Cray X-MP Series, 24, 22 Reference Manual

c:

RESEARCH

Any

shipment United States requires a U.S. Government export

license.

to a country

INC.

J

outside

of

the

CRAY COMPUTER SYSTEMS

CRAY X-MP SERIES

MODELS

MAINFRAME REFERENCE

HR-0032

parts thereof may

permission of CRAY

by

CRAY RESEARCH, INC. This manual

not

RESEARCH, INC.

22 & 24

MANUAL

be reproduced in any form without

RECORD OF REVISION

E

i

~ESEA~CHJ

INC.

PUBLICATION

NUMBER

HR-0032

Each time incorporated into against

Ol

Every corner. the one

Requests for copies

CRAY RESEARCH, 1440

Mendota Heights, Minnesota

thil

manuel il revised and reprinted, all

the

current

for

the

first change packet

P9

changed

Changes

page number indicates

page

to

another,

Northland Drive,

Revision

new version and

version in

by

to

part

but

of

INC.,

Description

a reprint

of 8 P8SlI

that

has

Crav Research, Inc. publications and comments

November, 1982 -

A

July, for

hardware

functions. Second functional

technical made.

chan~

the

form of ch.ange peckets. Each change packet

of

each revillon level. or

the

not

otherwise

55120

new version IS

by

a change packet has

are noted

entire page is new; a

bY

a change bar along

changed.

Original

1984 -

Reprint performance

Information

Vector

This

Logical

unit

and

editorial

revision

is

issued against

..

Igned an alphabetic level. Between reprints, changes may be issued

the

revision level

dot

the

in

ttle same place indicates

printing.

with

revision.

monitoring

was

also

functional

not

available

changes

obsoletes

the

previous version in

is

assigned 8 numeric designator, starting with

and

margin

about

change packet number in

of

the

page. A change bar in

these publications should

Instructions

and added unit on

and

all

to

is all correccions

form

of

change packets are

the

lower righthand

the

be

directed to:

margin opposite

that

information has been moved from

were added

SECDED

explain

used

systems.

maintenance

how

the

although

this

Numerous

were

also

printings.

BR-0032

ii

A

PREFACE

This dual-processor assist computers.

The equipment. Units hardware computer

Details Storage

publication

programmers

manual

HR-0030 HR-0630 HR-003l

describes

that

execute

exceptions,

systems.

of

the

Device

///////////////////////////////////////////////////////

This

frequency

accordance

interference tested A

computing FCC protection commercial a

residential which to the

describes

computer

and

It

also

describes

instructions,

I/O

Subsystem,

are

given

I/O

Subsystem

Mass

Rules,

take

interference.

Storage

Solid-state

equipment

energy

with

and

found which

against environment.

case

the

whatever

systems,

engineers

the

overall

and

provide

in

Storage

generates,

and

the

to

radio

to

device

are

area

user

measures

the

functions

models and

computer

the

operation

provide

interprocessor

the

disk

the

following

Hardware

Subsystem

Device

WARNING

uses,

if

not

instructions

communications.

comply

pursuant

designed

such

is

at

with

interference

Operation

likely

his

own

may

of

CRAY

22

and

assumes a familiarity

system,

of

memory

storage

publications:

Reference

Hardware

(SSO@)

and

installed

manual,

the

to

Subpart J of

to

provide

of

to

cause

expense

be

required

X-MP

Series

24.

the

units,

Manual

Reference

can

and

limits

when

this

It

its

configurations,

Central

protection,

communications

and

Reference

radiate

used

may

cause

It

has

for a Class

Part

reasonable

operated

equipment

interference

will

be

to

correct

is

been

written

with

Processing

report

the

Manual

radio

in

15

of in in

required

to

digital

and

within

Solid-state

a

in

the

HR-0032

///////////////////////////////////////////////////////

iii

A

CONTENTS,

PREFACE

1.

SYSTEM

INTRODUCTION

CONVENTIONS

SYSTEM

2.

CPU

SHARED

DESCRIPTION

•

Italics Register Number

Clock

• conventions

conventions

per

iod

COMPONENTS

Central

Processing

Interfaces

I/O

Subsystem

Disk

Solid-state

Condensing Power

storage

Storage

units

distribution

Motor-generator

CONFIGURATION

RESOURCES

•

units.

units

•

Units

Device

units

•

iii

1-1

1-1 1-4 1-4

1-4 1-4 1-4 1-5 1-5 1-7

1-9

1-11 1-12 1-13 1-14

1-15

1-16

2-1

INTRODUCTION CENTRAL

MEMORY Memory Memory

Memory

16-bank Memory

INTER-CPU

Real-time Inter-CPU

•

organization

addressing

Memory Memory

access

Conflict

addressing addressing

•

resolution Bank Busy Simultaneous Section

Memory

access

phasing

error

COMMUNICATION

clock

Access

priorities

•

correction

SECTION

•

communication

Shared

Semaphore

Address

registers

• for

for

conflict

Bank

conflict

•

and

Shared

HR-0032 v

6-co1umn

12-co1umn

conflict

•

control

Scalar

mainframe

• registers

2-1

2-2

2-3

•

2-3 2-4 2-4

2-7 2-7

2-7 2-7 2-7

2-8 2-8

2-10 2-10 2-11

•

2-12 2-12

A

2.

CPU

SHARED

CPU

INPUT/OUTPUT

Data Data

6 Mbyte

Multi-CPU programming • • • • • •

6 Mbyte

Input Input Output Programmed

Memory

I/O

Memory

I/O

I/O I/O

RESOURCES

transfer

per

per channel channel

channel

master

access

lockout

bank memory memory memory

conflicts

addressing

(continued)

SECTION

for for

second second

programming • • • • • • error

programming

• • • • •

• • • • • • • • • •

conflicts

• • • • • • • • • • • • • •

Solid-state

I/O

Subsystem

channels channel

conditions

clear

to

Storage

• • • • • •

• • • • •

operation

••••••

••••

external

. . . . . . .

• • •

. .

request

conditions

• • • • •

•

Device

~

••••

device

•

. . . . . .

. . . . .

. . . .

· . . . .

. . .

· . .

· . . . . .

· .

· . .

2-14 2-15

2-16 2-16

2-17 2-18 2-19 2-20 2-20 2-21 2-21 2-24 2-24 2-24 2-25 2-25

CPU

3.

CONTROL

INTRODUCTION INSTRUCTION

EXCHANGE

Active Exchange

Exchange Package management • •

SECTION

• • • • • • • • •

ISSUE Program Next Current Lower Instruction

Exchange

Address

Instruction

MECHANISM

Processor

vector Enable

Memory

Exchange

Mode

Flag Cluster Program

A

registers

S

registers

Program

Memory

Exchange Package • • • •

Exchange Exchange Exchange Exchange

AND

buffers

• • • • • • • • •

package

number

not

used

second error

registers

Address

register

Number State

Address

field

sequence

initiated initiated initiated

sequence

. . . . . . . . . . . . . . . . . . . . . .

· . . .

CONTROL

register

Parcel

(VNU)

vector

data

register

.,

.

logical

••••

. .

•

(ESVL)

· .

· . .

. . . .

. .

· . .

. .

register

••••••

•••••• register

register

••

• • •

••••• register

registers

• • • • • • •

by

deadstart

by

Interrupt

by

program

issue

. .

•

sequence flag

exit

conditions

· .

· . .

set

• •

· . .

. . . .

•

.

. .

3-1

3-1 3-1

3-2 3-2 3-2 3-3 3-3

3-5 3-5 3-7 3-7 3-8

3-8

3-9

3-9 3-11 3-12

3-12 3-12 3-12 3-13 3-13 3-13 3-13 3-14 3-14 3-14 3-15 3-15

HR-0032

vi

A

3.

CPU

CONTROL

SECTION

(continued)

MEMORY

Instruction

Data

Data Program

Operand

PROGRAMMABLE

Instructions Interrupt

Interrupt

Clear

PERFOBMANCE

DEADSTART

4.

CPU

COMPUTATION

INTRODUCTION

OPERATING

ADDRESS

A

B

SCALAR

S T

VECTOR

V Vector

FUNCTIONAL

Address

Scalar

Vector

FIELD

registers registers REGISTERS registers

registers REGISTERS

registers

PROTECTION

Base

Address

Limit

range range CLOCK

Interval Countdown

programmable

MONITOR

SEQUENCE

•

REGISTERS

V

register control

Vector

UNITS

functional Address Address

functional

Scalar Scalar Scalar Scalar

functional

Vector Vector Vector Full

Vector Second Vector

. . . . .

Base

Address

SECTION

Length

Mask

Add Shift

Logical Population/Parity/Leading

functional Add Shift

Vector

Population/parity

Address

Limit

•

• • • • • • Add

Multiply

Address register

register error error

•

• • • • •

registers

•

• •

register

counter

clock

reservations

register

units

functional

units

functional

unit

units

functional

Logical

register

•

interrupt

and

•

unit

functional

• unit

unit

•

unit

reservation

unit

functional

unit

functional

•

request

chaining

unit

•

• unit

• •

Zero

•

unit

3-16 3-17 3-17

.

•

3-18 3-18 3-18 3-19 3-19 3-19 3-19 3-20 3-20 3-20 3-21

4-1

4-3 4-3 4-3

4-5

4-6

4-8 4-9 4-9 4-12

4-13 4-13 4-13 4-14 4-14 4-15 4-15 4-15 4-15 4-16 4-16

4-16 4-16 4-17 4-17 4-17 4-18

4-18 4-19

HR-0032

vii

A

FONC'lIONAL

UNITS

(continued)

ARITHMETIC

LOGICAL

CPU

5.

INSTRUCTION

SPECIAL

INSTRUCTION INSTRUCTION

Floating-point

Reciprocal

OPERATIONS Integer Floating-point

OPERATIONS

INSTRUCTIONS

I-parcel

and k

I-parcel

and k

2-parcel

and m 2-parcel and m

REGISTER

arithmetic

Normalized Floating-point

Floating-point Floating-point Floating-point

functional Double-precision Addition Multiplication Division

Newton's

Derivation

FORMAT

instruction

fields

instruction

fields

instruction

fields

instruction

fields

ISSUE

DESCRIPTIONS

functional

Add Multiply

Approximation

• • • • • • • • • • • • • • • • •

•••••••••••

arithmetic

floating-point

range

algorithm

method

of

the

• • • • • • • • •

. . . .

••

• format

••

• • • • • • • • • • • • • • • • format

•••

• • • • • • • • • • • • • • • • •

VALUES

• • •

• • • • • • • • • • • format

format

• • • • • • • • •

• •

units

functional

• • • • • • • • • • •

errors Add Multiply

Reciprocal

unit

• • • • • • • • • • •

numbers • • • • • • • • • •

• • • • • • • • • • • • •

• • •

•••

division

• • • • unit

functional

numbers

functional

Approximation

• • • •

algorithm

••

unit

•••••

• • •

unit

. . . . . . . .

. . . .

with

discrete

with with with

combined j combined

combined

• • • •

• • • • •

•

unit

• •

. .

j

j,

k,

i,

j,

· . .

• • • • •

• • •

· .

· . .

· .

k,

. .

. . .

4-20 4-20 4-20

4-21

4-22

4-23

4-24 4-24 4-25

4-27 4-27 4-27 4-28 4-30

4-30

4-31 4-35

5-1 5-1

5-1 5-2 5-2 5-3

5-4

5-5

5-6

APPENDIX

A.

INSTRUCTION

B. 6

HR-0032

MBYTE

INTRODUCTION 6

MBYTE

SECTION

PER

Data

parity

bits

SUMMARY

SEOOND

• • • • • • • • • •

SEOOND

bits 0 through

FOR

CHANNEL

INPUT

20 through

CRAY

DESCRIPTIONS

CHANNEL

15

2

3 • • • • • • • • • • •

X-MP

MODELS

22

AND

. . . . .

SIGNAL

• • • • • • • • • •

viii

SEQUENCE.

24 • • • • • • •

. . . . . .

. . .

. . . .

. .

A-I

B-1

B-1 8-1

B-1

B-2

A

6

MBYTE

6

MBYTE

C.

PERFORMANCE

PER

SEOOND Ready Resume Disconnect

Data

Parity Ready Resume Disconnect

signal

PER

SECOND

bits

bits 0 through

signal

MONITOR

INPUT

signal

20 through

signal

• • • • • • • • • •

OUTPUT

• • • •

. . . . . . . . . . . . . . . . . . . . . .

CHANNEL

• • • • • • • • • • • • • • •

• • • • • • • • • • • • • • • • CHANNEL

15

2

3 •

• • • •

• • • • •

SIGNAL

••

SEQUENCE

• • • • • • • •

SEQUENCE

(continued)

. . .

. .

B-3 B-3

B-3 B-3 B-4

B-5 B-5 B-5 B-5

C-l

INTRODUCTION SELECTING READING TESTING

D.

SECDED

INTRODUCTION VERIFICATION VERIFICATION VERIFICATION CLEARING

FIGURES

1-1

1-2 1-3

1-4

1-5

1-6

1-7 1-8

1-9

1-10 1-11 1-12

1-13

2-1

2-2

2-3

2-4

CRAY

Cray Basic Control

CRAY

TYPical

I/O

DD-29

Solid-state

Condensing

Power

Motor-generator

Block with Block with

Central

6-column

12-co1umn memory

• • • • • • • • •

PERFORMANCE

PERFORMANCE PERFORMANCE

MAINTENANCE

• • • • • • • • • • • • •

OF

CHECK

OF

CHECK

OF

ERROR

MAINTENANCE

X-MP

Model 22

I/O

Subsystem

organization

and

data

X-MP

Models 22

interface

Subsystem

Disk

distribution diagram

full

diagram

block

Memory

memory memory

chassis

Storage

unit

of

disk

capacity

of

multiplexer

organization

EVENTS

RESULTS

COUNTERS •

FUNCTIONS

BIT

DETECTION

MODE

or

24

and

an

of

the

paths

cabinet

••••••••••

equipment

CRAY

address address

address

for a single

or

24

•••

Unit

Device

units

X-MP

X~

channels

. . . . . . . . . . .

. . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . .

STORAGE GENERATION

AND

FUNCTIONS

l2-column

SSD dual-processor

6-column

• • • • • • •

chassis

• • • • • • • • • dual-processor

••••••••• dual-processor

for a dual-processor

(32

banks)

(16

banks)

(32

banks)

•

CORRECTION

••••••

mainframe

•••••• CPU

mainframe

• • • •

• • • • • • • • • • • • • •

• • •

•••••

• •

• • • •

•••

•

with

• • • • • • • •

system

chassis

system

• • • • • • • • • •

system

• • • • • • •

a

system

. . .

• • • • •

. . .

C-1 C-l

C-3

D-l D-l

D-1 D-2 D-2 D-3

1-2

1-5

1-6

1-7 1-8 1-10 1-11 1-12 1-13 1-14

1-15

1-16

1-17

2-2

2-3

2-4

HR-0032

ix

A

FIGURES

(continued)

2-5

2-6

2-7

2-8

2-9

2-10 2-11

3-1 3-2 3-3 4-1

4-2

4-3 4-4

4-5 4-6 4-7

4-8

4-9

4-10 5-1 5-2 5-3

5-4

5-5

5-6

5-7

5-8

5-9

5-10

5-11

5-12

l2-column

Memory

Error Shared Basic Channel

memory

data

correction

registers

I/O

program

I/O

Input/output

Instruction

Instruction Exchange Address

Scalar

vector

Integer

package

registers registers registers

data

Floating-point

Exponent

Integer

functional

49-bit

matrix

multiply

unit

floating-point

Floating-point

Newton's

General

I-parcel I-parcel

k

fields

2-parcel

m

fields

2-parcel

combined

2-parcel

with

vector vector vector

vector

VL

greater

vector

method

form

instruction instruction

• • • • • • • • • • • • • • • • • • • • • • • • • • •

instruction

• • • • • • • • • • • • • • • • • • • • • • • • • instruction

i,

instruction

combined

left left left right

right

than

right

path

control

data issue buffers

formats

data

for

multiply

for

j,

k,

i,

double double double

double double

1

double

address with matrix and

flowchart

(shown paths and

(16

SECDED

real-time

for

••••••••

control

banks)

• • • • • • • • •

• • • • • • • • • clock

••••••••• one

elements

•••••••••••••

for a dual-processor

and and and

format

functional

• • • • •

• • • • • • • • • • • • • • • •

units units units

".

• • • •

Floating-point

in

Floating-point

••••

• • • • • • • • • • • •

addition

• • • • • • • • • •

partial-product

••••••••••••••••••••••• instructions

format

format format format

and m

fields

format

j,

k,

and m fields shift, shift, shift,

shift, shift,

••••••

shift,

first second last

••••••••••• with with

with

discrete combined j and

combined

for a branch

•••••••••

for a 24-bit

element,

element

first

second

element

element,

• • • • • •

last

operation

• • • • • • • • • • •

• • • • • • • • •

processor)

• • • • • • • • • • • •

system

•

••••

Multiply

unit

• • • • •

Multiply

sums

pyramid

j and k

j,

k, and

fields

with

immediate

constant

•••••••••••

VL

greater

VL

greater

than

• • • • • • • •

•

••••

• • • • • •

• •

. . .

• •

•

1 • •

than

2

2-4

2-8 2-9

2-11

2-19

2-22

2-23 3-1 3-3

3-6

4-4

4-7

4-10

4-22

4-23

4-25 4-27

4-28

4-29

4-31 5-1

5-2 5-2

5-3 5-4

5-4 5-71 5-71 5-71 5-72

5-73 5-73

TABLES

1-1

2-1 2-2

3-1

HR-0032

Access Channel

CRAY

x~p

dual-processor

conflicts

in a dual-processor

word

assembly/disassembly

Exchange

Package

system

to

shared computer

assignments

characteristics

registers

• • • •

x A

1-3

2-13

2-18 3-7

TABLES

(continued)

B-1 B-2

C-l

INDEX

Input

Output

channel

Performance

signal

counter

exchange

group

descriptions

• • • • • • • • • • •

• • • • • • • • • • • • • •

• • • • • •

B-2

B-4

C-2

HR-0032

xi

A

SYSTEM

INTRODUCTION

The

CRAY

X-MP/22 systems can scalar systems'

that

achieve

and

vector

random-access,

contain

extremely

DESCRIPTION

and

CRAY

X-MP/24

two

central

high

processing

solid-state

multiprocessing

capabilities

are

powerful,

processing

memory

units

rates

of

(RAM)

both

general

(CPUs). The

by

CPUs

and

purpose

efficiently

combined

shared

computer

systems

using

with

registers.

1

the

Vector ordered two greatly processing. providing techniques.

Equipment

(see 2 are matches rates devices,

In

Solid-state provides data

with a Cray

This

provides

processing

data.

or

more

exceeding

table

million

compatible

the

for

addition

files

section

solutions

options

communication

and a wide

significantly

overall

is

When

operations

the

Scalar

allow

1-1).

(model 22)

mainframe's

to Storage

repetitively.

I/O

describes

Central

with

the

mainframe

Subsystem

system

the

performance

two

or

more

can

be

computational

operations

to

problems

the

systems

Memory

or 4 million

all

existing processing

with

mass

variety

Device

system

of

and

can

improved

Figure

and

characteristics.

of

iterative

vector

executing

complement

not

of a dual-processor models

storage

host

I/O

be

configured

throughput

1-1

an

SSD®.

components

operations

each

rates readily

to

(model 24)

rates

computers.

Subsystem, a Cray

of the

be

configured

of

the

with

units,

of

illustrates

and

operations

are

chained

9.5-nanosecond conventional

vector

adaptable

64-bit

Cray

high

with

programs

configurations.

capability

to

for a particular

system words. I/O

input/output

other

the

peripheral

Research,

the

system.

that

mainframe

on

sets

together,

clock

scalar

by

vector

can

be

The

systems

Subsystem,

transfer

An

access

configured

Table

of

period,

use

either which

Inc.,

SSD

large

1-1

HR-0032

1-1

A

Figure

1-1.

CRAY

X-MP

Model 22

with a Cray

I/O

Subsystem

or

24

12-column

and

an

SSD

mainframe

HR-0032

1-2

A

Table

1-1.

CRAY

X~

dual-processor

system

characteristics

I

Configuration

CPU

speed

Memories - Mainframe

Input/Output

- Mainframe

-

I/O

Subsystem

-

Optional

-

9.5

ns

CPU

-

105

million

-

105

million

per

CPU

-

105

million

second

- 33 second

-

Simultaneous and

(model 24)

- One 1250 Mbyte (SSD)

-

Two I/O

-

Four

per

million

per

reciprocal

channel

100 Mbyte

Subsystem

6 Mbyte

with 2 Central

with

Solid-state

clock

floating-point

half-precision

CPU

full-precision

CPU

floating-point

has 2 million

64-bit

pair

per

2,

period

approximation

words

per

second

Processing

3,

or 4 I/O

Storage

floating-point

(model 22)

in

Solid-state

channel

Units

Processors

Device

additions multiplications

floating-point

addition,

within

Central

(SSD)

per

multiplication,

each

or 4 million

Memory

Storage

pairs

(CPUs)

second

per

divisions

CPU

for

interface

per

second

Device

CPU

per

to

I

Physical

HR-0032

-

64

sq

floor

-

15

sq

-

15

sq

-

5.25 6-column

-

1.5

-

1.5

-

Liquid

- 400

ft

floor space ft

floor ft

floor

tons,

mainframe

tons,

Hz

I/O

SSD refrigeration power from

space

for

6-column space space

l2-column

Subsystem weight

motor-generators

1-3

for

l2-column mainframe.

for

I/O

for

SSD

mainframe

weight.

weight

of

each

mainframe;

Subsystem

weight;

chassis

2.95

32

tons,

sq

ft

A

CONVENTIONS The

following

ITALICS

conventions

are

used

in

this

manual.

Italicized

REGISTER

CONVENTIONS

Parenthesized

of

shorthand

For

example,

contents

of

Designations For

example,

the T register

specified Register

2°.

Bit

by

bits

63

2

significant

most

significant conventions exceptions. and

are

not

most

significant register register. element

has

Bit

63.

lowercase

register

notation

"Branch

register

for "Transmit

the

letters,

names

for

to

(P)"

P." A, B,

(Tjk)

specified

the i designator."

are

numbered

of

an

S,

VL or T register

bit. for

Bits

numbered

64

Bit

bit.

the

Exchange

in

and

bits, 63

2

corresponds

2~3

(A

the as

powers

63

as

each

such

as

are

used

the

expression

means

S,

T,

to

by

the

right

of

an A or B register

"Branch

and V registers

sin

means

jk

designators

to

left

and B registers

Package

Exchange

Package

of 2 but

the

least

corresponding

to

element

jk,

indicate

frequently

"the

to

"Transmit

as

powers

value

represents

are

and

the

Vector

are

as

bits ° through

significant.

to

a word

0,

bit

variable

in

this

contents

the

address

are

used

the

to

the S register

of

value

24

bits.)

Mask

numbered

The element

2°

corresponds

information.

manual

of

register indicated

extensively.

contents

2,

starting

the

most

represents

The

numbering

register

from Vector

left

63

with ° as

Mask

in a vector

as

of

the

to

a form ___

by

with

are

right

.ft

the

NUMBER Unless

Octal

CONVENTIONS otherwise

numbers numbers, instruction

CLOCK The

PERIOD

basic referred and

other

HR-0032

are

channel

forms

unit

to

as a clock

timing

indicated,

indicated

numbers,

of

which

CPU

are

computation

period

considerations

numbers with

an 8 subscript.

instruction

given

in

time

(CP).

are

in

this

parcels

octal

is

Instruction

often

1-4

manual

in

instruction

without

9.5

nanoseconds

issue,

measured

are

decimal

Exceptions

the

subscript.

(ns)

memory

in

CPs.

numbers.

are

register

buffers,

and

is

references,

and

A

SYSTEM CDIPONEN'l'S

The

system devices, parts can

for

of a system.

be

refrigeration, distribution

components

CENTRAL PROCESSING UNITS

is

front-end

part

of

are

composed

interfaces,

the

system.

motor-generators

units

for

described

Optionally,

of

a mainframe and an

and

optional

a Cray

Supporting

to

the

mainframe,

on

the

following

I/O

tape

Solid-state

this

equipment

provide

I/O

Subsystem, pages.

Subsystem.

devices

Storage

are

system

power, and power

and

Mass

are

also

Device

condensing

the

SSD.

storage integral

(SSD)

units

System

Each share

the

(CPO

CPU

has

Central

sections

basic

organization components and Figure

CONTROL

•

1-4

SECTION

Instruction buffers

Control registers

Exchange mechanism

Interrupt Programmable

clock Status

register

shows mainframe

-

independent

Memory

are

and

described

of

control

COMPUTATION

•

and

SECTION Registers Functional

units

control the

the

data

and

computation

inter-CPO communication and

in

later

computer,

paths

sections.)

figure

of a single

chassis.

CPU

COMMUNICATION

SECTION

Shared

2

million

•

Semaphore

•

registers Real-time

•

register

MEMORY

64-bit

registers

SECTION

or 4 million

words

-

Clock

,

sections.

Figure

1-3

illustrates

CPU

COMPUTATION

SECTION

Registers

•

Functional

•

units

in

I/O

1-2

the

Both

CPOs

sections.

illustrates

the

system.

CONTROL

Instruction

•

buffers

Control

•

registers

Exchange

•

mechanism

Interrupt

•

Programmable

•

clock

Status

•

register

SECTION

I

HR-0032

Four

•

6 Mbyte

One 1250 Mbyte

Two

100 Mbyte

Figure

1-2.

I/O

SECTION

per

second

Basic

channel

organization

per

dual-processor

1-5

pairs

pair

pairs

of

system

the

A

77

liD

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jSj

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t

lSi

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lSi

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Ai

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c::..(.;'ooo----

lOa

Control

-I

___

ReaI-Ti.eClod

0--

I

0'-

I

and

A-'-i

____

SM

ST

S8

data

--

Sjl

I"

Sil

s;!

Ail

paths

......

----1

*The

Vector

input

path with

Approximation

The

Second Vector

its

input

Floating-point

Issue

tSi

Si

t

Si

t

tAi

for a single

Functional Units

Pop/Parity

unit.

and

output

Multiply

the

logical

shares

Reciprocal

s"ares

path

with

unit.

its

the

CPU

t

Second

HR-0032

Vector

Logical

unit

not

available

1-6

on

all

machines.

A

Figure

INTERFACES

The

Cray

computer

executes

1-4.

mainframe network. under

the

CRAY

is

A

front-end

control

X~P

Model

designed

of

22

or

for

use

computer

its

own

24 6-column

with

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system

operating

mainframe

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self

system.

chassis

computers

contained

in

and

a

Standard

of

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output

from compensate electrical

of

the

I/O

through

the

a 6 Mbyte

Cray

interface,

computer

HR-0032

interfaces

computers,

it

for

differences

logic

levels,

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per

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to

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widths,

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channels

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to

receiving

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word Master computer

size,

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system

adapter

Processor

module

through a front-end

channels

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The

front-end

located

front-end A

primary

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to

the

interface,

of

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near

the

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goal

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the

front-end

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host

user

of

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to

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faster

burst

channel.

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computer.

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interface

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Cray

than

rate

of

the

system.

the

in a stand-alone

Its

operation

Cray

is

user.

to

maximize

Since

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cabinet

invisible

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(figure

the

to

both

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connected

to

maximum

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rate

Interfaces

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As a master

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As a local

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As a local

•

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into a Single

•

As a remote

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Peripheral on

the

use

to

the

Cray

an

interactive

equipment

of

front-end

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operator operator batch

concentrator

Cray

batch

attached

the

Cray

computers

in

the

station

entry

station

for

channel

entry

station

communication

to

the

system.

allow following

the

ways:

multiplexing

station

front-end

several

computer

computers

other

stations

varies

to

depending

HR-0032

Figure

1-5.

Typical

1-8

interface

cabinet

A

I/O

SUBSYSTEM

The

I/O

X-MP

Computer

a

Buffer

transfer

devices,

Memory

Subsystem,

Systems Memory, between and

the

and

the

shown

and front-end

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Central

in

figure

and

has

two,

required

computers,

Subsystem's

Memory

of a Cray

1-6, three,

interfaces.

peripheral

Buffer

is

standard

or

four

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is

Memory

or

mainframe.

on

all

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Processors designed devices,

between

models

for

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of

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data

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Master

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one

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computation

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types

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lOP (XIOP).

BIOP. The number

lOP

of

section,

independent

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The standard

interfaces

of

the mainframe with

the

entire

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group

the

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over

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transferred

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100

through a 100

Disk

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processor

storage port Mbyte

to

per

connect

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the

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and

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a 6 Mbyte

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and

through

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units.

second

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of

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to

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input/output

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portion

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controls

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to

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connects

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(COS)

storage

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per

second

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to

four

uses

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used

to

channel

to

the

devices.

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disk

one

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pair

to

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section,

section.

of

the

memory

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coordinate

main

channel

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controller

DMA

port

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have

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dependent.

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access

front-end Peripheral

memory

Memory

pair.

link

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to

the

pair.

for

DMA

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Subsystem:

and

at

least

a

control

Input/output

requirements

ports

interfaces

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access

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to

The

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communicates

the

activities

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from

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mainframe's

disk units

each

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with

controller,

port

to Memory.

a

an

one

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and

section,

sections

for

the

to

its

local

and

(DMA)

port

the

of

the

mainframe's storage

is

Central

units.

up

to

16

one

connect

a

the

Auxiliary

The

and

interfaces

Each

controller

XIOP

uses

connect

t The

link

HR-0032

one

with

term

to

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to a maximum

can

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Buffer

station

the

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handle

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for

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means

end

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of up each

both

can

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four

to

four

controller

hardware

act

1-9

used

BMC-4

block

for

Block

multiplexer

and

software.

as a limited

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another

front

Controllers.

channels.

DMA

port

Station end

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channels

The

to

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the

MIOP).

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Subsystem

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and

Memory.t

The

CPU

input/output

in

section

Manual,

CRI

Subsystem.

hardware

DIOP

2

or

of

publication

XIOP

this

allows

of

the

section

manual.

HR-0030,

for

simultaneous

I/O

Subsystem

for

Cray

Refer

to

for a complete

data

and

the

dual-processor

the

I/O

Subsystem

description

transfers

mainframe's

systems

Reference

of

between

Central

is

described

the

I/O

t

Software XIOP

HR-0032

is

currently

to

Figure

support

the

not

1-6.

100

Mbyte

available.

I/O

Subsystem

1-10

per

second

chassis

channel

pair

to

the

A

DISK

For

STORAGE

mass

(DSUs). A with access single

The the

missing DSUs

DD-29

an

DCU.

I/O

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can

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(DNA)

Processor

port

data

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storage,

disk

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port.

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configured

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chassis.

the

system

controller

of

Up

to

and

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four

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on

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an

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Figure

unit

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of 2 and a maximum

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unit

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48

Each

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controller. Dynamic

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Manual,

CRI

has

two

data

sharing

software.

is

included

HR-0030,

publication

accesses

path

to

Reservation

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Further

in

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for

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each

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devices

the

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through

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the

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storage

CRI Reference

second

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to

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HR-0032

Figure

1-7.

DD-29

1-11

Disk

Storage

Unit

A

SOLID-STATE The

Solid-state

high-performance data

I

Cray The

actual

and

system

(SSD)

between interface

speed

configuration

Reference

STORAGE

Storage

device

the

mainframe's

cable

of

Manual,

DEVICE

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at a maximum

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transfers

as

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for

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shown

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speed

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in

the

HR-003l.

in

figure

data

storage.

and

the

of

1250 Mbytes

on

Solid-state

1-8

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an

It

transfers

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through a special

per

the

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memory

Storage

optional,

second.

size

Device

HR-0032

Figure

1-8.

Solid-state

Storage

1-12

Device

chassis

A

CONDENSING

UNITS

Condensing

refrigeration

25-ton level which

condensers.

cooling

cools

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units

the

unit.

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system system

computer,

used

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that

1-9)

to

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of

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and

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of

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water

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the

HR-0032

Figure

1-9.

Condensing

1-13

unit

A

I

POWER

The 3-phase

power contains column temperature strategic shutdown excessive

condensing

unit.

A Subsystem

DISTRIBUTION

Cray

power.

distribution

of

circuitry

smaller

mainframe,

The

adjustable

the

mainframe.

and

voltage

locations

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unit

power

chassis

are

distribution

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mainframe,

units.

transformers

monitoring

on

the

protects

control

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for

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the

mainframe

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on

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all

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in

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the

at

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Figure

and

for

1-10

the

shows

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Subsystem

the

power

or

distribution

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(right).

units

for

the

mainframe

(left)

HR-0032

Figure

1-10.

Power

1-14

distribution

units

A

MOTOR-GENERATOR

UNITS

Motor-generator

mains

system

The control control

to

the

from

equipment

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transients

units

400

Hz

consists

convert

power

Figure

used

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of

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1-11

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by

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on

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motor-generator

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from

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These

the

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motor-generator

commercial units

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and

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a

its

HR-0032

Figure

1-11.

Motor-generator

1-15

equipment

A

SYSTEM

CONFIGURATION

Figures

of

the

1-12

CRAY

and

x~p

1-13

illustrate

Computer

MIOP

SlOP

DIOP

System.

two

configurations

FRONT-END

COMPUTERS

FRONT-END

INTERFACES

for

models

CRAY

X·

MP

2

OR 4 MILLION

64·BIT

22

or

MAINFRAME

WORDS

24

SSD

_Cray

• Cray 100 Mbyte channel

• Cray 1250 Mbyte channel

6 Mbyte channel

Figure

1-12.

DIOP

Block

with

diagram

full

disk

of

CRAY

capacity

X-MP

dual-processor

system

HR-0032

1-16

A

MIOP

BIOP

DIOP

XIOP

1

TO

BLOCK

MULTIPLEXER

CONTROLLERS

FRONT-END COMPUTERS

FRONT-END

INTERFACES

CRAY

X -

MP

MAINFRAME

2

OR 4 MILLION

64-BIT

WORDS

2

- - -1

TO 8 CHANNELS

SSD

_Cray

• Cray 100 Mbyte channel .Cray

6 Mbyte channel

1250 t4byte channel

Figure

I

HR-0032

1-13.

Block with

diagram

block

of

CRAY

multiplexer

1-17

X-MP

dual-processor

channels

system

A

Cray X-MP Series, 24, 22 Reference Manual

Specifications and Main Features

Frequently Asked Questions

User Manual