Cray X-MP Series, 24, 22 Reference Manual

c:

RESEARCH

Any

shipment United States requires a U.S. Government export

license.

to a country

INC.

J

outside

of

the

CRAY COMPUTER SYSTEMS

CRAY X-MP SERIES

MODELS

MAINFRAME REFERENCE

HR-0032

parts thereof may

permission of CRAY

by

CRAY RESEARCH, INC. This manual

not

RESEARCH, INC.

22 & 24

MANUAL

be reproduced in any form without

RECORD OF REVISION

E

i

~ESEA~CHJ

INC.

PUBLICATION

NUMBER

HR-0032

Each time incorporated into against

Ol

Every corner. the one

Requests for copies

CRAY RESEARCH, 1440

Mendota Heights, Minnesota

thil

manuel il revised and reprinted, all

the

current

for

the

first change packet

P9

changed

Changes

page number indicates

page

to

another,

Northland Drive,

Revision

new version and

version in

by

to

part

but

of

INC.,

Description

a reprint

of 8 P8SlI

that

has

Crav Research, Inc. publications and comments

November, 1982 -

A

July, for

hardware

functions. Second functional

technical made.

chan~

the

form of ch.ange peckets. Each change packet

of

each revillon level. or

the

not

otherwise

55120

new version IS

by

a change packet has

are noted

entire page is new; a

bY

a change bar along

changed.

Original

1984 -

Reprint performance

Information

Vector

This

Logical

unit

and

editorial

revision

is

issued against

..

Igned an alphabetic level. Between reprints, changes may be issued

the

revision level

dot

the

in

ttle same place indicates

printing.

with

revision.

monitoring

was

also

functional

not

available

changes

obsoletes

the

previous version in

is

assigned 8 numeric designator, starting with

and

margin

about

change packet number in

of

the

page. A change bar in

these publications should

Instructions

and added unit on

and

all

to

is all correccions

form

of

change packets are

the

lower righthand

the

be

directed to:

margin opposite

that

information has been moved from

were added

SECDED

explain

used

systems.

maintenance

how

the

although

this

Numerous

were

also

printings.

BR-0032

ii

A

PREFACE

This dual-processor assist computers.

The equipment. Units hardware computer

Details Storage

publication

programmers

manual

HR-0030 HR-0630 HR-003l

describes

that

execute

exceptions,

systems.

of

the

Device

///////////////////////////////////////////////////////

This

frequency

accordance

interference tested A

computing FCC protection commercial a

residential which to the

describes

computer

and

It

also

describes

instructions,

I/O

Subsystem,

are

given

I/O

Subsystem

Mass

Rules,

take

interference.

Storage

Solid-state

equipment

energy

with

and

found which

against environment.

case

the

whatever

systems,

engineers

the

overall

and

provide

in

Storage

generates,

and

the

to

radio

to

device

are

area

user

measures

the

functions

models and

computer

the

operation

provide

interprocessor

the

disk

the

following

Hardware

Subsystem

Device

WARNING

uses,

if

not

instructions

communications.

comply

pursuant

designed

such

is

at

with

interference

Operation

likely

his

own

may

of

CRAY

22

and

assumes a familiarity

system,

of

memory

storage

publications:

Reference

Hardware

(SSO@)

and

installed

manual,

the

to

Subpart J of

to

provide

of

to

cause

expense

be

required

X-MP

Series

24.

the

units,

Manual

Reference

can

and

limits

when

this

It

its

configurations,

Central

protection,

communications

and

Reference

radiate

used

may

cause

It

has

for a Class

Part

reasonable

operated

equipment

interference

will

be

to

correct

is

been

written

with

Processing

report

the

Manual

radio

in

15

of in in

required

to

digital

and

within

Solid-state

a

in

the

HR-0032

///////////////////////////////////////////////////////

iii

A

CONTENTS,

PREFACE

1.

SYSTEM

INTRODUCTION

CONVENTIONS

SYSTEM

2.

CPU

SHARED

DESCRIPTION

•

Italics Register Number

Clock

• conventions

conventions

per

iod

COMPONENTS

Central

Processing

Interfaces

I/O

Subsystem

Disk

Solid-state

Condensing Power

storage

Storage

units

distribution

Motor-generator

CONFIGURATION

RESOURCES

•

units.

units

•

Units

Device

units

•

iii

1-1

1-1 1-4 1-4

1-4 1-4 1-4 1-5 1-5 1-7

1-9

1-11 1-12 1-13 1-14

1-15

1-16

2-1

INTRODUCTION CENTRAL

MEMORY Memory Memory

Memory

16-bank Memory

INTER-CPU

Real-time Inter-CPU

•

organization

addressing

Memory Memory

access

Conflict

addressing addressing

•

resolution Bank Busy Simultaneous Section

Memory

access

phasing

error

COMMUNICATION

clock

Access

priorities

•

correction

SECTION

•

communication

Shared

Semaphore

Address

registers

• for

for

conflict

Bank

conflict

•

and

Shared

HR-0032 v

6-co1umn

12-co1umn

conflict

•

control

Scalar

mainframe

• registers

2-1

2-2

2-3

•

2-3 2-4 2-4

2-7 2-7

2-7 2-7 2-7

2-8 2-8

2-10 2-10 2-11

•

2-12 2-12

A

2.

CPU

SHARED

CPU

INPUT/OUTPUT

Data Data

6 Mbyte

Multi-CPU programming • • • • • •

6 Mbyte

Input Input Output Programmed

Memory

I/O

Memory

I/O

I/O I/O

RESOURCES

transfer

per

per channel channel

channel

master

access

lockout

bank memory memory memory

conflicts

addressing

(continued)

SECTION

for for

second second

programming • • • • • • error

programming

• • • • •

• • • • • • • • • •

conflicts

• • • • • • • • • • • • • •

Solid-state

I/O

Subsystem

channels channel

conditions

clear

to

Storage

• • • • • •

• • • • •

operation

••••••

••••

external

. . . . . . .

• • •

. .

request

conditions

• • • • •

•

Device

~

••••

device

•

. . . . . .

. . . . .

. . . .

· . . . .

. . .

· . .

· . . . . .

· .

· . .

2-14 2-15

2-16 2-16

2-17 2-18 2-19 2-20 2-20 2-21 2-21 2-24 2-24 2-24 2-25 2-25

CPU

3.

CONTROL

INTRODUCTION INSTRUCTION

EXCHANGE

Active Exchange

Exchange Package management • •

SECTION

• • • • • • • • •

ISSUE Program Next Current Lower Instruction

Exchange

Address

Instruction

MECHANISM

Processor

vector Enable

Memory

Exchange

Mode

Flag Cluster Program

A

registers

S

registers

Program

Memory

Exchange Package • • • •

Exchange Exchange Exchange Exchange

AND

buffers

• • • • • • • • •

package

number

not

used

second error

registers

Address

register

Number State

Address

field

sequence

initiated initiated initiated

sequence

. . . . . . . . . . . . . . . . . . . . . .

· . . .

CONTROL

register

Parcel

(VNU)

vector

data

register

.,

.

logical

••••

. .

•

(ESVL)

· .

· . .

. . . .

. .

· . .

. .

register

••••••

•••••• register

register

••

• • •

••••• register

registers

• • • • • • •

by

deadstart

by

Interrupt

by

program

issue

. .

•

sequence flag

exit

conditions

· .

· . .

set

• •

· . .

. . . .

•

.

. .

3-1

3-1 3-1

3-2 3-2 3-2 3-3 3-3

3-5 3-5 3-7 3-7 3-8

3-8

3-9

3-9 3-11 3-12

3-12 3-12 3-12 3-13 3-13 3-13 3-13 3-14 3-14 3-14 3-15 3-15

HR-0032

vi

A

3.

CPU

CONTROL

SECTION

(continued)

MEMORY

Instruction

Data

Data Program

Operand

PROGRAMMABLE

Instructions Interrupt

Interrupt

Clear

PERFOBMANCE

DEADSTART

4.

CPU

COMPUTATION

INTRODUCTION

OPERATING

ADDRESS

A

B

SCALAR

S T

VECTOR

V Vector

FUNCTIONAL

Address

Scalar

Vector

FIELD

registers registers REGISTERS registers

registers REGISTERS

registers

PROTECTION

Base

Address

Limit

range range CLOCK

Interval Countdown

programmable

MONITOR

SEQUENCE

•

REGISTERS

V

register control

Vector

UNITS

functional Address Address

functional

Scalar Scalar Scalar Scalar

functional

Vector Vector Vector Full

Vector Second Vector

. . . . .

Base

Address

SECTION

Length

Mask

Add Shift

Logical Population/Parity/Leading

functional Add Shift

Vector

Population/parity

Address

Limit

•

• • • • • • Add

Multiply

Address register

register error error

•

• • • • •

registers

•

• •

register

counter

clock

reservations

register

units

functional

units

functional

unit

units

functional

Logical

register

•

interrupt

and

•

unit

functional

• unit

unit

•

unit

reservation

unit

functional

unit

functional

•

request

chaining

unit

•

• unit

• •

Zero

•

unit

3-16 3-17 3-17

.

•

3-18 3-18 3-18 3-19 3-19 3-19 3-19 3-20 3-20 3-20 3-21

4-1

4-3 4-3 4-3

4-5

4-6

4-8 4-9 4-9 4-12

4-13 4-13 4-13 4-14 4-14 4-15 4-15 4-15 4-15 4-16 4-16

4-16 4-16 4-17 4-17 4-17 4-18

4-18 4-19

HR-0032

vii

A

FONC'lIONAL

UNITS

(continued)

ARITHMETIC

LOGICAL

CPU

5.

INSTRUCTION

SPECIAL

INSTRUCTION INSTRUCTION

Floating-point

Reciprocal

OPERATIONS Integer Floating-point

OPERATIONS

INSTRUCTIONS

I-parcel

and k

I-parcel

and k

2-parcel

and m 2-parcel and m

REGISTER

arithmetic

Normalized Floating-point

Floating-point Floating-point Floating-point

functional Double-precision Addition Multiplication Division

Newton's

Derivation

FORMAT

instruction

fields

instruction

fields

instruction

fields

instruction

fields

ISSUE

DESCRIPTIONS

functional

Add Multiply

Approximation

• • • • • • • • • • • • • • • • •

•••••••••••

arithmetic

floating-point

range

algorithm

method

of

the

• • • • • • • • •

. . . .

••

• format

••

• • • • • • • • • • • • • • • • format

•••

• • • • • • • • • • • • • • • • •

VALUES

• • •

• • • • • • • • • • • format

format

• • • • • • • • •

• •

units

functional

• • • • • • • • • • •

errors Add Multiply

Reciprocal

unit

• • • • • • • • • • •

numbers • • • • • • • • • •

• • • • • • • • • • • • •

• • •

•••

division

• • • • unit

functional

numbers

functional

Approximation

• • • •

algorithm

••

unit

•••••

• • •

unit

. . . . . . . .

. . . .

with

discrete

with with with

combined j combined

combined

• • • •

• • • • •

•

unit

• •

. .

j

j,

k,

i,

j,

· . .

• • • • •

• • •

· .

· . .

· .

k,

. .

. . .

4-20 4-20 4-20

4-21

4-22

4-23

4-24 4-24 4-25

4-27 4-27 4-27 4-28 4-30

4-30

4-31 4-35

5-1 5-1

5-1 5-2 5-2 5-3

5-4

5-5

5-6

APPENDIX

A.

INSTRUCTION

B. 6

HR-0032

MBYTE

INTRODUCTION 6

MBYTE

SECTION

PER

Data

parity

bits

SUMMARY

SEOOND

• • • • • • • • • •

SEOOND

bits 0 through

FOR

CHANNEL

INPUT

20 through

CRAY

DESCRIPTIONS

CHANNEL

15

2

3 • • • • • • • • • • •

X-MP

MODELS

22

AND

. . . . .

SIGNAL

• • • • • • • • • •

viii

SEQUENCE.

24 • • • • • • •

. . . . . .

. . .

. . . .

. .

A-I

B-1

B-1 8-1

B-1

B-2

A

6

MBYTE

6

MBYTE

C.

PERFORMANCE

PER

SEOOND Ready Resume Disconnect

Data

Parity Ready Resume Disconnect

signal

PER

SECOND

bits

bits 0 through

signal

MONITOR

INPUT

signal

20 through

signal

• • • • • • • • • •

OUTPUT

• • • •

. . . . . . . . . . . . . . . . . . . . . .

CHANNEL

• • • • • • • • • • • • • • •

• • • • • • • • • • • • • • • • CHANNEL

15

2

3 •

• • • •

• • • • •

SIGNAL

••

SEQUENCE

• • • • • • • •

SEQUENCE

(continued)

. . .

. .

B-3 B-3

B-3 B-3 B-4

B-5 B-5 B-5 B-5

C-l

INTRODUCTION SELECTING READING TESTING

D.

SECDED

INTRODUCTION VERIFICATION VERIFICATION VERIFICATION CLEARING

FIGURES

1-1

1-2 1-3

1-4

1-5

1-6

1-7 1-8

1-9

1-10 1-11 1-12

1-13

2-1

2-2

2-3

2-4

CRAY

Cray Basic Control

CRAY

TYPical

I/O

DD-29

Solid-state

Condensing

Power

Motor-generator

Block with Block with

Central

6-column

12-co1umn memory

• • • • • • • • •

PERFORMANCE

PERFORMANCE PERFORMANCE

MAINTENANCE

• • • • • • • • • • • • •

OF

CHECK

OF

CHECK

OF

ERROR

MAINTENANCE

X-MP

Model 22

I/O

Subsystem

organization

and

data

X-MP

Models 22

interface

Subsystem

Disk

distribution diagram

full

diagram

block

Memory

memory memory

chassis

Storage

unit

of

disk

capacity

of

multiplexer

organization

EVENTS

RESULTS

COUNTERS •

FUNCTIONS

BIT

DETECTION

MODE

or

24

and

an

of

the

paths

cabinet

••••••••••

equipment

CRAY

address address

address

for a single

or

24

•••

Unit

Device

units

X-MP

X~

channels

. . . . . . . . . . .

. . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . .

STORAGE GENERATION

AND

FUNCTIONS

l2-column

SSD dual-processor

6-column

• • • • • • •

chassis

• • • • • • • • • dual-processor

••••••••• dual-processor

for a dual-processor

(32

banks)

(16

banks)

(32

banks)

•

CORRECTION

••••••

mainframe

•••••• CPU

mainframe

• • • •

• • • • • • • • • • • • • •

• • •

•••••

• •

• • • •

•••

•

with

• • • • • • • •

system

chassis

system

• • • • • • • • • •

system

• • • • • • •

a

system

. . .

• • • • •

. . .

C-1 C-l

C-3

D-l D-l

D-1 D-2 D-2 D-3

1-2

1-5

1-6

1-7 1-8 1-10 1-11 1-12 1-13 1-14

1-15

1-16

1-17

2-2

2-3

2-4

HR-0032

ix

A

FIGURES

(continued)

2-5

2-6

2-7

2-8

2-9

2-10 2-11

3-1 3-2 3-3 4-1

4-2

4-3 4-4

4-5 4-6 4-7

4-8

4-9

4-10 5-1 5-2 5-3

5-4

5-5

5-6

5-7

5-8

5-9

5-10

5-11

5-12

l2-column

Memory

Error Shared Basic Channel

memory

data

correction

registers

I/O

program

I/O

Input/output

Instruction

Instruction Exchange Address

Scalar

vector

Integer

package

registers registers registers

data

Floating-point

Exponent

Integer

functional

49-bit

matrix

multiply

unit

floating-point

Floating-point

Newton's

General

I-parcel I-parcel

k

fields

2-parcel

m

fields

2-parcel

combined

2-parcel

with

vector vector vector

vector

VL

greater

vector

method

form

instruction instruction

• • • • • • • • • • • • • • • • • • • • • • • • • • •

instruction

• • • • • • • • • • • • • • • • • • • • • • • • • instruction

i,

instruction

combined

left left left right

right

than

right

path

control

data issue buffers

formats

data

for

multiply

for

j,

k,

i,

double double double

double double

1

double

address with matrix and

flowchart

(shown paths and

(16

SECDED

real-time

for

••••••••

control

banks)

• • • • • • • • •

• • • • • • • • • clock

••••••••• one

elements

•••••••••••••

for a dual-processor

and and and

format

functional

• • • • •

• • • • • • • • • • • • • • • •

units units units

".

• • • •

Floating-point

in

Floating-point

••••

• • • • • • • • • • • •

addition

• • • • • • • • • •

partial-product

••••••••••••••••••••••• instructions

format

format format format

and m

fields

format

j,

k,

and m fields shift, shift, shift,

shift, shift,

••••••

shift,

first second last

••••••••••• with with

with

discrete combined j and

combined

for a branch

•••••••••

for a 24-bit

element,

element

first

second

element

element,

• • • • • •

last

operation

• • • • • • • • • • •

• • • • • • • • •

processor)

• • • • • • • • • • • •

system

•

••••

Multiply

unit

• • • • •

Multiply

sums

pyramid

j and k

j,

k, and

fields

with

immediate

constant

•••••••••••

VL

greater

VL

greater

than

• • • • • • • •

•

••••

• • • • • •

• •

. . .

• •

•

1 • •

than

2

2-4

2-8 2-9

2-11

2-19

2-22

2-23 3-1 3-3

3-6

4-4

4-7

4-10

4-22

4-23

4-25 4-27

4-28

4-29

4-31 5-1

5-2 5-2

5-3 5-4

5-4 5-71 5-71 5-71 5-72

5-73 5-73

TABLES

1-1

2-1 2-2

3-1

HR-0032

Access Channel

CRAY

x~p

dual-processor

conflicts

in a dual-processor

word

assembly/disassembly

Exchange

Package

system

to

shared computer

assignments

characteristics

registers

• • • •

x A

1-3

2-13

2-18 3-7

TABLES

(continued)

B-1 B-2

C-l

INDEX

Input

Output

channel

Performance

signal

counter

exchange

group

descriptions

• • • • • • • • • • •

• • • • • • • • • • • • • •

• • • • • •

B-2

B-4

C-2

HR-0032

xi

A

SYSTEM

INTRODUCTION

The

CRAY

X-MP/22 systems can scalar systems'

that

achieve

and

vector

random-access,

contain

extremely

DESCRIPTION

and

CRAY

X-MP/24

two

central

high

processing

solid-state

multiprocessing

capabilities

are

powerful,

processing

memory

units

rates

of

(RAM)

both

general

(CPUs). The

by

CPUs

and

purpose

efficiently

combined

shared

computer

systems

using

with

registers.

1

the

Vector ordered two greatly processing. providing techniques.

Equipment

(see 2 are matches rates devices,

In

Solid-state provides data

with a Cray

This

provides

processing

data.

or

more

exceeding

table

million

compatible

the

for

addition

files

section

solutions

options

communication

and a wide

significantly

overall

is

When

operations

the

Scalar

allow

1-1).

(model 22)

mainframe's

to Storage

repetitively.

I/O

describes

Central

with

the

mainframe

Subsystem

system

the

performance

two

or

more

can

be

computational

operations

to

problems

the

systems

Memory

or 4 million

all

existing processing

with

mass

variety

Device

system

of

and

can

improved

Figure

and

characteristics.

of

iterative

vector

executing

complement

not

of a dual-processor models

storage

host

I/O

be

configured

throughput

1-1

an

SSD®.

components

operations

each

rates readily

to

(model 24)

rates

computers.

Subsystem, a Cray

of the

be

configured

of

the

with

units,

of

illustrates

and

operations

are

chained

9.5-nanosecond conventional

vector

adaptable

64-bit

Cray

high

with

programs

configurations.

capability

to

for a particular

system words. I/O

input/output

other

the

peripheral

Research,

the

system.

that

mainframe

on

sets

together,

clock

scalar

by

vector

can

be

The

systems

Subsystem,

transfer

An

access

configured

Table

of

period,

use

either which

Inc.,

SSD

large

1-1

HR-0032

1-1

A

Figure

1-1.

CRAY

X-MP

Model 22

with a Cray

I/O

Subsystem

or

24

12-column

and

an

SSD

mainframe

HR-0032

1-2

A

Table

1-1.

CRAY

X~

dual-processor

system

characteristics

I

Configuration

CPU

speed

Memories - Mainframe

Input/Output

- Mainframe

-

I/O

Subsystem

-

Optional

-

9.5

ns

CPU

-

105

million

-

105

million

per

CPU

-

105

million

second

- 33 second

-

Simultaneous and

(model 24)

- One 1250 Mbyte (SSD)

-

Two I/O

-

Four

per

million

per

reciprocal

channel

100 Mbyte

Subsystem

6 Mbyte

with 2 Central

with

Solid-state

clock

floating-point

half-precision

CPU

full-precision

CPU

floating-point

has 2 million

64-bit

pair

per

2,

period

approximation

words

per

second

Processing

3,

or 4 I/O

Storage

floating-point

(model 22)

in

Solid-state

channel

Units

Processors

Device

additions multiplications

floating-point

addition,

within

Central

(SSD)

per

multiplication,

each

or 4 million

Memory

Storage

pairs

(CPUs)

second

per

divisions

CPU

for

interface

per

second

Device

CPU

per

to

I

Physical

HR-0032

-

64

sq

floor

-

15

sq

-

15

sq

-

5.25 6-column

-

1.5

-

1.5

-

Liquid

- 400

ft

floor space ft

floor ft

floor

tons,

mainframe

tons,

Hz

I/O

SSD refrigeration power from

space

for

6-column space space

l2-column

Subsystem weight

motor-generators

1-3

for

l2-column mainframe.

for

I/O

for

SSD

mainframe

weight.

weight

of

each

mainframe;

Subsystem

weight;

chassis

2.95

32

tons,

sq

ft

A

CONVENTIONS The

following

ITALICS

conventions

are

used

in

this

manual.

Italicized

REGISTER

CONVENTIONS

Parenthesized

of

shorthand

For

example,

contents

of

Designations For

example,

the T register

specified Register

2°.

Bit

by

bits

63

2

significant

most

significant conventions exceptions. and

are

not

most

significant register register. element

has

Bit

63.

lowercase

register

notation

"Branch

register

for "Transmit

the

letters,

names

for

to

(P)"

P." A, B,

(Tjk)

specified

the i designator."

are

numbered

of

an

S,

VL or T register

bit. for

Bits

numbered

64

Bit

bit.

the

Exchange

in

and

bits, 63

2

corresponds

2~3

(A

the as

powers

63

as

each

such

as

are

used

the

expression

means

S,

T,

to

by

the

right

of

an A or B register

"Branch

and V registers

sin

means

jk

designators

to

left

and B registers

Package

Exchange

Package

of 2 but

the

least

corresponding

to

element

jk,

indicate

frequently

"the

to

"Transmit

as

powers

value

represents

are

and

the

Vector

are

as

bits ° through

significant.

to

a word

0,

bit

variable

in

this

contents

the

address

are

used

the

to

the S register

of

value

24

bits.)

Mask

numbered

The element

2°

corresponds

information.

manual

of

register indicated

extensively.

contents

2,

starting

the

most

represents

The

numbering

register

from Vector

left

63

with ° as

Mask

in a vector

as

of

the

to

a form ___

by

with

are

right

.ft

the

NUMBER Unless

Octal

CONVENTIONS otherwise

numbers numbers, instruction

CLOCK The

PERIOD

basic referred and

other

HR-0032

are

channel

forms

unit

to

as a clock

timing

indicated,

indicated

numbers,

of

which

CPU

are

computation

period

considerations

numbers with

an 8 subscript.

instruction

given

in

time

(CP).

are

in

this

parcels

octal

is

Instruction

often

1-4

manual

in

instruction

without

9.5

nanoseconds

issue,

measured

are

decimal

Exceptions

the

subscript.

(ns)

memory

in

CPs.

numbers.

are

register

buffers,

and

is

references,

and

A

SYSTEM CDIPONEN'l'S

The

system devices, parts can

for

of a system.

be

refrigeration, distribution

components

CENTRAL PROCESSING UNITS

is

front-end

part

of

are

composed

interfaces,

the

system.

motor-generators

units

for

described

Optionally,

of

a mainframe and an

and

optional

a Cray

Supporting

to

the

mainframe,

on

the

following

I/O

tape

Solid-state

this

equipment

provide

I/O

Subsystem, pages.

Subsystem.

devices

Storage

are

system

power, and power

and

Mass

are

also

Device

condensing

the

SSD.

storage integral

(SSD)

units

System

Each share

the

(CPO

CPU

has

Central

sections

basic

organization components and Figure

CONTROL

•

1-4

SECTION

Instruction buffers

Control registers

Exchange mechanism

Interrupt Programmable

clock Status

register

shows mainframe

-

independent

Memory

are

and

described

of

control

COMPUTATION

•

and

SECTION Registers Functional

units

control the

the

data

and

computation

inter-CPO communication and

in

later

computer,

paths

sections.)

figure

of a single

chassis.

CPU

COMMUNICATION

SECTION

Shared

2

million

•

Semaphore

•

registers Real-time

•

register

MEMORY

64-bit

registers

SECTION

or 4 million

words

-

Clock

,

sections.

Figure

1-3

illustrates

CPU

COMPUTATION

SECTION

Registers

•

Functional

•

units

in

I/O

1-2

the

Both

CPOs

sections.

illustrates

the

system.

CONTROL

Instruction

•

buffers

Control

•

registers

Exchange

•

mechanism

Interrupt

•

Programmable

•

clock

Status

•

register

SECTION

I

HR-0032

Four

•

6 Mbyte

One 1250 Mbyte

Two

100 Mbyte

Figure

1-2.

I/O

SECTION

per

second

Basic

channel

organization

per

dual-processor

1-5

pairs

pair

pairs

of

system

the

A

77

liD

Ak

jSj

Si

t

lSi

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lSi

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t

IAi

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Figure

Ai

1-3.

\....-,ij----.:..;.:.....----I-4--+-~_..j

c::..(.;'ooo----

lOa

Control

-I

___

ReaI-Ti.eClod

0--

I

0'-

I

and

A-'-i

____

SM

ST

S8

data

--

Sjl

I"

Sil

s;!

Ail

paths

......

----1

*The

Vector

input

path with

Approximation

The

Second Vector

its

input

Floating-point

Issue

tSi

Si

t

Si

t

tAi

for a single

Functional Units

Pop/Parity

unit.

and

output

Multiply

the

logical

shares

Reciprocal

s"ares

path

with

unit.

its

the

CPU

t

Second

HR-0032

Vector

Logical

unit

not

available

1-6

on

all

machines.

A

Figure

INTERFACES

The

Cray

computer

executes

1-4.

mainframe network. under

the

CRAY

is

A

front-end

control

X~P

Model

designed

of

22

or

for

use

computer

its

own

24 6-column

with

front-end

system

operating

mainframe

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self

system.

chassis

computers

contained

in

and

a

Standard

of

front-end

output

from compensate electrical

of

the

I/O

through

the

a 6 Mbyte

Cray

interface,

computer

HR-0032

interfaces

computers,

it

for

differences

logic

levels,

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per

mainframe.

to

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Communication

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with a front-end

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1-7

mainframe's

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equipment.

widths,

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signals. pair

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through a front-end

typically

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channels

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to

receiving

Interfaces

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word Master computer

size,

I/O

system

adapter

Processor

module

through a front-end

channels

in

A

The

front-end

located

front-end A

primary

channel

to

the

interface,

of

the

near

the

computer

goal

connected

interface

the

front-end

interface

host

user

of

the

to

is

faster

burst

channel.

is

housed

computer.

and

interface

the

Cray

than

rate

of

the

system.

the

in a stand-alone

Its

operation

Cray

is

user.

to

maximize

Since

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the

MIOP channel limited

cabinet

invisible

use

of

channel

connected

by

(figure

the

to

both

front-end

connected

to

maximum

1-5)

the

rate

Interfaces

service

•

As a master

•

As a local

•

As a local

•

As a data

into a Single

•

As a remote

•

As

Peripheral on

the

use

to

the

Cray

an

interactive

equipment

of

front-end

mainframe

operator operator batch

concentrator

Cray

batch

attached

the

Cray

computers

in

the

station

entry

station

for

channel

entry

station

communication

to

the

system.

allow following

the

ways:

multiplexing

station

front-end

several

computer

computers

other

stations

varies

to

depending

HR-0032

Figure

1-5.

Typical

1-8

interface

cabinet

A

I/O

SUBSYSTEM

The

I/O

X-MP

Computer

a

Buffer

transfer

devices,

Memory

Subsystem,

Systems Memory, between and

the

and

the

shown

and front-end

I/O

Central

in

figure

and

has

two,

required

computers,

Subsystem's

Memory

of a Cray

1-6, three,

interfaces.

peripheral

Buffer

is

standard

or

four

It

is

Memory

or

mainframe.

on

all

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Processors designed devices,

between

models

for

fast

storage

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of

CRAY

(lOPs),

data

Four

Master

Auxiliary

one

Each

computation

are Subsystem.

types

of

lOP (MIOP), a

lOP (XIOP).

BIOP. The number

lOP

of

section,

independent

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Memory.

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The standard

interfaces

of

the mainframe with

the

entire

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Buffer

Central

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group

the

MIOP. The

over

Cray

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transferred

Memory

The This disk DMA

100

through a 100

Disk

I/O

processor

storage port Mbyte

to

per

connect

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Processors

the

I/O

and

lOP

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station

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a 6 Mbyte

Operating

Processor

and

through

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can

units.

second

Buffer

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of

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handle

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(MIOP)

t

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(BIOP)

the

mass

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Mbyte

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handle

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to

up

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channel

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configured

lOP (BIOP), a

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Subsystems and

XIOPs

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a memory

input/output

some

portion

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direct

controls

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to

one

connects

second

(COS)

storage

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per

second

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to

four

uses

is

used

to

channel

to

the

devices.

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disk

one

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pair

to

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is

section,

section.

of

the

memory

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direct

Buffer

coordinate

main

channel

for

additional

controller

DMA

port

and

another

mainframe

in

an

lOP (DIOP)

have

site

dependent.

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access

front-end Peripheral

memory

Memory

pair.

link

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to

the

pair.

for

DMA

I/O

Subsystem:

and

at

least

a

control

Input/output

requirements

ports

interfaces

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access

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to

The

MIOP

communicates

the

activities

the

from

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mainframe's

disk units

each

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storage

with

controller,

port

to Memory.

a

an

one

MIOP

and

section,

sections

for

the

to

its

local

and

(DMA)

port

the

of

the

mainframe's storage

is

Central

units.

up

to

16

one

connect

a

the

Auxiliary

The

and

interfaces

Each

controller

XIOP

uses

connect

t The

link

HR-0032

one

with

term

to

I/O

to a maximum

can

DNA

Buffer

station

the

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handle

port

for

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means

end

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(XIOP)

of up each

both

can

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four

to

four

controller

hardware

act

1-9

used

BMC-4

block

for

Block

multiplexer

and

software.

as a limited

block

multiplexer

Multiplexer

another

front

Controllers.

channels.

DMA

port

Station end

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channels

The

to

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the

MIOP).

A

I/O

Subsystem

BIOP

and

Memory.t

The

CPU

input/output

in

section

Manual,

CRI

Subsystem.

hardware

DIOP

2

or

of

publication

XIOP

this

allows

of

the

section

manual.

HR-0030,

for

simultaneous

I/O

Subsystem

for

Cray

Refer

to

for a complete

data

and

the

dual-processor

the

I/O

Subsystem

description

transfers

mainframe's

systems

Reference

of

between

Central

is

described

the

I/O

t

Software XIOP

HR-0032

is

currently

to

Figure

support

the

not

1-6.

100

Mbyte

available.

I/O

Subsystem

1-10

per

second

chassis

channel

pair

to

the

A

DISK

For

STORAGE

mass

(DSUs). A with access single

The the

missing DSUs

DD-29

an

DCU.

I/O

DMA

can

Disk

I/O

(DNA)

Processor

port

data

Subsystem

UNITS

storage,

disk

Processor

port.

and or

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configured

Storage

chassis.

the

system

controller

of

Up

to

and

the

four

DSUs

skipping

on

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an

four

disk

uses

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with

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(DCU)

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controller

all

revolutions.

an

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disk

Research,

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unit

DSUs

operating

A minimum

controller

units

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Figure

unit

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disk

direct

be

transfer

at

full

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memory

connected

data

speed

units

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without

of 2 and a maximum

1-7

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shows a

housed

in

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unit

to

of

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a

48

Each

DSU independent Inc.,

DSU. System

controller. Dynamic

(COS) subsystem publication

Manual,

CRI

has

two

data

sharing

software.

is

included

HR-0030,

publication

accesses

path

to

Reservation

of

Further

in

and

HR-0630.

for

connecting

each

DSU

devices

the

I/O

the

Mass

exists

logic

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provides

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information

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Storage

it

to

controllers.

through

controlled

supported

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Reference

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another

by

the

mass

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Hardware

The

Cray

access

Cray

storage

CRI Reference

second

Research,

to

each

Operating

HR-0032

Figure

1-7.

DD-29

1-11

Disk

Storage

Unit

A

SOLID-STATE The

Solid-state

high-performance data

I

Cray The

actual

and

system

(SSD)

between interface

speed

configuration

Reference

STORAGE

Storage

device

the

mainframe's

cable

of

Manual,

DEVICE

Device

used

set

at a maximum

these

transfers

as

CRI

(SSD)

for

temporary

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is described publication

shown

Memory

speed

dependent

in

the

HR-003l.

in

figure

data

storage.

and

the

of

1250 Mbytes

on

Solid-state

1-8

is

an

It

transfers

SSD

through a special

per

the

SSD

memory

Storage

optional,

second.

size

Device

HR-0032

Figure

1-8.

Solid-state

Storage

1-12

Device

chassis

A

CONDENSING

UNITS

Condensing

refrigeration

25-ton level which

condensers.

cooling

cools

condensing

units

the

unit.

(figure

system system

computer,

used

Heat

that

1-9)

to

is

removed

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picks

contain

cool not

part

up

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from

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the

major

computer

the

of

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and

transfers

components

chassis condensing computer

of

and

consist

unit system. it

to

the

of

by a second

Freon,

water

in

two

the

HR-0032

Figure

1-9.

Condensing

1-13

unit

A

I

POWER

The 3-phase

power contains column temperature strategic shutdown excessive

condensing

unit.

A Subsystem

DISTRIBUTION

Cray

power.

distribution

of

circuitry

smaller

mainframe,

The

adjustable

the

mainframe.

and

voltage

locations

cooling.

unit

power

chassis

are

distribution

UNITS

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Subsystem,

mainframe,

units.

transformers

monitoring

on

the

protects

control

also

mounted

or

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The power

for

The power

mainframe

the

mainframe

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on

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all

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in

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the

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the

unit

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Automatic

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have

for

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temperatures warning

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power

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Hz

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mainframe

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each

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the

for

the

at

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Figure

and

for

1-10

the

shows

I/O

Subsystem

the

power

or

distribution

SSD

(right).

units

for

the

mainframe

(left)

HR-0032

Figure

1-10.

Power

1-14

distribution

units

A

MOTOR-GENERATOR

UNITS

Motor-generator

mains

system

The control control

to

the

from

equipment

cabinet.

transients

units

400

Hz

consists

convert

power

Figure

used

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of

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1-11

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by

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on

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motor-generator

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from

the

These

the

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motor-generator

commercial units

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power

units

and

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a

its

HR-0032

Figure

1-11.

Motor-generator

1-15

equipment

A

SYSTEM

CONFIGURATION

Figures

of

the

1-12

CRAY

and

x~p

1-13

illustrate

Computer

MIOP

SlOP

DIOP

System.

two

configurations

FRONT-END

COMPUTERS

FRONT-END

INTERFACES

for

models

CRAY

X·

MP

2

OR 4 MILLION

64·BIT

22

or

MAINFRAME

WORDS

24

SSD

_Cray

• Cray 100 Mbyte channel

• Cray 1250 Mbyte channel

6 Mbyte channel

Figure

1-12.

DIOP

Block

with

diagram

full

disk

of

CRAY

capacity

X-MP

dual-processor

system

HR-0032

1-16

A

MIOP

BIOP

DIOP

XIOP

1

TO

BLOCK

MULTIPLEXER

CONTROLLERS

FRONT-END COMPUTERS

FRONT-END

INTERFACES

CRAY

X -

MP

MAINFRAME

2

OR 4 MILLION

64-BIT

WORDS

2

- - -1

TO 8 CHANNELS

SSD

_Cray

• Cray 100 Mbyte channel .Cray

6 Mbyte channel

1250 t4byte channel

Figure

I

HR-0032

1-13.

Block with

diagram

block

of

CRAY

multiplexer

1-17

X-MP

dual-processor

channels

system

A

CPU

INTRODUCTION

SHARED

RESOURCES

2

I

Both Central

million

Memory S

words of

Central

Memory, input/output the

following

CENTRAL Central

access Standard

sequentially

72

Central

(ns).

(scalar) (vector) (intermediate

The CPs. is 2 words

MEMORY Memory

memory

words

bits

with Memory

Access

to

maximum

per

Transfer

32

parcels

Central

register

Processing

the

section.

pages.

consists

(RAM)

Memory

with addressed 64

data

cycle

time,

an

operating

registers.

and

address)

transfer

CP;

for A and S registers

of

instructions

(8

words)

per

CP.

Units

inter-CPU

These

of

and

is sizes

32

banks.

words

bits

time

the

time

register,

Access

16

or T (intermediate

rate

per

(CPUs)

communication

areas

a number shared

and 8 check

is 4 clock

required

CPs +

per

CP.

are:

Banks

reside

is

time

block

CPU

to

For

by

instruction

of a system

common

of

banks

the

CPUs

2

million

are

independent

in

sequential

bits.

periods

to

fetch

14

CPs

is

17

CPs +

length

for

B,

T,

per

CPU,

the

I/O

share

section,

to

the

CPUs

of

solid-state,

and

the

words

(CPs)

an

(133

vector

for a block

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MEMORY

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Figure

t Low-numbered 4

HR-0032

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Banks

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21,25,31,35

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banks

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MEMORY

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*******************************************************

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memory mode

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HR-0032

2-7

A

l6-BANK The

increase

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MEMORY

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CORRECTION

correction/double

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Technical

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processing

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HR-0032

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216

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set

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to

INTER-CPU

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hardware

real-time

Scalar

registers,

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REAL-TIME

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(CP)

9.5 program

of

from

involved

for

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check

Appendix D

COMMUNICATION

inter-CPU

for

clock.

(ST),

described

CLOCK

mainframe

both

CPs. However,

CPUs. Programs

counter.

nanosecond

execution,

other

bit

for

communication

communication and

with

in

contains

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clock

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with

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the

if

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generation,

information

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Real-time sources

following

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counter

period.

it

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in

such

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interrupt

logic

SECTION

can

that

on

section

between

(SM)

and

Real-time

be

is

Since

be

used

an

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2-25

A

CP.u

INTRODUCTION

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SECTION

3

Both registers control execution exchange

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Exchange Two

the determined instructions

The two

non-monitor

exchange

termination same

instruction

selects

initiated

exchange

in

the F register.

initiated

program

instruction

000

004

exits

back

as

for a normal

001401

to

address 0 in

which

sequence

signal

exit

by which

are:

E~

EX

enable a program

(object)

to

of

an

CPU

by

can

to

initiate

by

instructions

execution

of

program

the

monitor

object

exit.

(IP)

memory.

is

deadstarted

Interrupt

be

initiated

Setting

program

is

the

two

program.

is

issued

(A

flag

of

an

exchange

exit

initiate

the

same

flags

Error

Normal

usually

program.

to

exit

request

The

in

switch

first.)

set

by

one

an

in

is

exit

uses

The exchange

the

first

on

setting or

more

sequence.

exchange

either

set

in

its

own

the

normal

error

CPU,

the

mainframe's

anyone flags

sequence.

case;

the F register.

termination.

exit

address

the

of

causes a Request

the

difference

exit

instruction

allows

selected

second

control

the

Interrupt

Timing

The two

A

for

CPU

of is

to

abnormal is

the

Each set

executes

program The

by

register

HR-0032

instruction

if

inactive

monitor

setting

the

currently Exchange in

monitor

termination

program

the

and

then

has a flag

active

Package

mode.

cause. selects

address

of

executing a normal

in

Exchange

called

Flags

an

the

the F register.

Package

in

this

case

are

checked

inactive

Exchange

exit

3-14

The

is

not

is

normally

for

evaluation

Package

instruction.

appropriate in

monitor

one

of

for

in

the

flag

mode. The

that

the

activation

XA

is

A

Exchange The

following

cases

for

sequence

are

an

exchange

issue

hold

conditions

issue

conditions,

sequence.

execution

time,

and

special

Hold

conditions:

• NIP

•

S,

Execution

For

32

fetch For

16

fetch

Special

cases:

If a test

CIP

and

(Waiting

test

EXCHANGE Each

l6-word deadstart. words

of

program's

and

monitor

for

the

programs

addresses

so

that

The

it

defined Exchange Exchange

in a CPU Packages software

register

V,

or A registers

contains

time:

banks,

40

operation

banks,

42

operation

and

set

NIP

registers

for

Semaphore)

and

set

instruction.

PACKAGE

MANAGEMENT

Exchange

The

defined

memory. The

Exchange

tasks.

Package.

Non-monitor

they

for

the

programs.

can

access

field

Packages

Package.

and

which

controlled

allows other

memory

can

Since be

situations.

CPs;

consists

(16

CPs).

CPs;

consists

(18

CPs).

instruction

are

Package

area

package

represent all

of

the

than

no

transfers

used

a

valid

busy

cleared

flag

resides

must

at

Other

packages

as Only memory, monitor

its

interlock

in

by

another

instruction

of

an

exchange

of

an

exchange

is

holding

and

the

set

and

the P register

in

an

lie

within

address 0 is

packages

lie

determined

the

monitor

including

program

own

when

it

exists

another

CPU

CPU,

should

sequence

in

the

CIP

exchange

area

defined

the

lower

the

deadstart

provide

for

outside

by

the

program

Exchange

to

define

is

the

currently

between

modification

be

avoided,

(24 CPs)

register,

occurs

pointing

during

4096

(10,0008)

monitor

object

of

the

field

base

and

has a field

Package

or

alter

an

exchange

of

except

and

both

with

to

the

system

programs

lengths

limit

defined areas. all

active

sequence

Exchange

under

a

WS

Proper

management

program

it.

The

exchanged

HR-0032

always

exchange

into

of

Exchange

exchanges

ensures

its

proper

Packages

back

that

to

the

Exchange

the

monitor program Package.

3-15

dictates

information

that a non-monitor

program

that

is

exchanged

always

to

A

For

example,

following

execution

exits so,

by

program A sets program execute. Package

The

program same

to

exchange

B's

time,

Exchange

When

To

the

illustrate

executing,

the deadstart. interval

issuing

(B)

Exchange

Program A

point

sequence

Exchange

the

Package

exchange

the

an

Interrupt

program B cannot

B's

Program program execution

parameters

A's

parameters

interval

monitor

since

a

normal the

Package

sets

back

to

Package

exchange

area

with

is

complete,

exchange

alter

exchange

program

No

interrupts

it

exit

contents

the

to

program

is

(A)

in

monitor

instruction

of

so

that

exchange

A.

program B causes

to

be

address

all

in other program B begins

sequence,

flag

the exchange

held

sets

XA

register,

in

back

initiating

back

program

into

begins

(except

mode. Program A

(004).

the

XA

register

program B is

address

the entered the

XA

in

register

program

assume

the

into

B's

the

its

package

operating

an

execution

memory)

However, to

the

in

program

exchange the

XA

goes

parameters

its

that

while

an

exchange

exit

is

Exchange

area

interval

can

terminate

voluntarily

point next

program

B's

address

register.

to

program

for

execution

program B is

sequence.

back

to

Package

during

registers.

before

to

the

Exchange

from

At

program

interval.

program

area; the

its

doing user

to

the

B's

A.

Since A.

Program the

exchange

processor Exchange clears

normal C

can

the

exit

execute

Further COS

EXEC/STP/CSP

MEMORY At

for

FIELD

execution

instructions

program

begin

can

The

All one

at

continue

fields

memory of

the

field.

an

absolute

reference

determine

A, upon

resuming

and

into

execution.

Package

interrupt

instruction

in

information

PROTECTION

time

when

any

can

the word to

another

overlap.

addresses two

base

An

object

address

to

memory

if

the

sets for

the

the and

monitor

on Exchange

Internal

each

object

and

data.

object

program

address

contained

addresses

program

lower

is

checked

address

execution,

XA

register

To

do interrupt initiates

(004).

mode

or

Reference

program

The

that

is a multiple

in

specifying cannot than

that against

is

within

determines

to

this,

program A sets

processing

execution

Depending

in

user

Package

management

Manual,

has a designated

field

is

that

read

loaded

is

the

or

limits

one

object

base

the

bounds

call

the

program

of

on

the

mode.

publication

are

and

initiated.

of

less

program

the

beginning

alter

any

address.

limit

assigned.

an

interrupt

proper

interrupt

XA

to

(C).

program C by

operating

is

contained

SM-0040.

field

specified

The

32

(that

is,

than a multiple

code

are

of

the

memory

Each

and

base

location

object

addresses

A memory

has

caused

point Program A

executing

task,

program

in

of

memory

by

the

monitor

fields

408) and of

relative

appropriate

program

read

to

the

32.

with

to

the

a

can

to

HR-0032

3-16

A

reference zero

value

the

assigned

beyond

is

transferred

field

the

limits

assigned

from memory. A memory is

field

allowed

limits

to

issues

issue,

write

but

and

completes,

no

write

reference

occurs.

but

a

beyond

Field

Address

Data register. limits

limits

Base

are

(IBA)

Address

These described

INSTRUCTION

The

Instruction

userls

if

than

register

instruction

the

absolute

or

equal

of

instruction The

contents

bits

of a 22-bit

assumed

Absolute

the

lBA

to

be 0 because

memory

register

twenty-second

A

reference

can

only

the

occur

memory

capacity

are

register,

BASE

Base address

to

the

program

buffer

of

the

addresses

power.

to

an through

contained

the

(DBA)

four

ADDRESS

register,

registers

in

the

REGISTER

Address

field.

at

the

contents

executing.

fetch

memory

IBA

time

register address. of

to

the P register

absolute

a jump

of

the

in

four

Instruction

and

following

(IBA)

An

instruction

which

of by

the

number

for

an

address

or

machine.

registers:

Limit

and

the

flags

paragraphs.

register

the

instruction

the

current

This

determination

the

CPU.

are

interpreted

The

low-order 5 bits

of

banks,

instruction

(high-order

less

branch

than instruction

the

Address

Data

Limit

associated

holds

can

only

is

Exchange

as

32

fetch

22

the

address

Instruction

(ILA) Address with

the

base

be

executed

located

Package

is

the

high-order

of

(decimal)

are

formed

bits)

modulo two

defined

to

an

Base

register,

(DLA)

the

field

address

by

is

greater

IBA

made

the

at

address

banks.

by

address

of

the

17

adding

to

by

IBA

beyond

the

CPU

are

the

INSTRUCTION

The

Instruction

the

userls absolute current

address

Exchange

determination

The

contents bits

of a 22-bit assumed largest

[(ILA) x 2

If

by

the

generates

to

absolute

the

final

CPU

currently

5

a

HR-0032

LDMIT

ADDRESS

Limit

field.

An where Package

is

made

of

the

lLA

memory

be 0 because

address

] -

1.

absolute

does

not

fall

executing

program

range

REGISTER

Address instruction

it

is

located

lLA

register

at

instruction

register address.

of

the

that

address

can

of

between

Exchange

error

(ILA)

can

are

The

number

be

the the Package

interrupt.

3-17

register

only

is

of

buffer

less

the

holds

be

executed

than

program

fetch

interpreted

low-order 5 bits

of

banks,

executed

32

by a program

instruction range

of

IBA

addresses

and

the

executing.

time

as

the

(decimal)

buffer lLA

registers,

limit

by

the

contents

by

the

high-order

of

the

is

fetch

contained

address

CPU

if

of

the

This

CPU.

address

banks.

defined

as

computed

within

the

of

the

17

are

The

by

CPU

A

DATA

BASE

The

Data

data

field. absolute the

contents

executing.

stored The

bits

by

contents

of a 22-bit

register

formed

two

to

by

the

ADDRESS

Base

An

address

of

This

the

of

REGISTER

Address

operand

where

the

determination

CPU.

the

memory

are

assumed

adding

the

twenty-second

(DBA)

can

the

current

DBA

register

address.

to

be

DBA

register power.

register

only

be

operand

Exchange

is

are

O.

Absolute

holds

fetched

is

located

Package

made

interpreted

The

low-order

to

the

each

memory

modified

base

or

stored

is

DBA

time

5

addresses

address

by

greater

register

an

operand

as

the

bits

operand

of

the

CPU

than

of

the

is

high-order

of

the

for

operands

address

the

if

or

equal

program

fetched

DBA

modulo

user's

the

to

or

17

are

DATA

contents

The the CPU

LLMIT

Data user's

if

the

Limit

of

executing.

stored The

bits

register

by

contents

of a 22-bit

are

referenced

If

the

final

not

fall

between

executing

operand

PROGRAM

The

(address)

RANGE

Program boundaries out-of-range a

branch

the

or

limits. terminates

the

Program aborting

the

ADDRESS

Address

data

field.

absolute

the

current

This

determination

the

CPU.

of

the

memory

assumed

for

data

absolute

the

Exchange

ERROR

Range

of

the

memory

jump

instruction

The

Program

program

Range

user

REGISTER

(DLA)

An

address

Exchange

DLA

register

address.

to

be

by a program

address

range

Package

range

Error

IBA

error

flag

and

ILA

reference

Range

execution.

Error

flag

program.

register

operand

where

is

O.

The

of

addresses

DBA

and

interrupt.

sets

registers can

calling

Error The

and

holds

can

only

the

operand

Package

made

are

The

DLA

each

interpreted

low-order

largest

is

defined

the

operand

contained

DLA

registers,

if

a memory

is

occur

in a non-monitor

for a program

flag

monitor

takes

appropriate

the

be

is

register

time

absolute

by

as

reference

for

an

causes

program

(upper)

fetched

located an

operand

as

the

5

bits

address

[(DLA)

computed

within

the

instruction

address

an

error

checks

action,

limit

or

stored

is

of

the

high-order

of

the

x 25] -

by

the

CPU

generates

outside

mode

above condition the

perhaps

address

by

less

than

program

is

fetched

DLA

that

can

1.

the

CPU

currently

the

fetch.

program

or

state

of

the

or

17

be

does an

An

on below that

of

HR-0032

3-18

A

OPERAND RANGE ERROR

The

Operand

set

and

registers register

Range

program

Range

Error Error

Range

a memory

is

called

and

the

flag

execution.

flag

reference

Operand causes

and

program.

Error

to

The

takes

flag

outside

read

or

Range

an

error

monitor

appropriate

sets

write Interrupt

condition

program

if

the

an

Operand

boundaries

operand

Error

flag

that

checks

action,

the

perhaps

Range

for

of

the

an is

Error

A, set.

terminates

state

aborting

DBA

B,

the

of

Mode and

S, The

the

flag

DLA

T,

or

Operand

user

Operand

the

user

is

V

PROGRAMMABLE

The

programmable intervals. periodic

interrupt. nanoseconds shorter

overhead

than

involved programmable Interrupt

Countdown (ICD)

INSTRUCTIONS

Four

monitor

0014j4

001405

001406 ECI

CLOCK

clock

Intervals to

approximately

100

microseconds

in

clock

mode

PCI

are

instructions

Sj

CCI

can

be

selected

The

clock

40.8

processing

the

Interrupt

counter,

Enter

Clear

request

Enable request

used

under frequency

seconds

are

not

the

support

(sj)

to

accurately

monitor

is

are

practical

interrupt.

Interval

and

four

the

Interrupt

the

programmable

the

programmable

measure

program

105

Mhz.

control

possible.

due

to

Supporting

(II)

register,

monitor

mode

programmable

Interval

clock

the

Intervals

the

monitor

the

instructions.

clock:

(II)

register

interrupt

duration generate

from

the

of a

9.5

with

001407

INTERRUPT

The

32-bit value clock

equal

interrupt low-order counter

when

HR-0032

DCI

INTERVAL

Interrupt

to

the

requests.

32

bits

of

instruction

REGISTER

Interval

number

the

of

Sj

0014j4

Disable request

(II)

CPs

The

interrupt

register

that

is

executed.

3-19

the

programmable

can

are

to

interval

into

the

be

elapse

II

register

clock

loaded

between

is

transferred

interrupt

with a binary

programmable

from

and

the

ICD

the

A

This

counter

request. instruction

value

each

is

time

The

0014j4.

held content

in

the

II

counter

of

the

register

reaches 0 and

II

register

and

is

transferred

generates

is

changed

an

only

to

the

interrupt

by

another

ICD

INTERRUPT

The

32-bit

the

II continuously of

the

request

repeats

interrupt

When programmable

mode.

CLEAR

Following a program

the

until programmable

interrupt request

interrupt

COUNTDOWN

Interrupt

register

counter

and the

request

programmable

a

clear

request

set

PROGRAMMABLE

request

when

but

counts

is

samples

countdown

at

programmable clock clock

causes

in

monitor

can

COUNTER

Countdown (ICD) instruction

down,

o.

The

ICD

the

interval

to

zero

regular

clock

interrupt interrupt

mode

CLOCK

interrupt

be

interrupt

clock

an

interrupt is

INTERRUPT

cleared

counter

0014j4 decrementing sets

cycle,

intervals

request request

interval,

the

value

interrupt

held

REQUEST

by

setting

request

can

is

only

until

executing

is

preset

is

executed. by 1

each

programmable

held

determined

in

the

is

request

be

set

executed.

when

the

system

an

active

instruction

the

programmable

by

set,

only

not

programmable

to

the

This

counter

CP

until

clock

II

is

after

A

programmable

in

switches

interrupt

register.

the

interval

it

remains

executed.

the

monitor

001405.

contents

runs

the

content

The

clock

value.

set

A

enable

clock

mode. A

to

user

clock

of

ICD

Following

the

programmable

001407.

PERFORMANCE

The

system hardware performance.

instructions references,

Appendix C

HR-0032

any

MONITOR

contains

for

deadstart,

clock

events

The

events

issued,

and

complete

interrupt

a

set

that

hold are

information

the

monitor

of

eight can

that

can

issue

selected

program

by

issuing

performance

be

used

be

tracked

conditions,

through

on

performance

3-20

should

instructions

counters

to

indicate

are

the

number

instruction

ensure

to

relative

the

number

of

0015jO.

monitoring.

the

001405

track

of

fetches,

state

and

certain specific Refer

of

to

A

DEADSTART The

deadstart mainframe whenever All

registers memory

following I/O

Subsystem.

1.

2.

4.

The

Master

critical

clears activates inactive. monitor

memory.

sequence program

the

should

Turn Turn

3.

Turn Load memory

5.

Turn

control

the

program.

Turning

to

in

SEQUENCE

sequence

after

sequence

the

power

operating

in be

on

Master

on

I/O

off

Clear

input

MCU

The

I/O

read

CPU

0 (PN=O).

the considered

I/O

Master signal

latches

Channel

input

The Exchange

off

this

of

operations

has

been

system

machine,

of

operations

Clear

via

Subsystem

signal.

Clear

I/O Clear halts

to Address

channel.

the

Master

package

signal.

starts

turned

is

all

invalid

to

signal.

Subsystem.

signal.

all

predetermined

then

Package

Clear

and

off

to

be

control

after begin

internal

register

All

other

loads

signal

to

begin

reinitialized

must

a

program

and

then

latches, power the

program

computation states. of

the

input

an

initial

be

located

initiates

execution

turned and

has

been

The

MCU

channels

Exchange

running

on

in

the

all

words

turned

is

initiated

and

forces

I/O

Clear

channel

at

address 0 in

the

exchange

of

the

in

the

again

mainframe.

and

remain

Package

monitor

or

in

on.

by

signal

The

the

and

I

CPU

1 (PN=l)

(IP)

is

Because Exchange

Package

can

be

started panel.) system.

remains

issued the

Package

at

Subsequent

in

CPU

exchange

at

address 0 before

first

in a master-cleared

O.

Then

of

CPU 0 overwrites

address

by

using a switch

actions

CPU 1 exchanges

0,

CPU 0 must

allowing are

dictated

other

on

state

the

reinitialize the

by

until to

contents

CPUs

to

mainframe's

the

design

instruction

address 0 in

of

the

Exchange

start.

of

(Either

control

the

001401

memory_

inactive

CPU

operating

HR-0032

3-21

A

CPU

INTRODUCTION

C·OMP.UT

ATION

SECTION

4

I

Each computation

Address

performed A

a of or

The

instruction processing

units

functional

set dedicated

functional

Address

to

distributed controlling registers

units

address Central

CPU associated addresses

integer

vector

series

results.

operand

main

dedicated

of

64-element

information

address

generate

registers.

Memory

processing arithmetic

of

contains

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4-13

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word 3

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population

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subsection

on

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64-bit

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4-20

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subsection

zero is

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bits

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larger

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A

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