Cosmo CEB-V850ES/FJ3, CEB-V850ES/SJ3 Hardware User Manual

CEB-V850ES/FJ3·SJ3 Evaluation Board HardwareUser’s Manual

CEB-V850ES/FJ3·SJ3 EVALUATION BOARD
HARDWARE USER’S MANUAL

Date Published Sep. 2007 (The 1.1 st edition)
COSMO Co., Ltd.
Control No. CCEB-HUMFJ3SJ3_01_1E

CEB-V850ES/FJ3·SJ3 Evaluation Board HardwareUser’s Manual

Cautions

• The information in this document is subject to change without notice. Before using this document,
please confirm that this is the latest version.

• No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of COSMO Co., Ltd.

• COSMO Co., Ltd. does not assume any liability for infringement of patents, copyrights or other
intellectual property rights of third parties by or arising from use of device described herein or any
other liability arising from use of such device. No license, either express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of COSMO Co., Ltd.
Descriptions of circuits, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, and information in the design of the customer’s equipment shall be done under the full
responsibility of the customer. COSMO Co., Ltd. assumes no responsibility for any losses incurred by
the customer or third parties arising from the use of these circuits, and information.

The information in this document is current as of 2007. T he information is subject to change without
notice.

Trademarks
CEB-V850ES/FJ3·SJ3 is a trademark of COSMO Co., Ltd.
Other company names and product names provide in this document are either registered trademarks or
trademarks of respective companies.

CEB-V850ES/FJ3·SJ3 Evaluation Board HardwareUser’s Manual

CONTENTS



1.

Overview .....................................................................................................................................................1

2. Document....................................................................................................................................................1

3. Hardware Specifications..............................................................................................................................2

3.1 Overview .....................................................................................................................................................2

3.2 Block Diagram.............................................................................................................................................3

3.3 Configuration...............................................................................................................................................4

3.3.1 Power supply........................................................................................................................................5

3.3.2 CAN-I/F................................................................................................................................................7

3.3.3 LIN-I/F................................................................................................................................................ 11

3.3.4 Expansion connectors (J5, J6)...........................................................................................................14

3.3.5 7-segment LED (LED1)......................................................................................................................15

3.3.6 8-bit DIP SW (SW1) ...........................................................................................................................15

3.3.7 RESET...............................................................................................................................................16

3.3.8 INTP0 SW (SW2)............................................................................................................................... 17

3.3.9 NMI SW (SW3)...................................................................................................................................17

3.3.10 CLOCK...............................................................................................................................................18

3.3.11 USB....................................................................................................................................................19

3.3.12 Evaluation environment......................................................................................................................21

3.3.13 The connector for MINICUBE (CN6) ..................................................................................................24

3.3.14 The connector for FL-PR4, FL-PR5, MINICUBE2 (CN5).................................................................... 25

3.3.15 The connector for CPU I/O pins check...............................................................................................26

3.4 Memory map .............................................................................................................................................28

3.5 Notes at the time of user circuitry..............................................................................................................30

3.5.1 Consumption current..........................................................................................................................30

3.5.2 I/O signals ..........................................................................................................................................30

3.6 A jumper setup at the time of shipment.....................................................................................................31

4. CAN expansion board ...............................................................................................................................32

4.1 Specifications.....................................................................................................................................32

4.2 Block diagram .................................................................................................................................... 32

4.3 Board size.......................................................................................................................................... 33

4.4 External connectors............................................................................................................................34

4.5 Evaluation board mating.....................................................................................................................35

1

1. Overview

This manual prescribes a CEB-V850ES/FJ3 Evaluation Board and a CEB-V850ES/SJ3 Evaluation Board.
The CEB-V850ES/FJ3 features an NEC Electronics-made 32-bit single-chip microcontroller V850ES/FJ3.
The CEB-V850ES/SJ3 features an NEC Electronics-made 32-bit single-chip microcontroller V850ES/SJ3.
In addition, USB interface, 7-segment LED, CAN interface, LIN interface, N-wire connector, etc. are carried
as a common device.
Moreover, the CEB-V850ES/FJ3 Evaluation Board can extend a CAN port by two channels b y connecting
an optional CAN expansion board(CAN-EXT BOARD).
The MINICUBE or the MINICUBE2 by NEC electronics incorporated company can be used as development
environment.
The FL-PR4 or the FL-PR5 (or the FP-LITE) made by Naito Densei Machida Mfg. Co., Ltd. are required for
writing programs.

*The MINICUBE, the MINICUBE2, the FL-PR4, and the FL-PR5 are not included with this evaluation kit.

2. Document

The following documents are included as PDF files.

CEB-V850ES/FJ3·SJ3 Evaluation Board Hardware User's Manual
CEB-V850ES/FJ3 Evaluation Board Circuit Diagrams
CEB-V850ES/FJ3 Evaluation Board Parts List
CEB-V850ES/SJ3 Evaluation Board Circuit Diagrams
CEB-V850ES/SJ3 Evaluation Board Parts List
V850ES/FJ3 Hardware Preliminary User's Manual
V850ES/SJ3 Hardware Preliminary User's Manual

In addition, please refer to attached "document list."

CEB-V850ES/FJ3·SJ3 Evaluation Board HardwareUser’s Manual

2

3. Hardware Specifications

3.1 Overview

The specifications of the CEB-V850ES/FJ3·SJ3 Evaluation Board are shown below.

• CPU V850ES/FJ3 × 1 (or V850ES/SJ3)

·V850ES/FJ3
Operating CLK direct mode: 6 MHz, PLL mode: 48 MHz
Oscillator (MAIN: 6 MHz , SUB: 32.768 KHz )

·V850ES/SJ3
Operating CLK direct mode: 4 MHz, PLL mode: 32 MHz
Oscillator (MAIN: 4 MHz , SUB: 32.768 KHz )
* The crystal for MAIN clocks is socket-mounted.

• Check pin A through hole for each signal line check is around CPU.
( Two rows of half pitch)

• External connectors Expansion connector (30-pin 2.54 pitch) × 2
Connector for FL-PR4, FL-PR5, MINCUBE2 (16-pin) × 1
MINICUBE connector (26-pin) × 1
CAN-I/F connector (D-SUB 9-pin [female] ) × 2
LIN-I/F connector (3-pin) × 2

• SW PUSH SW × 3 (RESET, NMI, INTP0 )
DIP SW (8-bit) × 1

• Jumpers Development environment setting
(MINICUBE2 / MINICUBE, FL-PR4, FL-PR5)
UART setting
(USB / FL-PR4, FL-PR5, MINICUBE2)
CAN termination resistance setting
LIN-master/slave switching

• LED Power LED (+5 V ): Green,
7-segment LED × １

• Check pin +12 V, +5 V, +3.3 V, GND

• Power supply AC adapter (DC+12 V) input

With regulator IC, +5 V(FJ3) , +3.3V(SJ3) output

CEB-V850ES/FJ3·SJ3 Evaluation Board HardwareUser’s Manual

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3.2 Block Diagram

Whole block diagram

FJ3

MINICUBE

FL-PR4/FL-PR5/MINICUBE2

LIN0 LI N1CAN0 CAN1

DRV

DRV

DRV

DRV

Expans ion J5 Expansi on J 6

C_POW

C_POW

+12V

RESET NMI INTP0

DIPSW8 bit 7seg 8bit

Power supply

+12V IN

5/3.3

reg

C-POW

USB

miniB

VBUS

+5V

RFJ

RSJ

Max 500

mA

12 / 5

reg

+12 V

USB

USB/

UART

V850ES/FJ3

Evaluation Boar d wh ole block diagram

Figure 3.2

The above figure is the case where V850ES/FJ3 is mounted. In this case, CPU power supply voltage is set
to +5V. Moreover, when V850ES/SJ3 is mounted, CPU power supply voltage is set to +3.3V.*

* Since a voltage setup is set up at the time of shipment, especially a visitor does not need to be conscious
of it.

CEB-V850ES/FJ3·SJ3 Evaluation Board HardwareUser’s Manual

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3.3 Configuration

The following figure shows the physical placement and the outside of the major components on the
CEB-V850ES/FJ3·SJ3 evaluation CPU board.
The various components are described below.

Figure 3.3

CN1:CAN0(FJ3) CAN1(SJ3), CN2:CAN1(FJ3) CAN0(SJ3), CN3:LIN0, CN4:LIN1
CN5:FL-PR4 / FL-PR5 / MINICUBE2, CN6:MINICUBE
CN7:USB
CN8:POWER
J5:EXPANSION, J6:EXPANSION
SW1:DIP8bit, SW2:INTP0, SW3:NMI, SW4:RESET

CN1

CN2

CN3 CN4

CN7

J5

J6

SW1

SW2

SW3

SW4

CN1

CN2

CN3 CN4

CN5

CN6

CN7

CN8

J5

J6

SW1

SW2

SW3

SW4

CEB-V850ES/FJ3·SJ3 Evaluation Board HardwareUser’s Manual

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3.3.1 Power supply

(1) Power supply part

Although premised fundamental on use in +12V input from the attached AC/DC adapto r, it is possible to
also make it operate by the power supply supply from a USB port.
Notes: As for the USB port, power supply supply capability is restricted to 500mA by specification. When
you operate this board in a USB port, please use cons umption current by 500mA or less. moreover, since
+5V are supplied from a USB port, A LIN-I/F function cannot be used.
A block diagram is shown below.

Power Supply

+12 V IN

5/3.3

reg

C-POW

USB

miniB

VBUS

+5 V

RFJ

RSJ

Max500 mA

12 / 5

reg

+12V

+12V

LIN-0
LIN-1

Peripheral IO device
Expansion connectors

+5V

C-POW

CPU
CPU Peripheral

(

Pull

-up resistance

）

Figure 3.3.1(1)

CEB-V850ES/FJ3·SJ3 Evaluation Board HardwareUser’s Manual

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(2) Power supply connector (CN8)

Please use DC jack side of an attached AC adaptor for a power supply connector (CN8), connecting.
The power supply to supply is as follows.

AC adaptor : NP12-US1210 (Akizuki Denshi Corp)
Input voltage range : AC100-240 V 50/60 Hz
Output voltage : DC12 V
Current : 1 A max
Suitable connector : Type A (φ5.5)
Polarity :

GND

GND

+12 V+12 V

Figure 3.3.1 (2)

CEB-V850ES/FJ3·SJ3 Evaluation Board HardwareUser’s Manual

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3.3.2 CAN-I/F

(1) CAN-I/F overview

Two CAN interfaces are mounted as standard.
A block diagram is shown below.

CTXDn TXD

RXD

CAN_H
CAN_L

CAN transceiver

( TJA 1050 )

1

6

2

7

3

8

4

9

5

RS

CRXDn

V850ES/FJ3·SJ3

Common

mode filter

Terminator

change jumper

JP1,2

Open setting

jumper
JPX2,4

D-SUB

9 pin

[ female]

P***

Open setting

jumper
JPX1,3

Figure 3.3.2(1)

CEB-V850ES/FJ3·SJ3 Evaluation Board HardwareUser’s Manual

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(2) CAN-I/F connector (CN1, CN2)

In the case of CEB-V850 ES/FJ3, CAN0 is assigned to CN1 and CAN1 is assigned to CN2, respectively.
In the case of CEB-V850 ES/SJ3, CAN1 is assigned to CN1 and CAN0 is assigned to CN2, respectively.
Since the connector on a substrate mounts Dsub9 pin (female), the connector by the side of a cable should
use Dsub9 pin (male) at the time of cable creation.
Pin distribution table is shown below.

CAN I/F connector pin distribution table

Pin№

CN1(CAN0:FJ3 CAN1:SJ3) CN2(CAN1:FJ3 CAN0:SJ3)

1 N.C. N.C.
2 CAN_L0(FJ3) CAN_L1(SJ3) CAN_L1(FJ3) CAN_L0(SJ3)
3 GND GND
4 N.C. N.C.
5 Coupling with capacitor and fed to GND. Coupling with capacitor and fed to GND.
6 N.C. N.C.
7 CAN_H0(FJ3) CAN_H1(SJ3) CAN_H1(FJ3) CAN_H0(SJ3)
8 N.C. N.C.
9 N.C. N.C.

Table 3.3.2 (2)

Loading connector part number : XM3B-0922-112 (OMRON Corp.)

CEB-V850ES/FJ3·SJ3 Evaluation Board HardwareUser’s Manual

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(3) CAN transceiver

TJA1050T (Philips Corp.) are mounted in this board as a CAN transceiver.
Refer to the applicable data sheet for the details of a device.
Connection of CPU and a CAN transceiver is shown below.

CN1 connection

CPU TJA1050T Signal Name
CTXD0(FJ3) CTXD1(SJ3)（P33）

TXD Transmitting data

CRXD0(FJ3) CRXD1(SJ3)（P34）

RXD Receiving data

VREF VREF
CAN_H,CAN_L CAN
PCM4 RS RS
VCC,GND

Power supply（+5Vsupply）

Table 3.3.2 (3)-1

CN2 connection

CPU TJA1050T Signal Name
CTXD1(FJ3) CTXD0(SJ3)（P36）

TXD Transmitting data

CRXD1(FJ3) CRXD0(SJ3)（P37）

RXD Receiving data

VREF VREF
CAN_H,CAN_L CAN
PCM5 RS RS
VCC,GND Power supply(+5Vsupply)

Table 3.3.2 (3)-2

(4) CAN signal terminus setup

A CAN signal terminus value is set up by JP1 and JP2.
JP1 corresponds to CN1 and JP2 correspond to CN2, respectively.

Setup Terminator value (common to JP1 and JP2)
Open Infinite (default)
1-2 short circuit

120Ω

1-2,3-4 short circuit

60Ω

Others Prohibition of a setup

Table 3.3.2 (4)

JP1,2

4 2

3 1

CEB-V850ES/FJ3·SJ3 Evaluation Board HardwareUser’s Manual

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(5) About JPX1-JPX4

Although the pattern connects between 1-2 and between 3-4 of JPX1-JPX4, a signal is separable by cutting
the pattern on the back side (soldering side) of each jumper.
As standard, the following jumper is un-mounting.

The installation part of each jumper is shown below.



JPX Function
JPX1 CN1 ( Between CAN transceiver - CAN connector )
JPX2 CN1 ( Between CPU - CAN transceiver )
JPX3 CN2 ( Between CAN transceiver - CAN connector )
JPX4 CN2 ( Between CPU - CAN transceiver )

Table 3.3.2 (5)

JPX1,3

4 2

3 1

JPX2,4

4 2

3 1

CEB-V850ES/FJ3·SJ3 Evaluation Board HardwareUser’s Manual

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3.3.3 LIN-I/F

(1) LIN-I/F outlline

Two LIN interfaces are mounted as standard.
A block diagram is shown below.

TXDA* TXD

RXD

LIN

LIN transceiver

(TJA1020)

NSLP

+12V

RXDA*

V850ES/FJ3·SJ3

Open setting

jumper

JPX5 , 8

3pin

connector

P***

BAT

1
2
3

Open setting

jumper

JPX6 , 10

Open setting

jumper

JPX7 , 9

NWAKE

INH

Master / Slave

Change jumper

JP3 , 5

Master / Slave

Change jumper

JP4 , 6

Cmaster Cslave

+12V

Figure 3.3.3 (1)

(2) LINE-I/F connector (CN3, CN4)

LIN0 is assigned to CN3 and LIN1 is assigned to CN4, respectively.
Connector pin distribution table is shown below.

LIN I/F connector pin description

Pin№ CN3（LIN0） CN4（LIN1）

1 LIN_Bus LIN_Bus
2 +12V +12V
3 GND GND

Table 3.3.3 (2)

Loading connector part number : IL-SP-S3FP2(J.S.T. Mfg Co.Ltd.)

CEB-V850ES/FJ3·SJ3 Evaluation Board HardwareUser’s Manual

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(3) LIN transceiver

TJA1020T (Philips Corp.) are mounted in this board as a LIN transceiver.
Refer to the applicable data sheet for the details of a device.
Connection of CPU and a LIN transceiver is shown below.

LIN0

CPU TJA1020T Signal name
RXDD2（P39）

RXD Reception
P63 NSLP SLEEP MODE
（pullup）

NWAKE
TXDD2（P38）

TXD Transmission
LIN LIN
（JP3）

INH MASTER/SLAVE
BAT,GND Powersupply(+12V supply)

Table 3.3.3 (3)-1

LIN1

CPU TJA1020T Signal name
RXDD3（P80）

RXD Reception
P64 NSLP SLEEP MODE
（pullup）

NWAKE
TXDD3（P81）

TXD Transmission
LIN LIN
（JP5）

INH MASTER/SLAVE
BAT,GND Power supply(+12V supply)

Table 3.3.3 (3)-2

(4) LIN MASTER/SLAVE setting

A jumper is set up by the mode of LIN of operation.

・LIN0 MASTER/SLAVE

Jumper MASTER setting SLAVE setting
JP3 2-3 short circuit (default) 1-2 short circuit
JP4 1-2 short circuit (default) 2-3 short circuit

Table 3.3.3 (4)-1

・LIN1 MASTER/SLAVE

Jumper MASTER setting SLAVE setting
JP5 2-3 short circuit 1-2 short circuit (default)
JP6 1-2 short circuit 2-3 short circuit (default)

Table 3.3.3 (4)-2

JP3−6

1
2
3

CEB-V850ES/FJ3·SJ3 Evaluation Board HardwareUser’s Manual

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(5) About JPX5-JPX10

Although the pattern connects between 1-2 and between 3-4 of JPX5-JPX8, and between 1-2 of JPX6,
JPX9, JPX10, a signal is separable by cutting the pattern on the back side (soldering side) of each jumper.
As standard, the following jumper is un-mounting.

The installation part of each jumper is shown below.

JPX Function
JPX5 LIN0 ( Between CPU - LIN transceiver )

JPX6 LIN0 ( Between CPU – LIN transceiver NSLP )
JPX7 LIN0 ( Between LIN transceiver – LIN connector )
JPX8 LIN1 ( Between CPU – LIN transceiver )
JPX9 LIN1 ( Between CPU – LIN transceiver NSLP )
JPX10 LIN1 ( Between LIN transceiver – LIN connector )

Table 3.3.3 (5)

4 2

JPX5,8

3 1

JPX6,7,9,10

1 2

CEB-V850ES/FJ3·SJ3 Evaluation Board HardwareUser’s Manual

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3.3.4 Expansion connectors (J5, J6)

A signal can be pulled out from this connector and it can connect with a user circuit. Moreover, an optional
*CAN expansion board is connectable.
As standard, it is not mounted.

Expansion connectors table

J5 J6

Pin

№

Signal name

Function used

on a Board

Pin

№

Signal name

Function used

on a Board
1 P00 8bit DIP-SW 1 P98/SOB1(A8) ­2 P10/INTP9 - 2 P912/_SCKB2(A12) ­3 P01 8bit DIP-SW 3 P99/_SCKB1(A9) ­4 P11/INTP10 - 4 P913/INTP4(A13) ­5 P03/INTP0 Push-SW（INTP0） 5 P910/SIB2(A10) ­6 P32/ASCKA0 8bit DIP-SW 6 P914/INTP5(A14) ­7 P04/INTP1 - 7 P911/SOB2(A11) ­8 P35 8bit DIP-SW 8 P915/INTP6(A15) ­9 P06/INTP3 - 9 PCS0/_CS0 ­10 P41/SOB0 Flash PRO4 10 PCM0/_WAIT
11 P40/SIB0 Flash PRO4 11 PCS1/_CS1 ­12 P42/_SCKB0 Flash PRO4 12 P36(IETX0) ­13 P50/KR0 8bit DIP-SW 13 PCS2/_CS2 -

14 P53/KR3/DDO N-Wire 14 P37(IERX0) ­15 P51/KR1 8bit DIP-SW 15 PCS3/_CS3 ­16 P54/KR4/DCK N-Wire 16 PCT5 8bit DIP-SW
17 P52/KR2/DDI N-Wire 17 P73/ANI3 ­18 P55/KR5/DMS N-Wire 18 PCT7 8bit DIP-SW
19 P90/TXDA1(A0) - 19 P72/ANI2 ­20 P95(A5) - 20 P60/INTP11

Expansion CAN（CAN2）RS

21 P91/RXDA1(A1) - 21 P61/INTP12

Expansion CAN（CAN3）RS
22 P96(A6) - 22 P70/ANI0
23 P92(A2) - 23 P71/ANI1 ­24 P97/SIB1(A7) - 24 P65/CTXD2 Expansion CAN（CAN2）TXD
25 P93(A3) - 25 P66/CRXD2 Expansion CAN（CAN2）RXD
26 CPOW 26

+5V

27 P94(A4) - 27 P67/CTXD3

Expansion CAN（CAN3）TXD
28 _RESET Push-SW（RESET） 28 P68/CRXD3 Expansion CAN（CAN3）RXD
29

GND

29

+12V

-

30

GND

30

GND

Table 3.3.4

The pull-up of each signal is carried out by resistance 47kΩ.
CPOW=CPU power supply FJ3:+5V, SJ3:+3.3V

*Refer to Chapter 4.

CEB-V850ES/FJ3·SJ3 Evaluation Board HardwareUser’s Manual

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3.3.5 7-segment LED (LED1)

The seven-segment LED is mounted on a board.
The LED can be statically switched on the light or put out from the port of CPU.
In case you make each segment turn on, please set a corresponding port as "0."

f b

e c

d

g

a

DP

a

.PCD

0

b

.PCD

1

c.PCD

2

d

.PCD

3

e.PCS

4

f

.

PCS

5

g.PCS

6

DP

.PCS

7

Figure 3.3.5

Segment Correspondence port Light/Extinguish default
a PCD0 0 / 1

1（pullup）

b PCD1 0 / 1

1（pullup）

c PCD2 0 / 1

1（pullup）

d PCD3 0 / 1

1（pullup）

e PCS4 0 / 1

1（pullup）

f PCS5 0 / 1

1（pullup）

g PCS6 0 / 1

1（pullup）

D.P. PCS7 0 / 1

1（pullup）

Table 3.3.5

3.3.6 8-bit DIP SW (SW1)

8-bit DIP SW is mounted on a board.
ON/OFF of DIP SW can be checked in a CPU port.
If DIP SW is turned "ON", a port will be set to "0", and a port will be set to "1" if it turns "OFF."

bit Port
DIP-SW1 P50

DIP-SW2 P51
DIP-SW3 PCT5
DIP-SW4 PCT7
DIP-SW5 P32
DIP-SW6 P35
DIP-SW7 P00
DIP-SW8 P01

Table 3.3.6

CEB-V850ES/FJ3·SJ3 Evaluation Board HardwareUser’s Manual

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3.3.7 RESET

(1) RESET overview

When the time of power on or SW4 are pushed, reset starts a board.
It is a RESET signal at the MINICUBE or FL-PR4 or FL-PR5 use and MINICUBE2 use time, and
composition differs.
A reset signal block diagram is shown below.

MINICU BE2

/ RESin

Resistance for

logic stable

11
12
13
14
15
16

VDD2

FLMD1
RFU-1

FLMD0
(/RESin)

NC

FJ3/ SJ3 MINICUBE· FL-PR4 / FL-PR5 / MINICUBE2 connection

CN 5

FL- PR4 / FL-P R 5 / MMINICUBE 2 con n e cto r

1
2
3
4
5
6
7
8
9
10

GND
/ RESout
SI/ RXD

VDD
SO /TXD

VPP

SCK

H/ S

CLK

VDE

CN6

MINICUBE

A7
A8
A9
A10
A11
A12
A13

DDI

DCK

DMS

DDO

/DRST

/RESET

FLMD0

MINICUBE , FL- PR4, FL -PR5 and

MINICUBE2 are promised on

exclusion use, respectively.

(/RESET signal is communalized)

C- POW

(

Reset sign al bl oc k diagram)

P30/ TXD0
P31/ RXD0

FLMD0

FLMD1

/RESET

DDI
DCK
DMS

DDO

/DRST

V850FJ3 /SJ 3

P62

C-POW

Short pin

2-3

1- 2
1-2
1-2

Select

A
B
B
B

Connection apparatus

MINICUBE 2
MINICUBE

FL-PR4
FL-PR5

MINICUBE 2

FL- PR4 , FL-PR5

MINICUBE

The flow of a reset signal

A

Y

B

A/B

_

ABY

A/B

_

C-POW

C-POW

Nothing 1- 2

B

FL-PR4/ FL-PR5 /

MINICUBE 2 connector

SW4

JP7

Figure 3.3.7(1)

CEB-V850ES/FJ3·SJ3 Evaluation Board HardwareUser’s Manual

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(2)RESET signal setting (JP7)

A setup of a RESET signal changes with apparatus connected.
JP7 performs a setup.

JP7

Function

1-2 short circuit Normal use, During connecting FL-PR4, FL-PR5, MINICUBE (Default )
2-3 short circuit During connecting MINICUBE2

Table 3.3.7 (2)

In case FL-PR4 or FL-PR5 or MINICUBE are used, a JP7 short pin is set to the "1-2" side, and it is set as
the course of dashed-and-dotted line (FL-PR4) and a dotted line (MINICUBE) among Figure 3.3.7(1).
(Refer to reset signal block diagram)
In case MINICUBE2 is used, a JP7 short pin is set to the "2-3" side, and it is set as the course of a solid
line (MINICUBE2) among Figure 3.3.7(1).
Please use a JP7 short pin for the "1-2" side at the time of real operation, setting it up (when you do not use
a debugger).

(3)RESET SW (SW4)

If SW4 is pushed, CPU and an evaluation board will be in a reset state.

3.3.8 INTP0 SW (SW2)

SW2 on a board is connected to P03-/INTP0 port.
A push on SW2 inputs "0" into P03-/INTP0 port.

3.3.9 NMI SW (SW3)

SW3 on a board is connected to P02-/NMI port.
A push on SW3 inputs "0" into P02-NMI port.

JP7

1
2
3

CEB-V850ES/FJ3·SJ3 Evaluation Board HardwareUser’s Manual

18

3.3.10 CLOCK

(1) Main Clock

The crystal oscillator is connected to X1 and X2 terminals of CPU.
Oscillation frequency is 6MHz in FJ3, and it is 4MHz in SJ3.
Since the socket is mounted, a crystal oscillator is exchangeable if needed. Please purchase a HC49 U/S
type crystal oscillator.
Since it operates by the CPU internal clock by the default, in case an external clock is used, an inside
register setup of CPU is changed.
Please refer to an applicable CPU user’s manual for details.

(2)Sub Clock

The crystal oscillator is connected to XT1 and XT2 terminals of CPU. Oscillation frequency is 32.768kHz.
Since it is soldered directly, crystal is unexchangeable.

CEB-V850ES/FJ3·SJ3 Evaluation Board HardwareUser’s Manual

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3.3.11 USB

(1) USB overview

USB connection with a personal computer is made using the UART interface of CPU.
USB-UART interface device FT232R is mounted and USB is changed into UART.
The USB section block diagram is shown below.

FJ3/SJ3 USB connection

P30/TXD0

P31/RXD0

V850FJ3/SJ3

FT232R

1kΩ

C-POW

RXD
TXD
/RTS
/CTS

VBUS

USBP

USBN

GND

miniB

USBN

USBP

VBUS

FP4-TXD

FP4-RXD

VCC

+5V

Supplement : Power supply

+12V IN

5/3.3

reg

C-POW

USB

miniB

VBUS

+5V

RFJ

RSJ

Max500mA

P69

/VBUSEN

VBUS

C-POW

VCCIO

C-POW

12/5

reg

+12V

JP8

1
3

2

Figure 3.3.11(1)

CEB-V850ES/FJ3·SJ3 Evaluation Board HardwareUser’s Manual

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(2) USB setting

With a flash write-in circuit, since P31 (RXD0) is common, please set a jumper (JP8) to the "1-2" side, and
perform USB communication.

JP8

CPU RXD0（P31）

1-2 short circuit TXD of USB connects. (default)
2-3 short circuit TXD of CN5 connects.

Table3.3.11 (2)

(3) The check of USB cable insertion and extraction

The insertion and extraction state of a USB cable can be checked by checking the level of P69.

P69 input state
Lo USB cable connecting
Hi USB cable un-connecting

Table 3.3.11 (3)

Refer to the user's manual etc. for a setup of P69.

(4) About driver software

It is downloadable from the homepage of Future Technology Devices International Corp.

(5) USB bus power

VBUS which is the bus power of USB is set “DIODE OR” to +5V power supply of this board.
When making it operate with this board simple substance, it can operate only by connecting USB with PC.
However, since drive current is restricted to 500mA as a standard of VBUS which is bus power, the drive of
CAN is not recommended.
(Please confirm that the whole board consumption current is 500mA or less)
Since +12V are required about LIN, it cannot operate by USB bus power.
When you operate LIN, please supply +12V from this board power supply jack.

JP8

1
2
3

CEB-V850ES/FJ3·SJ3 Evaluation Board HardwareUser’s Manual

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3.3.12 Ev aluation environment

(1) Overview

The development environment which can be used on this board is as follows.

CPU Built-in FLASH writing - FL-PR4, FL-PR5

Debugging - MINICUBE, MINICUBE2
It is designing on the assumption that the four above-mentioned kinds.
This board mounts the connector for FL-PR4, FL-PR5 connection in built-in FLASH writing.

The connector for FL-PR4, FL-PR5 connection is as common as the connector for MINICUBE2.(CN5)
Moreover, the connector for MINICUBE connection is mounted.(CN6)
A block diagram is shown in the following clause.
In circuit composition, FL-PR4, FL-PR5, MINICUBE2(CN5) and MINICUBE(CN6) constitute exclusion use
as a premise.
If FL-PR4, FL-PR5, or MINICUBE2(CN5) and MINICUBE(CN6) are connected simultaneously, since it may
be failure, please avoid concurrent use by a signal collision occurring.

(2) Setup

A setup of the following jumper (JP7) is changed according to the development environment to be used.

JP7 Function
1-2 short circuit Normal use, During connecting FL-PR4, FL-PR5, MINICUBE (Default)
2-3 short circuit During connecting MINICUBE2

Table 3.3.12 (2)

In case FL-PR4, FL-PR5 and MINICUBE are used, a JP7 short pin is set to the "1-2" side, and it is set as
the course of dashed-and-dotted line (FL-PR4, FL-PR5) and a dotted line (MINICUBE).
(Refer to Figure 4.3.7)
In case MINICUBE2 is used, a JP7 short pin is set to the "2-3" side, and it is set as the course of solid line
(MINICUBE2).
Please use a JP7 short pin for the "1-2" side at the time of real operation, setting it up (when you do not use
a debugger).

JP7

1
2
3

CEB-V850ES/FJ3·SJ3 Evaluation Board HardwareUser’s Manual

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(3)MINICUBE and FL-PR4, FL-PR5, MINICUBE2 connection block diagram

11
12
13
14
15
16

VDD 2
FLMD1
RFU- 1
FLMD0

(/ RESin)

NC

FJ3/SJ3 MI NICUBE・FL-PR4/FL-PR5/MINICUBE2connection

FL-PR4/FL-PR5/

MINICUBE2 (CN5 )

1
2
3
4
5
6
7
8
9

10

GND
/RESout
SI / RXD

VDD
SO/ TXD
VPP
SCK

H/S

CLK
VDE

P30/TXD0
P31/RXD0

FLMD0
FLMD1

/RESET

1kΩ

MINICUBE(CN6)

A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13

2A

13

B1
B2
B3

B4

B5
B6
B7
B8

B9
B10
B11
B12
B13

GND
GND
GND
GND
GND
GND
DDI
DCK
DMS

DDO
/DRST
/RESET

FLMD0

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

PORT0

PORT1

VDD

DDI
DCK
DMS
DDO

/DRST

C-POW

MINICUBE ( CN6) and FL-

PR4/FL-PR5, MINICUBE2(CN5)

are premised on exclusion use.

( /RESET and FLMD 0 signal are

communalized )

V850ES/FJ3・SJ3

USB-RXD

USB-TXD

Self-progr am f unct ion

P62

P62
Normal mode : LO
Self-programming mode : HI

1kΩ

SELF-P

( Communic ation / contr ol s ignal bloc k diagram )

C-POW

C-POW

C-POW

JP8

1

2

3

Figure 3.3.12(3)

CEB-V850ES/FJ3·SJ3 Evaluation Board HardwareUser’s Manual

23

(4) About the CPU interface at the time of CN5 use

FL-PR4, FL-PR5 and MINICUBE2(CN5) support only communication by UART for circuit simplification.
* “3-wire serial” mode is not supported.Please use FL-PR4, FL-PR5 and MINICUBE2 by “UART” mode.
(Please refer to the user’s manual of each equipment for details)
With a USB circuit (figure 3.3.11), since P31 (RXD0) is common, please set a jumper (JP8) to the "2-3" side,
and perform development and flash writing.

JP8

CPU RXD0（P31）

1-2 short circuit T XD of USB connects (default)
2-3 short circuit TXD of CN5 connects

Table 3.3.12 (4)

(5)Self-programming function

By operating FLMD0 signal by P62, a self-program function is realizable.
P62 is connected to FLMD0 through an OR gate.
P62 will become effective if FLMD0 from a debugger and a flash writer is made into a "LO" level, or in the
state of un-connecting a debugger and a flash writer.

P62 output Status Explanation / Conditions
Lo Normal Normal state

Hi Self-programming MODE FLMD0 of a debugger and a flash writer

"Lo" or it un-connects

Table 3.3.12 (5)

Refer to the user's manual of CPU etc. for a setup of P62.
Refer to the user's manual of CPU for the details of self programming.

JP8

1
2
3

CEB-V850ES/FJ3·SJ3 Evaluation Board HardwareUser’s Manual

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3.3.13 The connector for MINICUBE (CN6)

It is a connector for connecting MINICUBE which is a target CPU debugger.

No. Signal No. Signal
A1 GND B1 GND

A2 GND B2 GND
A3 GND B3 GND
A4 GND B4 GND
A5 GND B5 GND
A6 GND B6 GND
A7 DDI B7 GND
A8 DCK B8 GND
A9 DMS B9 GND
A10 DDO B10 GND
A11 /DRST B11 PORT0
A12 /RESET B12 PORT1
A13 FLMD0 B13 VDD

Table 3.3.13

CEB-V850ES/FJ3·SJ3 Evaluation Board HardwareUser’s Manual

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3.3.14 The connector for FL-PR4, FL-PR5, MINICUBE2 (CN5)

It is a connector for connecting MINICUBE2 which is a target CPU debugger.
Moreover, it is as common as the connection connector of FL-PR4 or FL-PR5 which is a FLASH write-in
tool with a built-in CPU.

PinNo. Signal V850ES/FJ3
1 GND GND
2 _RESET _RESET
3 SI/RxD P40/SIB0 or P31/RXDD0
4 VDD EVDD
5 SO/TxD P41/SOB0 or P30/TXDD0
6 VPP N.C.
7 SCK P42/SCKB0
8 H/S PCM0
9 CLK N.C.
10 VDE N.C.
11 VDD2 N.C.
12 FLMD1 N.C.
13 RFU-1 N.C.
14 FLMD0 FLMD0
15 /RESETin N.C.
16 N.C. N.C.

Table 3.3.14

The "/RESETin" of a No. 15 pin is the reset signal passed to MINICUBE2. It is not used at the time of
FL-PR4 / FL-PR5 connection.
*After connection with CN5 and CN6 connector and separation check that a power supply is OFF, please
carry them out. There is a possibility that an evaluation board, a debugger, etc. may be damaged.

CEB-V850ES/FJ3·SJ3 Evaluation Board HardwareUser’s Manual

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3.3.15 The connector for CPU I/O pins check

The through hole for checking each terminal of CPU is arranged around a CPU chip.
The column from which the CPU pin number is "-" is not pulled out to the connector for a check.
(Each signal name has indicated the thing of FJ3)

(1) J1

No Signal name CPUpin No Signal name CPUpin
1 (GND) - 2 (GND) ­3 P10/INT9 3 4 P11/INT10 4
5 (GND) - 6 P00/… 6
7 P01/… 7 8 FLMD0 8
9 (GND) - 10 (GND) ­11 (GND) - 12 (GND) ­13 (GND) - 14 /RESET 14
15 (GND) - 16 (GND) ­17 P02/NMI 17 18 P03/INT0 18
19 P04/INT1/… 19 20 P05/INT2 20
21 P06/INT3/… 21 22 P40/… 22
23 P41/… 23 24 P42/… 24
25 P30/TXD0 25 26 P31/RXD0/… 26
27 P32/… 27 28 P33/… 28
29 P34/… 29 30 P35/… 30
31 P36/CTXD1 31 32 P37/CRTX1 32
33 (GND) - 34 (GND) ­35 P38/TXD2 35 36 P39/RXD2/… 36

Table 3.3.15 (1)

(2) J2

No Signal name CPUpin No Signal name CPUpin
1 P50/KR0/… 37 2 P51/KR1/… 38

3 P52/KR2/… 39 4 P53/KR3/… 40
5 P54/KR4/… 41 6 P55/KR5/… 42
7 P60/INT11 43 8 P61/INT12 44
9 P62/INT12/… 45 10 P63/SCKB3 46
11 P64/SCKB3 47 12 P65/CTXD2 48
13 P66/CRXD2 49 14 P67/CTXD3 50
15 P68/CRXD3 51 16 P69 52
17 P610/… 53 18 P611/… 54
19 P612/… 55 20 P613/… 56
21 P614 57 22 P615 58
23 P80/RXD3/… 59 24 P81/TXD3 60
25 P90/KR6/… 61 26 P91/KR7/… 62
27 P92/… 63 28 P93/… 64
29 P94/… 65 30 P95/… 66
31 P96/… 67 32 P97/SIB1/… 68
33 P98/SOB1/… 69 34 P99/SCKB1/.. 70
35 P910/SIB2/… 71 36 P911/SOB2/… 72

Table 3.3.15 (2)

CEB-V850ES/FJ3·SJ3 Evaluation Board HardwareUser’s Manual

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(3) J3

No Signal name CPUpin No Signal name CPUpin
1 P912/SCKB2/… 73 2 P913/INT4/… 74
3 P914/INT5/… 75 4 P915/INT6/… 76
5 PCD0 77 6 PCD1 78
7 PCD2 79 8 PCD3 80
9 PCS0/CS0 81 10 PCS1/CS1 82
11 PCS2/CS2 83 12 PCS3/CS3 84
13 PCM0/WAIT 85 14 PCM1/CLKO 86
15 PCM2/HLDAK 87 16 PCM3/HLDRQ 88
17 PCM4 89 18 PCM5 90
19 PCS4 91 20 PCS5 92
21 PCS6 93 22 PCS7 96
23 PCT0/WR0 95 24 PCT1/WR1 94
25 PCT2 97 26 PCT3 98
27 PCT4/RD 99 28 PCT5 100
29 PCT6/ASTB 101 30 PCT7 102
31 (GND) 103 32 (GND) 104
33 PDL0/AD0 105 34 PDL1/AD1 106
35 PDL2/AD2 107 36 PDL3/AD3 108

Table 3.3.15 (3)

(4) J4

No Signal name CPUpin No Signal name CPUpin
1 PDL4/AD4 109 2 PDL5/FLMD1/… 110
3 PDL6/AD6 111 4 PDL7/AD7 112
5 PDL8/AD8 113 6 PDL9/AD9 114
7 PDL10/AD10 115 8 PDL11/AD11 116
9 PDL12/AD12 117 10 PDL13/AD13 118
11 PDL14/AD14 119 12 PDL15/AD15 120
13 P127/ANI23 121 14 P126/ANI22 122
15 P125/ANI21 123 16 P124/ANI20 124
17 P123/ANI19 125 18 P122/ANI18 126
19 P121/ANI17 127 20 P120/ANI16 128
21 P715/ANI15 129 22 P714/ANI14 130
23 P713/ANI13 131 24 P712/ANI12 132
25 P711/ANI11 133 26 P713/ANI10 134
27 P79/ANI9 135 28 P78/ANI8 136
29 P77/ANI7 137 30 P76/ANI6 138
31 P75/ANI5 139 32 P74/ANI4 140
33 P73/ANI3 141 34 P72/ANI2 142
35 P71/ANI1 143 36 P70/ANI0 144

Table 3.3.15 (4)

CEB-V850ES/FJ3·SJ3 Evaluation Board HardwareUser’s Manual

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3.4 Memory map

(1) V850ES/FJ3 ‘F3380

Built-in FLASH 512KB, Built-in RAM32KB

[80KB]

External memory

area
[8MB]
(CS3)

External memory

area
[2MB]
(CS1)

[2MB]
(CS0)

x3FFFFFFH

x3FEC000H
x3FEBFFFH

x0FFFFFFH

x1000000H

x0800000H

x07FFFFFH

x0200000H

x01FFFFFH

x0000000H

External memory

area
[4MB]
(CS2)

x03FFFFFH

x0400000H

Prohibition of use

Built-in ROM area

(1MB)

External memory

area

(1MB)

x0000000H

x0100000H

x01FFFFFH

Area for AFCAN

(12KB)

Prohibition of use

Built-in RAM area

(32KB)

Built-in peripheral

I/O area

(4KB)

x3FEC000H

x3FEF000H

x3FF7000H

x3FFF000H

x3FFFFFFH

Figure 3.4 (1)

CEB-V850ES/FJ3·SJ3 Evaluation Board HardwareUser’s Manual

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(2) V850ES/SJ3 ‘F3368

Built-in FLASH 1024kB, Built-in RAM60kB

[80KB]

External memory

area
[8MB]
(CS3)

External memory

area
[2MB]
(CS1)

[2MB]
(CS0)

x3FFFFFFH

x3FEC000H
x3FEBFFFH

x0FFFFFFH

x1000000H

x0800000H

x07FFFFFH

x0200000H

x01FFFFFH

x0000000H

External memory

area
[4MB]
(CS2)

x03FFFFFH

x0400000H

Prohibition of use

Built-in ROM area

(1MB)

External memory

area

(1MB)

x0000000H

x0100000H

x01FFFFFH

Prohibition of use

Built-in RAM area

(60KB)

Built-in peripheral

I/O area

(4KB)

x3FEC000H

x3FF0000H

x3FFF000H

x3FFFFFFH

Area for AFCAN

(12KB)

x3FEF000H

Figure 3.4 (2)

CEB-V850ES/FJ3·SJ3 Evaluation Board HardwareUser’s Manual

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3.5 Notes at the time of user circuitry

In adding and connecting a user circuit at an evaluation board, please consider the following notes to the
design and manufacture which cannot receive influence of a noise etc. in reference easily.
Moreover, there are restrictions matters, such as drive current, in each terminal. Please refer to these notes
and a correspondence CPU user’s manual, and use it within rating.

3.5.1 Consumption current

Since consumption current is generating internal logic voltage from external 12V power supply, it
recommends combining this board and an extension board and using it below 0.1A. (The consumption
current in a main part simple substance is about 0.05A.)
When the current exceeding 0.1A is required, please use a heat sink for U13 as much as possible.
When the current exceeding 0.2A is required, please be sure to use a heat sink. If the current which
exceeds 0.2A without a heat sink is sent, U13 generates heat and there is danger, such as a burn and a
fire.
Moreover, power supply supply stops by the shutdown function which U13 has.
The AC adaptor more than power supply capacity 12v, 0.5A is enclosed.

3.5.2 I/O signals

Each signal line currently outputted to J3 and J4 is outputted to the connector, after pulling up by 47kΩ.
Pay attention to pattern damage, pattern bridge, etc., and implement measures as needed, such as
removing mounted parts.
For the specifications of each pin and the electrical specifications, refer to the correspondence CPU user ’s
manual.

CEB-V850ES/FJ3·SJ3 Evaluation Board HardwareUser’s Manual

31

3.6 A jumper setup at the time of shipment

A setup of the jumper at the time of shipment is as in the following tables.



No State Function

1-2 OPEN

JP1

3-4 OPEN

CAN0(FJ3) CAN1(SJ3)
no terminator

1-2 OPEN

JP2

3-4 OPEN

CAN1(FJ3) CAN0(SJ3)

no terminator
JP3 2-3 SHORT LIN0 master
JP4 1-2 SHORT LIN0 master
JP5 2-3 SHORT LIN1 master
JP6 1-2 SHORT LIN1 master
JP7 1-2 SHORT Reset normal use
JP8 1-2 SHORT RXD0,USB(UART) use

Table 3.6

CEB-V850ES/FJ3·SJ3 Evaluation Board HardwareUser’s Manual

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4. CAN expansion board

The CAN expansion board (CAN-EXT BOARD) is a board for CAN interface expansion developed for the
CEB-V850ES/FJ2.
(As standard, it is not attached. Moreover, extension of CAN I/F cannot be performed in CEB-V850ES/SJ3.)

4.1 Specifications

The CAN expansion board, which expands the number of CAN channels by 2 channels, is used connected
to the J5 and J6 connectors of the CEB-V850ES/FJ3.

4.2 Block diagram

P65/CTXD2

P66/ CRXD2
P60

P67

/CTXD 3

P68/CRXD3

P61

CAN expansion board (CAN-EXT BOARD) block diagram

connector

Ｊ 5, J 6

V850ES /FJ 3

Evaluation CPU board

CAN

connector

CAN

connector

CAN te r min atio n

Resistan ce

( connect /open)

enable

CAN

trans c eiver

IC

CAN

IC

JP

JP

connector

J3, J4

CAN expansion board

mating

)

transceiver

CAN te rm ina tion

Resistan ce

( connect/open)

enable

Figure 4.2

CEB-V850ES/FJ3·SJ3 Evaluation Board HardwareUser’s Manual

33

4.3 Board size

J3

J4

65 .00

90. 00

CAN circuit

(

CAN2＆ CAN

3)

Expansion connector（30pin

）

CAN connector [

CAN

2

]

(

9pin- DSUB

)

CAN connector

[

CAN

3

]

(

9pin- DSUB

)

Expansion connector

（

30pin

）

10.00

10.00

10 .00

Figure 4.3

CEB-V850ES/FJ3·SJ3 Evaluation Board HardwareUser’s Manual

34

4.4 External connectors

Table of Connection connectors (J3, J4)

Table 4.4

* J3 is connected to J5 of CEB-V850ES/FJ3.
* J4 is connected to J6 of CEB-V850ES/FJ3.

J3 J4

Pin

No.

Signal Name

Usage Type with CAN

Expansion Board

Pin

No.

Signal Name

Usage Type with CAN

Expansion Board
1 P00 N.C 1 P98/SOB1(A8) N.C
2 P10/INTP9 N.C 2 P912/_SCKB2(A12) N.C
3 P01 N.C 3 P99/_SCKB1(A9) N.C
4 P11/INTP10 N.C 4 P913/INTP4(A13) N.C
5 P03/INTP0 N.C 5 P910/SIB2(A10) N.C
6 P32/ASCKA0 N.C 6 P914/INTP5(A14) N.C
7 P04/INTP1 N.C 7 P911/SOB2(A11) N.C
8 P35 N.C 8 P915/INTP6(A15) N.C
9 P06/INTP3 N.C 9 PCS0/_CS0 N.C
10 P41/SOB0 N.C 10 PCM0/_WAIT N.C
11 P40/SIB0 N.C 11 PCS1/_CS1 N.C
12 P42/_SCKB0 N.C 12 P36(IETX0) N.C
13 P50/KR0 N.C 13 PCS2/_CS2 N.C
14 P53/KR3/DDO N.C 14 P37(IERX0) N.C
15 P51/KR1 N.C 15 PCS3/_CS3 N.C
16 P54/KR4/DCK N.C 16 PCT5 N.C
17 P52/KR2/DDI N.C 17 P73/ANI3 N.C
18 P55/KR5/DMS N.C 18 PCT7 N.C
19 P90/TXDA1(A0) N.C 19 P72/ANI2 N.C
20 P95(A5) N.C 20 P60/INTP11 Expansion CAN(CAN2)RS
21 P91/RXDA1(A1) N.C 21 P61/INTP12 Expansion CAN(CAN3)RS
22 P96(A6) N.C 22 P70/ANI0 N.C
23 P92(A2) N.C 23 P71/ANI1 N.C
24 P97/SIB1(A7) N.C 24 P65/CTXD2 Expansion CAN(CAN2)TXD
25 P93(A3) N.C 25 P66/CRXD2 Expansion CAN(CAN2)RXD
26 CPOW N.C 26

+5V +5V

27 P94(A4) N.C 27 P67/CTXD3 Expansion CAN(CAN3)TXD
28 _RESET N.C 28 P68/CRXD3 Expansion CAN(CAN3)RXD
29

GND

N.C 29 +12V N.C

30

GND GND

30

GND GND

CEB-V850ES/FJ3·SJ3 Evaluation Board HardwareUser’s Manual

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4.5 Evaluation board mating

The following figure illustrates mating of the V850ES/FJ3 evaluation CPU board and expansion board.

DIPSW

《

Longitudinal View

》

J6 connector

CAN connector

CAN expansion board

MINICUBE connector

FL-PR4/FL-PR5/MINICUBE2 connector

Expansion CAN connector

Expansion CAN connector

Power supply jack

《

Transversal View

》

CAN expansion board

FJ3 Evaluation CPU board

FJ3 Evaluation CPU board

DIPSW

J6 J5

J4 J3

Figure 4.5

CEB-V850ES/FJ3·SJ3 Evaluation Board HardwareUser’s Manual

36

Revision History

Edition Description Page(s)
The 1.0 st Apr. 2007 The first-edition issue
The 1.1 st Sep. 2007 The 1.1 st edition issue