Page 1
SECTION
9
9.0
GENERAL
This
section
which
9.1
MODEL
The
Model
a
16
key
messages
addresses
are
options
2115
2115
membrane-type
and
data
Predetermined
‘The
13
function
_ 9 Blood
the
available
DATA
Data
Entry
keypad
are
displayed
Messages
keys
are
capable
Pressure
e
Vaginal
©
Position
©
Temperature
e
Rupture
®
Oxytocin
OPTIONS
two
external
for
use
with
ENTRY
Exam
Change
of
SYSTEM
System
is
designed
on a 16-character
of
printing
Membrane
Data
the
an
option
to
(ROM)
Entry
115
Fetal
that
print
the
following
—
THEORY
Systems
Monitor.
plugs
messages
LCD
on
predetermined
(2115
into
and
the
front
and
the
data
OF
OPERATION
2116)
back
(3103)
on
the
of
the
keypad
messages:
and
the
of
strip
chart
two
the
Model
of
before
Recorder
115
Fetal
the
Model
being
printed.
Boards
Monitor.
115
Fetal
(6808
Monitor.
and
This
6666)
option
The
is
Ta
addition,
Model
The
Model
®
Pulse
e
pH
e
IV
e
Respiration
e
Fetal
*
e
an
event
2115
Subassemblies
2115
Data
@
®
©
@
@
Movement
Oxygen
Medication
mark
can
Entry
System
Processor
Keypad
Auxiliary
LCD
Main
Board
Composite
Board
Display
Cable
(FM)
also
be
printed.
consists
(5809)
(S840A)
(5983A)
Unit
(5958A)
Assembly
(5959A)
of
.
the
following
five
subassemblies:
Processor
All
data
and
This
includes
the
processor
Description
control
operations
communications
board
also
are
between
contains
and
performed
the
keypad
executes
by
the
the
following
hardware
and
Model
and
firmware
115
Monitor
test
routines.
(ROM)
and
the
located
keypad
on
and
the
the
5809
LCD
Processor
display.
In
Board.
addition,
Page 2
After
1.
Setting
2.
Loading
3.
Clearing
power-up,
the
display
the
the
the
system
mode.
special
display
display.
processor
characters
(U1)
initializes
into
the
the
display
LCD
RAM.
display
by:
Power-Up
After
completing
on
the
display.
Jine
is a logic
After
the
1.
The
routine
message
2.
The
2115
and 5 of
3.
After
test
message.
4.
The
2115
A
logic
low
an
"ERROR
the
Model
mainline
not
go
low
ing
the
END
sages
sent
Test
Routine
these
After
low,
the
BUSY
line
tests
its
(00H)
to
then
waits
U2).
detecting
115
routine.
tests
on
this
37”
and
message
the
the
line
reinserted
“ERROR
following
OF
STRING
to
the
115
operations,
displaying
Data
is
sensed
system
the
for
Entry
115.
the
this
System
high,
RAM
115
acknowledge,
status
of
the
INVLD
indicates
the
60 ps
must
that
and
enters a halted
into
its
2”
indicates
delay,
(EOS)
message
be
terminated
the
processor
message,
remains
the
following
and
the
to
acknowledge
the
2115
line
the
message
socket.
the
the
Data
(10H).
with
begins a power-up
the
processor
in a loop
sequence
link
to
the
Model
the
message.
waits
approximately
(pin
39
of
U1).
sent
was
state.
To
clear
(NOTE:
failure
the
of
Entry
After
EOS
“ERROR
the
System
sending
byte
test
samples
waiting
the
for
occurs:
115
Fetal
The
60
determined
this
error,
1°’
indicates
UI
RAM
which
assumes
the
EOS
to
indicate
routine.
BUSY
this
line
Monitor.
115
accomplishes
jas
to
allow
to
be
incorrect.
the
Model
the
requires
the
correct
message
that
the
This
routine
line
(pin 6 of
to
go
high.
The
link
the
Model
If
2115
must
failure
its
replacement.)
message
the
2115
transfer
is
places
U1)
from
test
is
initiated
this
by
lowering
115
time
this
happens,
be
unplugged
of
the
115
was
received
exits
the
complete.)
the
to
to
accept
If
test
*“WAIT”?
the
Model
by
sending a test
the
IBF
process
the
2115
from
data
the
INVLD
and
responds
routine.
message
115. If
line
(pins
the
displays
the
back
during
line
by issu-
(All
mes-
this
4
of
the
does
Functional
Upon
successful
is
operational.
of
the
program,
the
BUSY
line.
of
both
the
Entry
System
As
long
as
routine
9.2
MODEL
The
Model
The
keyboard
mation
dures,
entry
or
Model
The
Model
is
exited
or
the
and
printing.
2116
Description
exit
from
Once
in
the
the
2115
If
the
BUSY
[Mark
Enter]
is
capable
the
BUSY
and
2116
2116
consists
FIXED
drug-related
the
DATA
Data
line
Entry
of
TEXT
of
“READY”
information.
Subassemblies
2116
Data
Entry
©
Processor
the
test
“READY”
scans
the
line
key
and
sending
remains
ENTRY
System
53
keys
MODE
System
Board
routine,
state
keyboard
is
low,
the
the
BUSY
only
event
low
the
display
SYSTEM
is
designed
by
which
for
easy
Ali
data
consists
(6180A)
the
Model
the
system
looking
BUSY
line
while
marks
2115
remains
appears.
to
the
user
entry
appears
of
the
2115
displays a “READY”
processor
for a keypress.
routine
is
called.
displaying
to
the
in
print
messages
can
employ
of
commonly
115
the
the
(the
BUSY
the
used
on a 40-character
following
four
”
begins
the
scan
If
no
keypress
In
the
BUSY
event
and
FREE
"WAIT"
state.
data
medical
marks
When
on
the
TEXT
LCD.at
message.
are
terms,
the
subassemblies:
message
portion
of
is
detected,
routine,
During
printed
the
BUSY
strip
chart
MODE
for
patient
top
of
to
he
user
the
software.
the
routine
the
processor
the
only
if
the
line
is
of
the
Model
entering
parameters,
the
keyboard
to
indicate
the
During
tests
the
monitors
BUSY
routine
115
recorder
brought
high,
115
Fetal
comprehensive
medical
for
review
system
this
section
status
of
the status
the
Data
is
on).
the
BUSY
Monitor.
infor-
proce-
prior
to
9-2
e
Keyboard
©
LCD
e
Main
Composite
Display
Cable
Unit
Assembly
(6928A
(7064A)
(70694)
A)
Page 3
Processor
The
8749H
for the
1.
Scanning
2.
Communicating
3.
Communicating
Three
ports
plexor
two
VAC
Description
6180
PCB
is a single
following
additional
available
senses
places:
needed
contains
the
to
which
Ul,
an
to
drive
the
circuitry
chip
containing a processor,
three
maior
functions:
53
microkey
with
with
chips
the
8749; a 74LS138
key
ICL7660
the
keyboard
the
40-character
the
Model
support
the
is
depressed.
voltage
LCD
backlight.
required
for
LCD
115
Fetal
8749H
in its
decoder
In
addition
converter
to
control
ROM, RAM,
any
key
display.
Monitor.
tasks:
serves
to
provides
the
functions
and
closures.
the
74LS157
as
the
driver
these chips
the — 5 V
of
VO
ports
quad
for
a,
74LS05
necessary
the
2116.
within a 40-pin
dual-input
scanning
hex
inverter
to
bias
the
It
is
an
8749H
DIP.
multiplexor
keyboard;
package
the
LCD
display
processor
This
expands
based
processor
the
and a 74LS151
is
used
to
provide
and
U7
system.
is
responsible
number
8-input
inverters
provides
The
of
I/O
multi-
the
120
in
Functional
The
RESET
ing
this
reset
line
signal
from
Description
with
After a RESET
special
Once
tests.
processor
Data
2.
NOTE:
1.
3.
4
.
5.
A5
The
The
After
(33
If
characters
these
operations
It
begins
waits
Entry
System
is
placed
nibble
keyboard
the
pin 5 or
no
error
All
low
signal
on
pin 3 of
U2
(pins
the
115, the
has
occurred,
into
by
testing
in a loop
and
on
the
is
strobed
waits
recorder
is
byte
has
U3
pin
detected,
transmissions
nibble.
J3
is
an
active
12, 13)
the
display,
have
the
for
the
data
into
for
the
acknowleged
8749H
the
been
BUSY/
the
line
Model
lines
the
recorder
an
active
uses a 1 F capacitor
2116
begins
and
clearing
completed,
line
to
go
115
Monitor
to
the
115
by
3).
steps 1 through 4 are
to
the
monitor
high
low
reset
its
power
the
the
8749H
from
the
inactive.
as
115
(U4,
pins
toggling
to
the
the
acknowledge
byte
the
repeated
are
.
signal
coming
signal
is
(C7)
up
sequence
display.
(U4)
places a BUSY
115 (pin 4 of
Once
the
transition
follows.
21,
22, 23,
STB/line
the
byte
ERROR/
line
with
done
by
transmitting
from a port
provided
to
J3)
to
the
provide a power-up
by
setting
through
multiplexor
occurs,
and
24
or
J3
(U4
pin 38
or
by
lowering
is
checked
the
following
sequence:
the
byte
chip
on
RESET/
the
display
message
the
processor
pins
9,
J3
pin
7).
the
IBF
to
ensure
at
two
the
recorder
input
reset
mode
in
the
U3
(pin
10, 11,
line
(J3
that
the
AH,
1H,
nibbles:
PCB
of
the
8749H.
signal.
for
LCD
and
6).
tests
the
and
12).
pin 6 or
byte
was
0H.
high
of
the
the
LCD,
begins
If
this
link
U3
pin
received
nibble
115.
By
In
addition
`
loading
its
power
line
is
active
between
3).
correctly
first,
then
invert-
to
the
up
the
the
2116
the
6.
If
no
errors
occur
for
approximately 2 seconds.
the
display.
7.
If
an
error
is
dectected,
loop
preventing
cursor
at
the
left
a
scan
code
(0 to
of
the 8 keyboard
the
other
outputs
by
sequencing
state
of
scanned.
line
(pin
by
the
processor
ENTER
the
115
is
resent.
the
keyboard
If a key
13
of
key
is
and
the
If
three
through
U3).
used
during
any
further
margin
7)
on
the
scan
lines
if
multiple
the 8 return
return
is
detected
The
to
determine
to
send
ERROR/
failures
the
link
test
After
the
WAIT
message
functioning.
and
the
keyboard
address
(U5
pins
keys
lines
while
pins
happen
can
scanning,
combination
the
appropriate
the
message
line
monitored
of a single
the
WAIT
the 2 second
is
replaced
Once
the
is
ready
of
US
(pins
7,
and
9-15).
to
be
depressed.
lines
using
multiplexor
be
sensed
the
of
the
depressed
action.
to
the
monitor.
to
ensure
message
are
message
delay,
is
this
message
removed
by a LINK
power-up
to
1,
Diodes
on pin 5 of
state
test
process
2,
and
D1 - D8
Once
U6.
U6.
of
the
shift
key
and
has
key
3).
the
By
This
the
This
After a message
Once
this
the
message
is
detected. a MESSAGE
from
the
display
is
removed
ERROR
message
successfully
depressions.
code
are
scan
addressing
scanning
keys
is
state
has
key
is
sent
correctly.
The
is
decoded
used
to
prevent
line
has
U6
process
also
checked
of
the
SHIFT/line
been
built by a series
depressed,
ERROR
and a LINK
and a cursor
and
the
keyboard
been
completed
process
been
scans
by
U5
one
output
selected,
with a code
is
repeated
by
reading
provides
the
message
If
an
error
is
is
displayed
OK
message
appears
to
at
the
left
is
placed
the
display
the
keyboard
shows
produce a logic O on
logic 0 from
depressed
on
pins
until
the
of
key
is
detected,
and
keys
9,
10,
and
all
lines
state
of
the
the
unique
depressions,
sent
in
nibble
the
entire
the
message
appears
margin
of
into a tight
the
by
placing
one
affecting
are
sensed
11,
the
have been
SHIFT/
code
used
the
form
to
message
aborted.
9-
Page 4
Throughout
from
the
keyboard,
H
the
BUSY/
except
for
běcause
The
display
J3)
pressed
The
and a menu
listed
all
MARK
is
is
lowered
is
Test
in
TABLE
cleared
restored.
switch
all
scanning,
and
line
is
detected
detection
printing
IN/
of
of
lines
(pin
and
for
those 2 seconds.
is
used
tests
appears
9-1.
Test
No.
a
2
3
4
5
the
14
an
three
the
are
of
EVENT
to
additional
TEST
signal
low,
the
MARK
U3)
activate
used,
in
the
IN/
or
goes
MARKER
After
the
display.
lines
from
pushbutton
keyboard
line.
This
the
recorder
low
when
the
message
the
two
internal
Description
ROM
A
RAM
A
tests of
The
tests
Test
checksum
Test
test
of
Display
A
pattern
are
working
Link
Test
A
test
pattern
the
connection.
Exit
This
selection
are
monitored.
displays
line
goes
has
been
user
depresses
is
seconds
the
are
selected
is
performed
all
RAM
Test
of
characters
and
all
similar
terminates
These
SW1.
the
WAIT
low
whenever
turned
the
displayed
has
elapsed,
keyboard.
by
on a section
is
performed
is
displayed
data
lines
to
the
the
are
the
BUSY/line
message
off.
for 2 seconds.
When
pressing
power-up
test
MARK
any
to
to
the
mode
the
in
the
115
cannot
key
message
the
pushbutton
the
number
of
the
verify
that
providing
display
link
and returns
from
display
on
Also,
test
and
accept
the
keyboard.
the
MARK/line
displayed
is
of
the
ROM
to
it
is
functioning
verification
are
functioning
is
sent
the
the
115,
the
stops
all
keyboard
any
more
When
prior
to
the
depressed,
desired
ensure
to
keyboard
its
properly.
that
properly.
the
115
test.
integrity.
all
Fetal
MARK
messages
this
happens,
to
the
115
MARK
the
display
The
tests
dots
in
the
Monitor
to
functional
IN/line
scanning
either
the
(pin 8 of
being
de-
is
cleared
are
display
to
check
mode.
9.3
RECORDER
The
Recorder
nal
computer.
RS-232C
Principle
U16
and
ciated
components.
$251
USART
The
heart
ing
functions:
1.
Converts
ing
of 8 serial
2.
Converts
quires 1 start
switches 3 and
BOARD
Board
It
also
Hardware
RS-232C
U18.
Additionally,
of
the
interface
8-bit
parallel
bits
an
8-bit
bit, a minimum
(6808
or 6666)
includes
Hardware
is
data
(LSB
stream
4.
W/RS-232C
contains
an
intemal
includes
support
the
on
first),
(from
PROM
hardware
8251A
Programmable
the
CPU
one
or
the
RxD
of 1
stop
SELF-TESTS — 2116
TABLE
OPTION
hardware
self-test
data
zero
port,
bit
and
(6808
and
capability.
U9,
USART
includes
parity
regulators,
Communication
bus
to a serial
bits, 1 start
pin
3)
either
or
firmware
U23,
to 8 parallel
zero, 1 even
KEYBOARD
9-1
6666)
RS-232C
U30
bit
stream
bit,
to
interface
and
Interface
(which
and
is
data
bits
parity
the
Model
compatible
U31,
3-state
(USART).
is
conveyed
programmed
which
are
bit,
or 1 odd
115
gates
U24,
buffer
This
to
by
firmware
strobed
parity
Fetal
U2S,
U15,
device
the
TxD
onto
bit)
as
Monitor
and
to
the
with
and
counters
their
asso-
performs
port,
pin
send 2 stop
CPU
data
programmed
an
exter-
the
follow-
19)
consist-
bits.
bus
by
(re-
SP2,
94
Page 5
3.
Sets
4.
Detects
the
5.
Generates
the
baud
framing
data.
and
rate
as
and
accepts
determined
overrun
errors
RS-232C
by
switches 1 through
(and
parity
errors
signals
used
in
modem
10
of
SP1
if
parity-error
control
and
(both
transmit
detection
similar
and
receive).
is
enabled)
applications
which
(OTR,
causes
RTS,
DSR,
the
CPU
and
to
ignore
CTS).
USART
Before
rate,
consisting
C/D1,
Most
These
During
used
buffer.
Initialization
any
data
character
of a Reset,
WRO
of
the
parameters
operation,
to
convey a status
(Before
appropriate
framing
In
Interface.
ates a RST
at
RS-232C
Salient
error.
the
Transmit/Receive
When
5.5
top
priority)
Logic
features
and
Control
transfer
length,
between
number
followed
(U23,
pins
12
and
initialization
the
flag
bit
data
are
controlled
in
addition
byte
CPU
can
set
indicating
to
Mode,
the
USART
interrupt
and
routine
accept
the
Interface
of
the
RS-232C
the
CPU
of
stop
bits,
by
writes
10,
respectively).
is
fixed
in
the
by
the
appropriate
to
transferring
the
CPU
(C/D1,
write a data
the
receive
which
that
115
buffer
byte
the
must
causes
byte.
Specifications
and
the
and
of
command
firmware
8251A
similar
can
parameters.
words
with
switches
patient
buffer
RDO).
to
the
is
also
data
One
USART,
empty).
be
able
from
of
to
contains a received
the
CPU
to
(ELA)
for
interfacing
begin,
on
the
the
exceptions
which
the
the
bits
any
previous
Other
bits
receive
byte,
service
the
the
USART
This
is
‘‘AD”’
are
sampled
CPU
to
in
this
are
serial
it
drives
interrupt
flags
must
accomplished
bus; a command
of
parity
by the
the
USART
byte
indicates
byte
must
indicating
data
from
the
RxRDY
(on a priority
data-processing
be
initialized
by
enable,
parity
CPU
(C/D1,
the
have
been
parity
the
external
line
equipment
the
CPU
write
to
selection,
on
power-up
RDO),
status
sent
error,
computer
high
basis
with
are
in
regards
to
the
baud-
through a sequence
the
USART
via
the
*““AD””
of
the
out
serially
overrun
(pin
14,
the
as
follows:
indicated
and
baud-rate.
U15.
bus
USART
and
error,
via the
RS-232C
U23).This
RST
7.7
is
transmit
the
and
interrupt
by
also
initi-
1.
Voltage
2.
Levels
3.
Logic
4.
Output
The
Gates
RS-232C
U24
330-pF
supplies
sistors
device
accepts
USART
There
1.
2.
magnitudes
are
transitions
devices
USART
U24
devices.
is a type
capacitor
required
disconnect
rating
the
Clocks
are
two
Synchronization
is
tied
to
3.072
MHz).
signals
Clock
U16,
U17
positive
must
is a TTL
and
U25
MC1488
ensures
by
the
if
the
RS-232C
clock
pin
37
to
and
for
logic
for
logic 0 and
must
not
be
able
device
along
with
line
the
the
gates
gates
during
Vec
and
signal
functions
with
the
(CLK
OUT)
the
set
Ui8.
levels
must
negative
exceed a slew
to
withstand a short
and
is
not
directly
regulators
driver
with
approximately
below
is
rate
slew
to
interface
power
off.
Vee
inputs
are
levels
from
the
required
by
microprocessor
of
US,
and
the
of
rate
baud
be
between 5 and
for
logic
rate
of
30
compatible
U31
and
U31
30-V/microsecond
the
with
the
RS-232,
This
is
connected
external
the
USART:
clock
computer
for
performs
transmitted
15 V for a 3000
1.
V/ps.
between
serve
300
any
with
as
ohms
of
the
equipment
the
interface
of
output
tolerance.
RS-232C
necessary
levels.
since a short
to a low-impedance
and
converts
data
and
command
this
function
and
(CLK
received
data
to
7000-ohm
interconnecting-cable
which
satisfies
between
resistance.
Regulators
Additionally,
of
all
four
during
power
them
to
TTL
transfer
OUT
streams.
is
via
1/2
These
the
the
TTL
This
resistance
the
gate
off.
levels
the
data
the
frequency
functions
load.
conductors.
foregoing
levels
U30
regulators
outputs
U25,
for
bus.
of
in
combination
U31
and
to + 15 V
an
MC1489
the
USART.
Pin
at
pin
performed
are
specifications.
the
USART
and
with
+
exceeds
Line
(CLK)
US
the
output
the
Receiver
of
023
giving
U2,
by
tran-
provide
internal
20
1,
the
12V
baud
The
these
rate
inputs
by
set
is
are
programmed
the
clock
appearing
signal
internally
as
RXC
the
at
divide-by-16
counters.
and
TXC
inputs
(pins
25
and
9)
of
U23.
During
initialization,
Page 6
The
RXC
and
a
divide-by-10
The
output
frequency
TXC
clock
counter
signals
which
from
drives
U18
are
also
the
(which
BAUD
9600
4800
2400
1200
derived
U18
“CPA”
is a dual
RATE
from
3.072
clock
binary
MHz
inpuz
counter)
to
via the
at
307.2
U23
divider
kHz.
depends
OUTPUT
chain
consisting
on
the
baud
FREQUENCY
153.6
kHz
76.8
kHz
38.4
kHz
19.2
kHz
rate
selected
(U18)
of
U16
and
by
U18.
SPI
U16
as
follows:
is
The
to
4.8
for
300
Heart
the
19.2
kHz.
the
desired
Baud
rate
U6
PIA PB1
kHz
signal
The
baud
Detect
and
UA
serves
selected
signal
rate.
data
are
port
(pin
as
the
not
30).
clock
is
then
sent
This
routed
at
the
port
COUNTER
for
the
300
is
driven
other
to
U23
band
high
OUTPUT
TABLE
binary
where
rate.
Selection
if
counter
the
SP1
is
FREQUENCY
9-2
in
U18.
intemal
in
divide-by-16
of
the
the
300
300
baud
For
the
rate
position.
300
counters
is
detected
baud
rate,
this
produce
by
the
microprocessor
signal
the
correct
is
divided
frequency
(U5)
by
via
4
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