Corelis PCIe-1149.1 User Manual

CORELIS

PCIe-1149.1

High-Speed PCI Express Bus

Boundary-Scan Controller

User’s Manual

Document Part Number: 70369 REV B

12607 Hidden Creek Way Cerritos, CA 90703-2146

Telephone: (562) 926-6727 • Fax: (562) 404-6196

Preface

PRINTING HISTORY

New editions are complete revisions of the manual. Update packages, which are issued between editions, contain additional and replacement pages to be merged into the manual by the customer. The dates on the title page change only when a new edition is published.

A software code may be printed before the date; this indicates the version of the software product at the time the manual or update was issued. Many product updates and fixes do not require manual changes and, conversely, manual corrections may be done without accompanying product changes. Therefore, do not expect a one to one correspondence between product updates and manual updates.

Revision A, September 2006 Revision B, November 2007

GENERAL NOTICE

Information contained in this document is subject to change without notice. CORELIS shall not be liable for errors contained herein for incidental or consequential damages in connection with the furnishing, performance, or use of material contained in this manual. This document contains proprietary information, which is protected by copyright. All rights reserved. No part of this document may be reproduced or translated to other languages without the prior written consent of CORELIS.

CORELIS assumes no responsibility for the use of or reliability of its software on equipment that is not furnished by CORELIS.

ENVIRONMENTAL NOTICE

This product must be disposed of in accordance with the WEEE directive.

TRADEMARK NOTICE

Windows is a registered trademark of Microsoft Corporation.

Other products and services named in this book are trademarks or registered trademarks of their respective companies. All trademarks and registered trademarks in this book are the property of their respective holders.

PRODUCT WARRANTY

This CORELIS product has a warranty against defects in material and workmanship for a period of 90 days from date of shipment. During the warranty period, CORELIS will, at its option, either repair or replace products that prove to be defective.

For warranty service or repair, this product must be returned to a service facility designated by CORELIS. Outside CORELIS service travel areas, warranty service will be performed at the Buyer's facility only upon CORELIS' prior agreement and Buyer shall pay CORELIS' round trip travel expenses.

For products returned to CORELIS for warranty service, the Buyer shall prepay shipping charges to CORELIS and CORELIS shall pay shipping charges to return the product to the Buyer. However, the Buyer shall pay all shipping charges, duties, and taxes for products returned to CORELIS from another country.

CORELIS warrants that its software and firmware designated by CORELIS for use with an instrument will execute its programming instructions when properly installed on that instrument. CORELIS does not warrant that the operation of the instrument, software, or firmware will be uninterrupted or error-free.

The foregoing warranty shall not apply to defects resulting from improper or inadequate maintenance by the Buyer, Buyer-supplied software or interfacing, unauthorized modification or misuse, operation outside of the environmental specifications for the product, or improper site preparation or maintenance.

NO OTHER WARRANTY IS EXPRESSED OR IMPLIED. CORELIS SPECIFICALLY DISCLAIMS THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.

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THE REMEDIES CONTAINED HEREIN ARE THE CUSTOMER'S SOLE AND EXCLUSIVE REMEDIES. CORELIS SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, WHETHER BASED ON CONTRACT, TORT, OR ANY OTHER LEGAL THEORY.

Product maintenance agreements and other customer assistance agreements are available for Corelis products. For assistance, contact your nearest Corelis Sales and Service Office.

RETURN POLICY

No items returned to CORELIS for warranty, service, or any other reason shall be accepted unless first authorized by CORELIS, either direct or through its authorized sales representatives. All returned items must be shipped pre-paid and clearly display a Returned Merchandise Authorization (RMA) number on the shipping carton. Freight collect items will NOT be accepted. Customers or authorized sales representatives must first contact CORELIS with notice of request for return of merchandise. RMA's can only originate from CORELIS. If authorization is granted, an RMA number will be forwarded to the customer either directly or through its authorized sales representative.

Table of Contents

CHAPTER 1 PRODUCT OVERVIEW..........................................................................1-1

Introduction................................................................................................................................................1-1

What Is IEEE Standard 1149.1? ................................................................................................................1-2

Features of the PCIe-1149.1 ......................................................................................................................1-3

Adjustable Voltage Interfaces................................................................................................................................ 1-4

Parallel Input/Output Ports.................................................................................................................................... 1-4

PCI Express Interface............................................................................................................................................1-4

Programmable Clocks............................................................................................................................................1-5

Features of the ScanTAP-4........................................................................................................................1-5

PCIe-1149.1 Specifications........................................................................................................................1-6

ScanTAP-4 Specifications .........................................................................................................................1-7

CHAPTER 2 PCIE-1149.1 INSTALLATION ................................................................2-1

Software Installation First! ........................................................................................................................2-2

Hardware Installation.................................................................................................................................2-2

Hardware Installation.................................................................................................................................2-3

CHAPTER 3 CONNECTING TO THE TARGET..........................................................3-1

Connecting to the Target............................................................................................................................3-1

20-Pin ScanTAP Connector.......................................................................................................................3-3

68-pin Host Connector...............................................................................................................................3-4

PCIe-1149.1 Parallel I/O Connectors.........................................................................................................3-5

CHAPTER 4 USING PCIE-1149.1 WITH SCANPLUS ................................................4-1

Hardware Setup..........................................................................................................................................4-1

Using PCIe-1149.1 with ScanPlus Tools...................................................................................................4-1

ScanTAP-4 TAP Configuration.................................................................................................................4-5

TAP Configuration - Method 1..................................................................................................................4-6

TAP Configuration - Method 2..................................................................................................................4-8

TAP Configuration - Method 3..................................................................................................................4-9

Gang Programming with ScanPlus Runner .............................................................................................4-13

Gang Programming with ScanPlus Flash Programmer............................................................................4-20

CHAPTER 5 THIRD PARTY APPLICATION INTERFACE.........................................5-1

Using PCIe-1149.1 with ScanPlus Runner Command-line.......................................................................5-1

APPENDIX A RECOMMENDED TARGET CONNECTORS ..........................................1

10-pin TAP Connector..................................................................................................................................1

Flash Programming TAP Connector.............................................................................................................4

20-pin TAP Connector..................................................................................................................................7

iii

APPENDIX B SELF TEST UTILITY SOFTWARE.......................................................... 1

Self-Test........................................................................................................................................................1

Table of Figures

Figure 1-1. The Corelis PCIe-1149.1 Boundary-Scan Controller ........................................................................... 1-1

Figure 1-2. Test Access Port (TAP).......................................................................................................................... 1-2

Figure 1-3. PCIe-1149.1 Block Diagram................................................................................................................. 1-3

Figure 3-1. ScanTAP-4 20-pin TAP Header Connectors (top view)........................................................................ 3-1

Figure 4-1. Controller Configuration Screen........................................................................................................... 4-1

Figure 4-2. PCIe-1149.1 Setup Screen (but ScanTAP-4 not connected).................................................................. 4-2

Figure 4-3. Successful PCIe-1149.1 With ScanTAP Setup Screen........................................................................... 4-3

Figure 4-4. Advanced Configuration Setup Screen.................................................................................................. 4-4

Figure 4-5. Controller Configuration TAP Configuration Options..........................................................................4-6

Figure 4-6. Typical ScanPlus Runner Test Plan...................................................................................................... 4-9

Figure 4-7. ScanPlus Runner Pop-up Menu........................................................................................................... 4-10

Figure 4-8. Infrastructure Test Options Dialog Box.............................................................................................. 4-11

Figure 4-9. Available ScanTAP-4 Configuration................................................................................................... 4-12

Figure 4-10. ScanPlus Runner Test Plan for Gang Programming......................................................................... 4-14

Figure 4-11. ScanPlus Runner Pop-up Menu......................................................................................................... 4-15

Figure 4-12. Infrastructure Test Options Dialog Box............................................................................................ 4-16

Figure 4-13. Available ScanTAP-4 TAP Configuration......................................................................................... 4-17

Figure 4-14. Available ScanTAP-4 TAP Configuration for .fpi files...................................................................... 4-18

Figure 4-15. ScanPlus Flash Programmer Gang Programming Window..............................................................4-20

Figure A-1. Standard TAP connector (top view)..........................................................................................................1

Figure A-2. TAP Connector Schematic........................................................................................................................3

Figure A-3. Boundary-scan Flash Programming 16 Pin TAP Connector (top view)...................................................4

Figure A-4. Flash Programming TAP Connector Schematics......................................................................................6

Figure A-5. Boundary-scan Flash Programming 20-Pin TAP Connector (top view)..................................................7

Figure A-6. 20-pin TAP Connector Schematic for SPI................................................................................................10

Figure A-7. 20-pin TAP Connector Schematic for I2C...............................................................................................11

Figure B-1. Self-Test Result for the PCIe-1149.1 when the ScanTAP-4 is NOT connected.........................................2

Figure B-2. Self-Test Results for the PCIe-1149.1 with the ScanTAP-4 Connected.....................................................3

Table of Tables

Table 1-1. Programmable TCK Frequencies............................................................................................................ 1-5

Table 1-2. ScanTAP-4 DC Characteristics............................................................................................................... 1-7

Table 1-3. ScanTAP-4 SPI Interface DC Characteristics.........................................................................................1-8

Table 1-4. ScanTAP-4 I2C Interface DC Characteristics........................................................................................ 1-9

Table 3-1. ScanTAP-4 TAP Pin Assignment............................................................................................................. 3-3

Table 3-2. 68-Pin SCSI type Cable Parts................................................................................................................. 3-4

Table 3-3. Connector P2 Parallel Output Pin Assignment.......................................................................................3-5

Table 3-4. Connector P1 Parallel Input Pin Assignment......................................................................................... 3-6

Table 4-1. ScanPlus Runner ScanTAP-4 Configuration........................................................................................... 4-7

Table 4-2. ScanPlus Runner Naming Conventions.................................................................................................... 4-8

Table 4-3. ScanPlus Runner Naming Conventions for Gang Programming........................................................... 4-13

Table 4-4. ScanPlus Runner ScanTAP-4 Configuration......................................................................................... 4-19

Table 5-1. PCIe-1149.1 Controller Parameters....................................................................................................... 5-2

Table A-1. Signal Description and Termina t i on...........................................................................................................2

Table A-2. Standard 10-Pin TAP Connector ................................................................................................................2

Table A-3. Flash Programming TAP 16 Pin Connector...............................................................................................5

Table A-4. Signal Description and Termina t i on...........................................................................................................5

Table A-5. Flash Programming TAP 16 Pin Connector...............................................................................................8

Table A-6. Signal Description and Termina t i on...........................................................................................................9

Chapter 1

Product Overview

Introduction

The PCIe-1149.1 High-Speed PCI Express Bus boundary-scan controller is a member of the Corelis ScanExpress™ family of high performance scan-based test, analysis, and diagnostic tools. The PCIe-1149.1 High-Speed PCI Express (PCIe) Bus Boundary-Scan Controller card, with memorybehind-the-pin architecture, interfaces between a host computer and any IEEE Standard 1149.1 compatible target. The PCIe-1149.1 is designed to control the operation of an IEEE Standard

1149.1 boundary-scan test path by generating the proper signals under software control to interface with the target system. It also supports remote operation of multiple boundary-scan (JTAG) Test Access Ports (TAPs) using any of the Corelis ScanTAP family of Multiple TAP Intelligent pods such as the ScanTAP-4, ScanTAP-8 or ScanTAP-32. The PCIe-1149.1 is shown in Figure 1-1.

Figure 1-1. The Corelis PCIe-1149.1 Boundary-Scan Controller

The most popular Intelligent Pod is the ScanTAP-4. It connected to the PCIe-1149.1 card via a standard SCSI-II cable and it provides up to 4 independent TAP connectors with a programmable low-voltage-compatible interface. Each of the 4 TAP connectors contains direct access to JTAG, I2C and SPI interfaces. It also supports simultaneous programming and verification of Flash memory devices at continuous scan clock (TCK) speeds of up to 80 MHz. The ScanTAP pods include direct hardware compare of expected scan results and are therefore especially suitable for gang (parallel) testing and programming of units under test (UUTs).

Product Overview 1-1

The PCIe-1149.1 facilitates software-controlled boundary-scan operations per IEEE Standard

1149.1. It provides command access to the target’s Test Access Port (TAP), to verify PCB interconnects, perform functional testing, and debug without manual probing. Furthermore, the JTAG interface gives access to internal device functions that are not accessible via external probing, enabling fault isolation within the device itself. The JTAG interface also enables programming target Flash and CPLD devices, as well as downloading and uploading of data blocks to and from various storage devices. Application software for the PCIe-1149.1 is sold separately.

What Is IEEE Standard 1149.1?

The IEEE Standard 1149.1 test bus and boundary-scan architecture enable control of an IC, board, or system, via a standard four-signal interface. Each IEEE Standard 1149.1-compliant IC incorporates a feature known as boundary-scan, which ensures that a JTAG controller can control and observe each functional pin of the IC via the four-wire interface. A controller can load test, debug, or initialization patterns serially into the appropriate IC(s) via the IEEE Standard 1149.1 test bus. Thus, even with limited physical access, a user can observe or control IC, board, or system functions.

Two main elements comprise the IEEE Standard 1149.1 test bus: a Test Access Port (TAP), which interfaces internal IC logic with the external world via a four-signal (optionally five-signal) bus as shown in Figure 1-2, and a boundary-scan architecture, which defines standard boundary cells that drive and receive data at the IC pins. IEEE Standard 1149.1 also defines both mandatory and optional opcodes and test features. The test bus signals are: Test Clock (TCK), Test Mode Select (TMS), Test Data In (TDI), Test Data Out (TDO), and the optional Test Logic Reset (TRST).

The IEEE-1149.1 Test Access Port Interface (TAP) consists of four required signals:

Test Mode Select (TMS) Test Clock (TCK) Test Data In (TDI) Test Data Out (TDO)

A fifth signal is defined as optional:

Test Reset (TRST*)

TMS TCK

TDI TDO TRST*

T A

Figure 1-2. Test Access Port (TAP)

1-2 Product Overview

Features of the PCIe-1149.1

The Corelis PCIe-1149.1 is a high performance JTAG controller that can access devices, boards or systems compliant with IEEE Standard 1149.1. This PCI Express bus compatible card directly supports one JTAG boundary-scan chain (TAP), expandable to additional TAPs using ScanTAP intelligent pods. Two general purpose 8-bit parallel I/O ports are also provided for test and/or control of non-boundary-scan areas of the unit under test (UUT). With its software-controlled voltage translating logic, the PCIe-1149.1 can test low voltage systems. The SCSII type connector includes high high-speed differential signals for reliable interfacing to external ScanTAP pods and it supports high speed gang (parallel) testing and programming of multiple UUTs.

The PCIe-1149.1 contains several performance enhancing functional sections aimed at increasing test vector throughput. A functional block diagram of the PCIe-1149.1 is shown in Figure 1-3. Key functional elements include the TAP controller, and the memory resources that support it. The onboard memory provides scan data storage and can store the entire scan data for maximum performance, real-time scan operations.

A test system accesses the TAP controller and its associated memory through the host PCI Express bus memory-mapped I/O. This supports the high data rate of the PCI Express bus, regardless of actual test clock speeds. The ability to download information into these memory elements further decouples the scan operations from the host software. A state machine that contains status and control registers accessible through the PCI Express bus controls all functions of the PCIe-1149.1.

68 Pin SCSI II type

Connector

ScanTAP

TAP

Interface

Remote

Pod I/F

Parallel Ports Input Connector

PORT A

Low Voltage

INPUTS

TAP ADJUSTABLE

VOLTAGE INTERFACE

PORT B

Low Voltage

INPUTS

TAP

CONTROLLER

Programmable

CLOCK

GENERATOR

Figure 1-3. PCIe-1149.1 Block Diagram

Parallel Ports Output Connector

PORT A

Low Voltage

OUTPUTS

PCI EXPRESS INTERFACE

PORT B

Low Voltage

OUTPUTS

MEMORY

CONTROL/

STATUS

Registers

The PCIe-1149.1 TAP controller contains special autonomous hardware accelerator mechanisms to greatly increase performance where scan patterns repeat numerous times. This applies to target download/upload sequences conveying large data blocks. As a result, time consuming tasks such as

Product Overview 1-3

flash programming and emulator data transfers are more efficient for a given clock rate. This mechanism off-loads the host interaction requirements by generating repeated vectors internally, using host pre-loaded memory information. After host initialization, this mode of operation results in continuous and maximal scanning rates at all clock frequencies. The only exception occurs when the target paces the sequence by indicating a non-ready completion of data transfer, requiring a rescan of the target’s status. When not in this special mode, the scan stream bursts at the programmed TCK rate, as paced by the flow of vector bits from the host.

Another performance enhancement provides hardware expected-value verification of scanned-back data at programmable chain positions. Thus, the target output stream is evaluated without host intervention and accompanying process delays. This further supports the above autonomous operation enabling the scanning sequence to loop and rescan until the desired feedback is supplied, also without host intervention.

A programmable, time delay skew compensation mechanism supports the PCIe-1149.1’s high clock rates. This accommodates the returned target scan stream delays due to signal travel time down and up the cables. It can also adjust for a target’s on-board TCK-to-TDO response delay.

An auxiliary feature of the PCIe-1149.1 is the target power-shorted detector for two voltages sense target interface pins. With the target un-powered, this mechanism effectively measures the impedance of the target load for each of two possible connected voltages, determining if a short exists (some unacceptably low impedance). If this impedance is less than about 1 ohm (about an 11 watt target or greater at 3.3V, for example), it is deemed shorted.

Adjustable Voltage Interfaces

The software-programmable voltage level of the parallel I/O and TAP interfaces can be set to any voltage between 1.25 V and 3.30 V in increments of 0.05V minimum.

Parallel Input/Output Ports

The PCIe-1149.1 contains 16 parallel inputs and 16 parallel outputs. The board groups these digital I/O into two 8-bit parallel input ports, and two 8-bit parallel output ports: Port A and Port B. The host computer can access the output ports via the Corelis ScanPlus Runner software. The input ports are for future use and are not currently available to the user.

The output ports are useful for providing discrete signals that control functions on the user target system such as reset, power control, and disable/enable signals for operating non-boundary-scan devices on target boards that include some non IEEE-1149.1 compliant components.

PCI Express Interface

The PCIe-1149.1 is a single lane (x1)

(x1, x4, x8, x16).

It is mapped to 132 MB of memory space of the host system as established during

system initialization.

PCI Express add-in card, compatible with all compliant PCIe slots

1-4 Product Overview

Programmable Clocks

The PCIe-1149.1’s programmable TCK outputs to the IEEE Standard 1149.1 compatible target system can generate a wide range of TCK frequencies with onboard TCK generation circuitry. A programmable Phase Locked Loop (PLL) and counter dividers provide both a wide range and fine selection resolution. See Table 1-1 for the set of programmable values.

TCK range (MHz) Rate Resolution (MHz)

25 to 80 1

12.5 to 25 0.5

6.25 to 12.5 0.25

5 to 6.25 0.125

2.5 to 5 0.10

1.25 to 2.5 0.05

0.62 to 1.25 0.025

0.39 to 0.62 0.0156

0.05 to 0.39 0.05

Table 1-1. Programmable TCK Frequencies

Features of the ScanTAP-4

The Corelis ScanTAP-4 Multiple TAP Intelligent pod connects to the PCIe-1149.1 boundary-scan controller via the 68-pin SCSI II type HOST connector. No external power supply is required—the PCIe-1149.1 card supplies it. Differential signal driving supports cables of up to 30 feet. Automatic delay mechanisms compensate for transport delays through the cable. The four TAPs are individually configurable for interface voltages from 1.25 to 3.3 V. On-board voltage translation logic allows a host to chain these TAPs together, or to configure them for gang programming. During gang programming each TAP drives the same data out to up to four targets, and simultaneously programs and verifies them. Optional Slow Slew rate (Voltages limited to 1.8 V to

3.3 V for slow slew) is provided. Each TAP can detect power shorts to ground for up to 2 voltages per TAP (with user-provided test software), allowing the ScanTAP-4 to detect potentially damaging conditions before the target system(s) is powered up.

Refer to Chapter 4 for further explanation on how to configure the ScanTAP-4 when using ScanPlus Runner or ScanExpress Runner software tools.

Product Overview 1-5

PCIe-1149.1 Specifications

Host Computer

CPU Pentium III @ 1 GHz or better Operating System Windows 2000 or XP

PCI Express Interface

Width Single Lane (x1) Memory Space Size 132 MB

ScanTAP Interface

Maximum TCK frequency 80 MHz TCK frequency steps 1.00 MHz increments between 25 and 80 MHz TCK frequency steps (cont’d) 0.80 MHz increments between 12.5 and 25 MHz TCK frequency steps (cont’d) 0.25 MHz increments (or less) below 12.5 MHz Maximum scanning data length unlimited

Physical

Card Outline Dimensions (PCB) 3.875 ± 0.25 inches × 6.75 ± 0.25 inches

I/O Connectors

P3 - Boundary-scan Connector 68-pin SCSI II type (AMP P/N 787171-7 or equivalent) P1 - Input Port Connector 34-pin header (3M part no. 2534-6002UB or equivalent) P2 - Output Port Connector 34-pin header (3M part no. 2534-6002UB or equivalent)

Power Requirements (from host expansion bus)

3.3 V 1.5 Amps maximum

On-board Fuse (feeds power from PCIe-1149.1 to external pod)

1.5 Amp, SLO-BLO

Littelfuse part number 045401.5

Operating Environment

Temperature 0C to 55C Relative Humidity 10% to 90%, non condensing

Storage Environment

Temperature -40C to 85C

1-6 Product Overview

ScanTAP-4 Specifications

PCIe-1149.1 Interface

Host Connector 68-pin SCSI type (AMP part no. 787171-7 or equivalent) Host Cable Length: 6 foot (standard) - Corelis P/N 15314 15 foot (optional) - Corelis P/N 15328 30 foot (optional) - Corelis P/N 15329

TAP Interface

Connectors Four 20-pin shrouded headers, 0.1 in. × 0.1 in. spacing Number of TAPs 4 Maximum TCK frequency 80 MHz (Concurrent scanning at all TAPs occurs at up to the

full TCK rate capability of the PCIe-1149.1) Maximum scanning data length unlimited Programmable Interface Voltage 1.25 to 3.3 V in 0.05 V increments Programmable TAPs 4, each TAP can have its own programmable voltage settings Signals DC characteristics See Table 1-2

Symbol Test Conditions Limit Min Limit Max Units

VIH Vdd Adjust >= 2.5 V 2 Vdd + 0.5 V

Vdd Adjust < 2.50 V 0.65 × Vdd Vdd + 0.5 V

VIL Vdd Adjust >= 2.00 0.7 V

Vdd Adjust <= 2.0 0.35 × Vdd V

VOH I

VOL I

= -2 mA Vdd – 0.35 V

= 2 mA

0.45 V

Vdd =1.65 V

IOH Vdd = 1.65-1.95 V -4 mA

IOL Vdd = 1.65-1.95 V 4 mA

Note: Also refer to Low Voltage CMOS (LVC) family signal characteristics data available from TI.

Product Overview 1-7

Table 1-2. ScanTAP-4 DC Characteristics

SPI Interface - available on ScanTAP-4 units P/N 10302A or later (with blue power-on LED)

SCK frequency 1 MHz Signal DC Characteristics See Table 1-3:

Symbol Test Conditions Limit Min Limit Max Units

VIH Vdd Adjust >= 2.5 V 2 Vdd + 0.5 V

Vdd Adjust < 2.50 V 0.65 × Vdd Vdd + 0.5 V

VIL Vdd Adjust >= 2.00 0.7 V

Vdd Adjust <= 2.0 0.35 × Vdd V

VOH I

= -2 mA Vdd – 0.35 V

IOL = 2 mA

VOL

0.45 V

Vdd =1.65 V

IOH Vdd = 1.65-1.95 V -4 mA

IOL Vdd = 1.65-1.95 V 4 mA

Table 1-3. ScanTAP-4 SPI Interface DC Characteristics

1-8 Product Overview

I2C Interface - available on ScanTAP-4 units P/N 10302A or later (with blue power-on LED)

The ScanTAP-4 I2C interface has open-drain outputs and the SDA/SCL signals must be pulled up to 3.3V (VDD ) by the target.

SCL frequency 100 kHz Signal DC Characteristics See Table 1-4:

Symbol Test Conditions Limit Min Limit Max Units

VDD 3.0 3.6 V

VIH V

VIL V

>= 3.3 V 2.0 3.6 V

>= 3.3 V -0.5 0.8 V

IOL = 16 mA

VOL

0.0 0.4 V

VDD = 3.3 V

IOL V

Table 1-4. ScanTAP-4 I2C Interface DC Characteristics

= 3.3 V 16 mA

Product Overview 1-9

Power Short Test Pins

Power (Vcc) Sense Pins 2 per TAP connector (Vcc1, Vcc2), 8 total Vcc Measurement Type Short to GND detect, Target un-Powered, Voltage sense/measurement of +/- 50 VDC Voltage Sense Resolution 12-bit ADC Voltage Sense Accuracy +/- 50 mV

Physical

Box Outline Dimensions 4.00 in. × 4.60 in. × 0.75 in.

Power Requirements

No external supply needed Power is provided by the host controller

Operating Environment

Temperature 0C to 55C Relative Humidity 10% to 90%, non condensing

Storage Environment

Temperature -40C to 85C

1-10 Product Overview

Chapter 2

PCIe-1149.1 Installation

The PCIe-1149.1 product typically consists of the following components:

 PCIe-1149.1 PCI Express based boundary-scan controller card  PCIe-1149.1 User’s Manual

Ensure all materials listed are present and free from visible damage or defects before proceeding. If anything appears to be missing or damaged, contact Corelis at the number listed on the front cover immediately.

The ScanTAP-4 typically consists of the following components:

 ScanTAP-4 box  Host Cable, 6-foot, 68-pin SCSI type, one-to-one Cable, Corelis P/N 15314  A set of four 20-pin to 10-pin TAP cables, Corelis P/N 15310

NOTE: The actual hardware shipped to the customer may vary depending on the customer order.

When this manual was published the following optional target interface TAP cables were available from Corelis:

 Bag of 4 TAP cables, 20-pin to 16-pin TAP, Corelis P/N 15311  Bag of 4 TAP cables, 20-pin to 20-pin TAP, Corelis P/N 15312  Special for RISCwatch / PowerPC, 20-pin to 16-pin TAP, Corelis P/N 15433  Special for MIPS, 20-pin to 14-pin TAP, Corelis P/N 15425  Host Cable, 15-foot, 68-pin SCSI type, one-to-one cable, Corelis P/N 15328  Host Cable, 30-foot, 68-pin SCSI type, one-to-one cable, Corelis P/N 15329

PCIe-1149.1 Installation 2-1

Software Installation First!

The installation procedure requires the use of software that contains the driver for the PCIe-1149.1 card. Obtain the ScanPlus CD-ROM (or any other Corelis application that supports the PCIe-

1149.1 card) in order to proceed with installation. Install the ScanPlus Application Software before installing the PCIe-1149.1 controller. The PCIe-1149.1 controller is a plug-and-play device, and its drivers are installed with the ScanPlus Application Software. Windows will automatically recognize and configure the PCIe-1149.1 the first time it is detected in your system.

WARNING !

You MUST install the software first – before installing the card. Do not install the PCIe-1149.1 card until you have successfully installed the application software (ScanPlus, CodeRunner,

etc.). Installing the software provides the plug-and-play driver for the card so that the operating system is able to properly detect and configure the card. Installing the card before the software may result in improper card configuration and operation.

2-2 PCIe-1149.1 Installation

Hardware Installation

Again, make sure to install the ScanPlus Application Software before installing the PCIe-

1149.1 controller. The PCIe-1149.1 controller is a plug-and-play device, and its drivers are installed

with the ScanPlus Application Software. Windows will automatically recognize and configure the PCIe-1149.1 the first time it is detected in your system.

To install the PCIe-1149.1 on a PC:

 Update the PC BIOS and chipset drivers to the latest version from the manufacturer  Install ScanPlus Applications from the CD, and shut down the PC.  Remove the PCIe-1149.1 from its package.  Disconnect the PC power cord from the power source and then remove the enclosure

cover from the PC.

 Plug the PCIe-1149.1 board into the PC in an available full height PCI Express slot.  Use a screw to firmly attach the PCIe-1149.1 card bracket to the PC chassis.  Close the PC enclosure, apply power and verify that the PC boots up correctly.

Preserve the original packing material for future shipment or storage of the PCIe-1149.1.

In the event that you installed the PCIe-1149.1 controller before installing the software, cancel the Add/Remove Hardware Wizard and install the ScanPlus Applications from the CD. The next time you start the PC, Windows will automatically recognize and configure the PCIe-1149.1.

Once the PCIe-1149.1 is installed in the PC, connect the ScanTAP-4 to the PCIe-1149.1 card using the 68-pin SCSI type host cable:

 Power down (shutdown) the PC  Plug the 68-pin host cable to the mating connector on the PCIe-1149.1 (that should not

protrude from the back of your PC enclosure).

 Plug the other side of the 68-pin host cable to the HOST connector of the ScanTAP-4

box.

 Apply power and verify that the PC boots up correctly. The “ON” LED should be

constantly illuminated when the PC is powered up.

PCIe-1149.1 Installation 2-3

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Corelis PCIe-1149.1 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual