Continental Automotive TIS 03 User Manual

Functional description

IS-03

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1. SYSTEM OVERVIEW

The tire pressure monitoring system (referred as TG for Tire Guard) consists of the following u

nits:

- Tire guard wheel unit type TIS-03 which includes an integrated pressure, temperature and

acceleration sensor and a RF transmitter.

- LF receiver unit which includes a LF receiver (not described in this document)

The TG monitors a vehicle's tire pressure while driving or stationary. An electronic unit (wheel unit) inside each tire, mounted to the valve stem, periodically measures the actual tire pressure. By means of RF communication, this pressure information is transmitted to the RF transmitter.

. TECHNICAL DESCRIPTION

Carrier frequency: 433.92 MHz Number of channels: 1 Type of modulation: Frequency Shift Keying (FSK) Baud rate: 9600bps Rated Output Power: < 10mW Antenna: Internal Voltage supply range : 2.1 up to 3.2V

3. TYPICAL USAGE PATTERN

3.1 AVERAGE FACTOR CALCULATION (Standard 47 CFR Part 15C (periodic intentional transmitter))

Maximum transmitting duration in whatever 100ms windows: 10.31ms

 Averaging factor = 20xlog(10.31/100)=-19.73dB

Note : The time between inter frames is always higher than the 100ms FCC window.

BLOCK DIAGRAM

The block diagram below shows the main electronic units of the wheel unit:

Sensor Block Diagram

FXTH870x5

(P ress ure ,

te m per a tur e,

a cce le rat io n se ns o r,

µ co nt roll er & R F

T ran s m i tte r)

C rys tal :2 6M Hz

4 3 3. 92M H z o r 3 1 5M H z

R F C IRC UI T (T un n in g C om pon en ts)

A NT E NN A

Le ar nin g LF co il

(1 a xe C oil @

1 25 KH z)

L I TH I UM

B A TT E RY

3 V C R 20 5 0H R

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IC Block Diagram: FXTH870x5

he FXTH870x5 contains:

• Microcontroller with accelerometer and pressure sensor interfaces,

and RF transmitter (MCU)

• Optional ranges on pressure transducers

• Z-axis acceleration transducer

The MCU interfaces to the RF transmitter using a standard memory mapped registers. The transducers connect to the MCU using custom analog interfaces and inter-chip bonding wires.

5. PICTURE

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6. LABEL

1.1. U

Continental TIS-03 FCC ID: KR5TIS-03

his device complies with Part 15 of the FCC Rules. Operation is subject to the following

T two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation.

Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the equipment.

1.2. CANADA

Continental TIS-03 IC: 7812D-TIS03

Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation.

Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the equipment.

of 4

FXTH870x6

Top and bottom view

Top view

Pin connections

24-Pin, 1-hole lid

7 x 7 QFN

PTA3

LFA

LFB

BKGD/PTA4

PTB1

PTA2

PTA1

RESET

DDA

SSA

REG

PTB0

N/C

ID Feature on top lid

PTA0

RFV

Freescale Semiconductor Document Number: FXTH870x6

Data Sheet: Advance Information Rev. 1.5, 02/2015

An Energy-Efficient Solution by Freescale

FXTH870x6 Tire Pressure Monitor Sensor

The FXTH870x6 family is comprised of the following functions all within the same package.

Features

• Pressure sensor with one of two calibrated pressure ranges — 100 - 450 kPa — 100 - 900 kPa

• Temperature sensor

• Optional XZ- or Z-axis accelerometer with adjustable offset option

• Voltage reference measured by ADC10

• Six-channel, 10-bit analog-to-digital converter (ADC10) with two external

I/O inputs

• 8-bit MCU — S08 Core with SIM and interrupt — 512 RAM — 8K FLASH (in addition to 8K providing factory firmware and trim

• Dedicated state machines to sequence routine measurement and

transmission processes for reduced power consumption

• Internal 315-/434-MHz RF transmitter

• Differential input LF detector/decoder on independent signal pins

• Seven multipurpose GPIO pins

• Real-Time Interrupt driven by LFO with interrupt intervals of

8, 16, 32, 64, 128, 256, 512 or 1024 ms

• Low-power, wakeup timer and periodic reset driven by LFO

• Watchdog timeout with selectable times and clock sources

• Two-channel general purpose timer/PWM module (TPM1)

This document contains information on a new product. Specifications and information herein are subject to change without notice.

data)

— 64-byte, low-power, parameter registers

— External crystal oscillator — PLL-based output with fractional-n divider — OOK and FSK modulation capability — Programmable data rate generator — Manchester, Bi-Phase or NRZ data encoding — 256-bit RF data buffer variable length interrupt — Direct access to RF transmitter from MCU for unique formats — Low power consumption (less than 8 mA at 434 MHz, 5 dBM at

3.0 V, 25 °C)

— Four pins can be connected to optional internal pullups/pulldowns and STOP4 wakeup interrupt — Two of seven pins can be connected to a channel on the ADC10 — Two of seven pins can be connected to a channel on the TPM1

• Internal oscillators

Related Documentation

The FXTH870x6 device features and operations are described in a variety of reference manuals, user guides, and application notes. To find the most-current versions of these documents:

1. Go to the Freescale homepage at:

http://www.freescale.com/

2. In the Keyword search box at the top of the page, enter the device number FXTH870x6.

— MCU bus clock of 0.5, 1, 2 and 4 MHz (1, 2, 4 and 8 MHz HFO) — Low frequency, low power time clock (LFO) with 1 ms period — Medium frequency, controller clock (MFO) of 8 sec period

• Low-voltage detection

• Normal temperature restart in hardware (over- or under-temperature detected by software)

ORDERING INFORMATION

Part number Accelerometer axis Package Range Code1

FXTH8705026T1 Z 2264 (7 x 7, 1-hole lid) 100-450 kPa $08 FXTH8705116T1 XZ 2264 (7 x 7, 1-hole lid) 100-450 kPa $0C FXTH8709026T1 Z 2264 (7 x 7, 1-hole lid) 100-900 kPa $18 FXTH8709116T1 XZ 2264 (7 x 7, 1-hole lid) 100-900 kPa $1C FXTH8709126T1 XZ Ext. Range 2264 (7 x 7, 1-hole lid) 100-900 kPa $1E

Code1 Code0

FXTH8709226T1 XZ 2264 (7 x 7, 1-hole lid) 100-900 kPa $1C Rel11

Sensors Freescale Semiconductor, Inc. 2

FXTH870x6

Contents

1 General Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.1 Overall Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.2 Multi-Chip Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.3 System Clock Distribution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.4 Reference Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2 Pins and Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.1 Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.2 Recommended Application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.3 Signal Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.2 RUN Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.3 WAIT Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.4 ACTIVE BACKGROUND Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.5 STOP Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.1 MCU Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.2 Reset and Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.3 MCU Register Addresses and Bit Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.4 High Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.5 MCU Parameter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.6 MCU RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.7 FLASH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.8 Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.9 FLASH Registers and Control Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5 Reset, Interrupts and System Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.2 MCU Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.3 Computer Operating Properly (COP) Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.4 SIM Test Register (SIMTST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

5.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

5.6 Low-Voltage Detect (LVD) System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

5.7 System Clock Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

5.8 Keyboard Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

5.9 Real Time Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

5.10 Temperature Sensor and Restart System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

5.11 Reset, Interrupt and System Control Registers And Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

5.12 System STOP Exit Status Register (SIMSES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

6 General Purpose I/O. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

6.1 Unused Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

6.2 Pin Behavior in STOP Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

6.3 General Purpose I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

6.4 Port A Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

6.5 Port B Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

7 Keyboard Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

7.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

7.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

7.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

7.4 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

7.5 Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.6 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

8 Central Processing Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

8.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

8.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

8.3 Programmer’s Model and CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

8.4 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

8.5 Special Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

8.6 HCS08 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

. . . . . . . . . . . . . . . . . . . . 52

FXTH870x6

Sensors Freescale Semiconductor, Inc. 3

9 Timer Pulse-Width Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

9.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

9.2 TPM1 Configuration Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

9.3 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

9.4 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

9.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

9.6 TPM1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

10 .Other MCU Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

10.1 Pressure Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

10.2 Temperature Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

10.3 Voltage Measurements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

10.4 Optional Acceleration Measurements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

10.5 Optional Battery Condition Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

10.6 Measurement Firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

10.7 Thermal Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

11 Periodic Wakeup Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

11.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

11.2 Wakeup Divider Register - PWUDIV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

11.3 PWU Control/Status Register 0 - PWUCS0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

11.4 PWU Control/Status Register 1 - PWUCS1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

11.5 PWU Wakeup Status Register - PWUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

11.6 Functional Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

12 LF Receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

12.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

12.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

12.3 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

12.4 Input Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

12.5 LFR Data Mode States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

12.6 Carrier Detect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

12.7 Auto-Zero Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

12.8 Data Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

12.9 Data Clock Recovery and Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

12.10 Manchester Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

12.11 Duty-Cycle For Data Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

12.12 Input Signal Envelope. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

12.13 Telegram Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

12.14 Error Detection and Handling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

12.15 Continuous ON Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

12.16 Initialization Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

12.17 LFR Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

13 RF Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

13.1 RF Data Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

13.2 RF Output Buffer Data Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

13.3 Transmission Randomization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

13.4 RFM in STOP1 Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

13.5 Data Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

13.6 RF Output Stage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.7 RF Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

13.8 Datagram Transmission Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

13.9 RFM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

13.10 RFM Control Register 1 - RFCR1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

13.11 RFM Control Register 2 - RFCR2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

13.12 RFM Control Register 3 - RFCR3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

13.13 RFM Control Register 4 - RFCR4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

13.14 RFM Control Register 5 - RFCR5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

13.15 RFM Control Register 6 - RFCR6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

13.16 RFM Control Register 7 - RFCR7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

13.17 PLL Control Registers A- PLLCR[1:0], RPAGE = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

13.18 PLL Control Registers B- PLLCR[3:2], RPAGE = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

13.19 EPR Register - EPR (RPAGE = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

13.20 RF DATA Registers - RFD[31:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

13.21 VCO Calibration Machine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

. . . . . . . . . . . . . . . . . . . . 121

FXTH870x6

Sensors

4 Freescale Semiconductor, Inc.

14 Firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

14.1 Software Jump Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

14.2 Function Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

14.3 Memory Resource Usage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

15 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

15.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

15.2 Background Debug Controller (BDC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

15.3 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

16 Battery Charge Consumption Modeling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

16.1 Standby Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

16.2 Measurement Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

16.3 Transmission Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

16.4 Total Consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

17 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

17.1 Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

17.2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

17.3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

17.4 Power Consumption (MCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

17.5 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

17.6 Voltage Measurement Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

17.7 Temperature Measurement Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

17.8 Pressure Measurement Characteristic (100 to 450 kPa ranges) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

17.9 Pressure Measurement Characteristic (100 to 900 kPa Ranges) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

17.10 Optional Acceleration Sensor Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

17.11 LFR Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

17.12 LFR Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

17.13 LFR Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

17.14 RF Output Stage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

17.15 Power Consumption RF Transmissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

18 Mechanical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

18.1 Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

18.2 Media Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

18.3 Mounting Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

19 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

20 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

FXTH870x6

Sensors Freescale Semiconductor, Inc. 5

1 General Information

1.1 Overall Block Diagram

The block diagram of the FXTH870x6 is shown in Figure 1. This diagram covers all the main blocks mentioned above and their main signal interactions. Power management controls and bus control signals are not shown in this block diagram for clarity.

1.2 Multi-Chip Interface

The FXTH870x6 contains two to three devices using the best process technology for each.

• Microcontroller with accelerometer and pressure sensor interfaces, and RF transmitter (MCU)

• Optional ranges on pressure transducers

• Optional XZ- or Z-axis acceleration transducer As shown in Figure 1 the MCU interfaces to the RF transmitter using a standard memory mapped registers. The transducers

connect to the MCU using custom analog interfaces and inter-chip bonding wires.

1.3 System Clock Distribution

The various clock sources and their distribution are shown in Figure 2. All clock sources except the low frequency oscillator, LFO, can be turned off by software control in order to conserve power.

FXTH870x6

Sensors

6 Freescale Semiconductor, Inc.

8K USER

FLASH

MEMORY

RAM

MEMORY

512

TPM1

TIMER/PWM

2-CHAN

LVD

RTI

TIMER

MCU CORE

S08

TEMP

SENSOR

PRESS

SENSOR

BANDGAP

REF

LFA

PTA1

ADC10

10-BIT

6-CHAN

TEMP

BKGD

LFB

64 Byte

PARAMETER

DATA

ENCODE

BIT

RATE

256-BIT

DATA

BUFFER

AMP

VCO/PLL

FRACTL

DIVIDER

XTAL

OSC

MCU

TRANSDUCERS

VOLT

REG

RESTART

OSC

GEN

PWU

TIMER

MFO

8 Sec

RESET

RECVR

SENS

LFO

1 ms

LFI

SMI

HFO

1, 2, 4 or 8

MHz

GP I/O

KEY

KBI

BOARD

WAKEUP

MFO

FIRMWARE

MEMORY

PTA0

SENSOR MEASUREMENT

(SMI)

RF CONTROLLER

INTERF A CE

LFO

(LFR)

RFM

REG

PTA2

PTA3

RF LVD

RFV

REG

PTB0

PTB1

PTA4

ACCEL

(OPTION)

ACCEL

(OPTION)

Figure 1. FXTH870x6 Overall Block Diagram

FXTH870x6

Sensors Freescale Semiconductor, Inc. 7

RTI

SYSTEM

CONTROL

LOGIC

 2

HFO OSC

1, 2, 4,

OSC

BUS

CPU

BDC

TPM1

RAM FLASH

LFR

ADC10

MFO OSC

8 Sec

PWU

CLSA, CLKSB

LFO

(1 kHz)

XTL

OSC

26 MHz

XI XO

PLL VCO

BIT

RATE

DATA

BUFFER

PRESSURE

SENSOR

TRANSDUCERS

MCU

RTICLKS

PAR

REG

MFO

XCO

GEN

(500 kHz)

LFO

OSC

1 mS

PERIOD

SENSOR MEASUREMENT

INTERFACE

ADC10

CLOCK

ADCCLK ADC10

BUSCLKS[1:0]

WATCH

DOG

COPCLKS

Z-AXIS

SENSOR

4 kbps

(125 kHz)

RF STATE MACHINE

LFRO

OSCILL

 8

TCLKDIV

LFOSEL

MFO

PTA3

PTA2

LFO

(1 kHz)

CH0 CH1

RANDOM

(0 - 1 MHz)

RANDOM

(0 - 1 MHz)

OUT

41.67 kHz Sampling

and 8 MHz

X-AXIS

SENSOR

41.67 kHz Sampling

Figure 2. Clock Distribution

1.4 Reference Documents

The FXTH870x6 utilizes the standard product MC9S08 CPU core. The user can obtain further detail on the full capabilities of this core by referring to the HCS08 Family Reference Manual (HCS08RMV1).

FXTH870x6

8 Freescale Semiconductor, Inc.

Sensors

2 Pins and Connections

PTA3

LFA

LFB

BKGD/PTA4

PTB1

PTA2

PTA1

RESET

DDA

SSA

REG

PTB0

N/C

ID Feature on top lid

PTA0

RFV

N/C = No Connect: Do not connect PCB pads to signal traces, power/ground or multi-layer via.

Top View

BKGD/PTA4

X-AXIS

ORIENTATION

-X

Y-AXIS

ORIENTATION

-Y

Side View

Pressure

Port

POSITIVE ACCELERATION MOVES MASS IN +Z DIRECTION (VALUE INCREASES)

Z-AXIS

ORIENTATION

-Z

This section describes the pin layout and general function of each pin.

2.1 Package Pinout

The pinout for the FXTH870x6 device QFN package is shown in Figure 3 for the orientation of the pressure port up. The orientation of the internal Z-axis accelerometer is shown in Figure 4.

Figure 3. FXTH870x6 QFN Package Pinout

2.2 Recommended Application

Example of a simple OOK/FSK tire pressure monitors using the internal PLL-based RF output stage is shown in Figure 5. Any of the PTA[3:0] pins can also be used as general purpose I/O pins. Any of the PTA[3:0] pins that are not used in the application should be handled as described in Section 6.1.

Sensors Freescale Semiconductor, Inc. 9

Figure 4. FXTH870x6 QFN Optional Z-axis Accelerometer Orientation

FXTH870x6

2.3 Signal Properties

FXTH870xxx

0.1 µF

3.0 V

BATTERY

COIL

XTAL

ANT

BKGD/PTA4

LFA

LFB

PTA1

RESET

GENERAL

PURPOSE I/O

PTA0

PTA2

REG

470 nF

0.1 µF

PTA3

MATCHING

NETWORK

C2, C3, C4 optimized for crystal

C4*

R2 and R3, <10 k

recommended for

highest EMC resistance

PTB0 PTB1

L1 and matching network optimized for specific PWB and antenna layout. Recommend 0603 minimum size for L1 and other matching network inductors for maximum efficiency.

C1 and R1 optimized for coil used, but recommended RC < 15.3 sec.

The device C

, although drawn here as a capacitor, may be any type of passive component(s) sufficient to block or reduce unwanted external radiated signals from corrupting the crystal oscillator circuit: PCB traces for the LFA / LFB, A V

/ VDD, and VSS / A VSS pins and bypass capacitors should be minimized to reduce unw anted external

radiated signals from corrupting the power input circuits.

The following sections describe the general function of each pin.

2.3.1 VDD and VSS Pins

The digital circuits operate from a single power supply connected to the FXTH870x6 through the VDD and VSS pins. VDD is the positive supply and V locally decoupled as shown in Figure 6.

Care should be taken to reduce measurement signal noise by separating the V connection such that each metal trace does not share any load currents with other external devices as shown in Figure 6.

2.3.2 AVDD and AVSS Pins

is the ground. The conductors to the power supply should be connected to the VDD and VSS pins and

Figure 5. FXTH870x6 Example Application

The analog circuits operate from a single power supply connected to the FXTH870x6 through the AVDD and AVSS pins. AVDD is the positive supply and AVSS is the ground. The conductors to the power supply should be connected to the AVDD and AVSS pins and locally decoupled as shown in Figure 6.

, VSS, A VDD, A VSS and RVSS pins using a “star”

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10 Freescale Semiconductor, Inc.

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Care should be taken to reduce measurement signal noise by separating the V

0.1 µF

FXTH870xxx

to other

Battery

LOAD

Bypass capacitors closely coupled to the package pins

FXTH870xxx and Other Load Currents star connected to battery terminals

loads

0.1 µF

The decoupling devices, although drawn here as 0.1 F capacitors, may be any type of passive component(s) sufficient to block or reduce unwanted external radiated signals from corrupting the power input protection circuits; application tuning may be required.

connection such that each metal trace does not share any load currents with other external devices as shown in Figure 6.

Figure 6. Recommended Power Supply Connections

, VSS, A VDD, A VSS and RVSS pins using a “star”

2.3.3 V

The internal regulator for the analog circuits requires an external stabilization capacitor to AVSS.

REG

2.3.4 RVSS Pin

Power in the RF output amplifier is returned to the supply through the RVSS pin. This conductor should be connected to the power supply as shown in Figure 6 using a “star” connection such that each metal trace does not share any load currents with other supply pins.

2.3.5 RF Pin

The RF pin is the RF energy data supplied by the FXTH870x6 to an external antenna.

2.3.6 XO, XI Pins

The XO and XI pins are for an external crystal to be used by the internal PLL for creating the carrier frequencies and data rates for the RF pin.

2.3.7 LF[A:B] Pins

The LF[A:B] pins can be used by the LF receiver (LFR) as one differential input channel for sensing low level signals from an external low frequency (LF) coil. The external LF coil should be connected between the LFA and the LFB pins.

Signaling into the LFR pins can place the FXTH870x6 into various diagnostic or operational modes. The LFR is comprised of the detector and the decoder.

Each LF[A:B] pin will always have an impedance of approximately 500 k to V pins are used by the LFR when the LFEN con tro l b it is set and are not functional when the LFEN control bit is clear.

2.3.8 PTA[1:0] Pins

The PTA[1:0] pins are general purpose I/O pins. These two pins can be configured as normal bidirectional I/O pins with programmable pullup or pulldown devices and/or wakeup interrupt capability; or one or both can be connected to the two input channels of the A/D converter module. The pulldown devices can only be activated if the wakeup interrupt capability is enabled. User software must configure the general purpose I/O pins so that they do not result in “floating” inputs as described in

Section 6.1. PTA[1:02] map to keyboard Interrupt function bits [1:0].

Sensors Freescale Semiconductor, Inc. 11

due to the LFR input circuitry. The LFA/LFB

FXTH870x6

2.3.9 PTA[3:2] Pins

RESET

0.7 V

0.3 V

> 100 nsec

Reset Initiated

The PTA[3:2] pins are general purpose I/O pin. These two pins can be configured as normal bidirectional I/O pin with programmable pullup or pulldown devices and/or wakeup interrupt capability; or one or both can be connected to the two input channels of the Timer Pulse Width (TPM1) module. The pulldown devices can only be activated if the wakeup interrupt capability is enabled. User software must configure the general purpose I/O pins so that they do not result in “floating” inputs as described in Section 6.1. PTA[3:2] map to keyboard Interrupt function bits [3:2].

2.3.10 BKGD/PTA4 Pin

The BKGD/PTA4 pin is used to place the FXTH870x6 in the BACKGROUND DEBUG mode (BDM) to evaluate MCU code and to also transfer data to/from the internal memories. If the BKGD/PT A4 pin is held low when the FXTH870x6 comes out of a poweron reset the device will go into the ACTIVE BACKGROUND DEBUG mode (BDM).

The BKGD/PTA4 pin has an internal pullup device and can connected to V BDM operation after the device as been soldered into the PWB. If in-circuit BDM is desired the BKGD/PTA4 pin can be left unconnected, but should be connected to VDD through a low impedance resistor (< 10 k) which can be over-driven by an external signal. This low impedance resistor reduces the possibility of getting into the debug mode in the application due to an EMC event.

in the application unless there is a need to enter

2.3.11 RESET Pin

The RESET pin is used for test and establishing the BDM condition and providing the programming voltage source to the internal FLASH memory. This pin can also be used to direct to the MCU to the reset vector as described in Section 5.2.

The RESET operation after the device as been soldered to the PWB. If in-circuit BDM is desired the RESET should be connected to VDD through a low impedance resistor (< 10 k) which can be over-driven by an external signal. This low impedance resistor reduces the possibility of getting into the debug mode in the application due to an EMC event.

Activation of the external reset function occurs when the voltage on the RESET pin goes below 0.3 x V before rising above 0.7 x VDD as shown in Figure 7.

pin has an internal pullup device and can connected to VDD in the application unless there is a need to enter BDM

pin can be left unconnected; but

for at least 100 nsec

Figure 7. RESET Pin Timing

2.3.12 PTB[1:0] Pins

The PTB[1:0] pins are general purpose I/O pins. These two pins can be configured as nominal bidirectional I/O pins with programmable pullup. User software must configure the general purpose I/O pins so that they do not result in “floating” inputs as described in Section 6.1

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3 Modes of Operation

The operating modes of the FXTH870x6 are described in this section. Entry into each mode, exit from each mode, and functionality while in each of the modes are described.

3.1 Features

• ACTIVE BACKGROUND DEBUG mode for code development

• STOP modes: — System clocks stopped — STOP1: Power down of most internal circuits, including RAM, for maximum power savings; voltage regulator in

standby

— STOP4: All internal circuits powered and full voltage regulation maintained for fastest recovery

3.2 RUN Mode

This is the normal operating mode for the FXTH870x6. This mode is selected when the BKGD/PTA4 pin is high at the rising edge of reset. In this mode, the CPU executes code from internal memory following a reset with execution beginning at address specified by the reset pseudo-vector ($DFFE and $DFFF).

3.3 WAIT Mode

The WAIT mode is also present like other members of the Freescale S08 family members; but is not normally used by the FXTH870x6 firmware or typical TPMS applications.

3.4 ACTIVE BACKGROUND Mode

The ACTIVE BACKGROUND mode functions are managed through the BACKGROUND DEBUG controller (BDC) in the HCS08 core. The BDC provides the means for analyzing MCU operation during software development.

ACTIVE BACKGROUND mode is entered in any of four ways:

• When the BKGD/PTA4 pin is low at the rising edge of a power up reset

• When a BACKGROUND command is received through the BKGD/PTA4 pin

• When a BGND instruction is executed by the CPU

• When encountering a BDC breakpoint

Once in ACTIVE BACKGROUND mode, the CPU is held in a suspended state waiting for serial BACKGROUND commands rather than executing instructions from the user’s application program. Background commands are of two types:

• Non-intrusive commands, defined as commands that can be issued while the user program is running. Non-intrusive

commands can be issued through the BKGD/PTA4 pin while the MCU is in RUN mode; non-intrusive commands can also be executed when the MCU is in the ACTIVE BACKGROUND mode. Non-intrusive commands include:

— Memory access commands — Memory-access-with-status commands — BDC register access commands — The BACKGROUND command

• ACTIVE BACKGROUND commands, which can only be executed while the MCU is in ACTIVE BACKGROUND mode.

ACTIVE BACKGROUND commands include commands to:

— Read or write CPU registers — Trace one user progra m in stru ct io n at a time — Leave ACTIVE BACKGROUND mode to return to the user’s application program (GO)

The ACTIVE BACKGROUND mode is used to program a bootloader or user application program into the FLASH program memory before the MCU is operated in RUN mode for the first time. When the FXTH870x6 is shipped from the Freescale factory, the FLASH program memory is erased by default (unless specifically requested otherwise) so there is no program that could be executed in RUN mode until the FLASH memory is initially programmed.

The ACTIVE BACKGROUND mode can also be used to erase and reprogram the FLASH memory after it has been previously programmed.

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3.5 STOP Modes

One of two stop modes are entered upon execution of a STOP instruction when the STOPE bit in the system option register is set. In all STOP modes, all internal clocks are halted except for the low frequency 1 kHz oscillator (LFO) which runs continuously whenever power is applied to the VDD and VSS pins. If the STOPE bit is not set when the CPU executes a STOP instruction, the MCU will not enter any of the STOP modes and an illegal opcode reset is forced. The STOP modes are selected by setting the appropriate bits in SPMSC2. Table 1 summarizes the behavior of the MCU in each of the STOP1 and STOP4 modes. The STOP2 mode found in other Freescale S08 family members is not available; but the STOP3 mode is present like other members of the Freescale S08 family members.

3.5.1 STOP1 Mode

The STOP1 mode provides the lowest possible standby power consumption by causing the internal circuitry of the MCU to be powered down.

When the MCU is in STOP1 mode, all internal circuits that are powered from the voltage regulator are turned off. The voltage regulator is in a low-power standby state. STOP1 is exited by asserting either a reset or an interrupt function to the MCU.

Entering STOP1 mode automatically asserts LVD. STOP1 cannot be exited until the V

is greater than V

LVDH

or V

LV/DL

rising

(VDD must rise above the LVI re-arm voltage). Upon wakeup from STOP1 mode, the MCU will start up as from a power-on reset (POR) by taking the reset vector.

NOTE

If there are any pending interrupts that have yet to be serviced then the device will not go into the STOP1 mode. Be certain that all interrupt flags have been cleared before entry to STOP1 mode.

3.5.2 STOP4 LVD Enabled in STOP Mode

The L VD system is cap able of generating either an interrupt or a reset when the supply voltage drops below the LVD voltage. If the LVD is enabled by setting the LVDE and the LVDSE bits in SPMSC1 when the CPU executes a STOP instruction, then the voltage regulator remains active during STOP mode. If the user attempts to enter the STOP1 with the LVD enabled in STOP (LVDSE = 1), the MCU will enter STOP4 instead.

Table 1. STOP Mode Behavior

Mode STOP1 STOP4

LFO Oscillator, PWU Always On & Clocking Real-Time Interrupt (RTI) MFO Oscillator HFO Oscillator Off Off CPU Off Standby RAM Off Standby Parameter Registers On On FLASH Off Standby TPM1 2-Chan Timer/PWM Off Off Digital I/O Disabled Standby Sensor Measurement Interface (SMI) Off Optionally On Pressure P-cell Off Optionally On Optional Acceleration g-cell Off Optionally On Temperature Sensor (in ADC10) Off Optionally On Normal Temperature Restart Optionally On Optionally On Voltage Reference (in ADC10) Off Optionally On LFR Detector LFR Decoder Optionally On Optionally On RF Controller, Data Buffer, Encoder Optionally On Optionally On RF Transmitter ADC10 Off Optionally On

(2)

(4)

(5)

(1)

Optionally On Optionally On

Periodically On Periodically On

Optionally On Optionally On

Always On if using LFO as Clock

(3)

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Table 1. STOP Mode Behavior (continued)

Mode STOP1 STOP4

Regulator Off On I/O Pins Hi-Z States Held Wakeup Methods Interrupts, resets Interrupts, resets

1. RTI can be used in STOP1 or STOP4 if the clock selected is the LFO. To use the HFO as the clock the MCU must be in the RUN mode.

2. MFO oscillator started if the LFR detectors are periodically sampled, the LFR detectors detect an input signal; a pressure or acceleration reading is in progress or the RF state machine is sending data.

3. Requires internal ADC10 clock to be enabled.

4. Period of sampling set by MCU.

5. RF data buffer may be set up to run while the CPU is in the STOP modes.

Specific to the tire pressure monitoring application the parameter registers and the LFO with wakeup timer are powered up at all times whenever voltage is applied to the supply pins. The LFR detector and MFO may be periodically powered up by the LFR decoder.

3.5.3 Active BDM Enabled in STOP Mode

Entry into the ACTIVE BACKGROUND DEBUG mode from RUN mode is enabled if the ENBDM bit in BDCSCR is set. The BDCSCR register is not memory mapped so it can only be accessed through the BDM interface by use of the BDM commands READ_STATUS and WRITE_CONTROL. If ENBDM is set when the CPU executes a STOP instruction, the s ystem clocks to the BACKGROUND DEBUG logic remain active when the MCU enters STOP mode so BACKGROUND DEBUG communication is still possible. In addition, the voltage regulator does not enter its low-power standby state but maintains full internal regulation. If the user attempts to enter the STOP1 with ENDBM set, the MCU will instead enter this mode which is STOP4 with system clocks running.

Most BACKGROUND commands are not available in STOP mode. The memory-access-with-status commands do not allow memory access, but they report an error indicating that the MCU is in STOP mode. The BACKGROUND command can be used to wake the MCU from stop and enter ACTIVE BACKGROUND mode if the ENDBM bit is set. Once in BACKGROUND DEBUG mode, all BACKGROUND commands are available.

3.5.4 MCU On-Chip Peripheral Modules in STOP Modes

When the MCU enters any STOP mode, system clocks to the internal peripheral modules except the wakeup timer and LFR detectors/decoder are stopped. Even in the exception case (ENDBM = 1), where clocks are kept alive to the BACKGROUND debug logic, clocks to the peripheral systems are halted to reduce power consumption.

I/O Pins

If the MCU is configured to go into STOP1 mode, the I/O pins are forced to their default reset state (Hi-Z) upon entry into stop. This means that the I/O input and output buffers are turned off and the pullup is disconnected.

Memory

All module interface registers will be reset upon wakeup from STOP1 and the contents of RAM are not preserved. The MCU must be initialized as upon reset. The contents of the FLASH memory are non-volatile and are preserved in any of the STOP modes.

Parameter Registers

The 64 bytes of parameter registers are kept active in all modes of operation as long as power is applied to the supply pins. The contents of the parameter registers behave like RAM and are unaffected by any reset.

LFO

The LFO remains active regardless of any mode of operation.

MFO

The medium frequency oscillator (MFO) will remain powered up when the MCU enters the STOP mode only when the SMI has been initiated to make a pressure or acceleration measurement; or when the RF transmitter’s state machine is processing data.

HFO

The HFO is halted in all STOP modes.

PWU

The PWU remains active regardless of any mode of operation.

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Sensors Freescale Semiconductor, Inc. 15

ADC10

The internal asynchronous ADC10 clock is always used as the conversion clock. The ADC10 can continue operation during STOP4 mode. Conversions can be initiated while the MCU is the STOP4 mode. All ADC10 module registers contain their reset values following exit from STOP1 mode.

LFR

When the MCU enters STOP mode the detectors in the LFR will remain powered up depending on the states of the bits selecting the periodic sampling. Refer to Section 12 for more details.

Bandgap Reference

The bandgap reference is enabled whenever the sensor measurement interface requires sensor or voltage measurements.

TPM1

When the MCU enters STOP mode, the clock to the TPM1 module stops and the module halts operation. If the MCU is configured to go into STOP1 mode, the TPM1 module will be reset upon wakeup from STOP and must be re-initialized.

Voltage Regulator

The voltage regulator enters a low-power standby state when the MCU enters any of the STOP modes except STOP4 (LVDSE = 1 or ENBDM = 1).

Temperature Sensor

The temperature sensor is powered up on command from the MCU.

Temperature Restart

When the MCU enters a STOP mode the temperature restart will remain powered up if the TRE bit is set. If the temperature restart level is reached the MCU will restart from the reset vector.

3.5.5 RFM Module in STOP Modes

The RFM’s external crystal oscillator (XCO), bit rate generator, PLL, VCO, RF data buffer , data encoder , and RF output stage will remain powered up in STOP modes during a transmission, or if the SEND bit has been set and DIRECT mode has been enabled.

RF Output

When the RFM finishes a transmission sequence the external crystal oscillator (XCO), bit rate generator, PLL, VCO, RF data buffer, data encoder, and RF output stage will remain powered up if the SEND bit is set.

3.5.6 P-cell in STOP Modes

The P-cell is powered up only during a measurement if scheduled by the sensor measurement interface. Otherwise it is powered down.

3.5.7 Optional g-Cell in STOP Modes

The g-cell is powered up only during a measurement if scheduled by the sensor measurement interface. Otherwise it is powered down.

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4Memory

$0000 $004F

$0050 $008F

$1800

$17FF

$182B $182C

$FFFF

$0090

$C000

$BFFF

DIRECT PAGE REGISTERS

RAM 512 BYTES

UNIMPLEMENTED

HIGH PAGE REGISTERS

5488 BYTES

41964 BYTES

$028F $0290

PARAMETER REGISTERS

$DFC0

$DFBF

USER FLASH

8128 BYTES

USER VECTORS

FIRMWARE FLASH

8128 BYTES

$E000

$DFFF

$E040

$E03F

FIRMWARE JUMP TABLE

The overall memory map of the FXTH870x6 resides on the MCU.

4.1 MCU Memory Map

As shown in Figure 8, MCU on-chip memory in the FXTH870x6 consists of parameter registers, RAM, FLASH program memory for nonvolatile data storage, and I/O and control/status registers. The registers are divided into four groups:

• Direct-page registers ($0000 through $004F)

• Parameter registers ($0050 through $008F)

• RAM ($0090 through $028F)

• High-page registers ($1800 through $182B)

Figure 8. FXTH870x6 MCU Memory Map

The total programmable FLASH memory map is 16K, but the upper 8K is used for firmware and test software. Upon power up the firmware will initialize the device and redirect all vectors to the user area from $DFC0 through $DFFF . Any calls to the firmware subroutines are accessed through a jump table starting at location $E000 (see Section 14).

4.2 Reset and Interrupt Vectors

Table 2 shows address assignments for jump table to the reset and interrupt vectors. The vector names shown in this table are

the labels used in the equate file provided by Freescale in the CodeWarrior project file.

Table 2. Vector Summary

User Vector Addr Vector Name Module Source

$DFE0:DFE1 Vkbi KBI $DFE2:DFE3 $DFE4:DFE5 $DFE6:DFE7 Vrti Sys Ctrl - RTI

$DFE8:DFE9 Vlfrcvr LFR $DFEA:DFEB Vadc1 ADC10 $DFEC:DFED Vrf RFM

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Reserved Reserved

FXTH870x6

Table 2. Vector Summary (continued)

User Vector Addr Vector Name Module Source

$DFEE:DFEF Vsm SMI

$DFF0:DFF1 Vtpm1ovf TPM1

$DFF2:DFF3 Vtpm1ch1 TPM1

$DFF4:DFF5 Vtpm1ch0 TPM1

$DFF6:DFF7 Vwuktmr PWU

$DFF8:DFF9 Vlvd Sys Ctrl - LVD

$DFFA:DFFB $DFFC:DFFD Vswi SWI opcode

$DFFE:DFFF Vreset

Reserved

Sys Ctrl - POR, PRF, COP, LVD

Temp Restart, Illegal opcode or address

4.3 MCU Register Addresses and Bit Assignments

The registers in the FXTH870x6 are divided into these four groups:

• Direct-page registers are located in the first 80 locations in the memory map; these are accessible with efficient direct addressing mode instructions.

• The parameter registers begin at address $0050; these are also accessible with efficient direct addressing mode instructions.

• High-page registers are used less often, so they are located above $1800 in the memory map. This leaves more room in the direct page for more frequently used registers and variables.

• The nonvolatile register area consists of a block of 16 locations in FLASH memory at $FFB0:FFBF. Nonvolatile register locations include:

— Three values that are loaded into working registers at reset — An 8-byte back door comparison key that optionally allows the user to gain controlled access to secure memory.

Because the nonvolatile register locations are FLASH memory, they must be erased and programmed like other FLASH memory locations.

Direct page registers are located within the first 256 locations in the memory map, so they are accessible with efficient direct addressing mode instructions, which requires only the lower byte of the address. Bit manipulation instructions can be used to access any bit in any direct-page register. Table 3 is a summary of all user-accessible direct-page registers and control bits. Those related to the TPMS application and modules are described in detail in this specification.

The register names in column two of the following tables are shown in bold to set them apart from the bit names to the right. Cells that are not associated with named bits are shaded. A shaded cell with a 0 indicates this unused bit always reads as a 0. Shaded cells with dashes indicate unused or reserved bit locations that could read as 1s or 0s.

Table 3. MCU Direct Page Register Summary

AddressRegister NameBit 7654321Bit 0

$0000 PTAD $0001 PTAPE $0002 Reserved $0003 PTADD PTADD[3:0] $0004 PTBD $0005 PTBPE $0006 Reserved $0007 PTBDD PTBDD[1:0] $0008 Reserved $0009 Reserved $000A Reserved $000B Reserved $000C KBISC 0 0 0 0 KBF KBACK KBIE KBIMOD

PTAD[4:0]

PTAPE[3:0]

PTBD[1:0]

PTBPE[1:0]

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Table 3. MCU Direct Page Register Summary (continued)

AddressRegister NameBit 7654321Bit 0

$000D KBIPE KBIPE[3:0] $000E KBIES $000F Reserved $0010 TPM1SC TOF TOIE CPWMS CLKSB CLKSA PS2 PS1 PS0 $0011 TPM1CNTH Bit [15:8] $0012 TPM1CNTL Bit [7:0] $0013 TPM1MODH Bit [15:8] $0014 TPM1MODL Bit [7:0] $0015 TPM1C0SC CH0F CH0IE MS0B MS0A ELS0B ELS0A $0016 TPM1C0VH Bit [15:8] $0017 TPM1C0VL Bit [7:0] $0018 TPM1C1SC CH1F CH1IE MS1B MS1A ELS1B ELS1A $0019 TPM1C1VH Bit [15:8] $001A TPM1C1VL Bit [7:0] $001B Reserved $001C PWUDIV WDIV[5:0] $001D PWUCS0 WUF WUFAK WUT[5:0] $001E PWUCS1 PRF PRFAK PRST[5:0] $001F PWUS PSEL 0 CSTAT[5:0] $0020-27 LFR Registers LFR Registers, see Table 4 and Table 5 $0028 ADSC1 $0029 ADSC2 $002A ADRH $002B ADRL $002C ADCVH $002D ADCVL $002E ADCFG $002F ADPCTL1 $0030-4F RFM Registers RFM Registers, see Table 6 and Table 7 $0050-8F Parameter Reg PARAM[63:0]

Note: Shaded bits are recommended to only be controlled by firmware or factory test.

COCO AIEN ADCO ADCH[4:0]

ADACT ADTRG ACFE ADCFGT 0 0 0 0

0 0 0 0 ADR[11:8]

ADR[7:0]

0 0 0 0 ADCV[11:8]

ADCV[7:0]

ADLPC ADIV[1:0] ADLSMP MODE[1:0] ADICLK[1:0]

ADPC[7:0]

KBEDG[3:0]

0 0

Table 4. LFR Register Summary - LPAGE = 0

AddressRegister NameBit 7654321Bit 0

$0020 LFCTL1 LFEN SRES CARMOD LPAGE IDSEL[1:0] SENS[1:0] $0021 LFCTL2 LFSTM[3:0] LFONTM[3:0] $0022 LFCTL3 LFDO TOGMOD SYNC[1:0] LFCDTM[3:0] $0023 LFCTL4 LFDRIE LFERIE LFCDIE LFIDIE DECEN VALEN TIMOUT[1:0] $0024 LFS LFDRF LFERF LFCDF LFIDF LFOVF LFEOMF LPSM LFIAK $0025 LFDATA RXDATA[7:0] $0026 LFIDL ID[7:0] $0027 LFIDH ID[15:8]

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Table 5. LFR Register Summary - LPAGE = 1

AddressRegister NameBit 7654321Bit 0

$0020 LFCTL1 LFEN SRES CARMOD LPAGE IDSEL[1:0] SENS[1:0] $0021 LFCTRLE $0022 LFCTRLD AVFOF[1:0} DEQS AZDC[1:0] ONMODE CHK125[1:0] $0023 LFCTRLC AMPGAIN[1:0] FINSEL[1:0] AZEN LOWQ[1:0] DEQEN $0024 LFCTRLB HYST[1:0] LFFAF LFCAF LFPOL LFCPTAZ[2:0] $0025 LFCTRLA TESTSEL[3:0] LFCC[3:0] $0026 Reserved $0027 Reserved Note: Shaded bits are recommended to only be controlled by firmware or factory test.

TRIMEE AZSC[2:0]

Table 6. RFM Register Summary - RPAGE = 0

AddressRegister NameBit 7654321Bit 0

$0030 RFCR0 BPS[7:0] $0031 RFCR1 FRM[7:0] $0032 RFCR2 SEND RPAGE EOM PWR[4:0] $0033 RFCR3 DATA $0034 RFCR4 RFBT[7:0] $0035 RFCR5 BOOST LFSR[6:0] $0036 RFCR6 VCO_GAIN[1:0] RFFT[5:0] $0037 RFCR7 RFIF RFEF RFVF RFIAK RFIEN RFLVDEN RCTS RFMRST $0038 PLLCR0 AFREQ[12:5] $0039 PLLCR1 AFREQ[4:0] POL CODE[1:0] $003A PLLCR2 BFREQ[12:5] $003B PLLCR3 BFREQ[4:0] CF MOD CKREF $003C RFD0 RFD[7:0] $003D RFD1 RFD[15:8] $003E RFD2 RFD[23:16] $003F RFD3 RFD[31:24] $0040 RFD4 RFD[39:32] $0041 RFD5 RFD[47:40] $0042 RFD6 RFD[55:48] $0043 RFD7 RFD[63:56] $0044 RFD8 RFD[71:64]] $0045 RFD9 RFD[79:72] $0046 RFD10 RFD[87:80] $0047 RFD11 RFD[95:88] $0048 RFD12 RFD[103:96] $0049 RFD13 RFD[111:104] $004A RFD14 RFD[119:112] $004B RFD15 RFD[127:120] $004C Reserved $004D Reserved $004E Reserved $004F Reserved

Note: Shaded bits are recommended to only be controlled by firmware or factory test.

IFPD ISPC IFID FNUM[3:0]

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Table 7. RFM Register Summary - RPAGE = 1

AddressRegister NameBit 7654321Bit 0

$0030 RFCR0 BPS[7:0] $0031 RFCR1 FRM[7:0] $0032 RFCR2 SEND RPAGE EOM PWR[4:0] $0033 RFCR3 DATA $0034 RFCR4 RFBT[7:0] $0035 RFCR5 BOOST LFSR[6:0] $0036 RFCR6 VCO_GAIN[1:0] RFFT[5:0] $0037 RFCR7 RFIF RFEF RFVF RFIAK RFIEN RFLVDEN RCTS RFMRST $0038 EPR —/VCD3 PLL_LPF_[2:0]/VCD[2:0] $0039 Reserved $003A Reserved $003B Reserved $003C RFD0 RFD[135:128] $003D RFD1 RFD[143:136] $003E RFD2 RFD[151:144] $003F RFD3 RFD[159:152] $0040 RFD4 RFD[167:160] $0041 RFD5 RFD[175:168] $0042 RFD6 RFD[183:176] $0043 RFD7 RFD[191:184] $0044 RFD8 RFD[199:192] $0045 RFD9 RFD[207:200] $0046 RFD10 RFD[215:208] $0047 RFD11 RFD[223:216] $0048 RFD12 RFD[231:224] $0049 RFD13 RFD[239:232] $004A RFD14 RFD[247:240] $004B RFD15 RFD[255:248] $004C Reserved $004D Reserved $004E Reserved $004F Reserved Note: Shaded bits are recommended to only be controlled by firmware or factory test.

IFPD ISPC IFID FNUM[3:0]

PA_SLOPE VCD_EN

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4.4 High Address Registers

High-page registers are used much less often, so they are located above $1800 in the memory map. This leaves more room in the direct page for more frequently used registers and variables. The registers control system level features as given in Table 8.

Table 8. MCU High Address Register Summary

AddressRegister NameBit 7654321Bit 0

$1800 SRS POR PIN COP ILOP ILAD PWU LVD $1801 SBDFR $1802 SIMOPT1 COPE COPCLKS STOPE RFEN TRE TRH BKGDPE $1803 SIMOPT2 $1804 Reserved $1805 Reserved $1806 SDIDH REV[3:0] ID[11:8] $1807 SDIDL ID[7:0] $1808 SRTISC RTIF RTIACK RTICLKS RTIE

$1809 SPMSC1 LVDF LVDACK LVDIE LVDRE LVDSE LVDE $180A SPMSC2 $180B Reserved $180C SPMSC3 LVWF LVWACK LVDV LVWV 0 0 0 0 $180D SIMSES $180E SOTRM SOTRM[7:0]

$180F SIMTST

$1810-1F Reserved

$1820 FCDIV DIVLD PRDIV8 DIV[5:0]

$1821 FOPT KEYEN FNORED

$1822 Reserved

$1823 FCNFG 0 0 KEYACC 0 0 0 0 0

$1824 FPROT FPS[7:1] FPDIS

$1825 FSTAT FCBEF FCCF FPVIOL FACCERR

$1826 FCMD FERASE FCMD[6:0]

$1827-3F Reserved

Note: Reserved bits shown as 0 must always be written to 0.

Reserved bits shown as 1 must always be written to 1. Shaded bits are recommended to only be controlled by firmware or factory test.

0 0 0 0 0 0 0BDFR

0 COPT[2:0] LFOSEL TCLKDIV BUSCLKS[1:0]

0RTIS{2:0]

0BGBE

0 0 0PDF0 PPDACK PDC 0

KBF IRQF TRF PWUF LFF RFF

TRH[2:0] TRO

0 0 0 0 SEC0[1:0}

0 FBLANK 0 0

4.5 MCU Parameter Registers

The 64 bytes of parameter registers are located at addresses $0050 through $008F. These registers are powered up at all times and may be used to store temporary or history data during the times that the MCU is in any of the STOP modes. The parameter register at $008F is used by the firmware for interrupt flags.

4.6 MCU RAM

The FXTH870x6 includes static RAM. The locations in RAM below $0100 can be accessed using the more efficient direct addressing mode, and any single bit in this area can be accessed with the bit-manipulation instructions (BCLR, BSET, BRCLR, and BRSET). Locating the most frequently accessed program variables in this area of RAM is preferred.

The RAM retains data when the MCU is in low-power WAIT, STOP3 or ST OP4 modes. At power-on or after wakeup from STOP1, the contents of RAM are not initialized. RAM data is unaffected by any reset provided that the supply voltage does not drop below the minimum value for RAM retention (V

When security is enabled, the RAM is considered a secure memory resource and is not accessible through BDM or through code executing from non-secure memory. See Section 4.8 for a detailed description of the security feature.

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RAM).

Sensors

None of the RAM locations are used directly by the firmware provided by Freescale. The firmware routines utilize RAM only through stack operations; and the user needs to be aware of stack depth required by each routine as described in the CodeWarrior project files supplied by Freescale.

4.7 FLASH

The FLASH memory is intended primarily for program storage. The operating program can be loaded into the FLASH memory after final assembly of the application product using the single-wire BACKGROUND DEBUG interface. Because no speci al voltages are needed for FLASH erase and programming operations, in-application programming is also possible through other software-controlled communication paths. For a more detailed discussion of in-circuit and in-application programming, refer to the HCS08 Family Reference Manual, Volume I, Freescale document order number HCS08RMV1/D.

4.7.1 Features

Features of the FLASH memory include:

• User Program FLASH Size — 8192 bytes (16 pages of 512 bytes each)

• Single power supply program and erase

• Command interface for fast program and erase operation

• Up to 100,000 program/erase cycles at typical voltage and temperature

• Flexible block protection

• Security feature for FLASH and RAM

• Auto power-down for low-frequency read accesses

4.7.2 Program and Erase Times

Before any program or erase command can be accepted, the FLASH clock divider register (FCDIV) must be written to set the internal clock for the FLASH module to a frequency (f so normally this write is performed during reset initialization. FCDIV cannot be written if the access error flag, FACCERR in FSTAT, is set. The user must ensure that FACCERR is not set before writing to the FCDIV register. One period of the resulting clock (1/f

) is used by the command processor to time program and erase pulses. An integer number of these timing pulses

FCLK

are used by the command processor to complete a program or erase command.

) between 150 kHz and 200 kHz. This register can be written only once,

FCLK

Table 9 shows program and erase times. The bus clock frequency and FCDIV determine the frequency of FCLK (f

for one cycle of FCLK is t case where t

=5s. Program and erase times shown include overhead for the command state machine and enabling and

FCLK

=1/f

. The times are shown as a number of cycles of FCLK and as an absolute time for the

FCLK

). The time

disabling of program and erase voltages.

Table 9. Program and Erase Times

Parameter Cycles of FCLK Time if FCLK = 200 kHz

Byte program 9 45 s

Byte program (burst) 4 20 s

Page erase 4000 20 ms Mass erase 20,000 100 ms

1. Excluding start/end overhead

(1)

4.7.3 Program and Erase Command Execution

The steps for executing any of the commands are listed below. The FCDIV register must be initialized and any error flags cleared before beginning command execution. The command execution steps are:

1. Write a data value to an address in the FLASH array. The address and data information from this write is latched into the FLASH interface. This write is a required first step in any command sequence. For erase and blank check commands, the value of the data is not important. For page erase commands, the address may be any address in the 512-byte page of FLASH to be erased. For mass erase and blank check commands, the address can be any address in the FLASH memory. Whole pages of 512 bytes are the smallest block of FLASH that may be erased. Do not program any byte in the FLASH more than once after a successful erase operation. Reprogramming bits to a byte which is already programmed is not allowed without first erasing the page in which the byte resides or mass erasing the entire FLASH memory. Programming without first erasing may disturb data stored in the FLASH.

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2. Write the command code for the desired command to FCMD. The five valid commands are blank check (0x05), byte program (0x20), burst program (0x25), page erase (0x40), and mass erase (0x41). The command code is latched into the command buffer.

3. Write a 1 to the FCBEF bit in FSTAT to clear FCBEF and launch the command (including its address and data information).

A partial command sequence can be aborted manually by writing a 0 to FCBEF any time after the write to the memory array and before writing the 1 that clears FCBEF and launches the complete command. Aborting a command in this way sets the FACCERR access error flag which must be cleared before starting a new command.

A strictly monitored procedure must be obeyed or the command will not be accepted. This minimizes the possibility of any unintended changes to the FLASH memory contents. The command complete flag (FCCF) indicates when a command is complete. The command sequence must be completed by clearing FCBEF to launch the command. Figure 9 is a flowchart for executing all of the commands except for burst programming. The FCDIV register must be initialized before using any FLASH commands. This must be done only once following a reset.

4.7.4 Burst Program Execution

The burst program command is used to program sequential bytes of data in less time than would be required using the standard program command. This is possible because the high voltage to the FLASH array does not need to be disabled between program operations. Ordinarily, when a program or erase command is issued, an internal charge pump associated with the FLASH memory must be enabled to supply high voltage to the array. Upon completion of the command, the charge pump is turned off. When a burst program command is issued, the charge pump is enabled and then remains enabled after completion of the burst program operation if these two conditions are met:

• The next burst program command has been queued before the current program operation has completed.

• The next sequential address selects a byte on the same physical row as the current byte being programmed. A row of FLASH memory consists of 64 bytes. A byte within a row is selected by addresses A5 through A0. A new row begins when addresses A5 through A0 are all zero.

The first byte of a series of sequential bytes being programmed in burst mode will take the same amount of time to program as a byte programmed in standard mode. Subsequent bytes will program in the burst program time provided that the conditions above are met. In the case the next sequential address is the beginning of a new row, the program time for that byte will be the standard time instead of the burst time. This is because the high voltage to the array must be disabled and then enabled again. If a new burst command has not been queued before the current command completes, then the charge pump will be disabled and high voltage removed from the array.

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START

WRITE TO FLASH

TO BUFFER ADDRESS AND DATA

WRITE COMMAND TO FCMD

YES

FPVIOL OR

WRITE 1 TO FCBEF

TO LAUNCH COMMAND

AND CLEAR FCBEF

(2)

FCCF?

ERROR EXIT

DONE

Note 2: Wait at least four bus cycles

FACCERR?

CLEAR ERROR

FACCERR?

WRITE TO FCDIV

(1)

Note 1: Required only once after reset.

before checking FCBEF or FCCF.

FLASH PROGRAM AND

ERASE FLOW

Figure 9. FLASH Program and Erase Flowchart

Programming time for the FLASH through the BDM function is dependent on the specific external BDM interface tool and software being used. Consult tool vendor for programming times.

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FXTH870x6

FCBEF?

START

WRITE TO FLASH

TO BUFFER ADDRESS AND DATA

WRITE COMMAND ($25) TO FCMD

YES

FPVIO OR

WRITE 1 TO FCBEF

TO LAUNCH COMMAND

AND CLEAR FCBEF

(2)

YES

NEW BURST COMMAND?

FCCF?

ERROR EXIT

DONE

Note 2: Wait at least four bus cycles before

FACCERR?

CLEAR ERROR

FACCERR?

Note 1: Required only once after reset.

WRITE TO FCDIV

(1)

checking FCBEF or FCCF.

FLASH BURST

PROGRAM FLOW

4.7.5 Access Errors

An access error occurs whenever the command execution protocol is violated. Any of the following specific actions will cause the access error flag (FACCERR) in FSTAT to be set. FACCERR must be cleared

Figure 10. FLASH Burst Program Flowchart

by writing a 1 to FACCERR in FSTAT before any command can be processed.

• Writing to a FLASH address before the internal FLASH clock frequency has been set by writing to the FCDIV register

• Writing to a FLASH address while FCBEF is not set (A new command cannot be started until the command buffer is empty.)

• Writing a second time to a FLASH address before launching the previous command (There is only one write to FLASH for every command.)

• Writing a second time to FCMD before launching the previous command (There is only one write to FCMD for every command.)

• Writing to any FLASH control register other than FCMD after writing to a FLASH address

• Writing any command code other than the five allowed codes (0x05, 0x20, 0x25, 0x40, or 0x41) to FCMD

• Accessing (read or write) any FLASH control register other than the write to FSTAT (to clear FCBEF and launch the command) after writing the command to FCMD.

• The MCU enters STOP mode while a program or erase command is in progress (The command is aborted.)

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