Consumer Microcircuits Limited FX980L7, FX980L6 Datasheet
CML Semiconductor Products
TETRA Baseband Processor FX980
1997 Consumer Microcircuits Limited
D/980/3 November 1997
1.0 Features Advance Information
•• RRC Filters for both Tx and Rx •• 4 x10-Bit D-A and 4 Input 10-Bit A-D
•• ππ/4 DQPSK Modulation
•• Transmit Output Power Control
•• 2x 13-Bit Resolution Sigma Delta D-A •• Low Power 3.0 - 5.5Volt Operation
•• 2x 16-Bit Resolution Sigma Delta A-D •• Effective Power down Modes
1.1 Brief Description
This device is intended to act as an interface between the analogue and digital sections of a Digital Radio
System, and performs many critical and DSP-intensive functions. The chip is designed with the necessary
capability to meet the requirements for use in both mobile and base station applications in Terrestrial Trunked
Radio (TETRA) systems.
The transmit path comprises all the circuitry required to convert digital data into suitably filtered analogue I
and Q signals for subsequent up-conversion and transmission. This includes digital control of the output
amplitudes, digital control of the output offsets and fully programmable digital filters: default coefficients
provide the RRC response required for TETRA.
The receive section accepts differential analogue I and Q signals at baseband and converts these into a
suitably filtered digital form for further processing and data extraction. A facility is provided for digital offset
correction and the digital filters are fully programmable with default coefficients providing the RRC response
required for TETRA.
Auxiliary DAC and ADC functions are included for the control and measurement of the RF section of the radio
system. This may include AFC, AGC, RSSI, or may be used as part of the control system for a Cartesian
Loop.
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CONTENTS
Section Page
1.0 FEATURES.......................................................................................................................................1.
1.1 BRIEF DESCRIPTION.......................................................................................................................1
1.2 BLOCK DIAGRAM............................................................................................................................3
1.3 SIGNAL LIST....................................................................................................................................4
1.4 EXTERNAL COMPONENTS.............................................................................................................6
1.5 GENERAL DESCRIPTION................................................................................................................7
1.5.1 Connection and Decoupling of Power Supplies...................................................................7
1.5.2 Tx Data Path............................................................................................................................8
1.5.2.1 Modulator..............................................................................................................................8
1.5.2.2 Filters....................................................................................................................................8
1.5.2.3 Gain Multiplier........................................................................................................................8
1.5.2.4 Offset Adjust..........................................................................................................................8
1.5.2.5 Sigma-Delta D-A Converters and Reconstruction Filters.........................................................8
1.5.2.6 Phase Pre-distortion...............................................................................................................8
1.5.2.7 Ramping Output Amplitude....................................................................................................8
1.5.3 Rx Data Path............................................................................................................................9
1.5.3.1 Anti-Alias Filtering and Sigma-Delta A-D Converters..............................................................9
1.5.3.2 Filters.....................................................................................................................................9
1.5.3.3 Offset Registers.....................................................................................................................9
1.5.3.4 I and Q Channel Gain.............................................................................................................9
1.5.4 Auxiliary Circuits....................................................................................................................9
1.5.4.1 10-Bit DACs...........................................................................................................................9
1.5.4.2 10-Bit ADC.............................................................................................................................9
1.5.4.3 Power Ramping and Control.................................................................................................10
1.5.5 IRQ Function.........................................................................................................................10
1.5.6 Serial Interface......................................................................................................................10
1.5.6.1 Command Interface..............................................................................................................11
1.5.6.2 Command Read Interface....................................................................................................12
1.5.6.3 Rx Data Interface.................................................................................................................12
1.5.6.4 Transmission of Data...........................................................................................................12
1.5.6.5 Command Control Serial Word.............................................................................................13
1.5.7 Register Description.............................................................................................................14
1.5.7.1 Register and Access Point Summary...................................................................................16
1.6 APPLICATION NOTES...................................................................................................................33
1.6.1 General...................................................................................................................................33
1.6.2 Transmitter.............................................................................................................................33
1.6.3 Receiver.................................................................................................................................33
1.6.4 Timing.....................................................................................................................................33
1.7 PERFORMANCE SPECIFICATION.................................................................................................33
1.7.1 Electrical Performance............................................................................................................33
1.7.2 Packaging...............................................................................................................................33
Note: As this product is still in development, it is likely that a number of changes and additions will be made
to this specification. Items marked TBD or left blank will be included in later issues. Information in this
data sheet should not be relied upon for final product design.
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1.2 Block Diagram
Figure 1 Block Diagram
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1.3 Signal List
L6 Package
44 PLCC
Package
#
Signal Description
Pin No. Pin No. Name Type
15 MCLK I/P Master clock input (typically 9.216MHz)
16 SClk O/P Serial interface clock
17 CmdDat BI Command serial interface Data
18 CmdFS I/P Command serial interface Frame
19 CmdRdDat O/P Command serial interface Read Data
20 CmdRdFS O/P Command serial interface Read Frame
11 RxDat O/P Receive serial interface Data
12 RxFS O/P Receive serial interface Strobe
23 N_IRQ O/P Interrupt request
14 N_RESET I/P Chip Reset
24 SCANSEL I/P Scan Select (normally tied low)
25 ITXP O/P Transmit "I" channel, positive output
26 ITXN O/P Transmit "I" channel, negative output
30 QTXP O/P Transmit "Q" channel, positive output
29 QTXN O/P Transmit "Q" channel, negative output
42 IRXP I/P Receive "I" channel, positive input
41 IRXN I/P Receive "I" channel, negative input
38 QRXP I/P Receive "Q" channel, positive input
37 QRXN I/P Receive "Q" channel, negative input
43 AUXADC1 I/P Auxiliary ADC channel 1
44 AUXADC2 I/P Auxiliary ADC channel 2
1 AUXADC3 I/P Auxiliary ADC channel 3
2 AUXADC4 I/P Auxiliary ADC channel 4
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1.3 Signal List (continued)
L6 Package
44 PLCC
Package
#
Signal Description
Pin No. Pin No. Name Type
10 AUXDAC1 O/P Auxiliary DAC channel 1
9 AUXDAC2 O/P Auxiliary DAC channel 2
8 AUXDAC3 O/P Auxiliary DAC channel 3
7 AUXDAC4 O/P Auxiliary DAC channel 4
36 BIAS1 BI Analogue bias level. This pin should be de-
coupled to V
SSB.
35 BIAS2 BI Analogue bias level. This pin should be de-
coupled to V
SSB
.
32 V
CC1
Power I Channel analogue positive supply rail. This
pin should be de-coupled to V
SS1.
33 V
CC2
Power Q Channel analogue positive supply rail. This
pin should be de-coupled to V
SS2.
34 V
CC3
Power Analogue Bias positive supply rail. Levels and
voltages are dependent upon this supply. This
pin should be de-coupled to V
SSB.
6 V
DD1
Power Auxiliary analogue positive supply rail. This
pin should be de-coupled to V
SSA.
3,21 V
DD
Power Digital positive supply rail. This pin should be
de-coupled to V
SS.
27,40 V
SS1
Ground I Channel analogue negative supply rail.
28,39 V
SS2
Ground Q Channel analogue negative supply rail.
31 V
SSB
Ground Analogue Bias negative supply rail.
5 V
SSA
Ground Auxiliary analogue negative supply rail.
4,13,22 V
SS
Ground Primary digital negative supply rail.
Notes: I/P = Input
O/P = Output
BI = Bi-directional
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1.4 External Components
Rx Inputs
When using the internal anti-alias filter, the following is suggested
Example values:
R1 = 220
Ω C1 = 1.5nF (R1, C1 precise values are not critical) (-3dB at 240kHz)
R2 = 408
Ω C2 = 3.9nF (R2 x C2 time constant should be preserved) (-3dB at 50kHz)
When not using the internal anti alias filter, it is suggested that the user should follow the guidelines in Section
1.5.3.1. In both cases, there should be at least one filter pole close to the chip inputs.
Figure 2a Recommended External Components - Rx Inputs
Tx Outputs
Example values:
R3 = 220
Ω C3 = 1nF
Decoupling capacitors should be employed as detailed in Section 1.5.1
Figure 2b Recommended External Components - Tx Outputs
AGC
IRXP
IRXN
QRXP
QRXN
Filter 1
R2
R2
C2
R2
R2
C2
R1
R1
R3
R1
C1
C1
R1
C3
ITXP
ITXN
QTXP
QTXN
R3
C3
R3
R3
C3
C3
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1.5 General Description
1.5.1 Connection and Decoupling of Power Supplies
Optimum performance from the FX980 can only be obtained by the use of adequate decoupling and
the separation of analogue and digital signals, including the use of separate ground planes.
Printed circuit board layout should follow the recommendations shown in Figure 3.
Figure 3 Recommended Decoupling Components
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1.5.2 Tx Data Path
The features described below give a high degree of flexibility for the user to compensate in the
baseband processing for non-ideal performance in the IF, RF and RF linear amplifier sections.
1.5.2.1 Modulator
This takes the 2-bit symbols, performs a Gray code conversion and uses a recursive adder to
generate a 3-bit code representing the 8 possible phase states. A look up table provides the digitally
encoded I and Q values for each phase state. The modulator function can be by-passed if required; in
this case the 3-bit code representing the 8 possible phase states which are passed to the look up
table is provided directly via the serial interface.
1.5.2.2 Filters
Digital filtering is applied to the data from the modulator; the coefficients are set as default to give a
Root Raised Cosine response with roll-off factor of 0.35. These FIR filters operate at 8x the incoming
symbol rate and are configured, for each channel, as two filters in cascade: the first filter has 79 taps
and the second filter has 49 taps. The first filter is used to enhance stop-band rejection and act as a
sampling correction filter and the second filter provides the primary shaping. Coefficients for the filters
may also be downloaded to the device via the serial interface; this gives the opportunity, if required, to
fine tune the frequency response of a complete system so as to minimise the BER or to use the
device in other applications. The filters can also be by-passed if required.
1.5.2.3 Gain Multiplier
This circuitry allows independent external control of the digital amplitudes in the I and Q channels to
12 bits of resolution. Extra circuits allow a mode of operation which will enable linear ramping up to a
maximum value, stay at this value for a specified duration, then ramp back down to zero. The
maximum value for each channel, the duration at maximum, the ramping up rate and the ramping
down rate are all programmable via the serial interface.
1.5.2.4 Offset Adjust
Offset registers allow any offsets introduced in the analogue sections of the transmit path to be
corrected digitally via the serial interface. The offset adjust has a resolution of 1 LSB and a maximum
value of 0.25x full scale.
1.5.2.5 Sigma-Delta D-A Converters and Reconstruction Filters
The converters are designed to have low distortion and >80dB dynamic range. These 3rd order
converters operate at a frequency of 128x symbol rate so as to over-sample the data at their inputs a
further 16 times. The reconstruction filters are 5th order, switched capacitor, low pass filters designed
to work in conjunction with an external RC.
1.5.2.6 Phase Pre-distortion
A further feature allows the user to compensate for a non-orthogonal carrier phase in the external
quadrature modulator by adding a programmable fraction of up to 1/8 of the filtered I and Q channel
signals to each other immediately prior to the DAC input.
1.5.2.7 Ramping Output Amplitude
A facility is provided to allow linear ramping of the outputs. This is accomplished, if enabled, by
multiplying the gain multiplier words by the ramping control register (RCR) value. The RCR is a 12-bit
word, representing a value from 0 to 1, which is designed to increment by an amount (INC) until its
maximum value. This value is held until a number of symbol times from the start of transmission
(TRD) when RCR decrements by an amount (DEC) until zero. INC, DEC and TRD are all 12-bit words
input via the serial interface prior to the start of a transmission.
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1.5.3 Rx Data Path
1.5.3.1 Anti-Alias Filtering and Sigma-Delta A-D Converters
The sampling frequency of the Sigma-Delta A-D is 128x symbol rate. The high oversampling rate
relaxes the design requirements on the anti-alias filter. However, to achieve optimum performance the
anti-alias filter must reject the sampling frequency to about -110dB, of which at least 40dB must be
provided externally. Additionally, in order to ease the complexity of the subsequent digital filters, there
is a further requirement that the anti-alias filter suppress 8x symbol rate to about -30dB. The on-chip
anti-alias filter is designed to achieve this when used in conjunction with some external filtering. If
required, the on-chip anti-alias filter can be by-passed and powered down, although external antialiasing must then be provided. The 4th order Sigma-Delta A-D converters are designed to have low
distortion and >96dB dynamic range. The baseband I and Q channels must be provided as differential
signals; this minimises in-band pick up both on and off the chip.
1.5.3.2 Filters
Digital filtering is applied to the data from the Sigma-Delta A-D converters; the default coefficients are
set to give a Root Raised Cosine response with roll-off factor of 0.35. These FIR filters are configured,
for each channel, as three filters in cascade. The first filter gives sufficient rejection at 8x symbol rate
to permit decimation at that frequency (note that -30dB is provided by the primary anti-alias filters).
The second filter has 63 taps and is used to enhance stop-band rejection. The third filter has 49 taps
and provides the primary shaping requirements. Coefficients for the second and third filters are
programmable via the serial interface. This gives the opportunity, if required, to fine tune the
frequency response of a complete system so as to minimise the BER or to use the device in other
applications. The filters can also be by-passed if required, by setting the centre coefficient to maximum
and all other coefficients to zero.
1.5.3.3 Offset Registers
System generated offsets may be removed by control of the offset register via the serial interface.
1.5.3.4 I and Q Channel Gain
Programmable gain modules are provided in both I and Q channels. These blocks allow the user to
adjust the dynamic range of the received data within the digital filters, thus optimising the filter signal
to noise performance for a range of levels at the Rx input pins.
The two channels are independently programmable. This enables differential gain corrections to be
made within the digital domain.
1.5.4 Auxiliary Circuits
1.5.4.1 10-Bit DACs
Four 10-bit DACs are provided to assist in a variety of control functions. The DACs are designed to
provide an output as a proportion of the supply voltage, depending on the digital input. They are
monotonic with an absolute accuracy of better than 1%. Control and Data for these come via the serial
interface.
1.5.4.2 10-Bit ADC
A 10-bit ADC is provided to assist in a variety of measurement and control functions. The ADC is
designed to produce a digital output proportional to the input voltage; full scale being the positive
supply. It is monotonic with an absolute accuracy of about 1%. An input multiplexer allows the input to
be selected from one of four sources. Control and digital data output is via the serial interface.
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1.5.4.3 Power Ramping and Control
One of the DACs has an additional feature which enables a set of values to be sequenced out at a
pre-selected frequency. This is aimed at enabling power ramping of a RF output with a suitable profile.
The sequence may be reversed for power down. The sequence of values is stored in a dedicated
RAM, which can be loaded via the serial interface.
1.5.5 IRQ Function
An interrupt request (IRQ) pin is provided for asynchronous communication with an external
processor. The IRQ (asserted low) will be asserted when any of the error or user information flags are
activated by an internal operation. Some examples of operations which may generate an IRQ are:
1. An attempt by the user to write to a full Tx data-input FIFO
2. An attempt is made by the Tx to read from the Tx data-input FIFO when it is empty.
3. An internal arithmetic overflow has occurred in an FIR filter.
The IRQ feature may also be used to establish the phasing of the received I and Q channel data from
the RxDat serial port should synchronisation be lost for any reason.
The cause of the IRQ can be obtained by reading the error flags register. All possible causes of an
IRQ are masked on reset. Mask status can be altered by writing to the IRQ mask register.
Note that default coefficients and settings have been optimised to maximise performance and should
not cause arithmetic overflows. However, use of non-default coefficients, large offset corrections or
large Tx phase adjustments may cause problems, which can be corrected by scaling down coefficients
or via the gain multiplier feature.
1.5.6 Serial Interface
All digital data I/O and control functions for the FX980 are via the serial interface. It is expected that
the FX980 will be used in conjunction with a DSP and/or other processor. The device has three serial
interface ports, each port is based on the industrial standard three wire serial interface. This interface
allows communication with standard DSP ICs using a minimum of external components. The three
serial interface ports are:
Cmd Command port, generally this is an input port receiving commands and data from the host,
but may also be configured as a bi-directional I/O interface.
CmdRd Command read port, an output port to send command read data back to the host. Read
data is only sent on this port in response to a read command.
RxData Receive data port, an output port to send receive data back to the host. Data is only
present on this interface when the Rx Data path is active. This port may also be
configured as the CmdRd port.
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Functions performed by the serial interface include:
• Power up or down and optional bypassing of selected blocks
• Setting digital filter coefficients
• Loading ramp up and ramp down increments and burst lengths for Tx
• Loading and transmitting data
• Loading offset correction, gain multiplier and phase adjustment registers
• Enabling/disabling of output via the Rx serial interface
• Vary sampling time for Rx data relative to the symbol (144kHz) clock.
• Loading data into auxiliary DACs
• Initiating conversions using auxiliary ADCs and reading results
• Writing data to, and reading data from, the Waveform Generation SRAM
• Power Ramping time step control
The three interfaces consist of the following signal pins:
SClk Output Serial Clock pin. This pin is common for all three interfaces.
CmdDat In/Out Command port Data pin. This pin is by default an input, but may be
configured as an open drain bi-directional pin.
CmdFS Input Command port Frame Sync pin. This pin is used to mark the first bit in a
serial frame.
CmdRdDat Output Command read port Data pin. This pin only has active data on it in
response to a read command.
CmdRdFS Output Command read port Frame Sync pin. This pin is used to mark the first bit in
a serial frame.
RxDat Output Receive data port Data pin. This pin is only active when the Rx Data path is
active.
RxFS Output Receive data port Frame Sync pin. This pin is used to mark the first bit in
a serial frame.
Note: All Frame Sync strobe signals are actually coincident with the last bit of a dataframe. See
Figures 4 and 5 for further details.
1.5.6.1 Command Interface
A serial command word consists of a 16-bit frame. Each frame is marked by an active Frame Sync
event which precedes the MSB bit. A command word can be either a control word or a transmit data
word.
MSB LSB
R/ W
Address Data
15 14 8 7 0
Command Control Serial Word
MSB LSB
1 Tx Data Address U/D 4/1 Tx Data
15 14 10 9 8 7 0
Command Transmit Data Serial Word
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1.5.6.2 Command Read Interface
Command read data is either output on one of the serial read ports, or driven out in the last 8 bits
(data field) on the Cmd port. When command read data is output on a serial read port, the read
address is put in the most significant half of the word, and the read data in the least significant half.
MSB LSB
0 Read Address Data
15 14 8 7 0
Command Read Serial Word
1.5.6.3 Rx Data Interface
The Rx Data interface is used only for output of the I and Q received data, unless it is operating in the
mode where CmdRd data is directed to it. When data reception is enabled, I and Q received data will
be output at either 8x or 4x the symbol rate, under control of command register RxSetup2. (see
Section 1.5.7). This is achieved by reducing the serial interface clock rate from MCLK/2 to MCLK/4
and discarding alternate data samples under control of command registers ConfigCtrl1 and
RxSetup2. 16-bit I and Q data words are output at the Rx Data interface, I data and MSB first (by
default), on the rising edge of SClk.
1.5.6.4 Transmission of Data
The address of the Tx FIFO is given consecutive locations ($0x04-$0x07), which allows the address
bits A1 and A0 (bits 11 and 10) of the Command Transmit Data Serial Word to be utilised as transmit
control functions. Data to be transmitted can be in either one or four (2-bit) symbol blocks, which are
subsequently modulated into the DQPSK constellation, or in 3-bit words, which map directly into
constellation points according to the table shown below.
3 bit
code
000 001 010 011 100 101 110 111
I
Q
1
0
0.7071
0.7071
0
1
-0.7071
0.7071
-1
0
-0.7071
-0.7071
0
-1
0.7071
-0.7071
Constellation map
The user initiates a transmit frame by asserting the TxEn bit in the TxSetup register. However,
internal transmission of the data will wait until specific conditions have been met. Firstly, a valid data
word must be written into the FIFO with the TxRampEn bit of the TxSetup register asserted.
Secondly, the internal symbol clock must be active. Therefore there is a variable delay between
asserting the TxEn bit and transmission starting. The user may poll the TxPathEn bit of the
TxFIFOStatus register to establish when transmission has started, and in this case the active state of
TxPathEn in High. In general, the user will wish to know when the transmit frame has completed.
This is indicated by TxPathEn returning Low.
To relieve the user of polling overheads when waiting for Tx frame completion, an interrupt can be set
up to occur on the transition of the TxPathEn bit from High to Low. In such circumstances, the
interrupt activation state of the TxPathEn can be considered Low.
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Two control bits are associated with each data transmission word. One controls the format of the word
and the other initiates and terminates a transmission cycle. This close association enables precise
control of the transmission frame. To relieve the user of the need to synchronise each TxData write
with the internal transmit cycle, transmit data words are written into an internal 4-word-deep FIFO.
Symbols or constellation points are then read as needed from this FIFO. It is necessary to make sure
that there is always a word to be read, and also that the FIFO is never written to when full. This may
be accomplished by using one of two data interlock mechanisms.
Data Interlock Mechanisms
There are two possible transmission data interlock mechanisms. It is recommended that the user
should always use one of these methods.
• Software polling.
• Serial Clock when ready.
Software polling requires the user to first check that the FIFO is not full before writing each TxData
word. This may be accomplished by inspecting the relevant FIFO status bits before writing one or
more TxData words.
The Serial Clock when ready method is a hardware interlock mechanism (enabled by setting the
TxHandshakeEn bit of ConfigCtrl1 register active). The mechanism allows the user to write TxData
words without doing any FIFO checks: the hardware handshake is implemented by stopping the serial
port clock when the FIFO is full. To prevent a serial port lockout-condition, the handshake is only
enabled once the transmission frame has been initiated and is automatically disabled at the end of a
frame. This mechanism should be used with care, because stopping the clock will freeze all other
serial port transfers (the serial port clock SClk is common to all three serial ports), including access to
auxiliary data converters and receive data.
Power Ramping and Frame Interlock
The RampUp bit in the TxData word is used to control both the power ramping function and the frame
activation. To start a transmission frame, a transmission word is written with the RampUp bit active. All
subsequent TxData words prior to frame termination must also have this bit active. The frame is
terminated by writing transmit data words with the RampUp bit inactive. Subsequent TxData words
must also have this bit inactive, until initiation of a new frame is required. While the power ramping is
active (up or down) the user must supply transmission symbols or valid constellation points. Once the
ramp down operation has completed, all subsequent TxData writes with the RampUp bit inactive will
be ignored.
1.5.6.5 Command Control Serial Word
A command word either directly accesses an internal register for a read or write operation, or
addresses a memory access point to indirectly access a block of internal memory. For test purposes
all registers that can be written may also be read. Not all registers may be written, as some are just
status registers. Each register or memory access point is assigned a unique address: the whole (8bit) address range is reserved for the FX980.
Indirect Memory Addressing
All internal memory access is via an access point. First, a command word access is used to reset the
internal address pointer, then data port access operations post-increment this address pointer.
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Example: To program the fifth and sixth locations of the Auxiliary SRAM with $0x01AA the
commands would be:
$0x0000
⇒Cmd
; set ConfigCtrl1 all bits Low ; use default conditions
$0x0118
⇒Cmd
; set ConfigCtrl2 bits 7 and 6 Low ; required by default for these
Reserved bits
; set ConfigCtrl2 bit 4 High ; post-increment addresses on a
read operation
; set ConfigCtrl2 bit 3 High ; enable read/write access to the
Auxiliary SRAM
$0xF300
⇒Cmd
; read SramData LSB register ; read fourth memory location
(LSB). Post-increment pointer.
CmdRd
⇒$0xF3xx
; SramData LSB register data returned ; discard this byte
$0x7002
⇒Cmd
; write SramData LSB register ; write $0x02 to fifth memory
location (LSB)
$0x716A
⇒Cmd
; write SramData MSB register ; write $0x6A to sixth memory
location (MSB)
$0xF000
⇒Cmd
; read SramData LSB register ; read fifth memory location (LSB)
CmdRd
⇒$0xF002
; SramData LSB register data returned ; check this byte is $0x02
$0xF100
⇒Cmd
; read SramData MSB register ; read sixth memory location (MSB)
CmdRd
⇒$0xF16A
; SramData MSB register data returned ; check this byte is $0x6A
$0x0110
⇒Cmd
; set ConfigCtrl2 bit 3 Low ; disable read/write access to the
Auxiliary SRAM
1.5.6.6 Coefficient Memory
The convention for naming filter coefficients is A1 to An, where n is given by (Filter Length + 1)/2, i.e. for the
15-tap filter, n = 8. This arises from the internal architecture of the filters and the fact that they are all “odd”
and symmetrical. Write or read operations beyond this coefficient number will be reflected about the central
coefficient e.g. the tenth read operation from the 15-tap filter would access coefficient location A6.
There is no practical reason to write or read beyond location n, but the user in any case must avoid write
operations at the (Filter Length + 1) location. This location (A0) location must be zero for the filters to operate
correctly. The global reset (N-RESET pin) establishes this condition when taken Low.
1.5.7 Register Description
This section describes in detail each of the registers and access points addressed by the Command Control
Serial Word.
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Key to Register Map
Each section that follows describes in detail the operation and use of each of the registers in the device. The
registers are split into their functional groups, grouping associated registers together. Each section consists of
a Title, an Address, a Function Reference Field, a Description, and a Bit Specification.
The Function Reference Field describes the overall access available to this section (RW/W/R, where R = Read
and W = Write).
The Bit Specification describes the function of each individual bit, or a range of bits within a register. There is a
separate line for each distinct field of bits. The State column indicates the action available to each group of
bits (RW/W/R).
Register Reset State
All I/O access points (both read and write) are reset to logic zero on taking N_RESET Low, except where
explicitly shown in this document. The reset state of status bits will depend on the level of the status signal
being monitored. Other registers (both read and write) are not affected by taking N_RESET Low.
TETRA Baseband Processor FX980
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1.5.7.1 Register and Access Point Summary
Control and Status Registers
$0x00
ConfigCtrl1
Configuration control register 1
$0x01
ConfigCtrl2
Configuration control register 2
$0x02
PowerDownCtrl
Power control register
$0x03
TxSetup
Transmit set-up register
$0x04-$0x07
TxData
Transmit data registers
$0x08
RxSetup1
Receive set-up control register 1
$0x09
RxSetup2
Receive set-up control register 2
$0x0A
AnaCtrl
Analogue configuration control register
$0x0B
AuxAdcCtrl
Auxiliary ADC data converter control register
$0x0C
RamDacCtrl
Ram Dac control register
$0x0D
LoopBackCtrl
Loopback control register
$0x0E
TxErrorStatus
Transmit error status register
$0x0F
TxErrStatMask
Transmit error status interrupt mask register
Auxiliary Function Registers
$0x10-$0x17
AuxAdcData
Auxiliary ADC data registers
$0x18-$0x1F
AuxDacData
Auxiliary DAC data registers
Status and Interrupt Registers
$0x20
RxErrorStatus
Receive error status register
$0x21
RxErrorStatMask
Receive error status interrupt mask register
$0x22
TxFIFOStatus
Transmission data FIFO status register
$0x23
TxFIFOStatMask
Tx data FIFO status interrupt mask register
Memory I/O Access Points
$0x24-$0x2D
CoeffRamData
Coefficient memory I/O access addresses
$0x2E-$0x2F Not Used.
Rx Data Path Registers
$0x30-$0x31
RxIQGainMult
Receive I channel gain attenuation registers
$0x32-$0x33
RxIQOffset
Receive I channel offset correction registers
$0x34-$0x35
RxIQGainMult
Receive Q channel gain attenuation registers
$0x36-$0x37
RxIQOffset
Receive Q channel offset correction registers
TETRA Baseband Processor FX980
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Rx Data Path Access Points
$0x38-$0x39
RxDataAccess
Receive path data access point (I)
$0x3A-$0x3B
RxDataAccess
Receive path data access point (Q)
$0x3C-$0x3F Not Used
Tx Data Path Registers
$0x40-$0x41
TxPhase
Transmit I channel phase correction registers
$0x42-$0x43
TxIQGainMult
Transmit I channel gain attenuation registers
$0x44-$0x45
TxIQOffset
Transmit I channel offset correction registers
$0x46-$0x47
TxPhase
Transmit Q channel phase correction registers
$0x48-$0x49
TxIQGainMult
Transmit Q channel gain attenuation registers
$0x4A-$0x4B
TxIQOffset
Transmit Q channel offset correction registers
$0x4C-$0x4D
TxRampUpInc
Transmit ramp-up increment registers
$0x4E-$0x4F
TxRampDnDec
Transmit ramp-down decrement registers
Tx Data Path Access Points
$0x50-$0x51
TxDataAccess
Transmit path data access point (I)
$0x52-$0x53
TxDataAccess
Transmit path data access point (Q)
$0x54-$0x5F Not Used
Self Test Registers
$0x60-$0x61
BISTPRSG
Built-in self test pseudo-random sequence generator
$0x62
BISTControl
Built-in self test control register
$0x63 Not Used
$0x64-$0x6D
BISTCRCRegisters
Built-in self test cyclic redundancy code checkers
$0x6E-$0x6F Not Used
SRAM Memory Access Points
$0x70-$0x73
SramData
Auxiliary DAC1 memory I/O access addresses
$0x74-$0x7F Not Used
Note: Addresses $0x80 to $0xFF cannot be used as the MSB controls the direction of data flow:
“1” = High = Read and “0” = Low = Write.
TETRA Baseband Processor FX980
1997 Consumer Microcircuits Limited 18 D/980/3
ConfigCtrl1
Title: Configuration Control register
Address: $0x00
Function: RW
Description: General configuration bits, together with operational control signal bits.
Bit Name Active State Function
7 DataRateHi High RW When set active all serial port data transfers will be at
half of the master clock rate. When inactive, all serial
port data rates will be at a quarter of the master clock
rate. This has the effect of altering the Rx sample output
rate from 8 times the symbol rate when active to 4 times
when inactive.
6 TxHandshakeEn High RW When set active enable the transmit hardware interlock
protocol, thereby stopping the Serial Clock (SClk) if the
transmit path is enabled and the transmit FIFO is full.
5 BiDirCmdPortEn High RW When this bit is set active the Cmd port will drive its
data line out of the chip for the last 8 bits of read
operations. When set inactive command read data will
be returned on either the Rx or the CmdRd port
(default).
4 RxDataForCmdRdEn High RW This bit only takes effect if the BiDirCmdPortEn bit is
inactive. When set active this bit causes all command
read operations to respond with data on the Rx serial
port. When set inactive the command read data will be
output via the CmdRd port (default).
(5,4) CommandReadDataMode RW The BiDirCmdPortEn bit and RxDataForCmdRdEn bit
together control the method by which command read
data is returned to the user.
00 (Default) Read data returned on CmdRd port.
01 Read data returned on Rx port and CmdRd port
10,11 Read data returned on Cmd port.
3 LowRxRdFS High RW When set active both the CmdRdFS and the RxFS
output pins will be driven active low, when set inactive
the two frame sync's will be driven active high (default).
2 RxDataPortDisable High RW When set active tristates the RxDat and RxFS pins.
1 RdCmdPortDisable High RW When set active tristates the CmdRdDat and CmdRdFS
pins.
0 SymboModuBypass High RW Setting this bit bypasses the Modulator, thereby taking
the least significant 3 bits of each Command Transmit
Data Serial Word received via the serial interface to
represent an absolute constellation mapping.
TETRA Baseband Processor FX980
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• Address and Data format for ConFigCtrl1 access
Data field [7:0]
D7 D6 D5 D4 D3 D2 D1 D00000 0 0 0
Address field [6:0]
TETRA Baseband Processor FX980
1997 Consumer Microcircuits Limited 20 D/980/3
ConfigCtrl2
Title: Configuration Control register
Address: $0x01
Function: RW
Description: General configuration bits, together with operational control signal bits.
Bit Name Active State Function
7 RW Reserved. Set this bit Low. Undefined on read.
6 RW User defined bit. This bit has no internal functionality and
is reset Low with the global N_RESET pin. The user may
employ this bit for any useful purpose.
5 n_SlowDown Low RW When active, this bit reduces the slew rate of digital output
pins. This reduces power consumption, ground bounce and
reflection problems associated with fast edges on poorly
terminated lines. De-activation speeds up the digital
outputs, but increases power consumption, ground bounce
and reflection problems. It is anticipated that the latter
mode will be used only in 3.3V systems.
4 SRamIoRdInc High RW This bit determines whether a read or write operation to the
Auxiliary SRAM will increment the address pointers. When
set active causes read operations to move the address
pointer on, this would therefore allow an efficient write then
read verify scheme to be used. When set inactive write
operations increment the address pointer.
3 SRamloEn High RW When set active allows read/write access to the Auxiliary
SRAM. It is only valid to activate this bit when the SRAM is
not being accessed by the RamDac. When this bit is set
active, the first access to SramData will access the first
SRAM address location. Subsequent read or write
accesses will increment the address pointer to the next
memory location.
2 CoeffRamIoRdInc High RW This bit determines whether a read or write operation to a
coefficient memory will increment the address pointers.
When set active the address pointer is incremented by any
coefficient ram read operation, thereby allowing a write
then read verification. When set inactive, write operations
increment the address pointer.
1 CoeffRamloEn High RW When set active allows read/write access to all the
coefficient memories. This bit is valid only when the Tx and
Rx Data paths are inactive. When this bit is set active, the
first access to any of the coefficient memories will access
the first coefficient location (A1). Subsequent read or write
accesses to any coefficient memory will increment the
address pointers for all the coefficient memories.
TETRA Baseband Processor FX980
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0 n_BigEndData Low RW When set active causes serial port read data, from the Rx
port to be generated with the MSB data bit as the first serial
word bit. If inactive, the LSB is first. On taking N_RESET
Low this bit is active (i.e. the default is MSB first).
• Address and Data format for ConFigCtrl2 access
Data field [7:0]
R D6 D5 D4 D3 D2 D1 D01000 0 0 0
Address field [6:0]
TETRA Baseband Processor FX980
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PowerDownCtrl
Title: Power Control register
Address: $0x02
Function: RW
Description: This register, together with the following bits, controls the power saving features:
TxEn bit of register TxSetup
RxEn bit of register RxSetup1
TxClkStop bit of register TxSetup
RxClkStop bit of register RxSetup1
Bit Name Active State Function
7 RW Reserved. Set this bit Low. Undefined on read.
6 BiaslCtrl High RW When set active, increases Tx and Rx analogue bias
currents.
5 BiasPowDn Low RW When set active powers down the analogue bias section.
4 AuxDac4PowDn Low RW When set active powers down Auxiliary Dac4.
3 AuxDac3PowDn Low RW When set active powers down Auxiliary Dac3.
2 AuxDac2PowDn Low RW When set active powers down Auxiliary Dac2.
1 AuxDac1PowDn Low RW When set active powers down Auxiliary Dac1.
0 RxAafPowDn Low RW When set active powers down the receive analogue
anti-alias filter (AAF).
• Address and Data format for PowerDownCtrl access
Data field [7:0]
R D6 D5 D4 D3 D2 D1 D00100 0 0 0
Address field [6:0]
TETRA Baseband Processor FX980
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TxSetup
Title: Transmit Set-up register
Address: $0x03
Function: RW
Description: Sets up the transmit functions.
Bit Name Active State Function
7:4 RW Reserved. Set these bits Low. Undefined on read.
3 TxClkStop High RW When set active causes the TxEn bit to also be used to
gate the Tx Data path master clock. When inactive (default
state) the Tx Data path master clock is always supplied.
2 TxEn High RW When set active, enables the Tx Data path, allowing
transmission to start when the correct enable sequence
has been seen. This bit may only be cleared when the
TxPathEn status bit in the TxFIFOStatus register is
inactive, setting inactive during a transmission cycle will
cause erroneous behaviour. This bit also acts as a transmit
section power enable bit.
1 TxRampEn High RW When set active, this bit enables the transmit amplitude
ramping function. Ramping is then controlled by the
TxRampUp bit of the TxData register When this bit is
inactive, the TxRampUp bit will directly control the transmit
amplitude (High meaning full amplitude, Low meaning zero
amplitude).
0 TxFirCoeffReset Low RW When set active this bit forces all the Tx Data path filters to
load their default coefficient values. This bit will be set
active on taking N_RESET Low, and therefore needs to be
deactivated before default filter coefficients can be
overwritten.
• Address and Data format for TxSetup access
Data field [7:0]
R R R R D3 D2 D1 D01100 0 0 0
Address field [6:0]
TETRA Baseband Processor FX980
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TxData
Title: Transmit Data register
Address: $0x04 - $0x07 (Mapped over four locations, two address bits being used as data bits)
Function: W FIFO input
R FIFO output
Description: This transmit data register is 10 bits wide. The two least significant bits of the address bus are
used to drive bits 8 and 9, hence it can be considered to be mapped over four consecutive
locations. This data word is written into a FIFO. The function is only decoded when the FIFO is
read (there is an exception for the first data word). The FIFO will be read when the Tx Data path
demands data. This will only occur when the TxEn bit of the TxSetup register is set active. For
test purposes the FIFO data output may be accessed by reading these registers.
Data write with symbol modulator not bypassed
Bit Name Active State Function
9 TxRampUp High W This bit is written to the FIFO. While the TxEn bit of the
TxSetup register is active, it controls the Tx Data path
ramping. Setting it active will cause the amplitude to ramp
up to its full value, conversely setting the bit inactive will
cause the amplitude to ramp down to its minimum value. If
the bit is changed while the amplitude is being ramped, the
ramp direction will change to the direction set by this bit.
While the TxRampEn bit is inactive, the TxRampUp bit will
directly control the transmit amplitude (High meaning full
amplitude and Low meaning zero amplitude).
8 MultiSymbol High W This bit is written to the FIFO and when this bit is set
active, the FIFO symbol data will be marked as a four
symbol word. When set inactive, the FIFO symbol data
will be marked as a single symbol word. This bit is inactive
if the SymbModuBypass bit of the ConfigCtrl1 register is
active.
7:6 TxRelSymbol4 Data W Fourth symbol in word to be written to FIFO.
5:4 TxRelSymbol3 Data W Third symbol in word to be written to FIFO.
3:2 TxRelSymbol2 Data W Second symbol in word to be written to FIFO.
1:0 TxRelSymbol1 Data W First symbol in word to be written to FIFO.
Data write with symbol modulator bypassed
Bit Name Active State Function
9 TxRampUp High W (See above)
8:3 (not used) Data W Redundant data which is still written into the FIFO. Set
these bits Low.
2:0 TxAbsSymbol Data W IQ constellation point which is written into the FIFO.
TETRA Baseband Processor FX980
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Read operation
Bit Name Active State Function
Address $0x04
7:2 Reserved. Bit values are not defined.
1:0 UpperFIFORdData Data R Reads address access bits 9 and 8 of the FIFO data output
register, these are placed in bits 1 and 0.
Address $0x05
7:0 LowerFIFORdData Data R Reads address access bits 7 to 0 of the FIFO data output
register. Reading this location also performs a FIFO read
operation, thereby moving the next (if any) FIFO data
location into the FIFO data output register.
Address $0x06 and $0x07
7:0 R Reserved. Bit values are not defined.
For these read operations to be valid, the Tx Data path must be active (TxEn bit of TxSetup register set
active) and the SymbModuBypass bit of the ConfigCtrl1 register must also be set active.
TETRA Baseband Processor FX980
1997 Consumer Microcircuits Limited 26 D/980/3
Address and Data format for TxData Write access
D8
Data field [7:0]
D910000Address field [6:0]
D1D0D7D6D5D4D3
D2
MultiSymbol bit
TxRampUp bit
Address and Data format for TxData (Modulator Bypass Mode) Write access
NU
Data field [7:0]
D910 0 0 0
Address field [6:0]
D1 D0NU NU NU NU NU D2
Not Used
TxRampUp bit
Address and Data format for TxData Read access
Data field [7:0]
0010 0 0 0
Address field [6:0]
D9 D8R R R R R R
D1 D0D7 D6 D5 D4 D3 D21010 0 0 0
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