Consumer Microcircuits Limited FX828P4, FX828D5, FX828D2 Datasheet
CML Semiconductor Products
CTCSS/DCS/SELCALL Processor FX828
1997 Consumer Microcircuits Limited
D/828/3 July 1997
1.0 Features Provisional Issue
•• Fast CTCSS Detection •• Programmable Tone Decoder
•• Full 23/24 Bit DCS Codec •• Programmable Comparator for RSSI
•• Non-Predictive Tone Detection •• Programmable Modulator Drivers
•• Low Power 3.3V/5V Operation •• Programmable Tone Encoders
•• Variable Gain Audio Filter •• Full Duplex CTCSS and Selcall
1.1 Brief Description
The FX828 is an innovative CTCSS, DCS and Selcall Codec, designed for the latest generation of Land Mobile
Radio equipment. Designed to complement the FX829, the FX828 has many advanced features which assist
the operation of modern SUBAUDIO and INBAND based signalling systems. The FX828 is electrically,
physically and software compatible with the FX818 and FX829. It permits manufacturers to add new features
to their equipment with minimal design changes.
The FX828 incorporates a programmable tone decoder which can be set to respond to between 1 and 15
CTCSS or Selcall tones with minimum software intervention. In addition, a 'Fast' CTCSS detector can respond
to a single programmed tone in 60 ms, or can be used to provide an output if any CTCSS tone is present at the
detector input. Two high resolution tone encoders perform accurate generation of any CTCSS or Selcall tone
in current use. Full 23 or 24 bit DCS encoding and decoding complements the CTCSS/Selcall line-up. A timer
is included which, for example, may be used for timing Selcall transmissions and a comparator is provided to
assist with carrier or RSSI monitoring. The device can operate full duplex in all operating modes except for
DCS.
The FX828 along with the FX818 and FX829 is offered in a choice of small SSOP, DIL and SOIC 24-pin
packages. It may be used with 3.0 to 5.5 volt supply.
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CONTENTS
Section Page
1.0 Features ..........................................................................................................1
1.2 Block Diagram................................................................................................3
1.3 Signal List.......................................................................................................4
1.3 Signal List.......................................................................................................4
1.4 External Components.................................................................................... 6
1.4 External Components.................................................................................... 6
1.5 General Description....................................................................................... 7
1.5.1 Software Description.....................................................................7
1.6 Application Notes......................................................................................... 20
1.6.1 General..........................................................................................20
1.6.2 Transmitter ...................................................................................20
1.6.3 Receiver (Decode)........................................................................21
1.6.4 Receiver (Fast Detect) .................................................................21
1.6.5 Receiver (DCS Decoder)..............................................................21
1.6.6 General Purpose Timer................................................................22
1.6.7 Full Duplex Modes .......................................................................22
1.6.8 Tx / Fast Rx Tone Table...............................................................23
1.6.9 Rx Program Tone Table...............................................................23
1.6.10 Tx Tone Program Table : Selcall...............................................24
1.6.11 Rx Tone Program Table : Selcall ..............................................25
1.6.12 Tx DCS Code Table....................................................................26
1.7 Performance Specification..........................................................................27
1.7.1 Electrical Performance ................................................................27
1.7.2 Packaging .....................................................................................33
Note: As this product is still in development, it is likely that a number of changes and additions will be made to
this specification. Items marked TBD or left blank will be included in later issues.
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1.2 Block Diagram
Figure 1 Block Diagram
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1.3 Signal List
Package
D2/D5/P4
Signal Description
Pin No. Name Type
1 XTALN O/P The inverted output of the on-chip oscillator.
2 XTAL/CLOCK I/P The input to the on-chip oscillator, for external
Xtal circuit or clock.
3 SERIAL CLOCK I/P The "C-BUS" serial clock input. This clock,
produced by the µController, is used for transfer
timing of commands and data to and from the
device. See "C-BUS" Timing Diagram (Figure
4).
4 COMMAND DATA I/P The "C-BUS" serial data input from the
µController. Data is loaded into this device in
8-bit bytes, MSB (B7) first, and LSB (B0) last,
synchronised to the SERIAL CLOCK. See
"C-BUS" Timing Diagram (Figure 4).
5 REPLY DATA O/P The "C-BUS" serial data output to the
µController. The transmission of REPLY DATA
bytes is synchronised to the SERIAL CLOCK
under the control of the CSN input. This 3-state
output is held at high impedance when not
sending data to the µController. See "C-BUS"
Timing Diagram (Figure 4).
6 CSN I/P The "C-BUS" data loading control function: this
input is provided by the µController. Data
transfer sequences are initiated, completed or
aborted by the CSN signal. See "C-BUS" Timing
Diagram (Figure 4).
7 IRQN O/P This output indicates an interrupt condition to the
µController by going to a logic "0". This is a
"wire-ORable" output, enabling the connection of
up to 8 peripherals to 1 interrupt port on the
µController. This pin has a low impedance
pulldown to logic "0" when active and a highimpedance when inactive. An external pullup
resistor is required.
The conditions that cause interrupts are
indicated in the IRQ FLAG register and are
effective if not masked out by a corresponding
bit in the IRQ MASK register.
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1.3 Signal List (continued)
Package
D2/D5/P4
Signal Description
Pin No. Name Type
8 COMPOUT O/P The output of the comparator.
9 COMPIN I/P The input to the comparator.
10 A/D CAP 1 O/P An internal reference voltage for the CTCSS A to
D. Decouple to V
SS
with an external capacitor.
11 A/D CAP 2 O/P An internal reference voltage for the DCS A to
D. Decouple to V
SS
with an external capacitor.
12 V
ss
Power The negative supply rail (ground).
13 V
BIAS
O/P A bias line for the internal circuitry, held at ½
V
DD
. This pin must be decoupled by a capacitor
mounted close to the device pins.
14 RX AMP IN I/P The inverting input to the Rx input amplifier.
15 RX AMP OUT O/P The output of the Rx input amplifier and the input
to the audio filter section.
16 RX AUDIO OUT O/P Output of the Rx audio filter section.
17 TX AUDIO OUT O/P Output of the selcall tone generator.
18 SUM IN I/P Input to the audio summing amplifier.
19 SUM OUT O/P Output of the audio summing amplifier.
20 MOD1 IN I/P Input to MOD1 audio gain control.
21 TX SUB AUDIO OUT O/P Output of the CTCSS or DCS Tx tone generator.
22 MOD1 O/P Output of MOD1 audio gain control.
23 MOD2 O/P Output of MOD2 audio gain control.
24 V
DD
Power The positive supply rail. Levels and voltages are
dependent upon this supply. This pin should be
decoupled to V
SS
by a capacitor.
Notes: I/P = Input
O/P = Output
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1.4 External Components
C1 22pF ±20% R1 1M ±5% X1 4.032MHz
C2 22pF ±20% R2 100k
±10% (tolerance depends upon
C3 100pF ±20% R3 100k
±10% system requirements)
C4 0.1µF ±20% R4 Note 2 ±10%
C5 100pF ±20% R5 22k
±10%
C6 0.1µF ±20% R6 Note 1 ±10%
C7 Note 2 ±20% R7 Note 1 ±10%
C8 0.1µF ±20%
C9 1.0 to 3.3µF ±20%
Notes: 1. R2, R6, R7 and C3 form the gain components for the Summing Amplifier. R6 and R7 should be
chosen as required from the system specification, using the following formula:
Tx Sub Audio Gain =
−
R2
R6
Tx Audio Gain = −
R2
R7
2. R3, R4, C5 and C7 form the gain components for the Rx Input Amplifier. R4 should be chosen
as required by the signal level, using the following formula:
Gain =
−
R3
R4
C7 x R4 should be chosen so as not to compromise the low frequency performance of this
product.
Figure 2 Recommended External Components
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1.5 General Description
The FX828 is a signalling encoder/decoder for use in land mobile radio equipment, see Figure 1. The
transmitter section of this device has independently controllable tone generators for sub-audio
(CTCSS) and inband (Selcall) signalling. It also features a DCS code generator, which may be used in
place of the CTCSS tone generator.
The receiver section of the FX828 has a fast/predictive CTCSS tone detector which operates in parallel
with a DCS decoder and a CTCSS/Selcall tone decoder. The latter is switchable to perform either
CTCSS or Selcall tone decoding of a user-programmable set of up to 15 tones. In the CTCSS mode it
performs a more accurate (but slower) analysis of the tones detected by the fast/predictive CTCSS
tone detector, which is a single detector that is switchable to provide either a fast response to any
CTCSS tone (FAST DETECT mode) or a fast response to a single user-programmed CTCSS tone
(PREDICTIVE mode).
Other functions on the FX828 are a comparator with programmable threshold level, a general purpose
timer and a summing amplifier with two adjustable gain blocks, which may be used for two point
modulation, for example. All FX828 functions are controlled by an external µC over the C-BUS
interface, a serial interface designed to reduce interference levels in radio equipment.
1.5.1 Software Description
Address/Commands
Instructions and data are transferred, via "C-BUS", in accordance with the timing information given in
Figure 4.
Instruction and data transactions to and from the FX828 consist of an Address/Command (A/C) byte
followed by either:
(i) a further instruction or data (1 or 2 bytes) or
(ii) a status or Rx data reply (1 byte)
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8-bit Write Only Registers
HEX
ADDRESS/
COMMAND
REGISTER
NAME
BIT 7
(D7)
BIT 6
(D6)
BIT 5
(D5)
BIT 4
(D4)
BIT 3
(D3)
BIT 2
(D2)
BIT 1
(D1)
BIT 0
(D0)
$01 GENERAL N/A N/A N/A N/A N/A N/A N/A N/A
RESET
SUBAUDIO TONE FAST SELCALL DCS
$80 SIGNALLING TX DECODER DETECT TX RX
CONTROL ENABLE ENABLE ENABLE 0 0 ENABLE 0 ENABLE
TONE DECODER BANDWIDTH
FAST CTCSS
$82 SIGNALLING MSB LSB
MODE
TONE SUBAUDIO DCS
SET-UP BIT 3 BIT 2 BIT 1 BIT 0
DETECT/
PREDICTIVE
DECODER
MODE
TX MODE 23/24
DCS BYTE 3
$85 DCS
OPTIONAL
MSB
BYTE 3 BIT 23 BIT 22 BIT 21 BIT 20 BIT 19 BIT 18 BIT 17 BIT 16
DCS BYTE 2
$86 DCS
BYTE 2 BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8
DCS BYTE 1
$87 DCS LSB
BYTE 1 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
BPF MSB LSB
$88 GENERAL BPF BPF 6dB DAC DAC DAC GP TIMER GP TIMER
CONTROL ENABLE UN-MUTE PAD BIT 2 BIT 1 BIT 0 ENABLE RE-CYCLE
GENERAL
GENERAL PURPOSE TIMER
$8B PURPOSE MSB LSB
TIMER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
GP TIMER COMP COMP TONE CTCSS DCS
$8E IRQ 0 IRQ 0 to 1 1 to 0 IRQ FAST IRQ 0 IRQ
MASK MASK IRQ MASK IRQ MASK MASK MASK MASK
$9C
Reserved for later use
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16-bit Write Only Registers
HEX
ADDRESS/
COMMAND
REGISTER
NAME
BIT 7
(D7)
BIT 6
(D6)
BIT 5
(D5)
BIT 4
(D4)
BIT 3
(D3)
BIT 2
(D2)
BIT 1
(D1)
BIT 0
(D0)
CTCSS TX/
CTCSS TX/FAST RX FREQUENCY
$83 FAST RX CTCSS (TX) 0 0 MSB
FREQUENCY (1) NOTONE BIT 12 BIT 11 BIT 10 BIT 9 BIT 8
CTCSS TX/
CTCSS TX/FAST RX FREQUENCY
FAST RX LSB
FREQUENCY (2) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
RX TONE
TONE ADDRESS TONE FREQUENCY
$84 PROGRAM MSB LSB MSB
(1) BIT 3 BIT 2 BIT 1 BIT 0 BIT 11 BIT 10 BIT 9 BIT 8
RX TONE
TONE FREQUENCY
PROGRAM LSB
(2) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
AUDIO
MOD 1
$8A CONTROL 0 0 MOD 1 MSB LSB
(1) ENABLE BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
AUDIO
MOD 2
CONTROL 0 0 MOD 2 MSB LSB
(2) ENABLE BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
SELCALL TX TONE
$8D SELCALL TX SELCALL 0 0 MSB
(1) NOTONE BIT 12 BIT 11 BIT 10 BIT 9 BIT 8
SELCALL TX TONE
SELCALL TX LSB
(2) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
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Write Only Register Description
GENERAL RESET (Hex address $01)
The reset command has no data attached to it. It sets the device registers into the specific (all powersaved)
states as listed below:
REGISTER NAME HEX
ADDRESS
BIT 7
(D7)
BIT 6
(D6)
BIT 5
(D5)
BIT 4
(D4)
BIT 3
(D3)
BIT 2
(D2)
BIT 1
(D1)
BIT 0
D0)
SIGNALLING CONTROL $80 0 0 0 0 0 0 0 0
SELCALL & SUB-AUDIO STATUS $81 0 0 0 0 X X X X
SIGNALLING SET-UP $82 0 0 0 0 0 0 0 0
CTCSS TX / FAST RX
FREQUENCY
(1) $83 0 0 0 0 0 0 0 0
CTCSS TX / FAST RX
FREQUENCY
(2) 0 0 0 0 0 0 0 0
RX TONE PROGRAM (1) $84 0 0 0 0 0 0 0 0
RX TONE PROGRAM (2) 0 0 0 0 0 0 0 0
DCS BYTE 3 $85 0 0 0 0 0 0 0 0
DCS BYTE 2 $86 0 0 0 0 0 0 0 0
DCS BYTE 1 $87 0 0 0 0 0 0 0 0
GENERAL CONTROL $88 0 0 0 0 0 0 0 0
AUDIO CONTROL (1) $8A 0 0 0 0 0 0 0 0
AUDIO CONTROL (2) 0 0 0 0 0 0 0 0
GENERAL PURPOSE TIMER $8B 0 0 0 0 0 0 0 0
SELCALL TX (1) $8D 0 0 0 0 0 0 0 0
SELCALL TX (2) 0 0 0 0 0 0 0 0
IRQ MASK $8E 0 0 0 0 0 0 0 0
IRQ FLAG $8F 0 0 0 0 0 0 0 0
X = undefined
SIGNALLING CONTROL Register (Hex address $80)
This register is used to control the functions of the device as described below:
SUBAUDIO TX
ENABLE
(Bit 7)
Bit 7 should be set to “1” to enable the CTCSS/DCS subaudio transmitter. The
subaudio Tx type will depend on the state of the SUBAUDIO TX MODE (Bit 1
SIGNALLING SET-UP Register $82).
TONE DECODER
ENABLE
(Bit 6)
Bit 6 should be set to “1” to enable the CTCSS/Selcall tone decoder or the DCS
decoder. Note: See also Bit 0 for DCS decoder operation.
Bits 7 and 6 should not both be set to “1” when Bit 0 is set to “1” because the
DCS function is half-duplex only.
CTCSS FAST
DETECT ENABLE
(Bit 5)
When this bit is "1", the FAST CTCSS DETECT or FAST CTCSS PREDICTIVE
mode is enabled, depending upon the setting of FAST CTCSS MODE (Bit 3
SIGNALLING SET-UP Register, $82). When this bit is "0", both FAST CTCSS
DETECT and FAST CTCSS PREDICTIVE tone detectors are disabled.
SELCALL TX
ENABLE
(Bit 2)
When this bit is "1" the Selcall transmitter is enabled. When this bit is "0" the
Selcall transmitter is disabled and powersaved.
DCS RX ENABLE
(Bit 0)
When this bit is "1" and Bit 6 is “1”, the DCS decoder is enabled. When this bit is
"0" the DCS decoder is disabled.
The DCS decoder and the subaudio (CTCSS or DCS) transmitter should not be
enabled at the same time.
(Bits 4, 3, and 1) Reserved for future use. These bits should be set to "0".
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SIGNALLING SET-UP Register (Hex address $82)
This register is used to define the signalling parameters, as described below:
TONE DECODER
BANDWIDTH
(Bits 7, 6, 5 and 4)
These four bits set the bandwidth of the CTCSS/Selcall tone decoder according
to the table below:
BANDWIDTH
Bit 7 Bit 6 Bit 5 Bit 4 Will Decode Will Not Decode
Recommended for CTCSS 1 0 0 0 ±1.1% ±2.4%
Recommended for CCIR 1 0 0 1 ±1.3% ±2.7%
1 0 1 0 ±1.6% ±2.9%
1 0 1 1 ±1.8% ±3.2%
1 1 0 0 ±2.0% ±3.5%
1 1 0 1 ±2.2% ±3.7%
Recommended for ZVEI 1 1 1 0 ±2.5% ±4.0%
1 1 1 1 ±2.7% ±4.2%
FAST CTCSS MODE
(Bit 3)
When CTCSS FAST DETECT ENABLE (Bit 5 SIGNALLING CONTROL
Register, $80) is "1", this bit selects the FAST CTCSS DETECT or the FAST
CTCSS PREDICTIVE mode, according to the table below:
DETECT/
PREDICTIVE
Bit 3
Function
0 DETECT mode
1 PREDICTIVE mode
If the CTCSS FAST DETECT ENABLE bit is "0" then both modes are
deselected.
TONE DECODER
MODE
(Bit 2)
When this bit is "1" the CTCSS/Selcall tone decoder is set to detect inband
(Selcall) tones. When this bit is "0" the tone decoder is set to detect subaudio
(CTCSS) tones.
SUBAUDIO TX MODE
(Bit 1)
When this bit is "1" the subaudio transmitter will be set to transmit DCS signals, if
enabled. When this bit is "0" the subaudio transmitter will be set to transmit
CTCSS signals, if enabled.
DCS 23/24
(Bit 0)
When this bit is "1" the DCS transmitter and decoder are configured for a 23-bit
code. When this bit is "0" they are configured for a 24-bit code.
DCS BYTE 3 Register (Hex address $85)
DCS BYTE 2 Register (Hex address $86)
DCS BYTE 1 Register (Hex address $87)
These three bytes set the code that is transmitted or received in the DCS mode. The LSB bit "0" of the DCS
BYTE 1 is transmitted first and the last bit is the MSB bit 23 of DCS BYTE 3 in the 24-bit mode or bit 22 in the
23-bit mode.
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