The FX663 decodes the standard audible tone signals provided by telecom systems worldwide to indicate Dial,
Ringing, Busy, Unobtainable and other stages of a call attempt. It provides the key features needed for
intelligent, full-function, call progress monitoring by applications involving machine dialling or automatic call
placement. The FX663 also incorporates the following features:
•Single and dual tone decoding for better cross-system Call Progress monitoring.
•"US Busy" tone detector, saving time needed for "cadence verification" under Busy and Unobtainable
conditions. This incorporates a separate 620Hz detector for improved response.
•A detector to indicate speech and non-call progress signals; this reduces voice falsing of call progress
tones and adds Voice-Answer detection as a "connected" prompt.
•A fax and modem tone decoder.
•A separate, adjustable threshold, signal-level detector which reduces noise falsing.
The FX663 uses new digital signal processing techniques to provide these advantages. It is a low cost, low
power product with superior performance. It is available in industry standard 16-pin packages.
1XTALNO/PThe inverted output of the on-chip oscillator.
2XTAL/CLOCKI/PThe input to the on-chip oscillator, for external
Xtal circuit or clock.
3
4
5
6
D3
D2
D1
D0
O/P
O/P
O/P
O/P
D3, D2, D1 and D0 is a 4-bit parallel data word
output to the µController. The transmission of
data is under the control of the CSN input.
These 3-state outputs are held at high
impedance when CSN is at "1". See Bus Timing
Diagram (Figure 8).
If CSN is permanently at "0", D3, D2, D1 and D0
are permanently active. See Timing Diagram
(Figure 4 to 7).
7CSNI/PThe data output control function: this input is
provided by the µController. Data transfer
sequences are initiated, completed or aborted
by the CSN signal. See Bus Timing Diagram
(Figure 8).
8IRQNO/PThis output indicates an interrupt condition to
the µController by going to a logic "0". This is a
"wire-ORable" output, enabling the connection of
up to 8 peripherals to 1 interrupt port on the
µController. This pin has a low impedance
pulldown to logic "0" when active and a highimpedance when inactive. An external pullup
resistor is required.
If CSN is permanently at "0", the interrupt
condition is a logic "0" pulse. See Timing
Diagram (Figure 4 to 7).
9ENABLEI/PA low level input selects the powersave mode,
all circuits are reset and disabled. D0 - D3
outputs become high impedance. A high level
enables all circuits. (See also CSN).
1997 Consumer Microcircuits Limited4D/663/2
Call Progress DecoderFX663
1.3Signal List (continued)
Package
D4/P3
SignalDescription
Pin No.NameType
10V
ss
PowerThe negative supply rail (ground).
11SIGINI/PSignal input. The signal to this pin should be ac
coupled. The dc bias of this pin is set internally.
12V
BIAS
O/PInternally generated bias voltage, held at V
when the device is not in powersave mode. It
should be decoupled to Vss by a capacitor
mounted close to the device pins. In powersave
mode this pin is pulled towards V
SS
.
13AMPNINVI/PThe non-inverting input to the on-chip amplifier.
14AMPINVI/PThe inverting input to the on-chip amplifier.
15AMPOPO/PThe output of the on-chip amplifier, this is
internally connected to the input of the Level
Detector.
16V
DD
PowerThe positive supply rail. Levels and voltages are
dependent upon this supply. This pin should be
decoupled to V
by a capacitor.
SS
DD /2
Notes: I/P=Input
O/P =Output
1997 Consumer Microcircuits Limited5D/663/2
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