Consumer Microcircuits Limited FX641P4, FX641D2 Datasheet

4.1

PRODUCT INFORMATION

FX641

Dual Subscriber Private
Metering (SPM) Detector

Selectable Tone Follower or
Packet Mode Outputs

High Speech-Band Rejection
Properties

“Output Enable” Multiplexing
Facility

Call-Charge Applications on
PABX Line Cards

+

-

+

-

Ch 2

BANDPASS

FILTER

Ch 2

INPUT

AMPLIFIER

CHANNEL 2

CHANNEL 1

Ch 2AMP OUT

Ch2 AMP IN (-)

Ch2 AMP IN (+)

Ch 2

OUTPUT

Ch 2

COMPARATOR

PULSE

GENERATOR

AND

DIVIDER

PULSE

MEASUREMENT

LOGIC

PULSE

LENGTH

LOGIC

OUTPUT
SELECT

CIRCUITS

+

-

+

-

Ch 1

BANDPASS

FILTER

XTAL/CLOCK
GENERATOR

XTAL/CLOCK

CLOCK OUT CLOCK IN

V

DD

V

BIAS

V

SS

BUFFER

CLOCK

DIVIDERS

LEVEL/
SYSTEM
SETTING

SERIAL

INPUT
LOGIC

SERIAL

DATA

SERIAL
CLOCK

PRESET LEVEL

SYSTEM SELECT

Ch 1

INPUT

AMPLIFIER

12kHz/16kHz

SYSTEM

12kHz/16kHz

SYSTEM

12kHz/16kHz

SYSTEM

TONE FOLLOWER

MODE

TONE FOLLOWER

MODE

PACKET

MODE

PACKET

MODE

INTERNAL

CLOCKS

INTERNAL

COMPARATOR

THRESHOLD

INTERNAL

COMPARATOR

THRESHOLD

GAIN

ADJUST

GAIN

ADJUST

Ch 1 AMP OUT

Ch1 AMP IN (-)

Ch1 AMP IN (+)

Ch 1

OUTPUT

OUTPUT

SELECT

Ch 1

COMPARATOR

PULSE

GENERATOR

AND

DIVIDER

PULSE

MEASUREMENT

LOGIC

PULSE

LENGTH

LOGIC

OUTPUT
SELECT

CIRCUITS

XTAL

OUTPUT
ENABLE

CHIP SELECT

Brief Description

The FX641 is a low-power, system-selectable Dual

Subscriber Private Metering (SPM) Detector

-two

detectors on a single chip-

to indicate the presence,
on a telephone line, of either 12kHz or 16kHz
telephone call-charge frequencies.

Under µProcessor control via a common serial
interface, each channel of the FX641 will detect
call-charge pulses from a telephone line and provide a
digital output for recording, billing or security
purposes.

A common set of external components and a stable

3.579545MHz Xtal/clock input ensures that the FX641
adheres accurately to most national “Must and Must­Not” decode band-edges and threshold levels.

CML Semiconductor Products

FX641

Fig.1 Functional Block Diagram

The digital output is pin-selectable to one of three
modes:

(1) Tone Follower mode -a logic level for the period of

a correct decode.

(2) Packet mode -respond/de-respond after a

cumulative period of tone or notone in a preset
period.

(3) High-impedance output -for device multiplexing.
For non-µProcessor systems a preset sensitivity/system
input allows external channel level and system setting.

This device, which is suitable for PBX and PABX
line-card and remote telephone installations, is available
in compact 24-pin plastic DIL and small outline (S.O.I.C.)
packages.
The FX641 requires approximately 4.5mA at 5-volts.

Features

Two (12kHz/16kHz) SPM
Detectors on a Single Chip

Detects 12kHz and 16kHz SPM
Frequencies

Xtal Accuracy; Stable Frequency
Limits

“Controlled” (µC) and “Fixed”
Signal Sensitivity Modes

Publication D/641/3 November 1997
Provisional Issue

4.2

Pin Number Function

FX641
D2/P4

1

2

3

4

5

6

7

8

9

10

11

12

Xtal/Clock: The input to the on-chip clock oscillator; for use with a 3.579545MHz Xtal in conjunction

with the Xtal output; circuit components are on-chip. When using a Xtal input, the Clock Out pin
should be connected directly to the Clock In pin. If a clock pulse input is employed to the Clock In pin,
this (Xtal/Clock) pin must be connected directly to V

DD

(see Figure 2). See Figure 4 for details of clock

frequency distribution.

Xtal: The output of the on-chip clock oscillator inverter.

Clock Out: The buffered output of the on-chip-clock oscillator inverter. If a Xtal input is employed,

this output should be connected directly to Clock In pin. This output can support up to 3 additional
FX641 microcircuits. See Figure 4 for details of clock frequency distribution.

Clock In: The 3.579545 clock pulse input to the internal clock dividers. If an externally generated
clock pulse input is employed, the Xtal/Clock input pin should be connected to VDD.

Output Enable: For multi-chip output multiplexing; controls the state of both Ch1 and Ch2 outputs.
When this input is placed high (logic '1') both outputs are set to a high impedance. When placed low
(logic '0') both outputs are enabled.

Ch 2 Output: The digital output of the Channel 2 SPM detector when enabled. The format of the
signal at this pin, in common with Ch 1, is selectable to either 'Tone Follower' or 'Packet' mode via the
Output Select input.

Ch 1 Output: The digital output of the Channel 1 SPM detector when enabled. The format of the
signal at this pin, in common with Ch 2, is selectable to either 'Tone Follower' or 'Packet' mode via the
Output Select input.

V

BIAS

: The output of the on-chip analogue bias circuitry. Held internally at VDD/2, this pin should be

decoupled to VSS (see Figure 2).

Ch 1 Amp Out: The output of the Channel 1 Input Amplifier. See Figures 2 and 3.

Ch 1 Amp In (-): The negative input to the Channel 1 Input Amplifier. See Figures 2 and 3.

Ch 1 Amp In (+): The positive input to the Channel 1 Input Amplifier. See Figures 2 and 3.

VSS: Negative supply rail (GND).

4.3

FX641
D2/P4

13

14

15

16

17

18

19

20

21

22

23

24

No internal connection; leave open circuit.

Ch 2 Amp In (+): The positive input to the Channel 2 Input Amplifier. See Figures 2 and 3.

Ch 2 Amp In (-): The negative input to the Channel 2 Input Amplifier. See Figures 2 and 3.

Ch 2 Amp Out: The output of the Channel 2 Input Amplier. See Figures 2 and 3.

Output Select: A logic input to set the Channel 1 and Channel 2 output modes.

When high (logic '1'), the outputs are in the Tone Follower mode; when low (logic '0'), the outputs are
in the Packet mode.

Preset Level: A logic input to set the sensitivity mode of the FX641.
When high (logic '1'), both channels are in the Fixed Sensitivity mode. The external components
govern the input sensitivity; the System Select input selects 12kHz or 16kHz operation. When low
(logic '0'), both channels are in the Controlled Sensitivity mode. Device sensitivities and system
selection are via the Chip Select/Serial Data/Serial Clock inputs. This input has an internal pullup
resistor on chip (Fixed Sensitivity Mode).

Chip Select: The Chip Select input for use in data loading when using the FX641 in the Controlled
Sensitivity mode (see Figure 9).
The device is selected when this input is set low (logic '0').
When the device is in the Fixed Sensitivity mode this input should be connected to either VSS or VDD.

Serial Clock: The Serial Clock input for use in data loading when using the FX641 in the Controlled
Sensitivity mode (see Figure 9). Data is loaded to the FX641 on this clock's rising edge.
When the device is in the Fixed Sensitivity mode this input should be connected to either VSS or VDD.

Serial Data: The Serial Data input for use in data loading when using the FX641 in the Controlled
Sensitivity mode (see Figure 9 and Table 2).
When the device is in the Fixed Sensitivity mode this input should be connected to either VSS or VDD.

System Select: In the Fixed Sensitivity mode this pin selects the system frequency.
High (logic ‘1’) = 12kHz; Low (logic ‘0’) = 16kHz.
In the Controlled Sensitivity mode this pin is inactive and may be left unconnected.
This pin has an internal pullup resistor on chip.

No internal connection; leave open circuit.

VDD: Positive supply rail; a single, stable power supply is required. Critical levels and voltages within
the FX641 are dependant upon this supply. This pin should be decoupled to VSS by a capacitor
mounted close to the pin.

Pin Number Function

4.4

Application Information

Fig.3 Example Input Configurations

+

-

Tip (a)

Ring (b)

INPUT AMP

FX641 (par t)

FX641 (par t)

V

BIAS

V

SS

+

-

INPUT AMP

V

BIAS

V

SS

Common Mode Input

XTAL

XTAL/CLOCK

XTAL/CLOCK

For use with a Clock Pulse input

- Remove Xtal (X

1

)

- Connect Pin 1 to V

DD

- Remove link (Pins 3/4)

- Input clock pulses to CLOCK IN
See Figure 4

CLOCK IN

IN

OUT

CLOCK

Ch2 OUTPUT
Ch1 OUTPUT

Ch1 AMP IN (+)

V

BIAS

V

DD

V

DD

V

SS

V

SS

V

SS

C

1

X

1

R

3

R

1

R

2

R

4

R

8

R

6

C

6

C

5

R

5

C

3

C

4

C

2

R

7

FX641D2

1
2
3

11
12

24
23
22

21
20
19

18

17
16
15
14
13

4
5
6
7
8
9
10

OUTPUT ENABLE

Ch1 AMP OUT

Ch1 AMP IN (-)

Ch2 AMP OUT

OUTPUT SELECT

PRESET LEVEL

SERIAL CLOCK

SERIAL DATA

SYSTEM SELECT

Ch2 AMP IN (-)

Ch2 AMP IN (+)

CHIP SELECT

Component Value Tolerance

R

1

68kΩ ± 1%

R

2

68kΩ ±1%

R

3

750kΩ ±1%

R

4

750kΩ ±1%

R

5

68kΩ ± 1%

R

6

68kΩ ± 1%

R

7

750kΩ ±1%

R

8

750kΩ ±1%

C

1

1.0µF ±20%

C

2

1.0µF ±20%

C

3

270pF ±5%

C

4

270pF ±5%

C

5

270pF ±5%

C

6

270pF ±5%

X

1

3.579545MHz

Fixed Sensitivity Setting

Note that when calculating/selecting gain components, R3, R4, R7 and R8 should always be greater than or equal to
100kΩ.

Differential Input

Fig.2 Recommended External Components