Consumer Microcircuits Limited FX629J Datasheet

CML Semiconductor Products

PRODUCT INFORMATION

FX629

Features/Applications

Designed to Meet Mil-Std-188-113
Military Communications

Delta MUX, Switch and Phone
Applications

Single-Chip Full-Duplex Codec
On-Chip Input and Output Filters

DATA ENABLE
ENCODER FORCE IDLE

ENCODER INPUT
V

DD

V

SS

f

XTAL/CLOCK

XTAL
ENCODER DATA CLOCK

DECODER DATA CLOCK
V

BIAS

MODE 1
MODE 2

ALGORITHM

1

CLOCK MODE
LOGIC

f

0

CLOCK RATE
GENERATORS

SAMPLING RATE

CONTROL

Delta Modulation Codec

Publication D/629/2 July 1994

Provisional Issue

Programmable Sampling Clocks
3 or 4-bit Compand Algorithm
Forced Idle Facility
Powersave Facility
Single 5V CMOS Process

Full-Duplex CVSD* Codec

MOD

f

2

ENCODER OUTPUT

FX629

3 or 4-BIT

POWERSAVE

DECODER INPUT

DECODER FORCE IDLE

Fig.1 Internal Block Diagram

f

3

DEMOD

Brief Description

The FX629 is an LSI circuit designed as a
*Continuously Variable Slope Delta Codec and
is intended for use in military communications
systems.
Designed to meet Mil-Std-188-113 with
external components, the device is suitable for
applications in military Delta Multiplexers,
switches and phones.
Encoder input and decoder output filters are
incorporated on-chip. Sampling clock rates can
be programmed to 16, 32 or 64 k bits/second
from an internal clock generator or may be
externally applied in the range 8 to 64 k bits/
second. Sampling clock frequencies are output
for the synchronization of external circuits.

f

1

DECODER OUTPUT

The encoder has an enable function for use in
multiplexer applications.
Encoder and Decoder forced idle facilities are

provided, forcing a 10101010..... pattern in

encode and a VDD/2 bias in decode.
The companding circuits may be operated with
a pin-selected 3 or 4-bit algorithm.
The powersave facility puts the device into the
standby mode thereby reducing current
consumption when not operating.
A reference 1.024MHz oscillator uses an
external clock pulse or Xtal input.
The FX629 is a low-power, 5 volt CMOS
device and is available in 22-pin cerdip DIL
package.

Pin Number Function

FX629J

1

Xtal/Clock : Input to the clock oscillator inverter. A 1.024MHz Xtal input or externally

derived clock is injected here. See Clock Mode pins and Figure 3.

2

Xtal : Output of clock oscillator inverter. Xtal circuitry shown is in accordance with CML

application note D/XT/1 April 1986.

3

4

No connection

Encoder Data Clock : A logic I/O port. External encode clock input or internal data clock
output. Clock frequency is dependant upon clock mode 1, 2 inputs and Xtal frequency (see
Clock Mode pins).

5

Encoder Output : The encoder digital output, this is a three state output whose condition is

set by Data Enable and Powersave inputs as shown :

Data Enable Powersave Encoder Output

1 1 Enabled
0 1 High Z (o/c)
1 0 Vss

10

11

6

Encoder Force Idle : When this pin is a logical '0' the encoder is forced to an idle state and

the encoder digital output is 0101..., a perfect idle pattern. When this pin is a logical '1' the
encoder encodes as normal. Internal 1MΩ Pullup.

7

Data Enable : Data is made available at the encoder output pin by control of this input. See

Encoder Output pin. Internal 1MΩ Pullup.

8

9

No connection

Bias : Normally at V

. Internally pulled to VSS when "Powersave" is a logical '0'.

C

4

Encoder Input : The analogue signal input. Internally biased at V
are required on this input. The source impedance should be less than 100Ω, output idle

/2 bias, this pin requires to be externally decoupled by a capacitor,

DD

/2, external components

DD

channel noise levels will improve with an even lower source impedance. See Fig. 3.

: Negative Supply.

V

SS

2

Pin Number Function

FX629J

12

13

14

15

16

No connection

Decoder Output : The recovered analogue signal is output at this pin, it is the buffered
output of a bandpass filter and requires external components. During "Powersave" this
output is o/c.

No connection

Powersave : A logical '0' at this pin puts most parts of the codec into a quiescent non­operational state. When at a logical '1' the codec operates normally. Internal 1MΩ Pullup.

Decoder Force Idle : A logical '0' at this pin gates a 0101...pattern internally to the
decoder so that the decoder output goes to V
decoder operates as normal. Internal 1MΩ Pullup.

/2. When this pin is at a logical '1' the

DD

17

18

19

20
21

Decoder Input : The received digital signal input. Internal 1MΩ Pullup.

Decoder Data Clock : A Logic I/O port. External decode clock input or internal data clock

output, dependant upon clock mode 1, 2 inputs, see Clock Mode pins.

Algorithm : A logical '1' at this pin sets this device for a 3-bit companding algorithm. A
logical '0' sets a 4-bit companding algorithm. Internal 1MΩ Pullup.

Clock Mode 2 :

Clock Mode 1 Clock Mode 2 Facility

Clock Mode 1 : 0 0 External clocks

Internal 1MΩ 0 1 Internal, 64kb/s = f ÷ 16
Pullups. 1 0 Internal, 32kb/s = f ÷ 32

1 1 Internal, 16kb/s = f ÷ 64

Clock rates refer to f = 1.024 MHz Xtal/clock input. During internal operation the data clock
frequencies are available at the ports for external circuit synchronization.
Independent or common data rate inputs to Encode and Decode data clock ports may be
employed in the External Clocks mode. Optimum performance will be achieved when the
applied external clocks are synchronous with the master Xtal/clock, and a sub-multiple of
128kHz.

22

: Positive Supply. A single + 5 volt power supply is required.

V

DD

3