Consumer Microcircuits Limited FX619M1, FX619L2, FX619L1, FX619J Datasheet
6.1
The encoder has an enable function for use in
multiplexer applications. Encoder and Decoder
forced idle facilities are provided forcing a
10101010..... pattern in encode and a VDD/2
bias in decode. The companding circuits may
be operated with a 3 or 4-bit algorithm which is
externally selected. The device may be put in
the standby mode by selection of the
powersave facility. A reference 1.024MHz
oscillator uses an external clock or Xtal.
The FX619 is a low-power, 5 volt CMOS
device and is available in 22-pin cerdip DIL,
24-lead/pin plastic and 28-lead ceramic
leadless SMT packages.
FX619 'Eurocom' Delta Codec
CML Semiconductor Products
PRODUCT INFORMATION
The FX619 is an LSI circuit designed as a
*Continuously Variable Slope Delta Codec and
is intended for use in military communications
systems.
Designed to meet Eurocom D1-IA8 with
external components, the device is suitable for
applications in military Delta Multiplexers,
switches and phones.
Encoder input and decoder output filters are
incorporated on-chip. Sampling clock rates can
be programmed to 16, 32 or 64 k bits/second
from an internal clock generator or may be
externally applied in the range 8 to 64 k bits/
second. Sampling clock frequencies are output
for the synchronization of external circuits.
Brief Description
Fig.1 Internal Block Diagram
DECODER DATA CLOCK
MODE 2
MODE 1
ENCODER DATA CLOCK
XTAL
DATA ENABLE
ENCODER FORCE IDLE
DECODER INPUT
MOD
ENCODER INPUT
DEMOD
XTAL/CLOCK
ENCODER OUTPUT
DECODER OUTPUT
CLOCK RATE
GENERATORS
SAMPLING RATE
CONTROL
ALGORITHM
POWERSAVE
3 or 4-BIT
CLOCK MODE
LOGIC
DECODER FORCE IDLE
f
3
f
1
V
SS
V
DD
V
BIAS
f
0
f
1
f
2
FX619
Publication D/619/6 September 1997
Features/Applications
Designed to Meet Eurocom D1-IA8f
Meets Stanag 4209 and
Stanag 4380
Delta MUX, Switch and Phone
Applications
Single Chip Full Duplex Codec
Military Communications
Powersave Facility
Single 5V CMOS Process
Full Duplex CVSD* Codec
Programmable Sampling Clocks
3 or 4-bit Compand Algorithm
Forced Idle Facility
On-Chip Input and Output Filters
2
Pin Number Function
Xtal/Clock : Input to the clock oscillator inverter. A 1.024MHz Xtal input or externally
derived clock is injected here. See Clock Mode pins and Figure 3.
No connection
Xtal : Output of clock oscillator inverter. Xtal circuitry shown is in accordance with CML
application note D/XT/1 April 1986.
No connection
Encoder Data Clock : A logic I/O port. External encode clock input or internal data clock
output. Clock frequency is dependant upon clock mode 1, 2 inputs and Xtal frequency (see
Clock Mode pins).
Encoder Output : The encoder digital output, this is a three state output whose condition is
set by Data Enable and Powersave inputs as shown :
Data Enable Powersave Encoder Output
1 1 Enabled
0 1 High Z (o/c)
1 0 Vss
No connection
Encoder Force Idle : When this pin is a logical '0' the encoder is forced to an idle state and
the encoder digital output is 0101..., a perfect idle pattern. When this pin is a logical '1' the
encoder encodes as normal. Internal 1MΩ Pullup.
Data Enable : Data is made available at the encoder output pin by control of this input. See
Encoder Output pin. Internal 1MΩ Pullup.
No connection
Bias : Normally at VDD /2 bias, this pin requires to be externally decoupled by a capacitor,
C4. Internally pulled to VSS when "Powersave" is a logical '0'.
Encoder Input : The analogue signal input. Internally biased at VDD /2, external
components are required on this input. The source impedance should be less than 100Ω,
output idle channel noise levels will improve with an even lower source impedance. See
Fig. 3.
VSS : Negative Supply.
FX619
J
1
2
3
4
5
6
7
8
9
10
11
FX619
L1/L2
1
2
3
4
5
6
7
8
9
10
11
12
FX619
M1
1
2
3
4
5
6
7, 8
9
10
11
12
13
14
3
Pin Number Function
No connection
Decoder Output : The recovered analogue signal is output at this pin, it is the buffered
output of a bandpass filter and requires external components. During "Powersave" this
output is o/c.
No connection
Powersave : A logical '0' at this pin puts most parts of the codec into a quiescent nonoperational state. When at a logical '1' the codec operates normally. Internal 1MΩ Pullup.
No connection
Decoder Force Idle : A logical '0' at this pin gates a 0101...pattern internally to the
decoder so that the decoder output goes to VDD/2. When this pin is at a logical '1' the
decoder operates as normal. Internal 1MΩ Pullup.
Decoder Input : The received digital signal input. Internal 1MΩ Pullup.
Decoder Data Clock : A Logic I/O port. External decode clock input or internal data clock
output, dependant upon clock mode 1, 2 inputs, see Clock Mode pins.
Algorithm : A logical '1' at this pin sets this device for a 3-bit companding algorithm. A
logical '0' sets a 4-bit companding algorithm. Internal 1MΩ Pullup.
Clock Mode 2 :
Clock Mode 1 Clock Mode 2 Facility
Clock Mode 1 : 0 0 External clocks
Internal 1MΩ 0 1 Internal, 64kb/s = f ÷ 16
Pullups. 1 0 Internal, 32kb/s = f ÷ 32
1 1 Internal, 16kb/s = f ÷ 64
Clock rates refer to f = 1.024 MHz Xtal/clock input. During internal operation the data
clock frequencies are available at the ports for external circuit synchronization.
Independant or common data rate inputs to Encode and Decode data clock ports may be
employed in the External Clocks mode.
V
DD
: Positive Supply. A single + 5 volt power supply is required.
FX619
L1/L2
13
14
15
16
17
18
19
20
21
22
23
24
FX619
J
12
13
14
15
16
17
18
19
20
21
22
FX619
M1
15,16
17
18,19
20
21
22
23
24
25
26
27
28
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