Consumer Microcircuits Limited FX506P, FX506LS, FX506LG Datasheet

Publication D/506/3 July 1994

CML Semiconductor Products

PRODUCT INFORMATION

Military/Marine and Mobile
Radio Applications

FM/AM/SSB Applications
16-kbit Data and Voice Scrambler

Compatible
Low-Power 5-Volt CMOS

Process

Full Rx and Tx Filtering to
CEPT Standards

Digital Control of Volume,
Noise Squelch and R.S.S.I.

Tx VOGAD Circuitry
Serial µP Control of ALL Chip

Functions
Deviation Limiter

FX506

Features/Applications

PA

Rx

Tx

TRANSMITTER

AUDIO

REF.

VCO

MIC.1

MIC.2

µP

SERIAL

BUS

SYSTEM

SQUELCH/CARRIER

DETECT

SQUELCH VOLUME

UP

DOWN

LOW

HIGH

4.0MHz

EXTERNAL AUDIO

PROCESSES

MODULATION

RECEIVER

RSSI

CTCSS and DATA

Tx AUDIO

FX506

Single-Chip

Audio Processor

The Post-Process Path can adjust and prepare
the input audio for output to the chosen transmitter
driver or loudspeaker amplifier.

Suitably software configured, the FX506, which can
operate on voice, direct-digital or tone-data and sub­audio frequencies, is compatible with FM, AM and
SSB type transceivers. Digital gain elements are
provided on-chip for dynamic control and balance of
signal-path levels during manufacturing, test and
operation.

System Squelch, a separate path, is sourced from
either the incoming signal or Received Signal
Strength Indication (R.S.S.I.) from the radio circuitry.

The FX506, a low-power 5-volt CMOS device, is
available in 24-pin/lead plastic DIL and SMD
packages.

Brief Description

The FX506 is a µProcessor-controlled, single-chip
device containing ALL the circuit elements necessary
to perform the audio functions of a mobile (or portable)
radio system.

On-chip signal paths include: speech-band/pre­emphasis filters, variable gain/attenuation stages,
voice-compression and deviation limiter circuitry.

Each function in the signal path can be addressed or
by-passed ––

providing “real-time,” dynamic control

––
by the µProcessor. This half-duplex device comprises
two separate audio signal paths.

The Pre-Process Path performs filtering and level
adjustment on audio (Rx or Tx) for use in auxiliary
systems such as “Frequency Inversion Scrambling,”
“Sub-Audio” tone or “In-Band” data signalling. This path
is output at the “Pre-Process Audio Output” pin. If no
external processes are being used this output should
be connected to the “Pre-process Audio Input” pin.

Mobile Radio Audio Processor

FX506

2

Pin Number Function

DIL Quad

FX506P FX506LG

FX506LS

1

2

3

4

5

6

7

8

9

10

11

12

13

Xtal: The output of the 4.0MHz on-chip clock oscillator.

Xtal/Clock: The input to the on-chip 4.0MHz clock oscillator inverter. All oscillator components are

included on-chip. A 4.0MHz Xtal or externally derived clock should be connected here.
See Figure 2.

V

DD

: Positive supply rail. A single, stable +5-volt supply is required. Levels and voltages within the

Audio Processor are dependent upon this supply.

Post Process Audio Input: The analogue input to the Post-Process Path from external audio
operations. Inputs to this pin should be a.c. coupled via a capacitor C7.
See Figures 2 and 4.

Pre-Process Audio Output: The analogue output to external audio operations.
See Figure 4.

Rx Audio Input: The input from the radio receiver demodulator. This input, which requires to be
a.c. coupled via capacitor C

6

, is selected by serial data. Audio at this input will be available for use

as a signal-squelch noise source. See Figures 2 and 4.

V

BIAS

: The output of the on-chip analogue bias circuitry, held internally at VDD/2. This pin should be

decoupled to VSS via capacitor C1. See Figure 2.

CTCSS/Data Input: To allow the introduction of sub-audio tones or data to the VCO drives.
By manipulation of bits 17, 18 and 19 this input can be “mixed” into the signal path or added as a
burst in between speech segments.

Tx Audio Input: The pre-process transmit audio input. This input can be driven from an external
source or from the FX506 Mic. input circuitry. See Figures 2, 3 and 4.

Mic. Output: The output of the microphone multiplexer, selected by serial input data. If additional
gain is required for the pre-process input, an external amplifier as shown in Figure 3 is
recommended.

Mic.1 Input:

These separate microphone audio inputs are individually selected by the
serial input data. See Figures 2, 3 and 4.

Mic.2 Input:

V

SS

: Negative supply rail (GND).

3

Pin Number Function

DIL Quad

FX506P FX506LG

FX506LS

14

15

16

17

18

19

20

21

22

23

24

Compression Capacitor: External components connected to this pin provide the required

compression time-constant. See Figure 2.

Audio Output (Rx): The received audio output from the Post-Process path. This output is data
selected and when powersaved is held at V

BIAS

.

VCO Ref. Drive (Tx) Output: The output to drive the modulation reference oscillator. This output
is data selected and when powersaved is held at V

BIAS

. To prevent any d.c. level at this output
causing incorrect frequency selection it is recommended that a.c. coupling components as shown
in Figure 2 are employed. For modulation down to near d.c., these components should be by­passed.

VCO Drive (Tx) Output: The output to drive the modulation VCO. This output is data selected
and when powersaved is held at V

BIAS

.

R.S.S.I.: The input to the Squelch Selection circuitry from the radio's Received Signal Strength
Indicator output. A data selected input.

Noise Input: The noise level can be applied to this pin. This would be the Noise Output integrated
by external components, as indicated in Figure 2, or an externally produced noise level.

Noise Output: The output of the on-chip “squelch noise rectifier.” This output is a half-wave
rectified d.c. level that can be applied to the Noise Input via external integrating components. This
output could also be used by an external signal detector circuit. This output level is at V

BIAS

for no

input. See Figures 2, 3 and 4.

Squelch Drive: A TTL compatible output. The inputs to the comparator are: the logically selected
threshold level from the Digital-to-Analogue converter and the selected noise input. A logic “0”
signifies that the noise threshold has been exceeded.

Serial Clock: The externally produced serial data loading clock input. See Figure 5.
This input has an internal 1MΩ pullup resistor.

Serial Data: The controlling, 47-bit serial data input. With Chip Select maintained at a logic “0” the
serial data is entered at this pin, loaded bit 46 first, bit 0 last.
Detailed information on the allocation and function of serial data bits (0 to 46) is given in tabular
form on later pages. Data load timing should be carried out as described in Figure 5. This input
has an internal 1MΩ pullup resistor.

Chip Select: The data loading control function. During serial loading this input should be operated
as shown in Figure 5. New data is latched on the rising edge of this waveform.
This input has an internal 1MΩ pullup resistor.

4

External Components and Interfacing

CTCSS/DATA INPUT

PRE-PROCESS AUDIO OUTPUT

Rx
AUDIO INPUT

POST PROCESS
AUDIO INPUT

MIC. OUTPUT

MIC. INPUT 1

MIC. INPUT 2

XTAL/CLOCK

AUDIO OUTPUT (Rx)

VCO REF. DRIVE (Tx)

COMPRESSION

CAPACITOR

VCO DRIVE (Tx)

R.S.S.I.

NOISE INPUT

NOISE OUTPUT

SQUELCH DRIVE

SERIAL DATA INPUT

SERIAL CLOCK INPUT

R

2

R

1

C

2

C

9

C

4

C

1

C

3

C

6

C

7

C

8

X

1

R

4

Tx AUDIO INPUT

CHIP SELECT

R

3

C

5

SEE
FIG.3

BELOW

13

14

15

16

17

18

19

20

21

22

23

24

1
2
3
4
5

6
7

8
9

10
11

12

FX506P

V

DD

V

DD

V

BIAS

V

SS

V

SS

V

BIAS

V

SS

XTAL

Fig.2 Recommended External Components

Notes

For dual Tx inputs using both Mic.1 and Mic.2 inputs without
pre-emphasis, capacitors C

3

and C4 will be required at the

inputs as shown in Figure 2.
If pre-emphasis is required, the external circuit shown in

Figure 3 is recommended.
The Op-Amp selected for this application should be of a “low

noise wide-bandwidth” type i.e. with at least 60dB of gain at
6kHz.

In addition to the components shown in Figure 2, it is
recommended that the power and V

BIAS

lines to the external

Op-Amp are decoupled to V

SS

physically close to the

amplifier

, by a 1.0µF capacitor.

Layout Recommendations

Audio microcircuit performance will be affected by external
noise.

All external components should be kept as close to
the device as possible.

Tracks to the device should be kept short, particularly
the Audio and V

BIAS

inputs.

A “ground-plane” connected to V

SS

will help to

eliminate external pick-up.

Ensure that all inputs (analogue and d.c.) are free from
noise.

Xtal/clock and digital tracks should be kept well away
from analogue circuitry. Analogue inputs and outputs
should be screened wherever possible with high-level
outputs isolated from very low-level inputs.

Circuit References

Component Value Tolerance

R1= 100kΩ = ± 10%
R

2

390kΩ± 10%

R

3

100kΩ± 1%

R

4

10kΩ± 10%

R

5

18.0kΩ± 1%

R

6

2.7MΩ± 1%

Tx

AUDIO INPUT

+

–

R

5

R

6

EXTERNAL

OP-AMP

BIAS

MIC. I/P

2

MIC. O/P

12

11

MIC. I/P

1

10

9

C

10

/C

4

C

3

C1= 1.0µF ± 20%
C

2

6.8µF ± 20%

C

3

1.0nF ± 1%

C

4

1.0nF ± 1%

C

5

15nF ± 1%

C

6

0.1µF ± 20%

C7= 0.1µF ± 20%
C

8

0.1µF ± 20%

C

9

1.0µF ± 20%

C

10

12.0pF ± 1%

X

1

4.0MHz

Fig.3 Typical 2nd Order Pre-emphasis Input Circuit

PMR Audio Processor Explanatory Block Diagram

Fig.4 PMR Audio Processor – Facilities

Rx AUDIO INPUT

POST

PROCESS GAIN

PRE-EMPHASIS LIMITER

POST-DEVIATION

LIMITER FILTER

VCO REF

DRIVE (Tx)

VCO

DRIVE (Tx)

AUDIO

OUTPUT (Rx)

OUTPUT DRIVE

POST PROCESS

AUDIO INPUT

INPUT SELECT

# 3, 4, 5, 6

INPUT GAIN AMP

(0 to 15dB)

# 10, 11, 12, 13

COMPRESSOR (VOGAD)

0dB Gain

INPUT HPF PRE-PROCESS GAIN

(-2.75dB to +1.0dB)

COMPRESSION

CAPACITOR

PRE-PROCESS

AUDIO OUTPUT

Test

300Hz

INPUT LPF

16

V

SS

Rx (Noise)

NOISE

OUTPUT

SQUELCH DETECT

SQUELCH

DRIVE

SQUELCH LEVEL

COMPARATOR

-

+

Threshold

(1.5V to 3.5V)

NOISE

INPUT

# 45, 46

R.S.S.I.

# 41, 42, 43, 44

16

Function Control

Bits (#)

SERIAL DATA

INPUT

SERIAL CLOCK

INPUT

#

#

#

#

# 37, 38, 39

XTAL/CLOCK

XTAL

MIC. 1

MIC. 2

MIC. OUTPUT

SQUELCH SELECT

16

# 20, 21, 22

# 23, 24, 25, 26

16

# 40

(Nar./Wide)

PRE-PROCESS PATH

POST-PROCESS PATH

SQUELCH SYSTEM

TEST SIGNAL PATH

V

DD

# 32, 33, 34, 35

# 28, 29, 30, 31

4.0MHz CLOCK

OSCILLATOR

AND

LOGIC

# 15

16

16

8

# 16

(Nar./Wide)

8

(-3.0dB to +4.0dB)

KEY

# = Controlling Logic Bit Number/s

= Adjustable Element, n = Number of steps

= General Powersave

n

Tx AUDIO INPUT

V

BIAS

V

BIAS

DE-EMPHASIS

20dB/dec.

3000Hz

DETECT

Threshold

20dB/dec.

MIXER

AMP

2550Hz

3000Hz

CTCSS/DATA

INPUT

dB

V

BIAS

V

BIAS

V

BIAS

# /

U

DAC

Rx (Noise)

# 1, 2

MIC. SELECT

# 0

(# 7, # 8, # 9 [# 14])

# 14

# 18, 19

OUTPUT DRIVE

SELECT

Test

# 27

# 36

# 36

# 27

SERIAL INPUT

PORT

# 17

GENERAL POWERSAVE

(GPS)

(GPS)

0/14dB

(GPS)

(GPS)

(GPS)

(GPS)

(GPS)

(GPS)

(GPS)

(GPS)

(GPS)

(GPS)

2dB

GPS

∑

CHIP SELECT

dB

(I & II)

5