Consumer Microcircuits Limited FX465D5 Datasheet

FX465
PRODUCT INFORMATION
CML Semiconductor Products
Publication D/465/2 May 1996
Advance Information
FX465
Brief Description
The FX465 is a 3-volt, half-duplex predictive Continuous Tone Controlled Squelch System (CTCSS) encoder/decoder microcircuit. The FX465 has integral voice-band filtering for prefiltering of Tx audio and the rejection of the CTCSS tone in receive.
Under µProcessor control, the FX465 will encode and decode any one of 47 sub-audio frequencies (+NOTONE) in the range 67.0Hz to 254.1Hz. Tone frequencies and all functional commands can be loaded to the device in either pin-selectable 8-bit parallel or serial format.
A separate, Rx/Tx voice-audio path is available with a highpass (sub-audio reject) filter automatically placed in the relevant Rx or Tx voice line.
The Rx sub-audio (CTCSS) path contains a (selected tone frequency) bandpass filter and period detector providing a logic level output (Rx Tone Detect) to indicate a successful decode operation.
Rx “Press to Listen” (PTL) and Tx “Squelch-Tail Elimination” functions are available in both command loading modes. The squelch-tail elimination function will provide (Tx tone) phase-reversal to minimise the annoying audio outputs that occur at the receiver on completion of a transmission.
Tone frequencies and filter accuracies are maintained by an on-chip 4.0MHz clock oscillator employing an external crystal or clock pulse input.
The FX465, which exhibits high audio and sub-audio performance with low falsing, is available in a 24-pin plastic small outline SSOP package.
Fig.1 Functional Block Diagram
Extended Code CTCSS Encoder/Decoder
New SSOP D5 package
Features
Low-Voltage (3-Volt) Supply 47 Programmable Sub-Audio
Tones + N OTONE Meets MPT1306 and TIA/EIA 603 High Voiceband/CTCSS Isolation Separate Sub-Audio and Rx/Tx
Audio Paths and Filtering
Applications
Mobile Radio Systems Community Base Stations “Sports Radio” (Japan) Sub-Audio Signalling and
Selective Calling Status and Alarm Systems Amateur Radio
LOAD/LATCH
D2/SERIAL CLOCK
D0
CLKS
CLKS
CLKS/XTAL
CLKS/XTAL
Tx TONE OUT
V
DD
Rx TONE DETECT
A0 - A5
D0 - D10
TONE DETECT
LOGIC
REFERENCE VOLTAGE
TONE
ROM
48 x 10
TONE DECODE
FILTER
TONE IN
FILTER
TONE OUT FILTER
AUDIO FILTER
CLK
XTAL/CLOCK
D5/SERIAL ENABLE
TONE IN
D4/SERIAL ENABLE
D1
PTL
RX AUDIO IN
DECODE COMPARATOR IN
Rx AUDIO OUT
Rx TONE DECODE
TX AUDIO IN
DECODE COMPARATOR REF
Tx AUDIO OUT
D3/SERIAL DATA IN
TONE
RX/TX
XTAL
DIGITAL
INTERFACE
AND
CLOCK
GENERATION
f
-
+
-
+
-
+
V
SS
V
BIAS
2
Pin Number Function
VDD: Positive supply.
Xtal/CIock: Input to the on-chip inverter; used with a 4.0MHz Xtal or external clock source.
Xtal: Output of the on-chip inverter (clock output).
Load/Latch: Controls 8 on-chip latches and is used to latch Rx/Tx, PTL, D0 - D5. This pin is internally
pulled to VDD. A logic ‘1’ applied to this input puts the 8 latches into a 'transparent' mode. A logic ‘0’ applied to this input puts the 8 latches into the ‘latched’ mode. In parallel mode data is loaded and latched by a logic ‘1’ to ‘0’ transition (see Figure 4). In serial mode data is loaded and latched by a ‘0’ to ‘1’ to ‘0’ strobe pulse on this pin (see Figure 4).
D5/Serial Enable: Data input D5 (Parallel Mode); Serial Enable (Serial Mode). A logic ‘l’ applied to this input, together with a logic ‘0’ applied to D4/Serial Enable, will put the device into 'Serial Mode' (see Figure 4). This pin is internally pulled to VDD.
D4/Serial Enable: Data input D4 (Parallel Mode); Serial Enable (Serial Mode). A logic ‘0’ applied to this input, together with a logic ‘1’ applied to D5/Serial Enable, will place the device into ‘Serial Mode’ (see Figure 4). This pin internally pulled to VDD.
D3/Serial Data In: Data input D3 (Parallel Mode); Serial Data Input (Serial Mode). In Serial Mode this pin becomes the serial data input for D5 - D0, Rx/Tx, PTL (see Figure 4). D5 is clocked-in first and PTL last. This pin internally pulled to VDD.
D2/Serial Clock: Data input D2 (Parallel Mode); Serial Clock Input (Serial Mode). In Serial Mode this pin becomes the Serial Clock input. Data is clocked on the positive-going edge (see Figure 4). This pin is internally pulled to VDD.
D1: Data input D1 (Parallel Mode); Not used (Serial Mode). This pin is internally pulled to VDD.
D0: Data input D0 (Parallel Mode); Not used (Serial Mode). This pin is internally pulled to VDD.
VSS: Negative supply.
Decode Comparator Ref. (I/P): Internally biased to VDD/3 or 2VDD/3 via 1.0M resistors depending on
the logical state of the Rx Tone Decode pin. Rx Tone Decode = logic ‘1’ will bias this input to 2VDD/3, a logic ‘0’ will bias this input to VDD/3. This input provides the decode comparator reference voltage; switching of bias voltages provides hysteresis to reduce 'chatter' under marginal conditions.
FX465 D5
1
2
3
4
5
6
7
8
9
10
11
12
3
Pin Number Function
FX465 D5
13
14
15
16
17
18
19
20
21
22
23
24
Rx Tone Decode (O/P): The gated output of the on-chip Decode Comparator.
This output is used to gate the Rx Audio path. A logic ‘0’ on this pin indicates a successful decode and that the ‘Decode Comparator In’ pin is more positive than the ‘Decode Comparator Ref.’ input (see Table 1).
Decode Comparator In: The inverting input of the Decode Comparator. This pin is normally connected to the integrated output of the Rx Tone Detect pin.
Rx Tone Detect (O/P): In the Rx mode this output will go to a logic ‘1’ during a successful decode (Table 1). This must be externally integrated to control response and deresponse times (Figure 2).
Tx Tone Out: The CTCSS sinewave output appears on this pin under the control of the Rx/Tx pin. This output, when not transmitting a sub-audio tone, may be biased to VDD/2 as described in Table 1.
Rx/Tx: This input (Parallel Mode) selects Rx or Tx modes (see Figure 2). Logic ‘1’ = Rx; logic ‘0’ = Tx. In Serial Mode this (Rx or Tx) function is serially loaded. This pin is internally pulled to
VDD via a 1M resistor.
PTL: A dual-function input. In parallel Rx mode this pin operates as a “Push To Listen” function by enabling the Rx audio path, thus overriding the tone-squelch function. In the parallel load mode, Tx operation this input reverses the phase of the transmitting CTCSS tone (squelch tail elimination). In the serial load mode (Rx and Tx) these functions are serially loaded. Internal pull-up to VDD.
Rx Audio Out: The high-pass filtered ‘Received Audio’ output. This pin outputs audio when Rx Tone Decode = ‘0’, or PTL = ‘1’ or when ‘Notone’ is programmed (Table 2). In Tx Mode this pin is biased to VDD/2.
Tx Audio Out: The high-pass filtered ‘Transmit Audio’ output. In Tx mode this pin outputs audio present at the Tx Audio input by opening the Tx audio path. In Rx mode this pin is biased to VDD/2.
V
BIAS
: The output of the on-chip analogue bias circuitry. Held internally at VDD/2, this pin should be
externally decoupled to VSS via a capacitor.
Tx Audio In: The Tx Audio Input pin. Tx voice-band audio may be prefiitered, using the audio path, thus helping to avoid talk-off due to the intermodulation of speech frequencies with the transmitted CTCSS tone. This pin is internally biased to VDD/2.
Rx Audio In: The input to the audio high-pass filter in the Rx Mode. This pin is internally biased to VDD/2.
Tone In: The input to the CTCSS tone detector; this input is internally biased to VDD/2.
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