Consumer Microcircuits Limited FX365CJ, FX365CDW Datasheet
FX365C
PRODUCT INFORMATION
CML Semiconductor Products
Publication D/365C/3 October 1995
Applications
Mobile Radio Systems
Community Base Stations
“Sports Radio” (Japan)
Sub-Audio Signalling and Selec-
tive Calling
Status and Alarm Systems
Amateur Radio
Features
Low-Voltage (3-Volt) Supply
39 Programmable Sub-Audio
Tones + N
OTONE
Meets MPT1306 and EIA - 220 B
High Voiceband/CTCSS Isolation
Separate Sub-Audio and Rx/Tx
Audio Paths and Filtering
DIGITAL
PERIOD
DETECTOR
OUTPUT
LATCH
XTAL/CLOCK
GENERATOR
8-BIT
LATCH
TONE
GENERATOR
PROGRAM
LOGIC
XTAL/CLOCK
Tx ENABLE
Tx
Rx
Tx
(Rx)
CONTROL
CONTROL
TONE FREQUENCY
BUS
(Rx)
SUB-AUDIO
TONE INPUT
Rx AUDIO
INPUT
Rx AUDIO
OUTPUT
Rx TONE
DETECT
Tx TONE
OUTPUT
Tx AUDIO
INPUT
Tx AUDIO
OUTPUT
V
DD
V
BIAS
V
SS
SERIAL ENABLE 1/D
5
SERIAL ENABLE 2/D
4
SERIAL DATA/D
3
SERIAL CLOCK/D
2
D
1
D
0
PTL
DECODE
COMPARATOR REF.
DECODE
COMPARATOR
INPUT
DECODE COMPARATOR
8-BIT
SERIAL
SHIFT
REGISTER
LOGIC
LOGIC
300Hz
f
TONE
XTAL
+
-
Rx TONE DECODE
OUTPUT
LOAD/LATCH
VOICE-AUDIO PATH
SUB-AUDIO PATH
Rx/Tx
V
DD
3
2V
DD
3
Low-Voltage CTCSS Encoder/
Decoder
FX365C
Brief Description
The FX365C is a 3-volt, half-duplex predictive
Continuous Tone Controlled Squelch System
(CTCSS) encoder/decoder microcircuit. The FX365C
has integral voice-band filtering for prefiltering of Tx
audio and the rejection of the CTCSS tone in receive.
Under µProcessor control, the FX365C will encode
and decode any one of 39 sub-audio frequencies
(+N
OTONE) in the range 67.0Hz to 250.3Hz. Tone
frequencies and all functional commands can be
loaded to the device in either pin-selectable 8-bit
parallel or serial format.
A separate, Rx/Tx voice-audio path is available with
a highpass (sub-audio reject) filter automatically
placed in the relevant Rx or Tx voice line.
The Rx sub-audio (CTCSS) path contains a
(selected tone frequency) bandpass filter and period
detector providing a logic level output (Rx Tone
Detect) to indicate a successful decode operation.
Rx “Press to Listen” (PTL) and Tx “Squelch-Tail
Elimination” functions are available in both command
loading modes. The squelch-tail elimination function
will provide (Tx tone) phase-reversal to minimise the
annoying audio outputs that occur at the receiver on
completion of a transmission.
Tone frequencies and filter accuracies are
maintained by an on-chip 1.0MHz clock oscillator
employing an external crystal or clock pulse input.
The FX365C, which exhibits high audio and subaudio performance with low falsing, is available in 24pin DIL and small outline SMD packages.
Fig.1 Functional Block Diagram
2
Pin Number Function
DW and J package styles.
V
DD
: Positive supply rail. A single stable supply is required; levels and voltages within the FX365C are
dependent upon this supply.
This pin should be decoupled to V
SS
by a capacitor located close to the pin.
Xtal/CIock: Input to the on-chip inverter; used with a 1.0MHz Xtal or external clock source.
Xtal: Output of the on-chip clock oscillator inverter.
Load/Latch: Controls 8 on-chip latches and is used to latch Rx/Tx, PTL, D
0
- D5. This pin is internally
pulled to V
DD
. A logic ‘1’ applied to this input places the 8 latches into a 'transparent' mode. A logic ‘0’
applied to this input places the 8 latches into the ‘latched’ mode.
In parallel mode data is loaded and latched by a logic ‘1’ to ‘0’ transition (see Figure 4a).
In serial mode data is loaded and latched by a ‘0’ to ‘1’ to ‘0’ strobe pulse on this pin (see Figure 4b).
D
5
/Serial Enable 1: Data input D5 (Parallel Mode); Serial Enable 1 (Serial Mode).
A logic ‘l’ applied to this input, together with a logic ‘0’ applied to D
4
/Serial Enable 2, will put the device
into 'Serial Mode' (see Figure 4b). This pin is internally pulled to V
DD
.
D
4
/Serial Enable 2: Data input D4 (Parallel Mode); Serial Enable 2 (Serial Mode).
A logic ‘0’ applied to this input, together with a logic ‘1’ applied to D
5
/Serial Enable 1, will place the
device into ‘Serial Mode’ (see Figure 4b). This pin internally pulled to V
DD
.
D
3
/Serial Data: Data input D3 (Parallel Mode); Serial Data Input (Serial Mode).
In Serial Mode this pin becomes the serial data input for D
5
- D0, Rx/Tx, PTL (see Figure 4b). D5 is
clocked-in first and PTL last. This pin internally pulled to V
DD
.
D
2
/Serial Clock: Data input D2 (Parallel Mode); Serial Clock Input (Serial Mode).
In Serial Mode this pin becomes the Serial Clock input. Data is clocked on the positive-going edge
(see Figure 4b). This pin is internally pulled to V
DD
.
D
1
: Data input D1 (Parallel Mode); Not Used (Serial Mode). This pin is internally pulled to VDD.
D
0
: Data input D0 (Parallel Mode); Not Used (Serial Mode). This pin is internally pulled to VDD.
V
SS
: Negative supply (GND).
Decode Comparator Ref. (I/P): Internally biased to V
DD
/3 or 2VDD/3 via 1.0MΩ resistors depending
on the logical state of the Tone Decode Output pin, this input provides the decode comparator
reference voltage; switching of bias voltages provides hysteresis to reduce 'chatter' under marginal
conditions. Tone Decode Output = logic ‘1’ will place this input to 2V
DD
/3 bias, a logic ‘0’ will bias this
input to V
DD
/3.
FX365C
1
2
3
4
5
6
7
8
9
10
11
12
3
FX365C
13
14
15
16
17
18
19
20
21
22
23
24
Pin Number Function
DW and J package styles.
Rx Tone Decoder (O/P): The gated output of the on-chip Decode Comparator.
This output is used to gate the Rx Audio path. A logic ‘0’ output on this pin indicates a successful
decode and indicates that the ‘Decode Comparator Input’ pin is more positive than the ‘Decode
Comparator Ref’ input (see Table 1).
Decode Comparator Input: The inverting input of the Decode Comparator. This pin is to be
connected to the Rx Tone Detect pin via external integrating components as shown in Figure 2.
Rx Tone Detect (O/P): In the Rx mode this output will go to a logic ‘1’ during a successful decode
(Table 1). This pin is to be connected to the Decode Comparator Input via the external integrating
circuitry as shown in Figure 2.
Tx Tone Output: A low-impedance emitter-follower source, under the control of the Rx/Tx pin, of the
CTCSS sinewave. This output, when not transmitting a sub-audio tone, may be set to a V
DD
/(2-0.7)V
bias or open-circuit as described in Table 1.
Rx/Tx: This input (Parallel Mode) selects Rx or Tx modes (see Figure 2). Logic ‘1’ = Rx;
logic ‘0’ = Tx. In Serial Mode this (Rx or Tx) function is serially loaded via pin 7 (Serial Data) and this
pin not used. This pin is internally pulled to V
DD
via a 1MΩ resistor (Rx operaion).
PTL: A dual-function input. In the parallel load mode, Rx operation: A logic ‘1’ provides a “Press To
Listen” function by overriding the tone-squelch and enabling the audio path.
In the parallel load mode, Tx operation: A logic ‘1’ provides a “Squelch Tail Elimination” function by
reversing the phase of the transmitting sub-audio tone; the phase reversal function should be applied
by a suitable timing circuit.
In the serial load mode (Rx and Tx) these functions are loaded via the serial data word at pin 7.
Rx Audio Output: The high-pass filtered ‘Received Audio’ output. This pin outputs audio when Rx
Tone Decode = ‘0’, or PTL = ‘1’ or ‘Notone’ is programmed (Table 2). In Tx Mode this pin is biased to
V
DD
/2.
Tx Audio Output: The high-pass filtered ‘Transmit Audio’ output. In Tx mode this pin outputs audio
present at the Tx Audio Input by opening the Tx audio path. In Rx mode this pin is biased to V
DD
/2.
V
BIAS
: The output of the on-chip analogue bias circuitry. Held internally at VDD/2, this pin should be
externally decoupled to V
SS
.
Tx Audio Input: The Tx Audio Input pin. Tx voice-band audio may be prefiitered, using the Voice
Audio Path, thus helping to avoid talk-off due to the intermodulation of speech frequencies with the
transmitted CTCSS tone. The Tx Audio Path may also be used to pre-filter speech when employing
‘scramblers’ which could introduce noise into the low frequency band. This pin is internally biased to
V
DD
/2.
Rx Audio Input: The input to the Voice Audio high-pass filter in the Rx Mode.
This pin is internally biased to V
DD
/2.
Tone Input: The input to the CTCSS tone detector and is internally biased to V
DD
/2.
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