Consumer Microcircuits Limited CMX624P4, CMX624D5, CMX624D2 Datasheet
CMX624
D/624/6 January 2001 Provisional Information
V.23/Bell 202 Modem
Features Applications
•• V.23 / Bell 202 Compatible Modem •• Telephone Telemetry Systems
•• Integrated DTMF Encoder •• Remote Utility Meter Reading
•• Call Progress Tone Detection •• Security Systems/Cash Terminals
•• Line Reversal and Ring Detector •• Industrial Control Systems
•• Low Power Operation (2.7V) •• Pay-Phones
•• Part of the CMX6x4 Modem Series •• Cable TV Set-Top Boxes
1.1 Brief Description
The CMX624 V.23 / Bell 202 modem is intended for use in any telephone based information and telemetry
system with low power requirements. Using FSK signalling, fast call set-up times and robust error resistant
transmission can be implemented by efficient low power circuits. The circuit can operate at 1200bps full
duplex over a 4-wire circuit or 1200 bps plus low speed data over a 2-wire circuit. Flexible line driver and
receive hybrid circuitry are integrated on chip requiring only passive external components to build a 2- or 4wire interface. A low impedance pull down output is provided for a hook relay.
Control of the device is via a simple high speed serial bus; this allows easy interfacing to a host µController.
The data transmitted and received by the modem is also transferred over the same high speed serial bus. Onchip programmable Tx and Rx UARTs allow asynchronous data to be simultaneously encoded and decoded.
Either UART may be disabled to allow 8-bit raw data to be received or transmitted. Any repetitive 8-bit data
pattern can be sent without the controller having to reload data every 8 bits. All 16 DTMF combinations are
available along with a single tone 'melody' mode. The ringing, 2100Hz, call progress and data detectors
included on the CMX624 make the set-up of a telephone call a simple matter for the host µController.
In many data collection and telemetry systems low power consumption is important. The CMX624 features a
'Zero Power' standby mode. Whilst in standby the ring detector continues to operate and will supply the host
µController with an interrupt when line reversal or ringing is detected. The CMX624 can operate on a supply
voltage between 3.0V and 5.5V across the full temperature range of -40°C to +85°C.
The CMX624 is pin compatible with the CMX644A V22 and Bell 212A modem also from CML.
2001 Consumer Microcircuits Limited
V23 / Bell 202 Modem CMX624
CONTENTS
Section
Page
1.1 Brief Description .......................................................................................1
1.2 Block Diagram ...........................................................................................3
1.3 Signal List...................................................................................................4
1.4 External Components...............................................................................6
1.5 General Description..................................................................................6
1.5.1 Xtal Osc and Clock Dividers.......................................................6
1.5.2 Rx Input Amplifier........................................................................7
1.5.3 Receive Filter and Equaliser.......................................................7
1.5.4 FSK Demodulator.........................................................................8
1.5.5 Rx Energy Detector .....................................................................8
1.5.6 FSK / DTMF Modulator ................................................................8
1.5.7 Transmit Filter ..............................................................................9
1.5.8 Transmit Output Buffer.............................................................10
1.5.9 Ring Signal Detector..................................................................10
1.5.10 Tx/Rx UART.................................................................................11
1.5.11 ‘C-BUS’ Interface........................................................................13
1.5.12 ‘C-BUS’ Registers......................................................................14
1.6 Application Notes....................................................................................14
1.6.1 Line Interface..............................................................................15
1.6.2 Ring Detector Interface.............................................................17
1.7 Performance Specification.....................................................................19
1.7.1 Electrical Performance..............................................................19
1.7.2 Packaging....................................................................................24
Note: This product is in development: Changes and additions will be made to this specification. Items
marked TBD or left blank will be included in later issues.
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1.2 Block Diagram
Figure 1 Block Diagram
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1.3 Signal List
CMX624
D2/D5/P4
Pin No. Name Type
1 XTALN O/P The output of the on-chip Xtal oscillator inverter.
2 XTAL/CLOCK I/P The input to the oscillator inverter from the Xtal
3 SERIAL
4 COMMAND
Signal Description
circuit or external clock source.
CLOCK
I/P
The ‘C-BUS’ serial clock input from the µC. See
Section 1.5.11
DATA
I/P
The ‘C-BUS’ serial data input from the µC.
5 REPLY DATA T/S
A 3-state ‘C-BUS’ serial data output to the µC.
This output is high impedance when not sending
data to the
µC.
6 CSN I/P The ‘C-BUS’ transfer control input provided by
µC.
the
7 IRQN O/P
A ‘wire-ORable’ output for connection to a µC
Interrupt Request input. This output is pulled
down to Vss when active and is high impedance
when inactive. An external pullup resistor is
required.
8 TOP O/P The Tx analogue signal output.
9 TXO O/P The output of the line driving amplifier.
10 TXN I/P The inverting input to the line driver amplifier.
11 TXON O/P The inverted output of the line driving amplifier.
12 V
13 V
Power The negative supply rail (ground).
SS
O/P Internally generated bias voltage of V
BIAS
DD
/2,
except when the device is in ‘Zero Power’ mode
when V
decoupled to V
will discharge to VSS. Should be
BIAS
by a capacitor mounted close
SS
to the device pins.
14 RLYDRV O/P Relay drive open drain output. This output is
pulled down to V
when active and is high
SS
impedance when inactive.
15 RXP I/P The non-inverting input to the Rx input amplifier.
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CMX624
D2/D5/P4
Signal Description
Pin No. Name Type
16 RXN I/P The inverting input to the Rx input amplifier.
17 RXO O/P The output of the Rx input amplifier.
18 RT BI Open drain output and Schmitt trigger input
forming part of the Ring Signal detector.
19 RD I/P Schmitt trigger input to the Ring Signal Detector.
20 - NC No connection should be made to this pin.
21 - NC No connection should be made to this pin.
22 - NC No connection should be made to this pin if the
printed circuit board is to be used for CMX624
only. If the board is also to be used for
CMX644A, a capacitor should be connected as
shown in Figure 2.
23 - I/P No connection should be made to this pin if the
printed circuit board is to be used for CMX624
only. If the board is also to be used for
CMX644A, a capacitor should be connected as
shown in Figure 2.
24 V
Power The positive supply rail. Levels and thresholds
DD
within the device are proportional to this voltage.
Should be decoupled to V
by a capacitor
SS
mounted close to the device pins.
Notes:
I/P = Input
O/P = Output
BI = Bidirectional
T/S = 3-state Output
NC = No Connection
This device is capable of detecting and decoding small amplitude signals. To achieve this VDD and V
decoupling and protecting the receive path from extraneous in-band signals are very important. It is
recommended that the printed circuit board is laid out with a ground plane in the CMX624 area to provide a
low impedance connection between the V
pin and the VDD and V
SS
decoupling capacitors.
BIAS
BIAS
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1.4 External Components
R1
100kΩ
X1 3.579545MHz
C1, C2 18pF
C3, C4
0.1µF
C5 *
Resistors
±5%, capacitors ±10% unless otherwise stated.
* This component is only required for compatibility with CMX644A,
see CMX644A Data Sheet for further details.
Figure 2 Recommended External Components for Typical Application
1.5 General Description
The CMX624 contains a V.23/Bell 202 compatible FSK modem capable of duplex operation at 1200/75 or
1200/150 bps over a 2-wire line or 1200/1200 bps over a 4-wire line, a flexible FSK data UART, a receive FSK
or Call Progress Tone energy detector, a 2100Hz detector, a DTMF generator, a Tx line driving buffer
amplifier, a telephone line Ringing Signal or Line Voltage Reversal detector and a 3.579545MHz Xtal
oscillator. These functions are all controlled over a ‘C-BUS’ serial
and receive FSK modem data.
1.5.1 Xtal Osc and Clock Dividers
Frequency and timing accuracy of the CMX624 is determined by a 3.579545MHz clock present at the
XTAL/CLOCK pin. This may be generated by the on-chip oscillator inverter using the external components
C1, C2 and X1 of Figure 2, or may be supplied from an external source to the XTAL/CLOCK input. If the clock
is supplied from an external source, C1, C2 and X1 should not be fitted.
The on-chip oscillator is turned off in the 'Zero-Power' mode.
If the clock is provided by an external source which is not always running, then the 'Zero-Power' mode must
be set when the clock is not available. Failure to observe this rule may cause a rise in the supply current
drawn by CMX624.
µC interface which also carries the transmit
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Call Progress
1.5.2 Rx Input Amplifier
This amplifier, with suitable external components, is used to adjust the received signal to the correct amplitude
for the FSK receiver and Energy Detect circuits and may also form part of a 2-wire or 4-wire hybrid circuit; see
Section 1.6.1.
1.5.3 Receive Filter and Equaliser
This block includes a bandpass filter whose characteristics are set by bits 4 and 5 of the FSK MODE Register
according to the receive operating mode (Call Progress, 75/150bps FSK or 1200bps FSK). It is used to
attenuate out of band noise and interfering signals, especially the locally generated transmit FSK signal which
could otherwise interfere with the received FSK signal when the modem is operating in 2-wire duplex mode.
When receiving 1200bps FSK data an optional equaliser section, enabled by setting bit 6 of the FSK MODE
Register, compensates for one-half of the ETS Test Line 1 characteristics shown in Figure 3b.
0
-10
-20
dB
-30
-40
100 1000 10000
Hz
1200bps
75/150 bps
Figure 3a Rx Frequency Responses with Line Interface,
see section 1.6.1 (equaliser disabled)
5
4
3
dB
ms
2
1
dB wrt 800Hz
ms wrt 1700Hz
0
0 500 1000 1500 2000 2500 3000 3500 4000
Hz
Figure 3b ETS 300 114 Test Line 1 Characteristics (Normalised)
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1.5.4 FSK Demodulator
This block is enabled when bits 1 and 5 of the FSK MODE Register are set to ‘1’, and converts the 75, 150 or
1200 bps FSK input signal to a binary received data signal which is sent to the Rx UART block.
Note that in the absence of a valid FSK signal, the demodulator may falsely interpret speech or other
extraneous signals as data.
1.5.5 Rx Energy and 2100Hz Detector
The function of this block is controlled by Bits 4 and 5 of the FSK MODE Register and Bit 0 of the TX TONES
Register.
When Bit 0 of the TX TONES Register and Bits 4 and 5 of the FSK MODE Register are set to ‘1’ this block will
measure the frequency and amplitude of the incoming signal. When a signal of 2100Hz is present of sufficient
amplitude and time Bit 4 of the FLAGS Register is set high. See Section 1.7.1 for amplitude, time and
frequency limits.
When Bit 0 of the TX TONES Register is set to ‘0’ this block compares the level of the signal at the output of
the Receive Filter against an internal threshold and may be used as a FSK level detector or a simple Call
Progress Signal detector according to the settings of bits 4 and 5 of the FSK MODE Register, which affect the
Receive Filter pass band as described in Section 1.5.3.
The required register settings are summarised in the table below:
TX TONES Reg
FSK MODE Reg
Bit 0 Bit 5 Bit 4 Detection Mode
0 0 0 Call Progress
0 1 0 75 / 150 bps FSK
0 1 1 1200 bps FSK
1 1 1 2100 Hz
Bit 4 of the FLAGS Register is set to ‘1’ by the output of this block when the received level has exceeded the
threshold for sufficient time. Amplitude and time hysteresis are used to reduce chattering in marginal
conditions.
See Section 1.7.1 for definitions of Teon and Teoff
1.5.6 FSK / DTMF Modulator
Figure 4 Rx Energy Detector Timing
When bit 7 of the TX TONES Register is set to ‘0’ then this block generates FSK signals as determined by
bits 0 and 1 of the FSK MODE Register and the Tx data bits from the UART block as shown in the tables
below:
V.23 mode (bit 7 of SETUP register = ‘0’):
FSK MODE Reg
FSK / DTMF Modulator block output FSK Signal Frequency
Bit 1 Bit 0 (Bit 7 of TX TONES = ‘0’) ‘0’ (Space) ‘1’ (Mark)
0 x Disabled (o/p held at VDD / 2) - 1 0 75bps FSK 450Hz 390Hz
1 1 1200bps FSK 2100Hz 1300Hz
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