Congatec TS87 User Manual

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COM Express™ conga-TS87

4th Generation Intel® Core™ i7, i5, i3 processor with QM87 or HM86 PCH

User’s Guide

Revision 1.3

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Revision History

Revision Date (yyyy.mm.dd) Author Changes

0.1 2013.06.03 AEM • Preliminary release for Internal use

0.2 2013.09.30 AEM

0.3 2013.11.05 AEM

1.0 2014.03.26 AEM

1.1 2014.07.09 AEM

1.2 2014.10.24 AEM

1.3 2016.15.07 AEM

• Updated section 2.5.1

• Updated section 5 “Onboard Temperature Sensors”

• Updated section 10 “System Resources”

• Updated section 2.1 “Feature List”

• Updated section 4.1 with Flat pipe heatspreader. Deleted section 4.2 ‘Heatspreader thermal Imagery

• Updated table 2 in section 6.2.3 “Digital Display Interface”

• Added UART support for rev. B.0 and later in sections 2.1 “Feature List”, 6.1.11 “General Purpose Serial Interface” and table 18

• Updated COM Express concept in section 1 “Introduction”

• Deleted the variant with PN:046809 from sections 1 “Introduction”, 2 ”Feature List” and 2.5 “Power Consumption”. This variant is not on congatec’s roadmap. Added additional two variants with part numbers 046810 and 046811

• Updated section 2.5 “Power Consumption”

• Updated section 3 “Block Diagram”

• Corrected pins D63 and D64 in section 9.4 “C-D Connector Pinout”

• Added section 11 “BIOS Setup Description”

• Ofﬁcial release

• Updated section 2.5 “Power Consumption”

• Updated section 11 “BIOS Setup Description”

• Added note about the ULP mode in section 6.1.4 “Gigabit Ethernet”

• Updated section 7.3 “Watchdog”

• Updated section 8.2.5 “Intel Virtualization Technology”

• Updated section 11 “BIOS Setup Description”

• Corrected the BIOS Aptio UEFI version in section 2.1 “Feature List”

• Added section 4 “Cooling Solution”

• Added Windows 10 to section 2.2 “Supported Operating Systems”

• Updated section 6.1.10 “LVDS/eDP”

• Update section 7.7 “congatec Battery Management Interface”

• Updated section 10.3 “PCI Interrupt Routing Map”

• Deleted the comment “not supported” for SUS_S4# signal in table 17 “Power and System Management Signal Descriptions”. Corrected also the description of PWRBTN# signal

• Deleted sections 12.3 “BIOS Security Features” and 12.4 “Hard Disk Security Features” due to duplication

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Preface

This user’s guide provides information about the components, features, connectors and BIOS Setup menus available on the conga-TS87. It is one of three documents that should be referred to when designing a COM Express™ application. The other reference documents that should be used include the following:

The links to these documents can be found on the congatec AG website at www.congatec.com

Disclaimer

The information contained within this user’s guide, including but not limited to any product speciﬁcation, is subject to change without notice.

congatec AG provides no warranty with regard to this user’s guide or any other information contained herein and hereby expressly disclaims any implied warranties of merchantability or ﬁtness for any particular purpose with regard to any of the foregoing. congatec AG assumes no liability for any damages incurred directly or indirectly from any technical or typographical errors or omissions contained herein or for discrepancies between the product and the user’s guide. In no event shall congatec AG be liable for any incidental, consequential, special, or exemplary damages, whether based on tort, contract or otherwise, arising out of or in connection with this user’s guide or any other information contained herein or the use thereof.

COM Express™ Design Guide COM Express™ Speciﬁcation

Intended Audience

This user’s guide is intended for technically qualiﬁed personnel. It is not intended for general audiences.

Lead-Free Designs (RoHS)

All congatec AG designs are created from lead-free components and are completely RoHS compliant.

Electrostatic Sensitive Device

All congatec AG products are electrostatic sensitive devices and are packaged accordingly. Do not open or handle a congatec AG product except at an electrostatic-free workstation. Additionally, do not ship or store congatec AG products near strong electrostatic, electromagnetic, magnetic, or radioactive ﬁelds unless the device is contained within its original manufacturer’s packaging. Be aware that failure to comply with these guidelines will void the congatec AG Limited Warranty.

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Symbols

The following symbols are used in this user’s guide:

Warning

Warnings indicate conditions that, if not observed, can cause personal injury.

Caution

Cautions warn the user about how to prevent damage to hardware or loss of data.

Note

Notes call attention to important information that should be observed.

congatec AG has made every attempt to ensure that the information in this document is accurate yet the information contained within is supplied “as-is”.

Trademarks

Product names, logos, brands, and other trademarks featured or referred to within this user’s guide, or the congatec website, are the property of their respective trademark holders. These trademark holders are not afﬁliated with congatec AG, our products, or our website.

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Warranty

congatec AG makes no representation, warranty or guaranty, express or implied regarding the products except its standard form of limited warranty (“Limited Warranty”) per the terms and conditions of the congatec entity, which the product is delivered from. These terms and conditions can be downloaded from www.congatec.com. congatec AG may in its sole discretion modify its Limited Warranty at any time and from time to time.

The products may include software. Use of the software is subject to the terms and conditions set out in the respective owner’s license agreements, which are available at www.congatec.com and/or upon request.

Beginning on the date of shipment to its direct customer and continuing for the published warranty period, congatec AG represents that the products are new and warrants that each product failing to function properly under normal use, due to a defect in materials or workmanship or due to non conformance to the agreed upon speciﬁcations, will be repaired or exchanged, at congatec’s option and expense.

Customer will obtain a Return Material Authorization (“RMA”) number from congatec AG prior to returning the non conforming product freight prepaid. congatec AG will pay for transporting the repaired or exchanged product to the customer.

Repaired, replaced or exchanged product will be warranted for the repair warranty period in effect as of the date the repaired, exchanged or replaced product is shipped by congatec, or the remainder of the original warranty, whichever is longer. This Limited Warranty extends to congatec’s direct customer only and is not assignable or transferable.

Except as set forth in writing in the Limited Warranty, congatec makes no performance representations, warranties, or guarantees, either express or implied, oral or written, with respect to the products, including without limitation any implied warranty (a) of merchantability, (b) of ﬁtness for a particular purpose, or (c) arising from course of performance, course of dealing, or usage of trade.

congatec AG shall in no event be liable to the end user for collateral or consequential damages of any kind. congatec shall not otherwise be liable for loss, damage or expense directly or indirectly arising from the use of the product or from any other cause. The sole and exclusive remedy against congatec, whether a claim sound in contract, warranty, tort or any other legal theory, shall be repair or replacement of the product only.

Certiﬁcation

congatec AG is certiﬁed to DIN EN ISO 9001 standard.

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Technical Support

congatec AG technicians and engineers are committed to providing the best possible technical support for our customers so that our products can be easily used and implemented. We request that you ﬁrst visit our website at www.congatec.com for the latest documentation, utilities and drivers, which have been made available to assist you. If you still require assistance after visiting our website then contact our technical support department by email at support@congatec.com

Terminology

Term Description

GB Gigabyte (1,073,741,824 bytes)

GHz Gigahertz (one billion hertz)

kB Kilobyte (1024 bytes)

MB Megabyte (1,048,576 bytes)

Mbit Megabit (1,048,576 bits)

kHz Kilohertz (one thousand hertz)

MHz Megahertz (one million hertz)

TDP Thermal Design Power

PCIe PCI Express

SATA Serial ATA

PEG PCI Express Graphics

PCH Platform Controller Hub

eDP Embedded DisplayPort

T.O.M. Top of memory = max. DRAM installed

HDA High Deﬁnition Audio

I/F Interface

N.C. Not connected

N.A. Not available

TBD To be determined

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Contents

1 Introduction .............................................................................11

1.1 COM Express™ Concept .........................................................11

1.2 Options Information ................................................................. 12

2 Speciﬁcations ........................................................................... 13

2.1 Feature List ..............................................................................13

2.2 Supported Operating Systems ................................................ 14

2.3 Mechanical Dimensions ........................................................... 14

2.4 Supply Voltage Standard Power .............................................. 15

2.4.1 Electrical Characteristics .......................................................... 15

2.4.2 Rise Time ................................................................................. 15

2.5 Power Consumption ................................................................ 16

2.5.1 Intel® Core™ i7-4700EQ 2.4 GHz Quad Core™ 6MB Cache . 17

2.5.2 Intel® Core™ i5-4402E 1.6 GHz Dual Core™ 3MB Cache .....17

2.5.3 Intel® Core™ i5-4400E 2.7 GHz Dual Core™ 3MB Cache .....18

2.5.4 Intel® Core™ i3-4102E 1.6 GHz Dual Core™ 3MB Cache .....18

2.5.5 Intel® Core™ i3-4100E 2.4 GHz Dual Core™ 3MB Cache .....18

2.5.6 Intel® Celeron® 2000E 2.2 GHz Dual Core™ 2MB Cache .......19

2.5.7 Intel® Celeron® 2002E 1.5 GHz Dual Core™ 2MB Cache .......19

2.6 Supply Voltage Battery Power .................................................19

2.6.1 CMOS Battery Power Consumption ........................................ 20

2.7 Environmental Speciﬁcations ................................................... 20

3 Block Diagram .......................................................................... 21

4 Cooling Solution ...................................................................... 22

4.1 CSA Dimensions ...................................................................... 22

4.2 CSP Dimensions ....................................................................... 23

4.3 Heatspreader ...........................................................................24

5 Onboard Temperature Sensors ................................................ 26

6 Connector Subsystems Rows A, B, C, D .................................. 28

6.1 Primary Connector Rows A and B ............................................ 29

6.1.1 Serial ATA™ (SATA) ..................................................................29

6.1.2 USB 2.0 .................................................................................... 29

6.1.3 High Deﬁnition Audio (HDA) Interface .................................... 29

6.1.4 Gigabit Ethernet ..................................................................... 29

6.1.5 LPC Bus .................................................................................... 30

6.1.6 I²C Bus Fast Mode ................................................................... 30

6.1.7 PCI Express™ ...........................................................................30

6.1.8 ExpressCard™ .........................................................................31

6.1.9 Graphics Output (VGA/CRT) .................................................... 31

6.1.10 LVDS/eDP .................................................................................31

6.1.11 General Purpose Serial Interface ............................................. 31

6.1.12 Power Control .......................................................................... 32

6.1.13 Power Management ................................................................. 34

6.2 Secondary Connector Rows C and D ....................................... 35

6.2.1 PCI Express™ ...........................................................................35

6.2.2 PCI Express Graphics (PEG) ..................................................... 35

6.2.3 Digital Display Interface ........................................................... 36

6.2.3.1 HDMI ........................................................................................ 37

6.2.3.2 DVI ........................................................................................... 37

6.2.3.3 DisplayPort (DP) ....................................................................... 37

6.2.4 USB 3.0 .................................................................................... 38

7 Additional Features ..................................................................39

7.1 congatec Board Controller (cBC) ............................................. 39

7.2 Board Information .................................................................... 39

7.3 Watchdog ................................................................................39

7.4 I2C Bus ...................................................................................... 39

7.5 Power Loss Control .................................................................. 39

7.6 OEM BIOS Customization ........................................................ 40

7.6.1 OEM Default Settings .............................................................. 40

7.6.2 OEM Boot Logo ....................................................................... 40

7.6.3 OEM POST Logo ..................................................................... 40

7.6.4 OEM BIOS Code/Data ............................................................. 40

7.6.5 OEM DXE Driver ...................................................................... 41

7.7 congatec Battery Management Interface ................................ 41

7.8 API Support (CGOS) ................................................................ 41

7.9 Security Features ......................................................................42

7.10 Suspend to Ram ....................................................................... 42

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8 conga Tech Notes .................................................................... 43

8.1 Intel® PCH Features .................................................................43

8.1.1 Intel® Rapid Storage Technology ............................................ 43

8.1.1.1 AHCI ........................................................................................ 43

8.1.1.2 RAID ......................................................................................... 43

8.1.2 Intel® Smart Response Technology ......................................... 43

8.1.3 Intel® Rapid Start Technology .................................................. 44

8.2 Intel® Processor Features .........................................................44

8.2.1 Intel® Turbo Boost Technology ................................................ 44

8.2.2 Thermal Monitor and Catastrophic Thermal Protection .......... 45

8.2.3 Processor Performance Control ............................................... 45

8.2.4 Intel® 64 Architecture ............................................................... 46

8.2.5 Intel® Virtualization Technology ............................................... 47

8.2.6 Thermal Management ............................................................. 47

8.3 ACPI Suspend Modes and Resume Events .............................. 48

8.4 Low Voltage Memory (DDR3L) ................................................. 48

8.5 USB 2.0 EHCI Host Controller Support ....................................49

9 Signal Descriptions and Pinout Tables ..................................... 50

9.1 A-B Connector Signal Descriptions ......................................... 51

9.2 A-B Connector Pinout .............................................................. 61

9.3 C-D Connector Signal Descriptions ......................................... 63

9.4 C-D Connector Pinout ............................................................. 72

9.5 Boot Strap Signals ................................................................... 74

10 System Resources ....................................................................75

10.1 I/O Address Assignment .......................................................... 75

10.1.1 LPC Bus .................................................................................... 75

10.2 PCI Conﬁguration Space Map ................................................. 76

10.3 PCI Interrupt Routing Map ....................................................... 77

10.4 I²C Bus ..................................................................................... 78

10.5 SM Bus ..................................................................................... 78

11 BIOS Setup Description ........................................................... 79

11.1 Entering the BIOS Setup Program. .......................................... 79

11.1.1 Boot Selection Popup .............................................................. 79

11.2 Setup Menu and Navigation .................................................... 79

11.3 Main Setup Screen ................................................................... 80

11.3.1 Platform Information Submenu ................................................ 81

11.4 Advanced Setup ...................................................................... 81

11.4.1 Graphics Submenu ................................................................... 82

11.4.1.1 GOP Conﬁguration Submenu .................................................. 85

11.4.2 Watchdog Submenu ................................................................85

11.4.3 Hardware Health Monitoring Submenu ................................... 87

11.4.4 PCI & PCI Express Submenu .................................................... 88

11.4.4.1 PCI Express Settings Submenu ................................................ 89

11.4.4.2 PIRQ Routing & IRQ Reservation Submenu ............................. 90

11.4.4.3 PCI Express Graphics (PEG) Port Submenu .............................90

11.4.4.4 PCI Express Port Submenu ......................................................93

11.4.5 ACPI Submenu ......................................................................... 95

11.4.6 RTC Wake Submenu ................................................................ 96

11.4.7 Trusted Computing Submenu ..................................................96

11.4.8 CPU Submenu .......................................................................... 97

11.4.9 SATA Submenu ......................................................................101

11.4.9.1 Software Feature Mask Conﬁguration ...................................102

11.4.10 Intel(R) Rapid Start Technology Submenu .............................. 104

11.4.11 Acoustic Management Submenu ........................................... 104

11.4.12 USB Submenu ........................................................................ 105

11.4.12.1 USB Ports Per-Port Disable Control Submenu ....................... 107

11.4.13 SMART Settings Submenu ..................................................... 108

11.4.14 Super I/O Submenu ............................................................... 108

11.4.15 Serial Port Console Redirection Submenu ............................. 109

11.4.15.1 Console Redirection Settings Submenu ................................ 109

11.4.16 UEFI Network Stack Submenu ............................................... 110

11.4.17 Intel (R) Ethernet Connection I218-LM Submenu .................. 110

11.4.18 NIC Conﬁguration Submenu ................................................. 111

11.5 Chipset Setup ........................................................................ 112

11.5.1 Platform Controller Hub (PCH) Submenu .............................. 112

11.5.2 Processor (Integrated Components) Submenu ...................... 113

11.5.2.1 DMI Conﬁguration Submenu ................................................. 114

11.5.2.2 Memory Conﬁguration Submenu .......................................... 114

11.5.2.3 GT - Power Management Control Submenu .........................116

11.6 Boot Setup ............................................................................. 116

11.6.1 Boot Settings Conﬁguration .................................................. 116

11.6.1.1 CSM & Option ROM Control Submenu ................................. 118

11.7 Security Setup ........................................................................ 119

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11.7.1 Security Settings .................................................................... 120

11.7.1.1 BIOS Security Features ..........................................................120

11.7.1.2 Hard Disk Security Features ................................................... 121

11.8 Save & Exit Menu ................................................................... 122

12 Additional BIOS Features ......................................................123

12.1 Supported Flash Devices ....................................................... 123

12.2 Updating the BIOS ................................................................. 123

13 Industry Speciﬁcations ........................................................... 124

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List of Tables

Table 1 conga-TS87 Variants ................................................................12

Table 2 Feature Summary ..................................................................... 13

Table 3 Display Combination ............................................................... 36

Table 4 Signal Tables Terminology Descriptions ..................................50

Table 5 Intel® High Deﬁnition Audio Link Signals Descriptions ............ 51

Table 6 Gigabit Ethernet Signal Descriptions....................................... 52

Table 7 Serial ATA Signal Descriptions ................................................. 52

Table 8 PCI Express Signal Descriptions (general purpose) .................53

Table 9 ExpressCard Support Pins Signal Descriptions ........................ 54

Table 10 LPC Signal Descriptions ........................................................... 54

Table 11 USB Signal Descriptions ........................................................... 54

Table 12 CRT Signal Descriptions ........................................................... 55

Table 13 LVDS Signal Descriptions ......................................................... 56

Table 14 Embedded DisplayPort Signal Descriptions ............................ 56

Table 15 SPI BIOS Flash Interface Signal Descriptions ........................... 57

Table 16 Miscellaneous Signal Descriptions ........................................... 57

Table 17 General Purpose I/O Signal Descriptions ................................ 58

Table 18 Power and System Management Signal Descriptions ............. 59

Table 19 General Purpose Serial Interface Signal Descriptions .............. 59

Table 20 Power and GND Signal Descriptions ....................................... 60

Table 21 Connector A-B Pinout .............................................................. 61

Table 22 PCI Express Signal Descriptions (general purpose) .................63

Table 23 USB 3.0 Signal Descriptions ..................................................... 63

Table 24 PCI Express Signal Descriptions (x16 Graphics) .......................63

Table 25 DDI Signal Description ............................................................. 66

Table 26 HDMI Signal Descriptions ........................................................ 68

Table 27 DisplayPort (DP) Signal Descriptions ....................................... 69

Table 28 Module Type Deﬁnition Signal Description ............................. 71

Table 29 Power and GND Signal Descriptions ....................................... 71

Table 30 Connector C-D Pinout ............................................................. 72

Table 31 Boot Strap Signal Descriptions ................................................ 74

Table 32 PCI Conﬁguration Space Map ................................................. 76

Table 33 PCI Interrupt Routing Map ....................................................... 77

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1 Introduction

1.1 COM Express™ Concept

COM Express™ is an open industry standard deﬁned speciﬁcally for COMs (computer on modules). Its creation makes it possible to smoothly transition from legacy interfaces to the newest technologies available today. COM Express™ modules are available in following form factors:

• Mini 84mm x 55mm

• Compact 95mm x 95mm

• Basic 125mm x 95mm

• Extended 155mm x110mm

The COM Express™ speciﬁcation 2.1 deﬁnes seven different pinout types.

Types Connector Rows PCIe Lanes PCI IDE SATA Ports LAN ports USB 2.0/ USB 3.0 Display Interfaces

Type 1 A-B Up to 6 - 4 1 8 / 0 VGA, LVDS

Type 2 A-B C-D Up to 22 32 bit 1 4 1 8 / 0 VGA, LVDS, PEG/SDVO Type 3 A-B C-D Up to 22 32 bit - 4 3 8 / 0 VGA,LVDS, PEG/SDVO Type 4 A-B C-D Up to 32 1 4 1 8 / 0 VGA,LVDS, PEG/SDVO Type 5 A-B C-D Up to 32 - 4 3 8 / 0 VGA,LVDS, PEG/SDVO Type 6 A-B C-D Up to 24 - 4 1 8 / 4* VGA,LVDS/eDP, PEG, 3x DDI Type 10 A-B Up to 4 - 2 1 8 / 0 LVDS/eDP, 1xDDI

* The SuperSpeed USB ports (USB 3.0) are not in addition to the USB 2.0 ports. Up to 4 of the USB 2.0 ports can support SuperSpeed USB

The conga-TS87 modules use the Type 6 pinout deﬁnition and comply with COM Express 2.1 speciﬁcation. They are equipped with two high performance connectors that ensure stable data throughput.

The COM (computer on module) integrates all the core components and is mounted onto an application speciﬁc carrier board. COM modules are legacy-free design (no Super I/O, PS/2 keyboard and mouse) and provide most of the functional requirements for any application. These functions include, but are not limited to a rich complement of contemporary high bandwidth serial interfaces such as PCI Express, Serial ATA, USB 2.0, and Gigabit Ethernet. The Type 6 pinout provides the ability to offer PCI Express, Serial ATA, and LPC options thereby expanding the range of potential peripherals. The robust thermal and mechanical concept, combined with extended power-management capabilities, is perfectly suited for all applications.

Carrier board designers can use as little or as many of the I/O interfaces as deemed necessary. The carrier board can therefore provide all the interface connectors required to attach the system to the application speciﬁc peripherals. This versatility allows the designer to create a dense and optimized package, which results in a more reliable product while simplifying system integration. Most importantly, COM Express™

Page 13

modules are scalable, which means once an application has been created there is the ability to diversify the product range through the use of different performance class or form factor size modules. Simply unplug one module and replace it with another; no redesign is necessary.

1.2 Options Information

The conga-TS87 is currently available in seven variants. This user’s guide describes all of these variants. The tables below show the different conﬁgurations available. Check for the Part No. that applies to your product. This will tell you what options described in this user’s guide are available on your particular module.

Table 1 conga-TS87 Variants

Part-No. 046804 046805 046806 046807 046808

Processor Intel® Core™ i7-4700EQ

2.4 GHz Quad Core™

Smart Cache 6 MByte 3 MByte 3 MByte 3 MByte 3 MByte

Intel

Graphics GT2 GT2 GT2 GT2 GT2

PEG Yes Yes Yes Yes Yes

LVDS Ye s Yes Yes Ye s Ye s

DisplayPort (DP) Yes Yes Ye s Yes Yes

HDMI Yes Yes Ye s Yes Yes

Processor TDP 47 W 25 W 37 W 25 W 37 W

Intel® Core™ i5-4402E

1.6 GHz Dual Core™

Intel® Core™ i5-4400E

2.7 GHz Dual Core™

Intel® Core™ i3-4102E

1.6 GHz Dual Core™

Intel® Core™ i3-4100E

2.4 GHz Dual Core™

Part-No. 046810 046811

Processor Intel® Celeron® 2000E

2.2 GHz Dual Core™

Smart Cache 2 MByte 2 MByte

Intel

Graphics GT1 GT1

PEG Yes Yes

LVDS Yes Yes

DisplayPort (DP) Ye s Yes

HDMI Yes Yes

Processor TDP 37 W 25 W

Intel® Celeron® 2002E

1.5 GHz Dual Core™

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2 Speciﬁcations

2.1 Feature List

Table 2 Feature Summary

Form Factor Processor

Memory

congatec Board Controller Chipset

Audio Ethernet Graphics

Options

Peripheral Interfaces

BIOS Power

Management Security

Based on COM Express™ standard pinout Type 6 Rev. 2.1 (Basic size 95 x 125mm).

Intel® 4th Generation Core i7,i5,i3 and Celeron mobile processors.

Two memory sockets (located on the top and bottom side of the conga-TS87). Supports

- SO-DIMM non-ECC DDR3L (low voltage @ 1.35V) modules

- Data rates up to 1600 MT/s

- Maximum 16 GB capacity

Multi-stage watchdog, manufacturing and board information, board statistics, hardware monitoring, fan control, I2C bus, Power loss control.

Intel® 8 Series Chipset: Intel

HDA (High Deﬁnition Audio)/digital audio interface with support for multiple codecs

Gigabit Ethernet support via Intel

Next Generation Intel® HD Graphics with support for Intel® Clear Video Technology (HD encode/transcode, Blu-ray playback), DirectX Video Acceleration (full AVC/VC1/MPEG2 hardware decode), OpenGL 4.0 and DirectX11.1. Up to 3 independent displays supported (DP, HDMI/DVI, VGA)

1x LVDS

- Integrated ﬂat panel interface with 25-112MHz single/dual-channel LVDS Transmitter

- Single-channel LVDS interface: 1 x 18 bpp or 1 x 24 bpp.

- Dual channel LVDS interface: 2 x 18 bpp or 2 x 24 bpp panel.

- VESA LVDS and OpenLDI color mappings

- Automatic Panel Detection via Embedded Panel Interface based on VESA EDID™

1.3.

- Resolution up to 1920x1200 in dual LVDS bus mode.

1x Optional eDP interface (NOTE: Either eDP or LVDS signals supported. Both not supported).

4x Serial ATA® with RAID support 0/1/5/10 7 PCI Express® Gen2 Lanes. 8x USB 2.0 (EHCI) 4x USB 3.0 (XHCI) 2x UART (Rev. B.0 and later)

AMI Aptio

ACPI 4.0 compliant with battery support. Also supports Suspend to RAM (S3) and Intel AMT 9.0. Conﬁgurable TDP

Optional discrete Trusted Platform Module “TPM 1.2”.

UEFI 4.x ﬁrmware, 8/16 MByte serial SPI with congatec Embedded BIOS features.

DH82QM87 and DH82HM86 PCH

l218LM GbE LAN controller. Variants with Intel

QM87 support AMT 9.0.

1x VGA

- 180 MHz RAMDAC with resolution up to 1920 x 1200

and 24 bit color @ 60Hz refreshed rate with reduced blanking.

1x PEG Port (x16 Gen 3 (8GT/s)). 3x DisplayPorts (DP 1.1) on digital ports B, C and D. 3x HDMI 1.4 ports on digital ports B, C and D. 3x DVI ports on digital ports B, C and D. The DP and HDMI/DVI ports are multiplexed together. The interfaces support Hot-Plug detect.

LPC Bus I²C Bus, Fast Mode, multimaster SM Bus SPI GPIOs 2x ExpressCard

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Note

Some of the features mentioned in the above feature summary are optional. Check the article number of your module and compare it to the options information table in section 1.2 to determine what options are available on your particular module.

2.2 Supported Operating Systems

The conga-TS87 supports the following operating systems.

• Microsoft® Windows

• Microsoft® Windows® 7

• Microsoft® Windows® Embedded Standard

• Linux

2.3 Mechanical Dimensions

• 95.0 mm x 125.0 mm (3.74” x 4.92”)

• Height approximately 18 or 21mm (including heatspreader) depending on the carrier board connector that is used. If the 5mm (height) carrier board connector is used, then approximate overall height is 18mm. If the 8mm (height) carrier board connector is used, then approximate overall height is 21mm.

Page 16

2.4 Supply Voltage Standard Power

• 12V DC ± 5%

The dynamic range shall not exceed the static range.

Absolute Maximum12.60V

2.4.1 Electrical Characteristics

Power supply pins on the module’s connectors limit the amount of input power. The following table provides an overview of the limitations for pinout Type 6 (dual connector, 440 pins).

Power Rail Module Pin

Current Capability (Amps)

VCC_12V 12 12 11.4-12.6 11.4 +/- 100 137 85% 116

VCC_5V-SBY 2 5 4.75-5.25 4.75 +/- 50 9

VCC_RTC 0.5 3 2.0-3.3 +/- 20

12.10V

11.90V

11.40V

Nominal Input (Volts)

12V

Input Range (Volts)

Derated Input (Volts)

Dynamic Range

Nominal Static Range

Absolute Minimum

Max. Input Ripple (10Hz to 20MHz) (mV)

Max. Module Input Power (w. derated input) (Watts)

Assumed Conversion Efﬁciency

Max. Load Power (Watts)

2.4.2 Rise Time

The input voltages shall rise from 10% of nominal to 90% of nominal at a minimum slope of 250V/s. The smooth turn-on requires that, during the 10% to 90% portion of the rise time, the slope of the turn-on waveform must be positive.

Page 17

2.5 Power Consumption

The power consumption values listed in this document were measured under a controlled environment. The hardware used for testing includes a conga-TS87 module, conga-Cdebug carrier board, CRT monitor, SATA drive, and USB keyboard. The conga-Cdebug is modiﬁed so that the 12V input is only routed to the module and all other circuitry on the carrier itself is powered by the 5V input. The SATA drive was powered externally by an ATX power supply so that it does not inﬂuence the power consumption value that is measured for the module. The USB keyboard was detached once the module was conﬁgured within the OS. All recorded values were averaged over a 30 second time period. Cooling of the module was done by the module speciﬁc heatpipe heatspreader and a fan cooled heatsink to measure the power consumption under normal thermal conditions.

The conga-Cdebug originally does not provide 5V standby power. Therefore, an extra 5V_SB connection without any external loads was made. Using this setup, the power consumption of the module in S3 (Standby) mode was measured directly.

Each module was measured while running Windows 7 Professional 64Bit, Hyper Threading enabled, Speed Step enabled, CPU Turbo Mode enabled and Power Plan set to “Power Saver”. This setting ensures that Core™ processors run in LFM (lowest frequency mode) with minimal core voltage during desktop idle. Each module was tested while using two 1GB memory modules. Using different sizes of RAM, as well as one or two memory modules, will cause slight variances in the measured results.

To measure the worst case power consumption the cooling solution was removed and the CPU core temperature was allowed to run up to between 95° and 100°C while running 100% workload with the Power Plan set to “Balanced”. The peak current value was then recorded. This value should be taken into consideration when designing the system’s power supply to ensure that the power supply is sufﬁcient during worst case scenarios.

Power consumption values were recorded during the following stages:

Windows 7 (64 bit)

• Desktop Idle (power plan = Power Saver)

• 100% CPU workload (see note below, power plan = Power Saver)

• 100% CPU workload at approximately 100°C peak power consumption (power plan = Balanced)

• Suspend to RAM. Supply power for S3 mode is 5V.

Note

A software tool was used to stress the CPU to Max Turbo Frequency.

Page 18

Processor Information

The tables below provide additional information about the power consumption data for each of the conga-TS97 variants offered. The values are recorded at various operating mode.

2.5.1 Intel® Core™ i7-4700EQ 2.4 GHz Quad Core™ 6MB Cache

conga-TS87 Art. No. 046804

Max Turbo Frequency Memory Size Operating System Power Consumption (Amps/Watts)

Peak Power Consumption

Intel® Core™ i7-4700EQ 2.4 GHz 4 Core™ 6MB Intel® Smart Cache (22nm) Layout Rev. TS87LA0 /BIOS Rev. TS87R005

3.4 GHz

2 x 2GB

Windows 7 (64 bit)

Desktop Idle 0.3 A/3.7 W (12V) Suspend to Ram (S3) 5V Input Power 0.1 A/0.4 W (5V)

100% workload without turbo mode 3.1 A/36.9 W (12V) 100% Workload with turbo mode 4.0 A/48.2 W (12V)

100% CPU and GPU without turbo mode 4.5 A/53.4 W (12V) 100% CPU and GPU with turbo mode 5.0 A/60.4 W (12V)

5.6 A/67.3 W (12V)

2.5.2 Intel® Core™ i5-4402E 1.6 GHz Dual Core™ 3MB Cache

conga-TS87 Art. No. 046805

Max Turbo Frequency Memory Size Operating System Power Consumption (Amps/Watts)

Peak Power Consumption

Intel® Core™ i5-4402E 1.6 GHz 2 Core™ 3MB Intel® Smart Cache (22nm) Layout Rev. TS87LA0 /BIOS Rev. TS87R005

2.7 GHz

2 x 2GB

Windows 7 (64 bit)

Desktop Idle 0.3 A/3.5 W (12V) Suspend to Ram (S3) 5V Input Power 0.1 A/0.4 W (5V)

100% workload without turbo mode 1.3 A/16.0 W (12V) 100% Workload with turbo mode 2.3 A/28.0 W (12V)

100% CPU and GPU without turbo mode 2.3 A/27.2 W (12V) 100% CPU and GPU with turbo mode 2.9 A/34.2 W (12V)

3.4 A/40.5 W (12V)

Page 19

2.5.3 Intel® Core™ i5-4400E 2.7 GHz Dual Core™ 3MB Cache

conga-TS87 Art. No. 046806

Max Turbo Frequency Memory Size Operating System Power Consumption (Amps/Watts)

Peak Power Consumption

Intel® Core™ i5-4400E 2.7 GHz 2 Core™ 3MB Intel® Smart Cache (22nm) Layout Rev. TS87LA0 /BIOS Rev. TS87R005

3.3 GHz

2 x 2GB

Windows 7 (64 bit)

Desktop Idle 0.3 A/3.5 W (12V) Suspend to Ram (S3) 5V Input Power 0.1 A/0.4 W (5V)

100% workload without turbo mode 1.6 A/18.6 W (12V) 100% Workload with turbo mode 3.4 A/40.3 W (12V)

100% CPU and GPU without turbo mode 2.6 A/31.3 W (12V) 100% CPU and GPU with turbo mode 4.0 A/48.0 W (12V)

4.3 A/52.1 W (12V)

2.5.4 Intel® Core™ i3-4102E 1.6 GHz Dual Core™ 3MB Cache

conga-TS87 Art. No. 046807

Max Turbo Frequency Memory Size Operating System Power Consumption (Amps/Watts)

Peak Power Consumption

Intel® Core™ i3-4102E 1.6 GHz 2 Core™ 3MB Intel® Smart Cache (22nm) Layout Rev. TS87LA0 /BIOS Rev. TS87R005

N.A

2 x 2GB

Windows 7 (64 bit)

Desktop Idle 0.3 A/3.4 W (12V) Suspend to Ram (S3) 5V Input Power 0.1 A/0.4 W (5V)

100% workload without turbo mode 1.2 A/14.4 W (12V) 100% Workload with turbo mode N.A

100% CPU and GPU without turbo mode 2.0 A/24.2 W (12V) 100% CPU and GPU with turbo mode N.A

2.1 A/25.1 W (12V)

2.5.5 Intel® Core™ i3-4100E 2.4 GHz Dual Core™ 3MB Cache

conga-TS87 Art. No. 046808

Max Turbo Frequency Memory Size Operating System Power Consumption (Amps/Watts)

Peak Power Consumption

Intel® Core™ i3-4100E 2.4 GHz 2 Core™ 3MB Intel® Smart Cache (22nm) Layout Rev. TS87LA0 /BIOS Rev. TS87R005

N.A

2 x 2GB

Windows 7 (64 bit)

Desktop Idle 0.3 A/3.4 W (12V) Suspend to Ram (S3) 5V Input Power 0.1 A/0.4 W (5V)

100% workload without turbo mode 2.1 A/25.3 W (12V) 100% Workload with turbo mode N.A

100% CPU and GPU without turbo mode 3.4 A/40.8 W (12V) 100% CPU and GPU with turbo mode N.A

3.6 A/42.7 W (12V)

Page 20

2.5.6 Intel® Celeron® 2000E 2.2 GHz Dual Core™ 2MB Cache

conga-TS87 Art. No. 046810

Max Turbo Frequency Memory Size Operating System Power Consumption (Amperes/Watts)

Peak Power Consumption

Intel® Celeron® 2000E 2.2 GHz 2 Core™ 2MB Intel® Smart Cache (22nm) Layout Rev. TS87LA0 /BIOS Rev. TS87R005

N.A

2 x 2GB

Windows 7 (64 bit)

Desktop Idle 0.58 A/6.9 W (12V) Suspend to Ram (S3) 5V Input Power 0.1 A/0.4 W (5V)

100% workload without turbo mode 1.76 A/21.1 W (12V) 100% Workload with turbo mode N.A

100% CPU and GPU without turbo mode 2.08 A/25.0 W (12V) 100% CPU and GPU with turbo mode N.A

N.A

2.5.7 Intel® Celeron® 2002E 1.5 GHz Dual Core™ 2MB Cache

conga-TS87 Art. No. 046811

Max Turbo Frequency Memory Size Operating System Power Consumption (Amps/Watts)

Peak Power Consumption

Intel® Celeron® 2002E 1.5 GHz 2 Core™ 2MB Intel® Smart Cache (22nm) Layout Rev. TS87LA0 /BIOS Rev. TS87R005

N.A

2 x 2GB

Windows 7 (64 bit)

Desktop Idle 0.56 A/6.7 W (12V) Suspend to Ram (S3) 5V Input Power 0.1 A/0.4 W (5V)

100% workload without turbo mode 1.12 A/13.4 W (12V) 100% Workload with turbo mode N.A

100% CPU and GPU without turbo mode 1.50 A/18.0 W (12V) 100% CPU and GPU with turbo mode N.A

N.A

2.6 Supply Voltage Battery Power

• 2.0V-3.5V DC

• Typical 3V DC

Page 21

2.6.1 CMOS Battery Power Consumption

RTC @ 20ºC Voltage Current

Integrated in the Intel® DH82QM87 or DH82HM86 PCH 3V DC 2.27 µA

The CMOS battery power consumption value listed above should not be used to calculate CMOS battery lifetime. You should measure the CMOS battery power consumption in your customer speciﬁc application in worst case conditions, for example during high temperature and high battery voltage. The self-discharge of the battery must also be considered when determining CMOS battery lifetime. For more information about calculating CMOS battery lifetime refer to application note AN9_RTC_Battery_Lifetime.pdf on congatec AG website at www.congatec. com.

2.7 Environmental Speciﬁcations

Temperature Operation: 0° to 60°C Storage: -20° to +80°C

Humidity Operation: 10% to 90% Storage: 5% to 95%

Caution

The above operating temperatures must be strictly adhered to at all times. When using a congatec heatspreader, the maximum operating temperature refers to any measurable spot on the heatspreader’s surface.

Humidity speciﬁcations are for non-condensing conditions.

Page 22

3 Block Diagram

COM Express AB

Type 6

220 pos / Bottom side

LVDS / eDP

CRT

Ethernet

PCI Port 5 PCI Port 4 PCI Port 3 PCI Port 2 PCI Port 1 PCI Port 0

HDA I/F

USB Port 0..7

LPC Bus

SATA Port 0 SATA Port 1 SATA Port 2 SATA Port 3

SPI

I2C Bus

GPIOs

LID#/SLEEP#

FAN control

eDP (assembly option)

eDP to LVDS

Ethernet 10/100/1000

Intel218LM

TPM

eDP1

CRT

PCIe7 x1

PCIe6 x1

PCIe0 - PCIe5 x1

HDA

USB 2.0

LPC

SATA0 - SATA3

I2C

4th Generaon Intel® Core™ processor

CPU Platform

Turbo Boost 2.0 Technology

HT Technology

AVX2 SSE 4.2 TSX

AMT 9.0

Integrated Intel HD Graphics

Hardware Graphics Accelerators

Video Codecs

MPEG-2 decoding

H.264

WMV9

Mobile Intel

HDMI and PHY

SATA USB 2.0

® 8 Series Chipset QM87

Display Interface

Multimedia Features

Vector Graphics

up to 4K resolution

ASRC

I/O Inerfaces

LPC BusPCIe

TXT

AES-NI

OpenCL 1.2

OpenGL 4.0

DirectX 11.1

DMI x4FDI

GPIOs

USB 3.0

2x SO-DIMMO (X1/X2)

Dual Channel DDR3L

PEG x16 (1x16, 2x8, 1x8 + 2x4)

PECI

SPI

Flash

GPIOs

Board Controller

congatec

Monitoring

socket

SPI

Flash

COM Express AB

Type 6

220 pos / Bottom side

PEG x16

DP/HDMI Port B

DP/HDMI Port C

DP/HDMI Port D

PCIe Port 7

PCIe Port 6

USB 3.0 Port 0 USB 3.0 Port 1 USB 3.0 Port 2 USB 3.0 Port 3

(TX BC) congatec custom

Page 23

4 Cooling Solution

congatec AG offers three cooling solutions for the conga-TS87:

• Active cooling solution (CSA)

• Passive cooling solution (CSP)

• Heatspreader

The dimensions of the cooling solutions are shown below and all measurements are in millimeter. The maximum torque speciﬁcation for heatspreader screws is 0.3 Nm. Mechanical system assembly mounting shall follow the valid DIN/ISO speciﬁcations.

4.1 CSA Dimensions

125

0.15 +

0.25

1.10

96.6 95

0.1 +

0.2

1.3

250 ±10

M2.5x11mm threaded standoff for threaded version or

2.7x11mm non-thread standoff for bore hole version

Page 24

4.2 CSP Dimensions

125

0.15 +

0.25

1.10

0.1 +

0.2

1.3

M2.5x11mm threaded standoff for threaded version or

2.7x11mm non-thread standoff for bore hole version

Page 25

4.3 Heatspreader

The heatspreader acts as a thermal coupling device to the module and is thermally coupled to the CPU via a thermal gap ﬁller. On some modules, it may also be thermally coupled to other heat generating components with the use of additional thermal gap ﬁllers.

Although the heatspreader is the thermal interface where most of the heat generated by the module is dissipated, it is not to be considered as a heatsink. It has been designed as a thermal interface between the module and the application speciﬁc thermal solution. The application speciﬁc thermal solution may use heatsinks with fans, and/or heat pipes, which can be attached to the heatspreader. Some thermal solutions may also require that the heatspreader is attached directly to the systems chassis thereby using the whole chassis as a heat dissipater.

11 ±0.1

125

0.15 +

0.25

1.10

0.1 +

0.2

1.3

M2.5x11mm threaded standoff for threaded version or

2.7x11mm non-thread standoff for bore hole version

Page 26

Note

The gap pad material used on all heatspreaders contains silicon oil that can seep out over time depending on the environmental conditions it is subjected to. For more information about this subject, contact your local congatec sales representative and request the gap pad material manufacturer’s speciﬁcation.

Caution

congatec cooling solutions are designed for commercial temperature range only (0° to 60°C). Therefore, do not use the congatec cooling solutions in temperatures above 60°C or below 0°C. If an end user’s system operates above 60°C or below 0°C, or is assembled with a noncongatec cooling solution, then the end user must use or design an optimized thermal solution that meets the needs of their application.

For adequate heat dissipation, use the mounting holes on the heatspreader to attach it to the module. Apply thread-locking ﬂuid on the screws if the heatspreader is used in a high-shock and/or vibration environment. To prevent the standoff from stripping or cross-threading, use non-threaded carrier board standoffs to mount threaded heatspreaders.

For applications that require vertically-mounted heatspreader, use only heatspreaders that secure the thermal stacks with ﬁxing post. Without the ﬁxing post feature, the thermal stacks may move.

Also, do not exceed the maximum torque speciﬁcation for the heatspreader screws. Doing so may damage the module or/and the carrier board.

Page 27

5 Onboard Temperature Sensors

Onboard the conga-TS87 are two sensors - the board temperature sensor and the system environment temperature sensor. These sensors are deﬁned in the CGOS API as CGOS_TEMP_BOARD and CGOS_TEMP_ENV.

Board Temperature Sensor:

The board sensor (T12) is located at the top of the conga-TS87. This sensor measures the board temperature and is deﬁned in CGOS API as CGOS_TEMP_BOARD. It is located on the module as shown below:

Sensor Location

DDR3 RVS 1.5V

Page 28

System Environment Temperature Sensor:

The system environment sensor is located at the bottom of the conga-TS87. This sensor measures the system environment temperature and is deﬁned in CGOS API as CGOS_TEMP_ENV. It is located on the module as shown below:

Sensor Location

Page 29

6 Connector Subsystems Rows A, B, C, D

The conga-TS87 is connected to the carrier board via two 220-pin connectors (COM Express Type 6 pinout) for a total of 440 pins connectivity. These connectors are broken down into four rows. The primary connector consists of rows A and B while the secondary connector consists of rows C and D.

In this view the connectors are seen “through” the module.

A-B

6 PCI Express Lanes

4x Serial A TA

8x USB 2.0

High Definition Audio I/F

Gigabit Ethernet

(connected via a x1 PCI Express Lane)

LPC Bus

I²C Bus Fast Mode

VGA (CRT)

LVDS/eDP

2x UART (Rev. B.0 & later)

SPI

GPIOs

Power Control

Power Management

Fan Control

C-D

1 PCI Express Lane

x16 PEG Port

4x USB 3.0

3x HDMI

(Routed to DDI interface at

connector)

3x DisplayPort (DP)

(Routed to DDI interface at

connector)

3x DVI

(Routed to DDI interface at

connector)

C-D

A-B

top view

Page 30

6.1 Primary Connector Rows A and B

The following subsystems can be found on the primary connector rows A and B.

6.1.1 Serial ATA™ (SATA)

The conga-TS87 provides 4 SATA ports (SATA 0-3) externally via the Intel® QM87 PCH. The SATA ports are based on Serial ATA Speciﬁcation, Revision 3.0 and support up to 6.0 Gb/s data transfer rates. Variants equipped with Intel® HM86 PCH support 6.0 Gb/s data rates only on SATA ports 0 and 1.

The SATA controller featured on the conga-TS87 operates in three modes in order to support different operating system conditions. The modes of operation are Native IDE, AHCI and RAID mode. Hot-plug is also supported when operating in non-native IDE mode. For more information, refer to section 11 “BIOS Setup Description”.

Note

Only variants equipped with Intel® QM87 PCH support 6.0 Gb/s data rates on all SATA ports. The conga-TS87 variants equipped with Intel® HM86 PCH support 6.0 Gb/s data rates on only SATA ports 0 and 1.

6.1.2 USB 2.0

The conga-TS87 offers two EHCI USB host controllers that support USB high speed signalling via Intel® QM87 PCH. These controllers comply with USB standard 1.1 and 2.0 and offer a total of 8 USB ports via connector rows A and B. Each port is capable of supporting USB 1.1 and 2.0 compliant devices. For more information about how the USB host controllers are routed, see section 8.5.

6.1.3 High Deﬁnition Audio (HDA) Interface

The conga-TS87 provides an interface that supports the connection of HDA audio codecs.

6.1.4 Gigabit Ethernet

The conga-TS87 is equipped with a Gigabit Ethernet Controller that is integrated within the Intel® QM87 PCH. This integrated controller is routed to the Intel® l218-LM Phy through the use of the seventh PCI Express lane. The Ethernet interface consists of 4 pairs of low voltage differential pair signals designated from GBE0_MD0± to GBE0_MD3± plus control signals for link activity indicators. These signals can be used to connect to a 10/100/1000 BaseT RJ45 connector with integrated or external isolation magnetics on the carrier board.

Page 31

Note

The GBE0_LINK# output is only active during a 100Mbit or 1Gbit connection. It is not active during a 10Mbit connection. This is a limitation of Ethernet controller since it only has 3 LED outputs, ACT#, LINK100# and LINK1000#. The GBE0_LINK# signal is a logic AND of the GBE0_LINK100# and GBE0_LINK1000# signals on the conga-TS87 module.

The Intel i218 device driver offers a new feature called ULP (Ultra Low Power) mode. In this mode, the Intel i218 driver sets the LED outputs of the controller to tri-state mode. As a result, the ethernet link and activity LEDs may lit when no ethernet cable is connected. This issue is common with older driver versions because the ULP feature is enabled by default and cannot be disabled. In newer driver version, this feature can be disabled.

To have the correct LED status, congatec recommends that you use the latest i218 device driver provided on the website and additionally disable the ULP mode.

6.1.5 LPC Bus

conga-TS87 offers the LPC (Low Pin Count) bus through the Intel® QM87 PCH. There are many devices available for this Intel® deﬁned bus. The LPC bus corresponds approximately to a serialized ISA bus yet with a signiﬁcantly reduced number of signals. Due to the software compatibility to the ISA bus, I/O extensions such as additional serial ports can be easily implemented on an application speciﬁc baseboard using this bus. See section 10.2.1 for more information about the LPC Bus.

6.1.6 I²C Bus Fast Mode

The I²C bus is implemented through the congatec board controller (STMicroelectronics STM32) and accessed through the congatec CGOS driver and API. The controller provides a Fast Mode multi-master I²C Bus that has maximum I²C bandwidth.

6.1.7 PCI Express™

The conga-TS87 offers 8 PCI Express™ lanes via the Intel® QM87 PCH. Seven of these lanes are offered externally on the AB and CD connectors. The remaining lane is used by the onboard Gigabit Ethernet interface. The lanes are Gen 2 compliant and offer support for full 5 Gb/s bandwidth in each direction per x1 link.

The conga-TS87 offers 6 lanes on the AB connector and 1 lane on the CD connector. Default conﬁguration for the lanes on the AB connector is 6x1 link. A 1x4 and 2x1 link conﬁguration is also possible but requires a special/customized BIOS ﬁrmware. Contact congatec technical support for more information about this subject.

The PCI Express interface is based on the PCI Express Speciﬁcation 2.0 with Gen 1 (2.5Gb/s) and Gen 2 (5 Gb/s) speed.

Page 32

6.1.8 ExpressCard™

The conga-TS87 supports the implementation of ExpressCards, which requires the dedication of one USB port or a x1 PCI Express link for each ExpressCard used.

6.1.9 Graphics Output (VGA/CRT)

The conga-TS87 provides an analog VGA display interface on the AB connector. The VGA display interface is supported on the PCH even though the main display engine is in the processor. The display engine sends display data over to the PCH via the Intel FDI - a bus connecting the processor and the PCH display components.

The analog VGA display interface has a RAM-based Digital-to-Analog Converter (RAMDAC) that transforms the digital data from the graphics engine to analog data for the VGA monitor. The 180 MHz RAMDAC supports up to 1920 x 1200 resolutions at 60 Hz refresh rate.

6.1.10 LVDS/eDP

The conga-TS87 offers an LVDS interface with optional eDP overlay on the AB connector. The LVDS/eDP interface is by default conﬁgured to provide LVDS signals. The interface can optionally support eDP (assembly option). For more information, contact congatec technical center.

The single/dual channel LVDS interface is provided through an integrated eDP to LVDS bridge device. The eDP to LVDS bridge processes incoming DisplayPort stream and converts the DP protocol to LVDS, before transmitting the processed stream in LVDS format. The bridge supports single and dual channel signalling with color depths of 18 bits or 24 bits per pixel and pixel clock frequency up to 112 MHz.

Note

The LVDS/eDP interface supports either LVDS or eDP signals. Both interfaces are not supported simultaneously.

6.1.11 General Purpose Serial Interface

Two TTL compatible two wire ports are available on Type 6 COM Express modules. These pins are designated SER0_TX, SER0_RX, SER1_TX and SER1_RX. Data out of the module is on the _TX pins. Hardware handshaking and hardware ﬂow control are not supported. The module asynchronous serial ports are intended for general purpose use and for use with debugging software that make use of the “console redirect” features available in many operating systems.

Note

The conga-TS87 supports two UART interfaces on revision B.0 and later. These interfaces are provided on the AB connecter via single-chip USB to dual UART bridge. They do not support legacy COM port emulation and console redirection.

Page 33

6.1.12 Power Control

PWR_OK

Power OK from main power supply or carrier board voltage regulator circuitry. A high value indicates that the power is good and the module can start its onboard power sequencing.

Carrier board hardware must drive this signal low until all power rails and clocks are stable. Releasing PWR_OK too early or not driving it low at all can cause numerous boot up problems. It is a good design practice to delay the PWR_OK signal a little (typically 100ms) after all carrier board power rails are up, to ensure a stable system.

A sample screenshot is shown below:

Note

The module is kept in reset as long as the PWR_OK is driven by carrier board hardware.

Page 34

The conga-TS87 PWR_OK input circuitry is implemented as shown below:

+V12.0_S0

R1%47k5S02

R4 R1%100kS02

R13 R1%1k00S02

To Module Power Logic

PWR_OK

R1%20k0S02

TB TBC847

R5 R1%47k5S02

The voltage divider ensures that the input complies with 3.3V CMOS characteristic and also allows for carrier board designs that are not driving PWR_OK. Although the PWR_OK input is not mandatory for the onboard power-up sequencing, it is strongly recommended that the carrier board hardware drives the signal low until it is safe to let the module boot-up.

When considering the above shown voltage divider circuitry and the transistor stage, the voltage measured at the PWR_OK input pin may be only around 0.8V when the 12V is applied to the module. Actively driving PWR_OK high is compliant to the COM Express speciﬁcation but this can cause back driving. Therefore, congatec recommends driving the PWR_OK low to keep the module in reset and tri-state PWR_OK when the carrier board hardware is ready to boot.

The three typical usage scenarios for a carrier board design are:

• Connect PWR_OK to the “power good” signal of an ATX type power supply.

• Connect PWR_OK to the last voltage regulator in the chain on the carrier board.

• Simply pull PWR_OK with a 1k resistor to the carrier board 3.3V power rail.

With this solution, it must be ensured that by the time the 3.3V is up, all carrier board hardware is fully powered and all clocks are stable.

Page 35

The conga-TS87 provides support for controlling ATX-style power supplies. When not using an ATX power supply then the conga-TS87’s pins SUS_S3/PS_ON, 5V_SB, and PWRBTN# should be left unconnected.

SUS_S3#/PS_ON#

The SUS_S3#/PS_ON# (pin A15 on the A-B connector) signal is an active-low output that can be used to turn on the main outputs of an ATXstyle power supply. In order to accomplish this the signal must be inverted with an inverter/transistor that is supplied by standby voltage and is located on the carrier board.

PWRBTN#

When using ATX-style power supplies PWRBTN# (pin B12 on the A-B connector) is used to connect to a momentary-contact, active-low debounced push-button input while the other terminal on the push-button must be connected to ground. This signal is internally pulled up to 3V_SB using a 10k resistor. When PWRBTN# is asserted it indicates that an operator wants to turn the power on or off. The response to this signal from the system may vary as a result of modiﬁcations made in BIOS settings or by system software.

Power Supply Implementation Guidelines

12 volt input power is the sole operational power source for the conga-TS87. The remaining necessary voltages are internally generated on the module using onboard voltage regulators. A carrier board designer should be aware of the following important information when designing a power supply for a conga-TS87 application:

• It has also been noticed that on some occasions, problems occur when using a 12V power supply that produces non monotonic voltage when powered up. The problem is that some internal circuits on the module (e.g. clock-generator chips) will generate their own reset signals when the supply voltage exceeds a certain voltage threshold. A voltage dip after passing this threshold may lead to these circuits becoming confused resulting in a malfunction. It must be mentioned that this problem is quite rare but has been observed in some mobile power supply applications. The best way to ensure that this problem is not encountered is to observe the power supply rise waveform through the use of an oscilloscope to determine if the rise is indeed monotonic and does not have any dips. This should be done during the power supply qualiﬁcation phase therefore ensuring that the above mentioned problem doesn’t arise in the application. For more information about this issue visit www.formfactors.org and view page 25 ﬁgure 7 of the document “ATX12V Power Supply Design Guide V2.2”.

6.1.13 Power Management

ACPI 3.0 compliant with battery support. Also supports Suspend to RAM (S3).

Page 36

6.2 Secondary Connector Rows C and D

The following subsystems can be found on the secondary connector rows C and D.

6.2.1 PCI Express™

The conga-TS87 offers 1 lane on the CD connector and 6 lanes on the AB connector. The PCI Express interface is based on the PCI Express Speciﬁcation 2.0 with Gen 1 (2.5Gb/s) and Gen 2 (5 Gb/s) speed.

6.2.2 PCI Express Graphics (PEG)

PCI Express Graphics (PEG) is supported on conga-TS87 variants. The PEG lanes are same as PCI Express lanes 16-31 and are designed to be compliant with the PCI Express Speciﬁcation 3.0, with support for 8.0 Gb/s speed.

The x16 PEG interface is by default conﬁgured as a 1x16 link. It is however possible to optionally conﬁgure the x16 PEG interface to support graphics and/or non-graphic PCI Express devices. This conﬁguration increases the available PCI Express lanes on top of those explained in section 6.1.7 and section 6.2.1. It also enables the use of the PEG lanes for supporting x1, x2, x4 or x8 PCI Express devices. The possible conﬁgurations are 1x16 link (default), 2x8 links or 1x8 + 2x4 links as shown in the diagram below:

PEG

LANE

Single Link (1x16 Link)

Link 1

Double Links (2x8 Links)

Link 1

Triple Links (1x8 + 2x4 Links)

Link 1 Link 2 Link 3

Link 2

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The 16 PEG lanes can operate at 2.5 GT/s, 5 GT/s or 8 GT/s.

The sixteen PCIe lanes of the PEG interface are controlled by three controllers. Each controller can automatically operate on a lower link width allowing up to three simultaneous operating devices on the PEG interface. The PEG root port conﬁguration can be selected in the BIOS setup.

Note

The PEG lanes can not be linked together with the PCI Express lanes discussed in sections 6.1.7 and 6.2.1.

6.2.3 Digital Display Interface

The Haswell processor onboard the conga-TS87 supports three Digital Display Interfaces. These interfaces can be conﬁgured as DisplayPort, HDMI or DVI. The processor also supports High-bandwidth Digital Content Protection (HDCP) for playing high deﬁnition content over digital interfaces.

Integrated in the processor is a dedicated Mini HD audio controller which drives audio on integrated digital display interfaces such as HDMI and DisplayPort. This controller supports two High Deﬁnition Audio streams simultaneously on any of the three digital ports.

For three independent displays, the processor supports the combination of DisplayPort, HDMI, DVI and VGA as shown below. This combination however does not include three simultaneous HDMI/DVI display.

Table 3 Display Combination

Display 1 Display 2 Display 3 Display 1

Max. Resolution

DP DP DP 3840x2160 @60Hz 3840x2160 @60Hz 3840x2160 @60Hz

HDMI HDMI DP 4096x2304 @24Hz

2560x1600 @60Hz

DVI DVI DP 1920x1200 @60Hz 1920x1200 @60Hz 3840x2160 @60Hz

VGA DP HDMI 1920x1200 @60Hz 3840x2160 @60Hz 4096x2304 @24Hz

LVDS/eDP DP HDMI LVDS:1920x1200@60Hz

eDP: 3840x2160 @60Hz

LVDS/eDP DP DP LVDS:1920x1200@60Hz

eDP: 3840x2160 @60Hz

LVDS/eDP HDMI HDMI LVDS:1920x1200@60Hz

eDP: 3840x2160 @60Hz

Display 2 Max. Resolution

4096x2304 @24Hz 2560x1600 @60Hz

3840x2160 @60Hz 4096x2304 @24Hz

3840x2160 @60Hz 3840x2160 @60Hz

4096x2304 @24Hz 2560x1600 @60Hz

Display 3 Max. Resolution

3840x2160 @60Hz

2560x1600 @60Hz

4096x2304 @24Hz 2560x1600 @60Hz

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Note

Two channel DDR3L memory conﬁguration is required for driving three simultaneous 3840x2160 @ 60Hz display resolutions.

6.2.3.1 HDMI

The conga-TS87 offers three HDMI ports on the CD connector via the Digital Display Interfaces supported by the processor. The HDMI interfaces are based on HDMI 1.4 speciﬁcation with support for 3D, 4K, Deep Color and x.v Color. These interfaces are multiplexed onto the Digital Display Interface of the COM Express connector.

Supported audio formats are AC-3 Dolby Digital, Dolby Digital Plus, DTS-HD, LPCM, 192 KHz/24 bit, 8 channel, Dolby TrueHD, DTS-HD Master Audio (Lossless Blu-Ray Disc Audio Format).

Note

The processor supports a maximum of 2 independent HDMI displays. See table 2 above for possible display combinations.

6.2.3.2 DVI

The conga-TS87 offers three DVI ports on the CD connector. The DVI interfaces are multiplexed onto the Digital Display Interface of the COM Express connector.

Note

The processor supports a maximum of 2 independent DVI displays. See table 2 above for possible display combinations.

6.2.3.3 DisplayPort (DP)

The conga-TS87 offers three DP ports, each capable of supporting data rate of 1.62 GT/s, 2.7 GT/s and 5.4 GT/s on 1, 2 or 4 data lanes. The DP is multiplexed onto the Digital Display Interface (DDI) of the COM Express connector and can support up to 3840x2160 resolutions at 60Hz.

The DisplayPort speciﬁcation is a VESA standard aimed at consolidating internal and external connection methods to reduce device complexity, supporting key cross industry applications, and providing performance scalability to enable the next generation of displays. See section 9.5 of this document for more information about enabling DisplayPort peripherals.

Note

The DisplayPort supports 3 independent displays. See table 2 above for possible display combinations.

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6.2.4 USB 3.0

The conga-TS87 offers four SuperSpeed USB 3.0 ports on variants with Intel QM87 and two SuperSpeed USB 3.0 on variants with Intel HM86. These ports are controlled by an xHCI host controller provided by the Intel® QM87/HM86 PCH. The host controller allows data transfers of up to 5 Gb/s and supports SuperSpeed, high-speed, full-speed and low-speed trafﬁc.

Note

The xHCI controller does not support USB debug port. If you desire USB debug port functionality, use the EHCI based debug port.

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7 Additional Features

7.1 congatec Board Controller (cBC)

The conga-TS87 is equipped with a STMicroelectronics STM32 microcontroller. This onboard microcontroller plays an important role for most of the congatec embedded/industrial PC features. It fully isolates some of the embedded features such as system monitoring or the I²C bus from the x86 core architecture, which results in higher embedded feature performance and more reliability, even when the x86 processor is in a low power mode. It also ensures that the congatec embedded feature set is fully compatible amongst all congatec modules.

7.2 Board Information

The cBC provides a rich data-set of manufacturing and board information such as serial number, EAN number, hardware and ﬁrmware revisions, and so on. It also keeps track of dynamically changing data like runtime meter and boot counter.

7.3 Watchdog

The conga-TS87 is equipped with a multi stage watchdog solution that is triggered by software. The COM Express™ Speciﬁcation does not provide support for external hardware triggering of the Watchdog, which means the conga-TS87 does not support external hardware triggering. For more information about the Watchdog feature, see the BIOS setup description in section 11.4.2 of this document and application note AN3_Watchdog.pdf on the congatec AG website at www.congatec.com.

Note

The conga-TS87 module does not support the watchdog NMI mode.

7.4 I2C Bus

The conga-TS87 supports I2C bus. Thanks to the I2C host controller in the cBC, the I2C bus is multimaster capable and runs at fast mode.

7.5 Power Loss Control

The cBC has full control of the power-up of the module and therefore can be used to specify the behaviour of the system after a AC power loss condition. Supported modes are “Always On”, “Remain Off” and “Last State”.

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7.6 OEM BIOS Customization

The conga-TS87 is equipped with congatec Embedded BIOS, which is based on American Megatrends Inc. Aptio UEFI ﬁrmware. The congatec Embedded BIOS allows system designers to modify the BIOS. For more information about customizing the congatec Embedded BIOS, refer to the congatec System Utility user’s guide, which is called CGUTLm1x.pdf and can be found on the congatec website at www.congatec.com or contact technical support.

The customization features supported are described below:

7.6.1 OEM Default Settings

This feature allows system designers to create and store their own BIOS default conﬁguration. Customized BIOS development by congatec for OEM default settings is no longer necessary because customers can easily perform this conﬁguration by themselves using the congatec system utility CGUTIL. See congatec application note AN8_Create_OEM_Default_Map.pdf on the congatec website for details on how to add OEM default settings to the congatec Embedded BIOS.

7.6.2 OEM Boot Logo

This feature allows system designers to replace the standard text output displayed during POST with their own BIOS boot logo. Customized BIOS development by congatec for OEM Boot Logo is no longer necessary because customers can easily perform this conﬁguration by themselves using the congatec system utility CGUTIL. See congatec application note AN8_Create_And_Add_Bootlogo.pdf on the congatec website for details on how to add OEM boot logo to the congatec Embedded BIOS.

7.6.3 OEM POST Logo

This feature allows system designers to replace the congatec POST logo displayed in the upper left corner of the screen during BIOS POST with their own BIOS POST logo. Use the congatec system utility CGUTIL 1.5.4 or later to replace/add the OEM POST logo.

7.6.4 OEM BIOS Code/Data

With the congatec embedded BIOS it is possible for system designers to add their own code to the BIOS POST process. The congatec Embedded BIOS ﬁrst calls the OEM code before handing over control to the OS loader.

Except for custom speciﬁc code, this feature can also be used to support Win XP SLP installation, Window 7 SLIC table (OA2.0), Windows 8 OEM activation (OA3.0), verb tables for HDA codecs, PCI/PCIe opROMs, bootloaders, rare graphic modes and Super I/O controller initialization.

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Note

The OEM BIOS code of the new UEFI based ﬁrmware is only called when the CSM (Compatibility Support Module) is enabled in the BIOS setup menu. Contact congatec technical support for more information on how to add OEM code.

7.6.5 OEM DXE Driver

This feature allows designers to add their own UEFI DXE driver to the congatec embedded BIOS. Contact congatec technical support for more information on how to add an OEM DXE driver.

7.7 congatec Battery Management Interface

In order to facilitate the development of battery powered mobile systems based on embedded modules, congatec AG has deﬁned an interface for the exchange of data between a CPU module (using an ACPI operating system) and a Smart Battery system. A system developed according to the congatec Battery Management Interface Speciﬁcation can provide the battery management functions supported by an ACPI capable operating system (e.g. charge state of the battery, information about the battery, alarms/events for certain battery states, ...) without the need for any additional modiﬁcations to the system BIOS.

The conga-TS87 BIOS fully supports this interface. For more information about this subject visit the congatec website and view the following documents:

• congatec Battery Management Interface Speciﬁcation

• Battery System Design Guide

• conga-SBM3 User’s Guide

7.8 API Support (CGOS)

In order to beneﬁt from the above mentioned non-industry standard feature set, congatec provides an API that allows application software developers to easily integrate all these features into their code. The CGOS API (congatec Operating System Application Programming Interface) is the congatec proprietary API that is available for all commonly used Operating Systems such as Win32, Win64, Win CE, Linux. The architecture of the CGOS API driver provides the ability to write application software that runs unmodiﬁed on all congatec CPU modules. All the hardware related code is contained within the congatec embedded BIOS on the module. See section 1.1 of the CGOS API software developers guide, which is available on the congatec website .

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7.9 Security Features

The conga-TS87 can be equipped optionally with a “Trusted Platform Module“ (TPM 1.2). This TPM 1.2 includes coprocessors to calculate efﬁcient hash and RSA algorithms with key lengths up to 2,048 bits as well as a real random number generator. Security sensitive applications like gaming and e-commerce will beneﬁt also with improved authentication, integrity and conﬁdence levels.

7.10 Suspend to Ram

The Suspend to RAM feature is available on the conga-TS87.

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8 conga Tech Notes

The conga-TS87 has some technological features that require additional explanation. The following section will give the reader a better understanding of some of these features. This information will also help to gain a better understanding of the information found in the System Resources section of this user’s guide as well as some of the setup nodes found in the BIOS Setup Program description section.

8.1 Intel® PCH Features

8.1.1 Intel® Rapid Storage Technology

The Intel

QM87 provides support for Intel® Rapid Storage Technology, allowing AHCI functionality and RAID 0/1/5/10 support.

8.1.1.1 AHCI

The Intel® DH82QM87 or DH82HM86 provides hardware support for Advanced Host Controller Interface (AHCI), a new programming interface for SATA host controllers. Platforms supporting AHCI may take advantage of performance features such as no master/slave designation for SATA devices (each device is treated as a master) and hardware-assisted native command queuing. AHCI also provides usability enhancements such as Hot-Plug.

8.1.1.2 RAID

The industry-leading RAID capability provides high performance RAID 0, 1, 5, and 10 functionality on the 4 SATA ports of Intel Software components include an Option ROM for pre-boot conﬁguration and boot functionality, a Microsoft* Windows* compatible driver, and a user interface for conﬁguration and management of the RAID capability of the Intel

Note

The conga-TS87 variants that feature the Intel® HM86 chipset do not support RAID.

8.1.2 Intel® Smart Response Technology

QM87 PCH.

Intel® Smart Response Technology is a disk caching solution that can provide improved computer system performance with improved power savings. It allows conﬁguration of a computer systems with the advantage of having HDDs for maximum storage capacity with system performance at or near SSD performance levels.

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8.1.3 Intel® Rapid Start Technology

Intel® Rapid Start Technology enables systems to quickly resume from deep sleep. With this feature enabled, the system resumes smoothly and faster than with fresh Start Up or Resume from Hibernate, while maintaining the previous activity of the user.

Note

This feature requires an Intel® Core Processor

8.2 Intel® Processor Features

8.2.1 Intel® Turbo Boost Technology

Intel® Turbo Boost Technology allows processor cores to run faster than the base operating frequency if it’s operating below power, current, and

temperature speciﬁcation limits. Intel performance state. The maximum frequency of Intel

Turbo Boost Technology is activated when the Operating System (OS) requests the highest processor

Turbo Boost Technology is dependent on the number of active cores. The amount of time

the processor spends in the Intel Turbo Boost 2 Technology state depends on the workload and operating environment. Any of the following

can set the upper limit of Intel

Turbo Boost Technology on a given workload:

• Number of active cores

• Estimated current consumption

• Estimated power consumption

• Processor temperature

When the processor is operating below these limits and the user’s workload demands additional performance, the processor frequency will dynamically increase by 100 MHz on short and regular intervals until the upper limit is met or the maximum possible upside for the number of

active cores is reached. For more information about Intel

Turbo Boost 2 Technology visit the Intel® website.

Note

Only conga-TS87 module variants that feature the Core™ i7 and i5 processors support Intel® Turbo Boost 2 Technology. Refer to the power consumption tables in section 2.5 of this document for information about the maximum turbo frequency available for each variant of the conga-TS87.

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8.2.2 Thermal Monitor and Catastrophic Thermal Protection

Intel® Core™ i7/i5/i3 and Celeron® processors have a thermal monitor feature that helps to control the processor temperature. The integrated TCC (Thermal Control Circuit) activates if the processor silicon reaches its maximum operating temperature. The activation temperature that the

Intel

Thermal Monitor uses to activate the TCC, can be slightly modiﬁed via TCC Activation Offset in BIOS setup submenu “CPU submenu”.

The Thermal Monitor can control the processor temperature through the use of two different methods deﬁned as TM1 and TM2. TM1 method consists of the modulation (starting and stopping) of the processor clocks at a 50% duty cycle. The TM2 method initiates an Enhanced Intel Speedstep transition to the lowest performance state once the processor silicon reaches the maximum operating temperature.

Note

The maximum operating temperature for Intel® Core™ i7/i5/i3 and Celeron® processors is 100°C.

To ensure that the TCC is active for only short periods of time, thus reducing the impact on processor performance to a minimum, it is necessary to have a properly designed thermal solution. The Intel you with more information about this subject.

THERMTRIP# signal is used by Intel

’s Core™ i7/i5/i3 and Celeron® processors for catastrophic thermal protection. If the processor’s silicon reaches a temperature of approximately 125°C then the processor signal THERMTRIP# will go active and the system will automatically shut down to prevent any damage to the processor as a result of overheating. The THERMTRIP# signal activation is completely independent from processor activity and therefore does not produce any bus cycles.

Note

In order for THERMTRIP# to be able to automatically switch off the system, it is necessary to use an ATX style power supply.

8.2.3 Processor Performance Control

Intel® Core™ i7/i5/i3 and Celeron is referred to as Enhanced Intel® SpeedStep® technology (EIST). Operating systems that support performance control take advantage of microprocessors that use several different performance states in order to efﬁciently operate the processor when it’s not being fully used. The operating system will determine the necessary performance state that the processor should run at so that the optimal balance between performance and power consumption can be achieved during runtime.

The Windows family of operating systems links its processor performance control policy to the power scheme setting. You must ensure that the power scheme setting you choose has the ability to support Enhanced Intel

processors found on the conga-TS87 run at different voltage/frequency states (performance states), which

Core™ i7/i5/i3 and Celeron® processor’s respective datasheet can provide

SpeedStep® technology.

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8.2.4 Intel® 64 Architecture

The formerly known Intel® Extended Memory 64 Technology is an enhancement to Intel®’s IA-32 architecture. Intel® 64 is only available on Intel® Core™ i7/i5/i3 and Celeron

processors and is designed to run with newly written 64-bit code and access more than 4GB of memory. Processors with Intel® 64 architecture support 64-bit-capable operating systems from Microsoft, Red Hat and SuSE. Processors running in legacy mode remain fully compatible with today’s existing 32-bit applications and operating systems

Platforms with Intel

64 can be run in three basic ways :

1. Legacy Mode: 32-bit operating system and 32-bit applications. In this mode no software changes are required, however the beneﬁts of

Intel® 64 are not utilized.

2. Compatibility Mode: 64-bit operating system and 32-bit applications. This mode requires all device drivers to be 64-bit. The operating

system will see the 64-bit extensions but the 32-bit application will not. Existing 32-bit applications do not need to be recompiled and may or may not beneﬁt from the 64-bit extensions. The application will likely need to be re-certiﬁed by the vendor to run on the new 64bit extended operating system.

3. 64-bit Mode: 64-bit operating system and 64-bit applications. This usage requires 64-bit device drivers. It also requires applications to be

modiﬁed for 64-bit operation and then recompiled and validated.

Intel® 64 provides support for:

• 64-bit ﬂat virtual address space

• 64-bit pointers

• 64-bit wide general purpose registers

• 64-bit integer support

• Up to one Terabyte (TB) of platform address space

You can ﬁnd more information about Intel

64 Technology at: http://developer.intel.com/technology/intel64/index.htm

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8.2.5 Intel® Virtualization Technology

Intel® Virtualization Technology (Intel® VT) makes a single system appear as multiple independent systems to software. This allows multiple, independent operating systems to run simultaneously on a single system. Intel® VT comprises technology components to support virtualization of platforms based on Intel architecture microprocessors and chipsets. Intel® Virtualization Technology for IA-32, Intel® 64 and Intel® Architecture Intel® VT-x) added hardware support in the processor to improve the virtualization performance and robustness.

Note

congatec does not offer virtual machine monitor (VMM) software. All VMM software support questions and queries should be directed to the VMM software vendor and not congatec technical support.

8.2.6 Thermal Management

ACPI is responsible for allowing the operating system to play an important part in the system’s thermal management. This results in the operating system having the ability to take control of the operating environment by implementing cooling decisions according to the demands put on the CPU by the application.

The conga-TS87 supports Critical Trip Point. This cooling policy ensures that the operating system shuts down properly if the temperature in the thermal zone reaches a critical point, in order to prevent damage to the system as a result of high temperatures. Use the “critical trip point” setup node in the BIOS setup program to determine the temperature threshold that the operating system will use to shut down the system.

Note

The end user must determine the cooling preferences for the system by using the setup nodes in the BIOS setup program to establish the appropriate trip points.

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8.3 ACPI Suspend Modes and Resume Events

conga-TS87 supports S3 (STR= Suspend to RAM). For more information about S3 wake events, see section 11.4.5 “ACPI Conﬁguration Submenu”.

S4 (Suspend to Disk) is not supported by the BIOS (S4_BIOS) but it is supported by the following operating systems (S4_OS= Hibernate):

• Windows 8, Windows 7, Windows Vista, Linux.

This table lists the “Wake Events” that resume the system from S3 unless otherwise stated in the “Conditions/Remarks” column:

Wake Event Power Button Onboard LAN Event SMBALERT# PCI Express WAKE# PME#

USB Mouse/Keyboard Event

RTC Alarm Watchdog Power Button

Conditions/Remarks

Wakes unconditionally from S3-S5.

Device driver must be conﬁgured for Wake On LAN support.

Wakes unconditionally from S3-S5.

Activate the wake up capabilities of a PCI device using Windows Device Manager conﬁguration options for this device OR set Resume On PME# to Enabled in the Power setup menu.

When Standby mode is set to S3, USB hardware must be powered by standby power source. Set USB Device Wakeup from S3/S4 to ENABLED in the ACPI setup menu (if setup node is available in BIOS setup program). In Device Manager look for the keyboard/mouse devices. Go to the Power Management tab and check ‘Allow this device to bring the computer out of standby’.

Activate and conﬁgure Resume On RTC Alarm in the Power setup menu. Only available in S5.

Wakes unconditionally from S3-S5.

Event

8.4 Low Voltage Memory (DDR3L)

The Haswell processor featured on the conga-TS87 supports low voltage system memory interface. The memory interface I/O voltage is 1.35V and supports non-ECC, unbuffered DDR3L SO-DIMMs. With this low voltage system memory interface on the processor, the conga-TS87 offers a system optimized for lowest possible power consumption. The reduction in power consumption due to lower voltage subsequently reduces the heat generated.

Note

The usage of DDR3@1.5V SO-DIUM modules may affect the stability or boot-up of the conga-TS87. Therefore use only non-ECC, unbuffered DDR3L SO-DIMM memory modules up to 1600 MT/s on the conga-TS87.

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8.5 USB 2.0 EHCI Host Controller Support

The 8 available USB ports are provided by two USB 2.0 Rate Matching Hubs (RMH) integrated within the Intel® QM87 PCH . Each EHCI controller has one hub connected to it as shown below. The Hubs convert low and full-speed trafﬁc into high-speed trafﬁc. When the RMHs are enabled, they will appear to software like an external hub is connected to Port 0 of each EHCI controller. In addition, port 1 of each of the RMHs is muxed with Port 1 of the EHCI controllers and is able to bypass the RMH for use as the Debug Port. The hub operates like any USB 2.0 Discrete Hub and will consume one tier of hubs allowed by the USB 2.0 Spec. A maximum of four additional non-root hubs can be supported on any of the PCH USB Ports. The RMH will report the following Vendor ID = 8087h and Product ID = 0024h.

Routing Diagram

EHCI #1 EHCI #2EHCI #1

EHCI #1 EHCI #2

EHCI #2

USB 2.0 Rate Matching HubUSB 2.0 Rate Matching Hub

Port 5Port 4Port 3Port 2Port 1Port 0Internal Port:

Port 5Port 4Port 3Port 2Port 1Port 0COM Express Port: Unused Unused UnusedUnusedPort 7Port 6UnusedUnused

Port 7Port 6

Ports 6-7 and 10-13

Not supported on the conga-TS87

Port 11 Port 12 Port 13Port 10Port 9Port 8

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9 Signal Descriptions and Pinout Tables

The following section describes the signals found on COM Express™ Type VI connectors used for congatec AG modules. The pinout of the modules complies with COM Express Type 6 Rev. 2.1.

Table 3 describes the terminology used in this section for the Signal Description tables. The PU/PD column indicates if a COM Express™ module pull-up or pull-down resistor has been used, if the ﬁeld entry area in this column for the signal is empty, then no pull-up or pull-down resistor has been implemented by congatec.

The “#” symbol at the end of the signal name indicates that the active or asserted state occurs when the signal is at a low voltage level. When “#” is not present, the signal is asserted when at a high voltage level.

Note

The Signal Description tables do not list internal pull-ups or pull-downs implemented by the chip vendors, only pull-ups or pull-downs implemented by congatec are listed. For information about the internal pull-ups or pull-downs implemented by the chip vendors, refer to the respective chip’s datasheet.

Table 4 Signal Tables Terminology Descriptions

Term Description

PU congatec implemented pull-up resistor

PD congatec implemented pull-down resistor

I/O 3.3V Bi-directional signal 3.3V tolerant

I/O 5V Bi-directional signal 5V tolerant

I 3.3V Input 3.3V tolerant

I 5V Input 5V tolerant

I/O 3.3VSB Input 3.3V tolerant active in standby state

O 3.3V Output 3.3V signal level

O 5V Output 5V signal level

OD Open drain output

P Power Input/Output

DDC Display Data Channel

PCIE In compliance with PCI Express Base Speciﬁcation, Revision 2.0

PEG PCI Express Graphics

SATA In compliance with Serial ATA speciﬁcation Revision 2.6 and 3.0.

REF Reference voltage output. May be sourced from a module power plane.

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PDS Pull-down strap. A module output pin that is either tied to GND or is not connected. Used to signal module

capabilities (pinout type) to the Carrier Board.

9.1 A-B Connector Signal Descriptions

Table 5 Intel® High Deﬁnition Audio Link Signals Descriptions

Signal Pin # Description I/O PU/PD Comment

AC/HDA_RST# A30 Intel® High Deﬁnition Audio Reset: This signal is the master hardware reset to

external codec(s).

AC/HDA_SYNC A29 Intel

AC/HDA_BITCLK A32 Intel

AC/HDA_SDOUT A33 Intel

AC/HDA_SDIN[2:0] B28-B30 Intel

Note

High Deﬁnition Audio Sync: This signal is a 48 kHz ﬁxed rate sample

sync to the codec(s). It is also used to encode the stream number.

High Deﬁnition Audio Bit Clock Output: This signal is a 24.000MHz

serial data clock generated by the Intel® High Deﬁnition Audio controller.

High Deﬁnition Audio Serial Data Out: This signal is the serial TDM data

output to the codec(s). This serial output is double-pumped for a bit rate of 48 Mb/s for Intel® High Deﬁnition Audio.

High Deﬁnition Audio Serial Data In [0]: These signals are serial TDM

data inputs from the three codecs. The serial input is single-pumped for a bit rate of 24 Mb/s for Intel® High Deﬁnition Audio.

O 3.3VSB AC’97 codecs are not supported.

O 3.3VSB PU 1K

3.3VSB

O 3.3VSB AC’97 codecs are not supported.

O 3.3VSB PU 1K

3.3VSB

I 3.3VSB AC’97 codecs are not supported.

AC’97 codecs are not supported. AC/HDA_SYNC is a boot strap signal (see note below)

AC’97 codecs are not supported. AC/HDA_SDOUT is a boot strap signal (see note below)

Some signals have special functionality during the reset process. They may bootstrap some basic important functions of the module.

For more information refer to section 9.5 of this user’s guide.

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Table 6 Gigabit Ethernet Signal Descriptions

Gigabit

Pin # Description I/O PU/PDComment

Ethernet

GBE0_MDI0+ GBE0_MDI0GBE0_MDI1+ GBE0_MDI1GBE0_MDI2+ GBE0_MDI2GBE0_MDI3+ GBE0_MDI3-

GBE0_ACT# B2 Gigabit Ethernet Controller 0 activity indicator, active low. O 3.3VSB

GBE0_LINK# A8 Gigabit Ethernet Controller 0 link indicator, active low. O 3.3VSB

GBE0_LINK100# A4 Gigabit Ethernet Controller 0 100Mbit/sec link indicator, active low. O 3.3VSB

GBE0_LINK1000# A5 Gigabit Ethernet Controller 0 1000Mbit/sec link indicator, active low. O 3.3VSB

GBE0_CTREF A14 Reference voltage for Carrier Board Ethernet channel 0 magnetics center tap. The reference voltage is

A13 A12 A10 A9 A7 A6 A3 A2

Gigabit Ethernet Controller 0: Media Dependent Interface Differential Pairs 0, 1, 2, 3. The MDI can operate in 1000, 100, and 10Mbit/sec modes. Some pairs are unused in some modes according to the following:

1000 100 10

MDI[0]+/- B1_DA+/- TX+/- TX+/-

MDI[1]+/- B1_DB+/- RX+/- RX+/-

MDI[2]+/- B1_DC+/-

MDI[3]+/- B1_DD+/-

determined by the requirements of the module PHY and may be as low as 0V and as high as 3.3V. The reference voltage output shall be current limited on the module. In the case in which the reference is shorted to ground, the current shall be limited to 250mA or less.

I/O Analog

Twisted pair signals for external transformer.

Not connected

Note

The GBE0_LINK# output is only active during a 100Mbit or 1Gbit connection, it is not active during a 10Mbit connection. This is a limitation of Ethernet controller since it only has 3 LED outputs, ACT#, LINK100# and LINK1000#. The GBE0_LINK# signal is a logic AND of the GBE0_LINK100# and GBE0_LINK1000# signals on the conga-TS87 module.

Table 7 Serial ATA Signal Descriptions

Signal Pin # Description I/O PU/PD Comment

SATA0_RX+ SATA0_RX-

SATA0_TX+ SATA0_TX-

SATA1_RX+ SATA1_RX-

SATA1_TX+ SATA1_TX-

A19 A20

A16 A17

B19 B20

B16 B17

Serial ATA channel 0, Receive Input differential pair. I SATA Supports Serial ATA speciﬁcation, Revision 3.0

Serial ATA channel 0, Transmit Output differential pair. O SATA Supports Serial ATA speciﬁcation, Revision 3.0

Serial ATA channel 1, Receive Input differential pair. I SATA Supports Serial ATA speciﬁcation, Revision 3.0

Serial ATA channel 1, Transmit Output differential pair. O SATA Supports Serial ATA speciﬁcation, Revision 3.0

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Signal Pin # Description I/O PU/PD Comment

SATA2_RX+ SATA2_RX-

SATA2_TX+ SATA2_TX-

SATA3_RX+ SATA3_RX-

SATA3_TX+ SATA3_TX-

(S)ATA_ACT# A28 ATA (parallel and serial) or SAS activity indicator, active low. I/O 3.3v

A25 A26

A22 A23

B25 B26

B22 B23

Serial ATA channel 2, Receive Input differential pair. I SATA Supports Serial ATA speciﬁcation, Revision 3.0

Serial ATA channel 2, Transmit Output differential pair. O SATA Supports Serial ATA speciﬁcation, Revision 3.0

Serial ATA channel 3, Receive Input differential pair. I SATA Supports Serial ATA speciﬁcation, Revision 3.0

Serial ATA channel 3, Transmit Output differential pair. O SATA Supports Serial ATA speciﬁcation, Revision 3.0

Table 8 PCI Express Signal Descriptions (general purpose)

Signal Pin # Description I/O PU/PD Comment

PCIE_RX0+ PCIE_RX0-

PCIE_TX0+ PCIE_TX0-

PCIE_RX1+ PCIE_RX1-

PCIE_TX1+ PCIE_TX1-

PCIE_RX2+ PCIE_RX2-

PCIE_TX2+ PCIE_TX2-

PCIE_RX3+ PCIE_RX3-

PCIE_TX3+ PCIE_TX3-

PCIE_RX4+ PCIE_RX4-

PCIE_TX4+ PCIE_TX4-

PCIE_RX5+ PCIE_RX5-

PCIE_TX5+ PCIE_TX5-

B68 B69

A68 A69

B64 B65

A64 A65

B61 B62

A61 A62

B58 B59

A58 A59

B55 B56

A55 A56

B52 B53

A52 A53

PCI Express channel 0, Receive Input differential pair. I PCIE Supports PCI Express Base Speciﬁcation, Revision 2.0

PCI Express channel 0, Transmit Output differential pair. O PCIE Supports PCI Express Base Speciﬁcation, Revision 2.0

PCI Express channel 1, Receive Input differential pair. I PCIE Supports PCI Express Base Speciﬁcation, Revision 2.0

PCI Express channel 1, Transmit Output differential pair. O PCIE Supports PCI Express Base Speciﬁcation, Revision 2.0

PCI Express channel 2, Receive Input differential pair. I PCIE Supports PCI Express Base Speciﬁcation, Revision 2.0

PCI Express channel 2, Transmit Output differential pair. O PCIE Supports PCI Express Base Speciﬁcation, Revision 2.0

PCI Express channel 3, Receive Input differential pair. I PCIE Supports PCI Express Base Speciﬁcation, Revision 2.0

PCI Express channel 3, Transmit Output differential pair. O PCIE Supports PCI Express Base Speciﬁcation, Revision 2.0

PCI Express channel 4, Receive Input differential pair. I PCIE Supports PCI Express Base Speciﬁcation, Revision 2.0

PCI Express channel 4, Transmit Output differential pair. O PCIE Supports PCI Express Base Speciﬁcation, Revision 2.0

PCI Express channel 5, Receive Input differential pair. I PCIE Supports PCI Express Base Speciﬁcation, Revision 2.0

PCI Express channel 5, Transmit Output differential pair. O PCIE Supports PCI Express Base Speciﬁcation, Revision 2.0

Page 55

PCIE_CLK_REF+ PCIE_CLK_REF-

A88 A89

PCI Express Reference Clock output for all PCI Express and PCI Express Graphics Lanes.

O PCIE A PCI Express Gen2/3 compliant clock buffer chip must be

used on the carrier board if more than one PCI Express device is designed in.

Table 9 ExpressCard Support Pins Signal Descriptions

Signal Pin # Description I/O PU/PD Comment

EXCD0_CPPE# EXCD1_CPPE#

EXCD0_PERST# EXCD1_PERST#

A49 B48

A48 B47

ExpressCard capable card request. I 3.3V PU 10k 3.3V

ExpressCard Reset O 3.3V PU 10k 3.3V

Table 10 LPC Signal Descriptions

Signal Pin # Description I/O PU/PD Comment

LPC_AD[0:3] B4-B7 LPC multiplexed address, command and data bus I/O 3.3V

LPC_FRAME# B3 LPC frame indicates the start of an LPC cycle O 3.3V

LPC_DRQ[0:1]# B8-B9 LPC serial DMA request I 3.3V

LPC_SERIRQ A50 LPC serial interrupt I/O OD

3.3V

LPC_CLK B10 LPC clock output - 33MHz nominal O 3.3V

PU 10k 3.3V

Table 11 USB Signal Descriptions

Signal Pin # Description I/O PU/PD Comment

USB0+ A46 USB Port 0, data + or D+ I/O USB 2.0 compliant. Backwards compatible to USB 1.1

USB0- A45 USB Port 0, data - or D- I/O USB 2.0 compliant. Backwards compatible to USB 1.1

USB1+ B46 USB Port 1, data + or D+ I/O USB 2.0 compliant. Backwards compatible to USB 1.1

USB1- B45 USB Port 1, data - or D- I/O USB 2.0 compliant. Backwards compatible to USB 1.1

USB2+ A43 USB Port 2, data + or D+ I/O USB 2.0 compliant. Backwards compatible to USB 1.1

USB2- A42 USB Port 2, data - or D- I/O USB 2.0 compliant. Backwards compatible to USB 1.1

USB3+ B43 USB Port 3, data + or D+ I/O USB 2.0 compliant. Backwards compatible to USB 1.1

USB3- B42 USB Port 3, data - or D- I/O USB 2.0 compliant. Backwards compatible to USB 1.1

USB4+ A40 USB Port 4, data + or D+ I/O USB 2.0 compliant. Backwards compatible to USB 1.1

Page 56

Signal Pin # Description I/O PU/PD Comment

USB4- A39 USB Port 4, data - or D- I/O USB 2.0 compliant. Backwards compatible to USB 1.1

USB5+ B40 USB Port 5, data + or D+ I/O USB 2.0 compliant. Backwards compatible to USB 1.1

USB5- B39 USB Port 5, data - or D- I/O USB 2.0 compliant. Backwards compatible to USB 1.1

USB6+ A37 USB Port 6, data + or D+ I/O USB 2.0 compliant. Backwards compatible to USB 1.1

USB6- A36 USB Port 6, data - or D- I/O USB 2.0 compliant. Backwards compatible to USB 1.1

USB7+ B37 USB Port 7, data + or D+ I/O USB 2.0 compliant. Backwards compatible to USB 1.1

USB7- B36 USB Port 7, data - or D- I/O USB 2.0 compliant. Backwards compatible to USB 1.1

USB_0_1_OC# B44 USB over-current sense, USB ports 0 and 1. A pull-up for this line shall

be present on the module. An open drain driver from a USB current monitor on the carrier board may drive this line low.

USB_2_3_OC# A44 USB over-current sense, USB ports 2 and 3. A pull-up for this line shall

be present on the module. An open drain driver from a USB current monitor on the carrier board may drive this line low. .

USB_4_5_OC# B38 USB over-current sense, USB ports 4 and 5. A pull-up for this line shall

be present on the module. An open drain driver from a USB current monitor on the carrier board may drive this line low.

USB_6_7_OC# A38 USB over-current sense, USB ports 6 and 7. A pull-up for this line shall

be present on the module. An open drain driver from a USB current monitor on the carrier board may drive this line low.

3.3VSB

PU 10k

3.3VSB

PU 10k

3.3VSB

PU 10k

3.3VSB

PU 10k

3.3VSB

Do not pull this line high on the carrier board.

Table 12 CRT Signal Descriptions

Signal Pin # Description I/O PU/PD Comment

VGA_RED B89 Red for monitor. Analog DAC output, designed to drive a 37.5-Ohm equivalent load.

VGA_GRN B91 Green for monitor. Analog DAC output, designed to drive a 37.5-Ohm equivalent

load.

VGA_BLU

VGA_HSYNC

VGA_VSYNC

VGA_I2C_CK

VGA_I2C_DAT B96 DDC data line.

B92 Blue for monitor. Analog DAC output, designed to drive a 37.5-Ohm equivalent load.

B93 Horizontal sync output to VGA monitor

B94 Vertical sync output to VGA monitor

B95 DDC clock line (I²C port dedicated to identify VGA monitor capabilities)

O Analog

O 3.3V

I/O OD 5V

PD 150R Analog output

PD 150R

PU 2k2 3.3V

Analog output

Page 57

Table 13 LVDS Signal Descriptions

Signal Pin # Description I/O PU/PD Comment

LVDS_A0+ LVDS_A0LVDS_A1+ LVDS_A1LVDS_A2+ LVDS_A2LVDS_A3+ LVDS_A3-

LVDS_A_CK+ LVDS_A_CK-

LVDS_B0+ LVDS_B0LVDS_B1+ LVDS_B1LVDS_B2+ LVDS_B2LVDS_B3+ LVDS_B3-

LVDS_B_CK+ LVDS_B_CK-

LVDS_VDD_EN A77 LVDS panel power enable O 3.3V PD 10k

LVDS_BKLT_EN B79 LVDS panel backlight enable O 3.3V PD 10k

LVDS_BKLT_CTRL B83 LVDS panel backlight brightness control O 3.3V

LVDS_I2C_CK A83 DDC lines used for ﬂat panel detection and control. O 3.3V PU 2k2 3.3V

LVDS_I2C_DAT A84 DDC lines used for ﬂat panel detection and control. I/O 3.3V PU 2k2 3.3V .

A71 A72 A73 A74 A75 A76 A78 A79

A81 A82

B71 B72 B73 B74 B75 B76 B77 B78

B81 B82

LVDS Channel A differential pairs O LVDS

LVDS Channel A differential clock O LVDS

LVDS Channel B differential pairs O LVDS

LVDS Channel B differential clock O LVDS

Table 14 Embedded DisplayPort Signal Descriptions

Signal Pin # Description I/O PU/PD Comment

eDP_TX3+ eDP_TX3eDP_TX2+ eDP_TX2eDP_TX1+ eDP_TX1eDP_TX0+ eDP_TX0-

A81 A82 A71 A72 A73 A74 A75 A76

eDP differential pairs. AC coupled off

module.

eDP_TX2 and eDP_TX3 pairs are not supported on conga-TS87.

Page 58

Signal Pin # Description I/O PU/PD Comment

eDP_VDD_EN A77 eDP power enable. O 3.3V PD 10k

eDP_BKLT_EN B79 eDP backlight enable. O 3.3V PD 10k

eDP_BKLT_CTRL B83 eDP backlight brightness control. O 3.3V

eDP_AUX+ A83 eDP AUX+. AC coupled off

module.

eDP_AUX- A84 eDP AUX-. AC coupled off

module.

eDP_HPD A87 Detection of Hot Plug / Unplug and notiﬁcation of the link

layer.

I 3.3V

Table 15 SPI BIOS Flash Interface Signal Descriptions

Signal Pin # Description I/O PU/PD Comment

SPI_CS# B97 Chip select for Carrier Board SPI BIOS Flash. O 3.3VSB Carrier shall pull to SPI_POWER when

external SPI provided but not used.

SPI_MISO A92 Data in to module from carrier board SPI BIOS ﬂash. I 3.3VSB

SPI_MOSI A95 Data out from module to carrier board SPI BIOS ﬂash. O 3.3VSB

SPI_CLK A94 Clock from module to carrier board SPI BIOS ﬂash. O 3.3VSB

SPI_POWER A91 Power source for carrier board SPI BIOS ﬂash. SPI_POWER shall be used to power

SPI BIOS ﬂash on the carrier only.

BIOS_DIS0# A34 Selection strap to determine the BIOS boot device. I 3.3VSB PU 10K

BIOS_DIS1# B88 Selection strap to determine the BIOS boot device. I 3.3VSB PU 10K

+ 3.3VSB

Carrier shall be left as no-connect.

3.3VSB

Carrier shall be left as no-connect

3.3VSB

Table 16 Miscellaneous Signal Descriptions

Signal Pin # Description I/O PU/PD Comment

I2C_CK B33 General purpose I²C port clock output/input I/O 3.3V PU 2K2 3.3VSB

I2C_DAT B34 General purpose I²C port data I/O line I/O 3.3V PU 2K2 3.3VSB

SPKR B32 Output for audio enunciator, the “speaker” in PC-AT systems O 3.3V SPEAKER is a boot strap signal

(see note below)

WDT B27 Output indicating that a watchdog time-out event has occurred. O 3.3V PD 10K

Page 59

Signal Pin # Description I/O PU/PD Comment

FAN_PWNOUT B101 Fan speed control. Uses the Pulse Width Modulation (PWM) technique to control

the fan’s RPM.

FAN_TACHIN B102 Fan tachometer input. I OD PU 10K 3.3V Requires a fan with a two pulse

TPM_PP A96 Physical Presence pin of Trusted Platform Module (TPM). Active high. TPM chip

has an internal pull-down. This signal is used to indicate Physical Presence to the TPM.

O OD

3.3V

I 3.3V Trusted Platform Module chip is

PU 10K 3.3V

output.

optional.

Note

Some signals have special functionality during the reset process. They may bootstrap some basic important functions of the module. For more information refer to section 9.5 of this user’s guide.

Table 17 General Purpose I/O Signal Descriptions

Signal Pin # Description I/O PU/PD Comment

GPO0 A93 General purpose output pins.

Shared with SD_CLK. Output from COM Express, input to SD

GPO1 B54 General purpose output pins.

Shared with SD_CMD. Output from COM Express, input to SD

GPO2 B57 General purpose output pins.

Shared with SD_WP. Output from COM Express, input to SD

GPO3 B63 General purpose output pins.

Shared with SD_CD. Output from COM Express, input to SD

GPI0 A54 General purpose input pins. Pulled high internally on the module.

Shared with SD_DATA0. Bidirectional signal

GPI1 A63 General purpose input pins. Pulled high internally on the module.

Shared with SD_DATA1. Bidirectional signal

GPI2 A67 General purpose input pins. Pulled high internally on the module.

Shared with SD_DATA2. Bidirectional signal

GPI3 A85 General purpose input pins. Pulled high internally on the module.

Shared with SD_DATA3. Bidirectional signal.

O 3.3V SDIO interface is not supported on the conga-TS87

I 3.3V PU 10K 3.3V SDIO interface is not supported on the conga-TS87

Page 60

Table 18 Power and System Management Signal Descriptions

Signal Pin # Description I/O PU/PD Comment

PWRBTN# B12 Power button to bring system out of S5 (soft off), active on falling edge. I 3.3VSB PU 10k 3.3VSB

SYS_RESET# B49 Reset button input. Active low input. Edge triggered.

System will not be held in hardware reset while this input is kept low.

CB_RESET# B50 Reset output from module to Carrier Board. Active low. Issued by module chipset and may

result from a low SYS_RESET# input, a low PWR_OK input, a VCC_12V power input that falls below the minimum speciﬁcation, a watchdog timeout, or may be initiated by the module software.

PWR_OK B24 Power OK from main power supply. A high value indicates that the power is good. I 3.3V Set by resistor

SUS_STAT# B18 Indicates imminent suspend operation; used to notify LPC devices. O 3.3VSB PU 10k 3.3VSB

SUS_S3# A15 Indicates system is in Suspend to RAM state. Active-low output. An inverted copy of SUS_S3#

on the carrier board (also known as “PS_ON”) may be used to enable the non-standby power on a typical ATX power supply.

SUS_S4# A18 Indicates system is in Suspend to Disk state. Active low output. O 3.3VSB

SUS_S5# A24 Indicates system is in Soft Off state. O 3.3VSB

WAKE0# B66 PCI Express wake up signal. I 3.3VSB PU 1k 3.3VSB

WAKE1# B67 General purpose wake up signal. May be used to implement wake-up on PS/2 keyboard or

mouse activity.

BATLOW# A27 Battery low input. This signal may be driven low by external circuitry to signal that the system

battery is low, or may be used to signal some other external power-management event.

THRM# B35 Input from off-module temp sensor indicating an over-temp situation. I 3.3V PU 10k 3.3V

THERMTRIP# A35 Active low output indicating that the CPU has entered thermal shutdown. O 3.3V PU 10k 3.3V

SMB_CK B13 System Management Bus bidirectional clock line. I/O 3.3VSB PU 2k2 3.3VSB

SMB_DAT# B14 System Management Bus bidirectional data line. I/O OD

SMB_ALERT# B15 System Management Bus Alert – active low input can be used to generate an SMI# (System

Management Interrupt) or to wake the system.

LID# A103 Lid button. Used by the ACPI operating system for a LID switch. I OD 3.3V PU 10k 3.3VSB

SLEEP B103 Sleep button. Used by the ACPI operating system to bring the system to sleep state or to wake

it up again.

I 3.3VSB PU 10k 3.3VSB

O 3.3V PD 100k

divider to accept

3.3V.

O 3.3VSB

I 3.3VSB PU 10k 3.3VSB

PU 2k2 3.3VSB

3.3VSB

I 3.3VSB PU 10k 3.3VSB

I OD 3.3V PU 10k 3.3VSB

Table 19 General Purpose Serial Interface Signal Descriptions

Page 61

Signal Pin # Description I/O PU/PD Comment

SER0_TX A98 General purpose serial port transmitter O 3.3V Supported on Rev. B.0 and later SER1_TX A101 General purpose serial port transmitter O 3.3V Supported on Rev. B.0 and later SER0_RX A99 General purpose serial port receiver I 3.3V PU 50k 3.3V Supported on Rev. B.0 and later SER1_RX A102 General purpose serial port receiver I 3.3V PU 50k 3.3V Supported on Rev. B.0 and later

Table 20 Power and GND Signal Descriptions

Signal Pin # Description I/O PU/PD Comment

VCC_12V A104-A109

B104-B109

VCC_5V_SBY B84-B87 Standby power input: +5.0V nominal. If VCC5_SBY is used, all available VCC_5V_SBY

VCC_RTC A47 Real-time clock circuit-power input. Nominally +3.0V. P

GND A1, A11, A21, A31,

A41, A51, A57, A60, A66, A70, A80, A90, A100, A110, B1, B11, B21, B31, B41, B51, B60, B70, B80, B90, B100, B110

Primary power input: +12V nominal. All available VCC_12V pins on the connector(s) shall be used.

pins on the connector(s) shall be used. Only used for standby and suspend functions. May be left unconnected if these functions are not used in the system design.

Ground - DC power and signal and AC signal return path. All available GND connector pins shall be used and tied to Carrier Board GND plane.

Page 62

9.2 A-B Connector Pinout

Table 21 Connector A-B Pinout

Pin Row A Pin Row B Pin Row A Pin Row B

A1 GND (FIXED) B1 GND (FIXED) A56 PCIE_TX4- B56 PCIE_RX4-

A2 GBE0_MDI3- B2 GBE0_ACT# A57 GND B57 GPO2

A3 GBE0_MDI3+ B3 LPC_FRAME# A58 PCIE_TX3+ B58 PCIE_RX3+

A4 GBE0_LINK100# B4 LPC_AD0 A59 PCIE_TX3- B59 PCIE_RX3-

A5 GBE0_LINK1000# B5 LPC_AD1 A60 GND (FIXED) B60 GND (FIXED)

A6 GBE0_MDI2- B6 LPC_AD2 A61 PCIE_TX2+ B61 PCIE_RX2+

A7 GBE0_MDI2+ B7 LPC_AD3 A62 PCIE_TX2- B62 PCIE_RX2-

A8 GBE0_LINK# B8 LPC_DRQ0# A63 GPI1 B63 GPO3

A9 GBE0_MDI1- B9 LPC_DRQ1# A64 PCIE_TX1+ B64 PCIE_RX1+

A10 GBE0_MDI1+ B10 LPC_CLK A65 PCIE_TX1- B65 PCIE_RX1-

A11 GND (FIXED) B11 GND (FIXED) A66 GND B66 WAKE0#

A12 GBE0_MDI0- B12 PWRBTN# A67 GPI2 B67 WAKE1#

A13 GBE0_MDI0+ B13 SMB_CK A68 PCIE_TX0+ B68 PCIE_RX0+

A14 GBE0_CTREF (*) B14 SMB_DAT A69 PCIE_TX0- B69 PCIE_RX0-

A15 SUS_S3# B15 SMB_ALERT# A70 GND (FIXED) B70 GND (FIXED)

A16 SATA0_TX+ B16 SATA1_TX+ A71 eDP_TX2+/LVDS_A0+

A17 SATA0_TX- B17 SATA1_TX- A72 eDP_TX2-/LVDS_A0- B72 LVDS_B0-

A18 SUS_S4# B18 SUS_STAT# A73 eDP_TX1+/LVDS_A1+ B73 LVDS_B1+

A19 SATA0_RX+ B19 SATA1_RX+ A74 eDP_TX1-/LVDS_A1- B74 LVDS_B1-

A20 SATA0_RX- B20 SATA1_RX- A75 eDP_TX0+/LVDS_A2+ B75 LVDS_B2+

A21 GND (FIXED) B21 GND (FIXED) A76 eDP_TX0-/LVDS_A2- B76 LVDS_B2-

A22 SATA2_TX+ B22 SATA3_TX+ A77 eDP/LVDS_VDD_EN B77 LVDS_B3+

A23 SATA2_TX- B23 SATA3_TX- A78 LVDS_A3+ B78 LVDS_B3-

A24 SUS_S5# B24 PWR_OK A79 LVDS_A3- B79 eDP/LVDS_BKLT_EN

A25 SATA2_RX+ B25 SATA3_RX+ A80 GND (FIXED) B80 GND (FIXED)

A26 SATA2_RX- B26 SATA3_RX- A81 eDP_TX3+/LVDS_A_CK+ B81 LVDS_B_CK+

A27 BATLOW# B27 WDT A82 eDP_TX3-/LVDS_A_CK- B82 LVDS_B_CK-

A28 (S)ATA_ACT# B28 AC/HDA_SDIN2 A83 eDP_AUX+/LVDS_I2C_CK B83 eDP/LVDS_BKLT_CTRL

A29 AC/HDA_SYNC B29 AC/HDA_SDIN1 A84 eDP_AUX-/LVDS_I2C_DAT B84 VCC_5V_SBY

A30 AC/HDA_RST# B30 AC/HDA_SDIN0 A85 GPI3 B85 VCC_5V_SBY

B71 LVDS_B0+

Page 63

Pin Row A Pin Row B Pin Row A Pin Row B

A31 GND (FIXED) B31 GND (FIXED) A86 RSVD B86 VCC_5V_SBY

A32 AC/HDA_BITCLK B32 SPKR A87 eDP_HPD B87 VCC_5V_SBY

A33 AC/HDA_SDOUT B33 I2C_CK A88 PCIE0_CK_REF+ B88 BIOS_DIS1#

A34 BIOS_DIS0# B34 I2C_DAT A89 PCIE0_CK_REF- B89 VGA_RED

A35 THRMTRIP# B35 THRM# A90 GND (FIXED) B90 GND (FIXED)

A36 USB6- B36 USB7- A91 SPI_POWER B91 VGA_GRN

A37 USB6+ B37 USB7+ A92 SPI_MISO B92 VGA_BLU

A38 USB_6_7_OC# B38 USB_4_5_OC# A93 GPO0 B93 VGA_HSYNC

A39 USB4- B39 USB5- A94 SPI_CLK B94 VGA_VSYNC

A40 USB4+ B40 USB5+ A95 SPI_MOSI B95 VGA_I2C_CK

A41 GND (FIXED) B41 GND (FIXED) A96 TPM_PP B96 VGA_I2C_DAT

A42 USB2- B42 USB3- A97 TYPE10# B97 SPI_CS#

A43 USB2+ B43 USB3+ A98 SER0_TX B98 RSVD

A44 USB_2_3_OC# B44 USB_0_1_OC# A99 SER0_RX B99 RSVD

A45 USB0- B45 USB1- A100 GND (FIXED) B100 GND (FIXED)

A46 USB0+ B46 USB1+ A101 SER1_TX

A47 VCC_RTC B47 EXCD1_PERST# A102 SER1_RX B102 FAN_TACHIN

A48 EXCD0_PERST# B48 EXCD1_CPPE# A103 LID# B103 SLEEP#

A49 EXCD0_CPPE# B49 SYS_RESET# A104 VCC_12V B104 VCC_12V

A50 LPC_SERIRQ B50 CB_RESET# A105 VCC_12V B105 VCC_12V

A51 GND (FIXED) B51 GND (FIXED) A106 VCC_12V B106 VCC_12V

A52 PCIE_TX5+ B52 PCIE_RX5+ A107 VCC_12V B107 VCC_12V

A53 PCIE_TX5- B53 PCIE_RX5- A108 VCC_12V B108 VCC_12V

A54 GPI0 B54 GPO1 A109 VCC_12V B109 VCC_12V

A55 PCIE_TX4+ B55 PCIE_RX4+ A110 GND (FIXED) B110 GND (FIXED)

B101 FAN_PWMOUT

Note

The signals marked with asterisk symbol (*) are not supported on the conga TS87.

Page 64

9.3 C-D Connector Signal Descriptions

Table 22 PCI Express Signal Descriptions (general purpose)

Signal Pin # Description I/O PU/PD Comment

PCIE_RX6+ PCIE_RX6-

PCIE_TX6+ PCIE_TX6-

PCIE_RX7+ PCIE_RX7-

PCIE_TX7+ PCIE_TX7-

Table 23 USB 3.0 Signal Descriptions

Signal Pin # Description I/O PU/PD Comment

USB_SSRX0+ C4 Additional receive signal differential pairs for the Superspeed USB data path I

USB_SSRX0- C3 I

USB_SSTX0+ D4 Additional transmit signal differential pairs for the Superspeed USB data

USB_SSTX0- D3 O

C19 C20

D19 D20

C22 C23

D22 D23

PCI Express channel 6, Receive Input differential pair. I PCIE Supports PCI Express Base Speciﬁcation, Revision 2.0

PCI Express channel 6, Transmit Output differential pair. O PCIE Supports PCI Express Base Speciﬁcation, Revision 2.0

PCI Express channel 7, Receive Input differential pair. I PCIE Not supported

PCI Express channel 7, Transmit Output differential pair. O PCIE Not supported

path

USB_SSRX1+ C7 Additional receive signal differential pairs for the Superspeed USB data path I

USB_SSRX1- C6 I

USB_SSTX1+ D7 Additional transmit signal differential pairs for the Superspeed USB data

USB_SSTX1- D6 O

USB_SSRX2+ C10 Additional receive signal differential pairs for the Superspeed USB data path I

USB_SSRX2- C9 I

USB_SSTX2+ D10 Additional transmit signal differential pairs for the Superspeed USB data

USB_SSTX2- D9 O

USB_SSRX3+ C13 Additional receive signal differential pairs for the Superspeed USB data path I

USB_SSRX3- C12 I

USB_SSTX3+ D13 Additional transmit signal differential pairs for the Superspeed USB data

USB_SSTX3- D12 O

path

Table 24 PCI Express Signal Descriptions (x16 Graphics)

Page 65

Signal Pin # Description I/O PU/PD Comment

PEG_RX0+ PEG_RX0PEG_RX1+ PEG_RX1PEG_RX2+ PEG_RX2PEG_RX3+ PEG_RX3PEG_RX4+ PEG_RX4PEG_RX5+ PEG_RX5PEG_RX6+ PEG_RX6PEG_RX7+ PEG_RX7PEG_RX8+ PEG_RX8PEG_RX9+ PEG_RX9PEG_RX10+ PEG_RX10PEG_RX11+ PEG_RX11PEG_RX12+ PEG_RX12PEG_RX13+ PEG_RX13PEG_RX14+ PEG_RX14PEG_RX15+ PEG_RX15-

C52 C53 C55 C56 C58 C59 C61 C62 C65 C66 C68 C69 C71 C72 C74 C75 C78 C79 C81 C82 C85 C86 C88 C89 C91 C92 C94 C95 C98 C99 C101 C102

PCI Express Graphics Receive Input differential pairs.

Note: Can also be used as PCI Express Receive Input differential pairs 16 through 31 known as PCIE_RX[16-31] + and -.

I PCIE

Page 66

Signal Pin # Description I/O PU/PD Comment

PEG_TX0+ PEG_TX0PEG_TX1+ PEG_TX1PEG_TX2+ PEG_TX2PEG_TX3+ PEG_TX3PEG_TX4+ PEG_TX4PEG_TX5+ PEG_TX5PEG_TX6+ PEG_TX6PEG_TX7+ PEG_TX7PEG_TX8+ PEG_TX8PEG_TX9+ PEG_TX9PEG_TX10+ PEG_TX10PEG_TX11+ PEG_TX11PEG_TX12+ PEG_TX12PEG_TX13+ PEG_TX13PEG_TX14+ PEG_TX14PEG_TX15+ PEG_TX15-

PEG_LANE_RV# D54 PCI Express Graphics lane reversal input strap. Pull low on the carrier board to reverse lane

D52 D53 D55 D56 D58 D59 D61 D62 D65 D66 D68 D69 D71 D72 D74 D75 D78 D79 D81 D82 D85 D86 D88 D89 D91 D92 D94 D95 D98 D99 D101 D102

PCI Express Graphics Transmit Output differential pairs.

Note: Can also be used as PCI Express Transmit Output differential pairs 16 through 31 known as PCIE_TX[16-31] + and -.

order.

O PCIE

I PU 10k

3.3V

PEG_LAN_RV# is a boot strap signal (see note below)

Note

Dedicated PEG Channels are provided in Type 6. SDVO is no longer multiplexed on the PEG port.

Some signals have special functionality during the reset process. They may bootstrap some basic important functions of the module. For more information refer to section 9.5 of this user’s guide.

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Table 25 DDI Signal Description

Signal Pin # Description I/O PU/PD Comment

DDI1_PAIR0+ DDI1_PAIR0-

DDI1_PAIR1+ DDI1_PAIR1-

DDI1_PAIR2+ DDI1_PAIR2-

DDI1_PAIR3+ DDI1_PAIR3-

DDI1_PAIR4+ DDI1_PAIR4-

DDI1_PAIR5+ DDI1_PAIR5-

DDI1_PAIR6+ DDI1_PAIR6-

DDI1_HPD C24 Multiplexed with DP1_HPD and HDMI1_HPD. I 3.3V PD 1M

DDI1_CTRLCLK_AUX+ D15 Multiplexed with DP1_AUX+ and HMDI1_CTRLCLK.

DDI1_CTRLDATA_AUX- D16 Multiplexed with DP1_AUX- and HDMI1_CTRLDATA.

DDI1_DDC_AUX_SEL D34 Selects the function of DDI1_CTRLCLK_AUX+ and DDI1_CTRLDATA_AUX-

DDI2_PAIR0+ DDI2_PAIR0-

DDI2_PAIR1+ DDI2_PAIR1-

DDI2_PAIR2+ DDI2_PAIR2-

DDI2_PAIR3+ DDI2_PAIR3-

DDI2_HPD D44 Multiplexed with DP2_HPD and HDMI2_HPD. I 3.3V PD 1M

D26

Multiplexed with DP1_LANE0+ and TMDS1_DATA2+.

D27

Multiplexed with DP1_LANE0- and TMDS1_DATA2-.

D29

Multiplexed with DP1_LANE1+ and TMDS1_DATA1+.

D30

Multiplexed with DP1_LANE1- and TMDS1_DATA1-.

D32

Multiplexed with DP1_LANE2+ and TMDS1_DATA0+.

D33

Multiplexed with DP1_LANE2- and TMDS1_DATA0-.

D36

Multiplexed with DP1_LANE3+ and TMDS1_CLK+.

D37

Multiplexed with DP1_LANE3- and TMDS1_CLK-.

C25

Multiplexed with SDVO1_INT+.

C26

Multiplexed with SDVO1_INT-.

C29

Multiplexed with SDVO1_TVCLKIN+.

C30

Multiplexed with SDVO1_TVCLKIN-.

C15

Multiplexed with SDVO1_FLDSTALL+.

C16

Multiplexed with SDVO1_FLDSTALL-.

DP AUX+ function if DDI1_DDC_AUX_SEL is no connect. HDMI/DVI I2C CTRLCLK if DDI1_DDC_AUX_SEL is pulled high

DP AUX- function if DDI1_DDC_AUX_SEL is no connect. HDMI/DVI I2C CTRLDATA if DDI1_DDC_AUX_SEL is pulled high

. This pin shall have a IM pull-down to logic ground on the module. If this input is ﬂoating, the AUX pair is used for the DP AUX+/- signals. If pulledhigh, the AUX pair contains the CTRLCLK and CTRLDATA signals.

D39

Multiplexed with DP2_LANE0+ and TMDS2_DATA2+.

D40

Multiplexed with DP2_LANE0- and TMDS2_DATA2-.

D42

Multiplexed with DP2_LANE1+ and TMDS2_DATA1+.

D43

Multiplexed with DP2_LANE1- and TMDS2_DATA1-.

D46

Multiplexed with DP2_LANE2+ and TMDS2_DATA0+.

D47

Multiplexed with DP2_LANE2- and TMDS2_DATA0-.

D49

Multiplexed with DP2_LANE3+ and TMDS2_CLK+.

D50

Multiplexed with DP2_LANE3- and TMDS2_CLK-.

O PCIE

PD100k I/O PCIE I/O OD

3.3V

PU I/O PCIE I/O OD

3.3V

I 3.3V PD 1M

O PCIE

100k

3.3V

Not supported

DDI1_CTRLDATA_AUX- is a boot strap signal (see not below). DDI enable strap already populated.

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Signal Pin # Description I/O PU/PD Comment

DDI2_CTRLCLK_AUX+ C32 Multiplexed with DP2_AUX+ and HDMI2_CTRLCLK.

DP AUX+ function if DDI2_DDC_AUX_SEL is no connect. HDMI/DVI I2C CTRLCLK if DDI2_DDC_AUX_SEL is pulled high

DDI2_CTRLDATA_AUX- C33 Multiplexed with DP2_AUX- and HDMI2_CTRLDATA.

DP AUX- function if DDI2_DDC_AUX_SEL is no connect. HDMI/DVI I2C CTRLDATA if DDI2_DDC_AUX_SEL is pulled high.

DDI2_DDC_AUX_SEL C34 Selects the function of DDI2_CTRLCLK_AUX+ and DDI2_CTRLDATA_AUX-

DDI3_PAIR0+ DDI3_PAIR0-

DDI3_PAIR1+ DDI3_PAIR1-

DDI3_PAIR2+ DDI3_PAIR2-

DDI3_PAIR3+ DDI3_PAIR3-

DDI3_HPD C44 Multiplexed with DP3_HPD and HDMI3_HPD. I 3.3V PD 1M

DDI3_CTRLCLK_AUX+ C36 Multiplexed with DP3_AUX+ and HDMI3_CTRLCLK.

DDI3_CTRLDATA_AUX- C37 Multiplexed with DP3_AUX- and HDMI3_CTRLDATA.

DDI3_DDC_AUX_SEL C38 Selects the function of DDI3_CTRLCLK_AUX+ and DDI3_CTRLDATA_AUX-

C39

Multiplexed with DP3_LANE0+ and TMDS3_DATA2+.

C40

Multiplexed with DP3_LANE0- and TMDS3_DATA2-.

C42

Multiplexed with DP3_LANE1+ and TMDS3_DATA1+.

C43

Multiplexed with DP3_LANE1- and TMDS3_DATA1-.

C46

Multiplexed with DP3_LANE2+ and TMDS3_DATA0+.

C47

Multiplexed with DP3_LANE2- and TMDS3_DATA0-.

C49

Multiplexed with DP3_LANE3+ and TMDS3_CLK+.

C50

Multiplexed with DP3_LANE3- and TMDS3_CLK-.

DP AUX+ function if DDI3_DDC_AUX_SEL is no connect. HDMI/DVI I2C CTRLCLK if DDI3_DDC_AUX_SEL is pulled high

DP AUX- function if DDI3_DDC_AUX_SEL is no connect. HDMI/DVI I2C CTRLDATA if DDI3_DDC_AUX_SEL is pulled high.

I/O PCIE I/O OD

3.3V

I/O PCIE I/O OD

3.3V

I 3.3V

O PCIE

I/O PCIE I/O OD

3.3V

I/O PCIE I/O OD

3.3V

I 3.3V PD 1M

100k

3.3V

100k

DDI2_CTRLCLK_AUX- is a boot strap signal (see note below). DDI enable strap already populated.

DDI3_CTRLDATA_AUX- is a boot strap signal (see note below). DDI enable strap already populated.

Note

Some signals have special functionality during the reset process. They may bootstrap some basic important functions of the module. For more information refer to section 9.5 of this user’s guide.

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The Digital Display Interface (DDI) signals are multiplexed with HDMI and DisplayPort (DP). The signals for these interfaces are routed to the DDI interface of the COM Express connector. Refer to the HDMI and DisplayPort signal description tables in this section for information about the signals routed to the DDI interface of the COM Express connector.

Table 26 HDMI Signal Descriptions

Signal Pin # Description I/O PU/PD Comment

TMDS1_CLK + TMDS1_CLK -

TMDS1_DATA0+ TMDS1_DATA0-

TMDS1_DATA1+ TMDS1_DATA1-

TMDS1_DATA2+ TMDS1_DATA2-

HDMI1_HPD C24 HDMI/DVI Hot-plug detect.

HDMI1_CTRLCLK D15 HDMI/DVI I

HDMI1_CTRLDATA D16 HDMI/DVI I

TMDS2_CLK + TMDS2_CLK -

TMDS2_DATA0+ TMDS2_DATA0-

TMDS2_DATA1+ TMDS2_DATA1-

TMDS2_DATA2+ TMDS2_DATA2-

HDMI2_HPD D44 HDMI/DVI Hot-plug detect.

HDMI2_CTRLCLK C32 HDMI/DVI I

HDM12_CTRLDATA C33 HDMI/DVI I

TMDS3_CLK + TMDS3_CLK -

TMDS3_DATA0+ TMDS3_DATA0-

D36 D37

D32 D33

D29 D30

D26 D27

D49 D50

D46 D47

D42 D43

D39 D40

C49 C50

C46 C47

HDMI/DVI TMDS Clock output differential pair. Multiplexed with DDI1_PAIR3+ and DDI1_PAIR3-.

HDMI/DVI TMDS differential pair. Multiplexed with DDI1_PAIR2+ and DDI1_PAIR2-.

HDMI/DVI TMDS differential pair. Multiplexed with DDI1_PAIR1+ and DDI1_PAIR1-..

HDMI/DVI TMDS differential pair. Multiplexed with DDI1_PAIR0+ and DDI1_PAIR0-.

Multiplexed with DDI1_HPD.

C Control Clock

Multiplexed with DDI1_CTRLCLK_AUX+

C Control Data

Multiplexed with DDI1_CTRLDATA_AUX-

HDMI/DVI TMDS Clock output differential pair.. Multiplexed with DDI2_PAIR3+ and DDI2_PAIR3-.

HDMI/DVI TMDS differential pair. Multiplexed with DDI2_PAIR2+ and DDI2_PAIR2-.

HDMI/DVI TMDS differential pair. Multiplexed with DDI2_PAIR1+ and DDI2_PAIR1-.

HDMI/DVI TMDS differential pair. Multiplexed with DDI2_PAIR0+ and DDI2_PAIR0-..

Multiplexed with DDI2_HPD

C Control Clock

Multiplexed with DDI2_CTRLCLK_AUX+

C Control Data

Multiplexed with DDI2_CTRLDATA_AUX-

HDMI/DVI TMDS Clock output differential pair.. Multiplexed with DDI3_PAIR3+ and DDI3_PAIR3-.

HDMI/DVI TMDS differential pair. Multiplexed with DDI3_PAIR2+ and DDI3_PAIR2-.

O PCIE

I PCIE PD 1M

I/O OD

PD 100k

3.3V

I/O OD

3.3V

PU 100k

3.3V

O PCIE

I PCIE PD 1M

I/O OD

PD 100k

3.3V

I/O OD

3.3V

PU 100k

3.3V

O PCIE

HDMI1_CTRLDATA is a boot strap signal (see note below). HDMI enable strap already populated

HDMI2_CTRLDATA is a boot strap signal (see note below). HDMI enable strap is already populated.

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Signal Pin # Description I/O PU/PD Comment

TMDS3_DATA1+ TMDS3_DATA1-

TMDS3_DATA2+ TMDS3_DATA2-

HDMI3_HPD C44 HDMI/DVI Hot-plug detect.

HDMI3_CTRLCLK C36 HDMI/DVI I

HDMI3_CTRLDATA C37 HDMI/DVI I

C42 C43

C39 C40

HDMI/DVI TMDS differential pair. Multiplexed with DDI3_PAIR1+ and DDI3_PAIR1-..

HDMI/DVI TMDS differential pair. Multiplexed with DDI3_PAIR0+ and DDI3_PAIR0-.

Multiplexed with DDI3_HPD.

C Control Clock

Multiplexed with DDI3_CTRLCLK_AUX+

C Control Data

Multiplexed with DDI3_CTRLDATA_AUX-

O PCIE

I PCIE PD 1M

I/O OD

3.3V

I/O OD

3.3V

PD 100k

PU 100k

3.3V

HDMI3_CTRLDATA is a boot strap signal (see note below). HDMI enable strap is already populated.

Note

Some signals have special functionality during the reset process. They may bootstrap some basic important functions of the module. For more information refer to section 9.5 of this user’s guide.

Table 27 DisplayPort (DP) Signal Descriptions

Signal Pin # Description I/O PU/PD Comment

DP1_LANE3+ DP1_LANE3-

DP1_LANE2+ DP1_LANE2-

DP1_LANE1+ DP1_LANE1-

DP1_LANE0+ DP1_LANE0-

DP1_HPD C24 Detection of Hot Plug / Unplug and notiﬁcation of the link layer.

DP1_AUX+ D15 Half-duplex bi-directional AUX channel for services such as link

DP1_AUX- D16 Half-duplex bi-directional AUX channel for services such as link

D36 D37

D32 D33

D29 D30

D26 D27

Uni-directional main link for the transport of isochronous streams and secondary data. Multiplexed with DDI1_PAIR3+ and DDI1_PAIR3-.

Uni-directional main link for the transport of isochronous streams and secondary data. Multiplexed with DDI1_PAIR2+ and DDI1_PAIR2-.

Uni-directional main link for the transport of isochronous streams and secondary data. Multiplexed with DDI1_PAIR1+ and DDI1_PAIR1-.

Uni-directional main link for the transport of isochronous streams and secondary data. Multiplexed with DDI1_PAIR0+ and DDI1_PAIR0-.

Multiplexed with DDI1_HPD.

conﬁguration or maintenance and EDID access.

O PCIE

I 3.3V PD 1M

I/O PCIE

PD 100k

PU 100k

3.3V

DP1_AUX- is a boot strap signal (see note below). DP enable strap is already populated.

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Signal Pin # Description I/O PU/PD Comment

DP2_LANE3+ DP2_LANE3-

DP2_LANE2+ DP2_LANE2-

DP2_LANE1+ DP2_LANE1-

DP2_LANE0+ DP2_LANE0-

DP2_HPD D44 Detection of Hot Plug / Unplug and notiﬁcation of the link layer.

DP2_AUX+ C32 Half-duplex bi-directional AUX channel for services such as link

DP2_AUX- C33 Half-duplex bi-directional AUX channel for services such as link

DP3_LANE3+ DP3_LANE3-

DP3_LANE2+ DP3_LANE2-

DP3_LANE1+ DP3_LANE1-

DP3_LANE0+ DP3_LANE0-

DP3_HPD C44 Detection of Hot Plug / Unplug and notiﬁcation of the link layer.

DP3_AUX+ C36 Half-duplex bi-directional AUX channel for services such as link

DP3_AUX- C37 Half-duplex bi-directional AUX channel for services such as link

D49 D50

D46 D47

D42 D43

D39 D40

C49 C50

C46 C47

C42 C43

C39 C40

Uni-directional main link for the transport of isochronous streams and secondary data. Multiplexed with DDI2_PAIR3+ and DDI2_PAIR3-

Uni-directional main link for the transport of isochronous streams and secondary data. Multiplexed with DDI2_PAIR2+ and DDI2_PAIR2-

Uni-directional main link for the transport of isochronous streams and secondary data. Multiplexed with DDI2_PAIR1+ and DDI2_PAIR1-

Uni-directional main link for the transport of isochronous streams and secondary data. Multiplexed with DDI2_PAIR0+ and DDI1_PAIR0-

Multiplexed with DDI2_HPD.

conﬁguration or maintenance and EDID access.

Uni-directional main link for the transport of isochronous streams and secondary data. Multiplexed with DDI3_PAIR3+ and DDI3_PAIR3-.

Uni-directional main link for the transport of isochronous streams and secondary data. Multiplexed with DDI3_PAIR2+ and DDI3_PAIR2-.

Uni-directional main link for the transport of isochronous streams and secondary data. Multiplexed with DDI3_PAIR1+ and DDI3_PAIR1-.

Uni-directional main link for the transport of isochronous streams and secondary data. Multiplexed with DDI3_PAIR0+ and DDI3_PAIR0-.

Multiplexed with DDI3_HPD.

conﬁguration or maintenance and EDID access.

O PCIE

I 3.3V PD 1M

I/O PCIE

O PCIE

I 3.3V PD 1M

I/O PCIE

PD 100k

PU 100k

3.3V

PD 100k

PU 100k

3.3V

DP2_AUX- is a boot strap signal (see note below). DP enable strap already populated.

DP3_AUX- is a boot strap signal (see note below). DP enable strap already populated.

Note

Some signals have special functionality during the reset process. They may bootstrap some basic important functions of the module. For more information refer to section 9.5 of this user’s guide.

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Table 28 Module Type Deﬁnition Signal Description

Signal Pin # Description I/O Comment

TYPE0# TYPE1# TYPE2#

TYPE10# A97 Dual use pin. Indicates to the carrier board that a Type 10 module is installed. Indicates to the carrier that a Rev.

C54 C57 D57

The TYPE pins indicate to the Carrier Board the Pin-out Type that is implemented on the module. The pins are tied on the module to either ground (GND) or are no-connects (NC). For Pinout Type 1, these pins are don’t care (X).

TYPE2# TYPE1# TYPE0#

X NC NC NC NC GND

The Carrier Board should implement combinatorial logic that monitors the module TYPE pins and keeps power off (e.g deactivates the ATX_ON signal for an ATX power supply) if an incompatible module pin-out type is detected. The Carrier Board logic may also implement a fault indicator such as an LED.

1.0/2.0 module is installed.

TYPE10#

X NC NC GND GND NC

X NC GND NC GND NC

Pinout Type 1 Pinout Type 2 Pinout Type 3 (no IDE) Pinout Type 4 (no PCI) Pinout Type 5 (no IDE, no PCI) Pinout Type 6 (no IDE, no PCI)

PDS TYPE[0:2]# signals are

available on all modules following the Type 2-6 Pinout standard. The conga-TS87 is based on the COM Express Type 6 pinout therefore the pins 0 and 1 are not connected and pin 2 is connected to GND.

PDS Not connected to indicate

“Pinout R2.0”.

NC PD 12V

This pin is reclaimed from VCC_12V pool. In R1.0 modules this pin will connect to other VCC_12V pins. In R2.0 this pin is deﬁned as a no-connect for Types 1-6. A carrier can detect a R1.0 module by the presence of 12V on this pin. R2.0 module Types 1-6 will no-connect this pin. Type 10 modules shall pull this pin to ground through a 4.7k resistor.

Pinout R2.0 Pinout Type 10 pull down to ground with 4.7k resistor Pinout R1.0

Table 29 Power and GND Signal Descriptions

Signal Pin # Description I/O PU/PD Comment

VCC_12V C104-C109

D104-D109

GND C1, C2, C5, C8, C11, C14, C21, C31,

C41, C51, C60, C70,C73, C76, C80, C84, C87, C90, C93, C96, C100, C103, C110, D1, D2, D5, D8, D11, D14, D21, D31, D41, D51, D60, D67, D70, D73, D76, D80, D84, D87, D90, D93, D96, D100, D103, D110

Primary power input: +12V nominal. All available VCC_12V pins on the connector(s) shall be used.

Ground - DC power and signal and AC signal return path. All available GND connector pins shall be used and tied to carrier board GND plane.

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9.4 C-D Connector Pinout

Table 30 Connector C-D Pinout

Pin Row C Pin Row D Pin Row C Pin Row D

C1 GND (FIXED) D1 GND (FIXED) C56 PEG_RX1- D56 PEG_TX1-

C2 GND D2 GND C57 TYPE1# D57 TYPE2#

C3 USB_SSRX0- D3 USB_SSTX0- C58 PEG_RX2+ D58 PEG_TX2+

C4 USB_SSRX0+ D4 USB_SSTX0+ C59 PEG_RX2- D59 PEG_TX2-

C5 GND D5 GND C60 GND (FIXED) D60 GND (FIXED)

C6 USB_SSRX1- D6 USB_SSTX1- C61 PEG_RX3+ D61 PEG_TX3+

C7 USB_SSRX1+ D7 USB_SSTX1+ C62 PEG_RX3- D62 PEG_TX3-

C8 GND D8 GND C63 RSVD D63 RSVD

C9 USB_SSRX2- D9 USB_SSTX2- C64 RSVD D64 RSVD

C10 USB_SSRX2+ D10 USB_SSTX2+ C65 PEG_RX4+ D65 PEG_TX4+

C11 GND (FIXED) D11 GND (FIXED) C66 PEG_RX4- D66 PEG_TX4-

C12 USB_SSRX3- D12 USB_SSTX3- C67 RSVD D67 GND

C13 USB_SSRX3+ D13 USB_SSTX3+ C68 PEG_RX5+ D68 PEG_TX5+

C14 GND D14 GND C69 PEG_RX5- D69 PEG_TX5-

C15 DDI1_PAIR6+ D15 DDI1_CTRLCLK_AUX+ C70 GND (FIXED) D70 GND (FIXED)

C16 DDI1_PAIR6- D16 DDI1_CTRLDATA_AUX- C71 PEG_RX6+

C17 RSVD D17 RSVD C72 PEG_RX6- D72 PEG_TX6-

C18 RSVD D18 RSVD C73 GND D73 GND

C19 PCIE_RX6+ D19 PCIE_TX6+ C74 PEG_RX7+ D74 PEG_TX7+

C20 PCIE_RX6- D20 PCIE_TX6- C75 PEG_RX7- D75 PEG_TX7-

C21 GND (FIXED) D21 GND (FIXED) C76 GND D76 GND

C22 PCIE_RX7+ (*) D22 PCIE_TX7+ (*) C77 RSVD D77 RSVD

C23 PCIE_RX7- (*) D23 PCIE_TX7- (*) C78 PEG_RX8+ D78 PEG_TX8+

C24 DDI1_HPD D24 RSVD C79 PEG_RX8- D79 PEG_TX8-

C25 DDI1_PAIR4+ D25 RSVD C80 GND (FIXED) D80 GND (FIXED)

C26 DDI1_PAIR4- D26 DDI1_PAIR0+ C81 PEG_RX9+ D81 PEG_TX9+

C27 RSVD D27 DDI1_PAIR0- C82 PEG_RX9- D82 PEG_TX9-

C28 RSVD D28 RSVD C83 RSVD D83 RSVD

C29 DDI1_PAIR5+ D29 DDI1_PAIR1+ C84 GND D84 GND

C30 DDI1_PAIR5- D30 DDI1_PAIR1- C85 PEG_RX10+ D85 PEG_TX10+

D71 PEG_TX6+

Page 74

Pin Row C Pin Row D Pin Row C Pin Row D

C31 GND (FIXED) D31 GND (FIXED) C86 PEG_RX10- D86 PEG_TX10-

C32 DDI2_CTRLCLK_AUX+ D32 DDI1_PAIR2+ C87 GND D87 GND

C33 DDI2_CTRLDATA_AUX- D33 DDI1_PAIR2- C88 PEG_RX11+ D88 PEG_TX11+

C34 DDI2_DDC_AUX_SEL D34 DDI1_DDC_AUX_SEL C89 PEG_RX11- D89 PEG_TX11-

C35 RSVD D35 RSVD C90 GND (FIXED) D90 GND (FIXED)

C36 DDI3_CTRLCLK_AUX+ D36 DDI1_PAIR3+ C91 PEG_RX12+ D91 PEG_TX12+

C37 DDI3_CTRLDATA_AUX- D37 DDI1_PAIR3- C92 PEG_RX12- D92 PEG_TX12-

C38 DDI3_DDC_AUX_SEL D38 RSVD C93 GND D93 GND

C39 DDI3_PAIR0+ D39 DDI2_PAIR0+ C94 PEG_RX13+ D94 PEG_TX13+

C40 DDI3_PAIR0- D40 DDI2_PAIR0- C95 PEG_RX13- D95 PEG_TX13-

C41 GND (FIXED) D41 GND (FIXED) C96 GND D96 GND

C42 DDI3_PAIR1+ D42 DDI2_PAIR1+ C97 RVSD D97 RSVD

C43 DDI3_PAIR1- D43 DDI2_PAIR1- C98 PEG_RX14+ D98 PEG_TX14+

C44 DDI3_HPD D44 DDI2_HPD C99 PEG_RX14- D99 PEG_TX14-

C45 RSVD D45 RSVD C100 GND (FIXED) D100 GND (FIXED)

C46 DDI3_PAIR2+ D46 DDI2_PAIR2+ C101 PEG_RX15+

C47 DDI3_PAIR2- D47 DDI2_PAIR2- C102 PEG_RX15- D102 PEG_TX15-

C48 RSVD D48 RSVD C103 GND D103 GND

C49 DDI3_PAIR3+ D49 DDI2_PAIR3+ C104 VCC_12V D104 VCC_12V

C50 DDI3_PAIR3- D50 DDI2_PAIR3- C105 VCC_12V D105 VCC_12V

C51 GND (FIXED) D51 GND (FIXED) C106 VCC_12V D106 VCC_12V

C52 PEG_RX0+ D52 PEG_TX0+ C107 VCC_12V D107 VCC_12V

C53 PEG_RX0- D53 PEG_TX0- C108 VCC_12V D108 VCC_12V

C54 TYPE0# D54 PEG_LANE_RV# C109 VCC_12V D109 VCC_12V

C55 PEG_RX1+ D55 PEG_TX1+ C110 GND (FIXED) D110 GND (FIXED)

D101 PEG_TX15+

Note

The signals marked with asterisk symbol (*) are not supported.

Page 75

9.5 Boot Strap Signals

Table 31 Boot Strap Signal Descriptions

Signal Pin # Description of Boot Strap Signal I/O PU/PD Comment

AC/HDA_SYNC A29 High Deﬁnition Audio Sync: This signal is a 48 kHz ﬁxed rate sample sync to

AC/HDA_SDOUT A33 High Deﬁnition Audio Serial Data Out: .This signal is the serial TDM data

SPKR B32 Output for audio enunciator, the “speaker” in PC-AT systems O 3.3V SPKR is a boot strap signal (see

PEG_LAN_RV# D54 PCI Express Graphics lane reversal input strap. Pull low on the carrier board to

DDI1_CTRLDATA_AUXDP1_AUXHDMI_CTRLDATA

DDI2_CTRLDATA_AUXDP2_AUXHDM2_CTRLDATA

DDI3_CTRLDATA_AUXDP3_AUXHDM3_CTRLDATA

D16 Multiplexed with DP1_AUX- and HDMI1_CTRLDATA.

C33 Multiplexed with DP2_AUX- and HDMI2_CTRLDATA.

C37 Multiplexed with DP3_AUX- and HDMI3_CTRLDATA.

the codec(s). It is also used to encode the stream number.

output to the codec(s). This serial output is double-pumped for a bit rate of 48 Mb/s for High Deﬁnition Audio.

reverse lane order

DP AUX- function if DDI1_DDC_AUX_SEL is no connect. HDMI/DVI I2C CTRLDATA if DDI1_DDC_AUX_SEL is pulled high.

DP AUX- function if DDI2_DDC_AUX_SEL is no connect. HDMI/DVI I2C CTRLDATA if DDI2_DDC_AUX_SEL is pulled high.

DP AUX- function if DDI3_DDC_AUX_SEL is no connect. HDMI/DVI I2C CTRLDATA if DDI3_DDC_AUX_SEL is pulled high

O 3.3VSB PU 1K

3.3VSB

O 3.3VSB PU 1K

3.3VSB

I 3.3V PU 10k

3.3V

PU100k I/O PCIE I/O OD

3.3V

I/O PCIE I/O OD

3.3V

I/O PCIE I/O OD

3.3V

PU100k

3.3V

PU100k

3.3V

AC/HDA_SYNC is a boot strap signal (see caution statement below)

AC/HDA_SDOUT is a boot strap signal (see caution statement below)

caution statement below)

PEG_LANE_RV# is a boot strap signal (see caution statement below).

DDI1_CTRLDATA_AUX- is a boot strap signal (see not below).

DDI2_CTRLDATA_AUX- is a boot strap signal (see not below).

DDI3_CTRLDATA_AUX- is a boot strap signal (see not below).

Caution

The signals listed in the table above are used as chipset conﬁguration straps during system reset. In this condition (during reset), they are inputs that are pulled to the correct state by either COM Express™ internally implemented resistors or chipset internally implemented resistors that are located on the module. No external DC loads or external pull-up or pull-down resistors should change the conﬁguration of the signals listed in the above table. External resistors may override the internal strap states and cause the COM Express™ module to malfunction and/ or cause irreparable damage to the module.

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10 System Resources

10.1 I/O Address Assignment

The I/O address assignment of the conga-TS87 module is functionally identical with a standard PC/AT.

Note

The BIOS assigns PCI and PCI Express I/O resources from FFF0h downwards. Non PnP/PCI/PCI Express compliant devices must not consume I/O resources in that area.

10.1.1 LPC Bus

On the conga-TS87, the PCI Express Bus acts as the subtractive decoding agent. All I/O cycles that are not positively decoded are forwarded to the PCI Bus not the LPC Bus. Only speciﬁed I/O ranges are forwarded to the LPC Bus. In the congatec Embedded BIOS, the following I/O address ranges are sent to the LPC Bus:

2Eh – 2Fh 4Eh – 4Fh

60h, 64h

A00 – BFFh

Parts of these ranges are not available if a Super I/O is used on the carrier board. If a Super I/O is not implemented on the carrier board, then this range is available for customer use. If you require additional LPC Bus resources other than those mentioned above, or more information about this subject, contact congatec technical support for assistance.

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10.2 PCI Conﬁguration Space Map

Table 32 PCI Conﬁguration Space Map

Bus Number (hex) Device Number (hex) Function Number (hex) PCI Interrupt Routing Description

00h 00h 00h N.A. Host Bridge

00h 01h 00h Internal PCI Express Graphic Root Port 0

00h 01h 01h Internal PCI Express Graphic Root Port 1

00h 01h 02h Internal PCI Express Graphic Root Port 2

00h 02h 00h Internal VGA Graphics

00h 03h 00h Internal Intel High Deﬁnition Audio controller

00h 14h 00h Internal XHCI Host Controller

00h( Note1) 16h 00h Internal Management Engine (ME) Interface 1

00h( Note1) 16h 01h Internal Intel ME Interface 2

00h( Note1) 16h 02h Internal ME IDE Redirection (IDE-R) Interface

00h( Note1) 16h 03h Internal ME KT (Remote Keyboard and Text)

00h 19h 00h Internal Onboard Gigabit LAN Controller

00h 1Ah 00h Internal EHCI Host Controller 2

00h (Note2) 1Ch 00h Internal PCI Express Root Port 0

00h (Note2) 1Ch 01h Internal PCI Express Root Port 1

00h (Note2) 1Ch 02h Internal PCI Express Root Port 2

00h (Note2) 1Ch 03h Internal PCI Express Root Port 3

00h (Note2) 1Ch 04h Internal PCI Express Root Port 4

00h (Note2) 1Ch 05h Internal PCI Express Root Port 5

00h (Note2) 1Ch 07h Internal PCI Express Root Port 7

00h 1Dh 00h Internal EHCI Host Controller 1

00h 1Fh 00h N.A. PCI to LPC Bridge

00h 1Fh 02h Internal Serial ATA Controller 1

00h 1Fh 03h Internal SMBus Host Controller

00h 1Fh 05h Internal Serial ATA Controller 2

00h 1Fh 06h Internal

01h (Note3) 00h 00h Internal PEG Port 0

02h (Note3) 00h 00h Internal PEG Port 1

03h (Note3) 00h 00h Internal PEG Port 2

04h (Note3) 00h 00h Internal PCI Express Port 0

Thermal Subsystem

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05h (Note3) 00h 00h Internal PCI Express Port 1

06h (Note3) 00h 00h Internal PCI Express Port 2

07h (Note3) 00h 00h Internal PCI Express Port 3

08h (Note3) 00h 00h Internal PCI Express Port 4

09h (Note3) 00h 00h Internal PCI Express Port 5

0Ah (Note3) 00h 00h Internal PCI Express Port 6

Note

1. In the standard conﬁguration, the Intel Management Engine (ME) related devices are partly present or not present at all.

2. The PCI Express Ports are visible only if a device is attached behind them to the PCI Express Slot on the carrier board.

3. The table represents a case when a single function PCI/PCIe device is connected to all possible slots on the carrier board. The given bus numbers will change based on actual hardware conﬁguration.

10.3 PCI Interrupt Routing Map

Table 33 PCI Interrupt Routing Map

PIRQ PCI BUS

INT Line ¹

A INTA 16 x x x x x x x x ² x

B INTB 17 x ³ x

C INTC 18 x x

D INTD 19 x x x

E 20 x

F 21

G 22

H 23 x

APIC Mode IRQ

VGA HDA XHCI EHCI 1EHCI 2SM

Bus + Thermal

LAN SATA1 SATA2 PEG

Root Port 1

PEG Root Port 2

PEG Root Port 3

PEG Port 0

PEG Port 1

PEG Port 2

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PIRQ PCI-EX

Root Port 0

PCI-EX Root Port 1

PCI-EX Root Port 2

PCI-EX Root Port 3

PCI-EX Root Port 4

PCI-EX Root Port 5

PCI-EX Root Port 7

A x x x

B x x x

C x x

D x x x

Note

These interrupt lines are virtual (message based).

Interrupt used by single function PCI Express devices (INTA).

Interrupt used by multifunction PCI Express devices (INTB).

Interrupt used by multifunction PCI Express devices (INTC).

Interrupt used by multifunction PCI Express devices (INTD).

PCI-EX Port 0

PCI-EX Port 1

PCI-EX Port 2

x ² x

x ³ x

PCI-EX Port 3

PCI-EX Port 4

x ² x

x ³ x

PCI-EX Port 5

PCI-EX Port

The COM Express PCIe Port 6 is routed to the PCIe Root Port 7 of the PCH.

10.4 I²C Bus

There are no onboard resources connected to the I²C bus. Address 16h is reserved for congatec Battery Management solutions.

10.5 SM Bus

System Management (SM) bus signals are connected to the Intel® DH82QM87 or DH82HM86 PCH and the SM bus is not intended to be used by off-board non-system management devices. For more information about this subject, contact congatec technical support.

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11 BIOS Setup Description

The following section describes the BIOS setup program. The BIOS setup program can be used to view and change the BIOS settings for the module. Only experienced users should change the default BIOS settings.

11.1 Entering the BIOS Setup Program.

The BIOS setup program can be accessed by pressing the <DEL> or <F2> key during POST. The question is - how to – enter

11.1.1 Boot Selection Popup

Press the <F11> key during POST to access the Boot Selection Popup menu. A selection menu displays immediately after POST, allowing the operator to select either the boot device that should be used or an option to enter the BIOS setup program

11.2 Setup Menu and Navigation

The congatec BIOS setup screen is composed of the menu bar, left frame and right frame. The menu bar is shown below:

Main Advanced Chipset Boot Security Save & Exit

The left frame displays all the options that can be conﬁgured in the selected menu. Grayed-out options cannot be conﬁgured. Only the blue options can be conﬁgured. When an option is selected, it is highlighted in white.

Note

Entries in the option column that are displayed in bold indicate BIOS default values.

The right frame displays the key legend. Above the key legend is an area reserved for text messages. These text messages explain the options and the possible impacts when changing the selected option in the left frame.

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The setup program uses a key-based navigation system. Most of the keys can be used at any time while in setup. The table below explains the supported keys:

Key Description

← → Left/Right Select a setup menu (e.g. Main, Boot, Exit).

↑ ↓ Up/Down Select a setup item or sub menu.

+ - Plus/Minus Change the ﬁeld value of a particular setup item.

Tab Select setup ﬁelds (e.g. in date and time).

F1 Display General Help screen.

F2 Load previous settings.

F9 Load optimal default settings.

F10 Save changes and exit setup.

ESC Discard changes and exit setup.

ENTER Display options of a particular setup item or enter submenu.

11.3 Main Setup Screen

When you ﬁrst enter the BIOS setup, you will enter the main setup screen. The main setup screen reports BIOS, processor, memory and board information and is for conﬁguring the system date and time. You can always return to the main setup screen by selecting the ‘Main’ tab.

The Main screen reports BIOS, processor, memory and board information and is for conﬁguring the system date and time.

Feature Options Description

Main BIOS Version No option Displays the main BIOS version.

OEM BIOS Version No option Displays the additional OEM BIOS version.

Build Date No option Displays the date the BIOS was built.

Product Revision No option Displays the hardware revision of the board.

Serial Number No option Displays the serial number of the board ﬁrmware revision.

BC Firmware Revision No option Displays the controller ﬁrmare revision

MAC Address No option Displays the MAC address of the onboard ethernet controller.

Boot Counter No option Displays the number of boot-ups. (max. 16777215).

Running Time No option Displays the time the board is running [in hours max. 65535].

►Platform Information

System Date Day of week, month/

submenu Opens the Platform Information submenu.

Speciﬁes the current system date

day/year

Note: The date is in month-day-year format.

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Feature Options Description

System Time Hour:Minute:Second Speciﬁes the current system time.

11.3.1 Platform Information Submenu

The platform information submenu offers additional hardware and software information.

Feature Options Description

Processor Information No option Subtitle.

Processor Type No option Displays the processor ID string. The “Processor Type” text itself is not

Codename No option Displays the processor codename

Processor Speed No option Displays the processor speed.

Processor Signature No option Displays the processor signature.

Stepping No option Displays the processor stepping.

Processor Cores No option Displays the number of processor cores.

Microcode Revision No option Displays the processor microcode revision.

IGD HW Version No option Displays the version of the graphics controller.

IGD VBIOS Version No option Displays the video BIOS version.

Total Memory No option Displays the total amount of installed memory.

PCH Information No option subtitle

Codename No option Displays the codename of the Platform Controller hub (PCH).

PCH SKU No option Displays the SKU name of the PCH.

Stepping No option Displays the PCH stepping.

Note: The time is in 24 hour format.

displayed just the ID string.

11.4 Advanced Setup

Select the advanced tab from the setup menu to enter the advanced BIOS setup screen. The menu is used for setting advanced features and only features described within this user’s guide are listed.

Main Advanced Chipset Boot Security Save & Exit

Graphics

Watchdog

Hardware Health Monitoring

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Main Advanced Chipset Boot Security Save & Exit

PCI & PCI Express

ACPI

RTC Wake

Trusted Computing

CPU

SATA

Intel(R) Rapid Start Technology

Acoustic Management

USB

SMART Settings

Super IO

Serial Port Console Redirection

UEFI Network Stack

Intel(R) Ethernet Connection I218-LM

11.4.1 Graphics Submenu

Feature Options Description

Primary Graphics Device Auto

Internal Graphics Device Auto

IGD Pre-Allocated Graphics Memory

IGD Total Graphics Memory 128MB

IGD

PEG PCI/PCIe

Disabled Enabled

32M, 64M, 96M, 128M, 160M, 192M, 224M, 256M, 288M, 320M, 352M, 384M, 416M, 448M, 480M, 512M, 1024M

256MB

MAX

Select primary graphics adapter to be used during boot up. Auto: BIOS will select it automatically. IGD: Internal Graphics Device (IGD) located in chipset. PEG: External PCI Express Graphics (PEG) card attached to the PEG port. PCI/PCIe: PCI/PCIe graphics card attached to some other (not PEG) PCI/PCIe port.

Enable or disable Internal Graphics Device (IGD).

Select amount of pre-allocated (ﬁxed) graphics memory used by the Internal Graphics Device.

Select amount of total graphics memory that may be used by the Internal Graphics Device. Memory above the ﬁxed graphics memory will be dynamically allocated by the graphics driver according to DVMT

5.0 speciﬁcation. MAX = Use as much graphics memory as possible. Depends on total system memory installed and the operating system used (see DVMT 5.0 speciﬁcation).

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Feature Options Description

Primary IGD Boot Display Device

Secondary IGD Boot Display Device

Active LFP Conﬁguration No Local Flat Panel

Always Try Auto Panel Detect No

Local Flat Panel Type Auto

Backlight Inverter Type None

Auto CRT LFP EFP EFP2 EFP3

Disabled

CRT LFP EFP EFP2 EFP3

Integrated LVDS

eDP

Yes

VGA 640x480 1x18 (002h) VGA 640x480 1x18 (013h) WVGA 800x480 1x24 (01Bh) SVGA 800x600 1x18 (01Ah) XGA 1024x768 1x18 (006h) XGA 1024x768 2x18 (007h) XGA 1024x768 1x24 (008h) XGA 1024x768 2x24 (012h) WXGA 1280x800 1x18 (01Eh) WXGA 1280x768 1x24 (01Ch) SXGA 1280x1024 2x24 (00Ah) SXGA 1280x1024 2x24 (018h) UXGA 1600x1200 2x24 (00Ch) HD 1920x1080 2x24 (01Dh) WUXGA 1920x1200 2x18 (015h) WUXGA 1920x1200 2x24 (00Dh) Customized EDID™ 1 Customized EDID™ 2 Customized EDID™ 3

PWM

I2C

Select the Primary IGD display device(s) used for boot up. CRT selects Analog VGA display port. LFP (Local Flat Panel) selects a LVDS panel connected to the integrated LVDS port. EFPx (External Flat Panel ) selects a HDMI/DVI or DisplayPort device connected to the Digital Display Interfaces DDI1, DDI2 and DDI3. Examples for EFPx name assignment to DDI1, DDI2, DDI3:

1. If only DDI2 is enabled then the EFP name is assigned to DDI2.

2. If both port DDI1 and DDI2 are enabled then EFP is assigned to DDI1 and EFP2 is assigned to DDI2. EFP selections are valid only when DDI1, DDI2 and/or DDI3 are enabled.

Select the Secondary IGD display device(s) used for boot up.

VGA modes will be supported only on Primary display. For other details see Primary IGD Boot Display Device.

Select the active local ﬂat panel conﬁguration.

If set to ‘Yes’ the BIOS will ﬁrst look for an EDID data set in an external EEPROM to conﬁgure the Local Flat Panel. Only if no external EDID data set can be found, the data set selected under ‘Local Flat Panel Type’ will be used as a fallback data set.

Select a predeﬁned LFP type or choose Auto to let the BIOS automatically detect and conﬁgure the attached LVDS panel. Auto detection is performed by reading an EDID data set via the video I²C bus. The number in brackets speciﬁes the congatec internal number of the respective panel data set.

Note: Customized EDID™ utilizes an OEM deﬁned EDID™ data set stored in the BIOS ﬂash device.

Select the type of backlight inverter used. PWM = Use IGD PWM signal. I2C = Use I2C backlight inverter device connected to the video I²C bus.

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Feature Options Description

PWM Inverter Polarity Normal

Inverted

PWM Inverter Frequency (Hz) 200 - 40000 Set the PWM inverter frequency in Hz. Only visible if Backlight Inverter Type is set to PWM.

Backlight Setting 0%, 10%, 25%, 40%, 50%, 60%,

75%, 90%, 100%

Inhibit Backlight No

Permanent Until End Of POST

Invert Backlight Setting No

Yes

LVDS SSC Disabled, 0.5%, 1.0%, 1.5%,

2.0%, 2.5%

Digital Display Interface 1 (DDI1)

Digital Display Interface 2 (DDI2)

Digital Display Interface 3 (DDI3)

►GOP Conﬁguration submenu Conﬁgure graphics output when using the UEFI Graphics Output Protocol (GOP) driver instead of legacy

Auto Selection

isabled HDMI/DVI

Auto Selection

Disabled Display Port HDMI/DVI

Auto Selection

Disabled Display Port HDMI/DVI

Select PWM inverter polarity. Only visible if Backlight Inverter Type is set to PWM .

Actual backlight value in percent of the maximum setting.

Decide whether the backlight on signal should be activated when the panel is activated or whether it should remain inhibited until the end of BIOS POST or permanently.

Allow to invert backlight control values if required for the actual I2C type backlight hardware controller.

Conﬁgure LVDS spread spectrum clock modulation depth with center spreading and ﬁxed modulation frequency of 32.9kHz.

Select the output type of the digital display interface. NOTE: On conga-TS87 rev. A, the ‘Auto Selection’ option is not displayed and the default conﬁguration is ‘HDMI/DVI’.

video BIOS. Only visible if GOP driver is conﬁgured to be used in the ‘Video Option ROM Launch Policy’ setup node.

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11.4.1.1 GOP Conﬁguration Submenu

Feature Options Description

Output Device (options depend on detected display devices) Select boot display device in GOP driver mode.

BIST Enable Disabled

Enabled

11.4.2 Watchdog Submenu

Feature Options Description

POST Watchdog Disabled

30sec 1min 2min 5min 10min 30min

Stop Watchdog For User Interaction

Runtime Watchdog Disabled

Delay Disabled

Event 1 ACPI Event

Event 2 Disabled

Yes

One-time Trigger Single Event Repeated Event

10sec 30sec 1min 2min 5min 10min 30min

Reset

Power Button

ACPI Event Reset Power Button

Starts or stops the BIST (built in self test) on the integrated display panel.

Select the timeout value for the POST watchdog.

The watchdog is only active during the power-on-self-test of the system and provides a facility to prevent errors during boot up by performing a reset.

Select whether the POST watchdog should be stopped during the popup boot selection menu or while waiting for setup password insertion.

Selects the operating mode of the runtime watchdog. This watchdog will be initialized just before the operating system starts booting. If set to ‘One-time Trigger’ the watchdog will be disabled after the ﬁrst trigger. If set to ‘Single Event’, every stage will be executed only once, then the watchdog will be disabled. If set to ‘Repeated Event’ the last stage will be executed repeatedly until a reset occurs.

Select the delay time before the runtime watchdog becomes active. This ensures that an operating system has enough time to load.

Selects the type of event that will be generated when timeout 1 is reached. For more information about ACPI Event, see note below.

Selects the type of event that will be generated when timeout 2 is reached.

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Feature Options Description

Event 3 Disabled

ACPI Event Reset Power Button

Timeout 1 1sec

2sec 5sec 10sec

30sec

1min 2min 5min 10min 30min

Timeout 2 see above Selects the timeout value for the second stage watchdog event.

Timeout 3 see above Selects the timeout value for the third stage watchdog event.

Watchdog ACPI Event

Shutdown

Restart

Selects the type of event that will be generated when timeout 3 is reached.

Selects the timeout value for the ﬁrst stage watchdog event.

Select the operating system event that is initiated by the watchdog ACPI event. These options perform a critical but orderly operating system shutdown or restart.

Note

In ACPI mode, it is not possible for a “Watchdog ACPI Event” handler to directly restart or shutdown the OS. For this reason the congatec BIOS will do one of the following:

For Shutdown: An over temperature notiﬁcation is executed. This causes the OS to shut down in an orderly fashion.

For Restart: An ACPI fatal error is reported to the OS.

Additionally, the conga-TS87 module does not support the watchdog NMI mode.

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11.4.3 Hardware Health Monitoring Submenu

Feature Options Description

CPU Temperature No option Displays the actual CPU temperature in °C.

Board Temperature No option Displays the actual board temperature in °C.

Environment Temperature No option Displays the actual environment temperature in °C.

12V Standard No option Displays the actual voltage of the 12V standard power supply.

5V Standby No option Displays the actual voltage of the 5V standby power supply.

CPU Fan Speed No option Displays the actual CPU fan speed in RPM.

Fan PWM Frequency Mode Low Frequency

High Frequency

Continuous Tacho Reading Disabled

Pulses Per Revolution 1, 2, 3, 4 Select number of pulses per revolution generated by the attached fan.

Automatic Fan Speed Control

Fan Control Temperature CPU Temperature

Start Temperature 30, 40, 50, 60, 70, 80,

Temperature Range 5, 10, 15, 20, 25, 30, 40,

Minimum Fan Speed Fan Off, 10%, 15%, 20%,

Maximum Fan Speed Fan Off, 10%, 15%, 20%,

Fan Always On At Minimum Speed

Enabled

Disabled

Enabled

Board Temperature Environ Temperature

90, 100°C

55, 80°C

25%, 30%, 35%, 40%, 45%, 50%, 55%, 60%, 65%, 70%, 75%, 80%, 85%, 90%, 95% 100%

Disabled

Enabled

Select fan PWM base frequency mode. Low frequency: 35.3Hz High frequency: 22.5kHz

If enabled, the fan tacho pulses are measured continuously instead of once per second. Helps to avoid audible pulsing of the fan as the speed would be set to 100% for a very short time during measurement.

Enable hardware fan speed control. Independent from any operating system the fan will be turned on once a certain start temperature is reached and linearly ramped up to the deﬁned maximum speed within the given temperature range.

Select which temperature input is used for the automatic fan speed control.

At this temperature the fan will be turned on at the deﬁned minimum fan speed.

Within this temperature range the fan will ramp up to the deﬁned maximum fan speed.

Select minimum/start fan speed to be set when the start temperature of the control slope is reached.

Select maximum/end fan speed to be ramped up to until the end temperature of the control slope is reached.

If enabled, the fan will always run at least at the selected minimum speed, even if the control temperature is below the fan control start temperature. This is to ensure a minimum air ﬂow all the time.

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11.4.4 PCI & PCI Express Submenu

Feature Options Description

PCI Settings

PCI Latency Timer 32, 64, 96, 128,

160, 192, 224, 248 PCI Bus Clocks

VGA Palette Snoop Disabled

Enabled

PERR# Generation Disabled

Enabled

SERR# Generation Disabled

Enabled

Generate EXCD0/1_PERST# Disabled

1ms 5ms

10ms

50ms 100ms 150ms 200ms 250ms

►PCI Express Settings submenu PCI Express device and link settings.

►PIRQ Routing & IRQ

Reservation

►PCI Express Graphics (PEG) Port

PCIE Root Port Function Swapping

Subtractive Decode Disabled

►PCI Express Port 0 submenu Opens the PCI Express Port submenu

►PCI Express Port 1 submenu Opens the PCI Express Port submenu

►PCI Express Port 2 submenu Opens the PCI Express Port submenu

►PCI Express Port 3 submenu Opens the PCI Express Port submenu

►PCI Express Port 4 submenu Opens the PCI Express Port submenu

►PCI Express Port 5 submenu Opens the PCI Express Port submenu

►PCI Express Port 6 submenu Opens the PCI Express Port submenu

submenu Manual PIRQ routing and interrupt reservation for legacy devices.

submenu PCI Express Graphics (PEG) port settings. PEG port is not supported on low end CPUs.

Disabled

Enabled

Select value to be programmed into PCI latency timer register.

Enable or disable VGA palette registers snooping.

Enable or disable PCI device to generate PERR#.

Enable or disable PCI device to generate SERR#.

Select whether the COM Express EXCD0_PERST# and EXCD1_PERST# pins should be driven low during POST and how long it will be, if enabled.

Enable or disable PCI Express root port function swapping.

Enable or disable PCI Express subtractive decode.

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11.4.4.1 PCI Express Settings Submenu

Feature Options Description

Relaxed Ordering Disabled

Enabled

Extended Tag Disabled

Enabled

No Snoop Disabled

Enabled

Maximum Payload Auto

128 Bytes 256 Bytes 512 Bytes 1024 Bytes 2048 Bytes 4096 Bytes

Maximum Read Request Auto

128 Bytes 256 Bytes 512 Bytes 1024 Bytes 2048 Bytes 4096 Bytes

ASPM Disabled

Auto Force L0s

Extended Synch Disabled

Enabled

Link Training Retry Disabled, 2, 3, 5 Deﬁnes number of retry attempts software will take to retrain the link if previous training attempt was unsuccessful.

Link Training Timeout (us) 10-10000

Default : 100

Unpopulated Links Keep Link On

Disabled

Restore PCIe Registers Enabled

Disabled

Enable or disable PCI Express device relaxed ordering.

If enabled a device may use an 8-bit tag ﬁled as a requester.

Enable or disable PCI Express device 'No Snoop' option.

Set maximum payload of PCI Express devices or allow system BIOS to select the value.

Set maximum read request size of PCI Express devices or allow system BIOS to select the value.

PCI Express Active State Power Management settings.

If enabled, the generation of extended PCI Express synchronization patterns is allowed.

Deﬁnes number of microseconds software will wait before polling link training bit in the link status register. Value ranges from 10 to 10000 us.

In order to save power, software will disable unpopulated PCI Express links, if this option is set to disabled.

On non-PCI Express aware operating systems some devices may not be re-initialized correctly after S3. Setting this node to Enabled restores PCI Express conﬁguration on S3 resume. Warning: Enabling this may cause issues with other hardware after S3 resume.

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11.4.4.2 PIRQ Routing & IRQ Reservation Submenu

Feature Options Description

PIRQA Auto, IRQ3,

IRQ4, IRQ5, IRQ6, IRQ10, IRQ11, IRQ14, IRQ15

PIRQB same as PIRQA same as PIRQA

PIRQC same as PIRQA same as PIRQA

PIRQD same as PIRQA same as PIRQA

PIRQE same as PIRQA same as PIRQA

PIRQF same as PIRQA same as PIRQA

PIRQG same as PIRQA same as PIRQA

PIRQH same as PIRQA same as PIRQA

Reserve Legacy Interrupt 1 None, IRQ3,

IRQ4, IRQ5, IRQ6, IRQ10, IRQ11, IRQ14, IRQ15

Reserve Legacy Interrupt 2 same as Reserve

Legacy Interrupt 1

Set interrupt for selected PIRQ. Please refer to the board’s resource list for a detailed list of devices connected to the respective PIRQ. Note: These settings will only be effective while operating in PIC (non-IOAPIC) interrupt mode.

The interrupt reserved here will not be assigned to any PCI or PCI Express device and thus maybe available for some legacy bus device.

same as Reserve Legacy Interrupt 1

11.4.4.3 PCI Express Graphics (PEG) Port Submenu

Feature Options Description

PCI Express Graphics (PEG) Port

PEG Port Conﬁguration 1x16

PEG0 No option Displays the width and the operation mode at which the attached device currently operates on PEG0 port

Disabled Enabled

Auto

2x8 1x8+2x4

Disabled = Disable internal PEG interface devices and do not detect the devices connected to PEG port. Enabled = Enable internal PEG interface devices also if no device is detected on PEG port. Auto = Disable internal PEG interface devices if no device is detected on PEG port.

It determines how many ports with certain widths, will be formed from available 16 PCIe lanes.

(B0:D1:F0). Some Gen3, Gen2 devices start up in Gen1 mode and their OS driver just sets them to Gen3 or Gen2 mode.

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Feature Options Description

PEG0 Speed Auto

Gen1 Gen2 Gen3

PEG0 ASPM Disabled

Auto ASPM L0s ASPM L1 ASPM L0sL1

ASPM L0s Disabled

Root Port Only Endpoint Port Only

Both Root and Endpoint Ports

PEG0 De-emphasis Control -6 dB

-3.5 dB

PEG1 No option Displays the width and the operation mode at which the attached device currently operates on PEG1 port

PEG1 Speed Auto

Gen1 Gen2 Gen3

PEG1 ASPM Disabled

Auto ASPM L0s ASPM L1 ASPM L0sL1

ASPM L0s Disabled

Root Port Only Endpoint Port Only

Both Root and Endpoint Ports

PEG1 De-emphasis Control -6 dB

-3.5 dB

PEG2 No option Displays the width and the operation mode at which the attached device currently operates on PEG2 port

PEG0 port (B0:D1:F0) max. speed Auto = Gen1, Gen2 or Gen3 Gen1 = 2.5GT/s Gen2 = 5.0GT/s Gen3 = 8.0GT/s Some older non-compliant PCI Express devices will function only if Gen1 is selected.

Control ASPM support for the PEG device. This has no effect if PEG is not the currently active device.

Enable PCIe ASPM L0s on PEG0 port (B0:D1:F0).

Conﬁgure the de-emphasis control on PEG.

(B0:D1:F1). Some Gen3, Gen2 devices start up in Gen1 mode and their OS driver just sets them to Gen3 or Gen2 mode.

PEG1 port (B0:D1:F1) max. speed Auto = Gen1, Gen2 or Gen3 Gen1 = 2.5GT/s Gen2 = 5.0GT/s Gen3 = 8.0GT/s Some older non-compliant PCI Express devices will function only if Gen1 is selected.

Control ASPM support for the PEG device. This has no effect if PEG is not the currently active device.

Enable PCIe ASPM L0s on PEG1 port (B0:D1:F1).

Conﬁgure the de-emphasis control on PEG.

(B0:D1:F2). Some Gen3, Gen2 devices start up in Gen1 mode and their OS driver just sets them to Gen3 or Gen2 mode.

Page 93

Feature Options Description

PEG2 Speed Auto

Gen1 Gen2 Gen3

PEG2 ASPM Disabled

Auto ASPM L0s ASPM L1 ASPM L0sL1

ASPM L0s Disabled

Root Port Only Endpoint Port Only

Both Root and Endpoint Ports

PEG2 De-emphasis Control -6 dB

Run-time C7 Allowed Disabled

Detect Non-compliant Device Disabled

Program PCIe ASPM after OpROM

PEG Sampler Calibrate Auto

Swing Control Half

PEG Gen3 Equalization Enabled

Gen3 Eq Phase 2 Auto

► PEG Gen3 Root Port Preset Value for each Lane

► PEG Gen3 Endpoint Preset Value for each Lane

► PEG Gen3 Endpoint Hint Value for each Lane

-3.5 dB

Enabled

Disabled

Enabled

Disabled

Full

Disabled

Enabled

Disabled

submenu In this submenu the Root Port Preset Value for PEG port lanes 0 -15 can be set individually.

submenu In this submenu, the Endpoint Preset Value for PEG port lanes 0 -15 can be set individually.

submenu In this submenu, the Endpoint Hint Value for PEG port lanes 0 -15 can be set individually.

PEG2 port (B0:D1:F2) max. speed Auto = Gen1, Gen2 or Gen3 Gen1 = 2.5GT/s Gen2 = 5.0GT/s Gen3 = 8.0GT/s Some older non-compliant PCI Express devices will function only if Gen1 is selected.

Control ASPM support for the PEG device. This has no effect if PEG is not the currently active device.

Enable PCIe ASPM L0s on PEG2 port (B0:D1:F2).

Conﬁgure the de-emphasis control on PEG.

Enable or disable the entry to C7 state (run-time control). Don’t enable this feature until you have all the appropriate Save/Restore Controller/Endpoint state.

Try to detect also a non-compliant PCI Express device on the PEG port.

Enabled = PCIe ASPM will be programmed after OpROM. Disabled = PCIe ASPM will be programmed before OpROM

Enable or disable PEG sampler calibrate.

Swing Control

Perform PEG Gen3 equalization steps.

Perform PEG Gen3 equalization phase 2.

Page 94

Feature Options Description

Gen3 Eq Preset Search Enabled

Disabled

Always Re-search Gen3 Eq Preset

Preset Search Dwell Time 1-65535

Error Target 1-65535

PEG RxCEM Loopback Mode Enabled

PEG Lane Number for Test 1-15

► PCIe Gen3 RxCTLEp Setting

Enabled

Disabled

Default : 1000

Default : 1

Disabled

Default : 0

submenu In this submenu, the RxCTLEp Value for PEG lanes 0 -7 can be set individually.

Note

The items related to PEG 1 will only be displayed when you conﬁgure PEG Port as 2x8 or 1x8+2x4.

The items releated to PEG 2 will only be displayed when you conﬁgure PEG Port as 1x8+2x4.

11.4.4.4 PCI Express Port Submenu

Perform PEG Gen3 preset search algorithm.

Always re-search Gen3 preset, even if it has been done once.

PEG Gen3 preset search dwell time in [ms].

Set the margin search error target value [1..65535].

Enable or disable PEG RxCEM loopback mode.

PEG lane number for RxCEM Loopback mode (0~15)

Feature Options Description

PCI Express Port x Disabled

Enabled

ASPM Disabled

L0s L1 L0sL1 Auto

L1 Substates Disabled

L1.1 L1.2 L1.1 & L1.2

URR Disabled

Enabled

Enable or disable the respective PCI Express port x. Note: Unless the Always Enable Port (see below) is enabled as well, an unpopulated port will still be disabled if no PCI Express device is connected.

PCI Express Active State Power Management settings.

PCI Express L1 substates settings.

Enable or disable PCI Express Unsupported Request Reporting.

Page 95

Feature Options Description

FER Disabled

Enabled

NFER Disabled

Enabled

CER Disabled

Enabled

CTO Disabled

Enabled

SEFE Disabled

Enabled

SENFE Disabled

Enabled

SECE Disabled

Enabled

PME SCI Disabled

Enabled

Always Enable Port Disabled

Enabled

PCIe Speed Auto

Gen1

Detect Non-compliant Device Disabled

Enabled

Extra Bus Reserved 0-7

Default : 0

Reserved Memory 1-20

Default : 10

Prefetchable Memory 1-20

Default : 10

Reserved I/O 4-20

Default : 4

PCIe LTR Disabled

Enabled

PCIe LTR Lock Disabled

Enabled

Enable or disable PCI Express device Fatal Error Reporting.

Enable or disable PCI Express device Non-Fatal Error Reporting.

Enable or disable PCI Express device Correctable Error Reporting.

Enable or disable PCI Express Completion Timeout timer.

Enable or disable Root PCI Express System Error on Fatal Error.

Enable or disable Root PCI Express System Error on Non-Fatal Error.

Enable or disable Root PCI Express System Error on Correctable Error.

Enable or disable PCI Express PME (power management event) SCI.

Disabled = Disable the internal PCI Express interface device if no device is detected on the port. Enabled = Enable the internal PCI Express interface device also if no device is detected on the port.

Maximum speed of the PCIe port. Auto = Gen1 or Gen2 Gen1 = 2.5GT/s Some older non-compliant PCI Express devices will function only if Gen1 is selected. Some Gen2 devices start up in Gen1 mode and then their OS driver sets them to Gen2 mode.

Try to detect also a non-compliant PCI Express device. If enabled, POST time will be longer.

Extra bus reserved (0-7) for bridges behind this root bridge.

Reserved memory range for this root bridge.

Prefetchable memory range for this root bridge.

Reserved I/O range for this root bridge.

Enable or disable PCI Express Latency Tolerance Reporting (LTR).

PCIe LTR conﬁguration lock.

Page 96

Feature Options Description

Snoop Latency Override Disabled

Snoop Latency Multiplier 1 ns, 32 ns, 1024 ns

Snoop Latency Value 0-252

No-Snoop Latency Override Disabled

No-Snoop Latency Multiplier 1 ns, 32 ns, 1024 ns

No-Snoop Latency Value 0-252

11.4.5 ACPI Submenu

Feature Options Description

Hibernation Support Disabled

ACPI Sleep State Suspend Disabled

Lock Legacy Resources Disabled

S3 Video Repost Disabled

Native PCI Express Support Disabled

Native ASPM Disabled

ACPI Debug Disabled

Manual

Auto

32768 ns, 1048576 ns 33554432 ns

Default : 60

Manual

Auto

32768 ns, 1048576 ns 33554432 ns

Default : 60

Enabled

S1 only (CPU Stop Clock)

S3 (Suspend to RAM)

Both S1 and S3 available for OS to choose from

Enabled

Snoop latency override for PCH PCIe.

Snoop latency multiplier for PCH PCIe.

Snoop latency value for PCH PCIe.

No-Snoop latency override for PCH PCIe.

No-Snoop latency multiplier for PCH PCIe.

No-Snoop latency override for PCH PCIe.

Enable or disable system ability to hibernate (operating system S4 sleep state). This option may not be effective with some operating systems.

Select the state used for ACPI system sleep/suspend.

Enable or disable locking of legacy resources.

Enable or disable video BIOS re-post on S3 resume. Required by some operating systems.

Enable or disable native OS PCI Express support.

Enabled = The OS will control the ASPM support of the PCI Express device. Disabled = The BIOS will control the ASPM support of the PCI Express device.

Open a memory buffer for storing debug strings. Use method ADBG to write strings to buffer.

Page 97

Feature Options Description

ACPI 5.0 CPPC Support Disabled

ACPI 5.0 CPPC Platform SCI Disabled

Automatic Critical Trip Point Disabled

Critical Trip Point Value 71 C, 79 C, 87 C,

Lid Support Disabled

Sleep Button Support Disabled

11.4.6 RTC Wake Submenu

Feature Options Description

Wake System At Fixed Time Disabled

Wake up hour Specify wake up hour. For example, enter “3” for 3am and “15” for 3pm.

Wake up minute Specify wake up minute.

Wake up second Specify wake up second.

Enabled

95 C, 103 C, 106 C, 111 C, 119 C, 127 C

Enabled

Enable ACPI 5.0 Collaborative Processor Performance Control (CPPC) support. When enabled, platform exposes CPPC interfaces to operating system. When disabled, platform exposes legacy (non-CPPC) processor interfaces to operating system.

Enable ACPI 5.0 platform generation of SCI on CPPC command completion. When enabled, platform generates GPE/SCI. When disabled platform does not generate GPE/SCI and OS polls for command completion.

Enabled = Conﬁgure the critical trip point - the temperature threshold at which the ACPI aware OS performs a critical shutdown - automatically to recommended value. Disabled = Conﬁgure the critical trip point manually.

Speciﬁes the temperature threshold at which the ACPI aware OS performs a critical shutdown.

Conﬁgure COM Express LID# signal to act as ACPI lid.

Conﬁgure COM Express SLEEP# signal to act as ACPI sleep button.

Enable system to wake from S5 using RTC alarm.

11.4.7 Trusted Computing Submenu

Feature Options Description

Security Device Support Disabled

Enabled

TPM State Disabled

Enabled

Enable or disable TPM support. System reset is required after change.

Enable or disable TPM chip. Note: System might restart several times during POST to acquire target state.

Page 98

Feature Options Description

Pending operation None,

11.4.8 CPU Submenu

Feature Options Description

Processor Type No option Displays the processor ID string. The “Processor Type” is not displayed, just the ID string.

CPU Signature No option Displays the CPU Signature.

Microcode Patch No option Displays the revision of the Microcode Patch.

FSB Speed No option Displays the FSB Speed.

Max CPU Speed No option Displays the Max CPU Speed.

Min CPU Speed No option Displays the Min CPU Speed.

CPU Speed No option Displays the current CPU Speed.

Processor Cores No option Displays the number of the Processor Cores.

Intel HT Technology No option Displays whether Intel HT Technology is supported.

Intel VT-x Technology No option Displays whether Intel VT-x Technology is supported.

Intel SMX Technology No option Displays whether Intel SMX Technology is supported.

64-bit No option Displays whether 64-bit is supported.

EIST Technology No option Displays whether Enhanced Intel SpeedStep Technology (EIST) is supported.

CPU C3 State No option Displays whether CPU C3 State is supported.

CPU C6 State No option Displays whether CPU C6 State is supported.

CPU C7 State No option Displays whether CPU C7 State is supported.

L1 Data Cache No option Displays the size of the L1 Data Cache.

L1 Code Cache No option Displays the size of the L1 Code Cache.

L2 Cache No option Displays the size of the L2 Cache.

L3 Cache No option Displays the size of the L3 Cache.

Set Boot Freq Ratio 8-23

Hyper-Threading Disabled

Enable Take Ownership, Disable Take Ownership, TPM Clear

Default : 255

Enabled

Perform selected TPM chip operation. Note: System might restart several times during POST to perform selected operation.

Range: 8 - 23. This sets the boot ratio. If ratio is out of range, maximum ratio is used. Non-ACPI OSes will use this ratio. The range 8-23 is just an example as the possible range depends on processor variant.

Enable or disable Hyper-Threading technology.

Page 99

Feature Options Description

Active Processor Cores All

1 2 3

Overclocking Lock Disabled

Enabled

Limit CPUID Maximum Disabled

Enabled

Execute Disable Bit Disabled

Enabled

Intel Virtualization Technology Disabled

Enabled

Hardware Prefetcher Disabled

Enabled

Adjacent Cache Line Prefetch Disabled

Enabled

CPU AES Disabled

Enabled

EIST Disabled

Enabled

Energy Performance Performance

Balanced Perform. Balanced Energy Energy Efﬁcient

Turbo Mode Disabled

Enabled

Package Power Limit Lock Disabled

Enabled

CPU Power Limit1 0-255

Default : 0

CPU Power Limit1 Time 0-255

Default : 0

CPU Power Limit2 0-255

Default : 0

Platform Power Limit Lock Disabled

Enabled

Set number of cores to be enabled.

FLEX_RATIO(194) MSR

When enabled, the processor will limit the maximum CPUID input value to 03h when queried, even if the processor supports a higher CPUID input value. When disabled, the processor will return the actual maximum CPUID input value of the processor when queried. Limiting the CPUID input value may be required for older operating systems that cannot handle the extra CPUID information returned when using the full CPUID input value.

Enable/Disable the Execute Disable Bit (XD) of the processor. With the XD bit set to enabled, certain classes of malicious buffer overﬂow attacks can be prevented when combined with a supporting OS.

When enabled, a VMM can utilize the integrated hardware virtualization support.

Enable the Mid Level Cache (L2) streamer prefetcher.

Enable the Mid Level Cache (L2) prefetching of adjacent cache lines.

Enable/Disable CPU Advanced Encryption Standard (AES) instructions.

Enable /Disable or disable Enhanced Intel SpeedStep Technology (EIST).

Optimize between performance and power savings.

Enable/Disable Turbo Mode.

When enabled, PACKAGE_POWER_LIMIT MSR will be locked and a reset will be required to unlock the register.

CPU Power Limit1 value

Time window in which the Power Limit1 is maintained.

CPU Power Limit2 value

When enabled, PLATFORM_POWER_LIMIT MSR will be locked and a reset will be required to unlock the register.

Page 100

Feature Options Description

CPU Power Limit3 0-255

Default : 0

CPU Power Limit3 Time 0-255

Default : 0

CPU Power Limit3 Duty Cycle 0-100

Default : 0

DDR Power Limit1 0-255

Default : 0

DDR Power Limit1 Time 0-255

Default : 0

DDR Power Limit2 0-255

Default : 0

1-Core Ratio Limit 0-255

Default : 0

2-Core Ratio Limit 0-255

Default : 0

3-Core Ratio Limit 0-255

Default : 0

4-Core Ratio Limit 0-255

Default : 0

VR Current Value Lock Disabled

Enabled

VR Current Value 0-8191

Default : 0

CPU C States Disabled

Enabled

Enhanced C1 State Disabled

Enabled

CPU C3 Report Disabled

Enabled

CPU C6 Report Disabled

Enabled

C6 Latency Short

Long

CPU C7 Report Disabled

CPU C7

CPU C7s

C7 Latency Short

Long

CPU Power Limit3 value

Time window in which the Power Limit3 is maintained.

Specify in percentage the duty cycle that the CPU is required to maintain over the conﬁgured Power Limit3 time windows.

DDR Power Limit1 value

Time window in which the DDR Power Limit1 is maintained.

DDR Power Limit2 value

Limit for 1 active core. 0 means using the factory-conﬁgured value.

Limit for 2 active cores. 0 means using the factory-conﬁgured value

Limit for 3 active cores. 0 means using the factory-conﬁgured value.

Limit for 4 active cores. 0 means using the factory-conﬁgured value

Locks VR current value from further writes until a reset.

Voltage regulator current limit. 0 means automatic.

Enable or disable CPU C states.

Enhanced C1 state

Enable or disable CPU C3 report to OS.

Enable or disable CPU C6 report to OS.

Conﬁgure Short/Long latency for C6.

Enable or disable CPU C7 report to OS.

Conﬁgure Short/Long latency for C7.

Congatec TS87 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual