CONEX Bt849AKPF, Bt848KPF, Bt848AKPF Datasheet
Advance Information
This document contains information on a product under development.
The parametric information contains target parameters that are subject to change.
Bt848/848A/849A
Single-Chip Video Capture for PCI
Bt848 is a complete, low cost single-chip solution for analog
NTSC/PAL/SECAM video capture on the PCI bus. As a bus master, Bt848 does
not require any local memory buffers to store video pixel data which significantly minimizes the hardware cost for this architecture. Bt848 takes advantage
of the PCI-based system’s high bandwidth and inherent multimedia capability. It
is designed to be interoperable with any other PCI multimedia device at the
component or board level, thus enabling video capture and overlay capability to
be added to PCI systems in a modular fashion at low cost. The Bt848 solution is
independent of the PCI system bus topology and may be used in a variety of system bus organizations: directly on a motherboard planar bus, on a card for a planar or secondary bus.
The Bt848A/849A are fully backward compatible enhancements to the
Bt848. The Bt848A and 849A both include all the functionality of the Bt848,
while adding support for peaking, single crystal operation, and digital camera
support.
Functional Block Diagram
XTAL
MUXIN
MUXOUT
SYNCDET
REFOUT
YIN
CIN
Analog
Mux
AGC
40 MHz
ADC
40 MHz
ADC
Ultralock™
and
Clock Generation
Horizontal, Vertical
and T emporal
Scaling
Luma-Chroma
Separation
Decimation LPF
Chroma Demod
and
Video Timing
Unit
IIC JT A G
Pixel Format
Conversion
630 Byte FIFO
DMA Controller
PCI I/F
Target
Initiator
Distinguishing Features
• Fully PCI Rev. 2.1 compliant
• Auxiliary GPIO data port and video data
port
• Supports image resolutions up to
768x576 (full PAL resolution)
• Supports complex clipping of video
source
• Zero wait state PCI burst writes
• Field/frame masking support to throttle
bandwidth to target
• Multiple YCrCb and RGB pixel
formats supported on output
• Supports NTSC/SECAM/PAL analog
input
• Image size scalable down to icon using
vertical & horizontal interpolation
filtering
• Multiple composite and S-video inputs
• Supports different destinations for even
and odd fields
• Supports different color space/scaling
factors for even and odd fields
• Support for mapping of video to 225
color palette
• VBI data capture for closed captioning,
teletext and intercast data decoding
Additional Features
in Bt848A/849A Only
• Supports peaking
• Requires only one crystal
• Digital camera support through GPIO
port
• Support for WST decode (Bt849A only)
Brooktree
Digital Camera
Input (Bt848A/849A)
and GPIO Port
Brooktree Division • Rockwell Semiconductor Systems, Inc. • 9868 Scranton Road • San Diego, CA 92121-3707
®
619-452-7580 • 1-800-2-BT-APPS • FAX: 619-452-1249 • Internet: apps@brooktree.com • L848A_A
Applications
• PC TV
• Intercast receiver
• Desktop video phone
• Motion video capture
• Still frame capture
• Teletext/Intertext
• VBI data services capture
Ordering Information
Model Number
Bt848KPF 160-pin PQFP 0˚C to +70˚C
Bt848AKPF 160-pin PQFP 0˚C to +70˚C
Bt849AKPF 160-pin PQFP 0˚C to +70˚C
Package Ambient Temperature Range
Copyright © 1997 Brooktree Corporation. All rights reserved.
Print date: February 1997
Brooktree reserves the right to make changes to its products or specifications to improve performance, reliability, or
manufacturability. Information furnished by Brooktree Corporation is believed to be accurate and reliable. However, no
responsibility is assumed by Brooktree Corporation for its use; nor for any infringement of patents or other rights of third parties
which may result from its use. No license is granted by its implication or otherwise under any patent or patent rights of Brooktree
Corporation.
Brooktree products are not designed or intended for use in life support appliances, devices, or systems where malfunction of a
Brooktree product can reasonably be expected to result in personal injury or death. Brooktree customers using or selling Brooktree
products for use in such applications do so at their own risk and agree to fully indemnify Brooktree for any damages resulting from
such improper use or sale.
Brooktree is a registered trademark of Brooktree Corporation. Product names or services listed in this publication are for
identification purposes only, and may be trademarks or registered trademarks of their respective companies. All other marks
mentioned herein are the property of their respective holders.
Specifications are subject to change without notice.
PRINTED IN THE UNITED STATES OF AMERICA
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List Of Figures
List of Tables
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viii
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . x
Functional Description
Functional Overview
Video Capture Over PCI Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Supports Intel Intercast™. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Bt848A Analog Video and Digital Camera Capture Over the PCI Bus. . . . . . . . . . . . 2
DMA Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
PCI Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
UltraLock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Scaling and Cropping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Input Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
GPIO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Vertical Blanking Interval Data Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
I
C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Descriptions
Pin Assignments
UltraLock
Composite Video Input Formats
Y/C Separation and Chroma Demodulation
Video Scaling, Cropping, and Temporal Decimation
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
The Challenge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Operation Principles of UltraLock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Horizontal and Vertical Scaling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Luminance Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Peaking (Bt848A and Bt849A Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Chrominance Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Scaling Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Image Cropping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Cropping Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Temporal Decimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
. . . . . . . . . . . . . . . . . . . . . . . . . . 21
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®
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Video Adjustments
The Hue Adjust Register (HUE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
The Contrast Adjust Register (CONTRAST). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
The Saturation Adjust Registers (SAT_U, SAT_V) . . . . . . . . . . . . . . . . . . . . . . . . . . 33
The Brightness Register (BRIGHT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Automatic Chrominance Gain Control
Low Color Detection and Removal
Coring
VBI Data Output Interface
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Video Data Format Conversion
Pixel Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Video Control Code Status Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
YCrCb to RGB Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Gamma Correction Removal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
YCrCb Sub-sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Byte Swapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Video and Control Data FIFO
Logical Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
FIFO Data Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Physical Implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
FIFO Input/Output Rates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
DMA Controller
Target Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
RISC Program Setup and Synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
RISC Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Complex Clipping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Executing Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
FIFO Over-run Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
FIFO Data Stream Resynchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Single-Chip Video Capture for PCI
Bt848/848A/849A
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
iv
Electrical Interfaces
Input Interface
Analog Signal Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Multiplexer Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Autodetection of NTSC or PAL/SECAM Video . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Flash A/D Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
A/D Clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Power-up Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Automatic Gain Controls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Crystal Inputs and Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Single Crystal Operation (Bt848A/849A Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2X Oversampling and Input Filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
L848A_A
Brooktree
®
Bt848/848A/849A
Single-Chip Video Capture for PCI
PCI Bus Interface
General Purpose I/O Port
GPIO Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
GPIO SPI Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Digital Video in Support (Bt848A/849A Only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
2
I
C Interface
JTAG Interface
Need for Functional Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
JTAG Approach to Testability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Optional Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Verification with the Tap Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
PC Board Layout Considerations
Ground Planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Power Planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Digital Signal Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Analog Signal Interconnect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Latch-up Avoidance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
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. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Control Register Definitions
PCI Configuration Space
PCI Configuration Registers
Vendor and Device ID Register
Command and Status Register
Revision ID and Class Code Register
Latency Timer Register
Base Address 0 Register
Interrupt Line, Interrupt Pin, Min_Gnt, Max_Lat Register
Local Registers
Device Status Register
Input Format Register
Temporal Decimation Register
MSB Cropping Register
Vertical Delay Register, Lower Byte
Vertical Active Register, Lower Byte
Horizontal Delay Register, Lower Byte
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
. . . . . . . . . . . . . . . . . . . . . . 89
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Brooktree
Horizontal Active Register, Lower Byte
Horizontal Scaling Register, Upper Byte
®
L848A_A
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
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Horizontal Scaling Register, Lower Byte
Brightness Control Register
Miscellaneous Control Register
Luma Gain Register, Lower Byte
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Chroma (U) Gain Register, Lower Byte
Chroma (V) Gain Register, Lower Byte
Hue Control Register
SC Loop Control Register
Output Format Register
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Vertical Scaling Register, Upper Byte
Vertical Scaling Register, Lower Byte
Test Control Register
AGC Delay Register
Burst Delay Register
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Single-Chip Video Capture for PCI
Bt848/848A/849A
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
ADC Interface Register
Video Timing Control
Software Reset Register
Color Format Register
Color Control Register
Capture Control
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
VBI Packet Size. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
VBI Packet Size / Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
PLL Reference Multiplier - PLL_F_LO (Bt848A/849A only). . . . . . . . . . . . . . . . . . . . 111
PLL Reference Multiplier - PLL_F_HI (Bt848A/849A only). . . . . . . . . . . . . . . . . . . . . 111
Integer- PLL-XCI (Bt848A/849A only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Field Capture Counter-(FCAP) (Bt848A/849A only) . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Interrupt Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Interrupt Mask. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
RISC Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
RISC Program Start Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
GPIO and DMA Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
vi
GPIO Output Enable Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
GPIO Registered Input Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
GPIO Data I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
I2C Data/Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
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Bt848/848A/849A
Single-Chip Video Capture for PCI
Control Register Digital Video In Support (Bt848A/849A Only). . . . . . . . . . . . . . . 119
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Digital Video Signal Interface Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Timing Generator Load Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Timing Generator Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Luma Gain Register, Lower Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Chroma (V) Gain Register, Lower Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Chroma (U) Gain Register, Lower Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
HDELAY/HSCALE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
ParametricInformation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
DC Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
AC Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Package Mechanical Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Datasheet Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
TABLE OF CONTENTS
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®
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LIST OF FIGURES
List Of Figures
Figure 1. Bt848/848A/849A Detailed Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 2. Bt848 Video Decoder and Scaler Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. Bt848/848A/849A Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 4. UltraLock Behavior for NTSC Square Pixel Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 5. Y/C Separation and Chroma Demodulation for Composite Video . . . . . . . . . . . . . . . . . . 19
Figure 6. Y/C Separation Filter Responses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 7. Filtering and Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 8. Optional Horizontal Luma Low-Pass Filter Responses. . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 9. Combined Luma Notch, 2x Oversampling
Figure 10. Combined Luma Notch, 2x Oversampling
Figure 11. Frequency Responses for the Four Optional Vertical Luma Low-Pass Filters . . . . . . . . . 23
Figure 12. Combined Luma Notch and 2x Oversampling Filter Response . . . . . . . . . . . . . . . . . . . . 23
Figure 13. Peaking Filters (Bt848A/849A only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 14. Luma Peaking Filters with 2x Oversampling Filter
Figure 15. Effect of the Cropping and Active Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 16. Regions of the Video Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 17. Coring Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 18. Regions of the Video Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 19. VBI Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 20. VBI Section Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 21. Video Data Format Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 22. Data FIFO Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 23. RISC Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 24. Example of Bt848 Performing Complex Clipping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 25. Typical External Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 26. Clock Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 27. Luma and Chroma 2x Oversampling Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 28. PCI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 29. GPIO Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 30. GPIO SPI Input Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 31. GPIO SPI Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 32. Video Timing in SPI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 33. Basic Timing Relationships for SPI Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 34. CCIR 656 or ByteStream Interface to Digital Input Port . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Single-Chip Video Capture for PCI
Bt848/848A/849A
and Optional Low-Pass Filter Response (NTSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
and Optional Low-Pass Filter Response (PAL/SECAM) . . . . . . . . . . . . . . . . . . . . . . . . . 22
and Luma Notch (Bt848A/849A only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
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Bt848/848A/849A
Single-Chip Video Capture for PCI
Figure 35. The Relationship between SCL and SDA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 36. I2C Typical Protocol Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 37. Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 38. Example Ground Plane Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 39. Optional Regulator Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 40. Typical Power and Ground Connection Diagram and Parts List . . . . . . . . . . . . . . . . . . . 82
Figure 41. PCI Configuration Space Header. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 42. Clock Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Figure 43. GPIO Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Figure 44. JTAG Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Figure 45. 160-pin PQFP Package Mechanical Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
LIST OF FIGURES
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L848A_A
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LIST OF TABLES
List of Tables
Table 1. PCI Video Decoder Product Family. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Table 2. Pin Descriptions Grouped by Pin Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. Bt848 Pin List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 4. Video Input Formats Supported by the Bt848 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 5. Register Values for Video Input Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 6. Scaling Ratios for Popular Formats Using Frequency Values . . . . . . . . . . . . . . . . . . . . . . 28
Table 7. Color Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 8. Byte Swapping Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 9. Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 10. Table of PCI Bus Access Latencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 11. RISC Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 12. FIFO Full/Almost Full Counts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 13. Synchronous Pixel Interface (SPI) GPIO Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 14. Pin Definition of GPIO Port When Using Digital Video-In Mode . . . . . . . . . . . . . . . . . . . . 73
Table 15. Device Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 16. Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Table 17. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Table 18. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Table 19. Clock Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Table 20. GPIO SPI Mode Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Table 21. Power Supply Current Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Table 22. Power Supply Current Parameters (Bt848A/849A only) . . . . . . . . . . . . . . . . . . . . . . . . . 128
Table 23. JTAG Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Table 24. Decoder Performance Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Table 25. Bt848 Datasheet Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Single-Chip Video Capture for PCI
Bt848/848A/849A
x
L848A_A
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®
FUNCTIONAL DESCRIPTION
Functional Overview
Video Capture
Over PCI Bus
Supports
Intel Intercast™
The Bt848/848A/849A integrates an NTSC/PAL/SECAM composite & S-Video
decoder, scaler, DMA controller, and PCI Bus master on a single device.
Bt848/848A/849A can place video data directly into host memory for video capture applications and into a target video display frame buffer for video o v erlay applications. As a PCI initiator, Bt848/848A/849A can take control of the PCI bus as
soon as it is available, thereby avoiding the need for on-board frame buffers.
Bt848/848A/849A contains a pixel data FIFO to decouple the high speed PCI bus
from the continuous video data stream. Figure 1 shows a block diagram of the
Bt848/848A/849A, and Figure 2 shows a detailed block diagram of the decoder
and scaler sections.
The video data input may be scaled, color translated, and burst transferred to a
target location on a field basis. This allows for simultaneous preview of one field
and capture of the other field. Alternatively, Bt848/848A/849A is able to capture
both fields simultaneously or preview both fields simultaneously. The fields may
be interlaced into memory or sent to separate field buffers.
The Bt849A includes all the capability in the Bt848A and adds support for WST
decoding (the encoding method for European based Teletext). The Bt849A implements a significant amount of WST decoding in S/W ensuring a very lo w cost TV
card for use in locations requiring Teletext
See Table 1 for a comparison of the Bt848/848A/849A.
The Bt848/848A/849A fully supports the Intel Intercast technology.
Intel Intercast technology combines the rich programming of television and the
exciting world of the Internet on your PC. Imagine watching a news broadcast and
simultaneously getting a Web page providing a historical perspective. Or viewing
a music video and ordering tickets on the Internet for the band’s next appearance
in your area. Or enjoying a favorite sho w and getting special web pages associated
with that program. Now your PC can let you interact with television in all kinds of
new and exciting ways.
Brooktree
®
L848A_A
1
FUNCTIONAL DESCRIPTION
Functional Overview
Single-Chip Video Capture for PCI
Bt848/848A/849A
Table 1. PCI Video Decoder Product Family
Bt848 Bt848A Bt849A
Bt848A Analog Video and
Digital Camera Capture
Over the PCI Bus
Composite, S-Video multi-standard Video
Decoder and PCI bus master
Peaking, single crystal operation, digital camera
support
WST (Teletext) decoding support X
XXX
XX
The Bt848A provides support for digital cameras. The Bt848A includes a digital
camera port providing the ability to perform digital capture when a Bt848A is used
in the development of a video board product. The Bt848A is fully compatible with
the Bt848. The datasheet defines the registers and functionality required for implementing analog video capture support. In order to implement digital video interface, refer to the Digital Video section of the datasheet. Note the majority of the
register settings are identical for both analog and digital video support. The Digital
Video section identifies all changes, additional registers, all changes to the analog
register setting that are required in order to support digital video.
The Bt848A can accept digital video from a multitude of sources including the
Silicon Vision and Logitech video cameras. The digital stream is routed to the high
quality down scaler and color adjustment processing. It is then bus mastered into
system memory or displayed via the graphics frame buffer.
DMA Channels Bt848/848A/849A provides two DMA channels for the odd and even fields, each
controlled by a pixel instruction list. This instruction list is created by the Bt848
device driver and placed in the host memory. The instructions control the transfer
of pixels to target memory locations on a byte resolution basis. Complex clipping
can be accomplished by the instruction list, blocking the generation of PCI bus cycles for pixels that are not to be seen on the display.
The DMA channels can be programmed on a field basis to deliver the video data
in packed or planar format. In packed mode, YCrCb data is stored in a single continuous block of memory. In planar mode, the YCrCb data is separated into three
streams which are burst to different target memory blocks. Having the video data
in planar format is useful for applications where the data compression is accomplished via software and the CPU.
2
L848A_A
Brooktree
®
Bt848/848A/849A
Single-Chip Video Capture for PCI
FUNCTIONAL DESCRIPTION
Functional Overview
Figure 1. Bt848/848A/849A Detailed Block Diagram
PCI
Bus
FIFO Data MUX
Address Generator
DMA Controller PCI Initiator
FIFOs
Y: 70x36
Format
Cb: 35x36
MUX
Instruction
Cr: 35x36
Queue
# DWORDS
Instr Data
Wr
Local Registers
PCI
AD MUX
Controller
PCI T arget
PCI
Config
Bus
Parity Generator
Rd
Interrupts
Registers
GPIO
Input
(Digital Video
Bt848A & Bt849A
Only)
Video Data Format Converter
YCrCb 4:2:2, 4:1:1
Video
Video
Video
Analog
8-Bit Dither
CSC/Gamma
Scaler
Decoder
C Master
2
I
GPIO
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®
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FUNCTIONAL DESCRIPTION
Functional Overview
Figure 2. Bt848 Video Decoder and Scaler Block Diagram
(!)
SYNCDET
AGCCAP
REFOUT
MUXOUT
MUX0
MUX1
(2)
MUX2
MUX3
Single-Chip Video Capture for PCI
Bt848/848A/849A
XT1O
XT1I
XT0O
XT0I
and Brightness
Hue, Saturation,
Clocking
Adjust
Horizontal and
YREF+
YIN
YREF–
CLEVEL
CREF+
CIN
CREF–
Y
A/D
C
A/D
AGC and
Sync Detect
Oversampling
Low-Pass Filter
Y/C
Separation
Demod
Chroma
Notes: (1). Bt848 only.
(2). Bt848A and Bt849A only.
PCI Bus Interface Bt848/848A/849A is designed to efficiently utilize the available 132 MB/s PCI
bus. The 32-bit DWORDs are output on the PCI bus with the appropriate image
data under the control of the DMA channels. The video stream consumes bus
bandwidth with average data rates varying from 44 MB/s for full size 768x576
PAL RGB32, to 4.6 MB/s for NTSC CIF 320 x 240 RGB16, to 0.14 MB/s for
NTSC ICON 80 x 60 8-bit mode.
The pixel instruction stream for the DMA channels consumes a minimum of 0.1
MB/s. Achieving high performance throughput on PCI may be a problem with
slow targets and long bus access latencies. The Bt848/848A/849A provides the
means for handling the bandwidth bottlenecks that sometimes occur depending on
a particular system configuration. Bt848/848A/849A’s ability to gracefully degrade and to recover from FIFO overruns to the nearest pix el in real-time is the best
possible solution to these system bottlenecks.
and Scaling
Vertical Filtering
To FIFO Input Data Formatter
4
L848A_A
Brooktree
®
Bt848/848A/849A
Single-Chip Video Capture for PCI
FUNCTIONAL DESCRIPTION
Functional Overview
UltraLock The Bt848/848A/849A employs a proprietary technique known as UltraLock to
lock to the incoming analog video signal. It will always generate the required number of pixels per line from an analog source in which the line length can vary by as
much as a few microseconds. UltraLock’ s digital locking circuitry enables the V ideoStream decoders to quickly and accurately lock on to video signals, regardless of
their source. Since the technique is completely digital, UltraLock can recognize
unstable signals caused by VCR headswitches or an y other deviation, and adapt the
locking mechanism to accommodate the source. UltraLock uses nonlinear techniques which are difficult, if not impossible, to implement in genlock systems. And
unlike linear techniques, it adapts the locking mechanism automatically.
Scaling and Cropping The Bt848/848A/849A can reduce the video image size in both horizontal and ver-
tical directions independently using arbitrarily selected scaling ratios. The X and Y
dimensions can be scaled down to one-sixteenth of the full resolution. Horizontal
scaling is implemented with a six-tap interpolation filter while up to 5-tap interpolation is used for vertical scaling with a line store.
The video image can be arbitrarily cropped by reducing the number of active
scan lines and active horizontal pixels per line.
The Bt848/848A/849A supports a temporal decimation feature that reduces
video bandwidth by allowing frames or fields to be dropped from a video sequence
at fixed but arbitrarily selected intervals.
Input Interface Analog video signals are input to the Bt848/848A/849A via a three-input multi-
plexer that can select between three composite source inputs or between two composite and a single S-video input source. When an S-video source is input to the
Bt848/848A/849A, the luma component is fed through the input analog multiplexer, and the chroma component is fed directly into the C input pin. An automatic
gain control circuit enables the Bt848 to compensate for non-standard amplitudes
in the analog signal input. On the Bt848A and Bt849A there is an additional mux
input (providing a four-input multiplexer).
The clock signal interface consists of two pairs of pins for crystal connection
and two clock output pins. One pair of crystal pins is for connection to a 28.64
MHz (8*NTSC Fsc) crystal which is selected for NTSC operation. The other is for
P AL operation with a 35.47 MHz (8*PAL Fsc) crystal. Either fundamental or third
harmonic crystals may be used. Alternatively, CMOS oscillators may be used.
GPIO The Bt848/848A/849A provides a 24-bit general purpose I/O bus. This interface
can be used to input or output up to 24 general purpose I/O signals. Alternatively,
the GPIO port can be used as a means to input or output video decoder data. For example, the Bt848/848A/849A can input the video data from an external video decoder and bypass the Bt848/848A/849A’s internal video decoder block. Another
application is to output the video decoder data from the Bt848/848A/849A over the
GPIO bus for use by external circuitry.
Brooktree
®
L848A_A
5
FUNCTIONAL DESCRIPTION
Functional Overview
Single-Chip Video Capture for PCI
Bt848/848A/849A
Vertical Blanking Interval
Data Capture
2
I
C Interface The Bt848/848A/849A provides a two-wire Inter-Integrated Circuit (I2C) inter-
Bt848/848A/849A provides a complete solution for capturing and decoding Vertical Blanking Interval (VBI) data. The Bt848/848A/849A can operate in a VBI Line
Output Mode, in which the VBI data is only captured during select lines. This
mode of operation enables concurrent capture of VBI lines containing ancillary
data and normal video image data.
In addition, the Bt848/848A/849A supports a VBI Frame Output Mode, in
which every line in the video frame is treated as if it was a VBI line. This mode of
operation is designed for use with still frame capture/processing applications.
face. As an I
2
C master, Bt848/848A/849A can program other devices on the video
card, such as a TV tuner. Serial clock and data lines, SCL and SDA are used to
transfer data at a rate of 100 Kbits/s.
6
L848A_A
Brooktree
®
Bt848/848A/849A
Single-Chip Video Capture for PCI
FUNCTIONAL DESCRIPTION
Pin Descriptions
Pin Descriptions
Table 2 provides a description of pin functions, grouped by common function, Table 3 is a list of pin names in
pin-number order, and Figure 3 shows the pinout diagram.
NOTE:
Table 2. Pin Descriptions Grouped by Pin Function
Pins with alternate definitions on the Bt848A and Bt849A are indicated by shading
(1 of 6)
Pin # Pin Name I/O Signal Description
PCI Interface (50 pins)
11 CLK I Clock This input provides timing for all PCI transactions. All PCI sig-
nals except RST and INTA are sampled on the rising edge of
CLK, and all other timing parameters are defined with respect
to this edge. The Bt848 supports a PCI clock of up to
33.333333 MHz.
9 RST I Reset This input three-states all PCI signals asynchronous to the
CLK signal.
13 GNT I Grant Agent granted bus.
28 IDSEL I Initialization Device
Select
15–17,
20–24,
29–32,
35–38,
53–55,
58–62,
66–69,
72–75
AD[31:0] I/O Address/Data These three-state, bi-directional, I/O pins transfer both
This input is used to select the Bt848 during configuration
read and write transactions.
address and data information. A bus transaction consists of
an address phase followed by one or more data phases for
either read or write operations.
The address phase is the clock cycle in which FRAME
first asserted. During the address phase, AD[31:0] contains a
byte address for I/O operations and a DWORD address for
configuration and memory operations. During data phases,
AD[7:0] contains the least significant byte and AD[31:24] contains the most significant byte.
Read data is stable and valid when TRD
write data is stable and valid when IRD
transferred during the clocks when both TRD
asserted.
Y is asserted and
Y is asserted. Data is
Y and IRDY are
is
27, 39,
52, 65
Brooktree
[3:0] I/O Bus Com-
CBE
mand/Byte
Enables
®
These three-state, bi-directional, I/O pins transfer both bus
command and byte enable information. During the address
phase of a transaction, CBE
During the data phase, CBE
The byte enables are valid for the entire data phase and
determine which byte lanes carry meaningful data. CBE
refers to the most significant byte and CBE
least significant byte.
[3:0] contain the bus command.
[3:0] are used as byte enables.
[0] refers to the
L848A_A
[3]
7
FUNCTIONAL DESCRIPTION
Pin Descriptions
Single-Chip Video Capture for PCI
Bt848/848A/849A
Table 2. Pin Descriptions Grouped by Pin Function
Pin # Pin Name I/O Signal Description
51 PAR I/O Parity This three-state, bi-directional, I/O pin provides even parity
42 FRAME I/O Cycle Frame This sustained three-state signal is driven by the current
43 IRDY I/O Initiator Ready This sustained three-state signal indicates the bus master’s
(2 of 6)
across AD[31:0] and CBE
of 1’s on PAR, AD[31:0], and CBE
ber.
PAR is stable and valid one clock after the address phase.
For data phases, PAR is stable and valid one clock after
either TRD
write. Once valid, PAR remains valid until one clock after the
completion of the current data phase. PAR and AD[31:0] have
the same timing, but PAR is delayed by one clock. The target
drives PAR for read data phases; the master drives PAR for
address and write data phases.
master to indicate the beginning and duration of an access.
FRAME
tion. Data transfer continues throughout assertion. At deassertion, the transaction is in the final data phase.
readiness to complete the current data phase.
and TRD
clock. During a read, IRD
ready to accept data. During a write, IRD
initiator has placed valid data on AD[31:0]. Wait cycles are
inserted until both IRD
Y is asserted on a read or IRDY is asserted on a
is asserted to signal the beginning of a bus transac-
Y is used in conjunction with TRDY. When both IRDY
IRD
Y are asserted, a data phase is completed on that
[3:0]. This means that the number
[3:0] equals an even num-
Y indicates when the initiator is
Y indicates when the
Y and TRDY are asserted together.
44 TRDY I/O Target Ready This sustained three-state signal indicates the target’s readi-
ness to complete the current data phase.
Y is used in conjunction with TRDY. When both IRDY
IRD
and TRD
clock. During a read, TRD
senting data. During a write, TRD
is ready to accept the data. Wait cycles are inserted until both
IRD
45 DEVSEL I/O Device Select This sustained three-state signal indicates device selection.
When actively driven, DEVSEL
has decoded its address as the target of the current access.
46 STOP I/O Stop This sustained three-state signal indicates the target is
requesting the master to stop the current transaction.
49 PERR I/O Parity Error Report data parity error.
14 REQ O Request Agent desires bus.
8 INTA O Interrupt A This signal is an open drain interrupt output.
50 SERR O System Error Report address parity error. Open drain.
See PCI Specification 2.1 for further documentation
Y are asserted, a data phase is completed on that
Y indicates when the target is pre-
Y indicates when the target
Y and TRDY are asserted together.
indicates the driving device
8
L848A_A
Brooktree
®
Bt848/848A/849A
Single-Chip Video Capture for PCI
FUNCTIONAL DESCRIPTION
Pin Descriptions
Table 2. Pin Descriptions Grouped by Pin Function
Pin # Pin Name I/O Signal Description
General Purpose I/O (27 pins)
82–89,
92–99,
110–117
119 GPINTR I GP Interrupt GP port requests an interrupt. Internally pulled up to VDDG.
118 GPWE I GP Write Enable GP port write enable for registered inputs. Internally pulled up
GPIO[23:0] I/O General Purpose
I/O
GPIO[23]
GPIO[22]
GPIO[21]
GPIO[20]
GPIO[19]
GPIO[18]
GPIO[17]
GPIO[16]
GPIO[9]
GPIO[8]
GPIO[7:0]
O
Clkx1
O
Field
O
Vactive
O
Vsync
O
Hactive
O
Hsync
O
Composite Active
O
Composite Sync
I
Vsync/Field
I
Hsync
I
Video Data Input at
GPCLK = CLKX2
rate
(3 of 6)
24 bits of programmable I/O. These pins are internally pulled
up to VDDG.
Bt848A and Bt849A pin decoding when in digital video input
and SPI mode.
to VDDG.
108 GPCLK I/O GP Clock Video clock. Internally pulled up to VDDG.
Input Stage (14 pins)
141 MUX0 I Analog composite video inputs to the on-chip input multi143 MUX1 I
145 MUX2 I
139 MUXOUT O The analog video output of the 3 to 1 multiplexer. Must con-
138 YIN I The analog composite or luma input to theY-ADC.
154 CIN I The analog chroma input to the C-ADC.
147 SYNCDET I The sync stripper input used to generate timing information
MUX3 I In the Bt848A and Bt849A the SYNCDET is not required and
131 AGCCAP A The AGC time constant control capacitor node. Must be con-
plexer. Used to select between three composite sources or
two composite and one S-video source. Unused pins should
be connected to ground.
nect to the YIN pin.
for the AGC circuit. Must be connected through a 0.1 µF
capacitor to the same source as the Y-ADC. A 1 MΩ bleeder
resistor should be connected to ground.
is used as a fourth mux input.
Analog composite video inputs to the on-chip input multiplexer. Used to select between three composite sources or
two composite and one S-video source. Unused pins should
be connected to ground.
nected to a 0.1 µF capacitor to ground.
Brooktree
®
L848A_A
9
FUNCTIONAL DESCRIPTION
Pin Descriptions
Single-Chip Video Capture for PCI
Bt848/848A/849A
Table 2. Pin Descriptions Grouped by Pin Function
Pin # Pin Name I/O Signal Description
133 REFOUT O Output of the AGC which drives the YREF+ and CREF+ pins.
REFOUT O In the Bt848Aand Bt849A, the external 30 K, 30 K, and 2 K
137 YREF+ I The top of the reference ladder of the Y-ADC. This should be
150 YREF– I The bottom of the reference ladder of the Y-ADC. This should
151 CREF+ I The top of the ref erence ladder of the C-ADC. This should be
157 CREF– I The bottom of the reference ladder of the C-ADC . This should
158 CLEVEL I An input to provide the DC level reference for the C-ADC.
CLEVEL I In the Bt848A and Bt849A, this input is internally generated.
(4 of 6)
resistors are not required. However, the 0.1 µF capacitor
ground to GND is still needed (see Figure 25).
connected to REFOUT.
be connected to analog ground (AGND).
connected to REFOUT.
be connected to analog ground (AGND).
This voltage should be one half of CREF+.
No external components are required.
2
C Interface (2 pins)
I
78 SCL I/O Serial Clock Bus clock, output open drain.
79 SDA I/O Serial Data Bit Data or Acknowledge, output open drain.
Video Timing Clock Interface (5 pins)
102 XT0I A Clock Zero pins. A 28.636363 MHz (8*Fsc) fundamental (or
103 XT0O A
XT0I A In the Bt848A and Bt849A, this is the only clock source
XT0O A
105 XT1I A Clock One pins. A 35.468950 MHz (8*Fsc) fundamental (or
106 XT1O A
third harmonic) crystal can be tied directly to these pins, or a
single-ended oscillator can be connected to XT0I. CMOS
level inputs must be used. This clock source is selected for
NTSC input sources. When the chip is configured to decode
PAL but not NTSC (and therefore only one clock source is
needed), the 35.468950 MHz source is connected to this port
(XT0).
required to decode all video formats. If only one source is
used the frequency must be 28.636363 MHz (50 ppm) and a
series resistor must be added to the layout. Alternatively, the
Bt848A and Bt849A may be configured exactly as the Bt848
(using 28.636363 and 35.468950 MHz sources).
third harmonic) crystal can be tied directly to these pins, or a
single-ended oscillator can be connected to XT1I. CMOS
level inputs must be used. This clock source is selected for
PAL input sources. If either NTSC or PAL is being decoded,
and therefore only XT0I and XT0O are connected to a crystal,
must
XT1I should be tied either high or low, and XT1O
floating.
be left
10
L848A_A
Brooktree
®
Bt848/848A/849A
Single-Chip Video Capture for PCI
FUNCTIONAL DESCRIPTION
Pin Descriptions
Table 2. Pin Descriptions Grouped by Pin Function
Pin # Pin Name I/O Signal Description
104 NUMXTAL I Crystal Format Pin. This pin is set to indicate whether one or
3 TCK I Test clock. Used to synchronize all JTAG test structures.
5 TMS I Test Mode Select. JTAG input pin whose transitions drive the
7 TDI I Test Data Input. JTAG pin used for loading instructions to the
6 TDO O Test Data Output. JTAG pin used for verifying test results of
(5 of 6)
two crystals are present so that the Bt848 can select XT1 or
XT0 as the default in auto format mode. A logical zero on this
pin indicates one crystal is present. A logical one indicates
two crystals are present. This pin is internally pulled up to
VDDG.
JTAG (5 pins)
When JTAG operations are not being performed, this pin
must be driven to a logical low.
JTAG state machine through its sequences. When JTAG
operations are not being performed, this pin must be left floating or tied high.
TAP controller or for loading test vector data for boundary-scan operation. When JTAG operations are not being
performed, this pin must be left floating or tied high.
all JTAG sampling operations. This output pin is active for
certain JTAG operations and will be three-stated at all other
times.
2 TRST I Test Reset. JTAG pin used to initialize the JTAG controller.
This pin is tied low for normal device operation. When pulled
high, the JTAG controller is ready for device testing.
Note:
Not all PCs drive the PCI bus TRST pin. In these
pin on the Bt848 board is connected
1, 18, 40,
63, 81,
101, 120
130, 134,
136, 148,
152, 156
10, 25,
33, 47,
56, 70, 76
computers, if the TRST
to TRST
power up in an undefined state. In these designs, the TRST
pin on the Bt848 card must be tied low (disabling JTAG).
Power & Ground (57 pins)
VDD +5V P Power supply for digital circuitry. All VDD pins must be con-
nected together as close to the device as possible. A 0.1 µF
capacitor should be connected between each group of VDD
pins and the ground plane as close to the device as possible.
VAA +5V
VPOS +5V
VDDP
PCI VIO
P Power supply for analog circuitry. All VAA pins and VPOS
must be connected together as close to the device as possible. A 0.1 µF ceramic capacitor should be connected
between each group of VAA pins and the ground plane as
close to the device as possible.
P P o w er supply for PCI bus signals. A 0.1 µF ceramic capacitor
should be connected between the VDDP pins and the ground
plane as close to the device as possible.
on the PCI bus (which is not driven) the Bt848 may
Brooktree
®
L848A_A
11
FUNCTIONAL DESCRIPTION
Pin Descriptions
Single-Chip Video Capture for PCI
Bt848/848A/849A
Table 2. Pin Descriptions Grouped by Pin Function
Pin # Pin Name I/O Signal Description
90, 109,
123
12, 19,
26, 34,
41, 48,
57, 64,
71, 77,
80, 91,
100, 107,
121, 122,
160
132, 135,
140, 142,
144, 146,
149, 153,
155, 159
4 PVREF A This pin should be connected to GND (this reference signal
VDDG +5V P Power supply for GPIO port signals. A 0.1 µF ceramic capac-
GND G Ground for digital circuitry. All GND pins must be connected
AGND,
VNEG
G Ground for analog circuitry. All AGND pins and VNEG must
(6 of 6)
itor should be connected between the VDDG pins and the
ground plane as close to the device as possible.
together as close to the device as possible.
be connected together as close to the device as possible.
may be connected to the +3.3 V pin on the PCI bus, even if
the PCI bus does not supply 3.3 V).
124–129 N/C No connect Reserved
GPX[5:0] I/O Remapped from
GPIO [5:0]
I/O Column Legend:
I = Digital Input
O = Digital Output
I/O = Digital Bidirectional
A = Analog
G = Ground
P = Power
These pins are remapped on the Bt848A and Bt849A to provide the same functionality as on the Bt848 but on a different
pin.
12
L848A_A
Brooktree
®
Bt848/848A/849A
Single-Chip Video Capture for PCI
Pin Assignments
Figure 3. Bt848/848A/849A Pinout Diagram
GND
AGND
CLEVEL
CREF–
VAA
AGND
CIN
AGND
VAA
CREF+
YREF–
AGND
VAA
SYNCDET (MUX3)
AGND
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
1
VDD
TCK
TMS
TDO
TDI
INT
RST
CLK
GNT
VDD
VDD
2
3
4
5
6
7
8
A
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
[3]
27
28
29
30
31
32
33
34
35
36
37
38
[2]
39
40
48
47
46
45
44
43
42
41
Bt848/848A/849A
55
54
53
52
51
50
49
TRST
PVREF
VDDP
GND
REQ
AD[31]
AD[30]
AD[29]
GND
AD[28]
AD[27]
AD[26]
AD[25]
AD[24]
VDDP
GND
CBE
IDSEL
AD[23]
AD[22]
AD[21]
AD[20]
VDDP
GND
AD[19]
AD[18]
AD[17]
AD[16]
CBE
MUX2
AGND
144
145
57
56
MUX1
AGND
142
143
59
58
MUX0
AGND
140
141
61
60
MUXOUT
YIN
YREF+
137
138
139
64
63
62
VAA
136
65
AGND
135
66
VAA
REFOUT
133
134
68
67
VNEG
AGCCAP
131
132
70
69
VPOS
N/C (GPX0)
N/C (GPX1)
128
129
130
73
72
71
N/C (GPX2)
N/C (GPX3)
N/C (GPX4)
N/C (GPX5)
124
125
126
127
77
76
75
74
VDDG
GND
122
123
79
78
FUNCTIONAL DESCRIPTION
Pin Assignments
GND
121
120
VDD
119
GPINTR
118
GPWE
117
GPIO[0]
116
GPIO[1]
115
GPIO[2]
GPIO[3]
114
GPIO[4]
113
GPIO[5]
112
GPIO[6]
111
GPIO[7]
110
VDDG
109
GPCLK
108
GND
107
XT1O
106
XT1I
105
NUMXTAL
104
XT0O
103
XT0I
102
VDD
101
GND
100
GPIO[8] (HSYNC)
99
GPIO[9] (VSYNC/FIELD)
98
GPIO[10]
97
GPIO[11]
96
GPIO[12]
95
GPIO[13]
94
GPIO[14]
93
GPIO[15]
92
GND
91
VDDG
90
GPIO[16] (Composite SYNC)
89
GPIO[17] (Composite ACTIVE)
88
GPIO[18] (HSYNC)
87
GPIO[19] (HACTIVE)
86
GPIO[20] (VSYNC)
85
GPIO[21] (VACTIVE)
84
GPIO[22] (FIELD)
83
GPIO[23] (CLKX1)
82
VDD
81
80
GND
FRAME
IRDY
TRDY
DEVSEL
STOP
GND
VDDP
PERR
SERR
PAR
CBE
AD[15]
AD[14]
VDDP
AD[13]
GND
AD[12]
AD[11]
AD[10]
AD[9]
AD[8]
VDD
GND
[1]
Note: Bt848A and Bt849A pin alternate definitions indicated in ().
Brooktree
®
L848A_A
[0]
CBE
AD[7]
AD[6]
AD[5]
AD[4]
GND
VDDP
AD[3]
AD[2]
AD[1]
AD[0]
GND
VDDP
SCL
SDA
GND
13
FUNCTIONAL DESCRIPTION
Pin Assignments
Table 3. Bt848 Pin List
Single-Chip Video Capture for PCI
Bt848/848A/849A
Pin
#
1 VDD 33 VDDP 65 CBE
2 TRST 34 GND 66 AD[7] 98 GPIO[9]
3 TCK 35 AD[19] 67 AD[6] 99 GPIO[8]
Pin
Name
Pin
#
Pin
Name
Pin
#
Pin
Name
Pin
#
Pin
Name
Pin
#
[0] 97 GPIO[10] 129 N/C
(1)
(1)
130 VPOS
131 AGCCAP
Pin
Name
(1)
4 PVREF 36 AD[18] 68 AD[5] 100 GND 132 VNEG
5 TMS 37 AD[17] 69 AD[4] 101 VDD 133 REFOUT
6 TDO 38 AD[16] 70 VDDP 102 XT0I 134 VAA
7 TDI 39 CBE[2] 71 GND 103 XT0O 135 AGND
8 INTA 40 VDD 72 AD[3] 104 NUMXTAL 136 VAA
9 RST 41 GND 73 AD[2] 105 XT1I 137 YREF+
10 VDDP 42 FRAME 74 AD[1] 106 XT1O 138 YIN
11 CLK 43 IRDY 75 AD[0] 107 GND 139 MUXOUT
12 GND 44 TRDY 76 VDDP 108 GPCLK 140 AGND
13 GNT 45 DEVSEL 77 GND 109 VDDG 141 MUX0
14 REQ 46 STOP 78 SCL 110 GPIO[7] 142 AGND
15 AD[31] 47 VDDP 79 SDA 111 GPIO[6] 143 MUX1
16 AD[30] 48 GND 80 GND 112 GPIO[5] 144 AGND
17 AD[29] 49 PERR 81 VDD 113 GPIO[4] 145 MUX2
18 VDD 50 SERR 82 GPIO[23]
19 GND 51 PAR 83 GPIO[22]
20 AD[28] 52 CBE[1] 84 GPIO[21]
21 AD[27] 53 AD[15] 85 GPIO[20]
22 AD[26] 54 AD[14] 86 GPIO[19]
23 AD[25] 55 AD[13] 87 GPIO[18]
24 AD[24] 56 VDDP 88 GPIO[17]
25 VDDP 57 GND 89 GPIO[16]
(1)
114 GPIO[3] 146 AGND
(1)
115 GPIO[2] 147 SYNCDET
(1)
116 GPIO[1] 148 VAA
(1)
117 GPIO[0] 149 AGND
(1)
118 GPWE 150 YREF–
(1)
119 GPINTR 151 CREF+
(1)
120 VDD 152 VAA
(1)
121 GND 153 AGND
26 GND 58 AD[12] 90 VDDG 122 GND 154 CIN
27 CBE[3] 59 AD[11] 91 GND 123 VDDG 155 AGND
28 IDSEL 60 AD[10] 92 GPIO[15] 124 N/C
29 AD[23] 61 AD[9] 93 GPIO[14] 125 N/C
30 AD[22] 62 AD[8] 94 GPIO[13] 126 N/C
31 AD[21] 63 VDD 95 GPIO[12] 127 N/C
32 AD[20] 64 GND 96 GPIO[11] 128 N/C
(1)
(1)
(1)
(1)
(1)
156 VAA
157 CREF–
158 CLEVEL
159 AGND
160 GND
(1)
Notes: (1). Alternate pin definitions on Bt848A and Bt849A.
14
L848A_A
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Bt848/848A/849A
Single-Chip Video Capture for PCI
The Challenge The line length (the interval between the midpoints of the falling edges of succeed-
FUNCTIONAL DESCRIPTION
UltraLock
UltraLock
ing horizontal sync pulses) of analog video sources is not constant. For a stable
source such as studio quality source or test signal generators, this variation is very
small: ±2 ns. However, for an unstable source such as a VCR, laser disk player, or
TV tuner, line length variation is as much as a few microseconds.
Digital display systems require a fixed number of pixels per line despite these
variations. The Bt848 employs a technique known as UltraLock to implement
locking to the horizontal sync and the subcarrier of the incoming analog video signal and generating the required number of pixels per line.
Operation Principles of
UltraLock
UltraLock is based on sampling using a fixed-frequency, stable clock. Since the
video line length will vary , the number of samples generated using a fixed-frequency sample clock will also vary from line to line. If the number of generated samples
per line is always greater than the number of samples per line required by the particular video format, the number of acquired samples can be reduced to fit the required number of pixels per line.
The Bt848 requires an 8*Fsc (28.64 MHz for NTSC and 35.47 MHz for PAL)
crystal or oscillator input signal source. The 8*Fsc clock signal, or CLKx2, is divided down to CLKx1 internally (14.32 MHz for NTSC and 17.73 MHz for PAL).
CLKx2 and CLKx1 are internal signals and are not made available to the system.
UltraLock operates at CLKx1 although the input waveform is sampled at CLKx2
then low pass filtered and decimated to CLKx1 sample rate.
At a 4*Fsc (CLKx1) sample rate there are 910 pixels for NTSC and 1,135 pixels
for PAL/SECAM within a nominal line time interval (63.5 µs for NTSC and 64 µs
for PAL/SECAM). For square pixel NTSC and PAL/SECAM formats, there
should only be 780 and 944 pixels per video line, respectively. This is because the
square pixel clock rates are slower than a 4*Fsc clock rate, i.e., 12.27 MHz for
NTSC and 14.75 MHz for PAL.
UltraLock accommodates line length variations from nominal in the incoming
video by always acquiring more samples, at an effective 4*Fsc rate, than are required by the particular video format and outputting the correct number of pixels
per line. UltraLock then interpolates the required number of pixels in a way that
maintains the stability of the original image despite variation in the line length of
the incoming analog waveform.
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FUNCTIONAL DESCRIPTION
UltraLock
Single-Chip Video Capture for PCI
Bt848/848A/849A
The example illustrated in Figure 4 shows three successive lines of video being
decoded for square pixel NTSC output. The first line is shorter than the nominal
NTSC line time interval of 63.5 µs. On this first line, a line time of 63.2 µs sampled
at 4*Fsc (14.32 MHz) generates only 905 pixels. The second line matches the
nominal line time of 63.5 µs and provides the expected 910 pixels. Finally, the
third line is too long at 63.8 µs within which 913 pixels are generated. In all three
cases, UltraLock outputs only 780 pixels.
Figure 4. UltraLock Behavior for NTSC Square Pixel Output
Analog
Waveform
Line
Length
Pixels
Per Line
Pixels
Sent to
the FIFO
by
UltraLock
63.2 µs
905 pixels
780 pixels
63.5 µs
910 pixels
780 pixels
63.8 µs
913 pixels
780 pixels
UltraLock can be used to extract any programmable number of pixels from the
original video stream as long as the sum of the nominal pixel line length (910 for
NTSC and 1,135 for PAL/SECAM) and the worst case line length variation from
nominal in the active region is greater than or equal to the required number of output pixels per line, i.e.,
P
where: P
Nom
+P
NomPVar
= Nominal number of pixels per line at 4*Fsc sample rate
≥
Desired
(910 for NTSC, 1,135 for PAL/SECAM)
P
= Variation of pixel count from nominal at 4*Fsc (can be a
Var
positive or negative number)
P
= Desired number of output pixels per line
Desired
16
It should be noted that, for stable inputs, UltraLock guarantees the time between
the falling edges of HRESET only to within one pixel. UltraLock does, however,
guarantee the number of active pixels in a line as long as the above relationship
holds.
L848A_A
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Bt848/848A/849A
Single-Chip Video Capture for PCI
FUNCTIONAL DESCRIPTION
Composite Video Input Formats
Composite Video Input Formats
Bt848 supports several composite video input formats. Table 4 shows the different
video formats and some of the countries in which each format is used.
Table 4. Video Input Formats Supported by the Bt848
Format Lines Fields F
NTSC-M 525 60 3.58 MHz
NTSC-Japan
PAL-B 625 50 4.43 MHz
PAL-D 625 50 4.43 MHz
PAL-G 625 50 4.43 MHz
PAL-H 625 50 4.43 MHz
PAL-I 625 50 4.43 MHz
PAL-M 525 60 3.58 MHz
PAL-N Combination 625 50 3.58 MHz
PAL-N 625 50 4.43 MHz
SECAM 625 50 4.43 MHz
Notes:(1). NTSC-Japan has 0 IRE setup.
(1)
525 60 3.58 MHz
SC
The video decoder must be programmed appropriately for each of the composite video input formats. Table 5 lists the register values that need to be programmed
for each input format.
L848A_A
17
FUNCTIONAL DESCRIPTION
Composite Video Input Formats
Table 5. Register Values for Video Input Formats
Single-Chip Video Capture for PCI
Bt848/848A/849A
Register Bit NTSC-M NTSC-Japan
IFORM
(0x01)
XTSEL
[4:3]
FORMAT
01 01 10 01 10 01 10
001 010 011 100 101 111 110
PAL-B, D,
G, H, I
PAL-M PAL-N
PAL-N
Combination
SECAM
[2:0]
Cropping:
HDELAY,
VDELAY,
VACTIVE,
[7:0] in all
five
registers
Set to desired
cropping
values in
registers
Set to NTSC-M
square pixel
values
Set to desired
cropping
values in
registers
Set to NTSC-M
square pixel
values
Set to PAL-B, D, G, H, I square pixel
values
CROP
HSCALE
[15:0] 0x02AC 0x02AC 0x033C 0x02AC 0x033C 0x033C
(1)
0x033C
(0x08,
0x09)
ADELAY
[7:0] 0x68 0x68 0x7F 0x68 0x7F 0x7F 0x7F
(0x18)
BDELAY
[7:0] 0x5D 0x5D 0x72 0x5D 0x72 0x72 tbd
(0x19)
Notes: (1). The Bt848A and Bt849A will not output square pixel resolution for PAL N-combination. A smaller number of pixels
must be output.
18
L848A_A
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Bt848/848A/849A
Single-Chip Video Capture for PCI
Y/C Separation and Chroma Demodulation
Y/C separation and chroma decoding are handled as shown in Figure 5. Bandpass
and notch filters are implemented to separate the composite video stream. The filter responses are shown in Figure 6. The optional chroma comb filter is implemented in the vertical scaling block. See the Video Scaling, Cropping, and
Temporal Decimation section in this chapter.
Figure 7 schematically describes the filtering and scaling operations.
In addition to the Y/C separation and chroma demodulation illustrated in
Figure 5, the Bt848 also supports chrominance comb filtering as an optional filtering stage after chroma demodulation. The chroma demodulation generates baseband I and Q (NTSC) or U and V (PAL/SECAM) color difference signals.
For S-Video operation, the digitized luma data bypasses the Y/C separation
block completely, and the digitized chrominance is passed directly to the chroma
demodulator.
For monochrome operation, the Y/C separation block is also bypassed, and the
saturation registers (SAT_U and SAT_V) are set to zero.
Figure 5. Y/C Separation and Chroma Demodulation for Composite Video
Y/C Separation and Chroma Demodulation
FUNCTIONAL DESCRIPTION
Composite
Notch Filter
Band Pass Filter
Y
U
Low Pass Filter
sin
V
Low Pass Filter
cos
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FUNCTIONAL DESCRIPTION
Y/C Separation and Chroma Demodulation
Figure 6. Y/C Separation Filter Responses
Single-Chip Video Capture for PCI
Bt848/848A/849A
Luma Notch Filter Frequency Responses for NTSC and PAL/SECAM
Figure 7. Filtering and Scaling
Horizontal Scaler
Luminance
ABZ1–CZ2–DZ3–EZ4–FZ
+++++=
Chrominance GHZ
NTSC
PAL/SECAM
1–
+=
Chroma Band Pass Filter Frequency Responses for NTSC and PAL/SECAM
NTSC
Vertical Scaler
5–
Luminance CDZ
Chrominance
+=
1
-- 2
1
-- -Z1–+=
2
PAL/SECAM
1–
(Chroma Comb)
Vertical Filter Options
Luminance
Optional
Y Y
3 MHz
Horizontal
Low Pass
Filter
C
6 Tap, 32 Phase
Interpolation
and
Horizontal
Scaling
2 Tap, 32 Phase
Interpolation
and
Horizontal
Scaling
1
-- -1 z1–+()=
2
1
-- -1 2
4
1
-- -1 3
8
1
------ 1 4
16
1–
Z
++()=
Z
+++()=
Z
++++()=
2–
1Z
1–
3Z2–1Z
1–
6 Z2–4 Z
On-chip Memory
On-chip Memory
3–
3–
4–
Z
Luma Comb
Vertical Scaling
Vertical Filtering
Chroma Comb
and
Vertical Scaling
C
Note: Z–1 refers to a pixel delay in the horizontal direction, and a line delay in the vertical direction. The coefficients
are determined by UltraLock and the scaling algorithm
20
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