Computime CTL3575 User Manual

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n supersede ing the infor

Rev.3

All informatio s and replac

ation descri

and data

s all informati

ed in this

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Revision

Rev.

1

2

3

Date

(

D-MM-YYY

21-01-201 05-08-201 08-06-201

nsceiver M

dule CTL3

85_CTL35

Hist

5

ry

)

First Re Change Add CT

leased d the PCB si

3575 in the

e, Power sett

RD

ings and etc.

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mited. All r

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Rev. 3

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85_CTL35

5

Table

1.

 Gen

2.Appli

3.

 Feat

4.Abso

5.

 Rec

6. Elect

7.

 Typi

8. Pin

9. Pin

10. Bl

11. R

12. P

13. M

of Con

ral Descript

cations .......

res ............

lute Maximu

mmended

rical Specifi

al applicati ssignment .. escription .. ck Diagram Frequency B Layout R chanical Di

tents

on ...............

...................

m Ratings ...

perating Co

ations .........

n block .......

...................

Detail ..........

commenda

ensions .....

...................

nditions ......

...................

ions ............

...................

....................

.. 1 .. 1 .. 1 .. 2 .. 2 .. 2 .. 3 .. 4 .. 5 .. 9 10 11 12

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85_CTL35

5

1. Gen

The CTL specially IEEE 80

24.5 x 1 network and inte powerful

2. App

Ho

automa

building

3. Feat

ral Desc

3585/CTL

designed

.15.4 sta

x 2.8 mm

processor

rated RA

software d

ications

e

ion &

ontrol

ures

iption

575 are co or Ember

dard in th It integrat

(ARM Cort

for prog

bugging a

Home

ppliances

alarms

mpact surf

igBee™ p

2.4GHz d a 2.4G x-M3 Pro

am and d

nd progra

Monit

re

sys

ce mount

otocol sta

orld-wide

z, IEEE 80

essor) to

ta storag

ming of th

ring of ote

tems

d High Po k for wirel

ISM band.

2.15.4-200 un Ember . It utilize

network p

Securit

systems

lighting

control

er Wireles

ss networ

The size

complian

Net. It co s the nonrocessor.

Se

ca

e

RF Trans

s, EmberZ

f CTL358

transceiv

tains emb

intrusive S

sor data

pture in

bedded tworks

ceiver Mod

et, based

(CTL3575

r with a 32

dded FLA

IF module

ule

on is bit

H

for

 Com  Integ  Non-

rated IEEE

intrusive d

 SPI i

(EZS

P)

 Inter  High  16 c  On-c

performan

annels in t

hip regulat

 Thre  32-bi  256  128  +20d

t ARM® C

B or 512K B or 192K

Bm Max. tr

 -100  Smal  Extr

l footprint:

mely low

lete ZigB

terface fo

al RC osci

deep low

Bm sensiti

e-ready m

802.15.4 bug interfa

communi

llator for ti

e direct se

e 2.4 GH

r for 2.1-3.

power mo

rtex™-M3

FLASH,w

FLASH,w ansmissio vity

4.5x17x2.

eep Sleep

dule with i

HY and M ce (SIF) ation and

er quence sp ISM band 6V operati

es processo ith optional ith optional

power

mm

Current.

tegrated

C layer

ontrolled b

ead spectr

n.

read prote read prote

CB antenn

the Host

m (DSSS)

tion and 3 tion and 1

sing the E

RF transc

or 64KB KB RAM(

berZNet

iver

AM(CTL3 TL3575)

erial Prot

85)

col

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nsceiver M

imum Ra

dule CTL3

ings

85_CTL35

5

Regulatorinp Voltageon a

PC[7:0]),SW

Voltageon a PB7, PC1), general pur range select

Voltageon O

Storage tem

5. Rec

Regulator in Operating te

Parame

tvoltage(VD

yGPIO (PA[

LK,nRESET

yGPIO pin (

hen used ose ADC

d

CA,OSCB,

erature

mmende

Paramet

ut voltage (V

perature ran

er

_PADS) :0], PB[7:0],

VREG_OUT

A4, PA5, PB

s an input

with thelo

C

d Operati

D_PADS)

ge

, PB6,

tothe

oltage

ng Condi

ions

Test Co

Test C

nditions

Mi

. Ma

-0.3

VDD_

-0.3

2.

-0.3

VDD_P

-40

Min

. Typ.

2.1

-40

. Uni

+3

6 V

ADS

3

V

DSA3 V

+0

+85

Max. Uni

°C

3.6 V

+85 °C

V

Moisture Sen

6. Elec

T=25℃, V

Parameter

RF Operatin

Number of c Channel spa Frequency s

Transmit po

Sensitivity

Adjacent ch

sitivity Level(

trical Spe

C = 3.0V, F

frequency

annels

ing

ability

er

nnel rejection

SL)

cification

=2450MHz,

+/-5 MHz

+/-10 MHz

f nothing els

Con

Prog steps

For I For I

Prog PER

defin mod

IEEE dBm

stated.

ition / Note

ammable in

for IEEE 802

EE 802.15.4 EE 802.15.4

ammable fro

= 1% PE

d by IEE

802.15.4

MHz steps,

.15.4 complia

compliance compliance

firmware , 20byte

802.15.4

ompliance a

Min

Typ.

MHz

nce

acket

Boost

t -82

2.4

MSL3

16

5

-100

35/35

40/40

Max Uni

2.5 GH

MH

/-40 ppm

+20 dB

dB

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ed.

Re

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CGNJTCPC

SPAPA

5

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7

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6

F

A

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k

v

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dule CTL3

85_CTL35

5

Parameter

Supply volta Current cons

RX mode

Current cons TX mode

Deep sleep

Flash Memo

MCU clock f MCU Low S

7. Typi

e

umption,

urrent

y

equency

eed Clock

cal appli

ation blo

k

Con

ition / Note

Max

FLA

H memory in

FLA

H memory in

Exter

nal crystal

clock

X sensitivity

EM3585 EM357

r Ext 32.7

8KHz

Min

2.1

Typ.

30

150

2.8

512 192

24

32.768

Max Unit

3.6 V

mA

mA uA

KB KB MH

KHz

HOST

MCU

Debug and

programmin

interface

VDD_P

VB

D 2 0

P

3

D

g

K 4

NRE

ET 4 5

Fi

gure 1: E

ample of

CT

CTL

M

L3585/

575 R

odule

pplication

DS=2.1- 3.6

circuit

LINK_ACTI

32.768

VITY

Hz

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mputime L

mited. All r

ights reser

ed.

Re

. 3

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a

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9

o

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5

T

7

v

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ZigBee-

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nsceiver M

dule CTL3

85_CTL35

5

8. Pin

ssignm

nt

Pin 8

Pin 18

Pin 1

Pi

29

igure 2: C

L3585/C

L3575 pin

assignme

t

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mputime L

mited. All r

ights reser

ed.

Rev. 3

R

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a

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5

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7

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t

2

e

a

1

a

n

G

g

c

n

ZigBee-

eady RF Tr

nsceiver M

dule CTL3

85_CTL35

5

9. Pin

Moduel

Pin#

1

2

3

escripti

EM3585

EM357

Pin#

36

49

40

n

Name

PB0

VREF

IRQA

TRACECLK

TIM1CLK

TIM2MSK

GND

PC0

JRST

IRQD

TRACEDATA1

Direction

I/O

Analog O

Analog I

I

O

I

I/O High curre

I

O

Digital I/O

ADC refere

External int

Synchrono

Timer 1 ext

Timer 2 ext

t Digital I/O

JTAG rese

Default ext

Synchrono

nce output

nce input

errupt source A

s CPU trace clock

ernal clock input

ernal clock mask i

ither Enable with

input from debug

rnal interrupt sour

s CPU trace data

Descriptio

put

PIO_DBGCFG[5]

er

e D

bit 1

PB7

ADC2

4

5

41

42

IRQC

TIM1C2

PB6

ADC1

IRQB

TIM1C1

I/OHighcurren

Analog

I

O

1

I/O High curre

Analog

I

O

I

Digital I/O

ADC input

Default ext

Timer 1 ch

t Digital I/O

ADC input

External int

Timer 1 ch

rnal interrupt sour

nnel 2 output

nnel 2 input

errupt source B

nnel 1 output

nnel 1 input

e C

Copyrig

mputime L

mited. All r

ights reser

ed.

Rev. 3

R

h

E

a

o

i

m

K

V

X

S

K

5

o

g

r

h

t

7

v

t

x

z

7

p

h

e

h

S

e

i

X

t

w

n

o

t

i

F

ZigBee-

Moduel

Pin#

eady RF Tr

M3585/EM3

Pin#

nsceiver M

57

Pin Na

dule CTL3

e Directi

85_CTL35

n

5

Descript

on

10

11

12

PB5

ADC0

6

7

8

9

43

49

12

13

14

TIM2CL

TIM1CL

GND

nRESET

PC6

OSC32B

NTX_ACTI

PC7

OSC32A

OSC32_E

I

E O

T I

I/O

Analo

ADC inpu

I

I/O

Digital I/O

Timer 2 e

Timer 1 e

Active low

Digital I/O

32.768KH

Inverted T

Digital I/O

32.768KH

Digital 32.

0

ternal clock input

ternal clock mask

chip reset(internal

crystal oscillator.

_ACTIVE signal

crystal oscillator.

68KHz clock inpu

nput

pull-up)

source

13

14

15

16,23,28,37

18

19

VDD_PAD

PA7

TIM1C4

REG_EN

PB3

TIM2C3

SC1nCT

SC1SCL

S Powe

O

I

O

I

I/O Hig

curren

O

I

I/O

O

I

Pads sup

Digital I/O

Timer 1 c

External r

Digital I/O

Timer 2 c

UART CT

SPI mast

SPI slave

ly(2.1-3.6V)

Disable REG_EN

annel 4 output

annel 4 input

gulator open drai

annel 3 output

annel 3 input

handshake of Se

r clock of serial C

clock of serial Con

ith GPIO_DBGC

output

rial Controller 1

ntroller 1

roller 1

G [4]

Copyrig

mputime L

mited. All r

ights reser

ed.

Rev. 3

R

h

E

a

o

i

m

S

L

O

K

l

5

o

7

v

h

S

s

h

d

h

o

d

h

c

s

h

r

t

n

2

o

2

n

r

t

ZigBee-

eady RF Tr

nsceiver M

dule CTL3

85_CTL35

5

Moduel

Pin#

16

17

M3585/EM3

Pin#

20

21

57

Pin Na

PB4

TIM2C4

SC1nRT

SC1nSSE

PA0

TIM2C1

SC2MOS

PA1

TIM2C3

e Directi

O

I

I O

I I

I/O

n

Digital I/O

O

i

O

I

O

Timer 2 c

UART RT

SPI slave

Digital I/O

Timer 2 c

SPI maste

SPI slave

Digital I/O

Timer 2 c

annel 4 output

annel 4 input

handshake of se

elect of serial con

annel 1 output

annel 1 input

r data out of serial

ata in of serial co

annel 3 output

Descripti

ial controller 1

roller 1

controller 2

troller 2

on

18

19

20

22

24

25

TIM2C3

SC2SDA

SC2MIS

O

SC2MIS

I

PA2

TIM2C4

SC2SCL

O

SC2SCL

I

PA3

SC2Nsse

I

TIM2C2

I/O

I

O

I

O

I

Timer 2 c

TWI data

SPI slave

SPI maste

Digital I/O

Timer 2 c

TWI clock

SPI maste

SPI slave

Digital I/O

SPI slave

Timer 2 c

annel 3 input

f serial controller

ata out of serial c

r data in of serial c

annel 4 output

annel 4 input

of serial controller

r clock of serial co

lock of serial cont

elect of serial con

annel 2 output

annel 2 input

ntroller 2

troller 2

oller 2

roller 2

Copyrig

mputime L

mited. All r

ights reser

ed.

Rev. 3

R

h

E

a

o

i

m

T

A

D

T

O

A

O

D

5

g

t

7

v

t

o

t

a

d

o

t

h

e

o

n

h

e

h

c

e

a

n

r

a

o

1

c

n

c

g

u

i

s

ZigBee-

eady RF Tr

nsceiver M

dule CTL3

85_CTL35

5

Moduel

Pin#

21

22

23

M3585/EM3

Pin#

26

27

29

57

Pin Na

PA4

ADC4

PTI_EN

TRACEDA

PA5

ADC5

PTI_DAT

NBOOTMO

TRACEDA

PA6

TIM1C3

e Directi

A2 O

O

E I

A3 O

I/O

Analo

O

I/O

Analo

I/O Hig

curren

O

I

on

h

ADC inpu

Digital I/O

Frame sig

Synchron

Digital I/O

Data sign

Embedde

Synchron

Digital I/O

Timer 1 c

4

nal of packet trace

us CPU trace dat

5

l of packet trace i

serial bootloade

us CPU trace dat

annel 3 output

annel 3 input

Descript

interface

bit 2

terface

activation out of re

bit 3

on

et

24

25

30

31

PB1

SC1MIS

O

SC1MOS

I O

SC1SD

I/O

SC1TXD

O

TIM2C1

PB2

SC1MIS

I

SC1MOS

I I

SC1SCL

SC1RX

I

TIM2C2

I/O

Digital I/O

SPI slave

data out of serial c

SPI mast

TWI data

UART tra

O

I

O

I

Timer 2 c

Digital I/O

SPI mast

SPI slave

TWI clock

UART rec

Timer 2 c

r data out of serial

f serial controller

smit data of serial

annel 1 output

annel 1 input

r data in of serial

data in of serial co

of serial controller

ive data of serial

annel 2 output

annel 2 input

ntroller 1

controller 1

ontroller 1

troller 1

1

ontroller 1

JTCK

26

Copyrig

32

SWCLK

mputime L

mited. All r

I

I/O

ights reser

JTAG clo

Serial Wir

k input from debu

Clock input/outp

ed.

ger

t with debugger

Rev. 3

R

h

MM3

c

P

n

a

o

i

A

R

m

o

i

D

eZi

N

E

A

5

D

T

D

T

D

T

o

7

v

i

e

a

r

i

r

a

r

o

T

k

E

H

G

B

e

M

n

v

ZigBee-

Mod

uel

Pin#

eady RF Tr

E

3585/E

57 Pin#

nsceiver M

P

n Name

PC2

dule CTL3

irection

I/O

85_CTL35

escription

igital I/O Enable w

5

th GPIO_DBGCF

[5]

27

28

29

10. Blo

33

34

35

k Diagra

TR

T

JTDO

SWO

CEDATA0

PC3

JTDI

ACECLK

PC4

JTMS

SWDIO

O J

O S

I/O

I J

O S

I/O

I J

I/O S

AG data out to d

erial Wire Output

ynchronous CPU t

igital I/O Enable w

AG data in from d

ynchronous CPU t

igital I/O Either En

AG mode select f

erial Wire bidirecti

2.

1– 3.6V

bugger

synchronous trace

ace data bit3

th GPIO_DBGCF

ebugger

ace clock

ble with GPIO_D

om debugger

nal data to/from d

output to debugg

[5]

GCFG[5]

bugger

UART/S Commu

I/I2C

ication

32 Bit

Us

IEE

RM Process

rApplicati

on

gbeeTM

etwork

802.15.4

MAC

Figu

r

C

TL3585/C

re 3: Bloc

24M

IE

RF

z

E 802.15.4

Transceiver

L3575

Diagram

FE

PCB anten

a

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mited. All r

ights reser

ed.

Re

. 3

R

h

F

w

h

w

n

qEmb

BLNA

a

o

y

w

s

p

C

u

T

w

i

w

i

g

o

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R

C

d

L

5

T

m

o

T

A

7

v

d

h

R

w

d

1

~

N

E

c

H

o

h

l

4

r

u

k

2

n

f

t

6

0

N

v

w

ZigBee-

eady RF Tr

nsceiver M

dule CTL3

85_CTL35

5

11. RF

The follo

Note: t 2480M c

The use regulatio

2.4GHz I The follo

requenc

ing table

e output

hannel to

of RF freq

ns. The C

SM band.

ing table

Detail

hows the

ower of

omply F

encies an

L3585/CT

s the settin

F channel

11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

TL3585/C C require

maximu

3575 are c

g for the C

s as define

L3575 s

ent.

allowed

mplying

L3585 an

by the IE

Frequen

2405M 2410M 2415M 2420M 2425M 2430M 2435M 2440M 2445M 2450M 2455M 2460M 2465M 2470M 2475M 2480M

ould be c

F power s

ith the app

CTL3575

E 802.15.

y

z z z z z z z z z z z z z z z z

nfigured

ould acco

icable reg

to US mar

standard.

lower tha

ding to dif

lations for

et:

-24dBm

erent natio he world

for

nal ide

FCC

CH1

Cha

nel

Fre

The follo

(MHz) er settin

ing table

s the settin

g for the P

2405

-4dBm +

:

PA SETTI

ALL

OFF

RX

Y PASS

TX

Copyrig

mputime L

PB3

0

1

X

mited. All r

ights reser

~25

2475

o boost

GS

PC1

0

1

ed.

-

CH2

248

4dBm +

PC5

0

1

o boost

Re

. 3

R

h

B

e

a

n

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. 3

Computime CTL3575 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual