This manual is for anyone who services this system. It includes
troubleshooting information, configuration rules, and instructions for
removal and replacement of field-replaceable units.
Compaq Computer Corporat ion
Notice
The in fo rmatio n in this p ublication is subject to ch ange w ithout n otice.
COMPAQ COMPUTER CORPORATION SHALL NOT BE LIABLE FOR TECHNICAL
OR EDITORIAL ERRORS OR OMISSIONS CONTAINED HEREIN, NOR FOR
INCIDENTAL OR CONSEQUENTIAL DAMAGES RESULTING FROM THE
FURNISHING, PERFORMANCE, OR USE OF THIS MATERIAL.
This publication c ont ai ns in formation protecte d by copyright. No par t of this p ubl ic at ion may b e
photocopied or repr oduced in any form without prior written consent from Compaq Co mp ut er
Corporation.
The software desc ri bed i n th is do cument is furnished under a license agreement or
nondisclosure agr eement and may be used or copied only in acco rda nce with the terms of the
agreement.
Corporation. A lphaS erver, DIGITAL, OpenVMS, and StorageWorks are trademarks or
registered trademarks of Digital Equ ip me nt Corporation. Micros oft, Windows, and Windows
NT are registere d tr ademarks of Microsoft Corporat ion. U N IX is a regi stered tradem ar k in th e
U.S. and other countr ie s, licens ed exclusively through X/Open Company Ltd. Other produc t
names mentioned herein may be trademarks and/o r reg is tered trademarks of their respect iv e
companies.
Digital Equipmen t Corporation now ow ned by C ompaq Compu ter Co rporation.
FCC Notice: The equipment described in thi s ma nual generates, use s, and may emit radio
frequency energ y. T he equipment has been typ e te st ed and f ound to comply with the l im i ts for a
Class A digital device pursuant to Part 15 of FCC Rules, w hich are de si gned to provide
reasonable prote ct ion a gainst such radio freq uency interferenc e. O pera ti on of thi s equ ipment in
a residential area may cause inter fe rence, in which case the user at his own expense will be
required to take w hat ever measures a re re quired to correc t the interference.
Shielded Cables: If shielded cables have been supplied or specified, they mus t be us ed on t he
syste m in order to mainta in internatio n al regulatory compliance.
Warning! This is a Clas s A produ ct. In a do mestic environment this product may cause radio
interference, in wh i ch case the user may be required to take adequate measures.
Achtung! Dieses ist ein Gerä t de r Funk st örgrenzwertkla ss e A . In Wohnbereichen können bei
Betrieb dieses Geräte s Rundfunkstörungen auftreten, in welchen Fäl le n der Be nut zer für
entsprechend e G egenmaßnahmen ve rantwortlich ist.
Avertissement! Cet appareil est un appareil de Classe A. Dans un environnement résidentiel,
cet appareil peut provoquer des brouillages radioélectriques. Dans ce cas, il peut être demandé à
l'utilisateur de prendre les mesures appropriées.
Contents
Preface........................................................................... ix
This manual is written for the customer service engineer.
Document Structure
This manual uses a structured document ation desig n. Topics are organ ized into small
sections for efficient online and printed reference. Each topic begins with an abstract,
followed by an illustration or example, and ends with descriptive text.
This manual has four chapters and three appendixes, as follows:
• Chapter 1, System Overview, introduces the Compaq AlphaServer DS20
system. It describes each system component.
• Chapter 2, Trouble shoo ting , describes troubleshooting during power-up and
booting, as well as the test command.
• Chapter 3, Error Registers, describes the error registers used to hold error
information.
• Chapter 4, Removal and Replacement, describes removal and replacement
procedures for field-replaceable units (FRUs).
• Appendix A, Halts, Co nsole Commands, a nd Enviro nment Vari a bles,
summarizes the commands used to examine and alter the system configuration.
• Appendix B, Managing t he System Remotel y, describes how to use the Remote
Console Manager (RCM) to monitor and control the system remotely.
• Appendix C, Firmware Upda te, describes how to update system firmware.
ix
Documentation Titles
Table 1 lists books in the documentation set.
Table 1 AlphaServer DS20 Documentation
TitleOrder Number
User and Installation Documentation KitQZ–014AA–G8
User’s GuideEK–AS140–UG
Basic InstallationEK–AS140–IN
Service Information
Service ManualEK–AS140–SV
Information on the Internet
Using a Web browser you can access the AlphaServer InfoCenter at:
http://www.digital.com/info/alphaserver/products.html
Access the latest system firmware either with a Web browser or via FTP as follows:
ftp://ftp.digital.com/pub/Digital/Alpha/firmware/
Interim firmware released since the last firmware CD is located at:
The Compaq Alpha Server DS2 0 system c onsi sts of up to two CPUs, up to 4 Gbytes of
memory, 6 I/O slots, and up to 7 SCSI storage devices. AlphaServer DS20 systems
can be mounted in a standard 19” rack.
AlphaServer DS20 systems support OpenVMS, Compaq Tru64 UNIX, Windows NT,
and Linux.
Topics in this chapter include the following:
• System Enclosure
• Operator Control Panel and Drives
• System Consoles
• System Architecture
• CPU Types
• Memory
• Memory Addressing and Data Location
• System Board
• Server Feature Module
• Power Circuit and Cover Interlock
• Power Supply
• Power Up/Down Sequence
• TIG Bus
• Maintenance Bus (I
• StorageWorks Drives
2
C Bus)
System Overview 1-1
1.1 System Enclosure
The system has up to two CPU modules and up to 4 Gby tes of memory. A single
fast wide UltraSCSI Stora geW orks she lf prov i des up to 128 Gbyte s of storage.
Figure 1-1 System Enclosure
4
1
2
5
PKW-1402-98
3
6
1-2 AlphaServer DS20Service Manual
The numbered callouts in Figure 1-1 refer to the system components.
➊
System card cage, which holds the system board and the CPU, memory, and
system I/O.
➋ PCI/ISA section of the system card cage.
➌ Operator contro l p anel assemb ly, which in cludes th e control p anel, the LC D
display, and the floppy drive.
➍ CD-ROM drive.
➎
Cooling section containing two fans and the server feature module.
➏ StorageWorks shelf.
Cover Interlock
The system has a single cover interlock switch tripped by the top cover.
Figure 1-2 Cover Interlock Circuit
Power
Server Feature Module
Switch
pack
Supply
Cover
Interlock
Push button
ON/OFF
OCP
DC_ENABLE_L
OCP
Connector
PK1405-99
NOTE: The cover interlock must be engaged to enable power-up.
To overr ide the cover inter lock, use a s u itable object to close the inter lock cir cuit.
Disk damage will result if the system is run with the top cover off.
Cover
Interlock
Switch
System Overview 1-3
1.2 Operator Control Panel and Drives
The control panel includes the On/Off, Halt, and Reset buttons and an LCD
display.
Figure 1-3 Control Panel Assembly
CD-ROM
Floppy
OCP Display
1
OCP display. The OCP display is a 16-character LCD that indicates status during
power-up and self-test. While the operating system is running, the LCD displays the
system type. Its controller is on the XBUS.
CD-ROM. The CD-ROM drive is used to load software, firmware, and updates. Its
controller i s on P CI1 on th e P C I backplane on the system b oa rd.
Floppy disk. The floppy drive is used to load software and firmware updates. The
floppy c ontrol ler is on the XBUS on the PCI backplane on the system b oard.
2
3
PKW-0501-97
1-4 AlphaServer DS20Service Manual
➊On/Off button. Powers the system on or off. When the LED to the right of the
button is lit, the power is on. The On/Off button is connected to the power
supplies through the system interlock and the RCM logic.
➋Rese t but ton. Initializes the system.
➌Halt button. When the Halt button is pressed, different results are manifest
depending upon the state of the machine.
The major function of the Halt button is to stop whatever the machine is doing
and return the system to the SRM console.
To get to the SRM console, for sy stems r u nni ng OpenVMS o r Compaq Tr u64
UNIX, press the Halt button.
To get to the SRM console, for systems running Windows NT, press the Halt
button and then press the Reset button. (Pressing the Halt button when the
system is running Windows NT causes a “halt assertion” flag to be set in the
firmware. When Reset is pressed, the console reads the “halt assertion” flag and
ignores environment variables that would cause the system to boot.)
The function of the Halt button is complex; it depends upon the state of the
machine when the button is pressed. See Section B.1 for a full discussion of the
Halt button.
System Overview 1-5
1.3 System Consoles
There are two console progra ms: the SRM consol e and the AlphaBIOS console.
SRM Console Prompt
On systems running the Compaq Tru64 UNIX or OpenVMS operating system, the
following console prompt is displayed after system startup messages are displayed, or
whenever the SRM console is invoked:
P00>>>
NOTE: The console prompt displays only after the entir e power-u p s equenc e is
complete. This can take up to several minutes if the memory is very large.
AlphaBIOS Boot Menu
On systems running the Windows NT operating system, the Boot menu is displayed
when the AlphaBIOS console is invoked:
1-6 AlphaServer DS20Service Manual
SRM Console
The SRM console is a command-line interface used to boot the Compaq Tru64 UNIX
and OpenVMS operating systems. It also provides support for examining and
modifying the system state and configuring and testing the system. The SRM console
can be run from a serial terminal or a graphics monitor.
AlphaBIOS Console
The AlphaBIOS console is a menu-based interface that supports the Microsoft
Windows NT operating system. AlphaBIOS is used to set up operating system
selections, boot Windows NT, and display information about the system configuration.
The ISA Configuration Utility and the RAID Standalone Configuration Utility are run
from the AlphaBIOS console. AlphaBIOS runs on either a serial terminal or graphics
terminal. Windows NT requires a graphics monitor.
Environment Variables
Environment variables are software parameters that define, among other things, the
system configuration. They are used to pass information to different pieces of
software running in the system at various times . The os_type environment variable,
which can be set to VMS, UNIX, or NT, determines which of the two consoles is used.
The SRM console is always brought into memory, but AlphaBIOS is loaded if os_type
is set to NT and the Halt LED is not lit .
Refer to Appendix A of this guide for a list of the environment variables used to
configure a system.
Refer to your system User’s Guide for information on setting environment variables.
Most environment variables are stored in the NVRAM area of the flash ROM on the
system board. It is recommended that you keep a record of the environment variables
for each system that you service. Some environment variable settings are lost when a
module is swapped and must be restored after the new module is installed. Refer to
Appendix A for a convenient worksheet for recording environment variable settings.
System Overview 1-7
1.4 System Architecture
1 or 2
PKW1400-98
An Alpha microprocessor chi p is use d in this system. The CPU, memo ry, and the
I/O modules are physically connected to the system board and logically connected
through a switch-based interconnect implemented in a cross-bar switch chipset.
Figure 1-4 Block Diagram
Command, Address, and Control lines for each Memory Array
C chip
Control lines for D chips
Probe/
Addr.
CMD/
Addr.
CPU 0
Probe/
Addr.
CMD/
Addr.
CPU 1
(optional)
B cache
CPU
Data
Bus
CAPbus
P chip
P chip
PAD
Bus
64 bit PCI
8 D chips
64 bit PCI
Up to 2
Memory
Banks
Memory
Data
Bus
Memory
Banks
B cache
1-8 AlphaServer DS20Service Manual
The AlphaServer DS20 is a switch-based interconnect system; it uses a cross-bar
switch chipset that allows data to move directly from place to place in the system. The
CPU, memory, and I/O devices physically connect to the system board and each has
one or two logical connections to the switch. The arrows on the block diagram shown
in Figure 1-4 indicate the flow of data, command/address, and control signals.
On the system board is:
• A system switch consisting of a control chip (C-chip) and 8 data chips (D-chips)
• Three buses to the D-chips: the memory data bus, the CPU data bus, and the
P-chip address and data bu s (PAD bus)
• One bus from the C-chip to the P-chips (CAP bus)
• Two 60 command/address and control connections between each CPU and the
C-chip: the command/a d dress li ne f rom the CPUs to the C-chi p and the probe
address lines from the C-chip to the CPUs
• A TIG bus connected to the C-chip
• Control lines from the C-chip to the D-chips
• Control, timing, and address lines from the C-chip to each memory array
• Two 64-bit PCI buses with three PCI option slots each
• One ISA bus bridged on PCI0 and two SCSI ports (unused at FRS) also on PCI0
(If an ISA option is used, PCI 1 slot 9 cannot be used for a PCI option.)
• One ISA to XBUS bridge to the built-in XBUS options
A fully configu red pe desta l syst em can have two CPUs, sixte en DIMMs, a total of six
I/O options, and seven 18 Gbyte UltraSCSI disks. Maximum memory is 4 Gbytes.
The I/O options can be all PCI options or five PCI options and a single ISA option.
Other major lines in the system are used for command, addresses, and control.
For information on CPUs, see Sectio n 1. 5.
For information on memory, see Sections 1.6 and 1.7.
There are two 64-bit PCI buses connected to the cross-bar switch chipset by two PAD
buses and a single CAP bus. Each bus has three PCI slots for I/O devices. PCI bus 0
has an ISA bridge and a SCSI adapter with two ports (not used) embedded on the bus.
A single ISA slot is available on PCI bus 0 that, when used, eliminates the use of one
PCI slot on PCI bus 1.
Logic and sensors on the system feature module monitor power status and the system
environment (temperature and fan speeds).
The Alpha 21264 chip uses 0.35 micron chip technology, has a transistor count of 15.2
million, consumes 50 watts of power, and is air cooled (a fan is on the chip). The
default cache system is write-back.
Chip Description
UnitDescription
Instruction64-Kbyte I-cache
Execution4-way execution; four integer units, two of which can perform
memory address calculations for load and store instructions;
dedicated units for floating-point add, multiply, divide, and
square root operations.
MemoryMerge logic, 64-Kbyte write-through first-level data cache,
bus interface unit that consists of two ports, one a 16-byte Bcache port and the other an 8-byte system port.
CPU Variants
Module VariantClock FrequencyOnboard Cache
KN310-Ax500 MHz4 Mbytes
CPU Configuration Rules
• The first CPU must be in CPU slot 0.
• Both CPUs must have the same Alpha chi p clo c k spee d selected.
Module LEDs
Description (read LEDs from right to left on the
LED Name
module)
2V_PWRGOOD_LEDNormally on. Indicates the presence of 2.XV.
SROM_CLK_LEDNormally off. Toggles on and off rapidly during the
SROM load phase.
DC_OK_LEDNormally on. Indicates the presence of DC_OK.
CPU_SELF_TEST_LEDNormally on. Indicates the status of self-test. If the LED
is off, there was an error or timeout after the SROM load.
System Overview 1-11
1.6 Memory
Memory consists of up to four memory options, each consisting of four DIMMs.
There are four option variants: 128 Mbytes, 256 Mbytes, 512 Mbytes, and 1
Gbyte.
Memory is organized on two 256 plus ECC bit buses. Each bus can hold up to two
memory banks (a memory option) made up of four DIMM modules. Memory can be
configured from a minimum of 128 Mbytes (1 MS340-BA) to 4 Gbytes (4 MS340EA). All memory is synchronous.
DRAM
Number/
OptionSizeModuleType
optionSize
MS340-BA128 MB54-25066-BASynch.364 x 32MB
MS340-CA256 MB54-25053-BASynch.364 x 64MB
MS340-DA512 MB54-25941-KASynch.364 x 128MB
MS340-EA1 GB54-25941-BASynch.364 x 256MB
Memory Operation
Two 256-bit memory buses transfer data between the cross-bar chipset switch and
main memory. Each DIMM bank, made up of four DIMM modules, provides the data,
or 256 bits p lus 32 ECC b its, of the 32 by tes transferred. Two modules in the b an k
provide the odd bytes of data, and the other two modules provide the even bytes of
data.
Memory Configuration Rules
In a system, memories of different sizes are permitted, but:
• A memory option consists of four DIMMs all of which must be the same size.
• Convention places the largest memory option in slots marked 0 on the system
board. See Figure 1-6.
• Memory options must be installed in slots designated for each bank. The first
bank goes into slots marked 0, the second bank into slots marked 1, and so on.
System Overview 1-13
1.7 Memory Addressing and Data Location
0
0
0
0
PK1488-98
Memory addressing is contiguous beginning with memory bank 0. The first
address of each bank is one above the ending address of the previous bank.
Data is located in DIMMs as described by Figure 1-7.
Figure 1-7 Contents of DIMMs
D
Chip
D
Chip
DIMM Slots
D
Chip
D
Chip
DIMM Contains
Bank 1 even b yt es 0, 2, 4, 6, 8, 10, 12, 14
Bank 3 even bytes 0, 2, 4, 6, 8, 10, 12, 14
Bank 1 even b yt es 16, 18, 20, 22, 24, 26, 28, 3
Bank 3 even b yt es 16, 18, 20, 22, 24, 26, 28, 3
Bank 0 even bytes 0, 2, 4, 6, 8, 10, 12, 14
Bank 2 even bytes 0, 2, 4, 6, 8, 10, 12, 14
Bank 0 even b yt es 16, 18, 20, 22, 24, 26, 28, 3
Bank 2 even b yt es 16, 18, 20, 22, 24, 26, 28, 3
The first address of each bank is one above the ending address of the previous bank.
Examp le 1 –1 and Figure 1-8 show the starting address of each memory bank using
Total Ba d Pa ge s = 0
Total Good Memory = 512 MBytes
P00>>>
Figure 1-8 Memory Configuration
Display System ConfigurationF1= Hel
Systemboard Configuration
Hard Disk Configuration
PCI Configuration
SCSI Configuration
ISA Configuration
Memory Configuration
Integrated Peripherals
æ
Bank 0: 128 MB (32 MB per DIMM)-- Starting Address = 0x000 00000
Bank 1: 128 MB (32 MB per DIMM)-- Starting Address = 0x800 00000
Bank 2: 128 MB (32 MB per DIMM)-- Starting Address = 0x100 00000
Bank 3: 128 MB (32 MB per DIMM)-- Starting Address = 0x180 00000
ESC =Exit
DIMM Contents
Figure 1-7 shows the data contents of each DIMM in memory. Odd data bytes are in
DIMMs below the cross-bar swi tch chip set , a nd the even data byte s are in the DIMMs
above the cross-bar switch chipset.
stem Memory Configuration
System Overview 1-15
1.8 System Board
r
r
The system board contains five major logic sections performing five major
system functio ns.
• The cross-bar switch chipset and the system components attached to it (CPU(s),
memory, PCI chips, and the TIG bus)
• The power connections and voltage regulator
• The I/O subsystem
System Overview 1-17
1.8.1 Cross-Bar Switch and System Components
8
The cross-bar switch chipset consists of a single control chip, the C-chip, and
eight data chips, the D-chips. Into and out of the D-chips are two system buses to
CPUs, two PAD buses to PCI chips, and two memory data buses that connect to
up to four memory banks.
Figure 1-10 Cross-Bar Switch Data Block Diagram
%FDFKH
%FDFKH
,2'HYLFHV
,2'HYLFHV
&38
&38
0HPRU\'DWD%XV
ELW3&,
ELW3&,
3$'%XV
6\V'DWD%XV
6\V'DWD%XV
3FKLS
ELW
CAP Bus
3FKLS
3$'%XV
ELW
TIG Bus
FKLS
Interrupts
TIG
PAL
&
'
'
'
'
'
'
'
'
0HPRU\
'DWD%XV
0HPRU\EDQN
0HPRU\EDQN
1-18 AlphaServer DS20 Service Manual
0HPRU\
EDQN
0HPRU\
EDQN
PK1489-9
Each type of bus in the system is unique:
• The two memory data buses operate in 256-bit mode passing two hex words (32
bytes) of data between memory and the D-chips per cycle. The bus operates at
83.3 MHz.
• The two CPU data buses operate in “64-bit mode” passing a quadword (8 bytes)
of data between CPU and the D-chips per cycle. Though the CPU data bus is
narrower than the memory data bus, it operates at four times the speed of the
memory data bus at 333 MHz.
• The single CAP bus is a 24-bit wide bidirectional bus that carries commands and
addresses and is also used for transmitting data to and from the C-chip CSRs and
the TIG bus.
• The two PAD buses operate in 32-bit mode passing 8 nibbles per cycle. Two
cycles are required to pass 8 bytes of data. The PAD bus runs at 83.3 MHz.
• The TIG bus handles flash ROM data (system diagnostics and console programs)
and system interrupts.
The cross-bar switch is controlled by the C-chip which synchronizes, along with the
clock, the D-c hips, th e CPUs, me m ory, and the P- chi p s. Figure 1- 10 sho ws the major
data paths through the system.
The C-chip contains:
• Buffers for requests for the P-chips (shared), and each CPU
• Request queues for each memory bank
• A CPU interface for probe and fill requests and issues
• A P-chip interfac e co ntroller and bridg e b etween PCI comman ds and addresses
and CPU PIO commands and addresses
• D-chip contr olle r s, o ne for the PAD bus and one fo r ever yth i ng el se
The D-chip contains:
• Queues to and from t he P-c hip , to an d from th e CPUs, and to and from memory
• Control from the C-chip
The P-chip contains:
• Upstream (away from the PCI) and downstream (toward the PCI) data queues
• Upstream and downstream address queues
• An upstream address state machin e fo r DMA and peer-to-peer reads and writes
• A scatter/gather table for direct mapped and scatter/gather DMA memory access
System Overview 1-19
1.8.2 I/O Subsystem
s
The I/O subsystem consists of two 64-bit PCI buses. One has an embedded ISA
bridge, three PCI option slots, and a single ISA sl ot; the other bus has three PCI
option slots.
Figure 1-11 PCI Block Diagram
Crossbar
Switch
8 D Chips
P Chip
PCI 1
I/O ASIC
CAP Bus (24 bits)
P Chip
PCI 0
C Chip
PAD Bus (32 bits)
1 ISA
Slot
Cypress Chip
3&,%XV
PCI-0
3 64-bi t slots
(ISA Bridge,
IDE, KBRD,
MSE, USB)
ADAPTEC
Ultra SCSI
Controller
(2 ports)
1-20 AlphaServer DS20 Service Manual
COM1
COM2
Parallel
Port
Floppy
PCI- 1 B u
PCI-1
3 64-bi t slots
PK1494- 9 8
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