Compaq AlphaPC 264DP Technical Reference Manual
AlphaPC 264DP
Technical Reference Manual
Order Number: EC–RB0DA–TE
Revision/Update Information:
This is a new document.
Preliminary
Compaq Computer Corporation
February 1999
The information in this publication is subje ct to change without no ti ce.
COMPAQ COMPUTER CORPORATION SHALL NOT BE LIABLE FOR TECHNICAL OR EDITORIAL
ERRORS OR OMISSIONS CONTAINED HEREIN, NOR FOR INCIDENTAL OR CONSEQUENTIAL DAMAGES RESULTING FROM THE FURNISHING, PERFORMANCE, OR USE OF THIS MATERIAL. THIS
INFORMATION IS PROVIDED "AS IS" AND COMPAQ COMPUTER CORPORATION DISCLAIMS ANY
WARRANTIES, EXPRESS, IMPLIED OR STATUTORY AND EXPRESSLY DISCLAIMS THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR PARTICULAR PURPOSE, GOOD TITLE AND AGAINST
INFRINGEMENT.
This publication con ta ins information protecte d by copyright. No part of this publ i ca ti on m ay be photocopied or
reproduced in any form wit hout prior written consen t from Compaq Computer Corporation.
©1999 Digital Equipment Corporation.
All rights reserved. Printed in U.S.A.
COMPAQ, the Compaq logo, the Digital logo, and DIGITAL Registered in U.S. Patent and Trademark Office.
AlphaPC, DECchip, and Tru64 are trademarks of Comp aq Computer Corporation.
Intel is a registered trademark of Intel Corporation.
Microsoft, Visual C++, and Windows NT are registered trademarks of Microsoft Corporation.
Other product names mentioned herein may be the trademarks of their respective companies.
12 February 1999 – Subject to Change
Contents
1 AlphaPC 264DP Introduction
1.1 System Components and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.1.1 Memory Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.1.2 21272 Core Logic Chipset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.1.3 CPU Daughtercard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1.1.3.1 Level 2 Cache Subsystem Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.1.3.2 21264 DC-to-DC Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.1.4 Clock Subsystem. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.1.5 PCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
1.1.6 ISA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
1.1.7 IDE Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
2 System Configuration and Connectors
2.1 Board Layouts and Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.2 AlphaPC 264DP Mainboard Configuration Switches . . . . . . . . . . . . . . . . . . . . . . 2-5
2.2.1 Fail-Safe Booter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.2.2 Memory Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.2.3 Mini-Debugger. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.2.4 Password Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.2.5 Flash Write Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2.2.6 21272 Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2.3 AlphaPC 264DP Daughtercard Configuration Switches. . . . . . . . . . . . . . . . . . . . 2-8
2.4 AlphaPC 264DP Mainboard Connector Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.4.1 Daughtercard Connector Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.4.2 PCI Bus Connector Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
2.4.3 ISA Expansion Bus Connector Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2.4.4 IDE Drive Bus Connector Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
2.4.5 Ultra SCSI Bus Connector Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
2.4.6 SDRAM DIMM Connector Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
2.4.7 Diskette (Floppy) Drive Bus Connector Pinouts. . . . . . . . . . . . . . . . . . . . . . . 2-17
2.4.8 Parallel Bus Connector Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
12 February 1999 – Subject to Change
iii
2.4.9 COM1/COM2 Serial Line Connector Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . 2-18
2.4.10 Keyboard/Mouse Connector Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
2.4.11 +3-V Power Connector Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
2.4.12 +5-V Power Connector Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
2.4.13 Fan Box Power Connector Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
2.4.14 Speaker Connector Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
2.4.15 Halt Button Connector Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
2.4.16 Reset Button Connector Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
2.4.17 System Power Button Connector Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
2.4.18 Ultra SCSI Hard Drive LED Connector Pinouts. . . . . . . . . . . . . . . . . . . . . . . 2-21
2.4.19 Power LED Connector Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
2.5 AlphaPC 264DP Daughtercard Connector Pinouts. . . . . . . . . . . . . . . . . . . . . . . . 2-22
2.5.1 Microprocessor Fan Power Connector Pinouts. . . . . . . . . . . . . . . . . . . . . . . 2-22
2.5.2 SROM Test Data Input Connector Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
2.5.3 AlphaPC 264DP Daughtercard Connector Pinouts. . . . . . . . . . . . . . . . . . . . 2-22
2.5.4 AlphaPC 264DP Daughtercard Input Power Connector Pinouts. . . . . . . . . . 2-24
3 Power and Environmental Requirements
3.1 Power Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.2 Environmental Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.3 Physical Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.4 AlphaPC 264DP Hole and Connector Specifications . . . . . . . . . . . . . . . . . . . . . . 3-3
3.5 AlphaPC 264DP Daughtercard Hole Specification. . . . . . . . . . . . . . . . . . . . . . . . 3-6
4 Functional Description
4.1 21272 Core Logic Chipset Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.2 Cchip Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
4.2.1 CPU Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
4.2.2 Memory Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
4.2.2.1 Memory Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
4.2.2.2 Programmable Memory Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
4.2.2.3 General-Purpose Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
4.3 Dchip Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
4.3.1 Sysdata Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
4.3.2 Memdata Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
4.3.3 Padbus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
4.4 Pchip Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
4.4.1 PCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
4.5 Clock Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
4.5.1 CPU and System Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
4.6 PCI Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
4.6.1 PCI0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
iv
12 February 1999 – Subject to Change
4.6.1.1 Southbridge Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
4.6.1.2 PCI0 Expansion Slots. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
4.6.1.3 PCI SCSI Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10
4.6.2 PCI1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10
4.6.3 PCI Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10
4.7 PCI and System Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
4.8 ISA Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 -13
4.8.1 Super I/O Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14
4.8.2 ISA Expansion Slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14
4.9 DC Power Distribution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14
4.10 Reset and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16
4.11 System Software. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17
4.11.1 Serial ROM Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17
4.11.2 Flash ROM Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17
4.11.3 Operating Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17
5 System Memory and Address Mapping
5.1 Memory Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
5.2 Configuring SDRAM Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.3 System Address Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
5.3.1 CPU Address Mapping to PCI Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
5.3.2 TIGbus Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
A Support, Products, and Documentation
A.1 Customer Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
A.2 Supporting Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2
A.2.1 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2
A.2.2 Power Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2
A.2.3 Enclosure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2
A.3 Alpha Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3
A.4 Alpha Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-4
A.5 Third–Party Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-4
12 February 1999 – Subject to Change
v
Figures
1–1 AlphaPC 264DP Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
2–1 AlphaPC 264DP Mainboard Switch/Connector/Component Location. . . . . . . . . . 2-2
2–2 AlphaPC 264DP Daughtercard Switch/Connector/Component
Location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2–3 Mainboard Switchpack 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2–4 Mainboard Switchpack 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2–5 Daughtercard Configuration Switches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
3–1 AlphaPC 264DP Mainboard Hole Specifications . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3–2 AlphaPC 264DP Mainboard Connector Specifications. . . . . . . . . . . . . . . . . . . . . 3-4
3–3 AlphaPC 264DP Mainboard I/O Connector Specifications. . . . . . . . . . . . . . . . . . 3-5
3–4 AlphaPC 264DP Daughtercard Hole Specification—Component Side. . . . . . . . . 3-6
4–1 Memory Datapath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
4–2 Clock Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
4–3 PCI0 Arbitration Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10
4–4 Interrupt Request Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
4–5 AlphaPC 264DP Power Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16
5–1 AlphaPC 264DP Memory Subsystem. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
5–2 AlphaPC 264DP DIMM Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5–3 Gpen4 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
5–4 Gpen5 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
5–5 Gpen6 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
5–6 Feature Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
vi
12 February 1999 – Subject to Change
Tables
1–1 L2 Cache Size. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
2–1 AlphaPC 264DP Mainboard Switch/Connector/Component List. . . . . . . . . . . . . . 2-3
2–2 AlphaPC 264DP Daughtercard Switch/Connector/Component List . . . . . . . . . . . 2-5
2–3 Daughtercard Connector Pinouts (J18, J23). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2–4 PCI Bus Connector Pinouts (J35, J40–J42, J44, J46) . . . . . . . . . . . . . . . . . . . . . 2-11
2–5 ISA Expansion Bus Connector Pinouts (J47) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2–6 IDE Drive Bus Connector Pinouts (J45) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
2–7 Ultra SCSI Bus Connector Pinouts (J34, J38) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
2–8 SDRAM DIMM Connector Pinouts (J1, J5, J6, J9, J11, J13, J14, J16, J25–J32). 2-15
2–9 Diskette (Floppy) Drive Bus Connector Pinouts (J43). . . . . . . . . . . . . . . . . . . . . . 2-17
2–10 Parallel Bus Connector Pinouts (J17). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
2–11 COM1/COM2 Serial Line Connector Pinouts (J19). . . . . . . . . . . . . . . . . . . . . . . . 2-18
2–12 Keyboard/Mouse Connector Pinouts (J21). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
2–13 +3-V Power Connector Pinouts (J3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 -19
2–14 +5-V Power Connector Pinouts (J33) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
2–15 Fan Box Power Connector Pinouts (J2, J15, J22, J24) . . . . . . . . . . . . . . . . . . . . 2-19
2–16 Speaker Connector Pinouts (J39). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
2–17 Halt Button Connector Pinouts (J12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
2–18 Reset Button Connector Pinouts (J8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
2–19 System Power Button Connector Pinouts (J7) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
2–20 Ultra SCSI Hard Drive LED Connector Pinouts (J10). . . . . . . . . . . . . . . . . . . . . . 2-21
2–21 Power LED Connector Pinouts (J36) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
2–22 Microprocessor Fan Power Connector Pinouts (J1) . . . . . . . . . . . . . . . . . . . . . . . 2-22
2–23 SROM Test Data Input Connector Pinouts (J2) . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
2–24 Daughtercard Connector Pinouts (J3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
2–25 Input Power Connector Pinouts (J4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24
3–1 Power Supply DC Current Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3–2 AlphaPC 264DP Environmental Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
4–1 IDSEL Assignments for PCI Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
4–2 CPU Interrupt Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
4–3 ISA Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13
5–1 AlphaPC 264DP SDRAM Memory Configurations . . . . . . . . . . . . . . . . . . . . . . . . 5-3
5–2 TIGbus Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
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vii
Overview
This manual describe s t he COMPAQ AlphaPC 264DP, including the mainboard and
the daughtercard, for computing systems based on COMPAQ’s Alpha 21264 microprocessor and the COMPAQ 21272 core logic chipset.
Audience
This manual is intended for system designers and others who use the AlphaPC
264DP to design or evaluate computer systems based on the Alpha 21264 microprocessor and the 21272 core logic chipset.
Scope
This manual describes the features, configuration, functional operation, and interfaces of the AlphaPC 264DP. This manual does not include specific bus specifications (for e xample, PCI or I SA buses). Add itional information is avai lable in the
AlphaPC 264DP schematics, program source files, and the appropriate vendor and
IEEE specifications. See Appendix A for information on how to order related documentation and obtain additional technical support.
Preface
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ix
Manual Organization
This manual includes the following chapters, an appendix, and an index.
• Chapter 1, AlphaPC 264DP Introduc tion, is an overvi ew of the Alpha PC 264DP,
including its components, features, and uses.
• Chapter 2, System Configuration and Connectors, describes the user-environ-
ment configuration, boar d connectors and functions, and s witch functions. It also
identifies switch settings and connector locations.
• Chapter 3, Power and Environmental Requirements, describes the AlphaPC
264DP power and environmental requirements and provides board dimensions.
• Chapter 4, Functional Description, provides a functional description of the
AlphaPC 264DP mainboard, including the 21272 core logic chipset, L2 backup
cache (Bcache) and memory subsystems, system interrupts, clock and power
subsystems, and peripher al component interconnect (PCI) and In dustry Sta ndard
Architecture (ISA) devices.
• Chapter 5, System Memory a nd Addre ss Mapp ing, desc ribes how t o upgr ade t he
AlphaPC 264DP mainboard’s SDRAM memory.
• Appendix A, Support, Products, and Documentation, lists sources for compo-
nents and accessories not included with the AlphaPC 264DP, describes how to
obtain COMPAQ informat ion and techn ical support , and how to orde r COMPAQ
products and associated literature.
Conventions
This section defines product-specific terminology, abbreviations, and other conventions used throughout this manual.
Abbreviations
Register Access
•
The following list describes the register bit and field abbreviations:
Bit/Field Abbreviation Description
RO (read only) Bits and fields specified as RO can be read but not written.
RW (read/write) Bits and fields specified as RW can be read and written.
WO (write only) Bits and fields specified as WO can be written but not read.
x
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• Binary Multiples
The abbreviations K, M, and G (kil o, mega, and gi ga) re prese nt bina ry multi ples
and have the following values:
K
M
G
10
=2
20
=2
30
=2
(1024)
(1,048,576)
(1,073,741,824)
For example:
2KB = 2 kilobytes
4MB = 4 megabytes
8GB = 8 gigabytes
Addresses
=2 × 2
=4 × 2
=8 × 2
10
bytes
20
bytes
30
bytes
Unless otherwise noted, all addresses and offsets are hexadecimal.
Bit Notation
Multiple-bit fields can include contiguous and noncontiguous bits contained in
brackets ([]). Multiple contiguous bits are indicated by a pair of numbers separated
by a colon (:). For example, [9:7,5,2:0] specifies bits 9,8,7,5,2,1, and 0. Similarly,
single bits are frequently indicated with brackets. For example, [27] specifies bit 27.
Caution
Cautions indicate potential damage to equipment, software, or data.
Data Field Size
The term INTnn, where nn is one of 2, 4, 8, 16, 32, or 64, refers to a data field of
nn contiguous NATURALLY ALIGNED bytes. For example, INT4 refers to a
NATURALLY ALIGNED longword.
Data Units
The following data-unit terminology is used throughout this manual.
Term Words Bytes Bits Other
Byte ½18—
Word 1 2 16 —
Longword/Dword 2 4 32 Longword
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xi
Term Words Bytes Bits Other
Quadword 4 8 64 2 L ongwords
Octaword 8 16 128 2 Quadwords
Hexword 16 32 256 2 Octa words
Note
Notes emphasize particularly important information.
Numbering
All numbers are decimal or hexadecimal unless otherwise indicated. The prefix 0x
indicates a hexadecimal number. For example, 19 is decimal, but 0x19 and 0x19A
are hexadecimal (also see Addresses). Otherwise, the base is indicated by a subscript; for example, 100
Ranges and Extents
is a binary number.
2
Ranges are specified by a pai r of nu mbers separ ated b y two per iods ( ..) and a re inc lusive. For example, a range of integers 0..4 includes the integers 0, 1, 2, 3, and 4.
Extents are specified by a pair of numbers in brackets ([]) separated by a colon (:)
and are inclusive. Bit fields are often specified as extents. For example, bits [7:3]
specifies bits 7, 6, 5, 4, and 3.
Register and Memory Figures
xii
Register figures have bit and field position numbering starting at the right (low
order) and increasing to the left (high order).
Memory figures have addresses starting at the top and increasing toward the bottom.
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Signal Names
All signal names are printed in boldface type. Signal names that originate in an
industry-standard specification, such as PCI or IDE, are printed in the case as found
in the specification (usually uppercase). Active-high signals are indicated by the _h
suffix. Active-low signals have the _l suffix, a pound sign “#” appended, or a “not”
overscore bar. Signals with no suffix are consider ed high-asserted signals. Fo r exa m ple, signals data_h[127:0] and cia_int are active-high signals. Signals mem_ack_l,
FRAME#, and RESET
UNPREDICTABLE and UNDEFINED
are active-low signals.
Throughout this manual the terms UNPREDICTABLE and UNDEFINED are used.
Their meanings are quite different and must be carefully distinguished.
In particular, only priv il eg e d sof tw are (th a t is , sof tw a re ru nn ing in ke rnel mod e )
can trigger UNDEFINED operations. Unprivileged software cannot trigger
UNDEFINED operations. However, either privileged or unprivi leged softwa re can
trigger UNPREDICTABLE results or occurrences.
UNPREDICTABLE results or occurrences do not disrupt the basic operation of the
processor. The processor continues to execute instructions in its normal manner. In
contrast, UNDEFINED operations can halt the processor or cause it to lose information.
The terms UNPREDICTABLE and UNDEFINED can be further described as follows:
• UNPREDICTABLE
– Results or occurrences specified as UNPREDICTABLE might vary from
moment to moment, impleme ntation to impleme ntation, and instru ction to
instruction withi n implement ations. Soft ware can never dep end on resul ts
specified as UNPREDICTABLE.
– An UNPREDICTABLE result might acquire an arbitrary value that is
subject to a few constraints. Such a result might be an arbitrary function
of the input operands or of any state information that is accessible to the
process in its current access mode. UNPREDICTABLE results may be
unchanged from their previous values.
Operations that produce UNPREDICTABLE results might also produce
exceptions.
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xiii
– An occurrence specified as UNPREDICTABLE may or may not happen
based on an arbitrary choice function. The choice function is subject to
the same constraints as are UNPREDICTABLE results and must not constitute a security hole.
Specifically, UNPREDICTABLE results must not depend upon, or be a
function of, the co ntents of memo ry loca tions or r egist ers t hat ar e inac cessible to the current process in the current access mode.
Also, operations that migh t pr odu ce UNPREDI CTABLE results must not
write or modify the con tents of memor y locations or registers to which the
current process in the current access mode does not have access. They
must also not halt or hang the system or any of its components.
For example, a security hole would exist if some UNPREDICTABLE
result depended on the value of a register in another process, on the contents of processor te mp ora ry r eg is ter s l ef t behi nd by some previously running process, or on a sequence of actions of different processes.
• UNDEFINED
– Operati ons spe cifi ed as UNDEFINED can vary from moment to moment ,
implementation to implementation, and i nstruction to instruction w ithin
implementations. The operation can vary in effect from nothing, to stopping system operation.
xiv
– UNDEFINED operations can halt the processor or cause it to lose infor-
mation. However, UNDEFINED operations must not cause the processor
to hang, that is, reach an unhalted state from which there is no transition
to a normal state in which the machine executes instructions. Only privileged software (that is, software running in kernel mode) can trigger
UNDEFINED operations.
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System Components and Features
AlphaPC 264DP Introduction
This chapter prov ides a n overv iew of the Alp haPC 2 64DP syst em, includi ng its c omponents, features, and uses.
The AlphaPC 264DP system consists of an AlphaPC 264DP mainboard (mainboard) and one or two AlphaPC 264DP daughtercards (daughtercards). The daughtercard consists of the 21264 microprocessor, L2 cache, reset field programmable
gate array (reset FPGA), and power converters for 2.2 volts and 1.5 volts.
1.1 System Components and Features
1
The AlphaPC 264DP is implemented in industry-standard parts and uses one or two
21264 CPUs running at 500 MHz. The functional components are shown in
Figure 1–1 and introduced in the following subsections.
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AlphaPC 264DP Introduction 1–1
System Components and Features
Figure 1–1 AlphaPC 264DP Functional Block Diagram
Daughtercard 1
L2 Cache
2/4MB
21264
CPU
Daughtercard 2
(Optional)
L2 Cache
2/4MB
21264
CPU
Sysdata
bus 0
Cmd/addr
bus 0
Cmd/addr
bus 1
Sysdata
bus 1
1.1.1 Memory Subsystem
The DRAM memory subsystem on the AlphaPC 264DP consists of sixteen 200-pin
buffered DIMM slots, which are organized as four arrays of memory. The 21272
core logic chipset (21272) supports two 256-bit memory buses (288-bit including
ECC) with two arrays on each bus.
Mainboard
memdata1
21272
Dchip
(8)
memdata0
Cchip
Flash
FPGA
ROM
capbus
TIGbus
Config
SDRAM
8 DIMMs
Main Memory
SDRAM
8 DIMMs
Pchip
(2)
IRQ
I
S
A
Southbridge
PCI1
PCI1 Slots (3)
ISA Slot (1)
Combination
Controller
Keyboard
Mouse
IDE
PCI0
COM1
COM2
Parallel Port
Floppy Diskette
Connector
PCI/SCSI
PCI0 Slots (3)
The 72-bit, 100-MHz DIMMs consist of 64 bits of data and 8 bits of ECC, and can
be 32MB, 64MB, 128MB, or 256MB. The minimum conf iguration (one array populated with four 32MB DIMMs) is 128MB. The maximum configuation (four arrays
each populated with four 256MB DIMMs) is 4GB.
The memory cycle time is 83 MHz, identical to the 21272 cycle time.
Note: Although the memory cycle time is 83 MHz, qualified 100-MHz
DIMMs are r equired.
1.1.2 21272 Core Logic Chipset
The 21264 is supported by the 21272, with a 256-bit memory interface. The 21272
consists of the following three chips:
1–2 AlphaPC 264DP Introduction
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• The Cchip provides the interface from the CPU and main memory, and includes
a general-purpose int erface for the fla sh ROM and interrupts (TI Gbus Interface).
One Cchip is used per system.
• The Dchip provides the data path from the CPU to memory and I/O. Two, four,
or eight Dchips can be used in a system configuration. Eight Dchips provide
two 256-bit memory bus interfaces on the AlphaPC 264DP.
• The Pchip provides a n i nt erf ace to the periphe ra l component interconne ct (PCI).
One or two Pchips can be used in a system configuration. Two Pchips can be
used to provide two independent 64-bit PCI buses. AlphaPC 264DP uses two
Pchips to support two 64-bit PCI buses running at 33 MHz.
The chipset includes the majority of functions required to develop a high-performance PC or workstation, requiring minimum discrete logic on the module. It provides flexible and generic functions to allow its use in a wide range of systems.
1.1.3 CPU Daughtercard
The 21264 microprocessor and level 2 cache reside on a separate daughtercard that
plugs into the mainboard. One or two daughtercards can be used in an AlphaPC
264DP system. The daughtercard is a 10-layer printed-circuit board with dimen-
sions of approximately 14 .99 cm × 30.48 cm (5.905 in × 12.0 in). The daughtercard
consists of the following :
System Components and Features
• 21264 CPU
• Synchronous level 2 cache (2MB or 4MB cache, using late-write cache
SSRAMs)
• A linear regulator, providing 3.3 volts to 1.5 volts conversion for SSRAMs
• dc-to-dc converter for 5 volts to 2.2 volts for 21264 core power
• Reset and configuration FPGA
• Presence detect for cache configuration and CPU speed
• 512KB flash ROM used as SROM
• SROM test port
• 270-pin interface to mainboa rd (system clock forwarding interface and misc el la -
neous signals)
12 February 1999 – Subject To Change
AlphaPC 264DP Introduction 1–3
System Components and Features
1.1.3.1 Level 2 Cache Subsystem Overview
The external level 2 (L2) cache subsystem on the daughtercard supports 2MB or
4MB cache sizes using a 128-bit data bus.
The AlphaPC 264DP supports L2 cache using the synchronous SRAM (SSRAM)
sizes shown in Table 1–1. Nine SSRAMs are required per daught ercard f or 4MB L2
cache and five SSRAMs are re quired per daughtercard f or 2MB L2 c ache. In a dualprocessor system, cache sizes must be the same across the two daughtercards. The
first implementation of the daughtercard uses late-write SSRAMs.
Table 1–1 L2 Cache Size
L2 Cache Size SRAM Type
2MB Four 128KB × 36 data SSRAMs and one 128KB × 36 tag SSRAM
4MB Eight 256KB × 18 data SSRAMs and one 128KB × 36 tag SSRAM
1.1.3.2 21264 DC-to-DC Converter
The dc-to-dc converter is a 3.0 × 2.2 × 1.4-inch module that is mounted on the
daughtercard. It delivers 2.2 volts to the 21264. The features include:
• Programmable voltage between 1.5 volts and 2.5 volts
• Remote sense
• Overvoltage protection
• Current limit and short circuit protection
• Thermal shutdown
1.1.4 Clock Subsystem
The clock subsystem provides c locks t o the CPU, 2127 2, SDRAM DIMMs, and PCI
devices. A PC clock generator provides clocks for the SCSI, ISA, and combination
chip functions.
1–4 AlphaPC 264DP Introduction
12 February 1999 – Subject To Change
1.1.5 PCI Interface
The PCI interface provides a PCI speed of 33 MHz. The Cypress CY82C693UB
(southbridge) provides the following:
• PCI-to-ISA b ridge
• PCI to IDE in terface
• Real-time clock support
• Mouse and keyboard controller
The PCI to SCSI interface is derived from the Adaptec AIC7895 controller
(AIC7895). The AIC7895 supports two separated ultrawide SCSI ports.
The PCI has five dedicated 64-bit slots and one shared 64-bit slot. The one shared
slot also provides a 16-bit ISA expansion slot. Six expansion slots in total are sup-
ported—six PCI, or five PCI and one ISA.
The two PCI buses are configured as follows:
• PCI bus 0: contains Pchip0, southbridge, Adaptec SCSI, and three 64-bit expan-
sion slots
System Components and Features
• PCI bus 1: contains Pchip1 and three 64-bit expansion slots
1.1.6 ISA Interface
The ISA bus provides an expansion bus and the following system support functions:
• The ISA bus has one shared expansion slot with the PCI.
• An SMC FDC37C669 super I/O controller chip is used as the combination con-
troller chip that provides a diskette controller, two universal, asynchronous
receiver/transmitters (UARTs) for com ports, and a parallel port.
1.1.7 IDE Interface
The integrated drive electronics (IDE) provides an additional expansion bus, with
one connector on the mainboard.
Note: Only CD-ROMs with an IDE cable length of 12 inches or less are sup-
ported.
12 February 1999 – Subject To Change
AlphaPC 264DP Introduction 1–5
System Configuration and Connectors
2.1 Board Layouts and Components
The AlphaPC 264DP uses switches to implement variations in clock frequency
(21272 and 21264) and L2 ca che configur ation. Note that the swi tches for the 21264
speed and L2 cache configuration are on the daughtercard. The switches for the
21272 speed are on the ma inboar d. These switch es must b e confi gured f or the user’s
environment. Onboard connectors are provided for the I/O, memory DIMMs, serial
and parallel peripherals, and IDE devices.
After the board is configured, you can apply power and start up the firmware that is
loaded in the flash ROM.
Figure 2–1 shows the AlphaPC 264DP mainboard and its components.
2
12 February 1999 – Subject To Change
System Configuration and Connectors 2–1
Board Layouts and Components
Figure 2–1 AlphaPC 264DP Mainboard Switch/Connector/Component Location
J1
J5
J6
J9
J11
J13
J17
J20
J19
J21
U8
U16
U7
U15
J14
J16
J4
U11
J2
J7
J8
J10
J12
J15
U3
J3
U1
J18
U6
U5
U13
U4
U12
U10
U9
J22
J25
J26
J27
J28
J29
J30
J31
J32
J35
J40
J41
U51
J42
J44
J46
J47
indicates pin 1. indicates switch 1.
U14
U49
U57
U46
U50
J34
J38
J23
J24
D1
D2
J33
J37
U30
U26
J36
J39
SW2
SW3
U27U28
U31
XB1
B1
J43
J45
2–2 System Configuration and Connectors
12 February 1999 – Subject To Change
Board Layouts and Components
Ta ble 2–1 describes AlphaPC 264DP mainboard components.
Table 2–1 AlphaPC 264DP Mainboard Switch/Connector/Component List
Item No. Description Item No. Description
XB1 RTC battery (CR2032) J45 IDE bus connector
J1, J5, J6, J9
J11, J 13, J14,
J16, J25-J32
J2, J15, J22,
J24
J3 +3-V power connector SW 2, SW3 Switchpacks
J4 Reserved U1 MIC29502
J7 Power button connector U3 MC12439
J8 Reset button connector U4, U5, U7,
J10 SCSI LED connector U6 DC1046 Cchip
J12 Halt button connector U9, U10 100LVE222
J17 Parallel I/O connector U11 MC100LVEL37
J18, J23 Daughtercard connectors U14 MPC951
J19 COM1/COM2 (DB9) connectors
J20 Reserved U27, U28 DC1048 P chips
J21 Keyboard/mouse connector
J33 +5-V power connector U31 I
J34, J38 SC S I connectors U46 SRAM for SCSI
J35, J40-J42,
J44, J46
J36 Power LED connector U50 SCSI BIOS flash ROM
J37 Reserved U51 Super I/O (FDC37C669)
J39 Speaker connector U57 Southbridge (CY82C693UB)
J43 Floppy drive connector
1
COM1 is the top connector, COM2 is the bottom one.
2
Mouse connector is on the top, keyboard connector is on the bottom.
Memory connectors J47 ISA bus connector
Fan box power connector D1, D2 LEDs
DC4047 Dchips
U8, U12, U13,
U15, U16
1
U26 TIGbus FPGA
2
U30 AlphaBIOS flash ROM
2
C bus controller
PCI connectors U49 AIC7895
12 February 1999 – Subject To Change
System Configuration and Connectors 2–3
Board Layouts and Components
Figure 2–2 shows the AlphaPC 264DP daughtercard and its components, and
Ta ble 2–2 describes these components.
Figure 2–2 AlphaPC 264DP Daughtercard Switch/Connector/Component
Location
Side 1–Component Side
J4
U16
U17
U18
U19
D5
D4
D3
D2
D1
H2
SW2
indicates pin 1. indicates switch 1.
Side 2
U104
U15
U11
U10
U12U13U14
U9
U102
U7
H1
U6
U5
J3
J2
U4
U3
U2
U1
J1
U103
2–4 System Configuration and Connectors
U101
12 February 1999 – Subject To Change
AlphaPC 264DP Mainboard Configuration Switches
Table 2–2 AlphaPC 264DP Daughtercard Switch/Connector/Component List
Item No. Description Item No. Description
J1 Fan power U5 Microprocessor, socketed
(Alpha 21264)
J2 SROM debug connector U6 Bcache tag SSRAM
J3 Daughtercard data connector U7 Reset FPGA
J4 Daughtercard power connector U11, U13, U14 lcx38
H1 21264 heat sink U12 8 582 EEPROM
H2 +1.5-V regulator heat sink U15 5-V to 2.2-V converter
D1-D5 LEDs U16 tl7702b supervisor
SW2 Switchpack U17 512K×8 flash ROM, socketed
U1, U2,
U9, U10,
U101-104
U3 1489 U19 mic29302 3.3-V to 1.5-V regulator
U4 1488
Bcache data SSRAMs U18 74f151 multiplexer
2.2 AlphaPC 264DP Mainboard Configuration Switches
The AlphaPC 264DP mainboard has two sets of programmable switches located at
SW2 and SW3, as shown in Figure 2–1. These switches set the hardware
configuration.
Note: There is no switchpack SW1 on production mainboards.
Figures 2–3 and 2–4 reflect the mainboard switches.
12 February 1999 – Subject To Change
System Configuration and Connectors 2–5
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