Compal Electronics LA-3011, Satellite M100, Tecra A6 Schematic

A

1 1

2 2

B

C

D

E

Compal confidential

Schematics Document

Mobile Yonah uFCPGA with Intel
Calistoga_PM+ICH7-M core logic

3 3

4 4

A

B

2005-06-01

REV:0.1

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2005/06/01 2006/06/01

Compal Secret Data

Deciphered Date

D

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3011

401395

 

05

148, 01, 20

E

of

A

A

B

C

D

E

Compal confidential

Model:HAQAA

NAPA

File Name : LA-3011

1 1

Fan Control

page 4

LCD CONN

page 17

nVIDIA G72/G73
ATI M52/M54

page 18

PCI-E x 16

CRT / TV-OUT

page 16

2 2

10/100/1000 LAN

82562GX/82573E/82573V

page 26,27

RJ45/11 CONN

page 26

Mini Express Card

page 28

PCI-E BUS

(port 1)

PCI BUS

CardBus Controller

TI PCI7412

page 22,23

Mobile Yonah

uFCPGA-479 CPU

FSB

H_A#(3..31)

533/667MHz

Intel Calistoga MCH

945PM

PCBGA 1466

Intel ICH7-M

mBGA-652

page 19,20,21,22

page 4,5,6

page 7,8,9,10,11,12

DMI

H_D#(0..63)

DDR2 -400/533/667

Thermal Sensor
ADM1032AR

page 4

Dual Channel

USB2.0

Clock Generator

ICS9LPRS325AKLFT

page 15

DDR2-SO-DIMM X2

BANK 0, 1, 2, 3

page 13,14

Accelerometer
KXP84-0200

page 28

USB conn x1

(port 6)

(Docking)

page 34

USB2.0 HUB /

(port 0)

FP Conn
USB conn x2

BT Conn

page 38

page 24

page 24

(port 4,5)

(port 7)

USB conn x2

(port 2,3)

(Sub Board)

Azalia

Audio CKT AMP & Audio Jack

ALC861

page 29 page 30

page 24

TPA0232

FingerPrinter UPEK TCS3C/TCD42A
USBx1

MDC1.5

page 37

page 38

3 3

Slot 0

page 23

1394 port

page 22

LED

page 36

RTC CKT.

page 19

TPM1.2

Docking

page 34

Power On/O ff CKT.

page 37

SLB9635TT1.2

page 38

5in1 Slot

page 22

Super I/O

LPC47N217&207

page 33,38

FIR

page 33

LPC BUS

ENE KB910QF

page 25

SATA Master

PATA Slave

SATA HDD Connector

page 19

PATA ODD Connector

page 19

CIR

page 33

DC/DC Interface CKT.

4 4

page 39

Touch Pad Int.KBD

page 37page 37

BIOS

page 35

Power Circuit DC/DC

Page,40,41,42,43,44,45,46

A

B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2005/06/01 2006/06/01

Compal Secret Data

Deciphered Date

D

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC , M / B L A-3011

401395

 

248¬P , 01, 2005

E

of

A

5

4

3

2

1

Voltage Rails

Power Plane

VIN

D D

C C

B+
+CPU_CORE
+VCCP
+0.9VS
+1.5VS
+1.8V

+2.5VS

+3VALW

+5VALW
+5VS
+RTC_VCC

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

Description

Adapter power supply (18.5V)
AC or battery power rail for power circuit
Core voltage for CPU

1.05V power rail for Processor I/O and MCH/ICH core power

0.9V switched power rail for DDRII Vtt

1.5V switched power rail for PCI-E interface

1.8V power r ail for DDRII

3.3V always on power rail+2.5VALW ON ON ON*

3.3V always on power rail

3.3V switched power rail+3VS
5V always on power rail
5V switched power rail
RTC power ONON

S0-S1

N/A

ON OFF
ON
ON
ON
ON
ON+1.8VS OFF OFF1.8V switched power rail
ON OFF

ON
ON OFF OFF
ON
ON

S5

S3

N/A

N/A
N/A

N/AN/A
OFF

OFF

OFF

OFF

OFF
OFF

OFF

OFF

ON

OFF2.5V switched power rail for MCH video PLL

ON

ON*

ON

ON*
OFF

OFF
ON

Internal PCI Devices

DEVICE

LAN
Azalia D27

USB1.1/2.0
PCI to PCI (DMI to PCI)
AC97 MODEM
AC97 Audio
PATA/SATA
LPC I/F
SMBUS
CPU I/F

B B

Bus

1
0
0
0
0
0
0
0
0
0
0
0
0

PCI Device ID

D8

D28PCI-E
D29
D30
D30
D30
D31
D31
D31

D31 AD15DMA
D31 AD15PMU

IDSEL #

AD24
AD11
AD12
AD13
AD14
AD14
AD14
AD15
AD15
AD15
AD15D31

Board ID / SK U I D T ab l e for AD channel

Vcc 3.3V +/- 5%

Board ID

0
1
2
3
4
5
6
7 NC

100K +/- 1%Ra/Rc/Re

Rb / Rd / Rf V min

0

8.2K +/- 1%
18K +/- 1%
33K +/- 1%
56K +/- 1%
100K +/- 1%
200K +/- 1%

AD_BID

0 V

0.216 V 0.250 V 0.289 V

0.436 V

0.712 V

1.036 V

1.453 V 1.650 V 1.759 V

1.935 V

2.500 V

Vtyp

BOARD ID Table

Board ID

0
1
2
3
4
5
6
7

PCB Revision

0.1

SKU ID Table

SKU ID

0
1
2
3
4
5
6
7

SKU

BTO Option Table

AD_BID

V

AD_BID

0 V 0.100 V

0.503 V

0.819 V

0.538 V

0.875 V

1.185 V 1.264 V

2.200 V

3.300 V

2.341 V

3.300 V

max

External PCI Devices

DEVICE

CARD BUS

PCI Device ID

D6

IDSEL #

AD22

REQ/GNT #

2

PIRQ

ABCD

I2C / SMBUS ADDRESSING

DEVICE

A A

DDR SO-DIMM 0
DDR SO-DIMM 1
CLOCK GENERATOR (EXT.)

5

HEX

A0
A4
D2

ADDRESS

1 0 1 0 0 0 0 0
1 0 1 0 0 1 0 0
1 1 0 1 0 0 1 0

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/06/01 2006/06/01

BTO Item BOM Structure

VGA

LAN

INT MIC.
DOCKING

CIR
FIR

SUPER I/O

Battery

Compal Secret Data

Deciphered Date

PM@
GM@

82573G@
82573L@
82573@
82562@

45MIC@
WD@
WOD@
CIR@
FIR@

217@

SI207@

45@

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3011

 

401395

348, 01, 2005

1

of

A

5

4

3

2

1

This shall place near CPU

1

2

1000P_0402_50V7K

C371 10U_0805_10V4Z

1000P_0402_50V7K

1

+VCCP

@

C374

@

+

150U_D2_6.3VM

C373

1

2

+3VS

R429
10K_0402_5%

1 2

ACES_85205-0300

1

2

448, 01, 20

JP16

1
2
3

A

of

H_A#[3..31]

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8

CLK_CPU_BCLK
CLK_CPU_BCLK#

OCP#

H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_ADSTB#0
H_ADSTB#1

H_ADS#
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DRDY#
H_HIT#
H_HITM#
H_IERR#
H_LOCK#
H_RESET#

H_RS#0
H_RS#1
H_RS#2
H_TRDY#

XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3

DBRESET#

H_DBSY#
H_DPSLP#
H_DPRSTP#
H_DPWR#
XDP_BPM#4
XDP_BPM#5
H_PROCHOT#

H_PWRGOOD
H_CPUSLP#
XDP_TCK
XDP_TDI
XDP_TDO
TEST1
TEST2
XDP_TMS
XDP_TRST#

H_THERMDA
H_THERMDC
H_THERMTRIP#

D D

H_REQ#[0..4]

H_ADSTB#0

C C

R114

56_0402_5%

1 2

+VCCP

B B

+VCCP

H_THERMDA, H_THERMDC routing together.
Trace width / Spacing = 10 / 10 mil

A A

H_PROCHOT# OCP#

H_ADSTB#1

CLK_CPU_BCLK

CLK_CPU_BCLK#

H_DEFER#

H_RESET#

H_RS#[0..2]

DBRESET#

H_DPSLP#

H_DPRSTP#

H_DPWR#

1 2

56_0402_5%

H_PWRGOOD

H_CPUSLP#

R111 51_0402_5%

1 2

R112 51_0402_5%

1 2

H_THERMTRIP#

+VCCP

12

R118

56_0402_5%@

B

2

E

3 1

C

Q13

MMBT3904_SOT23@

5

H_ADS#
H_BNR#

H_BPRI#

H_BR0#

H_DRDY#

H_HIT#

H_HITM#

H_LOCK#

H_TRDY#

H_DBSY#

R115

JP22A

J4

A3#

L4

A4#

M3

A5#

K5

A6#

M1

A7#

N2

A8#

J1

A9#

N3

A10#

P5

A11#

P2

A12#

L1

A13#

P4

A14#

P1

A15#

R1

A16#

Y2

A17#

U5

A18#

R3

A19#

W6

A20#

U4

A21#

Y5

A22#

U2

A23#

R4

A24#

T5

ADDR GROUP

A25#

T3

A26#

W3

A27#

W5

A28#

Y4

A29#

W2

A30#

Y1

A31#

K3

REQ0#

H2

REQ1#

K2

REQ2#

J3

REQ3#

L5

REQ4#

L2

ADSTB0#

V4

ADSTB1#

A22

BCLK0

A21

H1

E2

G5

F1

H5

F21

G6

E4

D20

H4

B1

F3

F4
G3
G2

AD4
AD3
AD1
AC4

C20

E1

B5

E5

D24
AC2
AC1
D21

D6
D7

AC5
AA6
AB3
C26
D25
AB5
AB6

A24
A25

C7

HOST CLK

BCLK1

ADS#
BNR#
BPRI#
BR0#
DEFER#
DRDY#
HIT#

CONTROL

HITM#
IERR#
LOCK#
RESET#

RS0#
RS1#
RS2#
TRDY#

BPM0#
BPM1#
BPM2#
BPM3#

DBR#
DBSY#
DPSLP#
DPRSTP#
DPWR#
PRDY#
PREQ#
PROCHOT#

PWRGOOD
SLP#
TCK
TDI
TDO
TEST1
TEST2
TMS
TRST#

THERMAL

THERMDA

DIODE

THERMDC
THERMTRIP#

FOX_PZ47903-2741-42_YONAH

H_DPSLP#

1 2

56_0402_5%@

H_DPRSTP#

1 2

56_0402_5%@

YONAH

DATA GROUP

MISC

LEGACY CPU

+VCCP

R117

R110

4

D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#

DINV0#
DINV1#
DINV2#
DINV3#

DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#

A20M#
FERR#

IGNNE#

INIT#
LINT0
LINT1

STPCLK#

SMI#

H_D#0

E22

D0#

H_D#1

F24

D1#

H_D#2

E26

D2#

H_D#3

H22

D3#

H_D#4

F23

D4#

H_D#5

G25

D5#

H_D#6

E25

D6#

H_D#7

E23

D7#

H_D#8

K24

D8#

H_D#9

G24

D9#

H_D#10

J24

H_D#11

J23

H_D#12

H26

H_D#13

F26

H_D#14

K22

H_D#15

H25

H_D#16

N22

H_D#17

K25

H_D#18

P26

H_D#19

R23

H_D#20

L25

H_D#21

L22

H_D#22

L23

H_D#23

M23

H_D#24

P25

H_D#25

P22

H_D#26

P23

H_D#27

T24

H_D#28

R24

H_D#29

L26

H_D#30

T25

H_D#31

N24

H_D#32

AA23

H_D#33

AB24

H_D#34

V24

H_D#35

V26

H_D#36

W25

H_D#37

U23

H_D#38

U25

H_D#39

U22

H_D#40

AB25

H_D#41

W22

H_D#42

Y23

H_D#43

AA26

H_D#44

Y26

H_D#45

Y22

H_D#46

AC26

H_D#47

AA24

H_D#48

AC22

H_D#49

AC23

H_D#50

AB22

H_D#51

AA21

H_D#52

AB21

H_D#53

AC25

H_D#54

AD20

H_D#55

AE22

H_D#56

AF23

H_D#57

AD24

H_D#58

AE21

H_D#59

AD21

H_D#60

AE25

H_D#61

AF25

H_D#62

AF22

H_D#63

AF26

H_DINV#0

J26

H_DINV#1

M26

H_DINV#2

V23

H_DINV#3

AC20

H_DSTBN#0

H23

H_DSTBN#1

M24

H_DSTBN#2

W24

H_DSTBN#3

AD23

H_DSTBP#0

G22

H_DSTBP#1

N25

H_DSTBP#2

Y25

H_DSTBP#3

AE24

H_A20M#

A6

H_FERR#

A5

H_IGNNE#

C4

H_INIT#

B3

H_INTR

C6

H_NMI

B4

H_STPCLK#

D5

H_SMI#

A3

H_D#[0..63]

+3VS

Thermal Sensor ADM1032ARM

1

C148

0.1U_0402_16V4Z

1

C163

2200P_0402_50V7K

EC_SMB_CK2
EC_SMB_DA2

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

H_DSTBN#[0..3]

H_DSTBP#[0..3]

H_A20M#
H_FERR#
H_IGNNE#
H_INIT#
H_INTR
H_NMI

H_STPCLK#
H_SMI#

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/06/01 2006/06/01

THERMDA

2

THERMDC

Compal Secret Data

2
3
8
7

EN_DFAN1

Deciphered Date

U8

D+

ALERT#

D-

THERM#

SCLK
SDATA

ADM1032ARM_RM8

0.01U_0402_25V4Z
C6

+VCCP

2

VDD1

GND

12

R1
150K_0402_5%

2

1
6
4
5

B+

12

3

+IN

2

-IN

5

+IN

6

-IN

R255

1 2

56_0402_5%@

8

P

OUT

U2A

G

LM358A_SO8

4

OUT

U2B
LM358A_SO8

H_PWRGOOD

12

R116

10K_0402_5%@

FAN1_ON

1

R2

1 2

100K_0402_5%

7

H_FERR#

H_SMI#
H_INIT#

H_NMI
H_A20M#
H_INTR
H_IGNNE#
H_STPCLK#

H_CPUSLP#

XDP_TDI
XDP_TMS
XDP_TDO
XDP_BPM#5
XDP_TRST#
XDP_TCK

C212 180P_0402_50V8J@

C159 180P_0402_50V8J@
C145 180P_0402_50V8J@
C160 180P_0402_50V8J@
C161 180P_0402_50V8J@
C144 180P_0402_50V8J@
C139 180P_0402_50V8J@
C137 180P_0402_50V8J@
C134 180P_0402_50V8J@
C138 180P_0402_50V8J@

R79 56_0402_5%

1 2

R77 56_0402_1%

1 2

R76 56_0402_5%

1 2

R75 56_0402_5%

1 2

R80 56_0402_5%

1 2

R78 56_0402_5%

1 2

+5VS

1 2

C362
10U_1206_16V4Z

6

2

1

D

G

S

4 5

FAN1

12

D30

1N4148_SOD80

Q29

SI3456DV-T1_TSOP6

1

2

C372

FAN_SPEED1

@

3

Placement near to ICH7

12

12
12
12
12
12
12
12
12
12

Placement near to CPU side

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3011

401395

 

05

5

4

3

2

1

V_CPU_GTLREF

+VCCP

12

R89
1K_0402_1%

12

R90
2K_0402_1%

+VCC_CORE

R86
100_0402_1%

1 2

R85
100_0402_1%

1 2

VCCSENSE

VSSSENSE

Close to CPU pin
within 500mils.

CPU_BSEL CPU_BSEL2 CPU_BSEL1

133

166

00

0

12

12

R571

54.9_0402_1%

R105

R579

27.4_0402_1%

D D

Close to CPU pin AD26
within 500mils.

C C

B B

Length match within 25 mils
The trace width 18 mils space
7 mils

+1.5VS

1

C143

C141

2

0.01U_0402_16V7K

CPU_BSEL0

1

1

Resistor placed within

0.5" of CPU pin.Trace
should be at least 25
mils away from any
other toggling signal.

12

27.4_0402_1%

1

R96

54.9_0402_1%

12

1

2

10U_0805_10V4Z

VCCSENSE
VSSSENSE

H_PSI#

CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6

V_CPU_GTLREF

CPU_BSEL0
CPU_BSEL1
CPU_BSEL2

+VCC_CORE

+VCCP

VCCSENSE
VSSSENSE

H_PSI#
CPU_VID0

CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6

CPU_BSEL0
CPU_BSEL1
CPU_BSEL2

COMP0
COMP1
COMP2
COMP3

JP22B

AF7

VCCSENSE

AE7

VSSSENSE

B26

VCCA

K6

VCCP

J6

VCCP

M6

VCCP

N6

VCCP

YONAH

VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP

PSI#
VID0

VID1
VID2
VID3
VID4
VID5
VID6

GTLREF
BSEL0

BSEL1
BSEL2

COMP0
COMP1
COMP2
COMP3

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

FOX_PZ47903-2741-42_YONAH

W21

AD26

AB20
AA20
AF20
AE20
AB18
AB17
AA18
AA17
AD18
AD17
AC18
AC17
AF18
AF17

T6

R6

K21

J21
M21
N21
T21
R21
V21

V6

G21

AE6
AD6

AF5
AE5
AF4
AE3
AF2
AE2

B22
B23
C21

R26
U26

U1

V1

E7

D2

F6
D3
C1

AF1
D22
C23
C24
AA1
AA4
AB2
AA3

M4
N5

T2

V3

B2

C3

T22
B25

AB26

VSS

AA25

VSS

AD25

VSS

AE26

VSS

AB23

VSS

AC24

VSS

AF24

VSS

AE23

VSS

AA22

VSS

AD22

VSS

AC21

VSS

AF21

VSS

AB19

VSS

AA19

VSS

AD19

VSS

AC19

VSS

AF19

VSS

AE19

VSS

AB16

VSS

AA16

VSS

AD16

VSS

AC16

VSS

AF16

VSS

AE16

VSS

AB13

VSS

AA14

VSS

AD13

VSS

AC14

VSS

AF13

VSS

AE14

VSS

AB11

VSS

AA11

VSS

AD11

VSS

AC11

VSS

AF11

VSS

AE11

VSS

AB8

VSS

AA8

VSS

AD8

VSS

AC8

VSS

AF8

VSS

AE8

VSS

AA5

VSS

AD5

VSS

AC6

VSS

AF6

VSS

AB4

VSS

AC3

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AF3
AE4
AB1
AA2
AD2
AE1
B6
C5
F5
E6
H6
J5
M5
L6
P6
R5
V5
U6
Y6
A4
D4
E3
H3
G4
K4
L3
P3
N4
T4
U3
Y3
W4
D1
C2
F2
G1

POWER, GROUNG, RESERVED SIGNALS AND NC

+VCC_CORE

JP22C

AE18

VCC

AE17

VCC

AB15

VCC

AA15

VCC

AD15

VCC

AC15

VCC

AF15

VCC

AE15

VCC

AB14

VCC

AA13

VCC

AD14

VCC

AC13

VCC

AF14

VCC

AE13

VCC

AB12

VCC

AA12

VCC

AD12

VCC

AC12

VCC

AF12

VCC

AE12

VCC

AB10

VCC

AB9

VCC

AA10

VCC

AA9

VCC

AD10

VCC

AD9

VCC

AC10

VCC

AC9

VCC

AF10

VCC

AF9

VCC

AE10

POWER, GROUND

VCC

AE9

VCC

AB7

VCC

AA7

VCC

AD7

VCC

AC7

VCC

B20

VCC

A20

VCC

F20

VCC

E20

VCC

B18

VCC

B17

VCC

A18

VCC

A17

VCC

D18

VCC

D17

VCC

C18

VCC

C17

VCC

F18

VCC

F17

VCC

E18

VCC

E17

VCC

B15

VCC

A15

VCC

D15

VCC

C15

VCC

F15

VCC

E15

VCC

B14

VCC

A13

VCC

D14

VCC

C13

VCC

F14

VCC

E13

VCC

B12

VCC

A12

VCC

D12

VCC

C12

VCC

F12

VCC

E12

VCC

B10

VCC

B9

VCC

A10

VCC

A9

VCC

D10

VCC

D9

VCC

C10

VCC

C9

VCC

F10

VCC

F9

VCC

E10

VCC

E9

VCC

B7

VCC

A7

VCC

F7

VCC

FOX_PZ47903-2741-42_YONAH

YONAH

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

K1
J2
M2
N1
T1
R2
V2
W1
A26
D26
C25
F25
B24
A23
D23
E24
B21
C22
F22
E21
B19
A19
D19
C19
F19
E19
B16
A16
D16
C16
F16
E16
B13
A14
D13
C14
F13
E14
B11
A11
D11
C11
F11
E11
B8
A8
D8
C8
F8
E8
G26
K26
J25
M25
N26
T26
R25
V25
W26
H24
G23
K23
L24
P24
N23
T23
U24
Y24
W23
H21
J22
M22
L21
P21
R22
V22
U21
Y21

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/06/01 2006/06/01

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3011

 

401395

05

548, 01, 20

1

A

of

5

4

3

2

1

+VCC_CORE

330U_D_2VM

+VCC_CORE

+VCC_CORE

+VCC_CORE

+VCC_CORE

1

+

C172

2

1

C506
22U_0805_6.3V6M

2

1

C107
22U_0805_6.3V6M

2

1

C530
22U_0805_6.3V6M

2

1

C149
22U_0805_6.3V6M

2

@

1

C173

2

330U_D_2VM

+

1

C505
22U_0805_6.3V6M

2

1

C108
22U_0805_6.3V6M

2

1

C529
22U_0805_6.3V6M

2

1

C150
22U_0805_6.3V6M

2

@

330U_D_2VM

1

+

C171

2

1

+

C532

2

330U_D_2VM

1

C504
22U_0805_6.3V6M

2

1

C109
22U_0805_6.3V6M

2

1

C528
22U_0805_6.3V6M

2

1

C151
22U_0805_6.3V6M

2

@

330U_D_2VM

1

+

C129

2

C523

330U_D_2VM

1

C503
22U_0805_6.3V6M

2

1

C110
22U_0805_6.3V6M

2

1

C527
22U_0805_6.3V6M

2

1

C152
22U_0805_6.3V6M

2

@

330U_D_2VM@

1

+

C491

2

1

C502
22U_0805_6.3V6M

2

1

C111
22U_0805_6.3V6M

2

1

C526
22U_0805_6.3V6M

2

@

1

C153
22U_0805_6.3V6M

2

@

North Side Secondary

1

1

+

+

2

C490

330U_D_2VM@

2

1

C501
22U_0805_6.3V6M

2

1

C112
22U_0805_6.3V6M

2

1

C525
22U_0805_6.3V6M

2

@

1

C154
22U_0805_6.3V6M

2

@

1

C115
22U_0805_6.3V6M

2

1

C113
22U_0805_6.3V6M

2

1

C135
22U_0805_6.3V6M

2

@

1

C155
22U_0805_6.3V6M

2

@

1

C116
22U_0805_6.3V6M

2

1

C114
22U_0805_6.3V6M

2

1

C136
22U_0805_6.3V6M

2

@

1

C156
22U_0805_6.3V6M

2

@

ESR <= 1.5m ohm
Capacitor > 1980uF

Mid Frequence Decoupling

D D

Place these capacitors on L8
(North side,Secondary Layer)

Place these capacitors on L8
(North side,Secondary Layer)

Place these capacitors on L8
(Sorth side,Secondary Layer)

C C

Place these capacitors on L8
(Sorth side,Secondary Layer)

South Side Secondary

B B

+VCCP

1

1

+

C522

330U_D2E_2.5VM_R9

@

A A

+

C531

2

2

1

C513

0.1U_0402_16V4Z

2

330U_D2E_2.5VM_R9

1

C515

0.1U_0402_16V4Z

2

1

C517

0.1U_0402_16V4Z

2

1

C512

0.1U_0402_16V4Z

2

1

C514

0.1U_0402_16V4Z

2

1

C516

0.1U_0402_16V4Z

2

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

Place these inside
socket cavity on L8
(North side
Secondary)

2005/06/01 2006/06/01

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3011

 

401395

05

648, 01, 20

1

of

A

5

4

3

2

1

H_D#[0..63]

D D

C C

+VCCP

12

12

R82

R81

54.9_0402_1%

H_XSCOMP/H_YSCOMP trace

L

width and spacing is 5/20.

B B

A A

54.9_0402_1%

H_VREF
H_XRCOMP
H_XSCOMP
H_YRCOMP
H_YSCOMP
H_SWNG0
H_SWNG1

12

12

R73

R72

24.9_0402_1%

24.9_0402_1%

Layout Note:
H_XRCOMP / H_YRCOMP / H_VREF / H_SWNG0 /
H_SWNG1 trace width and spacing is 18/20.

+VCCP

12

R517

100_0402_1%

H_VREF

12

1

R518

C473

2

200_0402_1%

0.1U_0402_16V4Z

5

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

U6A

F1

HD0#

J1

HD1#

H1

HD2#

J6

HD3#

H3

HD4#

K2

HD5#

G1

HD6#

G2

HD7#

K9

HD8#

K1

HD9#

K7

HD10#

J8

HD11#

H4

HD12#

J3

HD13#

K11

HD14#

G4

HD15#

T10

HD16#

W11

HD17#

T3

HD18#

U7

HD19#

U9

HD20#

U11

HD21#

T11

HD22#

W9

HD23#

T1

HD24#

T8

HD25#

T4

HD26#

W7

HD27#

U5

HD28#

T9

HD29#

W6

HD30#

T5

HD31#

AB7

HD32#

AA9

HD33#

W4

HD34#

W3

HD35#

Y3

HD36#

Y7

HD37#

W5

HD38#

Y10

HD39#

AB8

HD40#

W2

HD41#

AA4

HD42#

AA7

HD43#

AA2

HD44#

AA6

HD45#

AA10

HD46#

Y8

HD47#

AA1

HD48#

AB4

HD49#

AC9

HD50#

AB11

HD51#

AC11

HD52#

AB3

HD53#

AC2

HD54#

AD1

HD55#

AD9

HD56#

AC1

HD57#

AD7

HD58#

AC6

HD59#

AB5

HD60#

AD10

HD61#

AD4

HD62#

AC8

HD63#

J13

HVREF0

K13

HVREF1

E1

HXRCOMP

E2

HXSCOMP

Y1

HYRCOMP

U1

HYSCOMP

E4

HXSWING

W1

HYSWING

CALISTOGA_FCBGA1466~D

PM@

H9

HA3#

C9

HA4#

E11

HA5#

G11

HA6#

F11

HA7#

G12

HA8#

F9

HA9#

H11

HA10#

J12

HA11#

G14

HA12#

D9

HA13#

J14

HA14#

H13

HA15#

J15

HA16#

F14

HA17#

D12

HA18#

A11

HA19#

C11

HA20#

A12

HA21#

A13

HA22#

E13

HA23#

G13

HA24#

F12

HA25#

B12

HA26#

B14

HA27#

C12

HA28#

A14

HA29#

C14

HA30#

D14

HA31#

D8

HREQ#0

G8

HREQ#1

B8

HREQ#2

F8

HREQ#3

A8

HREQ#4

B9

HADSTB#0

C13

HADSTB#1

HCLKN
HCLKP

HDSTBN#0
HDSTBN#1
HDSTBN#2
HDSTBN#3
HDSTBP#0
HDSTBP#1
HDSTBP#2
HDSTBP#3

HDINV#0
HDINV#1
HDINV#2
HDINV#3

HCPURST#

HADS#

HTRDY#

HDPWR#

HDRDY#

HDEFER#

HHITM#

HHIT#

HLOCK#

HBREQ0#

HBNR#

HBPRI#

HDBSY#

HCPUSLP#

HRS0#
HRS1#
HRS2#

12

R557

12

R549

AG1
AG2

K4
T7
Y5
AC4
K3
T6
AA5
AC5

J7
W8
U3
AB10

B7
E8
E7
J9
H8
C3
D4
D3
B3
C7
C6
F6
A7
E3

B4
E6
D6

221_0603_1%

100_0402_1%

HOST

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_ADSTB#0
H_ADSTB#1

CLK_MCH_BCLK#
CLK_MCH_BCLK

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

H_RESET#
H_ADS#
H_TRDY#
H_DPWR#
H_DRDY#
H_DEFER#
H_HITM#
H_HIT#
H_LOCK#
H_BR0#
H_BNR#
H_BPRI#
H_DBSY#
H_CPUSLP#

H_RS#0
H_RS#1
H_RS#2

H_SWNG0

1

C482

2

0.1U_0402_16V4Z

4

+VCCP+VCCP

R87

R84

12

221_0603_1%

12

100_0402_1%

H_A#[3..31]

H_REQ#[0..4]

H_ADSTB#0
H_ADSTB#1

CLK_MCH_BCLK#
CLK_MCH_BCLK
H_DSTBN#[0..3]

H_DSTBP#[0..3]

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

H_RESET#
H_ADS#
H_TRDY#
H_DPWR#
H_DRDY#
H_DEFER#
H_HITM#
H_HIT#
H_LOCK#
H_BR0#
H_BNR#
H_BPRI#
H_DBSY#
H_CPUSLP#

H_RS#[0..2]

H_SWNG1

1

C100

2

0.1U_0402_16V4Z

U6B

AE35

DMIRXN0

AF39

DMIRXN1

AG35

DMIRXN2

AH39

DMIRXN3

AC35

DMIRXP0

AE39

DMIRXP1

AF35

DMIRXP2

AG39

DMIRXP3

AE37

DMITXN0

AF41

DMITXN1

AG37

DMITXN2

AH41

DMITXN3

AC37

DMITXP0

AE41

DMITXP1

AF37

DMITXP2

AG41

DMITXP3

AY35

SM_CK0

AR1

SM_CK1

AW7

SM_CK2

AW40

SM_CK3

AW35

SM_CK0#

AT1

SM_CK1#

AY7

SM_CK2#

AY40

SM_CK3#

AU20

SM_CKE0

AT20

SM_CKE1

BA29

SM_CKE2

AY29

SM_CKE3

AW13

SM_CS0#

AW12

SM_CS1#

AY21

SM_CS2#

AW21

SM_CS3#

AL20

SM_OCDCOMP0

AF10

SM_OCDCOMP1

BA13

SM_ODT0

BA12

SM_ODT1

AY20

SM_ODT2

AU21

SM_ODT3

AV9

SM_RCOMPN

AT9

SM_RCOMPP

AK1

SM_VREF0

AK41

SM_VREF1

G28

PM_BMBUSY#

F25

PM_EXTTS0#

H26

PM_EXTTS1#

G6

PM_THERMTRIP#

AH33

PWROK

AH34

RSTIN#

K28

ICH_SYNC#

CALISTOGA_FCBGA1466~D

PM@

Layout Note:
Route as short
as possible

12

R503

R519

40.2_0402_1%

40.2_0402_1%

12

DMI

DDR MUXING

M_OCDOCMP0
M_OCDOCMP1

DPRSLPVR

V_DDR_MCH_REF

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3

M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3

DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

+1.8V

R520 80.6_0402_1%
R515 80.6_0402_1%

R495 0_0402_5%

PLT_RST#

M_ODT0
M_ODT1
M_ODT2
M_ODT3

1 2
1 2

V_DDR_MCH_REF

PM_BMBUSY#

1 2

H_THERMTRIP#

@

R40 100_0402_1%

MCH_ICH_SYNC#

Layout Note:
V_DDR_MCH_REF
trace width and
spacing is 20/20.

V_DDR_MCH_REF

1

C101

2

0.1U_0402_16V4Z

PWROK

+1.8V

12

R83

12

R74

12

100_0402_1%

100_0402_1%

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3

M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3

DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

M_OCDOCMP0
M_OCDOCMP1

M_ODT0
M_ODT1
M_ODT2
M_ODT3

SMRCOMPN
SMRCOMPP

PM_BMBUSY#
PM_EXTTS#0
PM_EXTTS#1
H_THERMTRIP#
PWROK
PLTRST_R#

Stuff R531 & R532 for A1 Calistoga

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/06/01 2006/06/01

Compal Secret Data

Deciphered Date

2

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8

CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16

CFG

CFG17
CFG18
CFG19
CFG20

G_CLKP
G_CLKN

D_REF_CLKN
D_REF_CLKP

CLKNC

D_REF_SSCLKN
D_REF_SSCLKP

CLK_REQ#

NC0
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8

NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18

RESERVED1
RESERVED2

PM

RESERVED3
RESERVED4
RESERVED5
RESERVED6
RESERVED7
RESERVED8

RESERVED9
RESERVED10
RESERVED11
RESERVED12
RESERVED13

RESERVED

PM_EXTTS#0

PM_EXTTS#1

Title

SCHEMATIC, M/B LA-3011

Size Document Number Rev

Date: Sheet

 

Description at page11.

MCH_CLKSEL0

K16

MCH_CLKSEL1

K18

MCH_CLKSEL2

J18

CFG3

F18

CFG4

E15

CFG5

F15

CFG6

E18

CFG7

D19

CFG8

D16

CFG9

G16

CFG10

E16

CFG11

D15

CFG12

G15

CFG13

K15

CFG14

C15

CFG15

H16

CFG16

G18

CFG17

H15

CFG18

J25

CFG19

K27

CFG20

J26

CLK_MCH_3GPLL

AG33

CLK_MCH_3GPLL#

AF33

GMCH_A27

A27

GMCH_A26

A26

GMCH_C40

C40

GMCH_D41

D41

MCH_CLKREQ#

H32

A3
A39
A4
A40
AW1
AW41
AY1
BA1
BA2
BA3
BA39
BA40
BA41
C1
AY41
B2
B41
C41
D1

T32
R32
F3
F7
AG11
AF11
H7
J19
A41
A34
D28
D27
A35

R481

10K_0402_5%

R494

10K_0402_5%

@
@

@
@
@

@
@

@

12

12

PAD
PAD

PAD
PAD
PAD

PAD
PAD

PAD

+3VS

MCH_CLKSEL0
MCH_CLKSEL1

MCH_CLKSEL2

T16
T20

CFG5

T14

CFG7

T18

CFG9

T17

CFG11

CFG12

CFG13

T21
T15

CFG16

T22

CFG18

CFG19

CFG20

CLK_MCH_3GPLL

CLK_MCH_3GPLL#

CLK_MCH_DREFCLK#

CLK_MCH_DREFCLK

MCH_SSCDREFCLK#

MCH_SSCDREFCLK

MCH_CLKREQ#

Compal Electronics, Inc.

401395

05

748, 01, 20

1

A

of

5

D D

4

3

2

1

DDR_A_BS#0
DDR_A_BS#1
DDR_A_BS#2

DDR_A_DM[0..7]

DDR_A_DQS[0..7]

C C

DDR_A_DQS#[0..7]

DDR_A_MA[0..13]

B B

DDR_A_CAS#
DDR_A_RAS#

DDR_A_WE#

T7 PAD
T6 PAD

DDR_A_BS#0
DDR_A_BS#1
DDR_A_BS#2

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5

DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11 DDR_B_MA11
DDR_A_MA12
DDR_A_MA13

DDR_A_CAS#
DDR_A_RAS#
DDR_A_WE#
SA_RCVENIN#
SA_RCVENOUT#

U6D

AU12

SA_BS0

AV14

SA_BS1

BA20

SA_BS2

AJ33

SA_DM0

AM35

SA_DM1

AL26

SA_DM2

AN22

SA_DM3

AM14

SA_DM4

AL9

SA_DM5

AR3

SA_DM6

AH4

SA_DM7

AK33

SA_DQS0

AT33

SA_DQS1

AN28

SA_DQS2

AM22

SA_DQS3

AN12

SA_DQS4

AN8

SA_DQS5

AP3

SA_DQS6

AG5

SA_DQS7

AK32

SA_DQS0#

AU33

SA_DQS1#

AN27

SA_DQS2#

AM21

SA_DQS3#

AM12

SA_DQS4#

AL8

SA_DQS5#

AN3

SA_DQS6#

AH5

SA_DQS7#

AY16

SA_MA0

AU14

SA_MA1

AW16

SA_MA2

BA16

SA_MA3

BA17

SA_MA4

AU16

SA_MA5

AV17

SA_MA6

AU17

SA_MA7

AW17

SA_MA8

AT16

SA_MA9

AU13

SA_MA10

AT17

SA_MA11

AV20

SA_MA12

AV12

SA_MA13

AY13

SA_CAS#

AW14

SA_RAS#

AY14

SA_WE#

AK23

SA_RCVENIN#

AK24

SA_RCVENOUT#

CALISTOGA_FCBGA1466~D

PM@

SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8

SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39

DDR SYS MEMORY A

SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63

AJ35
AJ34
AM31
AM33
AJ36
AK35
AJ32
AH31
AN35
AP33
AR31
AP31
AN38
AM36
AM34
AN33
AK26
AL27
AM26
AN24
AK28
AL28
AM24
AP26
AP23
AL22
AP21
AN20
AL23
AP24
AP20
AT21
AR12
AR14
AP13
AP12
AT13
AT12
AL14
AL12
AK9
AN7
AK8
AK7
AP9
AN9
AT5
AL5
AY2
AW2
AP1
AN2
AV2
AT3
AN1
AL2
AG7
AF9
AG4
AF6
AG9
AH6
AF4
AF8

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

DDR_A_D[0..63] DDR_B_D[0..63]

DDR_B_BS#0
DDR_B_BS#1
DDR_B_BS#2

DDR_B_DM[0..7]

DDR_B_DQS[0..7]

DDR_B_DQS#[0..7]

DDR_B_MA[0..13]

DDR_B_CAS#

DDR_B_RAS#

DDR_B_WE#

T19 PAD
T13 PAD

DDR_B_BS#0
DDR_B_BS#1
DDR_B_BS#2

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6DDR_A_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10

DDR_B_MA12
DDR_B_MA13

DDR_B_CAS#
DDR_B_RAS#
DDR_B_WE#
SB_RCVENIN#
SB_RCVENOUT#

U6E

AT24

SB_BS0

AV23

SB_BS1

AY28

SB_BS2

AK36

SB_DM0

AR38

SB_DM1

AT36

SB_DM2

BA31

SB_DM3

AL17

SB_DM4

AH8

SB_DM5

BA5

SB_DM6

AN4

SB_DM7

AM39

SB_DQS0

AT39

SB_DQS1

AU35

SB_DQS2

AR29

SB_DQS3

AR16

SB_DQS4

AR10

SB_DQS5

AR7

SB_DQS6

AN5

SB_DQS7

AM40

SB_DQS0#

AU39

SB_DQS1#

AT35

SB_DQS2#

AP29

SB_DQS3#

AP16

SB_DQS4#

AT10

SB_DQS5#

AT7

SB_DQS6#

AP5

SB_DQS7#

AY23

SB_MA0

AW24

SB_MA1

AY24

SB_MA2

AR28

SB_MA3

AT27

SB_MA4

AT28

SB_MA5

AU27

SB_MA6

AV28

SB_MA7

AV27

SB_MA8

AW27

SB_MA9

AV24

SB_MA10

BA27

SB_MA11

AY27

SB_MA12

AR23

SB_MA13

AR24

SB_CAS#

AU23

SB_RAS#

AR27

SB_WE#

AK16

SB_RCVENIN#

AK18

SB_RCVENOUT#

CALISTOGA_FCBGA1466~D

PM@

AK39

SB_DQ0

AJ37

SB_DQ1

AP39

SB_DQ2

AR41

SB_DQ3

AJ38

SB_DQ4

AK38

SB_DQ5

AN41

SB_DQ6

AP41

SB_DQ7

AT40

SB_DQ8

AV41

SB_DQ9

AU38

SB_DQ10

AV38

SB_DQ11

AP38

SB_DQ12

AR40

SB_DQ13

AW38

SB_DQ14

AY38

SB_DQ15

BA38

SB_DQ16

AV36

SB_DQ17

AR36

SB_DQ18

AP36

SB_DQ19

BA36

SB_DQ20

AU36

SB_DQ21

AP35

SB_DQ22

AP34

SB_DQ23

AY33

SB_DQ24

BA33

SB_DQ25

AT31

SB_DQ26

AU29

SB_DQ27

AU31

SB_DQ28

AW31

SB_DQ29

AV29

SB_DQ30

AW29

SB_DQ31

AM19

SB_DQ32

AL19

SB_DQ33

AP14

SB_DQ34

AN14

SB_DQ35

AN17

SB_DQ36

AM16

SB_DQ37

AP15

SB_DQ38

AL15

SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63

AJ11
AH10
AJ9
AN10
AK13
AH11
AK10
AJ8
BA10
AW10
BA4
AW4
AY10
AY9
AW5
AY5
AV4
AR5
AK4
AK3
AT4
AK5
AJ5
AJ3

DDR SYS MEMORY B

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/06/01 2006/06/01

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3011

 

401395

05

848, 01, 20

1

A

of

5

4

3

2

1

PCIE_MTX_C_GRX_N[0..15]
PCIE_MTX_C_GRX_P[0..15]

PCIE_GTX_C_MRX_N[0..15]

D D

+3VS

GM@

R56 2.2K_0402_5%
R57 2.2K_0402_5%
R483 2.2K_0402_5%
R60 2.2K_0402_5%
R480 10K_0402_5%
R478 10K_0402_5%

R484 100K_0402_5%

C C

B B

R55 1.5K_0402_1%
R69 75_0402_1%
R68 150_0402_1%
R67 150_0402_1%

R8 100K_0402_5%

GM@

1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2
1 2

1 2

12
12

LDDC_CLK

LDDC_DATA
GMCH_CRT_CLK
GMCH_CRT_DATA

LCTLB_DATA

LCTLA_CLK

GMCH_ENBKL
LIBG
GMCH_TV_COMPS
GMCH_TV_LUMA
GMCH_TV_CRMA
GMCH_ENVDD

GMCH_CRT_R
GMCH_CRT_G
GMCH_CRT_B

GMCH_TV_LUMA
GMCH_TV_CRMA

GMCH_TXOUT0+
GMCH_TXOUT1+
GMCH_TXOUT2+

GMCH_TXOUT0­GMCH_TXOUT1­GMCH_TXOUT2-

GMCH_TZOUT0+
GMCH_TZOUT1+
GMCH_TZOUT2+

GMCH_TZOUT0­GMCH_TZOUT1­GMCH_TZOUT2-

GMCH_TXCLK+
GMCH_TXCLK­GMCH_TZCLK+
GMCH_TZCLK-

GMCH_ENBKL

GMCH_LCD_CLK

GMCH_LCD_DATA

GMCH_ENVDD

GMCH_TV_COMPS
GMCH_TV_LUMA
GMCH_TV_CRMA

R504 4.99K_0402_1%

GMCH_CRT_CLK
GMCH_CRT_DATA

GMCH_CRT_VSYNC
GMCH_CRT_HSYNC

12

GM@
GM@
GM@

12
12
12

R493 150_0402_5%
R498 150_0402_5%
R502 150_0402_5%

GMCH_TXOUT0+
GMCH_TXOUT1+
GMCH_TXOUT2+

GMCH_TXOUT0­GMCH_TXOUT1­GMCH_TXOUT2-

GMCH_TZOUT0+
GMCH_TZOUT1+
GMCH_TZOUT2+

GMCH_TZOUT0­GMCH_TZOUT1­GMCH_TZOUT2-

GMCH_TXCLK+
GMCH_TXCLK­GMCH_TZCLK+
GMCH_TZCLK-

GMCH_ENBKL
LCTLA_CLK
LCTLB_DATA
LDDC_CLK
LDDC_DATA
GMCH_ENVDD
LIBG

TV_REFSET

R505 0_0402_5%

GMCH_CRT_CLK
GMCH_CRT_DATA

12

1 2

R499 255_0402_1%

U6C

H27

SDVOCTRL_DATA

H28

SDVOCTRL_CLK

B37

LA_DATA0

B34

LA_DATA1

A36

LA_DATA2

C37

LA_DATA#0

B35

LA_DATA#1

A37

LA_DATA#2

F30

LB_DATA0

D29

LB_DATA1

F28

LB_DATA2

G30

LB_DATA#0

D30

LB_DATA#1

F29

LB_DATA#2

A32

LA_CLK

A33

LA_CLK#

E26

LB_CLK

E27

LB_CLK#

D32

LBKLT_CTL

J30

LBKLT_EN

H30

LCTLA_CLK

H29

LCTLB_DATA

G26

LDDC_CLK

G25

LDDC_DATA

F32

LVDD_EN

B38

LIBG

C35

LVBG

C33

LVREFH

C32

LVREFL

A16

TVDAC_A

C18

TVDAC_B

A19

TVDAC_C

J20

TV_IREF

B16

TV_IRTNA

B18

TV_IRTNB

B19

TV_IRTNC

J29

TV_DCONSEL1

K30

TV_DCONSEL0

C26

DDCCLK

C25

DDCDATA

H23

VSYNC

G23

HSYNC

E23

BLUE

D23

BLUE#

C22

GREEN

B22

GREEN#

A21

RED

B21

RED#

J22

CRT_IREF

CALISTOGA_FCBGA1466~D

PM@

LVDS

TV CRT

PCI-EXPRESS GRAPHICS

PCIE_GTX_C_MRX_P[0..15]

PEGCOMP tr ace width

L

and spacing is 18/25 mils.

D40

EXP_COMPI

EXP_RXN0
EXP_RXN1
EXP_RXN2
EXP_RXN3
EXP_RXN4
EXP_RXN5
EXP_RXN6
EXP_RXN7
EXP_RXN8

EXP_RXN9
EXP_RXN10
EXP_RXN11
EXP_RXN12
EXP_RXN13
EXP_RXN14
EXP_RXN15

EXP_RXP0

EXP_RXP1

EXP_RXP2

EXP_RXP3

EXP_RXP4

EXP_RXP5

EXP_RXP6

EXP_RXP7

EXP_RXP8

EXP_RXP9
EXP_RXP10
EXP_RXP11
EXP_RXP12
EXP_RXP13
EXP_RXP14
EXP_RXP15

EXP_TXN0

EXP_TXN1

EXP_TXN2

EXP_TXN3

EXP_TXN4

EXP_TXN5

EXP_TXN6

EXP_TXN7

EXP_TXN8

EXP_TXN9
EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15

EXP_TXP0
EXP_TXP1
EXP_TXP2
EXP_TXP3
EXP_TXP4
EXP_TXP5
EXP_TXP6
EXP_TXP7
EXP_TXP8

EXP_TXP9
EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15

D38
F34

G38
H34
J38
L34
M38
N34
P38
R34
T38
V34
W38
Y34
AA38
AB34
AC38

D34
F38
G34
H38
J34
L38
M34
N38
P34
R38
T34
V38
W34
Y38
AA34
AB38

F36
G40
H36
J40
L36
M40
N36
P40
R36
T40
V36
W40
Y36
AA40
AB36
AC40

D36
F40
G36
H40
J36
L40
M36
N40
P36
R40
T36
V40
W36
Y40
AA36
AB40

EXP_COMPO

PEGCOMP

PCEI_GTX_C_MRX_N0
PCEI_GTX_C_MRX_N1
PCEI_GTX_C_MRX_N2
PCEI_GTX_C_MRX_N3
PCEI_GTX_C_MRX_N4
PCEI_GTX_C_MRX_N5
PCEI_GTX_C_MRX_N6
PCEI_GTX_C_MRX_N7
PCEI_GTX_C_MRX_N8
PCEI_GTX_C_MRX_N9
PCEI_GTX_C_MRX_N10
PCEI_GTX_C_MRX_N11
PCEI_GTX_C_MRX_N12
PCEI_GTX_C_MRX_N13
PCEI_GTX_C_MRX_N14
PCEI_GTX_C_MRX_N15

PCEI_GTX_C_MRX_P0
PCEI_GTX_C_MRX_P1
PCEI_GTX_C_MRX_P2
PCEI_GTX_C_MRX_P3
PCEI_GTX_C_MRX_P4
PCEI_GTX_C_MRX_P5
PCEI_GTX_C_MRX_P6
PCEI_GTX_C_MRX_P7
PCEI_GTX_C_MRX_P8
PCEI_GTX_C_MRX_P9
PCEI_GTX_C_MRX_P10
PCEI_GTX_C_MRX_P11
PCEI_GTX_C_MRX_P12
PCEI_GTX_C_MRX_P13
PCEI_GTX_C_MRX_P14
PCEI_GTX_C_MRX_P15

PCIE_MTX_C_GRX_N[0..15]

PCIE_MTX_C_GRX_P[0..15]
PCEI_GTX_C_MRX_N[0..15]
PCEI_GTX_C_MRX_P[0..15]

R472

24.9_0402_1%

1 2

C400 0.1U_0402_16V7KPM@
C36 0.1U_0402_16V7KPM@
C384 0.1U_0402_16V7KPM@
C25 0.1U_0402_16V7KPM@
C398 0.1U_0402_16V7KPM@
C38 0.1U_0402_16V7KPM@
C382 0.1U_0402_16V7KPM@
C27 0.1U_0402_16V7KPM@
C396 0.1U_0402_16V7KPM@
C40 0.1U_0402_16V7KPM@
C380 0.1U_0402_16V7KPM@
C29 0.1U_0402_16V7KPM@
C394 0.1U_0402_16V7KPM@
C42 0.1U_0402_16V7KPM@
C387 0.1U_0402_16V7KPM@
C31 0.1U_0402_16V7KPM@

C401 0.1U_0402_16V7KPM@
C35 0.1U_0402_16V7KPM@
C385 0.1U_0402_16V7KPM@
C24 0.1U_0402_16V7KPM@
C399 0.1U_0402_16V7KPM@
C37 0.1U_0402_16V7KPM@
C383 0.1U_0402_16V7KPM@
C26 0.1U_0402_16V7KPM@
C397 0.1U_0402_16V7KPM@
C39 0.1U_0402_16V7KPM@
C381 0.1U_0402_16V7KPM@
C28 0.1U_0402_16V7KPM@
C395 0.1U_0402_16V7KPM@
C41 0.1U_0402_16V7KPM@
C388 0.1U_0402_16V7KPM@
C30 0.1U_0402_16V7KPM@

+1.5VS_PCIE

PCIE_MTX_C_GRX_N0
PCIE_MTX_C_GRX_N1
PCIE_MTX_C_GRX_N2
PCIE_MTX_C_GRX_N3
PCIE_MTX_C_GRX_N4
PCIE_MTX_C_GRX_N5
PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_N7
PCIE_MTX_C_GRX_N8

PCIE_MTX_C_GRX_N9
PCIE_MTX_C_GRX_N10
PCIE_MTX_C_GRX_N11
PCIE_MTX_C_GRX_N12
PCIE_MTX_C_GRX_N13
PCIE_MTX_C_GRX_N14
PCIE_MTX_C_GRX_N15

PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_P13
PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_P15

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/06/01 2006/06/01

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3011

 

401395

05

948, 01, 20

1

A

of

5

4

3

2

1

R508

0_0805_5%

C460

0.1U_0402_16V4Z

R41

1 2

0.5_0805_1%

1

C34

2

1

C484

2

0.1U_0402_16V4Z

1

+

C417

2

0.1U_0402_16V4Z~D

GM@

Deciphered Date

+2.5VS

1

2

12

1

C416

2

0.1U_0402_16V4Z

C418

1

2

0.1U_0402_16V4Z

1

C55

2

1

C427

2

0.1U_0402_16V4Z

1

2

2200P_0402_50V7K

C430

0.1U_0402_16V4Z

0_0805_5%

C57

0.1U_0402_16V4Z

R62

12

1

2

PCI-E/MEM/FSB PLL decoupling

R550

0_0805_5%

1

C483
10U_0805_6.3V6M

2

R470

0_0805_5%

1

C419

2

330U_D2E_2.5VM_R9

R42

0_0805_5%

12

12

2

+1.5VS+1.5VS_3GPLL

12

C44

+1.5VS

+1.5VS_TVDAC +1.5VS

0.022U_0402_16V7K

1

2

0.1U_0402_16V4Z

@

1

C462

2

+1.5VS_HPLL

1

C493

2

Title

Size Document Number Rev

Date: Sheet

0_0805_5%

1

C449

2

10U_0805_6.3V6M

@

R560

0_0805_5%

1

C494
10U_0805_6.3V6M

2

0.1U_0402_16V4Z

1

2

Compal Electronics, Inc.

SCHEMATIC , M / B L A-3011

 

R58

C441

C464

2200P_0402_50V7K

1

+

2

0.1U_0402_16V4Z~D

GM@

401395

1

C465

2

12

12

R59

0_0805_5%

C434

330U_D2E_2.5VM_R9

R511

0_0805_5%

0.1U_0402_16V4Z

1

C53

0.022U_0402_16V7K

2

+1.5VS+1.5VS

12

1

12

+1.5VS

+3VS+3VS_TVDACA+3VS+3VS_TVDACB+3VS+3VS_TVDACC

A

of

10 48¬P , 01, 2005

D D

1

+

C497

C425

5

2

1

C480

2

4.7U_0805_10V4Z

1

2

0.22U_0603_10V7K

C511

C438

1

2

330U_D2E_2.5VM_R9

C C

B B

A A

1

+

2

1

2

2.2U_0805_16V4Z

MCH_A6

1

C93

2

MCH_D2

C102

0.22U_0603_10V7K

C103

+1.5VS

+VCCP

330U_D2E_2.5VM_R9

@

0.47U_0603_10V7K

MCH_AB1

1

2

0.47U_0603_10V7K

U6H

AC14

VTT0

AB14

VTT1

W14

VTT2

V14

VTT3

T14

VTT4

R14

VTT5

P14

VTT6

N14

VTT7

M14

VTT8

L14

VTT9

AD13

VTT10

AC13

VTT11

AB13

VTT12

AA13

VTT13

Y13

VTT14

W13

VTT15

V13

VTT16

U13

VTT17

T13

VTT18

R13

VTT19

N13

VTT20

M13

VTT21

L13

VTT22

AB12

VTT23

AA12

VTT24

Y12

VTT25

W12

VTT26

V12

VTT27

U12

VTT28

T12

VTT29

R12

VTT30

P12

VTT31

N12

VTT32

M12

VTT33

L12

VTT34

R11

VTT35

P11

VTT36

N11

VTT37

M11

VTT38

R10

VTT39

P10

VTT40

N10

VTT41

M10

VTT42

P9

VTT43

N9

VTT44

M9

VTT45

R8

VTT46

P8

VTT47

N8

VTT48

M8

VTT49

P7

VTT50

N7

VTT51

M7

VTT52

R6

VTT53

P6

VTT54

M6

VTT55

A6

VTT56

R5

VTT57

P5

VTT58

N5

VTT59

M5

VTT60

P4

VTT61

N4

VTT62

M4

VTT63

R3

VTT64

P3

VTT65

N3

VTT66

M3

VTT67

R2

VTT68

P2

VTT69

M2

VTT70

D2

VTT71

AB1

VTT72

R1

VTT73

P1

VTT74

N1

VTT75

M1

VTT76

AG14

VCCAUX32

AF14

VCCAUX33

AE14

VCCAUX34

Y14

VCCAUX35

AF13

VCCAUX36

AE13

VCCAUX37

AF12

VCCAUX38

AE12

VCCAUX39

AD12

VCCAUX40

CALISTOGA_FCBGA1466~D

PM@

P O W E R

VCCTX_LVDS0
VCCTX_LVDS1
VCCTX_LVDS2

VCCA_CRTDAC0
VCCA_CRTDAC1
VSSA_CRTDAC2

VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1

VCCD_HMPLL0
VCCD_HMPLL1

VCCDQ_TVDAC

4

VCC_SYNC

VCC3G0
VCC3G1
VCC3G2
VCC3G3
VCC3G4
VCC3G5
VCC3G6

VCCA_3GPLL

VCCA_3GBG
VSSA_3GBG

VCCA_DPLLA
VCCA_DPLLB

VCCA_HPLL

VCCA_LVDS

VSSA_LVDS

VCCA_MPLL
VCCA_TVBG

VSSA_TVBG

VCCD_LVDS0
VCCD_LVDS1
VCCD_LVDS2

VCCD_TVDAC

VCCHV0
VCCHV1
VCCHV2

VCCAUX0
VCCAUX1
VCCAUX2
VCCAUX3
VCCAUX4
VCCAUX5
VCCAUX6
VCCAUX7
VCCAUX8

VCCAUX9
VCCAUX10
VCCAUX11
VCCAUX12
VCCAUX13
VCCAUX14
VCCAUX15
VCCAUX16
VCCAUX17
VCCAUX18
VCCAUX19
VCCAUX20
VCCAUX21
VCCAUX22
VCCAUX23
VCCAUX24
VCCAUX25
VCCAUX26
VCCAUX27
VCCAUX28
VCCAUX29
VCCAUX30
VCCAUX31

H22

B30
C30
A30

AB41
AJ41
L41
N41
R41
V41
Y41

AC33
G41
H41

E21
F21
G21

B26
C39
AF1

A38
B39

AF2
H20

G20

E19
F19
C20
D20
E20
F20

AH1
AH2

A28
B28
C28

D21
H19

A23
B23
B25

AK31
AF31
AE31
AC31
AL30
AK30
AJ30
AH30
AG30
AF30
AE30
AD30
AC30
AG29
AF29
AE29
AD29
AC29
AG28
AF28
AE28
AH22
AJ21
AH21
AJ20
AH20
AH19
P19
P16
AH15
P15
AH14

+2.5VS

+2.5VS

W=40 mils

+1.5VS_3GPLL
+2.5VS

+2.5VS_CRTDAC

+1.5VS_DPLLA
+1.5VS_DPLLB
+1.5VS_HPLL

+2.5VS

+1.5VS_MPLL
+3VS_TVBG

+3VS_TVDACA
+3VS_TVDACB
+3VS_TVDACC

+1.5VS

+1.5VS_TVDAC

+1.5VS

1

C470

2

220U_D2_4VM

@

1

2

C450

0.1U_0402_16V4Z

1

+

C23

2

220U_D2_4VM

1

2

+1.5VS_PCIE

10U_0805_6.3V6M

1

1

+

C379

2

2

L14 BLM11A601S_0603

1 2

1

C457

C456

2

2200P_0402_50V7K

+3VS

1

C453
10U_0805_6.3V6M

2

0.1U_0402_16V4Z

C405

R467

0_0805_5%

C406

1

10U_0805_6.3V6M

2

+2.5VS

12

+1.5VS

1

1

C461

2

2

2200P_0402_50V7K

1

C43

2

0.1U_0402_16V4Z
10U_0805_6.3V6M

+1.5VS_MPLL

45mA Max. 45mA Max.

0.1U_0402_16V4Z

+3VS+3VS_TVBG

R70

12

0_0805_5%

1

1

C77

2

2

C81

0.1U_0402_16V4Z

2200P_0402_50V7K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/06/01 2006/06/01

+1.5VS_DPLLB +1.5VS_DPLLA

40mA Max. 40mA Max.

Compal Secret Data

5

4

3

2

1

Strap Pin Table

CFG[3:17] have internal pull up

+VCCP

D D

1

1

1

C475

C467

C454

2

0.22U_0603_10V7K

10U_0805_6.3V6M

1

C485

C466

2

10U_0805_6.3V6M

C C

C99

330U_D2E_2.5VM_R9

@

C495

330U_D2E_2.5VM_R9

B B

2

2

0.22U_0603_10V7K

0.22U_0603_10V7K

1

1

C435

2

2

1U_0603_10V4Z

330U_D2E_2.5VM_R9

1

1

+

+

C492

2

2

1

+

2

+VCCP

U6F

AD27

VCC_NCTF0

AC27

VCC_NCTF1

AB27

VCC_NCTF2

AA27

VCC_NCTF3

Y27

VCC_NCTF4

W27

VCC_NCTF5

V27

VCC_NCTF6

U27

VCC_NCTF7

T27

VCC_NCTF8

R27

VCC_NCTF9

AD26

VCC_NCTF10

AC26

VCC_NCTF11

AB26

VCC_NCTF12

AA26

VCC_NCTF13

Y26

VCC_NCTF14

W26

VCC_NCTF15

V26

VCC_NCTF16

U26

VCC_NCTF17

T26

VCC_NCTF18

R26

VCC_NCTF19

AD25

VCC_NCTF20

AC25

VCC_NCTF21

AB25

VCC_NCTF22

AA25

VCC_NCTF23

Y25

VCC_NCTF24

W25

VCC_NCTF25

V25

VCC_NCTF26

U25

VCC_NCTF27

T25

VCC_NCTF28

R25

VCC_NCTF29

AD24

VCC_NCTF30

AC24

VCC_NCTF31

AB24

VCC_NCTF32

AA24

VCC_NCTF33

Y24

VCC_NCTF34

W24

VCC_NCTF35

V24

VCC_NCTF36

U24

VCC_NCTF37

T24

VCC_NCTF38

R24

VCC_NCTF39

AD23

VCC_NCTF40

V23

VCC_NCTF41

U23

VCC_NCTF42

T23

VCC_NCTF43

R23

VCC_NCTF44

AD22

VCC_NCTF45

V22

VCC_NCTF46

U22

VCC_NCTF47

T22

VCC_NCTF48

R22

VCC_NCTF49

AD21

VCC_NCTF50

V21

VCC_NCTF51

U21

VCC_NCTF52

T21

VCC_NCTF53

R21

VCC_NCTF54

AD20

VCC_NCTF55

V20

VCC_NCTF56

U20

VCC_NCTF57

T20

VCC_NCTF58

R20

VCC_NCTF59

AD19

VCC_NCTF60

V19

VCC_NCTF61

U19

VCC_NCTF62

T19

VCC_NCTF63

AD18

VCC_NCTF64

AC18

VCC_NCTF65

AB18

VCC_NCTF66

AA18

VCC_NCTF67

Y18

VCC_NCTF68

W18

VCC_NCTF69

V18

VCC_NCTF70

U18

VCC_NCTF71

T18

VCC_NCTF72

M19

VCC100

L19

VCC101

N18

VCC102

M18

VCC103

L18

VCC104

P17

VCC105

N17

VCC106

M17

VCC107

N16

VCC108

M16

VCC109

L16

VCC110

CALISTOGA_FCBGA1466~D

PM@

VCCAUX_NCTF0
VCCAUX_NCTF1
VCCAUX_NCTF2
VCCAUX_NCTF3
VCCAUX_NCTF4
VCCAUX_NCTF5
VCCAUX_NCTF6
VCCAUX_NCTF7
VCCAUX_NCTF8

VCCAUX_NCTF9
VCCAUX_NCTF10
VCCAUX_NCTF11
VCCAUX_NCTF12
VCCAUX_NCTF13
VCCAUX_NCTF14
VCCAUX_NCTF15
VCCAUX_NCTF16
VCCAUX_NCTF17
VCCAUX_NCTF18
VCCAUX_NCTF19
VCCAUX_NCTF20
VCCAUX_NCTF21
VCCAUX_NCTF22
VCCAUX_NCTF23
VCCAUX_NCTF24
VCCAUX_NCTF25
VCCAUX_NCTF26
VCCAUX_NCTF27
VCCAUX_NCTF28
VCCAUX_NCTF29
VCCAUX_NCTF30
VCCAUX_NCTF31
VCCAUX_NCTF32
VCCAUX_NCTF33
VCCAUX_NCTF34
VCCAUX_NCTF35
VCCAUX_NCTF36

P O W E R

VCCAUX_NCTF37
VCCAUX_NCTF38
VCCAUX_NCTF39
VCCAUX_NCTF40
VCCAUX_NCTF41
VCCAUX_NCTF42
VCCAUX_NCTF43
VCCAUX_NCTF44
VCCAUX_NCTF45
VCCAUX_NCTF46
VCCAUX_NCTF47
VCCAUX_NCTF48
VCCAUX_NCTF49
VCCAUX_NCTF50
VCCAUX_NCTF51
VCCAUX_NCTF52
VCCAUX_NCTF53
VCCAUX_NCTF54
VCCAUX_NCTF55
VCCAUX_NCTF56
VCCAUX_NCTF57

VSS_NCTF0
VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
VSS_NCTF8

VSS_NCTF9
VSS_NCTF10
VSS_NCTF11
VSS_NCTF12

VCC_SM100

VCC_SM101

VCC_SM102

VCC_SM103

VCC_SM104

VCC_SM105

VCC_SM106

VCC_SM107

AG27
AF27
AG26
AF26
AG25
AF25
AG24
AF24
AG23
AF23
AG22
AF22
AG21
AF21
AG20
AF20
AG19
AF19
R19
AG18
AF18
R18
AG17
AF17
AE17
AD17
AB17
AA17
W17
V17
T17
R17
AG16
AF16
AE16
AD16
AC16
AB16
AA16
Y16
W16
V16
U16
T16
R16
AG15
AF15
AE15
AD15
AC15
AB15
AA15
Y15
W15
V15
U15
T15
R15

AE27
AE26
AE25
AE24
AE23
AE22
AE21
AE20
AE19
AE18
AC17
Y17
U17

AR6
AP6
AN6
AL6
AK6
AJ6
AV1
AJ1

+1.5VS

VCCSM_LF2
VCCSM_LF1

C104

+1.8V

0.47U_0603_10V7K

1

1

C105

2

2

0.47U_0603_10V7K

Place near pin AV1 & AJ1

A A

+VCCP

AA33

AA32

AA31

AA30

AA29

AB28
AA28

AB23
AA23

AC22
AB22

AC21
AA21

AC20
AB20

AB19
AA19

U6G

VCC0

W33

VCC1

P33

VCC2

N33

VCC3

L33

VCC4

J33

VCC5
VCC6

Y32

VCC7

W32

VCC8

V32

VCC9

P32

VCC10

N32

VCC11

M32

VCC12

L32

VCC13

J32

VCC14
VCC15

W31

VCC16

V31

VCC17

T31

VCC18

R31

VCC19

P31

VCC20

N31

VCC21

M31

VCC22
VCC23

Y30

VCC24

W30

VCC25

V30

VCC26

U30

VCC27

T30

VCC28

R30

VCC29

P30

VCC30

N30

VCC31

M30

VCC32

P O W E R

VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75
VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC82
VCC83
VCC84
VCC85
VCC86
VCC87
VCC88
VCC89
VCC90
VCC91
VCC92
VCC93
VCC94
VCC95
VCC96
VCC97
VCC98
VCC99

CALISTOGA_FCBGA1466~D

PM@

W29

W22

W21

W20

L30
Y29

V29
U29
R29

P29
M29

L29

Y28

V28
U28

T28
R28

P28
N28
M28

L28

P27
N27
M27

L27

P26
N26

L26
N25
M25

L25

P24
N24
M24

Y23

P23
N23
M23

L23

Y22

P22
N22
M22

L22

N21
M21

L21

Y20

P20
N20
M20

L20

Y19
N19

VCC_SM0
VCC_SM1
VCC_SM2
VCC_SM3
VCC_SM4
VCC_SM5
VCC_SM6
VCC_SM7
VCC_SM8

VCC_SM9
VCC_SM10
VCC_SM11
VCC_SM12
VCC_SM13
VCC_SM14
VCC_SM15
VCC_SM16
VCC_SM17
VCC_SM18
VCC_SM19
VCC_SM20
VCC_SM21
VCC_SM22
VCC_SM23
VCC_SM24
VCC_SM25
VCC_SM26
VCC_SM27
VCC_SM28
VCC_SM29
VCC_SM30
VCC_SM31
VCC_SM32
VCC_SM33
VCC_SM34
VCC_SM35
VCC_SM36
VCC_SM37
VCC_SM38
VCC_SM39
VCC_SM40
VCC_SM41
VCC_SM42
VCC_SM43
VCC_SM44
VCC_SM45
VCC_SM46
VCC_SM47
VCC_SM48
VCC_SM49
VCC_SM50
VCC_SM51
VCC_SM52
VCC_SM53
VCC_SM54
VCC_SM55
VCC_SM56
VCC_SM57
VCC_SM58
VCC_SM59
VCC_SM60
VCC_SM61
VCC_SM62
VCC_SM63
VCC_SM64
VCC_SM65
VCC_SM66
VCC_SM67
VCC_SM68
VCC_SM69
VCC_SM70
VCC_SM71
VCC_SM72
VCC_SM73
VCC_SM74
VCC_SM75
VCC_SM76
VCC_SM77
VCC_SM78
VCC_SM79
VCC_SM80
VCC_SM81
VCC_SM82
VCC_SM83
VCC_SM84
VCC_SM85
VCC_SM86
VCC_SM87
VCC_SM88
VCC_SM89
VCC_SM90
VCC_SM91
VCC_SM92
VCC_SM93
VCC_SM94
VCC_SM95
VCC_SM96
VCC_SM97
VCC_SM98
VCC_SM99

AU41
AT41
AM41
AU40
BA34
AY34
AW34
AV34
AU34
AT34
AR34
BA30
AY30
AW30
AV30
AU30
AT30
AR30
AP30
AN30
AM30
AM29
AL29
AK29
AJ29
AH29
AJ28
AH28
AJ27
AH27
BA26
AY26
AW26
AV26
AU26
AT26
AR26
AJ26
AH26
AJ25
AH25
AJ24
AH24
BA23
AJ23
BA22
AY22
AW22
AV22
AU22
AT22
AR22
AP22
AK22
AJ22
AK21
AK20
BA19
AY19
AW19
AV19
AU19
AT19
AR19
AP19
AK19
AJ19
AJ18
AJ17
AH17
AJ16
AH16
BA15
AY15
AW15
AV15
AU15
AT15
AR15
AJ15
AJ14
AJ13
AH13
AK12
AJ12
AH12
AG12
AK11
BA8
AY8
AW8
AV8
AT8
AR8
AP8
BA6
AY6
AW6
AV6
AT6

+1.8V

VCCSM_LF4
VCCSM_LF5

C32

0.47U_0603_10V7K

Place near pin AT41 & AM41

C424

C54

0.47U_0603_10V7K

Place near pin BA23

C92

10U_0805_6.3V6M

C71

0.47U_0603_10V7K

Place near pin BA15

1

2

1

2

1

2

1

2

1

2

C33

0.47U_0603_10V7K

0.1U_0402_16V4Z

C52

1

2

1

C481

2

0.1U_0402_16V4Z

1

2

10U_0805_6.3V6M

CFG[2:0]

CFG5

CFG7

CFG9

CFG11

CFG[13:12]

+1.8V

CFG16

1

1

C452

C431

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

CFG18

CFG19

SDVO_CTRLDATA

CFG20

(PCIE/SDVO select)

CFG[19:18] have internal pull down

011 = 667MT/s FSB
001 = 533MT/s FSB

0 = DMI x 2
1 = DMI x 4

0 = Reserved
1 = Mobile Yonah CPU

0 = Lane Reversal Enable
1 = Normal Operation

0 = Calistoga

(According to Intel Napa Schematic Checklist & CRB
Rev1.301 document 2.2Kohm pull-down resistor
request)

1 = Reserved

00 = Reserved
01 = XOR Mode Enabled
10 = All Z Mode Enabled
11 = Normal Operation

0 = Dynamic ODT Disabled
1 = Dynamic ODT Enabled (Default)

0 = 1.05V
1 = 1.5V

0 = Normal Operation
1 = DMI Lane Reversal Enable

0 = No SDVO Device Present

(Default)

(Default)

*

*

(Default)

*

(Default)

*

(Default)

*

*

1 = SDVO Device Present

0 = Only PCIE or SDVO is
operational.
1 = PCIE/SDVO are operating
simu.

CFG5
CFG7

CFG9
CFG11
CFG12
CFG13
CFG16

CFG18
CFG19
CFG20

R513 2.2K_0402_5%@
R507 2.2K_0402_5%@
R509 2.2K_0402_5%@
R514 2.2K_0402_5%
R512 2.2K_0402_5%@
R510 2.2K_0402_5%@
R506 2.2K_0402_5%@

R479 1K_0402_5%@
R482 1K_0402_5%@
R490 1K_0402_5%@

*

1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2

(Default)

*

(Default)

*

(Default)

*

+3VS

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/06/01 2006/06/01

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3011

 

401395

05

11 48, 01, 20

1

A

of

5

4

3

2

1

U6I

AC41

VSS0

AA41

VSS1

W41

VSS2

T41

VSS3

P41

VSS4

M41

D D

C C

B B

A A

VSS5

J41

VSS6

F41

VSS7

AV40

VSS8

AP40

VSS9

AN40

VSS10

AK40

VSS11

AJ40

VSS12

AH40

VSS13

AG40

VSS14

AF40

VSS15

AE40

VSS16

B40

VSS17

AY39

VSS18

AW39

VSS19

AV39

VSS20

AR39

VSS21

AN39

VSS22

AJ39

VSS23

AC39

VSS24

AB39

VSS25

AA39

VSS26

Y39

VSS27

W39

VSS28

V39

VSS29

T39

VSS30

R39

VSS31

P39

VSS32

N39

VSS33

M39

VSS34

L39

VSS35

J39

VSS36

H39

VSS37

G39

VSS38

F39

VSS39

D39

VSS40

AT38

VSS41

AM38

VSS42

AH38

VSS43

AG38

VSS44

AF38

VSS45

AE38

VSS46

C38

VSS47

AK37

VSS48

AH37

VSS49

AB37

VSS50

AA37

VSS51

Y37

VSS52

W37

VSS53

V37

VSS54

T37

VSS55

R37

VSS56

P37

VSS57

N37

VSS58

M37

VSS59

L37

VSS60

J37

VSS61

H37

VSS62

G37

VSS63

F37

VSS64

D37

VSS65

AY36

VSS66

AW36

VSS67

AN36

VSS68

AH36

VSS69

AG36

VSS70

AF36

VSS71

AE36

VSS72

AC36

VSS73

C36

VSS74

B36

VSS75

BA35

VSS76

AV35

VSS77

AR35

VSS78

AH35

VSS79

AB35

VSS80

AA35

VSS81

Y35

VSS82

W35

VSS83

V35

VSS84

T35

VSS85

R35

VSS86

P35

VSS87

N35

VSS88

M35

VSS89

L35

VSS90

J35

VSS91

H35

VSS92

G35

VSS93

F35

VSS94

D35

VSS95

AN34

VSS96

AK34

VSS97

AG34

VSS98

AF34

VSS99

CALISTOGA_FCBGA1466~D

PM@

P O W E R

VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199

AE34
AC34
C34
AW33
AV33
AR33
AE33
AB33
Y33
V33
T33
R33
M33
H33
G33
F33
D33
B33
AH32
AG32
AF32
AE32
AC32
AB32
G32
B32
AY31
AV31
AN31
AJ31
AG31
AB31
Y31
AB30
E30
AT29
AN29
AB29
T29
N29
K29
G29
E29
C29
B29
A29
BA28
AW28
AU28
AP28
AM28
AD28
AC28
W28
J28
E28
AP27
AM27
AK27
J27
G27
F27
C27
B27
AN26
M26
K26
F26
D26
AK25
P25
K25
H25
E25
D25
A25
BA24
AU24
AL24
AW23
AT23
AN23
AM23
AH23
AC23
W23
K23
J23
F23
C23
AA22
K22
G22
F22
E22
D22
A22
BA21
AV21
AR21

U6J

AN21

VSS200

AL21

VSS201

AB21

VSS202

Y21

VSS203

P21

VSS204

K21

VSS205

J21

VSS206

H21

VSS207

C21

VSS208

AW20

VSS209

AR20

VSS210

AM20

VSS211

AA20

VSS212

K20

VSS213

B20

VSS214

A20

VSS215

AN19

VSS216

AC19

VSS217

W19

VSS218

K19

VSS219

G19

VSS220

C19

VSS221

AH18

VSS222

P18

VSS223

H18

VSS224

D18

VSS225

A18

VSS226

AY17

VSS227

AR17

VSS228

AP17

VSS229

AM17

VSS230

AK17

VSS231

AV16

VSS232

AN16

VSS233

AL16

VSS234

J16

VSS235

F16

VSS236

C16

VSS237

AN15

VSS238

AM15

VSS239

AK15

VSS240

N15

VSS241

M15

VSS242

L15

VSS243

B15

VSS244

A15

VSS245

BA14

VSS246

AT14

VSS247

AK14

VSS248

AD14

VSS249

AA14

VSS250

U14

VSS251

K14

VSS252

H14

VSS253

E14

VSS254

AV13

VSS255

AR13

VSS256

AN13

VSS257

AM13

VSS258

AL13

VSS259

AG13

VSS260

P13

VSS261

F13

VSS262

D13

VSS265

B13

VSS264

AY12

VSS263

AC12

VSS266

K12

VSS267

H12

VSS268

E12

VSS269

AD11

VSS270

AA11

VSS271

Y11

VSS272

J11

VSS273

D11

VSS274

B11

VSS275

AV10

VSS276

AP10

VSS277

AL10

VSS278

AJ10

VSS279

CALISTOGA_FCBGA1466~D

PM@

P O W E R

VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
VSS286
VSS287
VSS288
VSS289
VSS290
VSS292
VSS291
VSS293
VSS294
VSS295
VSS296
VSS297
VSS298
VSS299
VSS300
VSS301
VSS302
VSS303
VSS304
VSS305
VSS306
VSS307
VSS308
VSS309
VSS310
VSS311
VSS312
VSS313
VSS314
VSS315
VSS316
VSS317
VSS318
VSS319
VSS320
VSS321
VSS322
VSS323
VSS324
VSS325
VSS326
VSS327
VSS328
VSS329
VSS330
VSS331
VSS332
VSS333
VSS334
VSS335
VSS336
VSS337
VSS338
VSS339
VSS340
VSS341
VSS342
VSS343
VSS344
VSS345
VSS346
VSS347
VSS348
VSS349
VSS350
VSS351
VSS352
VSS353
VSS354
VSS355
VSS356
VSS357
VSS358
VSS359
VSS360

AG10
AC10
W10
U10
BA9
AW9
AR9
AH9
AB9
Y9
R9
G9
E9
A9
AG8
AD8
AA8
U8
K8
C8
BA7
AV7
AP7
AL7
AJ7
AH7
AF7
AC7
R7
G7
D7
AG6
AD6
AB6
Y6
U6
N6
K6
H6
B6
AV5
AF5
AD5
AY4
AR4
AP4
AL4
AJ4
Y4
U4
R4
J4
F4
C4
AY3
AW3
AV3
AL3
AH3
AG3
AF3
AD3
AC3
AA3
G3
AT2
AR2
AP2
AK2
AJ2
AD2
AB2
Y2
U2
T2
N2
J2
H2
F2
C2
AL1

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/06/01 2006/06/01

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3011

 

401395

05

12 48, 01, 20

1

A

of

5

DDR_A_DQS#[0..7]

DDR_A_D[0..63]

DDR_A_DM[0..7]
DDR_A_DQS[0..7]
DDR_A_MA[0..13]

D D

Layout Note:
Place near JP27

+1.8V

2.2U_0805_16V4Z

2.2U_0805_16V4Z

C C

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS

+0.9VS

0.1U_0402_16V4Z

B B

DDR_A_MA5
DDR_A_MA8

DDR_A_MA1
DDR_A_MA3

DDR_A_RAS#
DDR_CS0_DIMMA#

DDR_A_BS#0
DDR_A_MA10

DDR_A_CAS#

A A

DDR_A_WE#

DDR_CS1_DIMMA#
M_ODT1

C95

C59

1

1

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C62

C70

RP34

1 4
2 3

RP35

1 4
2 3

RP17

1 4
2 3

RP36

1 4
2 3

RP37

1 4
2 3

RP38

2 3
1 4

5

2.2U_0805_16V4Z

2.2U_0805_16V4Z
C72

1

2

0.1U_0402_16V4Z

1

1

2

2

C73

C79

+0.9VS

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

C56

1

2

0.1U_0402_16V4Z

1

2

C85

0.1U_0402_16V4Z

2.2U_0805_16V4Z
C89

1

1

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C463

C91

RP32 56_0404_4P2R_5%

DDR_A_BS#2

14

DDR_CKE0_DIMMA

23

RP8 56_0404_4P2R_5%

DDR_A_MA7

14

DDR_A_MA6

23

RP33 56_0404_4P2R_5%

DDR_A_MA9

14

DDR_A_MA12

23

RP11 56_0404_4P2R_5%

DDR_A_MA4

14

DDR_A_MA2

23

RP14 56_0404_4P2R_5%

DDR_A_MA0

14

DDR_A_BS#1

23

RP20 56_0404_4P2R_5%

M_ODT0

14

DDR_A_MA13

23

RP5 56_0404_4P2R_5%

DDR_CKE1_DIMMA

14

DDR_A_MA11

23

0.1U_0402_16V4Z

C65

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C468

4

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C64

1

1

2

2

0.1U_0402_16V4Z

1

1

2

2

C474

C476

Layout Note:
Place these resistor
closely JP27,all
trace length Max=1.5"

C78

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C477

C478

C87

0.1U_0402_16V4Z

1

2

C472

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

DDR_CKE0_DIMMA

DDR_A_BS#2

DDR_A_BS#0

DDR_A_WE#

DDR_A_CAS#

DDR_CS1_DIMMA#

M_ODT1

CLK_SMBDATA

CLK_SMBCLK

3

2

+1.8V

JP19

1

VREF

3

DDR_A_D0
DDR_A_D4

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D2
DDR_A_D3

DDR_A_D8
DDR_A_D14

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D10
DDR_A_D11

DDR_A_D21
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D22
DDR_A_D19 DDR_A_D23

DDR_A_D25
DDR_A_D24

DDR_A_DM3

DDR_A_D27
DDR_A_D30

DDR_CKE0_DIMMA

DDR_A_BS#2
DDR_A_MA12

DDR_A_MA9 DDR_A_MA7
DDR_A_MA8

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#

DDR_A_CAS#
DDR_CS1_DIMMA#

M_ODT1
DDR_A_D34

DDR_A_D38
DDR_A_DQS#4

DDR_A_DQS4
DDR_A_D39

DDR_A_D35
DDR_A_D45

DDR_A_D41
DDR_A_DM5
DDR_A_D42

DDR_A_D43
DDR_A_D52

DDR_A_D53

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D55
DDR_A_D56

DDR_A_D61
DDR_A_DM7
DDR_A_D58

DDR_A_D59
CLK_SMBDATA

CLK_SMBCLK

+3VS

1

C126

0.1U_0402_16V4Z

2005/06/01 2006/06/01

2

Compal Secret Data

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

PTI_A5652D-A0G16-P

SO-DIMM A

Deciphered Date

DQ4
DQ5

DM0
DQ6

DQ7

DQ12
DQ13

DM1

CK0#
DQ14

DQ15

DQ20
DQ21

DM2

DQ22
DQ23

DQ28
DQ29

DQS3#

DQS3
DQ30

DQ31

NC/CKE1

VDD
NC/A15
NC/A14

VDD

VDD

VDD

RAS#

VDD

ODT0

NC/A13

VDD

DQ36
DQ37

DM4

DQ38
DQ39

DQ44
DQ45

DQS5#

DQS5
DQ46

DQ47
DQ52

DQ53

CK1#

DM6

DQ54
DQ55

DQ60
DQ61

DQS7#

DQS7
DQ62

DQ63

SAO

VSS

VSS
VSS

VSS

VSS
VSS

CK0
VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

A11

BA1
S0#

VSS

VSS
VSS

VSS

VSS

VSS

VSS

VSS
CK1

VSS
VSS

VSS

VSS

VSS

VSS
SA1

NC

NC

2

+1.8V

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92

A7

94

A6

96
98

A4

100

A2

102

A0

104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

R104

V_DDR_MCH_REF

DDR_A_D7
DDR_A_D1

DDR_A_DM0
DDR_A_D5

DDR_A_D6
DDR_A_D12

DDR_A_D13
DDR_A_DM1
M_CLK_DDR0

M_CLK_DDR#0
DDR_A_D9

DDR_A_D15

DDR_A_D20
DDR_A_D16

DDR_A_DM2
DDR_A_D18

DDR_A_D29
DDR_A_D28

DDR_A_DQS#3
DDR_A_DQS3

DDR_A_D26
DDR_A_D31

DDR_CKE1_DIMMA

DDR_A_MA11
DDR_A_MA6
DDR_A_MA4

DDR_A_MA2
DDR_A_MA0

DDR_A_BS#1
DDR_A_RAS#
DDR_CS0_DIMMA#

M_ODT0
DDR_A_MA13

DDR_A_D36
DDR_A_D33

DDR_A_DM4
DDR_A_D37

DDR_A_D32
DDR_A_D40

DDR_A_D44
DDR_A_DQS#5

DDR_A_DQS5
DDR_A_D47

DDR_A_D46
DDR_A_D48

DDR_A_D49
M_CLK_DDR1

M_CLK_DDR#1
DDR_A_DM6
DDR_A_D50DDR_A_D51

DDR_A_D54
DDR_A_D60

DDR_A_D57
DDR_A_DQS#7

DDR_A_DQS7
DDR_A_D62

DDR_A_D63

12

12

R101

10K_0402_5%

10K_0402_5%

1

C17

V_DDR_MCH_REF

1

of

13 48, 01, 20

0.1U_0402_16V4Z

2.2U_0805_16V4Z
C11

1

1

2

2

M_CLK_DDR0
M_CLK_DDR#0

DDR_CKE1_DIMMA

DDR_A_BS#1
DDR_A_RAS#
DDR_CS0_DIMMA#

M_ODT0

M_CLK_DDR1
M_CLK_DDR#1

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3011

401395

 

05

A

5

DDR_B_DQS#[0..7]

DDR_B_D[0..63]

DDR_B_DM[0..7]
DDR_B_DQS[0..7]
DDR_B_MA[0..13]

D D

C C

B B

A A

Layout Note:
Place near JP26

+1.8V

2.2U_0805_16V4Z

2.2U_0805_16V4Z
C60

1

2

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS

+0.9VS

0.1U_0402_16V4Z

1

2

C61

DDR_B_MA1
DDR_B_MA3

DDR_B_BS#0
DDR_B_MA10

DDR_B_MA0
DDR_B_BS#1

DDR_B_RAS#
DDR_CS2_DIMMB#

DDR_B_CAS#
DDR_B_WE#

DDR_CS3_DIMMB# M_ODT2
M_ODT3

0.1U_0402_16V4Z

C58

1

2

0.1U_0402_16V4Z

1

2

C68

RP15

RP18

RP16

RP19

RP21

RP23

5

2.2U_0805_16V4Z
C97

1

2

0.1U_0402_16V4Z

1

2

C76

1 4
2 3

56_0404_4P2R_5%

1 4
2 3

56_0404_4P2R_5%

1 4
2 3

56_0404_4P2R_5%

1 4
2 3

56_0404_4P2R_5%

1 4
2 3

56_0404_4P2R_5%

2 3
1 4

56_0404_4P2R_5%

1

2

C83

2.2U_0805_16V4Z

+0.9VS

C94

1

2

0.1U_0402_16V4Z

1

2

C88

2.2U_0805_16V4Z
C84

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C96

RP10 56_0404_4P2R_5%

14
23

RP6 56_0404_4P2R_5%

14
23

RP13 56_0404_4P2R_5%

14
23

RP9 56_0404_4P2R_5%

14
23

RP12 56_0404_4P2R_5%

14
23

RP22 56_0404_4P2R_5%

14
23

RP7

14
23

56_0404_4P2R_5%

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C67

1

2

0.1U_0402_16V4Z

1

1

2

2

C63

C69

DDR_B_MA9
DDR_B_MA12

5/16

DDR_B_MA7
DDR_CKE3_DIMMB

DDR_B_MA5
DDR_B_MA8

5/16

DDR_B_MA6
DDR_B_MA11

DDR_B_MA4
DDR_B_MA2

DDR_B_MA13

DDR_B_BS#2
DDR_CKE2_DIMMB

0.1U_0402_16V4Z

C75

1

2

0.1U_0402_16V4Z

1

2

C74

0.1U_0402_16V4Z

C66

1

1

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C86

C80

Layout Note:
Place these resistor
closely JP26,all
trace length Max=1.5"

4

C82

1

+

2

220U_D2_4VM

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C90

C415

1

+

C106

2

220U_D2_4VM

1

2

C98

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

DDR_CKE2_DIMMB

DDR_B_BS#2

DDR_B_BS#0
DDR_B_WE#

DDR_B_CAS#

DDR_CS3_DIMMB#

M_ODT3

CLK_SMBDATA

CLK_SMBCLK

3

2

+1.8V

JP20

1

VREF

3

DDR_B_D0
DDR_B_D5

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D7
DDR_B_D3

DDR_B_D8
DDR_B_D9

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D11

DDR_B_D20
DDR_B_DQS#2

DDR_B_DQS2
DDR_B_D22

DDR_B_D23
DDR_B_D24

DDR_B_D25
DDR_B_DM3

DDR_B_D30
DDR_B_D31

DDR_CKE2_DIMMB

DDR_B_BS#2
DDR_B_MA12

DDR_B_MA9
DDR_B_MA8

DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

DDR_B_MA10
DDR_B_BS#0
DDR_B_WE#

DDR_B_CAS#
DDR_CS3_DIMMB#

M_ODT3
DDR_B_D37

DDR_B_D36
DDR_B_DQS#4

DDR_B_DQS4
DDR_B_D35

DDR_B_D34
DDR_B_D40

DDR_B_D41
DDR_B_DM5
DDR_B_D42

DDR_B_D47
DDR_B_D48

DDR_B_D53

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D51
DDR_B_D50

DDR_B_D60
DDR_B_D61

DDR_B_DM7
DDR_B_D58

DDR_B_D59
CLK_SMBDATA

CLK_SMBCLK

+3VS

1

C127

0.1U_0402_16V4Z

2005/06/01 2006/06/01

2

Compal Secret Data

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

P-TWO_A5692B-A0G16-P

SO-DIMM B

Deciphered Date

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS

CK0

CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

VDD

VDD

RAS#

VDD
ODT0

NC/A13

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

CK1

CK1#

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

SAO

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50

NC

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90

A11

92

A7

94

A6

96
98

A4

100

A2

102

A0

104
106

BA1

108
110

S0#

112
114
116
118
120

NC

122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

SA1

2

+1.8V

V_DDR_MCH_REF

DDR_B_D4
DDR_B_D1

DDR_B_DM0
DDR_B_D6

DDR_B_D2
DDR_B_D12

DDR_B_D13
DDR_B_DM1
M_CLK_DDR3

M_CLK_DDR#3
DDR_B_D14

DDR_B_D15

DDR_B_D16DDR_B_D21
DDR_B_D18

DDR_B_DM2
DDR_B_D17

DDR_B_D19
DDR_B_D26

DDR_B_D28
DDR_B_DQS#3

DDR_B_DQS3
DDR_B_D29

DDR_B_D27
DDR_CKE3_DIMMB

DDR_B_MA11
DDR_B_MA7
DDR_B_MA6

DDR_B_MA4
DDR_B_MA2
DDR_B_MA0

DDR_B_BS#1
DDR_B_RAS#
DDR_CS2_DIMMB#

M_ODT2
DDR_B_MA13

DDR_B_D33
DDR_B_D32

DDR_B_DM4
DDR_B_D38

DDR_B_D39
DDR_B_D44

DDR_B_D45
DDR_B_DQS#5

DDR_B_DQS5
DDR_B_D43

DDR_B_D46
DDR_B_D49

DDR_B_D52
M_CLK_DDR2

M_CLK_DDR#2
DDR_B_DM6
DDR_B_D54

DDR_B_D55
DDR_B_D56

DDR_B_D57
DDR_B_DQS#7

DDR_B_DQS7
DDR_B_D62

DDR_B_D63

1

V_DDR_MCH_REF

0.1U_0402_16V4Z

2.2U_0805_16V4Z

M_CLK_DDR3
M_CLK_DDR#3

DDR_CKE3_DIMMB

DDR_B_BS#1
DDR_B_RAS#
DDR_CS2_DIMMB#

M_ODT2

M_CLK_DDR2
M_CLK_DDR#2

R106

1 2

10K_0402_5%

12

10K_0402_5%

R103

Title

SCHEMATIC, M/B LA-3011

Size Document Number Rev

Date: Sheet

 

1

1

C18

C12

2

2

+3VS

Compal Electronics, Inc.

401395

05

1

A

of

14 48, 01, 20

5

+CK_VDD_MAIN1

1 2

+3VS

R235 0_0805_5%

1 2

+3VS

+3VS

CPU_BSEL0

CPU_BSEL1

FSC

CPU_BSEL2

R239

10K_0402_5%@

CLK_ENABLE#

R222

300_0402_5%

J10

NO SHORT PADS

R129 0_0805_5%

R127

1 2

0_0805_5%

R602

8.2K_0402_5%

FSA

1 2

R603

0_0402_5%

CLK_Ra

1 2

R593

0_0402_5%

CLK_Rb

R159

8.2K_0402_5%

1 2

R157

0_0402_5%

CLK_Rc

+3VS

12

12

12

@

D D

C C

B B

A A

+CK_VDD_MAIN2

+CK_VDD_DP

+VCCP

1 2

12

1 2

12

+VCCP

1 2

FSB

1 2

12

+VCCP

1 2

1 2

12

12

+3VS +3VS

1:CPU ITP *0:SRC 10

5

1

C193
10U_0805_10V4Z

2

1

C142
10U_0805_10V4Z

2

1

C165
10U_0805_10V4Z

2

R601

56_0402_5%

CLK_Rd

R599

1K_0402_5%

R598
1K_0402_5%@

R587
1K_0402_5%@

R588

1K_0402_5%

R586

0_0402_5%

CLK_Re

R149
1K_0402_5%@

R148

1K_0402_5%

R150

0_0402_5%

CLK_Rf

12

R238
10K_0402_5%@

PCI_ICH PCI_MINI

12

R208

10K_0402_5%

for Pin 6,5

1

C185

0.1U_0402_16V4Z

2

1

C147

0.1U_0402_16V4Z

2

5/20

1

C182

0.1U_0402_16V4Z

2

MCH_CLKSEL0

MCH_CLKSEL1

Reserve for ICS954305 & R need change to 475ohm

MCH_CLKSEL2

1:24M *0:test Mode

12

R193

12

R200

1

C535

0.1U_0402_16V4Z

2

1

C146

0.1U_0402_16V4Z

2

1

C536

0.1U_0402_16V4Z

2

14.31818MHZ_20P_6X1430004201

Reserve for ICS954305

*0:CLKREQ5# for Pin 29

CLK_MCH_DREFCLK#

ICH_SMBDATA

+3VS

ICH_SMBCLK

+3VS +3VS

12

10K_0402_5%@

10K_0402_5%

R217

12

R199

for Pin 43,44/47,48

1:27M/SRC0 *0:DOT 96M/LCD100

4

1

C166

0.1U_0402_16V4Z

2

R125

1 2

1_0805_1%

1 2

R124

2.2_0805_1%

1

C537

0.1U_0402_16V4Z

2

C15722P_0402_50V8J

1 2

Y1

1 2

C15822P_0402_50V8J

CLK_48M_ICH

CLK_48M_CB

CLK_14M_ICH

CLK_PCI_TCG
CLK_PCI_PCM

CLK_PCI_EC

CLK_PCI_USB20

CLK_PCI_SIO

CLK_14M_SIO

CLK_MCH_DREFCLK

CLK_PCI_ICH

CLK_EN#

CLK_SMBCLK

CLK_SMBDATA

+3VS

2.2K_0402_5%
Q37
2N7002_SOT23

D

S

1 3

G

2

2

G

1 3

D

S

2N7002_SOT23

Q38

10K_0402_5%@

PCI_PCM

10K_0402_5%

4

CK_VDD_REF

CK_VDD_48

0.1U_0402_16V4Z

12

CLK_XTAL_IN

CLK_XTAL_OUT

CLK_48M_ICH
CLK_48M_CB

CLK_14M_ICH

R166 33_0402_5%

R158 12_0402_5%

CLK_MCH_DREFCLK
CLK_MCH_DREFCLK#

CLK_PCI_ICH PCI_ ICH

CLK_ENABLE#

CLK_SMBCLK

CLK_SMBDATA

R580

R581

2.2K_0402_5%

CLK_SMBDATA

CLK_SMBCLK

1:48M *0:CLKREQ7#

for Pin 38for Pin 45

12

R216

10K_0402_5%@

PCI_EC

12

R206

10K_0402_5%

+CK_VDD_DP

+CK_VDD_MAIN1

C168

1 2
1 2

C194 0.1U_0402_16V4Z

R209 12_0402_5%

R223 12_0402_5%

R142 33_0402_5%

1 2

R218 33_0402_5%GM@

1 2

R219 33_0402_5%GM@

33_0402_5%

12

R207

0_0402_5%

CK_VDD_REF
CK_VDD_48

12
12

R19233_0402_5% @

12

R19433_0402_5%

12

R18833_0402_5%

12

R18733_0402_5%

12
12

R16510K_0402_5%@

12
12

MCH_DREFCLK

MCH_DREFCLK#

12

R119

12

Security Classification

Issued Date

THIS SHEET OF E NGI NEER ING DR AWI NG I S T HE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONIC S, INC. AND C ONTAINS CONFID ENTIAL
AND TRADE S ECR ET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

FSA
FSB
FSC

PCI_PCM
PCI_EC
PCI_MINI

REF1CLK_14M_SIO

+3VS

3

U9

1

VDDSRC

49

VDDSRC

54

VDDSRC

65

VDDSRC

30

VDDPCI

36

VDDPCI

12

VDDCPU

18

VDDREF

40

VDD48

20

X1

19

X2

41

USB_48MHz/FSLA

45

FSLB/TEST_MODE/24Mhz

23

REF0/FSLC/TEST_SEL

34

PCICLK4/FCTSEL1

33

SEL_48M/PCICLK3

32

SEL_24M/PCICLK2

27

SEL_PCI6/PCICLK1

22

SEL_PCI5/REF1

43

DOTT_96MHz/27MHz_Nonspread

44

DOTC_96MHz/27MHz_spread

37

ITP_EN/PCICLK_F0

39

VTT_PWRGD#/PD

9

GND

16

SMBCLK

17

SMBDAT

4

GNDSRC

15

GNDCPU

21

GNDREF

31

GNDPCI

35

GNDPCI

42

GND48

68

GNDSRC

ICS9LPR325AKLFT_MLF72

R14110K_0402_5%

12

R58910K_0402_5%

1 2

R18110K_0402_5%

1 2

R19010K_0402_5%

1 2

2005/06/01 2006/06/01

3

VDDA
GNDA

PCI_SRC_STOP#

CPU_STOP#

CPUCLKT1LP

CPUCLKC1LP

CPUCLKT0LP

CPUCLKC0LP

CPUCLKT2_ITP/SRCCLKT10LP

CPUCLKC2_ITP/SRCCLKC10LP

SRCCLKT9LP

SRCCLKC9LP

CLKREQ9#

SRCCLKT8LP

SRCCLKC8LP

CLKREQ8#

SRCCLKT7LP

SRCCLKC7LP

CLKREQ7#/48Mhz_1

SRCCLKT6LP

SRCCLKC6LP

CLKREQ6#

SRCCLKT5LP

SRCCLKC5LP

CLKREQ5#/PCICLK6

SRCCLKT4LP

SRCCLKC4LP

CLKREQ4#

SRCCLKT3LP

SRCCLKC3LP

CLKREQ3#/PCICLK5

SRCCLKT2LP

SRCCLKC2LP

CLKREQ2#

SRCCLKT1LP

SRCCLKC1LP

CLKREQ1#
LCD100/96/SRC0_TLP
LCD100/96/SRC0_CLP

*1:PCICLK3 for Pin28

REF1
SATA_CLKREQA#
CLKREQC#
CLKREQD#

Compal Secret Data

Deciphered Date

2

+VDDAD

7
8

25
24

MCH_BCLK

11

MCH_BCLK#

10

CPU_BCLK

14

CPU_BCLK#

13

6
5

3
2
72
70
69
71

PCIE_SATA

66

PCIE_SATA# CLK_PCIE_SATA#

67

CLKREQ7#

38
63
64
62

MCH_3GPLL

60

MCH_3GPLL#

61
29
58
59
57
55

PCIE_ICH#

56

PCI_CLK5

28
52
53

CLKREQ2#

26
50
51

CLKREQ1#

46
47
48

R126

12

0_0805_5%

H_STP_PCI#

H_STP_CPU#

1 2

R132 0_0402_5%

1 2

R133 0_0402_5%

1 2

R130 0_0402_5%

1 2

R131 0_0402_5%

1 2

R151 0_0402_5%

1 2

R143 0_0402_5%
R594 0_0402_5%

1 2

R167 0_0402_5%

1 2

R160 0_0402_5%
R172 0_0402_5%

1 2

R182 0_0402_5%

1 2

R178 0_0402_5%
R189 0_0402_5%

1 2

R201 0_0402_5%

1 2

R196 0_0402_5%

1 2

R186

1 2

R214 0_0402_5%

1 2

R215 0_0402_5%
R171 0_0402_5%

1 2

R212 0_0402_5%

1 2

R213 0_0402_5%

1 2

R210 0_0402_5%

1 2

R211 0_0402_5%

12

12

12

0_0402_5%

12

CLKREQ7#
CLKREQ1#
CLKREQ2#
CLKREQ5#

PCI_CLK5

2

+3VS

CLK_MCH_BCLK
CLK_MCH_BCLK#

CLK_CPU_BCLK
CLK_CPU_BCLK#

CLK_PCIE_SATA

CLK_MCH_3GPLL
CLK_MCH_3GPLL#
MCH_CLKREQ#CLKREQ5#

MINI_CLKREQ#
CLK_PCIE_ICHPCIE_ICH
CLK_PCIE_ICH#

CLK_PCIE_LAN
CLK_PCIE_LAN#
LAN_CLKREQ#
CLK_PCIE_VGA
CLK_PCIE_VGA#

CLK_PCIE_GMCH
CLK_PCIE_GMCH#

CLKSEL1

FSLA

CLKSEL0

FSLC1FSLB

CLKSEL2

0

0

1

H_STP_PCI#
H_STP_CPU#

CLK_MCH_BCLK
CLK_MCH_BCLK#

CLK_CPU_BCLK
CLK_CPU_BCLK#

Place these components
near each pin within 40
mils.

CLK_CPU_BCLK
CLK_CPU_BCLK#

CLK_MCH_BCLK
CLK_MCH_BCLK#

CLK_PCIE_SATA

SATA_CLKREQ#

R595 10K_0402_5%@
R592 10K_0402_5%@
R164 10K_0402_5%@
R173 10K_0402_5%@
R180 10K_0402_5%@

CLK_PCIE_SATA#

SATA_CLKREQ#

CLK_MCH_3GPLL
CLK_MCH_3GPLL#
MCH_CLKREQ#
CLK_PCIE_MCARD
CLK_PCIE_MCARD#
MINI_CLKREQ#
CLK_PCIE_ICH
CLK_PCIE_ICH#

CLK_PCI_TCG

CLK_PCIE_LAN
CLK_PCIE_LAN#

LAN_CLKREQ#
CLK_PCIE_VGA
CLK_PCIE_VGA#

MCH_SSCDREFCLK
MCH_SSCDREFCLK#

12
12
12
12
12

Title

Size Document Number Re v

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3011

401395

 

?01, 2005

CLK_PCIE_GMCH
CLK_PCIE_GMCH#

CLK_PCIE_VGA
CLK_PCIE_VGA#

CLK_PCIE_SATA
CLK_PCIE_SATA#

CLK_MCH_3GPLL
CLK_MCH_3GPLL#

CLK_PCIE_MCARD
CLK_PCIE_MCARD#

CLK_PCIE_ICH
CLK_PCIE_ICH#

CLK_MCH_DREFCLK
CLK_MCH_DREFCLK#

CLK_PCIE_LAN
CLK_PCIE_LAN#

1

PCI

SRC

CPU
MHz

133

166

+VDDAD

MHz

MHz

33.31

1000

100

33.3

1

C167

0.1U_0402_16V4Z

2

12

R120 49.9_0402_1%

12

@

R121 49.9_0402_1%

@

12

R122 49.9_0402_1%

12

@

R123 49.9_0402_1%

@

1 2

R226 49.9_0402_1%

1 2

@

R227 49.9_0402_1%

@

1 2

R228 49.9_0402_1%

1 2

@

R229 49.9_0402_1%

@

1 2

R152 49.9_0402_1%

1 2

@

R144 49.9_0402_1%

@

1 2

R168 49.9_0402_1%

1 2

@

R161 49.9_0402_1%

@

1 2

R183 49.9_0402_1%

1 2

@

R179 49.9_0402_1%

@

1 2

R202 49.9_0402_1%

1 2

@

R197 49.9_0402_1%

@

1 2

R224 49.9_0402_1%

1 2

@

R225 49.9_0402_1%

1 2

@

R230 49.9_0402_1%

1 2

@

R231 49.9_0402_1%

@

Reserve for ICS954305

A

of

15 48, 

1

A

CRT Connector

U3

DOCKIN#

1 1

VGA_CRT_R
GMCH_CRT_R

VGA_CRT_G
GMCH_CRT_G

VGA_CRT_B
GMCH_CRT_B

1 2

R28 0_0402_5%GM@

1 2

R29 0_0402_5%GM@

1 2

R30 0_0402_5%GM@

DOCKIN#

Close to VGA conn.

VGA_CRT_R

R16 0_0402_5%WOD@

VGA_CRT_G

R22 0_0402_5%WOD@
R448 0_0402_5%WOD@

Pop with No-Docking

2 2

1 2
1 2
1 2

CRT_R
CRT_G
CRT_BVGA_CRT_B

VGA_CRT_HSYNC
GMCH_CRT_HSYNC

VGA_CRT_VSYNC
GMCH_CRT_VSYNC

1 2

R38 39_0402_5%GM@

1 2

R39 39_0402_5%GM@

Close to VGA conn.

+3VS

R270_0402_5%GM@

GMCH_CRT_DATA

VGA_DDC_DATA

VGA_DDC_CLK

3 3

GMCH_CRT_CLK

1 2

VGA_DDC_DATA

1 2

0_0402_5% GM@

R26

Close to VGA conn.

VGA_TV_LUMA
GMCH_TV_LUMA

VGA_TV_CRMA
GMCH_TV_CRMA

1 2

R34 0_0402_5%GM@

1 2

R35 0_0402_5%GM@

Close to VGA conn.

12

R107

150_0402_1%

12

R113

150_0402_1%

1

SEL

15

OE#

4

1A

7

2A

9

3A

12

4A

8

GND

WD@

FSAV330MTC_TSSOP16

12

G

2

S

BSS138_SOT23

C128
100P_0402_25V8K

VCC

R4310_0402_5%

S

BSS138_SOT23

13

D

Q31

B

+5VS

1 2

C376

WD@

16

D_CRT_R

2

1B1

D_CRT_G

5

2B1

D_CRT_B

11

3B1

14

4B1

3

1B2

6

2B2

10

3B2

13

4B2

12

R9

150_0402_1%

1 2

C375 0.1U_0402_16V4Z

+5VS

12

R427

G

2

4.7K_0402_5%

13

D

Q32

L2

FBM-11-160808-121T_0603

L1

FBM-11-160808-121T_0603

C140
100P_0402_25V8K

0.1U_0402_16V4Z

D_CRT_R
D_CRT_G
D_CRT_B

12

12

R21

R441

150_0402_1%

150_0402_1%

+5VS

5

1

P

4

OE#

A2Y

G

U37

SN74AHCT1G125GW_SOT353-5

3

1 2

C370 0.1U_0402_16V4Z

12

R430

4.7K_0402_5%

DSUB_12_DATA

DSUB_15_CLKVGA_DDC_CLK

C133

1 2

22P_0402_50V8J

@

1 2

1 2

C130

1 2

22P_0402_50V8J

@

100P_0402_25V8K

Match with Docking resistor to 150ohm

D_CRT_R

R6 470_0402_1%

1 2

R18 470_0402_1%

1 2

R434 470_0402_1%

1 2

12

R433 10K_0402_5%

D_CRT_HSYNC

D_CRT_VSYNC

4

OE#

U36
SN74AHCT1G125GW_SOT353-5

CRMA_1
LUMA_1

C132

CRT_R
CRT_G
CRT_B

C131

D_CRT_G
D_CRT_B

+5VS

5

1

P

A2Y

G

3

100P_0402_25V8K

C

TV-OUT Conn.

JP23

4

4

3

6

3

6

2

5

2

5

1

1

ALLTO_C10877-104A1-L_4P

D

Near to JP45

CRT CONNECTOR

CRT_R DVI_G

CRT_G

CRT_B

1

1

C364

2

6P_0402_50V8K

C365

2

6P_0402_50V8K

D_CRT_HSYNC

D_CRT_VSYNC

1. Y ground

2. C ground

3. Y (luminance+sync)

4. C (crominance)

L13

1 2

FCM2012C-800_0805

L10

1 2

FCM2012C-800_0805

L11

1 2

FCM2012C-800_0805

1

C369
6P_0402_50V8K

2

D_CRT_HSYNC

D_CRT_VSYNC VSYNC

1 2

L12 FCM1608C-121T_0603

1 2

L9 FCM1608C-121T_0603

VGA_DDC_DATA

VGA_DDC_CLK

D29

DAN217_SC59

@

1

C368

2

6P_0402_50V8K@

1

2

3

C363

10P_0402_50V8J

BSS138_SOT23 GM@

BSS138_SOT23 GM@

D27

DAN217_SC59

@

1

C366
6P_0402_50V8K@

2

+3VS

G

S

+3VS

G

S

2

1

2

2

2

1

3

HSYNC

13

D

Q33

13

D

Q30

1

2

1

C358
10P_0402_50V8J

2

D_DDC_DATA

12

R4320_0402_5% PM@

D_DDC_CLK

12

R4280_0402_5% PM@

1

D28

DAN217_SC59

2

@

C361

6P_0402_50V8K@

+3VS

3

+5VS +R_CRT_VCC

D25

2 1

POLYSWITCH_1A

CH491D_SC59

0.1U_0402_16V4Z

DVI_R

DVI_B

1

C357

2

220P_0402_50V7K

C367

68P_0402_50V8K

D_DDC_DATA

D_DDC_CLK

E

F1

1

2

+CRT_VCC

1

C360

2

1

C356

2

68P_0402_50V8K

CRT Conn.

JP15

6

11

1
7

12

2
8

13

3
9

14

4
10
15

5

TYCO_1470801-1

DSUB_12_DATA
DSUB_15_CLK

4 4

Security Classification

Issued Date

THIS SHEET OF E NGIN EERIN G DRA WING I S THE P ROPRI ETAR Y PROP ERTY OF CO MPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE S ECR ET I NFO RMA TION . T HIS SHE ET MAY NOT BE TRANSFERED FROM T HE CUSTODY OF THE COMPET ENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUT HORIZ ED B Y COM PAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL EL ECTRONICS, INC.

C

2005/06/01 2006/06/01

Compal Secret Data

Deciphered Date

D

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3011



 

401395

, 01, 2005

E

16 48

of

A

5

LCD POWER CIRCUIT

VGA_ENVDD

GMCH_ENVDD

D D

GMCH_ENVDD

+LCDVDD

12

R25

300_0402_5%

13

D

Q4

2N7002_SOT23

G

S

2

R3 0_0402_5%PM@

1 2

R15 0_0402_5%GM@

1 2

+3VALW

C7

0.01U_0402_16V7K

R14
100K_0402_5%

1 2

1

2

1

2

U4

1

5

P

OE#

A2Y

G

3

C386

0.047U_0402_16V7K

LCD/PANEL BD. Conn.

C C

+LCDVDD

C45

4.7U_0805_10V4Z

0_0402_5% PM@

LCD_CLK

LCD_DATA

TXOUT0­TXOUT0+

TXOUT1­TXOUT1+

TXOUT2­TXOUT2+

TXCLK­TXCLK+

LCD_CLK

LCD_DATA

TXOUT0­TXOUT0+

TXOUT1­TXOUT1+

TXOUT2­TXOUT2+

TXCLK­TXCLK+

0_0402_5% PM@

R461 0_0402_5%PM@
R460 0_0402_5%PM@

R463 0_0402_5%PM@
R462 0_0402_5%PM@

R464 0_0402_5%PM@
R468 0_0402_5%PM@

R469 0_0402_5%PM@
R471 0_0402_5%PM@

0_0402_5% GM@

0_0402_5% GM@

R45 0_0402_5%GM@
R44 0_0402_5%GM@

R47 0_0402_5%GM@
R46 0_0402_5%GM@

R48 0_0402_5%GM@
R49 0_0402_5%GM@

R50 0_0402_5%GM@
R51 0_0402_5%GM@

B B

A A

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

12
12

12
12

B+ B+

DISPOFF#

LCD_DATA
TXCLK+

TXCLK-

2

TXOUT2+
TXOUT2­TXOUT1-

1

TXOUT1+
TXOUT0­TXOUT0+

VGA_LCD_CLK

R449

VGA_LCD_DATA

R450

GMCH_LCD_CLK

R457

GMCH_LCD_DATA

R458

JP3

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29

ACES_88242-3000

VGA_TXOUT0-

VGA_TXOUT0+

VGA_TXOUT1-

VGA_TXOUT1+

VGA_TXOUT2-

VGA_TXOUT2+

VGA_TXCLK-

VGA_TXCLK+

GMCH_LCD_CLK

GMCH_LCD_DATA

GMCH_TXOUT0­GMCH_TXOUT0+

GMCH_TXOUT1­GMCH_TXOUT1+

GMCH_TXOUT2­GMCH_TXOUT2+

GMCH_TXCLK­GMCH_TXCLK+

2

DAC_BRIG

4

INVT_PWM

6
8

LCD_CLK

10
12

TZCLK-

14

TZCLK+

16
18

TZOUT1-

20

TZOUT1+

22

TZOUT2+

24

TZOUT2-

26

TZOUT0+

28

TZOUT0-

30

4

SN74AHCT1G125GW_SOT353-5

4

R7

1 2

100_0402_5%

G

2

DAC_BRIG
INVT_PWM

0.1U_0402_16V4Z

R440 0_0402_5%PM@

TZOUT0+
TZOUT1-

TZOUT1+
TZOUT2-

TZOUT2+
TZCLK-

TZCLK+

TZOUT0­TZOUT0+

TZOUT1­TZOUT1+

TZOUT2­TZOUT2+

TZCLK­TZCLK+

1 2

R439 0_0402_5%PM@

1 2

R435 0_0402_5%PM@

1 2

R436 0_0402_5%PM@

1 2

R438 0_0402_5%PM@

1 2

R437 0_0402_5%PM@

1 2

R451 0_0402_5%PM@

1 2

R452 0_0402_5%PM@

1 2

R447 0_0402_5%GM@

1 2

R446 0_0402_5%GM@

1 2

R442 0_0402_5%GM@

1 2

R443 0_0402_5%GM@

1 2

R445 0_0402_5%GM@

1 2

R444 0_0402_5%GM@

1 2

R454 0_0402_5%GM@

1 2

R455 0_0402_5%GM@

1 2

+3VS

BKOFF#

S

D

1 3

1

C404

2

C378

Q35
AO3413_SOT23

4.7U_0805_10V4Z

+3VS

1

2

3

+3VS

12

R33

4.7K_0402_5%

21

PCIE_MTX_C_GRX_N[0..15]

PCIE_MTX_C_GRX_P[0..15]
PCEI_GTX_C_MRX_N[0..15]
PCEI_GTX_C_MRX_P[0..15]

RB751V_SOD323

1

C389

0.1U_0402_16V4Z

2

VGA_TZOUT0-TZOUT0-

VGA_TZOUT0+

VGA_TZOUT1-

VGA_TZOUT1+

VGA_TZOUT2-

VGA_TZOUT2+

VGA_TZCLK­VGA_TZCLK+

GMCH_TZOUT0­GMCH_TZOUT0+

GMCH_TZOUT1­GMCH_TZOUT1+

GMCH_TZOUT2­GMCH_TZOUT2+

GMCH_TZCLK­GMCH_TZCLK+

D2

BKOFF# DISPOFF#

PCIE_MTX_C_GRX_N[0..15]
PCIE_MTX_C_GRX_P[0..15]
PCIE_GTX_C_MRX_N[0..15]
PCIE_GTX_C_MRX_P[0..15]

+LCDVDD

CLK_PCIE_VGA

CLK_PCIE_VGA#
VGA_CRT_R
VGA_CRT_G
VGA_CRT_B
PLT_RST#

SUSP#
VGA_ENBKL
DVI_TXC+

DVI_TXC­DVI_TXD0+

DVI_TXD0-

2

VGA BOARD Conn.

B+

+1.5VS

+2.5VS

VGA_LCD_CLK

VGA_LCD_DATA

VGA_TZCLK­VGA_TZCLK+ VGA_TXCLK+

VGA_TZOUT0­VGA_TZOUT0+

VGA_TZOUT1­VGA_TZOUT1+

VGA_TZOUT2­VGA_TZOUT2+

PCEI_GTX_C_MRX_P0
PCEI_GTX_C_MRX_N0

PCEI_GTX_C_MRX_P1
PCEI_GTX_C_MRX_N1

PCEI_GTX_C_MRX_P2
PCEI_GTX_C_MRX_N2

PCEI_GTX_C_MRX_P3
PCEI_GTX_C_MRX_N3

PCEI_GTX_C_MRX_P4
PCEI_GTX_C_MRX_N4

PCEI_GTX_C_MRX_P5
PCEI_GTX_C_MRX_N5

PCEI_GTX_C_MRX_P6
PCEI_GTX_C_MRX_N6

PCEI_GTX_C_MRX_P7
PCEI_GTX_C_MRX_N7

PCEI_GTX_C_MRX_P8
PCEI_GTX_C_MRX_N8

PCEI_GTX_C_MRX_P9
PCEI_GTX_C_MRX_N9

PCEI_GTX_C_MRX_P10
PCEI_GTX_C_MRX_N10

PCEI_GTX_C_MRX_P11
PCEI_GTX_C_MRX_N11

PCEI_GTX_C_MRX_P12
PCEI_GTX_C_MRX_N12

PCEI_GTX_C_MRX_P13
PCEI_GTX_C_MRX_N13

PCEI_GTX_C_MRX_P14
PCEI_GTX_C_MRX_N14

PCEI_GTX_C_MRX_P15
PCEI_GTX_C_MRX_N15

CLK_PCIE_VGA

CLK_PCIE_VGA#
VGA_CRT_R
VGA_CRT_G
VGA_CRT_B

SUSP#
VGA_ENVDD
VGA_ENBKL

JP18

1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
45 46
47 48
49 50
51 52
53 54
55 56
57 58
59 60
61 62
63 64
65 66
67 68
69 70
71 72
73 74
75 76
77 78
79 80
81 82
83 84
85 86
87 88
89 90
91 92
93 94
95 96
97 98
99 100
101 102
103 104
105 106
107 108
109 110
111 112
113 114
115 116
117 118
119 120
121 122
123 124
125 126
127 128
129 130
131 132
133 134
135 136
137 138
139 140
141 142
143 144
145 146
147 148
149 150
151 152
153 154
155 156
157 158
159 160
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

ACES_88386-1K71

162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

+1.8VS

VGA_TXCLK-

VGA_TXOUT0­VGA_TXOUT0+

VGA_TXOUT1­VGA_TXOUT1+

VGA_TXOUT2­VGA_TXOUT2+

PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_N0

PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_N1

PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_N2

PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_N3

PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_N4

PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_N5

PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_N6

PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_N7

PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_N8

PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_N9

PCIE_MTX_C_GRX_P10

PCIE_MTX_C_GRX_N10

PCIE_MTX_C_GRX_P11

PCIE_MTX_C_GRX_N11

PCIE_MTX_C_GRX_P12

PCIE_MTX_C_GRX_N12

PCIE_MTX_C_GRX_P13

PCIE_MTX_C_GRX_N13

PCIE_MTX_C_GRX_P14

PCIE_MTX_C_GRX_N14

PCIE_MTX_C_GRX_P15

PCIE_MTX_C_GRX_N15

VGA_DDC_CLK
VGA_DDC_DATA

VGA_TV_LUMA
VGA_TV_CRMA
VGA_CRT_VSYNC

VGA_CRT_HSYNC

+3VS

+5VS

1

VGA_DDC_CLK
VGA_DDC_DATA

VGA_TV_LUMA
VGA_TV_CRMA

VGA_CRT_VSYNC
VGA_CRT_HSYNC

DVI_DET#

DVI_SCLK
DVI_SDATA

DVI_TXD1+
DVI_TXD1-

DVI_TXD2+
DVI_TXD2-

Security Classification

Issued Date

THIS SHEET OF E NGI NEER ING DR AWI NG I S T HE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONIC S, INC. AND C ONTAINS CONFID ENTIAL
AND TRADE S ECR ET INFORMATION. TH IS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/06/01 2006/06/01

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Re v

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3011

 

01, 2005



401395

17 48,

1

A

of

5

4

3

2

1

D D

C C

B B

+3VS

R328 8.2K_0402_5%

1 2

R616 8.2K_0402_5%

1 2

R617 8.2K_0402_5%

1 2

R615 8.2K_0402_5%

1 2

R619 8.2K_0402_5%

1 2

R343 8.2K_0402_5%

1 2

R334 8.2K_0402_5%

1 2

R622 8.2K_0402_5%

1 2

R325 8.2K_0402_5%

1 2

R618 8.2K_0402_5%

1 2

+3VS

R355 8.2K_0402_5%

1 2

R352 8.2K_0402_5%

1 2

R348 8.2K_0402_5%

1 2

R346 8.2K_0402_5%

1 2

R630 8.2K_0402_5%

1 2

R646 8.2K_0402_5%

1 2

R634 8.2K_0402_5%

1 2

R650 8.2K_0402_5%

1 2

R643 8.2K_0402_5%

1 2

R306 8.2K_0402_5%

1 2

R303 8.2K_0402_5%

1 2

R624 8.2K_0402_5%

1 2

R318 8.2K_0402_5%

1 2

PCI_DEVSEL#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#
PCI_PLOCK#
PCI_IRDY#
PCI_SERR#
PCI_PERR#
PCI_REQ4#
PCI_REQ3#

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#
PCI_REQ0#
PCI_REQ1#
PCI_REQ2#
PCI_REQ5#
ICH_GPIO48

PCI_AD[0..31]

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

U21B

E18

AD0

C18

AD1

A16

AD2

F18

AD3

E16

AD4

A18

AD5

E17

AD6

A17

AD7

A15

AD8

C14

AD9

E14

AD10

D14

AD11

B12

AD12

C13

AD13

G15

AD14

G13

AD15

E12

AD16

C11

AD17

D11

AD18

A11

AD19

A10

AD20

F11

AD21

F10

AD22

E9

AD23

D9

AD24

B9

AD25

A8

AD26

A6

AD27

C7

AD28

B6

AD29

E6

AD30

D6

AD31

Interrupt I/F

A3

PIRQA#

B4

PIRQB#

C5

PIRQC#

B5

PIRQD#

AE5

RSVD[1]

AD5

RSVD[2]

AG4

RSVD[3]

AH4

RSVD[4]

AD9

RSVD[5]

ICH7_BGA652~D

PCI

REQ4# / GPIO22
GNT4# / GPIO48

GPIO1 / REQ5#

GPIO17 / GNT5#

GPIO2 / PIRQE#
GPIO3 / PIRQF#
GPIO4 / PIRQG#
GPIO5 / PIRQH#

MISC

MCH_SYNC#

REQ0#
GNT0#
REQ1#
GNT1#
REQ2#
GNT2#
REQ3#
GNT3#

C/BE0#
C/BE1#
C/BE2#
C/BE3#

IRDY#

PAR

PCIRST#

DEVSEL#

PERR#

PLOCK#

SERR#

STOP#
TRDY#

FRAME#

PLTRST#

PCICLK

PME#

RSVD[6]
RSVD[7]
RSVD[8]
RSVD[9]

D7
E7
C16
D16
C17
D17
E13
F13
A13
A14
C8
D8

B15
C12
D12
C15

A7
E10
B18
A12
C9
E11
B10
F15
F14
F16

C26
A9
B19

G8
F7
F8
G7

AE9
AG8
AH8
F21
AH20

PCI_REQ0#
PCI_REQ1#
PCI_REQ2#

PCI_GNT2#
PCI_REQ3#

PCI_REQ4#
ICH_GPIO48
PCI_REQ5#

PCI_CBE#0
PCI_CBE#1
PCI_CBE#2
PCI_CBE#3

PCI_IRDY#
PCI_PAR
PCI_PCIRST#
PCI_DEVSEL#
PCI_PERR#
PCI_PLOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#

PCI_PLTRST#
CLK_PCI_ICH

PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#

PCI_REQ2#
PCI_GNT2#

PCI_CBE#0
PCI_CBE#1
PCI_CBE#2
PCI_CBE#3

PCI_IRDY#
PCI_PAR

PCI_DEVSEL#
PCI_PERR#

PCI_SERR#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#

CLK_PCI_ICH

MCH_ICH_SYNC#

PCI_PCIRST#

PCI_PLTRST#

+3VS

5

U18

1

P

B

Y

2

A

G

TC7SH08FU_SSOP5@

12

+3VS

1

B

2

A

12

3

5

U17

P

Y

G

TC7SH08FU_SSOP5

3

R299
0_0402_5%

R296
0_0402_5%@

Place closely pin A9

CLK_PCI_ICH

R336

10_0402_5% @

1 2
1

C254

8.2P_0402_50V@

2

PCI_RST#

4

PLT_RST#

4

PCI_RST#

PLT_RST#

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/06/01 2006/06/01

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3011

 

401395

05

18 48, 01, 20

1

A

of

5

4

3

2

1

+5V_IDE+5V_SATA

J5

2

112

JUMP_43X118

@

2

J6

112

JUMP_43X118

12

R345

13

+5VS

1

C270

2

10U_0805_10V4Z

2

DTC124EK_SC59

2

1 3

Q23

Reserve for test

1

C281

0.1U_0402_16V4Z

2

ODD CONN

INT_CD_R
PD_D8

PD_D9
PD_D10
PD_D11
PD_D12
PD_D13
PD_D14
PD_D15
PD_DREQ
PD_IOR#

PD_DACK#
PDIAG#

PD_A2

1

C521

0.1U_0402_16V4Z

2

ODD_RST#

W=80mils

C524 0.1U_0402_16V4Z

INT_CD_R

R109 100K_0402_5%

1 2

+5VS
+5VS
+5VS

12

Compal Electronics, Inc.

401395

01, 2005

1

+5VS

AOS 3401_SOT23

Q24

+5V_IDE

C274

0.1U_0402_16V4Z

IDE_RESET#

of

19 48,

+5VS

A

EEP_CS
EEP_SK
EEP_DOUT
EEP_DIN

R37133_0402_5%

12

R37033_0402_5%

12

1 2

24.9_0402_1%

R3154.7K_0402_5%

12

R3048.2K_0402_5%

12

ICH_RTCX1

12

R386
10M_0402_5%

ICH_RTCX2

ICH_RTCRST#

ICH_INTVRMEN
SM_INTRUDER#

ACZ_SDIN0
ACZ_SDIN1

ACZ_SDOUT

SATA_RXN0_C
SATA_RXP0_C
SATA_TXN0_C
SATA_TXP0_C

CLK_PCIE_SATA#
CLK_PCIE_SATA

R333

PD_IORDY
PD_IRQ
PD_DACK#
PD_IOW#
PD_IOR#

JP26

1

GND

RESERVED

+3VS

R108

1 2

A+

A-

GND

B-

B+

GND

VCC3.3
VCC3.3
VCC3.3

GND
GND

GND
VCC5
VCC5
VCC5

GND

GND

VCC12
VCC12
VCC12

C179

12

12

AF18

AH10

AG10

AG16

AH16
AF16
AH15
AF15

AB1
AB2

AA3

W4

Y5

W1

Y1
Y2

W3

V3
U3
U5

V4
T5

U7
V6
V7

U1
R6

R5
T2

T3
T1

T4

AF3
AE3
AG2
AH2

AF7
AE7
AG6
AH6

AF1
AE1

U21A

RTXC1
RTCX2

RTCRST#
INTVRMEN

INTRUDER#

EE_CS
EE_SHCLK
EE_DOUT
EE_DIN

LAN_CLK
LAN_RSTSYNC
LAN_RXD0

LAN_RXD1
LAN_RXD2

LAN_TXD0
LAN_TXD1
LAN_TXD2

ACZ_BCLK
ACZ_SYNC

ACZ_RST#
ACZ_SDIN0

ACZ_SDIN1
ACZ_SDIN2

ACZ_SDOUT

SATALED#

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

SATA_CLKN
SATA_CLKP

SATARBIASN
SATARBIASP

IORDY
IDEIRQ
DDACK#
DIOW#
DIOR#

ICH7_BGA652~D

RTC

LAD0
LAD1
LAD2
LAD3

LDRQ0#

LPCCPU

LDRQ1# / GPIO23

LFRAME#

LAN

A20GATE

A20M#

CPUSLP#

TP1 / DPRSTP#

TP2 / DPSLP#

FERR#

GPIO49 / CPUPWRGD

IGNNE#

INIT3_3V#

INIT#
INTR

AC-97/AZALIA

RCIN#

SMI#

STPCLK#

THERMTRIP#

DCS1#
DCS3#

SATA

DD10
DD11
DD12
DD13

IDE

DD14
DD15

DDREQ

LPC_AD0

AA6

LPC_AD1

AB5

LPC_AD2

AC4

LPC_AD3

Y6

LPC_DRQ#0

AC3

LPC_DRQ#1

AA5

LPC_FRAME#

AB3

EC_GA20

AE22

H_A20M#

AH28

H_CPUSLP_R#

AG27

DPRSLP#

AF24

H_DPSLP#

AH25

H_FERR#

AG26

H_PWRGOOD

AG24

H_IGNNE#

AG22
AG21

H_INIT#

AF22

H_INTR

AF25

EC_KBRST#

AG23

H_SMI#

AF23

H_NMI

AH24

NMI

DA0
DA1
DA2

DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9

AH22
AF26

AH17
AE17
AF17

AE16
AD16

AB15
AE14
AG13
AF13
AD14
AC13
AD12
AC12
AE12
AF12
AB13
AC14
AF14
AH13
AH14
AC15

AE15

H_STPCLK#
THRMTRIP_ICH#

PD_A0
PD_A1
PD_A2

PD_CS#1
PD_CS#3

PD_D0
PD_D1
PD_D2
PD_D3
PD_D4
PD_D5
PD_D6
PD_D7
PD_D8
PD_D9
PD_D10
PD_D11
PD_D12
PD_D13
PD_D14
PD_D15

PD_DREQ

LPC_AD[0..3]

LPC_DRQ#0
LPC_DRQ#1

LPC_FRAME#

R279 10K_0402_5%

12

EC_GA20

H_A20M#

T29

PAD

R271 0_0402_5%
R251 56_0402_5%

R274 10K_0402_5%

12
12

H_FERR#
H_PWRGOOD
H_IGNNE#
H_INIT#

H_INTR

12

EC_KBRST#

H_SMI#
H_NMI

H_STPCLK#

R266

1 2

24.9_0402_1%

+3VS

H_DPRSTP#
H_DPSLP#

+VCCP

+VCCP

12

***Must be placed close to AF26 pin within 2"

+3VS

SUYIN_127043FB022G208ZR_22P_RV

R267
56_0402_5%

H_THERMTRIP#

INT_CD_L

10K_0402_5%

SHDD_LED#

+5VS

R95 4 .7K_0402_5%@
R93 470_0402_5%

RTC Battery

BATT1

-+

45@

RTCBATT

+RTCVCC

4

+RTCBATT

12

1

C310

0.1U_0402_16V4Z

2

+RTCBATT

1

D17
BAS40-04_SOT23

2

3

+CHGRTC

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOU T PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2005/06/01 2006/06/01

Compal Secret Data

Deciphered Date

SATA_TXP0

2

SATA_TXN0

3
4

SATA_RXN0

5

SATA_RXP0

6
7

J4

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

+5VS

1

C293
10U_0805_10V4Z

2

12

10U_0805_10V4Z

ODD_RST#
PD_D7
PD_D6
PD_D5
PD_D4
PD_D3
PD_D2
PD_D1
PD_D0

PD_IOW#
PD_IORDY
PD_IRQ
PD_A1
PD_A0
PD_CS#1 PD_CS#3
SHDD_LED#

+5VS
+5VS

SEC_CSEL

+5VS

1

C518
10U_0805_10V4Z

2

2

112

JUMP_43X118

+5VS

+5V_SATA

+3VS

1 2

R351

C275

1 2

1U_0603_10V4Z

240K_0402_5%

10K_0402_5%

Place component's closely IDE CONN.

CD_AGND

JP24

OCTEK_CDR-50JD1

1

C289

0.1U_0402_16V4Z

2

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

1

C520

0.1U_0402_16V4Z

2

1

C290

0.1U_0402_16V4Z

2

CD_AGND

1
3
5
7

9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
53 54

1

C519

0.1U_0402_16V4Z

2

Place component's closely ODD CONN.

+3VALW

5

PLT_RST#

ODDRST#

2

PLT_RST#

U32

1

P

B

4

Y

2

A

G

TC7SH08FU_SSOP5@

3

12

R391 33_0402_5%

Title

Size Document Number R e v

Date: Sheet

SCHEMATIC, M/B LA-3011

 

C308 10P_0402_50V8K

12

Y232.768KHZ_12.5P_1TJS125BJ2A251

IN

NC

OUT

NC

12

R641

1 2

1M_0402_5%

1

CS

2

SK

3

DI

4

DO

LCI_CLK

LCI_RSTSYNC

LCI_RXD0
LCI_RXD1
LCI_RXD2

LCI_TXD0
LCI_TXD1
LCI_TXD2

20K_0402_5%

CLK_PCIE_SATA#
CLK_PCIE_SATA

1
4

12

2
3

+RTCVCC

1

2

R38333_0402_5%
R38433_0402_5%

R38033_0402_5%

R36833_0402_5%

12

R38133_0402_5%

R36933_0402_5%

12

+3VS

+3VS

SATA_TXN0SATA_TXN0_C

C291 10P_0402_50V8K

U31

8

VCC

7

NC

6

NC

5

GND

AT93C46-10SI-2.7_SO8@

ACZ_BITCLK
ACZ_SYNC

ACZ_RST#

ICH_AC_SDIN0
ACZ_SDIN1

R311

R385

+RTCVCC

D D

ICH_BITCLK_AUDIO

C C

B B

20K_0402_5%

CMOS_CLR1

1 2

SHORT PADS

C498

1U_0603_10V4Z

1 2

ACZ_BITCLK_MDC

ACZ_SYNC_MDC

ICH_SYNC_AUDIO

ACZ_RST#_MDC

ICH_RST_AUDIO#

+3VALW

12

R621
332K_0402_1%@

1 2

+3VALW

C283

0.1U_0402_16V4Z@

R649

C602

1 2

12

10P_0402_25V8K@

+RTCVCC

12

R620
332K_0402_1%

12

R623

SATA_TXP0_C SATA_TXP0

10_0402_5%@

1 2
1 2
1 2

1 2

ICH_SDOUT_AUDIO

ACZ_SDOUT_MDC

PHDD_LED#

ICH_INTVRMEN

0_0402_5%@

C282 3900P_0402_50V7K

1 2

C279 3900P_0402_50V7K

1 2

Near ICH7 side.

SATA_RXN0_C

SATA_RXP0_C

C219 3900P_0402_50V7K

1 2

C221 3900P_0402_50V7K

1 2

SATA_RXN0

SATA_RXP0

Near Device side.

A A

5

5

4

3

2

1

Place closely pin B2 Place c losely pin AC1

100K_0402_5%

1 2

1

B

2

A

CLK_14M_ICH

12

R655

10_0402_5%@

1

C605

4.7P_0402_50V8C@

2

12

R284

C187

0.1U_0402_16V4Z

SLP_S4#
SLP_S5#

+3VA

R640
10K_0402_5%

PM_SLP_S5#

CLK_48M_ICH

12

R367

10_0402_5%@

1

C313

4.7P_0402_50V8C@

2

TC7SH08FU_SSOP5

USB_OC#4
USB_OC#5
USB_OC#6
USB_OC#7

USB_OC#3
USB_OC#0
USB_OC#1
USB_OC#2

DPRSLPVR

+3VA

5

U11

P

4

Y

G

3

RP29

4 5
3 6
2 7
1 8

10K_1206_8P4R_5%

RP28

4 5
3 6
2 7
1 8

10K_1206_8P4R_5%

+3VA

R254

R256

1 2

10K_0402_5%

1 2

ICH_SMBCLK

ICH_SMBDATA

ICH_SMBCLK
ICH_SMBDATA

PCIE_RXN1

PCIE_RXP1
PCIE_TXN1
PCIE_TXP1

PCIE_RXN2

PCIE_RXP2
PCIE_TXN2
PCIE_TXP2

PCIE_WAKE#

VGATE

LINKALERT#

SIRQ

PM_CLKRUN#

BT_DET#

12

DBRESET#

OCP#

EC_SWI#

ICH_LOW_BAT#

12

SPI_CS#

SPI_MOSI

SPI_MISO

SB_PCIE_WAKE#

10K_0402_5%

D D

+3VS

C C

+3VA

B B

A A

R285

R249

R281

R297

R365

R275

R264

R245

R280

R626

R625

R382

10K_0402_5%@

1 2

10K_0402_5%

1 2

8.2K_0402_5%

1 2

100K_0402_5%

10K_0402_5%

1 2

10K_0402_5%

1 2

8.2K_0402_5%

1 2

8.2K_0402_5%

10K_0402_5%

1 2

10K_0402_5%

1 2

10K_0402_5%

1 2

1K_0402_5%

1 2

R268

1 2
1 2

R272

2.2K_0402_5%
0_0402_5%

0_0402_5%

SB_INT_FLASH_SEL#

R614 0_0402_5%

R273

EC_SWI#

SB_SPKR
SUS_STAT#
DBRESET#

PM_BMBUSY#

OCP#

H_STP_PCI#

H_STP_CPU#

PM_CLKRUN#

IDE_RESET#

1 2

SIRQ

EC_THERM#

R276

1 2

EC_SMI#

+3VA

12

0_0402_5%

C2010.1U_0402_16V7K

12

C2000.1U_0402_16V7K

12

C2030.1U_0402_16V7K

12

C2020.1U_0402_16V7K

12

12

R269

2.2K_0402_5%

ICH_SMB_CLK
ICH_SMB_DATA
LINKALERT#
ICH_SMLINK0
ICH_SMLINK1

SB_SPKR
SUS_STAT#
DBRESET#

PM_BMBUSY#
OCP#
H_STP_PCI#

H_STP_CPU#

PM_CLKRUN#

SB_PCIE_WAKE#
SIRQ

EC_THERM#

PCIE_RXN1
PCIE_RXP1
PCIE_C_TXN1
PCIE_C_TXP1

PCIE_RXN2
PCIE_RXP2
PCIE_C_TXN2
PCIE_C_TXP2

SPI_CS#

SPI_MOSI
SPI_MISO

EC_SWI#

EC_SMI#

USB_OC#0
USB_OC#1
USB_OC#2
USB_OC#3
USB_OC#4
USB_OC#5
USB_OC#6
USB_OC#7

U21C

C22

SMBCLK

B22

SMBDATA

A26

LINKALERT#

B25

SMLINK0

A25

SMLINK1

A28

RI#

A19

SPKR

A27

SUS_STAT#

A22

SYS_RST#

AB18

GPIO0 / BM_BUSY#

B23

GPIO11 / SMBALERT#

AC20

GPIO18 / STPPCI#

AF21

GPIO20 / STPCPU#

A21

GPIO26

B21

GPIO27

E23

GPIO28

AG18

GPIO32 / CLKRUN#

AC19

GPIO33 / AZ_DOCK_EN#

U2

GPIO34 / AZ_DOCK_RST#

F20

WAKE#

AH21

SERIRQ

AF20

THRM#

AD22

VRMPWRGD

AC21

GPIO6

AC18

GPIO7

E21

GPIO8

ICH7_BGA652~D

U21D

F26

PERn1

F25

PERp1

E28

PETn1

E27

PETp1

H26

PERn2

H25

PERp2

G28

PETn2

G27

PETp2

K26

PERn3

K25

PERp3

J28

PETn3

J27

PETp3

M26

PERn4

M25

PERp4

L28

PETn4

L27

PETp4

P26

PERn5

P25

PERp5

N28

PETn5

N27

PETp5

T25

PERn6

T24

PERp6

R28

PETn6

R27

PETp6

R2

SPI_CLK

P6

SPI_CS#

P1

SPI_ARB

P5

SPI_MOSI

P2

SPI_MISO

D3

OC0#

C4

OC1#

D5

OC2#

D4

OC3#

E5

OC4#

C3

OC5# / GPIO29

A2

OC6# / GPIO30

B3

OC7# / GPIO31

ICH7_BGA652~D

SMB

SATA

SYS

Clocks

GPIO

POWER MGT

GPIO

Need update symbol

DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP

DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP

PCI-EXPRESS

DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP

DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP

DMI_CLKN
DMI_CLKP

DIRECT MEDIA INTERFACE

DMI_ZCOMP

DMI_IRCOMP

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N

SPI

USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P

USB

USBP6N
USBP6P
USBP7N
USBP7P

USBRBIAS#

USBRBIAS

GPIO21 / SATA0GP
GPIO19 / SATA1GP
GPIO36 / SATA2GP
GPIO37 / SATA3GP

GPIO

GPIO16 / DPRSLPVR

TP0 / BATLOW#

PWRBTN#

LAN_RST#

GPIO35 / SATAREQ#

V26
V25
U28
U27

Y26
Y25
W28
W27

AB26
AB25
AA28
AA27

AD25
AD24
AC28
AC27

AE28
AE27

C25
D25

F1
F2
G4
G3
H1
H2
J4
J3
K1
K2
L4
L5
M1
M2
N4
N3

D2
D1

CLK14
CLK48

SUSCLK

SLP_S3#
SLP_S4#
SLP_S5#

PWROK

RSMRST#

GPIO9
GPIO10
GPIO12
GPIO13
GPIO14
GPIO15
GPIO24
GPIO25

GPIO38
GPIO39

AF19
AH18
AH19
AE19

AC1
B2

C20
B24

D23
F22

AA4
AC22
C21
C23
C19
Y4

E20
A20
F19
E19
R4
E22
R3
D20
AD21
AD20
AE20

DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0

DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1

DMI_RXN2
DMI_RXP2
DMI_TXN2
DMI_TXP2

DMI_RXN3
DMI_RXP3
DMI_TXN3
DMI_TXP3

CLK_PCIE_ICH#
CLK_PCIE_ICH

DMI_IRCOMP
USB20_N0

USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5
USB20_N6
USB20_P6
USB20_N7
USB20_P7

USBRBIAS

R295

100_0402_5%

1 2

CLK_14M_ICH
CLK_48M_ICH

ICH_SUSCLK

PM_SLP_S3#
SLP_S4#

SLP_S5#
PWROK
DPRSLPVR
ICH_LOW_BAT#

PBTN_OUT#

EC_RSMRST#

R645 10K_0402_5%

1 2

EC_SCI#

BT_DET#
EC_LID_OUT#

EC_FLASH#
SATA_CLKREQ#

R610 24.9_0402_1%

1 2

R656 22.6_0402_1%

1 2

Within 500 mils

CLK_14M_ICH
CLK_48M_ICH

T31 PAD

PWROK
DPRSLPVR

PBTN_OUT#
LAN_RST#
EC_RSMRST#

EC_LID_OUT#

DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0

DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1

DMI_RXN2
DMI_RXP2
DMI_TXN2
DMI_TXP2

DMI_RXN3
DMI_RXP3
DMI_TXN3
DMI_TXP3

CLK_PCIE_ICH#
CLK_PCIE_ICH

Within 500 mils

USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5
USB20_N6
USB20_P6
USB20_N7
USB20_P7

1 2

EC_SCI#

BT_DET#

NVM_PORT
LAN_DISABLE#
ODDRST#
EC_FLASH#
SATA_CLKREQ#

+1.5VS

PM_SLP_S3#

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/06/01 2006/06/01

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3011

 

401395

05

20 48, 01, 20

1

A

of

5

4

3

2

1

112

+3VS

+RTCVCC

+3VALW+3VA

U21E

A4

VSS[0]

A23

VSS[1]

B1

VSS[2]

B8

VSS[3]

B11

VSS[4]

B14

VSS[5]

B17

VSS[6]

B20

VSS[7]

B26

VSS[8]

B28

VSS[9]

C2

VSS[10]

C6

VSS[11]

C27

VSS[12]

D10

VSS[13]

D13

VSS[14]

D18

VSS[15]

D21

VSS[16]

D24

VSS[17]

E1

VSS[18]

E2

VSS[19]

E4

VSS[21]

E8

VSS[22]

E15

VSS[23]

F3

VSS[24]

F4

VSS[25]

F5

VSS[26]

F12

VSS[27]

F27

VSS[28]

F28

VSS[29]

G1

VSS[30]

G2

VSS[31]

G5

VSS[32]

G6

VSS[33]

G9

VSS[34]

G14

VSS[35]

G18

VSS[36]

G21

VSS[37]

G24

VSS[38]

G25

VSS[39]

G26

VSS[40]

H3

VSS[41]

H4

VSS[42]

H5

VSS[43]

H24

VSS[44]

H27

VSS[45]

H28

VSS[46]

J1

VSS[47]

J2

VSS[48]

J5

VSS[49]

J24

VSS[50]

J25

VSS[51]

J26

VSS[52]

K24

VSS[53]

K27

VSS[54]

K28

VSS[55]

L13

VSS[56]

L15

VSS[57]

L24

VSS[58]

L25

VSS[59]

L26

VSS[60]

M3

VSS[61]

M4

VSS[62]

M5

VSS[63]

M12

VSS[64]

M13

VSS[65]

M14

VSS[66]

M15

VSS[67]

M16

VSS[68]

M17

VSS[69]

M24

VSS[70]

M27

VSS[71]

M28

VSS[72]

N1

VSS[73]

N2

VSS[74]

N5

VSS[75]

N6

VSS[76]

N11

VSS[77]

N12

VSS[78]

N13

VSS[79]

N14

VSS[80]

N15

VSS[81]

N16

VSS[82]

N17

VSS[83]

N18

VSS[84]

N24

VSS[85]

N25

VSS[86]

N26

VSS[87]

P3

VSS[88]

P4

VSS[89]

P12

VSS[90]

P13

VSS[91]

P14

VSS[92]

P15

VSS[93]

P16

VSS[94]

P17

VSS[95]

P24

VSS[96]

P27

VSS[97]

ICH7_BGA652~D

VSS[98]

VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]

P28
R1
R11
R12
R13
R14
R15
R16
R17
R18
T6
T12
T13
T14
T15
T16
T17
U4
U12
U13
U14
U15
U16
U17
U24
U25
U26
V2
V13
V15
V24
V27
V28
W6
W24
W25
W26
Y3
Y24
Y27
Y28
AA1
AA24
AA25
AA26
AB4
AB6
AB11
AB14
AB16
AB19
AB21
AB24
AB27
AB28
AC2
AC5
AC9
AC11
AD1
AD3
AD4
AD7
AD8
AD11
AD15
AD19
AD23
AE2
AE4
AE8
AE11
AE13
AE18
AE21
AE24
AE25
AF2
AF4
AF8
AF11
AF27
AF28
AG1
AG3
AG7
AG11
AG14
AG17
AG20
AG25
AH1
AH3
AH7
AH12
AH23
AH27

J8

2

JUMP_43X118

1

C587

0.1U_0402_16V4Z

2

1

1

C591

C590

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

ICH_V5REF_RUN

C209

C210

10U_0805_10V4Z

+3VS

+1.5VS

C606

0.1U_0402_16V4Z

+1.5VS

1

+

C548

2

0.1U_0402_16V4Z

220U_D2_4VM

+1.5VS_DMIPLL+1.5VS_DMIPLLR

1

1

C546

2

2

0.01U_0402_16V7K

1

C578

2

0.1U_0402_16V4Z

1

2

1

2

Place closely pin
D28,T28,AD28.

Place closely pin AG5.

Place closely pin AG9.

D D

100_0402_5%

10_0402_5%

C C

B B

A A

R338

R337

12

12

+3VS+5VS

21

D14
CH751H-40_SC76

ICH_V5REF_RUN

1

C579

0.1U_0402_16V4Z

2

+3VA+5VALW

21

D15
CH751H-40_SC76

ICH_V5REF_SUS

1

C588

0.1U_0402_16V4Z

2

+1.5VS

1

C570

0.1U_0402_16V4Z

2

Place closely pin AG28 within 100mlis.

C599

1 2

0_0805_5%

1

C600

2

1

2

R250

0.1U_0402_16V4Z

R241

1 2

0.5_0805_1%

0.1U_0402_16V4Z

+1.5VS

+3VA

0.1U_0402_16V4Z

1

C545

C547

2

0.1U_0402_16V4Z

C551

0.1U_0402_16V4Z

+1.5VS

C592

0.1U_0402_16V4Z

+1.5VS

C251

1U_0603_10V4Z

T36 P AD
T33 P AD

@
@

+3VA

ICH_V5REF_SUS

1

2

+3VS

1

2

+1.5VS_DMIPLL

1

2

1

2

ICH_AA2
ICH_Y7

ICH_SUSLAN

G10

AD17

F6

AA22
AA23
AB22
AB23
AC23
AC24
AC25
AC26
AD26
AD27
AD28

D26
D27
D28
E24
E25
E26
F23
F24
G22
G23
H22
H23
J22
J23
K22
K23
L22

L23
M22
M23

N22

N23

P22

P23

R22

R23

R24

R25

R26

T22

T23

T26

T27

T28

U22

U23

V22

V23
W22
W23

Y22

Y23

B27

AG28

AB7
AC6
AC7
AD6

AE6

AF5

AF6
AG5
AH5

AD2

AH11
AB10

AB9

AC10
AD10
AE10
AF10

AF9
AG9
AH9

E3

C1

AA2

Y7
V5

V1
W2
W7

1

C583

0.1U_0402_16V4Z

2

U21F

V5REF[1]
V5REF[2]
V5REF_Sus
Vcc1_5_B[1]

Vcc1_5_B[2]
Vcc1_5_B[3]
Vcc1_5_B[4]
Vcc1_5_B[5]
Vcc1_5_B[6]
Vcc1_5_B[7]
Vcc1_5_B[8]
Vcc1_5_B[9]
Vcc1_5_B[10]
Vcc1_5_B[11]
Vcc1_5_B[12]
Vcc1_5_B[13]
Vcc1_5_B[14]
Vcc1_5_B[15]
Vcc1_5_B[16]
Vcc1_5_B[17]
Vcc1_5_B[18]
Vcc1_5_B[19]
Vcc1_5_B[20]
Vcc1_5_B[21]
Vcc1_5_B[22]
Vcc1_5_B[23]
Vcc1_5_B[24]
Vcc1_5_B[25]
Vcc1_5_B[26]
Vcc1_5_B[27]
Vcc1_5_B[28]
Vcc1_5_B[29]
Vcc1_5_B[30]
Vcc1_5_B[31]
Vcc1_5_B[32]
Vcc1_5_B[33]
Vcc1_5_B[34]
Vcc1_5_B[35]
Vcc1_5_B[36]
Vcc1_5_B[37]
Vcc1_5_B[38]
Vcc1_5_B[39]
Vcc1_5_B[40]
Vcc1_5_B[41]
Vcc1_5_B[42]
Vcc1_5_B[43]
Vcc1_5_B[44]
Vcc1_5_B[45]
Vcc1_5_B[46]
Vcc1_5_B[47]
Vcc1_5_B[48]
Vcc1_5_B[49]
Vcc1_5_B[50]
Vcc1_5_B[51]
Vcc1_5_B[52]
Vcc1_5_B[53]

Vcc3_3[1]
VccDMIPLL
Vcc1_5_A[1]

Vcc1_5_A[2]
Vcc1_5_A[3]
Vcc1_5_A[4]
Vcc1_5_A[5]
Vcc1_5_A[6]
Vcc1_5_A[7]
Vcc1_5_A[8]
Vcc1_5_A[9]

VccSATAPLL
Vcc3_3[2]
Vcc1_5_A[10]

Vcc1_5_A[11]
Vcc1_5_A[12]
Vcc1_5_A[13]
Vcc1_5_A[14]
Vcc1_5_A[15]
Vcc1_5_A[16]
Vcc1_5_A[17]
Vcc1_5_A[18]

VccSus3_3[19]
VccUSBPLL
VccSus1_05/VccLAN1_05[1]

VccSus1_05/VccLAN1_05[2]
VccSus3_3/VccLAN3_3[1]

VccSus3_3/VccLAN3_3[2]
VccSus3_3/VccLAN3_3[3]
VccSus3_3/VccLAN3_3[4]

ICH7_BGA652~D

Vcc1_05[1]
Vcc1_05[2]
Vcc1_05[3]
Vcc1_05[4]
Vcc1_05[5]
Vcc1_05[6]
Vcc1_05[7]
Vcc1_05[8]

Vcc1_05[9]
Vcc1_05[10]
Vcc1_05[11]
Vcc1_05[12]
Vcc1_05[13]
Vcc1_05[14]
Vcc1_05[15]
Vcc1_05[16]
Vcc1_05[17]
Vcc1_05[18]
Vcc1_05[19]
Vcc1_05[20]

Vcc3_3 / VccHDA

VccSus3_3/VccSusHDA

V_CPU_IO[1]
V_CPU_IO[2]
V_CPU_IO[3]

Vcc3_3[3]
Vcc3_3[4]
Vcc3_3[5]
Vcc3_3[6]
Vcc3_3[7]
Vcc3_3[8]

Vcc3_3[9]
Vcc3_3[10]
Vcc3_3[11]

Vcc3_3[12]
Vcc3_3[13]
Vcc3_3[14]
Vcc3_3[15]
Vcc3_3[16]
Vcc3_3[17]
Vcc3_3[18]
Vcc3_3[19]
Vcc3_3[20]
Vcc3_3[21]

VccRTC
VccSus3_3[1]
VccSus3_3[2]

VccSus3_3[3]
VccSus3_3[4]
VccSus3_3[5]
VccSus3_3[6]

VccSus3_3[7]
VccSus3_3[8]
VccSus3_3[9]

VccSus3_3[10]
VccSus3_3[11]
VccSus3_3[12]
VccSus3_3[13]
VccSus3_3[14]
VccSus3_3[15]
VccSus3_3[16]
VccSus3_3[17]
VccSus3_3[18]

Vcc1_5_A[19]
Vcc1_5_A[20]

Vcc1_5_A[21]
Vcc1_5_A[22]
Vcc1_5_A[23]

Vcc1_5_A[24]
Vcc1_5_A[25]

VccSus1_05[1]
VccSus1_05[2]

VccSus1_05[3]

Vcc1_5_A[26]
Vcc1_5_A[27]
Vcc1_5_A[28]
Vcc1_5_A[29]
Vcc1_5_A[30]

L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18

U6
R7
AE23

AE26
AH26

AA7
AB12
AB20
AC16
AD13
AD18
AG12
AG15
AG19

A5
B13
B16
B7
C10
D15
F9
G11
G12
G16

W5
P7
A24

C24
D19
D22
G19

K3
K4
K5
K6
L1
L2
L3
L6
L7
M6
M7
N7

AB17
AC17

T7
F17
G17

AB8
AC8

K7
C28

G20
A1

H6
H7
J6
J7

+VCCP

0.1U_0402_16V4Z

1

C567

C198

2

1U_0603_10V4Z

1

C573

2

0.1U_0402_16V4Z

1

C558

0.1U_0402_16V4Z

2

1

C589

0.1U_0402_16V4Z

2

+1.5VS

1 2

C568 0.1U_0402_16V4Z

ICH_K7
ICH_C28

ICH_G20

+1.5VS

1

C586

0.1U_0402_16V4Z

2

1

2

+3VA

+3VS

1

C572

0.1U_0402_16V4Z

2

1

1

C577

2

2

0.1U_0402_16V4Z

1

C565

0.1U_0402_16V4Z

2

1

C597

0.1U_0402_16V4Z

2

@
@

@

1

+

C218

330U_D2E_2.5VM_R9

2

+3VS

C596

0.1U_0402_16V4Z

T34PAD
T28PAD

T30PAD

+VCCP

+3VA

+3VA

C553

1 2

0.1U_0402_16V4Z

1 2

C552

0.1U_0402_16V4Z

1 2

C199

4.7U_0805_10V4Z

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/06/01 2006/06/01

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet of

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3011

 

401395

05

21 48, 01, 20

1

A

5

+3VS

CHB1608U301_0603

L16

D D

PCI_AD[0..31]

PCI_CBE #[0 ..3]

C C

TYCO_1470383-2

4

6

3

G

5

2

G

1

B B

JP25

PCI_AD[0..31]
PCI_CB E#[0 ..3]

CLK_48M_CB

2

12

C231

1U_0603_10V4Z

12

R287

56.2_0603_1%

1

C224

2

220P_0402_50V7K

R289

1

4
3
2
1

CLOSE TO CHIP

R608 1K_0402_5%
R220 0_0402_5%
R605 4.7K_0402_5%

+3VS

12

R290

56.2_0603_1%

56.2_0603_1%

12

R288

56.2_0603_1%

12

R301

5.1K_0603_1%

+AVDD_7411

12

C555

0.1U_0402_16V4Z

MC_PWRON#
SM_RB

SD_CD#
MS_CD#

MSCLK_SDCLK_SMELWP#
MSBS_SDCMD_SMWE#
MSD3_SDD3_SMD3
MSD2_SDD2_SMD2
MSD1_SDD1_SMD1
MSD0_SDD0_SMD0

SMRE
SDCMD_SMALE
SDD0_SMD4
SDD1_SMD5
SDD2_SMD6
SDD3_SMD7
SDWP#_SMCE#

SMCLE
XD_CD#

1 2
1 2
1 2

R609 6.34K_0402_1%

XTPBIAS0
XTPA0+
XTPA0­XTPB0+
XTPB0­XTPBIAS1
XTPA1+
XTPA1-

XTPB1­CPS

+3VS

R607

1 2

4.7K_0402_5%

0.1U_0402_16V4Z

1

1

C554

2

2

0.01U_0402_16V7K

1 2

X_OUT
X_IN

CPS

0.01U_0402_16V7K

1

1

C564

C566

2

2

U13B

C8

MC_PWR_CTRL_0

F8

MC_PWR_CTRL_1/SM_R/B#

E9

SD_CD#

A8

MS_CD#

B8

SM_CD#

A7

MS_CLK/SD_CLK/SM_EL_WP#

E8

MS_BS/SD_CMD/SM_WE#

B6

MS_DATA3/SD_DAT3/SM_D3

A6

MS_DATA2/SD_DAT2/SM_D2

C7

MS_DATA1/SD_DAT1/SM_D1

B7

MS_SDIO(DATA0)/SD_DAT0/SM_D0

A4

SD_CLK/SM_RE#

C5

SD_CMD/SM_ALE

C6

SD_DAT0/SM_D4

A5

SD_DAT1/SM_D5

B5

SD_DAT2/SM_D6

E6

SD_DAT3/SM_D7

E7

SD_WP/SM_CE#

G5

SC_PWR_CTRL

B4

SM_CLE

A3

XD_CD#/SM_PHYS_WP#

P12

TEST0

F1

CLK_48

P17

PHY_TEST_MA

T18

R0

T19

R1

R13

TPBIAS0

V14

TPA0P

W14

TPA0N

V13

TPB0P

W13

TPB0N

W17

TPBIAS1

V16

TPA1P

W16

TPA1N

V15

TPB1P

W15

TPB1N

R12

CPS

R18

XO

R19

XI

CLOSE TO CHIP

12

2

C232

1

XTPA1+
XTPA1­XTPB1+
XTPB1-

A A

1U_0603_10V4Z

R291

C228

12

R293

R294

56.2_0603_1%

56.2_0603_1%

XTPBIAS1
XTPA1+
XTPA1­XTPB1+
XTPB1-

12

12

R292

56.2_0603_1%

56.2_0603_1%

12

1

R302

2

5.1K_0603_1%

220P_0402_50V7K

5

4

10U_0805_10V4Z

C550

AVDD_33

U19

VDDPLL_33

P15

VDDPLL_15

1 2

K19

VR_PORTK1VR_PORT

1

C569

10U_0805_10V4Z

2

P13

P14

AVDD_33

AVDD_33

U15

PCI7412

VSSPLL

AGND

AGND

AGND

R17

R14

U13

U14

+VDDPLL

C56218P_0402_50V8J

24.576MHz_16P_3XG-24576-43E1

C54018P_0402_50V8J

4

1

C561

C563

2

0.01U_0402_16V7K

+VDDPLL

0.1U_0402_16V4Z

1 2

C549 1U_0603_10V4Z

W8

VCCPP1VCCP

DEVSEL#

RI_OUT#/PME#

SUSPEND#

SPKROUT

MFUNC0
MFUNC1
MFUNC2
MFUNC3
MFUNC4
MFUNC5
MFUNC6

PCI7412ZHK_PBGA257PCI7412@

X_OUT

X2

1 2

X_IN

0.01U_0402_16V7K

1

C560

2

AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10

AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0

C/BE3#
C/BE2#
C/BE1#
C/BE0#

PAR

FRAME#

TRDY#

IRDY#

STOP#

IDSEL
PERR#
SERR#

REQ#
GNT#

PCLK
PRST#
GRST#

SCL
SDA

VR_EN#

1

2

0.1U_0402_16V4Z

PCI_AD31

M1

PCI_AD30

M2

PCI_AD29

M3

PCI_AD28

M6

PCI_AD27

M5

PCI_AD26

N1

PCI_AD25

N2

PCI_AD24

N3

PCI_AD23

P3

PCI_AD22

R1

PCI_AD21

R2

PCI_AD20

P5

PCI_AD19

R3

PCI_AD18

T1

PCI_AD17

T2

PCI_AD16

W4

PCI_AD15

W7

PCI_AD14

R8

PCI_AD13

U8

PCI_AD12

V8

PCI_AD11

W9

PCI_AD10

V9

PCI_AD9

U9

PCI_AD8

R9

PCI_AD7

V10

PCI_AD6

U10

PCI_AD5

R10

PCI_AD4

W11

PCI_AD3

V11

PCI_AD2

U11

PCI_AD1

P11

PCI_AD0

R11

PCI_CBE#3

P2

PCI_CBE#2

U5

PCI_CBE#1

V7

PCI_CBE#0

W10
U7

R6
W5
V5
V6
U6
N5
R7
W6
L3
L2

L1
K3
K5
L5

J5
H3
G1

H5
H2
H1
J1
J2
J3

G2

1 2

R234 300_0402_5%

G3

1 2

R600 300_0402_5%

K2

1 2

3

CHB1608U301_0603

1

C556

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

1

C538

2

0.1U_0402_16V4Z

R258

12

100_0402_5%

CLK_PCI_PCM

R606

5IN1_LED

1

C204

0.1U_0402_16V4Z

2

1 2

1

2

PCI_AD22

PCI_RST#

+3VS

R604 10K_0402_5%

1

C559

2

1 2

43K_0402_5%

R248
1K_0402_5%

Security Classification

Issued Date

THIS SHEET OF E NGI NEER ING DR AWI NG I S T HE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONIC S, INC. AND C ONTAINS CONFID ENTIAL
AND TRADE S ECR ET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+3VS

L15

+3VS

0.01U_0402_16V7K

1

C542

2

PCI_PAR
PCI_FRAME#
PCI_TRDY#

PCI_IRDY#

PCI_STOP#

PCI_DEVSEL#
PCI_PERR#

PCI_SERR#
PCI_REQ2#

PCI_GNT2#

CLK_PCI_PCM

PCI_RST#

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#

SIRQ

PCI_PIRQD#

5IN1_LED#

12

1

C539

2

0.01U_0402_16V7K

+3VS

2005/06/01 2006/06/01

2

C544

1

12

R591
33K_0603_1%

Compal Secret Data

C541

1U_0603_10V4Z

PCM_SPK

10K_0402_5%

MC_PWRON#

Deciphered Date

2

MSD0_SDD0_SMD0
MSD1_SDD1_SMD1
MSD2_SDD2_SMD2
MSD3_SDD3_SMD3
SDD0_SMD4
SDD1_SMD5
SDD2_SMD6
SDD3_SMD7

MSBS_SDCMD_SMWE
SMELWP#
SDCMD_SMALE
XD_CD#
SM_RB
SMRE
SDWP#_SMCE
SMCLE

+3VS

R298

1 2

2

MSBS_SDCMD_SMWE

SMRE

SDWP#_SMCE

SM_RB

MSCLK_SDCLK_SMELWP#

place near Chip 7411

5 in 1 CardReader C onn.

JP29

41

XD-VCC

33

XD-D0

34
35
36
37
38
39
40

30
31
29
23
25
26
27
28

32
24

42
18

CLK_48M_CB

12

R205

2

C191

1

U16

1
2
3
4

G528_SO8

XD-D1
XD-D2
XD-D3
XD-D4
XD-D5
XD-D6
XD-D7

XD-WE
XD-WP
XD-ALE
XD-CD
XD-R/B
XD-RE
XD-CE
XD-CLE

XD-GND
XD-GND

N.C.
N.C.

TAITW_R007-530-L3

10_0402_5%@

10P_0402_50V8J@

GND

OUT

IN

OUT
OUT

IN

FLG

EN#

4 IN 1 CONN

0.1U_0402_16V4Z

Custom

1

+VCC_5IN1

R260 2.2K_0402_5%

1 2

R262 2.2K_0402_5%

1 2

R261 2.2K_0402_5%

1 2

R263 2.2K_0402_5%

1 2

R176 33_0402_5%

1 2

R175

1 2

33_0402_5%

SD-VCC

MS-VCC

SD_CLK
SD-DAT0
SD-DAT1
SD-DAT2
SD-DAT3

SD-CMD

SD-CD-SW

SD-CD-COM

SD-WP-SW

SD-WP-COM

MS-SCLK
MS-DATA0
MS-DATA1
MS-DATA2
MS-DATA3

MS-INS

SD-GND
SD-GND
MS-GND
MS-GND

CLK_PCI_PCMXTPB1+

12

R253

10_0402_5%@

1

C206

15P_0402_50V8J@

2

+VCC_5IN1

8
7
6
5

C227

Title

Size Document Number Re v

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3011

 

01, 2005



15
9

16
19
20
11
12
13
21
22
43
44

8
4
3
5
7
6
2

MS-BS

14
17
1
10

1

C222

2

1U_0603_10V4Z

401395

MSCLK_SDCLK

SMELWP#

MSCLK_SDCLK
MSD0_SDD0_SMD0
MSD1_SDD1_SMD1
MSD2_SDD2_SMD2
MSD3_SDD3_SMD3
MSBS_SDCMD_SMWE#
SD_CD#

SDWP#_SMCE#

MSCLK_SDCLK
MSD0_SDD0_SMD0
MSD1_SDD1_SMD1
MSD2_SDD2_SMD2
MSD3_SDD3_SMD3
MS_CD#
MSBS_SDCMD_SMWE#

+VCC_5IN1

R310

470_0402_5%

1 2
13

D

Q21

2

G

2N7002_SOT23

S

1

C220

4.7U_0805_10V4Z

2

1

+VCC_5IN1+VCC_5IN1

MC_PWRON#

of

22 48,

A

5

4

+3VS+S1_VCC

3

2

1

CardBus Power Switch

U45

9

12V

F12

F14

J14

L14

VCC

VCCJ6VCC

K14

M14

VCCL6VCC

GND

GNDN6GNDP7GND

P10

VCCP6VCCP8VCC

P9

DATA/VD2/VPPD1

CLOCK/VD1/VCCD0#

LATCH/VD3/VPPD0

RSVD/D2

RSVD/VD0/VCCD1#

RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

PCI7412ZHK_PBGA257

B9
A9
C9

B10
C4
D1
E1
E2
E3
F2
F3
F5
G6
H17
M19

A2
A17
A18
B1
B2
B3
B17
B18
B19
C1
C2
C3
C16
C17
C18
C19
D2
D3
D17
D18
E5
N14
P18
T3
T17
U1
U2
U3
U4
U12
U16
U17
U18
V1
V2
V3
V4
V12
V17
V18
V19
W2
W3
W12
W18

S1_D2

S1_A18
S1_D14

VPPD1
VCCD0#
VPPD0

R174
43K_0402_5%

1 2

VCCD1#

+5VS

C5740.1U_0402_16V4Z
C5764.7U_0805_10V4Z

C5750.1U_0402_16V4Z
C5714.7U_0805_10V4Z

10K_0402_5%

R629

+3VS

5
6

3
4

1 2

Near to PCMCIA slot.

+S1_VCC

1

C223
10U_0805_10V4Z

2

+S1_VPP

1

C233
10U_0805_10V4Z

2

1

2

1

2

5V
5V

3.3V

3.3V

C225

0.1U_0402_16V4Z

C230

0.1U_0402_16V4Z

A15

D D

C C

S1_A16_C

B B

C543

12

100P_0402_25V8K
C183

12

100P_0402_25V8K

R596

1 2

33_0402_5%

S1_CD1#

S1_CD2#

S1_D10
S1_D9
S1_D1
S1_D8
S1_D0
S1_A0
S1_A1
S1_A2
S1_A3
S1_A4
S1_A5
S1_A6
S1_A25
S1_A7
S1_A24
S1_A17
S1_IOWR#
S1_A9
S1_IORD#
S1_A11
S1_OE#
S1_CE2#
S1_A10
S1_D15
S1_D7
S1_D13
S1_D6
S1_D12
S1_D5
S1_D11
S1_D4
S1_D3

S1_REG#
S1_A12
S1_A8
S1_CE1#

S1_A13
S1_A23
S1_A22
S1_A15
S1_A20
S1_A21
S1_A19
S1_A14
S1_WAIT#
S1_INPACK#
S1_WE#
S1_BVD1
S1_WP
S1_A16
S1_RDY#

S1_RST
S1_BVD2
S1_CD1#

S1_CD2#
S1_VS1
S1_VS2

U13A

C10

CAD31/D10

A10

CAD30/D9

F11

CAD29/D1

E11

CAD28/D8

C11

CAD27/D0

B13

CAD26/A0

C13

CAD25/A1

A14

CAD24/A2

B14

CAD23/A3

B15

CAD22/A4

E14

CAD21/A5

A16

CAD20/A6

D19

CAD19/A25

E17

CAD18/A7

F15

CAD17/A24

H19

CAD16/A17

J17

CAD15/IOWR#

J15

CAD14/A9

J18

CAD13/IORD#

K15

CAD12/A11

K17

CAD11/OE#

K18

CAD10/CE2#

L15

CAD9/A10

L18

CAD8/D15

L19

CAD7/D7

M17

CAD6/D13

M18

CAD5/D6

N19

CAD4/D12

M15

CAD3/D5

N17

CAD2/D11

N18

CAD1/D4

P19

CAD0/D3

E13

CC/BE3#/REG#

E18

CC/BE2#/A12

H18

CC/BE1#/A8

L17

CC/BE0#/CE1#

H14

CPAR/A13

E19

CFRAME#/A23

G15

CTRDY#/A22

F17

CIRDY#/A15

G18

CSTOP#/A20

F19

CDEVSEL#/A21

H15

CBLOCK#/A19

G19

CPERR#/A14

C12

CSERR#/WAIT#

C14

CREQ#/INPACK#

G17

CGNT#/WE#

A12

CSTSCHG/BVD1(STSCHG#/RI#)

A11

CCLKRUN#/WP(IOIS16#)

F18

CCLK/A16

E12

CINT#/READY(IREQ#)

C15

CRST#/RESET

B12

CAUDIO/BVD2(SPKR#)

N15

CCD1#/CD1#

B11

CCD2#/CD2#

A13

CVS1/VS1#

B16

CVS2/VS2#

E10

A_USB_EN#

PCI7412@

J19

VCCF6VCCF9VCC

VCCB

VCCB

PCI 7412

GNDF7GND

GND

GND

GNDH6GNDK6GND

F10

F13

G14

VCC
VCC
VCC

VPP

VCCD0
VCCD1

VPPD0
VPPD1

GND

SHDN

TPS2211AIDBR_SSOP16

7

16

OC

13

40mil

12
11

20mil

10

1
2
15
14

8

JP11

DATA11
DATA12
DATA13
DATA14
DATA15

INPACK#

DATA10

SANTA_130602-2

GND
GND

DATA3

CD1#

DATA4
DATA5
DATA6
DATA7

CE1#

ADD10

CE2#

OE#

VS1#

ADD11

IORD#

ADD9

IOWR#

ADD8
ADD17
ADD13
ADD18
ADD14
ADD19

WE#

ADD20

READY

ADD21

VCC
VCC
VPP

VPP
ADD16
ADD22
ADD15
ADD23
ADD12
ADD24

ADD7

ADD25

ADD6

VS2#

ADD5

RESET

ADD4

WAIT#

ADD3
ADD2

REG#
ADD1
BVD2
ADD0

BVD1
DATA0
DATA8
DATA1
DATA9
DATA2

CD2#

GND
GND

+S1_VCC

+S1_VPP

***

WP

1
35
2
36
3
37
4
38
5
39
6
40
7
41
8
42
9
43
10
44
11
45
12
46
13
47
14
48
15
49
16
50
17
51
18
52
19
53
20
54
21
55
22
56
23
57
24
58
25
59
26
60
27
61
28
62
29
63
30
64
31
65
32
66
33
67
34
68

1 2

C594 0.1U_0402_16V4Z
C593 0.1U_0402_16V4Z

1 2

C595 10U_0805_10V4Z

1 2

C582 0.01U_0402_25V4Z

1 2

C580 1U_0603_10V4Z

VCCD0#
VCCD1#
VPPD0
VPPD1

S1_D3
S1_CD1#
S1_D4
S1_D11
S1_D5
S1_D12
S1_D6
S1_D13
S1_D7
S1_D14
S1_CE1#
S1_D15
S1_A10
S1_CE2#
S1_OE#
S1_VS1
S1_A11
S1_IORD#
S1_A9
S1_IOWR#
S1_A8
S1_A17
S1_A13
S1_A18
S1_A14
S1_A19
S1_WE#
S1_A20
S1_RDY#
S1_A21
S1_VCC

S1_VPP
S1_A16_C
S1_A22
S1_A15
S1_A23
S1_A12
S1_A24
S1_A7
S1_A25
S1_A6
S1_VS2
S1_A5
S1_RST
S1_A4
S1_WAIT#
S1_A3
S1_INPACK#
S1_A2
S1_REG#
S1_A1
S1_BVD2
S1_A0
S1_BVD1
S1_D0
S1_D8
S1_D1
S1_D9
S1_D2
S1_D10
S1_WP
S1_CD2#

+S1_VCC

+S1_VPP

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/06/01 2006/06/01

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3011

401395

 

23 48, 01, 2005

1

A

of

5

4

3

2

1

+USB_VCCC

1

+

C117

3

1

3

1

150U_D2_6.3VM

2

150U_D2_6.3VM

2

2

C510

2.2P_0402_50V8C

+USB_VCCA

1

+

C355

2

C353

D D

+5VALW

1

+

C611

150U_D2_6.3VM @

C C

USB20_N2

USB20_P2 USB20_P3

2 port in right side

USB_EN#

2

J7

1

2

3

4

5

6

7

8

9

10

11

12

ACES_88025-120L

+5VALW

USB20_N3

USB_EN#

+5VALW

1

C508

4.7U_0805_10V4Z

2

USB_EN#

+5VALW

1

C359

4.7U_0805_10V4Z

2

USB_EN#

U43

1
2
3
4

G528_SO8

1
2
3
4

GND
IN
IN
EN#

U35

GND
IN
IN
EN#

G528_SO8

OUT
OUT
OUT

FLG

OUT
OUT
OUT

FLG

8
7
6
5

8
7
6
5

+USB_VCCC

+USB_VCCA

USB20_N4
USB20_P4

USB20_N5
USB20_P5

PSOT24C_SOT23

PSOT24C_SOT23

D32

@

D26

@

Bluetooth Conn.

+USB_VCCC

1

C118

0.1U_0402_16V4Z

2

2.2P_0402_50V8C

+USB_VCCA

1

C350

0.1U_0402_16V4Z

2

W=60mils

1

C120
1000P_0402_50V7K

2

1
2
3
4

SUYIN_2537A-04G5T

Place on the left side

C509

USB CONN.2

W=60mils

1

C351
1000P_0402_50V7K

2

1
2
3
4

SUYIN_2537A-04G5T

Place on the rear side

C352

JP21

JP14

VCC
D­D+
GND

VCC
D­D+
GND

***

***

USB CONN. 1

2.2P_0402_50V8C

BT_DET#

BT_RESET#
BT_WAKE_UP

(MAX=200mA)

0.1U_0402_16V4Z

C124

C121

G

2

+3VS

S

Q12
SI2301BDS_SOT23

D

1 3

1

C123

4.7U_0805_10V4Z

2

1

C122
1U_0603_10V4Z

2

+BT_VCC

W=40mils

+3VS

C119 0.1U_0402_16V4Z

5

U7

1

KILL_SW#

BT_RST#

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

P

B

2

A

G

3

R88 0_0402_5%@

3

BT_RESET#

4

Y

TC7SH08FU_SSOP5

2005/06/01 2006/06/01

Compal Secret Data

Deciphered Date

BT_DET#

BT_WAKE_UP

BT_DETACH

WLAN_BT_CLK

USB20_P7

USB20_N7

WLAN_BT_DATA

+BT_VCC

2

B B

BT_PWR

Q10
DTC124EK_SC59

A A

5

+5VS

12

R92
100K_0402_5%

13

2

1

0.1U_0402_16V4Z

2

2.2P_0402_50V8C

JP7

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

ACES_87151-2005

(Top Contact)

Bluetooth Connector

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3011



401395

01, 2005



24 48,

1

of

A

5

KBA[0..19]

ADB[0..7]

L3

1 2

D D

C C

B B

A A

FBM-L11-160808-800LMT_0603

VGA_ENBKL

GMCH_ENBKL

PCI_RST#
PLT_RST#

+3VALW

SKU ID definition,
Please see page 3.

R140
100K_0402_1%

Rc

1 2

C180 0.1U_0402_16V4Z

1 2

R155 0_0402_5%

Rd

R154 8.2K_0402_1%
R153 18K_0402_1%
R136 33K_0402_1%
R137 56K_0402_1%
R138 100K_0402_1%
R139 200K_0402_1%

+LDO3_EC

1 2

R236 10K_0402_5%

+LDO3_EC

RP25

1 8
2 7
3 6
4 5

10K_0804_8P4R_5%

+5VALW

RP27

1 8
2 7
3 6
4 5

4.7K_0804_8P4R_5%

+5VS

+3VALW

22P_0402_50V8J@

SKU_ID

12
12

@

12

@

12

@

12

@

12

@

12

@

IE_BTN#

MODE#
FRD#
SELIO#
FSEL#

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

12

R2574.7K_0402_5%

12

R2654.7K_0402_5%

12

R2771K_0402_5%

12

R2821K_0402_5%

12

R2861K_0402_5%

12

R307100K_0402_5%

5

KBA[0..19]
ADB[0..7]

ECAGND

C213

TP_CLK

TP_DATA

KBA1
KBA4
KBA5

EJCTSW#

R259 33_0402_5%@

12

CLK_PCI_EC

R243 0_0402_5%

1 2

R233 0_0402_5%

1 2

R316 0_0402_5%

1 2

R317 0_0402_5%@

1 2

+5VS

RP24

1 8
2 7
3 6
4 5

4.7K_0804_8P4R_5%

12

PM@

GM@

PME#

DPCONF_S5P

KB_CLK
KB_DATA
PS_CLK
PS_DATA

C207 0.1U_0402_16V4Z

12

+3VALW

R252 47K_0402_5%

1 2

R221 120K_0402_5%@

1 2

R146 10K_0402_5%

1 2

R147 1K_0402_5%

1 2

R184 1K_0402_5%

0.1U_0402_16V4Z

ENBKL

LRST#

12

ENBKL

DPCONF_S5P_R

1394_DILSON_S3P

1394_PHYRST_S3P

4

0.1U_0402_16V4Z

1

1

C217

2

2

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

LPC_FRAME#

SIRQ

DOCKIN#

+3VALW

1 2

PME#

IE_BTN#

+3VALW

R232 100K_0402_5%

KB_CLK

KB_DATA

PS_CLK

PS_DATA
TP_CLK
TP_DATA

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

DKN_B+_ON

EC_SCI#
BT_RST#

BT_WAKE_UP

BKOFF#
FSTCHG
EC_SMI#

R145

1 2

WL_OFF#

EC_SWI#
S4_LATCH
S4_DATA
LID_SW#

MODE#
SYSON
SUSP#
VR_ON

EJCTSW#
BT_DETACH
PBTN_OUT#

PADS_LED#
CAPS_LED#
NUM_LED#
PHDD_LED#

EC_GA20
EC_KBRST#

4

C237

1

2

0.1U_0402_16V4Z

PGD_IN

FRD#
FWR#
FSEL#

R308
10K_0402_5%

5.6K_0402_5%

0.1U_0402_16V4Z

1

C239

2

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

LRST#

DOCKIN#
PGD_IN

FRD#
FWR#
FSEL#
SELIO#
ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7
KBA0
KBA1
KBA2
KBA3
KBA4
KBA5
KBA6
KBA7
KBA8
KBA9
KBA10
KBA11
KBA12
KBA13
KBA14
KBA15
KBA16
KBA17
KBA18
KBA19

IE_BTN#

12

KB_CLK
KB_DATA
PS_CLK
PS_DATA
TP_CLK
TP_DATA

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

DKN_B+_ON
EC_SCI#
BT_RST#
BT_WAKE_UP
ENBKL
BKOFF#

FSTCHG

EC_SMI#

DPCONF_S5P_R

LID_SW#
MODE#
SYSON
SUSP#
VR_ON
EJCTSW#
BT_DETACH

PBTN_OUT#

PADS_LED#
CAPS_LED#
NUM_LED#

3

+LDO3_EC

R198

Change to 0 ohm

1 2

2

C214

1000P_0402_50V7K

1

15
14
13
10

165

18
25

24

150
151
173
152
138
139
140
141
144
145
146
147
124
125
126
127
128
131
132
133
143
142
135
134
130
129
121
120
113
112
104
103
108
105

110
111
114
115
116
117

163
164
169
170

20
21
22
27
28
48
62
63
69
70

75
109
118
119
148
149
155
156
162
168

55

54

23

41

19

31

C181

U14

LAD0
LAD1
LAD2
LAD3

9

LFRAME#
LRST#/GPIO2C
LCLK

7

SERIRQ
CLKRUN#/GPIO0C
LPCPD#/GPIO0B

RD#
WR#
MEMCS#
IOCS#
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1/XIOP_TP
A2
A3
A4/DMRP_TP
A5/EMWB_TP
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20/GPIO23
E51CS#/GPIO20/ISPEN

PSCLK1
PSDAT1
PSCLK2

PS2 Interface

PSDAT2
PSCLK3
PSDAT3

SCL1
SDA1
SCL2
SDA2

8

GPIO04
GPIO07
GPIO08
GPIO09
GPIO0D
GPIO0E
GPIO10
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO24
GPIO25
GPIO26
GPIO27
GPIO28
GPIO29
GPIO2A
GPIO2B
GPIO2D

FnLock#/GPIO12
CapLock#/GPIO011
NumLock#/GPIO0A
ScrollLock#/GPIO0F
ECRST#

5

GA20/GPIO02

6

KBRST#/GPIO03
ECSCI#

2

1

LPC Interface

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS , INC . AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

0_0603_5%

C192
1000P_0402_50V7K

VCC16VCC34VCC45VCC

*

*

X-BUS Interface

SMBus

GPIO

*

*
*

*

MISC

1

C189

2

0.1U_0402_16V4Z

ECAGND

95

136

157

166

VCC

VCC

VCC

96

161

159

VCCA

AGND

VCCBAT

BATGND

FAN2PWM/GPOW2/PWM2

Pulse Width

FAN1PWM/GPOW7/PWM7

GPOK0/KSO0
GPOK1/KSO1
GPOK2/KSO2
GPOK3/KSO3
GPOK4/KSO4
GPOK5/KSO5
GPOK6/KSO6
GPOK7/KSO7
GPOK8/KSO8

GPOK9/KSO9
GPOK10/KSO10
GPOK11/KSO11
GPOK12/KSO12
GPOK13/KSO13
GPOK14/KSO14
GPOK15/KSO15
GPOK16/KSO16
GPOK17/KSO17

Internal Keyboard

GPOW0/PWM0
GPOW1/PWM1

GPOW3/PWM3
GPOW4/PWM4
GPOW5/PWM5
GPOW6/PWM6

GPIK0/KSI0
GPIK1/KSI1
GPIK2/KSI2
GPIK3/KSI3
GPIK4/KSI4
GPIK5/KSI5
GPIK6/KSI6
GPIK7/KSI7

123

Wake Up Pin

TIN1/GPWU6

TIN2/FANFB2/GPWU7

GPIAD0/AD0
GPIAD1/AD1
GPIAD2/AD2

ENE-KB910-B4

Analog To Digital

Digital To Analog

Expanded I/O

FAN

TEST_TP/GPIO05/FAN3PWM

Timer Pin

GND17GND35GND46GND

GND

GND

122

137

167

2005/06/01 2006/06/01

3

GPIAD3/AD3
GPIAD4/AD4
GPIAD5/AD5
GPIAD6/AD6
GPIAD7/AD7

GPODA0/DA0

GPODA1/DA1

GPODA2/DA2

GPODA3/DA3

GPODA4/DA4

GPODA5/DA5

GPODA6/DA6

GPODA7/DA7

GPIO18/XIO8CS#

*

GPIO19/XIO9CS#

*

GPIO1A/XIOACS#

*

*

GPIO1B/XIOBCS#
GPIO1C/XIOCCS#

*

GPIO1D/XIODCS#

*

GPIO1E/XIOECS#

*

GPIO1F/XIOFCS#

*

GPIO2E/TOUT1/FANFB1

DPLL_TP/GPIO06/FANFB3

TOUT2/GPIO2F

E51IT0/GPIO00
E51IT1/GPIO01

E51RXD/GPIO21/ISPCLK

E51TXD/GPIO22/ISPDAT

KB910Q B4_LQFP176

Compal Secret Data

Deciphered Date

0.1U_0402_16V4Z

49
50
51
52
53
56
57
58
59
60
61
64
65
66
67
68
153
154

71
72
73
74
77
78
79
80

32
33
36
37
38
39
40
43

2

GPWU0

26

GPWU1

29

GPWU2

30

GPWU3

44

GPWU4

76

GPWU5

172
176

81
82
83
84
87
88
89
90

99
100
101
102
1
42
47
174

85
86
91
92
93
94
97
98

171
12
11

175
3

4
106
107

158

XCLKI

160

XCLKO

C238

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15

KSO17
KSI0

KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

INVT_PWM
BEEP#

PWR_SUSP_LED#

ACOFF
USB_EN#
EC_ON
EC_LID_OUT#
EC_MUTE

ON/OFF
KILL_SW#

PM_SLP_S3#
PM_SLP_S5#

PME#

BATT_TEMPA
BATT_AOVP

AD_BID0

DAC_BRIG
BT_PWR
IREF
EN_DFAN1#

AUD_SUDMUT_P3#
PWR_LED#

WL_LED
HDD_LED#
BATT_LOW_LED#
BATT_CHGI_LED#

Motion
F_FALL

FAN_SPEED1
1394_PHYRST_S3P
1394_DILSON_S3P

EC_THERM#

SHDD_LED#

E51_TXD

1

2

+LDO3_EC

1 2

1

2

R309

SKU_ID

CRY2
CRY1

2

R320
0_0402_5%

C243
1U_0603_10V4Z

1 2

0_0402_5%@

R329 0_0402_5%

1 2

1 2

R242 0_0402_5%

2

KSI[0..7]
KSO[0..15]

KSO17
EC_PLAYBTN#

EC_STOPBTN#
EC_FRDBTN#
EC_REVBTN#

INVT_PWM
BEEP

PWR_SUSP_LED#

ACOFF
USB_EN#
EC_ON
EC_LID_OUT#
EC_MUTE

ON/OFF

KILL_SW#
PM_SLP_S3#
PM_SLP_S5#

CIR_IN

BATT_AOVP

X_SENSOR

Y_SENSOR

Z_SENSOR

DAC_BRIG
BT_PWR
IREF
EN_DFAN1

PWROK

G_BEEP
Docking_Ctrl
AUD_SUDMUT_P3#

PWR_LED#
WL_LED
HDD_LED#
BATT_LOW_LED#
BATT_CHGI_LED#

VGATE

MOTION
F_FALL

1394_PHYRST_S3P

1394_DILSON_S3P
EC_THERM#
EC_RSMRST#

SHDD_LED#

ALI/MH#E51_RXD

1

+LDO3+LDO3_EC

@

J3

2

112

JUMP_43X118
J2

2

112

JUMP_43X118

KSI[0..7]

KSO[0..15]

Analog Board ID definition,
Please see page 3.

Ra

Rb

+3VALW

R247
10K_0402_5%

1 2

D10

2 1

RB751V_SOD323

PCIE_WAKE#

C178 0.01U_0402_16V7K

FAN_SPEED1

Title

Size Document Number Rev

Date: Sheet

ECAGND

12

1 2

100K_0402_5%

R191

1 2

C186 0.22U_0402_10V4Z

ALI/MH#

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3011

401395



, 01, 2005



EC_CIR@

+3VALW

For EC Tools

JP12

1

1

2

2

3

3

4

4

ACES_85205-0400@

+3VALW

R162
100K_0402_5%

1 2

R169
33K_0402_1%

1 2

ACIN

BATT_TEMPA

ADP_I

CRY1

1 2

1

C248

1

IN

2

10P_0402_50V8J

2

32.768KHZ_12.5P_1TJS125BJ2A251

1

E51_RXD
E51_TXD

AD_BID0

1

C184

0.1U_0402_16V4Z

2

R319
20M_0603_5%@

4

X1

OUT

NC3NC

of

25 48

CRY2

+5VALW

1

C247

2

10P_0402_50V8J

A

5

Tekoa 82573E -> IAMT support only (WoL Support)
Vidalia 82573L -> No management
82562GZ -> 10/100 support

PCIE_TXP1

D D

When support S5 WOL
this pin connect to EC
to be a wake up even

C C

Connect to GPIO pin for SPI protect
Pull high -> NVM protect
Pull low -> Non protect

B B

When use 82573G/L R748,R749,R754, R750 = 49.9ohm
When use 82562GZ R748,R749,R754, R750 = 54.9ohm
and C603, C604, non-stuff

A A

PCIE_TXN1
PCIE_RXP1

PCIE_RXN1

CLK_PCIE_LAN
CLK_PCIE_LAN#

Only stuff for 82562 bias

PCIE_WAKE#

LAN_MDI0P
LAN_MDI0N
LAN_MDI1P

LAN_MDI1N
LAN_MDI2P
LAN_MDI2N

LAN_MDI3P

LAN_MDI3N

R71 649_0603_1%
R540 619_0402_1%

NVM_PORT

12

12

82573@

82573@

49.9_0402_1%

R535

R534

1

C489

2

82573@

0.1U_0402_16V4Z

12

R64
1K_0402_5%

Install to use SPI
Flash (Tekoa only)

Stuff for 82573G
No-stuff for 82573L

5

1 2
1 2

Pull high support D3
cold power state

+3VLAN

12

82573@

49.9_0402_1%

R533

49.9_0402_1%

C4470.1U_0402_16V7K 82573@

12

C4480.1U_0402_16V7K 82573@

12

T3PAD~D
T2PAD~D

82562@

82562@

LAN_SPI_MOSI
LAN_SPI_MOSO
LAN_SPI_CE#
LAN_SPI_CLK

Pull down
when with docking
(Control PHY strength)

T27PAD~D

T4PAD~D
T26PAD~D
T24PAD~D
T23PAD~D

R65 3.3K_0402_5%

1 2

R66 100_0402_5%@

1 2

12

R63
10K_0402_5%@

12

Non stuff when use 82562GZ

12

12

R531

49.9_0402_1%82573@

1

C487

2

NVM_SHRDNVM_TYPE

12

R491

@

1K_0402_5%

Install when sharing
SPI Flash with the ICH7M

1

2

12

82573@

R532

49.9_0402_1%

C488

82573@

0.1U_0402_16V4Z

Use dedicate SPI flash only

SPI_MOSI
SPI_MOSO
SPI_CE#
SPI_CLK

LAN1_XO
LAN1_XI

NVM_TYPE
NVM_PORT

NVM_SHRD

R500

3.3K_0402_5%

R529

R530

49.9_0402_1%82573@

82573@

0.1U_0402_16V4Z

49.9_0402_1%82573@

4

F2

PE_R0p-NC

F1

PE_R0n-NC

D1

PE_T0p-NC

C1

PE_T0n-NC

G1

PE_CLKp-NC

G2

PE_CLKn-NC

L3

THERMp-NC

L2

THERMn-NC

B12

PHY_TESTp-TOUT

B13

PHY_TESTn-RBIAS100

B14

PHY_TSTPT-RBIAS10

C7

SDP[3]-NC

C8

SDP[2]-NC

B8

SDP[1]-NC

A8

SDP[0]-NC

A9

NVM_SI-NC

B9

NVM_SO-NC

B10

NVM_CE#-NC

C9

NVM_SK-NC

K14

XTAL1-XTAL1

J14

XTAL2-XTAL2

C6

AUX_PWR-NC

P10

PE_WAKE#-NC

A6

NVM_TYPE-NC

A5

NVM_PROT-NC

B4

NVM_REQ-NC

D3

NVM_SHARED#-NC

C3

DOCK_IND-NC

H1

TEST0-NC

H2

TEST1-NC

H3

TEST2-NC

J1

TEST3-NC

J2

TEST4-NC

J3

TEST5-NC

K1

TEST6-NC

L1

TEST7-NC

M1

TEST8-NC

M3

TEST9-NC

N2

TEST10-NC

P1

TEST11-NC

Close to IC 82573

82573L@

12

12

R528

49.9_0402_1%82573@

1

C486

2

82573@

0.1U_0402_16V4Z

4

3

*ICH7 SMBALRT# signal reserve*
*a 0ohm resistor connect to S0 power*

Must pull high to S0 power

U41A

SMB_ALRT#-NC

SMB_DATA-NC

SMB_CLK-NC

MDIOp-TDP
MDIOn-TDN

MDI1p-RDP

MDI1n-RDN

MDI2p-NC
MDI2n-NC
MDI3p-NC
MDI3n-NC

LED0#-SPEED_LED

LED1#-ACT_LED

LED2#-LILED

NC-JRXD[2]
NC-JRXD[1]
NC-JRXD[0]

NC-JRST_SYNC

CLK_VIEW-JTXD[2]

NC-JXD[1]
NC-JXD[0]

NC-JCLK

LAN_PWR_GOOD-NC

PE_RST#-NC

ALT_CLK125-NC

NC-NC1
NC-NC2
NC-NC3
NC-NC4
NC-NC5
NC-NC6
NC-NC7
NC-NC8

TEST16-NC
TEST15-NC
TEST14-NC
TEST13-NC
TEST12-NC

82573E_FBGA196

22P_0402_50V8J

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

for system power good

R537 3.3K_0603_5%

N11

ICH_SMBDATA

M11

ICH_SMBCLK

P11

LAN_MDI0P

C13

LAN_MDI0N

C14

LAN_MDI1P

E13

LAN_MDI1N

E14

LAN_MDI2P

F13

LAN_MDI2N

F14

LAN_MDI3P

H13

LAN_MDI3N

H14

LAN_LINK#

B11

LAN_ACTIVITY#

C11
A12

R523 0_0402_5% 82562@

M12

R543 0_0402_5% 82562@

N13

R524 0_0402_5% 82562@

P13

R544 0_0402_5% 82562@

M13

R527 0_0402_5% 82562@

L14

R545 0_0402_5% 82562@

L13

R526 0_0402_5% 82562@

M14

R525 0_0402_5% 82562@

N14

P5
P7

TP_ALT_CLK125

N10

M9
N9
N7
L8
P14
J13
M5
D11

A14
E3

LAN_CLKREQ#

P9
M8
N3

for PCIE clock request

25MHZ_20PF_1BG25000CK1A

1

C496

2

1 2

1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2

R542 0_0402_5%

1 2

R541 0_0402_5%@

1 2

Connect to colck gen

Y3

2005/06/10

3

ICH_SMBDATA
ICH_SMBCLK

PLT_RST#

T25 PAD~D

LAN_CLKREQ#

LAN1_XILAN1_XO

12

+3VS

LCI_TXD2
LCI_TXD1
LCI_TXD0

LCI_RSTSYNC

LCI_RXD2
LCI_RXD1
LCI_RXD0
LCI_CLK

EC_RSMRST#

PCI_RST#

1

C499
22P_0402_50V8J

2

Compal Secret Data

Deciphered Date

LCI_TXD2
LCI_TXD1
LCI_TXD0

LCI_RSTSYNC

LCI_RXD2
LCI_RXD1
LCI_RXD0
LCI_CLK

+LAN_AVDD25

82573@

LAN_MDI0P
LAN_MDI0N

LAN_MDI2P
LAN_MDI2N

LAN_MDI3P
LAN_MDI3N

LAN_MDI1P
LAN_MDI1N

R36

2

+3VLAN

1 2

0_0402_5%

C19 0.1U_0402_16V4Z

1

2

R425 200_0402_5%
R426 200_0402_5%

LAN_ACTIVITY#

RJ45_MDI3­RJ45_MDI3+
RJ45_MDI1­RJ45_MDI2­RJ45_MDI2+
RJ45_MDI1+
RJ45_MDI0­RJ45_MDI0+
LAN_LINK#

RJ45_GND

Must connect to RSMRST#
(S5 power)

R37

82573@

1 2

0_0402_5%

C21 0.1U_0402_16V4Z 82573@

C20 0.1U_0402_16V4Z 82573@

C22 0.1U_0402_16V4Z

1

1

1

2

2

2

2006/06/01

2

1

12
12

LAN_ACTIVITY#

RJ45_MDI3­RJ45_MDI3+
RJ45_MDI1­RJ45_MDI2­RJ45_MDI2+
RJ45_MDI1+
RJ45_MDI0­RJ45_MDI0+

LAN_LINK#

JP13

12

T=10mil

T=10mil

RJ45_GND LANGND

C354
1000P_1206_2KV7K

Amber LED+

11

Amber LED-

8

PR4-

7

PR4+

6

PR2-

5

PR3-

4

PR3+

3

PR2+

2

PR1-

1

PR1+

10

Green LED-

9

Green LED+

TYCO_3-440470-4

1 2

***

SHLD2
SHLD1

SHLD2
SHLD1

1

2

0.1U_0402_16V4Z

1

C348

2

16
15

Chassis ground

14
13

C349

4.7U_0805_10V4Z

GST5009 for GIGA LAN
TST1284B for 10/100 LAN

T1

1

TCT1

2

TD1+

3

TD1-

4

TCT2

5

TD2+
TD2-6MX2-

7

TCT3

8

TD3+

9

TD3-

10

TCT4

11

TD4+

12

TD4-

0.5u_GST5009

82573@

Title

SCHEMATIC, M/B LA-3011

Size Document Number Rev

Custom

Date: Sheet

@, 01, 2005

24

MCT1

23

MX1+

22

MX1-

21

MCT2

20

MX2+

19
18

MCT3

17

MX3+

16

MX3-

15

MCT4

14

MX4+

13

MX4-

R11

R10

R12

R13

12

75_0402_1%

12

12

75_0402_1%

75_0402_1%

12

75_0402_1%

RJ45_GND

Compal Electronics, Inc.

401395



1

26 48

RJ45_MDI0+
RJ45_MDI0-

RJ45_MDI2+
RJ45_MDI2-

RJ45_MDI3+
RJ45_MDI3-

RJ45_MDI1+
RJ45_MDI1-

of

A

1

C445

2

0.1U_0402_16V4Z

5

1

C459

2

0.1U_0402_16V4Z

1

C469

2

0.1U_0402_16V4Z

+LAN_AVDD25

1

2

0.1U_0402_16V4Z

1

C436

2

0.1U_0402_16V4Z

1

C442

2

0.1U_0402_16V4Z

C432

0.1U_0402_16V4Z

+3VLAN

1

1

C446

2

D D

C458

2

0.1U_0402_16V4Z

*For 82562GZ stuff 1Kbits EEPROM at ICH7*

Only dedicate SPI support

SPI_CE#
SPI_MOSO

R489

47_0402_5%

82573G@

LAN_SPI_CE#
LAN_SPI_CLK
LAN_SPI_MOSI

C C

LAN_SPI_MOSO

+3VLAN

12

R486

10K_0402_5%

SPI_CE#
SPI_CLK
SPI_MOSI
SPI_MOSO

U39

82573G@

1

CE#

2

SO

3

WP#

4

VSS

82573G@

Flash stuff for 82573E

+3VLAN +3VLAN

8

VDD

7

HOLD#

6

SCK

5

SI

SST25LF080A_SO8

U40

1

CS

VCC

2

SK

3
4

NC

DI

NC

DO

GND

AT93C46-10SI-2.7_SO8

82573L@

EEPROM stuff for 82573L

1

C451

2

0.1U_0402_16V4Z

82573G@

47_0402_5%
R497
R496

47_0402_5%

82573G@

+3VLAN

8
7
6
5

10K_0402_5%@

For 82562GZ LAN disable function

Only 82562GZ mode0 stuff
If use mode1,2 no-stuff and
only connect LAN_DISABLE#
signal to Ball L7

R551

4.7K_0402_5%

(Connect to GPIO)

LAN_DISABLE#

B B

1.2V power supply

R43

4.7K_0402_5%

LAN_CTRL12

A A

LAN_DISABLE#

+3VLAN

12

1

Q34

BCP69_SOT223

C50

4.7U_0805_10V4Z

10U_0805_10V4Z

5

12

3

2

1

2

+3VLAN

+3VLAN

2N7002_SOT23@

R477

1_2010_5%

4

12

12

Q36

13

2

G

4.7U_0805_10V4Z

1

2

1/2W Resistor

40mil

12

R476
1_2010_5%

1

C426

2

R555
470_0402_5%

@

D

S

1

C421

2

22U_0805_6.3V6M

0.1U_0402_16V4Z

1

2

200_0402_5%@

R547

1 2

100_0402_5%

@

R558

1 2

100_0402_5%

@

R539

1 2

100_0402_5%

@

R553

1 2

100_0402_5%

@

200_0402_5%

82562@

22U_0805_6.3V6M

1

C422

C423

2

0.1U_0402_16V4Z

1

C428

C429

2

0.1U_0402_16V4Z

R522

R536

1

2

+LAN_VDD12

12

R516

+3VLAN

C420

1

C443

2

0.1U_0402_16V4Z

R501

10K_0402_5%

82573G@

12

200_0402_5%@

12

R556

12

R559

200_0402_5%

82562@

4

+LAN_VDD12

1

1

C437

2

2

0.1U_0402_16V4Z

SPI_CLK
SPI_MOSI

200_0402_5%

82562@

12

12

R554

R552

200_0402_5%

82562@

12

12

R548

R546

200_0402_5%@

EC_RSMRST#

For 82562GZ LAN_RST# signal must
not be de-asserted sooner than 10ms
after the Resume power supply reaches
its nominal voltage.

1

1

C433

12

12

200_0402_5%@

C402

2

0.1U_0402_16V4Z

Size:
IAMT support:
At last 4Mbits SPI flash
ASF2.0 Support:
64Kbits EEPROM or SPI flash
No magagement:
1Kbits EEPROM

Strapping resistor for 82562GZ
Ehanced Mode configuration
Populate according table

TESTEN
ISOL_TCK
ISOL_TI
ISOL_EXEC

LAN_DISABLE#

C407

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

J9

2

+LDO3

JUMP_43X118
J1

2

JUMP_43X118

@

(Default Mode 1)

+3VLAN

5

U42

1

P

B

2

A

G

TC7SH08FU_SSOP5

3

82562@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

2

Y

3

1

1

1

C408

C413

2

0.1U_0402_16V4Z

112

112

82562GZ mode0 LAN_DISABLE# pin
is used as ADV10 (auto-negotiation

4

C414

0.1U_0402_16V4Z

R538

R521

82573@

C403

2

0.1U_0402_16V4Z

+3VLAN

12

R61

10K_0402_5%

T10 PAD~D

T8 PAD~D
T11 PAD~D
T9 PAD~D
T12 PAD~D

4.99K_0402_1%

1 2

1 2

3.3K_0402_5%

2

0.1U_0402_16V4Z

+3VLAN+3VALW

80 mil

82573@

LAN_DISABLE#

advertise 10M only)

Connect to ICH7 LAN reset pin

LAN_RST#

82562GZ Hardware configuration table (Default Mode 1)
Mode

TESTEN

Mode0
Mode1
Test Mode
Isolate
Power down

2005/06/10

3

E10

F11

F10
G11
G10
H10

C10

G14

C12
D13
N12

M6

K12

L11

ISOL_TI
ISOL_TCK
ISOL_EXEC
TESTEN

LAN_DISABLE#

0
0
1
0
1

D12
D14
D10
A13

0
0
0
1
1

Compal Secret Data

Deciphered Date

A1

VSS1-NC

C2

VSS2-NC

D2

VSS3-NC

G4

VSS4-NC

D4

VSS5-NC

D5

VSS6-NC

B3

VSS7-NC

E4

VSS8-VSS

E5

VSS9-VSS
VSS10-VSS
VSS11-VSS
VSS12-VSS
VSS13-VSS
VSS14-VSS
VSS15-VSS

F5

VSS16-VSS

F4

VSS17-VSS

VSS-VSS1

D6

VSS-VSS2

D7

VSS-VSS3

D8

VSS-VSS4

E6

VSS-VSS5

E7

VSS-VSS6

E8

VSS-VSS7

E9

VSS-VSS8

F6

VSS-VSS9

F7

VSS-VSS10

F8

VSS-VSS11

F9

VSS-VSS12

G7

VSS-VSS13

G8

VSS-VSS14

G9

VSS-VSS15

H9

VSS-VSS16
VSS-VSS17

K2

VSS-VSS18

E2

VSS-VSS19

N1

VSS-VSS20

P8

VSS1-VSS
VSS2-VSS
VSS3-VSS
VSS4-VSS

B7

NC1-VSS
NC2-VSS

L6

NC3-VSS
NC4-VSS
NC5-VSS

B5

EN2.5REG-NC

A4

CTRL_2.5-NC

N4

JTAG_TMS-NC

N5

JTAG_TCK-NC

P4

JTAG_TDI-NC

P6

JTAG_TDO-NC

PHY_REF-ISOL_TI
NC-ISOL_TCK
NC-ISOL_TXE
TEST_EN-TEST_EN

L7

DEVICE_OFF#-AVD10

ISOL_TI

1
1
1
1

2

VCC3.3_REG2.5-NC5
VCC3.3_REG2.5-NC6

VCC2.5_PCIE-VCC3.3-1
VCC2.5_PCIE-VCC3.3-2
VCC2.5_PCIE-VCC3.3-3

VCC2.5_XTAL-VCC3.3-4

VCC2.5_PHY-VCC3.3

VCC3.3_REG2.5-VCC3.3

82573E_FBGA196

82573L@

ISOL_EXEC

0
1
0
1
1

2006/06/01

2

U41B

NC-VCC3.3-1
NC-VCC3.3-2
NC-VCC3.3-3
NC-VCC3.3-4

VCC1.2-NC1
VCC1.2-NC2
VCC1.2-NC3
VCC1.2-NC4
VCC1.2-NC5
VCC1.2-NC6

VCC1.2-VCC3.3-1
VCC1.2-VCC3.3-2
VCC1.2-VCC3.3-3
VCC1.2-VCC3.3-4
VCC1.2-VCC3.3-5
VCC1.2-VCC3.3-6
VCC1.2-VCC3.3-7
VCC1.2-VCC3.3-8

VCC1.2-VCC3.3-9
VCC1.2-VCC3.3-10
VCC1.2-VCC3.3-11
VCC1.2-VCC3.3-12
VCC1.2-VCC3.3-13
VCC1.2-VCC3.3-14
VCC1.2-VCC3.3-15
VCC1.2-VCC3.3-16
VCC1.2-VCC3.3-17
VCC1.2-VCC3.3-18
VCC1.2-VCC3.3-19
VCC1.2-VCC3.3-20
VCC1.2-VCC3.3-21
VCC1.2-VCC3.3-22
VCC1.2-VCC3.3-23
VCC1.2-VCC3.3-24

VCC3.3-NC1
VCC3.3-NC2
VCC3.3-NC3
VCC3.3-NC4

VCC2.5_IO-NC1
VCC2.5_IO-NC2
VCC2.5_IO-NC3
VCC2.5_IO-NC4

VCC2.5_IO-NC5
VCC2.5_PHY-NC6
VCC2.5_PHY-NC7

VCC3.3-VCC3.3-1
VCC3.3-VCC3.3-2
VCC3.3-VCC3.3-3
VCC3.3-VCC3.3-4
VCC3.3-VCC3.3-5

CTRL_1.2-NC

2.5V_OUT-NC1

2.5V_OUT-NC2

Mode

XOR tree

Mode2
Mode3

Mode4
Reserved
Testing

1

+LAN_VDD12 +3VLAN

C440

10U_0805_6.3V4Z

12

R485
0_0603_5%

82573@

C471

10U_0805_6.3VM

ISOL_TI

1

12

R487
0_0603_5%

82573@

1

C444

2

1

2

0
1
0
0
1

E1
L4
E11
E12

F12
H12
G12
C5
C4
A10

G6
H6
H7
J6
J7
J8
K4
K5
K7
K8
L5
H8
J9
J10
J11
K9
K10
L9
L10
K11
K6
H11
K3
G13

M10
J4
F3
D9
A2
M2

J5
G5
H5
K13
H4
N7
M4
G3
B6
J12
L12
A11

P2
N6
A7
P12
N8
A3

P3
B2

B1

+LAN_AVDD25

LAN_CTRL12

Use internal regulator
please take care thermal

TESTENISOL_TCK

1

1

1

C439

2

2

10U_0805_6.3V4Z

+3VLAN

1

+

2

+LAN_AVDD25

ISOL_TCK

00
10
1
1
1
1

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3011

Custom

@, 01, 2005



0

1

1

1

401395

12

0.1U_0402_16V4Z

+3VLAN+LAN_AVDD25

12

R492
0_0603_5%

82562@

+3VLAN

1

C479

2

0.1U_0402_16V4Z

ISOL_EXEC

00
1
1
0
1
0

27 48

of

R488
0_0603_5%

82562@

C455

0.1U_0402_16V4Z

A

A

+3VS +1.5VS +3VALW

B

C

D

E

1

1 1

C211

0.01U_0402_16V7K

0.1U_0402_16V4Z

2

C271

1

4.7U_0805_10V4Z

2

C278

1

0.01U_0402_16V7K

2

Mini-Express Card

JP28

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

53

GND1

FOX_AS0B226-S40N-7F~D

1 2
1 2

PCIE_WAKE#

MINI_CLKREQ#
CLK_PCIE_MCARD#

CLK_PCIE_MCARD

PCIE_C_RXN2PCIE_RXN2
PCIE_C_RXP2

PCIE_TXN2
PCIE_TXP2

PCIE_WAKE#
WLAN_BT_DATA
WLAN_BT_CLK

MINI_CLKREQ#

CLK_PCIE_MCARD#

CLK_PCIE_MCARD

2 2

PCIE_RXN2
PCIE_RXP2

PCIE_RXP2

R305 0_0402_5%

R300 0_0402_5%

PCIE_TXP2

C215

GND2

***

2
4
6

8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

1

0.1U_0402_16V4Z

2

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

54

1

C226

4.7U_0805_10V4Z

2

XMIT_OFF#

PLT_RST#

+3VALW

ICH_SMBCLK
ICH_SMBDATAPCIE_TXN2

R283 0_0402_5%
R278 0_0402_5%

1

C261

12
12

2

0.1U_0402_16V4Z

USB20_N1
USB20_P1

C234

+1.5VS +3VS

1

2

X_SENSOR
Y_SENSOR
Z_SENSOR

0.1U_0402_16V4Z

+3VS +3VS

MOTION
F_FALL

1

1

C175

1

C174

2

2

2

2200P_0402_50V7K

2200P_0402_50V7K

C177

0.01U_0402_16V7K

C169

U10

1

GND

2

VDD

3

MOTION

4

FF

5

Output X

6

Output Y
Output Z7RESET

KXP84-0200_DFN14

1

C164
3300P_0402_50V7K

2

1

1

C176

2

2

0.1U_0402_16V4Z

IO VDD

SCL/SCLK

SDA/SDO

ADDR0/SDI

+3VS

10U_0805_6.3V6M

1

C170

2

14

NC

13
12
11
10
9

CS#

8

EC_SMB_CK2
EC_SMB_DA2

R134 10K_0402_5%

1 2

1 2

C162

12

8.2K_0402_5%
R128

10U_0805_10V4Z

+3VS

Kill SWITCH

3 3

D18
DAN217_SC59

+3VALW

3

2

+3VALW

+3VALW

C235 0.1U_0402_16V4Z

1 2

5
WL_OFF#
KILL_SW#

4 4

A

WL_OFF#
KILL_SW#

1

B

2

A

U20

P

4

Y

G

TC7SH08FU_SSOP5

3

B

RB751V_SOD323

TIP

D13

XMIT_OFF#

21

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2005/06/01 2006/06/01

3

Compal Secret Data

Deciphered Date

1

11223

SW41BS003-1211L_3P

R402
100K_0402_5%

1 2

KILL_SW#

D

KILL_SW#

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3011

 

401395

05

28 48, 01, 20

E

of

A

A

BEEP

1 1

PCM_SPK

SB_SPKR

1U_0603_10V4Z

C330

1 2

C333

1U_0603_10V4Z

C335

1U_0603_10V4Z

B

1 2

1 2

R401

1 2

560_0402_5%

R403

1 2

560_0402_5%

R406

1 2

560_0402_5%

R353

10K_0402_5%

2

B

12

+VDDA

12

R404
10K_0402_5%

C337 1U_0603_10V4Z

12

R415
10K_0402_5%

1

C

Q25

2SC2411K_SC59

E

3

D16

RB751V_SOD323

2 1

C

1 2

C341

1 2

1U_0603_10V4Z

1 2

R407

2.4K_0402_5%

MONO_IN

D

E

F

G

H

28.7K for Module Design (VDDA = 4.702)

(output = 250 mA)

40mil

R397
30K_0402_1%

1

2

1

1

2

2

1 2
12

R396
10K_0402_1%

LINEL

LINER

C287

1U_0402_6.3V4ZWOD@

+VDDA

4.85V

1

C324
10U_1206_16V4Z

2

LINE_IN_L

LINE_IN_R

+5VALW

1

C323

10U_1206_16V4Z

2

SYSON

60mil

1

C325

2

0.1U_0402_16V4Z

R359 6.8K_0402_5%@
R360 6.8K_0402_5%@
R358

R361

12
12
12

6.8K_0402_5%WD@

12

6.8K_0402_5%WD@

U33

4

VIN

2

SENSE or ADJ

DELAY
ERROR7CNOISE

8

SD

SI9182DH-AD_MSOP8

1 2

1 2

VOUT

GND

C294

C295

C286

5
6
1
3

1U_0402_6.3V4ZWD@

1U_0402_6.3V4ZWD@

1U_0402_6.3V4ZWOD@

C332

0.1U_0402_16V4Z

HD Audio Codec

2 2

L4

+VDDA

INT_CD_L

INT_CD_R

3 3

4 4

CD_AGND

R392 20K_0402_5%
R388 6.8K_0402_5%
R390 6.8K_0402_5%
R394 20K_0402_5%

R393 20K_0402_5%

12

1 2

R658 0_0603_5%

1 2

R400 0_0603_5%

1 2

R366 0_0603_5%

R398
0_0402_5%@

12
12
12
12

12

R389

6.8K_0402_5%

12

1 2

FBM-L11-160808-800LMT_0603

10U_1206_16V4Z

CD_L_R
CD_R_R CD_R_RC
CD_AGND_R

MIC1_L
MIC1_R

MIC1_L

R395

0_0402_5%@

1 2

0.1U_0402_16V4Z

1

C331

C305

2

1 2

C316 1U_0603_10V4Z

1 2

C318 1U_0603_10V4Z

1 2

C317 1U_0603_10V4Z

1 2

C604 1U_0603_10V4Z

1 2

C603 1U_0603_10V4Z

ICH_RST_AUDIO#
ICH_SYNC_AUDIO

ICH_SDOUT_AUDIO

GND GNDA

40mil

1

1

C329

2

2

0.1U_0402_16V4Z

LINEL
LINER

CD_L_RC

CD_AGND_RC
MIC1_C_L
MIC1_C_RMIC1_R

MONO_IN

DGND AGND

+AVDD_AC97

U48

AVDD125AVDD2

14

LINE2_L

15

LINE2_R

16

MIC2_L

17

MIC2_R

23

LINE1_L

24

LINE1_R

18

CD_L

20

CD_R

19

CD_GND

21

MIC1_L

22

MIC1_R

13

SENSE A

12

PC_BEEP

11

RESET#

10

SYNC

5

SDATA_OUT

45

SIDE-SURR-L

46

SIDE-SURR-R

48

SPDIFO

4

DVSS1

7

DVSS2

ALC861-GR_LQFP48

38

20mil

DVDD11DVDD2

FRONT-OUT-L

FRONT-OUT-R

SURR_OUT_L

SURR_OUT_R

BIT_CLK

SDATA_IN

MIC2_VREFO

MIC1_VREFO_L

VREF

MIC1_VREFO_R

LINE2_VREFO

SENSE B

CEN-OUT

LFE-OUT

JDREF
AVSS1
AVSS2

0.1U_0402_16V4Z

1

C322

2

9

NC
NC
NC
NC
NC
NC

0.1U_0402_16V4Z

AMP_LEFT

35

AMP_RIGHT

36

39
41

6

R387 33_0402_5%

8
2

33
47
37
3
29

30
28

10mil

27
32

10mil

31
34

43
44

40
26
42

1

C328

2

1 2

PAD

MIC1_VREFO_L

MIC1_VREFO_R

12

1

C303
10U_1206_16V4Z

2

1000P_0402_50V7K

@

HP_OUT_L
HP_OUT_R

T5

ACZ_VREF

R399
20K_0402_1%@

+3VS

1

C327

2

1 2

C326 27P_0402_50V8J

ICH_BITCLK_AUDIO

ICH_AC_SDIN0

10mil

1

C319
10U_0805_10V4Z

2

1

C617
1000P_0402_50V7K

@

2

AMP_LEFT
AMP_RIGHT

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

C

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

2005/05/12 2006/06/01

Compal Secret Data

Deciphered Date

E

Title

Size Document Number Rev

B

F

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3011



G

401395

01, 2005



29 48,

A

of

H

A

1 1

0.1U_0402_16V4Z

R362 100K_0402_5%

SPKL+

AMP_LEFT
AMP_RIGHT

2 2

SPKR+

0.1U_0402_16V4Z

1 2

1 2

C608 1U_0402_6.3V4Z

1 2

C616 1U_0402_6.3V4Z

2

2

C615

1

1

C607

0.1U_0402_16V4Z

VOL_AMP

LEFT_2
RIGHT_2

1

C609

2

0.1U_0402_16V4Z

Volumn Control VR

Reserve for noise.

0.1U_0402_16V4Z@

VOL_AMP

R411

100K_0402_5%

2

G

+5VS

1 2
13

D

Q27
2N7002_SOT23

S

3 3

NBA_PLUG

2

G

C336

R408

1 2

1.5K_0603_1%

13

D

S

1

2

Q28
2N7002_SOT23

C288

+5VS

2

B

+5VS

W=40mil

1

1

C292

4.7U_0805_10V4Z

2

2

U47

7

PVDD

18

PVDD

19

VDD

2

HP/LINE#

3

VOLUME

4

LOUT+

21

ROUT+

5

LLINEIN

23

RLINEIN

6

LHPIN

20

RHPIN

17

CLK

TPA0232PWP_TSSOP24

1

C614

0.047U_0402_16V7K

2

R410

2.61K_0603_1%

1 2

1

4

0.01W_10KC_EVUTWZB19C14

VR1

5

3

R409

5.76K_0603_1%

1 2

SHUTDOWN#

SE/BTL#

PC-BEEP

BYPASS

LOUT-

ROUT-

GND
GND
GND
GND

C

+5VS

12

R660
100K_0402_5%

SHUTDOWN#

22

NBA_PLUG

15
14

BYPASS

11
9
16
10

LIN

8

RIN

1
12
13
24

C298

1U_0402_6.3V4Z

Q26

13

D

2N7002_SOT23

2

G

S

R659 100K_0402_5%

1 2

1 2

C613 1U_0402_6.3V4Z

2

2

C296

1

1

1U_0402_6.3V4Z

SPKL­SPKR-

EC_MUTE

2

C297
1U_0402_6.3V4Z

1

+5VS

G_BEEP

SPKL+
SPKL­SPKR+
SPKR-

20mil

D

R19 0_0603_5%

1 2

R24 0_0603_5%

1 2

R31 0_0603_5%

1 2

R32 0_0603_5%

1 2

Speaker Conn.

E

PSOT24C_SOT23@

1

1

D3

3

D1

PSOT24C_SOT23@

2

3

2

SPK_L+
SPK_L­SPK_R+
SPK_R-

JP2

4
3
2
1

ACES_85204-0400

Headphone JACK 1

JP31

5
4
3

6
2
1

FOX_JA6033L-5S1-TR

JP32

5
4
3

6
2
1

FOX_JA6033L-5S1-TR

45@

45@

MIC2

WM-64PCY_2P

MIC1

WM-64PCY_2P

Int MIC Conn.

1
2

1
2

15mil
15mil

10mil

SPKR+
SPKL+

+

1 2

C321 150U_D2_6.3VM

+

1 2

C320 150U_D2_6.3VM

INT_MIC_R

INT_MIC_L

HPOUT1_R_2 HPOUT1_R_3
HPOUT1_L_2 HPOUT1_L_3

MIC1_R
MIC1_L

+5VS

1 2

R421 0_0603_5%

1 2

R420 0_0603_5%

MIC1_R MIC1_R_1

1 2

MIC1_L MIC1_L_1

1 2

220P_0402_50V7K

R405 100K_0402_5%

1 2

L6 FBM-11-160808-700T_0603

1 2

L5 FBM-11-160808-700T_0603

10mil

R413

4.7K_0402_5%

L8

FBM-11-160808-700T_0603

L7

FBM-11-160808-700T_0603

C338

330P_0402_50V7K

MIC1_VREFO_L

10mil

12

1

220P_0402_50V7K

2

HPOUT1_R_4
HPOUT1_L_4

C340

MIC1_VREFO_R

12

R414

4.7K_0402_5%

1

C339

2

NBA_PLUG

12

C334

330P_0402_50V7K

BTL MODE
R293//R294=1.19K
Vmax=0.431V , GAINmax=14dB
Vmin=4.05V, G AINmin=-80dB

SE MODE
Vmax=1.53V , GAINmax=-6db
Vmin=4.28V, G AINmin=-80db

4 4

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/25 2006/06/01

C

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

D

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3011

 

401395

30 48, 01, 2005

E

A

of

5

LINEIL#

LINEIL

D D

LINEIR#

LINEIR

1 2

C256 1U_0402_6.3V4ZWD@

1 2

C277

WD@

1 2

C255

WD@

1 2

C276

WD@

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

R627

1 2

R647

1 2

1K_0402_5%WD@

+DOCK_AUD_VREF

R628 1K_0402_5%WD@

1 2

R648

1 2

+DOCK_AUD_VREF

1K_0402_5%WD@

C264 1000P_0402_50V7KWD@

C285 1000P_0402_50V7KWD@

C262 1000P_0402_50V7KWD@

C284 1000P_0402_50V7KWD@

1K_0402_5%WD@

4

R631 10K_0402_5%WD@

1 2

1

2
1

2

R651 10K_0402_5%WD@

1 2

R652 4.7K_0402_5%WD@

1 2

R632 10K_0402_5%WD@

1 2

1

2
1

2

R654 10K_0402_5%WD@

1 2

R653

1 2

3

R638 4.7K_0402_5%WD@

1 2

+VDDA

4

2

-

3

+

11

R639 4.7K_0402_5%WD@

+VDDA

C263

V+

O

V-

U26A

1 2

1 2

1

LMV824MTX_TSSOP14WD@

1U_0402_6.3V4ZWD@

LINE_IN_L

4

6

-

V+

7

O

5

+

V-

U26B

LMV824MTX_TSSOP14WD@

4.7K_0402_5%WD@

11

LINE_IN_R

+VDDA

2

R375

1 2

100K_0402_5%WD@

100K_0402_5%WD@

R374

1 2

C307

1

2

0.1U_0402_16V4Z

WD@

9

10

+VDDA

4

-

V+

O

+

V-

U26C

LMV824MTX_TSSOP14

11

WD@

8

1

+DOCK_AUD_VREF

+DOCK_AUD_VREF

1

C306

2

1U_0402_6.3V4Z@

R378 22K_0402_5%WD@

1 2

1 2

2

C304

0.1U_0402_16V4Z

1

@

C312 68P_0402_50V8KWD@

+VDDA

4

9

-

V+

O

10

+

V-

U28C

11

8

LMV824MTX_TSSOP14WD@

R339

4.7K_0402_5%

WD@

C C

R379

22K_0402_5%WD@

1 2

HP_OUT_L

1U_0402_6.3V4ZWD@

1 2

C315

+DOCK_AUD_VREF

+VDDA

C267

4

­+

11

WD@

+VDDA

1U_0402_6.3V4Z

V+

O

V-

U28A

LMV824MTX_TSSOP14WD@

2
3

1 2

R342 4.7K_0402_5%

1

12

1 2

WD@

1 2

C268 1U_0402_6.3V4Z

WD@

LINEOL

4

6

-

V+

7

O

+DOCK_AUD_VREF

C258

0.1U_0402_16V4Z

B B

R376

C311

R377
22K_0402_5%WD@

1 2

2

0.1U_0402_16V4Z

1

@

9

10

C302

HP_OUT_R

1U_0402_6.3V4ZWD@

1 2

C314

+DOCK_AUD_VREF

1 2

1 2

+VDDA

4

-

V+

+

V-

11

68P_0402_50V8KWD@

O

U27C

22K_0402_5%WD@

8

LMV824MTX_TSSOP14WD@

R340

4.7K_0402_5%WD@

1 2

R341

WD@

+VDDA

C265 1 U_0402_6.3V4Z

4

2

-

V+

O

3

+

V-

U27A

11

+VDDA

1 2

WD@

1

12

LMV824MTX_TSSOP14WD@

4.7K_0402_5%WD@

5

+

2

V-

11

1

C266 1U_0402_6.3V4Z

U28B

1 2

LMV824MTX_TSSOP14WD@

WD@

1 2

C253 1U_0402_6.3V4Z

WD@

LINEOR

LINEOL#

+VDDA

4

13

-

V+

14

O

12

+

V-

U26D

LMV824MTX_TSSOP14WD@

11

+VDDA

4

13

-

V+

14

O

12

+

V-

U28D

LMV824MTX_TSSOP14WD@

11

+VDDA

4

13

-

V+

14

O

12

+

V-

U27D

LMV824MTX_TSSOP14WD@

11

4

6

-

V+

A A

+DOCK_AUD_VREF

C257

0.1U_0402_16V4Z

@

2

1

5

Security Classification

Issued Date

PROPRIETARY NOTE

5

4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

7

O

+

V-

U27B

11

LMV824MTX_TSSOP14WD@

2005/04/25 2006/06/01

3

1 2

C252 1U_0402_6.3V4Z

WD@

Compal Secret Data

Deciphered Date

LINEOR#

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3011



401395

01, 2005



31 48,

1

A

of

A

B

RTCVREF RTCVREF RTCVREF RTCVREF

C

D

E

1 2

Q39
2N7002_SOT23

RTCVREF

1 2

R185
10K_0402_5%

12

R584
680K_0402_5%

1

2

D9

2 1

RB751V_SOD323

12

12

2

G

RTCVREF

+3VALW

R585
100K_0402_5%

C533 1U_0805_16V7K

13

D

S

1 2

R246
10K_0402_5%

R590

100K_0402_5%

1 1

S4_LID_SW#

S4_LATCH

R204

2 2

10K_0402_5%

1 2

S4_DATA

Docking Parallel Port

+5V_PRN

RB420D_SOT23217@

68_1206_8P4R_5%217@

4 5
3 6
2 7
1 8

RP30

RP31

4 5
3 6
2 7
1 8

68_1206_8P4R_5%217@

D4

2 1

R_LPTSTB#
AFD#/3M#
LPTINIT#
LPTSLCTIN#SLCTIN#

FD0
FD1
FD2
FD3

FD7
FD6
FD5

12

R52

217@

2.2K_0402_5%

1 2

R_LPTSTB#
AFD#/3M#
LPTINIT#
LPTSLCTIN#

FD0
FD1
FD2
FD3

FD7
FD6
FD5
FD4

C51

220P_0402_50V7K217@

B

3 3

LPTSTB#

LPTSTB#
LPTAFD#
INIT#
SLCTIN#

4 4

R53 33_0402_5%

LPTAFD#

R475 33_0402_5%

INIT#

R474 33_0402_5%
R473 33_0402_5%

LPD0
LPD1
LPD2
LPD3

LPD7
LPD6
LPD5
LPD4

A

+5VS

217@

1 2

217@

1 2

217@

1 2

217@

1 2

LPD0
LPD1
LPD2
LPD3

LPD7
LPD6
LPD5
LPD4 FD4

C49 220P_0402_50V7K@

1 2

C48 220P_0402_50V7K@

1 2

C47 220P_0402_50V7K@

1 2

C46 220P_0402_50V7K@

1 2

C409 220P_0402_50V7K@

1 2

C410 220P_0402_50V7K@

1 2

C411 220P_0402_50V7K@

1 2

C412 220P_0402_50V7K@

1 2

C13 220P_0402_50V7K@

1 2

C14 220P_0402_50V7K@

1 2

C15 220P_0402_50V7K@

1 2

C16 220P_0402_50V7K@

1 2

C390 220P_0402_50V7K@

1 2

C393
C391 220P_0402_50V7K@

1 2

C392 220P_0402_50V7K@

1 2

1 2

220P_0402_50V7K@

1 2

R240
10K_0402_5%

C188

1U_0805_16V7K@

12

D33

1N4148_SOT23

C534 0.1U_0402_16V4Z

1 2

5

P

2

C197 1U_0805_16V7K

4

A

Y

G

U44

3

NC7SZ14M5X_SOT23-5

SYSON

1 2

U12

1

CD1#

VCC

2

D1

CD2#

3

CP1

4

SD1#

CP2

5

Q1

SD2#

6

Q1#

7

GND

Q2#

74LCX74MTC_TSSOP14

D_SET_S4

R597
10K_0402_5%

2N7002_SOT23

14
13
12

D2

11
10
09

Q2

08

1 2

2

G

Q40

RTCVREF

C196 0.1U_0402_16V4Z

13

D

S

1 2

13

D

Q19

2

2N7002_SOT23

G

S

13

D

Q18

2

G

2N7002_SOT23

S

Close to Docking

LPTSLCTIN#
LPTINIT#
LPTERR#
AFD#/3M#
LPTACK#
LPTBUSY
LPTPE
LPTSLCT
FD0
FD1
FD2
FD3
FD4
FD5
FD6
FD7

+5V_PRN

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

RP3

2.7K_1206_8P4R_5%217@
RP4

2.7K_1206_8P4R_5%217@
RP1

2.7K_1206_8P4R_5%217@
RP2

2.7K_1206_8P4R_5%217@

LPTSLCT

LPTPE

LPTBUSY
LPTACK#

AFD#/3M#
LPTERR#
LPTINIT#
LPTSLCTIN#

FD0
FD1
FD2
FD3

FD7
FD6
FD5
FD4

Compal Secret Data

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

2005/04/25 2006/06/01

Close to Docking

LPTSLCT
LPTPE
LPTBUSY
LPTACK#

LPTERR#

DTR#1
RTS#1
TXD1

SUSP#

Deciphered Date

ON/OFFBTN#

2

C195

1

0.1U_0402_16V4Z

0.1U_0402_16V4ZWD@

CTS#1
RI#1
RXD1
DCD#1
DSR#1

D

2

3

D7

1

PSOT24C_SOT23

C5

0.1U_0402_16V4ZWD@

C1

ON/OFFBTN#

2

1

2

1

2

1

+3VS

C4

0.1U_0402_16V4ZWD@

26

28

C1+

24

C1-

1

C2+

2

C2-

14

TIN1

13

TIN2

12

TIN3

19

ROUT1

18

ROUT2

17

ROUT3

16

ROUT4

15

ROUT5

20

ROUTB2

23

FORCEON

22

FORCEOFF#

MAX3243CAI_SSOP28WD@

Title

SCHEMATIC, M/B LA-3011

Size Document Number Rev

Date: Sheet

U1

VCC

TOUT1
TOUT2
TOUT3

RIN1
RIN2
RIN3
RIN4
RIN5

INVLD#

GND

27

V+

3

V-

9
10
11
4
5
6
7
8

21
25

12

C2 0.1U_0402_16V4ZWD@

12

C3 0.1U_0402_16V4ZWD@

DTR#
RTS#
TXD
CTS#
RI#
RXD
DCD#
DSR#

Compal Electronics, Inc.

401395

󰛗

E

32 48@, 01, 2005

DTR#
RTS#
TXD
CTS#
RI#
RXD
DCD#
DSR#

of

A

A

B

+3VS

C

D

E

SUPER I/O SMsC LPC47N217

+3VS

1 1

2 2

10K_0402_5%@

15P_0402_50V8J@

3 3

10U_0805_10V4Z@

4 4

10U_1206_16V4ZFIR@

217@

R372 10K_0402_5%

1 2

R354 10K_0402_5%217@

1 2

R364 100K_0402_5%217@

12

SIO_IRQ
IRRX

Agilent IRRX unpop 10K
Vishay IRRX pop 10K

CLK_14M_SIO

R349

C280

1

C343

2

1

C347

2

CLK_PCI_SIO

1 2

R373

1

1 2
1

2

C309

2

+3VS

R424
0_1206_5%

FIR@

1 2

+IR_3VS

(30mil)

1

C618

0.1U_0402_16V4ZFIR@

2

A

SIO_PD#
SIO_SMI#
FIR_DET#

R350 10K_0402_5%@
R347 10K_0402_5%

10_0402_5%@

15P_0402_50V8J@

12

1 2

FIR Module

C342

22U_1206_16V4Z_V1

(30mil, 3via)

L: R POP; FIR Enable
H: R De-POPFIR Disable

FIR_DET#

R363 1K_0402_5%

1 2

+3VS

(60mil)

R417 4.7_1206_5%@

1

2

IRRX IRMODE

SD/MODE: SHUTDOWN MODE, HIGH ACTIVE
MODE: HIGH/LOW SPEED SELECT

R418 4.7_1206_5%

IR1

2

IRED_C

4

RXD

6

VCC

8

GND

TFDU6102-TR3_8PFIR@

FIR@

1 2
1 2

IRED_A

SD/MODE

1

C245

4.7U_0805_10V4Z

2

217@

FIR_DET#

SIO_GPIO11

FIR@

TXD

MODE

B

+IR_ANODE

1
3
5
7

217@

1

C300

0.1U_0402_16V4Z

2

217@

LPC_FRAME#
LPC_DRQ#0

PCI_RST#

SIO_PD#

PM_CLKRUN#

CLK_PCI_SIO

SIRQ

CLK_14M_SIO

+3VS

R356

10K_0402_5%@

Base I/O L-Address

1 2

0 = 02Eh

*

1 = 04Eh

R357

1K_0402_5%

1 2

(60mil)

IRTXOUT

LPC_AD[0..3]

U30

10

LAD0

12

LAD1

13

LAD2

14

LAD3

15

LFRAME#

16

LDRQ#

17

PCI_RESET#

18

LPCPD#

19

CLKRUN#

20

PCI_CLK

21

SER_IRQ

6

IO_PME#

9

CLK14

CLOCK

23

GPIO40

24

GPIO41

25

GPIO42

27

GPIO43

28

GPIO44

29

GPIO45

30

GPIO46

31

GPIO47

32

GPIO10

33

GPIO11/SYSOPT

34

GPIO12/IO_SMI#

35

GPIO13/IRQIN1

36

GPIO14/IRQIN2

40

GPIO23

8

VSS

22

VSS

43

VSS

52

VSS

LPC47N217-JV_STQFP64

217@

LPC I/F

GPIO

POWER

RXD1

TXD1
DSR1#
RTS1#
CTS1#
DTR1#

RI1#

DCD1#

SERIAL I/F

IRRX2

FIR

IRTX2

IRMODE/IRRX3

INIT#

SLCTIN#

PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7

SLCT

BUSY

ACK#

PARALLEL I/F

ERROR#

ALF#

STROBE#

VTR
VCC
VCC
VCC
VCC

RXD1

62

TXD1

63

DSR#1

64

RTS#1

1

CTS#1

2

DTR#1

3

RI#1

4

DCD#1

5

IRRX

37

IRTXOUT

38

IRMODE

39

INIT#

41

SLCTIN#

42

LPD0

44

LPD1

46

LPD2

47

LPD3

48

LPD4

49

LPD5

50

LPD6

51

LPD7

53

LPTSLCT

55

LPTPE

56

PE

LPTBUSY

57

LPTACK#

58

LPTERR#

59

LPTAFD#

60

LPTSTB#

61

7
11
26
45
54

+3VS

PME#

FIR_DET#

LPC_AD[0..3]

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

LPC_FRAME#
LPC_DRQ#0

SIO_RST#
SIO_PD#

PM_CLKRUN#
CLK_PCI_SIO
SERIRQ
PME#

CLK_14M_SIO

SIO_GPIO11
SIO_SMI#
SIO_IRQ

Serial Port
for Debug

+5VS

RXD1
TXD1
DSR#1
RTS#1
CTS#1
DTR#1
RI#1
DCD#1

CIR

U49

TSOP6238-TR_4P

GND
GND
VCC

ROUT

1
2
3
4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

2

2005/04/25 2006/06/01

C

JP5

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

E&T_96212-1011S@

C344

4.7U_0805_10V4ZCIR@
R423 100_0805_5%

1 2

1 2

R422 0_0402_5%

CIR@

Compal Secret Data

CIR_IN

Deciphered Date

+5VALW

10_0402_5%@

18P_0402_50V8K@

RXD1
TXD1
DSR#1
RTS#1
CTS#1
DTR#1
RI#1
DCD#1

IRRX
IRTXOUT
IRMODE

INIT#
SLCTIN#
LPD0
LPD1
LPD2
LPD3
LPD4
LPD5
LPD6
LPD7

LPTSLCT
LPTPE
LPTBUSY
LPTACK#
LPTERR#
LPTAFD#
LPTSTB#

C273

+3VS

0.1U_0402_16V4Z217@

1

2

Port 80 Debug Card Connector

PCI_CBE#0

PCI_AD6
PCI_AD4
PCI_AD2
PCI_AD0
PCI_AD1
PCI_AD3
PCI_AD5
PCI_AD7

PCI_AD8
PCI_CBE#1
PCI_CBE#2
PCI_CBE#3

CLK_PCI_USB20

+5VS

PCI_RST#

PCI_FRAME#

PCI_TRDY#

PCI_AD9

CLK_PCI_USB20_C

12

R570

1

C500

2

Title

SCHEMATIC, M/B LA-3011

Size Document Number Rev

Date: Sheet

D



**

R572 33_0402_5%
R573 33_0402_5%
R574 33_0402_5%
R575 33_0402_5%
R576 33_0402_5%
R577 33_0402_5%
R578 33_0402_5%
R563 33_0402_5%
R564 33_0402_5%
R565 33_0402_5%
R566 33_0402_5%
R567 33_0402_5%
R568 33_0402_5%

R569 33_0402_5%
R100 33_0402_5%

R99 33_0402_5%
R98 33_0402_5%
R97 33_0402_5%

12
12
12
12
12
12
12
12
12
12
12
12
12

CLK_PCI_USB20_C

12
12

12
12
12

20
19
18
17
16
15
14
13
12
11
10

9
8
7
6
5
4
3
2
1

Compal Electronics, Inc.

401395

01, 2005



33 48,

E

JP8

20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

ACES_85201-2005

A

of

A

Docking Conn.

JP17A

1 1

+DC_IN_S1 +DC_IN_S1

DKN_B+ DKN_B+ DKN_B+ DKN_B+

+5VS +5VS +5VS +5VS

PS_CLK
KB_CLK

1394_PHYRST_S3P

DPCONF_S5P

D_DDC_CLK

D_CRT_R
D_CRT_G
D_CRT_B

D_CRT_VSYNC

DVI_SCLK

DVI_TXD2+

2 2

3 3

4 4

DVI_TXD2­DVI_TXD1+
DVI_TXD1­DVI_TXD0+
DVI_TXD0-

DVI_TXC+
DVI_TXC­DVI_DET#

RJ45_MDI3+
RJ45_MDI3-

MDC to Docking Conn.

MDC1_RING
MDC2_TIP

DCOCT1#

PS_CLK PS_DATA
KB_CLK KB_DATA

1394_PHYRST_S3P
DPCONF_S5P

D_DDC_CLK

D_CRT_R

D_CRT_G

D_CRT_B
D_CRT_VSYNC
DVI_SCLK DVI_SDATA

DVI_TXD2+
DVI_TXD2­DVI_TXD1+
DVI_TXD1­DVI_TXD0+
DVI_TXD0-

DVI_TXC+
DVI_TXC­DVI_DET#

RJ45_MDI3+
RJ45_MDI3-

MDC1_RING
MDC2_TIP

JP1

1
2
3
4

ACES_87213-0410WD@

A

245

GND
GND

VCC

S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
S37
S38
S39
S40
S41
S42
S43
S44
S45
S46
S47
S48
S49
S50
S51
S52

S55
S56

M59
M60

GND

GND
GND

VCC

S61
S62
S63
S64
S65
S66
S67
S68
S69
S70
S71
S72
S73
S74
S75
S76
S77
S78
S79
S80
S81
S82
S83
S84
S85
S86
S87
S88
S89
S90
S91
S92
S93
S94
S95
S96
S97
S98

S99
S100
S101
S102
S103
S104
S105
S106
S107
S108
S109
S110
S111
S112

S115
S117

MODEM

TYCO_1674036WD@

246
241

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52

55
56

59
60

253

B

+3VALW

10K_0402_5%WD@
R456
R453

247
248

242

61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112

115
117

EJCTSW#

1394_DILSON_S3P

D_DDC_DATA

Pin 73, 74 and 75 for VGA GND

D_CRT_HSYNC

RJ45_MDI2­RJ45_MDI2+

100K_0402_5%WD@

EC_SMB_DA2

1 2

EJCTSW#
PS_DATA

KB_DATA

1394_DILSON_S3P

D_DDC_DATA

D_CRT_HSYNC

DVI_SDATA

RJ45_MDI2­RJ45_MDI2+

+5VALW

R23

G

S

2N7002_SOT23WD@

12

1 2

2

10K_0402_5%WD@

EC_SMB_CK2

13

D

Q5

+3VALW

2

1 3

D

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DCOCT1#
DCOCT2#

G

S

C

+3VALW

C377

5

U38

2

P

I0

O

1

I1

G

3

AUD_SUDMUT_P3#

DOCK_ON/OFFBTN#

Q6

2N7002_SOT23WD@

G

2

13

D

S

Q3

2N7002_SOT23WD@

2005/06/01 2006/06/01

C

0.1U_0402_16V4ZWD@

12

DOCKIN#

4

TC7SH32FU_SSOP5WD@

+5VALW

XTPA1+ XTPA1­XTPB1+ XTPB1-

LINEOL
LINEIL
LINEIR#

DCD#
DSR#

TXD

RI#
LPTPE
FD7
FD6

FD4
FD1
FD2
FD0
R_LPTSTB#

+3VALW

RJ45_GND

RJ45_MDI0+

RJ45_MDI0-

1 2

R17

1 2

R20

Compal Secret Data

Deciphered Date

+3VALW

12

D_EC_SMB_CK2 D_EC_SMB_DA2

TPA1+ TPA1­TPB1+ TPB1-

AUD_SUDMUT_P3#
LINEOL

LINEIL
LINEIR#

DOCK_ON/OFFBTN#
DCD#
DSR#
TXD
RI#
LPTPE
FD7
FD6

FD4
FD1
FD2
FD0
R_LPTSTB#

RJ45_GND
RJ45_MDI0+
RJ45_MDI0-

1394_DILSON_S3P

4.7K_0402_5%WD@

D_EC_SMB_CK2

4.7K_0402_5%

WD@

D_EC_SMB_DA2

R459
100K_0402_5%

DOCKIN#

+5VALW

+5VALW

D

JP17B

249

GND

250

GND

243

VCC

121

S121

122

S122

123

S123

124

S124

125

S125

126

S126

127

S127

128

S128

129

S129

130

S130

131

S131

132

S132

133

S133

134

S134

135

S135

136

S136

137

S137

138

S138

139

S139

140

S140

141

S141

142

S142

143

S143

144

S144

145

S145

146

S146

147

S147

148

S148

149

S149

150

S150

151

S151

152

S152

153

S153

154

S154

155

S155

156

S156

157

S157

158

S158

159

S159

160

S160

161

S161

162

S162

163

S163

164

S164

165

S165

166

S166

167

S167

168

S168

169

S169

170

S170

171

S171

172

S172

173

S173

175

S175

178

L178

179

L179

180

L180

TYCO_1674036WD@

D

251

GND

252

GND

244

VCC

181

S181

182

S182

183

S183

184

S184

185

S185

186

S186

187

S187

188

S188

189

S189

190

S190

191

S191

192

S192

193

S193

194

S194

195

S195

196

S196

197

S197

198

S198

199

S199

200

S200

201

S201

202

S202

203

S203

204

S204

205

S205

206

S206

207

S207

208

S208

209

S209

210

S210

211

S211

212

S212

213

S213

214

S214

215

S215

216

S216

217

S217

218

S218

219

S219

220

S220

221

S221

222

S222

223

S223

224

S224

225

S225

226

S226

227

S227

228

S228

229

S229

230

S230

231

S231

232

S232

233

S233

234

S234

235

S235

236

S236

LAN

239

L239

240

L240

254

GND

Title

SCHEMATIC, M/B LA-3011

Size Document Number Rev

Date: Sheet



USB20_P6
USB20_N6

LINEOR
LINEOR#
LINEOL#
LINEIL#
LINEIR

RXD
RTS#
CTS#
DTR#
LPTSLCT
LPTBUSY
LPTACK#
FD5

FD3
LPTSLCTIN#
LPTINIT#
LPTERR#
AFD#/3M#

LAN_ACTIVITY#
LAN_LINK#
DCOCT2#

RJ45_MDI1+
RJ45_MDI1-

Compal Electronics, Inc.

401395

01, 2005



E

E

USB20_P6
USB20_N6

LINEOR
LINEOR#
LINEOL#
LINEIL#
LINEIR

RXD

RTS#

CTS#
DTR#
LPTSLCT
LPTBUSY
LPTACK#
FD5

FD3
LPTSLCTIN#
LPTINIT#
LPTERR#
AFD#/3M#

LAN_ACTIVITY#
LAN_LINK#

RJ45_MDI1+
RJ45_MDI1-

34 48,

A

of

FWE#

EC_SMB_CK1
EC_SMB_DA1

C242

1 2

0.1U_0402_16V4Z

4

+LDO3_EC

5

U22

2

P

I0

O

1

I1

G

TC7SH32FU_SSOP5

3

+5VALW

C244 0.1U_0402_16V4Z

1 2

U24

8

VCC

7

WP

6

SCL

5

SDA

AT24C16AN-10SI-2.7_SO8

+LDO3_EC

12

R312
100K_0402_5%

A0
A1
A2

GND

+3VALW

SB_INT_FLASH_SEL#

1

14

2

G

1 3

D

S

Q20
2N7002_SOT23

+5VALW

12

R335
100K_0402_5%

1
2
3
4

12

R326
100K_0402_5%

SUSP#

EC_FLASH#

FWR#

10

U19C

8

OE#

I9O

SN74LVC125APWLE_TSSOP14

INT_FSEL#

INT_FLASH_SEL

SN74LVC125APWLE_TSSOP14

R314
10K_0402_5%

R322 22_0402_5%

1 2

R321 0_0402_5%@

U19A

3

+3VALW

1 2

4

U19B

6

SN74LVC125APWLE_TSSOP14

1 2

P

OE#

I2O

G

7

C240 0.1U_0402_16V4Z

INT_FLASH_EN#

OE#

I5O

SN74LVC125APWLE_TSSOP14

13

OE#

I12O

R313
100K_0402_5%

U19D

SUS_STAT#

1 2

1 2

FSEL#

11

FRD#

1MB Flash ROM

KBA0
KBA1
KBA2
KBA3
KBA4
KBA5
KBA6
KBA7
KBA8
KBA9
KBA10
KBA11
KBA12
KBA13
KBA14
KBA15
KBA16
KBA17
KBA18
KBA19

INT_FSEL#
FRD#
FWE#

U23

21

A0

20

A1

19

A2

18

A3

17

A4

16

A5

15

A6

14

A7

8

A8

7

A9

36

A10

6

A11

5

A12

4

A13

3

A14

2

A15

1

A16

40

A17

13

A18

37

A19

22

CE#

24

OE#

9

WE#

SST39VF080-70_TSOP40

VCC0
VCC1

RP#

READY/BUSY#

NC0
NC1

GND0
GND1

KBA[0..19]
ADB[0..7]

KBA[0..19]
ADB[0..7]

1MB ROM Socket

+LDO3_EC

31
30

ADB0

25

D0
D1
D2
D3
D4
D5
D6
D7

NC

ADB1

26

ADB2

27

ADB3

28

ADB4

32

ADB5

33

ADB6

34

ADB7

35

RESET#

10
11
12
29
38

23
39

1 2

R344 100K_0402_5%

1

C259

0.1U_0402_16V4Z

2

+LDO3_EC

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/06/01 2006/06/01

KBA16 KBA17
KBA15
KBA14

KBA12
KBA11
KBA9
KBA8
FWE#
RESET#
INT_FLASH_EN#
INT_FLASH_SEL
KBA18
KBA7
KBA6
KBA5
KBA4
KBA3
KBA2
KBA1

Compal Secret Data

Deciphered Date

JP30

1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40

SUYIN_80065AR-040G2T

KBA19KBA13
KBA10
ADB7
ADB6
ADB5
ADB4

ADB3
ADB2
ADB1
ADB0
FRD#

FSEL#
KBA0

+3VALW

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3011



401395

01, 2005



35 48,

of

A

ON/OFFBTN#

KSI2
KSI3
KSI4
KSI5
KSO3

HDD_LED#

PWR BTN/B

INBTN#
PWR_LED0#
PWR_SUSPLED0#
Mode_Key

HDD LED

+5VS

Green

D22

HT-191UYG-DT_GRN_0603

12

21

JP4

1
2
3
4
5
6
7
8
9
10
11
12

ACES_85201-1205

R666
300_0603_1%

INBTN#

1

DAN202U_SC70

Vivace(SW-DJ) Button

Mode_Key

1

+3VALW

47K

Q48

DTA114YKA_SC59

DTA114YKA_SC59

10K

2

1 3

R667 120_0402_5%

1 2

R668 120_0402_5%

1 2

+5VALW

47K

Q7

10K

1 3

R465 300_0402_5%

R466 300_0402_5%

Change from 300 to 120

R244 100K_0402_5%

D11

2

51ON#

3

R270 100K_0402_5%

D12

2

51ON#

3

DAN202U_SC70

Q45

2

R661

1 2

2N7002_SOT23

2

1 2

1 2

1 3

D

Q8

R54

1 2

G

S

0_0402_5%@

1 3

D

2N7002_SOT23

Change from 120 to 300

1 2

IE_BTN#

1 2

MODE#

SYSON

PWR_SUSP_LED#

PWR_SUSPLED0#

PWR_SUSPLED1#

Power LED

2

G

PWR_LED#

S

0_0402_5%@

PWR_LED0#

PWR_LED1#

+3VALW

51ON#

10C/10GC:Green:SC591UYG000

10/10C:Blue:SC5191NB000

+LDO3_EC

AC-IN LED

D19
HT-191UYG-DT_GRN_0603

PWR_SUSP_LED#

Low Active

SYSON

PWR_LED#

Low Active

Green

ACIN

2

G

+5VALW

21

12

R664
300_0603_1%

13

D

Q46

S

2N7002_SOT23

5 In 1 Card LED
(Close to Socket)

+3VS

12

R665
150_0603_5%

21

Green

D23

HT-191UYG-DT_GRN_0603

5IN1_LED#

+5VALW

Battery LED

Green

300_0603_1%

BATT_CHGI_LED# BATT_LOW_LED#

10/10C:Blue/Amber:SC597UDB000

10C/10GC:Green/Amber:SC500001900

Wireless Lan LED

+5VS

12

R669
150_0402_5%

R662

R663
300_0603_1%

1 2

1 2

21

34

D21
HT-297UD/NB_BLUE/AMB_0603

Amber

PWR_SUSPLED1#

PWR_LED1#

Amber

Amber

D20

3 4

2 1

HT-297UD/NB_BLUE/AMB_0603

WL_LED

WL_LED

2N7002_SOT23

Green

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CON TAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/06/01 2006/06/01

Compal Secret Data

Deciphered Date

D34

Amber:SC5110UD000

HT-110UD_1204

1 2
13

D

2

G

Q47

S

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC , M / B L A-3011

401395



, 01, 2005

 

of

36 48

A

ON/OFFBTN#

DOCK_ON/OFFBTN#

ACZ_SDOUT_MDC

ACZ_SYNC_MDC

ACZ_SDIN1

Reserved power button

SW1

5

6

R163

100K_0402_5%

WD@

3
4

SMT1-05_4P

PSOT24C_SOT23

ON/OFFBTN#

100K_0402_5%

WD@

1 2

D5

Q14

1
2

R324

33_0402_5%

1000P_0402_50V7K

2

3

1

RTCVREF

R156

1 2

G

2

D

S

2N7002_SOT23

WD@

1 2

R170 0_0402_5%@

1 2

1

C229

2

DAN202U_SC70

13

ACZ_SDOUT_MDC
ACZ_SYNC_MDC

ACZ_SDIN1_MDC
ACZ_RST#_MDC

+3VS

D6

1

2N7002_SOT23

MDC 1.5 Conn.

JP27

1

GND1

3

IAC_SDATA_OUT

5

GND2

7

IAC_SYNC

9

IAC_SDATA_IN

11

IAC_RESET#

GND13GND14GND15GND16GND17GND

1

1

C241

C236

2

2

0.1U_0402_16V4Z

Power Button

+3VALW

R177
100K_0402_5%

1 2

2

51ON#

3

Q15

13

D

G

S

Connector for MDC Rev1.5

4.7U_0805_10V4Z@

C190

2

1

1000P_0402_50V7K

2

R195

10K_0402_5%

1 2

EC_ON

ON/OFF
51ON#

12

RES0
RES1

3.3V
GND3
GND4

IAC_BITCLK

18

D8

RLZ20A_LL34

+3VS

2
4
6
8
10

ACZ_BITCLK_MDC

12

ACES_88018-124G

RTCVREF

0.1U_0402_16V4Z

R412

1 2

0_0402_5%

C345

ACZ_BITCLK_MDCACZ_RST#_MDC

4

1

2

Lid Switch

1 2

R419 47K_0402_5%
U34

A3212EEH_MLP6

VDD5OUTPUT

NC

NC

GND

3

+LDO3_EC

1 2

D24

LID_SW#

1

DAN202U_SC70

3
4

SMT1-05_4P

2
3

LID

1

2

1

C346

2

10P_0402_25V8K

TP Button

SW3

SW_L SW_R

1
2

5

6

R416
100K_0402_5%

1
2

ACES_88170-3400

LID_SW#

S4_LID_SW#

SW2

5

6

INT_KBD CONN.

KSO[0..17]
KSI[0..7]

KSO15

KSO14

KSO10

KSO11

KSO8

KSO9

KSO13

KSI7

KSO3

KSO7

KSO12

KSI4

KSI6

KSI5

KSO6

KSO5

KSI3

KSI0

KSO0

KSO1
KSI1
KSI2
KSO2

KSO4

1 2

1 2

KSI6
KSI5
KSO6

KSO5

KSO15
KSO14
KSO10
KSO11

TP CONN.

TP_DATA
TP_CLK

NUM_LED#
PADS_LED#
CAPS_LED#

1 2

R582300_0402_5%

R583300_0402_5%

100P_1206_8P4C_50V8

2
3
4 5

CP4

100P_1206_8P4C_50V8

2
3
4 5

CP1

TP_DATA
TP_CLK

SW_L
SW_R

R102

JP10

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34

3
4

SMT1-05_4P

KSO[0..17]
KSI[0..7]

+3VS

R135300_0402_5%

+3VS

+3VS

KSO8
KSO9
KSO13
KSI7

81
7
6

81
7
6

KSI1
KSI2
KSO2
KSO4

KSO3
KSO7
KSO12
KSI4

KSI3
KSI0
KSO0
KSO1

12

0_0402_5%@

Touchpad mount direction:
Standard: N/A, Reverse: Stuff

100P_1206_8P4C_50V8

100P_1206_8P4C_50V8

100P_1206_8P4C_50V8

100P_1206_8P4C_50V8

2
3
4 5

CP2

2
3
4 5

CP6

2
3
4 5

CP3

2
3
4 5

CP5

+5VS

JP9

12
11
10
9
8
7
6
5
4
3
2
1

ACES_87151-1207

81
7
6

81
7
6

81
7
6

81
7
6

C125

0.1U_0402_16V4Z

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/06/01 2006/06/01

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3011

 

401395

05

37 48, 01, 20

of

A

5

4

3

2

1

C507

12
12

DCD#1
RI#1
CTS#1
DSR#1

RXD1

1 2

R332 1K_0402_5%SI207@

DTR#1

1 2

R330 10K_0402_5%SI207@

RTS#1

+3VS

1

2

RP26

1 8
2 7
3 6
4 5

4.7K_8P4R_1206_5%

+3VS

R331

10K_0402_5%@

Base I/O Address

1 2

0 = 02Eh

*

1 = 04Eh

R327

1K_0402_5%SI207@

1 2

JP6

1
2
3
4
5

ACES_85201-0505

+3VS

SUPER I/O SMsC LPC47N207

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

LPC_DRQ#1
LPC_FRAME#
PM_CLKRUN#
SERIRQ
CLK_PCI_SIO

CLK_14M_SIO
SIO_PD#
PME#

LPC_AD[0..3]

1

C301

4.7U_0805_10V4ZSI207@

2

U29

64

LAD0

2

LAD1

4

LAD2

7

LAD3

10

LPC_CLK_33

12

LDRQ1#

24

LDRQ0#

14

LFRAME#

16

CLKRUN#

19

SERIRQ

21

PCI_CLK

22

PCIRST#

23

SIO_14M

25

LPCPD#

47

IO_PME#

63

DLAD0

1

DLAD1

3

DLAD2

6

DLAD3

9

DLPC_CLK_33

11

DLDRQ1#

13

DLFRAME#

15

DCLKRUN#

18

DSER_IRQ

26

DSIO_14M

LPC47N207-JN_STQFP64

SI207@

+3VS +3VALW

1

C299

2

0.1U_0402_16V4Z

+3VS

3.3V53.3V173.3V313.3V423.3V

LPC I/F

DLPC I/F

0.1U_0402_16V4Z

1

C272

2

48

60

VTR

GPIO12/IO_SMI#

GPIO13/IRQIN1
GPIO14/IRQIN2

RTS1#/SYSOPT0
DTR1#/SYSOPT1

SERIAL I/F

IRMODE/IRRX3

IR GPIO

GND08GND120GND229GND337GND445GND5

1

C581

2

0.1U_0402_16V4Z

1

2

GPIO10
GPIO11

GPIO15
GPIO16
GPIO17
GPIO30
GPIO31
GPIO32
GPIO33
GPIO34
GPIO35
GPIO36
GPIO37

RXD1

TXD1

DRSR1#

CTS1#

RI1#

DCD1#

IRTX2
IRRX2

62

C260

LPC_DRQ#1
LPC_FRAME#

PM_CLKRUN#

SIRQ
CLK_PCI_SIO
PCI_RST#
CLK_14M_SIO
SIO_PD#

PME#

LPC_AD[0..3]

1

C269

0.1U_0402_16V4ZSI207@

2

D D

C C

+3VS+3VALW

TPM1.2 on board

0.1U_0402_16V4Z

+3VS

T35 PA D
T32 PA D

12

R642

B B

A A

4.7K_0402_5%

R644

4.7K_0402_5%@

Base I/O Address

0 = 02Eh
1 = 04Eh

*

12

12

R637
0_0402_5%

SLB 9635 TT 1.2_TSSOP28

C584

1

2

6

GPIO

2

GPIO2

8

TEST1

9

TESTB1/BADD

3

NC

12

NC

1

NC

10

19

5

U46

VSB

VDD

VDD



GND

GND

GND

4

11

18

TPM_XTALI

TPM_XTALO

2

1

24

VDD

LAD0
LAD1
LAD2
LAD3

LFRAME#

LRESET#

LPCPD#
SERIRQ

LCLK

CLKRUN#

XTALO

XTALI/32K IN

GND

25

12

R657

10M_0402_5%

0.1U_0402_16V4Z

C585

26
23
20
17
22
16
28
27
21

15

7

PP

14
13

C612

1
4

C610

0.1U_0402_16V4Z

Y4

0.1U_0402_16V4Z

2

2

C601

1

1 2

1 2

C598

1

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

LPC_FRAME#

PLT_RST#

SUS_STAT#

CLK_PCI_TCG

PM_CLKRUN#

R633

TPM_XTALO
TPM_XTALI

18P_0402_50V8J

32.768KHZ_12.5P_1TJS125BJ2A251

IN

NC

OUT

NC

18P_0402_50V8J

SIRQ

12

4.7K_0402_5%

2
3

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#

SUS_STAT#
SIRQ
CLK_PCI_TCG

PM_CLKRUN#

+3VS

PLT_RST#

Finger printer

USB20_N0
USB20_P0

0.1U_0402_16V4ZSI207@

27
28
30
32
33
34
35
36
38
39
40
41

FIR_DET#

43
44
46
61

RXD1

52

TXD1

53

DSR#1

54

RTS#1

55

CTS#1

56

DTR#1

57

RI#1

58

DCD#1

59

IRTXOUT

49

IRRX

50

IRMODE

51

PACDN042_SOT23~D@

RXD1
TXD1
DSR#1
RTS#1
CTS#1
DTR#1
RI#1
DCD#1

IRTXOUT

IRRX
IRMODE

FIR_DET#

0.1U_0402_16V4Z

0_0402_5%
R562
R561

0_0402_5%

2

3

D31

1

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/06/01 2006/06/01

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3011

 

401395

05

38 48, 01, 20

1

A

of

A

1 1

2 2

SYSON#

SYSON

SUSP

SUSP#

SYSON#

2

G

SUSP

2

G

+5VALW

+5VALW

12

13

D

S

12

13

D

S

B

R635
47K_0402_5%

Q43
2N7002_SOT23

R636
10K_0402_5%

Q44
2N7002_SOT23

1

CF1

CF8

H1
HOLEA

C

1

1

FM2

CF10

CF14

H4
HOLEA

1

CF9

1

1

FM41FM6

1

CF6

1

1

H6

H5

HOLEA

HOLEA

1

FM5

1

CF4

CF5

1

1

H9

H8

H7
HOLEA

1

1

HOLEA

1

HOLEA

1

FM1

FM3

1

1

CF12

CF11

CF2

1

1

1

CF3

CF7

CF13

1

1

1

H3

H2

HOLEA

HOLEA

1

1

1

H10
HOLEA

1

D

E

+5VALW to +5VS Transfer

+5VALW +5VS

U15

S

D

S

D

S

D

G

D

SI4800DY_SO8

RUNON

1
2
3
4

B+

12

R612
330K_0402_5%

13

SUSP

3 3

D

Q41

2

2N7002_SOT23

G

S

C216

10U_0805_10V4Z

12

1

2

8
7

1

6
5

2

R611
470_0402_5%

C557

0.01U_0402_16V7K

1

C208
10U_0805_10V4Z

2

0.1U_0402_16V4Z

1

C205

2

Q42

2N7002_SOT23

12

R613
470_0402_5%

13

D

S

C249

10U_0805_10V4Z

SUSP

2

G

+3VALW to +3VS Transfer

+3VALW

U25

8

S

D

7

1

2

D

6

D

5

D

SI4800DY_SO8

S
S
G

+3VS

1

C246
10U_0805_10V4Z

2

2N7002_SOT23

0.1U_0402_16V4Z

1

C250

2

Q22

12

R323
470_0402_5%

13

D

S

SUSPRUNON

2

G

1
2
3
4

+1.8V to +1.8VS Transfer

+2.5VS +1.8V

12

R4
470_0805_5%

13

D

Q2

2N7002_SOT23

4 4

SUSP SYSON# SUSP SUSP

2

G

S

2N7002_SOT23

A

12

R94
470_0805_5%

13

D

Q11

2

G

S

2N7002_SOT23

2N7002_SOT23

+1.5VS +VCCP

12

R237
470_0805_5%

13

D

Q17

Q9

S

+0.9VS

12

R91
470_0805_5%

13

D

S

2

G

2

G

2N7002_SOT23

SUSP

12

R203
470_0805_5%

13

D

Q16

2

G

S

B

10U_0805_10V4Z

+1.8V

U5

8

S

D

7

1

C10

2

D

6

D

5

D

SI4800DY_SO8

S
S
G

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

+1.8VS

1

C8
10U_0805_10V4Z

2

2N7002_SOT23

0.1U_0402_16V4Z

12

1

C9

2

13

D

Q1

S

Compal Secret Data

Deciphered Date

R5
470_0402_5%

SUSPRUNON

2

G

1
2
3
4

2005/06/01 2006/06/01

D

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3011

 

401395

05

39 48, 01, 20

E

of

A

A

+DC_IN_S1

1 2

PD2

PR11

1 2

PR12

1 2

3.3V

12

PC10
10U_0805_10V4Z

PL1

1000P_0402_50V7K

12

1538VCC

12

12

PC7

0.22U_1206_25V7M@

OUT

PU2

IN

GND

1

S-812C33AUA-C2N-T2_SOT89

3

12

PC1

PR167 68_1206_5%

1 2

1 2

PR168 68_1206_5%

PQ1

2

2

12

PC9
1U_0805_25V4Z

+1.5VSP +1.5VS+3VALWP +3VALW

(3.5A,140mils ,Via NO.= 7)

PJP1

1

+

2

+

3

1 1

2 2

+CHGRTC

3 3

-

4

-

SINGA_2DW-0005-B03

@

BATT_A

51ON#

PR17

1 2

560_0603_5%

(5A,200mils ,Via NO.= 10)

+5VALWP +5VALW

(5A,200mils ,Via NO.= 10)

DC_IN_S2 DC_IN_S1

FBMA-L18-453215-900LMA90T_1812

1N4148_SOD80

200_0603_5%

100K_0402_5% @

PR14 22K_0402_5% @

RTCVREF

PR18

1 2

560_0603_5%

PJ1

@

2

112

JUMP_43X118

PJ3

@

2

112

JUMP_43X118

(2A,80mils ,Via NO.= 4)

PJ7

PJ5

+1.8VP +1.8V

(8A,320mils ,Via NO.= 16)

4 4

(3.5A,140mils ,Via NO.= 7)

2

JUMP_43X118

@

2

@

JUMP_43X118

PJ8

@

2

JUMP_43X118

112

112

112

A

+VCCP+VCCPP

(2A,80mils ,Via NO.= 4)

PF1

12A_65V_451012MRL

12

PC2

100P_0402_50V8J

13

TP0610K_SOT23@

PJ2

@

2

JUMP_43X118

PJ4

@

2

JUMP_43X118

PJ6

@

2

JUMP_43X118

21

VIN

1 2

12

PR8

12

112

112

112

B

12

PC3

1000P_0402_50V7K

PD1

1N4148_SOD80

12

PR9

68_1206_5%

PC8

0.1U_0603_25V7K

B

C

12

1

PC12

PD4

1N4148_SOD80

VIN

12

PR3

61.9K_0402_1%

1 2

PR5 15.4K_0402_1%

12

PR6
20K_0402_1%

12

PU1B

8

P

+

7

O

-

G

12

4

LM393DG_SO8

1000P_0402_50V7K

Compal Secret Data

Deciphered Date

12

PC6

0.1U_0402_16V7K

1 2

1K_1206_5%

1 2

1K_1206_5%

1 2

1K_1206_5%

1 2

2.2M_0402_5%

5
6

12

PC13

C

1 2

PR1 1M_0402_1%

3

+

2

-

PR10

10K_0402_5%

PR13

PR15

PR16

PR21

PR23

1 2

12

34K_0402_1%

PR24

66.5K_0402_1%

2N7002-7-F_SOT23-3

VIN

12

PC4

PC5

1000P_0402_50V7K

VS

68_1206_5%

100P_0402_50V8J

VIN

PR20

VL

MAINPWON

ACON

+0.9VS+0.9VSP

1 2

10K_0402_5%

PD5

2
3

RB715F_SOT323

0.1U_0402_16V7K

Precharge detector

+2.5VS+2.5VSP

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

14.3V/13.18V for adapter

2005/06/23 2006/06/23

VS

8

PU1A

P

1

O

G

LM393DG_SO8

4

12

RTCVREF

3.3V

VL

12

13

D

PQ2

S

PQ3

DTC115EUA_SC70

PD3

RLZ4.3B_LL34

PR25
237K_0402_1%

2

G

13

D

VS

12

PR2

5.6K_0402_5%

12

PR4
1K_0402_5%

12

PR7
10K_0402_5%

1 2

PACIN

ACIN

PACIN

Vin Detector

High 14.57 14.01 13.46
Low 14.06 13.51 12.98

B+

12

PR19
499K_0402_1%

12

PR22
499K_0402_1%

PR26

1 2

47K_0402_5%

2

Title

Size Document Number Rev

B

Date: Sheet

12

PC11
1000P_0402_50V7K

PACIN

+5VALWP

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3011

401395



, 01, 2005



D

40 48

of

A

A

B

C

D

PH1 under CPU botten side :

CPU thermal protection at 84 degree C
Recovery at 45 degree C

1 1

2 2

PJP2

@

1

BATT+

2

ID

3

B/I

4

TS

5

SMD

6

SMC

7

GND

SUYIN_250005MR007G132ZR

BATT_S1

ALI/NIMH#

AB/I

TS_A
EC_SMDA
EC_SMCA

PR33

1 2

PR34

100_0402_5%

1 2

100_0402_5%

1K_0402_5%

PR28

1 2

12

PR31

12

PR38
1K_0402_5%

12A_65V_451012MRL

PF2

1K_0402_5%

6.49K_0402_1%

21

1 2

47K_0402_5%

PR35

PR29

+3VALWP

12

VMB_A

FBMA-L18-453215-900LMA90T_1812

12

PC15
1000P_0402_50V7K

+3VALWP

1 2

PL2

ALI/MH#

BATT_TEMPA
EC_SMB_DA1
EC_SMB_CK1

12

PC16

0.01U_0402_25V7Z

BATT

100K_0603_1%_TH11-4H104FT

VL VS

12

PH1

PR32

1 2

13.7K_0402_1%

0.22U_0805_16V7K

12

12

PC17

PR36
22K_0402_1%

1000P_0402_50V7K

TM_REF1

12

PC18

12

PC14

0.1U_0603_25V7K

3

+

2

-

PR37

100K_0402_1%

12

PR39
100K_0402_1%

PR30

1 2

47K_0402_1%

8

PU3A

P

1

O

G

LM393DG_SO8

4

12

VL

VL

PR27
47K_0402_1%

1 2

1SS355_SOD323

PD6

MAINPW O N

13

PQ4
DTC115EUA_SC70

2

12

PH2 near main Battery CONN :

BAT. thermal protection at 79 degree C
Recovery at 45 degree C

100K_0603_1%_TH11-4H104FT

12

12

PH2

10.7K_0402_1%

1 2

12

PR43
22K_0402_1%

PR42

TM_REF1

1 2

47K_0402_1%

5

+

6

-

3 3

PC19

0.22U_0805_16V7K

PR41

8

PU3B

P

7

O

G

LM393DG_SO8

4

VLVL

1 2

PR40
47K_0402_1%

PD7

1SS355_SOD323

12

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

2005/06/23 2006/06/23

Compal Secret Data

Deciphered Date

C

Title

Size Document Number Rev

B

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3011

401395



, 01, 2005



D

41 48

of

A

A

B

C

D

P2

PQ6
AO4407_SO8

VIN

1 1

12

PR46
47K_0402_5%

2

13

D

PQ12

2

G

S

2N7002-7-F_SOT23-3

2 2

PACIN

ACON

8
7

5

47K

2

47K

13

DTA144EUA_SC70

PQ10

DTC115EUA_SC70

ACOFF#

1SS355_SOD323

PACIN

1 3

1 2

1 2

4

PQ8

PD8

PR57

3K_0402_1%

1
2
36

0.1U_0603_25V7K

PR45

PC23

12

PR53

2

G

PQ13

IREF=1.07*Icharge
IREF=0.6V~3.21V

PR174

47K_0402_5%

PR176

1 2

47K_0402_5%

1SS355_SOD323

+3VALWP

12

2

13

DTC115EUA_SC70

PD13

PQ15

12

A

DOCKING_CTRL

FSTCHG

BATT_AOVP

7

0

DOCKIN#

PR64
47K_0402_5%

8

PU5B

5

P

+

6

-

G

LM358ADR_SO8

4

2

3 3

4 4

12

CS

13

PQ14

DTC115EUA_SC70

PR69

2.2K_0402_5%

2

1

PQ7
AO4407_SO8

1
2
3 6

12

200K_0402_1%

12

100K_0402_1%

13

D

2N7002-7-F_SOT23-3

S

+3VALWP

1 2
13

DTC115EUA_SC70

VS

8

PU5A

P

+

0

-

G

LM358ADR_SO8

4

IREF

2

PQ40

3
2

4

12

PR175

43K_0402_5%

13

DTC115EUA_SC70

PR70

105K_0402_1%

8
7

5

ADP_I

12

PC26

162K_0402_1%

1 2

100K_0402_1%

PQ39

P3 B+

12

PR51

12.7K_0402_1%

12

PR61

PR65
340K_0402_1%

PR68
499K_0402_1%

PR50

PC29

PC33

12

0.1U_0402_16V7K

PR56

VMB_A

12

12

12

Iadp=0~4.7A

PR49 100K_0402_5%

12

PC27

1 2

25.5K_0402_1%

4700P_0402_25V7K

12

PC30

1 2

1000P_0402_50V7K

0.1U_0402_16V7K

PR59 10K_0402_5%

12

0.1U_0402_16V7K

PC38

0.01U_0402_25V7Z

PR44

12

0.015_2512_1%

12

PR52

1 2

10K_0402_5%

PR54

1 2

1K_0402_5%

12

PR62

150K_0603_0.1%

PU4

1

-INC2

+INC2

2

OUTC2

3

+INE2

4

-INE2

VCC(o)

5

FB2

6

VREF

7

FB1

8

-INE1

9

+INE1

10

OUTC1

11

OUTD

12

-INC1

+INC1

MB3387PFV-ERE1_SSOP24~N

12

GND

CS

OUT

VH

VCC

RT

-INE3

FB3

CTL

PJ9

@

2

JUMP_43X118

24

23

22

21

20

1 2

19

PC28

0.1U_0603_25V7K

18

1 2

17

PR55
68K_0402_5%

16

1 2

15

47K_0402_5%

ACON

14

13

112

CS

PR60

12

PC20

4.7U_1206_25V6K

PC24

0.022U_0402_16V7K

1 2

PC25

1 2

0.1U_0603_25V7K

PC31

1 2

0.1U_0603_25V7K

PC32

1 2

1500P_0402_50V7K

4.2V

12

PC21

4.7U_1206_25V6K

Adapter Iadp P R50

75W

90W

4.7A

5.52A

25.5K_0402_1%

20K_0402_1%

OVP voltage : LI

3S3P : 13.5V--> BATT_OVP= 1.5V

(BAT_OVP=0.1111 *VMB)

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

2005/06/23 2006/06/23

Compal Secret Data

Deciphered Date

C

12

N18

PD9

EC31QS04

PR63

12

300K_0603_0.1%

36

578

12

B++

241

PQ9
AO4407_SO8

LXCHRG

PL3

1 2

PD10

EC31QS04

B+

ACOFF#

DKN_B+_ON

Title

Size Document Number Rev

B

Date: Sheet

PC22

4.7U_1206_25V6K

16UH_D104C-919AS-160M_3.7A_20%

12

PQ5

1 2

47K_0402_5%

PR48

1K_0402_5%

1 2
13

2

PQ11

DTC115EUA_SC70

AO4407_SO8

1
2
3 6

PR47

8
7

5

4

VIN

ACOFF

CC=0.5~3.0A
CV=12.6V(6 CELLS LI-ION)

PR58

1 2

0.02_2512_1%

DKN_B+

PR66

27K_0402_1%

1 2

1 2

PC37
1U_1206_25V7K

4.7U_1206_25V6K

PQ16
AO4407_SO8

8
7

5

2

PQ17

DTC115EUA_SC70

4.7U_1206_25V6K

4.7U_1206_25V6K

PC35

12

12

PC34

1
2
36

4

PR67
10K_0402_1%

1 2
13

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3011

401395



, 01, 2005



D

12

PC36

B+

42 48

of

BATT

A

5

4

3

2

1

+3.3VALWP/+5VALWP

D D

PJP3

B+

JUMP_43X118

@

C C

B B

A A

112

B+++

2

12

PC39

+5VALWP

PC40

4.7U_1206_25V6K

4.7U_LF919AS-4R7M-P3_5.2A_20%

150U_V_6.3VM_R18

4.7U_1206_25V6K

1

+

PC51

2

5

2

3

LX_5V

+LDO5

12

BST_5V

12

FB5

LDO3P

PQ23

RHU002N06_SOT323

@

PD11

14
16
15

19
21

9
1

6
4
3

12

8

12

PC54

0.22U_0603_16V7K

PR93
100K_0402_5%

1 2

13

D

S

PR73

10_1206_5%

PC48

12

V+

LDO3

25

12

13

D

S

VL

PR71

1 2

47_0402_5%

0.1U_0603_25V7K

1 2

13

17

ILIM3

TON

VCC

ILIM5
BST3

DH3

DL3
LX3

OUT3

FB3

PGOOD

PRO#

10

MAX8734AEEI+_QSOP28

LDO3P

PC55

4.7U_0805_6.3V6K

2

G

Compal Secret Data

12

2VREF_8734

PC46

1U_0603_10V6K

ILIM3

5

ILIM5

11
28

26
24
27
22

7
2

0_0402_5%

1 2

1 2

PR90

0_0805_5%

EC_ON

Deciphered Date

PC44

0.1U_0402_16V7K

PR76

1 2

PR79

1 2

BST_3V
DH_3V

FB3

POK

PR88

1

B+++

12

12

PR72

10_1206_5%

12

PC45

4.7U_1206_25V6K

18

20

PU6

BST5

LD05

DH5
LX5

DL5
OUT5
FB5
N.C.

SHDN#
ON5
ON3

SKIP#
REF

GND

23

ACIN

2

G

PQ24

RHU002N06_SOT323

@

2005/06/23 2006/06/23

3

PR77

1 2

118K_0402_1%

PR80

1 2

499K_0402_1%

PR82

0_0603_5%

+LDO3

PR171

1 2

0_0805_5%@

43.2K_0402_1%

499K_0402_1%

0.1U_0603_25V7K

12

LX_3V

2

PL4

10.5K_0402_1%

6.81K_0402_1%

12

PC41

2200P_0402_50V7K

12

VS

12

MAINPWON

D8D7D6D

S1S2S3G

D8D7D6D

S1S2S3G

PD12

RLZ5.1B_LL34

PR84

1 2

47K_0402_5%

PR172

5

PQ19

SI4800BDY-T1-E3_SO8

4

1 2

5

PQ21
SI4810BDY-T1-E3_SO8

4

DL_5V

12

100K_0402_5%

PR92

0_0402_5%@

PR75

0_0603_5%

12

PC52

12

0.047U_0603_16V7K@

1U_1206_25V7K @

1 2

DH_5V

PC49

0.1U_0603_25V7K

ACIN

VL

12

PR91

@

12

PC56

PR170

0_0805_5%@

12

1 2

10K_0402_5%

806K_0603_1%

PQ22

RHU002N06_SOT323

@

12

PR83

1 2

PR87

1 2

DAP202U_SOT323

PR74

0_0805_5%

VL

12

PC47

4.7U_0805_6.3V6K

PR78 0_0603_5%

PR85

2VREF_8734

13

D

2

G

S

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PC50

B+++

5

4

5

4

6.81K_0402_1%

10K_0402_1%

PQ18

D8D7D6D

S1S2S3G

SI4800BDY-T1-E3_SO8

D8D7D6D

PQ20

S1S2S3G

SI4810BDY-T1-E3_SO8

PL5

1

12

12

PC42

PC43

4.7U_1206_25V6K

4.7U_1206_25V6K

PR81

0_0603_5%

1 2

12

Date: Sheet

DL_3V

Title

SCHEMATIC, M/B LA-3011

Size Document Number Rev

Custom



LX_3V

PR86

1 2

PR89

1 2

Compal Electronics, Inc.

401395

, 01, 2005



4.7U_LF919AS-4R7M-P3_5.2A_20%

12

1

+

PC53

2

150U_V_6.3VM_R18

43 48

+3VALWP

A

of

A

B

C

D

PL6

1 2

FBMA-L18-453215-900LMA90T_1812

12

PC60

4.7U_1206_25V6K

1 2

4.7U_LF919AS-4R7M-P3_5.2A_20%
PL8

PR104

0_0402_5%

VSE_1.5V

PR109

0_0402_5%@

12

12

PC57

D8D7D6D

S1S2S3G

D8D7D6D

S1S2S3G

5

4

5

4

DH_1.8V-2

DAP202U_SOT323

PC66

12

0.1U_0402_16V7K

1 2

PR102

1 2

2K_0402_1%

DL_1.8V

1 2

PR106

47K_0402_1%

0.1U_0402_16V7K@

1 1

PQ25

+1.8VP

+1.8VP

1

+

PC68

2

2 2

220U_D2_4VM_R15

12

PR100

12

12

10K_0402_1%

PR108
10K_0402_1%

PC69

SI4800BDY-T1-E3_SO8

1.8U_D104C-919AS-1R8N_9.5A_30%

1 2

PR101

0_0402_5%

0.01U_0402_25V7Z

1 2

VSE_1.8V

PR111

0_0402_5%@

1 2

LX_1.8V

PL7

PQ27

SI4810BDY-T1-E3_SO8

SYSON SUSP

PC58

4.7U_1206_25V6K

4.7U_1206_25V6K

PD14

BST_1.8V-1

PR96

1 2

0_0603_5%
PR98
0_0603_5%

PC73

12

1

2

ISE_1.8V ISE_1.5V

12

PC61

3

BST_1.2V-1

PC64

12

12

0.01U_0402_25V7Z

10
15
11

12

PR113
100K_0402_1%

4.7U_0805_6.3V6K

6

5
4

7
2

3

9
8

PR94

0_1206_5%

12

PC62

0.1U_0603_25V7K

PU7

SOFT1

BOOT1

UGATE1
PHASE1

ISEN1
LGATE1

PGND1

VOUT1
VSEN1
EN1
PG1

OCSET1

12

+5VALW

17

0.01U_0402_25V7Z

23

24
25

22
27

26

20
19
21
16

18

12

PC65

BST_1.5V-2BST_1.8V-2

DH_1.5V-1 DH_1.5VDH_1.8V-1

12

100K_0402_1%

PC63

2.2U_0805_10V6K

12

PR97

1 2

0_0603_5%

1 2

1 2

1.4K_0402_1%

PC72

PR112

PC67

12

0.1U_0402_16V7K
PR99
0_0603_5%

PR103

DL_1.5V

1 2

12

PR107 10K_0402_1%

0.1U_0402_16V7K@

PR95

2.2_0603_5%

1 2

14

28

VIN

GND

1

SOFT2

VCC

BOOT2

UGATE2

PHASE2

ISEN2

LGATE2

PGND2

VOUT2
VSEN2

EN2

PG2/REF
OCSET2

DDR

ISL6227CAZ-T_SSOP28

13

PC59

4.7U_1206_25V6K

LX_1.5V

12

5

4

5

4

PQ26

D8D7D6D

S1S2S3G

SI4800BDY-T1-E3_SO8

D8D7D6D

PQ28

SI4810DY-T1-E3_SO8

S1S2S3G

1 2

1 2

B+

0.01U_0402_25V
PC71

12

12

PR105

12

6.81K_0402_1%

PR110
10K_0402_1%

+1.5VSP

+1.5VSP

1

+

PC70

220U_D2_4VM_R15

2

3 3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/06/23 2006/06/23

Compal Secret Data

Deciphered Date

C

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3011

401395

,



01, 2005



D

44 48

of

A

5

4

3

2

1

D D

C C

B B

SUSP#

A A

0.1U_0402_16V7K@

SUSP#

PR123

0_0402_5%

1 2

PL9

1 2

B+

FBMA-L18-453215-900LMA90T_1812

PR173

1 2

0_0402_5%

7

POK

8

EN

12

PC94

PU10

+5VS

12

PC87

1U_0603_6.3V6M

6

5

VIN

3

VOUT

VCNTL

4

VOUT

2

FB

9

VIN

GND

1

APL5912-KAC-TRL_SO8~N

+2.5VSP

PHASE_VCCPP

14

15

PHASE

7

12

PR119

57.6K_0402_1%

12

UG

PR121
3K_0402_1%

SUSP

PR114

1 2

0_0603_5%

BOOT_VCCPP

13

BOOT

PVCC

LG

PGND

ISEN

VO

8

12

PC84

0.01U_0402_25V7Z

12

PR169

4.7_0603_5%

@

1 2

4.7_0603_5%

12

1 2

2.2U_0603_6.3V6K

LG_VCCPP

11

10

PR117

ISEN_VCCPP

9

1 2

11.5K_0402_1%

ISL6269CRZ-T_QFN16

PR120

1 2

2.26K_0402_1%

10U_1206_6.3V7K

PR125

0_0402_5%

1 2

0.1U_0402_16V7K @

UG_VCCPP

1 2

PC78 0.1U_0402_16V7K

+5VS

6269_VCC

PR115

PC79

+1.8V

1

1

2

2

12

PC88

2

G

12

PC97

2N7002-7-F_SOT23-3

PJ10

JUMP_43X118@

1K_0402_1%

13

D

S

PQ31

PR122

PR126

12

12

1K_0402_1%

5

4

5

4

PC95

0.1U_0402_16V7K

PQ29

D8D7D6D

S1S2S3G

SI4800BDY-T1-E3_SO8

PQ30

D8D7D6D

SI4810BDY-T1-E3_SO8

S1S2S3G

12

12

PC96
10U_1206_6.3V7K

1.8UH_SIL104R-1R8PF_9.5A_30%

1 2

PL10

PU9

VIN1VCNTL

2

GND

3

VREF

4

VOUT

APL5331KAC-TRL_SO8

+0.9VSP

6
5

NC

7

NC

8

NC

9

TP

1

+

PC81
220U_D2_4VM_R15

2

12

+VCCPP

+3VALWP

PC89
1U_0603_6.3V6M

+1.05V

12

PC76

10U_1206_25V6M

12

12

PC83

0.1U_0402_16V7K

+3VS

1

PJ11

1

JUMP_43X79

@

2

2

12

PC90
22U_1206_6.3V6M

2.15K_0402_1%

12

PC77

10U_1206_25V6M

6269_VCC

PC80

2.2U_0603_6.3V6K

12

PR124

12

PR127
1K_0402_1%

PR116

1 2

0_0402_5%

12

PC85

12

PC93

0.01U_0402_25V7Z

16

PU8

PGOOD

1

VIN

2

VCC

3

22P_0402_50V8J

PC91

FCCM

4

EN

COMP5FB6FSET

12

PR118

49.9K_0402_1%

12

PC86
6800P_0402_25V7K

1

12

+

PC92

150U_D_6.3VM@

2

22U_1206_6.3V6M

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/06/23 2006/06/23

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3011

401395

@, 01, 2005

󰛗

1

45 48

A

of

5

4

3

2

1

D D

CPU_VID4

CPU_VID3

CPU_VID5

CPU_VID2

CPU_VID1

UGATE1
PHASE1

LGATE1

LGATE2

PHASE2
UGATE2

1 2

12

PC120
1U_0603_6.3V6M

PR157

1 2

10_0603_5%

12

PR161

2.61K_0402_1%

11K_0402_1%

1 2

CPU_VID0

12

12

PC103

PC102

0.01U_0402_25V7Z

1U_0603_6.3V6M

PC107

0_0603_5%

LGATE_CPU1

LGATE_CPU2

PHASE_CPU2

UGATE_CPU2

PR145

1 2

PR134

1 2

1 2

0.22U_0603_10V7K

PC114

1 2

0.22U_0603_10V7K

2005/06/23 2006/06/23

3

IRF8113PBF_SO8

BOOT_CPU1

VID037VID138VID239VID340VID441VID542VID6

36

BOOT1

PGND1

PVCC

PGND2

35
34
33
32
31
30
29
28

UGATE_CPU1
PHASE_CPU1

27

BOOT2

NC

24

PR152 1_0603_5%

PH4

Security Classification

25

PU11

ISEN1
ISEN2

0_0603_5%

+5VS

+VCC_CORE

BOOT_CPU2

26

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

10K_0603_1%_TH11-4H104FT

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

CPU_VID6

VR_ON

PR129 0_0402_5%

DPRSLPVR

H_DPRSTP#

CLK_EN#

+3VS

+3VS

C C

VGATE

H_PSI#

PGD_IN

VR_TT#

PR143 4.22K_0402_1%@

B B

A A

1 2

PR153 61.9K_0402_1%

VCCSENSE

+CPU_CORE

PR160 20_0402_5%

PR136

499_0402_1%

PR142 147K_0402_1%

1 2

PH3

1 2

470K_0603_1%_TH11-4H104FT@

1 2

PC1120.015U_0402_16V7K@

PR144 13K_0402_1%

1 2
1 2

PR147 3.57K_0402_1%

1 2

1 2

PC116 5600P_0402_25V7K

1 2

1 2

PC121 390P_0402_50V7K

3.4K_0402_1%

1 2

PR156

1 2

PR158 1.82K_0402_1%

1 2

PR159 0_0402_5%

1 2

VSSSENSE

5

1 2

PC1130.015U_0603_25V7K

1 2

PC1151000P_0402_50V7K

PC118 1500P_0402_50V7K

12

PC122 470P_0402_50V7K

1 2

PR163

20_0402_5%

VCC_PRM

PR133 0_0402_5%

12

PR135

PC124 0.018U_0603_50V7K

12

PC125

0.018U_0603_50V7K

@

12

PR165 1K_0402_1%

0.22U_0603_10V7K

1 2

PR130 0_0402_5%

1 2

PR131 0_0402_5%

1 2

1 2

12

PC106

1U_0603_16V6M

1.91K_0402_1%

1

PGOOD

2

PSI#

3

PGD_IN

4

RBIAS

5

VR_TT#

6

NTC

7

SOFT

8

OCSET

9

VW

10

COMP

11

FB

12

FB2

12

PR154

@

0_0402_5%

1 2

1 2

1 2

PR162 0_0402_5%

PC127 180P_0402_50V8J

1 2

1 2

PC129

PR132

45

46

CLK_EN#

DPRSTP#

DPRSLPVR

ISL6262CRZ-T_QFN48

12

44

VR_ON

0_0402_5%

43

48

47

3V3

VDIFF13VSEN14RTN15DROOP16DFB17VO18VSUM19VIN20GND21VDD22ISEN223ISEN1

PR155
0_0402_5%@

12

PC123

0.01U_0402_25V7Z

12

PC126

0.018U_0603_50V7K

VSUM

12

1 2

PR166 5.62K_0402_1%

12

PC128 33N_0603_50V8J

1 2

PC130 0.33U_0603_10V7K

4

PR164

12

+5VS

1 2

12

12

PC104

0.01U_0402_25V7Z

578

PQ33

PQ36

IRF8113PBF_SO8

Compal Secret Data

PR128
1_0603_5%

PC105

1U_0603_6.3V6M

3 6

241

578

3 6

3 5

241

578

3 6

578

241

Deciphered Date

PQ32
SI7840DP_SO8

PR137

PQ34

PC108

241

IRF8113PBF_SO8

PQ35
SI7840DP_SO8

3 5

241

PQ37
IRF8113PBF_SO8

3 6

241

PC99

10U_1206_6.3V7K

12

@

12

12

@

12

@

12

PC100

10U_1206_6.3V7K

4.7_1206_5%

680P_0603_50V8J

@

PC110

10U_1206_6.3V7K

PR146

4.7_1206_5%

PC117
680P_0603_50V8J

2

+CPU_B+

1

12

12

PC101

10U_1206_6.3V7K

P_0.36H_ETQP4LR36WFC_24A_20%

12

PR138

3.65K_0402_1%

VSUM

12

P_0.36H_ETQP4LR36WFC_24A_20%

12

PR149

3.65K_0402_1%

VSUM

2

12

PL12

PR139

PR141 0_0603_5%@

10K_0402_1%

1 2

PC109

1 2

ISEN1

0.22U_0603_10V7K

12

PC111

10U_1206_6.3V7K

12

PR148

10K_0402_1%

PR151 0_0603_5%@

1 2

PC119

1 2

0.22U_0603_10V7K

ISEN2

Title

SCHEMATIC, M/B LA-3011

Size Document Number Rev

Custom

Date: Sheet

PL11

1 2

FBMA-L18-453215-900LMA90T_1812

+

PC98
220U_25V_M

12

12

PR140

1_0402_5%

VCC_PRM

+CPU_B+

12

PL13

12

PR150

1_0402_5%

VCC_PRM

Compal Electronics, Inc.

401395

@, 01, 2005



B+

+VCC_CORE

A

of

46 48

1

NO DATE PAGE MODIFICATION LIST PURPOSE

-------------------------------------------------------------------------------------------------------------

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTA INS CONFIDENT IAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVIS ION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONT AINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITT EN CO NSE NT OF COMPAL ELECTRONICS, INC.

2005/06/01 2006/06/01

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

SCHEMATIC, M/B LA-3011

Size Docum e n t N u mb er Re v

Date: Sheet

 

401395

, 2005

of

47 48, 01

A

5

D D

4

3

2

1

U6

945GM

GM@

U41

U41

C C

82573E

82573E@

82562

82562@

ZZZ

PCB ZKU LA-3011 REV0

U13

PCI8412

5

PCI8412@

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

3

2

Size Document Number Rev

B

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-3011





401395

, 01, 2005

1

48 48

A

of

B B

A A