Compal Electronics LA-3011, Satellite M100, Tecra A6 Schematic
A
1 1
2 2
B
C
D
E
Compal confidential
Schematics Document
Mobile Yonah uFCPGA with Intel
Calistoga_PM+ICH7-M core logic
3 3
4 4
A
B
2005-06-01
REV:0.1
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2005/06/01 2006/06/01
Compal Secret Data
Deciphered Date
D
Title
Size Document Number Rev
Custom
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC, M/B LA-3011
401395
05
148, 01, 20
E
of
A
A
B
C
D
E
Compal confidential
Model:HAQAA
NAPA
File Name : LA-3011
1 1
Fan Control
page 4
LCD CONN
page 17
nVIDIA G72/G73
ATI M52/M54
page 18
PCI-E x 16
CRT / TV-OUT
page 16
2 2
10/100/1000 LAN
82562GX/82573E/82573V
page 26,27
RJ45/11 CONN
page 26
Mini Express Card
page 28
PCI-E BUS
(port 1)
PCI BUS
CardBus Controller
TI PCI7412
page 22,23
Mobile Yonah
uFCPGA-479 CPU
FSB
H_A#(3..31)
533/667MHz
Intel Calistoga MCH
945PM
PCBGA 1466
Intel ICH7-M
mBGA-652
page 19,20,21,22
page 4,5,6
page 7,8,9,10,11,12
DMI
H_D#(0..63)
DDR2 -400/533/667
Thermal Sensor
ADM1032AR
page 4
Dual Channel
USB2.0
Clock Generator
ICS9LPRS325AKLFT
page 15
DDR2-SO-DIMM X2
BANK 0, 1, 2, 3
page 13,14
Accelerometer
KXP84-0200
page 28
USB conn x1
(port 6)
(Docking)
page 34
USB2.0 HUB /
(port 0)
FP Conn
USB conn x2
BT Conn
page 38
page 24
page 24
(port 4,5)
(port 7)
USB conn x2
(port 2,3)
(Sub Board)
Azalia
Audio CKT AMP & Audio Jack
ALC861
page 29 page 30
page 24
TPA0232
FingerPrinter UPEK TCS3C/TCD42A
USBx1
MDC1.5
page 37
page 38
3 3
Slot 0
page 23
1394 port
page 22
LED
page 36
RTC CKT.
page 19
TPM1.2
Docking
page 34
Power On/O ff CKT.
page 37
SLB9635TT1.2
page 38
5in1 Slot
page 22
Super I/O
LPC47N217&207
page 33,38
FIR
page 33
LPC BUS
ENE KB910QF
page 25
SATA Master
PATA Slave
SATA HDD Connector
page 19
PATA ODD Connector
page 19
CIR
page 33
DC/DC Interface CKT.
4 4
page 39
Touch Pad Int.KBD
page 37page 37
BIOS
page 35
Power Circuit DC/DC
Page,40,41,42,43,44,45,46
A
B
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2005/06/01 2006/06/01
Compal Secret Data
Deciphered Date
D
Title
Size Document Number Rev
Custom
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC , M / B L A-3011
401395
248¬P , 01, 2005
E
of
A
5
4
3
2
1
Voltage Rails
Power Plane
VIN
D D
C C
B+
+CPU_CORE
+VCCP
+0.9VS
+1.5VS
+1.8V
+2.5VS
+3VALW
+5VALW
+5VS
+RTC_VCC
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
Description
Adapter power supply (18.5V)
AC or battery power rail for power circuit
Core voltage for CPU
1.05V power rail for Processor I/O and MCH/ICH core power
0.9V switched power rail for DDRII Vtt
1.5V switched power rail for PCI-E interface
1.8V power r ail for DDRII
3.3V always on power rail+2.5VALW ON ON ON*
3.3V always on power rail
3.3V switched power rail+3VS
5V always on power rail
5V switched power rail
RTC power ONON
S0-S1
N/A
ON OFF
ON
ON
ON
ON
ON+1.8VS OFF OFF1.8V switched power rail
ON OFF
ON
ON OFF OFF
ON
ON
S5
S3
N/A
N/A
N/A
N/AN/A
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
ON
OFF2.5V switched power rail for MCH video PLL
ON
ON*
ON
ON*
OFF
OFF
ON
Internal PCI Devices
DEVICE
LAN
Azalia D27
USB1.1/2.0
PCI to PCI (DMI to PCI)
AC97 MODEM
AC97 Audio
PATA/SATA
LPC I/F
SMBUS
CPU I/F
B B
Bus
1
0
0
0
0
0
0
0
0
0
0
0
0
PCI Device ID
D8
D28PCI-E
D29
D30
D30
D30
D31
D31
D31
D31 AD15DMA
D31 AD15PMU
IDSEL #
AD24
AD11
AD12
AD13
AD14
AD14
AD14
AD15
AD15
AD15
AD15D31
Board ID / SK U I D T ab l e for AD channel
Vcc 3.3V +/- 5%
Board ID
0
1
2
3
4
5
6
7 NC
100K +/- 1%Ra/Rc/Re
Rb / Rd / Rf V min
0
8.2K +/- 1%
18K +/- 1%
33K +/- 1%
56K +/- 1%
100K +/- 1%
200K +/- 1%
AD_BID
0 V
0.216 V 0.250 V 0.289 V
0.436 V
0.712 V
1.036 V
1.453 V 1.650 V 1.759 V
1.935 V
2.500 V
Vtyp
BOARD ID Table
Board ID
0
1
2
3
4
5
6
7
PCB Revision
0.1
SKU ID Table
SKU ID
0
1
2
3
4
5
6
7
SKU
BTO Option Table
AD_BID
V
AD_BID
0 V 0.100 V
0.503 V
0.819 V
0.538 V
0.875 V
1.185 V 1.264 V
2.200 V
3.300 V
2.341 V
3.300 V
max
External PCI Devices
DEVICE
CARD BUS
PCI Device ID
D6
IDSEL #
AD22
REQ/GNT #
2
PIRQ
ABCD
I2C / SMBUS ADDRESSING
DEVICE
A A
DDR SO-DIMM 0
DDR SO-DIMM 1
CLOCK GENERATOR (EXT.)
5
HEX
A0
A4
D2
ADDRESS
1 0 1 0 0 0 0 0
1 0 1 0 0 1 0 0
1 1 0 1 0 0 1 0
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
4
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/06/01 2006/06/01
BTO Item BOM Structure
VGA
LAN
INT MIC.
DOCKING
CIR
FIR
SUPER I/O
Battery
Compal Secret Data
Deciphered Date
PM@
GM@
82573G@
82573L@
82573@
82562@
45MIC@
WD@
WOD@
CIR@
FIR@
217@
SI207@
45@
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC, M/B LA-3011
401395
348, 01, 2005
1
of
A
5
4
3
2
1
This shall place near CPU
1
2
1000P_0402_50V7K
C371 10U_0805_10V4Z
1000P_0402_50V7K
1
+VCCP
@
C374
@
+
150U_D2_6.3VM
C373
1
2
+3VS
R429
10K_0402_5%
1 2
ACES_85205-0300
1
2
448, 01, 20
JP16
1
2
3
A
of
H_A#[3..31]
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
CLK_CPU_BCLK
CLK_CPU_BCLK#
OCP#
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_ADSTB#0
H_ADSTB#1
H_ADS#
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DRDY#
H_HIT#
H_HITM#
H_IERR#
H_LOCK#
H_RESET#
H_RS#0
H_RS#1
H_RS#2
H_TRDY#
XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
DBRESET#
H_DBSY#
H_DPSLP#
H_DPRSTP#
H_DPWR#
XDP_BPM#4
XDP_BPM#5
H_PROCHOT#
H_PWRGOOD
H_CPUSLP#
XDP_TCK
XDP_TDI
XDP_TDO
TEST1
TEST2
XDP_TMS
XDP_TRST#
H_THERMDA
H_THERMDC
H_THERMTRIP#
D D
H_REQ#[0..4]
H_ADSTB#0
C C
R114
56_0402_5%
1 2
+VCCP
B B
+VCCP
H_THERMDA, H_THERMDC routing together.
Trace width / Spacing = 10 / 10 mil
A A
H_PROCHOT# OCP#
H_ADSTB#1
CLK_CPU_BCLK
CLK_CPU_BCLK#
H_DEFER#
H_RESET#
H_RS#[0..2]
DBRESET#
H_DPSLP#
H_DPRSTP#
H_DPWR#
1 2
56_0402_5%
H_PWRGOOD
H_CPUSLP#
R111 51_0402_5%
1 2
R112 51_0402_5%
1 2
H_THERMTRIP#
+VCCP
12
R118
56_0402_5%@
B
2
E
3 1
C
Q13
MMBT3904_SOT23@
5
H_ADS#
H_BNR#
H_BPRI#
H_BR0#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#
H_DBSY#
R115
JP22A
J4
A3#
L4
A4#
M3
A5#
K5
A6#
M1
A7#
N2
A8#
J1
A9#
N3
A10#
P5
A11#
P2
A12#
L1
A13#
P4
A14#
P1
A15#
R1
A16#
Y2
A17#
U5
A18#
R3
A19#
W6
A20#
U4
A21#
Y5
A22#
U2
A23#
R4
A24#
T5
ADDR GROUP
A25#
T3
A26#
W3
A27#
W5
A28#
Y4
A29#
W2
A30#
Y1
A31#
K3
REQ0#
H2
REQ1#
K2
REQ2#
J3
REQ3#
L5
REQ4#
L2
ADSTB0#
V4
ADSTB1#
A22
BCLK0
A21
H1
E2
G5
F1
H5
F21
G6
E4
D20
H4
B1
F3
F4
G3
G2
AD4
AD3
AD1
AC4
C20
E1
B5
E5
D24
AC2
AC1
D21
D6
D7
AC5
AA6
AB3
C26
D25
AB5
AB6
A24
A25
C7
HOST CLK
BCLK1
ADS#
BNR#
BPRI#
BR0#
DEFER#
DRDY#
HIT#
CONTROL
HITM#
IERR#
LOCK#
RESET#
RS0#
RS1#
RS2#
TRDY#
BPM0#
BPM1#
BPM2#
BPM3#
DBR#
DBSY#
DPSLP#
DPRSTP#
DPWR#
PRDY#
PREQ#
PROCHOT#
PWRGOOD
SLP#
TCK
TDI
TDO
TEST1
TEST2
TMS
TRST#
THERMAL
THERMDA
DIODE
THERMDC
THERMTRIP#
FOX_PZ47903-2741-42_YONAH
H_DPSLP#
1 2
56_0402_5%@
H_DPRSTP#
1 2
56_0402_5%@
YONAH
DATA GROUP
MISC
LEGACY CPU
+VCCP
R117
R110
4
D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#
DINV0#
DINV1#
DINV2#
DINV3#
DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#
A20M#
FERR#
IGNNE#
INIT#
LINT0
LINT1
STPCLK#
SMI#
H_D#0
E22
D0#
H_D#1
F24
D1#
H_D#2
E26
D2#
H_D#3
H22
D3#
H_D#4
F23
D4#
H_D#5
G25
D5#
H_D#6
E25
D6#
H_D#7
E23
D7#
H_D#8
K24
D8#
H_D#9
G24
D9#
H_D#10
J24
H_D#11
J23
H_D#12
H26
H_D#13
F26
H_D#14
K22
H_D#15
H25
H_D#16
N22
H_D#17
K25
H_D#18
P26
H_D#19
R23
H_D#20
L25
H_D#21
L22
H_D#22
L23
H_D#23
M23
H_D#24
P25
H_D#25
P22
H_D#26
P23
H_D#27
T24
H_D#28
R24
H_D#29
L26
H_D#30
T25
H_D#31
N24
H_D#32
AA23
H_D#33
AB24
H_D#34
V24
H_D#35
V26
H_D#36
W25
H_D#37
U23
H_D#38
U25
H_D#39
U22
H_D#40
AB25
H_D#41
W22
H_D#42
Y23
H_D#43
AA26
H_D#44
Y26
H_D#45
Y22
H_D#46
AC26
H_D#47
AA24
H_D#48
AC22
H_D#49
AC23
H_D#50
AB22
H_D#51
AA21
H_D#52
AB21
H_D#53
AC25
H_D#54
AD20
H_D#55
AE22
H_D#56
AF23
H_D#57
AD24
H_D#58
AE21
H_D#59
AD21
H_D#60
AE25
H_D#61
AF25
H_D#62
AF22
H_D#63
AF26
H_DINV#0
J26
H_DINV#1
M26
H_DINV#2
V23
H_DINV#3
AC20
H_DSTBN#0
H23
H_DSTBN#1
M24
H_DSTBN#2
W24
H_DSTBN#3
AD23
H_DSTBP#0
G22
H_DSTBP#1
N25
H_DSTBP#2
Y25
H_DSTBP#3
AE24
H_A20M#
A6
H_FERR#
A5
H_IGNNE#
C4
H_INIT#
B3
H_INTR
C6
H_NMI
B4
H_STPCLK#
D5
H_SMI#
A3
H_D#[0..63]
+3VS
Thermal Sensor ADM1032ARM
1
C148
0.1U_0402_16V4Z
1
C163
2200P_0402_50V7K
EC_SMB_CK2
EC_SMB_DA2
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
H_DSTBN#[0..3]
H_DSTBP#[0..3]
H_A20M#
H_FERR#
H_IGNNE#
H_INIT#
H_INTR
H_NMI
H_STPCLK#
H_SMI#
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/06/01 2006/06/01
THERMDA
2
THERMDC
Compal Secret Data
2
3
8
7
EN_DFAN1
Deciphered Date
U8
D+
ALERT#
D-
THERM#
SCLK
SDATA
ADM1032ARM_RM8
0.01U_0402_25V4Z
C6
+VCCP
2
VDD1
GND
12
R1
150K_0402_5%
2
1
6
4
5
B+
12
3
+IN
2
-IN
5
+IN
6
-IN
R255
1 2
56_0402_5%@
8
P
OUT
U2A
G
LM358A_SO8
4
OUT
U2B
LM358A_SO8
H_PWRGOOD
12
R116
10K_0402_5%@
FAN1_ON
1
R2
1 2
100K_0402_5%
7
H_FERR#
H_SMI#
H_INIT#
H_NMI
H_A20M#
H_INTR
H_IGNNE#
H_STPCLK#
H_CPUSLP#
XDP_TDI
XDP_TMS
XDP_TDO
XDP_BPM#5
XDP_TRST#
XDP_TCK
C212 180P_0402_50V8J@
C159 180P_0402_50V8J@
C145 180P_0402_50V8J@
C160 180P_0402_50V8J@
C161 180P_0402_50V8J@
C144 180P_0402_50V8J@
C139 180P_0402_50V8J@
C137 180P_0402_50V8J@
C134 180P_0402_50V8J@
C138 180P_0402_50V8J@
R79 56_0402_5%
1 2
R77 56_0402_1%
1 2
R76 56_0402_5%
1 2
R75 56_0402_5%
1 2
R80 56_0402_5%
1 2
R78 56_0402_5%
1 2
+5VS
1 2
C362
10U_1206_16V4Z
6
2
1
D
G
S
4 5
FAN1
12
D30
1N4148_SOD80
Q29
SI3456DV-T1_TSOP6
1
2
C372
FAN_SPEED1
@
3
Placement near to ICH7
12
12
12
12
12
12
12
12
12
12
Placement near to CPU side
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC, M/B LA-3011
401395
05
5
4
3
2
1
V_CPU_GTLREF
+VCCP
12
R89
1K_0402_1%
12
R90
2K_0402_1%
+VCC_CORE
R86
100_0402_1%
1 2
R85
100_0402_1%
1 2
VCCSENSE
VSSSENSE
Close to CPU pin
within 500mils.
CPU_BSEL CPU_BSEL2 CPU_BSEL1
133
166
00
0
12
12
R571
54.9_0402_1%
R105
R579
27.4_0402_1%
D D
Close to CPU pin AD26
within 500mils.
C C
B B
Length match within 25 mils
The trace width 18 mils space
7 mils
+1.5VS
1
C143
C141
2
0.01U_0402_16V7K
CPU_BSEL0
1
1
Resistor placed within
0.5" of CPU pin.Trace
should be at least 25
mils away from any
other toggling signal.
12
27.4_0402_1%
1
R96
54.9_0402_1%
12
1
2
10U_0805_10V4Z
VCCSENSE
VSSSENSE
H_PSI#
CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6
V_CPU_GTLREF
CPU_BSEL0
CPU_BSEL1
CPU_BSEL2
+VCC_CORE
+VCCP
VCCSENSE
VSSSENSE
H_PSI#
CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6
CPU_BSEL0
CPU_BSEL1
CPU_BSEL2
COMP0
COMP1
COMP2
COMP3
JP22B
AF7
VCCSENSE
AE7
VSSSENSE
B26
VCCA
K6
VCCP
J6
VCCP
M6
VCCP
N6
VCCP
YONAH
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
PSI#
VID0
VID1
VID2
VID3
VID4
VID5
VID6
GTLREF
BSEL0
BSEL1
BSEL2
COMP0
COMP1
COMP2
COMP3
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
FOX_PZ47903-2741-42_YONAH
W21
AD26
AB20
AA20
AF20
AE20
AB18
AB17
AA18
AA17
AD18
AD17
AC18
AC17
AF18
AF17
T6
R6
K21
J21
M21
N21
T21
R21
V21
V6
G21
AE6
AD6
AF5
AE5
AF4
AE3
AF2
AE2
B22
B23
C21
R26
U26
U1
V1
E7
D2
F6
D3
C1
AF1
D22
C23
C24
AA1
AA4
AB2
AA3
M4
N5
T2
V3
B2
C3
T22
B25
AB26
VSS
AA25
VSS
AD25
VSS
AE26
VSS
AB23
VSS
AC24
VSS
AF24
VSS
AE23
VSS
AA22
VSS
AD22
VSS
AC21
VSS
AF21
VSS
AB19
VSS
AA19
VSS
AD19
VSS
AC19
VSS
AF19
VSS
AE19
VSS
AB16
VSS
AA16
VSS
AD16
VSS
AC16
VSS
AF16
VSS
AE16
VSS
AB13
VSS
AA14
VSS
AD13
VSS
AC14
VSS
AF13
VSS
AE14
VSS
AB11
VSS
AA11
VSS
AD11
VSS
AC11
VSS
AF11
VSS
AE11
VSS
AB8
VSS
AA8
VSS
AD8
VSS
AC8
VSS
AF8
VSS
AE8
VSS
AA5
VSS
AD5
VSS
AC6
VSS
AF6
VSS
AB4
VSS
AC3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AF3
AE4
AB1
AA2
AD2
AE1
B6
C5
F5
E6
H6
J5
M5
L6
P6
R5
V5
U6
Y6
A4
D4
E3
H3
G4
K4
L3
P3
N4
T4
U3
Y3
W4
D1
C2
F2
G1
POWER, GROUNG, RESERVED SIGNALS AND NC
+VCC_CORE
JP22C
AE18
VCC
AE17
VCC
AB15
VCC
AA15
VCC
AD15
VCC
AC15
VCC
AF15
VCC
AE15
VCC
AB14
VCC
AA13
VCC
AD14
VCC
AC13
VCC
AF14
VCC
AE13
VCC
AB12
VCC
AA12
VCC
AD12
VCC
AC12
VCC
AF12
VCC
AE12
VCC
AB10
VCC
AB9
VCC
AA10
VCC
AA9
VCC
AD10
VCC
AD9
VCC
AC10
VCC
AC9
VCC
AF10
VCC
AF9
VCC
AE10
POWER, GROUND
VCC
AE9
VCC
AB7
VCC
AA7
VCC
AD7
VCC
AC7
VCC
B20
VCC
A20
VCC
F20
VCC
E20
VCC
B18
VCC
B17
VCC
A18
VCC
A17
VCC
D18
VCC
D17
VCC
C18
VCC
C17
VCC
F18
VCC
F17
VCC
E18
VCC
E17
VCC
B15
VCC
A15
VCC
D15
VCC
C15
VCC
F15
VCC
E15
VCC
B14
VCC
A13
VCC
D14
VCC
C13
VCC
F14
VCC
E13
VCC
B12
VCC
A12
VCC
D12
VCC
C12
VCC
F12
VCC
E12
VCC
B10
VCC
B9
VCC
A10
VCC
A9
VCC
D10
VCC
D9
VCC
C10
VCC
C9
VCC
F10
VCC
F9
VCC
E10
VCC
E9
VCC
B7
VCC
A7
VCC
F7
VCC
FOX_PZ47903-2741-42_YONAH
YONAH
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
K1
J2
M2
N1
T1
R2
V2
W1
A26
D26
C25
F25
B24
A23
D23
E24
B21
C22
F22
E21
B19
A19
D19
C19
F19
E19
B16
A16
D16
C16
F16
E16
B13
A14
D13
C14
F13
E14
B11
A11
D11
C11
F11
E11
B8
A8
D8
C8
F8
E8
G26
K26
J25
M25
N26
T26
R25
V25
W26
H24
G23
K23
L24
P24
N23
T23
U24
Y24
W23
H21
J22
M22
L21
P21
R22
V22
U21
Y21
A A
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/06/01 2006/06/01
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
2
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC, M/B LA-3011
401395
05
548, 01, 20
1
A
of
5
4
3
2
1
+VCC_CORE
330U_D_2VM
+VCC_CORE
+VCC_CORE
+VCC_CORE
+VCC_CORE
1
+
C172
2
1
C506
22U_0805_6.3V6M
2
1
C107
22U_0805_6.3V6M
2
1
C530
22U_0805_6.3V6M
2
1
C149
22U_0805_6.3V6M
2
@
1
C173
2
330U_D_2VM
+
1
C505
22U_0805_6.3V6M
2
1
C108
22U_0805_6.3V6M
2
1
C529
22U_0805_6.3V6M
2
1
C150
22U_0805_6.3V6M
2
@
330U_D_2VM
1
+
C171
2
1
+
C532
2
330U_D_2VM
1
C504
22U_0805_6.3V6M
2
1
C109
22U_0805_6.3V6M
2
1
C528
22U_0805_6.3V6M
2
1
C151
22U_0805_6.3V6M
2
@
330U_D_2VM
1
+
C129
2
C523
330U_D_2VM
1
C503
22U_0805_6.3V6M
2
1
C110
22U_0805_6.3V6M
2
1
C527
22U_0805_6.3V6M
2
1
C152
22U_0805_6.3V6M
2
@
330U_D_2VM@
1
+
C491
2
1
C502
22U_0805_6.3V6M
2
1
C111
22U_0805_6.3V6M
2
1
C526
22U_0805_6.3V6M
2
@
1
C153
22U_0805_6.3V6M
2
@
North Side Secondary
1
1
+
+
2
C490
330U_D_2VM@
2
1
C501
22U_0805_6.3V6M
2
1
C112
22U_0805_6.3V6M
2
1
C525
22U_0805_6.3V6M
2
@
1
C154
22U_0805_6.3V6M
2
@
1
C115
22U_0805_6.3V6M
2
1
C113
22U_0805_6.3V6M
2
1
C135
22U_0805_6.3V6M
2
@
1
C155
22U_0805_6.3V6M
2
@
1
C116
22U_0805_6.3V6M
2
1
C114
22U_0805_6.3V6M
2
1
C136
22U_0805_6.3V6M
2
@
1
C156
22U_0805_6.3V6M
2
@
ESR <= 1.5m ohm
Capacitor > 1980uF
Mid Frequence Decoupling
D D
Place these capacitors on L8
(North side,Secondary Layer)
Place these capacitors on L8
(North side,Secondary Layer)
Place these capacitors on L8
(Sorth side,Secondary Layer)
C C
Place these capacitors on L8
(Sorth side,Secondary Layer)
South Side Secondary
B B
+VCCP
1
1
+
C522
330U_D2E_2.5VM_R9
@
A A
+
C531
2
2
1
C513
0.1U_0402_16V4Z
2
330U_D2E_2.5VM_R9
1
C515
0.1U_0402_16V4Z
2
1
C517
0.1U_0402_16V4Z
2
1
C512
0.1U_0402_16V4Z
2
1
C514
0.1U_0402_16V4Z
2
1
C516
0.1U_0402_16V4Z
2
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
Place these inside
socket cavity on L8
(North side
Secondary)
2005/06/01 2006/06/01
Compal Secret Data
Deciphered Date
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC, M/B LA-3011
401395
05
648, 01, 20
1
of
A
5
4
3
2
1
H_D#[0..63]
D D
C C
+VCCP
12
12
R82
R81
54.9_0402_1%
H_XSCOMP/H_YSCOMP trace
L
width and spacing is 5/20.
B B
A A
54.9_0402_1%
H_VREF
H_XRCOMP
H_XSCOMP
H_YRCOMP
H_YSCOMP
H_SWNG0
H_SWNG1
12
12
R73
R72
24.9_0402_1%
24.9_0402_1%
Layout Note:
H_XRCOMP / H_YRCOMP / H_VREF / H_SWNG0 /
H_SWNG1 trace width and spacing is 18/20.
+VCCP
12
R517
100_0402_1%
H_VREF
12
1
R518
C473
2
200_0402_1%
0.1U_0402_16V4Z
5
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
U6A
F1
HD0#
J1
HD1#
H1
HD2#
J6
HD3#
H3
HD4#
K2
HD5#
G1
HD6#
G2
HD7#
K9
HD8#
K1
HD9#
K7
HD10#
J8
HD11#
H4
HD12#
J3
HD13#
K11
HD14#
G4
HD15#
T10
HD16#
W11
HD17#
T3
HD18#
U7
HD19#
U9
HD20#
U11
HD21#
T11
HD22#
W9
HD23#
T1
HD24#
T8
HD25#
T4
HD26#
W7
HD27#
U5
HD28#
T9
HD29#
W6
HD30#
T5
HD31#
AB7
HD32#
AA9
HD33#
W4
HD34#
W3
HD35#
Y3
HD36#
Y7
HD37#
W5
HD38#
Y10
HD39#
AB8
HD40#
W2
HD41#
AA4
HD42#
AA7
HD43#
AA2
HD44#
AA6
HD45#
AA10
HD46#
Y8
HD47#
AA1
HD48#
AB4
HD49#
AC9
HD50#
AB11
HD51#
AC11
HD52#
AB3
HD53#
AC2
HD54#
AD1
HD55#
AD9
HD56#
AC1
HD57#
AD7
HD58#
AC6
HD59#
AB5
HD60#
AD10
HD61#
AD4
HD62#
AC8
HD63#
J13
HVREF0
K13
HVREF1
E1
HXRCOMP
E2
HXSCOMP
Y1
HYRCOMP
U1
HYSCOMP
E4
HXSWING
W1
HYSWING
CALISTOGA_FCBGA1466~D
PM@
H9
HA3#
C9
HA4#
E11
HA5#
G11
HA6#
F11
HA7#
G12
HA8#
F9
HA9#
H11
HA10#
J12
HA11#
G14
HA12#
D9
HA13#
J14
HA14#
H13
HA15#
J15
HA16#
F14
HA17#
D12
HA18#
A11
HA19#
C11
HA20#
A12
HA21#
A13
HA22#
E13
HA23#
G13
HA24#
F12
HA25#
B12
HA26#
B14
HA27#
C12
HA28#
A14
HA29#
C14
HA30#
D14
HA31#
D8
HREQ#0
G8
HREQ#1
B8
HREQ#2
F8
HREQ#3
A8
HREQ#4
B9
HADSTB#0
C13
HADSTB#1
HCLKN
HCLKP
HDSTBN#0
HDSTBN#1
HDSTBN#2
HDSTBN#3
HDSTBP#0
HDSTBP#1
HDSTBP#2
HDSTBP#3
HDINV#0
HDINV#1
HDINV#2
HDINV#3
HCPURST#
HADS#
HTRDY#
HDPWR#
HDRDY#
HDEFER#
HHITM#
HHIT#
HLOCK#
HBREQ0#
HBNR#
HBPRI#
HDBSY#
HCPUSLP#
HRS0#
HRS1#
HRS2#
12
R557
12
R549
AG1
AG2
K4
T7
Y5
AC4
K3
T6
AA5
AC5
J7
W8
U3
AB10
B7
E8
E7
J9
H8
C3
D4
D3
B3
C7
C6
F6
A7
E3
B4
E6
D6
221_0603_1%
100_0402_1%
HOST
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_ADSTB#0
H_ADSTB#1
CLK_MCH_BCLK#
CLK_MCH_BCLK
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
H_RESET#
H_ADS#
H_TRDY#
H_DPWR#
H_DRDY#
H_DEFER#
H_HITM#
H_HIT#
H_LOCK#
H_BR0#
H_BNR#
H_BPRI#
H_DBSY#
H_CPUSLP#
H_RS#0
H_RS#1
H_RS#2
H_SWNG0
1
C482
2
0.1U_0402_16V4Z
4
+VCCP+VCCP
R87
R84
12
221_0603_1%
12
100_0402_1%
H_A#[3..31]
H_REQ#[0..4]
H_ADSTB#0
H_ADSTB#1
CLK_MCH_BCLK#
CLK_MCH_BCLK
H_DSTBN#[0..3]
H_DSTBP#[0..3]
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
H_RESET#
H_ADS#
H_TRDY#
H_DPWR#
H_DRDY#
H_DEFER#
H_HITM#
H_HIT#
H_LOCK#
H_BR0#
H_BNR#
H_BPRI#
H_DBSY#
H_CPUSLP#
H_RS#[0..2]
H_SWNG1
1
C100
2
0.1U_0402_16V4Z
U6B
AE35
DMIRXN0
AF39
DMIRXN1
AG35
DMIRXN2
AH39
DMIRXN3
AC35
DMIRXP0
AE39
DMIRXP1
AF35
DMIRXP2
AG39
DMIRXP3
AE37
DMITXN0
AF41
DMITXN1
AG37
DMITXN2
AH41
DMITXN3
AC37
DMITXP0
AE41
DMITXP1
AF37
DMITXP2
AG41
DMITXP3
AY35
SM_CK0
AR1
SM_CK1
AW7
SM_CK2
AW40
SM_CK3
AW35
SM_CK0#
AT1
SM_CK1#
AY7
SM_CK2#
AY40
SM_CK3#
AU20
SM_CKE0
AT20
SM_CKE1
BA29
SM_CKE2
AY29
SM_CKE3
AW13
SM_CS0#
AW12
SM_CS1#
AY21
SM_CS2#
AW21
SM_CS3#
AL20
SM_OCDCOMP0
AF10
SM_OCDCOMP1
BA13
SM_ODT0
BA12
SM_ODT1
AY20
SM_ODT2
AU21
SM_ODT3
AV9
SM_RCOMPN
AT9
SM_RCOMPP
AK1
SM_VREF0
AK41
SM_VREF1
G28
PM_BMBUSY#
F25
PM_EXTTS0#
H26
PM_EXTTS1#
G6
PM_THERMTRIP#
AH33
PWROK
AH34
RSTIN#
K28
ICH_SYNC#
CALISTOGA_FCBGA1466~D
PM@
Layout Note:
Route as short
as possible
12
R503
R519
40.2_0402_1%
40.2_0402_1%
12
DMI
DDR MUXING
M_OCDOCMP0
M_OCDOCMP1
DPRSLPVR
V_DDR_MCH_REF
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3
M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3
DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB
DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#
+1.8V
R520 80.6_0402_1%
R515 80.6_0402_1%
R495 0_0402_5%
PLT_RST#
M_ODT0
M_ODT1
M_ODT2
M_ODT3
1 2
1 2
V_DDR_MCH_REF
PM_BMBUSY#
1 2
H_THERMTRIP#
@
R40 100_0402_1%
MCH_ICH_SYNC#
Layout Note:
V_DDR_MCH_REF
trace width and
spacing is 20/20.
V_DDR_MCH_REF
1
C101
2
0.1U_0402_16V4Z
PWROK
+1.8V
12
R83
12
R74
12
100_0402_1%
100_0402_1%
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3
M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3
DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB
DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#
M_OCDOCMP0
M_OCDOCMP1
M_ODT0
M_ODT1
M_ODT2
M_ODT3
SMRCOMPN
SMRCOMPP
PM_BMBUSY#
PM_EXTTS#0
PM_EXTTS#1
H_THERMTRIP#
PWROK
PLTRST_R#
Stuff R531 & R532 for A1 Calistoga
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/06/01 2006/06/01
Compal Secret Data
Deciphered Date
2
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG
CFG17
CFG18
CFG19
CFG20
G_CLKP
G_CLKN
D_REF_CLKN
D_REF_CLKP
CLKNC
D_REF_SSCLKN
D_REF_SSCLKP
CLK_REQ#
NC0
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18
RESERVED1
RESERVED2
PM
RESERVED3
RESERVED4
RESERVED5
RESERVED6
RESERVED7
RESERVED8
RESERVED9
RESERVED10
RESERVED11
RESERVED12
RESERVED13
RESERVED
PM_EXTTS#0
PM_EXTTS#1
Title
SCHEMATIC, M/B LA-3011
Size Document Number Rev
Date: Sheet
Description at page11.
MCH_CLKSEL0
K16
MCH_CLKSEL1
K18
MCH_CLKSEL2
J18
CFG3
F18
CFG4
E15
CFG5
F15
CFG6
E18
CFG7
D19
CFG8
D16
CFG9
G16
CFG10
E16
CFG11
D15
CFG12
G15
CFG13
K15
CFG14
C15
CFG15
H16
CFG16
G18
CFG17
H15
CFG18
J25
CFG19
K27
CFG20
J26
CLK_MCH_3GPLL
AG33
CLK_MCH_3GPLL#
AF33
GMCH_A27
A27
GMCH_A26
A26
GMCH_C40
C40
GMCH_D41
D41
MCH_CLKREQ#
H32
A3
A39
A4
A40
AW1
AW41
AY1
BA1
BA2
BA3
BA39
BA40
BA41
C1
AY41
B2
B41
C41
D1
T32
R32
F3
F7
AG11
AF11
H7
J19
A41
A34
D28
D27
A35
R481
10K_0402_5%
R494
10K_0402_5%
@
@
@
@
@
@
@
@
12
12
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
+3VS
MCH_CLKSEL0
MCH_CLKSEL1
MCH_CLKSEL2
T16
T20
CFG5
T14
CFG7
T18
CFG9
T17
CFG11
CFG12
CFG13
T21
T15
CFG16
T22
CFG18
CFG19
CFG20
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
CLK_MCH_DREFCLK#
CLK_MCH_DREFCLK
MCH_SSCDREFCLK#
MCH_SSCDREFCLK
MCH_CLKREQ#
Compal Electronics, Inc.
401395
05
748, 01, 20
1
A
of
5
D D
4
3
2
1
DDR_A_BS#0
DDR_A_BS#1
DDR_A_BS#2
DDR_A_DM[0..7]
DDR_A_DQS[0..7]
C C
DDR_A_DQS#[0..7]
DDR_A_MA[0..13]
B B
DDR_A_CAS#
DDR_A_RAS#
DDR_A_WE#
T7 PAD
T6 PAD
DDR_A_BS#0
DDR_A_BS#1
DDR_A_BS#2
DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11 DDR_B_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_CAS#
DDR_A_RAS#
DDR_A_WE#
SA_RCVENIN#
SA_RCVENOUT#
U6D
AU12
SA_BS0
AV14
SA_BS1
BA20
SA_BS2
AJ33
SA_DM0
AM35
SA_DM1
AL26
SA_DM2
AN22
SA_DM3
AM14
SA_DM4
AL9
SA_DM5
AR3
SA_DM6
AH4
SA_DM7
AK33
SA_DQS0
AT33
SA_DQS1
AN28
SA_DQS2
AM22
SA_DQS3
AN12
SA_DQS4
AN8
SA_DQS5
AP3
SA_DQS6
AG5
SA_DQS7
AK32
SA_DQS0#
AU33
SA_DQS1#
AN27
SA_DQS2#
AM21
SA_DQS3#
AM12
SA_DQS4#
AL8
SA_DQS5#
AN3
SA_DQS6#
AH5
SA_DQS7#
AY16
SA_MA0
AU14
SA_MA1
AW16
SA_MA2
BA16
SA_MA3
BA17
SA_MA4
AU16
SA_MA5
AV17
SA_MA6
AU17
SA_MA7
AW17
SA_MA8
AT16
SA_MA9
AU13
SA_MA10
AT17
SA_MA11
AV20
SA_MA12
AV12
SA_MA13
AY13
SA_CAS#
AW14
SA_RAS#
AY14
SA_WE#
AK23
SA_RCVENIN#
AK24
SA_RCVENOUT#
CALISTOGA_FCBGA1466~D
PM@
SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
DDR SYS MEMORY A
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63
AJ35
AJ34
AM31
AM33
AJ36
AK35
AJ32
AH31
AN35
AP33
AR31
AP31
AN38
AM36
AM34
AN33
AK26
AL27
AM26
AN24
AK28
AL28
AM24
AP26
AP23
AL22
AP21
AN20
AL23
AP24
AP20
AT21
AR12
AR14
AP13
AP12
AT13
AT12
AL14
AL12
AK9
AN7
AK8
AK7
AP9
AN9
AT5
AL5
AY2
AW2
AP1
AN2
AV2
AT3
AN1
AL2
AG7
AF9
AG4
AF6
AG9
AH6
AF4
AF8
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
DDR_A_D[0..63] DDR_B_D[0..63]
DDR_B_BS#0
DDR_B_BS#1
DDR_B_BS#2
DDR_B_DM[0..7]
DDR_B_DQS[0..7]
DDR_B_DQS#[0..7]
DDR_B_MA[0..13]
DDR_B_CAS#
DDR_B_RAS#
DDR_B_WE#
T19 PAD
T13 PAD
DDR_B_BS#0
DDR_B_BS#1
DDR_B_BS#2
DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6DDR_A_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA12
DDR_B_MA13
DDR_B_CAS#
DDR_B_RAS#
DDR_B_WE#
SB_RCVENIN#
SB_RCVENOUT#
U6E
AT24
SB_BS0
AV23
SB_BS1
AY28
SB_BS2
AK36
SB_DM0
AR38
SB_DM1
AT36
SB_DM2
BA31
SB_DM3
AL17
SB_DM4
AH8
SB_DM5
BA5
SB_DM6
AN4
SB_DM7
AM39
SB_DQS0
AT39
SB_DQS1
AU35
SB_DQS2
AR29
SB_DQS3
AR16
SB_DQS4
AR10
SB_DQS5
AR7
SB_DQS6
AN5
SB_DQS7
AM40
SB_DQS0#
AU39
SB_DQS1#
AT35
SB_DQS2#
AP29
SB_DQS3#
AP16
SB_DQS4#
AT10
SB_DQS5#
AT7
SB_DQS6#
AP5
SB_DQS7#
AY23
SB_MA0
AW24
SB_MA1
AY24
SB_MA2
AR28
SB_MA3
AT27
SB_MA4
AT28
SB_MA5
AU27
SB_MA6
AV28
SB_MA7
AV27
SB_MA8
AW27
SB_MA9
AV24
SB_MA10
BA27
SB_MA11
AY27
SB_MA12
AR23
SB_MA13
AR24
SB_CAS#
AU23
SB_RAS#
AR27
SB_WE#
AK16
SB_RCVENIN#
AK18
SB_RCVENOUT#
CALISTOGA_FCBGA1466~D
PM@
AK39
SB_DQ0
AJ37
SB_DQ1
AP39
SB_DQ2
AR41
SB_DQ3
AJ38
SB_DQ4
AK38
SB_DQ5
AN41
SB_DQ6
AP41
SB_DQ7
AT40
SB_DQ8
AV41
SB_DQ9
AU38
SB_DQ10
AV38
SB_DQ11
AP38
SB_DQ12
AR40
SB_DQ13
AW38
SB_DQ14
AY38
SB_DQ15
BA38
SB_DQ16
AV36
SB_DQ17
AR36
SB_DQ18
AP36
SB_DQ19
BA36
SB_DQ20
AU36
SB_DQ21
AP35
SB_DQ22
AP34
SB_DQ23
AY33
SB_DQ24
BA33
SB_DQ25
AT31
SB_DQ26
AU29
SB_DQ27
AU31
SB_DQ28
AW31
SB_DQ29
AV29
SB_DQ30
AW29
SB_DQ31
AM19
SB_DQ32
AL19
SB_DQ33
AP14
SB_DQ34
AN14
SB_DQ35
AN17
SB_DQ36
AM16
SB_DQ37
AP15
SB_DQ38
AL15
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63
AJ11
AH10
AJ9
AN10
AK13
AH11
AK10
AJ8
BA10
AW10
BA4
AW4
AY10
AY9
AW5
AY5
AV4
AR5
AK4
AK3
AT4
AK5
AJ5
AJ3
DDR SYS MEMORY B
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
A A
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/06/01 2006/06/01
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
2
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC, M/B LA-3011
401395
05
848, 01, 20
1
A
of
5
4
3
2
1
PCIE_MTX_C_GRX_N[0..15]
PCIE_MTX_C_GRX_P[0..15]
PCIE_GTX_C_MRX_N[0..15]
D D
+3VS
GM@
R56 2.2K_0402_5%
R57 2.2K_0402_5%
R483 2.2K_0402_5%
R60 2.2K_0402_5%
R480 10K_0402_5%
R478 10K_0402_5%
R484 100K_0402_5%
C C
B B
R55 1.5K_0402_1%
R69 75_0402_1%
R68 150_0402_1%
R67 150_0402_1%
R8 100K_0402_5%
GM@
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
12
12
LDDC_CLK
LDDC_DATA
GMCH_CRT_CLK
GMCH_CRT_DATA
LCTLB_DATA
LCTLA_CLK
GMCH_ENBKL
LIBG
GMCH_TV_COMPS
GMCH_TV_LUMA
GMCH_TV_CRMA
GMCH_ENVDD
GMCH_CRT_R
GMCH_CRT_G
GMCH_CRT_B
GMCH_TV_LUMA
GMCH_TV_CRMA
GMCH_TXOUT0+
GMCH_TXOUT1+
GMCH_TXOUT2+
GMCH_TXOUT0GMCH_TXOUT1GMCH_TXOUT2-
GMCH_TZOUT0+
GMCH_TZOUT1+
GMCH_TZOUT2+
GMCH_TZOUT0GMCH_TZOUT1GMCH_TZOUT2-
GMCH_TXCLK+
GMCH_TXCLKGMCH_TZCLK+
GMCH_TZCLK-
GMCH_ENBKL
GMCH_LCD_CLK
GMCH_LCD_DATA
GMCH_ENVDD
GMCH_TV_COMPS
GMCH_TV_LUMA
GMCH_TV_CRMA
R504 4.99K_0402_1%
GMCH_CRT_CLK
GMCH_CRT_DATA
GMCH_CRT_VSYNC
GMCH_CRT_HSYNC
12
GM@
GM@
GM@
12
12
12
R493 150_0402_5%
R498 150_0402_5%
R502 150_0402_5%
GMCH_TXOUT0+
GMCH_TXOUT1+
GMCH_TXOUT2+
GMCH_TXOUT0GMCH_TXOUT1GMCH_TXOUT2-
GMCH_TZOUT0+
GMCH_TZOUT1+
GMCH_TZOUT2+
GMCH_TZOUT0GMCH_TZOUT1GMCH_TZOUT2-
GMCH_TXCLK+
GMCH_TXCLKGMCH_TZCLK+
GMCH_TZCLK-
GMCH_ENBKL
LCTLA_CLK
LCTLB_DATA
LDDC_CLK
LDDC_DATA
GMCH_ENVDD
LIBG
TV_REFSET
R505 0_0402_5%
GMCH_CRT_CLK
GMCH_CRT_DATA
12
1 2
R499 255_0402_1%
U6C
H27
SDVOCTRL_DATA
H28
SDVOCTRL_CLK
B37
LA_DATA0
B34
LA_DATA1
A36
LA_DATA2
C37
LA_DATA#0
B35
LA_DATA#1
A37
LA_DATA#2
F30
LB_DATA0
D29
LB_DATA1
F28
LB_DATA2
G30
LB_DATA#0
D30
LB_DATA#1
F29
LB_DATA#2
A32
LA_CLK
A33
LA_CLK#
E26
LB_CLK
E27
LB_CLK#
D32
LBKLT_CTL
J30
LBKLT_EN
H30
LCTLA_CLK
H29
LCTLB_DATA
G26
LDDC_CLK
G25
LDDC_DATA
F32
LVDD_EN
B38
LIBG
C35
LVBG
C33
LVREFH
C32
LVREFL
A16
TVDAC_A
C18
TVDAC_B
A19
TVDAC_C
J20
TV_IREF
B16
TV_IRTNA
B18
TV_IRTNB
B19
TV_IRTNC
J29
TV_DCONSEL1
K30
TV_DCONSEL0
C26
DDCCLK
C25
DDCDATA
H23
VSYNC
G23
HSYNC
E23
BLUE
D23
BLUE#
C22
GREEN
B22
GREEN#
A21
RED
B21
RED#
J22
CRT_IREF
CALISTOGA_FCBGA1466~D
PM@
LVDS
TV CRT
PCI-EXPRESS GRAPHICS
PCIE_GTX_C_MRX_P[0..15]
PEGCOMP tr ace width
L
and spacing is 18/25 mils.
D40
EXP_COMPI
EXP_RXN0
EXP_RXN1
EXP_RXN2
EXP_RXN3
EXP_RXN4
EXP_RXN5
EXP_RXN6
EXP_RXN7
EXP_RXN8
EXP_RXN9
EXP_RXN10
EXP_RXN11
EXP_RXN12
EXP_RXN13
EXP_RXN14
EXP_RXN15
EXP_RXP0
EXP_RXP1
EXP_RXP2
EXP_RXP3
EXP_RXP4
EXP_RXP5
EXP_RXP6
EXP_RXP7
EXP_RXP8
EXP_RXP9
EXP_RXP10
EXP_RXP11
EXP_RXP12
EXP_RXP13
EXP_RXP14
EXP_RXP15
EXP_TXN0
EXP_TXN1
EXP_TXN2
EXP_TXN3
EXP_TXN4
EXP_TXN5
EXP_TXN6
EXP_TXN7
EXP_TXN8
EXP_TXN9
EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15
EXP_TXP0
EXP_TXP1
EXP_TXP2
EXP_TXP3
EXP_TXP4
EXP_TXP5
EXP_TXP6
EXP_TXP7
EXP_TXP8
EXP_TXP9
EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15
D38
F34
G38
H34
J38
L34
M38
N34
P38
R34
T38
V34
W38
Y34
AA38
AB34
AC38
D34
F38
G34
H38
J34
L38
M34
N38
P34
R38
T34
V38
W34
Y38
AA34
AB38
F36
G40
H36
J40
L36
M40
N36
P40
R36
T40
V36
W40
Y36
AA40
AB36
AC40
D36
F40
G36
H40
J36
L40
M36
N40
P36
R40
T36
V40
W36
Y40
AA36
AB40
EXP_COMPO
PEGCOMP
PCEI_GTX_C_MRX_N0
PCEI_GTX_C_MRX_N1
PCEI_GTX_C_MRX_N2
PCEI_GTX_C_MRX_N3
PCEI_GTX_C_MRX_N4
PCEI_GTX_C_MRX_N5
PCEI_GTX_C_MRX_N6
PCEI_GTX_C_MRX_N7
PCEI_GTX_C_MRX_N8
PCEI_GTX_C_MRX_N9
PCEI_GTX_C_MRX_N10
PCEI_GTX_C_MRX_N11
PCEI_GTX_C_MRX_N12
PCEI_GTX_C_MRX_N13
PCEI_GTX_C_MRX_N14
PCEI_GTX_C_MRX_N15
PCEI_GTX_C_MRX_P0
PCEI_GTX_C_MRX_P1
PCEI_GTX_C_MRX_P2
PCEI_GTX_C_MRX_P3
PCEI_GTX_C_MRX_P4
PCEI_GTX_C_MRX_P5
PCEI_GTX_C_MRX_P6
PCEI_GTX_C_MRX_P7
PCEI_GTX_C_MRX_P8
PCEI_GTX_C_MRX_P9
PCEI_GTX_C_MRX_P10
PCEI_GTX_C_MRX_P11
PCEI_GTX_C_MRX_P12
PCEI_GTX_C_MRX_P13
PCEI_GTX_C_MRX_P14
PCEI_GTX_C_MRX_P15
PCIE_MTX_C_GRX_N[0..15]
PCIE_MTX_C_GRX_P[0..15]
PCEI_GTX_C_MRX_N[0..15]
PCEI_GTX_C_MRX_P[0..15]
R472
24.9_0402_1%
1 2
C400 0.1U_0402_16V7KPM@
C36 0.1U_0402_16V7KPM@
C384 0.1U_0402_16V7KPM@
C25 0.1U_0402_16V7KPM@
C398 0.1U_0402_16V7KPM@
C38 0.1U_0402_16V7KPM@
C382 0.1U_0402_16V7KPM@
C27 0.1U_0402_16V7KPM@
C396 0.1U_0402_16V7KPM@
C40 0.1U_0402_16V7KPM@
C380 0.1U_0402_16V7KPM@
C29 0.1U_0402_16V7KPM@
C394 0.1U_0402_16V7KPM@
C42 0.1U_0402_16V7KPM@
C387 0.1U_0402_16V7KPM@
C31 0.1U_0402_16V7KPM@
C401 0.1U_0402_16V7KPM@
C35 0.1U_0402_16V7KPM@
C385 0.1U_0402_16V7KPM@
C24 0.1U_0402_16V7KPM@
C399 0.1U_0402_16V7KPM@
C37 0.1U_0402_16V7KPM@
C383 0.1U_0402_16V7KPM@
C26 0.1U_0402_16V7KPM@
C397 0.1U_0402_16V7KPM@
C39 0.1U_0402_16V7KPM@
C381 0.1U_0402_16V7KPM@
C28 0.1U_0402_16V7KPM@
C395 0.1U_0402_16V7KPM@
C41 0.1U_0402_16V7KPM@
C388 0.1U_0402_16V7KPM@
C30 0.1U_0402_16V7KPM@
+1.5VS_PCIE
PCIE_MTX_C_GRX_N0
PCIE_MTX_C_GRX_N1
PCIE_MTX_C_GRX_N2
PCIE_MTX_C_GRX_N3
PCIE_MTX_C_GRX_N4
PCIE_MTX_C_GRX_N5
PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_N7
PCIE_MTX_C_GRX_N8
PCIE_MTX_C_GRX_N9
PCIE_MTX_C_GRX_N10
PCIE_MTX_C_GRX_N11
PCIE_MTX_C_GRX_N12
PCIE_MTX_C_GRX_N13
PCIE_MTX_C_GRX_N14
PCIE_MTX_C_GRX_N15
PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_P13
PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_P15
A A
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/06/01 2006/06/01
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
2
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC, M/B LA-3011
401395
05
948, 01, 20
1
A
of
5
4
3
2
1
R508
0_0805_5%
C460
0.1U_0402_16V4Z
R41
1 2
0.5_0805_1%
1
C34
2
1
C484
2
0.1U_0402_16V4Z
1
+
C417
2
0.1U_0402_16V4Z~D
GM@
Deciphered Date
+2.5VS
1
2
12
1
C416
2
0.1U_0402_16V4Z
C418
1
2
0.1U_0402_16V4Z
1
C55
2
1
C427
2
0.1U_0402_16V4Z
1
2
2200P_0402_50V7K
C430
0.1U_0402_16V4Z
0_0805_5%
C57
0.1U_0402_16V4Z
R62
12
1
2
PCI-E/MEM/FSB PLL decoupling
R550
0_0805_5%
1
C483
10U_0805_6.3V6M
2
R470
0_0805_5%
1
C419
2
330U_D2E_2.5VM_R9
R42
0_0805_5%
12
12
2
+1.5VS+1.5VS_3GPLL
12
C44
+1.5VS
+1.5VS_TVDAC +1.5VS
0.022U_0402_16V7K
1
2
0.1U_0402_16V4Z
@
1
C462
2
+1.5VS_HPLL
1
C493
2
Title
Size Document Number Rev
Date: Sheet
0_0805_5%
1
C449
2
10U_0805_6.3V6M
@
R560
0_0805_5%
1
C494
10U_0805_6.3V6M
2
0.1U_0402_16V4Z
1
2
Compal Electronics, Inc.
SCHEMATIC , M / B L A-3011
R58
C441
C464
2200P_0402_50V7K
1
+
2
0.1U_0402_16V4Z~D
GM@
401395
1
C465
2
12
12
R59
0_0805_5%
C434
330U_D2E_2.5VM_R9
R511
0_0805_5%
0.1U_0402_16V4Z
1
C53
0.022U_0402_16V7K
2
+1.5VS+1.5VS
12
1
12
+1.5VS
+3VS+3VS_TVDACA+3VS+3VS_TVDACB+3VS+3VS_TVDACC
A
of
10 48¬P , 01, 2005
D D
1
+
C497
C425
5
2
1
C480
2
4.7U_0805_10V4Z
1
2
0.22U_0603_10V7K
C511
C438
1
2
330U_D2E_2.5VM_R9
C C
B B
A A
1
+
2
1
2
2.2U_0805_16V4Z
MCH_A6
1
C93
2
MCH_D2
C102
0.22U_0603_10V7K
C103
+1.5VS
+VCCP
330U_D2E_2.5VM_R9
@
0.47U_0603_10V7K
MCH_AB1
1
2
0.47U_0603_10V7K
U6H
AC14
VTT0
AB14
VTT1
W14
VTT2
V14
VTT3
T14
VTT4
R14
VTT5
P14
VTT6
N14
VTT7
M14
VTT8
L14
VTT9
AD13
VTT10
AC13
VTT11
AB13
VTT12
AA13
VTT13
Y13
VTT14
W13
VTT15
V13
VTT16
U13
VTT17
T13
VTT18
R13
VTT19
N13
VTT20
M13
VTT21
L13
VTT22
AB12
VTT23
AA12
VTT24
Y12
VTT25
W12
VTT26
V12
VTT27
U12
VTT28
T12
VTT29
R12
VTT30
P12
VTT31
N12
VTT32
M12
VTT33
L12
VTT34
R11
VTT35
P11
VTT36
N11
VTT37
M11
VTT38
R10
VTT39
P10
VTT40
N10
VTT41
M10
VTT42
P9
VTT43
N9
VTT44
M9
VTT45
R8
VTT46
P8
VTT47
N8
VTT48
M8
VTT49
P7
VTT50
N7
VTT51
M7
VTT52
R6
VTT53
P6
VTT54
M6
VTT55
A6
VTT56
R5
VTT57
P5
VTT58
N5
VTT59
M5
VTT60
P4
VTT61
N4
VTT62
M4
VTT63
R3
VTT64
P3
VTT65
N3
VTT66
M3
VTT67
R2
VTT68
P2
VTT69
M2
VTT70
D2
VTT71
AB1
VTT72
R1
VTT73
P1
VTT74
N1
VTT75
M1
VTT76
AG14
VCCAUX32
AF14
VCCAUX33
AE14
VCCAUX34
Y14
VCCAUX35
AF13
VCCAUX36
AE13
VCCAUX37
AF12
VCCAUX38
AE12
VCCAUX39
AD12
VCCAUX40
CALISTOGA_FCBGA1466~D
PM@
P O W E R
VCCTX_LVDS0
VCCTX_LVDS1
VCCTX_LVDS2
VCCA_CRTDAC0
VCCA_CRTDAC1
VSSA_CRTDAC2
VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1
VCCD_HMPLL0
VCCD_HMPLL1
VCCDQ_TVDAC
4
VCC_SYNC
VCC3G0
VCC3G1
VCC3G2
VCC3G3
VCC3G4
VCC3G5
VCC3G6
VCCA_3GPLL
VCCA_3GBG
VSSA_3GBG
VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL
VCCA_LVDS
VSSA_LVDS
VCCA_MPLL
VCCA_TVBG
VSSA_TVBG
VCCD_LVDS0
VCCD_LVDS1
VCCD_LVDS2
VCCD_TVDAC
VCCHV0
VCCHV1
VCCHV2
VCCAUX0
VCCAUX1
VCCAUX2
VCCAUX3
VCCAUX4
VCCAUX5
VCCAUX6
VCCAUX7
VCCAUX8
VCCAUX9
VCCAUX10
VCCAUX11
VCCAUX12
VCCAUX13
VCCAUX14
VCCAUX15
VCCAUX16
VCCAUX17
VCCAUX18
VCCAUX19
VCCAUX20
VCCAUX21
VCCAUX22
VCCAUX23
VCCAUX24
VCCAUX25
VCCAUX26
VCCAUX27
VCCAUX28
VCCAUX29
VCCAUX30
VCCAUX31
H22
B30
C30
A30
AB41
AJ41
L41
N41
R41
V41
Y41
AC33
G41
H41
E21
F21
G21
B26
C39
AF1
A38
B39
AF2
H20
G20
E19
F19
C20
D20
E20
F20
AH1
AH2
A28
B28
C28
D21
H19
A23
B23
B25
AK31
AF31
AE31
AC31
AL30
AK30
AJ30
AH30
AG30
AF30
AE30
AD30
AC30
AG29
AF29
AE29
AD29
AC29
AG28
AF28
AE28
AH22
AJ21
AH21
AJ20
AH20
AH19
P19
P16
AH15
P15
AH14
+2.5VS
+2.5VS
W=40 mils
+1.5VS_3GPLL
+2.5VS
+2.5VS_CRTDAC
+1.5VS_DPLLA
+1.5VS_DPLLB
+1.5VS_HPLL
+2.5VS
+1.5VS_MPLL
+3VS_TVBG
+3VS_TVDACA
+3VS_TVDACB
+3VS_TVDACC
+1.5VS
+1.5VS_TVDAC
+1.5VS
1
C470
2
220U_D2_4VM
@
1
2
C450
0.1U_0402_16V4Z
1
+
C23
2
220U_D2_4VM
1
2
+1.5VS_PCIE
10U_0805_6.3V6M
1
1
+
C379
2
2
L14 BLM11A601S_0603
1 2
1
C457
C456
2
2200P_0402_50V7K
+3VS
1
C453
10U_0805_6.3V6M
2
0.1U_0402_16V4Z
C405
R467
0_0805_5%
C406
1
10U_0805_6.3V6M
2
+2.5VS
12
+1.5VS
1
1
C461
2
2
2200P_0402_50V7K
1
C43
2
0.1U_0402_16V4Z
10U_0805_6.3V6M
+1.5VS_MPLL
45mA Max. 45mA Max.
0.1U_0402_16V4Z
+3VS+3VS_TVBG
R70
12
0_0805_5%
1
1
C77
2
2
C81
0.1U_0402_16V4Z
2200P_0402_50V7K
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/06/01 2006/06/01
+1.5VS_DPLLB +1.5VS_DPLLA
40mA Max. 40mA Max.
Compal Secret Data
5
4
3
2
1
Strap Pin Table
CFG[3:17] have internal pull up
+VCCP
D D
1
1
1
C475
C467
C454
2
0.22U_0603_10V7K
10U_0805_6.3V6M
1
C485
C466
2
10U_0805_6.3V6M
C C
C99
330U_D2E_2.5VM_R9
@
C495
330U_D2E_2.5VM_R9
B B
2
2
0.22U_0603_10V7K
0.22U_0603_10V7K
1
1
C435
2
2
1U_0603_10V4Z
330U_D2E_2.5VM_R9
1
1
+
+
C492
2
2
1
+
2
+VCCP
U6F
AD27
VCC_NCTF0
AC27
VCC_NCTF1
AB27
VCC_NCTF2
AA27
VCC_NCTF3
Y27
VCC_NCTF4
W27
VCC_NCTF5
V27
VCC_NCTF6
U27
VCC_NCTF7
T27
VCC_NCTF8
R27
VCC_NCTF9
AD26
VCC_NCTF10
AC26
VCC_NCTF11
AB26
VCC_NCTF12
AA26
VCC_NCTF13
Y26
VCC_NCTF14
W26
VCC_NCTF15
V26
VCC_NCTF16
U26
VCC_NCTF17
T26
VCC_NCTF18
R26
VCC_NCTF19
AD25
VCC_NCTF20
AC25
VCC_NCTF21
AB25
VCC_NCTF22
AA25
VCC_NCTF23
Y25
VCC_NCTF24
W25
VCC_NCTF25
V25
VCC_NCTF26
U25
VCC_NCTF27
T25
VCC_NCTF28
R25
VCC_NCTF29
AD24
VCC_NCTF30
AC24
VCC_NCTF31
AB24
VCC_NCTF32
AA24
VCC_NCTF33
Y24
VCC_NCTF34
W24
VCC_NCTF35
V24
VCC_NCTF36
U24
VCC_NCTF37
T24
VCC_NCTF38
R24
VCC_NCTF39
AD23
VCC_NCTF40
V23
VCC_NCTF41
U23
VCC_NCTF42
T23
VCC_NCTF43
R23
VCC_NCTF44
AD22
VCC_NCTF45
V22
VCC_NCTF46
U22
VCC_NCTF47
T22
VCC_NCTF48
R22
VCC_NCTF49
AD21
VCC_NCTF50
V21
VCC_NCTF51
U21
VCC_NCTF52
T21
VCC_NCTF53
R21
VCC_NCTF54
AD20
VCC_NCTF55
V20
VCC_NCTF56
U20
VCC_NCTF57
T20
VCC_NCTF58
R20
VCC_NCTF59
AD19
VCC_NCTF60
V19
VCC_NCTF61
U19
VCC_NCTF62
T19
VCC_NCTF63
AD18
VCC_NCTF64
AC18
VCC_NCTF65
AB18
VCC_NCTF66
AA18
VCC_NCTF67
Y18
VCC_NCTF68
W18
VCC_NCTF69
V18
VCC_NCTF70
U18
VCC_NCTF71
T18
VCC_NCTF72
M19
VCC100
L19
VCC101
N18
VCC102
M18
VCC103
L18
VCC104
P17
VCC105
N17
VCC106
M17
VCC107
N16
VCC108
M16
VCC109
L16
VCC110
CALISTOGA_FCBGA1466~D
PM@
VCCAUX_NCTF0
VCCAUX_NCTF1
VCCAUX_NCTF2
VCCAUX_NCTF3
VCCAUX_NCTF4
VCCAUX_NCTF5
VCCAUX_NCTF6
VCCAUX_NCTF7
VCCAUX_NCTF8
VCCAUX_NCTF9
VCCAUX_NCTF10
VCCAUX_NCTF11
VCCAUX_NCTF12
VCCAUX_NCTF13
VCCAUX_NCTF14
VCCAUX_NCTF15
VCCAUX_NCTF16
VCCAUX_NCTF17
VCCAUX_NCTF18
VCCAUX_NCTF19
VCCAUX_NCTF20
VCCAUX_NCTF21
VCCAUX_NCTF22
VCCAUX_NCTF23
VCCAUX_NCTF24
VCCAUX_NCTF25
VCCAUX_NCTF26
VCCAUX_NCTF27
VCCAUX_NCTF28
VCCAUX_NCTF29
VCCAUX_NCTF30
VCCAUX_NCTF31
VCCAUX_NCTF32
VCCAUX_NCTF33
VCCAUX_NCTF34
VCCAUX_NCTF35
VCCAUX_NCTF36
P O W E R
VCCAUX_NCTF37
VCCAUX_NCTF38
VCCAUX_NCTF39
VCCAUX_NCTF40
VCCAUX_NCTF41
VCCAUX_NCTF42
VCCAUX_NCTF43
VCCAUX_NCTF44
VCCAUX_NCTF45
VCCAUX_NCTF46
VCCAUX_NCTF47
VCCAUX_NCTF48
VCCAUX_NCTF49
VCCAUX_NCTF50
VCCAUX_NCTF51
VCCAUX_NCTF52
VCCAUX_NCTF53
VCCAUX_NCTF54
VCCAUX_NCTF55
VCCAUX_NCTF56
VCCAUX_NCTF57
VSS_NCTF0
VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
VSS_NCTF8
VSS_NCTF9
VSS_NCTF10
VSS_NCTF11
VSS_NCTF12
VCC_SM100
VCC_SM101
VCC_SM102
VCC_SM103
VCC_SM104
VCC_SM105
VCC_SM106
VCC_SM107
AG27
AF27
AG26
AF26
AG25
AF25
AG24
AF24
AG23
AF23
AG22
AF22
AG21
AF21
AG20
AF20
AG19
AF19
R19
AG18
AF18
R18
AG17
AF17
AE17
AD17
AB17
AA17
W17
V17
T17
R17
AG16
AF16
AE16
AD16
AC16
AB16
AA16
Y16
W16
V16
U16
T16
R16
AG15
AF15
AE15
AD15
AC15
AB15
AA15
Y15
W15
V15
U15
T15
R15
AE27
AE26
AE25
AE24
AE23
AE22
AE21
AE20
AE19
AE18
AC17
Y17
U17
AR6
AP6
AN6
AL6
AK6
AJ6
AV1
AJ1
+1.5VS
VCCSM_LF2
VCCSM_LF1
C104
+1.8V
0.47U_0603_10V7K
1
1
C105
2
2
0.47U_0603_10V7K
Place near pin AV1 & AJ1
A A
+VCCP
AA33
AA32
AA31
AA30
AA29
AB28
AA28
AB23
AA23
AC22
AB22
AC21
AA21
AC20
AB20
AB19
AA19
U6G
VCC0
W33
VCC1
P33
VCC2
N33
VCC3
L33
VCC4
J33
VCC5
VCC6
Y32
VCC7
W32
VCC8
V32
VCC9
P32
VCC10
N32
VCC11
M32
VCC12
L32
VCC13
J32
VCC14
VCC15
W31
VCC16
V31
VCC17
T31
VCC18
R31
VCC19
P31
VCC20
N31
VCC21
M31
VCC22
VCC23
Y30
VCC24
W30
VCC25
V30
VCC26
U30
VCC27
T30
VCC28
R30
VCC29
P30
VCC30
N30
VCC31
M30
VCC32
P O W E R
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75
VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC82
VCC83
VCC84
VCC85
VCC86
VCC87
VCC88
VCC89
VCC90
VCC91
VCC92
VCC93
VCC94
VCC95
VCC96
VCC97
VCC98
VCC99
CALISTOGA_FCBGA1466~D
PM@
W29
W22
W21
W20
L30
Y29
V29
U29
R29
P29
M29
L29
Y28
V28
U28
T28
R28
P28
N28
M28
L28
P27
N27
M27
L27
P26
N26
L26
N25
M25
L25
P24
N24
M24
Y23
P23
N23
M23
L23
Y22
P22
N22
M22
L22
N21
M21
L21
Y20
P20
N20
M20
L20
Y19
N19
VCC_SM0
VCC_SM1
VCC_SM2
VCC_SM3
VCC_SM4
VCC_SM5
VCC_SM6
VCC_SM7
VCC_SM8
VCC_SM9
VCC_SM10
VCC_SM11
VCC_SM12
VCC_SM13
VCC_SM14
VCC_SM15
VCC_SM16
VCC_SM17
VCC_SM18
VCC_SM19
VCC_SM20
VCC_SM21
VCC_SM22
VCC_SM23
VCC_SM24
VCC_SM25
VCC_SM26
VCC_SM27
VCC_SM28
VCC_SM29
VCC_SM30
VCC_SM31
VCC_SM32
VCC_SM33
VCC_SM34
VCC_SM35
VCC_SM36
VCC_SM37
VCC_SM38
VCC_SM39
VCC_SM40
VCC_SM41
VCC_SM42
VCC_SM43
VCC_SM44
VCC_SM45
VCC_SM46
VCC_SM47
VCC_SM48
VCC_SM49
VCC_SM50
VCC_SM51
VCC_SM52
VCC_SM53
VCC_SM54
VCC_SM55
VCC_SM56
VCC_SM57
VCC_SM58
VCC_SM59
VCC_SM60
VCC_SM61
VCC_SM62
VCC_SM63
VCC_SM64
VCC_SM65
VCC_SM66
VCC_SM67
VCC_SM68
VCC_SM69
VCC_SM70
VCC_SM71
VCC_SM72
VCC_SM73
VCC_SM74
VCC_SM75
VCC_SM76
VCC_SM77
VCC_SM78
VCC_SM79
VCC_SM80
VCC_SM81
VCC_SM82
VCC_SM83
VCC_SM84
VCC_SM85
VCC_SM86
VCC_SM87
VCC_SM88
VCC_SM89
VCC_SM90
VCC_SM91
VCC_SM92
VCC_SM93
VCC_SM94
VCC_SM95
VCC_SM96
VCC_SM97
VCC_SM98
VCC_SM99
AU41
AT41
AM41
AU40
BA34
AY34
AW34
AV34
AU34
AT34
AR34
BA30
AY30
AW30
AV30
AU30
AT30
AR30
AP30
AN30
AM30
AM29
AL29
AK29
AJ29
AH29
AJ28
AH28
AJ27
AH27
BA26
AY26
AW26
AV26
AU26
AT26
AR26
AJ26
AH26
AJ25
AH25
AJ24
AH24
BA23
AJ23
BA22
AY22
AW22
AV22
AU22
AT22
AR22
AP22
AK22
AJ22
AK21
AK20
BA19
AY19
AW19
AV19
AU19
AT19
AR19
AP19
AK19
AJ19
AJ18
AJ17
AH17
AJ16
AH16
BA15
AY15
AW15
AV15
AU15
AT15
AR15
AJ15
AJ14
AJ13
AH13
AK12
AJ12
AH12
AG12
AK11
BA8
AY8
AW8
AV8
AT8
AR8
AP8
BA6
AY6
AW6
AV6
AT6
+1.8V
VCCSM_LF4
VCCSM_LF5
C32
0.47U_0603_10V7K
Place near pin AT41 & AM41
C424
C54
0.47U_0603_10V7K
Place near pin BA23
C92
10U_0805_6.3V6M
C71
0.47U_0603_10V7K
Place near pin BA15
1
2
1
2
1
2
1
2
1
2
C33
0.47U_0603_10V7K
0.1U_0402_16V4Z
C52
1
2
1
C481
2
0.1U_0402_16V4Z
1
2
10U_0805_6.3V6M
CFG[2:0]
CFG5
CFG7
CFG9
CFG11
CFG[13:12]
+1.8V
CFG16
1
1
C452
C431
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
CFG18
CFG19
SDVO_CTRLDATA
CFG20
(PCIE/SDVO select)
CFG[19:18] have internal pull down
011 = 667MT/s FSB
001 = 533MT/s FSB
0 = DMI x 2
1 = DMI x 4
0 = Reserved
1 = Mobile Yonah CPU
0 = Lane Reversal Enable
1 = Normal Operation
0 = Calistoga
(According to Intel Napa Schematic Checklist & CRB
Rev1.301 document 2.2Kohm pull-down resistor
request)
1 = Reserved
00 = Reserved
01 = XOR Mode Enabled
10 = All Z Mode Enabled
11 = Normal Operation
0 = Dynamic ODT Disabled
1 = Dynamic ODT Enabled (Default)
0 = 1.05V
1 = 1.5V
0 = Normal Operation
1 = DMI Lane Reversal Enable
0 = No SDVO Device Present
(Default)
(Default)
*
*
(Default)
*
(Default)
*
(Default)
*
*
1 = SDVO Device Present
0 = Only PCIE or SDVO is
operational.
1 = PCIE/SDVO are operating
simu.
CFG5
CFG7
CFG9
CFG11
CFG12
CFG13
CFG16
CFG18
CFG19
CFG20
R513 2.2K_0402_5%@
R507 2.2K_0402_5%@
R509 2.2K_0402_5%@
R514 2.2K_0402_5%
R512 2.2K_0402_5%@
R510 2.2K_0402_5%@
R506 2.2K_0402_5%@
R479 1K_0402_5%@
R482 1K_0402_5%@
R490 1K_0402_5%@
*
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
(Default)
*
(Default)
*
(Default)
*
+3VS
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/06/01 2006/06/01
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
2
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC, M/B LA-3011
401395
05
11 48, 01, 20
1
A
of
5
4
3
2
1
U6I
AC41
VSS0
AA41
VSS1
W41
VSS2
T41
VSS3
P41
VSS4
M41
D D
C C
B B
A A
VSS5
J41
VSS6
F41
VSS7
AV40
VSS8
AP40
VSS9
AN40
VSS10
AK40
VSS11
AJ40
VSS12
AH40
VSS13
AG40
VSS14
AF40
VSS15
AE40
VSS16
B40
VSS17
AY39
VSS18
AW39
VSS19
AV39
VSS20
AR39
VSS21
AN39
VSS22
AJ39
VSS23
AC39
VSS24
AB39
VSS25
AA39
VSS26
Y39
VSS27
W39
VSS28
V39
VSS29
T39
VSS30
R39
VSS31
P39
VSS32
N39
VSS33
M39
VSS34
L39
VSS35
J39
VSS36
H39
VSS37
G39
VSS38
F39
VSS39
D39
VSS40
AT38
VSS41
AM38
VSS42
AH38
VSS43
AG38
VSS44
AF38
VSS45
AE38
VSS46
C38
VSS47
AK37
VSS48
AH37
VSS49
AB37
VSS50
AA37
VSS51
Y37
VSS52
W37
VSS53
V37
VSS54
T37
VSS55
R37
VSS56
P37
VSS57
N37
VSS58
M37
VSS59
L37
VSS60
J37
VSS61
H37
VSS62
G37
VSS63
F37
VSS64
D37
VSS65
AY36
VSS66
AW36
VSS67
AN36
VSS68
AH36
VSS69
AG36
VSS70
AF36
VSS71
AE36
VSS72
AC36
VSS73
C36
VSS74
B36
VSS75
BA35
VSS76
AV35
VSS77
AR35
VSS78
AH35
VSS79
AB35
VSS80
AA35
VSS81
Y35
VSS82
W35
VSS83
V35
VSS84
T35
VSS85
R35
VSS86
P35
VSS87
N35
VSS88
M35
VSS89
L35
VSS90
J35
VSS91
H35
VSS92
G35
VSS93
F35
VSS94
D35
VSS95
AN34
VSS96
AK34
VSS97
AG34
VSS98
AF34
VSS99
CALISTOGA_FCBGA1466~D
PM@
P O W E R
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
AE34
AC34
C34
AW33
AV33
AR33
AE33
AB33
Y33
V33
T33
R33
M33
H33
G33
F33
D33
B33
AH32
AG32
AF32
AE32
AC32
AB32
G32
B32
AY31
AV31
AN31
AJ31
AG31
AB31
Y31
AB30
E30
AT29
AN29
AB29
T29
N29
K29
G29
E29
C29
B29
A29
BA28
AW28
AU28
AP28
AM28
AD28
AC28
W28
J28
E28
AP27
AM27
AK27
J27
G27
F27
C27
B27
AN26
M26
K26
F26
D26
AK25
P25
K25
H25
E25
D25
A25
BA24
AU24
AL24
AW23
AT23
AN23
AM23
AH23
AC23
W23
K23
J23
F23
C23
AA22
K22
G22
F22
E22
D22
A22
BA21
AV21
AR21
U6J
AN21
VSS200
AL21
VSS201
AB21
VSS202
Y21
VSS203
P21
VSS204
K21
VSS205
J21
VSS206
H21
VSS207
C21
VSS208
AW20
VSS209
AR20
VSS210
AM20
VSS211
AA20
VSS212
K20
VSS213
B20
VSS214
A20
VSS215
AN19
VSS216
AC19
VSS217
W19
VSS218
K19
VSS219
G19
VSS220
C19
VSS221
AH18
VSS222
P18
VSS223
H18
VSS224
D18
VSS225
A18
VSS226
AY17
VSS227
AR17
VSS228
AP17
VSS229
AM17
VSS230
AK17
VSS231
AV16
VSS232
AN16
VSS233
AL16
VSS234
J16
VSS235
F16
VSS236
C16
VSS237
AN15
VSS238
AM15
VSS239
AK15
VSS240
N15
VSS241
M15
VSS242
L15
VSS243
B15
VSS244
A15
VSS245
BA14
VSS246
AT14
VSS247
AK14
VSS248
AD14
VSS249
AA14
VSS250
U14
VSS251
K14
VSS252
H14
VSS253
E14
VSS254
AV13
VSS255
AR13
VSS256
AN13
VSS257
AM13
VSS258
AL13
VSS259
AG13
VSS260
P13
VSS261
F13
VSS262
D13
VSS265
B13
VSS264
AY12
VSS263
AC12
VSS266
K12
VSS267
H12
VSS268
E12
VSS269
AD11
VSS270
AA11
VSS271
Y11
VSS272
J11
VSS273
D11
VSS274
B11
VSS275
AV10
VSS276
AP10
VSS277
AL10
VSS278
AJ10
VSS279
CALISTOGA_FCBGA1466~D
PM@
P O W E R
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
VSS286
VSS287
VSS288
VSS289
VSS290
VSS292
VSS291
VSS293
VSS294
VSS295
VSS296
VSS297
VSS298
VSS299
VSS300
VSS301
VSS302
VSS303
VSS304
VSS305
VSS306
VSS307
VSS308
VSS309
VSS310
VSS311
VSS312
VSS313
VSS314
VSS315
VSS316
VSS317
VSS318
VSS319
VSS320
VSS321
VSS322
VSS323
VSS324
VSS325
VSS326
VSS327
VSS328
VSS329
VSS330
VSS331
VSS332
VSS333
VSS334
VSS335
VSS336
VSS337
VSS338
VSS339
VSS340
VSS341
VSS342
VSS343
VSS344
VSS345
VSS346
VSS347
VSS348
VSS349
VSS350
VSS351
VSS352
VSS353
VSS354
VSS355
VSS356
VSS357
VSS358
VSS359
VSS360
AG10
AC10
W10
U10
BA9
AW9
AR9
AH9
AB9
Y9
R9
G9
E9
A9
AG8
AD8
AA8
U8
K8
C8
BA7
AV7
AP7
AL7
AJ7
AH7
AF7
AC7
R7
G7
D7
AG6
AD6
AB6
Y6
U6
N6
K6
H6
B6
AV5
AF5
AD5
AY4
AR4
AP4
AL4
AJ4
Y4
U4
R4
J4
F4
C4
AY3
AW3
AV3
AL3
AH3
AG3
AF3
AD3
AC3
AA3
G3
AT2
AR2
AP2
AK2
AJ2
AD2
AB2
Y2
U2
T2
N2
J2
H2
F2
C2
AL1
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/06/01 2006/06/01
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
2
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC, M/B LA-3011
401395
05
12 48, 01, 20
1
A
of
5
DDR_A_DQS#[0..7]
DDR_A_D[0..63]
DDR_A_DM[0..7]
DDR_A_DQS[0..7]
DDR_A_MA[0..13]
D D
Layout Note:
Place near JP27
+1.8V
2.2U_0805_16V4Z
2.2U_0805_16V4Z
C C
Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS
+0.9VS
0.1U_0402_16V4Z
B B
DDR_A_MA5
DDR_A_MA8
DDR_A_MA1
DDR_A_MA3
DDR_A_RAS#
DDR_CS0_DIMMA#
DDR_A_BS#0
DDR_A_MA10
DDR_A_CAS#
A A
DDR_A_WE#
DDR_CS1_DIMMA#
M_ODT1
C95
C59
1
1
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C62
C70
RP34
1 4
2 3
RP35
1 4
2 3
RP17
1 4
2 3
RP36
1 4
2 3
RP37
1 4
2 3
RP38
2 3
1 4
5
2.2U_0805_16V4Z
2.2U_0805_16V4Z
C72
1
2
0.1U_0402_16V4Z
1
1
2
2
C73
C79
+0.9VS
56_0404_4P2R_5%
56_0404_4P2R_5%
56_0404_4P2R_5%
56_0404_4P2R_5%
56_0404_4P2R_5%
56_0404_4P2R_5%
C56
1
2
0.1U_0402_16V4Z
1
2
C85
0.1U_0402_16V4Z
2.2U_0805_16V4Z
C89
1
1
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C463
C91
RP32 56_0404_4P2R_5%
DDR_A_BS#2
14
DDR_CKE0_DIMMA
23
RP8 56_0404_4P2R_5%
DDR_A_MA7
14
DDR_A_MA6
23
RP33 56_0404_4P2R_5%
DDR_A_MA9
14
DDR_A_MA12
23
RP11 56_0404_4P2R_5%
DDR_A_MA4
14
DDR_A_MA2
23
RP14 56_0404_4P2R_5%
DDR_A_MA0
14
DDR_A_BS#1
23
RP20 56_0404_4P2R_5%
M_ODT0
14
DDR_A_MA13
23
RP5 56_0404_4P2R_5%
DDR_CKE1_DIMMA
14
DDR_A_MA11
23
0.1U_0402_16V4Z
C65
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
C468
4
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C64
1
1
2
2
0.1U_0402_16V4Z
1
1
2
2
C474
C476
Layout Note:
Place these resistor
closely JP27,all
trace length Max=1.5"
C78
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C477
C478
C87
0.1U_0402_16V4Z
1
2
C472
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
4
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
DDR_CKE0_DIMMA
DDR_A_BS#2
DDR_A_BS#0
DDR_A_WE#
DDR_A_CAS#
DDR_CS1_DIMMA#
M_ODT1
CLK_SMBDATA
CLK_SMBCLK
3
2
+1.8V
JP19
1
VREF
3
DDR_A_D0
DDR_A_D4
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D2
DDR_A_D3
DDR_A_D8
DDR_A_D14
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D10
DDR_A_D11
DDR_A_D21
DDR_A_D17
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D22
DDR_A_D19 DDR_A_D23
DDR_A_D25
DDR_A_D24
DDR_A_DM3
DDR_A_D27
DDR_A_D30
DDR_CKE0_DIMMA
DDR_A_BS#2
DDR_A_MA12
DDR_A_MA9 DDR_A_MA7
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#
DDR_A_CAS#
DDR_CS1_DIMMA#
M_ODT1
DDR_A_D34
DDR_A_D38
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D39
DDR_A_D35
DDR_A_D45
DDR_A_D41
DDR_A_DM5
DDR_A_D42
DDR_A_D43
DDR_A_D52
DDR_A_D53
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D55
DDR_A_D56
DDR_A_D61
DDR_A_DM7
DDR_A_D58
DDR_A_D59
CLK_SMBDATA
CLK_SMBCLK
+3VS
1
C126
0.1U_0402_16V4Z
2005/06/01 2006/06/01
2
Compal Secret Data
VSS
5
DQ0
7
DQ1
9
VSS
11
DQS0#
13
DQS0
15
VSS
17
DQ2
19
DQ3
21
VSS
23
DQ8
25
DQ9
27
VSS
29
DQS1#
31
DQS1
33
VSS
35
DQ10
37
DQ11
39
VSS
41
VSS
43
DQ16
45
DQ17
47
VSS
49
DQS2#
51
DQS2
53
VSS
55
DQ18
57
DQ19
59
VSS
61
DQ24
63
DQ25
65
VSS
67
DM3
69
NC
71
VSS
73
DQ26
75
DQ27
77
VSS
79
CKE0
81
VDD
83
NC
85
BA2
87
VDD
89
A12
91
A9
93
A8
95
VDD
97
A5
99
A3
101
A1
103
VDD
105
A10/AP
107
BA0
109
WE#
111
VDD
113
CAS#
115
NC/S1#
117
VDD
119
NC/ODT1
121
VSS
123
DQ32
125
DQ33
127
VSS
129
DQS4#
131
DQS4
133
VSS
135
DQ34
137
DQ35
139
VSS
141
DQ40
143
DQ41
145
VSS
147
DM5
149
VSS
151
DQ42
153
DQ43
155
VSS
157
DQ48
159
DQ49
161
VSS
163
NC,TEST
165
VSS
167
DQS6#
169
DQS6
171
VSS
173
DQ50
175
DQ51
177
VSS
179
DQ56
181
DQ57
183
VSS
185
DM7
187
VSS
189
DQ58
191
DQ59
193
VSS
195
SDA
197
SCL
199
VDDSPD
PTI_A5652D-A0G16-P
SO-DIMM A
Deciphered Date
DQ4
DQ5
DM0
DQ6
DQ7
DQ12
DQ13
DM1
CK0#
DQ14
DQ15
DQ20
DQ21
DM2
DQ22
DQ23
DQ28
DQ29
DQS3#
DQS3
DQ30
DQ31
NC/CKE1
VDD
NC/A15
NC/A14
VDD
VDD
VDD
RAS#
VDD
ODT0
NC/A13
VDD
DQ36
DQ37
DM4
DQ38
DQ39
DQ44
DQ45
DQS5#
DQS5
DQ46
DQ47
DQ52
DQ53
CK1#
DM6
DQ54
DQ55
DQ60
DQ61
DQS7#
DQS7
DQ62
DQ63
SAO
VSS
VSS
VSS
VSS
VSS
VSS
CK0
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A11
BA1
S0#
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
CK1
VSS
VSS
VSS
VSS
VSS
VSS
SA1
NC
NC
2
+1.8V
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
A7
94
A6
96
98
A4
100
A2
102
A0
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
R104
V_DDR_MCH_REF
DDR_A_D7
DDR_A_D1
DDR_A_DM0
DDR_A_D5
DDR_A_D6
DDR_A_D12
DDR_A_D13
DDR_A_DM1
M_CLK_DDR0
M_CLK_DDR#0
DDR_A_D9
DDR_A_D15
DDR_A_D20
DDR_A_D16
DDR_A_DM2
DDR_A_D18
DDR_A_D29
DDR_A_D28
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D26
DDR_A_D31
DDR_CKE1_DIMMA
DDR_A_MA11
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
DDR_A_BS#1
DDR_A_RAS#
DDR_CS0_DIMMA#
M_ODT0
DDR_A_MA13
DDR_A_D36
DDR_A_D33
DDR_A_DM4
DDR_A_D37
DDR_A_D32
DDR_A_D40
DDR_A_D44
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D47
DDR_A_D46
DDR_A_D48
DDR_A_D49
M_CLK_DDR1
M_CLK_DDR#1
DDR_A_DM6
DDR_A_D50DDR_A_D51
DDR_A_D54
DDR_A_D60
DDR_A_D57
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
12
12
R101
10K_0402_5%
10K_0402_5%
1
C17
V_DDR_MCH_REF
1
of
13 48, 01, 20
0.1U_0402_16V4Z
2.2U_0805_16V4Z
C11
1
1
2
2
M_CLK_DDR0
M_CLK_DDR#0
DDR_CKE1_DIMMA
DDR_A_BS#1
DDR_A_RAS#
DDR_CS0_DIMMA#
M_ODT0
M_CLK_DDR1
M_CLK_DDR#1
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC, M/B LA-3011
401395
05
A
5
DDR_B_DQS#[0..7]
DDR_B_D[0..63]
DDR_B_DM[0..7]
DDR_B_DQS[0..7]
DDR_B_MA[0..13]
D D
C C
B B
A A
Layout Note:
Place near JP26
+1.8V
2.2U_0805_16V4Z
2.2U_0805_16V4Z
C60
1
2
Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS
+0.9VS
0.1U_0402_16V4Z
1
2
C61
DDR_B_MA1
DDR_B_MA3
DDR_B_BS#0
DDR_B_MA10
DDR_B_MA0
DDR_B_BS#1
DDR_B_RAS#
DDR_CS2_DIMMB#
DDR_B_CAS#
DDR_B_WE#
DDR_CS3_DIMMB# M_ODT2
M_ODT3
0.1U_0402_16V4Z
C58
1
2
0.1U_0402_16V4Z
1
2
C68
RP15
RP18
RP16
RP19
RP21
RP23
5
2.2U_0805_16V4Z
C97
1
2
0.1U_0402_16V4Z
1
2
C76
1 4
2 3
56_0404_4P2R_5%
1 4
2 3
56_0404_4P2R_5%
1 4
2 3
56_0404_4P2R_5%
1 4
2 3
56_0404_4P2R_5%
1 4
2 3
56_0404_4P2R_5%
2 3
1 4
56_0404_4P2R_5%
1
2
C83
2.2U_0805_16V4Z
+0.9VS
C94
1
2
0.1U_0402_16V4Z
1
2
C88
2.2U_0805_16V4Z
C84
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
C96
RP10 56_0404_4P2R_5%
14
23
RP6 56_0404_4P2R_5%
14
23
RP13 56_0404_4P2R_5%
14
23
RP9 56_0404_4P2R_5%
14
23
RP12 56_0404_4P2R_5%
14
23
RP22 56_0404_4P2R_5%
14
23
RP7
14
23
56_0404_4P2R_5%
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C67
1
2
0.1U_0402_16V4Z
1
1
2
2
C63
C69
DDR_B_MA9
DDR_B_MA12
5/16
DDR_B_MA7
DDR_CKE3_DIMMB
DDR_B_MA5
DDR_B_MA8
5/16
DDR_B_MA6
DDR_B_MA11
DDR_B_MA4
DDR_B_MA2
DDR_B_MA13
DDR_B_BS#2
DDR_CKE2_DIMMB
0.1U_0402_16V4Z
C75
1
2
0.1U_0402_16V4Z
1
2
C74
0.1U_0402_16V4Z
C66
1
1
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C86
C80
Layout Note:
Place these resistor
closely JP26,all
trace length Max=1.5"
4
C82
1
+
2
220U_D2_4VM
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
C90
C415
1
+
C106
2
220U_D2_4VM
1
2
C98
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
4
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
DDR_CKE2_DIMMB
DDR_B_BS#2
DDR_B_BS#0
DDR_B_WE#
DDR_B_CAS#
DDR_CS3_DIMMB#
M_ODT3
CLK_SMBDATA
CLK_SMBCLK
3
2
+1.8V
JP20
1
VREF
3
DDR_B_D0
DDR_B_D5
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_D7
DDR_B_D3
DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D11
DDR_B_D20
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_DM3
DDR_B_D30
DDR_B_D31
DDR_CKE2_DIMMB
DDR_B_BS#2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
DDR_B_MA10
DDR_B_BS#0
DDR_B_WE#
DDR_B_CAS#
DDR_CS3_DIMMB#
M_ODT3
DDR_B_D37
DDR_B_D36
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D35
DDR_B_D34
DDR_B_D40
DDR_B_D41
DDR_B_DM5
DDR_B_D42
DDR_B_D47
DDR_B_D48
DDR_B_D53
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D51
DDR_B_D50
DDR_B_D60
DDR_B_D61
DDR_B_DM7
DDR_B_D58
DDR_B_D59
CLK_SMBDATA
CLK_SMBCLK
+3VS
1
C127
0.1U_0402_16V4Z
2005/06/01 2006/06/01
2
Compal Secret Data
VSS
5
DQ0
7
DQ1
9
VSS
11
DQS0#
13
DQS0
15
VSS
17
DQ2
19
DQ3
21
VSS
23
DQ8
25
DQ9
27
VSS
29
DQS1#
31
DQS1
33
VSS
35
DQ10
37
DQ11
39
VSS
41
VSS
43
DQ16
45
DQ17
47
VSS
49
DQS2#
51
DQS2
53
VSS
55
DQ18
57
DQ19
59
VSS
61
DQ24
63
DQ25
65
VSS
67
DM3
69
NC
71
VSS
73
DQ26
75
DQ27
77
VSS
79
CKE0
81
VDD
83
NC
85
BA2
87
VDD
89
A12
91
A9
93
A8
95
VDD
97
A5
99
A3
101
A1
103
VDD
105
A10/AP
107
BA0
109
WE#
111
VDD
113
CAS#
115
NC/S1#
117
VDD
119
NC/ODT1
121
VSS
123
DQ32
125
DQ33
127
VSS
129
DQS4#
131
DQS4
133
VSS
135
DQ34
137
DQ35
139
VSS
141
DQ40
143
DQ41
145
VSS
147
DM5
149
VSS
151
DQ42
153
DQ43
155
VSS
157
DQ48
159
DQ49
161
VSS
163
NC,TEST
165
VSS
167
DQS6#
169
DQS6
171
VSS
173
DQ50
175
DQ51
177
VSS
179
DQ56
181
DQ57
183
VSS
185
DM7
187
VSS
189
DQ58
191
DQ59
193
VSS
195
SDA
197
SCL
199
VDDSPD
P-TWO_A5692B-A0G16-P
SO-DIMM B
Deciphered Date
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
VDD
VDD
RAS#
VDD
ODT0
NC/A13
VDD
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
NC
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
A11
92
A7
94
A6
96
98
A4
100
A2
102
A0
104
106
BA1
108
110
S0#
112
114
116
118
120
NC
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
SA1
2
+1.8V
V_DDR_MCH_REF
DDR_B_D4
DDR_B_D1
DDR_B_DM0
DDR_B_D6
DDR_B_D2
DDR_B_D12
DDR_B_D13
DDR_B_DM1
M_CLK_DDR3
M_CLK_DDR#3
DDR_B_D14
DDR_B_D15
DDR_B_D16DDR_B_D21
DDR_B_D18
DDR_B_DM2
DDR_B_D17
DDR_B_D19
DDR_B_D26
DDR_B_D28
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D29
DDR_B_D27
DDR_CKE3_DIMMB
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
DDR_B_BS#1
DDR_B_RAS#
DDR_CS2_DIMMB#
M_ODT2
DDR_B_MA13
DDR_B_D33
DDR_B_D32
DDR_B_DM4
DDR_B_D38
DDR_B_D39
DDR_B_D44
DDR_B_D45
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D43
DDR_B_D46
DDR_B_D49
DDR_B_D52
M_CLK_DDR2
M_CLK_DDR#2
DDR_B_DM6
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
1
V_DDR_MCH_REF
0.1U_0402_16V4Z
2.2U_0805_16V4Z
M_CLK_DDR3
M_CLK_DDR#3
DDR_CKE3_DIMMB
DDR_B_BS#1
DDR_B_RAS#
DDR_CS2_DIMMB#
M_ODT2
M_CLK_DDR2
M_CLK_DDR#2
R106
1 2
10K_0402_5%
12
10K_0402_5%
R103
Title
SCHEMATIC, M/B LA-3011
Size Document Number Rev
Date: Sheet
1
1
C18
C12
2
2
+3VS
Compal Electronics, Inc.
401395
05
1
A
of
14 48, 01, 20
5
+CK_VDD_MAIN1
1 2
+3VS
R235 0_0805_5%
1 2
+3VS
+3VS
CPU_BSEL0
CPU_BSEL1
FSC
CPU_BSEL2
R239
10K_0402_5%@
CLK_ENABLE#
R222
300_0402_5%
J10
NO SHORT PADS
R129 0_0805_5%
R127
1 2
0_0805_5%
R602
8.2K_0402_5%
FSA
1 2
R603
0_0402_5%
CLK_Ra
1 2
R593
0_0402_5%
CLK_Rb
R159
8.2K_0402_5%
1 2
R157
0_0402_5%
CLK_Rc
+3VS
12
12
12
@
D D
C C
B B
A A
+CK_VDD_MAIN2
+CK_VDD_DP
+VCCP
1 2
12
1 2
12
+VCCP
1 2
FSB
1 2
12
+VCCP
1 2
1 2
12
12
+3VS +3VS
1:CPU ITP *0:SRC 10
5
1
C193
10U_0805_10V4Z
2
1
C142
10U_0805_10V4Z
2
1
C165
10U_0805_10V4Z
2
R601
56_0402_5%
CLK_Rd
R599
1K_0402_5%
R598
1K_0402_5%@
R587
1K_0402_5%@
R588
1K_0402_5%
R586
0_0402_5%
CLK_Re
R149
1K_0402_5%@
R148
1K_0402_5%
R150
0_0402_5%
CLK_Rf
12
R238
10K_0402_5%@
PCI_ICH PCI_MINI
12
R208
10K_0402_5%
for Pin 6,5
1
C185
0.1U_0402_16V4Z
2
1
C147
0.1U_0402_16V4Z
2
5/20
1
C182
0.1U_0402_16V4Z
2
MCH_CLKSEL0
MCH_CLKSEL1
Reserve for ICS954305 & R need change to 475ohm
MCH_CLKSEL2
1:24M *0:test Mode
12
R193
12
R200
1
C535
0.1U_0402_16V4Z
2
1
C146
0.1U_0402_16V4Z
2
1
C536
0.1U_0402_16V4Z
2
14.31818MHZ_20P_6X1430004201
Reserve for ICS954305
*0:CLKREQ5# for Pin 29
CLK_MCH_DREFCLK#
ICH_SMBDATA
+3VS
ICH_SMBCLK
+3VS +3VS
12
10K_0402_5%@
10K_0402_5%
R217
12
R199
for Pin 43,44/47,48
1:27M/SRC0 *0:DOT 96M/LCD100
4
1
C166
0.1U_0402_16V4Z
2
R125
1 2
1_0805_1%
1 2
R124
2.2_0805_1%
1
C537
0.1U_0402_16V4Z
2
C15722P_0402_50V8J
1 2
Y1
1 2
C15822P_0402_50V8J
CLK_48M_ICH
CLK_48M_CB
CLK_14M_ICH
CLK_PCI_TCG
CLK_PCI_PCM
CLK_PCI_EC
CLK_PCI_USB20
CLK_PCI_SIO
CLK_14M_SIO
CLK_MCH_DREFCLK
CLK_PCI_ICH
CLK_EN#
CLK_SMBCLK
CLK_SMBDATA
+3VS
2.2K_0402_5%
Q37
2N7002_SOT23
D
S
1 3
G
2
2
G
1 3
D
S
2N7002_SOT23
Q38
10K_0402_5%@
PCI_PCM
10K_0402_5%
4
CK_VDD_REF
CK_VDD_48
0.1U_0402_16V4Z
12
CLK_XTAL_IN
CLK_XTAL_OUT
CLK_48M_ICH
CLK_48M_CB
CLK_14M_ICH
R166 33_0402_5%
R158 12_0402_5%
CLK_MCH_DREFCLK
CLK_MCH_DREFCLK#
CLK_PCI_ICH PCI_ ICH
CLK_ENABLE#
CLK_SMBCLK
CLK_SMBDATA
R580
R581
2.2K_0402_5%
CLK_SMBDATA
CLK_SMBCLK
1:48M *0:CLKREQ7#
for Pin 38for Pin 45
12
R216
10K_0402_5%@
PCI_EC
12
R206
10K_0402_5%
+CK_VDD_DP
+CK_VDD_MAIN1
C168
1 2
1 2
C194 0.1U_0402_16V4Z
R209 12_0402_5%
R223 12_0402_5%
R142 33_0402_5%
1 2
R218 33_0402_5%GM@
1 2
R219 33_0402_5%GM@
33_0402_5%
12
R207
0_0402_5%
CK_VDD_REF
CK_VDD_48
12
12
R19233_0402_5% @
12
R19433_0402_5%
12
R18833_0402_5%
12
R18733_0402_5%
12
12
R16510K_0402_5%@
12
12
MCH_DREFCLK
MCH_DREFCLK#
12
R119
12
Security Classification
Issued Date
THIS SHEET OF E NGI NEER ING DR AWI NG I S T HE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONIC S, INC. AND C ONTAINS CONFID ENTIAL
AND TRADE S ECR ET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
FSA
FSB
FSC
PCI_PCM
PCI_EC
PCI_MINI
REF1CLK_14M_SIO
+3VS
3
U9
1
VDDSRC
49
VDDSRC
54
VDDSRC
65
VDDSRC
30
VDDPCI
36
VDDPCI
12
VDDCPU
18
VDDREF
40
VDD48
20
X1
19
X2
41
USB_48MHz/FSLA
45
FSLB/TEST_MODE/24Mhz
23
REF0/FSLC/TEST_SEL
34
PCICLK4/FCTSEL1
33
SEL_48M/PCICLK3
32
SEL_24M/PCICLK2
27
SEL_PCI6/PCICLK1
22
SEL_PCI5/REF1
43
DOTT_96MHz/27MHz_Nonspread
44
DOTC_96MHz/27MHz_spread
37
ITP_EN/PCICLK_F0
39
VTT_PWRGD#/PD
9
GND
16
SMBCLK
17
SMBDAT
4
GNDSRC
15
GNDCPU
21
GNDREF
31
GNDPCI
35
GNDPCI
42
GND48
68
GNDSRC
ICS9LPR325AKLFT_MLF72
R14110K_0402_5%
12
R58910K_0402_5%
1 2
R18110K_0402_5%
1 2
R19010K_0402_5%
1 2
2005/06/01 2006/06/01
3
VDDA
GNDA
PCI_SRC_STOP#
CPU_STOP#
CPUCLKT1LP
CPUCLKC1LP
CPUCLKT0LP
CPUCLKC0LP
CPUCLKT2_ITP/SRCCLKT10LP
CPUCLKC2_ITP/SRCCLKC10LP
SRCCLKT9LP
SRCCLKC9LP
CLKREQ9#
SRCCLKT8LP
SRCCLKC8LP
CLKREQ8#
SRCCLKT7LP
SRCCLKC7LP
CLKREQ7#/48Mhz_1
SRCCLKT6LP
SRCCLKC6LP
CLKREQ6#
SRCCLKT5LP
SRCCLKC5LP
CLKREQ5#/PCICLK6
SRCCLKT4LP
SRCCLKC4LP
CLKREQ4#
SRCCLKT3LP
SRCCLKC3LP
CLKREQ3#/PCICLK5
SRCCLKT2LP
SRCCLKC2LP
CLKREQ2#
SRCCLKT1LP
SRCCLKC1LP
CLKREQ1#
LCD100/96/SRC0_TLP
LCD100/96/SRC0_CLP
*1:PCICLK3 for Pin28
REF1
SATA_CLKREQA#
CLKREQC#
CLKREQD#
Compal Secret Data
Deciphered Date
2
+VDDAD
7
8
25
24
MCH_BCLK
11
MCH_BCLK#
10
CPU_BCLK
14
CPU_BCLK#
13
6
5
3
2
72
70
69
71
PCIE_SATA
66
PCIE_SATA# CLK_PCIE_SATA#
67
CLKREQ7#
38
63
64
62
MCH_3GPLL
60
MCH_3GPLL#
61
29
58
59
57
55
PCIE_ICH#
56
PCI_CLK5
28
52
53
CLKREQ2#
26
50
51
CLKREQ1#
46
47
48
R126
12
0_0805_5%
H_STP_PCI#
H_STP_CPU#
1 2
R132 0_0402_5%
1 2
R133 0_0402_5%
1 2
R130 0_0402_5%
1 2
R131 0_0402_5%
1 2
R151 0_0402_5%
1 2
R143 0_0402_5%
R594 0_0402_5%
1 2
R167 0_0402_5%
1 2
R160 0_0402_5%
R172 0_0402_5%
1 2
R182 0_0402_5%
1 2
R178 0_0402_5%
R189 0_0402_5%
1 2
R201 0_0402_5%
1 2
R196 0_0402_5%
1 2
R186
1 2
R214 0_0402_5%
1 2
R215 0_0402_5%
R171 0_0402_5%
1 2
R212 0_0402_5%
1 2
R213 0_0402_5%
1 2
R210 0_0402_5%
1 2
R211 0_0402_5%
12
12
12
0_0402_5%
12
CLKREQ7#
CLKREQ1#
CLKREQ2#
CLKREQ5#
PCI_CLK5
2
+3VS
CLK_MCH_BCLK
CLK_MCH_BCLK#
CLK_CPU_BCLK
CLK_CPU_BCLK#
CLK_PCIE_SATA
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
MCH_CLKREQ#CLKREQ5#
MINI_CLKREQ#
CLK_PCIE_ICHPCIE_ICH
CLK_PCIE_ICH#
CLK_PCIE_LAN
CLK_PCIE_LAN#
LAN_CLKREQ#
CLK_PCIE_VGA
CLK_PCIE_VGA#
CLK_PCIE_GMCH
CLK_PCIE_GMCH#
CLKSEL1
FSLA
CLKSEL0
FSLC1FSLB
CLKSEL2
0
0
1
H_STP_PCI#
H_STP_CPU#
CLK_MCH_BCLK
CLK_MCH_BCLK#
CLK_CPU_BCLK
CLK_CPU_BCLK#
Place these components
near each pin within 40
mils.
CLK_CPU_BCLK
CLK_CPU_BCLK#
CLK_MCH_BCLK
CLK_MCH_BCLK#
CLK_PCIE_SATA
SATA_CLKREQ#
R595 10K_0402_5%@
R592 10K_0402_5%@
R164 10K_0402_5%@
R173 10K_0402_5%@
R180 10K_0402_5%@
CLK_PCIE_SATA#
SATA_CLKREQ#
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
MCH_CLKREQ#
CLK_PCIE_MCARD
CLK_PCIE_MCARD#
MINI_CLKREQ#
CLK_PCIE_ICH
CLK_PCIE_ICH#
CLK_PCI_TCG
CLK_PCIE_LAN
CLK_PCIE_LAN#
LAN_CLKREQ#
CLK_PCIE_VGA
CLK_PCIE_VGA#
MCH_SSCDREFCLK
MCH_SSCDREFCLK#
12
12
12
12
12
Title
Size Document Number Re v
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC, M/B LA-3011
401395
?01, 2005
CLK_PCIE_GMCH
CLK_PCIE_GMCH#
CLK_PCIE_VGA
CLK_PCIE_VGA#
CLK_PCIE_SATA
CLK_PCIE_SATA#
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
CLK_PCIE_MCARD
CLK_PCIE_MCARD#
CLK_PCIE_ICH
CLK_PCIE_ICH#
CLK_MCH_DREFCLK
CLK_MCH_DREFCLK#
CLK_PCIE_LAN
CLK_PCIE_LAN#
1
PCI
SRC
CPU
MHz
133
166
+VDDAD
MHz
MHz
33.31
1000
100
33.3
1
C167
0.1U_0402_16V4Z
2
12
R120 49.9_0402_1%
12
@
R121 49.9_0402_1%
@
12
R122 49.9_0402_1%
12
@
R123 49.9_0402_1%
@
1 2
R226 49.9_0402_1%
1 2
@
R227 49.9_0402_1%
@
1 2
R228 49.9_0402_1%
1 2
@
R229 49.9_0402_1%
@
1 2
R152 49.9_0402_1%
1 2
@
R144 49.9_0402_1%
@
1 2
R168 49.9_0402_1%
1 2
@
R161 49.9_0402_1%
@
1 2
R183 49.9_0402_1%
1 2
@
R179 49.9_0402_1%
@
1 2
R202 49.9_0402_1%
1 2
@
R197 49.9_0402_1%
@
1 2
R224 49.9_0402_1%
1 2
@
R225 49.9_0402_1%
1 2
@
R230 49.9_0402_1%
1 2
@
R231 49.9_0402_1%
@
Reserve for ICS954305
A
of
15 48,
1
Loading...