Compal Electronics PICONODE User Manual
picoNode Module
Datasheet and Integration
Specification
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PicoNode Integration Specification
Contents
1 Overview ........................................................................................................................1
1.1 picoNode .......................................................................................................................... 1
2 DC and AC Characteristics ................................................................................................ 2
2.1 Absolute Maximum Ratings............................................................................................... 2
2.2 Recommended Operating Conditions ................................................................................ 2
3 Electrical Interface ...........................................................................................................5
3.1 Signal Descriptions ........................................................................................................... 7
4 Applications .................................................................................................................. 11
4.1 Powered Operating Mode ............................................................................................... 11
4.2 Battery Operated Mode .................................................................................................. 11
5 SPI Interface and Sequences ........................................................................................... 14
5.1 SPI System Interface Overview ........................................................................................ 14
5.2 SPI Mode and Timing ...................................................................................................... 15
5.3 Host Initialization ............................................................................................................ 15
5.4 Startup (Power On) Sequence ......................................................................................... 15
5.5 Wake Sequence .............................................................................................................. 17
5.6 Host-Driven Reset Sequence ........................................................................................... 19
5.7 Host MRQ Release/picoNode Allowed to Sleep Sequence ................................................. 20
6 Power States ................................................................................................................. 21
6.1 Operating States ............................................................................................................ 21
7 SPI Messaging Protocol .................................................................................................. 23
7.1 Arbitration ...................................................................................................................... 23
7.2 Message Protocol ........................................................................................................... 23
7.3 Host Interface SPI Bus State Machine .............................................................................. 26
7.4 SPI Bus Timing Example .................................................................................................. 27
7.5 Host Message SPI Example .............................................................................................. 28
7.6 Host Message “Connect” SPI Example ............................................................................. 30
8 picoNode Provisioning ................................................................................................... 33
9 Antenna Diversity .......................................................................................................... 34
9.1 Antenna Design Considerations ....................................................................................... 34
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PicoNode Integration Specification Contents
9.2 Diversity Considerations ................................................................................................. 35
9.3 Block Diagram ................................................................................................................ 36
9.4 Antennas ....................................................................................................................... 36
10 Regulatory Considerations ............................................................................................ 39
10.1 FCC Warnings ............................................................................................................... 39
11 Errata .......................................................................................................................... 41
Figures
Figure 1 Typical Application Diagram ...................................................................................... 1
Figure 2 SPI Timing, CPOL = 0, CPHA = 0 .............................................................................. 15
Figure 3 picoNode Power-up Timing Sequence ...................................................................... 16
Figure 4 Host-Initiated picoNode Wake Sequence – SRDY Low (Synchronous) ...................... 17
Figure 5 Host-Initiated picoNode Wake Sequence – SRDY High (Asynchronous) .................... 18
Figure 6 Host-Driven Reset Sequence................................................................................... 19
Figure 7 Host MRQ Release/picoNode Allowed to Sleep Sequence ........................................ 20
Figure 8 SPI Master and Slave Message Sequences ............................................................... 25
Figure 9 Host Interface SPI Bus State Machine ...................................................................... 26
Figure 10 SPI Timing Example .............................................................................................. 27
Figure 11 Host Message on SPI – MMsg Pair ......................................................................... 28
Figure 12 Host Message on SPI – MHdr Pair .......................................................................... 29
Figure 13. Antenna Diversity with Ethertronics ...................................................................... 34
Figure 14 picoNode Block Diagram ....................................................................................... 36
Figure 15 Controlled Impedance RF Trace Design .................................................................. 38
Figure 16 picoNode PCB Land Pattern .................................................................................. 45
Figure 17 picoNode PCB Land Pattern Keepouts ................................................................... 45
Figure 18. Powered Example ................................................................................................. 46
Figure 19 Lithium Battery Example ...................................................................................... 46
Figure 20 picoNode Mechanical Dimensions.......................................................................... 47
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PicoNode Integration Specification Contents
Tables
Table 1. picoNode Specifications ............................................................................................ 1
Table 2. Absolute Maximum Ratings ....................................................................................... 2
Table 3. Operating Conditions ................................................................................................ 2
Table 4. Operating Characteristics .......................................................................................... 2
Table 5. picoNode Pin Descriptions ......................................................................................... 5
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PicoNode Integration Specification
Revision History
Revision Release Date Change Description
0.1 May 10, 2017 Initial release
0.2 Jan. 15, 2018 Update Tables 1 and 4
0.3 Jan. 31, 2018 Add FCC Warnings in Sec. 10
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PicoNode Integration Specification
1 Overview
This document provides a brief overview of guidelines allowing an integrator to design a Host
product that utilizes the picoNode and ensures that the system meets all of its technical
objectives and requirements.
1.1 picoNode
The picoNode is a small form factor wireless network module that easily integrates with a
microcontroller or applications processor using a Serial Peripheral Interface (SPI). The top side
of the printed circuit board (PCB) is enclosed with a radio frequency (RF) shield. The picoNode is
an LGA-style module designed to be soldered directly onto a host board via SMT processes. For
details, see Appendix B: PCB Land Pattern and Keep-outs.
Table 1 picoNode Specifications
picoNode
Dimensions (per unit) 26 mm x 16 mm
Thickness: 2.4mm
Weight (per unit) 1.5 Grams
Transmit Power 21.5 dBm (typical)
RX Sensitivity -133 dBm (nominal)
For more mechanical details about the picoNode, refer to the mechanical drawing in 0D
Appendix D picoNode Mechanical Drawing.
The following figure shows how a picoNode interfaces with a Host application, running on an
applications processor.
Host
Sensor or Meter Reading or
Location Tracking Appl ication
Host Interface Protocol
Application
SPI Master Driver
MAC
RF PHY
Node
Host Interface
SPI Slave Driver
Figure 1 Typical Application Diagram
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PicoNode Integration Specification
2 DC and AC Characteristics
2.1 Absolute Maximum Ratings
Operating outside of these ranges may damage the unit.
The picoNode is MSL 3-rated and should be handled as an MSL 3 device per IPC/JEDEC J-STD033 (latest revision).
Table 2 Absolute Maximum Ratings
Parameter Min Max Unit
Storage Temperature -40 85 ⁰C
Operating Temperature -40 85 ⁰C
Vbatt Input Voltage 2.5 6.0 V
3.3V Supply 3.1 3.5 V
Digital Interface Signals, 3.3V nominal 3.0 3.6 V
2.2 Recommended Operating Conditions
Table 3 Operating Conditions
Parameter Min Max Unit
Input voltage, VBATT 2.5 5.5 V
3.3V Input 3.2 3.4 V
Ambient Temperature, Ta -40 85 ⁰C
The following characteristics apply across the -40°C to +85°C temperature range unless
otherwise noted.
Table 4 Operating Characteristics
Description Min Typ Max Units
DC Characteristics
Voltage – Vbatt 2.5 3.3 5.5 Volt
Off Current – Note 1 0.1 µA
Deep Sleep Current - Note 1 19 µA
Idle Current – Note 1 20 mA
Receive Current – Note 1 100 mA
picoNode: Transmit Current – Note 2 330 mA
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PicoNode Integration Specification
Description Min Typ Max Units
Digital
VOL – Voltage Output, Low (4mA sink) 0 0.4 V
VOH – Voltage Output High (4mA source) 2.4 3.3 V
SPI Clock – Note 11 0.1 8.6 MHz
Environmental
Operating Temperature -40 +85
Storage Temp -40 +85
Humidity – non-condensing 5 95 %
Ramp Temperature (maximum rate at which operating
temperature should change)
MTBF (picoNode) MHrs
Receiver
Receiver Sensitivity – Note 3 -133 dBm
Receiver Image Reject 25 33 dB
Noise Figure 4.9 dB
Input IP3 (high LNA gain mode) dBm
Maximum RF input level for specification compliance dBm
General RF Characteristics
Frequency Range – Note 4 2402 ~2482 MHz
Channel Spacing N/A 1.99 N/A MHz
Transmitter
Maximum RF Conducted Power –Note 5
FCC/IC markets:
ETSI markets:
Carrier Rejection -35 -51 dBc
Signal Modulation DSSS-
Signal Bandwidth 1.0 MHz
BT Factor 0.3
Peak to Average Ratio 2.3 dB
Spectral bandwidth at maximum RF power:
-6dB BW
-20dB BW
ACPR – Note 6 -30 dBc
Harmonics – Note 7 -43 dBm
Transmit Power Level Accuracy – Note 8
30
8.5
21.5
9.5
DBPSK
0.96
1.75
23.65
10
±1.5
°C
°C
°C/Hr.
dBm
dBm
MHz
MHz
dB
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PicoNode Integration Specification
Description Min Typ Max Units
Transmitter Spurious Outputs – Note 9
30MHz to 2400MHz:
2482MHz to 8000MHz:
VSWR Tolerance
Maximum VSWR for spec compliance – Note 10:
Maximum VSWR for stability.
< -43
< -43
1.5:1
9:1
dBm
dBm
NOTES:
1. Tested at 3.3V input, +25C. Please note the following:
a. There are power differences between the Voltage/Current numbers in this table.
b. The Table 4 refers to a maximal current draw that the Host system should be designed
to accommodate.
2. Measured at:
picoNode: +21.5 dBm TX output (Typ=50Ω), 3.3 V, range includes VSWR ≤ 1.5:1 (Po not
compensated).
3. Sensitivity at maximum DL spreading factor of 11 (2048) with 10% FER.
4. The upper frequency range is market dependent:
c. FCC/ISED: CH38; 2475.63 MHz.
d. ETSI: CH40; 2475.63 Hz.
e. Japan: CH41; 2481.60 MHz.
5. Maximum TX RF power:
picoNode: This is limited by FCC/IC grant to 21.5 dBm in these markets. Transmit power is
configured during network join time to meet country-specific deployment and regulatory
requirements. The configurable range is 0 – 21.5 dBm in 1 dB integer increments. For noninteger Power such as 21.5dBm, the Node’s MAX_TX Power must be set to 22dBm to force a
maximum calibrated value.
6. Spec and test method comes from FCC 15.247(d); Band Edge Emissions, 2 MHz offset.
7. At any TX power level, VSWR ≤ 3:1. Harmonics fall into FCC restricted bands.
8. Estimated sum of all contributors with VSWR ≤ 1.5:1. Normal link mode.
9. At any TX power level, VSWR ≤ 3:1. Applies to spurious, not ACPR or harmonics. Generally
the largest spurious output outside the 2.40-2.48GHz band is at 2/3LO and 4/3LO.
10. Maximum VSWR for spec compliance applies at 25°C only. Slightly degraded ACPR/mask
and power variation can be expected at temperature extremes.
11. The SPI clock has a maximum rate of 26 MHz/3 and a minimum of 100 kHz. There is no
physical limitation on the minimum clock rate but the 100 kHz is deemed “marginal” and is
not absolute. Depending on the data traffic model and level of debug traffic, 100 kHz may
cause a backup of SPI traffic, which then causes buffer overflow conditions. The application
must be validated to ensure that the SPI clock is sufficient to support required traffic.
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PicoNode Integration Specification
3 Electrical Interface
This chapter describes the electrical interface of the picoNode and how the Host processor controls for
the picoNode.
Table 5 picoNode Pin Descriptions
Pin # Pin Name Signal Direction
Relative to picoNode
2 WAKE Output, 1.8V CMOS_O* This is a 1.8V output signal that
1,3,4,5,7,10,12,
14,18,24,26,28,
29,30,31,32,34
23 3V3 Power Power The 3.3V can be continuously
15 VBATT Power Power Input power to the picoNode. This
Ground Power Power Ground return. Should be low RF
Signal Type Comment
reflects the status of the Node’s
power state. When WAKE is “high”
the Node is active in Idle, RX, or TX
states. When WAKE is “low”, the
Node’s 3.3V is internally gated OFF
and the Node is in its lowest power
state. This signal is to be used for
“battery operating modes”, as
describe in Figure 6 Lithium Battery
Example.
Connect the WAKE pin directly to
the enable pin of a voltage regulator
or FET switch controlling 3.3V
impedance to a solid ground plane
of the Host
supplied(line powered) or only when
the WAKE pin is asserted
“high”(battery powered). This
power domain is high power
(internal CPU, Transceiver, and RF
PA) and should be decoupled with a
low ESR, high capacitance
Capacitor.
power domain is low current but is
used 100% of the time to supply
internal Supervisory domains.
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PicoNode Integration Specification
Pin # Pin Name Signal Direction
Signal Type Comment
Relative to picoNode
8 SRQ Output CMOS_O SPI Slave Request. SRQ must be
connected to a pin that can wake
the application processor from
sleep, for battery powered
applications.
9 SRDY Output CMOS_O SPI Slave Ready
21 SCLK Input CMOS_I SPI Clock
19 MISO Output CMOS_O SPI Master Input Slave Output
22 CS Input CMOS_I SPI Chip Select(Note other slaves
are prohibited on the SPI interface,
but this pin must be controlled by
the Host Common Library). It
CANNOT be tied low on the PCB.
20 MOSI Input CMOS_I SPI Master Output Slave Input
11 MRQ Input CMOS_I SPI Master Request
13 ON_OFF Input CMOS_A This is used to turn ON/OFF the
Internal Power supplies of the
picoNode. It is controlled by the
Host Common Library.
Low: Node consumes <1uA
High: Node is active and will run
through a wide range of power
states.
17 TOUT Output CMOS_O TOUT is a normally low signal that
pulses high in response to specific
Network Timing Events. It allows an
application to trigger a
measurement with sub-1ms
accuracy.
6 RF_TXENA Output CMOS_O This signal is used to indicate status
of the Power Amplifier for the
picoNode:
Low = OFF
High = Enabled (Transmitting)
The rise edge can be used to trigger
a Host CPU’s ADC read of VBATT
(battery voltage while under
maximum load).
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PicoNode Integration Specification
Pin # Pin Name Signal Direction
Relative to picoNode
25,
27
33 RF_SHDN Output CMOS_O This pin indicates the status of the
16 TIME_QUAL Output CMOS_O This pin is reserved and should be
RF1,
RF2
RF RX/TX 50 Ohm These are the RF ports for the
Signal Type Comment
picoNode. They are 50 Ohm port,
DC coupled. RF1 is required but both
are desired for antenna diversity.
Single port or dual antenna port can
be configured in the provisioning
process.
RF Transceiver for the picoNode:
Low = Shutdown
High = Active
It can be used for WIFI/BT
coexistence, and to reduce power
supply current during low power
states (see 3.1.3)
left as Do Not Connect.
NOTES:
1. The VDD of the internal logic of the picoNode is 3.3Volt.
2. The Host is the SPI Master and the picoNode is the SPI Slave.
3. CMOS_I: The Node input voltages are 3.3V CMOS levels. VIH = 2.0V (minimum) and
VIL = 0.8V (maximum).
4. CMOS_O: The Node output voltages are 3.3V CMOS levels (4mA). VOH = 2.4V (minimum)
and VOL = 0.4V (maximum).
5. SPI inputs to the node (SCLK, MOSI, CS) must be tri-stated or driven low when the node
may be sleeping (MRQ and SRQ are both low). See section 5: SPI Interface and Sequences
for more details.
3.1 Signal Descriptions
3.1.1 GND
Ground is the Host CPU’s ground to enable a common reference between CPU and Node.
3.1.2 VBATT
This supplies a low current 2.5 V – 5.5 V for the Node’s internal supervisory circuitry. This pin
should be decoupled with a 0.1 µF capacitor on the Host processor board.
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PicoNode Integration Specification
3.1.3 3V3
This pin drives the CPU, Transceiver, RF PA section of the module. It can consume up to 800 mW.
Allow for bypassing with a 47 µF low ESR cap (bulk) and a 0.1 µF ceramic cap for optimal
performance. Depending on the Host design, there are some nuances that are important
regarding this signal:
3.3 V can be supplied continuously or only when the WAKE signal is asserted “high.”, for
battery powered applications.
The Node runs through various operating states when 3.3V is supplied.
If the Node internally is in a state that requires no RF, the 3.3 V can be “noisy” (+/-100
mV ripple). The RF state is defined by the RF_SHDN pin. This allows the Host’s 3.3 V
regulator to work in low quiescent (power save) modes.
If the Node internally is active and does require RF, the 3.3 V must be “clean” (+/-20mV
ripple). This forces the Host’s 3.3V supply into a high precision mode and forcing a high
quiescent current of that regulator.
If the Node is operated in a battery mode, when 3V3 isn't always enabled, the 3V3
supply must power up and be stable within 2mS of the WAKE signal going "high"
This switching of “noisy” and “clean” becomes clear (and important) when working with battery
operated devices and optimal low power drain.
3.1.4 ON_OFF
This input signal controls the power-on of the LDO circuitry for the picoNode. This signal is
controlled by the Host Common Library, compiled onto the user’s apps processor. For reference
only: It must be shut off prior to starting the picoNode power-up sequence as defined in section
5.4: Startup (Power On) Sequence. After the picoNode powers up, this signal is to remain logic
high during normal operational modes. This pin dually serves a power on/off function as well as
a Node Reset function.
3.1.5 MRQ
The MRQ (Master Request) is the Host’s normal way of waking the picoNode to initiate SPI
communications. Logic “High” forces the picoNode awake. This signal is controlled by the Host
Common Library, compiled onto the user’s application processor.
3.1.6 SRDY
SRDY (Slave Ready) is an indication from the picoNode that it has fully booted its internal
Firmware image, initialized its Hardware and Interfaces, and is ready for communication
(arbitration) with the Host. Logic “High” indicates the picoNode is ready for communications.
This signal is controlled/handled by the Host Common Library, compiled onto the user’s
application processor.
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PicoNode Integration Specification
3.1.7 SRQ
The SRQ (Slave Request) signal is an indication from the picoNode that it wants the Host’s
attention. When SRQ is asserted “High,” the Host must read the Status registers of picoNode. If
SRQ is “High,” SRDY will also be “High.” This signal is controlled/handled by the Host Common
Library, compiled onto the user’s application processor.
For battery powered applications, SRQ must be connected to a pin that can wake the
application processor from sleep.
3.1.8 SPI System
The SPI system is the generic term used for all SPI signals (MOSI, MISO, CS, SCLK) to be set up
for SPI communications to occur between Host and picoNode. The picoNode SPI is the Slave in
the Master/Slave communications and is defined in section 5.2: SPI Mode and Timing.
IMPORTANT NOTES:
1. Other SPI slaves are not allowed to share the SPI signals.
2. CS must be controlled by the Host Common Library API to guarantee correct sequencing.
Specifically, the user must ensure that the SPI CS is active (low) for the whole duration of a
message transfer, with no gaps.
3.1.9 TOUT
This signal is a Time Synchronizing signal that pulses high upon specific network timing events.
3.1.10 RF_TXENA
This signal indicates when the device is transmitting. When transmitting, it is recommended
that the Host processor use this opportunity as a trigger to read the system “Vbatt” power line
to show battery voltage under maximum load.
3.1.11 RF_SHDN
This Node signal indicates status of the RF Transceiver of the picoNode. If low, the transceiver
sleeps (no RX and no TX). This output of the module (3.3 V) indicates when the RF transceiver is
on or off. When RF_SHDN is high, the RF is “ON” (RX or TX). In the RF “ON” mode, the module
needs a “clean” 3.3 V (low ripple).
3.1.12 RF1 and RF2
These are the RF ports (RX and TX) of the Node. They are DC-coupled, 50 Ohm and require
special Host routing of PCB. RF1 is the primary antenna and is always required. RF2 is a
secondary antenna that the Node can use for Antenna Diversity. A single or dual antenna
(diversity) system can be configured during the Provisioning process. For best results ensure
the load termination (antenna) has a VSWR of 1.5:1 or better (return loss < -10 dB).
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PicoNode Integration Specification
3.1.13 WAKE
The WAKE signal is generated by the module and is 1.8V. It signals that it now requires a 3.3V
source. Generally, for a Powered Node (Figure 5 Powered Example) the WAKE is not required
since 3.3V already exists. In the battery example (Figure 6 Lithium Battery Example) the WAKE
turns on the Host's main supply to regulate the battery to the required 3.3V.
If WAKE is used to enable the Host's 3V3 supply, the 3V3 supply must be on and stable within
2mS of WAKE going high.
3.1.14 TIME_QUAL
This signal is reserved for Compal.
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PicoNode Integration Specification
4 Applications
This chapter describes two major methods of implementing the picoNode: Powered and
battery operated modes.
1. Powered Operating Mode
“Powered” refers to the Host board and its power supply. Specifically, it refers to a good
solid, consistent power supply – such as an AC powered source. In this type of usage case,
the Host can potentially supply a good clean 3.3 V rail (pin 4) without regard to extreme
detail of optimizing power consumption.
2. Battery Operated Mode
This mode refers to a battery operated device in which extreme care and attention is
applied to reducing overall power consumption. All details and all modes of power
consumption are considered and optimized.
4.1 Powered Operating Mode
In this scenario, the Host and Node’s power consumption is not really a consideration. In this
case, the Host can take an input Voltage and convert to a 100% duty 3.3 V supply. This would be
applied to:
Host CPU
VBATT of picoNode
3V3 of picoNode
In this case, the node will internally turn the 3.3 V rail ON/OFF as it is required. The Node
attempts to gate this internal supply OFF to conserve power, when it can. The HW status of the
3.3V supply is the WAKE signal (3.3V = “ON” if WAKE is High). When the 3.3V is internally gated
off, the Node consumes virtually no power on that supply.
However, the Host CPU is always powered by 3.3 V – the operating level of the Host-picoNode
SPI interface. The picoNode requires a full 3.3 V during SPI transfers. For a wired example of the
Powered circuitry, refer to Figure 5 Powered Example.
4.2 Battery Operated Mode
Battery operating mode offers a much more challenging design constraint. The goal is to
reduce current consumption where possible. To this conservation goal, see Figure 6 Lithium
Battery Example.
The assumption in this design goal is to use a long life battery such as Lithium battery/cell.
These primary cells offer:
Extreme low self-discharge
Long life
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