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NB250
Schematic
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Compal Electronics LA-5122P PAV10 Buffalo 10BL, NB250, NB255 Schematic

A
1 1
B
C
D
E
Compal Confidential
2 2
Buffalo 10BL
LA-5122P Schematics Document
Intel Pine View Processor/ Tiger point
3 3
4 4
A
B
2010-03-30
REV: 1.0
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2009/04/07 2012/10/21
2009/04/07 2012/10/21
2009/04/07 2012/10/21
C
Deciphered Date
Deciphered Date
Deciphered Date
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc. SCHEMATICS， MB A5122
SCHEMATICS， MB A5122
SCHEMATICS， MB A5122
401897 C
401897 C
401897 C
138Monday, September 20, 2010
138Monday, September 20, 2010
138Monday, September 20, 2010
of
of
E
of
A
B
C
D
E
Compal Confidential
Model Name : PAV10 File Name : LA-5122P
1 1
CRT Conn.
page 14
Fan Control
page 24
Intel Pineview-M
LED Conn.
page 15
LVDS
ONE CHANNEL
(22x22mm)
page 5,6,7
Thermal Sensor
EMC1402
page 6
Memory BUS(DDRII)
1.8V DDRIII 667
Low Power Clock Generator
ICS9LVRS387AKLFT MLF
page 8
202pin DDRII-SO-DIMM
page 9
2 2
DMI x 2
PCIeMini Card WiMax
USB port 6
page 16
PCIeMini Card WLAN
PCIe port 6
page 16
RJ45
page 21
3 3
RTC CKT.
page 16
RTL8105E 10/100M
PCIe port 3
Card Reader
RTS5138 2IN1 USB port 3
page 21
page 21
USB
5V 480MHz
PCIe 1x [2,4]
1.5V 2.5GHz(250MB/s)
PCIe 1x
1.5V 2.5GHz(250MB/s)
USB
5V 480MHz
Tiger Pointer
(17x17mm)
page 10,11,12,13
USB
5V 480MHz
SATA port 0
5V 1.5GHz(150MB/s)
HD Audio
DC/DC Interface CKT.
3.3V 33 MHz
page 25
Power Circuit DC/DC
page 26~32
Debug Port
page 23
Touch Pad
4 4
Power/B
page 24
page 24
ENE KB926 E0
Int.KBD
page 23
LPC BUS
page 22
SPI ROM
page 23
USB Conn X3
USB port 0,1,4
page 17
SATA HDD&SSD
3.3V 24.576MHz/48Mhz
Int. Camera
USB port 7
page 18
page 18
HDA Codec
ALC259-GR
Int.
page 20 page 20 page 20 page 20
page 19
HP CONN SPK CONNMIC CONNMIC CONN
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2009/04/07 2012/10/21
2009/04/07 2012/10/21
2009/04/07 2012/10/21
C
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
D
Date: Sheet
Compal Electronics, Inc.
SCHEMATICS， MB A5122
SCHEMATICS， MB A5122
SCHEMATICS， MB A5122
401897
401897
401897
238Monday, September 20, 2010
238Monday, September 20, 2010
238Monday, September 20, 2010
E
C
C
C
of
of
of
A
B
C
D
E
Voltage Rails
1 1
OFF
G3
OFF
Power Plane Description
VIN B+ +CPU_CORE
Adapter power supply (19V) AC or battery power rail for power circuit. Core voltage for CPU
S1 S3 S5
ON ON ON OFF ON ON ON ON
ON OFF +0.89VS 0.89VS GFX support voltage OFFON OFF OFF +0.75VS 0.75V switched power rail for DDR terminator +1.05VS +1.5VS +1.5V
VCCP switched power rail
1.5V switched power rail
1.5V power rail for DDR +1.8VS 1.8VS switched power rail +3VALW
3.3V always on power rail +3V_SB 3.3V power rail for LAN +3V_LAN 3.3V power rail for LAN ON
2 2
+3V_WLAN +3VS +5VALW
+5VS
3.3V power rail for LAN ON ON
3.3V switched power rail
5V always on power rail
5V switched power rail +VSB VSB always on power rail ON +RTCVCC RTC power
ON OFF ON OFF OFF ON OFF OFF ON OFF
ON
ON
OFF ONON
ON
ON ON
ON
ON
ON
OFF
ON
ON OFF
ON
ON
ON ON
ON
OFF
OFF
OFF OFF OFF OFF
OFF ON
OFF
OFF OFF
OFF
OFF OFF
OFF OFF
OFF
OFFON
OFF+5V_SB 5V power rail for SB
OFF ON
OFF
OFF
ON
OFF
BTO Option Table
Function
description
explain
BTO
STATE
Full ON
S1(Power On Suspend)
S3 (Suspend to RAM)
S4 (Suspend to Disk)
S5 (Soft OFF)
Mini PCI-E SLOT
WLAN@ 3GGPS@
WIMAX@
SIGNAL
3GGPSWi-Fi WiMax
SLP_S3#
SLP_S4#
SLP_S5#
HIGH HIGH HIGH
HIGH
LOW
LOW LOW
LOWLOW
CAMERA & MIC
3G
CAMERA MIC
3G@
CAM@ MIC@
HIGHHIGHHIGH
HIGH
HIGH
LOW
+VALW
ON
ON
ON
ON
ON
BLUE TOOTH
BLUE TOOTH
BT@
+V +VS Clock
ON
ON
ON
OFF
OFF
ON
OFF
OFF
OFF
ONON
LOW
OFF
OFF
OFF
STAR
POWER SAVING
STAR@
shor 0 ohm
0 ohm no pop
MP@
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
description
explain
BTO
Function
3 3
EC SM Bus1 address
Device
Smart Battery
Address
ICH7M SM Bus address
Device
Clock Generator (SLG8SP556VTR)
DDR DIMMA
Address
1101 001Xb
1010 000Xb
EC SM Bus2 address
Device
EMC1402
Address
1001 010X b0001 011X b
TR14
@ TR14
@
1 2
0_0402_5%
0_0402_5%
1TOP 1VCC 1IN1 1IN2 1GND 1BOT
CPU
MP CPU
MP_455@
TR10
@ TR10
@
1 2
0_0402_5%
0_0402_5%
TR12
@ TR12
@
1 2
0_0402_5%
0_0402_5%
TOP_out
TOP_in
TR15
@ TR15
@
1 2
0_0402_5%
0_0402_5%
TR18
@ TR18
@
1 2
0_0402_5%
0_0402_5%
TOP_L TOP_R
@ TR17
@
@ TR20
@
TOP_SL TOP_SR
TR17
0_0402_5%
0_0402_5%
TR20
0_0402_5%
0_0402_5%
12
12
3/23~3/30 Before PVT SMT
4 4
4/13~4/21 after PVT SMT
4/16 Short PAD
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2009/04/07 2012/10/21
2009/04/07 2012/10/21
2009/04/07 2012/10/21
C
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
D
Date: Sheet
Compal Electronics, Inc.
SCHEMATICS， MB A5122
SCHEMATICS， MB A5122
SCHEMATICS， MB A5122 401897
401897
401897
338Monday, September 20, 2010
338Monday, September 20, 2010
338Monday, September 20, 2010
of
of
E
of
C
C
C
5
4
3
2
1
DESIGN CURRENT 250mA
B+
SN0806081RHBR
Buffalo Power Map
Ipeak=5A, Imax=3.5A, Iocp min=5.2A
** The SW just is reserved. The power passes by jump or
SBPWR_EN#
** SI3456BDV
DESIGN CURRENT 508mA
DESIGN CURRENT 45mA
+3VALWP +-5%
+3V_SB
0-ohm resistor.
D D
** P-CHANNEL
AO-3413
Ipeak=5A, Imax=3.5A, Iocp min=5.08A
** 2N7002DW
SUSP
N-CHANNEL
SI4800
SUSP
C C
N-CHANNEL
SI4800
P-CHANNEL
AO-3413
SUSP#
SY8033BDBC
SUSP#
WOL_EN#
SBPWR_EN#
ENVDD
DESIGN CURRENT 3010mA
DESIGN CURRENT 10mA
DESIGN CURRENT 2851mA
DESIGN CURRENT 9314mA
DESIGN CURRENT 450mA
DESIGN CURRENT 2600mA
+3V_LAN
+5VALWP +-5%
+5V_SB
+5VS
+3VS
+LCD_VDD
+0.89VSP
TPS51117RGYR +1.05VSP +-5%
Ipeak=6A, Imax=4.2A, Iocp min=7.18A
DESIGN CURRENT 7301mA
VR_ON
B B
ISL6261ACRZ-T
DESIGN CURRENT 3127mA
+CPU_CORE
SYSON
Ipeak=5A, Imax=3.5A, Iocp min=5.8A
DESIGN CURRENT 1720mA
+1.5VP +-5%
RT8209BGQW
SUSP#
IREF8113PBF
DESIGN CURRENT 2500mA
SUSP
APL5331KAC
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
2009/10/21 2012/10/21
2009/10/21 2012/10/21
2009/10/21 2012/10/21
4
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
3
DESIGN CURRENT 900mA
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
2
Compal Electronics, Inc.
SCHEMATICS， MB A5122
SCHEMATICS， MB A5122
SCHEMATICS， MB A5122
401897
401897
401897
+1.5VSP
+0.75VSP
of
of
of
438Monday, September 20, 2010
438Monday, September 20, 2010
438Monday, September 20, 2010
1
C
C
C
5
4/23 U1 , CPU change p/n by Jordan command: SA00003WA00->SA00003WAA0
N455@
N455@
U1A
D D
CLK_CPU_EXP#8 CLK_CPU_EXP8
C C
DMI_RXP0_C DMI_RXN0_C DMI_RXP1_C DMI_RXN1_C
DMI_RXP011
DMI_RXN011
DMI_RXP111
DMI_RXN111
U1A
F3
DMI_RXP_0
F2
DMI_RXN_0
H4
DMI_RXP_1
G3
DMI_RXN_1
N7
EXP_CLKINN
N6
EXP_CLKINP
R10
EXP_TCLKINN
R9
EXP_TCLKINP
N10
RSVD
N9
RSVD
K2
RSVD
J1
RSVD
M4
RSVD
L3
RSVD
PINEVIEW-M_FCBGA8559
PINEVIEW-M_FCBGA8559
XDP Reserve
R495
R495
XDP_TDI6 XDP_TMS6
XDP_TDO6
B B
XDP_PREQ#6
XDP_TRST#6 XDP_TCK6
XDP_TMS XDP_TDO XDP_PREQ#
XDP_TRST# XDP_TCK
R496
R496 R499
R499 R501
R501
R502
R502 R505
R505
1 2
51_0402_5%
51_0402_5%
1 2
51_0402_5%
51_0402_5%
1 2
51_0402_5%
51_0402_5%
1 2
51_0402_5%
51_0402_5%
1 2
51_0402_5%
51_0402_5%
1 2
51_0402_5%
51_0402_5%
C948
C948
C949
C949
C950
C950
C951
C951
1 2
1 2
1 2
1 2
PINEVIEW_M
PINEVIEW_M
REV = 1.1
REV = 1.1
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
+1.05VS
3/23 remove XDP connector
3/23 R506, R507, R508, JXDP1 removed
A A
5
4
G2
DMI_TXP_0
G1
DMI_TXN_0
H3
DMI_TXP_1
J2
DMI_RXP0_C
DMI_RXN0_C
DMI_RXP1_C
DMI_RXN1_C
DMI_TXN_1
EXP_RCOMPO
EXP_ICOMPI
EXP_RBIAS
RSVD_TP RSVD_TP
RSVD RSVD RSVD RSVD
1 OF 6
1 OF 6
L10
DMI_IRCOMP
L9 L8
N11 P11
K3 L2 M2 N2
R492
R492 R493
R493
T1T1
Pull-down must be placed
T2T2
within 500 mils from Pineview-M
DMI
DMI
Close to CPU
7/21 Add C302 to GND for Intel request 7/27 Change C302 to GND for +1.8V pull up
3/23 D45, D46 removed
Place diff CPU side
10/19 Change footprint T5, T6 and T7 from TPC24 to TPC12
4
3
DDR_A_DQS#[0..7]9 DDR_A_D[0..63]9 DDR_A_DM[0..7]9 DDR_A_DQS[0..7]9 DDR_A_MA[0..14]9
DMI_TXP0 11 DMI_TXN0 11 DMI_TXP1 11 DMI_TXN1 11
DDR_A_WE#9 DDR_A_CAS#9
49.9_0402_1%
49.9_0402_1% 750_0402_1%
750_0402_1%
DDR_A_RAS#9 DDR_A_BS09
DDR_A_BS19 DDR_A_BS29
DDR_CS0#9 DDR_CS1#9
DDR_CKE09 DDR_CKE19
M_ODT09 M_ODT19
M_CLK_DDR09 M_CLK_DDR#09 M_CLK_DDR19 M_CLK_DDR#19
7/20 Add R238 and R239 for Ref board design
+1.8V
C952
C952
0.01U_0402_16V7K
0.01U_0402_16V7K
R497
R497
1
80.6_0402_1%
80.6_0402_1%
2
R503
R503
80.6_0402_1%
80.6_0402_1%
DDR_RPU
DDR_RPD
R500
R500
1K_0402_1%
1K_0402_1%
R504
R504
1K_0402_1%
1K_0402_1%
+1.8V
12
12
R494
R494
10K_0402_5%
10K_0402_5%
R498
10K_0402_5%
10K_0402_5%
DDR_VREF
1
2
DDR_A_WE# DDR_A_CAS# DDR_A_RAS#
DDR_A_BS0 DDR_A_BS1 DDR_A_BS2
DDR_CS0# DDR_CS1#
DDR_CKE0 DDR_CKE1
M_ODT0 M_ODT1
M_CLK_DDR0 M_CLK_DDR#0 M_CLK_DDR1 M_CLK_DDR#1
+1.8V
C953
C953
0.1U_0402_16V4Z
0.1U_0402_16V4Z
DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14
12
12
@R498
@
DDR_RPD DDR_RPU
2
AH19
DDR_A_MA_0
AJ18
DDR_A_MA_1
AK18
DDR_A_MA_2
AK16
DDR_A_MA_3
AJ14
DDR_A_MA_4
AH14
DDR_A_MA_5
AK14
DDR_A_MA_6
AJ12
DDR_A_MA_7
AH13
DDR_A_MA_8
AK12
DDR_A_MA_9
AK20
DDR_A_MA_10
AH12
DDR_A_MA_11
AJ11
DDR_A_MA_12
AJ24
DDR_A_MA_13
AJ10
DDR_A_MA_14
AK22
DDR_A_WE#
AJ22
DDR_A_CAS#
AK21
DDR_A_RAS#
AJ20
DDR_A_BS_0
AH20
DDR_A_BS_1
AK11
DDR_A_BS_2
AH22
DDR_A_CS#_0
AK25
DDR_A_CS#_1
AJ21
DDR_A_CS#_2
AJ25
DDR_A_CS#_3
AH10
DDR_A_CKE_0
AH9
DDR_A_CKE_1
AK10
DDR_A_CKE_2
AJ8
DDR_A_CKE_3
AK24
DDR_A_ODT_0
AH26
DDR_A_ODT_1
AH24
DDR_A_ODT_2
AK27
DDR_A_ODT_3
AG15
DDR_A_CK_0
AF15
DDR_A_CK_0#
AD13
DDR_A_CK_1
AC13
DDR_A_CK_1#
AC15
DDR_A_CK_3
AD15
DDR_A_CK_3#
AF13
DDR_A_CK_4
AG13
DDR_A_CK_4#
AD17
RSVD
AC17
RSVD
AB15
RSVD
AB17
RSVD
AB4
RSVD
AK8
RSVD
AB11
T3T3 T4T4
AB13 AL28
AK28
AJ26
AK29
RSVD_TP RSVD_TP
DDR_VREF DDR_RPD DDR_RPU
RSVD
8/14 Add +DDR_VREF net name 8/24 Change net to DDR_VREF
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2009/10/21 2012/10/21
2009/10/21 2012/10/21
2009/10/21 2012/10/21
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
PINEVIEW_M
U1B
U1B
PINEVIEW-M_FCBGA8559
PINEVIEW-M_FCBGA8559
PINEVIEW_M
REV = 1.1
REV = 1.1
DDR_A
DDR_A
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
2 OF 6
2 OF 6
1
DDR_A_DQS0
DDR_A_DQS_0
DDR_A_DQS#_0
DDR_A_DM_0 DDR_A_DQ_0
DDR_A_DQ_1 DDR_A_DQ_2 DDR_A_DQ_3 DDR_A_DQ_4 DDR_A_DQ_5 DDR_A_DQ_6 DDR_A_DQ_7
DDR_A_DQS_1
DDR_A_DQS#_1
DDR_A_DM_1 DDR_A_DQ_8
DDR_A_DQ_9 DDR_A_DQ_10 DDR_A_DQ_11 DDR_A_DQ_12 DDR_A_DQ_13 DDR_A_DQ_14 DDR_A_DQ_15
DDR_A_DQS_2
DDR_A_DQS#_2
DDR_A_DM_2 DDR_A_DQ_16
DDR_A_DQ_17 DDR_A_DQ_18 DDR_A_DQ_19 DDR_A_DQ_20 DDR_A_DQ_21 DDR_A_DQ_22 DDR_A_DQ_23
DDR_A_DQS_3
DDR_A_DQS#_3
DDR_A_DM_3 DDR_A_DQ_24
DDR_A_DQ_25 DDR_A_DQ_26 DDR_A_DQ_27 DDR_A_DQ_28 DDR_A_DQ_29 DDR_A_DQ_30 DDR_A_DQ_31
DDR_A_DQS_4
DDR_A_DQS#_4
DDR_A_DM_4 DDR_A_DQ_32
DDR_A_DQ_33 DDR_A_DQ_34 DDR_A_DQ_35 DDR_A_DQ_36 DDR_A_DQ_37 DDR_A_DQ_38 DDR_A_DQ_39
DDR_A_DQS_5
DDR_A_DQS#_5
DDR_A_DM_5 DDR_A_DQ_40
DDR_A_DQ_41 DDR_A_DQ_42 DDR_A_DQ_43 DDR_A_DQ_44 DDR_A_DQ_45 DDR_A_DQ_46 DDR_A_DQ_47
DDR_A_DQS_6
DDR_A_DQS#_6
DDR_A_DM_6 DDR_A_DQ_48
DDR_A_DQ_49 DDR_A_DQ_50 DDR_A_DQ_51 DDR_A_DQ_52 DDR_A_DQ_53 DDR_A_DQ_54 DDR_A_DQ_55
DDR_A_DQS_7
DDR_A_DQS#_7
DDR_A_DM_7 DDR_A_DQ_56
DDR_A_DQ_57 DDR_A_DQ_58 DDR_A_DQ_59 DDR_A_DQ_60 DDR_A_DQ_61 DDR_A_DQ_62 DDR_A_DQ_63
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
AD3
DDR_A_DQS#0
AD2
DDR_A_DM0
AD4
DDR_A_D0
AC4
DDR_A_D1
AC1
DDR_A_D2
AF4
DDR_A_D3
AG2
DDR_A_D4
AB2
DDR_A_D5
AB3
DDR_A_D6
AE2
DDR_A_D7
AE3
DDR_A_DQS1
AB8
DDR_A_DQS#1
AD7
DDR_A_DM1
AA9
DDR_A_D8
AB6
DDR_A_D9
AB7
DDR_A_D10
AE5
DDR_A_D11
AG5
DDR_A_D12
AA5
DDR_A_D13
AB5
DDR_A_D14
AB9
DDR_A_D15
AD6
DDR_A_DQS2
AD8
DDR_A_DQS#2
AD10
DDR_A_DM2
AE8
DDR_A_D16
AG8
DDR_A_D17
AG7
DDR_A_D18
AF10
DDR_A_D19
AG11
DDR_A_D20
AF7
DDR_A_D21
AF8
DDR_A_D22
AD11
DDR_A_D23
AE10
DDR_A_DQS3
AK5
DDR_A_DQS#3
AK3
DDR_A_DM3
AJ3
DDR_A_D24
AH1
DDR_A_D25
AJ2
DDR_A_D26
AK6
DDR_A_D27
AJ7
DDR_A_D28
AF3
DDR_A_D29
AH2
DDR_A_D30
AL5
DDR_A_D31
AJ6
DDR_A_DQS4
AG22
DDR_A_DQS#4
AG21
DDR_A_DM4
AD19
DDR_A_D32
AE19
DDR_A_D33
AG19
DDR_A_D34
AF22
DDR_A_D35
AD22
DDR_A_D36
AG17
DDR_A_D37
AF19
DDR_A_D38
AE21
DDR_A_D39
AD21
DDR_A_DQS5
AE26
DDR_A_DQS#5
AG27
DDR_A_DM5
AJ27
DDR_A_D40
AE24
DDR_A_D41
AG25
DDR_A_D42
AD25
DDR_A_D43
AD24
DDR_A_D44
AC22
DDR_A_D45
AG24
DDR_A_D46
AD27
DDR_A_D47
AE27
DDR_A_DQS6
AE30
DDR_A_DQS#6
AF29
DDR_A_DM6
AF30
DDR_A_D48
AG31
DDR_A_D49
AG30
DDR_A_D50
AD30
DDR_A_D51
AD29
DDR_A_D52
AJ30
DDR_A_D53
AJ29
DDR_A_D54
AE29
DDR_A_D55
AD28
DDR_A_DQS7
AB27
DDR_A_DQS#7
AA27
DDR_A_DM7
AB26
DDR_A_D56
AA24
DDR_A_D57
AB25
DDR_A_D58
W24
DDR_A_D59
W22
DDR_A_D60
AB24
DDR_A_D61
AB23
DDR_A_D62
AA23
DDR_A_D63
W27
SCHEMATICS， MB A5122
SCHEMATICS， MB A5122
SCHEMATICS， MB A5122
401897
401897
401897
538Monday, September 20, 2010
538Monday, September 20, 2010
538Monday, September 20, 2010
1
C
C
C
of
of
of
5
PINEVIEW_M
U1C
U1C
D12
T8T8 T18T18 T9T9 T10T10 T19T19
D D
T11T11 T20T20 T12T12 T13T13
XDP_RSVD_9
T14T14 T15T15 T44T44 T17T17 T21T21 T22T22 T23T23 T24T24
T25T25
C C
T26T26 T27T27 T28T28 T29T29
T31T31 T32T32 T33T33 T35T35 T37T37
C10 D10 B11 B10 B12 C11
AA7 AA6
AA21
W21
V21
A7 D6 C5 C7 C6 D8 B7 A9 D9 C8 B8
L11
R5 R6
T21
XDP_RSVD_00 XDP_RSVD_01 XDP_RSVD_02 XDP_RSVD_03 XDP_RSVD_04 XDP_RSVD_05 XDP_RSVD_06 XDP_RSVD_07 XDP_RSVD_08 XDP_RSVD_09 XDP_RSVD_10 XDP_RSVD_11 XDP_RSVD_12 XDP_RSVD_13 XDP_RSVD_14 XDP_RSVD_15 XDP_RSVD_16 XDP_RSVD_17
RSVD
RSVD_TP RSVD_TP RSVD_TP RSVD_TP
RSVD_TP RSVD_TP RSVD_TP RSVD_TP
PINEVIEW_M
REV = 1.1
REV = 1.1
VGA
VGA
PM_EXTTS#_1/DPRSLPVR
MISC
MISC
CRT_HSYNC CRT_VSYNC
CRT_RED
CRT_GREEN
CRT_BLUE
CRT_IRTN
CRT_DDC_DATA
CRT_DDC_CLK
DAC_IREF
REFCLKINP
REFCLKINN REFSSCLKINP REFSSCLKINN
PM_EXTTS#_0
PWROK
RSTIN#
HPL_CLKINN
HPL_CLKINP
8/14 Add CRT_IRTN net name 8/24 Det CRT_IRTN net name
M30 M29
GMCH_CRT_R
N31
GMCH_CRT_G
P30
GMCH_CRT_B
P29 N30
L31 L30
P28 Y30
Y29 AA30 AA31
K29 J30 L5 AA3
W8 W9
R510 be placed <500 mils to U1.P28
DAC_IREF CPU_DREFCLK
CPU_DREFCLK# CPU_SSCDREFCLK CPU_SSCDREFCLK#
8/14 Add DAC_IREF net name
MP@
MP@
PM_EXTTS#1 PM_EXTTS#0 PCH_POK PLTRST#
CLK_CPU_HPLCLK# CLK_CPU_HPLCLK
To be placed <250 mils to U1 ball
GMCH_CRT_R GMCH_CRT_G GMCH_CRT_B ENBKL
To be placed <500 mils to U1 ball
XDP_RSVD_9
4
GMCH_CRT_HSYNC 14 GMCH_CRT_VSYNC 14
GMCH_CRT_R 14 GMCH_CRT_G 14 GMCH_CRT_B 14
GMCH_CRT_DATA 14 GMCH_CRT_CLK 14
R510 665_0402_1%R510 665_0402_1%
0_0402_5%
0_0402_5%
R512
R512
PM_EXTTS#0 9 PCH_POK 12,23 PLTRST# 12,16,22,24
CPU_DREFCLK 8 CPU_DREFCLK# 8 CPU_SSCDREFCLK 8 CPU_SSCDREFCLK# 8
PM_DPRSLPVR 12
CLK_CPU_HPLCLK# 8 CLK_CPU_HPLCLK 8
R509 be placed U1.R22
PM_EXTTS#0
3/23 remove XDP_BPM#0~#3, reserve pad.
R514
R514
1 2
150_0402_1%
150_0402_1% R515
R515
1 2
150_0402_1%
150_0402_1% R516
R516
1 2
150_0402_1%
150_0402_1% R517
R517
100K_0402_5%
100K_0402_5%
01/11 Add 0 ohm for XDP signals.
XDP_TDI5 XDP_TDO5 XDP_TCK5 XDP_TMS5 XDP_TRST#5
3/23 short R619, R620, R621, R622, R623
3
LVDS_ACLK#15
LVDS_ACLK15 LVDS_A0#15 LVDS_A015 LVDS_A1#15 LVDS_A115 LVDS_A2#15 LVDS_A215
2.37K_0402_1%
2.37K_0402_1%
ENBKL23
GMCH_INVT_PWM15
LVDS_SCL15 LVDS_SDA15
GMCH_ENVDD15
+3VS
12
R513
R513 10K_0402_5%
10K_0402_5%
Close to Processor pin
Close to CPU
Close to CPU
XDP_TDI XDP_TDO XDP_TCK XDP_TMS
XDP_TRST#
R509
R509
ENBKL
XDP_BPM#0_R XDP_BPM#1_R XDP_BPM#2_R XDP_BPM#3_R
T30T30 T34T34
T36T36
T38T38
H_THERMDA H_THERMDC
L_IBG
U25 U26 R23 R24 N26 N27 R26 R27
R22 N22
N23
K25 K23 K24 H26
G11 E15 G13 F13
B18 B20 C20 B21
D14 D13 B14 C14 C16
D30 E30
J28
L27 L26 L23
G5
U1D
U1D
LA_CLKN LA_CLKP LA_DATAN_0 LA_DATAP_0 LA_DATAN_1 LA_DATAP_1 LA_DATAN_2 LA_DATAP_2
LIBG LVBG LVREFH LVREFL LBKLT_EN LBKLT_CTL LCTLA_CLK LCTLB_DATA LDDC_CLK LDDC_DATA LVDD_EN
BPM_1_0# BPM_1_1# BPM_1_2# BPM_1_3#
BPM_2_0#/RSVD BPM_2_1#/RSVD BPM_2_2#/RSVD BPM_2_3#/RSVD
RSVD TDI TDO TCK TMS TRST#
THRMDA_1 THRMDC_1
PINEVIEW_M
PINEVIEW_M
LVDS
LVDS
REV = 1.1
REV = 1.1
ICH
ICH
CPU
CPU
2
THERMTRIP#
PROCHOT#
CPUPWRGOOD
EXTBGREF
SMI# A20M# FERR#
LINT0 LINT1
IGNNE#
STPCLK#
DPRSTP#
DPSLP#
INIT# PRDY# PREQ#
GTLREF
VSS
RSVD RSVD
BCLKN BCLKP
BSEL_0 BSEL_1 BSEL_2
VID_0 VID_1 VID_2 VID_3 VID_4 VID_5 VID_6
RSVD RSVD RSVD RSVD
RSVD_TP RSVD_TP
H_SMI#
E7 H7 H6 F10 F11 E5 F8
G6 G10 G8 E11 F15
E13
H_A20M# H_FERR# H_INTR H_NMI H_IGNNE# H_STPCLK#
H_DPRSTP# H_DPSLP# H_INIT# XDP_PRDY# XDP_PREQ#
H_THERMTRIP#
H_SMI# 10 H_A20M# 10 H_FERR# 10 H_INTR 10 H_NMI 10 H_IGNNE# 10 H_STPCLK# 10
H_DPRSTP# 12 H_DPSLP# 12 H_INIT# 10
H_THERMTRIP# 10
Close to CPU
H_PROCHOT#
C18
H_PWRGD
W1
A13 H27
H_GTLREF
H_PWRGD 12
8/14 Change net name to +H_GTLREF
L6
8/24 Change net name to H_GTLREF
E17
CLK_CPU_BCLK#
H10 J10
K5 H5 K6
H30 H29 H28 G30 G29 F29 E29
L7 D20 H13 D18
K9 D19 K7
CLK_CPU_BCLK
CPU_BSEL0 CPU_BSEL1 CPU_BSEL2
CPU_VID0 CPU_VID1 CPU_VID2 CPU_VID3 CPU_VID4 CPU_VID5 CPU_VID6
T39T39 T40T40
H_EXTBGREF
CLK_CPU_BCLK# 8 CLK_CPU_BCLK 8
CPU_BSEL0 8 CPU_BSEL1 8 CPU_BSEL2 8
CPU_VID0 33 CPU_VID1 33 CPU_VID2 33 CPU_VID3 33 CPU_VID4 33 CPU_VID5 33 CPU_VID6 33
1
XDP_PREQ# 5
Close to CPU
+1.05VS
R51168_0402_5% R51168_0402_5%
8/14 Change net name to +H_EXTBGREF
R518
B B
3 OF 6
PINEVIEW-M_FCBGA8559
PINEVIEW-M_FCBGA8559
3 OF 6
7/21 Pull down 1K to GND for Intel request
+3VS
1
C961
C961
2
0.1U_0402_16V4Z
A A
+3VS
0.1U_0402_16V4Z
C968
C968
1 2
2200P_0402_50V7K
2200P_0402_50V7K
1 2
R524 10K_0402_5%R524 10K_0402_5%
5
H_THERMDA H_THERMDC CPU_THERM#
CPU THERMAL SENSOR
U2
U2
GND
8 7 6 5
EC_SMB_CK2 EC_SMB_DA2
1
VDD
2
DP
3
DN
4
THERM#
EMC1402-1-ACZL-TR_MSOP8
EMC1402-1-ACZL-TR_MSOP8
Address:0100_1100 EMC1402-1 Address:0100_1101 EMC1402-2
SMCLK
SMDATA
ALERT#
R518 1K_0402_5%
1K_0402_5%
1 2
H_DPRSTP# H_DPSLP# H_PWRGD H_A20M# H_IGNNE# H_INIT# H_INTR H_FERR# H_NMI
EC_SMB_CK2 23 EC_SMB_DA2 23
12
R523 10K_0402_5%@R523 10K_0402_5%@
4
+3VS
H_SMI# H_STPCLK#
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C954 220P_0402_50V7K@C954 220P_0402_50V7K@
1 2
C955 220P_0402_50V7K@C955 220P_0402_50V7K@
1 2
C956 220P_0402_50V7K@C956 220P_0402_50V7K@
1 2
C957 220P_0402_50V7K@C957 220P_0402_50V7K@
1 2
C958 220P_0402_50V7K@C958 220P_0402_50V7K@
1 2
C959 220P_0402_50V7K@C959 220P_0402_50V7K@
1 2
C960 220P_0402_50V7K@C960 220P_0402_50V7K@
1 2
C962 220P_0402_50V7K@C962 220P_0402_50V7K@
1 2
C965 220P_0402_50V7K@C965 220P_0402_50V7K@
1 2
C966 220P_0402_50V7K@C966 220P_0402_50V7K@
1 2
C967 220P_0402_50V7K@C967 220P_0402_50V7K@
1 2
2009/10/21 2012/10/21
2009/10/21 2012/10/21
2009/10/21 2012/10/21
3
C30
THRMDA_2/RSVD
D31
THRMDC_2/RSVD
PINEVIEW-M_FCBGA8559
PINEVIEW-M_FCBGA8559
ESD request
Deciphered Date
Deciphered Date
Deciphered Date
4 OF 6
4 OF 6
220P_0402_50V7K
220P_0402_50V7K
placed within 0.5" of processor pin.
2
C963
C963
@
@
1
2
8/24 Change net name to H_EXTBGREF
placed within 0.5" of processor pin and 5 mils spacing
+1.05VS+1.05VS
R520
R519
R519 1K_0402_1%
1K_0402_1%
R521
R521 2K_0402_1%
2K_0402_1%
H_EXTBGREFH_GTLREF
C964
C964
1U_0402_6.3V6K
1U_0402_6.3V6K
1
2
R520 976_0402_1%
976_0402_1%
R522
R522
3.3K_0402_1%
3.3K_0402_1%
7/20 Add C335 for Ref board design7/20 Reserve C336 for Ref board design
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
B
B
B
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
SCHEMATICS， MB A5122
SCHEMATICS， MB A5122
SCHEMATICS， MB A5122
401897
401897
401897
638Monday, September 20, 2010
638Monday, September 20, 2010
638Monday, September 20, 2010
1
of
of
of
C
C
C
5
U1E
U1E
+0.89VS
D D
+1.8V
R527
R527
1 2
0_0603_5%
0_0603_5%
C979
@C979
@
MP@
MP@
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
2
C980
C980
1
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
2
2
C982
C982
C981
C981
1
1
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
Please closed U1 ball
+1.8V
R530
R530
C C
1 2
0_0603_5%
0_0603_5%
MP@
MP@
22U_0805_6.3V6M
22U_0805_6.3V6M
1
C992
C992
0.1U_0402_10V6K
0.1U_0402_10V6K
2
1
2
Please closed U1 ball
B B
1380mA
2
2
C983
C983
1
1
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
+VCC_SM
+VCCCK_DDR
@
@
+VCCCK_DDR
C993
C993
+VCCA_VCCD
1320mA
+VCCSFR_AB_DPL
+VCC_SM
2270mA
W14 W16 W18 W19
AK13 AK19
AL11 AL16 AL21 AL25
W10 W11
AA10 AA11
AA19
AC31
T13 T14 T16 T18
T19 V13 V19
AK9
AK7 AL7
U10
U5 U6 U7 U8 U9 V2 V3 V4
V11
VCCGFX VCCGFX VCCGFX VCCGFX VCCGFX VCCGFX VCCGFX VCCGFX VCCGFX VCCGFX VCCGFX
VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM
VCCCK_DDR VCCCK_DDR
VCCA_DDR VCCA_DDR VCCA_DDR VCCA_DDR VCCA_DDR VCCA_DDR VCCA_DDR VCCA_DDR VCCA_DDR VCCA_DDR VCCA_DDR
VCCACK_DDR VCCACK_DDR
VCCD_AB_DPL
VCCD_HMPLL
VCCSFR_AB_DPL
PINEVIEW_M
PINEVIEW_M
GFX/MCH
GFX/MCH
DDR
DDR
REV = 1.1
REV = 1.1
154mA
+3VS
+RING_EAST +RING_WEST
+LGI_VID +DMI_HMPLL
+0.89VS
A A
2
C1006
C1006
C1005
C1005
1
2.2U_0603_10V6K
2.2U_0603_10V6K
+VCC_CRT_DAC
5mA
305mA
1
2
1U_0402_6.3V6K
1U_0402_6.3V6K
C1007
C1007
1
1
C1008
C1008
2
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
C1009
C1009
T30
VCCACRTDAC
T31
VCC_GIO
J31
VCCRING_EAST
C3
VCCRING_WEST
B2
VCCRING_WEST
C2
VCCRING_WEST
A21
VCC_LGI
5 OF 6
5 OF 6
PINEVIEW-M_FCBGA8559
PINEVIEW-M_FCBGA8559
1
1
2
1
C1012
C1010
C1010
2
1U_0402_6.3V6K
1U_0402_6.3V6K
C1012
C1011
C1011
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
EXP\CRT\PLL
EXP\CRT\PLL
1
2
1
C1013
C1013
C1014
2
C1014
1
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
Close Chipset pin
5
POWER
POWER
DMI
DMI
VCCSFR_DMIHMPLL
1
+
+
C1004
C1004
2
10U_0805_10V4Z
10U_0805_10V4Z
LVDS
LVDS
330U_D2_2.5VY_R9M
330U_D2_2.5VY_R9M
CPU
CPU
4
VCCSENSE
4
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
VSSSENSE
VCCA
VCCP VCCP
VCCP
VCCALVDS VCCDLVDS
VCCA_DMI VCCA_DMI VCCA_DMI
RSVD
VCCP
3500mA
1U_0402_6.3V6K
A23 A25 A27 B23 B24 B25 B26 B27 C24 C26 D23 D24 D26 D28 E22 E24 E27 F21 F22 F25 G19 G21 G24 H17 H19 H22 H24 J17 J19 J21 J22 K15 K17 K21 L14 L16 L19 L21 N14 N16 N19 N21
C29 B29 Y2
80mA
D4 B4
B3
1U_0402_6.3V6K
VCCSENSE VSSSENSE
@
@
Please closed U1.D4
+VCC_ALVD
V30
+VCC_DLVD
W31
60mA
+VCC_DMI
T1
480mA
T2 T3
P2 AA1
104mA
E2
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
C974
C974
C975
C975
2
2
1U_0402_6.3V6K
1U_0402_6.3V6K
Please closed U1 ball
+CPU_CORE
2 x 330uF(9mohm/2)
1
+
+
C984
C984
330U_D2_2.5VY_R9M
330U_D2_2.5VY_R9M
2
+CPU_CORE
1
1
C989
C989
C990
C990
2
2
22U_0805_6.3V6M
22U_0805_6.3V6M
+1.05VS
1
C999
C999
0.1U_0402_10V6K
0.1U_0402_10V6K
2
+1.05VS
Please closed U1.Y2
T41T41
Security Classification
Security Classification
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1
C976
C976
2
1
C991
C991
2
22U_0805_6.3V6M
22U_0805_6.3V6M
1
C996
C996
0.01U_0402_16V7K
0.01U_0402_16V7K
2
Issued Date
Issued Date
Issued Date
3
+CPU_CORE
1
C977
C977
1U_0402_6.3V6K
1U_0402_6.3V6K
2
1
+
+
C985
C985
330U_D2_2.5VY_R9M
330U_D2_2.5VY_R9M
2
22U_0805_6.3V6M
22U_0805_6.3V6M
+1.5VS
3
+1.05VS
R525
R525
1 2
0_0603_5%
0_0603_5%
MP@
MP@
+1.05VS
1 2
1 2
1 2
1 2
+CPU_CORE
12
R532
R532
100_0402_5%
100_0402_5%
VCCSENSE 33 VSSSENSE 33
12
R533
R533
100_0402_5%
100_0402_5%
2009/10/21 2012/10/21
2009/10/21 2012/10/21
2009/10/21 2012/10/21
1
C969
C969
2
@
@
0.1U_0402_10V6K
0.1U_0402_10V6K
R526
R526 0_0603_5%
0_0603_5%
MP@
MP@
R528
R528 0_0603_5%
0_0603_5%
MP@
MP@
R529
R529 0_0603_5%
0_0603_5%
MP@
MP@
R531
R531 0_0603_5%
0_0603_5%
MP@
MP@
+1.8VS
Compal Secret Data
Compal Secret Data
Compal Secret Data
2
C970
C970
1
@
@
0.1U_0402_10V6K
0.1U_0402_10V6K
C986
C986
R534
R534
1 2
0_0603_5%
0_0603_5%
MP@
MP@
1U_0402_6.3V6K
1U_0402_6.3V6K
R535
R535
1 2
0_0603_5%
0_0603_5%
MP@
MP@
1U_0402_6.3V6K
1U_0402_6.3V6K
R536
R536
1 2
0_0603_5%
0_0603_5%
MP@
MP@
1U_0402_6.3V6K
1U_0402_6.3V6K
R537
R537
1 2
0_0603_5%
0_0603_5%
MP@
MP@
22U_0805_6.3V6M
22U_0805_6.3V6M
R538
R538
1 2
0_0603_5%
0_0603_5%
MP@
MP@
1U_0402_6.3V6K
1U_0402_6.3V6K
Deciphered Date
Deciphered Date
Deciphered Date
1
2
C994
C994
C971
C971
1
2
22U_0805_6.3V6M
22U_0805_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1
2
C978
C978
+RING_WEST
C987
C987
@
@
C988
C988
C995
C995
1U_0402_6.3V6K
1U_0402_6.3V6K
C997
C997
C1000
C1000
C1001
C1001
C1002
C1002
C1003
C1003
+VCCA_VCCD
1
C972
C972
2
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
+RING_EAST
1
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1
2
1U_0402_6.3V6K
1U_0402_6.3V6K
+LGI_VID
1
2
1U_0402_6.3V6K
1U_0402_6.3V6K
+VCC_DMI
+VCC_DMI
1
2
1U_0402_6.3V6K
1U_0402_6.3V6K
+VCCSFR_AB_DPL
1
1U_0402_6.3V6K
1U_0402_6.3V6K
2
+VCC_CRT_DAC+VCC_CRT_DAC
1
2
+DMI_HMPLL
1
2
+VCC_ALVD
1
2
+VCC_DLVD
1
2
C973
C973
C998
C998
2
PINEVIEW_M
PINEVIEW_M
U1F
U1F
REV = 1.1
REV = 1.1
A11
VSS
1
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1
2
2
A16
VSS
A19
VSS
A29
RSVD_NCTF
A3
RSVD_NCTF
A30
RSVD_NCTF
A4
RSVD_NCTF
AA13
VSS
AA14
VSS
AA16
VSS
AA18
VSS
AA2
VSS
AA22
VSS
AA25
VSS
AA26
VSS
AA29
VSS
AA8
VSS
AB19
VSS
AB21
VSS
AB28
VSS
AB29
VSS
AB30
VSS
AC10
VSS
AC11
VSS
AC19
VSS
AC2
VSS
AC21
VSS
AC28
VSS
AC30
VSS
AD26
VSS
AD5
VSS
AE1
VSS
AE11
VSS
AE13
VSS
AE15
VSS
AE17
VSS
AE22
VSS
AE31
VSS
AF11
VSS
AF17
VSS
AF21
VSS
AF24
VSS
AF28
VSS
AG10
VSS
AG3
VSS
AH18
VSS
AH23
VSS
AH28
VSS
AH4
VSS
AH6
VSS
AH8
VSS
AJ1
RSVD_NCTF
AJ16
VSS
AJ31
RSVD_NCTF
AK1
RSVD_NCTF
AK2
RSVD_NCTF
AK23
VSS
AK30
RSVD_NCTF
AK31
RSVD_NCTF
AL13
VSS
AL19
VSS
AL2
RSVD_NCTF
AL23
VSS
AL29
RSVD_NCTF
AL3
RSVD_NCTF
AL30
RSVD_NCTF
AL9
VSS
B13
VSS
B16
VSS
B19
VSS
B22
VSS
B30
RSVD_NCTF
B31
RSVD_NCTF
B5
VSS
B9
VSS
C1
RSVD_NCTF
C12
VSS
C21
VSS
C22
VSS
C25
VSS
C31
RSVD_NCTF
D22
VSS
E1
RSVD_NCTF
E10
VSS
E19
VSS
E21
VSS
E25
VSS
E8
VSS
F17
VSS
F19
VSS
PINEVIEW-M_FCBGA8559
PINEVIEW-M_FCBGA8559
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
SCHEMATICS， MB A5122
SCHEMATICS， MB A5122
SCHEMATICS， MB A5122
6 OF 6
6 OF 6
GND
GND
1
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS
401897
401897
401897
1
F24 F28 F4 G15 G17 G22 G27 G31 H11 H15 H2 H21 H25 H8 J11 J13 J15 J4 K11 K13 K19 K26 K27 K28 K30 K4 K8 L1 L13 L18 L22 L24 L25 L29 M28 M3 N1 N13 N18 N24 N25 N28 N4 N5 N8 P13 P14 P16 P18 P19 P21 P3 P4 R25 R7 R8 T11 U22 U23 U24 U27 V14 V16 V18 V28 V29 W13 W2 W23 W25 W26 W28 W30 W4 W5 W6 W7 Y28 Y3 Y4
T29
C
C
C
of
of
of
738Monday, September 20, 2010
738Monday, September 20, 2010
738Monday, September 20, 2010
5
PCI
SRC
CPU
CLKSEL1
0
FSA
CLKSEL0
MHz
266
MHz
1000
MHz
MHz
33.30
14.318 96.0 48.0
DOT_96 MHz
USB MHz
FSC FSB REF
CLKSEL2
0 1000 133 33.31 14.318 96.0 48.0
0 1001 200 33.30 14.318 96.0 48.0
0 1001 166 33.31 14.318 96.0 48.0
D D
1 1000 333 33.30 14.318 96.0 48.0
1 1000 100 33.31 14.318 96.0 48.0
1 1001 400 33.30 14.318 96.0 48.0
111
Reserved
Normal Power Low Power
R477 @ Stuff R478 R479 R480 R483
C C
CPU_BSEL06
CPU_BSEL16
B B
CPU_BSEL26
Stuff Stuff
@ @
+1.05VS
R482
R482
2.2K_0402_5%
2.2K_0402_5%
FSA
FSB
FSC
1 2
R86
R86 0_0402_5%
0_0402_5%
R486
R486 1K_0402_5%
1K_0402_5%
1 2
R487
R487 0_0402_5%
0_0402_5%
R490
R490
10K_0402_5%
10K_0402_5%
1 2
R104
R104 0_0402_5%
0_0402_5%
12
+1.05VS
12
+1.05VS
12
7/22 Add R242 to R253 for Intel request
A A
2010.03.23 Change Y1 to 5 x3.2 size SJ114P3M720->SJ100009R00
5
@
@ Stuff Stuff
12
R481
R481 470_0402_5%
470_0402_5%
8/24 Change net name to FSB for U3.2
12
12
12
12
12
14.31818MHZ 20PF 7A14300003
14.31818MHZ 20PF 7A14300003
7/13 Add 33pF to GND for RF request
R484
@R484
@
7/21 Reserve 33pF to GND for RF request
1K_0402_5%
1K_0402_5%
8/27 C303, C324, C325, C326, C327 to GND for RF request
+3VS
7/22 Add R241 pull up to +3VS for RF Intel request
R485
R485 470_0402_5%
470_0402_5%
R488
@R488
@
0_0402_5%
0_0402_5%
+3VS
8/14 Add R250 pull up for Intel request
R489
R489 470_0402_5%
470_0402_5%
R491
@R491
@
0_0402_5%
0_0402_5%
C147 22P_0402_50V8JC147 22P_0402_50V8J
C148 22P_0402_50V8JC148 22P_0402_50V8J
12
Y1
Y1
Routing the trace at least 10mil
R65
R65
1 2
R608
R608
1 2
CLK_XTAL_IN
CLK_XTAL_OUT
+1.5VM_CK505
+1.05VM_CK505
+1.5VM_CK505
H_STP_CPU#
10K_0402_5%
10K_0402_5%
H_STP_PCI#_R
10K_0402_5%
10K_0402_5%
For ITP_EN, 0 =SRC8/SRC8#; 1 = ITP/ITP#
For PCI4_SEL, 0 = Pin24/25 : DOT96 / DOT96# Pin28/29 : LCDCLK / LCDCLK#
For PCI2_TME:0=Overclocking of CPU and SRC allowed (ICS only) 1=Overclocking of CPU and SRC NOT allowed
4
+3VM_CK505
R81
R81
+3VS
1 2
0_0603_5%
0_0603_5%
MP@
MP@
3/30 R81, R477, change p/n SM01000B200->SD013000080
R82
R82
1 2
+1.05VS
FBMH1608HM601-T_0603
FBMH1608HM601-T_0603
7/13 For RF request
R477
LOW@R477
LOW@
+1.5VS
1 2
0_0603_5%
0_0603_5%
7/13 For RF request
+3VM_CK505
R478
NORMAL@ R478
NORMAL@
LOW@R483
LOW@
NORMAL@ R479
NORMAL@
LOW@R480
LOW@
1 2
0_0603_5%
0_0603_5%
R483
1 2
0_0603_5%
0_0603_5%
R479
1 2
0_0603_5%
0_0603_5%
R480
1 2
0_0603_5%
0_0603_5%
+3VM_1.5VM_R
7/13 For RF request
3/30 R91, R92, change p/n 22 -> 10 ohm
CLK_48M_CR21 CLK_PCH_48M11
CLK_PCH_14M12
VGATE12,23,33
H_STP_CPU#12
H_STP_PCI#12
CLK_PCI_DDR16,24
CLK_PCI_LPC23
7/13 Add 33pF to GND for RF request
1 2
CLK_PCI_PCH10
1 = Pin24/25 : SRC_0 / SRC_0# Pin28/29 : 27M/27M_SS
ITP_EN PCI2_TME
R113
R113 10K_0402_5%
10K_0402_5%
PCI4_SEL
R114
R114 10K_0402_5%
10K_0402_5%
1 2
4
250 mA
1
C126
C126 10U_0805_10V4Z
10U_0805_10V4Z
2
+1.05VM_CK505
80 mA
1
C134
C134 10U_0805_10V4Z
10U_0805_10V4Z
2
+1.5VM_CK505
1
C942
C942
2
3/30 RT, LP= SA00003H730 , 1nd gerber out review
10U_0805_10V4Z
10U_0805_10V4Z
IDT, NP=SA000020H10 , 2nd,
1
C943
C943
C944
C944
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+1.05VM_1.5VM_R
1
C946
C946
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
R92 10_0402_5%R92 10_0402_5%
1 2
R91 10_0402_5%R91 10_0402_5%
1 2
1 2
C143 22P_0402_50V8JC143 22P_0402_50V8J
1 2
1 2
C868 22P_0402_50V8JC868 22P_0402_50V8J
R427 0_0402_5%@R427 0_0402_5%@
1 2
1
C127
C127
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
4/13 after PVT SMT, R82: SM01000B200 ->SM010007Z00
1
C135
C135
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
SA00003H610 (ICS :CS9LVRS387AKLFT MLF)
Low power CLK Gen.
+3VM_CK505
1
1
C945
C945
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+1.05VM_CK505
@
@
C947
C947
47P_0402_50V8J
47P_0402_50V8J
FSA FSB FSC
R9333_0402_5% R9333_0402_5%
VGATE
H_STP_CPU# H_STP_PCI#_R
CLK_XTAL_IN
R10333_0402_5% R10333_0402_5%
R10733_0402_5% R10733_0402_5% R10833_0402_5% R10833_0402_5%
CLK_XTAL_OUT
CLK_PCI_DDR_R
CLK_PCI_DDR_R PCI2_TME
PCI4_SEL
PCI4_SEL ITP_EN
ITP_EN
1 2
C144 22P_0402_50V8JC144 22P_0402_50V8J
1 2
1 2
C145 22P_0402_50V8JC145 22P_0402_50V8J
1 2 1 2
1 2
C146 22P_0402_50V8JC146 22P_0402_50V8J
+3VS
R112
R112 10K_0402_5%
10K_0402_5%
1 2
@
@
R115
R115 10K_0402_5%
10K_0402_5%
1 2
3
1
C128
C128
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
C136
C136
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
C129
C129
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
C137
C137
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
C130
@ C130
@
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
C138
C138
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
C131
@ C131
@
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
C139
C139
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2
1
C132
@ C132
@
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
C140
@ C140
@
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
8/27 Delete C93, C94, C95, C102 for low power CLK GEN
7/21 Delete C296, C297 for RF request 7/13 Add 22pF to gnd and close to U3 for RF request
U4
@ U4
@
55
VDD_SRC
6
VDD_REF
12
VDD_PCI
72
VDD_CPU
19
VDD_48
27
VDD_PLL3
66
VDD_CPU_IO
31
VDD_PLL3_IO
62
VDD_SRC_IO
52
VDD_SRC_IO
23
VDD_IO
38
VDD_SRC_IO
20
USB_0/FS_A
2
FS_B/TEST_MODE
7
REF_0/FS_C/TEST_
8
REF_1
1
CKPWRGD/PD#
11
NC
53
CPU_STOP#
54
PCI_STOP#
5
XTAL_IN
4
XTAL_OUT
13
PCI_1
14
PCI_2
15
PCI_3
16
PCI_4/SEL_LCDCL
17
PCIF_5/ITP_EN
18
VSS_PCI
3
VSS_REF
22
VSS_48
26
VSS_IO
69
VSS_CPU
30
VSS_PLL3
34
VSS_SRC
59
VSS_SRC
42
VSS_SRC
73
VSS
ICS9LVRS387AKLFT MLF
ICS9LVRS387AKLFT MLF
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
7/21 Reserve 22pF to gnd and close to U3 for RF request
CPU_0#
CPU_1#
SRC_0/DOT_96
SRC_0#/DOT_96#
LCDCLK/27M
LCDCLK#/27M_SS
SRC_2#
SRC_3#
SRC_4#
SRC_6#
SRC_7#
SRC_8/CPU_ITP
SRC_8#/CPU_ITP#
SRC_9#
SRC_10
SRC_10#
SRC_11
SRC_11#
CLKREQ_3# CLKREQ_4# CLKREQ_6# CLKREQ_7#
CLKREQ_9# SLKREQ_10# CLKREQ_11#
USB_1/CLKREQ_A#
2009/10/21 2012/10/21
2009/10/21 2012/10/21
2009/10/21 2012/10/21
9
SDA
10
SCL
71
CPU_0
70 68
CPU_1
67
24 25
28 29
32
SRC_2
33
35
SRC_3
36
39
SRC_4
40
57
SRC_6
56
61
SRC_7
60
64 63
44
SRC_9
45
50 51
48 47
37 41 58 65 43 49 46 21
Compal Secret Data
Compal Secret Data
Compal Secret Data
CLK_SMBDATA CLK_SMBCLK
CLK_CPU_BCLK CLK_CPU_BCLK# CLK_CPU_HPLCLK CLK_CPU_HPLCLK#
CPU_DREFCLK CPU_DREFCLK#
CPU_SSCDREFCLK CPU_SSCDREFCLK#
CLK_CPU_EXP CLK_CPU_EXP#
CLK_PCIE_SATA CLK_PCIE_SATA#
CLK_PCIE_WLAN CLK_PCIE_WLAN#
CLK_PCIE_LAN CLK_PCIE_LAN#
CLK_PCIE_PCH CLK_PCIE_PCH#
CLK_PCIE_WWAN CLK_PCIE_WWAN#
WLAN_CLKREQ#
LAN_CLKREQ#
WWAN_CLKREQ#
7/21 Change WWAN_CLKREQ# from REQ4 to REQ11
Deciphered Date
Deciphered Date
Deciphered Date
2
C133
C133 47P_0402_50V8J
47P_0402_50V8J
7/13 For RF request
C141
C141 47P_0402_50V8J
47P_0402_50V8J
CLK_SMBDATA 9,16 CLK_SMBCLK 9,16
CLK_CPU_BCLK 6 CLK_CPU_BCLK# 6 CLK_CPU_HPLCLK 6 CLK_CPU_HPLCLK# 6
CPU_DREFCLK 6 CPU_DREFCLK# 6
CPU_SSCDREFCLK 6 CPU_SSCDREFCLK# 6
CLK_CPU_EXP 5 CLK_CPU_EXP# 5
CLK_PCIE_SATA 10 CLK_PCIE_SATA# 10
CLK_PCIE_WLAN 16 CLK_PCIE_WLAN# 16
CLK_PCIE_LAN 22 CLK_PCIE_LAN# 22
CLK_PCIE_PCH 11 CLK_PCIE_PCH# 11
CLK_PCIE_WWAN 16 CLK_PCIE_WWAN# 16
WLAN_CLKREQ# 16
LAN_CLKREQ# 22
WWAN_CLKREQ# 16
1
CPU_SSCDREFCLK CPU_SSCDREFCLK#
C940
1
@C940
@
33P_0402_50V8K
33P_0402_50V8K
2
C941
1
@C941
@
33P_0402_50V8K
33P_0402_50V8K
2
7/13 Add 33pFfor RF request 7/21 Reserve 33pFfor RF request
+3VS
R83
PCH_SMBDATA12
PCH_SMBCLK12
2.2K_0402_5%
2.2K_0402_5%
Q1A
Q1A
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
6 1
+3VS
3
Q1B 2N7002DW-T/R7_SOT363-6Q1B 2N7002DW-T/R7_SOT363-6
R83
2 5
4
R84
R84
2.2K_0402_5%
2.2K_0402_5%
CLK_SMBDATA
CLK_SMBCLK
SRC PORT LIST
PORT
SRC0 SRC2 SRC3 SRC4 SRC6 SRC7 SRC8 SRC9 SRC10 SRC11
WLAN_CLKREQ# WWAN_CLKREQ# LAN_CLKREQ#
DEVICE
CPU_DREFCLK CPU_EXP
PCIE_SATA PCIE_WLAN
PCIE_LAN PCIE_PCH PCIE_WWAN
R99 10K_0402_5%R99 10K_0402_5% R100 10K_0402_5%R100 10K_0402_5% R101 10K_0402_5%R101 10K_0402_5%
12 12 12
REQ PORT LIST
DEVICEPORT
REQ_3#
REQ_4# REQ_6# REQ_7# REQ_9# REQ_10# REQ_11# REQ_A#
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
PEIC_WLAN
PCIE_LAN
PEIC_WWAN
SCHEMATICS， MB A5122
SCHEMATICS， MB A5122
SCHEMATICS， MB A5122 401897
401897
401897
1
of
838Monday, September 20, 2010
of
838Monday, September 20, 2010
of
838Monday, September 20, 2010
+3VS
C
C
C
5
DDR_A_DQS#[0..7]5
DDR_A_D[0..63]5
DDR_A_DM[0..7]5
DDR_A_DQS[0..7]5
DDR_A_MA[0..14]5
D D
+1.8V
2
2
C99
C99
C100
C100
C101
C101
1
1
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
1
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C115
C115
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
RP1
RP1
1 8 2 7 3 6 4 5
RP3
RP3
1 8 2 7 3 6 4 5
RP5
RP5
1 8 2 7 3 6 4 5
R609
R609
1 2
47_0402_5%
47_0402_5% R79
R79
1 2
47_0402_5%
47_0402_5% R80
R80
1 2
47_0402_5%
47_0402_5%
C108
C108
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
+0.9VS
+
+
@
@
C C
+0.9VS
1
C112
C112
C111
C111
B B
A A
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C107
C107
C106
C106
2
220U_B2_2.5VM_R35
220U_B2_2.5VM_R35
Layout Note: Place one cap close to every 2 pullup resistors terminated to +0.9VS
1
1
C114
C114
C113
C113
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
M_ODT1 DDR_CS1# DDR_A_CAS# DDR_A_WE#
47_0804_8P4R_5%
47_0804_8P4R_5%
DDR_A_MA8 DDR_A_MA9
DDR_A_MA12
DDR_A_MA5
47_0804_8P4R_5%
47_0804_8P4R_5%
DDR_A_BS1 DDR_A_MA0 DDR_A_MA2 DDR_A_MA6
47_0804_8P4R_5%
47_0804_8P4R_5%
DDR_CKE1 DDR_A_BS2 DDR_CKE0
5
2
1
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
C109
C109
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C116
C116
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
C102
C102
1
2
C117
C117
2
1
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
C110
C110
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
RP2
RP2
RP4
RP4
RP6
RP6
C103
C103
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C118
C118
0.1U_0402_16V4Z
0.1U_0402_16V4Z
DDR_A_BS0
18
DDR_A_MA10
27
DDR_A_MA1
36
DDR_A_MA3
45
M_ODT0
18
DDR_A_MA13
27
DDR_CS0#
36
DDR_A_RAS#
45
DDR_A_MA4
18
DDR_A_MA11
27
DDR_A_MA7
36
DDR_A_MA14
45
2
1
1
C119
C119
2
Layout Note: Place near JDDR1
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C120
C120
4
1
1
C121
C121
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
4
+1.8V
1
CZ03
CZ03
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
Add 4PCS CAP on 1.8V for EMI request
3/27 add CZ03, CZ04 for EMI request
1
1
1
C124
C124
C123
C123
C122
C122
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
Layout Note: Place these resistor closely DIMMA,all trace length<1000 mil
Layout Note: Place these resistor closely DIMMA,all trace length Max=1000 mil
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
CZ04
CZ04
2
@
@
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C142
C142
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
R74
R74
1K_0402_1%
1K_0402_1%
R75
R75
1K_0402_1%
1K_0402_1%
+DIMM_VREF
C104
C104
1
C155
C155
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C150
C150
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
3
+1.8V
12
+DIMM_VREF
12
Share +DIMM_VREF for
1.DDRII VREF
2.GMCH SM_VREF_0 SM_VREF_1
20mils
1
C105
C105
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
2
1
1
C158
C158
C157
C157
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C153
C153
1
C154
C154
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
3
1
C152
C152
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C156
C156
C151
C151
1
2
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+DIMM_VREF
DDR_CKE05
DDR_A_BS25
DDR_A_BS05
DDR_A_CAS#5
DDR_CS1#5
M_ODT15
CLK_SMBDATA8,16
CLK_SMBCLK8,16
+3VS
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2009/04/07 2012/10/21
2009/04/07 2012/10/21
2009/04/07 2012/10/21
DDR_A_D0 DDR_A_D1
DDR_A_DQS#0 DDR_A_DQS0
DDR_A_D2 DDR_A_D3
DDR_A_D9 DDR_A_D8
DDR_A_DQS#1 DDR_A_DQS1
DDR_A_D10 DDR_A_D11
DDR_A_D28 DDR_A_D29
DDR_A_DQS#3 DDR_A_DQS3
DDR_A_D30 DDR_A_D31
DDR_A_D16 DDR_A_D17
DDR_A_DM2
DDR_A_D18 DDR_A_D19
DDR_CKE0
DDR_A_BS2 DDR_A_MA12
DDR_A_MA9 DDR_A_MA8
DDR_A_MA5 DDR_A_MA3 DDR_A_MA1
DDR_A_MA10 DDR_A_BS0 DDR_A_WE#
DDR_A_CAS# DDR_CS1#
M_ODT1 DDR_A_D33
DDR_A_D32 DDR_A_DQS#4
DDR_A_DQS4 DDR_A_D39
DDR_A_D34 DDR_A_D41
DDR_A_D40 DDR_A_DM5 DDR_A_D42
DDR_A_D43 DDR_A_D48
DDR_A_D49
DDR_A_DQS#6 DDR_A_DQS6
DDR_A_D50 DDR_A_D51
DDR_A_D56 DDR_A_D57
DDR_A_DM7 DDR_A_D62
DDR_A_D59 CLK_SMBDATA
CLK_SMBCLK
1
C125
C125
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
Compal Secret Data
Compal Secret Data
Compal Secret Data
1
C1063
C1063
2
Deciphered Date
Deciphered Date
Deciphered Date
2
+1.8V
JDDR1
JDDR1
1 3 5 7 9
11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97
99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199
201
FOX_AS0A426-N4SN-7F_200P
FOX_AS0A426-N4SN-7F_200P
CONN@
CONN@
2
VREF VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS
VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 NC VSS DQ26 DQ27 VSS CKE0 VDD NC BA2 VDD A12 A9 A8 VDD A5 A3 A1 VDD A10/AP BA0 WE# VDD CAS# NC/S1# VDD NC/ODT1 VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS NC,TEST VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SDA SCL VDDSPD
G1
DIMMA
VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7
VSS DQ12 DQ13
VSS
DM1
VSS
CK0 CK0#
VSS DQ14 DQ15
VSS
VSS DQ20 DQ21
VSS
DM2
VSS DQ22 DQ23
VSS DQ28 DQ29
VSS
DQS3#
DQS3
VSS DQ30 DQ31
VSS
NC/CKE1
VDD
NC/A15 NC/A14
VDD
VDD
VDD
BA1 RAS#
VDD ODT0
NC/A13
VDD
VSS DQ36 DQ37
VSS
DM4
VSS DQ38 DQ39
VSS DQ44 DQ45
VSS
DQS5#
DQS5
VSS DQ46 DQ47
VSS DQ52 DQ53
VSS
CK1 CK1#
VSS
DM6
VSS DQ54 DQ55
VSS DQ60 DQ61
VSS
DQS7#
DQS7
VSS DQ62 DQ63
VSS
SA0
SA1
1
+1.8V
2
DDR_A_D5
4
DDR_A_D4
6 8
DDR_A_DM0
10 12
DDR_A_D6
14
DDR_A_D7
16 18
DDR_A_D12
20
DDR_A_D13
22 24
DDR_A_DM1
26 28
M_CLK_DDR0
30
M_CLK_DDR#0
32 34
DDR_A_D14
36
DDR_A_D15
38 40
42
DDR_A_D24
44
DDR_A_D25
46 48 50
NC
A11
A7 A6
A4 A2 A0
S0#
NC
G2
DDR_A_DM3
52 54
DDR_A_D26
56
DDR_A_D27
58 60
DDR_A_D20
62
DDR_A_D21
64 66
DDR_A_DQS#2
68
DDR_A_DQS2
70 72
DDR_A_D22
74
DDR_A_D23
76 78
DDR_CKE1
80 82 84
DDR_A_MA14
86 88
DDR_A_MA11
90
DDR_A_MA7
92
DDR_A_MA6
94 96
DDR_A_MA4
98
DDR_A_MA2
100
DDR_A_MA0
102 104
DDR_A_BS1
106
DDR_A_RAS#
108
DDR_CS0#
110 112
M_ODT0
114
DDR_A_MA13
116 118 120 122
DDR_A_D36
124
DDR_A_D37
126 128
DDR_A_DM4
130 132
DDR_A_D38
134
DDR_A_D35
136 138
DDR_A_D44
140
DDR_A_D45
142 144
DDR_A_DQS#5
146
DDR_A_DQS5
148 150
DDR_A_D46
152
DDR_A_D47
154 156
DDR_A_D52
158
DDR_A_D53
160 162
M_CLK_DDR1
164
M_CLK_DDR#1
166 168
DDR_A_DM6
170 172
DDR_A_D54
174
DDR_A_D55
176 178
DDR_A_D60
180
DDR_A_D61
182 184
DDR_A_DQS#7
186
DDR_A_DQS7
188 190
DDR_A_D58
192
DDR_A_D63
194 196
R77 10K_0402_5%R77 10K_0402_5%
198 200
202
1 2
R78 10K_0402_5%R78 10K_0402_5%
1 2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
M_CLK_DDR0 5 M_CLK_DDR#0 5
R76
R76
1 2
0_0402_5%
0_0402_5%
MP@
MP@
DDR_CKE1 5
DDR_A_BS1 5 DDR_A_RAS# 5 DDR_CS0# 5DDR_A_WE#5
M_ODT0 5
M_CLK_DDR1 5 M_CLK_DDR#1 5
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
SCHEMATICS， MB A5122
SCHEMATICS， MB A5122
SCHEMATICS， MB A5122
401897
401897
401897
1
PM_EXTTS#0 6
938Monday, September 20, 2010
938Monday, September 20, 2010
938Monday, September 20, 2010
C
C
C
of
of
of
+3VS
R539 8.2K_0402_5%R539 8.2K_0402_5%
1 2
R540 8.2K_0402_5%R540 8.2K_0402_5%
1 2
+3VS
D D
+3VS
+3VS
+3VS
C C
+3VS
B B
RP7
RP7
1 8 2 7 3 6 4 5
8.2K_0804_8P4R_5%
8.2K_0804_8P4R_5%
RP8
RP8
1 8 2 7 3 6 4 5
8.2K_0804_8P4R_5%
8.2K_0804_8P4R_5%
RP16
RP16
1 8 2 7 3 6 4 5
8.2K_0804_8P4R_5%
8.2K_0804_8P4R_5% RP10
RP10
1 8 2 7 3 6 4 5
8.2K_0804_8P4R_5%
8.2K_0804_8P4R_5%
RP11
RP11
1 8 2 7 3 6 4 5
8.2K_0804_8P4R_5%
8.2K_0804_8P4R_5%
5
PCI_PIRQB# PCI_PIRQF# PCI_PIRQC# PCI_PIRQA#
PCI_PIRQE# PCI_PLOCK# PCI_PIRQG# PCI_IRDY#
PCI_SERR# PCI_PERR# PCI_TRDY# GPIO1
GPIO22 PCI_DEVSEL# PCI_PIRQD# PCI_PIRQH#
REQ2# REQ1# PCI_STOP# PCI_FRAME#
RSVD01 RSVD02
CLK_PCI_PCH8 PCI_RST#23
4
100K_0402_5%
100K_0402_5%
For EC request.
R543
R543
10K_0402_5%
10K_0402_5%
@
@
@
@
1 2
CLK_PCI_PCH PCI_RST#
12
R541
R541
R544
R544 10K_0402_5%
10K_0402_5%
@
@
R545
R545 1K_0402_5%
1K_0402_5%
+3VS
PCI_DEVSEL#
PCI_IRDY# PCI_SERR#
PCI_STOP# PCI_PLOCK# PCI_TRDY# PCI_PERR# PCI_FRAME#
REQ1# REQ2#
GPIO22 GPIO1
PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD# PCI_PIRQE# PCI_PIRQF# PCI_PIRQG# PCI_PIRQH#
RSVD01 RSVD02
R551
R551
1 2
8.2K_0402_5%
8.2K_0402_5%
R12 AE20 AD17 AC15 AD18
Y12 AA10 AA12
Y10 AD15
W10
V12 AE21 AE18 AD19
U12 AC17
AB13 AC13 AB15
Y14 AB16
AE24 AE23
AA14
V14
AD16 AB11 AB10
AD23
B15 A23 C22
B11
A10 D10 A16
A18 E16
G16 A20
G14 C15
H10
D11
M13
A5
J12
B7
F14
A8
A2 C9
B2 D7 B3
E8 D6 H8 F8
K9
U15A
U15A
PAR DEVSEL# PCICLK PCIRST# IRDY# PME# SERR# STOP# PLOCK# TRDY# PERR# FRAME#
GNT1# GNT2#
REQ1# REQ2#
GPIO48/STRAP1# GPIO17/STRAP2# GPIO22 GPIO1
PIRQA# PIRQB# PIRQC# PIRQD# PIRQE#/GPIO2 PIRQF#/GPIO3 PIRQG#/GPIO4 PIRQH#/GPIO5
STRAP0# RSVD01 RSVD02
TIGERPOINT_ES1_BGA360
TIGERPOINT_ES1_BGA360
U15C
U15C
RSVD03 RSVD04 RSVD05 RSVD06 RSVD07 RSVD08 RSVD09 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 RSVD15 RSVD16 RSVD17 RSVD18
RSVD19 RSVD20 RSVD21 RSVD22 RSVD23
RSVD24 RSVD25 RSVD26
RSVD27 RSVD28
RSVD29 RSVD30 RSVD31
GPIO36
3
4/13 PVT SMT U15: SA000039N80 ->SA000039N60
TGP
TGP
4/23 pre-MP SMT U15: SA000039N60 -> SA000039NA0
PCI
PCI
TGP
TGP
SATA
SATA
HOST
HOST
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8
AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31
C/BE0# C/BE1# C/BE2# C/BE3#
1
1
SATA0RXN SATA0RXP SATA0TXN SATA0TXP SATA1RXN SATA1RXP SATA1TXN SATA1TXP
SATA_CLKN SATA_CLKP
SATARBIAS#
SATARBIAS
SATALED#
A20GATE
A20M#
CPUSLP#
IGNNE#
INIT3_3V#
INIT# INTR
FERR#
NMI
RCIN#
SERIRQ
SMI#
STPCLK#
THRMTRIP#
B22 D18 C17 C18 B17 C19 B18 B19 D16 D15 A13 E14 H14 L14 J14 E10 C11 E12 B9 B13 L12 B8 A3 B5 A6 G12 H12 C8 D9 C7 C1 B1
H16 M15 C13 L16
AE6 AD6 AC7 AD7 AE8 AD8 AD9 AC9
AD4 AC4
AD11 AC11 AD25
U16 Y20 Y21 Y18 AD21 AC25 AB24 Y22 T17 AC21 AA16 AA21 V18 AA20
SATARBIAS
GATEA20 H_A20M#
H_IGNNE# H_INIT#
H_INTR H_FERR# H_NMI EC_KBRST# SERIRQ H_SMI# H_STPCLK#
CLK_PCIE_SATA# 8 CLK_PCIE_SATA 8
R547 24.9_0402_1%R547 24.9_0402_1%
SATALED# 25
GATEA20 23 H_A20M# 6
H_IGNNE# 6 H_INIT# 6
H_INTR 6 H_FERR# 6 H_NMI 6 EC_KBRST# 23 SERIRQ 23 H_SMI# 6 H_STPCLK# 6
2
PCI_RST#
CLK_PCI_PCH
@
@
10_0402_5%
10_0402_5%
8.2P_0402_50V8D
8.2P_0402_50V8D
For EMI, close to TigerPoint
SATA_IRX_C_DTX_N0 18 SATA_IRX_C_DTX_P0 18 SATA_ITX_DRX_N0 18 SATA_ITX_DRX_P0 18
Please closed Tiger point PIN within 500 mils
+1.05VS
12
R552
R552 56_0402_5%
56_0402_5%
R110 to be within 1" from the Tiger Point chipset.
H_THERMTRIP# 6
1
12
1
2
1
2
C1015
C1015
0.1U_0402_16V4Z
0.1U_0402_16V4Z
H_FERR#
@
@
+1.05VS
R546
R546 56_0402_5%
56_0402_5%
R542
R542
@
@
C1016
C1016
R111 closed TigerPoint within 1"
+3VS
R548
SATALED#
GATEA20
SERIRQ
R548
10K_0402_5%
10K_0402_5%
R549
R549 10K_0402_5%
10K_0402_5% R550
R550
1 2
8.2K_0402_5%
8.2K_0402_5%
3
A A
5
4
TIGERPOINT_ES1_BGA360
TIGERPOINT_ES1_BGA360
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2009/10/21 2012/10/21
2009/10/21 2012/10/21
2009/10/21 2012/10/21
3
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
2
Date: Sheet
Compal Electronics, Inc.
SCHEMATICS， MB A5122
SCHEMATICS， MB A5122
SCHEMATICS， MB A5122
401897
401897
401897
1
of
10 38Monday, September 20, 2010
of
10 38Monday, September 20, 2010
of
10 38Monday, September 20, 2010
C
C
C
5
4
3
2
1
D D
TGP
U15B
U15B
DMI_TXN05 DMI_TXP05 DMI_RXN05 DMI_RXP05 DMI_TXN15 DMI_TXP15 DMI_RXN15 DMI_RXP15
C C
WLAN
LAN
WWLAN
B B
PCIE_PTX_C_IRX_N216 PCIE_PTX_C_IRX_P216
PCIE_ITX_C_PRX_N216
PCIE_ITX_C_PRX_P216
PCIE_PTX_C_IRX_N322
PCIE_PTX_C_IRX_P322 PCIE_ITX_C_PRX_N322 PCIE_ITX_C_PRX_P322 PCIE_PTX_C_IRX_N416
PCIE_PTX_C_IRX_P416 PCIE_ITX_C_PRX_N416 PCIE_ITX_C_PRX_P416
C1017 0.1U_0402_10V6KC1017 0.1U_0402_10V6K C1018 0.1U_0402_10V6KC1018 0.1U_0402_10V6K
C1019 0.1U_0402_10V6KC1019 0.1U_0402_10V6K C1020 0.1U_0402_10V6KC1020 0.1U_0402_10V6K
C1021 0.1U_0402_10V6K@C1021 0.1U_0402_10V6K@ C1022 0.1U_0402_10V6K@C1022 0.1U_0402_10V6K@
Please closed Tiger point PIN within 500 mils
CLK_PCIE_PCH#8 CLK_PCIE_PCH8
12 12
12 12
12 12
+1.5VS
PCIE_PTX_C_IRX_N2 PCIE_PTX_C_IRX_P2
PCIE_ITX_PRX_N2
PCIE_ITX_PRX_P2 PCIE_PTX_C_IRX_N3 PCIE_PTX_C_IRX_P3
PCIE_ITX_PRX_N3
PCIE_ITX_PRX_P3 PCIE_PTX_C_IRX_N4 PCIE_PTX_C_IRX_P4
PCIE_ITX_PRX_N4
PCIE_ITX_PRX_P4
R555 24.9_0402_1%R555 24.9_0402_1%
1 2
R23
DMI0RXN
R24
DMI0RXP
P21
DMI0TXN
P20
DMI0TXP
T21
DMI1RXN
T20
DMI1RXP
T24
DMI1TXN
T25
DMI1TXP
T19
DMI2RXN
T18
DMI2RXP
U23
DMI2TXN
U24
DMI2TXP
V21
DMI3RXN
V20
DMI3RXP
V24
DMI3TXN
V23
DMI3TXP
K21
PERN1
K22
PERP1
J23
PETN1
J24
PETP1
M18
PERN2
M19
PERP2
K24
PETN2
K25
PETP2
L23
PERN3
L24
PERP3
L22
PETN3
M21
PETP3
P17
PERN4
P18
PERP4
N25
PETN4
N24
PETP4
H24
DMI_ZCOMP
J22
DMI_IRCOMP
W23
DMI_CLKN
W24
DMI_CLKP
TIGERPOINT_ES1_BGA360
TIGERPOINT_ES1_BGA360
TGP
USB20_N0
H7
USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P
DMI PCI-E
DMI PCI-E
USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P
OC0# OC1# OC2# OC3#
USB
USB
OC4# OC5#/GPIO29 OC6#/GPIO30 OC7#/GPIO31
USBRBIAS
USBRBIAS#
CLK48
2
2
USB20_P0
H6
USB20_N1
H3
USB20_P1
H2
USB20_N2
J2
USB20_P2
J3
USB20_N3
K6
USB20_P3
K5
USB20_N4
K1
USB20_P4
K2
USB20_N5
L2
USB20_P5
L3
USB20_N6
M6
USB20_P6
M5
USB20_N7
N1
USB20_P7
N2
USB_OC#0_1_D
D4
USB_OC#0_1_D
C5
USB_OC#2
D3
USB_OC#3
D2
USB_OC#4_D
E5
SLP_CHG_M3
E6
SLP_CHG_M4
C2
USB_OC#7
C3
G2 G3
F4
22.6_0402_1%
22.6_0402_1%
CLK_PCH_48M
12
R554
R554 33_0402_5%
33_0402_5%
@
@
1
C1023
C1023
@
@
22P_0402_50V8J
22P_0402_50V8J
2
For EMI, Close to TigerPoint
R553
R553
R558 0_0402_5%
R558 0_0402_5%
01/12 Change power from +3VALW to +3V_EC for leakage issue if EC power change to +3VL
USB20_N0 17 USB20_P0 17 USB20_N1 17 USB20_P1 17 USB20_N2 18 USB20_P2 18 USB20_N3 21 USB20_P3 21 USB20_N4 17 USB20_P4 17 USB20_N5 16 USB20_P5 16 USB20_N6 16 USB20_P6 16 USB20_N7 15 USB20_P7 15
USB2(Right) USB1(Right) BT Card reader USB3(Left) WWAN WLAN CMOS
7/17 Reassign Tiger point USB port for TOSHIBA concern
12/17 SLP_CHG_M3,SLP_CHG_M4 will be no used because it won't support SLP_Charge function.
Please closed Tiger point PIN within 200 mils
CLK_PCH_48M 8
+3V_EC +3V_EC
R556
R556 330K_0402_5%
330K_0402_5%
@
@
@
D42
D42
2 1
CH751H-40PT_SOD323-2
CH751H-40PT_SOD323-2
1 2
MP@
MP@
@
1 2
USB PORT LIST
PORT USB0 USB1 USB2 USB3 USB4 USB5 USB6 USB7
USB_OC#4_DUSB_OC#0_1_D
DEVICE
USB3(Left) BT Card Reader USB2(Right) USB1(Right) WWAN WWAN WLAN CMOS
USB_OC#3 SLP_CHG_M4 USB_OC#0_1_D
10K_0804_8P4R_5%
10K_0804_8P4R_5%
USB_OC#7 USB_OC#2 USB_OC#4_D SLP_CHG_M3
10K_0804_8P4R_5%
10K_0804_8P4R_5%
@
@
D43
D43
2 1
CH751H-40PT_SOD323-2
CH751H-40PT_SOD323-2
1 2
R559 0_0402_5%
R559 0_0402_5%
MP@
MP@
RP12
RP12
4 5 3 6 2 7 1 8
RP13
RP13
4 5 3 6 2 7 1 8
R557
R557 330K_0402_5%
330K_0402_5%
@
@
1 2
Modify
USB2(Right) USB1(Right) BT Card Reader USB3(Left)
WLAN CMOS
+3V_SB
USB_OC#4 17,23USB_OC#0_1 17,23
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2009/10/21 2012/10/21
2009/10/21 2012/10/21
2009/10/21 2012/10/21
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
2
Date: Sheet
Compal Electronics, Inc.
SCHEMATICS， MB A5122
SCHEMATICS， MB A5122
SCHEMATICS， MB A5122
401897
401897
401897
11 38Monday, September 20, 2010
11 38Monday, September 20, 2010
11 38Monday, September 20, 2010
1
C
C
C
of
of
of
5
+3V_SB
R5602.2K_0402_5% R5602.2K_0402_5%
PCH_SMBCLK
1 2
PCH_SMBDATA
R5612.2K_0402_5% R5612.2K_0402_5%
1 2
+3V_SB
D D
10K_0402_5%
10K_0402_5%
8.2K_0402_5%
8.2K_0402_5%
10K_0402_5%
10K_0402_5% 10K_0402_5%
10K_0402_5%
R562
R562
R563
R563 R564
R564 R565
R565
12
12 12
SYS_RST#
ICH_RI# EC_SWI# SLP_CHG#
7/2 For EMI, Close to TigerPoint 9/1 C207 change to SE071100J80 for EMI request
HDA_BITCLK
2
C1024
C1024 10P_0402_50V8J
10P_0402_50V8J
1
12/17 Add Pull high Resistor for GPIO14
+3V_SB
RP14
RP14
10K_0804_8P4R_5%
+3V_SB
+RTCVCC
+3VS
+3VS
10K_0804_8P4R_5%
RP15
RP15
1 8 2 7 3 6 4 5
8.2K_0804_8P4R_5%
8.2K_0804_8P4R_5%
1M_0402_5%
1M_0402_5% 332K_0402_1%
332K_0402_1%
8.2K_0402_5%
8.2K_0402_5%
8.2K_0402_5%
8.2K_0402_5%
8.2K_0402_5%
8.2K_0402_5%
8.2K_0402_5%
8.2K_0402_5%
1K_0402_5%
1K_0402_5%
C C
B B
A A
9/1 R125 change to SM010027780 for EMI request
LINKALERT#
45
GPIO11
36
SMLINK0
27
SMLINK1
18
PCH_LOW_BAT#
R575
R575
1 2
R576
R576
1 2
R585
R585
1 2
3/30 change Y2 p/n SJ132P7K220->SJ132P7K230, gerber out review
GPIO15 GPIO12
EC_LID_OUT#
+RTCVCC
INTRUDER# INTVRMEN
R577
R577
SLPIOVR
R579
R579
PM_CLKRUN#
R580
R580
GPIO0
R581
R581
BT_DET#
MCH_SYNC#
+RTCVCC
1
C1029
C1029
2
C1025
C1025
18P_0402_50V8J
18P_0402_50V8J
12
Y2
Y2
32.768K_1TJS125BJ4A421P
32.768K_1TJS125BJ4A421P
2
NC
3
NC
C1027
C1027
18P_0402_50V8J
18P_0402_50V8J
12
R574
R574
1 2
20K_0402_5%
20K_0402_5%
J1
J1
@
@
2
112
JUMP_43X39
JUMP_43X39 C1028
C1028
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1 2
7/20 Add SLPIOVR pull up 8.2k to +3vs 9/23 Change RP17 to R256, R257, R258 for layout request
1
2
3
1U_0402_6.3V6K
1U_0402_6.3V6K
7/21 Change C156 to 1u for Intel request
HDA_BITCLK19
For EMI, Close to TigerPoint
1
IN
4
OUT
4/16 modify JUMP size and move to DDR2 socket
D6
D6 BAS40-04_SOT23-3
BAS40-04_SOT23-3
HDA_RST#19 HDA_SDIN019
HDA_SDOUT19 HDA_SYNC19 CLK_PCH_14M8
+RTCBATT
+3VL
4
RTCX1
R572
R572
RTCX2
12
10M_0402_5%
10M_0402_5%
PCH_SMBCLK8
PCH_SMBDATA8
3
TGP
U15D
U15D
AA5
LDRQ1#/GPIO23
BITCLK_PCH RST#_PCH
SDOUT_PCH SYNC_PCH
V6
LAD0/FWH0
AA6
LAD1/FWH1
Y5
LAD2/FWH2
W8
LAD3/FWH3
Y8
LDRQ0#
Y4
LFRAME#/FWH4
P6
HDA_BIT_CLK
U2
HDA_RST#
W2
HDA_SDIN0
V2
HDA_SDIN1
P8
HDA_SDIN2
AA1
HDA_SDOUT
Y1
HDA_SYNC
AA3
CLK14
U3
EE_CS
AE2
EE_DIN
T6
EE_DOUT
V3
EE_SHCLK
T4
LAN_CLK
P7
LANR_RSTSYNC
B23
LAN_RST#
AA2
LAN_RXD0
AD1
LAN_RXD1
AC2
LAN_RXD2
W3
LAN_TXD0
T7
LAN_TXD1
U4
LAN_TXD2
W4
RTCX1
V5
RTCX2
T5
RTCRST#
E20
SMBALERT#/GPIO11
H18
SMBCLK
E23
SMBDATA
H21
LINKALERT#
F25
SMLINK0
F24
SMLINK1
R2
SPI_MISO
T1
SPI_MOSI
M8
SPI_CS#
P9
SPI_CLK
R4
SPI_ARB
TIGERPOINT_ES1_BGA360
TIGERPOINT_ES1_BGA360
EPROM
EPROM
PCH_POK
EC_PWROK
LPC_AD023 LPC_AD123 LPC_AD223 LPC_AD323
LPC_FRAME#23
33_0402_5%
33_0402_5%
33_0402_5%
33_0402_5%
R566KC FBMA-11-100505-301T_0402 R566KC FBMA-11-100505-301T_0402
1 2
R567
R567
1 2
R568
R568
1 2
R56933_0402_5% R56933_0402_5%
1 2
12
R571
R571
10_0402_5%@
10_0402_5%@
1
C1026
C1026
4.7P_0402_50V8C@
4.7P_0402_50V8C@
2
RTCRST#
GPIO11 PCH_SMBCLK PCH_SMBDATA LINKALERT# SMLINK0 SMLINK1
3/23 reserve: C1030, U5, short:R586 3/23 reserve: D7A, D7B, R589, Q36, R590, short R587
EC_PWROK6,23 VGATE8,23,33
TGP
LPC
LPC
AUDIO
AUDIO
MP@
MP@
+3VS
@ C1030
@
5
U5
@U5
@
P
B
Y
A
G
TC7SH08FUF_SSOP5
TC7SH08FUF_SSOP5
3
CPUPWRGD/GPIO49
SUS_STAT#/LPCPD#
1
C1030
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
4
LAN
LAN
RTC
RTC
SMB
SMB
SPI
SPI
1 2
R583 10K_0402_5%R583 10K_0402_5%
1 2
R584 10K_0402_5%R584 10K_0402_5%
1 2
R586 0_0402_5%
R586 0_0402_5%
1 2
BMBUSY#/GPIO0
DPRSLPVR
STP_PCI#
STP_CPU#
CLKRUN#
VRMPWRGD MCH_SYNC#
MISC
MISC
PWRBTN#
SUSCLK
SYS_RESET#
PLTRST#
INTRUDER#
RSMRST#
INTVRMEN
SLP_S3# SLP_S4# SLP_S5#
BATLOW#
DPRSTP#
GPIO6 GPIO7 GPIO8
GPIO9 GPIO10 GPIO12 GPIO13 GPIO14 GPIO15
GPIO24 GPIO25 GPIO26 GPIO27 GPIO28
GPIO33 GPIO34 GPIO38 GPIO39
THRM#
WAKE#
PWROK
SPKR
DPSLP# RSVD31
RI#
PCH_POK 6,23
GPIO0
T15
BT_DET#
W16
SLPIOVR
W14
EC_SMI#
K18
EC_SCI#
H19
PCH_ACIN
M17
GPIO12
A24
EC_LID_OUT#
C23
SLP_CHG#
P5
GPIO15
E24 AB20 Y16 AB19 R3
R570 1K_0402_5%R570 1K_0402_5%
C24
BOARD_ID
D19 D20 F22
PM_CLKRUN#
AC19 U14 AC1 AC23 AC24
H_PWRGD
AB22
EC_THERM#
AB17
VGATE
V16
MCH_SYNC#
AC18
PBTN_OUT#
E21
ICH_RI#
H23 G22
EC_CLK
D22
SYS_RST#
G18
PLTRST#
G23
EC_SWI#
C25
INTRUDER#
T8
PCH_POK
U10
PCH_RSMRST#
AC3
INTVRMEN
AD3
SB_SPKR
J16 H20
E25 F21
PCH_LOW_BAT#
B25
H_DPRSTP#
AB23
H_DPSLP#
AA18 F20
2
BT_DET# 18
EC_SMI# 23 EC_SCI# 23
EC_LID_OUT# 23
12/17 SLP_CHG# will be no used and need to Pull high
1 2
T42T42
7/20 Add test point
PM_DPRSLPVR 6 H_STP_PCI# 8 H_STP_CPU# 8
12/31 Add HW Board ID function
2010.04.22 Add C1064 for ESD solution
BT_RST# 18 BT_OFF 18
H_PWRGD 6
EC_THERM# 23
PBTN_OUT# 23
EC_CLK 23
SB_SPKR 19 PM_SLP_S3# 23
PM_SLP_S4# 23 PM_SLP_S5# 23
H_DPRSTP# 6 H_DPSLP# 6
01/11 Reserve EC_CLK for KBC
PLTRST# 6,16,22,24 EC_SWI# 23
PCH_ACIN
PCH_RSMRST#
R588
R588 10K_0402_5%
10K_0402_5%
@D7B
@
BAV99DW-7_SOT363
BAV99DW-7_SOT363
R590
R590
2.2K_0402_5%
2.2K_0402_5%
PLTRST#
C1064
C1064
0.1U_0402_16V4Z
0.1U_0402_16V4Z
8/24 Add R573 pull down for EC request
POK28,30
+3V_SB
R578
R578 330K_0402_5%
330K_0402_5%
1 2
R587 0_0402_5%
R587 0_0402_5%
@
1 2
D7B
@
@
@
4
5
3
12
1
2
2 1
CH751H-40PT_SOD323-2
CH751H-40PT_SOD323-2
MP@
MP@
123
C
C
Q36
Q36
2
6
1
3/31 reserve R610
R573
R573 100K_0402_5%
100K_0402_5%
1 2
2 1
CH751H-40PT_SOD323-2
CH751H-40PT_SOD323-2
CH751H-40PT_SOD323-2
CH751H-40PT_SOD323-2
BOARD_ID
D45
D45
D46
D46
PCH_RSMRST#PCH_POK
21
3/23 add D45, D46
D44
D44
12
E
E
MMBT3906_SOT23-3
MMBT3906_SOT23-3
B
B
1 2
R589
@R589
@
1
4.7K_0402_5%
4.7K_0402_5% D7A
@D7A
@
BAV99DW-7_SOT363
BAV99DW-7_SOT363
ACIN 23,25,29
EC_RSMRST# 23
+3V_SB
RSMRST# circuit
+3V_SB
12
@
@
R610
R610 10K_0402_5%
10K_0402_5%
12
@
@
R611
R611 10K_0402_5%
10K_0402_5%
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2009/10/21 2012/10/21
2009/10/21 2012/10/21
2009/10/21 2012/10/21
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
2
Date: Sheet
Compal Electronics, Inc.
SCHEMATICS， MB A5122
SCHEMATICS， MB A5122
SCHEMATICS， MB A5122
401897
401897
401897
1
12 38Monday, September 20, 2010
12 38Monday, September 20, 2010
12 38Monday, September 20, 2010
C
C
C
of
of
of
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