Compal Electronics LA-5121P KAVAA Buffalo, NB200, NB205 Schematic

A

1 1

B

C

D

E

Compal Confidential

2 2

Buffalo KAVAA

LA-5121P Schematics Document

Intel Diamondville Processor/ Calistoga(945GSE)/ ICH7M

3 3

4 4

A

B

2009-03-10

REV: 1.0

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/11/17 2009/11/17

C

Compal Secret Data

Deciphered Date

D

Title

Size Do cumen t Numb er R ev

Cu stom

Da te: Sheet o f

Compal Electronics, Inc.

Cover Page

KAVAA LA-5121P M/B

1 42Tu esday, M arch 10 , 2009

E

1.0

A

Compal Confidential

B

C

D

E

Model Name : KAVAA
File Name : LA-5121P

1 1

CRT Conn.

page 14

Fan Control

page 28

Intel Diamondville SC

FCBGA8-437 Pins

(22x22mm)

H_ A#( 3.. 31 ) H_ D#( 0..6 3)

FSB

400/533MHz

page 4,5

Intel Calistoga GSE

FC B GA 998

LED Conn.

page 13

2 2

PCIeMini Card
WiMax

USB po rt 4

page 19

PCIeMini Card
WLAN

PCIe po rt 2

page 19

PCIeMini Card
3G

USB po rt 5

page 19

PCIeMini Card
GPS

USB po rt 5

page 19

LVDS

ONE CHANNEL

PCI e 1x [ 2,4]

1.5V 2.5GHz(250MB/s)

(27x27mm)

page 6,7,8,9,10

DMI x 2

USB

5V 480MHz

Intel ICH7M

Thermal Sensor

EMC1402

page 4

Memory BUS(DDRII)

1.8V DDRII 400/533

US B Conn X3

USB port 0,2,7

USB

5V 480MHz

BT conn

USB port 6

page 21

page 20

Clock Generator

SLG8SP556VTR

page 12

200pin DDRII-SO-DIMM

Int. Camera

USB port 1

page 21

Touch Screen conn

BTO USB port 4 ,5

page 20

page 11

BG A -652

PC Ie 1x

RJ45

page 24

3 3

RTC CKT.

page 16

RTL8103EL 10/100M

PCIe po rt 3

Card R eader

RTS5159 2IN1
USB port 3

page 24

page 25

1.5V 2.5GHz(250MB/s)

USB

5V 480MHz

(31x31mm)

page 15,16,17,18

SATA port 0

5V 1.5GHz(150MB/s)

HD Audio

SATA HDD&SSD

page 21

3.3V 24.576MHz/48Mhz

DC/DC Interface CKT.

3.3V 33 MHz

page 30

Power Circuit DC/DC

page 31~37

Debug Port

page 28

Touch Pad

4 4

Power /B

page 29

A

B

page 29

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

ENE KB926 D3

Int.KBD

page 28

LPC BUS

page 26

SPI ROM

page 28

2008/11/17 2009/11/17

C

GSENSOR

page 27

Compal Secret Data

Deciphered Date

Int.

MIC CONN

page 23 page 23 page 23

D

HDA Codec

ALC272-GR

page 22

AMP.

E

TPA6017

page 23

SPK CO NN

page 23

2 42Tu esday, M arch 10 , 2009

MIC CONN

Title

Size Do cumen t Numb er R ev

Da te: Sheet o f

HP CONN

Compal Electronics, Inc.

Block Diagrams

KAVAA LA-5121P M/B

1.0

A

B

C

D

E

Voltage Rails

1 1

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

ON

OFF

OFF OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFFON

OFF+5V_SB 5V power rail for SB

OFF

ON

OFF

OFF

OFF

ON

G3

BTO Option Table

Function

description

explain

BTO

Power Plane Description

VIN

B+

+CPU_CORE

+0.9VS 0.9V switched power rail for DDR terminator

+1.05VS

+1.5VS

+1.8V

+2.5VS 2.5V switched power rail

+3VALW

+3V_SB 3.3V power rail for LAN

+3V_LAN 3.3V power rail for LAN ON

2 2

+3V_WLAN

+3VS

+5VALW

+5VS

+VSB VSB always on power rail ON

+RTCVCC RTC power

Adapter power supply (19V)

AC or battery power rail for power circuit.

Core voltage for CPU

VCCP switched power rail

1.5V switched power rail

1.8V power rail for DDR

3.3V always on power rail

3.3V power rail for LAN ON ON

3.3V switched power rail

5V always on power rail

5V switched power rail

S1 S3 S5

ON ON ON OFF

ON ON ON ON

ON OFF

ON OFF

ON OFF OFF

ON OFF OFF

ON OFF

ON

ON

OFF

ONON

ON

ON

ON

ON

ON

ON

OFF

ON

ON

OFF

ON

ON

ON

ON

ON

STAT E

Full ON

S1(P ower On Suspend)

S3 ( Susp end to RAM)

S4 ( Susp end to Disk)

S5 ( Soft OFF)

Mini PCI -E SL OT

WLAN @ 3GGP S@

WIMA X@

SIGN AL

3GGP SWi-F i WiMax

SLP_ S3#

SLP_ S4#

SLP_ S5#

HIGH HIGH HIGH

HIGH

LOW

LOW LOW

LOWLOW

CAME RA & MIC

CAME RA MIC

3G

3G@

CAM@ MIC@

HIGHHIGHHIGH

HIGH

HIGH

LOW

+VAL W

ON

ON

ON

ON

ON

BLUE TOOTH

BLUE TOOTH

BT@

+V +VS Cloc k

ON

ON

ON

OFF

OFF

ON

OFF

OFF

OFF

STAR

ONON

LOW

OFF

OFF

OFF

G-SE NSOR

POWE R SA VING H DD P ROTECT

STAR @

GSEN SOR@

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

description

explain

BTO

Function

3 3

EC SM Bus1 address

Device

Smart Battery

Address

EC SM Bus2 address

Device

EMC1402

Address

10 01 010 X b00 01 011 X b

ICH7M SM Bus address

Device

Cloc k Generator
(SL G8SP55 6VTR)

DDR DIMMA

4 4

A

Address

1101 001Xb

10 10 000Xb

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/11/17 2009/11/17

C

Compal Secret Data

Deciphered Date

Title

Size Do cumen t Numb er R ev

Cu stom

D

Da te: Sheet o f

Compal Electronics, Inc.

Notes List

KAVAA LA-5121P M/B

3 42Tu esday, M arch 10 , 2009

E

1.0

5

H_ A#[3..1 6]<6>

H_A #3
H_A #4
H_A #5
H_A #6
H_A #7
H_A #8
H_A #9
H_A #10
H_A #11
H_A #12

D D

H_A DSTB#0<6>
H_ REQ# [0..4]<6>

H_ A#[17.. 31]< 6>

C C

H_A DSTB#1<6>

H_A20M#<16>

H_ FERR#<16>

H_ IGNNE#< 16>

H_S TPCLK#<16>

H_ INTR<16>

H_ NMI<16>

H_S MI#<16>

+1.05VS

R11 1K_0402 _5%

1 2

R12 1K_0402 _5%

1 2

R16 1K_0402 _5%

1 2

R17 1K_0402 _5%

1 2

B B

+1.05VS

mou nt R1 8, R1 9 fo r KI Z00 proj ect

R18 1K_0402 _5%@

1 2

R19 1K_0402 _5%@

1 2

R23 1K_0402 _5%@

1 2

R24 1K_0402 _5%@

1 2

R25 1K_0402 _5%@

1 2

R26 1K_0402 _5%@

1 2

R27 1K_0402 _5%@

1 2

R28 1K_0402 _5%@

1 2

R29 1K_0402 _5%@

1 2

H_A #13
H_A #14
H_A #15
H_A #16

H_A DSTB#0

H_A P0

T1

H_R EQ#0

PAD

H_R EQ#1
H_R EQ#2
H_R EQ#3
H_R EQ#4

H_A #17
H_A #18
H_A #19
H_A #20
H_A #21
H_A #22
H_A #23
H_A #24
H_A #25
H_A #26
H_A #27
H_A #28
H_A #29
H_A #30
H_A #31
H_A #32
H_A #33
H_A #34
H_A #35
H_A DSTB#1
H_A P1

T6 PAD

H_A20M#
H_ FERR #
H_ IGNNE # CL K_CPU _BCLK#
H_S TPCLK#
H_ INTR
H_ NMI
H_S MI#

CRB rese rved

12/1 8 Re ser ve f or d ebug close
to S outh Brid ge

H_ FERR #

2/2 5 PVT :M ou nt C4 84~C 495 for E MI r eque st

H_S TPCLK#
H_ INIT#_ R

A A

H_A20M#
H_ IGNNE #
H_D PRSTP#
H_ DPWR #
H_D PSLP#
H_ INTR
H_ NMI
H_S MI#
H_P WRGO OD

12/1 8 Re ser ve f or d ebug close
to C PU

C484 220P_04 02_50V7K

1 2

C485 220P_04 02_50V7K

1 2

C486 220P_04 02_50V7K

1 2

C487 220P_04 02_50V7K

1 2

C488 220P_04 02_50V7K

1 2

C489 220P_04 02_50V7K

1 2

C490 220P_04 02_50V7K

1 2

C491 220P_04 02_50V7K

1 2

C492 220P_04 02_50V7K

1 2

C493 220P_04 02_50V7K

1 2

C494 220P_04 02_50V7K

1 2

C495 220P_04 02_50V7K

1 2

5

U1A

P21

A[3]#

H20

A[4]#

N20

A[5]#

R20

A[6]#

J19

A[7]#

N19

A[8]#

G20

A[9]#

M19

A[10]#

H21

A[11]#

L20

A[12]#

M20

A[13]#

K19

A[14]#

J20

A[15]#

L21

A[16]#

K20

ADSTB[0]#

D17

AP0

N21

REQ[0]#

J21

REQ[1]#

G19

REQ[2]#

P20

REQ[3]#

R19

REQ[4]#

C19

A[17]#

F19

A[18]#

E21

A[19]#

A16

A[20]#

D19

A[21]#

C14

A[22]#

C18

A[23]#

C20

A[24]#

E20

A[25]#

D20

A[26]#

B18

A[27]#

C15

A[28]#

B16

A[29]#

B17

A[30]#

C16

A[31]#

A17

A[32]#

B14

A[33]#

B15

A[34]#

A14

A[35]#

B19

ADSTB[1]#

M18

AP1

U18

A20M#

T16

FERR#

J4

IGNNE#

R16

STPCLK#

T15

LINT0

R15

LINT1

U17

SMI#

D6

NC1

G6

NC2

H6

NC3

K4

NC4

K5

NC5

M15

NC6

L16

NC7

AU8 0586GE 025512_FCBG A437

H_A #32
H_A #33
H_A #34
H_A #35

H_A20M#
H_ IGNNE #
H_D PRSTP#
H_ DPWR #
H_D PSLP#
H_ INTR
H_ NMI
H_S MI#
H_P WRGO OD

ADS#
BNR#

BPRI#

ADDR

GROUP

0

DEFER#

DRDY#
DBSY#

BR0#

IERR#

INIT#

LOCK#

CONTROL

RESET#

RS[0]#
RS[1]#
RS[2]#

TRDY#

HIT#

HITM#

BPM[0]#
BPM[1]#
BPM[2]#

ADDR GROUP 1

BPM[3]#

PRDY#
PREQ#

TCK

TDI
TDO
TMS

TRST#

BR1#

PROCHOT#

XDP /I TP S IGNAL S

THRMDA
THRMDC

THERMTRIP#

THERM

BCLK[0]
BCLK[1]

H CL K

RSVD3
RSVD2

NC

RSVD1

N7@
.

+1.05VS

+CP U_GTLREF

1

0.1U _0402_16 V4Z

C1

2

Close to CPU pin
within 500mils.
Zo=55ohm

+1.05VS

R32 56_0402 _5%

1 2

R33 56_0402 _5%

1 2

R34 56_0402 _5%

1 2

R35 56_0402 _5%

1 2

R36 56_0402 _5%

1 2

R37 56_0402 _5%

1 2

This shall place near CPU

V19
Y19
U21

T21
T19
Y18

T20

F16
V16

W20

D15
W18
Y17
U20
W19

AA17
V20

K17
J18
H15
J15
K18
J16
M17
N16
M16
L17
K16
V15

G17
E4
E5

H17

V11
V12

C21
C1
A3

12

R13
1K_0402 _1%

12

R20
2K_0402 _1%

4

H_A DS#
H_ BNR#
H_ BPRI#

H_ DEFER #
H_ DR DY#
H_ DBSY#

H_B R0#

H_ IERR#
H_ INIT#_ R

H_L OCK#

H_R ESET#
H_R S#0
H_R S#1
H_R S#2
H_ TRDY#

H_ HIT#
H_H ITM#

PRE Q#
ITP_TCK
ITP_ TDI
ITP_TD O
ITP_TMS
ITP_TRST#

H_P ROCHOT #_R
H_T HERMDA
H_ THERMD C

H_T HERMTRIP#

CLK _CPU_B CLK

4

H_A DS# <6>

H_ BNR# <6>

H_ BPRI# <6>

H_ DEFER # <6>

H_ DR DY# <6>

H_ DBSY# <6 >

H_B R0# <6>

R3 1K_0402 _5%

1 2

H_L OCK# <6>

H_R ESET# <6>

H_ TRDY# <6 >

H_H IT# <6>

H_H ITM# <6>

1 2

R4 22_0402_5 %

H_T HERMTRIP# < 6,16>

CLK _CPU_B CLK <12>
CLK _CPU_B CLK# <12>

+CP U_EXTBGREF

C2

1U_ 0402_6.3V 4Z

Close to CPU

Close to CPU

+1.05VS

12

R14
1K_0402 _1%

12

1

R21
2K_0402 _1%

2

Close to CPU pin
within 500mils.
Zo=55ohm

ITP_TMS
ITP_ TDI
PRE Q#
ITP_TD O

ITP_TCK
ITP_TRST#

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+1.05VS +1.05VS

12

R1
56_0402 _5%

12

H_ RS#[0 ..2] <6>

H_P ROCHOT # <37>

+CP U_GTLREF

0.1U _0402_16 V4Z

Close to CPU pin
within 500mils.
Zo=55ohm

3

H_ D#[0 ..15]<6 >

R2
330_040 2_5%

H_ INIT# <16>

H_D STBN#0<6>
H_D STBP#0<6>

H_ DINV#0<6>

H_ D#[16 ..31]<6>

H_D STBN#1<6>
H_D STBP#1<6>

H_ DINV#1<6>

R6 1K_ 0402_5%@

1 2

R8 1K_ 0402_5%@

1 2

+CP U_EXTBGREF

CPU _BSEL0<6,12>
CPU _BSEL1<6,12>
CPU _BSEL2<6,12>

+1.05VS

12

1

2

R15
1K_0402 _1%

12

R22
2K_0402 _1%

Compal Secret Data

Deciphered Date

+CP U_CMRE F

C3

2008/11/17 2009/11/17

3

H_ D#0
H_ D#1
H_ D#2
H_ D#3
H_ D#4
H_ D#5
H_ D#6
H_ D#7
H_ D#8
H_ D#9
H_D #10
H_D #11
H_D #12
H_D #13
H_D #14
H_D #15
H_D STBN#0
H_D STBP#0
H_ DINV# 0
H_D P#0

T2 PAD

H_D #16
H_D #17
H_D #18
H_D #19
H_D #20
H_D #21
H_D #22
H_D #23
H_D #24
H_D #25
H_D #26
H_D #27
H_D #28
H_D #29
H_D #30
H_D #31
H_D STBN#1 H_D STBN#3
H_D STBP#1
H_ DINV# 1
H_D P#1

T4 PAD

ACL KPH
DC LKPH

CPU _BSEL0
CPU _BSEL1
CPU _BSEL2

Layo ut n ote:
COMP 0,2 connect wit h Z o=27 .4ohm + /-15%, make
trac e le ngth sh orte r than 0.5"
COMP 1,3 connect wit h Z o=55 ohm +/-15%, make
trac e le ngth sh orte r than0.5"

H_TH ERMD A, H_TH ERMD C r outing together.
Trac e wi dth / S paci ng = 10 / 10 mil

C5

1 2

1 2

+3VS

R31 10K_040 2_5%

2

U1B

Y11

W10

Y12
AA14
AA11

W12

AA16

Y10

Y9

Y13

W15

AA13

Y16

W13

AA9

W9
Y14
Y15

W16

V9

AA5

Y8

W3

U1
W7
W6

Y7

AA6

Y3
W2

V3

U2

T3

AA8

V2
W4

Y4

Y5

Y6

R4

A7

U5

V5

T17

R6
M6

N15

N6

P17

T6

J6

H5
G5

AU8 0586GE 025512_FCBG A437

+3VS

1

C4

2

0.1 U_0402_ 16V4Z

H_T HERMDA

H_ THERMD C

2200P_0 402_50V7K

CPU _THERM#

2

D[0]#
D[1]#
D[2]#
D[3]#
D[4]#
D[5]#
D[6]#
D[7]#
D[8]#
D[9]#
D[10]#
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
DSTBN[0]#
DSTBP[0]#
DINV[0]#
DP#0

D[16]#
D[17]#
D[18]#
D[19]#
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
DSTBN[1]#
DSTBP[1]#
DINV[1]#
DP#1

GTLREF
ACLKPH
DCLKPH
BINIT#
EDM
EXTBGREF
FORCEPR#
HFPLL
MCERR#
RSP#
BSEL[0]
BSEL[1]
BSEL[2]

DATA GRP 0 DATA GRP 1

MI SC

PWRGOOD

CORE_DET

D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#

DAT A GRP 2

D[45]#
D[46]#

D[47]#
DSTBN[2]#
DSTBP[2]#

DINV[2]#

DP#2

D[48]#

D[49]#

D[50]#

D[51]#

D[52]#

D[53]#

D[54]#

D[55]#

D[56]#

D[57]#

D[58]#

D[59]#

D[60]#

D[61]#

DATA GRP 3

D[62]#

D[63]#
DSTBN[3]#
DSTBP[3]#

DINV[3]#

DP#3

COMP[0]
COMP[1]
COMP[2]
COMP[3]

DPRSTP#

DPSLP#

DPWR#

SLP#

CMREF[1]

N7@

.

R3
R2
P1
N1
M2
P2
J3
N3
G3
H2
N2
L2
M3
J2
H1
J1
K2
K3
L1
M4

C2
G2
F1
D3
B4
E1
A5
C3
A6
F2
C6
B6
B3
C4
C7
D2
E2
F3
C5
D4

T1
T2
F20
F21

R18
R17
U4
V17
N18
A13
B7

CPU THERMAL SENSOR

U2

1

VDD

2

DP

3

DN

4

THERM#

EMC 1402-1-ACZ L-TR_MSOP8

Addres s:0100_1100 EMC1402-1
Addres s:0100_1101 EMC1402-2

SMCLK

SMDATA

ALERT#

GND

Title

Size Do cumen t Numb er R ev

Cu stom

Da te: Sheet o f

1

H_D #32
H_D #33
H_D #34
H_D #35
H_D #36
H_D #37
H_D #38
H_D #39
H_D #40
H_D #41
H_D #42
H_D #43
H_D #44
H_D #45
H_D #46
H_D #47
H_D STBN#2
H_D STBP#2
H_ DINV# 2
H_D P#2

H_D #48
H_D #49
H_D #50
H_D #51
H_D #52
H_D #53
H_D #54
H_D #55
H_D #56
H_D #57
H_D #58
H_D #59
H_D #60
H_D #61
H_D #62
H_D #63

H_D STBP#3
H_ DINV# 3
H_D P#3

COMP0
COMP1
COMP2
COMP3

H_D PRSTP#
H_D PSLP#
H_ DPWR #
H_P WRGO OD
H_C PUSLP#

EC_ SMB_CK2

8

EC_ SMB_DA2

7

6

5

1 2
1 2

R30 10K_0 402_5%@

H_ D#[32 ..47] <6>

H_D STBN#2 <6>
H_D STBP#2 <6>
H_ DINV#2 < 6>

T3PAD

H_ D#[48 ..63] <6>

H_D STBN#3 <6>
H_D STBP#3 <6>
H_ DINV#3 < 6>

T5PAD
R5 27.4 _0402_1%
R7 54.9 _0402_1%
R9 27.4 _0402_1%

12

R10 54 .9_0402_1%

12

H_D PRSTP# <16,37 >
H_D PSLP# <16>
H_D PWR# < 6>
H_P WRGO OD <16>
H_C PUSLP# <6 >

+CP U_CMR EF

EC_ SMB_CK2 <26,27 >

EC_ SMB_DA2 <26,27 >

12

Compal Electronics, Inc.

Diamondville(1/2)

KAVAA LA-5121P M/B

1

+3VS

1.0

4 42Tu esday, M arch 10 , 2009

5

4

3

2

1

1

2

+1.5VS

1

2

1

C25

2

1U_ 0402_6.3V6K

1

C41

2

10U _0805_10V4 Z

+1.05VS

1

+

C7

220 U_B2_2.5VM _R35

2

C12

0.1U _0402_16V7 K

+CP U_COR E

12

12

1U_ 0402_6.3V6K

1

1

C26

2

2

10U _0805_10V4 Z

1

1

C42

2

2

max 1700mA ESR:21~35m ohm

R38

100_040 2_1%

VC CSENSE < 37>

VSS SENSE <37>

R39

100_040 2_1%

1U_ 0402_6.3V6K

1

C27

2

1U_ 0402_6.3V6K

C28

1

2

Length match within 25 mils
The trace space 7 mils,
Zo=27.4ohm

1

C29

2

1U_ 0402_6.3V6K

1U_ 0402_6.3V6K

1

C30

2

+CP U_COR E

2 x 330uF(9mohm/2)

1

+

C13

330 U_D2_2 .5VY_R9M

2

1

+

C14

330 U_D2_2 .5VY_R9M

2

U1 D

A2

VSS1

A4

VSS2

A8

VSS4

A15

VSS5

A18

VSS6

A19

VSS7

A20

VSS8

B1

VSS9

B2

VSS10

D D

C C

B B

A A

B5

VSS11

B8

VSS12

B13

VSS13

B20

VSS14

B21

VSS15

C8

VSS16

C17

VSS17

D1

VSS18

D5

VSS19

D8

VSS20

D14

VSS21

D18

VSS22

D21

VSS23

E3

VSS24

E6

VSS25

E7

VSS26

E8

VSS27

E15

VSS28

E16

VSS29

E19

VSS30

F4

VSS31

F5

VSS32

F6

VSS33

F7

VSS34

F17

VSS35

F18

VSS36

G1

VSS37

G4

VSS38

G7

VSS39

G9

VSS41

G13

VSS42

G21

VSS45

H3

VSS46

H4

VSS48

H7

VSS49

H9

VSS51

H13

VSS52

H16

VSS53

H18

VSS54

H19

VSS55

J5

VSS56

J7

VSS57

J9

VSS58

J13

VSS59

J17

VSS60

K1

VSS61

K6

VSS62

K7

VSS63

K9

VSS64

K13

VSS65

K15

VSS66

K21

VSS67

L3

VSS68

L4

VSS69

L5

VSS70

L6

VSS71

L7

VSS72

L9

VSS73

L13

VSS74

L15

VSS75

L18

VSS76

L19

VSS77

M1

VSS78

M5

VSS79

M7

VSS80

M9

VSS81

M13

VSS82

M21

VSS83

N4

VSS84

AU8 0586GE 025512_FCBG A437

N7@

VSS162
VSS161
VSS160
VSS159
VSS158
VSS157
VSS156
VSS155
VSS154
VSS153
VSS152
VSS151
VSS149
VSS148
VSS147
VSS146
VSS145
VSS144
VSS143
VSS142
VSS141
VSS140
VSS139
VSS138
VSS137
VSS136
VSS135
VSS134
VSS133
VSS132
VSS131
VSS130
VSS129
VSS128
VSS127
VSS126
VSS125
VSS124
VSS123
VSS122
VSS121
VSS120
VSS119
VSS118
VSS117
VSS116
VSS115
VSS114
VSS113
VSS112
VSS111
VSS110
VSS109
VSS108
VSS107
VSS106
VSS105
VSS104
VSS103
VSS102
VSS101
VSS100

VSS99
VSS98
VSS97
VSS96
VSS95

N5
N7
N9
N13
N17
P3
P4
P5
P6
P7
P9
P13
P15
P16
P18
P19
R1
R5
R7
R9
R13
R21
T4
T5
T7
T9
T10
T11
T12
T13
T18
U3
U6
U7
U15
U16
U19
V1
V4
V6
V7
V8
V13
V14
V18
V21
W1
W5
W8
W11
W14
W17
W21
Y1
Y2
Y20
Y21
AA2
AA3
AA4
AA7
AA10
AA12
AA15
AA18
AA19
AA20

+1.05VS

+CP U_COR E

.

+CP U_COR E

1

C15

2

1U_ 0402_6.3V6K

1

C31

2

10U _0805_10V4 Z

U1 C

V10

VCCF

A9

VCCQ1

B9

VCCQ2

A10

VCCP1

A11

VCCP2

A12

VCCP3

B10

VCCP4

B11

VCCP5

B12

VCCP6

C10

VCCP7

C11

VCCP8

C12

VCCP9

D10

VCCP10

D11

VCCP11

D12

VCCP12

E10

VCCP13

E11

VCCP14

E12

VCCP15

F10

VCCP16

F11

VCCP17

F12

VCCP18

G10

VCCP19

G11

VCCP20

G12

VCCP21

H10

VCCP22

H11

VCCP23

H12

VCCP24

J10

VCCP25

J11

VCCP26

J12

VCCP27

K10

VCCP28

K11

VCCP29

K12

VCCP30

L10

VCCP31

L11

VCCP32

L12

VCCP33

M10

VCCP34

M11

VCCP35

M12

VCCP36

N10

VCCP37

N11

VCCP38

N12

VCCP39

P10

VCCP40

P11

VCCP41

P12

VCCP42

R10

VCCP43

R11

VCCP44

R12

VCCP45

AU8 0586GE 025512_FCBG A437

N7@

1U_ 0402_6.3V6K

1

1

C17

C16

2

2

1U_ 0402_6.3V6K

10U _0805_10V4 Z

1

1

C33

C32

2

2

10U _0805_10V4 Z

VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8

VTT9
VTT10
VTT11
VTT12
VTT13
VTT14
VTT15
VTT16
VTT17
VTT18
VTT19
VTT20
VTT21
VTT22
VTT23
VTT24
VTT25
VTT26
VTT27
VTT28
VTT29
VTT30
VTT31
VTT32

VCCPC64
VCCPC63
VCCPC62
VCCPC61

VCCA

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

VCCSENSE

VSSSENSE

PLACE IN CAVITY

1U_ 0402_6.3V6K

1

C18

2

1U_ 0402_6.3V6K

10U _0805_10V4 Z

1

C35

C34

2

10U _0805_10V4 Z

C9
D9
E9
F8
F9
G8
G14
H8
H14
J8
J14
K8
K14
L8
L14
M8
M14
N8
N14
P8
P14
R8
R14
T8
T14
U8
U9
U10
U11
U12
U13
U14

F14
F13
E14
E13

D7

F15
D16
E18
G15
G16
E17
G18

C13

D13

C19

+1.5VS

CP U_VID 0
CP U_VID 1
CP U_VID 2
CP U_VID 3
CP U_VID 4
CP U_VID 5
CP U_VID 6

.

VC CSENSE

VSS SENSE

1U_ 0402_6.3V6K

1

C20

2

10U _0805_10V4 Z

1

C36

2

0.1U _0402_16V7 K

1

C21

2

1U_ 0402_6.3V6K

1

C37

2

10U _0805_10V4 Z

0.1U _0402_16V7 K

1

C9

C8

2

CP U_VID0 < 37>
CP U_VID1 < 37>
CP U_VID2 < 37>
CP U_VID3 < 37>
CP U_VID4 < 37>
CP U_VID5 < 37>
CP U_VID6 < 37>

1U_ 0402_6.3V6K

1

1

C22

2

2

10U _0805_10V4 Z

1

1

C38

2

2

2500mA

1U_ 0402_6.3V6K

1

1

C11

C10

2

2

1U_ 0402_6.3V6K

PLACE IN CAVITY

130mA

1U_ 0402_6.3V6K

1

C23

C24

2

1U_ 0402_6.3V6K

10U _0805_10V4 Z

1

C40

C39

2

10U _0805_10V4 Z

PLACE IN CORRIDOR AND CLOSE TO CPU

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/11/17 2009/11/17

3

Compal Secret Data

Deciphered Date

Title

Size Do cumen t Numb er R ev

Cu stom

2

Da te: Sheet o f

Compal Electronics, Inc.

Diamondville(2/2)

KAVAA LA-5121P M/B

5 42Tu esday, M arch 10 , 2009

1

1.0

5

4

3

2

1

H_ D#[0. .63]<4 >

D D

C C

+1.05VS

12

12

B B

A A

R4 8

R4 7

54. 9_0402_1%

54. 9_0402_1%

12

R5 3

R5 2

24. 9_0402_1%

24. 9_0402_1%

12

H_ D#0
H_ D#1
H_ D#2
H_ D#3
H_ D#4
H_ D#5
H_ D#6
H_ D#7
H_ D#8
H_ D#9
H_D #10
H_D #11
H_D #12
H_D #13
H_D #14
H_D #15
H_D #16
H_D #17
H_D #18
H_D #19
H_D #20
H_D #21
H_D #22
H_D #23
H_D #24
H_D #25
H_D #26
H_D #27
H_D #28
H_D #29
H_D #30
H_D #31
H_D #32
H_D #33
H_D #34
H_D #35
H_D #36
H_D #37
H_D #38
H_D #39
H_D #40
H_D #41
H_D #42
H_D #43
H_D #44
H_D #45
H_D #46
H_D #47
H_D #48
H_D #49
H_D #50
H_D #51
H_D #52
H_D #53
H_D #54
H_D #55
H_D #56
H_D #57
H_D #58
H_D #59
H_D #60
H_D #61
H_D #62
H_D #63

H_XRCOM P
H_XSCOM P

+H_ SWNG0

H_ YRCO MP
H_ YSCOMP

+H_ SWNG1

U3A

C4

H_D#_0

F6

H_D#_1

H9

H_D#_2

H6

H_D#_3

F7

H_D#_4

E3

H_D#_5

C2

H_D#_6

C3

H_D#_7

K9

H_D#_8

F5

H_D#_9

J7

H_D#_10

K7

H_D#_11

H8

H_D#_12

E5

H_D#_13

K8

H_D#_14

J8

H_D#_15

J2

H_D#_16

J3

H_D#_17

N1

H_D#_18

M5

H_D#_19

K5

H_D#_20

J5

H_D#_21

H3

H_D#_22

J4

H_D#_23

N3

H_D#_24

M4

H_D#_25

M3

H_D#_26

N8

H_D#_27

N6

H_D#_28

K3

H_D#_29

N9

H_D#_30

M1

H_D#_31

V8

H_D#_32

V9

H_D#_33

R6

H_D#_34

T8

H_D#_35

R2

H_D#_36

N5

H_D#_37

N2

H_D#_38

R5

H_D#_39

U7

H_D#_40

R8

H_D#_41

T4

H_D#_42

T7

H_D#_43

R3

H_D#_44

T5

H_D#_45

V6

H_D#_46

V3

H_D#_47

W2

H_D#_48

W1

H_D#_49

V2

H_D#_50

W4

H_D#_51

W7

H_D#_52

W5

H_D#_53

V5

H_D#_54

AB4

H_D#_55

AB8

H_D#_56

W8

H_D#_57

AA9

H_D#_58

AA8

H_D#_59

AB1

H_D#_60

AB7

H_D#_61

AA2

H_D#_62

AB5

H_D#_63

A10

H_XRCOMP

A6

H_XSCOMP

C15

H_XSWING

J1

H_YRCOMP

K1

H_YSCOMP

H1

H_YSWING

QG8 2945GS E SLB2 R A3_FCBGA998

H_ADSTB#_0
H_ADSTB#_1

HOST

H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3
H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3

PM_EXTTS#0

PM_EXTTS#1

H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8

H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31

H_ADS#

H_VREF0

H_BNR#

H_BPRI#

H_BREQ0#

H_CPURST#

H_VREF1

HCLKN
HCLKP

H_DBSY#

H_DEFER#
H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3

H_DPWR#

H_DRDY#

H_HIT#

H_HITM#

H_LOCK#
H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4

H_RS#_0
H_RS#_1
H_RS#_2

H_SLPCPU#

H_TRDY#

1 2

R57 10K_0 402_5%

1 2

R58 10K_0 402_5%

F8
D12
C13
A8
E13
E12
J12
B13
A13
G13
A12
D14
F14
J13
E17
H15
G15
G14
A15
B18
B15
E14
H13
C14
A17
E15
H17
D17
G17

F10
C12
H16
E2
B9
C7
G8
B10
E1

AA6
AA5
C10
C6
H5
J6
T9
U6
G7
E6
F3
M8
T1
AA3
F4
M7
T2
AB3

C8
B4
C5
G9
E9
G12
B8
F12
A5
B6
G10
E8
E10

@

H_A #3
H_A #4
H_A #5
H_A #6
H_A #7
H_A #8
H_A #9
H_A #10
H_A #11
H_A #12
H_A #13
H_A #14
H_A #15
H_A #16
H_A #17
H_A #18
H_A #19
H_A #20
H_A #21
H_A #22
H_A #23
H_A #24
H_A #25
H_A #26
H_A #27
H_A #28
H_A #29
H_A #30
H_A #31

H_A DS#
H_A DSTB#0
H_A DSTB#1
+H_ VREF
H_ BNR#
H_ BPRI#
H_B R0#
H_R ESET#
+H_ VREF

CLK _MCH_B CLK#
CLK _MCH_B CLK
H_ DBSY#
H_ DEFER #
H_ DINV# 0
H_ DINV# 1
H_ DINV# 2
H_ DINV# 3
H_ DPWR #
H_ DR DY#
H_D STBN#0
H_D STBN#1
H_D STBN#2
H_D STBN#3
H_D STBP#0
H_D STBP#1
H_D STBP#2
H_D STBP#3

H_ HIT#
H_H ITM#
H_L OCK#
H_R EQ#0
H_R EQ#1
H_R EQ#2
H_R EQ#3
H_R EQ#4
H_R S#0
H_R S#1
H_R S#2
H_C PUSLP#
H_ TRDY#

+3VS

H_ A#[3..3 1] <4>

H_A DS# <4>
H_A DSTB#0 <4>
H_A DSTB#1 <4>

H_ BNR# <4>
H_ BPRI# <4>
H_B R0# <4>
H_R ESET# <4>

CLK _MCH_B CLK# <12>
CLK _MCH_B CLK <12>
H_ DBSY# <4 >
H_ DEFER # <4>
H_ DINV#0 < 4>
H_ DINV#1 < 4>
H_ DINV#2 < 4>
H_ DINV#3 < 4>
H_ DPWR # <4>
H_ DR DY# <4>

H_ DSTBN #[0..3] <4>

H_D STBP# [0..3] <4>

H_ HIT# <4>
H_H ITM# <4>
H_L OCK# <4>

H_ REQ# [0..4] <4>

H_ RS#[ 0..2] <4>

H_C PUSLP# < 4>
H_ TRDY# <4 >

DMI_TXN0< 17>
DMI_TXN1< 17>
DMI_TXP0<17>
DMI_TXP1<17>

DMI_R XN0<17 >
DMI_R XN1<17 >
DMI_RX P0< 17>
DMI_RX P1< 17>

M_C LK_DDR 0<11>
M_C LK_DDR 1<11>

M_C LK_DDR #0<11>
M_C LK_DDR #1<11>

DD R_CKE 0<11>
DD R_CKE 1<11>

DD R_CS0 #<11>
DD R_CS1 #<11>

+1.8V

R44 80.6 _0402_1%

1 2
1 2

R46 80.6 _0402_1%

+DIMM _VREF

1

C4 3

2

Layo ut Note:
H_XR COMP / H_YR COMP / H_VREF / H_SWNG0 /
H_SW NG1 trace w idth an d spacing is 10/20.

+1.05VS

12

R5 1

100_0 402_1%

12

C4 6

R5 6

200_0 402_1%

M_ODT0<11>

M_ODT1<11>

10uA

Layout Note:
+DIMM_ VREF trace
width and spacing

0.1 U_0402_ 16V4Z

is 20/20.

+H_ VREF

1

2

0.1 U_0402_ 16V4Z

U3B

DMI_TXN0
DMI_TXN1
DMI_TXP0
DMI_TXP1

DMI_R XN0
DMI_R XN1
DMI_RX P0
DMI_RX P1

M_C LK_DDR0
M_C LK_DDR1

M_C LK_DDR# 0
M_C LK_DDR# 1

DD R_CKE 0
DD R_CKE 1

DD R_CS0 #
DD R_CS1 #

M_ODT0
M_ODT1

SMR COMPN
SMR COMPP

C44 ,C45,C46 be placed
<100mils from GMCH pin

Y29

DMI_RXN_0

Y32

DMI_RXN_1

Y28

DMI_RXP_0

Y31

DMI_RXP_1

V28

DMI_TXN_0

V31

DMI_TXN_1

V29

DMI_TXP_0

V32

DMI_TXP_1

AF33

SM_CK_0

AG1

SM_CK_1

AJ1

SM_CK_2

AM30

SM_CK_3

AG33

SM_CK#_0

AF1

SM_CK#_1

AK1

SM_CK#_2

AN30

SM_CK#_3

AN21

SM_CKE_0

AN22

SM_CKE_1

AF26

SM_CKE_2

AF25

SM_CKE_3

AG14

SM_CS#_0

AF12

SM_CS#_1

AK14

SM_CS#_2

AH12

SM_CS#_3

AJ21

SM_OCDCOMP_0

AF11

SM_OCDCOMP_1

AE12

SM_ODT_0

AF14

SM_ODT_1

AJ14

SM_ODT_2

AJ12

SM_ODT_3

AN12

SM_RCOMPN

AN14

SM_RCOMPP

AA33

SM_VREF_0

AE1

SM_VREF_1

QG8 2945GS E SLB2 R A3_FCBGA998

DMI

DDR2 MUXING

CFG_0
CFG_1
CFG_2
CFG_3
CFG_5
CFG_6

RESERVED1
RESERVED2
RESERVED7
RESERVED8
RESERVED9

CFG/RSVD

PM_ICHSYNC#

PM_BMBUSY#
PM_EXTTS#_0

PM

PM_EXTTS#_1

THRMTRIP#

PWROK

RSTIN#

D_REFCLKN
D_REFCLKP

CLK

D_REFSSCLKN
D_REFSSCLKP

CLKREQ#

+1.05VS

12

R4 9

221_0 402_1%

12

R5 4

100_0 402_1%

C4 4

C18
E18
G20
G18
J20
J18

K32
K31
C17
F18
A3

MCH _CLKSEL0
MCH _CLKSEL1
MCH _CLKSEL2
CF G3
CF G5
CF G6

R403 1K_04 02_5%

1 2

R404 1K_04 02_5%

1 2

R405 1K_04 02_5%

1 2

R40 2.2K_ 0402_5%@

1 2

R41 2.2K_ 0402_5%

1 2

R42 2.2K_ 0402_5%@

1 2

Strap Pin Table

CFG[ 2:0] 001=FS B533

CFG3

CFG6

CFG5

2/25 PVT: Change Net Name to ICH_PWROK

E31
G21
F26
H26
J15
AB29
W27

A27
A26
J33
H33
J22

PM_EXTTS#0
PM_EXTTS#1

PLTRST_ R#

H_T HERMTRIP#

ICH _PW ROK

1 2

R45 100_040 2_5%

12

R416 0_0402_5%

MC H_ICH _SYN C# <15>

PM_ BMBUSY# <17>
PM_EXTTS#0 <11>

12

R43 0_ 0402_5%

CLK _MCH_ DREFCL K# <12>
CL K_MCH_ DREFC LK <12>
MC H_SSCD REFCL K# <12>
MC H_SSC DREFCL K <12>

C511

@

22P_040 2_50V8J

2/5 DVT: For WWLAN request

+1.05VS

12

R5 0

221_0 402_1%

+H_ SWNG0

1

2

0.1 U_0402_ 16V4Z

12

R5 5

+H_ SWNG1

1

C4 5

2

100_0 402_1%

0.1 U_0402_ 16V4Z

000= FSB400

011= FSB667

Rese rved

0=DM I X 2

1=DM I X4

PM_ DPRSLPVR < 17,37>

H_T HERMTRIP# < 4,16>

ICH _PW ROK <17>

PLTRST# < 15,17,1 9,24,28>

MCH _CLKRE Q# <12>

CPU _BSEL0 <4,12 >
CPU _BSEL1 <4,12 >
CPU _BSEL2 <4,12 >

*

*

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/11/17 2009/11/17

3

Compal Secret Data

Deciphered Date

Title

Size Do cumen t Numb er R ev

Cu stom

2

Da te: Sheet o f

Compal Electronics, Inc.

Calistoga(1/5)-GTL/DMI/DDR

KAVAA LA-5121P M/B

6 42Tu esday, M arch 10 , 2009

1

1.0

5

4

3

2

1

D D

C C

B B

DDR _A_BS0<11 >
DDR _A_BS1<11 >
DDR _A_BS2<11 >

DD R_A_ DM[0..7 ]<11>

DD R_A_ DQS[0 ..7]<11>

DD R_A_ DQS#[0 ..7]<11>

DD R_A_M A[0..13 ]<1 1>

DDR _A_CA S#<11>
DDR _A_RA S#<11>

DDR _A_W E#<11>

T7 PAD
T8 PAD

DDR _A_BS0
DDR _A_BS1
DDR _A_BS2

DDR _A_DM0
DDR _A_DM1
DDR _A_DM2
DDR _A_DM3
DDR _A_DM4
DDR _A_DM5
DDR _A_DM6
DDR _A_DM7

DD R_A_DQ S0
DD R_A_DQ S1
DD R_A_DQ S2
DD R_A_DQ S3
DD R_A_DQ S4
DD R_A_DQ S5
DD R_A_DQ S6
DD R_A_DQ S7

DDR _A_DQS #0
DDR _A_DQS #1
DDR _A_DQS #2
DDR _A_DQS #3
DDR _A_DQS #4
DDR _A_DQS #5
DDR _A_DQS #6
DDR _A_DQS #7

DDR _A_MA0
DDR _A_MA1
DDR _A_MA2
DDR _A_MA3
DDR _A_MA4
DDR _A_MA5
DDR _A_MA6
DDR _A_MA7
DDR _A_MA8
DDR _A_MA9
DDR _A_MA10
DDR _A_MA11
DDR _A_MA12
DDR _A_MA13

DD R_A_CA S#
DD R_A_RA S#
SA _RCV ENIN#

SA_ RCVENO UT#

DDR _A_W E#

AK12
AH11
AG17

AB30

AL31
AF30

AK26

AG7
AK5
AH3

AC28

AJ30

AK33

AL25

AN9
AH8
AM2
AE3

AC29
AK30

AJ33

AM25

AN8

AM3
AE2

AJ15
AM17
AM15
AH15
AK15
AN15

AJ18

AF19
AN17

AL17
AG16

AL18
AG18

AL14

AJ17
AK18
AN28
AM28
AH17

AH21

AJ20
AE27

AN20

AL21
AK21
AK22

AL22
AH22
AG22

AF21
AM21
AE21

AL20
AE22
AE26
AE20

AL9

AJ8

U3 C

SA_BS_0
SA_BS_1
SA_BS_2

SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7

SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7

SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7

SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13

SA_CAS#
SA_RAS#
SA_RCVENIN#
SA_RCVENOUT#
SA_WE#

SB_BS_0
SB_BS_1
SB_BS_2

SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13

SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8

SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47

DDR2 SYSTEM MEMORY

SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63

SB_CAS#

SB_RAS#

SB_WE#

AB28
AE33
AF32
AC33
AB32
AB31
AE31
AH31
AK31
AL28
AK27
AH30
AL32
AJ28
AJ27
AH32
AF31
AH27
AF28
AJ32
AG31
AG28
AG27
AN27
AM26
AJ26
AJ25
AL27
AN26
AH25
AG26
AM12
AL11
AH9
AK9
AM11
AK11
AM8
AK8
AG9
AF9
AF8
AK6
AF7
AG11
AJ6
AH6
AN6
AM6
AK3
AL2
AM5
AL5
AJ3
AJ2
AG2
AF3
AE7
AF6
AH5
AG3
AG5
AF5

AG19
AG21
AG20

DD R_A_D 1
DD R_A_D 2
DD R_A_D 3
DD R_A_D 4
DD R_A_D 5
DD R_A_D 6
DD R_A_D 7
DD R_A_D 8
DD R_A_D 9
DD R_A_D 10
DD R_A_D 11
DD R_A_D 12
DD R_A_D 13
DD R_A_D 14
DD R_A_D 15
DD R_A_D 16
DD R_A_D 17
DD R_A_D 18
DD R_A_D 19
DD R_A_D 20
DD R_A_D 21
DD R_A_D 22
DD R_A_D 23
DD R_A_D 24
DD R_A_D 25
DD R_A_D 26
DD R_A_D 27
DD R_A_D 28
DD R_A_D 29
DD R_A_D 30
DD R_A_D 31
DD R_A_D 32
DD R_A_D 33
DD R_A_D 34
DD R_A_D 35
DD R_A_D 36
DD R_A_D 37
DD R_A_D 38
DD R_A_D 39
DD R_A_D 40
DD R_A_D 41
DD R_A_D 42
DD R_A_D 43
DD R_A_D 44
DD R_A_D 45
DD R_A_D 46
DD R_A_D 47
DD R_A_D 48
DD R_A_D 49
DD R_A_D 50
DD R_A_D 51
DD R_A_D 52
DD R_A_D 53
DD R_A_D 54
DD R_A_D 55
DD R_A_D 56
DD R_A_D 57
DD R_A_D 58
DD R_A_D 59
DD R_A_D 60
DD R_A_D 61
DD R_A_D 62
DD R_A_D 63

DD R_A_D 0

AC31

DD R_A_ D[0..6 3] <11>

QG8 2945GS E SLB2 R A3_FCBGA998

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/11/17 2009/11/17

3

Compal Secret Data

Deciphered Date

Title

Size Do cumen t Numb er R ev

Cu stom

2

Da te: Sheet o f

Compal Electronics, Inc.

Calistoga(2/5)-DDR2

KAVAA LA-5121P M/B

1

1.0

7 42Tu esday, M arch 10 , 2009

5

D D

4

3

2

1

U3 F

H27

GMCH _CRT_ R

R60 150_040 2_1%

R61 150_040 2_1%

R62 150_040 2_1%

C C

R64 100K_04 02_5%

+3VS

B B

12

GMCH _CRT_G

12

GMCH _CRT_B

12

Clos e to U3.H 25

R63 255_ 0402_1%

3/4 P VT: Ad d sup port DPS T fun ctio n

12

1 2

R66 10K_0 402_5%

1 2

R67 10K_0 402_5%

ENB KL

LCT LA_CLK

LCTLB_D ATA

CLK _MCH_3GPL L#<12>
CLK _MCH_3GPL L<12>

GMCH _CRT_ CLK<14>

GMCH _CRT_DA TA<1 4>

GMCH _CRT_B<14>

GMCH _CRT_G<14>

GMCH _CRT_ R<14>

GM CH_C RT_VSYN C<14>

12

ENB KL<26 >

R65 1.5 K_0402_1%

GM CH_C RT_HS YNC<14>

GMCH _INVT_PW M<1 3>

LVD S_SCL<13>
LVD S_SDA<13>

GM CH_EN VDD<13>

12

LVD S_ACLK#<13>
LVD S_ACLK< 13>

LVD S_A0#<13>
LVD S_A1#<13>
LVD S_A2#<13>

LVD S_A0<13>
LVD S_A1<13>
LVD S_A2<13>

GMCH _CRT_B

GMCH _CRT_G

GMCH _CRT_ R

CR T_IRE F

LCT LA_CLK
LCTLB_D ATA
LVD S_SCL
LVD S_SDA
GM CH_EN VDD
L_IBG

LVD S_ACLK#
LVD S_ACLK

LVD S_A0#
LVD S_A1#
LVD S_A2#

LVD S_A0
LVD S_A1
LVD S_A2

SDVO_CTRLDATA

J27

SDVO_CTRLCLK

Y26

G_CLKN

AA26

G_CLKP

H20

CRT_DDC_CLK

H22

CRT_DDC_DATA

A24

CRT_BLUE

A23

CRT_BLUE#

E25

CRT_GREEN

F25

CRT_GREEN#

C25

CRT_RED

D25

CRT_RED#

F27

CRT_VSYNC

D27

CRT_HSYNC

H25

CRT_IREF

H30

L_BKLTCTL

G29

L_BKLTEN

F28

L_CLKCTLA

E28

L_CTLBDATA

G28

L_DDC_CLK

H28

L_DDC_DATA

K30

L_VDDEN

K27

L_IBG

J29

L_VBG

J30

L_VREFH

K29

L_VREFL

D30

LA_CLKN

C30

LA_CLKP

A30

LB_CLKN

A29

LB_CLKP

G31

LA_DATAN_0

F32

LA_DATAN_1

D31

LA_DATAN_2

H31

LA_DATAP_0

G32

LA_DATAP_1

C31

LA_DATAP_2

F33

LB_DATAN_0

D33

LB_DATAN_1

F30

LB_DATAN_2

E33

LB_DATAP_0

D32

LB_DATAP_1

F29

LB_DATAP_2

QG8 2945GS E SLB2 R A3_FCBGA998

EXP_A_COMPI

EXP_A_ICOMPO

SDVO_TVCLKIN#

SDVO_FLDSTALL#

MISC

SDVO_TVCLKIN

SDVO_FLDSTALL

SDVO

SDVO_RED#

SDVO_GREEN#

SDVO_BLUE#

SDVO_CLKN

SDVO_GREEN

SDVO_BLUE
SDVO_CLKP

TV

LVDS VGA

TV_DCONSEL0
TV_DCONSEL1

SDVO_INT#

SDVO_RED

SDVO_INT

TV_DACA
TV_DACB
TV_DACC

TV_IREF
TV_IRTNA
TV_IRTNB

TV_IRTNC

R28
M28

N30
R30
T29

M30
P30
T30

P28
N32
P32
T32

N28
M32
P33
R32

A21
C20
E20
G23
B21
C21
D21

G26
J26

PEGCOMP

+1.5VS

1 2

Disable TV

R59

24.9 _0402_1%

+1.5 VS_PC IE

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/11/17 2009/11/17

3

Compal Secret Data

Deciphered Date

Title

Size Do cumen t Numb er R ev

Cu stom

2

Da te: Sheet o f

Compal Electronics, Inc.

Calistoga(3/5)-VGA/LVDS/TV

KAVAA LA-5121P M/B

8 42Tu esday, M arch 10 , 2009

1

1.0

5

+1.05VS

D D

C C

+1.05VS

B B

A A

U3H

T25

VCC_NCTF1

R25

VCC_NCTF2

P25

VCC_NCTF3

N25

VCC_NCTF4

M25

VCC_NCTF5

P24

VCC_NCTF6

N24

VCC_NCTF7

M24

VCC_NCTF8

Y22

VCC_NCTF9

W22

VCC_NCTF10

V22

VCC_NCTF11

U22

VCC_NCTF12

T22

VCC_NCTF13

R22

VCC_NCTF14

P22

VCC_NCTF15

N22

VCC_NCTF16

M22

VCC_NCTF17

Y21

VCC_NCTF18

W21

VCC_NCTF19

V21

VCC_NCTF20

U21

VCC_NCTF21

T21

VCC_NCTF22

R21

VCC_NCTF23

P21

VCC_NCTF24

N21

VCC_NCTF25

M21

VCC_NCTF26

Y20

VCC_NCTF27

W20

VCC_NCTF28

V20

VCC_NCTF29

U20

VCC_NCTF30

T20

VCC_NCTF31

R20

VCC_NCTF32

P20

VCC_NCTF33

N20

VCC_NCTF34

M20

VCC_NCTF35

Y19

VCC_NCTF36

P19

VCC_NCTF37

N19

VCC_NCTF38

M19

VCC_NCTF39

Y18

VCC_NCTF40

P18

VCC_NCTF41

N18

VCC_NCTF42

M18

VCC_NCTF43

Y17

VCC_NCTF44

P17

VCC_NCTF45

N17

VCC_NCTF46

M17

VCC_NCTF47

Y16

VCC_NCTF48

P16

VCC_NCTF49

N16

VCC_NCTF50

M16

VCC_NCTF51

Y15

VCC_NCTF52

P15

VCC_NCTF53

N15

VCC_NCTF54

M15

VCC_NCTF55

Y14

VCC_NCTF56

W14

VCC_NCTF57

V14

VCC_NCTF58

U14

VCC_NCTF59

T14

VCC_NCTF60

R14

VCC_NCTF61

P14

VCC_NCTF62

N14

VCC_NCTF63

M14

VCC_NCTF64

T10

VTT_NCTF1

R10

VTT_NCTF2

P10

VTT_NCTF3

N10

VTT_NCTF4

L10

VTT_NCTF5

D1

VTT_NCTF6

M10

RSVD_3

A18

RSVD_4

AB10

RSVD_5

AA10

RSVD_6

QG8294 5GSE SLB2R A3_FCBGA998

NCTF

4

VCCAUX_NCTF1
VCCAUX_NCTF2
VCCAUX_NCTF3
VCCAUX_NCTF4
VCCAUX_NCTF5
VCCAUX_NCTF6
VCCAUX_NCTF7
VCCAUX_NCTF8

VCCAUX_NCTF9
VCCAUX_NCTF10
VCCAUX_NCTF11
VCCAUX_NCTF12
VCCAUX_NCTF13
VCCAUX_NCTF14
VCCAUX_NCTF15
VCCAUX_NCTF16
VCCAUX_NCTF17
VCCAUX_NCTF18
VCCAUX_NCTF19
VCCAUX_NCTF20
VCCAUX_NCTF21
VCCAUX_NCTF22
VCCAUX_NCTF23
VCCAUX_NCTF24
VCCAUX_NCTF25
VCCAUX_NCTF26
VCCAUX_NCTF27
VCCAUX_NCTF28
VCCAUX_NCTF29
VCCAUX_NCTF30
VCCAUX_NCTF31
VCCAUX_NCTF32
VCCAUX_NCTF33
VCCAUX_NCTF34
VCCAUX_NCTF35
VCCAUX_NCTF36
VCCAUX_NCTF37
VCCAUX_NCTF38

VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
VSS_NCTF8

VSS_NCTF9
VSS_NCTF10
VSS_NCTF11
VSS_NCTF12
VSS_NCTF13
VSS_NCTF14
VSS_NCTF15
VSS_NCTF16
VSS_NCTF17
VSS_NCTF18
VSS_NCTF19

CFG_19

RESERVED10
RESERVED11
RESERVED12
RESERVED13
RESERVED14
RESERVED15
RESERVED16
RESERVED17
RESERVED18
RESERVED19
RESERVED20
RESERVED21
RESERVED22
RESERVED23
RESERVED24
RESERVED25

AD25
AC25
AB25
AD24
AC24
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
K14
AD13
Y13
W13
V13
U13
T13
R13
P13
N13
M13
AD12
Y12
W12
V12
U12
T12
R12
P12
N12
M12
AD11
AD10
K10
AN33
AA25
V25
U25
AA22
AA21
AA20
AA19
AA18
AA17
AA16
AA15
AA14
AA13
A4
A33
B2
AN1
C1

K28

K25
K26
R24
T24
K21
K19
K20
K24
K22
J17
K23
K17
K12
K13
K16
K15

+1.5VS

3

U3E

AH33

VSS_1

Y33

VSS_2

V33

VSS_3

R33

VSS_4

G33

VSS_5

AK32

VSS_6

AG32

VSS_7

AE32

VSS_8

AC32

VSS_9

AA32

VSS_10

U32

VSS_11

H32

VSS_12

E32

VSS_13

C32

VSS_14

AM31

VSS_15

AJ31

VSS_16

AA31

VSS_17

U31

VSS_18

T31

VSS_19

R31

VSS_20

P31

VSS_21

N31

VSS_22

M31

VSS_23

J31

VSS_24

F31

VSS_25

AL30

VSS_26

AG30

VSS_27

AE30

VSS_28

AC30

VSS_29

AA30

VSS_30

Y30

VSS_31

V30

VSS_32

U30

VSS_33

G30

VSS_34

E30

VSS_35

B30

VSS_36

AA29

VSS_37

U29

VSS_38

R29

VSS_39

P29

VSS_40

N29

VSS_41

M29

VSS_42

H29

VSS_43

E29

VSS_44

B29

VSS_45

AK28

VSS_46

AH28

VSS_47

AE28

VSS_48

AA28

VSS_49

U28

VSS_50

T28

VSS_51

J28

VSS_52

D28

VSS_53

AM27

VSS_54

AF27

VSS_55

AB27

VSS_56

AA27

VSS_57

Y27

VSS_58

U27

VSS_59

T27

VSS_60

R27

VSS_61

P27

VSS_62

N27

VSS_63

M27

VSS_64

G27

VSS_65

E27

VSS_66

C27

VSS_67

B27

VSS_68

AL26

VSS_69

AH26

VSS_70

W26

VSS_71

U26

VSS_72

AN25

VSS_73

AK25

VSS_74

AG25

VSS_75

AE25

VSS_76

J25

VSS_77

G25

VSS_78

A25

VSS_79

H23

VSS_80

F23

VSS_81

B23

VSS_82

AM22

VSS_83

AJ22

VSS_84

AF22

VSS_85

G22

VSS_86

E22

VSS_87

J21

VSS_88

H21

VSS_89

F21

VSS_90

AM20

VSS_91

AK20

VSS_92

AH20

VSS_93

AF20

VSS_94

D20

VSS_95

W19

VSS_96

R19

VSS_97

AM18

VSS_98

AH18

VSS_99

AF18

VSS_100

U18

VSS_101

H18

VSS_102

D18

VSS_103

AK17

VSS_104

V17

VSS_105

T17

VSS_106

F17

VSS_107

B17

VSS_108

AH16

VSS_109

U16

VSS_110

QG8294 5GSE SLB2R A3_FCBGA998

2

J16

VSS_111

AL15

VSS_112

AG15

VSS_113

W15

VSS_114

R15

VSS_115

F15

VSS_116

D15

VSS_117

AM14

VSS_118

AH14

VSS_119

AE14

VSS_120

H14

VSS_121

B14

VSS_122

F13

VSS_123

D13

VSS_124

AL12

VSS_125

AG12

VSS_126

H12

VSS_127

B12

VSS_128

AN11

VSS_129

AJ11

VSS_130

AE11

VSS_131

AM9

VSS_132

AJ9

VSS_133

AB9

VSS_134

W9

VSS_135

R9

VSS_136

M9

VSS_137

J9

VSS_138

F9

VSS_139

C9

VSS_140

A9

VSS_141

AL8

VSS_142

AG8

VSS_143

AE8

VSS_144

U8

VSS_145

AA7

VSS_146

V7

VSS_147

R7

VSS_148

N7

VSS_149

H7

VSS_150

E7

VSS_151

B7

VSS_152

AL6

VSS_153

AG6

VSS_154

AE6

VSS_155

AB6

VSS_156

W6

VSS_157

T6

VSS_158

M6

VSS_159

K6

VSS_160

AN5

VSS_161

AJ5

VSS_162

B5

VSS_163

AA4

VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185

V4
R4
N4
K4
H4
E4
AL3
AD3
W3
T3
B3
AK2
AH2
AF2
AB2
M2
K2
H2
F2
V1
R1

VSS

U3G

W33

NC1

AM33

NC2

AL33

NC3

C33

NC4

B33

NC5

AN32

NC6

A32

NC7

AN31

NC8

W28

NC9

V27

NC10

W29

NC11

J24

NC12

H24

NC13

W32

NC14

G24

NC15

F24

NC16

E24

NC17

D24

NC18

K33

NC19

A31

NC20

E21

NC21

C23

NC22

AN19

NC23

AM19

NC24

AL19

NC25

AK19

NC26

AJ19

NC27

AH19

NC28

AN3

NC29

Y9

NC30

J19

NC31

H19

NC32

G19

NC33

F19

NC34

E19

NC35

D19

NC36

C19

NC37

B19

NC38

A19

NC39

Y8

NC40

G16

NC41

F16

NC42

E16

NC43

D16

NC44

C16

NC45

B16

NC46

AN2

NC47

A16

NC48

Y7

NC49

AM4

NC50

AF4

NC51

AD4

NC52

AL4

NC53

AK4

NC54

W31

NC55

AJ4

NC56

AH4

NC57

AG4

NC58

AE4

NC59

AM1

NC60

QG8294 5GSE SLB2R A3_FCBGA998

NC

RESERVED26
RESERVED27
RESERVED28
RESERVED29
RESERVED30
RESERVED31
RESERVED32
RESERVED33
RESERVED34
RESERVED35
RESERVED36
RESERVED37
RESERVED38
RESERVED39
RESERVED40
RESERVED41
RESERVED42

1

NC61
NC62
NC63
NC64
NC65
NC66
NC67
NC68
NC69
NC70
NC71
NC72

W30
Y6
AL1
Y5
Y10
W10
W25
V24
U24
V10
U10
K18

Y25
Y24
AB22
AB21
AB19
AB16
AB14
AA12
W24
AA24
AB24
AB20
AB18
AB15
AB13
AB12
AB17

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/11/17 2009/11/17

Compal Secret Data

Deciphered Date

Title

Size D ocument N umber Re v

Cus tom

2

Date: Sheet of

Compal Electronics, Inc.

Calistoga(4/5)-PWR/GND

KAVAA LA-5121P M/B

9 42Tuesday, March 10, 2009

1

1.0

2940mA

1

1

+

+

C48

@

2

2

220U_B2_2.5VM_R35

+1.05VS

21

D1
CH751H-40PT_S OD323-2

12

+2.5VS

5

1

C49

2

10U_0805_10V4Z

1

1

C51

C50

2

2

10U_0805_10V4Z

0.1U_0402_16V4Z

C73

1 2

0.47U_0603_10V7K

C80

1 2

0.47U_0603_10V7K

1

+

C81

2

220U_B2_2.5VM_R35

C86

4.7U_06 03_6.3V6K

C93

0.47U_0603_10V7K

C52

1250mA

1

2

0.1U_0402_16V4Z

780mA

10mil

10mil

C87

4.7U_06 03_6.3V6K

10mil

1

2

C53

0.1U_0402_16V4Z

+1.5VS

C71

0.1U_0402_16V4Z

+1.05VS

1

2

1

2

U4_A14

U4_A7

U4_AA1
U4_F1

10mil

1

C94

0.47U_0603_10V7K

2

W18

W17

W16

AD33
AD32
AD31
AD30
AD29
AD28
AD27
AC27
AD26
AC26

AB26
AE19
AE18
AF17
AE17
AF16
AE16
AF15
AE15

T26
R26
P26
N26
M26
V19
U19
T19

V18
T18
R18

U17
R17

V16
T16
R16
V15
U15
T15

H10
AE9
AD9

AD8
AD7
AD6

A14
D10

AA1

J14
J10

U9

P9
L9

D9

P8
L8

D8

P7
L7

D7

A7
P6

L6
G6
D6
U5

P5

L5
G5
D5

Y4
U4

P4

L4
G4
D4

Y3
U3

P3

L3
G3
D3

Y2
U2

P2

L2
G2
D2

F1

+1.05VS

C47

D D

220U_B2_2.5VM_R35

R71

10_0402_5%

1/1 3 DVT :C ha nge D 1 P /N to SC1 H751 H010

C C

B B

A A

4

U3D

VCC0
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21

VCCAUX1
VCCAUX2
VCCAUX3
VCCAUX4
VCCAUX5
VCCAUX6
VCCAUX7
VCCAUX8
VCCAUX9
VCCAUX10
VCCAUX11
VCCAUX12
VCCAUX13
VCCAUX14
VCCAUX15
VCCAUX16
VCCAUX17
VCCAUX18
VCCAUX19
VCCAUX20
VCCAUX21
VCCAUX22
VCCAUX23
VCCAUX24
VCCAUX25
VCCAUX26
VCCAUX27
VCCAUX28

VTT0
VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8
VTT9
VTT10
VTT11
VTT12
VTT13
VTT14
VTT15
VTT16
VTT17
VTT18
VTT19
VTT20
VTT21
VTT22
VTT23
VTT24
VTT25
VTT26
VTT27
VTT28
VTT29
VTT30
VTT31
VTT32
VTT33
VTT34
VTT36
VTT35
VTT37
VTT38
VTT39
VTT40

QG8294 5GSE SLB2R A3_FCBGA998

VCCATVDACA0
VCCATVDACA1
VCCATVDACB0
VCCATVDACB1
VCCATVDACC0
VCCATVDACC1

VCCDTVDAC

VCCDQTVDAC

POWER

VCCDHMPLL1
VCCDHMPLL2

VCCTXLVDS0
VCCTXLVDS1

VCCACRTDAC0
VCCACRTDAC1

VSSACRTDAC

VCCATVBG
VSSATVBG

VCCDLVDS0
VCCDLVDS1
VCCDLVDS2

VCCHV0
VCCHV1
VCCHV2
VCCSM0
VCCSM1
VCCSM2
VCCSM3
VCCSM4
VCCSM5
VCCSM6
VCCSM7
VCCSM8

VCCSM9
VCCSM10
VCCSM11
VCCSM12
VCCSM13
VCCSM14
VCCSM15
VCCSM16
VCCSM17
VCCSM18
VCCSM19
VCCSM20
VCCSM21
VCCSM22
VCCSM23
VCCSM24
VCCSM25
VCCSM26
VCCSM27
VCCSM28
VCCSM29
VCCSM30
VCCSM31
VCCSM32
VCCSM33
VCCSM34
VCCSM35
VCCSM36
VCCSM37
VCCSM38
VCCSM39
VCCSM40
VCCSM41
VCCSM42
VCCSM43
VCCSM44
VCCSM45
VCCSM46
VCCSM47
VCCSM48
VCCSM49
VCCSM50
VCCSM51

VCCAMPLL

VCCAHPLL
VCCADPLLA
VCCADPLLB

VCC3G0
VCC3G1

VCCA3GPLL

VCCA3GBG
VSSA3GBG

VCCSYNC

VCCALVDS

VSSALVDS

VTT41
VTT42
VTT43
VTT44
VTT45

B20
A20
B22
A22
D22
C22
D23
E23
F20
F22
C28
B28
A28
E26
D26
C26
AB33
AM32
AN29
AM29
AL29
AK29
AJ29
AH29
AG29
AF29
AE29
AN24
AM24
AL24
AK24
AJ24
AH24
AG24
AF24
AE24
AN18
AN16
AM16
AL16
AK16
AJ16
AN13
AM13
AL13
AK13
AJ13
AH13
AG13
AF13
AE13
AN4
AM10
AL10
AK10
AH1
AH10
AG10
AF10
AE10
AN7
AM7
AL7
AK7
AJ7
AH7
AN10
AJ10
AD1
AD2
B26
J32
AE5
AD5
D29
C29
U33
T33
V26
N33
M33
J23
C24
B24
B25
B31
B32

P1
L1
G1
U1
Y1

+1.5VS

10mA

144mA

Disable TV

20mA

40mA

U4_AB33
U4_AM32

10mil

10mil

10mil

10mil

C79

+1.5VS_MPLL
+1.5VS_HPLL
+1.5VS_DPLLA
+1.5VS_DPLLB

150mA

+1.5VS

60mA

+2.5VS

400mA

+1.5VS_3GPLL
+2.5VS

+2.5VS_CR TDAC

+2.5VS

+1.05VS

3

10mil

1

1

C61

C62

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

C72
1U_0402_6.3V6K

2

1

C78

2

1

1U_0402_6.3V6K

2

1U_0402_6.3V6K

45mA
45mA

50mA
50mA

Route +2.5VS fr om GMCH pinN33 to
deco upling ca p <250mil to the edge.

400mA
2mA

70mA
70mA

1

1

2

2

C90

0.022U_0402_16V7K

Route VSSACRTDAC gnd from GMCH to
deco upling ca p ground lead and then
conn ect to the gnd plane .

+3VS

1

1

C60

C59

2

2

10U_0805_10V4Z

0.1U_0402_16V4Z

1

C68

C69

2

1U_0402_6.3V6K

1

C57

2

0.1U_0402_16V4Z

C67

C70

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

PLAC EIN CAVIY

+2.5VS

1

C82

2

10/2 3 EV T check wa ter wave

R73

12

+2.5VS

0_0402_5%

1

C91

C92

2

CRTDAC: Route FB
within 3" of Cal istoga

10U_0805_10V4Z

0.1U_0402_16V4Z

2

+1.5VS

1

C58

2

10U_0805_10V4Z

+1.5VS_MPLL

+1.8V

1

+

@

2

220U_B2_2.5VM_R25M

533 MTS=1720m A

C63

2/6 D VT: Re se rve C67 wit h 220 uf

1

C76

C74

2

0.1U_0402_16V4Z

220U_B2_2.5VM_R35

C84

1

2

10U_0805_10V4Z

+1.5VS_PCIE

C85

10U_0805_10V4Z

0.1U_0402_16V4Z

+2.5VS

1

1

C88

C89

2

2

10U_0805_10V4Z

0.1U_0402_16V4Z

1

PCI-E/MEM/PSB PLL decoupling

+1.5VS_3GPLL

1

1

C55

C54

2

2

10U_0805_10V4Z

0.1U_0402_16V4Z

R68

0_0603_5%

12

PLAC EIN CAVIY

0.1U_0402_16V4Z

1

2

45mA Max.

R69
0_0603_5%

1

C64

2

10U_0805_10V4Z

12

+1.5VS

+1.5VS_HPLL

C65

Plac e as cl ose as p ossible to the edge( <200mils)

L1

1 2

FBMA-L10-160808-301LMT_2P

1

+

2

0_0805_5%

1

1

+

C83

2

2

220U_B2_2.5VM_R35

+1.5VS +1.5VS

2/6 D VT: Fo r ESD team req uest

R72

12

+1.5VS

+2.5VS +2.5VS

C95

+1.5VS_DPLLA+1.5VS_DPLLB

1

1

C77

C514

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

C96

2

2

0.1U_0402_16V4Z

4.7U_06 03_6.3V6K

clos e pin C 29/D29 close pin B 31

+1.5VS

0.1U_0402_16V4Z

@

1

C66

2

1

+

C75

2

220U_B2_2.5VM_R35

1

C97

2

0.01U_0402_25V7K

+1.5VS+1.5VS_3GPLL

1

C56

2

0.1U_0402_16V4Z

45mA Max.

R70
0_0603_5%

1

2

10U_0805_10V4Z

50mA Max.50mA Max.

L2

1 2

FBMA-L10-160808-301LMT_2P

C98

0.1U_0402_16V4Z

12

+1.5VS

1

2

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/11/17 2009/11/17

Compal Secret Data

Deciphered Date

Title

Size D ocument N umber Re v

Cus tom

2

Date: Sheet of

Compal Electronics, Inc.

Calistoga(5/5)-PWR/GND

KAVAA LA-5121P M/B

10 42Tuesday, March 10, 2009

1

1.0

5

DDR_A _DQS#[0.. 7]<7>

DDR _A_D[0..6 3]<7>

DDR_A _DM[0..7]<7>

DDR_ A_DQS[0.. 7]<7>

DDR_A _MA[0..13]<7>

D D

+1.8V

2

2

2

C99

1

2.2U_0603_6.3V6K

1

+

@

C106

C107

2

220U_B2_2.5VM_R35

C C

Layou t Note:
Plac e on e cap close to every 2 p ullup
resi stor s termin ated to +0 .9VS

+0.9VS

1

1

1

C113

C112

C111

B B

A A

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

DDR_A_MA0
DDR_A_MA13
DDR_C S0#
M_ODT0

DDR_A_MA1
DDR_A_MA3
DDR_A_MA5
DDR_A _CAS#

DDR_A_W E#
DDR_A_BS 0
M_ODT1
DDR_C S1#

2

C114

2

0.1U_0402_16V4Z

1 8
2 7
3 6
4 5

56_0804_8P4R_5%

1 8
2 7
3 6
4 5

56_0804_8P4R_5%

1 8
2 7
3 6
4 5

56_0804_8P4R_5%

C101

C100

1

2.2U_0603_6.3V6K

1

1

C108

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

C115

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+0.9VS

RP1

RP3

RP5

C102

1

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

1

C109

2

0.1U_0402_16V4Z

1

C117

C116

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

RP2

56_0804_8P4R_5%

RP4

56_0804_8P4R_5%

RP6

56_0804_8P4R_5%

2

1

C110

1

2

18
27
36
45

18
27
36
45

18
27
36
45

2

C103

1

2.2U_0603_6.3V6K

1

2

0.1U_0402_16V4Z

1

C119

C118

2

0.1U_0402_16V4Z

DDR_A _RAS#

DDR_A_MA4
DDR_A_MA2

DDR_A_BS 1

DDR_C KE1
DDR_A_MA7
DDR_A_MA6

DDR_A_MA11

DDR_A_MA12

DDR_A_MA9
DDR_A_MA8

DDR_A_MA10

Layou t Note:
Plac e near JD DR1

1

2

0.1U_0402_16V4Z

4

+1.8V

12

R74

1K_0402_1%

+DIMM_VREF

12

R75

1K_0402_1%

+DIMM_VREF

C104

0.1U_0402_16V4Z

1

1

1

C121

C120

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C122

C123

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

Layout Note:
Place these resistor
closel y DIMMA,all
trace length<750 mil

Shar e +DIM M_VREF fo r

1.DDR II VREF

2.GM CH SM_VRE F_0
SM_VRE F_1

20mils

1

2

3

1

C105

2.2U_0603_6.3V6K

2

2

+1.8V +1.8V

JDD R1

+DIMM_VREF

DDR_C KE0<6>

DDR_A_BS 2<7>

DDR_A_BS 0<7>
DDR_A_W E#<7> DDR_C S0# <6>

DDR_A _CAS#<7>

DDR_C S1#<6>

M_ODT1<6>

CLK_SMBDATA<12,19>

CLK_SMBCLK<12,19>

DDR_A _D0
DDR_A _D1

DDR_A _DQS#0
DDR_A _DQS0 DDR_A _D6

DDR_A _D2
DDR_A _D3

DDR_A _D16
DDR_A _D17

DDR_A _DQS#2
DDR_A _DQS2

DDR_A _D18
DDR_A _D19

DDR_A _D9
DDR_A _D8

DDR_A _DQS#1
DDR_A _DQS1

DDR_A _D10
DDR_A _D11

DDR_A _D24
DDR_A _D25

DDR_A_DM 3

DDR_A _D26
DDR_A _D27

DDR_C KE0

DDR_A_BS 2

DDR_A_MA12
DDR_A_MA9
DDR_A_MA8

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

DDR_A_MA10
DDR_A_BS 0
DDR_A_W E#

DDR_A _CAS#

M_ODT1

DDR_A _D32
DDR_A _D33

DDR_A _DQS#4
DDR_A _DQS4

DDR_A _D34
DDR_A _D35

DDR_A _D40
DDR_A _D41

DDR_A_DM 5

DDR_A _D42
DDR_A _D43

DDR_A _D48
DDR_A _D49

DDR_A _DQS#6
DDR_A _DQS6

DDR_A _D50
DDR_A _D51

DDR_A _D56
DDR_A _D57

DDR_A_DM 7

DDR_A _D58
DDR_A _D59

CLK_SMBDATA
CLK_SMBCLK

+3VS

1

C125

0.1U_0402_16V4Z

2

1

VREF

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

201

G1

FOX_AS0A426-N4RN -7F

@

DIMMA

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS

CK0
CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

VDD

VDD

BA1

RAS#

VDD

ODT0

NC/A13

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

CK1
CK1#

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

SA0

SA1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50

NC

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90

A11

92

A7

94

A6

96
98

A4

100

A2

102

A0

104
106
108
110

S0#

112
114
116
118
120

NC

122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

202

G2

DDR_A _D4
DDR_A _D5

DDR_A_DM 0

DDR_A _D7

DDR_A _D20
DDR_A _D21

DDR_A_DM 2

M_CLK_DD R0
M_CLK_DDR#0

DDR_A _D22
DDR_A _D23

DDR_A _D12
DDR_A _D13

DDR_A_DM 1

DDR_A _D14
DDR_A _D15

DDR_A _D28
DDR_A _D29

DDR_A _DQS#3
DDR_A _DQS3

DDR_A _D30
DDR_A _D31

DDR_C KE1

DDR_A_MA11
DDR_A_MA7
DDR_A_MA6

DDR_A_MA4
DDR_A_MA2
DDR_A_MA0

DDR_A_BS 1
DDR_A _RAS#
DDR_C S0#

M_ODT0
DDR_A_MA13DDR_C S1#

DDR_A _D36
DDR_A _D37

DDR_A_DM 4

DDR_A _D38
DDR_A _D39

DDR_A _D44
DDR_A _D45

DDR_A _DQS#5
DDR_A _DQS5

DDR_A _D46
DDR_A _D47

DDR_A _D52
DDR_A _D53

M_CLK_DD R1
M_CLK_DDR#1

DDR_A_DM 6

DDR_A _D54
DDR_A _D55

DDR_A _D60
DDR_A _D61

DDR_A _DQS#7
DDR_A _DQS7

DDR_A _D62
DDR_A _D63

R77 10K_0402_5%
R78 10K_0402_5%

1 2
1 2

R76

1 2

1

M_CLK_DD R0 <6>
M_CLK_DD R#0 <6>

0_0402_5%

DDR_C KE1 <6>

DDR_A_BS 1 <7>
DDR_A _RAS# <7>

M_ODT0 <6>

M_CLK_DD R1 <6>
M_CLK_DD R#1 <6>

PM_EXTTS#0 <6>

DDR_A_BS 2

DDR_C KE0

5

R79

1 2

56_0402_5%
R80

1 2

56_0402_5%

Layout Note:
Place these resistor
closel y DIMMA,all
trace length
Max=1.3"

4

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/11/17 2009/11/17

Compal Secret Data

Deciphered Date

2

Title

Size D ocument N umber Re v

Cus tom

Date: Sheet of

Compal Electronics, Inc.

DDRII-SODIMMA

KAVAA LA-5121P M/B

11 42Tuesday, March 10, 2009

1

1.0

5

PCI

SRC

CPU

CLKS EL1

0

FSA

CLKS EL0

MHz

266

MHz

1000

MHz

MHz

33.30

14.318 96.0 48.0

DOT_96
MHz

USB
MHz

FSC FSB REF

CLKS EL2

0 1000 133 33.31 14.318 96.0 48.0

0 1001 200 33.30 14.318 96.0 48.0

0 1001 166 33.31 14.318 96.0 48.0

D D

1 1000 333 33.30 14.318 96.0 48.0

1 1000 100 33.31 14.318 96.0 48.0

1 1001 400 33.30 14.318 96.0 48.0

1 1 1

C C

Res erv ed

2/25 PVT: Mount C142,C143,C86 8 with 22P

FSA

CPU_BSEL0<4,6>

CPU_BSEL1<4,6>

CPU_BSEL2<4,6>

B B

3/5 P VT:R eserve R427 with 0 ohm
3/5 P VT:A dd R428 with 10Kohm to +3VS

12

R86 2. 2K_0402_5%

R104 10 K_0402_5%

+3VS

12

CPU_BSE L1

FS C

R428

1 2

10K_0402_5%

2/25 PVT: Mount C144,C145,C14 6 with 22P

For ITP_ EN, 0 =SRC8/SRC8#; 1 = ITP/ITP#

For P CI4_ SEL, 0 = Pin24/25 : DOT96 / DOT9 6#
Pin28 /29 : LCDCLK / LCDCLK#

For PC I2_TME :0=Overclocking of CPU and SRC allowed
(ICS o nly) 1=Overclocking of CPU and SRC N OT allowed

A A

C147 22P_0402_50V8J

14.31818MHZ_16P F_DSX840GA

C148 22P_0402_50V8J

Y1

CLK_XTAL_IN

12

CLK_XTAL_OUT

Rou ti ng the t race at least 10mil

5

4

+3VM_CK505

1 2

+3VS

FBMH1608HM601-T_0603

For WW AN re que st

1 2

+1.05VS

FBMH1608HM601-T_0603

R81

R82

250 mA

1

C126

10U_0805_10V4Z

2

+1.05VM_CK505

80 mA

1

C134

10U_0805_10V4Z

2

1

2

1

2

2/25 PVT: Chan ge R8 1,R82 form 0 oh m to FBMH1608HM 601

SA000020K00 (Silego : SLG8SP556VTR )
SA000020H10 (ICS : ICS9LPRS387AKLFT)

+1.05VM_CK505

CLK_4 8M_C R and CLK_ICH_4 8M
need to same leng h

H_STP_CPU#<17>

H_STP_PCI#<17>

CLK_P CI_DDR<28>

CLK_P CI_LPC<26>

CLK_P CI_ICH<15>

VGATE<17,26 ,37>

PCI4_SEL

R114

10K_0402_5%

1 2

C142 22P_0402 _50V8J

1 2

1 2

C143 22P_0402 _50V8J

C868 22P_0402 _50V8J

1 2

1 2

1 2

1 2

R427 0_0402_5%@

1 2

For WW AN re que st

C144 22P_0402 _50V8J

1 2

1 2

C145 22P_0402 _50V8J

1 2

1 2

1 2

1 2

+3VS

R112

10K_0402_5%

1 2

@

R115

10K_0402_5%

1 2

C146 22P_0402_50V8J

R9022_0402_5%

R9122_0402_5%

FS B

R9333_0402_5%

R10333_0402_5%

R10733_0402_5%

R10833_0402_5%

For WW AN re que st

CLK_48M_CR<25>

CLK_I CH_48M<17>

CLK_I CH_14M<17>

For WW AN re que st

1 = P in24 /25 : SRC_0 / SRC_0#
P in28 /29 : 27M/27M_S S

ITP_EN PCI2_ TME

R113

10K_0402_5%

1 2

4

C127

0.1U_0402_16 V4Z

C135

0.1U_0402_16 V4Z

+3VM_CK505

FSA

CPU_BSE L1

FS C

VGATE

H_STP_CP U#

H_STP_P CI#_RH_STP_P CI#_R

CLK_XTAL_IN

CLK_XTAL_OUT

CLK_P CI_DD R_R

PCI2_TME

PCI4_SEL

ITP_EN

3

1

C128

0.1U_0402_16 V4Z

2

1

C136

0.1U_0402_16 V4Z

2

1

C129

0.1U_0402_16 V4Z

2

1

C137

0.1U_0402_16 V4Z

2

1

C130

0.1U_0402_16 V4Z

2

1

C138

0.1U_0402_16 V4Z

2

1

C131

0.1U_0402_16 V4Z

2

1

C139

0.1U_0402_16 V4Z

2

2

1

C132

0.1U_0402_16 V4Z

2

1

C140

0.1U_0402_16 V4Z

2

2/25 PVT: Mount C133 ,C141 with 47P

U4

55

VDD_SRC

6

VDD_REF

12

VDD_PCI

72

VDD_CPU

19

VDD_48

27

VDD_PLL3

66

VDD_CPU_IO

31

VDD_PLL3_IO

62

VDD_SRC_IO

52

VDD_SRC_IO

23

VDD_IO

38

VDD_SRC_IO

20

USB_0/FS_A

2

FS_B/TEST_MODE

7

REF_0/FS_C/TEST_

8

REF_1

1

CKPWRGD/PD#

11

NC

53

CPU_STOP#

54

PCI_STOP#

5

XTAL_IN

4

XTAL_OUT

13

PCI_1

14

PCI_2

15

PCI_3

16

PCI_4/SEL_LCDCL

17

PCIF_5/ITP_EN

18

VSS_PCI

3

VSS_REF

22

VSS_48

26

VSS_IO

69

VSS_CPU

30

VSS_PLL3

34

VSS_SRC

59

VSS_SRC

42

VSS_SRC

73

VSS

SLG8SP556VT R_QFN72_10X10

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

SRC_0/DOT_96

SRC_0#/DOT_96#

LCDCLK/27M

LCDCLK#/27M_SS

SRC_8/CPU_ITP

SRC_8#/CPU_ITP#

SRC_10#

SRC_11#

CLKREQ_3#

CLKREQ_4#

CLKREQ_6#

CLKREQ_7#

CLKREQ_9#

SLKREQ_10#

CLKREQ_11#

USB_1/CLKREQ_A#

2008/11/17 2009/11/17

2/5 D VT: Reserve C509,C510 with 10P

CLK_SMBDATA

9

SDA

CLK_SMBCLK

10

SCL

CLK_ CPU_BCLK

71

CPU_0

CLK_ CPU_BCLK#

70

CPU_0#

CPU_1#

SRC_2#

SRC_3#

SRC_4#

SRC_6#

SRC_7#

SRC_9#

SRC_10

SRC_11

CPU_1

SRC_2

SRC_3

SRC_4

SRC_6

SRC_7

SRC_9

CLK_MCH_ BCLK

68

CLK_MCH_ BCLK#

67

C509 10 P_0402_50V8J@

24

CLK_M CH_DREFCLK#

25

C510 10 P_0402_50V8J@

MCH_S SCDREFCLK

28

MCH_S SCDREFCLK#

29

CLK_MCH_3GP LL

32

CLK_MCH_3GPL L#

33

CLK_PCIE_SATA

35

CLK_PCIE_S ATA#

36

CLK_PCI E_WWAN

39

CLK_PCIE_W WAN#

40

CLK_PCI E_WLAN

57

CLK_PCI E_WLAN#

56

61

60

64

63

CLK_P CIE_LAN

44

CLK_PCI E_LAN#

45

CLK_P CIE_ICH

50

CLK_P CIE_ICH#

51

48

47

SATA_CLKREQ#

37

WW AN_CLKREQ#

41

WL AN_CLKREQ#

58

65

LAN_C LKREQ#

43

49

46

MCH_CLK REQ#

21

1 2

CLK_M CH_DREFCLK

1 2

Compal Secret Data

Deciphered Date

2

C133

47P_0402_50V8J

For WW AN re que st

C141

47P_0402_50V8J

CLK_SMBDATA <11,19>

CLK_SMBCLK <11, 19>

CLK_C PU_BCLK <4>

CLK_C PU_BCLK# <4>

CLK_MCH_ BCLK <6>

CLK_MCH_BC LK# <6>

CLK_M CH_DREFCLK <6>

CLK_M CH_DREFCLK# <6>

MCH_S SCDREFCLK <6>

MCH_S SCDREFCLK# <6>

CLK_MCH_3GPL L <8>

CLK_MCH_3GPLL# <8>

CLK_PCIE_S ATA <16>

CLK_PCIE_S ATA# <16>

CLK_PCIE_ WWAN <19>

CLK_PCIE_ WWAN# <19>

CLK_PCI E_WLAN <19>

CLK_PCIE_ WLAN# <19>

CLK_PCI E_LAN <24>

CLK_PCI E_LAN# <24>

CLK_P CIE_ICH <17>

CLK_P CIE_ICH# <17>

SATA_CLKREQ# <17>

WW AN_CLKREQ# <19>

WLA N_CLKREQ# <19>

LAN_CLK REQ# <24>

MCH_CLKRE Q# <6>

1

+3VS

ICH_SMBDATA<17>

ICH_SMB CLK<17>

2.2K_0402_5%

Q1A

2N7002DW-T /R7_SOT363-6

6 1

+3VS

3

Q1B 2N7002DW-T/ R7_SOT363-6

R83

2

5

4

R84

2.2K_0402_5%

CLK_SMBDATA

CLK_SMBCLK

SRC PORT LIST

PORT

SRC0
SRC2
SRC3
SRC4
SRC6
SRC7
SRC8
SRC9
SRC10
SRC11

MCH_CLK REQ#
SATA_CLKREQ#
WL AN_CLKREQ#
WW AN_CLKREQ#
LAN_C LKREQ#

DEVICE

MCH_DREFCLK
PCIE_3GPLL
PCIE_SATA
PCIE_WWAN
PCIE_WLAN

PCIE_LAN
PCIE_ICH

R97 10K_0402_5%
R98 10K_0402_5%
R99 10K_0402_5%
R100 10K_0402_5%
R101 10K_0402_5%

12
12
12
12
12

REQ PORT LIST

DEVICEPORT

REQ_3#
REQ_4#
REQ_6#
REQ_7#
REQ_9#
REQ_10#
REQ_11#
REQ_A#

Title

Size Docum ent Number Re v

Date : Sheet o f

Compal Electronics, Inc.

PCIE_SATA
PEIC_WWAN
PEIC_WLAN

PCIE_LAN

MCH_3GPLL

Clock Generator CK505

KAVAA LA-5121P M/B

1

12 42Tuesd ay, March 10, 2009

+3VS

1.0

5

4

3

2

1

LCD POWER CIRCUIT

D D

2N7 002DW -T/R7_SOT363-6

GM CH_ENV DD<8>

C C

LED/PANEL BD. Conn.

R376 0_080 5_5%

250m A

C468

@

B+

+3VS

1

680P_04 02_50V7K

2

450m A

B B

+L CDVDD

680P_04 02_50V7K

For EM I req uest

1 2

R377 0_080 5_5%

1 2

1

C469

@

2

+L CDVDD

12

3

Q2B

4

100K_04 02_5%

BKO FF#<26 >

LVD S_A0<8>
LVD S_A0#<8>

LVD S_A1<8>
LVD S_A1#<8>

LVD S_A2<8>
LVD S_A2#<8>

LVD S_ACLK<8>
LVD S_ACLK#<8>

R116
150_060 3_5%

5

12

R142

C188680P_04 02_50V7K

12

C18968P_040 2_50V8J

12

1/2 2 D VT: Cha nge R117 from 47K to 100K

+3VS

12

R117
100K_04 02_5%

R141 47K_0 402_5%

61

Q2A

2

2N7 002DW -T/R7_SOT363-6

1

C183

0.1U _0402_16V7 K

2

12

1

C498

0.01 U_0402_25V 7K

2

1/2 2 D VT: Add C498 with 0.01uF

3/4 PV T:D el JLV DS pi n2

JLV DS

1

1

GND

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

GND

ACE S_87213-2000 G

@

21

22

(20 MIL)

LVD S_A0
LVD S_A0#

LVD S_A1
LVD S_A1#

LVD S_A2
LVD S_A2#

LVD S_ACLK
LVD S_ACLK#

+L EDVDD

+L CDVDD_ L

LCD _PWM
BKO FF#
LVD S_SDA
LVD S_SCL

G

2

W=40mils

+3VS

S

2A

D

Q11

1 3

AO3413_ SOT23

1

C186

@

4.7U _0805_10 V4Z

2

1

C149

@

4.7U _0805_10 V4Z

2

1/2 2 D VT: Cha nge Q1 1 fro m SI23 01BDS to A0 3413

+L CDVDD

W=40mils

1

C187

0.1U _0402_16 V4Z

2

R14 3

LVD S_SCL

LVD S_SDA

R419 0 _0402_5%

INVT_P WM<26>

GMCH _INVT_PW M< 8>

1 2

R420 0 _0402_5%@

1 2

3/4 PV T:A dd sup port D PST fu nction

+3VS

10K_0 402_5%

1 2

1 2

LCD _PWM

R14 4

10K_0 402_5%

LVD S_SCL <8>

LVD S_SDA <8>

LVD S_ACLK L VDS_AC LK#

C871 10P_0 402_50V8J

A A

1 2

2/2 5 P VT: Mou nt C8 71 wit h 10pF

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/11/17 2009/11/17

3

Compal Secret Data

Deciphered Date

Title

Size Do cumen t Numb er R ev

2

Da te: Sheet o f

Compal Electronics, Inc.

LVDS /INVERTER

KAVAA LA-5121P M/B

13 42Tu esday, M arch 10 , 2009

1

1.0

A

B

C

D

E

Place closed to conn.

CRT CONNECTOR

1

D2

1

D3

1

D4

2/16 DVT: Mount C504 for EMI request

1

C504

0.1U _0402_16 V4Z

2

CRT _R_LGMCH _CRT_ R

CRT _G_L

CRT _B_L

+3VS

2

3

@

DAN 217_SC 59

1 1

2

3

@

DAN 217_SC 59

2

3

@

DAN 217_SC 59

Place closed to conn.

L6

GMCH _CRT_ R<8>

12

150_0 402_1%

GMCH _CRT_G

GMCH _CRT_B

12

R147

1

1

C191

2.2 P_0402_50V 8C

C192

2

2.2 P_0402_50V 8C

C190

150_0 402_1%

2

GMCH _CRT_G< 8>

GMCH _CRT_B<8>

12

R145

R146

150_0 402_1%

1 2

BLM 15AG121SN1D _0402

L7

1 2

BLM 15AG121SN1D _0402

L8

1 2

BLM 15AG121SN1D _0402

1

2

2.2 P_0402_50V 8C

C193

1

2

1

C194

2

2.2 P_0402_50V 8C

1

C195

2

2.2 P_0402_50V 8C

2.2 P_0402_50V 8C

2 2

1 2

C196 0. 1U_04 02_16V4Z

GM CH_C RT_HS YNC<8>

SN7 4AHCT1 G125D CKR_SC70-5

GM CH_C RT_VSYN C<8>

3 3

+3VS

12

R151

4.7K_ 0402_5%

GMCH _CRT_DA TA< 8>

GMCH _CRT_ CLK<8>

4 4

+CR T_VCC

1

5

U13

P

OE#

A2Y

G

3

1 2

C197 0. 1U_04 02_16V4Z

12

R15 2

4.7K_ 0402_5%

Q3B

2N7 002DW -T/R7_SOT363-6

2

Q3A

2N7 002DW -T/R7_SOT363-6

4

+CR T_VCC

1

5

P

OE#

A2Y

G

SN7 4AHCT1 G125D CKR_SC70-5

3

+3VS

4.7K_ 0402_5%

5

4

3

61

470P_04 02_50V8J

1 2

R148 10K_0 402_5%

U14

4

+CR T_VCC

12

R153

C201

@

CR T_HS YNC_1

CR T_VS YNC_1

12

R154

4.7K_ 0402_5%

CR T_DDC_ DAT

CR T_DDC _CLK

1

2

1

C202
470P_04 02_50V8J

2

@

R149 39_04 02_5%

1 2

R150 39_04 02_5%

1 2

C198

+5VS

2

3

1

2

If= 1A

D5

HS YN C

VS YNC

1

C199

2

33P_0 402_50V8K

33P_0 402_50V8K

3/02 PVT:Change D5 from SC1B491D000 to SCS00002000.

+CR T_VCC_ R +CR T_VCC

1

RB4 91D_SOT23-3

CRT _R_L

CR T_DDC_ DAT
CRT _G_L

HS YN C
CRT _B_L

VS YNC

CR T_DDC _CLK

F1

+CR T_VCC

30m il

21

1.1A _6V_M INISMDC1 10F-2

C200

0.1U _0402_16 V4Z@

JC RT

6

RGND

11

ID0

1

Red

7

GGND

12

SDA

2

Green

8

BGND

13

Hsync

3

Blue

9

+5V

14

Vsync

4

res

10

SGND

15

SCL

5

GND

16

GND

17

GND

1

2

SU YIN_0705 46FR0 15S263 ZR

@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/11/17 2009/11/17

C

Compal Secret Data

Deciphered Date

Title

Size Do cumen t Numb er R ev

D

Da te: Sheet o f

Compal Electronics, Inc.

CRT PORT

KAVAA LA-5121P M/B

14 42Tu esday, M arch 10 , 2009

E

1.0

5

D D

4

3

2

1

U15 B

E18

AD0

C18

AD1

A16

AD2

F18

AD3

E16

+3VS

R157 8.2 K_0402_5%

1 2

R166 8.2 K_0402_5%

1 2

R168 8.2 K_0402_5%

1 2

R169 8.2 K_0402_5%

1 2

C C

+3VS

+3VS

B B

+3VS

R170 8.2 K_0402_5%

1 2

R171 8.2 K_0402_5%

1 2

R172 8.2 K_0402_5%

1 2

R174 8.2 K_0402_5%

1 2

R175 8.2 K_0402_5%

1 2

R178 8.2 K_0402_5%

1 2

RP1 0

1 8
2 7
3 6
4 5

8.2K _0804_8P4 R_5%

RP1 1

1 8
2 7
3 6
4 5

8.2K _0804_8P4 R_5%

RP1 2

1 8
2 7
3 6
4 5

8.2K _0804_8P4 R_5%

PC I_FRAME #

PC I_PIR QC#

PC I_PIRQ E#

PC I_PIR QF#

PC I_PIRQ G#

PC I_PIR QH#

PC I_REQ#0

PC I_REQ#1

PC I_REQ#2

PC I_REQ#5

PCI_S TOP#
PC I_TRD Y#
PC I_REQ#3
PC I_REQ#4

PCI_D EVSEL#
PCI_P LOCK#
PC I_SERR #
PC I_PERR #

PC I_I RDY#
PC I_PIR QD#
PC I_PIRQ B#
PC I_PIRQ A#

PC I_PIRQ A#
PC I_PIRQ B# PC I_PIR QF#
PC I_PIR QC#
PC I_PIR QD#

AD4

A18

AD5

E17

AD6

A17

AD7

A15

AD8

C14

AD9

E14

AD10

D14

AD11

B12

AD12

C13

AD13

G15

AD14

G13

AD15

E12

AD16

C11

AD17

D11

AD18

A11

AD19

A10

AD20

F11

AD21

F10

AD22

E9

AD23

D9

AD24

B9

AD25

A8

AD26

A6

AD27

C7

AD28

B6

AD29

E6

AD30

D6

AD31

Interrupt I/F

A3

PIRQA#

B4

PIRQB#

C5

PIRQC#

B5

PIRQD#

AE5

RSVD[1]

AD5

RSVD[2]

AG4

RSVD[3]

AH4

RSVD[4]

AD9

RSVD[5]

ICH7_ BGA652

PCI

REQ4# / GPIO22
GNT4# / GPIO48

GPIO1 / REQ5#

GPIO17 / GNT5#

GPIO2 / PIRQE#
GPIO3 / PIRQF#

GPIO4 / PIRQG#

GPIO5 / PIRQH#

MISC

MCH_SYNC#

REQ0#
GNT0#
REQ1#
GNT1#
REQ2#
GNT2#
REQ3#
GNT3#

C/BE0#
C/BE1#
C/BE2#
C/BE3#

IRDY#

PAR

PCIRST#

DEVSEL#

PERR#

PLOCK#

SERR#

STOP#
TRDY#

FRAME#

PLTRST#

PCICLK

PME#

RSVD[6]
RSVD[7]
RSVD[8]
RSVD[9]

D7
E7
C16
D16
C17
D17
E13
F13
A13
A14
C8
D8

B15
C12
D12
C15

A7
E10
B18
A12
C9
E11
B10
F15
F14
F16

C26
A9
B19

G8
F7
F8
G7

AE9
AG8
AH8
F21
AH20

PC I_REQ#0

PC I_REQ#1

PC I_REQ#2

PC I_REQ#3

PC I_REQ#4

PC I_REQ#5

PC I_I RDY#

PCI_R ST#
PCI_D EVSEL#
PC I_PERR #
PCI_P LOCK#
PC I_SERR #
PCI_S TOP#
PC I_TRD Y#

PC I_FRAME #

PLTRST#
CL K_PC I_ICH

PC I_PIRQ E#

PC I_PIRQ G#
PC I_PIR QH#

For EC r eques t.

1 2

R179

R165

1 2

100K_04 02_5%

100K_04 02_5%

PCI_R ST# <26>

PLTRST# < 6,17,19 ,24,28>
CL K_PC I_ICH <12>

MC H_ICH _SYN C# <6>

2/2 5 P VT: Mou nt C20 3,C204 for W WAN r equest

For EMI, close to ICH7

PCI_R ST#

PLTRST#

1

1

C20 3

C20 4

2

2

0.1 U_0402_ 16V4Z

0.1 U_0402_ 16V4Z

Pla ce cl ose ly pin A9

CL K_PC I_ICH

@

R173

10_0402 _5%

8.2P _0402_50V8 D

C205

1 2

1

@

2

12/ 18 Cha nge pa ckag e to 8 P4R wi th 8. 2K

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/11/17 2009/11/17

3

Compal Secret Data

Deciphered Date

Title

Size Do cumen t Numb er R ev

2

Da te: Sheet o f

Compal Electronics, Inc.

ICH7M(1/4)HUB,PCI,HOST

KAVAA LA-5121P M/B

15 42Tu esday, M arch 10 , 2009

1

1.0

5

4

3

2

1

1

D D

+RTCVCC

1

C454

0.1U_0402_16V4Z

2

C C

B B

HDA_B ITCLK<22>

HDA_S DOUT<22>

2

3

HDA _SYNC<22>

HDA_RST#<22>

+RTCBATT

D32
BAS40-04_SOT23-3

+CHGRTC

R182

+RTCVCC

+RTCVCC

ICH_IN TVRMEN

1 2

R185 332K_0402_1%

R186 1M_0402_5%

12/ 21 De l R1 90 w ith 8.2K ohm
Cha ng e R 18 9 fro m 4.7 K to 10 Kohm for cus tome r

+3VS

R189 10K_0402_5%

R191 10K_0402_5%

R193 39_0402_5%

R194 39_0402_5%

R195 39_0402_5%

R196 39_0402_5%

1 2

1 2

1 2

1 2

1 2

1 2

1 2

SM_INTR UDER#

IDE _DIO RDY_IRQ

SATALED#

1 2

20K_0402_5%

J1

@

C209

1U_0402_6.3V4Z

1 2

C207

18P_0402_50V8J

12

32.768K_1TJS125BJ4A421 P

2

3

C208

18P_0402_50V8J

12

21

3MM

SYNC _ICH

BITCL K_ICH

RST#_ICH

SDOUT _ICH

Y2

1

IN

NC

4

OUT

NC

SATALED#<29>

SATA_IRX_C_DTX_N0<21>
SATA_IRX_C_DTX_P0<21>
SATA_ITX_DRX_N0<21>
SATA_ITX_DRX_P0<21>

12/ 23 Th e un used port RX
sig na ls mu st be p rope rly
tie d to grou nd

CLK_PCIE_SATA#<12>
CLK_PCIE_SATA<12>

ICH_RTCX1

ICH_RTCX2

HDA_S DIN0<22>

12

R181

10M_0402_5%

SATALED#

SATA_IRX_C_DTX_N0
SATA_IRX_C_DTX_P0
SATA_ITX_DRX_N0
SATA_ITX_DRX_P0

CLK_PCIE_SATA#
CLK_PCIE_SATA

R192 24.9_0402_1%

10mils width less
than 500mils

ICH_R TCRST#

ICH_IN TVRMEN
SM_INTR UDER#

BITCL K_ICH
SYNC _ICH

RST#_ICH

SDOUT _ICH

SATARBIAS

12

IDE _DIO RDY_IRQ

AB1
AB2

AA3

AF18

AF3
AE3
AG2
AH2

AF7
AE7
AG6
AH6

AF1
AE1

AH10
AG10

AG16
AH16

AF16

AH15

AF15

W4

Y5

W1

Y1
Y2

W3

V3

U3

U5
V4

T5

U7
V6
V7

U1
R6

R5

T2
T3
T1

T4

U15A

RTXC1
RTCX2

RTCRST#

INTVRMEN
INTRUDER#

EE_CS
EE_SHCLK
EE_DOUT
EE_DIN

LAN_CLK

LAN_RSTSYNC

LAN_RXD0
LAN_RXD1
LAN_RXD2

LAN_TXD0
LAN_TXD1
LAN_TXD2

ACZ_BCLK
ACZ_SYNC

ACZ_RST#

ACZ_SDIN0
ACZ_SDIN1
ACZ_SDIN2

ACZ_SDOUT

SATALED#

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

SATA_CLKN
SATA_CLKP

SATARBIASN
SATARBIASP

IORDY
IDEIRQ
DDACK#
DIOW#
DIOR#

ICH7_BGA652

RTC

GPIO49 / CPUPWRGD

LPCCPU

LDRQ1# / GPIO23

LFRAME#

LAN

A20GATE

CPUSLP#

TP1 / DPRSTP#

TP2 / DPSLP#

INIT3_3V#

AC-97/AZALIA

STPCLK#

THERMTRIP#

SATA

IDE

LAD0
LAD1
LAD2
LAD3

LDRQ0#

A20M#

FERR#

IGNNE#

INIT#

INTR

RCIN#

SMI#

DCS1#
DCS3#

DD10
DD11
DD12
DD13
DD14
DD15

DDREQ

DA0
DA1
DA2

DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9

LPC_AD0

AA6

LPC_AD1

AB5

LPC_AD2

AC4

LPC_AD3

Y6

AC3
AA5

LPC_FRAME#

AB3

GATEA20

AE22

H_A20M#

AH28

AG27

H_DPRSTP#

AF24

H_DPSLP#

AH25

H_FER R#

AG26

H_PW RGOOD

AG24

H_IGNN E#

AG22
AG21

H_INIT#

AF22

H_INT R

AF25

EC_KBRST#

AG23

H_SMI#

AF23

H_NMI

AH24

NMI

AH22

AF26

AH17
AE17
AF17

AE16
AD16

AB15
AE14
AG13
AF13
AD14
AC13
AD12
AC12
AE12
AF12
AB13
AC14
AF14
AH13
AH14
AC15

AE15

H_STPCLK#

THRM TRIP_ICH#

LPC_A D[0..3] <26,28>

LPC_FRAME# <26,28>

R183 10K_0402_5%

12

GATEA20 <26>
H_A20M# <4>

56_0402_5%

12

H_FER R# <4>

H_PW RGOOD <4>

H_IGNN E# <4>

H_INIT# <4>
H_INTR <4>

EC_KBRST# <26>

H_SMI# <4 >
H_NMI <4>

H_STPCLK# <4>

R188

1 2

24.9_0402_1%

+3VS

H_DPRSTP# <4,37>
H_DPSLP# <4>

+1.05VS

R184

+1.05VS

12

R187
56_0402_5%

Layout note: R187 needs to placed
within 2" of ICH7, R193 mu st be placed
within 2 " of R187 w/o stub.

H_THERMTRIP# <4,6>

A A

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/11/17 2009/11/17

Compal Secret Data

Deciphered Date

Title

Size D ocument N umber Re v

Cus tom

2

Date: Sheet of

Compal Electronics, Inc.

ICH7M(2/4)LAN,ATA,LPC,RTC

KAVAA LA-5121P M/B

16 42Tuesday, March 10, 2009

1

1.0

5

4

3

2

1

+3VS

10K_0402_5%

R197

1 2

8.2K_0402_5%

R198

+3V_SB

R220

R207

R208

R209

R210

R212

R213

R214

R217

R218

R219

1 2

8.2K_0402_5%

10K_0402_5%

1 2

10K_0402_5%

1 2

10K_0402_5%

1 2

10K_0402_5%@

1 2

10K_0402_5%@

1 2

1K_0402_5%

1 2

8.2K_0402_5%

10K_0402_5%@

1 2

8.2K_0402_5%@

10K_0402_5%@

1 2

RP7

RP8

D D

C C

+3V_SB

B B

SERIR Q

PM_CLKRUN#

BT_DET#

12

LINKALERT#

ITP_DBRESET#

OCP#

SPI_MISO

SB_SPI_CS#

EC_SW I#

ICH_LOW_B AT#

12

SPI_MOSI

EC_SMI#

12

EC_SC I#

USB_OC#0_ 2_D

45
36

USB_OC#1

27

USB_OC#3

18

10K_0804_8P4R_5%

USB_OC#4

45

SLP_CHG_M3

36

SLP_CHG_M4

27

USB_OC#7_ D

18

10K_0804_8P4R_5%

R199

10K_0402_5%

R200

10K_0402_5%

1 2

1 2

ICH_SMBCLK<12>

ICH_SMBDATA<12>

2/2 5 PVT :C ha nge n et na me fr om I CH_P CIE_W AKE# to EC_S WI#

WL AN

LAN

WW L AN

PCIE_PTX_C_IRX_N2<19>
PCIE_PTX_C_IRX_P2<19>

PCIE_ITX_C_PRX_N2<19>

PCIE_ITX_C_PRX_P2<19>

PCIE_PTX_C_IRX_N3<24>
PCIE_PTX_C_IRX_P3<24>

PCIE_ITX_C_PRX_N3<24>

PCIE_ITX_C_PRX_P3<24>

PCIE_PTX_C_IRX_N4<19>
PCIE_PTX_C_IRX_P4<19>

PCIE_ITX_C_PRX_N4<19>

PCIE_ITX_C_PRX_P4<19>

2/2 5 PVT :R es erv e WWL AN PC IE I nter face

+3VALW

R410
330K_0402_5%

@

1 2

USB_OC#7_ D

3/5 P VT: Ad d R42 3, R42 4, Rese rve R410 ,R42 1,D4 4,D45

A A

USB_OC#0_ 2_D

D44

2 1

CH751H-40PT_S OD323-2@

1 2

R423 0_0402_5%

D45

2 1

CH751H -40PT_SOD323-2@

1 2

R424 0_0402_5%

5

+3VALW

1 2

R421
330K_0402_5%

@

USB_OC#7 <20,26>

3/4 P VT: Fo r USB o ver curr ent prote ct

USB_OC#0_2 <20,26>

+3V_SB+3V_SB

12

12

R202

R201

SB_SPKR<22>

H_STP_PCI#<12>

EC_SW I#<26>
SERIR Q<26>

BT_DET#<21>

EC_SMI#<2 6>

4

2.2K_0402_5%

R203

1 2

8.2K_0402_5%

T9PAD

12
12

12
12

12
12

SLP_CHG_M3<20>
SLP_CHG_M4<20>

2.2K_0402_5%

+3V_SB

PM_BMBUSY#<6>

H_STP_CPU#<12>

EC_THERM#<26>

C213 0.1U_0402_16V7K
C214 0.1U_0402_16V7K

C215 0.1U_0402_16V7K
C216 0.1U_0402_16V7K

C217 0.1U_0402_16V7K@
C218 0.1U_0402_16V7K@

ICH_SMBCLK
ICH_SMBDATA
LINKALERT#
ICH_S MLINK0
ICH_S MLINK1

ICH _RI#

SB_SPKR
SUS_STAT#
ITP_DBRESET#

PM_BMBUSY#

OCP#

H_STP_PCI#
H_STP_CPU#

PM_CLKRUN#

EC_SW I#
SERIR Q
EC_THERM#

VGATE

BT_DET#

EC_SMI#

U15C

C22

SMBCLK

B22

SMBDATA

A26

LINKALERT#

B25

SMLINK0

A25

SMLINK1

A28

RI#

A19

SPKR

A27

SUS_STAT#

A22

SYS_RST#

AB18

GPIO0 / BM_BUSY#

B23

GPIO11 / SMBALERT#

AC20

GPIO18 / STPPCI#

AF21

GPIO20 / STPCPU#

A21

GPIO26

B21

GPIO27

E23

GPIO28

AG18

GPIO32 / CLKRUN#

AC19

GPIO33 / AZ_DOCK_EN#

U2

GPIO34 / AZ_DOCK_RST#

F20

WAKE#

AH21

SERIRQ

AF20

THRM#

AD22

VRMPWRGD

AC21

GPIO6

AC18

GPIO7

E21

GPIO8

ICH7_ BGA652

PCIE_PTX_C_IRX_N2

PCIE_PTX_C_IRX_P2

PCIE_ITX_PRX_N2
PCIE_ITX_PRX_P2

PCIE_PTX_C_IRX_N3

PCIE_PTX_C_IRX_P3

PCIE_ITX_PRX_N3
PCIE_ITX_PRX_P3

PCIE_PTX_C_IRX_N4

PCIE_PTX_C_IRX_P4

PCIE_ITX_PRX_N4
PCIE_ITX_PRX_P4

SB_SPI_CS#

SPI_MOSI
SPI_MISO

USB_OC#0_ 2_D
USB_OC#1
USB_OC#0_2
USB_OC#3
USB_OC#4
SLP_CHG_M3
SLP_CHG_M4
USB_OC#7_ D

+3VS

R204

8.2K_0402_5%

1 2

CLK_ICH_14M
CLK_ICH_48M

ICH_S USCLK

PM_SLP_S3#
PM_SLP_S4#
PM_SLP_S5#

ICH_P WROK

PM_DPRSLPVR

ICH_LOW_B AT#

PBTN_OUT#

PLTRST#

SB_RSMRST#

EC_SC I#
ICH _ACIN

EC_LID_OUT#
SLP_CHG#

SATA_CLKREQ#

DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0

DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1

CLK_P CIE_ICH#
CLK_P CIE_ICH

DMI_IRCOM P

USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5
USB20_N6
USB20_P6
USB20_N7
USB20_P7

USBR BIAS

Compal Secret Data

CLK14
CLK48

SUSCLK

SLP_S3#
SLP_S4#
SLP_S5#

PWROK

PWRBTN#

LAN_RST#

RSMRST#

GPIO9
GPIO10
GPIO12
GPIO13
GPIO14
GPIO15
GPIO24
GPIO25

GPIO38
GPIO39

DMI0RXN
DMI0RXP
DMI0TXN

DMI0TXP

DMI1RXN
DMI1RXP
DMI1TXN

DMI1TXP

DMI2RXN
DMI2RXP
DMI2TXN

DMI2TXP

DMI3RXN
DMI3RXP
DMI3TXN

DMI3TXP

DMI_CLKN
DMI_CLKP

DMI_ZCOMP

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P

USBRBIAS#

USBRBIAS

AF19
AH18
AH19
AE19

AC1
B2

C20

B24
D23
F22

AA4

AC22

C21

C23

C19

Y4

E20
A20
F19
E19
R4
E22
R3
D20
AD21
AD20
AE20

V26
V25
U28
U27

Y26
Y25
W28
W27

AB26
AB25
AA28
AA27

AD25
AD24
AC28
AC27

AE28
AE27

C25
D25

F1
F2
G4
G3
H1
H2
J4
J3
K1
K2
L4
L5
M1
M2
N4
N3

D2
D1

2008/11/17 2009/11/17

GPIO21 / SATA0GP

SMB

GPIO19 / SATA1GP
GPIO36 / SATA2GP
GPIO37 / SATA3GP

SATA

GPIO

SYS

Clocks

GPIO

GPIO16 / DPRSLPVR

TP0 / BATLOW#

POWER MGT

H26
H25
G28
G27

M26
M25

N28
N27

R28
R27

F26
F25
E28
E27

K26
K25

J28
J27

L28
L27

P26
P25

T25
T24

R2
P6
P1

P5
P2

D3
C4
D5
D4
E5
C3
A2
B3

GPIO

U15D

PERn1
PERp1
PETn1
PETp1

PERn2
PERp2
PETn2
PETp2

PERn3
PERp3
PETn3
PETp3

PERn4
PERp4
PETn4
PETp4

PERn5
PERp5
PETn5
PETp5

PERn6
PERp6
PETn6
PETp6

SPI_CLK
SPI_CS#
SPI_ARB

SPI_MOSI
SPI_MISO

OC0#
OC1#
OC2#
OC3#
OC4#
OC5# / GPIO29
OC6# / GPIO30
OC7# / GPIO31

ICH7_BGA652

GPIO35 / SATAREQ#

PCI-EXPRESS

DIRECT MEDIA IN TER FACE

DMI_IRCOMP

SPI

USB

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

12/ 4 SW rec omme nd

BT_RST# <21>

BT_OFF <21>

CLK_ICH_ 14M <12>
CLK_ICH_ 48M <12>

T10 PAD

PM_SLP_S3# <26>

PM_SLP_S4# <26>
PM_SLP_S5# <26>

PM_DPRSLPVR <6,37>

PBTN_OUT# <26>

PLTRST# <6,1 5,19,24,28>

EC_SC I# <26>

EC_LI D_OUT# <26>
SLP_CHG# <20>

SATA_CLKREQ# <12>

DMI_RXN0 <6 >
DMI_RXP0 <6>

DMI_TXN0 <6>
DMI_TXP0 <6>

DMI_RXN1 <6 >
DMI_RXP1 <6>

DMI_TXN1 <6>
DMI_TXP1 <6>

CLK_P CIE_ICH# <12>
CLK_P CIE_ICH <12>

R221 24.9_0402_1%

1 2

USB20_N0 <20>
USB20_P0 <20>
USB20_N1 <21>
USB20_P1 <21>
USB20_N2 <20>
USB20_P2 <20>
USB20_N3 <25>
USB20_P3 <25>
USB20_N4 <19>
USB20_P4 <19>
USB20_N5 <19>
USB20_P5 <19>
USB20_N6 <21>
USB20_P6 <21>
USB20_N7 <20>
USB20_P7 <20>

R222 22.6_0402_1%

1 2

Within 500 mils

Deciphered Date

BIO S nee d to
set GP IO

Within 500 mils

+1.5VS

USB1(Right)
CMOS
USB2(Right)
Card Reader
WiMAX
WWAN
BT
USB3(Left)

2

Pla ce c los el y pin B2 Pl ace clos ely p in AC1

CLK_ICH_48M

12

R205

10_0402_5%@

1

C211

4.7P_0402_50V8C@

2

2/2 5 PVT :C ha nge N et Name to I CH_P WROK

2/2 5 PVT :f or co rr ect ing pow er d own s eque nce

ICH_P WROK

1 2

R211 10K_0402_5%

EC_PWROK

1 2

R418 10K_0402_5%

@

1 2

R417 0_0402_5%

+3VS

5

U37

1

EC_PWROK<26>

VGATE<12,26,37>

12/ 18 Ad d RS MRS T# Ci rc uit f or l eaka ge c urre nt

SB_RSMRST#

1 2

R215
10K_0402_5%

D43B

BAV99DW-7_SOT363

R409

2.2K_0402_5%

ICH _ACIN

Title

Size D ocument Number Re v

Cus tom

Date: Sheet of

P

B

Y

2

A

G

TC7SH 08FUF_SSOP5

3

R406 0_0402_5%@

Q31

123

C

MMBT3906_SOT23-3

B

4

5

12

1

2

3

6

RSMRST# circuit

+3V_SB

R216
330K_0402_5%

1 2

Compal Electronics, Inc.

ICH7M(3/4)USB,GPIO,PCIE

KAVAA LA-5121P M/B

CLK_ICH_14M

12

R206

10_0402_5%@

1

C212

4.7P_0402_50V8C@

2

4

12

E

1 2

R408

4.7K_0402_5%

D43A
BAV99DW-7_SOT363

D6

2 1

CH751H-40PT_S OD323-2

1

ICH_P WROK <6>

EC_RSMRST# <26>

+3V_SB

ACIN <26,29,31>

1.0

17 42Tuesday, March 10, 2 009

5

+3VS+5VS

1/1 3 DV T:C han ge D 7 P/ N t o SC 1H75 1H0 10

21

12

R223

100_0402_5%

1U_0402 _6.3V4Z

D D

C C

B B

+1.5VS

D7
CH751H- 40PT_SOD323-2

+ICH _V5REF_RU N

1

C222

2

12

R224

10_0402_5%

SBPWR _EN#<26,30>

2N7002D W-T/R7_SOT363-6

+1.5VS

50mA

L9
MBK16081 21YZF_0603

1 2

0.1U_04 02_16V4Z

1 2

0.5_0805_1%

C250

+1.5VS

0.77A

1

+

C223

+3V_SB+5V_SB

21

D8
CH751H- 40PT_SOD323-2

+ICH_V 5REF_SUS

1

C226

0.1U_04 02_16V4Z

2

SBPWR _EN#

4

1 2

C496

0.1U_0402_25V6

SBPWR _EN#

R369 100K_0402_5%

Place clo se ly pin AG28 within 100mlis .

+1.5VS_ DMIPLLR

R227

1

2

220U_B2 _2.5VM_R35

1 2

R385 0_0603_5%

2N7002D W-T/R7_SOT363-6

Q4B

2

5

STAR@

1 2

3

R226

330K_0402_5%@

1 2

STAR@

1 2

STAR@

R228

1 2

0_0805_5%

2

0.1U_04 02_16V4Z

1/1 3 DV T:C han ge D 8 P/ N t o SC 1H75 1H0 10

61

Q4A

STAR@

R225
47K_0402_5%

STAR@

+3VS

+5VALW+5V_SB

+VSB

+5VALW

+1.5VS_DMIPLL

1

C248

C247

2

10U_0805_10V4Z

0.01U_0402_25V7K

+1.5VS_SATAPLL

1

C251

2

C227

1

2

0.1U_04 02_16V4Z

12/ 18 A dd L 15 f or ripp le

+3V_SB

0.1U_04 02_16V4Z

A A

C254

5

1

2

+1.5VS

L15

1 2

MBK16081 21YZF_0603

C255

0.1U_04 02_16V4Z

10mA

1

2

4

+ICH _V5REF_RU N

6mA

+ICH_V 5REF_SUS

10mA

0.1U_04 02_16V4Z

1

1

1

2

Place clo se ly p in
D28,T28,AD28.

C225

C224

2

0.1U_04 02_16V4Z

C240

0.1U_04 02_16V4Z

+1.5VS

0.64A

C249

0.1U_04 02_16V4Z

2

+3VS

1

2

+1.5VS_DMIPLL

1

2

Place clo se ly p in AG5.

+1.5VS

1U_0402 _6.3V4Z

C253

1

2

Place clo se ly p in AG9.

T14 PAD
T15 PAD

+3V_SB

ICH_ AA2
ICH _Y7

4

U15F

G10

AD17

F6

AA22
AA23
AB22

AB23
AC23
AC24
AC25
AC26
AD26
AD27
AD28

D26
D27
D28
E24
E25
E26

F23

F24
G22
G23
H22
H23

J22

J23
K22
K23

L22

L23

M22
M23

N22
N23
P22
P23
R22
R23
R24
R25
R26

T22

T23

T26

T27

T28
U22
U23
V22
V23

W22
W23

Y22
Y23

B27

AG28

AB7

AC6
AC7
AD6

AE6
AF5
AF6

AG5
AH5

AD2

AH11

AB10

AB9

AC10
AD10

AE10
AF10

AF9

AG9
AH9

E3

C1

AA2

Y7

V5

V1
W2
W7

ICH7_BGA652

1

C257

0.1U_04 02_16V4Z

2

3

+1.05VS

1

2

+3V_SB

0.27A

1

C234

2

0.1U_04 02_16V4Z

0.1U_04 02_16V4Z

1

1

C237

2

2

0.1U_04 02_16V4Z

1

C242

0.1U_04 02_16V4Z

2

1

C246

0.1U_04 02_16V4Z

2

Deciphered Date

0.94A

1

+

C221

220U_B2_2.5VM_R35

2

10mA

+3VS

1

C235

2

0.1U_04 02_16V4Z

+3VS

C238

0.1U_04 02_16V4Z

+3V_SB

+3V_SB

17mA

T11PAD

T12PAD
T13PAD

V5REF[1]

V5REF[2]

V5REF_Sus

Vcc1_5_B[1]
Vcc1_5_B[2]
Vcc1_5_B[3]
Vcc1_5_B[4]
Vcc1_5_B[5]
Vcc1_5_B[6]
Vcc1_5_B[7]
Vcc1_5_B[8]
Vcc1_5_B[9]
Vcc1_5_B[10]
Vcc1_5_B[11]
Vcc1_5_B[12]
Vcc1_5_B[13]
Vcc1_5_B[14]
Vcc1_5_B[15]
Vcc1_5_B[16]
Vcc1_5_B[17]
Vcc1_5_B[18]
Vcc1_5_B[19]
Vcc1_5_B[20]
Vcc1_5_B[21]
Vcc1_5_B[22]
Vcc1_5_B[23]
Vcc1_5_B[24]
Vcc1_5_B[25]
Vcc1_5_B[26]
Vcc1_5_B[27]
Vcc1_5_B[28]
Vcc1_5_B[29]
Vcc1_5_B[30]
Vcc1_5_B[31]
Vcc1_5_B[32]
Vcc1_5_B[33]
Vcc1_5_B[34]
Vcc1_5_B[35]
Vcc1_5_B[36]
Vcc1_5_B[37]
Vcc1_5_B[38]
Vcc1_5_B[39]
Vcc1_5_B[40]
Vcc1_5_B[41]
Vcc1_5_B[42]
Vcc1_5_B[43]
Vcc1_5_B[44]
Vcc1_5_B[45]
Vcc1_5_B[46]
Vcc1_5_B[47]
Vcc1_5_B[48]
Vcc1_5_B[49]
Vcc1_5_B[50]
Vcc1_5_B[51]
Vcc1_5_B[52]
Vcc1_5_B[53]

Vcc3_3[1]

VccDMIPLL

Vcc1_5_A[1]
Vcc1_5_A[2]
Vcc1_5_A[3]
Vcc1_5_A[4]
Vcc1_5_A[5]
Vcc1_5_A[6]
Vcc1_5_A[7]
Vcc1_5_A[8]
Vcc1_5_A[9]

VccSATAPLL

Vcc3_3[2]

Vcc1_5_A[10]
Vcc1_5_A[11]
Vcc1_5_A[12]
Vcc1_5_A[13]
Vcc1_5_A[14]
Vcc1_5_A[15]
Vcc1_5_A[16]
Vcc1_5_A[17]
Vcc1_5_A[18]

VccSus3_3[19]

VccUSBPLL

VccSus1_05/VccLAN1_05[1]
VccSus1_05/VccLAN1_05[2]

VccSus3_3/VccLAN3_3[1]
VccSus3_3/VccLAN3_3[2]
VccSus3_3/VccLAN3_3[3]
VccSus3_3/VccLAN3_3[4]

Vcc3_3 / VccHDA

VccSus3_3/VccSusHDA

V_CPU_IO[1]
V_CPU_IO[2]
V_CPU_IO[3]

VccSus3_3[1]

VccSus3_3[2]
VccSus3_3[3]
VccSus3_3[4]
VccSus3_3[5]
VccSus3_3[6]

VccSus3_3[7]
VccSus3_3[8]

VccSus3_3[9]
VccSus3_3[10]
VccSus3_3[11]
VccSus3_3[12]
VccSus3_3[13]
VccSus3_3[14]
VccSus3_3[15]
VccSus3_3[16]
VccSus3_3[17]
VccSus3_3[18]

Vcc1_5_A[19]

Vcc1_5_A[20]

Vcc1_5_A[21]

Vcc1_5_A[22]

Vcc1_5_A[23]

Vcc1_5_A[24]

Vcc1_5_A[25]

VccSus1_05[1]

VccSus1_05[2]
VccSus1_05[3]

Vcc1_5_A[26]

Vcc1_5_A[27]

Vcc1_5_A[28]

Vcc1_5_A[29]

Vcc1_5_A[30]

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Vcc1_05[1]
Vcc1_05[2]
Vcc1_05[3]
Vcc1_05[4]
Vcc1_05[5]
Vcc1_05[6]
Vcc1_05[7]
Vcc1_05[8]

Vcc1_05[9]
Vcc1_05[10]
Vcc1_05[11]
Vcc1_05[12]
Vcc1_05[13]
Vcc1_05[14]
Vcc1_05[15]
Vcc1_05[16]
Vcc1_05[17]
Vcc1_05[18]
Vcc1_05[19]
Vcc1_05[20]

Vcc3_3[3]
Vcc3_3[4]
Vcc3_3[5]
Vcc3_3[6]
Vcc3_3[7]
Vcc3_3[8]

Vcc3_3[9]
Vcc3_3[10]
Vcc3_3[11]

Vcc3_3[12]
Vcc3_3[13]
Vcc3_3[14]
Vcc3_3[15]
Vcc3_3[16]
Vcc3_3[17]
Vcc3_3[18]
Vcc3_3[19]
Vcc3_3[20]
Vcc3_3[21]

VccRTC

3

L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18

U6

R7

AE23
AE26
AH26

AA7
AB12
AB20
AC16
AD13
AD18
AG12
AG15
AG19

A5
B13
B16
B7
C10
D15
F9
G11
G12
G16

W5

P7

A24
C24
D19
D22
G19

K3
K4
K5
K6
L1
L2
L3
L6
L7
M6
M7
N7

AB17
AC17

T7
F17
G17

AB8
AC8

K7

C28
G20

A1
H6
H7
J6
J7

2008/11/17 2009/11/17

0.1U_04 02_16V4Z

1

C220

C219

2

1U_0402 _6.3V4Z

1

1

C233

C232

2

2

0.1U_04 02_16V4Z

1

C236

2

0.1U_04 02_16V4Z

1

C241

0.1U_04 02_16V4Z

2

1

C245

0.1U_04 02_16V4Z

2

+1.5VS

1 2

C252 0.1U_040 2_16V4Z

ICH_ K7

ICH_ C28
ICH_G 20

+1.5VS

1

C256

0.1U_04 02_16V4Z

2

Compal Secret Data

14mA

C229

0.1U_04 02_16V4Z

45mA

2

A4

A23

B1

B8
B11
B14
B17
B20
B26
B28

C2

C6
C27
D10
D13
D18
D21
D24

E1

E2

E4

E8

56mA

+3VS

1

C228

+1.05VS

0.1U_04 02_16V4Z

2

1

C230

2

2

1

1

C231

2

2

4.7U_08 05_10V4Z

0.1U_04 02_16V4Z

+RTCVCC

1

1

C243

C244

2

2

0.1U_04 02_16V4Z

0.1U_04 02_16V4Z

Title

Size Docum ent Number R ev

Cust om

Date: Sheet o f

E15

F3

F4

F5
F12
F27
F28

G1
G2
G5
G6

G9
G14
G18
G21
G24
G25
G26

H3
H4

H5
H24
H27
H28

J1
J2

J5
J24
J25
J26
K24
K27
K28
L13
L15
L24
L25
L26

M3
M4

M5
M12
M13
M14
M15
M16
M17
M24
M27
M28

N1
N2
N5

N6
N11
N12
N13
N14
N15
N16
N17
N18
N24
N25
N26

P3

P4
P12
P13
P14
P15
P16
P17
P24
P27

Compal Electronics, Inc.

ICH7M(4/4)POWER/GND

KAVAA LA-5121P M/B

U15E

VSS[0]
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]
VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]

ICH7_BGA652

1

P28

VSS[98]

R1

VSS[99]

R11

VSS[100]

R12

VSS[101]

R13

VSS[102]

R14

VSS[103]

R15

VSS[104]

R16

VSS[105]

R17

VSS[106]

R18

VSS[107]

T6

VSS[108]

T12

VSS[109]

T13

VSS[110]

T14

VSS[111]

T15

VSS[112]

T16

VSS[113]

T17

VSS[114]

U4

VSS[115]

U12

VSS[116]

U13

VSS[117]

U14

VSS[118]

U15

VSS[119]

U16

VSS[120]

U17

VSS[121]

U24

VSS[122]

U25

VSS[123]

U26

VSS[124]

V2

VSS[125]

V13

VSS[126]

V15

VSS[127]

V24

VSS[128]

V27

VSS[129]

V28

VSS[130]

W6

VSS[131]

W24

VSS[132]

W25

VSS[133]

W26

VSS[134]

Y3

VSS[135]

Y24

VSS[136]

Y27

VSS[137]

Y28

VSS[138]

AA1

VSS[139]

AA24

VSS[140]

AA25

VSS[141]

AA26

VSS[142]

AB4

VSS[143]

AB6

VSS[144]

AB11

VSS[145]

AB14

VSS[146]

AB16

VSS[147]

AB19

VSS[148]

AB21

VSS[149]

AB24

VSS[150]

AB27

VSS[151]

AB28

VSS[152]

AC2

VSS[153]

AC5

VSS[154]

AC9

VSS[155]

AC11

VSS[156]

AD1

VSS[157]

AD3

VSS[158]

AD4

VSS[159]

AD7

VSS[160]

AD8

VSS[161]

AD11

VSS[162]

AD15

VSS[163]

AD19

VSS[164]

AD23

VSS[165]

AE2

VSS[166]

AE4

VSS[167]

AE8

VSS[168]

AE11

VSS[169]

AE13

VSS[170]

AE18

VSS[171]

AE21

VSS[172]

AE24

VSS[173]

AE25

VSS[174]

AF2

VSS[175]

AF4

VSS[176]

AF8

VSS[177]

AF11

VSS[178]

AF27

VSS[179]

AF28

VSS[180]

AG1

VSS[181]

AG3

VSS[182]

AG7

VSS[183]

AG11

VSS[184]

AG14

VSS[185]

AG17

VSS[186]

AG20

VSS[187]

AG25

VSS[188]

AH1

VSS[189]

AH3

VSS[190]

AH7

VSS[191]

AH12

VSS[192]

AH23

VSS[193]

AH27

VSS[194]

18 42Tuesday, March 10, 200 9

1

1.0

A

B

C

D

E

Mini-Express Card for WLAN/WiMax

+3V_WLAN

120 m il

0.1U_0402_16V4Z

1

1

C259

C258

WLAN@

WLAN@

1 1

2 2

EC_TX_P80_DATA<26>
EC_RX_P80_CLK<26>

Debug card using

2

0.01U_0402_25V7K

WLAN_BT_DATA<21>
WLAN_BT_CLK<21>

WLAN _CLKREQ#<12>

CLK_P CIE_WLAN#<12>

CLK_P CIE_WLAN<12>

PCIE_PTX_C_IRX_N2<17>
PCIE_PTX_C_IRX_P2<17>

PCIE_ITX_C_PRX_N2<17>
PCIE_ITX_C_PRX_P2<17>

WLAN / Wi Fi

R425 0_0402_5%
R426 0_0402_5%

3/5 P VT: A dd R4 25, R426 wit h 0 ohm

C260

WLAN@

2

4.7U_0805_10V4Z

+3V_WLAN

1 2
1 2

1

2

WLAN_BT_DATA
WLAN_BT_CLK
WLAN _CLKREQ#

C479

47P_0402_50V8J

For W WAN re ques t Fo r WWA N reque st

11
13
15

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

53
54

C261

WLAN@

0.01U_0402_25V7K

JWLAN

1

1

3

3

5

5

7

7

9

9
11
13
15

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

GND
GND

P-TWO_A54402-A0G16-N

@

2/2 5 PVT :M ou nt C47 9,C4 80 w ith 47pf

+1.5VS

0.1U_0402_16V4Z

1

1

C262

WLAN@

2

2

2

4

4

6

6

8

8

10

10

12

12

14

14

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

40

42

42

44

44

46

46

48

48

50

50

52

52

1

C263

WLAN@

2

2

4.7U_0805_10V4Z

+3V_WLAN

+1.5VS

2/4 D VT: A dd PJ 20 ,PJ 21 for Echo Peak Iss ue

XMIT_OFF#
PLTRST#

C480

47P_0402_50V8J

2

2

LED_WIMAX#LED_WIMAX#

R229
100K_0402_5%

1 2

PJ20

JUMP_43X79@

PJ21

JUMP_43X79@

PLTRST# <6,1 5,17,24,28>

CLK_SMBCLK < 11,12>
CLK_SMBDATA <11,12>

USB20_N4 <17>
USB20_P4 <17>

+3VS

112

+3V_SB

112

LED_WIMAX# <29>

+3VS

Wi Ma x

Plea se p lace n eer to MIN I card con n.

USB20_N4
USB20_P4

USB20_P5

R378 0_0402_5%TSP4@

1 2

R379 0_0402_5%TSP4@

1 2

R380 0_0402_5%TSP5@

1 2

R381 0_0402_5%TSP5@

1 2

12/ 1 res er ve to uc h sc reen fun ction

Kill SWITCH

+3VS

2

SW1

G2
G1

3
2
1

1BS003-1210L_3P

@

3

DM1

5
4

3
2
1

DAN217_SC5 9

@

1

USB20_TS­USB20_TS+
USB20_TS-USB20_N5
USB20_TS+

2/3 D VT: A dd R4 11 w ith 0 oh m

Res er ve SW 1, RM1 ,U 17, C2 64 for del kil l sw itch func tion

RM1

@

1 2

100K_0402_5%

+3VS

KILL_SW# <26>

USB20_TS- <21>
USB20_TS+ <21>

WL_O FF#<26>

KILL_SW#

NC7SZ08P5X_NL_SC70-5

1 2

R411 0_0402_5%

+3VS

U17

5

2

P

B

1

A

G

3

C264 0.1U_0402_16V4Z

1 2

@

XMIT_OFF#

4

Y

@

Mini-Express Card for 3G/GPS

3G cu rre nt ne ed to 2750mA

+3VS

120 m il

0.1U_0402_16V4Z

1

1

C266

C265

3GGPS@

3GGPS@

2

0.01U_0402_25V7K

3 3

C267

3GGPS@

2

4.7U_0805_10V4Z

Reserve

WW AN_CLKREQ#<12>

CLK_P CIE_WWAN#<12>

CLK_P CIE_WWAN<12>

PCIE_PTX_C_IRX_N4<17>
PCIE_PTX_C_IRX_P4<17>

PCIE_ITX_C_PRX_N4<17>

PCIE_ITX_C_PRX_P4<17>

4 4

A

12/ 1 Cha ng e BOM C onf ig from GPS @ to 3GGP S@

1

C482

2

47P_0402_50V8J

For W WAN re ques t For W WAN re ques t

C268

3GGPS@

0.01U_0402_25V7K

2/2 5 PVT :M ou nt C48 2,C4 81 w ith 47pf

JGPS

1

1

3

3

5

WW AN_CLKREQ#

+3VS

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

53

GND

54

GND

P-TWO_A54402-A0G16-N

@

+1.5VS

10
12
14
16

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

1

2

120 m il

2
4
6
8

0.1U_0402_16V4Z

1

C269

3GGPS@

2

2
4
6
8
10
12
14
16

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

B

1

C270

3GGPS@

2

4.7U_0805_10V4Z

+3VS

+1.5VS

+UIM_PWR

C481

47P_0402_50V8J

UIM_DATA
UIM_CLK
UIM_RST
UIM_VPP

UWB _OFF#
PLTRST#

CLK_SMBCLK
CLK_SMBDATA

LED_WIMAX#

C271

+UIM_PWR

1

2

C

UIM_RST

12

UIM_CLK

D9
GLZ20A LL-34

3G@

10P_0402_50V8J

2008/11/17 2009/11/17

1

1

C272

C273
10P_0402_50V8J

2

2

3G@

3G@

Compal Secret Data

Deciphered Date

1

3

D10
DAN217_SC5 9

@

2

+UIM_PWR

+1.5VS
+UIM_PWR

USB20_N5 <17>
USB20_P5 <17>

0.1U_0402_16V4Z

UWB _OFF# <26>

3G@

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+UIM_PWR

12

R230

4.7K_0402_5%

E

@

UIM_DATA

1

C274
22P_0402_50V8J

2

@

19 42Tuesday, March 10, 2009

1.0

J3GSIM

1

VCC

2

RST

3

CLK

7

1

NC

MOLEX_47273-0001

D11
DAN217_SC5 9

@

2

3

D

4

GND

VPP

I/O

NC

@

DAN217 _SC59

Title

Size D ocument N umber Re v

Date: Sheet of

UIM_VPP

5
6

8

1

D12

@

2

3

+UIM_PWR

Compal Electronics, Inc.

WLAN/WiMAX Express Slot

KAVAA LA-5121P M/B

5

USB CONN--Right

D D

USB _EN#<26>

+5VALW +US B_VCCA

USB _EN#

U18

1

GND

2

IN

3

IN

4

EN#

G528_SO 8

1.4A

OUT
OUT
OUT

FLG

W=60mils

8
7
6
5

1

C283

@

4.7U _0805_10 V4Z

2

USB _OC#0_2 <17 ,26>

4

+US B_VCCA +US B_VCCA

C455

150 U_B_6.3VM_R 40M

+US B_VCCA

1

+

C464

2

D37

1

I/O1

2

REF1

I/O23I/O3

CM1293A -04SO_SOT23-6

@

3

2

W=60mils W=60mils

+US B_VCCA

C515

0.1U _0402_16 V4Z

1

C466

2

0.1U _0402_16 V4Z

1

C465

2

1000P_0 402_50V7K

USB 20_N0_ R
USB 20_P0_R

6

I/O4

5

REF2

4

1

2

JUS BA

1

VCC

2

D-

3

D+

4

GND

5

GND1

6

GND2

7

GND3

8

GND4

SUYIN_ 02017 3MR004 S512ZL

@

USB 20_N0_ RUSB 20_P0_R USB 20_N2_ RUSB 20_P2_R

150 U_B_6.3VM_R 40M

2/9 DV T:C han ge C45 5,C45 8 from 220u f to 1 50uf
2/6 DV T:M odi fy JUS BA,J USBB S ymbol for G ND pad
3/4 PV T:A dd C515 for E MI req uest

C458

@

1

+

2

470P_04 02_50V8J

1

2

1

2

CM1293A -04SO_SOT23-6

1

C467

2

1000P_0 402_50V7K

USB 20_N2_ R
USB 20_P2_R

D38

I/O1

I/O4

REF1

REF2

I/O23I/O3

@

1

JUS BB

1

VCC

2

D-

3

D+

4

GND

5

GND1

6

GND2

7

GND3

8

GND4

SUYIN_ 02017 3MR004 S512ZL

@

6

5

+5VALW+5VALW

4

2/3 DV T: Cha nge D3 8,D 37 fro m PRTR5V 0U2X_S OT143- 4 to CM1293 A-04SO _SOT23 -6

1 2

R386 0_ 0402_5%

L10

C C

USB 20_N0< 17>

USB 20_P0<17>

USB 20_P0 USB 20_P0_R

1

1

4

4

WCM-2 012-900T_0805 @

1 2

R388 0_ 0402_5%

For EMI request For EMI request

2

3

USB 20_N0_ RUSB 20_N0

2

3

USB 20_N2< 17>

USB 20_P2<17>

USB 20_N2

USB 20_P2 USB 20_P2_R

1 2

R387 0_ 0402_5%

L11

1

1

4

4

WCM-2 012-900T_0805 @

1 2

R389 0_ 0402_5%

USB 20_N2_ R

2

2

3

3

USB Board--Left

+US B_VCCB +U SB_VC CB

12

R232
75K_040 2_1%

USB20 _P7_S_O
USB 20_N7_S_O

B B

SLP _CHG_M3<1 7>

SLP _CHG_M4<1 7>

USB 20_P7_S

+US B_VCCB

A A

12

10
13

12

14

2

C29 3

0.1U _0402_ 16V4Z

1

R234
51K_040 2_1%

U20

1

1OE#

4

2OE#
3OE#
4OE#

2

1A

5

2A

9

3A
4A

VCC

SN7 4CBT3125PW RG4_TSSOP 14

SLP_CHG_M3

Mode 3

Mode 4

5

HIGH

LOW HIGH

12

R233
43K_040 2_1%

12

R235
51K_040 2_1%

USB 20_P7_S_O

3

1B

USB 20_N7_S_OUSB 20_N7_S

6

2B

R236 100_0 402_5%

8

1 2

11

7

GND

3B
4B

SLP_CHG_M4

LOW

USB 20_P7_S

USB 20_N7_S

USB 20_P7<17>

USB 20_N7< 17>

USB _CHG_ EN#<26>

USB 20_P7

USB 20_N7

+5VALW +US B_VCCB

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

U19

1

1D+

2

1D-

3

2D+

4

2D-

5

GND

TS3 USB221RS ER_QFN10_2X1 P5

LOW

HIGH

1
2
3
4

Issued Date

1.4A

U21

GND
IN
IN
EN#

G528_SO 8

ple ase cl ose to S B unde r 30mm

+3VALW

0.1U _0402_16 V4Z

C291

1 2

USB 20_P7_R

USB 20_N7_ R

SLP _CHG# <17>

3/4 PV T:A dd C516 for E MI req uest
2/9 DV T:C han ge C288 from 220uf to 15 0uf

VCC

OE#

10

9

S

8

D+

7

D-

6

FUNCTIONSLP_CHG

D=1D

D=2D

W=30mils

8

OUT

7

OUT

6

OUT

5

FLG

2008/11/17 2009/11/17

3

1

C292

4.7U _0805_10 V4Z

2

@

Compal Secret Data

2/3 DV T: Cha nge D1 5 f rom PR TR5 V0U2X_ SOT143 -4 to CM129 3A-04S O_SOT2 3-6

USB _OC#7 <17,26 >

Deciphered Date

150 U_B_6.3VM_R 40M

+US B_VCCB

+US B_VCCB

1

1

+

C516

C288

2

2

470P_04 02_50V8J

D15

1

I/O1

2

REF1

I/O23I/O3

CM1293A -04SO_SOT23-6

2

6

I/O4

5

REF2

4

@

USB 20_N7_ R

USB 20_P7_R USB 20_P7_R_S

W=30mils

0.1U _0402_16 V4Z

1

C289

2

+5VALW

USB 20_N7_ R_SUSB 20_P7_R_S

R390 0_ 0402_5%

1

4

WCM-2 012-900T_0805 @

R391 0_ 0402_5%

For EMI request

Title

Size Do cumen t Numb er R ev

Da te: Sheet o f

1

C290

2

1000P_0 402_50V7K

USB 20_N7_ R_S
USB 20_P7_R_S

2/6 DV T:M odi fy JUSB C Symb ol for GND pad

1 2

L12

1

4

1 2

2

3

Compal Electronics, Inc.

USB Conn

KAVAA LA-5121P M/B

2

3

JU SBC

1

VCC

2

D-

3

D+

4

GND

5

GND1

6

GND2

7

GND3

8

GND4

SUYIN_ 02017 3MR004 S512ZL

@

USB 20_N7_ R_S

20 42Tu esday, M arch 10 , 2009

1

1.0

A

B

C

D

E

F

G

H

SATA Conn.

Lid SW

For 1.8" SSD

+3VS+5VS

Place closely JHDD SATA CONN.

1.2A

1

C275

1 1

10U _0805_10V4 Z

2

2 2

ALL TO_C1667 4-12204-L_NR

26
25

24
23

JSATA

boss
boss

GND
GND

@

1

C276

0.1U _0402_16 V4Z

2

GND

RX+

RX-

GND

TX-

TX+

GND

3.3V

3.3V

3.3V
GND
GND
GND

5V
5V
5V

GND

Rsv

GND

12V
12V
12V

1
2
3
4
5
6
7

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

1

C277

0.1U _0402_16 V4Z

2

SATA_ITX_ C_DRX_P0
SATA_ITX_ C_DRX_N0

SATA_IRX_ DTX_N0
SATA_IRX_DTX_ P0

1

C278

0.1U _0402_16 V4Z

2

C284 0.01U _0402_25V7K

1 2

C285 0.01U _0402_25V7K

1 2

C286 0.01U _0402_25V7K

1 2

C287 0.01U _0402_25V7K

1 2

+3VS

+5VS

BlueTooth Interface

BT@

2

1

2

+3VS

G

R241

(MAX =200mA )

0.1U _0402_16 V4Z

+3VS

12

R23 7
100K_04 02_5%

BT@

47K_040 2_5%

3 3

4 4

BT_ OFF< 17>

1/2 2 D VT: Cha nge R238 from 10K to 47K
Add C499 with 0.01uF

BT@

BT_RST#<17 >

1 2

R240 10 0K_0402_5%

1 2

R238

BT_RESE T#

0.1U _0402_16 V4Z

C296

BT@

BT@

0.1U _0402_16V7 K

1 2

C294

1

C499

BT@

0.01 U_0402_25V 7K

2

USB 20_P6<17>
USB 20_N6< 17>

WL AN_BT_CLK<19>

BT_DET#<17 >

WLA N_BT_DATA<19 >

+3VS

+BT_VCC

C297

4.7U _0805_10 V4Z

BT@

SSD HD D n eed 40 0mA fo r 3V(P HISON)

1

C279

@

10U _0805_10V4 Z

2

S

D

Q16

BT@

1 3

AO3413_ SOT23

+BT _VCC

USB 20_P6
USB 20_N6

BT@

1 2

R239 0_ 0402_5%

1 2

@

4.7K_ 0402_5%

C298

BT@

1

C280

@

0.1U _0402_16 V4Z

2

SATA_ITX_ DRX_P0 <16>
SATA_ITX_ DRX_N0 <16>

SATA_IRX_ C_DTX_N0 <16 >

SATA_IRX_ C_DTX_P0 <16>

R242

BT@

4.7K_ 0402_5%

1 2

1

C281

@

0.1U _0402_16 V4Z

2

Bluetooth Connector

JBT

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

GND1

12

GND2

ACE S_87213-1000 G

@

1

C282

@

0.1U _0402_16 V4Z

2

Camera Conn.

Int. Camera

+5VS

JCA M

1

1

2

2

3

3

4

4

5

5

6

GND1

7

GND2

ACE S_88266-0500 1

@

Touch Screen Conn.

USB20_T S-<19>

USB20_T S+<19 > TS_STOP<2 6>

12/ 22 Add C8 72 and clo se to JBT f or EMI reque st

+3VALW

U22
APX9132 ATI-TRL_SOT23-3

VDD2VOUT

1

C300

0.1U _0402_16 V4Z

2

W=20mils

+CA M_VDD

1 2

C299

0.1U _0402_16 V4Z

CAM@

USB 20_N1_ R
USB 20_P1_R

1 2

R394 0_ 0402_5%
L14

1

1

4

4

WCM2 012F2S-900T04 _0805@

1 2

R395 0_ 0402_5%

For EMI request

GND

1

2

2

3

3

3

C301

10P_040 2_50V8J

CAM@

1 2

R392 0_ 0402_5%

L13

1

1

4

4

WCM2 012F2S-900T04 _0805@

1 2

R393 0_ 0402_5%

CAM@

For EMI request

1

2

USB 20_TS-_R
USB20_T S+_R

TS_RST<26>

LID_ SW# <26>

2

2

3

3

680P_04 02_50V7K

C470

1 2

@

USB 20_N1 <17>
USB 20_P1 <17>

+3VS

1
2
3
4
5
6

ACE S_87213-0600 G

JTS

1
2
3
4

7

5

G1

8

6

G2

@

WL AN_BT_CLK

A

C872 10P_0 402_50V8J@

1 2

B

C

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

2008/11/17 2009/11/17

Compal Secret Data

Deciphered Date

E

Title

Size Do cumen t Numb er R ev

Cu stom

F

Da te: Sheet o f

Compal Electronics, Inc.

SATA /BT/CMOS/TS/ Lid SW

KAVAA LA-5121P M/B

G

21 42Tu esday, M arch 10 , 2009

1.0

H

A

B

C

D

E

+AVDD

AVDD125AVDD2

+3VS_D VDD

38

1

9

DVDD

DVDD_IO

HPOUT_R

MONO_OU T

DMIC_CLK1 /2

DMIC_CLK3 /4

LINE2_VRE FO

LINE1_VRE FO

MIC1_VREF O

MIC2_VREF O

0.1U_04 02_16V4Z

0.1U_04 02_16V4Z

LOUT1_L

LOUT1_R

LOUT2_L

LOUT2_R

SPDIFO1

SPDIFO2

HPOUT_L

CPVEE

VREF

JDREF

CBN

CBP

AVSS1
AVSS2

10U_080 5_10V4Z

1

CA2

CA1

2

10U_080 5_10V4Z

1

CA8

CA7

2

35

36

39

41

48

45

33

1 2

RA5 63. 4_0402_1%

1 2

32

RA6 63. 4_0402_1%

37

46

44

20

18

10mil

28

10mil

19

31

AC_V REF

27

AC _JDREF

40

1 2

30

CA17 2.2U_06 03_6.3V6K

29

26
42

AGND

1

30mil

2

1

2

1/2 2 DV T: Lin k UA 2. 37 to U A3 .1 7 fo r m ono spea ker

+MIC1_ VREFO

+MIC2_ VREFO

1 2

CA16 2.2U_06 03_6.3V6K

RA10

1 2

20K_0402_1%

3/1 0 PV T: Cha ng e CA 18 fr om 10u F t o 0. 1uf

HD Audio Codec

CA5

40mil

0.1U_04 02_16V4Z

1

1

CA6

2

2

UA2

14

LINE2-L

15

LINE2-R

16

MIC2_L

17

MIC2_R

23

LINE1_L

24

LINE1_R

21

MIC1_L

22

MIC1_R

12

BEEP_IN

6

BITCLK

5

SDATA_O UT

8

SDATA_IN

11

RESET#

10

SYNC

2

GPIO0/DMIC_DA TA1/2

3

GPIO1/DMIC_DA TA3/4

13

SENSE A

34

SENSE B

47

EAPD

43

NC

4

DVSS

7

DVSS

ALC272-G R_LQFP48_7X7

need to re -link ALC272

+VDDA

1 1

RA3

0_0603_1%

Int. Mic

2/4 D VT :C han ge C A1 4 fro m 100p f t o 0. 1uf

2 2

CA34 10P_0 402_50V8J

3 3

1 2

CA42 100P_ 0402_25V8K

1 2

For E MI r equ est

Ext. Mic

HDA_ BITCLK<16>

HDA_ SDOUT<16>

HDA_ SDIN0<16>

HDA_R ST#<16>

HD A_SYN C<16>

EAPD<26>

1 2

RA31 22_0402_5%

HDA_ RST#

IF tes t OK, link direct

RA37 4.7K_0402_5%

10U_080 5_10V4Z

12

1

2

MIC2_L<23>

MIC2_ R<23>

CA4

MONO _IN

HDA_ SDIN0_ R

12

+3VS

1

2

0.1U_04 02_16V4Z

SENSE_A

SENSE_B

EAPD _R

DGND

CA3

10U_080 5_10V4Z

MIC1_C _L<23>

MIC1_ C_R<23>

1 2

CA14 0.1U_04 02_16V4Z

RA7 3 3_0402_5%

1 2

RA4 0_0402_5%

HDA_ BITCLK

12

2/2 5 PV T: Mou nt R A3 1 wit h 22 oh m,C A34 with 10 pf

RA1

0_0603_1%

HP_L <23>

HP_R <23>

AMP_SPK <23>

CA18

1

2

0.1U_04 02_16V4Z

12

CA19

+3VS

1

2

HP out

SPK out

2/1 1 DV T: mou nt R A1 3 w ith 0 o hm

Layout need to open channel

1 2

RA12 0_0603_5%@

1 2

RA13 0_0603_5%

1 2

0.1U_04 02_16V4Z

RA14 0_0603_5%@

DGND AGND

Audio regulator

2

CA9

@

1U_0402 _6.3V4Z

1

Beep sound

(output= 300mA)

UA1

1

VIN

2

GND

3

SHDN#

@

APL5151- 475BC-TRL_SOT23-5

2/5 D VT :R ese rv er U A1, CA9, CA1 1

EC Beep

BEEP#<26>

PCI Beep

SB_SPKR<17>

VOUT

RA8

1 2

47K_0402_5%

RA9

1 2

47K_0402_5%

10K_0402_5%

5

4

BP

0.22U_0 402_10V4Z

12

RA11

@

30mil

CA11

@

12

CA15

1 2

0.1U_04 02_16V4Z

1

CA20

0.1U_04 02_16V4Z

2

112

PJ19
JUMP_43X79

+VDD A+5VS

4.75V

2

CA10

@

1U_0402 _6.3V4Z

1

MONO _IN

2

+5VS

Sense Pin Impedance

39.2K

SENSE A

4 4

SENSE B

A

20K

10K

5.1K

39.2K

20K

10K

5.1K

Codec Signals

PORT-A (PIN 39, 41)

PORT-B (PIN 21, 22)

PORT-C (PIN 23, 24)

PORT-D (PIN 35, 36)

PORT-E (PIN 14, 15)

PORT-F (PIN 16, 17)

PORT-H (PIN 37)

PORT-I (PIN 32, 33)

Function

Ext. MIC

SPK out

Int. MIC

Headphone out

B

MIC_SEN SE<23>

NBA_PL UG<23>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

place close to chip

1 2

RA18 20K_0402_1%

1 2

RA16 5.1K_0402_1%

1 2

RA17 20K_0402_1%

MIC@

2008/11/17 2009/11/17

C

SENSE_A

SENSE_B

Compal Secret Data

Deciphered Date

Title

Size Doc ument Num ber R ev

Cust om

D

Dat e: Sheet of

Compal Electronics, Inc.

ALC272-GR Codec

KAVAA LA-5121P M/B

22 42Tuesd ay, March 1 0, 2009

E

1.0

A

B

C

D

E

Ext. Mic

RA21

1K_0402 _5%

12

12

12

12

2/3 DV T:C han ge DA3 fro m PJDL C05 t o PACD N042Y3 R
2/1 6 D VT: Mou nt DA3 w ith EM I requ est

1K_0402 _5%

RA22

RA2 5

MIC@

1K_0402 _5%

1K_0402 _5%

RA2 6

MIC@

12

12

12

12

1/1 3 D VT: Cha nge ne t na me fro m JLI NE to JEXMIC

CA4 0

100P_04 02_25V8K

@

MIC1_ L_R

MIC1_ L_L

3

2

CA21

CA22

MIC@

CA2 6

CA28

MIC@

TPA6017 Medium Range Amplifier

+5VS

CA2 3

NC

0.1U _0402_16 V4Z

1

1

CA2 4

2

2

2

3

18

14

4

8

12

Ke ep 10 mi l width

AMP _BYPASS

10

GAI N0 G AIN1 Av(db )

0

0 1

1

1 1

1

CA2 5

2

0.1U _0402_16 V4Z

SPKR+

SPK R-

2

CA3 3

0.47 U_0603_10 V7K

1

0

10

0

15.6

21.6

RA2 8

100K_04 02_5%

RA3 0

100K_04 02_5%

Rin (ohm)

6

90K

70K

45K

25K

@

10 d B

+5VS

12

12

12

12

RA2 7
100K_04 02_5%

RA2 9
100K_04 02_5%

@

1 1

2/6 D VT: C han ge R A38,RA 40 wit h 2K ohm
C han ge RA39,R A41 wi th 8. 2K ohm

CA2 9

1 2

0.03 3U_0402_16 V7K

CA3 0

AMP_SPK<2 2>

1 2

0.03 3U_0402_16 V7K

Use mon o SPK

set ting 68Hz

2 2

F=1 /2kRC -- > -3db

C=0 .03 3U, R=70K, F=68H z

3 3

Rin =70Kohm

1 2

RA3 8 2K_0402 _5%

1 2

RA3 9 8. 2K_0402_5%

1 2

RA4 0 2K_0402 _5%

1 2

RA4 1 8. 2K_0402_5%

CA3 1 0. 033U_040 2_16V7K

EC_MUTE #<26>

CA4 3

1 2

1U_ 0402_6.3V6K

CA4 4

1 2

1U_ 0402_6.3V6K

1 2

LIN E_C_O UTR

7

17

9

5

19

UA3

RIN+

RIN-

LIN+

LIN-

SHUTDOWN

GND5

20

21

10U _0805_10V4 Z

16

15

6

VDD

PVDD1

PVDD2

GAIN0

GAIN1

ROUT+

ROUT-

LOUT+

LOUT-

BYPASS

GND41GND311GND213GND1

TPA6017 A2_TSSOP20

MIC1_ C_L<22>

MIC 1_C_R<22>

Int. Mic

MIC2_ L<2 2>

MIC 2_R<2 2>

Ex.MIC JACK

2/3 DV T:C han ge DA7 fro m PJDL C05 t o PACD N042Y3 R

MIC 1_R

MIC1_ L

2/3 DV T:C han ge DA6 fro m PJDL C05 t o PACD N042Y3 R
2/1 6 D VT: Mou nt DA6 w ith EM I requ est
3/4 PV T:R ese rve DA6 with P ACDN04 2Y3R

4.7U _0805_10 V4Z

4.7U _0805_10 V4Z

1U_ 0402_6.3V 4Z

1U_ 0402_6.3V 4Z

MIC_S ENSE< 22>

1 2

LA7 0_0603_ 5%

1 2

LA8 0_0603_ 5%

DA6

1

PAC DN042Y3 R_SOT2 3-3@

CH7 51H-40 PT_SOD323-2

RA2 0

12

4.7K_ 0402_5%

RA2 3

12

4.7K_ 0402_5%
CH7 51H-40 PT_SOD323-2

1 2

CA27

220P_04 02_50V7K

MIC@

1

1

CA4 1
100P_04 02_25V8K

2

2

@

DA1

DA2

INT _MIC

3

PAC DN042Y 3R_SO T23-3

21

MIC1_ L

MIC 1_R

21

MIC@

12

RA244.7K _0402_5%

2

DA3

1

JEX MIC

5

4

3
6
2
1

FOX_JA6 033L-B3T4-7F_6 P-T

+MIC1 _VREFO

+MIC1 _VREFO

+MIC2 _VREFO

JM IC

1

1

2

2

3

GND

4

GND

ACE S_88231-0200 1

@

2/2 5 P VT: Cha nge JE XMIC,J LINE P CB fo otprin t

Head Phone JACK

Right Speaker Connector

DA5 PJ DLC05_ SOT23-3

1

SPKR+

LA5 0_060 3_5%

SPK R-

4 4

1 2

LA6 0_060 3_5%

1 2

3/4 PV T:M oun t D A5 wit h EMI reques t

A

3

2

SPK _R1
SPK _R2

JSP KR

1
2

3

1

NC1

4

2

NC2

ACE S_85204-02 00N

@

Security Classification

Compal Secret Data

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

HP _R<22>

HP_ L<22>

Deciphered Date

NBA _PLUG<22>

1 2

LA9 0_0603_ 5%

1 2

LA10 0_060 3_5%

1

PAC DN042Y3 R_SOT2 3-3

DA7

@

3

2

HP _R_R

HP_ L_R

2009/11/172008/11/17

D

2/3 DV T:C han ge DA7 fro m PJDL C05 t o PACD N042Y3 R

Title

Size Do cumen t Numb er R ev

Cu stom

Da te: Sheet o f

Compal Electronics, Inc.

AMP/VR/Audio Jack/MIC

KAVAA LA-5121P M/B

1/1 3 D VT: Cha nge ne t na me fro m JEX MIC to JLINE

AG ND

E

JL INE

5

4

3
6
2
1

FOX_JA6 033L-B3T4-7F_6 P-T

23 42Tu esday, M arch 10 , 2009

1.0

A

B

C

D

E

Clos e to Pin10,1 3,30,36

4 4

Place Close to Chip

1 2

PCIE_P TX_IRX_P3

PCIE_ PTX_IRX_N3

ISOLAT EB

LAN_X1
LAN_X2

CL9 0.1U_ 0402_16V7K

PCIE_ PTX_C_IRX_P3<1 7>

PCIE_ PTX_C_IRX_ N3<17>

LOM_W AKE#<26>

+3V_LAN

3 3

+3VS

12

RL5
1K_0402 _5%

ISOLAT EB

RL6
15K_040 2_5%

2 2

1 2

CL8 0.1U_ 0402_16V7K

1 2

PCIE_ ITX_C_PRX_P3<1 7>

PCIE_ ITX_C_PRX_ N3<17>

CLK _PCIE_ LAN<12>

CLK _PCIE_L AN#<1 2>

LAN _CLKREQ #<12>

PLTRST#<6 ,15,17 ,19,28>

RL3 2.49 K_0402_1%

RL4 100K _0402_5%

12

Plac e CL 20,CL21 clo sed to UL3

1 2

CL20 0.0 1U_0402_2 5V7K

1 2

CL21 0.0 1U_0402_2 5V7K

UL2

20

HSOP

21

HSON

15

HSIP

16

HSIN

17

REFCLK_P

18

REFCLK_M

25

CLKREQB

27

PERSTB

46

RSET

26

LANWAKEB

28

ISOLATEB

41

CKXTAL1

42

CKXTAL2

23

NC

24

NC

7

GND

14

GND

31

GND

47

GND

22

GNDTX

RTL 8103EL-GR_LQFP 48_7X7

1

CL17

27P_040 2_50V8J

LAN _MDI0+ RJ 45_MIDI0 +
LAN _MDI0-

LAN _MDI1+
LAN _MDI1- RJ4 5_MIDI1-

2

RTL8 103EL-GR

YL 1

12

25MHz_20pF_6X25000017

UL3

1

TD+
TD­CT
NC
NC
CT
RD+
RD-8RX-

8456E

TX+

RX+

TX-

CT
NC
NC
CT

2
3
4
5
6
7

LAN_X2LAN_X1

16
15
14
13
12
11
10
9

LED3/EEDO

LED2/EEDI/AUX

LED1/EESK

EECS

LED0

MDIP0

MDIN0

MDIP1

MDIN1

NC
NC
NC
NC

NC

VCTRL12A

VDDTX
DVDD12
DVDD12
DVDD12
DVDD12

NC

NC

VCTRL12D

VDD33
VDD33

AVDD33

NC
NC

1

CL18

27P_040 2_50V8J

2

RJ 45_MID I0-

CL26 100 0P_0402_50V8 -J

CL27 100 0P_0402_50V8 -J

RJ 45_MIDI1 +

LAN _DO

33

LA N_DI

34

LAN _SK_LA N_LINK#

35

LAN _CS

32

LA N_ACT IVITY#

38

LAN _MDI0+

2

LAN _MDI0-

3

LAN _MDI1+

5

LAN _MDI1-

6
8
9
11
12

4

VCT RL12

48

19
30
36
13
10

39

44
45

29
37

1
40
43

1 2
1 2

PAD

T16

1 2

RL1 3.6 K_0402_5%

1 2

RL2 1K_04 02_5%

+EV DD12
+LA N_VDD12

+LA N_VDD12

+3V_LAN

RL8

RL9

75_0402 _1%

75_0402 _1%

1 2
1 2

+3V_LAN

RJ 45_GN D

Clos e to Pin48 Clos e to Pin1,37,29

12/ 18 Del CL6 w ith 1 0U

Clos e to Pin 45

1

2

LA N_ACT IVITY#

68P_040 2_50V8J

LAN _SK_LA N_LINK#

68P_040 2_50V8J

2/6 DV T: Cha nge UL 3 f rom NS 681 680(SP 050003 N00) t o 845 6E(SP0 50005V 00)

1 1

2

CL15

0.1U _0402_16 V4Z

1

VCT RL12

2

CL7

0.1U _0402_16 V4Z

1

+LA N_VDD12

CL28

10U _0805_10V4 Z

CL19

CL22

RJ 45_GN D LA NGND

2

1

RL7 150_040 2_1%

1

+3V_LAN

2

RL10 15 0_0402_1%

1

+3V_LAN

2

1 2

CL23

2

CL2

0.1U _0402_16 V4Z

1

CL5

0.1U _0402_16 V4Z

12

RL11 15 0_0402_1%

RJ 45_MID I1-

RJ 45_MIDI1 +

RJ 45_MID I0-

RJ 45_MIDI0 +

12

RL12 15 0_0402_1%

1000P_1 808_3KV7K

2

CL10

0.1U _0402_16 V4Z

1

12

12

1

CL24

0.1U _0402_16 V4Z

2

2

1

12

11

8

7

6

5

4

3

2

1

10

9

+LA N_VDD12

2

1

2

CL11

0.1U _0402_16 V4Z

1

+EV DD12

CL4

0.1U _0402_16 V4Z

CL3

0.1U _0402_16 V4Z

Clos e to Pin19

2

CL13

1U_ 0402_6.3V 4Z

1

LAN Conn.

JL AN

Amber LED-

Amber LED+

PR4-

PR4+

PR2-

PR3-

PR3+

PR2+

PR1-

PR1+

Green LED-

Green LED+

FOX _JM36113-P222 1-7F

@

SHLD4

SHLD3

SHLD2

SHLD1

1

CL25

4.7U _0603_ 6.3V6K

2

+3V_LAN

2

CL12

0.1U _0402_16 V4Z

1

2

CL14

1U_ 0402_6.3V 4Z

1

16

15

14

13

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/11/17 2009/11/17

C

Compal Secret Data

Deciphered Date

Title

Size Do cumen t Numb er R ev

Cu stom

D

Da te: Sheet o f

Compal Electronics, Inc.

RTL8103EL 10/100 LAN

KAVAA LA-5121P M/B

Tuesday, March 10, 2009

E

1.0

24 42

5

CC1

0.1U_0402_16V4Z

+VCC_ 3IN1

+3VS_CR

RC2 0_0603_5%

+3VS

+3VALW

conf irm that whe ther can b e removed

D D

1 2

1 2

RC4 0_0603_5%@

+3VS_CR

RC8
100K_0402_5%

1 2

RC10 0_0402_5%

RST# RST#_R

1

CC8
1U_0402_6.3V4Z

2

1

2

+3VS_CR

12

2/2 5 PVT :M ou nt RC 21, CC 16 an d cl ose to U C2.4 8

MODE SEL

C C

CC13

0.1U_0402_16V4Z

@

12

1

RC16
0_0402_5%

2

+3VS

XTLI

12

RC13
220_0402_5%

21

DC1
HT-11 0UYG-CT_YEL/GRN

4

CC5

4.7U_06 03_6.3V6K

10_0402_5%

1 2

RC21

CC4 0.1U _0402_16V4Z

12

+3VS_CR

USB20_N3<17>
USB20_P3<17>

10P_0402_50V8J

CC16

RC14

6.19K_0402_1%

RST#_R
MODE SEL
XTLO
XTLI

CR_LED #

1 2

CC6 0 .1U_0402_16V4Z

1 2

UC2

1

AV_PLL

3

NC

7

NC

9

CARD_3V3

11

D3V3

33

D3V3

8

3V3_IN

44

RST#

45

MODE_SEL

47

XTLO

48

XTLI

4

DM

5

DP

14

GPIO0

2

RREF

12

DGND

32

DGND

6

AGND

46

AGND

RTS5159-GR_LQFP48_7X7
RC15
0_0402_5%

1 2

3

RC7 0_0402_5%

12

XD_CLE_SP19
XD_CE#_SP18
XD_ALE_SP17

SD_DAT2/XD_RE#_SP16

SD_DAT3/XD_WE#_SP 15

SD_DAT4/XD_WP#/MS_ D7_SP13

SD_DAT5/XD_D0/MS_D6_SP12

SD_CLK/XD_D1/MS_CLK_SP11

SD_DAT6/XD_D7/MS_D3_SP10

XD_RDY_SP14

SD_DAT7/XD_D2/MS_D2_SP8
SD_DAT0/XD_D6/MS_D0_SP7
SD_DAT1/XD_D3/MS_D1_SP6

MS_INS#_SP9

XD_D5_SP5

XD_D4/SD_DAT1_SP4

SD_CD#_SP3

SD_WP_SP2

XD_CD#_SP1

XTAL_CTR

VREG

MS_D4

EEDI

MS_D5

EEDO
EECS
EESK

SD_CMD

2

10
22

1

30

NC

43
42
41
40
39
38
37
35
34
31
29
28
27
26
25
23
21
20
19
18

13
24

15
16
17
36

CC7
1U_04 02_6.3V4Z

2

SD_DATA2
SD_DATA3

SD_MS_CLK

SD_MS_DATA0

SD_DATA1
SDCD #
SDWP#

XTAL_CTR

1 2

RC20 0 _0402_5%

SDCMD

RC11 33_0402_5%

1 2

+3VS_CR

XTAL_CTR

0
1

SDCLK

Description

Use 12MHz Crystal

Use 48MHz CLK Gen

1

2 in 1 Card Reader

CR_LED #

SD_DATA3

B B

RNCC

0

48Mhz

CLK_48M_CR<12>

1 2

RC19 0_0402_5%

XTLI

12Mhz

A A

CC9 6P_0402_50V8D@

CC12 6P_0402_50 V8D@

5

XTLI

12

YC1

@

12MHZ_16P_6X12000012

XTLO

NC

NC

NC

10K

10K

4

USB AUTO DE-LINK

47P

NC

680P

180P

680P

YES

YES

YES

MS FORMATTER

YES

YES

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

Description

Recommended

Compatible with RTS5158E

LED ON

LED ON

2008/11/17 2009/11/17

Compal Secret Data

Deciphered Date

+VCC_ 3IN1

2

1

CC10

2

1U_04 02_6.3V4Z

SDCMD

SDCLK

1

SD_MS_DATA0
SD_DATA1

CC11

2

SD_DATA2
SDWP#
SDCD #

0.1U_0402_16V4Z

10_0402_5%

SDCLK

1 2

RC18

@

Title

Size D ocument N umber Re v

Cus tom

Date: Sheet of

@

Compal Electronics, Inc.

RTS5159 Card Reader

KAVAA LA-5121P M/B

JCA RD

1

D3

2

CMD

3

VSS1

4

VDD

5

CLK

6

VSS2

7

D0

8

D1

9

D2

10

WP

11

CD

12

GND1

13

GND2

TAITW_PSDBTC09GLBS1N 14N0

10P_0402_50V8J

CC15

@

25 42Tuesday, March 10, 2009

1

1.0

0.1 U_0402_ 16V4Z

EC_ KBRST#<16 >

LPC _FRAME#<16,28>

CL K_PCI_L PC<1 2>

+3VALW

R303
47K_040 2_5%

C387 0. 1U_04 02_16V4Z

KS O[0..15 ]<28>

KS I[0..7 ]<28 >

ECR ST#

12

12

KS O[0..15 ]

KS I[0..7 ]

WL_ BT_LED#<29>

conf irm bat tery tea m c hang e +5VAL W to +3VALW

RP9

EC_ SMB_CK1

+3VALW

+5VS

For EC r eco mmend 10/17

BATT_TEMPA

A CIN_D

1 8
2 7
3 6
4 5

4.7K _0804_8P4 R_5%

EC_ SMB_CK2

R308 2.2 K_0402_5%

EC_ SMB_DA2

R309 2.2 K_0402_5%

1 2

C388 100P _0402_25V8K

1 2

C390 100P _0402_25V8K

KSO1

1 2

R312 47K_040 2_5%

KSO2

1 2

R313 47K_040 2_5%

EC_ SMB_DA1
TP_CLK
TP_DATA

+3VALW

+3VS

EC_TX_P 80_DATA<1 9>
EC_ RX_P80_CLK<1 9>

ON /OFFBT N#<2 9>

PW R_SUS P_LED#<29>

EC_ SMB_CK1<3 2>
EC_ SMB_DA1<3 2>
EC_ SMB_CK2<4 ,27>
EC_ SMB_DA2<4 ,27>

PM_SLP_ S3#<1 7>
PM_SLP_ S5#<1 7>
EC_ SMI#<1 7>

HD PINT<27>

FAN _SPEED1<28>

NUM _LED#<29>

1 2

to a void EC ent ry E NE test mode

1

C392

X1

2

15P _0402_50V8J

32.7 68KHZ _12.5P F_1TJS125BJ4 A421P

PCI_R ST#<15>

R314

20M_040 2_5%@

2

+3VALW

0.1 U_0402_ 16V4Z

0.1 U_0402_ 16V4Z

C37 8

C37 9

1

1

2

2

GATEA20<16>

SE RIRQ<1 7>

LPC _AD3<16,28>
LPC _AD2<16,28>
LPC _AD1<16,28>
LPC _AD0<16,28>

EC _SCI#<17>

CR Y2C RY1

4IN1

1

2

OUT

NC3NC

0.1 U_0402_ 16V4Z

C38 0

1

2

GATEA20
EC_ KBRST#
SE RIRQ
LPC _FRAME#
LPC _AD3
LPC _AD2
LPC _AD1
LPC _AD0

CL K_PCI_L PC
PCI_R ST#
ECR ST#
EC _SCI#
WL_ BT_LED#

KS I0
KS I1
KS I2
KS I3
KS I4
KS I5
KS I6
KS I7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15

EC_ SMB_CK1
EC_ SMB_DA1
EC_ SMB_CK2
EC_ SMB_DA2

PM_SLP_ S3#
PM_SLP_ S5#
EC_ SMI#

HD PINT

FAN _SPEED1

EC_TX_P 80_DATA

EC_ RX_P80_CLK
ON /OFFBT N#
PW R_SUS P_LED#
NUM _LED#

CR Y1
CR Y2

C393

15P _0402_50V8J

C38 1

1

2

10

12
13
37
20
38

55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82

77
78
79
80

14
15
16
17
18
19
25
28
29
30
31
32
34
36

122
123

1000P _0402_50V7K

1000P _0402_50V7K

1
2
3
4
5
7
8

6

C38 3

C38 2

U29

GA20/GPIO00
KBRST#/GPIO01
SERIRQ#
LFRAME#
LAD3
LAD2
LAD1
LAD0

PCICLK
PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D

KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25
KSO6/GPIO26
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49

SCL1/GPIO44
SDA1/GPIO45
SCL2/GPIO46
SDA2/GPIO47

PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A

XCLK1
XCLK0

KB9 26QFC0 _LQFP128

1

2

LPC & MISC

1

2

Int. K/B
Matrix

SM Bu s

9

PS 2 In terf ace

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+3VALW

22

33

VCC

VCC

PW M Ou tpu t

96

111

125

VCC

VCC

VCC

VCC

INVT_PWM/PWM1/GPIO0F

ACOFF/FANPWM2/GPIO13

BATT_TEMP/AD0/GPIO38

67

BATT_OVP/AD1/GPIO39

AD I nput

DAC_BRIG/DA0/GPIO3C

DA Out put

EN_DFAN1/DA1/GPIO3D

TP_CLK/PSCLK3/GPIO4E

TP_DATA/PSDAT3/GPIO4F

SP I Devic e Int erfac e

SP I Fla sh R OM

FSTCHG/SELIO#/GPIO50

BATT_CHGI_LED#/GPIO52

GP IO

BATT_LOW_LED#/GPIO54

VR_ON/XCLK32K/GPIO57

G PO

GP IO

GP I

GND

GND

GND

GND

GND

11

24

35

69

94

113

C384

1 2

0.1U _0402_16 V4Z

AVCC

BEEP#/PWM2/GPIO10

FANPWM1/GPIO12

ADP_I/AD2/GPIO3A

AD3/GPIO3B
AD4/GPIO42

SELIO2#/AD5/GPIO43

IREF/DA2/GPIO3E

DA3/GPIO3F

PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C
PSDAT2/GPIO4D

SDICS#/GPXOA00
SDICLK/GPXOA01

SDIDO/GPXOA02

SDIDI/GPXID0

SPIDI/RD#

SPIDO/WR#

SPICLK/GPIO58

SPICS#

CIR_RX/GPIO40

CIR_RLC_TX/GPIO41

CAPS_LED#/GPIO53

SUSP_LED#/GPIO55

SYSON/GPIO56

AC_IN/GPIO59

EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04

EC_ON/GPXO05

EC_SWI#/GPXO06

ICH_PWROK/GPXO06

BKOFF#/GPXO08

WL_OFF#/GPXO09

GPXO10
GPXO11

PM_SLP_S4#/GPXID1

ENBKL/GPXID2

GPXID3
GPXID4
GPXID5
GPXID6
GPXID7

V18R

AGND

2008/11/17 2009/11/17

INVT_P WM

21

BEEP#

23
26

AC OFF

27

BATT_TEMPA

63
64

AD P_I

65

ADP _V

66

KILL_ SW#

75

HD PACT

76

US B_CHG_ EN#

68

EN _DFAN 1

70

IR EF

71

CH GVAD J

72

EC_MUTE #

83

USB _EN#

84

TS_STOP

85

TS_RST

86

TP_CLK

87

TP_DATA

88

VGATE

97

WO L_EN#

98

SBP WR_EN#

99

LID_ SW#

109

EC_ SI_SPI_S O

119

EC_ SO_SPI_ SI

120

EC _SPICLK

126

SP I_CS#

128

USB _OC#0_2

73

USB _OC#7

74

FS TCHG

89

BAT T_FULL_LED#

90

CAP S_LED#

91

BAT T_CHG_LOW _LED#

92

PW R_ON_ LED#

93

SY SON

95

VR _ON

121

A CIN_D

127

EC_ RSMRST#

100

EC_ LID_OUT#

101

EC _ON

102

EC_ SWI#

103

EC_ PWROK

104

BKO FF#

105

WL _OFF#

106

UW B_OFF #

107

ARR OW_L ED#

108

PM_SLP_ S4#

110

ENB KL

112

EAP D

114

EC_ THERM#

115

SUS P#

116

PBTN_OU T#

117

LOM_W AKE#

118

+EC _V18R

124

20mi l

Compal Secret Data

Deciphered Date

INVT_P WM <13>
BEEP# <2 2>

AC OFF <33>

BATT_TEMPA <32>

HDP ACT <27>

USB _CHG_ EN# <20>
EN _DFAN 1 < 28>
IR EF <33>
CH GVADJ < 33>

EC_MUTE # <23>

USB _EN# <20>

TS_STOP <21>

TP_CLK < 29>

VGATE <1 2,17,37>
WO L_EN# <30>
SBP WR_EN # < 18,30>
LID_ SW# <21>

EC_ SO_SPI_ SI <28>

USB _OC#0_2 <17 ,20>

USB _OC#7 <17,20 >
FST CHG <33>

BAT T_FULL_LED# < 29>

CAP S_LED# <28>

BAT T_CHG_LOW _LED# <29>

PW R_ON_ LED# <29>

SY SON <30,35 >

VR _ON <37>

3/4 PV T:A dd net name to USB _OC#0_ 2

EC_ RSMRST# <17>
EC_ LID_OUT # <17>
EC _ON <29>
EC_ SWI# <29>
EC_ PWROK < 17>

BKO FF# <13>

UW B_OFF # < 19>
ARR OW_L ED# <29>

PM_SLP_ S4# <17>
ENB KL <8>
EAP D < 22>
EC_ THERM# <17>
SUS P# <30,33 ,35,36>
PBTN_OU T# <17>

LOM_W AKE# <24>

C391

4.7U _0603_ 6.3V6K

AD P_I <33>
ADP _V <33>
KILL_S W# <19>

TS_RST <21 >

TP_DATA <2 9>

EC_ SI_SPI_S O <28>

EC_ SPICLK <2 8>

SPI_ CS# <28>

WL _OFF# <19>

CL K_PCI_L PC

12

R30 2

@

10_0402 _5%

1

@

+3VALW

1 2

A CIN_D

C38 5

22P _0402_50V8J

+3VALW

R307330K_04 02_5%

2

R243

1 2

47K_040 2_5%

2 1

CH7 51H-40 PT_SOD323-2

LID_ SW#

D21

AC IN <17,29 ,31>

Add D21 for AC- IN l eakage i ssue

3/1 0 P VT: Add EC _SW I# for U SB sle ep&ch arge f unctio n

2/2 5 P VT: Cha nge ne t n ame fr om IC H_POK to EC_ PWROK

Title

Size Do cumen t Numb er R ev

Cu stom

Da te: Sheet o f

Compal Electronics, Inc.

KB926 D3

KAVAA LA-5121P M/B

26 42Tuesday, March 10, 2009

1.0

5

4

3

2

1

G-Sensor

DVT ph ase :us e S A00 003 5U0 0 (TIS35 5AL 3TR L GA)
PVT ph ase :us e S A00 003 990 0(TSH35TR LGA)

D D

+5VS +3V S_HDP

C4 97

1U_0 402_6 .3V4Z

C C

+3V S_HDP

B B

GSE NSOR @

2/6 Re serve C867 w ith 0. 22 fo r U33. 4 NC pin
2/6 Ch ange U 33 fro m APL 5151- 33BC t o G919 1-330T1U

HD PINT<26>

CH75 1H-4 0PT_S OD323-2

2

1

EC_ SMB_CK 2< 4,26>

R3 19 4.7K _0402 _5%

R3 20 4.7K _0402 _5%

R3 21 4.7K _0402 _5%

R3 22 4.7K _0402 _5%

HD PIN T

U3 3

1

IN

2

GND

SHDN#3BYP

G91 91-330T1U_ SOT23-5

GSE NSOR @

12

GSE NSOR @

12

GSE NSOR @

12

GSE NSOR @

12

GSE NSOR @

R3 23 1K_ 0402_5%

GSE NSOR @

0.1U _0402 _16V4Z

D2 3

GSE NSOR @

21

OUT

EC_ SMB_ CK2

SELF_T EST

12

1

C4 02

2

5

4

XOUT

XIN

+3V S_HDP

SELF_T EST

+3V S_HDP

12/18 Change P/N f rom SA 00003 0500 t o SA000035U00

2/11 D VT:Cha nge P/ N from SA00 0035U0 0 to S A000039900

C8 67

@

12

0.22 U_040 2_10V 4Z

U3 4

1

P3_5/SSCK/SCL/CMP1_2

2

P3_7/CNTR0#/SSO/TXD1

3

RESET#

4

XOUT/P4_7

5

VSS/AVSS

6

XIN/P4_6

7

VCC/AVCC

8

MODE

9

P4_5/INT0#/RXD1

10

P1_7/CNTR00/INT10#

1

2

R5F 211B4 D31SP LSSOP GSE NSOR @

C4 03

GSE NSOR @

0.1U _0402 _16V4Z

U3 1

2

@

C4 00
1U_0 402_6 .3V4Z

1

Vdd12Voutx

12

Vdd2

4

ST

6

PD

8

FS

9

Rev

TSH 35TR LGA

GSE NSOR @

Vouty
Voutz

NC1
NC2
NC3
NC4
NC5

GND1
GND2

VOUTX

3

V OUTY

5

VOU TZ

7

10
11
14
15
16

1
13

C3 98 0.1 U_040 2_16V 4Z@

C3 99 0.1 U_040 2_16V 4Z@

C3 97 0.1 U_040 2_16V 4Z@

12/24 Change U32.7 link to +3 VS_HDP

12/25 Del R3 98 wit h 0 oh m and U32.1 0 link to GND

P1_6/CLK0/SSI01

P1_5/RXD0/CNTR01/INT11#

P1_3/KI3#/AN11/TZOUT

P1_2/KI2#/AN10/CMP0_2

P1_1/KI1#/AN9/CMP0_1

P1_0/KI0#/AN8/CMP0_0

P3_3/TCIN/INT3#/SSI00/CMP1_0

P3_4/SCS#/SDA/CMP1_1

2/16 D VT pha se:Use SA000 037Y60

C3 94 0.0 33U_0 402_16V7K G SEN SOR@

1 2

C3 95 0.0 33U_0 402_16V7K G SEN SOR@

1 2

C3 96 0.0 33U_0 402_16V7K G SEN SOR@

1 2

VOUTX

2

12

V OUTY

3

12

VOU TZ

4

12

9

+3V S_HDP

SELF_T EST

7
10
13

MMA 7360LR2 _LGA14

Change U32.9 no co nnect

P1_4/TXD0

P4_2/VREF

11

12

13

14

15

16

17

18

19

20

VOU TZ

VOUTX

V OUTY

EC_ SMB_ DA2

12

R3 18
47K _0402_5%

GSE NSOR @

1

2

U3 2

XOUT

VDD

YOUT

NC

ZOUT

NC
NC

0G-DET

NC

NC
SLEEP#
G-SELECT

VSS

ST

@

HD PACT <26>

+3V S_HDP

C4 01

0.1U _0402 _16V4Z

GSE NSOR @

EC_ SMB_DA 2 <4,2 6>

+3V S_HDP

6

1
8
11
12
14

5

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/11/17 2009/11/17

Compal Secret Data

Deciphered Date

2

Title

Size Doc umen t Num ber Re v

Cu stom

Da te: Sheet of

Compal Electronics, Inc.

G-Sensor

KA VAA LA -51 21P M/B

1

27 4 2Tues day, Mar ch 1 0, 2009

1. 0

FAN Control Circuit

+5VS

1A

EN _DFAN1<2 6>

+FA N1

1

2

LPC Debug Port

Plea se p lace th e co nne ctor neer to DDR door

+3VS

CL K_PC I_DDR<12>

LPC _AD0<16,26>
LPC _AD1<16,26>
LPC _AD2<16,26>
LPC _AD3<16,26>

LPC _FRAME#<16,26>

PLTRST#<6 ,15,17, 19,24>

CL K_PC I_DDR

LPC _AD0
LPC _AD1
LPC _AD2
LPC _AD3
LPC _FRAME#

PLTRST#

U35

1

EN

2

VIN

3

VOUT

4

VSET

APL 5607KI-TRG_S O8

C40 9
10U _0805_10V4 Z

10U _0805_10V4 Z

GND
GND
GND
GND

JP4

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

GND

12

GND

ACE S_85201-10 05N

CL K_PC I_DDR

R341

22_0402 _5%

@

1 2
2

C438
22P_040 2_50V8J

1

@

SPI Flash (8Mb*1)

2/3 DVT: Ad d C5 01,C 502 ,C50 3,R412 for EM I request

+3VALW

U36

1

2

8
7
6
5

C40 7

12

D28
1SS 355_SOD323-2@

+FA N1

12

D29

@

BAS16_S OT23-3

2

C408

@

1000P_0 402_25V8J

1

@

R332 1 0K_0402_5%

2

C410

@

1

0.01 U_0402_16V 7K

JF AN

1

1

2

2

3

3

4

GND

5

GND

ACE S_85204-03 00N

12

+3VS

FAN _SPEED1 <26>

330P_04 02_50V7K

+3VALW

EC_ SI_SPI_S O<2 6>

C501

SPI_ CS#<26 >

1

2

3/2 PVT: Cha nge U36 to MX25 L8005M2C(SA00 000XT00)

2/25 PVT :Ch ange R41 2 w ith 33ohm ,C508 with 33pF

1

CE#

2

SO

3

WP#

4

VSS

MX25L8005M2 C-15G_SO8

KEYBOARD
CONN.

KS I[0..7 ]

KS O[0..15 ]

JKB

1
2
3
4
5
6

@

7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34

ACE S_88170-3400@

12/1 8 Fo llo w KB Mat rix the same to K SKAA

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/11/17 2009/11/17

KS I[0..7 ] <26>

KS O[0..15 ] < 26>

R382 300_0 402_5%

1 2

KS I1
KS I6
KS I5
KS I0
KS I4
KS I3
KS I2
KS I7
KSO15
KSO12
KSO11
KSO10
KSO9
KSO8
KSO13
KSO7
KSO6
KSO14
KSO5
KSO3
KSO4
KSO0
KSO1
KSO2

Compal Secret Data

Deciphered Date

CAP S_LED# <26>

+3VS

8

VDD

7

HOLD#

6

SCK

5

SI

C508

1 2

33P_040 2_50V8K

KS I0

KS I1

KS I2

KS I3

KS I4

KS I5

KS I6

KS I7

KSO0

KSO1

KSO2

KSO3

KSO4

KSO5

KSO6

KSO7

KSO8

KSO9

KSO10

KSO11

KSO12

KSO13

KSO14

KSO15

CAP S_LED#

3/4 PVT: Mou nt C 414~ C43 7,C4 61 for EMI request

Title

Size Do cumen t Numb er R ev

Da te: Sheet o f

330P_04 02_50V7K

1

C503

2

470P_04 02_50V8J

EC _SPICLK

EC_ SO_SPI_ SI

R412

1 2

33_0402 _5%

C414 100P_ 0402_50V8J

1 2

C419 100P_ 0402_50V8J

1 2

C416 100P_ 0402_50V8J

1 2

C418 100P_ 0402_50V8J

1 2

C422 100P_ 0402_50V8J

1 2

C424 100P_ 0402_50V8J

1 2

C426 100P_ 0402_50V8J

1 2

C428 100P_ 0402_50V8J

1 2

C430 100P_ 0402_50V8J

1 2

C432 100P_ 0402_50V8J

1 2

C434 100P_ 0402_50V8J

1 2

C436 100P_ 0402_50V8J

1 2

C415 100P_ 0402_50V8J

1 2

C420 100P_ 0402_50V8J

1 2

C417 100P_ 0402_50V8J

1 2

C421 100P_ 0402_50V8J

1 2

C423 100P_ 0402_50V8J

1 2

C425 100P_ 0402_50V8J

1 2

C427 100P_ 0402_50V8J

1 2

C429 100P_ 0402_50V8J

1 2

C431 100P_ 0402_50V8J

1 2

C433 100P_ 0402_50V8J

1 2

C435 100P_ 0402_50V8J

1 2

C437 100P_ 0402_50V8J

1 2

C461 100P_ 0402_50V8J

1 2

1

C502

2

EC _SPICLK

1

C411

0.1U _0402_16 V4Z

2

EC_ SPICLK <2 6>

EC_ SO_SPI_ SI <26>

SPI ROM//KB//FAN/Debug Poart

KAVAA LA-5121P M/B

Tuesday, March 10, 2009

1.0

28 42

A

Power Button

SW3

TOP sid e

1 1

BTM sid e

1

2

5

6

SW4

1

2

5

6

deb ug ph ase usi ng

3

4

SMT1-05_4P

3

4

SMT1-05_4P

ON/OFF BTN#_R

1

EC_ON<26>

D24

2

3

CHN20 2UPT SC-70

R327

10K_0402_5%

+3VALW

R324

100K_0402_5%

1 2

2

G

1 2

3/4 P VT: Ch an ge R4 13, R4 14 ,R4 15 fro m 0 ohm t o FB MA-1 0-10 0505 -151 T

PWR _ON_LED#
PWR _ON_LED
ON/OFF BTN#_R

R413 FBMA-10-100505-151T

1 2

R414 FBMA-10-100505-151T

1 2

R415 FBMA-10-100505-151T

1 2

1/1 3 DVT :C ha nge O N/O FFB TN# to ON/OF FBTN #_R

1

@

2

2 2

180P_0402_50V8J

LED Conn

DC-IN LED

Vf= 2. 0V( ty p), 2.4V (max )
If= 30 mA( max)

+3VALW

R370 220_0402_5%

1 2

D33

2 1

HT-11 0UYG-CT_YEL/GRN

BATT CHARGE/FULL LED

Vf= 1. 9V( ty p) ,2. 4V(m ax) for ambe r
Vf= 2. 0V( ty p) ,2. 4V(m ax) for gree n
If= 30 mA( max)

D34

3 3

+3VALW

1 2

R371 220_0402_5%

1

HT-21 0UD/UYG_AMB /GRN

POWER/SUSPEND LED

D35

+3VALW

+5VALW

1 2

R372 220_0402_5%

1 2

R375 300_0402_5%

1

HT-21 0UD/UYG_AMB /GRN

PWR _ON_LED

ARROW MODE LED

1 2

+3VS

4 4

R383 220_0402_5%

D40

2 1

HT-11 0UYG-CT_YEL/GRN

AC IN

2

G

1 3

D

S

Q27 2N 7002_SOT23

2

3

2

3

2/3 D VT: Ch an ge R3 75. 1 Ne t nam e fr om + 3VAL W to +5V ALW
2/3 D VT: Ch an ge R3 75 from 220 to 3 00 o hm

ARROW _LED# <26>

13

D

Q15

2N7002_SOT23

S

1

C506

C505

@

2

180P_0402_50V8J

ACIN <17,26,31>

PWR_SUSP_LED# <26>

PWR _ON_LED# <26>

B

ON/OFF BTN# <26>

51_ON# <31>

1
2
3
4

1

@

2

180P_0402_50V8J

BATT_CHG_LOW_LED# <26>

BATT_FULL_LED# <26>

E&T_6905-E04N-00R

C507

JPOWER

1
2
3
4

@

C

TP_SWR

180P_0402_50V8J

D27

1

PACD N042Y3R_SOT23-3

@

TP_SWL

180P_0402_50V8J

1

C404

2

2/3 D VT: Fo r E MI r eque st

C406

3

2

1

2

HDD LED

1 2

+3VS

R374 220_0402_5%

WiMAX&3G LED

Vf= 2. 8V( ty p), 3.15 V(ma x)
If= 20 mA( max)

1 2

+5VS

R336 300_0402_5%

WIMAX@

WL&BT LED

+3VS

R333 220_0402_5%

Ri ght Swit ch

SW2
SMT1-05_4P

1

2

5

6

Lef t s witc h

SW5
SMT1-05_4P

1

2

5

6

+3VS

D36

2 1

HT-11 0UYG-CT_YEL/GRN

D31

2 1

HT-11 0NB5 1204 BLUE

WIMAX@

Vf= 1. 9V( ty p), 2.4V (max )
If= 20 mA( max)

1 2

WLAN@

D

3

4

+5VS

1U_0402_6.3V4Z

3

4

R373

12

10K_0402_5%

WIMAX_LED_GND

HT-110UD_1204_AMBER

5

3

Q10B 2N7002DW -T/R7_SOT363-6

WIMAX_LED_GND

+5VS

10K_0402_5%

WIMAX@

D30

12

WLAN@

Touch/B Connector

1/2 2 DVT :J TO UCH p in d efin e re versa l

TP_CLK<26>

2

C405

TP_DATA<26>

1

D26

1

PJDLC05_SOT23-3

@

TP_SWL
TP_SWR

3

2

ISPD

ZZ Z

PCB

PCB L A-5121P DAZ BOM

U1

CPU

CPU N 280

N8@

SATALED#

2

2N7002DW-T/R7_SOT363-6

6 1

Q10A

4

R334

1 2

0_0402_5%

2

@

R335

Q5B 2N7002DW -T/R7_SOT363-6

Q5A 2N7002DW-T/R7_SOT363-6

12

6 1

5

3

WIMAX@

4

WIMAX@

WL_BT_LED# <26>

SATALED# <16>

LED_WIMAX# <19>

DC-IN

E

JTOUC H

8

GND

7

GND

6

6

5

5

4

4

3

3

2

2

1

1

ACES_85201-06051

@

PJP1

PJP1

45@

NUMERIC MODE LED

D41

+3VS

R384 220_0402_5%

1 2

A

2 1

HT-11 0UYG-CT_YEL/GRN

NUM_LED# <26>

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/11/17 2009/11/17

C

Compal Secret Data

Deciphered Date

Title

Size D ocument Number Re v

Cus tom

D

Date: Sheet of

Compal Electronics, Inc.

ON/OFF /TP Conn/LEDS

KAVAA LA-5121P M/B

29 42Tuesday, March 10, 2 009

E

1.0

A

B

C

D

E

+5VALW TO +5VS+3VALW TO +3VS

+3VALW +3V S

Q18

1 1

8
7
6
5

SI48 00BDY_S O8

1

C446

2

4.7 U_0805_ 10V4Z

D
D
D
D

C439

1

S

2

S

3

S

4

G

1

C447

2

0.0 22U_0402_1 6V7K

2/2 5 P VT: Cha nge C447 with 0 .022uF

Vgs =-0 V,I d=9A ,Rds= 18.5mo hm

1

1U_ 0402_6.3V 4Z

2

12

R348

330K_04 02_5%

Q6A

1

C440

4.7U _0805_10 V4Z

2

R344

1 2

47K_040 2_5%

61

2

2N7 002DW -T/R7_SOT363-6
2N7 002DW -T/R7_SOT363-6

R342

470_0 805_5%

+VSB

SUS P SUS P

1 2
3

Q6B

5

4

+3VALW TO +3V_LAN

+3VALW +3VALW

2 2

WO L_EN#<26>

1/2 2 D VT: Ch ang e R3 55 fro m 3.3K to 4 7K

Add C5 00 with 0 .01uf

R353
100K_04 02_5%

STAR@

1 2

STAR@

1 2

R355 47K _0402_5%

1

C451

STAR@

0.1U _0402_16V7 K

2

AO3413_ SOT23

STAR@

1 2

C500 0. 01U_0402 _25V7K

STAR@

4.7U _0805_10 V4Z

Q21

+5VALW

Q19

8

D

7

D

6

D

5

D

SI48 00BDY_S O8

1

C448

2

4.7 U_0805_ 10V4Z

Vgs =-4 .5V ,Id= 3A,Rd s<97mo hm

2

S

PJ17

2

C452

G

@

2

JUMP_43 X79

@

1

D

1 3

1

1

2

1

C453 1 U_0402 _6.3V4Z

2

+5VS

1

C441

1

S

2

S

3

S

4

G

1

2

0.0 1U_0402_25 V7K

2/2 5 P VT: Res erv e R349 with 200Koh m

+3V_LAN

STAR@

1U_ 0402_6.3V 4Z

2

12

C449

R349
200K_04 02_5%

@

Cha nge R3 46 wi th 47 Kohm

C442

R346

1 2

47K_040 2_5%

61

Q7A

2

2N7 002DW -T/R7_SOT363-6
2N7 002DW -T/R7_SOT363-6

SUS P<36>

SUS P#<2 6,33,35,36 >

1

4.7U _0805_10 V4Z

2

+VSB

R401

10K_040 2_5%

SUS P

R343

470_0 805_5%

1 2
3

Q7B

5

4

+5VALW

2

G

Q28 2N7002_SO T23

1 2

R361
100K_04 02_5%

1 2

13

D

S

SBP WR_EN#<18,26>

+3VALW TO +3V_SB

+3VALW

4.7U _0603_ 6.3V6K

1

C444

STAR@

2

+VSB

R347 47K_0402_5%

STAR@

2N7 002DW -T/R7_SOT363-6

12

5

STAR@

SY SON<2 6,35>

Vgs =10 V,I d=6A, Rds=3 5mohm

PJ18

2

112

JUMP_43 X79@

Q20

D

6

S

G

3

R350

STAR@

120K_04 02_5%

Q8B

SYS ON#

SY SON

R402

45

4.7U _0603_ 6.3V6K

1 2

2
1

STAR@

SI345 6BDV-T1-E3_T SOP6

3

4

10K_040 2_5%

+3V_SB

1

C445

STAR@

C443

1U_ 0402_6.3V 4Z

@

2

1

C450

0.1U _0402_25V6

STAR@

2

+5VALW

R362
100K_04 02_5%

1 2

13

D

2

G

Q29 2N7002_SO T23

S

1

R345

STAR@

2

470_080 5_5%

1 2
61

Q8A

2

2N7 002DW -T/R7_SOT363-6

STAR@

SBP WR_EN#SBP WR_EN#

Screw Hole

+1.5VS

3 3

R363
470_060 3_5%

@

1 2

13

D

S

SUS P

2

G

Q30
2N7002_ SOT23

@

2/6 DV T: Res erv e + 1.5 VS, +1. 05VS, +0.9VS ,+1.8V S disc harge circu it

R366
470_060 3_5%

@

4 4

1 2

13

D

SUS P SYS ON#

2

G

Q25

S

2N7002_ SOT23

@

A

+2.5VS +1.0 5VS

R364
470_060 3_5%

1 2

13

D

SUS P S USP

2

G

Q23

S

2N7002_ SOT23

+1.8V+0.9 VS

R367
470_060 3_5%

@

1 2

13

D

2

G

Q26

S

2N7002_ SOT23

@

R365
470_060 3_5%

@

1 2

13

D

S

2

G

Q24
2N7002_ SOT23

@

B

M/B

H1

H2

@

1

H_3 P0

1

@

H_3 P0

H3

@

1

H_3 P0

H4

1

@

H_3 P0

H5

@

1

H_3 P0

GNDA

H6

H7

@

1

H_3 P0

1

@

H_3 P0

H8

@

1

H_3 P0

JUMP_43 X79

FAN

H9

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

@

H_1 P2

H10

H17

@

1

H_1 P2

2008/11/17 2009/11/17

C

@

1

H_1 P2

Compal Secret Data

Deciphered Date

MINI Card
Full card

H11

1

KB

H15

1

1

PJ22

1

@

2

2

@

H_3 P3

@

H_3 P0N

H12

1

@

H_3 P3

12

H13

1

H16

1

R422
0_0402_ 5%

@

@

H_3 P3

@

H_3 P0

H14

1

@

H_3 P3

Half card

H20

1/1 3 D VT: Add H2 0,H21 for ha lf car d

+3VS +3VS +3VS +3VS

2

1

0.1 U_0402_ 16V4Z

3/4 PV T:F or ESD t eam re quest

3/5 PV T:F or EM I req uest

H18

@

1

H_2 P6N

3/2 PV T:C han ge H18 from H_3P0N to H _2P6N
3/2 PV T:C han ge H19 fr om H_6 P0X3P 0N to H_6P0X 2P6N

H19

@

1

H_6P 0X2P 6N

D

FIDUCIAL_C40M80

Title

Size Do cumen t Numb er R ev

Cu stom

Da te: Sheet o f

H21

@

@

1

1

H_3 P3

H_3 P3

2

2

2

C51 7

1

0.1 U_0402_ 16V4Z

FM1

@

1

FM2

C51 9

C51 8

0.1 U_0402_ 16V4Z

@

1

1

1

0.1 U_0402_ 16V4Z

FM3

@

1

Compal Electronics, Inc.

DC INTERFACE

KAVAA LA-5121P M/B

E

FM4

C52 0

@

1

1.0

30 42Tu esday, M arch 10 , 2009

A

B

C

D

PD1

VS

12

PR3

5.6K_ 0402_5%

12

PR4
10K_0 402_1%

1 2

PAC IN

12

PR7
10K_0 402_1%

AC IN <17,26,29>

PAC IN <33>

Vin Detector

High 18.384 17.901 17.430
Low 17.728 17.257 16.976

PL1

12

100P_ 0402_50V8J

68_12 06_5%

2

PR17
200_0 603_5%

PC10

SMB3 025500YA_2P

1 2

PC2

VI N

PD2
RLS41 48_LL34-2

1 2

12

PR9

13

12

PC8

0.1U_ 0603_25V7K

12

PR10
68_12 06_5%

12

PC3
1000P _0402_50V7K

RTC Battery

SP093MX0000

DC301001M80

PJP1

1

+

SINGA _2DW -0005-B03@

PR21

560_0 603_5%

1 2

2

-

51_ON #<29>

1 1

2 2

+CH GRTC

BATT+

CH GRTCP

PR22
560_0 603_5%

1 2

DC_ IN_S1

RLS41 48_LL34-2

200_0 603_5%

RTC VREF

PF1

5A_24 VDC_4290 07.WRML

12

PD3

PR11

1 2

12

PR13

100K_ 0402_1%

1 2

PR15

22K_0 402_1%

3.3V

3

12

PC9
10U_0 805_10V4Z

DC_ IN_S2

21

12

PC1
1000P _0402_50V7K

TP0610K-T1-E3_SOT23- 3

N1

12

PC7

0.22U _1206_25V7K

PU2 G92 0AT24U_SOT89-3

OUT

GND

N2

2

IN

1

PQ1

12

12

1U_08 05_25V4Z

VI N

12

PC4
100P_ 0402_50V8J

PC5

0.068 U_0402_10V6K

VS

PBJ1

MAXEL_ML1220T10@

+-

12

+RTCBATT

+RTCBATT

VI N

12

PR2

84.5K _0402_1%

PR5

22K_0 402_1%

1 2

12

12

PR6
20K_0 402_1%

12

PC6
.1U_0 402_16V7K

PR1

1M_0402_1%

1 2

VS

8

3

+

2

-

4

PR8

10K_0 402_1%

5

+

6

-

PU1A

P

1

O

G

LM393 DG_SO8

12

RTC VREF

3.3V

8

PU1B

P

7

O

G

LM393 DG_SO8

4

GLZ4. 3B_LL34-2

3 3

+3VALWP

(5A,200mils ,Via NO.= 10)

PJ1

2

112

JUMP_43X118@

+3VALW +1.8V+1.8VP

(5A,200mils ,Via NO.= 10)

PJ2

2

112

JUMP_43X118@

(OCP min=6.44A) (OCP min=6.07A)

PJ3

+5VALWP

(120mA,40mils ,Via NO.= 1)

4 4

+0.9VS P +0.9VS

2

112

(5A,200mils ,Via NO.= 10)

JUMP_43X118@

(OCP min=6.53A)

PJ5

2

112

JUM P_43X39@

PJ7

2

112

(2A,80mils ,Via NO.= 4)

JUMP_43X79@

A

+5VALW +1.05VSP

+VSB+VSBP

(6A,240mils ,Via NO.=12)

(OCP min=7.55A)

+1.5VSP +1.5VS

(3A,120mils ,Via NO.=6)

+2.5VS P +2.5VS

(100mA,40mils ,Via NO.= 2)

PJ4

2

112

JUMP_43X118@

PJ6

2

112

JUMP_43X79@

PJ8

2

112

JUMP_43X39@

+1.05VS

B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/11/17 2009/11/17

Compal Secret Data

Deciphered Date

C

Title

Size Do cumen t Numb er R ev

Dat e: S heet o f

Compal Electronics, Inc.

DCIN&DECTOR

KAVAA LA-5121P M/B

D

31 42Tuesday, March 10, 200 9

1.0

A

B

C

D

PH1 under CPU botten side :

CPU thermal protection at 92 degree C
Recovery at 56 degree C

+3VALWP

+3VALWP

BATT_TEMPA < 26>

EC_SM B_DA1 <26>

EC_SM B_CK1 <26>

VMB

SMB3 025500YA_2P

12

PC14
1000P _0402_50V7K

PL2

1 2

BATT+

12

PC15

0.01U _0402_25V7K

VL

12

100K_ 0603_1%_ TH11-4H104FT

PH1

0.1U_ 0603_25V7K

PR32

13.7K _0402_1%

1 2

12

PC17

0.22U_ 0805_16V7K

12

PR37

15.4K_ 0402_1%

PH2 near main Battery CONN :

PC16

TM_REF1

12

PC18

1000P _0402_50V7K

PF2

PJP2

1 1

9

8

SUY IN_250005 MR007G1 63ZR

@

2 2

1

1

2

2

3

3

4

4

5

5

9

6

6

7

7

8

BATT_S1

BATT_P3
BATT_P4
BATT_P5
EC_SM DA

EC_SM CA

PR34

100_0 402_1%

7A_24 VDC_4290 07.WRML

PR35
100_0 402_1%

1 2

1 2

21

12

PR39
1K_04 02_1%

1 2

12

PR33
1K_04 02_1%

PR28

1K_04 02_1%

6.49K _0402_1%

1 2

PR29
47K_0 402_1%

<BOM Structure>

PR36

12

12

12

PR40
100K_ 0402_1%

VL

47K_0 402_1%

1 2

8

PU3A

3

P

+

2

-

G

LM393 DG_SO8

4

PR38

100K_ 0402_1%

PR31

O

12

VL

PR30
47K_0 402_1%

1 2

2

1

VL

PD6

RLS41 48_LL34-2

12

13

PQ4
DTC11 5EUA_SC 70-3

MAINP WON <34>

BAT. thermal protection at 90 degree C
Recovery at 53 degree C

VLVL

PQ5

TP0610K-T1-E3_SOT23- 3

B+

3 3

100K_ 0402_1%

POK<34>

4 4

VL

PR47

PR48

1 2

0_0402_5%

1 2

12

PC22

A

2

G

.1U_04 02_16V7K@

PR45

22K_0 402_1%

1 2

13

D

PQ6
SSM3 K7002FU_SC 70-3

S

12

12

PR43

PC19

100K_ 0402_1%

0.22U_ 1206_25V7K@

13

2

B

+VSBP

12

PC20

0.1U_0 603_25V7K@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

100K_ 0603_1%_ TH11-4H104FT

PC21

0.22U _0805_16V7K

2008/11/17 2009/11/17

12

PH2

13.7K _0402_1%

1 2

12

12

PR46

16.9K _0402_1%

Compal Secret Data

Deciphered Date

C

PR44

TM_REF1

47K_0 402_1%

1 2

5

+

6

-

PR41

PR42

8

P

G

4

47K_0 402_1%

1 2

PU3B

7

O

LM393 DG_SO8

Title

Size Do cumen t Numb er R ev

Dat e: S heet o f

12

PD7

RLS41 48_LL34-2

Compal Electronics, Inc.

BATTERY CONN/OTP

KAVAA LA-5121P M/B

D

32 42Tuesday, March 10, 200 9

1.0

A

B

C

D

B+

PQ7

1
2
3 6

12

PR50
200K_ 0402_1%

12

PR58
150K_ 0402_1%

13

D

PQ17
SSM3 K7002FU_SC 70-3

S

IREF<26>

P2003 EVG_SO8

4

PC26

5600P _0402_25V7K

FSTCHG< 26>

0.01U _0402_25V7K

PR68

309K_ 0402_1%

PR71

100K_ 0402_1%

CS ON

ADP _I<26>

12

PC42

1SS35 5_SOD323-2

.1U_0 402_16V7K

PC37 100P_0 402_50V8J@

12

0.01U_ 0402_25V7K

P3

P3

100K_ 0402_1%

1 2

10K_0 402_1%

1 2

PC29

680P_ 0402_50V7K

PC34 68 00P_0402_25V7K

PR63 6. 81K_0402_1%

1 2

6251 VREF

8
7

5

1 2

PC35

1 2

12

CHGVADJ<26>

PR52

PD12

PR56

12

PC30

@

1 2

1 2

1 2

1 2

PC38
.1U_0 402_16V7K

24.9K _0402_1%

1 2

20K_0 402_1%

PR49 0.05_1 206_1%

1

2

PQ10 TP0 610K-T1-E3_SOT23-3

12

6251 VDD

12

PR59

PR65 100_0402_1%

1 2

PR70

12

PR72

PR74

15.4K _0402_1%

1 2

PR75

31.6K _0402_1%

4

3

2

PC28

2.2U_0 603_6.3V 6K

100K_ 0402_1%

6251_ EN CS ON

6251 VREF

6251 aclim

12

VIN

1 1

DTA14 4EUA_SC70-3

12

PR51

47K_0 402_1%

2

13

D

2

PQ13

G

S

SSM3 K7002FU_SC 70-3

2 2

PAC IN<31>

ACO FF<26>

3 3

PD9

B340A_SMA2

PQ9

2

13

PQ12

PR67

22K_0 402_1%

PAC IN

1 2

DTC11 5EUA_SC 70-3

PQ19

ACO FF

12

1 3

DTC11 5EUA_SC 70-3

2

P2

12

PC27

0.1U_ 0603_25V7K

2

G

13

Iad a=0~1 .579A( 30W) CP= 9 2%*Iada; C P=1.45 26A

100K_ 0402_1%

12

D CIN

13

PR54

1

2

3

4

5

6

7

8

9

10

11

12

B+

13

12

PU5

DCIN

ACPRN

CSON

CSOP

CSIN

CSIP

PHASE

UGATE

BOOT

VDDP

LGATE

PGND

24

23

22

21

20

19

18

17

16

15

14

13

VDD

ACSET

EN

CELLS

ICOMP

VCOMP

ICM

VREF

CHLIM

ACLIM

VADJ

GND

ISL625 1AHAZ-T_Q SOP24

PJ9

2

JUMP_43X118@

PQ11
DTC11 5EUA_SC 70-3

PD10

1

2

RB715 F_SOT323-3

PC31

0.1U_ 0603_25V7K

D CIN

PC32

0.047 U_0603_16V7K

1 2

1 2

PR61

20_06 03_5%

PC36

0.1U_ 0603_25V7K

1 2

LX_CHG

DH_ CHG

PR69

2.2_0 603_5%

BST_C HG

1 2

6251V DDP

DL_ CHG

1 2

112

CSI P

FST CHG

2

3

12

PR60

20_06 03_5%

1 2

PR62

20_06 03_5%

1 2

PR64

2.2_0 603_5%

0.1U_ 0603_25V7K

BST_C HGA

12

PD14
RB751 V-40TE17_SOD323 -2

1 2

PR73

4.7_0 603_5%

PC43

4.7U_ 0805_6.3V 6K

CS IN

12

12

PC24

PC23

4.7U_1 206_25V6K

4.7U_1 206_25V6K

SUSP# <26,30, 35,36>

CSOP

12

PC39

12

6251 VDD

12

PC124

2200P _0402_50V7K

PQ18
AO4466_ SO8

PC131

CHG_ B+

12

0.1U_0 402_25V6

578

3 6

578

3 6

241

241

PR55

10K_0 402_1%

PQ15

DTC11 5EUA_SC 70-3

PQ16
AO4466_ SO8

PL3

10UH_ MPL73-100_3A _20%

1 2

12

PR19

4.7_12 06_5%

12

PC13

680P_ 0603_50V8J

PQ8
P2003 EVG_SO8

1
2
3 6

4

PR53

1 2

47K_0 402_1%

1 2

1 2

13

1SS35 5_SOD323-2

PD13

1 2

2

1SS35 5_SOD323-2

PC33

0.1U_ 0603_25V7K

C HG

1

2

8
7

5

VIN

PD11

200K_ 0402_1%

12

PR66

0.02_ 2512_1%

ACO FF

PR57

1 2

13

D

PQ14

S

SSM3 K7002FU_SC 70-3

4

3

VI N

PAC IN

2

G

BATT+

12

PC40

12

PC41

10U_1 206_25V6M

10U_1 206_25V6M

CP mo de

Va cli m= 2. 39 *( 20 K/ /1 52K /(2 4.9 K//1 52K +20 K// 152 K))= 1.0 817 V

Ii npu t= (1 /0 .0 5) ((0 .05 *Vac lm) /2. 39+ 0.05 )
wh ere V ac lm = 1.08 17V , I inp ut= 1.45 26A

CC=0.25A~2A

IREF=1.636*Icharge

IREF=0.409V~3.272V

VCHLIM need over 95mV

CELL S

4 4

VDD

CELL number 4

CHGVAD J=(Vcell-4)/0.10627

Vcell

4V

4.2V

4.35V

GND Float

3

2

-

A

CHGVADJ

0V

1.2V

3.3V

PD15

@

GLZ4. 3B_LL34-2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/11/17 2009/11/17

309K_ 0402_1%

12

Compal Secret Data

PR76

PR77

47K_0 402_1%

Deciphered Date

C

VI N

12

PR12

10K_0 402_1%

1 2

12

12

PC44

.1U_0 402_16V7K

ADP_V <26>

Title

Size Do cumen t Numb er R ev

Dat e: S heet o f

Compal Electronics, Inc.

CHARGER

KAVAA LA-5121P M/B

D

33 42Tuesday, March 10, 200 9

1.0

5

4

3

2

1

TPS51427_B+

TPS51427_B+

PJ10

2

B+

D D

150 U_B2_6.3VM_ R35M

C C

B B

+3.3 VALW P Ipeak =6A ; Imax=4.2A
Chok e DC Rmax=65. 6m ohm
Rds( on)= 18m ohm (max ) ; Rds (on)=15m ohm(typical)
Vlim it=( 5E-06 * 200 K)/10=100mV
Ilim it=1 00mV/15 m ~100mV/18m
= 5.55A ~6.66A
Iocp =Ili mit+1/2 *Delta IL
= 6.44A ~ 7.55A
1/2* Delt a IL=0. 89A (Freq=300KHz)

A A

JUMP_43 X118@

+3VALWP

PC5 5

112

12

PC1 29

0.1 U_0402_25V 6

12

1

+

PC 99

2

.1U _0402_16V7 K@

PR8 0
0_0402_ 5%

12

PR8 5

@

10K_040 2_1%

1 2

12

PC 46

PC 45

4.7 U_0805_25V 6-K

4.7 U_0805_25V 6-K

PL4

4.7U H_PCM C063T- 4R7MN_5.5A_2 0%

1 2

680P_06 03_50V8J

GLZ 5.1B_LL34-2

VS

1SS 355_SOD323-2

PD1 7

12

PC 47

2200P _0402_50V7K

PR8 1

4.7_ 1206_5%

PC5 8

PD1 6

1 2

12

MAINPWON<32>

12

12

12

1 2

2

3 6

241

3 6

241

PR8 9

100K_04 02_1%

PR 90

578

PQ20

AO4466_ SO8

578

PQ23
AO4712_ SO8

PC6 2

0.22 U_0603_10V 7K

1 2

1 2

200K_ 0402_1%

VL

PR9 5

806K_06 03_1%

PR9 7

0_0402_ 5%

12

PQ24

TP0610K-T1-E3 _SOT23-3

1 3

1 2

PR7 8

0_0805_ 5%

1 2

PR7 9

2.2_ 0603_5%

1 2

PC5 6

0.1U _0603_25V7 K

1 2

PC6 1 0.22 U_0603_10V 7K

@

0_0402_ 5%

PR9 8

@

47K_040 2_5%

1 2

12

PC 64

0.0 47U_0603_1 6V7K

0.1U _0603_25V7 K

D H3

BST3A

LX3

DL3

FB3

VL

2VREF_TPS51427

1 2

PR9 3

1 2

2VR EF_TPS5142 7

12

PC6 5

@

0.04 7U_0402_16 V7K

PC5 1

1 2

VL

1 2

PU6

33

TP

26

DRVH2

24

VBST2

25

LL2

23

DRVL2

30

VOUT2

32

REFIN2

1

VREF2

8

LDOREFIN

20

NC

4

EN_LDO

14

EN1

27

EN2

PR 94

0_040 2_5%

PC 63

1 2

PC 52

1U_ 0603_10V6K

3

6

VIN

V5FILT

TONSE

VREF3

2

5

12

PR9 6
0_0402_ 5%

1 2

1U_ 0603_10V6K

2VR EF_TPS5142 7

12

PC 53

7

4.7 U_0805_ 6.3V6K

19

LDO

V5DRV

DRVH1

VBST1

LL1

DRVL1

PGND

VOUT1

FB1

VSW

SKIPSEL

PGOOD2

PGOOD1

TRIP1

TRIP2

GND

SN0 806081 RHBR_QFN3 2_5X5

21

D H5

15

BST5A

17

LX5

16

DL5

18

22

10

FB5

11

9

29

28

13

ILM1

12

ILIM 2

31

PC5 4

1U_ 0603_10V6K

1 2

PR8 3

2.2_ 0603_5%

1 2

PC5 7

0.1U _0603_25V7 K

PR8 7 0_0402_ 5%@

PR8 8 0_0402_ 5%

1 2

+5VA LWP Ipeak=5 .84A ; Imax=4.088A
Chok e DC Rmax=65. 6m ohm
Rds( on)= 18m ohm (max ) ; Rds (on)=15m ohm(typical)
Vlim it=( 5E-06 * 200 K)/10=100mV
Ilim it=1 00mV/15 m ~ 100mV/18m
= 5.55A ~ 6.66A
Iocp =Ili mit+1/2 *Delta IL
= 6.53A ~ 7.64A
1/2* Delt a IL=0. 98A (Freq=400KHz)

1 2

12

PR9 1

200K_04 02_1%

PR9 2

200K_04 02_1%

578

3 6

578

3 6

241

241

12

PC 48

PC 49

4.7 U_0805_25V 6-K

PQ21

AO4466_ SO8

PQ22
AO4712_ SO8

4.7 U_0805_25V 6-K

4.7U H_PCM C063T- 4R7MN_5.5A_2 0%

12

12

PL5

PR8 2

4.7_ 1206_5%

PC5 9
680P_06 03_50V8J

12

PC 50

2200P _0402_50V7K

12

12

12

PC1 30

0.1 U_0402_25V 6

+5VALWP

PR 84

61. 9K_0402_1%@

1 2

PR 86

0_040 2_5%

1 2

1

12

+

PC6 0

.1U _0402_16V7 K@

150 U_B2_6.3VM_ R45M

2

PC1 20

VL

POK <32>

12

12

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/11/17 2009/11/17

3

Compal Secret Data

Deciphered Date

Title

Size Do cumen t Numb er R ev

2

Da te: Sheet o f

Compal Electronics, Inc.

+5VALWP/+3VALWP

KAVAA LA-5121P M/B

34 42Tu esday, M arch 10 , 2009

1

1.0

A

B

C

D

12

0.1U_0 402_25V6

PC128

0.1U_0 402_25V6

12

PJ11

2

JUMP_43X118@

+1.05VS P

220U_ B2_2.5VM

1

+

PC70

2

PJ12

2

JUMP_43X118@

12

1

+

PC79
220U_ B2_2.5VM_R25M

2

112

112

+1.8VP

1.05V_B +

12

1 1

PR99

PR100
0_0402_5%

1 2

SUSP #< 26,30,33, 36>

+5VALW

2 2

PR103

422_0 603_1%

1 2

1U_06 03_10V6K

PC71

12

PC68

@

.1U_0 402_16V7K

12

PC73

@

47P_0 402_50V8J

1 2

PR105

8.25K _0402_1%

1 2

12

PR106

20.5K _0402_1%

1 2

255K_ 0402_1%

1

PU7

2

TON

EN_PSV

3

VOUT

4

V5FILT

5

VFB

6

PGOOD

GND7PGND

8

PR101

2.2_0 603_5%

BST_1.05V

1 2

14TP15

VBST

13

DRVH

12

LL

11

TRIP

10

V5DRV

9

DRVL

TPS 51117RGY R_QFN14 _3.5x3.5

BST_1. 05V-1

DH _1.05V

LX_1.05V

1 2

PR104

13.7K _0402_1%

DL_1. 05V

PC69

1 2

0.1U_ 0603_25V7K

+5VALW

12

PC74

4.7U_ 0805_10V6K

578

3 6

578

3 6

PQ25
AO4466_ SO8

241

2.2UH _PCMC0 63T-2R2M N_8A_20%

PQ26
AO4712_ SO8

241

1 2

12

PR102

12

PC72

PC66

4.7_12 06_5%

680P_ 0603_50V8J

12

578

PQ27
AO4466_ SO8

3 6

578

3 6

241

2.2UH _PCMC0 63T-2R2M N_8A_20%

PQ28
AO4712_ SO8

241

12

12

PR107

255K_ 0402_1%

PR108

0_0402_5%

1 2

3 3

SYS ON<26 ,30>

+5VALW

4 4

PR111

422_0 603_1%

1 2

1U_06 03_10V6K

PC80

12

PC77

@

.1U_0 402_16V7K

12

PC82

47P_0 402_50V8J@

1 2

PR113

28.7K _0402_1%

1 2

12

PR114

20.5K _0402_1%

1 2

1

PU8

2

TON

EN_PSV

3

VOUT

4

V5FILT

5

VFB

6

PGOOD

GND7PGND

8

PR109

2.2_0 603_5%

BST_1.8V

1 2

14TP15

VBST

13

DRVH

12

LL

11

TRIP

10

V5DRV

9

DRVL

TPS 51117RGY R_QFN14 _3.5x3.5

BST_1.8V- 1

DH _1.8V

LX_1.8V

1 2

PR112

15.4K _0402_1%

DL_1. 8V

PC78

1 2

0.1U_ 0603_25V7K

+5VALW

12

PC83

4.7U_ 0805_10V6K

12

PC67

4.7U_1 206_25V6K

PL6

51117_B+

12

PC75

4.7U_1 206_25V6K

PL7

1 2

PR110

4.7_12 06_5%

PC81

680P_ 0603_50V8J

12

PC127

PC125

4.7U_1 206_25V6K
2200P _0402_50V7K

12

PC121

.1U_04 02_16V7K@

12

PC76

PC126

4.7U_1 206_25V6K
2200P _0402_50V7K

PC122

.1U_04 02_16V7K@

B+

B+

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/11/17 2009/11/17

Compal Secret Data

Deciphered Date

C

Title

Size Do cumen t Numb er R ev

Dat e: S heet o f

Compal Electronics, Inc.

1.05VSP/1.8VP

KAVAA LA-5121P M/B

D

35 42Tuesday, March 10, 200 9

1.0

5

D D

4

3

2

1

+1.8V

1

1

PJ13
JUMP_43X79@

2

2

PC84

4.7U_ 0805_6.3V 6K

C C

PR117

0_0402_5%

1 2

SUSP<30>

0.1U_ 0402_16V7K@

PC89

12

1 2

13

2

G

D

PQ29

S

SSM3 K7002FU_SC 70-3

PR115

1K_04 02_1%

PR118

1K_04 02_1%

12

12

12

PC88

.1U_04 02_16V7K

PU9

VIN1VCNTL

2

GND

3

VREF

4

VOUT

APL53 31KAC-TRL_SO8

+0.9VSP

12

PC90
10U_0 805_6.3V6M

6

5

NC

7

NC

8

NC

9

TP

+3VALW

12

PC85
1U_06 03_10V6K

+3VS

PJ14

JUMP_43X79@

112

12

PC86

PC123

.1U_04 02_16V7K

2

2

12

APL55 08-25DC-T RL_SOT89-3

1U_06 03_10V6K

PU10

IN

GND

3

OUT

1

12

PC87

4.7U_ 0805_6.3V 6K

12

PR116

@

150_1 206_5%

+2.5VSP

+1.8V+5VALW

1

PJ15

JUMP_43X39@

12

B B

PR119
0_0402_5%

1 2

SUSP #<2 6,30,33, 35>

A A

12

PC95

0.47U _0402_6. 3V6K@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

PC91

1U_06 03_10V6K

PU11

7

POK

8

EN

APL59 12-KAC-TRL_SO8

2008/11/17 2009/11/17

6

1

VCNTL

GND

VOUT

VOUT

VIN

FB

VIN

10U_0 805_6.3V6M

5

4

3

2

9

2.7K_ 0402_1%

3K_04 02_1%

Compal Secret Data

PC92

PR120

PR121

Deciphered Date

1

2

2

12

12

12

12

12

PC93

0.01U_ 0402_25V7K

2

+1.5VSP

PC94

22U_0 805_6.3V6M

Title

Size Do cumen t Numb er R ev

Dat e: S heet o f

Compal Electronics, Inc.

+0.9VSP/+1.5VP/+2.5VSP

KAVAA LA-5121P M/B

36 42Tuesday, March 10, 200 9

1

1.0

A

B

C

D

E

F

G

H

1 1

PM_ DPRS LPVR<6 ,17>

0_0 402_5%

H_D PRST P#< 4,16>

CLK _ENA BLE#

+3VS

+1.05VS

PR1 36

68_ 0402_5%

2 2

H_P ROCH OT#<4>

3 3

VGATE<1 2,17,26 >

12

0.1 U_04 02_16V7 K@

PR1 37

1 2

147 K_0402 _1%

100 K_06 03_1%_TH 11-4H10 4FT@

1 2

PR1 43

PC1 07

100 0P_040 2_50V7K

1 2

PR145
332K_0402_1%

PC1 09
82P _0402 _50V8J

PR1 50

PR1 52

PC1 17

PC1 03

1 2

40. 2K_040 2_1%

@

H_P ROCH OT#

PC1 05

PR1 48

1 2

1.5 4K_040 2_1%

1K_ 0402_1%

1 2

12

PR1 39

12

1 2

PW ON

1 2

PR1 44

1 2

12

120 P_0402_ 50V8

PH 3

0.0 15U_ 0402_16 V7K

1 2

4.1 2K_040 2_1%

1 2

0_0 402_5%

1 2

0_0 402_5%

330 P_0402 _50V7K

VC CSEN SE<5>

VSS SENSE<5>

1 2

PR1 42

4.2 2K_040 2_1%@

6.8 1K_040 2_1%

PC1 08

1 2

PR1 25 0_0402 _5%

1 2

PR1 26

0_0 402_5%

1 2

12

PR1 27
10K _0402_1 %

1

2

3

4

5

6

7

8

9

10

PC1 11
120 0P_040 2_50V7K

1 2

PR1 49

PC1 13 1000P _0402_5 0V7K

1 2

PC1 14
100 0P_040 2_50V7K

PC1 16 330P_ 0402_50V 7K

1 2

1 2

PR1 54

1K_ 0402_1%

PR1 23

PU 12

FDE

PMON

RBIAS

VR_TT#

NTC

SOFT

OCSET

VW

COMP

FB

1 2

1.6 2K_040 2_1%

12

41

GND PAD

PR1 55

1 2

PC1 00

1U_ 0603_1 0V6K

39

40

PGOOD

11

PR1 22
499 _0402_1 %

38

3V3

CLK_EN

RTN

13

12

PC1 04

0.2 2U_0 603_25V 7K

1 2

+5VS

PR1 24

1_0 603_5%

1 2

12

PC1 02

578

1U_ 0402_ 6.3V6K

3 6

241

PQ3 0

AO4 466_SO8

12

470 0P_040 2_25V7K

578

PQ31

AO4 712_SO 8

3 6

241

<5>

<5>

<5>

<26>
CP U_VI D5

CP U_VI D6

CP U_VI D3

CP U_VI D4

VR _ON

12

12

12

12

12

<5>

<5>

CP U_VI D2

CP U_VI D1

12

12

<5>

<5>

CP U_VI D0

12

PC1 01

PR1 32 0_0402 _5%

PR1 30 0_0402 _5%

PR1 31 0_0402 _5%

PR1 28 0_0402 _5%

PR1 29 0_0402 _5%

34

35

36

37

VCCP

LGATE

PHASE

UGATE

BOOT

VSS19VSUM17DFB

18

12

1 2

12

PC1 12

0.2 2U_0 603_25V7K

VID331VID432VID533VID6

VID2

VID1

VID0

VSSP

NC

VDD20VIN

1 2

PC1 10

1U_ 0402 _6.3V6K

PR1 47
10_ 0603_5%

VR_ON

DPRSTP#

DPRSLPVR

VO16DROOP14VSEN12VDIFF

15

12

1 2

PC1 15

PC1 18

0.0 68U_ 0402_10 V6K@

.1U _040 2_16V7K

PR1 35 0_0402 _5%

PR1 33 0_0402 _5%

PR1 34 0_0402 _5%

30

29

28

27

LGA TE_C PU

26

25

PHA SE_C PU

24

UGA TE_ CPU

23

BOO T_CP U

22

21

ISL 6261 ACRZ -T_QFN4 0_6X6

PR1 46
10_ 0603_5%

+5VS

+CPU_B+

VSU M

12

PR1 51

12

3.5 7K_040 2_1%@

PR1 53

1.8 2K_040 2_1%

PH 4
10K B_06 03_5% _ERTJ1V R103J@

1 2

PR1 38

2.2 _0603_ 5%

1 2

0.0 1U_0 402_25V7K

PC 96

12

12

PC 97

4.7 U_080 5_25V6M

PD 18
B34 0A_SMA2

+CPU_B+

12

4.7 U_080 5_25V6M

12

12

PC 98

PR1 40

@

4.7 _1206_ 5%

PC1 06

@

680 P_060 3_50V8J

PL8

FBM A-L11-20 1209-121L MA50T_0 805

1 2

1.5 UH_ PCMC 063T- 1R5MN_ 9A_20%

PL9

1 2

12

PR1 41

11. 8K_040 2_1%

VSU M

+CPU_C OREP

B+

PJ1 6

112

@

JUM P_43X118

2

+CPU_CORE

+CPU_C OREP

12

PC1 19

0.2 2U_0 603_25V7K

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

C

D

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

E

2008/11/17 2009/11/17

Compal Secret Data

Deciphered Date

F

Title

Size D ocum ent Num ber R ev

Dat e: Sh eet of

G

Compal Electronics, Inc.

+CPU_CORE

KAVAA LA-5121P M/B

37 42T ues day, Mar ch 10, 2009

H

1.0

NO DATE PAGE MODIFICATION LIST PURPOSE

-------------------------------------------------------------------------------------------------------------

P34-3VAL W/5VALWEVT Chan ge PD17 SC1SS3 55010 T O SC1000 01K00 Choice t he same rating

P35-1.05 VSP/1.8 VPEVT Change P R101&10 9 0_06 03_1% t o0_0603_5% Choice the sa me rating

EVT Change P R67 2 2K_0402 _5% to 22K_040 2_1%

EVT

EVT

P33-CHAR GER Choice t he same rating

P36-+0.9 VSP/+1. 5VP/+2. 5VSP

P36-+0.9 VSP/+1. 5VP/+2. 5VSP

Change P C85 1U _0603_6 .3V6M T O 1U_060 3_10V6M

Change P C88 SE0 76104KM 8 to SE 076104K80

EVT Change P C115 SE07610 4KM8 to SE07610 4K80P37-+CPU _CORE

P33-CHAR GER Choice t he A51 compone ntEVT Change P R76 SD 0343093 8L to S D034309380

P34-3VAL W/5VALWEVT Chan ge PC55 & PC60 SGA00 001E00 T O SGA00 002900 Choi ce the small si ze

P31-DCIN /DECTORDVT Chan ge PF1 SP0410 7P303 T O SP0400 00P00 Decrease the ra ting(Me mo)

P37-+CPU _COREDVT Change P C116 & PC117 S E074331 K00 TO S E074331K80 Choi ce the pb free material

DVT Change P C60 Sg a000029 00 TO S ga00001e00 Change main s ourceP34-3VAL W/5VALW

P31-DCIN /DECTORDVT Chan ge PJP1 4pin t o 2pin change dimati on

DVT Change P C55 Change the ESRP34-3VAL W/5VALW

P35-1.05 VSP/1.8 VPDVT Change P C79 TO SGA0000 4800 Change t he ESR

P33-CHAR GER Design c hangeDVT Change P R68 1 54K_040 2_1% t o 309K_0 402_1%

P33-CHAR GER Design c hangePVT add PR1 2 10K

P33-CHAR GER RF tema requirePVT add pc13 1 & pc1 24

PVT PR83 & P R79 cha nge to 2.2ohm EMIP34-3VAL W/5VALW

PVT ADD PC12 9 & PC1 30 RF tema requireP34-3V ALW/5VALW

P35-1.05 VSP/1.8 VPPVT PR101 & PR109 c hnage t o 2.20hm EMI team req uire

P37-+CPU _COREPVT PR138 ch ange to 2.2 ohm EMI tema requ ire

P35-1.05 VSP/1.8 VPPVT ADD PC1 28 & PC 127& PC 125 & P C126 RF team require

P33-CHAR GER Design c hangePVT add PQ9 &PR51& PQ12&PQ 13

P33-CHAR GERP VT Change PR 74 & De lete PD 15 Design chan ge

P37-+CPU _COREPVT PR140 & PC106 r eserved EMI te ma requ ire

Choice t he same rating

Choice t he same vender

Choice t he same vender

ESD reco mmendDVT Add PC1 23 0. 1uP36-+0.9 VSP/+1. 5VP/+2. 5VSP

RF recom mendDVT Sunber A llAll

EMI tema require

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/11/17 2009/11/17

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size D ocu ment Nu mber R ev

Dat e: Sh eet of

Power PIR

KA VAA LA -512 1P M /B

38 42T uesd ay, Mar ch 10, 2009

1.0

5

4

3

2

1

PIR (Product Improve Record)

KAVA A LA -5121P SCHEMATIC CHANGE LI ST
REVI SION CH ANGE: 0.1

NO DATE PAGE MO DIFI CATION LIS T PUR POSE

---- ---- --- ---- ---- --- ---- --- ---------- ---------- ---------- ---------- --------- ---------- ---------- ---------- ---------

08/12/1 5
(1) P15 Del C7 wit h 22 0U For layou t placeme nt limit
(2) P16 Cha nge Net n ame R182.1 from +RT CBATT to + RTCVCC

D D

Cha nge Net n ame R185.1 from +RT CBATT to + RTCVCC
Del C210 with 0.1uf
(3) P18 Cha nge Net n ame C244 f rom +RTCB ATT to +RT CVCC
(4) P28 Rev ersa l K B Pi n d efine Fo r KB pin d efine dif ference fr om PCB Foo rprint

08/12/1 1
(1) P25 Cha nge Car d Reader Function " 3IN1" to " 2IN1" For Co st down
(2) P26 Lin k Ne t n ame TS_ST OP from U2 9.85 to JT S.4 For To uch Scree n
Lin k Ne t n ame TS_RE S from U2 9.86 to JT S.5 For To uch Scree n

08/12/1 0
(1) P25 Cha nge Card Rea der Footp rint T-SOL _143-14003 03600_21P_ NR-T
(2) P28 Chang e KB Matri x from 30 pin to 34 pin
(3) P29 Add D40 ,D41 for Key boar d F10/F11 function

08/12/0 9
(1) P12 Res erve C4 72~C478 with 47P for WWLAN requ est
(2) P19 Res erve C4 79~C481 with 47P for WWLAN requ est
(3) P28 Res erve R3 99,Q32 f or test for cost down plan

08/12/0 5
(1) P13 Res erve R4 68,R469 w ith 680pF for EM I request

C C

(2) P20 Res erve L1 0,L11,L12 Commom ch oke for EM I request for EM I request
(3) P21 Res erve L1 3,L14 Com mom choke for EMI re quest for EM I request
(4) P22 Add PJ1 9 a nd link to +5VS for Cost Down Plan
(5) P22 Res erve RA 31,RA37,C A34,CA42 f or EMI req uest for EM I request
(6) P22 Res erve RA 4 with 0 ohm for EM I request for EM I request
(7) P28 Res erve R3 96,Q 31,C471 ,D39 for test for cos t down pla n

08/12/0 4
(1) P17 Cha nge BT_ RST# from GPIO37/SA TA3GP to G PIO21/SATA 0GP for SW recommen d
(2) P17 Lin k R2 04. 1 to GPIO 37/SATA3GP for SW recommen d
(3) P26 Cha nge pac kage R749 from 0603 to 0 402 for layout placement limit
(4) P13 Cha nge LVD S footpri nt to "ACE S_87213-20 00G_20P" for ME request
(5) P21 Cha nge TOU CH SCREEN CONN. foo tprint to "ACES_8721 3-0600G_6P " for ME request

08/1 2/01
(1) 13 Ch ange L4,L 5 from Bea d to 0ohm
(2) 14 Change R15 1,R152 fro m 2.2K to 4.7K
(3) 14 Change R15 3,R154 for m 2.2k to 4.7K
(4) 17 Change p ower sours e +3VALW t o +3V_SB
(5) 18 Add R 385 with 0 ohm
(6) 18 Ch ange R226 from STAR @ to @
(6) 19 Change R22 9 from WIN MAX@ to A LWAY

B B

(7) 19 Change C 265~C270 f orm GPS@ t o 3GGPS@
(8) 19 Add R 378~R381 with Oohm for touch screen sel ect
(9) 20 Add D3 7,D38 ESD diode to U SB D+/- po rt0,2
(10) 21 Add T ouch scree n conn.
(11) 23 Del RA31,RA32 with 0ohm
(12) 25 Del RC2 1 with 0oh m
(13) 25 Del Q C1 with 2N 7002
(14) 25 Change net name CR_L ED to CR_ LED#
(15) 26 Del ROM Circu it of rese rve
(16) 28 Del R 368 with 3 00ohm
(17) 28 Add R382~384 with 300oh m
(18) 29 Change Q14 A form SOT 363 to SO T23
(19) 30 Ch ange R355 from 1k t o 3.3k
(20) 30 Change C451 with 0.1uf and link to + 3VALW
(21) 30 Change R353.2 li nk from +5 VALW to +3 VALW
(22) 30 Change Q 14B,Q9 for m SOT363 t o SOT23

A A

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/11/17 2009/11/17

Compal Secret Data

Deciphered Date

Title

Size D ocument N umber Re v

2

Date: Sheet of

Compal Electronics, Inc.

ISPD

KAVAA LA-5121P M/B

39 42Tuesday, March 10, 2009

1

1.0

5

4

3

2

1

PIR (Product Improve Record)

KAVAA LA-5121P SCHEMATIC CHANGE LIST
REVISI ON CHANGE: 0.1

NO DA TE P AGE M ODIFI CATION LIST PURPOSE

------ ------ ------ ----- ------ ------ ----------------------------------------------------------------------------------

08/12/30
(1) P 30 Mount R361 with 1 00K ohm For SUSP pull high
08/12/26
N0 P AGE MODIFI CATIO N LIST PURPOSE

D D

(1) P 29 Add U1 (SA00 0036K0 0)forN280 CPU
08/12/25
(1) P 27 Del R3 98 wi th 0 o hm and U32.10 link to GND For customer recommend
(2) P 31 Change H3 l ink to GNDA For EMI request

08/12/24
N0 P AGE MODIFI CATIO N LIST PURPOSE
(1) P 27 Change U32.7 link to +3VS_HDP
Change U32.9 no connect
08/12/23
(1) P 16 Add U1 5A.AF 7 and U15A.A E7 lin k to GND The unused STAT port RX signals must be properly tied to ground
08/12/22
(1) P 15 Change C203.1 Net name from PLTRST#_R to PLTRST#
(2) P 12 Reserv e C86 8 with 10P For Custome request
(3) P 13 Reserv e C87 1 with 10P For Custome request
(4) P 25 Reserv e RC2 1 with 10 oh m and CC16 with 10P For Custome request

08/12/21
(1) P 16 Change C209 Packa ge from 0603 to 0402 For layout pacement limit
(2) P 18 Change C222 Packa ge from 0603 to 0402 For layout pacement limit
Change C219 Packa ge from 0603 to 0402 For layout pacement limit
(3) P 25 Mount RC20 with 0 ohm For CLK 48Mhz

C C

08/12/18
(1) P 4 Reserv e C48 4~C495 with 180p For debug
(2) P 6 Add R4 03~R4 05 wit h 1K ohm For CPU CLK link to NB
(3) P 10 Change pack age C6 1,C62,C68,C78,C79 from 0603 to 0402 For layout pacement limit
Change pack age C7 4,C75 from D2 to B2 For layout pacement limit
(4) p 11 Del C1 24 wi th 2.2U
(5) P 12 Del R8 5,R87 ,R88,R 89,R92,R94,R95,R96,R102,R105,R106,R109 For CPU BSELE0~2 link to CLK Gen
Change R90, R91 fr om 33 ohm to 22 ohm For damping resistor when loading is two device
Chagne net name F SB to CPU_BSEL1 For CPU link to CLK Gen
Del R1 10,R1 11 wit h 10K ohm For UMA platform not need to reserve
(6) P 13 Change Net name R 117.1 from +3V_SB to +3VS For layout pacement
Change C183 link from GND to +3VS For layout pacement
Change JLVD S pin2 from +LEDVDD to +LCDVDD_L For LCD power consumption
(7) P 14 Change C190 ~195 to 2.2P For EMI request
(8) P 15 Change pack age to 8P4R with 8.2K For layout pacement limit
Dell U16,R180,C206
(9) P 16 Del R1 90 wi th 8.2 Kohm For customer request
Change R189 from 4.7K to 10K ohm
Change Net name from IDE_DIORDY to IDE_DIORDY_IRQ
(10) P 17 Change R216 from 100K to 330K ohm For ACIN issue
Add R2 15,R4 06,Q31 ,R408, D43,R409 For leakage current of RSMRST# Circuit
Add R4 10,D4 4 For EC leakage current to SB
(11) P 18 Add R4 96 wi th 0.1U For soft start
(12) P 18 Add L1 5 wit h MBK1608121YZF_0603 For Ripple

B B

(13) P 20 Change C455 ,C458, C222 from D2 to B2 with 220U For layout placeemnt limit
Change U21. 4 from USB_EN# to USB_CHG_EN# For customer request
Add U21.5 link to U29.74
(14) P 21 Dell Q 17 wi th 2N7002 For cost down
Change R237.1 from +5VS to +3VS
Chagne C294.2 from GND to +3VS
(15) P 22 Reserv e PJ1 9
(16) P 24 Dell CL6 with 10U
Change UL3 from HD-024A to NS681680 For cost down
(17) P 25 Reserve CC9,CC12,YC1
Mount RC19 for 48Mhz
Mount RC20 For 48Mhz
(18) P 26 Del R304 with 10K ohm
Change R307 from 100K to 330K ohm
R243 please close to EC
Add Net Name USB_CHG_EN#
Del D22,R310,R311
(19) P 27 Change U31 P/N from SA000030500 to SA000035U00
(20) P 28 Chagne U36 ROM Size from 16M*1 to 8M*1
JBK KB Matrix the same to KSKAA
Del JP2
(21) P 29 Change R370 ,R371,R372,R375,R383,R384,R374,R333 from 120 ohm to 220 ohm
Del R325,R326

A A

(22) p 30 Add R401,R402 with 10K ohm

Security Classifi cation

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/11/17 2009/11/17

Compal Secret Data

Deciphered Date

Title

Size Docum ent Number Re v

2

Date : Sheet o f

Compal Electronics, Inc.

ISPD

KAVAA LA-5121P M/B

40 42Tuesd ay, March 10, 2009

1

1.0

5

4

3

2

1

PIR (Product Improve Record)

KAVA A LA -5121P SCHEMATIC CHANGE LI ST
REVI SION CHANGE: 0 .1-->0.2

NO DATE PAGE MO DIFI CATION LIS T PUR POSE

---- ---- --- ---- ---- --- ---- --- ---------- ---------- ---------- ---------- --------- ---------- ---------- ---------- ---------

1) 1/13 10 Ch ang e D1 to CH751H-4 0PT_SOD323 -2 For BOM simpl ify

2) 1/13 18 Ch ang e D7,D8 to CH751 H-40PT_SOD 323-2 For BOM simpl ify

3) 1/13 23 Ch ang e net na me from JL INE to JEX MIC For E XMIC JACK

D D

4) 1/13 23 Ch ang e net na me from JE XMIC to JL INE For J LINE JACK

5) 1/13 29 Ch agn e JP OWE R.3 net na me from ON /OFFBTN# to ON/OFFB TN#_R Fo r PWR/B ca n't power on with ba ttery mode
1/13 30 Ad d H20,H2 1 For h alf card

6) 1/22 13 Ch ang e R 117 f rom 47k to 100K ohm For LCD Soft s tart redus e inrush c urrent
Ch ang e Q 11 fr om SI2301B DS to A034 13 For LCD Soft s tart redus e inrush c urrent
Ad d C 498 w ith 0.01uF For LCD Soft s tart redus e inrush c urrent

7) 1/22 19 Ch ang e SW1 .3 to dumm y pin F or Kill sw itch issue
Ch ang e SW1 .1 to GND F or Kill sw itch issue

8) 1/22 21 Ch ang e R 238 f rom 10K to 47K For BT Soft st art reduse inrush cu rrent
Ad d C 499 w ith 0.01uF For BT Soft st art reduse inrush cu rrent

9) 1/22 22 De l Net na me AMP_SPK _R and AMP _SPK_L For M ono SPK
Ad d Net na me AMP_SPK from UA2. 37 to UA3. 17 For M ono SPK
23 De l C A32 with 0.033UF For Code c output less than 0.9V
Ad d R A38,RA40 with 1K o hm For Code c output less than 0.9V
Ad d R A39,RA41 with 9.09 k ohm For Code c output less than 0.9V
Ad d C A43 with 1uf For Code c output less than 0.9V
1/22 27 Ch ang e U 34 P/N from SA00 000XZ50 to SA000037Y 60 For G- sensor con troller c hip change
29 JT OUC H pi n define reversal For ME r equest as sembly eas y
30 Ch ang e R 355 f rom 3.3K t o 47K For LAN Soft s tart redus e inrush c urrent
Ad d C 500 w ith 0.01uf For LAN Soft s tart redus e inrush c urrent

10) 2/3 14 Re ser ve C504 with 0.1u f For EMI reque st
2/3 19 Ad d R 411 with 0 ohm Del Kill switch fun ction

C C

2/3 Re ser ve S W1,RM1,U17 ,C264 for del kill s witch func tion Del kill switch fun ction
2/3 20 Ch ang e D15,D 38,D37 fr om PRTR5V0 U2X to CM1 293A-04SO For EMI reque st
2/3 23 Ch ang e DA3,D A6,DA7 fr om PJDLC05 to PACDN0 42Y3R For EMI reque st
2/3 28 Ad d C501,C 502 with 3 30pf For E MI reques t
Ad d C503 w ith 470pf For E MI reques t
Ad d R412 w ith 10 ohm For E MI reques t
Ad d C508 with 6pf For EMI reque st
2/3 29 Ad d R413,R 414,R415 w ith 0 ohm For E MI reques t
Re ser ve C505,C 506,C507 w ith 0.1uf For E MI reques t
Ch ang e D27 fr om PJDLC05 to PACDN0 42Y3R For E MI reques t
De l D25 wi th PJDLC05 For E MI reques t
Ch ang e R37 5 from 220 to 300 oh m F or White L ED of PWR/ B
Ch ang e R37 5.1 Net na me from +3 VALW to + 5VALW F or White L ED of PWR/ B

11) 2/4 22 Ch ang e CA14 from 100p f to 0.1uf For SPK noise issue
Ad d P J20,P J21 For customer r equest(Ech o Peak Iss ue)
24 Ch ang e UL3 fr om 16pin(S P050003N00 ) to 24pin (SP050003P 00) For E MI issue

12) 2/5 06 Ad d R416 with 0 oh m For WWLAN req uest
Re ser ve C511 with 22pf For WWLAN req uest
12 Re ser ve C509, C510 with 10p For WWLAN req uest
22 Re ser ve UA1,C A9,CA11 For cost down plan
2/6 Mo dif y JUSBA, JUSBB,JUSB C Symbol f or GND pad For G ND pin
10 Re ser ve C67 with 220u F F or Cost do wn plan

B B

Ad d C51 4 with 0.1 uF F or ESD tea m request
23 Ch ang e R A38,RA40 with 2K o hm For Code c output less than 0.9V
Ch ang e R A39,RA41 with 8.2K ohm For Code c output less than 0.9V
24 Ch ang e UL3 f rom NS681 680(SP0500 03N00)to 8 456E(SP050 005V00)For ESD fail issue
30 Re ser ve +1.5V S,+1.05VS ,+0.9VS,+1 .8VS disch arge circu it For Cost down plan
27 Re ser ve C867 with 0.22 uf For U33.4 NC pin
Ch ang e U 33 from APL5151-3 3BC to G91 91-330T1U For powe r sequenc e issues o n HPC
2/9 20 Ch ange C4 55,C288 f rom 220uf to 150uf
Re ser ve C45 8 with 150 uf F or Cost do wn plan
2/11 22 Mo unt R A13 with 0 ohm For EMI r equet open channel
27 Ch ang e U 31 from SA000035 U00 to SA0 00039900 For Cu stomer req uest vers ion change
2/16 14 Mo unt C504 with 0.1u F For EMI reque st
23 Mo unt DA3/D A6 with P ACDN042Y3R For EMI reque st
17 Re ser ve C 217,C218 with 0.1u F For Rese rve WWAN PCIE inter face

A A

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/11/17 2009/11/17

Compal Secret Data

Deciphered Date

Title

Size D ocument N umber Re v

2

Date: Sheet of

Compal Electronics, Inc.

ISPD

KAVAA LA-5121P M/B

41 42Tuesday, March 10, 2009

1

1.0

5

4

3

2

1

PIR (Product Improve Record)

KAVA A LA -5121P SCHEMATIC CHANGE LI ST
REVI SION CHANGE: 0 .2-->1.0

NO DATE PAGE MO DIFI CATION LIS T PUR POSE

---- ---- --- ---- ---- --- ---- --- ---------- ---------- ---------- ---------- --------- ---------- ---------- ---------- ---------

1) 2/25 4 Mo unt C484~C 495 with 2 20pF For EM I reques t

2) 2/25 6 Ch ang e N et name from ICH _POK to IC H_PWROK For cor recting po wer down sequence

3) 2/25 12 Ch ang e R81,R8 2 from 0 o hm to FBMH 1608HM601- T_0603 For WW AN reques t

D D

Mo unt C133,C 141 with 4 7pF For WW AN reques t
Mo unt C142, C143,C144 ,C145,C146 ,C868 with 22pF For WWAN reque st

4) 2/25 13 Mo unt C871 w ith 10pF For WW AN reques t

5) 2/25 15 Mo unt C203,C 204 with 0 .1uF For WW AN reques t

6) 2/25 17 Ch ang e N et name from ICH _POK to IC H_PWROK For cor recting po wer down sequence
Ad d R 418 wit h 10K ohm For cor recting po wer down sequence
Ad d U 37 with TC7SHO8F UF_SSOP5(S A007080100 ) For cor recting po wer down sequence
Re ser ve R 417 wit h 0 ohm For cor recting po wer down sequence

7) 2/25 19 Mo unt C479,C 480,C481,C 482 with 4 7pF For WW AN reques t

8) 2/25 22 Mo unt RA31 w ith 22 ohm ,CA34 with 10pF For WW AN reques t

9) 2/25 23 Ch ang e JEXMIC ,JLINE PCB footprint to JA6033 L-B3T4-7F_ 6P-TFor ME reques t

10) 2/25 25 Mo unt CC16 w ith 10pf,R C21 with 1 0 ohm For WW AN reques t

11) 2/25 26 Ch ang e U 29.104 net name from ICH_P OK to EC_P WROK For cor recting po wer down sequence

12) 2/25 28 Mo unt C508 w ith 33pF,R 412 with 3 3 ohm For WW AN reques t

13) 2/25 30 Re ser ve R349 with 200K ohm For design cha nge
Ch ang e C447 from 0.01 uf to 0.02 2uF For design cha nge
Ch ang e R346 from 20K to 47K ohm For design cha nge

14) 3/2 14 Ch ang e D5 fr om SC1B49 1D000 to S CS00002000 For buyer reco mmend
28 Ch ang e Cha nge U36 to MX25L8005 M2C(SA000 00XT00) Fo r CLK freq uency 75MH z
3/2 30 Ch ang e H18 fr om H_3P0N to H_2P6N For ME request
H19 fr om H_6P0X3 P0N to H_6 P0X2P6N For ME reqeust
3/4 08 Ad d G MCH_INVT_P WM on U3.H 30 For suppor t DPST fun ction

C C

13 Ad d R 419 with 0 ohm For suppor t DPST fun ction
Re ser ve R 420 with 0 ohm For suppor t DPST fun ction
De l JLVDS pin 2 fo r dummy pi n For prevent sh ort B+
23 Mo unt DA5 wi th PJDLC05 For EM I request
23 Re ser ve DA6 wi th PJDLC05 For EM I reqeust
20 Ad d C515,C 516 with 4 70pF For EM I request
28 Mo unt C414~C 437,C461 w ith 100pF For EM I request
17 Ad d R 421 with 3 30K ohm to +3VALW For USB ov er current protect
17 Ad d D 45 with CH 751H-40PT to USB_OC# 0_2 For USB ov er current protect
17 Ch ang e R P7.4 from USB_OC#0_2 to USB_OC #0_2_D For USB ov er current protect
17 Ch ang e U 15.D3 from USB_OC#0 _2 to USB_ OC#0_2_D For USB ov er current protect
26 Ad d N et name to USB_OC#0_ 2 For USB ov er current protect
29 Ch ang e R413,R 414,R415 f rom 0 ohm to FBMA-10 -100505-15 1T For EM I request
30 Ad d C517~ C520 with 0.1uF For ESD reques t
3 /5 12 Re ser ve R42 7 with 0 o hm Fo r Silego s ource chip
Ad d R42 8 with 10K ohm to +3 VS Fo r Silego s ource chip
Ch ang e U4. 54 from H_ STP_PCI# t o H_STP_P CI#_R Fo r Silego s ource chip
3 /5 17 Ad d R42 3,R424 wit h 0 ohm Fo r design c hange
Re ser ve R410, R421 with 330 K ohm For design cha nge
Re ser ve D44,D 45 with C H751H-40PT For design cha nge
19 Ad d R425,R42 6 with 0 o hm For deb ug
30 Re ser ve R422 w ith 0 ohm and PJ22 w ith JUMP_4 3X79 For EM I request

B B

30 Ch ang e H15 t o Non-PTH hole For design cha nge
3 /10 17 Ch ang e R21 4.2,U15.F2 0 from ICH _PCIE_WAK E# to EC_S WI# Fo r wakeup L AN functio n
30 Ad d EC_ SWI# and l ink to bot h U29.103 to U15.F2 0 Fo r wakeup L AN functio n
3 /10 22 Ch ang e CA1 8 from 10u F to 0.1uF Fo r Audio no ise

A A

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/11/17 2009/11/17

Compal Secret Data

Deciphered Date

Title

Size D ocument N umber Re v

2

Date: Sheet of

Compal Electronics, Inc.

ISPD

KAVAA LA-5121P M/B

42 42Tuesday, March 10, 2009

1

1.0