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NM-A181 ZX10 AILZB
Schematic
62 pgs1.04 Mb0

Compal NM-A181 ZX10 AILZA, IdeaPad Z410, IdeaPad Z510, NM-A181 ZX10 AILZB, NM-A181 ZX10 AILZC Schematic

A
1 1
B
C
D
E
LCFC Confidential
AILZA/B/C (ZX10)
MB MA181 Schematics
2 2
nVIDIA N14P-GV2
2012-12-27
3 3
4 4
Security Classification
Security Classification
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
A
B
REV:1.1
Issued Date
Issued Date
Issued Date
2012/12/14
2012/12/14
2012/12/14
C
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2012/12/21
2012/12/21
2012/12/21
D
Title
Title
Title
Cover Page
Cover Page
Cover Page
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
Friday, July 12, 2013
Friday, July 12, 2013
Friday, July 12, 2013
401025
401025
401025
E
of
of
of
161
161
161
1.1
1.1
1.1
A
LCFC confidential
File Name : ZX10
B
PCI-Express 8X Gen3
C
D
E
1 1
N14P-GV2
Page 23,24,25,26,27,32
VRAM 128*16/256*16
DDR3*4
Page 28,29
HDMI Conn.
Edp Conn.
Int. Camera
USB 2.0 Port 0
2 2
Int. MIC Conn.
Page 34 Page 34
Touch Screen
USB 2.0 Port 8
SPI ROM (4MB+2MB)
Page 17
eDP
USB 2.0 1x
USB 2.0 1x
SPI BUS
Intel CPU Haswell 37W/47W
rPGA-947
37.5mm*37.5mm
Page 5,6,7,8,9,10
DMI *4 5GT/s
Intel PCH Lynx point HM86
695 ball FCBGA
FDI *2
20mm*20mm
RJ45 Conn.
3 3
Transform
Page 38Page 38
LAN Realtek RTL8106E/8111G(S)
Page 37
Page 36
PCIe Port 4
CRT Conn.
Sub-board ( for 14")
POWERBOARD
Codec ALC282-CG
Page 43
SPK Conn. (1.5W x 2)
USBBoard
PCIe 1x
VGA
HD Audio
Page 13,14,15,16,17,18,19,20,21,22
LPC BUS
Page 43
Memory BUS (DDR3L) Dual Channel
1.35V DDR3L 1333/1600 MT/s
USB 2.0 2x
USB 3.0 2x
PCIe 1x
USB 2.0 1x
USB 2.0 1x
USB 2.0 1x
SATA Gen3 Port 2
SATA Gen3 Port 4
USB Left
USB 2.0 Port 1 USB 3.0 Port 1 USB 2.0 Port 2 USB 3.0 Port 2
PCIeMini Card WLAN&BT
PCIe Port 5 USB 2.0 Port 10
USB right
USB 2.0 Port 5
Cardreader Genesys GL834L
USB 2.0 Port 4
SATA ODD
SATA Port 2
SATA HDD
SATA Port 4
DDR3-SO-DIMM X2
UP TO 16G
Page 41
Page 40
SD/MMC Conn.
Page 42
Page 42
Page 11,12
USBBoard
Page 45
EC
HP&Mic Combo Conn.
Sub-board ( for 15")
POWERBOARD
USBBoard
4 4
iphone type
USBBoard
Page 45
Touch Pad Int.KBD
ITE ITE8586 128LQFP
Page 44
Thermal Sensor
Page 45 Page 45 Page 39
EMC 1403
LEDBoard
Title
Title
ODDBoard
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
2012/12/14
2012/12/14
2012/12/14
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
2012/12/21
2012/12/21
2012/12/21
Title
Block Diagram
Block Diagram
Block Diagram
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Friday, July 12, 2013
Friday, July 12, 2013
Date: Sheet
Date: Sheet
Date: Sheet
Friday, July 12, 2013
401025
401025
401025
E
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261
261
261
1.1
1.1
1.1
A
B
C
D
E
Voltage Rails
Power Plane
1 1
State
S0
S3
2 2
S3 Battery only
S5 S4/AC Only
S5 S4 Battery only
S5 S4 AC & Battery don't exist
( O --> Means ON , X --> Means OFF )
+3VALW
B+
+5VALW
O
+3V_PCH
OO O
O
O
O X
O
O
O
XX
XX
+1.35V
OO
X
O
X
O
O
O
X
X
X
+5VS +3VS +1.5VS +1.05VS
+0.675VS +CPU_CORE
+VGA_CORE +3.3VS_VGA +1.5VS_VGA
+1.05VS_VGA
X
X
X
X
STATE
Full ON
S1(Power On Suspend)
S3 (Suspend to RAM)
S4 (Suspend to Disk)
S5 (Soft OFF)
SIGNAL
USB Port Table
USB 3.0USB 2.0 Port
XHCI
1
EHCI1
2
EHCI2
SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
HIGH HIGH HIGH HIGH
LOW
LOW
LOW
LOW LOW LOW LOW
3 External USB Port
0
Camera
1
USB Port (Left Side)
2
USB Port (Left Side)
3
Cardreader
4 5
USB Port (Right Side)
6
HIGH
LOWLOWLOW
HIGHHIGHHIGH
HIGH
HIGH
ON
ON
ON
ON
ON
ONONON ON
ON
ON
OFF
OFF
OFF
OFF
OFF
LOW
OFF
OFF
OFF
7
TOUCH PANEL
8 9
Mini Card(WLAN)
10 11 12 13
BOM Structure Table
BTO ItemBOM Structure
AOAC@ OPT@ UMA@
14@ 15@
8106@ 8111G@ 8111GS@ N14PGV2@ GIGA@ Gastube@ NOTS@ GC6@ TS@ @ ME@ XDP@ 37@ 47@ H2@ M2@ M4@ S2@ S4@ M1GB@ M2GB@ S1GB@ S2GB@ H1GB@
AOAC support part
External GPU SKU ID part UMA SKU ID part For Z410 part
For Z510 part
8106E LAN part 8111G LAN Part 8111GS LAN Part N14P GV2 stuff
GIGA LAN Part
Gastube Part No Touch screen part GPU GC6 function part
Touch screen part Not stuff Connector XDP part 37W CPU part 47W CPU part Hynix 2Gb Vram part Micron 2Gb Vram part Micron 4Gb Vram part Samsung 2Gb Vram part Samsung 4Gb Vram part Micron 1GB Vram BOM Micron 2GB Vram BOM samsung 1GB Vram BOM samsung 2GB Vram BOM hynix 1GB Vram BOM
PCIE PORT LIST
SMBUS Control Table
3 3
EC_SMB_DA1
EC_SMB_CK2 EC_SMB_DA2
PCH_SMBCLK PCH_SMBDATA
EC SM Bus1 address
4 4
Device
Smart Battery Charger
SOURCE
IT8586EEC_SMB_CK1
+3VALW
IT8586E
+3VS
+3V_PCH +3VS +3VS
VGA BATT SODIMM
X
X
V
+3VS_VGA
PCH
XXX X
IT8586E
V
V
+3VS +3VS
EC SM Bus2 address
Device
0001 011X b 0001 0010 b
A
Thermal Sensor EMC1403-2
VGA PCH
WLAN
Thermal
WiMAX
Sensor
XXV
X
X
VV
Address
1001_101xb 0x9E 0x96
V
X
V
+3V_PCH
+3V_PCH
PCH SM Bus address
Device Address
DDR DIMMA DDR DIMMB Wlan TP
B
PCH
TP Module
XX
V
X
V
+3VS
charger
V
X
X
0xA0 0xA2 Rsvd 0x2C for Synaptics
0x15 for ELAN vendor
XDP
+3VS
X
X
V
Port Device
1 2 3 4
LAN
5
WLAN
6 7 8
C
PCIE 3
PCIE 3
FixedSignals
PCIE
PCIE
4
5
PCIE
PCIE
4
5
2012/12/21
2012/12/21
2012/12/21
PCIE 6
PCIE 6
*
FixedSignals
USB3
USB3
1
2
HM86
USB3
USB3
1
2012/12/14
2012/12/14
2012/12/14
2
HM87 QM87
SoftStrap:(USB3P4_PCIEP2_MODE) 00:PCIeLane2isstaticallyassignedtoPCIEExpress(orGbE) 01:PCIeLane2isstaticallyassignedtoUSB3Port4
SoftStrap:(USB3P3_PCIEP1_MODE) 00:PCIeLane1isstaticallyassignedtoPCIEExpress(orGbE) 01:PCIeLane1isstaticallyassignedtoUSB3Port3
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MuxedSignals
NA PCIE
NA NA NA
USB3
USB3
5
6
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
PCIE
1
2
(00)
(00)
USB3
USB3
3
4
(01) (0b) (0b)
(01)
PCIE
PCIE
1
2
USB3
USB3
4
5
Deciphered Date
Deciphered Date
Deciphered Date
D
SATA 6Gb/s 5
PCIE 2
SATA 6Gb/s 5 PCIE 3
Friday, July 12, 2013
Friday, July 12, 2013
Friday, July 12, 2013
SATA 3Gb/s 0
SATA 6Gb/s 0
FixedSignals
SATA 6Gb/s 1
GPIO16,49
11
00PCIE1,PECI2
401025
401025
401025
E
SATA 3Gb/s 2
SATA 3Gb/s 2
MuxedSignals
PCIE
PCIE
SATA
7
8
6Gb/s 4
(1b) (1b)
PCIE 1
PCIE
PCIE
SATA
7
8
6Gb/s 4 PCIE 2
Config
SATA4,SATA5
Title
Title
Title
Notes List
Notes List
Notes List
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
SATA 3Gb/s 3
361
361
361
1.1
1.1
1.1
of
of
of
5
4
3
2
1
VGA and GDDR3 Voltage Rails (N14P GPIO)
GPIO I/O ACTIVE Function Description
D D
GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10
C C
GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19
IN FB Clamp monitor­OUT
N/A
OUT
N/A
OUT
N/A
OUT
N/A N/A
-
OUT OUT
N/A
I/O
­I/O N/A OUT
N/A
IN OUT IN
N/A
IN
N/A
OUT
N/A
IN
N/A
IN
N/A
IN
N/A
Active low FB Clamp toggle request
Thermal Catastrophic Over Temperature
2.2K Pull-up
GPU Core VDD PWM control signal-OUT AC Power Detect Input Phase Shedding-
(10K pull High)
Performance Mode P0 TDP at Tj = 102 C* (DDR3)
GPU Mem NVCLK (4) (1,5) (6)
(W) (W) (MHz)
Products
N14P 64bit
25W TBD 32 TBD 1.7 2.55 TBD TBD 1.98 2.1 TBD TBD TBD TBD TBD TBD 1GB/2GB DDR3
Physical Strapping pin
ROM_SCLK ROM_SI ROM_SO FB[0] STRAP0 STRAP1 STRAP2 STRAP3 STRAP4
GPU
Power Rail
+3VS_VGA +3VS_VGA +3VS_VGA +3VS_VGA +3VS_VGA +3VS_VGA +3VS_VGA +3VS_VGA
Device ID
/MCLK NVVDD
(V) (A) (W) (A) (W)
1000MHz TBD
Logical Strapping Bit3
PCI_DEVID[4]
FB[1]
3GIO_PAD_CFG_ADR[2] 3GIO_PAD_CFG_ADR[1]3GIO_PAD_CFG_ADR[3] PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0] SOR3_EXPOSED
RESERVED PCIE_SPEED_
SMB_ALT_ADDR
(ROM_SO Bit 1)
setting
N14P-GV2 0x1292
ROM_SO ROM_SCLKGPU STRAP2STRAP1STRAP0
ROM_SI
N14P-GV2 PD 45.3K
TBD PU 4.99K PU 45.3K
PU 45.3KPU 4.99K PD 15K
FBVDDQ PCI Express I/O and
FBVDD
(GPU+Mem) (1.5V)(1.5V)
(A) (W) (W)(A) (W) (W) (W)(mA) (mA) (mA)
Logical Strapping Bit2
SUB_VENDOR
USER[2] USER[1] USER[0]USER[3]
SOR2_EXPOSED SOR1_EXPOSED
CHANGE_GEN3
I2C Slave addrees ID
0
1
0x9E
0x9C
(1.05V)
Logical Strapping Bit1
PCI_DEVID5] RAM_CFG[1]RAM_CFG[3] RAM_CFG[2]
PLLVDD
I/O and PLLVDD
Logical Strapping Bit0
PEX_PLL_EN_TERM RAM_CFG[0]
VGA_DEVICESMB_ALT_ADDR
3GIO_PAD_CFG_ADR[0]
SOR0_EXPOSED
PCIE_MAX_SPEED DP_PLL_VDD33V
(Default)
STRAP3
STRAP4
PD 4.99K
Other (3.3V)(1.05V)(1.8V)
B B
A A
5
+3VS_VGA
+VGA_CORE
+1.5VS_VGA
+1.05VS_VGA
Other Power rail
+3VS_VGA
tNVVDD >0
tFBVDDQ >0
tPEX_VDD >0
1. all power rail ramp up time should be larger than 40us
Tpower-off <10ms
1.all GPU power rails should be turned off within 10ms
2. Optimus system VDD33 avoids drop down earlier than NVDD and FBVDDQ
4
GPU
FB Memory (DDR3)
Samsung 1GHz
Micron 1GMHz
Hynix 1GMHz
Samsung 900MHz
Micron 900MHz
Security Classification
Security Classification
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
3
K4W2G1646E-BC1A
128M x 16
MT41J128M16JT-093G:K
128M x 16
128M x 16
K4W4G1646B-HC11
256M x 16
MT41K256M16HA-107G:E
256M x 16
Issued Date
Issued Date
Issued Date
2012/12/14
2012/12/14
2012/12/14
N14P_GV2
ROM_SI
0x7 PD 45.3K
0x5 PD 30.1K
0x4H5TC2G63FFR-11C PD 24.9K
0x3 PD 20K
0x1 PD 10K
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2012/12/21
2012/12/21
2012/12/21
Title
Title
Title
VGA Notes List
VGA Notes List
VGA Notes List
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Friday, July 12, 2013
Friday, July 12, 2013
Friday, July 12, 2013
Date: Sheet
Date: Sheet
Date: Sheet
401025
401025
401025
1
of
of
of
461
461
461
1.1
1.1
1.1
5
4
3
2
+VCCIOA_OUT
1
D D
JCPU1A
DMI_CRX_PTX_N015 DMI_CRX_PTX_N115 DMI_CRX_PTX_N215 DMI_CRX_PTX_N315
DMI_CRX_PTX_P015 DMI_CRX_PTX_P115 DMI_CRX_PTX_P215 DMI_CRX_PTX_P315
DMI_CTX_PRX_N015 DMI_CTX_PRX_N115 DMI_CTX_PRX_N215 DMI_CTX_PRX_N315
DMI_CTX_PRX_P015 DMI_CTX_PRX_P115 DMI_CTX_PRX_P215
C C
FDI_CSYNC15 FDI_INT15
B B
DMI_CTX_PRX_P315
1 2
RC2 0_0402_5%@
1 2
RC3 0_0402_5%@
Change RC2,RC3 to 0ohm jump
DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3
DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3
DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3
DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3
FDI_CSYNC_R FDI_INT_R
D21
DMI_RXN_0
C21
DMI_RXN_1
B21
DMI_RXN_2
A21
DMI_RXN_3
D20
DMI_RXP_0
C20
DMI_RXP_1
B20
DMI_RXP_2
A20
DMI_RXP_3
D18
DMI_TXN_0
C17
DMI_TXN_1
B17
DMI_TXN_2
A17
DMI_TXN_3
D17
DMI_TXP_0
C18
DMI_TXP_1
B18
DMI_TXP_2
A18
DMI_TXP_3
H29
FDI_CSYNC
J29
DISP_INT
FOX_PZ94726-3641-41H_HASWELL
ME@
Haswell rPGA EDS
FDIDMI
1 OF 9
PEG
PEG_RCOMP
PEG_RXN_0 PEG_RXN_1 PEG_RXN_2 PEG_RXN_3 PEG_RXN_4 PEG_RXN_5 PEG_RXN_6 PEG_RXN_7 PEG_RXN_8
PEG_RXN_9 PEG_RXN_10 PEG_RXN_11 PEG_RXN_12 PEG_RXN_13 PEG_RXN_14 PEG_RXN_15
PEG_RXP_0
PEG_RXP_1
PEG_RXP_2
PEG_RXP_3
PEG_RXP_4
PEG_RXP_5
PEG_RXP_6
PEG_RXP_7
PEG_RXP_8
PEG_RXP_9 PEG_RXP_10 PEG_RXP_11 PEG_RXP_12 PEG_RXP_13 PEG_RXP_14 PEG_RXP_15
PEG_TXN_0
PEG_TXN_1
PEG_TXN_2
PEG_TXN_3
PEG_TXN_4
PEG_TXN_5
PEG_TXN_6
PEG_TXN_7
PEG_TXN_8
PEG_TXN_9 PEG_TXN_10 PEG_TXN_11 PEG_TXN_12 PEG_TXN_13 PEG_TXN_14 PEG_TXN_15
PEG_TXP_0
PEG_TXP_1
PEG_TXP_2
PEG_TXP_3
PEG_TXP_4
PEG_TXP_5
PEG_TXP_6
PEG_TXP_7
PEG_TXP_8
PEG_TXP_9 PEG_TXP_10 PEG_TXP_11 PEG_TXP_12 PEG_TXP_13 PEG_TXP_14 PEG_TXP_15
E23
PEG_COMP
M29
PCIE_CRX_GTX_N0
K28
PCIE_CRX_GTX_N1
M31
PCIE_CRX_GTX_N2
L30
PCIE_CRX_GTX_N3
M33
PCIE_CRX_GTX_N4
L32
PCIE_CRX_GTX_N5
M35
PCIE_CRX_GTX_N6
L34
PCIE_CRX_GTX_N7
E29
PCIE_CRX_GTX_N8
D28
PCIE_CRX_GTX_N9
E31
PCIE_CRX_GTX_N10
D30
PCIE_CRX_GTX_N11
E35
PCIE_CRX_GTX_N12
D34
PCIE_CRX_GTX_N13
E33
PCIE_CRX_GTX_N14
E32
PCIE_CRX_GTX_N15
L29
PCIE_CRX_GTX_P0
L28
PCIE_CRX_GTX_P1
L31
PCIE_CRX_GTX_P2
K30
PCIE_CRX_GTX_P3
L33
PCIE_CRX_GTX_P4
K32
PCIE_CRX_GTX_P5
L35
PCIE_CRX_GTX_P6
K34
PCIE_CRX_GTX_P7
F29
PCIE_CRX_GTX_P8
E28
PCIE_CRX_GTX_P9
F31
PCIE_CRX_GTX_P10
E30
PCIE_CRX_GTX_P11
F35
PCIE_CRX_GTX_P12
E34
PCIE_CRX_GTX_P13
F33
PCIE_CRX_GTX_P14
D32
PCIE_CRX_GTX_P15
H35
PCIE_CTX_GRX_N0
H34
PCIE_CTX_GRX_N1
J33
PCIE_CTX_GRX_N2
H32
PCIE_CTX_GRX_N3
J31
PCIE_CTX_GRX_N4
G30
PCIE_CTX_GRX_N5
C33
PCIE_CTX_GRX_N6
B32
PCIE_CTX_GRX_N7
B31
PCIE_CTX_GRX_N8
A30
PCIE_CTX_GRX_N9
B29
PCIE_CTX_GRX_N10
A28
PCIE_CTX_GRX_N11
B27
PCIE_CTX_GRX_N12
A26
PCIE_CTX_GRX_N13
B25
PCIE_CTX_GRX_N14
A24
PCIE_CTX_GRX_N15
J35
PCIE_CTX_GRX_P0
G34
PCIE_CTX_GRX_P1
H33
PCIE_CTX_GRX_P2
G32
PCIE_CTX_GRX_P3
H31
PCIE_CTX_GRX_P4
H30
PCIE_CTX_GRX_P5
B33
PCIE_CTX_GRX_P6
A32
PCIE_CTX_GRX_P7
C31
PCIE_CTX_GRX_P8
B30
PCIE_CTX_GRX_P9
C29
PCIE_CTX_GRX_P10
B28
PCIE_CTX_GRX_P11
C27
PCIE_CTX_GRX_P12
B26
PCIE_CTX_GRX_P13
C25
PCIE_CTX_GRX_P14
B24
PCIE_CTX_GRX_P15
PCIE_CRX_GTX_N[0..15] 23
PCIE_CRX_GTX_P[0..15] 23
1 2
CC1 0.22U_0402_10V6K@
1 2
CC2 0.22U_0402_10V6K@
1 2
CC3 0.22U_0402_10V6K@
1 2
CC4 0.22U_0402_10V6K@
1 2
CC5 0.22U_0402_10V6K@
1 2
CC6 0.22U_0402_10V6K@
1 2
CC7 0.22U_0402_10V6K@
1 2
CC8 0.22U_0402_10V6K@
1 2
CC9 0.22U_0402_10V6KOPT@
1 2
CC10 0.22U_0402_10V6KOPT@
1 2
CC11 0.22U_0402_10V6KOPT@
1 2
CC12 0.22U_0402_10V6KOPT@
1 2
CC13 0.22U_0402_10V6KOPT@
1 2
CC14 0.22U_0402_10V6KOPT@
1 2
CC15 0.22U_0402_10V6KOPT@
1 2
CC16 0.22U_0402_10V6KOPT@
1 2
CC17 0.22U_0402_10V6K@
1 2
CC18 0.22U_0402_10V6K@
1 2
CC19 0.22U_0402_10V6K@
1 2
CC20 0.22U_0402_10V6K@
1 2
CC21 0.22U_0402_10V6K@
1 2
CC22 0.22U_0402_10V6K@
1 2
CC23 0.22U_0402_10V6K@
1 2
CC24 0.22U_0402_10V6K@
1 2
CC25 0.22U_0402_10V6KOPT@
1 2
CC26 0.22U_0402_10V6KOPT@
1 2
CC27 0.22U_0402_10V6KOPT@
1 2
CC28 0.22U_0402_10V6KOPT@
1 2
CC29 0.22U_0402_10V6KOPT@
1 2
CC30 0.22U_0402_10V6KOPT@
1 2
CC31 0.22U_0402_10V6KOPT@
1 2
CC32 0.22U_0402_10V6KOPT@
PCIE_CTX_C_GRX_N0 PCIE_CTX_C_GRX_N1 PCIE_CTX_C_GRX_N2 PCIE_CTX_C_GRX_N3 PCIE_CTX_C_GRX_N4 PCIE_CTX_C_GRX_N5 PCIE_CTX_C_GRX_N6 PCIE_CTX_C_GRX_N7 PCIE_CTX_C_GRX_N8 PCIE_CTX_C_GRX_N9 PCIE_CTX_C_GRX_N10 PCIE_CTX_C_GRX_N11 PCIE_CTX_C_GRX_N12 PCIE_CTX_C_GRX_N13 PCIE_CTX_C_GRX_N14 PCIE_CTX_C_GRX_N15 PCIE_CTX_C_GRX_P0 PCIE_CTX_C_GRX_P1 PCIE_CTX_C_GRX_P2 PCIE_CTX_C_GRX_P3 PCIE_CTX_C_GRX_P4 PCIE_CTX_C_GRX_P5 PCIE_CTX_C_GRX_P6 PCIE_CTX_C_GRX_P7 PCIE_CTX_C_GRX_P8 PCIE_CTX_C_GRX_P9 PCIE_CTX_C_GRX_P10 PCIE_CTX_C_GRX_P11 PCIE_CTX_C_GRX_P12 PCIE_CTX_C_GRX_P13 PCIE_CTX_C_GRX_P14 PCIE_CTX_C_GRX_P15
PEG_COMP
CADNote: Tracewidth=12mils,Spacing=15mil Maxlength=400mils.
PEG Static Lane Reversal - CFG2 is for the 16x
CFG2
1 2
RC1 24.9_0402_1%
1: Normal Operation; Lane # definition matches socket pin map definition
*
0:Lane Reversed
PCIE_CTX_C_GRX_N[0..15] 23
PCIE_CTX_C_GRX_P[0..15] 23
A A
Title
Title
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
3
2012/12/14
2012/12/14
2012/12/14
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2012/12/21
2012/12/21
2012/12/21
Title
CPU (1/7) DMI, FDI, PEG
CPU (1/7) DMI, FDI, PEG
CPU (1/7) DMI, FDI, PEG
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Friday, July 12, 2013
Friday, July 12, 2013
Date: Sheet
Date: Sheet
Date: Sheet
Friday, July 12, 2013
401025
401025
401025
1
of
of
of
561
561
561
1.1
1.1
1.1
5
4
3
2
1
+1.05VS
1 2
RC4 0_0603_5%@
D D
.1U_0402_10V6-K
ReserveforDesignGuideandCRBrecommended.
Buffered Reset to CPU
C C
CPU_PLTRST#19
1.05V
RC22 0_0402_5%@
1 2
Change RC22 to 0ohm jump
B B
+3V_PCH
SM_DRAMPWROKwithDDRPowerGatingTopology
+3VALW
PM_DRAM_PWRGD15
RC79 0_0402_5%@ RC78 0_0402_5%@
SYS_PWROK15,44
VDDQ_PGOOD44,55
RC77
RC39
.01U_0402_16V7-K
Change RC77 to 0ohm jump
A A
CC33
@
12 12
RC35
0_0402_5%
1 2
@
0_0402_5%
@
1 2
10K_0402_5%
CC40
+VCCST
1
1
CC34
4.7U_0603_6.3V6K
@
2
2
H_PROCHOT#44,51,52
CLK_CPU_DPLL#16 CLK_CPU_DPLL16 CLK_CPU_SSC_DPLL#16 CLK_CPU_SSC_DPLL16
BUF_CPU_RST#
ForESDconcern,pleaseputnearCPU
ForESD
+3VDRAM
200_0402_5%
100K_0402_5%
12
12
RC32
RC31
@
@
@
12
1
@
2
CC37
5
1
P
B
2
A
G
3
74AHC1G09GW_TSSOP5
@
RC41 0_0402_5%
RUN_ON_CPU1.5VS3#10
+VCCIO_OUT
12
RC7
62_0402_5%
H_PM_SYNC15 H_CPUPWRGD19
Change RC11,RC13,RC15,RC16,RC17 to 0ohm jump
1
CC35 220P_0402_50V7K
2
@
1 2
@
.1U_0402_10V6-K
4
Y
UC1
12
2
G
+VCCST
1 2
RC9 56_0402_5%
1 2
RC11 0_0402_5%@
1 2
RC13 0_0402_5%@
1 2
RC15 0_0402_5%@
1 2
RC16 0_0402_5%@
1 2
RC17 0_0402_5%@
CLK_CPU_DMI#16 CLK_CPU_DMI16
1
CC36 220P_0402_50V7K
2
@
+1.35V_CPU_VDDQ
RC42
39_0402_5%
@
1 2 13
D
QC2
@
S
2N7002KW_SOT323-3
PAD@
1
TC81
H_PECI44
H_THRMTRIP#19
H_PM_SYNC VCCPWRGOOD_0_R PM_DRAM_PWRGD_CPU BUF_CPU_RST#
CPU_DPLL# CPU_DPLL CPU_SSC_DPLL# CPU_SSC_DPLL CLK_CPU_DMI# CLK_CPU_DMI
SSCCLOCKTERMINATION,IFNOTUSED,stuffRC25,RC27
12
RC33
1.8K_0402_1%
@
1 2
RC36
0_0402_5%
Change RC36 to 0ohm jump
12
RC40
3.3K_0402_1%
H_CATERR# H_PECI
H_PROCHOT#_R H_THRMTRIP#
PM_DRAM_PWRGD_CPURUNPWROK_AND
AP32
AN32 AR27
AK31 AM30 AM35
AT28
AL34 AC10
AT26
G28 H28 F27 E27 D26 E26
+VCCIO_OUT
@
RC25 10K_0402_5%
@
RC27 10K_0402_5%
JCPU1B
SKTOCC CATERR
PECI FC_AK31 PROCHOT THERMTRIP
PM_SYNC PWRGOOD SM_DRAMPWROK PLTRSTIN
DPLL_REF_CLKN DPLL_REF_CLKP SSC_DPLL_REF_CLKN SSC_DPLL_REF_CLKP BCLKN BCLKP
FOX_PZ94726-3641-41H_HASWELL
ME@
12
CPU_SSC_DPLLVCCPWRGOOD_0_RBUF_CPU_RST#
12
CPU_SSC_DPLL#
Haswell rPGA EDS
MISC
THERMAL CLOCK
PWR
DRAMRST_CNTRL_PCH17
DRAMRST_CNTRL7
DRAMRST_CNTRL_EC44
2 OF 9
AP3
SM_RCOMP_0 SM_RCOMP_1
DDR3L
SM_RCOMP_2 SM_DRAMRST
PRDY PREQ
TCK TMS
TRST
JTAG
TDO DBR
BPM_N_0 BPM_N_1 BPM_N_2 BPM_N_3 BPM_N_4 BPM_N_5 BPM_N_6 BPM_N_7
CADNote: AvoidstubinthePWRGDpath whileplacingresistorsRC11&RC26
RC37 0_0402_5%
RC38 0_0402_5%
AR3 AP2 AN3
AR29 AT29 AM34 AN33 AM33 AM31
TDI
AL33 AP33
AR30 AN31 AN29 AP31 AP30 AN28 AP29 AP28
4.99K_0402_1%
@
1 2
1 2
@
SM_RCOMP0 SM_RCOMP1 SM_RCOMP2 H_DRAMRST#
XDP_PRDY# XDP_PREQ# XDP_TCLK XDP_TMS XDP_TRST# XDP_TDI_R XDP_TDO_R XDP_DBRESET#_R
XDP_BPM0 XDP_BPM1 XDP_BPM2 XDP_BPM3 XDP_BPM4 XDP_BPM5 XDP_BPM6 XDP_BPM7
RC34
ReserveforDeepS3
@
@ @ @ @ @ @ @ @
VCCPWRGOOD_0_R
12
RC26 10K_0402_5%
@
1 2
DRAMRST_CNTRL
1
1 1 1 1 1 1 1 1
S
RC28 0_0402_5%@
G
TC59
PAD
TC61
PAD
TC60
PAD
TC4
PAD
TC5
PAD
TC6
PAD
TC7
PAD
TC8
PAD
TC9
PAD
Change RC28 to 0ohm jump
1 2
D
13
DDR3_DRAMRST#_RH_DRAMRST#
QC1 2N7002KW_SOT323-3
@
2
1
CC39
0.047U_0402_16V7K
@
2
+1.35V
DDR3COMPENSATIONSIGNALS
SM_RCOMP0 SM_RCOMP1 SM_RCOMP2
CADNote: Tracewidth=12~15mil,Spcing=20mils Maxtracelength=500mil
1 2
RC5 100_0402_1%
1 2
RC6 75_0402_1%
1 2
RC8 100_0402_1%
PU/PDforJTAGsignals
1
CC38 .1U_0402_10V6-K
@
2
12
12 12 12 12
12 12
DDR3_DRAMRST# 11,12
XDP_DBRESET#_R
XDP_TMS XDP_TDI_R XDP_PREQ# XDP_TDO_R
XDP_TCLK XDP_TRST#
12
RC29 1K_0402_5%
@
RC30
1 2
1K_0402_5%
@
RC14 1K_0402_1%
RC18 51_0402_1%@ RC19 51_0402_1%@ RC20 51_0402_1%@ RC21 51_0402_1%@
RC23 51_0402_1%@ RC24 51_0402_1%@
+3VS
+1.05VS
Title
Title
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
3
2012/12/14
2012/12/14
2012/12/14
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2012/12/21
2012/12/21
2012/12/21
Title
CPU (2/7) PM, XDP, CLK
CPU (2/7) PM, XDP, CLK
CPU (2/7) PM, XDP, CLK
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Friday, July 12, 2013
Friday, July 12, 2013
Date: Sheet
Date: Sheet
Date: Sheet
Friday, July 12, 2013
401025
401025
401025
1
of
of
of
661
661
661
1.1
1.1
1.1
5
4
3
2
1
Haswell rPGA EDS
@
1
TC10 PAD
DDRA_CLK0#11 DDRA_CLK011 DDRA_CKE011 DDRA_CLK1#11
D D
C C
B B
DDRA_CLK111 DDRA_CKE111
DDRA_CS0#11 DDRA_CS1#11
DDRA_ODT011 DDRA_ODT111
DDRA_BS0#11 DDRA_BS1#11 DDRA_BS2#11
DDRA_RAS#11 DDRA_WE#11 DDRA_CAS#11
DDRA_MA[0..15]11
DDRA_DQS#[0..7]11
DDRA_DQS[0..7]11
DDRA_MA0 DDRA_MA1 DDRA_MA2 DDRA_MA3 DDRA_MA4 DDRA_MA5 DDRA_MA6 DDRA_MA7 DDRA_MA8 DDRA_MA9 DDRA_MA10 DDRA_MA11 DDRA_MA12 DDRA_MA13 DDRA_MA14 DDRA_MA15
DDRA_DQS#0 DDRA_DQS#1 DDRA_DQS#2 DDRA_DQS#3 DDRA_DQS#4 DDRA_DQS#5 DDRA_DQS#6 DDRA_DQS#7 DDRA_DQS0 DDRA_DQS1 DDRA_DQS2 DDRA_DQS3 DDRA_DQS4 DDRA_DQS5 DDRA_DQS6 DDRA_DQS7 +VREF_CA_R
JCPU1C
AC7
RSVD27
U4
SA_CKN0
V4
SA_CKP0
AD9
SA_CKE_0
U3
SA_CKN1
V3
SA_CKP1
AC9
SA_CKE_1
U2
SA_CKN2
V2
SA_CKP2
AD8
SA_CKE_2
U1
SA_CKN3
V1
SA_CKP3
AC8
SA_CKE_3
M7
SA_CS_N_0
L9
SA_CS_N_1
M9
SA_CS_N_2
M10
SA_CS_N_3
M8
SA_ODT_0
L7
SA_ODT_1
L8
SA_ODT_2
L10
SA_ODT_3
V5
SA_BS_0
U5
SA_BS_1
AD1
SA_BS_2
V10
VSS330
U6
SA_RAS
U7
SA_WE
U8
SA_CAS
V8
SA_MA_0
AC6
SA_MA_1
V9
SA_MA_2
U9
SA_MA_3
AC5
SA_MA_4
AC4
SA_MA_5
AD6
SA_MA_6
AC3
SA_MA_7
AD5
SA_MA_8
AC2
SA_MA_9
V6
SA_MA_10
AC1
SA_MA_11
AD4
SA_MA_12
V7
SA_MA_13
AD3
SA_MA_14
AD2
SA_MA_15
AP15
SA_DQS_N_0
AP8
SA_DQS_N_1
AJ8
SA_DQS_N_2
AF3
SA_DQS_N_3
J3
SA_DQS_N_4
E2
SA_DQS_N_5
C5
SA_DQS_N_6
C11
SA_DQS_N_7
AP14
SA_DQS_P_0
AP9
SA_DQS_P_1
AK8
SA_DQS_P_2
AG3
SA_DQS_P_3
H3
SA_DQS_P_4
E3
SA_DQS_P_5
C6
SA_DQS_P_6
C12
SA_DQS_P_7
FOX_PZ94726-3641-41H_HASWELL
ME@
SA_DIMM_VREFDQ SB_DIMM_VREFDQ
3 OF 9
SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8
SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63
SM_VREF
AR15 AT14 AM14 AN14 AT15 AR14 AN15 AM15 AM9 AN9 AM8 AN8 AR9 AT9 AR8 AT8 AJ9 AK9 AJ6 AK6 AJ10 AK10 AJ7 AK7 AF4 AF5 AF1 AF2 AG4 AG5 AG1 AG2 J1 J2 J5 H5 H2 H1 J4 H4 F2 F1 D2 D3 D1 F3 C3 B3 B5 E6 A5 D6 D5 E5 B6 A6 E12 D12 B11 A11 E11 D11 B12 A12 AM3 F16 F13
DDRA_DQ0 DDRA_DQ1 DDRA_DQ2 DDRA_DQ3 DDRA_DQ4 DDRA_DQ5 DDRA_DQ6 DDRA_DQ7 DDRA_DQ8 DDRA_DQ9 DDRA_DQ10 DDRA_DQ11 DDRA_DQ12 DDRA_DQ13 DDRA_DQ14 DDRA_DQ15 DDRA_DQ16 DDRA_DQ17 DDRA_DQ18 DDRA_DQ19 DDRA_DQ20 DDRA_DQ21 DDRA_DQ22 DDRA_DQ23 DDRA_DQ24 DDRA_DQ25 DDRA_DQ26 DDRA_DQ27 DDRA_DQ28 DDRA_DQ29 DDRA_DQ30 DDRA_DQ31 DDRA_DQ32 DDRA_DQ33 DDRA_DQ34 DDRA_DQ35 DDRA_DQ36 DDRA_DQ37 DDRA_DQ38 DDRA_DQ39 DDRA_DQ40 DDRA_DQ41 DDRA_DQ42 DDRA_DQ43 DDRA_DQ44 DDRA_DQ45 DDRA_DQ46 DDRA_DQ47 DDRA_DQ48 DDRA_DQ49 DDRA_DQ50 DDRA_DQ51 DDRA_DQ52 DDRA_DQ53 DDRA_DQ54 DDRA_DQ55 DDRA_DQ56 DDRA_DQ57 DDRA_DQ58 DDRA_DQ59 DDRA_DQ60 DDRA_DQ61 DDRA_DQ62 DDRA_DQ63
+V_DDR_REFA_R +V_DDR_REFB_R
DDRA_DQ[0..63] 11
+VREF_CA_R
@
1
TC11 PAD
DDRB_CLK0#12 DDRB_CLK012 DDRB_CKE012 DDRB_CLK1#12 DDRB_CLK112 DDRB_CKE112
DDRB_CS0#12 DDRB_CS1#12
DDRB_ODT012 DDRB_ODT112
DDRB_BS0#12 DDRB_BS1#12 DDRB_BS2#12
DDRB_RAS#12 DDRB_WE#12 DDRB_CAS#12
DDRB_MA[0..15]12
DDRB_DQS#[0..7]12
DDRB_DQS[0..7]12
DDRB_MA0 DDRB_MA1 DDRB_MA2 DDRB_MA3 DDRB_MA4 DDRB_MA5 DDRB_MA6 DDRB_MA7 DDRB_MA8 DDRB_MA9 DDRB_MA10 DDRB_MA11 DDRB_MA12 DDRB_MA13 DDRB_MA14 DDRB_MA15
DDRB_DQS#0 DDRB_DQS#1 DDRB_DQS#2 DDRB_DQS#3 DDRB_DQS#4 DDRB_DQS#5 DDRB_DQS#6 DDRB_DQS#7 DDRB_DQS0 DDRB_DQS1 DDRB_DQS2 DDRB_DQS3 DDRB_DQS4 DDRB_DQS5 DDRB_DQS6 DDRB_DQS7
AG8
Y4
AA4
AF10
Y3
AA3
AG10
Y2 AA2 AG9
Y1 AA1 AF9
P4
R2
P3
P1
R4
R3
R1
P2
R7
P8 AA9
R10
R6
P6
P7
R8
Y5
Y10
AA5
Y7 AA6
Y6 AA7
Y8
AA10
R9
Y9 AF7
P9 AA8 AG7
AP18 AP11
AP5
AJ3
L3
H9
C8 C14
AP17 AP12
AP6 AK3
M3
H8
C9 C15
FOX_PZ94726-3641-41H_HASWELL
ME@
JCPU1D
RSVD28 SB_CKN0 SB_CKP0 SB_CKE_0 SB_CKN1 SB_CKP1 SB_CKE_1 SB_CKN2 SB_CKP2 SB_CKE_2 SB_CKN3 SB_CKP3 SB_CKE_3
SB_CS_N_0 SB_CS_N_1 SB_CS_N_2 SB_CS_N_3
SB_ODT_0 SB_ODT_1 SB_ODT_2 SB_ODT_3 SB_BS_0 SB_BS_1 SB_BS_2
VSS331 SB_RAS SB_WE SB_CAS
SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8 SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14 SB_MA_15
SB_DQS_N_0 SB_DQS_N_1 SB_DQS_N_2 SB_DQS_N_3 SB_DQS_N_4 SB_DQS_N_5 SB_DQS_N_6 SB_DQS_N_7 SB_DQS_P_0 SB_DQS_P_1 SB_DQS_P_2 SB_DQS_P_3 SB_DQS_P_4 SB_DQS_P_5 SB_DQS_P_6 SB_DQS_P_7
Haswell rPGA EDS
4 OF 9
SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8
SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63
AR18 AT18 AM17 AM18 AR17 AT17 AN17 AN18 AT12 AR12 AN12 AM11 AT11 AR11 AM12 AN11 AR5 AR6 AM5 AM6 AT5 AT6 AN5 AN6 AJ4 AK4 AJ1 AJ2 AM1 AN1 AK2 AK1 L2 M2 L4 M4 L1 M1 L5 M5 G7 J8 G8 G9 J7 J9 G10 J10 A8 B8 A9 B9 D8 E8 D9 E9 E15 D15 A15 B15 E14 D14 A14 B14
DDRB_DQ0 DDRB_DQ1 DDRB_DQ2 DDRB_DQ3 DDRB_DQ4 DDRB_DQ5 DDRB_DQ6 DDRB_DQ7 DDRB_DQ8 DDRB_DQ9 DDRB_DQ10 DDRB_DQ11 DDRB_DQ12 DDRB_DQ13 DDRB_DQ14 DDRB_DQ15 DDRB_DQ16 DDRB_DQ17 DDRB_DQ18 DDRB_DQ19 DDRB_DQ20 DDRB_DQ21 DDRB_DQ22 DDRB_DQ23 DDRB_DQ24 DDRB_DQ25 DDRB_DQ26 DDRB_DQ27 DDRB_DQ28 DDRB_DQ29 DDRB_DQ30 DDRB_DQ31 DDRB_DQ32 DDRB_DQ33 DDRB_DQ34 DDRB_DQ35 DDRB_DQ36 DDRB_DQ37 DDRB_DQ38 DDRB_DQ39 DDRB_DQ40 DDRB_DQ41 DDRB_DQ42 DDRB_DQ43 DDRB_DQ44 DDRB_DQ45 DDRB_DQ46 DDRB_DQ47 DDRB_DQ48 DDRB_DQ49 DDRB_DQ50 DDRB_DQ51 DDRB_DQ52 DDRB_DQ53 DDRB_DQ54 DDRB_DQ55 DDRB_DQ56 DDRB_DQ57 DDRB_DQ58 DDRB_DQ59 DDRB_DQ60 DDRB_DQ61 DDRB_DQ62 DDRB_DQ63
DDRB_DQ[0..63] 12
DRAMRST_CNTRL6
+VREF_DQ_DIMMA_R +VREF_DQ_DIMMB_R
A A
5
4
Change RC43,RC44 to 0ohm jump
DRAMRST_CNTRL
2N7002KW_SOT323-3
RC43 0_0402_5%@ RC44 0_0402_5%@
2N7002KW_SOT323-3
DRAMRST_CNTRL
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
QC3
1 3
D
1 2 1 2
1 3
D
QC4
3
2
G
@
S
+V_DDR_REFA_R +V_DDR_REFB_R
12
S
@
G
2
2012/12/14
2012/12/14
2012/12/14
RC45
1K_0402_1%
@
12
RC46 1K_0402_1%
@
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2012/12/21
2012/12/21
2012/12/21
Title
Title
Title
CPU (3/7) DDRIII
CPU (3/7) DDRIII
CPU (3/7) DDRIII
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Friday, July 12, 2013
Friday, July 12, 2013
Date: Sheet
Date: Sheet
Date: Sheet
Friday, July 12, 2013
401025
401025
401025
1
of
of
of
761
761
761
1.1
1.1
1.1
5
4
3
2
1
+VCCIO_OUT
2
G
12
RC47 10K_0402_5%
1 2
13
D
S
+VCCIOA_OUT
RC4924.9_0402_1%
EDP_HPD_IN#
QC5 2N7002KW_SOT323-3
HPDINVERSIONFOREDP
D D
HDMI D2 HDMI D1 HDMI D0 HDMI CLK
@
1 2
PCH_PWROK15,44
C C
RC50
6.04K_0402_1%
HDMI_TX2-35 HDMI_TX1-35 HDMI_TX0-35 HDMI_CLK-35
VCCST_PWRGD
12
RC75
2.67K_0402_1%
@
HDMI_TX2+35 HDMI_TX1+35 HDMI_TX0+35 HDMI_CLK+35
HDMI_TX2­HDMI_TX2+ HDMI_TX1­HDMI_TX1+ HDMI_TX0­HDMI_TX0+ HDMI_CLK­HDMI_CLK+
JCPU1H
T28
DDIB_TXN0
U28
DDIB_TXP0
T30
DDIB_TXN1
U30
DDIB_TXP1
U29
DDIB_TXN2
V29
DDIB_TXP2
U31
DDIB_TXN3
V31
DDIB_TXP3
T34
DDIC_TXN0
U34
DDIC_TXP0
U35
DDIC_TXN1
V35
DDIC_TXP1
U32
DDIC_TXN2
T32
DDIC_TXP2
U33
DDIC_TXN3
V33
DDIC_TXP3
P29
DDID_TXN0
R29
DDID_TXP0
N28
DDID_TXN1
P28
DDID_TXP1
P31
DDID_TXN2
R31
DDID_TXP2
N30
DDID_TXN3
P30
DDID_TXP3
FOX_PZ94726-3641-41H_HASWELL
ME@
Haswell rPGA EDS
DDI
eDP
EDP_AUXN
EDP_AUXP
EDP_HPD
EDP_RCOMP
EDP_DISP_UTIL
EDP_TXN_0 EDP_TXP_0 EDP_TXN_1 EDP_TXP_1
FDI_TXN_0 FDI_TXP_0 FDI_TXN_1 FDI_TXP_1
8 OF 9
M27 N27 P27 E24 R27
P35 R35 N34 P34 P33 R33 N32 P32
CPU_EDP_AUX# CPU_EDP_AUX EDP_HPD_IN# EDP_COMP
CPU_EDP_TX0­CPU_EDP_TX0+ CPU_EDP_TX1­CPU_EDP_TX1+ FDI_CTX_PRX_N0 FDI_CTX_PRX_P0 FDI_CTX_PRX_N1 FDI_CTX_PRX_P1
CPU_EDP_AUX# 34 CPU_EDP_AUX 34
1
PAD@
TC12
CPU_EDP_TX0- 34 CPU_EDP_TX0+ 34 CPU_EDP_TX1- 34 CPU_EDP_TX1+ 34 FDI_CTX_PRX_N0 15 FDI_CTX_PRX_P0 15 FDI_CTX_PRX_N1 15 FDI_CTX_PRX_P1 15
CPU_EDP_HPD34
12
RC48
100K_0402_5%
COMPENSATIONPUFOReDP
EDP_COMP
CADNote:Tracewidth=20mils,Spacing=25mil, Maxlength=100mils.
ReserveforDesignGuideandCRBrecommended.
CFG3
Haswell rPGA EDS
9 OF 9
12
RC192 1K_0402_1%
@
C23
RSVD_TP12
B23
RSVD_TP13
D24
RSVD_TP14
D23
RSVD_TP15
AT31
CFG_RCOMP
CFG_16 CFG_18 CFG_17 CFG_19
RSVD4 FC_G6 RSVD5 RSVD6 RSVD7 RSVD8
RSVD9 RSVD10 RSVD11
RSVD12
RSVD13
RSVD_TP16 RSVD_TP17
RSVD_TP18
VSS318 VSS319
VSS320 VSS321
NC
AR21 AR23 AP21 AP23
AR33 G6 AM27 AM26 F5 AM2 K6
E18 U10
P10 B1
A2 AR1
E21 E20
AP27 AR26
AL31 AL32
CFG_RCOMPCFG2 CFG16 CFG18 CFG17 CFG19
VCCST_PWRGD
PHYSICAL_DEBUG_ENABLED(DFXPRIVACY)
0:ENABLED
CFG3
SETDFXENABLEDBITINDEBUG INTERFACEMSR
1:DISABLED
*
1
PAD@
TC18
1
PAD@
TC19
1
PAD@
TC20
1
PAD@
TC16
1
PAD@
TC25
1
PAD@
TC29
1
PAD@
TC24
1
PAD@
TC27
1
PAD@
TC31
1
PAD@
TC33
1
PAD@
TC35
1
PAD@
TC36
1
PAD@
TC38
1
PAD@
TC40
1
PAD@
TC41
1
PAD@
TC44
1
PAD@
TC46
1
PAD@
TC50
1
PAD@
TC52
1
PAD@
TC55
1
PAD@
TC57
CFG[6:5]
*
CFG5 CFG6
12
RC51 1K_0402_1%
@
12
RC52 1K_0402_1%
PCIEPortBifurcationStraps 11:(Default)x16‐Device1functions1and2disabled 10:x8,x8‐Device1function1enabled;function2
disabled 01:Reserved‐(Device1function1disabled;function 2enabled)
00:x8,x4,x4‐Device1functions1and2enabled
12
RC55 1K_0402_1%
@
PEGDEFERTRAINING
1:(Default)PEGTrainimmediately
*
CFG7
followingxxRESETBdeassertion
0:PEGWaitforBIOSfortraining
NeedconfirmwithIntelifthisreservedcircuitcanbedeleted.
JCPU1I
1
PAD @
CFGSTRAPSforCPU
12
RC53 1K_0402_1%@
B B
A A
PEGStaticLaneReversal‐CFG2isforthe16x
1:(Default)NormalOperation;Lane#
*
CFG2
definitionmatchessocketpinmapdefinition
0:LaneReversed
CFG4 CFG7
12
RC54 1K_0402_1%
DisplayPortPresenceStrap
1:Disabled;NoPhysicalDisplayPort
CFG4
attachedtoEmbeddedDisplayPort
0:Enabled;AnexternalDisplayPortdeviceis
*
connectedtotheEmbeddedDisplayPort
TC13
1
PAD @
TC14
1
PAD @
TC15
1
PAD @
TC21
1
PAD @
TC22
1
PAD @
TC17
1
PAD @
TC23
1
PAD @
TC26
1
PAD @
TC28
TC30 TC32
TC34 TC37
TC39
TC56 TC58
TC43 TC45 TC47 TC48 TC49 TC51 TC53 TC54
RC56 49.9_0402_1% RC57 49.9_0402_1% RC58 49.9_0402_1%
1 1
1 1
1
1 1
1 1 1 1 1 1 1 1
PAD @ PAD @
PAD @ PAD @
PAD @
PAD @ PAD @
PAD @ PAD @ PAD @ PAD @ PAD @ PAD @ PAD @ PAD @
+VCC_CORE
12 12 12
H_CPU_TESTLO_G26
H_CPU_TESTLO_W34
H_CPU_TESTLO_G26 H_CPU_TESTLO_W34 CFG_RCOMP
CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15
AT1
RSVD_TP1
AT2
RSVD_TP2
AD10
RSVD1
A34
RSVD_TP3
A35
RSVD_TP4
W29
RSVD_TP5
W28
RSVD_TP6
G26
TESTLO_G26
W33
VSS317
AL30
RSVD2
AL29
RSVD3
F25
VCC104
C35
RSVD_TP7
B35
RSVD_TP8
AL25
RSVD_TP9
W30
RSVD_TP10
W31
RSVD_TP11
W34
TESTLO_W34
AT20
CFG_0
AR20
CFG_1
AP20
CFG_2
AP22
CFG_3
AT22
CFG_4
AN22
CFG_5
AT25
CFG_6
AN23
CFG_7
AR24
CFG_8
AT23
CFG_9
AN20
CFG_10
AP24
CFG_11
AP26
CFG_12
AN25
CFG_13
AN26
CFG_14
AP25
CFG_15
FOX_PZ94726-3641-41H_HASWELL
ME@
Title
Title
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
3
2012/12/14
2012/12/14
2012/12/14
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2012/12/21
2012/12/21
2012/12/21
Title
CPU (4/7) RSVD,CFG
CPU (4/7) RSVD,CFG
CPU (4/7) RSVD,CFG
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Friday, July 12, 2013
Friday, July 12, 2013
Date: Sheet
Date: Sheet
Date: Sheet
Friday, July 12, 2013
401025
401025
401025
1
of
of
of
861
861
861
1.1
1.1
1.1
5
4
3
2
1
Haswell rPGA EDS
JCPU1E
D D
CC49 .1U_0402_10V6-K
CC50 .1U_0402_10V6-K
75_0402_1%
RC66
130_0402_1%
+1.05VS
12
RC67 150_0402_1%
CPU_PWR_DEBUG#
12
RC68 10K_0402_5%
@
+VCCIO_OUT
+VCCIO_OUT
12
RC76
12
+VCCIO_OUT
+VCCIO2PCH
RC65 43_0402_5%
+1.05VS
1 2
RC63 0_0603_5%@
1 2
RC64 0_0603_5%@
C C
VR_SVID_ALRT#59 VR_SVID_CLK59 VR_SVID_DAT59
B B
TC65 TC64 TC66 TC67
1 2
1 2
TC68 TC69
TC70
TC71
TC72 TC73 TC74 TC75
1 2
TC76 TC77 TC78 TC79
1 1 1 1
@
@
1 1
1
1
1 1 1 1
CPU_PWR_DEBUG#
1 1 1 1
PAD @ PAD @ PAD @ PAD @
PAD @ PAD @
PAD @
PAD @
PAD @ PAD @ PAD @ PAD @
PAD @ PAD @ PAD @ PAD @
+1.35V_CPU_VDDQ+1.35V
+VCC_CORE
VCCSENSE_R
+VCCIO_OUT
+VCCIO2PCH
+VCCIOA_OUT
VR_SVID_ALRT#_R VR_SVID_CLK VR_SVID_DAT
+VCC_CORE
needconnecttopower
K27
RSVD15
L27
RSVD16
T27
RSVD17
V27
RSVD18
AB11
VDDQ1
AB2
VDDQ2
AB5
VDDQ3
AB8
VDDQ4
AE11
VDDQ5
AE2
VDDQ6
AE5
VDDQ7
AE8
VDDQ8
AH11
VDDQ9
K11
VDDQ10
N11
VDDQ11
N8
VDDQ12
T11
VDDQ13
T2
VDDQ14
T5
VDDQ15
T8
VDDQ16
W11
VDDQ17
W2
VDDQ18
W5
VDDQ19
W8
VDDQ20
N26
RSVD19
K26
VCC103
AL27
RSVD20
AK27
RSVD21
AL35
VCC_SENSE
E17
RSVD22
AN35
VCCIO_OUT
A23
FC_A23
F22
VCOMP_OUT
W32
RSVD23
AL16
RSVD24
J27
RSVD25
AL13
RSVD26
AM28
VIDALERT
AM29
VIDSCLK
AL28
VIDSOUT
AP35
VSS317
H27
PWR_DEBUG
AP34
VSS318
AT35
RSVD_TP19
AR35
RSVD_TP20
AR32
IVR_ERROR
AL26
IST_TRIGGER
AT34
VSS319
AL22
VSS320
AT33
VSS321
AM21
VSS322
AM25
VSS323
AM22
VSS324
AM20
VSS325
AM24
VSS326
AL19
VSS327
AM23
VSS328
AT32
VSS329
Y25
VCC1
Y26
VCC2
Y27
VCC3
Y28
VCC4
Y29
VCC5
Y30
VCC6
Y31
VCC7
Y32
VCC8
Y33
VCC9
Y34
VCC10
Y35
VCC11
FOX_PZ94726-3641-41H_HASWELL
ME@
5 OF 9
VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50 VCC51 VCC52 VCC53 VCC54 VCC55 VCC56 VCC57 VCC58 VCC59 VCC60 VCC61 VCC62 VCC63 VCC64 VCC65 VCC66 VCC67 VCC68 VCC69 VCC70 VCC71 VCC72 VCC73 VCC74 VCC75 VCC76 VCC77 VCC78 VCC79 VCC80 VCC81 VCC82 VCC83 VCC84 VCC85 VCC86 VCC87 VCC88 VCC89 VCC90 VCC91 VCC92 VCC93 VCC94 VCC95 VCC96
VCC97 VCC98 VCC99
VCC100 VCC101
VCC102
AA26 AA28 AA34 AA30 AA32 AB26 AB29 AB25 AB27 AB28 AB30 AB31 AB33 AB34 AB32 AC26 AB35 AC28 AD25 AC30 AD28 AC32 AD31 AC34 AD34 AD26 AD27 AD29 AD30 AD32 AD33 AD35 AE26 AE32 AE28 AE30 AG28 AG34 AE34 AF25 AF26 AF27 AF28 AF29 AF30 AF31 AF32 AF33 AF34 AF35 AG26 AH26 AH29 AG30 AG32 AH32 AH35 AH25 AH27 AH28 AH30 AH31 AH33 AH34 AJ25 AJ26 AJ27 AJ28 AJ29 AJ30 AJ31 AJ32 AJ33 AJ34 AJ35 G25 H25 J25 K25 L25 M25 N25 P25 R25 T25
U25 U26 V25 V26
W26 W27
+VCC_CORE
+1.35V_CPU_VDDQ
VCC_SENSE
VCCSENSE59
VSSSENSE59
VDDQDECOUPLING
10U_0603_6.3V6M
1
2
22U_0805_6.3V6M
1
2
CC51
CC63
10U_0603_6.3V6M
10U_0603_6.3V6M
1
1
CC52
2
2
22U_0805_6.3V6M
22U_0805_6.3V6M
1
1
CC64
2
2
+VCC_CORE
12
RC59 100_0402_1%
CADNote:RC59SHOULDBEPLACEDCLOSETOCPU
12
VCCSENSE VCCSENSE_R
@
RC600_0402_5%
CADNote:RC62SHOULDBEPLACEDCLOSETOCPU
12
VSSSENSE VSSSENSE_R
CC53
CC65
12
RC62 100_0402_1%
10U_0603_6.3V6M
10U_0603_6.3V6M
1
1
1
CC55
CC54
2
2
2
22U_0805_6.3V6M
22U_0805_6.3V6M
1
CC66
1
CC67
2
2
1
2
@
RC800_0402_5%
Change RC60,RC61 to 0ohm jump
10U_0603_6.3V6M
CC57
CC69
10U_0603_6.3V6M
1
1
CC58
CC59
2
2
22U_0805_6.3V6M
22U_0805_6.3V6M
1
1
CC71
CC70
2
2
10U_0603_6.3V6M
10U_0603_6.3V6M
1
CC56
2
22U_0805_6.3V6M
22U_0805_6.3V6M
1
CC68
2
VSSSENSE_R 10
Power
@
10U_0603_6.3V6M
330U_2.5V_M
1
CC61
1
+
CC60
2
2
22U_0805_6.3V6M
22U_0805_6.3V6M
1
1
CC73
CC72
2
2
A A
Title
Title
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
3
2012/12/14
2012/12/14
2012/12/14
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2012/12/21
2012/12/21
2012/12/21
Title
CPU (5/7) PWR, BYPASS
CPU (5/7) PWR, BYPASS
CPU (5/7) PWR, BYPASS
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Friday, July 12, 2013
Friday, July 12, 2013
Friday, July 12, 2013
Date: Sheet
Date: Sheet
Date: Sheet
401025
401025
401025
1
961
961
961
of
of
of
1.1
1.1
1.1
5
Haswell rPGA EDS
JCPU1F
A10
VSS1
A13
VSS2
A16
VSS3
A19
VSS4
A22
VSS5
A25
VSS6
A27
VSS7
A29
VSS8
A3
VSS9
A31
VSS10
A33
VSS11
A4
D D
C C
B B
VSS12
A7
VSS13
AA11
VSS14
AA25
VSS15
AA27
VSS16
AA31
VSS17
AA29
VSS18
AB1
VSS19
AB10
VSS20
AA33
VSS21
AA35
VSS22
AB3
VSS23
AC25
VSS24
AC27
VSS25
AB4
VSS26
AB6
VSS27
AB7
VSS28
AB9
VSS29
AC11
VSS30
AD11
VSS31
AC29
VSS32
AC31
VSS33
AC33
VSS34
AC35
VSS35
AD7
VSS36
AE1
VSS37
AE10
VSS38
AE25
VSS39
AE29
VSS40
AE3
VSS41
AE27
VSS42
AE35
VSS43
AE4
VSS44
AE6
VSS45
AE7
VSS46
AE9
VSS47
AF11
VSS48
AF6
VSS49
AF8
VSS50
AG11
VSS51
AG25
VSS52
AE31
VSS53
AG31
VSS54
AE33
VSS55
AG6
VSS56
AH1
VSS57
AH10
VSS58
AH2
VSS59
AG27
VSS60
AG29
VSS61
AH3
VSS62
AG33
VSS63
AG35
VSS64
AH4
VSS65
AH5
VSS66
AH6
VSS67
AH7
VSS68
AH8
VSS69
AH9
VSS70
AJ11
VSS71
AJ5
VSS72
AK11
VSS73
AK25
VSS74
AK26
VSS75
AK28
VSS76
AK29
VSS77
AK30
VSS78
AK32
VSS79
E19
VSS80
FOX_PZ94726-3641-41H_HASWELL
ME@
For Deep S3
+3VALW
12
RC70
100K_0402_5%
QC8
2
G
@
RUN_ON_CPU1.5VS3#
13
D
@
S
@
RC73
SUSP40,46,55
A A
CPU1.5V_S3_GATE44
5
1 2
0_0402_5%
2N7002KW_SOT323-3
6 OF 9
2
G
4
AK34
VSS81
AK5
VSS82
AL1
VSS83
AL10
VSS84
AL11
VSS85
AL12
VSS86
AL14
VSS87
AL15
VSS88
AL17
VSS89
AL18
VSS90
AL2
VSS91
AL20
VSS92
AL21
VSS93
AL23
VSS94
E22
VSS95
AL3
VSS96
AL4
VSS97
AL5
VSS98
AL6
VSS99
AL7
VSS100
AL8
VSS101
AL9
VSS102
AM10
VSS103
AM13
VSS104
AM16
VSS105
AM19
VSS106
E25
VSS107
AM32
VSS108
AM4
VSS109
AM7
VSS110
AN10
VSS111
AN13
VSS112
AN16
VSS113
AN19
VSS114
AN2
VSS115
AN21
VSS116
AN24
VSS117
AN27
VSS118
AN30
VSS119
AN34
VSS120
AN4
VSS121
AN7
VSS122
AP1
VSS123
AP10
VSS124
AP13
VSS125
AP16
VSS126
AP19
VSS127
AP4
VSS128
AP7
VSS129
W25
VSS130
AR10
VSS131
AR13
VSS132
AR16
VSS133
AR19
VSS134
AR2
VSS135
AR22
VSS136
AR25
VSS137
AR28
VSS138
AR31
VSS139
AR34
VSS140
AR4
VSS141
AR7
VSS142
AT10
VSS143
AT13
VSS144
AT16
VSS145
AT19
VSS146
AT21
VSS147
AT24
VSS148
AT27
VSS149
AT3
VSS150
AT30
VSS151
AT4
VSS152
AT7
VSS153
B10
VSS154
B13
VSS155
B16
VSS156
B19
VSS157
B2
VSS158
B22
VSS159
+VSB
RC69 need to check on SDV
12
RC69 100K_0402_5%
@
RUN_ON_CPU1.5VS3
13
D
QC6 2N7002KW_SOT323-3
S
@
RUN_ON_CPU1.5VS3# 6
4
3
+1.35V_CPU_VDDQ
J1
2
112
JUMP_43X79
+1.35V +1.35V_CPU_VDDQ
QC9
1 2
470K_0402_5%
12
RC74 470K_0402_5%
@
1 2
CC74 .1U_0402_10V6-K@
1 2
CC75 .1U_0402_10V6-K@
1 2
CC76 .1U_0402_10V6-K@
1 2
CC77 .1U_0402_10V6-K@
8 7 6 5
4
@
RC72
@
AO4304L Vgs=10V,Id=18A, Rds<6.7m ohm P/N: SB00000RV00
1
CC78 .01U_0402_16V7-K
@
2
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
AO4456_SO8
1 2 3
3
+1.35V_CPU_VDDQ+1.35V
12
RC71 470_0603_5%
@
13
D
QC7
S
2N7002KW_SOT323-3
@
2012/12/14
2012/12/14
2012/12/14
2
SUSP
G
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Haswell rPGA EDS
JCPU1G
B34
VSS160
B4
VSS161
B7
VSS162
C1
VSS163
C10
VSS164
C13
VSS165
C16
VSS166
C19
VSS167
C2
VSS168
C22
VSS169
C24
VSS170
C26
VSS171
C28
VSS172
C30
VSS173
C32
VSS174
C34
VSS175
C4
VSS176
C7
VSS177
D10
VSS178
D13
VSS179
D16
VSS180
D19
VSS181
D22
VSS182
D25
VSS183
D27
VSS184
D29
VSS185
D31
VSS186
D33
VSS187
D35
VSS188
D4
VSS189
D7
VSS190
E1
VSS191
E10
VSS192
E13
VSS193
E16
VSS194
E4
VSS195
E7
VSS196
F10
VSS197
F11
VSS198
F12
VSS199
F14
VSS200
F15
VSS201
F17
VSS202
F18
VSS203
F20
VSS204
F21
VSS205
F23
VSS206
F24
VSS207
F26
VSS208
F28
VSS209
F30
VSS210
F32
VSS211
F34
VSS212
F4
VSS213
F6
VSS214
F7
VSS215
F8
VSS216
F9
VSS217
G1
VSS218
G11
VSS219
G2
VSS220
G27
VSS221
G29
VSS222
G3
VSS223
G31
VSS224
G33
VSS225
G35
VSS226
G4
VSS227
G5
VSS228
H10
VSS229
H26
VSS230
H6
VSS231
H7
VSS232
J11
VSS233
J26
VSS234
J28
VSS235
J30
VSS236
J32
VSS237
J34
VSS238
J6
VSS239
K1
VSS240
FOX_PZ94726-3641-41H_HASWELL
ME@
Deciphered Date
Deciphered Date
Deciphered Date
7 OF 9
2
VSS_SENSE
2
VSS241 VSS242 VSS243 VSS244 VSS245 VSS246 VSS247 VSS248 VSS249 VSS250 VSS251 VSS252 VSS253 VSS254 VSS255 VSS256 VSS257 VSS258 VSS259 VSS260 VSS261 VSS262 VSS263 VSS264 VSS265 VSS266 VSS267 VSS268 VSS269 VSS270 VSS271 VSS272 VSS273 VSS274 VSS275 VSS276 VSS277 VSS278 VSS279 VSS280 VSS281 VSS282 VSS283 VSS284 VSS285 VSS286 VSS287 VSS288 VSS289 VSS290 VSS291 VSS292 VSS293 VSS294 VSS295 VSS296 VSS297 VSS298 VSS299 VSS300 VSS301 VSS302 VSS303 VSS304 VSS305 VSS306 VSS307 VSS308 VSS309 VSS310 VSS311 VSS312 VSS313 VSS314 VSS315 VSS316
RSVD14
2012/12/21
2012/12/21
2012/12/21
K10 K2 K29 K3 K31 K33 K35 K4 K5 K7 K8 K9 L11 L26 L6 M11 M26 M28 M30 M32 M34 M6 N1 N10 N2 N29 N3 N31 N33 N35 N4 N5 N6 N7 N9 P11 P26 P5 R11 R26 R28 R30 R32 R34 R5 T1 T10 T29 T3 T31 T33 T35 T4 T6 T7 T9 U11 U27 V11 V28 V30 V32 V34 W1 W10 W3 W35 W4 W6 W7 W9 Y11 H11 AL24 F19 T26 AK35 AK33
1
1
PAD@
TC80
Title
Title
Title
CPU (6/7) PWR
CPU (6/7) PWR
CPU (6/7) PWR
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Friday, July 12, 2013
Friday, July 12, 2013
Date: Sheet
Date: Sheet
Date: Sheet
Friday, July 12, 2013
VSSSENSE_R 9
401025
401025
401025
1
of
of
of
10 61
10 61
10 61
1.1
1.1
1.1
5
4
3
2
1
DDR3 SO-DIMM A
+VREF_DQ_DIMMA_R
D D
1
CD1 .1U_0402_10V6-K
2
12
RD4
24.9_0402_1%
For EMC
C C
B B
A A
RD2
1 2
@
0_0402_5%
+1.35V
12
RD1 1K_0402_1%
+VREF_DQ_DIMMA
12
RD31K_0402_1%
CD2
DDRA_CKE07
DDRA_BS2#7
DDRA_CLK07 DDRA_CLK0#7
DDRA_BS0#7 DDRA_WE#7
DDRA_CAS#7
DDRA_CS1#7
+3VS
CD27
2.2U_0603_6.3V6K
Change RD2 to 0ohm jump
DDRA_DQ0 DDRA_DQ1
1
1
CD3
2
2
2.2U_0603_6.3V6K
1
1
2
2
5
.1U_0402_10V6-K
CD28 .1U_0402_10V6-K
DDRA_DQ2 DDRA_DQ3
DDRA_DQ8 DDRA_DQ9
DDRA_DQS#1 DDRA_DQS1
DDRA_DQ10 DDRA_DQ11
DDRA_DQ16 DDRA_DQ17
DDRA_DQS#2 DDRA_DQS2
DDRA_DQ18 DDRA_DQ19
DDRA_DQ24 DDRA_DQ25
DDRA_DQ26 DDRA_DQ27
DDRA_CKE0
DDRA_BS2# DDRA_MA12
DDRA_MA9 DDRA_MA8
DDRA_MA5 DDRA_MA3
DDRA_MA1 DDRA_CLK0
DDRA_CLK0# DDRA_MA10
DDRA_BS0# DDRA_WE#
DDRA_CAS# DDRA_MA13
DDRA_CS1#
DDRA_DQ32 DDRA_DQ33
DDRA_DQS#4 DDRA_DQS4
DDRA_DQ34 DDRA_DQ35
DDRA_DQ40 DDRA_DQ41
DDRA_DQ42 DDRA_DQ43
DDRA_DQ48 DDRA_DQ49
DDRA_DQS#6 DDRA_DQS6
DDRA_DQ50 DDRA_DQ51
DDRA_DQ56 DDRA_DQ57
DDRA_DQ58 DDRA_DQ59
1 2
RD9
10K_0402_5%
12
RD10 10K_0402_5%
3A@1.5V
JDDRH1
VREF_DQ1VSS1
3
VSS2
5
DQ0
7
DQ1
9
VSS4
11
DM0
13
VSS5
15
DQ2
17
DQ3
19
VSS7
21
DQ8
23
DQ9
25
VSS9
27
DQS#1 DQS129RESET#
31
VSS11
33
DQ10
35
DQ11
37
VSS13
39
DQ16
41
DQ17
43
VSS15
45
DQS#2
47
DQS2
49
VSS18
51
DQ18
53
DQ19
55
VSS20
57
DQ24
59
DQ25 VSS2261DQS#3
63
DM3
65
VSS23
67
DQ26
69
DQ27
71
VSS25
73
CKE0
75
VDD1
77
NC1
79
BA2
81
VDD3
83
A12/BC#
85
A9
87
VDD5
89
A8
91
A5
93
VDD7
95
A3
97
A1
99
VDD9
101
CK0
103
CK0#
105
VDD11
107
A10/AP
109
BA0
111
VDD13
113
WE#
115
CAS#
117
VDD15
119
A13
121
S1#
123
VDD17
125
NCTEST
127
VSS27
129
DQ32
131
DQ33
133
VSS29
135
DQS#4
137
DQS4
139
VSS32
141
DQ34
143
DQ35
145
VSS34
147
DQ40
149
DQ41
151
VSS36
153
DM5
155
VSS37
157
DQ42
159
DQ43
161
VSS39
163
DQ48
165
DQ49
167
VSS41
169
DQS#6
171
DQS6
173
VSS44
175
DQ50
177
DQ51
179
VSS46
181
DQ56
183
DQ57
185
VSS48
187
DM7
189
VSS49
191
DQ58
193
DQ59
195
VSS51
197
SA0
199
VDDSPD
201
SA1
203
VTT1
205
G1
LCN_DAN06-K4806-0102
ME@
DQ4 DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6 DQ7
VSS8 DQ12 DQ13
VSS10
DM1
VSS12
DQ14 DQ15
VSS14
DQ20 DQ21
VSS16
DM2
VSS17
DQ22 DQ23
VSS19
DQ28 DQ29
VSS21
DQS3
VSS24
DQ30 DQ31
VSS26
CKE1 VDD2
VDD4
VDD6
VDD8
VDD10
CK1#
VDD12
RAS#
VDD14
ODT0
VDD16
ODT1
VDD18
VREF_CA
VSS28
DQ36 DQ37
VSS30
DM4
VSS31
DQ38 DQ39
VSS33
DQ44 DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46 DQ47
VSS40
DQ52 DQ53
VSS42
DM6
VSS43
DQ54 DQ55
VSS45
DQ60 DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62 DQ63
VSS52
EVENT#
VTT2
A15 A14
A11
CK1
BA1
S0#
NC2
SDA SCL
+1.35V+1.35V
2 4
DDRA_DQ4
6
DDRA_DQ5
8 10
DDRA_DQS#0
12
DDRA_DQS0
14 16
DDRA_DQ6
18
DDRA_DQ7
20 22
DDRA_DQ12
24
DDRA_DQ13
26 28 30
DDR3_DRAMRST#
32 34
DDRA_DQ14
36
DDRA_DQ15
38 40
DDRA_DQ20
42
DDRA_DQ21
44 46 48 50
DDRA_DQ22
52
DDRA_DQ23
54 56
DDRA_DQ28
58
DDRA_DQ29
60 62
DDRA_DQS#3
64
DDRA_DQS3
66 68
DDRA_DQ30
70
DDRA_DQ31
72
74
DDRA_CKE1
76 78
DDRA_MA15
80
DDRA_MA14
82 84
DDRA_MA11
86
A7 A6
A4 A2
A0
G2
DDRA_MA7
88 90
DDRA_MA6
92
DDRA_MA4
94 96
DDRA_MA2
98
DDRA_MA0
100 102
DDRA_CLK1
104
DDRA_CLK1#
106 108
DDRA_BS1#
110
DDRA_RAS#
112 114
DDRA_CS0#
116
DDRA_ODT0
118 120
DDRA_ODT1
122 124 126 128 130
DDRA_DQ36
132
DDRA_DQ37
134 136 138 140
DDRA_DQ38
142
DDRA_DQ39
144 146
DDRA_DQ44
148
DDRA_DQ45
150 152
DDRA_DQS#5
154
DDRA_DQS5
156 158
DDRA_DQ46
160
DDRA_DQ47
162 164
DDRA_DQ52
166
DDRA_DQ53
168 170 172 174
DDRA_DQ54
176
DDRA_DQ55
178 180
DDRA_DQ60
182
DDRA_DQ61
184 186
DDRA_DQS#7
188
DDRA_DQS7
190 192
DDRA_DQ62
194
DDRA_DQ63
196 198 200
SMB_DATA_S3
202
SMB_CLK_S3
204 206
4
0.65A@0.75V
For RF request
0.047U_0402_16V7K
1
@
CD4
2
DDR3_DRAMRST# 6,12
DDRA_CKE1 7
DDRA_CLK1 7 DDRA_CLK1# 7
DDRA_BS1# 7 DDRA_RAS# 7
DDRA_CS0# 7 DDRA_ODT0 7
DDRA_ODT1 7
.1U_0402_10V6-K
CD21
1
1
2
2
SMB_DATA_S3 12,17,40,45 SMB_CLK_S3 12,17,40,45
+0.675VS
0.047U_0402_16V7K
0.047U_0402_16V7K
1
1
@
@
2
CD6
CD5
2
Layout Note: Place near DIMM
OSCON (220uF_6.3V_4.2L_ESR17m)*1=(SF000002Y00) (10uF_0603_6.3V)*8 (0.1uF_402_10V)*4
+1.35V
10U_0603_6.3V6M
10U_0603_6.3V6M
CD7
CD8
1
2
+VREF_CA
CD22
2.2U_0603_6.3V6K
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
3
10U_0603_6.3V6M
10U_0603_6.3V6M
CD10
CD9
1
1
2
2
CD11
1
2
Change RD6 to 0ohm jump
+VREF_CA 12
Layout Note: Place near DIMM
+0.675VS
CD23
2012/12/14
2012/12/14
2012/12/14
10U_0603_6.3V6M
CD12
1
1
2
2
+1.35V
+VREF_CA
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
CD24
2
2
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
DDRA_DQ[0..63] 7 DDRA_DQS[0..7] 7 DDRA_DQS#[0..7] 7 DDRA_MA[0..15] 7
10U_0603_6.3V6M
CD13
1
2
12
RD5 1K_0402_1%
RD6
@
0_0402_5%
12
RD7 1K_0402_1%
1U_0402_6.3V6K
1
CD25
2
Deciphered Date
Deciphered Date
Deciphered Date
10U_0603_6.3V6M
12
CD26
CD14
1
2
+VREF_CA_R
1U_0402_6.3V6K
1
2
2
.1U_0402_10V6-K
10U_0603_6.3V6M
.1U_0402_10V6-K
CD16
CD15
1
2
Note: VREFtracewidth:20milsatleast Spacing:20milstoothersignal/planes PlacenearDIMMscoket
1
CD20 .1U_0402_10V6-K
@
2
12
RD8
24.9_0402_1%
@
CD17
1
2
Layout Note: Place near DIMM
DDR_A_DM[0:7] connect to GND
2012/12/21
2012/12/21
2012/12/21
ReserveforEMI
1000P_0402_50V7K
.1U_0402_10V6-K
.1U_0402_10V6-K
CD18
1
1
2
2
Title
Title
Title
DDRIII SO-DIMM A
DDRIII SO-DIMM A
DDRIII SO-DIMM A
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Friday, July 12, 2013
Friday, July 12, 2013
Date: Sheet
Date: Sheet
Date: Sheet
Friday, July 12, 2013
CD19
220U_6.3V_M
1
+
2
401025
401025
401025
.01U_0402_16V7-K
CD56
CD55
@
1
1
2
11 61
11 61
11 61
1
2
@
of
of
of
1.1
1.1
1.1
5
4
3
2
1
+VREF_DQ_DIMMB_R
RD12
1 2
@
0_0402_5%
D D
1
CD29 .1U_0402_10V6-K
2
12
RD14
24.9_0402_1%
For EMC
C C
B B
A A
2.2U_0603_6.3V6K
Change RD12 to 0ohm jump
+1.35V
12
RD11 1K_0402_1%
+VREF_DQ_DIMMB
1K_0402_1%
5
CD53
2.2U_0603_6.3V6K
1
CD30
2
DDRB_CKE07
DDRB_BS2#7
DDRB_CLK07 DDRB_CLK0#7
DDRB_BS0#7 DDRB_WE#7
DDRB_CAS#7
DDRB_CS1#7
1
2
RD13
12
+3VS
.1U_0402_10V6-K
1
CD31
2
1
CD54 .1U_0402_10V6-K
2
DDRB_DQ0 DDRB_DQ1
DDRB_DQ2 DDRB_DQ3
DDRB_DQ8 DDRB_DQ9
DDRB_DQS#1 DDRB_DQS1
DDRB_DQ10 DDRB_DQ11
DDRB_DQ16 DDRB_DQ17
DDRB_DQS#2 DDRB_DQS2
DDRB_DQ18 DDRB_DQ19
DDRB_DQ24 DDRB_DQ25
DDRB_DQ26 DDRB_DQ27
DDRB_CKE0
DDRB_BS2# DDRB_MA12
DDRB_MA9 DDRB_MA8
DDRB_MA5 DDRB_MA3
DDRB_MA1 DDRB_CLK0
DDRB_CLK0# DDRB_MA10
DDRB_BS0# DDRB_WE#
DDRB_CAS# DDRB_MA13
DDRB_CS1#
DDRB_DQ32 DDRB_DQ33
DDRB_DQS#4 DDRB_DQS4
DDRB_DQ34 DDRB_DQ35
DDRB_DQ40 DDRB_DQ41
DDRB_DQ42 DDRB_DQ43
DDRB_DQ48 DDRB_DQ49
DDRB_DQS#6 DDRB_DQS6
DDRB_DQ50 DDRB_DQ51
DDRB_DQ56 DDRB_DQ57
DDRB_DQ58 DDRB_DQ59
1 2
RD16 10K_0402_5%
1 2
RD17 10K_0402_5%
DDR3 SO-DIMM B
+1.35V +1.35V
3A@1.5V
JDDRL1
VREF_DQ1VSS1
3
VSS2
5
DQ0
7
DQ1
9
VSS4
11
DM0
13
VSS5
15
DQ2
17
DQ3
19
VSS7
21
DQ8
23
DQ9
25
VSS9
27
DQS#1 DQS129RESET# VSS1131VSS12
33
DQ10
35
DQ11 VSS1337VSS14
39
DQ16
41
DQ17 VSS1543VSS16
45
DQS#2
47
DQS2
49
VSS18
51
DQ18
53
DQ19
55
VSS20
57
DQ24
59
DQ25 VSS2261DQS#3
63
DM3 VSS2365VSS24
67
DQ26
69
DQ27 VSS2571VSS26
73
CKE0
75
VDD1
77
NC1
79
BA2
81
VDD3
83
A12/BC#
85
A9
87
VDD5
89
A8
91
A5
93
VDD7
95
A3
97
A1
99
VDD9
101
CK0
103
CK0#
105
VDD11
107
A10/AP
109
BA0
111
VDD13
113
WE#
115
CAS#
117
VDD15
119
A13
121
S1#
123
VDD17
125
NCTEST
127
VSS27
129
DQ32
131
DQ33
133
VSS29
135
DQS#4
137
DQS4
139
VSS32
141
DQ34
143
DQ35
145
VSS34
147
DQ40
149
DQ41
151
VSS36
153
DM5
155
VSS37
157
DQ42
159
DQ43
161
VSS39
163
DQ48
165
DQ49
167
VSS41
169
DQS#6
171
DQS6
173
VSS44
175
DQ50
177
DQ51
179
VSS46
181
DQ56
183
DQ57
185
VSS48
187
DM7
189
VSS49
191
DQ58
193
DQ59
195
VSS51
197
SA0
199
VDDSPD
201
SA1
203
VTT1
205
G1
LCN_DAN06-K4406-0102 ME@
DQ4 DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7 VSS8 DQ12 DQ13
VSS10
DM1
DQ14 DQ15
DQ20 DQ21
DM2
VSS17
DQ22 DQ23
VSS19
DQ28 DQ29
VSS21
DQS3
DQ30 DQ31
CKE1
VDD2
VDD4
VDD6
VDD8
VDD10
CK1 CK1#
VDD12
RAS#
VDD14
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36 DQ37
VSS30
DM4
VSS31
DQ38 DQ39
VSS33
DQ44 DQ45
VSS35 DQS#5
DQS5
VSS38
DQ46 DQ47
VSS40
DQ52 DQ53
VSS42
DM6
VSS43
DQ54 DQ55
VSS45
DQ60 DQ61
VSS47 DQS#7
DQS7
VSS50
DQ62 DQ63
VSS52
EVENT#
SDA
SCL VTT2
4
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72
74 76 78
A15
80
A14
82 84
A11
86
A7
88 90
A6
92
A4
94 96
A2
98
A0
100 102 104 106 108
BA1
110 112 114
S0#
116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204
206
G2
DDRB_DQ4 DDRB_DQ5
DDRB_DQS#0 DDRB_DQS0
DDRB_DQ6 DDRB_DQ7
DDRB_DQ12 DDRB_DQ13
DDR3_DRAMRST# DDRB_DQ14
DDRB_DQ15 DDRB_DQ20
DDRB_DQ21
DDRB_DQ22 DDRB_DQ23
DDRB_DQ28 DDRB_DQ29
DDRB_DQS#3 DDRB_DQS3
DDRB_DQ30 DDRB_DQ31
DDRB_CKE1 DDRB_MA15
DDRB_MA14 DDRB_MA11
DDRB_MA7 DDRB_MA6
DDRB_MA4 DDRB_MA2
DDRB_MA0 DDRB_CLK1
DDRB_CLK1# DDRB_BS1#
DDRB_RAS# DDRB_CS0#
DDRB_ODT0 DDRB_ODT1
DDRB_DQ36 DDRB_DQ37
DDRB_DQ38 DDRB_DQ39
DDRB_DQ44 DDRB_DQ45
DDRB_DQS#5 DDRB_DQS5
DDRB_DQ46 DDRB_DQ47
DDRB_DQ52 DDRB_DQ53
DDRB_DQ54 DDRB_DQ55
DDRB_DQ60 DDRB_DQ61
DDRB_DQS#7 DDRB_DQS7
DDRB_DQ62 DDRB_DQ63
SMB_DATA_S3 SMB_CLK_S3
0.65A@0.75V
For RF request
CD32
@
DDRB_CKE1 7
DDRB_CLK1 7 DDRB_CLK1# 7
DDRB_BS1# 7 DDRB_RAS# 7
DDRB_CS0# 7 DDRB_ODT0 7
DDRB_ODT1 7
.1U_0402_10V6-K
1
CD47
2
SMB_DATA_S3 11,17,40,45 SMB_CLK_S3 11,17,40,45 +0.675VS
0.047U_0402_16V7K
0.047U_0402_16V7K
1
1
CD33
2
2
@
DDR3_DRAMRST# 6,11
+VREF_CB
1
CD48
2.2U_0603_6.3V6K
2
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
0.047U_0402_16V7K
1
CD34
2
@
Layout Note: Place near DIMM
CD35
3
+1.35V
10U_0603_6.3V6M
CD36
1
1
2
2
RD15
1 2
@
0_0402_5%
Change RD15 to 0ohm jump
2012/12/14
2012/12/14
2012/12/14
10U_0603_6.3V6M
10U_0603_6.3V6M
CD38
CD37
1
2
+VREF_CA 11
Layout Note: Place near DIMM
CD49
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
(10uF_0603_6.3V)*8 (0.1uF_402_10V)*4
10U_0603_6.3V6M
10U_0603_6.3V6M
CD39
1
2
+0.675VS
1U_0402_6.3V6K
1
CD50
2
Deciphered Date
Deciphered Date
Deciphered Date
CD40
1
1
2
2
1U_0402_6.3V6K
CD51
1U_0402_6.3V6K
1
2
2
1
2
10U_0603_6.3V6M
CD52
2012/12/21
2012/12/21
2012/12/21
DDRB_DQ[0..63] 7 DDRB_DQS[0..7] 7 DDRB_DQS#[0..7] 7 DDRB_MA[0..15] 7
10U_0603_6.3V6M
CD41
CD42
1
2
1U_0402_6.3V6K
1
2
.1U_0402_10V6-K
10U_0603_6.3V6M
CD43
1
2
1
2
Layout Note: Place near DIMM
.1U_0402_10V6-K
.1U_0402_10V6-K
CD44
CD45
1
1
2
2
CD46
.1U_0402_10V6-K
1
2
DDR_B_DM[0:7] connect to GND
Title
Title
Title
DDRIII SO-DIMM B
DDRIII SO-DIMM B
DDRIII SO-DIMM B
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Friday, July 12, 2013
Friday, July 12, 2013
Date: Sheet
Date: Sheet
Date: Sheet
Friday, July 12, 2013
401025
401025
401025
1
12 61
12 61
12 61
1.1
1.1
1.1
of
of
of
5
4
3
2
1
1 2
@
1 2
@
1 2
@
PCH_RTCX1
PCH_RTCX2
1
18P_0402_50V8J
2
1K_0402_5%
1K_0402_5%
1K_0402_5%
CH3
SM_INTRUDER# PCH_INTVRMEN
+3VS
RH14 51_0402_1%@ RH16 210_0402_1%@ RH18 210_0402_1%@ RH20 210_0402_1%@
Place JUMPER under RAM door
+RTCVCC
1 2
RH3
1 2
RH4
RH7
1 2
10K_0402_5%
1 2 1 2 1 2
HDA_SDOUT
PCH_SPKR
HDA_SYNC
PCH_GPIO33
@
ME_FLASH44
12
RH1
1 2
10M_0402_5% YH1
1 2
32.768KHZ_12.5PF_200458-PG14
1
D D
C C
B B
CH2
18P_0402_50V8J
2
+RTCVCC
*
1 2
RH5 1M_0402_5%
1 2
RH6 330K_0402_5%
INTVRMEN H Integrated VRM enable (Default)　 L Integrated VRM disable　 (INTVRMEN should always be pull high.)
GPIO33 This signal has a weak internal pull-down. DMI TX Termination Strap (Rising edge of PWROK) This signal only takes effect if DMI is configured in DC-
+3V_PCH
coupled mode. 0 = DMI TX is terminated to VSS.
*
12
1 = DMI TX is terminated to VCC/2.
RH12 0_0603_5%
@
+3.3V_ALW_PCH_JTAG PCH_JTAG_TMS
+3V_PCH
RH25
HDA_SDO This signal has a weak internal pull-down. 0 = Enable security measures defined in the Flash Descriptor.
*
1 = Disable Flash Descriptor Security (override). This strap should only be asserted high using external pull­ up in manufacturing/debug environments ONLY.
+3VS
RH28
SPKR The signal has a weak internal pull-down. H Enable ( No Reboot, PCH will disable the TCO Timer system reboot feature, This function is useful when running ITP/XDP. ) L Disable (Default)
*
+3V_PCH
RH31
W=20mils W=20mils
+RTCBATT +RTCVCC
RH2
1 2
0_0402_5%
CMOS
1 2
@
TH3 TH4
PCH_RTCX1
PCH_RTCX2 PCH_SRTCRST# SM_INTRUDER# PCH_INTVRMEN PCH_RTCRST#
HDA_BIT_CLK
HDA_SYNC
PCH_SPKR
HDA_RST#
HDA_SDIN0
PCH_GPIO33
PCH_GPIO13
PCH_TP25
0_0402_5%
1 1
1
2
1
2
1 2 1 2
@
1 2
@
100_0402_1%
12
12
JME1
@
SHORT PADS
12
JCMOS1 SHORT PADS@
PCH_SPKR43
HDA_SDIN043
1K_0402_5%
PCH_JTAG_TCK
PCH_JTAG_TDI PCH_JTAG_TDO
RH21
PAD@ PAD@
CH4
1U_0402_6.3V6K
20K_0402_5%
20K_0402_5%
ME_FLASH HDA_SDOUT
+3V_PCH
1U_0402_6.3V6K
RH11 10K_0402_5%
100_0402_1%
12
12
RH23
RH22
@
@
CH5
Change RH9 to 0ohm jump
RH9 0_0402_5%@ RH10
100_0402_1%
RH24
@
HDA AUDIO
1 2
HDA_SYNC_AUDIO43
HDA_RST_AUDIO#43
HDA_SDOUT_AUDIO43
HDA_BITCLK_AUDIO43
RH27
33_0402_5%
1 2
RH29
33_0402_5%
1 2
RH30
33_0402_5%
1 2
RH26
33_0402_5%
1
CH77 100P_0402_50V8J
2
@
1
CH1
1U_0402_6.3V6K
2
B5 B4 B9 A8
G10
D9
B25 A22
AL10
C24
L22 K22 G22
F22 A24 B17 C22
AB3 AD1
AE2 AD3
F8 C26 AB6
UH1A
RTCX1 RTCX2 SRTCRST# INTRUDER# INTVRMEN RTCRST#
HDA_BCLK HDA_SYNC SPKR HDA_RST# HDA_SDI0 HDA_SDI1 HDA_SDI2 HDA_SDI3 HDA_SDO DOCKEN#/GPIO33 HDA_DOCK_RST#/GPIO13
JTAG_TCK JTAG_TMS JTAG_TDI JTAG_TDO TP25 TP22 TP20
LYNX-POINT-DH82LPMS_BGA695
HDA_SYNC
HDA_RST#
HDA_SDOUT
HDA_BIT_CLK
1
CH78 100P_0402_50V8J
2
@
For EMC
LPT_PCH_M_EDS
JTAGRTC AZALIA
REV = 5
SATA
SATALED#
SATA_IREF
TP9 TP8
BC8 BE8
AW8 AY8
BC10 BE10
AV10 AW10
BB9
SATA_PRX_DTX_N2
BD9
SATA_PRX_DTX_P2
AY13
SATA_PTX_DRX_N2
AW13
SATA_PTX_DRX_P2
BC12 BE12
AR13 AT13
BD13
SATA_PRX_DTX_N4
BB13
SATA_PRX_DTX_P4
AV15
SATA_PTX_DRX_N4
AW15
SATA_PTX_DRX_P4
BC14 BE14
AP15 AR15
AY5
SATA_COMP
AP3
HDD_LED#
AT1
PCH_GPIO21
AU2
PCH_GPIO19
BD4
SATA_IREF
BA2 BB2
SATA_RXN_0 SATA_RXP_0
SATA_TXN_0
SATA_TXP_0
SATA_RXN_1 SATA_RXP_1
SATA_TXN_1
SATA_TXP_1
SATA_RXN_2 SATA_RXP_2
SATA_TXN_2
SATA_TXP_2
SATA_RXN_3 SATA_RXP_3
SATA_TXN_3
SATA_TXP_3
SATA_RXN4/PERN1 SATA_RXP4/PERP1
SATA_TXN4/PETN1 SATA_TXP4/PETP1
SATA_RXN5/PERN2 SATA_RXP5/PERP2
SATA_TXN5/PETN2 SATA_TXP5/PETP2
SATA_RCOMP
SATA0GP/GPIO21 SATA1GP/GPIO19
1 OF 11
SATAImpedanceCompensation
SATA_COMP
CADnote: Placetheresistorwithin500milsofthePCH.Avoid routingnexttoclockpins.
1 2
1 1
RH8
1 2
RH15
1 2
RH17
1 2
RH19
TH1 TH2
7.5K_0402_1%
0_0402_5% PAD@
PAD@
+1.5VS
RH13
10K_0402_5% 10K_0402_5%
+1.5VS
1 2
10K_0402_5%
+3VS +3VS
Boot BIOS Strap bit0 BBS0
Bit11
SATA1GP /GPIO19
ODD
HDD
+3VS
Bit10
01
0
1 1
1
0
0
SATA_PRX_DTX_N2 42
SATA_PRX_DTX_P2 42 SATA_PTX_DRX_N2 42
SATA_PTX_DRX_P2 42
SATA_PRX_DTX_N4 42 SATA_PRX_DTX_P4 42
SATA_PTX_DRX_N4 42 SATA_PTX_DRX_P4 42
Boot BIOS Destination
Reserved Reserved SPI
*
LPC
(Default)
A A
Title
Title
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
5
4
3
2012/12/14
2012/12/14
2012/12/14
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2012/12/21
2012/12/21
2012/12/21
Title
PCH (1/9) RTC,HDA,SATA
PCH (1/9) RTC,HDA,SATA
PCH (1/9) RTC,HDA,SATA
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Friday, July 12, 2013
Friday, July 12, 2013
Date: Sheet
Date: Sheet
Date: Sheet
Friday, July 12, 2013
401025
401025
401025
1
13 61
13 61
13 61
of
of
of
1.1
1.1
1.1
5
+3VS
1 2
RH34
RH35
D D
RH36 RH37 RH38
1 2
1 2
150_0402_1%
1 2
150_0402_1%
1 2
150_0402_1%
2.2K_0402_5%
2.2K_0402_5%
PCH_CRT_B PCH_CRT_G PCH_CRT_R
PCH_CRT_DDC_CLK
PCH_CRT_DDC_DAT
PCH_CRT_B36 PCH_CRT_G36
PCH_CRT_R36 PCH_CRT_DDC_CLK36 PCH_CRT_DDC_DAT36
PCH_CRT_HSYNC36
PCH_CRT_VSYNC36
Change RH40,RH41,RH42 to 0ohm jump
1 2
C C
+3VS
B B
GPIO53 The signal has a weak internal pull-up. H DMI is in DC-coupling mode (desktop, mobile or server/workstation).
*
L DMI is in AC-coupling mode (server/workstation only, not meant for desktop/mobile).
DGPU_HOLD_RST#23
NVDD_PWR_EN46,58 DGPU_PWR_EN23,46
1 2
RH44 8.2K_0402_5%@
1 2
RH45 8.2K_0402_5%@
1 2
RH47 8.2K_0402_5%
1 2
RH48 8.2K_0402_5%UMA@
1 2
RH49 8.2K_0402_5%@
1 2
RH50 8.2K_0402_5%@
1 2
RH51 8.2K_0402_5%@
1 2
RH52 1K_0402_5%@
RH40 0_0402_5%@
NVDD_PWR_EN NVDD_PWR_EN_R DGPU_PWR_EN DGPU_PWR_EN_R
DGPU_GC6_EN27 PCH_WL_OFF#40
PPT EDS DOC#474146
PCH_GPIO51 DGPU_GC6_EN
PCH_WL_OFF# DGPU_PWR_EN_R DGPU_HOLD_RST#
DGPU_GC6_EN DGPU_HOLD_RST#
PCH_WL_OFF#
4
1 2
RH46 1K_0402_5%@
LPT_PCH_M_EV
LVDSCRT
UH1E
PCH_CRT_B PCH_CRT_G PCH_CRT_R
PCH_CRT_DDC_CLK PCH_CRT_DDC_DAT PCH_CRT_HSYNC PCH_CRT_VSYNC
1 2
RH39
649_0402_1%
PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD#
PCH_DGPU_HOLD_RST#
@
0_0402_5%
@
0_0402_5%
PCH_GPIO51 DGPU_GC6_EN PCH_WL_OFF#
PCH_EDP_PWM PCH_ENBKL PCH_ENVDD
PCH_EDP_PWM34 PCH_ENBKL34 PCH_ENVDD34
1 2
RH41
1 2
RH42
T45
VGA_BLUE
U44
VGA_GREEN
V45
VGA_RED
M43
VGA_DDC_CLK
M45
VGA_DDC_DATA
N42
VGA_HSYNC
N44
VGA_VSYNC
U40
DAC_IREF
U39
VGA_IRTN
N36
EDP_BKLTCTL
K36
EDP_BKLTEN
G36
EDP_VDDEN
H20
PIRQA#
L20
PIRQB#
K17
PIRQC#
M20
PIRQD#
A12
GPIO50
B13
GPIO52
C12
GPIO54
C10
GPIO51
A10
GPIO53
AL6
GPIO55
LYNX-POINT-DH82LPMS_BGA695
PCH_GPIO51
BootBIOSStrap
BBS_BIT1 (GPIO51)
*
SATA_SLPD (BBS_BIT0)
BootBIOSLocation
00 LPC
0 1 Reserved(NAND)
10
11 SPI
REV = 5
PCI
PCI
DISPLAY
3
DDPB_CTRLCLK
DDPB_CTRLDATA
DDPC_CTRLCLK
DDPC_CTRLDATA
DDPD_CTRLCLK
DDPD_CTRLDATA
5 OF 11
DDPB_AUXN DDPC_AUXN DDPD_AUXN DDPB_AUXP DDPC_AUXP DDPD_AUXP
DDPB_HPD DDPC_HPD DDPD_HPD
PIRQE#/GPIO2 PIRQF#/GPIO3 PIRQG#/GPIO4 PIRQH#/GPIO5
PME#
PLTRST#
R40 R39 R35 R36 N40 N38
H45 K43 J42 H43 K45 J44 K40 K38 H39
G17 F17 L15 M15 AD10 Y11
DDPB_CLK DDPB_DATA
TMDS_B_HPD
PCH_GPIO2 ODD_DA# PCH_GPIO4 PCH_GPIO5
PLT_RST#
1
PLT_RST#
+3VS
2
+3VS
1 2
RH32
RH33
DDPB_CLK 35 DDPB_DATA 35
DDPB_CTRLDATA The signal has a weak internal pull-down. H Port B is detected.
*
L Port B is not detected.
TMDS_B_HPD 35
ODD_DA# 42
PAD@
TH5
PLT_RST# 23,37,40,44
12
RH43 100K_0402_5%
RPH1
18
PCI_PIRQD#
27
PCI_PIRQA#
36
PCI_PIRQC#
45
PCI_PIRQB#
8.2K_8P4R_5% RPH2
18
PCH_GPIO4
27 36
PCH_GPIO2
45
8.2K_8P4R_5%
PCH_GPIO5
1 2
2.2K_0402_5%
2.2K_0402_5%
DDPB_CLK
DDPB_DATA
ODD_DA#
ForESD
1
CH6 220P_0402_50V7K
2
@
1
GPIO55 The signal has a weak internal pull-up. H Disable ' Top-Block Swap ' mode.
*
L Enable ' Top-Block Swap ' mode.
A A
Title
Title
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
3
2012/12/14
2012/12/14
2012/12/14
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2012/12/21
2012/12/21
2012/12/21
Title
PCH (2/9) CRT,DP,PCI
PCH (2/9) CRT,DP,PCI
PCH (2/9) CRT,DP,PCI
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Friday, July 12, 2013
Friday, July 12, 2013
Date: Sheet
Date: Sheet
Date: Sheet
Friday, July 12, 2013
401025
401025
401025
1
of
of
of
14 61
14 61
14 61
1.1
1.1
1.1
5
+3VS
1
CH7
.1U_0402_10V6-K
D D
C C
B B
VR_READY44,59
+3V_PCH
RH56
RH58 is 8.2K as intel check list, will test 10k in future
+3VALW
+3VS
1 2
RH58
RH54
1 2
RH59 10K_0402_5%
1 2
RH67
1 2
VR_READY PCH_PWROK
10K_0402_5%
200K_0402_5%
12
10K_0402_5%
10K_0402_5%
2
@
SUSWARN#
PCH_AC_PRESENT_R
PCH_PWROK
PCH_RSMRST#_R
SYS_RESET#
5
1
VCC
IN1
2
IN2
GND
3
@
MC74VHC1G08DFT2G_SC70-5
UH2
4
OUT
For Deep S3
SUSACK#44
SYS_PWROK6,44 PCH_PWROK8,44
APWROK can be connect to PWROK if iAMT disable
PBTN_OUT#44
AC_PRESENT44
+3VALW
+3V_PCH
PM_DRAM_PWRGD6
EC_RSMRST#44
SUSWARN#44
SYS_PWROK_R
12
@
RH53 100K_0402_5%
DMI_CTX_PRX_N05 DMI_CTX_PRX_N15
DMI_CTX_PRX_N25 DMI_CTX_PRX_N35
DMI_CTX_PRX_P05 DMI_CTX_PRX_P15
DMI_CTX_PRX_P25 DMI_CTX_PRX_P35
DMI_CRX_PTX_N05 DMI_CRX_PTX_N15
DMI_CRX_PTX_N25 DMI_CRX_PTX_N35
DMI_CRX_PTX_P05 DMI_CRX_PTX_P15
DMI_CRX_PTX_P25 DMI_CRX_PTX_P35
+1.5VS
+1.5VS
1 2
RH66
@
1 2
RH193 0_0402_5%@
1 2
RH70 0_0402_5%@
1 2
RH73 0_0402_5%@
1 2
RH74 0_0402_5%
1 2
RH75 0_0402_5%@
1 2
RH76 0_0402_5%@
1 2
RH77 8.2K_0402_5%
1 2
RH79 10K_0402_5%
Change RH62,RH193,RH70,RH71,RH73,RH75,RH76,RH60 to 0ohm jump
1 2
RH62 0_0402_5%@
1 2
RH64
0_0402_5%
4
PAD@ PAD@
7.5K_0402_1%
1 2
RH71
0_0402_5%
PAD@ PAD@
DMI_CTX_PRX_N0 DMI_CTX_PRX_N1
DMI_CTX_PRX_N2 DMI_CTX_PRX_N3
DMI_CTX_PRX_P0 DMI_CTX_PRX_P1
DMI_CTX_PRX_P2 DMI_CTX_PRX_P3
DMI_CRX_PTX_N0 DMI_CRX_PTX_N1
DMI_CRX_PTX_N2 DMI_CRX_PTX_N3
DMI_CRX_PTX_P0 DMI_CRX_PTX_P1
DMI_CRX_PTX_P2 DMI_CRX_PTX_P3
DMI_IREF
1
TH11
1
TH13
DMI_RCOMP
SUSACK#_R SYS_RESET# SYS_PWROK_R PWROK
@
APWROK PM_DRAM_PWRGD PCH_RSMRST#_R SUSWARN#_R
PM_PWRBTN#_R PCH_AC_PRESENT_R
PCH_GPIO72 RI#
1
TH17
1
TH19
UH1B
AW22
DMI_RXN_0
AR20
DMI_RXN_1
AP17
DMI_RXN_2
AV20
DMI_RXN_3
AY22
DMI_RXP_0
AP20
DMI_RXP_1
AR17
DMI_RXP_2
AW20
DMI_RXP_3
BD21
DMI_TXN_0
BE20
DMI_TXN_1
BD17
DMI_TXN_2
BE18
DMI_TXN_3
BB21
DMI_TXP_0
BC20
DMI_TXP_1
BB17
DMI_TXP_2
BC18
DMI_TXP_3
BE16
DMI_IREF
AW17
TP12
AV17
TP7
AY17
DMI_RCOMP
R6
SUSACK#
AM1
SYS_RESET#
AD7
SYS_PWROK
F10
PWROK
AB7
APWROK
H3
DRAMPWROK
J2
RSMRST#
J4
SUSWARN#/SUSPWRNACK/GPIO30
K1
PWRBTN#
E6
ACPRESENT/GPIO31
K7
BATLOW#/GPIO72
N4
RI#
AB10
TP21
D2
SLP_WLAN#/GPIO29
LYNX-POINT-DH82LPMS_BGA695
LPT_PCH_M_EDS
DMI
System Power
Management
REV = 5
3
FDI
SUS_STAT#/GPIO61
FDI_RXN_0 FDI_RXN_1
FDI_RXP_0 FDI_RXP_1
FDI_CSYNC
FDI_RCOMP
DSWVRMEN
SUSCLK/GPIO62 SLP_S5#/GPIO63
SLP_SUS# PMSYNCH SLP_LAN#
4 OF 11
AJ35
FDI_CTX_PRX_N0
AL35
FDI_CTX_PRX_N1
AJ36
FDI_CTX_PRX_P0
AL36
FDI_CTX_PRX_P1
AV43
TP16
AY45
TP5
AV45
TP15
AW44
TP10
AL39 AL40
FDI_INT
AT45
FDI_IREF
AU42
TP17
AU44
TP13
AR44
C8 L13
DPWROK
K3
WAKE#
AN7
CLKRUN#
U7 Y6 Y7 C6
SLP_S4#
H1
SLP_S3#
F3
SLP_A#
F1 AY3 G5
Can be left NC if no use integrated LAN.
1
TH6
1
TH7
1
TH8
1
TH9
FDI_CSYNC FDI_INT
1 2
FDI_IREF
RH60
1
TH10
1
TH12
FDI_RCOMP
DSWODVREN PCH_DPWROK_R
PM_CLKRUN# SUS_STAT# SUSCLK PM_SLP_S5# PM_SLP_S4# PM_SLP_S3#
1 2
RH63
7.5K_0402_1%
RH239 0_0402_5%
RH68 0_0402_5%@ RH69 0_0402_5%
1
TH14
1
TH15
Can be left NC when IAMT is not support on the platfrom
PM_SLP_SUS#_R H_PM_SYNC
1
RH78 0_0402_5%@
TH18
PAD@ PAD@ PAD@ PAD@
0_0402_5%@ PAD@ PAD@
1 2
1 2 1 2
PAD@
PAD@
PM_SLP_S5# 44 PM_SLP_S4# 44 PM_SLP_S3# 44
1 2
H_PM_SYNC 6
PAD@
2
FDI_CTX_PRX_N0 8 FDI_CTX_PRX_N1 8 FDI_CTX_PRX_P0 8 FDI_CTX_PRX_P1 8
FDI_CSYNC 5 FDI_INT 5
+1.5VS
+1.5VS
1
+RTCVCC
12
RH55 330K_0402_5%
DSWODVREN
DSWODVREN - On Die DSW VR Enable H Enable　
*
L Disable　
12
RH57 330K_0402_5%
@
RH61 is 1% as check list request, CRB is 5%. follow CRB
1 2
RH61 100K_0402_5%
+3VS
1 2
RH65 8.2K_0402_5%
For Deep S3
note need connect to GPIO27
@
1 2
RH72 10K_0402_5%
For Deep S3
1 2
RH80 10K_0402_5%
+3VALW
+3V_PCH
EC_RSMRST#
DPWROK_EC PCIE_WAKE#WAKE#
PCH_DPWROK_R
PM_CLKRUN#
DPWROK_EC 44 PCIE_WAKE# 19,37,40,44
SUSCLK
SUSCLK/GPIO62 - (Have weak internal pull-up) PLL On-Die Voltage Regulator Enable H Enable　
*
L Disable　
PM_SLP_SUS# 44,46
WAKE#
AS EMC request
PCH_PWROK SYS_PWROK_R PCH_DPWROK_R
1
CH83
A A
.1U_0402_10V6-K
5
2
.1U_0402_10V6-K
CH84
1
2
.1U_0402_10V6-K
CH85
1
2
Title
Title
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
3
2012/12/14
2012/12/14
2012/12/14
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2012/12/21
2012/12/21
2012/12/21
Title
PCH (3/9) DMI,FDI,PM
PCH (3/9) DMI,FDI,PM
PCH (3/9) DMI,FDI,PM
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Friday, July 12, 2013
Friday, July 12, 2013
Date: Sheet
Date: Sheet
Date: Sheet
Friday, July 12, 2013
401025
401025
401025
1
of
of
of
15 61
15 61
15 61
1.1
1.1
1.1
5
4
3
2
1
UH1C
D D
PCH_GPIO18
PCH_GPIO20
LAN
WLAN
C C
CLK_PCI_EC44
RH84 22_0402_5%
CLK_PCIE_LAN#37 CLK_PCIE_LAN37
CLKREQ_LAN#37
CLK_PCIE_WLAN#40 CLK_PCIE_WLAN40 WLAN_CLKREQ1#40
1 2
1 2
RH87 22_0402_5%
CLK_PCIE_LAN# CLK_PCIE_LAN CLKREQ_LAN#
CLK_PCIE_WLAN# CLK_PCIE_WLAN WLAN_CLKREQ1#
PCH_GPIO44
PCH_GPIO45
PCH_GPIO46
CLK_PCI_EC_R
PCI_LOOPBACKOUTCLK_PCI_LOOPBACK
PCH_GPIO73
Y43
CLKOUT_PCIE_N_0
Y45
CLKOUT_PCIE_P_0
AB1
PCIECLKRQ0#/GPIO73
AA44
CLKOUT_PCIE_N_1
AA42
CLKOUT_PCIE_P_1
AF1
PCIECLKRQ1#/GPIO18
AB43
CLKOUT_PCIE_N_2
AB45
CLKOUT_PCIE_P_2
AF3
PCIECLKRQ2#/GPIO20/SMI#
AD43
CLKOUT_PCIE_N_3
AD45
CLKOUT_PCIE_P_3
T3
PCIECLKRQ3#/GPIO25
AF43
CLKOUT_PCIE_N_4
AF45
CLKOUT_PCIE_P_4
V3
PCIECLKRQ4#/GPIO26
AE44
CLKOUT_PCIE_N5
AE42
CLKOUT_PCIE_P_5
AA2
PCIECLKRQ5#/GPIO44
AB40
CLKOUT_PCIE_N_6
AB39
CLKOUT_PCIE_P_6
AE4
PCIECLKRQ6#/GPIO45
AJ44
CLKOUT_PCIE_N_7
AJ42
CLKOUT_PCIE_P_7
Y3
PCIECLKRQ7#/GPIO46
AH43
CLKOUT_ITPXDP_N
AH45
CLKOUT_ITPXDP_P
D44
CLKOUT_33MHZ0
E44
CLKOUT_33MHZ1
B42
CLKOUT_33MHZ2
F41
CLKOUT_33MHZ3
A40
CLKOUT_33MHZ4
CLOCK SIGNAL
LYNX-POINT-DH82LPMS_BGA695
LPT_PCH_M_EDS
REV = 5
PEG_A_CLKRQ#/GPIO47
PEG_B_CLKRQ#/GPIO56
CLKIN_33MHZLOOPBACK
2 OF 11
CLKOUT_PEG_A_N
CLKOUT_PEG_A_P
CLKOUT_PEG_B_N
CLKOUT_PEG_B_P
CLKOUT_DMI_N CLKOUT_DMI_P
CLKOUT_DP_N CLKOUT_DP_P
CLKOUT_DPNS_N CLKOUT_DPNS_P
CLKIN_DMI_N CLKIN_DMI_P
CLKIN_GND_N CLKIN_GND_P
CLKIN_DOT96N CLKIN_DOT96P
CLKIN_SATA_N CLKIN_SATA_P
REFCLK14IN
XTAL25_IN
XTAL25_OUT CLKOUTFLEX0/GPIO64 CLKOUTFLEX1/GPIO65 CLKOUTFLEX2/GPIO66 CLKOUTFLEX3/GPIO67
ICLK_IREF
TP19 TP18
DIFFCLK_BIASREF
AB35
CLK_PCIE_VGA#
AB36
CLK_PCIE_VGA
AF6
CLK_REQ_GPU#_R
Y39 Y38 U4
CLK2_REQ_GPU#_R
AF39
CLK_CPU_DMI#
AF40
CLK_CPU_DMI
AJ40
CLK_CPU_SSC_DPLL#
AJ39
CLK_CPU_SSC_DPLL
AF35
CLK_CPU_DPLL#
AF36
CLK_CPU_DPLL
AY24
CLK_BUF_CPU_DMI#
AW24
CLK_BUF_CPU_DMI
AR24
CLKIN_DMI2#
AT24
CLKIN_DMI2
H33
CLK_BUF_DREF_96M#
G33
CLK_BUF_DREF_96M
BE6
CLK_BUF_PCIE_SATA#
BC6
CLK_BUF_PCIE_SATA
F45
CLK_BUF_ICH_14M
D17
CLK_PCI_LOOPBACK
AM43
XTAL25_IN
AL44
XTAL25_OUT
C40 F38 F36 F39
PCH_GPIO67
AM45
ICLK_IREF
AD39 AD38
AN44
PCH_CLK_BIASREF
RH83 10K_0402_5%
1 2
1
PAD@
TH22
1
PAD@
TH23
1 2
CLK_PCIE_VGA# 23 CLK_PCIE_VGA 23
1 2
RH81 10K_0402_5%
1 2
RH82 10K_0402_5%
CLK_CPU_DMI# 6 CLK_CPU_DMI 6
CLK_CPU_SSC_DPLL# 6 CLK_CPU_SSC_DPLL 6
CLK_CPU_DPLL# 6 CLK_CPU_DPLL 6
1 2
PCH_GPIO67 19
RH86
@
+1.5VS
RH88
0_0402_5%
7.5K_0402_1%
Change RH86 to 0ohm jump
+1.05V_+1.5V_RUN
+3V_PCH
+3V_PCH
CLK_BUF_CPU_DMI CLK_BUF_CPU_DMI# CLKIN_DMI2 CLKIN_DMI2#
CLK_BUF_DREF_96M# CLK_BUF_DREF_96M CLK_BUF_PCIE_SATA# CLK_BUF_PCIE_SATA
CLK_REQ_GPU#_R 23
RPH3
4 5 3 6 2 7 1 8
RPH4
4 5 3 6 2 7 1 8
10K_0804_8P4R_5%
10K_0804_8P4R_5%
B B
A A
+3V_PCH
1 2
RH89 10K_0402_5%
1 2
RH90 10K_0402_5%
1 2
RH91 10K_0402_5%
1 2
RH93 10K_0402_5%
1 2
RH94 10K_0402_5%
1 2
RH98 10K_0402_5%
+3VS
1 2
RH96 10K_0402_5%
1 2
RH97 10K_0402_5%
5
CLKREQ_LAN# WLAN_CLKREQ1# PCH_GPIO44
PCH_GPIO45 PCH_GPIO46 PCH_GPIO73
PCH_GPIO18 PCH_GPIO20
Reserve for EMI please close to PCH
3
CH8
1 2
22P_0402_50V8-J
@
2012/12/14
2012/12/14
2012/12/14
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
RH95
CLK_PCI_LOOPBACK
4
12
33_0402_5%
@
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
XTAL25_IN XTAL25_OUT
12P_0402_50V8-J
2012/12/21
2012/12/21
2012/12/21
2
CH9
1 2
RH92 1M_0402_5%
YH2
1
OSC1
1
2
GND12OSC2
25MHZ_10PF_7V25000014
Title
Title
Title
PCH (3/9) CLOCK
PCH (3/9) CLOCK
PCH (3/9) CLOCK
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
GND2
Friday, July 12, 2013
Friday, July 12, 2013
Friday, July 12, 2013
4 3
1
CH10
12P_0402_50V8-J
2
1.1
1.1
401025
401025
401025
1
16 61
16 61
16 61
1.1
of
of
of
5
LPC_AD044 LPC_AD144 LPC_AD244 LPC_AD344
D D
LPC_FRAME#44
SERIRQ44
SPI_CLK_PCH_0 SPI_CLK_PCH_1_R
SPI_SB_CS0#_R SPI_CS1#_R
SPI_SI_R SPI_SI_R1 SPI_SI
SPI_SO_L SPI_SO_L1
LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3
LPC_FRAME#
1 2
+3VS
RH104 10K_0402_5%
1 2
RH105 33_0402_5%
1 2
RH106 33_0402_5%
1 2
RH107 0_0402_5%@
1 2
RH108 0_0402_5%@
1 2
RH109 33_0402_5%
1 2
RH110 33_0402_5%
1 2
RH111 33_0402_5%
1 2
RH112 33_0402_5%
SERIRQ
SPI_CLK_PCH SPI_SB_CS0# SPI_CS1#
SPI_SO_R
Change RH107,RH108 to 0ohm jump
C C
SPI_CS1#_R44
SPI_SI_R144
SPI_SO_L144
SPI_CLK_PCH_144
SPI_CS1#_R
SPI_SI_R1
SPI_SO_L1
1 2
RH118 0_0402_5%
Change RH118 to 0ohm resistor from 0ohm jump
A20 C20 A18 C18 B21 D21
G20
AL11
AJ11
AJ7 AL7
AJ10
AH1 AH3
AJ4 AJ2
SPI_CLK_PCH_1_RSPI_CLK_PCH_1
4
UH1D
LAD_0 LAD_1 LAD_2 LAD_3 LFRAME# LDRQ0# LDRQ1#/GPIO23 SERIRQ
SPI_CLK SPI_CS0# SPI_CS1# SPI_CS2# SPI_MOSI SPI_MISO SPI_IO2 SPI_IO3
LYNX-POINT-DH82LPMS_BGA695
SPILPC
LPT_PCH_M_EDS
SMBus
C-Link
Thermal
REV = 5
SML1ALERT#/PCHHOT#/GPIO74
3 OF 11
3
SMBALERT#/GPIO11
SMBCLK
SMBDATA
SML0ALERT#/GPIO60
SML0CLK
SML0DATA
SML1CLK/GPIO58
SML1DATA/GPIO75
CL_CLK CL_DATA CL_RST#
TD_IREF
TP1 TP2 TP4 TP3
N7
PCH_GPIO11
R10
PCH_SMBCLK
U11
PCH_SMBDATA
N8 U8
SML0CLK
R7
SML0DATA
H6
PCH_HOT#
K6
SML1CLK
N11
SML1DATA
AF11 AF10 AF7
BA45 BC45 BE43 BE44 AY43
PCH_TD_IREF
DRAMRST_CNTRL_PCH 6
1
PAD@
TH24
1
PAD@
TH25
1
PAD@
TH26
1
PAD@
TH27
1 2
RH113 8.2K_0402_1%
+3V_PCH
1 2
RH114 2.2K_0402_5%
1 2
RH116 2.2K_0402_5%
PCH_SMBCLK
PCH_SMBDATA
2
PCH_GPIO11 DRAMRST_CNTRL_PCH SML0CLK SML0DATA PCH_HOT#
+3VS
6 1
5
QH1A 2N7002KDWH_SOT363-6
G
3 4
S
D
QH1B 2N7002KDWH_SOT363-6
2
G
S
D
1 2
RH99 10K_0402_5% RH100 1K_0402_5%
1 2
RH101 2.2K_0402_5%
1 2
RH102 2.2K_0402_5%
1 2
RH103 10K_0402_5%
2N7002KDWH Vth= min 1V, max 2.5V ESD 2KV
SMB_CLK_S3
SMB_DATA_S3
1
+3V_PCH
12
DIMM1, DIMM2, Mini CARD, TP
1 2
RH115 2.2K_0402_5%
1 2
RH117 2.2K_0402_5%
SMB_CLK_S3 11,12,40,45
SMB_DATA_S3 11,12,40,45
+3VS
For EMI
SPI_CLK_PCH_0 SPI_CLK_PCH_1_R
+3VS_PCH_VCCSPI +3VS_PCH_VCCSPI
1 2
RH123 3.3K_0402_5%
1 2
RH125 3.3K_0402_5%
UH3
SPI_SB_CS0#_R
B B
A A
SPI_SO_L SPI_WP#
1
CS
2
DO(IO1)
3
WP(IO2)
4
GND
W25Q16DVSSIG_SO8
5
HOLD(IO3)
DI(IO0)
8
VCC
7 6
CLK
5
ROMPWREN44
RH119 10_0402_5%
1 2
1
@
CH11
10P_0402_50V8J
2
SPI_WP# SPI_HOLD#
SPI_HOLD# SPI_WP#_1 SPI_CLK_PCH_0 SPI_SI_R
@
+3VS_PCH_VCCSPI
1
CH13 .1U_0402_10V6-K
2
ROMPWREN
@
12
RH192 0_0402_5%
SPI_CS1#_R SPI_SO_L1
1 2
RH237 10K_0402_5%@
1 2
@
RB751V-40_SOD323-2
1 2
0_0402_5%
4
RH124 3.3K_0402_5% RH126 3.3K_0402_5%
DH6
RH85
@
32Mb Flash ROM16Mb Flash ROM
1 2 1 2
UH4
1
CS
2
DO(IO1)
3
WP(IO2)
4
GND
W25Q32FVSSIG_SO8
CH80
4.7U_0603_6.3V6K
For EMI
HOLD/RST(IO3)
+3VALW
1
@
2
RH120 10_0402_5%
1 2
1
@
CH12
10P_0402_50V8J
2
1 2
0_0402_5%
LP2301ALT1G_SOT23-3
S
QH9
@
G
@
Issued Date
Issued Date
Issued Date
3
@
+3VS_PCH_VCCSPI
1
CH14 .1U_0402_10V6-K
2
RH235
D
13
2
1
CH81 .1U_0402_10V6-K
@
2
SPI_WP#_1 SPI_HOLD#_1
8
VCC
7
SPI_HOLD#_1
6
SPI_CLK_PCH_1_R
CLK
5
SPI_SI_R1
DI(IO0)
+3V_PCH +3VS_PCH_VCCSPI
+3VALW
RH191
100K_0402_5%
@
1 2
13
D
2
G
QH7
S
2N7002KW_SOT323-3
Security Classification
Security Classification
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
2012/12/14
2012/12/14
2012/12/14
+3V_PCH
1
PAD@
TH34
1 2
RH236
@
0_0402_5%
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
1 2
RH121 2.2K_0402_5%
1 2
RH122 2.2K_0402_5%
SML1CLK
SML1DATA
+3VS
2012/12/21
2012/12/21
2012/12/21
2
2
G
6 1
D
5
QH2A 2N7002KDWH_SOT363-6
G
3 4
S
D
QH2B 2N7002KDWH_SOT363-6
Title
Title
Title
PCH (5/9) LPC,SPI,SMBUS
PCH (5/9) LPC,SPI,SMBUS
PCH (5/9) LPC,SPI,SMBUS
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
GPU, EC, Thermal Sensor
+3VS
EC_SMB_CK2
S
EC_SMB_DA2
Friday, July 12, 2013
Friday, July 12, 2013
Friday, July 12, 2013
EC_SMB_CK2 23,39,44
EC_SMB_DA2 23,39,44
401025
401025
401025
1
17 61
17 61
17 61
of
of
of
1.1
1.1
1.1
5
4
3
2
1
UH1I
AW31
PERN1/USB3RN3
AY31
PERP1/USB3RP3
BE32
PETN1/USB3TN3
BC32
D D
1 2
RH128
0_0402_5%
PAD@
PAD@
1 2
RH129
PCIE_PRX_DTX_N4 PCIE_PRX_DTX_P4
PCIE_PTX_DRX_N4 PCIE_PTX_DRX_P4
PCIE_PRX_DTX_N5 PCIE_PRX_DTX_P5
PCIE_PTX_DRX_N5 PCIE_PTX_DRX_P5
PCH_PCIE_IREF
TH32
TH33
PCH_PCIE_RCOMP
7.5K_0402_1%
1
1
PCIE_PRX_DTX_N437
LAN
WLAN
C C
PCIE_PRX_DTX_P437 PCIE_PTX_C_DRX_N437
PCIE_PTX_C_DRX_P437 PCIE_PRX_DTX_N540
PCIE_PRX_DTX_P540 PCIE_PTX_C_DRX_N540
PCIE_PTX_C_DRX_P540
1 2
CH15 .1U_0402_10V6-K
1 2
CH16 .1U_0402_10V6-K
1 2
CH17 .1U_0402_10V6-K
1 2
CH18 .1U_0402_10V6-K
Change RH128 to 0ohm jump
+1.5VS
+1.5VS
B B
@
PETP1/USB3TP3
AT31
PERN2/USB3RN4
AR31
PERP2/USB3RP4
BD33
PETN2/USB3TN4
BB33
PETP2/USB3TP4
AW33
PERN_3
AY33
PERP_3
BE34
PETN_3
BC34
PETP_3
AT33
PERN_4
AR33
PERP_4
BE36
PETN_4
BC36
PETP_4
AW36
PERN_5
AV36
PERP_5
BD37
PETN_5
BB37
PETP_5
AY38
PERN_6
AW38
PERP_6
BC38
PETN_6
BE38
PETP_6
AT40
PERN_7
AT39
PERP_7
BE40
PETN_7
BC40
PETP_7
AN38
PERN_8
AN39
PERP_8
BD42
PETN_8
BD41
PETP_8
BE30
PCIE_IREF
BC30
TP11
BB29
TP6
BD29
PCIE_RCOMP
LYNX-POINT-DH82LPMS_BGA695
LPT_PCH_M_EDS
REV = 5
PCIe
USB
9 OF 11
USB2N0 USB2P0 USB2N1 USB2P1 USB2N2 USB2P2 USB2N3 USB2P3 USB2N4 USB2P4 USB2N5 USB2P5 USB2N6 USB2P6 USB2N7 USB2P7 USB2N8 USB2P8 USB2N9 USB2P9
USB2N10
USB2P10
USB2N11
USB2P11
USB2N12
USB2P12
USB2N13
USB2P13
USB3RN1 USB3RP1 USB3TN1 USB3TP1 USB3RN2 USB3RP2 USB3TN2 USB3TP2 USB3RN5 USB3RP5 USB3TN5 USB3TP5 USB3RN6
USB3RP6 USB3TN6 USB3TP6
USBRBIAS#
USBRBIAS
TP24 TP23
OC0#/GPIO59 OC1#/GPIO40 OC2#/GPIO41 OC3#/GPIO42 OC4#/GPIO43
OC5#/GPIO9 OC6#/GPIO10 OC7#/GPIO14
B37
USB20_N0
D37
USB20_P0
A38
USB20_N1
C38
USB20_P1
A36
USB20_N2
C36
USB20_P2
A34 C34 B33
USB20_N4
D33
USB20_P4
F31
USB20_N5
G31
USB20_P5
K31 L31
Some PCH config not support USB port 6 & 7.
G29 H29 A32
USB20_N8
C32
USB20_P8
A30 C30 B29 D29 A28 C28 G26 F26 F24 G24
AR26 AP26 BE24 BD23 AW26 AV26 BD25 BC24 AW29 AV29 BE26 BC26 AR29 AP29 BD27 BE28
K24 K26
M33 L33
P3 V1 U2 P1 M3 T1 N2 M1
1
1
USB20_N10 USB20_P10
USB30_RX_N1 USB30_RX_P1 USB30_TX_N1
USB30_TX_P1 USB30_RX_N2 USB30_RX_P2 USB30_TX_N2
USB30_TX_P2
USBRBIAS
Within 500 mils
1 1
USB_OC0# USB_OC1# USB_OC2# USB_OC3# USB_OC4# USB_OC5# USB_OC6# USB_OC7#
TH28 TH29
TH30 TH31
USB20_N0 34 USB20_P0 34 USB20_N1 41 USB20_P1 41 USB20_N2 41 USB20_P2 41
USB20_N4 45 USB20_P4 45 USB20_N5 45 USB20_P5 45
USB20_N8 34 USB20_P8 34
PAD@ PAD@
USB20_N10 40 USB20_P10 40
USB30_RX_N1 41 USB30_RX_P1 41 USB30_TX_N1 41
USB30_TX_P1 41 USB30_RX_N2 41 USB30_RX_P2 41 USB30_TX_N2 41
USB30_TX_P2 41
1 2
RH127
22.6_0402_1% PAD@ PAD@
USB_OC1# 41 USB_OC2# 45
Camera LEFT USB (3.0)
LEFT USB (3.0)
Card reader RIGHT USB (2.0)
Touch screen
Debug port, reserved test point
Buletooth
USB3.0
USB_OC4# USB_OC7# USB_OC6# USB_OC3#
USB_OC0# USB_OC5# USB_OC2# USB_OC1#
LEFT USB
LEFT USB
4 5 3 6 2 7 1 8
4 5 3 6 2 7 1 8
RPH5
10K_1206_8P4R_5% RPH6
10K_1206_8P4R_5%
Port1
Port2
Port5
Port6
+3V_PCH
A A
Title
Title
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
3
2012/12/14
2012/12/14
2012/12/14
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2012/12/21
2012/12/21
2012/12/21
Title
PCH (5/9) PCI, USB
PCH (5/9) PCI, USB
PCH (5/9) PCI, USB
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Friday, July 12, 2013
Friday, July 12, 2013
Date: Sheet
Date: Sheet
Date: Sheet
Friday, July 12, 2013
401025
401025
401025
1
of
of
of
18 61
18 61
18 61
1.1
1.1
1.1
5
CMOS_ON#34
1 2
+3VS
1 2
RH133
+3V_PCH
D D
C C
1 2
RH135
1 2
RH140 1K_0402_5%
@
Place CH82 close to R23
CMOS_ON#
CH82
0.01U_0402_25V7K
GPIO28 On-Die PLL Voltage Regulstor (Have internal Pull-High) High: VCCVRM VR Enable
*
Low: VCCVRM VR Disable
EC_SCI#
10K_0402_5%
EC_SMI#
10K_0402_5%
1
2
1 2
RH160 1K_0402_5%
@
GC6_EVENT#23,44
+3VS
+3VS
+3V_PCH
EC_LID_OUT#44
+3VS_VGA
DGPU_PWROK27,46,57,58
PCH_BT_DISABLE#40 ODD_EN42
PCIE_WAKE#15,37,40,44
PCH_BT_ON#40
+3V_PCH
PCH_GPIO28
RH132 10K_0402_5%
FB_CLAMP23,27,44
RH139 10K_0402_5% RH136 10K_0402_5%
RH137 10K_0402_5%@ RH138 10K_0402_5%
RH142 10K_0402_5%
RH144 10K_0402_5%
+3VS
RH147 10K_0402_5%
+3V_PCH
RH148 10K_0402_5%
+3VS
RH149 10K_0402_5%@
+3VS
RH151 10K_0402_5%
+3VS
RH154 10K_0402_5%
RH156
@
1 2
1 2
1 2 1 2
1 2 1 2
1 2 1 2
RH143
0_0402_5%
1 2
1 2
RH146
1 2 1 2 1 2
1 2 1 2
1 2
RH134
@
0_0402_5%
ODD_DETECT#42
RH131
0_0402_5%
EC_SCI#44 EC_SMI#44
10K_0402_5%
0_0402_5%
@
+3VS
@
@
1 2
4
RH130 0_0402_5%
GC6_EVENT#_R
PCH_GPIO1 PCH_GPIO6 EC_SCI# EC_SMI# PCH_GPIO12 EC_LID_OUT#
PCH_GPIO16 PCH_DGPU_PWROK PCH_BT_DISABLE#
DS3_WAKE#_R
PCH_GPIO28
PCH_BT_ON#
PCH_GPIO35
ODD_DETECT#
PCH_GPIO37 PCH_GPIO38 PCH_GPIO39 PCH_GPIO48 PCH_GPIO49 PCH_GPIO57 PCH_GPIO68 PCH_GPIO69 PCH_GPIO70 PCH_GPIO71
1 2
RH161
1 2
RH162
PCH_GPIO68CMOS_ON#
Change RH130,RH143 to 0ohm jump
UH1F
AT8
BMBUSY#/GPIO0
F13
TACH1/GPIO1
A14
TACH2/GPIO6
G15
TACH3/GPIO7
Y1
GPIO8
K13
LAN_PHY_PWR_CTRL/GPIO12
AB11
GPIO15
AN2
SATA4GP/GPIO16
C14
TACH0/GPIO17
BB4
SCLOCK/GPIO22
Y10
GPIO24
R11
GPIO27
AD11
GPIO28
AN6
GPIO34
AP1
GPIO35/NMI#
AT3
SATA2GP/GPIO36
AK1
SATA3GP/GPIO37
AT7
SLOAD/GPIO38
AM3
SDATAOUT0/GPIO39
AN4
SDATAOUT1/GPIO48
AK3
SATA5GP/GPIO49
U12
GPIO57
C16
TACH4/GPIO68
D13
TACH5/GPIO69
G13
TACH6/GPIO70
H15
TACH7/GPIO71
BE41
VSS_NCTF_1
BE5
VSS_NCTF_2
C45
VSS_NCTF_3
A5
VSS_NCTF_4
LYNX-POINT-DH82LPMS_BGA695
PCH_GPIO68
10K_0402_5%
PCH_GPIO69
10K_0402_5%
LPT_PCH_M_EDS
REV = 5
GPIO
3
CPU/Misc
AN10
TP14 PECI
RCIN#
PROCPWRGD
THRMTRIP#
PLTRST_PROC#
VSS_N10
VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8
VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 VSS_NCTF_15 VSS_NCTF_16 VSS_NCTF_17 VSS_NCTF_18 VSS_NCTF_19 VSS_NCTF_20 VSS_NCTF_21
6 OF 11
VSS_NCTF_22 VSS_NCTF_23 VSS_NCTF_24
NCTF
GATEA20_PCH
AY1 AT6
KBRST#
AV3 AV1
PCH_THRMTRIP#_R H_THRMTRIP#
AU4
CPU_PLTRST#
N10
A2 A41 A43 A44 B1 B2 B44 B45 BA1 BC1 BD1 BD2 BD44 BD45 BE2 BE3 D1 E1 E45 A4
Change RH194 to 0ohm jump
1 2
RH141 10K_0402_5%
1 2
RH194
@
0_0402_5%
KBRST# 44
390_0402_5%
CPU_PLTRST# 6
H_CPUPWRGD 6
1 2
RH145
2
+3VS
GATEA20 44
H_THRMTRIP# 6
PCH_THRMTRIP#_R 23
SKU ID
PCH_GPIO6716
AS EMC request
KBRST#
.1U_0402_10V6-K
PCH_GPIO38 PCH_GPIO67 PCH_GPIO70 PCH_GPIO71
CH86
RH152
@
RH157
@
1
2
PCH_THRMTRIP#_R
+3VS
RH150
RH155
RH153
@
1 2
1 2
10K_0402_5%
RH158
RH159
@
1 2
1 2
10K_0402_5%
1 2
+3VS
RH163
@
1 2
10K_0402_5%
RH195
@
1 2
10K_0402_5%
1 2
RH234 1K_0402_5%@
@
1 2
10K_0402_5%
10K_0402_5%
@
1 2
10K_0402_5%
10K_0402_5%
KBRST#
10K_0402_5%
1
+1.05VS
PCH_GPIO27 (Have internal Pull-High) High: VCCVRM VR Enable
*
B B
A A
Low: VCCVRM VR Disable
+3VALW
1 2
RH166 10K_0402_5%
1 2
RH169
1 2
RH170
GPIO37 H Enable Intel ME Crypto Transport Layer Security
(TLS) cipher suite (with confidentiality) L Disable Intel ME Crypto Transport Layer Security
*
(TLS) cipher suite (no confidentiality)
10K_0402_5%
10K_0402_5%
5
ODD_DETECT#
PCH_GPIO37
DS3_WAKE#_R
GPIO36 DMI RX termination Strap (Rising edge of PWROK)
If DMI is operating in DC-coupled mode (e.g. Client applications), then DMI RX is terminated to VSS and the value of this strap is ignored by the PCH and does not take effect.
USB3 1
+3VS
RH164 RH165
RH167 RH168
FixedSignals
USB3 2
4
USB3 5
1 2 1 2
1 2
@
1 2
@
USB3 6
PCH_GPIO16
10K_0402_5%
PCH_GPIO49
10K_0402_5%
PCH_GPIO16
10K_0402_5%
PCH_GPIO49
10K_0402_5%
Config
SATA4,SATA5
*
MuxedSignals
PCIE
PCIE
1
2
(00)
(00)
USB3
USB3
3
4
(01)
(01) (0b) (0b)
PCIE 3
FixedSignals
PCIE
PCIE
4
5
PCIE 6
PCIE 7
GPIO16,49
11
00PCIE1,PECI2
PCIE 8
MuxedSignals
SATA
SATA
4
5
(1b)
(1b)
PCIE
PCIE
1
2
3
Function
UMA 14"
UMA 15"
14" VRAM 900MHz
14"
VRAM 1GHz
FixedSignals
SATA
SATA 0
SATA
1
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
SATA
2
3
2012/12/14
2012/12/14
2012/12/14
15" VRAM 900MHz
15"
VRAM 1GHz
UMA 15"
Touch
VRAM 900MHz15"
15" VRAM 1GHz
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
Touch
Touch
2012/12/21
2012/12/21
2012/12/21
PCH_GPIO38
PCH_GPIO67
00
10
10
1
PCH_GPIO70
0
10
0
0
011
1
1
1
PCH_GPIO71
0
0
0
0
0
0
1010
1110
1111
Title
Title
Title
PCH (6/9) GPIO, CPU, MISC
PCH (6/9) GPIO, CPU, MISC
PCH (6/9) GPIO, CPU, MISC
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
Friday, July 12, 2013
Friday, July 12, 2013
Friday, July 12, 2013
Date: Sheet
Date: Sheet
Date: Sheet
401025
401025
401025
1
19 61
19 61
19 61
1.1
1.1
1.1
of
of
of
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