COMPAL NM-A141 Schematic

A

1 1

B

C

D

E

QIQY5

Whisky3.0 (Y400S)

2 2

NM-A141 Rev0.2 Schematic

Intel IVY Bridge Processor with DDRIII + Panther Point PCH

3 3

4 4

A

nVIDIA N14P GT + 2nd VGA N14P GT

2012-10-25-Rev0.2

Security Class ification

Security Class ification

Security Class ification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2011/11/ 01

2011/11/ 01

2011/11/ 01

C

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2012/12/ 31

2012/12/ 31

2012/12/ 31

D

Title

Title

Title

COVER PAGE

COVER PAGE

COVER PAGE

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Monday, January 14, 2013

Monday, January 14, 2013

Monday, January 14, 2013

Y400S-NM-A141

Y400S-NM-A141

Y400S-NM-A141

E

1 65

1 65

1 65

of

of

of

1.0

1.0

1.0

A

B

C

D

E

PCI-Express 16X Gen3

EG 8~15

2nd VGA, N14P-GT1

1 1

Sub/B

VRAM 64*32

GDDR5* 8

Page 32 Page 23,24,25,26,27,28,29,30,31

VRAM 64*32

GDDR5* 8

PEG 0~7P

N14P-GT1

Intel CPU
Ivy Bridge

rPGA-989

37.5mm*37.5mm

age 5,6,7,8,9,10,11

P

Memory BUS (DDRIII)
Dual Channel

1.5V DDRIII 1066/1333/1600 MT/s

DDR3-SO-DIMM X2

BANK 0, 1, 2, 3

UP TO 16G

FDI *8

2.7GT/s

HDMI Conn.

Page 36 P

HDMI1.4b

2 2

RJ45 Conn.

Page 39

CRT Conn.

age 35 Page 34

Atheros
A

R8161 1G

AR8151 1G

PCIe port 1

LVDS Conn.

Page 38

PCIe Gen1 1x

1.5V 5GT/s

Intel PCH

anther Point

P

FCBGA-989 Balls
25mm*25mm

CardReader
JMB38C
SD/MMC/MS/XD

PCIe port 4

3 3

(4

Page 44

SPI ROM

MB+2MB)

Page 14

PCIe Gen1 1x

1.5V 5GT/s

SPI BUS

3.3V 33MHz

Page 14,15,16,17,18,19,20,21,22

LPC BUS

3.3V 33MHz

DMI *4
5GT/s

USB 2.0 4x
5V

480MHz

USB 3.0 2x

5V 5GT/s

USB 2.0 1x
5V 480MHz

PCIe Gen1 1x
5V 480MHz

SATA Gen3 Port 0
5V 6GHz(600MB/s)

SATA Gen3 Port 1
5V 6GHz(600MB/s)

SATA Gen1 Port2

3GHz(300MB/s)

5V

HD Audio

24MHz

3.3V

USB Left

USB 2.0 Port 2
USB 3.0 Port 2

Int. Camera

USB 3.0 Port 0

PCIeMini Card

AN

WL

PCIeMini Card
WLAN

SATA HDD

SATA ODD

USB Right

USB 2.0 Port 9

Page 48 Page 49

Page 34

USB 2.0 Port 5, Cha

Sub/B

BT

SB 2.0 Port 13

U

mSATA SSD

PCIe Port 2

page 37

USB Port 10

page 37

SATA Port 1

page 41

SATA Port 1

page 41

Page 47

SATA Port 0

page 37

Debug Port

Page 45

Power Circuit DC/DC

Page 52,53 ,54,55,56, 57,

58,59,60,6 1,62

4 4

DC/DC Interface CKT.

POWER/B Conn. AUDIO, USB/B Conn.

ODD/B Conn.

Page 51

Page 40 Page 49

page 41

A

RTC CKT.

NOVO/B Conn.

Page 52

Page 40

Touch Pad

Page 46

B

EC

E IT8580E-HX

IT

Page 45

Int.KBD

Page 46

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

C

Thermal Sensor

EMC 1403

Page 40

LC Future Center Secret Data

LC Future Center Secret Data

2011/11/01

2011/11/01

2011/11/01

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Codec

A

LC269Q-VC3

Int. MIC Conn.
(JCMOS Conn.)

Page 34 Page 49

2012/12/31

2012/12/31

2012/12/31

D

age 42

P

AMP

MA

X98400B

Page 43

Ext. MIC Conn.

Su

b/B

Title

Title

Title

BlOCK DIAGRAM

BlOCK DIAGRAM

BlOCK DIAGRAM

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Monday, January 14, 2013

Monday, January 14, 2013

Monday, January 14, 2013

HP Conn.

ub/B

S

Y400S-NM-A141

Y400S-NM-A141

Y400S-NM-A141

SPK Conn.

Page 49

E

Page 43

of

of

of

2 65

2 65

2 65

1.0

1.0

1.0

A

B

C

D

E

Voltage Rails

( O --> Means ON ,

Power Plane

1 1

B+

S

tate

S0

S

3

2 2

S5 S4/AC Only

S5 S4

Battery only

O

O

O

O

S5 S4
AC & Battery
don't exist

MBUS Control Table

S

SOURCE

3 3

IT

8580EEC_SMB_CK1

EC_SMB_DA1

EC_SMB_CK2

C_SMB_DA2

E

SMB_CLK_S3
S

MB_DATA_S3

+3VALW

IT8580E

+3VS

PCH

+3VS

X X

Main
V

GA

X

V

+3VS +3VS

X X

X --> Means OFF )

+5VS

+3VS

+1.5VS

+VCCSA

+V1.5S_VCC P

+3VALW

+1.5V

+5VALW

+CPU_CORE

+VGA_CORE

GFX_CORE

+

+1.8VS

+1.05VS

+0.75VS

+3.3VS_VGA

+1.5VS_VGA

+1.05VS_VG A

O O O

OO

O

X

X X

X

2nd
VGA

BATT SODIMM

IT8580E

X X

+3VALW

V

X

X

X X X

X

X

V V

+3VS

WLAN
WiMAX

X

X

V

X

X

X

X

Thermal
Sensor

V

+3VS

PCH

XV

V

+3V_PCH

+3V_PCH+3VS

IGNAL

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

S

USB Port Table

USB 3.0USB 2.0 Port

XHCI

EHCI1

EHCI2

TP

Mo

dule

XX

X

V

+3VS

SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

ON

HIGH HIGH HIGH HIGH

LOW

LOW

LOW

LOW LOW LOW LOW

0

1

1

2

2

3

3

4

4
5
6

USB Port (Left Side)

USB Port (Right Side)

7

8
9

USB Port (Right Side)

10

Mini Card(WLAN)

11
12
13

HIGH

LOWLOWLOW

4 External
USB Port

Camera

Blue Tooth

HIGHHIGHHIGH

HIGH

HIGH

ON

ON

ON

ON

ON

ON

OFF

ON

OFF

BOM Structure Table

HDMI@

CHG@

NOCHG@
CMOS@
8161@
8151@
8161S@
8151S@

SURGE@

61@
51@
X76@

GC6@

NOGC6@
AOAC@

KBL@
ME@

OPT@

PCIE PORT LIST

Port Device

1

LAN

2

WLAN

3
4

Card Reader

SLI@

DS3@

S3@

GT@

@

5
6
7
8

ON ON

ON

OFF

OFF

OFF

LOW

OFF

OFF

OFF

BTO ItemBOM Structure

HDMI part

USB charger part

No USB charger part

CMOS Camera part

AR8161 LAN part

AR8151 LAN part

AR8161 LAN surge part

A

R8151 LAN surge part

AR8151&8161 LAN surge part --> Delete (201200627)

X76 P/N for AR8161

X76 P/N for AR8151

X76 Level part for VRAM

NV CG6 support part

NV no CG6 support part
AOAC support part

K/B Light part

ME part

For optimus function part

For SLI function part

Deep S3 support part

For S3 function part

NV chip part

Unpop

A

Address

0001 011X b

EC SM Bus2 address

Device

Thermal Sen sor EMC1403-2

Master VGA

Slave VGA

B

Address

1001_101xb

0x9E

0x9C

PCH SM Bus address

Device Address

DDR DIMM0

DDR DIMM2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

C

1001 000Xb

1001 010Xb

2011/11/01

2011/11/01

2011/11/01

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

2012/12/31

2012/12/31

2012/12/31

4 4

EC SM Bus1 address

Device

Smart Battery

ZZZ1

DAZ00200100

Title

Title

Title

NOTES LIST

NOTES LIST

NOTES LIST

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Tuesday, March 12, 2013

Tuesday, March 12, 2013

Tuesday, March 12, 2013

Y400S-NM-A141

Y400S-NM-A141

Y400S-NM-A141

E

of

of

of

3 65

3 65

3 65

1.0

1.0

1.0

5

ot plug detect for IFP link E

H

VGA and GDDR5 Voltage Rails (N13Px GPIO)

GPIO I/O ACTIVE Function Description

PIO0

+3VS_VGA

+VGA_CORE

+1.5VS_VGA

+1.05VS_VGA

OUT FB_CLAMP-

OUT

-

OUT

OUT

OUT

OUT

OUT

OUT

I/O

OUT

OUT

VGA_BL_PWM

-

VGA_ENVDD

-

- V

GA_ENBKL

-

FB_CLAMP_TOGGLE_REQ#

-

-

-

OVERT#

-

VGA_ALERT#

-

Memory VREF Control

NVVDD PWM_VID-OUT

-

N

N/A

-

/A

-

-

VGA_AC_DET_R

DPRSLPVR_VGA-

dGPU_HDMI_HPD

tNVVDD >0

tFBVDDQ >0

tPEX_VDD >0

IN

OUT

OUT

IN

OUT

IN

IN

IN

1. all power ra il ramp up tim e should be la rger than 40us

(10K pull High)

G

D D

GPIO1

GPIO2

GPIO3

GPIO4

GPIO5

GPIO6

GPIO7

GPIO8

GPIO9

GPIO10

C C

GPIO11

GPIO12

GPIO13

GPIO14

GPIO15

GPIO16

GPIO17

GPIO18

GPIO19

B B

4

3

2

1

Performance Mode P0 TDP at Tj = 102 C* (GDDR5)

GPU Mem NVCLK
(4) (1,5) (6)

Products

(W) (W) (MHz)

N13X
128bit
1GB
GDDR5

Physical
Strapping pin

ROM_SCLK

ROM_SI

ROM_SO FB[0]

STRAP0

STRAP1

STRAP2

STRAP3

STRAP4

/MCLK NVVDD

(V) (A) (W) (A) (W)

TBD TBDTBD TBD TBD TBD TBD TBD T BD TBD TBD TBD TBD TBD TBD TBD TBD TBD

Power Rail

+3VS_VGA

+3VS_VGA

+

3VS_VGA

+3VS_VGA

+3VS_VGA

+3VS_VGA

+3VS_VGA

+3VS_VGA

Logical
Strapping Bit3

PCI_DEVID[4]

AM_CFG[3] RAM_C FG[2]

FB[1]

PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0]

SOR3_EXPOSED

RESERVED PCIE_SPEED_

Device ID

N13P-GT
(28nm)

0x0FDB

SMB_ALT_ADDR

(ROM_SO Bit 1)

FBVDD

Logical
Strapping Bit2

SUB_VENDOR

SER[2] USER[1] USER[0]USER[3]

U

3GIO_PAD_CFG_AD R[2] 3GIO_PAD_CFG_AD R[1]3GIO_PAD_CFG_AD R[3]

SOR2_EXPOSED SOR1_EXPOSED

CHANGE_GEN3

setting

0

1

ROM_SO

GPU

N13P-GT1
28nm

FB Memory (GDDR5)

Samsung
2500MHz

Hynix
2500MHz

Samsung
2500MHz

2500MHz

ROM_SCLK

PU 25K

PU 45KPU 10K PD 10K

PD 35K

PU 25K PD 35KPU 45KPU 20K PD 10K PD 5K PD 10K

GPU

N13P-GT

ROM_SI

K4G10325FG-HC04

32Mx32

PD 45K

H5GQ1H24BFR-T2C

32Mx32 PD 35K

K4G20325FD-FC04

64Mx32

PD 30K

H5GQ2H24MFR-T2CHynix

64Mx32

PD 25K

FBVDDQ PCI Express I/O and
(GPU+Mem)
(1.35V)(1.35V)

(A) (W) (W)(mA) (W) (W) (W)(mA) (mA) (mA)

(1.05V)

Logical
Strapping Bit1

SLOT_CLK_CFG

RAM_CFG[1]R

PCIE_MAX_SPEED DP_PLL_VDD33V

PLLVDD

I2C Slave addrees ID

0x9E

0x9C

STRAP2STRAP1STRAP0

STRAP3

STRAP4

PU 5K PD 10K

Master

Slave

I/O and
PLLVDD

Logical
Strapping Bit0

PEX_PLL_EN_TERM

R

AM_CFG[0]

VGA_DEVICESMB_ALT_ADDR

3GIO_PAD_CFG_AD R[0]

SOR0_EXPOSED

Other

(3.3V)(1.05V)(1.8V)

Other Power rail

A A

+3VS_VGA

power-off <10ms

T

1.all GPU power rails should be turned off within 10ms
. Optimus syste m VDD33 avoids drop down ear lier than NVDD and FBVDDQ

2

5

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2011/11/01

2011/11/01

2011/11/01

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2012/12/31

2012/12/31

2012/12/31

Title

VGA NOTES LIST

VGA NOTES LIST

VGA NOTES LIST

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Y400S-NM-A141

Y400S-NM-A141

Y400S-NM-A141

Monday, January 14, 2013

Monday, January 14, 2013

Monday, January 14, 2013

4 65

4 65

1

4 65

1.0

1.0

1.0

5

D D

DMI_CRX_PTX_N0<16 >
DMI_CRX_PTX_N1<16 >
DMI_CRX_PTX_N2<16 >
DMI_CRX_PTX_N3<16 >

DMI_CRX_PTX_P0<16>
DMI_CRX_PTX_P1<16>
DMI_CRX_PTX_P2<16>
DMI_CRX_PTX_P3<16>

DMI_CTX_PRX_N0<16 >
DMI_CTX_PRX_N1<16 >
DMI_CTX_PRX_N2<16 >
DMI_CTX_PRX_N3<16 >

DMI_CTX_PRX_P0<16>
DMI_CTX_PRX_P1<16>
DMI_CTX_PRX_P2<16>

C C

B B

DMI_CTX_PRX_P3<16>

FDI_CTX_PRX_N0<16>
FDI_CTX_PRX_N1<16>
FDI_CTX_PRX_N2<16>
FDI_CTX_PRX_N3<16>
FDI_CTX_PRX_N4<16>
FDI_CTX_PRX_N5<16>
FDI_CTX_PRX_N6<16>
FDI_CTX_PRX_N7<16>

FDI_CTX_PRX_P0<16>
FDI_CTX_PRX_P1<16>
FDI_CTX_PRX_P2<16>
FDI_CTX_PRX_P3<16>
FDI_CTX_PRX_P4<16>
FDI_CTX_PRX_P5<16>
FDI_CTX_PRX_P6<16>
FDI_CTX_PRX_P7<16>

FDI_FSYNC0<16>
FDI_FSYNC1<16>

FDI_INT<16>

FDI_LSYNC0<16>
FDI_LSYNC1<16>

+1.05VS

eDP_COMPIO and ICOMPO signals
should be short ed near balls
and routed with typical
impedance <25 m ohms

R7

1 2

24.9_0402_1%

4

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

FDI_FSYNC0
FDI_FSYNC1

FDI_INT

FDI_LSYNC0
FDI_LSYNC1

EDP_COMP

JCPU1A

ME@

B27

DMI_RX#[0]

B25

DMI_RX#[1]

A25

DMI_RX#[2]

B24

DMI_RX#[3]

B28

DMI_RX[0]

B26

DMI_RX[1]

A24

DMI_RX[2]

B23

DMI_RX[3]

G21

DMI_TX#[0]

E22

DMI_TX#[1]

F21

DMI_TX#[2]

D21

DMI_TX#[3]

G22

DMI_TX[0]

D22

DMI_TX[1]

F20

DMI_TX[2]

C21

DMI_TX[3]

A21

FDI0_TX#[0]

H19

FDI0_TX#[1]

E19

FDI0_TX#[2]

F18

FDI0_TX#[3]

B21

FDI1_TX#[0]

C20

FDI1_TX#[1]

D18

FDI1_TX#[2]

E17

FDI1_TX#[3]

A22

FDI0_TX[0]

G19

FDI0_TX[1]

E20

FDI0_TX[2]

G18

FDI0_TX[3]

B20

FDI1_TX[0]

C19

FDI1_TX[1]

D19

FDI1_TX[2]

F17

FDI1_TX[3]

J18

FDI0_FSYNC

J17

FDI1_FSYNC

H20

FDI_INT

J19

FDI0_LSYNC

H17

FDI1_LSYNC

A18

eDP_COMPIO

A17

eDP_ICOMPO

B16

eDP_HPD#

C15

eDP_AUX

D15

eDP_AUX#

C17

eDP_TX[0]

F16

eDP_TX[1]

C16

eDP_TX[2]

G15

eDP_TX[3]

C18

eDP_TX#[0]

E16

eDP_TX#[1]

D16

eDP_TX#[2]

F15

eDP_TX#[3]

TYCO_2013620-2_IVY BRIDGE

3

J22

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]

DMI

Intel(R) FDI

eDP

PEG_RX#[7]
PEG_RX#[8]

PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]

PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]

PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]

PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]

PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]

PCI EXPRESS* - GRAPHICS

PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]

PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]

PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]

J21
H22

K33

PCIE_CRX_GTX_N0

M35

PCIE_CRX_GTX_N1

L34

PCIE_CRX_GTX_N2

J35

PCIE_CRX_GTX_N3

J32

PCIE_CRX_GTX_N4

H34

PCIE_CRX_GTX_N5

H31

PCIE_CRX_GTX_N6

G33

PCIE_CRX_GTX_N7

G30

PCIE_CRX_GTX_N8

F35

PCIE_CRX_GTX_N9

E34

PCIE_CRX_GTX_N10

E32

PCIE_CRX_GTX_N11

D33

PCIE_CRX_GTX_N12

D31

PCIE_CRX_GTX_N13

B33

PCIE_CRX_GTX_N14

C32

PCIE_CRX_GTX_N15

J33

PCIE_CRX_GTX_P0

L35

PCIE_CRX_GTX_P1

K34

PCIE_CRX_GTX_P2

H35

PCIE_CRX_GTX_P3

H32

PCIE_CRX_GTX_P4

G34

PCIE_CRX_GTX_P5

G31

PCIE_CRX_GTX_P6

F33

PCIE_CRX_GTX_P7

F30

PCIE_CRX_GTX_P8

E35

PCIE_CRX_GTX_P9

E33

PCIE_CRX_GTX_P10

F32

PCIE_CRX_GTX_P11

D34

PCIE_CRX_GTX_P12

E31

PCIE_CRX_GTX_P13

C33

PCIE_CRX_GTX_P14

B32

PCIE_CRX_GTX_P15

M29

PCIE_CTX_GRX_C_N0

M32

PCIE_CTX_GRX_C_N1

M31

PCIE_CTX_GRX_C_N2

L32

PCIE_CTX_GRX_C_N3

L29

PCIE_CTX_GRX_C_N4

K31

PCIE_CTX_GRX_C_N5

K28

PCIE_CTX_GRX_C_N6

J30

PCIE_CTX_GRX_C_N7

J28

PCIE_CTX_GRX_C_N8

H29

PCIE_CTX_GRX_C_N9

G27

PCIE_CTX_GRX_C_N10

E29

PCIE_CTX_GRX_C_N11

F27

PCIE_CTX_GRX_C_N12

D28

PCIE_CTX_GRX_C_N13

F26

PCIE_CTX_GRX_C_N14

E25

PCIE_CTX_GRX_C_N15

M28

PCIE_CTX_GRX_C_P0

M33

PCIE_CTX_GRX_C_P1

M30

PCIE_CTX_GRX_C_P2

L31

PCIE_CTX_GRX_C_P3

L28

PCIE_CTX_GRX_C_P4

K30

PCIE_CTX_GRX_C_P5

K27

PCIE_CTX_GRX_C_P6

J29

PCIE_CTX_GRX_C_P7

J27

PCIE_CTX_GRX_C_P8

H28

PCIE_CTX_GRX_C_P9

G28

PCIE_CTX_GRX_C_P10

E28

PCIE_CTX_GRX_C_P11

F28

PCIE_CTX_GRX_C_P12

D27

PCIE_CTX_GRX_C_P13

E26

PCIE_CTX_GRX_C_P14

D25

PCIE_CTX_GRX_C_P15

PEG_COMP

+1.05VS

R1

12

24.9_0402_1%

PCIE_CRX_GTX_N[0..15] <23,32>

PCIE_CRX_GTX_P[0..15] <23,32>

C1 0.22U_0402_1 0V6K
C2 0.22U_0402_1 0V6K
C3 0.22U_0402_1 0V6K
C4 0.22U_0402_1 0V6K
C5 0.22U_0402_1 0V6K
C6 0.22U_0402_1 0V6K
C7 0.22U_0402_1 0V6K
C8 0.22U_0402_1 0V6K
C9 0.22U_0402_1 0V6KSLI@
C10 0.22U_0402_10V 6KSLI@
C11 0.22U_0402_10V 6KSLI@
C12 0.22U_0402_10V 6KSLI@
C13 0.22U_0402_10V 6KSLI@
C14 0.22U_0402_10V 6KSLI@
C15 0.22U_0402_10V 6KSLI@
C16 0.22U_0402_10V 6KSLI@

C20 0.22U_0402_10V 6K
C23 0.22U_0402_10V 6K
C25 0.22U_0402_10V 6K
C30 0.22U_0402_10V 6K
C18 0.22U_0402_10V 6K
C22 0.22U_0402_10V 6K
C28 0.22U_0402_10V 6K
C32 0.22U_0402_10V 6K
C19 0.22U_0402_10V 6KSLI@
C24 0.22U_0402_10V 6KSLI@
C29 0.22U_0402_10V 6KSLI@
C17 0.22U_0402_10V 6KSLI@
C21 0.22U_0402_10V 6KSLI@
C27 0.22U_0402_10V 6KSLI@
C26 0.22U_0402_10V 6KSLI@
C31 0.22U_0402_10V 6KSLI@

2

1. PEG_ICOMPI and RCOMPO signals should be shorted and routed with
a. max length = 500 mils
b. typical impedance = 43 mohms

2. PEG_ICOMPO signals should be routed with
a. max length = 500 mils
b. typical impedance = 14.5 mohms

PEG Static Lane Reversal - CFG2 is for the 16x

1: Normal Operation; Lane # definition matches
socket pin map definition

0

:Lane Reversed

*

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

CFG2

PCIE_CTX_GRX_N0
PCIE_CTX_GRX_N1
PCIE_CTX_GRX_N2
PCIE_CTX_GRX_N3
PCIE_CTX_GRX_N4
PCIE_CTX_GRX_N5
PCIE_CTX_GRX_N6
PCIE_CTX_GRX_N7
PCIE_CTX_GRX_N8
PCIE_CTX_GRX_N9
PCIE_CTX_GRX_N10
PCIE_CTX_GRX_N11
PCIE_CTX_GRX_N12
PCIE_CTX_GRX_N13
PCIE_CTX_GRX_N14
PCIE_CTX_GRX_N15

PCIE_CTX_GRX_P0
PCIE_CTX_GRX_P1
PCIE_CTX_GRX_P2
PCIE_CTX_GRX_P3
PCIE_CTX_GRX_P4
PCIE_CTX_GRX_P5
PCIE_CTX_GRX_P6
PCIE_CTX_GRX_P7
PCIE_CTX_GRX_P8
PCIE_CTX_GRX_P9
PCIE_CTX_GRX_P10
PCIE_CTX_GRX_P11
PCIE_CTX_GRX_P12
PCIE_CTX_GRX_P13
PCIE_CTX_GRX_P14
PCIE_CTX_GRX_P15

1

PCIE_CTX_GRX_N[0..15] < 23,32>

PCIE_CTX_GRX_P[0..15] <23,32>

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUT URE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUT URE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUT URE CENTER.

3

2011/11/01

2011/11/01

2011/11/01

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2012/12/31

2012/12/31

2012/12/31

Title

PROCESSOR(1/7) DMI,FDI,PEG

PROCESSOR(1/7) DMI,FDI,PEG

PROCESSOR(1/7) DMI,FDI,PEG

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Monday, January 14, 2013

Monday, January 14, 2013

Monday, January 14, 2013

Y400S-NM-A141

Y400S-NM-A141

Y400S-NM-A141

1

of

of

of

5 65

5 65

5 65

1.0

1.0

1.0

5

D D

ROC_SEL

H : Sandy Bridg e

P

L : IVY Bridge

+1.05VS

R9

1 2

62_0402_5%

C C

H_CPUPWRGD<19>

C550

100P_0402_50V8J

9/23 ESD Reques t

1

2

R27
10K_0402_5%

1 2

H_PROCHOT#<45,53>

H_PM_SYNC<16>

4

H_SNB_IVB#<19>

T14 PAD

H_PECI<45>

H_PROCHOT#H_PROCHOT#

H_THRMTRIP#<19>

H_PM_SYNC

H_CPUPWRGD

R15

1 2

56_0402_5%

R22

1 2

R_short 0_0402_5%

R26

1 2

R_short 0_0402_5%

R29

1 2

130_0402_5%

H_SNB_IVB#

H_CATERR#

H_PROCHOT#_R

H_THRMTRIP#

H_PM_SYNC_R

H_CPUPWRGD_R

PM_DRAM_PWR GD_RPM_SYS_PWRGD_BUF

BUF_CPU_RST#

H_PECI

JCPU1B

C26

AN34

AL33

AN33

AL32

AN32

AM34

AP33

V8

AR33

3

ME@

PROC_SELECT#

SKTOCC#

CATERR#

PECI

PROCHOT#

THERMTRIP#

PM_SYNC

UNCOREPWRGOOD

SM_DRAMPWR OK

RESET#

BCLK

BCLK#

MISCTHERMALPWR MANAGEMENT

DPLL_REF_CLK

DPLL_REF_CLK#

CLOCKS

SM_DRAMRST#

SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]

DDR3

MISC

PRDY#
PREQ#

TCK
TMS

TRST#

TDI

TDO

DBR#

BPM#[0]
BPM#[1]

JTAG & BPM

BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]

2

A28

CLK_CPU_DMI

A27

CLK_CPU_DMI#

A16
A15

R8

AK1
A5
A4

H_DRAMRST#

SM_RCOMP0
SM_RCOMP1
SM_RCOMP2

R12 1K_0402_5%
R13 1K_0402_5%

R16 140_0402_1%
R17 25.5_0402_1%
R18 200_0402_1%

DDR3 Compensation Signals

AP29
AP27

AR26
AR27
AP30

AR28
AP26

AL35

AT28
AR29
AR30
AT30
AP32
AR31
AT31
AR32

XDP_TCK
XDP_TMS
XDP_TRST#

XDP_TDI
XDP_TDO

XDP_TMS
XDP_TDI
XDP_TDO

XDP_TCK
XDP_TRST#

PU/PD for JTAG signals

CLK_CPU_DMI <15>
CLK_CPU_DMI# <15>

12
12

H_DRAMRST# <7>

12
12
12

R20 51_0402_5%
R21 51_0402_5%
R23 51_0402_5%

R24 51_0402_5%
R25 51_0402_5%

+1.05VS

12
12
12

@

12
12

1

+1.05VS

TYCO_2013620-2_IVY BRIDGE

B B

Buffered Reset to CPU

+3VS

1

5

P

B

O

A

G

U1
74AHC1G09GW_TSSOP5

3

4

C33

0.1U_0402_16V4Z

2

4

R338

10K_0402_5%

1 2

1 2

SYS_PWROK<16>

PM_DRAM_PWR GD<16>

A A

5

R65 0_0402_5%@

1

2

+1.5V_CPU_VDDQ+3VALW

12

R30
200_0402_5%

PM_SYS_PWRGD_BUF

1.05V

12

R35

@

0_0402_5%

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

3

2011/11/01

2011/11/01

2011/11/01

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

+1.05VS +3VS

12

R32

75_0402_5%

R34

1 2

43_0402_1%

BUFO_CPU_RST#BUF_CPU_RS T#

Deciphered Date

Deciphered Date

Deciphered Date

0.1U_0402_16V4Z

2

C34

4

2012/12/31

2012/12/31

2012/12/31

1

2

5

P

NC

Y

A

G

3

1

is is NC pin

Th

2

PLT_RST#

U2
SN74LVC1G07DCKR_SC70-5

Title

Title

Title

PROCESSOR(2/7) PM,XDP,CLK

PROCESSOR(2/7) PM,XDP,CLK

PROCESSOR(2/7) PM,XDP,CLK

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

3V

PLT_RST# <18,23,32,37,38,44,45>

Y400S-NM-A141

Y400S-NM-A141

Monday, January 14, 2013

Monday, January 14, 2013

Monday, January 14, 2013

Y400S-NM-A141

1

of

of

of

6 65

6 65

6 65

1.0

1.0

1.0

5

JCPU1C

ME@

4

3

JCPU1D

2

ME@

1

DDR_A_D[0..63]<12>

D D

C C

B B

DDR_A_BS0<12>
DDR_A_BS1<12>
DDR_A_BS2<12>

DDR_A_CAS#<12>
DDR_A_RAS#<12>
DDR_A_WE#<12>

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

AP11
AN11

AL12
AM12
AM11

AL11
AP12
AN12

AJ14
AH14

AL15
AK15

AL14
AK14

AJ15
AH15

AE10

AF10

G10

N10

M10

AG6
AG5
AK6
AK5
AH5
AH6

AK8

AK9
AH8
AH9
AL9
AL8

AE8
AD9
AF9

F10

AJ5
AJ6
AJ8

AJ9

C5
D5
D3
D2
D6
C6
C2
C3

F8

G9
F9
F7
G8
G7
K4
K5
K1
J1
J5
J4
J2
K2

M8

N8
N7

M9
N9
M7

V6

SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]

SA_BS[0]
SA_BS[1]
SA_BS[2]

SA_CAS#
SA_RAS#
SA_WE#

DDR SYSTEM MEMORY A

SA_CK[0]

SA_CLK#[0]

SA_CKE[0]

SA_CK[1]

SA_CLK#[1]

SA_CKE[1]

SA_CK[2]

SA_CLK#[2]

SA_CKE[2]

SA_CK[3]

SA_CLK#[3]

SA_CKE[3]

SA_CS#[0]
SA_CS#[1]
SA_CS#[2]
SA_CS#[3]

SA_ODT[0]
SA_ODT[1]
SA_ODT[2]
SA_ODT[3]

SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]

SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]

SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]

SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]

AB6
AA6
V9

AA5
AB5
V10

AB4
AA4
W9

AB3
AA3
W10

AK3
AL3
AG1
AH1

AH3
AG3
AG2
AH2

C4
G6
J3
M6
AL6
AM8
AR12
AM15

D4
F6
K3
N6
AL5
AM9
AR11
AM14

AD10
W1
W2
W7
V3
V2
W3
W6
V1
W5
AD8
V4
W4
AF8
V5
V7

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

M_CLK_DDR0 <12>
M_CLK_DDR#0 <12>
DDR_CKE0_DIMMA <12>

M_CLK_DDR1 <12>
M_CLK_DDR#1 <12>
DDR_CKE1_DIMMA <12>

DDR_CS0_DIMMA# <12>
DDR_CS1_DIMMA# <12>

M_ODT0 <12>
M_ODT1 <12>

DDR_A_DQS#[0..7] <12>

DDR_A_DQS[0..7] <12>

DDR_A_MA[0..15] <12> DDR_B_MA[0..15] <13>

DDR_B_D[0..63]<13>

DDR_B_BS0<13>
DDR_B_BS1<13>
DDR_B_BS2<13>

DDR_B_CAS#<13>
DDR_B_RAS#<13>
DDR_B_WE#<13>

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

D10

K10

AM5
AM6
AR3

AP3
AN3
AN2
AN1

AP2

AP5
AN9

AT5

AT6

AP6
AN8
AR6
AR5
AR9

AJ11

AT8

AT9

AH11

AR8

AJ12
AH12
AT11
AN14
AR14
AT14
AT12
AN15
AR15
AT15

AA9
AA7

AA10

AB8
AB9

J10

C9
A7

C8
A9
A8
D9
D8
G4
F4
F1
G1
G5
F5
F2
G2

J7
J8

K9

J9

K8
K7
M5
N4
N2
N1
M4
N5
M2
M1

R6

SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]

SB_BS[0]
SB_BS[1]
SB_BS[2]

SB_CAS#
SB_RAS#
SB_WE#

DDR SYSTEM MEMORY B

SB_CK[0]

SB_CLK#[0]

SB_CKE[0]

SB_CK[1]

SB_CLK#[1]

SB_CKE[1]

SB_CK[2]

SB_CLK#[2]

SB_CKE[2]

SB_CK[3]

SB_CLK#[3]

SB_CKE[3]

SB_CS#[0]
SB_CS#[1]
SB_CS#[2]
SB_CS#[3]

SB_ODT[0]
SB_ODT[1]
SB_ODT[2]
SB_ODT[3]

SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]

SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]

SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]

SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]

AE2
AD2
R9

AE1
AD1
R10

AB2
AA2
T9

AA1
AB1
T10

AD3
AE3
AD6
AE6

AE4
AD4
AD5
AE5

D7
F3
K6
N3
AN5
AP9
AK12
AP15

C7
G3
J6
M3
AN6
AP8
AK11
AP14

AA8
T7
R7
T6
T2
T4
T3
R2
T5
R3
AB7
R1
T1
AB10
R5
R4

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15

M_CLK_DDR2 <13>
M_CLK_DDR#2 <13>
DDR_CKE2_DIMMB <13>

M_CLK_DDR3 <13>
M_CLK_DDR#3 <13>
DDR_CKE3_DIMMB <13>

DDR_CS2_DIMMB# <13>
DDR_CS3_DIMMB# <13>

M_ODT2 <13>
M_ODT3 <13>

DDR_B_DQS#[0..7] <13>

DDR_B_DQS[0..7] <13>

TYCO_2013620-2_IVY BRIDGE

+1.5V

12

R37

1K_0402_5%

D

S

13

H_DRAMRST#<6>

R39

A A

DRAMRST_CNTRL_PC H<15>

DRAMRST_CNTRL<1 0>

DRAMRST_CNTRL_EC<45>

Reserve for Dee p S3

5

4.99K_0402_1%

1 2

@

R40 0_0402_5%

1 2

DS3@

R64 0_0402_5%

1 2

DRAMRST_CNTRL

DDR3_DRAMRST#_RH_DRAMRST#

Q2

G

BSS138_NL_SOT23-3

2

1

C35

0.047U_0402_16V4Z

2

Module design u sed 0.047u

4

R38

1 2

1K_0402_5%

DDR3_DRAMRST# <12,13>

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

3

2011/11/01

2011/11/01

2011/11/01

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

TYCO_2013620-2_IVY BRIDGE

2012/12/31

2012/12/31

2012/12/31

2

Title

Title

Title

PROCESSOR(3/7) DDRIII

PROCESSOR(3/7) DDRIII

PROCESSOR(3/7) DDRIII

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Monday, January 14, 2013

Monday, January 14, 2013

Monday, January 14, 2013

Y400S-NM-A141

Y400S-NM-A141

Y400S-NM-A141

1

of

of

of

7 65

7 65

7 65

1.0

1.0

1.0

5

D D

JCPU1E

ME@

AK28

CFG[0]

AK29

CFG[1]

CFG2

CFG5
CFG6
CFG7

C C

11/24 --> Intel recommend
t

o reserve test point

B B

T56 PAD
T57 PAD
T58 PAD
T59 PAD

AL26

CFG[2]

AL27

CFG[3]

AK26

CFG[4]

AL29

CFG[5]

AL30

CFG[6]

AM31

CFG[7]

AM32

CFG[8]

AM30

CFG[9]

AM28

CFG[10]

AM26

CFG[11]

AN28

CFG[12]

AN31

CFG[13]

AN26

CFG[14]

AM27

CFG[15]

AK31

CFG[16]

AN29

CFG[17]

AJ31

VAXG_VAL_SENSE

AH31

VSSAXG_VAL_SENSE

AJ33

VCC_VAL_SENSE

AH33

VSS_VAL_SENSE

AJ26

RSVD5

F25

RSVD8

F24

RSVD9

F23

RSVD10

D24

RSVD11

G25

RSVD12

G24

RSVD13

E23

RSVD14

D23

RSVD15

C30

RSVD16

A31

RSVD17

B30

RSVD18

B29

RSVD19

D30

RSVD20

B31

RSVD21

A30

RSVD22

C29

RSVD23

J20

RSVD24

B18

RSVD25

J15

RSVD27

CFG

4

VCC_DIE_SENSE

VSS

RSVD28
RSVD29
RSVD30
RSVD31

RSVD32

RSVD33
RSVD34
RSVD35

RSVD37
RSVD38
RSVD39
RSVD40

RSVD_NCTF1
RSVD_NCTF2
RSVD_NCTF3
RSVD_NCTF4
RSVD_NCTF5

RSVD_NCTF6
RSVD_NCTF7

RESERVED

RSVD_NCTF8
RSVD_NCTF9

RSVD_NCTF10

RSVD51
RSVD52

BCLK_ITP

BCLK_ITP#

RSVD_NCTF11
RSVD_NCTF12
RSVD_NCTF13

KEY

AH27
AH26

L7
AG7
AE7
AK2

W8

AT26
AM33
AJ27

T8
J16
H16
G16

AR35
AT34
AT33
AP35
AR34

B34
A33
A34
B35
C35

AJ32
AK32

AN35
AM35

AT2
AT1
AR1

B1

3

CFG Straps for Processor

CFG2

CFG6

CFG5

1K_0402_1%

CFG7

12

R41

@

1K_0402_1%

12

12

R44

R43

@

1K_0402_1%

12

R45

@

1K_0402_1%

PEG Static Lane Reversal - CFG2 is for the 16x

CFG2

Display Port Presence Strap

CFG4

PCIE Port Bifurcation Straps

CFG[6:5]

PEG DEFER TRAINING

CFG7

2

1: Normal Operation; Lane # definition matches

*

socket pin map definition

0:Lane Reversed

1 : Disabled; No Physical Display Port
attached to Embedded Display Port

*

0 : Enabled; An external Display Port device is
c

onnected to the Embedded Display Port

11: (Default) x16 - Device 1 functions 1 and 2 disabled

10: x8, x8 - Device 1 function 1 enabled ; function 2

*

disabled

01: Reserved - (Device 1 function 1 disabled ; function

2 enabled)

00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

: (Default) PEG Train immediately following xxRESETB

1
de assertion

0: PEG Wait for BIOS for training

1

TYCO_2013620-2_IVY BRIDGE

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

3

2011/11/01

2011/11/01

2011/11/01

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2012/12/31

2012/12/31

2012/12/31

Title

PROCESSOR(4/7) RSVD,CFG

PROCESSOR(4/7) RSVD,CFG

PROCESSOR(4/7) RSVD,CFG

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Monday, January 14, 2013

Monday, January 14, 2013

Monday, January 14, 2013

Y400S-NM-A141

Y400S-NM-A141

Y400S-NM-A141

1

of

of

of

8 65

8 65

8 65

1.0

1.0

1.0

5

4

3

2

1

JCPU1F

+VCC_CORE

D D

C C

B B

A A

5

C=94A

Q
DC=53A

AG35

VCC1

AG34

VCC2

AG33

VCC3

AG32

VCC4

AG31

VCC5

AG30

VCC6

AG29

VCC7

AG28

VCC8

AG27

VCC9

AG26

VCC10

AF35

VCC11

AF34

VCC12

AF33

VCC13

AF32

VCC14

AF31

VCC15

AF30

VCC16

AF29

VCC17

AF28

VCC18

AF27

VCC19

AF26

VCC20

AD35

VCC21

AD34

VCC22

AD33

VCC23

AD32

VCC24

AD31

VCC25

AD30

VCC26

AD29

VCC27

AD28

VCC28

AD27

VCC29

AD26

VCC30

AC35

VCC31

AC34

VCC32

AC33

VCC33

AC32

VCC34

AC31

VCC35

AC30

VCC36

AC29

VCC37

AC28

VCC38

AC27

VCC39

AC26

VCC40

AA35

VCC41

AA34

VCC42

AA33

VCC43

AA32

VCC44

AA31

VCC45

AA30

VCC46

AA29

VCC47

AA28

VCC48

AA27

VCC49

AA26

VCC50

Y35

VCC51

Y34

VCC52

Y33

VCC53

Y32

VCC54

Y31

VCC55

Y30

VCC56

Y29

VCC57

Y28

VCC58

Y27

VCC59

Y26

VCC60

V35

VCC61

V34

VCC62

V33

VCC63

V32

VCC64

V31

VCC65

V30

VCC66

V29

VCC67

V28

VCC68

V27

VCC69

V26

VCC70

U35

VCC71

U34

VCC72

U33

VCC73

U32

VCC74

U31

VCC75

U30

VCC76

U29

VCC77

U28

VCC78

U27

VCC79

U26

VCC80

R35

VCC81

R34

VCC82

R33

VCC83

R32

VCC84

R31

VCC85

R30

VCC86

R29

VCC87

R28

VCC88

R27

VCC89

R26

VCC90

P35

VCC91

P34

VCC92

P33

VCC93

P32

VCC94

P31

VCC95

P30

VCC96

P29

VCC97

P28

VCC98

P27

VCC99

P26

VCC100

TYCO_2013620-2_IVY BRIDGE

POWER

ME@

CORE SUPPLY

VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8

VCCIO9
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCCIO21
VCCIO22
VCCIO23
VCCIO24

VCCIO25
VCCIO26
VCCIO27
VCCIO28
VCCIO29
VCCIO30
VCCIO31

PEG AND DDR

VCCIO32
VCCIO33
VCCIO34
VCCIO35
VCCIO36
VCCIO37
VCCIO38
VCCIO39

VCCIO40

VIDALERT#

VIDSCLK
VIDSOUT

VCC_SENSE
VSS_SENSE

VCCIO_SENSE

VSS_SENSE_VCCIO

SENSE LINES SVID

4

+1.05VS

8.5A

AH13
AH10
AG10
AC10
Y10
U10
P10
L10
J14
J13
J12
J11
H14
H12
H11
G14
G13
G12
F14
F13
F12
F11
E14
E12

E11
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11

J23

Reserve 0.1u to avoid noise

AJ29
AJ30
AJ28

H_CPU_SVIDALRT#
H_CPU_SVIDCLK
H_CPU_SVIDDAT

1 2

R47 43_0402_5%

1 2

R48 R_short 0_0402_5%

1 2

R49 R_short 0_0402_5%

R50 130_0402_5%

12

Place the PU re sistor close t o CPU

AJ35

VCCSENSE_R VCCSENSE

AJ34

VSSSENSE_R

B10

VCCIO_SENSE

A10

VSSIO_SENSE

1 2

R52 R_short 0_0402_5%

1 2

R53 R_short 0_0402_5%

R1294 10_0402_1%

R1297 10_0402_1%

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

3

+1.05VS

12

12

0.1U_0402_10V7K

+1.05VS

2011/11/01

2011/11/01

2011/11/01

+1.05VS

1

C36

@

2

+VCC_CORE

VSSSENSE

VCCIO_SENSE <57>

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

12

R46
75_0402_5%

Place the PU re sistor close t o CPU

VR_SVID_ALRT# <59>
VR_SVID_CLK <59>
VR_SVID_DAT <59>

12

R51
100_0402_1%

V

CC_SENCE 100ohm +-1% pull-up to VCC near pr ocessor

VCCSENSE <59>

12

R54

100_0402_1%

VSSSENSE <59>

VSS_SENCE 100oh m +-1% pull-do wn to GND near processor

2012/12/31

2012/12/31

2012/12/31

2

Title

Title

Title

PROCESSOR(5/7) PWR,BYPASS

PROCESSOR(5/7) PWR,BYPASS

PROCESSOR(5/7) PWR,BYPASS

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Monday, January 14, 2013

Monday, January 14, 2013

Monday, January 14, 2013

Y400S-NM-A141

Y400S-NM-A141

Y400S-NM-A141

1

of

of

of

9 65

9 65

9 65

1.0

1.0

1.0

5

4

3

2

1

+1.5V_CPU_VDDQ

For Deep S3

D D

R1538

SUSP<37,51,55,57>

CPU1.5V_S3_GATE<45>

C C

B B

1 2

R_short 0_0402_5%

0_0402_5%

+3VALW

12

R1537

100K_0402_5%

+VCC_GFXCORE_AXG

@

13

D

2

G

S

4

RV174

SLI@

1 2

@

Q156
2N7002_SOT23

6A

+VSB

12

R56 need to che ck on SDV

R56
100K_0402_5%

61

D

2

G

S

Q4A
2N7002KDWH_SOT363-6

JCPU1G

AT24

VAXG1

AT23

VAXG2

AT21

VAXG3

AT20

VAXG4

AT18

VAXG5

AT17

VAXG6

AR24

VAXG7

AR23

VAXG8

AR21

VAXG9

AR20

VAXG10

AR18

VAXG11

AR17

VAXG12

AP24

VAXG13

AP23

VAXG14

AP21

VAXG15

AP20

VAXG16

AP18

VAXG17

AP17

VAXG18

AN24

VAXG19

AN23

VAXG20

AN21

VAXG21

AN20

VAXG22

AN18

VAXG23

AN17

VAXG24

AM24

VAXG25

AM23

VAXG26

AM21

VAXG27

AM20

VAXG28

AM18

VAXG29

AM17

VAXG30

AL24

VAXG31

AL23

VAXG32

AL21

VAXG33

AL20

VAXG34

AL18

VAXG35

AL17

VAXG36

AK24

VAXG37

AK23

VAXG38

AK21

VAXG39

AK20

VAXG40

AK18

VAXG41

AK17

VAXG42

AJ24

VAXG43

AJ23

VAXG44

AJ21

VAXG45

AJ20

VAXG46

AJ18

VAXG47

AJ17

VAXG48

AH24

VAXG49

AH23

VAXG50

AH21

VAXG51

AH20

VAXG52

AH18

VAXG53

AH17

VAXG54

RUN_ON_CPU1.5VS3

POWER

GRAPHICS

+1.5V

1 2

470K_0402_5%

12

R57
470K_0402_5%

VAXG_SENSE

VSSAXG_SENSE

SENSE

LINES

SM_VREF

SA_DIMM_VREFDQ
SB_DIMM_VREFDQ

VREFMISC

DDR3 -1.5V RAILS

1 2

C287 0.1U_0402_10V 6K

1 2

C286 0.1U_0402_10V 6K

1 2

C96 0.1U_0402_10V 6K

1 2

C95 0.1U_0402_10V 6K

U3

8
7
6
5

AO4304L_SO8

R1349

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8

VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15

VCCSA1
VCCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6
VCCSA7
VCCSA8

4

A
Vgs=10V,Id=18A,
Rds<6.7m ohm
P/N: SB00000RV0 0

1

C97

0.01U 50V K X7R 0603

2

AK35

VCC_AXG_SENSE_R

AK34

VSS_AXG_SENSE_R

AL1

+V_SM_VREF_CNT

B4

+V_DDR_REFA_R

D1

+V_DDR_REFB_R

5A

AF7
AF4
AF1
AC7
AC4
AC1
Y7
Y4
Y1
U7
U4
U1
P7
P4
P1

6A

M27
M26
L26
J26
J25
J24
H26
H25

O4304L

1
2
3

+1.5V_CPU_VDDQ

12

R1487

@

470_0603_5%

34

D

S

Q4B
2N7002KDWH_SOT363-6

1 2

R1488 0_0402_5%OPT@

1 2

R1489 0_0402_5%

10U_0603_6.3V6M

10U_0603_6.3V6M

C118

C117

1

1

2

+VCCSA

10U_0805_6.3V6M

1

2

1

2

2

10U_0805_6.3V6M

C124

C125

1

1

2

2

5

G

OPT@

1

C114

0.1U_0402_16V4Z

2

10U_0603_6.3V6M

10U_0603_6.3V6M

C119

1

2

10U_0805_6.3V6M

C126

1

@

2

SUSP

C120

10U_0805_6.3V6M

DRAMRST_CNTRL<7>

+VREF_DQ_DIMMA
+VREF_DQ_DIMMB

6/8: Add M3 Circuit (Processor Generated SO-DIMM VREF

VCC_AXG_SENSE

VSS_AXG_SENSE

VCC_AXG_SENSE <59>
VSS_AXG_SENSE <59>

+1.5V_CPU_VDDQ

10U_0603_6.3V6M

10U_0603_6.3V6M

C122

C121

1

1

2

2

C127

+VCCSA

@

1

+

@

2

330U_D2_2.5VY_R9M

C128

1

+

2

R66 100_0402_1%

R90 100_0402_1%

330U_D2_2.5VY_R9M

C123

DRAMRST_CNTRL

DRAMRST_CNTRL

OPT@

12

OPT@

12

+1.5V_CPU_VDDQ

12

R77
1K_0402_1%

12

R88
1K_0402_1%

2

G

Q8 BSS138_SOT23

1 3

D

S

1 2

R74 0_0402_5%@

1 2

R75 0_0402_5%@

1 3

D

Q7 BSS138_SOT23

2

S

G

R139

1K_0402_1%

@

12

+V_DDR_REFA_R
+V_DDR_REFB_R

12

R132

@

1K_0402_1%

_DQ)

+VCC_GFXCORE_AXG

Place the PU/PD resi stor clos e to CPU w ithin 2 i nch
(R

eserve pow er side)

SA RAIL

VCCIO_SEL

H23

C22
C24

A19

+1.8VS

R67

1 2

A A

R_short 0_0805_5%

10U_0805_6.3V6M

1

+

C130

C279

@

2

330U_B2_2.5VM_R15M

1

1

C131

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

C132

+1.8VS_VCCPLL

1

2

11/24 change 22 U X2 to 330U B 2 size

5

B6

VCCPLL1

A6

VCCPLL2

A2

VCCPLL3

TYCO_2013620-2_IVY BRIDGE

ME@

4

1.8V RAIL

VCCSA_SENSE

VCCSA_VID[0]
VCCSA_VID[1]

+VCCSA_SENSE <56>

H_VCCSA_VID0 <56>
H_VCCSA_VID1 <56>

6/3 modify for VCCSA 4-Level voltage

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

3

+VCCSA_SENSE

2011/11/01

2011/11/01

2011/11/01

1 2

R68 0_0402_5%@

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2012/12/31

2012/12/31

2012/12/31

Title

Title

Title

PROCESSOR(6/7) PWR

PROCESSOR(6/7) PWR

PROCESSOR(6/7) PWR

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Monday, January 14, 2013

Monday, January 14, 2013

Monday, January 14, 2013

Y400S-NM-A141

Y400S-NM-A141

Y400S-NM-A141

1

of

of

of

10 65

10 65

10 65

1.0

1.0

1.0

5

4

3

2

1

D D

C C

B B

AT35
AT32
AT29
AT27
AT25
AT22
AT19
AT16
AT13
AT10

AR25
AR22
AR19
AR16
AR13
AR10

AR7
AR4

AR2
AP34
AP31
AP28
AP25
AP22
AP19
AP16
AP13
AP10

AP7

AP4

AP1

AN30
AN27
AN25
AN22
AN19
AN16
AN13
AN10

AN7

AN4

AM29
AM25
AM22
AM19
AM16
AM13
AM10

AM7

AM4

AM3

AM2

AM1
AL34
AL31
AL28
AL25
AL22
AL19
AL16
AL13
AL10

AK33
AK30
AK27
AK25
AK22
AK19
AK16
AK13
AK10

AK7

AK4
AJ25

JCPU1H

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10

AT7

VSS11

AT4

VSS12

AT3

VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65

AL7

VSS66

AL4

VSS67

AL2

VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80

VSS

VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS98

VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160

AJ22
AJ19
AJ16
AJ13
AJ10
AJ7
AJ4
AJ3
AJ2
AJ1
AH35
AH34
AH32
AH30
AH29
AH28
AH25
AH22
AH19
AH16
AH7
AH4
AG9
AG8
AG4
AF6
AF5
AF3
AF2
AE35
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2

M34

H33
H30
H27
H24
H21
H18
H15
H13
H10

G35
G32
G29
G26
G23
G20
G17
G11

JCPU1I

T35

VSS161

T34

VSS162

T33

VSS163

T32

VSS164

T31

VSS165

T30

VSS166

T29

VSS167

T28

VSS168

T27

VSS169

T26

VSS170

P9

VSS171

P8

VSS172

P6

VSS173

P5

VSS174

P3

VSS175

P2

VSS176

N35

VSS177

N34

VSS178

N33

VSS179

N32

VSS180

N31

VSS181

N30

VSS182

N29

VSS183

N28

VSS184

N27

VSS185

N26

VSS186
VSS187

L33

VSS188

L30

VSS189

L27

VSS190

L9

VSS191

L8

VSS192

L6

VSS193

L5

VSS194

L4

VSS195

L3

VSS196

L2

VSS197

L1

VSS198

K35

VSS199

K32

VSS200

K29

VSS201

K26

VSS202

J34

VSS203

J31

VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213

H9

VSS214

H8

VSS215

H7

VSS216

H6

VSS217

H5

VSS218

H4

VSS219

H3

VSS220

H2

VSS221

H1

VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230

F34

VSS231

F31

VSS232

F29

VSS233

VSS

VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285

F22
F19
E30
E27
E24
E21
E18
E15
E13
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
D35
D32
D29
D26
D20
D17
C34
C31
C28
C27
C25
C23
C10
C1
B22
B19
B17
B15
B13
B11
B9
B8
B7
B5
B3
B2
A35
A32
A29
A26
A23
A20
A3

TYCO_2013620-2_IVY BRIDGE

ME@

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

3

2011/11/01

2011/11/01

2011/11/01

TYCO_2013620-2_IVY BRIDGE

ME@

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2012/12/31

2012/12/31

2012/12/31

Title

Title

Title

PROCESSOR(7/7) VSS

PROCESSOR(7/7) VSS

PROCESSOR(7/7) VSS

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Monday, January 14, 2013

Monday, January 14, 2013

Monday, January 14, 2013

Y400S-NM-A141

Y400S-NM-A141

Y400S-NM-A141

1

of

of

of

11 65

11 65

11 65

1.0

1.0

1.0

5

4

3

2

1

DDR3 SO-DIMM A

VSS3

DQS0
VSS6

VSS8
DQ12
DQ13

DQ14
DQ15

DQ20
DQ21

DQ22
DQ23

DQ28
DQ29

DQS3

DQ30
DQ31

CKE1
VDD2

VDD4

VDD6

VDD8

CK1#

RAS#

ODT0

ODT1

DQ36
DQ37

DQ38
DQ39

DQ44
DQ45

DQS5

DQ46
DQ47

DQ52
DQ53

DQ54
DQ55

DQ60
DQ61

DQS7

DQ62
DQ63

VTT2

+1.5V+1.5V

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

206

DDR_A_D4
DDR_A_D5

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D6
DDR_A_D7

DDR_A_D12
DDR_A_D13

DDR3_DRAMRST#

DDR_A_D14
DDR_A_D15

DDR_A_D20
DDR_A_D21

DDR_A_D22
DDR_A_D23

DDR_A_D28
DDR_A_D29

DDR_A_DQS#3
DDR_A_DQS3

DDR_A_D30
DDR_A_D31

DDR_CKE1_DIMMA

DDR_A_MA15
DDR_A_MA14

DDR_A_MA11
DDR_A_MA7

DDR_A_MA6
DDR_A_MA4

DDR_A_MA2
DDR_A_MA0

M_CLK_DDR1
M_CLK_DDR#1

DDR_A_BS1
DDR_A_RAS#

DDR_CS0_DIMMA#

M_ODT1

DDR_A_D36
DDR_A_D37

DDR_A_D38
DDR_A_D39

DDR_A_D44
DDR_A_D45

DDR_A_DQS#5
DDR_A_DQS5

DDR_A_D46
DDR_A_D47

DDR_A_D52
DDR_A_D53

DDR_A_D54
DDR_A_D55

DDR_A_D60
DDR_A_D61

DDR_A_DQS#7
DDR_A_DQS7

DDR_A_D62
DDR_A_D63

SMB_DATA_S3
SMB_CLK_S3

0.65A@0.75V

0.65A@0.75V

0.65A@0.75V0.65A@0.75V

DQ4
DQ5

DQ6
DQ7

DM1

DM2

A15
A14

A11

A7

A6
A4

A2
A0

CK1

BA1

S0#

NC2

DM4

DM6

SDA
SCL

G2

4

For RF request

0.047U_0402_16V4Z

1

C51

@

2

DDR3_DRAMRST# <13,7>

DDR_CKE1_DIMMA <7>

M_CLK_DDR1 <7>
M_CLK_DDR#1 <7>

DDR_A_BS1 <7>
DDR_A_RAS# <7>

DDR_CS0_DIMMA# <7>
M_ODT0 <7>

M_ODT1 <7>

0.1U_0402_10V6K

1

C149

C150

2

SMB_DATA_S3 <13,15,37,46>
SMB_CLK_S3 <13,15,37,46>

+0.75VS

0.047U_0402_16V4Z

1

C52

@

2

0.047U_0402_16V4Z

1

C53

@

2

Layout Note:
Place near DIMM

DDR_A_D[0..63] <7>

DDR_A_DQS[0..7] <7>

DDR_A_DQS#[0..7] <7>

DDR_A_MA[0..15] <7>

OSCON (220uF_6.3V_4.2L_ESR17m)*1=(SF000002Y00)
(10uF_0603_6.3V)*8
(0.1uF_402_10V)*4

+1.5V +1.5V

12

R80
1K_0402_1%

+VREF_CA

2.2U_0603_6.3V6K

1

2

12

R81
1K_0402_1%

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

10U_0603_6.3V6M

1

C151

C142

@

@

2

Layout Note:
Place near DIMM

+0.75VS

1U_0402_6.3V6K

1

C288

1

C158

2

2

10U_0603_6.3V6M

1

2

1U_0402_6.3V6K

C143

1

C159

2

2011/11/01

2011/11/01

2011/11/01

10U_0603_6.3V6M

1

2

1U_0402_6.3V6K

10U_0603_6.3V6M

1

C144

C152

2

1U_0402_6.3V6K

1

C160

2

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

10U_0603_6.3V6M

10U_0603_6.3V6M

1

1

C145

2

1

C153

2

2

Layout Note:
Place near DIMM

DDR_A_DM[0:7] connect to GND

2012/12/31

2012/12/31

2012/12/31

2

10U_0603_6.3V6M

10U_0603_6.3V6M

1

C146

2

0.1U_0402_10V6K

0.1U_0402_10V6K

1

1

C154

C155

2

Title

Title

Title

DDRIII-SODIMM SLOT1

DDRIII-SODIMM SLOT1

DDRIII-SODIMM SLOT1

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

C147

2

2

Monday, January 14, 2013

Monday, January 14, 2013

Monday, January 14, 2013

0.1U_0402_10V6K

0.1U_0402_10V6K

1

C156

2

Y400S-NM-A141

Y400S-NM-A141

Y400S-NM-A141

1

1

+

C148
220U_6.3V_M

2

12 65

12 65

12 65

1.0

1.0

1.0

+1.5V

12

R78

1K_0402_1%

+VREF_DQ_DIMMA

D D

C C

B B

A A

1K_0402_1%

12

R79

+3VS

2.2U_0603_6.3V6K

C141

DDR_CKE0_DIMMA<7>

DDR_A_BS2<7>

M_CLK_DDR0<7>
M_CLK_DDR#0<7>

DDR_A_BS0<7>

DDR_A_WE#<7>
DDR_A_CAS#<7>

DDR_CS1_DIMMA#<7>

5

C290

1

2

C140

2.2U_0603_6.3V6K

1

2

+VREF_DQ_DIMMA

1

2

0.1U_0402_10V6K

1

C162

0.1U_0402_10V6K

2

3A@1.5V

DDR_A_D0
DDR_A_D1

DDR_A_D2
DDR_A_D3

DDR_A_D8
DDR_A_D9

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D10
DDR_A_D11

DDR_A_D16
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18
DDR_A_D19

DDR_A_D24
DDR_A_D25

DDR_A_D26
DDR_A_D27

DDR_CKE0_DIMMA

DDR_A_BS2

DDR_A_MA12
DDR_A_MA9

DDR_A_MA8
DDR_A_MA5

DDR_A_MA3
DDR_A_MA1

M_CLK_DDR0
M_CLK_DDR#0

DDR_A_MA10
DDR_A_BS0

DDR_A_WE#
DDR_A_CAS# M_ODT0

DDR_A_MA13
DDR_CS1_DIMMA#

DDR_A_D32
DDR_A_D33

DDR_A_DQS#4
DDR_A_DQS4

DDR_A_D34
DDR_A_D35

DDR_A_D40
DDR_A_D41

DDR_A_D42
DDR_A_D43

DDR_A_D48
DDR_A_D49

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D50
DDR_A_D51

DDR_A_D56
DDR_A_D57

DDR_A_D58
DDR_A_D59

R82

1 2

10K_0402_5%

12

R83
10K_0402_5%

JDIMM1

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1
DQS129RESET#
VSS1131VSS12

33

DQ10

35

DQ11
VSS1337VSS14

39

DQ16

41

DQ17
VSS1543VSS16

45

DQS#2
DQS247VSS17

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25
VSS2261DQS#3

63

DM3
VSS2365VSS24

67

DQ26

69

DQ27
VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1
VDD999VDD10

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

LCN_DAN06-K4806-0103

E

@

M

DQS#0

VSS10

VSS19

VSS21

VDD12

VDD14

VDD16

VDD18

VREF_CA

VSS28

VSS30

VSS31

VSS33

VSS35
DQS#5

VSS38

VSS40

VSS42

VSS43

VSS45

VSS47
DQS#7

VSS50

VSS52

EVENT#

5

+1.5V

12

R84

1K_0402_1%

+VREF_DQ_DIMMB

12

C289

D D

C C

B B

A A

1K_0402_1%

R85

2.2U_0603_6.3V6K

+3VS

DDR_CKE2_DIMMB<7>

DDR_B_BS2<7>

M_CLK_DDR2<7>
M_CLK_DDR#2<7>

DDR_B_BS0<7>

DDR_B_WE#<7>
DDR_B_CAS#<7>

DDR_CS3_DIMMB#<7>

5

1

2

C177

C157

2.2U_0603_6.3V6K

+VREF_DQ_DIMMB

1

2

0.1U_0402_10V6K

1

1

2

2

R97 10K_0402_5%

C178

0.1U_0402_10V6K

DDR_B_D0
DDR_B_D1

DDR_B_D2
DDR_B_D3

DDR_B_D8
DDR_B_D9

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D11

DDR_B_D16
DDR_B_D17

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D18
DDR_B_D19

DDR_B_D24
DDR_B_D25

DDR_B_D26
DDR_B_D27

DDR_CKE2_DIMMB

DDR_B_BS2

DDR_B_MA12
DDR_B_MA9

DDR_B_MA8
DDR_B_MA5

DDR_B_MA3
DDR_B_MA1

M_CLK_DDR2
M_CLK_DDR#2

DDR_B_MA10
DDR_B_BS0

DDR_B_WE#
DDR_B_CAS#

DDR_B_MA13
DDR_CS3_DIMMB#

DDR_B_D32
DDR_B_D33

DDR_B_DQS#4
DDR_B_DQS4

DDR_B_D34
DDR_B_D35

DDR_B_D40
DDR_B_D41

DDR_B_D42
DDR_B_D43

DDR_B_D48
DDR_B_D49

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D50
DDR_B_D51

DDR_B_D56
DDR_B_D57

DDR_B_D58
DDR_B_D59

R95

1 2

10K_0402_5%

1 2

DDR3 SO-DIMM B

3A@1.5V

JDIMM2

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1
VSS49DQS#0

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9
VSS925VSS10

27

DQS#1
DQS129RESET#
VSS1131VSS12

33

DQ10

35

DQ11
VSS1337VSS14

39

DQ16

41

DQ17
VSS1543VSS16

45

DQS#2
DQS247VSS17

49

VSS18

51

DQ18
DQ1953VSS19

55

VSS20

57

DQ24
DQ2559VSS21
VSS2261DQS#3

63

DM3
VSS2365VSS24

67

DQ26

69

DQ27
VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1
VDD999VDD10

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

TYCO_2-2013287-1

ME@

DQ4
DQ5

VSS3

DQS0
VSS6

DQ6

DQ7
VSS8
DQ12
DQ13

DM1

DQ14
DQ15

DQ20
DQ21

DM2

DQ22
DQ23

DQ28
DQ29

DQS3

DQ30
DQ31

CKE1
VDD2

VDD4

VDD6

VDD8

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

NC2

VDD18

VREF_CA

VSS28

DQ36
DQ37

VSS30

DM4

VSS31

DQ38
DQ39

VSS33

DQ44
DQ45

VSS35
DQS#5

DQS5

VSS38

DQ46
DQ47

VSS40

DQ52
DQ53

VSS42

DM6

VSS43

DQ54
DQ55

VSS45

DQ60
DQ61

VSS47
DQS#7

DQS7

VSS50

DQ62
DQ63

VSS52

EVENT#

SDA

VTT2

4

+1.5V+1.5V

2
4

DDR_B_D4

6

DDR_B_D5

8
10

DDR_B_DQS#0

12

DDR_B_DQS0

14
16

DDR_B_D6

18

DDR_B_D7

20
22

DDR_B_D12

24

DDR_B_D13

26
28
30

DDR3_DRAMRST#

32
34

DDR_B_D14

36

DDR_B_D15

38
40

DDR_B_D20

42

DDR_B_D21

44
46
48
50

DDR_B_D22

52

DDR_B_D23

54
56

DDR_B_D28

58

DDR_B_D29

60
62

DDR_B_DQS#3

64

DDR_B_DQS3

66
68

DDR_B_D30

70

DDR_B_D31

72

74

DDR_CKE3_DIMMB

76
78

A15
A14

A11

A7

A6
A4

A2
A0

CK1

BA1

S0#

SCL

G2

DDR_B_MA15

80

DDR_B_MA14

82
84

DDR_B_MA11

86

DDR_B_MA7

88
90

DDR_B_MA6

92

DDR_B_MA4

94
96

DDR_B_MA2

98

DDR_B_MA0

100
102

M_CLK_DDR3

104

M_CLK_DDR#3

106
108

DDR_B_BS1

110

DDR_B_RAS#

112
114

DDR_CS2_DIMMB#

116

M_ODT2

118
120

M_ODT3

122
124
126
128
130

DDR_B_D36

132

DDR_B_D37

134
136
138
140

DDR_B_D38

142

DDR_B_D39

144
146

DDR_B_D44

148

DDR_B_D45

150
152

DDR_B_DQS#5

154

DDR_B_DQS5

156
158

DDR_B_D46

160

DDR_B_D47

162
164

DDR_B_D52

166

DDR_B_D53

168
170
172
174

DDR_B_D54

176

DDR_B_D55

178
180

DDR_B_D60

182

DDR_B_D61

184
186

DDR_B_DQS#7

188

DDR_B_DQS7

190
192

DDR_B_D62

194

DDR_B_D63

196
198
200

SMB_DATA_S3

202

SMB_CLK_S3

204

206

4

0.65A@0.75V

0.65A@0.75V

0.65A@0.75V0.65A@0.75V

For RF request

0.047U_0402_16V4Z

1

C54

@

2

DDR3_DRAMRST# <12,7>

DDR_CKE3_DIMMB <7>

M_CLK_DDR3 <7>
M_CLK_DDR#3 <7>

DDR_B_BS1 <7>
DDR_B_RAS# <7>

DDR_CS2_DIMMB# <7>
M_ODT2 <7>

M_ODT3 <7>

0.1U_0402_10V6K

1

C280

C281

2

SMB_DATA_S3 <12,15,37,46>
SMB_CLK_S3 <12,15,37,46>

+0.75VS

0.047U_0402_16V4Z

1

C55

@

2

+VREF_CB

2.2U_0603_6.3V6K

1

2

3

0.047U_0402_16V4Z

1

C56

@

2

Layout Note:
Place near DIMM

+1.5V

12

R86
1K_0402_1%

12

R87
1K_0402_1%

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

+1.5V

10U_0603_6.3V6M

1

C282

C161

@

@

2

Layout Note:
Place near DIMM

+0.75VS

1U_0402_6.3V6K

1

C173

1

C174

2

2

10U_0603_6.3V6M

1

2

1U_0402_6.3V6K

C175

2011/11/01

2011/11/01

2011/11/01

DDR_B_D[0..63] <7>

DDR_B_DQS[0..7] <7>

DDR_B_DQS#[0..7] <7>

DDR_B_MA[0..15] <7>

(10uF_0603_6.3V)*8
(

0.1uF_402_10V)*4

10U_0603_6.3V6M

1

C163

C164

2

1U_0402_6.3V6K

1

1

C176

2

2

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

1

2

10U_0603_6.3V6M

C165

1U_0402_6.3V6K

Deciphered Date

Deciphered Date

Deciphered Date

2

10U_0603_6.3V6M

10U_0603_6.3V6M

1

C166

2

10U_0603_6.3V6M

1

1

C167

2

2

Layout Note:
Place near DIMM

DDR_B_DM[0:7] connect to GND

2012/12/31

2012/12/31

2012/12/31

2

C168

10U_0603_6.3V6M

1

2

0.1U_0402_10V6K

1

C169

2

Title

Title

Title

DDRIII-SODIMM SLOT2

DDRIII-SODIMM SLOT2

DDRIII-SODIMM SLOT2

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

0.1U_0402_10V6K

1

C170

C171

2

Monday, January 14, 2013

Monday, January 14, 2013

Monday, January 14, 2013

1

0.1U_0402_10V6K

0.1U_0402_10V6K

1

1

C172

2

2

Y400S-NM-A141

Y400S-NM-A141

Y400S-NM-A141

1

13 65

13 65

13 65

1.0

1.0

1.0

5

4

3

2

1

W=20mils W=20mils

+RTCBATT +RTCVCC

D D

+RTCVCC

INTVRMEN

H

*

L

R99

12

1K_0402_5%

1 2

R101 1M_0402_5%

1 2

R102 330K_0402_5%

：：：：

Integrated VRM enable (Defaul t)

：：：：

Integrated VRM disable

1

2

C179
1U_0603_10V4Z

SM_INTRUDER#

PCH_INTVRMEN

+RTCVCC

1 2

R103 20K_04 02_5%

1 2

R100 20K_04 02_5%

1U_0603_10V4Z

1U_0603_10V4Z

(INTVRMEN should always be pull high.)

+3VS

*

C C

+3V_PCH

*

+3V_PCH

1 2

R105 1K_0402_5%@

HIGH= Enable ( No Reboot )
LOW= Disable (D efault)

R106 1K_0402_5%@

Low = Disabled (Default)
High = Enabled

R108 1K_0402_5%

12

[Flash Descrip tor Security O veride]

12

HDA_SPKR

HDA_SDOUT

HDA_SYNC

ME_FLASH<45>

This signal has a weak intern al pull-down

On Die PLL VR S elect is suppl ied by

1.5V when smapl ed high (Defau lt)

1.8V when sampl ed low

*

Needs to be pul led High for C hief River pla tfrom

ME_FLASH

+3V_PCH

SPI_CLK_PCH_0
SPI_CLK_PCH_1

SPI_SB_CS0#_R

SPI_CS1#_R

SPI_SI_R
SPI_SI_R1 SPI_SI

SPI_SO_L
SPI_SO_L1

R298 33_0402_5%
R299 33_0402_5%

R130 R_short 0_0402_5%

R303 R_short 0_0402_5%

R133 33_0402_5%
R204 33_0402_5%

R131 33_0402_5%
R294 33_0402_5%

CMOS

1

2

1

@

2

HDA_SPKR<42>

HDA_SDIN0<42>

1 2

1 2

12

12

12
12

12

JCMOS
SHORT PADS@

12

JME
SHORT PADS

12

12

C183

C182

R109 R_short 0_0402_5%

R107 1K_040 2_1%@

R317 10K_04 02_5%@

R110 51_0402_5 %

1 2
1 2

1 2
1 2

U4A

PCH_RTCX1

PCH_RTCX2

PCH_RTCRST#

PCH_SRTCRST#

SM_INTRUDER#

PCH_INTVRMEN SERIRQ

HDA_BIT_CLK

HDA_SYNC

HDA_SPKR

HDA_RST#

HDA_SDIN0

HDA_SDOUT

PCH_GPIO33

PCH_GPIO13

PCH_JTAG_TCK

PCH_JTAG_TMS

PCH_JTAG_TDI

PCH_JTAG_TDO

SPI_CLK_PCH

SPI_SB_CS0#

SPI_CS1#

SPI_SO_R

A20

RTCX1

C20

RTCX2

D20

RTCRST#

G22

SRTCRST#

K22

INTRUDER#

C17

INTVRMEN

N34

HDA_BCLK

L34

HDA_SYNC

T10

SPKR

K34

HDA_RST#

E34

HDA_SDIN0

G34

HDA_SDIN1

C34

HDA_SDIN2

A34

HDA_SDIN3

A36

HDA_SDO

C36

HDA_DOCK_EN# / GPIO33

N32

HDA_DOCK_RST# / GPIO13

J3

JTAG_TCK

H7

JTAG_TMS

K5

JTAG_TDI

H1

JTAG_TDO

T3

SPI_CLK

Y14

SPI_CS0#

T1

SPI_CS1#

V4

SPI_MOSI

U3

SPI_MISO

PANTHER-POINT_FCBGA989

RTCIHDA

JTAG

SPI

FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3

LPC

FWH4 / LFRAME#

LDRQ0#

LDRQ1# / GPIO23

SERIRQ

SATA0RXN
SATA0RXP

SATA0TXN
SATA0TXP

SATA1RXN
SATA1RXP

SATA 6G

SATA1TXN
SATA1TXP

SATA2RXN
SATA2RXP

SATA2TXN
SATA2TXP

SATA3RXN
SATA3RXP

SATA3TXN
SATA3TXP

SATA4RXN
SATA4RXP

SATA4TXN

SATA

SATA4TXP

SATA5RXN
SATA5RXP

SATA5TXN
SATA5TXP

SATAICOMPO

SATAICOMPI

SATA3RCOMPO

SATA3COMPI

SATA3RBIAS

SATALED#

SATA0GP / GPIO21

SATA1GP / GPIO19

EC and Mini car d debug port

C38

LPC_AD0

A38

LPC_AD1

B37

LPC_AD2

C37

LPC_AD3

D36

LPC_FRAME#

E36
K36

V5

AM3

SATA_DTX_C_IRX_N0

AM1

SATA_DTX_C_IRX_P0

AP7

SATA_ITX_C_DRX_N0

AP5

SATA_ITX_C_DRX_P0

AM10

SATA_DTX_C_IRX_N1

AM8

SATA_DTX_C_IRX_P1

AP11

SATA_ITX_C_DRX_N1

AP10

SATA_ITX_C_DRX_P1

AD7

SATA_DTX_C_IRX_N2

AD5

SATA_DTX_C_IRX_P2

AH5

SATA_ITX_C_DRX_N2

AH4

SATA_ITX_C_DRX_P2

AB8
AB10
AF3
AF1

Y7
Y5
AD3
AD1

Y3
Y1
AB3
AB1

Y11

Y10

SATA_COMP

AB12

AB13

SATA3_COMP

AH1

RBIAS_SATA3

P3

HDD_LED#

V14

PCH_GPIO21

P1

SATA_DET#

LPC_AD0 <37,45>
LPC_AD1 <37,45>
LPC_AD2 <37,45>
LPC_AD3 <37,45>

LPC_FRAME# <37,45>

R104 10K_0402_5%

12

SERIRQ <45>

12

C184 0.01U_0402_16V7K

12

C185 0.01U_0402_16V7K

12

C273 0.01U_0402_16V7K

12

C272 0.01U_0402_16V7K

12

C186 0.01U_0402_16V7K

12

C187 0.01U_0402_16V7K

1 2

R111 37.4_0402_1%

1 2

R113 49.9_0402_1%

1 2

R115 750_0402_1%

R120 10K_0402_5%

R119 10K_0402_5%

R316 10K_0402_5%

12

12

12

+3VS

SATA_ITX_DRX_N0
SATA_ITX_DRX_P0

SATA_ITX_DRX_N1
SATA_ITX_DRX_P1

SATA_ITX_DRX_N2_CONN
SATA_ITX_DRX_P2_CONN

+1.05VS_VCC_SATA

+1.05VS_SATA3

HDD_LED# <47>

SATA_DET# <37>

+3VS

+3VS

+3VS

S

HDD

ODD

SD

SATA_DTX_C_IRX_N0 <37>
SATA_DTX_C_IRX_P0 <37>

SATA_ITX_DRX_N0 <37>
SATA_ITX_DRX_P0 <37>

SATA_DTX_C_IRX_N1 <41>

SATA_DTX_C_IRX_P1 <41>
SATA_ITX_DRX_N1 <41>
SATA_ITX_DRX_P1 <41>

SATA_DTX_C_IRX_N2 <41>

SATA_DTX_C_IRX_P2 <41>
SATA_ITX_DRX_N2_CONN <41>
SATA_ITX_DRX_P2_CONN <41>

B B

HDA AUDIO

HDA_BITCLK_AUDIO<42>

HDA_SYNC_AUDIO<42>

HDA_RST_AUDIO#<42>

HDA_SDOUT_AUDIO<42>

1 2

R112
33_0402_5%

1 2

R114
33_0402_5%

1 2

R116
33_0402_5%

1 2

R118
33_0402_5%

HDA_BIT_CLK

HDA_SYNC_R

HDA_RST#

HDA_SDOUT

12

R1353
1M_0402_5%

+5VS

G

2

S

13

HDA_SYNC

D

Q10
BSS138_NL_SOT23-3

1

2

R98

1 2

10M_0402_5%

Y1

1 2

32.768KHZ_12.5PF_CM31532768DZFT

C180
18P_0402_50V8J

PCH_RTCX1

PCH_RTCX2

1

C181
18P_0402_50V8J

2

For EMI

SPI_CLK_PCH

33_0402_5%

22P_0402_50V8J

R124

C190

12

@

@

4MB P/N : SA00005P500 2MB P/N : SA00003FO10

+3V_PCH +3V_PCH +3V_PCH

12

R123

@

200_0402_5%

12

R128

@

100_0402_1%

4

5

12

R122

@

200_0402_5%

12

R126

@

100_0402_1%

12

R121

@

A A

200_0402_5%

PCH_JTAG_TDO PCH_JTAG_TDIPCH_JTAG_TMS

12

R125

@

100_0402_1%

+3VS

1 2

R127 3.3K_0402_5%

1 2

R129 3.3K_0402_5%

U5

SPI_SB_CS0#_R

SPI_SO_L
SPI_WP#

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUT URE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUT URE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUT URE CENTER.

1

CS#

2

DO

HOLD#

3

WP#

4

GND

W25Q32BVSSIG_SO8

2011/11/01

2011/11/01

2011/11/01

3

VCC

CLK

SPI_WP#
SPI_HOLD#

8
7

SPI_HOLD#

6

SPI_CLK_PCH_0

5

SPI_SI_R

DI

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

+3VS

1

2

Deciphered Date

Deciphered Date

Deciphered Date

C191

0.1U_0402_16V4Z

2

2012/12/31

2012/12/31

2012/12/31

+3VS

1 2

R292 3.3K_0402_5%

1 2

R246 3.3K_0402_5%

SPI_CS1#_R
SPI_SO_L1
SPI_WP#_1

1
2
3
4

Title

Title

Title

PCH (1/9) SATA,HDA,SPI, LPC, XDP

PCH (1/9) SATA,HDA,SPI, LPC, XDP

PCH (1/9) SATA,HDA,SPI, LPC, XDP

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

U9

CS#
DO(IO1)

HOLD#(IO3)
WP#(IO2)
GND

W25Q16BVSSIG_SO8

DI(IO0)

Monday, January 14, 2013

Monday, January 14, 2013

Monday, January 14, 2013

SPI_WP#_1
SPI_HOLD#_1

8

VCC

7
6

CLK

5

Y400S-NM-A141

Y400S-NM-A141

Y400S-NM-A141

SPI_HOLD#_1
SPI_CLK_PCH_1
SPI_SI_R1

1

+3VS

1

C275

0.1U_0402_16V4Z

2

of

of

of

14 65

14 65

14 65

1.0

1.0

1.0

5

PCIE_PRX_DTX_N1<38>

LAN

D D

WLAN

Card Reader

C C

PCIE_PRX_DTX_P1<38>
PCIE_PTX_C_DRX_N1<38>
PCIE_PTX_C_DRX_P1<38>

PCIE_PRX_DTX_N2<37>
PCIE_PRX_DTX_P2<37>
PCIE_PTX_C_DRX_N2<37>
PCIE_PTX_C_DRX_P2<37>

PCIE_PRX_DTX_N4<44>
PCIE_PRX_DTX_P4<44>
PCIE_PTX_C_DRX_N4<44>
PCIE_PTX_C_DRX_P4<44>

LAN

WLAN

1 2

C192 0.1U_0402_10V7K

1 2

C193 0.1U_0402_10V7K

1 2

C194 0.1U_0402_10V7K

1 2

C195 0.1U_0402_10V7K

1 2

C277 0.1U_0402_10V7K

1 2

C276 0.1U_0402_10V7K

CLK_PCIE_LAN#<38>
CLK_PCIE_LAN<38>

CLKREQ_LAN#<38>

CLK_PCIE_WLAN1#<37>
CLK_PCIE_WLAN1<37>

WLAN_CLKREQ1#<37>

Only for 15" TV function

Card Reader

B B

2nd VGA

+3V_PCH

R152 10K_0402_5%

R168 10K_0402_5%

R165 10K_0402_5%

R147 10K_0402_5%

R170 10K_0402_5%

R172 10K_0402_5%

R174 10K_0402_5%

+3VS

A A

R158 10K_0402_5%

R308 10K_0402_5%

12

12

12

12

12

12

12

12

12

CLK_PCIE_CARD_PCH#<44>
CLK_PCIE_CARD_PCH<44>

CLKREQ_LAN#

PCH_GPIO25

PCH_GPIO26

PCH_GPIO44

CLK2_REQ_GPU#_R

PCH_GPIO45

PCH_GPIO46

WLAN_CLKREQ1#

PCH_GPIO20

CLK_PCIE_2VGA#<32>
CLK_PCIE_2VGA<32>

CLK2_REQ_GPU#_R<32>

PCIE_PRX_DTX_N1
PCIE_PRX_DTX_P1
PCIE_PTX_DRX_N1
PCIE_PTX_DRX_P1

PCIE_PRX_DTX_N2
PCIE_PRX_DTX_P2
PCIE_PTX_DRX_N2
PCIE_PTX_DRX_P2

PCIE_PRX_DTX_N4
PCIE_PRX_DTX_P4
PCIE_PTX_DRX_N4
PCIE_PTX_DRX_P4

CLK_PCIE_LAN#
CLK_PCIE_LAN

CLKREQ_LAN#

CLK_PCIE_WLAN1#
CLK_PCIE_WLAN1

WLAN_CLKREQ1#

PCH_GPIO20

CLK_PCIE_CARD_PCH#
CLK_PCIE_CARD_PCH

PCH_GPIO25

PCH_GPIO26

PCH_GPIO44

CLK_PCIE_2VGA#
CLK_PCIE_2VGA

CLK2_REQ_GPU#_R

PCH_GPIO45

PCH_GPIO46

4

BG34

BJ34
AV32
AU32

BE34

BF34

BB32

AY32

BG36

BJ36
AV34
AU34

BF36
BE36

AY34
BB34

BG37
BH37

AY36
BB36

BJ38
BG38
AU36
AV36

BG40

BJ40

AY40
BB40

BE38
BC38

AW38

AY38

Y40
Y39

J2

AB49
AB47

M1

AA48
AA47

V10

Y37
Y36

A8

Y43
Y45

L12

V45
V46

L14

AB42
AB40

E6

V40
V42

T13

V38
V37

K12

AK14
AK13

PANTHER-POINT_FCBGA989

U4B

PERN1
PERP1
PETN1
PETP1

PERN2
PERP2
PETN2
PETP2

PERN3
PERP3
PETN3
PETP3

PERN4
PERP4
PETN4
PETP4

PERN5
PERP5
PETN5
PETP5

PERN6
PERP6
PETN6
PETP6

PERN7
PERP7
PETN7
PETP7

PERN8
PERP8
PETN8
PETP8

CLKOUT_PCIE0N
CLKOUT_PCIE0P

PCIECLKRQ0# / GPIO73

CLKOUT_PCIE1N
CLKOUT_PCIE1P

PCIECLKRQ1# / GPIO18

CLKOUT_PCIE2N
CLKOUT_PCIE2P

PCIECLKRQ2# / GPIO20

CLKOUT_PCIE3N
CLKOUT_PCIE3P

PCIECLKRQ3# / GPIO25

CLKOUT_PCIE4N
CLKOUT_PCIE4P

PCIECLKRQ4# / GPIO26

CLKOUT_PCIE5N
CLKOUT_PCIE5P

PCIECLKRQ5# / GPIO44

CLKOUT_PEG_B_N
CLKOUT_PEG_B_P

PEG_B_CLKRQ# / GPIO56

CLKOUT_PCIE6N
CLKOUT_PCIE6P

PCIECLKRQ6# / GPIO45

CLKOUT_PCIE7N
CLKOUT_PCIE7P

PCIECLKRQ7# / GPIO46

CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P

SMBUSController

SML1ALERT# / PCHHOT# / GPIO74

PCI-E*

CLOCKS

SMBALERT# / GPIO11

SML0ALERT# / GPIO60

SML1CLK / GPIO58

SML1DATA / GPIO75

Link

PEG_A_CLKRQ# / GPIO47

CLKOUT_PEG_A_N
CLKOUT_PEG_A_P

CLKOUT_DMI_N
CLKOUT_DMI_P

CLKOUT_DP_N

CLKOUT_DP_P

CLKIN_DMI_N
CLKIN_DMI_P

CLKIN_GND1_N
CLKIN_GND1_P

CLKIN_DOT_96N
CLKIN_DOT_96P

CLKIN_SATA_N
CLKIN_SATA_P

REFCLK14IN

CLKIN_PCILOOPBACK

XTAL25_OUT

XCLK_RCOMP

CLKOUTFLEX0 / GPIO64

CLKOUTFLEX1 / GPIO65

CLKOUTFLEX2 / GPIO66

CLKOUTFLEX3 / GPIO67

FLEX CLOCKS

3

E12

PCH_GPIO11

H14

SMBCLK

SMBDATA

SML0CLK

SML0DATA

CL_CLK1

CL_DATA1

CL_RST1#

XTAL25_IN

PCH_SMBCLK

C9

PCH_SMBDATA

A12

C8

SML0CLK

G12

SML0DATA

C13

PCH_HOT#

E14

SML1CLK

M16

SML1DATA

M7

T11

P10

M10

CLK_REQ_GPU#_R

AB37

CLK_PCIE_VGA#

AB38

CLK_PCIE_VGA

AV22

CLK_CPU_DMI#

AU22

CLK_CPU_DMI

AM12
AM13

BF18

CLK_BUF_CPU_DMI#

BE18

CLK_BUF_CPU_DMI

BJ30

CLKIN_DMI2#

BG30

CLKIN_DMI2

G24

CLK_BUF_DREF_96M#

E24

CLK_BUF_DREF_96M

AK7

CLK_BUF_PCIE_SATA#

AK5

CLK_BUF_PCIE_SATA

K45

CLK_BUF_ICH_14M

H45

CLK_PCI_LPBACK

V47

XTAL25_IN

V49

XTAL25_OUT

Y47

XCLK_RCOMP

K43

F47

H47

S_DGPU_RST_R

K49

PCH_GPIO67

BIOS Request SKU ID

GP

IO64, 65 that only for GC6

1. GPIO64 : S_DGPU_GC6_EN

2. GPIO65 : S_DGPU_PWROK

+3V_PCH

DRAMRST_CNTRL_PC H <7>

CLK_REQ_GPU#_R <23>

R155 10K_0402_5%
R157 10K_0402_5%

R159 10K_0402_5%
R160 10K_0402_5%

R162 10K_0402_5%
R163 10K_0402_5%

R164 10K_0402_5%
R166 10K_0402_5%

R167 10K_0402_5%

R171 90.9_0402_1%

R182 10K_0402_5%

R1504 0_0402_5%

2

R136

1 2

2.2K_0402_5%

R135

1 2

2.2K_0402_5%

PCH_SMBCLK

PCH_SMBDATA SMB_DATA_S3

+3V_PCH +3V S

CLK_PCIE_VGA# <23>
CLK_PCIE_VGA <23>

CLK_CPU_DMI# <6>
CLK_CPU_DMI <6>

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2

CLK_PCI_LPBACK <18>

1 2

12

1 2

PCH_GPIO67 <19>

1 2

1 2

SML1CLK

SML1DATA

+1.05VS_VCCDIFFCLKN

+3VS

3 4

R141

2.2K_0402_5%

R142

2.2K_0402_5%

S_DGPU_RST <18,32>

5

G

D

2

G

6 1

D

Q60B

S

2N7002KDWH_SOT363-6

3 4

DI

MM1, DIMM2, Mini CARD, TP

2N7002KDWH
Vth= min 1V, max 2.5V
ESD 2KV

SMB_CLK_S3

S

Q60A
2N7002KDWH_SOT363-6

R137

R138

20120731 --> ch ange to +3VS

VGA, EC, Thermal Sensor

2

G

20120731 --> change to +3VS

6 1

D

5

G

D

S

20120816 --->

1.

2. C196, C197 change to 10pf

EC_SMB_CK2

S

Q61A
2N7002KDWH_SOT363-6

EC_SMB_DA2

Q61B
2N7002KDWH_SOT363-6

PCH_GPIO11

DRAMRST_CNTRL_PC H

SML0CLK

SML0DATA

PCH_HOT#

CLK_REQ_GPU#_R

XTAL25_IN

XTAL25_OUT

1

2

change P/N to 7V2500014(10pf), SJ10000E80J

Reserve for EMI please close to
PCH

CLK_BUF_ICH_14M

CLK_PCI_LPBACK

1

12

2.2K_0402_5%

12

2.2K_0402_5%

SMB_CLK_S3 < 12,13,37,46>

SMB_DATA_S3 <12,13,37,46>

EC_SMB_CK2 <23,32,40,45>

EC_SMB_DA2 <23,32,40,45>

R134

R329

R335

1 2

R336

1 2

R140

R202

1 2

1 2

1M_0402_5%

Y2

1

1

GND

2

25MHZ_10PF_7V25000014

C196
10P_0402_50V8J

R175

@

33_0402_5%

12

R176

@

33_0402_5%

12

12

10K_0402_5%

12

1K_0402_5%

2.2K_0402_5%

2.2K_0402_5%

12

10K_0402_5%

10K_0402_5%

R169

GND

10P_0402_50V8J

+3VS

+3V_PCH

3

3

4

C197

C198

@

22P_0402_50V8J

1 2

C199

@

22P_0402_50V8J

1 2

1

2

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

3

2011/11/01

2011/11/01

2011/11/01

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2012/12/31

2012/12/31

2012/12/31

Title

PCH (2/9) PCIE, SMBUS, CLK

PCH (2/9) PCIE, SMBUS, CLK

PCH (2/9) PCIE, SMBUS, CLK

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Monday, January 14, 2013

Monday, January 14, 2013

Monday, January 14, 2013

Y400S-NM-A141

Y400S-NM-A141

Y400S-NM-A141

1

of

of

of

15 65

15 65

15 65

1.0

1.0

1.0

5

D D

+3VS

1

C1060

0.1U_0402_16V4Z

VGATE<59>

C C

B B

+3V_PCH

MC74VHC1G08DFT2G SC70 5P

R192 200_0402_5%

R194 10K_0402_5%

VGATE

PCH_PWROK

12

12

2

2

B

1

A

U6

F

or Deep S3

For Deep S3

5

P

4

Y

12

G

3

PM_DRAM_PWR GD

SUSWARN#

R180

@

100K_0402_1%

PCH_PWROK<45>

APWROK can be c onnect to
PWROK if iAMT d isable

PM_DRAM_PWR GD<6>

PBTN_OUT#<45>

AC_PRESENT<45>

+3V_PCH

SYS_PWROK <6>

SUSACK#<45> DPWROK_EC <45>

+3VS

SUSWARN#<45>

+3VS

R1290 200_0402_5%@

7/28 Modify fol low Module Des ign.

4

DMI_CTX_PRX_N0<5>
DMI_CTX_PRX_N1<5>
DMI_CTX_PRX_N2<5>
DMI_CTX_PRX_N3<5>

DMI_CTX_PRX_P0<5>
DMI_CTX_PRX_P1<5>
DMI_CTX_PRX_P2<5>
DMI_CTX_PRX_P3<5>

DMI_CRX_PTX_N0<5>
DMI_CRX_PTX_N1<5>
DMI_CRX_PTX_N2<5>
DMI_CRX_PTX_N3<5>

DMI_CRX_PTX_P0<5>
DMI_CRX_PTX_P1<5>
DMI_CRX_PTX_P2<5>
DMI_CRX_PTX_P3<5>

+1.05VS

R1457 R_short 0_0402_5%

R184 10K_0402_5%

R190

R_short 0_0402_5%

1 2

R193 R_short 0_0402_5%

R1455 R_short 0_0402_5%

1 2

R198 R_short 0_0402_5%

1 2

R208 R_short 0_0402_5%

1 2

R200 8.2K_0402_5%

R201 10K_0402_5%

12

R177

1 2

49.9_0402_1%

R178

1 2

750_0402_1%

4mil width and place
within 500mil o f the PCH

12

12

12

R191

R_short 0_0402_5%

12

12

PM_DRAM_PWR GD

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

DMI_IRCOMP

RBIAS_CPY

SUSACK#_R

SYS_RST#

SYS_PWROK

PWROK

12

APWROK

PM_DRAM_PWR GD

PCH_RSMRST#_R

SUSWARN#_R

PBTN_OUT#_R

AC_PRESENT_R

PCH_GPIO72

RI#

U4C

BC24

DMI0RXN

BE20

DMI1RXN

BG18

DMI2RXN

BG20

DMI3RXN

BE24

DMI0RXP

BC20

DMI1RXP

BJ18

DMI2RXP

BJ20

DMI3RXP

AW24

DMI0TXN

AW20

DMI1TXN

BB18

DMI2TXN

AV18

DMI3TXN

AY24

DMI0TXP

AY20

DMI1TXP

AY18

DMI2TXP

AU18

DMI3TXP

BJ24

DMI_ZCOMP

BG25

DMI_IRCOMP

BH21

DMI2RBIAS

C12

SUSACK#

K3

SYS_RESET#

P12

SYS_PWROK

L22

PWROK

L10

APWROK

B13

DRAMPWROK

C21

RSMRST#

K16

SUSWARN#/SUSPW RDNACK/GPIO30

E20

PWRBTN#

H20

ACPRESENT / GPIO31

E10

BATLOW# / GPIO72

A10

RI#

PANTHER-POINT_FCBGA989

3

FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7

FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5

DMI

System Power Management

FDI_RXP6

FDI

FDI_RXP7

FDI_INT

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

DSWVRMEN

DPWROK

WAKE#

CLKRUN# / GPIO32

SUS_STAT# / GPIO61

SUSCLK / GPIO62

SLP_S5# / GPIO63

SLP_S4#

SLP_S3#

SLP_A#

SLP_SUS#

PMSYNCH

SLP_LAN# / GPIO29

2

BJ14

FDI_CTX_PRX_N0

AY14

FDI_CTX_PRX_N1

BE14

FDI_CTX_PRX_N2

BH13

FDI_CTX_PRX_N3

BC12

FDI_CTX_PRX_N4

BJ12

FDI_CTX_PRX_N5

BG10

FDI_CTX_PRX_N6

BG9

FDI_CTX_PRX_N7

BG14

FDI_CTX_PRX_P0

BB14

FDI_CTX_PRX_P1

BF14

FDI_CTX_PRX_P2

BG13

FDI_CTX_PRX_P3

BE12

FDI_CTX_PRX_P4

BG12

FDI_CTX_PRX_P5

BJ10

FDI_CTX_PRX_P6

BH9

FDI_CTX_PRX_P7

AW16

FDI_INT

AV12

FDI_FSYNC0

BC10

FDI_FSYNC1

AV14

FDI_LSYNC0

BB10

FDI_LSYNC1

A18

DSWODVREN

E22

PCH_DPWROK_R

B9

N3

PM_CLKRUN#

G8

SUS_STAT#

N14

SUSCLK

D10

PM_SLP_S5#

H4

PM_SLP_S4#

F4

PM_SLP_S3#

G10

Can be left NC when IAMT is n ot support on the platfrom

G16

PM_SLP_SUS#_R

AP14

H_PM_SYNC

K14

PCH_GPIO29

Can be left NC if no use inte grated LAN.
10/06 Test poin t request

FDI_CTX_PRX_N0 <5>
FDI_CTX_PRX_N1 <5>
FDI_CTX_PRX_N2 <5>
FDI_CTX_PRX_N3 <5>
FDI_CTX_PRX_N4 <5>
FDI_CTX_PRX_N5 <5>
FDI_CTX_PRX_N6 <5>
FDI_CTX_PRX_N7 <5>

FDI_CTX_PRX_P0 <5>
FDI_CTX_PRX_P1 <5>
FDI_CTX_PRX_P2 <5>
FDI_CTX_PRX_P3 <5>
FDI_CTX_PRX_P4 <5>
FDI_CTX_PRX_P5 <5>
FDI_CTX_PRX_P6 <5>
FDI_CTX_PRX_P7 <5>

FDI_INT <5>

FDI_FSYNC0 <5>

FDI_FSYNC1 <5>

FDI_LSYNC0 <5>

FDI_LSYNC1 <5>

1 2

R181 R_short 0_0402_5%

1 2

R185 R_short 0_0402_5%

1 2

R253 10K_0402_5%

T60PAD

T61PAD

T62PAD

PM_SLP_S4# <45>EC_RSMRST#<45>

PM_SLP_S3# <45>

R1447 R_short 0_0402_5%

12

H_PM_SYNC <6>

T74PAD

DSWODVREN - On Die DSW VR Ena ble

*

H

：：：：

Enable

：：：：

Disable

L

DPWROK_EC

PCIE_WAKE#WAKE#

PCIE_WAKE# <19,37,38>

WAKE#

R186 10K_0402_5%

PM_SLP_SUS# <45,51>

1

DSWODVREN

1 2

+RTCVCC

For Deep S3

For Deep S3

12

R179
330K_0402_5%

12

R183
330K_0402_5%@

+3V_PCH

+3VALW

R195 200K_0402_5%

A A

12

5

AC_PRESENT_R

R197 10K_0402_5%

12

4

PCH_RSMRST#_R

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

3

2011/11/01

2011/11/01

2011/11/01

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2012/12/31

2012/12/31

2012/12/31

Title

Title

Title

PCH (3/9) DMI,FDI,PM,

PCH (3/9) DMI,FDI,PM,

PCH (3/9) DMI,FDI,PM,

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Monday, January 14, 2013

Monday, January 14, 2013

Monday, January 14, 2013

Y400S-NM-A141

Y400S-NM-A141

Y400S-NM-A141

1

of

of

of

16 65

16 65

16 65

1.0

1.0

1.0

5

D D

+3VS

OPT@

R836 2.2K_0402_5%

OPT@

R835 2.2K_0402_5%

OPT@

1 2

R205 2.2K_0402_5%

OPT@

1 2

R261 2.2K_0402_5%

OPT@

OPT@

OPT@

OPT@

OPT@

1 2

OPT@

1 2

12

12

12

12

R257 2.37K_0402_1%

C C

R266 150_0402_1%

R264 150_0402_1%

R262 150_0402_1%

B B

+3VS

R848 2.2K_0402_5%

R849 2.2K_0402_5%

EDID_CLK

EDID_DATA

CTRL_CLK

CTRL_DATA CTRL_CLK

LVDS_IBG

DAC_BLU

DAC_GRN

DAC_RED

CRT_DDC_CLK

CRT_DDC_DATA

4

PCH_ENBKL<34>
PCH_ENVDD<34>

PCH_PWM<34>

EDID_CLK<34>
EDID_DATA<34>

Remove netname LVD_REF

LVDS_ACLK#<34>
LVDS_ACLK<34>

LVDS_A0#<34>
LVDS_A1#<34>
LVDS_A2#<34>

LVDS_A0<34>
LVDS_A1<34>
LVDS_A2<34>

DAC_BLU<35>
DAC_GRN<35>
DAC_RED< 35>

CRT_DDC_CLK<35>
CRT_DDC_DATA<35>

CRT_HSYNC<35>
CRT_VSYNC<35>

R211

1K_0402_1%

PCH_ENBKL
PCH_ENVDD

PCH_PWM

EDID_CLK
EDID_DATA

CTRL_DATA

LVDS_IBG

LVDS_ACLK#
LVDS_ACLK

LVDS_A0#
LVDS_A1#
LVDS_A2#

LVDS_A0
LVDS_A1
LVDS_A2

DAC_BLU
DAC_GRN
DAC_RED

CRT_DDC_CLK
CRT_DDC_DATA

CRT_HSYNC
CRT_VSYNC

CRT_IREF

12

U4D

J47

L_BKLTEN

M45

L_VDD_EN

P45

L_BKLTCTL

T40

L_DDC_CLK

K47

L_DDC_DATA

T45

L_CTRL_CLK

P39

L_CTRL_DATA

AF37

LVD_IBG

AF36

LVD_VBG

AE48

LVD_VREFH

AE47

LVD_VREFL

AK39

LVDSA_CLK#

AK40

LVDSA_CLK

AN48

LVDSA_DATA#0

AM47

LVDSA_DATA#1

AK47

LVDSA_DATA#2

AJ48

LVDSA_DATA#3

AN47

LVDSA_DATA0

AM49

LVDSA_DATA1

AK49

LVDSA_DATA2

AJ47

LVDSA_DATA3

AF40

LVDSB_CLK#

AF39

LVDSB_CLK

AH45

LVDSB_DATA#0

AH47

LVDSB_DATA#1

AF49

LVDSB_DATA#2

AF45

LVDSB_DATA#3

AH43

LVDSB_DATA0

AH49

LVDSB_DATA1

AF47

LVDSB_DATA2

AF43

LVDSB_DATA3

N48

CRT_BLUE

P49

CRT_GREEN

T49

CRT_RED

T39

CRT_DDC_CLK

M40

CRT_DDC_DATA

M47

CRT_HSYNC

M49

CRT_VSYNC

T43

DAC_IREF

T42

CRT_IRTN

PANTHER-POINT_FCBGA989

3

SDVO_INTN
SDVO_INTP

DDPB_HPD

DDPB_0N

DDPB_0P

DDPB_1N

DDPB_1P

DDPB_2N

DDPB_2P

DDPB_3N

DDPB_3P

DDPC_HPD

DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P

DDPD_HPD

DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P

AP43
AP45

AM42
AM40

AP39
AP40

P38
M39

AT49
AT47
AT40

AV42
AV40
AV45
AV46
AU48
AU47
AV47
AV49

P46
P42

AP47
AP49
AT38

AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49

M43
M36

AT45
AT43
BH41

BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42

SDVO_TVCLKINN
SDVO_TVCLKINP

SDVO_STALLN
SDVO_STALLP

SDVO_CTRLCLK

SDVO_CTRLDATA

DDPB_AUXN
DDPB_AUXP

LVDS

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPC_AUXN
DDPC_AUXP

Digital Display Interface

DDPD_CTRLCLK

DDPD_CTRLDATA

DDPD_AUXN

CRT

DDPD_AUXP

HDMICLK
HDMIDAT

TMDS_B_HPD

TMDS_B_DATA2#_PCH
TMDS_B_DATA2_PCH
TMDS_B_DATA1#_PCH
TMDS_B_DATA1_PCH
TMDS_B_DATA0#_PCH
TMDS_B_DATA0_PCH
TMDS_B_CLK#_PCH
TMDS_B_CLK_PCH

2

HDMICLK <36>
HDMIDAT <36>

TMDS_B_HPD <36>

TMDS_B_DATA2#_PCH <36>
TMDS_B_DATA2_PCH <36>
TMDS_B_DATA1#_PCH <36>
TMDS_B_DATA1_PCH <36>
TMDS_B_DATA0#_PCH <36>
TMDS_B_DATA0_PCH <36>
TMDS_B_CLK#_PCH <36>
TMDS_B_CLK_PCH <36>

HDMICLK

HDMIDAT

1

OPT@

OPT@

12

12

R203 2.2K_0402_5%

R267 2.2K_0402_5%

+3VS

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUT URE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUT URE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUT URE CENTER.

3

2011/11/01

2011/11/01

2011/11/01

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2012/12/31

2012/12/31

2012/12/31

Title

PCH (4/9) LVDS,CRT,DP,HDMI

PCH (4/9) LVDS,CRT,DP,HDMI

PCH (4/9) LVDS,CRT,DP,HDMI

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Monday, January 14, 2013

Monday, January 14, 2013

Monday, January 14, 2013

Y400S-NM-A141

Y400S-NM-A141

Y400S-NM-A141

1

of

of

of

17 65

17 65

17 65

1.0

1.0

1.0

5

4

3

2

1

+3VS

D D

+3VS

C C

GP

IO53 => This Signal has a weak internal pull-up.
NOTE: The internal pull-up is disabled after
PLTRST# deasserts.

B B

PCH_GPIO51

A A

RP2

18

PCI_PIRQA#

27

PCI_PIRQD#

36

PCI_PIRQC#

45

8.2K_0804_8P4R_5%

8.2K_0804_8P4R_5%

R305 8.2K_0402_5%@

R297 8.2K_0402_5%@

R213 8.2K_0402_5%

R225 8.2K_0402_5%

R212 8.2K_0402_5%

R252 8.2K_0402_5%

R306 8.2K_0402_5%

R214 8.2K_0402_5%

R215 1K_0402_5%@

A16 swap overide Strap/Top-Block
Swap Override jumper

PCI_GNT3#

PCI_PIRQB#

RP1

18

PCH_GPIO2

27

DGPU_PWR_EN

36

PCH_GPIO4

45

ODD_DA#_R

1 2

1 2

1 2

1 2

1 2

1 2

1 2

@

1 2

@

12

Low = A16 swap
override/Top-Block
Swap Override enabled

**High=Default

*

1 2

R221 1K_0402_5%@

PPT EDS DOC#474146

Boot BIOS Strap bit1 BBS1

Boot BIOS

Bit10

0

1

0

Destination

eserved

R

Reserved

SPI

*

LPC

GNT1#/
GPIO51

Bit11

0 1

1

1

0

5

PCH_GPIO51

DGPU_GC6_EN

PCH_GPIO5

PCH_WL_OFF#

NVDD_PWR_EN

DGPU_HOLD_RST#

DGPU_GC6_EN

DGPU_HOLD_RST#

PCH_WL_OFF#

S_DGPU_RST<15,32>

CLK_PCI_LPBACK<15>
CLK_PCI_EC<45>

CLK_PCI_DB<37>

(Default)

Port1

Port2

Port3

Port4

USB30_RX_N3<48>

USB30_RX_P3<48>

USB30_TX_N3<48>

USB30_TX_P3<48>

DGPU_HOLD_RST#<23>

1 2

R1505 0_0402_5%@

NVDD_PWR_EN<58>
DGPU_PWR_EN<23,51>

DGPU_GC6_EN<27>
PCH_WL_OFF#<37>

ODD_DA#_R<41>

PLT_RST#<23,32,37,38,44,45,6>

1 2

R219 22_0402_5%

1 2

R220 22_0402_5%
R173 22_0402_5%

4

12

@

USB3.0

LEFT USB

USB30_RX_N3

USB30_RX_P3

USB30_TX_N3

USB30_TX_P3

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

DGPU_HOLD_RST#
NVDD_PWR_EN
DGPU_PWR_EN

PCH_GPIO51
DGPU_GC6_EN
PCH_WL_OFF#

PCH_GPIO2
ODD_DA#_R
PCH_GPIO4
PCH_GPIO5

20111024 Del PC I_PME#

PLT_RST#

CLK_PCI_LPBACK_R
CLK_PCI_EC_R
CLK_PCI_DB_R

PLT_RST#

12

R223
100K_0402_5%

U4E

BG26

TP1

BJ26

TP2

BH25

TP3

BJ16

TP4

BG16

TP5

AH38

TP6

AH37

TP7

AK43

TP8

AK45

TP9

C18

TP10

N30

TP11

H3

TP12

AH12

TP13

AM4

TP14

AM5

TP15

Y13

TP16

K24

TP17

L24

TP18

AB46

TP19

AB45

TP20

B21

TP21

M20

TP22

AY16

TP23

BG46

TP24

BE28

USB3Rn1

BC30

USB3Rn2

BE32

USB3Rn3

BJ32

USB3Rn4

BC28

USB3Rp1

BE30

USB3Rp2

BF32

USB3Rp3

BG32

USB3Rp4

AV26

USB3Tn1

BB26

USB3Tn2

AU28

USB3Tn3

AY30

USB3Tn4

AU26

USB3Tp1

AY26

USB3Tp2

AV28

USB3Tp3

AW30

USB3Tp4

K40

PIRQA#

K38

PIRQB#

H38

PIRQC#

G38

PIRQD#

C46

REQ1# / GPIO50

C44

REQ2# / GPIO52

E40

REQ3# / GPIO54

D47

GNT1# / GPIO51

E42

GNT2# / GPIO53

F46

GNT3# / GPIO55

G42

PIRQE# / GPIO2

G40

PIRQF# / GPIO3

C42

PIRQG# / GPIO4

D44

PIRQH# / GPIO5

K10

PME#

C6

PLTRST#

H49

CLKOUT_PCI0

H43

CLKOUT_PCI1

J48

CLKOUT_PCI2

K42

CLKOUT_PCI3

H40

CLKOUT_PCI4

PANTHER-POINT_FCBGA989

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

RSVD

PCI

USB

OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43

OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14

2011/11/01

2011/11/01

2011/11/01

3

AY7

RSVD1

AV7

RSVD2

AU3

RSVD3

BG4

RSVD4

AT10

RSVD5

BC8

RSVD6

AU2

RSVD7

AT4

RSVD8

AT3

RSVD9

AT1

RSVD10

AY3

RSVD11

AT5

RSVD12

AV3

RSVD13

AV1

RSVD14

BB1

RSVD15

BA3

RSVD16

BB5

RSVD17

BB3

RSVD18

BB7

RSVD19

BE8

RSVD20

BD4

RSVD21

BF6

RSVD22

AV5

RSVD23

AV10

RSVD24

AT8

RSVD25

AY5

RSVD26

BA2

RSVD27

AT12

RSVD28

BF3

RSVD29

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P

USBP10N

USBP10P

USBP11N

USBP11P

USBP12N

USBP12P

USBP13N

USBP13P

USBRBIAS#

USBRBIAS

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

USB DEBUG = PORT1 AND PORT9

C24

USB20_N0

A24

USB20_P0

C25
B25
C26

USB20_N2

A26

USB20_P2

K28
H28
E28
D28
C28

USB20_N5

A28

USB20_P5

C29
B29
N28
M28
L30
K30
G30

USB20_N9

E30

USB20_P9

C30

USB20_N10

A30

USB20_P10

L32
K32
G32
E32
C32

USB20_N13

A32

USB20_P13

C33

USBRBIAS

Within 500 mils

B33

A14

USB_OC0#

K20

USB_OC1#

B17

USB_OC2#

C16

USB_OC3#

L16

USB_OC4#

A16

USB_OC5#

D14

USB_OC6#

C14

USB_OC7#

Deciphered Date

Deciphered Date

Deciphered Date

USB20_N0 <34>
USB20_P0 <34>

USB20_N2 <48>
USB20_P2 <48>

USB20_N5 <49>
USB20_P5 <49>

Camera

LEFT USB

RIGHT USB 1 (CHARGER PORT, SUB/B)

Some PCH config not support U SB port 6 & 7.

2

USB20_N9 <49>
USB20_P9 <49>
USB20_N10 <37>
USB20_P10 <37>

USB20_N13 <47>
USB20_P13 <47>

R218

1 2

22.6_0402_1%

USB_OC1# <48>
USB_OC2# <49>

USB_OC4# <49>

2012/12/31

2012/12/31

2012/12/31

RIGHT USB 2 (SUB/B)
WLAN

BT

USB3 Port3, USB 2 Port2

SB2 Port5, Char ger Port

U

USB2 Port9, Rig ht USB (Sub/B)

+3V_PCH

RP3

USB_OC5#
USB_OC2#
USB_OC7#
USB_OC0#

USB_OC6#
USB_OC1#
USB_OC4#
USB_OC3#

Title

Title

Title

PCH (5/9) PCI, USB

PCH (5/9) PCI, USB

PCH (5/9) PCI, USB

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Monday, January 14, 2013

Monday, January 14, 2013

Monday, January 14, 2013

Y400S-NM-A141

Y400S-NM-A141

Y400S-NM-A141

1

4 5
3 6
2 7
1 8

10K_1206_8P4R_5%

RP4

4 5
3 6
2 7
1 8

10K_1206_8P4R_5%

of

of

of

18 65

18 65

18 65

1.0

1.0

1.0

5

D D

+3VS

R1493 10K_0402_5%

+3V_PCH

R235 10K_0402_5%

GPIO28

On-Die PLL Voltage Regulator
This signal has a weak internal pull up

：

On-Die voltage regulator enab le

H

*

L

：

On-Die PLL Volt age Regulator disable

R240 1K_0402_5%@

C C

PCH_GPIO27 (Have internal Pull-High)

*

H

igh: VCCVRM VR Enable

Low: VCCVRM VR Disable

+3VALW

R207 10K_0402_5%

R245 10K_0402_5%@

R250 200K_0402_5%

+3VS

B B

+3V_PCH

R251

R259 10K_0402_5%

1 2

DS3@

1 2

1 2

1 2

1 2

12

12

12

10K_0402_5%

EC_SCI#

EC_SMI#

PCH_GPIO28

DS3_WAKE#_R

ODD_DETECT#

SLAVE_PRESENT#

PCH_GPIO37

GC6_EVENT#<23,32,45>

+3VS

+3VS

+3V_PCH

EC_LID_OUT#<45>

+3VS

DGPU_PWROK<27,55,58>

PCH_BT_DISABLE#<37>

PCH_BT_ON#<37,47>

+3VS

PCIE_WAKE#<16,37,38>

+3VS

+3VS

4

1 2

R233 10K_0402_5%

1 2

R227 10K_0402_5%

1 2

R228 10K_0402_5%

1 2

R229 10K_0402_5%@

1 2

R230 10K_0402_5%

1 2

R231 10K_0402_5%

1 2

R232 10K_0402_1%

1 2

R238 10K_0402_5%

1 2

R241 10K_04 02_5%<BOM Structure>

+3V_PCH

+3VS

1 2

1 2

R243 10K_0402_5%

1 2

R247 10K_0402_5%

1 2

R248 10K_0402_5%

1 2

R249 10K_0402_5%

R242

3

Function

Optimus

Reserve

DIS
(SLI)

Reserve

14"

@

12

GC6_EVENT#_R

R2340_0402_5%

PCH_GPIO1

PCH_GPIO6

EC_SCI#<45>

EC_SMI#<45>

@

ODD_EN<41>

@

12

R2240_0402_5%

10K_0402_5%

ODD_DETECT#<41>

SLAVE_PRESENT#<32>

EC_SCI#

EC_SMI#

PCH_GPIO12

EC_LID_OUT#

PCH_GPIO16

DGPU_PWROK

PCH_BT_DISABLE#

ODD_EN

DS3_WAKE#_R

PCH_GPIO28

PCH_BT_ON#

PCH_GPIO35

ODD_DETECT#

PCH_GPIO37

PCH_GPIO38

PCH_GPIO39

PCH_GPIO48

PCH_GPIO49

SLAVE_PRESENT#

15"

U4F

T7

BMBUSY# / GPIO0

A42

TACH1 / GPIO1

H36

TACH2 / GPIO6

E38

TACH3 / GPIO7

C10

GPIO8

C4

LAN_PHY_PWR_CTRL / GPIO12

G2

GPIO15

U2

SATA4GP / GPIO16

D40

TACH0 / GPIO17

T5

SCLOCK / GPIO22

E8

GPIO24

E16

GPIO27

P8

GPIO28

K1

STP_PCI# / GPIO34

K4

GPIO35

V8

SATA2GP / GPIO36

M5

SATA3GP / GPIO37

N2

SLOAD / GPIO38

M3

SDATAOUT0 / GPIO39

V13

SDATAOUT1 / GPIO48

V3

SATA5GP / GPIO49 / TEMP_ALERT#

D6

GPIO57

A4

VSS_NCTF_1

A44

VSS_NCTF_2

A45

VSS_NCTF_3

A46

VSS_NCTF_4

A5

VSS_NCTF_5

A6

VSS_NCTF_6

B3

VSS_NCTF_7

B47

VSS_NCTF_8

BD1

VSS_NCTF_9

BD49

VSS_NCTF_10

BE1

VSS_NCTF_11

BE49

VSS_NCTF_12

BF1

VSS_NCTF_13

BF49

VSS_NCTF_14

PANTHER-POINT_FCBGA989

PCH_GPIO38

0 0

0 1

1 0

1 1

X

X X

GPIO

NCTF

PCH_GPIO67

X

TACH4 / GPIO68

TACH5 / GPIO69

TACH6 / GPIO70

TACH7 / GPIO71

A20GATE

PECI

RCIN#

PROCPWRGD

THRMTRIP#

INIT3_3V#

DF_TVS

CPU/MISC

TS_VSS1

TS_VSS2

TS_VSS3

TS_VSS4

NC_1

VSS_NCTF_15

VSS_NCTF_16

VSS_NCTF_17

VSS_NCTF_18

VSS_NCTF_19

VSS_NCTF_20

VSS_NCTF_21

VSS_NCTF_22

VSS_NCTF_23

VSS_NCTF_24

VSS_NCTF_25

VSS_NCTF_26

VSS_NCTF_27

VSS_NCTF_28

VSS_NCTF_29

VSS_NCTF_30

VSS_NCTF_31

VSS_NCTF_32

PCH_GPIO70

C40

S_DGPU_PWROK

B41

S_DGPU_PWR_EN

C41

A40

S_NVDD_PWR_EN

P4

AU16

P5

KBRST#

AY11

AY10

PCH_THRMTRIP#_R

T14

AY1

NV_CLE

AH8

AK11

AH10

AK10

P37

BG2

BG48

BH3

BH47

BJ4

BJ44

BJ45

BJ46

BJ5

BJ6

C2

C48

D1

D49

E1

E49

F1

F49

X

X

X

X

0

1

PCH_GPIO70

2

S_DGPU_PWROK <32>

S_DGPU_PWR_EN <32,51>

9/18 Reseve for SKU ID

S_NVDD_PWR_EN <32>

1 2

R236 10K_0402_5%

KBRST# < 45>

1 2

R239 390_0402_5%

H_CPUPWRGD <6>

H_THRMTRIP#

INIT3_3V

This signal has weak internal
PU, can't pull low

Intel schematic reviwe recommand.

SKU ID

PCH_GPIO67<15>

S_DGPU_PWR_EN

S_NVDD_PWR_EN

+3VS

GATEA20 <45>

H_THRMTRIP# <6>

PCH_THRMTRIP#_R <23,32>

S_DGPU_PWROK

KBRST#

PCH_THRMTRIP#_R

PROC_SEL

NV_CLE

H : Sandy Bridge

L : IVY Bridge

1 2

R217 1K_0402_5%

CLOSE TO THE BRANCHING POINT

1

R711

PCH_GPIO38

PCH_GPIO67

PCH_GPIO70

R712

OPT@

1 2

R268 10K_0402_5%

1 2

R237 10K_0402_5%

1 2

R255 10K_0402_5%

1 2

R226 10K_0402_5%

1 2

R244 10K_0402_5%

+1.8VS

R708

SLI@

@

1 2

10K_0402_5%

R709

1 2

10K_0402_5%

R216

2.2K_0402_5%

H_SNB_IVB# <6>

+3VS

R704

1 2

10K_0402_5%

R706

1 2

10K_0402_5%

@

1 2

10K_0402_5%

1 2

10K_0402_5%

+3VS

+3VS

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

3

2011/11/01

2011/11/01

2011/11/01

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2012/12/31

2012/12/31

2012/12/31

Title

PCH (6/9) GPIO, CPU, MISC

PCH (6/9) GPIO, CPU, MISC

PCH (6/9) GPIO, CPU, MISC

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Monday, January 14, 2013

Monday, January 14, 2013

Monday, January 14, 2013

Y400S-NM-A141

Y400S-NM-A141

Y400S-NM-A141

1

of

of

of

19 65

19 65

19 65

1.0

1.0

1.0

5

4

3

2

1

+1.05VS

1

D D

+1.05VS

R254 R_short 0_0603_5%

C C

B B

+1.05VS

Del R296 for 14 '
l

ayout

+3VS

+1.05VS

2

This pin can be left as no connect in
On-Die VR enabled mode (default).

C221

10U_0603_6.3V6M

1

2

R260

1 2

R_short 0_0603_5%

R263

1 2

R_short 0_0603_5%

10U_0603_6.3V6M

C209

12

+1.05VS

1U_0402_6.3V6K

1

2

C222

+1.05VS

C210

1U_0402_6.3V6K

1

2

T47PAD @

C223

1U_0402_6.3V6K

1

2

1

C227

0.1U_0402_10V7K

2

T48PAD @

+VCCP_VCCDMI

C211

1U_0402_6.3V6K

1

1

2

2

+1.05VS_VCCDPLLEXP

+VCCAPLLEXP

C224

1U_0402_6.3V6K

1

2

+3VS_VCCA3GBG

+VCCAFDI_VRM

+1.05VS_VCCAPLL_FDI

+1.05VS_VCCDPLL_FDI

C212

1U_0402_6.3V6K

C225

1U_0402_6.3V6K

1

2

U4G

1700mA

AA23

VCCCORE[1]

AC23

VCCCORE[2]

AD21

VCCCORE[3]

AD23

VCCCORE[4]

AF21

VCCCORE[5]

AF23

VCCCORE[6]

AG21

VCCCORE[7]

AG23

VCCCORE[8]

AG24

VCCCORE[9]

AG26

VCCCORE[10]

AG27

VCCCORE[11]

AG29

VCCCORE[12]

AJ23

VCCCORE[13]

AJ26

VCCCORE[14]

AJ27

VCCCORE[15]

AJ29

VCCCORE[16]

AJ31

VCCCORE[17]

AN19

VCCIO[28]

BJ22

VCCAPLLEXP

AN16

VCCIO[15]

AN17

VCCIO[16]

AN21

VCCIO[17]

AN26

VCCIO[18]

AN27

VCCIO[19]

AP21

VCCIO[20]

AP23

VCCIO[21]

AP24

VCCIO[22]

AP26

VCCIO[23]

AT24

VCCIO[24]

AN33

VCCIO[25]

AN34

VCCIO[26]

BH29

VCC3_3[3]

AP16

VCCVRM[2]

BG6

VccAFDIPLL

AP17

VCCIO[27]

AU20

VCCDMI[2]

PANTHER-POINT_FCBGA989

POWER

3711mA

63mA

CRTLVDS

1

VCC CORE

40mA

DMI

70mA

VCCIO

190mA

DFT / SPI HVCMOS

FDI

VCCADAC

VSSADAC

mA

VCCALVDS

VSSALVDS

VCCTX_LVDS[1]

VCCTX_LVDS[2]

VCCTX_LVDS[3]

VCCTX_LVDS[4]

VCC3_3[6]

VCC3_3[7]

VCCVRM[3]

VCCDMI[1]

VCCCLKDMI

VCCDFTERM[1]

VCCDFTERM[2]

VCCDFTERM[3]

VCCDFTERM[4]

10mA

VCCSPI

U48

U47

AK36

AK37

AM37

AM38

AP36

AP37

V33

V34

AT16

AT20

AB36

AG16

AG17

AJ16

AJ17

V1

+VCCADAC

1

C213

0.01U_0402_16V7K

2

+VCCA_LVDS

+VCCTX_LVDS

1

C216

0.01U_0402_16V7K

2

+3VS_VCC3_3_6

+VCCAFDI_VRM

+VCCP_VCCDMI

+1.05VS_VCC_DMI_CCI

1

C226
1U_0402_6.3V6K

2

+VCCPNAND

1

C228

0.1U_0402_10V7K

2

+3V_VCCPSPI

1

C230
1U_0402_6.3V6K

2

1

C219

0.1U_0402_10V7K

2

1

C214

0.1U_0402_10V7K

2

1

C217

0.01U_0402_16V7K

2

R256

R_short 0_0603_5%

R300

R_short 0_0603_5%

R293

R_short 0_0603_5%

R399

R_short 0_0603_5%

L1 change to 1 ohm P/N

RES 1/10W 1 +-1% 0603

S

1

C215
10U_0603_6.3V6M

2

1

C218
22U_0805_6.3V6M

2

+3VS

12

+1.05VS

12

+1.8VS

12

+3VS

12

L1

12

1_0603_1%

R295

12

R_short 0_0603_5%

0.1UH_MLF1608DR10KT_10%_1608

L2

0.1uH inductor, 200mA

12

1

R_short 0_0603_5%

C220
1U_0402_6.3V6K

2

+1.8VS

R258

+3VS

+3VS

PCH Power Rail Table

efer to CPU EDS R1.5

R

5

5

.05

S0 Iccmax
Current (A)

0.001

0.001

0.001

0.228

0.063

0.08

0.08

1.7

0.047

Voltage Rail

V_PROC_IO

V5REF

V5REF_Sus

Vcc3_3

VccADAC

VccADPLLA

VccADPLLB

VccCore

VccDMI

Voltage

1.05

3.3

3.3

1

1.05

1.05

1.05

1.05VccIO 3.711

+1.05VS+VCCP_VCCDMI

12

1.05VccASW 0. 903

3.3VccSPI 0 .01

3.3VccDSW 0 .001

1.8 0.00 2VccDFTERM

3.3VccRTC 6 uA

3.3VccSus3_3

3.3 / 1.5VccSusHDA

0.095

0.01

VccVRM 1.8 / 1.5 0.167

VccSSC 1

1.05VccCLKDMI

.05 0.095

0.07

VccDIFFCLKN 1.05 0.055

VccALVDS 3.3

0.001

1.8VccTX_LVDS 0.04

+1.5VS +VCCAFDI_VRM

Intel reco mmand
stuff R265 and unstu ff R266

R265

12

R_short 0_0603_5%

+VCCAFDI_VRM

VCCVRM==>1.5V FOR MOBILE

CCVRM==>1.8V FOR DESKTOP

V

VCCVRM = 1 60mA detal waiting for newest spec

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUT URE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUT URE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUT URE CENTER.

3

2011/11/01

2011/11/01

2011/11/01

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2012/12/31

2012/12/31

2012/12/31

Title

PCH (7/9) PWR

PCH (7/9) PWR

PCH (7/9) PWR

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Monday, January 14, 2013

Monday, January 14, 2013

Monday, January 14, 2013

Y400S-NM-A141

Y400S-NM-A141

Y400S-NM-A141

1

of

of

of

20 65

20 65

20 65

1.0

1.0

1.0