COMPAL NM-A141 Schematic

A

1 1

B

C

D

E

QIQY5

Whisky3.0 (Y400S)

2 2

NM-A141 Rev0.2 Schematic

Intel IVY Bridge Processor with DDRIII + Panther Point PCH

3 3

4 4

A

nVIDIA N14P GT + 2nd VGA N14P GT

2012-10-25-Rev0.2

Security Class ification

Security Class ification

Security Class ification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2011/11/ 01

2011/11/ 01

2011/11/ 01

C

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2012/12/ 31

2012/12/ 31

2012/12/ 31

D

Title

Title

Title

COVER PAGE

COVER PAGE

COVER PAGE

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Monday, January 14, 2013

Monday, January 14, 2013

Monday, January 14, 2013

Y400S-NM-A141

Y400S-NM-A141

Y400S-NM-A141

E

1 65

1 65

1 65

of

of

of

1.0

1.0

1.0

A

B

C

D

E

PCI-Express 16X Gen3

EG 8~15

2nd VGA, N14P-GT1

1 1

Sub/B

VRAM 64*32

GDDR5* 8

Page 32 Page 23,24,25,26,27,28,29,30,31

VRAM 64*32

GDDR5* 8

PEG 0~7P

N14P-GT1

Intel CPU
Ivy Bridge

rPGA-989

37.5mm*37.5mm

age 5,6,7,8,9,10,11

P

Memory BUS (DDRIII)
Dual Channel

1.5V DDRIII 1066/1333/1600 MT/s

DDR3-SO-DIMM X2

BANK 0, 1, 2, 3

UP TO 16G

FDI *8

2.7GT/s

HDMI Conn.

Page 36 P

HDMI1.4b

2 2

RJ45 Conn.

Page 39

CRT Conn.

age 35 Page 34

Atheros
A

R8161 1G

AR8151 1G

PCIe port 1

LVDS Conn.

Page 38

PCIe Gen1 1x

1.5V 5GT/s

Intel PCH

anther Point

P

FCBGA-989 Balls
25mm*25mm

CardReader
JMB38C
SD/MMC/MS/XD

PCIe port 4

3 3

(4

Page 44

SPI ROM

MB+2MB)

Page 14

PCIe Gen1 1x

1.5V 5GT/s

SPI BUS

3.3V 33MHz

Page 14,15,16,17,18,19,20,21,22

LPC BUS

3.3V 33MHz

DMI *4
5GT/s

USB 2.0 4x
5V

480MHz

USB 3.0 2x

5V 5GT/s

USB 2.0 1x
5V 480MHz

PCIe Gen1 1x
5V 480MHz

SATA Gen3 Port 0
5V 6GHz(600MB/s)

SATA Gen3 Port 1
5V 6GHz(600MB/s)

SATA Gen1 Port2

3GHz(300MB/s)

5V

HD Audio

24MHz

3.3V

USB Left

USB 2.0 Port 2
USB 3.0 Port 2

Int. Camera

USB 3.0 Port 0

PCIeMini Card

AN

WL

PCIeMini Card
WLAN

SATA HDD

SATA ODD

USB Right

USB 2.0 Port 9

Page 48 Page 49

Page 34

USB 2.0 Port 5, Cha

Sub/B

BT

SB 2.0 Port 13

U

mSATA SSD

PCIe Port 2

page 37

USB Port 10

page 37

SATA Port 1

page 41

SATA Port 1

page 41

Page 47

SATA Port 0

page 37

Debug Port

Page 45

Power Circuit DC/DC

Page 52,53 ,54,55,56, 57,

58,59,60,6 1,62

4 4

DC/DC Interface CKT.

POWER/B Conn. AUDIO, USB/B Conn.

ODD/B Conn.

Page 51

Page 40 Page 49

page 41

A

RTC CKT.

NOVO/B Conn.

Page 52

Page 40

Touch Pad

Page 46

B

EC

E IT8580E-HX

IT

Page 45

Int.KBD

Page 46

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

C

Thermal Sensor

EMC 1403

Page 40

LC Future Center Secret Data

LC Future Center Secret Data

2011/11/01

2011/11/01

2011/11/01

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Codec

A

LC269Q-VC3

Int. MIC Conn.
(JCMOS Conn.)

Page 34 Page 49

2012/12/31

2012/12/31

2012/12/31

D

age 42

P

AMP

MA

X98400B

Page 43

Ext. MIC Conn.

Su

b/B

Title

Title

Title

BlOCK DIAGRAM

BlOCK DIAGRAM

BlOCK DIAGRAM

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Monday, January 14, 2013

Monday, January 14, 2013

Monday, January 14, 2013

HP Conn.

ub/B

S

Y400S-NM-A141

Y400S-NM-A141

Y400S-NM-A141

SPK Conn.

Page 49

E

Page 43

of

of

of

2 65

2 65

2 65

1.0

1.0

1.0

A

B

C

D

E

Voltage Rails

( O --> Means ON ,

Power Plane

1 1

B+

S

tate

S0

S

3

2 2

S5 S4/AC Only

S5 S4

Battery only

O

O

O

O

S5 S4
AC & Battery
don't exist

MBUS Control Table

S

SOURCE

3 3

IT

8580EEC_SMB_CK1

EC_SMB_DA1

EC_SMB_CK2

C_SMB_DA2

E

SMB_CLK_S3
S

MB_DATA_S3

+3VALW

IT8580E

+3VS

PCH

+3VS

X X

Main
V

GA

X

V

+3VS +3VS

X X

X --> Means OFF )

+5VS

+3VS

+1.5VS

+VCCSA

+V1.5S_VCC P

+3VALW

+1.5V

+5VALW

+CPU_CORE

+VGA_CORE

GFX_CORE

+

+1.8VS

+1.05VS

+0.75VS

+3.3VS_VGA

+1.5VS_VGA

+1.05VS_VG A

O O O

OO

O

X

X X

X

2nd
VGA

BATT SODIMM

IT8580E

X X

+3VALW

V

X

X

X X X

X

X

V V

+3VS

WLAN
WiMAX

X

X

V

X

X

X

X

Thermal
Sensor

V

+3VS

PCH

XV

V

+3V_PCH

+3V_PCH+3VS

IGNAL

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

S

USB Port Table

USB 3.0USB 2.0 Port

XHCI

EHCI1

EHCI2

TP

Mo

dule

XX

X

V

+3VS

SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

ON

HIGH HIGH HIGH HIGH

LOW

LOW

LOW

LOW LOW LOW LOW

0

1

1

2

2

3

3

4

4
5
6

USB Port (Left Side)

USB Port (Right Side)

7

8
9

USB Port (Right Side)

10

Mini Card(WLAN)

11
12
13

HIGH

LOWLOWLOW

4 External
USB Port

Camera

Blue Tooth

HIGHHIGHHIGH

HIGH

HIGH

ON

ON

ON

ON

ON

ON

OFF

ON

OFF

BOM Structure Table

HDMI@

CHG@

NOCHG@
CMOS@
8161@
8151@
8161S@
8151S@

SURGE@

61@
51@
X76@

GC6@

NOGC6@
AOAC@

KBL@
ME@

OPT@

PCIE PORT LIST

Port Device

1

LAN

2

WLAN

3
4

Card Reader

SLI@

DS3@

S3@

GT@

@

5
6
7
8

ON ON

ON

OFF

OFF

OFF

LOW

OFF

OFF

OFF

BTO ItemBOM Structure

HDMI part

USB charger part

No USB charger part

CMOS Camera part

AR8161 LAN part

AR8151 LAN part

AR8161 LAN surge part

A

R8151 LAN surge part

AR8151&8161 LAN surge part --> Delete (201200627)

X76 P/N for AR8161

X76 P/N for AR8151

X76 Level part for VRAM

NV CG6 support part

NV no CG6 support part
AOAC support part

K/B Light part

ME part

For optimus function part

For SLI function part

Deep S3 support part

For S3 function part

NV chip part

Unpop

A

Address

0001 011X b

EC SM Bus2 address

Device

Thermal Sen sor EMC1403-2

Master VGA

Slave VGA

B

Address

1001_101xb

0x9E

0x9C

PCH SM Bus address

Device Address

DDR DIMM0

DDR DIMM2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

C

1001 000Xb

1001 010Xb

2011/11/01

2011/11/01

2011/11/01

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

2012/12/31

2012/12/31

2012/12/31

4 4

EC SM Bus1 address

Device

Smart Battery

ZZZ1

DAZ00200100

Title

Title

Title

NOTES LIST

NOTES LIST

NOTES LIST

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Tuesday, March 12, 2013

Tuesday, March 12, 2013

Tuesday, March 12, 2013

Y400S-NM-A141

Y400S-NM-A141

Y400S-NM-A141

E

of

of

of

3 65

3 65

3 65

1.0

1.0

1.0

5

ot plug detect for IFP link E

H

VGA and GDDR5 Voltage Rails (N13Px GPIO)

GPIO I/O ACTIVE Function Description

PIO0

+3VS_VGA

+VGA_CORE

+1.5VS_VGA

+1.05VS_VGA

OUT FB_CLAMP-

OUT

-

OUT

OUT

OUT

OUT

OUT

OUT

I/O

OUT

OUT

VGA_BL_PWM

-

VGA_ENVDD

-

- V

GA_ENBKL

-

FB_CLAMP_TOGGLE_REQ#

-

-

-

OVERT#

-

VGA_ALERT#

-

Memory VREF Control

NVVDD PWM_VID-OUT

-

N

N/A

-

/A

-

-

VGA_AC_DET_R

DPRSLPVR_VGA-

dGPU_HDMI_HPD

tNVVDD >0

tFBVDDQ >0

tPEX_VDD >0

IN

OUT

OUT

IN

OUT

IN

IN

IN

1. all power ra il ramp up tim e should be la rger than 40us

(10K pull High)

G

D D

GPIO1

GPIO2

GPIO3

GPIO4

GPIO5

GPIO6

GPIO7

GPIO8

GPIO9

GPIO10

C C

GPIO11

GPIO12

GPIO13

GPIO14

GPIO15

GPIO16

GPIO17

GPIO18

GPIO19

B B

4

3

2

1

Performance Mode P0 TDP at Tj = 102 C* (GDDR5)

GPU Mem NVCLK
(4) (1,5) (6)

Products

(W) (W) (MHz)

N13X
128bit
1GB
GDDR5

Physical
Strapping pin

ROM_SCLK

ROM_SI

ROM_SO FB[0]

STRAP0

STRAP1

STRAP2

STRAP3

STRAP4

/MCLK NVVDD

(V) (A) (W) (A) (W)

TBD TBDTBD TBD TBD TBD TBD TBD T BD TBD TBD TBD TBD TBD TBD TBD TBD TBD

Power Rail

+3VS_VGA

+3VS_VGA

+

3VS_VGA

+3VS_VGA

+3VS_VGA

+3VS_VGA

+3VS_VGA

+3VS_VGA

Logical
Strapping Bit3

PCI_DEVID[4]

AM_CFG[3] RAM_C FG[2]

FB[1]

PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0]

SOR3_EXPOSED

RESERVED PCIE_SPEED_

Device ID

N13P-GT
(28nm)

0x0FDB

SMB_ALT_ADDR

(ROM_SO Bit 1)

FBVDD

Logical
Strapping Bit2

SUB_VENDOR

SER[2] USER[1] USER[0]USER[3]

U

3GIO_PAD_CFG_AD R[2] 3GIO_PAD_CFG_AD R[1]3GIO_PAD_CFG_AD R[3]

SOR2_EXPOSED SOR1_EXPOSED

CHANGE_GEN3

setting

0

1

ROM_SO

GPU

N13P-GT1
28nm

FB Memory (GDDR5)

Samsung
2500MHz

Hynix
2500MHz

Samsung
2500MHz

2500MHz

ROM_SCLK

PU 25K

PU 45KPU 10K PD 10K

PD 35K

PU 25K PD 35KPU 45KPU 20K PD 10K PD 5K PD 10K

GPU

N13P-GT

ROM_SI

K4G10325FG-HC04

32Mx32

PD 45K

H5GQ1H24BFR-T2C

32Mx32 PD 35K

K4G20325FD-FC04

64Mx32

PD 30K

H5GQ2H24MFR-T2CHynix

64Mx32

PD 25K

FBVDDQ PCI Express I/O and
(GPU+Mem)
(1.35V)(1.35V)

(A) (W) (W)(mA) (W) (W) (W)(mA) (mA) (mA)

(1.05V)

Logical
Strapping Bit1

SLOT_CLK_CFG

RAM_CFG[1]R

PCIE_MAX_SPEED DP_PLL_VDD33V

PLLVDD

I2C Slave addrees ID

0x9E

0x9C

STRAP2STRAP1STRAP0

STRAP3

STRAP4

PU 5K PD 10K

Master

Slave

I/O and
PLLVDD

Logical
Strapping Bit0

PEX_PLL_EN_TERM

R

AM_CFG[0]

VGA_DEVICESMB_ALT_ADDR

3GIO_PAD_CFG_AD R[0]

SOR0_EXPOSED

Other

(3.3V)(1.05V)(1.8V)

Other Power rail

A A

+3VS_VGA

power-off <10ms

T

1.all GPU power rails should be turned off within 10ms
. Optimus syste m VDD33 avoids drop down ear lier than NVDD and FBVDDQ

2

5

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2011/11/01

2011/11/01

2011/11/01

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2012/12/31

2012/12/31

2012/12/31

Title

VGA NOTES LIST

VGA NOTES LIST

VGA NOTES LIST

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Y400S-NM-A141

Y400S-NM-A141

Y400S-NM-A141

Monday, January 14, 2013

Monday, January 14, 2013

Monday, January 14, 2013

4 65

4 65

1

4 65

1.0

1.0

1.0

5

D D

DMI_CRX_PTX_N0<16 >
DMI_CRX_PTX_N1<16 >
DMI_CRX_PTX_N2<16 >
DMI_CRX_PTX_N3<16 >

DMI_CRX_PTX_P0<16>
DMI_CRX_PTX_P1<16>
DMI_CRX_PTX_P2<16>
DMI_CRX_PTX_P3<16>

DMI_CTX_PRX_N0<16 >
DMI_CTX_PRX_N1<16 >
DMI_CTX_PRX_N2<16 >
DMI_CTX_PRX_N3<16 >

DMI_CTX_PRX_P0<16>
DMI_CTX_PRX_P1<16>
DMI_CTX_PRX_P2<16>

C C

B B

DMI_CTX_PRX_P3<16>

FDI_CTX_PRX_N0<16>
FDI_CTX_PRX_N1<16>
FDI_CTX_PRX_N2<16>
FDI_CTX_PRX_N3<16>
FDI_CTX_PRX_N4<16>
FDI_CTX_PRX_N5<16>
FDI_CTX_PRX_N6<16>
FDI_CTX_PRX_N7<16>

FDI_CTX_PRX_P0<16>
FDI_CTX_PRX_P1<16>
FDI_CTX_PRX_P2<16>
FDI_CTX_PRX_P3<16>
FDI_CTX_PRX_P4<16>
FDI_CTX_PRX_P5<16>
FDI_CTX_PRX_P6<16>
FDI_CTX_PRX_P7<16>

FDI_FSYNC0<16>
FDI_FSYNC1<16>

FDI_INT<16>

FDI_LSYNC0<16>
FDI_LSYNC1<16>

+1.05VS

eDP_COMPIO and ICOMPO signals
should be short ed near balls
and routed with typical
impedance <25 m ohms

R7

1 2

24.9_0402_1%

4

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

FDI_FSYNC0
FDI_FSYNC1

FDI_INT

FDI_LSYNC0
FDI_LSYNC1

EDP_COMP

JCPU1A

ME@

B27

DMI_RX#[0]

B25

DMI_RX#[1]

A25

DMI_RX#[2]

B24

DMI_RX#[3]

B28

DMI_RX[0]

B26

DMI_RX[1]

A24

DMI_RX[2]

B23

DMI_RX[3]

G21

DMI_TX#[0]

E22

DMI_TX#[1]

F21

DMI_TX#[2]

D21

DMI_TX#[3]

G22

DMI_TX[0]

D22

DMI_TX[1]

F20

DMI_TX[2]

C21

DMI_TX[3]

A21

FDI0_TX#[0]

H19

FDI0_TX#[1]

E19

FDI0_TX#[2]

F18

FDI0_TX#[3]

B21

FDI1_TX#[0]

C20

FDI1_TX#[1]

D18

FDI1_TX#[2]

E17

FDI1_TX#[3]

A22

FDI0_TX[0]

G19

FDI0_TX[1]

E20

FDI0_TX[2]

G18

FDI0_TX[3]

B20

FDI1_TX[0]

C19

FDI1_TX[1]

D19

FDI1_TX[2]

F17

FDI1_TX[3]

J18

FDI0_FSYNC

J17

FDI1_FSYNC

H20

FDI_INT

J19

FDI0_LSYNC

H17

FDI1_LSYNC

A18

eDP_COMPIO

A17

eDP_ICOMPO

B16

eDP_HPD#

C15

eDP_AUX

D15

eDP_AUX#

C17

eDP_TX[0]

F16

eDP_TX[1]

C16

eDP_TX[2]

G15

eDP_TX[3]

C18

eDP_TX#[0]

E16

eDP_TX#[1]

D16

eDP_TX#[2]

F15

eDP_TX#[3]

TYCO_2013620-2_IVY BRIDGE

3

J22

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]

DMI

Intel(R) FDI

eDP

PEG_RX#[7]
PEG_RX#[8]

PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]

PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]

PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]

PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]

PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]

PCI EXPRESS* - GRAPHICS

PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]

PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]

PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]

J21
H22

K33

PCIE_CRX_GTX_N0

M35

PCIE_CRX_GTX_N1

L34

PCIE_CRX_GTX_N2

J35

PCIE_CRX_GTX_N3

J32

PCIE_CRX_GTX_N4

H34

PCIE_CRX_GTX_N5

H31

PCIE_CRX_GTX_N6

G33

PCIE_CRX_GTX_N7

G30

PCIE_CRX_GTX_N8

F35

PCIE_CRX_GTX_N9

E34

PCIE_CRX_GTX_N10

E32

PCIE_CRX_GTX_N11

D33

PCIE_CRX_GTX_N12

D31

PCIE_CRX_GTX_N13

B33

PCIE_CRX_GTX_N14

C32

PCIE_CRX_GTX_N15

J33

PCIE_CRX_GTX_P0

L35

PCIE_CRX_GTX_P1

K34

PCIE_CRX_GTX_P2

H35

PCIE_CRX_GTX_P3

H32

PCIE_CRX_GTX_P4

G34

PCIE_CRX_GTX_P5

G31

PCIE_CRX_GTX_P6

F33

PCIE_CRX_GTX_P7

F30

PCIE_CRX_GTX_P8

E35

PCIE_CRX_GTX_P9

E33

PCIE_CRX_GTX_P10

F32

PCIE_CRX_GTX_P11

D34

PCIE_CRX_GTX_P12

E31

PCIE_CRX_GTX_P13

C33

PCIE_CRX_GTX_P14

B32

PCIE_CRX_GTX_P15

M29

PCIE_CTX_GRX_C_N0

M32

PCIE_CTX_GRX_C_N1

M31

PCIE_CTX_GRX_C_N2

L32

PCIE_CTX_GRX_C_N3

L29

PCIE_CTX_GRX_C_N4

K31

PCIE_CTX_GRX_C_N5

K28

PCIE_CTX_GRX_C_N6

J30

PCIE_CTX_GRX_C_N7

J28

PCIE_CTX_GRX_C_N8

H29

PCIE_CTX_GRX_C_N9

G27

PCIE_CTX_GRX_C_N10

E29

PCIE_CTX_GRX_C_N11

F27

PCIE_CTX_GRX_C_N12

D28

PCIE_CTX_GRX_C_N13

F26

PCIE_CTX_GRX_C_N14

E25

PCIE_CTX_GRX_C_N15

M28

PCIE_CTX_GRX_C_P0

M33

PCIE_CTX_GRX_C_P1

M30

PCIE_CTX_GRX_C_P2

L31

PCIE_CTX_GRX_C_P3

L28

PCIE_CTX_GRX_C_P4

K30

PCIE_CTX_GRX_C_P5

K27

PCIE_CTX_GRX_C_P6

J29

PCIE_CTX_GRX_C_P7

J27

PCIE_CTX_GRX_C_P8

H28

PCIE_CTX_GRX_C_P9

G28

PCIE_CTX_GRX_C_P10

E28

PCIE_CTX_GRX_C_P11

F28

PCIE_CTX_GRX_C_P12

D27

PCIE_CTX_GRX_C_P13

E26

PCIE_CTX_GRX_C_P14

D25

PCIE_CTX_GRX_C_P15

PEG_COMP

+1.05VS

R1

12

24.9_0402_1%

PCIE_CRX_GTX_N[0..15] <23,32>

PCIE_CRX_GTX_P[0..15] <23,32>

C1 0.22U_0402_1 0V6K
C2 0.22U_0402_1 0V6K
C3 0.22U_0402_1 0V6K
C4 0.22U_0402_1 0V6K
C5 0.22U_0402_1 0V6K
C6 0.22U_0402_1 0V6K
C7 0.22U_0402_1 0V6K
C8 0.22U_0402_1 0V6K
C9 0.22U_0402_1 0V6KSLI@
C10 0.22U_0402_10V 6KSLI@
C11 0.22U_0402_10V 6KSLI@
C12 0.22U_0402_10V 6KSLI@
C13 0.22U_0402_10V 6KSLI@
C14 0.22U_0402_10V 6KSLI@
C15 0.22U_0402_10V 6KSLI@
C16 0.22U_0402_10V 6KSLI@

C20 0.22U_0402_10V 6K
C23 0.22U_0402_10V 6K
C25 0.22U_0402_10V 6K
C30 0.22U_0402_10V 6K
C18 0.22U_0402_10V 6K
C22 0.22U_0402_10V 6K
C28 0.22U_0402_10V 6K
C32 0.22U_0402_10V 6K
C19 0.22U_0402_10V 6KSLI@
C24 0.22U_0402_10V 6KSLI@
C29 0.22U_0402_10V 6KSLI@
C17 0.22U_0402_10V 6KSLI@
C21 0.22U_0402_10V 6KSLI@
C27 0.22U_0402_10V 6KSLI@
C26 0.22U_0402_10V 6KSLI@
C31 0.22U_0402_10V 6KSLI@

2

1. PEG_ICOMPI and RCOMPO signals should be shorted and routed with
a. max length = 500 mils
b. typical impedance = 43 mohms

2. PEG_ICOMPO signals should be routed with
a. max length = 500 mils
b. typical impedance = 14.5 mohms

PEG Static Lane Reversal - CFG2 is for the 16x

1: Normal Operation; Lane # definition matches
socket pin map definition

0

:Lane Reversed

*

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

CFG2

PCIE_CTX_GRX_N0
PCIE_CTX_GRX_N1
PCIE_CTX_GRX_N2
PCIE_CTX_GRX_N3
PCIE_CTX_GRX_N4
PCIE_CTX_GRX_N5
PCIE_CTX_GRX_N6
PCIE_CTX_GRX_N7
PCIE_CTX_GRX_N8
PCIE_CTX_GRX_N9
PCIE_CTX_GRX_N10
PCIE_CTX_GRX_N11
PCIE_CTX_GRX_N12
PCIE_CTX_GRX_N13
PCIE_CTX_GRX_N14
PCIE_CTX_GRX_N15

PCIE_CTX_GRX_P0
PCIE_CTX_GRX_P1
PCIE_CTX_GRX_P2
PCIE_CTX_GRX_P3
PCIE_CTX_GRX_P4
PCIE_CTX_GRX_P5
PCIE_CTX_GRX_P6
PCIE_CTX_GRX_P7
PCIE_CTX_GRX_P8
PCIE_CTX_GRX_P9
PCIE_CTX_GRX_P10
PCIE_CTX_GRX_P11
PCIE_CTX_GRX_P12
PCIE_CTX_GRX_P13
PCIE_CTX_GRX_P14
PCIE_CTX_GRX_P15

1

PCIE_CTX_GRX_N[0..15] < 23,32>

PCIE_CTX_GRX_P[0..15] <23,32>

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUT URE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUT URE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUT URE CENTER.

3

2011/11/01

2011/11/01

2011/11/01

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2012/12/31

2012/12/31

2012/12/31

Title

PROCESSOR(1/7) DMI,FDI,PEG

PROCESSOR(1/7) DMI,FDI,PEG

PROCESSOR(1/7) DMI,FDI,PEG

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Monday, January 14, 2013

Monday, January 14, 2013

Monday, January 14, 2013

Y400S-NM-A141

Y400S-NM-A141

Y400S-NM-A141

1

of

of

of

5 65

5 65

5 65

1.0

1.0

1.0

5

D D

ROC_SEL

H : Sandy Bridg e

P

L : IVY Bridge

+1.05VS

R9

1 2

62_0402_5%

C C

H_CPUPWRGD<19>

C550

100P_0402_50V8J

9/23 ESD Reques t

1

2

R27
10K_0402_5%

1 2

H_PROCHOT#<45,53>

H_PM_SYNC<16>

4

H_SNB_IVB#<19>

T14 PAD

H_PECI<45>

H_PROCHOT#H_PROCHOT#

H_THRMTRIP#<19>

H_PM_SYNC

H_CPUPWRGD

R15

1 2

56_0402_5%

R22

1 2

R_short 0_0402_5%

R26

1 2

R_short 0_0402_5%

R29

1 2

130_0402_5%

H_SNB_IVB#

H_CATERR#

H_PROCHOT#_R

H_THRMTRIP#

H_PM_SYNC_R

H_CPUPWRGD_R

PM_DRAM_PWR GD_RPM_SYS_PWRGD_BUF

BUF_CPU_RST#

H_PECI

JCPU1B

C26

AN34

AL33

AN33

AL32

AN32

AM34

AP33

V8

AR33

3

ME@

PROC_SELECT#

SKTOCC#

CATERR#

PECI

PROCHOT#

THERMTRIP#

PM_SYNC

UNCOREPWRGOOD

SM_DRAMPWR OK

RESET#

BCLK

BCLK#

MISCTHERMALPWR MANAGEMENT

DPLL_REF_CLK

DPLL_REF_CLK#

CLOCKS

SM_DRAMRST#

SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]

DDR3

MISC

PRDY#
PREQ#

TCK
TMS

TRST#

TDI

TDO

DBR#

BPM#[0]
BPM#[1]

JTAG & BPM

BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]

2

A28

CLK_CPU_DMI

A27

CLK_CPU_DMI#

A16
A15

R8

AK1
A5
A4

H_DRAMRST#

SM_RCOMP0
SM_RCOMP1
SM_RCOMP2

R12 1K_0402_5%
R13 1K_0402_5%

R16 140_0402_1%
R17 25.5_0402_1%
R18 200_0402_1%

DDR3 Compensation Signals

AP29
AP27

AR26
AR27
AP30

AR28
AP26

AL35

AT28
AR29
AR30
AT30
AP32
AR31
AT31
AR32

XDP_TCK
XDP_TMS
XDP_TRST#

XDP_TDI
XDP_TDO

XDP_TMS
XDP_TDI
XDP_TDO

XDP_TCK
XDP_TRST#

PU/PD for JTAG signals

CLK_CPU_DMI <15>
CLK_CPU_DMI# <15>

12
12

H_DRAMRST# <7>

12
12
12

R20 51_0402_5%
R21 51_0402_5%
R23 51_0402_5%

R24 51_0402_5%
R25 51_0402_5%

+1.05VS

12
12
12

@

12
12

1

+1.05VS

TYCO_2013620-2_IVY BRIDGE

B B

Buffered Reset to CPU

+3VS

1

5

P

B

O

A

G

U1
74AHC1G09GW_TSSOP5

3

4

C33

0.1U_0402_16V4Z

2

4

R338

10K_0402_5%

1 2

1 2

SYS_PWROK<16>

PM_DRAM_PWR GD<16>

A A

5

R65 0_0402_5%@

1

2

+1.5V_CPU_VDDQ+3VALW

12

R30
200_0402_5%

PM_SYS_PWRGD_BUF

1.05V

12

R35

@

0_0402_5%

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

3

2011/11/01

2011/11/01

2011/11/01

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

+1.05VS +3VS

12

R32

75_0402_5%

R34

1 2

43_0402_1%

BUFO_CPU_RST#BUF_CPU_RS T#

Deciphered Date

Deciphered Date

Deciphered Date

0.1U_0402_16V4Z

2

C34

4

2012/12/31

2012/12/31

2012/12/31

1

2

5

P

NC

Y

A

G

3

1

is is NC pin

Th

2

PLT_RST#

U2
SN74LVC1G07DCKR_SC70-5

Title

Title

Title

PROCESSOR(2/7) PM,XDP,CLK

PROCESSOR(2/7) PM,XDP,CLK

PROCESSOR(2/7) PM,XDP,CLK

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

3V

PLT_RST# <18,23,32,37,38,44,45>

Y400S-NM-A141

Y400S-NM-A141

Monday, January 14, 2013

Monday, January 14, 2013

Monday, January 14, 2013

Y400S-NM-A141

1

of

of

of

6 65

6 65

6 65

1.0

1.0

1.0

5

JCPU1C

ME@

4

3

JCPU1D

2

ME@

1

DDR_A_D[0..63]<12>

D D

C C

B B

DDR_A_BS0<12>
DDR_A_BS1<12>
DDR_A_BS2<12>

DDR_A_CAS#<12>
DDR_A_RAS#<12>
DDR_A_WE#<12>

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

AP11
AN11

AL12
AM12
AM11

AL11
AP12
AN12

AJ14
AH14

AL15
AK15

AL14
AK14

AJ15
AH15

AE10

AF10

G10

N10

M10

AG6
AG5
AK6
AK5
AH5
AH6

AK8

AK9
AH8
AH9
AL9
AL8

AE8
AD9
AF9

F10

AJ5
AJ6
AJ8

AJ9

C5
D5
D3
D2
D6
C6
C2
C3

F8

G9
F9
F7
G8
G7
K4
K5
K1
J1
J5
J4
J2
K2

M8

N8
N7

M9
N9
M7

V6

SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]

SA_BS[0]
SA_BS[1]
SA_BS[2]

SA_CAS#
SA_RAS#
SA_WE#

DDR SYSTEM MEMORY A

SA_CK[0]

SA_CLK#[0]

SA_CKE[0]

SA_CK[1]

SA_CLK#[1]

SA_CKE[1]

SA_CK[2]

SA_CLK#[2]

SA_CKE[2]

SA_CK[3]

SA_CLK#[3]

SA_CKE[3]

SA_CS#[0]
SA_CS#[1]
SA_CS#[2]
SA_CS#[3]

SA_ODT[0]
SA_ODT[1]
SA_ODT[2]
SA_ODT[3]

SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]

SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]

SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]

SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]

AB6
AA6
V9

AA5
AB5
V10

AB4
AA4
W9

AB3
AA3
W10

AK3
AL3
AG1
AH1

AH3
AG3
AG2
AH2

C4
G6
J3
M6
AL6
AM8
AR12
AM15

D4
F6
K3
N6
AL5
AM9
AR11
AM14

AD10
W1
W2
W7
V3
V2
W3
W6
V1
W5
AD8
V4
W4
AF8
V5
V7

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

M_CLK_DDR0 <12>
M_CLK_DDR#0 <12>
DDR_CKE0_DIMMA <12>

M_CLK_DDR1 <12>
M_CLK_DDR#1 <12>
DDR_CKE1_DIMMA <12>

DDR_CS0_DIMMA# <12>
DDR_CS1_DIMMA# <12>

M_ODT0 <12>
M_ODT1 <12>

DDR_A_DQS#[0..7] <12>

DDR_A_DQS[0..7] <12>

DDR_A_MA[0..15] <12> DDR_B_MA[0..15] <13>

DDR_B_D[0..63]<13>

DDR_B_BS0<13>
DDR_B_BS1<13>
DDR_B_BS2<13>

DDR_B_CAS#<13>
DDR_B_RAS#<13>
DDR_B_WE#<13>

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

D10

K10

AM5
AM6
AR3

AP3
AN3
AN2
AN1

AP2

AP5
AN9

AT5

AT6

AP6
AN8
AR6
AR5
AR9

AJ11

AT8

AT9

AH11

AR8

AJ12
AH12
AT11
AN14
AR14
AT14
AT12
AN15
AR15
AT15

AA9
AA7

AA10

AB8
AB9

J10

C9
A7

C8
A9
A8
D9
D8
G4
F4
F1
G1
G5
F5
F2
G2

J7
J8

K9

J9

K8
K7
M5
N4
N2
N1
M4
N5
M2
M1

R6

SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]

SB_BS[0]
SB_BS[1]
SB_BS[2]

SB_CAS#
SB_RAS#
SB_WE#

DDR SYSTEM MEMORY B

SB_CK[0]

SB_CLK#[0]

SB_CKE[0]

SB_CK[1]

SB_CLK#[1]

SB_CKE[1]

SB_CK[2]

SB_CLK#[2]

SB_CKE[2]

SB_CK[3]

SB_CLK#[3]

SB_CKE[3]

SB_CS#[0]
SB_CS#[1]
SB_CS#[2]
SB_CS#[3]

SB_ODT[0]
SB_ODT[1]
SB_ODT[2]
SB_ODT[3]

SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]

SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]

SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]

SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]

AE2
AD2
R9

AE1
AD1
R10

AB2
AA2
T9

AA1
AB1
T10

AD3
AE3
AD6
AE6

AE4
AD4
AD5
AE5

D7
F3
K6
N3
AN5
AP9
AK12
AP15

C7
G3
J6
M3
AN6
AP8
AK11
AP14

AA8
T7
R7
T6
T2
T4
T3
R2
T5
R3
AB7
R1
T1
AB10
R5
R4

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15

M_CLK_DDR2 <13>
M_CLK_DDR#2 <13>
DDR_CKE2_DIMMB <13>

M_CLK_DDR3 <13>
M_CLK_DDR#3 <13>
DDR_CKE3_DIMMB <13>

DDR_CS2_DIMMB# <13>
DDR_CS3_DIMMB# <13>

M_ODT2 <13>
M_ODT3 <13>

DDR_B_DQS#[0..7] <13>

DDR_B_DQS[0..7] <13>

TYCO_2013620-2_IVY BRIDGE

+1.5V

12

R37

1K_0402_5%

D

S

13

H_DRAMRST#<6>

R39

A A

DRAMRST_CNTRL_PC H<15>

DRAMRST_CNTRL<1 0>

DRAMRST_CNTRL_EC<45>

Reserve for Dee p S3

5

4.99K_0402_1%

1 2

@

R40 0_0402_5%

1 2

DS3@

R64 0_0402_5%

1 2

DRAMRST_CNTRL

DDR3_DRAMRST#_RH_DRAMRST#

Q2

G

BSS138_NL_SOT23-3

2

1

C35

0.047U_0402_16V4Z

2

Module design u sed 0.047u

4

R38

1 2

1K_0402_5%

DDR3_DRAMRST# <12,13>

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

3

2011/11/01

2011/11/01

2011/11/01

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

TYCO_2013620-2_IVY BRIDGE

2012/12/31

2012/12/31

2012/12/31

2

Title

Title

Title

PROCESSOR(3/7) DDRIII

PROCESSOR(3/7) DDRIII

PROCESSOR(3/7) DDRIII

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Monday, January 14, 2013

Monday, January 14, 2013

Monday, January 14, 2013

Y400S-NM-A141

Y400S-NM-A141

Y400S-NM-A141

1

of

of

of

7 65

7 65

7 65

1.0

1.0

1.0

5

D D

JCPU1E

ME@

AK28

CFG[0]

AK29

CFG[1]

CFG2

CFG5
CFG6
CFG7

C C

11/24 --> Intel recommend
t

o reserve test point

B B

T56 PAD
T57 PAD
T58 PAD
T59 PAD

AL26

CFG[2]

AL27

CFG[3]

AK26

CFG[4]

AL29

CFG[5]

AL30

CFG[6]

AM31

CFG[7]

AM32

CFG[8]

AM30

CFG[9]

AM28

CFG[10]

AM26

CFG[11]

AN28

CFG[12]

AN31

CFG[13]

AN26

CFG[14]

AM27

CFG[15]

AK31

CFG[16]

AN29

CFG[17]

AJ31

VAXG_VAL_SENSE

AH31

VSSAXG_VAL_SENSE

AJ33

VCC_VAL_SENSE

AH33

VSS_VAL_SENSE

AJ26

RSVD5

F25

RSVD8

F24

RSVD9

F23

RSVD10

D24

RSVD11

G25

RSVD12

G24

RSVD13

E23

RSVD14

D23

RSVD15

C30

RSVD16

A31

RSVD17

B30

RSVD18

B29

RSVD19

D30

RSVD20

B31

RSVD21

A30

RSVD22

C29

RSVD23

J20

RSVD24

B18

RSVD25

J15

RSVD27

CFG

4

VCC_DIE_SENSE

VSS

RSVD28
RSVD29
RSVD30
RSVD31

RSVD32

RSVD33
RSVD34
RSVD35

RSVD37
RSVD38
RSVD39
RSVD40

RSVD_NCTF1
RSVD_NCTF2
RSVD_NCTF3
RSVD_NCTF4
RSVD_NCTF5

RSVD_NCTF6
RSVD_NCTF7

RESERVED

RSVD_NCTF8
RSVD_NCTF9

RSVD_NCTF10

RSVD51
RSVD52

BCLK_ITP

BCLK_ITP#

RSVD_NCTF11
RSVD_NCTF12
RSVD_NCTF13

KEY

AH27
AH26

L7
AG7
AE7
AK2

W8

AT26
AM33
AJ27

T8
J16
H16
G16

AR35
AT34
AT33
AP35
AR34

B34
A33
A34
B35
C35

AJ32
AK32

AN35
AM35

AT2
AT1
AR1

B1

3

CFG Straps for Processor

CFG2

CFG6

CFG5

1K_0402_1%

CFG7

12

R41

@

1K_0402_1%

12

12

R44

R43

@

1K_0402_1%

12

R45

@

1K_0402_1%

PEG Static Lane Reversal - CFG2 is for the 16x

CFG2

Display Port Presence Strap

CFG4

PCIE Port Bifurcation Straps

CFG[6:5]

PEG DEFER TRAINING

CFG7

2

1: Normal Operation; Lane # definition matches

*

socket pin map definition

0:Lane Reversed

1 : Disabled; No Physical Display Port
attached to Embedded Display Port

*

0 : Enabled; An external Display Port device is
c

onnected to the Embedded Display Port

11: (Default) x16 - Device 1 functions 1 and 2 disabled

10: x8, x8 - Device 1 function 1 enabled ; function 2

*

disabled

01: Reserved - (Device 1 function 1 disabled ; function

2 enabled)

00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

: (Default) PEG Train immediately following xxRESETB

1
de assertion

0: PEG Wait for BIOS for training

1

TYCO_2013620-2_IVY BRIDGE

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

3

2011/11/01

2011/11/01

2011/11/01

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2012/12/31

2012/12/31

2012/12/31

Title

PROCESSOR(4/7) RSVD,CFG

PROCESSOR(4/7) RSVD,CFG

PROCESSOR(4/7) RSVD,CFG

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Monday, January 14, 2013

Monday, January 14, 2013

Monday, January 14, 2013

Y400S-NM-A141

Y400S-NM-A141

Y400S-NM-A141

1

of

of

of

8 65

8 65

8 65

1.0

1.0

1.0

5

4

3

2

1

JCPU1F

+VCC_CORE

D D

C C

B B

A A

5

C=94A

Q
DC=53A

AG35

VCC1

AG34

VCC2

AG33

VCC3

AG32

VCC4

AG31

VCC5

AG30

VCC6

AG29

VCC7

AG28

VCC8

AG27

VCC9

AG26

VCC10

AF35

VCC11

AF34

VCC12

AF33

VCC13

AF32

VCC14

AF31

VCC15

AF30

VCC16

AF29

VCC17

AF28

VCC18

AF27

VCC19

AF26

VCC20

AD35

VCC21

AD34

VCC22

AD33

VCC23

AD32

VCC24

AD31

VCC25

AD30

VCC26

AD29

VCC27

AD28

VCC28

AD27

VCC29

AD26

VCC30

AC35

VCC31

AC34

VCC32

AC33

VCC33

AC32

VCC34

AC31

VCC35

AC30

VCC36

AC29

VCC37

AC28

VCC38

AC27

VCC39

AC26

VCC40

AA35

VCC41

AA34

VCC42

AA33

VCC43

AA32

VCC44

AA31

VCC45

AA30

VCC46

AA29

VCC47

AA28

VCC48

AA27

VCC49

AA26

VCC50

Y35

VCC51

Y34

VCC52

Y33

VCC53

Y32

VCC54

Y31

VCC55

Y30

VCC56

Y29

VCC57

Y28

VCC58

Y27

VCC59

Y26

VCC60

V35

VCC61

V34

VCC62

V33

VCC63

V32

VCC64

V31

VCC65

V30

VCC66

V29

VCC67

V28

VCC68

V27

VCC69

V26

VCC70

U35

VCC71

U34

VCC72

U33

VCC73

U32

VCC74

U31

VCC75

U30

VCC76

U29

VCC77

U28

VCC78

U27

VCC79

U26

VCC80

R35

VCC81

R34

VCC82

R33

VCC83

R32

VCC84

R31

VCC85

R30

VCC86

R29

VCC87

R28

VCC88

R27

VCC89

R26

VCC90

P35

VCC91

P34

VCC92

P33

VCC93

P32

VCC94

P31

VCC95

P30

VCC96

P29

VCC97

P28

VCC98

P27

VCC99

P26

VCC100

TYCO_2013620-2_IVY BRIDGE

POWER

ME@

CORE SUPPLY

VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8

VCCIO9
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCCIO21
VCCIO22
VCCIO23
VCCIO24

VCCIO25
VCCIO26
VCCIO27
VCCIO28
VCCIO29
VCCIO30
VCCIO31

PEG AND DDR

VCCIO32
VCCIO33
VCCIO34
VCCIO35
VCCIO36
VCCIO37
VCCIO38
VCCIO39

VCCIO40

VIDALERT#

VIDSCLK
VIDSOUT

VCC_SENSE
VSS_SENSE

VCCIO_SENSE

VSS_SENSE_VCCIO

SENSE LINES SVID

4

+1.05VS

8.5A

AH13
AH10
AG10
AC10
Y10
U10
P10
L10
J14
J13
J12
J11
H14
H12
H11
G14
G13
G12
F14
F13
F12
F11
E14
E12

E11
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11

J23

Reserve 0.1u to avoid noise

AJ29
AJ30
AJ28

H_CPU_SVIDALRT#
H_CPU_SVIDCLK
H_CPU_SVIDDAT

1 2

R47 43_0402_5%

1 2

R48 R_short 0_0402_5%

1 2

R49 R_short 0_0402_5%

R50 130_0402_5%

12

Place the PU re sistor close t o CPU

AJ35

VCCSENSE_R VCCSENSE

AJ34

VSSSENSE_R

B10

VCCIO_SENSE

A10

VSSIO_SENSE

1 2

R52 R_short 0_0402_5%

1 2

R53 R_short 0_0402_5%

R1294 10_0402_1%

R1297 10_0402_1%

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

3

+1.05VS

12

12

0.1U_0402_10V7K

+1.05VS

2011/11/01

2011/11/01

2011/11/01

+1.05VS

1

C36

@

2

+VCC_CORE

VSSSENSE

VCCIO_SENSE <57>

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

12

R46
75_0402_5%

Place the PU re sistor close t o CPU

VR_SVID_ALRT# <59>
VR_SVID_CLK <59>
VR_SVID_DAT <59>

12

R51
100_0402_1%

V

CC_SENCE 100ohm +-1% pull-up to VCC near pr ocessor

VCCSENSE <59>

12

R54

100_0402_1%

VSSSENSE <59>

VSS_SENCE 100oh m +-1% pull-do wn to GND near processor

2012/12/31

2012/12/31

2012/12/31

2

Title

Title

Title

PROCESSOR(5/7) PWR,BYPASS

PROCESSOR(5/7) PWR,BYPASS

PROCESSOR(5/7) PWR,BYPASS

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Monday, January 14, 2013

Monday, January 14, 2013

Monday, January 14, 2013

Y400S-NM-A141

Y400S-NM-A141

Y400S-NM-A141

1

of

of

of

9 65

9 65

9 65

1.0

1.0

1.0

5

4

3

2

1

+1.5V_CPU_VDDQ

For Deep S3

D D

R1538

SUSP<37,51,55,57>

CPU1.5V_S3_GATE<45>

C C

B B

1 2

R_short 0_0402_5%

0_0402_5%

+3VALW

12

R1537

100K_0402_5%

+VCC_GFXCORE_AXG

@

13

D

2

G

S

4

RV174

SLI@

1 2

@

Q156
2N7002_SOT23

6A

+VSB

12

R56 need to che ck on SDV

R56
100K_0402_5%

61

D

2

G

S

Q4A
2N7002KDWH_SOT363-6

JCPU1G

AT24

VAXG1

AT23

VAXG2

AT21

VAXG3

AT20

VAXG4

AT18

VAXG5

AT17

VAXG6

AR24

VAXG7

AR23

VAXG8

AR21

VAXG9

AR20

VAXG10

AR18

VAXG11

AR17

VAXG12

AP24

VAXG13

AP23

VAXG14

AP21

VAXG15

AP20

VAXG16

AP18

VAXG17

AP17

VAXG18

AN24

VAXG19

AN23

VAXG20

AN21

VAXG21

AN20

VAXG22

AN18

VAXG23

AN17

VAXG24

AM24

VAXG25

AM23

VAXG26

AM21

VAXG27

AM20

VAXG28

AM18

VAXG29

AM17

VAXG30

AL24

VAXG31

AL23

VAXG32

AL21

VAXG33

AL20

VAXG34

AL18

VAXG35

AL17

VAXG36

AK24

VAXG37

AK23

VAXG38

AK21

VAXG39

AK20

VAXG40

AK18

VAXG41

AK17

VAXG42

AJ24

VAXG43

AJ23

VAXG44

AJ21

VAXG45

AJ20

VAXG46

AJ18

VAXG47

AJ17

VAXG48

AH24

VAXG49

AH23

VAXG50

AH21

VAXG51

AH20

VAXG52

AH18

VAXG53

AH17

VAXG54

RUN_ON_CPU1.5VS3

POWER

GRAPHICS

+1.5V

1 2

470K_0402_5%

12

R57
470K_0402_5%

VAXG_SENSE

VSSAXG_SENSE

SENSE

LINES

SM_VREF

SA_DIMM_VREFDQ
SB_DIMM_VREFDQ

VREFMISC

DDR3 -1.5V RAILS

1 2

C287 0.1U_0402_10V 6K

1 2

C286 0.1U_0402_10V 6K

1 2

C96 0.1U_0402_10V 6K

1 2

C95 0.1U_0402_10V 6K

U3

8
7
6
5

AO4304L_SO8

R1349

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8

VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15

VCCSA1
VCCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6
VCCSA7
VCCSA8

4

A
Vgs=10V,Id=18A,
Rds<6.7m ohm
P/N: SB00000RV0 0

1

C97

0.01U 50V K X7R 0603

2

AK35

VCC_AXG_SENSE_R

AK34

VSS_AXG_SENSE_R

AL1

+V_SM_VREF_CNT

B4

+V_DDR_REFA_R

D1

+V_DDR_REFB_R

5A

AF7
AF4
AF1
AC7
AC4
AC1
Y7
Y4
Y1
U7
U4
U1
P7
P4
P1

6A

M27
M26
L26
J26
J25
J24
H26
H25

O4304L

1
2
3

+1.5V_CPU_VDDQ

12

R1487

@

470_0603_5%

34

D

S

Q4B
2N7002KDWH_SOT363-6

1 2

R1488 0_0402_5%OPT@

1 2

R1489 0_0402_5%

10U_0603_6.3V6M

10U_0603_6.3V6M

C118

C117

1

1

2

+VCCSA

10U_0805_6.3V6M

1

2

1

2

2

10U_0805_6.3V6M

C124

C125

1

1

2

2

5

G

OPT@

1

C114

0.1U_0402_16V4Z

2

10U_0603_6.3V6M

10U_0603_6.3V6M

C119

1

2

10U_0805_6.3V6M

C126

1

@

2

SUSP

C120

10U_0805_6.3V6M

DRAMRST_CNTRL<7>

+VREF_DQ_DIMMA
+VREF_DQ_DIMMB

6/8: Add M3 Circuit (Processor Generated SO-DIMM VREF

VCC_AXG_SENSE

VSS_AXG_SENSE

VCC_AXG_SENSE <59>
VSS_AXG_SENSE <59>

+1.5V_CPU_VDDQ

10U_0603_6.3V6M

10U_0603_6.3V6M

C122

C121

1

1

2

2

C127

+VCCSA

@

1

+

@

2

330U_D2_2.5VY_R9M

C128

1

+

2

R66 100_0402_1%

R90 100_0402_1%

330U_D2_2.5VY_R9M

C123

DRAMRST_CNTRL

DRAMRST_CNTRL

OPT@

12

OPT@

12

+1.5V_CPU_VDDQ

12

R77
1K_0402_1%

12

R88
1K_0402_1%

2

G

Q8 BSS138_SOT23

1 3

D

S

1 2

R74 0_0402_5%@

1 2

R75 0_0402_5%@

1 3

D

Q7 BSS138_SOT23

2

S

G

R139

1K_0402_1%

@

12

+V_DDR_REFA_R
+V_DDR_REFB_R

12

R132

@

1K_0402_1%

_DQ)

+VCC_GFXCORE_AXG

Place the PU/PD resi stor clos e to CPU w ithin 2 i nch
(R

eserve pow er side)

SA RAIL

VCCIO_SEL

H23

C22
C24

A19

+1.8VS

R67

1 2

A A

R_short 0_0805_5%

10U_0805_6.3V6M

1

+

C130

C279

@

2

330U_B2_2.5VM_R15M

1

1

C131

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

C132

+1.8VS_VCCPLL

1

2

11/24 change 22 U X2 to 330U B 2 size

5

B6

VCCPLL1

A6

VCCPLL2

A2

VCCPLL3

TYCO_2013620-2_IVY BRIDGE

ME@

4

1.8V RAIL

VCCSA_SENSE

VCCSA_VID[0]
VCCSA_VID[1]

+VCCSA_SENSE <56>

H_VCCSA_VID0 <56>
H_VCCSA_VID1 <56>

6/3 modify for VCCSA 4-Level voltage

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

3

+VCCSA_SENSE

2011/11/01

2011/11/01

2011/11/01

1 2

R68 0_0402_5%@

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2012/12/31

2012/12/31

2012/12/31

Title

Title

Title

PROCESSOR(6/7) PWR

PROCESSOR(6/7) PWR

PROCESSOR(6/7) PWR

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Monday, January 14, 2013

Monday, January 14, 2013

Monday, January 14, 2013

Y400S-NM-A141

Y400S-NM-A141

Y400S-NM-A141

1

of

of

of

10 65

10 65

10 65

1.0

1.0

1.0

5

4

3

2

1

D D

C C

B B

AT35
AT32
AT29
AT27
AT25
AT22
AT19
AT16
AT13
AT10

AR25
AR22
AR19
AR16
AR13
AR10

AR7
AR4

AR2
AP34
AP31
AP28
AP25
AP22
AP19
AP16
AP13
AP10

AP7

AP4

AP1

AN30
AN27
AN25
AN22
AN19
AN16
AN13
AN10

AN7

AN4

AM29
AM25
AM22
AM19
AM16
AM13
AM10

AM7

AM4

AM3

AM2

AM1
AL34
AL31
AL28
AL25
AL22
AL19
AL16
AL13
AL10

AK33
AK30
AK27
AK25
AK22
AK19
AK16
AK13
AK10

AK7

AK4
AJ25

JCPU1H

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10

AT7

VSS11

AT4

VSS12

AT3

VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65

AL7

VSS66

AL4

VSS67

AL2

VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80

VSS

VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS98

VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160

AJ22
AJ19
AJ16
AJ13
AJ10
AJ7
AJ4
AJ3
AJ2
AJ1
AH35
AH34
AH32
AH30
AH29
AH28
AH25
AH22
AH19
AH16
AH7
AH4
AG9
AG8
AG4
AF6
AF5
AF3
AF2
AE35
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2

M34

H33
H30
H27
H24
H21
H18
H15
H13
H10

G35
G32
G29
G26
G23
G20
G17
G11

JCPU1I

T35

VSS161

T34

VSS162

T33

VSS163

T32

VSS164

T31

VSS165

T30

VSS166

T29

VSS167

T28

VSS168

T27

VSS169

T26

VSS170

P9

VSS171

P8

VSS172

P6

VSS173

P5

VSS174

P3

VSS175

P2

VSS176

N35

VSS177

N34

VSS178

N33

VSS179

N32

VSS180

N31

VSS181

N30

VSS182

N29

VSS183

N28

VSS184

N27

VSS185

N26

VSS186
VSS187

L33

VSS188

L30

VSS189

L27

VSS190

L9

VSS191

L8

VSS192

L6

VSS193

L5

VSS194

L4

VSS195

L3

VSS196

L2

VSS197

L1

VSS198

K35

VSS199

K32

VSS200

K29

VSS201

K26

VSS202

J34

VSS203

J31

VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213

H9

VSS214

H8

VSS215

H7

VSS216

H6

VSS217

H5

VSS218

H4

VSS219

H3

VSS220

H2

VSS221

H1

VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230

F34

VSS231

F31

VSS232

F29

VSS233

VSS

VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285

F22
F19
E30
E27
E24
E21
E18
E15
E13
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
D35
D32
D29
D26
D20
D17
C34
C31
C28
C27
C25
C23
C10
C1
B22
B19
B17
B15
B13
B11
B9
B8
B7
B5
B3
B2
A35
A32
A29
A26
A23
A20
A3

TYCO_2013620-2_IVY BRIDGE

ME@

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

3

2011/11/01

2011/11/01

2011/11/01

TYCO_2013620-2_IVY BRIDGE

ME@

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2012/12/31

2012/12/31

2012/12/31

Title

Title

Title

PROCESSOR(7/7) VSS

PROCESSOR(7/7) VSS

PROCESSOR(7/7) VSS

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Monday, January 14, 2013

Monday, January 14, 2013

Monday, January 14, 2013

Y400S-NM-A141

Y400S-NM-A141

Y400S-NM-A141

1

of

of

of

11 65

11 65

11 65

1.0

1.0

1.0

5

4

3

2

1

DDR3 SO-DIMM A

VSS3

DQS0
VSS6

VSS8
DQ12
DQ13

DQ14
DQ15

DQ20
DQ21

DQ22
DQ23

DQ28
DQ29

DQS3

DQ30
DQ31

CKE1
VDD2

VDD4

VDD6

VDD8

CK1#

RAS#

ODT0

ODT1

DQ36
DQ37

DQ38
DQ39

DQ44
DQ45

DQS5

DQ46
DQ47

DQ52
DQ53

DQ54
DQ55

DQ60
DQ61

DQS7

DQ62
DQ63

VTT2

+1.5V+1.5V

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

206

DDR_A_D4
DDR_A_D5

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D6
DDR_A_D7

DDR_A_D12
DDR_A_D13

DDR3_DRAMRST#

DDR_A_D14
DDR_A_D15

DDR_A_D20
DDR_A_D21

DDR_A_D22
DDR_A_D23

DDR_A_D28
DDR_A_D29

DDR_A_DQS#3
DDR_A_DQS3

DDR_A_D30
DDR_A_D31

DDR_CKE1_DIMMA

DDR_A_MA15
DDR_A_MA14

DDR_A_MA11
DDR_A_MA7

DDR_A_MA6
DDR_A_MA4

DDR_A_MA2
DDR_A_MA0

M_CLK_DDR1
M_CLK_DDR#1

DDR_A_BS1
DDR_A_RAS#

DDR_CS0_DIMMA#

M_ODT1

DDR_A_D36
DDR_A_D37

DDR_A_D38
DDR_A_D39

DDR_A_D44
DDR_A_D45

DDR_A_DQS#5
DDR_A_DQS5

DDR_A_D46
DDR_A_D47

DDR_A_D52
DDR_A_D53

DDR_A_D54
DDR_A_D55

DDR_A_D60
DDR_A_D61

DDR_A_DQS#7
DDR_A_DQS7

DDR_A_D62
DDR_A_D63

SMB_DATA_S3
SMB_CLK_S3

0.65A@0.75V

0.65A@0.75V

0.65A@0.75V0.65A@0.75V

DQ4
DQ5

DQ6
DQ7

DM1

DM2

A15
A14

A11

A7

A6
A4

A2
A0

CK1

BA1

S0#

NC2

DM4

DM6

SDA
SCL

G2

4

For RF request

0.047U_0402_16V4Z

1

C51

@

2

DDR3_DRAMRST# <13,7>

DDR_CKE1_DIMMA <7>

M_CLK_DDR1 <7>
M_CLK_DDR#1 <7>

DDR_A_BS1 <7>
DDR_A_RAS# <7>

DDR_CS0_DIMMA# <7>
M_ODT0 <7>

M_ODT1 <7>

0.1U_0402_10V6K

1

C149

C150

2

SMB_DATA_S3 <13,15,37,46>
SMB_CLK_S3 <13,15,37,46>

+0.75VS

0.047U_0402_16V4Z

1

C52

@

2

0.047U_0402_16V4Z

1

C53

@

2

Layout Note:
Place near DIMM

DDR_A_D[0..63] <7>

DDR_A_DQS[0..7] <7>

DDR_A_DQS#[0..7] <7>

DDR_A_MA[0..15] <7>

OSCON (220uF_6.3V_4.2L_ESR17m)*1=(SF000002Y00)
(10uF_0603_6.3V)*8
(0.1uF_402_10V)*4

+1.5V +1.5V

12

R80
1K_0402_1%

+VREF_CA

2.2U_0603_6.3V6K

1

2

12

R81
1K_0402_1%

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

10U_0603_6.3V6M

1

C151

C142

@

@

2

Layout Note:
Place near DIMM

+0.75VS

1U_0402_6.3V6K

1

C288

1

C158

2

2

10U_0603_6.3V6M

1

2

1U_0402_6.3V6K

C143

1

C159

2

2011/11/01

2011/11/01

2011/11/01

10U_0603_6.3V6M

1

2

1U_0402_6.3V6K

10U_0603_6.3V6M

1

C144

C152

2

1U_0402_6.3V6K

1

C160

2

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

10U_0603_6.3V6M

10U_0603_6.3V6M

1

1

C145

2

1

C153

2

2

Layout Note:
Place near DIMM

DDR_A_DM[0:7] connect to GND

2012/12/31

2012/12/31

2012/12/31

2

10U_0603_6.3V6M

10U_0603_6.3V6M

1

C146

2

0.1U_0402_10V6K

0.1U_0402_10V6K

1

1

C154

C155

2

Title

Title

Title

DDRIII-SODIMM SLOT1

DDRIII-SODIMM SLOT1

DDRIII-SODIMM SLOT1

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

C147

2

2

Monday, January 14, 2013

Monday, January 14, 2013

Monday, January 14, 2013

0.1U_0402_10V6K

0.1U_0402_10V6K

1

C156

2

Y400S-NM-A141

Y400S-NM-A141

Y400S-NM-A141

1

1

+

C148
220U_6.3V_M

2

12 65

12 65

12 65

1.0

1.0

1.0

+1.5V

12

R78

1K_0402_1%

+VREF_DQ_DIMMA

D D

C C

B B

A A

1K_0402_1%

12

R79

+3VS

2.2U_0603_6.3V6K

C141

DDR_CKE0_DIMMA<7>

DDR_A_BS2<7>

M_CLK_DDR0<7>
M_CLK_DDR#0<7>

DDR_A_BS0<7>

DDR_A_WE#<7>
DDR_A_CAS#<7>

DDR_CS1_DIMMA#<7>

5

C290

1

2

C140

2.2U_0603_6.3V6K

1

2

+VREF_DQ_DIMMA

1

2

0.1U_0402_10V6K

1

C162

0.1U_0402_10V6K

2

3A@1.5V

DDR_A_D0
DDR_A_D1

DDR_A_D2
DDR_A_D3

DDR_A_D8
DDR_A_D9

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D10
DDR_A_D11

DDR_A_D16
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18
DDR_A_D19

DDR_A_D24
DDR_A_D25

DDR_A_D26
DDR_A_D27

DDR_CKE0_DIMMA

DDR_A_BS2

DDR_A_MA12
DDR_A_MA9

DDR_A_MA8
DDR_A_MA5

DDR_A_MA3
DDR_A_MA1

M_CLK_DDR0
M_CLK_DDR#0

DDR_A_MA10
DDR_A_BS0

DDR_A_WE#
DDR_A_CAS# M_ODT0

DDR_A_MA13
DDR_CS1_DIMMA#

DDR_A_D32
DDR_A_D33

DDR_A_DQS#4
DDR_A_DQS4

DDR_A_D34
DDR_A_D35

DDR_A_D40
DDR_A_D41

DDR_A_D42
DDR_A_D43

DDR_A_D48
DDR_A_D49

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D50
DDR_A_D51

DDR_A_D56
DDR_A_D57

DDR_A_D58
DDR_A_D59

R82

1 2

10K_0402_5%

12

R83
10K_0402_5%

JDIMM1

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1
DQS129RESET#
VSS1131VSS12

33

DQ10

35

DQ11
VSS1337VSS14

39

DQ16

41

DQ17
VSS1543VSS16

45

DQS#2
DQS247VSS17

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25
VSS2261DQS#3

63

DM3
VSS2365VSS24

67

DQ26

69

DQ27
VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1
VDD999VDD10

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

LCN_DAN06-K4806-0103

E

@

M

DQS#0

VSS10

VSS19

VSS21

VDD12

VDD14

VDD16

VDD18

VREF_CA

VSS28

VSS30

VSS31

VSS33

VSS35
DQS#5

VSS38

VSS40

VSS42

VSS43

VSS45

VSS47
DQS#7

VSS50

VSS52

EVENT#

5

+1.5V

12

R84

1K_0402_1%

+VREF_DQ_DIMMB

12

C289

D D

C C

B B

A A

1K_0402_1%

R85

2.2U_0603_6.3V6K

+3VS

DDR_CKE2_DIMMB<7>

DDR_B_BS2<7>

M_CLK_DDR2<7>
M_CLK_DDR#2<7>

DDR_B_BS0<7>

DDR_B_WE#<7>
DDR_B_CAS#<7>

DDR_CS3_DIMMB#<7>

5

1

2

C177

C157

2.2U_0603_6.3V6K

+VREF_DQ_DIMMB

1

2

0.1U_0402_10V6K

1

1

2

2

R97 10K_0402_5%

C178

0.1U_0402_10V6K

DDR_B_D0
DDR_B_D1

DDR_B_D2
DDR_B_D3

DDR_B_D8
DDR_B_D9

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D11

DDR_B_D16
DDR_B_D17

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D18
DDR_B_D19

DDR_B_D24
DDR_B_D25

DDR_B_D26
DDR_B_D27

DDR_CKE2_DIMMB

DDR_B_BS2

DDR_B_MA12
DDR_B_MA9

DDR_B_MA8
DDR_B_MA5

DDR_B_MA3
DDR_B_MA1

M_CLK_DDR2
M_CLK_DDR#2

DDR_B_MA10
DDR_B_BS0

DDR_B_WE#
DDR_B_CAS#

DDR_B_MA13
DDR_CS3_DIMMB#

DDR_B_D32
DDR_B_D33

DDR_B_DQS#4
DDR_B_DQS4

DDR_B_D34
DDR_B_D35

DDR_B_D40
DDR_B_D41

DDR_B_D42
DDR_B_D43

DDR_B_D48
DDR_B_D49

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D50
DDR_B_D51

DDR_B_D56
DDR_B_D57

DDR_B_D58
DDR_B_D59

R95

1 2

10K_0402_5%

1 2

DDR3 SO-DIMM B

3A@1.5V

JDIMM2

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1
VSS49DQS#0

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9
VSS925VSS10

27

DQS#1
DQS129RESET#
VSS1131VSS12

33

DQ10

35

DQ11
VSS1337VSS14

39

DQ16

41

DQ17
VSS1543VSS16

45

DQS#2
DQS247VSS17

49

VSS18

51

DQ18
DQ1953VSS19

55

VSS20

57

DQ24
DQ2559VSS21
VSS2261DQS#3

63

DM3
VSS2365VSS24

67

DQ26

69

DQ27
VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1
VDD999VDD10

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

TYCO_2-2013287-1

ME@

DQ4
DQ5

VSS3

DQS0
VSS6

DQ6

DQ7
VSS8
DQ12
DQ13

DM1

DQ14
DQ15

DQ20
DQ21

DM2

DQ22
DQ23

DQ28
DQ29

DQS3

DQ30
DQ31

CKE1
VDD2

VDD4

VDD6

VDD8

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

NC2

VDD18

VREF_CA

VSS28

DQ36
DQ37

VSS30

DM4

VSS31

DQ38
DQ39

VSS33

DQ44
DQ45

VSS35
DQS#5

DQS5

VSS38

DQ46
DQ47

VSS40

DQ52
DQ53

VSS42

DM6

VSS43

DQ54
DQ55

VSS45

DQ60
DQ61

VSS47
DQS#7

DQS7

VSS50

DQ62
DQ63

VSS52

EVENT#

SDA

VTT2

4

+1.5V+1.5V

2
4

DDR_B_D4

6

DDR_B_D5

8
10

DDR_B_DQS#0

12

DDR_B_DQS0

14
16

DDR_B_D6

18

DDR_B_D7

20
22

DDR_B_D12

24

DDR_B_D13

26
28
30

DDR3_DRAMRST#

32
34

DDR_B_D14

36

DDR_B_D15

38
40

DDR_B_D20

42

DDR_B_D21

44
46
48
50

DDR_B_D22

52

DDR_B_D23

54
56

DDR_B_D28

58

DDR_B_D29

60
62

DDR_B_DQS#3

64

DDR_B_DQS3

66
68

DDR_B_D30

70

DDR_B_D31

72

74

DDR_CKE3_DIMMB

76
78

A15
A14

A11

A7

A6
A4

A2
A0

CK1

BA1

S0#

SCL

G2

DDR_B_MA15

80

DDR_B_MA14

82
84

DDR_B_MA11

86

DDR_B_MA7

88
90

DDR_B_MA6

92

DDR_B_MA4

94
96

DDR_B_MA2

98

DDR_B_MA0

100
102

M_CLK_DDR3

104

M_CLK_DDR#3

106
108

DDR_B_BS1

110

DDR_B_RAS#

112
114

DDR_CS2_DIMMB#

116

M_ODT2

118
120

M_ODT3

122
124
126
128
130

DDR_B_D36

132

DDR_B_D37

134
136
138
140

DDR_B_D38

142

DDR_B_D39

144
146

DDR_B_D44

148

DDR_B_D45

150
152

DDR_B_DQS#5

154

DDR_B_DQS5

156
158

DDR_B_D46

160

DDR_B_D47

162
164

DDR_B_D52

166

DDR_B_D53

168
170
172
174

DDR_B_D54

176

DDR_B_D55

178
180

DDR_B_D60

182

DDR_B_D61

184
186

DDR_B_DQS#7

188

DDR_B_DQS7

190
192

DDR_B_D62

194

DDR_B_D63

196
198
200

SMB_DATA_S3

202

SMB_CLK_S3

204

206

4

0.65A@0.75V

0.65A@0.75V

0.65A@0.75V0.65A@0.75V

For RF request

0.047U_0402_16V4Z

1

C54

@

2

DDR3_DRAMRST# <12,7>

DDR_CKE3_DIMMB <7>

M_CLK_DDR3 <7>
M_CLK_DDR#3 <7>

DDR_B_BS1 <7>
DDR_B_RAS# <7>

DDR_CS2_DIMMB# <7>
M_ODT2 <7>

M_ODT3 <7>

0.1U_0402_10V6K

1

C280

C281

2

SMB_DATA_S3 <12,15,37,46>
SMB_CLK_S3 <12,15,37,46>

+0.75VS

0.047U_0402_16V4Z

1

C55

@

2

+VREF_CB

2.2U_0603_6.3V6K

1

2

3

0.047U_0402_16V4Z

1

C56

@

2

Layout Note:
Place near DIMM

+1.5V

12

R86
1K_0402_1%

12

R87
1K_0402_1%

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

+1.5V

10U_0603_6.3V6M

1

C282

C161

@

@

2

Layout Note:
Place near DIMM

+0.75VS

1U_0402_6.3V6K

1

C173

1

C174

2

2

10U_0603_6.3V6M

1

2

1U_0402_6.3V6K

C175

2011/11/01

2011/11/01

2011/11/01

DDR_B_D[0..63] <7>

DDR_B_DQS[0..7] <7>

DDR_B_DQS#[0..7] <7>

DDR_B_MA[0..15] <7>

(10uF_0603_6.3V)*8
(

0.1uF_402_10V)*4

10U_0603_6.3V6M

1

C163

C164

2

1U_0402_6.3V6K

1

1

C176

2

2

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

1

2

10U_0603_6.3V6M

C165

1U_0402_6.3V6K

Deciphered Date

Deciphered Date

Deciphered Date

2

10U_0603_6.3V6M

10U_0603_6.3V6M

1

C166

2

10U_0603_6.3V6M

1

1

C167

2

2

Layout Note:
Place near DIMM

DDR_B_DM[0:7] connect to GND

2012/12/31

2012/12/31

2012/12/31

2

C168

10U_0603_6.3V6M

1

2

0.1U_0402_10V6K

1

C169

2

Title

Title

Title

DDRIII-SODIMM SLOT2

DDRIII-SODIMM SLOT2

DDRIII-SODIMM SLOT2

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

0.1U_0402_10V6K

1

C170

C171

2

Monday, January 14, 2013

Monday, January 14, 2013

Monday, January 14, 2013

1

0.1U_0402_10V6K

0.1U_0402_10V6K

1

1

C172

2

2

Y400S-NM-A141

Y400S-NM-A141

Y400S-NM-A141

1

13 65

13 65

13 65

1.0

1.0

1.0

5

4

3

2

1

W=20mils W=20mils

+RTCBATT +RTCVCC

D D

+RTCVCC

INTVRMEN

H

*

L

R99

12

1K_0402_5%

1 2

R101 1M_0402_5%

1 2

R102 330K_0402_5%

：：：：

Integrated VRM enable (Defaul t)

：：：：

Integrated VRM disable

1

2

C179
1U_0603_10V4Z

SM_INTRUDER#

PCH_INTVRMEN

+RTCVCC

1 2

R103 20K_04 02_5%

1 2

R100 20K_04 02_5%

1U_0603_10V4Z

1U_0603_10V4Z

(INTVRMEN should always be pull high.)

+3VS

*

C C

+3V_PCH

*

+3V_PCH

1 2

R105 1K_0402_5%@

HIGH= Enable ( No Reboot )
LOW= Disable (D efault)

R106 1K_0402_5%@

Low = Disabled (Default)
High = Enabled

R108 1K_0402_5%

12

[Flash Descrip tor Security O veride]

12

HDA_SPKR

HDA_SDOUT

HDA_SYNC

ME_FLASH<45>

This signal has a weak intern al pull-down

On Die PLL VR S elect is suppl ied by

1.5V when smapl ed high (Defau lt)

1.8V when sampl ed low

*

Needs to be pul led High for C hief River pla tfrom

ME_FLASH

+3V_PCH

SPI_CLK_PCH_0
SPI_CLK_PCH_1

SPI_SB_CS0#_R

SPI_CS1#_R

SPI_SI_R
SPI_SI_R1 SPI_SI

SPI_SO_L
SPI_SO_L1

R298 33_0402_5%
R299 33_0402_5%

R130 R_short 0_0402_5%

R303 R_short 0_0402_5%

R133 33_0402_5%
R204 33_0402_5%

R131 33_0402_5%
R294 33_0402_5%

CMOS

1

2

1

@

2

HDA_SPKR<42>

HDA_SDIN0<42>

1 2

1 2

12

12

12
12

12

JCMOS
SHORT PADS@

12

JME
SHORT PADS

12

12

C183

C182

R109 R_short 0_0402_5%

R107 1K_040 2_1%@

R317 10K_04 02_5%@

R110 51_0402_5 %

1 2
1 2

1 2
1 2

U4A

PCH_RTCX1

PCH_RTCX2

PCH_RTCRST#

PCH_SRTCRST#

SM_INTRUDER#

PCH_INTVRMEN SERIRQ

HDA_BIT_CLK

HDA_SYNC

HDA_SPKR

HDA_RST#

HDA_SDIN0

HDA_SDOUT

PCH_GPIO33

PCH_GPIO13

PCH_JTAG_TCK

PCH_JTAG_TMS

PCH_JTAG_TDI

PCH_JTAG_TDO

SPI_CLK_PCH

SPI_SB_CS0#

SPI_CS1#

SPI_SO_R

A20

RTCX1

C20

RTCX2

D20

RTCRST#

G22

SRTCRST#

K22

INTRUDER#

C17

INTVRMEN

N34

HDA_BCLK

L34

HDA_SYNC

T10

SPKR

K34

HDA_RST#

E34

HDA_SDIN0

G34

HDA_SDIN1

C34

HDA_SDIN2

A34

HDA_SDIN3

A36

HDA_SDO

C36

HDA_DOCK_EN# / GPIO33

N32

HDA_DOCK_RST# / GPIO13

J3

JTAG_TCK

H7

JTAG_TMS

K5

JTAG_TDI

H1

JTAG_TDO

T3

SPI_CLK

Y14

SPI_CS0#

T1

SPI_CS1#

V4

SPI_MOSI

U3

SPI_MISO

PANTHER-POINT_FCBGA989

RTCIHDA

JTAG

SPI

FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3

LPC

FWH4 / LFRAME#

LDRQ0#

LDRQ1# / GPIO23

SERIRQ

SATA0RXN
SATA0RXP

SATA0TXN
SATA0TXP

SATA1RXN
SATA1RXP

SATA 6G

SATA1TXN
SATA1TXP

SATA2RXN
SATA2RXP

SATA2TXN
SATA2TXP

SATA3RXN
SATA3RXP

SATA3TXN
SATA3TXP

SATA4RXN
SATA4RXP

SATA4TXN

SATA

SATA4TXP

SATA5RXN
SATA5RXP

SATA5TXN
SATA5TXP

SATAICOMPO

SATAICOMPI

SATA3RCOMPO

SATA3COMPI

SATA3RBIAS

SATALED#

SATA0GP / GPIO21

SATA1GP / GPIO19

EC and Mini car d debug port

C38

LPC_AD0

A38

LPC_AD1

B37

LPC_AD2

C37

LPC_AD3

D36

LPC_FRAME#

E36
K36

V5

AM3

SATA_DTX_C_IRX_N0

AM1

SATA_DTX_C_IRX_P0

AP7

SATA_ITX_C_DRX_N0

AP5

SATA_ITX_C_DRX_P0

AM10

SATA_DTX_C_IRX_N1

AM8

SATA_DTX_C_IRX_P1

AP11

SATA_ITX_C_DRX_N1

AP10

SATA_ITX_C_DRX_P1

AD7

SATA_DTX_C_IRX_N2

AD5

SATA_DTX_C_IRX_P2

AH5

SATA_ITX_C_DRX_N2

AH4

SATA_ITX_C_DRX_P2

AB8
AB10
AF3
AF1

Y7
Y5
AD3
AD1

Y3
Y1
AB3
AB1

Y11

Y10

SATA_COMP

AB12

AB13

SATA3_COMP

AH1

RBIAS_SATA3

P3

HDD_LED#

V14

PCH_GPIO21

P1

SATA_DET#

LPC_AD0 <37,45>
LPC_AD1 <37,45>
LPC_AD2 <37,45>
LPC_AD3 <37,45>

LPC_FRAME# <37,45>

R104 10K_0402_5%

12

SERIRQ <45>

12

C184 0.01U_0402_16V7K

12

C185 0.01U_0402_16V7K

12

C273 0.01U_0402_16V7K

12

C272 0.01U_0402_16V7K

12

C186 0.01U_0402_16V7K

12

C187 0.01U_0402_16V7K

1 2

R111 37.4_0402_1%

1 2

R113 49.9_0402_1%

1 2

R115 750_0402_1%

R120 10K_0402_5%

R119 10K_0402_5%

R316 10K_0402_5%

12

12

12

+3VS

SATA_ITX_DRX_N0
SATA_ITX_DRX_P0

SATA_ITX_DRX_N1
SATA_ITX_DRX_P1

SATA_ITX_DRX_N2_CONN
SATA_ITX_DRX_P2_CONN

+1.05VS_VCC_SATA

+1.05VS_SATA3

HDD_LED# <47>

SATA_DET# <37>

+3VS

+3VS

+3VS

S

HDD

ODD

SD

SATA_DTX_C_IRX_N0 <37>
SATA_DTX_C_IRX_P0 <37>

SATA_ITX_DRX_N0 <37>
SATA_ITX_DRX_P0 <37>

SATA_DTX_C_IRX_N1 <41>

SATA_DTX_C_IRX_P1 <41>
SATA_ITX_DRX_N1 <41>
SATA_ITX_DRX_P1 <41>

SATA_DTX_C_IRX_N2 <41>

SATA_DTX_C_IRX_P2 <41>
SATA_ITX_DRX_N2_CONN <41>
SATA_ITX_DRX_P2_CONN <41>

B B

HDA AUDIO

HDA_BITCLK_AUDIO<42>

HDA_SYNC_AUDIO<42>

HDA_RST_AUDIO#<42>

HDA_SDOUT_AUDIO<42>

1 2

R112
33_0402_5%

1 2

R114
33_0402_5%

1 2

R116
33_0402_5%

1 2

R118
33_0402_5%

HDA_BIT_CLK

HDA_SYNC_R

HDA_RST#

HDA_SDOUT

12

R1353
1M_0402_5%

+5VS

G

2

S

13

HDA_SYNC

D

Q10
BSS138_NL_SOT23-3

1

2

R98

1 2

10M_0402_5%

Y1

1 2

32.768KHZ_12.5PF_CM31532768DZFT

C180
18P_0402_50V8J

PCH_RTCX1

PCH_RTCX2

1

C181
18P_0402_50V8J

2

For EMI

SPI_CLK_PCH

33_0402_5%

22P_0402_50V8J

R124

C190

12

@

@

4MB P/N : SA00005P500 2MB P/N : SA00003FO10

+3V_PCH +3V_PCH +3V_PCH

12

R123

@

200_0402_5%

12

R128

@

100_0402_1%

4

5

12

R122

@

200_0402_5%

12

R126

@

100_0402_1%

12

R121

@

A A

200_0402_5%

PCH_JTAG_TDO PCH_JTAG_TDIPCH_JTAG_TMS

12

R125

@

100_0402_1%

+3VS

1 2

R127 3.3K_0402_5%

1 2

R129 3.3K_0402_5%

U5

SPI_SB_CS0#_R

SPI_SO_L
SPI_WP#

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUT URE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUT URE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUT URE CENTER.

1

CS#

2

DO

HOLD#

3

WP#

4

GND

W25Q32BVSSIG_SO8

2011/11/01

2011/11/01

2011/11/01

3

VCC

CLK

SPI_WP#
SPI_HOLD#

8
7

SPI_HOLD#

6

SPI_CLK_PCH_0

5

SPI_SI_R

DI

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

+3VS

1

2

Deciphered Date

Deciphered Date

Deciphered Date

C191

0.1U_0402_16V4Z

2

2012/12/31

2012/12/31

2012/12/31

+3VS

1 2

R292 3.3K_0402_5%

1 2

R246 3.3K_0402_5%

SPI_CS1#_R
SPI_SO_L1
SPI_WP#_1

1
2
3
4

Title

Title

Title

PCH (1/9) SATA,HDA,SPI, LPC, XDP

PCH (1/9) SATA,HDA,SPI, LPC, XDP

PCH (1/9) SATA,HDA,SPI, LPC, XDP

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

U9

CS#
DO(IO1)

HOLD#(IO3)
WP#(IO2)
GND

W25Q16BVSSIG_SO8

DI(IO0)

Monday, January 14, 2013

Monday, January 14, 2013

Monday, January 14, 2013

SPI_WP#_1
SPI_HOLD#_1

8

VCC

7
6

CLK

5

Y400S-NM-A141

Y400S-NM-A141

Y400S-NM-A141

SPI_HOLD#_1
SPI_CLK_PCH_1
SPI_SI_R1

1

+3VS

1

C275

0.1U_0402_16V4Z

2

of

of

of

14 65

14 65

14 65

1.0

1.0

1.0

5

PCIE_PRX_DTX_N1<38>

LAN

D D

WLAN

Card Reader

C C

PCIE_PRX_DTX_P1<38>
PCIE_PTX_C_DRX_N1<38>
PCIE_PTX_C_DRX_P1<38>

PCIE_PRX_DTX_N2<37>
PCIE_PRX_DTX_P2<37>
PCIE_PTX_C_DRX_N2<37>
PCIE_PTX_C_DRX_P2<37>

PCIE_PRX_DTX_N4<44>
PCIE_PRX_DTX_P4<44>
PCIE_PTX_C_DRX_N4<44>
PCIE_PTX_C_DRX_P4<44>

LAN

WLAN

1 2

C192 0.1U_0402_10V7K

1 2

C193 0.1U_0402_10V7K

1 2

C194 0.1U_0402_10V7K

1 2

C195 0.1U_0402_10V7K

1 2

C277 0.1U_0402_10V7K

1 2

C276 0.1U_0402_10V7K

CLK_PCIE_LAN#<38>
CLK_PCIE_LAN<38>

CLKREQ_LAN#<38>

CLK_PCIE_WLAN1#<37>
CLK_PCIE_WLAN1<37>

WLAN_CLKREQ1#<37>

Only for 15" TV function

Card Reader

B B

2nd VGA

+3V_PCH

R152 10K_0402_5%

R168 10K_0402_5%

R165 10K_0402_5%

R147 10K_0402_5%

R170 10K_0402_5%

R172 10K_0402_5%

R174 10K_0402_5%

+3VS

A A

R158 10K_0402_5%

R308 10K_0402_5%

12

12

12

12

12

12

12

12

12

CLK_PCIE_CARD_PCH#<44>
CLK_PCIE_CARD_PCH<44>

CLKREQ_LAN#

PCH_GPIO25

PCH_GPIO26

PCH_GPIO44

CLK2_REQ_GPU#_R

PCH_GPIO45

PCH_GPIO46

WLAN_CLKREQ1#

PCH_GPIO20

CLK_PCIE_2VGA#<32>
CLK_PCIE_2VGA<32>

CLK2_REQ_GPU#_R<32>

PCIE_PRX_DTX_N1
PCIE_PRX_DTX_P1
PCIE_PTX_DRX_N1
PCIE_PTX_DRX_P1

PCIE_PRX_DTX_N2
PCIE_PRX_DTX_P2
PCIE_PTX_DRX_N2
PCIE_PTX_DRX_P2

PCIE_PRX_DTX_N4
PCIE_PRX_DTX_P4
PCIE_PTX_DRX_N4
PCIE_PTX_DRX_P4

CLK_PCIE_LAN#
CLK_PCIE_LAN

CLKREQ_LAN#

CLK_PCIE_WLAN1#
CLK_PCIE_WLAN1

WLAN_CLKREQ1#

PCH_GPIO20

CLK_PCIE_CARD_PCH#
CLK_PCIE_CARD_PCH

PCH_GPIO25

PCH_GPIO26

PCH_GPIO44

CLK_PCIE_2VGA#
CLK_PCIE_2VGA

CLK2_REQ_GPU#_R

PCH_GPIO45

PCH_GPIO46

4

BG34

BJ34
AV32
AU32

BE34

BF34

BB32

AY32

BG36

BJ36
AV34
AU34

BF36
BE36

AY34
BB34

BG37
BH37

AY36
BB36

BJ38
BG38
AU36
AV36

BG40

BJ40

AY40
BB40

BE38
BC38

AW38

AY38

Y40
Y39

J2

AB49
AB47

M1

AA48
AA47

V10

Y37
Y36

A8

Y43
Y45

L12

V45
V46

L14

AB42
AB40

E6

V40
V42

T13

V38
V37

K12

AK14
AK13

PANTHER-POINT_FCBGA989

U4B

PERN1
PERP1
PETN1
PETP1

PERN2
PERP2
PETN2
PETP2

PERN3
PERP3
PETN3
PETP3

PERN4
PERP4
PETN4
PETP4

PERN5
PERP5
PETN5
PETP5

PERN6
PERP6
PETN6
PETP6

PERN7
PERP7
PETN7
PETP7

PERN8
PERP8
PETN8
PETP8

CLKOUT_PCIE0N
CLKOUT_PCIE0P

PCIECLKRQ0# / GPIO73

CLKOUT_PCIE1N
CLKOUT_PCIE1P

PCIECLKRQ1# / GPIO18

CLKOUT_PCIE2N
CLKOUT_PCIE2P

PCIECLKRQ2# / GPIO20

CLKOUT_PCIE3N
CLKOUT_PCIE3P

PCIECLKRQ3# / GPIO25

CLKOUT_PCIE4N
CLKOUT_PCIE4P

PCIECLKRQ4# / GPIO26

CLKOUT_PCIE5N
CLKOUT_PCIE5P

PCIECLKRQ5# / GPIO44

CLKOUT_PEG_B_N
CLKOUT_PEG_B_P

PEG_B_CLKRQ# / GPIO56

CLKOUT_PCIE6N
CLKOUT_PCIE6P

PCIECLKRQ6# / GPIO45

CLKOUT_PCIE7N
CLKOUT_PCIE7P

PCIECLKRQ7# / GPIO46

CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P

SMBUSController

SML1ALERT# / PCHHOT# / GPIO74

PCI-E*

CLOCKS

SMBALERT# / GPIO11

SML0ALERT# / GPIO60

SML1CLK / GPIO58

SML1DATA / GPIO75

Link

PEG_A_CLKRQ# / GPIO47

CLKOUT_PEG_A_N
CLKOUT_PEG_A_P

CLKOUT_DMI_N
CLKOUT_DMI_P

CLKOUT_DP_N

CLKOUT_DP_P

CLKIN_DMI_N
CLKIN_DMI_P

CLKIN_GND1_N
CLKIN_GND1_P

CLKIN_DOT_96N
CLKIN_DOT_96P

CLKIN_SATA_N
CLKIN_SATA_P

REFCLK14IN

CLKIN_PCILOOPBACK

XTAL25_OUT

XCLK_RCOMP

CLKOUTFLEX0 / GPIO64

CLKOUTFLEX1 / GPIO65

CLKOUTFLEX2 / GPIO66

CLKOUTFLEX3 / GPIO67

FLEX CLOCKS

3

E12

PCH_GPIO11

H14

SMBCLK

SMBDATA

SML0CLK

SML0DATA

CL_CLK1

CL_DATA1

CL_RST1#

XTAL25_IN

PCH_SMBCLK

C9

PCH_SMBDATA

A12

C8

SML0CLK

G12

SML0DATA

C13

PCH_HOT#

E14

SML1CLK

M16

SML1DATA

M7

T11

P10

M10

CLK_REQ_GPU#_R

AB37

CLK_PCIE_VGA#

AB38

CLK_PCIE_VGA

AV22

CLK_CPU_DMI#

AU22

CLK_CPU_DMI

AM12
AM13

BF18

CLK_BUF_CPU_DMI#

BE18

CLK_BUF_CPU_DMI

BJ30

CLKIN_DMI2#

BG30

CLKIN_DMI2

G24

CLK_BUF_DREF_96M#

E24

CLK_BUF_DREF_96M

AK7

CLK_BUF_PCIE_SATA#

AK5

CLK_BUF_PCIE_SATA

K45

CLK_BUF_ICH_14M

H45

CLK_PCI_LPBACK

V47

XTAL25_IN

V49

XTAL25_OUT

Y47

XCLK_RCOMP

K43

F47

H47

S_DGPU_RST_R

K49

PCH_GPIO67

BIOS Request SKU ID

GP

IO64, 65 that only for GC6

1. GPIO64 : S_DGPU_GC6_EN

2. GPIO65 : S_DGPU_PWROK

+3V_PCH

DRAMRST_CNTRL_PC H <7>

CLK_REQ_GPU#_R <23>

R155 10K_0402_5%
R157 10K_0402_5%

R159 10K_0402_5%
R160 10K_0402_5%

R162 10K_0402_5%
R163 10K_0402_5%

R164 10K_0402_5%
R166 10K_0402_5%

R167 10K_0402_5%

R171 90.9_0402_1%

R182 10K_0402_5%

R1504 0_0402_5%

2

R136

1 2

2.2K_0402_5%

R135

1 2

2.2K_0402_5%

PCH_SMBCLK

PCH_SMBDATA SMB_DATA_S3

+3V_PCH +3V S

CLK_PCIE_VGA# <23>
CLK_PCIE_VGA <23>

CLK_CPU_DMI# <6>
CLK_CPU_DMI <6>

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2

CLK_PCI_LPBACK <18>

1 2

12

1 2

PCH_GPIO67 <19>

1 2

1 2

SML1CLK

SML1DATA

+1.05VS_VCCDIFFCLKN

+3VS

3 4

R141

2.2K_0402_5%

R142

2.2K_0402_5%

S_DGPU_RST <18,32>

5

G

D

2

G

6 1

D

Q60B

S

2N7002KDWH_SOT363-6

3 4

DI

MM1, DIMM2, Mini CARD, TP

2N7002KDWH
Vth= min 1V, max 2.5V
ESD 2KV

SMB_CLK_S3

S

Q60A
2N7002KDWH_SOT363-6

R137

R138

20120731 --> ch ange to +3VS

VGA, EC, Thermal Sensor

2

G

20120731 --> change to +3VS

6 1

D

5

G

D

S

20120816 --->

1.

2. C196, C197 change to 10pf

EC_SMB_CK2

S

Q61A
2N7002KDWH_SOT363-6

EC_SMB_DA2

Q61B
2N7002KDWH_SOT363-6

PCH_GPIO11

DRAMRST_CNTRL_PC H

SML0CLK

SML0DATA

PCH_HOT#

CLK_REQ_GPU#_R

XTAL25_IN

XTAL25_OUT

1

2

change P/N to 7V2500014(10pf), SJ10000E80J

Reserve for EMI please close to
PCH

CLK_BUF_ICH_14M

CLK_PCI_LPBACK

1

12

2.2K_0402_5%

12

2.2K_0402_5%

SMB_CLK_S3 < 12,13,37,46>

SMB_DATA_S3 <12,13,37,46>

EC_SMB_CK2 <23,32,40,45>

EC_SMB_DA2 <23,32,40,45>

R134

R329

R335

1 2

R336

1 2

R140

R202

1 2

1 2

1M_0402_5%

Y2

1

1

GND

2

25MHZ_10PF_7V25000014

C196
10P_0402_50V8J

R175

@

33_0402_5%

12

R176

@

33_0402_5%

12

12

10K_0402_5%

12

1K_0402_5%

2.2K_0402_5%

2.2K_0402_5%

12

10K_0402_5%

10K_0402_5%

R169

GND

10P_0402_50V8J

+3VS

+3V_PCH

3

3

4

C197

C198

@

22P_0402_50V8J

1 2

C199

@

22P_0402_50V8J

1 2

1

2

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

3

2011/11/01

2011/11/01

2011/11/01

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2012/12/31

2012/12/31

2012/12/31

Title

PCH (2/9) PCIE, SMBUS, CLK

PCH (2/9) PCIE, SMBUS, CLK

PCH (2/9) PCIE, SMBUS, CLK

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Monday, January 14, 2013

Monday, January 14, 2013

Monday, January 14, 2013

Y400S-NM-A141

Y400S-NM-A141

Y400S-NM-A141

1

of

of

of

15 65

15 65

15 65

1.0

1.0

1.0

5

D D

+3VS

1

C1060

0.1U_0402_16V4Z

VGATE<59>

C C

B B

+3V_PCH

MC74VHC1G08DFT2G SC70 5P

R192 200_0402_5%

R194 10K_0402_5%

VGATE

PCH_PWROK

12

12

2

2

B

1

A

U6

F

or Deep S3

For Deep S3

5

P

4

Y

12

G

3

PM_DRAM_PWR GD

SUSWARN#

R180

@

100K_0402_1%

PCH_PWROK<45>

APWROK can be c onnect to
PWROK if iAMT d isable

PM_DRAM_PWR GD<6>

PBTN_OUT#<45>

AC_PRESENT<45>

+3V_PCH

SYS_PWROK <6>

SUSACK#<45> DPWROK_EC <45>

+3VS

SUSWARN#<45>

+3VS

R1290 200_0402_5%@

7/28 Modify fol low Module Des ign.

4

DMI_CTX_PRX_N0<5>
DMI_CTX_PRX_N1<5>
DMI_CTX_PRX_N2<5>
DMI_CTX_PRX_N3<5>

DMI_CTX_PRX_P0<5>
DMI_CTX_PRX_P1<5>
DMI_CTX_PRX_P2<5>
DMI_CTX_PRX_P3<5>

DMI_CRX_PTX_N0<5>
DMI_CRX_PTX_N1<5>
DMI_CRX_PTX_N2<5>
DMI_CRX_PTX_N3<5>

DMI_CRX_PTX_P0<5>
DMI_CRX_PTX_P1<5>
DMI_CRX_PTX_P2<5>
DMI_CRX_PTX_P3<5>

+1.05VS

R1457 R_short 0_0402_5%

R184 10K_0402_5%

R190

R_short 0_0402_5%

1 2

R193 R_short 0_0402_5%

R1455 R_short 0_0402_5%

1 2

R198 R_short 0_0402_5%

1 2

R208 R_short 0_0402_5%

1 2

R200 8.2K_0402_5%

R201 10K_0402_5%

12

R177

1 2

49.9_0402_1%

R178

1 2

750_0402_1%

4mil width and place
within 500mil o f the PCH

12

12

12

R191

R_short 0_0402_5%

12

12

PM_DRAM_PWR GD

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

DMI_IRCOMP

RBIAS_CPY

SUSACK#_R

SYS_RST#

SYS_PWROK

PWROK

12

APWROK

PM_DRAM_PWR GD

PCH_RSMRST#_R

SUSWARN#_R

PBTN_OUT#_R

AC_PRESENT_R

PCH_GPIO72

RI#

U4C

BC24

DMI0RXN

BE20

DMI1RXN

BG18

DMI2RXN

BG20

DMI3RXN

BE24

DMI0RXP

BC20

DMI1RXP

BJ18

DMI2RXP

BJ20

DMI3RXP

AW24

DMI0TXN

AW20

DMI1TXN

BB18

DMI2TXN

AV18

DMI3TXN

AY24

DMI0TXP

AY20

DMI1TXP

AY18

DMI2TXP

AU18

DMI3TXP

BJ24

DMI_ZCOMP

BG25

DMI_IRCOMP

BH21

DMI2RBIAS

C12

SUSACK#

K3

SYS_RESET#

P12

SYS_PWROK

L22

PWROK

L10

APWROK

B13

DRAMPWROK

C21

RSMRST#

K16

SUSWARN#/SUSPW RDNACK/GPIO30

E20

PWRBTN#

H20

ACPRESENT / GPIO31

E10

BATLOW# / GPIO72

A10

RI#

PANTHER-POINT_FCBGA989

3

FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7

FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5

DMI

System Power Management

FDI_RXP6

FDI

FDI_RXP7

FDI_INT

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

DSWVRMEN

DPWROK

WAKE#

CLKRUN# / GPIO32

SUS_STAT# / GPIO61

SUSCLK / GPIO62

SLP_S5# / GPIO63

SLP_S4#

SLP_S3#

SLP_A#

SLP_SUS#

PMSYNCH

SLP_LAN# / GPIO29

2

BJ14

FDI_CTX_PRX_N0

AY14

FDI_CTX_PRX_N1

BE14

FDI_CTX_PRX_N2

BH13

FDI_CTX_PRX_N3

BC12

FDI_CTX_PRX_N4

BJ12

FDI_CTX_PRX_N5

BG10

FDI_CTX_PRX_N6

BG9

FDI_CTX_PRX_N7

BG14

FDI_CTX_PRX_P0

BB14

FDI_CTX_PRX_P1

BF14

FDI_CTX_PRX_P2

BG13

FDI_CTX_PRX_P3

BE12

FDI_CTX_PRX_P4

BG12

FDI_CTX_PRX_P5

BJ10

FDI_CTX_PRX_P6

BH9

FDI_CTX_PRX_P7

AW16

FDI_INT

AV12

FDI_FSYNC0

BC10

FDI_FSYNC1

AV14

FDI_LSYNC0

BB10

FDI_LSYNC1

A18

DSWODVREN

E22

PCH_DPWROK_R

B9

N3

PM_CLKRUN#

G8

SUS_STAT#

N14

SUSCLK

D10

PM_SLP_S5#

H4

PM_SLP_S4#

F4

PM_SLP_S3#

G10

Can be left NC when IAMT is n ot support on the platfrom

G16

PM_SLP_SUS#_R

AP14

H_PM_SYNC

K14

PCH_GPIO29

Can be left NC if no use inte grated LAN.
10/06 Test poin t request

FDI_CTX_PRX_N0 <5>
FDI_CTX_PRX_N1 <5>
FDI_CTX_PRX_N2 <5>
FDI_CTX_PRX_N3 <5>
FDI_CTX_PRX_N4 <5>
FDI_CTX_PRX_N5 <5>
FDI_CTX_PRX_N6 <5>
FDI_CTX_PRX_N7 <5>

FDI_CTX_PRX_P0 <5>
FDI_CTX_PRX_P1 <5>
FDI_CTX_PRX_P2 <5>
FDI_CTX_PRX_P3 <5>
FDI_CTX_PRX_P4 <5>
FDI_CTX_PRX_P5 <5>
FDI_CTX_PRX_P6 <5>
FDI_CTX_PRX_P7 <5>

FDI_INT <5>

FDI_FSYNC0 <5>

FDI_FSYNC1 <5>

FDI_LSYNC0 <5>

FDI_LSYNC1 <5>

1 2

R181 R_short 0_0402_5%

1 2

R185 R_short 0_0402_5%

1 2

R253 10K_0402_5%

T60PAD

T61PAD

T62PAD

PM_SLP_S4# <45>EC_RSMRST#<45>

PM_SLP_S3# <45>

R1447 R_short 0_0402_5%

12

H_PM_SYNC <6>

T74PAD

DSWODVREN - On Die DSW VR Ena ble

*

H

：：：：

Enable

：：：：

Disable

L

DPWROK_EC

PCIE_WAKE#WAKE#

PCIE_WAKE# <19,37,38>

WAKE#

R186 10K_0402_5%

PM_SLP_SUS# <45,51>

1

DSWODVREN

1 2

+RTCVCC

For Deep S3

For Deep S3

12

R179
330K_0402_5%

12

R183
330K_0402_5%@

+3V_PCH

+3VALW

R195 200K_0402_5%

A A

12

5

AC_PRESENT_R

R197 10K_0402_5%

12

4

PCH_RSMRST#_R

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

3

2011/11/01

2011/11/01

2011/11/01

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2012/12/31

2012/12/31

2012/12/31

Title

Title

Title

PCH (3/9) DMI,FDI,PM,

PCH (3/9) DMI,FDI,PM,

PCH (3/9) DMI,FDI,PM,

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Monday, January 14, 2013

Monday, January 14, 2013

Monday, January 14, 2013

Y400S-NM-A141

Y400S-NM-A141

Y400S-NM-A141

1

of

of

of

16 65

16 65

16 65

1.0

1.0

1.0

5

D D

+3VS

OPT@

R836 2.2K_0402_5%

OPT@

R835 2.2K_0402_5%

OPT@

1 2

R205 2.2K_0402_5%

OPT@

1 2

R261 2.2K_0402_5%

OPT@

OPT@

OPT@

OPT@

OPT@

1 2

OPT@

1 2

12

12

12

12

R257 2.37K_0402_1%

C C

R266 150_0402_1%

R264 150_0402_1%

R262 150_0402_1%

B B

+3VS

R848 2.2K_0402_5%

R849 2.2K_0402_5%

EDID_CLK

EDID_DATA

CTRL_CLK

CTRL_DATA CTRL_CLK

LVDS_IBG

DAC_BLU

DAC_GRN

DAC_RED

CRT_DDC_CLK

CRT_DDC_DATA

4

PCH_ENBKL<34>
PCH_ENVDD<34>

PCH_PWM<34>

EDID_CLK<34>
EDID_DATA<34>

Remove netname LVD_REF

LVDS_ACLK#<34>
LVDS_ACLK<34>

LVDS_A0#<34>
LVDS_A1#<34>
LVDS_A2#<34>

LVDS_A0<34>
LVDS_A1<34>
LVDS_A2<34>

DAC_BLU<35>
DAC_GRN<35>
DAC_RED< 35>

CRT_DDC_CLK<35>
CRT_DDC_DATA<35>

CRT_HSYNC<35>
CRT_VSYNC<35>

R211

1K_0402_1%

PCH_ENBKL
PCH_ENVDD

PCH_PWM

EDID_CLK
EDID_DATA

CTRL_DATA

LVDS_IBG

LVDS_ACLK#
LVDS_ACLK

LVDS_A0#
LVDS_A1#
LVDS_A2#

LVDS_A0
LVDS_A1
LVDS_A2

DAC_BLU
DAC_GRN
DAC_RED

CRT_DDC_CLK
CRT_DDC_DATA

CRT_HSYNC
CRT_VSYNC

CRT_IREF

12

U4D

J47

L_BKLTEN

M45

L_VDD_EN

P45

L_BKLTCTL

T40

L_DDC_CLK

K47

L_DDC_DATA

T45

L_CTRL_CLK

P39

L_CTRL_DATA

AF37

LVD_IBG

AF36

LVD_VBG

AE48

LVD_VREFH

AE47

LVD_VREFL

AK39

LVDSA_CLK#

AK40

LVDSA_CLK

AN48

LVDSA_DATA#0

AM47

LVDSA_DATA#1

AK47

LVDSA_DATA#2

AJ48

LVDSA_DATA#3

AN47

LVDSA_DATA0

AM49

LVDSA_DATA1

AK49

LVDSA_DATA2

AJ47

LVDSA_DATA3

AF40

LVDSB_CLK#

AF39

LVDSB_CLK

AH45

LVDSB_DATA#0

AH47

LVDSB_DATA#1

AF49

LVDSB_DATA#2

AF45

LVDSB_DATA#3

AH43

LVDSB_DATA0

AH49

LVDSB_DATA1

AF47

LVDSB_DATA2

AF43

LVDSB_DATA3

N48

CRT_BLUE

P49

CRT_GREEN

T49

CRT_RED

T39

CRT_DDC_CLK

M40

CRT_DDC_DATA

M47

CRT_HSYNC

M49

CRT_VSYNC

T43

DAC_IREF

T42

CRT_IRTN

PANTHER-POINT_FCBGA989

3

SDVO_INTN
SDVO_INTP

DDPB_HPD

DDPB_0N

DDPB_0P

DDPB_1N

DDPB_1P

DDPB_2N

DDPB_2P

DDPB_3N

DDPB_3P

DDPC_HPD

DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P

DDPD_HPD

DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P

AP43
AP45

AM42
AM40

AP39
AP40

P38
M39

AT49
AT47
AT40

AV42
AV40
AV45
AV46
AU48
AU47
AV47
AV49

P46
P42

AP47
AP49
AT38

AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49

M43
M36

AT45
AT43
BH41

BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42

SDVO_TVCLKINN
SDVO_TVCLKINP

SDVO_STALLN
SDVO_STALLP

SDVO_CTRLCLK

SDVO_CTRLDATA

DDPB_AUXN
DDPB_AUXP

LVDS

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPC_AUXN
DDPC_AUXP

Digital Display Interface

DDPD_CTRLCLK

DDPD_CTRLDATA

DDPD_AUXN

CRT

DDPD_AUXP

HDMICLK
HDMIDAT

TMDS_B_HPD

TMDS_B_DATA2#_PCH
TMDS_B_DATA2_PCH
TMDS_B_DATA1#_PCH
TMDS_B_DATA1_PCH
TMDS_B_DATA0#_PCH
TMDS_B_DATA0_PCH
TMDS_B_CLK#_PCH
TMDS_B_CLK_PCH

2

HDMICLK <36>
HDMIDAT <36>

TMDS_B_HPD <36>

TMDS_B_DATA2#_PCH <36>
TMDS_B_DATA2_PCH <36>
TMDS_B_DATA1#_PCH <36>
TMDS_B_DATA1_PCH <36>
TMDS_B_DATA0#_PCH <36>
TMDS_B_DATA0_PCH <36>
TMDS_B_CLK#_PCH <36>
TMDS_B_CLK_PCH <36>

HDMICLK

HDMIDAT

1

OPT@

OPT@

12

12

R203 2.2K_0402_5%

R267 2.2K_0402_5%

+3VS

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUT URE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUT URE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUT URE CENTER.

3

2011/11/01

2011/11/01

2011/11/01

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2012/12/31

2012/12/31

2012/12/31

Title

PCH (4/9) LVDS,CRT,DP,HDMI

PCH (4/9) LVDS,CRT,DP,HDMI

PCH (4/9) LVDS,CRT,DP,HDMI

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Monday, January 14, 2013

Monday, January 14, 2013

Monday, January 14, 2013

Y400S-NM-A141

Y400S-NM-A141

Y400S-NM-A141

1

of

of

of

17 65

17 65

17 65

1.0

1.0

1.0

5

4

3

2

1

+3VS

D D

+3VS

C C

GP

IO53 => This Signal has a weak internal pull-up.
NOTE: The internal pull-up is disabled after
PLTRST# deasserts.

B B

PCH_GPIO51

A A

RP2

18

PCI_PIRQA#

27

PCI_PIRQD#

36

PCI_PIRQC#

45

8.2K_0804_8P4R_5%

8.2K_0804_8P4R_5%

R305 8.2K_0402_5%@

R297 8.2K_0402_5%@

R213 8.2K_0402_5%

R225 8.2K_0402_5%

R212 8.2K_0402_5%

R252 8.2K_0402_5%

R306 8.2K_0402_5%

R214 8.2K_0402_5%

R215 1K_0402_5%@

A16 swap overide Strap/Top-Block
Swap Override jumper

PCI_GNT3#

PCI_PIRQB#

RP1

18

PCH_GPIO2

27

DGPU_PWR_EN

36

PCH_GPIO4

45

ODD_DA#_R

1 2

1 2

1 2

1 2

1 2

1 2

1 2

@

1 2

@

12

Low = A16 swap
override/Top-Block
Swap Override enabled

**High=Default

*

1 2

R221 1K_0402_5%@

PPT EDS DOC#474146

Boot BIOS Strap bit1 BBS1

Boot BIOS

Bit10

0

1

0

Destination

eserved

R

Reserved

SPI

*

LPC

GNT1#/
GPIO51

Bit11

0 1

1

1

0

5

PCH_GPIO51

DGPU_GC6_EN

PCH_GPIO5

PCH_WL_OFF#

NVDD_PWR_EN

DGPU_HOLD_RST#

DGPU_GC6_EN

DGPU_HOLD_RST#

PCH_WL_OFF#

S_DGPU_RST<15,32>

CLK_PCI_LPBACK<15>
CLK_PCI_EC<45>

CLK_PCI_DB<37>

(Default)

Port1

Port2

Port3

Port4

USB30_RX_N3<48>

USB30_RX_P3<48>

USB30_TX_N3<48>

USB30_TX_P3<48>

DGPU_HOLD_RST#<23>

1 2

R1505 0_0402_5%@

NVDD_PWR_EN<58>
DGPU_PWR_EN<23,51>

DGPU_GC6_EN<27>
PCH_WL_OFF#<37>

ODD_DA#_R<41>

PLT_RST#<23,32,37,38,44,45,6>

1 2

R219 22_0402_5%

1 2

R220 22_0402_5%
R173 22_0402_5%

4

12

@

USB3.0

LEFT USB

USB30_RX_N3

USB30_RX_P3

USB30_TX_N3

USB30_TX_P3

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

DGPU_HOLD_RST#
NVDD_PWR_EN
DGPU_PWR_EN

PCH_GPIO51
DGPU_GC6_EN
PCH_WL_OFF#

PCH_GPIO2
ODD_DA#_R
PCH_GPIO4
PCH_GPIO5

20111024 Del PC I_PME#

PLT_RST#

CLK_PCI_LPBACK_R
CLK_PCI_EC_R
CLK_PCI_DB_R

PLT_RST#

12

R223
100K_0402_5%

U4E

BG26

TP1

BJ26

TP2

BH25

TP3

BJ16

TP4

BG16

TP5

AH38

TP6

AH37

TP7

AK43

TP8

AK45

TP9

C18

TP10

N30

TP11

H3

TP12

AH12

TP13

AM4

TP14

AM5

TP15

Y13

TP16

K24

TP17

L24

TP18

AB46

TP19

AB45

TP20

B21

TP21

M20

TP22

AY16

TP23

BG46

TP24

BE28

USB3Rn1

BC30

USB3Rn2

BE32

USB3Rn3

BJ32

USB3Rn4

BC28

USB3Rp1

BE30

USB3Rp2

BF32

USB3Rp3

BG32

USB3Rp4

AV26

USB3Tn1

BB26

USB3Tn2

AU28

USB3Tn3

AY30

USB3Tn4

AU26

USB3Tp1

AY26

USB3Tp2

AV28

USB3Tp3

AW30

USB3Tp4

K40

PIRQA#

K38

PIRQB#

H38

PIRQC#

G38

PIRQD#

C46

REQ1# / GPIO50

C44

REQ2# / GPIO52

E40

REQ3# / GPIO54

D47

GNT1# / GPIO51

E42

GNT2# / GPIO53

F46

GNT3# / GPIO55

G42

PIRQE# / GPIO2

G40

PIRQF# / GPIO3

C42

PIRQG# / GPIO4

D44

PIRQH# / GPIO5

K10

PME#

C6

PLTRST#

H49

CLKOUT_PCI0

H43

CLKOUT_PCI1

J48

CLKOUT_PCI2

K42

CLKOUT_PCI3

H40

CLKOUT_PCI4

PANTHER-POINT_FCBGA989

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

RSVD

PCI

USB

OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43

OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14

2011/11/01

2011/11/01

2011/11/01

3

AY7

RSVD1

AV7

RSVD2

AU3

RSVD3

BG4

RSVD4

AT10

RSVD5

BC8

RSVD6

AU2

RSVD7

AT4

RSVD8

AT3

RSVD9

AT1

RSVD10

AY3

RSVD11

AT5

RSVD12

AV3

RSVD13

AV1

RSVD14

BB1

RSVD15

BA3

RSVD16

BB5

RSVD17

BB3

RSVD18

BB7

RSVD19

BE8

RSVD20

BD4

RSVD21

BF6

RSVD22

AV5

RSVD23

AV10

RSVD24

AT8

RSVD25

AY5

RSVD26

BA2

RSVD27

AT12

RSVD28

BF3

RSVD29

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P

USBP10N

USBP10P

USBP11N

USBP11P

USBP12N

USBP12P

USBP13N

USBP13P

USBRBIAS#

USBRBIAS

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

USB DEBUG = PORT1 AND PORT9

C24

USB20_N0

A24

USB20_P0

C25
B25
C26

USB20_N2

A26

USB20_P2

K28
H28
E28
D28
C28

USB20_N5

A28

USB20_P5

C29
B29
N28
M28
L30
K30
G30

USB20_N9

E30

USB20_P9

C30

USB20_N10

A30

USB20_P10

L32
K32
G32
E32
C32

USB20_N13

A32

USB20_P13

C33

USBRBIAS

Within 500 mils

B33

A14

USB_OC0#

K20

USB_OC1#

B17

USB_OC2#

C16

USB_OC3#

L16

USB_OC4#

A16

USB_OC5#

D14

USB_OC6#

C14

USB_OC7#

Deciphered Date

Deciphered Date

Deciphered Date

USB20_N0 <34>
USB20_P0 <34>

USB20_N2 <48>
USB20_P2 <48>

USB20_N5 <49>
USB20_P5 <49>

Camera

LEFT USB

RIGHT USB 1 (CHARGER PORT, SUB/B)

Some PCH config not support U SB port 6 & 7.

2

USB20_N9 <49>
USB20_P9 <49>
USB20_N10 <37>
USB20_P10 <37>

USB20_N13 <47>
USB20_P13 <47>

R218

1 2

22.6_0402_1%

USB_OC1# <48>
USB_OC2# <49>

USB_OC4# <49>

2012/12/31

2012/12/31

2012/12/31

RIGHT USB 2 (SUB/B)
WLAN

BT

USB3 Port3, USB 2 Port2

SB2 Port5, Char ger Port

U

USB2 Port9, Rig ht USB (Sub/B)

+3V_PCH

RP3

USB_OC5#
USB_OC2#
USB_OC7#
USB_OC0#

USB_OC6#
USB_OC1#
USB_OC4#
USB_OC3#

Title

Title

Title

PCH (5/9) PCI, USB

PCH (5/9) PCI, USB

PCH (5/9) PCI, USB

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Monday, January 14, 2013

Monday, January 14, 2013

Monday, January 14, 2013

Y400S-NM-A141

Y400S-NM-A141

Y400S-NM-A141

1

4 5
3 6
2 7
1 8

10K_1206_8P4R_5%

RP4

4 5
3 6
2 7
1 8

10K_1206_8P4R_5%

of

of

of

18 65

18 65

18 65

1.0

1.0

1.0

5

D D

+3VS

R1493 10K_0402_5%

+3V_PCH

R235 10K_0402_5%

GPIO28

On-Die PLL Voltage Regulator
This signal has a weak internal pull up

：

On-Die voltage regulator enab le

H

*

L

：

On-Die PLL Volt age Regulator disable

R240 1K_0402_5%@

C C

PCH_GPIO27 (Have internal Pull-High)

*

H

igh: VCCVRM VR Enable

Low: VCCVRM VR Disable

+3VALW

R207 10K_0402_5%

R245 10K_0402_5%@

R250 200K_0402_5%

+3VS

B B

+3V_PCH

R251

R259 10K_0402_5%

1 2

DS3@

1 2

1 2

1 2

1 2

12

12

12

10K_0402_5%

EC_SCI#

EC_SMI#

PCH_GPIO28

DS3_WAKE#_R

ODD_DETECT#

SLAVE_PRESENT#

PCH_GPIO37

GC6_EVENT#<23,32,45>

+3VS

+3VS

+3V_PCH

EC_LID_OUT#<45>

+3VS

DGPU_PWROK<27,55,58>

PCH_BT_DISABLE#<37>

PCH_BT_ON#<37,47>

+3VS

PCIE_WAKE#<16,37,38>

+3VS

+3VS

4

1 2

R233 10K_0402_5%

1 2

R227 10K_0402_5%

1 2

R228 10K_0402_5%

1 2

R229 10K_0402_5%@

1 2

R230 10K_0402_5%

1 2

R231 10K_0402_5%

1 2

R232 10K_0402_1%

1 2

R238 10K_0402_5%

1 2

R241 10K_04 02_5%<BOM Structure>

+3V_PCH

+3VS

1 2

1 2

R243 10K_0402_5%

1 2

R247 10K_0402_5%

1 2

R248 10K_0402_5%

1 2

R249 10K_0402_5%

R242

3

Function

Optimus

Reserve

DIS
(SLI)

Reserve

14"

@

12

GC6_EVENT#_R

R2340_0402_5%

PCH_GPIO1

PCH_GPIO6

EC_SCI#<45>

EC_SMI#<45>

@

ODD_EN<41>

@

12

R2240_0402_5%

10K_0402_5%

ODD_DETECT#<41>

SLAVE_PRESENT#<32>

EC_SCI#

EC_SMI#

PCH_GPIO12

EC_LID_OUT#

PCH_GPIO16

DGPU_PWROK

PCH_BT_DISABLE#

ODD_EN

DS3_WAKE#_R

PCH_GPIO28

PCH_BT_ON#

PCH_GPIO35

ODD_DETECT#

PCH_GPIO37

PCH_GPIO38

PCH_GPIO39

PCH_GPIO48

PCH_GPIO49

SLAVE_PRESENT#

15"

U4F

T7

BMBUSY# / GPIO0

A42

TACH1 / GPIO1

H36

TACH2 / GPIO6

E38

TACH3 / GPIO7

C10

GPIO8

C4

LAN_PHY_PWR_CTRL / GPIO12

G2

GPIO15

U2

SATA4GP / GPIO16

D40

TACH0 / GPIO17

T5

SCLOCK / GPIO22

E8

GPIO24

E16

GPIO27

P8

GPIO28

K1

STP_PCI# / GPIO34

K4

GPIO35

V8

SATA2GP / GPIO36

M5

SATA3GP / GPIO37

N2

SLOAD / GPIO38

M3

SDATAOUT0 / GPIO39

V13

SDATAOUT1 / GPIO48

V3

SATA5GP / GPIO49 / TEMP_ALERT#

D6

GPIO57

A4

VSS_NCTF_1

A44

VSS_NCTF_2

A45

VSS_NCTF_3

A46

VSS_NCTF_4

A5

VSS_NCTF_5

A6

VSS_NCTF_6

B3

VSS_NCTF_7

B47

VSS_NCTF_8

BD1

VSS_NCTF_9

BD49

VSS_NCTF_10

BE1

VSS_NCTF_11

BE49

VSS_NCTF_12

BF1

VSS_NCTF_13

BF49

VSS_NCTF_14

PANTHER-POINT_FCBGA989

PCH_GPIO38

0 0

0 1

1 0

1 1

X

X X

GPIO

NCTF

PCH_GPIO67

X

TACH4 / GPIO68

TACH5 / GPIO69

TACH6 / GPIO70

TACH7 / GPIO71

A20GATE

PECI

RCIN#

PROCPWRGD

THRMTRIP#

INIT3_3V#

DF_TVS

CPU/MISC

TS_VSS1

TS_VSS2

TS_VSS3

TS_VSS4

NC_1

VSS_NCTF_15

VSS_NCTF_16

VSS_NCTF_17

VSS_NCTF_18

VSS_NCTF_19

VSS_NCTF_20

VSS_NCTF_21

VSS_NCTF_22

VSS_NCTF_23

VSS_NCTF_24

VSS_NCTF_25

VSS_NCTF_26

VSS_NCTF_27

VSS_NCTF_28

VSS_NCTF_29

VSS_NCTF_30

VSS_NCTF_31

VSS_NCTF_32

PCH_GPIO70

C40

S_DGPU_PWROK

B41

S_DGPU_PWR_EN

C41

A40

S_NVDD_PWR_EN

P4

AU16

P5

KBRST#

AY11

AY10

PCH_THRMTRIP#_R

T14

AY1

NV_CLE

AH8

AK11

AH10

AK10

P37

BG2

BG48

BH3

BH47

BJ4

BJ44

BJ45

BJ46

BJ5

BJ6

C2

C48

D1

D49

E1

E49

F1

F49

X

X

X

X

0

1

PCH_GPIO70

2

S_DGPU_PWROK <32>

S_DGPU_PWR_EN <32,51>

9/18 Reseve for SKU ID

S_NVDD_PWR_EN <32>

1 2

R236 10K_0402_5%

KBRST# < 45>

1 2

R239 390_0402_5%

H_CPUPWRGD <6>

H_THRMTRIP#

INIT3_3V

This signal has weak internal
PU, can't pull low

Intel schematic reviwe recommand.

SKU ID

PCH_GPIO67<15>

S_DGPU_PWR_EN

S_NVDD_PWR_EN

+3VS

GATEA20 <45>

H_THRMTRIP# <6>

PCH_THRMTRIP#_R <23,32>

S_DGPU_PWROK

KBRST#

PCH_THRMTRIP#_R

PROC_SEL

NV_CLE

H : Sandy Bridge

L : IVY Bridge

1 2

R217 1K_0402_5%

CLOSE TO THE BRANCHING POINT

1

R711

PCH_GPIO38

PCH_GPIO67

PCH_GPIO70

R712

OPT@

1 2

R268 10K_0402_5%

1 2

R237 10K_0402_5%

1 2

R255 10K_0402_5%

1 2

R226 10K_0402_5%

1 2

R244 10K_0402_5%

+1.8VS

R708

SLI@

@

1 2

10K_0402_5%

R709

1 2

10K_0402_5%

R216

2.2K_0402_5%

H_SNB_IVB# <6>

+3VS

R704

1 2

10K_0402_5%

R706

1 2

10K_0402_5%

@

1 2

10K_0402_5%

1 2

10K_0402_5%

+3VS

+3VS

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

3

2011/11/01

2011/11/01

2011/11/01

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2012/12/31

2012/12/31

2012/12/31

Title

PCH (6/9) GPIO, CPU, MISC

PCH (6/9) GPIO, CPU, MISC

PCH (6/9) GPIO, CPU, MISC

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Monday, January 14, 2013

Monday, January 14, 2013

Monday, January 14, 2013

Y400S-NM-A141

Y400S-NM-A141

Y400S-NM-A141

1

of

of

of

19 65

19 65

19 65

1.0

1.0

1.0

5

4

3

2

1

+1.05VS

1

D D

+1.05VS

R254 R_short 0_0603_5%

C C

B B

+1.05VS

Del R296 for 14 '
l

ayout

+3VS

+1.05VS

2

This pin can be left as no connect in
On-Die VR enabled mode (default).

C221

10U_0603_6.3V6M

1

2

R260

1 2

R_short 0_0603_5%

R263

1 2

R_short 0_0603_5%

10U_0603_6.3V6M

C209

12

+1.05VS

1U_0402_6.3V6K

1

2

C222

+1.05VS

C210

1U_0402_6.3V6K

1

2

T47PAD @

C223

1U_0402_6.3V6K

1

2

1

C227

0.1U_0402_10V7K

2

T48PAD @

+VCCP_VCCDMI

C211

1U_0402_6.3V6K

1

1

2

2

+1.05VS_VCCDPLLEXP

+VCCAPLLEXP

C224

1U_0402_6.3V6K

1

2

+3VS_VCCA3GBG

+VCCAFDI_VRM

+1.05VS_VCCAPLL_FDI

+1.05VS_VCCDPLL_FDI

C212

1U_0402_6.3V6K

C225

1U_0402_6.3V6K

1

2

U4G

1700mA

AA23

VCCCORE[1]

AC23

VCCCORE[2]

AD21

VCCCORE[3]

AD23

VCCCORE[4]

AF21

VCCCORE[5]

AF23

VCCCORE[6]

AG21

VCCCORE[7]

AG23

VCCCORE[8]

AG24

VCCCORE[9]

AG26

VCCCORE[10]

AG27

VCCCORE[11]

AG29

VCCCORE[12]

AJ23

VCCCORE[13]

AJ26

VCCCORE[14]

AJ27

VCCCORE[15]

AJ29

VCCCORE[16]

AJ31

VCCCORE[17]

AN19

VCCIO[28]

BJ22

VCCAPLLEXP

AN16

VCCIO[15]

AN17

VCCIO[16]

AN21

VCCIO[17]

AN26

VCCIO[18]

AN27

VCCIO[19]

AP21

VCCIO[20]

AP23

VCCIO[21]

AP24

VCCIO[22]

AP26

VCCIO[23]

AT24

VCCIO[24]

AN33

VCCIO[25]

AN34

VCCIO[26]

BH29

VCC3_3[3]

AP16

VCCVRM[2]

BG6

VccAFDIPLL

AP17

VCCIO[27]

AU20

VCCDMI[2]

PANTHER-POINT_FCBGA989

POWER

3711mA

63mA

CRTLVDS

1

VCC CORE

40mA

DMI

70mA

VCCIO

190mA

DFT / SPI HVCMOS

FDI

VCCADAC

VSSADAC

mA

VCCALVDS

VSSALVDS

VCCTX_LVDS[1]

VCCTX_LVDS[2]

VCCTX_LVDS[3]

VCCTX_LVDS[4]

VCC3_3[6]

VCC3_3[7]

VCCVRM[3]

VCCDMI[1]

VCCCLKDMI

VCCDFTERM[1]

VCCDFTERM[2]

VCCDFTERM[3]

VCCDFTERM[4]

10mA

VCCSPI

U48

U47

AK36

AK37

AM37

AM38

AP36

AP37

V33

V34

AT16

AT20

AB36

AG16

AG17

AJ16

AJ17

V1

+VCCADAC

1

C213

0.01U_0402_16V7K

2

+VCCA_LVDS

+VCCTX_LVDS

1

C216

0.01U_0402_16V7K

2

+3VS_VCC3_3_6

+VCCAFDI_VRM

+VCCP_VCCDMI

+1.05VS_VCC_DMI_CCI

1

C226
1U_0402_6.3V6K

2

+VCCPNAND

1

C228

0.1U_0402_10V7K

2

+3V_VCCPSPI

1

C230
1U_0402_6.3V6K

2

1

C219

0.1U_0402_10V7K

2

1

C214

0.1U_0402_10V7K

2

1

C217

0.01U_0402_16V7K

2

R256

R_short 0_0603_5%

R300

R_short 0_0603_5%

R293

R_short 0_0603_5%

R399

R_short 0_0603_5%

L1 change to 1 ohm P/N

RES 1/10W 1 +-1% 0603

S

1

C215
10U_0603_6.3V6M

2

1

C218
22U_0805_6.3V6M

2

+3VS

12

+1.05VS

12

+1.8VS

12

+3VS

12

L1

12

1_0603_1%

R295

12

R_short 0_0603_5%

0.1UH_MLF1608DR10KT_10%_1608

L2

0.1uH inductor, 200mA

12

1

R_short 0_0603_5%

C220
1U_0402_6.3V6K

2

+1.8VS

R258

+3VS

+3VS

PCH Power Rail Table

efer to CPU EDS R1.5

R

5

5

.05

S0 Iccmax
Current (A)

0.001

0.001

0.001

0.228

0.063

0.08

0.08

1.7

0.047

Voltage Rail

V_PROC_IO

V5REF

V5REF_Sus

Vcc3_3

VccADAC

VccADPLLA

VccADPLLB

VccCore

VccDMI

Voltage

1.05

3.3

3.3

1

1.05

1.05

1.05

1.05VccIO 3.711

+1.05VS+VCCP_VCCDMI

12

1.05VccASW 0. 903

3.3VccSPI 0 .01

3.3VccDSW 0 .001

1.8 0.00 2VccDFTERM

3.3VccRTC 6 uA

3.3VccSus3_3

3.3 / 1.5VccSusHDA

0.095

0.01

VccVRM 1.8 / 1.5 0.167

VccSSC 1

1.05VccCLKDMI

.05 0.095

0.07

VccDIFFCLKN 1.05 0.055

VccALVDS 3.3

0.001

1.8VccTX_LVDS 0.04

+1.5VS +VCCAFDI_VRM

Intel reco mmand
stuff R265 and unstu ff R266

R265

12

R_short 0_0603_5%

+VCCAFDI_VRM

VCCVRM==>1.5V FOR MOBILE

CCVRM==>1.8V FOR DESKTOP

V

VCCVRM = 1 60mA detal waiting for newest spec

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUT URE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUT URE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUT URE CENTER.

3

2011/11/01

2011/11/01

2011/11/01

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2012/12/31

2012/12/31

2012/12/31

Title

PCH (7/9) PWR

PCH (7/9) PWR

PCH (7/9) PWR

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Monday, January 14, 2013

Monday, January 14, 2013

Monday, January 14, 2013

Y400S-NM-A141

Y400S-NM-A141

Y400S-NM-A141

1

of

of

of

20 65

20 65

20 65

1.0

1.0

1.0

5

+3VS

R280

12

R_short 0_0603_5%

D D

On-Die PLL Voltage Regulator

H

：

On-Die PLL volt age regulator enable

VCCFDIPLL, VCCAPLLEXP ,VCCAPLLD MI2
,VCCAPLLSA TA

+1.05VS

C C

L5

1 2

BLM18PG181SN1D_0603

L6

1 2

BLM18PG181SN1D_0603

+3VS_VCC_CLKF33

C231

10U_0805_10V4Z

1

2

+1.05VS_VCCA_A_DPL

+1.05VS_VCCA_B_DPL

C250

22U_0805_6.3V6M

1

C251

1U_0402_6.3V6K

1

2

2

C232

1U_0402_6.3V6K

1

+3VALW

2

+1.05VS

+1.05VS

C252

22U_0805_6.3V6M

1

2

R_short 0_0603_5%

R_short 0_0603_5%

1 2

R_short 0_0805_5%

C253

1U_0402_6.3V6K

1

2

R269

R271

R277

Before gerber out change to 22u_0805

0.1U_0402_10V7K

B B

+1.05VS

+1.05VS

+1.05VS

A A

R274

12

R_short 0_0603_5%

R304

12

R_short 0_0603_5%

R284

12

R_short 0_0603_5%

1

C256
1U_0402_6.3V6K

2

1

C259
1U_0402_6.3V6K

2

1

C262
1U_0402_6.3V6K

2

+1.05VS_VCCDIFFCLKN

+1.05VS

R286

R_short 0_0603_5%

0.1U_0402_10V7K

12

4

Have internal VRM

12

12

C258

C263

1

2

1

2

4.7U_0603_6.3V6K

+VCCDPLL_CPY

C244

1U_0402_6.3V6K

1

2

1

2

C265

1

2

+VCCPDSW

1

C234

0.1U_0402_10V7K

2

+3VS_VCC_CLKF33

+VCCSUS1

1

C239

@

1U_0402_6.3V6K

2

+1.05VM_VCCASW

C241

22U_0805_6.3V6M

1

1

2

2

C245

1U_0402_6.3V6K

1

1

2

2

+VCCRTCEXT

+VCCAFDI_VRM

+1.05VS_VCCA_A_DPL

+1.05VS_VCCA_B_DPL

+VCCDIFFCLK

+1.05VS_VCCDIFFCLKN

+1.05VS_SSCVCC

+VCCSST

+V_CPU_IO

C266

0.1U_0402_10V7K

C267

0.1U_0402_10V7K

1

+RTCVCC

2

@

3

2

1

VCC3_3 = 2 66mA detal waiting for newest spec

CCDMI = 42 mA detal w aiting fo r newest s pec

V

U4J

AD49

VCCACLK

T16

VCCDSW3_3

V12

DCPSUSBYP

T38

VCC3_3[5]

BH23

VCCAPLLDMI2

AL29

VCCIO[14]

AL24

DCPSUS[3]

AA19

VCCASW[1]

AA21

VCCASW[2]

AA24

C242

22U_0805_6.3V6M

C246

1U_0402_6.3V6K

0.1U_0402_10V7K

C268

1U_0402_6.3V6K

1

1

2

2

AA26

AA27

AA29

AA31

AC26

AC27

AC29

AC31

AD29

AD31

W21

W23

W24

W26

W29

W31

W33

N16

Y49

BD47

BF47

AF17
AF33
AF34

AG34

AG33

V16

T17
V19

BJ8

A22

C269

C270

0.1U_0402_10V7K

1

@

2

VCCASW[3]

VCCASW[4]

VCCASW[5]

VCCASW[6]

VCCASW[7]

VCCASW[8]

VCCASW[9]

VCCASW[10]

VCCASW[11]

VCCASW[12]

VCCASW[13]

VCCASW[14]

VCCASW[15]

VCCASW[16]

VCCASW[17]

VCCASW[18]

VCCASW[19]

VCCASW[20]

DCPRTC

VCCVRM[4]

VCCADPLLA

VCCADPLLB

VCCIO[7]
VCCDIFFCLKN[1]
VCCDIFFCLKN[2]
VCCDIFFCLKN[3]

VCCSSC

DCPSST

DCPSUS[1]
DCPSUS[2]

V_PROC_IO

VCCRTC

PANTHER-POINT_FCBGA989

POWER

VCCIO[29]

228mA

PCI/GPIO/LPCMISC

SATA USB

HDA

VCCSUS3_3[7]

VCCSUS3_3[8]

VCCSUS3_3[9]

VCCSUS3_3[10]

VCCSUS3_3[6]

1mA

VCCSUS3_3[1]

1mA

VCCSUS3_3[2]

VCCSUS3_3[3]

VCCSUS3_3[4]

VCCSUS3_3[5]

VCCAPLLSATA

VCCASW[22]

VCCASW[23]

VCCASW[21]

10mA

VCCSUSHDA

VCCIO[30]

VCCIO[31]

VCCIO[32]

VCCIO[33]

VCCIO[34]

V5REF_SUS

DCPSUS[4]

V5REF

VCC3_3[1]

VCC3_3[8]

VCC3_3[4]

VCC3_3[2]

VCCIO[5]

VCCIO[12]

VCCIO[13]

VCCIO[6]

VCCVRM[1]

VCCIO[2]

VCCIO[3]

VCCIO[4]

1

mA

903mA

Clock and Miscellaneous

80mA

80mA

55mA

95mA

1mA

CPURTC

N26

P26

P28

T27

T29

T23

T24

V23

V24

P24

T26

M26

AN23

AN24

P34

N20

N22

P20

P22

AA16

W16

T34

AJ2

AF13

AH13

AH14

AF14

AK1

AF11

AC16

AC17

AD17

T21

V21

T19

P32

+1.05VS_VCCAUPLL

+PCH_V5REF_SUS

+VCCA_USBSUS

+3V_VCCPSUS

+PCH_V5REF_RUN

+3V_VCCPSUS

+3VS_VCCPCORE

+3VS_VCCPPCI

+VCC3_3_2

+VCCAFDI_VRM

+1.05VS_VCC_SATA

+1.05VS

+VCCSUSHDA

+1.05VS_VCCUSBCORE

1

C233
1U_0402_6.3V6K

2

+3V_VCCPUSB

C236

0.1U_0402_10V7K

1

+3V_VCCAUBG

2

1

R_short 0_0603_5%

C255

2

0.1U_0402_10V7K

+VCCAFDI_VRM

+1.05VS_VCC_SATA

1

C271

0.1U_0402_16V4Z

2

1

C238

0.1U_0402_10V7K

2

1 2

C243 1U_0402_6.3V6K@

+3VS

R283

12

+1.05VS_SATA3

1

2

R287

R_short 0_0603_5%

R_short 0_0603_5%

R_short 0_0603_5%

R_short 0_0603_5%

R_short 0_0603_5%

1

2

1

2

1

2

+1.05VS_SATA3

1

2

R288

R_short 0_0603_5%

C261
1U_0402_6.3V6K

+3V_PCH

12

R270

12

R272

12

R273

12

R276

12

C247
1U_0402_6.3V

C249

0.1U_0402_10V7K

C254

0.1U_0402_10V7K

C257
1U_0402_6.3V6K

12

+1.05VS

+3V_PCH

+3V_PCH

+1.05VS

+3V_PCH

R278

12

R_short 0_0603_5%

R281

R_short 0_0603_5%

R282

R_short 0_0603_5%

R285

R_short 0_0603_5%

On-Die PLL Voltage Regulator

H

VCCFDIPLL, VCCAPLLEXP ,VCCAPLLD MI2

+1.05VS

,V

+3VS

12

+3VS

12

+1.05VS

12

：

On-Die PLL volt age regulator enable

CCAPLLSATA

R275

10_0402_5%

R279

10_0402_5%

+3V_PCH+5V_PCH

12

+3VS+5VS

12

21

D1
CH751H-40PT_SOD323-2

+PCH_V5REF_SUS

1

C240

0.1U_0603_25V7K

2

21

D2
CH751H-40PT_SOD323-2

+PCH_V5REF_RUN

1

C248
1U_0603_10V6K

2

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUT URE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUT URE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUT URE CENTER.

3

2011/11/01

2011/11/01

2011/11/01

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2012/12/31

2012/12/31

2012/12/31

Title

PCH (8/9) PWR

PCH (8/9) PWR

PCH (8/9) PWR

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Monday, January 14, 2013

Monday, January 14, 2013

Monday, January 14, 2013

Y400S-NM-A141

Y400S-NM-A141

Y400S-NM-A141

1

of

of

of

21 65

21 65

21 65

1.0

1.0

1.0

5

4

3

2

1

U4H

H5

VSS[0]

AA17

VSS[1]

AA2

VSS[2]

AA3

VSS[3]

AA33

D D

C C

B B

A A

VSS[4]

AA34

VSS[5]

AB11

VSS[6]

AB14

VSS[7]

AB39

VSS[8]

AB4

VSS[9]

AB43

VSS[10]

AB5

VSS[11]

AB7

VSS[12]

AC19

VSS[13]

AC2

VSS[14]

AC21

VSS[15]

AC24

VSS[16]

AC33

VSS[17]

AC34

VSS[18]

AC48

VSS[19]

AD10

VSS[20]

AD11

VSS[21]

AD12

VSS[22]

AD13

VSS[23]

AD19

VSS[24]

AD24

VSS[25]

AD26

VSS[26]

AD27

VSS[27]

AD33

VSS[28]

AD34

VSS[29]

AD36

VSS[30]

AD37

VSS[31]

AD38

VSS[32]

AD39

VSS[33]

AD4

VSS[34]

AD40

VSS[35]

AD42

VSS[36]

AD43

VSS[37]

AD45

VSS[38]

AD46

VSS[39]

AD8

VSS[40]

AE2

VSS[41]

AE3

VSS[42]

AF10

VSS[43]

AF12

VSS[44]

AD14

VSS[45]

AD16

VSS[46]

AF16

VSS[47]

AF19

VSS[48]

AF24

VSS[49]

AF26

VSS[50]

AF27

VSS[51]

AF29

VSS[52]

AF31

VSS[53]

AF38

VSS[54]

AF4

VSS[55]

AF42

VSS[56]

AF46

VSS[57]

AF5

VSS[58]

AF7

VSS[59]

AF8

VSS[60]

AG19

VSS[61]

AG2

VSS[62]

AG31

VSS[63]

AG48

VSS[64]

AH11

VSS[65]

AH3

VSS[66]

AH36

VSS[67]

AH39

VSS[68]

AH40

VSS[69]

AH42

VSS[70]

AH46

VSS[71]

AH7

VSS[72]

AJ19

VSS[73]

AJ21

VSS[74]

AJ24

VSS[75]

AJ33

VSS[76]

AJ34

VSS[77]

AK12

VSS[78]

AK3

VSS[79]

PANTHER-POINT_FCBGA989

VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]

VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]

AK38
AK4
AK42
AK46
AK8
AL16
AL17
AL19
AL2
AL21
AL23
AL26
AL27
AL31
AL33
AL34
AL48
AM11
AM14
AM36
AM39
AM43
AM45
AM46
AM7
AN2
AN29
AN3
AN31
AP12
AP19
AP28
AP30
AP32
AP38
AP4
AP42
AP46
AP8
AR2
AR48
AT11
AT13
AT18
AT22
AT26
AT28
AT30
AT32
AT34
AT39
AT42
AT46
AT7
AU24
AU30
AV16
AV20
AV24
AV30
AV38
AV4
AV43
AV8
AW14
AW18
AW2
AW22
AW26
AW28
AW32
AW34
AW36
AW40
AW48
AV11
AY12
AY22
AY28

U4I

AY4

VSS[159]

AY42

VSS[160]

AY46

VSS[161]

AY8

VSS[162]

B11

VSS[163]

B15

VSS[164]

B19

VSS[165]

B23

VSS[166]

B27

VSS[167]

B31

VSS[168]

B35

VSS[169]

B39

VSS[170]

B7

VSS[171]

F45

VSS[172]

BB12

VSS[173]

BB16

VSS[174]

BB20

VSS[175]

BB22

VSS[176]

BB24

VSS[177]

BB28

VSS[178]

BB30

VSS[179]

BB38

VSS[180]

BB4

VSS[181]

BB46

VSS[182]

BC14

VSS[183]

BC18

VSS[184]

BC2

VSS[185]

BC22

VSS[186]

BC26

VSS[187]

BC32

VSS[188]

BC34

VSS[189]

BC36

VSS[190]

BC40

VSS[191]

BC42

VSS[192]

BC48

VSS[193]

BD46

VSS[194]

BD5

VSS[195]

BE22

VSS[196]

BE26

VSS[197]

BE40

VSS[198]

BF10

VSS[199]

BF12

VSS[200]

BF16

VSS[201]

BF20

VSS[202]

BF22

VSS[203]

BF24

VSS[204]

BF26

VSS[205]

BF28

VSS[206]

BD3

VSS[207]

BF30

VSS[208]

BF38

VSS[209]

BF40

VSS[210]

BF8

VSS[211]

BG17

VSS[212]

BG21

VSS[213]

BG33

VSS[214]

BG44

VSS[215]

BG8

VSS[216]

BH11

VSS[217]

BH15

VSS[218]

BH17

VSS[219]

BH19

VSS[220]

H10

VSS[221]

BH27

VSS[222]

BH31

VSS[223]

BH33

VSS[224]

BH35

VSS[225]

BH39

VSS[226]

BH43

VSS[227]

BH7

VSS[228]

D3

VSS[229]

D12

VSS[230]

D16

VSS[231]

D18

VSS[232]

D22

VSS[233]

D24

VSS[234]

D26

VSS[235]

D30

VSS[236]

D32

VSS[237]

D34

VSS[238]

D38

VSS[239]

D42

VSS[240]

D8

VSS[241]

E18

VSS[242]

E26

VSS[243]

G18

VSS[244]

G20

VSS[245]

G26

VSS[246]

G28

VSS[247]

G36

VSS[248]

G48

VSS[249]

H12

VSS[250]

H18

VSS[251]

H22

VSS[252]

H24

VSS[253]

H26

VSS[254]

H30

VSS[255]

H32

VSS[256]

H34

VSS[257]

F3

VSS[258]

PANTHER-POINT_FCBGA989

VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[333]
VSS[334]
VSS[335]
VSS[337]
VSS[338]
VSS[340]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]

H46
K18
K26
K39
K46
K7
L18
L2
L20
L26
L28
L36
L48
M12
P16
M18
M22
M24
M30
M32
M34
M38
M4
M42
M46
M8
N18
P30
N47
P11
P18
T33
P40
P43
P47
P7
R2
R48
T12
T31
T37
T4
W34
T46
T47
T8
V11
V17
V26
V27
V29
V31
V36
V39
V43
V7
W17
W19
W2
W27
W48
Y12
Y38
Y4
Y42
Y46
Y8
BG29
N24
AJ3
AD47
B43
BE10
BG41
G14
H16
T36
BG22
BG24
C22
AP13
M14
AP3
AP1
BE16
BC16
BG28
BJ28

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUT URE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUT URE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUT URE CENTER.

3

2011/11/01

2011/11/01

2011/11/01

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2012/12/31

2012/12/31

2012/12/31

Title

PCH (9/9) VSS

PCH (9/9) VSS

PCH (9/9) VSS

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Monday, January 14, 2013

Monday, January 14, 2013

Monday, January 14, 2013

Y400S-NM-A141

Y400S-NM-A141

Y400S-NM-A141

1

of

of

of

22 65

22 65

22 65

1.0

1.0

1.0

5

PCIE_CTX_GRX_N[0..15]<32,5>

PCIE_CTX_GRX_P[0..15]<32,5>

PCIE_CRX_GTX_N[0..15]<32,5>

PCIE_CRX_GTX_P[0..15]<32,5>

D D

+1.05VS_VGA

180ohms (ESR=0.2) Bead

LV1 BLM18PG181SN1D_2P

1 2

180ohms (ESR=0.2) Bead

+3VS_VGA

RV24

2.2K_0402_5%

VGA_SMB_CK2

VGA_SMB_DA2

C C

B B

A A

1 2

DGPU_HOLD_RST#<18>

DGPU_PWR_EN<18,23,51>

RV25

2.2K_0402_5%

1 2

2N7002DW-T/R7_SOT363-6

2

QV1A

2N7002DW-T/R7_SOT363-6

PLT_RST#<18,32,37,38,44,45,6>

10K_0402_5%

2N7002KW_SOT323-3

GC6@

+3VS_VGA

5

QV1B

3

4

61

PU AT EC SIDE, +3VS AND 4.7K

C1061

0.1U_0402_16V4Z

PLT_RST#

DGPU_HOLD_RST#

NC7SZ08P5X_NL_SC70-5

+3VS

12

RV235

GC6@

AO3413_SOT23-3

13

D

2

G

QV3

S

0.1U_0402_10V7K

5

EC_SMB_CK2 <15,32,40,45>

EC_SMB_DA2 <15,32,40,45>

+3VS

1

2

5

UV2

2

P

B

Y

1

A

G

3

R1495

@

1 2

QV2

2

G

GC6@

1

CV148

2

GC6@

RV237

10K_0402_5%

@

4

0_0402_5%

FB_CLAMP_MON

0_0402_5%

GC6@

13

D

10K_0402_5%

GC6@

S

For GC6

12

PLT_RST_VGA#

RV111
10K_0402_5%

1 2

RV238

RV236

FB_CLAMP <23,27,45>

PCIE_CTX_GRX_N[0..15]

PCIE_CTX_GRX_P[0..15]

PCIE_CRX_GTX_N[0..15]

PCIE_CRX_GTX_P[0..15]

Under GPU(below 150mils)

1

CV112

2

22U_0805_6.3V6M

PCIE_CRX_GTX_P7
PCIE_CRX_GTX_N7
PCIE_CRX_GTX_P6
PCIE_CRX_GTX_N6
PCIE_CRX_GTX_P5
PCIE_CRX_GTX_N5
PCIE_CRX_GTX_P4
PCIE_CRX_GTX_N4
PCIE_CRX_GTX_P3
PCIE_CRX_GTX_N3
PCIE_CRX_GTX_P2
PCIE_CRX_GTX_N2
PCIE_CRX_GTX_P1 PCIE_CRX_C_GTX_P1
PCIE_CRX_GTX_N1
PCIE_CRX_GTX_P0
PCIE_CRX_GTX_N0

Differential signal

1 2

12

DGPU_PWR_EN<18,23,51>

4

1

1

CV4

CV113

2

2

0.1U_0402_10V7K

0.1U_0402_10V7K

4.7U_0402_6.3V6M

1 2

CV24 0.22U_0402_10V6K

1 2

CV26 0.22U_0402_10V6K

1 2

CV21 0.22U_0402_10V6K

1 2

CV23 0.22U_0402_10V6K

1 2

CV25 0.22U_0402_10V6K

1 2

CV27 0.22U_0402_10V6K

1 2

CV29 0.22U_0402_10V6K

1 2

CV31 0.22U_0402_10V6K

1 2

CV33 0.22U_0402_10V6K

1 2

CV28 0.22U_0402_10V6K

1 2

CV30 0.22U_0402_10V6K

1 2

CV32 0.22U_0402_10V6K

1 2

CV36 0.22U_0402_10V6K

1 2

CV41 0.22U_0402_10V6K

1 2

CV34 0.22U_0402_10V6K

1 2

CV35 0.22U_0402_10V6K

CLK_REQ_GPU#_R<15>

4

1

CV5

2

CLK_PCIE_VGA<15>

CLK_PCIE_VGA#<15>

RV231

10K_0402_5%

150mA

+SP_PLLVDD

1 2

@

RV20 200_0402_1%

1 2

RV22 2.49K_0402_1%

+3VS_VGA

1 2

12

2

QV16

1 3

D

2N7002H 1N_SOT23-3

@

1 2

RV233 0_0402_5%

PCIE_CTX_GRX_P7
PCIE_CTX_GRX_N7
PCIE_CTX_GRX_P6
PCIE_CTX_GRX_N6
PCIE_CTX_GRX_P5
PCIE_CTX_GRX_N5
PCIE_CTX_GRX_P4
PCIE_CTX_GRX_N4
PCIE_CTX_GRX_P3
PCIE_CTX_GRX_N3
PCIE_CTX_GRX_P2
PCIE_CTX_GRX_N2
PCIE_CTX_GRX_P1
PCIE_CTX_GRX_N1
PCIE_CTX_GRX_P0
PCIE_CTX_GRX_N0

RV230

10K_0402_5%

@

G

S

PCIE_CRX_C_GTX_P7
PCIE_CRX_C_GTX_N7
PCIE_CRX_C_GTX_P6
PCIE_CRX_C_GTX_N6
PCIE_CRX_C_GTX_P5
PCIE_CRX_C_GTX_N5
PCIE_CRX_C_GTX_P4
PCIE_CRX_C_GTX_N4
PCIE_CRX_C_GTX_P3
PCIE_CRX_C_GTX_N3
PCIE_CRX_C_GTX_P2
PCIE_CRX_C_GTX_N2

PCIE_CRX_C_GTX_N1
PCIE_CRX_C_GTX_P0
PCIE_CRX_C_GTX_N0

CLK_PCIE_VGA
CLK_PCIE_VGA#

CLK_REQ_GPU#

PEX_TSTCLK_OUT
PEX_TSTCLK_OUT#

PLT_RST_VGA#

PEX_TERMP

+3VS_VGA

RV32
10K_0402_5%

1 2

RV232

@

10K_0402_5%

1 2

AN12
AM12
AN14
AM14

AP14

AP15
AN15
AM15
AN17
AM17

AP17

AP18
AN18
AM18
AN20
AM20

AP20

AP21
AN21
AM21
AN23
AM23

AP23

AP24
AN24
AM24
AN26
AM26

AP26

AP27
AN27
AM27

AK14

AJ14
AH14
AG14

AK15

AJ15

AL16

AK16

AK17

AJ17
AH17
AG17

AK18

AJ18

AL19

AK19

AK20

AJ20
AH20
AG20

AK21

AJ21

AL22

AK22

AK23

AJ23
AH23
AG23

AK24

AJ24

AL25

AK25

AJ11

AL13

AK13

AK12

AJ26

AK26

AJ12

AP29

N14P_FCBGA908

CLK_REQ_GPU#

3

UV1A

CV37

27P_0402_50V8J

Part 1 of 7

GPIO10
GPIO11
GPIO12
GPIO13
GPIO14

GPIO

GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21

DACA_RED

DACA_GREEN

DACA_BLUE

DACA_HSYNC

DACA_VSYNC

DACs

DACA_VDD
DACA_VREF
DACA_RSET

I2CA_SCL

PCI EXPRESS

I2CA_SDA

I2CB_SCL
I2CB_SDA

I2CC_SCL

I2C

I2CC_SDA

I2CS_SCL
I2CS_SDA

PLLVDD

SP_PLLVDD

VID_PLLVDD

XTAL_IN

CLK

XTAL_OUT

XTAL_OUTBUFF

XTAL_SSIN

GT@

4

1

XTAL_IN

27MHZ 16PF +-30PPM X3G027000FG1H-HX

1

2

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9

1 2

YV1

NC

OSC

PEX_RX0
PEX_RX0_N
PEX_RX1
PEX_RX1_N
PEX_RX2
PEX_RX2_N
PEX_RX3
PEX_RX3_N
PEX_RX4
PEX_RX4_N
PEX_RX5
PEX_RX5_N
PEX_RX6
PEX_RX6_N
PEX_RX7
PEX_RX7_N
PEX_RX8
PEX_RX8_N
PEX_RX9
PEX_RX9_N
PEX_RX10
PEX_RX10_N
PEX_RX11
PEX_RX11_N
PEX_RX12
PEX_RX12_N
PEX_RX13
PEX_RX13_N
PEX_RX14
PEX_RX14_N
PEX_RX15
PEX_RX15_N

PEX_TX0
PEX_TX0_N
PEX_TX1
PEX_TX1_N
PEX_TX2
PEX_TX2_N
PEX_TX3
PEX_TX3_N
PEX_TX4
PEX_TX4_N
PEX_TX5
PEX_TX5_N
PEX_TX6
PEX_TX6_N
PEX_TX7
PEX_TX7_N
PEX_TX8
PEX_TX8_N
PEX_TX9
PEX_TX9_N
PEX_TX10
PEX_TX10_N
PEX_TX11
PEX_TX11_N
PEX_TX12
PEX_TX12_N
PEX_TX13
PEX_TX13_N
PEX_TX14
PEX_TX14_N
PEX_TX15
PEX_TX15_N

PEX_WAKE_N

PEX_REFCLK
PEX_REFCLK_N
PEX_CLKREQ_N

PEX_TSTCLK_OUT
PEX_TSTCLK_OUT_N

PEX_RST_N
PEX_TERMP

20120816 --> CV37, CV38 change to 27pf

3

P6

FB_CLAMP_MON

M3
L6
P5
P7
L7
M7
N8
M1
M2
L1
M5
N3
M4
N4
P2
R8
M6
R1
P3
P4
P1

AK9
AL10
AL9

AM9
AN9

AG10
AP9
AP8

R4
R5

R7
R6

R2
R3

T4
T3

AD8

AE8

AD7

H3
H2

J4
H1

RV138 0_0402_5%

VGA_BL_PWM
VGA_ENVDD
VGA_ENBKL

FB_CLAMP_TOGGLE_REQ#

OVERT#
VGA_ALERT#

NVVDD PWM_VID

DPRSLPVR_VGA

DGPU_HDMI_HPD

VGA_AC_DET_R

VGA_CRT_R
VGA_CRT_G
VGA_CRT_B

VGA_CRT_HSYNC
VGA_CRT_VSYNC

+DACA_VDD
+DACA_VREF
DACA_RSET

VGA_CRT_CLK
VGA_CRT_DATA

I2CB_SCL
I2CB_SDA

VGA_EDID_CLK
VGA_EDID_DATA

VGA_SMB_CK2
VGA_SMB_DA2

60mA

+PLLVDD

RV112 0_0402_5%@

45

mA

45mA

XTAL_IN

XTAL_OUT

XTALOUT

XTALSSIN

Internal Thermal Sensor

RV23 10M_0402_5%

3

XTAL_OUT

OSC

2

NC

CV38

27P_0402_50V8J

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF LC FU TURE CENTER. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF LC FU TURE CENTER. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF LC FU TURE CENTER. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENTER.

@

1 2

VGA_BL_PWM <34>
VGA_ENVDD <34>
VGA_ENBKL <34>

NVVDD PWM_VID <58>

RB751V-40_SOD323-2

VGA_CRT_CLK <35>

VGA_CRT_DATA <35>

VGA_EDID_CLK <34>

VGA_EDID_DATA <34>

1 2

1 2

1

2

VGA_AC_DET_R

DPRSLPVR_VGA <58>

DGPU_HDMI_HPD <36>

DV2

12

V

endor recommand reserve PU/PD resistor

VGA_CRT_R <35>
VGA_CRT_G <35>
VGA_CRT_B <35>

VGA_CRT_HSYNC <35>
VGA_CRT_VSYNC <35>

RV107

124_0402_1%

SLI@

+SP_PLLVDD

12

RV2610K_0402_5%

RV27

10K_0402_5%

2011/11/01

2011/11/01

2011/11/01

2

FB_CLAMP <23,27,45>

VGA_AC_DET_R <32>

VGA_AC_DET <45>

12

CV130

SLI@12

0.1U_0402_10V7K

CRT

LVDS

120mA

+DACA_VDD

+PLLVDD

Under GPU Near GPU

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

2

+3VS_VGA

RV65

@

10K_0402_5%

1 2

MEM_VREF <28,29,30,31>

12

RV223

FB_CLAMP_TOGGLE_REQ#

OVERT#

10K_0402_5%

PLT_RST_VGA#

+3VS_VGA

RV52
10K_0402_5%

1 2

S

2N7002KW_SOT323-3

GPIO 14 of GPU connect to PCH GPIO 0

SLI@

VGA_BL_PWM

12

RV16 10K_0402_5%

Close to GPU

SLI@

VGA_CRT_R

VGA_CRT_G

VGA_CRT_B

1 2

RV106 150_0402_1%

SLI@

1 2

RV108 150_0402_1%

SLI@

1 2

RV109 150_0402_1%

Under GPU Near GPU

1

CV125

@

2

0.1U_0402_10V7K

1

2

0.1U_0402_10V7K

Deciphered Date

Deciphered Date

Deciphered Date

1

CV126

@

0.1U_0402_10V7K

CV40

1

CV139

2

2

SLI@

0.1U_0402_10V7K

LV7

1 2

R_short 0_0402_5%

2012/12/31

2012/12/31

2012/12/31

CV122

SLI@

1

2

0.1U_0402_10V7K

1

CV131

2

22U_0805_6.3V6M

1

+3VS_VGA

12

RV208
10K_0402_5%

61

QV7A
DMN66D0LDW-7 2N_SOT363-6

2

13

D

2

G

S

G

2

QV6

13

D

1

CV127

2

SLI@

1U_0402_6.3V6K

PCH_THRMTRIP#_R

3

QV7B
DMN66D0LDW-7 2N_SOT363-6

5

4

QV5
2N7002KW_SOT323-3

2012-0418 --> Stuff QV7, RV208
2012-0429 --> Add QV5, C3 8 has abnormal shutdown issue

PLT_RST_VGA#

+3VALW

GC6@

RV53
10K_0402_5%

1 2

1

CV128

2

SLI@

4.7U_0603_6.3V6K

+1.05VS_VGA

Title

Title

Title

N14P-PCIE/DAC/GPIO

N14P-PCIE/DAC/GPIO

N14P-PCIE/DAC/GPIO

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Monday, January 14, 2013

Monday, January 14, 2013

Monday, January 14, 2013

Date: Sheet of

Date: Sheet of

Date: Sheet

GC6_EVENT# <19,32,45>

VGA_ALERT#

VGA_EDID_CLK

VGA_EDID_DATA

VGA_CRT_DATA

VGA_CRT_CLK

I2CB_SCL

I2CB_SDA

OVERT#

VGA_AC_DET_R

2

1 2

RV15 2.2K_0402_5%

1 2

RV4 2.2K_0402_5%

1 2

RV7 2.2K_0402_5%

1 2

RV10 2.2K_0402_5%

1 2

RV11 2.2K_0402_5%

1 2

RV12 2.2K_0402_5%

1 2

RV13 2.2K_0402_5%

1 2

RV1 10K_0402_5%

1 2

RV2 10K_0402_5%

20 ohms @100MHz (ESR=0.05)

LV5

SLI@

12

BLM18PG181SN1D_0603

CV126

10K_0402_5%

OPT@

Y400S-NM-A141

Y400S-NM-A141

Y400S-NM-A141

1

PCH_THRMTRIP#_R <19,32>

+3VS_VGA

+3VS_VGA

of

23 65

23 65

23 65

1.0

1.0

1.0

5

VGA_TXCLK+<34>
VGA_TXCLK-<34>

VGA_TXOUT0+<34>

VGA_TXOUT0-<34>

VGA_TXOUT1+<34>

VGA_TXOUT1-<34>

VGA_TXOUT2+<34>

VGA_TXOUT2-<34>

D D

for 15" dual channel

C C

VGA_HDMI_TX2+<36>

VGA_HDMI_TX2-<36>

VGA_HDMI_TX1+<36>

VGA_HDMI_TX1-<36>

VGA_HDMI_TX0+<36>

VGA_HDMI_TX0-<36>

VGA_HDMI_CLK+<36>

VGA_HDMI_CLK-<36>

B B

+3VS_VGA

SLI@

1 2

RV113 4.7K_0402_5%

SLI@

1 2

RV114 4.7K_0402_5%

HDMI

VGA_HDMI_DATA

VGA_HDMI_CLK<36>
VGA_HDMI_DATA<36>

4

VGA_TXCLK+
VGA_TXCLK­VGA_TXOUT0+
VGA_TXOUT0­VGA_TXOUT1+
VGA_TXOUT1­VGA_TXOUT2+
VGA_TXOUT2-

VGA_HDMI_TX2+

VGA_HDMI_TX2-

VGA_HDMI_TX1+

VGA_HDMI_TX1-

VGA_HDMI_TX0+

VGA_HDMI_TX0-

VGA_HDMI_CLK+

VGA_HDMI_CLK-

VGA_HDMI_CLKVGA_HDMI_CLK
VGA_HDMI_DATA

UV1D

AM6

IFPA_TXC

AN6

IFPA_TXC_ N

AP3

IFPA_TXD0

AN3

IFPA_TXD0 _N

AN5

IFPA_TXD1

AM5

IFPA_TXD1 _N

AL6

IFPA_TXD2

AK6

IFPA_TXD2 _N

AJ6

IFPA_TXD3

AH6

IFPA_TXD3 _N

AJ9

IFPB_TXC

AH9

IFPB_TXC_ N

AP6

IFPB_TXD4

AP5

IFPB_TXD4 _N

AM7

IFPB_TXD5

AL7

IFPB_TXD5 _N

AN8

IFPB_TXD6

AM8

IFPB_TXD6 _N

AK8

IFPB_TXD7

AL8

IFPB_TXD7 _N

AK1

IFPC_L0

AJ1

IFPC_L0_N

AJ3

IFPC_L1

AJ2

IFPC_L1_N

AH3

IFPC_L2

AH4

IFPC_L2_N

AG5

IFPC_L3

AG4

IFPC_L3_N

AM1

IFPD_L0

AM2

IFPD_L0_N

AM3

IFPD_L1

AM4

IFPD_L1_N

AL3

IFPD_L2

AL4

IFPD_L2_N

AK4

IFPD_L3

AK5

IFPD_L3_N

AD2

IFPE_L0

AD3

IFPE_L0_N

AD1

IFPE_L1

AC1

IFPE_L1_N

AC2

IFPE_L2

AC3

IFPE_L2_N

AC4

IFPE_L3

AC5

IFPE_L3_N

AE3

IFPF_L0

AE4

IFPF_L0_N

AF4

IFPF_L1

AF5

IFPF_L1_N

AD4

IFPF_L2

AD5

IFPF_L2_N

AG1

IFPF_L3

AF1

IFPF_L3_N

AG3

IFPC_AUX_ I2CW _SCL

AG2

IFPC_AUX_ I2CW _SDA_N

AK3

IFPD_AUX_ I2CX_SCL

AK2

IFPD_AUX_ I2CX_SDA _N

AB3

IFPE_AUX_ I2CY_SCL

AB4

IFPE_AUX_ I2CY_SDA_N

AF3

IFPF_AUX_ I2CZ_SC L

AF2

IFPF_AUX_ I2CZ_SD A_N

Part 4 of 7

VDD_SEN SE

GND_SEN SE

TEST

JTAG_TR ST_N

SERIAL

LVDS/TMDS

GENERAL

MULTI_STR AP_REF0_GND

3

NC

TESTMOD E

JTAG_TC K

JTAG_TD I
JTAG_TD O
JTAG_TM S

ROM_CS_ N
ROM_SCL K

ROM_SI

ROM_SO

BUFRST_ N

CEC

STRAP0
STRAP1
STRAP2
STRAP3
STRAP4

THERMDP

THERMDN

P8

NC

AC6

NC

AJ28

NC

AJ4

NC

AJ5

NC

AL11

NC

C15

NC

D19

NC

D20

NC

D23

NC

D26

NC

H31

NC

T8

NC

V32

NC

L4

VCCSENSE_VGA

L5

VSSSENSE_VGA

AK11

AM10
AM11
AP12
AP11
AN11

H6
H4
H5
H7

RV35 10K_0402_5%

L2

L3

J1

J2
J7
J6
J5
J3

K3
K4

VCCSENSE_VGA <58>

TV2
TV3
TV4
TV5

12

VSSSENSE_VGA <58>

ROM_SCLK <33>
ROM_SI <33>
ROM_SO <33>

STRAP0 <33>
STRAP1 <33>
STRAP2 <33>
STRAP3 <33>
STRAP4 <33>

trace width: 16mils
differential voltage sensing.
differential signal routing.

TESTMODE

1 2

RV34 10K_0402_5%

ROM_CS#
ROM_SCLK
ROM_SI
ROM_SO

1 2

RV38 40.2K_0402_1%

STRAP0
STRAP1
STRAP2
STRAP3
STRAP4

12

10K_0402_5%
RV33

2

1

N14P_FCBGA908

CV295

12

0.1U_0402_16V4Z

ROM_CS#

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2011/11/01

2011/11/01

2011/11/01

3

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

@

@

RV224 0_0402_5%

1 2
1 2

RV226 0_0402_5%

@

Deciphered Date

Deciphered Date

Deciphered Date

1MB SPI ROM FOR VBIOS ROM (SLI)

+3VS_VGA

20mils

12

@

RV229

10K_0402_5%

ROM_CS#_R

2012/12/31

2012/12/31

2012/12/31

2

@

UV15

1

CS#

2

HOLD#

DO

3

WP#

4

GND

MX25L1005AMC-12G SOP

12

@

RV225
10K_0402_5%

8

VCC

7

ROM_HOLD#ROM_SO_RROM_SO

6

CLK

5

DIO

ROM_SCLK_R
ROM_SI_R

Title

Title

Title

N14P-LVDS/HDMI/DP/THM

N14P-LVDS/HDMI/DP/THM

N14P-LVDS/HDMI/DP/THM

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

@

RV228 0_0402_5%

1 2
1 2

RV227 0_0402_5%

@

Y400S-NM-A141

Y400S-NM-A141

Monday, January 14, 2013

Monday, January 14, 2013

Monday, January 14, 2013

Y400S-NM-A141

ROM_SCLK
ROM_SI

1

24 65

24 65

24 65

of

of

of

1.0

1.0

1.0

5

4

3

2

1

+1.5VS_VGA

D D

+1.5VS_VGA

1

CV277

2

1U_0402_6.3V6K

C C

B B

+3VS_VGA

A A

300ohms @100MHz (ESR=0.25)
P

/N: SM010031680

CV147

OPT@

220ohms @100MHz (ESR=0.05)

+1.05VS_VGA

CV172

OPT@

For GDDR5 setti ng. Near GPU

1

1

2

4.7U_0603_6.3V6K

1

CV264

CV263

2

2

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

1

1

CV267

CV266

CV265

2

2

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

Under GPU(below 150mils)

1

1

1

CV282

CV281

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

CV278

CV279

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

VDDQ_SENSE<55>

CALIBRATION PIN

FB_CAL_x_PD_VDDQ

FB_CAL_x_PU_GND

FB_CAL_xTERM_GND

LV9

BLM18PG181SN1D_0603

10K_0402_5%

10K_0402_5%

12

SLI@

LV10

12

BLM18PG181SN1D_0603

SLI@

4.7U_0603_6.3V6K

SLI@

1

1

2

4.7U_0603_6.3V6K

SLI@

CV147

CV149

2

1U_0402_6.3V6K

SLI@

1

1

CV152

2

2

1U_0402_6.3V6K

SLI@

4.7U_0603_6.3V6K

0.1U_0402_10V7K

SLI@

1

2

1

CV280

2

1

2

2

2

CV268

CV269

1

1

10U_0603_6.3V6M

10U_0603_6.3V6M

1

CV292

2

0.1U_0402_10V7K

0.1U_0402_10V7K

1

1

CV173

CV171

0.1U_0402_10V7K

SLI@

2

2

0.1U_0402_10V7K

SLI@

Place near ball s

CV172

0.1U_0402_10V7K

SLI@

2

2

0.1U_0402_10V7K

SLI@

1

1

CV158

CV153

Place near ball s

2

2

CV270

CV271

1

1

10U_0603_6.3V6M

10U_0603_6.3V6M

1

1

CV294

CV287

2

2

0.1U_0402_10V7K

1

CV272

2

22U_0805_6.3V6M

1

2

0.1U_0402_10V7K

1 2

R_short 0_0402_5%

1 2

R_short 0_0402_5%

+1.5VS_VGA

CV273

CV284

1

2

22U_0805_6.3V6M

0.1U_0402_10V7K

RV141

RV142

GDDR5

40.2Ohm

40.2Ohm

60.4Ohm

220mA

+IFPEF_PLLVDD

CV150

570mA

+IFPE_IOVDD +IFPAB_IOVDD

+1.05VS_VGA

+3VS_VGA

CV176

OPT@

P

BLM18PG181SN1D_0603

10K_0402_5%

1

1

2

22U_0805_6.3V6M

CV285

0.1U_0402_10V7K

1 2

1 2

1 2

CV276

CV275

2

22U_0805_6.3V6M

1

CV286

2

FB_VDDQ_SENSE

FB_VSS_SENSE

CV274

1

2

RV6 40.2_0402_1%

RV8 40.2_0402_1%

RV9 60.4_0402_1%

lace near balls

120ohms @100MHz (ESR=0.18)

/N:SM01000BZ00

P

CV140

10K_0402_5%

OPT@

80ohms @100MHz (ESR=0.2)

1
P/N: SM01003071 0

LV4

SLI@

LV6

BLM18PG181SN1D_0603

SLI@

12

1

CV156

2

SLI@

4.7U_0603_6.3V6K

3.5A

12

UV1E

AA27

FBVDDQ_0

AA30

FBVDDQ_1

AB27

FBVDDQ_2

AB33

FBVDDQ_3

AC27

FBVDDQ_4

AD27

FBVDDQ_5

AE27

FBVDDQ_6

AF27

FBVDDQ_7

AG27

FBVDDQ_8

B13

FBVDDQ_9

B16

FBVDDQ_10

B19

FBVDDQ_11

E13

FBVDDQ_12

E16

FBVDDQ_13

E19

FBVDDQ_14

H10

FBVDDQ_15

H11

FBVDDQ_16

H12

FBVDDQ_17

H13

FBVDDQ_18

H14

FBVDDQ_19

H15

FBVDDQ_20

H16

FBVDDQ_21

H18

FBVDDQ_22

H19

FBVDDQ_23

H20

FBVDDQ_24

H21

FBVDDQ_25

H22

FBVDDQ_26

H23

FBVDDQ_27

H24

FBVDDQ_28

H8

FBVDDQ_29

H9

FBVDDQ_30

L27

FBVDDQ_31

M27

FBVDDQ_32

N27

FBVDDQ_33

P27

FBVDDQ_34

R27

FBVDDQ_35

T27

FBVDDQ_36

T30

FBVDDQ_37

T33

FBVDDQ_38

V27

FBVDDQ_39

W27

FBVDDQ_40

W30

FBVDDQ_41

W33

FBVDDQ_42

Y27

FBVDDQ_43

F1

FB_VDDQ_SENSE

F2

FB_GND_SENSE

J27

FB_CAL_PD_VDDQ

H27

FB_CAL_PU_GND

H25

FB_CAL_TERM_GND

N14P_FCBGA908

1

CV146

2

SLI@

4.7U_0603_6.3V6K

1

CV176

2

0.1U_0402_10V7K

1U_0402_6.3V6K

SLI@

SLI@

Place near ball s

Part 5 of 7

200mA

1

1

CV140

2

2

0.1U_0402_10V7K

1U_0402_6.3V6K

SLI@

SLI@

Place near ball s

IFPA_IOVDD and

1

1

2

IFPB_IOVDD comb ined

CV197

CV216

2

0.1U_0402_10V7K

SLI@

PEX_IOVDD_0
PEX_IOVDD_1
PEX_IOVDD_2
PEX_IOVDD_3
PEX_IOVDD_4
PEX_IOVDD_5

PEX_IOVDDQ_0
PEX_IOVDDQ_1
PEX_IOVDDQ_2
PEX_IOVDDQ_3
PEX_IOVDDQ_4
PEX_IOVDDQ_5
PEX_IOVDDQ_6
PEX_IOVDDQ_7
PEX_IOVDDQ_8

PEX_IOVDDQ_9
PEX_IOVDDQ_10
PEX_IOVDDQ_11
PEX_IOVDDQ_12
PEX_IOVDDQ_13

PEX_PLL_HVDD

PEX_SVDD_3V3

POWER

PEX_PLLVDD

IFPAB_PLLVDD

IFPAB_RSET

IFPA_IOVDD
IFPB_IOVDD

IFPC_PLLVDD

IFPC_RSET

IFPC_IOVDD

IFPD_PLLVDD

IFPD_RSET

IFPD_IOVDD

IFPEF_PLVDD

IFPEF_RSET

IFPE_IOVDD
IFPF_IOVDD

+IFPAB_PLLVDD

CV141

VDD33_0
VDD33_1
VDD33_2
VDD33_3

2000mA

AG19
AG21
AG22
AG24
AH21
AH25

AG13
AG15
AG16
AG18
AG25
AH15
AH18
AH26
AH27
AJ27
AK27
AL27
AM28
AN28

AH12

AG12

AG26

J8
K8
L8
M8

AH8

+IFPAB_PLLVDD

AJ8

AG8

+IFPAB_IOVDD

AG9

AF7

+IFPC_PLLVDD

AF8

AF6

+IFPC_IOVDD

AG7

+IFPD_PLLVDD

AN2

AG6

+IFPD_IOVDD

AB8

+IFPEF_PLLVDD

AD6

AC7

+IFPE_IOVDD

AC8

1

1

CV43

2

1U_0402_6.3V6K

Under GPU(below 150mils)

1

CV54

2

22U_0805_6.3V6M

+PEX_PLLVDD

1

CV44

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

CV53

2

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

2

0.1U_0402_10V7K

S3 off --> +3VS, +3VS_VGA, +VDD33MISC

+VDD33

NV Check

RV401K_0402_1%

@

@

1 2

RV4210K_0402_5%

@

1 2

1 2

@

1 2

@

RV431K_0402_1%

@

RV4410K_0402_5%

RV4510K_0402_5%

RV461K_0402_1%

@

RV4710K_0402_5%

RV501K_0402_1%

Near GPU

1

1

CV45

1U_0402_6.3V6K

CV56

22U_0805_6.3V6M

CV70

4.7U_0603_6.3V6K

12

12

12

12

CV47

CV46

2

2

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

+1.05VS_VGA

1

CV55

2

1

1

CV73

CV74

2

2

4.7U_0603_6.3V6K

Under GPU(below 150mils)

IFPAB & IFPEF have to use

+PEX_PLLVDD

2

1

CV48

2

+3VS_VGA

0.1U_0402_10V7K

Place near ball s

2

CV49

1

1

10U_0603_6.3V6M

10U_0603_6.3V6M

1

1

CV111

CV109

2

2

0.1U_0402_10V7K

1

2

0.1U_0402_10V7K

Place near ball s

2

CV51

CV50

1

10U_0603_6.3V6M

10U_0603_6.3V6M

Place near GPU

1

1

CV293

2

2

4.7U_0603_6.3V6K

1U_0402_6.3V6K

120mA

1

1

CV3

CV65

2

2

1U_0603_10V6K

4.7U_0805_25V6-K

2

1

CV75

CV66

+1.05VS_VGA

CV52

R_short 0_0603_5%

RV5

12

LV2

R_short 0_0603_5%

+3VS_VGA

+1.05VS_VGA

12

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2011/11/01

2011/11/01

2011/11/01

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2012/12/31

2012/12/31

2012/12/31

Title

N14P-POWER

N14P-POWER

N14P-POWER

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Monday, January 14, 2013

Monday, January 14, 2013

Monday, January 14, 2013

Date: Sheet

Date: Sheet

Date: Sheet

Y400-LA8691P

Y400-LA8691P

Y400-LA8691P

1

25 65

25 65

25 65

of

of

of

1.0

1.0

1.0

5

4

3

2

1

UV1F

A2
AA17
AA18
AA20
AA22
AB12
AB14
AB16
AB19

AB21

AB23
AB28
AB30
AB32

AC13
AC15
AC17
AC18
AA13
AC20
AC22

AE28
AE30
AE32
AE33

AH10
AA15
AH13
AH16
AH19

AH2
AH22
AH24
AH28
AH29
AH30
AH32
AH33

AH5

AH7

AK10

AL12
AL14
AL15
AL17
AL18

AL20
AL21
AL23
AL24
AL26
AL28
AL30
AL32
AL33

AM13
AM16
AM19
AM22
AM25

AN1
AN10
AN13
AN16
AN19
AN22
AN25
AN30
AN34

AN4

AN7

AP33

4

AB2

A33

AB5
AB7

AE2

AE5
AE7

AJ7

AK7

AL2

AL5

AP2

B1
B10
B22
B25
B28
B31
B34

B4

B7
C10
C13
C19
C22
C25
C28

C7

N14P_FCBGA908

AA12
AA14
AA16
AA19
AA21
AA23
AB13
AB15
AB17
AB18
AB20
AB22
AC12
AC14
AC16
AC19
AC21
AC23

UV1G

Part 7 of 7

VDD_0
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
VDD_10
VDD_11
VDD_12
VDD_13
VDD_14
VDD_15
VDD_16
VDD_17

M12

VDD_18

M14

VDD_19

M16

VDD_20

M19

VDD_21

M21

VDD_22

M23

VDD_23

N13

VDD_24

N15

VDD_25

N17

VDD_26

N18

VDD_27

N20

VDD_28

N22

VDD_29

P12

VDD_30

P14

VDD_31

P16

VDD_32

P19

VDD_33

P21

VDD_34

P23

VDD_35

R13

VDD_36

R15

VDD_37

R17

VDD_38

R18

VDD_39

R20

VDD_40

R22

VDD_41

T12

VDD_42

T14

VDD_43

T16

VDD_44

T19

VDD_45

T21

VDD_46

T23

VDD_47

U13

VDD_48

U15

VDD_49

U17

VDD_50

U18

VDD_51

U20

VDD_52

U22

VDD_53

V13

VDD_54

V15

VDD_55

N14

P_FCBGA908

5

POWER

VDD_56
VDD_57
VDD_58
VDD_59
VDD_60
VDD_61
VDD_62
VDD_63
VDD_64
VDD_65
VDD_66
VDD_67
VDD_68
VDD_69
VDD_70
VDD_71

XVDD_1
XVDD_2
XVDD_3
XVDD_4
XVDD_5
XVDD_6
XVDD_7
XVDD_8

XVDD_9
XVDD_10
XVDD_11
XVDD_12
XVDD_13
XVDD_14
XVDD_15
XVDD_16

XVDD_17
XVDD_18
XVDD_19
XVDD_20
XVDD_21
XVDD_22

XVDD_23
XVDD_24
XVDD_25
XVDD_26
XVDD_27
XVDD_28
XVDD_29
XVDD_30

XVDD_31
XVDD_32
XVDD_33
XVDD_34
XVDD_35
XVDD_36
XVDD_37
XVDD_38

+VGA_CORE

D D

C C

B B

A A

V17
V18
V20
V22
W12
W14
W16
W19
W21
W23
Y13
Y15
Y17
Y18
Y20
Y22

U1
U2
U3
U4
U5
U6
U7
U8

V1
V2
V3
V4
V5
V6
V7
V8

W2
W3
W4
W5
W7
W8

Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8

AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8

+VGA_CORE

GND_0
GND_1
GND_2
GND_3
GND_4
GND_5
GND_6
GND_7
GND_8
GND_9
GND_10
GND_11
GND_12
GND_13
GND_14
GND_15
GND_16
GND_17
GND_18
GND_19
GND_20
GND_21
GND_22
GND_23
GND_24
GND_25
GND_26
GND_27
GND_28
GND_29
GND_30
GND_31
GND_32
GND_33
GND_34
GND_35
GND_36
GND_37
GND_38
GND_39
GND_40
GND_41
GND_42
GND_43
GND_44
GND_45
GND_46
GND_47
GND_48
GND_49
GND_50
GND_51
GND_52
GND_53
GND_54
GND_55
GND_56
GND_57
GND_58
GND_59
GND_60
GND_61
GND_62
GND_63
GND_64
GND_65
GND_66
GND_67
GND_68
GND_69
GND_70
GND_71
GND_72
GND_73
GND_74
GND_75
GND_76
GND_77
GND_78
GND_79
GND_80
GND_81
GND_82
GND_83
GND_84
GND_85
GND_86
GND_87
GND_88
GND_89
GND_90
GND_91
GND_92
GND_93
GND_94
GND_95
GND_96
GND_97
GND_98
GND_99

Part 6 of 7

GND

GND_100
GND_101
GND_102
GND_103
GND_104
GND_105
GND_106
GND_107
GND_108
GND_109
GND_110
GND_111
GND_112
GND_113
GND_114
GND_115
GND_116
GND_117
GND_118
GND_119
GND_120
GND_121
GND_122
GND_123
GND_124
GND_125
GND_126
GND_127
GND_128
GND_129
GND_130
GND_131
GND_132
GND_133
GND_134
GND_135
GND_136
GND_137
GND_138
GND_139
GND_140
GND_141
GND_142
GND_143
GND_144
GND_145
GND_146
GND_147
GND_148
GND_149
GND_150
GND_151
GND_152
GND_153
GND_154
GND_155
GND_156
GND_157
GND_158
GND_159
GND_160
GND_161
GND_162
GND_163
GND_164
GND_165
GND_166
GND_167
GND_168
GND_169
GND_170
GND_171
GND_172
GND_173
GND_174
GND_175
GND_176
GND_177
GND_178
GND_179
GND_180
GND_181
GND_182
GND_183
GND_184
GND_185
GND_186
GND_187
GND_188
GND_189
GND_190
GND_191
GND_192
GND_193
GND_194
GND_195
GND_196
GND_197
GND_198

GND_199
GND_OPT
GND_OPT

D2
D31
D33
E10
E22
E25
E5
E7
F28
F7
G10
G13
G16
G19
G2
G22
G25
G28
G3
G30
G32
G33
G5
G7
K2
K28
K30
K32
K33
K5
K7
M13
M15
M17
M18
M20
M22
N12
N14
N16
N19
N2
N21
N23
N28
N30
N32
N33
N5
N7
P13
P15
P17
P18
P20
P22
R12
R14
R16
R19
R21
R23
T13
T15
T17
T18
T2
T20
T22
AG11
T28
T32
T5
T7
U12
U14
U16
U19
U21
U23
V12
V14
V16
V19
V21
V23
W13
W15
W17
W18
W20
W22
W28
Y12
Y14
Y16
Y19
Y21
Y23
AH11
C16
W32

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENTDIVISIO N OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENTDIVISIO N OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENTDIVISIO N OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEETN OR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEETN OR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEETN OR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2011/11/01

2011/11/01

2011/11/01

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2012/12/31

2012/12/31

2012/12/31

Title

Title

Title

N14P-VGA CORE, GND

N14P-VGA CORE, GND

N14P-VGA CORE, GND

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Monday, January 14, 201 3

Monday, January 14, 201 3

Monday, January 14, 201 3

Date: Sheet

Date: Sheet of

Date: Sheet of

Y400S-NM-A141

Y400S-NM-A141

Y400S-NM-A141

1

26 65

26 65

26 65

of

1.0

1.0

1.0

5

@

QV4
2N7002_SOT23

FBA_D[0..63]

RV172

1 2

0_0402_5%

FBA_DBI0#<28>
FBA_DBI1#<28>
FBA_DBI2#<28>
FBA_DBI3#<28>
FBA_DBI4#<29>
FBA_DBI5#<29>
FBA_DBI6#<29>
FBA_DBI7#<29>

@

DV3 DAN202UT106_SC70-3

2

1

3

GC6@

RV156

NOGC6@

1 2

0_0402_5%

FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8

FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63

FBA_DBI0#
FBA_DBI1#
FBA_DBI2#
FBA_DBI3#
FBA_DBI4#
FBA_DBI5#
FBA_DBI6#
FBA_DBI7#

FBA_EDC0
FBA_EDC1
FBA_EDC2
FBA_EDC3
FBA_EDC4
FBA_EDC5
FBA_EDC6
FBA_EDC7

GC6_EN <32>

12

RV29
200K_0402_5%

UV1B

L28

FBA_D0

M29

FBA_D1

L29

FBA_D2

M28

FBA_D3

N31

FBA_D4

P29

FBA_D5

R29

FBA_D6

P28

FBA_D7

J28

FBA_D8

H29

FBA_D9

J29

FBA_D10

H28

FBA_D11

G29

FBA_D12

E31

FBA_D13

E32

FBA_D14

F30

FBA_D15

C34

FBA_D16

D32

FBA_D17

B33

FBA_D18

C33

FBA_D19

F33

FBA_D20

F32

FBA_D21

H33

FBA_D22

H32

FBA_D23

P34

FBA_D24

P32

FBA_D25

P31

FBA_D26

P33

FBA_D27

L31

FBA_D28

L34

FBA_D29

L32

FBA_D30

L33

FBA_D31

AG28

FBA_D32

AF29

FBA_D33

AG29

FBA_D34

AF28

FBA_D35

AD30

FBA_D36

AD29

FBA_D37

AC29

FBA_D38

AD28

FBA_D39

AJ29

FBA_D40

AK29

FBA_D41

AJ30

FBA_D42

AK28

FBA_D43

AM29

FBA_D44

AM31

FBA_D45

AN29

FBA_D46

AM30

FBA_D47

AN31

FBA_D48

AN32

FBA_D49

AP30

FBA_D50

AP32

FBA_D51

AM33

FBA_D52

AL31

FBA_D53

AK33

FBA_D54

AK32

FBA_D55

AD34

FBA_D56

AD32

FBA_D57

AC30

FBA_D58

AD33

FBA_D59

AF31

FBA_D60

AG34

FBA_D61

AG32

FBA_D62

AG33

FBA_D63

P30

FBA_DQM0

F31

FBA_DQM1

F34

FBA_DQM2

M32

FBA_DQM3

AD31

FBA_DQM4

AL29

FBA_DQM5

AM32

FBA_DQM6

AF34

FBA_DQM7

M31

FBA_DQS_WP0

G31

FBA_DQS_WP1

E33

FBA_DQS_WP2

M33

FBA_DQS_WP3

AE31

FBA_DQS_WP4

AK30

FBA_DQS_WP5

AN33

FBA_DQS_WP6

AF33

FBA_DQS_WP7

M30

FBA_DQS_RN0

H30

FBA_DQS_RN1

E34

FBA_DQS_RN2

M34

FBA_DQS_RN3

AF30

FBA_DQS_RN4

AK31

FBA_DQS_RN5

AM34

FBA_DQS_RN6

AF32

FBA_DQS_RN7

N14P_FCBGA908

FBVDDQ_PWR_EN <55>

GC6@

FBA_D[0..63]<28,29>

30ohms (ESR=0.01) Bead
P/N;SM010007W00

+1.05VS_VGA +FB_PLLAVDD

FBMA-L11-160808300LMA25T_2P

D D

C C

B B

1 2

LV3

Place close to BGA

For N13P-GT GC6 support

A A

DGPU_GC6_EN<18>

200mA

+FB_PLLAVDD

FBA_EDC[3..0]<28>

FBA_EDC[7..4]<29>

+3VS

13

D

2

G

RV169

@

S

1 2

0_0402_5%

RV18

1 2

FB_CLAMP S_GC6_EN

GC6@

0_0402_5%

12

RV6810K_0402_5%

GC6@

DGPU_PWROK<19,55,58>

5

Part 2 of 7

4

MEMORY INTERFACE

A

4

FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8

FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30
FBA_CMD31

FBA_CMD_RFU0
FBA_CMD_RFU1

FBA_DEBUG0
FBA_DEBUG1

FBA_CLK0

FBA_CLK0_N

FBA_CLK1

FBA_CLK1_N

FBA_WCK01

FBA_WCK01_N

FBA_WCK23

FBA_WCK23_N

FBA_WCK45

FBA_WCK45_N

FBA_WCK67

FBA_WCK67_N

FBA_WCKB01

FBA_WCKB01_N

FBA_WCKB23

FBA_WCKB23_N

FBA_WCKB45

FBA_WCKB45_N

FBA_WCKB67

FBA_WCKB67_N

FB_CLAMP

FB_DLL_AVDD

FBA_PLL_AVDD

FB_VREF

U30

FBA_CS#_L

T31

FBA_MA3_BA3_L

U29

FBA_MA2_BA0_L

R34

FBA_MA4_BA2_L

R33

FBA_MA5_BA1_L

U32

FBA_WE#_L

U33

FBA_MA7_MA8_L

U28

FBA_MA6_MA11_L

V28

FBA_ABI#_L

V29

FBA_MA12_RFU_L

V30

FBA_MA0_MA10_L

U34

FBA_MA1_MA9_L

U31

FBA_RAS#_L

V34

FBA_RST#_L

V33

FBA_CKE_L

Y32

FBA_CAS#_L

AA31

FBA_CS#_H

AA29

FBA_MA3_BA3_H

AA28

FBA_MA2_BA0_H

AC34

FBA_MA4_BA2_H

AC33

FBA_MA5_BA1_H

AA32

FBA_WE#_H

AA33

FBA_MA7_MA8_H

Y28

FBA_MA6_MA11_H

Y29

FBA_ABI#_H

W31

FBA_MA12_RFU_H

Y30

FBA_MA0_MA10_H

AA34

FBA_MA1_MA9_H

Y31

FBA_RAS#_H

Y34

FBA_RST#_H

Y33

FBA_CKE_H

V31

FBA_CAS#_H

R32
AC32

1 2

R28
AC28

1 2

@

R30

FBA_CLK0

R31

FBA_CLK0#

AB31

FBA_CLK1

AC31

FBA_CLK1#

K31

FBA_WCK0

L30

FBA_WCK0_N

H34

FBA_WCK1

J34

FBA_WCK1_N

AG30

FBA_WCK2

AG31

FBA_WCK2_N

AJ34

FBA_WCK3

AK34

FBA_WCK3_N

J30
J31
J32
J33

GC6 suppor t on 15"

AH31
AJ31

FB_CLAMP

AJ32
AJ33

BOM structure from "NOGC6@" to "Mount"

RV66 10K_0402_5%

NOGC6@

E1

CV106 0.1U_0402_10V7K

1 2

K27

Place close to ball

U27

H26

P

lace close to ball Place close to B GA

FBA_RST#_L
FBA_RST#_H

@

RV5860.4_0402_1%
RV5960.4_0402_1%

12

1

2

0.1U_0402_10V7K

12

FBA_CS#_L <28>
FBA_MA3_BA3_L <28>
FBA_MA2_BA0_L <28>
FBA_MA4_BA2_L <28>
FBA_MA5_BA1_L <28>
FBA_WE#_L <28>
FBA_MA7_MA8_L <28>
FBA_MA6_MA11_L < 28>
FBA_ABI#_L <28>
FBA_MA12_RFU_L <28>
FBA_MA0_MA10_L < 28>
FBA_MA1_MA9_L <28>
FBA_RAS#_L <28>
FBA_RST#_L <28>

FBA_CAS#_L <28>
FBA_CS#_H <29>
FBA_MA3_BA3_H <29>
FBA_MA2_BA0_H <29>
FBA_MA4_BA2_H <29>
FBA_MA5_BA1_H <29>
FBA_WE#_H <29>
FBA_MA7_MA8_H <29>
FBA_MA6_MA11_H <29>
FBA_ABI#_H <29>
FBA_MA12_RFU_H <29>
FBA_MA0_MA10_H <29>
FBA_MA1_MA9_H <29>
FBA_RAS#_H <29>
FBA_RST#_H <29>

FBA_CAS#_H <29>

FBA_CLK0 <28>
FBA_CLK0# <28>
FBA_CLK1 <29>
FBA_CLK1# <29>

FBA_WCK0 <28>
FBA_WCK0_N <28>
FBA_WCK1 <28>
FBA_WCK1_N <28>
FBA_WCK2 <29>
FBA_WCK2_N <29>
FBA_WCK3 <29>
FBA_WCK3_N <29>

FB_CLAMP <23,45>

+FB_PLLAVDD

1

CV107

CV110

2

1U_0402_6.3V6K

12

RV71
10K_0402_5%

+1.5VS_VGA

1

2

22U_0805_6.3V6M

RV72
10K_0402_5%

+FB_PLLAVDD

CV39

FBC_D[0..63]<30,31>

+1.5VS_VGA

12

+1.5VS_VGA

12

RV209
10K_0402_5%

RV221
10K_0402_5%

FBC_EDC[3..0]<30>

FBC_EDC[7..4]<31>

3

FBC_D[0..63]

FBA_CKE_L <28>

FBA_CKE_H <29>

FBC_DBI0#<30>
FBC_DBI1#<30>
FBC_DBI2#<30>
FBC_DBI3#<30>
FBC_DBI4#<31>
FBC_DBI5#<31>
FBC_DBI6#<31>
FBC_DBI7#<31>

3

2

UV1C

FBC_D0
FBC_D1
FBC_D2
FBC_D3
FBC_D4
FBC_D5
FBC_D6
FBC_D7
FBC_D8

FBC_D9
FBC_D10
FBC_D11
FBC_D12
FBC_D13
FBC_D14
FBC_D15
FBC_D16
FBC_D17
FBC_D18
FBC_D19
FBC_D20
FBC_D21
FBC_D22
FBC_D23
FBC_D24
FBC_D25
FBC_D26
FBC_D27
FBC_D28
FBC_D29
FBC_D30
FBC_D31
FBC_D32
FBC_D33
FBC_D34
FBC_D35
FBC_D36
FBC_D37
FBC_D38
FBC_D39
FBC_D40
FBC_D41
FBC_D42
FBC_D43
FBC_D44
FBC_D45
FBC_D46
FBC_D47
FBC_D48
FBC_D49
FBC_D50
FBC_D51
FBC_D52
FBC_D53
FBC_D54
FBC_D55
FBC_D56
FBC_D57
FBC_D58
FBC_D59
FBC_D60
FBC_D61
FBC_D62
FBC_D63

FBC_DBI0#
FBC_DBI1#
FBC_DBI2#
FBC_DBI3#
FBC_DBI4#
FBC_DBI5#
FBC_DBI6#
FBC_DBI7#

FBC_EDC0
FBC_EDC1
FBC_EDC2
FBC_EDC3
FBC_EDC4
FBC_EDC5
FBC_EDC6
FBC_EDC7

G9

E9

G8

F9

F11

G11

F12

G12

G6

F5
E6
F6
F4

G4

E2
F3
C2
D4
D3
C1
B3
C4
B5

C5
A11
C11
D11
B11

D8

A8

C8

B8
F24

G23

E24

G24

D21
E21

G21

F21

G27

D27

G26

E27
E29
F29
E30
D30
A32
C31
C32
B32
D29
A29
C29
B29
B21
C23
A21
C21
B24
C24
B26
C26

E11

E3

A3

C9
F23
F27
C30
A24

D10

D5

C3

B9
E23
E28
B30
A23

D9

E4

B2

A9
D22
D28
A30
B23

Part 3 of 7

FBB_D0
FBB_D1
FBB_D2
FBB_D3
FBB_D4
FBB_D5
FBB_D6
FBB_D7
FBB_D8
FBB_D9
FBB_D10
FBB_D11
FBB_D12
FBB_D13
FBB_D14
FBB_D15
FBB_D16
FBB_D17
FBB_D18
FBB_D19
FBB_D20
FBB_D21
FBB_D22
FBB_D23
FBB_D24
FBB_D25
FBB_D26
FBB_D27
FBB_D28
FBB_D29
FBB_D30
FBB_D31
FBB_D32
FBB_D33
FBB_D34
FBB_D35
FBB_D36
FBB_D37
FBB_D38
FBB_D39
FBB_D40
FBB_D41
FBB_D42
FBB_D43
FBB_D44
FBB_D45
FBB_D46
FBB_D47
FBB_D48
FBB_D49
FBB_D50
FBB_D51
FBB_D52
FBB_D53
FBB_D54
FBB_D55
FBB_D56
FBB_D57
FBB_D58
FBB_D59
FBB_D60
FBB_D61
FBB_D62
FBB_D63

FBB_DQM0
FBB_DQM1
FBB_DQM2
FBB_DQM3
FBB_DQM4
FBB_DQM5
FBB_DQM6
FBB_DQM7

FBB_DQS_WP0
FBB_DQS_WP1
FBB_DQS_WP2
FBB_DQS_WP3
FBB_DQS_WP4
FBB_DQS_WP5
FBB_DQS_WP6
FBB_DQS_WP7

FBB_DQS_RN0
FBB_DQS_RN1
FBB_DQS_RN2
FBB_DQS_RN3
FBB_DQS_RN4
FBB_DQS_RN5
FBB_DQS_RN6
FBB_DQS_RN7

N14P_FCBGA908

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF LC FU TURE CENTER. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF LC FU TURE CENTER. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF LC FU TURE CENTER. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENTER.

FBB_CMD_RFU0
FBB_CMD_RFU1

MEMORY INTERFACE B

FBB_CMD0
FBB_CMD1
FBB_CMD2
FBB_CMD3
FBB_CMD4
FBB_CMD5
FBB_CMD6
FBB_CMD7
FBB_CMD8

FBB_CMD9
FBB_CMD10
FBB_CMD11
FBB_CMD12
FBB_CMD13
FBB_CMD14
FBB_CMD15
FBB_CMD16
FBB_CMD17
FBB_CMD18
FBB_CMD19
FBB_CMD20
FBB_CMD21
FBB_CMD22
FBB_CMD23
FBB_CMD24
FBB_CMD25
FBB_CMD26
FBB_CMD27
FBB_CMD28
FBB_CMD29
FBB_CMD30
FBB_CMD31

FBB_DEBUG0

FBB_DEBUG1

FBB_CLK0

FBB_CLK0_N

FBB_CLK1

FBB_CLK1_N

FBB_WCK01

FBB_WCK01_N

FBB_WCK23

FBB_WCK23_N

FBB_WCK45

FBB_WCK45_N

FBB_WCK67

FBB_WCK67_N

FBB_WCKB01

FBB_WCKB01_N

FBB_WCKB23

FBB_WCKB23_N

FBB_WCKB45

FBB_WCKB45_N

FBB_WCKB67

FBB_WCKB67_N

FBB_PLL_AVDD

2011/11/01

2011/11/01

2011/11/01

D13

FBC_CS#_L

E14

FBC_MA3_BA3_L

F14

FBC_MA2_BA0_L

A12

FBC_MA4_BA2_L

B12

FBC_MA5_BA1_L

C14

FBC_WE#_L

B14

FBC_MA7_MA8_L

G15

FBC_MA6_MA11_L

F15

FBC_ABI#_L

E15

FBC_MA12_RFU_L

D15

FBC_MA0_MA10_L

A14

FBC_MA1_MA9_L

D14

FBC_RAS#_L

A15

FBC_RST#_L

B15

FBC_CKE_L

C17

FBC_CAS#_L

D18

FBC_CS#_H

E18

FBC_MA3_BA3_H

F18

FBC_MA2_BA0_H

A20

FBC_MA4_BA2_H

B20

FBC_MA5_BA1_H

C18

FBC_WE#_H

B18

FBC_MA7_MA8_H

G18

FBC_MA6_MA11_H

G17

FBC_ABI#_H

F17

FBC_MA12_RFU_H

D16

FBC_MA0_MA10_H

A18

FBC_MA1_MA9_H

D17

FBC_RAS#_H

A17

FBC_RST#_H

B17

FBC_CKE_H

E17

FBC_CAS#_H

C12
C20

@

1 2

G14

1 2

G20

D12
E12
E20
F20

F8
E8
A5
A6
D24
D25
B27
C27

D6
D7
C6
B6
F26
E26
A26
A27

H17

@

FBC_CLK0
FBC_CLK0#
FBC_CLK1
FBC_CLK1#

FBC_WCK0
FBC_WCK0_N
FBC_WCK1
FBC_WCK1_N
FBC_WCK2
FBC_WCK2_N
FBC_WCK3
FBC_WCK3_N

1

CV108

2

0.1U_0402_10V7K

Place close to ball

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

FBC_CS#_L <30>
FBC_MA3_BA3_L <30>
FBC_MA2_BA0_L <30>
FBC_MA4_BA2_L <30>
FBC_MA5_BA1_L <30>
FBC_WE#_L <30>
FBC_MA7_MA8_L <30>
FBC_MA6_MA11_L <30>
FBC_ABI#_L <30>
FBC_MA12_RFU_L <30>
FBC_MA0_MA10_L <30>
FBC_MA1_MA9_L <30>
FBC_RAS#_L <30>
FBC_RST#_L <30>

FBC_CAS#_L <30>
FBC_CS#_H <31>
FBC_MA3_BA3_H <31>
FBC_MA2_BA0_H <31>
FBC_MA4_BA2_H <31>
FBC_MA5_BA1_H <31>
FBC_WE#_H <31>
FBC_MA7_MA8_H <31>
FBC_MA6_MA11_H <31>
FBC_ABI#_H <31>
FBC_MA12_RFU_H <31>
FBC_MA0_MA10_H <31>
FBC_MA1_MA9_H <31>
FBC_RAS#_H <31>
FBC_RST#_H <31>

FBC_CAS#_H <31>

RV6060.4_0402_1%
RV6160.4_0402_1%

FBC_CLK0 <30>
FBC_CLK0# <30>
FBC_CLK1 <31>
FBC_CLK1# <31>

FBC_WCK0 <30>
FBC_WCK0_N <30>
FBC_WCK1 <30>
FBC_WCK1_N <30>
FBC_WCK2 <31>
FBC_WCK2_N <31>
FBC_WCK3 <31>
FBC_WCK3_N <31>

+FB_PLLAVDD

+1.5VS_VGA

FBC_RST#_L
FBC_RST#_H

2012/12/31

2012/12/31

2012/12/31

PU for X16 modePU for X16 mode

+1.5VS_VGA

+1.5VS_VGA

1

GDDR5
Mode H - Mirror Mode Mapping

12

RV210
10K_0402_5%

FBC_CKE_L <30>

12

RV222
10K_0402_5%

FBC_CKE_H <31>

12

12

RV74
10K_0402_5%

Title

Title

Title

N14P-MEM Interface

N14P-MEM Interface

N14P-MEM Interface

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

RV73
10K_0402_5%

Address

FBx_CMD0

FBx_CMD1

FBx_CMD2

FBx_CMD3

FBx_CMD4

FBx_CMD5

FBx_CMD6

FBx_CMD7

FBx_CMD8

FBx_CMD9

FBx_CMD10

FBx_CMD11

FBx_CMD12

FBx_CMD13

FBx_CMD14

FBx_CMD15

FBx_CMD16

FBx_CMD17

FBx_CMD18

FBx_CMD19

FBx_CMD20

FBx_CMD21

FBx_CMD22

FBx_CMD23

FBx_CMD24

FBx_CMD25

FBx_CMD26

FBx_CMD27

FBx_CMD28

FBx_CMD29

FBx_CMD30

FBx_CMD31

Y400S-NM-A141

Y400S-NM-A141

Y400S-NM-A141

Monday, January 14, 2013

Monday, January 14, 2013

Monday, January 14, 2013

1

CS#

A3_BA3

A2_BA0

A4_BA2

A5_BA1

WE#

A7_A8

A6_A11

ABI#

A12_RFU

A0_A10

A1_A9

RAS#

RST#

CKE#

CAS#

DATA Bus

27 65

27 65

27 65

2..630..31

3

CS#

A3_BA3

A2_BA0

A4_BA2

A5_BA1

WE#

A7_A8

A6_A11

ABI#

A12_RFU

A0_A10

A1_A9

RAS#

RST#

CKE#

CAS#

1.0

1.0

1.0

5

Memory - Lower 32 bits

FBA_EDC0

FBA_D[0..31]< 27>

FBA_EDC[3..0]<27>

D D

Follow DG

1 2

FBA_CLK0

RV21 40.2_0402_1%

RV123
160_0402_1%

FBA_CLK0#

MEM_VREF<23,29,30,31>

@

1 2

1 2

RV28 40.2_0402_1%

2

G

1

CV155

2

0.01U_0402_25V7K

RV212

1 2

931_0402_1%

1.33K_0402_1%

13

D

QV9

S

2N7002W-T/R7_SOT323-3

+1.5VS_VGA

549_0402_1%

10U_0603_6.3V6M

C C

B B

A A

FBA_DBI0#<27>

FBA_DBI2#<27> FBA_DBI1#<27>

FBA_CLK0<27>

FBA_CLK0#<27>

FBA_CKE_L<27>

FBA_MA2_BA0_L<27>
FBA_MA5_BA1_L<27>
FBA_MA4_BA2_L<27>
FBA_MA3_BA3_L<27>

FBA_MA7_MA8_L<27>

FBA_MA1_MA9_L<27>
FBA_MA0_MA10_L<27>
FBA_MA6_MA11_L<27>
FBA_MA12_RFU_L<27>

RV119

121_0402_1%

FBA_ABI#_L<27>

FBA_RAS#_L<27>

FBA_CS#_L<27>

FBA_CAS#_L<27>

FBA_WE#_L<27>

FBA_WCK0_N<27>
FBA_WCK0<27>

FBA_WCK1_N<27>
FBA_WCK1<27>

FBA_RST#_L<27>

+1.5VS_VGA

12

RV127

12

1

RV128

2

820P_0402_25V7

+1.5VS_VGA

12

RV129

549_0402_1%

RV213

1 2

931_0402_1%

12

RV130

1.33K_0402_1%

UV3 SIDE

2

1

CV68

CV166

1

2

1U_0603_25V6

1U_0603_25V6

FBA_EDC2

FBA_DBI0#

FBA_DBI2#

FBA_CLK0
FBA_CLK0#
FBA_CKE_L

FBA_MA2_BA0_L
FBA_MA5_BA1_L

FBA_MA4_BA2_L

FBA_MA3_BA3_L

FBA_MA7_MA8_L

FBA_MA1_MA9_L
FBA_MA0_MA10_L
FBA_MA6_MA11_L

FBA_MA12_RFU_L

12

RV115

1K_0402_1%

12

RV117

12

1K_0402_1%

FBA_ABI#_L

FBA_RAS#_L

FBA_CS#_L

FBA_CAS#_L

FBA_WE#_L

FBA_WCK0_N
FBA_WCK0

FBA_WCK1_N
FBA_WCK1

+FBA_VREFD_L

+FBA_VREFC0

FBA_RST#_L

+FBA_VREFC0

16 mil

CV42

+1.5VS_VGA +1.5VS_VGA

+FBA_VREFD_L

820P_0402_25V7

1

1

CV69

CV77

2

2

1U_0603_25V6

1U_0603_25V6

UV3

MF=0 MF=1 MF=0MF=1

C2

EDC0 EDC3

C13

EDC1 EDC2

R13

EDC2 EDC1

R2

EDC3 EDC0

D2

DBI0# DBI3#

D13

DBI1# DBI2#

P13

DBI2# DBI1#

P2

DBI3# DBI0#

J12

CK

J11

CK#

J3

CKE#

H11

BA0/A2 BA2/A4

K10

BA1/A5 BA3/A3

K11

BA2/A4 BA0/A2

H10

BA3/A3 BA1/A5

K4

A8/A7 A10/A0

H5

A9/A1 A11/A6

H4

A10/A0 A8/A7

K5

A11/A6 A9/A1

J5

A12/RFU/NC

A5

VPP/NC

U5

VPP/NC

J1

MF

J10

SEN

J13

ZQ

J4

ABI#

G3

RAS# CAS#

G12

CS# WE#

L3

CAS# RAS#

L12

WE# CS#

D5

WCK01# WCK23#

D4

WCK01 WCK23

P5

WCK23# WCK01#

P4

WCK23 WCK01

A10

VREFD

U10

VREFD

J14

VREFC

J2

RESET#

H1

VSS

K1

VSS

B5

VSS

G5

VSS

L5

VSS

T5

VSS

B10

VSS

D10

VSS

G10

VSS

L10

VSS

P10

VSS

T10

VSS

H14

VSS

K14

VSS

G1

VDD

L1

VDD

G4

VDD

L4

VDD

C5

VDD

R5

VDD

C10

VDD

R10

VDD

D11

VDD

G11

VDD

L11

VDD

P11

VDD

G14

VDD

L14

VDD

1

CV58

2

1

2

170-BALL

SGRAM GDDR5

X76@

1

CV78

2

0.1U_0402_10V7K

1

1

CV129

CV132

2

2

0.1U_0402_10V7K

0.1U_0402_10V7K

CV133

4

DQ24 DQ0
DQ25 DQ1
DQ26 DQ2
DQ27 DQ3
DQ28 DQ4
DQ29 DQ5
DQ30 DQ6
DQ31 DQ7
DQ16 DQ8
DQ17 DQ9

DQ18 DQ10
DQ19 DQ11
DQ20 DQ12
DQ21 DQ13
DQ22 DQ14
DQ23 DQ15
DQ8 DQ16
DQ9 DQ17
DQ10 DQ18
DQ11 DQ19
DQ12 DQ20
DQ13 DQ21
DQ14 DQ22
DQ15 DQ23
DQ0 DQ24
DQ1 DQ25
DQ2 DQ26
DQ3 DQ27
DQ4 DQ28
DQ5 DQ29
DQ6 DQ30
DQ7 DQ31

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

H5GQ1H24AFR-T2L_BGA170

3

UV4

A4

FBA_D0

A2

FBA_D1

B4

FBA_D2

B2

FBA_D3

E4

FBA_D4

E2

FBA_D5

F4

FBA_D6

F2

FBA_D7

A11
A13
B11
B13
E11
E13
F11
F13
U11

FBA_D16

U13

FBA_D17

T11

FBA_D18

T13

FBA_D19

N11

FBA_D20

N13

FBA_D21

M11

FBA_D22

M13

FBA_D23

U4
U2
T4
T2
N4
N2
M4
M2

B1
D1
F1
M1
P1
T1
G2
L2
B3
D3
F3
H3
K3
M3
P3
T3
E5
N5
E10
N10
B12
D12
F12
H12
K12
M12
P12
T12
G13
L13
B14
D14
F14
M14
P14
T14

A1
C1
E1
N1
R1
U1
H2
K2
A3
C3
E3
N3
R3
U3
C4
R4
F5
M5
F10
M10
C11
R11
A12
C12
E12
N12
R12
U12
H13
K13
A14
C14
E14
N14
R14
U14

+1.5VS_VGA

10U_0603_6.3V6M

2

1

CV174

BYTE0

BYTE2

UV4 SIDE

1

CV71

2

1U_0603_25V6

FBA_DBI3#<27>

+1.5VS_VGA

RV120

121_0402_1%

1

1

1

CV76

2

2

1U_0603_25V6

1U_0603_25V6

1

CV79

CV80

CV134

2

2

1U_0603_25V6

0.1U_0402_10V7K

0.1U_0402_10V7K

12

1

CV135

2

FBA_EDC3

FBA_EDC1

FBA_DBI3#

FBA_DBI1#

FBA_CLK0
FBA_CLK0#
FBA_CKE_L

FBA_MA4_BA2_L
FBA_MA3_BA3_L
FBA_MA2_BA0_L
FBA_MA5_BA1_L

FBA_MA0_MA10_L
FBA_MA6_MA11_L

FBA_MA7_MA8_L
FBA_MA1_MA9_L

FBA_MA12_RFU_L

12

RV116

1K_0402_1%

12

RV118

1K_0402_1%

FBA_ABI#_L

FBA_CAS#_L

FBA_WE#_L

FBA_RAS#_L

FBA_CS#_L

FBA_WCK1_N
FBA_WCK1

FBA_WCK0_N
FBA_WCK0

+FBA_VREFD_L

+FBA_VREFC0

FBA_RST#_L

1

CV136

2

0.1U_0402_10V7K

MF=0 MF=1 MF=0MF=1

C2

EDC0 EDC3

C13

EDC1 EDC2

R13

EDC2 EDC1

R2

EDC3 EDC0

D2

DBI0# DBI3#

D13

DBI1# DBI2#

P13

DBI2# DBI1#

P2

DBI3# DBI0#

J12

CK

J11

CK#

J3

CKE#

H11

BA0/A2 BA2/A4

K10

BA1/A5 BA3/A3

K11

BA2/A4 BA0/A2

H10

BA3/A3 BA1/A5

K4

A8/A7 A10/A0

H5

A9/A1 A11/A6

H4

A10/A0 A8/A7

K5

A11/A6 A9/A1

J5

A12/RFU/NC

A5

VPP/NC

U5

VPP/NC

J1

MF

J10

SEN

J13

ZQ

J4

ABI#

G3

RAS# CAS#

G12

CS# WE#

L3

CAS# RAS#

L12

WE# CS#

D5

WCK01# WCK23#

D4

WCK01 WCK23

P5

WCK23# WCK01#

P4

WCK23 WCK01

A10

VREFD

U10

VREFD

J14

VREFC

J2

RESET#

H1

VSS

K1

VSS

B5

VSS

G5

VSS

L5

VSS

T5

VSS

B10

VSS

D10

VSS

G10

VSS

L10

VSS

P10

VSS

T10

VSS

H14

VSS

K14

VSS

G1

VDD

L1

VDD

G4

VDD

L4

VDD

C5

VDD

R5

VDD

C10

VDD

R10

VDD

D11

VDD

G11

VDD

L11

VDD

P11

VDD

G14

VDD

L14

VDD

170-BALL

SGRAM GDDR5

X76@

DQ24 DQ0
DQ25 DQ1
DQ26 DQ2
DQ27 DQ3
DQ28 DQ4
DQ29 DQ5
DQ30 DQ6
DQ31 DQ7
DQ16 DQ8
DQ17 DQ9

DQ18 DQ10
DQ19 DQ11
DQ20 DQ12
DQ21 DQ13
DQ22 DQ14
DQ23 DQ15
DQ8 DQ16
DQ9 DQ17
DQ10 DQ18
DQ11 DQ19
DQ12 DQ20
DQ13 DQ21
DQ14 DQ22
DQ15 DQ23
DQ0 DQ24
DQ1 DQ25
DQ2 DQ26
DQ3 DQ27
DQ4 DQ28
DQ5 DQ29
DQ6 DQ30
DQ7 DQ31

H5GQ1H24AFR-T2L_BGA170

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

2

A4

FBA_D24

A2

FBA_D25

B4

FBA_D26

B2

FBA_D27

E4

FBA_D28

E2

FBA_D29

F4

FBA_D30

F2

FBA_D31

A11
A13
B11
B13
E11
E13
F11
F13
U11

FBA_D8

U13

FBA_D9

T11

FBA_D10

T13

FBA_D11

N11

FBA_D12

N13

FBA_D13

M11

FBA_D14

M13

FBA_D15

U4
U2
T4
T2
N4
N2
M4
M2

B1
D1
F1
M1
P1
T1
G2
L2
B3
D3
F3
H3
K3
M3
P3
T3
E5
N5
E10
N10
B12
D12
F12
H12
K12
M12
P12
T12
G13
L13
B14
D14
F14
M14
P14
T14

A1
C1
E1
N1
R1
U1
H2
K2
A3
C3
E3
N3
R3
U3
C4
R4
F5
M5
F10
M10
C11
R11
A12
C12
E12
N12
R12
U12
H13
K13
A14
C14
E14
N14
R14
U14

BYTE3

GDDR5

B

TE1

Y

+1.5VS_VGA+1.5VS_VGA

Mode H - Mirror Mode Mapping

Address

FBx_CMD0

FBx_CMD1

FBx_CMD2

FBx_CMD3

FBx_CMD4

FBx_CMD5

FBx_CMD6

FBx_CMD7

FBx_CMD8

FBx_CMD9

FBx_CMD10

FBx_CMD11

FBx_CMD12

FBx_CMD13

FBx_CMD14

FBx_CMD15

FBx_CMD16

FBx_CMD17

FBx_CMD18

FBx_CMD19

FBx_CMD20

FBx_CMD21

FBx_CMD22

FBx_CMD23

FBx_CMD24

FBx_CMD25

FBx_CMD26

FBx_CMD27

FBx_CMD28

FBx_CMD29

FBx_CMD30

FB

x_CMD31

1

DATA Bus

0..31 32..63

CS#

A3_BA3

A2_BA0

A4_BA2

A5_BA1

WE#

A7_A8

A6_A11

ABI#

A12_RFU

A0_A10

A1_A9

RAS#

RST#

CKE#

CAS#

CS#

A3_BA3

A2_BA0

A4_BA2

A5_BA1

WE#

A7_A8

A6_A11

ABI#

A12_RFU

A0_A10

A1_A9

RAS#

RST#

CKE#

CAS#

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THISSHEE T NORTHE INFORMATIONIT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THISSHEE T NORTHE INFORMATIONIT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THISSHEE T NORTHE INFORMATIONIT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTPRIOR WRI TTEN CONSENT OF LC FUTURECENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTPRIOR WRI TTEN CONSENT OF LC FUTURECENTER.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTPRIOR WRI TTEN CONSENT OF LC FUTURECENTER.

2011/11/01

2011/11/01

2011/11/01

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2012/12/31

2012/12/31

2012/12/31

Title

N14P-VRAM A Lower

N14P-VRAM A Lower

N14P-VRAM A Lower

Size Doc ument Number Rev

Size Doc ument Number Rev

Size Doc ument Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Y400-LA8691P

Y400-LA8691P

Y400-LA8691P

Monday, March 11, 2013

Monday, March 11, 2013

Monday, March 11, 2013

1

of

of

of

28 65

28 65

28 65

1.0

1.0

1.0

5

Memory - Upper 32 bits

C2

FBA_EDC4

C13
R13

FBA_CLK1

FBA_CLK1#

FBA_MA2_BA0_H
FBA_MA5_BA1_H
FBA_MA4_BA2_H
FBA_MA3_BA3_H

FBA_MA7_MA8_H

FBA_MA1_MA9_H
FBA_MA0_MA10_H
FBA_MA6_MA11_H
FBA_MA12_RFU_H

12

+FBA_VREFC1

16 mil

CV59

+FBA_VREFD_H

820P_0402_25V7

1

CV138

2

FBA_CKE_H

12

RV131

1K_0402_1%

12

RV133

1K_0402_1%

FBA_ABI#_H

FBA_RAS#_H

FBA_CS#_H

FBA_CAS#_H

FBA_WE#_H

FBA_WCK2_N
FBA_WCK2

FBA_WCK3_N
FBA_WCK3

+FBA_VREFD_H

+FBA_VREFC1

FBA_RST#_H

+1.5VS_VGA

1

CV60

2

1

CV142

2

0.1U_0402_10V7K

FBA_EDC6

FBA_DBI4#

FBA_DBI6#

1

2

0.1U_0402_10V7K

R2

D2

D13

P13

P2

J12
J11

J3

H11

K10
K11

H10

K4
H5
H4
K5

J5

A5
U5

J1
J10
J13

J4

G3

G12

L3
L12

D5
D4

P5
P4

A10

U10

J14

J2

H1
K1
B5
G5

L5

T5
B10

D10
G10

L10
P10
T10

H14

K14

G1

L1

G4

L4

C5

R5
C10
R10
D11
G11

L11
P11

G14

L14

CV137

FBA_D[63..32]<27>

D D

FBA_EDC[7..4]<27>

Follow DG

1 2

FBA_CLK1

RV31 40.2_0402_1%

RV139

C C

B B

MEM_VREF<23,28,30,31>

A A

FBA_CLK1#

160_0402_1%

@

1 2

1 2

RV36 40.2_0402_1%

13

D

2

G

QV11

S

2N7002W-T/R7_SOT323-3

+1.5VS_VGA

UV5 SIDE

2

CV179

1

1U_0603_25V6

10U_0603_6.3V6M

0.01U_0402_25V7K

1 2

1

CV84

2

1

CV175

2

RV214

931_0402_1%

RV215

1 2

931_0402_1%

1

2

1U_0603_25V6

549_0402_1%

1.33K_0402_1%

549_0402_1%

1.33K_0402_1%

CV81

1U_0603_25V6

FBA_MA2_BA0_H<27>
FBA_MA5_BA1_H<27>
FBA_MA4_BA2_H<27>
FBA_MA3_BA3_H<27>

FBA_MA7_MA8_H<27>

FBA_MA1_MA9_H<27>
FBA_MA0_MA10_H<27>
FBA_MA6_MA11_H<27>
FBA_MA12_RFU_H<27>

RV143

RV144

RV145

RV146

1

CV82

2

FBA_CLK1<27>

FBA_CLK1#<27>

FBA_CKE_H<27>

FBA_ABI#_H<27>

FBA_RAS#_H<27>

FBA_CS#_H<27>

FBA_CAS#_H<27>

FBA_WE#_H<27>

FBA_WCK2_N<27>
FBA_WCK2<27>

FBA_WCK3_N<27>
FBA_WCK3<27>

FBA_RST#_H<27>

+1.5VS_VGA

12

12

+1.5VS_VGA

12

12

1U_0603_25V6

1

2

RV135

CV83

FBA_DBI4#<27>

FBA_DBI6#<27>

121_0402_1%

1

2

820P_0402_25V7

0.1U_0402_10V7K

4

UV5

MF=0 MF=1 MF=0MF=1

EDC0 EDC3
EDC1 EDC2
EDC2 EDC1
EDC3 EDC0

DBI0# DBI3#
DBI1# DBI2#
DBI2# DBI1#
DBI3# DBI0#

CK
CK#
CKE#

BA0/A2 BA2/A4
BA1/A5 BA3/A3
BA2/A4 BA0/A2
BA3/A3 BA1/A5

A8/A7 A10/A0
A9/A1 A11/A6
A10/A0 A8/A7
A11/A6 A9/A1
A12/RFU/NC

VPP/NC
VPP/NC

MF
SEN
ZQ

ABI#
RAS# CAS#
CS# WE#
CAS# RAS#
WE# CS#

WCK01# WCK23#
WCK01 WCK23

WCK23# WCK01#
WCK23 WCK01

VREFD
VREFD
VREFC

RESET#

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

170-BALL

SGRAM GDDR5

X76@

DQ24 DQ0
DQ25 DQ1
DQ26 DQ2
DQ27 DQ3
DQ28 DQ4
DQ29 DQ5
DQ30 DQ6
DQ31 DQ7
DQ16 DQ8
DQ17 DQ9

DQ18 DQ10
DQ19 DQ11
DQ20 DQ12
DQ21 DQ13
DQ22 DQ14
DQ23 DQ15
DQ8 DQ16
DQ9 DQ17
DQ10 DQ18
DQ11 DQ19
DQ12 DQ20
DQ13 DQ21
DQ14 DQ22
DQ15 DQ23
DQ0 DQ24
DQ1 DQ25
DQ2 DQ26
DQ3 DQ27
DQ4 DQ28
DQ5 DQ29
DQ6 DQ30
DQ7 DQ31

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

H5GQ1H24AFR-T2L_BGA170

3

UV6

MF=0 MF=1 MF=0MF=1

A4

FBA_D32

A2

FBA_D33

B4

FBA_D34

B2

FBA_D35

E4

FBA_D36

E2

FBA_D37

F4

FBA_D38

F2

FBA_D39

A11

A13
B11
B13
E11
E13
F11
F13
U11

FBA_D48

U13

FBA_D49

T11

FBA_D50

T13

FBA_D51

N11

FBA_D52

N13

FBA_D53

M11

FBA_D54

M13

FBA_D55

U4
U2
T4
T2
N4
N2
M4
M2

B1

D1

F1

M1

P1

T1

G2

L2

B3

D3

F3

H3

K3

M3

P3

T3

E5

N5

E10

N10

B12

D12

F12

H12

K12

M12

P12

T12

G13

L13

B14

D14

F14

M14

P14

T14

A1
C1
E1
N1
R1
U1
H2
K2
A3
C3
E3
N3
R3
U3
C4
R4
F5
M5
F10
M10
C11
R11
A12
C12
E12
N12
R12
U12
H13
K13
A14
C14
E14
N14
R14
U14

+1.5VS_VGA

+1.5VS_VGA

10U_0603_6.3V6M

BYTE4

FBA_DBI7#<27>

FBA_DBI5#<27>

FBA_CLK1

FBA_CLK1#

FBA_CKE_H

FBA_MA4_BA2_H
FBA_MA3_BA3_H
FBA_MA2_BA0_H

+1.5VS_VGA

RV136

121_0402_1%

1

2

0.1U_0402_10V7K

12

CV145

FBA_MA5_BA1_H

FBA_MA0_MA10_H
FBA_MA6_MA11_H

FBA_MA7_MA8_H
FBA_MA1_MA9_H

FBA_MA12_RFU_H

RV132

RV134

+FBA_VREFD_H

+FBA_VREFC1

+1.5VS_VGA

1

CV143

2

0.1U_0402_10V7K

1K_0402_1%

1K_0402_1%

FBA_ABI#_H

FBA_CAS#_H

FBA_WE#_H

FBA_RAS#_H

FBA_CS#_H

FBA_WCK3_N
FBA_WCK3

FBA_WCK2_N
FBA_WCK2

FBA_RST#_H

0.1U_0402_10V7K

BYTE6

6 SIDE

UV

1

2

CV187

2

1

1U_0603_25V6

1

1

CV87

2

1U_0603_25V6

1

CV85

CV88

CV86

2

2

1U_0603_25V6

1U_0603_25V6

FBA_EDC7

FBA_EDC5

FBA_DBI7#

FBA_DBI5#

12

12

1

2

C2

EDC0 EDC3

C13

EDC1 EDC2

R13

EDC2 EDC1

R2

EDC3 EDC0

D2

DBI0# DBI3#

D13

DBI1# DBI2#

P13

DBI2# DBI1#

P2

DBI3# DBI0#

J12

CK

J11

CK#

J3

CKE#

H11

BA0/A2 BA2/A4

K10

BA1/A5 BA3/A3

K11

BA2/A4 BA0/A2

H10

BA3/A3 BA1/A5

K4

A8/A7 A10/A0

H5

A9/A1 A11/A6

H4

A10/A0 A8/A7

K5

A11/A6 A9/A1

J5

A12/RFU/NC

A5

VPP/NC

U5

VPP/NC

J1

MF

J10

SEN

J13

ZQ

J4

ABI#

G3

RAS# CAS#

G12

CS# WE#

L3

CAS# RAS#

L12

WE# CS#

D5

WCK01# WCK23#

D4

WCK01 WCK23

P5

WCK23# WCK01#

P4

WCK23 WCK01

A10

VREFD

U10

VREFD

J14

VREFC

J2

RESET#

H1

VSS

K1

VSS

B5

VSS

G5

VSS

L5

VSS

T5

VSS

B10

VSS

D10

VSS

G10

VSS

L10

VSS

P10

VSS

T10

VSS

H14

VSS

K14

VSS

G1

VDD

L1

VDD

G4

VDD

L4

VDD

C5

VDD

R5

VDD

C10

VDD

R10

VDD

D11

VDD

G11

VDD

L11

VDD

P11

VDD

G14

VDD

L14

VDD

170-BALL

SGRAM GDDR5

X76@

CV144

2

DQ24 DQ0
DQ25 DQ1
DQ26 DQ2
DQ27 DQ3
DQ28 DQ4
DQ29 DQ5
DQ30 DQ6
DQ31 DQ7
DQ16 DQ8
DQ17 DQ9

DQ18 DQ10
DQ19 DQ11
DQ20 DQ12
DQ21 DQ13
DQ22 DQ14
DQ23 DQ15
DQ8 DQ16
DQ9 DQ17
DQ10 DQ18
DQ11 DQ19
DQ12 DQ20
DQ13 DQ21
DQ14 DQ22
DQ15 DQ23
DQ0 DQ24
DQ1 DQ25
DQ2 DQ26
DQ3 DQ27
DQ4 DQ28
DQ5 DQ29
DQ6 DQ30
DQ7 DQ31

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

H5GQ1H24AFR-T2L_BGA170

1

A4

FBA_D56

A2

FBA_D57

B4

FBA_D58

B2

FBA_D59

E4

FBA_D60

E2

FBA_D61

F4

FBA_D62

F2

FBA_D63

A11
A13
B11
B13
E11
E13
F11
F13
U11

FBA_D40

U13

FBA_D41

T11

FBA_D42

T13

FBA_D43

N11

FBA_D44

N13

FBA_D45

M11

FBA_D46

M13

FBA_D47

U4
U2
T4
T2
N4
N2
M4
M2

B1
D1
F1
M1
P1
T1
G2
L2
B3
D3
F3
H3
K3
M3
P3
T3
E5
N5
E10
N10
B12
D12
F12
H12
K12
M12
P12
T12
G13
L13
B14
D14
F14
M14
P14
T14

A1
C1
E1
N1
R1
U1
H2
K2
A3
C3
E3
N3
R3
U3
C4
R4
F5
M5
F10
M10
C11
R11
A12
C12
E12
N12
R12
U12
H13
K13
A14
C14
E14
N14
R14
U14

+1.5VS_VGA

B

TE7

Y

BYTE5

GDDR5
Mo

de H - Mirror Mode Mapping

Address

FBx_CMD0

FBx_CMD1

FBx_CMD2

FBx_CMD3

FBx_CMD4

FBx_CMD5

FBx_CMD6

FBx_CMD7

FBx_CMD8

FBx_CMD9

FBx_CMD10

FBx_CMD11

FBx_CMD12

FBx_CMD13

FBx_CMD14

FBx_CMD15

FBx_CMD16

FBx_CMD17

FBx_CMD18

FBx_CMD19

FBx_CMD20

FBx_CMD21

FBx_CMD22

FBx_CMD23

FBx_CMD24

FBx_CMD25

FBx_CMD26

FBx_CMD27

FBx_CMD28

FBx_CMD29

FBx_CMD30

FBx_CMD31

0..31

CS#

A3_BA3

A2_BA0

A4_BA2

A5_BA1

WE#

A7_A8

A6_A11

ABI#

A12_RFU

A0_A10

A1_A9

RAS#

RST#

CKE#

CAS#

DATA Bus

32..63

CS#

A3_BA3

A2_BA0

A4_BA2

A5_BA1

WE#

A7_A8

A6_A11

ABI#

A12_RFU

A0_A10

A1_A9

RAS#

RS

T#

CKE#

CAS#

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THISSHEE T NORTHE INFORMATIONIT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THISSHEE T NORTHE INFORMATIONIT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THISSHEE T NORTHE INFORMATIONIT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTPRIOR WRI TTEN CONSENT OF LC FUTURECENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTPRIOR WRI TTEN CONSENT OF LC FUTURECENTER.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTPRIOR WRI TTEN CONSENT OF LC FUTURECENTER.

2011/11/01

2011/11/01

2011/11/01

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2012/12/31

2012/12/31

2012/12/31

Title

N14P-VRAM A Upper

N14P-VRAM A Upper

N14P-VRAM A Upper

Size Doc ument Number Rev

Size Doc ument Number Rev

Size Doc ument Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Y400S-NM-A141

Y400S-NM-A141

Y400S-NM-A141

Monday, March 11, 2013

Monday, March 11, 2013

Monday, March 11, 2013

1

of

of

of

29 65

29 65

29 65

1.0

1.0

1.0

5

4

3

2

1

Memory Partition C - Lower 32 bits

UV7

MF=0 MF=1 MF=0MF=1

C2

FBC_EDC0

FBC_CLK0
FBC_CLK0#

FBC_CKE_L

FBC_MA2_BA0_L
FBC_MA5_BA1_L
FBC_MA4_BA2_L
FBC_MA3_BA3_L

FBC_MA7_MA8_L

FBC_MA1_MA9_L
FBC_MA0_MA10_L
FBC_MA6_MA11_L

FBC_MA12_RFU_L

RV147

RV149

FBC_ABI#_L

FBC_RAS#_L

FBC_CS#_L

FBC_CAS#_L

FBC_WE#_L

FBC_WCK0_N
FBC_WCK0

FBC_WCK1_N
FBC_WCK1

+FBC_VREFD_L

+FBC_VREFC0

+FBC_VREFC0

1

CV61

2

+1.5VS_VGA

+FBC_VREFD_L

1

2

820P_0402_25V7

1

CV157

2

0.1U_0402_10V7K

FBC_EDC2

FBC_DBI0#

FBC_DBI2#

12

1K_0402_1%

12

1K_0402_1%

FBC_RST#_L

CV62

1

2

0.1U_0402_10V7K

FBC_D[0..31]<27>

D D

C C

B B

A A

FBC_EDC[3..0]<27>

Follow DG

FBC_CLK0

FBC_CLK0#

MEM_VREF<23,28,29,31>

+1.5VS_VGA

1 2

RV37 40.2_0402_1%

RV155
160_0402_1%

@

1 2

1 2

RV39 40.2_0402_1%

13

D

2

G

S

7 SIDE

UV

1

2

CV91

CV199

2

1

1U_0603_25V6

10U_0603_6.3V6M

FBC_MA12_RFU_L<27>

1

CV195

2

0.01U_0402_25V7K

RV216

1 2

931_0402_1%

1.33K_0402_1%

549_0402_1%

RV217

1 2

931_0402_1%

1.33K_0402_1%

QV13

2N7002W-T/R7_SOT323-3

1

1

CV92

CV89

2

2

1U_0603_25V6

1U_0603_25V6

FBC_CLK0<27>

FBC_CLK0#<27>

FBC_CKE_L<27>

FBC_MA2_BA0_L<27>
FBC_MA5_BA1_L<27>
FBC_MA4_BA2_L<27>
FBC_MA3_BA3_L<27>

FBC_MA7_MA8_L<27>

FBC_MA1_MA9_L<27>
FBC_MA0_MA10_L<27>
FBC_MA6_MA11_L<27>

FBC_ABI#_L<27>

FBC_RAS#_L<27>

FBC_CS#_L<27>

FBC_CAS#_L<27>

FBC_WE#_L<27>

FBC_WCK0_N<27>
FBC_WCK0<27>

FBC_WCK1_N<27>
FBC_WCK1<27>

FBC_RST#_L<27>

+1.5VS_VGA

RV159

549_0402_1%

RV160

+1.5VS_VGA

RV161

RV162

1

2

1U_0603_25V6

CV90

RV151

12

12

12

12

0.1U_0402_10V7K

FBC_DBI0#<27>

FBC_DBI2#<27>

12

121_0402_1%

820P_0402_25V7

1

CV160

2

CV159

EDC0 EDC3

C13

EDC1 EDC2

R13

EDC2 EDC1

R2

EDC3 EDC0

D2

DBI0# DBI3#

D13

DBI1# DBI2#

P13

DBI2# DBI1#

P2

DBI3# DBI0#

J12

CK

J11

CK#

J3

CKE#

H11

BA0/A2 BA2/A4

K10

BA1/A5 BA3/A3

K11

BA2/A4 BA0/A2

H10

BA3/A3 BA1/A5

K4

A8/A7 A10/A0

H5

A9/A1 A11/A6

H4

A10/A0 A8/A7

K5

A11/A6 A9/A1

J5

A12/RFU/NC

A5

VPP/NC

U5

VPP/NC

J1

MF

J10

SEN

J13

ZQ

J4

ABI#

G3

RAS# CAS#

G12

CS# WE#

L3

CAS# RAS#

L12

WE# CS#

D5

WCK01# W CK23#

D4

WCK01 WCK23

P5

WCK23# W CK01#

P4

WCK23 WCK01

A10

VREFD

U10

VREFD

J14

VREFC

J2

RESET#

H1

VSS

K1

VSS

B5

VSS

G5

VSS

L5

VSS

T5

VSS

B10

VSS

D10

VSS

G10

VSS

L10

VSS

P10

VSS

T10

VSS

H14

VSS

K14

VSS

G1

VDD

L1

VDD

G4

VDD

L4

VDD

C5

VDD

R5

VDD

C10

VDD

R10

VDD

D11

VDD

G11

VDD

L11

VDD

P11

VDD

G14

VDD

L14

VDD

170-BALL

SGRAM GDDR5

X76@

DQ24 DQ0
DQ25 DQ1
DQ26 DQ2
DQ27 DQ3
DQ28 DQ4
DQ29 DQ5
DQ30 DQ6
DQ31 DQ7
DQ16 DQ8
DQ17 DQ9

DQ18 DQ10
DQ19 DQ11
DQ20 DQ12
DQ21 DQ13
DQ22 DQ14
DQ23 DQ15
DQ8 DQ16
DQ9 DQ17
DQ10 DQ18
DQ11 DQ19
DQ12 DQ20
DQ13 DQ21
DQ14 DQ22
DQ15 DQ23
DQ0 DQ24
DQ1 DQ25
DQ2 DQ26
DQ3 DQ27
DQ4 DQ28
DQ5 DQ29
DQ6 DQ30
DQ7 DQ31

H5GQ1H24AFR-T2L_BGA170

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

A4

FBC_D0

A2

FBC_D1

B4

FBC_D2

B2

FBC_D3

BY

+1.5VS_VGA

TE0

BYTE2

+1.5VS_VGA

10U_0603_6.3V6M

2

1

CV207

UV8 SIDE

1

CV95

2

1U_0603_25V6

FBC_DBI3#<27>

FBC_DBI1#<27>

+1.5VS_VGA

12

RV152

121_0402_1%

1

1

1

CV96

2

1U_0603_25V6

CV94

CV93

2

2

1U_0603_25V6

1U_0603_25V6

0.1U_0402_10V7K

E4

FBC_D4

E2

FBC_D5

F4

FBC_D6

F2

FBC_D7

A11
A13
B11
B13
E11
E13
F11
F13
U11

FBC_D16

U13

FBC_D17

T11

FBC_D18

T13

FBC_D19

N11

FBC_D20

N13

FBC_D21

M11

FBC_D22

M13

FBC_D23

U4
U2
T4
T2
N4
N2
M4
M2

B1
D1
F1
M1
P1
T1
G2
L2
B3
D3
F3
H3
K3
M3
P3
T3
E5
N5
E10
N10
B12
D12
F12
H12
K12
M12
P12
T12
G13
L13
B14
D14
F14
M14
P14
T14

A1
C1
E1
N1
R1
U1
H2
K2
A3
C3
E3
N3
R3
U3
C4
R4
F5
M5
F10
M10
C11
R11
A12
C12
E12
N12
R12
U12
H13
K13
A14
C14
E14
N14
R14
U14

FBC_MA0_MA10_L
FBC_MA6_MA11_L

FBC_MA12_RFU_L

1

CV163

2

FBC_EDC3

FBC_EDC1

FBC_DBI3#

FBC_DBI1#

FBC_CLK0
FBC_CLK0#
FBC_CKE_L

FBC_MA4_BA2_L
FBC_MA3_BA3_L
FBC_MA2_BA0_L
FBC_MA5_BA1_L

FBC_MA7_MA8_L
FBC_MA1_MA9_L

12

RV148

1K_0402_1%

12

RV150

1K_0402_1%

FBC_ABI#_L

FBC_CAS#_L

FBC_WE#_L

FBC_RAS#_L

FBC_CS#_L

FBC_WCK1_N
FBC_WCK1

FBC_WCK0_N
FBC_WCK0

+FBC_VREFD_L

+FBC_VREFC0

FBC_RST#_L

+1.5VS_VGA

1

CV161

2

0.1U_0402_10V7K

UV8

MF=0 MF=1 MF=0MF=1

C2

EDC0 EDC3

C13

EDC1 EDC2

R13

EDC2 EDC1

R2

EDC3 EDC0

D2

DBI0# DBI3#

D13

DBI1# DBI2#

P13

DBI2# DBI1#

P2

DBI3# DBI0#

J12

CK

J11

CK#

J3

CKE#

H11

BA0/A2 BA2/A4

K10

BA1/A5 BA3/A3

K11

BA2/A4 BA0/A2

H10

BA3/A3 BA1/A5

K4

A8/A7 A10/A0

H5

A9/A1 A11/A6

H4

A10/A0 A8/A7

K5

A11/A6 A9/A1

J5

A12/RFU/NC

A5

VPP/NC

U5

VPP/NC

J1

MF

J10

SEN

J13

ZQ

J4

ABI#

G3

RAS# CAS#

G12

CS# WE#

L3

CAS# RAS#

L12

WE# CS#

D5

WCK01# W CK23#

D4

WCK01 WCK23

P5

WCK23# W CK01#

P4

WCK23 WCK01

A10

VREFD

U10

VREFD

J14

VREFC

J2

RESET#

H1

VSS

K1

VSS

B5

VSS

G5

VSS

L5

VSS

T5

VSS

B10

VSS

D10

VSS

G10

VSS

L10

VSS

P10

VSS

T10

VSS

H14

VSS

K14

VSS

G1

VDD

L1

VDD

G4

VDD

L4

VDD

C5

VDD

R5

VDD

C10

VDD

R10

VDD

D11

VDD

G11

VDD

L11

VDD

P11

VDD

G14

VDD

L14

VDD

170-BALL

SGRAM GDDR5

X76@

1

CV162

2

0.1U_0402_10V7K

DQ24 DQ0
DQ25 DQ1
DQ26 DQ2
DQ27 DQ3
DQ28 DQ4
DQ29 DQ5
DQ30 DQ6
DQ31 DQ7
DQ16 DQ8
DQ17 DQ9

DQ18 DQ10
DQ19 DQ11
DQ20 DQ12
DQ21 DQ13
DQ22 DQ14
DQ23 DQ15
DQ8 DQ16
DQ9 DQ17
DQ10 DQ18
DQ11 DQ19
DQ12 DQ20
DQ13 DQ21
DQ14 DQ22
DQ15 DQ23
DQ0 DQ24
DQ1 DQ25
DQ2 DQ26
DQ3 DQ27
DQ4 DQ28
DQ5 DQ29
DQ6 DQ30
DQ7 DQ31

H5GQ1H24AFR-T2L_BGA170

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

A4

FBC_D24

A2

FBC_D25

B4

FBC_D26

B2

FBC_D27

E4

FBC_D28

E2

FBC_D29

F4

FBC_D30

F2

FBC_D31

A11
A13
B11
B13
E11
E13
F11
F13
U11

FBC_D8

U13

FBC_D9

T11

FBC_D10

T13

FBC_D11

N11

FBC_D12

N13

FBC_D13

M11

FBC_D14

M13

FBC_D15

U4
U2
T4
T2
N4
N2
M4
M2

B1
D1
F1
M1
P1
T1
G2
L2
B3
D3
F3
H3
K3
M3
P3
T3
E5
N5
E10
N10
B12
D12
F12
H12
K12
M12
P12
T12
G13
L13
B14
D14
F14
M14
P14
T14

A1
C1
E1
N1
R1
U1
H2
K2
A3
C3
E3
N3
R3
U3
C4
R4
F5
M5
F10
M10
C11
R11
A12
C12
E12
N12
R12
U12
H13
K13
A14
C14
E14
N14
R14
U14

+1.5VS_VGA

BYTE3

GDDR5
Mode H - Mirror Mode Mapping

BYTE1

Address

FBx_CMD0

FBx_CMD1

FBx_CMD2

FBx_CMD3

FBx_CMD4

FBx_CMD5

FBx_CMD6

FBx_CMD7

FBx_CMD8

FBx_CMD9

FBx_CMD10

FBx_CMD11

FBx_CMD12

FBx_CMD13

FBx_CMD14

FBx_CMD15

FBx_CMD16

FBx_CMD17

FBx_CMD18

FBx_CMD19

FBx_CMD20

FBx_CMD21

FBx_CMD22

FBx_CMD23

FBx_CMD24

FBx_CMD25

FBx_CMD26

FBx_CMD27

FBx_CMD28

FBx_CMD29

FBx_CMD30

FBx_CMD31

0..31

CS#

A3_BA3

A2_BA0

A4_BA2

A5_BA1

WE#

A7_A8

A6_A11

ABI#

A12_RFU

A0_A10

A1_A9

RAS#

RST#

CKE#

CAS#

DATA Bus

32..63

CS#

A3_BA3

A2_BA0

A4_BA2

A5_BA1

WE#

A7_A8

A6_A11

ABI#

A12_RFU

A0_A10

A1_A9

RAS#

RS

T#

CKE#

CAS#

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF LC FU TURE CENTER. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF LC FU TURE CENTER. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF LC FU TURE CENTER. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENTER.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENTER.

2011/11/01

2011/11/01

2011/11/01

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2012/12/31

2012/12/31

2012/12/31

Title

N14P-VRAM C Lower

N14P-VRAM C Lower

N14P-VRAM C Lower

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Y400S-NM-A141

Y400S-NM-A141

Y400S-NM-A141

Monday, March 11, 2013

Monday, March 11, 2013

Monday, March 11, 2013

1

30 65

30 65

30 65

1.0

1.0

1.0

5

4

3

2

1

Memory Partition C - Upper 32 bits

UV9

MF=0 MF=1 MF=0MF=1

C2

FBC_EDC4

FBC_CLK1#

FBC_MA0_MA10_H
FBC_MA6_MA11_H
FBC_MA12_RFU_H

1

CV64

2

820P_0402_25V7

CV167

0.1U_0402_10V7K

FBC_EDC6

FBC_DBI4#

FBC_DBI6#

FBC_CLK1

FBC_CKE_H

FBC_MA2_BA0_H
FBC_MA5_BA1_H
FBC_MA4_BA2_H
FBC_MA3_BA3_H

FBC_MA7_MA8_H
FBC_MA1_MA9_H

12

RV163

1K_0402_1%

12

RV165

1K_0402_1%

FBC_ABI#_H

FBC_RAS#_H

FBC_CS#_H

FBC_CAS#_H

FBC_WE#_H

FBC_WCK2_N
FBC_WCK2

FBC_WCK3_N
FBC_WCK3

+FBC_VREFD_H

+FBC_VREFC1

FBC_RST#_H

+1.5VS_VGA

1

1

CV164

2

2

0.1U_0402_10V7K

FBC_D[63..32]<27>

D D

FBC_EDC[7..4]<27>

Follow DG

1 2

FBC_CLK1

RV41 40.2_0402_1%

FBC_CLK1#

RV171
160_0402_1%

@

1 2

1 2

RV48 40.2_0402_1%

1 2

1 2

13

D

2

G

QV15

S

2N7002W-T/R7_SOT323-3

+1.5VS_VGA

9 SIDE

UV

1

2

CV245

2

1

1U_0603_25V6

10U_0603_6.3V6M

1

2

0.01U_0402_25V7K

RV218

931_0402_1%

RV219

931_0402_1%

CV99

1U_0603_25V6

CV215

549_0402_1%

1.33K_0402_1%

549_0402_1%

1.33K_0402_1%

1

CV100

2

1U_0603_25V6

+1.5VS_VGA

RV175

RV176

+1.5VS_VGA

RV177

RV178

1

CV97

2

C C

B B

MEM_VREF<23,28,29,30>

A A

FBC_DBI4#<27>

FBC_DBI6#<27>

FBC_CLK1<27>

FBC_CLK1#<27>

FBC_CKE_H<27>

FBC_MA2_BA0_H<27>
FBC_MA5_BA1_H<27>
FBC_MA4_BA2_H<27>
FBC_MA3_BA3_H<27>

FBC_MA7_MA8_H<27>

FBC_MA1_MA9_H<27>
FBC_MA0_MA10_H<27>
FBC_MA6_MA11_H<27>
FBC_MA12_RFU_H<27>

12

RV167

121_0402_1%

FBC_ABI#_H<27>

FBC_RAS#_H<27>

FBC_CS#_H<27>

FBC_CAS#_H<27>

FBC_WE#_H<27>

FBC_WCK2_N<27>
FBC_WCK2<27>

FBC_WCK3_N<27>
FBC_WCK3<27>

FBC_RST#_H<27>

12

+FBC_VREFC1

12

1

CV63

2

820P_0402_25V7

12

+FBC_VREFD_H

12

1

1

CV98

2

2

1U_0603_25V6

0.1U_0402_10V7K

CV165

EDC0 EDC3

C13

EDC1 EDC2

R13

EDC2 EDC1

R2

EDC3 EDC0

D2

DBI0# DBI3#

D13

DBI1# DBI2#

P13

DBI2# DBI1#

P2

DBI3# DBI0#

J12

CK

J11

CK#

J3

CKE#

H11

BA0/A2 BA2/A4

K10

BA1/A5 BA3/A3

K11

BA2/A4 BA0/A2

H10

BA3/A3 BA1/A5

K4

A8/A7 A10/A0

H5

A9/A1 A11/A6

H4

A10/A0 A8/A7

K5

A11/A6 A9/A1

J5

A12/RFU/NC

A5

VPP/NC

U5

VPP/NC

J1

MF

J10

SEN

J13

ZQ

J4

ABI#

G3

RAS# CAS#

G12

CS# WE#

L3

CAS# RAS#

L12

WE# CS#

D5

WCK01# W CK23#

D4

WCK01 WCK23

P5

WCK23# W CK01#

P4

WCK23 WCK01

A10

VREFD

U10

VREFD

J14

VREFC

J2

RESET#

H1

VSS

K1

VSS

B5

VSS

G5

VSS

L5

VSS

T5

VSS

B10

VSS

D10

VSS

G10

VSS

L10

VSS

P10

VSS

T10

VSS

H14

VSS

K14

VSS

G1

VDD

L1

VDD

G4

VDD

L4

VDD

C5

VDD

R5

VDD

C10

VDD

R10

VDD

D11

VDD

G11

VDD

L11

VDD

P11

VDD

G14

VDD

L14

VDD

170-BALL

SGRAM GDDR5

X76@

DQ24 DQ0
DQ25 DQ1
DQ26 DQ2
DQ27 DQ3
DQ28 DQ4
DQ29 DQ5
DQ30 DQ6
DQ31 DQ7
DQ16 DQ8
DQ17 DQ9

DQ18 DQ10
DQ19 DQ11
DQ20 DQ12
DQ21 DQ13
DQ22 DQ14
DQ23 DQ15
DQ8 DQ16
DQ9 DQ17
DQ10 DQ18
DQ11 DQ19
DQ12 DQ20
DQ13 DQ21
DQ14 DQ22
DQ15 DQ23
DQ0 DQ24
DQ1 DQ25
DQ2 DQ26
DQ3 DQ27
DQ4 DQ28
DQ5 DQ29
DQ6 DQ30
DQ7 DQ31

H5GQ1H24AFR-T2L_BGA170

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

A4

FBC_D32

A2

FBC_D33

B4

FBC_D34

B2

FBC_D35

E4

FBC_D36

E2

FBC_D37

F4

FBC_D38

F2

FBC_D39

A11
A13
B11
B13
E11
E13
F11
F13
U11

FBC_D48

U13

FBC_D49

T11

FBC_D50

T13

FBC_D51

N11

FBC_D52

N13

FBC_D53

M11

FBC_D54

M13

FBC_D55

U4
U2
T4
T2
N4
N2
M4
M2

B1
D1
F1
M1
P1
T1
G2
L2
B3
D3
F3
H3
K3
M3
P3
T3
E5
N5
E10
N10
B12
D12
F12
H12
K12
M12
P12
T12
G13
L13
B14
D14
F14
M14
P14
T14

A1
C1
E1
N1
R1
U1
H2
K2
A3
C3
E3
N3
R3
U3
C4
R4
F5
M5
F10
M10
C11
R11
A12
C12
E12
N12
R12
U12
H13
K13
A14
C14
E14
N14
R14
U14

+1.5VS_VGA

+1.5VS_VGA

10U_0603_6.3V6M

2

1

BY

BYTE6

UV10 SIDE

CV227

1U_0603_25V6

TE4

FBC_DBI7#<27>

FBC_DBI5#<27>

+1.5VS_VGA

12

RV168

121_0402_1%

1

2

1

1

CV103

2

1U_0603_25V6

1

CV101

CV104

CV102

2

2

1U_0603_25V6

1U_0603_25V6

0.1U_0402_10V7K

FBC_CLK1

FBC_CLK1#

FBC_CKE_H

FBC_MA4_BA2_H
FBC_MA3_BA3_H
FBC_MA2_BA0_H
FBC_MA5_BA1_H

FBC_MA0_MA10_H
FBC_MA6_MA11_H

FBC_MA7_MA8_H
FBC_MA1_MA9_H

FBC_MA12_RFU_H

RV164

1K_0402_1%

RV166

1K_0402_1%

FBC_ABI#_H

FBC_CAS#_H

FBC_WE#_H

FBC_RAS#_H

FBC_CS#_H

FBC_WCK3_N
FBC_WCK3

FBC_WCK2_N
FBC_WCK2

+FBC_VREFD_H

+FBC_VREFC1

+1.5VS_VGA

1

CV170

2

0.1U_0402_10V7K

FBC_EDC7

FBC_EDC5

FBC_DBI7#

FBC_DBI5#

12

12

FBC_RST#_H

1

CV168

2

0.1U_0402_10V7K

1

CV169

2

UV10

MF=0 MF=1 MF=0MF=1

C2

EDC0 EDC3

C13

EDC1 EDC2

R13

EDC2 EDC1

R2

EDC3 EDC0

D2

DBI0# DBI3#

D13

DBI1# DBI2#

P13

DBI2# DBI1#

P2

DBI3# DBI0#

J12

CK

J11

CK#

J3

CKE#

H11

BA0/A2 BA2/A4

K10

BA1/A5 BA3/A3

K11

BA2/A4 BA0/A2

H10

BA3/A3 BA1/A5

K4

A8/A7 A10/A0

H5

A9/A1 A11/A6

H4

A10/A0 A8/A7

K5

A11/A6 A9/A1

J5

A12/RFU/NC

A5

VPP/NC

U5

VPP/NC

J1

MF

J10

SEN

J13

ZQ

J4

ABI#

G3

RAS# CAS#

G12

CS# WE#

L3

CAS# RAS#

L12

WE# CS#

D5

WCK01# W CK23#

D4

WCK01 WCK23

P5

WCK23# W CK01#

P4

WCK23 WCK01

A10

VREFD

U10

VREFD

J14

VREFC

J2

RESET#

H1

VSS

K1

VSS

B5

VSS

G5

VSS

L5

VSS

T5

VSS

B10

VSS

D10

VSS

G10

VSS

L10

VSS

P10

VSS

T10

VSS

H14

VSS

K14

VSS

G1

VDD

L1

VDD

G4

VDD

L4

VDD

C5

VDD

R5

VDD

C10

VDD

R10

VDD

D11

VDD

G11

VDD

L11

VDD

P11

VDD

G14

VDD

L14

VDD

170-BALL

SGRAM GDDR5

X76@

DQ24 DQ0
DQ25 DQ1
DQ26 DQ2
DQ27 DQ3
DQ28 DQ4
DQ29 DQ5
DQ30 DQ6
DQ31 DQ7
DQ16 DQ8
DQ17 DQ9

DQ18 DQ10
DQ19 DQ11
DQ20 DQ12
DQ21 DQ13
DQ22 DQ14

DQ23 DQ15
DQ8 DQ16
DQ9 DQ17

DQ10 DQ18

DQ11 DQ19

DQ12 DQ20

DQ13 DQ21

DQ14 DQ22

DQ15 DQ23
DQ0 DQ24
DQ1 DQ25
DQ2 DQ26
DQ3 DQ27
DQ4 DQ28
DQ5 DQ29
DQ6 DQ30
DQ7 DQ31

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

H5GQ1H24AFR-T2L_BGA170

A4

FBC_D56

A2

FBC_D57

B4

FBC_D58

B2

FBC_D59

E4

FBC_D60

E2

FBC_D61

F4

FBC_D62

F2

FBC_D63

A11
A13
B11
B13
E11
E13
F11
F13
U11

FBC_D40

U13

FBC_D41

T11

FBC_D42

T13

FBC_D43

N11

FBC_D44

N13

FBC_D45

M11

FBC_D46

M13

FBC_D47

U4
U2
T4
T2
N4
N2
M4
M2

B1
D1
F1
M1
P1
T1
G2
L2
B3
D3
F3
H3
K3
M3
P3
T3
E5
N5
E10
N10
B12
D12
F12
H12
K12
M12
P12
T12
G13
L13
B14
D14
F14
M14
P14
T14

A1
C1
E1
N1
R1
U1
H2
K2
A3
C3
E3
N3
R3
U3
C4
R4
F5
M5
F10
M10
C11
R11
A12
C12
E12
N12
R12
U12
H13
K13
A14
C14
E14
N14
R14
U14

+1.5VS_VGA

BYTE7

BYTE5

GDDR5
Mode H - Mirror Mode Mapping

Address

FBx_CMD0

FBx_CMD1

FBx_CMD2

FBx_CMD3

FBx_CMD4

FBx_CMD5

FBx_CMD6

FBx_CMD7

FBx_CMD8

FBx_CMD9

FBx_CMD10

FBx_CMD11

FBx_CMD12

FBx_CMD13

FBx_CMD14

FBx_CMD15

FBx_CMD16

FBx_CMD17

FBx_CMD18

FBx_CMD19

FBx_CMD20

FBx_CMD21

FBx_CMD22

FBx_CMD23

FBx_CMD24

FBx_CMD25

FBx_CMD26

FBx_CMD27

FBx_CMD28

FBx_CMD29

FBx_CMD30

FBx_CMD31

0..31

CS#

A3_BA3

A2_BA0

A4_BA2

A5_BA1

WE#

A7_A8

A6_A11

ABI#

A12_RFU

A0_A10

A1_A9

RAS#

RST#

CKE#

CAS#

DATA Bus

32..63

CS#

A3_BA3

A2_BA0

A4_BA2

A5_BA1

WE#

A7_A8

A6_A11

ABI#

A12_RFU

A0_A10

A1_A9

RAS#

RS

T#

CKE#

CAS#

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF LC FU TURE CENTER. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF LC FU TURE CENTER. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF LC FU TURE CENTER. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENTER.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENTER.

2011/11/01

2011/11/01

2011/11/01

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2012/12/31

2012/12/31

2012/12/31

Title

N13P-VRAM C Upper

N13P-VRAM C Upper

N13P-VRAM C Upper

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Y400S-NM-A141

Y400S-NM-A141

Y400S-NM-A141

Monday, March 11, 2013

Monday, March 11, 2013

Monday, March 11, 2013

1

31 65

31 65

31 65

1.0

1.0

1.0

5

4

3

2

1

11/11 for 2nd VGA fan

D D

C C

B B

need to notic EC

PCIE_CTX_GRX_N[0..15]<23,5>

PCIE_CTX_GRX_P[0..15]<23,5>

PCIE_CRX_GTX_N[0..15]<23,5>

PCIE_CRX_GTX_P[0..15]<23,5>

PCIE_CRX_GTX_N15
PCIE_CRX_GTX_P15

PCIE_CRX_GTX_N14
PCIE_CRX_GTX_P14

PCIE_CRX_GTX_N13
PCIE_CRX_GTX_P13

PCIE_CRX_GTX_N12
PCIE_CRX_GTX_P12

PCIE_CRX_GTX_N11
PCIE_CRX_GTX_P11

PCIE_CRX_GTX_N10
PCIE_CRX_GTX_P10

PCIE_CRX_GTX_N9
PCIE_CRX_GTX_P9

PCIE_CRX_GTX_N8
PCIE_CRX_GTX_P8

PCIE_CTX_GRX_N[0..15]

PCIE_CTX_GRX_P[0..15]

PCIE_CRX_GTX_N[0..15]

PCIE_CRX_GTX_P[0..15]

12

CV200.22U_0402_10V6K SLI@

12

CV220.22U_0402_10V6K SLI@

12

CV160.22U_0402_10V6K SLI@

12

CV180.22U_0402_10V6K SLI@

12

CV190.22U_0402_10V6K SLI@

12

CV140.22U_0402_10V6K SLI@

12

CV150.22U_0402_10V6K SLI@

12

CV170.22U_0402_10V6K SLI@

12

CV120.22U_0402_10V6K SLI@

12

CV130.22U_0402_10V6K SLI@

12

CV100.22U_0402_10V6K SLI@

12

CV110.22U_0402_10V6K SLI@

12

CV80.22U_0402_10V6K SLI@

12

CV90.22U_0402_10V6K SLI@

12

CV60.22U_0402_10V6K SLI@

12

CV70.22U_0402_10V6K SLI@

PCIE_CTX_GRX_N15
PCIE_CTX_GRX_P15

PCIE_CTX_GRX_N14
PCIE_CTX_GRX_P14

PCIE_CTX_GRX_N13
PCIE_CTX_GRX_P13

PCIE_CTX_GRX_N12
PCIE_CTX_GRX_P12

PCIE_CTX_GRX_N11
PCIE_CTX_GRX_P11

PCIE_CTX_GRX_N10
PCIE_CTX_GRX_P10

PCIE_CTX_GRX_N9
PCIE_CTX_GRX_P9

PCIE_CTX_GRX_N8
PCIE_CTX_GRX_P8

PCIE_CRX_C_GTX_N15
PCIE_CRX_C_GTX_P15

PCIE_CRX_C_GTX_N14
PCIE_CRX_C_GTX_P14

PCIE_CRX_C_GTX_N13
PCIE_CRX_C_GTX_P13

PCIE_CRX_C_GTX_N12
PCIE_CRX_C_GTX_P12

PCIE_CRX_C_GTX_N11
PCIE_CRX_C_GTX_P11

PCIE_CRX_C_GTX_N10
PCIE_CRX_C_GTX_P10

PCIE_CRX_C_GTX_N9
PCIE_CRX_C_GTX_P9

PCIE_CRX_C_GTX_N8
PCIE_CRX_C_GTX_P8

follow MXM 3.0 spec

JSLI1

1

GND

3

NC

5

NC

7

NC

9

NC

11

NC

13

NC

15

NC

17

GND

19

PEG_RX_N7

21

PEG_RX_P7

23

GND

25

PEG_RX_N6

27

PEG_RX_P6

29

GND

31

GND

33

PEG_RX_N5

35

PEG_RX_P5

37

GND

39

PEG_RX_N4

41

PEG_RX_P4

43

GND

45

PEG_RX_N3

47

PEG_RX_P3

49

GND

51

PEG_RX_N2

53

PEG_RX_P2

55

GND

57

PEG_RX_N1

59

PEG_RX_P1

61

GND

63

PEG_RX_N0

65

PEG_RX_P0

67

GND

69

GND

71

PEG_TX_N7

73

PEG_TX_P7

75

GND

77

PEG_TX_N6

79

PEG_TX_P6

81

GND

83
85
87
89
91
93
95
97

99
101
103
105
107
109
111
113
115
117

119
121

PEX_STD_SW#
PEG_TX_N5
PEG_TX_P5
GND
PEG_TX_N4
PEG_TX_P4
GND
PEG_TX_N3
PEG_TX_P3
GND
PEG_TX_N2
PEG_TX_P2
GND
PEG_TX_N1
PEG_TX_P1
GND
PEG_TX_N0
PEG_TX_P0
GND

GND
GND

TE_2199022-1_118P-T ME@

PWR_GOOD

TH_OVERT#

CLK_PCIE_N
CLK_PCIE_P

GND
GND
GND
GND
+19V
+19V
+19V
+19V
+19V
+19V
+19V

+19V
GND
GND
GND
GND
GND
GND

GND
GND
GND

GND

TH_TACH

TH_PWN

AC_DC

PWR_EN

CLK_REQ#

RSVD
RSVD

RSVD

SMB_DAT

SMB_CLK

WAKE#

RSVD
RSVD

GND

GND

GND
GND

B+_SLI

2
4
6
8
10
12
14
16
18
20
22

24
26
28
30
32
34
36
38

+5V

40

+5V

42

+5V

44

+5V

46

+5V

48
50
52

54

NC

56

+3V

58

+3V

60
62

NC

64

NC

66

NC

68

NC

70

NC

72

NC

74
76
78

NC

80
82
84
86
88
90
92
94

NC

96
98

NC

100
102
104
106
108
110
112
114
116
118

120
122

+5VS_SLI

+3VS_SLI

SLI_B+_ON#
SLI_5V_ON#
SUSP#

SLI_FAN_SPEED
SLI_FAN_PWM

VGA_AC_DET_R

S_DGPU_PWROK

S_DGPU_PWR_EN#
CLK2_REQ_GPU#_R
S_NVDD_PWR_EN
S_DGPU_RST
SLAVE_PRESENT#
PCH_THRMTRIP#_R
PLT_RST#
GC6_EVENT_SLI#
EC_SMB_DA2
EC_SMB_CK2

GC6_EN

S_DGPU_PWR_EN

CLK_PCIE_2VGA#
CLK_PCIE_2VGA

+3VS

SLI_B+_ON# <52>
SLI_5V_ON# <52>

SUSP# <45,51,55,57>

SLI_FAN_SPEED <41,45>

SLI_FAN_PWM <41,45>

VGA_AC_DET_R <23>
S_DGPU_PWROK <19>

S_DGPU_PWR_EN# <51>

CLK2_REQ_GPU#_R <15>

S_NVDD_PWR_EN <19>
S_DGPU_RST <15,18>

PCH_THRMTRIP#_R <19,23>
PLT_RST# <18,23,37,38,44,45,6>

EC_SMB_DA2 <15,23,40,45>
EC_SMB_CK2 <15,23,40,45>

S_DGPU_PWR_EN <19,51>

CLK_PCIE_2VGA# <15>
CLK_PCIE_2VGA <15>

1 2

RV158 0_0402_5%@

GC6_EN <27>

GC6_EVENT# <19,23,45>

1

2

SLAVE_PRESENT# <19>

CV177

0.01U_0402_25V7K

Close to SLI connector

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2011/11/01

2011/11/01

2011/11/01

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2012/12/31

2012/12/31

2012/12/31

Title

2ND VGA CONN.

2ND VGA CONN.

2ND VGA CONN.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet of

Date: Sheet of

Y400S-NM-A141

Y400S-NM-A141

Y400S-NM-A141

Monday, March 11, 2013

Monday, March 11, 2013

Monday, March 11, 2013

of

32 65

32 65

1

32 65

1.0

1.0

1.0

5

RV92

D D

STRAP0<24>
STRAP1<24>
STRAP2<24>
STRAP3<24>
STRAP4<24>

STRAP0
STRAP1
STRAP2
STRAP3
STRAP4

45.3K_0402_ 1%

1 2

RV93

4.99K_0402_ 1%

@

1 2

RV94

24.9K_0402_ 1%

@

1 2

4

+3VS_VGA

RV121

4.99K_0402_ 1%

1 2

1 2

RV122
20K_0402_1 %

@

3

Physical
Strapping pin

ROM_SCLK

ROM_SI

ROM_SO F

STRAP0

TRAP1

S

STRAP2

STRAP3

S

RAP4

T

Power Rail

+3VS_VGA

+3VS_VGA

+3VS_VGA

+3VS_VGA

+3VS_VGA

+3VS_VGA

+3VS_VGA

+3VS_VGA

Logical

trapping Bit3

S

PCI_DEVID[4]

FB[1]

PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0]

SOR3_EXPOSED

RESERVED PCIE_SPEED_

2

3GIO_PAD_CFG_ADR[2] 3GIO_PAD_CFG_ADR[1]3GIO_PAD_CFG_ADR[3]

Logical
Strapping Bit2

SUB_VENDOR

RAM_CFG[2]

B[0]

SER[2] USER[1] USER[0]USER[3]

U

Logical
Strapping Bit1

SLOT_CLK_CFG

R

AM_CFG[1]RAM_CFG[3]

MB_ALT_ADDR

SOR2_EXPOSED SOR1_EXPOSED

CHANGE_GEN3

PCIE_MAX_SPEED DP_PLL_VDD33V

1

Logical
Strapping Bit0

PEX_PLL_EN_TERM

RAM_CFG[0]

VGA_DEVICES

3GIO_PAD_CFG_ADR[0]

SOR0_EXPOSED

RV95

@

45.3K_0402_ 1%

1 2

RV96

4.99K_0402_ 1%

1 2

RV97

24.9K_0402_ 1%

1 2

@

RV124

4.99K_0402_ 1%

1 2

RV125

45.3K_0402_ 1%

1 2

Resistor Values

5K

10K

15K

20K

25K

30K

C C

+3VS_VGA

35K

45K

3GIO_PADCFG

RV98

4.99K_0402_ 1%

@

1 2

ROM_SI<2 4>

ROM_SO<24>

ROM_SCLK<24>

B B

ROM_SI
ROM_SO
ROM_SCLK

X76

RV101
20K_0402_1 %

X76@

1 2

RV99
10K_0402_1 %

1 2

RV102
30K_0402_1 %

@

1 2

RV100

4.99K_0402_ 1%

@

2012-0418 --> Set BOM

1 2

st

ructure as Stuff for ALL SKU

RV103
15K_0402_1 %

1 2

3GIO_PADCFG[3:0]

0000

PEX_PLL_EN_TERM

0

Disable (Default)

1

E

nable

SMBUS_ALT_ADDR

0

0x9E (Default)

1

0x9C (Multi-GPU usage)

Pull-up to
+3VS_VGA

1000

1001

1010

1011

1100

1101

1110

1111

Notebook Default

Pull-down to Gnd

0000

0001

0010

0011

0100

0101

0110

0111

XCLK_417

0

277MHz (Default)

1

Reserved

PCIE_MAX_SPEED

0

Limit to PCIE Gen1

1

PCIE Gen 2/3 Capable

VGA_DEVICE

0

3D Device (Class Code 302h)

1

V

GA Device (Default)

SLOT_CLK_CFG

0

GPU and MCH don't share a common reference clock

1

G

PU and MCH share a common reference clock (Default)

SUB_VENDOR

0

No VBIOS ROM (Default)

1

BIOS ROM is present

USER Straps

User[3:0]

1

000-1100

Customer defined

FB_0_BAR_SIZE

0

Reserved

1

Reserved

2

256MB (Default)

3

Reserved

X76

GPU

Samsung

N13P-GT1
28nm

A A

Hynix

FB Memory (GDDR5)

4G20325FD-FC04 2G 64Mx32

K

K4G10325FG-HC04 1G 32Mx32

H5GQ2H24MFR-T2C 2G 64Mx32

H5GQ1H24BFR-T2C 1G 32Mx32

5GQ2H24AFR-T2C 2G 64Mx32

5

ROM_SI ROM_SO ROM_SCLK STRAP0 STRAP1 STRAP2 STRAP3 STRAP4

PD 30K

EOL

PD 45K

PD 25K

PU 10K

PU 35K

(ALL SKU)

PU 45K PD 5K PD 25K PU 5K PD 45K

PD 20K

PD 5KH

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIA L

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIA L

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIA L
AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D
DEPARTMENT EXCEPT AS A UTHORIZED BY LC FUTURE CENTER NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS A UTHORIZED BY LC FUTURE CENTER NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS A UTHORIZED BY LC FUTURE CENTER NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF LC FUTURE CENTER.

4

2011/11/01

2011/11/01

2011/11/01

3

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

VRAM

Samsung

2012/12/31

2012/12/31

2012/12/31

2

X76

VRAM P/N

X76409JVL01 (2G 64Mx32) SA00005B70J

SA00003RS0JX76409JVL51 (1G 32Mx16)

7

6409JVL02 (2G 64Mx32)

X

SA00004GD0J

SA00004GD1JHynix X76409JVL02 (2G 64Mx32)

X76409JVL52 (1G 32Mx16) SA00003WL1J

Title

Title

Title

N14P_MISC

N14P_MISC

N14P_MISC

Size Document Nu mber Rev

Size Document Nu mber Rev

Size Document Nu mber Rev

Custom

Custom

Custom

Monday, January 14, 2013

Monday, January 14, 2013

Date: Sheet

Date: Sheet

Date: Sheet

Monday, January 14, 2013

Y400S-NM-A141

Y400S-NM-A141

Y400S-NM-A141

1

EOL

of

of

of

33 6 5

33 6 5

33 6 5

1.0

1.0

1.0

5

+LCDVDD_CONN

LVDS_A0#_CONN
LVDS_A0_CONN
LVDS_A1#_CONN
LVDS_A1_CONN
LVDS_A2#_CONN
LVDS_A2_CONN

LVDS_ACLK#_CONN
LVDS_ACLK_CONN

D D

ECR_EN<45>

JLVDS1ME@

112
334
556
778
9910
111112
131314
151516
171718
191920
212122
232324
252526
272728
292930

GND31GND

+LEDVDD

2
4
6

W=60mils

8
10
12
14
16
18
20
22
24
26
28
30

32

INVPWM
EDID_DATA_CONN
EDID_CLK_CONN

R822 4.7K_0402_5%

R891 R_short 0_0402_5%

4

470P_0603_50V8J

9/23 EMI Request

@

12

12

2A 80 mil

C523

1

2

BKOFF#DISPOFF#

1 2

1

R_short 0_0805_5%

C524

4.7U_0805_25V6-K

2

+3VS

R813

BKOFF# <45>

2A 80 mil

B++LEDVDD

1

680P_0402_50V7K

2

C528

3

CMOS Camera

+3VS

@

CMOS_ON#<45>

2

1 2

+3VS

R435

100K_0402_5%

(40 MIL)

C1051

CMOS@

0.1U_0402_16V4Z

CMOS@

1

@

2

Q94 AO3413_SOT23-3

S

1

2

C520

0.1U_0402_16V4Z

D

13

CMOS@

G

2

C1052

0.01U_0402_16V7K

+CMOS_PW_R

1

CMOS@

2

1

R432

0_0603_5%

1 2

CMOS@

1

CMOS@

C518

0.1U_0402_16V4Z

2

+CMOS_PW

1

2

W=40mils

C519

10U_0603_6.3V6M

@

EDID_CLK<17>

VGA_EDID_CLK<23>

EDID_DATA<17>

VGA_EDID_DATA<23>

C C

B B

INVPWM

PCH_ENBKL<17>

VGA_ENBKL<23>

PCH

VGA

EDID_CLK

VGA_EDID_CLK

EDID_DATA

VGA_EDID_DATA

12

R1515

@

0_0402_5%

SLI@

12

R824

0_0402_5%

OPT@

12

R847

20120806 --> ch ange to 0-ohm normal symbol
20

120807 -->

1. R1515 change to "@",

2. R824 change to "SLI@", R84 7 change to "O PT@" W=40mils

LVDS_ACLK#<17>
LVDS_ACLK< 17>
LVDS_A0#<17>
LVDS_A0<17>
LVDS_A1#<17>
LVDS_A1<17>
LVDS_A2#<17>
LVDS_A2<17>

VGA_TXCLK-<24>
VGA_TXCLK+<24>
VGA_TXOUT0-<24>
VGA_TXOUT0+<24>
VGA_TXOUT1-<24>
VGA_TXOUT1+<24>
VGA_TXOUT2-<24>
VGA_TXOUT2+<24>

0_0402_5%

OPT@

1 2

0_0402_5%

SLI@

1 2

0_0402_5%

LVDS_ACLK#
LVDS_ACLK LVDS_ACLK_CONN
LVDS_A0#
LVDS_A0
LVDS_A1#
LVDS_A1
LVDS_A2#
LVDS_A2

VGA_TXCLK­VGA_TXCLK+
VGA_TXOUT0­VGA_TXOUT0+
VGA_TXOUT1­VGA_TXOUT1+
VGA_TXOUT2­VGA_TXOUT2+

1 2

R1210
0_0402_5%

OPT@

1 2

R1199
0_0402_5% S LI@

1 2

R1211
0_0402_5%

OPT@

1 2

R1200
0_0402_5% S LI@

EC_INVT_PWM <45>

VGA_BL_PWM < 23>

PCH_PWM <17>

R1212

R1201

R827

100K_0402_1%

1 2

R1255 0_0402_5%OPT@
R1257 0_0402_5%OPT@
R1259 0_0402_5%OPT@
R1261 0_0402_5%OPT@
R1262 0_0402_5%OPT@
R1265 0_0402_5%OPT@
R1267 0_0402_5%OPT@
R1269 0_0402_5%OPT@

R1260 0_0402_5%
R1264 0_0402_5%
R1263 0_0402_5%SLI@
R1266 0_0402_5%SLI@
R1268 0_0402_5%SLI@
R1270 0_0402_5%SLI@
R1271 0_0402_5%SLI@
R1272 0_0402_5%SLI@

ENBKL <45>

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

SLI@

1 2
1 2

SLI@
1 2
1 2
1 2
1 2
1 2
1 2

EDID_CLK_CONN

EDID_DATA_CONN

LVDS_ACLK#_CONN

LVDS_A0#_CONN
LVDS_A0_CONN
LVDS_A1#_CONN
LVDS_A1_CONN
LVDS_A2#_CONN
LVDS_A2_CONN

LVDS_ACLK#_CONN
LVDS_ACLK_CONN
LVDS_A0#_CONN
LVDS_A0_CONN
LVDS_A1#_CONN
LVDS_A1_CONN
LVDS_A2#_CONN
LVDS_A2_CONN

+CMOS_PW

Fo

r CMOS

USB20_N0<18>
USB20_P0<18>

+3VS

DMIC_CLK<42>

DMIC_DATA<42>

C58

For RF request

@

12

0.047U_0402_16V4Z

USB20_N0
USB20_P0

10

1
2
3
4
5
6
7
8

9

JCMOS1

1
2
3
4
5
6
7
8

GND
GND

ME@

LCDVDD

2N7002DW-T/R7_SOT363-6

A A

VGA_ENVDD<23>

PCH_ENVDD<17>

+LCDVDD_CONN

R816

150_0603_1%

61

Q67A

SLI@

1 2

R1197 0_0402_5%

OPT@

1 2

R1195 0_0402_5%

5

100K_0402_5%

2

100K_0402_5%

+5VALW

12

R1467

@

LCD_ENVDD#

R821

+3VS +3VS

12

R817
100K_0402_5%

1 2

100K_0402_5%

3

0.1U_0402_16V4Z

5

Q67B

2N7002DW-T/R7_SOT363-6

4

12

0.1U_0402_16V4Z

R820

C1050

W=60mils

C530

1

C1046

0.01U_0402_16V7K

@

2

4.7U_0603_6.3V6K

4

EMI request

D59

@

1

S

2

G

2

Q68
AO3413_SOT23-3

D

1

1 3

2

1

1

C531

2

2

W=60mils

C532

0.1U_0402_16V4Z

+LCDVDD_CONN

DMIC_CLK

R1498
0_0402_5%

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUT URE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUT URE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUT URE CENTER.

3

@

1

C934

2

100P_0402_50V8J

2011/11/01

2011/11/01

2011/11/01

@

1 2

INVPWM

DISPOFF#

C525

@

1

2

470P_0402_50V7K

@

1

C527

2

470P_0402_50V7K

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2012/12/31

2012/12/31

2012/12/31

USB20_P0

+3VS

USB20_N0

Title

Title

Title

LVDS/ CMOS/ USB-REDRIVER

LVDS/ CMOS/ USB-REDRIVER

LVDS/ CMOS/ USB-REDRIVER

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Monday, January 14, 2013

Monday, January 14, 2013

Monday, January 14, 2013

4

I/O3

5

VDD

6

I/O4

AZC099-04S.R7G_SOT23-6

Y400S-NM-A141

Y400S-NM-A141

Y400S-NM-A141

1

DMIC_DATA

I/O1

2

GND

3

DMIC_CLK

I/O2

1.0

1.0

1.0

of

of

of

34 65

34 65

1

34 65

A

VGA_CRT _R< 23>

1 1

2 2

3 3

VGA_CRT _G<23 >

VGA_CRT _B<23>

DAC_RED<17>

DAC_GRN<17>

DAC_BLU<1 7>

VGA_CRT _R

VGA_CRT _G

VGA_CRT _B

DAC_RED

DAC_GRN

DAC_BLU

CRT_HSYNC< 17>

VGA_CRT _HSYNC<23>

CRT_VSYNC<17>

VGA_CRT _VSYNC<23>

1 2

R1276 0_0 402_5%

SLI@

1 2

R1273 0_0 402_5%

SLI@

1 2

R1275 0_0 402_5%

SLI@

1 2

R1274 0_0 402_5%

OPT@

1 2

R1181 0_0 402_5%

OPT@

1 2

R1182 0_0 402_5%

OPT@

CRT_HSYNC HS YNC_G

VGA_CRT _HSYNC

CRT_VSYNC

VGA_CRT _VSYNC VSYNC_G

1 2

R1183 0_0 402_5%

R1184 0_0 402_5%

1 2

R1185 0_0 402_5%

OPT@

1 2

R1186 0_0 402_5%

SLI@

OPT@

1 2

SLI@

B

12

R830
150_040 2_1%

C

+5VS +5VS +5VS

3

2

@

D31
BAT54S-7 -F_SOT23-3

DAC_RED _1

DAC_GRN _1

DAC_BLU _1

12

R831
150_040 2_1%

CLOSE TO CONN

C544

0.1U_040 2_16V4Z

C546

0.1U_040 2_16V4Z

+3VS

1

12

R832
150_040 2_1%

+CRT_VC C

1

2

+CRT_VC C

1

2

5

P

A2Y

G

3

5

P

A2Y

G

3

3

2

1

1

C537

C538

2

2

10P_040 2_50V8J

R833

1 2

1K_0402 _5%

OE#

1

OE#

U24
SN74AHC T1G125DCKR_S C70-5

OE#

1

OE#

U25
SN74AHC T1G125DCKR_S C70-5

+CRT_VC C

4

CRT_HSYNC _1

4

CRT_VSYNC _1

10P_040 2_50V8J

3

1

@

D32
BAT54S-7 -F_SOT23-3

1 2

L16 NBQ1005 05T-800Y_0402

1 2

L17 NBQ1005 05T-800Y_0402

1 2

L18 NBQ1005 05T-800Y_0402

1

C539
10P_040 2_50V8J

2

R840

1 2

33_0603 _5%

R839

1 2

33_0603 _5%

2

1

C540

2

10P_040 2_50V8J

CRT_HSYNC _2

CRT_VSYNC _2

@

D33

NBQ1005 05T-800Y_0402

NBQ1005 05T-800Y_0402

1

REDGREENBLUE

BAT54S-7 -F_SOT23-3

1

1

C541

C542

10P_040 2_50V8J

2

2

10P_040 2_50V8J

1 2

L19

1 2

L20

D

+5VS

T75 PAD

RED

CRT_DDC _DAT_CONN
GREEN

JVGA_HS
BLUE

JVGA_VS

CRT_DDC _CLK_CONN

1

@

C545
10P_040 2_50V8J

2

1

C547

@

10P_040 2_50V8J

2

D36

2 1

RB491D_ SC59-3

JVGA_HS

JVGA_VS

+CRT_VC C

F1

0.5A_8V_ KMC3S050RY

W=40mils

CRT_TES T

1

2

CRT_DDC _CLK_CONN

CRT Connector

21

C543

100P_04 02_50V8J

JVGA_VS

+CRT_VC C_CONN

1

C536

0.1U_040 2_16V4Z

2

JCRT1

6

11

1
7

12

2
8

13

3
9

14

4
10
15

5

3

2

1

16

G

17

G

SUYIN_070546 HR015M22BZR

ME@

D8

@

I/O2

GND

I/O1

AZC099-0 4S.R7G_SOT23-6

I/O4

VDD

I/O3

E

6

5

4

JVGA_HS

+5VS

CRT_DDC _DAT_CONN

12

2.2K_0402_5%

C548

@

12

R838

2.2K_040 2_5%

CRT_DDC _DAT_CONN

CRT_DDC _CLK_CONN

1

1

@

C549
68P_040 2_50V8K

2

2

2011/11/ 01

2011/11/ 01

2011/11/ 01

C

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2012/12/ 31

2012/12/ 31

2012/12/ 31

D

Title

Title

Title

CRT CONN.

CRT CONN.

CRT CONN.

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Monday, January 14, 2013

Monday, January 14, 2013

Monday, January 14, 2013

Y400S-NM-A141

Y400S-NM-A141

Y400S-NM-A141

E

35 65

35 65

35 65

of

of

of

1.0

1.0

1.0

G

5

R837

CRT_DDC _DATA<17>

CRT_DDC _CLK<1 7>

VGA_CRT _DATA<23>

VGA_CRT _CLK<23>

4 4

CRT_DDC _DATA

CRT_DDC _CLK

VGA_CRT _DATA

VGA_CRT _CLK

A

1 2

R1189 0_0402_5 %

OPT@

1 2

R1190 0_0402_5 %

OPT@

1 2

R1191 0_0402_5 %

SLI@

1 2

R1192 0_0402_5 %

SLI@

CRT_DDC _DATA_R

CRT_DDC _CLK_R

B

G

2

S

Q73A

2N7002K DWH_SOT36 3-6

Security Class ification

Security Class ification

Security Class ification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

34

D

S

Q73B

2N7002K DWH_SOT36 3-6

61

D

100P_04 02_50V8J

Issued Date

Issued Date

Issued Date

5

WCM-2 012-900T_4P

HDMI_CLK+ _CK

HDMI_CLK-_ CK

D D

C C

B B

HDMI_TX0+ _CK

HDMI_TX0-_ CK

HDMI_TX1+ _CK

HDMI_TX1-_ CK

HDMI_TX2+ _CK

HDMI_TX2-_ CK

HDMI_CLK+ _CONN

HDMI_CLK-_ CONN

HDMI_TX0+ _CONN

HDMI_TX0-_ CONN

HDMI_TX1+ _CONN

HDMI_TX1-_ CONN

HDMI_TX2+ _CONN

HDMI_TX2-_ CONN

R327

680_040 2_1%

OPT@

R324

4

4

1

1

L23

L24

1

1

4

4

WCM-2 012-900T_4P

WCM-2 012-900T_4P

4

4

1

1

L26

L27

1

1

4

4

WCM-2 012-900T_4P

+3VS

R326

680_040 2_1%

OPT@

R323

3

3

2

2

2

2

3

3

3

3

2

2

2

2

3

3

SLI@

1 2

SLI@

1 2

R321 4 99_0402_1%

SLI@

1 2

R322 499_040 2_1%

SLI@

1 2

R323 499_04 02_1%

SLI@

1 2

R324 499 _0402_1%

SLI@

1 2

R325 499_0 402_1%

SLI@

1 2

R326 499_040 2_1%

SLI@

1 2

R327 499_040 2_1%

1 2

R328 100K_0 402_5%

HDMI_CLK+ _CONN

HDMI_CLK-_ CONN

HDMI_TX0+ _CONN

HDMI_TX0-_ CONN

HDMI_TX1+ _CONN

HDMI_TX1-_ CONN

HDMI_TX2+ _CONN

HDMI_TX2-_ CONN

R320

499_040 2_1%

@

1 2

C1016 3.3P_040 2_50V8C

@

1 2

C1015 3.3P_040 2_50V8C

@

1 2

C1018 3.3P_040 2_50V8C

@

1 2

C1017 3.3P_040 2_50V8C

@

1 2

C1020 3.3P_040 2_50V8C

@

1 2

C1019 3.3P_040 2_50V8C

@

1 2

C1022 3.3P_040 2_50V8C

@

1 2

C1021 3.3P_040 2_50V8C

@

13

D

2

G

Q114

2N7002H 1N_SOT23-3

HDMI@

S

4

HDMIDAT_R
HDMICLK_R

2

3

D57
PJSOT24 C 3P C/A SOT-23

@

1

TMDS_B_ HPD<17>

DGPU_HD MI_HPD<2 3>

VGA_HDM I_CLK+<24>
VGA_HDM I_TX0-<24>

VGA_HDM I_TX0+<24>
VGA_HDM I_TX1-<24>

VGA_HDM I_TX1+<24>
VGA_HDM I_TX2-<24>

VGA_HDM I_TX2+<24>

R1486
0_0402_ 5%

VGA_HDM I_CLK-< 24>

3

1 2

L67

VGA_HDM I_CLK

VGA_HDM I_DATA

R885
20K_040 2_5%

12

@

VGA_HDM I_CLK<24>

HDMICLK<17>

VGA_HDM I_DATA<24>

HDMIDAT<17>

+3VS

R862

1M_0402 _5%

1 2

OPT@

R1499
0_0402_ 5%

SLI@

1 2

R859

1K_0402 _5%

12

R864

@

100K_0402_5%

VGA_HDM I_CLK- HDMI_CLK-_ CK

VGA_HDM I_CLK+ HDMI_CLK+ _CK
VGA_HDM I_TX0-

VGA_HDM I_TX0+
VGA_HDM I_TX1-

VGA_HDM I_TX1+
VGA_HDM I_TX2-

VGA_HDM I_TX2+

G

2

1 2

S

for NV recommend

@

12

Q85

13

D

2N7002_ SOT23

HDMI_DET_ R

CV254 0.1U_0 402_10V6KSLI@

CV253 0.1U_0 402_10V6KSLI@
CV256 0.1U_0 402_10V6KSLI@

CV255 0.1U_0 402_10V6KSLI@
CV258 0.1U_0 402_10V6KSLI@

CV257 0.1U_0 402_10V6KSLI@
CV260 0.1U_0 402_10V6KSLI@

CV259 0.1U_0 402_10V6KSLI@

BLM18PG 181SN1D_0603

1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2

HDMICLK

HDMIDAT

1

@

C59
220P_04 02_25V8J

2

HDMI_TX0-_ CK

HDMI_TX0+ _CK
HDMI_TX1-_ CK

HDMI_TX1+ _CK
HDMI_TX2-_ CK

HDMI_TX2+ _CK

2

R1470 0_0 402_5%SLI@

1 2

R1471 0_0 402_5%OPT@

1 2

R1472 0_0 402_5%SLI@

1 2

R1473 0_0 402_5%OPT@

+5VS

R866 0_0402_ 5%@

R865 0_0402_ 5%@
R868 0_0402_ 5%@

R867 0_0402_ 5%@
R870 0_0402_ 5%@

R869 0_0402_ 5%@
R872 0_0402_ 5%@

R871 0_0402_ 5%@

1 2

3

1

1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2

R1468

0_0402_ 5%

OPT@

BSH111_ SOT23-3

2

@

D38
BAT54S-7 -F_SOT23-3

HDMI_DET

+3VS_VG A

+3VS

1 2

1 2

BSH111_ SOT23-3

2

3 1

SGD

2

3 1

SGD

Q80

HDMI@

PMEG2010AEH
IF=0.1A, 0.29V
IF=1A, 0.43V

R860

2.2K_040 2_5%

HDMI@

1 2

HDMIDAT_R

HDMICLK_R

HDMI_CLK-_ CONN

HDMI_CLK+ _CONN
HDMI_TX0-_ CONN

HDMI_TX0+ _CONN
HDMI_TX1-_ CONN

HDMI_TX1+ _CONN
HDMI_TX2-_ CONN

HDMI_TX2+ _CONN

R1469
0_0402_ 5%

SLI@

R861

2.2K_040 2_5%

HDMI@

1 2

1

Q152

HDMI@

HDMICLK_R

HDMIDAT_R

+5VS

21

HDMI@

D37
PMEG201 0AEH_SOD123

21

HDMI@

F2

0.5A_8V_ KMC3S050RY

+5VS_HD MI

1

2

JHDMI1

19

HP_DET

18

+5V

17

DDC/CEC_GND

16

SDA

15

SCL

14

Reserved

13

CEC

12

CK-

11

CK_shield

10

CK+

9

D0-

8

D0_shield

7

D0+

6

D1-

5

D1_shield

4

D1+

3

D2-

2

D2_shield

1

D2+

TAITW_ PDVBR0-19FLBS 4NN4N0

ME@

C561

0.1U_040 2_16V4Z

HDMI@

20

GND

21

GND

22

GND

23

GND

5

680_040 2_1%

OPT@

R320

680_040 2_1%

OPT@

R322

680_040 2_1%

OPT@

TMDS_B_ DATA2#_PCH<17>
TMDS_B_ DATA2_PCH<17>

TMDS_B_ DATA1#_PCH<17>

TMDS_B_ DATA1_PCH<17>
TMDS_B_ DATA0#_PCH<17>
TMDS_B_ DATA0_PCH<17>
TMDS_B_ CLK#_PCH<17>
TMDS_B_ CLK_PCH<17 >

Security Class ification

Security Class ification

Security Class ification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

TMDS_B_ DATA2#_PCH
TMDS_B_ DATA2_PCH
TMDS_B_ DATA1#_PCH
TMDS_B_ DATA1_PCH
TMDS_B_ DATA0#_PCH
TMDS_B_ DATA0_PCH
TMDS_B_ CLK#_PCH
TMDS_B_ CLK_PCH

2011/11/ 01

2011/11/ 01

2011/11/ 01

3

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

1 2

C200 0.1U _0402_10V6KOPT@

1 2

C201 0.1U _0402_10V6KOPT@

1 2

C203 0.1U _0402_10V6KOPT@

1 2

C206 0.1U _0402_10V6KOPT@

1 2

C204 0.1U _0402_10V6KOPT@

1 2

C205 0.1U _0402_10V6KOPT@

1 2

C208 0.1U _0402_10V6KOPT@

1 2

C207 0.1U _0402_10V6KOPT@

2012/12/ 31

2012/12/ 31

2012/12/ 31

2

HDMI_TX2-_ CK
HDMI_TX2+ _CK
HDMI_TX1-_ CK
HDMI_TX1+ _CK
HDMI_TX0-_ CK
HDMI_TX0+ _CK
HDMI_CLK-_ CK
HDMI_CLK+ _CK

@

46@

W/LOG O

HDMI W/O Logo: RO0000001HM

Title

Title

Title

HDMI CONN.

HDMI CONN.

HDMI CONN.

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Monday, March 11, 2013

Monday, March 11, 2013

Monday, March 11, 2013

Y400S-NM-A141

Y400S-NM-A141

Y400S-NM-A141

1

36 65

36 65

36 65

of

of

of

1.0

1.0

1.0

680_040 2_1%

OPT@

R321

680_040 2_1%

OPT@

A A

R325

680_040 2_1%

OPT@

A

B

C

D

E

Mini-Express Card(WLAN/WiMAX)

1 1

LAN_WAKE#<38,45>

R897

1 2

COMBT@

0_0402_5%

R1556

1 2

1K_0402_5%

BT_DISABLE#

COMBT@

For isolate Intel
Rainbow Peak and
Compal debug card.

2 2

PCIE_WAKE#<16,19,38>

WLAN_CLKREQ1#<15>

CLK_PCIE_WLAN1#<15>
CLK_PCIE_WLAN1<15>

PCIE_PRX_DTX_N2<15>
PCIE_PRX_DTX_P2<15>

PCIE_PTX_C_DRX_N2<15>
PCIE_PTX_C_DRX_P2<15>

EC_TX<45>
EC_RX<45>

For EC to detect
d

ebug card insert.

1 2

R1620 0_0402_5%@

PCIE_WAKE#

BT_CTRL_RBT_CTRL
WLAN_CLKREQ1#

PCI_RST#_R
CLK_PCI_DB

1 2

EC_TX

1 2

EC_RX

+3VS_WLAN

100_0402_1%

R887

R888

100_0402_1%

R889
100K_0402_5%

1 2

BT_DISABLE#

JWLN1

1

WAKE#

3

NC

5

NC

7

CLKREQ#

9

GND

11

REFCLK-

13

REFCLK+

15

GND

17

NC

19

NC

21

GND

23

PERn0

25

PERp0

27

GND

29

GND

31

PETn0

33

PETp0

35

GND

37

NC

39

NC

41

NC

LED_WWAN#

43

NC

LED_WLAN#

45

NC

LED_WPAN#

47

NC

49

NC

51

NC

53

GND

TAITW_PFPET0-AFGLBG1ZZ4N0

ME@

SMB_DATA

GND

GND

PERST#

+3.3Vaux

GND

+1.5V

SMB_CLK

GND

USB_D-

USB_D+

GND

+1.5V

GND

+3.3V

GND

9/

18 JP1 Pin2,24,52 contact to +3VS_WLAN for AOAC function

+3VS_WLAN

1

C57

@

2

2

3.3V

4
6

1.5V

8

NC

10

NC

12

NC

14

NC

16

NC

18
20

NC

22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

54

0.047U_0402_16V4Z

+1.5VS_WLAN
LPC_FRAME#_R
LPC_AD3_R
LPC_AD2_R
LPC_AD1_R
LPC_AD0_R

WL_OFF#

PLT_RST#

SMB_CLK_S3_R
SMB_DATA_S3_R

+1.5VS +1.5VS

12

For RF request

USB20_N10 <18>
USB20_P10 <18>

R400
R_short 0_0603_5%

R1541 0_0402_5%@

1 2

R880 0_0402_5%

1 2

R881 0_0402_5%@

1 2

R882 0_0402_5%

1 2

R883 0_0402_5%@

1 2

R884 0_0402_5%@

1

C564

0.1U_0402_16V4Z

2

12

EC_WL_OFF# <45>

PCH_WL_OFF# <18>

PLT_RST# <18,23,32,38,44,45,6>
+3VALW
+3VS_WLAN

SMB_CLK_S3 <12,13,15,46>
SMB_DATA_S3 <12,13,15,46>

Reserve for SW mini-pcie debug card.

eries resistors closed to KBC side.

S

1

C565

0.1U_0402_16V4Z

2

LPC_FRAME#_R
LPC_AD3_R
LPC_AD2_R
LPC_AD1_R
LPC_AD0_R
PCI_RST#_R
CLK_PCI_DB

AOAC_ON#<51>

R873 0_0402_5%@
R874 0_0402_5%@
R875 0_0402_5%@
R876 0_0402_5%@
R878 0_0402_5%@
R879 0_0402_5%@

AOAC@

1 2
1 2
1 2
1 2
1 2
1 2

R436

1 2

100K_0402_5%

+3VALW

AOAC@

0.1U_0402_16V4Z

LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
PLT_RST#

+3VS

1

C526

2

1

2

J8

112

JUMP_43X79

Q104
AO3413_SOT23-3

S

G

AOAC@

@

C1055

0.1U_0402_16V4Z

LPC_FRAME# <14,45>
LPC_AD3 <14,45>
LPC_AD2 <14,45>
LPC_AD1 <14,45>
LPC_AD0 <14,45>

CLK_PCI_DB <18>

@

2

D

13

1

2

C1048

AOAC@

2

+3VS_WLAN

1

AOAC@

C533

0.1U_0402_16V4Z

2

0.01U_0402_25V7K

softstart (RC) will check on EVT PCB

R1557

COMBT@

PCH_BT_DISABLE#<19>

PCH_BT_ON#<19,47> SUSP <10,51,55,57>

0_0402_5%

1 2

2

BT_CTRL

61

D

G

Q157A

S

@

34

D

5

G

Q157B

S

@

2N7002KDWH_SOT363-6

2N7002KDWH_SOT363-6

WLAN&BT Combo m odule circuits

*

BT_CRTL (GPIO22)

PCH_BT_ON#

BT on module
Enable

H

L

BT on module
Disable

L

H

/18 Increase for Intel AOAC fu nction

9

3 3

Mini-Express Card(SSD)

0.1U_0402_16V4Z

1

C566

2

0.01U_0402_25V7K

SATA_DTX_C_IRX_P0<14>

SATA_DTX_C_IRX_N0<14>

SATA_ITX_DRX_N0<14>

4 4

SATA_ITX_DRX_P0<14>

For SSD use:

A

+3VS_SSD

1

C567

2

10U_0805_10V6K

SATA_DTX_C_IRX_P0
SATA_DTX_C_IRX_N0 SATA_DTX_IRX_N0

SATA_DET#<14>

1

C568

2

0.01U_0402_16V7K

0.01U_0402_16V7K

SATA_ITX_DRX_N0
SATA_ITX_DRX_P0

SATA_DET#

R896 0_0402_5%

10U_0805_10V6K

1

@

C569

2

12

C572

12

C573

1 2

@

SATA_DTX_IRX_P0

+3VS_SSD

B

SSD Active:4.5W(1.5A)

+3VS

JSSD1

1

WAKE#

3

NC

5

NC

7

CLKREQ#

9

GND

11

REFCLK-

13

REFCLK+

15

GND

17

NC

19

NC

21

GND

PERST#

23

PERn0

+3.3Vaux

25

PERp0

27

GND

29
31
33
35
37
39
41
43
45
47
49
51

53

+1.5V

GND

SMB_CLK

PETn0

SMB_DATA
PETp0
GND

USB_D-

NC

USB_D+
NC
NC

LED_WWAN#

NC

LED_WLAN#

NC

LED_WPAN#

NC

+1.5V
NC
NC

+3.3V

GND

TAITW_PFPET0-AFGLBG1ZZ4N0

ME@

J5

JUMP_43X79

@

3.3V

GND

1.5V
NC
NC
NC
NC
NC

GND

NC

GND

GND

GND

GND

GND

112

+3VS_SSD

2

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

54

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC F UTURE CENTER. AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC F UTURE CENTER. AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC F UTURE CENTER. AND CONTAINS CON FIDENTIAL
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.

C

2011/11/01

2011/11/01

2011/11/01

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

2012/12/31

2012/12/31

2012/12/31

Title

Title

Title

MINI-CARD CONN.

MINI-CARD CONN.

MINI-CARD CONN.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet

Date: Sheet

Date: Sheet

Y400S-NM-A141

Y400S-NM-A141

Y400S-NM-A141

Monday, March 11, 2013

Monday, March 11, 2013

Monday, March 11, 2013

of

37 65

of

37 65

of

E

37 65

1.0

1.0

1.0

5

Atheros request can't disable LAN power

Layout Notice : Place as close
chip as possible.

D D

LAN_PWR_ON#< 45>

Vendor recomman d reseve the
PU resistor clo se LAN chip

+3V_LAN

PLT_RST#<18,23,32,37,44,45,6>

LAN_PWR_ON#

1 2

R345 4.7K_0402_5%@

0.1U_0402_16V4Z

100K_0402_5%

+3VALW +3V_LAN

C552

R59

12

PLT_RST#

4

J10

@

112

JUMP_43X79

Q70 LP2301ALT1G_SOT-23

1

2

S

G

2

1

@

2

D

13

C1056

0.1U_0402_16V4Z

2

1

C1047

0.01U_0402_25V7K

2

3

+1.7_VDDCT

R1356 0_0402_5%8151@

1 2

R1357 0_0402_5%8161@

1 2

+1.1_DVDDL

20120806 -->
1

. Main source w as EOL, P/N : SHI0000740J

2. Change L74 P /N to "SH00000 GT0J" (has used on SIT by SMT Memo)

Close together

L74

+LX_R +LX

C935

C936

@

1000P_0402_50V7K

1 2

4.7UH_SIA4012-4R7M_20%

1

1

C937

Note: Place Close to LAN chip
L39 DCR< 0.15 ohm

2

2

0.1U_0402_16V4Z

10U_0805_10V4Z

Close to

n40

Pi

Rate current > 1A

+LX

2

X Voltage

L
<Pin 40>

AR8151

AR8161

+1.7V
<VDDCT>

+1.1V
<DVDDL,AVDDL>

FBMA-L11160808601LMA10T_2P

1

1

C980

C967

2

2

1U_0402_6.3V4Z

0.1U_0402_16V4Z

1 2

1

C278

2

4.7U_0603_6.3V6K

L75

R1356,C955

R1357,R1372,L76

1

Configure

FBMA-L11160808601LMA10T_2P

L76

1 2

8161@

+1.1_DVDDL+1.1_AVDDL+1.1_AVDDL_L

Place close to Pin34

U63

Place Close to Chip

1 2

C C

B B

A A

PCIE_PRX_DTX_N1<15>

PCIE_PRX_DTX_P1<15>

PCIE_PTX_C_DRX_N1<15>

PCIE_PTX_C_DRX_P1<15>

CLK_PCIE_LAN#<15>
CLK_PCIE_LAN<15>

PCIE_WAKE#<16,19,37>

LAN_WAKE#<37,45>

20120718 --> fo r LAN wakeup b acklight issue
1

. R1369 to "Mou nt"

2. R1370 ro "@"

CLKREQ_LAN#<15>

Y6

1

1

GND

1

C968

15P_0402_50V8J

25MHZ_10PF_7V25000014

2

20120816 --->

. change P/N to 7V2500014(10pf), SJ10000E80J

1

C946 0.1U_0402_16V7K

C947 0.1U_0402_16V7K

R1369 0_0402_5%

R1370 0_0402_5%@

1

C956

2

0.1U_0402_16V4Z

Near

in13

P

3

GND

2

4

5

1 2

1 2

1 2

1

C957

2

Near
Pin19

3

0.1U_0402_16V4Z

Near
Pin31

LAN_XTALI

LAN_XTALO

1

C969
15P_0402_50V8J

2

1

C958

2

0.1U_0402_16V4Z

PCIE_PRX_C_DTX_N1

PCIE_PRX_C_DTX_P1

PLT_RST#

PCIE_WAKE#_R

LAN_XTALO
LAN_XTALI

+1.1_AVDDL
+1.1_AVDDL
+1.1_AVDDL
+1.1_AVDDL_L
+1.1_AVDDL

1

1

C960

C959

2

2

1U_0402_6.3V4Z

0.1U_0402_16V4Z

Near
Pin6

8161@

29

TX_N

30

36

35

32
33

2

3

25
26

28
27

7
8

4

13
19
31
34

6

41

Atheros

TX_P

AR8151/AR8161

RX_N

RX_P

REFCLK_N
REFCLK_P

PERST#

WAKE#

SMCLK
SMDATA

NC
TESTMODE

XTLO
XTLI

CLKREQ#

AVDDL
AVDDL
AVDDL
AVDDL
AVDDL_REG/AVDDL

GND

AR8161-AL3A-R_QFN40_5X5

4

DVDDL_REG/DVDD L

U63

8151@

SA00003LE20

LED_0
LED_1
LED_2

TRXN0

TRXP0
TRXN1
TRXP1
TRXN2
TRXP2
TRXN3
TRXP3

RBIAS

VDD33

VDDCT/ISOLAN

DVDDL/PPS

AVDDH/AVDD33

AVDDH

AVDDH_REG

H --> Overclock ing mode
L --> Not overc locking mode

38

ACTIVITY#

39

LAN_LINK#

23

LX

LAN_CLK_SEL

12

MDI0-

11

MDI0+

15

MDI1-

14

MDI1+

18

MDI2-

17

MDI2+

21

MDI3-

20

MDI3+

10

LAN_RBIAS

1

+3V_LAN

40

+LX

5

+1.7_VDDCT

24
37

+1.1_DVDDL

16

+AVDDH_AVDD3.3

22

+2.7_AVDDH

9

+2.7_AVDDH

Near
Pin9

R58 10K_0402 _5%

1 2

R1371 2 .37K_0402_1%

Place Close to PIN10

+LX

1

1

C962

C961

2

2

1U_0402_6.3V4Z

0.1U_0402_16V4Z

Near
Pin22

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED B YL C FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED B YL C FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED B YL C FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUT URE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUT URE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUT URE CENTER.

@

MDI0- <39>
MDI0+ <39>
MDI1- <39>
MDI1+ <39>
MDI2- <39>
MDI2+ <39>
MDI3- <39>
MDI3+ <39>

1 2

R1372 30K_0402_5%8161@

1 2

C955 0.1U_0402_16V4Z

8151@

1 2

R1366 0_0402_5%8151@

1

C963

2

0.1U_0402_16V4Z

LAN IC VR

8161 SA000050E1J

No use

Issued Date

Issued Date

Issued Date

3

2011103 for ven dor comment

+3VS

+1.1_DVDDL+1.1_DVDDL_R

C964

Near
Pin37

1

2

0.1U_0402_16V4Z

2

1

C966

C965

1

2

1U_0402_6.3V4Z

Near
Pin24

X

76

X76409JVL04

2011/11/01

2011/11/01

2011/11/01

Place Close to PIN1

1

1

@

1 2

1000P_0402_50V7K

8151@

0.1U_0402_16V4Z

For AR8151: Stuff C966,R1366
For AR8161: NC

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

2

C950

0.1U_0402_16V4Z

SA00003LE2J8151 X76409JVL03

Deciphered Date

Deciphered Date

Deciphered Date

C951

1U_0402_6.3V4Z

2

AM P/N

ACTIVITY# <39>
LAN_LINK# <39>

12

Place Close to LAN chip

MDI0+

MDI0-

+3V_LAN

1

1

@

2

2

C952

C953

10U_0805_10V4Z

10U_0805_10V4Z

MDI1+

MDI1-

MDI2+

MDI2-

MDI3+

C954

MDI3-

1 2

R1358 49.9_0402_1%8151@

1 2

R1359 49.9_0402_1%8151@

1 2

R1360 49.9_0402_1%8151@

1 2

R1361 49.9_0402_1%8151@

1 2

R1362 49.9_0402_1%8151@

1 2

R1363 49.9_0402_1%8151@

1 2

R1364 49.9_0402_1%8151@

1 2

R1365 49.9_0402_1%8151@

Note : C938, C940, C942, 944, reserved for EMI.

For AR8151: Stuff 49.9K and 0.1u
For AR8161: NC

+AVDDH_AVDD3.3 +2.7_AVDDH

1

1

C948

C949

2

2

0.1U_0402_16V4Z

Place close to Pin16

For AR8151: Stuff R1368 for +AVDD3.3
For AR8161: Stuff R1367,C949 for +AVDDH

Title

Title

Title

2012/12/31

2012/12/31

2012/12/31

2

LAN-AR8151/8161

LAN-AR8151/8161

LAN-AR8151/8161

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet of

Date: Sheet of

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

8161@

1 2

R1367 0_0402_5%

8151@

1 2

R1368 0_0402_5%

8161@

1U_0402_6.3V4Z

Y400S-NM-A141

Y400S-NM-A141

Monday, March 11, 2013

Monday, March 11, 2013

Monday, March 11, 2013

Y400S-NM-A141

C938 1000P_0402_50V7K@

C939 0.1U_0402_16V4Z8151@

C940 1000P_0402_50V7K@

C941 0.1U_0402_16V4Z8151@

C942 1000P_0402_50V7K@

C943 0.1U_0402_16V4Z8151@

C944 1000P_0402_50V7K@

C945 0.1U_0402_16V4Z8151@

+3V_LAN

+2.7_AVDDH

1.0

1.0

38 65

38 65

1

38 65

1.0

of

5

4

3

2

1

+1.7_VDDCT

D D

C C

0_0603_5%

6/

23 update

8151@

12

R1373

@

8161S@

0.1U_0402_16V4Z

8161S@

0.1U_0402_16V4Z

1

C976
1U_0402_6.3V4Z

2

C970

C974

+1.7_VDDCT_R

C972

8161S@

0.1U_0402_16V4Z

C975

8161S@

0.1U_0402_16V4Z

2

C970

8151@

0.1U_0402_16V4Z

1

2

C972

8151@

0.1U_0402_16V4Z

1

2

C974

8151@

0.1U_0402_16V4Z

1

2

C975

8151@

0.1U_0402_16V4Z

1

Place close to T49(TCT) pin

MDI3+<38>

MDI3-<38>

MDI2+<38>

MDI2-<38>

MDI1+<38>

MDI1-<38>

MDI0+<38>

MDI0-<38>

MDI3+

MDI3-

MDI2+

MDI2-

MDI1+

MDI1-

MDI0+

MDI0-

T49

1

TCT1

2

TD1+

3

TD1-

4

TCT2

5

TD2+

6

TD2-

7

TCT3

8

TD3+

9

TD3-

10

TCT4

11

TD4+

12

TD4-

NS892402 1G

LAN Transformer

1:1

1:1

1:1

1:1

MCT1

MX1+

MX1-

MCT2

MX2+

MX2-

MCT3

MX3+

MX3-

MCT4

MX4+

MX4-

24

MCT3

23

MDO3+

22

MDO3-

21

MCT2

20

MDO2+

19

MDO2-

18

MCT1

17

MDO1+

16

MDO1-

15

MCT0

14

MDO0+

13

MDO0-

R1374

12

R_short 0_0402_5%

R1375

12

R_short 0_0402_5%

R1377

12

R_short 0_0402_5%

R1376

12

R_short 0_0402_5%

If vendor test result is "ok", need to change as bel

1. Change R1374,R1375,R1376,R1377 to 0 ohm

2. Change R1194 to 75 ohm

3. Mount F6

4. Un mount F3,F4,F5

--> 2012/02/20 : already implement to Sch

BOM option:

1. For GDTx4
R1374/R1375/R13 76/R1377=75 oh m
R1194=0 ohm
MCT0~3=Mount

2. For GDTx1
R1374/R1375/R13 76/R1377=0 ohm
R1194=75 ohm
MCT0=Mount
MCT1~3=Mount

12

R1194
75_0402_5%

1

C973
10P_1206_2KV7K

2

w

o

Place Close to T49

D68

8151S@

MDI2-

B B

MDI2+

MDI0-

MDI0+

1
2
3
4

1
2
3
4

10

1

10

9

2

9

8

3

8

7

4

7

6

556

GND

11

TCLAMP3302N.TCT_SLP2626P10-10

R02

D67

8151S@

10

1

10

9

2

9

8

3

8

7

4

7

6

556

GND

11

TCLAMP3302N.TCT_SLP2626P10-10

R02

MDI3+

MDI3-

MDI1+

MDI1-

Reserve D67,D68 for EMI go ru ral solution

A A

5

Place Close to T49

MCT3

MCT2

MCT1

MCT0

F6

1 2

R

eserve for EMI go rural solut ion

2012-0622 -->

. Change the BOM Structure of LAN SURGE to "@" --> F3, F4, F5

1

2. Del SURGE@ on Y400 BOM, and change the BOM structure of F6 to "Stuff"
20120807 -->

1. Change Lan Surge P/N to "SCV00001F0J" to meet DC400V Lenovo spec

2. Only change P/N(F3,F4,F5 and F6), not used correct symbol.

4

@

F3

1 2

LSE-200NX3216TRLF_1206-2

@

F4

1 2

LSE-200NX3216TRLF_1206-2

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

LSE-200NX3216TRLF_1206-2

Issued Date

Issued Date

Issued Date

@

F5

1 2

LSE-200NX3216TRLF_1206-2

2011/11/01

2011/11/01

2011/11/01

3

LAN_LINK#<38>

C978

470P_0402_50V7K

ACTIVITY#<38>

C979

470P_0402_50V7K

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

1

@

2

1

@

2

2

LAN_LINK#

+3V_LAN

ACTIVITY#

+3V_LAN

2012/12/31

2012/12/31

2012/12/31

AN Conn.

L

JRJ1

ME@

9

R1378

12

220_0402_5%

R1442

220_0402_5%

MDO0+

MDO0-

MDO1+

MDO2+

MDO2-

MDO1-

MDO3+

MDO3-

12

Title

Title

Title

LAN TRANSFORMER

LAN TRANSFORMER

LAN TRANSFORMER

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Green LED-

10

Green LED+

1

PR1+

2

PR1-

3

PR2+

4

PR3+

5

PR3-

6

PR2-

7

PR4+

8

PR4-

11

Yellow LED-

12

Yellow LED+

SANTA_130456-111

Y400S-NM-A141

Y400S-NM-A141

Monday, January 14, 2013

Monday, January 14, 2013

Monday, January 14, 2013

Y400S-NM-A141

1

G2

G1

14

13

39 65

39 65

39 65

1.0

1.0

1.0

of

of

of

5

4

3

2

1

D D

C C

B B

Close U29

C449

2200P_0 402_50V7K

C658

2200P_0 402_50V7K

1

2

1

2

REMOTE1 +

REMOTE1 -

REMOTE2 +

REMOTE2 -

+3VS

Remove +VDD netname

2

C443

0.1U_040 2_16V4Z

1

FAN_PWM & TACH
for PWM FAN

REMOTE1 +

REMOTE1 -

REMOTE2 +

REMOTE2 -

SMSC thermal sensor

laced near by VRAM

p

U29

1

VDD

2

DP1

3

DN1

4

DP2

5

DN2

EMC1403 -2-AIZL-TR_MSOP10

Address 1001_101xb

internal pull up 1.2K to 1.5V
R

for initial thermal

shutdown temp

SMCLK

SMDATA

ALERT#

THERM#

GND

10

9

8

7

6

R624

10K_040 2_5%

EC_SMB_ CK2

EC_SMB_ DA2

12

+3VS

@

EC_SMB_ CK2 <15,23,32,45 >

EC_SMB_ DA2 <15,23,32,45 >

REMOTE1 +

C982

100P_04 02_50V8J

REMOTE1 -

REMOTE2 +

C984

100P_04 02_50V8J

REMOTE2 -

1

@

2

Close to SSD side

1

@

2

C

2

Q137

B

MMST390 4-7-F_SOT323-3

E

3 1

C

2

Q138

B

MMST390 4-7-F_SOT323-3

E

3 1

Under VRAM

REMOTE2+/-:

race width/space:10/10 mil

T
Trace length:<8"

FAN1 Conn

+5VS

JFAN1

1

1

2

2

3

3

4

4

5

G5

6

G6

ACES_85 205-04001

ME@

40 65

40 65

40 65

1

1.0

1.0

1.0

of

of

of

2

C986

10U_080 5_10V6K

A A

Security Class ification

Security Class ification

Security Class ification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2011/11/ 01

2011/11/ 01

2011/11/ 01

3

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

0.1U_040 2_10V7K

1

2012/12/ 31

2012/12/ 31

2012/12/ 31

2

C49

1

@

2

EC_FAN_ SPEED<45>
EC_FAN_ PWM< 45>

Title

Title

Title

EMC THERMAL SENSOR/FAN CONN.

EMC THERMAL SENSOR/FAN CONN.

EMC THERMAL SENSOR/FAN CONN.

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Monday, January 14, 2013

Monday, January 14, 2013

Monday, January 14, 2013

Y400S-NM-A141

Y400S-NM-A141

Y400S-NM-A141

A

B

C

D

E

F

G

H

1 1

J12

@

SATA_ITX_DRX_P1
SATA_ITX_DRX_N1

SATA_DTX_IRX_N1SATA_DTX_C_IRX_N1
SATA_DTX_IRX_P1

2

+5VS_HDD

1

C635

10U_0603_6.3V6M

2

SATA_ITX_DRX_P1<14>
SATA_ITX_DRX_N1<14>

1 2

SATA_DTX_C_IRX_N1<14>

SATA_DTX_C_IRX_P1<14>

+5VS

2 2

1

C631
1000P_0402_50V7K

2

SATA_DTX_C_IRX_P1

1

C632

0.1U_0402_16V4Z

2

C627 0.01U_0402_16V7K

1 2

C628 0.01U_0402_16V7K

+5VS

1

C633
1U_0603_10V4Z

2

JUMP_43X79

1

C634

10U_0603_6.3V6M

2

112

SATA HDD Conn.

JHDD1

ME@

1

GND

2

A+

3

A-

4

GND

5

B-

6

B+

7

GND

8

VCC3.3

9

VCC3.3

10

VCC3.3

11

GND

12

GND

13

GND

14

VCC5

15

VCC5

16

VCC5

17

GND

18

RESERVED

19

GND

20

VCC12

21

VCC12

22

VCC12

23

GND

24

GND

SANTA_190302-1

SATA_ITX_DRX_P2_CONN<14>
SATA_ITX_DRX_N2_CONN<14>

SATA_DTX_C_IRX_N2<14>

SATA_DTX_C_IRX_P2<14>

SLI_FAN_SPEED<32,45>

ODD_DETECT#<19>

ODD_DA#_R<18>
SLI_FAN_PWM<32,45>

SATA_ITX_DRX_P2_CONN
SATA_ITX_DRX_N2_CONN

SATA_DTX_C_IRX_N2
SATA_DTX_C_IRX_P2

+5VS_ODD

+3VS

1 2

C629 0.01U_0402_16V7K

1 2

C630 0.01U_0402_16V7K

1 2

R1479 R_short 0_0402_5%

1 2

R1476 0 _0402_5%

@

1 2

R710 0_0402_5%

@

1 2

R921 10K_0402_5%

1 2

R1497 0 _0402_5%@

1 2

R1494 R_short 0_0402_5%

SATA_DTX_IRX_N2
SATA_DTX_IRX_P2

SATA ODD Conn.

1
2
3
4
5
6
7

8

9
10
11

ODD_DA#

12

JODD2

ME@

GND
A+
A­GND
B­B+
GND

DP
+5V
+5V
MD
GND

GND

GND13GND

SANTA_202404-1

15
14

ODD Power Control

J6

@

2

112

JUMP_43X79

Q88 AO3413_SOT23-3

S

G

1

2

2

2

1

AO3413
VGS= -4.5V, Id=-3A, Rds<97m ohm

D

13

2

C638

0.01U_0402_16V7K

1

C1057

0.01U_0402_16V7K@

1

C639
10U_0603_6.3V6M

2

+5VS_ODD

1

2

C637

0.1U_0402_16V4Z

ODD_EN#

5

G

+5VS_ODD

12

34

D

S

R1477
470_0603_5%

@

Q89B

2N7002KDWH_SOT363-6

100K_0402_5% @

2

G

12

R1478
100K_0402_5%

+5VALW +5VS

12

R923

61

D

S

12

R1496
100K_0402_5%

R1110

12

100K_0402_5%

Q89A
2N7002KDWH_SOT363-6

C1049

0.1U_0402_16V4Z

ODD_EN#

3 3

ODD_EN<19>

4 4

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

A

B

C

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

D

2011/11/01

2011/11/01

2011/11/01

E

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

F

2012/12/31

2012/12/31

2012/12/31

Title

HDD/ODD CONN.

HDD/ODD CONN.

HDD/ODD CONN.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Monday, January 14, 2013

Monday, January 14, 2013

Monday, January 14, 2013

G

Y400S-NM-A141

Y400S-NM-A141

Y400S-NM-A141

of

of

of

41 65

41 65

41 65

H

1.0

1.0

1.0

A

B

C

D

E

F

G

H

LA1

+5VS

600ohms @100MHz 1A
P

1 1

1 2

FBMA-L11160808601LMA10T_2P

/N: SM01000BU00

1

CA13

2

4.7U_0805_10V4Z

+5VS_AVDD

1

CA14

2

0.1U_0402_16V4Z

Place near UA8. Pin25

+5VS

600ohms @100MHz 2A
P/N: SM01000EE00

1 2

R_short 0_0805_5%

1

2

CA7

CA6

2

1

0.1U_0402_16V4Z

4.7U_0603_6.3V6K

+5VS_PVDD

1

CA8

2

0.1U_0402_16V4Z

UA8

Place near UA8. Pin39, Pin46

RA5

2012-0418 --> C hannge EAPD ne tname to EAPD#

2 2

+3VS

RA475

4.7K_0402_5%@

HDA_RST_AUDIO#

1 2

CA1368

@

100P_0402_50V8J~N

3 3

MIC Sense --> RA1639 place near pin13

apless HP Sense --> RA1638 place near pin34

C

MIC_JD<49>

PLUG_IN<49>

EAPD#<43>

HDA_SDOUT_AUDIO<14> MIC2_R <49>

HDA_BITCLK_AUDIO<14>

HDA_SDIN0<14>

HDA_SYNC_AUDIO<14>

HDA_RST_AUDIO#<14>

PLUG_IN

EAPD#

HDA_SDOUT_AUDIO

HDA_BITCLK_AUDIO

HDA_SDIN0 HDA_SDIN0_R

HDA_SYNC_AUDIO

HDA_RST_AUDIO#

RA1639 20K_0402_1%

RA1638 39.2K_0402_1%

1 2

CA1288 2.2U_0603_6.3V6K

CA19 2.2U_0603_6.3V6K

CA20 4.7U_0603_6.3V6K

22_0402_5%

20K_0402_1%

12

12

12

12

+MIC1_VREFO_R

+MIC1_VREFO_L

RA1637

12

RA1640

12

Del RA3, RA4

PC_BEEP

JDREF

CBN

CBP

CPVEE

LDO_CAP

10 mils

10 mils

SENSEAMIC_JD

For EMI

HDA_SDOUT_AUDIOHDA_SYNC_AUDIO

2

CA1278
10P_0402_50V8J

1

1

CA1282

@

22P_0402_50V8J~N

2

@

RA1635

0_0402_5%

2

CA1285

@

10P_0402_50V8J

1

12

HDA_BITCLK_AUDIO

47

DAPD/COMB_JACK

4

PD#

5

SDATA-OUT

6

BIT-CLK

8

SDATA-IN

10

SYNC

11

RESET#

12

PCBEEP

19

JDREF

20

MONO-OUT(PORT-H)

13

Sense A

18

Sense-B

35

CBN

36

CBP

34

CPVEE

28

LDO-CAP

29

MIC2-VREFO

30

MIC1-VREFO-R

31

MIC1-VREFO-L

42

PVSS1

43

PVSS2

7

DVSS

ALC269Q-VC2-GR_QFN48_6X6

+5VS_AVDD

RA7

1 2

R_short 0_0603_5%

+3VS_DVDD

1

CA15

2

0.1U_0402_16V4Z

Place near UA8. Pin1

+5VS_AVDD

+5VS_AVDD

2

1

CA22

CA21

1

VREF

AVSS1

AVSS2

2

0.1U_0402_16V4Z

4.7U_0603_6.3V6K

Place near UA8. Pin38

30 mils

24

SPKOUT_R1

23

SPKOUT_L1

22

C_MIC2

21

17

16

15

14

40

41

44

45

33

32

48

3

2

27

26

37

49

CA1277 2.2U_0603_6.3V6K

C_MIC1

CA1276 2.2U_0603_6.3V6K

10 mils

10 mils

HPOUTR_R

HPOUTL_R

SPDIF SPDIF_OUT

DMIC_CLK_R

DMIC_DATA_R DMIC_DATA

10 mils

AC97_VREF

R945
FBMA-10-100505-301T_2P

R955
FBMA-10-100505-301T_2P
R954 R_short 0_0402_5%

+3VS_DVDD

+3VS_DVDDIO

25

39

46

PVDD1

PVDD2

38

AVDD1

AVDD2

9

1

DVDD1

DVDD-IO

LINE1-R(PORT-C-R)

LINE1-L(PORT-C-L)

MIC1-R(PORT-B-R)

MIC1-L(PORT-B-L)

MIC2-R(PORT-F-R)

MIC2-L(PORT-F-L)

LINE2-R(PORT-E-R)

LINE2-L(PORT-E-L)

SPK-OUT-L+

SPK-OUT-L-

SPK-OUT-R-

SPK-OUT-R+

HPOUT-R(PORT-A-R)

HPOUT-L(PORT-A-L)

SPDIF-OUT

GPIO1/DMIC-CLK

GPIO0/DMIC-DATA

Thermal PAD

AGND

+3VS_DVDD +3VS_DVDDIO

120813 --> RA6 symbol

20
from R_short to Bead
symbol

SPKOUT_R1 <43>

SPKOUT_L1 <43>

12

12

R3 75_0402_5%

R4 75_0402_5%

12

12

1 2

1 2

12

RA6

1 2

FBMA-10-100505-101T 0402

P/N: SM01000DI0 J

E

xternal SPK (One Channel)

MIC2_R

MIC1_R

HP_OUTR

HP_OUTL

EMI Request

DMIC_CLK

+3VS_DVDDIO

Place near UA8. Pin1

1
Change CA17 typ e to 0603

MIC1_R <49>

1

CA17

2

@

10U_0603_6.3V6M

1/07 -->

Ext. MIC

HP_OUTR <49>

HP_OUTL <49>

SPDIF_OUT <49>

DMIC_CLK <34>

DMIC_DATA <34>

10 mils

2

CA1290

1

1

CA1291

2

1U_0603_10V4Z

Close to UA8.Pin27

0.1U_0402_16V4Z

@

CA16

CA18

+3VS_DVDD+3VS

1

2

1U_0603_10V4Z

1

2

0.1U_0402_16V4Z

HeadPhone

SPDIF

Int. MIC

Pin Assignment Location Function

PC Beep

4 4

EC Beep

PCH Beep

BEEP#<45>

HDA_SPKR<14>

A

1 2

CA4 0.1U_0402_ 16V4Z

1 2

CA5 0.1U_0402_ 16V4Z

B

12

RA2

@

10K_0402_5%

RA1

1 2

33_0402_5%

PC_BEEPPC_BEEP1

C

RA1647

1 2

@

0_0402_5%

DGND AGND

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

D

2011/11/01

2011/11/01

2011/11/01

E

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

SPK-OUT (Pin40/41/44/45)

Capless HP-OUT (Pin32/33)

MIC1(Pin21/22) External Mic in

Title

Title

2012/12/31

2012/12/31

2012/12/31

F

Title

HD AUDIO ALC269Q-VC3

HD AUDIO ALC269Q-VC3

HD AUDIO ALC269Q-VC3

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Monday, January 14, 2013

Monday, January 14, 2013

Monday, January 14, 2013

G

Internal

External

Y400S-NM-A141

Y400S-NM-A141

Y400S-NM-A141

Int Speaker

Headphone out

42 65

42 65

42 65

H

1.0

1.0

1.0

of

of

of

A

B

C

D

E

F

G

H

B+

1 1

2 2

1A, W=40 mils

R_short 0_0402_5%

R899

0_0402_5%

R898

LA57

12

0_0603_5%

B+_PVDD

One channel analog input

+5VS

12

@

12

2

CA1

CA2

1

22U_1210_25V6K~D

2

2uf*3, 10uf*8 for Damage issue

St

uff --> CA1, CA2, CA3, CA1374, CA1375 and CA1376

SPKOUT_L1<42>

SPKOUT_R1<42>

+3VALW

2

2

CA3

1

22U_1210_25V6K~D

22U_1210_25V6K~D

SPKOUT_L1

SPKOUT_R1

1U_0402_6.3V6K

Change BOM structure to @
for leakage

12

@

CA1369

10U_0805_25V6K

B+_PVDD

1 2

1 2

C45

R960 0_0402_5%@

@

CA1370

1

2

1 2

12

1

C43 1U_0402_6.3V6K

C44 1U_0402_6.3V6K

R1407 10K_0402_5%

12

@

10U_0805_25V6K

C46

1U_0402_6.3V6K

1U_0402_6.3V6K

12

@

CA1371

CA1372

10U_0805_25V6K

C42

1 2

1 2

AMP OFF#

1U_0402_6.3V6K

12

12

@

@

CA1373

10U_0805_25V6K

10U_0805_25V6K

+5VS

U73

4

VS

21

PVDD

22

PVDD

8

INL+

12

INR+

9

INL-

11

INR-

7

LIM_TH

13

TEMPLOCK

15

SHUTDOWN

14

RELEASE

1

C47

MAX98400BETGLFT_TQFN-EP24_4X4

2

12

12

12

OUTL+

OUTL­OUTL-

OUTR­OUTR-

OUTR+

GND
PGND
PGND
PGND
PGND

1U_0603_25V6

CA1376

10U_0805_25V6K

5

G1

6

G2

3

1
2

17
18

16

10
19
20
23
24

25

EP

CA1374

CA1375

10U_0805_25V6K

10U_0805_25V6K

C40

SPKOUT_L1+

SPKOUT_L2-

SPKOUT_R2-

SPKOUT_R1+

1

1U_0603_25V6

2

GAIN1
GAIN2

C41

2012-0429 --> Change C42~C47 Cap to X5R type for Vendor suggestion

B+_PVDD

B+ = 19V

1

2

2012-0418 --> W=40 mils

LA56 R_short 0_0603_5%

LA58 R_short 0_0603_5%

LA61 R_short 0_0603_5%

LA60 R_short 0_0603_5%

12

12

12

12

Add JUMP for la yout route

SPK_L1

SPK_L2

SPK_R2

SPK_R1

AIN SETTING

G

AIN1

GND GND

*

NC GND

+5VS GND

GND NC

NC NC

+5VS NC

2012-0418 --> Add R892 for Gain setting

+5VS

GAIN1

GAIN2

R892

1 2

0_0402_5%

@

12

R895
0_0402_5%

GAIN2 GAIN SETTING (dB)G

12

R890
0_0402_5%

9 (Default)

13

16.7

20.1

23.3

26.4

2012-0418 --> Set R890 BOM structure as Stuff

3 3

EC_MUTE#<45>

EAPD#<42>

2012-0622 --> change these BOM structure for BOBO noise issue

1. R958, R959 --> "UnStuff"

2. U74, C1064 --> "Stuff"

4 4

A

EC_MUTE#

1 2

R959 0_0402_5%@

1

IN1

2

EAPD#

IN2

1 2

R958 0_0402_5%

+3VS

2

5

P

G

3

@

1

4

O

U74
SN74AHC1G08DCKR_SC70-5

B

C1064

0.1U_0402_10V7K

AMP OFF#

C

SPK_R1

SPK_R2

SPK_L1

SPK_L2

2

3

D62

@

AZ5125-02S.R7G_SOT23-3

1

Reserve for ESD request.

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

D

2

3

D61
AZ5125-02S.R7G_SOT23-3

1

CA9 1000P_0402_50V7K~N@

CA10 1000P_0402_50V7K~N@

CA11 1000P_0402_50V7K~N@

CA12 1000P_0402_50V7K~N@

@

1 2

1 2

1 2

1 2

2011/11/01

2011/11/01

2011/11/01

E

20

09/11/02 Modify

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

F

2012/12/31

2012/12/31

2012/12/31

Speaker Conn.

JSPK1

ME@

SPK_L1
SPK_L2
SPK_R1
SPK_R2

Title

Title

Title

AMP-MAX98400BETG+T

AMP-MAX98400BETG+T

AMP-MAX98400BETG+T

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Monday, January 14, 2013

Monday, January 14, 2013

Monday, January 14, 2013

G

1

1

2

2

3

3

4

4

5

G5

6

G6

ACES_85205-04001

Y400S-NM-A141

Y400S-NM-A141

Y400S-NM-A141

of

of

of

43 65

43 65

43 65

H

1.0

1.0

1.0

5

R1458

R_short 0_0603_5%

D D

+1.8VS_CARD

+3VS_CARD

+1.8VS_CARD

1 2

C1027

2.2U_0603_6.3V6K

Please close to pin43

PLT_RST#

+CRD_POWER

C C

B B

W=20mils

SD_CD#
MS_CD#
XD_CD#

12

U71

5

APVDD

10

APV18

36

TAV33

19

DV33

20

DV33

44

DV33

18

DV18

37

DV18

43

SDDV33_18

1

XRSTN

2

XTEST

13

CPPE_N

21

CR1_LEDN

17

CR1_PCTLN

16

CR1_CD0N/WAKEN

15

CR1_CD1N

14

CR2_CD2N

33

SPI_CSN

34

SPI_SO

35

SPI_SI

30

SPI_SCK

39

TXIN

6

APGND

31

GND

32

GND

38

GND

JMB389-LGAZ0C_LQFP48_7X7

+3VS_CARD+3VS

JMB389

Power

System

GND

PCIECard Reader

1

2

C1034

0.1U_0402_16V4Z

Close to pin10

XD_CD#

A A

SD_CD#

C1044

0.1U_0402_16V4Z

@

1

C1045

0.1U_0402_16V4Z

2

@

5

1

2

MDIO6

MDIO13

1 2

R1465
1K_0402_5%

1 2

R1466
1K_0402_5%

4

3

APCLKN

4

APCLKP

APREXT

APRXN

APRXP
APTXN
APTXP

MDIO0
MDIO1
MDIO2
MDIO3
MDIO4
MDIO5
MIDO6
MDIO7
MDIO8

MDIO9
MDIO10
MDIO11
MDIO12
MDIO13
MDIO14

7
9
8
11
12

48
47
46
45
41
42
24
40
29
28
27
26
25
23
22

APREXT

PCIE_PRX_C_DTX_N4
PCIE_PRX_C_DTX_P4

MDIO0
MDIO1
MDIO2
MDIO3
MDIO4
MDIO5
MDIO6
MDIO7
MDIO8
MDIO9
MDIO10
MDIO11
MDIO12
MDIO13
MDIO14

C1036

0.1U_0402_16V4Z

R_short 0_0402_5%

1

2

Close to pin5->1000P->0.1u->10u

+CRD_POWER

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

4

CLK_PCIE_CARD_PCH#
CLK_PCIE_CARD_PCH

1 2

R1461

12K_0402_1%

1 2

C1026 .1U_0402_16V7K

1 2

C1028 .1U_0402_16V7K

R1463

1 2

+1.8VS_CARD

1

2

C1037

10U_0805_10V6K

Issued Date

Issued Date

Issued Date

3

CLK_PCIE_CARD_PCH# <15>
CLK_PCIE_CARD_PCH <15>

PCIE_PTX_C_DRX_N4
PCIE_PTX_C_DRX_P4
PCIE_PRX_DTX_N4
PCIE_PRX_DTX_P4

R1464

1 2

MDIO5_R MDIO5_RR

1

@

2

R_short 0_0402_5%

C1031
22P_0402_50V8J

@

2011/11/01

2011/11/01

2011/11/01

+3VS_CARD

1

2

C1038

0.1U_0402_16V4Z

3

close to JREAD1 pin 9

close to JREAD1 pin 17

close to JREAD1 pin 36

PCIE_PTX_C_DRX_N4 <15>
PCIE_PTX_C_DRX_P4 <15>
PCIE_PRX_DTX_N4 <15>
PCIE_PRX_DTX_P4 <15>

+CRD_POWER

1

C1029

10U_0805_10V6K

Close to CONN.

1

2

C1039

0.1U_0402_16V4Z

Close to pin 44

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

1

2

C1041

C1040

@

0.1U_0402_16V4Z

ose to pin 36

Cl

Deciphered Date

Deciphered Date

Deciphered Date

2

C1030

0.1U_0402_16V4Z

1

2

0.1U_0402_16V4Z

(40mil)

800mA

1

2

MDIO0
MDIO1
MDIO2
MDIO3
MDIO8
MDIO9
MDIO10

MDIO4
MDIO6
MDIO14
XD_CD#
MDIO13
MDIO12
MDIO5_RR
MDIO7

2012/12/31

2012/12/31

2012/12/31

2

MDIO5_R

MDIO5_R

MDIO5_RR

R1459

100_0402_5%

R1460

100_0402_5%

R1462

100_0402_5%

Close to connector for EMI request.

JREAD1

22

30
29
28
27
26
25
24
23

33
32
34
39
38
37
36
35

31
40

41
42

ME@

XD-VCC

XD10-D0
XD11-D1
XD12-D2
XD13-D3
XD14-D4
XD15-D5
XD16-D6
XD17-D7

XD07-WE
XD08-WP
XD06-ALE
XD01-CD
XD02-R/B
XD03-RE
XD04-CE
XD05-CLE

XD GND
XD GND

SD CD/WP GND
SD CD/WP GND

T-SOL_144-131300 2600_40P_NR-T

1

C1042

0.1U_0402_16V4Z

2

Close to pin 37Close to pin 19,20

Title

Title

Title

CARD READER JMB389

CARD READER JMB389

CARD READER JMB389

Size Documen t Number Re v

Size Documen t Number Re v

Size Documen t Number Re v

B

B

B

Date: Sheet

Date: Sheet

2

Date: Sheet

12

@

12

@

12

@

+1.8VS_CARD

@

1 2

C1023

100P_0402_50V8J

@

1 2

C1024

100P_0402_50V8J

@

1 2

C1025

100P_0402_50V8J

11

SD4-VDD

18

MS9-VCC

9

SD5-CLK

SD2-CMD

SD-CD

SD-WP

SD6-VSS
SD3-VSS

MS6-INS

MS2-BS

MS1-VSS

C1043

4
3
21
19
16
1
2

6
13

17
10
8
12
15
14
7
5
20

SD7-DAT0
SD8-DAT1
SD9-DAT2
SD1-DAT3

MS8-SCLK
MS4-DATA0
MS3-DATA1
MS5-DATA2
MS7-DATA3

MS10-VSS

1

10U_0805_10V6K

2

Close to pin 18

Y400S-NM-A141

Y400S-NM-A141

Monday, January 14, 2013

Monday, January 14, 2013

Monday, January 14, 2013

Y400S-NM-A141

MDIO5_R
MDIO0
MDIO1
MDIO2
MDIO3
MDIO4
SD_CD#MDIO11
MDIO6

MDIO5_R
MDIO0
MDIO1
MDIO2
MDIO3
MS_CD#
MDIO4

1

(40mil)

1

+CRD_POWER

(40mil)

1

2

C1032

0.1U_0402_16V4Z

of

of

of

44 65

44 65

44 65

1

2

C1033

0.1U_0402_16V4Z

1.0

1.0

1.0

EC_SCI#/ EC_SMI# pull up to PCH

EC_SMI#<19>

EC_SCI#<19>

Support DC S5 Charge

+3VALW

NOS5C@

1 2

R1404
100K_0402_5%

+3VL

S5C@

1 2

R1405
100K_0402_5%

EC_SMB_CK1<49,53,62>
EC_SMB_DA1<49,53,62>

EC_SMB_CK2<15,23,32,40>
EC_SMB_DA2<15,23,32,40>

Please place R1435
close to EC within 790mil

H_PECI<6>

For Deep S3

D70

12

EC_SMI#_R

RB751V-40_SOD323-2

D71

12

EC_SCI#_R

RB751V-40_SOD323-2

pull up to PCH

1

C999
1U_0402_6.3V6K

2

KSO[0..15]<46>

KSI[0..7]<46>

EC_SMB_CK1
EC_SMB_DA1

EC_SMB_CK2
EC_SMB_DA2

Reserved SMBus channel 0
for debugging

H_PECI PECI_EC

ECR_EN<34>

CPU1.5V_S3_GATE<10>

FB_CLAMP<23,27>

KBRST#<19>
SERIRQ<14>
LPC_FRAME#<14,37>
LPC_AD3<14,37>
LPC_AD2<14,37>
LPC_AD1<14,37>
LPC_AD0<14,37>
CLK_PCI_EC<18>

BATT_LEN#<53>

PLT_RST#<18,23,32,37,38,44,6>

GATEA20<19>

KSO[0..15]

KSI[0..7]

LAN_PWR_ON#<38>

PM_SLP_S3#<16>
PM_SLP_S4#<16>

EC_RSMRST#< 16>
ON/OFF<50>

NOVO#<50>

USB_ON#<48,49>

DPWROK_EC<16>

EC_LID_OUT#<19>

R1539
0_0402_5%

R1540
0_0402_5%

R1542
0_0402_5%

12

1 2

1 2

1 2

@

GC6@

R1435 43_0402_1%

+RTCBATT

KBRST#

SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
CLK_PCI_EC

WRST#

EC_SMI#_R

BATT_LEN#

PLT_RST#

EC_SCI#_R

GATEA20

KSI0

KSI1

KSI2

KSI3

KSI4

KSI5

KSI6

KSI7

KSO0

KSO1

KSO2

KSO3

KSO4

KSO5

KSO6

KSO7

KSO8

KSO9

KSO10

KSO11

KSO12

KSO13

KSO14

KSO15

EC_SMB_CK2

EC_SMB_DA2

EC_SMB_CK1

EC_SMB_DA1

LAN_PWR_ON#
PM_SLP_S3#
PM_SLP_S4#

EC_RSMRST#
ON/OFF

NOVO#

USB_ON#

NUM_LED# only for Y500

DPWROK_EC

EC_LID_OUT#

ECR_EN_R

100K_0402_5%

close EC

C1082

1 2

.1U_0402_16V7K

@

R1519

0_0402_5%

R1520

R_short 0_0402_5%

U70

4

KBRST#/GPB6

5

SERIRQ/GPM6

6

LFRAME#/GPM5

7

LAD3/GPM3

8

LAD2/GPM2

9

LAD1/GPM1

10

LAD0/GPM0

13

LPCCLK/GPM4

14

WRST#

15

ECSMI#/GPD4

16

PWUREQ#/BBO/SMCLK2ALT/GPC7

17

NC

22

LPCRST#/WUI4/GPD2

23

ECSCI#/GPD3

126

GA20/GPB5

58

KSI0/STB#

59

KSI1/AFD#

60

KSI2/INIT#

61

KSI3/SLIN#

62

KSI4

63

KSI5

64

KSI6

65

KSI7

36

KSO0/PD0

37

KSO1/PD1

38

KSO2/PD2

39

KSO3/PD3

40

KSO4/PD4

41

KSO5/PD5

42

KSO6/PD6

43

KSO7/PD7

44

KSO8/ACK#

45

KSO9/BUSY

46

KSO10/PE

51

KSO11/ERR#

52

KSO12/SLCT

53

KSO13

54

KSO14

55

KSO15

56

KSO16/SMOSI/GPC3

57

KSO17/SMISO/GPC5

110

SMCLK0/GPB3

111

SMDAT0/GPB4

115

SMCLK1/GPC1

116

SMDAT1/GPC2

117

SMCLK2/PECI/WUI22/GPF6

118

SMDAT2/PECIRQT#/WUI23/GPF7

94

WUI17/CRX1/SIN1/SMCLK3/GPH1/ID1

95

WUI18/CTX1/SOUT1/GPH2/SMDAT3/ID2

112

RING#/PWRFAIL#/CK32KOUT/LPCRST#/GPB7

125

PWRSW/GPE4

19

BAO/WUI24/GPE0

33

GINT/CTS0#/GPD5

35

RTS1#/WUI5/GPE5

93

CLKRUN#/WUI16/GPH0/ID0

2

CK32KE/GPJ7

128

CK32K/GPJ6

12

R1102

VCOREVCC

12

12

3

VBAT/VCC

Int. K/B
Matrix

12

LPC

1

+3VS

11

VCORE/VCC

SM Bus

WAKE UP

Clock

VSS/GND

VSS/GND20VSS/GND

21

Support DC S5 Charge

18

50

92

114

121

VCC/VCC

VSTBY/VCC

VSTBY/VCC

VSTBY/VCC

VSTBY/VCC

VSTBY/VCC26VSTBY/VCC

ADC

ADC5/DCD1#/WUI29/GPI5
ADC6/DSR1#/WUI30/GPI6

ADC7/CTS1#/WUI31/GPI7

DAC

PS2

SPI Flash ROM

EXTERNAL SERIAL FLASH

UART

GPIO

DTR1#/SBUSY/GPG1/ID7

GPIO

VSS/GND

VSS/GND

VSS/GND

VSS/GND49VSS/GND

27

75

91

113

122

NOS5C@

1 2

R1524 0_0603_5%

S5C@

1 2

R1525 0_0603_5%

+3VALW_R

+3VALW_EC

74

127

AVCC

VSTBY/VCC

PWM

PWM6/SSCK/GPA6

PWM7/RIG1#/GPA7

TMRI0/WUI2/GPC4
TMRI1/WUI3/GPC6

ADC4/WUI28/GPI4

DAC2/TACH0B/GPJ2
DAC3/TACH1B/GPJ3

DAC4/DCD0#/GPJ4

DAC5/RIG0#/GPJ5

PS2CLK0/TMB0/GPF0

PS2DAT0/TMB1/GPF1
PS2CLK1/DTR0#/GPF2
PS2DAT1/RTS0#/GPF3

PS2CLK2/WUI20/GPF4

PS2DAT2/WUI21/GPF5

WUI19/GPH3/ID3

RXD/SIN0/GPB0

TXD/SOUT0/GPB1

EGAD/WUI25/GPE1
EGCS#/WUI26/GPE2
EGCLK/WUI27/GPE3

SSCE0#/GPG2
SSCE1#/GPG0

CTX0/TMA0/GPB2

TACH1A/TMA1/GPD7

TACH0A/GPD6

AVSS/AGND

IT8580E-HX_LQFP128

All capacitors close to EC

minimum trace width 12 mil

24

PWM0/GPA0

25

PWM1/GPA1

28

PWM2/GPA2

29

PWM3/GPA3

30

PWM4/GPA4

31

PWM5/GPA5

32
34
120
124

66

ADC0/GPI0

67

ADC1/GPI1

68

ADC2/GPI2

69

ADC3/GPI3

70
71
72
73

78
79
80
81

85
86
87
88
89
90

96
97

GPH4/ID4

98

GPH5/ID5

99

GPH6/ID6

101

GPG3

102

GPG4

103

GPG5

105

GPG7

108
109

82
83
84

77

GPJ1

100
106
104

DSR0#/GPG6

107
119

CRX0/GPC0

123

76

TACH2/GPJ0

48
47

+3VALW

+3VL

+3VALW_R

C1081

C1077

0.1U_0402_16V4Z

C1078

0.1U_0402_16V4Z

C1079

C1076

0.1U_0402_16V4Z

1

1

2

2

PWR_LED#
BATT_CHG_LED#
BATT_LOW_LED#

LED_KB_PWM

SLI_FAN_PWM
EC_FAN_PWM
BEEP#

ACIN
VGA_AC_DET

VGA_IMON Cancel

SA_PGOOD
BATT_TEMP
IMVP_IMON
LAN_WAKE#
ADP_I

AD_ID
LID_SW#

SUSWARN#
AC_PRESENT
DRAMRST_CNTRL_EC

EC_WL_OFF#

USB_CH#

PBTN_OUT#
PM_SLP_SUS#
SUSACK#
TP_CLK
TP_DATA

CAPS_LED#

PCH_PWR_EN
ACOFF

PCH_PWROK PCH_PWROK

GPG3
GPG4
GPG5

CMOS_ON#

EC_RX
EC_TX

SYSON
SUSP#
VR_ON

EC_MUTE#
ENBKL

H_PROCHOT#_EC

ME_FLASH

EC_ON

BKOFF#

AOAC_ON

TP_LED#

SLI_FAN_SPEED

EC_FAN_SPEED

0.1U_0402_16V4Z

1

1

2

2

0.1U_0402_16V4Z

C1080

0.1U_0402_16V4Z

1

1

2

2

PWR_LED# <47>
BATT_CHG_LED# <47>

BATT_LOW_LED# <47>

LED_KB_PWM <46>

SLI_FAN_PWM <32,41>

EC_FAN_PWM <40>
BEEP# <42>

EC_INVT_PWM

ACIN < 62>
VGA_AC_DET <23>

SA_PGOOD <56>

BATT_TEMP <53>
IMVP_IMON <59>

ADP_I <53,62>

AD_ID <53>

LID_SW# <46>

SUSWARN# <16>

AC_PRESENT <16>

DRAMRST_CNTRL_EC <7>

EC_WL_OFF# <37>

USB_CH# <49>

PBTN_OUT# <16>

PM_SLP_SUS# <16,51>

SUSACK# <16>

TP_CLK <46>

TP_DATA <46>

CAPS_LED# <47>

PCH_PWR_EN <51>

ACOFF <62>

PCH_PWROK <16>

CMOS_ON# <34>

EC_RX <37>

EC_TX <37>

SYSON <55>

SUSP# <32,51,55,57>

VR_ON <59>

EC_MUTE# <43>

ENBKL <34>

ME_FLASH <14>

EC_ON <50,54>

BKOFF# <34>

AOAC_ON <51>

SLI_FAN_SPEED <32,41>

EC_FAN_SPEED <40>

1 2

@

@

+3VALW_R +3VALW_EC

For 2nd fan
For fan
For EC beep

R1430

12

0_0402_5%

AD_ID

12

R1429
0_0402_5%

R1619
0_0402_5%

L80

1 2

BLM18PG181SN1D_0603

L81

1 2

BLM18PG181SN1D_0603

EC_INVT_PWM <34>

GC6_EVENT# <19,23,32>

1 2

R1532 100K_0402_5%@

1 2

R1533

for power adapter ID
3V--- 90W

1.5V--- 120W
0V--- 170W

1. Change BOM structure of R1532 and R1533 to "@"
For Adapter AD_ID function, Power team had

2.

reserved resistance (PR396, Pr397) at power side

R1433

1 2

@

10K_0402_5%

PROCHOT <53>

TouchPad_LED

TP_LED# <47>
A_DET#_R <49>

1

2

ECAGND

100K_0402_5%

@

OPT,35W --> R1532
OP

T,45W --> R1532, R1533

SLI --> R1533

VR_HOT#<59>

C1072

0.1U_0402_16V4Z

+3VALW

VR_HOT#

H_PROCHOT#_EC

+3VS

1

C1073
1000P_0402_50V7K

2

Support DC S5 Charge

+3VALW +3VL

12

NOS5C@

R1529

0_0603_5%

EC_SMB_CK1

R1417 2. 2K_0402_5%

EC_SMB_DA1

R1424 2. 2K_0402_5%

20120713 --> change to normal footprint

EC_FAN_SPEED

SLI_FAN_SPEED

TP_CLK

TP_DATA

EC_SMB_CK2

EC_SMB_DA2

USB_CH#

USB_ON#

EC_FAN_PWM

LPC_FRAME#

R1427

1 2

R_short 0_0402_5%

2N7002H_SOT23-3

Q141

13

D

2

G

S

12

12

12

R1431 10K_0402_5%

12

R1485 10K_0402_5%

1 2

R1410 4.7K_0402_5%

1 2

R1412 4.7K_0402_5%

R1423 2.2K_0402_5%

R1422 2.2K_0402_5%

1 2

R1482 10K_0402_5%

1 2

10K_0402_5%

R1409

@

R1402

10K_0402_5%

1 2

R1521 10K_0402_5%

1

C1004
47P_0402_50V8J

2

12

12

12

H_PROCHOT# <53,6>

1

C1075

0.1U_0402_16V4Z

2

12

S5C@

R1530
0_0603_5%

+3VS

+3VS

+3VS

+5VALW

+3VS

+3VS

For factory EC flash

GPG5
CMOS_ON#
GPG3

GPG4

H_PROCHOT#_EC

WRST#

ECAGND

IT0PAD
IT1PAD
IT2PAD
IT3PAD
IT4PAD
IT5PAD
IT6PAD
IT7PAD

IT8PAD

EMC Request

C1007

1

@

2

0.1U_0402_10V6K

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC F UTURE CENTER. AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC F UTURE CENTER. AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC F UTURE CENTER. AND CONTAINS CON FIDENTIAL
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.

BATT_TEMP

ACINSYSON

2011/11/01

2011/11/01

2011/11/01

1 2

C1000 100P_0402_50V8J

1 2

C1001 100P_0402_50V8J

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

SUSP#

12

100K_0402_5%
R1101

2012/12/31

2012/12/31

2012/12/31

SYSON

12

100K_0402_5%
R1522

Title

Title

Title

EC IT8580E

EC IT8580E

EC IT8580E

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet

Date: Sheet

Date: Sheet

+3VALW

LAN_WAKE#

Y400S-NM-A141

Y400S-NM-A141

Y400S-NM-A141

Monday, January 14, 2013

Monday, January 14, 2013

Monday, January 14, 2013

R1434
10K_0402_5%

1 2

LAN_WAKE# <37,38>

of

45 65

of

45 65

of

45 65

1.0

1.0

1.0

5

14" INT_KBD Conn.

4

3

2

1

KSI[0..7]

D D

KSO2

KSO15

KSO6

KSO8

KSO13

KSO12

KSO11

KSO10

KSO3

KSO4

KSI0

KSO0

C734 100P_0402_50V8J@

C736 100P_0402_50V8J@

C738 100P_0402_50V8J@

C740 100P_0402_50V8J@

C742 100P_0402_50V8J@

C744 100P_0402_50V8J@

C746 100P_0402_50V8J@

C748 100P_0402_50V8J@

C750 100P_0402_50V8J@

C752 100P_0402_50V8J@

C754 100P_0402_50V8J@

C756 100P_0402_50V8J@

KSO[0..15]

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

CONN PIN define need double check

C C

KSI[0..7] <45>

KSO[0..15] <45>

KSO1

KSO7

KSI2

KSO5

KSI3

KSO14

KSI7

KSI6

KSI5

KSI4

KSO9

KSI1

1 2

C735 100P_0402 _50V8J@

1 2

C737 100P_0402 _50V8J@

1 2

C739 100P_0402 _50V8J@

1 2

C741 100P_0402 _50V8J@

1 2

C743 100P_0402 _50V8J@

1 2

C745 100P_0402 _50V8J@

1 2

C747 100P_0402 _50V8J@

1 2

C749 100P_0402 _50V8J@

1 2

C751 100P_0402 _50V8J@

1 2

C753 100P_0402 _50V8J@

1 2

C755 100P_0402 _50V8J@

1 2

C757 100P_0402 _50V8J@

KSI1
KSI7
KSI6
KSO9
KSI4
KSI5
KSO0
KSI2
KSI3
KSO5
KSO1
KSI0
KSO2
KSO4
KSO7
KSO8
KSO6
KSO3
KSO12
KSO13
KSO14
KSO11
KSO10
KSO15

JKB1

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25

G1

26

G2

ACES_85202-24051

ME@

KB Lighting CONN.4pin

+VCC_KB_LED

R1229

10K_0402_5%

KBL@

R1480

2

G

12

LED_KB_PWM<45>

100K_0402_5%

KBL@

2

C905

@

1

0.1U_0402_10V6K

12

C1053

0.1U_0402_16V4Z

1 2

R1232 0_0402_5%

KBL@

13

D

Q122
2N7002_SOT23

S

KBL@

JKBL1

1

1

2

2

3

3

4

4

5

G1

6

G2

E&T_6906-Q04N-00R

ME@

+5VS

AO3413
VGS= -4.5V, Id=-3A, Rds<97m ohm

AO3413_SOT23-3

Q121

D

S

KBL@

13

G

1

2

1

C907

0.01U_0402_16V7K

2

@

@

2

@

+VCC_KB_LED

1

2

C1054

C908

@

0.01U_0402_25V7K

0.1U_0402_16V4Z

1

2

To TP/B Conn.

JTP1

ME@

SMB_DATA_S3<12,13,15,37>
SMB_CLK_S3<12,13,15,37>

TP_DATA<45>

B B

TP_CLK<45>

SMB_DATA_S3
SMB_CLK_S3

TP_DATA
TP_CLK

1

@

C761
100P_0402_50V8J

2

1

@

C762
100P_0402_50V8J

2

+3VALW

+3VS

C760

0.1U_0402_16V4Z

D58

4

I/O3

5

VDD

6

I/O4

AZC099-04S.R7G_SOT23-6

@

For ESD request

GND

1

I/O1

2

3

I/O2

1

1

2

2

3

3

4

4

5

5

6

6

7

GND

8

GND

ACES_88514-00601-071

+3VALW

R1002

1 2

R_short 0_0402_5%

0.1U_0402_16V4Z

L

id Switch

+VCC_LID

1

C758

2

1 2

R1003 100K_0402_5%

2

5711ACDL-M3T1S SOT-23

VDD

3

OUTPUT

GND

U37

1

2

C759

10P_0402_50V8J

1

LID_SW# <45>

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

3

2011/11/01

2011/11/01

2011/11/01

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2012/12/31

2012/12/31

2012/12/31

Title

KB /SW /LPC DEBUG CONN.

KB /SW /LPC DEBUG CONN.

KB /SW /LPC DEBUG CONN.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Monday, January 14, 2013

Monday, January 14, 2013

Monday, January 14, 2013

Y400S-NM-A141

Y400S-NM-A141

Y400S-NM-A141

1

of

of

of

46 65

46 65

46 65

1.0

1.0

1.0

+3VALW

12

R1562

100K_0402_5%

1

C1100

0.1U_0402_16V4Z

34

D

BATT_LOW_LED#<45>

5

G

2

Q160B
2N7002KDWH_SOT363-6

S

1 2

R1564
0_0402_5%

@

2

G

BATT_LOW_LED#_R

61

D

Q160A

S

2N7002KDWH_SOT363-6

BATT_CHG_LED#<45>

R1558

100K_0402_5%

5

G

+3VALW

12

34

D

Q158B
2N7002KDWH_SOT363-6

S

R1561
0_0402_5%

1

C1098

0.1U_0402_16V4Z

2

1 2

@

2

G

BATT_CHG_LED#_R

61

D

Q158A

2N7002KDWH_SOT363-6

S

BA

TT CHARGE/LOW LED

Amber

BATT_LOW_LED#_R

hite

W

BATT_CHG_LED#_R

2

012-0507 --> Add MOS solution onLED3, 2 to avoid the

R1012

470_0402_5%

R1014

470_0402_5%

12

3

12

2

light blinked.

White

LED2

1

12-22-S2ST3D-C30-2C_WHI-ORG

+5VALW

100K_0402_5%

PWR_LED#<45>

BlueTooth DC

PCH_BT_ON#<19,37>

5

R1559

G

+3VALW

12

34

D

Q159B
2N7002KDWH_SOT363-6

S

R1560
0_0402_5%

1

C1099

0.1U_0402_16V4Z

2

1 2

@

R1526

1 2

100K_0402_5%

BT@

PWR_LED#_R

61

D

Q159A

2

G

S

2N7002KDWH_SOT363-6

+3VS +3VS_BT

1

C1070

0.1U_0402_16V4ZB T@

2

1

C1084

0.1U_0402_16V4Z@

2

BT@

S

G

2

TouchPad_LED

TP_LED#<45>

HDD_LED#<14>

Q154
AO3413_SOT23-3

D

13

1

2

C1069

0.01U_0402_25V7KBT@

R1621
0_0402_5%

R1622
0_0402_5%

USB20_P13<18>
USB20_N13<18>

1 2

1 2

@

30mils

1

C1083

0.1U_0402_16V4ZB T@

2

+3VS_BT

10K_0402_1%

5

G

USB20_P13
USB20_N13

R1490

+5VS

12

34

@

+5VS

@

D

Q151B
2N7002KDWH_SOT363-6

S

1 2

R1492
0_0402_5%

BT Conn.

JBT1

1

1

2

2

3

3

4

4

5

GND

6

GND

ACES_50209-0040N-001

R1491

1 2

10K_0402_1%

ME@

@

TP_LED#_R

61

D

Q151A

@

2

G

S

2N7002KDWH_SOT363-6

2012-0507 --> Change LED1 to T/P LED

PWR LED HDD LED

PWR_LED#_R<50>

TP_LED#_R

CAPS_LED#< 45>

CapsLK LED

White

LED3

LED1

LED4

21

21

21

12-21SYGCS530-E1S155TR8_W

12-21SYGCS530-E1S155TR8_W

12-21SYGCS530-E1S155TR8_W

R1013

300_0402_5%

R1322

300_0402_5%

R1323

300_0402_5%

12

+5VALW

12

+5VS

12

+5VS

LED3 LED2 LED1 LED4

POWER BATTERY T/P CapsLK

Screw Hole

MIN PCIE: H_3P3 X 1CPU and GPU: H_3P8X 6

C: H_3P8X 3

H13

H10
HOLEA

1

H12
HOLEA

1

HOLEA

1

ME: H_8P0 X 8; H_3P3X 1; H_4P0X3P0N X 2; H_2P0X 1

A: H_2P8X 8

H22

H16

HOLEA

HOLEA

1

1

H24
HOLEA

1

B: H_3P8X 3

H14

H11

HOLEA

HOLEA

1

1

GPUCPU

H25

H30

HOLEA

HOLEA

1

1

H15
HOLEA

1

H31
HOLEA

1

H32
HOLEA

1

H33
HOLEA

1

E: H_3P3X 1

H28
HOLEA

1

PCB Fedical Mark PAD

FD3

FD1

FD2

1

1

FD4

1

1

E: H_3P3X 1 H_4P0X3P0NX 3 H_2P0X 2

H20

H29
HOLEA

1

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

2011/11/01

2011/11/01

2011/11/01

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

HOLEA

1

2012/12/31

2012/12/31

2012/12/31

H21
HOLEA

1

H23
HOLEA

1

Title

Title

Title

LED/EC SPI ROM/BT

LED/EC SPI ROM/BT

LED/EC SPI ROM/BT

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Monday, January 14, 2013

Monday, January 14, 2013

Monday, January 14, 2013

Y400S-NM-A141

Y400S-NM-A141

Y400S-NM-A141

47 65

47 65

47 65

of

of

of

1.0

1.0

1.0

A

B

C

D

E

LEFT SIDE USB3.0 PORT X1

VOUT
VOUT

FLG

+USB_VCCA+5VALW

8
7
6
5

1

C904

1000P_0402_50V7K@

2

USB_OC1# <18>

+USB_VCCA

C814 220U_6.3V_M

1 2

+

1 2

C816 470P_0402_50V7K

U39

1

GND

1 1

C767 0.1U_0402_16V4Z

12

USB_ON#<45,49>

USB_ON# USB_OC1#

2

VIN
VIN3VOUT

4

EN

G547I2P81U_MSOP8

Low Active 2A

r EMI request

Fo

USB2.0 choke --> SM070000I00

USB3.0 Choke --> SM070001U00

L68

USB30_RX_N3

2 2

3 3

USB30_RX_P3

USB30_TX_C_N3

USB30_TX_C_P3

USB20_N2

USB20_P2 USB30_TX_R_P3

2

2

3

3

WCM-2012-900T_4P

L70

2

2

3

3

WCM-2012-900T_4P

L72

2

2

3

3

WCM-2012-900T_4P

1

USB30_RX_R_N3

1

4

USB30_RX_R_P3

4

1

USB30_TX_R_N3

1

4

USB30_TX_R_P3

4

1

1

4

4

USB20_N2_R

USB20_P2_R

USB20_N2<18>
USB20_P2<18>

USB30_RX_N3<18>
USB30_RX_P3<18>

USB30_TX_N3<18>
USB30_TX_P3<18>

For ESD request

USB30_RX_R_N3

USB30_RX_R_P3

USB30_TX_R_N3

YSCLAMP0524P_SLP2510P8-10-9

USB30_RX_P3 USB30_RX_R_P3

USB30_TX_N3 USB30_TX_C_N3 US B30_TX_R_N3

D27

@

9

10

8

9

7

7

6

6 5

1

2

4

3

8

1 2

C300 0.1U_0402_10V6K

1 2

C299 0.1U_0402_10V6K

1

USB30_RX_R_N3

2

USB30_RX_R_P3

4

USB30_TX_R_N3

5

USB30_TX_R_P3

3

USB20_N2_R

USB30_TX_C_P3 USB 30_TX_R_P3USB30_TX_P3

D24

@

3

I/O2

2

GND

1

I/O1

AZC099-04S.R7G_SOT23-6

1 2

R1162 0_0402_5%

@

1 2

R1163 0_0402_5%

@

1 2

R1154 0_0402_5%

@

1 2

R1155 0_0402_5%

@

1 2

R1156 0_0402_5%

@

1 2

R1157 0_0402_5%

@

6

I/O4

5

4

+5VALW

USB20_P2_R

VDD

I/O3

USB20_N2_RUSB20_N2
USB20_P2_RUSB20_P2

USB30_RX_R_N3USB30_RX_N3

JUSB1

1

VBUS

2

D-

3

D+

4

GND_1

5

SSRX-

6

SSRX+

7

GND_2

8

SSTX-

9

SSTX+

SANTA_370300-1

ME@

GND_6
GND_5
GND_4
GND_3

13
12
11
10

4 4

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

A

B

2011/11/01

2011/11/01

2011/11/01

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

C

2012/12/31

2012/12/31

2012/12/31

D

Title

USB3.0 PORT

USB3.0 PORT

USB3.0 PORT

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Monday, January 14, 2013

Monday, January 14, 2013

Date: Sheet

Date: Sheet

Date: Sheet

Monday, January 14, 2013

Y400S-NM-A141

Y400S-NM-A141

Y400S-NM-A141

E

48 65

48 65

48 65

of

of

of

1.0

1.0

1.0

5

4

3

2

1

Sleep & Charge

ight side USB Charger Port (USB_Port5, near JMIC1)

R

D D

VBUS1
VBUS2

DPOUT

DMOUT

A_DET#
ALERT#

+5V_CHGUSB

tive Mode Selection:

Ac

M1 M2 EM_EN ACTIVE MODE

0 0 1 Dedicated Charger Emulation Cycle
0 1 0 Date Pass-through

Del C1095

3
4

17

USB20_P5_C

16

USB20_N5_C

18

A_DET#_R

13

USB_OC2#

11

EC_SMB_DA1

12

EC_SMB_CK1

6

SEL

CH_SEL
CH_ILIM

1 2

R1555

33K_0402_5%

5

R1587

10K_0402_5%

1 2

@

R1583

10K_0402_5%

1 2

1 2

R1553

10K_0402_5%

+3VALW

A_DET#_R <45>
USB_OC2# <18>
EC_SMB_DA1 <45,53,62>
EC_SMB_CK1 <45,53,62>

0 1 1 BC1.2 DCP
1 0 0 BC1.2 SDP
1 0 1 Dedicated Charger Emulation Cycle
1 1 0 Date Pass-through
1 1 1 BC1.2 CDP

*

ILIM SETTING

Pull Low
OR-500mA
10K-900mA
12K-1000mA
15K-1200mA
18K-1500mA
22K-1800mA
27K-2000mA
33K-2500mA

*

SEL Pin Decode

Pull Low
0R -1010_000
10K-1010_000

*

12K-1010_000
15K-1010_000
18K-0110_000
22K-0110_000
27K-0110_000
33K-0110_000

+5VALW

0.1U_0402_16V4Z

1U_0402_6.3V6K

C1093

+5VALW

C C

+5VALW

10U_0603_6.3V6M

C1096

0.01U_0402_16V7K

1

2

R1551
10K_0402_5%

R1585
10K_0402_5%

R1586
10K_0402_5%

1

C1097

2

1 2

1 2

1 2

USB20_P5<18>
USB20_N5<18>

EM_EN

CH_M1

CH_M2

USB_CH#<45>

R1584
10K_0402_5%

R1552
10K_0402_5%

R1554
10K_0402_5%

USB20_P5
USB20_N5

USB_CH#

EM_EN

CH_M1
CH_M2

@

@

@

2

1

C1094

1

2

9

U8

7

VS1

VS2

DPIN
DMIN

PWR_EN

EM_EN

M1
M2

GND FLAG21GND

VDD

SMDATA/LATCH

SMCLK/S0

COMM_SEL/ILIM

20

UCS1002-1-BP-TR_QFN20_4X4

8

14
15

10

19

1
2

12

12

12

2012-0429 --> Set default mode is "BC1.2 CDP" Mode (2.5A on S0)for USB Port5

USB Power (USB20_P9)

+5VS

2

+USB_VCCB

+5V_CHGUSB

USB20_P9
USB20_N9

USB20_P5_C
USB20_N5_C

EXT_MIC_L
EXT_MIC_R
MIC_JD
HP_OUTR
HP_OUTL
SPDIF_OUT
PLUG_IN

2012/12/31

2012/12/31

2012/12/31

B B

USB_ON#<45,48>

USB_ON# USB_OC4#

1

C988

0.1U_0402_16V4Z

2

Ext. MIC

A A

MIC2_R<42>

MIC1_R<42>

5

RA1634 1K_0402_5%

RA1633 1K_0402_5%

12

12

U69

1

GND

2

VIN
VIN3VOUT

4

EN

G547I2P81U_MSOP8

Low Active 2A

+MIC1_VREFO_R

Realtek Review 10.24

RA1622

2.2K_0402_5%

VOUT
VOUT

FLG

+MIC1_VREFO_L

1 2

+USB_VCCB+5VALW

8
7
6
5

1

C989

@

1000P_0402_50V7K

2

Remove Diode (DA1, DA2)

RA1623

2.2K_0402_5%

1 2

4

EXT_MIC_R

EXT_MIC_L

USB_OC4# <18>

USB20_P9<18>
USB20_N9<18>

MIC_JD<42>

HP_OUTR<42>
HP_OUTL<42>
SPDIF_OUT<42>

PLUG_IN<42>

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

3

2011/11/01

2011/11/01

2011/11/01

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

AUDIO/B Conn.

JSB1

ME@

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25

GND1

26

GND2

ACES_88514-02401-071

Title

Title

Title

AUDIO/B, USB CHARGER

AUDIO/B, USB CHARGER

AUDIO/B, USB CHARGER

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Monday, January 14, 2013

Monday, January 14, 2013

Monday, January 14, 2013

Y400S-NM-A141

Y400S-NM-A141

Y400S-NM-A141

1

of

of

of

49 65

49 65

49 65

1.0

1.0

1.0

ON/OFF switch

Power Button

OP Side

T

Bottom Side

ON/OFFBT N#

1

2

SHORT PA DS

Support DC S5 C harge

SW2

J7

1 2

@

SMT1-05_ 4P

5

6

@

Support DC S5 C harge

NOS5C@

R1116

100K_04 02_5%

2

G

1 2

+3VALW

3

4

S5C@

1 2

R1531 0 _0603_5%

D72

NOS5C@

3

1

2

DAN202U T106_SC70-3

EC_ON<45,5 4>

EC_ON

R1523

10K_040 2_5%

1 2

ON/OFF

51_ON#

13

D

Q153

S

2N7002_ SOT23-3

+3VL

S5C@

R1117
100K_04 02_5%

1 2

ON/OFF <45>

51_ON# <5 2>

Power Button/B link
to Function/B Conn. 10pin

PWR_ LED#_R<47>

NOVO_BT N#

ON/OFFBT N#

C551

100P_04 02_50V8J

9/23 ESD Reques t

+5VALW

JPW R1

ME@

1

1

2

2

3

3

4

4

5

5

6

@

1

2

6

7

GND

8

GND

ACES_88 514-00601-071

51_ON#

ON/OFF

NOVO#< 45>

NOVO#

1 2

R19 0_040 2_5%NOS5C@

1 2

R28 0_040 2_5%@

NOS5C@

+3VALW

1 2

R1118
100K_04 02_5%

+3VL

R1119
100K_04 02_5%S5C@

1 2

D56

2

1

3

DAN202U T106_SC70-3

NOVO_BT N#

EMI REQUEST 1ST = SCA00000E00

2ST = SCA00000R00

Security Class ification

Security Class ification

Security Class ification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2011/11/ 01

2011/11/ 01

2011/11/ 01

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2012/12/ 31

2012/12/ 31

2012/12/ 31

Title

Title

Title

OTHER I/O CONN.

OTHER I/O CONN.

OTHER I/O CONN.

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Monday, January 14, 2013

Monday, January 14, 2013

Monday, January 14, 2013

Y400S-NM-A141

Y400S-NM-A141

Y400S-NM-A141

of

of

of

50 65

50 65

50 65

1.0

1.0

1.0

A

B

C

D

E

+5VALW to +5VS +1.5V to +1.5VS

AP4800BGM
VGS=10V, ID=9A, Rds=18m ohm
VGS=+-25V

+5VALW

U46

8
7

1

1 1

2 2

3 3

C836

2

10U_0805_10V6K

PCH_PWR_EN<45>

PM_SLP_SUS#<16,45>

AOAC_ON<45>

6
5

PCH_PWR_EN#_R

1
2
3

AP4800BGM-HF

4

1

C842

0.01U_0402_25V7K

2

PCH_PWR_EN

PM_SLP_SUS#

AOAC_ON

+5VS

1 2

82K_0402_5%

R60
100K_0402_5%

R1448
0_0402_5%

AOAC_ON#<37>

R1453
0_0402_5%

1

C837
10U_0603_6.3V6M

2

R1088

R1484

820K_0402_5%

1 2

DS3@

1 2

R117

R_short 0_0402_5%

12

@

100K_0402_5%

AOAC@

1 2

100K_0402_5%

1

C838
1U_0603_10V4Z

2

5VS_GATE5V S_GATE_R

12

D

@

S

100K_0402_5%

PCH_PWR_EN#

12

R1121

100K_0402_5%

AOAC_ON#

12

R1123

R1085

150K_0402_5%

61

2

G

Q99A
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6

+5VALW

12

R1120

DS3@

13

DS3@

D

2

G

S

DS3@

+5VALW

12

R1122

AOAC@

13

AOAC@

D

2

G

S

AOAC@

12

R1475

@

470_0603_5%

+VSB +VSB

34

D

5

SUSP

G

Q99B

Q118
2N7002_SOT23

Q119
2N7002_SOT23

S

0.1U_0402_16V4Z

PCH_PWR_EN#_R PCH_PWR_EN#_R

+V1.05S_VCCP_PWRGOOD<56,57>

+3VALW to +3VS

AP4800BGM
VGS=10V, ID=9A, Rds=18m ohm
VGS=+-25V

+3VALW

1

C839

2

10U_0805_10V6K

U47

8
7
6
5

+3VS

1
2
3

AP4800BGM-HF

4

1

C843

0.01U_0402_25V7K

2

1

C840
10U_0603_6.3V6M

2

R1089

1 2

R_short 0_0402_5%

R1483

820K_0402_5%

3VS_GATE3VS_GATE_R

12

@

1

C841
1U_0603_10V4Z

2

470K_0402_5%

61

D

S

470_0603_5%

R1086

12

2

SUSP

G

Q100A
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6

Q100B

12

R1474

@

34

D

5

G

S

+3VALW to +3V_PCH +5VALW to +5V_PCH

+3VALW +3 V_PCH +5VALW +5V_PCH

C1065

1

2

DS3@

J11

@

2

112

JUMP_43X79

Q148
AO3413_SOT23

D

S

13

DS3@

G

2

DS3@

100K_0402_5%

SUSP

2N7002KDWH_SOT363-6

1

C38

@

0.1U_0402_16V4Z

2

1. C38, C39 resistance change to 0.1u_0402

2.

and the BOM structure as "@" for discharge

1

C1066

0.01U_0402_25V7K

2

100K_0402_5%

0.75VR_EN#<57>

R8

@

Q144A

12

0.75VR_EN

2

G

5

G

61

D

@

2N7002KDWH_SOT363-6

S

+3VALW

R6

12

@

34

D

@

Q144B

S

C1067

0.1U_0402_16V4Z

+3VS to +3VS_VGA

For S3 CPU Power Saving

1

2

DS3@

DGPU_PWR_EN<18,23>

J14

@

112

JUMP_43X79

Q149
AO3413_SOT23

D

S

DS3@

G

2

2

13

DS3@

DGPU_PWR_EN#

1

C39

0.1U_0402_16V4Z

2

1

C1068

0.01U_0402_25V7K

2

R1452

12

R_short 0_0402_5%

R1454

100K_0402_5%

SUSP#

@

2

G

R1449

47K_0402_5%

2

G

12

10U_0805_10V6K

+3VALW

12

R1087
100K_0402_5%

61

D

S

+5VALW

12

61

D

Q146A
2N7002KDWH_SOT363-6

S

+1.5V +1.5VS

1

C856

2

SI2301BDS-T1-E3_SOT23-3

R1090

1 2

R_short 0_0402_5%

Q101A
2N7002KDWH_SOT363-6

1 2

10K_0402_5%

1.5VS_GATE

100K_0402_5%

SUSP<10,37,55,57>

SUSP#<32,45,55,57>

2N7002KDWH_SOT363-6

0.1U_0402_16V4Z

R1451

0.1U_0402_10V7K @

Q107A

+3VS

C1058

C1011

1

2

1

2

J15

@

+1.5V_CPU_VDDQ +1.5VS

S

D

13

C845
.1U_0402_16V7K

12

61

D

S

1

C857
10U_0603_6.3V6M

2

Q120

G

2

1

2

+5VALW +0.75VS

R1097

SUSP

2

G

2

112

JUMP_43X79

1.5VS_GATE

2N7002KDWH_SOT363-6

12

R1094
22_0603_5%

34

D

G

S

1

C835
1U_0603_10V4Z

2

R1481

470_0603_5%

5

G

Q101B

5

SUSP

Q107B
2N7002KDWH_SOT363-6

For Intel S3 Po wer Reduction.

+3VS_VGA

Q145

AO3413_SOT23

D

S

13

1

G

2

DGPU_PWR_EN#

2N7002KDWH_SOT363-6

C1059

0.01U_0402_25V7K

2

Q146B

R1450

470_0603_5%

5

G

12

@

C37

10U_0603_6.3V6M

34

D

S

2

1

12

@

34

D

S

SLI@

SLI@

C1062

C1012

+3VS

1

2

1

2

+3VS to +3VS_SLI

2012-0419 --> m odify +3VS_SLI BOM structure to "SLI@"

4 4

S_DGPU_PWR_EN<19,32>

S_DGPU_PWR_EN#<32>

SLI@

R1503

12

0_0402_5%

R1501

SLI@

100K_0402_5%

A

SLI@

R1502

47K_0402_5%

2

G

12

+5VALW

12

61

D

Q150A

S

2N7002KDWH_SOT363-6

0.1U_0402_16V4Z

R1513

1 2

10K_0402_5%

0.1U_0402_10V7K @

SLI@

Q147

SLI@

AO3413_SOT23

D

S

13

G

2

S_DGPU_PWR_EN#

B

+3VS_SLI

1

SLI@

C1063

0.01U_0402_25V7K

2

470_0603_5%

5

Q150B

SLI@

2N7002KDWH_SOT363-6

G

R1500

12

2

@

C48

SLI@

10U_0603_6.3V6M

1

34

D

Title

Title

Security Classification

Security Classification

S

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

C

2011/11/01

2011/11/01

2011/11/01

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

2012/12/31

2012/12/31

2012/12/31

Title

DC INTERFACE

DC INTERFACE

DC INTERFACE

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Monday, March 11, 2013

Monday, March 11, 2013

Monday, March 11, 2013

Y400S-NM-A141

Y400S-NM-A141

Y400S-NM-A141

E

of

of

of

51 65

51 65

51 65

1.0

1.0

1.0

5

4

3

2

1

DC030006J00

PF1
12A_65V_451012MRL

4

4

3

3

2

4602-Q04C-09R 4P P2.5@
JDCIN1

2

1

1

D D

21

APDIN1APDIN

12

PC1

SMB3025500YA_2P

12

1000P_0402_50V7K

PL1

1 2

PC2

100P_0402_50V8J

VIN

12

12

PC4

PC3

100P_0402_50V8J

1000P_0402_50V7K

200K_0402_1%

SLI_B+_ON#< 32>

PR303

SLI@

B+ to SLI_B+

1

3

SLI@

PC347

1 2

1 2

0.22U_0603_25V7K

SLI@

PR304

47K_0402_1%

1 2

SLI@

PQ49
AON7403L_DFN8-5

4

B+_SLIB+

+5VS to +5VS_SLI

PQ50

1

2

PR308

47K_0402_1%

1 2

JUMP_43X79

PJ19

112

AO6409L_TSOP6

4

SLI@

PC349

0.1U_0402_16V4Z

SLI@

@

2

D

S

6
5
2
1

G

3

PC350

1

1

PC351
10U_0603_6.3V6M

2

2

SLI@

0.01U_0402_16V7K

SLI@

52

12

PC348

SLI@

0.1U_0603_25V7K

SLI_5V_ON#<32>

+5VS +5VS_SLI

PR305

200K_0402_1%

SLI@

1 2

VIN

PD1

LL4148_LL34-2

1 2

51ON-1

12

12

PR2

PR1

68_1206_5%

68_1206_5%

13

12

PC6

0.1U_0603_25V7K

VS

JRTC1

- +

MAXEL_ML1220T10@

RTC Battery

PR3

@

200_0402_1%

1 2

PD2

LL4148_LL34-2

PR5

22K_0402_1%

1 2

+CHGRTC

12

12

PR4

3.3V

12

PC7
10U_0603_6.3V6M

@

51ON-2

PC5

1 2

0.22U_0603_25V7K

100K_0402_1%

51ON-3

PU1

@

APL5156-33DI-TRL_SOT89-3

3

VOUT

GND

1

PJ1
JUMP_43X39@

2

112

PQ1

TP0610K-T1-E3_SOT23-3

2

12

PR9
200_0603_5%@

2

CHGRTCIN

VIN

12

PC8
1U_0805_25V6K

@

C C

+3VLP

PR8

B B

BATT+

51_ON#<50>

0_0402_5%

1 2

2012/04/13
add SLI Hot-plug Load-SW solution

PR6

560_0603_5%

1 2

12

PR7

560_0603_5%

1 2

PD3

12

+RTCBATT

RB751V-40_SOD323-2

1 2

RB751V-40_SOD323-2

+CHGRTC

PD4

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

3

2011/11/01

2011/11/01

2011/11/01

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2012/12/31

2012/12/31

2012/12/31

Title

VIN DETECTOR

VIN DETECTOR

VIN DETECTOR

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Monday, January 14, 2013

Monday, January 14, 2013

Monday, January 14, 2013

Y400S-NM-A141

Y400S-NM-A141

Y400S-NM-A141

1

of

of

of

52 65

52 65

52 65

1.0

1.0

1.0

5

4

3

2

1

JBATT1

VMB2

1

1

2

2

3

EC_SMCA

3

4

EC_SMDA

4

5

D D

C C

5

6

6

7

7

8

GND

9

GND

TYCO_1775789-1

@

12

PR10

+3VALW

12

PR11

100_0402_1%

100_0402_1%

OPT,35W --> PR396
OPT,45W --> PR396, PR397
SLI --> PR397

PR396

100K_0402_5%

PR397 100K_0402_5%

CPU3@

PF2
12A_65V_451012MRL

21

12

PC92
33P_0201_50V8J

2012/0705
add to PC92 for EMI

1 2

PR12

6.49K_0402_1%

1 2

PR14
10K_0402_5%

12

12

2012/04/13
add power adapter ID
3V--- 90W

1.5V--- 120W
0V--- 170W

AD_ID <45>

VMB

SMB3025500YA_2P

1 2

12

PC9
1000P_0402_50V7K

EC_SMB_CK1 <45,49,62>

EC_SMB_DA1 <45,49,62>

+3VALW

BATT_TEMP <45>

PL2

BATT+

12

PC10

0.01U_0402_25V7K

For KB930 --> Keep PU1 circuit
(Vth = 0.825V)

For KB9012 (Red square) --> Remove PU1 circuit, but keep PR206
PH201, PR205,PR211,PQ201,PR208,PR212

ADP_I<45,62>

OTP_N_002

ADP_OCP_2

PR15

1 2

4.42K_0402_1%

Turbo_V

1 2

PR20

57.6K_0402_1%

PR20

57.6K:90W

82.5K:120W

76.8K:170W

PR15

4.

42K:90W

9.1K:120W

16.5K:170W

+3VLP

@

PR19

10K_0402_1%

PR21

1 2

10K_0402_1%

12

PR16

13.7K_0402_1%

12

12

PR17

21.5K_0402_1%

12

PH1

100K_0402_1% TSM0B104F4251RZ

A/D

PH1 under CPU botten side :
CPU thermal protection at 92+-3 degree C
Recovery at 56 +-3 degree C

VL

12

PC11

+3VS

H_PROCHOT#<45,6>

PQ3

2N7002KW_SOT323-3

PROCHOT<45>

D

S

0.1U_0603_25V7K

13

PR18

1 2

2

ADP_OCP_1

G

PR22
0_0402_5%

1 2

100K_0402_1%

@

PU2

1

VCC

2

GND

3

OT1

4

OT2

G718TM1U_SOT23-8

OTP_N_003

PR23
R_short 0_0402_5%

12

TMSNS1

RHYST1

TMSNS2

RHYST2

8

7

6

5

MAINPWON <54>

B B

VMB2

PR27
768K_0402_1%

PR29

10K_0402_1%

1 2

1 2

PR31
221K_0402_1%

1 2

A A

5

12

P2

PC12

0.01U_0402_25V7K

8

3

P

+

2

-

G

4

PR34

@

10K_0402_1%

PR36

10K_0402_1%

PR28

10M_0402_5%

1 2

1

O

PU3A

AS393MTR-E1 SO 8P OP

12

+CHGRTC

12

2VREF_8205

BATT_LEN#<45>

PR24

1 2

100K_0402_1%

2N7002KW_SOT323-3

PR37

10K_0402_1%

PQ5

2

G

+3VALW

PR35

12

PR25

1 2

+3VALW+3VALW

1 2

100K_0402_1%

13

D

S

100K_0402_1%

2

G

4

PQ7

13

D

2N7002KW_SOT323-3

S

BATT_OUT <62>

PQ4

TP0610K-T1-E3_SOT23-3

B+

VL

PR32

100K_0402_1%

SPOK<54>

PR33

1 2

1K_0402_1%

1 2

12

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

3

22K_0402_1%

13

D

2

G

S

PC15

1U_0402_6.3V6K

2011/11/01

2011/11/01

2011/11/01

12

PR26

PR30

1 2

PQ6

2N7002KW_SOT323-3

100K_0402_1%

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

12

PC13

0.22U_0603_25V7K

Deciphered Date

Deciphered Date

Deciphered Date

13

12

2

2012/12/31

2012/12/31

2012/12/31

2

+VSBP

PC14

0.1U_0603_25V7K

+VSBP

PJ2
JUMP_43X39@

2

112

Title

Title

Title

BATTERY CONN/OTP

BATTERY CONN/OTP

BATTERY CONN/OTP

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Monday, January 14, 2013

Monday, January 14, 2013

Monday, January 14, 2013

+VSB

Y400S-NM-A141

Y400S-NM-A141

Y400S-NM-A141

1

of

of

of

53 65

53 65

53 65

1.0

1.0

1.0

5

Note:
Use TPS51125 IC can remove RTC refernece LDO
Use TPS51427 IC must keep RTC refernece LDO

4

3

2

1

2VREF_8205

+3VALW P + 3VALW

D D

2012/07/05
change PR38 from 13K to 13.7K

PR38

13.7K_04 02_1%

1 2

154K_04 02_1%

BST_3V

UG_3V

LX_3V

LG_3V

PC35

1U_0603_10V6K

PR50

0_0402_ 5%

PR52

0_0402_ 5%

PR54

0_0402_ 5%

PR40

20K_040 2_1%

1 2

PR43

1 2

PU4

25

P PAD

7

VO2

8

VREG3

9

BOOT2

10

UGATE2

11

PHASE2

12

LGATE2

12

12

@

12

@

12

3

RT8205_B+

B+

PC22

C C

B B

ACPRN

A A

PJ5

2

112

JUMP_43 X118@

12

0.1U_0603_25V7K

2012/02/29
ch

ange PC29, PC32,
PC34 from
SGA00001E0J to
SGA00002N8J

MAINPW ON<5 3>

EC_ON

PC17

EC_ON<45,5 0>

PR56

200K_04 02_1%

2

12

0.1U_0603_25V7K

+3VALWP

PR51

0_0402_ 5%

PR185

0_0402_ 5%

@

12

5

12

PC18

4.7U_0805_25V6-K

12

12

2

13

12

PC19

PC20

4.7U_0805_25V6-K
2200P_0402_50V7K

1

+

PC29

2

150U_B2_6.3VM_R35M

2N7002K DW-2N_SOT3 63-6

PQ14

2N7002K W_SOT323 -3

13

D

G

S

PQ15

DTC115E UA_SC70-3

12

PQ8

AO4466L _SO8

3.3UH +-20 % PCMC063T-3R3M N 6A

PL3

1 2

PQ12A

12

PR46

4.7_1206_5%

12

PC30

680P_0603_50V7K

ENTRIP1 ENTRIP2

61

2

100K_04 02_1%

VL

1 2

VS

PR57

100K_04 02_1%

12

12

PR58

40.2K_0402_1%

PR53

PC38

123

12

2

2.2U_0603_10V6K

241

6

578

578

3 6

4

4

PQ10
AO4712_ SO8

13

Typ: 175mA

PR55

0_0402_ 5%

+3VL

PQ12B

34

2N7002K DW-2N_SOT3 63-6

5

PQ13
DTC115E UA_SC70-3

+3VLP

12

12

PC24

4.7U_0805_10V6K

PR44

1 2

1 2

2.2_0603 _5%

PC27

0.1U_060 3_25V7K

PR48

499K_04 02_1%

1 2

B+

12

PR49

100K_0402_1%

2VREF_8205

VL

+3.3VALWP Imax=7.5A ; Ipeak=9A
1/2 Delta I=1.113A (F=375K Hz)
Vtrip=0.169V
Rds(on)=18m ohm(max) ; Rds(on)=15m ohm(typical)
Ilimit_min=0.169/18m=9.388A
Ilimit_max=0.169/15=11.26A
Iocp=Ilimit+1/2Delta I=10.5A~12.373A

Security Class ification

Security Class ification

Security Class ification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

PC16

1U_0603_10V6K

ENTRIP2

6

ENTRIP2

VFB=2.0V

EN

13

RT8205_ B+

2011/11/ 01

2011/11/ 01

2011/11/ 01

12

30K_040 2_1%

1 2

20K_040 2_1%

1 2

1 2

ENTRIP1

1

2

5

4

3

FB1

FB2

REF

TONSEL

ENTRIP1

VO1

PGOOD

BOOT1

UGATE1

PHASE1

LGATE1

SKIPSEL

14

15

NC18VREG5

VIN16GND

17

12

PC36

4.7U_0805_10V6K

12

PC37

0.1U_0603_25V7K

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

PR39

PR41

PR42

88.7K_04 02_1%

24

23

BST_5V

UG_5V

LX_5V

LG_5V

1 2

22

21

20

19

RT8205L ZQW_W QFN24_4X4

VL

Typ: 175mA

+5VALW P + 5VALW

RT8205_ B+

12

12

12

PC23

PC21

4.7U_0805_25V6-K

4.7U_0805_25V6-K

SPOK <53>

PR45

2.2_0603 _5%

PC28

0.1U_060 3_25V7K

1 2

RT8205
TONSEL=VREF (1)SMPS1=300KHZ (+5VALWP)

TPS51125A

ONSEL=VREF (1)S MPS1=245KHZ (+ 5VALWP)

T

+5VALWP Imax=11.1A ; Ipeak=13.32A
1/

2 Delta I=1.33A (F=300K Hz)
Vtrip=0.098V
Rds(on)=7.0m ohm(max) ; Rds(on)=5.1m ohm(typical)
Ilimit_min=0.098/7m=14.03A
Ilimit_max=0.098/5.1m=19.21A
Iocp=Ilimit+1/2Delta I=15.36A ~ 20.54A

2012/12/ 31

2012/12/ 31

2012/12/ 31

2

12

PC26

PC25

0.1U_0603_25V7K

2200P_0402_50V7K

4

AO4456_ SO8

(2)SMPS2=375KHZ(+3VALWP)

(2)SMPS2=305KH Z(+3VALWP)

Title

Title

Title

3VALWP/5VALWP

3VALWP/5VALWP

3VALWP/5VALWP

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

578

3 6

5

Monday, January 14, 2013

Monday, January 14, 2013

Monday, January 14, 2013

PJ3

2

112

JUMP_43 X118@

PJ4

2

112

JUMP_43 X118

@

PQ9
AO4406A L_SO8

241

4.7UH_VM PI1004AR-4R7M-Z01 _10A_20%

786

PQ11

123

PL4

1 2

12

PR47

4.7_1206_5%

12

PC33

680P_0603_50V7K

Y400S-NM-A141

Y400S-NM-A141

Y400S-NM-A141

1

PC31

1U_0603_10V6K@

12

PC32

150U_B2_6.3VM_R35M

54 65

54 65

54 65

1

+

2

of

of

of

+5VALWP

1

+

PC34

2

150U_B2_6.3VM_R35M

1.0

1.0

1.0

A

Freq= 266~314KHz , 290KHz(typ)

Iocp=13.58A~23.10A

PR59

0_0402_5%

1 1

2 2

FBVDDQ_PWR_EN

SUSP#<32,45,51,57>

3 3

Freq= 266~314KHz , 290KHz(typ)

SYSON<45>

1 2

PR60

47K_0402_5%

PD9

RB751V-40_SOD323-2

1 2

PR67

0_0402_5%

1 2

PR68

0_0402_5%@

1 2

@

PR69

1 2

47K_0402_5%

@

12

PC44

1 2

.1U_0402_16V7K

12

PR63

PR65

1 2

12

11.5K_0402_1%

PR66
10K_0402_1%

@

12

PC54

.1U_0402_16V7K

12

PR72

75K_0402_1%

PR74

1 2

12

11.5K_0402_1%

PR76
10K_0402_1%

PR64

84.5K_0402_1%

1 2

PR73

1 2

1

2

3

4

5

470K_0402_1%

1

PGOOD

2

TRIP

3

EN

4

VFB

5

RF

TPS51212DSCR_SON10_3X 3

470K_0402_1%

Iocp=12.25A~20.77A

+5VALW

12

PR78
10K_0402_1%

PR82

0_0402_5%

DGPU_PWROK<19,27,58>

SUSP#

4 4

A

1 2

PR83
0_0402_5%@

1 2

34

PQ22B

5

12

PC64

2N7002KDW-2N_SOT363-6

1U_0603_10V6K@

B

PU5

PGOOD

TRIP

EN

VFB

RF

TPS51212DSCR_SON10_3X 3

VFB=0.7V

PU6

DRVH

VBST

DRVH

V5IN

DRVL

VBST

V5IN

DRVL

SW

TP

10

9

8

SW

7

6

11

TP

10

9

8

7

6

11

VFB=0.7V

+5VALW

PQ22A

2

B

C

578

PR61

2.2_0603_5%

1 2

BST_1.5V

DH_1.5V

LX_1.5V

DL_1.5V

BST_1.5VSP_VGA

DH_1.5VSP_VGA

LX_1.5VSP_VGA

DL_1.5VSP_VGA

12

PR79
100K_0402_1%

1 2

61

2N7002KDW-2N_SOT363-6

12

PR70

2.2_0603_5%

1 2

BST_1.5VSP_VGA-1

12

1U_0603_10V6K

12

PC60

10U_0805_25V6K

PR81

100K_0402_1%

PD10

RB751V-40_SOD323-2

1 2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.

0.22U_0603_16V7K

BST_1.5V-1

+5VALW

PC47

1U_0603_10V6K

PC55

0.22U_0603_16V7K

1 2

+5VALW

PC57

AON6504_POW ERDFN56-8-5

+1.05VS

PC45

1 2

8
7
6
5

PQ20

4

AO4456_SO8

SUSP<10,37,51,57>

12

0.01u_0603_10V6K

2011/11/01

2011/11/01

2011/11/01

5

4

5

PQ18

4

5

PQ19

4

+1.05VS_VGA

1
2

12

3

PC61

10U_0805_25V6K

PC63

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

1.5V_B+

PQ16
AO4406AL_SO8

3 6

241

786

PQ17

AO4456_SO8

123

1.5VSP_VGA_B+

MDV1525URH_PDFN33- 8-5

123

12

12

123

12

PC62

1U_0603_10V6K

PR80
0_0402_5%@

1 2

PR84
0_0402_5%@

1 2

Deciphered Date

Deciphered Date

Deciphered Date

C

2

G

12

PC39

10U_0805_25V6K

S COIL 1UH +-20% VMPI0703AR-1R0M-Z01 11A

1 2

12

@

PR62

4.7_1206_5%

@

12

PC48

1000P_0603_50V7K

12

PC49

10U_0805_25V6K

PL6

1UH_PCMC063T-1R0M N_11A_20%

1 2

@

PR71

4.7_1206_5%

@

PC59

1000P_0603_50V7K

PR77

1 2

470K_0603_5%@

13

D

2N7002KW_S OT323-3

S

12

PC40

10U_0805_25V6K

PL5

12

PC50

10U_0805_25V6K

PJ10

2

JUMP_43X118@

PQ21

@

2012/12/31

2012/12/31

2012/12/31

PJ6

2

12

12

PC42

PC41

0.1U_0402_25V6
2200P_0402_50V7K

JUMP_43X118@

12

PC43

470P_0603_50V7K

D

112

B+

+1.5VP

1

+

PC46

2

PJ7

220U_B2_6.3VM_R15M

12

12

PC51

PC52

0.1U_0402_25V6

12

<BOM Struct ure>

PC53

2200P_0402_50V7K

+1.5VP

470P_0603_50V7K

PJ8

2

JUMP_43X118@

2

112

JUMP_43X118@

112

B+

+1.5V

+1.5VSP_VGA

1

+

PC56

1 2

2

PC58

220U_B2_6.3VM_R15M

112

0.1U_0402_10V7K

+1.5VSP_VGA

PR75

0_0402_5%

+1.05VS_VGA+1.05VS

Title

Title

Title

1.5VP/1.5VSP_VGA/1.05VSP_VGA

1.5VP/1.5VSP_VGA/1.05VSP_VGA

1.5VP/1.5VSP_VGA/1.05VSP_VGA

Size D ocument Number Rev

Size D ocument Number Rev

Size D ocument Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Monday, January 14, 2013

Monday, January 14, 2013

Monday, January 14, 2013

PJ9

2

112

JUMP_43X118@

12

Y400S-NM-A141

Y400S-NM-A141

Y400S-NM-A141

D

+1.5VS_VGA

VDDQ_SENSE <25>

of

of

of

55 65

55 65

55 65

1.0

1.0

1.0

5

VID [0] VID[1] VCCSA Vout

0 0 0.9V
0 1 0.8V
1 0 0.725V
1 1 0.675V

output voltage adjustable network

D D

2

1

PC77

2

+VCCSA_PWR_SRC

2200P_0402_50V7K

PJ12

+3VALW

C C

2

112

JUMP_43X118@

2

PC78

1 2

0.1U_0603_25V7K

PC80

PC79

1

1

10U_0805_6.3V6M

10U_0805_6.3V6M

2.2U_0603_10V7K

+VCCSA_PWR_SRC

4

PC66

1 2

PC81

0.22U_0402_10V6K

SA_PGOOD<45>

+5VALW

12

3300P_0402_50V7K

10_0402_1%

19

20

21

22

23

24

PC82

PR88

PU7

PGND

PGND

PGND

VIN

VIN

VIN

12

4.99K_0402_1%

+3VS

12

PR86

100K_0402_5%

SA_PGOOD

PC65

1 2

12

1U_0603_10V6K

18

17

16

V5FILT

V5DRV

PGOOD

TPS51461RGER_QFN24_4X4

COMP

GND

VREF

3

1

2

12

PR94

PC83

3

PR85

1K_0402_1%

12

H_VCCSA_VID1 <10>

12

+VCCSA_BT

+VCCSA_PHASE

@

33K_0402_5%

H_VCCSA_VID0 <10>

0_0402_5%

1 2

PR90

2.2_0603_5%

1 2

PR92

12

PR89

+VCCSA_BT_1

12

12

0.22U_0603_16V7K

PC68

1000P_0603_50V7K

PR91

4.7_1206_5%

+V1.05S_VCCP_PWRGOOD <51,57>

PC67

1 2

PR87

1K_0402_1%

H_VCCSA_VID0

H_VCCSA_VID1

15

VID1

SLEW

4

1 2

0.01U_0402_25V7K

+VCCSA_EN

14

13

EN

VID0

12

BST

11

SW

10

SW

9

SW

8

SW

7

SW

25

TP

VOUT

MODE

5

6

+VCC_SAP
TDC 4.2A
Peak Current 6 A
OCP current 7.2 A

The 1k PD on the VCCSA VIDs are empty.
T
VCCSA VID is 00 prior to VCCIO stability.

PL7

0.47UH_FDVE0630-H-R47M=P3_17.7A_20%

1 2

2

hese should be stuffed to ensure that

@

@

PC69

1 2

22U_0805_6.3V6M

12

PC70

22U_0805_6.3V6M

1 2

PC71

0.1U_0402_10V7K

PR93

100_0402_5%

PR95

0_0402_5%

PC72

1 2

22U_0805_6.3V6M

12

12

+VCCSAP

PC73

1 2

22U_0805_6.3V6M

@

12

PC75

1 2

PC74

22U_0805_6.3V6M

2200P_0402_50V7K

+VCCSA_SENSE <10>

PJ11

1 2

PAD-OPEN 4x4m

@

PC76

1 2

22U_0805_6.3V6M

1

+VCCSA

+VCCSAP

B B

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC F UTURE CENTER. AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC F UTURE CENTER. AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC F UTURE CENTER. AND CONTAINS CON FIDENTIAL
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.

3

2011/11/01

2011/11/01

2011/11/01

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2012/12/31

2012/12/31

2012/12/31

Title

VCCSAP/1.05S_VCCPP

VCCSAP/1.05S_VCCPP

VCCSAP/1.05S_VCCPP

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet

Date: Sheet

Date: Sheet

Y400S-NM-A141

Y400S-NM-A141

Y400S-NM-A141

Monday, January 14, 2013

Monday, January 14, 2013

Monday, January 14, 2013

of

56 65

of

56 65

of

1

56 65

1.0

1.0

1.0

5

4

3

2

1

PL8

HCB1608 KF-121T30_060 3

+5VALW

D D

1 2

SUSP#<32,45,51,55>

C C

0.75VR_EN#<51>

SUSP<10,37,51,55>

2012/02/29
c

hange PR103 from 33k to 47k

PR105

0_0402_ 5%

PC100

0.1U_0402_25V6

1 2

12

PR114

1 2

10_0402 _1%

PR111

1 2

PR112

1 2

SUSP#

B B

VCCIO_SEN SE<9>

A A

+V1.05S_VCCP_PW RGOOD<51,56>

5

PR98

1 2

0_0402_ 5%

PR106

10.7K_0402_1%

1 2

12K_0402_1%

PC109

1 2

1.8VSP_V IN

12

PC84
22U_080 5_6.3VAM

EN_1.8VS P

1M_0402 _5%

0_0402_ 5%@

1 2

47K_040 2_1%

1 2

12

10K_0402_1%@

1 2

PR108
0_0402_ 5%

1 2

PC104

0.01U_04 02_25V7K

@

PR116

1 2

1000P_0402_50V7K

PR99

PR102

PR103

PC97

.1U_0402_16V7K@

0.01U_04 02_25V7K

0_0402_5%

PC110
1000P_0 402_50V7K

1 2

1 2

12

PC96

0.1U_0402_10V7K

PU10

1

VREF

2

REFIN

3

GSNS

4

VSNS

PC107

1 2

PR117

1 2

10_0402 _1%

PU8 SY8033BDBC_ DFN10_3X3

10

PVIN

9

PVIN

8

SVIN

5

EN

TP

11

@

12

PC89

0.1U_0402_10V7K

13

D

2

G

PQ23

2N7002K W_SOT323 -3

S

+3VS

PR107

1 2

100K_0402_1%

PR109

100K_0402_1%

1 2

17

16

15

PAD

TPS5121 9RTER_QFN16_ 3X3

COMP5TRIP6GND

4

MODE

PGOOD

7

12

PR115

54.9K_0402_1%

4

LX

PG

LX

FB

NC

7

1

13

14

EN

8

2

1.8VSP_LX

3

6

NC

1UH_PH0 41H-1R0MS_3.8A _20%

12

12

FB=0.6Volt

+1.5V

1

PJ15

1

JUMP_43 X118

@

2

2

PC90

4.7U_080 5_6.3V6K

1 2

PR110

0_0603_ 5%

1 2

BST_1.05 VS_VCCP

BST

12

SW

11

DH

10

DL

9

V5

PGND

Security Class ification

Security Class ification

Security Class ification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

PR101

1K_0402 _1%

LX_1.05V S_VCCP

DH_1.05V S_VCCP

12

12

PR104

0.1U_060 3_25V7K

PL9

1 2

20K_040 2_1%

PR96

4.7_1206_5%

PC86

1.8VSP_F B

680P_0603_50V7K

10K_040 2_1%

12

PC95

1K_0402_1%

0.1U_0402_16V4Z

PC103

1 2

DL_1.05V S_VCCP

12

PC108

1U_0603 _10V6K

2011/11/ 01

2011/11/ 01

2011/11/ 01

3

PR97

PR100

12

PC93

10U_0603_6.3V6M

+5VALW

12

12

1

2

3

4

12

12

PC85

12

68P_0402_50V8J

PU9

VIN

GND

VREF

VOUT

APL5336 KAI-TRL_SOP8P8

VCNTL

8

NC

7

NC

6

5

NC

9

TP

+0.75VSP

PC94

10U_0603_6.3V6M

5

4

123

PQ25

5

4

123

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

12

PC88

PC87

22U_0805_6.3VAM

12

1.05VS_B +

PQ24

AON6428 L_DFN8-5

12

PR113

AON6504 1N DFN

12

PC106

+1.8VSP

22U_0805_6.3VAM

+3VALW

PC91

1U_0603 _10V6K

12

PC98

PC101

0.1U_0402_25V6

2200P_0402_50V7K

PL10

1UH_PCM B062D-1R0MS_9 A_20%

1 2

4.7_1206_5%

1000P_0603_50V7K

2012/12/ 31

2012/12/ 31

2012/12/ 31

2

+1.05VS_VCCPP OCP(min)=22.38A

PJ18

2

112

12

12

PC99

4.7U_0805_25V6-K

JUMP_43 X118@

12

PC102

4.7U_0805_25V6-K

330U_D2_2VM_R6M

1

PC105

+

2 3

Title

Title

Title

1.8VSP/0.75VSP/1.05VS_VCCPP

1.8VSP/0.75VSP/1.05VS_VCCPP

1.8VSP/0.75VSP/1.05VS_VCCPP

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

PJ13

2

112

JUMP_43 X118

@

PJ14

2

112

JUMP_43 X118@

PJ16

2

112

JUMP_43 X118@
PJ17

2

112

JUMP_43 X118@

B+

+1.05VS_VCCPP

Y400S-NM-A141

Y400S-NM-A141

Monday, January 14, 2013

Monday, January 14, 2013

Monday, January 14, 2013

Y400S-NM-A141

1

+1.05VS+1.05VS_ VCCPP

+1.8VS+1.8VSP

+0.75VS+0.75VSP

57 65

57 65

57 65

1.0

1.0

1.0

of

of

of

8

7

6

5

4

3

2

1

+VGA_CORE

H H

12

PC815

G G

+VGA_CORE

1

12

PC829

2

22U_0805_6.3V6M

1

1

F F

PC869

PC868

2

2

22U_0805_6.3V6M

22U_0805_6.3V6M

nder VGA Core

U

12

12

12

PC802

PC801

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

12

12

PC817

PC816

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

Near VGA Core

PC830

47U_0805_6.3V6M

PC803

PC804

4.7U_0603_6.3V6M

12

PC818

0.1U_0402_10V7K

12

12

PC819

4.7U_0603_6.3V6M

PC806

PC805

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

12

12

PC820

PC821

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

12

12

12

PR805 = 45.3K ==>Fsw = 450KHz

PR806 0_0402_5%

E E

D D

VSSSENSE_VGA<24>

VCCSENSE_VGA<24>

1 2

PC853

1000P_0402_50V7K

1 2

PR807 0_0402_5%

12

47P_0402_50V8J

VCC_SEN

N14P-GT 35W

peak=50A

I

C C

Imax=35A
Iocp=64.8A
Fsw=450KHz
bulk cap 330uF 9m *5

GB4-128 package

12

12

12

PC808

PC807

4.7U_0603_6.3V6M

PC822

4.7U_0603_6.3V6M

PC852

1 2

4.7U_0603_6.3V6M

12

VSS_SEN

10K_0402_1%

1 2

PC823

4.7U_0603_6.3V6M

VREF

0_0402_5%

PR808

4.7U_0603_6.3V6M

12

PC824

PR825

1 2

PR809

51_0402_1%

1 2

N14P-GS 25W
Ipeak=36A
Imax=25A
Iocp=64.8A
Fsw=450KHz
bulk cap 330uF 9m *3

12

12

PC809

12

4.7U_0603_6.3V6M

PR824

20K_0402_1%

PC854

0.01U_0603_50V7K

Thermistor near MOSFET
t

PC811

PC810

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

12

12

PC825

PC826

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

12

2700P_0402_50V7-K

PR826

18K_0402_1%

12

36.5K_0402_1%

PC850 10P_0402_50V8J

1 2

PC851

100P_0402_50V8J

rigger point 97 degree C.

12

PC812

4.7U_0603_6.3V6M

12

PC827

4.7U_0603_6.3V6M

PC859

@

12

12

PC856

2200P_0402_50V7K

PR805

1 2

FB2_VGA

82K_0402_1%

.1U_0402_16V7K

12

PC813

4.7U_0603_6.3V6M

PC828

4.7U_0603_6.3V6M

12

12

1 2

PR810

PC849

10P_0402_50V8J@

COMP_VGAFB1_VGA

12

4.7U_0603_6.3V6M

PC858

12

FB_VGA

PC814

4.7U_0603_6.3V6M

PR823

20K_0402_1%

PR829
2K_0402_1%

VREF

FS

12

NVVDD PWM_VID

+3VS_VGA

1 2

PR801 0_0402_5%

12

GPU_VID

12

VIDBUF

6

7

REFIN

8

VREF

9

NCP81172MNTWG_QFN24_4X4

FS

10

FBRTN

11

FB

12

COMP

GND

25

12

12

PH801

PR812 5.9K_0402_1%

100K_0402_1%_NCP15WF104F03RC

VREF

PD801

RB751V-40_SOD323-2

<23>

PR803

120K_0402_5%

1 2

DPRSLPVR_VGA

PC855

.1U_0402_16V7K

1 2

1 2

1 2

PR802 0_0402_5%

PR804 10K_0402_5%

UGATE1_VGA

EN_VGA

PSI_VGA

2

5

4

3

EN

PSI

VID

VIDBUF

TSNS13TALERT#14VCC15PGOOD16HG217BST2

HG1

PU801

VCC_VGA

PR816 10K_0402_5%

PR815 2.2_0402_5%

1 2

PC848

1U_0402_10V6K

PR813 10K_0402_5%

12

12

<23>

BOOT1_2_VGA

1

BST1

PH1

LG1

PGND

PVCC

LG2

PH2

18

BOOT2_VGA

UGATE2_VGA

12

12

+3VS

24

23

22

21

20

19

+3VS

PR831
10K_0402_5%

@

1 2

12

PR832
10K_0402_5%

PHASE1_VGA

LGATE1_VGA

PVCC_VGA

DGPU_PWROK <19,27,55>

+3VS

+5VS

NVDD_PWR_EN <18>

UGATE1_2_VGA

PC838

0.22U_0603_10V7K

1 2

0_0402_5%

12

S TR FDMS3664S 2N POWER56-8

+5VS

PR818

12

BOOT2_2_VGA

PR822

0_0402_5%

12

PR821

0_0603_5%

12

PR811 0_0402_5%

1 2

PC839 4.7U_0603_10V6K

1 2

PR817

0_0603_5%

PHASE2_VGA

LGATE2_VGA

MDU1512, Rdson(max)=5mohm

12

PR834

2.2_0402_5%

UGATE2_2_VGA

PC847

0.22U_0603_10V7K

1 2

+VGA_B+

12

12

12

PC832

PC831

0.1U_0402_25V6

S TR FDMS3664S 2N POWER56-8

PQ801

2

1

6

435

@

1

7

6

S TR FDMS3664S 2N POWER56-8

1

6

PQ802

2

7

12

PR820

@

435

PQ803

2

7

435

4.7_1206_5%

SNUB1_VGA

12

680P_0402_50V7K@

S TR FDMS3664S 2N POWER56-8

1

6

12

PC833

10U_0805_25V6K

PL803

1 2

PQ804

7

PC834

2200P_0402_50V7K

0.24UH_FDUE0630J-H-R24M-P3_22A_20%

PC835

2

435

PL801

HCB2012KF-121T50_0805

1 2

PL802

HCB2012KF-121T50_0805

1 2

10U_0805_25V6K

1

1

+

+

PC837

PC836

2

2

12

0.24UH_FDUE0630J-H-R24M-P3_22A_20%

1 2

12

@

PR819

4.7_1206_5%

@

SNUB2_VGA

12

PC844

680P_0402_50V7K

PL804

330U_D2_2V_Y

330U_D2_2V_Y

12

PC840

PC841

0.1U_0402_25V6
2200P_0402_50V7K

1

+

2

+VGA_CORE

1

+

PC857

2

+VGA_B+

12

PC842

10U_0805_25V6K

+VGA_CORE

PC845

330U_D2_2V_Y

B+

330U_D2_2V_Y

12

PC843

1

+

PC846

2

330U_D2_2V_Y

10U_0805_25V6K

B B

A A

8

7

6

5

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC F UTURE CENTER. AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC F UTURE CENTER. AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC F UTURE CENTER. AND CONTAINS CON FIDENTIAL
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.

4

2011/11/01

2011/11/01

2011/11/01

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

3

2012/12/31

2012/12/31

2012/12/31

Title

Title

Title

VGA_COREP

VGA_COREP

VGA_COREP

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet

Date: Sheet

Date: Sheet

2

Y400-LA8691P

Y400-LA8691P

Y400-LA8691P

Monday, January 14, 2013

Monday, January 14, 2013

Monday, January 14, 2013

58 65

58 65

58 65

1

of

of

of

1.0

1.0

1.0

5

4

3

2

1

PR190

PR188

PR247

1K_0402_1%

CPU2@

0.033u_0402_16V7K

1 2

FBA3

PC191

PR216

54.9_0402_1%

1 2

PR220

1 2

1 2

PC174

PC178

0.033U_0402_16V7K

12

.1U_0402_16V7K

0_0402_5%

PR238

10_0402_1%

8.06K_0402_1%

CPU3@

3P: 806
2P: 1K

GFX@

FBA1

12

GFX@

VR_RDYA

VR_SVID_DAT1

+3VS

12

PR227
10K_0402_5%

FB_CPU3

PR241

1 2

PR247

1 2

806_0402_1%

PR189

1 2

806_0402_1%

GFX@

+3VS

12

VR_ON<45>

CPU_B+

PR222 1K_0402_1%

PR229

1 2

0_0402_5%

PR232

1 2

0_0402_5%

PC204

49.9_0402_1%

1 2

0.033u_0402_16V7K

FB_CPU2

PC207

DROOP

PR193

1 2

10_0402_1%

GFX@

PR195

1 2

1K_0402_1%

GFX@

PR210
10K_0402_1%

+5VS

PR221

95.3K_0402_1%

1 2

1 2

12

PR236

1 2

1 2

12

0.033u_0402_16V7K

PC212

1 2

1000P_0402_50V7K

GFX@

1 2

FBA2

560P_0402_50V7K

1000P_0402_50V7K

PR213

1 2

2_0603_5%

PC188

1 2

2.2U_0603_10V7K
PR217

1 2

0_0402_5%

PR219

1 2

10K_0402_1%

12

PC194

VSN

PC197
1000P_0402_50V7K

VSP

PR234

1 2

1K_0402_1%

PC202

1 2

FB_CPU1

470P_0402_50V7K

PR242

806_0402_1%

PR244

24.9K_0402_1%

CPU2@

CSREFCSCOMP

PC180

0.01U_0402_25V7K

PC184

6132_VCC

VR_ON_CPU

VBOOT

DIFF_CPU

IMVP_IMON<45>

0_0402_1%

SLI@

2P: 24K
1P: 24.9K

PR196

1 2

5.11K_0402_1%

GFX@

2P: 21.5K
1P: 15.8K

1 2

GFX@

VR_RDYA

VR_SVID_DAT1
VR_SVID_ALRT#
VR_SVID_CLK

ROSC_CPU
VRMP
VR_HOT#
VGATE

PC200

10P_0402_50V8J

CPU2@

3P: 22p
2P: 10p

CPU3@

PR237

12

6.04K_0402_1%

3P: 23.7K
2P: 24.9K

PC181

1 2

10P_0402_50V8J

COMPA1

PR202

1 2

0_0402_5%

PR207

1 2

0_0402_5%

PU14

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15

PC200

22P_0402_50V8J

COMP_CPU1

CPU3@

PC175

1 2

.1U_0402_16V7K

1 2

PR190

GFX@

24K_0402_1%

GFX@

GFX@

GFX@

PC182

1 2

2200P_0402_50V7K

1 2

0_0402_5%

PR199

SLI@

SLI@

SLI@

DIFFA

TRBSTA#

58

60

57

59

61

PAD

VSPA

VSNA

DIFFA

VCC
VDDBP
VRDYA
EN
SDIO
ALERT#
SCLK
VBOOT

NCP6132AMNR2G_QFN60_7X7

ROSC
VRMP
VRHOT#
VRDY
VSN
VSP
DIFF

COMP

TRBST#

18

19

16

FB_CPU

TRBST#

COMP_CPU

12

PC203

12

2200P_0402_50V7K

1 2

PC209

PR244

1 2

23.7K_0402_1%

PUT COLSE
TO VCORE
Phase 1
Inductor

FBA

56

TRBSTA#

IOUT

20

ILIM_CPU

1 2

COMPA

IMONAIMONA

54

55

FBA

COMPA

DROOP

ILIM

21FB17

DROOP

CPU3@

PR233 21K_0402_1%

CSCOMPCSCOMPCSCOMPCSCOMPCSCOMPCSCOMP

.1U_0402_16V7K

GFX@

GFX@

PR203

1 2

21.5K_0402_1%

DROOPA

ILIMA

52

53

ILIMA

IOUTA

DROOPA

CSCOMP22CSP325CSREF24CSSUM

23

1 2

PC969@QC

1 2

75K_0402_1%

GFX@

1 2

1 2

PC177

PC176

1200P_0402_50V7K

330P_0402_50V8J

12

PR197

CSCOMPA

51

PR248

PH7

165K_0402_1%

PR198

1 2

GFX@

0_0402_5%SLI@

91K_0603_1%

1 2

PR200

91K_0603_1% GFX@

PC185

GFX@

1000P_0402_50V7K
PR204

12

1 2

0_0402_5% SLI@

PR205

0_0402_5% SLI@

PR208

0_0402_5%

1 2

CSP1A

.1U_0402_16V7K

CSSUMA

TSENSEA

PR211

0_0402_5%

46

49

48

47

50

CSP2A

CSP1A

TSNSA

CSREFA

CSSUMA

PWMA

CSCOMPA

BSTA

HGA
SWA

LGA

BST2

HG2

SW2

LG2
PVCC
PGND

LG1

SW1

HG1

BST1

CSP1

DRVEN

CSP2

TSNS

PWM

27

29

26

28

30

TSENSETSENSE CSP2A

PC198

1 2

.1U_0402_16V7K

CSP1
CSP2
CSP3

3P: 21K
2P: 12.4K

PC205
1000P_0402_50V7K

CSSUM

PC208

1 2

1500P_0402_50V7K

1 2

1 2

NTC_PH201

12

220K_0402_5%_ERTJ0EV224J

PR191

GFX@

1 2

12

NTC_PH203

PR194

2P: install

SWN2A

1P: @

SWN1A

12

SLI@

12

GFX@

PC187

12

SLI@

45

44
43
42
41
40

BST2

39

38

37

36

6132P_VCCP

35

34

33

32
31

BST1

PR228

1 2

73.2K_0402_1%

CPU3@

PR233

12.4K_0402_1%

CPU2@

CSREF <60>

CPU3@

PC210
330P_0402_50V7K

PC211
330P_0402_50V7K

PR249

1 2

165K_0402_1%

GFX@

75K_0402_1%

CSREFA <60>

+5VS

1 2

36K_0402_1%

GFX@

BSTA1

3P: 73.2K
2P: 41.2K

6132_PWM <60>

DRVEN <60>

PC208

1200P_0402_50V7K

CPU2@

3P: 1500p
2P: 1200p

12

PUT COLSE
TO GT
Inductor

PH4

220K_0402_5%_ERTJ0EV224J

GFX@

CSREFA

PC183

0.047U_0402_16V7K

GFX@

1 2

CSP1A

CSREFA

PC186

0.047U_0402_16V7K

1 2

CSP2A

GFX@

PR212

2P: 36K
1P: 26.1K

PR214

1 2

2.2_0603_5%

HG1A <60>

GFX@

LG1A <60>

1 2

PR218

4.7_0603_5%

HG2 <60>

LG2 <60>

1 2

PR223

0_0402_5%

LG1 <60>

HG1 <60>

1 2

PR225

4.7_0603_5%

41.2K_0402_1%

CPU2@

CSP3

CSP3

PR300

CSREF

21K_0402_1%

@

1 2

CSP2

@

PR301

CSREF

21K_0402_1%

1 2

CSP1CSP1

@

PR302

CSREF

21K_0402_1%

1 2

PR243

1 2

130K_0603_1%

1 2

PR245

130K_0603_1%

1 2

PR246

130K_0603_1%

CPU3@

3P: install
2P: @

GFX@

PR201 5.49K_0402_1%

1 2

1 2

PR209

5.49K_0402_1%

GFX@

6132_PWMA <60>

PC189

12

BSTA1_1

0.22U_0603_10V7K
PC192

12

BST2_1

0.22U_0603_10V7K

12

PC193

2.2U_0603_10V7K

12

BST1_1

PC195 0.22U_0603_10V7K

PR228

1 2

12

6.98K_0402_1%

PC199

0.047U_0402_16V7K

1 2

12

6.98K_0402_1%

PC201

0.047U_0402_16V7K

1 2

12

6.98K_0402_1%

PC206

0.047U_0402_16V7K

SWN1

SWN2

SWN3

CSCOMPA

SWN1A <60>

2P: install
1P: @

SWN2A <60>

GFX@

CPU3@

PR231

3P: install
2P: @

PR235

PR239

+5VS

PR186

10_0402_1%

1 2

D D

TRBSTA#

C C

PC190

VR_SVID_DAT<9>

VR_SVID_ALRT#<9>

VR_SVID_CLK<9>

GFX@

1 2

8.06K_0402_1%

GFX@

VCC_AXG_SENSE<10>

VSS_AXG_SENSE<10>

+1.05VS

12

PR215

.1U_0402_16V7K

130_0402_1%

1 2

+1.05VS

12

PR226

PC196

@

43P_0402_50V7K

75_0402_1%

VR_HOT#<45>

VSSSENSE<9>

VCCSENSE<9>

B B

A A

1 2

TRBST#

VGATE<16>

PR192

0_0402_1%

SLI@

1 2

1.65K_0402_1%

2P: 1.65K
1P: 1K

SW1A <60>

SW2 <60>

SW1 <60>

PR192

GFX@

Option for
1 phase GFX

GFX@

PC179

1 2

1000P_0402_50V7K

TSENSEA

12

PR206

15K_0402_1%

@

PUT COLSE
TO V_GT
HOT SPOT

CSP2A

CSREFADROOPA

PH5

100K_0402_1%_TSM0B104F4251RZ

1 2

GFX@

+5VS

0_0402_5%

2Phase: @
1Phase: install

12

@

PR224

+5VS

CSP3

TSENSE

12

PR240

15K_0402_1%

@

PUT COLSE
TO VCORE
HOT SPOT

CPU2@

12

PR230

1 2

3Phase: @
2Phase: install

0_0402_5%

PH6

100K_0402_1%_TSM0B104F4251RZ

Option for
2 phase CPU

SWN3 <60>

SWN2 <60>

SWN1 <60>

2012/05/07
change PR240, PR206 from 8.25Kohm to 15Kohm

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2011/11/01

2011/11/01

2011/11/01

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2012/12/31

2012/12/31

2012/12/31

Title

CPU_CORE

CPU_CORE

CPU_CORE

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Y400S-NM-A141

Y400S-NM-A141

Y400S-NM-A141

Monday, January 14, 2013

Monday, January 14, 2013

Monday, January 14, 2013

59 65

59 65

59 65

of

of

1

of

1.0

1.0

1.0

5

4

3

2

1

CPU_B+

5

PQ27

PQ29

PQ32

4

CPU3@

4

CPU3@

PC330

5

123

5

123

9

8

7

6

5

BST3_1

4

4

PC228

0.22U_0603_10V7K

1 2

CPU3@

HG3

SW3

LG3

123

5

123

AON6504 1N DFN

AON6428L_DFN8-5

AON6504 1N DFN

HG1<59>

D D

SW1<59>

LG1<59>

PR254

1 2

BST3

4.7_0603_5%

CPU3@

PU15

1

BST

C C

6132_PWM<59>

DRVEN<59>

+5VS

CPU3@

PR255
2K_0402_1%

PR256

12

0_0402_5% CPU3@

PC233

2.2U_0603_10V7K

CPU3@

12

EN_CPU3

12

VCC_CPU3

FLAG

2

PWM

DRVH

3

EN

SW

4

VCC

GND

DRVL

NCP5911MNTBG_DFN8_2X2

CPU3@

3Phase: install
2Phase:: @

12

PC213

1000P_0402_50V7K

12

PR250

4.7_1206_5%

SNUB_CPU1

12

PC226

680P_0402_50V7K

PQ31

AON6428L_DFN8-5

12

10U_0805_25V6K

12

SNUB_CPU3

12

12

12

PC216

PC215

PC214

10U_0805_25V6K

0.1U_0402_25V6

PL15

0.36UH_VMPI1004AR-R36M-Z03_30A_20%

1

2

PC229

10U_0805_25V6K

PR257

4.7_1206_5%

CPU3@

PC234

680P_0402_50V7K

CPU3@

2200P_0402_25V7K

12

CPU3@

PL17

1

2

12

4

3

<BOM Structure>

PC230

10U_0805_25V6K

CPU3@

+VCC_CORE

V1N_CPU

12

CPU3@

B+

HCB4532KF-800T90_1812

12

PR252

12

10_0402_1%

CPU_B+

12

12

PC232

PC231

0.1U_0402_25V6
2200P_0402_25V7K

+VCC_CORE

CPU3@

CPU3@

4

3

0.36UH_VMPI1004AR-R36M-Z03_30A_20%

V3N_CPU

PR258

10_0402_1%

CPU3@

PL14

1 2

PC221

470P_0603_50V7K

CSREF <59>

SWN1 <59>

12

CSREF

1

+

2

PC222

SWN3 <59>

5

CPU_B+

1

12

12

+

PC223

PC224

2

68U_25V_M_R0.36

68U_25V_M_R0.36

1000P_0603_50V7K

HG2<59>

PC225

470P_0603_50V7K

SW2<59>

LG2<59>

QC 45W CPU
VID1=0.9V
IccMax=94A
Icc_Dyn=66A
Icc_TDC=52A
R_LL=1.9m ohm
OCP~110A

4

4

123

5

123

PQ28

AON6428L_DFN8-5

PQ30

AON6504 1N DFN

DC 35W CPU
VID1=1.05V
IccMax=53A
Icc_Dyn=43A
Icc_TDC=36A
R_LL=1.9m ohm
OCP~65A

PC440

1000P_0402_50V7K

12

SNUB_CPU2

12

12

12

PR251

4.7_1206_5%

PC227

680P_0402_50V7K

PC218

PC217

10U_0805_25V6K

10U_0805_25V6K

PL16

0.36UH_VMPI1004AR-R36M-Z03_30A_20%

1

2

CPU_B+

12

12

12

PC220

PC219

0.1U_0402_25V6
2200P_0402_25V7K

+VCC_CORE

4

3

12

PR253

10_0402_1%

CSREF

SWN2 <59>

V2N_CPU

B B

5

HG1A<59>

SW1A<59>

LG1A<59>

A A

4

GFX@

5

4

GFX@

5

PQ33

AON6428L_DFN8-5

123

PQ35

AON6504 1N DFN

123

GFX@

12

PC235

10U_0805_25V6K

GFX@

12

12

PC236

10U_0805_25V6K

PR261

PC245

GFX@

12

SNUB_GFX1

12

12

PC237

PC238

0.1U_0402_25V6

GFX@

2200P_0402_25V7K

+VCC_GFXCORE_AXG

12

PR267

10_0402_1%

GFX@

CSREFA <59>

SWN1A <59>

QC 45W GT2
VID1=1.23V
IccMax=46A
Icc_Dyn=37A
Icc_TDC=38A
R_LL=3.9m ohm
OCP~55A

DC 35W GT2
VID1=1.23V
IccMax=33A
Icc_Dyn=20.2A
Icc_TDC=21.5A
R_LL=3.9m ohm
OCP~40A

3

12

4.7_1206_5%@

PR265

GFX@

680P_0402_50V7K@

PL18

0.36UH 20% PDME064T-R36MS1R405 24A

1 2

GFX@

0_0402_5%

4

2Phase: install
1Phase:: @

1 2

PR259

2.2_0603_5%

GFX@

BST

FLAG

PWM

DRVH

EN

VCC

GND

DRVL

Deciphered Date

Deciphered Date

Deciphered Date

BSTA2_1

PC240

0.22U_0603_10V7K

1 2

GFX@

9

8

HG2A

7

SW

SW2A

6

5

2012/12/31

2012/12/31

2012/12/31

2

PQ36

AON6504 1N DFN

LG2A

4

GFX@

4

BSTA2

PU16

1

6132_PWMA<59>

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC F UTURE CENTER. AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC F UTURE CENTER. AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC F UTURE CENTER. AND CONTAINS CON FIDENTIAL
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.

+5VS

DRVEN

GFX@

2K_0402_1%

12

GFX@

PR262
0_0402_5%

GFX@

PR260

PC244

2.2U_0603_10V7K

2011/11/01

2011/11/01

2011/11/01

2

3

12

EN_GFX2

4

12

VCC_GFX2

NCP5911MNTBG_DFN8_2X2

GFX@

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

12

12

5

PQ34

AON6428L_DFN8-5

123

5

GFX@

123

Title

Title

Title

CPU_CORE

CPU_CORE

CPU_CORE

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet

Date: Sheet

Date: Sheet

PC241

10U_0805_25V6K

GFX@

0.36UH 20% PDME064T-R36MS1R405 24A

12

PR263

@

4.7_1206_5%

SNUB_GFX2

12

PC246

@

680P_0402_50V7K

Monday, January 14, 2013

Monday, January 14, 2013

Monday, January 14, 2013

12

12

PC243

PC242

PC239

10U_0805_25V6K

0.1U_0402_25V6

GFX@

GFX@

PL19

1 2

GFX@

12

PR264

0_0402_5%

GFX@

Y400S-NM-A141

Y400S-NM-A141

Y400S-NM-A141

1

GFX@

2200P_0402_25V7K

+VCC_GFXCORE_AXG

10_0402_1%

GFX@

PR266

12

CSREFA

of

60 65

of

60 65

of

60 65

SWN2A <59>

1.0

1.0

1.0

CPU_B+CPU_B+

5

4

3

2

1

+VCC_CORE

1

PC247

10U_080 5_6.3VAM

2

D D

1

PC252
10U_080 5_6.3VAM

2

1

PC248
10U_080 5_6.3VAM

2

1

PC253
10U_080 5_6.3VAM

2

1

PC249
10U_080 5_6.3VAM

2

1

PC254
10U_080 5_6.3VAM

2

1

PC250
10U_080 5_6.3VAM

2

1

PC255
10U_080 5_6.3VAM

2

+VCC_CORE

1

PC266
22U_080 5_6.3V6M

2

1

PC290
22U_080 5_6.3V6M

2

C C

1

PC306
22U_080 5_6.3V6M

2

1

PC267
22U_080 5_6.3V6M

2

1

PC291
22U_080 5_6.3V6M

2

1

PC307
22U_080 5_6.3V6M

2

1

PC268
22U_080 5_6.3V6M

2

1

PC292
22U_080 5_6.3V6M

2

1

PC308
22U_080 5_6.3V6M

2

1

PC269
22U_080 5_6.3V6M

2

1

PC293
22U_080 5_6.3V6M

2

1

PC309
22U_080 5_6.3V6M

2

+CPU_CORE +VCC_GFXCORE_AXG

1

PC251
10U_080 5_6.3VAM

2

1

PC256
10U_080 5_6.3VAM

2

1

PC270
22U_080 5_6.3V6M

2

1

PC294
22U_080 5_6.3V6M

2

1

PC310
22U_080 5_6.3V6M

2

1

PC257
10U_080 5_6.3VAM

2

+VCC_GFXCORE_AXG

22U_0805_6.3V6M

22U_0805_6.3V6M

GFX@

GFX@

GFX@

22U_0805_6.3V6M

PC259

PC258

1

1

2

2

GFX@

GFX@

22U_0805_6.3V6M

22U_0805_6.3V6M

PC282

GFX@

330U_D2_2VM_R9M

PC283

1

2

GFX@

1

PC303

+

2 3

GFX@

1

2

1

+

2 3

22U_0805_6.3V6M

PC260

1

1

2

2

GFX@

22U_0805_6.3V6M

22U_0805_6.3V6M

PC284

1

1

2

2

GFX@

330U_D2_2VM_R9M

1

PC304

+

2 3

GFX@

PC261

GFX@

PC285

GFX@

330U_D2_2VM_R9M

22U_0805_6.3V6M

22U_0805_6.3V6M

PC263

PC262

1

1

2

2

GFX@

GFX@

22U_0805_6.3V6M

22U_0805_6.3V6M

PC287

PC286

1

1

2

2

GFX@

GFX@

PC305

PC59@DC

22U_0805_6.3V6M

22U_0805_6.3V6M

PC265

PC264

1

1

2

2

GFX@

22U_0805_6.3V6M

22U_0805_6.3V6M

PC288

1

2

PC289

1

2

GFX@

Below is 458544_CRV_PDDG_0.5 Table 5-8.

5 x 22 µF (0805)

Socket Bottom

5 x (0805) no-stuff
sites

7 x 22 µF (0805)

Socket Top

2 x (0805) no-stuff
sites

+1.05VS

22U_0805_6.3V6M

22U_0805_6.3V6M

1

PC271

2

22U_0805_6.3V6M

1

1

PC272

2

2

+1.05VS

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

1

1

PC273

2

1

2

PC275

PC274

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

PC295

PC296

2

22U_0805_6.3V6M

1

PC276

2

22U_0805_6.3V6M

1

PC297

2

22U_0805_6.3V6M

1

2

22U_0805_6.3V6M

1

2

1

1

PC277

PC278

2

2

22U_0805_6.3V6M

1

1

PC299

PC298

2

2

1

+

2 3

22U_0805_6.3V6M

22U_0805_6.3V6M

PC279

22U_0805_6.3V6M

PC300

330U_D2_2VM_R6M

PC311

22U_0805_6.3V6M

1

1

PC280

PC281

2

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

1

2

PC302

PC301

2

330U_D2_2VM_R6M

1

PC312

+

2 3

PC38,PC39,PC40,PC41

1

PC313
22U_080 5_6.3V6M

2

1

PC314
22U_080 5_6.3V6M

2

1

PC315
22U_080 5_6.3V6M

2

+VCC_CORE

1

1

1

+

+

PC317

PC318

CPU3@

PC319

2 3

470U_D2_2VM_R4.5M

B B

2 3

@

470U_D2_2VM_R4.5M

1

1

+

+

PC321

PC320

2 3

2 3

470U_D2_2VM_R4.5M

470U_D2_2VM_R4.5M

1

+

2 3

2

470U_D2_2VM_R4.5M

1

PC316
22U_080 5_6.3V6M

2

PC8,PC21,PC22,PC63

+

PC322

470U_D2_2VM_R4.5M

PC38,PC39,PC40,PC41

PC32,PC49,PC54,PC55,PC56

DC:PC73,PC74,PC75,PC76,PC77,PC78(330uF/9m)
QC:PC76,PC78(470uF/4.5m),PC73,PC74,PC75(330uF/9m)

A A

Title

Title

Security Class ification

Security Class ification

Security Class ification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2011/11/ 01

2011/11/ 01

2011/11/ 01

3

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2012/12/ 31

2012/12/ 31

2012/12/ 31

2

Title

CPU_CORE1

CPU_CORE1

CPU_CORE1

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Monday, January 14, 2013

Monday, January 14, 2013

Monday, January 14, 2013

Y400S-NM-A141

Y400S-NM-A141

Y400S-NM-A141

1

61 65

61 65

61 65

of

of

of

1.0

1.0

1.0

5

4

3

2

1

Charge Option() bit[8]=1

B+

PR268

4

3

ACN

ACP

PC333

+3VALWP

1 2

12

@

PR276

100K_0402_1%

PR279

1 2

1 2

12

4.7M_0603_1%

5

4

ACOK

PU17

BQ24737RGRR_VQFN20_ 3P5X3P5

11

12

BM#

6.8_0603_5%
PC345

@

0.1U_0603_25V7K

PR295

10K_0402_5%

1 2

12

+3VS

0.1U_0603_25V7K

PR277

10K_0603_1%@

@

3

CMPIN

CMPOUT

SRN12BM

SRP

12
13

PR294

PR293

10_0603_5%

12

PC346

0.1U_0603_25V7K

PC335

2

ACP

GND

14

PL20

1UH_PCMB061H-1R0M S_7A_20%

1 2

SH00000AA00

21

20

19

18

17

BST_CHG

RB751V-40_SOD323-2

16

12

12

1 2

PD7

PC344
1U_0603_25V6

5

1 2

PC324

10U_0805_25V6K@

PC334

0.1U_0603_25V7K

0.1U_0603_25V7K

12

1

ACN

VCC

PHASE

HIDRV

BTST

REGN

LODRV

15

47K_0402_1%

ACPRN

12

TP

PR296

PC325

10U_0805_25V6K@

PR282

10_1206_5%

1 2

DH_CHG

12

BQ24737_VDD

DL_CHG

BQ24737_VDD

12

PR297
10K_0402_1%

34

PQ45B

P2

PC339

1 2

1U_0603_25V6

PR288

2.2_0603_5%

1 2

1 2

LX_CHG

0.047U_0603_16V7K

PR298

10K_0402_1%

1 2

PACIN

12

PR299

12K_0402_1%

1 2

PC331

4.7U_0805_25V6-K

PC340

1 2

PC332

PC326

4.7U_0805_25V6-K

4.7U_0805_25V6-K

AON7408L_DFN8-5

12

ACIN <45>

1 2

PQ46

CHG_B+

PQ39

AO4423L 1P SO8

1
2
3 6

DISCHG_G

PC327

2200P_0402_50V7K

5

4

123

5

4

123

PR271

47K_0402_1%

1 2

PR272
10K_0402_1%

1 2

DISCHG_G-1

PQ42

13

DTC115EUA_SC70-3

2

SH000005Y80

12

6251_SN

12

PL21

1 2

PR290

4.7_1206_5%

PC343

680P_0603_50V7K

4.7UH_KJ0730-4R7M _5.5A_20%

PQ48
AON7702L_DFN8-5

ACOFF-1

PD5

1SS355_SOD323-2

1 2

1 2

CHGCHG

4

1 2

PD6
1SS355_SOD323-2

12

PC336

0.1U_0603_25V7K

PR285

0.01_1206_1%

1

2

8
7

5

PR273
200K_0402_1%

61

PQ45A
2N7002KDW -2N_SOT363-6

4

3

VIN

2

PACIN

BATT+

12

12

PC342

PC341

10U_0805_25V6K

10U_0805_25V6K

PQ37

AO4423L 1P SO8

DTA144EUA_SC70-3

200K_0402_5%

13

2

PQ43A

PQ47

DTC115EUA_SC70-3

PR286

1 2

10K_0402_5%

8
7

5

PQ40

2

1 3

PQ41

DTC115EUA_SC70-3

PR281
47K_0402_1%

1 2

2

ACOFF-1

12

PR291
0_0402_5%

34

PQ44B

5

2N7002KDW-2N_SOT363-6

4

VIN

D D

12

PR269

61

2

2N7002KDW -2N_SOT363-6

C C

PACIN

ACOFF<45>

B B

BATT_OUT

1
2
36

12

150K_0402_1%

5

13

P2

12

PR270

PC328

0.1U_0603_25V7K

P2-1

12

P2-2

34

PQ43B

EC_SMB_DA1<45,49,53>

EC_SMB_CK1<45,49,53>

PQ38

AO4423L 1P SO8

1
2
3 6

4

2200P_0402_50V7K

200K_0402_1%

PR275

2N7002KDW-2N_SOT363-6

2012/02/29
A

dd PC337 0.1uF

0.1U_0603_25V7K

12

PR274

5.1K_0402_5%

61

PQ44A
2N7002KDW -2N_SOT363-6

2

PR283

64.9K_0603_1%

1 2

PC337 .1U_0603_25V7K

12

PR280

8
7

5

PC323

1 2

1 2

PC329

@

VIN

12

390K_0603_1%

PR284

0_0402_5%

1 2

PR287

0_0402_5%

1 2

+3VALWP

P3

BATT_OUT <53>

1 2

147K_0402_1%

ADP_I<45,53>

1 2

100P_0603_50V8

PR289

PR292

100K_0402_1%

PC338

PR278

39.2K_0402_1%

6

7

8

9

10

12

0.01_1206_1%

1

2

ACPRN< 54>

@

ACDET

IOUT

SDA

SCL

ILIM

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.

3

2011/11/01

2011/11/01

2011/11/01

2N7002KDW-2N_SOT363-6

For disable pre-charge circuit.

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2012/12/31

2012/12/31

2012/12/31

2

Title

Title

Title

CHARGER

CHARGER

CHARGER

Size D ocument Number Rev

Size D ocument Number Rev

Size D ocument Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Monday, January 14, 2013

Monday, January 14, 2013

Monday, January 14, 2013

Y400S-NM-A141

Y400S-NM-A141

Y400S-NM-A141

1

of

of

of

62 65

62 65

62 65

1.0

1.0

1.0

5

4

3

2

1

D D

DE

DE

A1

VIN

BATT

B1

V

V

PU2

B5

V

B4

A3

+3VALW

A5

V

B7 2

V
V

A2

PU3

V

B+

B2

B+

AC
M

O

BATT
MO

PCH_PWR_EN#

2

V

PQ2

EC

VV

A5

ON

A4

/OFF

B7

B6

V

V

PBTN_OUT#

PM_SLP_S3#
PM_SLP_S4#
PM_SLP_S5#
PM_SLP_A#
PM_SLP_SUS#

V

SYSON

DGPU_PWR_EN

SUSP#,SUSP

B3

51ON#

C C

EC_ON

2

4

PCH_RSMRST#

5

7 SYSON#

(D

8a

8

6

IS)

1

4,+3VALW_PCH

U

V

QH4,+5VALW_PCH

+3VALW_PCH

3

+5VALW_PCH

V

PCH

V V

+1.5V
PU5

V

VGA_ON

U49

V

+5VS

V

SYS_PWROK

PM

_DRAM_PWRGD

H_CPUPWRGD

PLT_RST#

+3VSDGPU

V

Q6

+1.5VSDGPU

V

13

V

14

C

PU

V

15

V

VVVV

11

VGATE

U40

U20

V

+3VS

+1.8VSDGPU

V

VGA

V

U37

B B

U13

V

+1.5VS

+1.0VSDGPU

V

PU28

PU8

VV

VCCPPWRGOOD

V

PU9
+1.05VS_VCCP

VR_ON

9

PU1000
+CPU_CORE

V

+0.75V

PU7
+VCCSA

+VGA_CORE

V

PU998

VGA_PWROK

(D

IS)

8b

U47
CK505

V

10

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

3

2011/11/01

2011/11/01

2011/11/01

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2012/12/31

2012/12/31

2012/12/31

Title

Power sequence

Power sequence

Power sequence

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Monday, January 14, 2013

Monday, January 14, 2013

Monday, January 14, 2013

Y400S-NM-A141

Y400S-NM-A141

Y400S-NM-A141

1

of

of

of

63 65

63 65

63 65

1.0

1.0

1.0

5

4

3

2

Version change list (P.I.R. List) Page 1 of 1

for PWR

Reason for change PG# Modify List Date PhaseItem

1

1

D D

2

For NV suggest

For TI suggest

58 Add (reserve parts ) PC859

Add (reserve parts ) PR834

58

3

4

5

6

7

8

C C

9

10

11

12

13

14

B B

15

16

17

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.

3

2012/10/11

2012/10/11

2012/10/11

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2014/07/01

2014/07/01

2014/07/01

2

Title

PIR (PWR)

PIR (PWR)

PIR (PWR)

Size D ocument Number Rev

Size D ocument Number Rev

Size D ocument Number Rev

Custom

Custom

Custom

Monday, January 14, 2013

Monday, January 14, 2013

Date: Sheet

Date: Sheet

Date: Sheet

Monday, January 14, 2013

NM-A141

NM-A141

NM-A141

NM-A141

NM-A141

NM-A141

NM-A141NM-A141

NM-A141NM-A141

NM-A141NM-A141

1

of

of

of

64 65

64 65

64 65

1.0

1.0

1.0

5

4

3

2

1

QIWY5 HW PIR List

NO DATE PAGE MODIFICATION LIST PURPOSE

P23

1

P23

2

D D

3

Change DGPU_PWR_EN to PLT_RST_VGA#

Add CV148

For GC6 function
For GC6 function

4
5
6
7
8
9
10
11
12
13
14
14
15
16

C C

EVT TO DVT

B B

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.

3

2012/10/11

2012/10/11

2012/10/11

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2014/07/01

2014/07/01

2014/07/01

2

Title

PIR (HW)

PIR (HW)

PIR (HW)

Size D ocument Number Rev

Size D ocument Number Rev

Size D ocument Number Rev

Custom

Custom

Custom

Monday, January 14, 2013

Monday, January 14, 2013

Date: Sheet

Date: Sheet

Date: Sheet

Monday, January 14, 2013

NM-A142

NM-A142

NM-A142

NM-A142

NM-A142

NM-A142

NM-A142NM-A142

NM-A142NM-A142

NM-A142NM-A142

1

of

of

of

65 65

65 65

65 65

1.0

1.0

1.0