Compal NM-A032 VIQY1 Schematic
A
1 1
B
C
D
E
VIQY1
(Y510)
2 2
NM_A032 Rev1.0 Schematic
Intel Haswell Processor with DDRIII + Lynx point PCH
3 3
4 4
A
nVIDIA N14P GT + 2nd VGA N14P GT
2013-03-19 Rev1.0
Security Class ification
Security Class ification
Security Class ification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
B
2012/07/ 01
2012/07/ 01
2012/07/ 01
C
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2014/07/ 01
2014/07/ 01
2014/07/ 01
D
Title
Title
Title
Cover Page
Cover Page
Cover Page
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
Custom
Custom
Custom
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Date: Sheet of
Date: Sheet of
Date: Sheet of
Wednesday, March 27, 2013
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032Y510 NM-A032
Y510 NM-A032Y510 NM-A032
Y510 NM-A032Y510 NM-A032
E
1 69
1 69
1 69
1.0
1.0
1.0
A
B
C
D
E
PCI-Express 16X Gen3
Intel CPU
P
G 0~7PEG 8~15
E
2
d VGA, N14P-GT1
1 1
n
V
AM 64*32
R
GDDR5* 8
Sub/B
HDMI Conn. CRT Conn.
HDMI1.4b
2 2
3 3
Page 39 Page 36
Page 32 Page 23,24,25,26,27,28,29,30,31,33
MUX
Page 37
LVDS Conn.
HDMI
Page 35
RJ45 Conn.
Page 42
Card reader
Conn.
Page 48
LVDS
N
4P-GT1
1
VRAM 64*32
GDDR5* 8
MUX
Page 37
eDP to LVDS
PS8625
Page 34
Atheros
QCA8171-BL3A-R
PCIe port 3
SPI ROM
(4MB+2MB)
SATA HDD
SATA ODD
Card reader IC
GL3213
CRT
MUX
Page 38
Page 41
Page 17
SATA Port 5
page 44
SATA Port 2
page 44
Page 48
eDP
eDP
PCIe Gen1
1.5V 5GT/s
SPI BUS
3.3V 33MHz
SATA Gen3 Port 5
3V 6GHz(600MB/s)
SATA Gen1 Port2
3V 3GHz(300MB/s)
USB 3.0 Port6
5V 5GT/s
USB 2.0 Port4
5V 480MHz
FDI *2
2.7GT/s
Haswell
rPGA946
37.5mm*37.5mm
Page 5,6,7,8,9,10
DMI *4
5GT/s
Intel PCH
Lynx point
FCBGA 695Balls
20mm*20mm
Page 13,14,15,16,17,18,19,20,21,22
LPC BUS
3.3V 33MHz
1
35V DDRIIIL 1066/1333/1600 MT/s
.
USB 2.0 Port1
5V 480MHz
USB 2.0
5V 480MHz
USB 3.0
5V 5GT/s
USB 2.0
5V 480MHz
PCIe Gen1
5V 480MHz
SATA Gen3
5V 6GHz(600MB/s)
HD Audio
3.3V 24MHz
M
mory BUS (DDRIII)
e
Dual Channel
USB Charger IC
GL887T
USB Left
USB 2.0 Port 2
USB 3.0 Port 2
Int. Camera
USB 2.0 Port 0
PCIeMini Card
WLAN
PCIeMini Card
WLAN
Page 50
Page 49
Page 35
PCIe Port 4
page 40
USB Port 10
page 40
DDR3-SO-DIMM X2
B
ANK 0, 1, 2, 3
P TO 16G
U
Page 11,12
USB Charger
Conn.
Sub/B
USB Left
USB 2.0 Port 3
USB 3.0 Port 5
Touch panel
USB 2.0 Port 8
NGFF SSD
Page 50
Page 49
Page 50
SATA Port 4
page 40
Debug Port
Page 40
Power Circuit DC/DC
Page 56,57 ,58,59,60, 61,
62,63 ,64,65,66
4 4
DC/DC Interface CKT.
POWER/B Conn. AUDIO, USB/B Conn.
ODD/B Conn.
Page 55
Page 52 Page 50
page 44
A
RTC CKT.
NOVO/B Conn.
Page 56
Page 52
Touch Pad
B
EC
ITE IT8586E-FX
Page 46
Int.KBD
Page 47
Security Classification
Security Classification
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
Issued Date
Issued Date
Issued Date
Page 47
C
Thermal Sensor
EMC 1403
2012/07/01
2012/07/01
2012/07/01
Page 43
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Codec
ALC282CG
Int. MIC Conn.
(JCMOS Conn.)
Page 35 Page 50
2014/07/01
2014/07/01
2014/07/01
D
Page 45
SPK Conn.
Page 45
Ext. MIC Conn.
Sub/B
Title
Title
Title
Block Diagram
Block Diagram
Block Diagram
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Date: Sheet of
Date: Sheet of
Date: Sheet of
Wednesday, March 27, 2013
HP Conn.
Sub/B
Page 50
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
E
2 69
2 69
2 69
1.0
1.0
1.0
A
B
C
D
E
Voltage Rails
( O --> Means ON ,
Power Plane
1 1
B+
S
tate
S0
S3
2 2
S5 S4/AC Only
S5 S4
Battery only
O
O
O
O
S5 S4
AC & Battery
X X
don't exist
SMBUS Control Table
SOURCE
3 3
IT
8580EEC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
C_SMB_DA2
E
SMB_CLK_S3
SMB_DATA_S3
+3VALW
IT8580E
+3VS
PCH
+3VS
Main
V
GA
X
V
+3VS +3VS
X X
X --> Means OFF )
+5VS
+3VS
+1.5VS
+VCCSA
+V1.5S_VCC P
+3VALW
+1.5V
+5VALW
+CPU_CORE
+VGA_CORE
GFX_CORE
+
+1.8VS
+1.05VS
+0.75VS
+3.3VS_VGA
+1.5VS_VGA
+1.05VS_VG A
O O O
OO
O
X
X X
X
2nd
VGA
BATT SODIMM
IT8580E
X X
+3VALW
V
X
X
X X X
X
X
V V
+3VS
WLAN
WiMAX
X
X
V
X
X
X
X
Thermal
Sensor
V
+3VS
PCH
XV
V
+3V_PCH
+3V_PCH+3VS
IGNAL
STATE
Full ON
S1(Power On Suspend)
S3 (Suspend to RAM)
S4 (Suspend to Disk)
S5 (Soft OFF)
S
USB Port Table
USB 3.0USB 2.0 Port
XHCI
EHCI1
2
5
6
EHCI2
TP
M
odule
XX
X
V
+3VS
SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
ON
HIGH HIGH HIGH HIGH
LOW
LOW
LOW
LOW LOW LOW LOW
HIGH
LOWLOWLOW
HIGHHIGHHIGH
HIGH
HIGH
ON
ON
ON
ON
ON
ON
OFF
ON
OFF
BOM Structure Table
4 External
USB Port
0
1
USB Port (Right Side)
2
3
USB Port (Left Side)
USB Port (Left Side)
4
5
6
7
8
9
10
Mini Card(WLAN)
11
12
13
PCIE PORT LIST
Port Device
1
2
3
4
5
6
7
8
LAN
WLAN
Camera
Card Reader
Touch panel
GT@
GT1@
CMOS@
SURGE@
X76@
GC6@
NOGC6@
AOAC@
KBL@
ME@
@
DS3@
daul@
887T@
887@
TI@
EDP@
SLI@
47W@
37W@
ON ON
ON
OFF
OFF
OFF
LOW
OFF
OFF
OFF
BTO ItemBOM Structure
NV GT750M
NV GT755M
CMOS Camera part
QCA8171 LAN surge part
X76 Level part for VRAM
NV CG6 support part
NV no CG6 support part
AOAC support part
K/B Light part
ME part
Unpop
Deep S3 support part
Support daul channel panel function
GENESYS 887T USB charger solution
GENESYS 887 USB charger solution
TI USB charger solution
Support EDP panel function
For SLI function part
For 47W CPU part
For 37W CPU part
A
Address
0001 011X b
EC SM Bus2 address
Device
Thermal Sen sor EMC1403-2
Master VGA
Slave VGA
B
Address
1001_101xb
0x9E
0x9C
PCH SM Bus address
Device Address
DDR DIMM0
DDR DIMM2
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
C
1001 000Xb
1001 010Xb
2012/07/01
2012/07/01
2012/07/01
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2014/07/01
2014/07/01
2014/07/01
D
4 4
EC SM Bus1 address
Device
Smart Battery
ZZZ1
ZZZ1
DAZ0SF00100
DAZ0SF00100
Title
Title
Title
Notes List
Notes List
Notes List
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Date: Sheet of
Date: Sheet of
Date: Sheet of
Wednesday, March 27, 2013
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
E
3 69
3 69
3 69
1.0
1.0
1.0
5
4
3
2
1
Hot plug detect for IFP link E
VGA and GDDR5 Voltage Rails (N14Px GPIO)
GPIO I/O ACTIVE Function Description
GPIO0
D D
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
C C
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
B B
IN FB_CLAMP_MON-
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
IN
OUT
IN
IN
IN
+3VS_VGA
+VGA_CORE
+1.5VS_VGA
+1.05VS_VGA
-
NAOUT
VGA_BL_PWM
-
-
VGA_ENVDD
- VGA_ENBKL
NA
-
FB_CLAMP_TOGGLE_REQ#
-
NA
-
OVERT#
-
VGA_ALERT#
-
Memory VREF Control
-
NVVDD PWM_VID-OUT
-
AC Power Detect Input
DPRSLPVR_VGA -
NA
-
-
NA
-
NA
-
VGA_EDP_HPD
-
DGPU_HDMI_HPD
NA
-
tNVVDD >0
tFBVDDQ >0
tPEX_VDD >0
1. all power r ail ramp up ti me should be la rger than 40us
(10K pull High)
Performance Mode P0 TDP at Tj = 102 C* (GDDR5)
GPU Mem NVCLK
(4) (1,5) (6)
Products
(W) (W) (MHz)
N14X
128bit
1GB
GDDR5
Physical
Strapping pin
ROM_SCLK
ROM_SI
ROM_SO FB[0]
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
N13P-GT
(28nm)
/MCLK NVVDD
(V) (A) (W) (A) (W)
TBD TBDTBD TBD TBD TBD TBD TBD T BD TBD TBD TBD TBD TBD TBD TBD TBD TBD
Power Rail
+3VS_VGA
+3VS_VGA
+
3VS_VGA
+3VS_VGA
+3VS_VGA
+3VS_VGA
+3VS_VGA
+3VS_VGA
Device ID
0x0FCD
Logical
Strapping Bit3
PCI_DEVID[4]
FB[1]
PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0]
SOR3_EXPOSED
RESERVED PCIE_SPEED_
3GIO_PAD_CFG_ADR [2] 3GIO_PAD_CFG_ADR [1]3GIO_PAD_CFG_ADR [3]
setting
SMB_ALT_ADDR
(ROM_SO Bit 1)
0
1
ROM_SO ROM_SCLK
GPU
N14P-GT
28nm
PU 10K PD 25K
FB Memory (GDDR5)
Samsung
3000MHz
Hynix
3000MHz
Samsung
2500MHz
2500MHz
PD 15K
PU 45K
PU 25K PD 35KPU 45KPU 20K PD 10K PD 5K PD 10K
GPU
K4G20325FD-FC03
64Mx32
H5GQ2H24AFR-R0C
64Mx32 PD 25K
K4G20325FD-FC04
64Mx32
H5GQ2H24AFR-T2CHynix
64Mx32
PD 5K
N14P-GT
ROM_SI
PD 30K
PD 25K
FBVDDQ PCI Express I/O and
FBVDD
(GPU+Mem)
(1.35V)(1.35V)
(A) (W) (W)(mA) (W) (W) (W)(mA) (mA) (mA)
Logical
Strapping Bit2
SUB_VENDOR
SER[2] USER[1] USER[0]USER[3]
U
SOR2_EXPOSED SOR1_EXPOSED
CHANGE_GEN3
I2C Slave addrees ID
0x9E
0x9C
STRAP2STRAP1STRAP0
N14P-GT1
ROM_SI
PD 30K
(1.05V)
Logical
Strapping Bit1
SLOT_CLK_CFG
RAM_CFG[1]RAM_CFG[3] RAM_CFG [2]
PCIE_MAX_SPEED DP_PLL _VDD33V
STRAP3
STRAP4
PU 5K PD 45K
PLLVDD
Master
Slave
I/O and
PLLVDD
Logical
Strapping Bit0
PEX_PLL_EN_TERM
R
AM_CFG[0]
VGA_DEVICESMB_ALT_ADDR
3GIO_PAD_CFG_ADR [0]
SOR0_EXPOSED
Other
(3.3V)(1.05V)(1.8V)
Other Power rail
A A
+3VS_VGA
power-off <10m s
T
1.all GPU powe r rails should be turned off within 10ms
. Optimus syst em VDD33 avoid s drop down ear lier than NVDD and FBVDDQ
2
5
Title
Title
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
4
3
2012/07/01
2012/07/01
2012/07/01
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2014/07/01
2014/07/01
2014/07/01
Title
VGA Notes List
VGA Notes List
VGA Notes List
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Date: Sheet of
Date: Sheet of
Date: Sheet of
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
1
4 69
4 69
4 69
1.0
1.0
1.0
5
4
3
2
1
D D
Haswell rPGA EDS
Haswell rPGA EDS
D21
C21
B21
A21
D20
C20
B20
A20
D18
C17
B17
A17
D17
C18
B18
A18
H29
J29
DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3
DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3
DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3
DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3
FDI_CSYNC
FDI_INT
IN
IN
TEL_HASWELL_HAS WELL
TEL_HASWELL_HAS WELL
12
12
DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
FDI_CSYNC_R
FDI_INT_R
DMI_CRX_PTX_N0<15>
DMI_CRX_PTX_N1<15>
DMI_CRX_PTX_N2<15>
DMI_CRX_PTX_N3<15>
DMI_CRX_PTX_P0<15>
DMI_CRX_PTX_P1<15>
DMI_CRX_PTX_P2<15>
DMI_CRX_PTX_P3<15>
DMI_CTX_PRX_N0<15>
C C
FDI_CSYNC<15>
FDI_INT<15>
B B
DMI_CTX_PRX_N1<15>
DMI_CTX_PRX_N2<15>
DMI_CTX_PRX_N3<15>
DMI_CTX_PRX_P0<15>
DMI_CTX_PRX_P1<15>
DMI_CTX_PRX_P2<15>
DMI_CTX_PRX_P3<15>
RC3 0_0402_5%RC3 0_0402_5%
RC87 0_0402_5%RC87 0_0402_5%
JCPUA
JCPUA
PEG_RCOMP
PEG
PEG
DMI FDI
DMI FDI
PEG_RXN_10
PEG_RXN_11
PEG_RXN_12
PEG_RXN_13
PEG_RXN_14
PEG_RXN_15
PEG_RXP_10
PEG_RXP_11
PEG_RXP_12
PEG_RXP_13
PEG_RXP_14
PEG_RXP_15
PEG_TXN_10
PEG_TXN_11
PEG_TXN_12
PEG_TXN_13
PEG_TXN_14
PEG_TXN_15
PEG_TXP_10
PEG_TXP_11
PEG_TXP_12
PEG_TXP_13
PEG_TXP_14
PEG_TXP_15
1 OF 9
1 OF 9
PEG_RXN_0
PEG_RXN_1
PEG_RXN_2
PEG_RXN_3
PEG_RXN_4
PEG_RXN_5
PEG_RXN_6
PEG_RXN_7
PEG_RXN_8
PEG_RXN_9
PEG_RXP_0
PEG_RXP_1
PEG_RXP_2
PEG_RXP_3
PEG_RXP_4
PEG_RXP_5
PEG_RXP_6
PEG_RXP_7
PEG_RXP_8
PEG_RXP_9
PEG_TXN_0
PEG_TXN_1
PEG_TXN_2
PEG_TXN_3
PEG_TXN_4
PEG_TXN_5
PEG_TXN_6
PEG_TXN_7
PEG_TXN_8
PEG_TXN_9
PEG_TXP_0
PEG_TXP_1
PEG_TXP_2
PEG_TXP_3
PEG_TXP_4
PEG_TXP_5
PEG_TXP_6
PEG_TXP_7
PEG_TXP_8
PEG_TXP_9
E23
PEG_COMP
M29
PCIE_CRX_GTX_N0
K28
PCIE_CRX_GTX_N1
M31
PCIE_CRX_GTX_N2
L30
PCIE_CRX_GTX_N3
M33
PCIE_CRX_GTX_N4
L32
PCIE_CRX_GTX_N5
M35
PCIE_CRX_GTX_N6
L34
PCIE_CRX_GTX_N7
E29
PCIE_CRX_GTX_N8
D28
PCIE_CRX_GTX_N9
E31
PCIE_CRX_GTX_N10
D30
PCIE_CRX_GTX_N11
E35
PCIE_CRX_GTX_N12
D34
PCIE_CRX_GTX_N13
E33
PCIE_CRX_GTX_N14
E32
PCIE_CRX_GTX_N15
L29
PCIE_CRX_GTX_P0
L28
PCIE_CRX_GTX_P1
L31
PCIE_CRX_GTX_P2
K30
PCIE_CRX_GTX_P3
L33
PCIE_CRX_GTX_P4
K32
PCIE_CRX_GTX_P5
L35
PCIE_CRX_GTX_P6
K34
PCIE_CRX_GTX_P7
F29
PCIE_CRX_GTX_P8
E28
PCIE_CRX_GTX_P9
F31
PCIE_CRX_GTX_P10
E30
PCIE_CRX_GTX_P11
F35
PCIE_CRX_GTX_P12
E34
PCIE_CRX_GTX_P13
F33
PCIE_CRX_GTX_P14
D32
PCIE_CRX_GTX_P15
H35
PCIE_CTX_GRX_N0
H34
PCIE_CTX_GRX_N1
J33
PCIE_CTX_GRX_N2
H32
PCIE_CTX_GRX_N3
J31
PCIE_CTX_GRX_N4
G30
PCIE_CTX_GRX_N5
C33
PCIE_CTX_GRX_N6
B32
PCIE_CTX_GRX_N7
B31
PCIE_CTX_GRX_N8
A30
PCIE_CTX_GRX_N9
B29
PCIE_CTX_GRX_N10
A28
PCIE_CTX_GRX_N11
B27
PCIE_CTX_GRX_N12
A26
PCIE_CTX_GRX_N13
B25
PCIE_CTX_GRX_N14
A24
PCIE_CTX_GRX_N15
J35
PCIE_CTX_GRX_P0
G34
PCIE_CTX_GRX_P1
H33
PCIE_CTX_GRX_P2
G32
PCIE_CTX_GRX_P3
H31
PCIE_CTX_GRX_P4
H30
PCIE_CTX_GRX_P5
B33
PCIE_CTX_GRX_P6
A32
PCIE_CTX_GRX_P7
C31
PCIE_CTX_GRX_P8
B30
PCIE_CTX_GRX_P9
C29
PCIE_CTX_GRX_P10
B28
PCIE_CTX_GRX_P11
C27
PCIE_CTX_GRX_P12
B26
PCIE_CTX_GRX_P13
C25
PCIE_CTX_GRX_P14
B24
PCIE_CTX_GRX_P15
PEG_COMP
CAD Note:
Trace width=12 mils ,Spacing=15mil
Max length= 400 mils.
PCIE_CRX_GTX_N[0..15] <23,32>
PCIE_CRX_GTX_P[0..15] <23,32>
CC1 0.22U_0402_10V6KCC1 0.22U_0402_10V6K
CC2 0.22U_0402_10V6KCC2 0.22U_0402_10V6K
CC3 0.22U_0402_10V6KCC3 0.22U_0402_10V6K
CC4 0.22U_0402_10V6KCC4 0.22U_0402_10V6K
CC5 0.22U_0402_10V6KCC5 0.22U_0402_10V6K
CC6 0.22U_0402_10V6KCC6 0.22U_0402_10V6K
CC7 0.22U_0402_10V6KCC7 0.22U_0402_10V6K
CC8 0.22U_0402_10V6KCC8 0.22U_0402_10V6K
CC9 0.22U_0402_10V6KCC9 0.22U_0402_10V6K
CC10 0.22U_ 0402_10V6KCC10 0.22U_0402_10V6 K
CC11 0.22U_ 0402_10V6KCC11 0.22U_0402_10V6 K
CC12 0.22U_ 0402_10V6KCC12 0.22U_0402_10V6 K
CC13 0.22U_ 0402_10V6KCC13 0.22U_0402_10V6 K
CC14 0.22U_ 0402_10V6KCC14 0.22U_0402_10V6 K
CC15 0.22U_ 0402_10V6KCC15 0.22U_0402_10V6 K
CC16 0.22U_ 0402_10V6KCC16 0.22U_0402_10V6 K
CC20 0.22U_ 0402_10V6KCC20 0.22U_0402_10V6 K
CC23 0.22U_ 0402_10V6KCC23 0.22U_0402_10V6 K
CC25 0.22U_ 0402_10V6KCC25 0.22U_0402_10V6 K
CC30 0.22U_ 0402_10V6KCC30 0.22U_0402_10V6 K
CC18 0.22U_ 0402_10V6KCC18 0.22U_0402_10V6 K
CC22 0.22U_ 0402_10V6KCC22 0.22U_0402_10V6 K
CC28 0.22U_ 0402_10V6KCC28 0.22U_0402_10V6 K
CC32 0.22U_ 0402_10V6KCC32 0.22U_0402_10V6 K
CC19 0.22U_ 0402_10V6KCC19 0.22U_0402_10V6 K
CC24 0.22U_ 0402_10V6KCC24 0.22U_0402_10V6 K
CC29 0.22U_ 0402_10V6KCC29 0.22U_0402_10V6 K
CC17 0.22U_ 0402_10V6KCC17 0.22U_0402_10V6 K
CC21 0.22U_ 0402_10V6KCC21 0.22U_0402_10V6 K
CC27 0.22U_ 0402_10V6KCC27 0.22U_0402_10V6 K
CC26 0.22U_ 0402_10V6KCC26 0.22U_0402_10V6 K
CC31 0.22U_ 0402_10V6KCC31 0.22U_0402_10V6 K
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
+VCCIOA_OUT
12
RC224.9_0402_1% RC224.9_0402_1%
PEG Static Lane Reversal - CFG2 is for the 16x
CFG2
PCIE_CTX_C_GRX_N0
PCIE_CTX_C_GRX_N1
PCIE_CTX_C_GRX_N2
PCIE_CTX_C_GRX_N3
PCIE_CTX_C_GRX_N4
PCIE_CTX_C_GRX_N5
PCIE_CTX_C_GRX_N6
PCIE_CTX_C_GRX_N7
PCIE_CTX_C_GRX_N8
PCIE_CTX_C_GRX_N9
PCIE_CTX_C_GRX_N10
PCIE_CTX_C_GRX_N11
PCIE_CTX_C_GRX_N12
PCIE_CTX_C_GRX_N13
PCIE_CTX_C_GRX_N14
PCIE_CTX_C_GRX_N15
PCIE_CTX_C_GRX_P0
PCIE_CTX_C_GRX_P1
PCIE_CTX_C_GRX_P2
PCIE_CTX_C_GRX_P3
PCIE_CTX_C_GRX_P4
PCIE_CTX_C_GRX_P5
PCIE_CTX_C_GRX_P6
PCIE_CTX_C_GRX_P7
PCIE_CTX_C_GRX_P8
PCIE_CTX_C_GRX_P9
PCIE_CTX_C_GRX_P10
PCIE_CTX_C_GRX_P11
PCIE_CTX_C_GRX_P12
PCIE_CTX_C_GRX_P13
PCIE_CTX_C_GRX_P14
PCIE_CTX_C_GRX_P15
1: Normal Operation; Lane # definition matches
socket pin map definition
:Lane Reversed
0
*
PCIE_CTX_C_GRX_N[0..15] <23,32>
PCIE_CTX_C_GRX_P[0..15] <23,32>
A A
Title
Title
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
3
2012/07/01
2012/07/01
2012/07/01
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2014/07/01
2014/07/01
2014/07/01
Title
CPU (1/7) DMI, FDI, PEG
CPU (1/7) DMI, FDI, PEG
CPU (1/7) DMI, FDI, PEG
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Wednesday, March 20, 2013
Wednesday, March 20, 2013
Date: Sheet of
Date: Sheet of
Date: Sheet of
Wednesday, March 20, 2013
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
1
5 69
5 69
5 69
0.1
0.1
0.1
5
4
3
2
1
+1.35V
RC60
RC60
1 2
0_0402_5%
0_0402_5%
D
S
D
S
H_DRAMRST#
RC1544
D D
DRAMRST_CNTRL_PC H<17>
DRAMRST_CNTRL<7>
DRAMRST_CNTRL_EC<46>
RC42 0_0402_5%
RC42 0_0402_5%
Reserve for Deep S3
RC1544
4.99K_0402_1% @
4.99K_0402_1% @
1 2
@
@
RC1545
RC1545
1 2
R_short 0_0402_5%
R_short 0_0402_5%
1 2
DRAMRST_CNTRL
@
@
G
G
2
1
2
13
DDR3_DRAMRST#_R
QC3
QC3
BSS138_NL_SOT23-3
BSS138_NL_SOT23-3
CC50
CC50
0.047U_0402_16V4Z@
0.047U_0402_16V4Z@
RC62
1K_0402_5%
1K_0402_5%
12
@RC62
@
RC1543
RC1543
1 2
0_0402_5%
0_0402_5%
DDR3_DRAMRST# <11,12>
RC5 need to close to JCPU1
H_CPUPWRGD H_CPUP WRGD_XDP
SIO_PWRBTN#_R<15>
CPU_PWR_DEBU G<9>
+1.05VS
1 2
RC5 1K_0402_1%RC5 1K_0402_1%
1 2
RC6 0_0402_5%@RC6 0_0402_5%@
VGATE<15,64>
CLK_CPU_ITP<16>
CLK_CPU_ITP#<16>
1 2
PU/PD for JTAG signals
C C
XDP_DBRESET#_R
XDP_TMS
XDP_TDI
XDP_PREQ#
XDP_TDO
XDP_TCLK
XDP_TRST#
B B
PM_DRAM_PWR GD<15>
A A
RC19 1K_040 2_1%RC19 1K_0402_1%
RC27 51_0402_1 %@RC 27 51_0402_1%@
RC29 51_0402_1 %@RC 29 51_0402_1%@
RC32 51_0402_1 %@RC 32 51_0402_1%@
RC35 51_0402_1 %@RC 35 51_0402_1%@
RC40 51_0402_1 %RC40 51_0402_1%
RC41 51_0402_1 %RC41 51_0402_1%
SM_DRAMPWROK with DDR Power Gating Topology
SYS_PWROK<15>
12
12
12
12
12
12
12
RC88 0_0402_5%
RC88 0_0402_5%
+3VS
+1.05VS
H_PECI<46>
1 2
H_PROCHOT#<46,57>
H_PM_SYNC<15>
H_CPUPWRGD<19>
CLK_CPU_DPLL#<16>
CLK_CPU_DPLL<16>
CLK_CPU_SSC_DPLL#<16>
CLK_CPU_SSC_DPLL<16>
+3V_PCH
200_0402_5%
200_0402_5%
12
RC89
RC89
RC1547 0_ 0402_5%@RC1547 0_ 0402_5%@
RUN_ON_CPU1.5VS3#<10>
+3V_PCH
12
RC84
RC84
1
2
CC156
CC156
1 2
0.1U_0402_25V6K
0.1U_0402_25V6K
5
P
B
4
O
A
G
UC4
UC4
74AHC1G09GW_TSSOP5
74AHC1G09GW_TSSOP5
3
12
100K_0402_5%
100K_0402_5%
@
@
12
RC57 56_0402_5%RC57 56_0402_5%
RC25
RC25
R_short 0_0402_5%
R_short 0_0402_5%
RC51 0_0402_5%RC51 0_0402_5%
RC52 0_0402_5%RC52 0_0402_5%
RC43 0_0402_5%RC43 0_0402_5%
RC22 0_0402_5%RC22 0_0402_5%
@
@
2
G
G
H_THRMTRIP#<19>
1 2
12
12
12
12
CLK_CPU_DMI#<16>
CLK_CPU_DMI<16>
497750_497750_SH RKBY_MBL_SCH_CH KLST 0.5
page19 item 3.6 SM_DRAMPWROK
+1.35V_CPU_VDDQ
1.8K_0402_1%
1.8K_0402_1%
12
RC16
RC16
RC28 0_0402_5%RC28 0_0402_5%
3.3K_0402_1%
3.3K_0402_1%
39_0402_5%
39_0402_5%
12
RC14
RC14
@RC64
@
RC64
SSM3K7002FU_SC70-3
SSM3K7002FU_SC70-3
1 2
13
D
D
@
@
QC1
QC1
S
S
H_CATERR#
H_PECI
T55PAD @T55PAD @
H_PROCHOT#_R
H_THRMTRIP#
H_PM_SYNC
VCCPWRGOOD_0_R
PM_DRAM_PWR GD_CPU
BUF_CPU_RST#
CPU_DPLL#
CPU_DPLL
CPU_SSC_DPLL#
CPU_SSC_DPLL
CLK_CPU_DMI#
CLK_CPU_DMI
12
PM_DRAM_PWR GD_CPURUNPWROK_AND
AP32
SKTOCC
AN32
CATERR
AR27
PECI
AK31
RSVD
AM30
PROCHOT
AM35
THERMTRIP
AT28
PM_SYNC
AL34
PWRGOOD
AC10
SM_DRAMPWR OK
AT26
PLTRSTIN
G28
DPLL_REF_CLKN
H28
DPLL_REF_CLKP
F27
SSC_DPLL_REF_CLKN
E27
SSC_DPLL_REF_CLKP
D26
BCLKN
E26
BCLKP
Haswell rPGA EDS
Haswell rPGA EDS
INTEL_HASWELL_HAS WELL
INTEL_HASWELL_HAS WELL
JCPUB
JCPUB
MISC
MISC
THERMAL
THERMAL
PWR
PWR
CPU_PLTRST#<19>
AP3
SM_RCOMP0
AR3
SM_RCOMP1
AP2
SM_RCOMP2
AN3
H_DRAMRST#
AR29
XDP_PRDY#
AT29
XDP_PREQ#
AM34
XDP_TCLK
AN33
XDP_TMS
AM33
XDP_TRST#
AM31
XDP_TDI XDP_TDI_R
TDI
AL33
XDP_TDO XDP_TDO_R
AP33
AR30
XDP_OBS0_R
AN31
XDP_OBS1_R
AN29
XDP_OBS2_R
AP31
XDP_OBS3_R
AP30
XDP_OBS4_R
AN28
XDP_OBS5_R
AP29
XDP_OBS6_R
AP28
XDP_OBS7_R
DDR3
DDR3
CLOCK
CLOCK
SM_RCOMP_0
SM_RCOMP_1
SM_RCOMP_2
SM_DRAMRST
PRDY
PREQ
JTAG
JTAG
BPM_N_0
BPM_N_1
BPM_N_2
BPM_N_3
BPM_N_4
BPM_N_5
BPM_N_6
BPM_N_7
2 OF 9
2 OF 9
TCK
TMS
TRST
TDO
DBR
For ESD
Buffered Reset to CPU
+VCCIO_OUT
.05V
1
1 2
0_0402_5%
0_0402_5%
RC46
RC46
XDP Connector
XDP_PREQ#_R
XDP_PRDY#_R
XDP_OBS0
XDP_OBS1
XDP_OBS2
XDP_OBS3
CFD_PWRBTN#_X DP
CPU_PWR_DEBU G
VGATE
CLK_CPU_ITP
CLK_CPU_ITP#
XDP_RST#_RBUF_CPU_RST#
XDP_DBRESET#
RC81K_0402_1% RC81K_0402_1%
XDP_TDO_R
XDP_TRST#_R
XDP_TDI_R
XDP_TMS_R
XDP_TCK_R
20120806 VA
change XDP connector to 28 pin
1 2
RC47 0_0402_5%RC 47 0_0402_5%
1 2
RC48 0_0402_5%RC 48 0_0402_5%
1 2
RC50 0_0402_5%RC 50 0_0402_5%
1 2
RC53 0_0402_5%RC 53 0_0402_5%
1 2
RC54 0_0402_5%RC 54 0_0402_5%
1 2
RC23 0_0402_5%RC23 0_0402_5%
1 2
RC24 0_0402_5%RC24 0_0402_5%
RC26 0_0402_5%RC26 0_0402_5%
1 2
RC30 0_0402_5%RC30 0_0402_5%
1 2
RC31 0_0402_5%RC31 0_0402_5%
1 2
RC33 0_0402_5%RC33 0_0402_5%
1 2
RC34 0_0402_5%RC34 0_0402_5%
1 2
RC36 0_0402_5%RC36 0_0402_5%
1 2
RC37 0_0402_5%RC37 0_0402_5%
1 2
RC38 0_0402_5%RC38 0_0402_5%
1 2
RC39 0_0402_5%RC39 0_0402_5%
VCCPWRGOOD_0_RBUF_CPU_RST#
1
@
@
CC61
CC61
220P_0402_25V8J
220P_0402_25V8J
2
+1.05VS
BUF_CPU_RST#
RC126
RC128
RC44
RC44
1 2
@RC126
@
1 2
@RC128
@
1 2
12
@
@
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
MOLEX 52435-2671
MOLEX 52435-2671
XDP_PRDY#_R
XDP_PREQ#_R
XDP_TCK_R
XDP_TMS_R
XDP_TRST#_R
1
CC60
CC60
220P_0402_25V8J
220P_0402_25V8J
2
H_THRMTRIP#
100_0402_1%
100_0402_1%
H_CATERR#
49.9_0402_1%
49.9_0402_1%
H_PROCHOT#
62_0402_5%
62_0402_5%
JXDP
XDP_DBRESET#XDP_DBRESET#_R
XDP_OBS0
XDP_OBS1
XDP_OBS2
XDP_OBS3
@JXDP
@
Place near JXDP1
27
28
+1.05VS
@
@
0.1U_0402_25V6K
0.1U_0402_25V6K
0.1U_0402_25V6K
0.1U_0402_25V6K
1
1
CC65
CC65
CC66
CC66
@
@
2
2
DDR3 COMPENSATION SIGNALS
RC1539
RC1539
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
CAD Note:
Trace width=12~15 mil, Spcing=20 mils
Max trace length= 500 mil
For ESD concern, please put near CPU
CPU_SSC_DPLL
CPU_SSC_DPLL#
SSC CLOCK TERMINATION, IF NOT USED, stuff RC20,RC21
1 2
1 2
RC55 75_0402_1%RC 55 75_0402_1%
1 2
RC49 100_0402_ 1%RC49 100_0402_1%
VCCPWRGOOD_0_R
CAD Note:
Avoid stub in the PWRGD path
while placing resistors RC25 & RC130
1 2
1 2
10K_0402_5%
10K_0402_5%
12
+VCCIO_OUT
RC2010K_0402_5% @RC2010K_0402_5% @
RC2110K_0402_5% @RC2110K_0402_5% @
100_0402_1%
100_0402_1%
RC130
RC130
Title
Title
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
3
2012/07/01
2012/07/01
2012/07/01
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2014/07/01
2014/07/01
2014/07/01
Title
CPU (2/7) PM, XDP, CLK
CPU (2/7) PM, XDP, CLK
CPU (2/7) PM, XDP, CLK
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Date: Sheet of
Date: Sheet of
Date: Sheet of
Wednesday, March 27, 2013
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
1
6 69
6 69
6 69
1.0
1.0
1.0
5
DDRA_DQ[0..63]<11>
D D
C C
+VREF_CA_R
B B
+V_DDR_REFA_R
+V_DDR_REFB_R
DDRA_DQ0
DDRA_DQ1
DDRA_DQ2
DDRA_DQ3
DDRA_DQ4
DDRA_DQ5
DDRA_DQ6
DDRA_DQ7
DDRA_DQ8
DDRA_DQ9
DDRA_DQ10
DDRA_DQ11
DDRA_DQ12
DDRA_DQ13
DDRA_DQ14
DDRA_DQ15
DDRA_DQ16
DDRA_DQ17
DDRA_DQ18
DDRA_DQ19
DDRA_DQ20
DDRA_DQ21
DDRA_DQ22
DDRA_DQ23
DDRA_DQ24
DDRA_DQ25
DDRA_DQ26
DDRA_DQ27
DDRA_DQ28
DDRA_DQ29
DDRA_DQ30
DDRA_DQ31
DDRA_DQ32
DDRA_DQ33
DDRA_DQ34
DDRA_DQ35
DDRA_DQ36
DDRA_DQ37
DDRA_DQ38
DDRA_DQ39
DDRA_DQ40
DDRA_DQ41
DDRA_DQ42
DDRA_DQ43
DDRA_DQ44
DDRA_DQ45
DDRA_DQ46
DDRA_DQ47
DDRA_DQ48
DDRA_DQ49
DDRA_DQ50
DDRA_DQ51
DDRA_DQ52
DDRA_DQ53
DDRA_DQ54
DDRA_DQ55
DDRA_DQ56
DDRA_DQ57
DDRA_DQ58
DDRA_DQ59
DDRA_DQ60
DDRA_DQ61
DDRA_DQ62
DDRA_DQ63
AR15
AT14
AM14
AN14
AT15
AR14
AN15
AM15
AM9
AM8
AJ10
AK10
AM3
AN9
AN8
AR9
AT9
AR8
AT8
AK9
AK6
AK7
AF4
AF5
AF1
AF2
AG4
AG5
AG1
AG2
D12
D11
AJ9
AJ6
AJ7
J1
J2
J5
H5
H2
H1
J4
H4
F2
F1
D2
D3
D1
F3
C3
B3
B5
E6
A5
D6
D5
E5
B6
A6
E12
B11
A11
E11
B12
A12
F16
F13
SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63
SM_VREF
SA_DIMM_VREFDQ
SB_DIMM_VREFDQ
3 OF 9
3 OF 9
JCPUC
JCPUC
4
Haswell rPGA EDS
Haswell rPGA EDS
RSVD_AC7
SA_CK_N_0
SA_CK_P_0
SA_CKE_0
SA_CK_N_1
SA_CK_P_1
SA_CKE_1
SA_CK_N_2
SA_CK_P_2
SA_CKE_2
SA_CK_N_3
SA_CK_P_3
SA_CKE_3
SA_CS_N_0
SA_CS_N_1
SA_CS_N_2
SA_CS_N_3
SA_ODT_0
SA_ODT_1
SA_ODT_2
SA_ODT_3
SA_BS_0
SA_BS_1
SA_BS_2
RSVD_V10
SA_RAS
SA_WE
SA_CAS
SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14
SA_MA_15
SA_DQS_N_0
SA_DQS_N_1
SA_DQS_N_2
SA_DQS_N_3
SA_DQS_N_4
SA_DQS_N_5
SA_DQS_N_6
SA_DQS_N_7
SA_DQS_P_0
SA_DQS_P_1
SA_DQS_P_2
SA_DQS_P_3
SA_DQS_P_4
SA_DQS_P_5
SA_DQS_P_6
SA_DQS_P_7
TEL_HASWELL_HAS WELL
TEL_HASWELL_HAS WELL
IN
IN
AC7
U4
V4
AD9
U3
V3
AC9
U2
V2
AD8
U1
V1
AC8
M7
L9
M9
M10
M8
L7
L8
L10
V5
U5
AD1
V10
U6
U7
U8
V8
DDRA_MA0
AC6
DDRA_MA1
V9
DDRA_MA2
U9
DDRA_MA3
AC5
DDRA_MA4
AC4
DDRA_MA5
AD6
DDRA_MA6
AC3
DDRA_MA7
AD5
DDRA_MA8
AC2
DDRA_MA9
V6
DDRA_MA10
AC1
DDRA_MA11
AD4
DDRA_MA12
V7
DDRA_MA13
AD3
DDRA_MA14
AD2
DDRA_MA15
AP15
DDRA_DQS#0
AP8
DDRA_DQS#1
AJ8
DDRA_DQS#2
AF3
DDRA_DQS#3
J3
DDRA_DQS#4
E2
DDRA_DQS#5
C5
DDRA_DQS#6
C11
DDRA_DQS#7
AP14
DDRA_DQS0
AP9
DDRA_DQS1
AK8
DDRA_DQS2
AG3
DDRA_DQS3
H3
DDRA_DQS4
E3
DDRA_DQS5
C6
DDRA_DQS6
C12
DDRA_DQS7+VREF_CA_R
T64 PAD@T64 PAD@
DDRA_CLK0# <11>
DDRA_CLK0 <11>
DDRA_CKE0 <11>
DDRA_CLK1# <11>
DDRA_CLK1 <11>
DDRA_CKE1 <11>
DDRA_CS0# <11>
DDRA_CS1# <11>
DDRA_ODT0 <11>
DDRA_ODT1 <11>
DDRA_BS0# <11>
DDRA_BS1# <11>
DDRA_BS2# <11>
DDRA_RAS# <11>
DDRA_WE# <11>
DDRA_CAS# <11>
DDRA_MA[0..15] <11>
DDRA_DQS#[0..7] <11>
DDRA_DQS[0..7] <11>
3
DDRB_DQ[0..63]<12>
DDRB_DQ0
DDRB_DQ1
DDRB_DQ2
DDRB_DQ3
DDRB_DQ4
DDRB_DQ5
DDRB_DQ6
DDRB_DQ7
DDRB_DQ8
DDRB_DQ9
DDRB_DQ10
DDRB_DQ11
DDRB_DQ12
DDRB_DQ13
DDRB_DQ14
DDRB_DQ15
DDRB_DQ16
DDRB_DQ17
DDRB_DQ18
DDRB_DQ19
DDRB_DQ20
DDRB_DQ21
DDRB_DQ22
DDRB_DQ23
DDRB_DQ24
DDRB_DQ25
DDRB_DQ26
DDRB_DQ27
DDRB_DQ28
DDRB_DQ29
DDRB_DQ30
DDRB_DQ31
DDRB_DQ32
DDRB_DQ33
DDRB_DQ34
DDRB_DQ35
DDRB_DQ36
DDRB_DQ37
DDRB_DQ38
DDRB_DQ39
DDRB_DQ40
DDRB_DQ41
DDRB_DQ42
DDRB_DQ43
DDRB_DQ44
DDRB_DQ45
DDRB_DQ46
DDRB_DQ47
DDRB_DQ48
DDRB_DQ49
DDRB_DQ50
DDRB_DQ51
DDRB_DQ52
DDRB_DQ53
DDRB_DQ54
DDRB_DQ55
DDRB_DQ56
DDRB_DQ57
DDRB_DQ58
DDRB_DQ59
DDRB_DQ60
DDRB_DQ61
DDRB_DQ62
DDRB_DQ63
AR18
AT18
AM17
AM18
AR17
AT17
AN17
AN18
AT12
AR12
AN12
AM11
AT11
AR11
AM12
AN11
AR5
AR6
AM5
AM6
AT5
AT6
AN5
AN6
AK4
AM1
AN1
AK2
AK1
G10
D15
D14
AJ4
AJ1
AJ2
J10
E15
A15
B15
E14
A14
B14
L2
M2
L4
M4
L1
M1
L5
M5
G7
J8
G8
G9
J7
J9
A8
B8
A9
B9
D8
E8
D9
E9
SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63
4 OF 9
4 OF 9
2
Haswell rPGA EDS
JCPUD
JCPUD
I
I
N
N
Haswell rPGA EDS
SB_DQS_N_0
SB_DQS_N_1
SB_DQS_N_2
SB_DQS_N_3
SB_DQS_N_4
SB_DQS_N_5
SB_DQS_N_6
SB_DQS_N_7
SB_DQS_P_0
SB_DQS_P_1
SB_DQS_P_2
SB_DQS_P_3
SB_DQS_P_4
SB_DQS_P_5
SB_DQS_P_6
SB_DQS_P_7
TEL_HASWELL_HAS WELL
TEL_HASWELL_HAS WELL
RSVD
SB_CKN0
SB_CK0
SB_CKE_0
SB_CKN1
SB_CK1
SB_CKE_1
SB_CKN2
SB_CK2
SB_CKE_2
SB_CKN3
SB_CK3
SB_CKE_3
SB_CS_N_0
SB_CS_N_1
SB_CS_N_2
SB_CS_N_3
SB_ODT_0
SB_ODT_1
SB_ODT_2
SB_ODT_3
SB_BS_0
SB_BS_1
SB_BS_2
RSVD
SB_RAS
SB_WE
SB_CAS
SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14
SB_MA_15
AG8
Y4
AA4
AF10
Y3
AA3
AG10
Y2
AA2
AG9
Y1
AA1
AF9
P4
R2
P3
P1
R4
R3
R1
P2
R7
P8
AA9
R10
R6
P6
P7
R8
DDRB_MA0
Y5
DDRB_MA1
Y10
DDRB_MA2
AA5
DDRB_MA3
Y7
DDRB_MA4
AA6
DDRB_MA5
Y6
DDRB_MA6
AA7
DDRB_MA7
Y8
DDRB_MA8
AA10
DDRB_MA9
R9
DDRB_MA10
Y9
DDRB_MA11
AF7
DDRB_MA12
P9
DDRB_MA13
AA8
DDRB_MA14
AG7
DDRB_MA15
AP18
DDRB_DQS#0
AP11
DDRB_DQS#1
AP5
DDRB_DQS#2
AJ3
DDRB_DQS#3
L3
DDRB_DQS#4
H9
DDRB_DQS#5
C8
DDRB_DQS#6
C14
DDRB_DQS#7
AP17
DDRB_DQS0
AP12
DDRB_DQS1
AP6
DDRB_DQS2
AK3
DDRB_DQS3
M3
DDRB_DQS4
H8
DDRB_DQS5
C9
DDRB_DQS6
C15
DDRB_DQS7
T63 PAD@ T63 PAD@
DDRB_CLK0# <12>
DDRB_CLK0 <12>
DDRB_CKE0 <12>
DDRB_CLK1# <12>
DDRB_CLK1 <12>
DDRB_CKE1 <12>
DDRB_CS0# <12>
DDRB_CS1# <12>
DDRB_ODT0 <12>
DDRB_ODT1 <12>
DDRB_BS0# <12>
DDRB_BS1# <12>
DDRB_BS2# <12>
DDRB_RAS# <12>
DDRB_WE# <12>
DDRB_CAS# <12>
DDRB_MA[0..15] <12>
DDRB_DQS#[0..7] <12>
DDRB_DQS[0..7] <12>
1
DRAMRST_CNTRL<6>
+VREF_DQ_DIMMA_R
+VREF_DQ_DIMMB_R
A A
5
6/8: Add M3 Circuit (Processor Generated SO-DIMM VREF_DQ)
4
DRAMRST_CNTRL
DRAMRST_CNTRL
2
G
G
QC11 BSS138_SOT23
QC11 BSS138_SOT23
1 3
D
S
D
S
@
@
1 2
RC1548 0_0402_ 5%RC1548 0_0402_5%
1 2
RC92 0_0402_5%RC92 0_0402_5%
@
@
1 3
D
S
D
S
QC9 BSS138_SOT23
QC9 BSS138_SOT23
G
G
2
+V_DDR_REFA_R
+V_DDR_REFB_R
12
12
RC143
@ RC143
@
RC144
@RC144
@
1K_0402_1%
1K_0402_1%
1K_0402_1%
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
1K_0402_1%
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
2012/07/01
2012/07/01
2012/07/01
3
Deciphered Date
Deciphered Date
Deciphered Date
2
2014/07/01
2014/07/01
2014/07/01
Title
Title
Title
CPU (3/7) DDRIII
CPU (3/7) DDRIII
CPU (3/7) DDRIII
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Date: Sheet of
Date: Sheet of
Date: Sheet of
Wednesday, March 27, 2013
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
1
7 69
7 69
7 69
1.0
1.0
1.0
5
4
3
2
1
CFG STRAPS for CPU
CFG2
D D
PEG Static Lane Reversal - CFG2 is for the 16x
*
20120829 VA1
Add net for add HDMI MUX
CPU_HDMI_TX2-<37>
CPU_HDMI_TX2+<37>
CPU_HDMI_TX1-<37>
CPU_HDMI_TX1+<37>
CPU_HDMI_TX0-<37>
CPU_HDMI_TX0+<37>
CPU_HDMI_CLK-<37>
check CLK item
CPU_HDMI_CLK+<37>
COMPENSATION PU FOR eDP
12
C C
EDP_COMP
CAD Note:Trace width=20 mils ,Spacing=25mil,
Max length=100 mils.
+VCCIOA_OUT
12
RC124.9_0402_1% RC12 4.9_0402_1%
+VCCIO_OUT
10K_0402_5%
10K_0402_5%
RC45 49.9_0402_1%RC45 49.9_0402_1%
RC58 49.9_0402_1%RC58 49.9_0402_1%
RC59 49.9_0402_1%RC59 49.9_0402_1%
RC65
RC65
H_CPU_TESTLO
12
CFG_RCOMP
12
H_CPU_RSVD
HPD INVERSION FOR EDP
1 2
EDP_HPD_IN#
BSS138_SOT23
BSS138_SOT23
13
D
D
QC6
QC6
CPU_EDP_HPD<38>
B B
A A
2
G
G
S
100K_0402_5%
100K_0402_5%
12
RC75
RC75
S
T70 PAD@T70 PAD@
T71 PAD@T71 PAD@
T72 PAD@T72 PAD@
T73 PAD@T73 PAD@
T77 PAD@T77 PAD@
T76 PAD@T76 PAD@
T80 PAD@T80 PAD@
T79 PAD@T79 PAD@
T94 PAD@T94 PAD@
+VCC_CORE
T82 PAD@T82 PAD@
T81 PAD@T81 PAD@
T85 PAD@T85 PAD@
T84 PAD@T84 PAD@
T83 PAD@T83 PAD@
T173PAD@ T173PAD@
T116PAD@ T116PAD@
T117PAD@ T117PAD@
T126PAD@ T126PAD@
T129PAD@ T129PAD@
T130PAD@ T130PAD@
T131PAD@ T131PAD@
T132PAD@ T132PAD@
T133PAD@ T133PAD@
T134PAD@ T134PAD@
T135PAD@ T135PAD@
T136PAD@ T136PAD@
T137PAD@ T137PAD@
T138PAD@ T138PAD@
T142PAD@ T142PAD@
T143PAD@ T143PAD@
H_CPU_RSVD
H_CPU_TESTLO
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
Haswell rPGA EDS
Haswell rPGA EDS
T28
DDIB_TXBN_0
U28
DDIB_TXBP_0
T30
DDIB_TXBN_1
U30
DDIB_TXBP_1
U29
DDIB_TXBN_2
V29
DDIB_TXBP_2
U31
DDIB_TXBN_3
V31
DDIB_TXBP_3
T34
DDIC_TXCN_0
U34
DDIC_TXCP_0
U35
DDIC_TXCN_1
V35
DDIC_TXCP_1
U32
DDIC_TXCN_2
T32
DDIC_TXCP_2
U33
DDIC_TXCN_3
V33
DDIC_TXCP_3
P29
DDID_TXDN_0
R29
DDID_TXDP_0
N28
DDID_TXDN_1
P28
DDID_TXDP_1
P31
DDID_TXDN_2
R31
DDID_TXDP_2
N30
DDID_TXDN_3
P30
DDID_TXDP_3
INTEL_HASWELL_HAS WELL
INTEL_HASWELL_HAS WELL
AT1
AT2
AD10
A34
A35
W29
W28
G26
W33
AL30
AL29
F25
C35
B35
AL25
W30
W31
W34
AT20
CFG0
AR20
AP20
AP22
AT22
AN22
AT25
AN23
AR24
AT23
AN20
AP24
AP26
AN25
AN26
AP25
Haswell rPGA EDS
Haswell rPGA EDS
RSVD_TP
RSVD_TP
RSVD
RSVD_TP
RSVD_TP
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
VCC
RSVD_TP
RSVD_TP
RSVD_TP
RSVD
RSVD
TESTLO
CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
INT
INT
EL_HASWELL_HASW ELL
EL_HASWELL_HASW ELL
JCPUH
JCPUH
eDP
eDP
EDP_AUXN
EDP_AUXP
EDP_HPD
EDP_RCOMP
RSVD
EDP_TXN_0
EDP_TXP_0
EDP_TXN_1
EDP_TXP_1
FDI_TXN_0
FDI_TXP_0
FDI_TXN_1
FDI_TXP_1
DDI
DDI
8 OF 9
8 OF 9
JCPUI
JCPUI
M27
N27
P27
E24
R27
P35
R35
N34
P34
P33
R33
N32
P32
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
CFG_RCOMP
CFG_16
CFG_18
CFG_17
CFG_19
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD_TP
RSVD_TP
RSVD_TP
RSVD
RSVD
RSVD
RSVD
9 OF 9
9 OF 9
CPU_EDP_AUX#
CPU_EDP_AUX
EDP_HPD_IN#
EDP_COMP
CPU_EDP_TX0ÂCPU_EDP_TX0+
CPU_EDP_TX1ÂCPU_EDP_TX1+
FDI_CTX_PRX_N0
FDI_CTX_PRX_P0
FDI_CTX_PRX_N1
FDI_CTX_PRX_P1
C23
B23
D24
D23
AT31
AR21
AR23
AP21
AP23
AR33
G6
AM27
AM26
F5
AM2
K6
E18
U10
P10
B1
NC
A2
AR1
E21
E20
AP27
AR26
AL31
AL32
CFG_RCOMP
CFG16
CFG18
CFG17
CFG19
CPU_EDP_AUX# <38>
CPU_EDP_AUX <38>
T69PAD @T69PAD @
CPU_EDP_TX0- <38>
CPU_EDP_TX0+ <38>
CPU_EDP_TX1- <38>
CPU_EDP_TX1+ <38>
FDI_CTX_PRX_N0 <15>
FDI_CTX_PRX_P0 <15>
FDI_CTX_PRX_N1 <15>
FDI_CTX_PRX_P1 <15>
T86PAD @T86PAD @
T78PAD @T78PAD @
T87PAD @T87PAD @
T88PAD @T88PAD @
T156PAD @T156PAD @
T164PAD @T164PAD @
T165PAD @T165PAD @
T166PAD @T166PAD @
T91PAD @T91PAD @
T90PAD @T90PAD @
T92PAD @T92PAD @
T89PAD @T89PAD @
T93PAD @T93PAD @
T95PAD @T95PAD @
T104PAD @T104PAD @
T96PAD @T96PAD @
T98PAD @T98PAD @
T97PAD @T97PAD @
T100PAD @T100PAD @
T99PAD @T99PAD @
T102PAD @T102PAD @
T101PAD @T101PAD @
CFG[6:5]
CFG2
Display Port Presence Strap
1 : Disabled; No Physical Display Port
CFG4
attached to Embedded Display Port
0 : Enabled; An external Display Port device is
*
connected to the Embedded Display Port
CFG5
CFG6
11: (Default) x16 - Device 1 functions 1 and 2 disabled
10: x8, x8 - Device 1 function 1 enabled ; function 2
*
disabled
01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
*
CFG7
1K_0402_1%
1K_0402_1%
12
@RC76
@
RC76
1:(Default) Normal Operation; Lane #
definition matches socket pin map definition
0:Lane Reversed
CFG4
1K_0402_1%
1K_0402_1%
1K_0402_1%
1K_0402_1%
12
12
@RC83
@
RC83
RC85
RC85
1K_0402_1%
1K_0402_1%
12
RC77
RC77
PCIE Port Bifurcation Straps
CFG7
1K_0402_1%
1K_0402_1%
12
@RC86
@
RC86
PEG DEFER TRAINING
1: (Default) PEG Train immediately
following xxRESETB de assertion
0: PEG Wait for BIOS for training
Title
Title
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
3
2012/07/01
2012/07/01
2012/07/01
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2014/07/01
2014/07/01
2014/07/01
Title
CPU (4/7) RSVD,CFG
CPU (4/7) RSVD,CFG
CPU (4/7) RSVD,CFG
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Date: Sheet of
Date: Sheet of
Date: Sheet of
Wednesday, March 27, 2013
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
1
8 69
8 69
8 69
1.0
1.0
1.0
5
4
3
2
1
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AA26
AA28
AA34
AA30
AA32
AB26
AB29
AB25
AB27
AB28
AB30
AB31
AB33
AB34
AB32
AC26
AB35
AC28
AD25
AC30
AD28
AC32
AD31
AC34
AD34
AD26
AD27
AD29
AD30
AD32
AD33
AD35
AE26
AE32
AE28
AE30
AG28
AG34
AE34
AF25
AF26
AF27
AF28
AF29
AF30
AF31
AF32
AF33
AF34
AF35
AG26
AH26
AH29
AG30
AG32
AH32
AH35
AH25
AH27
AH28
AH30
AH31
AH33
AH34
AJ25
AJ26
AJ27
AJ28
AJ29
AJ30
AJ31
AJ32
AJ33
AJ34
AJ35
G25
H25
J25
K25
L25
M25
N25
P25
R25
T25
U25
U26
V25
V26
W26
W27
+VCC_CORE
Haswell rPGA EDS
Haswell rPGA EDS
AB11
AB2
AB5
AB8
AE11
AE2
AE5
AE8
AH11
K11
N11
W11
N26
K26
AL27
AK27
AL35
E17
AN35
A23
W32
AL16
AL13
AM28
AM29
AL28
AP35
H27
AP34
AT35
AR35
AR32
AL26
AT34
AL22
AT33
AM21
AM25
AM22
AM20
AM24
AL19
AM23
AT32
K27
L27
T27
V27
N8
T11
T2
T5
T8
W2
W5
W8
F22
J27
Y25
Y26
Y27
Y28
Y29
Y30
Y31
Y32
Y33
Y34
Y35
RSVD
RSVD
RSVD
RSVD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
RSVD
VCC
RSVD
RSVD
VCC_SENSE
RSVD
VCCIO_OUT
VCCIO2PCH
VCCIOA_OUT
RSVD
RSVD
VSS
RSVD
VIDALERT
VIDSCLK
VIDSOUT
VSS
PWR_DEBUG
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
TEL_HASWELL_HAS WELL
TEL_HASWELL_HAS WELL
IN
IN
T107 PAD@ T107 PAD@
T106 PAD@ T106 PAD@
D D
+1.35V
CC151 0.1U_04 02_25V6KCC151 0.1U_04 02_25V6K
CC152 0.1U_04 02_25V6KCC152 0.1U_04 02_25V6K
C C
VCC_SENSE
VCCSENSE<64>
need connect to power
VSSSENSE<64>
B B
+1.35V_CPU_VDDQ
10U_0603_6.3V6M
10U_0603_6.3V6M
1
CC171
CC171
2
22U_0805_6.3V6M
22U_0805_6.3V6M
1
CC33
A A
CC33
2
+VCC_CORE
100_0402_1%
100_0402_1%
12
RC66
RC66
CAD Note: RC67 SHOULD BE PLACED CLOSE TO CPU
VCCSENSE VCCSENSE_R
RC67
RC67
12
R_short 0_0402_5%
R_short 0_0402_5%
CAD Note: RC68 SHOULD BE PLACED CLOSE TO CPU
VSSSENSE VSSSENSE_R
RC68
RC68
100_0402_1%
100_0402_1%
12
RC70
RC70
12
R_short 0_0402_5%
R_short 0_0402_5%
VDDQ DECOUPLING
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1
1
CC169
CC169
CC170
CC170
2
2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1
1
CC35
CC35
CC34
CC34
2
2
@
@
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1
CC168
CC168
2
22U_0805_6.3V6M
22U_0805_6.3V6M
1
CC36
CC36
2
10U_0603_6.3V6M
1
1
CC161
CC161
CC162
CC162
2
2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1
1
CC37
CC37
CC38
CC38
2
2
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1
1
CC163
CC163
2
2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1
1
CC39
CC39
2
2
RC4
RC4
+1.05VS +VCCIO_OUT
VSSSENSE_R <10>
Power
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1
CC164
CC164
CC165
CC165
2
22U_0805_6.3V6M
22U_0805_6.3V6M
1
CC41
CC41
CC40
CC40
2
@
@
330U_D2_2VM_R6M
330U_D2_2VM_R6M
330U_D2_2VM_R6M
330U_D2_2VM_R6M
1
1
CC167
CC167
CC172
1
CC166
CC166
@
@
2
22U_0805_6.3V6M
22U_0805_6.3V6M
1
CC42
CC42
2
CC172
+
+
+
+
@
@
2
2
22U_0805_6.3V6M
22U_0805_6.3V6M
1
CC43
CC43
2
0_0603_5% @
0_0603_5% @
VR_SVID_ALRT#<64>
VR_SVID_CLK<64>
VR_SVID_DAT<64>
+1.05VS
150_0402_1%
150_0402_1%
12
@
@
CPU_PWR_DEBU G
10K_0402_5%
10K_0402_5%
12
12
RC61 43_0402_5%RC61 43_0402_5%
1 2
12
RC63
RC63
@
@
130_0402_1%
130_0402_1%
+VCCIO_OUT
RC69
RC69
CPU_PWR_DEBU G <6>
@
@
RC71
RC71
need connect to power
T112 PAD@ T112 PAD@
T113 PAD@ T113 PAD@
12
12
placement
T115 PAD@ T115 PAD@
+VCC_CORE
T151 PAD@ T151 PAD@
T152 PAD@ T152 PAD@
T153 PAD@ T153 PAD@
+VCCIO_OUT
+1.05VS
+VCCIOA_OUT
T160 PAD@ T160 PAD@
T159 PAD@ T159 PAD@
T154 PAD@ T154 PAD@
VR_SVID_ALRT#_R
VR_SVID_CLK
VR_SVID_DAT
CPU_PWR_DEBU G
T157 PAD@ T157 PAD@
T158 PAD@ T158 PAD@
T162 PAD@ T162 PAD@
T163 PAD@ T163 PAD@
+1.35V_CPU_VDDQ
VCCSENSE_R
+VCC_CORE
JCPUE
JCPUE
5 OF 9
5 OF 9
Title
Title
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
3
2012/07/01
2012/07/01
2012/07/01
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2014/07/01
2014/07/01
2014/07/01
Title
CPU (5/7) PWR, BYPASS
CPU (5/7) PWR, BYPASS
CPU (5/7) PWR, BYPASS
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Date: Sheet of
Date: Sheet of
Date: Sheet
Wednesday, March 27, 2013
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
1
9 69
9 69
9 69
of
1.0
1.0
1.0
5
Haswell rPGA EDS
Haswell rPGA EDS
A10
VSS
A13
VSS
A16
VSS
A19
VSS
A22
VSS
A25
VSS
A27
VSS
A29
VSS
A3
VSS
A31
VSS
A33
VSS
A4
D D
C C
B B
AA11
AA25
AA27
AA31
AA29
AB1
AB10
AA33
AA35
AB3
AC25
AC27
AB4
AB6
AB7
AB9
AC11
AD11
AC29
AC31
AC33
AC35
AD7
AE1
AE10
AE25
AE29
AE3
AE27
AE35
AE4
AE6
AE7
AE9
AF11
AF6
AF8
AG11
AG25
AE31
AG31
AE33
AG6
AH1
AH10
AH2
AG27
AG29
AH3
AG33
AG35
AH4
AH5
AH6
AH7
AH8
AH9
AJ11
AK11
AK25
AK26
AK28
AK29
AK30
AK32
VSS
A7
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AJ5
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
E19
VSS
JCPUF
JCPUF
TEL_HASWELL_HAS WELL
TEL_HASWELL_HAS WELL
IN
IN
For Deep S3
+3VALW
12
RC1537
@RC 1537
13
D
D
2
G
G
S
S
@
RUN_ON_CPU1.5VS3#
@
@
QC156
QC156
2N7002KW_SOT323-3
2N7002KW_SOT323-3
2
G
G
100K_0402_5%
100K_0402_5%
RC1538
RC1538
1 2
@
A A
SUSP<40,55,61>
CPU1.5V_S3_GATE<46>
@
0_0402_5%
0_0402_5%
4
AK34
VSS
AK5
VSS
AL1
VSS
AL10
VSS
AL11
VSS
AL12
VSS
AL14
VSS
AL15
VSS
AL17
VSS
AL18
VSS
AL2
VSS
AL20
VSS
AL21
VSS
AL23
VSS
E22
VSS
AL3
VSS
AL4
VSS
AL5
VSS
AL6
VSS
AL7
VSS
AL8
VSS
AL9
VSS
AM10
VSS
AM13
VSS
AM16
VSS
AM19
VSS
E25
VSS
AM32
VSS
AM4
VSS
AM7
VSS
AN10
VSS
AN13
VSS
AN16
VSS
AN19
VSS
AN2
VSS
AN21
VSS
AN24
VSS
AN27
VSS
AN30
VSS
AN34
VSS
AN4
VSS
AN7
VSS
AP1
VSS
AP10
VSS
AP13
VSS
AP16
VSS
AP19
VSS
AP4
VSS
AP7
VSS
W25
VSS
AR10
RSVD
AR13
VSS
AR16
VSS
AR19
VSS
AR2
VSS
AR22
VSS
AR25
VSS
AR28
VSS
AR31
VSS
AR34
VSS
AR4
VSS
AR7
VSS
AT10
VSS
AT13
VSS
AT16
VSS
AT19
VSS
AT21
VSS
AT24
VSS
AT27
VSS
AT3
VSS
AT30
VSS
AT4
VSS
AT7
VSS
B10
VSS
B13
VSS
B16
VSS
B19
VSS
B2
VSS
B22
VSS
6 OF 9
6 OF 9
+VSB
12
R56 need to chec k on SDV
RC56
@ RC56
@
100K_0402_5%
100K_0402_5%
RUN_ON_CPU1.5VS3
13
D
D
@
@
QC4
QC4
2N7002KW_SOT323-3
2N7002KW_SOT323-3
S
S
+1.35V_CPU_VDDQ
@ J15
@
2
JUMP_43X79
JUMP_43X79
+1.35V
12
RC1546
@ RC1546
@
470K_0402_5%
470K_0402_5%
1 2
470K_0402_5%
470K_0402_5%
1 2
CC287 0.1U_0402_10V6KCC287 0.1U_0402_10V6K
1 2
CC286 0.1U_0402_10V6KCC286 0.1U_0402_10V6K
1 2
CC96 0.1U_0402_10V6KCC96 0.1U_0402_10V6K
1 2
CC95 0.1U_0402_10V6KCC95 0.1U_0402_10V6K
UC3
UC3
8
7
6
5
AO4304L_SO8
AO4304L_SO8
RC1349
4
@RC134 9
@
1
@
@
2
J15
112
1
2
3
@
@
AO4304L
Vgs=10V,Id=18A,
Rds<6.7m ohm
P/N: SB00000RV00
CC97
CC97
0.01U 50V K X7R 0603
0.01U 50V K X7R 0603
3
+1.35V_CPU_VDDQ+1.35V
+1.35V_CPU_VDDQ
12
RC1487
@ RC1487
@
470_0603_5%
470_0603_5%
QC5
QC5
13
D
D
@
@
S
S
2
SUSP
G
G
2N7002KW_SOT323-3
2N7002KW_SOT323-3
Haswell rPGA EDS
Haswell rPGA EDS
B34
VSS
B4
VSS
B7
VSS
C1
VSS
C10
VSS
C13
VSS
C16
VSS
C19
VSS
C2
VSS
C22
VSS
C24
VSS
C26
VSS
C28
VSS
C30
VSS
C32
VSS
C34
VSS
C4
VSS
C7
VSS
D10
VSS
D13
VSS
D16
VSS
D19
VSS
D22
VSS
D25
VSS
D27
VSS
D29
VSS
D31
VSS
D33
VSS
D35
VSS
D4
VSS
D7
VSS
E1
VSS
E10
VSS
E13
VSS
E16
VSS
E4
VSS
E7
VSS
F10
VSS
F11
VSS
F12
VSS
F14
VSS
F15
VSS
F17
VSS
F18
VSS
F20
VSS
F21
VSS
F23
VSS
F24
VSS
F26
VSS
F28
VSS
F30
VSS
F32
VSS
F34
VSS
F4
VSS
F6
VSS
F7
VSS
F8
VSS
F9
VSS
G1
VSS
G11
VSS
G2
VSS
G27
VSS
G29
VSS
G3
VSS
G31
VSS
G33
VSS
G35
VSS
G4
VSS
G5
VSS
H10
VSS
H26
VSS
H6
VSS
H7
VSS
J11
VSS
J26
VSS
J28
RSVD
J30
VSS
J32
VSS
J34
VSS
J6
VSS
K1
VSS
TEL_HASWELL_HAS WELL
TEL_HASWELL_HAS WELL
IN
IN
JCPUG
JCPUG
2
RSVD
RSVD
RSVD
RSVD
VSS_SENSE
RSVD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
7 OF 9
7 OF 9
K10
K2
K29
K3
K31
K33
K35
K4
K5
K7
K8
K9
L11
L26
L6
M11
M26
M28
M30
M32
M34
M6
N1
N10
N2
N29
N3
N31
N33
N35
N4
N5
N6
N7
N9
P11
P26
P5
R11
R26
R28
R30
R32
R34
R5
T1
T10
T29
T3
T31
T33
T35
T4
T6
T7
T9
U11
U27
V11
V28
V30
V32
V34
W1
W10
W3
W35
W4
W6
W7
W9
Y11
H11
AL24
F19
T26
AK35
AK33
RC237 0_0402_5%RC237 0_0402_5%
1 2
T65PAD @T65PAD @
1
RC238 0_0402_5%RC238 0_0402_5%
VSSSENSE_R <9>
1 2
Title
Title
RUN_ON_CPU1.5VS3# <6>
5
4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
3
2012/07/01
2012/07/01
2012/07/01
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2014/07/01
2014/07/01
2014/07/01
Title
CPU (6/7) PWR
CPU (6/7) PWR
CPU (6/7) PWR
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Date: Sheet of
Date: Sheet of
Date: Sheet of
Wednesday, March 27, 2013
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
1
10 69
10 69
10 69
1.0
1.0
1.0
5
4
3
2
1
DDR3 SO-DIMM A
+VREF_DQ_DIMMA_R
1 2
0_0402_5%
0_0402_5%
D D
1
CD180
CD180
0.1U_0402_10V6K
0.1U_0402_10V6K
2
12
RD90
RD90
24.9_0402_1%
24.9_0402_1%
C C
B B
A A
RD91
RD91
20120727 VA
SWAP DQ for layout
+3VS
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
+1.35V
12
RD78
RD78
1K_0402_1%
1K_0402_1%
+VREF_DQ_DIMMA
12
RD79
RD79
1
CD141
CD141
2
1K_0402_1%
1K_0402_1%
20120727 VA
SWAP DQ for layout
DDRA_CKE0<7>
DDRA_BS2#<7>
DDRA_CLK0<7>
DDRA_CLK0#<7>
DDRA_BS0#<7>
DDRA_WE#<7>
DDRA_CAS#<7>
DDRA_CS1#<7>
1
CD290
CD290
2
5
1
CD140
CD140
2
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
1
CD162
CD162
0.1U_0402_10V6K
0.1U_0402_10V6K
2
+1.35V+1.35V
3A@1.5V
JDDRL1
JDDRL1
VREF_DQ1VSS1
3
VSS2
DDRA_DQ4
DDRA_DQ0
0.1U_0402_10V6K
0.1U_0402_10V6K
DDRA_DQ13 DDRA_DQ15
DDRA_DQ12
DDRA_DQS#1
DDRA_DQS1
DDRA_DQ9
DDRA_DQ8
DDRA_DQ20
DDRA_DQ21
DDRA_DQS#2
DDRA_DQS2
DDRA_DQ23
DDRA_DQ19
DDRA_DQ25
DDRA_DQ28
DDRA_DQ27
DDRA_DQ26
DDRA_CKE0
DDRA_BS2#
DDRA_MA12
DDRA_MA9
DDRA_MA8
DDRA_MA5
DDRA_MA3
DDRA_MA1
DDRA_CLK0
DDRA_CLK0#
DDRA_MA10
DDRA_BS0#
DDRA_WE#
DDRA_CAS# DDRA_ODT0
DDRA_MA13
DDRA_CS1#
DDRA_DQ32
DDRA_DQ33
DDRA_DQS#4
DDRA_DQS4
DDRA_DQ37 DDRA_DQ35
DDRA_DQ36
DDRA_DQ40
DDRA_DQ41
DDRA_DQ42
DDRA_DQ44
DDRA_DQ52
DDRA_DQ53
DDRA_DQS#6
DDRA_DQS6
DDRA_DQ48
DDRA_DQ50
DDRA_DQ61 DDRA_DQ57
DDRA_DQ60
DDRA_DQ58
DDRA_DQ59
RD82
RD82
1 2
10K_0402_5%
10K_0402_5%
12
RD83
RD83
10K_0402_5%
10K_0402_5%
5
DQ0
7
DQ1
9
VSS4
11
DM0
13
VSS5
15
DQ2
17
DQ3
19
VSS7
21
DQ8
23
DQ9
25
VSS9
27
DQS#1
DQS129RESET#
VSS1131VSS12
33
DQ10
35
DQ11
VSS1337VSS14
39
DQ16
41
DQ17
VSS1543VSS16
45
DQS#2
47
DQS2
49
VSS18
51
DQ18
53
DQ19
55
VSS20
57
DQ24
59
DQ25
VSS2261DQS#3
63
DM3
VSS2365VSS24
67
DQ26
69
DQ27
VSS2571VSS26
73
CKE0
75
VDD1
77
NC1
79
BA2
81
VDD3
83
A12/BC#
85
A9
87
VDD5
89
A8
91
A5
93
VDD7
95
A3
97
A1
99
VDD9
101
CK0
103
CK0#
105
VDD11
107
A10/AP
109
BA0
111
VDD13
113
WE#
115
CAS#
117
VDD15
119
A13
121
S1#
123
VDD17
125
NCTEST
127
VSS27
129
DQ32
131
DQ33
133
VSS29
135
DQS#4
137
DQS4
139
VSS32
141
DQ34
143
DQ35
145
VSS34
147
DQ40
149
DQ41
151
VSS36
153
DM5
155
VSS37
157
DQ42
159
DQ43
161
VSS39
163
DQ48
165
DQ49
167
VSS41
169
DQS#6
171
DQS6
173
VSS44
175
DQ50
177
DQ51
179
VSS46
181
DQ56
183
DQ57
185
VSS48
187
DM7
189
VSS49
191
DQ58
193
DQ59
195
VSS51
197
SA0
199
VDDSPD
201
SA1
203
VTT1
205
G1
LCN_DAN06-K4806-0102
LCN_DAN06-K4806-0102
ME@
ME@
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
DQ14
DQ15
DQ20
DQ21
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS3
DQ30
DQ31
CKE1
VDD2
VDD4
VDD6
VDD8
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
A15
80
A14
82
84
A11
86
A7
88
90
A6
92
A4
94
96
A2
98
A0
100
102
104
106
108
110
112
114
S0#
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
G2
4
DDRA_DQ7
DDRA_DQ6
DDRA_DQS#0
DDRA_DQS0
DDRA_DQ2DDRA_DQ1
DDRA_DQ3DDRA_DQ5
DDRA_DQ14
DDR3_DRAMRST#
DDRA_DQ11
DDRA_DQ10
DDRA_DQ16
DDRA_DQ17
DDRA_DQ22
DDRA_DQ18
DDRA_DQ31
DDRA_DQ29
DDRA_DQS#3
DDRA_DQS3
DDRA_DQ24
DDRA_DQ30
DDRA_CKE1
DDRA_MA15
DDRA_MA14
DDRA_MA11
DDRA_MA7
DDRA_MA6
DDRA_MA4
DDRA_MA2
DDRA_MA0
DDRA_CLK1
DDRA_CLK1#
DDRA_BS1#
DDRA_RAS#
DDRA_CS0#
DDRA_ODT1
DDRA_DQ38
DDRA_DQ34
DDRA_DQ39
DDRA_DQ45
DDRA_DQ47
DDRA_DQS#5
DDRA_DQS5
DDRA_DQ43
DDRA_DQ46
DDRA_DQ49
DDRA_DQ51
DDRA_DQ54
DDRA_DQ55
DDRA_DQ56
DDRA_DQS#7
DDRA_DQS7
DDRA_DQ62
DDRA_DQ63
SMB_DATA_S3
SMB_CLK_S3
0.65A@0.75V
0.65A@0.75V
0.65A@0.75V0.65A@0.75V
For RF request
0.047U_0402_16V4Z
0.047U_0402_16V4Z
1
CD51
CD51
CD52
CD52
@
@
@
@
2
DDR3_DRAMRST# <12,6>
20120727 VA
SWAP DQ for layout
DDRA_CKE1 <7>
DDRA_CLK1 <7>
DDRA_CLK1# <7>
DDRA_BS1# < 7>
DDRA_RAS# <7>
DDRA_CS0# <7>
DDRA_ODT0 <7>
DDRA_ODT1 <7>
0.1U_0402_10V6K
0.1U_0402_10V6K
1
CD149
CD149
+0.675VS
1
CD150
CD150
2
2
20120727 VA
SWAP DQ for layout
SMB_DATA_S3 <12,17,40,47>
SMB_CLK_S3 <12,17,40,47>
0.047U_0402_16V4Z
0.047U_0402_16V4Z
0.047U_0402_16V4Z
0.047U_0402_16V4Z
1
1
CD53
CD53
@
@
2
2
Layout Note:
Pl
ace near DIMM
OSCON (220uF_6.3V_4.2L_ESR17m)*1=(SF000002Y00)
(10uF_0603_6.3V)*8
(0.1uF_402_10V)*4
+1.35V
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1
2
3
1
CD142
CD142
2
+VREF_CA <12>
CD151
CD151
+VREF_CA
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
CD143
CD143
10U_0603_6.3V6M
1
CD152
CD152
2
+VREF_CA
Layout Note:
ace near DIMM
Pl
+0.675VS
CD288
CD288
2012/07/01
2012/07/01
2012/07/01
1
2
1K_0402_1%
1K_0402_1%
1K_0402_1%
1K_0402_1%
1
2
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1
CD144
CD144
2
12
RD80
RD80
12
RD81
RD81
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1
CD158
CD158
2
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
DDRA_DQ[0..63] <7>
DDRA_DQS[0..7] <7>
DDRA_DQS#[0..7] <7>
DDRA_MA[0..15] <7>
10U_0603_6.3V6M
10U_0603_6.3V6M
1
CD145
CD145
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1
CD159
CD159
2
Deciphered Date
Deciphered Date
Deciphered Date
10U_0603_6.3V6M
10U_0603_6.3V6M
1
CD153
CD153
2
+VREF_CA_R+1.35V
RD89
RD89
12
0_0402_5%
0_0402_5%
CD179 0.1U_0402_10V6KCD179 0.1U_0402_10V6K
24.9_0402_1%
24.9_0402_1%
1U_0402_6.3V6K
1U_0402_6.3V6K
1
CD160
CD160
2
2
10U_0603_6.3V6M
CD146
CD146
RD88
RD88
10U_0603_6.3V6M
1
2
1
2
12
0.1U_0402_10V6K
0.1U_0402_10V6K
1
CD154
CD154
2
Note:
VREF trace width:20 mils at least
Spacing:20mils to other signal/planes
Place near DIMM scoket
Layout Note:
Place near DIMM
DDR_A_DM[0:7] connect to GND
2014/07/01
2014/07/01
2014/07/01
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
1
1
CD147
CD147
CD155
CD155
2
2
Title
Title
Title
DDRIII SO-DIMM A
DDRIII SO-DIMM A
DDRIII SO-DIMM A
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Date: Sheet
Date: Sheet of
Date: Sheet of
Wednesday, March 27, 2013
0.1U_0402_10V6K
0.1U_0402_10V6K
1
CD156
CD156
2
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
1
+
+
CD148
CD148
220U_6.3V_M
220U_6.3V_M
2
of
11 69
11 69
1
11 69
1.0
1.0
1.0
5
4
3
2
1
+VREF_DQ_DIMMB_R
1 2
0_0402_5%
0_0402_5%
D D
C C
B B
A A
1
CD181
CD181
0.1U_0402_10V6K
0.1U_0402_10V6K
2
12
RD92
RD92
24.9_0402_1%
24.9_0402_1%
RD93
RD93
+1.35V
12
RD84
RD84
1K_0402_1%
1K_0402_1%
12
RD85
RD85
CD289
CD289
1K_0402_1%
1K_0402_1%
DDRB_CKE0<7>
DDRB_BS2#<7>
DDRB_CLK0<7>
DDRB_CLK0#<7>
DDRB_BS0#<7>
DDRB_WE#<7>
DDRB_CAS#<7>
DDRB_CS1#<7>
+3VS
CD177
CD177
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
5
1
2
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
1
2
+VREF_DQ_DIMMB
1
CD157
CD157
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
CD178
CD178
0.1U_0402_10V6K
0.1U_0402_10V6K
2
DDRB_DQ4
DDRB_DQ2
DDRB_DQ3
DDRB_DQ13
DDRB_DQ12
DDRB_DQS#1
DDRB_DQS1
DDRB_DQ15
DDRB_DQ20
DDRB_DQ16
DDRB_DQS#2
DDRB_DQS2
DDRB_DQ22
DDRB_DQ23
DDRB_DQ28
DDRB_DQ29
DDRB_DQ26
DDRB_DQ27
DDRB_CKE0
DDRB_BS2#
DDRB_MA12
DDRB_MA9
DDRB_MA8
DDRB_MA5
DDRB_MA3
DDRB_MA1
DDRB_CLK0
DDRB_CLK0#
DDRB_MA10
DDRB_BS0#
DDRB_WE#
DDRB_CAS#
DDRB_MA13
DDRB_CS1#
DDRB_DQ39
DDRB_DQ33
DDRB_DQS#4
DDRB_DQS4
DDRB_DQ32
DDRB_DQ36
DDRB_DQ44
DDRB_DQ45
DDRB_DQ40
DDRB_DQ42
DDRB_DQ53
DDRB_DQ55
DDRB_DQS#6
DDRB_DQS6
DDRB_DQ49
DDRB_DQ48
DDRB_DQ60
DDRB_DQ63
DDRB_DQ62
RD95
RD95
1 2
10K_0402_5%
10K_0402_5%
1 2
RD9710K_0402_5%RD9710K_0402_5%
DDR3 SO-DIMM B
+1.35V +1.35V
3A@1.5V
JDDRL2
JDDRL2
VREF_DQ1VSS1
3
VSS2
5
DQ0
7
DQ1
9
VSS4
11
DM0
13
VSS5
15
DQ2
17
DQ3
19
VSS7
21
DQ8
23
DQ9
25
VSS9
27
DQS#1
DQS129RESET#
VSS1131VSS12
33
DQ10
35
DQ11
VSS1337VSS14
39
DQ16
41
DQ17
VSS1543VSS16
45
DQS#2
47
DQS2
49
VSS18
51
DQ18
53
DQ19
55
VSS20
57
DQ24
59
DQ25
VSS2261DQS#3
63
DM3
VSS2365VSS24
67
DQ26
69
DQ27
VSS2571VSS26
73
CKE0
75
VDD1
77
NC1
79
BA2
81
VDD3
83
A12/BC#
85
A9
87
VDD5
89
A8
91
A5
93
VDD7
95
A3
97
A1
99
VDD9
101
CK0
103
CK0#
105
VDD11
107
A10/AP
109
BA0
111
VDD13
113
WE#
115
CAS#
117
VDD15
119
A13
121
S1#
123
VDD17
125
NCTEST
127
VSS27
129
DQ32
131
DQ33
133
VSS29
135
DQS#4
137
DQS4
139
VSS32
141
DQ34
143
DQ35
145
VSS34
147
DQ40
149
DQ41
151
VSS36
153
DM5
155
VSS37
157
DQ42
159
DQ43
161
VSS39
163
DQ48
165
DQ49
167
VSS41
169
DQS#6
171
DQS6
173
VSS44
175
DQ50
177
DQ51
179
VSS46
181
DQ56
183
DQ57
185
VSS48
187
DM7
189
VSS49
191
DQ58
193
DQ59
195
VSS51
197
SA0
199
VDDSPD
201
SA1
203
VTT1
205
G1
FOX_AS0A621-U4SG-7H
FOX_AS0A621-U4SG-7H
ME@
ME@
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
DQ14
DQ15
DQ20
DQ21
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS3
DQ30
DQ31
CKE1
VDD2
VDD4
VDD6
VDD8
VDD10
CK1#
VDD12
RAS#
VDD14
ODT0
VDD16
ODT1
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
VTT2
4
A15
A14
A11
CK1
BA1
S0#
NC2
SCL
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
A7
88
90
A6
92
A4
94
96
A2
98
A0
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
G2
DDRB_DQ0
DDRB_DQ1DDRB_DQ5
DDRB_DQS#0
DDRB_DQS0
DDRB_DQ6
DDRB_DQ7
DDRB_DQ8
DDRB_DQ9
DDR3_DRAMRST#
DDRB_DQ14
DDRB_DQ10DDRB_DQ11
DDRB_DQ17
DDRB_DQ21
DDRB_DQ18
DDRB_DQ19
DDRB_DQ30
DDRB_DQ31
DDRB_DQS#3
DDRB_DQS3
DDRB_DQ25
DDRB_DQ24
DDRB_CKE1
DDRB_MA15
DDRB_MA14
DDRB_MA11
DDRB_MA7
DDRB_MA6
DDRB_MA4
DDRB_MA2
DDRB_MA0
DDRB_CLK1
DDRB_CLK1#
DDRB_BS1#
DDRB_RAS#
DDRB_CS0#
DDRB_ODT0
DDRB_ODT1
DDRB_DQ35
DDRB_DQ37
DDRB_DQ38
DDRB_DQ34
DDRB_DQ41
DDRB_DQ47
DDRB_DQS#5
DDRB_DQS5
DDRB_DQ43
DDRB_DQ46
DDRB_DQ54
DDRB_DQ52
DDRB_DQ51
DDRB_DQ50
DDRB_DQ61
DDRB_DQ57DDRB_DQ56
DDRB_DQS#7
DDRB_DQS7
DDRB_DQ59
DDRB_DQ58
SMB_DATA_S3
SMB_CLK_S3
0.65A@0.75V
0.65A@0.75V
0.65A@0.75V0.65A@0.75V
For RF request
0.047U_0402_16V4Z
0.047U_0402_16V4Z
1
CD54
CD54
@
@
2
DDR3_DRAMRST# <11,6>
20120727 VA
SWAP DQ for layout
DDRB_CKE1 <7>
20120727 VA
SWAP DQ for layout
DDRB_CLK1 <7>
DDRB_CLK1# <7>
DDRB_BS1# < 7>
DDRB_RAS# <7>
DDRB_CS0# <7>
DDRB_ODT0 <7>
DDRB_ODT1 <7>
0.1U_0402_10V6K
0.1U_0402_10V6K
1
1
CD281
CD281
CD280
CD280
2
2
20120727 VA
SWAP DQ for layout
SMB_DATA_S3 <11,17,40,47>
SMB_CLK_S3 <11,17,40,47>
+0.675VS
Security Classification
Security Classification
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
1
CD55
CD55
@
@
2
+VREF_CA
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
Issued Date
Issued Date
Issued Date
0.047U_0402_16V4Z
0.047U_0402_16V4Z
CD56
CD56
@
@
3
0.047U_0402_16V4Z
0.047U_0402_16V4Z
1
2
Layout Note:
Place near DIMM
+1.35V
10U_0603_6.3V6M
10U_0603_6.3V6M
1
CD161
CD161
CD282
CD282
2
+VREF_CA <11>
2012/07/01
2012/07/01
2012/07/01
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1
1
CD163
CD163
CD164
CD164
2
2
Layout Note:
Place near DIMM
+0.675VS
CD173
CD173
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
(10uF_0603_6.3V)*8
(0
.1uF_402_10V)*4
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1
CD165
CD165
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1
CD174
CD174
2
Deciphered Date
Deciphered Date
Deciphered Date
1
2
1
1
CD166
CD166
2
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1
CD175
CD175
2
2014/07/01
2014/07/01
2014/07/01
2
DDRB_DQ[0..63] <7>
DDRB_DQS[0..7] <7>
DDRB_DQS#[0..7] <7>
DDRB_MA[0..15] <7>
10U_0603_6.3V6M
10U_0603_6.3V6M
1
CD168
CD168
CD167
CD167
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1
CD176
CD176
2
10U_0603_6.3V6M
10U_0603_6.3V6M
1
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
CD169
CD169
CD170
CD170
2
Layout Note:
ace near DIMM
Pl
0.1U_0402_10V6K
0.1U_0402_10V6K
1
1
CD171
CD171
2
2
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
1
CD172
CD172
2
DDR_B_DM[0:7] connect to GND
Title
Title
Title
DDRIII SO-DIMM B
DDRIII SO-DIMM B
DDRIII SO-DIMM B
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Date: Sheet
Date: Sheet of
Date: Sheet of
Wednesday, March 27, 2013
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
1
12 69
12 69
12 69
1.0
1.0
1.0
of
5
4
3
2
1
Place JUMPER under RAM door
+RTCVCC
1 2
D D
CRT_SWITCH_1<37>
+3V_PCH
0_0603_5%
0_0603_5%
12
RH288
C C
B B
RH288
@
@
+3.3V_ALW_PCH_JTAG PCH_JTAG_TMS
32.768KHZ_12.5PF_CM31532768DZFT
32.768KHZ_12.5PF_CM31532768DZFT
1
CH189
CH189
18P_0402_50V8J
18P_0402_50V8J
2
CRT_SWITCH_1 PCH_GPIO33PCH_GPIO33
RH59 51_0402_1 %@RH59 51_0402_1%@
RH44 210_0402_ 1%@RH 44 210_0402_1%@
RH45 210_0402_ 1%@RH 45 210_0402_1%@
RH46 210_0402_ 1%@RH 46 210_0402_1%@
RH145
RH145
1 2
10M_0402_5%
10M_0402_5%
Y3
Y3
1 2
RH148 20K_0402_5%RH148 20K_0402_5%
1 2
RH146 20K_0402_5%RH146 20K_0402_5%
+3VS
1 2
RH110 0_0402_5%RH110 0_0402_5%
ME_FLASH<46>
12
1 2
1 2
1 2
PCH_RTCX1
PCH_RTCX2
1
CH188
CH188
18P_0402_50V8J
18P_0402_50V8J
2
1U_0603_10V4Z
1U_0603_10V4Z
1U_0603_10V4Z
1U_0603_10V4Z
@
@
RH121
RH121
1 2
10K_0402_5%
10K_0402_5%
ME_FLASH HDA_SDOUT
RH109 R_short 0_0402_5%RH109 R_short 0_0402_5%
+3V_PCH
100_0402_1%
100_0402_1%
12
RH48
RH48
@
@
@
@
CH202
CH202
CH229
CH229
RH107 1K _0402_1%@RH107 1K_0402_1%@
RH317 10K_0402_5%@RH317 10K_0402_5%@
100_0402_1%
100_0402_1%
12
RH49
RH49
@
@
CMOS
1
2
1
2
1 2
1 2
100_0402_1%
100_0402_1%
12
RH47
RH47
@ JME1
@
HDA_SPKR<45>
HDA_SDIN0<45>
PCH_JTAG_TCK
PCH_JTAG_TDI
PCH_JTAG_TDO
12
JME1
SHORT PADS
SHORT PADS
12
JCMOS2
JCMOS2
SHORT PADS@
SHORT PADS@
12
RH1508 0_ 0402_5%
RH1508 0_ 0402_5%
T108 PAD@ T108 PAD@
T109 PAD@ T109 PAD@
+RTCVCC
PCH_RTCX1
PCH_RTCX2
PCH_SRTCRST#
SM_INTRUDER#
PCH_INTVRMEN
PCH_RTCRST#
HDA_BIT_CLK
HDA_SYNC
HDA_SPKR
HDA_RST#
HDA_SDIN0
PCH_GPIO33
PCH_GPIO13
1 2
PCH_TP25
@
@
1 2
RH149 1M_0402 _5%RH149 1M_0402 _5%
1 2
RH150 330K_0402_ 5%RH150 330K_0402_5%
INTVRMEN
H
：：：：
Integrated VRM e nable (Default)
*
L
：：：：
Integrated VRM d isable
UHA
UHA
B5
RTCX1
B4
RTCX2
B9
SRTCRST#
A8
INTRUDER#
G10
INTVRMEN
D9
RTCRST#
B25
HDA_BCLK
A22
HDA_SYNC
AL10
SPKR
C24
HDA_RST#
L22
HDA_SDI0
K22
HDA_SDI1
G22
HDA_SDI2
F22
HDA_SDI3
A24
HDA_SDO
B17
DOCKEN#/GPIO33
C22
HDA_DOCK_RST#/GPIO13
AB3
JTAG_TCK
AD1
JTAG_TMS
AE2
JTAG_TDI
AD3
JTAG_TDO
F8
TP25
C26
TP22
AB6
TP20
(INTVRMEN should always be pull high.)
HDA AUDIO
1 2
RH112
HDA_BITCLK_AUDIO<45>
HDA_SYNC_AUDIO<45>
HDA_RST_AUDIO#<45>
A A
HDA_SDOUT_AUDIO<45>
RH112
33_0402_5%
33_0402_5%
1 2
RH114
RH114
33_0402_5%
33_0402_5%
1 2
RH116
RH116
33_0402_5%
33_0402_5%
1 2
RH118
RH118
33_0402_5%
33_0402_5%
HDA_BIT_CLK
HDA_SYNC_R HDA_SYNC
HDA_RST#
HDA_SDOUT
JTAGRTC AZALIA
JTAGRTC AZALIA
LYNXPOINT_BGA695
LYNXPOINT_BGA695
SM_INTRUDER#
PCH_INTVRMEN
S
S
12
1 2
RH1353
RH1353
1M_0402_5%
1M_0402_5%
LPT_PCH_M_EDS
LPT_PCH_M_EDS
REV = 5
REV = 5
SATA
SATA
1 OF 11
1 OF 11
SATA_RXN_0
SATA_RXP_0
SATA_TXN_0
SATA_TXP_0
SATA_RXN_1
SATA_RXP_1
SATA_TXN_1
SATA_TXP_1
SATA_RXN_2
SATA_RXP_2
SATA_TXN_2
SATA_TXP_2
SATA_RXN_3
SATA_RXP_3
SATA_TXN_3
SATA_TXP_3
SATA_RXN4/PERN1
SATA_RXP4/PERP1
SATA_TXN4/PETN1
SATA_TXP4/PETP1
SATA_RXN5/PERN2
SATA_RXP5/PERP2
SATA_TXN5/PETN2
SATA_TXP5/PETP2
SATA_RCOMP
SATALED#
SATA0GP/GPIO21
SATA1GP/GPIO19
SATA_IREF
+3VS
TP9
TP8
*
+5VS +3V_PCH
QH10
QH10
G
G
2
BSS138_NL_SOT23-3
BSS138_NL_SOT23-3
13
D
D
@
@
RH1509 0_04 02_5%
RH1509 0_04 02_5%
*
BC8
BE8
AW8
AY8
BC10
BE10
AV10
AW10
BB9
SATA_PRX_DTX_N2
BD9
SATA_PRX_DTX_P2
AY13
SATA_PTX_DRX_N2
AW13
SATA_PTX_DRX_P2
BC12
BE12
AR13
AT13
BD13
SATA_PRX_DTX_N0
BB13
SATA_PRX_DTX_P0
AV15
SATA_PTX_DRX_N0
AW15
SATA_PTX_DRX_P0
BC14
SATA_PRX_DTX_N1
BE14
SATA_PRX_DTX_P1
AP15
AR15
SATA_PTX_DRX_P1
AY5
SATA_COMP
AP3
HDD_LED#
AT1
PCH_GPIO21
AU2
SATA_DET#
BD4
BA2
BB2
RH105 1K_0402_5%@R H105 1K_0402_5%@
HIGH= Enable ( N o Reboot )
LOW= Disable (De fault)
RH108 1K_0402_5%RH108 1K_0402_5%
RH119 10K _0402_5%RH119 10K_0402_5%
SATA_IREF
T161PAD @T161PAD @
T155PAD @T155PAD @
1 2
<Intel update spec>
If
RH1509 = stuff
RH1353 = @
QH10 = @
RH108 = @
12
12
CH186 0.01U_0402_16V7KCH186 0.01U_0402_16V7K
12
CH187 0.01U_0402_16V7KCH187 0.01U_0402_16V7K
@
@
12
CH184 0.01U_0402_16V7K
CH184 0.01U_0402_16V7K
12
CH185 0.01U_0402_16V7K
CH185 0.01U_0402_16V7K
@
@
12
CH273 0.01U_0402_16V7KCH273 0.01U_0402_16V7K
12
CH272 0.01U_0402_16V7KCH272 0.01U_0402_16V7K
12
12
RH410_0402_5% RH410_0402_5%
HDA_SPKR
+3VS
+1.5VS
HDA_SYNC
This signal has a weak internal pull-down
On Die PLL VR Se lect is supplie d by
1.5V when smaple d high (Default )
1.8V when sample d low
Needs to be pull ed High for Chi ef River platfro m
ODD
SATA_PTX_C_DRX_N2
SATA_PTX_C_DRX_P2
SSD
SATA_PTX_C_DRX_N0
SATA_PTX_C_DRX_P0
H
DD
SATA_PTX_C_DRX_N1SATA_PTX_DRX_N1
SATA_PTX_C_DRX_P1
RH120 10K _0402_5%RH120 10K_0402_5%
RH316 10K_0402_5 %RH316 10K_0402_5%
12
W=20mils W=20mils
+RTCBATT +RTCVCC
SATA_PRX_DTX_N2 <44>
SATA_PRX_DTX_P2 <44>
SATA_PTX_C_DRX_N2 <44>
SATA_PTX_C_DRX_P2 <44>
SATA_PTX_DRX_N0 <40>
SATA_PTX_DRX_P0 <40>
SATA_PRX_DTX_N0 <40>
SATA_PRX_DTX_P0 <40>
SATA_PTX_C_DRX_N0 <40>
SATA_PTX_C_DRX_P0 <40>
SATA_PRX_DTX_N1 <44>
SATA_PRX_DTX_P1 <44>
SATA_PTX_C_DRX_N1 <44>
SATA_PTX_C_DRX_P1 <44>
12
HDD_LED# <51>
SATA_DET# <40>
RH99
RH99
1K_0402_5%
1K_0402_5%
SATA Impedance Compensation
SATA_COMP
CAD note:
Place the resistor within 500 mils of the PCH. Avoid
routing next to clock pins.
+3V_PCH
RH106 1K_0402_5%@RH 106 1K_0402_5%@
Low = Disabled ( Default)
*
High = Enabled
[Flash Des criptor Securit y Overide]
+3VS
+3VS
12
1 2
12
+1.5VS
RH407.5K_0402_1% RH407.5K_0402_1%
1
CH179
CH179
1U_0603_10V4Z
1U_0603_10V4Z
2
HDA_SDOUT
Title
Title
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
5
4
3
2012/07/01
2012/07/01
2012/07/01
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2014/07/01
2014/07/01
2014/07/01
Title
PCH (1/9) SATA,HDA,SPI, LPC
PCH (1/9) SATA,HDA,SPI, LPC
PCH (1/9) SATA,HDA,SPI, LPC
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Date: Sheet of
Date: Sheet of
Date: Sheet
Wednesday, March 27, 2013
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
1
13 69
13 69
13 69
of
1.0
1.0
1.0
5
+3VS
1 2
RH850 2.2K_0402_5%RH850 2.2K_0402_5%
D D
C C
B B
1 2
RH851 2.2K_0402_5%RH851 2.2K_0402_5%
RH339150_04 02_1% RH339150_0402_1%
RH340150_04 02_1% RH340150_0402_1%
RH341150_04 02_1% RH341150_0402_1%
DGPU_HOLD_RST#<23,54>
12
PCH_CRT_B
12
PCH_CRT_G
12
PCH_CRT_R
NVDD_PWR_EN<54,63>
PCH_CRT_DDC_CLK
PCH_CRT_DDC_DAT
20120829 VA1
Add net for add CRT MUX
PCH_CRT_DDC_CLK<37>
PCH_CRT_DDC_DAT<37>
PCH_CRT_HSYNC<37>
PCH_CRT_VSYNC<37>
DGPU_PWR_EN<23,54,55>
DGPU_GC6_EN<27,54>
PCH_WL_OFF#<40>
PCH_CRT_B<37>
PCH_CRT_G<37>
PCH_CRT_R<37>
PCH_EDP_PWM<35>
PCH_ENBKL<35>
PCH_ENVDD<35>
1 2
RH1519 0_0402_5%RH1519 0_0402_5%
NVDD_PWR_EN NVDD_PWR_EN_R
RH1526 0_0402_5%RH1526 0_0402_5%
DGPU_PWR_EN DGPU_PWR_EN_R
DGPU_GC6_EN
PCH_CRT_B
PCH_CRT_G
PCH_CRT_R
PCH_CRT_DDC_CLK
PCH_CRT_DDC_DAT
PCH_CRT_HSYNC
PCH_CRT_VSYNC
12
RH302
RH302
649_0402_1%
649_0402_1%
PCH_DGPU_HOLD_RST#
1 2
1 2
RH1525 0_0402_5%RH1525 0_0402_5%
CRT_IREF
PCH_EDP_PWM
PCH_ENBKL
PCH_ENVDD
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCH_GPIO51
PCH_WL_OFF#
4
T45
U44
V45
M43
M45
N42
N44
U40
U39
N36
K36
G36
H20
L20
K17
M20
A12
B13
C12
C10
A10
AL6
VGA_BLUE
VGA_GREEN
VGA_RED
VGA_DDC_CLK
VGA_DDC_DATA
VGA_HSYNC
VGA_VSYNC
DAC_IREF
VGA_IRTN
EDP_BKLTCTL
EDP_BKLTEN
EDP_VDDEN
PIRQA#
PIRQB#
PIRQC#
PIRQD#
GPIO50
GPIO52
GPIO54
GPIO51
GPIO53
GPIO55
LPT_PCH_M_EV
LPT_PCH_M_EV
LVDSCRT
LVDSCRT
LYNXPOINT_BGA695
LYNXPOINT_BGA695
3
REV = 5UHE
REV = 5UHE
DDPB_CTRLCLK
DDPB_CTRLDATA
DDPC_CTRLCLK
DDPC_CTRLDATA
DDPD_CTRLCLK
DDPD_CTRLDATA
DDPB_AUXN
DDPC_AUXN
DISPLAY
DISPLAY
PCI
PCI
5 OF 11
5 OF 11
DDPD_AUXN
DDPB_AUXP
DDPC_AUXP
DDPD_AUXP
PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5
DDPB_HPD
DDPC_HPD
DDPD_HPD
PME#
PLTRST#
R40
R39
R35
R36
N40
N38
H45
K43
J42
H43
K45
J44
K40
K38
H39
G17
F17
L15
M15
AD10
Y11
DDPB_CLK
DDPB_DATA
TMDS_B_HPD
PCH_GPIO2
ODD_DA#_R
PIRQH#
PLT_RST#
20120829 VA1
Add net for add HDMI MUX
ODD_DA#_R <44>
1 2
RH1522 0_0402_5%RH1522 0_0402_5%
T114 PAD@ T114 PAD@
PLT_RST# <23 ,32,40,41,46>
DDPB_CLK <37>
DDPB_DATA <37>
TMDS_B_HPD <37>
CRT_DET#CRT_DET#_R
2
CRT_DET# <36>
PLT_RST#
RH301
RH301
100K_0402_5%
100K_0402_5%
1
+3VS
1 2
RH314 8.2K_0402_5%@RH314 8.2K_0402_5%@
1 2
RH318 8.2K_0402_5%@RH318 8.2K_0402_5%@
1 2
RH313 8.2K_0402_5%RH313 8.2K_0402_5%
1 2
RH312 8.2K_0402_5%RH312 8.2K_0402_5%
1 2
RH320 8.2K_0402_5%RH320 8.2K_0402_5%
1 2
RH311 8.2K_0402_5%RH311 8.2K_0402_5%
1 2
RH323 8.2K_0402_5%RH323 8.2K_0402_5%
1 2
RH324 8.2K_0402_5%RH324 8.2K_0402_5%
RH325 10K_0402_5%RH325 10K_0402_5%
@
@
1 2
RH310 8.2K_0402_5%
RH310 8.2K_0402_5%
1 2
RH315 8.2K_0402_5%
RH315 8.2K_0402_5%
@
@
RH308 1K_0402_5%@RH308 1K_0402_5%@
A16 swap overide Strap/Top-Block
Swap Override jumper
PCI_GNT3#
12
PPT EDS DOC#474146
PCH_GPIO51
DGPU_GC6_EN
PIRQH#
PCH_WL_OFF#
CRT_DET#_R
DGPU_HOLD_RST#
PCI_PIRQC#
12
12
Low = A16 swap
o
verride/Top-Block
Swap Override enabled
**High=Default
*
PCH_GPIO2
DGPU_PWR_EN
DGPU_GC6_EN
DGPU_HOLD_RST#
PCH_WL_OFF#
1 2
RH307 1K_0402_5%@RH307 1K_0402_5%@
Boot BIOS Strap
SATA_SLPD
(BBS_BIT0)
Boot BIOS Location
+3VS
RPH5
RPH5
18
27
36
45
8.2K_0804_8P4R_5%
8.2K_0804_8P4R_5%
PCI_PIRQD#
PCI_PIRQA#
ODD_DA#_R
PCI_PIRQB#
SWAP
PCH_GPIO51
BBS_BIT1
(GPIO51)
00 LPC
ODD_DA#_R
A A
5
4
For ESD
1
@
@
CC63
CC63
220P_0402_25V8J
220P_0402_25V8J
2
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
3
2012/07/01
2012/07/01
2012/07/01
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2014/07/01
2014/07/01
2014/07/01
0 1 Reserved (NAND)
1 0
*
Title
Title
Title
PCH (2/9) PCIE, SMBUS, CLK
PCH (2/9) PCIE, SMBUS, CLK
PCH (2/9) PCIE, SMBUS, CLK
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Date: Sheet of
Date: Sheet of
Date: Sheet of
Wednesday, March 27, 2013
PCI
11 SPI
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
1
14 69
14 69
14 69
1.0
1.0
1.0
5
4
3
2
1
+3V_PCH
D D
C C
B B
RH202 10K_0402_5%RH202 10K_0402_5%
+3VALW
RH222 200K_0402_5%RH222 200K_0402_5%
For Deep S3
A A
12
12
For Deep S3
SUSACK#<46>
+3VS
PCH_PWROK<46>
APWROK can be co nnect to
PWROK if iAMT d isable
EC_RSMRST#<46>
SIO_PWRBTN#_R<6>
SUSWARN#<46>
PBTN_OUT#<46>
AC_PRESENT<46>
+3VALW
+3V_PCH
RH319 10K_0 402_5%RH319 10K_0402_5%
SUSWARN#
PCH_AC_PRESENT_R
PM_DRAM_PWR GD<6>
12
DMI_CTX_PRX_N0<5>
DMI_CTX_PRX_N1<5>
DMI_CTX_PRX_N2<5>
DMI_CTX_PRX_N3<5>
DMI_CTX_PRX_P0<5>
DMI_CTX_PRX_P1<5>
DMI_CTX_PRX_P2<5>
DMI_CTX_PRX_P3<5>
DMI_CRX_PTX_N0<5>
DMI_CRX_PTX_N1<5>
DMI_CRX_PTX_N2<5>
DMI_CRX_PTX_N3<5>
DMI_CRX_PTX_P0<5>
DMI_CRX_PTX_P1<5>
DMI_CRX_PTX_P2<5>
DMI_CRX_PTX_P3<5>
+1.5VS
+1.5VS
RH1488 R_sh ort 0_0402_5%RH1488 R_short 0_0402_5%
RH188 10K_0402_5%RH188 10K_0402_5%
RH196
RH196
RH1511 R_sh ort 0_0402_5%RH1511 R_short 0_0402_5%
RH1489 R_short 0_0402_5%RH1489 R_short 0_0402_5%
RH1512 R_short 0_0402_5%RH1512 R_short 0_0402_5%
RH234 R_short 0_0402_5%RH234 R_short 0_0402_5%
RH246 8.2K_0402_5%RH246 8.2K_0402_5%
RH290 10K_0402_5%RH290 10K_0402_5%
RH43 0_0402_5%RH 43 0_0402_5%
RH204 7.5K_0402_1%RH204 7.5K_0402_1%
12
12
1 2
R_short 0_0402_5%
R_short 0_0402_5%
1 2
1 2
1 2
1 2
1 2
12
PCH_RSMRST#_R
T139 PAD@ T139 PAD@
T111 PAD@ T111 PAD@
1 2
RH1510
RH1510
R_short 0_0402_5%
R_short 0_0402_5%
T140 PAD@ T140 PAD@
EDP_SEL<38>
12
1 2
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
DMI_IREF
DMI_RCOMP
SUSACK#_R
SYS_RESET#
SYS_PWROK
PWROK
APWROK
PM_DRAM_PWR GD
PCH_RSMRST#_R
SUSWARN#_R
PCH_AC_PRESENT_R
PCH_GPIO72
RI#
VGATE<6,64>
AW22
AR20
AP17
AV20
AY22
AP20
AR17
AW20
BD21
BE20
BD17
BE18
BB21
BC20
BB17
BC18
BE16
AW17
AV17
AY17
R6
AM1
AD7
F10
AB7
H3
J2
J4
K1
E6
K7
N4
AB10
D2
CH1071
CH1071
0.1U_0402_16V4Z
0.1U_0402_16V4Z
VGATE
PCH_PWROK
MC74VHC1G08DFT2G SC70 5P
MC74VHC1G08DFT2G SC70 5P
UHB
UHB
DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3
DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3
DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3
DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3
DMI_IREF
TP12
TP7
DMI_RCOMP
SUSACK#
SYS_RESET#
SYS_PWROK
PWROK
APWROK
DRAMPWROK
RSMRST#
SUSWARN#/SUSPW RNACK/GPIO30
PWRBTN#
ACPRESENT/GPIO31
BATLOW#/GPIO72
RI#
TP21
SLP_WLAN#/GPIO29
LYNXPOINT_BGA695
LYNXPOINT_BGA695
1
2
2
1
LPT_PCH_M_EDS
LPT_PCH_M_EDS
+3VS
B
A
UH7
UH7
DMI
DMI
System Power
System Power
Management
Management
5
P
4
Y
12
G
3
REV = 5
REV = 5
4 OF 11
4 OF 11
RH182
@ RH182
@
100K_0402_1%
100K_0402_1%
FDI
FDI
SUS_STAT#/GPIO61
SUSCLK/GPIO62
SLP_S5#/GPIO63
FDI_RXN_0
FDI_RXN_1
FDI_RXP_0
FDI_RXP_1
TP16
TP15
TP10
FDI_CSYNC
FDI_INT
FDI_IREF
TP17
TP13
FDI_RCOMP
DSWVRMEN
DPWROK
WAKE#
CLKRUN#
SLP_S4#
SLP_S3#
SLP_A#
SLP_SUS#
PMSYNCH
SLP_LAN#
SYS_PWROK <6>
PCH_PWROK
12
RH203
RH203
10K_0402_5%
10K_0402_5%
For Intel checklist V0.5
AJ35
FDI_CTX_PRX_N0
AL35
FDI_CTX_PRX_N1
AJ36
FDI_CTX_PRX_P0
AL36
FDI_CTX_PRX_P1
AV43
AY45
TP5
AV45
AW44
AL39
FDI_CSYNC
AL40
FDI_INT
AT45
FDI_IREF
AU42
AU44
AR44
FDI_RCOMP
C8
DSWODVREN
L13
PCH_DPWROK_R DPWROK_E C
K3
AN7
PM_CLKRUN#
U7
SUS_STAT#
Y6
SUSCLK
Y7
PM_SLP_S5#
C6
PM_SLP_S4#
H1
PM_SLP_S3#
F3
Can be left NC w hen IAMT is not support on the platfrom
F1
PM_SLP_SUS#_R
AY3
H_PM_SYNC
G5
PCH_GPIO29
Can be left NC i f no use integr ated LAN.
10/06 Test point request
RH292 R_short 0_0402_5%RH292 R_short 0_0402_5%
RH294 R_short 0_0402_5%RH294 R_short 0_0402_5%
RH1456 R_sh ort 0_0402_5%RH1456 R_short 0_0402_5%
FDI_CTX_PRX_N0 <8>
FDI_CTX_PRX_N1 <8>
FDI_CTX_PRX_P0 <8>
FDI_CTX_PRX_P1 <8>
T144PAD @T144PAD @
T141PAD @T141PAD @
T147PAD @T147PAD @
T148PAD @T148PAD @
FDI_CSYNC <5>
FDI_INT <5>
12
RH420_0402_5% RH420_0402_5%
T145PAD @T145PAD @
T146PAD @T146PAD @
12
RH2067.5K_0402_1% RH2067.5K_0402_1%
1 2
1 2
T66PAD T66PAD
T67PAD T67PAD
T68PAD T68PAD
PM_SLP_S4# <46>
PM_SLP_S3# <46>
H_PM_SYNC <6>
T110PAD T110PAD
+1.5VS
+1.5VS
12
DSWODVREN - On D ie DSW VR Enabl e
*
H
：：：：
Enable
：：：：
Disable
L
PCIE_WAKE#WAKE#
DSWODVREN
PCH_DPWROK_R
For Intel checklist V0.6
PM_CLKRUN#
DPWROK_EC <46>
PCIE_WAKE# <19,40,41>
PM_SLP_SUS# <46,55>
WAKE#
RH187 10K_0402_5 %RH187 10K_0402_5%
+RTCVCC
12
RH189
RH189
330K_0402_5%
330K_0402_5%
12
RH291
RH291
330K_0402_5%@
330K_0402_5%@
12
RH184
RH184
100K_0402_1%
100K_0402_1%
+3VS
12
RH1858.2K_0402 _5% RH1858.2K_0402_5%
For Deep S3
note need connect to GPIO27
For Deep S3
Add one to +3VALW next Rev.
1 2
+3V_PCH
Title
Title
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
3
2012/07/01
2012/07/01
2012/07/01
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2014/07/01
2014/07/01
2014/07/01
Title
PCH (3/9) PCIE, SMBUS, CLK
PCH (3/9) PCIE, SMBUS, CLK
PCH (3/9) PCIE, SMBUS, CLK
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Date: Sheet of
Date: Sheet of
Date: Sheet of
Wednesday, March 27, 2013
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
1
15 69
15 69
15 69
1.0
1.0
1.0
5
D D
PCH_GPIO73
PCH_GPIO18
CLKREQ_TV#_R
LAN
WLAN
C C
CLK_CPU_ITP#<6>
CLK_CPU_ITP<6>
CLK_PCI_EC<46>
CLK_PCI_DB<40>
RH253 22_0402_5%RH253 22_0402_5%
RH174 22_0402_5%
RH174 22_0402_5%
CLK_PCIE_LAN#<41>
CLK_PCIE_LAN<41>
CLKREQ_LAN#<41>
CLK_PCIE_WLAN#<40>
CLK_PCIE_WLAN<40>
WLAN_CLKREQ1#<40>
RH280 0_0402_5%RH280 0_0402_5%
RH281 0_0402_5%RH281 0_0402_5%
1 2
RH1514 22_0402 _5%RH1514 22_0402_5%
12
12
12
@
@
12
CLK_PCIE_LAN#
CLK_PCIE_LAN
CLKREQ_LAN#
CLK_PCIE_WLAN#
CLK_PCIE_WLAN
WLAN_CLKREQ1#
PCH_GPIO44
PCH_GPIO45
PCH_GPIO46
CLK_BCLK_ITP#
CLK_BCLK_ITP
CLK_PCI_EC_R
CLK_PCI_DB_R
PCI_LOOPBACKOUTCLK_PCI_LOOPBACK
4
UHC
UHC
Y43
CLKOUT_PCIE_N_0
Y45
CLKOUT_PCIE_P_0
AB1
PCIECLKRQ0#/GPIO73
AA44
CLKOUT_PCIE_N_1
AA42
CLKOUT_PCIE_P_1
AF1
PCIECLKRQ1#/GPIO18
AB43
CLKOUT_PCIE_N_2
AB45
CLKOUT_PCIE_P_2
AF3
PCIECLKRQ2#/GPIO20/SMI#
AD43
CLKOUT_PCIE_N_3
AD45
CLKOUT_PCIE_P_3
T3
PCIECLKRQ3#/GPIO25
AF43
CLKOUT_PCIE_N_4
AF45
CLKOUT_PCIE_P_4
V3
PCIECLKRQ4#/GPIO26
AE44
CLKOUT_PCIE_N5
AE42
CLKOUT_PCIE_P_5
AA2
PCIECLKRQ5#/GPIO44
AB40
CLKOUT_PCIE_N_6
AB39
CLKOUT_PCIE_P_6
AE4
PCIECLKRQ6#/GPIO45
AJ44
CLKOUT_PCIE_N_7
AJ42
CLKOUT_PCIE_P_7
Y3
PCIECLKRQ7#/GPIO46
AH43
CLKOUT_ITPXDP
AH45
CLKOUT_ITPXDP_P
D44
CLKOUT_33MHZ0
E44
CLKOUT_33MHZ1
B42
CLKOUT_33MHZ2
F41
CLKOUT_33MHZ3
A40
CLKOUT_33MHZ4
CLOCK SIGNAL
CLOCK SIGNAL
LPT_PCH_M_EDS
LPT_PCH_M_EDS
LYNXPOINT_BGA695
LYNXPOINT_BGA695
2 OF 11
2 OF 11
REV = 5
REV = 5
CLKOUT_PEG_A
CLKOUT_PEG_A_P
PEGA_CLKRQ#/GPIO47
CLKOUT_PEG_B
CLKOUT_PEG_B_P
PEGB_CLKRQ#/GPIO56
CLKOUT_DMI
CLKOUT_DMI_P
CLKOUT_DP
CLKOUT_DP_P
CLKOUT_DPNS
CLKOUT_DPNS_P
CLKIN_DMI
CLKIN_DMI_P
CLKIN_GND
CLKIN_GND_P
CLKIN_DOT96N
CLKIN_DOT96P
CLKIN_SATA
CLKIN_SATA_P
REFCLK14IN
CLKIN_33MHZLOOPBACK
XTAL25_IN
XTAL25_OUT
CLKOUTFLEX0/GPIO64
CLKOUTFLEX1/GPIO65
CLKOUTFLEX2/GPIO66
CLKOUTFLEX3/GPIO67
ICLK_IREF
DIFFCLK_BIASREF
TP19
TP18
3
AB35
CLK_PCIE_VGA#
AB36
CLK_PCIE_VGA
AF6
CLK_REQ_GPU#_R
Y39
CLK_PCIE_2VGA#
Y38
CLK_PCIE_2VGA
U4
CLK2_REQ_GPU#_R
AF39
CLK_CPU_DMI#
AF40
CLK_CPU_DMI
AJ40
CLK_CPU_SSC_DPLL#
AJ39
CLK_CPU_SSC_DPLL
AF35
CLK_CPU_DPLL#
AF36
CLK_CPU_DPLL
AY24
CLK_BUF_CPU_DMI#
AW24
CLK_BUF_CPU_DMI
AR24
CLKIN_DMI2#
AT24
CLKIN_DMI2
H33
CLK_BUF_DREF_96M#
G33
CLK_BUF_DREF_96M
BE6
CLK_BUF_PCIE_SATA#
BC6
CLK_BUF_PCIE_SATA
F45
CLK_BUF_ICH_14M
D17
CLK_PCI_LOOPBACK
AL44
XTAL25_IN
AM43
XTAL25_OUT
C40
RH1505
RH1505
F38
F36
S_DGPU_RST_R
F39
PCH_GPIO67
AM45
ICLK_IREF
AD39
AD38
AN44
PCH_CLK_BIASREF
1 2
CLK_PCIE_VGA# <23>
CLK_PCIE_VGA <23>
1 2
RH1513 10K_0402_5%RH1513 10K_0402_5%
CLK_PCIE_2VGA# <32>
CLK_PCIE_2VGA <32>
1 2
RH170 10K_0402_5%RH170 10K_0402_5%
CLK_CPU_DMI# <6>
CLK_CPU_DMI <6>
CLK_CPU_SSC_DPLL# <6>
CLK_CPU_SSC_DPLL <6>
CLK_CPU_DPLL# <6>
CLK_CPU_DPLL <6>
1 2
RH162 10K_0402_5%RH162 10K_0402_5%
1 2
RH163 10K_0402_5%RH163 10K_0402_5%
1 2
RH164 10K_0402_5%RH164 10K_0402_5%
1 2
RH166 10K_0402_5%RH166 10K_0402_5%
1 2
RH167 10K_0402_5%RH167 10K_0402_5%
EDP_AUX_SEL <38>
R_short 0_0402_5%
R_short 0_0402_5%
PCH_GPIO67 < 19>
1 2
T149PAD @T149PAD @
T150PAD @T150PAD @
1 2
S_DGPU_PWROK <32,54>
RH183 10K_0402_5%RH183 10K_0402_5%
RH1504
RH1504
RH540_0402_5% R H540_0402_5%
RH2087.5K_0402_1% RH2087.5K_0402_1%
CLKIN_DMI2#
CLKIN_DMI2
CLK_BUF_CPU_DMI#
CLK_BUF_CPU_DMI
1 2
+1.5VS
+1.05V_+1.5V_RUN
2
+3V_PCH
+3V_PCH
12
R_short 0_0402_5%
R_short 0_0402_5%
CLK_REQ_GPU#_R <23>
CLK2_REQ_GPU#_R <32>
RPH1
RPH1
4 5
3 6
2 7
1 8
10K_0804_8P4R_5%
10K_0804_8P4R_5%
+3VS
S_DGPU_RST <32,54>
BIOS Request SKU ID
GPIO64, 65 that only for GC6
1
. GPIO64 : S_DGPU_GC6_EN
2. GPIO65 : S_DGPU_PWROK
1
2nd VGA
B B
A A
+3V_PCH
RH152 10K_0402_5 %RH152 10K_0402_5%
RH168 10K_0402_5 %RH168 10K_0402_5%
RH165 10K_0402_5 %RH165 10K_0402_5%
RH147 10K_0402_5 %RH147 10K_0402_5%
RH172 10K_0402_5 %RH172 10K_0402_5%
RH177 10K_0402_5 %RH177 10K_0402_5%
+3VS
RH158 10K_0402_5 %RH158 10K_0402_5%
RH329 10K_0402_5 %RH329 10K_0402_5%
5
12
12
12
12
12
12
12
12
PCH_GPIO73
CLKREQ_LAN#
WLAN_CLKREQ1#
PCH_GPIO44
PCH_GPIO45
PCH_GPIO46
PCH_GPIO18
CLKREQ_TV#_R
Change C196, C19 7 value of Cap
from 33pF to 10p F for TXC recom mend
XTAL25_IN
XTAL25_OUT
R
eserve for EMI please close to
PCH
12P_0402_50V8F
12P_0402_50V8F
CH199
@CH199
12
@
22P_0402_50V8J
22P_0402_50V8J
3
1 2
2012/07/01
2012/07/01
2012/07/01
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2014/07/01
2014/07/01
2014/07/01
RH176
@RH176
@
33_0402_5%
CLK_PCI_LOOPBACK
4
33_0402_5%
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
CH196
CH196
1
2
RH169
RH169
1 2
1M_0402_5%
1M_0402_5%
Y2
Y2
1
1
GND
2
25MHZ_10PF_7V25000014
25MHZ_10PF_7V25000014
Title
Title
Title
PCH (3/9) DMI, FDI, PM
PCH (3/9) DMI, FDI, PM
PCH (3/9) DMI, FDI, PM
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet
3
3
GND
4
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Wednesday, March 27, 2013
1
2
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
CH197
CH197
12P_0402_50V8F
12P_0402_50V8F
1
of
16 69
16 69
16 69
1.0
1.0
1.0
5
4
3
2
1
D D
UHD
UHD
EC and Mini card debug port
A20
LPC_FRAME#
SPI_CLK_PCH
SPI_SB_CS0#
SPI_CS1#
SPI_SO_R
12
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
C20
A18
C18
B21
D21
G20
AL11
AJ11
AJ7
AL7
AJ10
AH1
AH3
AJ4
AJ2
LAD_0
LAD_1
LAD_2
LAD_3
LFRAME#
LDRQ0#
LDRQ1#/GPIO23
SERIRQ
SPI_CLK
SPI_CS0#
SPI_CS1#
SPI_CS2#
SPI_MOSI
SPI_MISO
SPI_IO2
SPI_IO3
LPC_AD0<40,46>
LPC_AD1<40,46>
LPC_AD2<40,46>
LPC_AD3<40,46>
LPC_FRAME#<40,46>
SERIRQ<46>
+3VS
SPI_CLK_PCH_0
SPI_CLK_PCH_1_R
SPI_SB_CS0#_R
SPI_CS1#_R
C C
B B
SPI_SI_R
SPI_SI_R1 SPI_SI
SPI_SO_L
SPI_SO_L1
SPI_CS1#_R<46>
SPI_SI_R1<46>
SPI_SO_L1<46>
SPI_CLK_PCH_1<46>
1 2
1 2
RH331 33_ 0402_5%RH331 33_0402_5%
1 2
RH332 33_ 0402_5%RH332 33_0402_5%
1 2
RH133 33_ 0402_5%RH133 33_0402_5%
1 2
RH205 33_ 0402_5%RH205 33_0402_5%
RH131 33_ 0402_5%RH131 33_0402_5%
RH334 33_ 0402_5%RH334 33_0402_5%
SPI_CS1#_R
SPI_SI_R1
SPI_SO_L1
SPI_CLK_PCH_1 SPI_CLK_PCH_1_R
SERIRQ
RH10410K_0402_5% RH10410K_0402_5%
12
RH130 R_short 0_0402_5%RH130 R_short 0_0402_5%
12
RH333 R_short 0_0402_5%RH333 R_short 0_0402_5%
12
12
RH338 0_0402_5%
RH338 0_0402_5%
@
@
LPT_PCH_M_EDS
LPT_PCH_M_EDS
SPILPC
SPILPC
NXPOINT_BGA695
NXPOINT_BGA695
LY
LY
SMBus
SMBus
C-Link
C-Link
Thermal
Thermal
3 OF 11 REV = 5
3 OF 11 REV = 5
SMBALERT#/GPIO11
SMBCLK
SMBDATA
SML0ALERT#/GPIO60
SML0CLK
SML0DATA
SML1ALERT#/PCHHOT#/GPIO74
SML1CLK/GPIO58
SML1DATA/GPIO75
CL_CLK
CL_DATA
CL_RST#
TD_IREF
N7
PCH_GPIO11
R10
PCH_SMBCLK
U11
PCH_SMBDATA
N8
U8
SML0CLK
R7
SML0DATA
H6
PCH_HOT#
K6
SML1CLK
N11
SML1DATA
AF11
AF10
AF7
BA45
TP1
BC45
TP2
BE43
TP4
BE44
TP3
AY43
PCH_TD_IREF
RH322 8.2K_0402_1%RH322 8.2K_0402_1%
DRAMRST_CNTRL_PC H <6>
T118PAD @T118PAD @
T119PAD @T119PAD @
T120PAD @T120PAD @
T121PAD @T121PAD @
1 2
+3V_PCH
PCH_GPIO11
DRAMRST_CNTRL_PC H
SML0CLK
SML0DATA
PCH_HOT#
+3VS
RH136
RH136
1 2
2.2K_0402_5%
2.2K_0402_5%
RH135
RH135
1 2
2.2K_0402_5%
2.2K_0402_5%
PCH_SMBCLK
PCH_SMBDATA SMB_DATA_S3
5
G
G
3 4
D
D
2N7002KDWH
Vth= min 1V, max 2.5V
2
ESD 2KV
G
G
6 1
D
D
S
S
QH162A
QH162A
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
QH162B
QH162B
S
S
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
RH335 10K_0402_5%RH335 10K_0402_5%
1 2
RH336 10K_0402_5%RH336 10K_0402_5%
RH337
RH337
1 2
SMB_CLK_S3
RH134
RH134
12
10K_0402_5%
10K_0402_5%
12
10K_0402_5%
10K_0402_5%
RH140
RH140
12
10K_0402_5%
10K_0402_5%
VGA, EC, Thermal Sensor
RH137
RH137
12
RH138
RH138
12
+3V_PCH
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
SMB_CLK_S3 <11,12,40,47>
SMB_DATA_S3 <11,12,40,47>
+3VS
D
G
G
EC_SMB_CK2
S
S
QH61A
QH61A
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
EC_SMB_DA2
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Wednesday, March 27, 2013
IMM1, DIMM2, Mini CARD, TP
EC_SMB_CK2 <23,32,34,36,43,46>
EC_SMB_DA2 <23,32,34,36,43,46>
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
1
17 69
17 69
17 69
1.0
1.0
1.0
32Mb Flash ROM1
1 2
1 2
UH53
UH53
1
/CS
2
DO
3
/WP
4
GND
W25Q32FVSSIQ_SO8
W25Q32FVSSIQ_SO8
For EMI
VCC
/HOLD
CLK
DIO
RH115 10_0402_5%
RH115 10_0402_5%
1 2
@
@
1
CH200
@ CH200
@
2
SPI_WP#_1
SPI_HOLD#_1
8
7
6
5
SPI_CLK_PCH_1_R
SPI_SI_R1
10P_0402_50V8J
10P_0402_50V8J
1
CH275
CH275
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
3
2012/07/01
2012/07/01
2012/07/01
+3V_PCH +3VS
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
RH141
RH141
1 2
RH142
RH142
1 2
SML1CLK
SML1DATA
2
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
2014/07/01
2014/07/01
2014/07/01
2
6 1
D
D
5
G
G
3 4
QH61B
QH61B
D
D
S
S
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
Title
Title
Title
PCH (4/9) LVDS, CRT,DP,HDMI
PCH (4/9) LVDS, CRT,DP,HDMI
PCH (4/9) LVDS, CRT,DP,HDMI
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
For EMI
SPI_CLK_PCH_0 SPI_CLK_PCH_1_R
+3VS +3VS
SPI_SB_CS0#_R
SPI_SO_L
SPI_WP#
A A
6Mb Flash ROM
1 2
RH127 3.3K_0402_5%RH127 3.3K_0402_5%
1 2
RH129 3.3K_0402_5%RH129 3.3K_0402_5%
UH52
UH52
1
CS#
2
DO
3
WP#
4
GND
W25Q16DVSSIQ_SO8
W25Q16DVSSIQ_SO8
5
VCC
HOLD#
CLK
8
7
6
5
DI
SPI_WP#
SPI_HOLD#
SPI_HOLD#
SPI_CLK_PCH_0
SPI_SI_R
RH111 10_0402_5%
RH111 10_0402_5%
1 2
@
@
1
CH190
@ CH190
@
2
10P_0402_50V8J
10P_0402_50V8J
+3VS +3VS
1
CH191
CH191
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
4
RH330 3.3K_0402_5%RH330 3.3K_0402_5%
RH257 3.3K_0402_5%RH257 3.3K_0402_5%
SPI_CS1#_R
SPI_SO_L1 SPI_HOLD#_1
SPI_WP#_1
5
D D
PCIE_PRX_DTX_N4<41>
C C
LAN
WLAN
B B
PCIE_PRX_DTX_P4<41>
PCIE_PTX_C_DRX_N4<41>
PCIE_PTX_C_DRX_P4<41>
PCIE_PRX_DTX_N5<40>
PCIE_PRX_DTX_P5<40>
PCIE_PTX_C_DRX_N5<40>
PCIE_PTX_C_DRX_P5<40>
1 2
CH192 0.1U_0402_10V7KCH192 0.1U_0402_10V7K
1 2
CH193 0.1U_0402_10V7KCH193 0.1U_0402_10V7K
1 2
CH194 0.1U_0402_10V7KCH194 0.1U_0402_10V7K
1 2
CH195 0.1U_0402_10V7KCH195 0.1U_0402_10V7K
+1.5VS
+1.5VS
4
T124 PAD@ T124 PAD@
T125 PAD@ T125 PAD@
USB30_RX_N5
USB30_RX_P5
USB30_TX_N5
USB30_TX_P5
USB30_RX_N6
USB30_RX_P6
USB30_TX_N6
USB30_TX_P6
PCIE_PRX_DTX_N4
PCIE_PRX_DTX_P4
PCIE_PTX_DRX_N4
PCIE_PTX_DRX_P4
PCIE_PRX_DTX_N5
PCIE_PRX_DTX_P5
PCIE_PTX_DRX_N5
PCIE_PTX_DRX_P5
PCH_PCIE_IREF
PCH_PCIE_RCOMP
USB30_RX_N5<49>
USB30_RX_P5<49>
USB30_TX_N5<49>
USB30_TX_P5<49>
USB30_RX_N6<48>
USB30_RX_P6<48>
USB30_TX_N6<48>
USB30_TX_P6<48>
1 2
RH51 0_0402_5%RH51 0_0402_5%
1 2
RH210 7.5K_0402 _1%RH210 7.5K_0402_1%
AW31
AY31
BE32
BC32
AT31
AR31
BD33
BB33
AW33
AY33
BE34
BC34
AT33
AR33
BE36
BC36
AW36
AV36
BD37
BB37
AY38
AW38
BC38
BE38
AT40
AT39
BE40
BC40
AN38
AN39
BD42
BD41
BE30
BC30
BB29
BD29
UHI
UHI
PERN1/USB3RN3
PERP1/USB3RP3
PETN1/USB3TN3
PETP1/USB3TP3
PERN2/USB3RN4
PERP2/USB3RP4
PETN2/USB3TN4
PETP2/USB3TP4
PERN_3
PERP_3
PETN_3
PETP_3
PERN_4
PERP_4
PETN_4
PETP_4
PERN_5
PERP_5
PETN_5
PETP_5
PERN_6
PERP_6
PETN_6
PETP_6
PERN_7
PERP_7
PETN_7
PETP_7
PERN_8
PERP_8
PETN_8
PETP_8
PCIE_IREF
TP11
TP6
PCIE_RCOMP
LY
LY
NXPOINT_BGA695
NXPOINT_BGA695
3
LPT_PCH_M_EDS
LPT_PCH_M_EDS
PCIe
PCIe
9 OF 11 REV = 5
9 OF 11 REV = 5
2
B37
TP24
TP23
D37
A38
C38
A36
C36
A34
C34
B33
D33
F31
G31
K31
L31
G29
H29
A32
C32
A30
C30
B29
D29
A28
C28
G26
F26
F24
G24
AR26
AP26
BE24
BD23
AW26
AV26
BD25
BC24
AW29
AV29
BE26
BC26
AR29
AP29
BD27
BE28
K24
K26
M33
L33
P3
V1
U2
P1
M3
T1
N2
M1
USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4
Some PCH config not support USB port 6 & 7.
USB20_N8
USB20_P8
USB20_N10
USB20_P10
USB30_RX_N2
USB30_RX_P2
USB30_TX_N2
USB30_TX_P2
USBRBIAS
Within 500 mils
USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
USB_OC4#
USB_OC5#
USB_OC6#
USB_OC7#
USB2N0
USB2P0
USB2N1
USB2P1
USB2N2
USB2P2
USB2N3
USB2P3
USB2N4
USB2P4
USB2N5
USB2P5
USB2N6
USB2P6
USB2N7
USB2P7
USB2N8
USB2P8
USB2N9
USB2P9
USB2N10
USB2P10
USB2N11
USB2P11
USB2N12
USB
USB
USB2P12
USB2N13
USB2P13
USB3RN1
USB3RP1
USB3TN1
USB3TP1
USB3RN2
USB3RP2
USB3TN2
USB3TP2
USB3RN5
USB3RP5
USB3TN5
USB3TP5
USB3RN6
USB3RP6
USB3TN6
USB3TP6
USBRBIAS#
USBRBIAS
OC0#/GPIO59
OC1#/GPIO40
OC2#/GPIO41
OC3#/GPIO42
OC4#/GPIO43
OC5#/GPIO9
OC6#/GPIO10
OC7#/GPIO14
USB20_N0 <35>
USB20_P0 <35>
USB20_N1 <50>
USB20_P1 <50>
USB20_N2 <49>
USB20_P2 <49>
USB20_N3 <49>
USB20_P3 <49>
USB20_N4 <48>
USB20_P4 <48>
USB20_N8 <50>
USB20_P8 <50>
USB20_N10 <40>
USB20_P10 <40>
USB30_RX_N2 <49>
USB30_RX_P2 <49>
USB30_TX_N2 <49>
USB30_TX_P2 <49>
RH218
RH218
1 2
22.6_0402_1%
22.6_0402_1%
T122PAD @T122PAD @
T123PAD @T123PAD @
USB_OC0# <50>
USB_OC1# <49>
Camera
RIGHT USB 1 (SUB/B)
LEFT USB
LEFT USB
Card reader
Touch panel
T180PAD @T180PAD @
T181PAD @T181PAD @
Debug port, rese rved test point
WLAN
USB3.0
Port1
USB_OC5#
USB_OC2#
USB_OC7#
USB_OC0#
USB_OC6#
USB_OC1#
USB_OC4#
USB_OC3#
LEFT USB
LEFT USB
Card reader
Port2
Port5
Port6
RPH3
RPH3
4 5
3 6
2 7
1 8
10K_1206_8P4R_5%
10K_1206_8P4R_5%
RPH4
RPH4
4 5
3 6
2 7
1 8
10K_1206_8P4R_5%
10K_1206_8P4R_5%
1
+3V_PCH
A A
Title
Title
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
3
2012/07/01
2012/07/01
2012/07/01
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2014/07/01
2014/07/01
2014/07/01
Title
PCH (5/9) PCI, USB
PCH (5/9) PCI, USB
PCH (5/9) PCI, USB
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Date: Sheet of
Date: Sheet of
Date: Sheet of
Wednesday, March 27, 2013
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
1
18 69
18 69
18 69
1.0
1.0
1.0
5
4
3
2
1
SKU ID
PCH_GPIO67<16>
PCH_GPIO38
1 1
X
X X
12
RH25510K_0402 _5% RH25510K_0402_5%
12
KBRST#
RH22610K_0402 _5% RH22610K_0402_5%
PCH_GPIO67
PCH_GPIO38
PCH_GPIO67
PCH_GPIO70
12
RH151710K_0402_5% RH151710K_0402_5%
X
RH711
RH711
RH708
RH708
@
@
1 2
RH712
RH712
RH709
RH709
@
@
1 2
S_DGPU_PWR_EN
@
@
1 2
10K_0402_5%
10K_0402_5%
1 2
10K_0402_5%
10K_0402_5%
PCH_GPIO70
X
X
X
X
0
1
+3VS
RH704
RH704
1 2
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
RH706
RH706
@
@
1 2
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
CMOS_ON#<35>
GC6_EVENT#<23,54>
+3VS
D D
+3VS
+3V_PCH
EC_LID_OUT#<46>
waiting check
waiting check
DGPU_PWROK<27,54,62,63>
PCH_BT_DISABLE#<40>
PCIE_WAKE#<15,40,41>
PCH_BT_ON#<40>
waiting check
C C
RH252
RH252
+3V_PCH
GPIO28
O
n-Die PLL Voltage Regulator
This signal has a weak internal pull up
*
B B
PCH_GPIO27 (Have internal Pull-High)
*
H
Low: VCCVRM VR Disable
1 2
10K_0402_5%
10K_0402_5%
S_DGPU_PWR_EN<32,54,55>
S_NVDD_PWR_EN<32,54>
H：On-Die voltage r egulator enable
L：On-Die PLL Volta ge Regulator di sable
1 2
RH240 1K_0402_5%@RH240 1K_0402_5%@
igh: VCCVRM VR Enable
waiting
check
SLAVE_PRESENT#
RH233 10K_0402_5%RH233 10K_0402_5%
RH227 10K_0402_5%RH227 10K_0402_5%
RH228 10K_0402_5%RH228 10K_0402_5%
RH229 10K_0402_5%@RH229 10K_0402_5%@
RH230 10K_0402_5%RH230 10K_0402_5%
RH232 10K_0402_1%@RH232 10K_0402_1%@
+3VS
RH238 10K_0402_5%RH238 10K_0402_5%
+3VS
RH241 10K_0402_5 %RH241 10K_0402_5%
+3V_PCH
+3VS
RH243 10K_0402_5%
RH243 10K_0402_5%
+3VS
+3VS
RH247 10K_0402_5%RH247 10K_0402_5%
RH248 10K_0402_5%RH248 10K_0402_5%
RH249 0_0402_5%RH249 0_0402_5%
RH251 0_0402_5%RH251 0_0402_5%
PCH_GPIO28
CMOS_ON# PCH_GPIO68
1 2
1 2
1 2
1 2
1 2
1 2
1 2
@
@
12
1 2
1 2
RH242
RH242
1 2
@
@
1 2
1 2
SLAVE_PRESENT#<32>
12
Reseve for SKU ID
12
RH154 0_0402_5%RH154 0_0402_5%
1 2
RH156 0_0402_5%RH156 0_0402_5%
@
@
12
RH2250_0402_5%
RH2250_0402_5%
EC_SCI#<46>
EC_SMI#<46>
12
RH2310_0402_5% RH2310_0402_5%
ODD_EN<44>
RH2240_0402_5%
RH2240_0402_5%
10K_0402_5%
10K_0402_5%
ODD_DETECT#<44>
1 2
PCH_BT_DISABLE#
PCH_GPIO49
PCH_S_DGPU_PWR_ EN
PCH_S_NVDD_PW R_EN
TP_VSS_NCTF
HDSW_DDC<37>
HDSW_MAIN<37>
GC6_EVENT#_R
PCH_GPIO1
PCH_GPIO6
EC_SCI#
EC_SMI#
PCH_GPIO12
EC_LID_OUT#
PCH_GPIO16
PCH_DGPU_PWROK
ODD_EN
DS3_WAKE#_R
PCH_GPIO28
PCH_BT_ON#
PCH_GPIO35
ODD_DETECT#
PCH_GPIO37
PCH_GPIO38
PCH_GPIO39
PCH_GPIO48
SLAVE_PRESENT#
PCH_GPIO68
PCH_GPIO70
UHF
UHF
AT8
BMBUSY#/GPIO0
F13
TACH1/GPIO1
A14
TACH2/GPIO6
G15
TACH3/GPIO7
Y1
GPIO8
K13
LAN_PHY_PWR_CTRL/GPIO12
AB11
GPIO15
AN2
SATA4GP/GPIO16
C14
TACH0/GPIO17
BB4
SCLOCK/GPIO22
Y10
GPIO24
R11
GPIO27
AD11
GPIO28
AN6
GPIO34
AP1
GPIO35/NMI#
AT3
SATA2GP/GPIO36
AK1
SATA3GP/GPIO37
AT7
SLOAD/GPIO38
AM3
SDATAOUT0/GPIO39
AN4
SDATAOUT1/GPIO48
AK3
SATA5GP/GPIO49
U12
GPIO57
C16
TACH4/GPIO68
D13
TACH5/GPIO69
G13
TACH6/GPIO70
H15
TACH7/GPIO71
BE41
VSS
BE5
VSS
C45
VSS
A5
VSS
0_0402_5%
0_0402_5%
1 2
RH161
RH161
0_0402_5%
0_0402_5%
1 2
RH171
RH171
LPT_PCH_M_EDS
LPT_PCH_M_EDS
L
L
NXPOINT_BGA695
NXPOINT_BGA695
Y
Y
PCH_GPIO39
PCH_GPIO48
GPIO
GPIO
NCTF
NCTF
6 OF 11 REV = 5
6 OF 11 REV = 5
CPU/Misc
CPU/Misc
RCIN#
PROCPWRGD
THRMTRIP#
PLTRST_PROC#
AN10
TP14
AY1
PECI
AT6
KBRST#
AV3
AV1
PCH_THRMTRIP#_R H_THRMTRIP#
AU4
N10
VSS
A2
VSS
A41
VSS
A43
VSS
A44
VSS
B1
VSS
B2
VSS
B44
VSS
B45
VSS
BA1
VSS
BC1
VSS
BD1
VSS
BD2
VSS
BD44
VSS
BD45
VSS
BE2
VSS
BE3
VSS
D1
VSS
E1
VSS
E45
VSS
A4
VSS
RH239 390_0402_5%RH239 390_0402_5%
CPU_PLTRST#
+3VS
1 2
+3VS
+3V_PCH
RH265 10K_0402_5 %RH265 10K_0402_5%
RH266 10K_0402_5 %RH266 10K_0402_5%
1 2
RH272 10K_0402_5 %@ RH272 10K_0402_5%@
RH268 10K_0402_5 %@ RH268 10K_0402_5%@
Config
USB X4,PCIEX8,SATAX6
*
1 2
RH236 10K_0402_5%RH236 10K_0402_5%
KBRST# <46>
H_CPUPWRGD <6>
CPU_PLTRST# <6>
10K_0402_5%
10K_0402_5%
RH235 10K_0402_5%RH235 10K_0402_5%
12
12
12
12
12
PCH_GPIO16
PCH_GPIO49 PCH_GPIO68
PCH_GPIO16
PCH_GPIO49
GPIO16,49
11
01USB X6,PCIEX8,SATAX4
+3VS
GATEA20 <4 6>
H_THRMTRIP# <6>
PCH_THRMTRIP#_R <23,32>
RH1493
RH1493
EC_SCI#
EC_SMI#
Function
Reserve
14"
15"
+3VS
+3VS
+3VALW
DS3@
DS3@
1 2
1 2
5
12
DS3_WAKE#_R
@
@
RH250
RH250
ODD_DETECT#
PCH_GPIO37
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
3
2012/07/01
2012/07/01
2012/07/01
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2014/07/01
2014/07/01
2014/07/01
Title
Title
Title
PCH (6/9) GPIO, CPU, MISC
PCH (6/9) GPIO, CPU, MISC
PCH (6/9) GPIO, CPU, MISC
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Date: Sheet of
Date: Sheet of
Date: Sheet
Wednesday, March 27, 2013
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
1
19 69
19 69
19 69
of
1.0
1.0
1.0
RH207 10K_0402_5%
RH207 10K_0402_5%
A A
200K_0402_5%
200K_0402_5%
+3VS
RH259 10K_0402_5%RH259 10K_0402_5%
5
4
3
2
1
70mA
D D
1.312 A
J1
J1
112
JUMP_43X39
JUMP_43X39
RH209
RH209
+1.05VS_PCH_VCC
+1.05VS_PCH_VCC
10U_0603_6.3V6M
10U_0603_6.3V6M
1
CH30
CH30
2
670mA
+1.05VS_PCH_VCCASW
+1.05VS_PCH_VCCASW
RH37 5.11_0402_1%RH37 5.11_0402_1%
1U_0402_6.3V6K
1U_0402_6.3V6K
1
2
22U_0805_6.3V6M
22U_0805_6.3V6M
1
2
1 2
CH32
CH64
CH64
2
1
2
CH33
CH33
1U_0402_6.3V6K
1U_0402_6.3V6K
CH35
CH35
CH31
CH31
2
+PCH_VCCDSW
1U_0402_6.3V6K
1U_0402_6.3V6K
1
CH36
CH36
2
+PCH_VCCDSW
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
CH32
+1.05VS
2
C C
B B
+1.05VS
1 2
R_short 0_0603_5%
R_short 0_0603_5%
AA24
AA26
AD20
AD22
AD24
AD26
AD28
AE18
AE20
AE22
AE24
AE26
AG18
AG20
AG22
AG24
AA18
Y26
U14
U18
U20
U22
U24
V18
V20
V22
V24
Y18
Y20
Y22
UHG
UHG
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
DCPSUSBYP
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
LPT_PCH_M_EDS
LPT_PCH_M_EDS
Core
Core
LYNXPOINT_BGA695
LYNXPOINT_BGA695
CRT DAC
CRT DAC
FDI
FDI
HVCMOS
HVCMOS
USB3
USB3
PCIe/DMI
PCIe/DMI
SATA
SATA
VCCMPHY
VCCMPHY
7 OF 11 REV = 5
7 OF 11 REV = 5
VCCADAC1_5
VCCADACBG3_3
VCCVRM
VCCIO
VCCIO
VCC3_3_R30
VCC3_3_R32
DCPSUS1
VCCSUS3_3
VCCSUS3_3
DCPSUS3
DCPSUS3
VCCIO
VCCVRM
VCCVRM
VCCVRM
VCCIO
VCCVRM
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VSS
P45
P43
M31
BB44
AN34
AN35
R30
R32
Y12
AJ30
AJ32
AJ26
AJ28
AK20
AK26
AK28
BE22
AK18
AN11
AK22
AM18
AM20
AM22
AP22
AR22
AT22
+3VS
+3VS_PCH_VCC3_3
+PCH_USB_DCPSUS1
+3VPCH_PCH_VCCSUS 3_3
+PCH_USB_DCPSUS3
+1.05VS_PCH_VCCIO
+1.05VS_PCH_VCCIO
+VCCADAC
0.01U_0402_16V7K
0.01U_0402_16V7K
1
1
CH57
CH57
2
2
+3VPCH_PCH_VCCSUS 3_3
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
CH86
CH86
CH47
CH47
2
2
0.1U_0402_10V7K
0.1U_0402_10V7K
1
CH80
CH80
2
+1.05VS_PCH_VCCIO
1U_0402_6.3V6K
1U_0402_6.3V6K
1
CH46
CH46
2
10U_0603_6.3V6M
10U_0603_6.3V6M
CH56
CH56
1
2
1U_0402_6.3V6K
1U_0402_6.3V6K
CH45
CH45
1_0603_1%
1_0603_1%
1
2
RH1
RH1
12
+3VS_PCH_VCC3_3
0.1U_0402_10V7K
0.1U_0402_10V7K
1
CH38
CH38
2
+1.05V_+1.5V_RUN
+1.05V_+1.5V_RUN
10U_0603_6.3V6M
10U_0603_6.3V6M
1
2
10U_0603_6.3V6M
10U_0603_6.3V6M
CH44
CH44
+1.5VS
+1.05V_+1.5V_RUN
+1.05VS_PCH_VCCIO
@
@
CH85
CH85
1U_0402_6.3V6K
1U_0402_6.3V6K
1
2
+1.05V_+1.5V_RUN
10U_0603_6.3V6M
10U_0603_6.3V6M
@
@
1
CH83
CH83
2
10U_0603_6.3V6M
10U_0603_6.3V6M
@CH81
@
1
CH81
CH48
CH48
2
10U_0603_6.3V6M
10U_0603_6.3V6M
@
@
1
CH82
CH82
2
1U_0402_6.3V6K
1U_0402_6.3V6K
+PCH_VCCDSW_R
1
CH34
CH34
2
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
3
2012/07/01
2012/07/01
2012/07/01
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
+PCH_USB_DCPSUS1
1U_0402_6.3V6K
1U_0402_6.3V6K
1
2
+PCH_USB_DCPSUS3
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
@CH40
@
1
1
CH40
2
2
Deciphered Date
Deciphered Date
Deciphered Date
@CH61
@
CH61
1 2
@
@
CH39
CH39
2014/07/01
2014/07/01
2014/07/01
2
12
+1.05VS
RH3600_0402_5% @RH3600_0402_5% @
+1.05VS
RH1990_0603_5% @RH1990_0603_5% @
Title
Title
Title
PCH (7/9) PWR
PCH (7/9) PWR
PCH (7/9) PWR
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Date: Sheet of
Date: Sheet of
Date: Sheet
Wednesday, March 27, 2013
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
1
20 69
20 69
20 69
of
1.0
1.0
1.0
5
4
3
2
1
+3VPCH_PCH_VCCSUS 3_3
0.1U_0402_10V7K
CH70
CH70
1 2
1
2
1
2
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_10V7K
CH60
CH60
1
2
0.1U_0402_10V7K
0.1U_0402_10V7K
1
2
1U_0402_6.3V6K
1U_0402_6.3V6K
CH74
CH74
+1.05V_+1.5V_RUN
1U_0402_6.3V6K
1U_0402_6.3V6K
CH79
CH79
CH88
CH88
1
2
0.1U_0402_10V7K
0.1U_0402_10V7K
1
2
+3VPCH_VCCSUSHDA
+3VPCH_PCH_VCCSUS 3_3
+RTCVCC
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_10V7K
0.1U_0402_10V7K
1
1
CH67
CH67
CH68
CH68
CH69
CH69
2
2
+PCH_VPROC
+PCH_VCCCFUSE
CH55
CH55
0.1U_0402_10V7K
0.1U_0402_10V7K
1
1U_0402_6.3V6K
1U_0402_6.3V6K
1
2
CH58
CH58
2
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
1
1
CH73
CH73
2
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1
CH75
CH75
2
LPT_PCH_M_EDS
NXPOINT_BGA695
NXPOINT_BGA695
LY
LY
1U_0402_6.3V6K
1U_0402_6.3V6K
CH50
CH50
1
2
+PCH_VCCCLK3_3
1U_0402_6.3V6K
1U_0402_6.3V6K
CH51
CH51
1
2
LPT_PCH_M_EDS
USB
USB
GPIO/LPC
GPIO/LPC
Azalia
Azalia
RTC
RTC
CPU
CPU
ICC
ICC
SPI
SPI
Fuse
Fuse
Thermal
Thermal
8 OF 11 REV = 5
8 OF 11 REV = 5
1
2
1
2
R20
VCCSUS3_3
R22
VCCSUS3_3
A16
VCCDSW3_3
DCPSST
VCC3_3
VCC3_3
VCC3_3
VCCIO
VCCSUSHDA
VCCSUS3_3
VCCRTC
DCPRTC
DCPRTC
V_PROC_IO
V_PROC_IO
VCCSPI
VCC
VCC
VCCASW
VCCASW
VCCVRM
VCC3_3
VCC3_3
1U_0402_6.3V6K
1U_0402_6.3V6K
CH77
CH77
AA14
AE14
AF12
AG14
U36
A26
K8
A6
P14
P16
AJ12
AJ14
AD12
P18
+PCH_VCCCFUSE
P20
L17
R18
AW40
AK30
AK32
1U_0402_6.3V6K
1U_0402_6.3V6K
CH78
CH78
1
2
+PCH_VCCDSW 3_3
+PCH_VCCSST
CH84 0.1U_0402_10V7KCH84 0.1U_0402_10V7K
+1.05VS_PCH_VCCIO
+PCH_DCPRTC
0.1U_0402_10V7K
0.1U_0402_10V7K
+PCH_VPROC
+3VS_PCH_VCCSPI
+1.05VS_PCH_VCCASW
+3VS_PCH_VCC3_3
0.1U_0402_10V7K
0.1U_0402_10V7K
1
2
1 2
CH76
CH76
Place near pin AG30,AG32,AE30,AE32
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
CH52
CH52
1U_0402_6.3V6K
CH53
CH53
1
2
1U_0402_6.3V6K
CH54
CH54
1
2
UHH
+3VPCH_PCH_VCCSUS 3_3
0.1U_0402_10V7K
@
@
LH100
LH100
1 2
RH1516
RH1516
1 2
+1.05VS_PCH_VCCIO
12
0.1U_0402_10V7K
+1.05VS
1
CH59
CH59
0.1U_0402_10V7K
1
2
1U_0402_6.3V6K
1U_0402_6.3V6K
@CH87
@
CH87
10mA
22mA
0.1U_0402_10V7K
1
CH62
CH62
2
+3VS_PCH_VCC3_3
0.1U_0402_10V7K
0.1U_0402_10V7K
+1.05VS_PCH_VCCIO
CH63
CH63
1
2
+PCH_VCC
Place near pin AP45
1
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1
2
10U_0603_6.3V6M
10U_0603_6.3V6M
CH43
CH43
+1.05V_+1.5V_RUN
CH37
CH37
1U_0402_6.3V6K
1U_0402_6.3V6K
CH49
CH49
1
2
10U_0603_6.3V6M
10U_0603_6.3V6M
1
CH42
CH42
2
+PCH_USB_DCPSUS2
+PCH_VCC
+PCH_VCCCLK
+PCH_VCCCLK3_3
+PCH_VCCCLK
+1.05VS
306mA
RH200
RH200
1 2
R_short 0_0805_5%
R_short 0_0805_5%
2
3.629A
+3VS
183mA
55mA
1 2
R_short 0_0805_5%
R_short 0_0805_5%
D D
+1.05VS
1 2
RH361 0_0402 _5%@RH361 0_0402_5%@
C C
+3V_PCH +3VPCH_VCCS USHDA
RH215
RH215
R_short 0_0603_5%
R_short 0_0603_5%
+3VS +3VS_PCH_VCC SPI
RH213
RH213
R_short 0_0603_5%
B B
R_short 0_0603_5%
+1.05VS
JUMP_43X39
JUMP_43X39
+1.5VS +1.05V_+1.5V_RUN
+1.05VS
RH198 0_0603_5%@RH198 0_0603_5%@
+PCH_USB_DCPSUS2
+1.05VS
4.7UH_LQM18FN4R7M00D_20%
4.7UH_LQM18FN4R7M00D_20%
R_short 0_0603_5%
R_short 0_0603_5%
12
12
J2
J2
2
112
RH197
RH197
R_short 0_0603_5%
R_short 0_0603_5%
12
UHH
R24
VCCSUS3_3
R26
VCCSUS3_3
R28
VCCSUS3_3
U26
VCCSUS3_3
M24
VSS
U35
VCCUSBPLL
L24
VCC3_3
U30
VCCIO
V28
VCCIO
V30
VCCIO
Y30
VCCIO
Y35
DCPSUS2
AF34
VCCVRM
AP45
VCC
Y32
VCCCLK
M29
VCCCLK3_3
L29
VCCCLK3_3
L26
VCCCLK3_3
M26
VCCCLK3_3
U32
VCCCLK3_3
V32
VCCCLK3_3
AD34
VCCCLK
AA30
VCCCLK
AA32
VCCCLK
AD35
VCCCLK
AG30
VCCCLK
AG32
VCCCLK
AD36
VCCCLK
AE30
VCCCLK
AE32
VCCCLK
+PCH_VCCCLK
Place near pin Y32,AA30,AA32 Place near pin AD34 Place near pin AD35,AD36
RH212
RH212
15mA
+3VS_PCH_VCC3_3
0.1U_0402_10V7K
0.1U_0402_10V7K
1
CH65
CH65
2
CH66
CH66
1U_0402_6.3V6K
1U_0402_6.3V6K
1
CH72
CH72
CH71
CH71
2
12
RH2010_0402_5% @RH2010_0402_5% @
12
RH1515R_short 0_0402_5% RH1515R_short 0_0402_5%
RH219
RH219
R_short 0_0805_5%
R_short 0_0805_5%
@
@
12
RH2200_0805_5%
RH2200_0805_5%
12
RH2210_0805_5% RH2210_0805_5%
+3V_PCH
+3VALW
+1.05VS
12
+3VS
+1.05VS
+3V_PCH +3VPCH_PCH_VCCSUS 3_3
A A
RH211
RH211
R_short 0_0603_5%
R_short 0_0603_5%
RH214
RH214
R_short 0_0603_5%
R_short 0_0603_5%
5
12
+3VS_PCH_VCC3_3+3VS
12
261mA
133mA
4
Place near pin M29 Place near pin L29 Place near pin L26,M26 Place near pin U32,V32
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
3
2012/07/01
2012/07/01
2012/07/01
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2014/07/01
2014/07/01
2014/07/01
Title
Title
Title
PCH (8/9) PWR
PCH (8/9) PWR
PCH (8/9) PWR
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Date: Sheet of
Date: Sheet of
Date: Sheet
Wednesday, March 27, 2013
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
1
21 69
21 69
21 69
of
1.0
1.0
1.0
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