A
1 1
B
C
D
E
VIQY1
(Y510)
2 2
NM_A032 Rev1.0 Schematic
Intel Haswell Processor with DDRIII + Lynx point PCH
3 3
4 4
A
nVIDIA N14P GT + 2nd VGA N14P GT
2013-03-19 Rev1.0
Security Class ification
Security Class ification
Security Class ification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
B
2012/07/ 01
2012/07/ 01
2012/07/ 01
C
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2014/07/ 01
2014/07/ 01
2014/07/ 01
D
Title
Title
Title
Cover Page
Cover Page
Cover Page
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
Custom
Custom
Custom
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Date: Sheet of
Date: Sheet of
Date: Sheet of
Wednesday, March 27, 2013
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032Y510 NM-A032
Y510 NM-A032Y510 NM-A032
Y510 NM-A032Y510 NM-A032
E
1 69
1 69
1 69
1.0
1.0
1.0
A
B
C
D
E
PCI-Express 16X Gen3
Intel CPU
P
G 0~7PEG 8~15
E
2
d VGA, N14P-GT1
1 1
n
V
AM 64*32
R
GDDR5* 8
Sub/B
HDMI Conn. CRT Conn.
HDMI1.4b
2 2
3 3
Page 39 Page 36
Page 32 Page 23,24,25,26,27,28,29,30,31,33
MUX
Page 37
LVDS Conn.
HDMI
Page 35
RJ45 Conn.
Page 42
Card reader
Conn.
Page 48
LVDS
N
4P-GT1
1
VRAM 64*32
GDDR5* 8
MUX
Page 37
eDP to LVDS
PS8625
Page 34
Atheros
QCA8171-BL3A-R
PCIe port 3
SPI ROM
(4MB+2MB)
SATA HDD
SATA ODD
Card reader IC
GL3213
CRT
MUX
Page 38
Page 41
Page 17
SATA Port 5
page 44
SATA Port 2
page 44
Page 48
eDP
eDP
PCIe Gen1
1.5V 5GT/s
SPI BUS
3.3V 33MHz
SATA Gen3 Port 5
3V 6GHz(600MB/s)
SATA Gen1 Port2
3V 3GHz(300MB/s)
USB 3.0 Port6
5V 5GT/s
USB 2.0 Port4
5V 480MHz
FDI *2
2.7GT/s
Haswell
rPGA946
37.5mm*37.5mm
Page 5,6,7,8,9,10
DMI *4
5GT/s
Intel PCH
Lynx point
FCBGA 695Balls
20mm*20mm
Page 13,14,15,16,17,18,19,20,21,22
LPC BUS
3.3V 33MHz
1
35V DDRIIIL 1066/1333/1600 MT/s
.
USB 2.0 Port1
5V 480MHz
USB 2.0
5V 480MHz
USB 3.0
5V 5GT/s
USB 2.0
5V 480MHz
PCIe Gen1
5V 480MHz
SATA Gen3
5V 6GHz(600MB/s)
HD Audio
3.3V 24MHz
M
mory BUS (DDRIII)
e
Dual Channel
USB Charger IC
GL887T
USB Left
USB 2.0 Port 2
USB 3.0 Port 2
Int. Camera
USB 2.0 Port 0
PCIeMini Card
WLAN
PCIeMini Card
WLAN
Page 50
Page 49
Page 35
PCIe Port 4
page 40
USB Port 10
page 40
DDR3-SO-DIMM X2
B
ANK 0, 1, 2, 3
P TO 16G
U
Page 11,12
USB Charger
Conn.
Sub/B
USB Left
USB 2.0 Port 3
USB 3.0 Port 5
Touch panel
USB 2.0 Port 8
NGFF SSD
Page 50
Page 49
Page 50
SATA Port 4
page 40
Debug Port
Page 40
Power Circuit DC/DC
Page 56,57 ,58,59,60, 61,
62,63 ,64,65,66
4 4
DC/DC Interface CKT.
POWER/B Conn. AUDIO, USB/B Conn.
ODD/B Conn.
Page 55
Page 52 Page 50
page 44
A
RTC CKT.
NOVO/B Conn.
Page 56
Page 52
Touch Pad
B
EC
ITE IT8586E-FX
Page 46
Int.KBD
Page 47
Security Classification
Security Classification
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
Issued Date
Issued Date
Issued Date
Page 47
C
Thermal Sensor
EMC 1403
2012/07/01
2012/07/01
2012/07/01
Page 43
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Codec
ALC282CG
Int. MIC Conn.
(JCMOS Conn.)
Page 35 Page 50
2014/07/01
2014/07/01
2014/07/01
D
Page 45
SPK Conn.
Page 45
Ext. MIC Conn.
Sub/B
Title
Title
Title
Block Diagram
Block Diagram
Block Diagram
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Date: Sheet of
Date: Sheet of
Date: Sheet of
Wednesday, March 27, 2013
HP Conn.
Sub/B
Page 50
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
E
2 69
2 69
2 69
1.0
1.0
1.0
A
B
C
D
E
Voltage Rails
( O --> Means ON ,
Power Plane
1 1
B+
S
tate
S0
S3
2 2
S5 S4/AC Only
S5 S4
Battery only
O
O
O
O
S5 S4
AC & Battery
X X
don't exist
SMBUS Control Table
SOURCE
3 3
IT
8580EEC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
C_SMB_DA2
E
SMB_CLK_S3
SMB_DATA_S3
+3VALW
IT8580E
+3VS
PCH
+3VS
Main
V
GA
X
V
+3VS +3VS
X X
X --> Means OFF )
+5VS
+3VS
+1.5VS
+VCCSA
+V1.5S_VCC P
+3VALW
+1.5V
+5VALW
+CPU_CORE
+VGA_CORE
GFX_CORE
+
+1.8VS
+1.05VS
+0.75VS
+3.3VS_VGA
+1.5VS_VGA
+1.05VS_VG A
O O O
OO
O
X
X X
X
2nd
VGA
BATT SODIMM
IT8580E
X X
+3VALW
V
X
X
X X X
X
X
V V
+3VS
WLAN
WiMAX
X
X
V
X
X
X
X
Thermal
Sensor
V
+3VS
PCH
XV
V
+3V_PCH
+3V_PCH+3VS
IGNAL
STATE
Full ON
S1(Power On Suspend)
S3 (Suspend to RAM)
S4 (Suspend to Disk)
S5 (Soft OFF)
S
USB Port Table
USB 3.0USB 2.0 Port
XHCI
EHCI1
2
5
6
EHCI2
TP
M
odule
XX
X
V
+3VS
SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
ON
HIGH HIGH HIGH HIGH
LOW
LOW
LOW
LOW LOW LOW LOW
HIGH
LOWLOWLOW
HIGHHIGHHIGH
HIGH
HIGH
ON
ON
ON
ON
ON
ON
OFF
ON
OFF
BOM Structure Table
4 External
USB Port
0
1
USB Port (Right Side)
2
3
USB Port (Left Side)
USB Port (Left Side)
4
5
6
7
8
9
10
Mini Card(WLAN)
11
12
13
PCIE PORT LIST
Port Device
1
2
3
4
5
6
7
8
LAN
WLAN
Camera
Card Reader
Touch panel
GT@
GT1@
CMOS@
SURGE@
X76@
GC6@
NOGC6@
AOAC@
KBL@
ME@
@
DS3@
daul@
887T@
887@
TI@
EDP@
SLI@
47W@
37W@
ON ON
ON
OFF
OFF
OFF
LOW
OFF
OFF
OFF
BTO ItemBOM Structure
NV GT750M
NV GT755M
CMOS Camera part
QCA8171 LAN surge part
X76 Level part for VRAM
NV CG6 support part
NV no CG6 support part
AOAC support part
K/B Light part
ME part
Unpop
Deep S3 support part
Support daul channel panel function
GENESYS 887T USB charger solution
GENESYS 887 USB charger solution
TI USB charger solution
Support EDP panel function
For SLI function part
For 47W CPU part
For 37W CPU part
A
Address
0001 011X b
EC SM Bus2 address
Device
Thermal Sen sor EMC1403-2
Master VGA
Slave VGA
B
Address
1001_101xb
0x9E
0x9C
PCH SM Bus address
Device Address
DDR DIMM0
DDR DIMM2
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
C
1001 000Xb
1001 010Xb
2012/07/01
2012/07/01
2012/07/01
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2014/07/01
2014/07/01
2014/07/01
D
4 4
EC SM Bus1 address
Device
Smart Battery
ZZZ1
ZZZ1
DAZ0SF00100
DAZ0SF00100
Title
Title
Title
Notes List
Notes List
Notes List
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Date: Sheet of
Date: Sheet of
Date: Sheet of
Wednesday, March 27, 2013
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
E
3 69
3 69
3 69
1.0
1.0
1.0
5
4
3
2
1
Hot plug detect for IFP link E
VGA and GDDR5 Voltage Rails (N14Px GPIO)
GPIO I/O ACTIVE Function Description
GPIO0
D D
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
C C
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
B B
IN FB_CLAMP_MON-
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
IN
OUT
IN
IN
IN
+3VS_VGA
+VGA_CORE
+1.5VS_VGA
+1.05VS_VGA
-
NAOUT
VGA_BL_PWM
-
-
VGA_ENVDD
- VGA_ENBKL
NA
-
FB_CLAMP_TOGGLE_REQ#
-
NA
-
OVERT#
-
VGA_ALERT#
-
Memory VREF Control
-
NVVDD PWM_VID-OUT
-
AC Power Detect Input
DPRSLPVR_VGA -
NA
-
-
NA
-
NA
-
VGA_EDP_HPD
-
DGPU_HDMI_HPD
NA
-
tNVVDD >0
tFBVDDQ >0
tPEX_VDD >0
1. all power r ail ramp up ti me should be la rger than 40us
(10K pull High)
Performance Mode P0 TDP at Tj = 102 C* (GDDR5)
GPU Mem NVCLK
(4) (1,5) (6)
Products
(W) (W) (MHz)
N14X
128bit
1GB
GDDR5
Physical
Strapping pin
ROM_SCLK
ROM_SI
ROM_SO FB[0]
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
N13P-GT
(28nm)
/MCLK NVVDD
(V) (A) (W) (A) (W)
TBD TBDTBD TBD TBD TBD TBD TBD T BD TBD TBD TBD TBD TBD TBD TBD TBD TBD
Power Rail
+3VS_VGA
+3VS_VGA
+
3VS_VGA
+3VS_VGA
+3VS_VGA
+3VS_VGA
+3VS_VGA
+3VS_VGA
Device ID
0x0FCD
Logical
Strapping Bit3
PCI_DEVID[4]
FB[1]
PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0]
SOR3_EXPOSED
RESERVED PCIE_SPEED_
3GIO_PAD_CFG_ADR [2] 3GIO_PAD_CFG_ADR [1]3GIO_PAD_CFG_ADR [3]
setting
SMB_ALT_ADDR
(ROM_SO Bit 1)
0
1
ROM_SO ROM_SCLK
GPU
N14P-GT
28nm
PU 10K PD 25K
FB Memory (GDDR5)
Samsung
3000MHz
Hynix
3000MHz
Samsung
2500MHz
2500MHz
PD 15K
PU 45K
PU 25K PD 35KPU 45KPU 20K PD 10K PD 5K PD 10K
GPU
K4G20325FD-FC03
64Mx32
H5GQ2H24AFR-R0C
64Mx32 PD 25K
K4G20325FD-FC04
64Mx32
H5GQ2H24AFR-T2CHynix
64Mx32
PD 5K
N14P-GT
ROM_SI
PD 30K
PD 25K
FBVDDQ PCI Express I/O and
FBVDD
(GPU+Mem)
(1.35V)(1.35V)
(A) (W) (W)(mA) (W) (W) (W)(mA) (mA) (mA)
Logical
Strapping Bit2
SUB_VENDOR
SER[2] USER[1] USER[0]USER[3]
U
SOR2_EXPOSED SOR1_EXPOSED
CHANGE_GEN3
I2C Slave addrees ID
0x9E
0x9C
STRAP2STRAP1STRAP0
N14P-GT1
ROM_SI
PD 30K
(1.05V)
Logical
Strapping Bit1
SLOT_CLK_CFG
RAM_CFG[1]RAM_CFG[3] RAM_CFG [2]
PCIE_MAX_SPEED DP_PLL _VDD33V
STRAP3
STRAP4
PU 5K PD 45K
PLLVDD
Master
Slave
I/O and
PLLVDD
Logical
Strapping Bit0
PEX_PLL_EN_TERM
R
AM_CFG[0]
VGA_DEVICESMB_ALT_ADDR
3GIO_PAD_CFG_ADR [0]
SOR0_EXPOSED
Other
(3.3V)(1.05V)(1.8V)
Other Power rail
A A
+3VS_VGA
power-off <10m s
T
1.all GPU powe r rails should be turned off within 10ms
. Optimus syst em VDD33 avoid s drop down ear lier than NVDD and FBVDDQ
2
5
Title
Title
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
4
3
2012/07/01
2012/07/01
2012/07/01
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2014/07/01
2014/07/01
2014/07/01
Title
VGA Notes List
VGA Notes List
VGA Notes List
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Date: Sheet of
Date: Sheet of
Date: Sheet of
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
1
4 69
4 69
4 69
1.0
1.0
1.0
5
4
3
2
1
D D
Haswell rPGA EDS
Haswell rPGA EDS
D21
C21
B21
A21
D20
C20
B20
A20
D18
C17
B17
A17
D17
C18
B18
A18
H29
J29
DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3
DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3
DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3
DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3
FDI_CSYNC
FDI_INT
IN
IN
TEL_HASWELL_HAS WELL
TEL_HASWELL_HAS WELL
12
12
DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
FDI_CSYNC_R
FDI_INT_R
DMI_CRX_PTX_N0<15>
DMI_CRX_PTX_N1<15>
DMI_CRX_PTX_N2<15>
DMI_CRX_PTX_N3<15>
DMI_CRX_PTX_P0<15>
DMI_CRX_PTX_P1<15>
DMI_CRX_PTX_P2<15>
DMI_CRX_PTX_P3<15>
DMI_CTX_PRX_N0<15>
C C
FDI_CSYNC<15>
FDI_INT<15>
B B
DMI_CTX_PRX_N1<15>
DMI_CTX_PRX_N2<15>
DMI_CTX_PRX_N3<15>
DMI_CTX_PRX_P0<15>
DMI_CTX_PRX_P1<15>
DMI_CTX_PRX_P2<15>
DMI_CTX_PRX_P3<15>
RC3 0_0402_5%RC3 0_0402_5%
RC87 0_0402_5%RC87 0_0402_5%
JCPUA
JCPUA
PEG_RCOMP
PEG
PEG
DMI FDI
DMI FDI
PEG_RXN_10
PEG_RXN_11
PEG_RXN_12
PEG_RXN_13
PEG_RXN_14
PEG_RXN_15
PEG_RXP_10
PEG_RXP_11
PEG_RXP_12
PEG_RXP_13
PEG_RXP_14
PEG_RXP_15
PEG_TXN_10
PEG_TXN_11
PEG_TXN_12
PEG_TXN_13
PEG_TXN_14
PEG_TXN_15
PEG_TXP_10
PEG_TXP_11
PEG_TXP_12
PEG_TXP_13
PEG_TXP_14
PEG_TXP_15
1 OF 9
1 OF 9
PEG_RXN_0
PEG_RXN_1
PEG_RXN_2
PEG_RXN_3
PEG_RXN_4
PEG_RXN_5
PEG_RXN_6
PEG_RXN_7
PEG_RXN_8
PEG_RXN_9
PEG_RXP_0
PEG_RXP_1
PEG_RXP_2
PEG_RXP_3
PEG_RXP_4
PEG_RXP_5
PEG_RXP_6
PEG_RXP_7
PEG_RXP_8
PEG_RXP_9
PEG_TXN_0
PEG_TXN_1
PEG_TXN_2
PEG_TXN_3
PEG_TXN_4
PEG_TXN_5
PEG_TXN_6
PEG_TXN_7
PEG_TXN_8
PEG_TXN_9
PEG_TXP_0
PEG_TXP_1
PEG_TXP_2
PEG_TXP_3
PEG_TXP_4
PEG_TXP_5
PEG_TXP_6
PEG_TXP_7
PEG_TXP_8
PEG_TXP_9
E23
PEG_COMP
M29
PCIE_CRX_GTX_N0
K28
PCIE_CRX_GTX_N1
M31
PCIE_CRX_GTX_N2
L30
PCIE_CRX_GTX_N3
M33
PCIE_CRX_GTX_N4
L32
PCIE_CRX_GTX_N5
M35
PCIE_CRX_GTX_N6
L34
PCIE_CRX_GTX_N7
E29
PCIE_CRX_GTX_N8
D28
PCIE_CRX_GTX_N9
E31
PCIE_CRX_GTX_N10
D30
PCIE_CRX_GTX_N11
E35
PCIE_CRX_GTX_N12
D34
PCIE_CRX_GTX_N13
E33
PCIE_CRX_GTX_N14
E32
PCIE_CRX_GTX_N15
L29
PCIE_CRX_GTX_P0
L28
PCIE_CRX_GTX_P1
L31
PCIE_CRX_GTX_P2
K30
PCIE_CRX_GTX_P3
L33
PCIE_CRX_GTX_P4
K32
PCIE_CRX_GTX_P5
L35
PCIE_CRX_GTX_P6
K34
PCIE_CRX_GTX_P7
F29
PCIE_CRX_GTX_P8
E28
PCIE_CRX_GTX_P9
F31
PCIE_CRX_GTX_P10
E30
PCIE_CRX_GTX_P11
F35
PCIE_CRX_GTX_P12
E34
PCIE_CRX_GTX_P13
F33
PCIE_CRX_GTX_P14
D32
PCIE_CRX_GTX_P15
H35
PCIE_CTX_GRX_N0
H34
PCIE_CTX_GRX_N1
J33
PCIE_CTX_GRX_N2
H32
PCIE_CTX_GRX_N3
J31
PCIE_CTX_GRX_N4
G30
PCIE_CTX_GRX_N5
C33
PCIE_CTX_GRX_N6
B32
PCIE_CTX_GRX_N7
B31
PCIE_CTX_GRX_N8
A30
PCIE_CTX_GRX_N9
B29
PCIE_CTX_GRX_N10
A28
PCIE_CTX_GRX_N11
B27
PCIE_CTX_GRX_N12
A26
PCIE_CTX_GRX_N13
B25
PCIE_CTX_GRX_N14
A24
PCIE_CTX_GRX_N15
J35
PCIE_CTX_GRX_P0
G34
PCIE_CTX_GRX_P1
H33
PCIE_CTX_GRX_P2
G32
PCIE_CTX_GRX_P3
H31
PCIE_CTX_GRX_P4
H30
PCIE_CTX_GRX_P5
B33
PCIE_CTX_GRX_P6
A32
PCIE_CTX_GRX_P7
C31
PCIE_CTX_GRX_P8
B30
PCIE_CTX_GRX_P9
C29
PCIE_CTX_GRX_P10
B28
PCIE_CTX_GRX_P11
C27
PCIE_CTX_GRX_P12
B26
PCIE_CTX_GRX_P13
C25
PCIE_CTX_GRX_P14
B24
PCIE_CTX_GRX_P15
PEG_COMP
CAD Note:
Trace width=12 mils ,Spacing=15mil
Max length= 400 mils.
PCIE_CRX_GTX_N[0..15] <23,32>
PCIE_CRX_GTX_P[0..15] <23,32>
CC1 0.22U_0402_10V6KCC1 0.22U_0402_10V6K
CC2 0.22U_0402_10V6KCC2 0.22U_0402_10V6K
CC3 0.22U_0402_10V6KCC3 0.22U_0402_10V6K
CC4 0.22U_0402_10V6KCC4 0.22U_0402_10V6K
CC5 0.22U_0402_10V6KCC5 0.22U_0402_10V6K
CC6 0.22U_0402_10V6KCC6 0.22U_0402_10V6K
CC7 0.22U_0402_10V6KCC7 0.22U_0402_10V6K
CC8 0.22U_0402_10V6KCC8 0.22U_0402_10V6K
CC9 0.22U_0402_10V6KCC9 0.22U_0402_10V6K
CC10 0.22U_ 0402_10V6KCC10 0.22U_0402_10V6 K
CC11 0.22U_ 0402_10V6KCC11 0.22U_0402_10V6 K
CC12 0.22U_ 0402_10V6KCC12 0.22U_0402_10V6 K
CC13 0.22U_ 0402_10V6KCC13 0.22U_0402_10V6 K
CC14 0.22U_ 0402_10V6KCC14 0.22U_0402_10V6 K
CC15 0.22U_ 0402_10V6KCC15 0.22U_0402_10V6 K
CC16 0.22U_ 0402_10V6KCC16 0.22U_0402_10V6 K
CC20 0.22U_ 0402_10V6KCC20 0.22U_0402_10V6 K
CC23 0.22U_ 0402_10V6KCC23 0.22U_0402_10V6 K
CC25 0.22U_ 0402_10V6KCC25 0.22U_0402_10V6 K
CC30 0.22U_ 0402_10V6KCC30 0.22U_0402_10V6 K
CC18 0.22U_ 0402_10V6KCC18 0.22U_0402_10V6 K
CC22 0.22U_ 0402_10V6KCC22 0.22U_0402_10V6 K
CC28 0.22U_ 0402_10V6KCC28 0.22U_0402_10V6 K
CC32 0.22U_ 0402_10V6KCC32 0.22U_0402_10V6 K
CC19 0.22U_ 0402_10V6KCC19 0.22U_0402_10V6 K
CC24 0.22U_ 0402_10V6KCC24 0.22U_0402_10V6 K
CC29 0.22U_ 0402_10V6KCC29 0.22U_0402_10V6 K
CC17 0.22U_ 0402_10V6KCC17 0.22U_0402_10V6 K
CC21 0.22U_ 0402_10V6KCC21 0.22U_0402_10V6 K
CC27 0.22U_ 0402_10V6KCC27 0.22U_0402_10V6 K
CC26 0.22U_ 0402_10V6KCC26 0.22U_0402_10V6 K
CC31 0.22U_ 0402_10V6KCC31 0.22U_0402_10V6 K
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
+VCCIOA_OUT
12
RC224.9_0402_1% RC224.9_0402_1%
PEG Static Lane Reversal - CFG2 is for the 16x
CFG2
PCIE_CTX_C_GRX_N0
PCIE_CTX_C_GRX_N1
PCIE_CTX_C_GRX_N2
PCIE_CTX_C_GRX_N3
PCIE_CTX_C_GRX_N4
PCIE_CTX_C_GRX_N5
PCIE_CTX_C_GRX_N6
PCIE_CTX_C_GRX_N7
PCIE_CTX_C_GRX_N8
PCIE_CTX_C_GRX_N9
PCIE_CTX_C_GRX_N10
PCIE_CTX_C_GRX_N11
PCIE_CTX_C_GRX_N12
PCIE_CTX_C_GRX_N13
PCIE_CTX_C_GRX_N14
PCIE_CTX_C_GRX_N15
PCIE_CTX_C_GRX_P0
PCIE_CTX_C_GRX_P1
PCIE_CTX_C_GRX_P2
PCIE_CTX_C_GRX_P3
PCIE_CTX_C_GRX_P4
PCIE_CTX_C_GRX_P5
PCIE_CTX_C_GRX_P6
PCIE_CTX_C_GRX_P7
PCIE_CTX_C_GRX_P8
PCIE_CTX_C_GRX_P9
PCIE_CTX_C_GRX_P10
PCIE_CTX_C_GRX_P11
PCIE_CTX_C_GRX_P12
PCIE_CTX_C_GRX_P13
PCIE_CTX_C_GRX_P14
PCIE_CTX_C_GRX_P15
1: Normal Operation; Lane # definition matches
socket pin map definition
:Lane Reversed
0
*
PCIE_CTX_C_GRX_N[0..15] <23,32>
PCIE_CTX_C_GRX_P[0..15] <23,32>
A A
Title
Title
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
3
2012/07/01
2012/07/01
2012/07/01
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2014/07/01
2014/07/01
2014/07/01
Title
CPU (1/7) DMI, FDI, PEG
CPU (1/7) DMI, FDI, PEG
CPU (1/7) DMI, FDI, PEG
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Wednesday, March 20, 2013
Wednesday, March 20, 2013
Date: Sheet of
Date: Sheet of
Date: Sheet of
Wednesday, March 20, 2013
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
1
5 69
5 69
5 69
0.1
0.1
0.1
5
4
3
2
1
+1.35V
RC60
RC60
1 2
0_0402_5%
0_0402_5%
D
S
D
S
H_DRAMRST#
RC1544
D D
DRAMRST_CNTRL_PC H<17>
DRAMRST_CNTRL<7>
DRAMRST_CNTRL_EC<46>
RC42 0_0402_5%
RC42 0_0402_5%
Reserve for Deep S3
RC1544
4.99K_0402_1% @
4.99K_0402_1% @
1 2
@
@
RC1545
RC1545
1 2
R_short 0_0402_5%
R_short 0_0402_5%
1 2
DRAMRST_CNTRL
@
@
G
G
2
1
2
13
DDR3_DRAMRST#_R
QC3
QC3
BSS138_NL_SOT23-3
BSS138_NL_SOT23-3
CC50
CC50
0.047U_0402_16V4Z@
0.047U_0402_16V4Z@
RC62
1K_0402_5%
1K_0402_5%
12
@RC62
@
RC1543
RC1543
1 2
0_0402_5%
0_0402_5%
DDR3_DRAMRST# <11,12>
RC5 need to close to JCPU1
H_CPUPWRGD H_CPUP WRGD_XDP
SIO_PWRBTN#_R<15>
CPU_PWR_DEBU G<9>
+1.05VS
1 2
RC5 1K_0402_1%RC5 1K_0402_1%
1 2
RC6 0_0402_5%@RC6 0_0402_5%@
VGATE<15,64>
CLK_CPU_ITP<16>
CLK_CPU_ITP#<16>
1 2
PU/PD for JTAG signals
C C
XDP_DBRESET#_R
XDP_TMS
XDP_TDI
XDP_PREQ#
XDP_TDO
XDP_TCLK
XDP_TRST#
B B
PM_DRAM_PWR GD<15>
A A
RC19 1K_040 2_1%RC19 1K_0402_1%
RC27 51_0402_1 %@RC 27 51_0402_1%@
RC29 51_0402_1 %@RC 29 51_0402_1%@
RC32 51_0402_1 %@RC 32 51_0402_1%@
RC35 51_0402_1 %@RC 35 51_0402_1%@
RC40 51_0402_1 %RC40 51_0402_1%
RC41 51_0402_1 %RC41 51_0402_1%
SM_DRAMPWROK with DDR Power Gating Topology
SYS_PWROK<15>
12
12
12
12
12
12
12
RC88 0_0402_5%
RC88 0_0402_5%
+3VS
+1.05VS
H_PECI<46>
1 2
H_PROCHOT#<46,57>
H_PM_SYNC<15>
H_CPUPWRGD<19>
CLK_CPU_DPLL#<16>
CLK_CPU_DPLL<16>
CLK_CPU_SSC_DPLL#<16>
CLK_CPU_SSC_DPLL<16>
+3V_PCH
200_0402_5%
200_0402_5%
12
RC89
RC89
RC1547 0_ 0402_5%@RC1547 0_ 0402_5%@
RUN_ON_CPU1.5VS3#<10>
+3V_PCH
12
RC84
RC84
1
2
CC156
CC156
1 2
0.1U_0402_25V6K
0.1U_0402_25V6K
5
P
B
4
O
A
G
UC4
UC4
74AHC1G09GW_TSSOP5
74AHC1G09GW_TSSOP5
3
12
100K_0402_5%
100K_0402_5%
@
@
12
RC57 56_0402_5%RC57 56_0402_5%
RC25
RC25
R_short 0_0402_5%
R_short 0_0402_5%
RC51 0_0402_5%RC51 0_0402_5%
RC52 0_0402_5%RC52 0_0402_5%
RC43 0_0402_5%RC43 0_0402_5%
RC22 0_0402_5%RC22 0_0402_5%
@
@
2
G
G
H_THRMTRIP#<19>
1 2
12
12
12
12
CLK_CPU_DMI#<16>
CLK_CPU_DMI<16>
497750_497750_SH RKBY_MBL_SCH_CH KLST 0.5
page19 item 3.6 SM_DRAMPWROK
+1.35V_CPU_VDDQ
1.8K_0402_1%
1.8K_0402_1%
12
RC16
RC16
RC28 0_0402_5%RC28 0_0402_5%
3.3K_0402_1%
3.3K_0402_1%
39_0402_5%
39_0402_5%
12
RC14
RC14
@RC64
@
RC64
SSM3K7002FU_SC70-3
SSM3K7002FU_SC70-3
1 2
13
D
D
@
@
QC1
QC1
S
S
H_CATERR#
H_PECI
T55PAD @T55PAD @
H_PROCHOT#_R
H_THRMTRIP#
H_PM_SYNC
VCCPWRGOOD_0_R
PM_DRAM_PWR GD_CPU
BUF_CPU_RST#
CPU_DPLL#
CPU_DPLL
CPU_SSC_DPLL#
CPU_SSC_DPLL
CLK_CPU_DMI#
CLK_CPU_DMI
12
PM_DRAM_PWR GD_CPURUNPWROK_AND
AP32
SKTOCC
AN32
CATERR
AR27
PECI
AK31
RSVD
AM30
PROCHOT
AM35
THERMTRIP
AT28
PM_SYNC
AL34
PWRGOOD
AC10
SM_DRAMPWR OK
AT26
PLTRSTIN
G28
DPLL_REF_CLKN
H28
DPLL_REF_CLKP
F27
SSC_DPLL_REF_CLKN
E27
SSC_DPLL_REF_CLKP
D26
BCLKN
E26
BCLKP
Haswell rPGA EDS
Haswell rPGA EDS
INTEL_HASWELL_HAS WELL
INTEL_HASWELL_HAS WELL
JCPUB
JCPUB
MISC
MISC
THERMAL
THERMAL
PWR
PWR
CPU_PLTRST#<19>
AP3
SM_RCOMP0
AR3
SM_RCOMP1
AP2
SM_RCOMP2
AN3
H_DRAMRST#
AR29
XDP_PRDY#
AT29
XDP_PREQ#
AM34
XDP_TCLK
AN33
XDP_TMS
AM33
XDP_TRST#
AM31
XDP_TDI XDP_TDI_R
TDI
AL33
XDP_TDO XDP_TDO_R
AP33
AR30
XDP_OBS0_R
AN31
XDP_OBS1_R
AN29
XDP_OBS2_R
AP31
XDP_OBS3_R
AP30
XDP_OBS4_R
AN28
XDP_OBS5_R
AP29
XDP_OBS6_R
AP28
XDP_OBS7_R
DDR3
DDR3
CLOCK
CLOCK
SM_RCOMP_0
SM_RCOMP_1
SM_RCOMP_2
SM_DRAMRST
PRDY
PREQ
JTAG
JTAG
BPM_N_0
BPM_N_1
BPM_N_2
BPM_N_3
BPM_N_4
BPM_N_5
BPM_N_6
BPM_N_7
2 OF 9
2 OF 9
TCK
TMS
TRST
TDO
DBR
For ESD
Buffered Reset to CPU
+VCCIO_OUT
.05V
1
1 2
0_0402_5%
0_0402_5%
RC46
RC46
XDP Connector
XDP_PREQ#_R
XDP_PRDY#_R
XDP_OBS0
XDP_OBS1
XDP_OBS2
XDP_OBS3
CFD_PWRBTN#_X DP
CPU_PWR_DEBU G
VGATE
CLK_CPU_ITP
CLK_CPU_ITP#
XDP_RST#_RBUF_CPU_RST#
XDP_DBRESET#
RC81K_0402_1% RC81K_0402_1%
XDP_TDO_R
XDP_TRST#_R
XDP_TDI_R
XDP_TMS_R
XDP_TCK_R
20120806 VA
change XDP connector to 28 pin
1 2
RC47 0_0402_5%RC 47 0_0402_5%
1 2
RC48 0_0402_5%RC 48 0_0402_5%
1 2
RC50 0_0402_5%RC 50 0_0402_5%
1 2
RC53 0_0402_5%RC 53 0_0402_5%
1 2
RC54 0_0402_5%RC 54 0_0402_5%
1 2
RC23 0_0402_5%RC23 0_0402_5%
1 2
RC24 0_0402_5%RC24 0_0402_5%
RC26 0_0402_5%RC26 0_0402_5%
1 2
RC30 0_0402_5%RC30 0_0402_5%
1 2
RC31 0_0402_5%RC31 0_0402_5%
1 2
RC33 0_0402_5%RC33 0_0402_5%
1 2
RC34 0_0402_5%RC34 0_0402_5%
1 2
RC36 0_0402_5%RC36 0_0402_5%
1 2
RC37 0_0402_5%RC37 0_0402_5%
1 2
RC38 0_0402_5%RC38 0_0402_5%
1 2
RC39 0_0402_5%RC39 0_0402_5%
VCCPWRGOOD_0_RBUF_CPU_RST#
1
@
@
CC61
CC61
220P_0402_25V8J
220P_0402_25V8J
2
+1.05VS
BUF_CPU_RST#
RC126
RC128
RC44
RC44
1 2
@RC126
@
1 2
@RC128
@
1 2
12
@
@
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
MOLEX 52435-2671
MOLEX 52435-2671
XDP_PRDY#_R
XDP_PREQ#_R
XDP_TCK_R
XDP_TMS_R
XDP_TRST#_R
1
CC60
CC60
220P_0402_25V8J
220P_0402_25V8J
2
H_THRMTRIP#
100_0402_1%
100_0402_1%
H_CATERR#
49.9_0402_1%
49.9_0402_1%
H_PROCHOT#
62_0402_5%
62_0402_5%
JXDP
XDP_DBRESET#XDP_DBRESET#_R
XDP_OBS0
XDP_OBS1
XDP_OBS2
XDP_OBS3
@JXDP
@
Place near JXDP1
27
28
+1.05VS
@
@
0.1U_0402_25V6K
0.1U_0402_25V6K
0.1U_0402_25V6K
0.1U_0402_25V6K
1
1
CC65
CC65
CC66
CC66
@
@
2
2
DDR3 COMPENSATION SIGNALS
RC1539
RC1539
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
CAD Note:
Trace width=12~15 mil, Spcing=20 mils
Max trace length= 500 mil
For ESD concern, please put near CPU
CPU_SSC_DPLL
CPU_SSC_DPLL#
SSC CLOCK TERMINATION, IF NOT USED, stuff RC20,RC21
1 2
1 2
RC55 75_0402_1%RC 55 75_0402_1%
1 2
RC49 100_0402_ 1%RC49 100_0402_1%
VCCPWRGOOD_0_R
CAD Note:
Avoid stub in the PWRGD path
while placing resistors RC25 & RC130
1 2
1 2
10K_0402_5%
10K_0402_5%
12
+VCCIO_OUT
RC2010K_0402_5% @RC2010K_0402_5% @
RC2110K_0402_5% @RC2110K_0402_5% @
100_0402_1%
100_0402_1%
RC130
RC130
Title
Title
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
3
2012/07/01
2012/07/01
2012/07/01
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2014/07/01
2014/07/01
2014/07/01
Title
CPU (2/7) PM, XDP, CLK
CPU (2/7) PM, XDP, CLK
CPU (2/7) PM, XDP, CLK
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Date: Sheet of
Date: Sheet of
Date: Sheet of
Wednesday, March 27, 2013
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
1
6 69
6 69
6 69
1.0
1.0
1.0
5
DDRA_DQ[0..63]<11>
D D
C C
+VREF_CA_R
B B
+V_DDR_REFA_R
+V_DDR_REFB_R
DDRA_DQ0
DDRA_DQ1
DDRA_DQ2
DDRA_DQ3
DDRA_DQ4
DDRA_DQ5
DDRA_DQ6
DDRA_DQ7
DDRA_DQ8
DDRA_DQ9
DDRA_DQ10
DDRA_DQ11
DDRA_DQ12
DDRA_DQ13
DDRA_DQ14
DDRA_DQ15
DDRA_DQ16
DDRA_DQ17
DDRA_DQ18
DDRA_DQ19
DDRA_DQ20
DDRA_DQ21
DDRA_DQ22
DDRA_DQ23
DDRA_DQ24
DDRA_DQ25
DDRA_DQ26
DDRA_DQ27
DDRA_DQ28
DDRA_DQ29
DDRA_DQ30
DDRA_DQ31
DDRA_DQ32
DDRA_DQ33
DDRA_DQ34
DDRA_DQ35
DDRA_DQ36
DDRA_DQ37
DDRA_DQ38
DDRA_DQ39
DDRA_DQ40
DDRA_DQ41
DDRA_DQ42
DDRA_DQ43
DDRA_DQ44
DDRA_DQ45
DDRA_DQ46
DDRA_DQ47
DDRA_DQ48
DDRA_DQ49
DDRA_DQ50
DDRA_DQ51
DDRA_DQ52
DDRA_DQ53
DDRA_DQ54
DDRA_DQ55
DDRA_DQ56
DDRA_DQ57
DDRA_DQ58
DDRA_DQ59
DDRA_DQ60
DDRA_DQ61
DDRA_DQ62
DDRA_DQ63
AR15
AT14
AM14
AN14
AT15
AR14
AN15
AM15
AM9
AM8
AJ10
AK10
AM3
AN9
AN8
AR9
AT9
AR8
AT8
AK9
AK6
AK7
AF4
AF5
AF1
AF2
AG4
AG5
AG1
AG2
D12
D11
AJ9
AJ6
AJ7
J1
J2
J5
H5
H2
H1
J4
H4
F2
F1
D2
D3
D1
F3
C3
B3
B5
E6
A5
D6
D5
E5
B6
A6
E12
B11
A11
E11
B12
A12
F16
F13
SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63
SM_VREF
SA_DIMM_VREFDQ
SB_DIMM_VREFDQ
3 OF 9
3 OF 9
JCPUC
JCPUC
4
Haswell rPGA EDS
Haswell rPGA EDS
RSVD_AC7
SA_CK_N_0
SA_CK_P_0
SA_CKE_0
SA_CK_N_1
SA_CK_P_1
SA_CKE_1
SA_CK_N_2
SA_CK_P_2
SA_CKE_2
SA_CK_N_3
SA_CK_P_3
SA_CKE_3
SA_CS_N_0
SA_CS_N_1
SA_CS_N_2
SA_CS_N_3
SA_ODT_0
SA_ODT_1
SA_ODT_2
SA_ODT_3
SA_BS_0
SA_BS_1
SA_BS_2
RSVD_V10
SA_RAS
SA_WE
SA_CAS
SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14
SA_MA_15
SA_DQS_N_0
SA_DQS_N_1
SA_DQS_N_2
SA_DQS_N_3
SA_DQS_N_4
SA_DQS_N_5
SA_DQS_N_6
SA_DQS_N_7
SA_DQS_P_0
SA_DQS_P_1
SA_DQS_P_2
SA_DQS_P_3
SA_DQS_P_4
SA_DQS_P_5
SA_DQS_P_6
SA_DQS_P_7
TEL_HASWELL_HAS WELL
TEL_HASWELL_HAS WELL
IN
IN
AC7
U4
V4
AD9
U3
V3
AC9
U2
V2
AD8
U1
V1
AC8
M7
L9
M9
M10
M8
L7
L8
L10
V5
U5
AD1
V10
U6
U7
U8
V8
DDRA_MA0
AC6
DDRA_MA1
V9
DDRA_MA2
U9
DDRA_MA3
AC5
DDRA_MA4
AC4
DDRA_MA5
AD6
DDRA_MA6
AC3
DDRA_MA7
AD5
DDRA_MA8
AC2
DDRA_MA9
V6
DDRA_MA10
AC1
DDRA_MA11
AD4
DDRA_MA12
V7
DDRA_MA13
AD3
DDRA_MA14
AD2
DDRA_MA15
AP15
DDRA_DQS#0
AP8
DDRA_DQS#1
AJ8
DDRA_DQS#2
AF3
DDRA_DQS#3
J3
DDRA_DQS#4
E2
DDRA_DQS#5
C5
DDRA_DQS#6
C11
DDRA_DQS#7
AP14
DDRA_DQS0
AP9
DDRA_DQS1
AK8
DDRA_DQS2
AG3
DDRA_DQS3
H3
DDRA_DQS4
E3
DDRA_DQS5
C6
DDRA_DQS6
C12
DDRA_DQS7+VREF_CA_R
T64 PAD@T64 PAD@
DDRA_CLK0# <11>
DDRA_CLK0 <11>
DDRA_CKE0 <11>
DDRA_CLK1# <11>
DDRA_CLK1 <11>
DDRA_CKE1 <11>
DDRA_CS0# <11>
DDRA_CS1# <11>
DDRA_ODT0 <11>
DDRA_ODT1 <11>
DDRA_BS0# <11>
DDRA_BS1# <11>
DDRA_BS2# <11>
DDRA_RAS# <11>
DDRA_WE# <11>
DDRA_CAS# <11>
DDRA_MA[0..15] <11>
DDRA_DQS#[0..7] <11>
DDRA_DQS[0..7] <11>
3
DDRB_DQ[0..63]<12>
DDRB_DQ0
DDRB_DQ1
DDRB_DQ2
DDRB_DQ3
DDRB_DQ4
DDRB_DQ5
DDRB_DQ6
DDRB_DQ7
DDRB_DQ8
DDRB_DQ9
DDRB_DQ10
DDRB_DQ11
DDRB_DQ12
DDRB_DQ13
DDRB_DQ14
DDRB_DQ15
DDRB_DQ16
DDRB_DQ17
DDRB_DQ18
DDRB_DQ19
DDRB_DQ20
DDRB_DQ21
DDRB_DQ22
DDRB_DQ23
DDRB_DQ24
DDRB_DQ25
DDRB_DQ26
DDRB_DQ27
DDRB_DQ28
DDRB_DQ29
DDRB_DQ30
DDRB_DQ31
DDRB_DQ32
DDRB_DQ33
DDRB_DQ34
DDRB_DQ35
DDRB_DQ36
DDRB_DQ37
DDRB_DQ38
DDRB_DQ39
DDRB_DQ40
DDRB_DQ41
DDRB_DQ42
DDRB_DQ43
DDRB_DQ44
DDRB_DQ45
DDRB_DQ46
DDRB_DQ47
DDRB_DQ48
DDRB_DQ49
DDRB_DQ50
DDRB_DQ51
DDRB_DQ52
DDRB_DQ53
DDRB_DQ54
DDRB_DQ55
DDRB_DQ56
DDRB_DQ57
DDRB_DQ58
DDRB_DQ59
DDRB_DQ60
DDRB_DQ61
DDRB_DQ62
DDRB_DQ63
AR18
AT18
AM17
AM18
AR17
AT17
AN17
AN18
AT12
AR12
AN12
AM11
AT11
AR11
AM12
AN11
AR5
AR6
AM5
AM6
AT5
AT6
AN5
AN6
AK4
AM1
AN1
AK2
AK1
G10
D15
D14
AJ4
AJ1
AJ2
J10
E15
A15
B15
E14
A14
B14
L2
M2
L4
M4
L1
M1
L5
M5
G7
J8
G8
G9
J7
J9
A8
B8
A9
B9
D8
E8
D9
E9
SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63
4 OF 9
4 OF 9
2
Haswell rPGA EDS
JCPUD
JCPUD
I
I
N
N
Haswell rPGA EDS
SB_DQS_N_0
SB_DQS_N_1
SB_DQS_N_2
SB_DQS_N_3
SB_DQS_N_4
SB_DQS_N_5
SB_DQS_N_6
SB_DQS_N_7
SB_DQS_P_0
SB_DQS_P_1
SB_DQS_P_2
SB_DQS_P_3
SB_DQS_P_4
SB_DQS_P_5
SB_DQS_P_6
SB_DQS_P_7
TEL_HASWELL_HAS WELL
TEL_HASWELL_HAS WELL
RSVD
SB_CKN0
SB_CK0
SB_CKE_0
SB_CKN1
SB_CK1
SB_CKE_1
SB_CKN2
SB_CK2
SB_CKE_2
SB_CKN3
SB_CK3
SB_CKE_3
SB_CS_N_0
SB_CS_N_1
SB_CS_N_2
SB_CS_N_3
SB_ODT_0
SB_ODT_1
SB_ODT_2
SB_ODT_3
SB_BS_0
SB_BS_1
SB_BS_2
RSVD
SB_RAS
SB_WE
SB_CAS
SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14
SB_MA_15
AG8
Y4
AA4
AF10
Y3
AA3
AG10
Y2
AA2
AG9
Y1
AA1
AF9
P4
R2
P3
P1
R4
R3
R1
P2
R7
P8
AA9
R10
R6
P6
P7
R8
DDRB_MA0
Y5
DDRB_MA1
Y10
DDRB_MA2
AA5
DDRB_MA3
Y7
DDRB_MA4
AA6
DDRB_MA5
Y6
DDRB_MA6
AA7
DDRB_MA7
Y8
DDRB_MA8
AA10
DDRB_MA9
R9
DDRB_MA10
Y9
DDRB_MA11
AF7
DDRB_MA12
P9
DDRB_MA13
AA8
DDRB_MA14
AG7
DDRB_MA15
AP18
DDRB_DQS#0
AP11
DDRB_DQS#1
AP5
DDRB_DQS#2
AJ3
DDRB_DQS#3
L3
DDRB_DQS#4
H9
DDRB_DQS#5
C8
DDRB_DQS#6
C14
DDRB_DQS#7
AP17
DDRB_DQS0
AP12
DDRB_DQS1
AP6
DDRB_DQS2
AK3
DDRB_DQS3
M3
DDRB_DQS4
H8
DDRB_DQS5
C9
DDRB_DQS6
C15
DDRB_DQS7
T63 PAD@ T63 PAD@
DDRB_CLK0# <12>
DDRB_CLK0 <12>
DDRB_CKE0 <12>
DDRB_CLK1# <12>
DDRB_CLK1 <12>
DDRB_CKE1 <12>
DDRB_CS0# <12>
DDRB_CS1# <12>
DDRB_ODT0 <12>
DDRB_ODT1 <12>
DDRB_BS0# <12>
DDRB_BS1# <12>
DDRB_BS2# <12>
DDRB_RAS# <12>
DDRB_WE# <12>
DDRB_CAS# <12>
DDRB_MA[0..15] <12>
DDRB_DQS#[0..7] <12>
DDRB_DQS[0..7] <12>
1
DRAMRST_CNTRL<6>
+VREF_DQ_DIMMA_R
+VREF_DQ_DIMMB_R
A A
5
6/8: Add M3 Circuit (Processor Generated SO-DIMM VREF_DQ)
4
DRAMRST_CNTRL
DRAMRST_CNTRL
2
G
G
QC11 BSS138_SOT23
QC11 BSS138_SOT23
1 3
D
S
D
S
@
@
1 2
RC1548 0_0402_ 5%RC1548 0_0402_5%
1 2
RC92 0_0402_5%RC92 0_0402_5%
@
@
1 3
D
S
D
S
QC9 BSS138_SOT23
QC9 BSS138_SOT23
G
G
2
+V_DDR_REFA_R
+V_DDR_REFB_R
12
12
RC143
@ RC143
@
RC144
@RC144
@
1K_0402_1%
1K_0402_1%
1K_0402_1%
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
1K_0402_1%
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
2012/07/01
2012/07/01
2012/07/01
3
Deciphered Date
Deciphered Date
Deciphered Date
2
2014/07/01
2014/07/01
2014/07/01
Title
Title
Title
CPU (3/7) DDRIII
CPU (3/7) DDRIII
CPU (3/7) DDRIII
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Date: Sheet of
Date: Sheet of
Date: Sheet of
Wednesday, March 27, 2013
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
1
7 69
7 69
7 69
1.0
1.0
1.0
5
4
3
2
1
CFG STRAPS for CPU
CFG2
D D
PEG Static Lane Reversal - CFG2 is for the 16x
*
20120829 VA1
Add net for add HDMI MUX
CPU_HDMI_TX2-<37>
CPU_HDMI_TX2+<37>
CPU_HDMI_TX1-<37>
CPU_HDMI_TX1+<37>
CPU_HDMI_TX0-<37>
CPU_HDMI_TX0+<37>
CPU_HDMI_CLK-<37>
check CLK item
CPU_HDMI_CLK+<37>
COMPENSATION PU FOR eDP
12
C C
EDP_COMP
CAD Note:Trace width=20 mils ,Spacing=25mil,
Max length=100 mils.
+VCCIOA_OUT
12
RC124.9_0402_1% RC12 4.9_0402_1%
+VCCIO_OUT
10K_0402_5%
10K_0402_5%
RC45 49.9_0402_1%RC45 49.9_0402_1%
RC58 49.9_0402_1%RC58 49.9_0402_1%
RC59 49.9_0402_1%RC59 49.9_0402_1%
RC65
RC65
H_CPU_TESTLO
12
CFG_RCOMP
12
H_CPU_RSVD
HPD INVERSION FOR EDP
1 2
EDP_HPD_IN#
BSS138_SOT23
BSS138_SOT23
13
D
D
QC6
QC6
CPU_EDP_HPD<38>
B B
A A
2
G
G
S
100K_0402_5%
100K_0402_5%
12
RC75
RC75
S
T70 PAD@T70 PAD@
T71 PAD@T71 PAD@
T72 PAD@T72 PAD@
T73 PAD@T73 PAD@
T77 PAD@T77 PAD@
T76 PAD@T76 PAD@
T80 PAD@T80 PAD@
T79 PAD@T79 PAD@
T94 PAD@T94 PAD@
+VCC_CORE
T82 PAD@T82 PAD@
T81 PAD@T81 PAD@
T85 PAD@T85 PAD@
T84 PAD@T84 PAD@
T83 PAD@T83 PAD@
T173PAD@ T173PAD@
T116PAD@ T116PAD@
T117PAD@ T117PAD@
T126PAD@ T126PAD@
T129PAD@ T129PAD@
T130PAD@ T130PAD@
T131PAD@ T131PAD@
T132PAD@ T132PAD@
T133PAD@ T133PAD@
T134PAD@ T134PAD@
T135PAD@ T135PAD@
T136PAD@ T136PAD@
T137PAD@ T137PAD@
T138PAD@ T138PAD@
T142PAD@ T142PAD@
T143PAD@ T143PAD@
H_CPU_RSVD
H_CPU_TESTLO
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
Haswell rPGA EDS
Haswell rPGA EDS
T28
DDIB_TXBN_0
U28
DDIB_TXBP_0
T30
DDIB_TXBN_1
U30
DDIB_TXBP_1
U29
DDIB_TXBN_2
V29
DDIB_TXBP_2
U31
DDIB_TXBN_3
V31
DDIB_TXBP_3
T34
DDIC_TXCN_0
U34
DDIC_TXCP_0
U35
DDIC_TXCN_1
V35
DDIC_TXCP_1
U32
DDIC_TXCN_2
T32
DDIC_TXCP_2
U33
DDIC_TXCN_3
V33
DDIC_TXCP_3
P29
DDID_TXDN_0
R29
DDID_TXDP_0
N28
DDID_TXDN_1
P28
DDID_TXDP_1
P31
DDID_TXDN_2
R31
DDID_TXDP_2
N30
DDID_TXDN_3
P30
DDID_TXDP_3
INTEL_HASWELL_HAS WELL
INTEL_HASWELL_HAS WELL
AT1
AT2
AD10
A34
A35
W29
W28
G26
W33
AL30
AL29
F25
C35
B35
AL25
W30
W31
W34
AT20
CFG0
AR20
AP20
AP22
AT22
AN22
AT25
AN23
AR24
AT23
AN20
AP24
AP26
AN25
AN26
AP25
Haswell rPGA EDS
Haswell rPGA EDS
RSVD_TP
RSVD_TP
RSVD
RSVD_TP
RSVD_TP
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
VCC
RSVD_TP
RSVD_TP
RSVD_TP
RSVD
RSVD
TESTLO
CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
INT
INT
EL_HASWELL_HASW ELL
EL_HASWELL_HASW ELL
JCPUH
JCPUH
eDP
eDP
EDP_AUXN
EDP_AUXP
EDP_HPD
EDP_RCOMP
RSVD
EDP_TXN_0
EDP_TXP_0
EDP_TXN_1
EDP_TXP_1
FDI_TXN_0
FDI_TXP_0
FDI_TXN_1
FDI_TXP_1
DDI
DDI
8 OF 9
8 OF 9
JCPUI
JCPUI
M27
N27
P27
E24
R27
P35
R35
N34
P34
P33
R33
N32
P32
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
CFG_RCOMP
CFG_16
CFG_18
CFG_17
CFG_19
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD_TP
RSVD_TP
RSVD_TP
RSVD
RSVD
RSVD
RSVD
9 OF 9
9 OF 9
CPU_EDP_AUX#
CPU_EDP_AUX
EDP_HPD_IN#
EDP_COMP
CPU_EDP_TX0CPU_EDP_TX0+
CPU_EDP_TX1CPU_EDP_TX1+
FDI_CTX_PRX_N0
FDI_CTX_PRX_P0
FDI_CTX_PRX_N1
FDI_CTX_PRX_P1
C23
B23
D24
D23
AT31
AR21
AR23
AP21
AP23
AR33
G6
AM27
AM26
F5
AM2
K6
E18
U10
P10
B1
NC
A2
AR1
E21
E20
AP27
AR26
AL31
AL32
CFG_RCOMP
CFG16
CFG18
CFG17
CFG19
CPU_EDP_AUX# <38>
CPU_EDP_AUX <38>
T69PAD @T69PAD @
CPU_EDP_TX0- <38>
CPU_EDP_TX0+ <38>
CPU_EDP_TX1- <38>
CPU_EDP_TX1+ <38>
FDI_CTX_PRX_N0 <15>
FDI_CTX_PRX_P0 <15>
FDI_CTX_PRX_N1 <15>
FDI_CTX_PRX_P1 <15>
T86PAD @T86PAD @
T78PAD @T78PAD @
T87PAD @T87PAD @
T88PAD @T88PAD @
T156PAD @T156PAD @
T164PAD @T164PAD @
T165PAD @T165PAD @
T166PAD @T166PAD @
T91PAD @T91PAD @
T90PAD @T90PAD @
T92PAD @T92PAD @
T89PAD @T89PAD @
T93PAD @T93PAD @
T95PAD @T95PAD @
T104PAD @T104PAD @
T96PAD @T96PAD @
T98PAD @T98PAD @
T97PAD @T97PAD @
T100PAD @T100PAD @
T99PAD @T99PAD @
T102PAD @T102PAD @
T101PAD @T101PAD @
CFG[6:5]
CFG2
Display Port Presence Strap
1 : Disabled; No Physical Display Port
CFG4
attached to Embedded Display Port
0 : Enabled; An external Display Port device is
*
connected to the Embedded Display Port
CFG5
CFG6
11: (Default) x16 - Device 1 functions 1 and 2 disabled
10: x8, x8 - Device 1 function 1 enabled ; function 2
*
disabled
01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
*
CFG7
1K_0402_1%
1K_0402_1%
12
@RC76
@
RC76
1:(Default) Normal Operation; Lane #
definition matches socket pin map definition
0:Lane Reversed
CFG4
1K_0402_1%
1K_0402_1%
1K_0402_1%
1K_0402_1%
12
12
@RC83
@
RC83
RC85
RC85
1K_0402_1%
1K_0402_1%
12
RC77
RC77
PCIE Port Bifurcation Straps
CFG7
1K_0402_1%
1K_0402_1%
12
@RC86
@
RC86
PEG DEFER TRAINING
1: (Default) PEG Train immediately
following xxRESETB de assertion
0: PEG Wait for BIOS for training
Title
Title
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
3
2012/07/01
2012/07/01
2012/07/01
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2014/07/01
2014/07/01
2014/07/01
Title
CPU (4/7) RSVD,CFG
CPU (4/7) RSVD,CFG
CPU (4/7) RSVD,CFG
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Date: Sheet of
Date: Sheet of
Date: Sheet of
Wednesday, March 27, 2013
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
1
8 69
8 69
8 69
1.0
1.0
1.0
5
4
3
2
1
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AA26
AA28
AA34
AA30
AA32
AB26
AB29
AB25
AB27
AB28
AB30
AB31
AB33
AB34
AB32
AC26
AB35
AC28
AD25
AC30
AD28
AC32
AD31
AC34
AD34
AD26
AD27
AD29
AD30
AD32
AD33
AD35
AE26
AE32
AE28
AE30
AG28
AG34
AE34
AF25
AF26
AF27
AF28
AF29
AF30
AF31
AF32
AF33
AF34
AF35
AG26
AH26
AH29
AG30
AG32
AH32
AH35
AH25
AH27
AH28
AH30
AH31
AH33
AH34
AJ25
AJ26
AJ27
AJ28
AJ29
AJ30
AJ31
AJ32
AJ33
AJ34
AJ35
G25
H25
J25
K25
L25
M25
N25
P25
R25
T25
U25
U26
V25
V26
W26
W27
+VCC_CORE
Haswell rPGA EDS
Haswell rPGA EDS
AB11
AB2
AB5
AB8
AE11
AE2
AE5
AE8
AH11
K11
N11
W11
N26
K26
AL27
AK27
AL35
E17
AN35
A23
W32
AL16
AL13
AM28
AM29
AL28
AP35
H27
AP34
AT35
AR35
AR32
AL26
AT34
AL22
AT33
AM21
AM25
AM22
AM20
AM24
AL19
AM23
AT32
K27
L27
T27
V27
N8
T11
T2
T5
T8
W2
W5
W8
F22
J27
Y25
Y26
Y27
Y28
Y29
Y30
Y31
Y32
Y33
Y34
Y35
RSVD
RSVD
RSVD
RSVD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
RSVD
VCC
RSVD
RSVD
VCC_SENSE
RSVD
VCCIO_OUT
VCCIO2PCH
VCCIOA_OUT
RSVD
RSVD
VSS
RSVD
VIDALERT
VIDSCLK
VIDSOUT
VSS
PWR_DEBUG
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
TEL_HASWELL_HAS WELL
TEL_HASWELL_HAS WELL
IN
IN
T107 PAD@ T107 PAD@
T106 PAD@ T106 PAD@
D D
+1.35V
CC151 0.1U_04 02_25V6KCC151 0.1U_04 02_25V6K
CC152 0.1U_04 02_25V6KCC152 0.1U_04 02_25V6K
C C
VCC_SENSE
VCCSENSE<64>
need connect to power
VSSSENSE<64>
B B
+1.35V_CPU_VDDQ
10U_0603_6.3V6M
10U_0603_6.3V6M
1
CC171
CC171
2
22U_0805_6.3V6M
22U_0805_6.3V6M
1
CC33
A A
CC33
2
+VCC_CORE
100_0402_1%
100_0402_1%
12
RC66
RC66
CAD Note: RC67 SHOULD BE PLACED CLOSE TO CPU
VCCSENSE VCCSENSE_R
RC67
RC67
12
R_short 0_0402_5%
R_short 0_0402_5%
CAD Note: RC68 SHOULD BE PLACED CLOSE TO CPU
VSSSENSE VSSSENSE_R
RC68
RC68
100_0402_1%
100_0402_1%
12
RC70
RC70
12
R_short 0_0402_5%
R_short 0_0402_5%
VDDQ DECOUPLING
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1
1
CC169
CC169
CC170
CC170
2
2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1
1
CC35
CC35
CC34
CC34
2
2
@
@
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1
CC168
CC168
2
22U_0805_6.3V6M
22U_0805_6.3V6M
1
CC36
CC36
2
10U_0603_6.3V6M
1
1
CC161
CC161
CC162
CC162
2
2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1
1
CC37
CC37
CC38
CC38
2
2
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1
1
CC163
CC163
2
2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1
1
CC39
CC39
2
2
RC4
RC4
+1.05VS +VCCIO_OUT
VSSSENSE_R <10>
Power
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1
CC164
CC164
CC165
CC165
2
22U_0805_6.3V6M
22U_0805_6.3V6M
1
CC41
CC41
CC40
CC40
2
@
@
330U_D2_2VM_R6M
330U_D2_2VM_R6M
330U_D2_2VM_R6M
330U_D2_2VM_R6M
1
1
CC167
CC167
CC172
1
CC166
CC166
@
@
2
22U_0805_6.3V6M
22U_0805_6.3V6M
1
CC42
CC42
2
CC172
+
+
+
+
@
@
2
2
22U_0805_6.3V6M
22U_0805_6.3V6M
1
CC43
CC43
2
0_0603_5% @
0_0603_5% @
VR_SVID_ALRT#<64>
VR_SVID_CLK<64>
VR_SVID_DAT<64>
+1.05VS
150_0402_1%
150_0402_1%
12
@
@
CPU_PWR_DEBU G
10K_0402_5%
10K_0402_5%
12
12
RC61 43_0402_5%RC61 43_0402_5%
1 2
12
RC63
RC63
@
@
130_0402_1%
130_0402_1%
+VCCIO_OUT
RC69
RC69
CPU_PWR_DEBU G <6>
@
@
RC71
RC71
need connect to power
T112 PAD@ T112 PAD@
T113 PAD@ T113 PAD@
12
12
placement
T115 PAD@ T115 PAD@
+VCC_CORE
T151 PAD@ T151 PAD@
T152 PAD@ T152 PAD@
T153 PAD@ T153 PAD@
+VCCIO_OUT
+1.05VS
+VCCIOA_OUT
T160 PAD@ T160 PAD@
T159 PAD@ T159 PAD@
T154 PAD@ T154 PAD@
VR_SVID_ALRT#_R
VR_SVID_CLK
VR_SVID_DAT
CPU_PWR_DEBU G
T157 PAD@ T157 PAD@
T158 PAD@ T158 PAD@
T162 PAD@ T162 PAD@
T163 PAD@ T163 PAD@
+1.35V_CPU_VDDQ
VCCSENSE_R
+VCC_CORE
JCPUE
JCPUE
5 OF 9
5 OF 9
Title
Title
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
3
2012/07/01
2012/07/01
2012/07/01
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2014/07/01
2014/07/01
2014/07/01
Title
CPU (5/7) PWR, BYPASS
CPU (5/7) PWR, BYPASS
CPU (5/7) PWR, BYPASS
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Date: Sheet of
Date: Sheet of
Date: Sheet
Wednesday, March 27, 2013
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
1
9 69
9 69
9 69
of
1.0
1.0
1.0
5
Haswell rPGA EDS
Haswell rPGA EDS
A10
VSS
A13
VSS
A16
VSS
A19
VSS
A22
VSS
A25
VSS
A27
VSS
A29
VSS
A3
VSS
A31
VSS
A33
VSS
A4
D D
C C
B B
AA11
AA25
AA27
AA31
AA29
AB1
AB10
AA33
AA35
AB3
AC25
AC27
AB4
AB6
AB7
AB9
AC11
AD11
AC29
AC31
AC33
AC35
AD7
AE1
AE10
AE25
AE29
AE3
AE27
AE35
AE4
AE6
AE7
AE9
AF11
AF6
AF8
AG11
AG25
AE31
AG31
AE33
AG6
AH1
AH10
AH2
AG27
AG29
AH3
AG33
AG35
AH4
AH5
AH6
AH7
AH8
AH9
AJ11
AK11
AK25
AK26
AK28
AK29
AK30
AK32
VSS
A7
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AJ5
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
E19
VSS
JCPUF
JCPUF
TEL_HASWELL_HAS WELL
TEL_HASWELL_HAS WELL
IN
IN
For Deep S3
+3VALW
12
RC1537
@RC 1537
13
D
D
2
G
G
S
S
@
RUN_ON_CPU1.5VS3#
@
@
QC156
QC156
2N7002KW_SOT323-3
2N7002KW_SOT323-3
2
G
G
100K_0402_5%
100K_0402_5%
RC1538
RC1538
1 2
@
A A
SUSP<40,55,61>
CPU1.5V_S3_GATE<46>
@
0_0402_5%
0_0402_5%
4
AK34
VSS
AK5
VSS
AL1
VSS
AL10
VSS
AL11
VSS
AL12
VSS
AL14
VSS
AL15
VSS
AL17
VSS
AL18
VSS
AL2
VSS
AL20
VSS
AL21
VSS
AL23
VSS
E22
VSS
AL3
VSS
AL4
VSS
AL5
VSS
AL6
VSS
AL7
VSS
AL8
VSS
AL9
VSS
AM10
VSS
AM13
VSS
AM16
VSS
AM19
VSS
E25
VSS
AM32
VSS
AM4
VSS
AM7
VSS
AN10
VSS
AN13
VSS
AN16
VSS
AN19
VSS
AN2
VSS
AN21
VSS
AN24
VSS
AN27
VSS
AN30
VSS
AN34
VSS
AN4
VSS
AN7
VSS
AP1
VSS
AP10
VSS
AP13
VSS
AP16
VSS
AP19
VSS
AP4
VSS
AP7
VSS
W25
VSS
AR10
RSVD
AR13
VSS
AR16
VSS
AR19
VSS
AR2
VSS
AR22
VSS
AR25
VSS
AR28
VSS
AR31
VSS
AR34
VSS
AR4
VSS
AR7
VSS
AT10
VSS
AT13
VSS
AT16
VSS
AT19
VSS
AT21
VSS
AT24
VSS
AT27
VSS
AT3
VSS
AT30
VSS
AT4
VSS
AT7
VSS
B10
VSS
B13
VSS
B16
VSS
B19
VSS
B2
VSS
B22
VSS
6 OF 9
6 OF 9
+VSB
12
R56 need to chec k on SDV
RC56
@ RC56
@
100K_0402_5%
100K_0402_5%
RUN_ON_CPU1.5VS3
13
D
D
@
@
QC4
QC4
2N7002KW_SOT323-3
2N7002KW_SOT323-3
S
S
+1.35V_CPU_VDDQ
@ J15
@
2
JUMP_43X79
JUMP_43X79
+1.35V
12
RC1546
@ RC1546
@
470K_0402_5%
470K_0402_5%
1 2
470K_0402_5%
470K_0402_5%
1 2
CC287 0.1U_0402_10V6KCC287 0.1U_0402_10V6K
1 2
CC286 0.1U_0402_10V6KCC286 0.1U_0402_10V6K
1 2
CC96 0.1U_0402_10V6KCC96 0.1U_0402_10V6K
1 2
CC95 0.1U_0402_10V6KCC95 0.1U_0402_10V6K
UC3
UC3
8
7
6
5
AO4304L_SO8
AO4304L_SO8
RC1349
4
@RC134 9
@
1
@
@
2
J15
112
1
2
3
@
@
AO4304L
Vgs=10V,Id=18A,
Rds<6.7m ohm
P/N: SB00000RV00
CC97
CC97
0.01U 50V K X7R 0603
0.01U 50V K X7R 0603
3
+1.35V_CPU_VDDQ+1.35V
+1.35V_CPU_VDDQ
12
RC1487
@ RC1487
@
470_0603_5%
470_0603_5%
QC5
QC5
13
D
D
@
@
S
S
2
SUSP
G
G
2N7002KW_SOT323-3
2N7002KW_SOT323-3
Haswell rPGA EDS
Haswell rPGA EDS
B34
VSS
B4
VSS
B7
VSS
C1
VSS
C10
VSS
C13
VSS
C16
VSS
C19
VSS
C2
VSS
C22
VSS
C24
VSS
C26
VSS
C28
VSS
C30
VSS
C32
VSS
C34
VSS
C4
VSS
C7
VSS
D10
VSS
D13
VSS
D16
VSS
D19
VSS
D22
VSS
D25
VSS
D27
VSS
D29
VSS
D31
VSS
D33
VSS
D35
VSS
D4
VSS
D7
VSS
E1
VSS
E10
VSS
E13
VSS
E16
VSS
E4
VSS
E7
VSS
F10
VSS
F11
VSS
F12
VSS
F14
VSS
F15
VSS
F17
VSS
F18
VSS
F20
VSS
F21
VSS
F23
VSS
F24
VSS
F26
VSS
F28
VSS
F30
VSS
F32
VSS
F34
VSS
F4
VSS
F6
VSS
F7
VSS
F8
VSS
F9
VSS
G1
VSS
G11
VSS
G2
VSS
G27
VSS
G29
VSS
G3
VSS
G31
VSS
G33
VSS
G35
VSS
G4
VSS
G5
VSS
H10
VSS
H26
VSS
H6
VSS
H7
VSS
J11
VSS
J26
VSS
J28
RSVD
J30
VSS
J32
VSS
J34
VSS
J6
VSS
K1
VSS
TEL_HASWELL_HAS WELL
TEL_HASWELL_HAS WELL
IN
IN
JCPUG
JCPUG
2
RSVD
RSVD
RSVD
RSVD
VSS_SENSE
RSVD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
7 OF 9
7 OF 9
K10
K2
K29
K3
K31
K33
K35
K4
K5
K7
K8
K9
L11
L26
L6
M11
M26
M28
M30
M32
M34
M6
N1
N10
N2
N29
N3
N31
N33
N35
N4
N5
N6
N7
N9
P11
P26
P5
R11
R26
R28
R30
R32
R34
R5
T1
T10
T29
T3
T31
T33
T35
T4
T6
T7
T9
U11
U27
V11
V28
V30
V32
V34
W1
W10
W3
W35
W4
W6
W7
W9
Y11
H11
AL24
F19
T26
AK35
AK33
RC237 0_0402_5%RC237 0_0402_5%
1 2
T65PAD @T65PAD @
1
RC238 0_0402_5%RC238 0_0402_5%
VSSSENSE_R <9>
1 2
Title
Title
RUN_ON_CPU1.5VS3# <6>
5
4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
3
2012/07/01
2012/07/01
2012/07/01
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2014/07/01
2014/07/01
2014/07/01
Title
CPU (6/7) PWR
CPU (6/7) PWR
CPU (6/7) PWR
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Date: Sheet of
Date: Sheet of
Date: Sheet of
Wednesday, March 27, 2013
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
1
10 69
10 69
10 69
1.0
1.0
1.0
5
4
3
2
1
DDR3 SO-DIMM A
+VREF_DQ_DIMMA_R
1 2
0_0402_5%
0_0402_5%
D D
1
CD180
CD180
0.1U_0402_10V6K
0.1U_0402_10V6K
2
12
RD90
RD90
24.9_0402_1%
24.9_0402_1%
C C
B B
A A
RD91
RD91
20120727 VA
SWAP DQ for layout
+3VS
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
+1.35V
12
RD78
RD78
1K_0402_1%
1K_0402_1%
+VREF_DQ_DIMMA
12
RD79
RD79
1
CD141
CD141
2
1K_0402_1%
1K_0402_1%
20120727 VA
SWAP DQ for layout
DDRA_CKE0<7>
DDRA_BS2#<7>
DDRA_CLK0<7>
DDRA_CLK0#<7>
DDRA_BS0#<7>
DDRA_WE#<7>
DDRA_CAS#<7>
DDRA_CS1#<7>
1
CD290
CD290
2
5
1
CD140
CD140
2
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
1
CD162
CD162
0.1U_0402_10V6K
0.1U_0402_10V6K
2
+1.35V+1.35V
3A@1.5V
JDDRL1
JDDRL1
VREF_DQ1VSS1
3
VSS2
DDRA_DQ4
DDRA_DQ0
0.1U_0402_10V6K
0.1U_0402_10V6K
DDRA_DQ13 DDRA_DQ15
DDRA_DQ12
DDRA_DQS#1
DDRA_DQS1
DDRA_DQ9
DDRA_DQ8
DDRA_DQ20
DDRA_DQ21
DDRA_DQS#2
DDRA_DQS2
DDRA_DQ23
DDRA_DQ19
DDRA_DQ25
DDRA_DQ28
DDRA_DQ27
DDRA_DQ26
DDRA_CKE0
DDRA_BS2#
DDRA_MA12
DDRA_MA9
DDRA_MA8
DDRA_MA5
DDRA_MA3
DDRA_MA1
DDRA_CLK0
DDRA_CLK0#
DDRA_MA10
DDRA_BS0#
DDRA_WE#
DDRA_CAS# DDRA_ODT0
DDRA_MA13
DDRA_CS1#
DDRA_DQ32
DDRA_DQ33
DDRA_DQS#4
DDRA_DQS4
DDRA_DQ37 DDRA_DQ35
DDRA_DQ36
DDRA_DQ40
DDRA_DQ41
DDRA_DQ42
DDRA_DQ44
DDRA_DQ52
DDRA_DQ53
DDRA_DQS#6
DDRA_DQS6
DDRA_DQ48
DDRA_DQ50
DDRA_DQ61 DDRA_DQ57
DDRA_DQ60
DDRA_DQ58
DDRA_DQ59
RD82
RD82
1 2
10K_0402_5%
10K_0402_5%
12
RD83
RD83
10K_0402_5%
10K_0402_5%
5
DQ0
7
DQ1
9
VSS4
11
DM0
13
VSS5
15
DQ2
17
DQ3
19
VSS7
21
DQ8
23
DQ9
25
VSS9
27
DQS#1
DQS129RESET#
VSS1131VSS12
33
DQ10
35
DQ11
VSS1337VSS14
39
DQ16
41
DQ17
VSS1543VSS16
45
DQS#2
47
DQS2
49
VSS18
51
DQ18
53
DQ19
55
VSS20
57
DQ24
59
DQ25
VSS2261DQS#3
63
DM3
VSS2365VSS24
67
DQ26
69
DQ27
VSS2571VSS26
73
CKE0
75
VDD1
77
NC1
79
BA2
81
VDD3
83
A12/BC#
85
A9
87
VDD5
89
A8
91
A5
93
VDD7
95
A3
97
A1
99
VDD9
101
CK0
103
CK0#
105
VDD11
107
A10/AP
109
BA0
111
VDD13
113
WE#
115
CAS#
117
VDD15
119
A13
121
S1#
123
VDD17
125
NCTEST
127
VSS27
129
DQ32
131
DQ33
133
VSS29
135
DQS#4
137
DQS4
139
VSS32
141
DQ34
143
DQ35
145
VSS34
147
DQ40
149
DQ41
151
VSS36
153
DM5
155
VSS37
157
DQ42
159
DQ43
161
VSS39
163
DQ48
165
DQ49
167
VSS41
169
DQS#6
171
DQS6
173
VSS44
175
DQ50
177
DQ51
179
VSS46
181
DQ56
183
DQ57
185
VSS48
187
DM7
189
VSS49
191
DQ58
193
DQ59
195
VSS51
197
SA0
199
VDDSPD
201
SA1
203
VTT1
205
G1
LCN_DAN06-K4806-0102
LCN_DAN06-K4806-0102
ME@
ME@
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
DQ14
DQ15
DQ20
DQ21
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS3
DQ30
DQ31
CKE1
VDD2
VDD4
VDD6
VDD8
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
A15
80
A14
82
84
A11
86
A7
88
90
A6
92
A4
94
96
A2
98
A0
100
102
104
106
108
110
112
114
S0#
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
G2
4
DDRA_DQ7
DDRA_DQ6
DDRA_DQS#0
DDRA_DQS0
DDRA_DQ2DDRA_DQ1
DDRA_DQ3DDRA_DQ5
DDRA_DQ14
DDR3_DRAMRST#
DDRA_DQ11
DDRA_DQ10
DDRA_DQ16
DDRA_DQ17
DDRA_DQ22
DDRA_DQ18
DDRA_DQ31
DDRA_DQ29
DDRA_DQS#3
DDRA_DQS3
DDRA_DQ24
DDRA_DQ30
DDRA_CKE1
DDRA_MA15
DDRA_MA14
DDRA_MA11
DDRA_MA7
DDRA_MA6
DDRA_MA4
DDRA_MA2
DDRA_MA0
DDRA_CLK1
DDRA_CLK1#
DDRA_BS1#
DDRA_RAS#
DDRA_CS0#
DDRA_ODT1
DDRA_DQ38
DDRA_DQ34
DDRA_DQ39
DDRA_DQ45
DDRA_DQ47
DDRA_DQS#5
DDRA_DQS5
DDRA_DQ43
DDRA_DQ46
DDRA_DQ49
DDRA_DQ51
DDRA_DQ54
DDRA_DQ55
DDRA_DQ56
DDRA_DQS#7
DDRA_DQS7
DDRA_DQ62
DDRA_DQ63
SMB_DATA_S3
SMB_CLK_S3
0.65A@0.75V
0.65A@0.75V
0.65A@0.75V0.65A@0.75V
For RF request
0.047U_0402_16V4Z
0.047U_0402_16V4Z
1
CD51
CD51
CD52
CD52
@
@
@
@
2
DDR3_DRAMRST# <12,6>
20120727 VA
SWAP DQ for layout
DDRA_CKE1 <7>
DDRA_CLK1 <7>
DDRA_CLK1# <7>
DDRA_BS1# < 7>
DDRA_RAS# <7>
DDRA_CS0# <7>
DDRA_ODT0 <7>
DDRA_ODT1 <7>
0.1U_0402_10V6K
0.1U_0402_10V6K
1
CD149
CD149
+0.675VS
1
CD150
CD150
2
2
20120727 VA
SWAP DQ for layout
SMB_DATA_S3 <12,17,40,47>
SMB_CLK_S3 <12,17,40,47>
0.047U_0402_16V4Z
0.047U_0402_16V4Z
0.047U_0402_16V4Z
0.047U_0402_16V4Z
1
1
CD53
CD53
@
@
2
2
Layout Note:
Pl
ace near DIMM
OSCON (220uF_6.3V_4.2L_ESR17m)*1=(SF000002Y00)
(10uF_0603_6.3V)*8
(0.1uF_402_10V)*4
+1.35V
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1
2
3
1
CD142
CD142
2
+VREF_CA <12>
CD151
CD151
+VREF_CA
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
CD143
CD143
10U_0603_6.3V6M
1
CD152
CD152
2
+VREF_CA
Layout Note:
ace near DIMM
Pl
+0.675VS
CD288
CD288
2012/07/01
2012/07/01
2012/07/01
1
2
1K_0402_1%
1K_0402_1%
1K_0402_1%
1K_0402_1%
1
2
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1
CD144
CD144
2
12
RD80
RD80
12
RD81
RD81
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1
CD158
CD158
2
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
DDRA_DQ[0..63] <7>
DDRA_DQS[0..7] <7>
DDRA_DQS#[0..7] <7>
DDRA_MA[0..15] <7>
10U_0603_6.3V6M
10U_0603_6.3V6M
1
CD145
CD145
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1
CD159
CD159
2
Deciphered Date
Deciphered Date
Deciphered Date
10U_0603_6.3V6M
10U_0603_6.3V6M
1
CD153
CD153
2
+VREF_CA_R+1.35V
RD89
RD89
12
0_0402_5%
0_0402_5%
CD179 0.1U_0402_10V6KCD179 0.1U_0402_10V6K
24.9_0402_1%
24.9_0402_1%
1U_0402_6.3V6K
1U_0402_6.3V6K
1
CD160
CD160
2
2
10U_0603_6.3V6M
CD146
CD146
RD88
RD88
10U_0603_6.3V6M
1
2
1
2
12
0.1U_0402_10V6K
0.1U_0402_10V6K
1
CD154
CD154
2
Note:
VREF trace width:20 mils at least
Spacing:20mils to other signal/planes
Place near DIMM scoket
Layout Note:
Place near DIMM
DDR_A_DM[0:7] connect to GND
2014/07/01
2014/07/01
2014/07/01
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
1
1
CD147
CD147
CD155
CD155
2
2
Title
Title
Title
DDRIII SO-DIMM A
DDRIII SO-DIMM A
DDRIII SO-DIMM A
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Date: Sheet
Date: Sheet of
Date: Sheet of
Wednesday, March 27, 2013
0.1U_0402_10V6K
0.1U_0402_10V6K
1
CD156
CD156
2
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
1
+
+
CD148
CD148
220U_6.3V_M
220U_6.3V_M
2
of
11 69
11 69
1
11 69
1.0
1.0
1.0
5
4
3
2
1
+VREF_DQ_DIMMB_R
1 2
0_0402_5%
0_0402_5%
D D
C C
B B
A A
1
CD181
CD181
0.1U_0402_10V6K
0.1U_0402_10V6K
2
12
RD92
RD92
24.9_0402_1%
24.9_0402_1%
RD93
RD93
+1.35V
12
RD84
RD84
1K_0402_1%
1K_0402_1%
12
RD85
RD85
CD289
CD289
1K_0402_1%
1K_0402_1%
DDRB_CKE0<7>
DDRB_BS2#<7>
DDRB_CLK0<7>
DDRB_CLK0#<7>
DDRB_BS0#<7>
DDRB_WE#<7>
DDRB_CAS#<7>
DDRB_CS1#<7>
+3VS
CD177
CD177
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
5
1
2
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
1
2
+VREF_DQ_DIMMB
1
CD157
CD157
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
CD178
CD178
0.1U_0402_10V6K
0.1U_0402_10V6K
2
DDRB_DQ4
DDRB_DQ2
DDRB_DQ3
DDRB_DQ13
DDRB_DQ12
DDRB_DQS#1
DDRB_DQS1
DDRB_DQ15
DDRB_DQ20
DDRB_DQ16
DDRB_DQS#2
DDRB_DQS2
DDRB_DQ22
DDRB_DQ23
DDRB_DQ28
DDRB_DQ29
DDRB_DQ26
DDRB_DQ27
DDRB_CKE0
DDRB_BS2#
DDRB_MA12
DDRB_MA9
DDRB_MA8
DDRB_MA5
DDRB_MA3
DDRB_MA1
DDRB_CLK0
DDRB_CLK0#
DDRB_MA10
DDRB_BS0#
DDRB_WE#
DDRB_CAS#
DDRB_MA13
DDRB_CS1#
DDRB_DQ39
DDRB_DQ33
DDRB_DQS#4
DDRB_DQS4
DDRB_DQ32
DDRB_DQ36
DDRB_DQ44
DDRB_DQ45
DDRB_DQ40
DDRB_DQ42
DDRB_DQ53
DDRB_DQ55
DDRB_DQS#6
DDRB_DQS6
DDRB_DQ49
DDRB_DQ48
DDRB_DQ60
DDRB_DQ63
DDRB_DQ62
RD95
RD95
1 2
10K_0402_5%
10K_0402_5%
1 2
RD9710K_0402_5%RD9710K_0402_5%
DDR3 SO-DIMM B
+1.35V +1.35V
3A@1.5V
JDDRL2
JDDRL2
VREF_DQ1VSS1
3
VSS2
5
DQ0
7
DQ1
9
VSS4
11
DM0
13
VSS5
15
DQ2
17
DQ3
19
VSS7
21
DQ8
23
DQ9
25
VSS9
27
DQS#1
DQS129RESET#
VSS1131VSS12
33
DQ10
35
DQ11
VSS1337VSS14
39
DQ16
41
DQ17
VSS1543VSS16
45
DQS#2
47
DQS2
49
VSS18
51
DQ18
53
DQ19
55
VSS20
57
DQ24
59
DQ25
VSS2261DQS#3
63
DM3
VSS2365VSS24
67
DQ26
69
DQ27
VSS2571VSS26
73
CKE0
75
VDD1
77
NC1
79
BA2
81
VDD3
83
A12/BC#
85
A9
87
VDD5
89
A8
91
A5
93
VDD7
95
A3
97
A1
99
VDD9
101
CK0
103
CK0#
105
VDD11
107
A10/AP
109
BA0
111
VDD13
113
WE#
115
CAS#
117
VDD15
119
A13
121
S1#
123
VDD17
125
NCTEST
127
VSS27
129
DQ32
131
DQ33
133
VSS29
135
DQS#4
137
DQS4
139
VSS32
141
DQ34
143
DQ35
145
VSS34
147
DQ40
149
DQ41
151
VSS36
153
DM5
155
VSS37
157
DQ42
159
DQ43
161
VSS39
163
DQ48
165
DQ49
167
VSS41
169
DQS#6
171
DQS6
173
VSS44
175
DQ50
177
DQ51
179
VSS46
181
DQ56
183
DQ57
185
VSS48
187
DM7
189
VSS49
191
DQ58
193
DQ59
195
VSS51
197
SA0
199
VDDSPD
201
SA1
203
VTT1
205
G1
FOX_AS0A621-U4SG-7H
FOX_AS0A621-U4SG-7H
ME@
ME@
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
DQ14
DQ15
DQ20
DQ21
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS3
DQ30
DQ31
CKE1
VDD2
VDD4
VDD6
VDD8
VDD10
CK1#
VDD12
RAS#
VDD14
ODT0
VDD16
ODT1
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
VTT2
4
A15
A14
A11
CK1
BA1
S0#
NC2
SCL
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
A7
88
90
A6
92
A4
94
96
A2
98
A0
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
G2
DDRB_DQ0
DDRB_DQ1DDRB_DQ5
DDRB_DQS#0
DDRB_DQS0
DDRB_DQ6
DDRB_DQ7
DDRB_DQ8
DDRB_DQ9
DDR3_DRAMRST#
DDRB_DQ14
DDRB_DQ10DDRB_DQ11
DDRB_DQ17
DDRB_DQ21
DDRB_DQ18
DDRB_DQ19
DDRB_DQ30
DDRB_DQ31
DDRB_DQS#3
DDRB_DQS3
DDRB_DQ25
DDRB_DQ24
DDRB_CKE1
DDRB_MA15
DDRB_MA14
DDRB_MA11
DDRB_MA7
DDRB_MA6
DDRB_MA4
DDRB_MA2
DDRB_MA0
DDRB_CLK1
DDRB_CLK1#
DDRB_BS1#
DDRB_RAS#
DDRB_CS0#
DDRB_ODT0
DDRB_ODT1
DDRB_DQ35
DDRB_DQ37
DDRB_DQ38
DDRB_DQ34
DDRB_DQ41
DDRB_DQ47
DDRB_DQS#5
DDRB_DQS5
DDRB_DQ43
DDRB_DQ46
DDRB_DQ54
DDRB_DQ52
DDRB_DQ51
DDRB_DQ50
DDRB_DQ61
DDRB_DQ57DDRB_DQ56
DDRB_DQS#7
DDRB_DQS7
DDRB_DQ59
DDRB_DQ58
SMB_DATA_S3
SMB_CLK_S3
0.65A@0.75V
0.65A@0.75V
0.65A@0.75V0.65A@0.75V
For RF request
0.047U_0402_16V4Z
0.047U_0402_16V4Z
1
CD54
CD54
@
@
2
DDR3_DRAMRST# <11,6>
20120727 VA
SWAP DQ for layout
DDRB_CKE1 <7>
20120727 VA
SWAP DQ for layout
DDRB_CLK1 <7>
DDRB_CLK1# <7>
DDRB_BS1# < 7>
DDRB_RAS# <7>
DDRB_CS0# <7>
DDRB_ODT0 <7>
DDRB_ODT1 <7>
0.1U_0402_10V6K
0.1U_0402_10V6K
1
1
CD281
CD281
CD280
CD280
2
2
20120727 VA
SWAP DQ for layout
SMB_DATA_S3 <11,17,40,47>
SMB_CLK_S3 <11,17,40,47>
+0.675VS
Security Classification
Security Classification
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
1
CD55
CD55
@
@
2
+VREF_CA
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
Issued Date
Issued Date
Issued Date
0.047U_0402_16V4Z
0.047U_0402_16V4Z
CD56
CD56
@
@
3
0.047U_0402_16V4Z
0.047U_0402_16V4Z
1
2
Layout Note:
Place near DIMM
+1.35V
10U_0603_6.3V6M
10U_0603_6.3V6M
1
CD161
CD161
CD282
CD282
2
+VREF_CA <11>
2012/07/01
2012/07/01
2012/07/01
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1
1
CD163
CD163
CD164
CD164
2
2
Layout Note:
Place near DIMM
+0.675VS
CD173
CD173
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
(10uF_0603_6.3V)*8
(0
.1uF_402_10V)*4
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1
CD165
CD165
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1
CD174
CD174
2
Deciphered Date
Deciphered Date
Deciphered Date
1
2
1
1
CD166
CD166
2
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1
CD175
CD175
2
2014/07/01
2014/07/01
2014/07/01
2
DDRB_DQ[0..63] <7>
DDRB_DQS[0..7] <7>
DDRB_DQS#[0..7] <7>
DDRB_MA[0..15] <7>
10U_0603_6.3V6M
10U_0603_6.3V6M
1
CD168
CD168
CD167
CD167
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1
CD176
CD176
2
10U_0603_6.3V6M
10U_0603_6.3V6M
1
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
CD169
CD169
CD170
CD170
2
Layout Note:
ace near DIMM
Pl
0.1U_0402_10V6K
0.1U_0402_10V6K
1
1
CD171
CD171
2
2
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
1
CD172
CD172
2
DDR_B_DM[0:7] connect to GND
Title
Title
Title
DDRIII SO-DIMM B
DDRIII SO-DIMM B
DDRIII SO-DIMM B
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Date: Sheet
Date: Sheet of
Date: Sheet of
Wednesday, March 27, 2013
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
1
12 69
12 69
12 69
1.0
1.0
1.0
of
5
4
3
2
1
Place JUMPER under RAM door
+RTCVCC
1 2
D D
CRT_SWITCH_1<37>
+3V_PCH
0_0603_5%
0_0603_5%
12
RH288
C C
B B
RH288
@
@
+3.3V_ALW_PCH_JTAG PCH_JTAG_TMS
32.768KHZ_12.5PF_CM31532768DZFT
32.768KHZ_12.5PF_CM31532768DZFT
1
CH189
CH189
18P_0402_50V8J
18P_0402_50V8J
2
CRT_SWITCH_1 PCH_GPIO33PCH_GPIO33
RH59 51_0402_1 %@RH59 51_0402_1%@
RH44 210_0402_ 1%@RH 44 210_0402_1%@
RH45 210_0402_ 1%@RH 45 210_0402_1%@
RH46 210_0402_ 1%@RH 46 210_0402_1%@
RH145
RH145
1 2
10M_0402_5%
10M_0402_5%
Y3
Y3
1 2
RH148 20K_0402_5%RH148 20K_0402_5%
1 2
RH146 20K_0402_5%RH146 20K_0402_5%
+3VS
1 2
RH110 0_0402_5%RH110 0_0402_5%
ME_FLASH<46>
12
1 2
1 2
1 2
PCH_RTCX1
PCH_RTCX2
1
CH188
CH188
18P_0402_50V8J
18P_0402_50V8J
2
1U_0603_10V4Z
1U_0603_10V4Z
1U_0603_10V4Z
1U_0603_10V4Z
@
@
RH121
RH121
1 2
10K_0402_5%
10K_0402_5%
ME_FLASH HDA_SDOUT
RH109 R_short 0_0402_5%RH109 R_short 0_0402_5%
+3V_PCH
100_0402_1%
100_0402_1%
12
RH48
RH48
@
@
@
@
CH202
CH202
CH229
CH229
RH107 1K _0402_1%@RH107 1K_0402_1%@
RH317 10K_0402_5%@RH317 10K_0402_5%@
100_0402_1%
100_0402_1%
12
RH49
RH49
@
@
CMOS
1
2
1
2
1 2
1 2
100_0402_1%
100_0402_1%
12
RH47
RH47
@ JME1
@
HDA_SPKR<45>
HDA_SDIN0<45>
PCH_JTAG_TCK
PCH_JTAG_TDI
PCH_JTAG_TDO
12
JME1
SHORT PADS
SHORT PADS
12
JCMOS2
JCMOS2
SHORT PADS@
SHORT PADS@
12
RH1508 0_ 0402_5%
RH1508 0_ 0402_5%
T108 PAD@ T108 PAD@
T109 PAD@ T109 PAD@
+RTCVCC
PCH_RTCX1
PCH_RTCX2
PCH_SRTCRST#
SM_INTRUDER#
PCH_INTVRMEN
PCH_RTCRST#
HDA_BIT_CLK
HDA_SYNC
HDA_SPKR
HDA_RST#
HDA_SDIN0
PCH_GPIO33
PCH_GPIO13
1 2
PCH_TP25
@
@
1 2
RH149 1M_0402 _5%RH149 1M_0402 _5%
1 2
RH150 330K_0402_ 5%RH150 330K_0402_5%
INTVRMEN
H
：：：：
Integrated VRM e nable (Default)
*
L
：：：：
Integrated VRM d isable
UHA
UHA
B5
RTCX1
B4
RTCX2
B9
SRTCRST#
A8
INTRUDER#
G10
INTVRMEN
D9
RTCRST#
B25
HDA_BCLK
A22
HDA_SYNC
AL10
SPKR
C24
HDA_RST#
L22
HDA_SDI0
K22
HDA_SDI1
G22
HDA_SDI2
F22
HDA_SDI3
A24
HDA_SDO
B17
DOCKEN#/GPIO33
C22
HDA_DOCK_RST#/GPIO13
AB3
JTAG_TCK
AD1
JTAG_TMS
AE2
JTAG_TDI
AD3
JTAG_TDO
F8
TP25
C26
TP22
AB6
TP20
(INTVRMEN should always be pull high.)
HDA AUDIO
1 2
RH112
HDA_BITCLK_AUDIO<45>
HDA_SYNC_AUDIO<45>
HDA_RST_AUDIO#<45>
A A
HDA_SDOUT_AUDIO<45>
RH112
33_0402_5%
33_0402_5%
1 2
RH114
RH114
33_0402_5%
33_0402_5%
1 2
RH116
RH116
33_0402_5%
33_0402_5%
1 2
RH118
RH118
33_0402_5%
33_0402_5%
HDA_BIT_CLK
HDA_SYNC_R HDA_SYNC
HDA_RST#
HDA_SDOUT
JTAGRTC AZALIA
JTAGRTC AZALIA
LYNXPOINT_BGA695
LYNXPOINT_BGA695
SM_INTRUDER#
PCH_INTVRMEN
S
S
12
1 2
RH1353
RH1353
1M_0402_5%
1M_0402_5%
LPT_PCH_M_EDS
LPT_PCH_M_EDS
REV = 5
REV = 5
SATA
SATA
1 OF 11
1 OF 11
SATA_RXN_0
SATA_RXP_0
SATA_TXN_0
SATA_TXP_0
SATA_RXN_1
SATA_RXP_1
SATA_TXN_1
SATA_TXP_1
SATA_RXN_2
SATA_RXP_2
SATA_TXN_2
SATA_TXP_2
SATA_RXN_3
SATA_RXP_3
SATA_TXN_3
SATA_TXP_3
SATA_RXN4/PERN1
SATA_RXP4/PERP1
SATA_TXN4/PETN1
SATA_TXP4/PETP1
SATA_RXN5/PERN2
SATA_RXP5/PERP2
SATA_TXN5/PETN2
SATA_TXP5/PETP2
SATA_RCOMP
SATALED#
SATA0GP/GPIO21
SATA1GP/GPIO19
SATA_IREF
+3VS
TP9
TP8
*
+5VS +3V_PCH
QH10
QH10
G
G
2
BSS138_NL_SOT23-3
BSS138_NL_SOT23-3
13
D
D
@
@
RH1509 0_04 02_5%
RH1509 0_04 02_5%
*
BC8
BE8
AW8
AY8
BC10
BE10
AV10
AW10
BB9
SATA_PRX_DTX_N2
BD9
SATA_PRX_DTX_P2
AY13
SATA_PTX_DRX_N2
AW13
SATA_PTX_DRX_P2
BC12
BE12
AR13
AT13
BD13
SATA_PRX_DTX_N0
BB13
SATA_PRX_DTX_P0
AV15
SATA_PTX_DRX_N0
AW15
SATA_PTX_DRX_P0
BC14
SATA_PRX_DTX_N1
BE14
SATA_PRX_DTX_P1
AP15
AR15
SATA_PTX_DRX_P1
AY5
SATA_COMP
AP3
HDD_LED#
AT1
PCH_GPIO21
AU2
SATA_DET#
BD4
BA2
BB2
RH105 1K_0402_5%@R H105 1K_0402_5%@
HIGH= Enable ( N o Reboot )
LOW= Disable (De fault)
RH108 1K_0402_5%RH108 1K_0402_5%
RH119 10K _0402_5%RH119 10K_0402_5%
SATA_IREF
T161PAD @T161PAD @
T155PAD @T155PAD @
1 2
<Intel update spec>
If
RH1509 = stuff
RH1353 = @
QH10 = @
RH108 = @
12
12
CH186 0.01U_0402_16V7KCH186 0.01U_0402_16V7K
12
CH187 0.01U_0402_16V7KCH187 0.01U_0402_16V7K
@
@
12
CH184 0.01U_0402_16V7K
CH184 0.01U_0402_16V7K
12
CH185 0.01U_0402_16V7K
CH185 0.01U_0402_16V7K
@
@
12
CH273 0.01U_0402_16V7KCH273 0.01U_0402_16V7K
12
CH272 0.01U_0402_16V7KCH272 0.01U_0402_16V7K
12
12
RH410_0402_5% RH410_0402_5%
HDA_SPKR
+3VS
+1.5VS
HDA_SYNC
This signal has a weak internal pull-down
On Die PLL VR Se lect is supplie d by
1.5V when smaple d high (Default )
1.8V when sample d low
Needs to be pull ed High for Chi ef River platfro m
ODD
SATA_PTX_C_DRX_N2
SATA_PTX_C_DRX_P2
SSD
SATA_PTX_C_DRX_N0
SATA_PTX_C_DRX_P0
H
DD
SATA_PTX_C_DRX_N1SATA_PTX_DRX_N1
SATA_PTX_C_DRX_P1
RH120 10K _0402_5%RH120 10K_0402_5%
RH316 10K_0402_5 %RH316 10K_0402_5%
12
W=20mils W=20mils
+RTCBATT +RTCVCC
SATA_PRX_DTX_N2 <44>
SATA_PRX_DTX_P2 <44>
SATA_PTX_C_DRX_N2 <44>
SATA_PTX_C_DRX_P2 <44>
SATA_PTX_DRX_N0 <40>
SATA_PTX_DRX_P0 <40>
SATA_PRX_DTX_N0 <40>
SATA_PRX_DTX_P0 <40>
SATA_PTX_C_DRX_N0 <40>
SATA_PTX_C_DRX_P0 <40>
SATA_PRX_DTX_N1 <44>
SATA_PRX_DTX_P1 <44>
SATA_PTX_C_DRX_N1 <44>
SATA_PTX_C_DRX_P1 <44>
12
HDD_LED# <51>
SATA_DET# <40>
RH99
RH99
1K_0402_5%
1K_0402_5%
SATA Impedance Compensation
SATA_COMP
CAD note:
Place the resistor within 500 mils of the PCH. Avoid
routing next to clock pins.
+3V_PCH
RH106 1K_0402_5%@RH 106 1K_0402_5%@
Low = Disabled ( Default)
*
High = Enabled
[Flash Des criptor Securit y Overide]
+3VS
+3VS
12
1 2
12
+1.5VS
RH407.5K_0402_1% RH407.5K_0402_1%
1
CH179
CH179
1U_0603_10V4Z
1U_0603_10V4Z
2
HDA_SDOUT
Title
Title
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
5
4
3
2012/07/01
2012/07/01
2012/07/01
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2014/07/01
2014/07/01
2014/07/01
Title
PCH (1/9) SATA,HDA,SPI, LPC
PCH (1/9) SATA,HDA,SPI, LPC
PCH (1/9) SATA,HDA,SPI, LPC
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Date: Sheet of
Date: Sheet of
Date: Sheet
Wednesday, March 27, 2013
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
1
13 69
13 69
13 69
of
1.0
1.0
1.0
5
+3VS
1 2
RH850 2.2K_0402_5%RH850 2.2K_0402_5%
D D
C C
B B
1 2
RH851 2.2K_0402_5%RH851 2.2K_0402_5%
RH339150_04 02_1% RH339150_0402_1%
RH340150_04 02_1% RH340150_0402_1%
RH341150_04 02_1% RH341150_0402_1%
DGPU_HOLD_RST#<23,54>
12
PCH_CRT_B
12
PCH_CRT_G
12
PCH_CRT_R
NVDD_PWR_EN<54,63>
PCH_CRT_DDC_CLK
PCH_CRT_DDC_DAT
20120829 VA1
Add net for add CRT MUX
PCH_CRT_DDC_CLK<37>
PCH_CRT_DDC_DAT<37>
PCH_CRT_HSYNC<37>
PCH_CRT_VSYNC<37>
DGPU_PWR_EN<23,54,55>
DGPU_GC6_EN<27,54>
PCH_WL_OFF#<40>
PCH_CRT_B<37>
PCH_CRT_G<37>
PCH_CRT_R<37>
PCH_EDP_PWM<35>
PCH_ENBKL<35>
PCH_ENVDD<35>
1 2
RH1519 0_0402_5%RH1519 0_0402_5%
NVDD_PWR_EN NVDD_PWR_EN_R
RH1526 0_0402_5%RH1526 0_0402_5%
DGPU_PWR_EN DGPU_PWR_EN_R
DGPU_GC6_EN
PCH_CRT_B
PCH_CRT_G
PCH_CRT_R
PCH_CRT_DDC_CLK
PCH_CRT_DDC_DAT
PCH_CRT_HSYNC
PCH_CRT_VSYNC
12
RH302
RH302
649_0402_1%
649_0402_1%
PCH_DGPU_HOLD_RST#
1 2
1 2
RH1525 0_0402_5%RH1525 0_0402_5%
CRT_IREF
PCH_EDP_PWM
PCH_ENBKL
PCH_ENVDD
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCH_GPIO51
PCH_WL_OFF#
4
T45
U44
V45
M43
M45
N42
N44
U40
U39
N36
K36
G36
H20
L20
K17
M20
A12
B13
C12
C10
A10
AL6
VGA_BLUE
VGA_GREEN
VGA_RED
VGA_DDC_CLK
VGA_DDC_DATA
VGA_HSYNC
VGA_VSYNC
DAC_IREF
VGA_IRTN
EDP_BKLTCTL
EDP_BKLTEN
EDP_VDDEN
PIRQA#
PIRQB#
PIRQC#
PIRQD#
GPIO50
GPIO52
GPIO54
GPIO51
GPIO53
GPIO55
LPT_PCH_M_EV
LPT_PCH_M_EV
LVDSCRT
LVDSCRT
LYNXPOINT_BGA695
LYNXPOINT_BGA695
3
REV = 5UHE
REV = 5UHE
DDPB_CTRLCLK
DDPB_CTRLDATA
DDPC_CTRLCLK
DDPC_CTRLDATA
DDPD_CTRLCLK
DDPD_CTRLDATA
DDPB_AUXN
DDPC_AUXN
DISPLAY
DISPLAY
PCI
PCI
5 OF 11
5 OF 11
DDPD_AUXN
DDPB_AUXP
DDPC_AUXP
DDPD_AUXP
PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5
DDPB_HPD
DDPC_HPD
DDPD_HPD
PME#
PLTRST#
R40
R39
R35
R36
N40
N38
H45
K43
J42
H43
K45
J44
K40
K38
H39
G17
F17
L15
M15
AD10
Y11
DDPB_CLK
DDPB_DATA
TMDS_B_HPD
PCH_GPIO2
ODD_DA#_R
PIRQH#
PLT_RST#
20120829 VA1
Add net for add HDMI MUX
ODD_DA#_R <44>
1 2
RH1522 0_0402_5%RH1522 0_0402_5%
T114 PAD@ T114 PAD@
PLT_RST# <23 ,32,40,41,46>
DDPB_CLK <37>
DDPB_DATA <37>
TMDS_B_HPD <37>
CRT_DET#CRT_DET#_R
2
CRT_DET# <36>
PLT_RST#
RH301
RH301
100K_0402_5%
100K_0402_5%
1
+3VS
1 2
RH314 8.2K_0402_5%@RH314 8.2K_0402_5%@
1 2
RH318 8.2K_0402_5%@RH318 8.2K_0402_5%@
1 2
RH313 8.2K_0402_5%RH313 8.2K_0402_5%
1 2
RH312 8.2K_0402_5%RH312 8.2K_0402_5%
1 2
RH320 8.2K_0402_5%RH320 8.2K_0402_5%
1 2
RH311 8.2K_0402_5%RH311 8.2K_0402_5%
1 2
RH323 8.2K_0402_5%RH323 8.2K_0402_5%
1 2
RH324 8.2K_0402_5%RH324 8.2K_0402_5%
RH325 10K_0402_5%RH325 10K_0402_5%
@
@
1 2
RH310 8.2K_0402_5%
RH310 8.2K_0402_5%
1 2
RH315 8.2K_0402_5%
RH315 8.2K_0402_5%
@
@
RH308 1K_0402_5%@RH308 1K_0402_5%@
A16 swap overide Strap/Top-Block
Swap Override jumper
PCI_GNT3#
12
PPT EDS DOC#474146
PCH_GPIO51
DGPU_GC6_EN
PIRQH#
PCH_WL_OFF#
CRT_DET#_R
DGPU_HOLD_RST#
PCI_PIRQC#
12
12
Low = A16 swap
o
verride/Top-Block
Swap Override enabled
**High=Default
*
PCH_GPIO2
DGPU_PWR_EN
DGPU_GC6_EN
DGPU_HOLD_RST#
PCH_WL_OFF#
1 2
RH307 1K_0402_5%@RH307 1K_0402_5%@
Boot BIOS Strap
SATA_SLPD
(BBS_BIT0)
Boot BIOS Location
+3VS
RPH5
RPH5
18
27
36
45
8.2K_0804_8P4R_5%
8.2K_0804_8P4R_5%
PCI_PIRQD#
PCI_PIRQA#
ODD_DA#_R
PCI_PIRQB#
SWAP
PCH_GPIO51
BBS_BIT1
(GPIO51)
00 LPC
ODD_DA#_R
A A
5
4
For ESD
1
@
@
CC63
CC63
220P_0402_25V8J
220P_0402_25V8J
2
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
3
2012/07/01
2012/07/01
2012/07/01
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2014/07/01
2014/07/01
2014/07/01
0 1 Reserved (NAND)
1 0
*
Title
Title
Title
PCH (2/9) PCIE, SMBUS, CLK
PCH (2/9) PCIE, SMBUS, CLK
PCH (2/9) PCIE, SMBUS, CLK
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Date: Sheet of
Date: Sheet of
Date: Sheet of
Wednesday, March 27, 2013
PCI
11 SPI
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
1
14 69
14 69
14 69
1.0
1.0
1.0
5
4
3
2
1
+3V_PCH
D D
C C
B B
RH202 10K_0402_5%RH202 10K_0402_5%
+3VALW
RH222 200K_0402_5%RH222 200K_0402_5%
For Deep S3
A A
12
12
For Deep S3
SUSACK#<46>
+3VS
PCH_PWROK<46>
APWROK can be co nnect to
PWROK if iAMT d isable
EC_RSMRST#<46>
SIO_PWRBTN#_R<6>
SUSWARN#<46>
PBTN_OUT#<46>
AC_PRESENT<46>
+3VALW
+3V_PCH
RH319 10K_0 402_5%RH319 10K_0402_5%
SUSWARN#
PCH_AC_PRESENT_R
PM_DRAM_PWR GD<6>
12
DMI_CTX_PRX_N0<5>
DMI_CTX_PRX_N1<5>
DMI_CTX_PRX_N2<5>
DMI_CTX_PRX_N3<5>
DMI_CTX_PRX_P0<5>
DMI_CTX_PRX_P1<5>
DMI_CTX_PRX_P2<5>
DMI_CTX_PRX_P3<5>
DMI_CRX_PTX_N0<5>
DMI_CRX_PTX_N1<5>
DMI_CRX_PTX_N2<5>
DMI_CRX_PTX_N3<5>
DMI_CRX_PTX_P0<5>
DMI_CRX_PTX_P1<5>
DMI_CRX_PTX_P2<5>
DMI_CRX_PTX_P3<5>
+1.5VS
+1.5VS
RH1488 R_sh ort 0_0402_5%RH1488 R_short 0_0402_5%
RH188 10K_0402_5%RH188 10K_0402_5%
RH196
RH196
RH1511 R_sh ort 0_0402_5%RH1511 R_short 0_0402_5%
RH1489 R_short 0_0402_5%RH1489 R_short 0_0402_5%
RH1512 R_short 0_0402_5%RH1512 R_short 0_0402_5%
RH234 R_short 0_0402_5%RH234 R_short 0_0402_5%
RH246 8.2K_0402_5%RH246 8.2K_0402_5%
RH290 10K_0402_5%RH290 10K_0402_5%
RH43 0_0402_5%RH 43 0_0402_5%
RH204 7.5K_0402_1%RH204 7.5K_0402_1%
12
12
1 2
R_short 0_0402_5%
R_short 0_0402_5%
1 2
1 2
1 2
1 2
1 2
12
PCH_RSMRST#_R
T139 PAD@ T139 PAD@
T111 PAD@ T111 PAD@
1 2
RH1510
RH1510
R_short 0_0402_5%
R_short 0_0402_5%
T140 PAD@ T140 PAD@
EDP_SEL<38>
12
1 2
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
DMI_IREF
DMI_RCOMP
SUSACK#_R
SYS_RESET#
SYS_PWROK
PWROK
APWROK
PM_DRAM_PWR GD
PCH_RSMRST#_R
SUSWARN#_R
PCH_AC_PRESENT_R
PCH_GPIO72
RI#
VGATE<6,64>
AW22
AR20
AP17
AV20
AY22
AP20
AR17
AW20
BD21
BE20
BD17
BE18
BB21
BC20
BB17
BC18
BE16
AW17
AV17
AY17
R6
AM1
AD7
F10
AB7
H3
J2
J4
K1
E6
K7
N4
AB10
D2
CH1071
CH1071
0.1U_0402_16V4Z
0.1U_0402_16V4Z
VGATE
PCH_PWROK
MC74VHC1G08DFT2G SC70 5P
MC74VHC1G08DFT2G SC70 5P
UHB
UHB
DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3
DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3
DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3
DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3
DMI_IREF
TP12
TP7
DMI_RCOMP
SUSACK#
SYS_RESET#
SYS_PWROK
PWROK
APWROK
DRAMPWROK
RSMRST#
SUSWARN#/SUSPW RNACK/GPIO30
PWRBTN#
ACPRESENT/GPIO31
BATLOW#/GPIO72
RI#
TP21
SLP_WLAN#/GPIO29
LYNXPOINT_BGA695
LYNXPOINT_BGA695
1
2
2
1
LPT_PCH_M_EDS
LPT_PCH_M_EDS
+3VS
B
A
UH7
UH7
DMI
DMI
System Power
System Power
Management
Management
5
P
4
Y
12
G
3
REV = 5
REV = 5
4 OF 11
4 OF 11
RH182
@ RH182
@
100K_0402_1%
100K_0402_1%
FDI
FDI
SUS_STAT#/GPIO61
SUSCLK/GPIO62
SLP_S5#/GPIO63
FDI_RXN_0
FDI_RXN_1
FDI_RXP_0
FDI_RXP_1
TP16
TP15
TP10
FDI_CSYNC
FDI_INT
FDI_IREF
TP17
TP13
FDI_RCOMP
DSWVRMEN
DPWROK
WAKE#
CLKRUN#
SLP_S4#
SLP_S3#
SLP_A#
SLP_SUS#
PMSYNCH
SLP_LAN#
SYS_PWROK <6>
PCH_PWROK
12
RH203
RH203
10K_0402_5%
10K_0402_5%
For Intel checklist V0.5
AJ35
FDI_CTX_PRX_N0
AL35
FDI_CTX_PRX_N1
AJ36
FDI_CTX_PRX_P0
AL36
FDI_CTX_PRX_P1
AV43
AY45
TP5
AV45
AW44
AL39
FDI_CSYNC
AL40
FDI_INT
AT45
FDI_IREF
AU42
AU44
AR44
FDI_RCOMP
C8
DSWODVREN
L13
PCH_DPWROK_R DPWROK_E C
K3
AN7
PM_CLKRUN#
U7
SUS_STAT#
Y6
SUSCLK
Y7
PM_SLP_S5#
C6
PM_SLP_S4#
H1
PM_SLP_S3#
F3
Can be left NC w hen IAMT is not support on the platfrom
F1
PM_SLP_SUS#_R
AY3
H_PM_SYNC
G5
PCH_GPIO29
Can be left NC i f no use integr ated LAN.
10/06 Test point request
RH292 R_short 0_0402_5%RH292 R_short 0_0402_5%
RH294 R_short 0_0402_5%RH294 R_short 0_0402_5%
RH1456 R_sh ort 0_0402_5%RH1456 R_short 0_0402_5%
FDI_CTX_PRX_N0 <8>
FDI_CTX_PRX_N1 <8>
FDI_CTX_PRX_P0 <8>
FDI_CTX_PRX_P1 <8>
T144PAD @T144PAD @
T141PAD @T141PAD @
T147PAD @T147PAD @
T148PAD @T148PAD @
FDI_CSYNC <5>
FDI_INT <5>
12
RH420_0402_5% RH420_0402_5%
T145PAD @T145PAD @
T146PAD @T146PAD @
12
RH2067.5K_0402_1% RH2067.5K_0402_1%
1 2
1 2
T66PAD T66PAD
T67PAD T67PAD
T68PAD T68PAD
PM_SLP_S4# <46>
PM_SLP_S3# <46>
H_PM_SYNC <6>
T110PAD T110PAD
+1.5VS
+1.5VS
12
DSWODVREN - On D ie DSW VR Enabl e
*
H
：：：：
Enable
：：：：
Disable
L
PCIE_WAKE#WAKE#
DSWODVREN
PCH_DPWROK_R
For Intel checklist V0.6
PM_CLKRUN#
DPWROK_EC <46>
PCIE_WAKE# <19,40,41>
PM_SLP_SUS# <46,55>
WAKE#
RH187 10K_0402_5 %RH187 10K_0402_5%
+RTCVCC
12
RH189
RH189
330K_0402_5%
330K_0402_5%
12
RH291
RH291
330K_0402_5%@
330K_0402_5%@
12
RH184
RH184
100K_0402_1%
100K_0402_1%
+3VS
12
RH1858.2K_0402 _5% RH1858.2K_0402_5%
For Deep S3
note need connect to GPIO27
For Deep S3
Add one to +3VALW next Rev.
1 2
+3V_PCH
Title
Title
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
3
2012/07/01
2012/07/01
2012/07/01
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2014/07/01
2014/07/01
2014/07/01
Title
PCH (3/9) PCIE, SMBUS, CLK
PCH (3/9) PCIE, SMBUS, CLK
PCH (3/9) PCIE, SMBUS, CLK
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Date: Sheet of
Date: Sheet of
Date: Sheet of
Wednesday, March 27, 2013
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
1
15 69
15 69
15 69
1.0
1.0
1.0
5
D D
PCH_GPIO73
PCH_GPIO18
CLKREQ_TV#_R
LAN
WLAN
C C
CLK_CPU_ITP#<6>
CLK_CPU_ITP<6>
CLK_PCI_EC<46>
CLK_PCI_DB<40>
RH253 22_0402_5%RH253 22_0402_5%
RH174 22_0402_5%
RH174 22_0402_5%
CLK_PCIE_LAN#<41>
CLK_PCIE_LAN<41>
CLKREQ_LAN#<41>
CLK_PCIE_WLAN#<40>
CLK_PCIE_WLAN<40>
WLAN_CLKREQ1#<40>
RH280 0_0402_5%RH280 0_0402_5%
RH281 0_0402_5%RH281 0_0402_5%
1 2
RH1514 22_0402 _5%RH1514 22_0402_5%
12
12
12
@
@
12
CLK_PCIE_LAN#
CLK_PCIE_LAN
CLKREQ_LAN#
CLK_PCIE_WLAN#
CLK_PCIE_WLAN
WLAN_CLKREQ1#
PCH_GPIO44
PCH_GPIO45
PCH_GPIO46
CLK_BCLK_ITP#
CLK_BCLK_ITP
CLK_PCI_EC_R
CLK_PCI_DB_R
PCI_LOOPBACKOUTCLK_PCI_LOOPBACK
4
UHC
UHC
Y43
CLKOUT_PCIE_N_0
Y45
CLKOUT_PCIE_P_0
AB1
PCIECLKRQ0#/GPIO73
AA44
CLKOUT_PCIE_N_1
AA42
CLKOUT_PCIE_P_1
AF1
PCIECLKRQ1#/GPIO18
AB43
CLKOUT_PCIE_N_2
AB45
CLKOUT_PCIE_P_2
AF3
PCIECLKRQ2#/GPIO20/SMI#
AD43
CLKOUT_PCIE_N_3
AD45
CLKOUT_PCIE_P_3
T3
PCIECLKRQ3#/GPIO25
AF43
CLKOUT_PCIE_N_4
AF45
CLKOUT_PCIE_P_4
V3
PCIECLKRQ4#/GPIO26
AE44
CLKOUT_PCIE_N5
AE42
CLKOUT_PCIE_P_5
AA2
PCIECLKRQ5#/GPIO44
AB40
CLKOUT_PCIE_N_6
AB39
CLKOUT_PCIE_P_6
AE4
PCIECLKRQ6#/GPIO45
AJ44
CLKOUT_PCIE_N_7
AJ42
CLKOUT_PCIE_P_7
Y3
PCIECLKRQ7#/GPIO46
AH43
CLKOUT_ITPXDP
AH45
CLKOUT_ITPXDP_P
D44
CLKOUT_33MHZ0
E44
CLKOUT_33MHZ1
B42
CLKOUT_33MHZ2
F41
CLKOUT_33MHZ3
A40
CLKOUT_33MHZ4
CLOCK SIGNAL
CLOCK SIGNAL
LPT_PCH_M_EDS
LPT_PCH_M_EDS
LYNXPOINT_BGA695
LYNXPOINT_BGA695
2 OF 11
2 OF 11
REV = 5
REV = 5
CLKOUT_PEG_A
CLKOUT_PEG_A_P
PEGA_CLKRQ#/GPIO47
CLKOUT_PEG_B
CLKOUT_PEG_B_P
PEGB_CLKRQ#/GPIO56
CLKOUT_DMI
CLKOUT_DMI_P
CLKOUT_DP
CLKOUT_DP_P
CLKOUT_DPNS
CLKOUT_DPNS_P
CLKIN_DMI
CLKIN_DMI_P
CLKIN_GND
CLKIN_GND_P
CLKIN_DOT96N
CLKIN_DOT96P
CLKIN_SATA
CLKIN_SATA_P
REFCLK14IN
CLKIN_33MHZLOOPBACK
XTAL25_IN
XTAL25_OUT
CLKOUTFLEX0/GPIO64
CLKOUTFLEX1/GPIO65
CLKOUTFLEX2/GPIO66
CLKOUTFLEX3/GPIO67
ICLK_IREF
DIFFCLK_BIASREF
TP19
TP18
3
AB35
CLK_PCIE_VGA#
AB36
CLK_PCIE_VGA
AF6
CLK_REQ_GPU#_R
Y39
CLK_PCIE_2VGA#
Y38
CLK_PCIE_2VGA
U4
CLK2_REQ_GPU#_R
AF39
CLK_CPU_DMI#
AF40
CLK_CPU_DMI
AJ40
CLK_CPU_SSC_DPLL#
AJ39
CLK_CPU_SSC_DPLL
AF35
CLK_CPU_DPLL#
AF36
CLK_CPU_DPLL
AY24
CLK_BUF_CPU_DMI#
AW24
CLK_BUF_CPU_DMI
AR24
CLKIN_DMI2#
AT24
CLKIN_DMI2
H33
CLK_BUF_DREF_96M#
G33
CLK_BUF_DREF_96M
BE6
CLK_BUF_PCIE_SATA#
BC6
CLK_BUF_PCIE_SATA
F45
CLK_BUF_ICH_14M
D17
CLK_PCI_LOOPBACK
AL44
XTAL25_IN
AM43
XTAL25_OUT
C40
RH1505
RH1505
F38
F36
S_DGPU_RST_R
F39
PCH_GPIO67
AM45
ICLK_IREF
AD39
AD38
AN44
PCH_CLK_BIASREF
1 2
CLK_PCIE_VGA# <23>
CLK_PCIE_VGA <23>
1 2
RH1513 10K_0402_5%RH1513 10K_0402_5%
CLK_PCIE_2VGA# <32>
CLK_PCIE_2VGA <32>
1 2
RH170 10K_0402_5%RH170 10K_0402_5%
CLK_CPU_DMI# <6>
CLK_CPU_DMI <6>
CLK_CPU_SSC_DPLL# <6>
CLK_CPU_SSC_DPLL <6>
CLK_CPU_DPLL# <6>
CLK_CPU_DPLL <6>
1 2
RH162 10K_0402_5%RH162 10K_0402_5%
1 2
RH163 10K_0402_5%RH163 10K_0402_5%
1 2
RH164 10K_0402_5%RH164 10K_0402_5%
1 2
RH166 10K_0402_5%RH166 10K_0402_5%
1 2
RH167 10K_0402_5%RH167 10K_0402_5%
EDP_AUX_SEL <38>
R_short 0_0402_5%
R_short 0_0402_5%
PCH_GPIO67 < 19>
1 2
T149PAD @T149PAD @
T150PAD @T150PAD @
1 2
S_DGPU_PWROK <32,54>
RH183 10K_0402_5%RH183 10K_0402_5%
RH1504
RH1504
RH540_0402_5% R H540_0402_5%
RH2087.5K_0402_1% RH2087.5K_0402_1%
CLKIN_DMI2#
CLKIN_DMI2
CLK_BUF_CPU_DMI#
CLK_BUF_CPU_DMI
1 2
+1.5VS
+1.05V_+1.5V_RUN
2
+3V_PCH
+3V_PCH
12
R_short 0_0402_5%
R_short 0_0402_5%
CLK_REQ_GPU#_R <23>
CLK2_REQ_GPU#_R <32>
RPH1
RPH1
4 5
3 6
2 7
1 8
10K_0804_8P4R_5%
10K_0804_8P4R_5%
+3VS
S_DGPU_RST <32,54>
BIOS Request SKU ID
GPIO64, 65 that only for GC6
1
. GPIO64 : S_DGPU_GC6_EN
2. GPIO65 : S_DGPU_PWROK
1
2nd VGA
B B
A A
+3V_PCH
RH152 10K_0402_5 %RH152 10K_0402_5%
RH168 10K_0402_5 %RH168 10K_0402_5%
RH165 10K_0402_5 %RH165 10K_0402_5%
RH147 10K_0402_5 %RH147 10K_0402_5%
RH172 10K_0402_5 %RH172 10K_0402_5%
RH177 10K_0402_5 %RH177 10K_0402_5%
+3VS
RH158 10K_0402_5 %RH158 10K_0402_5%
RH329 10K_0402_5 %RH329 10K_0402_5%
5
12
12
12
12
12
12
12
12
PCH_GPIO73
CLKREQ_LAN#
WLAN_CLKREQ1#
PCH_GPIO44
PCH_GPIO45
PCH_GPIO46
PCH_GPIO18
CLKREQ_TV#_R
Change C196, C19 7 value of Cap
from 33pF to 10p F for TXC recom mend
XTAL25_IN
XTAL25_OUT
R
eserve for EMI please close to
PCH
12P_0402_50V8F
12P_0402_50V8F
CH199
@CH199
12
@
22P_0402_50V8J
22P_0402_50V8J
3
1 2
2012/07/01
2012/07/01
2012/07/01
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2014/07/01
2014/07/01
2014/07/01
RH176
@RH176
@
33_0402_5%
CLK_PCI_LOOPBACK
4
33_0402_5%
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
CH196
CH196
1
2
RH169
RH169
1 2
1M_0402_5%
1M_0402_5%
Y2
Y2
1
1
GND
2
25MHZ_10PF_7V25000014
25MHZ_10PF_7V25000014
Title
Title
Title
PCH (3/9) DMI, FDI, PM
PCH (3/9) DMI, FDI, PM
PCH (3/9) DMI, FDI, PM
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet
3
3
GND
4
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Wednesday, March 27, 2013
1
2
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
CH197
CH197
12P_0402_50V8F
12P_0402_50V8F
1
of
16 69
16 69
16 69
1.0
1.0
1.0
5
4
3
2
1
D D
UHD
UHD
EC and Mini card debug port
A20
LPC_FRAME#
SPI_CLK_PCH
SPI_SB_CS0#
SPI_CS1#
SPI_SO_R
12
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
C20
A18
C18
B21
D21
G20
AL11
AJ11
AJ7
AL7
AJ10
AH1
AH3
AJ4
AJ2
LAD_0
LAD_1
LAD_2
LAD_3
LFRAME#
LDRQ0#
LDRQ1#/GPIO23
SERIRQ
SPI_CLK
SPI_CS0#
SPI_CS1#
SPI_CS2#
SPI_MOSI
SPI_MISO
SPI_IO2
SPI_IO3
LPC_AD0<40,46>
LPC_AD1<40,46>
LPC_AD2<40,46>
LPC_AD3<40,46>
LPC_FRAME#<40,46>
SERIRQ<46>
+3VS
SPI_CLK_PCH_0
SPI_CLK_PCH_1_R
SPI_SB_CS0#_R
SPI_CS1#_R
C C
B B
SPI_SI_R
SPI_SI_R1 SPI_SI
SPI_SO_L
SPI_SO_L1
SPI_CS1#_R<46>
SPI_SI_R1<46>
SPI_SO_L1<46>
SPI_CLK_PCH_1<46>
1 2
1 2
RH331 33_ 0402_5%RH331 33_0402_5%
1 2
RH332 33_ 0402_5%RH332 33_0402_5%
1 2
RH133 33_ 0402_5%RH133 33_0402_5%
1 2
RH205 33_ 0402_5%RH205 33_0402_5%
RH131 33_ 0402_5%RH131 33_0402_5%
RH334 33_ 0402_5%RH334 33_0402_5%
SPI_CS1#_R
SPI_SI_R1
SPI_SO_L1
SPI_CLK_PCH_1 SPI_CLK_PCH_1_R
SERIRQ
RH10410K_0402_5% RH10410K_0402_5%
12
RH130 R_short 0_0402_5%RH130 R_short 0_0402_5%
12
RH333 R_short 0_0402_5%RH333 R_short 0_0402_5%
12
12
RH338 0_0402_5%
RH338 0_0402_5%
@
@
LPT_PCH_M_EDS
LPT_PCH_M_EDS
SPILPC
SPILPC
NXPOINT_BGA695
NXPOINT_BGA695
LY
LY
SMBus
SMBus
C-Link
C-Link
Thermal
Thermal
3 OF 11 REV = 5
3 OF 11 REV = 5
SMBALERT#/GPIO11
SMBCLK
SMBDATA
SML0ALERT#/GPIO60
SML0CLK
SML0DATA
SML1ALERT#/PCHHOT#/GPIO74
SML1CLK/GPIO58
SML1DATA/GPIO75
CL_CLK
CL_DATA
CL_RST#
TD_IREF
N7
PCH_GPIO11
R10
PCH_SMBCLK
U11
PCH_SMBDATA
N8
U8
SML0CLK
R7
SML0DATA
H6
PCH_HOT#
K6
SML1CLK
N11
SML1DATA
AF11
AF10
AF7
BA45
TP1
BC45
TP2
BE43
TP4
BE44
TP3
AY43
PCH_TD_IREF
RH322 8.2K_0402_1%RH322 8.2K_0402_1%
DRAMRST_CNTRL_PC H <6>
T118PAD @T118PAD @
T119PAD @T119PAD @
T120PAD @T120PAD @
T121PAD @T121PAD @
1 2
+3V_PCH
PCH_GPIO11
DRAMRST_CNTRL_PC H
SML0CLK
SML0DATA
PCH_HOT#
+3VS
RH136
RH136
1 2
2.2K_0402_5%
2.2K_0402_5%
RH135
RH135
1 2
2.2K_0402_5%
2.2K_0402_5%
PCH_SMBCLK
PCH_SMBDATA SMB_DATA_S3
5
G
G
3 4
D
D
2N7002KDWH
Vth= min 1V, max 2.5V
2
ESD 2KV
G
G
6 1
D
D
S
S
QH162A
QH162A
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
QH162B
QH162B
S
S
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
RH335 10K_0402_5%RH335 10K_0402_5%
1 2
RH336 10K_0402_5%RH336 10K_0402_5%
RH337
RH337
1 2
SMB_CLK_S3
RH134
RH134
12
10K_0402_5%
10K_0402_5%
12
10K_0402_5%
10K_0402_5%
RH140
RH140
12
10K_0402_5%
10K_0402_5%
VGA, EC, Thermal Sensor
RH137
RH137
12
RH138
RH138
12
+3V_PCH
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
SMB_CLK_S3 <11,12,40,47>
SMB_DATA_S3 <11,12,40,47>
+3VS
D
G
G
EC_SMB_CK2
S
S
QH61A
QH61A
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
EC_SMB_DA2
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Wednesday, March 27, 2013
IMM1, DIMM2, Mini CARD, TP
EC_SMB_CK2 <23,32,34,36,43,46>
EC_SMB_DA2 <23,32,34,36,43,46>
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
1
17 69
17 69
17 69
1.0
1.0
1.0
32Mb Flash ROM1
1 2
1 2
UH53
UH53
1
/CS
2
DO
3
/WP
4
GND
W25Q32FVSSIQ_SO8
W25Q32FVSSIQ_SO8
For EMI
VCC
/HOLD
CLK
DIO
RH115 10_0402_5%
RH115 10_0402_5%
1 2
@
@
1
CH200
@ CH200
@
2
SPI_WP#_1
SPI_HOLD#_1
8
7
6
5
SPI_CLK_PCH_1_R
SPI_SI_R1
10P_0402_50V8J
10P_0402_50V8J
1
CH275
CH275
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
3
2012/07/01
2012/07/01
2012/07/01
+3V_PCH +3VS
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
RH141
RH141
1 2
RH142
RH142
1 2
SML1CLK
SML1DATA
2
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
2014/07/01
2014/07/01
2014/07/01
2
6 1
D
D
5
G
G
3 4
QH61B
QH61B
D
D
S
S
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
Title
Title
Title
PCH (4/9) LVDS, CRT,DP,HDMI
PCH (4/9) LVDS, CRT,DP,HDMI
PCH (4/9) LVDS, CRT,DP,HDMI
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
For EMI
SPI_CLK_PCH_0 SPI_CLK_PCH_1_R
+3VS +3VS
SPI_SB_CS0#_R
SPI_SO_L
SPI_WP#
A A
6Mb Flash ROM
1 2
RH127 3.3K_0402_5%RH127 3.3K_0402_5%
1 2
RH129 3.3K_0402_5%RH129 3.3K_0402_5%
UH52
UH52
1
CS#
2
DO
3
WP#
4
GND
W25Q16DVSSIQ_SO8
W25Q16DVSSIQ_SO8
5
VCC
HOLD#
CLK
8
7
6
5
DI
SPI_WP#
SPI_HOLD#
SPI_HOLD#
SPI_CLK_PCH_0
SPI_SI_R
RH111 10_0402_5%
RH111 10_0402_5%
1 2
@
@
1
CH190
@ CH190
@
2
10P_0402_50V8J
10P_0402_50V8J
+3VS +3VS
1
CH191
CH191
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
4
RH330 3.3K_0402_5%RH330 3.3K_0402_5%
RH257 3.3K_0402_5%RH257 3.3K_0402_5%
SPI_CS1#_R
SPI_SO_L1 SPI_HOLD#_1
SPI_WP#_1
5
D D
PCIE_PRX_DTX_N4<41>
C C
LAN
WLAN
B B
PCIE_PRX_DTX_P4<41>
PCIE_PTX_C_DRX_N4<41>
PCIE_PTX_C_DRX_P4<41>
PCIE_PRX_DTX_N5<40>
PCIE_PRX_DTX_P5<40>
PCIE_PTX_C_DRX_N5<40>
PCIE_PTX_C_DRX_P5<40>
1 2
CH192 0.1U_0402_10V7KCH192 0.1U_0402_10V7K
1 2
CH193 0.1U_0402_10V7KCH193 0.1U_0402_10V7K
1 2
CH194 0.1U_0402_10V7KCH194 0.1U_0402_10V7K
1 2
CH195 0.1U_0402_10V7KCH195 0.1U_0402_10V7K
+1.5VS
+1.5VS
4
T124 PAD@ T124 PAD@
T125 PAD@ T125 PAD@
USB30_RX_N5
USB30_RX_P5
USB30_TX_N5
USB30_TX_P5
USB30_RX_N6
USB30_RX_P6
USB30_TX_N6
USB30_TX_P6
PCIE_PRX_DTX_N4
PCIE_PRX_DTX_P4
PCIE_PTX_DRX_N4
PCIE_PTX_DRX_P4
PCIE_PRX_DTX_N5
PCIE_PRX_DTX_P5
PCIE_PTX_DRX_N5
PCIE_PTX_DRX_P5
PCH_PCIE_IREF
PCH_PCIE_RCOMP
USB30_RX_N5<49>
USB30_RX_P5<49>
USB30_TX_N5<49>
USB30_TX_P5<49>
USB30_RX_N6<48>
USB30_RX_P6<48>
USB30_TX_N6<48>
USB30_TX_P6<48>
1 2
RH51 0_0402_5%RH51 0_0402_5%
1 2
RH210 7.5K_0402 _1%RH210 7.5K_0402_1%
AW31
AY31
BE32
BC32
AT31
AR31
BD33
BB33
AW33
AY33
BE34
BC34
AT33
AR33
BE36
BC36
AW36
AV36
BD37
BB37
AY38
AW38
BC38
BE38
AT40
AT39
BE40
BC40
AN38
AN39
BD42
BD41
BE30
BC30
BB29
BD29
UHI
UHI
PERN1/USB3RN3
PERP1/USB3RP3
PETN1/USB3TN3
PETP1/USB3TP3
PERN2/USB3RN4
PERP2/USB3RP4
PETN2/USB3TN4
PETP2/USB3TP4
PERN_3
PERP_3
PETN_3
PETP_3
PERN_4
PERP_4
PETN_4
PETP_4
PERN_5
PERP_5
PETN_5
PETP_5
PERN_6
PERP_6
PETN_6
PETP_6
PERN_7
PERP_7
PETN_7
PETP_7
PERN_8
PERP_8
PETN_8
PETP_8
PCIE_IREF
TP11
TP6
PCIE_RCOMP
LY
LY
NXPOINT_BGA695
NXPOINT_BGA695
3
LPT_PCH_M_EDS
LPT_PCH_M_EDS
PCIe
PCIe
9 OF 11 REV = 5
9 OF 11 REV = 5
2
B37
TP24
TP23
D37
A38
C38
A36
C36
A34
C34
B33
D33
F31
G31
K31
L31
G29
H29
A32
C32
A30
C30
B29
D29
A28
C28
G26
F26
F24
G24
AR26
AP26
BE24
BD23
AW26
AV26
BD25
BC24
AW29
AV29
BE26
BC26
AR29
AP29
BD27
BE28
K24
K26
M33
L33
P3
V1
U2
P1
M3
T1
N2
M1
USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4
Some PCH config not support USB port 6 & 7.
USB20_N8
USB20_P8
USB20_N10
USB20_P10
USB30_RX_N2
USB30_RX_P2
USB30_TX_N2
USB30_TX_P2
USBRBIAS
Within 500 mils
USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
USB_OC4#
USB_OC5#
USB_OC6#
USB_OC7#
USB2N0
USB2P0
USB2N1
USB2P1
USB2N2
USB2P2
USB2N3
USB2P3
USB2N4
USB2P4
USB2N5
USB2P5
USB2N6
USB2P6
USB2N7
USB2P7
USB2N8
USB2P8
USB2N9
USB2P9
USB2N10
USB2P10
USB2N11
USB2P11
USB2N12
USB
USB
USB2P12
USB2N13
USB2P13
USB3RN1
USB3RP1
USB3TN1
USB3TP1
USB3RN2
USB3RP2
USB3TN2
USB3TP2
USB3RN5
USB3RP5
USB3TN5
USB3TP5
USB3RN6
USB3RP6
USB3TN6
USB3TP6
USBRBIAS#
USBRBIAS
OC0#/GPIO59
OC1#/GPIO40
OC2#/GPIO41
OC3#/GPIO42
OC4#/GPIO43
OC5#/GPIO9
OC6#/GPIO10
OC7#/GPIO14
USB20_N0 <35>
USB20_P0 <35>
USB20_N1 <50>
USB20_P1 <50>
USB20_N2 <49>
USB20_P2 <49>
USB20_N3 <49>
USB20_P3 <49>
USB20_N4 <48>
USB20_P4 <48>
USB20_N8 <50>
USB20_P8 <50>
USB20_N10 <40>
USB20_P10 <40>
USB30_RX_N2 <49>
USB30_RX_P2 <49>
USB30_TX_N2 <49>
USB30_TX_P2 <49>
RH218
RH218
1 2
22.6_0402_1%
22.6_0402_1%
T122PAD @T122PAD @
T123PAD @T123PAD @
USB_OC0# <50>
USB_OC1# <49>
Camera
RIGHT USB 1 (SUB/B)
LEFT USB
LEFT USB
Card reader
Touch panel
T180PAD @T180PAD @
T181PAD @T181PAD @
Debug port, rese rved test point
WLAN
USB3.0
Port1
USB_OC5#
USB_OC2#
USB_OC7#
USB_OC0#
USB_OC6#
USB_OC1#
USB_OC4#
USB_OC3#
LEFT USB
LEFT USB
Card reader
Port2
Port5
Port6
RPH3
RPH3
4 5
3 6
2 7
1 8
10K_1206_8P4R_5%
10K_1206_8P4R_5%
RPH4
RPH4
4 5
3 6
2 7
1 8
10K_1206_8P4R_5%
10K_1206_8P4R_5%
1
+3V_PCH
A A
Title
Title
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
3
2012/07/01
2012/07/01
2012/07/01
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2014/07/01
2014/07/01
2014/07/01
Title
PCH (5/9) PCI, USB
PCH (5/9) PCI, USB
PCH (5/9) PCI, USB
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Date: Sheet of
Date: Sheet of
Date: Sheet of
Wednesday, March 27, 2013
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
1
18 69
18 69
18 69
1.0
1.0
1.0
5
4
3
2
1
SKU ID
PCH_GPIO67<16>
PCH_GPIO38
1 1
X
X X
12
RH25510K_0402 _5% RH25510K_0402_5%
12
KBRST#
RH22610K_0402 _5% RH22610K_0402_5%
PCH_GPIO67
PCH_GPIO38
PCH_GPIO67
PCH_GPIO70
12
RH151710K_0402_5% RH151710K_0402_5%
X
RH711
RH711
RH708
RH708
@
@
1 2
RH712
RH712
RH709
RH709
@
@
1 2
S_DGPU_PWR_EN
@
@
1 2
10K_0402_5%
10K_0402_5%
1 2
10K_0402_5%
10K_0402_5%
PCH_GPIO70
X
X
X
X
0
1
+3VS
RH704
RH704
1 2
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
RH706
RH706
@
@
1 2
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
CMOS_ON#<35>
GC6_EVENT#<23,54>
+3VS
D D
+3VS
+3V_PCH
EC_LID_OUT#<46>
waiting check
waiting check
DGPU_PWROK<27,54,62,63>
PCH_BT_DISABLE#<40>
PCIE_WAKE#<15,40,41>
PCH_BT_ON#<40>
waiting check
C C
RH252
RH252
+3V_PCH
GPIO28
O
n-Die PLL Voltage Regulator
This signal has a weak internal pull up
*
B B
PCH_GPIO27 (Have internal Pull-High)
*
H
Low: VCCVRM VR Disable
1 2
10K_0402_5%
10K_0402_5%
S_DGPU_PWR_EN<32,54,55>
S_NVDD_PWR_EN<32,54>
H：On-Die voltage r egulator enable
L：On-Die PLL Volta ge Regulator di sable
1 2
RH240 1K_0402_5%@RH240 1K_0402_5%@
igh: VCCVRM VR Enable
waiting
check
SLAVE_PRESENT#
RH233 10K_0402_5%RH233 10K_0402_5%
RH227 10K_0402_5%RH227 10K_0402_5%
RH228 10K_0402_5%RH228 10K_0402_5%
RH229 10K_0402_5%@RH229 10K_0402_5%@
RH230 10K_0402_5%RH230 10K_0402_5%
RH232 10K_0402_1%@RH232 10K_0402_1%@
+3VS
RH238 10K_0402_5%RH238 10K_0402_5%
+3VS
RH241 10K_0402_5 %RH241 10K_0402_5%
+3V_PCH
+3VS
RH243 10K_0402_5%
RH243 10K_0402_5%
+3VS
+3VS
RH247 10K_0402_5%RH247 10K_0402_5%
RH248 10K_0402_5%RH248 10K_0402_5%
RH249 0_0402_5%RH249 0_0402_5%
RH251 0_0402_5%RH251 0_0402_5%
PCH_GPIO28
CMOS_ON# PCH_GPIO68
1 2
1 2
1 2
1 2
1 2
1 2
1 2
@
@
12
1 2
1 2
RH242
RH242
1 2
@
@
1 2
1 2
SLAVE_PRESENT#<32>
12
Reseve for SKU ID
12
RH154 0_0402_5%RH154 0_0402_5%
1 2
RH156 0_0402_5%RH156 0_0402_5%
@
@
12
RH2250_0402_5%
RH2250_0402_5%
EC_SCI#<46>
EC_SMI#<46>
12
RH2310_0402_5% RH2310_0402_5%
ODD_EN<44>
RH2240_0402_5%
RH2240_0402_5%
10K_0402_5%
10K_0402_5%
ODD_DETECT#<44>
1 2
PCH_BT_DISABLE#
PCH_GPIO49
PCH_S_DGPU_PWR_ EN
PCH_S_NVDD_PW R_EN
TP_VSS_NCTF
HDSW_DDC<37>
HDSW_MAIN<37>
GC6_EVENT#_R
PCH_GPIO1
PCH_GPIO6
EC_SCI#
EC_SMI#
PCH_GPIO12
EC_LID_OUT#
PCH_GPIO16
PCH_DGPU_PWROK
ODD_EN
DS3_WAKE#_R
PCH_GPIO28
PCH_BT_ON#
PCH_GPIO35
ODD_DETECT#
PCH_GPIO37
PCH_GPIO38
PCH_GPIO39
PCH_GPIO48
SLAVE_PRESENT#
PCH_GPIO68
PCH_GPIO70
UHF
UHF
AT8
BMBUSY#/GPIO0
F13
TACH1/GPIO1
A14
TACH2/GPIO6
G15
TACH3/GPIO7
Y1
GPIO8
K13
LAN_PHY_PWR_CTRL/GPIO12
AB11
GPIO15
AN2
SATA4GP/GPIO16
C14
TACH0/GPIO17
BB4
SCLOCK/GPIO22
Y10
GPIO24
R11
GPIO27
AD11
GPIO28
AN6
GPIO34
AP1
GPIO35/NMI#
AT3
SATA2GP/GPIO36
AK1
SATA3GP/GPIO37
AT7
SLOAD/GPIO38
AM3
SDATAOUT0/GPIO39
AN4
SDATAOUT1/GPIO48
AK3
SATA5GP/GPIO49
U12
GPIO57
C16
TACH4/GPIO68
D13
TACH5/GPIO69
G13
TACH6/GPIO70
H15
TACH7/GPIO71
BE41
VSS
BE5
VSS
C45
VSS
A5
VSS
0_0402_5%
0_0402_5%
1 2
RH161
RH161
0_0402_5%
0_0402_5%
1 2
RH171
RH171
LPT_PCH_M_EDS
LPT_PCH_M_EDS
L
L
NXPOINT_BGA695
NXPOINT_BGA695
Y
Y
PCH_GPIO39
PCH_GPIO48
GPIO
GPIO
NCTF
NCTF
6 OF 11 REV = 5
6 OF 11 REV = 5
CPU/Misc
CPU/Misc
RCIN#
PROCPWRGD
THRMTRIP#
PLTRST_PROC#
AN10
TP14
AY1
PECI
AT6
KBRST#
AV3
AV1
PCH_THRMTRIP#_R H_THRMTRIP#
AU4
N10
VSS
A2
VSS
A41
VSS
A43
VSS
A44
VSS
B1
VSS
B2
VSS
B44
VSS
B45
VSS
BA1
VSS
BC1
VSS
BD1
VSS
BD2
VSS
BD44
VSS
BD45
VSS
BE2
VSS
BE3
VSS
D1
VSS
E1
VSS
E45
VSS
A4
VSS
RH239 390_0402_5%RH239 390_0402_5%
CPU_PLTRST#
+3VS
1 2
+3VS
+3V_PCH
RH265 10K_0402_5 %RH265 10K_0402_5%
RH266 10K_0402_5 %RH266 10K_0402_5%
1 2
RH272 10K_0402_5 %@ RH272 10K_0402_5%@
RH268 10K_0402_5 %@ RH268 10K_0402_5%@
Config
USB X4,PCIEX8,SATAX6
*
1 2
RH236 10K_0402_5%RH236 10K_0402_5%
KBRST# <46>
H_CPUPWRGD <6>
CPU_PLTRST# <6>
10K_0402_5%
10K_0402_5%
RH235 10K_0402_5%RH235 10K_0402_5%
12
12
12
12
12
PCH_GPIO16
PCH_GPIO49 PCH_GPIO68
PCH_GPIO16
PCH_GPIO49
GPIO16,49
11
01USB X6,PCIEX8,SATAX4
+3VS
GATEA20 <4 6>
H_THRMTRIP# <6>
PCH_THRMTRIP#_R <23,32>
RH1493
RH1493
EC_SCI#
EC_SMI#
Function
Reserve
14"
15"
+3VS
+3VS
+3VALW
DS3@
DS3@
1 2
1 2
5
12
DS3_WAKE#_R
@
@
RH250
RH250
ODD_DETECT#
PCH_GPIO37
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
3
2012/07/01
2012/07/01
2012/07/01
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2014/07/01
2014/07/01
2014/07/01
Title
Title
Title
PCH (6/9) GPIO, CPU, MISC
PCH (6/9) GPIO, CPU, MISC
PCH (6/9) GPIO, CPU, MISC
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Date: Sheet of
Date: Sheet of
Date: Sheet
Wednesday, March 27, 2013
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
1
19 69
19 69
19 69
of
1.0
1.0
1.0
RH207 10K_0402_5%
RH207 10K_0402_5%
A A
200K_0402_5%
200K_0402_5%
+3VS
RH259 10K_0402_5%RH259 10K_0402_5%
5
4
3
2
1
70mA
D D
1.312 A
J1
J1
112
JUMP_43X39
JUMP_43X39
RH209
RH209
+1.05VS_PCH_VCC
+1.05VS_PCH_VCC
10U_0603_6.3V6M
10U_0603_6.3V6M
1
CH30
CH30
2
670mA
+1.05VS_PCH_VCCASW
+1.05VS_PCH_VCCASW
RH37 5.11_0402_1%RH37 5.11_0402_1%
1U_0402_6.3V6K
1U_0402_6.3V6K
1
2
22U_0805_6.3V6M
22U_0805_6.3V6M
1
2
1 2
CH32
CH64
CH64
2
1
2
CH33
CH33
1U_0402_6.3V6K
1U_0402_6.3V6K
CH35
CH35
CH31
CH31
2
+PCH_VCCDSW
1U_0402_6.3V6K
1U_0402_6.3V6K
1
CH36
CH36
2
+PCH_VCCDSW
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
CH32
+1.05VS
2
C C
B B
+1.05VS
1 2
R_short 0_0603_5%
R_short 0_0603_5%
AA24
AA26
AD20
AD22
AD24
AD26
AD28
AE18
AE20
AE22
AE24
AE26
AG18
AG20
AG22
AG24
AA18
Y26
U14
U18
U20
U22
U24
V18
V20
V22
V24
Y18
Y20
Y22
UHG
UHG
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
DCPSUSBYP
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
LPT_PCH_M_EDS
LPT_PCH_M_EDS
Core
Core
LYNXPOINT_BGA695
LYNXPOINT_BGA695
CRT DAC
CRT DAC
FDI
FDI
HVCMOS
HVCMOS
USB3
USB3
PCIe/DMI
PCIe/DMI
SATA
SATA
VCCMPHY
VCCMPHY
7 OF 11 REV = 5
7 OF 11 REV = 5
VCCADAC1_5
VCCADACBG3_3
VCCVRM
VCCIO
VCCIO
VCC3_3_R30
VCC3_3_R32
DCPSUS1
VCCSUS3_3
VCCSUS3_3
DCPSUS3
DCPSUS3
VCCIO
VCCVRM
VCCVRM
VCCVRM
VCCIO
VCCVRM
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VSS
P45
P43
M31
BB44
AN34
AN35
R30
R32
Y12
AJ30
AJ32
AJ26
AJ28
AK20
AK26
AK28
BE22
AK18
AN11
AK22
AM18
AM20
AM22
AP22
AR22
AT22
+3VS
+3VS_PCH_VCC3_3
+PCH_USB_DCPSUS1
+3VPCH_PCH_VCCSUS 3_3
+PCH_USB_DCPSUS3
+1.05VS_PCH_VCCIO
+1.05VS_PCH_VCCIO
+VCCADAC
0.01U_0402_16V7K
0.01U_0402_16V7K
1
1
CH57
CH57
2
2
+3VPCH_PCH_VCCSUS 3_3
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
CH86
CH86
CH47
CH47
2
2
0.1U_0402_10V7K
0.1U_0402_10V7K
1
CH80
CH80
2
+1.05VS_PCH_VCCIO
1U_0402_6.3V6K
1U_0402_6.3V6K
1
CH46
CH46
2
10U_0603_6.3V6M
10U_0603_6.3V6M
CH56
CH56
1
2
1U_0402_6.3V6K
1U_0402_6.3V6K
CH45
CH45
1_0603_1%
1_0603_1%
1
2
RH1
RH1
12
+3VS_PCH_VCC3_3
0.1U_0402_10V7K
0.1U_0402_10V7K
1
CH38
CH38
2
+1.05V_+1.5V_RUN
+1.05V_+1.5V_RUN
10U_0603_6.3V6M
10U_0603_6.3V6M
1
2
10U_0603_6.3V6M
10U_0603_6.3V6M
CH44
CH44
+1.5VS
+1.05V_+1.5V_RUN
+1.05VS_PCH_VCCIO
@
@
CH85
CH85
1U_0402_6.3V6K
1U_0402_6.3V6K
1
2
+1.05V_+1.5V_RUN
10U_0603_6.3V6M
10U_0603_6.3V6M
@
@
1
CH83
CH83
2
10U_0603_6.3V6M
10U_0603_6.3V6M
@CH81
@
1
CH81
CH48
CH48
2
10U_0603_6.3V6M
10U_0603_6.3V6M
@
@
1
CH82
CH82
2
1U_0402_6.3V6K
1U_0402_6.3V6K
+PCH_VCCDSW_R
1
CH34
CH34
2
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
3
2012/07/01
2012/07/01
2012/07/01
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
+PCH_USB_DCPSUS1
1U_0402_6.3V6K
1U_0402_6.3V6K
1
2
+PCH_USB_DCPSUS3
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
@CH40
@
1
1
CH40
2
2
Deciphered Date
Deciphered Date
Deciphered Date
@CH61
@
CH61
1 2
@
@
CH39
CH39
2014/07/01
2014/07/01
2014/07/01
2
12
+1.05VS
RH3600_0402_5% @RH3600_0402_5% @
+1.05VS
RH1990_0603_5% @RH1990_0603_5% @
Title
Title
Title
PCH (7/9) PWR
PCH (7/9) PWR
PCH (7/9) PWR
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Date: Sheet of
Date: Sheet of
Date: Sheet
Wednesday, March 27, 2013
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
1
20 69
20 69
20 69
of
1.0
1.0
1.0
5
4
3
2
1
+3VPCH_PCH_VCCSUS 3_3
0.1U_0402_10V7K
CH70
CH70
1 2
1
2
1
2
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_10V7K
CH60
CH60
1
2
0.1U_0402_10V7K
0.1U_0402_10V7K
1
2
1U_0402_6.3V6K
1U_0402_6.3V6K
CH74
CH74
+1.05V_+1.5V_RUN
1U_0402_6.3V6K
1U_0402_6.3V6K
CH79
CH79
CH88
CH88
1
2
0.1U_0402_10V7K
0.1U_0402_10V7K
1
2
+3VPCH_VCCSUSHDA
+3VPCH_PCH_VCCSUS 3_3
+RTCVCC
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_10V7K
0.1U_0402_10V7K
1
1
CH67
CH67
CH68
CH68
CH69
CH69
2
2
+PCH_VPROC
+PCH_VCCCFUSE
CH55
CH55
0.1U_0402_10V7K
0.1U_0402_10V7K
1
1U_0402_6.3V6K
1U_0402_6.3V6K
1
2
CH58
CH58
2
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
1
1
CH73
CH73
2
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1
CH75
CH75
2
LPT_PCH_M_EDS
NXPOINT_BGA695
NXPOINT_BGA695
LY
LY
1U_0402_6.3V6K
1U_0402_6.3V6K
CH50
CH50
1
2
+PCH_VCCCLK3_3
1U_0402_6.3V6K
1U_0402_6.3V6K
CH51
CH51
1
2
LPT_PCH_M_EDS
USB
USB
GPIO/LPC
GPIO/LPC
Azalia
Azalia
RTC
RTC
CPU
CPU
ICC
ICC
SPI
SPI
Fuse
Fuse
Thermal
Thermal
8 OF 11 REV = 5
8 OF 11 REV = 5
1
2
1
2
R20
VCCSUS3_3
R22
VCCSUS3_3
A16
VCCDSW3_3
DCPSST
VCC3_3
VCC3_3
VCC3_3
VCCIO
VCCSUSHDA
VCCSUS3_3
VCCRTC
DCPRTC
DCPRTC
V_PROC_IO
V_PROC_IO
VCCSPI
VCC
VCC
VCCASW
VCCASW
VCCVRM
VCC3_3
VCC3_3
1U_0402_6.3V6K
1U_0402_6.3V6K
CH77
CH77
AA14
AE14
AF12
AG14
U36
A26
K8
A6
P14
P16
AJ12
AJ14
AD12
P18
+PCH_VCCCFUSE
P20
L17
R18
AW40
AK30
AK32
1U_0402_6.3V6K
1U_0402_6.3V6K
CH78
CH78
1
2
+PCH_VCCDSW 3_3
+PCH_VCCSST
CH84 0.1U_0402_10V7KCH84 0.1U_0402_10V7K
+1.05VS_PCH_VCCIO
+PCH_DCPRTC
0.1U_0402_10V7K
0.1U_0402_10V7K
+PCH_VPROC
+3VS_PCH_VCCSPI
+1.05VS_PCH_VCCASW
+3VS_PCH_VCC3_3
0.1U_0402_10V7K
0.1U_0402_10V7K
1
2
1 2
CH76
CH76
Place near pin AG30,AG32,AE30,AE32
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
CH52
CH52
1U_0402_6.3V6K
CH53
CH53
1
2
1U_0402_6.3V6K
CH54
CH54
1
2
UHH
+3VPCH_PCH_VCCSUS 3_3
0.1U_0402_10V7K
@
@
LH100
LH100
1 2
RH1516
RH1516
1 2
+1.05VS_PCH_VCCIO
12
0.1U_0402_10V7K
+1.05VS
1
CH59
CH59
0.1U_0402_10V7K
1
2
1U_0402_6.3V6K
1U_0402_6.3V6K
@CH87
@
CH87
10mA
22mA
0.1U_0402_10V7K
1
CH62
CH62
2
+3VS_PCH_VCC3_3
0.1U_0402_10V7K
0.1U_0402_10V7K
+1.05VS_PCH_VCCIO
CH63
CH63
1
2
+PCH_VCC
Place near pin AP45
1
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1
2
10U_0603_6.3V6M
10U_0603_6.3V6M
CH43
CH43
+1.05V_+1.5V_RUN
CH37
CH37
1U_0402_6.3V6K
1U_0402_6.3V6K
CH49
CH49
1
2
10U_0603_6.3V6M
10U_0603_6.3V6M
1
CH42
CH42
2
+PCH_USB_DCPSUS2
+PCH_VCC
+PCH_VCCCLK
+PCH_VCCCLK3_3
+PCH_VCCCLK
+1.05VS
306mA
RH200
RH200
1 2
R_short 0_0805_5%
R_short 0_0805_5%
2
3.629A
+3VS
183mA
55mA
1 2
R_short 0_0805_5%
R_short 0_0805_5%
D D
+1.05VS
1 2
RH361 0_0402 _5%@RH361 0_0402_5%@
C C
+3V_PCH +3VPCH_VCCS USHDA
RH215
RH215
R_short 0_0603_5%
R_short 0_0603_5%
+3VS +3VS_PCH_VCC SPI
RH213
RH213
R_short 0_0603_5%
B B
R_short 0_0603_5%
+1.05VS
JUMP_43X39
JUMP_43X39
+1.5VS +1.05V_+1.5V_RUN
+1.05VS
RH198 0_0603_5%@RH198 0_0603_5%@
+PCH_USB_DCPSUS2
+1.05VS
4.7UH_LQM18FN4R7M00D_20%
4.7UH_LQM18FN4R7M00D_20%
R_short 0_0603_5%
R_short 0_0603_5%
12
12
J2
J2
2
112
RH197
RH197
R_short 0_0603_5%
R_short 0_0603_5%
12
UHH
R24
VCCSUS3_3
R26
VCCSUS3_3
R28
VCCSUS3_3
U26
VCCSUS3_3
M24
VSS
U35
VCCUSBPLL
L24
VCC3_3
U30
VCCIO
V28
VCCIO
V30
VCCIO
Y30
VCCIO
Y35
DCPSUS2
AF34
VCCVRM
AP45
VCC
Y32
VCCCLK
M29
VCCCLK3_3
L29
VCCCLK3_3
L26
VCCCLK3_3
M26
VCCCLK3_3
U32
VCCCLK3_3
V32
VCCCLK3_3
AD34
VCCCLK
AA30
VCCCLK
AA32
VCCCLK
AD35
VCCCLK
AG30
VCCCLK
AG32
VCCCLK
AD36
VCCCLK
AE30
VCCCLK
AE32
VCCCLK
+PCH_VCCCLK
Place near pin Y32,AA30,AA32 Place near pin AD34 Place near pin AD35,AD36
RH212
RH212
15mA
+3VS_PCH_VCC3_3
0.1U_0402_10V7K
0.1U_0402_10V7K
1
CH65
CH65
2
CH66
CH66
1U_0402_6.3V6K
1U_0402_6.3V6K
1
CH72
CH72
CH71
CH71
2
12
RH2010_0402_5% @RH2010_0402_5% @
12
RH1515R_short 0_0402_5% RH1515R_short 0_0402_5%
RH219
RH219
R_short 0_0805_5%
R_short 0_0805_5%
@
@
12
RH2200_0805_5%
RH2200_0805_5%
12
RH2210_0805_5% RH2210_0805_5%
+3V_PCH
+3VALW
+1.05VS
12
+3VS
+1.05VS
+3V_PCH +3VPCH_PCH_VCCSUS 3_3
A A
RH211
RH211
R_short 0_0603_5%
R_short 0_0603_5%
RH214
RH214
R_short 0_0603_5%
R_short 0_0603_5%
5
12
+3VS_PCH_VCC3_3+3VS
12
261mA
133mA
4
Place near pin M29 Place near pin L29 Place near pin L26,M26 Place near pin U32,V32
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
3
2012/07/01
2012/07/01
2012/07/01
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2014/07/01
2014/07/01
2014/07/01
Title
Title
Title
PCH (8/9) PWR
PCH (8/9) PWR
PCH (8/9) PWR
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Date: Sheet of
Date: Sheet of
Date: Sheet
Wednesday, March 27, 2013
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
1
21 69
21 69
21 69
of
1.0
1.0
1.0
5
D D
AL34
VSS
AL38
VSS
AL8
VSS
AM14
VSS
AM24
VSS
AM26
VSS
AM28
VSS
AM30
VSS
AM32
VSS
AM16
VSS
AN36
VSS
AN40
C C
B B
AN42
AP13
AP24
AP31
AP43
AK16
AT10
AT15
AT17
AT20
AT26
AT29
AT36
AT38
AV13
AV22
AV24
AV31
AV33
BB25
AV40
AW2
AY10
AY15
AY20
AY26
AY29
AN8
AR2
D42
AV6
F43
AY7
B11
B15
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
LY
LY
LPT_PCH_M_EDS
LPT_PCH_M_EDS
UHJ
UHJ
NXPOINT_BGA695
NXPOINT_BGA695
4
K39
VSS
L2
VSS
L44
VSS
M17
VSS
M22
VSS
N12
VSS
N35
VSS
N39
VSS
N6
VSS
P22
VSS
P24
VSS
P26
VSS
P28
VSS
P30
VSS
P32
VSS
R12
VSS
R14
VSS
R16
VSS
R2
VSS
R34
VSS
R38
VSS
R44
VSS
R8
VSS
T43
VSS
U10
VSS
U16
VSS
U28
VSS
U34
VSS
U38
VSS
U42
VSS
U6
VSS
V14
VSS
V16
VSS
V26
VSS
V43
VSS
W2
VSS
W44
VSS
Y14
VSS
Y16
VSS
Y24
VSS
Y28
VSS
Y34
VSS
Y36
VSS
Y40
VSS
Y8
VSS
REV = 510 OF 11
REV = 510 OF 11
3
LPT_PCH_M_EDS
LPT_PCH_M_EDS
UHK
UHK
AA16
VSS
AA20
VSS
AA22
VSS
AA28
VSS
AA4
VSS
AB12
VSS
AB34
VSS
AB38
VSS
AB8
VSS
AC2
VSS
AC44
VSS
AD14
VSS
AD16
VSS
AD18
VSS
AD30
VSS
AD32
VSS
AD40
VSS
AD6
VSS
AD8
VSS
AE16
VSS
AE28
VSS
AF38
VSS
AF8
VSS
AG16
VSS
AG2
VSS
AG26
VSS
AG28
VSS
AG44
VSS
AJ16
VSS
AJ18
VSS
AJ20
VSS
AJ22
VSS
AJ24
VSS
AJ34
VSS
AJ38
VSS
AJ6
VSS
AJ8
VSS
AK14
VSS
AK24
VSS
AK43
VSS
AK45
VSS
AL12
VSS
AL2
VSS
BC22
VSS
BB42
VSS
LY
LY
NXPOINT_BGA695
NXPOINT_BGA695
2
B19
VSS
B23
VSS
B27
VSS
B31
VSS
B35
VSS
B39
VSS
B7
VSS
BA40
VSS
BD11
VSS
BD15
VSS
BD19
VSS
AY36
VSS
AT43
VSS
BD31
VSS
BD35
VSS
BD39
VSS
BD7
VSS
D25
VSS
AV7
VSS
F15
VSS
F20
VSS
F29
VSS
F33
VSS
BC16
VSS
D4
VSS
G2
VSS
G38
VSS
G44
VSS
G8
VSS
H10
VSS
H13
VSS
H17
VSS
H22
VSS
H24
VSS
H26
VSS
H31
VSS
H36
VSS
H40
VSS
H7
VSS
K10
VSS
K15
VSS
K20
VSS
K29
VSS
K33
VSS
BC28
VSS
REV = 511 OF 11
REV = 511 OF 11
1
A A
Title
Title
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
3
2012/07/01
2012/07/01
2012/07/01
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2014/07/01
2014/07/01
2014/07/01
Title
PCH (9/9) VSS
PCH (9/9) VSS
PCH (9/9) VSS
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Date: Sheet of
Date: Sheet of
Date: Sheet of
Wednesday, March 27, 2013
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
1
22 69
22 69
22 69
1.0
1.0
1.0
5
PCIE_CTX_C_GRX_N[0..15]<32,5>
PCIE_CTX_C_GRX_P[0..15]<32,5>
PCIE_CRX_GTX_N[0..15]<32,5>
PCIE_CRX_GTX_P[0..15]<32,5>
D D
+3VS_VGA
RV24
RV24
2.2K_0402_5%
2.2K_0402_5%
VGA_SMB_CK2
VGA_SMB_DA2
C C
1 2
+3VS_VGA
RV25
RV25
2.2K_0402_5%
2.2K_0402_5%
1 2
4
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
2
QV1A
QV1A
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
5
61
QV1B
QV1B
+1.05VS_VGA
3
180ohms (ESR=0.2) Bead
LV1 BLM18PG181SN1D_2PLV1 BLM18PG181SN1D_2P
1 2
EC_SMB_CK2 <17,32,34,36,43,46>
EC_SMB_DA2 <17,32,34,36,43,46>
PU AT EC SIDE, +3VS AND 4.7K
+3VS
1
C1061
C1061
0.1U_0402_16V4Z
0.1U_0402_16V4Z
10K_0402_5%
10K_0402_5%
GC6@
GC6@
QV3
QV3
GC6@
GC6@
DGPU_HOLD_RST#
+3VS
RV235
RV235
2
G
G
PLT_RST#
12
1K_0402_5% GC6@
1K_0402_5% GC6@
13
D
D
S
S
5
PLT_RST#<14, 32,40,41,46>
DGPU_HOLD_RST#<14,54>
B B
DGPU_PWR_EN<14,23,54, 55>
A A
2N7002KW_SOT323-3
2N7002KW_SOT323-3
2
5
2
P
B
1
A
G
3
NC7SZ08P5X_NL_SC70-5
NC7SZ08P5X_NL_SC70-5
R1495
R1495
RV239
RV239
2
12
G
G
GC6@
GC6@
1
GC6@
GC6@
CV148
CV148
2
0.1U_0402_10V7K
0.1U_0402_10V7K
UV2
UV2
4
Y
0_0402_5%
0_0402_5%
@
@
1 2
FB_CLAMP_MON
0_0402_5%
0_0402_5%
GC6@
GC6@
10K_0402_5%
10K_0402_5%
13
D
D
GC6@
GC6@
QV2
QV2
S
S
LP2301ALT1G_SOT-23
LP2301ALT1G_SOT-23
For GC6
12
RV237
RV237
10K_0402_5%
10K_0402_5%
GC6@
GC6@
PLT_RST_VGA#
RV111
RV111
10K_0402_5%
10K_0402_5%
1 2
RV238
RV238
1 2
12
RV236
RV236
FB_CLAMP <23,27,54>
PCIE_CTX_C_GRX_N[0..15]
PCIE_CTX_C_GRX_P[0..15]
PCIE_CRX_GTX_N[0..15]
PCIE_CRX_GTX_P[0..15]
Under GPU(below 150mils)
1
CV112
CV112
2
22U_0805_6.3V6M
22U_0805_6.3V6M
PCIE_CRX_GTX_P7
PCIE_CRX_GTX_N7
PCIE_CRX_GTX_P6
PCIE_CRX_GTX_N6
PCIE_CRX_GTX_P5
PCIE_CRX_GTX_N5
PCIE_CRX_GTX_P4
PCIE_CRX_GTX_N4
PCIE_CRX_GTX_P3
PCIE_CRX_GTX_N3
PCIE_CRX_GTX_P2
PCIE_CRX_GTX_N2
PCIE_CRX_GTX_P1 PCIE_CRX_C_GTX_P1
PCIE_CRX_GTX_N1
PCIE_CRX_GTX_P0
PCIE_CRX_GTX_N0
Differential signal
4
1
1
CV4
CV4
CV113
CV113
2
2
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
DGPU_PWR_EN<14,23,54,55>
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
CV24 0.22U_0402_10V6KCV24 0.22U_0402_10V6K
CV26 0.22U_0402_10V6KCV26 0.22U_0402_10V6K
CV21 0.22U_0402_10V6KCV21 0.22U_0402_10V6K
CV23 0.22U_0402_10V6KCV23 0.22U_0402_10V6K
CV25 0.22U_0402_10V6KCV25 0.22U_0402_10V6K
CV27 0.22U_0402_10V6KCV27 0.22U_0402_10V6K
CV29 0.22U_0402_10V6KCV29 0.22U_0402_10V6K
CV31 0.22U_0402_10V6KCV31 0.22U_0402_10V6K
CV33 0.22U_0402_10V6KCV33 0.22U_0402_10V6K
CV28 0.22U_0402_10V6KCV28 0.22U_0402_10V6K
CV30 0.22U_0402_10V6KCV30 0.22U_0402_10V6K
CV32 0.22U_0402_10V6KCV32 0.22U_0402_10V6K
CV36 0.22U_0402_10V6KCV36 0.22U_0402_10V6K
CV41 0.22U_0402_10V6KCV41 0.22U_0402_10V6K
CV34 0.22U_0402_10V6KCV34 0.22U_0402_10V6K
CV35 0.22U_0402_10V6KCV35 0.22U_0402_10V6K
CLK_REQ_GPU#_R< 16>
4
1
2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
CV5
CV5
CLK_PCIE_VGA<16>
CLK_PCIE_VGA#<16>
150mA
+SP_PLLVDD
1 2
@
@
RV20 200_0402_1%
RV20 200_0402_1%
1 2
RV22 2.49K_0402_1%R V22 2.49K_0402_1%
RV231
RV231
12
10K_0402_5%
10K_0402_5%
1 2
RV233 0_0402_5%
RV233 0_0402_5%
PCIE_CTX_C_GRX_P7
PCIE_CTX_C_GRX_N7
PCIE_CTX_C_GRX_P6
PCIE_CTX_C_GRX_N6
PCIE_CTX_C_GRX_P5
PCIE_CTX_C_GRX_N5
PCIE_CTX_C_GRX_P4
PCIE_CTX_C_GRX_N4
PCIE_CTX_C_GRX_P3
PCIE_CTX_C_GRX_N3
PCIE_CTX_C_GRX_P2
PCIE_CTX_C_GRX_N2
PCIE_CTX_C_GRX_P1
PCIE_CTX_C_GRX_N1
PCIE_CTX_C_GRX_P0
PCIE_CTX_C_GRX_N0
PCIE_CRX_C_GTX_P7
PCIE_CRX_C_GTX_N7
PCIE_CRX_C_GTX_P6
PCIE_CRX_C_GTX_N6
PCIE_CRX_C_GTX_P5
PCIE_CRX_C_GTX_N5
PCIE_CRX_C_GTX_P4
PCIE_CRX_C_GTX_N4
PCIE_CRX_C_GTX_P3
PCIE_CRX_C_GTX_N3
PCIE_CRX_C_GTX_P2
PCIE_CRX_C_GTX_N2
PCIE_CRX_C_GTX_N1
PCIE_CRX_C_GTX_P0
PCIE_CRX_C_GTX_N0
CLK_PCIE_VGA
CLK_PCIE_VGA#
CLK_REQ_GPU#
PEX_TSTCLK_OUT
PEX_TSTCLK_OUT#
PLT_RST_VGA#
+3VS_VGA
RV230
RV230
10K_0402_5%
10K_0402_5%
@
@
1 2
2
G
G
QV16
QV16
1 3
D
S
D
S
2N7002H 1N_SOT23-3
2N7002H 1N_SOT23-3
@
@
PEX_TERMP
+3VS_VGA
RV32
RV32
10K_0402_5%
10K_0402_5%
1 2
@RV232
@
10K_0402_5%
10K_0402_5%
1 2
AN12
AM12
AN14
AM14
AP14
AP15
AN15
AM15
AN17
AM17
AP17
AP18
AN18
AM18
AN20
AM20
AP20
AP21
AN21
AM21
AN23
AM23
AP23
AP24
AN24
AM24
AN26
AM26
AP26
AP27
AN27
AM27
AK14
AJ14
AH14
AG14
AK15
AJ15
AL16
AK16
AK17
AJ17
AH17
AG17
AK18
AJ18
AL19
AK19
AK20
AJ20
AH20
AG20
AK21
AJ21
AL22
AK22
AK23
AJ23
AH23
AG23
AK24
AJ24
AL25
AK25
AJ11
AL13
AK13
AK12
AJ26
AK26
AJ12
AP29
RV232
UV1A
UV1A
PEX_RX0
PEX_RX0_N
PEX_RX1
PEX_RX1_N
PEX_RX2
PEX_RX2_N
PEX_RX3
PEX_RX3_N
PEX_RX4
PEX_RX4_N
PEX_RX5
PEX_RX5_N
PEX_RX6
PEX_RX6_N
PEX_RX7
PEX_RX7_N
PEX_RX8
PEX_RX8_N
PEX_RX9
PEX_RX9_N
PEX_RX10
PEX_RX10_N
PEX_RX11
PEX_RX11_N
PEX_RX12
PEX_RX12_N
PEX_RX13
PEX_RX13_N
PEX_RX14
PEX_RX14_N
PEX_RX15
PEX_RX15_N
PEX_TX0
PEX_TX0_N
PEX_TX1
PEX_TX1_N
PEX_TX2
PEX_TX2_N
PEX_TX3
PEX_TX3_N
PEX_TX4
PEX_TX4_N
PEX_TX5
PEX_TX5_N
PEX_TX6
PEX_TX6_N
PEX_TX7
PEX_TX7_N
PEX_TX8
PEX_TX8_N
PEX_TX9
PEX_TX9_N
PEX_TX10
PEX_TX10_N
PEX_TX11
PEX_TX11_N
PEX_TX12
PEX_TX12_N
PEX_TX13
PEX_TX13_N
PEX_TX14
PEX_TX14_N
PEX_TX15
PEX_TX15_N
PEX_WAKE_N
PEX_REFCLK
PEX_REFCLK_N
PEX_CLKREQ_N
PEX_TSTCLK_OUT
PEX_TSTCLK_OUT_N
PEX_RST_N
PEX_TERMP
N14P-GT1-A2_FCBGA908
N14P-GT1-A2_FCBGA908
GT1@
GT1@
UV1
UV1
GT@
GT@
N14P-GT-A2_FCBGA908
N14P-GT-A2_FCBGA908
CLK_REQ_GPU#
Part 1 of 7
Part 1 of 7
PCI EXPRESS
PCI EXPRESS
3
3
GPIO
GPIO
DACs
DACs
I2C
I2C
CLK
CLK
XTAL_OUTBUFF
XTAL_IN
1
CV37
CV37
10P_0402_50V8J
10P_0402_50V8J
2
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
DACA_RED
DACA_GREEN
DACA_BLUE
DACA_HSYNC
DACA_VSYNC
DACA_VDD
DACA_VREF
DACA_RSET
I2CA_SCL
I2CA_SDA
I2CB_SCL
I2CB_SDA
I2CC_SCL
I2CC_SDA
I2CS_SCL
I2CS_SDA
PLLVDD
SP_PLLVDD
VID_PLLVDD
XTAL_IN
XTAL_OUT
XTAL_SSIN
4
1
27MHZ_10PF_7V27000050
27MHZ_10PF_7V27000050
P6
M3
L6
P5
P7
L7
M7
N8
M1
M2
L1
M5
N3
M4
N4
P2
R8
M6
R1
P3
P4
P1
AK9
AL10
AL9
AM9
AN9
AG10
AP9
AP8
R4
R5
R7
R6
R2
R3
T4
T3
AD8
AE8
AD7
H3
H2
J4
H1
1 2
RV23 10M_0402_5%RV23 10M_0402_5%
YV1
YV1
GND
IN
2
@
@
FB_CLAMP_MON
VGA_CRT_CLK
VGA_CRT_DATA
I2CC_SCL
I2CC_SDA
60mA
45mA
45mA
1 2
RV138 0_0402_5%
RV138 0_0402_5%
VGA_BL_PWM
VGA_ENVDD
VGA_ENBKL
FB_CLAMP_TOGGLE_REQ#
OVERT#
VGA_ALERT#
NVVDD PWM_VID
VGA_AC_DET_R
VGA_EDP_HPD
DGPU_HDMI_HPD
VGA_AC_DET_R
VGA_CRT_R
VGA_CRT_G
VGA_CRT_B
VGA_CRT_HSYNC
VGA_CRT_VSYNC
+DACA_VDD
+DACA_VREF
DACA_RSET
I2CB_SCL
I2CB_SDA
VGA_SMB_CK2
VGA_SMB_DA2
+PLLVDD
1 2
RV112 0_0402_5%@RV112 0_0402_5%@
XTAL_IN
XTAL_OUT
XTALOUT
1 2
XTALSSIN
VGA_BL_PWM <35>
VGA_ENVDD <35>
VGA_ENBKL <35>
VGA_EDP_HPD <38>
DGPU_HDMI_HPD <37,39>
RB751V-40_SOD323-2
RB751V-40_SOD323-2
VGA_CRT_R <37>
VGA_CRT_G <37>
VGA_CRT_B <37>
VGA_CRT_HSYNC <37>
VGA_CRT_VSYNC <37>
VGA_CRT_CLK <37>
VGA_CRT_DATA <37>
RV2610K_0402_5% RV2610K_0402_5%
10K_0402_5%
10K_0402_5%
Internal Thermal Sensor
Crystal
Crystal
3
XTAL_OUT
OUT
2
GND
1
CV38
CV38
10P_0402_50V8J
10P_0402_50V8J
2
DV2
DV2
124_0402_1%
124_0402_1%
RV27
RV27
12
RV107
RV107
+SP_PLLVDD
12
12
CRT
LVDS
FB_CLAMP <23,27,54>
NVVDD PWM_VID <63>
VGA_AC_DET_R <32>
DPRSLPVR_VGA <63>
VGA_AC_DET <46>
1
CV130
CV130
2
0.1U_0402_10V7K
0.1U_0402_10V7K
120mA
+DACA_VDD
+PLLVDD
+3VS_VGA
RV65
RV65
@
@
10K_0402_5%
10K_0402_5%
1 2
MEM_VREF <28,29,30,31>
12
RV223
RV223
10K_0402_5%
10K_0402_5%
Vendor recommand reserve PU/PD resistor
+3VS_VGA
1 2
FB_CLAMP_TOGGLE_REQ#
GPIO 14 of GPU connect to PCH GPIO 0
RV16 100K_0402_5%RV16 100K_0402_5%
VGA_BL_PWM
1 2
Close to GPU
VGA_CRT_R
VGA_CRT_G
VGA_CRT_B
1 2
RV106 150_0402_1%RV106 150_0402_1%
1 2
RV108 150_0402_1%RV108 150_0402_1%
1 2
RV109 150_0402_1%RV109 150_0402_1%
Under GPU Near GPU
1
1
CV126
@C V126
@
2
0.1U_0402_10V7K
0.1U_0402_10V7K
1
CV131
CV131
CV40
CV40
2
22U_0805_6.3V6M
22U_0805_6.3V6M
1
CV139
CV139
2
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
1 2
LV7 0_0402_5%LV7 0_0402_5%
CV125
@C V125
@
2
0.1U_0402_10V7K
0.1U_0402_10V7K
1
2
0.1U_0402_10V7K
0.1U_0402_10V7K
Under GPU Near GPU
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF LC FU TURE CENTER. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF LC FU TURE CENTER. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF LC FU TURE CENTER. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT C ONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT C ONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT C ONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENTER .
MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENTER .
MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENTER .
2012/07/01
2012/07/01
2012/07/01
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2014/07/01
2014/07/01
2014/07/01
OVERT#
PLT_RST_VGA#
RV52
RV52
100K_0402_5%
100K_0402_5%
1
CV122
CV122
2
1
+3VS_VGA
12
RV208
RV208
10K_0402_5%
10K_0402_5%
61
QV7A
QV7A
DMN66D0LDW-7 2N_SOT363-6
DMN66D0LDW-7 2N_SOT363-6
2
@
@
13
D
D
2
G
G
S
S
2012-0418 --> Stuff QV7, RV208
2012-0429 --> Add QV5, C3 8 has abnormal shutdown issue
1
CV127
CV127
2
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
+1.05VS_VGA
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
PCH_THRMTRIP#_R
3
QV7B
QV7B
DMN66D0LDW-7 2N_SOT363-6
DMN66D0LDW-7 2N_SOT363-6
5
@
@
4
QV5
QV5
2N7002KW_SOT323-3
2N7002KW_SOT323-3
1
@
@
2
CV151
CV151
0.1U_0402_10V7K
G
G
S
S
QV6
QV6
2N7002KW_SOT323-3
2N7002KW_SOT323-3
1
2
N13P_PCIE/ DAC/ GPIO
N13P_PCIE/ DAC/ GPIO
N13P_PCIE/ DAC/ GPIO
0.1U_0402_10V7K
2
13
D
D
VGA_ALERT#
VGA_CRT_DATA
VGA_CRT_CLK
I2CB_SCL
I2CB_SDA
I2CC_SCL
I2CC_SDA
CV128
CV128
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Wednesday, March 27, 2013
RV14 2.2K_0402_5%RV14 2.2K_0402_5%
RV10 2.2K_0402_5%RV10 2.2K_0402_5%
RV11 2.2K_0402_5%RV11 2.2K_0402_5%
RV12 2.2K_0402_5%RV12 2.2K_0402_5%
RV13 2.2K_0402_5%RV13 2.2K_0402_5%
OVERT#
VGA_AC_DET_R
RV1 10K_0402_5%RV1 10K_0402_5%
RV2 10K_0402_5%RV2 10K_0402_5%
RV15 2.2K_0402_5%RV15 2.2K_0402_5%
RV17 2.2K_0402_5%RV17 2.2K_0402_5%
220 ohms @100MHz (ESR=0.05)
LV5
LV5
BLM18PG181SN1D_0603
BLM18PG181SN1D_0603
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
1
PCH_THRMTRIP#_R <19,32>
PLT_RST_VGA#
GC6_EVENT# <19,54>
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
12
+3VS_VGA
23 69
23 69
23 69
+3VS_VGA
1.0
1.0
1.0
5
D D
for 15" dual channel
VGA_EDP_TX0+<38>
VGA_EDP_TX0-<38>
VGA_EDP_TX1+<38>
C C
20120829 VA1
Change net name for add HDMI MUX
RV19100K_0402_5% RV19100K_0402_5%
12
VGA_EDP_AUX
RV30100K_0402_5% RV30100K_0402_5%
12
VGA_EDP_AUX#
B B
+3VS_VGA
RV113 47K_0402_5%RV113 47K_0402_5%
1 2
RV114 47K_0402_5%RV114 47K_0402_5%
1 2
A A
GPU_HDMI_CLK
GPU_HDMI_DATA
5
VGA_EDP_TX1-<38>
GPU_HDMI_TX2+<37>
GPU_HDMI_TX2-<37>
GPU_HDMI_TX1+<37>
GPU_HDMI_TX1-<37>
GPU_HDMI_TX0+<37>
GPU_HDMI_TX0-<37>
GPU_HDMI_CLK+<37>
GPU_HDMI_CLK-<37>
VGA_EDP_AUX<38>
VGA_EDP_AUX#<38>
HDMI
GPU_HDMI_CLK<37>
GPU_HDMI_DATA<37>
20120829 VA1
Change net name for add HDMI MUX
4
VGA_EDP_TX0+
VGA_EDP_TX0VGA_EDP_TX1+
VGA_EDP_TX1-
GPU_HDMI_CLK+
VGA_EDP_AUX
VGA_EDP_AUX#
GPU_HDMI_CLK
GPU_HDMI_DATA
4
GPU_HDMI_TX2+
GPU_HDMI_TX2-
GPU_HDMI_TX1+
GPU_HDMI_TX1-
GPU_HDMI_TX0+
GPU_HDMI_TX0-
GPU_HDMI_CLK-
UV1D
UV1D
AM6
IFPA_TXC
AN6
IFPA_TXC_ N
AP3
IFPA_TXD0
AN3
IFPA_TXD0 _N
AN5
IFPA_TXD1
AM5
IFPA_TXD1 _N
AL6
IFPA_TXD2
AK6
IFPA_TXD2 _N
AJ6
IFPA_TXD3
AH6
IFPA_TXD3 _N
AJ9
IFPB_TXC
AH9
IFPB_TXC_ N
AP6
IFPB_TXD4
AP5
IFPB_TXD4 _N
AM7
IFPB_TXD5
AL7
IFPB_TXD5 _N
AN8
IFPB_TXD6
AM8
IFPB_TXD6 _N
AK8
IFPB_TXD7
AL8
IFPB_TXD7 _N
AK1
IFPC_L0
AJ1
IFPC_L0_N
AJ3
IFPC_L1
AJ2
IFPC_L1_N
AH3
IFPC_L2
AH4
IFPC_L2_N
AG5
IFPC_L3
AG4
IFPC_L3_N
AM1
IFPD_L0
AM2
IFPD_L0_N
AM3
IFPD_L1
AM4
IFPD_L1_N
AL3
IFPD_L2
AL4
IFPD_L2_N
AK4
IFPD_L3
AK5
IFPD_L3_N
AD2
IFPE_L0
AD3
IFPE_L0_N
AD1
IFPE_L1
AC1
IFPE_L1_N
AC2
IFPE_L2
AC3
IFPE_L2_N
AC4
IFPE_L3
AC5
IFPE_L3_N
AE3
IFPF_L0
AE4
IFPF_L0_N
AF4
IFPF_L1
AF5
IFPF_L1_N
AD4
IFPF_L2
AD5
IFPF_L2_N
AG1
IFPF_L3
AF1
IFPF_L3_N
AG3
IFPC_AUX_ I2CW _SCL
AG2
IFPC_AUX_ I2CW _SDA_N
AK3
IFPD_AUX_ I2CX_SCL
AK2
IFPD_AUX_ I2CX_SDA _N
AB3
IFPE_AUX_ I2CY_SCL
AB4
IFPE_AUX_ I2CY_SDA_N
AF3
IFPF_AUX_ I2CZ_SCL
AF2
IFPF_AUX_ I2CZ_SDA _N
N14P-GT-A2_FCBGA908
N14P-GT-A2_FCBGA908
Part 4 of 7
Part 4 of 7
VDD_SEN SE
GND_SEN SE
TEST
TEST
JTAG_TR ST_N
SERIAL
SERIAL
LVDS/TMDS
LVDS/TMDS
GENERAL
GENERAL
MULTI_STR AP_REF0_GND
3
NC
NC
TESTMOD E
JTAG_TC K
JTAG_TD I
JTAG_TD O
JTAG_TM S
ROM_CS_ N
ROM_SCL K
ROM_SI
ROM_SO
BUFRST_ N
CEC
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
THERMDP
THERMDN
P8
NC
AC6
NC
AJ28
NC
AJ4
NC
AJ5
NC
AL11
NC
C15
NC
D19
NC
D20
NC
D23
NC
D26
NC
H31
NC
T8
NC
V32
NC
L4
VCCSENSE_VGA
L5
VSSSENSE_VGA
AK11
AM10
AM11
AP12
AP11
AN11
H6
H4
H5
H7
RV35 10K_0402_5%RV35 10K_0402_5%
L2
L3
J1
J2
J7
J6
J5
J3
K3
K4
VCCSENSE_VGA <63>
VSSSENSE_VGA <63>
trace width: 16mils
differential voltage sensing.
differential signal routing.
TESTMODE
TV2TV2
TV3TV3
TV4TV4
1 2
RV34 10K_0402_5%RV34 10K_0402_5%
ROM_CS#
ROM_SCLK
ROM_SI
ROM_SO
1 2
RV38 40.2K_0402_1%RV38 40.2K_0402_1%
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
TV5TV5
12
ROM_SCLK <33>
ROM_SI <33>
ROM_SO <33>
STRAP0 <33>
STRAP1 <33>
STRAP2 <33>
STRAP3 <33>
STRAP4 <33>
12
10K_0402_5%
10K_0402_5%
RV33
RV33
2
1MB SPI ROM FOR VBIOS ROM (SLI)
RV229
RV229
10K_0402_5%
10K_0402_5%
ROM_CS#_R
+3VS_VGA
12
@
@
2014/07/01
2014/07/01
2014/07/01
2
20mils
SA00004EK0J(2012/0813)
UV15
UV15
1
CS#
2
HOLD#
DO
3
WP#
4
GND
MX25L2006EMIT-12G SOP
MX25L2006EMIT-12G SOP
CV295
CV295
12
@
0.1U_0402_16V4Z
0.1U_0402_16V4Z
ROM_CS#
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
2012/07/01
2012/07/01
2012/07/01
3
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
@
RV224 0_0402_5%
RV224 0_0402_5%
@
@
1 2
1 2
RV226 0_0402_5%
RV226 0_0402_5%
@
@
Deciphered Date
Deciphered Date
Deciphered Date
1
For EMI
ROM_SCLK_R
12
RV225
RV225
@
@
10K_0402_5%
@
@
8
VCC
7
ROM_HOLD#ROM_SO_RROM_SO
6
CLK
5
DIO
ROM_SCLK_R
ROM_SI_R
Title
Title
Title
N13P_LVDS/ HDMI/ THERM
N13P_LVDS/ HDMI/ THERM
N13P_LVDS/ HDMI/ THERM
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
10K_0402_5%
RV228
RV228
1 2
1 2
RV227
RV227
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Wednesday, March 27, 2013
RH123 10_0402_5%
RH123 10_0402_5%
1 2
@
@
@ CH201
@
10P_0402_50V8J
10P_0402_50V8J
0_0402_5%@
0_0402_5%@
ROM_SCLK
ROM_SI
0_0402_5%@
0_0402_5%@
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
24 69
24 69
24 69
1
1
2
CH201
1.0
1.0
1.0
5
+1.5VS_VGA
D D
+1.5VS_VGA
1
2
1U_0402_6.3V6K
1U_0402_6.3V6K
C C
B B
+3VS_VGA
300ohms @100MHz (ESR=0.25)
P
/N: SM010031680
For GDDR5 settin g. Near GPU
1
1
2
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
1
CV264
CV264
CV263
CV263
2
2
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
1
1
CV267
CV265
CV265
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
CV267
CV266
CV266
2
2
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
Under GPU(below 150mils)
1
1
CV281
CV281
CV277
CV277
1U_0402_6.3V6K
1U_0402_6.3V6K
CV282
CV282
2
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
CV279
CV279
CV278
CV278
2
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
VDDQ_SENSE<61>
CALIBRATION PIN
FB_CAL_x_PD_VDDQ
FB_CAL_x_PU_GND
FB_CAL_xTERM_GND
LV9
LV9
BLM18PG181SN1D_0603
BLM18PG181SN1D_0603
12
1
1
CV149
CV149
CV147
2
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
CV147
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1
2
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
1
CV280
CV280
2
2
2
CV268
CV268
1
10U_0603_6.3V6M
10U_0603_6.3V6M
1
2
0.1U_0402_10V7K
0.1U_0402_10V7K
2
CV270
CV270
CV269
CV269
1
1
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1
CV287
CV287
CV292
CV292
2
0.1U_0402_10V7K
0.1U_0402_10V7K
GDDR5
40.2Ohm
40.2Ohm
60.4Ohm
220mA
+IFPEF_PLLVDD
1
1
CV171
CV171
2
0.1U_0402_10V7K
0.1U_0402_10V7K
1
CV173
CV173
CV150
CV150
2
2
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
Place near balls
+1.05VS_VGA
A A
220ohms @100MHz (ESR=0.05)
LV10
LV10
12
BLM18PG181SN1D_0603
BLM18PG181SN1D_0603
1
CV152
CV152
2
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
1
1
CV172
CV172
2
2
0.1U_0402_10V7K
0.1U_0402_10V7K
1U_0402_6.3V6K
1U_0402_6.3V6K
Place near balls
570mA
+IFPE_IOVDD +IFPD_IOVDD
1
CV158
CV158
CV153
CV153
2
0.1U_0402_10V7K
0.1U_0402_10V7K
4
2
CV271
CV271
1
10U_0603_6.3V6M
10U_0603_6.3V6M
1
CV294
CV294
2
0.1U_0402_10V7K
0.1U_0402_10V7K
RV141 R_short 0_0402_5%RV141 R_short 0_0402_5%
1 2
RV142 R_short 0_0402_5%RV142 R_short 0_0402_5%
1 2
CV272
CV272
22U_0805_6.3V6M
22U_0805_6.3V6M
0.1U_0402_10V7K
0.1U_0402_10V7K
+3VS_VGA
+1.05VS_VGA
1
1
CV274
CV274
CV273
CV273
2
2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1
1
CV284
CV284
CV285
CV285
2
2
0.1U_0402_10V7K
0.1U_0402_10V7K
+1.5VS_VGA
1 2
RV6 40.2_0402_1%RV6 40.2_0402_1%
1 2
RV8 40.2_0402_1%RV8 40.2_0402_1%
1 2
RV9 60.4_0402_1%RV9 60.4_0402_1%
P
lace near balls
120ohms @100MHz (ESR=0.18)
P/N:SM01000BZ00
80ohms @100MHz ( ESR=0.2)
1
P/N: SM010030710
LV4
LV4
BLM18PG181SN1D_0603
BLM18PG181SN1D_0603
1
1
CV275
CV275
2
2
22U_0805_6.3V6M
22U_0805_6.3V6M
1
CV286
CV286
2
0.1U_0402_10V7K
0.1U_0402_10V7K
FB_VDDQ_SENSE
FB_VSS_SENSE
BLM18PG181SN1D_0603
BLM18PG181SN1D_0603
12
3
UV1E
UV1E
Part 5 of 7
3.5A
AA27
AA30
AB27
CV276
CV276
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
AB33
AC27
AD27
AE27
AF27
AG27
B13
B16
B19
E13
E16
E19
H10
H11
H12
H13
H14
H15
H16
H18
H19
H20
H21
H22
H23
H24
H8
H9
L27
M27
N27
P27
R27
T27
T30
T33
V27
W27
W30
W33
Y27
F1
F2
J27
H27
H25
LV6
LV6
12
1
CV146
CV146
2
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
1
1
2
CV176
CV176
CV156
CV156
2
1U_0402_6.3V6K
1U_0402_6.3V6K
Part 5 of 7
FBVDDQ_0
FBVDDQ_1
FBVDDQ_2
FBVDDQ_3
FBVDDQ_4
FBVDDQ_5
FBVDDQ_6
FBVDDQ_7
FBVDDQ_8
FBVDDQ_9
FBVDDQ_10
FBVDDQ_11
FBVDDQ_12
FBVDDQ_13
FBVDDQ_14
FBVDDQ_15
FBVDDQ_16
FBVDDQ_17
FBVDDQ_18
FBVDDQ_19
FBVDDQ_20
FBVDDQ_21
FBVDDQ_22
FBVDDQ_23
FBVDDQ_24
FBVDDQ_25
FBVDDQ_26
FBVDDQ_27
FBVDDQ_28
FBVDDQ_29
FBVDDQ_30
FBVDDQ_31
FBVDDQ_32
FBVDDQ_33
FBVDDQ_34
FBVDDQ_35
FBVDDQ_36
FBVDDQ_37
FBVDDQ_38
FBVDDQ_39
FBVDDQ_40
FBVDDQ_41
FBVDDQ_42
FBVDDQ_43
FB_VDDQ_SENSE
FB_GND_SENSE
FB_CAL_PD_VDDQ
FB_CAL_PU_GND
FB_CAL_TERM_GND
N14P-GT-A2_FCBGA908
N14P-GT-A2_FCBGA908
1U_0402_6.3V6K
1U_0402_6.3V6K
200mA
1
CV140
CV140
2
0.1U_0402_10V7K
0.1U_0402_10V7K
POWER
POWER
+IFPD_PLLVDD
1
CV141
CV141
2
Place near balls
1
2
0.1U_0402_10V7K
0.1U_0402_10V7K
IFPA_IOVDD and
1
IFPB_IOVDD combi ned
CV216
CV216
CV197
CV197
2
0.1U_0402_10V7K
0.1U_0402_10V7K
Place near balls
PEX_IOVDD_0
PEX_IOVDD_1
PEX_IOVDD_2
PEX_IOVDD_3
PEX_IOVDD_4
PEX_IOVDD_5
PEX_IOVDDQ_0
PEX_IOVDDQ_1
PEX_IOVDDQ_2
PEX_IOVDDQ_3
PEX_IOVDDQ_4
PEX_IOVDDQ_5
PEX_IOVDDQ_6
PEX_IOVDDQ_7
PEX_IOVDDQ_8
PEX_IOVDDQ_9
PEX_IOVDDQ_10
PEX_IOVDDQ_11
PEX_IOVDDQ_12
PEX_IOVDDQ_13
PEX_PLL_HVDD
PEX_SVDD_3V3
PEX_PLLVDD
IFPAB_PLLVDD
IFPAB_RSET
IFPA_IOVDD
IFPB_IOVDD
IFPC_PLLVDD
IFPC_RSET
IFPC_IOVDD
IFPD_PLLVDD
IFPD_RSET
IFPD_IOVDD
IFPEF_PLVDD
IFPEF_RSET
IFPE_IOVDD
IFPF_IOVDD
VDD33_0
VDD33_1
VDD33_2
VDD33_3
2000mA
AG19
AG21
AG22
AG24
AH21
AH25
AG13
AG15
AG16
AG18
AG25
AH15
AH18
AH26
AH27
AJ27
AK27
AL27
AM28
AN28
AH12
AG12
AG26
J8
K8
L8
M8
AH8
+IFPAB_PLLVDD
AJ8
AG8
+IFPAB_IOVDD
AG9
AF7
+IFPC_PLLVDD
AF8
AF6
+IFPC_IOVDD
AG7
+IFPD_PLLVDD
AN2
AG6
+IFPD_IOVDD
AB8
+IFPEF_PLLVDD
AD6
AC7
+IFPE_IOVDD
AC8
1
CV43
CV43
2
1U_0402_6.3V6K
1U_0402_6.3V6K
Under GPU(below 150mils)
1
CV54
CV54
2
22U_0805_6.3V6M
22U_0805_6.3V6M
+PEX_PLLVDD
+VDD33
@
1 2
1 2
@
@
1 2
@
1 2
1
1
CV44
CV44
2
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
CV53
CV53
2
2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1
CV70
CV70
2
0.1U_0402_10V7K
0.1U_0402_10V7K
RV4510K_0402_5%@RV4510K_0402_5%
RV4710K_0402_5%@RV4710K_0402_5%
RV4210K_0402_5%@RV4210K_0402_5%
RV4410K_0402_5%@RV4410K_0402_5%
12
RV401K_0402_1%@RV401K_0402_1%
@
12
RV431K_0402_1% @ RV431K_0402_1%@
12
RV461K_0402_1% RV461K_0402_1%
12
RV501K_0402_1% RV501K_0402_1%
2
Near GPU
1
CV45
CV45
CV46
CV46
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1
CV56
CV56
CV55
CV55
2
22U_0805_6.3V6M
22U_0805_6.3V6M
1
CV74
CV74
2
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
IFPAB & IFPEF have to use
1
1
CV47
CV47
2
2
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
+1.05VS_VGA
1
CV73
CV73
2
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
Under GPU(below 150mils)
Place near balls Place near GPU
+PEX_PLLVDD
2
2
CV50
CV48
CV48
10U_0603_6.3V6M
10U_0603_6.3V6M
+3VS_VGA
1
2
0.1U_0402_10V7K
0.1U_0402_10V7K
CV50
CV49
CV49
1
1
10U_0603_6.3V6M
10U_0603_6.3V6M
1
CV111
CV111
CV109
CV109
2
0.1U_0402_10V7K
0.1U_0402_10V7K
1
CV65
CV65
2
0.1U_0402_10V7K
0.1U_0402_10V7K
Place near balls
2
1
10U_0603_6.3V6M
10U_0603_6.3V6M
1
CV293
CV293
2
1U_0402_6.3V6K
1U_0402_6.3V6K
120mA
1
CV3
CV3
2
1U_0603_10V6K
1U_0603_10V6K
CV51
CV51
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
2
1
10U_0603_6.3V6M
10U_0603_6.3V6M
1
CV75
CV75
2
1
2
+1.05VS_VGA
CV52
CV52
RV5
RV5
R_short 0_0603_5%
R_short 0_0603_5%
CV66
CV66
12
RV4
RV4
0_0603_5%
0_0603_5%
1
+3VS_VGA
+1.05VS_VGA
12
Title
Title
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
5
4
3
2012/07/01
2012/07/01
2012/07/01
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2014/07/01
2014/07/01
2014/07/01
Title
N13P_Power
N13P_Power
N13P_Power
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Wednesday, March 27, 201 3
Wednesday, March 27, 201 3
Wednesday, March 27, 201 3
Date: Sheet of
Date: Sheet of
Date: Sheet of
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
1
25 69
25 69
25 69
1.0
1.0
1.0
5
V17
V18
V20
V22
W12
W14
W16
W19
W21
W23
Y13
Y15
Y17
Y18
Y20
Y22
U1
U2
U3
U4
U5
U6
U7
U8
V1
V2
V3
V4
V5
V6
V7
V8
W2
W3
W4
W5
W7
W8
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
+VGA_CORE
UV1G
+VGA_CORE
D D
C C
B B
A A
UV1G
AA12
VDD_0
AA14
VDD_1
AA16
VDD_2
AA19
VDD_3
AA21
VDD_4
AA23
VDD_5
AB13
VDD_6
AB15
VDD_7
AB17
VDD_8
AB18
VDD_9
AB20
VDD_10
AB22
VDD_11
AC12
VDD_12
AC14
VDD_13
AC16
VDD_14
AC19
VDD_15
AC21
VDD_16
AC23
VDD_17
M12
VDD_18
M14
VDD_19
M16
VDD_20
M19
VDD_21
M21
VDD_22
M23
VDD_23
N13
VDD_24
N15
VDD_25
N17
VDD_26
N18
VDD_27
N20
VDD_28
N22
VDD_29
P12
VDD_30
P14
VDD_31
P16
VDD_32
P19
VDD_33
P21
VDD_34
P23
VDD_35
R13
VDD_36
R15
VDD_37
R17
VDD_38
R18
VDD_39
R20
VDD_40
R22
VDD_41
T12
VDD_42
T14
VDD_43
T16
VDD_44
T19
VDD_45
T21
VDD_46
T23
VDD_47
U13
VDD_48
U15
VDD_49
U17
VDD_50
U18
VDD_51
U20
VDD_52
U22
VDD_53
V13
VDD_54
V15
VDD_55
N13P-GT1-A2_FCBGA908
N13P-GT1-A2_FCBGA908
5
Part 7 of 7
Part 7 of 7
POWER
POWER
VDD_56
VDD_57
VDD_58
VDD_59
VDD_60
VDD_61
VDD_62
VDD_63
VDD_64
VDD_65
VDD_66
VDD_67
VDD_68
VDD_69
VDD_70
VDD_71
XVDD_1
XVDD_2
XVDD_3
XVDD_4
XVDD_5
XVDD_6
XVDD_7
XVDD_8
XVDD_9
XVDD_10
XVDD_11
XVDD_12
XVDD_13
XVDD_14
XVDD_15
XVDD_16
XVDD_17
XVDD_18
XVDD_19
XVDD_20
XVDD_21
XVDD_22
XVDD_23
XVDD_24
XVDD_25
XVDD_26
XVDD_27
XVDD_28
XVDD_29
XVDD_30
XVDD_31
XVDD_32
XVDD_33
XVDD_34
XVDD_35
XVDD_36
XVDD_37
XVDD_38
4
4
3
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
3
2012/07/01
2012/07/01
2012/07/01
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
A2
AA17
AA18
AA20
AA22
AB12
AB14
AB16
AB19
AB2
AB21
A33
AB23
AB28
AB30
AB32
AB5
AB7
AC13
AC15
AC17
AC18
AA13
AC20
AC22
AE2
AE28
AE30
AE32
AE33
AE5
AE7
AH10
AA15
AH13
AH16
AH19
AH2
AH22
AH24
AH28
AH29
AH30
AH32
AH33
AH5
AH7
AJ7
AK10
AK7
AL12
AL14
AL15
AL17
AL18
AL2
AL20
AL21
AL23
AL24
AL26
AL28
AL30
AL32
AL33
AL5
AM13
AM16
AM19
AM22
AM25
AN1
AN10
AN13
AN16
AN19
AN22
AN25
AN30
AN34
AN4
AN7
AP2
AP33
B1
B10
B22
B25
B28
B31
B34
B4
B7
C10
C13
C19
C22
C25
C28
C7
2014/07/01
2014/07/01
2014/07/01
2
UV1F
UV1F
N13P-GT1-A2_FCBGA908
N13P-GT1-A2_FCBGA908
Part 6 of 7
Part 6 of 7
GND_0
GND_1
GND_2
GND_3
GND_4
GND_5
GND_6
GND_7
GND_8
GND_9
GND_10
GND_11
GND_12
GND_13
GND_14
GND_15
GND_16
GND_17
GND_18
GND_19
GND_20
GND_21
GND_22
GND_23
GND_24
GND_25
GND_26
GND_27
GND_28
GND_29
GND_30
GND_31
GND_32
GND_33
GND_34
GND_35
GND_36
GND_37
GND_38
GND_39
GND_40
GND_41
GND_42
GND_43
GND_44
GND_45
GND_46
GND_47
GND_48
GND_49
GND_50
GND_51
GND_52
GND_53
GND_54
GND_55
GND_56
GND_57
GND_58
GND_59
GND_60
GND_61
GND_62
GND_63
GND_64
GND_65
GND_66
GND_67
GND_68
GND_69
GND_70
GND_71
GND_72
GND_73
GND_74
GND_75
GND_76
GND_77
GND_78
GND_79
GND_80
GND_81
GND_82
GND_83
GND_84
GND_85
GND_86
GND_87
GND_88
GND_89
GND_90
GND_91
GND_92
GND_93
GND_94
GND_95
GND_96
GND_97
GND_98
GND_99
Title
Title
Title
N13P_+VGA CORE, GND
N13P_+VGA CORE, GND
N13P_+VGA CORE, GND
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet of
Date: Sheet of
GND
GND
Wednesday, March 27, 201 3
Wednesday, March 27, 201 3
Wednesday, March 27, 201 3
1
D2
GND_100
D31
GND_101
D33
GND_102
E10
GND_103
E22
GND_104
E25
GND_105
E5
GND_106
E7
GND_107
F28
GND_108
F7
GND_109
G10
GND_110
G13
GND_111
G16
GND_112
G19
GND_113
G2
GND_114
G22
GND_115
G25
GND_116
G28
GND_117
G3
GND_118
G30
GND_119
G32
GND_120
G33
GND_121
G5
GND_122
G7
GND_123
K2
GND_124
K28
GND_125
K30
GND_126
K32
GND_127
K33
GND_128
K5
GND_129
K7
GND_130
M13
GND_131
M15
GND_132
M17
GND_133
M18
GND_134
M20
GND_135
M22
GND_136
N12
GND_137
N14
GND_138
N16
GND_139
N19
GND_140
N2
GND_141
N21
GND_142
N23
GND_143
N28
GND_144
N30
GND_145
N32
GND_146
N33
GND_147
N5
GND_148
N7
GND_149
P13
GND_150
P15
GND_151
P17
GND_152
P18
GND_153
P20
GND_154
P22
GND_155
R12
GND_156
R14
GND_157
R16
GND_158
R19
GND_159
R21
GND_160
R23
GND_161
T13
GND_162
T15
GND_163
T17
GND_164
T18
GND_165
T2
GND_166
T20
GND_167
T22
GND_168
AG11
GND_169
T28
GND_170
T32
GND_171
T5
GND_172
T7
GND_173
U12
GND_174
U14
GND_175
U16
GND_176
U19
GND_177
U21
GND_178
U23
GND_179
V12
GND_180
V14
GND_181
V16
GND_182
V19
GND_183
V21
GND_184
V23
GND_185
W13
GND_186
W15
GND_187
W17
GND_188
W18
GND_189
W20
GND_190
W22
GND_191
W28
GND_192
Y12
GND_193
Y14
GND_194
Y16
GND_195
Y19
GND_196
Y21
GND_197
Y23
GND_198
AH11
GND_199
C16
GND_OPT
W32
GND_OPT
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
1
26 69
26 69
26 69
1.0
1.0
1.0
of
5
+3VS
13
D
S
S
@GD
@
QV4
QV4
2N7002_SOT23
2N7002_SOT23
FBA_D[0..63]
FBA_DBI0#<28>
FBA_DBI1#<28>
FBA_DBI2#<28>
FBA_DBI3#<28>
FBA_DBI4#<29>
FBA_DBI5#<29>
FBA_DBI6#<29>
FBA_DBI7#<29>
RV172
@RV172
@
1 2
0_0402_5%
0_0402_5%
DAN202UT106_SC70-3
DAN202UT106_SC70-3
2
3
GC6@
GC6@
RV156
RV156
1 2
NOGC6@
NOGC6@
0_0402_5%
0_0402_5%
FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63
FBA_DBI0#
FBA_DBI1#
FBA_DBI2#
FBA_DBI3#
FBA_DBI4#
FBA_DBI5#
FBA_DBI6#
FBA_DBI7#
FBA_EDC0
FBA_EDC1
FBA_EDC2
FBA_EDC3
FBA_EDC4
FBA_EDC5
FBA_EDC6
FBA_EDC7
S_GC6_EN <32,54>
DV3
DV3
1
UV1B
UV1B
L28
M29
L29
M28
N31
P29
R29
P28
J28
H29
J29
H28
G29
E31
E32
F30
C34
D32
B33
C33
F33
F32
H33
H32
P34
P32
P31
P33
L31
L34
L32
L33
AG28
AF29
AG29
AF28
AD30
AD29
AC29
AD28
AJ29
AK29
AJ30
AK28
AM29
AM31
AN29
AM30
AN31
AN32
AP30
AP32
AM33
AL31
AK33
AK32
AD34
AD32
AC30
AD33
AF31
AG34
AG32
AG33
P30
F31
F34
M32
AD31
AL29
AM32
AF34
M31
G31
E33
M33
AE31
AK30
AN33
AF33
M30
H30
E34
M34
AF30
AK31
AM34
AF32
N14P-GT-A2_FCBGA908
N14P-GT-A2_FCBGA908
FBVDDQ_PWR_EN <61>
12
RV29
RV29
200K_0402_5%
200K_0402_5%
GC6@
GC6@
FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63
FBA_DQM0
FBA_DQM1
FBA_DQM2
FBA_DQM3
FBA_DQM4
FBA_DQM5
FBA_DQM6
FBA_DQM7
FBA_DQS_WP0
FBA_DQS_WP1
FBA_DQS_WP2
FBA_DQS_WP3
FBA_DQS_WP4
FBA_DQS_WP5
FBA_DQS_WP6
FBA_DQS_WP7
FBA_DQS_RN0
FBA_DQS_RN1
FBA_DQS_RN2
FBA_DQS_RN3
FBA_DQS_RN4
FBA_DQS_RN5
FBA_DQS_RN6
FBA_DQS_RN7
FBA_D[0..63]<28,29>
30ohms (ESR=0.01) Bead
P/N;SM010007W00
+1.05VS_VGA +FB_PLLAVDD
FBMA-L11-160808300LMA25T_2P
FBMA-L11-160808300LMA25T_2P
D D
C C
B B
A A
1 2
LV3
LV3
Place close to BGA
DGPU_GC6_EN<14,54>
200mA
+FB_PLLAVDD
FBA_EDC[3..0]<28>
FBA_EDC[7..4]<29>
2
G
RV169
RV169
1 2
@
@
0_0402_5%
0_0402_5%
1 2
FB_CLAMP GC6_EN
GC6@
GC6@
RV18 0_0402_5%
RV18 0_0402_5%
12
RV6810K_0402_5% @ RV6810K_0402_5% @
DGPU_PWROK<19,54,62,63>
5
Part 2 of 7
Part 2 of 7
4
MEMORY INTERFACE
A
MEMORY INTERFACE
A
4
FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30
FBA_CMD31
FBA_CMD_RFU0
FBA_CMD_RFU1
FBA_DEBUG0
FBA_DEBUG1
FBA_CLK0
FBA_CLK0_N
FBA_CLK1
FBA_CLK1_N
FBA_WCK01
FBA_WCK01_N
FBA_WCK23
FBA_WCK23_N
FBA_WCK45
FBA_WCK45_N
FBA_WCK67
FBA_WCK67_N
FBA_WCKB01
FBA_WCKB01_N
FBA_WCKB23
FBA_WCKB23_N
FBA_WCKB45
FBA_WCKB45_N
FBA_WCKB67
FBA_WCKB67_N
FB_CLAMP
FB_DLL_AVDD
FBA_PLL_AVDD
FB_VREF
U30
FBA_CS#_L
T31
FBA_MA3_BA3_L
U29
FBA_MA2_BA0_L
R34
FBA_MA4_BA2_L
R33
FBA_MA5_BA1_L
U32
FBA_WE#_L
U33
FBA_MA7_MA8_L
U28
FBA_MA6_MA11_L
V28
FBA_ABI#_L
V29
FBA_MA12_RFU_L
V30
FBA_MA0_MA10_L
U34
FBA_MA1_MA9_L
U31
FBA_RAS#_L
V34
FBA_RST#_L
V33
FBA_CKE_L
Y32
FBA_CAS#_L
AA31
FBA_CS#_H
AA29
FBA_MA3_BA3_H
AA28
FBA_MA2_BA0_H
AC34
FBA_MA4_BA2_H
AC33
FBA_MA5_BA1_H
AA32
FBA_WE#_H
AA33
FBA_MA7_MA8_H
Y28
FBA_MA6_MA11_H
Y29
FBA_ABI#_H
W31
FBA_MA12_RFU_H
Y30
FBA_MA0_MA10_H
AA34
FBA_MA1_MA9_H
Y31
FBA_RAS#_H
Y34
FBA_RST#_H
Y33
FBA_CKE_H
V31
FBA_CAS#_H
R32
AC32
R28
1 2
1 2
AC28
R30
R31
AB31
AC31
K31
L30
H34
J34
AG30
AG31
AJ34
AK34
J30
J31
J32
J33
AH31
AJ31
AJ32
AJ33
E1
K27
U27
H26
@
FBA_CLK0
FBA_CLK0#
FBA_CLK1
FBA_CLK1#
FBA_WCK0
FBA_WCK0_N
FBA_WCK1
FBA_WCK1_N
FBA_WCK2
FBA_WCK2_N
FBA_WCK3
FBA_WCK3_N
GC6 suppor t on 15"
FB_CLAMP
RV66 10K_0402_5%NOGC6@RV66 10K_0402_5%NOGC6@
CV106 0.1U_0402_10V7KCV106 0.1U_0402_10V7K
1 2
Place close to ball
P
lace close to ball Place close to BGA
FBA_RST#_L
FBA_RST#_H
@
RV5860.4_0402_1%@RV5860.4_0402_1%
RV5960.4_0402_1%@RV5960.4_0402_1%
12
1
2
0.1U_0402_10V7K
0.1U_0402_10V7K
12
FBA_CS#_L <28>
FBA_MA3_BA3_L <28>
FBA_MA2_BA0_L <28>
FBA_MA4_BA2_L <28>
FBA_MA5_BA1_L <28>
FBA_WE#_L <28>
FBA_MA7_MA8_L <28>
FBA_MA6_MA11_L <28>
FBA_ABI#_L <28>
FBA_MA12_RFU_L <28>
FBA_MA0_MA10_L <28>
FBA_MA1_MA9_L <28>
FBA_RAS#_L <28>
FBA_RST#_L <28>
FBA_CAS#_L <28>
FBA_CS#_H <29>
FBA_MA3_BA3_H <29>
FBA_MA2_BA0_H <29>
FBA_MA4_BA2_H <29>
FBA_MA5_BA1_H <29>
FBA_WE#_H <29>
FBA_MA7_MA8_H <29>
FBA_MA6_MA11_H <29>
FBA_ABI#_H <29>
FBA_MA12_RFU_H <29>
FBA_MA0_MA10_H <29>
FBA_MA1_MA9_H <29>
FBA_RAS#_H <29>
FBA_RST#_H <29>
FBA_CAS#_H <29>
FBA_CLK0 <28>
FBA_CLK0# <28>
FBA_CLK1 <29>
FBA_CLK1# <29>
FBA_WCK0 <28>
FBA_WCK0_N <28>
FBA_WCK1 <28>
FBA_WCK1_N <28>
FBA_WCK2 <29>
FBA_WCK2_N <29>
FBA_WCK3 <29>
FBA_WCK3_N <29>
FB_CLAMP <23,54>
+FB_PLLAVDD
1
CV110
CV110
CV107
CV107
2
1U_0402_6.3V6K
1U_0402_6.3V6K
12
RV71
RV71
RV72
RV72
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
+1.5VS_VGA
1
2
22U_0805_6.3V6M
22U_0805_6.3V6M
+FB_PLLAVDD
CV39
CV39
FBC_D[0..63]<30, 31>
+1.5VS_VGA
12
+1.5VS_VGA
12
RV209
RV209
10K_0402_5%
10K_0402_5%
RV221
RV221
10K_0402_5%
10K_0402_5%
FBC_EDC[3..0]<30>
FBC_EDC[7..4]<31>
3
FBC_D[0..63]
FBA_CKE_L <28>
FBA_CKE_H <29>
FBC_DBI0#<30>
FBC_DBI1#<30>
FBC_DBI2#<30>
FBC_DBI3#<30>
FBC_DBI4#<31>
FBC_DBI5#<31>
FBC_DBI6#<31>
FBC_DBI7#<31>
3
2
UV1C
UV1C
Part 3 of 7
FBC_D0
FBC_D1
FBC_D2
FBC_D3
FBC_D4
FBC_D5
FBC_D6
FBC_D7
FBC_D8
FBC_D9
FBC_D10
FBC_D11
FBC_D12
FBC_D13
FBC_D14
FBC_D15
FBC_D16
FBC_D17
FBC_D18
FBC_D19
FBC_D20
FBC_D21
FBC_D22
FBC_D23
FBC_D24
FBC_D25
FBC_D26
FBC_D27
FBC_D28
FBC_D29
FBC_D30
FBC_D31
FBC_D32
FBC_D33
FBC_D34
FBC_D35
FBC_D36
FBC_D37
FBC_D38
FBC_D39
FBC_D40
FBC_D41
FBC_D42
FBC_D43
FBC_D44
FBC_D45
FBC_D46
FBC_D47
FBC_D48
FBC_D49
FBC_D50
FBC_D51
FBC_D52
FBC_D53
FBC_D54
FBC_D55
FBC_D56
FBC_D57
FBC_D58
FBC_D59
FBC_D60
FBC_D61
FBC_D62
FBC_D63
FBC_DBI0#
FBC_DBI1#
FBC_DBI2#
FBC_DBI3#
FBC_DBI4#
FBC_DBI5#
FBC_DBI6#
FBC_DBI7#
FBC_EDC0
FBC_EDC1
FBC_EDC2
FBC_EDC3
FBC_EDC4
FBC_EDC5
FBC_EDC6
FBC_EDC7
G9
E9
G8
F9
F11
G11
F12
G12
G6
F5
E6
F6
F4
G4
E2
F3
C2
D4
D3
C1
B3
C4
B5
C5
A11
C11
D11
B11
D8
A8
C8
B8
F24
G23
E24
G24
D21
E21
G21
F21
G27
D27
G26
E27
E29
F29
E30
D30
A32
C31
C32
B32
D29
A29
C29
B29
B21
C23
A21
C21
B24
C24
B26
C26
E11
E3
A3
C9
F23
F27
C30
A24
D10
D5
C3
B9
E23
E28
B30
A23
D9
E4
B2
A9
D22
D28
A30
B23
Part 3 of 7
FBB_D0
FBB_D1
FBB_D2
FBB_D3
FBB_D4
FBB_D5
FBB_D6
FBB_D7
FBB_D8
FBB_D9
FBB_D10
FBB_D11
FBB_D12
FBB_D13
FBB_D14
FBB_D15
FBB_D16
FBB_D17
FBB_D18
FBB_D19
FBB_D20
FBB_D21
FBB_D22
FBB_D23
FBB_D24
FBB_D25
FBB_D26
FBB_D27
FBB_D28
FBB_D29
FBB_D30
FBB_D31
FBB_D32
FBB_D33
FBB_D34
FBB_D35
FBB_D36
FBB_D37
FBB_D38
FBB_D39
FBB_D40
FBB_D41
FBB_D42
FBB_D43
FBB_D44
FBB_D45
FBB_D46
FBB_D47
FBB_D48
FBB_D49
FBB_D50
FBB_D51
FBB_D52
FBB_D53
FBB_D54
FBB_D55
FBB_D56
FBB_D57
FBB_D58
FBB_D59
FBB_D60
FBB_D61
FBB_D62
FBB_D63
FBB_DQM0
FBB_DQM1
FBB_DQM2
FBB_DQM3
FBB_DQM4
FBB_DQM5
FBB_DQM6
FBB_DQM7
FBB_DQS_WP0
FBB_DQS_WP1
FBB_DQS_WP2
FBB_DQS_WP3
FBB_DQS_WP4
FBB_DQS_WP5
FBB_DQS_WP6
FBB_DQS_WP7
FBB_DQS_RN0
FBB_DQS_RN1
FBB_DQS_RN2
FBB_DQS_RN3
FBB_DQS_RN4
FBB_DQS_RN5
FBB_DQS_RN6
FBB_DQS_RN7
N14P-GT-A2_FCBGA908
N14P-GT-A2_FCBGA908
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF LC FU TURE CENTER. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF LC FU TURE CENTER. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF LC FU TURE CENTER. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT C ONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT C ONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT C ONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENTER .
MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENTER .
MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENTER .
FBB_CMD_RFU0
FBB_CMD_RFU1
MEMORY INTERFACE B
MEMORY INTERFACE B
FBB_WCKB01_N
FBB_WCKB23_N
FBB_WCKB45_N
FBB_WCKB67_N
FBB_CMD0
FBB_CMD1
FBB_CMD2
FBB_CMD3
FBB_CMD4
FBB_CMD5
FBB_CMD6
FBB_CMD7
FBB_CMD8
FBB_CMD9
FBB_CMD10
FBB_CMD11
FBB_CMD12
FBB_CMD13
FBB_CMD14
FBB_CMD15
FBB_CMD16
FBB_CMD17
FBB_CMD18
FBB_CMD19
FBB_CMD20
FBB_CMD21
FBB_CMD22
FBB_CMD23
FBB_CMD24
FBB_CMD25
FBB_CMD26
FBB_CMD27
FBB_CMD28
FBB_CMD29
FBB_CMD30
FBB_CMD31
FBB_DEBUG0
FBB_DEBUG1
FBB_CLK0
FBB_CLK0_N
FBB_CLK1
FBB_CLK1_N
FBB_WCK01
FBB_WCK01_N
FBB_WCK23
FBB_WCK23_N
FBB_WCK45
FBB_WCK45_N
FBB_WCK67
FBB_WCK67_N
FBB_WCKB01
FBB_WCKB23
FBB_WCKB45
FBB_WCKB67
FBB_PLL_AVDD
2012/07/01
2012/07/01
2012/07/01
D13
FBC_CS#_L
E14
FBC_MA3_BA3_L
F14
FBC_MA2_BA0_L
A12
FBC_MA4_BA2_L
B12
FBC_MA5_BA1_L
C14
FBC_WE#_L
B14
FBC_MA7_MA8_L
G15
FBC_MA6_MA11_L
F15
FBC_ABI#_L
E15
FBC_MA12_RFU_L
D15
FBC_MA0_MA10_L
A14
FBC_MA1_MA9_L
D14
FBC_RAS#_L
A15
FBC_RST#_L
B15
FBC_CKE_L
C17
FBC_CAS#_L
D18
FBC_CS#_H
E18
FBC_MA3_BA3_H
F18
FBC_MA2_BA0_H
A20
FBC_MA4_BA2_H
B20
FBC_MA5_BA1_H
C18
FBC_WE#_H
B18
FBC_MA7_MA8_H
G18
FBC_MA6_MA11_H
G17
FBC_ABI#_H
F17
FBC_MA12_RFU_H
D16
FBC_MA0_MA10_H
A18
FBC_MA1_MA9_H
D17
FBC_RAS#_H
A17
FBC_RST#_H
B17
FBC_CKE_H
E17
FBC_CAS#_H
C12
C20
G14
G20
D12
E12
E20
F20
F8
E8
A5
A6
D24
D25
B27
C27
D6
D7
C6
B6
F26
E26
A26
A27
H17
@
1 2
1 2
@
FBC_CLK0
FBC_CLK0#
FBC_CLK1
FBC_CLK1#
FBC_WCK0
FBC_WCK0_N
FBC_WCK1
FBC_WCK1_N
FBC_WCK2
FBC_WCK2_N
FBC_WCK3
FBC_WCK3_N
1
CV108
CV108
2
0.1U_0402_10V7K
0.1U_0402_10V7K
Place close to ball
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
FBC_CS#_L <30>
FBC_MA3_BA3_L <30>
FBC_MA2_BA0_L <30>
FBC_MA4_BA2_L <30>
FBC_MA5_BA1_L <30>
FBC_WE#_L <30>
FBC_MA7_MA8_L <30>
FBC_MA6_MA11_L <30>
FBC_ABI#_L <30>
FBC_MA12_RFU_L <30>
FBC_MA0_MA10_L <30>
FBC_MA1_MA9_L <30>
FBC_RAS#_L <30>
FBC_RST#_L <30>
FBC_CAS#_L <30>
FBC_CS#_H <31>
FBC_MA3_BA3_H <31>
FBC_MA2_BA0_H <31>
FBC_MA4_BA2_H <31>
FBC_MA5_BA1_H <31>
FBC_WE#_H <31>
FBC_MA7_MA8_H <31>
FBC_MA6_MA11_H <31>
FBC_ABI#_H <31>
FBC_MA12_RFU_H <31>
FBC_MA0_MA10_H <31>
FBC_MA1_MA9_H <31>
FBC_RAS#_H <31>
FBC_RST#_H <31>
FBC_CAS#_H <31>
RV6060.4_0402_1%@RV6060.4_0402_1%
RV6160.4_0402_1%@RV6160.4_0402_1%
FBC_CLK0 <30>
FBC_CLK0# <30>
FBC_CLK1 <31>
FBC_CLK1# <31>
FBC_WCK0 <30>
FBC_WCK0_N <30>
FBC_WCK1 <30>
FBC_WCK1_N <30>
FBC_WCK2 <31>
FBC_WCK2_N <31>
FBC_WCK3 <31>
FBC_WCK3_N <31>
+FB_PLLAVDD
+1.5VS_VGA
FBC_RST#_L
FBC_RST#_H
2014/07/01
2014/07/01
2014/07/01
PU for X16 modePU for X16 mode
+1.5VS_VGA
12
+1.5VS_VGA
12
1
GDDR5
Mode H - Mirror Mode Mapping
RV210
RV210
10K_0402_5%
10K_0402_5%
FBC_CKE_L <30>
RV222
RV222
10K_0402_5%
10K_0402_5%
FBC_CKE_H <31>
12
12
RV74
RV74
RV73
RV73
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Address
FBx_CMD0
FBx_CMD1
FBx_CMD2
FBx_CMD3
FBx_CMD4
FBx_CMD5
FBx_CMD6
FBx_CMD7
FBx_CMD8
FBx_CMD9
FBx_CMD10
FBx_CMD11
FBx_CMD12
FBx_CMD13
FBx_CMD14
FBx_CMD15
FBx_CMD16
FBx_CMD17
FBx_CMD18
FBx_CMD19
FBx_CMD20
FBx_CMD21
FBx_CMD22
FBx_CMD23
FBx_CMD24
FBx_CMD25
FBx_CMD26
FBx_CMD27
FBx_CMD28
FBx_CMD29
FBx_CMD30
FBx_CMD31
N13P_MEM Interface
N13P_MEM Interface
N13P_MEM Interface
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Y501 NM-A032Y501 NM-A032
1
CS#
A3_BA3
A2_BA0
A4_BA2
A5_BA1
WE#
A7_A8
A6_A11
ABI#
A12_RFU
A0_A10
A1_A9
RAS#
RST#
CKE#
CAS#
DATA Bus
27 69
27 69
27 69
2..630..31
3
CS#
A3_BA3
A2_BA0
A4_BA2
A5_BA1
WE#
A7_A8
A6_A11
ABI#
A12_RFU
A0_A10
A1_A9
RAS#
RST#
CKE#
CAS#
1.0
1.0
1.0
5
Memory - Lower 32 bits
FBA_D[0..31]<27>
FBA_EDC[3..0]<27>
D D
Follow DG
1 2
FBA_CLK0
RV21 40.2_0402_1%RV 21 40.2_0402_1%
RV123
RV123
160_0402_1%
160_0402_1%
@
FBA_CLK0#
MEM_VREF<23,29,30,31>
@
1 2
1 2
RV28 40.2_0402_1%RV 28 40.2_0402_1%
2
G
G
1
CV155
CV155
2
0.01U_0402_25V7K
0.01U_0402_25V7K
RV212
RV212
1 2
931_0402_1%
931_0402_1%
13
D
D
QV9
QV9
S
S
2N7002W-T/R7_SOT323-3
2N7002W-T/R7_SOT323-3
+1.5VS_VGA
549_0402_1%
549_0402_1%
1.33K_0402_1%
1.33K_0402_1%
10U_0603_6.3V6M
10U_0603_6.3V6M
C C
B B
A A
FBA_DBI0#<27>
FBA_DBI2#<27> FBA_DBI1#<27>
FBA_CLK0<27>
FBA_CLK0#<27>
FBA_CKE_L<27>
FBA_MA2_BA0_L<27>
FBA_MA5_BA1_L<27>
FBA_MA4_BA2_L<27>
FBA_MA3_BA3_L<27>
FBA_MA7_MA8_L<27>
FBA_MA1_MA9_L<27>
FBA_MA0_MA10_L<27>
FBA_MA6_MA11_L<27>
FBA_MA12_RFU_L<27>
FBA_ABI#_L<27>
FBA_RAS#_L<27>
FBA_CS#_L<27>
FBA_CAS#_L<27>
FBA_WE#_L<27>
FBA_WCK0_N<27>
FBA_WCK0<27>
FBA_WCK1_N<27>
FBA_WCK1<27>
FBA_RST#_L<27>
+1.5VS_VGA
RV127
RV127
RV128
RV128
RV213
RV213
1 2
931_0402_1%
931_0402_1%
1.33K_0402_1%
1.33K_0402_1%
RV119
RV119
12
12
RV129
RV129
549_0402_1%
549_0402_1%
RV130
RV130
FBA_CLK0
FBA_CLK0#
FBA_CKE_L
FBA_MA2_BA0_L
FBA_MA5_BA1_L
FBA_MA4_BA2_L
FBA_MA3_BA3_L
FBA_MA7_MA8_L
FBA_MA1_MA9_L
FBA_MA0_MA10_L
FBA_MA6_MA11_L
FBA_MA12_RFU_L
12
RV115
RV115
1K_0402_1%
1K_0402_1%
12
RV117
RV117
12
1K_0402_1%
1K_0402_1%
121_0402_1%
121_0402_1%
FBA_ABI#_L
FBA_RAS#_L
FBA_CS#_L
FBA_CAS#_L
FBA_WE#_L
FBA_WCK0_N
FBA_WCK0
FBA_WCK1_N
FBA_WCK1
+FBA_VREFD_L
+FBA_VREFC0
FBA_RST#_L
+FBA_VREFC0
16 mil
1
CV42
CV42
2
+1.5VS_VGA +1.5VS_VGA
820P_0402_25V7
820P_0402_25V7
+1.5VS_VGA
12
+FBA_VREFD_L
12
820P_0402_25V7
820P_0402_25V7
UV3 SIDE
2
1
1
1
CV166
CV166
2
1U_0603_25V6
1U_0603_25V6
1
CV69
CV69
CV77
CV68
CV68
CV77
2
2
1U_0603_25V6
1U_0603_25V6
1U_0603_25V6
1U_0603_25V6
1U_0603_25V6
1U_0603_25V6
FBA_EDC0
FBA_EDC2
FBA_DBI0#
FBA_DBI2#
1
2
1
2
CV58
CV58
CV78
CV78
UV3
UV3
MF=0 MF=1 MF=0MF=1
MF=0 MF=1 MF=0MF=1
C2
EDC0 EDC3
C13
EDC1 EDC2
R13
EDC2 EDC1
R2
EDC3 EDC0
D2
DBI0# DBI3#
D13
DBI1# DBI2#
P13
DBI2# DBI1#
P2
DBI3# DBI0#
J12
CK
J11
CK#
J3
CKE#
H11
BA0/A2 BA2/A4
K10
BA1/A5 BA3/A3
K11
BA2/A4 BA0/A2
H10
BA3/A3 BA1/A5
K4
A8/A7 A10/A0
H5
A9/A1 A11/A6
H4
A10/A0 A8/A7
K5
A11/A6 A9/A1
J5
A12/RFU/NC
A5
VPP/NC
U5
VPP/NC
J1
MF
J10
SEN
J13
ZQ
J4
ABI#
G3
RAS# CAS#
G12
CS# WE#
L3
CAS# RAS#
L12
WE# CS#
D5
WCK01# WCK23#
D4
WCK01 WCK23
P5
WCK23# WCK01#
P4
WCK23 WCK01
A10
VREFD
U10
VREFD
J14
VREFC
J2
RESET#
H1
VSS
K1
VSS
B5
VSS
G5
VSS
L5
VSS
T5
VSS
B10
VSS
D10
VSS
G10
VSS
L10
VSS
P10
VSS
T10
VSS
H14
VSS
K14
VSS
G1
VDD
L1
VDD
G4
VDD
L4
VDD
C5
VDD
R5
VDD
C10
VDD
R10
VDD
D11
VDD
G11
VDD
L11
VDD
P11
VDD
G14
VDD
L14
VDD
170-BALL
170-BALL
SGRAM GDDR5
SGRAM GDDR5
X76@
X76@
1
1
CV129
CV129
CV132
CV132
2
2
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
1
2
0.1U_0402_10V7K
0.1U_0402_10V7K
CV133
CV133
4
DQ24 DQ0
DQ25 DQ1
DQ26 DQ2
DQ27 DQ3
DQ28 DQ4
DQ29 DQ5
DQ30 DQ6
DQ31 DQ7
DQ16 DQ8
DQ17 DQ9
DQ18 DQ10
DQ19 DQ11
DQ20 DQ12
DQ21 DQ13
DQ22 DQ14
DQ23 DQ15
DQ8 D Q16
DQ9 D Q17
DQ10 DQ18
DQ11 DQ19
DQ12 DQ20
DQ13 DQ21
DQ14 DQ22
DQ15 DQ23
DQ0 D Q24
DQ1 D Q25
DQ2 D Q26
DQ3 D Q27
DQ4 D Q28
DQ5 D Q29
DQ6 D Q30
DQ7 D Q31
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
H5GQ1H24AFR-T2L_BGA170
H5GQ1H24AFR-T2L_BGA170
3
UV4
UV4
MF=0 MF=1 MF=0MF=1
A4
FBA_D0
A2
FBA_D1
B4
FBA_D2
B2
FBA_D3
E4
FBA_D4
E2
FBA_D5
F4
FBA_D6
F2
FBA_D7
A11
A13
B11
B13
E11
E13
F11
F13
U11
FBA_D16
U13
FBA_D17
T11
FBA_D18
T13
FBA_D19
N11
FBA_D20
N13
FBA_D21
M11
FBA_D22
M13
FBA_D23
U4
U2
T4
T2
N4
N2
M4
M2
B1
D1
F1
M1
P1
T1
G2
L2
B3
D3
F3
H3
K3
M3
P3
T3
E5
N5
E10
N10
B12
D12
F12
H12
K12
M12
P12
T12
G13
L13
B14
D14
F14
M14
P14
T14
A1
C1
E1
N1
R1
U1
H2
K2
A3
C3
E3
N3
R3
U3
C4
R4
F5
M5
F10
M10
C11
R11
A12
C12
E12
N12
R12
U12
H13
K13
A14
C14
E14
N14
R14
U14
+1.5VS_VGA
10U_0603_6.3V6M
10U_0603_6.3V6M
2
1
CV174
CV174
BYTE0
BYTE2
UV4 SIDE
1
CV71
CV71
2
1U_0603_25V6
1U_0603_25V6
FBA_DBI3#<27>
+1.5VS_VGA
RV120
RV120
121_0402_1%
121_0402_1%
1
2
1U_0603_25V6
1U_0603_25V6
1
1
CV76
CV76
2
1U_0603_25V6
1U_0603_25V6
1
CV80
CV80
CV79
CV79
CV134
CV134
2
2
1U_0603_25V6
1U_0603_25V6
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
12
1
CV135
CV135
2
FBA_CLK0
FBA_CLK0#
FBA_CKE_L
FBA_MA4_BA2_L
FBA_MA3_BA3_L
FBA_MA2_BA0_L
FBA_MA5_BA1_L
FBA_MA0_MA10_L
FBA_MA6_MA11_L
FBA_MA7_MA8_L
FBA_MA1_MA9_L
FBA_MA12_RFU_L
12
RV116
RV116
1K_0402_1%
1K_0402_1%
12
RV118
RV118
1K_0402_1%
1K_0402_1%
FBA_ABI#_L
FBA_CAS#_L
FBA_WE#_L
FBA_RAS#_L
FBA_CS#_L
FBA_WCK1_N
FBA_WCK1
FBA_WCK0_N
FBA_WCK0
+FBA_VREFD_L
+FBA_VREFC0
FBA_RST#_L
1
CV136
CV136
2
0.1U_0402_10V7K
0.1U_0402_10V7K
FBA_EDC3
FBA_EDC1
FBA_DBI3#
FBA_DBI1#
MF=0 MF=1 MF=0MF=1
C2
EDC0 EDC3
C13
EDC1 EDC2
R13
EDC2 EDC1
R2
EDC3 EDC0
D2
DBI0# DBI3#
D13
DBI1# DBI2#
P13
DBI2# DBI1#
P2
DBI3# DBI0#
J12
CK
J11
CK#
J3
CKE#
H11
BA0/A2 BA2/A4
K10
BA1/A5 BA3/A3
K11
BA2/A4 BA0/A2
H10
BA3/A3 BA1/A5
K4
A8/A7 A10/A0
H5
A9/A1 A11/A6
H4
A10/A0 A8/A7
K5
A11/A6 A9/A1
J5
A12/RFU/NC
A5
VPP/NC
U5
VPP/NC
J1
MF
J10
SEN
J13
ZQ
J4
ABI#
G3
RAS# CAS#
G12
CS# WE#
L3
CAS# RAS#
L12
WE# CS#
D5
WCK01# WCK23#
D4
WCK01 WCK23
P5
WCK23# WCK01#
P4
WCK23 WCK01
A10
VREFD
U10
VREFD
J14
VREFC
J2
RESET#
H1
VSS
K1
VSS
B5
VSS
G5
VSS
L5
VSS
T5
VSS
B10
VSS
D10
VSS
G10
VSS
L10
VSS
P10
VSS
T10
VSS
H14
VSS
K14
VSS
G1
VDD
L1
VDD
G4
VDD
L4
VDD
C5
VDD
R5
VDD
C10
VDD
R10
VDD
D11
VDD
G11
VDD
L11
VDD
P11
VDD
G14
VDD
L14
VDD
170-BALL
170-BALL
SGRAM GDDR5
SGRAM GDDR5
X76@
X76@
DQ24 DQ0
DQ25 DQ1
DQ26 DQ2
DQ27 DQ3
DQ28 DQ4
DQ29 DQ5
DQ30 DQ6
DQ31 DQ7
DQ16 DQ8
DQ17 DQ9
DQ18 DQ10
DQ19 DQ11
DQ20 DQ12
DQ21 DQ13
DQ22 DQ14
DQ23 DQ15
DQ8 D Q16
DQ9 D Q17
DQ10 DQ18
DQ11 DQ19
DQ12 DQ20
DQ13 DQ21
DQ14 DQ22
DQ15 DQ23
DQ0 D Q24
DQ1 D Q25
DQ2 D Q26
DQ3 D Q27
DQ4 D Q28
DQ5 D Q29
DQ6 D Q30
DQ7 D Q31
H5GQ1H24AFR-T2L_BGA170
H5GQ1H24AFR-T2L_BGA170
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
2
A4
FBA_D24
A2
FBA_D25
B4
FBA_D26
B2
FBA_D27
E4
FBA_D28
E2
FBA_D29
F4
FBA_D30
F2
FBA_D31
A11
A13
B11
B13
E11
E13
F11
F13
U11
U13
T11
FBA_D10
T13
FBA_D11
N11
FBA_D12
N13
FBA_D13
M11
FBA_D14
M13
FBA_D15
U4
U2
T4
T2
N4
N2
M4
M2
B1
D1
F1
M1
P1
T1
G2
L2
B3
D3
F3
H3
K3
M3
P3
T3
E5
N5
E10
N10
B12
D12
F12
H12
K12
M12
P12
T12
G13
L13
B14
D14
F14
M14
P14
T14
A1
C1
E1
N1
R1
U1
H2
K2
A3
C3
E3
N3
R3
U3
C4
R4
F5
M5
F10
M10
C11
R11
A12
C12
E12
N12
R12
U12
H13
K13
A14
C14
E14
N14
R14
U14
FBA_D8
FBA_D9
BYTE3
GDDR5
B
TE1
Y
+1.5VS_VGA+1.5VS_VGA
Mode H - Mirror Mode Mapping
Address
FBx_CMD0
FBx_CMD1
FBx_CMD2
FBx_CMD3
FBx_CMD4
FBx_CMD5
FBx_CMD6
FBx_CMD7
FBx_CMD8
FBx_CMD9
FBx_CMD10
FBx_CMD11
FBx_CMD12
FBx_CMD13
FBx_CMD14
FBx_CMD15
FBx_CMD16
FBx_CMD17
FBx_CMD18
FBx_CMD19
FBx_CMD20
FBx_CMD21
FBx_CMD22
FBx_CMD23
FBx_CMD24
FBx_CMD25
FBx_CMD26
FBx_CMD27
FBx_CMD28
FBx_CMD29
FBx_CMD30
FB
x_CMD31
1
DATA Bus
0..31 32..63
CS#
A3_BA3
A2_BA0
A4_BA2
A5_BA1
WE#
A7_A8
A6_A11
ABI#
A12_RFU
A0_A10
A1_A9
RAS#
RST#
CKE#
CAS#
CS#
A3_BA3
A2_BA0
A4_BA2
A5_BA1
WE#
A7_A8
A6_A11
ABI#
A12_RFU
A0_A10
A1_A9
RAS#
RST#
CKE#
CAS#
Title
Title
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
5
4
3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
2012/07/01
2012/07/01
2012/07/01
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2014/07/01
2014/07/01
2014/07/01
Title
N13P_GDDR5_A Lower
N13P_GDDR5_A Lower
N13P_GDDR5_A Lower
Size Doc ument Number Rev
Size Doc ument Number Rev
Size Doc ument Number Rev
Custom
Custom
Custom
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Date: Sheet of
Date: Sheet of
Date: Sheet of
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
1
28 69
28 69
28 69
1.0
1.0
1.0
5
Memory - Upper 32 bits
C2
FBA_EDC4
C13
R13
FBA_CLK1
FBA_CLK1#
FBA_MA2_BA0_H
FBA_MA5_BA1_H
FBA_MA4_BA2_H
FBA_MA3_BA3_H
FBA_MA7_MA8_H
FBA_MA1_MA9_H
FBA_MA0_MA10_H
FBA_MA6_MA11_H
FBA_MA12_RFU_H
12
+FBA_VREFC1
16 mil
CV59
CV59
+FBA_VREFD_H
820P_0402_25V7
820P_0402_25V7
1
CV138
CV138
2
0.1U_0402_10V7K
0.1U_0402_10V7K
FBA_EDC6
FBA_DBI4#
FBA_DBI6#
FBA_CKE_H
12
RV131
RV131
1K_0402_1%
1K_0402_1%
12
RV133
RV133
1K_0402_1%
1K_0402_1%
FBA_ABI#_H
FBA_RAS#_H
FBA_CS#_H
FBA_CAS#_H
FBA_WE#_H
FBA_WCK2_N
FBA_WCK2
FBA_WCK3_N
FBA_WCK3
+FBA_VREFD_H
+FBA_VREFC1
FBA_RST#_H
+1.5VS_VGA
1
CV60
CV60
2
1
CV142
CV142
2
R2
D2
D13
P13
P2
J12
J11
J3
H11
K10
K11
H10
K4
H5
H4
K5
J5
A5
U5
J1
J10
J13
J4
G3
G12
L3
L12
D5
D4
P5
P4
A10
U10
J14
J2
H1
K1
B5
G5
L5
T5
B10
D10
G10
L10
P10
T10
H14
K14
G1
L1
G4
L4
C5
R5
C10
R10
D11
G11
L11
P11
G14
L14
1
CV137
CV137
2
0.1U_0402_10V7K
0.1U_0402_10V7K
FBA_D[63..32]<27>
D D
FBA_EDC[7..4]<27>
Follow DG
1 2
FBA_CLK1
RV31 40.2_0402_1%RV 31 40.2_0402_1%
RV139
RV139
160_0402_1%
C C
B B
MEM_VREF<23,28,30,31>
A A
FBA_CLK1#
160_0402_1%
@
@
1 2
1 2
RV36 40.2_0402_1%RV 36 40.2_0402_1%
13
D
D
2
G
G
QV11
QV11
S
S
2N7002W-T/R7_SOT323-3
2N7002W-T/R7_SOT323-3
+1.5VS_VGA
UV5 SIDE
2
CV179
CV179
1
1U_0603_25V6
1U_0603_25V6
10U_0603_6.3V6M
10U_0603_6.3V6M
0.01U_0402_25V7K
0.01U_0402_25V7K
1 2
1
CV84
CV84
2
1
CV175
CV175
2
RV214
RV214
931_0402_1%
931_0402_1%
RV215
RV215
1 2
931_0402_1%
931_0402_1%
1
2
1U_0603_25V6
1U_0603_25V6
549_0402_1%
549_0402_1%
1.33K_0402_1%
1.33K_0402_1%
549_0402_1%
549_0402_1%
1.33K_0402_1%
1.33K_0402_1%
CV81
CV81
1U_0603_25V6
1U_0603_25V6
FBA_MA0_MA10_H<27>
FBA_MA6_MA11_H<27>
FBA_MA12_RFU_H<27>
RV143
RV143
RV144
RV144
RV145
RV145
RV146
RV146
1
2
FBA_CLK1<27>
FBA_CLK1#<27>
FBA_CKE_H<27>
FBA_MA2_BA0_H<27>
FBA_MA5_BA1_H<27>
FBA_MA4_BA2_H<27>
FBA_MA3_BA3_H<27>
FBA_MA7_MA8_H<27>
FBA_MA1_MA9_H<27>
FBA_ABI#_H<27>
FBA_RAS#_H<27>
FBA_CAS#_H<27>
FBA_WE#_H<27>
FBA_WCK2_N<27>
FBA_WCK2<27>
FBA_WCK3_N<27>
FBA_WCK3<27>
FBA_RST#_H<27>
+1.5VS_VGA
+1.5VS_VGA
CV82
CV82
FBA_DBI4#<27>
FBA_DBI6#<27>
RV135
RV135
121_0402_1%
121_0402_1%
FBA_CS#_H<27>
12
12
1
2
820P_0402_25V7
820P_0402_25V7
12
12
1
CV83
CV83
2
1U_0603_25V6
1U_0603_25V6
0.1U_0402_10V7K
0.1U_0402_10V7K
4
UV5
UV5
MF=0 MF=1 MF=0MF=1
MF=0 MF=1 MF=0MF=1
EDC0 EDC3
EDC1 EDC2
EDC2 EDC1
EDC3 EDC0
DBI0# DBI3#
DBI1# DBI2#
DBI2# DBI1#
DBI3# DBI0#
CK
CK#
CKE#
BA0/A2 BA2/A4
BA1/A5 BA3/A3
BA2/A4 BA0/A2
BA3/A3 BA1/A5
A8/A7 A10/A0
A9/A1 A11/A6
A10/A0 A8/A7
A11/A6 A9/A1
A12/RFU/NC
VPP/NC
VPP/NC
MF
SEN
ZQ
ABI#
RAS# CAS#
CS# WE#
CAS# RAS#
WE# CS#
WCK01# WCK23#
WCK01 WCK23
WCK23# WCK01#
WCK23 WCK01
VREFD
VREFD
VREFC
RESET#
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
170-BALL
170-BALL
SGRAM GDDR5
SGRAM GDDR5
X76@
X76@
DQ24 DQ0
DQ25 DQ1
DQ26 DQ2
DQ27 DQ3
DQ28 DQ4
DQ29 DQ5
DQ30 DQ6
DQ31 DQ7
DQ16 DQ8
DQ17 DQ9
DQ18 DQ10
DQ19 DQ11
DQ20 DQ12
DQ21 DQ13
DQ22 DQ14
DQ23 DQ15
DQ8 D Q16
DQ9 D Q17
DQ10 DQ18
DQ11 DQ19
DQ12 DQ20
DQ13 DQ21
DQ14 DQ22
DQ15 DQ23
DQ0 D Q24
DQ1 D Q25
DQ2 D Q26
DQ3 D Q27
DQ4 D Q28
DQ5 D Q29
DQ6 D Q30
DQ7 D Q31
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
H5GQ1H24AFR-T2L_BGA170
H5GQ1H24AFR-T2L_BGA170
3
UV6
UV6
MF=0 MF=1 MF=0MF=1
MF=0 MF=1 MF=0MF=1
A4
FBA_D32
A2
FBA_D33
B4
FBA_D34
B2
FBA_D35
E4
FBA_D36
E2
FBA_D37
F4
FBA_D38
F2
FBA_D39
A11
A13
B11
B13
E11
E13
F11
F13
U11
FBA_D48
U13
FBA_D49
T11
FBA_D50
T13
FBA_D51
N11
FBA_D52
N13
FBA_D53
M11
FBA_D54
M13
FBA_D55
U4
U2
T4
T2
N4
N2
M4
M2
B1
D1
F1
M1
P1
T1
G2
L2
B3
D3
F3
H3
K3
M3
P3
T3
E5
N5
E10
N10
B12
D12
F12
H12
K12
M12
P12
T12
G13
L13
B14
D14
F14
M14
P14
T14
A1
C1
E1
N1
R1
U1
H2
K2
A3
C3
E3
N3
R3
U3
C4
R4
F5
M5
F10
M10
C11
R11
A12
C12
E12
N12
R12
U12
H13
K13
A14
C14
E14
N14
R14
U14
+1.5VS_VGA
+1.5VS_VGA
10U_0603_6.3V6M
10U_0603_6.3V6M
BYTE4
FBA_DBI7#<27>
FBA_DBI5#<27>
FBA_CLK1
FBA_CLK1#
FBA_CKE_H
FBA_MA4_BA2_H
FBA_MA3_BA3_H
FBA_MA2_BA0_H
+1.5VS_VGA
RV136
RV136
121_0402_1%
121_0402_1%
1
CV145
CV145
2
0.1U_0402_10V7K
0.1U_0402_10V7K
12
0.1U_0402_10V7K
0.1U_0402_10V7K
FBA_MA5_BA1_H
FBA_MA0_MA10_H
FBA_MA6_MA11_H
FBA_MA7_MA8_H
FBA_MA1_MA9_H
FBA_MA12_RFU_H
RV132
RV132
1K_0402_1%
1K_0402_1%
RV134
RV134
1K_0402_1%
1K_0402_1%
FBA_ABI#_H
FBA_CAS#_H
FBA_WE#_H
FBA_RAS#_H
FBA_CS#_H
FBA_WCK3_N
FBA_WCK3
FBA_WCK2_N
FBA_WCK2
+FBA_VREFD_H
+FBA_VREFC1
FBA_RST#_H
+1.5VS_VGA
1
CV143
CV143
2
0.1U_0402_10V7K
0.1U_0402_10V7K
BYTE6
SIDE
UV6
1
2
1
1
1
CV87
CV87
CV187
CV187
2
2
1U_0603_25V6
1U_0603_25V6
1U_0603_25V6
1U_0603_25V6
1
CV85
CV85
CV86
CV88
CV88
CV86
2
2
1U_0603_25V6
1U_0603_25V6
1U_0603_25V6
1U_0603_25V6
FBA_EDC7
FBA_EDC5
FBA_DBI7#
FBA_DBI5#
12
12
1
2
C2
EDC0 EDC3
C13
EDC1 EDC2
R13
EDC2 EDC1
R2
EDC3 EDC0
D2
DBI0# DBI3#
D13
DBI1# DBI2#
P13
DBI2# DBI1#
P2
DBI3# DBI0#
J12
CK
J11
CK#
J3
CKE#
H11
BA0/A2 BA2/A4
K10
BA1/A5 BA3/A3
K11
BA2/A4 BA0/A2
H10
BA3/A3 BA1/A5
K4
A8/A7 A10/A0
H5
A9/A1 A11/A6
H4
A10/A0 A8/A7
K5
A11/A6 A9/A1
J5
A12/RFU/NC
A5
VPP/NC
U5
VPP/NC
J1
MF
J10
SEN
J13
ZQ
J4
ABI#
G3
RAS# CAS#
G12
CS# WE#
L3
CAS# RAS#
L12
WE# CS#
D5
WCK01# WCK23#
D4
WCK01 WCK23
P5
WCK23# WCK01#
P4
WCK23 WCK01
A10
VREFD
U10
VREFD
J14
VREFC
J2
RESET#
H1
VSS
K1
VSS
B5
VSS
G5
VSS
L5
VSS
T5
VSS
B10
VSS
D10
VSS
G10
VSS
L10
VSS
P10
VSS
T10
VSS
H14
VSS
K14
VSS
G1
VDD
L1
VDD
G4
VDD
L4
VDD
C5
VDD
R5
VDD
C10
VDD
R10
VDD
D11
VDD
G11
VDD
L11
VDD
P11
VDD
G14
VDD
L14
VDD
170-BALL
170-BALL
SGRAM GDDR5
SGRAM GDDR5
X76@
X76@
CV144
CV144
H5GQ1H24AFR-T2L_BGA170
H5GQ1H24AFR-T2L_BGA170
2
DQ24 DQ0
DQ25 DQ1
DQ26 DQ2
DQ27 DQ3
DQ28 DQ4
DQ29 DQ5
DQ30 DQ6
DQ31 DQ7
DQ16 DQ8
DQ17 DQ9
DQ18 DQ10
DQ19 DQ11
DQ20 DQ12
DQ21 DQ13
DQ22 DQ14
DQ23 DQ15
DQ8 D Q16
DQ9 D Q17
DQ10 DQ18
DQ11 DQ19
DQ12 DQ20
DQ13 DQ21
DQ14 DQ22
DQ15 DQ23
DQ0 D Q24
DQ1 D Q25
DQ2 D Q26
DQ3 D Q27
DQ4 D Q28
DQ5 D Q29
DQ6 D Q30
DQ7 D Q31
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
1
A4
FBA_D56
A2
FBA_D57
B4
FBA_D58
B2
FBA_D59
E4
FBA_D60
E2
FBA_D61
F4
FBA_D62
F2
FBA_D63
A11
A13
B11
B13
E11
E13
F11
F13
U11
FBA_D40
U13
FBA_D41
T11
FBA_D42
T13
FBA_D43
N11
FBA_D44
N13
FBA_D45
M11
FBA_D46
M13
FBA_D47
U4
U2
T4
T2
N4
N2
M4
M2
B1
D1
F1
M1
P1
T1
G2
L2
B3
D3
F3
H3
K3
M3
P3
T3
E5
N5
E10
N10
B12
D12
F12
H12
K12
M12
P12
T12
G13
L13
B14
D14
F14
M14
P14
T14
A1
C1
E1
N1
R1
U1
H2
K2
A3
C3
E3
N3
R3
U3
C4
R4
F5
M5
F10
M10
C11
R11
A12
C12
E12
N12
R12
U12
H13
K13
A14
C14
E14
N14
R14
U14
+1.5VS_VGA
BYT
BYTE5
E7
GDDR5
Mod
e H - Mirror Mode Mapping
Address
FBx_CMD0
FBx_CMD1
FBx_CMD2
FBx_CMD3
FBx_CMD4
FBx_CMD5
FBx_CMD6
FBx_CMD7
FBx_CMD8
FBx_CMD9
FBx_CMD10
FBx_CMD11
FBx_CMD12
FBx_CMD13
FBx_CMD14
FBx_CMD15
FBx_CMD16
FBx_CMD17
FBx_CMD18
FBx_CMD19
FBx_CMD20
FBx_CMD21
FBx_CMD22
FBx_CMD23
FBx_CMD24
FBx_CMD25
FBx_CMD26
FBx_CMD27
FBx_CMD28
FBx_CMD29
FBx_CMD30
FBx_CMD31
0..31
CS#
A3_BA3
A2_BA0
A4_BA2
A5_BA1
WE#
A7_A8
A6_A11
ABI#
A12_RFU
A0_A10
A1_A9
RAS#
RST#
CKE#
CAS#
DATA Bus
32..63
CS#
A3_BA3
A2_BA0
A4_BA2
A5_BA1
WE#
A7_A8
A6_A11
ABI#
A12_RFU
A0_A10
A1_A9
RAS#
RST
CKE#
CAS#
#
Title
Title
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
5
4
3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
2012/07/01
2012/07/01
2012/07/01
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2014/07/01
2014/07/01
2014/07/01
Title
N13P_GDDR5_A Upper
N13P_GDDR5_A Upper
N13P_GDDR5_A Upper
Size Doc ument Number Rev
Size Doc ument Number Rev
Size Doc ument Number Rev
Custom
Custom
Custom
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Date: Sheet of
Date: Sheet of
Date: Sheet of
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
1
29 69
29 69
29 69
1.0
1.0
1.0
5
4
3
2
1
Memory Partition C - Lower 32 bits
UV8
UV7
UV7
MF=0 MF=1 MF=0MF=1
MF=0 MF=1 MF=0MF=1
C2
FBC_EDC0
FBC_MA0_MA10_L
FBC_MA6_MA11_L
FBC_MA12_RFU_L
+FBC_VREFC0
1
CV61
CV61
2
820P_0402_25V7
820P_0402_25V7
+FBC_VREFD_L
1
CV160
CV160
2
0.1U_0402_10V7K
0.1U_0402_10V7K
FBC_EDC2
FBC_DBI0#
FBC_DBI2#
FBC_CLK0
FBC_CLK0#
FBC_CKE_L
FBC_MA2_BA0_L
FBC_MA5_BA1_L
FBC_MA4_BA2_L
FBC_MA3_BA3_L
FBC_MA7_MA8_L
FBC_MA1_MA9_L
12
RV147
RV147
1K_0402_1%
1K_0402_1%
12
RV149
RV149
1K_0402_1%
1K_0402_1%
FBC_ABI#_L
FBC_RAS#_L
FBC_CS#_L
FBC_CAS#_L
FBC_WE#_L
FBC_WCK0_N
FBC_WCK0
FBC_WCK1_N
FBC_WCK1
+FBC_VREFD_L
+FBC_VREFC0
FBC_RST#_L
+1.5VS_VGA
1
CV62
CV62
2
820P_0402_25V7
820P_0402_25V7
1
CV157
CV157
2
0.1U_0402_10V7K
0.1U_0402_10V7K
FBC_D[0..31]<27>
D D
C C
B B
A A
FBC_EDC[3..0]<27>
Follow DG
FBC_CLK0
FBC_CLK0#
MEM_VREF<23,28,29,31>
+1.5VS_VGA
1 2
RV37 40.2_0402_1%RV37 40.2_0402_1%
RV155
RV155
160_0402_1%
160_0402_1%
@
@
1 2
1 2
RV39 40.2_0402_1%RV39 40.2_0402_1%
13
D
D
2
G
G
S
S
7 SIDE
UV
1
2
CV91
CV91
CV199
CV199
2
1
1U_0603_25V6
1U_0603_25V6
10U_0603_6.3V6M
10U_0603_6.3V6M
1
CV195
CV195
2
0.01U_0402_25V7K
0.01U_0402_25V7K
RV216
RV216
1 2
931_0402_1%
931_0402_1%
1.33K_0402_1%
1.33K_0402_1%
549_0402_1%
549_0402_1%
RV217
RV217
1 2
931_0402_1%
931_0402_1%
1.33K_0402_1%
1.33K_0402_1%
QV13
QV13
2N7002W-T/R7_SOT323-3
2N7002W-T/R7_SOT323-3
1
1
CV92
CV92
CV89
CV89
2
2
1U_0603_25V6
1U_0603_25V6
1U_0603_25V6
1U_0603_25V6
FBC_CLK0<27>
FBC_CLK0#<27>
FBC_CKE_L<27>
FBC_MA2_BA0_L<27>
FBC_MA5_BA1_L<27>
FBC_MA4_BA2_L<27>
FBC_MA3_BA3_L<27>
FBC_MA7_MA8_L<27>
FBC_MA1_MA9_L<27>
FBC_MA0_MA10_L<27>
FBC_MA6_MA11_L<27>
FBC_MA12_RFU_L<27>
FBC_ABI#_L<27>
FBC_RAS#_L<27>
FBC_CS#_L<27>
FBC_CAS#_L<27>
FBC_WE#_L<27>
FBC_WCK0_N<27>
FBC_WCK0<27>
FBC_WCK1_N<27>
FBC_WCK1<27>
FBC_RST#_L<27>
RV159
RV159
549_0402_1%
549_0402_1%
RV160
RV160
+1.5VS_VGA
RV161
RV161
RV162
RV162
1
2
1U_0603_25V6
1U_0603_25V6
RV151
RV151
+1.5VS_VGA
12
12
12
12
CV90
CV90
0.1U_0402_10V7K
0.1U_0402_10V7K
FBC_DBI0#<27>
FBC_DBI2#<27>
12
121_0402_1%
121_0402_1%
1
2
CV159
CV159
EDC0 EDC3
C13
EDC1 EDC2
R13
EDC2 EDC1
R2
EDC3 EDC0
D2
DBI0# DBI3#
D13
DBI1# DBI2#
P13
DBI2# DBI1#
P2
DBI3# DBI0#
J12
CK
J11
CK#
J3
CKE#
H11
BA0/A2 BA2/A4
K10
BA1/A5 BA3/A3
K11
BA2/A4 BA0/A2
H10
BA3/A3 BA1/A5
K4
A8/A7 A10/A0
H5
A9/A1 A11/A6
H4
A10/A0 A8/A7
K5
A11/A6 A9/A1
J5
A12/RFU/NC
A5
VPP/NC
U5
VPP/NC
J1
MF
J10
SEN
J13
ZQ
J4
ABI#
G3
RAS# CAS#
G12
CS# WE#
L3
CAS# RAS#
L12
WE# CS#
D5
WCK01# WCK23#
D4
WCK01 WCK23
P5
WCK23# WCK01#
P4
WCK23 WCK01
A10
VREFD
U10
VREFD
J14
VREFC
J2
RESET#
H1
VSS
K1
VSS
B5
VSS
G5
VSS
L5
VSS
T5
VSS
B10
VSS
D10
VSS
G10
VSS
L10
VSS
P10
VSS
T10
VSS
H14
VSS
K14
VSS
G1
VDD
L1
VDD
G4
VDD
L4
VDD
C5
VDD
R5
VDD
C10
VDD
R10
VDD
D11
VDD
G11
VDD
L11
VDD
P11
VDD
G14
VDD
L14
VDD
170-BALL
170-BALL
SGRAM GDDR5
SGRAM GDDR5
X76@
X76@
DQ24 DQ0
DQ25 DQ1
DQ26 DQ2
DQ27 DQ3
DQ28 DQ4
DQ29 DQ5
DQ30 DQ6
DQ31 DQ7
DQ16 DQ8
DQ17 DQ9
DQ18 DQ10
DQ19 DQ11
DQ20 DQ12
DQ21 DQ13
DQ22 DQ14
DQ23 DQ15
DQ8 DQ16
DQ9 DQ17
DQ10 DQ18
DQ11 DQ19
DQ12 DQ20
DQ13 DQ21
DQ14 DQ22
DQ15 DQ23
DQ0 DQ24
DQ1 DQ25
DQ2 DQ26
DQ3 DQ27
DQ4 DQ28
DQ5 DQ29
DQ6 DQ30
DQ7 DQ31
H5GQ1H24AFR-T2L_BGA170
H5GQ1H24AFR-T2L_BGA170
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
A4
FBC_D0
A2
FBC_D1
B4
FBC_D2
B2
FBC_D3
BY
+1.5VS_VGA
TE0
BYTE2
+1.5VS_VGA
10U_0603_6.3V6M
10U_0603_6.3V6M
2
1
CV207
CV207
UV8 SIDE
1
CV95
CV95
2
1U_0603_25V6
1U_0603_25V6
FBC_DBI3#<27>
FBC_DBI1#<27>
+1.5VS_VGA
RV152
RV152
121_0402_1%
121_0402_1%
1
1
2
1U_0603_25V6
1U_0603_25V6
1
CV93
CV93
CV94
CV96
CV96
CV94
2
2
1U_0603_25V6
1U_0603_25V6
1U_0603_25V6
1U_0603_25V6
0.1U_0402_10V7K
0.1U_0402_10V7K
E4
FBC_D4
E2
FBC_D5
F4
FBC_D6
F2
FBC_D7
A11
A13
B11
B13
E11
E13
F11
F13
U11
FBC_D16
U13
FBC_D17
T11
FBC_D18
T13
FBC_D19
N11
FBC_D20
N13
FBC_D21
M11
FBC_D22
M13
FBC_D23
U4
U2
T4
T2
N4
N2
M4
M2
B1
D1
F1
M1
P1
T1
G2
L2
B3
D3
F3
H3
K3
M3
P3
T3
E5
N5
E10
N10
B12
D12
F12
H12
K12
M12
P12
T12
G13
L13
B14
D14
F14
M14
P14
T14
A1
C1
E1
N1
R1
U1
H2
K2
A3
C3
E3
N3
R3
U3
C4
R4
F5
M5
F10
M10
C11
R11
A12
C12
E12
N12
R12
U12
H13
K13
A14
C14
E14
N14
R14
U14
12
1
CV163
CV163
2
FBC_EDC3
FBC_EDC1
FBC_DBI3#
FBC_DBI1#
FBC_CLK0
FBC_CLK0#
FBC_CKE_L
FBC_MA4_BA2_L
FBC_MA3_BA3_L
FBC_MA2_BA0_L
FBC_MA5_BA1_L
FBC_MA0_MA10_L
FBC_MA6_MA11_L
FBC_MA7_MA8_L
FBC_MA1_MA9_L
FBC_MA12_RFU_L
12
RV148
RV148
1K_0402_1%
1K_0402_1%
12
RV150
RV150
1K_0402_1%
1K_0402_1%
FBC_ABI#_L
FBC_CAS#_L
FBC_WE#_L
FBC_RAS#_L
FBC_CS#_L
FBC_WCK1_N
FBC_WCK1
FBC_WCK0_N
FBC_WCK0
+FBC_VREFD_L
+FBC_VREFC0
FBC_RST#_L
+1.5VS_VGA
1
CV161
CV161
2
0.1U_0402_10V7K
0.1U_0402_10V7K
UV8
MF=0 MF=1 MF=0MF=1
MF=0 MF=1 MF=0MF=1
C2
EDC0 EDC3
C13
EDC1 EDC2
R13
EDC2 EDC1
R2
EDC3 EDC0
D2
DBI0# DBI3#
D13
DBI1# DBI2#
P13
DBI2# DBI1#
P2
DBI3# DBI0#
J12
CK
J11
CK#
J3
CKE#
H11
BA0/A2 BA2/A4
K10
BA1/A5 BA3/A3
K11
BA2/A4 BA0/A2
H10
BA3/A3 BA1/A5
K4
A8/A7 A10/A0
H5
A9/A1 A11/A6
H4
A10/A0 A8/A7
K5
A11/A6 A9/A1
J5
A12/RFU/NC
A5
VPP/NC
U5
VPP/NC
J1
MF
J10
SEN
J13
ZQ
J4
ABI#
G3
RAS# CAS#
G12
CS# WE#
L3
CAS# RAS#
L12
WE# CS#
D5
WCK01# WCK23#
D4
WCK01 WCK23
P5
WCK23# WCK01#
P4
WCK23 WCK01
A10
VREFD
U10
VREFD
J14
VREFC
J2
RESET#
H1
VSS
K1
VSS
B5
VSS
G5
VSS
L5
VSS
T5
VSS
B10
VSS
D10
VSS
G10
VSS
L10
VSS
P10
VSS
T10
VSS
H14
VSS
K14
VSS
G1
VDD
L1
VDD
G4
VDD
L4
VDD
C5
VDD
R5
VDD
C10
VDD
R10
VDD
D11
VDD
G11
VDD
L11
VDD
P11
VDD
G14
VDD
L14
VDD
170-BALL
170-BALL
SGRAM GDDR5
SGRAM GDDR5
X76@
X76@
1
CV162
CV162
2
0.1U_0402_10V7K
0.1U_0402_10V7K
DQ24 DQ0
DQ25 DQ1
DQ26 DQ2
DQ27 DQ3
DQ28 DQ4
DQ29 DQ5
DQ30 DQ6
DQ31 DQ7
DQ16 DQ8
DQ17 DQ9
DQ18 DQ10
DQ19 DQ11
DQ20 DQ12
DQ21 DQ13
DQ22 DQ14
DQ23 DQ15
DQ8 DQ16
DQ9 DQ17
DQ10 DQ18
DQ11 DQ19
DQ12 DQ20
DQ13 DQ21
DQ14 DQ22
DQ15 DQ23
DQ0 DQ24
DQ1 DQ25
DQ2 DQ26
DQ3 DQ27
DQ4 DQ28
DQ5 DQ29
DQ6 DQ30
DQ7 DQ31
H5GQ1H24AFR-T2L_BGA170
H5GQ1H24AFR-T2L_BGA170
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
A4
FBC_D24
A2
FBC_D25
B4
FBC_D26
B2
FBC_D27
E4
FBC_D28
E2
FBC_D29
F4
FBC_D30
F2
FBC_D31
A11
A13
B11
B13
E11
E13
F11
F13
U11
FBC_D8
U13
FBC_D9
T11
FBC_D10
T13
FBC_D11
N11
FBC_D12
N13
FBC_D13
M11
FBC_D14
M13
FBC_D15
U4
U2
T4
T2
N4
N2
M4
M2
B1
D1
F1
M1
P1
T1
G2
L2
B3
D3
F3
H3
K3
M3
P3
T3
E5
N5
E10
N10
B12
D12
F12
H12
K12
M12
P12
T12
G13
L13
B14
D14
F14
M14
P14
T14
A1
C1
E1
N1
R1
U1
H2
K2
A3
C3
E3
N3
R3
U3
C4
R4
F5
M5
F10
M10
C11
R11
A12
C12
E12
N12
R12
U12
H13
K13
A14
C14
E14
N14
R14
U14
+1.5VS_VGA
BYTE3
GDDR5
Mode H - Mirror Mode Mapping
BYTE1
Address
FBx_CMD0
FBx_CMD1
FBx_CMD2
FBx_CMD3
FBx_CMD4
FBx_CMD5
FBx_CMD6
FBx_CMD7
FBx_CMD8
FBx_CMD9
FBx_CMD10
FBx_CMD11
FBx_CMD12
FBx_CMD13
FBx_CMD14
FBx_CMD15
FBx_CMD16
FBx_CMD17
FBx_CMD18
FBx_CMD19
FBx_CMD20
FBx_CMD21
FBx_CMD22
FBx_CMD23
FBx_CMD24
FBx_CMD25
FBx_CMD26
FBx_CMD27
FBx_CMD28
FBx_CMD29
FBx_CMD30
FBx_CMD31
0..31
CS#
A3_BA3
A2_BA0
A4_BA2
A5_BA1
WE#
A7_A8
A6_A11
ABI#
A12_RFU
A0_A10
A1_A9
RAS#
RST#
CKE#
CAS#
DATA Bus
32..63
CS#
A3_BA3
A2_BA0
A4_BA2
A5_BA1
WE#
A7_A8
A6_A11
ABI#
A12_RFU
A0_A10
A1_A9
RAS#
RS
T#
CKE#
CAS#
Title
Title
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF LC FU TURE CENTER. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF LC FU TURE CENTER. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF LC FU TURE CENTER. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT C ONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT C ONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT C ONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENTER .
MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENTER .
5
4
3
MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENTER .
2012/07/01
2012/07/01
2012/07/01
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2014/07/01
2014/07/01
2014/07/01
Title
N13P_GDDR5_C Lower
N13P_GDDR5_C Lower
N13P_GDDR5_C Lower
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Date: Sheet of
Date: Sheet of
Date: Sheet of
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
1
30 69
30 69
30 69
1.0
1.0
1.0
5
4
3
2
1
Memory Partition C - Upper 32 bits
UV9
UV9
MF=0 MF=1 MF=0MF=1
MF=0 MF=1 MF=0MF=1
C2
FBC_EDC4
FBC_CLK1#
FBC_MA0_MA10_H
FBC_MA6_MA11_H
FBC_MA12_RFU_H
1
CV64
CV64
2
820P_0402_25V7
820P_0402_25V7
CV167
CV167
0.1U_0402_10V7K
0.1U_0402_10V7K
FBC_EDC6
FBC_DBI4#
FBC_DBI6#
FBC_CLK1
FBC_CKE_H
FBC_MA2_BA0_H
FBC_MA5_BA1_H
FBC_MA4_BA2_H
FBC_MA3_BA3_H
FBC_MA7_MA8_H
FBC_MA1_MA9_H
12
RV163
RV163
1K_0402_1%
1K_0402_1%
12
RV165
RV165
1K_0402_1%
1K_0402_1%
FBC_ABI#_H
FBC_RAS#_H
FBC_CS#_H
FBC_CAS#_H
FBC_WE#_H
FBC_WCK2_N
FBC_WCK2
FBC_WCK3_N
FBC_WCK3
+FBC_VREFD_H
+FBC_VREFC1
FBC_RST#_H
+1.5VS_VGA
1
1
CV164
CV164
2
2
0.1U_0402_10V7K
0.1U_0402_10V7K
FBC_D[63..32]<27>
D D
FBC_EDC[7..4]<27>
Follow DG
1 2
FBC_CLK1
RV41 40.2_0402_1%RV41 40.2_0402_1%
RV171
FBC_CLK1#
RV171
160_0402_1%
160_0402_1%
@
@
1 2
1 2
RV48 40.2_0402_1%RV48 40.2_0402_1%
1 2
1 2
13
D
D
2
G
G
QV15
QV15
S
S
2N7002W-T/R7_SOT323-3
2N7002W-T/R7_SOT323-3
+1.5VS_VGA
9 SIDE
UV
2
1
CV245
CV245
1
2
1U_0603_25V6
1U_0603_25V6
10U_0603_6.3V6M
10U_0603_6.3V6M
1
2
0.01U_0402_25V7K
0.01U_0402_25V7K
RV218
RV218
931_0402_1%
931_0402_1%
RV219
RV219
931_0402_1%
931_0402_1%
CV99
CV99
1U_0603_25V6
1U_0603_25V6
CV215
CV215
549_0402_1%
549_0402_1%
1.33K_0402_1%
1.33K_0402_1%
549_0402_1%
549_0402_1%
1.33K_0402_1%
1.33K_0402_1%
1
CV100
CV100
2
1U_0603_25V6
1U_0603_25V6
+1.5VS_VGA
RV175
RV175
RV176
RV176
+1.5VS_VGA
RV177
RV177
RV178
RV178
1
CV97
CV97
2
C C
B B
MEM_VREF<23,28,29,30>
A A
FBC_DBI4#<27>
FBC_DBI6#<27>
FBC_CLK1<27>
FBC_CLK1#<27>
FBC_CKE_H<27>
FBC_MA2_BA0_H<27>
FBC_MA5_BA1_H<27>
FBC_MA4_BA2_H<27>
FBC_MA3_BA3_H<27>
FBC_MA7_MA8_H<27>
FBC_MA1_MA9_H<27>
FBC_MA0_MA10_H<27>
FBC_MA6_MA11_H<27>
FBC_MA12_RFU_H<27>
12
RV167
RV167
121_0402_1%
121_0402_1%
FBC_ABI#_H<27>
FBC_RAS#_H<27>
FBC_CS#_H<27>
FBC_CAS#_H<27>
FBC_WE#_H<27>
FBC_WCK2_N<27>
FBC_WCK2<27>
FBC_WCK3_N<27>
FBC_WCK3<27>
FBC_RST#_H<27>
12
+FBC_VREFC1
12
1
CV63
CV63
2
820P_0402_25V7
820P_0402_25V7
12
+FBC_VREFD_H
12
1
1
CV98
CV98
2
2
1U_0603_25V6
1U_0603_25V6
0.1U_0402_10V7K
0.1U_0402_10V7K
CV165
CV165
EDC0 EDC3
C13
EDC1 EDC2
R13
EDC2 EDC1
R2
EDC3 EDC0
D2
DBI0# DBI3#
D13
DBI1# DBI2#
P13
DBI2# DBI1#
P2
DBI3# DBI0#
J12
CK
J11
CK#
J3
CKE#
H11
BA0/A2 BA2/A4
K10
BA1/A5 BA3/A3
K11
BA2/A4 BA0/A2
H10
BA3/A3 BA1/A5
K4
A8/A7 A10/A0
H5
A9/A1 A11/A6
H4
A10/A0 A8/A7
K5
A11/A6 A9/A1
J5
A12/RFU/NC
A5
VPP/NC
U5
VPP/NC
J1
MF
J10
SEN
J13
ZQ
J4
ABI#
G3
RAS# CAS#
G12
CS# WE#
L3
CAS# RAS#
L12
WE# CS#
D5
WCK01# WCK23#
D4
WCK01 WCK23
P5
WCK23# WCK01#
P4
WCK23 WCK01
A10
VREFD
U10
VREFD
J14
VREFC
J2
RESET#
H1
VSS
K1
VSS
B5
VSS
G5
VSS
L5
VSS
T5
VSS
B10
VSS
D10
VSS
G10
VSS
L10
VSS
P10
VSS
T10
VSS
H14
VSS
K14
VSS
G1
VDD
L1
VDD
G4
VDD
L4
VDD
C5
VDD
R5
VDD
C10
VDD
R10
VDD
D11
VDD
G11
VDD
L11
VDD
P11
VDD
G14
VDD
L14
VDD
170-BALL
170-BALL
SGRAM GDDR5
SGRAM GDDR5
X76@
X76@
DQ24 DQ0
DQ25 DQ1
DQ26 DQ2
DQ27 DQ3
DQ28 DQ4
DQ29 DQ5
DQ30 DQ6
DQ31 DQ7
DQ16 DQ8
DQ17 DQ9
DQ18 DQ10
DQ19 DQ11
DQ20 DQ12
DQ21 DQ13
DQ22 DQ14
DQ23 DQ15
DQ8 DQ16
DQ9 DQ17
DQ10 DQ18
DQ11 DQ19
DQ12 DQ20
DQ13 DQ21
DQ14 DQ22
DQ15 DQ23
DQ0 DQ24
DQ1 DQ25
DQ2 DQ26
DQ3 DQ27
DQ4 DQ28
DQ5 DQ29
DQ6 DQ30
DQ7 DQ31
H5GQ1H24AFR-T2L_BGA170
H5GQ1H24AFR-T2L_BGA170
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
A4
FBC_D32
A2
FBC_D33
B4
FBC_D34
B2
FBC_D35
E4
FBC_D36
E2
FBC_D37
F4
FBC_D38
F2
FBC_D39
A11
A13
B11
B13
E11
E13
F11
F13
U11
FBC_D48
U13
FBC_D49
T11
FBC_D50
T13
FBC_D51
N11
FBC_D52
N13
FBC_D53
M11
FBC_D54
M13
FBC_D55
U4
U2
T4
T2
N4
N2
M4
M2
B1
D1
F1
M1
P1
T1
G2
L2
B3
D3
F3
H3
K3
M3
P3
T3
E5
N5
E10
N10
B12
D12
F12
H12
K12
M12
P12
T12
G13
L13
B14
D14
F14
M14
P14
T14
A1
C1
E1
N1
R1
U1
H2
K2
A3
C3
E3
N3
R3
U3
C4
R4
F5
M5
F10
M10
C11
R11
A12
C12
E12
N12
R12
U12
H13
K13
A14
C14
E14
N14
R14
U14
+1.5VS_VGA
+1.5VS_VGA
10U_0603_6.3V6M
10U_0603_6.3V6M
2
1
BY
TE4
BYTE6
UV10 SIDE
CV227
CV227
1U_0603_25V6
1U_0603_25V6
FBC_DBI7#<27>
FBC_DBI5#<27>
+1.5VS_VGA
12
RV168
RV168
121_0402_1%
121_0402_1%
1
1
1
CV103
CV103
2
2
1U_0603_25V6
1U_0603_25V6
1
CV101
CV101
CV104
CV104
CV102
CV102
2
2
1U_0603_25V6
1U_0603_25V6
1U_0603_25V6
1U_0603_25V6
FBC_CLK1
FBC_CLK1#
FBC_MA0_MA10_H
FBC_MA6_MA11_H
FBC_MA7_MA8_H
FBC_MA1_MA9_H
FBC_MA12_RFU_H
1
CV170
CV170
2
0.1U_0402_10V7K
0.1U_0402_10V7K
FBC_EDC7
FBC_EDC5
FBC_DBI7#
FBC_DBI5#
FBC_CKE_H
FBC_MA4_BA2_H
FBC_MA3_BA3_H
FBC_MA2_BA0_H
FBC_MA5_BA1_H
12
RV164
RV164
1K_0402_1%
1K_0402_1%
12
RV166
RV166
1K_0402_1%
1K_0402_1%
FBC_ABI#_H
FBC_CAS#_H
FBC_WE#_H
FBC_RAS#_H
FBC_CS#_H
FBC_WCK3_N
FBC_WCK3
FBC_WCK2_N
FBC_WCK2
+FBC_VREFD_H
+FBC_VREFC1
FBC_RST#_H
+1.5VS_VGA
1
CV168
CV168
2
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
1
CV169
CV169
2
UV10
UV10
MF=0 MF=1 MF=0MF=1
MF=0 MF=1 MF=0MF=1
C2
EDC0 EDC3
C13
EDC1 EDC2
R13
EDC2 EDC1
R2
EDC3 EDC0
D2
DBI0# DBI3#
D13
DBI1# DBI2#
P13
DBI2# DBI1#
P2
DBI3# DBI0#
J12
CK
J11
CK#
J3
CKE#
H11
BA0/A2 BA2/A4
K10
BA1/A5 BA3/A3
K11
BA2/A4 BA0/A2
H10
BA3/A3 BA1/A5
K4
A8/A7 A10/A0
H5
A9/A1 A11/A6
H4
A10/A0 A8/A7
K5
A11/A6 A9/A1
J5
A12/RFU/NC
A5
VPP/NC
U5
VPP/NC
J1
MF
J10
SEN
J13
ZQ
J4
ABI#
G3
RAS# CAS#
G12
CS# WE#
L3
CAS# RAS#
L12
WE# CS#
D5
WCK01# WCK23#
D4
WCK01 WCK23
P5
WCK23# WCK01#
P4
WCK23 WCK01
A10
VREFD
U10
VREFD
J14
VREFC
J2
RESET#
H1
VSS
K1
VSS
B5
VSS
G5
VSS
L5
VSS
T5
VSS
B10
VSS
D10
VSS
G10
VSS
L10
VSS
P10
VSS
T10
VSS
H14
VSS
K14
VSS
G1
VDD
L1
VDD
G4
VDD
L4
VDD
C5
VDD
R5
VDD
C10
VDD
R10
VDD
D11
VDD
G11
VDD
L11
VDD
P11
VDD
G14
VDD
L14
VDD
170-BALL
170-BALL
SGRAM GDDR5
SGRAM GDDR5
X76@
X76@
DQ24 DQ0
DQ25 DQ1
DQ26 DQ2
DQ27 DQ3
DQ28 DQ4
DQ29 DQ5
DQ30 DQ6
DQ31 DQ7
DQ16 DQ8
DQ17 DQ9
DQ18 DQ10
DQ19 DQ11
DQ20 DQ12
DQ21 DQ13
DQ22 DQ14
DQ23 DQ15
DQ8 DQ16
DQ9 DQ17
DQ10 DQ18
DQ11 DQ19
DQ12 DQ20
DQ13 DQ21
DQ14 DQ22
DQ15 DQ23
DQ0 DQ24
DQ1 DQ25
DQ2 DQ26
DQ3 DQ27
DQ4 DQ28
DQ5 DQ29
DQ6 DQ30
DQ7 DQ31
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
H5GQ1H24AFR-T2L_BGA170
H5GQ1H24AFR-T2L_BGA170
A4
FBC_D56
A2
FBC_D57
B4
FBC_D58
B2
FBC_D59
E4
FBC_D60
E2
FBC_D61
F4
FBC_D62
F2
FBC_D63
A11
A13
B11
B13
E11
E13
F11
F13
U11
FBC_D40
U13
FBC_D41
T11
FBC_D42
T13
FBC_D43
N11
FBC_D44
N13
FBC_D45
M11
FBC_D46
M13
FBC_D47
U4
U2
T4
T2
N4
N2
M4
M2
B1
D1
F1
M1
P1
T1
G2
L2
B3
D3
F3
H3
K3
M3
P3
T3
E5
N5
E10
N10
B12
D12
F12
H12
K12
M12
P12
T12
G13
L13
B14
D14
F14
M14
P14
T14
A1
C1
E1
N1
R1
U1
H2
K2
A3
C3
E3
N3
R3
U3
C4
R4
F5
M5
F10
M10
C11
R11
A12
C12
E12
N12
R12
U12
H13
K13
A14
C14
E14
N14
R14
U14
+1.5VS_VGA
BYTE7
BYTE5
GDDR5
Mode H - Mirror Mode Mapping
Address
FBx_CMD0
FBx_CMD1
FBx_CMD2
FBx_CMD3
FBx_CMD4
FBx_CMD5
FBx_CMD6
FBx_CMD7
FBx_CMD8
FBx_CMD9
FBx_CMD10
FBx_CMD11
FBx_CMD12
FBx_CMD13
FBx_CMD14
FBx_CMD15
FBx_CMD16
FBx_CMD17
FBx_CMD18
FBx_CMD19
FBx_CMD20
FBx_CMD21
FBx_CMD22
FBx_CMD23
FBx_CMD24
FBx_CMD25
FBx_CMD26
FBx_CMD27
FBx_CMD28
FBx_CMD29
FBx_CMD30
FBx_CMD31
0..31
CS#
A3_BA3
A2_BA0
A4_BA2
A5_BA1
WE#
A7_A8
A6_A11
ABI#
A12_RFU
A0_A10
A1_A9
RAS#
RST#
CKE#
CAS#
DATA Bus
32..63
CS#
A3_BA3
A2_BA0
A4_BA2
A5_BA1
WE#
A7_A8
A6_A11
ABI#
A12_RFU
A0_A10
A1_A9
RAS#
RS
T#
CKE#
CAS#
Title
Title
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF LC FU TURE CENTER. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF LC FU TURE CENTER. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF LC FU TURE CENTER. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT C ONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT C ONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT C ONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENTER .
MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENTER .
5
4
3
MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENTER .
2012/07/01
2012/07/01
2012/07/01
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2014/07/01
2014/07/01
2014/07/01
Title
N13P_GDDR5_C Upper
N13P_GDDR5_C Upper
N13P_GDDR5_C Upper
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Date: Sheet of
Date: Sheet of
Date: Sheet of
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
1
31 69
31 69
31 69
1.0
1.0
1.0
5
4
3
2
1
follow MXM 3.0 spec
JSLI1
D D
PCIE_CTX_C_GRX_N15
PCIE_CTX_C_GRX_P15
PCIE_CTX_C_GRX_N14
PCIE_CTX_C_GRX_P14
PCIE_CTX_C_GRX_N13
PCIE_CTX_C_GRX_P13
PCIE_CTX_C_GRX_N12
PCIE_CTX_C_GRX_P12
PCIE_CTX_C_GRX_N11
PCIE_CTX_C_GRX_P11
PCIE_CTX_C_GRX_N10
PCIE_CTX_C_GRX_P10
CV200.22U_0402_10V6K CV200.22U_0402_10V6K
CV220.22U_0402_10V6K CV220.22U_0402_10V6K
CV160.22U_0402_10V6K CV160.22U_0402_10V6K
CV180.22U_0402_10V6K CV180.22U_0402_10V6K
CV190.22U_0402_10V6K CV190.22U_0402_10V6K
CV140.22U_0402_10V6K CV140.22U_0402_10V6K
CV150.22U_0402_10V6K CV150.22U_0402_10V6K
CV170.22U_0402_10V6K CV170.22U_0402_10V6K
CV120.22U_0402_10V6K CV120.22U_0402_10V6K
CV130.22U_0402_10V6K CV130.22U_0402_10V6K
CV100.22U_0402_10V6K CV100.22U_0402_10V6K
CV110.22U_0402_10V6K CV110.22U_0402_10V6K
CV80.22U_0402_10V6K CV80.22U_0402_10V6K
CV90.22U_0402_10V6K CV90.22U_0402_10V6K
CV60.22U_0402_10V6K CV60.22U_0402_10V6K
CV70.22U_0402_10V6K CV70.22U_0402_10V6K
PCIE_CTX_C_GRX_N9
PCIE_CTX_C_GRX_P9
PCIE_CTX_C_GRX_N8
PCIE_CTX_C_GRX_P8
PCIE_CRX_C_GTX_N15
PCIE_CRX_C_GTX_P15
PCIE_CRX_C_GTX_N14
PCIE_CRX_C_GTX_P14
PCIE_CRX_C_GTX_N13
PCIE_CRX_C_GTX_P13
PCIE_CRX_C_GTX_N12
PCIE_CRX_C_GTX_P12
PCIE_CRX_C_GTX_N11
PCIE_CRX_C_GTX_P11
PCIE_CRX_C_GTX_N10
PCIE_CRX_C_GTX_P10
PCIE_CRX_C_GTX_N9
PCIE_CRX_C_GTX_P9
PCIE_CRX_C_GTX_N8
PCIE_CRX_C_GTX_P8
C C
PCIE_CRX_GTX_N15
PCIE_CRX_GTX_P15
PCIE_CRX_GTX_N14
PCIE_CRX_GTX_P14
PCIE_CRX_GTX_N13
PCIE_CRX_GTX_P13
PCIE_CRX_GTX_N12
PCIE_CRX_GTX_P12
PCIE_CRX_GTX_N11
PCIE_CRX_GTX_P11
PCIE_CRX_GTX_N10
PCIE_CRX_GTX_P10
PCIE_CRX_GTX_N9
PCIE_CRX_GTX_P9
PCIE_CRX_GTX_N8
PCIE_CRX_GTX_P8
B B
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
JSLI1
1
GND
3
NC
5
NC
7
NC
9
NC
11
NC
13
NC
15
NC
17
GND
19
PEG_RX_N7
21
PEG_RX_P7
23
GND
25
PEG_RX_N6
27
PEG_RX_P6
29
GND
31
GND
33
PEG_RX_N5
35
PEG_RX_P5
37
GND
39
PEG_RX_N4
41
PEG_RX_P4
43
GND
45
PEG_RX_N3
47
PEG_RX_P3
49
GND
51
PEG_RX_N2
53
PEG_RX_P2
55
GND
57
PEG_RX_N1
59
PEG_RX_P1
61
GND
63
PEG_RX_N0
65
PEG_RX_P0
67
GND
69
GND
71
PEG_TX_N7
73
PEG_TX_P7
75
GND
77
PEG_TX_N6
79
PEG_TX_P6
81
GND
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
PEX_STD_SW#
PEG_TX_N5
PEG_TX_P5
GND
PEG_TX_N4
PEG_TX_P4
GND
PEG_TX_N3
PEG_TX_P3
GND
PEG_TX_N2
PEG_TX_P2
GND
PEG_TX_N1
PEG_TX_P1
GND
PEG_TX_N0
PEG_TX_P0
GND
GND
GND
TE_2199022-1_118P-T ME@
TE_2199022-1_118P-T ME@
GND
GND
GND
GND
+19V
+19V
+19V
+19V
+19V
+19V
+19V
+19V
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
TH_TACH
TH_PWN
AC_DC
PWR_GOOD
PWR_EN
CLK_REQ#
RSVD
RSVD
TH_OVERT#
RSVD
SMB_DAT
SMB_CLK
WAKE#
RSVD
RSVD
GND
CLK_PCIE_N
CLK_PCIE_P
GND
GND
GND
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
+5V
40
+5V
42
+5V
44
+5V
46
+5V
48
50
52
54
NC
56
+3V
58
+3V
60
62
NC
64
NC
66
NC
68
NC
70
NC
72
NC
74
76
78
NC
80
82
84
86
88
90
92
94
NC
96
98
NC
100
102
104
106
108
110
112
114
116
118
120
122
B+_SLI
+5VS_SLI
+3VS_SLI +3VS
SLI_B+_ON#
SLI_5V_ON#
SUSP#
SLI_FAN_SPEED
SLI_FAN_PWM
VGA_AC_DET_R
S_DGPU_PWROK
S_DGPU_PWR_EN#
CLK2_REQ_GPU#_R
S_NVDD_PWR_EN
S_DGPU_RST
PCH_THRMTRIP#_R
PLT_RST#
GC6_EVENT_SLI#
EC_SMB_DA2
EC_SMB_CK2
GC6_SLI_EN
S_DGPU_PWR_EN
CLK_PCIE_2VGA#
CLK_PCIE_2VGA
1 2
RV234 0_0402_5%
RV234 0_0402_5%
@
@
SLI_B+_ON# <56>
SLI_5V_ON# <56>
SUSP# <46,55,60,61,62>
SLI_FAN_SPEED <44,46>
SLI_FAN_PWM <44,46>
VGA_AC_DET_R <23>
S_DGPU_PWROK <16,54>
S_DGPU_PWR_EN# <55>
CLK2_REQ_GPU#_R <16>
S_NVDD_PWR_EN <19,54>
S_DGPU_RST <16,54>
PCH_THRMTRIP#_R <19,23>
PLT_RST# <14,23,40,41,46>
EC_SMB_DA2 <17,23,34,36,43,46>
EC_SMB_CK2 <17,23,34,36,43,46>
S_DGPU_PWR_EN <19,54,55>
CLK_PCIE_2VGA# <16>
CLK_PCIE_2VGA <16>
1 2
RV173 0_0402_5%@RV173 0_0402_5%@
SLAVE_PRESENT# <19>
1 2
RV158 0_0402_5%@RV 158 0_0402_5%@
S_GC6_EN <27,54>
S_GC6_EVENT# <54>
11/11 for 2nd VGA fan
need to notic EC
A A
5
PCIE_CTX_C_GRX_N[0..15]<23,5>
PCIE_CTX_C_GRX_P[0..15]<23,5>
PCIE_CRX_GTX_N[0..15]<23,5>
PCIE_CRX_GTX_P[0..15]<23,5>
PCIE_CTX_C_GRX_N[0..15]
PCIE_CTX_C_GRX_P[0..15]
PCIE_CRX_GTX_N[0..15]
PCIE_CRX_GTX_P[0..15]
4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
3
2012/07/01
2012/07/01
2012/07/01
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2014/07/01
2014/07/01
2014/07/01
Title
Title
Title
VGA MXM
VGA MXM
VGA MXM
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Date: Sheet of
Date: Sheet of
Date: Sheet
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
1
32 69
32 69
32 69
of
1.0
1.0
1.0
5
RV93
RV92
RV92
45.3K_0402_ 1%
45.3K_0402_ 1%
D D
STRAP0<24>
STRAP1<24>
STRAP2<24>
STRAP3<24>
STRAP4<24>
C C
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
1 2
RV95
@RV9 5
@
45.3K_0402_ 1%
45.3K_0402_ 1%
1 2
RV93
@
@
4.99K_0402_ 1%
4.99K_0402_ 1%
1 2
RV96
RV96
4.99K_0402_ 1%
4.99K_0402_ 1%
1 2
RV94
RV94
30K_0402_1 %
30K_0402_1 %
GT1@
GT1@
1 2
RV97
RV97
24.9K_0402_ 1%
24.9K_0402_ 1%
GT@
GT@
1 2
+3VS_VGA
4
1 2
1 2
RV121
RV121
4.99K_0402_ 1%
4.99K_0402_ 1%
@
@
RV124
RV124
4.99K_0402_ 1%
4.99K_0402_ 1%
+3VS_VGA
RV122
RV122
20K_0402_1 %
20K_0402_1 %
@
@
1 2
RV125
RV125
45.3K_0402_ 1%
45.3K_0402_ 1%
1 2
3
Physical
Strapping pin
ROM_SCLK
ROM_SI
ROM_SO FB[0]
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
Resistor Values
Power Rail
+3VS_VGA
+3VS_VGA
+3VS_VGA
+3VS_VGA
+3VS_VGA
+3VS_VGA
+3VS_VGA
+3VS_VGA
Pull-up to
+
5K
10K
15K
20K
25K
30K
35K
45K
Logical
Strapping Bit3
PCI_DEVID[4]
FB[1]
PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0]
SOR3_EXPOSED
RESERVED PCIE_SPEED_
3VS_VGA
1000
1001
1010
1011
1100
1101
1110
1111
Pull-down to Gnd
0000
0001
0010
0011
0100
0101
0110
0111
2
Logical
Strapping Bit2
SUB_VENDOR
SER[2] USER[1] USER[0]USER[3]
U
3GIO_PAD_CFG_ADR[2] 3GIO_PAD_CFG_ADR[1]3GIO_PAD_CFG_ADR[3]
SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED
CHANGE_GEN3
Logical
Strapping Bit1
SLOT_CLK_CFG
RAM_CFG[1]RAM_CFG[3] RAM_CFG[2]
3GIO_PAD_CFG_ADR[0]
PCIE_MAX_SPEED DP_PLL_VDD33V
SLOT_CLK_CFG
0
GPU and MCH don't share a common reference clock
1
GPU and MCH share a common reference clock (Default)
SUB_VENDOR
0
No VBIOS ROM (Default)
1
BIOS ROM is present
1
Logical
Strapping Bit0
PEX_PLL_EN_TERM
RAM_CFG[0]
VGA_DEVICESMB_ALT_ADDR
3GIO_PADCFG
RV100
RV99
RV98
RV98
4.99K_0402_ 1%
4.99K_0402_ 1%
@
@
1 2
ROM_SI<24>
ROM_SO<2 4>
ROM_SCLK<2 4>
B B
ROM_SI
ROM_SO
ROM_SCLK
X76
1 2
RV101
RV101
20K_0402_1 %
20K_0402_1 %
X76@
X76@
RV99
10K_0402_1 %
10K_0402_1 %
1 2
RV102
RV102
30K_0402_1 %
30K_0402_1 %
@
@
1 2
RV100
4.99K_0402_ 1%
4.99K_0402_ 1%
@
@
2012-0418 --> Set BOM
1 2
s
tructure as Stuff for ALL SKU
RV103
RV103
RV103
4.99K_0402_ 1%
4.99K_0402_ 1%
GT1@
GT1@
1 2
RV103
GT@
GT@
15K_0402_1%
15K_0402_1%
3GIO_PADCFG[3:0]
0000
PEX_PLL_EN_TERM
0
Disable (Default)
1
Enable
SMBUS_ALT_ADDR
0
0x9E (Default)
1
0x9C (Multi-GPU usage)
Notebook Default
XCLK_417
0
277MHz (Default)
1
R
eserved
PCIE_MAX_SPEED
0
Limit to PCIE Gen1
1
PCIE Gen 2/3 Capable
VGA_DEVICE
0
3D Device (Class Code 302h)
1
VGA Device (Default)
USER Straps
User[3:0]
1000-1100
Customer defined
FB_0_BAR_SIZE
0
Reserved
1
Reserved
2
256MB (Default)
3
Reserved
X76
GPU
Samsung
N13P-GT1
28nm
Hynix
A A
FB Memory (GDDR5)
4G20325FD-FC04 2G 64Mx32
K
K4G10325FG-HC04 1G 32Mx32
H5GQ2H24MFR-T2C 2G 64Mx32
H5GQ1H24BFR-T2C 1G 32Mx32
5GQ2H24AFR-T2C 2G 64Mx32
5
ROM_SI ROM_SO ROM_SCLK STRAP0 STRAP1 STRAP2 STRAP3 STRAP4
PD 30K
PD 15K
(ROM not present)
PD 35K
(ROM present)
PU 45K PD 5K PD 25K PU 5K PD 45K
EOL
PD 45K
PD 25K
PU 10K
PD 20K
PD 25KH
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTI AL
THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTI AL
THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTI AL
AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D
AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D
AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D
DEPARTMENT EXCEPT AS A UTHORIZED BY LC FUTURE CENTER NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS A UTHORIZED BY LC FUTURE CENTER NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS A UTHORIZED BY LC FUTURE CENTER NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF LC FUTURE CENTER.
4
2012/07/01
2012/07/01
2012/07/01
3
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2014/07/01
2014/07/01
2014/07/01
2
VRAM
Samsung
X76
VRAM P/N
X76409JVL01 (2G 64Mx32) SA00005B70J
SA00003RS0JX76409JVL51 (1G 32Mx16)
X76409JVL02 (2G 64Mx32)
SA00004GD0J
EOL
SA00004GD1JHynix X76409JVL02 (2G 64Mx32)
X76409JVL52 (1G 32Mx16) SA00003WL1J
Title
Title
Title
N13P_MISC
N13P_MISC
N13P_MISC
Size Document Nu mber Rev
Size Document Nu mber Rev
Size Document Nu mber Rev
Custom
Custom
Custom
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Date: Sheet of
Date: Sheet of
Date: Sheet of
Wednesday, March 27, 2013
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
1
33 69
33 69
33 69
1.0
1.0
1.0
5
4
3
2
1
+3.3VS_DTL+ 3VS +3.3VS_DTL
12
RT1270 0_0402_5%RT1270 0_0402_5%
D D
CT12 0.1U _0402_10V7KCT12 0.1U_0402_10V7K
12
12
CT11 0.01U _0402_16V7KCT11 0.01U_04 02_16V7K
CT22 0.1U _0402_10V7KCT22 0.1U_0402_10V7K
12
12
CT13 0.01U _0402_16V7KCT13 0.01U_04 02_16V7K
CT8 0.1U_040 2_10V7KCT8 0.1U_0402_10V7K
12
12
C C
B B
CT7 0.1U_040 2_10V7KCT7 0.1U_0402_10V7K
RT2 10K_0402_5%RT2 10K_0402_5%
CT3
CT3
12
1U_0402_6.3V6K
1U_0402_6.3V6K
RT1 10K_0402_5%RT1 10K_0402_5%
CT1
CT1
12
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
EDP_AUX#_C<38>
EDP_AUX_C<38>
EDP_TX0+_C<38>
EDP_TX0-_C<38>
EDP_TX1+_C<38>
EDP_TX1-_C<38>
Power On Configuration
VDDIO_DTL
12
RT6
RT6
RA
4.7K_0402_5%
4.7K_0402_5%
RLV_CFG
12
RT15
RT15
RB
4.7K_0402_5%
4.7K_0402_5%
@
@
Default
A A
mapping selection, internal pull-down ~80K
RLV_CFG
H:6-bit both VESA
*
and JEIDA mapping
M:8-bit JEIDA mapping
L:8-bit VESA mapping
LT4 BLM18PG331SN1D_2PLT4 BLM18PG331SN1D_2P
1
2
1 2
1 2
RA RB
NA
Stuff
Stuff
NA
NANA
1 2
CT5
CT5
0.47U_0402_6.3V6K
0.47U_0402_6.3V6K
VDDRX_DTL
Close Pin6
VDD12_DTL
Close Pin19
VDDIO_DTL
VDDIO_DTL
Close Pin38,50
VDDIO_DTL
DTL_PD#
VDDIO_DTL
DTL_RST#
EDP_AUX#_C
EDP_AUX_C
EDP_TX0+_C
EDP_TX0-_C
EDP_TX1+_C
EDP_TX1-_C
Close to UT3
1
CT6
CT6
1U_0402_6.3V6K
1U_0402_6.3V6K
2
INVT_PWM<35>
Noe:
LVDS output swing control
4.99K for default swing, change the value for
swing adjust
RC RD
Default
*
I2C_ADDR: I2C Slave address selection, internal pull-down ~80KRLV_CFG: LVDS color depth and data
EDP_HPD<38>
CT17 0.1U _0402_10V7KCT17 0.1U_0402_10V7K
12
CT18 0.1U _0402_10V7KCT18 0.1U_0402_10V7K
12
CT19 0.1U _0402_10V7KCT19 0.1U_0402_10V7K
12
CT16 0.1U _0402_10V7KCT16 0.1U_0402_10V7K
12
CT15 0.1U _0402_10V7KCT15 0.1U_0402_10V7K
12
CT14 0.1U _0402_10V7KCT14 0.1U_0402_10V7K
12
VDDIO_DTL
12
RT3
@ RT3
@
4.7K_0402_5%
4.7K_0402_5%
ENPVCC_I2C_ADDR
ENPVCC_I2C_ADDR
H:0x90h~0x9Fh
L:0x10h~0x1Fh
RT14 4.99K_0402_1%RT1 4 4.99K_04 02_1%
12
12
RT9 4.99K_0402_1%RT9 4.99K_0402_1%
EDP_AUX#
EDP_AUX
EDP_TX0+
EDP_TX0-
EDP_TX1+
EDP_TX1-
RC
Stuff
NA
TL_INVPWM
ENPVCC_I2C_ADDR
VDDRX_DTL
VDDIOX_DTL
VDDIOX_DTL
VDD12_DTL
VDDIO_DTL
VDDIO_DTL
EDP_AUX#
EDP_AUX
EDP_TX0+
EDP_TX0-
EDP_TX1+
EDP_TX1-
EDP_HPD
INVT_PWM
DTL_RST#
DTL_PD#
GPIO0
RLV_CFG
EN_BACKLIGHT
REXT
RLV_AMP
SW_OUT
SW_OUT
VDDIO_DTL
12
RT10
DAUL@ RT10
DAUL@
4.7K_0402_5%
4.7K_0402_5%
GPIO0: LVDS single link or dual link selection, internal pull-down ~80K
Default
*
Use BLM18KG331SN1 U
se BLM18KG331SN1 Use BLM18KG331SN1
LT1 BLM18PG331SN1D_2PLT1 BLM18PG331SN1D_2P
1 2
1
CT10
CT10
0.47U_0402_6.3V6K
0.47U_0402_6.3V6K
2
UT3
UT3
6
VDDRX
13
VDDIOX
14
VDDIOX
19
VDD12
38
VDDIO
50
VDDIO
1
DAUXn
2
DAUXp
4
DRX0p
5
DRX0n
7
DRX1p
8
DRX1n
11
HPD
45
PWMI
9
RST#
10
PD#
12
PWMO
33
ENPVCC
21
RLV_LNK/GPIO0
22
RLV_CFG
23
ENBLT
26
REXT
27
RLV_AMP
20
TESTMODE
15
SW_OUT
16
SW_OUT
55
NC
56
NC
PS8625QFN56GTR-A0_QFN56_7X7
PS8625QFN56GTR-A0_QFN56_7X7
GPIO0
GPIO0
Single channel
Daul channel
VDDIOX_DTL SW_OUT VDDRX_DTLVDD 12_DTLVDDIO_DTL
1
CT4
CT4
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
2
Close Pin12,13
TA0p
TA0n
TB0p
PS8625
PS8625
RT1268 0_0402_5%
RT1268 0_0402_5%
RD
NA
Stuff
TB0n
TC0p
TC0n
TCK0p
TCK0n
TD0p
TD0n
TA1p
TA1n
TB1p
TB1n
TC1p
TC1n
TCK1p
TCK1n
TD1p
TD1n
DDC_SDA
DDC_SCL
CSDA/MSDA
CSCL/MSCL
GNDX
GNDX
GND
GND
Epad
EDP@
EDP@
1 2
53
54
51
52
48
49
46
47
43
44
41
42
39
40
36
37
34
35
31
32
30
29
24
25
17
18
28
3
57
LVDS_A0_NVS
LVDS_A0#_NVS
LVDS_A1_NVS
LVDS_A1#_NVS
LVDS_A2_NVS
LVDS_A2#_NVS
LVDS_ACLK_NVS
LVDS_ACLK#_NVS
LVDS_B0_NVS
LVDS_B0#_NVS
LVDS_B1_NVS
LVDS_B1#_NVS
LVDS_B2_NVS
LVDS_B2#_NVS
LVDS_BCLK_NVS
LVDS_BCLK#_NVS
EDID_DAT_CON
EDID_CLK_CON
CSDA/MSDA
CSCL/MSCL
EDP_HPD_CONEDP_HPD
EDP_HPD_CON <35>
EC_SMB_CK2<17,23,32,36,43,46>
EC_SMB_DA2<17,23,32,36,43,46>
Close Pin14
LT2
LT2
1 2
2.2UH_HPC252012F-2R2M_1.3A_20%
2.2UH_HPC252012F-2R2M_1.3A_20%
Use 2.2uH 800mA
GND of 4.7uF capacitor
behind Inductor.
LVDS_A0_NVS <35>
LVDS_A0#_NVS <35>
LVDS_A1_NVS <35>
LVDS_A1#_NVS <35>
LVDS_A2_NVS <35>
LVDS_A2#_NVS <35>
LVDS_ACLK_NVS <35>
LVDS_ACLK#_NVS <35>
LVDS_B0_NVS <35>
LVDS_B0#_NVS <35>
LVDS_B1_NVS <35>
LVDS_B1#_NVS <35>
LVDS_B2_NVS <35>
LVDS_B2#_NVS <35>
LVDS_BCLK_NVS <35>
LVDS_BCLK#_NVS <35>
2K_0402_5%
2K_0402_5%
EC_SMB_CK2
EC_SMB_DA2
LT3 BLM18PG331SN1D_2PLT3 BLM18PG331SN1D_2P
1 2
1
CT2
CT2
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
2
EDP_AUX#_C
EDP_AUX_C
EDP_TX0+_C
EDP_TX0-_C
EDP_TX1+_C
EDP_TX1-_C
+3.3VS_DTL
12
12
RT13
RT12
RT12
RT1272 0_0402_5%RT1272 0_0402_5%
RT1271 0_0402_5%RT1271 0_0402_5%
RT13
2K_0402_5%
2K_0402_5%
EDID_DAT_CON
EDID_CLK_CON
ENPVCC_I2C_ADDR
EN_BACKLIGHT
TL_INVPWM
1 2
1 2
1
CT9
CT9
1U_0402_6.3V6K
1U_0402_6.3V6K
2
CT300.1U_0402_10V7K
CT300.1U_0402_10V7K
1 2
CT310.1U_0402_10V7K
CT310.1U_0402_10V7K
1 2
CT320.1U_0402_10V7K
CT320.1U_0402_10V7K
1 2
CT330.1U_0402_10V7K
CT330.1U_0402_10V7K
1 2
CT340.1U_0402_10V7K
CT340.1U_0402_10V7K
1 2
CT350.1U_0402_10V7K
CT350.1U_0402_10V7K
1 2
EDP@
EDP@
EDP@
EDP@
EDP@
EDP@
EDP@
EDP@
EDP@
EDP@
EDP@
EDP@
EDP_AUX#_CON
EDP_AUX_CON
EDP_TX0+_CON
EDP_TX0-_CON
EDP_TX1+_CON
EDP_TX1-_CON
Close to JLVDS1
EDID_DAT_CON <35>
EDID_CLK_CON <35>
ENPVCC_I2C_ADDR <35>
EN_BACKLIGHT <35>
TL_INVPWM <35>
Initial Code EEPROM
+3.3VS_DTL
RT8 4.7K_0402 _5%@RT8 4.7K_0402_5%@
1 2
RT7 4.7K_0402 _5%@RT7 4.7K_0402_5%@
1 2
GPIO0
CSCL/MSCL
CSDA/MSDA
I2C_CFG = "H"
EPROM for Initial Code
E
I2C Address: 0xA0
Suggest minimum 8Kbit
1.2V
+3.3VS_DTL
8
VCC
7
WP
6
SCL
5
SDA
M24C08-WMN6TP_SO8
M24C08-WMN6TP_SO8
EDP_AUX#_CON <35>
EDP_AUX_CON <35>
EDP_TX0+_CON <35>
EDP_TX0-_CON <35>
EDP_TX1+_CON <35>
EDP_TX1-_CON <35>
To LVDS
panel
CSCL/MSCL
CSDA/MSDA
UT2
@ UT2
@
1
A0
2
A1
3
A2
4
GND
Title
Title
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
3
2012/07/01
2012/07/01
2012/07/01
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2014/07/01
2014/07/01
2014/07/01
Title
LVDS/ CMOS/ USB-ReDriver
LVDS/ CMOS/ USB-ReDriver
LVDS/ CMOS/ USB-ReDriver
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Date: Sheet of
Date: Sheet of
Date: Sheet of
Wednesday, March 27, 2013
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
1
34 69
34 69
34 69
1.0
1.0
1.0
5
EDID_CLK_CON<34>
EDID_DAT_CON<34>
TL_INVPWM<34>
LVDS_BCLK_NVS<34>
LVDS_BCLK#_NVS<34>
LVDS_B2_NVS<34>
LVDS_B2#_NVS<34>
LVDS_B1_NVS<34>
LVDS_B1#_NVS<34>
LVDS_B0_NVS<34>
LVDS_B0#_NVS<34>
LVDS_ACLK_NVS<34>
LVDS_ACLK#_NVS<34>
LVDS_A2_NVS<34>
D D
C C
LVDS_A2#_NVS<34>
LVDS_A1_NVS<34>
LVDS_A1#_NVS<34>
LVDS_A0_NVS<34>
LVDS_A0#_NVS<34>
EDID_CLK_CON
EDID_DAT_CON
LVDS_BCLK_NVS
LVDS_BCLK#_NVS
LVDS_B2_NVS
LVDS_B2#_NVS
LVDS_B1_NVS
LVDS_B1#_NVS
LVDS_B0_NVS
LVDS_B0#_NVS
LVDS_ACLK_NVS
LVDS_ACLK#_NVS
LVDS_A2_NVS
LVDS_A2#_NVS
LVDS_A1_NVS
LVDS_A1#_NVS
LVDS_A0_NVS
LVDS_A0#_NVS
JLVDS1
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
GND141GND2
ACES_87142-4041-BS
ACES_87142-4041-BS
ME@JLVDS1
ME@
2
2
4
4
6
6
8
8
10
10
12
12
14
14
16
16
18
18
20
20
22
22
24
24
26
26
28
28
30
30
32
32
34
34
36
36
38
38
40
40
42
EDP_AUX#_CON
EDP_AUX_CON
EDP_TX0+_CON
EDP_TX0-_CON
EDP_TX1+_CON
EDP_TX1-_CON
W=60mils
4
EDP_HPD_CON
DISPOFF#
+LCDVDD_CON
(60 MIL)
+LEDVDD
EDP_AUX#_CON <34>
EDP_AUX_CON <34>
EDP_TX0+_CON <34>
EDP_TX0-_CON <34>
EDP_TX1+_CON <34>
EDP_TX1-_CON <34>
EDP_HPD_CON <34>
R822 4.7K_0402_5%
R822 4.7K_0402_5%
+3VS
1
C529
C529
@
@
2
680P_0402_50V7K
680P_0402_50V7K
3
@
@
12
12
R8910_0402_5% R8910_0402_5%
12
R8230_0402_5%@R8230_0402_5%
@
BKOFF#
+3VS
BKOFF# <46>
EN_BACKLIGHT <34>
2A 80 mil
1
C523
C523
470P_0603_50V8J
470P_0603_50V8J
9/23 EMI Request
USB20_N0
USB20_N0<18>
USB20_P0<18>
USB20_N0
USB20_P0 USB20_P0_CMOS
R1166 0_0402_5%R1166 0_0402_5%
USB20_P0 USB20_P0_CMOS
R1167 0_0402_5%R1167 0_0402_5%
1 2
1 2
L74
L74
2
2
3
3
WCM-2012-900T_4P
WCM-2012-900T_4P
@
@
2
1
1
4
4
R813
R813
1 2
1
R_short 0_0805_5%
R_short 0_0805_5%
C524
C524
4.7U_0805_25V6-K
4.7U_0805_25V6-K
2
USB20_N0_CMOS
USB20_N0_CMOS
2A 80 mil
2
CMOS Camera
CMOS_ON#<19>
B++LEDVDD
+CMOS_PW
R435
R435
1 2
100K_0402_5%
100K_0402_5%
W=40mils
DMIC_DATA<45>
+3VS
C1051
0.1U_0402_16V4Z
0.1U_0402_16V4Z
CMOS@
CMOS@
+3VS
DMIC_CLK<45>
(40 MIL)
@C1051
@
1
C520
C520
0.1U_0402_16V4Z
0.1U_0402_16V4Z
CMOS@
CMOS@
2
C58
C58
@
@
12
0.047U_0402_16V4Z
0.047U_0402_16V4Z
USB20_N0_CMOS
USB20_P0_CMOS
Q94 AO3413_SOT23-3
Q94 AO3413_SOT23-3
D
S
D
S
13
CMOS@
CMOS@
G
G
2
1
C1052
0.01U_0402_16V7K
0.01U_0402_16V7K
2
1
2
3
4
5
6
7
8
9
10
+CMOS_PW_R
1
@C1052
@
2
JCMOS1
JCMOS1
1
2
3
4
5
6
7
8
GND
GND
ME@
ME@
1
R432
R432
0_0603_5%
0_0603_5%
1 2
1
CMOS@
CMOS@
C518
C518
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
CMOS@
CMOS@
+CMOS_PW
W=40mils
C519
10U_0603_6.3V6M@C519
10U_0603_6.3V6M
1
@
2
LCDVDD
eDP to LVDS
ENPVCC_I2C_ADDR<34>
1 2
R1198 0_0402_5%
VGA_ENVDD<23>
GPU
PCH_ENVDD<14>
PCH
B B
R1515
R1515
D60
D60
2
1
3
DAN202UT106_SC70-3
DAN202UT106_SC70-3
1 2
@
@
0_0402_5%
0_0402_5%
INVT_PWM
R829
R829
100K_0402_5%
100K_0402_5%
1 2
INVT_PWM <34>
TL_INVPWM
1 2
R826
VGA_BL_PWM<23>
PCH_EDP_PWM<14>
R826
R1197
R1197
0_0402_5%
0_0402_5%
1 2
0_0402_5%
0_0402_5%
EMI request E
1 2
R834
VGA_ENBKL<23>
A A
PCH_ENBKL<14>
5
R834
0_0402_5%
0_0402_5%
1 2
R1212 0_0402_5%R1212 0_0402_5%
LVDS LOAD SWITCH
1.9mS Typical Rise time ,Rds_on 80m ohm
D62
D62
2
1
3
DAN202UT106_SC70-3
DAN202UT106_SC70-3
ENBKL
ENBKL <46>
R827
R827
100K_0402_5%
100K_0402_5%
1 2
4
DMIC_CLK TL_INVPWM
1
C934
C934
2
100P_0402_50V8J
100P_0402_50V8J
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
3
2012/07/01
2012/07/01
2012/07/01
R1198 0_0402_5%
@
@
1 2
R1196 0_0402_5%
R1196 0_0402_5%
@
@
DISPOFF#
C525
C525
@
@
@
@
1
1
C527
C527
2
2
470P_0402_50V7K
470P_0402_50V7K
470P_0402_50V7K
470P_0402_50V7K
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
+3VS +LCDVDD_CON
1U_0402_6.3V6K
1U_0402_6.3V6K
1
C291
C291
2
1 2
R1202 0_0402_5%R1202 0_0402_5%
D61
@D61
@
2
1
3
DAN202UT106_SC70-3
DAN202UT106_SC70-3
U76
U76
5
IN
4
DIS
NCT3521U
NCT3521U
VOUT
1
2
GND
3
R818
R828
R828
100K_0402_5%
100K_0402_5%
1 2
R818
EN
SD request
USB20_P0_CMOS
+3VS
2014/07/01
2014/07/01
2014/07/01
USB20_N0_CMOS
Title
Title
Title
LVDS/ CMOS/ USB-ReDriver
LVDS/ CMOS/ USB-ReDriver
LVDS/ CMOS/ USB-ReDriver
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
AZC099-04S.R7G_SOT23-6
AZC099-04S.R7G_SOT23-6
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Wednesday, March 27, 2013
150_0603_1%
150_0603_1%
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
1
CV283
CV283
2
D59
@D59
@
4
I/O3
I/O1
5
VDD
GND
6
I/O4
I/O2
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
1
1
DMIC_DATA
2
3
DMIC_CLK
35 69
35 69
35 69
1.0
1.0
1.0
A
B
C
D
E
CRT Connector
D36
D36
2 1
RB491D_ SC59-3
RB491D_ SC59-3
+CRT_VC C
F1
F1
0.5A_8V_ KMC3S050RY
0.5A_8V_ KMC3S050RY
W=40mils
CRT_DET #
1
2
CRT_DDC _CLK_CON
+CRT_VC C_CON
21
C543
C543
100P_04 02_50V8J
100P_04 02_50V8J
CRT_R_C ON CRT_G_C ON
VSYNC_CON
+CRT_VC C_CON
1
C536
C536
0.1U_040 2_16V4Z
0.1U_040 2_16V4Z
2
JCRT1
JCRT1
6
11
1
7
12
2
8
13
3
9
14
4
10
15
3
2
1
AZC099-0 4S.R7G_SOT23-6
AZC099-0 4S.R7G_SOT23-6
3
2
1
16
G
G
17
G
G
5
SUYIN_070546 HR015M22BZR
SUYIN_070546 HR015M22BZR
ME@
ME@
D7
@D 7
@
I/O2
GND
I/O1
D31
I/O2
GND
I/O1
AZC099-0 4S.R7G_SOT23-6
AZC099-0 4S.R7G_SOT23-6
I/O4
VDD
I/O3
@D 31
@
I/O4
VDD
I/O3
6
5
4
CRT_B_C ONCRT_DET #
6
HSYNC_CON
5
4
CRT_DDC _DAT_CON
+CRT_VC C_CON
+CRT_VC C_CON
+5VS
1 1
CRT_DET #<14>
1 2
F
rom CRT SW
2 2
3 3
CRT_DDC _DATA_R<37 >
From SW
4 4
CRT_DDC _CLK_R<37>
EC_SMB_ DA2<1 7,23,32,34,43,46>
EC_SMB_ CK2<1 7,23,32,34,43,46>
DAC_RED _1<37>
DAC_GRN _1<37 >
DAC_BLU _1<37 >
From CRT SW
12
R830
R830
150_040 2_1%
150_040 2_1%
CLOSE TO CONN
0.1U_040 2_16V4Z
0.1U_040 2_16V4Z
HSYNC_G<37>
0.1U_040 2_16V4Z
0.1U_040 2_16V4Z
VSYNC_G<37>
CRT_DDC _DATA_R DDC_DAT _R
CRT_DDC _CLK_R
EC_SMB_ DA2
EC_SMB_ CK2
1 2
R1189 0_ 0402_5%R 1189 0_0402_5 %
1 2
R1190 0_ 0402_5%R 1190 0_0402_5 %
1 2
R1191 0_ 0402_5%
R1191 0_ 0402_5%
@
@
1 2
R1192 0_ 0402_5%
R1192 0_ 0402_5%
@
@
DDC_CLK _R
R831
R831
150_040 2_1%
150_040 2_1%
C544
C544
C546
C546
+3VS
G
G
2
S
S
Q73A
Q73A
12
R832
R832
150_040 2_1%
150_040 2_1%
1
2
1
2
S
S
61
D
D
12
2N7002K DWH_SOT36 3-6
2N7002K DWH_SOT36 3-6
1
C537
C537
2
10P_040 2_50V8J
10P_040 2_50V8J
+CRT_VC C
R833
R833
1 2
1K_0402 _5%
1K_0402 _5%
OE#
5
1
P
4
CRT_HSYNC _1
OE#
A2Y
G
U24
U24
SN74AHC T1G125DCKR_S C70-5
SN74AHC T1G125DCKR_S C70-5
3
+CRT_VC C
OE#
5
1
P
4
CRT_VSYNC _1
OE#
A2Y
G
U25
U25
SN74AHC T1G125DCKR_S C70-5
SN74AHC T1G125DCKR_S C70-5
3
+CRT_VC C
G
G
5
Q73B
Q73B
2N7002K DWH_SOT36 3-6
2N7002K DWH_SOT36 3-6
12
R837
R837
34
2.2K_0402_5%
2.2K_0402_5%
D
D
C548
C548
100P_04 02_50V8J
100P_04 02_50V8J
L16 NBQ1005 05T-800Y_0402L1 6 NBQ1005 05T-800Y_0402
1 2
L17 NBQ1005 05T-800Y_0402L1 7 NBQ1005 05T-800Y_0402
1 2
L18 NBQ1005 05T-800Y_0402L1 8 NBQ1005 05T-800Y_0402
1
1
C539
C539
C538
C538
10P_040 2_50V8J
10P_040 2_50V8J
2
2
10P_040 2_50V8J
10P_040 2_50V8J
R840
R840
1 2
33_0603 _5%
33_0603 _5%
R839
R839
1 2
33_0603 _5%
33_0603 _5%
12
R838
R838
2.2K_040 2_5%
2.2K_040 2_5%
CRT_DDC _DAT_CON
CRT_DDC _CLK_CON
1
1
@
@
@
@
C549
C549
68P_040 2_50V8K
68P_040 2_50V8K
2
2
1
2
10P_040 2_50V8J
10P_040 2_50V8J
CRT_HSYNC _2
CRT_VSYNC _2
1
C542
C542
C540
C540
2
10P_040 2_50V8J
10P_040 2_50V8J
NBQ1005 05T-800Y_0402
NBQ1005 05T-800Y_0402
1 2
L19
L19
NBQ1005 05T-800Y_0402
NBQ1005 05T-800Y_0402
1 2
L20
L20
1
C541
C541
10P_040 2_50V8J
10P_040 2_50V8J
2
CRT_R_C ON
CRT_DDC _DAT_CON
CRT_G_C ON
CRT_B_C ON
1
@
@
C545
C545
10P_040 2_50V8J
10P_040 2_50V8J
2
1
C547
@C 547
@
10P_040 2_50V8J
10P_040 2_50V8J
2
HSYNC_CON
VSYNC_CON
CRT_DDC _CLK_CON
HSYNC_CON
VSYNC_CON
Title
Title
Security Class ification
Security Class ification
Security Class ification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
A
B
2012/07/ 01
2012/07/ 01
2012/07/ 01
C
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2014/07/ 01
2014/07/ 01
2014/07/ 01
D
Title
CRT Connector
CRT Connector
CRT Connector
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
E
36 69
36 69
36 69
1.0
1.0
1.0
2
1
+3VS +3VS_HDSW +3VS_HDSW +3VS_HDSW +3VS_HDSW
0_0402_5%
0_0402_5%12CM2 4.7U_0603_6.3V6KCM2 4.7U_0603_6.3V6K
RM25
RM25
VDD
VDD
+3VS_HDSW
6
31
25
28
40
34
7
36
VGA_HDMI_TX0-
35
VGA_HDMI_TX0+
33
VGA_HDMI_TX1-
32
VGA_HDMI_TX1+
30
VGA_HDMI_TX2-
29
VGA_HDMI_TX2+
27
VGA_HDMI_CLK-
26
VGA_HDMI_CLK+
39
HDMI_CONN_HPD
38
VGA_HDMI_CLK
37
VGA_HDMI_DATA
PWDN_ASQ
CFG_HPD
DDC_BUF
PRE_EMI
UHM1
UHM1
1 2
CPU_HDMI_TX0-<8>
CPU_HDMI_TX0+<8>
CPU_HDMI_TX1-<8>
CPU_HDMI_TX1+<8>
CPU_HDMI_TX2-<8>
CPU_HDMI_TX2+<8>
CPU_HDMI_CLK-<8>
CPU_HDMI_CLK+<8>
B B
GPU_HDMI_TX0-<24>
GPU_HDMI_TX0+<24>
GPU_HDMI_TX1-<24>
GPU_HDMI_TX1+<24>
GPU_HDMI_TX2-<24>
GPU_HDMI_TX2+<24>
GPU_HDMI_CLK-<24>
GPU_HDMI_CLK+<24>
+3VS_HDSW
SW
A A
_DDC IN1---CPU
SW
CM4 0.1U_0402_10V6KCM 4 0.1U_0402_10V6K
1 2
CM5 0.1U_0402_10V6KCM 5 0.1U_0402_10V6K
1 2
CM6 0.1U_0402_10V6KCM 6 0.1U_0402_10V6K
1 2
CM7 0.1U_0402_10V6KCM 7 0.1U_0402_10V6K
1 2
CM8 0.1U_0402_10V6KCM 8 0.1U_0402_10V6K
1 2
CM9 0.1U_0402_10V6KCM 9 0.1U_0402_10V6K
1 2
CM10 0.1U _0402_10V6KCM10 0.1U_040 2_10V6K
1 2
CM11 0.1U _0402_10V6KCM11 0.1U_040 2_10V6K
1 2
CM12 0.1U_0402_10V6KCM12 0.1U_0402_10V6K
1 2
CM13 0.1U_0402_10V6KCM13 0.1U_0402_10V6K
1 2
CM14 0.1U_0402_10V6KCM14 0.1U_0402_10V6K
1 2
CM15 0.1U_0402_10V6KCM15 0.1U_0402_10V6K
1 2
CM16 0.1U_0402_10V6KCM16 0.1U_0402_10V6K
1 2
CM17 0.1U_0402_10V6KCM17 0.1U_0402_10V6K
1 2
CM18 0.1U_0402_10V6KCM18 0.1U_0402_10V6K
1 2
CM19 0.1U_0402_10V6KCM19 0.1U_0402_10V6K
TMDS_B_HPD<14>
DGPU_HDMI_HPD<23,39>
DDPB_CLK<14>
DDPB_DATA<14>
GPU_HDMI_CLK<24>
GPU_HDMI_DATA<24>
HDSW_DDC<19>
HDSW_MAIN<19>
CM1
CM1
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
RM27 4.7K_0402_5%R M27 4.7K_0402_5%
1 2
RM28 4.7K_0402_5%R M28 4.7K_0402_5%
1 2
RM29 2.2K_0402_5%R M29 2.2K_0402_5%
1 2
RM30 2.2K_0402_5%R M30 2.2K_0402_5%
1 2
Input Output
HDSW_DDC
HDSW_MAIN
DDPB_CLK
DDPB_DATA
IN2---GPU
SW_MAIN
IN1---CPU
IN2---GPU
CPU_HDMI_TX0-_C
CPU_HDMI_TX0+_C
CPU_HDMI_TX1-_C
CPU_HDMI_TX1+_C
CPU_HDMI_TX2-_C
CPU_HDMI_TX2+_C
CPU_HDMI_CLK-_C
CPU_HDMI_CLK+_C
GPU_HDMI_TX0-_C
GPU_HDMI_TX0+_C
GPU_HDMI_TX1-_C
GPU_HDMI_TX1+_C
GPU_HDMI_TX2-_C
GPU_HDMI_TX2+_C
GPU_HDMI_CLK-_C
GPU_HDMI_CLK+_C
DDPB_CLK
DDPB_DATA
HDSW_DDC
HDSW_MAIN
IN1_PEQ
IN2_PEQ
1
RM26
RM26
430_0402_1%
430_0402_1%
2
HDSW_MAIN HDSW_DDC
For PS8271: R35/R36 NC
For PS8272: R35/R36 NC, pin21/pin22 NC or SW_MAIN/SW_DDC driven to LOW
For PS8273: R35/R36 stuff or SW_MAIN/SW_DDC driven to HIGH
L=IN1
H=IN2
L=IN1
H=IN2
12
44
IN1_D1n
45
IN1_D1p
47
IN1_D2n
48
IN1_D2p
1
IN1_D3n
2
IN1_D3p
4
IN1_D4n
5
IN1_D4p
8
IN2_D1n
9
IN2_D1p
11
IN2_D2n
12
IN2_D2p
13
IN2_D3n
14
IN2_D3p
16
IN2_D4n
17
IN2_D4p
46
IN1_HPD
10
IN2_HPD
41
IN1_SCL
42
IN1_SDA
19
IN2_SCL
20
IN2_SDA
22
SW_DDC
21
SW_MAIN
3
IN1_PEQ
15
IN2_PEQ
23
CEXT
24
REXT
18
GND
43
GND
49
PAD
PS8271QFN48GTR-A1_QFN48_7X7
PS8271QFN48GTR-A1_QFN48_7X7
1 2
RM33 0_0402_5%RM33 0_0402_5%
PWDN_ASQ
CFG_HPD
DDCBUF
PRE_EMI
RTERM
OUT_D1n
OUT_D1p
OUT_D2n
OUT_D2p
OUT_D3n
OUT_D3p
OUT_D4n
OUT_D4p
OUT_HPD
OUT_SCL
OUT_SDA
Channel A --> GPU
Channel B --> PCH
1 2
CM3 0.01U_0402_16V7KCM3 0.01U_0402_16V7K
1 2
VGA_HDMI_TX0- <3 9>
VGA_HDMI_TX0+ <39>
VGA_HDMI_TX1- <3 9>
VGA_HDMI_TX1+ <39>
VGA_HDMI_TX2- <3 9>
VGA_HDMI_TX2+ <39>
VGA_HDMI_CLK- <39>
VGA_HDMI_CLK+ <39>
HDMI_CONN_HPD <39>
VGA_HDMI_CLK <3 9>
VGA_HDMI_DATA <39>
VGA_CRT_R<23>
VGA_CRT_G<23>
VGA_CRT_B<23>
VGA_CRT_CLK<23>
VGA_CRT_DATA<23>
VGA_CRT_HSYNC<23>
VGA_CRT_VSYNC<23>
PCH_CRT_R<14>
PCH_CRT_G<14>
PCH_CRT_B<14>
PCH_CRT_DDC_CLK<14>
PCH_CRT_DDC_DAT<14>
PCH_CRT_HSYNC<14>
PCH_CRT_VSYNC<14>
SEL
*
DDCBUF DDC_BUF_EN = L: No DDC active
buffer, passive DDC level shifting
SEL
*
PRE_EMI: TMDS output drive pre-emphasis and
EMI setting, Internal pull-down ~500K ohm
+3VS
12
1U_0603_10V6K
1U_0603_10V6K
1
2
Input SELx
RA RB
RM14
@RM14
VDD
VDD
VDD
VDD
VDD
0B1
1B1
2B1
3B1
4B1
5B1
6B1
0B2
1B2
2B2
3B2
4B2
5B2
6B2
@RM19
@
1 2
4.7K_0402_5%
4.7K_0402_5%
RA RB
Stuff
NA
RM20
1 2
4.7K_0402_5%
4.7K_0402_5%
Stuff
UM1
UM1
A0
A1
A2
A3
A4
SEL1
A5
A6
SEL2
GND
GND
GND
GND
GPAD
@
NA
Stuff
NANA
@RM20
@
RG RH
Stuff
NA
1
2
5
6
7
8
9
10
30
3
11
28
31
33
NA
NANA
CRT_SWITCH_1
CRT_SWITCH_1
Function
RM13
@RM13
@
1 2
4.7K_0402_5%
4.7K_0402_5%
DDC_BUF IN1_PEQ IN2_PEQ
DDC_BUF
H:Active DDC buffer
enable, setting 1
M:Active DDC buffer
enable, setting 2
L: No DDC active
buffer, passive
DDC level shifting
+3VS_HDSW +3VS_HDSW
CM1183
CM1183
RG RH RI RJ
RM19
1 2
4.7K_0402_5%
4.7K_0402_5%
PRE_EMI CFG_HPD
PRE_EMI
H: Pre-emphasis
added, no EMI control
M: No pre-emphasis,
EMI control selected
L: No pre-emphasis,
no EMI control
RM1
RM1
0_0402_5%
0_0402_5%
4
16
23
29
32
27
25
22
20
18
12
14
26
24
21
19
17
13
15
PI3V712-AZLEX_TQFN32_6X3
PI3V712-AZLEX_TQFN32_6X3
Input/Output An
RC RD RFRE
RM15
@RM15
@
RM16
@RM16
1 2
4.7K_0402_5%
4.7K_0402_5%
DAC_RED_1 <36>
DAC_GRN_1 <36>
DAC_BLU_1 <3 6>
CRT_DDC_CLK_R < 36>
CRT_DDC_DATA_R <36>
HSYNC_G <36>
VSYNC_G <36>
@
1 2
4.7K_0402_5%
4.7K_0402_5%
SEL
IN1_PEQ/IN2_PEQ
H: High level receiving
equalization selection
M: Low level receiving
equalization selection
L: Middle level
receiving equalization
*
selection
IN1_PEQ/IN2_PEQ: Rx Equalization Setting for
port1/port2.Internal pull-down ~500K ohm
RM21
1 2
4.7K_0402_5%
4.7K_0402_5%
SEL
CFG_HPD
H: IN1_HPD=OUT_HPD SW_DDC=L/
IN2_HPD=OUT_HPD SW_DDC=H
IN1_HPD=LOW otherwise /
IN2_HPD=LOW otherwise
M: IN1_HPD=OUT_HPD when SW_DDC=L or SW_MAIN=L /
IN2_HPD=OUT_HPD when SW_DDC=H or SW_MAIN=H
IN1_HPD=LOW otherwise / IN2_HPD=LOW otherwise
L: IN1_HPD=OUT_HPD when SW_MAIN=L /
IN2_HPD=OUT_HPD when SW_MAIN=H
IN1_HPD=LOW otherwise /
*
IN2_HPD=LOW otherwise
CFG_HPD: HPD switching configuration.
Internal pull-down ~500K
+3VS_HDSW
RM18
@RM18
@
RM17
@RM17
4.7K_0402_5%
4.7K_0402_5%
@RM21
@
1 2
Stuff
NA
Stuff
NA NA
RM22
1 2
4.7K_0402_5%
4.7K_0402_5%
RDRC
NA
@RM22
@
1 2
4.7K_0402_5%
4.7K_0402_5%
Stuff
NA
Stuff
@
RFRE
NA
NANA
Stuff
NA
NA NA
RK RL
RM23
@RM23
@
RM24
@RM24
1 2
4.7K_0402_5%
4.7K_0402_5%
PWDN_ASQ
SEL*PWDN_ASQ
H: power down
L: Normal operation
PWDN_ASQ: Power down control. Internal pull-down
~500K
CRT_SWITCH_1 <13>
1 2
4.7K_0402_5%
4.7K_0402_5%
@
Stuff
NA NA
For reserved CRT SW
RJRI
NA
Stuff
RHRG
NA
L
H An=nB2
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
2012/07/01
2012/07/01
2012/07/01
nB1--GPU
nB2---PCH
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
An=nB1
2014/07/01
2014/07/01
2014/07/01
Title
Title
Title
HDMI and CRT SW
HDMI and CRT SW
HDMI and CRT SW
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Date: Sheet of
Date: Sheet of
1
Date: Sheet of
Wednesday, March 27, 2013
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
37 69
37 69
37 69
1.0
1.0
1.0
5
D D
C C
4
CPU_EDP_TX0+<8>
CPU_EDP_TX0-<8>
CPU_EDP_TX1+<8>
CPU_EDP_TX1-<8>
CPU_EDP_AUX<8>
CPU_EDP_AUX#<8>
CPU_EDP_HPD<8>
VGA_EDP_TX0+<24>
VGA_EDP_TX0-<24>
VGA_EDP_TX1+<24>
VGA_EDP_TX1-<24>
VGA_EDP_AUX<24>
VGA_EDP_AUX#<24>
VGA_EDP_HPD<23>
CPU_EDP_TX0+
CPU_EDP_TX0CPU_EDP_TX1+
CPU_EDP_TX1-
CPU_EDP_AUX
CPU_EDP_AUX#
3
U79
31
30
27
26
19
18
17
25
24
23
22
15
14
13
21
28
33
U79
VDD
D0+A
VDD
D0-A
VDD
D1+A
VDD
D1-A
VDD
VDD
AUX+A
AUX-A
HPD_A
D0+
D0+B
D0-B
D1+B
D1-B
AUX+B
AUX-B
HPD_B
GND
GND
GPAD
PI3VDP3212ZLEX_TQFN32_6X3
PI3VDP3212ZLEX_TQFN32_6X3
D1+
AUX+
AUX-
HPD
SEL
OE#
AUX_SEL
D0-
D1-
2
+3VS
12
RM2
RM2
0_0402_5%
0_0402_5%
1U_0603_10V6K
1U_0603_10V6K
3
9
12
16
20
29
1
2
4
5
6
7
8
10
11
32
CM1184
CM1184
1
2
EDP_TX0+_C <34>
EDP_TX0-_C < 34>
EDP_TX1+_C <34>
EDP_TX1-_C < 34>
EDP_AUX_C <34>
EDP_AUX#_C <34>
EDP_HPD <3 4>
EDP_SEL <15>
EDP_AUX_SEL <16>
1
OE# SEL AUX_SEL FUNCTION
L L L PORT A
L L H PORT A-HS, PORT B-HPD/AUX
L H L PORT B-HS, PORT A-HPD/AUX
LHH
B B
A A
5
4
X
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
3
H
X
2012/07/01
2012/07/01
2012/07/01
PORT B
IC POWER DOWN
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2014/07/01
2014/07/01
2014/07/01
Title
Title
Title
LVDS/ CMOS/ USB-ReDriver
LVDS/ CMOS/ USB-ReDriver
LVDS/ CMOS/ USB-ReDriver
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Date: Sheet of
Date: Sheet of
Date: Sheet of
Wednesday, March 27, 2013
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
1
38 69
38 69
38 69
1.0
1.0
1.0
5
WCM2 012F2SF-900T0 4_4P
WCM2 012F2SF-900T0 4_4P
HDMI_CLK+ _R
HDMI_CLK-_ R
HDMI_TX0+ _R
D D
C C
B B
A A
HDMI_TX0-_ R
HDMI_TX1+ _R
HDMI_TX1-_ R
HDMI_TX2+ _R
HDMI_TX2-_ R
HDMI_CLK+ _CON
HDMI_CLK-_ CON
HDMI_TX0+ _CON
HDMI_TX0-_ CON
HDMI_TX1+ _CON
HDMI_TX1-_ CON
HDMI_TX2+ _CON
HDMI_TX2-_ CON
4
4
1
1
L23
L23
L24
L24
1
1
4
4
WCM2 012F2SF-900T0 4_4P
WCM2 012F2SF-900T0 4_4P
WCM2 012F2SF-900T0 4_4P
WCM2 012F2SF-900T0 4_4P
4
4
1
1
L26
L26
L27
L27
1
1
4
4
WCM2 012F2SF-900T0 4_4P
WCM2 012F2SF-900T0 4_4P
3
2
2
3
3
2
2
3
+3VS
VGA_HDM I_CLK
VGA_HDM I_DATA
3
HDMI_CLK+ _CON
2
HDMI_CLK-_ CON
2
HDMI_TX0+ _CON
3
HDMI_TX0-_ CON
3
HDMI_TX1+ _CON
2
HDMI_TX1-_ CON
2
HDMI_TX2+ _CON
3
HDMI_TX2-_ CON
499_040 2_1%
499_040 2_1%
1 2
1 2
R321 4 99_0402_1%
R321 4 99_0402_1%
1 2
R322 499_040 2_1%
R322 499_040 2_1%
1 2
R323 499_040 2_1%@R323 499_0402_1%@
1 2
R324 499_04 02_1%@R324 499_ 0402_1%@
1 2
R325 499_040 2_1%@R325 499_0402_1%@
1 2
R326 499_040 2_1%@R326 499_04 02_1%@
1 2
R327 499_040 2_1%@R327 499_0402_1%@
1 2
@
@
R328 100K_0 402_5%
R328 100K_0 402_5%
1 2
C1016 3.3P_040 2_50V8C
C1016 3.3P_040 2_50V8C
@
@
1 2
C1015 3.3P_040 2_50V8C
C1015 3.3P_040 2_50V8C
@
@
1 2
C1018 3.3P_040 2_50V8C
C1018 3.3P_040 2_50V8C
@
@
1 2
C1017 3.3P_040 2_50V8C
C1017 3.3P_040 2_50V8C
@
@
1 2
C1020 3.3P_040 2_50V8C
C1020 3.3P_040 2_50V8C
@
@
1 2
C1019 3.3P_040 2_50V8C
C1019 3.3P_040 2_50V8C
@
@
1 2
C1022 3.3P_040 2_50V8C
C1022 3.3P_040 2_50V8C
@
@
1 2
C1021 3.3P_040 2_50V8C
C1021 3.3P_040 2_50V8C
@
@
20120829 VA1
Change net name for add HDMI MUX
R320
R320
@
@
@
@
@
@
13
D
D
2
G
G
2N7002H 1N_SOT23-3
2N7002H 1N_SOT23-3
S
S
@
@
D57
3
I/O2
2
GND
1
I/O1
AZC099-0 4S.R7G_SOT23-6
AZC099-0 4S.R7G_SOT23-6
I/O4
VDD
I/O3
Q114
Q114
@D57
@
HDMI_CONN _HPD<37>
6
5
4
4
DGPU_HD MI_HPD<23,37>
HDMI_DET
+5VS_HD MI
1 2
R1486
R1486
0_0402_ 5%
0_0402_ 5%
@
@
R862
R862
1M_0402 _5%
1M_0402 _5%
R1499
R1499
0_0402_ 5%
0_0402_ 5%
1 2
R859
R859
12
R864
R864
@
@
100K_0402_5%
100K_0402_5%
1 2
@
@
1K_0402 _5%
1K_0402 _5%
VGA_HDM I_CLK-<37>
VGA_HDM I_CLK+<37>
VGA_HDM I_TX0-<37>
VGA_HDM I_TX0+<37>
VGA_HDM I_TX1-<37>
VGA_HDM I_TX1+<37>
VGA_HDM I_TX2-<37>
VGA_HDM I_TX2+<37>
HDMI_CLK+ _CON
HDMI_CLK-_ CON
HDMI_TX0-_ CON
HDMI_TX0+ _CON
+3VS
G
G
2
Q85
Q85
13
D
S
D
S
2N7002_ SOT23
2N7002_ SOT23
for NV recommend
12
HDMI_DET_ R
VGA_HDM I_CLK+ HDMI_CLK+_R
VGA_HDM I_TX0-
VGA_HDM I_TX0+
VGA_HDM I_TX1-
VGA_HDM I_TX1+
VGA_HDM I_TX2-
VGA_HDM I_TX2+
D32
D32
1
1
1
2
2
2
4
4
4
5
3
3
3
8
8
AZ1045-0 4F_DFN2510P1 0E-10-9
AZ1045-0 4F_DFN2510P1 0E-10-9
3
VGA_HDM I_CLK<37>
VGA_HDM I_DATA<37>
R885
R885
20K_040 2_5%
20K_040 2_5%
1 2
L67
L67
BLM18PG 181SN1D_0603
BLM18PG 181SN1D_0603
@
@
@
@
9
HDMI_CLK+ _CON
10
10
8
HDMI_CLK-_ CON
9
9
7
HDMI_TX0-_ CON
7
7
6
HDMI_TX0+ _CON
65
65
VGA_HDM I_CLK
VGA_HDM I_DATA
+5VS
3
12
1
@
@
C59
C59
220P_04 02_25V8J
220P_04 02_25V8J
2
1 2
R300 0_04 02_5%R 300 0_ 0402_5%
1 2
R301 0_04 02_5%R 301 0_ 0402_5%
1 2
R302 0_04 02_5%R 302 0_ 0402_5%
1 2
R303 0_0402_5%R303 0_0402_ 5%
1 2
R304 0_04 02_5%R 304 0_ 0402_5%
1 2
R305 0_04 02_5%R 305 0_ 0402_5%
1 2
R306 0_04 02_5%R 306 0_ 0402_5%
1 2
R307 0_04 02_5%R 307 0_ 0402_5%
Close to JHDMI1
HDMI_TX2-_ CON
HDMI_TX2+ _CON
HDMI_TX1+ _CON
HDMI_TX1-_ CON
2
@
@
1
D38
D38
BAT54S-7 -F_SOT23-3
BAT54S-7 -F_SOT23-3
+CRT_VC C_CON
HDMI_DET
HDMI_CLK-_ RVGA_H DMI_CLK-
HDMI_TX0-_ R
HDMI_TX0+ _R
HDMI_TX1-_ R
HDMI_TX1+ _R
HDMI_TX2-_ R
HDMI_TX2+ _R
AZ1045-0 4F_DFN2510P1 0E-10-9
AZ1045-0 4F_DFN2510P1 0E-10-9
2
2200P_0 402_50V7K
2200P_0 402_50V7K
R866 0_04 02_5%@R866 0_0402 _5%@
R865 0_04 02_5%@R865 0_0402 _5%@
R868 0_04 02_5%@R868 0_0402 _5%@
R867 0_04 02_5%@R867 0_0402 _5%@
R870 0_04 02_5%@R870 0_0402 _5%@
R869 0_04 02_5%@R869 0_0402 _5%@
R872 0_04 02_5%@R872 0_0402 _5%@
R871 0_04 02_5%@R871 0_0402 _5%@
D33
D33
1
1
1
2
2
2
4
4
4
5
3
3
3
8
8
C659
C659
1
2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
@
@
9
HDMI_TX2-_ CON
10
10
8
HDMI_TX2+ _CON
9
9
7
HDMI_TX1+ _CON
7
7
6
HDMI_TX1-_ CON
65
65
C562
C562
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
R1505
R1505
0_0402_ 5%
0_0402_ 5%
@
@
12
R860
R860
2.2K_040 2_5%
2.2K_040 2_5%
VGA_HDM I_DATA
VGA_HDM I_CLK
HDMI_CLK-_ CON
HDMI_CLK+ _CON
HDMI_TX0-_ CON
HDMI_TX0+ _CON
HDMI_TX1-_ CON
HDMI_TX1+ _CON
HDMI_TX2-_ CON
HDMI_TX2+ _CON
1 2
+5VS
U78
U78
1
VIN
GND2VOUT
3
+5VS_HD MI+CRT_VC C_CON
R861
R861
2.2K_040 2_5%
2.2K_040 2_5%
1 2
TAITW_ PDVBR0-19FLBS 4NN4N0
TAITW_ PDVBR0-19FLBS 4NN4N0
1
SA00004ZB0J
APL3517AI-TRG_SOT23-3
APL3517AI-TRG_SOT23-3
1
2
JHDMI1
JHDMI1
19
HP_DET
18
+5V
17
DDC/CEC_GND
16
SDA
15
SCL
14
Reserved
13
CEC
12
CK-
11
CK_shield
10
CK+
9
D0-
8
D0_shield
7
D0+
6
D1-
5
D1_shield
4
D1+
3
D2-
2
D2_shield
1
D2+
ME@
ME@
46@
46@
HDMI+HDCP
HDMI+HDCP
C561
C561
0.1U_040 2_16V4Z
0.1U_040 2_16V4Z
20
GND
21
GND
22
GND
23
GND
Title
Title
Security Class ification
Security Class ification
Security Class ification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
5
4
2012/07/ 01
2012/07/ 01
2012/07/ 01
3
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2014/07/ 01
2014/07/ 01
2014/07/ 01
2
Title
HDMI_CONN
HDMI_CONN
HDMI_CONN
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
1
39 69
39 69
39 69
1.0
1.0
1.0
A
B
C
D
E
Mini-Express Card(WLAN/WiMAX)
1 1
LAN_WAKE#<41,46,55>
COMBT@
COMBT@
1 2
R897 0_0402_5%
R897 0_0402_5%
1 2
BT_DISABLE#
R1556
R1556
1K_0402_5%
1K_0402_5%
COMBT@
R1557
0_0402_5%
0_0402_5%
COMBT@
R125 10_0402_5%
R125 10_0402_5%
1 2
@
@
COMBT@R1557
COMBT@
1 2
2
G
G
@
@
1
C199
@ C 199
@
2
10P_0402_50V8J
10P_0402_50V8J
BT_CTRL
61
D
D
Q157A
Q157A
S
S
For isolate Intel Rainbow Peak and
Compal debug card.
For EMI
CLK_PCI_DB
PCH_BT_DISABLE#<19>
2 2
PCH_BT_ON#<19> SUSP <10,55,61>
PCIE_WAKE#<15,19, 41>
BT_CTRL_RBT_CTRL
WLAN_CLKREQ1#<16>
CLK_PCIE_WLAN#<16>
CLK_PCIE_WLAN<16>
PCIE_PRX_DTX_N5<18>
PCIE_PRX_DTX_P5<18>
PCIE_PTX_C_DRX_N5<18>
PCIE_PTX_C_DRX_P5<18>
EC_TX<46>
EC_RX< 46>
34
D
D
5
G
G
Q157B
Q157B
S
S
@
@
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
NGFF(SSD)
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C566
C566
0_0402_5%
0_0402_5%
SATA_DTX_IRX_P0_R
SATA_DTX_IRX_N0_R
SATA_ITX_DRX_N0_R
SATA_ITX_DRX_P0_R
1 2
SATA_DET#
R896 0_0402_5%
R896 0_0402_5%
1
2
1
2
0.01U_0402_25V7K
0.01U_0402_25V7K
3 3
SATA_DET#<13>
For SSD use:
4 4
+3VS_SSD
C567
C567
10U_0805_10V6K
10U_0805_10V6K
@
@
12
R906
R906
@
@
1
C568
C568
2
10U_0805_10V6K
10U_0805_10V6K
JSSD1
JSSD1
1
CONFIG_3
3
GND1
5
GND2
7
USB_D+
9
USBD-
11
GND3
13
13
NC
NC
15
15
NC
NC
17
17
NC
NC
19
19
NC
NC
21
CONFIG_0
23
WAKE_ON_WWAN#
25
DPR
27
GND4
29
USB3.0-TX-(Device)
31
USB3.0-TX+(Device)
33
GND5
35
USB3.0-RX-(Device)
37
USB3.0-RX+(Device)
39
GND6
41
PERN0/SATA-B+
43
PERP0/SATA-B-
45
GND7
47
PETN0/SATA-A-
49
PETP0/SATA-A+
51
GND8
53
REFCLKN
55
REFCLKP
57
GND9
59
ANTCTL0
61
ANTCTL1
63
ANTCTL2
65
ANTCTL3
67
RESET#
69
CONFIG_1
71
GND10
73
GND11
75
CONFIG_2
76
PEG1
1
@
@
C569
C569
2
ME@
ME@
FULL_CARD_POWER_OFF#
1 2
R1620 0_0402_5%@R1620 0_0402_5%@
PCIE_WAKE#
WLAN_CLKREQ1#
PCI_RST#_R
CLK_PCI_DB
+3VS_WLAN
100_0402_1%
100_0402_1%
R887
R887
1 2
EC_TX
1 2
EC_RX
R888
R888
100_0402_1%
100_0402_1%
SSD Active:4.5W(1.5A)
+3VS
J5
J5
2
112
JUMP_43X79
JUMP_43X79
@
@
2
3.3VAUX1
4
3.3VAUX2
6
8
W_DISABLE#1
NC
NC
NC
NC
NC
NC
NC
NC
GPIO_5
GPIO_6
GPIO_7
W_DISABLE#2
UIM-RFU
UIM-RESET
UIM-CLK
UIM-DATA
UIM-PWR
DEVSLP
GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_4
PERST#
CLKREQ#
PEWAKE#
COEX3
COEX2
COEX1
SIM_DETECT
SUSCLK
3.3VAUX3
3.3VAUX4
3.3VAUX5
PEG2
TYCO_2199230-3
TYCO_2199230-3
10
12
12
14
14
16
16
18
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
NC1
58
NC2
60
62
64
66
68
70
72
74
77
LED#1/DAS/DSS#
BT_DISABLE#
R889
R889
100K_0402_5%
100K_0402_5%
For EC to detect
1 2
d
ebug card insert.
+3VS_SSD
R907
R907
1 2
0_0402_5%
0_0402_5%
@
@
JWLN1
JWLN1
1
WAKE#
3
NC
5
NC
7
CLKREQ#
9
GND
11
REFCLK-
13
REFCLK+
15
GND
17
NC
19
NC
21
GND
23
PERn0
25
PERp0
27
GND
29
GND
31
PETn0
33
PETp0
35
GND
37
NC
39
NC
41
NC
LED_WWAN#
43
NC
LED_WLAN#
45
NC
LED_WPAN#
47
NC
49
NC
51
NC
53
GND
TAITW_PFPET0-AFGLBG1ZZ4N0
TAITW_PFPET0-AFGLBG1ZZ4N0
RR6
RR6
4.7K_0402_5%
4.7K_0402_5%
SMB_DATA
@
@
9/18 JP1 Pin2,24,52 contact t o +3VS_WLAN for AOAC function
+3VS_WLAN
+1.5VS
12
For RF request
R880 0_0402_5%R880 0_0402_5%
R881 0_0402_5%@R881 0_0402_5%@
R882 R_short 0_0402_5%R882 R_s hort 0_0402_5%
R883 0_0402_5%@R883 0_0402_5%@
R884 0_0402_5%@R884 0_0402_5%@
USB20_N10 <18>
USB20_P10 <18>
BT_CRTL (GPIO22)
R400
R400
0_0603_5%
0_0603_5%
1 2
1 2
1 2
1 2
1 2
BT on module
Enable
GND
GND
PERST#
+3.3Vaux
GND
+1.5V
SMB_CLK
GND
USB_D-
USB_D+
GND
+1.5V
GND
+3.3V
GND
ME@
ME@
1
C57
C57
@
@
2
0.047U_0402_16V4Z
2
3.3V
4
6
1.5V
8
NC
10
NC
12
NC
14
NC
16
NC
18
20
NC
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
0.047U_0402_16V4Z
+1.5VS_WLAN
LPC_FRAME#_R
LPC_AD3_R
LPC_AD2_R
LPC_AD1_R
LPC_AD0_R
WL_OFF#
SMB_CLK_S3_R
SMB_DATA_S3_R
WLAN&BT Combo module circuits
*
PCH_BT_ON#
12
SATA_PRX_DTX_P0<13>
SATA_PRX_DTX_N0<13>
4.7K_0402_5%
4.7K_0402_5%
12
12
RR5
RR4
RR4
RR5
@
@
4.7K_0402_5%
4.7K_0402_5%
@
@
SATA_PTX_C_DRX_P0<13>
SATA_PTX_C_DRX_N0<13>
0.01U_0402_16V7K
0.01U_0402_16V7K
SATA_PRX_DTX_P0 SATA_DTX_IRX_P0
0.01U_0402_16V7K
0.01U_0402_16V7K
SATA_PTX_C_DRX_P0
SATA_PTX_C_DRX_N0
12
C572
@ C572
@
12
SATA_DTX_IRX_N0SATA_PRX_DTX_N0
C573
C573
@
@
+3VS
SATA_PTX_DRX_P0<13>
SATA_PTX_DRX_N0<13>
12
@
@
PLT_RST#
H
L
RR1
RR1
4.7K_0402_5%
4.7K_0402_5%
7
1
2
5
4
19
17
18
3
13
21
+1.5VS
1
@
@
C564
C564
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
PCH_WL_OFF# <14>
PLT_RST# <14,23,32,41,46>
+3VALW
+3VS_WLAN
SMB_CLK_S3 <11,12,17,47>
SMB_DATA_S3 <11,12,17,47>
BT on module
Disable
L
H
SATA_PTX_DRX_P0
SATA_PTX_DRX_N0
SATA_PRX_DTX_P0
SATA_PRX_DTX_N0
UR1
EN
A_INp
A_INn
B_OUTp
B_OUTn
A_PRE1
B_PRE1
TEST
GND1
GND2
EPAD
PS8520CTQFN20GTR2A0_TQFN20_4X4
PS8520CTQFN20GTR2A0_TQFN20_4X4
VDD1
VDD2
A_PRE0
B_PRE0
A_OUTp
A_OUTn
B_INp
B_INn
@UR1
@
NC1
NC2
Reserve for SW mini-pcie debug card.
eries resistors closed to KBC side.
1
@
@
C565
C565
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
S
LPC_FRAME#_R
LPC_AD3_R
LPC_AD2_R
LPC_AD1_R
LPC_AD0_R
PCI_RST#_R
CLK_PCI_DB
AOAC_ON#<46>
1 2
R873 0_0402_5%@R873 0_0402_5%@
1 2
R874 0_0402_5%@R874 0_0402_5%@
1 2
R875 0_0402_5%@R875 0_0402_5%@
1 2
R876 0_0402_5%@R876 0_0402_5%@
1 2
R878 0_0402_5%@R878 0_0402_5%@
1 2
R879 0_0402_5%@R879 0_0402_5%@
AOAC@
AOAC@
R436
R436
1 2
100K_0402_5%
100K_0402_5%
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
PLT_RST#
0.1U_0402_16V4Z
0.1U_0402_16V4Z
softstart (RC) will check on EVT PCB
C574 0.01U_0402_16V7KC574 0.01U_0402_16V7K
1 2
1 2
1 2
1 2
CR2
CR2
CR1
CR1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
@
@
2
2
CR3 0.01U_0402_16V7K
CR3 0.01U_0402_16V7K
CR4 0.01U_0402_16V7K
CR4 0.01U_0402_16V7K
CR5 0.01U_0402_16V7K
CR5 0.01U_0402_16V7K
CR6 0.01U_0402_16V7K
CR6 0.01U_0402_16V7K
SATA_PTX_C_DRX_P0_R
SATA_PTX_C_DRX_N0_R
SATA_PRX_DTX_P0_R
SATA_PRX_DTX_N0_R
0.01U_0402_16V7K
0.01U_0402_16V7K
4.7K_0402_5%
4.7K_0402_5%
1 2
1 2
@
@
1 2
1 2
@
@
C575 0.01U_0402_16V7KC575 0.01U_0402_16V7K
R903 0_0402_5%R903 0_0402_5%
R904 0_0402_5%R904 0_0402_5%
+3VS
@
@
10
20
6
16
9
8
15
SATA_ITX_DRX_P0_C SATA_ITX_DRX_P0_R
14
SATA_ITX_DRX_N0_C SATA_ITX_DRX_N0_R
11
SATA_DTX_IRX_P0_C SATA_DTX_IRX_P0_R
12
SATA_DTX_IRX_N0_C SATA_DTX_IRX_N0_R
12
RR2
RR2
@
@
@
@
@
@
R898 0_0402_5%R898 0_0402_5%
1 2
R899 0_0402_5%R899 0_0402_5%
1 2
C571 0.01U_0402_16V7KC571 0.01U_0402_16V7K
1 2
C570 0.01U_0402_16V7KC570 0.01U_0402_16V7K
1 2
12
RR3
RR3
4.7K_0402_5%
4.7K_0402_5%
@
@
LPC_FRAME# <17,46>
LPC_AD3 <17,46>
LPC_AD2 <17,46>
LPC_AD1 <17,46>
LPC_AD0 <17,46>
CLK_PCI_DB <16>
+3VALW
@
@
C526
C526
+3VS
Q104
Q104
AO3413_SOT23-3
AO3413_SOT23-3
1
AOAC@
AOAC@
2
1
C1055
C1055
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
J8
J8
112
JUMP_43X79
JUMP_43X79
S
S
G
G
+3VS_WLAN
@
@
2
D
D
13
1
AOAC@
AOAC@
C533
C533
1
0.1U_0402_16V4Z
@
@
2
0.1U_0402_16V4Z
2
0.01U_0402_25V7K
0.01U_0402_25V7K
2
C1048
C1048
9/18 Increase for Intel AOAC f unction
SATA_ITX_DRX_P0_R
SATA_ITX_DRX_N0_R
SATA_DTX_IRX_P0_R
SATA_DTX_IRX_N0_R
Title
Title
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF LC FU TURE CENTER. AND CONTAINS CON FIDENTIAL
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF LC FU TURE CENTER. AND CONTAINS CON FIDENTIAL
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF LC FU TURE CENTER. AND CONTAINS CON FIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.
A
B
C
2012/07/01
2012/07/01
2012/07/01
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
2014/07/01
2014/07/01
2014/07/01
Title
Mini-Card
Mini-Card
Mini-Card
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Date: Sheet of
Date: Sheet of
Date: Sheet of
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
E
40 69
40 69
40 69
1.0
1.0
1.0
5
+3VALW
D D
PCIE_PRX_DTX_N4<18>
PCIE_PRX_DTX_P4<18>
PCIE_PTX_C_DRX_N4<18>
PCIE_PTX_C_DRX_P4<18>
CLK_PCIE_LAN#<16>
CLK_PCIE_LAN<16>
+3VALW_LAN
15P_0402_50V8J
15P_0402_50V8J
LAN_PWR_ON#
+3VALW_LAN
PLT_RST#<14,23,32,40,46>
RL6 0_ 0402_5%RL6 0_0402_ 5%
RL7 0_ 0402_5%
RL7 0_ 0402_5%
RL16 4.7K_0402_5%
RL16 4.7K_0402_5%
1
CL50
CL50
2
Near
Pin13
1
1
1
CL62
CL62
25MHZ_10PF_7V25000014
25MHZ_10PF_7V25000014
2
LAN_PWR_ON#<46>
C C
PCIE_WAKE#<15,19,40>
LAN_WAKE#<40,46,55>
B B
A A
0.1U_0402_16V4Z
0.1U_0402_16V4Z
RL3
RL3
12
100K_0402_5%
100K_0402_5%
Vendor recommand reserve the
PU resistor close LAN chip
1 2
RL4 4.7K_0402_5%
RL4 4.7K_0402_5%
Place Close to Chip
1 2
CL43 0.1U_0402_16V7KCL43 0.1U_0402_16V7K
1 2
CL44 0.1U_0402_16V7KCL44 0.1U_0402_16V7K
1 2
1 2
@
@
1 2
@
@
+3VALW_LAN
CLKREQ_LAN#<16>
1
CL51
CL51
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
Near
Near
Pin19
Pin31
YL7
YL7
3
3
GND
GND
2
4
@
@
CL34
CL34
@
@
1 2
RL17 4.7K_0402_5%@RL17 4.7K_0402_5%@
1
CL52
CL52
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
LAN_XTALI
LAN_XTALOLAN_XTALO
1
CL63
CL63
15P_0402_50V8J
15P_0402_50V8J
2
J16
J16
112
JUMP_43X79
JUMP_43X79
QL1
QL1
D
S
D
S
G
G
1
LP2301ALT1G_SOT-23
LP2301ALT1G_SOT-23
2
2
1
CL39
CL39
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
PCIE_PRX_C_DTX_N4
PCIE_PRX_C_DTX_P4
PLT_RST#
PCIE_WAKE#_R
LAN_XTALO
LAN_XTALI
+1.1_AVDDL
+1.1_AVDDL
+1.1_AVDDL
+1.1_AVDDL_L
+1.1_AVDDL
1
CL53
CL53
2
Near
Pin6
13
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
@
@
1
CL54
CL54
2
PLT_RST#
+3VALW_LAN
1
@
@
CL35
CL35
0.01U_0402_25V7K
0.01U_0402_25V7K
2
29
30
36
35
32
33
2
3
25
26
27
28
7
8
4
13
19
31
34
6
41
0.1U_0402_16V4Z
0.1U_0402_16V4Z
UL1
UL1
@
@
SA00006540J
SA00006540J
QCA8172-AL3A-R_QFN40_5X5
4
UL1
UL1
TX_N
Atheros
Atheros
TX_P
QCA8171
QCA8171
RX_N
RX_P
REFCLK_N
REFCLK_P
PERST#
WAKE#
TESTMODE_0
TESTMODE_1
TESTMODE_2
NC
XTLO
XTLI
CLKREQ#
AVDDL
AVDDL
AVDDL
AVDDL
AVDDL_REG
GND
QCA8171-BL3A-R_QFN40_5X5
QCA8171-BL3A-R_QFN40_5X5
3
RL2 0_0603_5%RL2 0_0603_5%
1 2
1
CL37
CL37
CL36
@ CL36
@
2
1000P_0402_50V7K
1000P_0402_50V7K
Close to
Pi
n40
H --> Overclocking mode
L --> Not overclocking mode
38
LAN_ACTIVITY#
LED_0
39
LAN_LINK#
LED_1
23
LAN_CLK_SEL
LED_2
TRXN0
TRXP0
TRXN1
TRXP1
TRXN2
TRXP2
TRXN3
TRXP3
RBIAS
VDD33
DEBUGMODE
PPS
DVDDL_REG
AVDD33
AVDDH
AVDDH_REG
RL5 10K_0402_5%
12
LAN_MDI0-
11
LAN_MDI0+
15
LAN_MDI1-
14
LAN_MDI1+
18
LAN_MDI2-
17
LAN_MDI2+
21
LAN_MDI3-
20
LAN_MDI3+
10
LAN_RBIAS
1
+3VALW_LAN
40
+LX
LX
5
DEBUGMODE
24
37
16
+AVDD3.3
22
+2.7_AVDDH
9
Near
Pin9
RL5 10K_0402_5%
1 2
RL8 2.37K_0402_ 1%RL8 2.37K_0402_1%
Place Close to P IN10
RL9 30K_0402_5%
RL9 30K_0402_5%
+LX
RL10 30K_0402_5%RL10 30K_0402_5%
+1.1_DVDDL
1
1
CL55
CL55
CL56
CL56
2
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
@
@
LAN_MDI0- <42>
LAN_MDI0+ <42>
LAN_MDI1- <42>
LAN_MDI1+ <42>
LAN_MDI2- <42>
LAN_MDI2+ <42>
LAN_MDI3- <42>
LAN_MDI3+ <42>
@
@
1 2
1 2
1
CL57
CL57
2
Near
Pin22
12
0.1U_0402_16V4Z
0.1U_0402_16V4Z
QCA8171/72 Pin defination difference.
Pin17 Pin18 Pin19 Pin20 Pin21
QCA8171
QCA8172
LAN_MDI2+ LAN_MDI2- LAN_MDI3+ LAN_MDI3-+1.1_AVDDL
NC NC NC NC NC
Close together
LL1
LL1
1 2
4.7UH +-20% PCAA041B-4R7M 1.1A
4.7UH +-20% PCAA041B-4R7M 1.1A
1
CL38
CL38
Note: Place Close to LAN chip
LL1 DCR< 0.15 ohm
2
Rate current > 1A
10U_0805_10V4Z
10U_0805_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
LAN_ACTIVITY# <42>
LAN_LINK# <4 2>
RL5
N
C = 25MHz
Pull-Down = 48MH z
+LX
+LX+LX_R+1.1_DVDDL
Place Close to PIN1
1
@
@
1 2
2
CL45
CL45
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1000P_0402_50V7K
1000P_0402_50V7K
1U_0402_6.3V4Z
1U_0402_6.3V4Z
Near
in37
P
Optional
+3VS
+3VALW_LAN
1
1
CL59
CL59
CL58
CL58
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
SH00000GT0J
SH00000JM0J
1
2
CL46
CL46
1U_0402_6.3V4Z
1U_0402_6.3V4Z
CL47
CL47
10U_0805_10V4Z
10U_0805_10V4Z
+3VALW_LAN
1
2
CL48
CL48
2
Place close to Pin34
1
@C L49
@
2
CL49
10U_0805_10V4Z
10U_0805_10V4Z
FBMA-L11160808601LMA10T_2P
FBMA-L11160808601LMA10T_2P
1
1
CL40
CL40
CL41
CL41
2
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+AVDD3.3
Place close to Pin16
1 2
1
CL42
CL42
2
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
1
LL2
LL2
1
CL60
CL60
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
FBMA-L11160808601LMA10T_2P
FBMA-L11160808601LMA10T_2P
1
CL61
CL61
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
LL3
LL3
1 2
RL11 0_0603_5%RL11 0_0603_5%
1 2
+1.1_DVDDL+1.1_AVDDL_L +1.1_AVDDL
+3VALW_LAN
Title
Title
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
5
4
3
2012/07/01
2012/07/01
2012/07/01
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2014/07/01
2014/07/01
2014/07/01
Title
LAN_QCA8171
LAN_QCA8171
LAN_QCA8171
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Date: Sheet of
Date: Sheet of
Date: Sheet of
Wednesday, March 27, 2013
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
41 69
41 69
41 69
1
1.0
1.0
1.0
5
4
3
2
1
LAN_LINK#<41>
LAN_ACTIVITY#<41>
CL73 0.1U_0402_16V4ZCL73 0.1U_ 0402_16V4Z
D D
C C
LAN_MDI0+<41>
LAN_MDI0-<41>
LAN_MDI1+<41>
LAN_MDI1-<41>
LAN_MDI2+<41>
LAN_MDI2-<41>
LAN_MDI3+<41>
LAN_MDI3-<41>
@ CL69
@
0.1U_0402_16V4Z
0.1U_0402_16V4Z
place close to TL1
12
LAN_MDI0+ RJ45_MIDI0+
LAN_MDI0-
CL74 0.1U_0402_16V4ZCL74 0.1U_ 0402_16V4Z
12
LAN_MDI1+
LAN_MDI1-
CL75 0.1U_0402_16V4ZCL75 0.1U_ 0402_16V4Z
12
LAN_MDI2+
LAN_MDI2-
LAN_MDI3+
LAN_MDI3-
CL69
1
2
CL33
CL33
1U_0402_10V6K
1U_0402_10V6K
Place CL33 close to TL1CL69 reserved for EMI,
TCT
TL1
TL1
1
2
3
4
5
6
7
8
9
10
11
12
350UH_NS892407
350UH_NS892407
1
2
TCT1
TD1+
TD1-
TCT2
TD2+
TD2-
TCT3
TD3+
TD3-
TCT4
TD4+
TD4-
1:1
1:1
1:1
1:1
1:1
1:1
1:1
1:1
@
@
TL1
TL1
SP05000650J
SP05000650J
350UH_NS892405
MCT1
MX1+
MX1-
MCT2
MX2+
MX2-
MCT3
MX3+
MX3-
MCT4
MX4+
MX4-
JP/N
24
23
22
RJ45_MIDI0-
21
20
RJ45_MIDI1+
19
RJ45_MIDI1-
18
17
RJ45_MIDI2+
16
RJ45_MIDI2-
15
14
RJ45_MIDI3+
13
RJ45_MIDI3-
MCT0
MCT1
MCT2
MCT3
RL12
RL12
1 2
R_short 0_0805_5%
R_short 0_0805_5%
RL18
RL18
1 2
R_short 0_0805_5%
R_short 0_0805_5%
RL19
RL19
1 2
R_short 0_0805_5%
R_short 0_0805_5%
RL20
RL20
1 2
R_short 0_0805_5%
R_short 0_0805_5%
12
RL15
RL15
75_0402_1%
75_0402_1%
1
CL66
CL66
10P_1206_2KV7K
10P_1206_2KV7K
2
LAN_LINK#
LAN_ACTIVITY#
LAN_LINK#
470P_0402_50V7K
470P_0402_50V7K
LAN_ACTIVITY#
470P_0402_50V7K
470P_0402_50V7K
FL5
FL5
SURGE@
SURGE@
JRJ45
JRJ45
9
Green LED-
1 2
+3VALW_LAN
1
@
@
CL64
CL64
2
1
+3VALW_LAN
@
@
CL65
CL65
2
BS401N 1206
BS401N 1206
1 2
RL13 220_0 402_5%RL13 220_0402_5%
RJ45_MIDI0+
RJ45_MIDI0-
RJ45_MIDI1+
RJ45_MIDI2+
RJ45_MIDI2-
RJ45_MIDI1-
RJ45_MIDI3+
RJ45_MIDI3-
1 2
RL14 220_0 402_5%RL14 220_0402_5%
10
Green LED+
1
PR1+
2
PR1-
3
PR2+
4
PR3+
5
PR3-
6
PR2-
7
PR4+
8
PR4-
11
Yellow LED-
12
Yellow LED+
SANTA_130456-111
SANTA_130456-111
ME@
ME@
14
G2
13
G1
placement
B B
Place Close to TL1
MCT3
MCT2
MCT1
DL3
DL3
@
@
LAN_MDI0-
LAN_MDI0+
A A
1
2
3
4
10
1
10
9
2
9
8
3
8
7
4
7
6
556
GND
TCLAMP3302N.TCT_SLP2626P10-10
TCLAMP3302N.TCT_SLP2626P10-10
11
LAN_MDI1+
LAN_MDI1-
LAN_MDI2-
LAN_MDI2+
DL4
DL4
@
@
1
2
3
4
10
1
10
9
2
9
8
3
8
7
4
7
6
556
GND
TCLAMP3302N.TCT_SLP2626P10-10
TCLAMP3302N.TCT_SLP2626P10-10
11
LAN_MDI3+
LAN_MDI3-
DL3, DL4 Reserv e for Surge
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
5
4
3
2012/07/01
2012/07/01
2012/07/01
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
MCT0
SURGE@
SURGE@
2
FL2
BS401N 1206
BS401N 1206
SURGE@
SURGE@
FL2
1 2
FL3
FL3
BS401N 1206
BS401N 1206
FL1
FL1
1 2
FL1 ~ FL4 Reser ve for Serge Li ne to GND
L3 change to BS4 200N for ESD re quest
F
Title
Title
2014/07/01
2014/07/01
2014/07/01
Title
LAN Transformer
LAN Transformer
LAN Transformer
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
2
2
FL4
FL4
BS4200N-C-LV_SMB-F2
BS4200N-C-LV_SMB-F2
1
SURGE@
SURGE@
1
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Wednesday, March 27, 2013
BS401N 1206
BS401N 1206
1 2
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
1
42 69
42 69
42 69
1.0
1.0
1.0
5
4
3
2
1
D D
C C
B B
Close U29
C449
C449
2200P_0 402_50V7K
2200P_0 402_50V7K
C658
C658
2200P_0 402_50V7K
2200P_0 402_50V7K
1
2
1
2
REMOTE1 +
REMOTE1 -
REMOTE2 +
REMOTE2 -
+3VS
Remove +VDD netname
2
C443
C443
0.1U_040 2_16V4Z
0.1U_040 2_16V4Z
1
FAN_PWM & TACH
for PWM FAN
REMOTE1 +
REMOTE1 -
REMOTE2 +
REMOTE2 -
SMSC thermal sensor
laced near by VRAM
p
U29
U29
1
VDD
2
DP1
3
DN1
4
DP2
5
DN2
EMC1403 -2-AIZL-TR_MSOP10
EMC1403 -2-AIZL-TR_MSOP10
Address 1001_101xb
internal pull up 1.2K to 1.5V
R
for initial thermal
shutdown temp
SMCLK
SMDATA
ALERT#
THERM#
GND
10
9
8
7
6
R624
R624
10K_040 2_5%
10K_040 2_5%
EC_SMB_ CK2
EC_SMB_ DA2
12
+3VS
@
@
EC_SMB_ CK2 <17,23,32,34,3 6,46>
EC_SMB_ DA2 <17,23,32,34,3 6,46>
REMOTE2+/-:
Trace width/space:10/10 mil
Trace length:<8"
REMOTE1 +
C982
C982
100P_04 02_50V8J
100P_04 02_50V8J
REMOTE1 -
REMOTE2 +
C984
C984
100P_04 02_50V8J
100P_04 02_50V8J
REMOTE2 -
1
C
2
B
B
2
C
Q137
Q137
MMST390 4-7-F_SOT323-3
MMST390 4-7-F_SOT323-3
E
E
3 1
@
@
Close to SSD side
1
C
Under VRAM
2
B
B
2
C
Q138
Q138
MMST390 4-7-F_SOT323-3
MMST390 4-7-F_SOT323-3
E
E
3 1
@
@
FAN1 Conn
+5VS
JFAN1
JFAN1
1
1
2
C986
C986
10U_080 5_10V6K
10U_080 5_10V6K
A A
Security Class ification
Security Class ification
Security Class ification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
5
4
2012/07/ 01
2012/07/ 01
2012/07/ 01
3
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
0.1U_040 2_10V7K
0.1U_040 2_10V7K
1
2014/07/ 01
2014/07/ 01
2014/07/ 01
2
C49
1
@C4 9
@
2
EC_FAN_ SPEED<46 >
EC_FAN_ PWM< 46>
Title
Title
Title
VGA Thermal sensor/FAN CONN
VGA Thermal sensor/FAN CONN
VGA Thermal sensor/FAN CONN
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Wednesday, March 27, 2013
2
2
3
3
4
4
5
G5
6
G6
ACES_85 205-04001
ACES_85 205-04001
ME@
ME@
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
1
43 69
43 69
43 69
1.0
1.0
1.0
A
B
C
D
E
F
G
H
1 1
@J12
@
J12
SATA_PTX_C_DRX_P1
SATA_PTX_C_DRX_N1
SATA_PRX_C_DTX_N1SATA_PRX_DTX_N1
SATA_PRX_C_DTX_P1
2
1
C635
C635
10U_0603_6.3V6M
10U_0603_6.3V6M
2
SATA_PTX_C_DRX_P1<13>
SATA_PTX_C_DRX_N1<13>
1 2
SATA_PRX_DTX_N1<13>
SATA_PRX_DTX_P1<13>
+5VS
2 2
1
C631
C631
1000P_0402_50V7K
1000P_0402_50V7K
2
SATA_PRX_DTX_P1
1
C632
C632
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C627 0.01U_0402_16V7KC 627 0.01U_0402_16V7K
1 2
C628 0.01U_0402_16V7KC 628 0.01U_0402_16V7K
+5VS
1
C633
C633
1U_0603_10V4Z
1U_0603_10V4Z
2
JUMP_43X79
JUMP_43X79
1
C634
C634
10U_0603_6.3V6M
10U_0603_6.3V6M
2
112
SATA HDD Conn.
+5VS_HDD
JHDD1
JHDD1
1
GND
2
A+
3
A-
4
GND
5
B-
6
B+
7
GND
8
V33
9
V33
10
V33
11
GND
12
GND
13
GND
14
V5
15
V5
16
V5
17
GND
18
Reserved
19
GND
20
V12
21
V12
V1222GND
SANTA_191201-1
SANTA_191201-1
ME@
ME@
GND
HDD_PWR_DET#
SATA_PTX_C_DRX_P2<13>
SATA_PTX_C_DRX_N2<13>
SATA_PRX_DTX_N2<13>
SATA_PRX_DTX_P2<13>
24
23
SATA_PRX_DTX_N2
SATA_PRX_DTX_P2
SLI_FAN_SPEED<32,46>
ODD_DETECT#<19>
+5VS_ODD
ODD_DA#_R<14>
SLI_FAN_PWM<32,46>
+3VS
1 2
C629 0.01U_0402_16V7KC 629 0.01U_0402_16V7K
1 2
C630 0.01U_0402_16V7KC 630 0.01U_0402_16V7K
1 2
R1479 R_short 0_0402_5%R1479 R_short 0_0402_5%
1 2
R1476 0_0402_5%@R1476 0_0402_5%@
1 2
R710 0_0402_5%@R710 0_0402_5%@
1 2
R921 10K_0402_5%R921 10K_0402_5%
1 2
R1497 0_0402_5%@R1497 0_0402_5%@
1 2
R1494 R_short 0_0402_5%R1494 R_short 0_0402_5%
SATA_PTX_C_DRX_P2
SATA_PTX_C_DRX_N2
SATA_PRX_C_DTX_N2
SATA_PRX_C_DTX_P2
SATA ODD Conn.
1
2
3
4
5
6
7
8
9
10
11
ODD_DA#
12
JODD2
ME@JODD2
ME@
GND
A+
AGND
BB+
GND
DP
+5V
+5V
MD
GND
GND
GND13GND
SANTA_202404-1
SANTA_202404-1
15
14
ODD Power Control
J6
@ J6
@
2
112
JUMP_43X79
+5VALW +5VS
12
R923
3 3
ODD_EN<19>
100K_0402_5% @
100K_0402_5% @
12
R1478
R1478
100K_0402_5%
100K_0402_5%
2
R923
Q89
Q89
G
G
12
13
D
D
2N7002KW_SOT323-3
2N7002KW_SOT323-3
S
S
HDD_PWR_DET#
R1496
R1496
100K_0402_5%
100K_0402_5%
R1110
R1110
100K_0402_5%
100K_0402_5%
C1049
C1049
0.1U_0402_16V4Z @
0.1U_0402_16V4Z @
12
ODD_EN#
R1504 0_0402_5%R1504 0_0402_5%
1 2
JUMP_43X79
Q88 AO3413_SOT23-3
Q88 AO3413_SOT23-3
S
S
G
G
1
2
2
D
D
13
2
C1057
C1057
0.01U_0402_16V7K
0.01U_0402_16V7K
1
AO3413
VGS= -4.5V, Id=-3A, Rds<97m ohm
2
C638
C638
0.01U_0402_16V7K@
0.01U_0402_16V7K@
1
1
C639
C639
10U_0603_6.3V6M
10U_0603_6.3V6M
2
+5VS_ODD
1
2
C637
C637
0.1U_0402_16V4Z
0.1U_0402_16V4Z
ODD_EN#
2N7002KW_SOT323-3
2N7002KW_SOT323-3
+5VS_ODD
Q90
Q90
2
G
G
12
R1477
470_0603_5%
470_0603_5%
13
D
D
S
S
@R1477
@
@
@
4 4
Title
Title
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
A
B
C
D
2012/07/01
2012/07/01
2012/07/01
E
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
F
2014/07/01
2014/07/01
2014/07/01
Title
HDD/ODD CONN
HDD/ODD CONN
HDD/ODD CONN
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Date: Sheet of
Date: Sheet of
Date: Sheet of
Wednesday, March 27, 2013
G
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
44 69
44 69
44 69
H
1.0
1.0
1.0
5
D D
Place close to Pin 26
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C C
DMIC_CLK<35>
DMIC_DATA<35>
HDA_SDOUT_AUDIO
HDA_BITCLK_AUDIO
2
2
CA1399
B B
A A
CA1399
1
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
1
+3.3VD
+3.3VD
+CPVDD
FBMA-10-100505-301T_2P
FBMA-10-100505-301T_2P
+5VA
+5VD
FBMA-10-100505-301T_2P
FBMA-10-100505-301T_2P
+AVDD2
FBMA-10-100505-301T_2P
FBMA-10-100505-301T_2P
RA1660
RA1660
1 2
0_0402_5%
0_0402_5%
DGND
Tied at one point only under
the codec or near the codec
2
CA1397
CA1397
1
FBMA-10-100505-301T_2P
FBMA-10-100505-301T_2P
1 2
LA62
LA62
1 2
LA63
LA63
FBMA-10-100505-301T_2P
FBMA-10-100505-301T_2P
1 2
LA64
LA64
1 2
LA65
LA65
1 2
LA66
LA66
AGND
5
+5VA
1
2
CA1384
CA1384
CA1385
CA1385
2
1
10U_0805_10V4Z
10U_0805_10V4Z
HDA_SDOUT_AUDIO<13>
HDA_BITCLK_AUDIO<13>
HDA_SYNC_AUDIO<13>
PLUG_IN<50>
MIC_JD<50>
place close to pin 13
RA1651
RA1651
RA1652
RA1652
RA1653
RA1653
1 2
1 2
1 2
1 2
1 2
P/N chang to 0 ohm to B phase
1 2
R956 0_0402_5%R956 0_0402_5%
1 2
R957 0_0402_5%R957 0_0402_5%
PC Beep
HDA_SYNC_AUDIO
CA1398
CA1398
10P_0402_50V8J
10P_0402_50V8J
DMIC_CLK
EC Beep
PCH Beep
+3VS
+5VS
1 2
RA1658 0_0402_5%RA1658 0_0402_5%
1 2
@
@
RA1659 0_0402_5%
RA1659 0_0402_5%
If AVDD2 is design to 1.5V, you will get better
power consumption.
+1.5VS
+3VS
CA1379
CA1379
CA1386
CA1386
10_0402_5%
10_0402_5%
10_0402_5%
10_0402_5%
10_0402_5%
10_0402_5%
RA165439. 2K_0402_1% R A165439.2K_0402_1%
RA165620K_0402_1% RA165620K_0402_1%
10 mils
HDA_SDIN0<13>
+5VD
2
1
10U_0805_10V4Z
10U_0805_10V4Z
+5VD
2
CA1387
CA1387
1
10U_0805_10V4Z
10U_0805_10V4Z
DMIC_CLK_R
DMIC_DATA_RDMIC_DATA
BEEP#<46>
HDA_SPKR<13>
4
1
CA1380
CA1380
2
Place close to pin 1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
CA1381
CA1381
10U_0603_6.3V6M
10U_0603_6.3V6M
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
HDA_SDOUT_AUDIO_R
HDA_BITCLK_AUDIO_R
HDA_SYNC_AUDIO_R
MIC1_L<50>
MIC1_R<50>
HDA_SDIN0
4
3
1 2
@
Place close
to pin 9
+3.3VD
1
1
CA1382
CA1382
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
12
RA1657
RA1657
33_0402_5%
33_0402_5%
2
CA1396
CA1396
10P_0402_50V8J
10P_0402_50V8J
1
1 2
CA24 0.1U_0402_16V4ZCA24 0.1U_0402_16V4Z
1 2
CA23 0.1U_0402_16V4ZCA23 0.1U_0402_16V4Z
HDA_SDIN0_R
@
@
2
1
1 2
1 2
10U_0805_10V4Z
10U_0805_10V4Z
10U_0805_10V4Z
10U_0805_10V4Z
A_PDB
1
CA1378
CA1378
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
12
+AVDD2
CA1383
CA1383
DMIC_DATA_R
DMIC_CLK_R
PC_BEEP
C_MIC1_LMIC1_L
CA12802.2U_0603_6.3V6K CA12802.2U_0603_6.3V6K
C_MIC1_RMIC1_R
CA12792.2U_0603_6.3V6K CA12792.2U_0603_6.3V6K
10U_0805_10V4Z
10U_0805_10V4Z
CA1395
CA1395
CA1377
CA1377
HDA_RST_AUDIO#<13>
Place close to Pin 34/35/36
RA4
RA4
1 2
33_0402_5%
RA3
10K_0402_5%
10K_0402_5%
33_0402_5%
12
@ RA3
@
RA1648 0_0402_5%
RA1648 0_0402_5%
RA1649
RA1649
1 2
R_short 0_0402_5%
R_short 0_0402_5%
+CPVDD
1
2
PC_BEEPPC_BEEP1
@
UA1
UA1
1
DVDD
9
DVDD-IO
26
AVDD1
40
AVDD2
41
PVDD1
46
PVDD2
36
CPVDD
2
GPIO0/DMIC-DATA
3
GPIO1/DMIC-CLK
8
SDATA-IN
5
SDATA-OUT
6
BCLK
10
SYNC
12
PCBEEP
13
Sense A
14
Sense B
19
MIC1-L(PORT-B-L)
20
MIC1-R(PORT-B-R)
17
MIC2-L(PORT-F-L)
18
MIC2-R(PORT-F-R)
22
LINE1-L(PORT-C-L)
21
LINE1-R(PORT-C-R)
24
LINE2-L(PORT-E-L)
23
LINE2-R(PORT-E-R)
11
RESETB
47
PDB
ALC282-CG_MQFN48_6X6
ALC282-CG_MQFN48_6X6
+1.5VS
+3.3VD
HPOUT-L(PORT-I-L)
HPOUT-R(PORT-I-R)
ALC282 Configuation - example
4 external jacks: Line-in / Mic-in / Hp-out / SPDIF-OUT
Internal speaker
Internal Stereo DMIC
Pin Assignment Function
SPEAKER-OUT (pin-43/44/45/46_Port D)
Cap-Saving HP-OUT (pin-32/33_Port I) External Headphone out
MONO-OUT (pin-16)
MIC2 (pin-17/18_Port F)
Location
Internal
External Line in LINE1 (pin-21/22_Port C)
NC
Security Classification
Security Classification
Security Classification
NC
InternalDMIC1/2 (pin-2/3) Internal Mic ( Digital MIC )
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF LC FU TURE CENTER. AND CONTAINS CON FIDENTIAL
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF LC FU TURE CENTER. AND CONTAINS CON FIDENTIAL
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF LC FU TURE CENTER. AND CONTAINS CON FIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.
3
Issued Date
Issued Date
Issued Date
Internal Speaker
Mic inMIC1 (pin-19/20_Port B) External
MONO-OUT
MIC2-VREFO
MIC1-VREFO-R
MIC1-VREFO-L
JDREF
VREF
CPVEE
LDO1-CAP
LDO2-CAP
LDO3-CAP
SPK-OUT-LSPK-OUT-L+
SPK-OUT-R-
SPK-OUT-R+
SPDIF-OUT/GPIO2
DVSS
AVSS1
AVSS2
Thermal Pad
2
16
29
30
31
15
RA1650 20K_0402_1%RA1650 20K_0402_1%
28
32
HPOUTL_R HP_OUTL
33
HPOUTR_R HP_OUTR
Place close to Pin 34/35/36
35
CBN
37
CBP
CA1389 2.2U _0603_10V6KCA1389 2.2U_0603_10V6K
34
27
39
7
43
SPKOUT_L2-
42
SPKOUT_L1+
44
SPKOUT_R2-
45
SPKOUT_R1+
48
4
25
38
49
2012/05/02
2012/05/02
2012/05/02
+MIC1_VREFO_L
12
R5 60.4_0402_1%R5 60.4_0402_1%
R10 60.4_0402_1%R10 60.4_0402_1%
12
12
CA1391 2.2U_0603_10V6KCA1391 2.2U_0603_10V6K
1 2
CA1392 10U_0805_10V4ZCA1392 10U_0805_10V4Z
1 2
CA1393 10U_0805_10V4ZCA1393 10U_0805_10V4Z
1 2
CA1394 10U_0805_10V4ZCA1394 10U_0805_10V4Z
30 mils
1 2
R946
R946
FBMA-10-100505-301T_2P
FBMA-10-100505-301T_2P
SPK_R1
SPK_R2
SPK_L1
SPK_L2
For EMI
HDA_BITCLK_AUDIO_R
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
12
12
SPDIF_OUT
SPKOUT_R2-
R126 10_0402_5%
R126 10_0402_5%
1 2
10 mils
RA56
RA56
RA58
RA58
RA60
RA60
RA61
RA61
@
@
10P_0402_50V8J
10P_0402_50V8J
2012/5/02
2012/5/02
2012/5/02
10 mils
SPDIF_OUT <50>
EC_MUTE#<46>
1 2
CA9 1000P_0402_50V7K~N@ CA9 1000P_0402_50V7K~N@
1 2
CA10 1000P_0402_50V7K~N@ CA10 1000P_0402_50V7K~N@
1 2
CA11 1000P_0402_50V7K~N@ CA11 1000P_0402_50V7K~N@
1 2
CA12 1000P_0402_50V7K~N@ CA12 1000P_0402_50V7K~N@
0_0603_5%
0_0603_5%
1 2
0_0603_5%
0_0603_5%
1 2
0_0603_5%
0_0603_5%
1 2
0_0603_5%
0_0603_5%
1 2
DA1
@DA1
@
AZ5125-02S.R7G_SOT23-3
AZ5125-02S.R7G_SOT23-3
1
C200
@ C 200
@
2
Reserve for ESD request.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
Date: Sheet of
Date: Sheet of
Date: Sheet of
Ext. MIC
HP_OUTL <50>
HP_OUTR <50>
R438
R438
1 2
100K_0402_5%
100K_0402_5%
Audio Codec
Audio Codec
Audio Codec
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Wednesday, March 27, 2013
1
Place close to Pin 28
1
CA1388
CA1388
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2.2U_0603_10V6K
2.2U_0603_10V6K
12
R437
R437
100K_0402_5%
100K_0402_5%
@
@
2009/11/02 Modify
30 mils
SPK_L1SPKOUT_L1+
SPK_L2SPKOUT_L2SPK_R1SPKOUT_R1+
SPK_R2
2
3
2
3
1
DA2
AZ5125-02S.R7G_SOT23-3
AZ5125-02S.R7G_SOT23-3
1
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
1
1
CA1390
CA1390
2
ACES_85205-04001
ACES_85205-04001
@DA2
@
A_PDB
1
1
2
2
3
3
4
4
5
G5
6
G6
ME@
ME@
45 69
45 69
45 69
JSPK1
JSPK1
1.0
1.0
1.0
5
@
@
1
CE63
CE63
220P_0402_25V8J
220P_0402_25V8J
2
CE11
CE11
EC_SMB_CK1
EC_SMB_DA1
1
2
For EMI
CLK_PCI_EC
RE125 10_0402_5%
RE125 10_0402_5%
1 2
KBRST#<19>
SERIRQ<17>
LPC_FRAME#<17,40>
LPC_AD3<17,40>
LPC_AD2<17,40>
LPC_AD1<17,40>
LPC_AD0<17,40>
CLK_PCI_EC<16>
EC_SMI#<19>
EC_RX< 40>
EC_TX<40>
PLT_RST#<14,23,32,40,41>
EC_SCI#<19>
GATEA20<19>
EC_SMB_CK1
EC_SMB_DA1
KSI7
KSI6
WRST#
@
@
@ C E204
@
10P_0402_50V8J
10P_0402_50V8J
KSO[0..17]<47>
KSI[0..7]< 47>
1
CE204
2
KBRST#
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
CLK_PCI_EC
WRST#
EC_SMI#
EC_RX
EC_TX
PLT_RST#
EC_SCI#
GATEA20
KSO[0..17]
KSI[0..7]
IT0PAD IT0PAD
IT1PAD IT1PAD
IT2PAD IT2PAD
IT3PAD IT3PAD
IT4PAD IT4PAD
IT5PAD IT5PAD
IT6PAD IT6PAD
IT7PAD IT7PAD
For ESD
PLT_RST#
D D
WRST#<54>
+3VALW_R
Need to check which SMBus can be use for debug
C C
+3VALW_R
12
RE22
RE22
0_0603_5%
0_0603_5%
RE6
RE6
1 2
100K_0402_5%
100K_0402_5%
1U_0402_6.3V6K
1U_0402_6.3V6K
1 2
RE23 2.2K_0402_5%RE23 2.2K_0402_5%
1 2
RE24 2.2K_0402_5%RE24 2.2K_0402_5%
For factory EC flash
EC_GPO7
LAN_PWR_ON#<41>
DPWROK_EC<15>
EC_RSMRST#<15>
EC_LID_OUT#< 19>
100K_0402_5%
100K_0402_5%
ON/OFF<52>
PECI_EC
EC_SMB_CK2<17,23,32,34,36,43>
EC_SMB_DA2<17,23,32,34,36,43>
RE34 0_0402_5%RE34 0_0402_5%
VR_ON<64>
USB_ON#< 49>
RE25
RE25
1 2
12
@
@
LAN_PWR_ON#
USB_ON#
DPWROK_EC
EC_RSMRST#
AC_PRESENT_R
@ R E40
@
EC_SMB_CK1< 57,58>
EC_SMB_DA1< 57,58>
H_PECI<6>
B B
+3VS
1 2
RE29 2.2K_0402_5%RE29 2.2K_0402_5%
1 2
RE30 2.2K_0402_5%RE30 2.2K_0402_5%
+3VL
RE10 10K_0402_5%@RE10 10K_0402_5%@
1 2
RE13 10K_0402_5%RE13 10K_0402_5%
1 2
RE14 10K_0402_5%@RE14 10K_0402_5%@
1 2
RE15 10K_0402_5%RE15 10K_0402_5%
A A
1 2
RE33 10K_0402_5%RE33 10K_0402_5%
1 2
EC_SMB_CK1
EC_SMB_DA1
RE37 43_0402_5%RE37 43_0402_5%
EC_SMB_CK2
EC_SMB_DA2
ON/OFF
BKOFF#
ACPRN
LID_SW#
EXIO_CS
5
1 2
+3VLP
4
Close EC
.1U_0402_16V7K
.1U_0402_16V7K
RE2 0_0402_5%@RE2 0_0402_5%@
+RTCBATT
RE3 R_short 0_0402_5%RE3 R_short 0_0402_5%
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
EC_SMB_CK2
EC_SMB_DA2
VR_ON
EC_LID_OUT#
12
RE40
0_0402_5%
0_0402_5%
EC_SPI_CS1#
EC_SPI_SI
EC_SPI_SO_L
EC_SPI_CLK
4
CE1
CE1
12
VCOREVCC
1 2
1 2
UE1
UE1
4
KBRST#/GPB6
5
SERIRQ/GPM6
6
LFRAME#/GPM5
7
LAD3/GPM3
8
LAD2/GPM2
9
LAD1/GPM1
10
LAD0/GPM0
13
LPCCLK/GPM4
14
WRST#
15
ECSMI#/GPD4
16
PWUREQ#/BBO/SMCLK2ALT/GPC7
17
LPCPD#/GPE6
22
LPCRST#/GPD2
23
ECSCI#/GPD3
126
GA20/GPB5
58
KSI0/STB#
59
KSI1/AFD#
60
KSI2/INIT#
61
KSI3/SLIN#
62
KSI4
63
KSI5
64
KSI6
65
KSI7
36
KSO0/PD0
37
KSO1/PD1
38
KSO2/PD2
39
KSO3/PD3
40
KSO4/PD4
41
KSO5/PD5
42
KSO6/PD6
43
KSO7/PD7
44
KSO8/ACK#
45
KSO9/BUSY
46
KSO10/PE
51
KSO11/ERR#
52
KSO12/SLCT
53
KSO13
54
KSO14
55
KSO15
56
KSO16/SMOSI/GPC3
57
KSO17/SMISO/GPC5
110
PWRSW#
111
XLP_OUT
115
SMCLK1/GPC1
116
SMDAT1/GPC2
117
SMCLK2/PECI/GPF6
118
SMDAT2/PECIRQT#/GPF7
94
CRX1/SIN1/SMCLK3/GPH1/ID1
95
CTX1/SOUT1/GPH2/SMDAT3/ID2
112
VSTBY0
125
GPE4
33
GINT/CTS0#/GPD5
35
RTS1#/GPE5
93
CLKRUN#/GPH0/ID0
2
CK32KE/GPJ7
128
CK32K/GPJ6
S IC IT8586E/EX LQFP 128P KB CONTROLLER
S IC IT8586E/EX LQFP 128P KB CONTROLLER
1 2
RE1524
RE1524
1 2
RE1525
RE1525
1 2
RE1526
RE1526
1 2
RE1527
RE1527
+3VS
12
3
11
VBAT
VCORE
IT8586E/AX
IT8586E/AX
LQFP-128L
LQFP-128L
Int. K/B
Int. K/B
Matrix
Matrix
WAKE UP
WAKE UP
Clock
Clock
CPU1.5V_S3_GATE <10>
@
@
SPI_CS1#_R
0_0402_5%
0_0402_5%
@
@
SPI_SI_R1
0_0402_5%
0_0402_5%
@
@
SPI_SO_L1
0_0402_5%
0_0402_5%
@
@
SPI_CLK_PCH_1
0_0402_5%
0_0402_5%
1 2
RE5 0_0603_5%RE5 0_0603_5%
1 2
RE1 0_0603_5%@RE1 0_0603_5%@
+3VALW_EC
127
74
50
92
114
121
VCC
EXTERNAL SERIAL FLASH
EXTERNAL SERIAL FLASH
SM Bus
SM Bus
GPIO
GPIO
1
VSTBY
VSTBY
VSTBY
VSTBY26VSTBY
LPC
LPC
SPI Flash ROM
SPI Flash ROM
VSS
VSS
27
VSTBY(PLL)
VSS
VSS49VSS
91
113
AVCC
VSS
122
3
+3VL
+3VALW
All capacitors close to EC
+3VALW_R
0.1U_0402_16V4Z
0.1U_0402_16V4Z
12
CE10
CE10
minimum trace width 12 mil
PWM0/GPA0
PWM1/GPA1
PWM2/GPA2
PWM
PWM
UART
UART
AVSS
75
SPI_CS1#_R <17>
SPI_SI_R1 <17>
SPI_SO_L1 <17>
SPI_CLK_PCH_1 <17>
PWM3/GPA3
PWM4/GPA4
PWM5/GPA5
PWM6/SSCK/GPA6
PWM7/RIG1#/GPA7
TMRI0/GPC4
TMRI1/GPC6
ADC0/GPI0
ADC1/GPI1
ADC2/GPI2
ADC
ADC
ADC3/GPI3
ADC4/GPI4
ADC5/DCD1#/GPI5
ADC6/DSR1#/GPI6
ADC7/CTS1#/GPI7
DAC2/TACH0B/GPJ2
DAC3/TACH1B/GPJ3
DAC
DAC
DAC4/DCD0#/GPJ4
DAC5/RIG0#/GPJ5
PS2CLK0/TMB0/CEC/GPF0
PS2DAT0/TMB1/GPF1
PS2
PS2
PS2CLK2/GPF4
PS2DAT2/GPF5
EGAD/GPE1
EGCS#/GPE2
EGCLK/GPE3
GPIO
GPIO
SSCE0#/GPG2
SSCE1#/GPG0
DSR0#/GPG6
DTR1#/SBUSY/GPG1/ID7
CRX0/GPC0
CTX0/TMA0/GPB2
RI1#/GPD0
RI2#/GPD1
TACH2/GPJ0
TACH1A/TMA1/GPD7
TACH0A/GPD6
L80HLAT/BAO/GPE0
L80LLAT/GPE7
IT8586E-FX_LQFP128_14X14
IT8586E-FX_LQFP128_14X14
EC_AGND
GPF2
GPF3
GPH3/ID3
GPH4/ID4
GPH5/ID5
GPH6/ID6
AC_IN#
LID_SW#
GPJ1
NC
NC
NC
NC
3
2
+3VALW_R
+3VALW_R
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
12
12
CE9
CE9
CE8
CE8
24
PWR_LED#
25
BATT_CHG_LED#
28
BATT_LOW_LED#
29
LED_KB_PWM
30
SLI_FAN_PWM
31
EC_FAN_PWM
32
BEEP#
34
EC_GPO7
120
BATT_LEN#
124
SUSP#
66
NTC_V
67
TURBO_V
68
BATT_TEMP
69
IMVP_IMON
70
EC_ON
71
ADP_I
72
AD_ID
73
VDDQ_PGOOD
78
SUSWARN#
79
MAINPWON_EC
80
H_PROCHOT#_EC
81
ENBKL
85
USB_CH
86
PBTN_OUT#
87
PM_SLP_SUS#
88
SUSACK#
89
TP_CLK
90
TP_DATA
96
CAPS_LED#
97
PCH_PWR_EN
98
ACOFF
99
PCH_PWROK
101
EC_SPI_CS1#
102
EC_SPI_SI
103
EC_SPI_SO_L
105
EC_SPI_CLK
108
ACPRN
109
LID_SW#
82
EXIO_DATA
83
EXIO_CS
84
EXIO_CLK
77
EC_MUTE#
100
LAN_WAKE#
106
DRAMRST_CNTRL_EC
104
ME_FLASH
107
SYSON
119
BKOFF#
123
AOAC_ON#
18
PM_SLP_S3#
21
PM_SLP_S4#
76
NOVO#
48
SLI_FAN_SPEED
47
EC_FAN_SPEED
19
TP_LED#
20
NUM_LED#
VR_HOT#<64>
BATT_TEMP
ACPRN
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF LC FU TURE CENTER. AND CONTAINS CON FIDENTIAL
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF LC FU TURE CENTER. AND CONTAINS CON FIDENTIAL
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF LC FU TURE CENTER. AND CONTAINS CON FIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
12
CE7
CE7
RE39 0_0402_5%RE39 0_0402_5%
RE17 0_0402_5%RE17 0_0402_5%
CE16 100P_0402_50V8JC E16 100P_0402_50V8J
CE17 100P_0402_50V8JC E17 100P_0402_50V8J
0.1U_0402_16V4Z
12
12
CE6
CE6
CE5
CE5
1 2
RE38 0_0402_5%RE38 0_0402_5%
AC_PRESENT_R
EC_GPO7
EC_GPO7 SUS_VCCP
BATT_CHG_LED# <51>
BATT_LOW_LED# <51>
1 2
1 2
ACPRN <58>
LID_SW# <47>
1 2
RE41
RE41
R_short 0_0402_5%
R_short 0_0402_5%
H_PROCHOT#_EC
1 2
1 2
2012/05/02
2012/05/02
2012/05/02
RE43 0_0402_5%RE43 0_0402_5%
RE44 0_0402_5%
RE44 0_0402_5%
RE45 0_0402_5%RE45 0_0402_5%
PWR_LED# <51,52>
LED_KB_PWM <47>
SLI_FAN_PWM <32,44>
EC_FAN_PWM <43>
BEEP# <45>
BATT_LEN# <57>
SUSP# <32,55,60,61,62>
NTC_V <57>
TURBO_V < 57>
BATT_TEMP <57>
IMVP_IMON <64>
EC_ON <52,59>
ADP_I <57,58>
AD_ID <57>
VDDQ_PGOOD <60>
USB_CH <50>
PBTN_OUT# <15>
PM_SLP_SUS# <15,55>
SUSACK# <15>
TP_CLK <47>
TP_DATA <47>
CAPS_LED# <51>
PCH_PWR_EN <55,57>
ACOFF <58>
PCH_PWROK <15>
EXIO_DATA <54>
EXIO_CLK <54>
EC_MUTE# <45>
DRAMRST_CNTRL_EC <6>
ME_FLASH <13>
SYSON <60>
BKOFF# <35>
AOAC_ON# <40>
PM_SLP_S3# <15>
PM_SLP_S4# <15>
NOVO# <52>
SLI_FAN_SPEED <32,44>
EC_FAN_SPEED <43>
TP_LED# <51>
NUM_LED# <51>
2
G
G
QE1
QE1
2N7002H_SOT23-3
2N7002H_SOT23-3
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
@
@
SUSWARN# <15>
MAINPWON <57,59>
PROCHOT# <57>
ENBKL <35>
13
D
D
S
S
+3VALW_R
@
@
SUSP#
Deciphered Date
Deciphered Date
Deciphered Date
12
12
12
12
12
RE31
RE31
100K_0402_5%
100K_0402_5%
12
RE26
RE26
100K_0402_5%
100K_0402_5%
2
CE14
CE14
47P_0402_50V8J
47P_0402_50V8J
@
@
LE1
LE1
1 2
BLM18PG181SN1D_0603
BLM18PG181SN1D_0603
LE2
LE2
1 2
BLM18PG181SN1D_0603
BLM18PG181SN1D_0603
AC_PRESENTAC_PRESENT_R
VGA_AC_DET
EXIO_CS <54>
H_PROCHOT# <57,6>
SYSON
12
2012/5/02
2012/5/02
2012/5/02
12
CE3
CE3
0.1U_0402_16V4Z
0.1U_0402_16V4Z
EC_AGND
AC_PRESENT <15>
SUS_VCCP <62>
DRAMRST_CNTRL_EC
RE27
RE27
100K_0402_5%
100K_0402_5%
1
+3VALW_EC
12
VGA_AC_DET <23>
EC_FAN_SPEED
SLI_FAN_SPEED
TP_CLK
TP_DATA
USB_CH
USB_ON#
EC_FAN_PWM
LPC_FRAME#
ENBKL
CE4
CE4
1000P_0402_50V7K
1000P_0402_50V7K
+3VALW_R
12
RE8
RE8
10K_0402_5%
10K_0402_5%
@
@
RE7
RE7
1 2
@
@
100K_0402_5%
100K_0402_5%
+3VALW_R
@
@
LAN_WAKE#
12
12
1 2
1 2
1 2
RE1810K_0402_5% R E1810K_0402_5%
1 2
RE1910K_0402_5% R E1910K_0402_5%
1 2
RE2010K_0402_5%@RE2010K_0402_5%
@
1 2
RE2110K_0402_5% R E2110K_0402_5%
ACPRN
+3VS
20120730 VA
Reserved hardware
strapping for Auto load
code
12
RE4
RE4
10K_0402_5%
10K_0402_5%
12
RE32
RE32
10K_0402_5%
10K_0402_5%
+3VS
RE910K_0402_5% RE910K_0402_5%
RE1610K_0402_5% RE1610K_0402_5%
+3VS
RE114.7K_0402_5% RE114.7K_0402_5%
RE124.7K_0402_5% RE124.7K_0402_5%
+5VALW
+3VS
+3VS
RE28 10K_0402_5%RE28 10K_0402_5%
1 2
EMC Request
SYSON
CE15
CE15
1
@
@
2
0.1U_0402_10V6K
0.1U_0402_10V6K
Title
Title
Title
EC ITE8586LQFP
EC ITE8586LQFP
EC ITE8586LQFP
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
Date: Sheet of
Date: Sheet of
Date: Sheet of
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Wednesday, March 27, 2013
1
LAN_WAKE# <40,41,55>
+3VS
12
CE2
CE2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+3VLP
1.0
1.0
46 69
46 69
46 69
1.0
5
5" INT_KBD Conn.
1
D D
KSO16
KSO17
KSO2
KSO15
KSO6
KSO8
KSO13
KSO12
KSO11
KSO10
KSO3
KSO4
KSI0
KSO0
C C
CONN PIN define need double check
KSI[0..7]
KSO[0..17]
1 2
C794 100P_0402 _50V8J@C794 100P_0402_50V8J@
1 2
C795 100P_0402 _50V8J@C795 100P_0402_50V8J@
1 2
C734 100P_0402 _50V8J@C734 100P_0402_50V8J@
1 2
C736 100P_0402 _50V8J@C736 100P_0402_50V8J@
1 2
C738 100P_0402 _50V8J@C738 100P_0402_50V8J@
1 2
C740 100P_0402 _50V8J@C740 100P_0402_50V8J@
1 2
C742 100P_0402 _50V8J@C742 100P_0402_50V8J@
1 2
C744 100P_0402 _50V8J@C744 100P_0402_50V8J@
1 2
C746 100P_0402 _50V8J@C746 100P_0402_50V8J@
1 2
C748 100P_0402 _50V8J@C748 100P_0402_50V8J@
1 2
C750 100P_0402 _50V8J@C750 100P_0402_50V8J@
1 2
C752 100P_0402 _50V8J@C752 100P_0402_50V8J@
1 2
C754 100P_0402 _50V8J@C754 100P_0402_50V8J@
1 2
C756 100P_0402 _50V8J@C756 100P_0402_50V8J@
KSI[0..7] <46>
KSO[0..17] <46>
KSO1
KSO7
KSI2
KSO5
KSI3
KSO14
KSI7
KSI6
KSI5
KSI4
KSO9
KSI1
To TP/B Conn.
SMB_DATA_S3<11,12,17,40>
SMB_CLK_S3<11,12,17,40>
TP_DATA<46>
B B
TP_CLK<46>
SMB_DATA_S3
SMB_CLK_S3
TP_DATA
TP_CLK
1
@
@
C761
C761
100P_0402_50V8J
100P_0402_50V8J
2
1
@
@
C762
C762
100P_0402_50V8J
100P_0402_50V8J
2
+3VALW
+3VS
0.1U_0402_16V4Z
0.1U_0402_16V4Z
D58
D58
4
I/O3
5
VDD
6
I/O4
AZC099-04S.R7G_SOT23-6
AZC099-04S.R7G_SOT23-6
@
@
4
1 2
C735 100P_0402_50V8J@C735 100P_0402_50V8J@
1 2
C737 100P_0402_50V8J@C737 100P_0402_50V8J@
1 2
C739 100P_0402_50V8J@C739 100P_0402_50V8J@
1 2
C741 100P_0402_50V8J@C741 100P_0402_50V8J@
1 2
C743 100P_0402_50V8J@C743 100P_0402_50V8J@
1 2
C745 100P_0402_50V8J@C745 100P_0402_50V8J@
1 2
C747 100P_0402_50V8J@C747 100P_0402_50V8J@
1 2
C749 100P_0402_50V8J@C749 100P_0402_50V8J@
1 2
C751 100P_0402_50V8J@C751 100P_0402_50V8J@
1 2
C753 100P_0402_50V8J@C753 100P_0402_50V8J@
1 2
C755 100P_0402_50V8J@C755 100P_0402_50V8J@
1 2
C757 100P_0402_50V8J@C757 100P_0402_50V8J@
C760
C760
I/O1
GND
I/O2
For ESD request
3
JKB1
JKB1
1
1
2
2
3
3
4
4
KSO17
KSO16
KSO15
KSO10
KSO11
KSO14
KSO13
KSO12
KSO3
KSO6
KSO8
KSO7
KSO4
KSO2
KSI0
KSO1
KSO5
KSI3
KSI2
KSO0
KSI5
KSI4
KSO9
KSI6
KSI7
KSI1
JTP1
ME@JTP1
ME@
1
1
2
2
3
3
4
4
5
5
6
6
7
GND
8
GND
ACES_88514-00601-071
ACES_88514-00601-071
1
2
3
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
ACES_85202-3005N
ACES_85202-3005N
ME@
ME@
31
G1
32
G2
LED_KB_PWM<46>
+3VL
KB Lighting CONN.4pin
R1480
R1480
100K_0402_5%
100K_0402_5%
KBL@
KBL@
1 2
R1002
R1002
R_short 0_0402_5%
R_short 0_0402_5%
C758
C758
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
+VCC_KB_LED
R1229
R1229
10K_0402_5%
10K_0402_5%
KBL@
KBL@
Q163
Q163
2
G
12
G
Lid Switch
+VCC_LID
2
VDD
1
OUTPUT
2
GND
1
2
C905
C905
@
@
1
0.1U_0402_10V6K
0.1U_0402_10V6K
+5VS
AO3413
VGS= -4.5V, Id=-3A, Rds<97m ohm
AO3413_SOT23-3
AO3413_SOT23-3
Q121
R1232
R1232
1 2
0_0402_5%
0_0402_5%
1 2
3
Q121
S
S
G
G
2
1
@
@
2
12
13
D
D
2N7002KW_SOT323-3
2N7002KW_SOT323-3
S
S
R1003 100K_0402_5%R 1003 100K_0402_5%
5711ACDL-M3T1S SOT-23
5711ACDL-M3T1S SOT-23
U37
U37
D
D
KBL@
KBL@
13
KBL_DET
C907
C907
0.01U_0402_16V7K
0.01U_0402_16V7K
2
C759
C759
10P_0402_50V8J
10P_0402_50V8J
1
JKBL1
JKBL1
1
1
2
2
3
3
4
4
5
G1
6
G2
E&T_6906-Q04N-00R
E&T_6906-Q04N-00R
ME@
ME@
2
1
+3VS
R1230
R1230
1 2
@
@
10K_0402_5%
10K_0402_5%
R1231
R1231
1 2
@
@
10K_0402_5%
10K_0402_5%
1
+VCC_KB_LED
@
@
C908
C908
0.1U_0402_16V4Z
0.1U_0402_16V4Z
KBL_DET#
KBL_DET#
C553
C553
12
330P_0402_50V8J
330P_0402_50V8J
KBL_DET# <54>
LID_SW# <46>
A A
Title
Title
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
5
4
3
2012/07/01
2012/07/01
2012/07/01
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2014/07/01
2014/07/01
2014/07/01
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet
For ESD Request
KB/ KB-LIGHT/ LID IC
KB/ KB-LIGHT/ LID IC
KB/ KB-LIGHT/ LID IC
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
1
47 69
47 69
47 69
1.0
1.0
1.0
of
5
RW1
RW1
R_short 0_0603_5%
R_short 0_0603_5%
1 2
+3V3_AUX +3VS_CARD
D D
C C
RW10 R_short 0_0402_5%RW10 R _short 0_0402_5%
1.2V Power Source Selection:
ptional)
(O
1
CW25
CW25
15P_0402_50V8J
15P_0402_50V8J
2
12
RW2
RW2
1 2
1M_0402_5%
1M_0402_5%
YW1
YW1
1
1
25MHZ_10PF_7V25000014
25MHZ_10PF_7V25000014
Vendor recommend to reserve
GND
+3VS_CARD+3VS
AC Coupling close to
pin1 and pin2 of Chip
USB30_RX_N6<18>
USB30_RX_P6<18>
USB30_TX_N6<18>
USB30_TX_P6<18>
3
3
GND
2
4
1
CW26
CW26
15P_0402_50V8J
15P_0402_50V8J
2
4
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
USB20_P4<18>
USB20_N4<18>
680_0402_1%
680_0402_1%
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+3V3_AUX
CW5
CW5
1 2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 2
RW9
RW9
CW6
CW6
1 2
12
CW1
CW1
12
CW2
CW2
12
CW8
CW8
12
CW9
CW9
USB30_RX_N6_C
USB30_RX_P6_C
USB30_TX_N6_C
USB30_TX_P6_C
+DV12
+3VS_CARD
UW1
UW1
12
DVDD12
13
V33IN
1
TXN
2
TXP
4
RXN
5
RXP
6
X1
7
X2
3
AVDD12
28
AVDD12
26
DP
27
DM
8
AVDD33
9
RTERM
24
RSTZ
GL3213-OHY03_QFN28_5X5
GL3213-OHY03_QFN28_5X5
3
CW3
CW3
1 2
4.7U_0603_10V6K
4.7U_0603_10V6K
PMOS
AVDD33
DVDD33
VUHSI
SD_WP
SD_CDZ
MS_INS
23
25
22
21
20
SB6
19
SB5
18
SB4
17
SB3
16
SB2
SB1
G1
SD_DATA0_MS_DATA1_R
15
10
11
14
29
+CRD_POWER+DV12
+3VS_CARD
CW4
CW4
1 2
1U_0402_10V6K
1U_0402_10V6K
SD_DATA2_MS_CLK_R
SD_MS_DATA3_R
SD_CMD_MS_DATA2_R
SD_CLK_MS_DATA0_R
SD_DATA1_MS_BS_R
SD_WP
SD_CD#
MS_INS#
RW3 0_0402_5%RW3 0_0402_5%
RW4 0_0402_5%RW4 0_0402_5%
RW5 0_0402_5%RW5 0_0402_5%
RW6 0_0402_5%RW6 0_0402_5%
RW7 0_0402_5%RW7 0_0402_5%
RW8 0_0402_5%RW8 0_0402_5%
2
Close to chip
1 2
1 2
1 2
1 2
1 2
1 2
1
SD_DATA2_MS_CLK
SD_MS_DATA3
SD_CMD_MS_DATA2
SD_CLK_MS_DATA0
SD_DATA0_MS_DATA1
SD_DATA1_MS_BS
< 4 in 1 Card Reader Connector >
(40mil)
+CRD_POWER
800mA
+DV12
20 mils
1
@
1
2
CW19
CW19
B B
Close to Pin12
1
CW7
CW7
2
CW20
CW20
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1U_0402_10V6K
1U_0402_10V6K
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
Close to Pin3 Close to Pin 28
1
1
2
2
CW21
CW21
0.1U_0402_16V4Z
0.1U_0402_16V4Z
Colse to Conn.
@
CW15
CW15
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
All of cap. close to chip
mils
Clo
se to Pin22 Close to Pin 25 Close to Pin13
A A
+3VS_CARD +3V3_AUX
1
1
CW22
CW22
2
4.7U_0603_10V6K
4.7U_0603_10V6K
1
CW10
CW10
2
2
CW23
CW23
0.1U_0402_16V4Z
0.1U_0402_16V4Z
5
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
40 mils40
1
2
CW24
CW24
1U_0402_10V6K
1U_0402_10V6K
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
3
JREAD2
JREAD2
22
XD-VCC
30
XD10-D0
29
XD11-D1
28
XD12-D2
27
XD13-D3
26
XD14-D4
25
XD15-D5
24
XD16-D6
23
XD17-D7
33
XD07-WE
32
XD08-WP
34
XD06-ALE
39
XD01-CD
38
XD02-R/B
37
XD03-RE
36
XD04-CE
35
XD05-CLE
31
XD GND
40
XD GND
41
SD CD/WP GND
42
SD CD/WP GND
T-SOL_144-1313002600_40P_NR-T
T-SOL_144-1313002600_40P_NR-T
ME@
ME@
2012/07/01
2012/07/01
2012/07/01
SD4-VDD
MS9-VCC
SD5-CLK
SD7-DAT0
SD8-DAT1
SD9-DAT2
SD1-DAT3
SD2-CMD
SD-CD
SD-WP
SD6-VSS
SD3-VSS
MS8-SCLK
MS4-DATA0
MS3-DATA1
MS5-DATA2
MS7-DATA3
MS6-INS
MS2-BS
MS1-VSS
MS10-VSS
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
11
18
9
SD_CLK_MS_DATA0
4
SD_DATA0_MS_DATA1
3
SD_DATA1_MS_BS
21
SD_DATA2_MS_CLK
19
SD_MS_DATA3
16
SD_CMD_MS_DATA2
1
SD_CD#
2
SD_WP
6
13
17
SD_DATA2_MS_CLK
10
SD_CLK_MS_DATA0
8
SD_DATA0_MS_DATA1
12
SD_CMD_MS_DATA2
15
SD_MS_DATA3
14
MS_INS#
7
SD_DATA1_MS_BS
5
20
2014/07/01
2014/07/01
2014/07/01
2
+CRD_POWER
(40mil)
(40mil)
1
2
CW16
CW16
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
CW17
CW17
10U_0805_10V6K
10U_0805_10V6K
2
CW18
CW18
0.1U_0402_16V4Z
0.1U_0402_16V4Z
Colse to Conn. Colse to Socket Pin11.
SD_CLK_MS_DATA0 S D_DATA2_MS_CLK
RW11
RW11
10_0402_5%
10_0402_5%
10P_0402_50V8J
10P_0402_50V8J
SD_DATA2_MS_CLK SD_C LK_MS_DATA0
10P_0402_50V8J
10P_0402_50V8J
Title
Title
Title
Card reader GL3213
Card reader GL3213
Card reader GL3213
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
@
@
1 2
1
CW550
CW550
@
@
2
RW13
RW13
10_0402_5%
10_0402_5%
@
@
1 2
1
CW552
CW552
@
@
2
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Wednesday, March 27, 2013
For EMI
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
1
RW12
RW12
10_0402_5%
10_0402_5%
CW551
CW551
10P_0402_50V8J
10P_0402_50V8J
RW14
RW14
10_0402_5%
10_0402_5%
CW553
CW553
10P_0402_50V8J
10P_0402_50V8J
48 69
48 69
48 69
@
@
1 2
1
@
@
2
1 2
1
2
@
@
@
@
1.0
1.0
1.0
A
B
C
D
E
LEFT SIDE USB3.0 PORT X1
VOUT
VOUT
FLG
1
USB30_RX_R_N2
1
4
USB30_RX_R_P2
4
1
USB30_TX_R_N2
1
4
USB30_TX_R_P2
4
1
1
4
4
+USB_VCCA+5VALW
8
7
6
5
1
C904
C904
1000P_0402_50V7K@
1000P_0402_50V7K@
2
USB20_N2_R
USB20_P2_R
USB30_RX_P5 USB30_RX_R_P5
USB30_RX_R_N2
USB30_RX_R_P2
USB30_TX_R_N2
USB30_TX_R_P2
YSCLAMP0524P_SLP2510P8-10-9
YSCLAMP0524P_SLP2510P8-10-9
C302 0.1U_0402_10V6KC302 0.1U_0402_10V6K
C301 0.1U_0402_10V6KC301 0.1U_0402_10V6K
B
USB_OC1# <18>
USB20_N2<18>
USB20_P2<18>
USB30_RX_N2<18>
USB30_RX_P2<18>
USB30_TX_N2<18>
USB30_TX_P2<18>
USB30_RX_P2 USB30_RX_R_P2
USB30_TX_N2 USB30_TX_C_N2 USB30_TX_R_N2
1 2
C300 0.1U_0402_10V6KC300 0.1U_0402_10V6K
1 2
C299 0.1U_0402_10V6KC299 0.1U_0402_10V6K
For ESD request
D27
D27
@
@
9
10
10
8
9
9
7
7
7
6
6 5
6 5
1 2
1 2
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
1
USB30_RX_R_N2
1
1
2
2
2
4
4
4
5
3
3
3
8
8
USB30_TX_C_N5 USB30_TX_R_N5USB30_TX_N5
USB30_TX_C_P5 USB30_TX_R_P5USB30_TX_P5
USB30_RX_R_P2
USB30_TX_R_N2
USB30_TX_R_P2
USB20_N2_R
1 2
R1165 0_0402_5%@R1165 0_0402_5%@
1 2
R1164 0_0402_5%
R1164 0_0402_5%
@
@
1 2
R1161 0_0402_5%@R1161 0_0402_5%@
1 2
R1160 0_0402_5%
R1160 0_0402_5%
R1159 0_0402_5%@R1159 0_0402_5%@
R1158 0_0402_5%
R1158 0_0402_5%
2012/07/01
2012/07/01
2012/07/01
@
@
1 2
1 2
@
@
C
3
2
1
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
USB30_TX_C_P2 USB30_TX_R_P2USB30_TX_P2
D24
D24
@
@
I/O2
GND
I/O1
AZC099-04S.R7G_SOT23-6
AZC099-04S.R7G_SOT23-6
USB20_N3_RUSB20_N3
USB20_P3_RUSB20_P3
USB30_RX_R_N5USB30_RX_N5
I/O4
VDD
I/O3
+USB_VCCA
6
5
4
1 2
1 2
R1162 0_0402_5%
R1162 0_0402_5%
1 2
R1163 0_0402_5%
R1163 0_0402_5%
@
@
1 2
R1154 0_0402_5%
R1154 0_0402_5%
@
@
1 2
R1155 0_0402_5%
R1155 0_0402_5%
@
@
1 2
R1156 0_0402_5%
R1156 0_0402_5%
@
@
1 2
R1157 0_0402_5%
R1157 0_0402_5%
@
@
@
@
+5VALW
USB20_P2_R
C815 220U_6.3V_M
C815 220U_6.3V_M
@
@
+
+
1 2
C817 470P_0402_50V7KC817 470P_0402_50V7K
C818
C818
1 2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
JUSB2
JUSB2
1
VBUS
2
D-
3
D+
4
GND_1
5
SSRX-
6
7
8
9
GND_6
SSRX+
GND_5
GND_2
SSTX-
GND_4
SSTX+
GND_3
SANTA_370300-1
SANTA_370300-1
ME@
ME@
2014/07/01
2014/07/01
2014/07/01
For ESD request
13
12
11
10
D
+USB_VCCA
C814 220U_6.3V_M
C814 220U_6.3V_M
1 2
+
+
1 2
C816 470P_0402_50V7KC816 470P_0402_50V7K
1 2
C819
C819
0.1U_0402_16V4Z
0.1U_0402_16V4Z
JUSB1
JUSB1
1
VBUS
USB20_N2_RUSB20_N2
USB20_P2_RUSB20_P2
USB30_RX_R_N2USB30_RX_N2
2
D-
3
D+
4
GND_1
5
SSRX-
6
SSRX+
7
GND_2
8
SSTX-
9
SSTX+
SANTA_370300-1
SANTA_370300-1
ME@
ME@
GND_6
GND_5
GND_4
GND_3
For ESD request
13
12
11
10
For EMI request
USB2.0 choke --> SM070000I00
USB3.0 Choke --> SM070001U00
L69
L69
USB30_RX_N5
USB30_RX_P5
USB30_TX_C_N5
USB30_TX_C_P5
USB20_N3
USB20_P3
Title
Title
Title
USB 3.0 PORT (LEFT)
USB 3.0 PORT (LEFT)
USB 3.0 PORT (LEFT)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Date: Sheet of
Date: Sheet of
Date: Sheet of
Wednesday, March 27, 2013
2
2
3
3
WCM-2012-900T_4P
WCM-2012-900T_4P
L71
L71
2
2
3
3
WCM-2012-900T_4P
WCM-2012-900T_4P
L73
L73
2
2
3
3
WCM-2012-900T_4P
WCM-2012-900T_4P
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
1
USB30_RX_R_N5
1
4
USB30_RX_R_P5
4
1
USB30_TX_R_N5
1
4
USB30_TX_R_P5
4
1
1
4
4
E
USB20_N3_R
USB20_P3_R
49 69
49 69
49 69
1.0
1.0
1.0
U39
U39
1
GND
C767 0.1U_0402_16V4ZC767 0.1U_0402_16V4Z
1 1
12
USB_ON#<46>
Low Active 2A
Fo
2
VIN
VIN3VOUT
4
USB_ON# USB_OC1#
EN
G547I2P81U_MSOP8
G547I2P81U_MSOP8
r EMI request
USB2.0 choke --> SM070001S0J
USB3.0 Choke --> SM070001S0J
L68
L68
USB30_RX_N2
USB30_RX_P2
USB30_TX_C_N2
USB30_TX_C_P2
2 2
USB20_N2
USB20_P2
2
2
3
3
WCM-2012-900T_4P
WCM-2012-900T_4P
L70
L70
2
2
3
3
WCM-2012-900T_4P
WCM-2012-900T_4P
L72
L72
2
2
3
3
WCM-2012-900T_4P
WCM-2012-900T_4P
For ESD request
D29
D29
@
@
USB30_RX_R_N5
USB30_RX_R_P5
3 3
4 4
USB30_TX_R_N5
USB30_TX_R_P5
USB20_N3_R
9
10
10
8
9
9
7
7
7
6
6 5
6 5
YSCLAMP0524P_SLP2510P8-10-9
YSCLAMP0524P_SLP2510P8-10-9
D25
D25
@
@
3
I/O2
2
GND
1
I/O1
AZC099-04S.R7G_SOT23-6
AZC099-04S.R7G_SOT23-6
A
1
USB30_RX_R_N5
1
1
2
USB30_RX_R_P5
2
2
4
USB30_TX_R_N5
4
4
5
USB30_TX_R_P5
3
3
3
8
8
6
I/O4
5
VDD
4
I/O3
USB20_N3<18>
USB20_P3<18>
USB30_RX_N5<18>
USB30_RX_P5<18>
USB30_TX_N5<18>
USB30_TX_P5<18>
+5VALW
USB20_P3_R
5
4
3
2
1
+5V_CHGUSB
Touch panel
JTHP
ME@JTHP
R2 0_ 0603_5%R2 0_0603_5%
+5VS
D D
USB20_N8<18>
USB20_P8<18>
USB20_N8
USB20_P8
USB20_N8
1 2
R1168 0_0402_5%R1168 0 _0402_5%
1 2
R1169 0_0402_5%R1169 0 _0402_5%
L75
L75
2
2
3
3
WCM-2012-900T_4P
WCM-2012-900T_4P
@
@
1
1
4
4
USB20_N8_THP
USB20_P8_THP
USB20_N8_THP
USB20_P8_THPUSB20_P8
12
USB20_N8_THP
USB20_P8_THP
ME@
1
1
2
2
3
3
4
4
5
5
6
6
7
G7
8
G8
ACES_85205-06001
ACES_85205-06001
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C1099
@ C1099
@
2
USB20_P1_C
USB20_N1_C
EXT_MIC_L
EXT_MIC_R
MIC_JD<45>
HP_OUTR<45>
HP_OUTL<45>
SPDIF_OUT<45>
PLUG_IN<45>
MIC_JD
HP_OUTR
HP_OUTL
SPDIF_OUT
PLUG_IN
+5VS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
1
C1100
C1100
220P_0402_25V8J
220P_0402_25V8J
2
JSB1
JSB1
ME@
ME@
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
19
17
G1
20
18
G2
ACES_50505-0184N-001
ACES_50505-0184N-001
For ESD
Sleep & Charge
R
+5VALW
10U_0603_6.3V6M
10U_0603_6.3V6M
0.01U_0402_16V7K
0.01U_0402_16V7K
1
C1096
C1096
C C
1
C1097
C1097
2
2
For TI charger
Mode S0 S3
CHG_MOD 01
B B
CHG_MOD<54>
+5VALW
ight side USB Charger Port (USB_Port5, near JMIC1)
Close to U8 Pin 1
+5VALW
R1553
R1553
10K_0402_5%
10K_0402_5%
1 2
1 2
R1560 0_0402_5%R1560 0 _0402_5%
1 2
R1561 10K_040 2_5%
R1561 10K_040 2_5%
@
@
1 2
R1551
10K_0402_5%
10K_0402_5%
R1585
10K_0402_5%
10K_0402_5%
R1586
10K_0402_5%
10K_0402_5%
TI@R1551
TI@
1 2
@R 1585
@
1 2
@R 1586
@
CHG_MOD1
ILIM_SEL0
R1555
R1555
ILIM_SEL2
ILIM_SEL1
2
G
G
+5VALW
R1559
R1559
10K_0402_5%
10K_0402_5%
1 2
13
D
D
S
S
10K_0402_5%
10K_0402_5%
20K_0402_5%
20K_0402_5%
20K_0402_5%
20K_0402_5%
12
0_0402_5%
0_0402_5%
@
@
Q122
Q122
2N7002KW_SOT323-3
2N7002KW_SOT323-3
@
@
@
@
1 2
R1584
R1584
TI@
TI@
1 2
R1552
R1552
1 2
R1554
@R1554
@
R1558
R1558
12
0_0402_5%887@
0_0402_5%887@
CHG_MOD2
1
C1098
C1098
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
Close to U8
USB20_P1<18>
USB20_N1<18>
USB_CH<46>
+5VALW +5V_CHGUSB
50 mil 50 mil
USB20_P1
USB20_N1
USB_CH
CHG_MOD2
CHG_MOD1
CHG_MOD0
ILIM_SEL2
ILIM_SEL1
ILIM_SEL0
1
3
2
5
6
7
8
4
16
15
U8
P5V
DP_UP
DM_UP
PSW_EN
CHG_MOD2
CHG_MOD1
CHG_MOD0
NC2
NC1
NC0
887T@U8
887T@
VBUS_OUT
DP_DOWN
DM_DOWN
BC_CON
ALARM
GND
GND_PAD
GL887-OCGC_QFN16_3X3
GL887-OCGC_QFN16_3X3
U8
U8
TPS2546RTER_QFN1 6_4X4
TPS2546RTER_QFN1 6_4X4
12
10
11
9
13
14
17
USB20_P1_C
USB20_N1_C
TI@
TI@
@
USB_OC0# <18>
Genesys GL887
CHG_MOD1 C HG_MOD0
CHG_MOD2
0 0
0
*
0
1
1
1
1
*
20120902 VA2
T182PAD@T182PAD
Change to OC0#
0
1
0
1
1
0
0
0
1
1
0
1
1
*
*
Charge Mode
Charge Disable
CDP mode
DCP mode
Apple 1A mode
Apple 2A mode
Auto mode (DCP and Apple 1A)
Auto mode (DCP and Apple 2A)
TI TPS2543
CHG_MOD2
CHG_MOD1
0
1
1
1
0
1
1 1
0
0
0
1
1
1
1
0
0
1 1
0
Genesys GL887T
CHG_MOD1 C HG_MOD0
CHG_MOD2
0 0
0
0
X
1
1
0
*
1
0
1
0
1
LIM_SEL2
I
X
0
X
X
X
X
X
X
1
DCH
CDP
SDP2
SDP1
S
DCP_Short
DCP_Divider
DCP_Auto
D
*
CHG_MOD0
0
1 1 Data connected and Load detect active
1
0
0
0
1
0
1
0
1
0
1
1
MODE
O
UT held low /Data lines disconnected
Data connected
Data connected
DP1
Data connected
Stay in DCP BC1.2 Charging mode
Stay in DCP Divider1 Charging mode
Data disconnected and Load detect active
CP_Auto
Data disconnected and Load detect active
Auto 2A mode without wake up function
Auto 2A mode with wake up function
BC1.2 CDP mode with Smart CDP
Charge Mode
Power down mode
BC1.2 SDP mode
BC1.2 DCP mode
Apple 2A mode
Ext. MIC
A A
+MIC1_VREFO_L
Remove Diode (DA1, DA2)
RA1623
1 2
RA1623
2.2K_0402_5%
2.2K_0402_5%
1 2
4
EXT_MIC_R
EXT_MIC_L
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
3
2012/07/01
2012/07/01
2012/07/01
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2014/07/01
2014/07/01
2014/07/01
Title
Title
Title
AUDIO-B CONN/ USB CHARGER
AUDIO-B CONN/ USB CHARGER
AUDIO-B CONN/ USB CHARGER
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Date: Sheet of
Date: Sheet of
Date: Sheet of
Wednesday, March 27, 2013
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
1
50 69
50 69
50 69
1.0
1.0
1.0
RA1622
RA1622
2.2K_0402_5%
2.2K_0402_5%
MIC1_R<45>
MIC1_L<45>
5
RA1634 1K_0402_5%RA1634 1K_0402_5%
RA1633 1K_0402_5%RA1633 1K_0402_5%
12
12
A
TT CHARGE/LOW LED
B
White
LED2
Amber
BATT_LOW_LED#< 46>
BATT_CHG_LED#<46>
BATT_LOW_LED#
White
BATT_CHG_LED#
R1012
R1012
470_0402_5%
470_0402_5%
R1014
R1014
470_0402_5%
470_0402_5%
12
12
LED2
3
2
1
12-22-S2ST3D-C30-2C_WHI-ORG
12-22-S2ST3D-C30-2C_WHI-ORG
LION LED SC500007F0J
+5VALW
PWR_LED#<46,52>
HDD_LED#_R
CAPS_LED#<46>
CapsLK LED
12-21SYGCS530-E1S155TR8_W
12-21SYGCS530-E1S155TR8_W
PWR LED HDD LED
TouchPad_LED 2012-0507 --> Change LED1 to T/P LED
TP_LED#<46>
HDD_LED#<13>
R1621
R1621
0_0402_5%
0_0402_5%
R1622
0_0402_5%
0_0402_5%
1 2
1 2
@R1622
@
HDD_LED#_R
NUM_LED#<46>
Screw Hole
C: H_3P8X 3
H13
H13
H10
H10
H12
HOLEA
HOLEA
1
H12
HOLEA
HOLEA
1
HOLEA
HOLEA
1
ME: H_8P0 X 8; H_3P3X 1; H_4P0X3P0N X 2; H_2P0X 1
A: H_2P8X 8
B: H_3P8X 3
H11
H11
H14
H14
HOLEA
HOLEA
HOLEA
HOLEA
1
1
GPUCPU
H30
H30
HOLEA
HOLEA
LED3
LED3
12-21SYGCS530-E1S155TR8_W
12-21SYGCS530-E1S155TR8_W
LED1
LED1
12-21SYGCS530-E1S155TR8_W
12-21SYGCS530-E1S155TR8_W
LED4
LED4
12-21SYGCS530-E1S155TR8_W
12-21SYGCS530-E1S155TR8_W
H15
H15
HOLEA
HOLEA
1
H31
H31
HOLEA
HOLEA
1
1
LED5
LED5
H32
H32
HOLEA
HOLEA
1
White
21
21
21
21
H33
H33
HOLEA
HOLEA
1
LION LED:SC500004Y0J
12
R1563300_0402_5% R1563300_04 02_5%
R1013
R1013
12
300_0402_5%
300_0402_5%
R1322
R1322
12
300_0402_5%
300_0402_5%
R1323
R1323
12
300_0402_5%
300_0402_5%
LED3 LED2 LED1 LED4
POWER BATTERY T/P CapsLK
MIN PCIE: H_3P3 X 1CPU and GPU: H_3P8X 6
E: H_3P3X 1
+5VS
+5VALW
+5VS
+5VS
PCB Fedical Mark PAD
FD1FD1
FD2FD2
FD3FD3
FD4FD4
1
1
1
1
E: H_3P3X 3
H26
H16
H16
HOLEA
HOLEA
1
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
2012/07/01
2012/07/01
2012/07/01
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
H26
HOLEA
HOLEA
1
Deciphered Date
Deciphered Date
Deciphered Date
H23
H23
HOLEA
HOLEA
1
H_3P0X9
H25
H25
H24
H24
HOLEA
HOLEA
HOLEA
HOLEA
1
1
2014/07/01
2014/07/01
2014/07/01
H28
H28
HOLEA
HOLEA
1
H29
H29
HOLEA
HOLEA
1
H35
H35
H36
H36
H37
H34
H34
HOLEA
HOLEA
HOLEA
HOLEA
1
1
Title
Title
Title
LED
LED
LED
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Date: Sheet of
Date: Sheet of
Date: Sheet of
Wednesday, March 27, 2013
HOLEA
HOLEA
1
H37
HOLEA
HOLEA
H_2P8X4P0NX1
H20
H20
HOLEA
HOLEA
1
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
1
H21
H21
HOLEA
HOLEA
1
51 69
51 69
51 69
1.0
1.0
1.0
ON/OFF switch
SW2
ON/OFFBT N#
1
2
EC_ON<46 ,59>
1 2
SHORT PA DS
SHORT PA DS
Power Button
T
OP Side
tom Side
Bot
@S W2
@
SMT1-05_ 4P
SMT1-05_ 4P
5
6
J7
J7
@
@
51_ON#
ON/OFF
3
4
1 2
R1531 0_ 0603_5%R1531 0_0603_5%
DAN202U T106_SC70-3
DAN202U T106_SC70-3
EC_ON
R1523
R1523
10K_040 2_5%
10K_040 2_5%
NOVO#<4 6>
R19 0_0402_5 %
R19 0_0402_5 %
R28 0_0402 _5%R28 0_04 02_5%
For S3.5
100K_04 02_5%
100K_04 02_5%
D72
1
1 2
NO51ON@ R1118
NO51ON@
NO51ON@
NO51ON@
1 2
1 2
R1116
R1116
NO51ON@
NO51ON@
1 2
NO51ON@D 72
NO51ON@
3
2
13
D
D
2
G
G
S
S
+3VALW +3 VL
1 2
NOVO#
+3VL+3V ALW
R1117
R1117
100K_04 02_5%
100K_04 02_5%
1 2
For S3.5
ON/OFF
51_ON#
Q153
Q153
2N7002_ SOT23-3
2N7002_ SOT23-3
R1118
100K_04 02_5%
100K_04 02_5%
ON/OFF <46>
51_ON# <56 >
For S3.5
R1119
R1119
100K_04 02_5%
100K_04 02_5%
1 2
1 2
R1532 0_ 0603_5%
R1532 0_ 0603_5%
D56
D56
2
1
3
DAN202U T106_SC70-3
DAN202U T106_SC70-3
@
@
NOVO_BT N#
NO51ON@ default reserved
Power Button/B link
o Function/B Conn. 10pin
t
+5VALW
PWR_ LED#<46,51>
C552
C552
330P_04 02_50V8J
330P_04 02_50V8J
For ESD Request
EMI REQUEST 1ST = SCA00000E00
2ST = SCA00000R00
ON/OFFBT N#
12
NOVO_BT N#
1
100P_04 02_50V8J@
100P_04 02_50V8J@
2
C551
C551
JPW R1
ME@JPWR1
ME@
8
GND
7
GND
6
6
5
5
4
4
3
3
2
2
1
1
ACES_88 514-00601-071
ACES_88 514-00601-071
Security Class ification
Security Class ification
Security Class ification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
2012/07/ 01
2012/07/ 01
2012/07/ 01
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2014/07/ 01
2014/07/ 01
2014/07/ 01
Title
Title
Title
ONOFF SW/ PWR-B CONN/ ISPD
ONOFF SW/ PWR-B CONN/ ISPD
ONOFF SW/ PWR-B CONN/ ISPD
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
Custom
Custom
Custom
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Date: Sheet of
Date: Sheet of
Date: Sheet of
Wednesday, March 27, 2013
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
52 69
52 69
52 69
1.0
1.0
1.0
5
D D
C C
4
3
2
1
B B
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .
5
4
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .
3
2011/07/21 2012/12/31
2011/07/21 2012/12/31
2011/07/21 2012/12/31
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
Title
Title
Title
NVSR
NVSR
NVSR
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
Date: Sheet of
Date: Sheet of
Date: Sheet of
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
1
53 69Wednesday, March 27, 2013
53 69Wednesday, March 27, 2013
53 69Wednesday, March 27, 2013
1.0
1.0
1.0
1 2
@
@
RXE1 0_0603_5%
EXIO_DATA<46>
CHG_MOD<50,54>
EXIO_CLK<46>
EXIO_CS<46>
GC6_EVENT#<19,23,54>
CHG_MOD
EXIO_CLK
EXIO_CS
GC6_EVENT#
GC6@
GC6@
RXE2 0_0402_5%
RXE2 0_0402_5%
FB_CLAMP<23,27,54>
GC6_EVENT#<19,23,54>
DGPU_PWROK<19,27,62,63>
DGPU_PWR_EN<14,23,55>
DGPU_HOLD_RST#<14,23>
DGPU_GC6_EN<14,27>
NVDD_PWR_EN<14,63>
12
RE460_0402_5% RE460_0402_5%
12
KBL_DET#<47>
FB_CLAMP<23,27,54>
WRST#<46>
EXIO_DATA
FB_CLAMP
WRST#
12
GC6@
GC6@
RXE30_0402_ 5%
RXE30_0402_ 5%
2
4
3
5
6
7
8
9
10
11
14
KBL_DET# CHG_MOD
15
U80
U80
GPIO_DATA
GPIO_CLK
CYCLE_START
RESET#
GPIO4
GPIO5
GPIO7
GPIO9
GPIO11
GPIO13
GPIO18
GPIO20
25
1
12
VSS1
VSS2
VSTBY2
VSTBY1
GPIO35
GPIO33
GPIO31
GPIO29
GPIO27
GPIO26
GPIO24
GPIO22
GND
IT8302FN
IT8302FN
IT7230BFN-BX-0001_QFN24_4X4
IT7230BFN-BX-0001_QFN24_4X4
@
@
24
13
23
21
22
20
19
18
17
16
RXE1 0_0603_5%
CHG_MOD <50,54>
For USB charge
+3VALW_R
S_GC6_EN <27,32>
S_GC6_EVENT# <32>
S_DGPU_PWROK <16,32>
S_DGPU_PWR_EN <19,32,55>
S_DGPU_RST <16,32>
S_NVDD_PWR_EN <19,32>
T178PAD @T178PAD @
SLI_FB_Clamp
FB_clamp_req
GPU_PWR_GOOD
GPU_PWR_EN
PEX REST
DGPU_HOLD_RST#
GC6_EVENT# S_GC6_EVENT #
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
2012/07/01
2012/07/01
2012/07/01
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
1 2
RXE14 0_0402_5%
RXE14 0_0402_5%
@
@
Deciphered Date
Deciphered Date
Deciphered Date
2014/07/01
2014/07/01
2014/07/01
Title
Title
Title
EX IO
EX IO
EX IO
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Date: Sheet of
Date: Sheet of
Date: Sheet of
Wednesday, March 27, 2013
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
54 69
54 69
54 69
1.0
1.0
1.0
A
B
C
D
E
+5VALW to +5VS
AP4800BGM
VGS=10V, ID=9A, Rds=18m ohm
VGS=+-25V
+5VALW
U46
U46
8
7
C836
C836
@
@
10U_0805_10V6K
10U_0805_10V6K
PM_SLP_SUS#
LAN_WAKE#
1
2
PCH_PWR_EN<46,57>
6
5
PCH_PWR_EN#_R
PM_SLP_SUS#
1 1
2 2
通通
3 3
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+5VS
1
2
1
3
C837
C837
10U_0603_6.3V6M
10U_0603_6.3V6M
1 2
82K_0402_5%
82K_0402_5%
1 2
R60
100K_0402_5%
100K_0402_5%
1 2
R_short 0_0402_5%
R_short 0_0402_5%
R1448
0_0402_5%
0_0402_5%
R1453
R1453
0_0402_5%
0_0402_5%
+5VALW
2
R1088
R1088
820K_0402_5%
820K_0402_5%
DS3@R60
DS3@
R117
R117
@R1448
@
100K_0402_5%
100K_0402_5%
@
@
1
C43
C43
2
AP4800BGM-HF
AP4800BGM-HF
4
1
C842
C842
0.01U_0402_25V7K
0.01U_0402_25V7K
2
PCH_PWR_EN
Power 修修58頁,
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C44
C44
2
R1484
R1484
PCH_PWR_EN#
12
12
PCH_PWR_EN#_RLAN_WAKE#
5VS_GATE5VS_GATE_R
12
@
@
100K_0402_5%
100K_0402_5%
12
R1121
反反
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C838
C838
1U_0603_10V4Z
1U_0603_10V4Z
2
R1085
R1085
150K_0402_5%
150K_0402_5%
13
D
D
2
SUSP
G
G
Q99
Q99
S
S
2N7002KW_SOT323-3
2N7002KW_SOT323-3
+5VALW
12
R1120
R1120
DS3@
DS3@
13
DS3@
DS3@
D
D
2
Q118
Q118
G
2N7002_SOT23
G
2N7002_SOT23
S
S
DS3@R1121
DS3@
+5VS +3VS
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C42
C42
2
12
R1475
R1475
@
@
470_0603_5%
470_0603_5%
+VSB +VSB
13
D
D
2
G
G
S
S
0.1U_0402_16V4Z
0.1U_0402_16V4Z
PCH_PWR_EN#_RPCH_PWR_EN#_R
1
C45
C45
2
@
@
Q101
Q101
2N7002KW_SOT323-3
2N7002KW_SOT323-3
+3VALW to +3VS
AP4800BGM
VGS=10V, ID=9A, Rds=18m ohm
VGS=+-25V
+3VALW
U47
U47
8
7
1
6
5
C839
@ C839
@
2
10U_0805_10V6K
10U_0805_10V6K
+3VALW to +3V_PCH
+3VALW +3V _PCH
C1065
C1065
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
@
@
J11
@J11
@
112
JUMP_43X79
JUMP_43X79
Q148
Q148
AO3413_SOT23
AO3413_SOT23
D
S
D
S
13
G
G
2
1
C39
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
C40
C40
2
2
@C39
@
0.1U_0402_16V4Z
0.1U_0402_16V4Z
AP4800BGM-HF
AP4800BGM-HF
4
1
C843
C843
0.01U_0402_25V7K
0.01U_0402_25V7K
2
Id=3.2A
1
C1066
@ C1066
@
0.01U_0402_25V7K
0.01U_0402_25V7K
2
+3VS
1
2
3
R1089
R1089
1 2
R_short 0_0402_5%
R_short 0_0402_5%
+3VL+3VALW
1
C41
C41
2
1
C840
C840
10U_0603_6.3V6M
10U_0603_6.3V6M
2
R1483
R1483
820K_0402_5%
820K_0402_5%
C46
C46
1
2
3VS_GATE3VS_GATE_R
12
@
@
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
C841
C841
1U_0603_10V4Z
1U_0603_10V4Z
For ESD request
R1086
R1086
12
470K_0402_5%
470K_0402_5%
13
D
D
2
SUSP
G
G
Q100
Q100
S
S
2N7002KW_SOT323-3
2N7002KW_SOT323-3
+3VS to +3VS_VGA
DGPU_PWR_EN<14,23,54>
R1474
R1474
470_0603_5%
470_0603_5%
2
G
G
12
@
@
13
D
D
@
@
Q102
Q102
2N7002KW_SOT323-3
2N7002KW_SOT323-3
S
S
R1452
R1452
1 2
R_short 0_0402_5%
R_short 0_0402_5%
100K_0402_5%
100K_0402_5%
R1449
R1449
47K_0402_5%
47K_0402_5%
DGPU_PWR_EN#
2
G
G
Q146
Q146
12
2N7002KW_SOT323-3
2N7002KW_SOT323-3
R1454
R1454
+5VALW
12
13
D
D
S
S
SUSP<10,40,61>
SUSP#<32,46,60,61,62>
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
0.1U_0402_16V4Z
0.1U_0402_16V4Z
R1451
R1451
1 2
10K_0402_5%
10K_0402_5%
0.1U_0402_10V7K
0.1U_0402_10V7K
C1058
C1058
C1011
C1011
+5VALW +0.675VS
R1097
R1097
100K_0402_5%
100K_0402_5%
SUSP
2
G
G
Q107A
Q107A
+3VS
Q145
Q145
AO3413_SOT23
AO3413_SOT23
S
S
1
G
G
@
@
2
2
1
2
12
61
D
D
S
S
12
34
D
D
S
S
R1094
R1094
22_0603_5%
22_0603_5%
For Intel S3 Pow er Reduction.
+3VS_VGA
D
D
13
1
C1059
C1059
@
@
0.01U_0402_25V7K
0.01U_0402_25V7K
2
DGPU_PWR_EN#
2N7002KW_SOT323-3
2N7002KW_SOT323-3
R1450
470_0603_5%
470_0603_5%
2
G
G
5
SUSP
G
G
Q107B
Q107B
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
12
1
@R1450
@
2
13
D
D
@
@
Q149
Q149
S
S
C37
C37
10U_0603_6.3V6M
10U_0603_6.3V6M
For ESD request
+3VS to +3VS_SLI
+3VS
2012-0419 --> mo dify +3VS_SLI B OM structure to "SLI@"
+5VALW
@
12
R1502
R1502
47K_0402_5%
12
R1503
R1503
2N7002KW_SOT323-3
2N7002KW_SOT323-3
R1501
R1501
100K_0402_5%
100K_0402_5%
47K_0402_5%
2
G
G
Q150
Q150
12
13
D
D
S
S
4 4
S_DGPU_PWR_EN<19,32,54>
S_DGPU_PWR_EN#<32>
A
R_short 0_0402_5%
R_short 0_0402_5%
@
0.1U_0402_16V4Z
0.1U_0402_16V4Z
R1513
R1513
1 2
10K_0402_5%
10K_0402_5%
0.1U_0402_10V7K
0.1U_0402_10V7K
C1062
C1062
C1012
C1012
1
2
1
2
Q147
Q147
AO3413_SOT23
AO3413_SOT23
D
S
D
S
13
G
G
2
S_DGPU_PWR_EN#
B
+3VS_SLI
1
@
@
C1063
C1063
0.01U_0402_25V7K
0.01U_0402_25V7K
2
470_0603_5%
470_0603_5%
2N7002KW_SOT323-3
2N7002KW_SOT323-3
R1500
2
G
G
12
2
@R1500
@
C48
C48
10U_0603_6.3V6M
10U_0603_6.3V6M
1
13
D
D
@
@
Q151
Q151
S
S
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
C
2012/07/01
2012/07/01
2012/07/01
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
2014/07/01
2014/07/01
2014/07/01
Title
Title
Title
DC V TO VS INTERFACE
DC V TO VS INTERFACE
DC V TO VS INTERFACE
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Date: Sheet of
Date: Sheet of
Date: Sheet of
Wednesday, March 27, 2013
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
Y501 NM-A032Y501 NM-A032
E
55 69
55 69
55 69
1.0
1.0
1.0
5
4
3
2
1
12
@
@
2
13
12
PR109
PR109
200_0603_5%@
200_0603_5%@
12
PC108
PC108
1U_0805_25V6K
1U_0805_25V6K
@
@
VIN
SLI@
SLI@
PQ102
PQ102
AON7403L_DFN8-5
AON7403L_DFN8-5
12
100P_0402_50V8J
100P_0402_50V8J
1000P_0402_50V7K
1000P_0402_50V7K
PC104
PC104
PC103
PC103
PR110
PR110
200K_0402_1%
200K_0402_1%
SLI@
SLI@
1 2
VIN
PD101
PD101
LL4148_LL34-2
LL4148_LL34-2
1 2
51ON-1
12
12
@
@
@
@
PR102
PR102
PR101
PR101
68_1206_5%
68_1206_5%
68_1206_5%
68_1206_5%
SLI_B+_ON#<32> SLI_5V_ON#<32>
1
3
4
SLI@
SLI@
PC109
PC109
1 2
0.22U_0603_25V7K
0.22U_0603_25V7K
PR113
PR113
47K_0402_1%
47K_0402_1%
SLI@
SLI@
1 2
B+_SLIB+
52
12
SLI@
SLI@
PC110
PC110
0.1U_0603_25V7K
0.1U_0603_25V7K
200K_0402_1%
200K_0402_1%
+5VS to +5VS_SLI
JUMP_43X79
1
2
PQ103
PQ103
JUMP_43X79
PJ102
PJ102
112
AO6409L_TSOP6
AO6409L_TSOP6
4
SLI@
SLI@
PC111
PC111
0.1U_0402_16V4Z
0.1U_0402_16V4Z
S
S
+5VS +5VS_SLI
PR111
PR111
SLI@
SLI@
1 2
2
G
G
3
PR112
47K_0402_1%
47K_0402_1%
1 2
@
@
D
D
SLI@
SLI@
6
5
2
1
PC112
PC112
SLI@PR112
SLI@
0.01U_0402_16V7K
0.01U_0402_16V7K
SLI@
SLI@
1
2
1
PC113
PC113
10U_0603_6.3V6M
10U_0603_6.3V6M
2
SLI@
SLI@
VS
12
PC106
PC106
@
@
0.1U_0603_25V7K
0.1U_0603_25V7K
JRTC1
JRTC1
- +
MAXEL_ML1220T10@
MAXEL_ML1220T10@
PR106
PR106
560_0603_5%
560_0603_5%
12
1 2
PR107
PR107
560_0603_5%
560_0603_5%
1 2
PD103
PD103
12
+RTCBATT
RB751V-40_SOD323-2
RB751V-40_SOD323-2
1 2
RB751V-40_SOD323-2
RB751V-40_SOD323-2
PD104
PD104
+CHGRTC
RTC Battery
DC030006J00
PL101
PF101
PF101
12A_65V_451012MRL
12A_65V_451012MRL
BATT+
51_ON#<53>
21
APDIN1APDIN
PR103
@PR103
@
200_0402_1%
200_0402_1%
1 2
@
@
PD102
PD102
LL4148_LL34-2
LL4148_LL34-2
PR105
@PR105
@
22K_0402_1%
22K_0402_1%
1 2
+CHGRTC
12
PC101
PC101
12
@
@
12
PR104
PR104
3.3V
12
PC107
PC107
10U_0603_6.3V6M
10U_0603_6.3V6M
@
@
4
4
3
3
2
4602-Q04C-09R 4P P2.5@
4602-Q04C-09R 4P P2.5@
JDCIN1
JDCIN1
2
1
1
D D
C C
+3VLP
PR108
PR108
0_0402_5%
0_0402_5%
1 2
B B
PL101
SMB3025500YA_2P
SMB3025500YA_2P
1 2
12
100P_0402_50V8J
100P_0402_50V8J
1000P_0402_50V7K
1000P_0402_50V7K
PC102
PC102
51ON-2
@
@
PC105
PC105
1 2
0.22U_0603_25V7K
0.22U_0603_25V7K
100K_0402_1%
100K_0402_1%
51ON-3
PU101
@PU101
@
APL5156-33DI-TRL_SOT89-3
APL5156-33DI-TRL_SOT89-3
3
VOUT
PJ101
PJ101
JUMP_43X39@
JUMP_43X39@
112
@ PQ101
@
TP0610K-T1-E3_SOT23-3
TP0610K-T1-E3_SOT23-3
2
CHGRTCIN
VIN
GND
1
PQ101
2
A A
Title
Title
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
3
2012/07/01
2012/07/01
2012/07/01
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2014/07/01
2014/07/01
2014/07/01
Title
Vin Detector
Vin Detector
Vin Detector
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032Y510 NM-A032
Y510 NM-A032Y510 NM-A032
Y510 NM-A032Y510 NM-A032
1
56 69
56 69
56 69
1.0
1.0
1.0
5
4
3
2
1
JBATT1
VMB2
JBATT1
1
1
2
2
3
EC_SMCA
3
4
EC_SMDA
4
5
D D
C C
5
6
6
7
7
8
GND
9
GND
TYCO_1775789-1
TYCO_1775789-1
@
@
+3VALW
12
PR201
PR201
PR227
PR227
100_0402_1%
100_0402_1%
PR228
PR228
12
PR202
100_0402_1%
PR202
100_0402_1%
100K_0402_5%
100K_0402_5%
100K_0402_5%47W @
100K_0402_5%47W @
1 2
PR203
PR203
6.49K_0402_1%
6.49K_0402_1%
1 2
PR204
PR204
10K_0402_5%
10K_0402_5%
12
12
PF201
PF201
12A_65V_451012MRL
12A_65V_451012MRL
21
3V--- 90W
1.5V--- 120W
0V--- 170W
AD_ID <47>
VMB
+3VALW
PL201
PL201
SMB3025500YA_2P
SMB3025500YA_2P
1 2
12
PC201
PC201
1000P_0402_50V7K
1000P_0402_50V7K
EC_SMB_CK1 < 34,47,51,59>
EC_SMB_DA1 < 34,47,51,59>
BATT_TEMP <47>
BATT+
12
PC202
PC202
0.01U_0402_25V7K
0.01U_0402_25V7K
PH1 under CPU botten side :
CPU thermal protection at 92+-3 degree C
Recovery at 56 +-3 degree C
VL
12
PC207
PC207
@
@
+3VS
0.1U_0603_25V7K
H_PROCHOT#<6 ,47>
PQ201
PQ201
@
2N7002KW_SOT323-3@G
2N7002KW_SOT323-3
PROCHOT#<47>
0.1U_0603_25V7K
@
@
PR218
PR218
1 2
13
D
D
S
S
2
ADP_OCP_1
G
PR219
0_0402_5%
0_0402_5%
1 2
100K_0402_1%
100K_0402_1%
@PR219
@
OTP_N_003
0_0402_5%
0_0402_5%
1
2
3
4
@
@
PR220
PR220
PU201
PU201
VCC
TMSNS1
GND
RHYST1
OT1
TMSNS2
RHYST2
OT2
G718TM1U_SOT23-8
G718TM1U_SOT23-8
@
@
12
For KB930 --> Keep PU1 circuit
(Vth = 0.825V)
For KB9012 (Red square) --> Remove PU201 circuit, but
PH201, PR205,PR211,PQ201,PR208,PR212
ADP_I<47,59>
PR222
TURBO_V_1
PR221
PR221
57.6K_0402_1%@
57.6K_0402_1%@
PR222
1 2
8
7
OTP_N_002
6
5
ADP_OCP_2
MAINPWON <47,60>
PR221
57.6K:90W
82.5K:120W
76.8K:170W
1 2
4.42K_0402_1%
4.42K_0402_1%
PR222
4.42K:90W
9.1K:120W
16.5K:170W
PR223
PR223
PR231
0_0402_5%
PR231
0_0402_5%
10K_0402_1%
10K_0402_1%
1 2
1 2
TURBO_V
<47>
NTC_V_1
PR224
PR224
10K_0402_1%
10K_0402_1%
@
@
+3VLP
12
12
1 2
NTC_V
<47>
keep PR206
12
PR226
PR225
PR225
13.7K_0402_1%
13.7K_0402_1%
PR230
0_0402_5%
PR230
0_0402_5%
PR226
@
@
21.5K_0402_1%
21.5K_0402_1%
12
PH201
PH201
100K_0402_1%_NCP15WF104F03RC
100K_0402_1%_NCP15WF104F03RC
B B
VMB2
PR205
PR205
255K_0402_1%
255K_0402_1%
PR229
PR229
10K_0402_1%
10K_0402_1%
1 2
1 2
PR206
PR206
150K_0402_1%
150K_0402_1%
1 2
A A
5
12
P2
PC203
PC203
0.01U_0402_25V7K
0.01U_0402_25V7K
8
3
P
+
2
-
G
4
PR207
PR207
10K_0402_1%
10K_0402_1%
PR209
PR209
10M_0402_5%
10M_0402_5%
1 2
1
O
PU202A
PU202A
AS393MTR-E1 SO 8P OP
AS393MTR-E1 SO 8P OP
12
+CHGRTC
BATT_LEN#<47>
PR210
PR210
1 2
100K_0402_1%
100K_0402_1%
2N7002KW_SOT323-3
2N7002KW_SOT323-3
PR213
PR213
10K_0402_1%
10K_0402_1%
PQ203
PQ203
2
G
G
+3VALW
PR212
PR212
12
PR211
PR211
1 2
+3VALW+3VALW
1 2
100K_0402_1%
100K_0402_1%
13
D
D
S
S
100K_0402_1%
100K_0402_1%
2
G
G
4
BATT_OUT <59>
PQ205
PQ205
13
D
D
2N7002KW_SOT323-3
2N7002KW_SOT323-3
S
S
PQ202
PQ202
TP0610K-T1-E3_SOT23-3
TP0610K-T1-E3_SOT23-3
B+
+3VL
PR214
@PR214
@
200K_0402_1%
200K_0402_1%
PR215
@PR215
@
0_0402_5%
0_0402_5%
SPOK<60>
PCH_PWR_EN<47,56>
1 2
PR232
PR232
0_0402_5%
0_0402_5%
1 2
PR233
PR233
1 2
1K_0402_1%
1K_0402_1%
1 2
12
PC204
PC204
1U_0402_6.3V6K
1U_0402_6.3V6K
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
3
2
G
G
22K_0402_1%
22K_0402_1%
13
D
D
S
S
2012/07/01
2012/07/01
2012/07/01
12
PR217
PR216
PR216
1 2
PQ204
PQ204
2N7002KW_SOT323-3
2N7002KW_SOT323-3
PR217
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
12
PC205
PC205
100K_0402_1%
100K_0402_1%
0.22U_0603_25V7K
0.22U_0603_25V7K
Deciphered Date
Deciphered Date
Deciphered Date
13
2
2014/07/01
2014/07/01
2014/07/01
2
12
PC206
PC206
0.1U_0603_25V7K
0.1U_0603_25V7K
+VSBP
+VSBP
PJ201
PJ201
JUMP_43X39@
JUMP_43X39@
2
112
Title
Title
Title
BATTERY CONN/OTP
BATTERY CONN/OTP
BATTERY CONN/OTP
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Wednesday, March 27, 2013
+VSB
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032Y510 NM-A032
Y510 NM-A032Y510 NM-A032
Y510 NM-A032Y510 NM-A032
1
57 69
57 69
57 69
1.0
1.0
1.0
5
4
3
2
1
Charge Option() bit[8]=1
PQ301
PQ301
AO4423L 1P SO8
AO4423L 1P SO8
DTA144EUA_SC70-3
DTA144EUA_SC70-3
13
2
PQ305A
PQ305A
PQ306
PQ306
DTC115EUA_SC70-3
DTC115EUA_SC70-3
PR306
PR306
1 2
10K_0402_5%
10K_0402_5%
PQ307B
PQ307B
8
7
5
PQ303
PQ303
2
1 3
PQ304
PQ304
DTC115EUA_SC70-3
DTC115EUA_SC70-3
PR305
PR305
47K_0402_1%
47K_0402_1%
1 2
2
ACOFF-1
12
PR307
PR307
0_0402_5%
0_0402_5%
34
5
4
VIN
D D
12
PR301
PR301
200K_0402_5%
200K_0402_5%
61
2
2N7002KDW -2N_SOT363-6
2N7002KDW -2N_SOT363-6
C C
PACIN
ACOFF<47>
B B
BATT_OUT
2N7002KDW -2N_SOT363-6
2N7002KDW -2N_SOT363-6
1
2
36
12
150K_0402_1%
150K_0402_1%
5
13
P2
PC301
PC301
0.1U_0603_25V7K
0.1U_0603_25V7K
PQ305B
PQ305B
12
PR302
PR302
P2-1
12
PR304
PR304
P2-2
34
2N7002KDW-2N_SOT363-6
2N7002KDW-2N_SOT363-6
EC_SMB_DA1
<41,47,51,58>
EC_SMB_CK1
<41,47,51,58>
PQ302
PQ302
AO4423L 1P SO8
AO4423L 1P SO8
1
2
3 6
4
200K_0402_1%
200K_0402_1%
12
PR303
PR303
20K_0402_1%
20K_0402_1%
61
PQ307A
PQ307A
2N7002KDW -2N_SOT363-6
2N7002KDW -2N_SOT363-6
2
PR309
PR309
64.9K_0603_1%
64.9K_0603_1%
1 2
PC304 .1U_0603_25V7KPC304 .1U_0603_25V7K
2200P_0402_50V7K
2200P_0402_50V7K
0.1U_0603_25V7K
0.1U_0603_25V7K
PR308
PR308
12
+3VALWP
8
7
5
PC302
PC302
1 2
1 2
PC303
@PC303
@
VIN
12
390K_0603_1%
390K_0603_1%
PR310
PR310
0_0402_5%
0_0402_5%
1 2
PR311
PR311
0_0402_5%
0_0402_5%
1 2
P3
BATT_OUT <58>
PR312
PR312
1 2
147K_0402_1%
147K_0402_1%
PR313
PR313
100K_0402_1%
100K_0402_1%
ADP_I<4 7,59>
PC305
PC305
1 2
100P_0603_50V8
100P_0603_50V8
12
PR314
39.2K_0402_1%
39.2K_0402_1%
6
7
8
9
10
PR318
PR318
18K_0402_1%
18K_0402_1%
<60>
ACPRN
@PR314
@
ACDET
IOUT
SDA
SCL
ILIM
12
+3VALWP
12
@PR315
@
PR317
PR317
PR315
100K_0402_1%
100K_0402_1%
PR316
@PR316
@
1 2
12
1 2
4.7M_0603_1%
4.7M_0603_1%
3
4
5
ACOK
CMPIN
PU301
PU301
BQ24737RGRR_VQFN20_ 3P5X3P5
BQ24737RGRR_VQFN20_ 3P5X3P5
SRN12BM
12
13
11
12
BM#
PR319
PR319
6.8_0603_5%
6.8_0603_5%
PC307
PC307
0.1U_0603_25V7K
0.1U_0603_25V7K
12
12
12
PC306
PC306
0.1U_0603_25V7K
0.1U_0603_25V7K
1
2
ACP ACN
PC313
PC313
1 2
PC311
PC311
0.1U_0603_25V7K
0.1U_0603_25V7K
10K_0603_1%@
10K_0603_1%@
2
ACP
CMPOUT
GND
SRP
14
PR320
PR320
10_0603_5%
10_0603_5%
PC324
PC324
@
@
0.1U_0603_25V7K
0.1U_0603_25V7K
PR3270.01_2512_1% PR3270.01_2512_1%
0.1U_0603_25V7K
0.1U_0603_25V7K
12
1
15
ACPRN
ACN
PHASE
HIDRV
REGN
LODRV
B+
1UH_PCMB061H-1R0M S_7A_20%
1UH_PCMB061H-1R0M S_7A_20%
4
3
PC323
PC323
PC312
PC312
12
0.1U_0603_25V7K
0.1U_0603_25V7K
21
TP
20
VCC
19
18
17
BTST
16
12
PR328
PR328
47K_0402_1%
47K_0402_1%
PL302
PL302
1 2
1 2
10U_0805_25V6K@
10U_0805_25V6K@
PR321
PR321
10_1206_5%
10_1206_5%
1 2
DH_CHG
BST_CHG
PD301
PD301
RB751V-40_SOD323-2
RB751V-40_SOD323-2
12
BQ24737_VDD
12
PC308
PC308
1U_0603_25V6
1U_0603_25V6
DL_CHG
BQ24737_VDD
12
PR329
PR329
10K_0402_1%
10K_0402_1%
34
PQ308B
PQ308B
5
1 2
P2
PC310
PC310
1 2
1U_0603_25V6
1U_0603_25V6
PR322
PR322
2.2_0603_5%
2.2_0603_5%
1 2
PC322
PC322
10U_0805_25V6K@
10U_0805_25V6K@
LX_CHG
0.047U_0603_16V7K
0.047U_0603_16V7K
PR330
PR330
10K_0402_1%
10K_0402_1%
1 2
12
PR331
PR331
12K_0402_1%
12K_0402_1%
1 2
PACIN
1 2
PC321
PC321
4.7U_0805_25V6-K
4.7U_0805_25V6-K
AON7408L_DFN8-5
AON7408L_DFN8-5
PC309
PC309
CHG_B+
PQ310
PQ310
AO4423L 1P SO8
AO4423L 1P SO8
1
2
3 6
PC318
PC318
1 2
1 2
PC319
PC319
PC320
PC320
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
PQ311
PQ311
4
12
4
ACIN <47>
DISCHG_G
2200P_0402_50V7K
2200P_0402_50V7K
PR326
PR326
10K_0402_1%
10K_0402_1%
1 2
DISCHG_G-1
13
DTC115EUA_SC70-3
DTC115EUA_SC70-3
5
123
4.7UH_PCMB104E-4R 7MS_10A_20%
4.7UH_PCMB104E-4R 7MS_10A_20%
5
PQ312
PQ312
AON7702L_DFN8-5
AON7702L_DFN8-5
123
PR325
PR325
47K_0402_1%
47K_0402_1%
1 2
PQ309
PQ309
2
12
6251_SN
12
PL301
PL301
1 2
PR323
PR323
4.7_1206_5%
4.7_1206_5%
PC314
PC314
680P_0603_50V7K
680P_0603_50V7K
ACOFF-1
PD303
PD303
1SS355_SOD323-2
1SS355_SOD323-2
1 2
1 2
CHGCHG
4
1 2
PD302
PD302
1SS355_SOD323-2
1SS355_SOD323-2
12
PC317
PC317
0.1U_0603_25V7K
0.1U_0603_25V7K
PR332
PR332
0.01_2512_1%
0.01_2512_1%
1
2
8
7
5
PR324
PR324
200K_0402_1%
200K_0402_1%
61
PQ308A
PQ308A
2N7002KDW -2N_SOT363-6
2N7002KDW -2N_SOT363-6
2
4
3
VIN
PACIN
PC315
PC315
BATT+
12
12
PC316
PC316
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
A A
Security Classifi cation
Security Classifi cation
Security Classifi cation
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF LC FUTURE CENTER.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF LC FUTURE CENTER.
3
2012/07/01
2012/07/01
2012/07/01
2N7002KDW-2N_SOT363-6
2N7002KDW-2N_SOT363-6
For disable pre- charge circuit.
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2014/07/01
2014/07/01
2014/07/01
2
Title
Title
Title
CHARGER
CHARGER
CHARGER
Size D ocument Number Rev
Size D ocument Number Rev
Size D ocument Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032Y510 NM-A032
Y510 NM-A032Y510 NM-A032
Y510 NM-A032Y510 NM-A032
58 69
58 69
58 69
1
1.0
1.0
1.0
5
D D
4
PR401
PR401
13K_040 2_1%
13K_040 2_1%
1 2
PC410
PC410
0.1U_040 2_25V6
0.1U_040 2_25V6
1 2
1 2
@
@
PR403
PR403
20K_040 2_1%
20K_040 2_1%
+3VL
PR406
PR406
0_0603_5%~D
0_0603_5%~D
3
@
@
PC422
PC422
0.1U_040 2_25V6
0.1U_040 2_25V6
1 2
PR411
12
PC418
PC418
1 2
1U_0603_10V6K
1U_0603_10V6K
PR411
30K_040 2_1%
30K_040 2_1%
1 2
PR408
PR408
20K_040 2_1%
20K_040 2_1%
1 2
2
PJ401
PJ401
+3VALW P + 3VALW
+5VALW P + 5VALW
2
JUMP_43 X118@
JUMP_43 X118@
PJ402
PJ402
2
JUMP_43 X118@
JUMP_43 X118@
1
112
112
+3VLP
PR405
PR405
130K_04 02_1%
<58>
SPOK
PC423
PC423
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
130K_04 02_1%
PR402
PR402
2.2_0603 _5%
2.2_0603 _5%
1 2
B++
PU401
PU401
6
7
10
9
8
Issued Date
Issued Date
Issued Date
FB_3V
4
5
CS2
EN2
PGOOD
TPS5122 5CRUKR_QFN20 _3X3
TPS5122 5CRUKR_QFN20 _3X3
DRVH2
VBST2
SW2
DRVL211VIN12VREG5
12
PC411
PC411
0.1U_0603_25V7K
0.1U_0603_25V7K
1 2
3V_EN
UG_3V
BST_3V
SW2_ 3V
LG_3V
Security Class ification
Security Class ification
Security Class ification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
FB_5V
2
3
VREG3
13
3
VFB1
EN1
20
5V_EN
12
PC421
PC421
1U_0603_10V5K
1U_0603_10V5K
2012/07/ 01
2012/07/ 01
2012/07/ 01
VFB2
B++
PJ403
PJ403
2
B+
PC405
PC405
0.1U_0603_25V7K
C C
0.1U_0603_25V7K
+3VALWP
B B
A A
112
JUMP_43 X118@
JUMP_43 X118@
12
PC409
PC409
330U_D2E_6.3VM_R25M
330U_D2E_6.3VM_R25M
12
PC401
PC401
0.1U_0603_25V7K
0.1U_0603_25V7K
3.3UH +-20 % PCMB063T-3R3M S 6.5A
3.3UH +-20 % PCMB063T-3R3M S 6.5A
1
+
+
2
5
12
PC402
PC402
4.7U_0805_25V6-K
4.7U_0805_25V6-K
PL402
PL402
<47,53>
EC_ON
<47,58>
MAINPW ON
VL
12
PC403
PC403
PC404
PC404
4.7U_0805_25V6-K
4.7U_0805_25V6-K
12
PR409
PR409
PC412
PC412
PR419
100K_04 02_5%
100K_04 02_5%
LL4148_ LL34-2
LL4148_ LL34-2
VS
2200P_0402_50V7K
2200P_0402_50V7K
4.7_1206_5%
4.7_1206_5%
680P_0603_50V7K
680P_0603_50V7K
@P R419
@
12
12
SNUB_3V
12
12
PD402
@P D402
@
123
2
G
G
12
316K_04 02_1%
316K_04 02_1%
1 2
241
3V_EN
5V_EN
13
D
D
S
S
1M_0402 _1%
1M_0402 _1%
1 2
6
578
PQ401
PQ401
AO4466L _SO8
AO4466L _SO8
4
578
PQ403
PQ403
AO4712_ SO8
AO4712_ SO8
3 6
PR413
PR413
2.2K_040 2_5%
2.2K_040 2_5%
1 2
PD401
PD401
LL4148_ LL34-2
LL4148_ LL34-2
1 2
1 2
PR420
@P R420
@
330_040 2_5%
330_040 2_5%
PQ405
@
PQ405
@
2N7002K W_SOT323-3
2N7002K W_SOT323-3
PR416
@P R416
@
PR418
PR418
@
@
PC413
PC413
0.1U_060 3_25V7K
0.1U_060 3_25V7K
1 2
1 2
PR414 0 _0402_5%PR414 0_0 402_5%
1 2
PR415 0 _0402_5%PR415 0_0 402_5%
12
12
PR417
PR417
402K_0402_1%
402K_0402_1%
4
PR407
PR407
56K_040 2_1%
56K_040 2_1%
1 2
1
21
CS1
PAD
14
VO1
19
VCLK
16
DRVH1
DRVL1
15
VBST1
SW1
PR404
PR404
UG_5V
17
BST_5V
18
SW1_ 5V
LG_5V
1 2
0_0603_5%~D
0_0603_5%~D
VL
3VALWP
Imax=7.5A
OCP current 8.6A~13.92A
TYP MAX
H/S Rds(on): 22mohm , 30mohm
L/S Rds(on):10.8mohm ,13.6mohm
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
PR410
PR410
2.2_0603 _5%
2.2_0603 _5%
1 2
PC415
PC415
0.1U_060 3_25V7K
0.1U_060 3_25V7K
1 2
AO4456_ SO8
AO4456_ SO8
2014/07/ 01
2014/07/ 01
2014/07/ 01
2
4
578
3 6
5
PC414
PC414
PQ402
PQ402
AO4406A L_SO8
AO4406A L_SO8
241
4.7UH_VM PI1004AR-4R7M-Z01 _10A_20%
4.7UH_VM PI1004AR-4R7M-Z01 _10A_20%
786
PQ404
PQ404
PR412
PR412
123
PC416
PC416
5VALWP
Imax=10A
OCP current 11.5~19.5A
TYP MAX
H/S Rds(on):22mohm , 30mohm
L/S Rds(on):10.8mohm , 13.6mohm
Title
Title
Title
3VALWP/5VALWP
3VALWP/5VALWP
3VALWP/5VALWP
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
B++
12
12
PC420
PC420
PC419
PC419
0.1U_0402_25V6
0.1U_0402_25V6
2200P_0402_50V7K
2200P_0402_50V7K
PL401
PL401
1 2
12
4.7_1206_5%
4.7_1206_5%
SNUB_5V
12
680P_0603_50V7K
680P_0603_50V7K
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Wednesday, March 27, 2013
12
12
PC417
PC417
@
@
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
PC408
PC408
330U_D2E_6.3VM_R25M
330U_D2E_6.3VM_R25M
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032Y510 NM-A032
Y510 NM-A032Y510 NM-A032
Y510 NM-A032Y510 NM-A032
1
1
+
+
2
+5VALWP
59 69
59 69
59 69
1.0
1.0
1.0
PL501
PL501
HCB1608KF-121T30_0603
HCB1608KF-121T30_0603
1 2
B+
1 1
+1.35VP
2 2
A
B+_1.35V
12
12
12
PC503
PC503
PC502
PC502
PC501
PC501
0.1U_0402_25V6
0.1U_0402_25V6
68P_0402_50V8J
68P_0402_50V8J
PL502
1
2
330U_D2_2.5VY_R15M
330U_D2_2.5VY_R15M
PL502
1 2
2.2UH_VMPI0703AR-2R2M -Z01_8A_20%
2.2UH_VMPI0703AR-2R2M -Z01_8A_20%
+
+
PC506
PC506
2200P_0402_50V7K
2200P_0402_50V7K
12
PC504
PC504
12
PR501
PR501
4.7_1206_5%
4.7_1206_5%
SNB_1.35V
12
PC507
PC507
12
PC505
PC505
10U_0805_25V6K
10U_0805_25V6K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
PQ501
PQ501
SIS472DN-T1-GE3
SIS472DN-T1-GE3
3 5
241
PQ502
PQ502
3 5
241
SISA12DN-T1-GE3
SISA12DN-T1-GE3
680P_0603_50V7K
680P_0603_50V7K
B
PR502
PR502
5.1_0603_5%
5.1_0603_5%
1 2
+5VALW
12
<47>
VDDQ_PGOOD
PC510
PC510
0.22U_0402_10V6K
0.22U_0402_10V6K
1 2
PR503
PR503
20.5K_0402_1%
20.5K_0402_1%
1 2
PC508
PC508
1U_0603_10V6K
1U_0603_10V6K
PR505
PR505
0_0402_5%
0_0402_5%
1 2
DL_1.35V
CS_1.35V
VDDP_1.35V
VDD_1.35V
12
PC509
PC509
1U_0603_10V6K
1U_0603_10V6K
+3VS
B+_1.35V
PR504
PR504
2.2_0603_5%
2.2_0603_5%
1 2
15
14
13
12
11
PR531
PR531
0_0402_5%
0_0402_5%
PR532
PR532
10K_0402_5%
10K_0402_5%
PR506
PR506
887K_0402_1%
887K_0402_1%
1 2
DH_1.35V
LX_1.35V
17
16
PHASE
LGATE
PGND
CS
VDDP
VDD
12
12
UGATE
RT8207MZQW _WQFN20_3X3
RT8207MZQW _WQFN20_3X3
PGOOD
TON
9
10
TON_1.35V
C
D
+1.35VP
+0.675VSP
PJ501
1
VIN_1.35V
VIN_0.675V
BST_1.35V
19
18
20
PU501
PU501
21
VTT
BOOT
S5
8
S5_1.35V
PAD
VTTGND
VTTSNS
GND
VTTREF
VDDQ
FB
6
FB_1.35V
1
2
3
4
5
VTTSNS_0.675V
VTTREF_0.675V
VDDQ_1.35V
+1.35VP+5VALW
PR507
PR507
8.06K_0402_1%
8.06K_0402_1%
1 2
PC525
PC525
100P_0402_50V8J
100P_0402_50V8J
1 2
VLDOIN
S3
7
S3_1.35V
1
PC514
PC514
PC515
2
PC515
2
10U_0805_6.3VAM
10U_0805_6.3VAM
10U_0805_6.3VAM
10U_0805_6.3VAM
+1.35VP
+0.675VSP
12
PC513
PC513
0.033U_0402_16V7K
0.033U_0402_16V7K
+1.35VP
PJ501
JUMP_43X118
JUMP_43X118
PJ502
PJ502
2
JUMP_43X39
JUMP_43X39
12
+1.35V
112
+0.675VS
12
PR510
PR510
10K_0402_1%
12
PR516
PR516
100K +-1% 0402
100K +-1% 0402
3 3
4 4
<47>
SYSON
A
12
PR519
PR519
0_0402_5%
0_0402_5%
12
PC518
@PC5 18
@
0.1U_0402_10V7K
0.1U_0402_10V7K
PR514
PR514
0_0402_5%
0_0402_5%
SUSP#<32,47,56,62,63>
SUSP#_PWR<61,62>
B
1 2
PR540
@PR540
@
0_0402_5%
0_0402_5%
1 2
Security Classifi cation
Security Classifi cation
Security Classifi cation
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF LC FUTURE CENTER.
2012/07/01
2012/07/01
2012/07/01
12
PC517
@PC5 17
@
0.1U_0402_10V7K
0.1U_0402_10V7K
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
10K_0402_1%
Deciphered Date
Deciphered Date
Deciphered Date
C
2014/07/01
2014/07/01
2014/07/01
Title
Title
Title
1.35VP/0.675VSP
1.35VP/0.675VSP
1.35VP/0.675VSP
Size D ocument Number Rev
Size D ocument Number Rev
Size D ocument Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032Y510 NM-A032
Y510 NM-A032Y510 NM-A032
Y510 NM-A032Y510 NM-A032
D
60 69
60 69
60 69
of
1.0
1.0
1.0
A
PD502
PD502
RB751V-4 0_SOD323-2
RB751V-4 0_SOD323-2
1 1
2 2
FBVDDQ_ PWR_EN<27>
SUSP#<32,47 ,57,61,62,63>
1 2
PR533
PR533
0_0402_ 5%
0_0402_ 5%
1 2
PR524
PR524
0_0402_ 5%
0_0402_ 5%
1 2
@
@
@
@
@
@
12
PR523
PR523
1 2
1M_0402_1%
1M_0402_1%
PC530
PC530
.1U_0402_16V7K
.1U_0402_16V7K
1 2
12
PR517
PR517
10K_040 2_1%
10K_040 2_1%
B
12
PR526
PR526
75K_0402_1%
75K_0402_1%
PR518
PR518
11.5K_04 02_1%
11.5K_04 02_1%
C
5
PQ504
PQ504
4
PC529
PR529
PR529
2.2_0603 _5%
PU502
PU502
1
2
3
4
5
PR527
PR527
1 2
470K_0402_1%
470K_0402_1%
VBST
PGOOD
TRIP
DRVH
EN
V5IN
VFB
DRVL
RF
TPS5121 2DSCR_SON10_ 3X3
TPS5121 2DSCR_SON10_ 3X3
2.2_0603 _5%
1 2
10
9
8
SW
7
6
11
TP
BST_1.5V SP_VGA-1
12
PC542
PC542
1U_0603 _10V6K
1U_0603 _10V6K
AON6504 _POWERDFN 56-8-5
AON6504 _POWERDFN 56-8-5
PC529
0.22U_06 03_16V7K
0.22U_06 03_16V7K
1 2
+5VALW
PQ505
PQ505
4
MDV1525 URH_PDFN33-8-5
MDV1525 URH_PDFN33-8-5
123
1 2
12
PR521
PR521
@
5
123
@
4.7_1206_5%
4.7_1206_5%
SNUB_1.5V
12
@
@
PC526
PC526
680P_0603_50V7K
680P_0603_50V7K
PL503
PL503
1UH_PCM B063T-1R0MS_1 2A_20%
1UH_PCM B063T-1R0MS_1 2A_20%
12
PC528
PC528
10U_0805_25V6K
10U_0805_25V6K
PC56
PC56
+1.5VSP_ VGA +1.5VS_V GA
12
12
PC536
PC536
10U_0805_25V6K
10U_0805_25V6K
1
+
+
1 2
2
220U_B2_6.3VM_R15M
220U_B2_6.3VM_R15M
12
PC537
PC537
PC538
PC538
0.1U_0402_25V6
0.1U_0402_25V6
2200P_0402_50V7K
2200P_0402_50V7K
PC58
PC58
0.1U_0402_10V7K
0.1U_0402_10V7K
PR525
PR525
0_0402_ 5%
0_0402_ 5%
1 2
PJ504
PJ504
2
JUMP_43 X118@
JUMP_43 X118@
12
112
JUMP_43 X118
JUMP_43 X118
2
PC539
PC539
470P_0603_50V7K
470P_0603_50V7K
D
PJ503
PJ503
112
@
@
+1.5VSP_ VGA
VDDQ_SE NSE
B+
<25>
PR534
PR534
0_0402_ 5%
0_0402_ 5%
12
PU504
PU504
7
POK
8
EN
+5VS
12
PC549
PC549
1U_0402 _6.3V6K
1U_0402 _6.3V6K
6
VIN
VOUT
VCNTL
VOUT
FB
VIN
GND
APL5912 -KAC-TRL_SO8
APL5912 -KAC-TRL_SO8
1
5
4
3
2
9
+3VL
12
PR537
@PR537
@
100K_04 02_5%
100K_04 02_5%
3 3
SUSP<34>
2
G
G
SUSP#_P WR
13
D
D
PQ503
PQ503
2N7002K W_SOT323-3
2N7002K W_SOT323-3
S
S
@
@
<60,62>
SUSP#_P WR
<32,47,56 ,61,62,63>
SUSP#
+5VS
@
@
12
PR536
PR536
0_0402_ 5%
0_0402_ 5%
PR538
@P R538
@
SUSP#_PWR<60,61,62>
1 2
0_0402_ 5%
0_0402_ 5%
PR535
PR535
1 2
0_0402_ 5%
0_0402_ 5%
PC545
PC545
.1U_0603_25V7K
.1U_0603_25V7K
EN_1.5VS P
12
PR520
PR520
20K_040 2_1%
20K_040 2_1%
1 2
VFB=0.8V
4 4
Security Class ification
Security Class ification
Security Class ification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
B
Vo=VFB*(1+PR522/PR539)
2012/07/ 01
2012/07/ 01
2012/07/ 01
+3VALW
1
PJ508
PJ508
1
JUMP_43 X79
JUMP_43 X79
@
@
2
2
12
PC546
PC546
4.7U_080 5_6.3V6K
4.7U_080 5_6.3V6K
12
PR522
PR522
39.2K_04 02_1%
39.2K_04 02_1%
12
PR539
PR539
44.2K_04 02_1%
44.2K_04 02_1%
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
C
12
PC548
PC548
0.01U_04 02_25V7K
0.01U_04 02_25V7K
2014/07/ 01
2014/07/ 01
2014/07/ 01
PJ505
PJ505
2
112
JUMP_43 X118@
JUMP_43 X118@
+1.5VSP
12
PC547
PC547
22U_0805_6.3V6M
22U_0805_6.3V6M
Title
Title
Title
+1.5VS_VGA/+1.5VS
+1.5VS_VGA/+1.5VS
+1.5VS_VGA/+1.5VS
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032Y510 NM-A032
Y510 NM-A032Y510 NM-A032
Y510 NM-A032Y510 NM-A032
D
+1.5VS+1.5VSP
61 69
61 69
61 69
1.0
1.0
1.0
5
D D
+5VALW
PR701
@P R701
@
0_0402_ 5%
0_0402_ 5%
SUSP#< 32,47,56,61,62,63>
SUSP#_PWR<60 ,61>
SUS_VCCP<47>
C C
1 2
PR717
@P R717
@
0_0402_ 5%
0_0402_ 5%
1 2
PR718
PR718
0_0402_ 5%
0_0402_ 5%
1 2
PJ702
PJ702
JUMP_43 X118@
JUMP_43 X118@
112
PR702
47K_040 2_5%
47K_040 2_5%
22U_080 5_6.3V6M
22U_080 5_6.3V6M
2
@P R702
@
PC717
PC717
1 2
12
PC702
PC702
22U_080 5_6.3V6M
22U_080 5_6.3V6M
12
@
@
12
PC701
PC701
.1U_0402 _16V7K
.1U_0402 _16V7K
4
+3VS
PR703
PR703
10K_040 2_5%
10K_040 2_5%
PU701
PU701
10
PC718
PC718
1 2
12
4
LX
PVIN
PG
9
8
5
1U_0402_16V6K
1U_0402_16V6K
PVIN
SVIN
EN
TP
7
11
12
LX
FB
SS
1
.1U_0402 _16V7K
.1U_0402 _16V7K
PR716
PR716
10_0402 _5%
10_0402 _5%
PR715
PR715
0_0402_ 5%
0_0402_ 5%
12
12
VFB=0.6V
Vo=VFB*(1+PR706/PR705)
+3VS
2
3
6
LX
SY8036LDB C_DFN10_3X3
SY8036LDB C_DFN10_3X3
PC703
PC703
12
PR705
PR705
100K_04 02_1%
100K_04 02_1%
3
PL701
4.7_1206_5%
4.7_1206_5%
680P_0603_50V7K
680P_0603_50V7K
PL701
1 2
PR706
PR706
12
75K_040 2_1%
75K_040 2_1%
12
PC709
PC709
22P_040 2_50V8J
22P_040 2_50V8J
S COIL 1UH +-2 0% VMPI0703AR-1R 0M-Z01 11A
S COIL 1UH +-2 0% VMPI0703AR-1R 0M-Z01 11A
12
PR704
PR704
12
PC704
PC704
2
1
+1.05VS_VCCPP
12
12
PC705
PC705
22U_0805_6.3V6M
22U_0805_6.3V6M
12
PC706
PC706
22U_0805_6.3V6M
22U_0805_6.3V6M
12
PC708
PC707
PC707
PC708
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
PJ701
PJ701
2
112
JUMP_43 X118@
JUMP_43 X118@
+1.05VS+1.05 VS_VCCPP
PR713
PR713
10K_040 2_5%
10K_040 2_5%
PR714
PR714
0_0402_ 5%
0_0402_ 5%
PJ703
PJ703
2
DGPU_PW ROK<19,27,5 5,64>
112
JUMP_43 X39
JUMP_43 X39
@
@
SUSP#< 32,47,56,61,62,63>
5
PC716
PC716
22U_080 5_6.3VAM
22U_080 5_6.3VAM
12
PD701
PD701
RB751V-4 0_SOD323-2
RB751V-4 0_SOD323-2
1 2
PR709
PR709
1 2
0_0402_ 5%
0_0402_ 5%
PR712
PR712
1 2
0_0402_ 5%
0_0402_ 5%
+3VALW
B B
A A
1.05VMP_ VIN
12
PC710
PC710
22U_080 5_6.3VAM
22U_080 5_6.3VAM
EN_1.05V MP
@
@
1 2
12
PR710
PR710
1M_0402 _5%
1M_0402 _5%
PU702
PU702
4
IN
5
PG
GND
FB6EN
SY8032ABC _SOT23-6
SY8032ABC _SOT23-6
FB=0.6Volt
12
1 2
4
PL702
1 2
PR707
PR707
4.7_1206_5%
4.7_1206_5%
PC712
PC712
680P_0603_50V7K
680P_0603_50V7K
PL702
75K_040 2_1%
75K_040 2_1%
1.05VMP_ FB
PR708
PR708
2012/07/ 01
2012/07/ 01
2012/07/ 01
3
12
12
PR711
PR711
100K_04 02_1%
100K_04 02_1%
12
PC711
PC711
68P_0402_50V8J
68P_0402_50V8J
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
12
PC713
PC713
22U_0805_6.3VAM
22U_0805_6.3VAM
Deciphered Date
Deciphered Date
Deciphered Date
12
+1.05VSP_VGA
PJ704
PJ704
2
112
JUMP_43 X79@
JUMP_43 X79@
PC714
PC714
22U_0805_6.3VAM
22U_0805_6.3VAM
Title
Title
Title
2014/07/ 01
2014/07/ 01
2014/07/ 01
2
+1.05VS/+1.05VS_VGA
+1.05VS/+1.05VS_VGA
+1.05VS/+1.05VS_VGA
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032Y510 NM-A032
Y510 NM-A032Y510 NM-A032
Y510 NM-A032Y510 NM-A032
1
+1.05VS_ VGA+1.05VSP _VGA
62 69
62 69
62 69
1.0
1.0
1.0
1UH_PH0 41H-1R0MS_3.8A _20%
3
1.05VMP_LX
LX
2
1
@PC715
@
PC715
0.1U_0402_10V7K
0.1U_0402_10V7K
1UH_PH0 41H-1R0MS_3.8A _20%
12
12
Security Class ification
Security Class ification
Security Class ification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
A
B
C
D
+VGA_CORE
1 1
+VGA_CORE
2 2
Under VGA Core
12
12
12
12
PC802
PC802
PC801
PC801
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
12
12
PC816
PC816
PC815
PC815
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
Near VGA Core
1
12
PC830
PC830
PC829
PC829
2
47U_0805_6.3V6M
47U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
12
PC803
PC803
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
12
PC817
PC817
0.1U_0402_10V7K
0.1U_0402_10V7K
12
PC819
PC819
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
12
PC804
PC804
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
PC818
PC818
0.1U_0402_10V7K
0.1U_0402_10V7K
12
12
PC805
PC805
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
12
PC821
PC821
PC820
PC820
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
2N7002KW_SOT323- 3
2N7002KW_SOT323- 3
PC806
PC806
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
12
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
PR830 0_0402_5%PR8 30 0_ 0402_5%
100K_0402_1%
100K_0402_1%
PQ805
PQ805
PR805 = 34K ==>F sw = 450KHz
PR806 0_0402_5%PR8 06 0_ 0402_5%
VSSSENSE_VGA<24>
VCCSENSE_VGA<24>
3 3
1 2
PC853
PC853
1000P_0402_50V7K
1000P_0402_50V7K
1 2
PR807 0_0402_5%PR8 07 0_ 0402_5%
VSS_SEN
12
47P_0402_50V8J
47P_0402_50V8J
VCC_SEN
N14P-GT 35W
Ipeak=50A
Imax=35A
Iocp=64.8A
4 4
Fsw=450KHz
bulk cap 330uF 9m *5
A
GB4-128 package
12
12
12
PC807
PC807
PC808
PC808
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
12
12
PC824
PC823
PC823
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
S
S
@
@
10K_0402_1%
10K_0402_1%
1 2
<BOM Structure>
<BOM Structure>
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
12
12
G
G
2
0_0402_5%
0_0402_5%
PR808
PR808
PC824
@
@
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
13
D
D
PR825
PR825
1 2
PR809
PR809
51_0402_1%
51_0402_1%
1 2
PC822
PC822
PR827
PR827
PC852
PC852
1 2
N14P-GS 25W
Ipeak=36A
Imax=25A
Iocp=64.8A
Fsw=450KHz
bulk cap 330uF 9m *3
12
12
PC809
PC809
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
12
PC825
PC825
@
@
VREF
PR828
PR828
5.1K_0402_1%
5.1K_0402_1%
12
PC854
PC854
0.01U_0603_50V7K
0.01U_0603_50V7K
Thermistor near MOSFET
trigger point 97 degree C.
PC811
PC811
PC810
PC810
@
@
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
12
12
PC826
PC826
@
@
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
PR824
PR824
20K_0402_1%
20K_0402_1%
12
2700P_0402_50V7-K
2700P_0402_50V7-K
PR826
PR826
18K_0402_1%
18K_0402_1%
34K_0402_1%
34K_0402_1%
PC850 10P_0402_50V8JPC850 10P_0402_50V8J
1 2
PC851
PC851
100P_0402_50V8J
100P_0402_50V8J
12
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
PC827
PC827
@
@
@PC859
@
12
PR805
PR805
1 2
FB2_VGA
12
PC813
PC813
PC812
PC812
@
@
@
@
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
12
PC828
PC828
@
@
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
10P_0402_50V8J
10P_0402_50V8J
12
PC859
12
12
PC856
PC856
2200P_0402_50V7K
2200P_0402_50V7K
12
COMP_VGAFB1_VGA
1 2
PR810
PR810
82K_0402_1%
82K_0402_1%
PC849
PC849
.1U_0402_16V7K
.1U_0402_16V7K
12
@
@
PC858
PC858
20K_0402_1%
20K_0402_1%
12
VREF
FS
FB_VGA
PC814
PC814
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
12
PR823
PR823
PR829
PR829
2K_0402_1%
2K_0402_1%
7
8
9
10
11
12
12
PH801
PH801
<23>
12
VIDBUF
REFIN
VREF
FS
FBRTN
FB
COMP
100K_0402_1%_NCP15WF104F03 RC
100K_0402_1%_NCP15WF104F03 RC
1 2
12
<23>
RB751V-40_SOD323-2
RB751V-40_SOD323-2
30K_0402_1%
30K_0402_1%
1 2
NVVDD PWM_VID
GPU_VID
DPRSLPVR_VGA
+3VS_VGA
PR801 0_0402_5%PR8 01 0_ 0402_5%
6
NCP81172MNTWG_QF N24_4X4
NCP81172MNTWG_QF N24_4X4
GND
25
12
PR812 5.9K_0402_1%PR812 5.9K_0402_1 %
VREF
.1U_0402_16V7K
.1U_0402_16V7K
1 2
1 2
1 2
PR802 0_0402_5%PR8 02 0_ 0402_5%
PR804 1 0K_0402_5%PR804 10K_0402_5%
PSI_VGA
EN_VGA
5
2
3
4
EN
PSI
VID
VIDBUF
PU801
PU801
TSNS13TALERT#14VCC15PGOOD16HG217BST2
VCC_VGA
PR815 2.2_0402_5%PR815 2.2_0402 _5%
1 2
PC848
PC848
1U_0402_10V6K
1U_0402_10V6K
PR814 0_0402_5%PR8 14 0_ 0402_5%
PR813 10K_0402_5%PR813 10 K_0402_5%
B
PD801
PD801
12
PR803
PR803
PC855
PC855
UGATE1_VGA
1
HG1
BST1
24
PH1
23
LG1
22
PGND
21
PVCC
20
LG2
19
PH2
18
BOOT2_VGA
UGATE2_VGA
PR816 10K_0402_5 %PR816 10K_040 2_5%
12
12
12
+3VS
12
+3VS
PR831
PR831
10K_0402_5%
10K_0402_5%
1 2
12
PR832
PR832
100K_0402_5%
100K_0402_5%
@
@
0_0603_5%
0_0603_5%
BOOT1_VGA
PVCC_VGA
<19,27,55,63>
DGPU_PWROK
+3VS
+5VS
+VGA_B+
5
4
123
5
4
123
5
4
5
4
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered D ate
Deciphered D ate
Deciphered D ate
C
PC838
PC838
0.22U_0603_10V7K
0.22U_0603_10V7K
1 2
LGATE1_VGA
PC839
PC839
4.7U_0603_10V6K
4.7U_0603_10V6K
1 2
1 2
PR811 0_0402_5%PR8 11 0_ 0402_5%
PR817
PR817
0_0603_5%
0_0603_5%
PHASE2_VGA
LGATE2_VGA
Issued Date
Issued Date
Issued Date
<14>
12
0_0402_5%
0_0402_5%
12
PR834
2.2_0402_5%
2.2_0402_5%
0_0402_5%
0_0402_5%
12
PR833
2.2_0402_5%
2.2_0402_5%
PR822
PR822
12
@PR834
@
+5VS
PR818
PR818
12
BOOT2_2_VGA
@PR833
@
UGATE1_2_VGA
UGATE2_2_VGA
PC847
PC847
0.22U_0603_10V7K
0.22U_0603_10V7K
1 2
2012/07/01
2012/07/01
2012/07/01
NVDD_PWR_EN
PR821
PR821
12
BOOT1_2_VGA
PHASE1_VGA
Security Classif ication
Security Classif ication
Security Classif ication
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
PQ801
PQ801
FDMS7698
FDMS7698
PQ802
PQ802
FDMC0310AS
FDMC0310AS
PQ803
PQ803
123
FDMS7698
FDMS7698
PQ804
PQ804
123
FDMC0310AS
FDMC0310AS
12
12
PC831
PC831
PC832
PC832
0.1U_0402_25V6
0.1U_0402_25V6
2200P_0402_50V7K
2200P_0402_50V7K
5
4
123
12
12
PC841
PC841
PC840
PC840
0.1U_0402_25V6
0.1U_0402_25V6
5
4
2014/07/01
2014/07/01
2014/07/01
12
PC833
PC833
PQ806
PQ806
FDMC0310AS
FDMC0310AS
12
2200P_0402_50V7K
2200P_0402_50V7K
4.7_1206_5%
4.7_1206_5%
PQ807
PQ807
123
FDMC0310AS
FDMC0310AS
HCB2012KF-121T50_080 5
HCB2012KF-121T50_080 5
HCB2012KF-121T50_080 5
HCB2012KF-121T50_080 5
12
PC834
PC834
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
0.24UH_FDUE0630J-H-R2 4M-P3_22A_20%
0.24UH_FDUE0630J-H-R2 4M-P3_22A_20%
12
PR820
@PR820
@
4.7_1206_5%
4.7_1206_5%
SNUB1_VGA
12
PC835
@PC835
@
680P_0402_50V7K
680P_0402_50V7K
+VGA_B+
12
PC843
PC843
PC842
PC842
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
0.24UH_FDUE0630J-H-R2 4M-P3_22A_20%
0.24UH_FDUE0630J-H-R2 4M-P3_22A_20%
12
@
@
PR819
PR819
SNUB2_VGA
12
PC844
PC844
680P_0402_50V7K@
680P_0402_50V7K@
Title
Title
Title
VGA_CORE
VGA_CORE
VGA_CORE
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
PL801
PL801
1 2
PL802
PL802
1 2
PL803
PL803
1 2
PL804
PL804
1 2
1
+
+
PC836
PC836
2
1
+
+
2
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032Y510 NM-A032
Y510 NM-A032Y510 NM-A032
Wednesday, March 27, 201 3
Wednesday, March 27, 201 3
Wednesday, March 27, 201 3
Y510 NM-A032Y510 NM-A032
D
B+
+VGA_CORE
1
+
+
PC837
PC837
2
330U_D2_2V_Y
330U_D2_2V_Y
330U_D2_2V_Y
330U_D2_2V_Y
+VGA_CORE
1
+
+
PC846
PC846
PC845
PC845
2
330U_D2_2V_Y
330U_D2_2V_Y
330U_D2_2V_Y
330U_D2_2V_Y
1.0
1.0
63 69
63 69
63 69
1.0
5
D D
12
PH901
PH901
PR901
PR901
75K_0402_ 1%
75K_0402_ 1%
1 2
Place close to
phase 1 inductir
C C
PC914
PC914
390P_0402_50V7K
390P_0402_50V7K
1 2
1 2
PR920
PR920
49.9_0402_1%
49.9_0402_1%
1 2
PR921
PR921
1K_0402_1%
1K_0402_1%
1 2
PR922
PR922
0_0402_5%
B B
VSSSENSE<9>
VCCSENSE<9>
0_0402_5%
1 2
PR923
PR923
0_0402_5%
0_0402_5%
12
PR919
PR919
10K_0402_1%
10K_0402_1%
37W@
37W@
10P_0402_50V8J
10P_0402_50V8J
37W=10K
47W=7.5K
1 2
7.5K_0402_1%
7.5K_0402_1%
PC915
PC915
1000P_0402_50V7K
1000P_0402_50V7K
220K_0402 _5%_ERTJ0EV224J
220K_0402 _5%_ERTJ0EV224J
PC913
PC913
1 2
PR919
PR919
47W@
47W@
VSP
+5VALW
PR918
PR918
1K_0402_1%
1K_0402_1%
+VCCIO_OUT
PR902
PR902
165K_0402_1%
165K_0402_1%
1 2
CPU_B+
1 2
12
PC912
PC912
0.01U_040 2_25V7K
0.01U_040 2_25V7K
1 2
PR924
PR924
1K_0402_5%
1K_0402_5%
1 2
PC916
PC916
2200P_0402_50V7K
2200P_0402_50V7K
1 2
PR925
PR925
2_0603_5%
2_0603_5%
4
PR917
PR917
10K_0402_1%
10K_0402_1%
37W@
37W@
PR912
PR912
24.3K_0402_1%
24.3K_0402_1%
1 2
PC911
PC911
470P_0402_50V8-J
470P_0402_50V8-J
PC917
PC917
1 2
<47>
2.2U_0603 _10V7K
2.2U_0603 _10V7K
PC901
PC901
12
VSN_2VSN_1
1 2
1000P_040 2_50V7K
1000P_040 2_50V7K
VR_HOT#
3
PR903
PR903
121K +-1% 0603
121K +-1% 0603
1 2
121K +-1% 060347W@
121K +-1% 060347W@
1 2
121K +-1% 0603
121K +-1% 0603
PC902
PC902
1 2
680P_0402 _50V7K
680P_0402 _50V7K
PC903
PC903
1 2
1000P_040 2_50V7K
1000P_040 2_50V7K
<47>
CSSUM
IMVP_IMON
VR_ON<47>
37W=10K
47W=15.4K
PR917
PR917
15.4K_0402_1%
15.4K_0402_1%
47W@
47W@
1 2
CSCOMP
28
29
30
31
32
33
34
35
36
37
PR926
PR926
0_0402_5%
0_0402_5%
1 2
1 2
PR927
PR927
0_0402_5%
0_0402_5%
ILIM
IOUT
VRMP
COMP
FB
DIFFOUT
VSN
VSP
VCC
GND
27
26
CSSUM
CSCOMP
EN1VRHOT#2SDIO3ALERT#4ROSC7SCLK
VR_HOT#_1
25
1 2
CSP3
CSP2
CSP1
PU901
PU901
20
19
21
24
22
23
NCP81103MNTWG_QFN36_5X5
NCP81103MNTWG_QFN36_5X5
BST3
CSP3
CSP1
CSP2
DRON
CSREF
PWM2/IMAX
PVCC
PGND
BST1
VR_RDY
TSENSE
INT_SEL
5
6
8
9
TSENSE
VR_RDY
VR_SVID_DAT_1
VR_SVID_ALRT#_1
VR_SVID_CLK_1
PR929
PR929
34.8K_0402_1%
34.8K_0402_1%
1 2
PR904
PR904
PR905
PR905
CSREF <66>
PR906
PR906
66.5K_0402_1%
66.5K_0402_1%
1 2
47W@
47W@
18
HG3
17
SW3
16
LG3
15
14
13
LG1
12
SW1
11
HG1
10
PR928
PR928
45.3K_0402_1%
45.3K_0402_1%
1 2
PC910
PC910
.1U_0402_16V7K
.1U_0402_16V7K
1 2
SWN3
SWN2
SWN1
DRON <66>
NA for 37W
PR906
PR906
43K_0402_1%
43K_0402_1%
37W@
37W@
37W=43K
47W=66.5K
81103_PWM <66>
2.2_0603_5%
2.2_0603_5%
1 2
HG3 <66>
LG3 <66>
LG1 <66>
HG1 <66>
2.2_0603_5%
2.2_0603_5%
1 2
PR915
PR915
PR916
PR916
TSENSE
CSREF
CSREF
CSREF
PC907
PC907
0.22U_0402_10V6K
0.22U_0402_10V6K
1 2
PC908
PC908
1 2
2.2U_0603_10V7K
2.2U_0603_10V7K
PC909
PC909
0.22U_0402_10V6K
0.22U_0402_10V6K
1 2
CSP3
47W@
47W@
CSP2
CSP1
2
12
PC904
PC904
PR907
PR910
PR910
5.76K_0402_1%
5.76K_0402_1%
20K_0402_ 1%
@ PR907
20K_0402_ 1%
@
1 2
0.047U_04 02_16V7K
0.047U_04 02_16V7K
12
PC905
PC905
PR908
20K_0402_ 1%
@ PR908
20K_0402_ 1%
@
1 2
0.047U_04 02_16V7K
0.047U_04 02_16V7K
12
PC906
PC906
PR909
20K_0402_ 1%
@ PR909
20K_0402_ 1%
@
1 2
0.047U_04 02_16V7K
0.047U_04 02_16V7K
PR911
PR911
5.76K_0402_1%
5.76K_0402_1%
47W@
47W@
PR913
PR913
5.76K_0402_1%
5.76K_0402_1%
12
12
12
SWN3 <66>
SWN2 <66>
SWN1 <66>
NA for 37W
1
+5VALW
12
PR914
37W@
PR914
37W@
0_0402_5 %
0_0402_5 %
CSP2
SW3 <66>
PR951
PR951
0_0402_5%
0_0402_5%
1 2
SW1 <66>
+5VALW
Mount for 37W
12
12
PR931
0_0402_5 %
PR931
0_0402_5 %
PR930
PR934
PR934
PR933
PR933
PR932
PR932
75_0402_ 1%
75_0402_ 1%
130_0402 _1%
PR935
PR935
0_0402_5%
0_0402_5%
PR936
PR936
0_0402_5%
0_0402_5%
PR937
PR937
0_0402_5%
0_0402_5%
130_0402 _1%
A A
5
<9>
<9>
VR_SVID_ALRT#
<9>
VR_SVID_DAT
VR_SVID_CLK
1 2
1 2
1 2
54.9_040 2_1%
54.9_040 2_1%
1 2
1 2
1 2
VR_SVID_DAT_1
VR_SVID_ALRT#_1
VR_SVID_CLK_1
4
PC918
PC918
.1U_0402_16V7K
.1U_0402_16V7K
1 2
PR930
1.91K +-1 % 0402
1.91K +-1 % 0402
+3VS
VGATE
<6,15>
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
3
2012/07/01
2012/07/01
2012/07/01
PR938
PR938
PH902
PH902
13K_0402_ 1%
13K_0402_ 1%
1 2
1 2
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
100K_0402 _1%_TSM0B104F42 51RZ
100K_0402 _1%_TSM0B104F42 51RZ
Deciphered Date
Deciphered Date
Deciphered Date
Place close to
phase 2 MOSFET
2
2014/07/01
2014/07/01
2014/07/01
Title
Title
Title
CPU_CORE
CPU_CORE
CPU_CORE
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Wednesday, March 27, 201 3
Wednesday, March 27, 201 3
Wednesday, March 27, 201 3
Date: Sheet of
Date: Sheet of
Date: Sheet of
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032Y510 NM-A032
Y510 NM-A032Y510 NM-A032
Y510 NM-A032Y510 NM-A032
64 69
64 69
64 69
1
1.0
1.0
1.0
5
D D
4
3
2
1
CPU_B+
5
PR939
PR939
2.2_0603_1%
2.2_0603_1%
HG1<65>
SW1<65>
LG1<65>
C C
B B
81103_PWM<65>
DRON<65>
PR948
47W@ PR948
47W@
0_0402_5%
0_0402_5%
12
12
PC937
2.2U_0603_10V7K
2.2U_0603_10V7K
+5VALW
12
AON6504_POWERDFN56-8-5
AON6504_POWERDFN56-8-5
47W@
47W@
12
EN_VCORE2
PR945
PR945
2K_0402_1%
2K_0402_1%
VCC_VCORE2
47W@PC937
47W@
PQ902
PQ902
BSTA2 BSTA2_1
1
2
3
4
PU902
PU902
NCP81151MNTBG_DFN8_2X2
NCP81151MNTBG_DFN8_2X2
47W@
47W@
4
4
PR946
2.2_0603_5%
2.2_0603_5%
1 2
BST
PWM
EN
VCC
5
FLAG
DRVH
DRVL
GND
47W@PR946
47W@
SW
PQ901
PQ901
AON6428L_DFN8-5
AON6428L_DFN8-5
123
123
9
8
7
6
5
12
PR940
PR940
4.7_1206_5%
4.7_1206_5%
SNUB_CPU1
12
PC919
PC919
680P_0402_50V7K
680P_0402_50V7K
12
PC936
47W@PC936
47W@
0.22U_0402_10V6K
0.22U_0402_10V6K
47W@ PR947
47W@
HG2
SW2
LG2
AON6504_POWERDFN56-8-5
AON6504_POWERDFN56-8-5
12
12
PC921
PC921
PC920
PC920
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
PL902
PL902
0.22UH +-20% PCMB104T-R22MS 35A
0.22UH +-20% PCMB104T-R22MS 35A
1
2
4
PR947
2.2_0603_1%
2.2_0603_1%
12
4
PQ906
47W@ PQ906
47W@
12
4
3
PC922
PC922
10U_0805_25V6K
10U_0805_25V6K
V1N_CPU
5
5
12
12
PC923
PC923
0.1U_0402_25V6K
0.1U_0402_25V6K
12
PR941
PR941
10_0402_1%
10_0402_1%
PQ905
AON6428L_DFN8-5
AON6428L_DFN8-5
123
123
PC924
PC924
47W@PQ905
47W@
2200P_0402_50V7K
2200P_0402_50V7K
12
SNUB_CPU2
12
FBMA-L11-453215-800LMA90T_1812
FBMA-L11-453215-800LMA90T_1812
1 2
CSREF <65>
SWN1 <65>
12
PC939
PC939
47W@
47W@
PR949
PR949
4.7_1206_5%
4.7_1206_5%
47W@
47W@
PC938
PC938
680P_0402_50V7K
680P_0402_50V7K
47W@
47W@
PL901
PL901
1
+
+
PC933
PC933
2
68U_25V_M_R0.36
68U_25V_M_R0.36
+VCC_CORE
12
12
PC926@
PC926@
PC925@
PC925@
68P_0402_50V8J
68P_0402_50V8J
220P_0402_50V7K
220P_0402_50V7K
CPU_B+
12
12
12
12
PC940
PC940
10U_0805_25V6K
10U_0805_25V6K
47W@
47W@
0.22UH +-20% PCMB104T-R22MS 35A
0.22UH +-20% PCMB104T-R22MS 35A
10U_0805_25V6K
10U_0805_25V6K
47W@
47W@
1
2
47W@
47W@
PC941
PC941
PL904
PL904
10U_0805_25V6K
10U_0805_25V6K
47W@
47W@
PC942
PC942
0.1U_0402_25V6K
0.1U_0402_25V6K
47W@
47W@
4
3
B+
1
+
+
PC934
PC934
2
68U_25V_M_R0.36
68U_25V_M_R0.36
PC943
PC943
2200P_0402_50V7K
2200P_0402_50V7K
PR950
PR950
10_0402_1%
10_0402_1%
47W@
47W@
12
V2N_CPU CSR EF
HG3<65>
SW3<65>
LG3<65>
AON6504_POWERDFN56-8-5
AON6504_POWERDFN56-8-5
+VCC_CORE
SWN2 <65>
PR942
PR942
2.2_0603_1%
2.2_0603_1%
12
4
4
PQ904
PQ904
Mount for 47W
5
123
AON6428L_DFN8-5
AON6428L_DFN8-5
5
123
PQ903
PQ903
CPU_B+
12
12
12
PC927
PC927
PC928
PC928
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
12
12
PC930
PC930
PC929
PC929
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6K
0.1U_0402_25V6K
PL903
PL903
0.22UH +-20% PCMB104T-R22MS 35A
0.22UH +-20% PCMB104T-R22MS 35A
12
SNUB_CPU3
12
1
2
PR943
PR943
4.7_1206_5%
4.7_1206_5%
PC935
PC935
680P_0402_50V7K
680P_0402_50V7K
PC931
PC931
2200P_0402_50V7K
2200P_0402_50V7K
+VCC_CORE
4
3
PR944
PR944
12
V3N_CPU
10_0402_1%
10_0402_1%
CSREF
SWN3 <65>
A A
Title
Title
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF LC FU TURE CENTER. AND CONTAINS CON FIDENTIAL
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF LC FU TURE CENTER. AND CONTAINS CON FIDENTIAL
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF LC FU TURE CENTER. AND CONTAINS CON FIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.
3
2012/07/01
2012/07/01
2012/07/01
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2014/07/01
2014/07/01
2014/07/01
Title
CPU_CORE
CPU_CORE
CPU_CORE
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Date: Sheet of
Date: Sheet of
Date: Sheet of
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032Y510 NM-A032
Y510 NM-A032Y510 NM-A032
Y510 NM-A032Y510 NM-A032
1
65 69
65 69
65 69
1.0
1.0
1.0
5
4
3
2
1
Based on PDDG rev 0.7 Table 5-1.
+VCC_CORE
+VCC_CORE
D D
1
PC1001
PC1001
10U_080 5_6.3VAM
10U_080 5_6.3VAM
2
1
PC1011
PC1011
10U_080 5_6.3VAM
10U_080 5_6.3VAM
2
1
PC1002
PC1002
10U_080 5_6.3VAM
10U_080 5_6.3VAM
2
1
PC1010
PC1010
10U_080 5_6.3VAM
10U_080 5_6.3VAM
2
1
PC1003
PC1003
10U_080 5_6.3VAM
10U_080 5_6.3VAM
2
1
PC1009
PC1009
10U_080 5_6.3VAM
10U_080 5_6.3VAM
2
1
PC1004
PC1004
10U_080 5_6.3VAM
10U_080 5_6.3VAM
2
1
PC1008
PC1008
10U_080 5_6.3VAM
10U_080 5_6.3VAM
2
1
PC1005
PC1005
10U_080 5_6.3VAM
10U_080 5_6.3VAM
2
1
PC1007
PC1007
10U_080 5_6.3VAM
10U_080 5_6.3VAM
2
1
PC1006
PC1006
10U_080 5_6.3VAM
10U_080 5_6.3VAM
2
1
+
+
PC1030
PC1030
470U_D2 _2VM_R4.5M~D
470U_D2 _2VM_R4.5M~D
2
1
+
+
PC1034
PC1034
470U_D2 _2VM_R4.5M~D
470U_D2 _2VM_R4.5M~D
2
@
@
1
+
+
PC1031
PC1031
470U_D2 _2VM_R4.5M~D
470U_D2 _2VM_R4.5M~D
2
@
@
1
+
+
470U_D2 _2VM_R4.5M~D
470U_D2 _2VM_R4.5M~D
2
PC1035
PC1035
@
@
1
+
+
PC1032
PC1032
470U_D2 _2VM_R4.5M~D
470U_D2 _2VM_R4.5M~D
2
1
+
+
PC1033
PC1033
470U_D2 _2VM_R4.5M~D
470U_D2 _2VM_R4.5M~D
2
@
@
+VCC_CORE
1
PC1016
PC1016
22U_080 5_6.3VAM
22U_080 5_6.3VAM
2
C C
1
PC1017
PC1017
22U_080 5_6.3VAM
22U_080 5_6.3VAM
2
1
PC1026
PC1026
22U_080 5_6.3VAM
22U_080 5_6.3VAM
2
1
PC1015
PC1015
22U_080 5_6.3VAM
22U_080 5_6.3VAM
2
1
PC1018
PC1018
22U_080 5_6.3VAM
22U_080 5_6.3VAM
2
1
PC1025
PC1025
22U_080 5_6.3VAM
22U_080 5_6.3VAM
2
1
PC1014
PC1014
22U_080 5_6.3VAM
22U_080 5_6.3VAM
2
1
PC1019
PC1019
22U_080 5_6.3VAM
22U_080 5_6.3VAM
2
1
PC1024
PC1024
22U_080 5_6.3VAM
22U_080 5_6.3VAM
2
1
PC1013
PC1013
22U_080 5_6.3VAM
22U_080 5_6.3VAM
2
1
PC1020
PC1020
22U_080 5_6.3VAM
22U_080 5_6.3VAM
2
1
PC1023
PC1023
22U_080 5_6.3VAM
22U_080 5_6.3VAM
2
1
PC1012
PC1012
22U_080 5_6.3VAM
22U_080 5_6.3VAM
2
1
PC1021
PC1021
22U_080 5_6.3VAM
22U_080 5_6.3VAM
2
1
PC1022
PC1022
22U_080 5_6.3VAM
22U_080 5_6.3VAM
2
1
PC1027
PC1027
22U_080 5_6.3VAM
22U_080 5_6.3VAM
2
B B
A A
1
PC1028
PC1028
22U_080 5_6.3VAM
22U_080 5_6.3VAM
2
5
1
PC1029
PC1029
22U_080 5_6.3VAM
22U_080 5_6.3VAM
2
1
PC1036
PC1036
22U_080 5_6.3VAM
22U_080 5_6.3VAM
2
Title
Title
Security Class ification
Security Class ification
Security Class ification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
2012/07/ 01
2012/07/ 01
2012/07/ 01
3
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2014/07/ 01
2014/07/ 01
2014/07/ 01
2
Title
PROCESSOR DECOUPLING
PROCESSOR DECOUPLING
PROCESSOR DECOUPLING
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032Y510 NM-A032
Y510 NM-A032Y510 NM-A032
Y510 NM-A032Y510 NM-A032
1
66 69
66 69
66 69
1.0
1.0
1.0
5
4
3
2
1
D D
DE
A1
VIN
BATT
B1
V
PU301
V
A2
B2
BATT+
A3
B4
+3VALW
B5
V
A5
B7 2
V
V
B
+
PU401
V
V
VS
AC
ODE
M
BATT
MO
V
PQ101
EC
PCH_PWR_EN#
2
PCH_DPWROK_R
PCH_RSMRST#
VV
A5
B3
51ON#
C C
B B
EC_ON
N
/OFFBTN#
O
ON/OFF
B7
A4
B6
V
V
SUSP#,SUSP
PBTN_OUT#
PM_SLP_S3#
PM_SLP_S4#
PM_SLP_S5#
PM_SLP_A#
V
SYSON PU501
DGPU_PWR_EN (GPU)
NVDD_PWR_EN (PCH)
SUSP#,SUSP
U3
+1.35V_CPU_VDDQ
V
2-A
Q148,+3VALW_PCH
V
Q149,+5VALW_PCH
+3VALW_PCH
3
+5VALW_PCH
2
4
5
6
7
8-A
(DIS)
8
V
V
V
PCH
V
+1.35V, +0.675VS
VV
U46
+5VS
U47
V
+3VS
PU503
V
+1.8VS
PU504
V
+1.5VS
V
SYS_PWROK
PM
_DRAM_PWRGD_CPU
H_CPUPWRGD
PLT_RST#
Q145, Q147
+3VS_VGA
V
+3VS_SLI
PU502, PU702
+1.5VS_VGA
+1.05VS_VGA
V
DGPU_PWROK (PWR IC)
PU801
V
8-B
15
14
(DIS)
V
1
0-A
V
CPU
VV
V
11
VGATE
+VGA_CORE
PU701
+1.05VS_VCCP
V
+1.05VS
PU701
V
+1.05VS
VDDQ_PWRGOOD
9
V
10
VR_ON
A A
Security Classification
Security Classification
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
Issued Date
Issued Date
Issued Date
PU901
V
+VCC_CORE
3
2012/07/01
2012/07/01
2012/07/01
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2014/07/01
2014/07/01
2014/07/01
V
Title
Title
Title
Power Sequence
Power Sequence
Power Sequence
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Date: Sheet of
Date: Sheet of
Date: Sheet of
Wednesday, March 27, 2013
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032Y510 NM-A032
Y510 NM-A032Y510 NM-A032
Y510 NM-A032Y510 NM-A032
1
67 69
67 69
67 69
1.0
1.0
1.0
5
4
3
2
1
HW PIR (Product Improve Record)
QIQY5 LA-8691P SCHEMATIC CHANGE LIST
REVISION CHANGE: 0.2
GERBER-OUT DATE: 2012/03/09
NO DATE PAGE MODIFICATION LIST PURPOSE
D D
---------------------------------------------------------------------------------------------------------------------
01) 03/14 10 R64 Change R64 BOM structure from "@" to "DS3@" For Deep S3 Function
C C
B B
A A
Title
Title
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.
3
2012/07/01
2012/07/01
2012/07/01
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2014/07/01
2014/07/01
2014/07/01
Title
HW PIR
HW PIR
HW PIR
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Date: Sheet of
Date: Sheet of
Date: Sheet of
Wednesday, March 27, 2013
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032Y510 NM-A032
Y510 NM-A032Y510 NM-A032
Y510 NM-A032Y510 NM-A032
1
68 69
68 69
68 69
1.0
1.0
1.0
5
4
3
2
1
Version change list (P.I.R. List) Page 1 of 1
for PWR
Reason for change PG# Modify List Date PhaseItem
1
D D
2
3
4
5
6
7
8
C C
9
10
11
12
13
14
B B
15
16
17
A A
Title
Title
Security Classifi cation
Security Classifi cation
Security Classifi cation
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF LC FUTURE CENTER.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF LC FUTURE CENTER.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF LC FUTURE CENTER.
3
2012/07/01
2012/07/01
2012/07/01
LC Future Center Secret Data
LC Future Center Secret Data
LC Future Center Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2014/07/01
2014/07/01
2014/07/01
2
Title
PWR PIR
PWR PIR
PWR PIR
Size D ocument Number Rev
Size D ocument Number Rev
Size D ocument Number Rev
Wednesday, March 27, 2013
Wednesday, March 27, 2013
Date: Sheet of
Date: Sheet of
Date: Sheet of
Wednesday, March 27, 2013
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032
Y510 NM-A032Y510 NM-A032
Y510 NM-A032Y510 NM-A032
Y510 NM-A032Y510 NM-A032
69 69
69 69
69 69
1
1.0
1.0
1.0
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