Compal MIRAMAR17 Schematic

A

COMPAL

COMPALCOMPAL CONFIDENTIAL

CONFIDENTIAL

CONFIDENTIALCONFIDENTIAL

MODEL NAME :

1 1

MODEL NAME :MODEL NAME : PCB NO :

PCB NO :

PCB NO :PCB NO : BOM P/N :

BOM P/N :

BOM P/N : BOM P/N : GPIO MAP:

GPIO MAP:

GPIO MAP: GPIO MAP:

AAPB0

AAPB0AAPB0

LA-C551P

LA-C551PLA-C551P

4319X331L01

4319X331L014319X331L01

Gen7 GPIO Master_0520

Gen7 GPIO Master_0520Gen7 GPIO Master_0520

B

MIRAMAR17

MIRAMAR17MIRAMAR17

C

D

E

2 2

Skylake H-type (2 chip)

REV : 1.0 (A00)

REV : 1.0 (A00)REV : 1.0 (A00)

2015.08.18

2015.08.182015.08.18

@ : Nopop Component

@ : Nopop Component @ : Nopop Component

EMC@ : EMI/ESD/RF part

EMC@ : EMI/ESD/RF part EMC@ : EMI/ESD/RF part

CONN@ : Connector Component

CONN@ : Connector ComponentCONN@ : Connector Component

XDP@ : Total debug Component (pop them until ST)

XDP@ : Total debug Component (pop them until ST)XDP@ : Total debug Component (pop them until ST)

3 3

TB@ : Thunderbolt function

TB@ : Thunderbolt function TB@ : Thunderbolt function

Layout Dell logo

4 4

Power CKT:

Power CKT:Power CKT: 0108

0108

01080108

DATE: 1403-06

PCB_178 _LA-XXXXP_ REV0_MB

Part

Description

Number

DAXXXXXXXXX

PCB 178 LA-XXXXP REV0 MB

A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET O F ENGINEERING DRAWING AND SPEC IFICATIONS CONTAINS CONFIDENTI AL TRADE SECRET AND OTHER PROPRIE TARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHO UT THE EXPRESS WRITTEN AUTHORI ZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS WAY BE US ED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT DELL'S EXPRESS W RITTEN CONSENT.

B

C

D

Title

Size Document Nu mber Rev

Date: Sheet of

Compal Electronics, Inc.

Cover Sheet

LA-C551P

1 74Tuesday, Augus t 18, 2015

E

1.0

A

Lane x4

eDP MUX

TBT

TBT TBT Conn

Conn

ConnConn

P.6

P.6P.6

Docking

DockingDocking LAN

LAN

LANLAN

eDP MUX

eDP MUXeDP MUX

PS8331

PS8331 PS8331

P.29

P.29P.29

DDI1

DDI1DDI1

DP MUX

DP MUXDP MUX PS8331

PS8331

PS8331PS8331

DPC

DPCDPC

P.31

P.31P.31

mDP

mDPmDP

TBT_DP1

TBT_DP1TBT_DP1

TBT

TBTTBT AR-SP

AR-SP

AR-SPAR-SP

PCIE

PCIEPCIE

Port 5~8

Port 5~8Port 5~8

Port 4

Port 4Port 4

Intel Jacksonville

Intel JacksonvilleIntel Jacksonville WGI219LM

WGI219LM

WGI219LMWGI219LM

LAN switch

LAN switchLAN switch

PI3L720ZHEX

PI3L720ZHEXPI3L720ZHEX

RJ45

RJ45RJ45

TBT_DP0

TBT_DP0TBT_DP0

On Display

On DisplayOn Display TBT board

TBT board

TBT boardTBT board

P.35

P.35P.35

P.35

P.35P.35

P.36

P.36P.36

DP DEMUX

DP DEMUXDP DEMUX PS8338

PS8338

PS8338PS8338

eDP Panel

eDP PaneleDP Panel Conn

Conn

Conn Conn

P.30

P.30P.30

Docking

DockingDocking

1 1

DP Port1

DP Port1DP Port1

mDP

mDPmDP

1.2

1.21.2 Conn

Conn

Conn Conn

HDMI2.0

HDMI2.0HDMI2.0 Conn

Conn

ConnConn

UPD

UPD UPD PIC32MX150F128DT5

PIC32MX150F128DT5

PIC32MX150F128DT5PIC32MX150F128DT5

2 2

Port 3

Port 3Port 3

RTS5242

RTS5242RTS5242 SD4.0/MMC

SD4.0/MMC

SD4.0/MMCSD4.0/MMC

SDXC

SDXCSDXC

P.6

On I/O

On I/OOn I/O board

board

boardboard

3 3

4 4

P.6P.6

DC

DCDC

Lane x4Lane x4

Lane x4

Lane x4Lane x4

DP MUX

DP MUXDP MUX PS8331

PS8331

PS8331PS8331

DP MUX

DP MUXDP MUX PS8331

PS8331

PS8331PS8331

P.34

P.34P.34

Port 5~8

Port 5~8 Port 2

Port 5~8Port 5~8

Thunderbolt

ThunderboltThunderbolt

P.5~8

P.5~8P.5~8

On Display I/O board

On Display I/O boardOn Display I/O board

SATA Port 1

SATA Port 1SATA Port 1

USB2 Port 7

USB2 Port 7USB2 Port 7 USB2 Port 5

USB2 Port 5

USB2 Port 5USB2 Port 5

DAI

DAIDAI

RGB

RGBRGB

LAN

LANLAN

USB3.0 Port 6

USB3.0 Port 6USB3.0 Port 6

LPC

LPCLPC

Docking

DockingDocking DP

DP

DPDP

Docking

DockingDocking DP

DP

DPDP

M.2 Card slot_4

M.2 Card slot_4 M.2 Card slot_4 SSD

SSD

SSDSSD

P.33

P.33P.33

DDI3

DDI3DDI3

DPB

DPBDPB

DDI2

DDI2DDI2

DP DEMUX

DP DEMUXDP DEMUX PS8338

PS8338

PS8338PS8338

Docking

DockingDocking DP Port2

DP Port2

DP Port2DP Port2

Port 17~20

Port 17~20Port 17~20

B

DPA

DPADPA

P.32

P.32P.32

Port 9~12

Port 9~12Port 9~12

M.2 Card slot_3

M.2 Card slot_3 M.2 Card slot_3 SSD

SSD

SSDSSD

P.39

P.39P.39

SMSC SIO

SMSC SIO SMSC SIO ECE5048

ECE5048

ECE5048 ECE5048

E-Dock

E-DockE-Dock

P.39

P.39P.39

P.43

P.43P.43

Docking

DockingDocking CRT

CRT

CRTCRT

PEG x16

PEG x16PEG x16

(Gen3)

(Gen3)(Gen3)

DP_D

DP_DDP_D

DP_C

DP_CDP_C

MXM

MXM MXM Conn.

Conn.

Conn.Conn.

DP_B

DP_BDP_B

TYPE A

TYPE A TYPE A

DP_A

DP_ADP_A

VGA

VGAVGA

PCIE BUS

PCIE BUSPCIE BUS

Port 13

Port 13Port 13

M.2 Card slot_2

M.2 Card slot_2 M.2 Card slot_2 WWAN/LTE/HCA/

WWAN/LTE/HCA/

WWAN/LTE/HCA/WWAN/LTE/HCA/ Cache

Cache

Cache Cache

P.38

P.38P.38

USB2 Port8

USB2 Port8 USB2 Port 6

USB2 Port8USB2 Port8

BC BUS

BC BUSBC BUS

P.45

P.45P.45

FAN control

FAN controlFAN control CY8C4245AXI

CY8C4245AXI

CY8C4245AXICY8C4245AXI

FAN CONN

FAN CONNFAN CONN

Micro SIM Card

Micro SIM CardMicro SIM Card

Free Fall Sensor

Free Fall SensorFree Fall Sensor

LNG2DMTR

LNG2DMTRLNG2DMTR

P.18

P.18P.18

Port 2

Port 2Port 2

M.2 Card slot_1

M.2 Card slot_1M.2 Card slot_1 WLAN/BT/WiGig

WLAN/BT/WiGig

WLAN/BT/WiGigWLAN/BT/WiGig

USB2 Port 6

USB2 Port 6USB2 Port 6

SMSC KBC

SMSC KBC SMSC KBC MEC5085

MEC5085

MEC5085 MEC5085

P.28

P.28P.28

P.28

P.28P.28

P.38

P.38P.38

P.41

P.41P.41

P.38

P.38P.38

P.46

P.46P.46

KB/TP

KB/TPKB/TP CONN

CONN

CONNCONN

C

eDP

eDPeDP

Intel

Intel Intel

DDI3

DDI3DDI3

SKYLAKE-H

SKYLAKE-H SKYLAKE-H

DDI1

DDI1DDI1

BGA CPU

BGA CPU BGA CPU

DDI2

DDI2DDI2

1440 Pins

1440 Pins 1440 Pins

PEG

PEGPEG

Intel

Intel Intel SKYLAKE-H

SKYLAKE-H

SKYLAKE-H SKYLAKE-H BGA

BGA

BGA BGA 837 Pins

837 Pins

837 Pins 837 Pins

LPC BUS

P.48

P.48P.48

SPI

P.6~13

P.6~13P.6~13

DMI x4

DMI x4DMI x4 gen 2

gen 2

gen 2gen 2

P.18~26

P.18~26P.18~26

W25Q128FVSIQ

W25Q128FVSIQW25Q128FVSIQ

128Mb 4K sector

W25Q32FVSSIQ

W25Q32FVSSIQW25Q32FVSSIQ

32Mb 4K sector

Discrete TPM

Discrete TPM Discrete TPM NPCT650JAAYX

NPCT650JAAYX

NPCT650JAAYXNPCT650JAAYX

D

(DDR4) Memory Bus

1.2V DDR4 2133/2667/2 933MHz (Overclocking)

SATA Port 2

SATA Port 2SATA Port 2 PCIE Port 15

PCIE Port 15

PCIE Port 15PCIE Port 15

SATA3.0

SATA3.0SATA3.0

USB3.0

USB3.0USB3.0

USB2.0

USB2.0USB2.0

HD

HDHD Audio

Audio

AudioAudio

P.22

P.22P.22

P.22

P.22P.22

P.37

P.37P.37

On USH/B

On USH/BOn USH/B

Audio Codec

Audio Codec Audio Codec ALC3235

ALC3235

ALC3235 ALC3235

On I/O board

On I/O boardOn I/O board

P.4

P.4P.4

SATA/PCIE

SATA/PCIESATA/PCIE Repeater

Repeater

RepeaterRepeater

USB3 Port 3

USB3 Port 3USB3 Port 3

USB2 Port 2

USB2 Port 2USB2 Port 2

USB3 Port 4

USB3 Port 4USB3 Port 4

USB2 Port 3

USB2 Port 3USB2 Port 3

USB3 Port 5

USB3 Port 5USB3 Port 5

USB2 Port 4

USB2 Port 4USB2 Port 4

USB3 Port 1

USB3 Port 1USB3 Port 1

USB2 Port 1

USB2 Port 1USB2 Port 1

USB2 Port 11

USB2 Port 11USB2 Port 11

USB Port 7

USB Port 7USB Port 7

Universal Jack

Universal JackUniversal Jack

Int. Speaker

Int. SpeakerInt. Speaker

DDR4 ECC-SO-DIMM X4

DDR4 ECC-SO-DIMM X4DDR4 ECC-SO-DIMM X4

BANK 0, 1, 2, 3, 4 ,5 ,6 ,7

BANK 0, 1, 2, 3, 4 ,5 ,6 ,7BANK 0, 1, 2, 3, 4 ,5 ,6 ,7

P.42

P.42P.42

USB 3.0 Repeater

USB 3.0 RepeaterUSB 3.0 Repeater

PS8713B

PS8713BPS8713B

USB Power Share

USB Power ShareUSB Power Share

TPS2544

TPS2544TPS2544

USB 3.0 Repeater

USB 3.0 RepeaterUSB 3.0 Repeater

PS8713B

PS8713BPS8713B

USB Power Share

USB Power ShareUSB Power Share

TPS2544

TPS2544TPS2544

USB 3.0 Repeater

USB 3.0 RepeaterUSB 3.0 Repeater

PS8713B

PS8713BPS8713B

USB Power Share

USB Power ShareUSB Power Share

TPS2544

TPS2544TPS2544

USB 3.0 Repeater

USB 3.0 RepeaterUSB 3.0 Repeater

PS8713B

PS8713BPS8713B

USB Power Share

USB Power ShareUSB Power Share

TPS2544

TPS2544TPS2544

Digital Camera

Digital Camera Digital Camera

BRCM58100

BRCM58100BRCM58100 TPM 1.2

TPM 1.2

TPM 1.2 TPM 1.2

SPI

SPISPI

P.4

P.4P.4

E

P.14~17

P.14~17P.14~17

SATA EXPRESS HDD

SATA EXPRESS HDDSATA EXPRESS HDD

P.7

P.7P.7

P.7

P.7 P.7

P.7P.7

P.8

P.8P.8

P.8

P.8 P.8

P.8P.8

P.9

P.9P.9

P.9

P.9P.9

P.12

P.12P.12

P.12

P.12P.12

P.30

P.30P.30

TDA8034HN

TDA8034HNTDA8034HN

Smart Card

Smart CardSmart Card

SPI

SPISPI

RFID/NFC

RFID/NFCRFID/NFC

Fingerprint

Fingerprint Fingerprint CONN

CONN

CONN CONN

P.41

P.41P.41

USB 3.0 Conn

USB 3.0 Conn USB 3.0 Conn

Right Side

Right SideRight Side

USB Charger

USB ChargerUSB Charger

USB 3.0 Conn

USB 3.0 Conn USB 3.0 Conn

Right Side

Right SideRight Side

USB Charger

USB ChargerUSB Charger

USB 3.0 Conn

USB 3.0 Conn USB 3.0 Conn

Right Side

Right SideRight Side

USB Charger

USB ChargerUSB Charger

USB 3.0 Conn

USB 3.0 Conn USB 3.0 Conn

Left Side

Left SideLeft Side

USB Charger

USB ChargerUSB Charger

P.7

P.7P.7

P.8

P.8P.8

P.9

P.9P.9

P.12

P.12P.12

On Display

On Display On Display board

board

boardboard

P.37

P.37P.37

On I/O

On I/OOn I/O board

board

boardboard

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

A

B

C

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

D

Title

Size Document Number Rev

Date: Sheet of

Block Diagram

LA-C551P

E

2 74Tuesday, August 18, 2015

1.0

5

4

3

2

1

POWER STATES

Signal

State

S0 (Full ON) / M0

D D

S3 (Suspend to RAM) / M1 LOW HIGH HIGH HIGH ON ON ON OFF

S4 (Suspend to DISK) / M1 ON ON OFF

S5 (SOFT OFF) / M1 ON ON OFFLOW LOW HIGHLOW

S3 (Suspend to RAM) / M-OFF

S4 (Suspend to DISK) / M-OFF HIGH

S5 (SOFT OFF) / M-OFF

SLP S3#

HIGH

LOW HIGH HIGHLOW

LOW HIGH HIGH HIGH LOW ON ONOFF OFF OFF

LOW LOW LOW LOW ON OFF OFF OFF OFF

LOW LOW LOW LOW LOW ON OFF OFF OFF OFF

SLP

SLP S4#

HIGH HIGH HIGH

LOW

S5#

S4 STATE#

SLP M#

HIGH

ALWAYS PLANE

ON

M PLANE

ON

SUS

RUN

PLANE

ON ON ON

OFF

OFF OFF

CLOCKS

OFF

PCH

PM TABLE

+PWR_SRC

+5V_ALW

C C

State

power plane

+3.3V_ALW

+3.3V_ALW2 +1.0V_VCCST

+3.3V_ALW_DSW

+3.3V_ALW_PCH

+3.3V_RTC_LDO

+1.8V_ALW

+1.0V_PRIM

+3.3V_SUS

+1.2V_MEM

+2.5V_MEM

+5V_RUN

+3.3V_RUN

+1.5V_RUN +VCC_CORE

+0.675V_DDR_VTT

+3.3V_MXM

+5V_MXM

+MXM_PWR_SRC

+3.3V_M

(M-OFF)

+3.3V_M

+VCC_EDRAM

+VCC_EOPIO

+VCC_GTU

+VCC_GT

+1.0V_VCCSTG

+VCC_SA

SATA

SATA 0

SATA 1

DESTINATION

2280 SSD

Dock

SATA 2

S0

S3

S5 S4/AC

S5 S4/AC don't exist

B B

A A

Stack up

ON

ON ON

ON

OFF

OFFOFF

OFFON

OFF

ON

OFF

OFFOFF

USB3.0 DESTINATION

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

Left Side JUSB1

M.2 Slot-2 (WWAN/LTE/HCA)

Right Side JUSB1

Right Side JUSB2

Right Side JUSB3

Docking

SATA 3

SATA 4

SATA 5

SATAe HDD

2280 SSD

USH

PCI EXPRESS

USB PORT# DESTINATION

1

2

3

4

5

6

7

Left Side JUSB1

Right Side JUSB1

Right Side JUSB2

Right Side JUSB3

Docking USB3.0

M.2 Slot-1 (WLAN/BT/WiGig)

Docking USB 2.0

M.2 Slot-2 (WWAN/LTE/HCA)8

9

10

11

12

13

14

0

1

NA

USH

Camera

NA

BIO

NA

DESTINATION

Lane 1

Lane 2

Lane 3

Lane 4

Lane 5~8

Lane 9~12

Lane 13

Lane 15~16

Lane 17~20

NA

M.2 Slot-1 (WLAN/Wigig)

MMI(Card reader)

10/100/1G LOM

TBT-Alpine Ridge

SSD 2280

M.2 Slot-2 (WWAN/LTE/HCA)

HDD SATA-Express

SSD 2280

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Size Document Nu mber Rev

Date: Sheet of

Compal Electronics, Inc.

Index and Config.

LA-C551P

3 74Tuesday, Augus t 18, 2015

1

1.0

5

Docking

D D

ADAPTER

BATTERY

CHARGER

C C

SIO_SLP_S4#

RT8207 (PU200)

PCH_ALW_ON

B B

+V_DDR_REF

+0.6V_DDR_VTT

+1.2V_MEM

TPS22967

(UZ27)

TPS22967

(UZ24)

+3.3V_ALW_PCH

4

+PWR_SRC

EN_INVPWR

3.3V_RUN_GFX_ON

IMVP_VR_ON

SIO_SLP_S3#

IMVP_VR_ON

SIO_SLP_SUS#

FDC654P

(Q21)

SI4835DDY

(Q186)

ISL95812

(PU500)

SYX198DQNC

(PU300)

NCP81382MNTXG (PU1400,PU1401)

NCP81210MNTWG

(PU1600)

SYX198DQNC

(PU500)

TPS51212

(PU800)

+3.3V_ALW

3.3V_WWAN_EN

+3.3V_WWAN

RUN_ON

EM5209VF

(UZ20)

+3.3V_RUN

EM5209VF

(UZ26)

SIO_SLP_LAN#

SIO_SLP_WLAN#

EM5209VF

(UZ25)

+3.3V_LAN

AUX_EN_WOWL

+3.3V_WLAN

3.3V_RUN_GFX_ON

+3.3V_MXM

SLOT3_SSD_PWR_EN

EM5209VF

(UZ21)

+3.3V_SSD1

3

SLOT4_SSD_PWR_EN

+3.3V_SSD2

+BL_PWR_SRC

+MXM_PWR_SRC

+VCC_CORE

+VCC_IO

+VCC_GT

+VCC_GTU

+VCC_EDRAM

ALWON

SIO_SLP_S4#

SIO_SLP_A#

EM5209VF

(UZ2)

+3.3V_M

+3.3V_SUS

A_ON

+1.0V_PRIM

TPS51225

(PU101)

APL3512ABI

+LCDVDD

ENVDD_PCH

(U33)

RUN_ON

SIO_SLP_S0#

SIO_SLP_S3#

MXM_ENVDD

LCD_VCC_TEST_EN

SIO_SLP_S4#

+5V_ALW

SIO_SLP_SUS#

SY8003DFC

(PU900)

+1.8V_ALW

2

TPS22967

(UZ23)

TPS22961

TPS22967

(UZ18)

SIO_SLP_S4#

SY8003DFC

(PU400)

+2.5V_MEM

+1.0V_VCCSTG(UZ19)

+1.0V_VCCST

RUN_ON

3.3V_RUN_GFX_ON

Left IO Board

USB_PWR_SHR_VBUS_EN

USB1_VBUS_EN

USB2_VBUS_EN

USB3_VBUS_EN

Right IO Board

+1.0V_RUN

TPS22966

(UZ20)

EM5209VF

(UZ26)

TPS2544

(UI1)

TPS2544

(UI1)

TPS2544

(UI3)

TPS2544

(UI5)

+5V_RUN

+5V_MXM

+5V_USB_PWR1

+5V_USB_PWR2

+5V_USB_PWR3

1

+5V_HDD

RUN_ON

3.3V_CAM_EN#

DMG2301U

(Q24)

EM5209VF

(UZ22)

+1.8V_RUN

+CAMERA_VDD

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Power Rail

LA-C551P

1

4 74Tuesday, August 18, 2015

1.0

5

SMBUS Address [0x9a]

AW44

BB43

MEM_SMBCLK

MEM_SMBDATA

PCH

D D

1D

AW42AW45

SML1_SMBDATA

SML1_SMBCLK

B6A5

1D

AY44

BB39

1A

LAN_SMBCLK

LAN_SMBDATA

2.2K

B4

DOCK_TNY_SMB_CLK

A3

DOCK_TNY_SMB_DAT

+3.3V_ALW_PCH

2.2K

4

2.2K

+3.3V_ALW_PCH

+3.3V_LAN

28

31

+3.3V_ALW

DMN66D0LDW

LOM

SMBUS Address [0xC8]

127

DOCKING

129

3

SMBUS Address

APR_EC: 0x48 SPR_EC: 0x70 MSLICE_EC: 0x72 USB: 0x59 AUDIO: 0x34 SLICE_BATTERY: 0x17 SLICE_CHARGER: 0x13

2

253

254

253

254

253

254

253

254

53

51

DIMM1

DIMM2

DIMM3

DIMM4

XDP1

SMBUS Address [A0h] A0h --> 1010 0000

SMBUS Address [A4h] A4h --> 1010 0100

SMBUS Address [TBD]

1

SMBUS Address SMB_ADM1032: 0x98 SMB_DIAG_DUMP: 0x04 SMB_DIAG_DUMP2: 0x05 SMB_BLACKTOP: 0x60

C C

2.2K

+3.3V_ALW

KBC

1C1CB59

1E

A56

A50

B53

PBAT_SMBCLK

PBAT_SMBDAT

USH_SMBCLK

USH_SMBDAT

2.2K 100 ohm

100 ohm

MEC 5085

2.2K

DMN66D0LDW

+3.3V_ALW

+3.3V_RUN

DMN66D0LDW

B B

B50

A47

B49

B48

CHARGER_SMBCLK

CHARGER_SMBDAT

UPD_GPU_SMBCLK

UPD_GPU_SMBDAT

1G

1H

A A

7

BATTERY

6

5

6

CONN

LYNX(CV2)

SMBUS Address [0x16]

SMBUS Address [0xa4]

4.7K

9

8

Charger

@4.7K

70

68

+3.3V_RUN

20

AAC

21

SMBUS Address [0xFF]

+3.3V_MXM

SMBUS Address [TBD]

MXM

4.7K

+3.3V_TBT_SX

4.7K

24

UPD

23

1

4

2.2K

+3.3V_RUN

LNG2DMTR

SMBUS Address [TBD]

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

SMBUS Bolck Diagram

LA-C551P

5 74Tuesday, August 18, 2015

1

1.0

5

4

3

2

1

PEG_CRX _C_GTX_P[0..15]

PEG_CRX _C_GTX_N[0..15]

PEG_CTX _C_GRX_P[0..15]

?

SKYLAKE_HALO

E25

PEG_RXP[0]

D25

PEG_RXN[0]

E24

PEG_RXP[1]

F24

PEG_RXN[1]

E23

PEG_RXP[2]

D23

PEG_RXN[2]

E22

PEG_RXP[3]

F22

PEG_RXN[3]

E21

PEG_RXP[4]

D21

PEG_RXN[4]

E20

PEG_RXP[5]

F20

PEG_RXN[5]

E19

PEG_RXP[6]

D19

PEG_RXN[6]

E18

PEG_RXP[7]

F18

PEG_RXN[7]

D17

PEG_RXP[8]

E17

PEG_RXN[8]

F16

PEG_RXP[9]

E16

PEG_RXN[9]

D15

PEG_RXP[10]

E15

PEG_RXN[10]

F14

PEG_RXP[11]

E14

PEG_RXN[11]

D13

PEG_RXP[12]

E13

PEG_RXN[12]

F12

PEG_RXP[13]

E12

PEG_RXN[13]

D11

PEG_RXP[14]

E11

PEG_RXN[14]

F10

PEG_RXP[15]

E10

PEG_RXN[15]

G2

PEG_RCOMP

D8

DMI_RXP[0]

E8

DMI_RXN[0]

E6

DMI_RXP[1]

F6

DMI_RXN[1]

D5

DMI_RXP[2]

E5

DMI_RXN[2]

J8

DMI_RXP[3]

J9

DMI_RXN[3]

REV = 1

SKL-H_BG A1440

CPU1C

3

BGA1440

3 OF 14

PEG_TXP[0] PEG_TXN[0]

PEG_TXP[1] PEG_TXN[1]

PEG_TXP[2] PEG_TXN[2]

PEG_TXP[3] PEG_TXN[3]

PEG_TXP[4] PEG_TXN[4]

PEG_TXP[5] PEG_TXN[5]

PEG_TXP[6] PEG_TXN[6]

PEG_TXP[7] PEG_TXN[7]

PEG_TXP[8] PEG_TXN[8]

PEG_TXP[9] PEG_TXN[9]

PEG_TXP[10] PEG_TXN[10]

PEG_TXP[11] PEG_TXN[11]

PEG_TXP[12] PEG_TXN[12]

PEG_TXP[13] PEG_TXN[13]

PEG_TXP[14] PEG_TXN[14]

PEG_TXP[15] PEG_TXN[15]

DMI_TXP[0] DMI_TXN[0]

DMI_TXP[1] DMI_TXN[1]

DMI_TXP[2] DMI_TXN[2]

DMI_TXP[3] DMI_TXN[3]

PEG_CTX _GRX_P15

B25

PEG_CTX _GRX_N15

A25

PEG_CTX _GRX_P14

B24

PEG_CTX _GRX_N14

C24

PEG_CTX _GRX_P13

B23

PEG_CTX _GRX_N13

A23

PEG_CTX _GRX_P12

B22

PEG_CTX _GRX_N12

C22

PEG_CTX _GRX_P11

B21

PEG_CTX _GRX_N11

A21

PEG_CTX _GRX_P10

B20

PEG_CTX _GRX_N10

C20

PEG_CTX _GRX_P9 PEG_CTX _C_GRX_P9

B19 A19

PEG_CTX _GRX_P8

B18

PEG_CTX _GRX_N8

C18

PEG_CTX _GRX_P7

A17

PEG_CTX _GRX_N7

B17

PEG_CTX _GRX_P6

C16

PEG_CTX _GRX_N6

B16

PEG_CTX _GRX_P5 PEG_CTX _C_GRX_P5

A15 B15

PEG_CTX _GRX_P4

C14

PEG_CTX _GRX_N4

B14

PEG_CTX _GRX_P3 PEG_CTX _C_GRX_P3

A13

PEG_CTX _GRX_N3 PEG_CTX_C _GRX_N3

B13

PEG_CTX _GRX_P2

C12

PEG_CTX _GRX_N2

B12

PEG_CTX _GRX_P1

A11

PEG_CTX _GRX_N1

B11

PEG_CTX _GRX_P0

C10

PEG_CTX _GRX_N0

B10

DMI_CTX_P RX_P0

B8

DMI_CTX_P RX_N0

A8

DMI_CTX_P RX_P1

C6

DMI_CTX_P RX_N1DMI_CRX_P TX_N1

B6

DMI_CTX_P RX_P2

B5

DMI_CTX_P RX_N2

A5

D4 B4

?

2

D D

12

PEG_CRX _C_GTX_N15

PEG_CRX _C_GTX_N14

PEG_CRX _C_GTX_N13

PEG_CRX _C_GTX_N12

PEG_CRX _C_GTX_N11

PEG_CRX _C_GTX_P10 PEG_CRX _C_GTX_N10

PEG_CRX _C_GTX_P9 PEG_CRX _C_GTX_N9

C C

B B

PEG_COM P

CAD Note:

CAD Note:CAD Note: Trace width=12 mils

Trace width=12 mils

Trace width=12 milsTrace width=12 mils ,Spacing=15mil

,Spacing=15mil

,Spacing=15mil,Spacing=15mil Max length= 400 mils.

Max length= 400 mils.

Max length= 400 mils.Max length= 400 mils.

A A

5

PEG_CRX _C_GTX_P8 PEG_CRX _C_GTX_N8

PEG_CRX _C_GTX_P7 PEG_CRX _C_GTX_N7

PEG_CRX _C_GTX_P6 PEG_CRX _C_GTX_N6

PEG_CRX _C_GTX_P5 PEG_CRX _C_GTX_N5

PEG_CRX _C_GTX_N4

PEG_CRX _C_GTX_N3

PEG_CRX _C_GTX_N2

PEG_CRX _C_GTX_N1

PEG_CRX _C_GTX_P0 PEG_CRX _C_GTX_N0

+VCC_IO

12

RC224.9_040 2_1%

CC32 0.22U_04 02_10V6K

12

CC16 0.22U_04 02_10V6K

12

CC31 0.22U_04 02_10V6K

12

CC15 0.22U_04 02_10V6K

12

CC30 0.22U_04 02_10V6K

12

CC14 0.22U_04 02_10V6K

12

CC29 0.22U_04 02_10V6K

12

CC13 0.22U_04 02_10V6K

12

CC28 0.22U_04 02_10V6K

12

CC12 0.22U_04 02_10V6K

12

CC27 0.22U_04 02_10V6K

12

CC11 0.22U_04 02_10V6K

12

CC26 0.22U_04 02_10V6K

12

CC10 0.22U_04 02_10V6K

12

CC25 0.22U_04 02_10V6K

12

CC9 0.22U_04 02_10V6K

12

CC24 0.22U_04 02_10V6K

12

CC8 0.22U_04 02_10V6K

12

CC23 0.22U_04 02_10V6K

12

CC7 0.22U_04 02_10V6K

12

CC22 0.22U_04 02_10V6K

12

CC6 0.22U_04 02_10V6K

12

CC21 0.22U_04 02_10V6K

12

CC5 0.22U_04 02_10V6K

12

CC20 0.22U_04 02_10V6K

12

CC4 0.22U_04 02_10V6K

12

CC19 0.22U_04 02_10V6K

12

CC3 0.22U_04 02_10V6K

12

CC18 0.22U_04 02_10V6K

12

CC2 0.22U_04 02_10V6K

12

CC17 0.22U_04 02_10V6K

12

CC1 0.22U_04 02_10V6K

DMI_CRX_P TX_P0<20> DMI_CRX_P TX_N0<20>

DMI_CRX_P TX_P1<20> DMI_CRX_P TX_N1<20>

DMI_CRX_P TX_P2<20> DMI_CRX_P TX_N2<20>

DMI_CRX_P TX_P3<20> DMI_CRX_P TX_N3<20>

4

PEG_CRX _GTX_P15PEG_CRX _C_GTX_P15 PEG_CRX _GTX_N15

PEG_CRX _GTX_P14PEG_CRX _C_GTX_P14 PEG_CRX _GTX_N14

PEG_CRX _GTX_P13PEG_CRX _C_GTX_P13 PEG_CRX _GTX_N13

PEG_CRX _GTX_P12PEG_CRX _C_GTX_P12 PEG_CRX _GTX_N12

PEG_CRX _GTX_P11PEG_CRX _C_GTX_P11 PEG_CRX _GTX_N11

PEG_CRX _GTX_P10 PEG_CRX _GTX_N10

PEG_CRX _GTX_P9 PEG_CRX _GTX_N9

PEG_CRX _GTX_P8 PEG_CRX _GTX_N8

PEG_CRX _GTX_P7 PEG_CRX _GTX_N7

PEG_CRX _GTX_P6 PEG_CRX _GTX_N6

PEG_CRX _GTX_P5 PEG_CRX _GTX_N5

PEG_CRX _GTX_P4PEG_CR X_C_GTX_P4 PEG_CRX _GTX_N4

PEG_CRX _GTX_P3PEG_CR X_C_GTX_P3 PEG_CRX _GTX_N3

PEG_CRX _GTX_P2PEG_CR X_C_GTX_P2 PEG_CRX _GTX_N2

PEG_CRX _GTX_P1PEG_CR X_C_GTX_P1 PEG_CRX _GTX_N1

PEG_CRX _GTX_P0 PEG_CRX _GTX_N0

PEG_COM P

DMI_CRX_P TX_P0 DMI_CRX_P TX_N0

DMI_CRX_P TX_P1

DMI_CRX_P TX_P2 DMI_CRX_P TX_N2

DMI_CRX_P TX_P3 DMI_CTX_P RX_P3 DMI_CRX_P TX_N3 DMI_CTX_P RX_N3

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

PEG_CTX _C_GRX_N[0..15]

12

CC64 0.22U_04 02_10V6K

12

CC50 0.22U_04 02_10V6K

12

CC63 0.22U_04 02_10V6K

12

CC77 0.22U_04 02_10V6K

12

CC72 0.22U_04 02_10V6K

12

CC62 0.22U_04 02_10V6K

12

CC61 0.22U_04 02_10V6K

12

CC49 0.22U_04 02_10V6K

12

CC60 0.22U_04 02_10V6K

12

CC76 0.22U_04 02_10V6K

12

CC71 0.22U_04 02_10V6K

12

CC59 0.22U_04 02_10V6K

12

CC58 0.22U_04 02_10V6K

12

CC48 0.22U_04 02_10V6K

12

CC57 0.22U_04 02_10V6K

12

CC75 0.22U_04 02_10V6K

12

CC70 0.22U_04 02_10V6K

12

CC56 0.22U_04 02_10V6K

12

CC55 0.22U_04 02_10V6K

12

CC47 0.22U_04 02_10V6K

12

CC54 0.22U_04 02_10V6K

12

CC74 0.22U_04 02_10V6K

12

CC69 0.22U_04 02_10V6K

12

CC46 0.22U_04 02_10V6K

12

CC52 0.22U_04 02_10V6K

12

CC73 0.22U_04 02_10V6K

12

CC51 0.22U_04 02_10V6K

12

CC53 0.22U_04 02_10V6K

12

CC68 0.22U_04 02_10V6K

12

CC45 0.22U_04 02_10V6K

12

CC67 0.22U_04 02_10V6K

12

CC44 0.22U_04 02_10V6K

DMI_CTX_P RX_P0 <20> DMI_CTX_P RX_N0 <20>

DMI_CTX_P RX_P1 <20> DMI_CTX_P RX_N1 <20>

DMI_CTX_P RX_P2 <20> DMI_CTX_P RX_N2 <20>

DMI_CTX_P RX_P3 <20> DMI_CTX_P RX_N3 <20>

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

Size Docu ment Number Rev

Date: Sheet of

Compal Electronics, Inc.

SKYLAKE-H (1/8)

PEG_CRX _C_GTX_P[0..15] <18>

PEG_CRX _C_GTX_N[0..15] <18>

PEG_CTX _C_GRX_P[0..15] <18>

PEG_CTX _C_GRX_N[0..15] <18>

PEG_CTX _C_GRX_P15 PEG_CTX _C_GRX_N15

PEG_CTX _C_GRX_P14 PEG_CTX _C_GRX_N14

PEG_CTX _C_GRX_P13 PEG_CTX _C_GRX_N13

PEG_CTX _C_GRX_P12 PEG_CTX _C_GRX_N12

PEG_CTX _C_GRX_P11 PEG_CTX _C_GRX_N11

PEG_CTX _C_GRX_P10 PEG_CTX _C_GRX_N10

PEG_CTX _C_GRX_N9PEG_CTX _GRX_N9

PEG_CTX _C_GRX_P8 PEG_CTX _C_GRX_N8

PEG_CTX _C_GRX_P7 PEG_CTX _C_GRX_N7

PEG_CTX _C_GRX_P6 PEG_CTX _C_GRX_N6

PEG_CTX _C_GRX_N5PEG_CTX _GRX_N5

PEG_CTX _C_GRX_P4 PEG_CTX _C_GRX_N4

PEG_CTX _C_GRX_P2 PEG_CTX _C_GRX_N2

PEG_CTX _C_GRX_P1 PEG_CTX _C_GRX_N1

PEG_CTX _C_GRX_P0 PEG_CTX _C_GRX_N0

LA-C551P

1

1.0

6 74Tuesday, August 18 , 2015

1.0

5

+1.0V_PRIM

D D

RC216 0_0603_1%@

1 2

+1.0V_PRIM_XDP

0.1U_0402_25V6

12

+1.0V_PRIM_XDP

0.1U_0402_25V6

@

12

CC33

CC37

@

Place near JXDP1

RC5 need to close to JCPU1

PCH_RSMRST#_R H_VCCST_PWRGD_XDP

@

T191

PAD~D

SIO_PWRBTN#<23,46>

+1.0V_PRIM_XDP

+VCC_IO

H_PROCHOT#

+1.0V_VCCST

12

CFG0

PCH_SPI_D0<22,37>

RESET_OUT#<23,46>

10/23 Intel review

100_0402_5%

56.2_0402_1%

12

RC155

220_0402_5%

RC156

VR_SVID_DATA

CPU_VIDALERT#

RC327 0_0402_5%@

UC5

10/23 Intel review

CPU_XDP_PREQ#

C C

FIVR_EN_R

+1.0V_VCCST

+1.0V_VCCSTG

B B

VR_SVID_DATA<61,64>

VR_SVID_ALERT#<61,64>

A A

1 2

RC138 51_0402_5%@

1 2

RC132 150_0402_5%

12

1 2

RC180 1K_0402_5%

VR_SVID_DATA

VR_SVID_ALERT#

IMVP_VR_ON_EC<46>

SIO_SLP_S3#<11,23,37,44,46>

PCH_THERMTRIP#

RC3261K_0402_5%

PCH_JTAGX

RC1661K_0402_5% @

VCCST_PWRGD

RC1641K_0402_5%

H_CATERR#

RC17249.9_0402_1% @

SN74AHC1G08DCKR _SC70-5

5

RC157

1 2

+3.3V_ALW

1

IN1

2

IN2

PCH_JTAG_TCK<23>

5

P

G

3

1 2

RC124

XDP@ 1K_ 0402_5%

1 2

RC217 0_0402_5%@ RC126 1K_0402_5%XDP@

1 2 1 2

RC128 0_0402_5%XDP@

1 2

RC129 0_0402_5%@

DDR_XDP_WAN_SMBDAT<14,15,16,17,23,41>

DDR_XDP_WAN_SMBCLK<14,15,16,17,23,41>

PCH_RSMRST#<46>

ALW_PWRGD_3V_5V<51>

DDR_PG_CTRL<14>

IMVP_VR_ON

4

O

PCH_RSMRST#

VR_SVID_CLK<61,64>

H_PROCHOT#<46,57,61,64>

VCCST_PWRGD<46>

H_PWRGD<23> PLTRST_CPU#<19>

H_PM_SYNC_R<19> H_PM_DOWN<19> H_PECI<19,46>

PCH_THERMTRIP#<14,15,16,17,19,46>

IMVP_VR_ON <55,56,61,64>

CPU_XDP_PREQ# CPU_XDP_PRDY#

CFG0 CFG1

CFG2 CFG3

XDP_OBS0_R XDP_OBS1_R

CFG4 CFG5

CFG6 CFG7

SIO_PWRBTN#

FIVR_EN_R

SYS_PWROK_R

PCH_JTAG_TCK CPU_XDP_TCLK

PCH_CPU_BCLK_R_D<21> PCH_CPU_BCLK_R_D#<21>

PCH_CPU_PCIBCLK_R_D<21> PCH_CPU_PCIBCLK_R_D#<21>

CPU_24MHZ_R_D<21> CPU_24MHZ_R_D#<21>

VR_SVID_CLK

DDR_PG_CTRL

H_PWRGD PLTRST_CPU#

H_PECI

UC6

NC1VCC

2

A

3

GND

74AUP1G07GW_TSSO P5

4

+1.0V_PRIM_XDP

XDP_PRSNT_PIN1

JXDP1

1

GND0

3

OBSFN_A0

5

OBSFN_A1

7

GND2 OBSDATA_A09OBSDATA_C0 OBSDATA_A111OBSDATA_C1

13

GND4 OBSDATA_A215OBSDATA_C2 OBSDATA_A317OBSDATA_C3

19

GND6

21

OBSFN_B0

23

OBSFN_B1

25

GND8 OBSDATA_B027OBSDATA_D0 OBSDATA_B129OBSDATA_D1

31

GND10 OBSDATA_B233OBSDATA_D2 OBSDATA_B335OBSDATA_D3

37

GND12 PWRGOOD/HOOK039ITPCLK/HOOK4

41

HOOK1 VCC_OBS_AB43VCC_OBS_CD

45

HOOK2

47

HOOK3

49

GND14

51

SDA

53

SCL

55

TCK1

57

TCK0

59

GND16

+3.3V_ALW

CH17

1 2

0.1U_0402_25V6K

UC4

5

SN74AHC1G08DCKR _SC70-5

1

P

IN1

PM_RSMRST#_AND PCH_RSMRST#_R

4

O

2

IN2

G

3

PCH_CPU_BCLK_R_D PCH_CPU_BCLK_R_D #

PCH_CPU_PCIBCLK_R_ D PCH_CPU_PCIBCLK_R_ D#

CPU_24MHZ_R_D CPU_24MHZ_R_D#

1 2

RC158 499_0402_1%

1 2

RC159 60.4_0 402_1%

1 2 1 2

RC167 30_0402_5% RC168 20_0402_5%

1 2

RC169 0_0402_5%@

1 2 1 2

RC319 0_0402_5%@ RC171 0_0402_5%@

+3.3V_ALW

5

VCCST_PWRGD

4

Y

4

CPU XDP

CPU XDPCPU XDP

XDP@

1 2

CFG3

RC121 1K_0402_5%

1 2

RC122 0_0402_5%@

ITPCLK#/HOOK5

RESET#/HOOK6

DBR#/HOOK7

RC154 0_0402_5%@

CPU_VIDALERT#

VR_SVID_DATA H_PROCHOT#_RH_PROCHOT#

VCCST_PWRGD_C PUVCCST_PWRGD

H_PM_SYNCH_PM_SYNC_R H_PM_DOWN_RH_PM_DOWN

H_THERMTRIP#PCH_THERM TRIP#

H_SKTOCC# SKL_CNL#

H_CATERR#

GND1 OBSFN_C0 OBSFN_C1

GND3

GND5

GND7 OBSFN_D0 OBSFN_D1

GND9

GND11

GND13

GND15

TRST#

GND17

CONN@SAMTE_BSH-0 30-01-L-D-A

1 2

B31 A32

D35 C36

E31 D31

BH31 BH32 BH29 BR30

BT13

H13

BT31 BP35 BM34 BP31 BT34

J31

BR33

BN1

BM30

TD0

TDI

TMS

CPU1E

BCLKP BCLKN

PCI_BCLKP PCI_BCLKN

CLK24P CLK24N

VIDALERT# VIDSCK VIDSOUT PROCHOT#

DDR_VTT_CNTL

VCCST_PWRGD

PROCPWRGD RESET# PM_SYNC PM_DOWN PECI THERMTRIP#

SKTOCC# PROC_SELECT#

CATERR#

REV = 1

+1.0V_PRIM_XDP

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60

CFG17 CFG16

CFG8 CFG9

CFG10 CFG11

CFG19 CFG18

CFG12 CFG13

CFG14 CFG15

PCH_XDP_CLK_DP PCH_XDP_CLK_DN

CPU_XDP_HOOK6 XDP_DBRESET#

CPU_XDP_TDO CPU_XDP_TRST# CPU_XDP_TDI CPU_XDP_TMS CPU_XDP_PRS

12

RC318 47K_0402_5%

?

SKYLAKE_HALO

BGA1440

5 OF 14

3

PCH_XDP_CLK_DP <21> PCH_XDP_CLK_DN <21>

1 2

RC144 0_0402_5%XDP@

XDP_DBRESET# <20>

CPU_XDP_TRST# <25>

1 2

RC127 1K_0402_5%XDP@

PCH_RSMRST#_R <23>

BN25

CFG[0]

BN27

CFG[1]

BN26

CFG[2]

BN28

CFG[3]

BR20

CFG[4]

BM20

CFG[5]

BT20

CFG[6]

BP20

CFG[7]

BR23

CFG[8]

BR22

CFG[9]

BT23

CFG[10]

BT22

CFG[11]

BM19

CFG[12]

BR19

CFG[13]

BP19

CFG[14]

BT19

CFG[15]

BN23

CFG[17]

BP23

CFG[16]

BP22

CFG[19]

BN22

CFG[18]

BR27

BPM#[0]

BT27

BPM#[1]

BM31

BPM#[2]

BT30

BPM#[3]

BT28

PROC_TDO

BL32

PROC_TDI

BP28

PROC_TMS

BR28

PROC_TCK

BP30

PROC_TRST#

BL30

PROC_PREQ#

BP27

PROC_PRDY#

BT25

CFG_RCOMP

?

3

ITP_PMODE_CPU

PCH_SPI_D2_XDP

Place near JXDP1.41

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15

CFG17 CFG16 CFG19 CFG18

XDP_OBS0 XDP_OBS1

CPU_XDP_TDO CPU_XDP_TDI CPU_XDP_TMS CPU_XDP_TCLK

CPU_XDP_TRST# CPU_XDP_PREQ# CPU_XDP_PRDY#

12

RC222

49.9_0402_1%

2

CPU_XDP_HOOK6

1 2

RC6 2.2K_0402_5%

XDP@

10/23 Intel review

XDP_DBRESET#

PCH_SPI_D0

ITP_PMODE_CPU <23>

PCH_SPI_D2_XDP <22>

+3.3V_ALW

SIO_PWRBTN#

1 2 1 2

RC312 0_0402_5%@ RC313 0_0402_5%@

PAD~D PAD~D PAD~D PAD~D

PAD~D PAD~D PAD~D

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

EDS0.7

1.5K_0402_5%

XDP@

12

RC241

0.1U_0402_25V6

XDP@

12

CC269

CPU_XDP_TDO

CPU_XDP_TRST#

CPU_XDP_TCLK

CPU_XDP_TMS

CPU_XDP_TDI

CPU_XDP_TDO

CPU_XDP_TCLK

CPU_XDP_PREQ#

CPU_XDP_PRDY#

XDP_OBS0_R XDP_OBS1_R

@

T184

@

T185

@

T180

@

T181

@

T179

@

T190

@

T189

1 2

RC316 1.5K_0402_5%

XDP@

1 2

RC133 1.5K_0402_5%XDP@

1 2

RC307 0_0402_5%@

1 2

RC308 0_0402_5%@

1 2

RC309 0_0402_5%@

1 2

RC143 0_0402_5%

1 2

RC315 0_0402_5%@XDP@

1 2

RC314 0_0402_5%@XDP@

2

12

RC13551_0402_5%

12

RC33051_0402_5%

12

RC30651_0402_5%

PCH_JTAG_TMS <23>

PCH_JTAG_TDI <23>

PCH_JTAG_TDO <23>

PCH_JTAGX <23>

PCH_XDP_PREQ# <25>

PCH_XDP_PRDY# <25>

+1.0V_PRIM_XDP

+3.3V_ALW_PCH

+1.0V_VCCSTG

XDP_DBRESET#

RC143 for XDP debug

1

+3.3V_SPI

12

RC5

2.2K_0402_5%

0.1U_0402_25V6

CC35

12

XDP@

SYS_PWROK_R

0.1U_0402_25V6

12

CC36@

Place near JXDP1.47

CFG0

CFG2

CFG4

CFG5

CFG6

CFG7

Title

Size Document Number Rev

Date: Sheet of

Stall reset sequence after PCU

12

PLL lock until de-asserted

RC321

@

1K_0402_5%

No Stall

Stall

12

PEG LANE REVERSAL

RC181 1K_0402_5%

*

12

RC322 1K_0402_5%

PCI Express* Bifurcation

12

RC323

@

1K_0402_5%

1x8, 2x4

Reserved

2x8

RC324

@

1K_0402_5%

1x16

PEG Training

(default) PEG Train immediately following RESET# de-assertion

PEG Wait for BIOS for training

Compal Electronics, Inc.

SKYLAKE-H (2/8)

LA-C551P

1

12

RC325

@

1K_0402_5%

NORMAL

LANE REVERSED

eDP enable

Disabled

Enabled

1

0

1

0

1

0

[6:5]

00

01

10

11

1

0

7 74Tuesday, August 18, 2015

1.0

SKL-H_BGA1440

5

DDR_A_D[0 ..63]<14,15>

D D

C C

DDR_A_CB[ 0..7]<14,15 >

B B

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

DDR_A_CB0 DDR_A_CB1 DDR_A_CB2 DDR_A_CB3 DDR_A_CB4 DDR_A_CB5 DDR_A_CB6 DDR_A_CB7

CPU1A

BR6

DDR0_DQ[0]

BT6

DDR0_DQ[1]

BP3

DDR0_DQ[2]

BR3

DDR0_DQ[3]

BN5

DDR0_DQ[4]

BP6

DDR0_DQ[5]

BP2

DDR0_DQ[6]

BN3

DDR0_DQ[7]

BL4

DDR0_DQ[8]

BL5

DDR0_DQ[9]

BL2

DDR0_DQ[10]

BM1

DDR0_DQ[11]

BK4

DDR0_DQ[12]

BK5

DDR0_DQ[13]

BK1

DDR0_DQ[14]

BK2

DDR0_DQ[15]

BG4

DDR0_DQ[16]/DDR0_DQ[32]

BG5

DDR0_DQ[17]/DDR0_DQ[33]

BF4

DDR0_DQ[18]/DDR0_DQ[34]

BF5

DDR0_DQ[19]/DDR0_DQ[35]

BG2

DDR0_DQ[20]/DDR0_DQ[36]

BG1

DDR0_DQ[21]/DDR0_DQ[37]

BF1

DDR0_DQ[22]/DDR0_DQ[38]

BF2

DDR0_DQ[23]/DDR0_DQ[39]

BD2

DDR0_DQ[24]/DDR0_DQ[40]

BD1

DDR0_DQ[25]/DDR0_DQ[41]

BC4

DDR0_DQ[26]/DDR0_DQ[42]

BC5

DDR0_DQ[27]/DDR0_DQ[43]

BD5

DDR0_DQ[28]/DDR0_DQ[44]

BD4

DDR0_DQ[29]/DDR0_DQ[45]

BC1

DDR0_DQ[30]/DDR0_DQ[46]

BC2

DDR0_DQ[31]/DDR0_DQ[47]

AB1

DDR0_DQ[32]/DDR1_DQ[0]

AB2

DDR0_DQ[33]/DDR1_DQ[1]

AA4

DDR0_DQ[34]/DDR1_DQ[2]

AA5

DDR0_DQ[35]/DDR1_DQ[3]

AB5

DDR0_DQ[36]/DDR1_DQ[4]

AB4

DDR0_DQ[37]/DDR1_DQ[5]

AA2

DDR0_DQ[38]/DDR1_DQ[6]

AA1

DDR0_DQ[39]/DDR1_DQ[7]

V5

DDR0_DQ[40]/DDR1_DQ[8]

V2

DDR0_DQ[41]/DDR1_DQ[9]

U1

DDR0_DQ[42]/DDR1_DQ[10]

U2

DDR0_DQ[43]/DDR1_DQ[11]

V1

DDR0_DQ[44]/DDR1_DQ[12]

V4

DDR0_DQ[45]/DDR1_DQ[13]

U5

DDR0_DQ[46]/DDR1_DQ[14]

U4

DDR0_DQ[47]/DDR1_DQ[15]

R2

DDR0_DQ[48]/DDR1_DQ[32]

P5

DDR0_DQ[49]/DDR1_DQ[33]

R4

DDR0_DQ[50]/DDR1_DQ[34]

P4

DDR0_DQ[51]/DDR1_DQ[35]

R5

DDR0_DQ[52]/DDR1_DQ[36]

P2

DDR0_DQ[53]/DDR1_DQ[37]

R1

DDR0_DQ[54]/DDR1_DQ[38]

P1

DDR0_DQ[55]/DDR1_DQ[39]

M4

DDR0_DQ[56]/DDR1_DQ[40]

M1

DDR0_DQ[57]/DDR1_DQ[41]

L4

DDR0_DQ[58]/DDR1_DQ[42]

L2

DDR0_DQ[59]/DDR1_DQ[43]

M5

DDR0_DQ[60]/DDR1_DQ[44]

M2

DDR0_DQ[61]/DDR1_DQ[45]

L5

DDR0_DQ[62]/DDR1_DQ[46]

L1

DDR0_DQ[63]/DDR1_DQ[47]

BA2

DDR0_ECC[0]

BA1

DDR0_ECC[1]

AY4

DDR0_ECC[2]

AY5

DDR0_ECC[3]

BA5

DDR0_ECC[4]

BA4

DDR0_ECC[5]

AY1

DDR0_ECC[6]

AY2

DDR0_ECC[7]

DDR CHANNEL A

SKL-H_BG A1440

SKYLAKE_HALO

BGA1440

4

?

DDR0_CKP[0] DDR0_CKN[0] DDR0_CKN[1] DDR0_CKP[1]

DDR0_CLKP[2] DDR0_CLKN[2] DDR0_CLKP[3] DDR0_CLKN[3]

DDR0_CKE[0] DDR0_CKE[1] DDR0_CKE[2] DDR0_CKE[3]

DDR0_CS#[0]

DDR0_CS#[1]

DDR0_CS#[2]

DDR0_CS#[3]

DDR0_ODT[0] DDR0_ODT[1] DDR0_ODT[2]

DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]

DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]

DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]

DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]

DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]

DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8]

DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]

DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT#

1 OF 14

DDR0_ODT[3]

DDR0_MA[3] DDR0_MA[4]

DDR0_PAR

DDR0_ALERT#

DDR0_DQSN[0]

DDR0_DQSN[1] DDR0_DQSN[2]/DDR0_DQSN[4] DDR0_DQSN[3]/DDR0_DQSN[5] DDR0_DQSP[4]/DDR1_DQSP[0] DDR0_DQSP[5]/DDR1_DQSP[1] DDR0_DQSP[6]/DDR1_DQSP[4] DDR0_DQSP[7]/DDR1_DQSP[5]

DDR0_DQSP[0]

DDR0_DQSP[1] DDR0_DQSP[2]/DDR0_DQSP[4] DDR0_DQSP[3]/DDR0_DQSP[5] DDR0_DQSN[4]/DDR1_DQSN[0] DDR0_DQSN[5]/DDR1_DQSN[1] DDR0_DQSN[6]/DDR1_DQSN[4] DDR0_DQSN[7]/DDR1_DQSN[5]

DDR0_DQSP[8]

DDR0_DQSN[8]

3

DDR_A_CLK 0 DDR_B_CLK #0

AG1

DDR_A_CLK #0

AG2

DDR_A_CLK #1 DDR_B_CLK 1

AK1

DDR_A_CLK 1

AK2

DDR_A_CLK 2

AL3

DDR_A_CLK #2

AK3

DDR_A_CLK 3

AL2

DDR_A_CLK #3

AL1

DDR_A_CKE 0

AT1

DDR_A_CKE 1

AT2

DDR_A_CKE 2

AT3

DDR_A_CKE 3

AT5

DDR_A_CS# 0

AD5

DDR_A_CS# 1

AE2

DDR_A_CS# 2

AD2

DDR_A_CS# 3

AE5

DDR_A_ODT0

AD3

DDR_A_ODT1

AE4

DDR_A_ODT2

AE1

DDR_A_ODT3

AD4

DDR_A_BA 0

AH5

DDR_A_BA 1

AH1

DDR_A_BG 0

AU1

DDR_A_MA1 6

AH4

DDR_A_MA1 4

AG4

DDR_A_MA1 5

AD1

DDR_A_MA0

AH3

DDR_A_MA1

AP4

DDR_A_MA2

AN4

DDR_A_MA3

AP5

DDR_A_MA4

AP2

DDR_A_MA5

AP1

DDR_A_MA6

AP3

DDR_A_MA7

AN1

DDR_A_MA8

AN3

DDR_A_MA9

AT4

DDR_A_MA1 0

AH2

DDR_A_MA1 1

AN2

DDR_A_MA1 2

AU4

DDR_A_MA1 3

AE3

DDR_A_BG 1

AU2

DDR_A_ACT#

AU3

DDR_A_PA RITY

AG3

DDR_A_AL ERT#

AU5

DDR_A_DQS #0

BR5

DDR_A_DQS #1

BL3

DDR_A_DQS #2

BG3

DDR_A_DQS #3

BD3

DDR_A_DQS 4

AB3

DDR_A_DQS 5

V3

DDR_A_DQS 6

R3

DDR_A_DQS 7

M3

DDR_A_DQS 0

BP5

DDR_A_DQS 1

BK3

DDR_A_DQS 2

BF3

DDR_A_DQS 3

BC3

DDR_A_DQS #4

AA3

DDR_A_DQS #5

U3

DDR_A_DQS #6

P3

DDR_A_DQS #7

L3

DDR_A_DQS 8

AY3

DDR_A_DQS #8

BA3

?REV = 1

DDR_B_D[0 ..63]<1 6,17>

DDR_A_CLK 0 <15> DDR_A_CLK #0 <15> DDR_A_CLK #1 <15> DDR_A_CLK 1 <15> DDR_A_CLK 2 <14> DDR_A_CLK #2 <14> DDR_A_CLK 3 <14> DDR_A_CLK #3 <14>

DDR_A_CKE 0 <15> DDR_A_CKE 1 <15> DDR_A_CKE 2 <14> DDR_A_CKE 3 <14>

DDR_A_CS# 0 <15> DDR_A_CS# 1 <15> DDR_A_CS# 2 <14> DDR_A_CS# 3 <14>

DDR_A_ODT0 <15> DDR_A_ODT1 <15> DDR_A_ODT2 <14> DDR_A_ODT3 <14>

DDR_A_BA 0 < 14,15> DDR_A_BA 1 < 14,15> DDR_A_BG 0 < 14,15>

DDR_A_MA1 6 <1 4,15> DDR_A_MA1 4 <1 4,15> DDR_A_MA1 5 <1 4,15>

DDR_A_MA[ 0..13] <14,15>

DDR_A_BG 1 < 14,15> DDR_A_ACT# <14,15>

DDR_A_PA RITY <14,15> DDR_A_AL ERT# <14,15>

DDR_A_DQS #[0..3] <14,1 5>

DDR_A_DQS [4..7] <14,15 >

DDR_A_DQS [0..3] <14,15 >

DDR_B_CB[ 0..7]<16,17 >

DDR_A_DQS #[4..7] <14,1 5>

DDR_A_DQS 8 <14,15 > DDR_A_DQS #8 <14,1 5>

RD18 121_04 02_1% RD21 75_040 2_1% RD22 100_04 02_1%

1 2 1 2 1 2

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

DDR_B_CB0 DDR_B_CB1 DDR_B_CB2 DDR_B_CB3 DDR_B_CB4 DDR_B_CB5 DDR_B_CB6 DDR_B_CB7

DDR_RCOMP0 DDR_RCOMP1 DDR_RCOMP2

CPU1B

BT11

DDR1_DQ[0]/DDR0_DQ[16]

BR11

DDR1_DQ[1]/DDR0_DQ[17]

BT8

DDR1_DQ[2]/DDR0_DQ[18]

BR8

DDR1_DQ[3]/DDR0_DQ[19]

BP11

DDR1_DQ[4]/DDR0_DQ[20]

BN11

DDR1_DQ[5]/DDR0_DQ[21]

BP8

DDR1_DQ[6]/DDR0_DQ[22]

BN8

DDR1_DQ[7]/DDR0_DQ[23]

BL12

DDR1_DQ[8]/DDR0_DQ[24]

BL11

DDR1_DQ[9]/DDR0_DQ[25]

BL8

DDR1_DQ[10]/DDR0_DQ[26]

BJ8

DDR1_DQ[11]/DDR0_DQ[27]

BJ11

DDR1_DQ[12]/DDR0_DQ[28]

BJ10

DDR1_DQ[13]/DDR0_DQ[29]

BL7

DDR1_DQ[14]/DDR0_DQ[30]

BJ7

DDR1_DQ[15]/DDR0_DQ[31]

BG11

DDR1_DQ[16]/DDR0_DQ[48]

BG10

DDR1_DQ[17]/DDR0_DQ[49]

BG8

DDR1_DQ[18]/DDR0_DQ[50]

BF8

DDR1_DQ[19]/DDR0_DQ[51]

BF11

DDR1_DQ[20]/DDR0_DQ[52]

BF10

DDR1_DQ[21]/DDR0_DQ[53]

BG7

DDR1_DQ[22]/DDR0_DQ[54]

BF7

DDR1_DQ[23]/DDR0_DQ[55]

BB11

DDR1_DQ[24]/DDR0_DQ[56]

BC11

DDR1_DQ[25]/DDR0_DQ[57]

BB8

DDR1_DQ[26]/DDR0_DQ[58]

BC8

DDR1_DQ[27]/DDR0_DQ[59]

BC10

DDR1_DQ[28]/DDR0_DQ[60]

BB10

DDR1_DQ[29]/DDR0_DQ[61]

BC7

DDR1_DQ[30]/DDR0_DQ[62]

BB7

DDR1_DQ[31]/DDR0_DQ[63]

AA11

DDR1_DQ[32]/DDR1_DQ[16]

AA10

DDR1_DQ[33]/DDR1_DQ[17]

AC11

DDR1_DQ[34]/DDR1_DQ[18]

AC10

DDR1_DQ[35]/DDR1_DQ[19]

AA7

DDR1_DQ[36]/DDR1_DQ[20]

AA8

DDR1_DQ[37]/DDR1_DQ[21]

AC8

DDR1_DQ[38]/DDR1_DQ[22]

AC7

DDR1_DQ[39]/DDR1_DQ[23]

W8

DDR1_DQ[40]/DDR1_DQ[24]

W7

DDR1_DQ[41]/DDR1_DQ[25]

V10

DDR1_DQ[42]/DDR1_DQ[26]

V11

DDR1_DQ[43]/DDR1_DQ[27]

W11

DDR1_DQ[44]/DDR1_DQ[28]

W10

DDR1_DQ[45]/DDR1_DQ[29]

V7

DDR1_DQ[46]/DDR1_DQ[30]

V8

DDR1_DQ[47]/DDR1_DQ[31]

R11

DDR1_DQ[48]

P11

DDR1_DQ[49]

P7

DDR1_DQ[50]

R8

DDR1_DQ[51]

R10

DDR1_DQ[52]

P10

DDR1_DQ[53]

R7

DDR1_DQ[54]

P8

DDR1_DQ[55]

L11

DDR1_DQ[56]

M11

DDR1_DQ[57]

L7

DDR1_DQ[58]

M8

DDR1_DQ[59]

L10

DDR1_DQ[60]

M10

DDR1_DQ[61]

M7

DDR1_DQ[62]

L8

DDR1_DQ[63]

AW11

DDR1_ECC[0]

AY11

DDR1_ECC[1]

AY8

DDR1_ECC[2]

AW8

DDR1_ECC[3]

AY10

DDR1_ECC[4]

AW10

DDR1_ECC[5]

AY7

DDR1_ECC[6]

AW7

DDR1_ECC[7]

G1

DDR_RCOMP[0]

H1

DDR_RCOMP[1]

J2

DDR_RCOMP[2]

SKL-H_BG A1440

DDR CHANNEL B

2

?

SKYLAKE_HALO

BGA1440

DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]

DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]

DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]

DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]

DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT#

2 OF 14

REV = 1

DDR1_CKP[0] DDR1_CKN[0] DDR1_CKN[1]

DDR1_CKP[1] DDR1_CLKP[2] DDR1_CLKN[2] DDR1_CLKP[3] DDR1_CLKN[3]

DDR1_CKE[0]

DDR1_CKE[1]

DDR1_CKE[2]

DDR1_CKE[3]

DDR1_CS#[0] DDR1_CS#[1] DDR1_CS#[2] DDR1_CS#[3]

DDR1_ODT[0]

DDR1_ODT[1]

DDR1_ODT[2]

DDR1_ODT[3]

DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]

DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0] DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]

DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9]

DDR1_DQSN[0]/DDR0_DQSN[2] DDR1_DQSN[1]/DDR0_DQSN[3] DDR1_DQSN[2]/DDR0_DQSN[6] DDR1_DQSN[3]/DDR0_DQSN[7] DDR1_DQSN[4]/DDR1_DQSN[2] DDR1_DQSN[5]/DDR1_DQSN[3]

DDR1_DQSP[0]/DDR0_DQSP[2] DDR1_DQSP[1]/DDR0_DQSP[3] DDR1_DQSP[2]/DDR0_DQSP[6] DDR1_DQSP[3]/DDR0_DQSP[7] DDR1_DQSP[4]/DDR1_DQSP[2] DDR1_DQSP[5]/DDR1_DQSP[3]

DDR1_MA[3] DDR1_MA[4]

DDR1_PAR

DDR1_ALERT#

DDR1_DQSN[6] DDR1_DQSN[7]

DDR1_DQSP[6] DDR1_DQSP[7]

DDR1_DQSP[8] DDR1_DQSN[8]

DDR_VREF_CA DDR0_VREF_DQ DDR1_VREF_DQ

1

DDR_B_CLK 0

AM9 AN9

DDR_B_CLK #1

AM8 AM7

DDR_B_CLK 2

AM11

DDR_B_CLK #2

AM10

DDR_B_CLK 3

AJ10

DDR_B_CLK #3

AJ11

DDR_B_CKE 0

AT8

DDR_B_CKE 1

AT10

DDR_B_CKE 2

AT7

DDR_B_CKE 3

AT11

DDR_B_CS# 0

AF11

DDR_B_CS# 1

AE7

DDR_B_CS# 2

AF10

DDR_B_CS# 3

AE10

DDR_B_ODT0

AF7

DDR_B_ODT1

AE8

DDR_B_ODT2

AE9

DDR_B_ODT3

AE11

DDR_B_MA1 6

AH10

DDR_B_MA1 4

AH11

DDR_B_MA1 5

AF8

DDR_B_BA0

AH8

DDR_B_BA 1

AH9

DDR_B_BG 0

AR9

DDR_B_MA0

AJ9

DDR_B_MA1

AK6

DDR_B_MA2

AK5

DDR_B_MA3

AL5

DDR_B_MA4

AL6

DDR_B_MA5

AM6

DDR_B_MA6

AN7

DDR_B_MA7

AN10

DDR_B_MA8

AN8

DDR_B_MA9

AR11

DDR_B_MA1 0

AH7

DDR_B_MA1 1

AN11

DDR_B_MA1 2

AR10

DDR_B_MA1 3

AF9

DDR_B_BG 1

AR7

DDR_B_ACT#

AT9

DDR_B_PA RITY

AJ7

DDR_B_AL ERT#

AR8

DDR_B_DQS #0

BP9

DDR_B_DQS #1

BL9

DDR_B_DQS #2

BG9

DDR_B_DQS #3

BC9

DDR_B_DQS #4

AC9

DDR_B_DQS #5

W9

DDR_B_DQS #6

R9

DDR_B_DQS #7

M9

DDR_B_DQS 0

BR9

DDR_B_DQS 1

BJ9

DDR_B_DQS 2

BF9

DDR_B_DQS 3

BB9

DDR_B_DQS 4

AA9

DDR_B_DQS 5

V9

DDR_B_DQS 6

P9

DDR_B_DQS 7

L9

DDR_B_DQS 8

AW9

DDR_B_DQS #8

AY9

BN13 BP13 BR13

?

DDR_B_CLK 0 <17> DDR_B_CLK #0 <17> DDR_B_CLK #1 <17> DDR_B_CLK 1 <17> DDR_B_CLK 2 <16> DDR_B_CLK #2 <16> DDR_B_CLK 3 <16> DDR_B_CLK #3 <16>

DDR_B_CKE 0 <17> DDR_B_CKE 1 <17> DDR_B_CKE 2 <16> DDR_B_CKE 3 <16>

DDR_B_CS# 0 <17> DDR_B_CS# 1 <17> DDR_B_CS# 2 <16> DDR_B_CS# 3 <16>

DDR_B_ODT0 <17> DDR_B_ODT1 <17> DDR_B_ODT2 <16> DDR_B_ODT3 <16>

DDR_B_MA1 6 <1 6,17> DDR_B_MA1 4 <1 6,17> DDR_B_MA1 5 <1 6,17>

DDR_B_BA 0 < 16,17> DDR_B_BA 1 < 16,17> DDR_B_BG 0 < 16,17>

DDR_B_BG 1 < 16,17> DDR_B_ACT# <16,17>

DDR_B_PA RITY <16,17> DDR_B_AL ERT# <16,17>

DDR_B_DQS 8 <16,17> DDR_B_DQS #8 <16,17 >

+DDR_VREF_ CA

@

T199

PAD~D

+DDR_VREF_ B_DQ

DDR_B_MA[ 0..13] <16,17>

DDR_B_DQS #[0..7] <16,1 7>

DDR_B_DQS [0..7] <16,17 >

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Size Document Nu mber Rev

Date: Sheet of

Compal Electronics, Inc.

SKYLAKE-H (3/8)

LA-C551P

8 74Tuesday, August 18, 2015

1

1.0

5

CPU_DP1_P0<31> CPU_DP1_N0<31> CPU_DP1_P1<31>

Dock Port1

D D

TBT

C C

mDP/TBT

CPU_DP1_P2<31> CPU_DP1_N2<31> CPU_DP1_P3<31> CPU_DP1_N3<31>

CPU_DP1_AUXP<31> CPU_DP1_AUXN<31>

CPU_DP2_P0<34> CPU_DP2_N0<34> CPU_DP2_P1<34> CPU_DP2_N1<34> CPU_DP2_P2<34> CPU_DP2_N2<34> CPU_DP2_P3<34> CPU_DP2_N3<34>

CPU_DP2_AUXP<34> CPU_DP2_AUXN<34>

CPU_DP3_P0<33> CPU_DP3_N0<33> CPU_DP3_P1<33> CPU_DP3_N1<33> CPU_DP3_P2<33> CPU_DP3_N2<33> CPU_DP3_P3<33> CPU_DP3_N3<33>

CPU_DP3_AUXP<33> CPU_DP3_AUXN<33>

4

CPU_DP1_P0 CPU_DP1_N0 CPU_DP1_P1

CPU_DP1_P2 CPU_DP1_N2 CPU_DP1_P3 CPU_DP1_N3

CPU_DP1_AUXP CPU_DP1_AUXN

CPU_DP2_P0 CPU_DP2_N0 CPU_DP2_P1 CPU_DP2_N1 CPU_DP2_P2 CPU_DP2_N2 CPU_DP2_P3 CPU_DP2_N3

CPU_DP2_AUXP CPU_DP2_AUXN

CPU_DP3_P0 CPU_DP3_N0 CPU_DP3_P1 CPU_DP3_N1 CPU_DP3_P2 CPU_DP3_N2 CPU_DP3_P3 CPU_DP3_N3

CPU_DP3_AUXP CPU_DP3_AUXN

K36

DDI1_TXP[0]

K37

DDI1_TXN[0]

J35

DDI1_TXP[1]

J34

DDI1_TXN[1]

H37

DDI1_TXP[2]

H36

DDI1_TXN[2]

J37

DDI1_TXP[3]

J38

DDI1_TXN[3]

D27

DDI1_AUXP

E27

DDI1_AUXN

H34

DDI2_TXP[0]

H33

DDI2_TXN[0]

F37

DDI2_TXP[1]

G38

DDI2_TXN[1]

F34

DDI2_TXP[2]

F35

DDI2_TXN[2]

E37

DDI2_TXP[3]

E36

DDI2_TXN[3]

F26

DDI2_AUXP

E26

DDI2_AUXN

C34

DDI3_TXP[0]

D34

DDI3_TXN[0]

B36

DDI3_TXP[1]

B34

DDI3_TXN[1]

F33

DDI3_TXP[2]

E33

DDI3_TXN[2]

C33

DDI3_TXP[3]

B33

DDI3_TXN[3]

A27

DDI3_AUXP

B27

DDI3_AUXN

SKL-H_BGA1440

CPU1D

3

SKYLAKE_HALO

BGA1440

4 OF 14

REV = 1

?

EDP_TXP[0] EDP_TXN[0] EDP_TXP[1] EDP_TXN[1] EDP_TXN[2] EDP_TXP[2] EDP_TXN[3] EDP_TXP[3]

EDP_AUXP

EDP_AUXN

EDP_DISP_UTIL

EDP_RCOMP

PROC_AUDIO_CLK

PROC_AUDIO_SDI

PROC_AUDIO_SDO

2

EDP_TXP0

D29

EDP_TXN0

E29

EDP_TXP1

F28

EDP_TXN1CPU_DP1_N1

E28

EDP_TXN2

B29

EDP_TXP2

A29

EDP_TXN3

B28

EDP_TXP3

C28

EDP_AUXP

C26

EDP_AUXN

B26

A33

EDP_COMP

D37

G27 G25 G29

?

AUD_AZACPU_SDI AUD_AZACPU_SDI_R

@

T194

PAD~D

AUD_AZACPU_SCLK AUD_AZACPU_SDO AUD_AZACPU_SDI

1 2

RC66 20_0402_5%

COMPENSATION PU FOR

COMPENSATION PU FORCOMPENSATION PU FOR eDP

eDP

eDPeDP

CAD Note:Trace width=20 mils

CAD Note:Trace width=20 milsCAD Note:Trace width=20 mils

,Spacing=25mil,

,Spacing=25mil, ,Spacing=25mil,

Max length=100 mils.

Max length=100 mils.Max length=100 mils.

EDP_TXP0 <29> EDP_TXN0 <29> EDP_TXP1 <29> EDP_TXN1 <29>CPU_DP1_N1<31> EDP_TXN2 <29> EDP_TXP2 <29> EDP_TXN3 <29> EDP_TXP3 <29>

EDP_AUXP <29> EDP_AUXN <29>

EDP_COMP

AUD_AZACPU_SCLK <23> AUD_AZACPU_SDO <23>

1

+VCC_IO

12

RC124.9_0402_1%

AUD_AZACPU_SDI_R <23>

B B

A A

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Compal Electronics, Inc.

SKYLAKE-H (4/8)

LA-C551P

9 74Tuesday, August 18, 2015

1

1.0

5

D D

+VCC_EDRAM_FUSEPRG_ED2 +1.8V_RUN_EDRAM_ED2

1 2

RC226 100_0603_1%@

VCC_EDRAM_SENSE<55>

VSS_EDRAM_SENSE<55>

1 2 1 2

RC174 100_0603_1%@ RC223 0_0603_5%@

C C

1 2 1 2

RC176 100_0603_1%@ RC224 0_0603_5%@

1 2

RC230 100_0603_1%@

1 2 1 2

RC227 49.9_0402_1%

1 2

RC228 49.9_0402_1% RC229 49.9_0402_1%

+VCC_EOPIO

+VCC_EOPIO_ED2

VCC_EOPIO_SENSE<56> VSS_EOPIO_SENSE<56>

+1.8V_RUN_EDRAM

+VCC_EDRAM_FUSEPRG

+1.8V_RUN_EDRAM_ED2

+VCC_EDRAM_FUSEPRG_ED2

CPU_ZVM#<55,56> CPU_MSM#<56>

4

+VCC_EDRAM

3.3A

+VCC_EDRAM_ED2

100_0603_1%~D

12

@

RC173

VCC_EDRAM_SENSE VSS_EDRAM_SENSE

VCC_EDRAM_SENSE_ED2 VSS_EDRAM_SENSE_ED2

3.2A

1 2

RC175 100_0603_1%@

VCC_EOPIO_SENSE_ED3 VSS_EOPIO_SENSE_ED3

CPU_ZVM#_ED2 CPU_MSM#_ED2

CPU_EOPIO_RCOMP EDRAM_OPIO_RCOMP EDRAM_OPIO_RCOMP_ED2

BJ17 BJ19

BJ20 BK17 BK19 BK20

BL16

BL17

BL18

BL19

BL20

BL21 BM17 BN17

BJ23

BJ26

BJ27 BK23 BK26 BK27

BL23

BL24

BL25

BL26

BL27

BL28 BM24

BL15 BM16

BL22 BM22

BP15 BR15

BT15

BP16 BR16

BT16

BN15 BM15

BP17 BN16

BM14

BL14

BJ35

BJ36

AT13

AW13

AU13 AY13

BT29 BR25 BP25

SKL-H_BGA1440

SKYLAKE_HALO

CPU1J

BGA1440

VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC

RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD

VCCOPC_S ENSE VSSOPC_ SENSE

RSVD RSVD

VCCEOPIO VCCEOPIO VCCEOPIO

RSVD RSVD RSVD

VCCEOPIO _SENSE VSSEOPI O_SENSE

RSVD RSVD

VCC_OPC_ 1P8 VCC_OPC_ 1P8

RSVD RSVD

ZVM# MSM#

ZVM2# MSM2#

OPC_RCOMP OPCE_RCO MP OPCE_RCO MP2

REV = 1

?

10 OF 14

3

T1PAD~D @ T2PAD~D @ T3PAD~D @ T4PAD~D @

T5PAD~D @ T6PAD~D @

T7PAD~D @

T9PAD~D @ T10PAD~D @ T11PAD~D @ T8PAD~D @

T14PAD~D @ T13PAD~D @ T15PAD~D @ T12PAD~D @

PCH_2_CPU_TRIGGER<25>

CPU_2_PCH_TRIGGER<25>

?

PCH_2_CPU_TRIGGER CPU_2_PCH_TRIGGER_R

T16PAD~D @ T17PAD~D @

T18PAD~D @ T19PAD~D @

T21PAD~D @ T20PAD~D @

T23PAD~D @ T24PAD~D @ T22PAD~D @

TP_SKL_F30 TP_SKL_E30

2

CPU1K

D1

RSVD_TP

E1

RSVD_TP

E3

RSVD_TP

E2

RSVD_TP

BR1

RSVD_TP

BT2

RSVD_TP

BN35

RSVD

J24

RSVD

H24

RSVD

BN33

RSVD

BL34

RSVD

N29

RSVD

R14

RSVD

AE29

RSVD

AA14

RSVD

A36

RSVD

A37

RSVD

H23

PROC_TRIGIN

J23

PROC_TRIGOU T

F30

RSVD

E30

RSVD

B30

RSVD

C30

RSVD

G3

RSVD

J3

RSVD

BR35

RSVD

BR31

RSVD

BH30

RSVD

CPU_2_PCH_TRIGGER_RCPU_2_PCH_TRIGGER

1 2

RC177 30_0402_5%

1 2 1 2

RC178 0_0402_5%@ RC179 0_0402_5%@

SKYLAKE_HALO

BGA1440

SKL-H_BGA1440

?

11 OF 14

RSVD_TP RSVD_TP

RSVD RSVD

RSVD_TP RSVD_TP

RSVD RSVD

RSVD_TP RSVD_TP

RSVD RSVD RSVD

NCTF NCTF NCTF NCTF NCTF NCTF

1

BM33 BL33

BJ14 BJ13

BK28 BJ28

BJ18

VSS

BJ16 BK16

BK24 BJ24

BK21 BJ21

BT17 BR17

BK18

VSS

BJ34 BJ33

G13 AJ8 BL31

B2 B38 BP1 BR2 C1 C38

?REV = 1

T26 PAD~D@ T25 PAD~D@

T28 PAD~D@ T27 PAD~D@

T29 PAD~D@ T30 PAD~D@

T31 PAD~D@ T32 PAD~D@

T34 PAD~D@ T33 PAD~D@

T36 PAD~D@ T35 PAD~D@

T37 PAD~D@ T38 PAD~D@

T39 PAD~D@ T40 PAD~D@

T42 PAD~D@ T41 PAD~D@ T44 PAD~D@

T43 PAD~D@ T45 PAD~D@ T46 PAD~D@ T47 PAD~D@ T48 PAD~D@ T49 PAD~D@

B B

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

SKYLAKE-H (5/8)

LA-C551P

10 74Tuesday, August 18, 2015

1

1.0

5

+VCC_GT +VCC_SA

BG34 BG35 BG36

BH33 BH34 BH35 BH36 BH37 BH38

D D

C C

B B

BL36

BL37 BM36 BM37

BN36

BN37

BN38

BP37

BP38

BR37

BT37

BE38

BF13

BF14

BF29

BF30

BF31

BF32

BF35

BF36

BF37

BF38 BG29 BG30 BG31 BG32 BG33

BC36

BC37

BC38

BD13

BD14

BD29

BD30

BD31

BD32

BD33

BD34

BD35

BD36

BE31

BE32

BE37

BJ37 BJ38

SKYLAKE_HALO

CPU1H

VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT

SKL-H_BGA1440

?

BGA1440

8 OF 14

REV = 1

VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT

+VCC_GT

AV29 AV30 AV31 AV32 AV33 AV34 AV35 AV36 AW14 AW31 AW32 AW33 AW34 AW35 AW36 AW37 AW38 AY29 AY30 AY31 AY32 AY35 AY36 AY37 AY38 BA13 BA14 BA29 BA30 BA31 BA32 BA33 BA34 BA35 BA36 BB13 BB14 BB31 BB32 BB33 BB34 BB35 BB36 BB37 BB38 BC29 BC30 BC31 BC32 BC35 BE33 BE34 BE35 BE36

?

+VCC_IO

+1.0V_VCCSTG +1.0V_VCCST

RC317 0_0402_5%@

1 2

4

SKYLAKE_HALO

CPU1I

BGA1440

VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA

VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO

SKL-H_BGA1440

+VCC_VDDQ_CLK +1.2V_MEM

AG12

J30 K29 K30 K31 K32 K33 K34 K35 L31 L32 L35 L36 L37 L38 M29 M30 M31 M32 M33 M34 M35 M36

G15 G17 G19 G21 H15 H16 H17 H19 H20 H21 H26 H27

J15

J16

J17

J19

J20

J21

J26

J27

RC220 0_0402_5%@

?

9 OF 14

1 2

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VDDQC

VCCPLL_O C VCCPLL_O C

VCCST

VCCSTG

VCCPLL VCCPLL

VCCSA_SE NSE VSSSA_S ENSE

VCCIO_SE NSE VSSIO_S ENSE

3

+1.2V_MEM

12A

AA6 AE12 AF5 AF6 AG5 AG9 AJ12 AL11 AP6 AP7 AR12 AR6 AT12 AW6 AY6 J5 J6 K12 K6 L12 L6 R6 T6 W6

Y12

BH13 G11

H30

H29

G30

H28 J28

M38 M37

H14 J14

?REV = 1

+VCC_VDDQ_CLK

+VCC_SFR_OC

+1.0V_VCCST

+1.0V_VCCSTG

+1.0V_VCCSFR

VCC_SA_SENSE VSS_SA_SENSE

VCC_IO_SENSE VSS_IO_SENSE

VCC_SA_SENSE <61> VSS_SA_SENSE <61>

VCC_IO_SENSE <53> VSS_IO_SENSE <53>

SIO_SLP_S3#<7,11,23,37,44,46>

SIO_SLP_SUS#<46,49,58,59>

SIO_SLP_S4#<11,23,37,46,52,54>

RC332 0_0402_5%@

+1.2V_MEM

1 2

+3.3V_ALW

5

1

IN1

2

IN2

3

P

G

2

PDDG page19, if don`t support DS3, contact to VDDQ directly

+5V_ALW

@

1U_0402_6.3V6K

0.1U_0402_10V7K

1

12

CZ97

CZ96

2

C1471

@

1 2

0.1U_0402_10V7K

4

O

UC7

SN74AHC1G08DCKR_SC70-5

RC302 0_0402_5%@

UZ30

1

VIN1

2

VIN2

7

VIN thermal

3

VBIAS

4

ON

TPS22961DNYR_WSON8

12

VOUT

1

+VCC_SFR_OC

6

0.1U_0402_10V7K

@

12

5

GND

CZ95

VOUT

GND

+1.0V_VCCSTG

12

+1.0V_VCCSTG_C

6

5

@

PJP7 PAD-OPEN1x3m

+1.0V_VCCST source

+1.0V_VCCST source+1.0V_VCCST source

+1.0V_PRIM

1 2

CZ82 0.1U_0402_10V7K@

SIO_SLP_S4#<11,23,37,46,52,54>

RC303 0_0402_5%

1

2

1 2

1U_0402_6.3V6K

+5V_ALW

CZ90

0.1U_0402_10V7K

12

@

CZ89

UZ18

1

VIN1

2

VIN2

7

VIN thermal

3

VBIAS

4

ON

TPS22961DNYR_WSON8

4.4mohm/6A

4.4mohm/6A4.4mohm/6A TR=12.5us@Vin=1.05V

TR=12.5us@Vin=1.05V

TR=12.5us@Vin=1.05VTR=12.5us@Vin=1.05V

VOUT

GND

6

5

+1.0V_VCCST_UZ18

12

CZ63

0.1U_0402_10V7K

@

+1.0V_VCCST +1.0V_VCCSFR

PJP6

@

PAD-OPEN1x1m

1 2

12

RC304 0_0603_5%@

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

SKYLAKE-H (6/8)

LA-C551P

11 74Tuesday, August 18, 2015

1

1.0

+1.0V_VCCSTG source

+1.0V_VCCSTG source+1.0V_VCCSTG source

+1.0V_PRIM

UZ19

1

VIN1

2

@

0.1U_0402_10V7K CZ86

VIN2

7

VIN thermal

3

VBIAS

4

ON

TPS22961DNYR_WSON8

4.4mohm/6A

4.4mohm/6A4.4mohm/6A TR=12.5us@Vin=1.05V

TR=12.5us@Vin=1.05V

TR=12.5us@Vin=1.05VTR=12.5us@Vin=1.05V

4

+5V_ALW

1U_0402_6.3V6K

1

12

CZ88

2

+3.3V_ALW

C1421

@

1 2

0.1U_0402_10V7K

A A

SIO_SLP_S3#<7,11,23,37,44,46>

SIO_SLP_S0#<23, 37>

1 2

RC331 0_0402_5%

CC273

@

220P_0402_25V8J

5

1

P

IN1

4

O

2

IN2

G

UC1

RC320 0_0402_5%@

SN74AHC1G08DCKR_SC70-5

3

1 2

1

2

5

PLACE CAP IN

+VCC_EOPIO

PLACE CAP BACKSIDE

10U_0603_6.3V6M~D

1

CC173

2

D D

+VCC_EDRAM

PLACE CAP BACKSIDE

10U_0603_6.3V6M~D

1

CC177

2

10U_0603_6.3V6M~D

1

CC182

2

C C

+1.2V_MEM

+1.2V_MEM DECOUPLING

+1.2V_MEM DECOUPLING+1.2V_MEM DECOUPLING

10U_0603_6.3V6M~D

1

CC161

2

22U_0603_6.3V6M

B B

12

CC81

SOCKET EDGE TOP

+1.8V_RUN_EDRAM

10U_0603_6.3V6M~D

1

CC169

CC174

2

10U_0603_6.3V6M~D

1

CC176

CC179

CC175

2

10U_0603_6.3V6M~D

1

CC180

CC181

CC184

2

10U_0603_6.3V6M~D

1

CC170

12

1

CC164

CC168

2

22U_0603_6.3V6M

12

CC82

CC83

10U_0603_6.3V6M~D

1

CC190

2

10U_0603_6.3V6M~D

1

CC178

2

10U_0603_6.3V6M~D

1

CC183

2

PLACE CAP BACKSIDE

10U_0603_6.3V6M~D

1

CC163

2

CC84

10U_0603_6.3V6M~D

CC166

+VCC_VDDQ_CLK +1.0V_VCCSTG

10U_0603_6.3V6M~D

1

CC185

2

+VCC_IO

PLACE CAP BACKSIDE

22U_0603_6.3V6M

CC189

CC188

12

+1.0V_VCCST

1U_0402_6.3V6K

2

CC193

CC194

1

10U_0603_6.3V6M~D

1

CC171

2

1

CC172

CC165

2

1U_0402_6.3V6K

2

CC186

1

22U_0603_6.3V6M

CC187

12

10U_0603_6.3V6M~D

CC167

4

PLACE CAP BACKSIDE

+1.0V_VCCSFR +1.0V_VCCST

1U_0402_6.3V6K

2

CC195

1

+VCC_SA

22U_0603_6.3V6M

CC272

CC192

PLACE CAP BACKSIDE

10U_0603_6.3V6M~D

1

CC198

2

1U_0402_6.3V6K

2

CC203

1

3

+VCC_SFR_OC +VCC_GT +VCC_GTU

1U_0402_6.3V6K

2

CC191

1

10U_0603_6.3V6M~D

1

CC197

CC196

2

22U_0603_6.3V6M

1U_0402_6.3V6K

2

12

CC205

CC204

1

2

1

CC201

2

12

CC213

PLACE CAP SIDE

1U_0402_6.3V6K

2

CC209

CC210

1

10U_0603_6.3V6M~D

1

CC199

CC200

2

22U_0603_6.3V6M

12

CC212

CC211

AJ29

VCCGT

AJ30

VCCGT

AJ31

VCCGT

AJ32

VCCGT

AJ33

VCCGT

AJ34

VCCGT

AJ35

VCCGT

AJ36

VCCGT

AK31

VCCGT

AK32

VCCGT

AK33

VCCGT

AK34

VCCGT

AK35

VCCGT

AK36

VCCGT

AK37

VCCGT

AK38

VCCGT

AL13

VCCGT

AL29

VCCGT

AL30

VCCGT

AL31

VCCGT

AL32

VCCGT

AL35

CC202

CC208

AM13 AM14 AM29 AM30 AM31 AM32 AM33 AM34 AM35 AM36 AN13 AN14 AN31 AN32 AN33 AN34 AN35 AN36 AN37 AN38 AP13 AP14 AP29 AP30 AP31 AP32 AP35 AP36 AP37 AP38 AR29 AR30 AR31 AR32 AR33 AR34 AR35 AR36

AU14 AU29 AU30 AU31 AU32 AU35 AU36 AU37 AU38

VCCGT

AL36

VCCGT

AL37

VCCGT

AL38

VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT

AT14

VCCGT

AT31

VCCGT

AT32

VCCGT

AT33

VCCGT

AT34

VCCGT

AT35

VCCGT

AT36

VCCGT

AT37

VCCGT

AT38

VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT

REV = 1

SKYLAKE_HALO

CPU1N

SKL-H_BGA1440

?

BGA1440

14 OF 14

VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX

VCCGT_SENS E

VSSGTX_S ENSE

VSSGT_SE NSE

VCCGTX_SEN SE

2

AF29 AF30 AF31 AF32 AF33 AF34 AG13 AG14 AG31 AG32 AG33 AG34 AG35 AG36 AH13 AH14 AH29 AH30 AH31 AH32 AJ13 AJ14

VCCGT_SENSE

AH38

VSSGTX_SENSE

AH35

VSSGT_SENSE

AH37

VCCGTX_SENSE

AH36

?

VCCGT_SENSE <61> VSSGTX_SENSE <64> VSSGT_SENSE <61> VCCGTX_SENSE <64>

+VCC_CORE +VCC_CORE

AA13 AA31 AA32 AA33 AA34 AA35 AA36 AA37 AA38 AB29 AB30 AB31 AB32 AB35 AB36 AB37 AB38 AC13 AC14 AC29 AC30 AC31 AC32 AC33 AC34 AC35 AC36 AD13 AD14 AD31 AD32 AD33 AD34 AD35 AD36 AD37 AD38 AE13 AE14 AE30 AE31 AE32 AE35 AE36 AE37 AE38 AF35 AF36 AF37 AF38

K13 K14

L13 N13 N14 N30 N31 N32 N35 N36 N37 N38 P13

SKL-H_BGA1440

SKYLAKE_HALO

CPU1G

BGA1440

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

REV = 1 ?

?

7 OF 14

VCC_SENS E VSS_SEN SE

1

V32

VCC

V33

VCC

V34

VCC

V35

VCC

V36

VCC

V37

VCC

V38

VCC

W13

VCC

W14

VCC

W29

VCC

W30

VCC

W31

VCC

W32

VCC

W35

VCC

W36

VCC

W37

VCC

W38

VCC

Y29

VCC

Y30

VCC

Y31

VCC

Y32

VCC

Y33

VCC

Y34

VCC

Y35

VCC

Y36

VCC

L14

VCC

P29

VCC

P30

VCC

P31

VCC

P32

VCC

P33

VCC

P34

VCC

P35

VCC

P36

VCC

R13

VCC

R31

VCC

R32

VCC

R33

VCC

R34

VCC

R35

VCC

R36

VCC

R37

VCC

R38

VCC

T29

VCC

T30

VCC

T31

VCC

T32

VCC

T35

VCC

T36

VCC

T37

VCC

T38

VCC

U29

VCC

U30

VCC

U31

VCC

U32

VCC

U33

VCC

U34

VCC

U35

VCC

U36

VCC

V13

VCC

V14

VCC

V31

VCC

P14

VCC

VCC_SENSE

AG37 AG38

VSS_SENSE

VCC_SENSE <61> VSS_SENSE <61>

1 2

RC221 49.9_0402_1%@

A A

VCC_SENSEVSS_SENSE

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

SKYLAKE-H (7/8)

LA-C551P

12 74Tuesday, August 18, 2015

1

1.0

5

SKYLAKE_HALO

CPU1F

BGA1440

Y38

VSS

Y37

D D

C C

B B

Y14 Y13 Y11 Y10

Y9 Y8

Y7 W34 W33 W12

W5 W4 W3 W2 W1 V30 V29 V12

V6

U38 U37

U6

T34 T33 T14 T13 T12 T11 T10

T9

T8

T7

T5

T4

T3

T2

T1

R30 R29 R12

P38 P37 P12

P6

N34 N33 N12 N11 N10

N9

N8

N7

N6

N5

N4

N3

N2

N1

M14 M13 M12

M6 L34 L33 L30 L29 K38 K11 K10

K9

K8

K7

K5

K4

K3 K2

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

SKL-H_BGA1440

NCTFVSS

REV = 1

4

?

K1

VSS

J36

VSS

J33

VSS

J32

VSS

J25

VSS

J22

VSS

J18

VSS

J10

VSS

J7

VSS

J4

VSS

H35

VSS

H32

VSS

H25

VSS

H22

VSS

H18

VSS

H12

VSS

H11

VSS

G28

VSS

G26

VSS

G24

VSS

G23

VSS

G22

VSS

G20

VSS

G18

VSS

G16

VSS

G14

VSS

G12

VSS

G10

VSS

G9

VSS

G8

VSS

G6

VSS

G5

VSS

G4

VSS

F36

VSS

F31

VSS

F29

VSS

F27

VSS

F25

VSS

F23

VSS

F21

VSS

F19

VSS

F17

VSS

F15

VSS

F13

VSS

F11

VSS

F9

VSS

F8

VSS

F5

VSS

F4

VSS

F3

VSS

F2

VSS

E38

VSS

E35

VSS

E34

VSS

E9

VSS

E4

VSS

D33

VSS

D30

VSS

D28

VSS

D26

VSS

D24

VSS

D22

VSS

D20

VSS

D18

VSS

D16

VSS

D14

VSS

D12

VSS

D10

VSS

D9

VSS

D6

VSS

D3

VSS

C37

VSS

C31

VSS

C29

VSS

C27

VSS

D38

6 OF 14

BA38 BA37 BA12 BA11 BA10

AY34 AY33 AY14

AY12 AW30 AW29 AW12

AW5 AW4 AW3 AW2

AW1 AV38 AV37 AU34 AU33 AU12 AU11 AU10

AU9

AU8

AU7

AU6 AT30 AT29

AR38 AR37 AR14 AR13

AR5

AR4

AR3

AR2

AR1 AP34 AP33 AP12 AP11 AP10

AN30 AN29 AN12

AN6

AN5

AM38 AM37 AM12

AM5

AM4

AM3

AM2

AM1 AL34 AL33 AL14 AL12 AL10

?

BB4 BB3 BB2 BB1

BA9 BA8 BA7 BA6

B9

AT6

AP9 AP8

AL9 AL8 AL7 AL4

SKYLAKE_HALO

CPU1M

BGA1440

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

SKL-H_BGA1440

REV = 1

3

AK30

VSS

AK29

VSS

AK4

VSS

AJ38

VSS

AJ37

VSS

AJ6

VSS

AJ5

VSS

AJ4

VSS

AJ3

VSS

AJ2

VSS

AJ1

VSS

AH34

VSS

AH33

VSS

?

13 OF 14

NCTFVSS NCTFVSS NCTFVSS NCTFVSS NCTFVSS

AH12

VSS

AH6

VSS

AG30

VSS

AG29

VSS

AG11

VSS

AG10

VSS

AG8

VSS

AG7

VSS

AG6

VSS

AF14

VSS

AF13

VSS

AF12

VSS

AF4

VSS

AF3

VSS

AF2

VSS

AF1

VSS

AE34

VSS

AE33

VSS

AE6

VSS

AD30

VSS

AD29

VSS

AD12

VSS

AD11

VSS

AD10

VSS

AD9

VSS

AD8

VSS

AD7

VSS

AD6

VSS

AC38

VSS

AC37

VSS

AC12

VSS

AC6

VSS

AC5

VSS

AC4

VSS

AC3

VSS

AC2

VSS

AC1

VSS

AB34

VSS

AB33

VSS

AB6

VSS

AA30

VSS

AA29

VSS

AA12

VSS

A30

VSS

A28

VSS

A26

VSS

A24

VSS

A22

VSS

A20

VSS

A18

VSS

A16

VSS

A14

VSS

A12

VSS

A10

VSS

A9

VSS

A6

VSS

B37 B3 A34 A4 A3

?

2

?

SKYLAKE_HALO

CPU1L

BGA1440

C17

VSS

C13

VSS

C9

VSS

BT32

VSS

BT26

VSS

BT24

VSS

BT21

VSS

BT18

VSS

BT14

VSS

BT12

VSS

BT9

VSS

BT5

VSS

BR36

VSS

BR34

VSS

BR29

VSS

BR26

VSS

BR24

VSS

BR21

VSS

BR18

VSS

BR14

VSS

BR12

VSS

BR7

VSS

BP34

VSS

BP33

VSS

BP29

VSS

BP26

VSS

BP24

VSS

BP21

VSS

BP18

VSS

BP14

VSS

BP12

VSS

BP7

VSS

BN34

VSS

BN31

VSS

BN30

VSS

BN29

VSS

BN24

VSS

BN21

VSS

BN20

VSS

BN19

VSS

BN18

VSS

BN14

VSS

BN12

VSS

BN9

VSS

BN7

VSS

BN4

VSS

BN2

VSS

BM38

VSS

BM35

VSS

BM28

VSS

BM27

VSS

BM26

VSS

BM23

VSS

BM21

VSS

BM13

VSS

BM12

VSS

BM9

VSS

BM6

VSS

BM2

VSS

BL29

VSS

BK29

VSS

BK15

VSS

BK14

VSS

BJ32

VSS

BJ31

VSS

BJ25

VSS

BJ22

VSS

BH14

VSS

BH12

VSS

BH9

VSS

BH8

VSS

BH5

VSS

BH4

VSS

BH1

VSS

BG38

VSS

BG13

VSS

BG12

VSS

BF33

VSS

BF12

VSS

BE29

VSS

BE6

VSS

BD9

VSS

BC34

SKL-H_BGA1440

VSS

BC12

VSS

BB12

VSS

REV = 1

12 OF 14

1

NCTFVSS NCTFVSS NCTFVSS NCTFVSS NCTFVSS NCTFVSS

C25

VSS

C23

VSS

C21

VSS

C19

VSS

C15

VSS

C11

VSS

C8

VSS

C5

VSS

BM29

VSS

BM25

VSS

BM18

VSS

BM11

VSS

BM8

VSS

BM7

VSS

BM5

VSS

BM3

VSS

BL38

VSS

BL35

VSS

BL13

VSS

BL6

VSS

BK25

VSS

BK22

VSS

BK13

VSS

BK6

VSS

BJ30

VSS

BJ29

VSS

BJ15

VSS

BJ12

VSS

BH11

VSS

BH10

VSS

BH7

VSS

BH6

VSS

BH3

VSS

BH2

VSS

BG37

VSS

BG14

VSS

BG6

VSS

BF34

VSS

BF6

VSS

BE30

VSS

BE5

VSS

BE4

VSS

BE3

VSS

BE2

VSS

BE1

VSS

BD38

VSS

BD37

VSS

BD12

VSS

BD11

VSS

BD10

VSS

BD8

VSS

BD7

VSS

BD6

VSS

BC33

VSS

BC14

VSS

BC13

VSS

BC6

VSS

BB30

VSS

BB29

VSS

BB6

VSS

BB5

VSS

C2 BT36 BT35 BT4 BT3 BR38

?

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

PROPRIETARY NOTE:

PROPRIETARY NOTE: PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS

TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS

TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THISTRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

DOCUMENT MAY NOT

DOCUMENT MAY NOTDOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL.

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL.

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL.BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,

IN ADDITION,

IN ADDITION,IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED

NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED

NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSEDNEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

TO ANY THIRD

5

TO ANY THIRDTO ANY THIRD

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

Title

Size Document Number Rev

Date: Sheet of

2

Compal Electronics, Inc.

SKYLAKE-H (8/8)

LA-C551P

13 74T uesday, August 18, 2015

1

1.0

5

All VREF traces should

All VREF traces shouldAll VREF traces should

have 10 mil trace width

have 10 mil trace widthhave 10 mil trace width

D D

C C

B B

****

A A

DDR_A_DQS#[0..7]<8,15>

DDR_A_DQS[0..7]<8,15>

DDR_A_D[0..63]<8,15>

DDR_A_MA[0..13]<8,15 >

+1.2V_MEM

DIMM Select

DIMM SelectDIMM Select

SA0 SA1

0

DIMM4

DIMM1

1100

1

DIMM3

+2.5V_MEM

1U_0402_6.3V6K

1

CD2

CD3

2

10U_0603_6.3V6M

CD15

CD89

1

2

1U_0402_6.3V6K

1

CD5

CD4

2

Layout Note: Place near JDIMM1.258

+0.6V_DDR_VTT

10U_0603_6.3V6M

CD98

1

2

SA2

0DIMM2

0

1

0

10U_0603_6.3V6M

1

CD8

CD7

2

CD14 change to SGA20331E10

10U_0603_6.3V6M

CD10

CD9

CD11

1

2

1U_0402_6.3V6K

1

CD95

CD6

CD93

2

1U_0402_6.3V6K

1

CD17

CD19

2

+3.3V_RUN

+3.3V_RUN+3.3V_RUN

12

RD17

@

RD13

@

0_0402_5%

12

RD30

@

RD29

@

0_0402_5%

10U_0603_6.3V6M

1

CD13

CD12

CD90

1

+

2

1U_0402_6.3V6K

1

CD96

CD97

CD94

2

+V_DDR_REFCA_A

12

RD8

@

0_0402_5%

DIMM1_SA0 DIMM1_SA1 DIMM1_SA2

12

RD28

@

0_0402_5%

330U_D2_2V_Y

CD14

0.1U_0402_10V6K

1

2

+3.3V_RUN

2.2U_0402_6.3V6M

1

CD76

2

12

RD57

@

0_0603_5%

+3.3V_RUN_DIMM1

0.1U_0402_10V6K

1

CD21

2

4

DDR_A_CB0<8,15 >

DDR_A_CB5<8,15 >

DDR_A_DQS#8<8,15> DDR_A_DQS8<8,15>

DDR_A_CB3<8,15 >

DDR_A_CB2<8,15 >

DDR_A_CKE2<8>

DDR_A_BG1<8,15> DDR_A_BG0<8,15>

DDR_A_CLK2<8> DDR_A_CLK#2<8>

DDR_A_PARITY<8,15>

DDR_A_BA1<8,15>

DDR_A_CS#2<8>

DDR_A_MA14<8,15>

DDR_A_ODT2<8>

DDR_A_CS#3<8>

DDR_A_ODT3<8>

@

CD75

2.2U_0402_6.3V6M

@

1

CD22

2

+2.5V_MEM

JDIMM1 STD Type H=9.2

JDIMM1 STD Type H=9.2JDIMM1 STD Type H=9.2

JDIMM1

1

DDR_A_D4

DDR_A_D0

DDR_A_DQS#0 DDR_A_DQS0

DDR_A_D7

DDR_A_D3

DDR_A_D13

DDR_A_D12

DDR_A_D15

DDR_A_D14

DDR_A_D21

DDR_A_D20

DDR_A_DQS#2 DDR_A_DQS2

DDR_A_D22

DDR_A_D18

DDR_A_D29

DDR_A_D28

DDR_A_D27

DDR_A_D30

DDR_A_CB0

DDR_A_CB5

DDR_A_DQS#8 DDR_A_DQS8

DDR_A_CB3

DDR_A_CB2

DDR_A_CKE2

DDR_A_BG1 DDR_A_BG0

DDR_A_MA12 DDR_A_MA9

DDR_A_MA8 DDR_A_MA6

DDR_A_MA3 DDR_A_MA1

DDR_A_CLK2 DDR_A_CLK#2

DDR_A_PARITY

DDR_A_BA1

DDR_A_CS#2 DDR_A_MA14 DDR_A_MA16

DDR_A_ODT2 DDR_A_CS#3

DDR_A_ODT3

T51PAD~D @

DDR_A_D33

DDR_A_D37

DDR_A_DQS#4 DDR_A_DQS4

DDR_A_D38

DDR_A_D39

DDR_A_D44

DDR_A_D41

DDR_A_D43

DDR_A_D46

DDR_A_D50

DDR_A_D52

DDR_A_DQS#6 DDR_A_DQS6

DDR_A_D54

DDR_A_D51

DDR_A_D57

DDR_A_D61

DDR_A_D62

DDR_A_D58

+3.3V_RUN_DIMM1

VSS1

3

DQ5

5

VSS3

7

DQ1

9

VSS5 DQS0_c11DM0_n/DBI0_n

13

DQS0_t

15

VSS8

17

DQ7

19

VSS10

21

DQ3

23

VSS12

25

DQ13

27

VSS14

29

DQ9

31

VSS16

33

DM1_n/DBI_n

35

VSS17

37

DQ15

39

VSS19

41

DQ10

43

VSS21

45

DQ21

47

VSS23

49

DQ17

51

VSS25 DQS2_c53DM2_n/DBI2_n

55

DQS2_t

57

VSS28

59

DQ23

61

VSS30

63

DQ19

65

VSS32

67

DQ29

69

VSS34

71

DQ25

73

VSS36 DM3_n/DBI3_n75DQS3_t

77

VSS37

79

DQ30

81

VSS39

83

DQ26

85

VSS41

87

CB5/NC

89

VSS43

91

CB1/NC

93

VSS45 DQS8_c95DM8_n/DBI_n/NC

97

DQS8_t

99

VSS48

101

CB2/NC

103

VSS50

105

CB3/NC

107

VSS52

109

CKE0

111

VDD1

113

BG1

115

BG0

117

VDD3

119

A12

121

A9

123

VDD5

125

A8

127

A6

129

VDD7

131

A3

133

A1

135

VDD9

137

CK0_t

139

CK0_c

141

VDD11

143

PARITY

145

BA1

147

VDD13

149

CS0_n

151

WE_n/A14

153

VDD15

155

ODT0

157

CS1_n

159

VDD17

161

ODT1

163

VDD19

165

C1, CS3_n,NC

167

VSS53

169

DQ37

171

VSS55

173

DQ33

175

VSS57

177

DQS4_c

179

DQS4_t

181

VSS60

183

DQ38

185

VSS62

187

DQ34

189

VSS64

191

DQ44

193

VSS66

195

DQ40

197

VSS68

199

DM5_n/DBI5_n

201

VSS69

203

DQ46

205

VSS71

207

DQ42

209

VSS73

211

DQ52

213

VSS75

215

DQ49

217

VSS77

219

DQS6_c

221

DQS6_t

223

VSS80

225

DQ55

227

VSS82

229

DQ51

231

VSS84

233

DQ61

235

VSS86

237

DQ56

239

VSS88

241

DM7_n/DBI7_n

243

VSS89

245

DQ62

247

VSS91

249

DQ58

251

VSS93

253

SCL

255

VDDSPD

257

VPP1

259

VPP2

261

GND1

BELLW_80888-6021 CONN@

3

VSS11

VSS13

VSS15

DQS1_c

DQS1_t

VSS18

VSS20

VSS22

VSS24

VSS26

VSS27

VSS29

VSS31

VSS33

VSS35

DQS3_c

VSS38

VSS40

VSS42

CB4/NC

VSS44

CB0/NC

VSS46

VSS47

CB6/NC

VSS49

CB7/NC

VSS51

RESET_n

ACT_n

ALERT_n

EVENT_n/NF

VDD10 CK1_t/NF CK1_c/NF

VDD12

A10/AP

VDD14

RAS_n/A16

VDD16

CAS_n/A15

VDD18

C0/CS2_n/NC

VREFCA

VSS54

VSS56

VSS58

DM4_n/DBI4_n

VSS59

VSS61

VSS63

VSS65

VSS67

DQS5_c

DQS5_t

VSS70

VSS72

VSS74

VSS76

VSS78

DM6_n/DBI6_n

VSS79

VSS81

VSS83

VSS85

VSS87

DQS7_c

DQS7_t

VSS90

VSS92

VSS94

2

+1.2V_MEM+1.2V_MEM

2

VSS2

DQ4

VSS4

DQ0

VSS6

VSS7

DQ6

VSS9

DQ2

DQ12

DQ8

DQ14

DQ11

DQ20

DQ16

DQ22

DQ18

DQ28

DQ24

DQ31

DQ27

CKE1 VDD2

VDD4

A11

A7

VDD6

A5 A4

VDD8

A2

A0

BA0

A13

SA2

DQ36

DQ32

DQ39

DQ35

DQ45

DQ41

DQ47

DQ43

DQ53

DQ48

DQ54

DQ50

DQ60

DQ57

DQ63

DQ59

SDA SA0

VTT

SA1

GND2

DDR_A_D1

4 6

DDR_A_D5

8 10 12 14

DDR_A_D6

16 18

DDR_A_D2

20 22

DDR_A_D9

24 26

DDR_A_D8

28 30

DDR_A_DQS#1

32

DDR_A_DQS1

34 36

DDR_A_D10

38 40

DDR_A_D11

42 44

DDR_A_D16

46 48

DDR_A_D17

50 52 54 56

DDR_A_D19

58 60

DDR_A_D23

62 64

DDR_A_D24

66 68

DDR_A_D25

70 72

DDR_A_DQS#3

74

DDR_A_DQS3

76 78

DDR_A_D26

80 82

DDR_A_D31

84 86

DDR_A_CB1

88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144

146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 206 208 210 212 214 216 218 220 222 224 226 228 230 232 234 236 238 240 242 244 246 248 250 252 254 256 258 260 262

DDR_A_CB4

DDR_A_CB7

DDR_A_CB6

DDR_A_DRAMRST# DDR_A_CKE3

DDR_A_ACT# DDR_A_ALERT#

DDR_A_MA11 DDR_A_MA7

DDR_A_MA5 DDR_A_MA4

DDR_A_MA2 JDIMM1_EVENT#

DDR_A_CLK3 DDR_A_CLK#3

DDR_A_MA0

DDR_A_MA10

DDR_A_BA0

DDR_A_MA15 DDR_A_MA13

DIMM1_SA2

DDR_A_D36

DDR_A_D32

DDR_A_D35

DDR_A_D34

DDR_A_D40

DDR_A_D45

DDR_A_DQS#5 DDR_A_DQS5

DDR_A_D47

DDR_A_D42

DDR_A_D48

DDR_A_D49

DDR_A_D53

DDR_A_D55

DDR_A_D56

DDR_A_D60

DDR_A_DQS#7 DDR_A_DQS7

DDR_A_D59

DDR_A_D63

DIMM1_SA0

DIMM1_SA1

DDR_A_CB1 <8,15>

DDR_A_CB4 <8,15>

DDR_A_CB7 <8,15>

DDR_A_CB6 <8,15>

1 2

CD92 0 .1U_0402_10V6K@

DDR_A_CKE3 <8 >

DDR_A_ACT# <8,15> DDR_A_ALERT# <8,15>

DDR_A_CLK3 <8> DDR_A_CLK#3 <8>

DDR_A_BA0 <8,15> DDR_A_MA16 <8,15>

DDR_A_MA15 <8,15>

T50 PAD~D@

+V_DDR_REFCA_A

DDR_XDP_WAN_SMBDAT <7,15,16,17,23,41>DDR_XDP_WAN_SMBCLK<7,15,16,17,23,41>

+0.6V_DDR_VTT

+V_DDR_REFCA_A

CPU

+1.2V_MEM

12

RD7 470_0402_1%

0.1U_0402_10V6K

1

2

RD3 1K_0402_ 5%@

+DDR_VREF_CA +V_DDR_REFCA_B

1

2

12

DDR_PG_CTRL<7>

STD

STDSTD

JDIMM1

DDDD

AAAA

JDIMM2

STD

STD REV

STDSTD

1 2

RD6 0_0402 _5%@

1 2

RD15 0_0402_5%@

@

CD16

PCH_THERMTRIP#JDIMM1_EVENT#

1 2

+V_DDR_REFCA_B

1 2

RD45 2_0402_1%@

RD23 2_0402_1%

0.022U_0402_16V7K

CD127

24.9_0402_1% RD16

1 2

UD1

1

NC

2

A

3

GND

74AUP1G07GW_TSSOP5

+V_DDR_REFCA_A

VCC

Y

+3.3V_RUN

5

4

STD

STDSTD

JDIMM3

CCCC BBBB

JDIMM4

REV

REVREV

DDR_A_DRAMRST# DDR_B_DRAMRST#

PCH_THERMTRIP# <7,15,16,17,19,46>

1

2

330K_0402_5%

12

RD61

+1.2V_MEM

0.6V_DDR_VTT_ON

1

Top Side

Top SideTop Side

Bottom Side

Bottom SideBottom Side

DDR_A_DRAMRST# <15>DDR4_DRAMRST#_PCH<23> DDR_B_DRAMRST# <16,17>

+1.2V_MEM

1K_0402_5%

12

RD9

1

2

0.1U_0402_10V6K 1K_0402_5%

@

12

RD10

CD128

1 2

CD144@ 0.1U_0402_25V6

0.6V_DDR_VTT_ON <52>

0.1U_0402_10V6K

@

CD129

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

DDRIII-SODIMM SLOT1

Size Document Number Rev

Date: Sheet of

LA-C551P

1

14 74Tuesday, August 18, 2015

1.0

5

DDR_A_DQS#[0..7]<8,14>

DDR_A_DQS[0..7]<8,14>

DDR_A_D[0..63]<8,14>

D D

C C

B B

DIMM2

****

DIMM4

DIMM1 1

DIMM3

A A

DDR_A_MA[0..13]<8,14 >

+2.5V_MEM

1

2

+1.2V_MEM

1

2

1

2

Layout Note: Place near JDIMM2.258

DIMM Select

DIMM SelectDIMM Select

SA0 SA1

0

0 1

0

1 1

5

1U_0402_6.3V6K

CD33

10U_0603_6.3V6M

CD91

1U_0402_6.3V6K

CD20

+0.6V_DDR_VTT

SA2

0

1U_0402_6.3V6K

10U_0603_6.3V6M

1

CD35

CD38

2

10U_0603_6.3V6M

CD18

CD31

1

2

1U_0402_6.3V6K

1

CD23

CD24

2

10U_0603_6.3V6M

1U_0402_6.3V6K

CD105

1

CD36

2

12

RD26

@

0_0402_5%

12

RD35

@

0_0402_5%

10U_0603_6.3V6M

CD37

CD14 change to SGA20331E10

10U_0603_6.3V6M

CD27

CD28

CD32

1U_0402_6.3V6K

CD100

1U_0402_6.3V6K

1

2

CD30

1

2

1

2

12

1U_0402_6.3V6K

CD103

RD20

@

0_0402_5%

RD36

@

0_0402_5%

1

2

1U_0402_6.3V6K

1

CD101

2

+3.3V_RUN+3.3V_RUN+3.3V_RUN

12

@

0_0402_5%

DIMM2_SA0 DIMM2_SA1 DIMM2_SA2

12

@

0_0402_5%

10U_0603_6.3V6M

CD34

1

2

1U_0402_6.3V6K

1

CD102

2

+V_DDR_REFCA_A

RD19

RD31

4

DDR_A_D1

DDR_A_D5

DDR_A_DQS#0 DDR_A_DQS0

DDR_A_D6

DDR_A_D2

DDR_A_D9

DDR_A_D8

DDR_A_D10

DDR_A_D11

DDR_A_D16

DDR_A_D17

DDR_A_DQS#2 DDR_A_DQS2

DDR_A_D19

DDR_A_D23

DDR_A_D24

DDR_A_CB0<8,14 >

DDR_A_CB5<8,14 >

DDR_A_DQS#8<8,14> DDR_A_DQS8<8,14>

DDR_A_CB3<8,14 >

DDR_A_CB2<8,14 >

DDR_A_BG1<8,14> DDR_A_BG0<8,14>

DDR_A_CLK0<8> DDR_A_CLK#0<8>

DDR_A_PARITY<8,14>

DDR_A_CS#0<8>

DDR_A_ODT0<8>

DDR_A_CS#1<8>

DDR_A_ODT1<8>

DDR_A_BA1<8,14>

DDR_A_MA14<8,14>

+2.5V_MEM

T53PAD~D @

+3.3V_RUN_DIMM2

DDR_A_D25

DDR_A_D26

DDR_A_D31

DDR_A_CB0

DDR_A_CB5

DDR_A_DQS#8 DDR_A_DQS8

DDR_A_CB3

DDR_A_CB2

DDR_A_CKE0

DDR_A_BG1 DDR_A_BG0

DDR_A_MA12 DDR_A_MA9

DDR_A_MA8 DDR_A_MA6

DDR_A_MA3 DDR_A_MA1

DDR_A_CLK0 DDR_A_CLK#0

DDR_A_PARITY

DDR_A_BA1

DDR_A_CS#0 DDR_A_MA14

DDR_A_ODT0 DDR_A_CS#1

DDR_A_ODT1

DDR_A_D36

DDR_A_D32

DDR_A_DQS#4 DDR_A_DQS4

DDR_A_D35

DDR_A_D34

DDR_A_D40

DDR_A_D45

DDR_A_D47

DDR_A_D42

DDR_A_D48

DDR_A_D49

DDR_A_DQS#6 DDR_A_DQS6

DDR_A_D53

DDR_A_D55

DDR_A_D56

DDR_A_D60

DDR_A_D59

DDR_A_D63

330U_D2_2V_Y

1

CD99

CD25

+

2

RD58

+3.3V_RUN_DIMM2

0.1U_0402_10V6K

2.2U_0402_6.3V6M

@

1

CD26

CD29

2

DDR_A_CKE0<8>

CD104

0.1U_0402_10V6K

2.2U_0402_6.3V6M

@

1

CD78

CD77

2

+3.3V_RUN

12

@

0_0603_5%

1

2

4

3

JDIMM2 STD Type H=4

JDIMM2 STD Type H=4JDIMM2 STD Type H=4

JDIMM2

1

VSS1

3

DQ5

5

VSS3

7

DQ1

9

VSS5 DQS0_c11DM0_n/DBI0_n

13

DQS0_t

15

VSS8

17

DQ7

19

VSS10

21

DQ3

23

VSS12

25

DQ13

27

VSS14

29

DQ9

31

VSS16

33

DM1_n/DBI_n

35

VSS17

37

DQ15

39

VSS19

41

DQ10

43

VSS21

45

DQ21

47

VSS23

49

DQ17

51

VSS25 DQS2_c53DM2_n/DBI2_n

55

DQS2_t

57

VSS28

59

DQ23

61

VSS30

63

DQ19

65

VSS32

67

DQ29

69

VSS34

71

DQ25

73

VSS36 DM3_n/DBI3_n75DQS3_t

77

VSS37

79

DQ30

81

VSS39

83

DQ26

85

VSS41

87

CB5/NC

89

VSS43

91

CB1/NC

93

VSS45 DQS8_c95DM8_n/DBI_n/NC

97

DQS8_t

99

VSS48

101

CB2/NC

103

VSS50

105

CB3/NC

107

VSS52

109

CKE0

111

VDD1

113

BG1

115

BG0

117

VDD3

119

A12

121

A9

123

VDD5

125

A8

127

A6

129

VDD7

131

A3

133

A1

135

VDD9

137

CK0_t

139

CK0_c

141

VDD11

143

PARITY

145

BA1

147

VDD13

149

CS0_n

151

WE_n/A14

153

VDD15

155

ODT0

157

CS1_n

159

VDD17

161

ODT1

163

VDD19

165

C1, CS3_n,NC

167

VSS53

169

DQ37

171

VSS55

173

DQ33

175

VSS57

177

DQS4_c

179

DQS4_t

181

VSS60

183

DQ38

185

VSS62

187

DQ34

189

VSS64

191

DQ44

193

VSS66

195

DQ40

197

VSS68

199

DM5_n/DBI5_n

201

VSS69

203

DQ46

205

VSS71

207

DQ42

209

VSS73

211

DQ52

213

VSS75

215

DQ49

217

VSS77

219

DQS6_c

221

DQS6_t

223

VSS80

225

DQ55

227

VSS82

229

DQ51

231

VSS84

233

DQ61

235

VSS86

237

DQ56

239

VSS88

241

DM7_n/DBI7_n

243

VSS89

245

DQ62

247

VSS91

249

DQ58

251

VSS93

253

SCL

255

VDDSPD

257

VPP1

259

VPP2

261

GND1

LOTES_ADDR0106-P005A CONN@

3

VSS2

DQ4

VSS4

DQ0

VSS6

VSS7

DQ6

VSS9

DQ2

VSS11

DQ12

VSS13

DQ8

VSS15 DQS1_c DQS1_t

VSS18

DQ14

VSS20

DQ11

VSS22

DQ20

VSS24

DQ16

VSS26

VSS27

DQ22

VSS29

DQ18

VSS31

DQ28

VSS33

DQ24

VSS35 DQS3_c

VSS38

DQ31

VSS40

DQ27

VSS42 CB4/NC

VSS44 CB0/NC

VSS46

VSS47 CB6/NC

VSS49 CB7/NC

VSS51

RESET_n

CKE1 VDD2

ACT_n

ALERT_n

VDD4

A11

A7

VDD6

A5 A4

VDD8

A2

EVENT_n/NF

VDD10

CK1_t/NF

CK1_c/NF

VDD12

A0

A10/AP

VDD14

BA0

RAS_n/A16

VDD16

CAS_n/A15

A13

VDD18

C0/CS2_n/NC

VREFCA

SA2

VSS54

DQ36

VSS56

DQ32

VSS58

DM4_n/DBI4_n

VSS59

DQ39

VSS61

DQ35

VSS63

DQ45

VSS65

DQ41

VSS67

DQS5_c

DQS5_t

VSS70

DQ47

VSS72

DQ43

VSS74

DQ53

VSS76

DQ48

VSS78

DM6_n/DBI6_n

VSS79

DQ54

VSS81

DQ50

VSS83

DQ60

VSS85

DQ57

VSS87

DQS7_c

DQS7_t

VSS90

DQ63

VSS92

DQ59

VSS94

SDA SA0 VTT SA1

GND2

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

2

+1.2V_MEM+1.2V_MEM

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144

146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 206 208 210 212 214 216 218 220 222 224 226 228 230 232 234 236 238 240 242 244 246 248 250 252 254 256 258 260 262

DDR_A_D4

DDR_A_D0

DDR_A_D7

DDR_A_D3

DDR_A_D13

DDR_A_D12

DDR_A_DQS#1 DDR_A_DQS1

DDR_A_D15

DDR_A_D14

DDR_A_D21

DDR_A_D20

DDR_A_D22

DDR_A_D18

DDR_A_D29

DDR_A_D28

DDR_A_DQS#3 DDR_A_DQS3

DDR_A_D27

DDR_A_D30

DDR_A_CB1

DDR_A_CB4

DDR_A_CB7

DDR_A_CB6

DDR_A_DRAMRST# DDR_A_CKE1

DDR_A_ACT# DDR_A_ALERT#

DDR_A_MA11 DDR_A_MA7

DDR_A_MA5 DDR_A_MA4

DDR_A_MA2 JDIMM2_EVENT#

DDR_A_CLK1 DDR_A_CLK#1

DDR_A_MA0

DDR_A_MA10

DDR_A_BA0 DDR_A_MA16

DDR_A_MA15 DDR_A_MA13

DIMM2_SA2

DDR_A_D33

DDR_A_D37

DDR_A_D38

DDR_A_D39

DDR_A_D44

DDR_A_D41

DDR_A_DQS#5 DDR_A_DQS5

DDR_A_D43

DDR_A_D46

DDR_A_D50

DDR_A_D52

DDR_A_D54

DDR_A_D51

DDR_A_D57

DDR_A_D61

DDR_A_DQS#7 DDR_A_DQS7

DDR_A_D62

DDR_A_D58

DIMM2_SA0

DIMM2_SA1

DDR_A_CB1 <8,14>

DDR_A_CB4 <8,14>

DDR_A_CB7 <8,14>

DDR_A_CB6 <8,14>

1 2

CD122 0.1U_0402_10V6K@

DDR_A_CKE1 <8 >

DDR_A_ACT# <8,14> DDR_A_ALERT# <8,14>

DDR_A_CLK1 <8> DDR_A_CLK#1 <8>

DDR_A_BA0 <8,14> DDR_A_MA16 <8,14>

DDR_A_MA15 <8,14>

T52 PAD~D@

+V_DDR_REFCA_A

DDR_XDP_WAN_SMBDAT <7,14,16,17,23,41>DDR_XDP_WAN_SMBCLK<7,14,16,17,23,41>

+0.6V_DDR_VTT

CPU

+V_DDR_REFCA_A

AAAA

JDIMM2

RD4 1K_0402_ 5%@

JDIMM1

DDR_A_DRAMRST#

1 2

Top

TopTop Side

Side

SideSide

DDDD

Bottom

BottomBottom Side

Side

SideSide

JDIMM3

JDIMM4

PCH_THERMTRIP#JDIMM2_EVENT#

1

CCCC

BBBB

DDR_A_DRAMRST# <14>

PCH_THERMTRIP# <7,14,16,17,19,46>

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

DDRIII-SODIMM SLOT2

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

LA-C551P

1

15 74Tuesday, August 18, 2015

1.0

5

DDR_B_DQS#[0..7]<8,17>

DDR_B_DQS[0..7]<8,17>

DDR_B_D[0..63]<8,17>

DDR_B_MA[0..13]<8,17 >

D D

+2.5V_MEM

10U_0603_6.3V6M

1U_0402_6.3V6K

1

CD51

2

+1.2V_MEM

10U_0603_6.3V6M

CD106

1

2

C C

B B

DIMM Select

DIMM SelectDIMM Select

DIMM2

DIMM4

DIMM1 1

DIMM3

****

A A

1U_0402_6.3V6K

1

CD40

2

Layout Note: Place near JDIMM3.258

+0.6V_DDR_VTT

SA0 SA1

0

0 1

0

1 1

5

1

2

SA2

0

CD55

CD56

CD53

2

CD14 change to SGA20331E10

10U_0603_6.3V6M

CD49

CD50

CD39

1

2

1U_0402_6.3V6K

1

CD41

CD108

CD42

2

10U_0603_6.3V6M

1U_0402_6.3V6K

CD113

1

CD54

2

12

RD38

@

0_0402_5%

12

RD40

@

0_0402_5%

10U_0603_6.3V6M

CD45

CD46

1

2

1U_0402_6.3V6K

1

CD109

CD111

2

+V_DDR_REFCA_B

CD48

+3.3V_RUN+3.3V_RUN+3.3V_RUN

12

RD37

@

0_0402_5%

12

RD42

@

0_0402_5%

CD52

1

2

1

CD110

2

RD27

@

0_0402_5%

DIMM3_SA0 DIMM3_SA1 DIMM3_SA2

RD39

@

0_0402_5%

4

JDIMM3 STD Type H=5.2

JDIMM3 STD Type H=5.2JDIMM3 STD Type H=5.2

DDR_B_D4

DDR_B_D1

DDR_B_DQS#0 DDR_B_DQS0

DDR_B_D6

DDR_B_D3

DDR_B_D10

DDR_B_D9

DDR_B_D12

DDR_B_D13

DDR_B_D18

DDR_B_D22

DDR_B_DQS#2 DDR_B_DQS2

DDR_B_D19

DDR_B_D20

DDR_B_D25

DDR_B_CB4<8,17 >

DDR_B_CB2<8,17 >

DDR_B_DQS#8<8,17> DDR_B_DQS8<8,17>

DDR_B_CB7<8,17 >

DDR_B_CB5<8,17 >

DDR_B_BG1<8,17> DDR_B_BG0<8,17>

DDR_B_CLK2<8> DDR_B_CLK#2<8>

DDR_B_PARITY<8,17>

DDR_B_BA1<8,17>

DDR_B_CS#2<8>

DDR_B_MA14<8,17>

DDR_B_CS#3<8>

+2.5V_MEM

T55PAD~D @

+3.3V_RUN_DIMM3

DDR_B_D30

DDR_B_D29

DDR_B_D31

DDR_B_CB4

DDR_B_CB2

DDR_B_DQS#8 DDR_B_DQS8

DDR_B_CB7

DDR_B_CB5

DDR_B_CKE2

DDR_B_BG1 DDR_B_BG0

DDR_B_MA12 DDR_B_MA9

DDR_B_MA8 DDR_B_MA6

DDR_B_MA3 DDR_B_MA1

DDR_B_CLK2 DDR_B_CLK#2

DDR_B_PARITY

DDR_B_BA1

DDR_B_CS#2 DDR_B_MA14

DDR_B_ODT2 DDR_B_CS#3

DDR_B_ODT3

DDR_B_D35

DDR_B_D34

DDR_B_DQS#4 DDR_B_DQS4

DDR_B_D33

DDR_B_D32

DDR_B_D40

DDR_B_D41

DDR_B_D42

DDR_B_D46

DDR_B_D48

DDR_B_D52

DDR_B_DQS#6 DDR_B_DQS6

DDR_B_D50

DDR_B_D55

DDR_B_D57

DDR_B_D61

DDR_B_D56

DDR_B_D60

10U_0603_6.3V6M

330U_D2_2V_Y

1

CD107

CD43

+

2

1U_0402_6.3V6K

CD112

0.1U_0402_10V6K

2.2U_0402_6.3V6M

@

1

CD80

CD79

2

+3.3V_RUN

12

1

2

4

RD59

@

0_0603_5%

+3.3V_RUN_DIMM3

0.1U_0402_10V6K

2.2U_0402_6.3V6M

1

CD47

2

DDR_B_CKE2<8>

DDR_B_ODT2<8>

DDR_B_ODT3<8>

@

CD44

3

JDIMM3

1

VSS1

3

DQ5

5

VSS3

7

DQ1

9

VSS5 DQS0_c11DM0_n/DBI0_n

13

DQS0_t

15

VSS8

17

DQ7

19

VSS10

21

DQ3

23

VSS12

25

DQ13

27

VSS14

29

DQ9

31

VSS16

33

DM1_n/DBI_n

35

VSS17

37

DQ15

39

VSS19

41

DQ10

43

VSS21

45

DQ21

47

VSS23

49

DQ17

51

VSS25 DQS2_c53DM2_n/DBI2_n

55

DQS2_t

57

VSS28

59

DQ23

61

VSS30

63

DQ19

65

VSS32

67

DQ29

69

VSS34

71

DQ25

73

VSS36 DM3_n/DBI3_n75DQS3_t

77

VSS37

79

DQ30

81

VSS39

83

DQ26

85

VSS41

87

CB5/NC

89

VSS43

91

CB1/NC

93

VSS45 DQS8_c95DM8_n/DBI_n/NC

97

DQS8_t

99

VSS48

101

CB2/NC

103

VSS50

105

CB3/NC

107

VSS52

109

CKE0

111

VDD1

113

BG1

115

BG0

117

VDD3

119

A12

121

A9

123

VDD5

125

A8

127

A6

129

VDD7

131

A3

133

A1

135

VDD9

137

CK0_t

139

CK0_c

141

VDD11

143

PARITY

145

BA1

147

VDD13

149

CS0_n

151

WE_n/A14

153

VDD15

155

ODT0

157

CS1_n

159

VDD17

161

ODT1

163

VDD19

165

C1, CS3_n,NC

167

VSS53

169

DQ37

171

VSS55

173

DQ33

175

VSS57

177

DQS4_c

179

DQS4_t

181

VSS60

183

DQ38

185

VSS62

187

DQ34

189

VSS64

191

DQ44

193

VSS66

195

DQ40

197

VSS68

199

DM5_n/DBI5_n

201

VSS69

203

DQ46

205

VSS71

207

DQ42

209

VSS73

211

DQ52

213

VSS75

215

DQ49

217

VSS77

219

DQS6_c

221

DQS6_t

223

VSS80

225

DQ55

227

VSS82

229

DQ51

231

VSS84

233

DQ61

235

VSS86

237

DQ56

239

VSS88

241

DM7_n/DBI7_n

243

VSS89

245

DQ62

247

VSS91

249

DQ58

251

VSS93

253

SCL

255

VDDSPD

257

VPP1

259

VPP2

261

GND1

BELLW_80888-2021 CONN@

3

2

+1.2V_MEM+1.2V_MEM

2

VSS2

DQ4

VSS4

DQ0

VSS6

VSS7

DQ6

VSS9

DQ2

VSS11

DQ12

VSS13

DQ8

VSS15

DQS1_c

DQS1_t

VSS18

DQ14

VSS20

DQ11

VSS22

DQ20

VSS24

DQ16

VSS26

VSS27

DQ22

VSS29

DQ18

VSS31

DQ28

VSS33

DQ24

VSS35

DQS3_c

VSS38

DQ31

VSS40

DQ27

VSS42

CB4/NC

VSS44

CB0/NC

VSS46

VSS47

CB6/NC

VSS49

CB7/NC

VSS51

RESET_n

CKE1 VDD2

ACT_n

ALERT_n

VDD4

A11

A7

VDD6

A5 A4

VDD8

A2

EVENT_n/NF

VDD10

CK1_t/NF

CK1_c/NF

VDD12

A0

A10/AP VDD14

BA0

RAS_n/A16

VDD16

CAS_n/A15

A13

VDD18

C0/CS2_n/NC

VREFCA

SA2

VSS54

DQ36

VSS56

DQ32

VSS58

DM4_n/DBI4_n

VSS59

DQ39

VSS61

DQ35

VSS63

DQ45

VSS65

DQ41

VSS67

DQS5_c

DQS5_t

VSS70

DQ47

VSS72

DQ43

VSS74

DQ53

VSS76

DQ48

VSS78

DM6_n/DBI6_n

VSS79

DQ54

VSS81

DQ50

VSS83

DQ60

VSS85

DQ57

VSS87

DQS7_c

DQS7_t

VSS90

DQ63

VSS92

DQ59

VSS94

SDA

SA0 VTT SA1

GND2

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

DDR_B_D5

4 6

DDR_B_D0

8 10 12 14

DDR_B_D2

16 18

DDR_B_D7

20 22

DDR_B_D8

24 26

DDR_B_D14

28 30

DDR_B_DQS#1

32

DDR_B_DQS1

34 36

DDR_B_D11

38 40

DDR_B_D15

42 44

DDR_B_D17

46 48

DDR_B_D16

50 52 54 56

DDR_B_D23

58 60

DDR_B_D21

62 64

DDR_B_D28

66 68

DDR_B_D27

70 72

DDR_B_DQS#3

74

DDR_B_DQS3

76 78

DDR_B_D26

80 82

DDR_B_D24

84 86

DDR_B_CB1

88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144

146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 206 208 210 212 214 216 218 220 222 224 226 228 230 232 234 236 238 240 242 244 246 248 250 252 254 256 258 260 262

DDR_B_CB3

DDR_B_CB6

DDR_B_CB0

DDR_B_DRAMRST# DDR_B_CKE3

DDR_B_ACT# DDR_B_ALERT#

DDR_B_MA11 DDR_B_MA7

DDR_B_MA5 DDR_B_MA4

DDR_B_MA2 JDIMM3_EVENT#

DDR_B_CLK3 DDR_B_CLK#3

DDR_B_MA0

DDR_B_MA10

DDR_B_BA0 DDR_B_MA16

DDR_B_MA15 DDR_B_MA13

DIMM3_SA2

DDR_B_D38

DDR_B_D39

DDR_B_D36

DDR_B_D37

DDR_B_D44

DDR_B_D45

DDR_B_DQS#5 DDR_B_DQS5

DDR_B_D47

DDR_B_D43

DDR_B_D51

DDR_B_D54

DDR_B_D53

DDR_B_D49

DDR_B_D59

DDR_B_D62

DDR_B_DQS#7 DDR_B_DQS7

DDR_B_D58

DDR_B_D63

DIMM3_SA0

DIMM3_SA1

DDR_B_CB1 <8,17>

DDR_B_CB3 <8,17>

DDR_B_CB6 <8,17>

DDR_B_CB0 <8,17>

1 2

CD123 0.1U_0402_10V6K@

DDR_B_CKE3 <8 >

DDR_B_ACT# <8,17> DDR_B_ALERT# <8,17>

DDR_B_CLK3 <8> DDR_B_CLK#3 <8>

DDR_B_BA0 <8,17> DDR_B_MA16 <8,17>

DDR_B_MA15 <8,17>

T54 PAD~D@

+V_DDR_REFCA_B

DDR_XDP_WAN_SMBDAT <7,14,15,17,23,41>DDR_XDP_WAN_SMBCLK<7,14,15,17,23,41>

+0.6V_DDR_VTT

+V_DDR_REFCA_B

2

Top

TopTop Side

Side

SideSide

AAAA

JDIMM2

RD5 1K_0402_ 5%@

RD41 2_0402_1%

0.022U_0402_16V7K

1

CD136

2

24.9_0402_1%

12

RD34

1 2

RD11 0_0402_5%@

JDIMM1

DDDD

Bottom

BottomBottom

Side

SideSide

DDR_B_DRAMRST#

1 2

1

2

CPU

+DDR_VREF_B_DQ

+DIMM_DQ_R_VREF_B +V_DDR_REFCA_B

DELL CONFIDENTIAL/PROPRIETARY

Title

DDRIII-SODIMM SLOT3

Size Document Number Rev

Date: Sheet of

1

JDIMM3

CCCC BBBB

JDIMM4

DDR_B_DRAMRST# <14,17>

PCH_THERMTRIP#JDIMM3_EVENT#

+DIMM_DQ_R_VREF_B

RD14 0_0402_5%@

0.1U_0402_10V6K

@

CD143

Compal Electronics, Inc.

0.1U_0402_10V6K

1

2

1 2

@

CD137

1

2

LA-C551P

1

PCH_THERMTRIP# <7,14,15,17,19,46>

+1.2V_MEM

1K_0402_5%

12

RD43

1

2

0.1U_0402_10V6K 1K_0402_5%

@

12

RD44

CD138

1

2

+1.2V_MEM

12

16 74Tuesday, August 18, 2015

0.1U_0402_10V6K

@

CD139

0.1U_0402_10V6K

@

CD140

0.1U_0402_10V6K

1K_0402_5%

@

CD142

RD46

1

2

1K_0402_5%

@

RD47

1.0

5

DDR_B_DQS#[0..7]<8,16>

DDR_B_DQS[0..7]<8,16>

DDR_B_D[0..63]<8,16>

DDR_B_MA[0..13]<8,16 >

D D

+2.5V_MEM

10U_0603_6.3V6M

1U_0402_6.3V6K

1

CD69

2

+1.2V_MEM

10U_0603_6.3V6M

CD114

1

2

C C

B B

DIMM Select

DIMM SelectDIMM Select

DIMM2

DIMM4

****

DIMM1 1

DIMM3

A A

1

2

Layout Note: Place near JDIMM4.258

SA0 SA1

0

0 1

0

1 1

1U_0402_6.3V6K

1

CD58

2

+0.6V_DDR_VTT

SA2

0

CD73

CD74

CD71

2

CD14 change to SGA20331E10

10U_0603_6.3V6M

CD67

CD68

CD57

1

2

1U_0402_6.3V6K

1

CD59

CD116

CD60

2

10U_0603_6.3V6M

1U_0402_6.3V6K

CD121

1

CD72

2

12

RD53

@

0_0402_5%

12

RD55

@

0_0402_5%

10U_0603_6.3V6M

CD63

CD64

1

2

1U_0402_6.3V6K

1

CD117

CD119

2

CD66

+3.3V_RUN+3.3V_RUN+3.3V_RUN

12

RD52

@

0_0402_5%

12

RD56

@

0_0402_5%

10U_0603_6.3V6M

CD70

1

2

1U_0402_6.3V6K

1

CD118

2

+V_DDR_REFCA_B

RD51

@

0_0402_5%

DIMM4_SA0 DIMM4_SA1 DIMM4_SA2

RD54

@

0_0402_5%

4

10U_0603_6.3V6M

330U_D2_2V_Y

1

CD115

CD61

1

+

2

1U_0402_6.3V6K

1

CD120

2

0.1U_0402_10V6K

2.2U_0402_6.3V6M

@

1

CD82

CD81

2

+3.3V_RUN

12

1

2

RD60

@

0_0603_5%

+3.3V_RUN_DIMM4

0.1U_0402_10V6K

2.2U_0402_6.3V6M

@

1

CD65

CD62

2

DDR_B_CB4<8,16 >

DDR_B_CB2<8,16 >

DDR_B_DQS#8<8,16> DDR_B_DQS8<8,16>

DDR_B_CB7<8,16 >

DDR_B_CB5<8,16 >

DDR_B_CKE0<8>

DDR_B_BG1<8,16> DDR_B_BG0<8,16>

DDR_B_CLK0<8> DDR_B_CLK#0<8>

DDR_B_PARITY<8,16>

DDR_B_BA1<8,16>

DDR_B_CS#0<8>

DDR_B_MA14<8,16>

DDR_B_ODT0<8>

DDR_B_CS#1<8>

DDR_B_ODT1<8>

+2.5V_MEM

JDIMM4 REV Type H=4

JDIMM4 REV Type H=4JDIMM4 REV Type H=4

DDR_B_D5

DDR_B_D0

DDR_B_DQS#0 DDR_B_DQS0

DDR_B_D2

DDR_B_D7

DDR_B_D8

DDR_B_D14

DDR_B_D11

DDR_B_D15

DDR_B_D17

DDR_B_D16

DDR_B_DQS#2 DDR_B_DQS2

DDR_B_D23

DDR_B_D21

DDR_B_D28

DDR_B_D27

DDR_B_D26

DDR_B_D24

DDR_B_CB4

DDR_B_CB2

DDR_B_DQS#8 DDR_B_DQS8

DDR_B_CB7

DDR_B_CB5

DDR_B_CKE0

DDR_B_BG1 DDR_B_BG0

DDR_B_MA12 DDR_B_MA9

DDR_B_MA8 DDR_B_MA6

DDR_B_MA3 DDR_B_MA1

DDR_B_CLK0 DDR_B_CLK#0

DDR_B_PARITY

DDR_B_BA1

DDR_B_CS#0 DDR_B_MA14

DDR_B_ODT0 DDR_B_CS#1

DDR_B_ODT1

T57PAD~D @

DDR_B_D38

DDR_B_D39

DDR_B_DQS#4 DDR_B_DQS4

DDR_B_D36

DDR_B_D37

DDR_B_D44

DDR_B_D45

DDR_B_D47

DDR_B_D43

DDR_B_D51

DDR_B_D54

DDR_B_DQS#6 DDR_B_DQS6

DDR_B_D53

DDR_B_D49

DDR_B_D59

DDR_B_D62

DDR_B_D58

DDR_B_D63

+3.3V_RUN_DIMM4

3

JDIMM4

1

VSS1

3

DQ5

5

VSS3

7

DQ1

9

VSS5 DQS0_c11DM0_n/DBI0_n

13

DQS0_t

15

VSS8

17

DQ7

19

VSS10

21

DQ3

23

VSS12

25

DQ13

27

VSS14

29

DQ9

31

VSS16

33

DM1_n/DBI_n

35

VSS17

37

DQ15

39

VSS19

41

DQ10

43

VSS21

45

DQ21

47

VSS23

49

DQ17

51

VSS25 DQS2_c53DM2_n/DBI2_n

55

DQS2_t

57

VSS28

59

DQ23

61

VSS30

63

DQ19

65

VSS32

67

DQ29

69

VSS34

71

DQ25

73

VSS36 DM3_n/DBI3_n75DQS3_t

77

VSS37

79

DQ30

81

VSS39

83

DQ26

85

VSS41

87

CB5/NC

89

VSS43

91

CB1/NC

93

VSS45 DQS8_c95DM8_n/DBI_n/NC

97

DQS8_t

99

VSS48

101

CB2/NC

103

VSS50

105

CB3/NC

107

VSS52

109

CKE0

111

VDD1

113

BG1

115

BG0

117

VDD3

119

A12

121

A9

123

VDD5

125

A8

127

A6

129

VDD7

131

A3

133

A1

135

VDD9

137

CK0_t

139

CK0_c

141

VDD11

143

PARITY

145

BA1

147

VDD13

149

CS0_n

151

WE_n/A14

153

VDD15

155

ODT0

157

CS1_n

159

VDD17

161

ODT1

163

VDD19

165

C1, CS3_n,NC

167

VSS53

169

DQ37

171

VSS55

173

DQ33

175

VSS57

177

DQS4_c

179

DQS4_t

181

VSS60

183

DQ38

185

VSS62

187

DQ34

189

VSS64

191

DQ44

193

VSS66

195

DQ40

197

VSS68

199

DM5_n/DBI5_n

201

VSS69

203

DQ46

205

VSS71

207

DQ42

209

VSS73

211

DQ52

213

VSS75

215

DQ49

217

VSS77

219

DQS6_c

221

DQS6_t

223

VSS80

225

DQ55

227

VSS82

229

DQ51

231

VSS84

233

DQ61

235

VSS86

237

DQ56

239

VSS88

241

DM7_n/DBI7_n

243

VSS89

245

DQ62

247

VSS91

249

DQ58

251

VSS93

253

SCL

255

VDDSPD

257

VPP1

259

VPP2

261

GND1

LOTES_ADDR0107-P005A CONN@

VSS11

VSS13

VSS15

DQS1_c

DQS1_t

VSS18

VSS20

VSS22

VSS24

VSS26

VSS27

VSS29

VSS31

VSS33

VSS35

DQS3_c

VSS38

VSS40

VSS42

CB4/NC

VSS44

CB0/NC

VSS46

VSS47

CB6/NC

VSS49

CB7/NC

VSS51

RESET_n

ACT_n

ALERT_n

EVENT_n/NF

VDD10

CK1_t/NF

CK1_c/NF

VDD12

A10/AP VDD14

RAS_n/A16

VDD16

CAS_n/A15

VDD18

C0/CS2_n/NC

VREFCA

VSS54

VSS56

VSS58

DM4_n/DBI4_n

VSS59

VSS61

VSS63

VSS65

VSS67

DQS5_c

DQS5_t

VSS70

VSS72

VSS74

VSS76

VSS78

DM6_n/DBI6_n

VSS79

VSS81

VSS83

VSS85

VSS87

DQS7_c

DQS7_t

VSS90

VSS92

VSS94

GND2

2

+1.2V_MEM+1.2V_MEM

Top

AAAA

JDIMM2

RD12 1K_0402_5%@

TopTop Side

Side

SideSide

JDIMM1

DDDD

Bottom

BottomBottom Side

Side

SideSide

DDR_B_DRAMRST#

1 2

2

VSS2

DQ4

VSS4

DQ0

VSS6

VSS7

DQ6

VSS9

DQ2

DQ12

DQ8

DQ14

DQ11

DQ20

DQ16

DQ22

DQ18

DQ28

DQ24

DQ31

DQ27

CKE1 VDD2

VDD4

A11

A7

VDD6

A5 A4

VDD8

A2

A0

BA0

A13

SA2

DQ36

DQ32

DQ39

DQ35

DQ45

DQ41

DQ47

DQ43

DQ53

DQ48

DQ54

DQ50

DQ60

DQ57

DQ63

DQ59

SDA

SA0 VTT SA1

DDR_B_D4

4 6

DDR_B_D1

8 10 12 14

DDR_B_D6

16 18

DDR_B_D3

20 22

DDR_B_D10

24 26

DDR_B_D9

28 30

DDR_B_DQS#1

32

DDR_B_DQS1

34 36

DDR_B_D12

38 40

DDR_B_D13

42 44

DDR_B_D18

46 48

DDR_B_D22

50 52 54 56

DDR_B_D19

58 60

DDR_B_D20

62 64

DDR_B_D25

66 68

DDR_B_D30

70 72

DDR_B_DQS#3

74

DDR_B_DQS3

76 78

DDR_B_D29

80 82

DDR_B_D31

84 86

DDR_B_CB1

88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144

146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 206 208 210 212 214 216 218 220 222 224 226 228 230 232 234 236 238 240 242 244 246 248 250 252 254 256 258 260 262

DDR_B_CB3

DDR_B_CB6

DDR_B_CB0

DDR_B_DRAMRST# DDR_B_CKE1

DDR_B_ACT# DDR_B_ALERT#

DDR_B_MA11 DDR_B_MA7

DDR_B_MA5 DDR_B_MA4

DDR_B_MA2 JDIMM4_EVENT#

DDR_B_CLK1 DDR_B_CLK#1

DDR_B_MA0

DDR_B_MA10

DDR_B_BA0 DDR_B_MA16

DDR_B_MA15 DDR_B_MA13

DIMM4_SA2

DDR_B_D35

DDR_B_D34

DDR_B_D33

DDR_B_D32

DDR_B_D40

DDR_B_D41

DDR_B_DQS#5 DDR_B_DQS5

DDR_B_D42

DDR_B_D46

DDR_B_D48

DDR_B_D52

DDR_B_D50

DDR_B_D55

DDR_B_D57

DDR_B_D61

DDR_B_DQS#7 DDR_B_DQS7

DDR_B_D56

DDR_B_D60

DIMM4_SA0

DIMM4_SA1

DDR_B_CB1 <8,16>

DDR_B_CB3 <8,16>

DDR_B_CB6 <8,16>

DDR_B_CB0 <8,16>

1 2

CD124 0.1U_0402_10V6K@

DDR_B_CKE1 <8 >

DDR_B_ACT# <8,16> DDR_B_ALERT# <8,16>

DDR_B_CLK1 <8> DDR_B_CLK#1 <8>

DDR_B_BA0 <8,16> DDR_B_MA16 <8,16>

DDR_B_MA15 <8,16>

T56 PAD~D@

+V_DDR_REFCA_B

DDR_XDP_WAN_SMBDAT <7,14,15,16,23,41>DDR_XDP_WAN_SMBCLK<7,14,15,16,23,41>

+0.6V_DDR_VTT

+V_DDR_REFCA_B

CPU

JDIMM3

CCCC BBBB

JDIMM4

PCH_THERMTRIP#JDIMM4_EVENT#

1

DDR_B_DRAMRST# <14,16>

PCH_THERMTRIP# <7,14,15,16,19,46>

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

DDRIII-SODIMM SLOT4

Size Document Number Rev

Date: Sheet of

LA-C551P

1

17 74Tuesday, August 18, 2015

1.0

5

PEG_CRX_C_GTX_P[ 0..15]<6>

PEG_CRX_C_GTX_N[0. .15]<6>

PEG_CTX_C_GRX_P[ 0..15]<6>

PEG_CTX_C_GRX_N[0. .15]<6>

D D

PEG_CRX_C_GTX_P[ 0..15]

PEG_CRX_C_GTX_N[0. .15]

PEG_CTX_C_GRX_P[ 0..15]

PEG_CTX_C_GRX_N[0. .15]

4

+3.3V_MXM

R3 4.3K_0402 _5%@

R5 4.3K_0402 _5%@

R1977 10K_0402_5%

R1978 10K_0402_5%

3

+3.3V_MXM

MXM_ALERT#

10K_0402_5%

R4

12

S

DGPU_PEX_RST#

G

2

13

D

Q5 DMN65D8LW-7_ SOT323-3

DGPU_ALERT# <45>

DAT_DDC2_DOCK

1 2

CLK_DDC2_DOCK

1 2

DGPU_PWROK GPU_SMBDAT_R

1 2

MXM_CLK_REQ#

1 2

GPU_SMBCLK_R

+3.3V_MXM

4.7K_0402_5%

12

@

R1

2

+3.3V_MXM

4.7K_0402_5%

12

@

R2

DMN66D0LDW-7 _SOT363-6

Q295B

DMN66D0LDW-7 _SOT363-6

1

2

61

Q295A

354

UPD_GPU_SMBDAT <44,46>

UPD_GPU_SMBCLK <44,46>

+MXM_PWR_SRC

JMXM1A

1

PWR_SRC

3

PWR_SRC

5

PWR_SRC

7

PWR_SRC

9

E1 E2

PWR_SRC

11

PWR_SRC

13

PWR_SRC

15

PWR_SRC

17

PWR_SRC

19

OEM1 OEM3 OEM5 OEM7

C90

U16

PWR_SRC

21

GND

23

GND

25

GND

27

GND

29

GND

31

GND

33

E3 E4

GND

35

GND

37

GND

39

GND

41

5V

43

5V

45

5V

47

5V

49

5V

51

GND

53

GND

55

GND

57

GND

59

PEX_STD_SW#

61

VGA_DISABLE#

63

PNL_PWR_EN

65

PNL_BL_EN

67

PNL_BL_PWM

69

HDMI_CEC

71

DVI_HPD

73

LVDS_DDC_DAT

75

LVDS_DDC_CLK

77

GND

79

OEM

81

OEM

83

OEM

85

OEM

87

GND

89

PEX_RX15#

91

PEX_RX15

93

GND

95

PEX_RX14#

97

PEX_RX14

99

GND

101

PEX_RX13#

103

PEX_RX13

105

GND

107

PEX_RX12#

109

PEX_RX12

111

GND

113

PEX_RX11#

115

PEX_RX11

117

GND

119

PEX_RX10#

121

PEX_RX10

123

GND

125

PEX_RX9#

127

PEX_RX9

129

GND

131

PEX_RX8#

133

PEX_RX8

135

GND

137

PEX_RX7#

139

PEX_RX7

141

GND

143

PEX_RX6#

145

PEX_RX6

147

GND

149

PEX_RX5#

151

PEX_RX5

153

GND

155

PEX_RX4#

157

PEX_RX4

159

GND

161

PEX_RX3#

163

PEX_RX3

165

GND

FOX_AS0B826-S4 3B1-7H

CONN@

DGPU_HOLD_RST# <24>

PLTRST_GPU# <22>

100K_0402_5%

12

R51

MXM_DP_HDMI_HPD <45>

+5V_MXM

10U_0805_6.3V6M

0.1U_0402_16V7K

1

C328

C7

+5V_MXM

2

100mil(2.5A, 5VIA)

1 2

R1970 0_0402_5%@

1 2

R1971 0_0402_5%@

MXM_VGA_DIS#<45>

C C

B B

A A

DGPU_PEX_RST#

12

MXM_ENVDD<30>

MXM_PANEL_BKEN<30>

MXM_BIA_PWM<30>

GC6_FB_EN<24>

100K_0402_5%

@

R3750

MXM_DPC_HPD

MXM_DPA_HPD

MXM_DPB_HPD

T215PAD~D @

T208PAD~D @ T207PAD~D @

GC6_FB_EN

T209PAD~D @

PEG_CRX_C_GTX_N15 PEG_CRX_C_GTX_P1 5

PEG_CRX_C_GTX_N14 PEG_CRX_C_GTX_P1 4

PEG_CRX_C_GTX_N13 PEG_CRX_C_GTX_P1 3

PEG_CRX_C_GTX_N12 PEG_CRX_C_GTX_P1 2

PEG_CRX_C_GTX_N11 PEG_CRX_C_GTX_P1 1

PEG_CRX_C_GTX_N10 PEG_CRX_C_GTX_P1 0

PEG_CRX_C_GTX_N9 PEG_CRX_C_GTX_P9

PEG_CRX_C_GTX_N8 PEG_CRX_C_GTX_P8

PEG_CRX_C_GTX_N7 PEG_CRX_C_GTX_P7

PEG_CRX_C_GTX_N6 PEG_CRX_C_GTX_P6

PEG_CRX_C_GTX_N5 PEG_CRX_C_GTX_P5

PEG_CRX_C_GTX_N4 PEG_CRX_C_GTX_P4

PEG_CRX_C_GTX_N3 PEG_CRX_C_GTX_P3

+3.3V_ALW

0.1U_0402_1 0V7K

5

P

IN1

4

O

IN2

G

3

SN74AHC1G08DCKR_SC70 -5

1 2

R19 0_0402_5%@

D7

2 1

RB751VM-40TE-17_ SOD323-2

D8

2 1

RB751VM-40TE-17_ SOD323-2

D18

2 1

RB751VM-40TE-17_ SOD323-2

5

@

1 2

1

2

PWR_SRC PWR_SRC PWR_SRC PWR_SRC PWR_SRC PWR_SRC PWR_SRC PWR_SRC PWR_SRC PWR_SRC

PRSNT_R#

WAKE#

PWR_GOOD

PWR_EN

PWR_LEVEL TH_OVERT#

TH_ALERT#

TH_PWM

SMB_DAT SMB_CLK

PEX_TX15#

PEX_TX15

PEX_TX14#

PEX_TX14

PEX_TX13#

PEX_TX13

PEX_TX12#

PEX_TX12

PEX_TX11#

PEX_TX11

PEX_TX10#

PEX_TX10

PEX_TX9#

PEX_TX9

PEX_TX8#

PEX_TX8

PEX_TX7#

PEX_TX7

PEX_TX6#

PEX_TX6

PEX_TX5#

PEX_TX5

PEX_TX4#

PEX_TX4

PEX_TX3#

PEX_TX3

LInk CIS

LInk CISLInk CIS

GPIO0 GPIO1 GPIO2

RSVD RSVD RSVD RSVD

GND GND GND GND GND GND GND GND GND GND

GND OEM OEM OEM OEM GND

GND

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78

OEM0

80

OEM2

82

OEM4

84

OEM6

86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164

MXM_DPB_HPD_GATE

12

MXM_PWR_LEVEL

400mil(10A)

10U_0805_25VAK

1

C2

2

1 2

R1972 0_0402_5%@

MXM_PWR_LEVEL MXM_OVERT# MXM_ALERT#

GPU_SMBDAT_R GPU_SMBCLK_R

SYSTEM

SYSTEMSYSTEM

GPU_EVENT#_D

D94 RB751VM-40TE-17_SOD323-2

PEG_CTX_C_GRX_N15 PEG_CTX_C_GRX_P1 5

PEG_CTX_C_GRX_N14 PEG_CTX_C_GRX_P1 4

PEG_CTX_C_GRX_N13 PEG_CTX_C_GRX_P1 3

PEG_CTX_C_GRX_N12 PEG_CTX_C_GRX_P1 2

PEG_CTX_C_GRX_N11 PEG_CTX_C_GRX_P1 1

PEG_CTX_C_GRX_N10 PEG_CTX_C_GRX_P1 0

PEG_CTX_C_GRX_N9 PEG_CTX_C_GRX_P9

PEG_CTX_C_GRX_N8 PEG_CTX_C_GRX_P8

PEG_CTX_C_GRX_N7 PEG_CTX_C_GRX_P7

PEG_CTX_C_GRX_N6 PEG_CTX_C_GRX_P6

PEG_CTX_C_GRX_N5 PEG_CTX_C_GRX_P5

PEG_CTX_C_GRX_N4 PEG_CTX_C_GRX_P4

PEG_CTX_C_GRX_N3 PEG_CTX_C_GRX_P3

4

100K_0402_5%

@

R758

4

+MXM_PWR_SRC

0.1U_0603_25V7K

68P_0402_50V8J

680P_0603_50V7K

1

C1

C4

C3

2

MXM_PRESENTR# <19> PCIE_WAKE# <38 ,39,44,45>

DGPU_PWROK

DGPU_PWROK <23,45> DGPU_PWR_EN <45>

MXM_PWR_LEVEL <57>

MXM_PIN80_R for 3D function usage

MXM_PIN80_R for 3D function usageMXM_PIN80_R for 3D function usage (JMXM1_pin 80).

(JMXM1_pin 80).

(JMXM1_pin 80).(JMXM1_pin 80). 310 pin connector=Pin80

310 pin connector=Pin80

310 pin connector=Pin80310 pin connector=Pin80 314 pin connector=pin84

314 pin connector=pin84

314 pin connector=pin84314 pin connector=pin84

T210 PAD~D@ T211 PAD~D@

2 1

T212 PAD~D@

+3.3V_MXM

0.1U_0402_1 0V7K

5

P

IN1

O

IN2

G

3

SN74AHC1G08DCKR_SC70 -5

+3.3V_MXM

100K_0402_5%

12

R37

1

2

Docking port1

Docking port1Docking port1

GPU_EVENT#

C96

@

1 2

DGPU_PEX_RST#_D DGPU_PEX_RST#_D DGPU_PEX_RST#_D

U14

+3.3V_ALW

4

Y

GPU_EVENT# <24>

TBT/

TBT/TBT/ Docking DP port 2

Docking DP port 2

Docking DP port 2Docking DP port 2

C92

@

1 2

0.1U_0402_1 0V7K

5

U17

1

B

VCC

2

A

G

MC74VHC1G09DFT2G_SC7 0-5

3

ACAV_IN <46,57,6 0>

GPU_PWR_LEVEL <45>

MXM_DPA_AUXN<32> MXM_DPA_AUXP<32>

MXM_PRESENTL#<19>

4

O

100K_0402_5%

@

R519

1 2

DGPU_PEX_RST# DGPU_PEX_RST#_D DGPU_PWROK

3

PEG_CRX_C_GTX_N2 PEG_CRX_C_GTX_P2

PEG_CRX_C_GTX_N1 PEG_CRX_C_GTX_P1

PEG_CRX_C_GTX_N0 PEG_CRX_C_GTX_P0

CLK_PEG_N0<21> CLK_PEG_P0<21>

MXM_DPC_N0<31> MXM_DPC_P0<31>

MXM_DPC_N1<31> MXM_DPC_P1<31>

MXM_DPC_N2<31> MXM_DPC_P2<31>

MXM_DPC_N3<31> MXM_DPC_P3<31>

MXM_DPC_AUXN<31> MXM_DPC_AUXP<31>

+3.3V_MXM +3.3V_MXM

5

3

CLK_PEG_N0 CLK_PEG_P0

MXM_DPC_N0 MXM_DPC_P0

MXM_DPC_N1 MXM_DPC_P1

MXM_DPC_N2 MXM_DPC_P2

MXM_DPC_N3 MXM_DPC_P3

MXM_DPC_AUXN MXM_DPC_AUXP

MXM_DPA_N0

MXM_DPA_N0<32>

MXM_DPA_P0

MXM_DPA_P0<32>

MXM_DPA_N1

MXM_DPA_N1<32>

MXM_DPA_P1

MXM_DPA_P1<32>

MXM_DPA_N2

MXM_DPA_N2<32>

MXM_DPA_P2

MXM_DPA_P2<32>

MXM_DPA_N3

MXM_DPA_N3<32>

MXM_DPA_P3

MXM_DPA_P3<32>

MXM_DPA_AUXN MXM_DPA_AUXP MXM_PRESENTL#

C95

@

1 2

0.1U_0402_1 0V7K

1

P

IN1

2

IN2

G

U25

SN74AHC1G08DCKR_SC70 -5

D95

@

21

RB751VM-40TE-17_ SOD323-2

PROPRIETARY NOT E: THIS SHEET OF ENGINEERING DRAWING AND SP ECIFICATIONS CO NTAINS CONFIDE NTIAL TRADE SECRET AN D OTHER PROPRI ETARY INFORMATI ON OF DELL INC . ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITH OUT THE EXPRESS WRITTEN AUTHO RIZATION OF DEL L. IN ADDITION , NEITHER THIS SH EET NOR THE IN FORMATION IT CO NTAINS WAY BE USED BY OR DISC LOSED TO ANY T HIRD PARTY WITHOUT D ELL'S EXPRESS WRITTEN CONSENT .

+3.3V_MXM

12

167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 205 207 209 211 213 215 217 219 221 223 225 227 229 231 233 235 237 239 241 243 245 247 249 251 253 255 257 259 261 263 265 267 269 271 273 275 277 279 281 283 285 287 289 291 293 295 297 299 301 303 305 307 309 311 313 314

315

10K_0402_5%

@

R71

1000P_0402_50V7K

@

1

C1470

2

JMXM1B

GND PEX_RX2# PEX_RX2 GND PEX_RX1# PEX_RX1 GND PEX_RX0# PEX_RX0 GND PEX_REFCLK#

PEX_CLK_REQ# PEX_REFCLK GND RSVD RSVD RSVD RSVD RSVD LVDS_UCLK# LVDS_UCLK GND LVDS_UTX3# LVDS_UTX3 GND LVDS_UTX2# LVDS_UTX2 GND LVDS_UTX1# LVDS_UTX1 GND LVDS_UTX0# LVDS_UTX0 GND DP_C_L0# DP_C_L0 GND DP_C_L1# DP_C_L1 GND DP_C_L2# DP_C_L2 GND DP_C_L3# DP_C_L3 GND DP_C_AUX# DP_C_AUX RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD GND DP_A_L0# DP_A_L0 GND DP_A_L1# DP_A_L1 GND DP_A_L2# DP_A_L2 GND DP_A_L3# DP_A_L3 GND DP_A_AUX# DP_A_AUX PRSNT_L#

GND

FOX_AS0B826-S4 3B1-7H

CONN@

LInk CIS

LInk CISLInk CIS

MXM_DPA_HPD_GATEMXM_DPC_HPD_GATE

100K_0402_5%

12

@

R60

1 2

R72 0_0402_5%@

PEX_TX2#

PEX_TX2

PEX_TX1#

PEX_TX1

PEX_TX0#

PEX_TX0

PEX_RST# VGA_DDC_DAT VGA_DDC_CLK

VGA_VSYNC

VGA_HSYNC

VGA_RED

VGA_GREEN

VGA_BLUE

LVDS_LCLK#

LVDS_LCLK

LVDS_LTX3#

LVDS_LTX3

LVDS_LTX2#

LVDS_LTX2

LVDS_LTX1#

LVDS_LTX1

LVDS_LTX0#

LVDS_LTX0

DP_D_L0#

DP_D_L0

DP_D_L1#

DP_D_L1

DP_D_L2#

DP_D_L2

DP_D_L3#

DP_D_L3

DP_D_AUX#

DP_D_AUX

DP_C_HPD

DP_D_HPD

DP_B_L0#

DP_B_L0

DP_B_L1#

DP_B_L1

DP_B_L2#

DP_B_L2

DP_B_L3#

DP_B_L3

DP_B_AUX#

DP_B_AUX

DP_B_HPD

DP_A_HPD

2

GND

RSVD RSVD RSVD

GND

3V3 3V3

GND

166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 206 208 210 212 214 216 218 220 222 224 226 228 230 232 234 236 238 240 242 244 246 248 250 252 254 256 258 260 262 264 266 268 270 272 274 276 278 280 282 284 286 288 290 292 294 296 298 300 302 304 306 308 310 312

316

5

4

O

3

100K_0402_5%

12

R135

PEG_CTX_C_GRX_N2 PEG_CTX_C_GRX_P2

PEG_CTX_C_GRX_N1 PEG_CTX_C_GRX_P1

PEG_CTX_C_GRX_N0 PEG_CTX_C_GRX_P0

MXM_CLK_REQ# DGPU_PEX_RST# DAT_DDC2_DOCK CLK_DDC2_DOCK VSYNC_DOCK HSYNC_DOCK

RED_DOCK GREEN_DOCK BLUE_DOCK

MXM_EDP_N0 MXM_EDP_P0

MXM_EDP_N1 MXM_EDP_P1

MXM_EDP_N2 MXM_EDP_P2

MXM_EDP_N3 MXM_EDP_P3

MXM_EDP_AUXN MXM_EDP_AUXP MXM_DPC_HPD_GATE MXM_EDP_HPD

MXM_DPB_N0 MXM_DPB_P0

MXM_DPB_N1 MXM_DPB_P1

MXM_DPB_N2 MXM_DPB_P2

MXM_DPB_N3 MXM_DPB_P3

MXM_DPB_AUXN MXM_DPB_AUXP MXM_DPB_HPD_GATE MXM_DPA_HPD_GATE

C94

@

1 2

0.1U_0402_1 0V7K

1

P

IN1

2

IN2

G

U27

SN74AHC1G08DCKR_SC70 -5

MXM_OVERT#

DAT_DDC2_DOCK <43>

CLK_DDC2_DOCK <43> VSYNC_DOCK <43> HSYNC_DOCK <43>

RED_DOCK <43 > GREEN_DOCK <43> BLUE_DOCK <43>

MXM_EDP_N0 <29> MXM_EDP_P0 <29>

MXM_EDP_N1 <29> MXM_EDP_P1 <29>

MXM_EDP_N2 <29> MXM_EDP_P2 <29>

MXM_EDP_N3 <29> MXM_EDP_P3 <29>

MXM_EDP_AUXN <29> MXM_EDP_AUXP <29>

MXM_EDP_HPD <29>

+3.3V_MXM

MXM_DPB_N0 <33> MXM_DPB_P0 <33>

MXM_DPB_N1 <33> MXM_DPB_P1 <33>

MXM_DPB_N2 <33> MXM_DPB_P2 <33>

MXM_DPB_N3 <33> MXM_DPB_P3 <33>

MXM_DPB_AUXN <33> MXM_DPB_AUXP <33>

+3.3V_MXM

40mil(1A)

+3.3V_MXM

0.1U_0402_10V6K

10U_0603_6.3V6M

1

C8

C332

2

MXM_DPA_HPD <32>MXM_DPC_HPD <31>MXM_DPB_HPD <33>

+3.3V_MXM

+3.3V_ALW

10K_0402_5%

12

R10

10K_0402_5%

12

R11

DGPU_PEX_RST#

G

2

13

THERMATRIP3# <46>

D

S

Q4 DMN65D8LW-7_ SOT323-3

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Docking

Docking Docking CRT

CRT

CRTCRT

eDP MUX

eDP MUXeDP MUX

TBT/mDP

TBT/mDPTBT/mDP

MXM

LA-C551P

1

1.0

18 74Tuesday, August 18, 2015

5

4

3

2

1

UH1C

AV2

CL_CLK

AV3

CL_DATA

AW2

CL_RST#

R44

GPP_G8/FAN_PWM_0

R43

GPP_G9/FAN_PWM_1

U39

GPP_G10/FAN_PWM_2

N42

GPP_G11/FAN_PWM_3

U43

GPP_G0/FAN_TACH_0

U42

GPP_G1/FAN_TACH_1

U41

GPP_G2/FAN_TACH_2

M44

GPP_G3/FAN_TACH_3

U36

GPP_G4/FAN_TACH_4

P44

GPP_G5/FAN_TACH_5

T45

GPP_G6/FAN_TACH_6

T44

GPP_G7/FAN_TACH_7

B33

PCIE11_TXP

C33

PCIE11_TXN

K31

PCIE11_RXP

L31

PCIE11_RXN

AB33

GPP_F10/SCLOCK

AB35

GPP_F11/SLOAD

AA44

GPP_F13/SDATAOUT0

AA45

GPP_F12/SDATAOUT1

B38

PCIE14_TXN/SATA1B_TXN

C38

PCIE14_TXP/SATA1B_TXP

D39

PCIE14_RXN/SATA1B_RXN

E37

PCIE14_RXP/SATA1B_RXP

C36

PCIE13_TXN/SATA0B_TXN

B36

PCIE13_TXP/SATA0B_TXP

G35

PCIE13_RXN/SATA0B_RXN

E35

PCIE13_RXP/SATA0B_RXP

A35

PCIE12_TXP

B35

PCIE12_TXN

H33

PCIE12_RXP

G33

PCIE12_RXN

J45

PCIE20_TXP/SATA7_TXP

K44

PCIE20_TXN/SATA7_TXN

N38

PCIE20_RXP/SATA7_RXP

N39

PCIE20_RXN/SATA7_RXN

H44

PCIE19_TXP/SATA6_TXP

H43

PCIE19_TXN/SATA6_TXN

L39

PCIE19_RXP/SATA6_RXP

L37

PCIE19_RXN/SATA6_RXN

SKL-H-PCH_BGA837

1 2

PCH_CL_CLK1 PCH_CL_DATA1 PCH_CL_RST1#

CAM_MIC_CBL_DET#

TBT_CIO_PLUG_EVENT# MXM_PRESENTL# CONTACTLESS_DET#

MXM_PRESENTR#

PCIE_PTX_DRX_P11 PCIE_PTX_DRX_N11 PCIE_PRX_DTX_P11 PCIE_PRX_DTX_N11

BIOS_REC

CS_CTR

SATA_PTX_DRX_N1 SATA_PTX_DRX_P1 SATA_PRX_DTX_N1 SATA_PRX_DTX_P1

PCIE_PTX_DRX_N13 PCIE_PTX_DRX_P13 PCIE_PRX_DTX_N13 PCIE_PRX_DTX_P13

PCIE_PTX_DRX_P12 PCIE_PTX_DRX_N12 PCIE_PRX_DTX_P12 PCIE_PRX_DTX_N12

PCIE_PTX_DRX_P20 PCIE_PTX_DRX_N20 PCIE_PRX_DTX_P20 PCIE_PRX_DTX_N20 PCIE_PTX_DRX_P19 PCIE_PTX_DRX_N19 PCIE_PRX_DTX_P19 PCIE_PRX_DTX_N19

PCH_CL_CLK1<38>

PCH_CL_DATA1<38>

D D

C C

B B

+3.3V_ALW_PCH

1 2

RH341 10 K_0402_5%

+3.3V_RUN

1 2

RH319 10 K_0402_5%

1 2

RH317 10 K_0402_5%

1 2

RH76 10K_0402_5%

1 2

RH90 10K_0402_5%

1 2

RH91 10K_0402_5%

1 2

RH321 10 K_0402_5%

1 2

RH323 10 K_0402_5%

1 2

RH324 10 K_0402_5%

1 2

RH354 10 K_0402_5%

1 2

RH326 10 K_0402_5%

1 2

RH322 10 K_0402_5%

TBT_CIO_PLUG_EVENT#

CAM_MIC_CBL_DET#

MXM_PRESENTL#

BIOS_REC

CONTACTLESS_DET#

MXM_PRESENTR#

SATA_EXP_IFDET

SATAGP1

HDD_DET#

SATAGP5

SATAGP6

SATAGP7

M.2 SSD Slot#3

Tell EC don't read GFX Temp.in GC6 High: Read; Low: Don`t read

GC6_THM_ON<45>

Dock

WWAN

M.2 SSD Slot#3

M.2 SSD Slot#4

PCH_CL_RST1#<38>

CAM_MIC_CBL_DET#<30>

TBT_CIO_PLUG_EVENT#<44>

MXM_PRESENTL#<18>

CONTACTLESS_DET#<37 >

MXM_PRESENTR#<18>

PCIE_PTX_DRX_P11<39> PCIE_PTX_DRX_N11<39> PCIE_PRX_DTX_P11<39> PCIE_PRX_DTX_N11<39>

RH342 0_ 0402_5%

SATA_PTX_DRX_N1<43> SATA_PTX_DRX_P1<43> SATA_PRX_DTX_N1<43> SATA_PRX_DTX_P1<43>

PCIE_PTX_DRX_N13<38> PCIE_PTX_DRX_P13<38> PCIE_PRX_DTX_N13<38> PCIE_PRX_DTX_P13<38>

PCIE_PTX_DRX_P12<39> PCIE_PTX_DRX_N12<39> PCIE_PRX_DTX_P12<39> PCIE_PRX_DTX_N12<39>

PCIE_PTX_DRX_P20<39> PCIE_PTX_DRX_N20<39> PCIE_PRX_DTX_P20<39> PCIE_PRX_DTX_N20<39> PCIE_PTX_DRX_P19<39> PCIE_PTX_DRX_N19<39> PCIE_PRX_DTX_P19<39> PCIE_PRX_DTX_N19<39>

SPT-H_PCH

CLINK

FAN

PCIE9_RXN/SATA0A_RXN PCIE9_RXP/SATA0A_RXP PCIE9_TXN/SATA0A_TXN

PCIE9_TXP/SATA0A_TXP

PCIE10_RXN/SATA1A_RXN PCIE10_RXP/SATA1A_RXP

PCIE10_TXN/SATA1A_TXN PCIE10_TXP/SATA1A_TXP

PCIE15_RXN/SATA2_RXN PCIE15_RXP/SATA2_RXP

PCIE15_TXN/SATA2_TXN PCIE15_TXP/SATA2_TXP

PCIe/SATA

PCIE16_RXN/SATA3_RXN PCIE16_RXP/SATA3_RXP

PCIE16_TXN/SATA3_TXN PCIE16_TXP/SATA3_TXP

PCIE17_RXN/SATA4_RXN PCIE17_RXP/SATA4_RXP

PCIE17_TXN/SATA4_TXN PCIE17_TXP/SATA4_TXP

PCIE18_RXN/SATA5_RXN PCIE18_RXP/SATA5_RXP

PCIE18_TXN/SATA5_TXN PCIE18_TXP/SATA5_TXP

GPP_E0/SATAXPCIE0/SATAGP0 GPP_E1/SATAXPCIE1/SATAGP1 GPP_E2/SATAXPCIE2/SATAGP2 GPP_F0/SATAXPCIE3/SATAGP3 GPP_F1/SATAXPCIE4/SATAGP4 GPP_F2/SATAXPCIE5/SATAGP5 GPP_F3/SATAXPCIE6/SATAGP6 GPP_F4/SATAXPCIE7/SATAGP7

GPP_F21/EDP_BKLTCTL

GPP_F20/EDP_BKLTEN

GPP_F19/EDP_VDDEN

HOST

GPP_E8/SATALED#

THERMTRIP#

PLTRST_PROC#

PM_DOWN

PM_SYNC

PCIE_PRX_DTX_N9

G31

PCIE_PRX_DTX_P9

H31

PCIE_PTX_DRX_N9

C31

PCIE_PTX_DRX_P9

B31

PCIE_PRX_DTX_N10

G29

PCIE_PRX_DTX_P10

E29

PCIE_PTX_DRX_N10

C32

PCIE_PTX_DRX_P10

B32

PCIE_PRX_DTX_N15

F41

PCIE_PRX_DTX_P15

E41

PCIE_PTX_DRX_N15

B39

PCIE_PTX_DRX_P15

A39

PCIE_PRX_DTX_N16

D43

PCIE_PRX_DTX_P16

E42

PCIE_PTX_DRX_N16

A41

PCIE_PTX_DRX_P16

A40

PCIE_PRX_DTX_N17

H42

PCIE_PRX_DTX_P17

H40

PCIE_PTX_DRX_N17

E45

PCIE_PTX_DRX_P17

F45

PCIE_PRX_DTX_N18

K37

PCIE_PRX_DTX_P18

G37

PCIE_PTX_DRX_N18

G45

PCIE_PTX_DRX_P18

G44

PCH_SATA_LED#

AD44

M2_SLOT3_PEDET

AG36

SATAGP1

AG35

HDD_DET#

AG39

SATA_EXP_IFDET

AD35

M2_SLOT4_PEDET

AD31

SATAGP5

AD38

SATAGP6

AC43

SATAGP7

AB44

BIA_PWM_PCH

W36

PANEL_BKEN_PCH

W35

ENVDD_PCH

W42

PCH_THERMTRIP#_R PCH_THERMTRIP#

AJ3

PCH_PECI H_PECI

AL3

H_PM_SYNC_R

PECI

AJ4

PLTRST_CPU#

AK2

H_PM_DOWN

AH2

3 OF 12REV = 1.3

PCIE_PRX_DTX_N9 <3 9>

PCIE_PRX_DTX_P9 <39> PCIE_PTX_DRX_N9 <3 9> PCIE_PTX_DRX_P9 <39>

PCIE_PRX_DTX_N10 <39>

PCIE_PRX_DTX_P10 <39> PCIE_PTX_DRX_N10 <39> PCIE_PTX_DRX_P10 <39 >

PCIE_PRX_DTX_N15 <42>

PCIE_PRX_DTX_P15 <42> PCIE_PTX_DRX_N15 <42> PCIE_PTX_DRX_P15 <42 >

PCIE_PRX_DTX_N16 <42>

PCIE_PRX_DTX_P16 <42> PCIE_PTX_DRX_N16 <42> PCIE_PTX_DRX_P16 <42 >

PCIE_PRX_DTX_N17 <39>

PCIE_PRX_DTX_P17 <39> PCIE_PTX_DRX_N17 <39> PCIE_PTX_DRX_P17 <39 >

PCIE_PRX_DTX_N18 <39>

PCIE_PRX_DTX_P18 <39> PCIE_PTX_DRX_N18 <39> PCIE_PTX_DRX_P18 <39 >

1 2

RH75 620_0402_5%

1 2

RH73 43_0402_1%

PCH_SATA_LED# <47>

M2_SLOT3_PEDET <39>

HDD_DET# <41> SATA_EXP_IFDET <41,42> M2_SLOT4_PEDET <39>

BIA_PWM_PCH <30> PANEL_BKEN_PCH <30> ENVDD_PCH <30,46>

H_PM_SYNC_R <7> PLTRST_CPU# <7> H_PM_DOWN <7>

M.2 SSD Slot#3

SATA Express

SATA ExpressSATA Express

M.2 SSD Slot#4

SPSGP0

SPSGP3

SPSGP4

M2_SLOT3_PEDET 0=SATA

01SATA_EXP_IFDET

0

M2_SLOT4_PEDET 0=SATA 1=PCIE

PCH_THERMTRIP# <7,14,15,16,17,46> H_PECI <7,46>

0=SATA

PCH_PECI

1=PCIE

12

RH74

@

10K_0402_5%

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

3

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

2

Title

Size Document Number Rev

Date: Sheet of

SKYLAKE PCH-H (1/9)

LA-C551P

19 74Tuesday, August 18, 2015

1

1.0

5

D D

XDP_DBRESET#<7>

RH70 8.2K_0402_ 5%@

ME_RESET#

12

MC74VHC1G09DFT2 G_SC70-5

4

1 2

RH66@ 0_0 402_5%

+3.3V_RUN

CH10

@

1 2

0.1U_0402_25V6K

5

UC3

@

1

B

4

Y

VCC

2

A

G

CIS LINK OK

3

SYS_RESET#

SYS_RESET# <23,37>

3

2

1

UH1B

L27

DMI_RXN0

N27

DMI_RXP0

C27

DMI_TXN0

B27

DMI_TXP0

E24

DMI_RXN1

G24

DMI_RXP1

B28

DMI_TXN1

A28

DMI_TXP1

G27

DMI_RXN2

E26

DMI_RXP2

B29

DMI_TXN2

C29

DMI_TXP2

L29

DMI_RXN3

K29

DMI_RXP3

B30

DMI_TXN3

A30

DMI_TXP3

B18

PCIE_RCOMPN

C17

PCIE_RCOMPP

H15

PCIE1_RXN/USB3_7_RXN

G15

PCIE1_RXP/USB3_7_RXP

A16

PCIE1_TXN/USB3_7_TXN

B16

PCIE1_TXP/USB3_7_TXP

B19

PCIE2_TXN/USB3_8_TXN

C19

PCIE2_TXP/USB3_8_TXP

E17

PCIE2_RXN/USB3_8_RXN

G17

PCIE2_RXP/USB3_8_RXP

L17

PCIE3_RXN/USB3_9_RXN

K17

PCIE3_RXP/USB3_9_RXP

B20

PCIE3_TXN/USB3_9_TXN

C20

PCIE3_TXP/USB3_9_TXP

E20

PCIE4_RXN/USB3_10_RXN

G19

PCIE4_RXP/USB3_10_RXP

B21

PCIE4_TXN/USB3_10_TXN

A21

PCIE4_TXP/USB3_10_TXP

K19

PCIE5_RXN

L19

PCIE5_RXP

D22

PCIE5_TXN

C22

PCIE5_TXP

G22

PCIE6_RXN

E22

PCIE6_RXP

B22

PCIE6_TXN

A23

PCIE6_TXP

L22

PCIE7_RXN

K22

PCIE7_RXP

C23

PCIE7_TXN

B23

PCIE7_TXP

K24

PCIE8_RXN

L24

PCIE8_RXP

C24

PCIE8_TXN

B24

PCIE8_TXP

SKL-H-PCH_BGA837

1 2

DMI_CTX_PRX_N0 DMI_CTX_PRX_P0 DMI_CRX_PTX_N0 DMI_CRX_PTX_P0 DMI_CTX_PRX_N1 DMI_CTX_PRX_P1 DMI_CRX_PTX_N1 DMI_CRX_PTX_P1 DMI_CTX_PRX_N2 DMI_CTX_PRX_P2 DMI_CRX_PTX_N2 DMI_CRX_PTX_P2 DMI_CTX_PRX_N3 DMI_CTX_PRX_P3 DMI_CRX_PTX_N3 DMI_CRX_PTX_P3

PCIECOMP# PCIECOMP

PCIE_PTX_DRX_N2 PCIE_PTX_DRX_P2 PCIE_PRX_DTX_N2 PCIE_PRX_DTX_P2 PCIE_PRX_DTX_N3 PCIE_PRX_DTX_P3 PCIE_PTX_DRX_N3 PCIE_PTX_DRX_P3 PCIE_PRX_DTX_N4 PCIE_PRX_DTX_P4 PCIE_PTX_DRX_N4 PCIE_PTX_DRX_P4 PCIE_PRX_DTX_N5 PCIE_PRX_DTX_P5 PCIE_PTX_DRX_N5 PCIE_PTX_DRX_P5 PCIE_PRX_DTX_N6 PCIE_PRX_DTX_P6 PCIE_PTX_DRX_N6 PCIE_PTX_DRX_P6 PCIE_PRX_DTX_N7 PCIE_PRX_DTX_P7 PCIE_PTX_DRX_N7 PCIE_PTX_DRX_P7 PCIE_PRX_DTX_N8 PCIE_PRX_DTX_P8 PCIE_PTX_DRX_N8 PCIE_PTX_DRX_P8

DMI_CTX_PRX_N0<6>

DMI_CTX_PRX_P0<6> DMI_CRX_PTX_N0<6> DMI_CRX_PTX_P0<6>

DMI_CTX_PRX_N1<6>

DMI_CTX_PRX_P1<6> DMI_CRX_PTX_N1<6> DMI_CRX_PTX_P1<6>

DMI_CTX_PRX_N2<6>

DMI_CTX_PRX_P2<6>

WLAN

LAN

TBT

DMI_CRX_PTX_N2<6> DMI_CRX_PTX_P2<6>

DMI_CTX_PRX_N3<6>

DMI_CTX_PRX_P3<6> DMI_CRX_PTX_N3<6> DMI_CRX_PTX_P3<6>

RH192 100_ 0402_1%

PCIE_PTX_DRX_N2<38> PCIE_PTX_DRX_P2<38>

PCIE_PRX_DTX_N2<38>

PCIE_PRX_DTX_P2<38>

PCIE_PRX_DTX_N3<44>

PCIE_PRX_DTX_P3<44> PCIE_PTX_DRX_N3<44> PCIE_PTX_DRX_P3<44>

PCIE_PRX_DTX_N4<35>

PCIE_PRX_DTX_P4<35> PCIE_PTX_DRX_N4<35> PCIE_PTX_DRX_P4<35>

PCIE_PRX_DTX_N5<44>

PCIE_PRX_DTX_P5<44> PCIE_PTX_DRX_N5<44> PCIE_PTX_DRX_P5<44>

PCIE_PRX_DTX_N6<44>

PCIE_PRX_DTX_P6<44> PCIE_PTX_DRX_N6<44> PCIE_PTX_DRX_P6<44>

PCIE_PRX_DTX_N7<44>

PCIE_PRX_DTX_P7<44> PCIE_PTX_DRX_N7<44> PCIE_PTX_DRX_P7<44>

PCIE_PRX_DTX_N8<44>

PCIE_PRX_DTX_P8<44> PCIE_PTX_DRX_N8<44> PCIE_PTX_DRX_P8<44>

C C

Card reader

B B

A A

SPT-H_PCH

DMI

PCIe/USB 3

USB 2.0

GPP_E9/USB2_OC0# GPP_E10/USB2_OC1# GPP_E11/USB2_OC2# GPP_E12/USB2_OC3#

GPP_F15/USB2_OCB_4 GPP_F16/USB2_OCB_5 GPP_F17/USB2_OCB_6 GPP_F18/USB2_OCB_7

USB2_COMP

USB2_VBUSSENSE

RSVD_AB13

GPD7/RSVD

USB2N_1 USB2P_1 USB2N_2 USB2P_2 USB2N_3 USB2P_3 USB2N_4 USB2P_4 USB2N_5 USB2P_5 USB2N_6 USB2P_6 USB2N_7 USB2P_7 USB2N_8 USB2P_8 USB2N_9

USB2P_9 USB2N_10 USB2P_10 USB2N_11 USB2P_11 USB2N_12 USB2P_12 USB2N_13 USB2P_13 USB2N_14 USB2P_14

USB2_ID

2 OF 12REV = 1.3

USB20_N1

AF5

USB20_P1

AG7

USB20_N2

AD5

USB20_P2

AD7

USB20_N3

AG8

USB20_P3

AG10

USB20_N4

AE1

USB20_P4

AE2

USB20_N5

AC2

USB20_P5

AC3

USB20_N6

AF2

USB20_P6

AF3

USB20_N7

AB3

USB20_P7

AB2

USB20_N8

AL8

USB20_P8

AL7 AA1 AA2

USB20_N10

AJ8

USB20_P10

AJ7

USB20_N11

W2

USB20_P11

W3 AD3 AD2 V2 V1 AJ11 AJ13

USB_OC0#

AD43

USB_OC1#

AD42

USB_OC2#

AD39

USB_OC3#

AC44 Y43 Y41 W44 W43

USB2_COMP

AG3 AD10 AB13 AG2

3.3V_CAM_EN#

BD14

USB20_N1 <44>

----->Left Side JUSB1

USB20_P1 <44> USB20_N2 <44>

----->Right Side JUSB1

USB20_P2 <44> USB20_N3 <44>

----->Right Side JUSB2

USB20_P3 <44> USB20_N4 <44>

----->Right Side JUSB3

USB20_P4 <44> USB20_N5 <43>

----->MLK DOCK

USB20_P5 <43> USB20_N6 <38>

----->M.2 Slot-1 (WLAN/BT/WiGig)

USB20_P6 <38>

----->MLK DOCK

USB20_N7 <43> USB20_P7 <43> USB20_N8 <38>

----->M.2 Slot-2 (WWAN/LTE/HCA)

USB20_P8 <38>

USB20_N10 <37>

----->USH

USB20_P10 <37> USB20_N11 <30>

----->Camera

USB20_P11 <30>

USB_OC0# <44> USB_OC1# <44> USB_OC2# <44> USB_OC3# <44>

1 2 1 2

RH193 11 3_0402_1% RH355 1K_ 0402_5%

1 2

RH356 0_0402_5%@

3.3V_CAM_EN# <30 >

USB_OC1# USB_OC2# USB_OC3# USB_OC0#

RPH6

1 8 2 7 3 6 4 5

10K_8P4R_5%

+3.3V_ALW_PCH

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

3

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

2

Title

Size Document Number Rev

Date: Sheet of

SKYLAKE PCH-H (2/9)

LA-C551P

1

20 74Tuesday, August 18, 2015

1.0

5

D D

4

3

2

1

1 2

1M_0402_1%

RH152 0_0402_5%@

SPT-H_PCH

RH153

1 2

CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P

CLKOUT_CPUPCIBCLK_N

CLKOUT_CPUPCIBCLK_P

CLKOUT_PCIE_N0 CLKOUT_PCIE_P0

CLKOUT_PCIE_N1 CLKOUT_PCIE_P1

CLKOUT_PCIE_N2 CLKOUT_PCIE_P2

CLKOUT_PCIE_N3 CLKOUT_PCIE_P3

CLKOUT_PCIE_N4 CLKOUT_PCIE_P4

CLKOUT_PCIE_N5 CLKOUT_PCIE_P5

CLKOUT_PCIE_N6 CLKOUT_PCIE_P6

CLKOUT_PCIE_N7 CLKOUT_PCIE_P7

CLKOUT_PCIE_N8 CLKOUT_PCIE_P8

CLKOUT_PCIE_N9 CLKOUT_PCIE_P9

CLKOUT_PCIE_N10

CLKOUT_PCIE_P10

CLKOUT_PCIE_N11

CLKOUT_PCIE_P11

7 OF 12RE V = 1.3

3

4

YH2 24MHZ_12 PF_X3G024 000DC1H

1

2

XTAL24_O UT_R

PCH_XDP_ CLK_DN_R

L1

PCH_XDP_ CLK_DP_R

L2

PCH_CPU_P CIBCLK_D# PCH_CPU_P CIBCLK_R_D#

J1

PCH_CPU_P CIBCLK_D

J2

CLK_PEG _N0

N7

CLK_PEG _P0

N8

CLK_PCIE _N1

L7

CLK_PCIE _P1

L5

CLK_PCIE _N2

D3

CLK_PCIE _P2

F2

CLK_PCIE _N3

E5

CLK_PCIE _P3

G4

CLK_PCIE _N4

D5

CLK_PCIE _P4

E6

CLK_PCIE _N5

D8

CLK_PCIE _P5

D7

CLK_PCIE _N6

R8

CLK_PCIE _P6

R7

CLK_PCIE _N7

U5

CLK_PCIE _P7

U7

CLK_PCIE _N8

W10

CLK_PCIE _P8

W11

N3 N2

P3 P2

R3 R4

CH13

1 2

15P_040 2_50V8J

CH14

1 2

15P_040 2_50V8J

1 2 1 2

RH154 0_0402_5%@

1 2

RH155 0_0402_5%@

1 2

RH168 0_0402_5%@ RH167 0_0402_5%@

CLK_PEG _N0 <1 8> CLK_PEG _P0 <18>

CLK_PCIE _N1 <44> CLK_PCIE _P1 <44>

CLK_PCIE _N2 <38> CLK_PCIE _P2 <38>

CLK_PCIE _N3 <35> CLK_PCIE _P3 <35>

CLK_PCIE _N4 <44> CLK_PCIE _P4 <44>

CLK_PCIE _N5 <41> CLK_PCIE _P5 <41>

CLK_PCIE _N6 <38> CLK_PCIE _P6 <38>

CLK_PCIE _N7 <39> CLK_PCIE _P7 <39>

CLK_PCIE _N8 <39> CLK_PCIE _P8 <39>

PCH_XDP_ CLK_DN PCH_XDP_ CLK_DP

PCH_CPU_P CIBCLK_R_D

MXM

Card reader

M.2 Slot2 WWAN

LAN

TBT

HDD

M.2 Slot1 WLAN

M.2 Slot3 SSD2

M.2 Slot4 SSD3

3.3V_RUN_ GFX_ON<45 ,49>

PCH_XDP_ CLK_DN < 7> PCH_XDP_ CLK_DP <7> PCH_CPU_P CIBCLK_R_D# <7> PCH_CPU_P CIBCLK_R_D <7>

+3.3V_AL W_PCH

10K_0402_5%

RH128

1 2

CLKREQ_P EG#0

13

D

2

QH3

G

DMN65D8LW -7_SOT323-3

S

UH1G

AR17

GPP_A16/CLKOUT_48

G1

CLKOUT_CPUNSSC_P

F1

CLKOUT_CPUNSSC_N

G2

CLKOUT_CPUBCLK_P

H2

CLKOUT_CPUBCLK_N

A5

XTAL24_OUT

A6

XTAL24_IN

E1

XCLK_BIASREF

BC9

RTCX1

BD10

RTCX2

BC24

GPP_B5/SRCCLKREQ0#

AW24

GPP_B6/SRCCLKREQ1#

AT24

GPP_B7/SRCCLKREQ2#

BD25

GPP_B8/SRCCLKREQ3#

BB24

GPP_B9/SRCCLKREQ4#

BE25

GPP_B10/SRCCLKREQ5#

AT33

GPP_H0/SRCCLKREQ6#

AR31

GPP_H1/SRCCLKREQ7#

BD32

GPP_H2/SRCCLKREQ8#

BC32

GPP_H3/SRCCLKREQ9#

BB31

GPP_H4/SRCCLKREQ10#

BC33

GPP_H5/SRCCLKREQ11#

BA33

GPP_H6/SRCCLKREQ12#

AW33

GPP_H7/SRCCLKREQ13#

BB33

GPP_H8/SRCCLKREQ14#

BD33

GPP_H9/SRCCLKREQ15#

R13

CLKOUT_PCIE_N15

R11

CLKOUT_PCIE_P15

P1

CLKOUT_PCIE_N14

R2

CLKOUT_PCIE_P14

W7

CLKOUT_PCIE_N13

Y5

CLKOUT_PCIE_P13

U2

CLKOUT_PCIE_N12

U3

CLKOUT_PCIE_P12

SKL-H-PCH_B GA837

XTAL24_IN_R

XTAL24_OUT_R1

CLKREQ_P CIE#1<44>

CLKREQ_P CIE#2<38>

CLKREQ_P CIE#3<35>

CLKREQ_P CIE#4<44>

CLKREQ_P CIE#5<41>

CLKREQ_P CIE#6<38>

CLKREQ_P CIE#7<39>

CLKREQ_P CIE#8<39>

CH4

1 2

CH5

1 2

CPU_24MHZ_ R_D CPU_24MHZ_ R_D#

PCH_CPU_B CLK_R_D PCH_CPU_B CLK_R_D#

RH124 10K_040 2_5%

+3.3V_RUN

RH125 10K_040 2_5%

+3.3V_RUN

RH126 10K_040 2_5%

+3.3V_RUN

RH127 10K_040 2_5%

+3.3V_RUN

RH131 10K_040 2_5%

+3.3V_RUN

RH132 10K_040 2_5%

+3.3V_RUN

RH133 10K_040 2_5%

+3.3V_RUN

RH332 10K_040 2_5%

+3.3V_RUN

PCH_RTCX1_R

12

YH1

32.768K HZ_12.5PF_9 H03200042

RH43 0_0402_5%@

CPU_24MHZ_ R_D<7> CPU_24MHZ_ R_D#<7>

PCH_CPU_B CLK_R_D<7> PCH_CPU_B CLK_R_D#<7>

MXM

Card reader

C C

B B

M.2 Slot2 WWAN

M.2 Slot1 WLAN

M.2 Slot3 SSD1

M.2 Slot4 SSD2

LAN

TBT

HDD

18P_040 2_50V8J

+1.0V_CLK 5

1 2

RH169 0_0402_5%@ RH170 0_0402_5%@

RH161 0_0402_5%@ RH166 0_0402_5%@

12

1 2 1 2

1 2

RH171 2 .7K_0402_ 1%

CLKREQ_P EG#0

CLKREQ_P CIE#1

CLKREQ_P CIE#2

CLKREQ_P CIE#3

CLKREQ_P CIE#4

CLKREQ_P CIE#5

CLKREQ_P CIE#6

CLKREQ_P CIE#7

CLKREQ_P CIE#8

PCH_RTCX1

12

RH44 10M_040 2_5%

PCH_RTCX2

PCH_CPU_NS SC_CLK_D PCH_CPU_NS SC_CLK_D#

PCH_CPU_B CLK_D PCH_CPU_B CLK_D#

XTAL24_OUT_R1 XTAL24_IN_R

XCLK_RBI AS

PCH_RTCX1 PCH_RTCX2

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Size Document Nu mber Rev

Date: Sheet of

Compal Electronics, Inc.

SKYLAKE PCH-H (3/9)

LA-C551P

21 74Tuesday, Au gust 18, 20 15

1

1.0

5

D D

C C

+3.3V_AL W_PCH

PCH_SPI_ D3

11/6 MOW(BC)

RH335 1K _0402_5%@

RH334 1K_0 402_5%@

1 2

SIO_EXT_S MI#

12

RH31010K_ 0402_5%

+3.3V_SP I

RH180 0_0402_5%@

1 2

MEDIACARD_IRQ#<44>

PCH_SPI_CLK<37>

PCH_SPI_CS#2<37>

FFS_INT2<41> TPM_PIRQ#<37>

PCH_SPI_D2_XDP<7>

PCH_SPI_ D2_XDP

Intel required for pre-ES1/ES2 sample

+3.3V_SP I

PCH_SPI_ D2_0_R

1 2

R3664 1K_0402_5%

B B

A A

5

R3668 1K_0402_5%

+3.3V_SP I

PCH_SPI_ D3_0_R

1 2

PCH_SPI_ CS#0_R1 PCH_SPI_ CS#0_R2 PCH_SPI_ D1_R1 PCH_SPI_ D1_0_R

PCH_SPI_ D2_1_R

1 2

R3665 1K_0402_5%@

R3666 1K_0402_5%@

PCH_SPI_ CS#1_R1 PCH_SPI_ CS#1_R2

PCH_SPI_ D2_R1

1 2

PCH_SPI_ CLK_1_R

PCH_SPI_ D3_1_R

R936 0 _0402_5%@ R895 3 3_0402_5 %@ R3667 33_0402 _5%@

4

PME#

T178PA D~D @

T59PAD~D @ T60PAD~D @ T61PAD~D @ T58PAD~D @

T63PAD~D @ T62PAD~D @

PCH_SPI_ D0

1 2 1 2 1 2

11/17 RF request

PCH_SPI_ D1 PCH_SPI_ CS#0 PCH_SPI_ CLK PCH_SPI_ CS#1

PCH_SPI_ D2 PCH_SPI_ D3 PCH_SPI_ CS#2

MEDIACARD_ IRQ# FFS_INT2 TPM_PIRQ#

12

@EMC@

33_0402 _5%

1

@EMC@

27P_040 2_50V8J

2

4

PCH_SPI_D1<37>

R7 0_0 402_5%@ R8 33_ 0402_5% R9 33_ 0402_5%

PCH_SPI_ D2_0_RPCH_SPI_ D2_R1

PCH_SPI_ D1_1_RPCH_SPI_ D1_R1 PCH_SPI_ D2_1_R

R3755

C1466

BD17

AG15 AG14

AF17 AE17

AR19 AN17

BB29

BE30 BD31 BC31 AW31

BC29 BD30

AT31

AN36

AL39 AN41 AN38 AH43 AG44

SKL-H-PCH_B GA837

PCH_PLTRST#

UH1A

GPP_A11/PME#

RSVD RSVD RSVD RSVD

TP2 TP1

SPI0_MOSI SPI0_MISO SPI0_CS0# SPI0_CLK SPI0_CS1#

SPI0_IO2 SPI0_IO3 SPI0_CS2#

GPP_D1/SPI1_CLK GPP_D0/SPI1_CS# GPP_D3/SPI1_MOSI GPP_D2/SPI1_MISO GPP_D22/SPI1_IO3 GPP_D21/SPI1_IO2

200 MIL SO8

16MB Flash ROM

U52

1

/CS

2

DO(IO1)

3

/WP(IO2) GND4DI(IO0)

W25Q1 28FVSIQ_SO 8

200 MIL SO8

4MB Flash ROM

@

1

/CS

2

DO/IO1

3

/WP/IO2

4

GND

W25Q3 2FVSSIQ_SO 8

+3.3V_AL W_PCH +3.3V_RUN

12

5

1

IN1

2

IN2

3

SPT-H_PCH

GPP_G15/GSXSRESET#

GPP_H18/SML4ALERT#

GPP_H15/SML3ALERT#

GPP_H12/SML2ALERT#

REV = 1.3 1 O F 12 ?

8

VCC

7

/HOLD(IO3)

6

CLK

5

CIS LINK OK

U53

/HOLD/IO3

DI/IO0

8

VCC

7 6

CLK

5

CIS LINK OK

3

12

RH349 0_0402_ 5%

+U638_PW R

P

O

G

GPP_G12/GSXDOUT

GPP_G13/GSXSLOAD

GPP_H17/SML4DATA

GPP_H14/SML3DATA

GPP_H11/SML2DATA

RH350

@

0_0402_ 5%

U638 SN74AHC1 G08DCKR_SC7 0-5

PCH_PLTRST#_ EC

4

GPP_B13/PLTRST#

GPP_G16/GSXCLK

GPP_G14/GSXDIN

GPP_E3/CPU_GP0 GPP_E7/CPU_GP1 GPP_B3/CPU_GP2 GPP_B4/CPU_GP3

GPP_H16/SML4CLK

GPP_H13/SML3CLK

GPP_H10/SML2CLK

+3.3V_SP I

PCH_SPI_ CLK_0_R PCH_SPI_ D0_0_R PCH_SPI_ D0_R1

+3.3V_SP I

PCH_SPI_ D3_1_R

PCH_SPI_ D0_1_R

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

INTRUDER#

C746

1 2

0.1U_040 2_25V6K

C1216

@

1 2

0.1U_040 2_25V6K

3

12

RH196

@

100K_04 02_5%

BB27

TBT_FORCE_PW R

P43

RTD3_CIO_PW R_EN

R39 R36 R42 R41

SIO_EXT_S MI#

AF41 AE44

TOUCHPAD_INTR#

BC23

GPP_B4

BD24

BC36 BE34 BD39 BB36 BA35 BC35 BD35 AW35 BD34

PCH_INTRUDER_ HDR#

BE11

1 2

R3669 33_040 2_5%

1 2

R899 33_0402_5 %EMC@

1 2

R901 33_0402_5 %

1 2

R3670 33_0402 _5%@

1 2

R897 3 3_0402_5 %@EMC@

1 2

R900 3 3_0402_5 %@

1 2 1 2

RH197 0_0402_5%@ RH212 0_0402_5%@

1 2

RH346 0_0402_5%@

PCH_PLTRST#

TBT_FORCE_PWR <44> RTD3_CIO_PWR_EN <44,45>

SIO_EXT_SMI# <46>PCH_SPI_D0<7,37>

TOUCHPAD_INTR# <48>

+RTC_CELL

PCH_SPI_ D3_R1 PCH_SPI_ CLK_R1PCH_SPI_CLK_ 1_R PCH_SPI_ D0_R1

PLTRST_USH#_EC<45>

12

RH198 330K_04 02_5%

PCH_SPI_ D3_R1PCH_SPI_ D3_0_R PCH_SPI_ CLK_R1

+3.3V_SP I

2

PCH_PLTRST#_EC <38,39,45,46> PLTRST_TBT# <44> PLTRST_HDD# <41>

PLTRST_TPM#

1 2

RH187 0_0402_ 5%@

1 2

RH194 0_0402_ 5%@

1 2

RH195 0_0402_ 5%@

1 2

RH211 0_0402_ 5%@

1 2

RH210 0_0402_ 5%@

1 2

RH359 0_0402_ 5%@

+3.3V_AL W_PCH

+3.3V_M

2

1

GPP_B4

1 2

RH336 100K_0 402_5%

11/11 BC/PC for verb table

11/11 BC/PC for verb table11/11 BC/PC for verb table detect

detect

PCH_SPI_ CS#1

PCH_SPI_ D0

PCH_SPI_ D1

PCH_SPI_ CLK

PCH_SPI_ CS#0

PCH_SPI_ D2

PCH_SPI_ D3

detectdetect

12

@

RE1 33_0402 _5%

1

@

CE1 27P_040 2_50V8J

2

JSPI1

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20

1 2 2 3 4 4 5 6 6 7 8 8 9 10 10 11 12 12 13 14 14 15 16 16 17 18 18 19 20 20

21

G1

22

G2

23

G3

24

G4

ACES_50 559-02001-0 01

CONN@

CIS link OK

CIS link OKCIS link OK

PLTRST_TPM# <37> PLTRST_LAN# <35> PLTRST_GPU# <18> PLTRST_MMI# <44> PLTRST_USH# <37>

PCH_SPI_ CS#1_R1

12

RH1770_040 2_5%

PCH_SPI_ D0_R1

12

RH1780_040 2_5%

PCH_SPI_ D1_R1

12

RH1790_040 2_5%

PCH_SPI_ CLK_R1

12

RH1810_040 2_5%

PCH_SPI_ CS#0_R1

12

RH1820_040 2_5%

PCH_SPI_ D2_R1

12

RH1830_040 2_5%

PCH_SPI_ D3_R1

12

RH1840_040 2_5%

12

RH343 0 _0402_5%

12

RH344 0 _0402_5%@

1 2

RH185 0_0402_5%@

PCH_SPI_ CLK_0_R

+3.3V_SP I_PWR

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

Size Document Nu mber Rev

Date: Sheet of

Compal Electronics, Inc.

SKYLAKE PCH-H (4/9)

LA-C551P

1

+3.3V_RUN

22 74Tuesday, Au gust 18, 20 15

1.0

5

+3.3V_ALW_PCH

1 2

RH56 1K_0402_5%

1 2

RH65 1K_0402_5%

1 2

RH67 499_0402_1%

1 2

RH77 499_0402_1%

1 2

D D

RH80 1K_0402_5%

1 2

RH81 1K_0402_5%

+3.3V_RUN +3.3V_ALW_PCH

RH347

@

150K_0402_5%

1 2

GPP_B23 GPP_B23_Q

C C

+3.3V_PGPPBCH

1 2

RH61 4.7K_0402_5%

TLS CONFIDENTIALITY HIGH LOW(DEFAULT)

+3.3V_ALW_PCH

1 2

RH78 4.7K_0402_5%@

EC interface HIGH LOW(DEFAULT)

B B

+3.3V_ALW_PCH

1 2

RH86 4.7K_0402_5%@

TOP SWAP STRAP HIGH LOW(DEFAULT)

Service Mode Switch: Add a switch to ME_FWP signal to unlock the ME region and allow the entire region of the SPI flash to be updated using FPT.

+3.3V_ALW_PCH

12

R3728

@

1K_0402_5%

A A

ME_FWP PCH has internal 20K PD. (suspend power rail)

FLASH DESCRIPTOR SECURITY OVERRIDE

LOW = ENABLE (DEFAULT) -->Pin1 & Pin3 short HIGH = DISABLE (ME can update) -->Pin2 & Pin3 short

MEM_SMBCLK

MEM_SMBDATA

SML0_SMBCLK

SML0_SMBDATA

SML1_SMBCLK

SML1_SMBDATA

RH353

0_0402_5%

S

G

SIO_SLP_A#<23,37,46,49>

ME_FWP_EC

ME_FWP_EC<45>

2

EXI BOOT STALL BYPASS

HIGH LOW(DEFAULT)

WEAK INTERNAL PD

PCH_SMB_ALERT#

ENABLE DISABLE

GPP_C5

ESPI LPC

SPKR

ENABLE DISABLE

RC301 0_0402_5%

PT,ST pop R3728 and SW2; MP pop RC301

ME_FWP

5

12

D

1 2

13

QH5

@

DMN65D8LW-7_SOT323-3

ENABLED DIABLED

ME_FWP

12

SW2

@

1

A

2

B

3

C

4

G1

5

G2

SS3-CMFTQR9_3P

RH329 150K_0402_5%

AUD_AZACPU_SDO<9> AUD_AZACPU_SDI_R<9> AUD_AZACPU_SCLK< 9>

EMC@

CH268 22P_0402_50V8J

PCH_DPWROK<46>

SML0_SMBCLK<35> SML0_SMBDATA<35>

SML1_SMBCLK<46> SML1_SMBDATA<46>

1 2

HDA_BIT_CLK_R<44>

HDA_SDOUT_R<44>

AUD_AZACPU_SDI_R

4

Left Side

WWAN

EDOCK

Right Side JUSB1

Right Side JUSB2

Right Side JUSB3

11/17 RF request

1 2 1 2

RH46 33_0402_5%

HDA_RST#_R<44>

RH50 33_0402_5%

HDA_SDIN0< 44>

ME_FWP

HDA_SYNC_R<44>

+RTC_CELL

PCH_DPWROK

MEM_SMBCLK MEM_SMBDATA

SML0_SMBCLK SML0_SMBDATA

SML1_SMBCLK SML1_SMBDATA

1 2 1 2

RH328 1K_0402_ 5%

1 2

RH45 33_0402_5% RH48 33_0402_5%

1 2

RH39 30_0402_5%

1 2

RH38 30_0402_5%

DGPU_PWROK<18,45>

1 2 1 2

RH200 20K_0402_5% RH201 20K_0402_5%

PCH_PWROK<61,64>

PCH_RSMRST#_R<7>

RH215

RH215RH215

POP

NO Support Deep sleep

DE-POP

Support Deep sleep

PCH_DPWROK PCH_RSMRST#_R

1 2

RH215 0_0402_5%

@

1M_0402_5%

0.01U_0402_16V7K

12

1

RH308

CH266

2

4

USB3_PTX_DRX_N1<44> USB3_PTX_DRX_P1<44>

USB3_PRX_DTX_N1<44>

USB3_PRX_DTX_P1<44> USB3_PTX_DRX_N2<38> USB3_PTX_DRX_P2<38>

USB3_PRX_DTX_N2<38>

USB3_PRX_DTX_P2<38>

USB3_PTX_DRX_N6<43> USB3_PTX_DRX_P6<43>

USB3_PRX_DTX_N6<43>

USB3_PRX_DTX_P6<43> USB3_PTX_DRX_N5<44> USB3_PTX_DRX_P5<44>

USB3_PRX_DTX_N5<44>

USB3_PRX_DTX_P5<44>

USB3_PTX_DRX_P3<44> USB3_PTX_DRX_N3<44>

USB3_PRX_DTX_P3<44>

USB3_PRX_DTX_N3<44>

USB3_PTX_DRX_P4<44> USB3_PTX_DRX_N4<44>

USB3_PRX_DTX_P4<44>

USB3_PRX_DTX_N4<44>

HDA_BIT_CLK HDA_RST# HDA_SDIN0

HDA_SDOUT HDA_SYNC

AUD_AZACPU_SDO_RAUD_AZACPU_SDO

AUD_AZACPU_SCLK_RAUD_AZACPU_SCLK

DGPU_PWROK

PCH_RTCRST# SRTCRST#

PCH_PWROK PCH_RSMRST#_R

PCH_SMB_ALERT#

GPP_C5

GPP_B23

USB3_PTX_DRX_N1 USB3_PTX_DRX_P1 USB3_PRX_DTX_N1 USB3_PRX_DTX_P1 USB3_PTX_DRX_N2 USB3_PTX_DRX_P2 USB3_PRX_DTX_N2 USB3_PRX_DTX_P2

USB3_PTX_DRX_N6 USB3_PTX_DRX_P6 USB3_PRX_DTX_N6 USB3_PRX_DTX_P6 USB3_PTX_DRX_N5 USB3_PTX_DRX_P5 USB3_PRX_DTX_N5 USB3_PRX_DTX_P5

USB3_PTX_DRX_P3 USB3_PTX_DRX_N3 USB3_PRX_DTX_P3 USB3_PRX_DTX_N3

USB3_PTX_DRX_P4 USB3_PTX_DRX_N4 USB3_PRX_DTX_P4 USB3_PRX_DTX_N4

BA9

HDA_BCLK

BD8

HDA_RST#

BE7

HDA_SDI0

BC8

HDA_SDI1

BB7

HDA_SDO

BD9

HDA_SYNC

BD1

RSVD_BD1

BE2

RSVD_BE2

AM1

DISPA_SDO

AN2

DISPA_SDI

AM2

DISPA_BCLK

AL42

GPP_D8/I2S0_SCLK

AN42

GPP_D7/I2S0_RXD

AM43

GPP_D6/I2S0_TXD

AJ33

GPP_D5/I2S0_SFRM

AH44

GPP_D20/DMIC_DATA0

AJ35

GPP_D19/DMIC_CLK0

AJ38

GPP_D18/DMIC_DATA1

AJ42

GPP_D17/DMIC_CLK1

BC10

RTCRST#

BB10

SRTCRST#

AW11

PCH_PWROK

BA11

RSMRST#

AV11

DSW_PWROK

BB41

GPP_C2/SMBALERT#

AW44

GPP_C0/SMBCLK

BB43

GPP_C1/SMBDATA

BA40

GPP_C5/SML0ALERT#

AY44

GPP_C3/SML0CLK

BB39

GPP_C4/SML0DATA

AT27

GPP_B23/SML1ALERT#/PCHHOT#

AW42

GPP_C6/SML1CLK

AW45

GPP_C7/SML1DATA

SKL-H-PCH_BGA837

MEM_SMBCLK

MEM_SMBDATA

1 2

CH41 1U_0402_6.3VAK

1 2

CH40 1U_0402_6.3VAK

PCH_RTCRST#<37>

1

CMOS1 SHORT PADS~D@

UH1D

3

UH1F

C11

USB3_1_TXN

B11

USB3_1_TXP

B7

USB3_1_RXN

A7

USB3_1_RXP

B12

USB3_2_TXN/SSIC_1_TXN

A12

USB3_2_TXP/SSIC_1_TXP

C8

USB3_2_RXN/SSIC_1_RXN

B8

USB3_2_RXP/SSIC_1_RXP

B15

USB3_6_TXN

C15

USB3_6_TXP

K15

USB3_6_RXN

K13

USB3_6_RXP

B14

USB3_5_TXN

C14

USB3_5_TXP

G13

USB3_5_RXN

H13

USB3_5_RXP

D13

USB3_3_TXP/SSIC_2_TXP

C13

USB3_3_TXN/SSIC_2_TXN

A9

USB3_3_RXP/SSIC_2_RXP

B10

USB3_3_RXN/SSIC_2_RXN

B13

USB3_4_TXP

A14

USB3_4_TXN

G11

USB3_4_RXP

E11

USB3_4_RXN

SKL-H-PCH_BGA837

AUDIO

+3.3V_RUN

6 1

DMN66D0LDW-7_SOT363-6

354

QH4B

DMN66D0LDW-7_SOT363-6

SRTCRST#

PCH_RTCRST#

2

3

2

SPT-H_PCH

LPC/eSPI

USB

SPT-H_PCH

GPP_A12/BMBUSY#/ISH_GP6/SX_EXIT_HOLDOFF#

SMBUS

2

QH4A

GPP_A1/LAD0/ESPI_IO0 GPP_A2/LAD1/ESPI_IO1 GPP_A3/LAD2/ESPI_IO2 GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS0#

GPP_A6/SERIRQ/ESPI_CS1#

GPP_A7/PIRQA#/ESPI_ALERT0#

GPP_A0/RCIN#/ESPI_ALERT1#

GPP_A14/SUS_STAT#/ESPI_RESET#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

GPP_A10/CLKOUT_LPC1

GPP_G19/SMI# GPP_G18/NMI#

GPP_E6/DEVSLP2 GPP_E5/DEVSLP1 GPP_E4/DEVSLP0

SATA

GPP_A13/SUSWARN#/SUSPWRDNACK

JTAG

GPP_F9/DEVSLP7 GPP_F8/DEVSLP6 GPP_F7/DEVSLP5 GPP_F6/DEVSLP4 GPP_F5/DEVSLP3

GPP_A8/CLKRUN#

GPD11/LANPHYPC

GPD9/SLP_WLAN#

DRAM_RESET#

GPP_B2/VRALERT#

GPP_G17/ADR_COMPLETE

GPP_B11

SYS_PWROK

GPD6/SLP_A#

SLP_LAN#

GPP_B12/SLP_S0#

GPD4/SLP_S3# GPD5/SLP_S4#

GPD10/SLP_S5#

GPD8/SUSCLK

GPD0/BATLOW#

GPP_A15/SUSACK#

GPD2/LAN_WAKE#

GPD1/ACPRESENT

SLP_SUS#

GPD3/PWRBTN#

SYS_RESET#

GPP_B14/SPKR

PROCPWRGD

ITP_PMODE

JTAG_TMS JTAG_TDO

JTAG_TDI

JTAG_TCK

DDR_XDP_WAN_SMBCLK <7,14,15,16,17,41>

DDR_XDP_WAN_SMBDAT <7,14,15,16,17,41>

6 OF 12REV = 1.3

GPP_B1 GPP_B0

WAKE#

JTAGX

4 OF 12REV = 1.3

AT22 AV22 AT19 BD16

BE16 BA17 AW17 AT17 BC18

BC17 AV19

M45 N43

AE45 AG43 AG42 AB39 AB36 AB43 AB42 AB41

BB17 AW22

AR15

AV13

BC14 BD23 AL27 AR27 N44 AN24 AY1

BC13 BC15 AV15 BC26 AW15 BD15 BA13

AN15 BD13 BB19 BD19

BD11 BB15 BB13 AT13 AW1 BD26 AM3

AT2 AR3 AR2 AP1 AP2 AN3

ITP_PMODE_CPU PCH_JTAGX PCH_JTAG_TMS PCH_JTAG_TDO PCH_JTAG_TDI PCH_JTAG_TCK

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3

LPC_FRAME# IRQ_SERIRQ HDD_FALL_INT SIO_RCIN# GPP_A14

PCI_CLK_LPC0 PCI_CLK_LPC1

CLKRUN#

PM_LANPHY_ENABLE

SIO_SLP_WLAN#

DDR4_DRAMRST#_PCH VRALERT#

RESET_OUT#

PCH_PCIE_WAKE# SIO_SLP_A# SIO_SLP_LAN# SIO_SLP_S0# SIO_SLP_S3# SIO_SLP_S4# SIO_SLP_S5#

SUSCLK PCH_BATLOW#

SUSACK# ME_SUS_PWR_ACK

LAN_WAKE# AC_PRESENT_R SIO_SLP_SUS#_R SIO_PWRBTN# SYS_RESET# SPKR H_PWRGD

LPC_AD0 <45,46> LPC_AD1 <45,46> LPC_AD2 <45,46> LPC_AD3 <45,46>

LPC_FRAME# <45,46> IRQ_SERIRQ <45,46> HDD_FALL_INT <41> SIO_RCIN# <46>

RH96 22_0402_5%E MC@ RH97 22_0402_5%E MC@ RH99 22_0402_5%E MC@ RH98 22_0402_5%E MC@

CLKRUN# <45,46>

PM_LANPHY_ENABLE <35>

SIO_SLP_WLAN# <40,45>

DDR4_DRAMRST#_PCH <14>

RESET_OUT# <7,46>

PCH_PCIE_WAKE# <46> SIO_SLP_A# <23,37 ,46,49> SIO_SLP_LAN# <40,46> SIO_SLP_S0# <11,3 7> SIO_SLP_S3# <7,11 ,37,44,46> SIO_SLP_S4# <11,3 7,46,52,54> SIO_SLP_S5# <37,4 4,46>

SUSCLK <38,39>

SUSACK# <46>

ME_SUS_PWR_ACK <46>

LAN_WAKE# < 35,46>

SIO_SLP_SUS#_R <46>

SIO_PWRBTN# <7,46> SYS_RESET# <20,37> SPKR <44> H_PWRGD <7>

PAD~D

ITP_PMODE_CPU <7> PCH_JTAGX <7>

PCH_JTAG_TMS < 7> PCH_JTAG_TDO <7>

PCH_JTAG_TDI <7> PCH_JTAG_TCK <7>

PAD~D

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

2

1 2 1 2 1 2 1 2

@

T192

@

T182

@

T183

@

T186

@

T187

@

T188

AC_PRESENT<46>

1

CLK_PCI_5048 <45> CLK_PCI_MEC <46> CLK_PCI_LPDEBUG <46> CLK_PCI_DOCK <43>

CLK_PCI_5048

CLK_PCI_MEC

CLK_PCI_LPDEBUG

CLK_PCI_DOCK

GPP_A14

VRALERT#

SIO_SLP_LAN#

ME_SUS_PWR_ACK

PM_LANPHY_ENABLE

LAN_WAKE#

SIO_RCIN#

CLKRUN#

RESET_OUT#

10/23

ME_SUS_PWR_ACK

Title

Size Document Number Rev

Date: Sheet of

IRQ_SERIRQ

PCH_JTAG_TCK

SUSCLK

PCH_JTAG_TMS

PCH_JTAG_TDI

PCH_JTAG_TDO

Compal Electronics, Inc.

1 2

CH42 12P_0402_50V8JEMC@

1 2

CH49 12P_0402_50V8JEMC@

1 2

CH50 12P_0402_50V8JEMC@

1 2

CH51 12P_0402_50V8JEMC@

1 2

RH95 10K_0402_5%@

1 2

RH203 10K_0402_5%@

1 2

RH204 10K_0402_5%@

1 2

RH327 10K_0402_5%

1 2

PCH_PCIE_WAKE#

PCH_BATLOW#

RH338 100K_0402_5%

1 2

RH92 1K_0402_5%

1 2

RH93 10K_0402_5%

1 2

RH94 8.2K_0402_5%

1 2

RH213 10K_0402_5%

1 2

RH202 8.2K_0402_5%

1 2

RH199 100K_0402_5%

1 2

RH340 10K_0402_5%

12

RH840_04 02_5% @

12

RH850_0402 _5% @

SKYLAKE PCH-H (5/9)

LA-C551P

1

12

SUSACK# AC_PRESENT_RAC_PRESENT

12

RH31251_0402_5%

RH31451_0402_5%

RH31551_0402_5%

23 74Tuesday, August 18, 2015

+3.3V_ALW_PCH

+3.3V_DSW

+3.3V_RUN

RH31351_0402_5% @XDP@

RH831K_0402_5% @

+1.0V_VCCSTG

1.0

5

+3.3V_RUN

GPP_C8

1 2

RH207 100K_0402_5%

D D

C C

B B

RH71 10K_0402_5%

RH79 10K_0402_5%

RH331 4.7K_0402_5%@

RH339 10K_0402_5%

+3.3V_ALW_PCH

RH309 10K_0402_5%

RH345 10K_0402_5%@

RH351 49.9K_0402_1%

RH352 49.9K_0402_1%

+3.3V_ALW_PCH

12

@

8.2K_0402_5%

BBS_BIT0

BOOT BIOS Destination(Bit 10)

HIGH LOW(DEFAULT)

1 2

RH311

SBIOS_TX

3.3V_TP_EN

NRB_BIT

SIO_EXT_SCI#

SIO_EXT_WAKE#

GPU_EVENT#

LPSS_UART2_RXD

LPC SPI

SIO_EXT_SCI#<46>

11/14

GC6_FB_EN<18>

GPU_EVENT#< 18>

SBIOS_TX<46>

HOST_SD_WP#<44>

8/20

LCD_CBL_DET#<30>

SIO_EXT_WAKE#<46>

I2C_1_SCL<48> I2C_1_SDA<48>

PCH_AAC_SMBCLK<28>

PCH_AAC_SMBDAT<28>

PCH_DPB_HPD<31> PCH_DPC_HPD<34> PCH_DPD_HPD<33>

BBS_BIT0

SIO_EXT_SCI#

3.3V_TP_EN

NRB_BIT

GC6_FB_EN GPU_EVENT#

SBIOS_TX GPP_C8 HOST_SD_WP#

LPSS_UART2_TXD LPSS_UART2_RXDLPSS_UART2_TXD

CPU_EDP_HPD<29>

LCD_CBL_DET#

SIO_EXT_WAKE#

I2C_1_SCL I2C_1_SDA

PCH_DPB_HPD PCH_DPC_HPD PCH_DPD_HPD

CPU_EDP_HPD

4

UH1K

AT29

GPP_B22 /GSPI1_MOS I

AR29

GPP_B21 /GSPI1_MIS O

AV29

GPP_B20 /GSPI1_CLK

BC27

GPP_B19 /GSPI1_CS#

BD28

GPP_B18 /GSPI0_MOS I

BD27

GPP_B17 /GSPI0_MIS O

AW27

GPP_B16 /GSPI0_CLK

AR24

GPP_B15 /GSPI0_CS#

AV44

GPP_C9/U ART0_TXD

BA41

GPP_C8/U ART0_RXD

AU44

GPP_C11 /UART0_CTS#

AV43

GPP_C10 /UART0_RTS#

AU41

GPP_C15 /UART1_CTS#/ISH_ UART1_CTS#

AT44

GPP_C14 /UART1_RTS#/ISH_ UART1_RTS#

AT43

GPP_C13 /UART1_TXD/ISH_UA RT1_TXD

AU43

GPP_C12 /UART1_RXD/ISH_ UART1_RXD

AN43

GPP_C23 /UART2_CTS#

AN44

GPP_C22 /UART2_RTS#

AR39

GPP_C21 /UART2_TXD

AR45

GPP_C20 /UART2_RXD

AR41

GPP_C19 /I2C1_SCL

AR44

GPP_C18 /I2C1_SDA

AR38

GPP_C17 /I2C0_SCL

AT42

GPP_C16 /I2C0_SDA

AM44

GPP_D4/I SH_I2C2_SDA /ISH_I2C3_S DA

AJ44

GPP_D23 /ISH_I2C2_S CL/ISH_I2C3_ SCL

SKL-H-PCH_BGA837

UH1E

AW4

GPP_I0/D DPB_HPD0

AY2

GPP_I1/D DPC_HPD1

AV4

GPP_I2/D DPD_HPD2

BA4

GPP_I3/D DPE_HPD3

BD7

GPP_I4/E DP_HPD

SKL-H-PCH_BGA837

SPT-H_PCH

GPP_D9 GPP_D10 GPP_D11 GPP_D12

GPP_D16 /ISH_UART0_CTS#

GPP_D14 /ISH_UART0_TXD/S ML0BCLK/I2C 2_SCL

GPP_D13 /ISH_UART0_RXD /SML0BDATA/I2 C2_SDA

SPT-H_PCH

GPP_D15 /ISH_UART0_RTS#

GPP_H20 /ISH_I2C0_S CL GPP_H19 /ISH_I2C0_S DA

GPP_H22 /ISH_I2C1_S CL GPP_H21 /ISH_I2C1_S DA

GPP_A23 /ISH_GP5 GPP_A22 /ISH_GP4 GPP_A21 /ISH_GP3 GPP_A20 /ISH_GP2 GPP_A19 /ISH_GP1 GPP_A18 /ISH_GP0 GPP_A17 /ISH_GP7

11 OF 12 REV = 1.3

GPP_F14 GPP_F23 GPP_F22

GPP_G23 GPP_G22 GPP_G21 GPP_G20

GPP_H23

5 OF 12R EV = 1.3

BB3 BD6 BA5 BC4 BE5 BE6

Y44 V44 W39

L43 L44 U35 R35 BD36

GPP_I7/D DPC_CTRLCLK

GPP_I8/D DPC_CTRLDATA

GPP_I5/D DPB_CTRLCLK

GPP_I6/D DPB_CTRLDATA

GPP_I9/D DPD_CTRLCLK

GPP_I10 /DDPD_CTRLDATA

3

AL44 AL36 AL35 AJ39

AJ43 AL43 AK44 AK45

BC38 BB38

BD38 BE39

BC22 BD18 BE21 BD22 BD21 BB22 BC19

PCH_DPC_CTRL_CLK PCH_DPC_CTRL_DATA PCH_DPB_CTRL_CLK PCH_DPB_CTRL_DATA PCH_DPD_CTRL_CLK PCH_DPD_CTRL_DATA

GPP_F23

DIMM_TYPE

DGPU_HOLD_RST#

GPP_D16

GPP_D14

IR_CAM_DET#

AUD_PWR_EN KB_DET#

CLKDET#

DGPU_HOLD_RST# <18>

IR_CAM_DET# <30>

T201 PAD~D@

KB_DET# <48>

CLKDET# <41>

PCH_DPC_CTRL_CLK <34> PCH_DPC_CTRL_DATA <34> PCH_DPB_CTRL_CLK <31> PCH_DPB_CTRL_DATA <31> PCH_DPD_CTRL_CLK <33> PCH_DPD_CTRL_DATA <33>

2

KB_DET#

8/21

GPP_D16

GPP_D14

LCD_CBL_DET#

PCH_DPC_CTRL_CLK PCH_DPC_CTRL_DATA PCH_DPB_CTRL_CLK PCH_DPB_CTRL_DATA PCH_DPD_CTRL_CLK PCH_DPD_CTRL_DATA

DIMM_TYPE

GPP_F23

LPSS_UART2_TXD LPSS_UART2_RXD

1

1 2

RC74 10K_0402_5%

1 2

RC75 10K_0402_5%

1 2

RC76 10K_0402_5%

1 2

RC79 10K_0402_5%

1 2 1 2

RH220 2.2K_0402_5%

1 2

RH221 2.2K_0402_5%

1 2

RH222 2.2K_0402_5%

1 2

RH223 2.2K_0402_5%

1 2

RH224 2.2K_0402_5% RH225 2.2K_0402_5%

1 2

RC329 10K_0402_5%

1 2

RH214 100K_0402_5%

+5V_ALW

CONN@

JUART1

1

2

3

4

5

GND

6

GND

ACES_50207-00471-P01

+3.3V_ALW_PCH

+3.3V_RUN

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

SKYLAKE PCH-H (6/9)

LA-C551P

24 74Tuesday, August 18, 2015

1

1.0

5

4

3

2

1

+1.0V_PRI M +1.0V_A LW_PCH

1 2

RH254 0_ 1206_5%

+1.0V_AL W_PCH +1.0 V_DSW

D D

RH255 0_ 0402_5%@

RH256 0_0402_5%@

RH257 0_0402_5%@

RH258 0_0402_5%@

RH259 0_0402_5%@

RH260 0_0402_5%@

RH286 0_0402_5%@

C C

RH287 0_0402_5%@

RH288 0_0402_5%@

RH289 0_0402_5%@

RH290 0_0402_5%@

+3.3V_AL W_PCH

B B

RH298 0_0402_5%@

RH299 0_0402_5%@

RH300 0_0402_5%@

RH306 0_ 0402_5%@

+3.3V_AL W

RH301 0_ 0603_5%@

+3.3V_RUN +3.3 V_RUN_ATS

RH302 0_0402_5%@

+3.3V_AL W_PCH

A A

RH303 0_0402_5%@

RH304 0_0402_5%@

RH305 0_0402_5%@

1 2

PJP8

2

JUMP_43X 79

1 2

112

0.0454A

+1.0V_CLK 1

0.0348A

+1.0V_CLK 3

0.0237A

+1.0V_CLK 4

0.0327A

+1.0V_CLK 2

0.205A

+1.0V_F24

0.0046A

+1.0V_DUS B

0.533A

+2.8V_FHV

0.0908A

+1.0V_DTS

0.0061A

+1.0V_MPH Y

2.10A

+1.0V_AMP HYPLL

0.0248A

+1.0V_AP LLEBB

0.095A

+3.3V_PRTCP RIM

0.0002A

+3.3V_PHV C

0.2875A

+3.3V_1. 8V_FUSE

0.0811A

+3.3V_DSW

0.0811A

0.403A

0.0066A

+3.3V_PG PPEF

0.14107A

+3.3V_PG PPBCH

0.27262A

+3.3V_PG PPG

0.1318A

5

+3.3V_AL W +3. 3V_PUSBDSW

1 2

RH276 0_ 0603_5%@

+3.3V_PRTC+RTC_CELL

0.0002A

1 2

RH297 0_0402_5%@

+3.3V_AL W_PCH +3.3 V_ALW_P CHRES

1 2

RH279 0_ 0603_5%@

+3.3V_1. 8V_GPPA+3.3V_AL W_PCHRES

0.0879A

1 2

RH291 0_0402_5%@

+1.8V_AL W_PCHRES

1 2

RH294 0_ 0402_5%@

+3.3V_AL W_PCHRES +3.3V_1.8V_ AZIO

0.075A

1 2

RH292 0_0402_5%@

+1.8V_AL W_PCHRES

1 2

RH295 0_ 0402_5%@

+3.3V_1. 8V_GPPD+3.3V_AL W_PCHRES

0.0395A

1 2

RH293 0_0402_5%@

+1.8V_AL W_PCHRES

1 2

RH296 0_ 0402_5%@

+1.8V_RUN_ EDRAM+1.8V_RUN

1 2

RH252 0_ 0603_5%@

RH253 0_ 0603_5%@

RH246 0_ 0603_5%

+3.3V_M

RH348 0_ 0603_5%@

+1.8V_AL W_PCHRES

RH250 0_ 0603_5%@

RH247 0_ 0603_5%@

1 2

+VCC_EDRAM _FUSEPRG

+3.3V_1. 8V_SPI+3.3V _ALW_PCHR ES

+1.8V_AL W

+1.0V_CLK 5

+1.0V_CLK 2

+1.0V_CLK 4

+1.0V_CLK 3

NO CAP

+1.0V_AA ZPLL

+3.3V_1. 8V_AZIO

+3.3V_PUS BDSW

4

+1.0V_PRI M

NO CAP

+1.0V_DSW

+1.0V_CLK 1

NO CAP

+1.0V_MPH Y

+1.0V_AMP HYPLL

+1.0V_AP LLEBB

+1.0V_DUS B

+1.0V_AUS B

NO CAP

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

NO CAP

UH1J

BD2

VSS

BD45

VSS

BD44

VSS

BE44

VSS

D45

VSS

A42

VSS

B45

VSS

B44

VSS

A4

VSS

A3

VSS

B2

VSS

A2

VSS

B1

VSS

BB1

VSS

BC1

VSS

A44

VSS

C1

RSVD

D1

RSVD

SKL-H-PCH_B GA837

3

UH1H

AA23

VCCPRIM_1P0

AA26

VCCPRIM_1P0

AA28

VCCPRIM_1P0

AC23

VCCPRIM_1P0

AC26

VCCPRIM_1P0

AC28

VCCPRIM_1P0

AE23

VCCPRIM_1P0

AE26

VCCPRIM_1P0

Y23

VCCPRIM_1P0

Y25

VCCPRIM_1P0

BA29

DCPDSW_1P0

N17

VCCCLK1

R19

VCCCLK3

U20

VCCCLK4

V17

VCCCLK2

R17

VCCCLK2

K2

VCCCLK5

K3

VCCCLK5

U21

VCCMPHY_1P0

U23

VCCMPHY_1P0

U25

VCCMPHY_1P0

U26

VCCMPHY_1P0

V26

VCCMPHY_1P0

A43

VCCMPHYPLL_1P0

B43

VCCMPHYPLL_1P0

C44

VCCPCIE3PLL_1P0

C45

VCCPCIE3PLL_1P0

V28

VCCAPLLEBB_1P0

AC17

VCCPRIM_1P0

AJ5

VCCUSB2PLL_1P0

AL5

VCCUSB2PLL_1P0

AN19

VCCHDAPLL_1P0

BA15

VCCHDA

W15

VCCDSW_3P3

SKL-H-PCH_B GA837

SPT-H_PCH

CPU_TRST#

PCH_TRIGOUT

PCH_TRIGIN

REV = 1.3 10 OF 12

1 2

RH42 30_04 02_5%

SPT-H_PCH

CORE

MPHY

USB

REV = 1.3 8 OF 12

AR22

RSVD

W13

RSVD

U13

RSVD

P31

RSVD

N31

RSVD

P27

RSVD

R27

RSVD

N29

RSVD

P29

RSVD

AN29

RSVD

R24

RSVD

P24

RSVD

AT3

PCH_XDP_ PREQ#

PREQ#

AT4

PCH_XDP_ PRDY#

PRDY#

AY5

CPU_XDP_ TRST#

AL2

PCH_2_CP U_TRIGGER_R

AK1

CPU_2_PC H_TRIGGER

PCH_2_CP U_TRIGGERPCH_2_CPU_TRIGGE R_R

+2.8V_FHV

+1.0V_DTS

+3.3V_DSW

+3.3V_1. 8V_GPPA

NO CAP

+3.3V_RUN_ ATS

+3.3V_1. 8V_GPPD

+3.3V_1. 8V_FUSE

+3.3V_PG PPBCH

+3.3V_PRTCP RIM

+1.0V_PRI M

+3.3V_1. 8V_SPI

NO CAP

+3.3V_PG PPEF

+3.3V_PRTC

+DCPRTC

+3.3V_PG PPG

0.1U_0402_25V6

1

CH68

2

+3.3V_PHV C

VCCGPIO

VCCRTCPRIM_3P3

PAD~D PAD~D PAD~D PAD~D PAD~D

PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D

AL22

VCCPRIM_1P0

BA24

VCCDSW_3P3

BA31

VCCPGPPA

BC42

VCCPGPPBCH

BD40

VCCPGPPBCH

AJ41

VCCPGPPEF

AL41

VCCPGPPEF

AD41

VCCPGPPG

AN5

VCCPRIM_3P3

AD15

VCCPRIM_1P0

AD13

VCCATS

BA20 BA22

VCCRTC

BA26

DCPRTC

AJ20

VCCPRIM_1P0

AJ21

VCCPRIM_1P0

AJ23

VCCPRIM_1P0

AJ25

VCCPRIM_1P0

BE41

VCCSPI

BE43

VCCSPI

BE42

VCCSPI

BC44

VCCPGPPD

BA45

VCCPGPPD

BC45

VCCPGPPD

BB45

VCCPGPPD

BD3

VCCPRIM_3P3

BE3

VCCPRIM_3P3

BE4

VCCPRIM_3P3

@

T66

@

T67

@

T68

@

T69

@

T70

@

T71

@

T72

@

T74

@

T73

@

T76

@

T75

@

T77

PCH_XDP_ PREQ# <7> PCH_XDP_ PRDY# <7> CPU_XDP_ TRST# <7>

CPU_2_PC H_TRIGGER <10>

PCH_2_CP U_TRIGGER <10>

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

Size Document Nu mber Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

SKYLAKE PCH-H (7/9)

LA-C551P

25 74Tuesday, Au gust 18, 20 15

1

1.0

5

+1.0V_AMPHYPLL

4

+3.3V_PUSBDSW

+1.0V_MPHY

3

+3.3V_PRTCPRIM

2

1

+3.3V_PGPPEF

+3.3V_PGPPBCH

+3.3V_PGPPG

1U_0402_6.3VAK

@

1

CH31

2

+3.3V_1.8V_AZIO

0.1U_0402_25V6

@

0.1U_0402_25V6

@

1

CH62

2

0.1U_0402_25V6

@

1

CH63

2

0.1U_0402_25V6

@

1

CH64

2

1

CH269

2

1U_0402_6.3VAK

1

CH267

2

D D

+1.0V_ALW_PCH +VCCA USB_VCCAAZPLL_1P0 +1.0V_AUSB

1 2

RH238 0_0603_5%

+1.0V_F24 +1.0V_CLK5

C C

B B

RH241 0_0603_5%@

1 2

+3.3V_PRTC

22U_0805_6.3VAM

@

1

CH44

2

22U_0805_6.3VAM

@

1

CH29

2

1U_0402_6.3VAK

@

1

CH33

2

22U_0805_6.3VAM

@

1

CH45

2

22U_0805_6.3VAM

@

1

CH46

2

0.1U_0402_25V6

@

1

CH65

2

1 2

RH239 0_0603_5%

1 2

RH240 0_0603_5%

1U_0402_6.3VAK

@

CH32

+1.0V_AAZPLL

1

2

+1.0V_DSW

1U_0402_6.3VAK

1

2

+3.3V_RUN_ATS

1U_0402_6.3VAK

1

2

+3.3V_PHVC

0.1U_0402_25V6

1

2

1U_0402_6.3VAK

22U_0603_6.3V6M

1

CH34

CH47

2

CH35

CH36

@

CH66

+1.0V_DUSB

1U_0402_6.3VAK

0.1U_0402_25V6

1

CH37

CH67

2

1U_0402_6.3VAK

1

CH38

2

CRB 0.7

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

SKYLAKE PCH-H (8/9)

LA-C551P

26 74Tuesday, August 18, 2015

1

1.0

5

D D

4

3

2

1

UH1I

SPT-H_PCH

AC18

VSS

AN4

VSS

AN10

VSS

BE14

VSS

BE18

VSS

BE23

VSS

BE28

VSS

BE32

VSS

BE37

VSS

BE40

VSS

BE9

VSS

C10

VSS

C2

VSS

C28

VSS

C37

C C

B B

A A

VSS

J7

VSS

K10

VSS

K27

VSS

K33

VSS

K36

VSS

K4

VSS

K42

VSS

K43

VSS

L12

VSS

L13

VSS

L15

VSS

L4

VSS

L41

VSS

L8

VSS

M35

VSS

M42

VSS

N10

VSS

N15

VSS

N19

VSS

N22

VSS

N24

VSS

N35

VSS

N36

VSS

N4

VSS

N41

VSS

N5

VSS

P17

VSS

P19

VSS

P22

VSS

P45

VSS

R10

VSS

R14

VSS

R22

VSS

R29

VSS

R33

VSS

R38

VSS

R5

VSS

T1

VSS

T2

VSS

T4

VSS

Y18

VSS

Y20

VSS

Y21

VSS

Y26

VSS

Y28

VSS

Y29

VSS

A18

VSS

A25

VSS

A32

VSS

A37

VSS

AA17

VSS

AA18

VSS

AA20

VSS

AA21

VSS

AA25

VSS

AA29

VSS

AA4

VSS

AA42

VSS

AB10

VSS

SKL-H-PCH_B GA837

AR5

VSS

AR7

VSS

U15

VSS

AL4

VSS

AE29

VSS

AE4

VSS

AE42

VSS

AF18

VSS

AF20

VSS

AF21

VSS

AF23

VSS

AF25

VSS

AF26

VSS

AF28

VSS

AF29

VSS

AG11

VSS

AG13

VSS

AG31

VSS

AG32

VSS

AG33

VSS

AG38

VSS

AG4

VSS

AH1

VSS

AH17

VSS

AH18

VSS

AH20

VSS

AH21

VSS

AH23

VSS

AH25

VSS

AH26

VSS

AH28

VSS

AH29

VSS

AH45

VSS

AJ10

VSS

AJ14

VSS

AJ15

VSS

AJ17

VSS

AJ18

VSS

AJ26

VSS

AJ28

VSS

AJ29

VSS

AJ31

VSS

AJ32

VSS

AJ36

VSS

AK4

VSS

AK42

VSS

AU7

VSS

AV17

VSS

AV24

VSS

AV27

VSS

AV31

VSS

AV33

VSS

AV6

VSS

AW13

VSS

AW19

VSS

AW29

VSS

AW37

VSS

AW9

VSS

AY38

VSS

AY45

VSS

B25

VSS

B3

VSS

B37

VSS

B40

VSS

B6

VSS

BA1

VSS

BB11

VSS

BB16

VSS

BB21

VSS

BB25

VSS

BB30

VSS

BB34

VSS

BC2

VSS

BD43

VSS

9 OF 12RE V = 1.3

UH1L

C42

VSS

D10

VSS

D12

VSS

D15

VSS

D16

VSS

D17

VSS

D19

VSS

D21

VSS

D24

VSS

D25

VSS

D27

VSS

D29

VSS

D30

VSS

D31

VSS

D33

VSS

D35

VSS

D36

VSS

E13

VSS

E15

VSS

E31

VSS

E33

VSS

F44

VSS

F8

VSS

G42

VSS

G9

VSS

H17

VSS

H19

VSS

H22

VSS

H24

VSS

H27

VSS

H29

VSS

H3

VSS

H35

VSS

J10

VSS

J11

VSS

J3

VSS

J39

VSS

J5

VSS

T42

VSS

U10

VSS

U11

VSS

U14

VSS

U17

VSS

U18

VSS

U28

VSS

U29

VSS

U31

VSS

U32

VSS

U33

VSS

U38

VSS

U4

VSS

U8

VSS

V18

VSS

V20

VSS

V21

VSS

V23

VSS

V25

VSS

V29

VSS

V3

VSS

V45

VSS

W14

VSS

W31

VSS

W32

VSS

W33

VSS

W38

VSS

W4

VSS

W8

VSS

Y17

VSS

SKL-H-PCH_B GA837

SPT-H_PCH

AB11

VSS

AB7

VSS

AB14

VSS

AB31

VSS

AB32

VSS

AB38

VSS

AB4

VSS

AB5

VSS

AC1

VSS

AC20

VSS

AC21

VSS

AC25

VSS

AC29

VSS

AC45

VSS

AB8

VSS

AD11

VSS

AD14

VSS

AB15

VSS

AD32

VSS

AD33

VSS

AD36

VSS

AD4

VSS

AD8

VSS

AE18

VSS

AE20

VSS

AE21

VSS

AE25

VSS

AE28

VSS

AL10

VSS

AL11

VSS

AL13

VSS

AL17

VSS

AL19

VSS

AL24

VSS

AL29

VSS

AL32

VSS

AL33

VSS

AL38

VSS

AM15

VSS

AM17

VSS

AM19

VSS

AM22

VSS

AM24

VSS

AM27

VSS

AM29

VSS

AM45

VSS

AN11

VSS

AN22

VSS

AN27

VSS

AN31

VSS

AN39

VSS

AN7

VSS

AN8

VSS

AP11

VSS

AP4

VSS

AR33

VSS

AR34

VSS

AR42

VSS

AR9

VSS

AT10

VSS

AT15

VSS

AT36

VSS

AT9

VSS

AU1

VSS

AU35

VSS

AU36

VSS

AU39

VSS

AU45

VSS

C4

VSS

12 OF 12REV = 1.3

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Size Document Nu mber Rev

Date: Sheet of

Compal Electronics, Inc.

SKYLAKE PCH-H (9/9)

LA-C551P

27 74Tuesday, Au gust 18, 20 15

1

1.0

5

4

3

+3.3V_RUN

2

1

4.7K_0402_5%

12

U8

+3.3V_RUN

1

2

+3.3V_RUN

1

2

AAC@

1U_0402_6.3V6K

0.1U_0402_25V6K

AAC@

C31

1

C32

2

AAC@

1U_0402_6.3V6K

0.1U_0402_25V6K

AAC@

C33

1

C34

2

D D

C C

To FAN Connector

To CY8C4245AXI

To FAN Connector

To CY8C4245AXI

B B

OA_M2

1 2

R375 1K_0402_5%

AAC@

A A

12

C35 1U_0402 _6.3V6KAAC@

DMIC_CLK_R<30>

11/12

Input

Output

1U_0402_6.3V6K

AAC@

1

560_0402_5%

C36

12

2

FAN2_PWM FAN1_PWM

FAN1_PWM_EC_AAC FAN2_PWM_EC_AAC

FAN2_TACH_FB FAN1_TACH_FB

FAN1_TACH_EC_AAC FAN2_TACH_EC_AAC

C1420 2.2U_ 0402_6.3V6M

AAC@

@

R371

LTW-270US5_WHITE

21

@

LED5

1 2

11/12

OA_OUT1 OA_M1

OA_M1

1 2

R373 2.2K_0402_5%AAC@

P0_7

FAN2_TACH_EC_AAC FAN1_TACH_EC_AAC FAN2_TACH_FB_AAC FAN1_TACH_FB_AAC

ADC_BYPASS

ADC_M OA_M1 OA_OUT1 OA_OUT2 OA_M2 ADC_M

nXRES

1 2

R27 0_0402_5%AAC@

1 2

R28 0_0402_5%AAC@

1 2

R21 0_0402_5%@AAC@

1 2

R22 0_0402_5%@AAC@

1 2

R25 0_0402_5%AAC@

1 2

R26 0_0402_5%AAC@

1 2

R29 0_0402_5%AAC@

1 2

R30 0_0402_5%AAC@

1 2

R12 0_0402_5%@AAC@

1 2

R13 0_0402_5%@AAC@

1 2

R23 0_0402_5%AAC@

1 2

R24 0_0402_5%AAC@

C143 1500P_0402_50V7KAAC@

R376 20K_0402_5%AAC@

C141 3300P_0402_25V7KAAC@

R414 10K_0402_ 5%AAC@

1 2

AAC@

CY8C4245

33

VCCD

P2[7]

VDDD0 VDDD1

VDDA

P0[7] P0[6] P0[5] P0[4] P0[3] P0[2] P0[1] P0[0]

P1[7] P1[6] P1[5] P1[4] P1[3] P1[2] P1[1] P1[0]

XRES

FAN2_PWM_AAC FAN1_PWM_AAC

FAN2_PWM_EC FAN1_PWM_EC

FAN2_TACH_FB_AAC FAN1_TACH_FB_AAC

P2[6] P2[5] P2[4] P2[3] P2[2] P2[1] P2[0]

P3[7] P3[6] P3[5] P3[4] P3[3] P3[2] P3[1] P3[0]

P4[3] P4[2] P4[1] P4[0]

VSSA VSS1 VSS0

19 34

35

31 30 29 28 27 26 25 24

44 43 42 41 40 39 38 37

32

CY8C4245AXI-483_TQFP44_1 0X10

1 2

C365 2.2U_0402 _6.3V6M

AAC@

ADC_M

9 8 7 6

FAN2_PWM_EC_AAC

5

FAN1_PWM_EC_AAC

4

FAN2_PWM_AAC

3

FAN1_PWM_AAC

2

18

AAEN

17 16 15

SWV_CLK

14

SWV_IO

13 12 11

23 22

AAC_SMBDAT

21

AAC_SMBCLK

20

36 10 1

From CY8C4245AXI

FAN2_PWM_EC <46> FAN1_PWM_EC <46>

From CY8C4245AXI

FAN2_TACH_EC <46> FAN1_TACH_EC <46>

OA_M2OA_OUT2

DMIC0_R <30 >

Input

Output

AAEN <45>

11/12

PAD~D PAD~D

@ @

nXRES SWV_CLK SWV_IO

T205 T206

+3.3V_RUN

AAC_SMBDAT

AAC_SMBCLK

12

@

R3738

JP2

XDP@

1

2

3

4

5

6

SUYIN_254201MS006G291 ZO

@

R3739

R38 0_0402_5%@

R39 0_0402_5%@

1 2

R40 0_0402_5%@

R41 0_0402_5%@

R213 0_0603_5%@

1 2

12

D90

21

RB751S40T1G_SOD523-2

DMN66D0LDW-7_ SOT363-6

+5V_RUN

+3.3V_RUN

5

DMN66D0LDW-7_ SOT363-6

4

Q366B

@

PCH_AAC_SMBCLK <24>

FAN2_PWM_DFAN2_PWM

+5V_RUN

10U_0603_6.3V6M

11/3

2

61

Q366A

@

3

PCH_AAC_SMBDAT <24>

FAN2_PWM_D

FAN1_PWM

FAN2_PWM

FAN2_TACH_FB

FAN1_TACH_FB

ADC_M

P0_7

ADC_M

FAN1_PWM FAN1_TACH_FB

0.1U_0402_25V6K

10U_0805_10V6K

C364

C30

1

2

FAN2_TACH_FB

0.1U_0402_25V6K

C370

1

C330

2

USH_SMBDAT <37,46>

USH_SMBCLK <3 7,46>

12

R41110K_040 2_5% AAC@

CPU FAN

CPU FANCPU FAN

JFAN1

6

G6

5

G5

4

3

2

1

ACES_50273-0040N-001

CONN@

Link CIS

Link CISLink CIS OK

OK

OKOK

MXM FAN

MXM FANMXM FAN

JFAN2

6

G6

5

G5

4

3

2

1

ACES_50273-0040N-001

CONN@

Link CIS

Link CISLink CIS OK

OK

OKOK

+3.3V_RUN

R40310K_0402_ 5%

R40710 K_0402_5%

R40910 K_0402_5% @

R40510 K_0402_5%

R40810 K_0402_5%

R41010 K_0402_5% AAC@

R41310 K_0402_5% AAC@

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

FAN control

LA-C551P

28 74Tuesday, August 18, 2015

1

1.0

5

+3.3V_RUN

D D

MXM_EDP_ P0<18> MXM_EDP_ N0<18> MXM_EDP_ P1<18> MXM_EDP_ N1<18>

MXM

MXMMXM

C C

CPU

CPUCPU

MXM_EDP_ P2<18> MXM_EDP_ N2<18> MXM_EDP_ P3<18> MXM_EDP_ N3<18>

MXM_EDP_ AUXP<18> MXM_EDP_ AUXN<18>

EDP_AUXP<9> EDP_AUXN<9>

MXM_EDP_ P0 MXM_EDP_ N0 MXM_EDP_ P1 MXM_EDP_ N1 MXM_EDP_ P2 MXM_EDP_ N2 MXM_EDP_ P3 MXM_EDP_ N3

MXM_EDP_ AUXP MXM_EDP_ AUXN

EDP_TXP0

EDP_TXP0<9>

EDP_TXN0

EDP_TXN0<9>

EDP_TXP1

EDP_TXP1<9>

EDP_TXN1

EDP_TXN1<9>

EDP_TXP2

EDP_TXP2<9>

EDP_TXN2

EDP_TXN2<9>

EDP_TXP3

EDP_TXP3<9>

EDP_TXN3

EDP_TXN3<9>

EDP_AUXP EDP_AUXN

C549 0.1U_040 2_10V6K C537 0.1U_040 2_10V6K C557 0.1U_040 2_10V6K C556 0.1U_040 2_10V6K C560 0.1U_040 2_10V6K C559 0.1U_040 2_10V6K C564 0.1U_040 2_10V6K C562 0.1U_040 2_10V6K

C566 0.1U_040 2_10V6K C568 0.1U_040 2_10V6K

C561 0.1U_040 2_10V6K C563 0.1U_040 2_10V6K C565 0.1U_040 2_10V6K C567 0.1U_040 2_10V6K C569 0.1U_040 2_10V6K C571 0.1U_040 2_10V6K C570 0.1U_040 2_10V6K C572 0.1U_040 2_10V6K

C558 0.1U_040 2_10V6K C555 0.1U_040 2_10V6K

1

2

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

1 2 1 2

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

1 2 1 2

4

4.7U_0603_6.3V6K

0.1U_0402_10V6K

1

C784

C500

2

MXM_EDP_ HPD<1 8>

CPU_EDP_ HPD<24>

1

C501

2

0.1U_0402_10V6K

1

C502

C554

2

EDP_IN2_ PEQ EDP_IN1_ PEQ EDP_IN1_ AEQ# EDP_IN2_ AEQ#

MXM_EDP_ P0_C MXM_EDP_ N0_C MXM_EDP_ P1_C MXM_EDP_ N1_C MXM_EDP_ P2_C MXM_EDP_ N2_C MXM_EDP_ P3_C MXM_EDP_ N3_C

MXM_EDP_ AUXP_C MXM_EDP_ AUXN_C

EDP_TXP0_ C EDP_TXN0_ C EDP_TXP1_ C EDP_TXN1_ C EDP_TXP2_ C EDP_TXN2_ C EDP_TXP3_ C EDP_TXN3_ C

EDP_AUXP _C EDP_AUXN _C

MXM_EDP_ HPD CPU_EDP_ HPD

U630

21

VDD33

26

VDD33

35

VDD33

49

VDD33

60

VDD33

51

IN2_PEQ/SCL_CTL

52

IN1_PEQ/SDA_CTL

59

IN1_AEQ#

58

IN2_AEQ#

1

IN1_D0p

2

IN1_D0n

4

IN1_D1p

5

IN1_D1n

6

IN1_D2p

7

IN1_D2n

9

IN1_D3p

10

IN1_D3n

28

IN1_AUXp

27

IN1_AUXn

23

IN1_SCL

22

IN1_SDA

11

IN2_D0p

12

IN2_D0n

14

IN2_D1p

15

IN2_D1n

16

IN2_D2p

17

IN2_D2n

19

IN2_D3p

20

IN2_D3n

30

IN2_AUXp

29

IN2_AUXn

25

IN2_SCL

24

IN2_SDA

3

IN1_HPD

13

IN2_HPD

CIS LINK OK

3

OUT_AUXp_SCL OUT_AUXn_SDA

I2C_CTL_EN

PI0 PC0 PC1

CA_DET

OUT_D0p OUT_D0n OUT_D1p

OUT_D1n OUT2_D2p OUT2_D2n

OUT_D3p

OUT_D3n

SW

OUT_HPD

REXT CEXT

GND GND GND GND GND Epad

PS8331B QFN60GTR-A0_Q FN60_5X9

PD

SW1_E DP_AUXP

32

SW1_E DP_AUXN

31

53

EDP_MUX_ PI0

56

EDP_MUX_ PC0

38

EDP_MUX_ PC1

55

48

R3722 1M_0402_5%

46 45 43 42 40 39 37 36

54

SW1_E DP_HPD

44

34 47

8 18 33 41 57 61 50

1 2

SW1_E DP_P0 SW1_E DP_N0 SW1_E DP_P1 SW1_E DP_N1 SW1_E DP_P2 SW1_E DP_N2 SW1_E DP_P3 SW1_E DP_N3

MUX_REXT MUX_CET

SW1_E DP_AUXP <30> SW1_E DP_AUXN <30>

DGPU_SEL ECT# <30,45>

SW1_E DP_HPD <30 >

SW1_E DP_P0 <30> SW1_E DP_N0 <30> SW1_E DP_P1 <30> SW1_E DP_N1 <30> SW1_E DP_P2 <30> SW1_E DP_N2 <30> SW1_E DP_P3 <30> SW1_E DP_N3 <30>

R101

4.99K_0 402_1%

1 2

2

EDP_MUX_ PC0

EDP_MUX_ PC1

EDP_IN1_ AEQ#

EDP_IN2_ AEQ#

EDP_IN1_ PEQ

EDP_IN2_ PEQ

EDP_MUX_ PI0

MUX_CET

EDP_MUX_ PI0

EDP_MUX_ PC0

EDP_MUX_ PC1

EDP_IN1_ PEQ

EDP_IN2_ PEQ

eDP

eDPeDP Conn

Conn

ConnConn

DGPU_SELECT#; 0: MXM ; 1: i- GPU

SW

H

L

Input

IN2

IN1(Defaul t)

1

1 2

R100 4 .7K_0402_ 5%@

1 2

R109 4 .7K_0402_ 5%@

1 2

R140 4 .7K_0402_ 5%@

1 2

R142 4 .7K_0402_ 5%@

1 2

R127 4 .7K_0402_ 5%@

1 2

R133 4 .7K_0402_ 5%@

1 2

R143 4 .7K_0402_ 5%@

12

C98 2.2U_040 2_6.3V6M

1 2

R139 4 .7K_0402_ 5%@

1 2

R136 4 .7K_0402_ 5%@

1 2

R141 4 .7K_0402_ 5%@

1 2

R137 4 .7K_0402_ 5%@

1 2

R138 4 .7K_0402_ 5%@

+3.3V_RUN

B B

A A

5

INy_PEQ = Progr ammable input e qualization le vels L: default, LEQ , compensate ch annel loss up to 11.5dB @ HBR 2 H: HEQ, compens ate channel los s up to 14.5dB @ HBR2 M: LLEQ, compen sate channel lo ss up to 8.5dB @ HBR2

INy_AEQ# = Auto matic EQ disabl e L: Automatic EQ enable (defaul t) H: Automatic EQ disable

PI0 = Auto test enable L: Auto test di sable & input o ffset cancella tion enable (de fault) H: Auto test en able & input of fset cancellat ion enable M: Auto test di sable & input o ffset cancella tion disable

PC0 = AUX inter ception disable L: AUX intercep tion enable, dr iver configura tion is set by link training ( default) H: AUX intercep tion disable, d river output w ith fixed 800mV and 0dB M: AUX intercep tion disable, d river output w ith fixed 400mV and 0dB

PC1 = Output sw ing adjustment L: default H: +20% M: -16.7%

PROPRIETARY NOTE: THIS SHEET O F ENGINEERING DRAWING AND SPEC IFICATIONS CONTAINS CONFIDENTI AL TRADE SECRET AND OTHER PROPRIE TARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHO UT THE EXPRESS WRITTEN AUTHORI ZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS WAY BE US ED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT DELL'S EXPRESS W RITTEN CONSENT.

4

3

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

Size Document Nu mber Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

eDP MUX (PS8331)

LA-C551P

29 74Tuesday, Au gust 18, 20 15

1

1.0

5

Close to JEDP1

Close to JEDP1Close to JEDP1

CONN@

ACES_50398-04041-00 1

1

2

3

4

5

41 42 43 44 45

JEDP1

CIS link

CIS linkCIS link OK

OK

OKOK

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

G1

37

G2

38

G3

39

G4

40

G5

0.1U_0402_25V6K

C298

1

2

D D

C C

+BL_PWR_SRC +LCDVDD

0.1U_0603_50V7K

2

C249

1

Close to

Close toClose to JEDP1

JEDP1

JEDP1JEDP1

SW1_EDP_AUXN

11/10

SW1_EDP_HPD

SW1_EDP_AUXP

+BL_PWR_SRC

+LCDVDD

+CAMERA_VDD +3.3V_RUN

USB20_N11_R USB20_P11_R

R208 0_0603_5%@EMC@

DISP_ON

SW1_EDP_AUXP_C SW1_EDP_AUXN_C

SW1_EDP_N3_C SW1_EDP_P3_C SW1_EDP_N2_C SW1_EDP_P2_C SW1_EDP_N1_C SW1_EDP_P1_C SW1_EDP_N0_C SW1_EDP_P0_C

DMIC_CLK

DMIC0

12

LCD_CBL_DET# <24>

LCD_TST <45>

SW1_EDP_HPD <29>

12

R339100K_040 2_5%

R222100K_0402_5% @

R336100K_040 2_5%

+3.3V_RUN

R362 0_0 402_5%AAC@ R361 0_0 402_5%AAC@

DMIC_CLK <44>

DMIC0 <44>

BIA_PWM

DMIC_CLK

DMIC0

1 2 1 2

12 12

12 12 12 12 12 12 12 12

SW1_EDP_HPD

2

3

CAM_MIC_CBL_DET# <19>

C3710.1U_0402_10V6K C3730.1U_0402_10V6K

C3740.1U_0402_10V6K C3720.1U_0402_10V6K C3760.1U_0402_10V6K C3750.1U_0402_10V6K C3780.1U_0402_10V6K C3770.1U_0402_10V6K C3800.1U_0402_10V6K C3790.1U_0402_10V6K

4

@EMC@

D22

1

PESD5V0U2BT_SOT23-3

DMIC0_R <28> DMIC_CLK_R <28>

SW1_EDP_AUXP <29>

SW1_EDP_AUXN <29>

SW1_EDP_N3 <29 > SW1_EDP_P3 <29> SW1_EDP_N2 <29 > SW1_EDP_P2 <29> SW1_EDP_N1 <29 > SW1_EDP_P1 <29> SW1_EDP_N0 <29 > SW1_EDP_P0 <29>

DMIC_CLK

DMIC0

3

+3.3V_RUN

100K_0402_5%

IR_CAM_DET#

21

D65

D64

21

D69

21

RB751VM-40TE-17_SOD323- 2

D68

21

RB751VM-40TE-17_SOD323- 2

12

R366

IR_CAM_DET# <24>

PANEL_BKEN_PCH <19>

MXM_PANEL_BKEN <18>

PANEL_BKEN_EC <45>

D66

21

+3.3V_RUN

1

4

OE#

D71

21

0.1U_0402_10V7K

5

P

A2Y

G

TC7SH125FU_SSOP5

3

BIA_PWM_PCH <19>

C248

1 2

U3

MXM_BIA_PWM <18>

BIA_PWM_EC <46>

IR Conn.

+BL_PWR_SRC

CONN@

JIR1

1

2

3

4

5

6

7

G1

8

G2

ACES_50228-0067N-001

11/17 RF request

1 2

C1467 100P_0402_50V8JEMC@

1 2

C1468 100P_0402_50V8JEMC@

10K_0402_5%

12

R1137

RB751VM-40TE-17_SOD323- 2

DISP_ON

100K_0402_5%

12

R1138

+LCDVDD

R1034.7K_04 02_5%

12

DGPU_SELECT#<29,45>

BIA_PWM

2

40mil

+PWR_SRC

100K_0402_5%

1U_1206_50V7

C297

1

12

2

0.01U_0402_50V7K

1

C293

2

Panel backlight power control

Panel backlight power controlPanel backlight power control by EC

by EC

by ECby EC

DMP3050LVT-7_TSOT26-6

4 5

R422

BL_PWR_SRC_ON

1 2

R423 4 7K_0402_5%

EN_INVPWR<46>

Q21

S

G

3

D

6

2 1

Q22 DMN65D8LW-7_SOT323-3

1 3

D

+BL_PWR_SRC

G

2

1

40mil

0.1U_0603_50V7K

1

C296

2

S

B B

Webcam PWR CTRL

Webcam PWR CTRLWebcam PWR CTRL

+3.3V_RUN

0.1U_0402_25V6K

C301

A A

1

2

5

Q24

LP2301ALT1G_SOT23- 3

D

S

13

G

2

3.3V_CAM_EN# <20>

10U_0603_6.3V6M

+CAMERA_VDD

@

1

C300

2

0.1U_0402_25V6K

C299

1

2

USB20_N11<20>

USB20_P11<20>

4

EMC request change main source to SM070003Z00

L10

EMC@

1 2

MCM1012B900F06BP_4P

34

USB20_N11_R

USB20_P11_R

2

3

D21

@EMC@

PESD5V0U2BT_SOT23-3

1

Close to

Close toClose to

JEDP1

JEDP1JEDP1

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

LCD Power

LCD PowerLCD Power

2

C396

@

10U_0603_6.3V6M

12

LCD_VCC_TEST_EN<45>

ENVDD_PCH<19,4 6>

MXM_ENVDD<18>

+LCDVDD

1 2

R42 100K_0 402_5%@

BAT54CW_SOT323-3

RB751VM-40TE-17_SOD323- 2

D92

2 1

2

3

D93

1

VOUT

2

GND

3

/OC

G524B1T11U_SOT23-5

1

100K_0402_5%

12

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

eDP / CAM / TS

U33

5

VIN

4

EN

R3727

LA-C551P

1

+3.3V_ALW

1.0

30 74Tuesday, August 18, 2015

1.0

5

D D

2

1 2

MXM_DPC_P0 MXM_DPC_N0 MXM_DPC_P1 MXM_DPC_N1 MXM_DPC_P2 MXM_DPC_N2 MXM_DPC_P3 MXM_DPC_N3

MXM_DPC_AUXP MXM_DPC_AUXN

CPU_DP1_P0 CPU_DP1_N0 CPU_DP1_P1 CPU_DP1_N1 CPU_DP1_P2 CPU_DP1_N2 CPU_DP1_P3 CPU_DP1_N3

CPU_DP1_AUXP CPU_DP1_AUXN

DPD_CA_DET_Q

MXM_DPC_AUXP

MXM_DPC_AUXN

MXM_DPC_P0<18> MXM_DPC_N0<18> MXM_DPC_P1<18> MXM_DPC_N1<18>

MXM

MXMMXM

CPU

C C

B B

CPU

CPUCPU

+3.3V_RUN

DMN66D0LDW-7_SOT363-6

Q343B

MXM_DPC_P2<18> MXM_DPC_N2<18> MXM_DPC_P3<18> MXM_DPC_N3<18>

MXM_DPC_AUXP<18>

MXM_DPC_AUXN<18>

CPU_DP1_P0<9> CPU_DP1_N0<9> CPU_DP1_P1<9> CPU_DP1_N1<9> CPU_DP1_P2<9> CPU_DP1_N2<9> CPU_DP1_P3<9> CPU_DP1_N3<9>

CPU_DP1_AUXP<9> CPU_DP1_AUXN<9>

DOCK DPD (PORT1) DDC-before

DOCK DPD (PORT1) DDC-beforeDOCK DPD (PORT1) DDC-before PS8331

PS8331

PS8331PS8331

DMN66D0LDW-7_SOT363-6

3

61

Q343A

5

4

R129 4.7K_0402_5%

R132 4.7K_0402_5%

4

+3.3V_RUN

4.7U_0603_6.3V6K

0.1U_0402_10V6K

1

C783

C495

2

1 2

C523 0.1U_0402_10V6K

1 2

C525 0.1U_0402_10V6K

1 2

C524 0.1U_0402_10V6K

1 2

C527 0.1U_0402_10V6K

1 2

C526 0.1U_0402_10V6K

1 2

C529 0.1U_0402_10V6K

1 2

C530 0.1U_0402_10V6K

1 2

C528 0.1U_0402_10V6K

1 2

C532 0.1U_0402_10V6K

1 2

C531 0.1U_0402_10V6K

1 2

C593 0.1U_0402_10V6K

1 2

C597 0.1U_0402_10V6K

1 2

C598 0.1U_0402_10V6K

1 2

C626 0.1U_0402_10V6K

1 2

C628 0.1U_0402_10V6K

1 2

C629 0.1U_0402_10V6K

1 2

C586 0.1U_0402_10V6K

1 2

C584 0.1U_0402_10V6K

1 2

C591 0.1U_0402_10V6K

1 2

C588 0.1U_0402_10V6K

PCH_DPB_CTRL_CLK<24> PCH_DPB_CTRL_DATA<24>

MXM_DPC_HPD<18>

PCH_DPB_HPD<24>

+3.3V_RUN+5V_RUN

100K_0402_5%

12

DMN66D0LDW-7_SOT363-6

3

Q347B

4

100K_0402_5%

12

R721

5

DMN66D0LDW-7_SOT363-6

61

Q347A

0.1U_0402_10V6K

R722

2

C499

1

2

DPD_CA_DET

0.1U_0402_10V6K

1

C494

C504

2

DP1_MUX_IN2_PEQ DP1_MUX_IN1_PEQ DP1_MUX_IN1_AEQ# DP1_MUX_IN2_AEQ#

MXM_DPC_P0_C MXM_DPC_N0_C MXM_DPC_P1_C MXM_DPC_N1_C MXM_DPC_P2_C MXM_DPC_N2_C MXM_DPC_P3_C MXM_DPC_N3_C

MXM_DPC_AUXP_C MXM_DPC_AUXN_C

CPU_DP1_P0_C CPU_DP1_N0_C CPU_DP1_P1_C CPU_DP1_N1_C CPU_DP1_P2_C CPU_DP1_N2_C CPU_DP1_P3_C CPU_DP1_N3_C

CPU_DP1_AUXP_C

CPU_DP1_AUXN_C PCH_DPB_CTRL_CLK PCH_DPB_CTRL_DATA

MXM_DPC_HPD

PCH_DPB_HPD

DPD_CA_DET_Q

U629

21

VDD33

26

VDD33

35

VDD33

49

VDD33

60

VDD33

51

IN2_PEQ/ SCL_CTL

52

IN1_PEQ/ SDA_CTL

59

IN1_AEQ#

58

IN2_AEQ#

1

IN1_D0p

2

IN1_D0n

4

IN1_D1p

5

IN1_D1n

6

IN1_D2p

7

IN1_D2n

9

IN1_D3p

10

IN1_D3n

28

IN1_AUXp

27

IN1_AUXn

23

IN1_SCL

22

IN1_SDA

11

IN2_D0p

12

IN2_D0n

14

IN2_D1p

15

IN2_D1n

16

IN2_D2p

17

IN2_D2n

19

IN2_D3p

20

IN2_D3n

30

IN2_AUXp

29

IN2_AUXn

25

IN2_SCL

24

IN2_SDA

3

IN1_HPD

13

IN2_HPD

5

3

CIS LINK OK

PS8331BQFN60GTR-A0_QFN60_5X9

+3.3V_RUN

4.7K_0402_5%

12

@

R2195

61

@

2

DMN66D0LDW-7_SOT363-6

+3.3V_RUN

4.7K_0402_5%

12

@

R2196

DMN66D0LDW-7_SOT363-6

3

@

Q365B

4

SW2_DP_AUXP

I2C_CTL_EN

CA_DET

OUT_D0p OUT_D0n OUT_D1p

OUT_D1n OUT2_D2p OUT2_D2n

OUT_D3p

OUT_D3n

OUT_HPD

REXT CEXT

GND GND GND GND GND Epad

32

SW2_DP_AUXN

31

53

DP1_MUX_PI0

56

PI0

DP1_MUX_PC0

38

PC0

DP1_MUX_PC1

55

PC1

DPD_CA_DET

48

SW2_DP_P0

46

SW2_DP_N0

45

SW2_DP_P1

43

SW2_DP_N1

42

SW2_DP_P2

40

SW2_DP_N2

39

SW2_DP_P3

37

SW2_DP_N3

36

PBA_GPU_SEL#

54

SW

SW2_DP_HPD

44

DP1_MUX_REXT

34

DP1_MUX_CEXT

47

8 18 33 41 57 61 50

PD

INy_PEQ = Programmable input equalization levels L: default, LEQ, compensate channel loss up to 11.5dB @ HBR2 H: HEQ, compensate channel loss up to 14.5dB @ HBR2 M: LLEQ, compensate channel loss up to 8.5dB @ HBR2

INy_AEQ# = Automatic EQ disable L: Automatic EQ enable (default) H: Automatic EQ disable

PI0 = Auto test enable L: Auto test disable & input offset cancellation enable (default) H: Auto test enable & input offset cancellation enable M: Auto test disable & input offset cancellation disable

PC0 = AUX interception disable L: AUX interception enable, driver configuration is set by link training (default) H: AUX interception disable, driver output with fixed 800mV and 0dB M: AUX interception disable, driver output with fixed 400mV and 0dB

PC1 = Output swing adjustment L: default H: +20% M: -16.7%

OUT_AUXp_S CL OUT_AUXn_S DA

11/11

DDC between PS8331/PS8338, do not need pull up.

Q365A

SW2_DP_AUXP

SW2_DP_AUXP <43> SW2_DP_AUXN <43>

DPD_CA_DET <43>

SW2_DP_P0 <43> SW2_DP_N0 <43> SW2_DP_P1 <43> SW2_DP_N1 <43> SW2_DP_P2 <43> SW2_DP_N2 <43> SW2_DP_P3 <43> SW2_DP_N3 <43>

PBA_GPU_SEL# <45>

SW2_DP_HPD <43>

R96

4.99K_0402_1%

1 2

2

Docking

Docking Docking DP1

DP1

DP1DP1

PBA_GPU_SEL#; 0: MXM ; 1: i-GPU

SW Input

H IN2

IN1L (Default)

DP1_MUX_PC0

DP1_MUX_PC1

DP1_MUX_IN1_AEQ#

DP1_MUX_IN2_AEQ#

DP1_MUX_IN1_PEQ

DP1_MUX_IN2_PEQ

DP1_MUX_PI0

DP1_MUX_CEXT

DP1_MUX_PI0

DP1_MUX_PC0

DP1_MUX_PC1

DP1_MUX_IN1_PEQ

DP1_MUX_IN2_PEQ

1

1 2

R98 4.7K_0402_5%@

1 2

R99 4.7K_0402_5%

1 2

R117 4.7K_0402_5%@

1 2

R118 4.7K_0402_5%

1 2

R119 4.7K_0402_5%

1 2

R120 4.7K_0402_5%

1 2

R124 4.7K_0402_5%@

12

C97 2.2U_0402_6.3V6M

1 2

R123 4.7K_0402_5%@

1 2

R115 4.7K_0402_5%@

1 2

R116 4.7K_0402_5%@

1 2

R121 4.7K_0402_5%

1 2

R122 4.7K_0402_5%

+3.3V_RUN

A A

SW2_DP_AUXN

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

MXM/CPU MUX(PS8331)

LA-C551P

31 74Tuesday , August 18, 2015

1

1.0

5

4

3

2

1

+3.3V_RUN

RV42 4.7K_0402_5%

@

RV43 4.7K_0402_5%

@

D D

C C

B B

RV44 4.7K_0402_5%

RV28 1M_0402_5%

RV45 1M_0402_5%

+3.3V_RUN

12

RV29

RV30

@

4.7K_0402_5%

12

RV35

RV36

@

4.7K_0402_5%

12

4.7K_0402_5%

12

4.7K_0402_5%

1 2

RV31

@

4.7K_0402_5%

RV38

@

4.7K_0402_5%

12

DP1_DEMUX_CFG0

DPC_CA_DET

12

RV32

@

4.7K_0402_5%

12

RV37

@

4.7K_0402_5%

DP1_DEMUX_SW

DP1_DEMUX_PI0

MID1_CA_DET

12

RV33

RV34

@

4.7K_0402_5%

12

RV39

RV40

@

4.7K_0402_5%

MXM_DPA_P0

MXM_DPA_P0<18>

MXM_DPA_N0

MXM_DPA_N0<18>

MXM_DPA_P1

MXM_DPA_P1<18>

MXM_DPA_N1

MXM_DPA_N1<18>

MXM

MXMMXM

12

4.7K_0402_5%

DP1_DEMUX_PI1

DP1_DEMUX_PC10

DP1_DEMUX_PC11

DP1_DEMUX_PC20

DP1_DEMUX_PC21

12

4.7K_0402_5%

MXM_DPA_AUXP<18> MXM_DPA_AUXN< 18>

MXM_DPA_P2<18> MXM_DPA_N2<18>

MXM_DPA_P3<18> MXM_DPA_N3<18>

DPC_CA_DET_IN

MXM_DPA_P2 MXM_DPA_N2

MXM_DPA_P3 MXM_DPA_N3

MXM_DPA_AUXP MXM_DPA_AUXN

Port switching control or priority configuration. Internal pull down ~150KΩ, 3.3V I/O For Control Switching Mode (CFG0 = L): SW = L: Port1 is selected (default) SW = H: Port2 is selected

For Automatic Switching Mode (CFG0 = H): (By OUT1_HPD and OUT2_HPD) SW = L: Port1 has higher priority when both ports are plugged (default)

SW = H: Port2 has higher priority when both ports are plugged

DOCK DPC (PORT2)

DOCK DPC (PORT2)DOCK DPC (PORT2) DDC

DDC

DDCDDC

+3.3V_RUN

100K_0402_5%

12

R2197

61

2

0.01U_0402_16V7K

1

C1344

2

CV62 CV90 close to pin30 &57 CV66,CV69,CV70 close to pin5,21,51

0.01U_0402_16V7K

12

CV27

1 2

C545 0.1U_0402_10V6K

1 2

C540 0.1U_0402_10V6K

1 2

C551 0.1U_0402_10V6K

1 2

C550 0.1U_0402_10V6K

1 2

C573 0.1U_0402_10V6K C553 0.1U_0402_10V6K

1 2

C577 0.1U_0402_10V6K

1 2

C575 0.1U_0402_10V6K

1 2

C1438 0.1U_0402_10V6K

1 2

C1437 0.1U_0402_10V6K

+5V_RUN

100K_0402_5%

12

R2189

DPC_CA_DET_Q

DMN66D0LDW-7_SOT363-6

3

Q353B

5

4

DMN66D0LDW-7_SOT363-6

Q353A

0.01U_0402_16V7K

12

CV30

MXM_DPA_HPD<18>

+3.3V_RUN

4.7K_0402_5%

R2198

5

0.1U_0402_25V6

12

CV28

MXM_DPA_P0_C MXM_DPA_N0_C

MXM_DPA_P1_C MXM_DPA_N1_C

MXM_DPA_P2_C MXM_DPA_N2_C

MXM_DPA_P3_C MXM_DPA_N3_C

MXM_DPA_AUXP_C MXM_DPA_AUXN_C

+3.3V_RUN

4.7K_0402_5%

R2194

2

12

DMN66D0LDW-7_SOT363-6

3

Q355B

4

0.1U_0402_25V6

12

CV29

DPC_CA_DET_IN

DP1_DEMUX_PI1 DP1_DEMUX_PI0

DP1_DEMUX_CFG0

DP1_DEMUX_PC10 DP1_DEMUX_PC11 DP1_DEMUX_PC20 DP1_DEMUX_PC21

12

DMN66D0LDW-7_SOT363-6

61

Q355A

+3.3V_RUN

0.1U_0402_25V6

Dock has high priority when both ports plugged

UV2

CV31

5

VDD33

CFG0

MXM_DPA_AUXP

21

VDD33

30

VDD33

51

VDD33

57

VDD33

6

IN_D0p

7

IN_D0n

9

IN_D1p

10

IN_D1n

12

IN_D2p

13

IN_D2n

15

IN_D3p

16

IN_D3n

4

IN_CA_DET

3

IN_HPD

2

I2C_CTL_EN

1

Pl1/SCL_CTL

60

Pl0/SDA_CTL

22

IN_DDC_SCL

23

IN_DDC_SDA

24

IN_AUXp

25

IN_AUXn

59

CFG0

58

CFG1

56

PC10

55

PC11

54

PC20

53

PC21

11

GND

19

GND

52

GND

61

PAD(GND)

PS8338BQFN60GTR-A0_QFN60_5X9

H L

V

VSW

OUT1_D0p OUT1_D0n

OUT1_D1p OUT1_D1n

OUT1_D2p OUT1_D2n

OUT1_D3p OUT1_D3n

OUT2_D0p OUT2_D0n

OUT2_D1p OUT2_D1n

OUT2_D2p OUT2_D2n

OUT2_D3p OUT2_D3n

OUT1_AUXp_SCL OUT1_AUXn_SDA

OUT2_AUXp_SCL OUT2_AUXn_SDA

OUT1_CA_DET

OUT1_HPD

OUT2_CA_DET

OUT2_HPD

DPC_CA_DET_Q

50 49

47 46

45 44

42 41

40 39

37 36

35 34

32 31

26 27

28 29

43 48

33 38

18

SW

8

PEQ

14

PD

17

CEXT

20

REXT

5

SW3_DP1_P0 SW3_DP1_N0

SW3_DP1_P1 SW3_DP1_N1

SW3_DP1_P2 SW3_DP1_N2

SW3_DP1_P3 SW3_DP1_N3

SW3_DP2_P0 <34> SW3_DP2_N0 <34>

SW3_DP2_P1 <34> SW3_DP2_N1 <34>

SW3_DP2_P2 <34> SW3_DP2_N2 <34>

SW3_DP2_P3 <34> SW3_DP2_N3 <34>

SW3_DP1_AUXP

SW3_DP1_AUXP <43>

SW3_DP1_AUXN

SW3_DP1_AUXN <43>

SW3_DP2_AUXP <34>

SW3_DP2_AUXN <34>

DPC_CA_DET

DPC_CA_DET <43>

SW3_DP1_HPD

SW3_DP1_HPD <43>

MID1_CA_DET

MID1_CA_DET <34,44>

DP1_DEMUX_SW DP1_DEMUX_PEQDP1_DEMUX_PEQ

RV41

+3.3V_RUN

4.7K_0402_5%

@

R3736

SW3_DP2_HPD <34>

2.2U_0402_6.3V6M

12

CV42

4.99K_0402_1%

+3.3V_RUN

11/11

DDC between PS8331/PS8338, do not need pull up.

4.7K_0402_5%

12

@

R3737

DMN66D0LDW-7_SOT363-6

61

@

Q364A

2

SW3_DP1_AUXP

12

DMN66D0LDW-7_SOT363-6

3

@

Q364B

4

SW3_DP1_P0 <43> SW3_DP1_N0 <43>

SW3_DP1_P1 <43> SW3_DP1_N1 <43>

SW3_DP1_P2 <43> SW3_DP1_N2 <43>

SW3_DP1_P3 <43> SW3_DP1_N3 <43>

Docking port2

Docking port2Docking port2

MUX

MUXMUX

MXM_DPA_AUXN

A A

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

SW3_DP1_AUXN

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

DP DeMUX (PS8338)

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

LA-C551P

1

1.0

32 74Tuesday, August 18, 2015

2

+3.3V_RUN

4.7U_0603_6.3V6K

0.1U_0402_10V6K

1

C786

C506

2

MXM_DPB_P0

MXM_DPB_P0<18>

MXM_DPB_N0

MXM_DPB_N0<18>

MXM_DPB_P1

MXM_DPB_P1<18>

MXM_DPB_N1

MXM_DPB_N1<18>

MXM_DPB_P2

B B

+3.3V_RUN

DMN66D0LDW-7_SOT363-6

61

3

Q369A

Q369B

5

4

R3745 4.7K_0402_5%

R3747 4.7K_0402_5%

MXM

MXMMXM

CPU

CPUCPU

11/11

Vendor review, MXM card need add DDC pull up

2

MID2_CA_DET_Q

MXM_DPB_AUXP

1 2

MXM_DPB_AUXN

1 2

MXM_DPB_P2<18>

MXM_DPB_N2

MXM_DPB_N2<18>

MXM_DPB_P3

MXM_DPB_P3<18>

MXM_DPB_N3

MXM_DPB_N3<18>

MXM_DPB_AUXP<18> MXM_DPB_AUXN<18>

CPU_DP3_P0<9> CPU_DP3_N0<9> CPU_DP3_P1<9> CPU_DP3_N1<9> CPU_DP3_P2<9> CPU_DP3_N2<9> CPU_DP3_P3<9> CPU_DP3_N3<9>

12

DMN66D0LDW-7_SOT363-6

3

Q367B

4

MXM_DPB_AUXP MXM_DPB_AUXP_C

CPU_DP3_P0 CPU_DP3_N0 CPU_DP3_P1 CPU_DP3_N1 CPU_DP3_P2 CPU_DP3_N2 CPU_DP3_P3 CPU_DP3_N3

CPU_DP3_AUXP<9> CPU_DP3_AUXN<9>

CPU_DP3_AUXP CPU_DP3_AUXN

+3.3V_RUN+5V_RUN

100K_0402_5%

12

R3744

R3746

5

DMN66D0LDW-7_SOT363-6

61

Q367A

2

MID2_CA_DET

C587 0.1U_0402_10V6K

1 2 1 2

C585 0.1U_0402_10V6K

1 2

C590 0.1U_0402_10V6K

1 2

C589 0.1U_0402_10V6K

1 2

C594 0.1U_0402_10V6K C592 0.1U_0402_10V6K

1 2 1 2

C596 0.1U_0402_10V6K

1 2

C595 0.1U_0402_10V6K

1 2

C601 0.1U_0402_10V6K C627 0.1U_0402_10V6K

1 2

C1448 0.1U_0402_10V6K

1 2 1 2

C1450 0.1U_0402_10V6K

1 2

C1453 0.1U_0402_10V6K

1 2

C1451 0.1U_0402_10V6K

1 2

C1449 0.1U_0402_10V6K C1454 0.1U_0402_10V6K

1 2 1 2

C1455 0.1U_0402_10V6K

1 2

C1452 0.1U_0402_10V6K

1 2

C1447 0.1U_0402_10V6K C1446 0.1U_0402_10V6K

1 2

PCH_DPD_CTRL_CLK<24> PCH_DPD_CTRL_DATA<24>

MXM_DPB_HPD<18>

PCH_DPD_HPD<24>

1

C507

2

0.1U_0402_10V6K

1

C509

C508

2

DP3_MUX_IN2_PEQ DP3_MUX_IN1_PEQ DP3_MUX_IN1_AEQ# DP3_MUX_IN2_AEQ#

MXM_DPB_P0_C MXM_DPB_N0_C MXM_DPB_P1_C MXM_DPB_N1_C MXM_DPB_P2_C MXM_DPB_N2_C MXM_DPB_P3_C MXM_DPB_N3_C

MXM_DPB_AUXN_CMXM_DP B_AUXN

CPU_DP3_P0_C CPU_DP3_N0_C CPU_DP3_P1_C CPU_DP3_N1_C CPU_DP3_P2_C CPU_DP3_N2_C CPU_DP3_P3_C CPU_DP3_N3_C

CPU_DP3_AUXP_C

CPU_DP3_AUXN_C PCH_DPD_CTRL_CLK PCH_DPD_CTRL_DATA

MXM_DPB_HPD

PCH_DPD_HPD

CIS LINK OK

U636

21

VDD33

26

VDD33

35

VDD33

49

VDD33

60

VDD33

51

IN2_PEQ/SCL_CTL

52

IN1_PEQ/SDA_CTL

59

IN1_AEQ#

58

IN2_AEQ#

1

IN1_D0p

2

IN1_D0n

4

IN1_D1p

5

IN1_D1n

6

IN1_D2p

7

IN1_D2n

9

IN1_D3p

10

IN1_D3n

28

IN1_AUXp

27

IN1_AUXn

23

IN1_SCL

22

IN1_SDA

11

IN2_D0p

12

IN2_D0n

14

IN2_D1p

15

IN2_D1n

16

IN2_D2p

17

IN2_D2n

19

IN2_D3p

20

IN2_D3n

30

IN2_AUXp

29

IN2_AUXn

25

IN2_SCL

24

IN2_SDA

3

IN1_HPD

13

IN2_HPD

OUT_AUXp_SCL

OUT_AUXn_SDA

I2C_CTL_EN

PI0 PC0 PC1

CA_DET

OUT_D0p OUT_D0n OUT_D1p

OUT_D1n OUT2_D2p OUT2_D2n

OUT_D3p

OUT_D3n

SW

OUT_HPD

REXT CEXT

GND GND GND GND GND Epad

PS8331BQFN60GTR-A0_QFN60_5X9

INy_PEQ = Programmable input equalization levels L: default, LEQ, compensate channel loss up to 11.5dB @ HBR2 H: HEQ, compensate channel loss up to 14.5dB @ HBR2 M: LLEQ, compensate channel loss up to 8.5dB @ HBR2

INy_AEQ# = Automatic EQ disable L: Automatic EQ enable (default) H: Automatic EQ disable

PI0 = Auto test enable L: Auto test disable & input offset cancellation enable (default) H: Auto test enable & input offset cancellation enable M: Auto test disable & input offset cancellation disable

PC0 = AUX interception disable L: AUX interception enable, driver configuration is set by link training (default) H: AUX interception disable, driver output with fixed 800mV and 0dB M: AUX interception disable, driver output with fixed 400mV and 0dB

PC1 = Output swing adjustment L: default H: +20% M: -16.7%

PD

32 31

53

56 38 55

48

46 45 43 42 40 39 37 36

54

44

34 47

8 18 33 41 57 61 50

DP3_MUX_PI0 DP3_MUX_PC0 DP3_MUX_PC1

MID2_CA_DET

SW5_DP_P0 SW5_DP_N0 SW5_DP_P1 SW5_DP_N1 SW5_DP_P2 SW5_DP_N2 SW5_DP_P3 SW5_DP_N3

DP2_GPU_SEL#

SW5_DP_HPD

DP3_MUX_REXT DP3_MUX_CEXT

SW5_DP_AUXP SW5_DP_AUXN

SW5_DP_AUXP <44> SW5_DP_AUXN <44>

MID2_CA_DET <44>

SW5_DP_P0 <44> SW5_DP_N0 <44> SW5_DP_P1 <44> SW5_DP_N1 <44> SW5_DP_P2 <44> SW5_DP_N2 <44> SW5_DP_P3 <44> SW5_DP_N3 <44>

DP2_GPU_SEL# <45>

SW5_DP_HPD <44>

R106

4.99K_0402_1%

1 2

1

DP3_MUX_PC0

DP3_MUX_PC1

DP3_MUX_IN1_AEQ#

DP3_MUX_IN2_AEQ#

DP3_MUX_IN1_PEQ

DP3_MUX_IN2_PEQ

DP3_MUX_PI0

DP3_MUX_CEXT

DP3_MUX_PI0

mDP

mDPmDP

DP3_MUX_PC0

DP3_MUX_PC1

DP3_MUX_IN1_PEQ

DP3_MUX_IN2_PEQ

MID2_CA_DET

DP2_GPU_SEL#; 0: MXM ; 1: i-GPU

SW

H

L

Input

IN2

IN1(Default)

1 2

R105 4.7K_0402_5%@

1 2

R107 4.7K_0402_5%@

1 2

R159 4.7K_0402_5%@

R161 4.7K_0402_5%@

1 2

R153 4.7K_0402_5%

1 2

R154 4.7K_0402_5%

1 2

R162 4.7K_0402_5%@

12

C100 2.2U_0402_6.3V6M

1 2

R158 4.7K_0402_5%@

1 2

R155 4.7K_0402_5%@

1 2

R160 4.7K_0402_5%@

R156 4.7K_0402_5%

1 2

R157 4.7K_0402_5%

1 2

RV48 1M_0402_5%

+3.3V_RUN

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

PROPRIETARY NOTE:

PROPRIETARY NOTE: PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS

TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS

TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THISTRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

DOCUMENT MAY NOT

DOCUMENT MAY NOTDOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL.

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL.

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL.BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,

IN ADDITION,

IN ADDITION,IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED

NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED

NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSEDNEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

TO ANY THIRD

2

TO ANY THIRDTO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

1

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

HDMI CONN

LA-C551P

33 74Tuesday, August 18, 2015

1.0

5

4

3

2

1

D D

SW3_DP2_P0<32> SW3_DP2_N0<32> SW3_DP2_P1<32> SW3_DP2_N1<32>

MUX

MUXMUX

C C

B B

CPU

CPUCPU

SW3_DP2_P2<32> SW3_DP2_N2<32> SW3_DP2_P3<32> SW3_DP2_N3<32>

CPU_DP2_P0<9> CPU_DP2_N0<9> CPU_DP2_P1<9> CPU_DP2_N1<9> CPU_DP2_P2<9> CPU_DP2_N2<9> CPU_DP2_P3<9> CPU_DP2_N3<9>

CPU_DP2_AUXP<9> CPU_DP2_AUXN<9>

SW3_DP2_P0 SW3_DP2_N0 SW3_DP2_P1 SW3_DP2_N1 SW3_DP2_P2 SW3_DP2_N2 SW3_DP2_P3 SW3_DP2_N3

CPU_DP2_P0 CPU_DP2_N0 CPU_DP2_P1 CPU_DP2_N1 CPU_DP2_P2 CPU_DP2_N2 CPU_DP2_P3 CPU_DP2_N3

CPU_DP2_AUXP CPU_DP2_AUXN

+3.3V_RUN

4.7U_0603_6.3V6K

0.1U_0402_10V6K

1

C785

C496

2

C1460 0.1U_0402_1 0V6K

1 2 1 2

C1463 0.1U_0402_1 0V6K C1457 0.1U_0402_1 0V6K

1 2 1 2

C1458 0.1U_0402_1 0V6K

1 2

C1461 0.1U_0402_1 0V6K C1464 0.1U_0402_1 0V6K

1 2 1 2

C1462 0.1U_0402_1 0V6K C1459 0.1U_0402_1 0V6K

1 2

SW3_DP2_AUXP<32> SW3_DP2_AUXN<32 >

C574 0.1U_0402_10V6K

1 2 1 2

C576 0.1U_0402_10V6K C578 0.1U_0402_10V6K

1 2 1 2

C580 0.1U_0402_10V6K

1 2

C581 0.1U_0402_10V6K C583 0.1U_0402_10V6K

1 2 1 2

C546 0.1U_0402_10V6K C535 0.1U_0402_10V6K

1 2

C552 0.1U_0402_10V6K C548 0.1U_0402_10V6K

1 2

PCH_DPC_CTRL_C LK<24> PCH_DPC_CTRL_D ATA<24>

SW3_DP2_HPD<32>

PCH_DPC_HPD<24>

0.1U_0402_10V6K

1

C503

2

SW3_DP2_AUXP SW3_DP2_AUXN

PCH_DPC_CTRL_C LK PCH_DPC_CTRL_D ATA

0.1U_0402_10V6K

1

C505

C497

2

DP2_MUX_IN2_PEQ DP2_MUX_IN1_PEQ DP2_MUX_IN1_AEQ# DP2_MUX_IN2_AEQ#

SW3_DP2_P0_C SW3_DP2_N0_C SW3_DP2_P1_C SW3_DP2_N1_C SW3_DP2_P2_C SW3_DP2_N2_C SW3_DP2_P3_C SW3_DP2_N3_C

CPU_DP2_P0_C CPU_DP2_N0_C CPU_DP2_P1_C CPU_DP2_N1_C CPU_DP2_P2_C CPU_DP2_N2_C CPU_DP2_P3_C CPU_DP2_N3_C

CPU_DP2_AUXP_C CPU_DP2_AUXN_C

SW3_DP2_HPD PCH_DPC_HPD

CIS LINK OK

U631

21

VDD33

26

VDD33

35

VDD33

49

VDD33

60

VDD33

51

IN2_PEQ/SCL_CTL

52

IN1_PEQ/SDA_CTL

59

IN1_AEQ#

58

IN2_AEQ#

1

IN1_D0p

2

IN1_D0n

4

IN1_D1p

5

IN1_D1n

6

IN1_D2p

7

IN1_D2n

9

IN1_D3p

10

IN1_D3n

28

IN1_AUXp

27

IN1_AUXn

23

IN1_SCL

22

IN1_SDA

11

IN2_D0p

12

IN2_D0n

14

IN2_D1p

15

IN2_D1n

16

IN2_D2p

17

IN2_D2n

19

IN2_D3p

20

IN2_D3n

30

IN2_AUXp

29

IN2_AUXn

25

IN2_SCL

24

IN2_SDA

3

IN1_HPD

13

IN2_HPD

OUT_AUXp_SCL OUT_AUXn_SDA

I2C_CTL_EN

PS8331BQFN60GTR-A0_ QFN60_5X9

INy_PEQ = Programmable input equalization levels L: default, LEQ, compensate channel loss up to 11.5dB @ HBR2 H: HEQ, compensate channel loss up to 14.5dB @ HBR2 M: LLEQ, compensate channel loss up to 8.5dB @ HBR2

INy_AEQ# = Automatic EQ disable L: Automatic EQ enable (default) H: Automatic EQ disable

PI0 = Auto test enable L: Auto test disable & input offset cancellation enable (default) H: Auto test enable & input offset cancellation enable M: Auto test disable & input offset cancellation disable

PC0 = AUX interception disable L: AUX interception enable, driver configuration is set by link training (default) H: AUX interception disable, driver output with fixed 800mV and 0dB M: AUX interception disable, driver output with fixed 400mV and 0dB

PC1 = Output swing adjustment L: default H: +20% M: -16.7%

CA_DET

OUT2_D2p OUT2_D2n

OUT_HPD

SW4_DP_AUXP

32

SW4_DP_AUXN

31

53

DP2_MUX_PI0

56

PI0

DP2_MUX_PC0

38

PC0

DP2_MUX_PC1

55

PC1

MID1_CA_DET

48

46 45 43 42 40 39 37 36

DP1_GPU_SEL#

54

SW

SW4_DP_HPD

44

DP2_MUX_REXT

34

REXT

DP2_MUX_CEXT

47

CEXT

8

GND

18

GND

33

GND

41

GND

57

GND

61

Epad

50

PD

SW4_DP_AUXP <44> SW4_DP_AUXN <4 4>

MID1_CA_DET <32 ,44>

SW4_DP_P0 <44> SW4_DP_N0 <44> SW4_DP_P1 <44> SW4_DP_N1 <44> SW4_DP_P2 <44> SW4_DP_N2 <44> SW4_DP_P3 <44> SW4_DP_N3 <44>

DP1_GPU_SEL# <4 5>

SW4_DP_HPD <44>

R97

4.99K_0402_1%

1 2

TBT/HDMI

TBT/HDMITBT/HDMI

DP1_GPU_SEL#; 0: MXM ; 1: i-GPU

SW Input

H IN2

IN1L(Default)

11/11

DP2_MUX_PC0

DP2_MUX_PC1

DP2_MUX_IN1_AEQ#

DP2_MUX_IN2_AEQ#

DP2_MUX_IN1_PEQ

DP2_MUX_IN2_PEQ

DP2_MUX_PI0

SW4_DP_AUXN

DP2_MUX_CEXT

DP2_MUX_PI0

DP2_MUX_PC0

DP2_MUX_PC1

DP2_MUX_IN1_PEQ

DP2_MUX_IN2_PEQ

1 2

R102 4.7K_0402_5%@

1 2

R104 4.7K_0402_5%@

1 2

R149 4.7K_0402_5%@

R151 4.7K_0402_5%@

1 2

R125 4.7K_0402_5%@

1 2

R126 4.7K_0402_5%@

1 2

R152 4.7K_0402_5%@

1 2

R381 100K_0402_5%

C99 2.2U_0402_6.3V6M

R148 4.7K_0402_5%@

1 2

R128 4.7K_0402_5%@

1 2

R150 4.7K_0402_5%@

1 2

R146 4.7K_0402_5%@

1 2

R147 4.7K_0402_5%@

+3.3V_RUN

12

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPE CIFICATIONS CONTAINS CONFIDENT IAL TRADE SECRET AND OTHER PROPRI ETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NO T BE TRANSFERRED OR COPIED WITH OUT THE EXPRESS WRITTEN AUTHOR IZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE IN FORMATION IT CONTAINS WAY BE U SED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

VGA CONN

LA-C551P

1

34 74Tuesday, August 18, 2015

1.0

5

4

3

2

1

+3.3V_LAN

R545 10K_0402_5%@

R546 10K_0402_5%@

+3.3V_LAN

PM_LANPHY_ENABLE<23>

Layout Notice : Place

Layout Notice : PlaceLayout Notice : Place

bead as close PI3L720

bead as close PI3L720bead as close PI3L720

as possible

as possibleas possible

R559 4.7K_0402_5%@

22P_0402_50V8J

D D

C C

B B

A A

1 2

C470

LAN_MDIN3

LAN_MDIN2

LAN_MDIN1

LAN_MDIP1

XTALO_R

1

2

FROM

FROMFROM NIC

NIC

NICNIC

R555 0_0402_5%@

5

TP_LAN_JTAG_TMS

TP_LAN_JTAG_TCK

LAN_WAKE#_R

12

1 2

R1144 0_040 2_5%@

Y3

25MHZ_18PF_X3G0250 00DI1H-H

3

OUT

4

GND

1 2

R63 0_0603_5 %

1 2

R64 0_0603_5 %

1 2

R65 0_0603_5 %

1 2

R66 0_0603_5 %

1 2

R67 0_0603_5 %

1 2

R68 0_0603_5 %

1 2

R69 0_0603_5 %

1 2

R70 0_0603_5 %

DOCKED<45>

DOCKED

DOCKEDFROM

DOCKEDDOCKED

1

IN

2

+3.3V_LAN

LOM_ACTLED_YEL# LOM_SPD100LED_ORG # LOM_SPD10LED_GRN #

1: TO DOCK

1: TO DOCK1: TO DOCK

0: TO RJ45

0: TO RJ450: TO RJ45

+3.3V_LAN

12

0.1U_0402_25V6K

1

2

10K_0402_5%

@

R549

LAN_DISABLE#_R

10K_0402_5%

@

R557

1

2

1

C472

2

XTALO

XTALI

27P_0402_50V8J

C471

0.1U_0402_25V6K

C473

LAN_MDIN3_L

LAN_MDIP3_LLAN_ MDIP3

LAN_MDIN2_L

LAN_MDIP2_LLAN_ MDIP2

LAN_MDIN1_L

LAN_MDIP1_L

LAN_MDIN0_LLAN_MDIN 0

LAN_MDIP0_LLAN_ MDIP0

0.1U_0402_25V6K

1

C474

2

CLKREQ_PCIE#3<21> PLTRST_LAN#<22>

CLK_PCIE_P3<21> CLK_PCIE_N3<21>

PCIE_PRX_DTX_P4<20>

PCIE_PRX_DTX_N4<20>

PCIE_PTX_DRX_P4<20>

PCIE_PTX_DRX_N4<20>

SML0_SMBCLK<23>

SML0_SMBDATA<23 >

SMBus Device Ad dress 0xC8

LAN_WAKE#<23,46>

LAN ANALOG

LAN ANALOGLAN ANALOG

SWITCH

SWITCHSWITCH

39

U32

2

A0+

3

A0-

6

A1+

7

A1-

9

A2+

10

A2-

11

A3+

12

A3-

13

SEL

15

LEDA0

16

LEDA1

42

LEDA2

5

PD

43

PAD_GND

PI3L720ZHEX_TQFN42_9 X3P5~D

PN change from SA00003B20L to SA00003B200

38

B0+

VDD1VDD4VDD8VDD14VDD21VDD30VDD

37

B0-

34

B1+

33

B1-

29

B2+

28

B2-

25

B3+

24

B3-

17

LEDB0

18

LEDB1

41

LEDB2

36

C0+

35

C0-

32

C1+

31

C1-

27

C2+

26

C2-

23

C3+

22

C3-

19

LEDC0

20

LEDC1

40

LEDC2

4

R556 0_0402_5%@

LAN_DISABLE#_R<45>

T142 PAD~D@ T143 PAD~D@

CLK_PCIE_P3 CLK_PCIE_N3

PCIE_PRX_C_DTX_P4

12

C458 0.1U_040 2_10V7K

PCIE_PRX_C_DTX_N4

12

C459 0.1U_040 2_10V7K

PCIE_PTX_C_DRX_P4

1 2

C460 0.1U_040 2_10V7K

PCIE_PTX_C_DRX_N4

1 2

C461 0.1U_040 2_10V7K

1 2

LAN_DISABLE#_R

LOM_ACTLED_YEL# LOM_SPD100LED_ORG # LOM_SPD10LED_GRN #

TP_LAN_JTAG_TDI TP_LAN_JTAG_TDO TP_LAN_JTAG_TMS TP_LAN_JTAG_TCK

LAN_TEST_EN

RES_BIAS

3.01K_0402_1%

1K_0402_1%

12

R562

R561

SW1_LAN0_MDIN3 SW1_LAN0_MDIP3

SW1_LAN0_MDIN2 SW1_LAN0_MDIP2

SW1_LAN0_MDIN1 SW1_LAN0_MDIP1

SW1_LAN0_MDIN0 SW1_LAN0_MDIP0

LAN_ACTLED_YEL# LED_100_ORG# LED_10_GRN#

SW1_LAN1_MDIN3 SW1_LAN1_MDIP3

SW1_LAN1_MDIN2 SW1_LAN1_MDIP2

SW1_LAN1_MDIN1 SW1_LAN1_MDIP1

SW1_LAN1_MDIN0 SW1_LAN1_MDIP0

DOCK_LOM_ACTLED_YEL# DOCK_LOM_SPD100LED _ORG# DOCK_LOM_SPD10LED_ GRN#

U31

48

CLK_REQ_N

36

PE_RST_N

44

PE_CLKP

45

PE_CLKN

38

PETp

39

PETn

41

PERp

42

PERn

28

SMB_CLK

31

SMB_DATA

LAN_WAKE#_R

2

LANWAKE_N

3

LAN_DISABLE_N

26

LED0

27

LED1

25

LED2

32

JTAG_TDI

34

JTAG_TDO

33

JTAG_TMS

35

JTAG_TCK

9

XTALO

XTAL_OUT

10

XTALI

XTAL_IN

30

TEST_EN

12

RBIAS

WGI219LM-QREF-A0 _QFN48_6X6

PN change to SA000081G1L

SW1_LAN0_MDIN3 <36> SW1_LAN0_MDIP3 <36>

SW1_LAN0_MDIN2 <36> SW1_LAN0_MDIP2 <36>

SW1_LAN0_MDIN1 <36> SW1_LAN0_MDIP1 <36>

SW1_LAN0_MDIN0 <36> SW1_LAN0_MDIP0 <36>

SW1_LAN1_MDIN3 <43> SW1_LAN1_MDIP3 <43>

SW1_LAN1_MDIN2 <43> SW1_LAN1_MDIP2 <43>

SW1_LAN1_MDIN1 <43> SW1_LAN1_MDIP1 <43>

SW1_LAN1_MDIN0 <43> SW1_LAN1_MDIP0 <43>

DOCK_LOM_ACTLED_YEL# <43> DOCK_LOM_SPD100LED _ORG# <43> DOCK_LOM_SPD10LED_ GRN# <43>

JTAG LED

MDI

PCIE

RSVD1_VCC3P3

SMBUS

MDI_PLUS0

MDI_MINUS0

MDI_PLUS1

MDI_MINUS1

MDI_PLUS2

MDI_MINUS2

MDI_PLUS3

MDI_MINUS3

SVR_EN_N

VDD3P3_IN

VDD3P3_4

VDD3P3_15 VDD3P3_19 VDD3P3_29

VDD0P9_47 VDD0P9_46 VDD0P9_37

VDD0P9_43

VDD0P9_11

VDD0P9_40 VDD0P9_22 VDD0P9_16

VDD0P9_8

CTRL0P9

VSS_EPAD

3

TO

TO TO DOCK

DOCK

DOCKDOCK

13 14

17 18

20 21

23 24

VCT_LAN_R1

6

+RSVD_VCC3P3_2

1

5

4

15 19 29

47 46 37

43

11

40 22 16 8

+REGCTL_PNP10

7

49

LAN_MDIP0 LAN_MDIN0

LAN_MDIP1 LAN_MDIN1

LAN_MDIP2 LAN_MDIN2

LAN_MDIP3 LAN_MDIN3

1 2

R558 0_0402_5%@

12

R553 4.7K_0402_5%@

12

R554 4.7K_0402_5%

+3.3V_LAN_OUT

+0.9V_LAN

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPE CIFICATIONS CONTAINS CONFIDENT IAL TRADE SECRET AND OTHER PROPRI ETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NO T BE TRANSFERRED OR COPIED WITH OUT THE EXPRESS WRITTEN AUTHOR IZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE IN FORMATION IT CONTAINS WAY BE U SED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

R209@ 0_0603_1%

1 2

1U_0603_10V7K

1

C464

2

DMN66D0LDW -7_SOT363-6

LAN_ACTLED_YEL#

12

R377 1M_0402_5%

DMN66D0LDW -7_SOT363-6

LED_100_ORG# LED_10_GRN#

Q325A

Q325B

4

+3.3V_LAN

2

SYS_LED_MASK#

5

SYS_LED_MASK#

+REGCTL_PNP10

+3.3V_LAN

+0.9V_LAN

61

LAN_ACTLED_YEL#_Q <36>

SYS_LED_MASK# <45,47>

3

LED_100_ORG#_Q <36> LED_10_GRN#_Q <36>

2

L29

1 2

4.7UH_BRC2012T4 R7MD_20%

Idc

IdcIdc

min=500mA

min=500mAmin=500mA

DCR=100m

DCR=100mDCR=100m

ohm

ohmohm

Place C462, C463 and L29 close

Place C462, C463 and L29 closePlace C462, C463 and L29 close to U31

to U31

to U31to U31

0.1U_0402_10V7K

1

2

Note: +1.0V_LAN will work at 0.95V to

Note: +1.0V_LAN will work at 0.95V toNote: +1.0V_LAN will work at 0.95V to

1.15V

1.15V1.15V

0.1U_0402_10V7K

1

C466

2

C467

1

C468

2

+3.3V_LAN+3.3V_LAN

1

2

LOM_SPD100LED_ORG #

LOM_SPD10LED_GRN #

12

R378 1M_0402_5%

+0.9V_LAN

0.1U_0402_10V7K

10U_0603_6.3V6M

C463

C462

1

2

+3.3V_LAN

22U_0805_6.3V6M

0.1U_0402_10V7K

C1177

1

C469

2

22U_0805_6.3V6M

0.1U_0402_10V7K

C1178

1

C1418

2

Place C1178 close to

Place C1178 close toPlace C1178 close to pin5

pin5

pin5pin5

+3.3V_LAN

C478

@

1 2

0.1U_0402_10V7K

U15

5

SN74AHC1G08DCKR _SC70-5

1

P

IN1

4

O

2

IN2

G

3

Q327 DMN65D8LW- 7_SOT323-3

D

S

13

G

2

SYS_LED_MASK#

WLAN_DISBL# <45>

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

LAN/LAN SW

LA-C551P

1

1.0

35 74Tuesday, August 18, 2015

1.0

5

4

3

2

1

+3.3V_LAN/+3.3V_LAN_LOM:20mils

D D

+3.3V_LA N

LAN_ACTLE D_YEL#_Q<35>

DVT1 change from SP050006P00 to SP050006Y00

T156

SW1_L AN0_MDIP0<35>

C C

0.47U_0603_10V7K

C479

1

2

B B

0.47U_0603_10V7K

1

C484

2

A A

+TRM_CT1

+TRM_CT2

0.47U_0603_10V7K

C480

1

2

+TRM_CT3

+TRM_CT4

0.47U_0603_10V7K

1

C486

2

SW1_L AN0_MDIN0<35>

SW1_L AN0_MDIP1<35>

SW1_L AN0_MDIN1<35>

SW1_L AN0_MDIP2<35>

SW1_L AN0_MDIN2<35>

SW1_L AN0_MDIP3<35>

SW1_L AN0_MDIN3<35>

SW1_L AN0_MDIP0

SW1_L AN0_MDIN0

SW1_L AN0_MDIP1

SW1_L AN0_MDIN1

SW1_L AN0_MDIP2

SW1_L AN0_MDIN2

SW1_L AN0_MDIP3

SW1_L AN0_MDIN3

1

TD1+

2

TD1-

3

TDCT1

4

TDCT2

5

TD2+

6

TD2-

7

TD3+

8

TD3-

9

TDCT3

10

TDCT4

11

TD4+

12

TD4-

350uH_IH -115-F

1:1

TXCT1

TXCT2

1:1

TXCT3

TXCT4

1:1

TX1+

TX2+

TX3+

TX4+

RJ45_MDIP 0

24

RJ45_MDIN0

23

TX1-

22

Z2805

21

Z2807 RJ45_MDIP 1

20

RJ45_MDIN1

19

TX2-

RJ45_MDIP 2

18

RJ45_MDIN2

17

TX3-

16

Z2806

15

Z2808 RJ45_MDIP 3

14

RJ45_MDIN3

13

TX4-

GND_CHASS IS

1 2

C485 150P_ 1808_2.5K V8JEMC@

12

R574 75_0402_1%

R572 75_0402_1%12R573 75_0402_1%

R571 75_0402_1%

LED_10_ GRN#_Q< 35>

LED_100 _ORG#_Q<35>

GND CHASSIS

PROPRIETARY NOTE: THIS SHEET O F ENGINEERING DRAWING AND SPEC IFICATIONS CONTAINS CONFIDENTI AL TRADE SECRET AND OTHER PROPRIE TARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHO UT THE EXPRESS WRITTEN AUTHORI ZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS WAY BE US ED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT DELL'S EXPRESS W RITTEN CONSENT.

5

4

3

2

1 2

R1171 150_ 0402_5%

RJ45_MDIN3

RJ45_MDIP 3

RJ45_MDIN1

RJ45_MDIN2

RJ45_MDIP 2

RJ45_MDIP 1

RJ45_MDIN0

RJ45_MDIP 0

1 2

R1170 150_ 0402_5%

1 2

R1167 150_ 0402_5%

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Nu mber Rev

Date: Sheet of

+3.3V_LA N

JLOM1

13

Yellow_LED-

12

Yellow_LED+

8

PR4-

7

PR4+

6

PR2-

5

PR3-

4

PR3+

3

PR2+

2

PR1-

PR1+

Green_LED-

LED+

ORANGE_LED-

LInk

LInkLInk CIS

CIS

CISCIS

470P_0402_50V7K

1

C1167

2

SHLD2

SHLD1

1

10

9

11

SANTA_130 454-3

CONN@

0.1U_0402_10V7K

1U_0603_10V6K

1

C483

C481

2

Close to JLOM1

Compal Electronics, Inc.

RJ45

LA-C551P

1

15

14

1.0

36 74Tuesday, Au gust 18, 20 15

1.0

5

4

3

2

1

D D

C C

B B

33_0402_5%

1 2

12

power rail option: TPM power rail must same as +3.3V_SPI (SPI ROM)

+3.3V_M

12

RZ75 0_ 0603_5%@

PCH_SPI_D1<22>

PCH_SPI_D0<7,22>

PCH_SPI_CLK<22>

PCH_SPI_CS#2<22>

SPI_CLKTP M

@EMC@

RZ35

0.1U_0402_25V6

@EMC@

CZ9

+3.3V_AL W_PCH

+3.3V_M_TPM

SIO_SLP_S0#<11,23,37>

+3.3V_RUN

RZ30 3 3_0402_5% RZ29 3 3_0402_5%

RZ26 3 3_0402_5% RZ17 0 _0402_5%

PJP@

PJP2

1 2

PAD-OPEN1 x1m

TPM_PIRQ#

1 2

RZ69 10K_04 02_5%

SIO_SLP _S0#

1 2

RZ111 0_0402_ 5%

1 2

RZ90 10K_040 2_5%@

1 2 1 2

TPM_PIRQ#<22>

1 2 1 2

PLTRST_TPM#<22>

PCH_SPI_CS#2_R

RZ112 100_04 02_5%

RZ112 RZ82 POP

1K MMBT3 9061K

+3.3V_M_TPM

TPM_LPM#

SPI_DINTPM SPI_DOTPM TPM_PIRQ#

SPI_CLKTP M PCH_SPI_ CS#2_R

TPM_GPIO4

10K_0402_5%

12

RZ20

1 2

12/3

U637

29

GPIO0/SDA/XOR_OUT

30

GPIO1/SCL

3

GPIO2/GPX

6

GPIO3/BADD

24

LAD0/MISO

21

LAD1/MOSI

18

LAD2/SPI_IRQ#

15

LAD3

19

LCKL/SCLK

20

LFRAME#/SCS#

17

LRESET#/SPI_RST#/SRESET#

27

SERIRQ

13

CLKRUN#/GPIO4/SINT#

28

LPCPD#

4

PP

5

TEST

NPCT650JAA YX_QFN32_5X 5

PN change to 1.2(SA00008EL20)

+3.3V_M_TPM

S

3

G

2

D

1

+3.3V_M_TP M

+3.3V_RUN

LP2301A LT1G_SOT23-3

QZ2

TPM_LPM#

12

VSB

VDD VDD VDD

NC NC NC NC NC NC NC

GND GND GND GND

PGND

Reserved

RZ82

10K_040 2_5%

1 2

RZ88 0 _0402_5%@

1 2

RZ89 0 _0402_5%

+3.3V_AL W

1

+U637_TPM

8 14 22

2 7 10 11 25 26 31

9 16 23 32 33 12

1 2

RZ110 0_0402 _5%@

USH_PWR_STATE#

1 2

RZ10 1 M_0402_5%

DZ3

2 1

RZ72 0_ 0402_5%@

RZ76 0_ 0402_5%@

CONTACTLESS_DET#<19 > USH_PWR_STATE#<45 >

1 2

BCM5882_ALERT#<45>

PLTRST_USH#

1

2

RB751S4 0T1G_SOD523 -2

PLTRST_USH#<22>

+5V_RUN

+3.3V_RUN

+5V_ALW

+3.3V_ALW

USH_SMBDAT<28,46> USH_SMBCLK<28,4 6>

USB20_P10<2 0> USB20_N10<20>

EC_FPM_EN<4 6> POA_WAKE#<46>

CV2_ON<46>

0.047U_0402_16V4Z

CZ57

ESD request

+5V_ALW 2_R

+3.3V_AL W2_R +PWR_S RC_R

+U637_TPM

0.1U_0402_25V6

1

CZ4

+3.3V_M_TPM

0.1U_0402_25V6

1

CZ5

2

10U_0603_25V6M

0.1U_0402_25V6

1

CZ8

CZ7

2

0.1U_0402_25V6

10U_0603_25V6M

1

CZ6

CZ15

2

0.1U_0402_25V6

CZ10

12

Close to JUSH1

+3.3V_ALW+3.3V_RUN+5V_RUN

0.1U_0402_25V6

@

CZ11

12

0.1U_0402_25V6

12

+3.3V_ALW2 +PWR_SRC

USH_DET#<45>

+5V_ALW2

@

CZ12

1 2

RZ70 0 _0402_5%@

1 2

RZ73 0 _0402_5%@

Check ME about wire to board PN

+3.3V_AL W_PCH

SIO_SLP _S3#<7,11 ,23,44,46>

+3.3V_AL W

SIO_SLP _S5#<23,44,46> SIO_SLP _S4#<11,2 3,46,52,54 >

TPM_GPIO4PCH_SPI_CS# 2_R

SIO_SLP _A#<2 3,46,49>

+3.3V_AL W

PCH_RTCRST#<23>

POWER_ SW#_MB<44,46>

SYS_RESE T#<20,23 >

SIO_SLP _S0#<11,23,37>

Intel Management Engine Test Suite

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20

ACES_50 506-01841-P 01

USH_DET#_R

JAPS1

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 GND GND

CONN@

JUSH1

1

2

2 2

3

4

4 4

5

6

6 6

7

8

8 8

9

10

10 10

11

12

12 12

13

14

14 14

15

16

16 16

17

18

18 18

19

20

20 20

21

22

22 22

23

24

24 24

25

26

26 26

27

G1

28

G2

29

G3

30

G4

ACES_50 559-02601-0 01

CONN@

CIS link OK

CIS link OKCIS link OK

LP2301A10K100

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINSPROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL

CONFIDENTIAL

CONFIDENTIAL CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS

TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS

TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THISTRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

DOCUMENT MAY NOT

DOCUMENT MAY NOTDOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. INBE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,

ADDITION,

ADDITION,ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO

NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO

5

4

NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TONEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO

3

ANY THIRD

ANY THIRDANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

2

Title

Size Document Nu mber Rev

Date: Sheet of

Compal Electronics, Inc.

TPM/USH

LA-C551P

37 74Tuesday, Aug ust 18, 201 5

1

1.0

5

4

WLAN/BT/WiGig

WLAN/BT/WiGigWLAN/BT/WiGig

3

2

1

NGFF slot_1 Key A

JNGFF1

1

+3.3V_W LAN

3 5 7

67

69

BELLW _80148 -4221

0.047U_0402_16V4Z

0.1U_0402_25V6K

@

1

C603

2

1 2

RZ77 0_ 0402_5 %@ EMC@

1 2

RZ71 0_ 0402_5 %@ EMC@

11/17 RF request

LI2EMC@

2

3

DLW21HN900HQ2L_4P

LI3EMC@

2

3

DLW21HN900HQ2L_4P

1 2

RZ78 0_ 0402_5 %@ EMC@

1 2

RZ74 0_ 0402_5 %@ EMC@

3 5 7

9910 111112 131314 151516 171718 191920 212122 232324 252526 272728 292930 313132 333334 353536 373738 393940 414142 434344 454546 474748 494950 515152 535354 555556 575758 595960 616162 636364 656566 67

GND

Need update

Need updateNeed update

C604

4

1 2

CZ3 0.1U_0402 _10V7K

1 2

CZ58 0.1U_ 0402_1 0V7K

PCIE_PRX_DTX_P2<20> PCIE_PRX_DTX_N2<20>

CLK_PCIE_P6<21> CLK_PCIE_N6<21>

CLKREQ_PCIE#6<21> PCIE_WAKE#<1 8,39,44,45>

USB3_PR X_DTX_ N2<23>

USB3_PR X_DTX_ P2<23>

1 2

33P_0402_50V8J

EMC@

22U_0603_6.3V6M

EMC@

1

12

+

C612

C614

C613

2

USB20_P6<20 > USB20_N6<20>

USB3_PR X_DTX_ N2

USB3_PR X_DTX_ P2

USB3_PT X_C_DR X_N2

USB3_PT X_C_DR X_P2

330U_D2E_6.3VM_R25M

EMC@

1

+

C615

2

PCIE_PTX_C_DRX_P 2

PCIE_PTX_C_DRX_N2

330U_D2E_6.3VM_R25M

@

C1176

PCIE_W AKE#

D D

PCIE_PTX_DRX_P2<20> PCIE_PTX_DRX_N2<20>

C C

+3.3V_WWAN

B B

A A

WWAN_PWR_EN

1 2

RZ3 0_0402_5%@

USB3_PT X_DRX_ N2

USB3_PT X_DRX_ P2

0.047U_0402_16V4Z

EMC@

1

C610

2

CZ91 0.1U_ 0402_1 0V7K

CZ92 0.1U_ 0402_1 0V7K

33P_0402_50V8J

EMC@

1

C611

2

C613 change to 0603 due to height limitation.

5

USB3_PT X_DRX_ N2<23>

USB3_PT X_DRX_ P2<23>

+3.3V_W WAN

C615 footprint change to C_APXK2R5ARA331MF451

+3.3V_WLAN

CONN@

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42

PCH_PLT RST#_E C

44

BT_RADIO_DIS#_R

46

WLAN_WIGIG60GHZ_ DIS#_R

48 50 52 54 56 58 60 62 64 66

68

GND

0.1U_0402_25V6K

2

C606

1

USB3_PR X_L_DT X_N2

USB3_PR X_L_DT X_P2

USB3_PT X_L_DR X_N2

USB3_PT X_L_DR X_P2

330U_D2E_6.3VM_R25M

4.7U_0603_6.3V6K

1

+

C608

C607

2

PCIE_PTX_DRX_N13<19> PCIE_PTX_DRX_P1 3<19>

0.1U_0402_25V6K

0.047U_0402_16V4Z

2

1

C605

1

2

1

443

1

443

@

C1402

CZ1 0 .1U_040 2_10V7 K CZ2 0 .1U_040 2_10V7 K

10/23

PCH_CL_RST1# <19>

PCH_CL_DATA1 <19>

PCH_CL_CLK1 <19>

SUSCLK <23,38,39> PCH_PLTRST#_EC <22,39,45,46>

WLAN_W IGIG6 0GHZ_D IS#_R

BT_RAD IO_DIS #_R

WWAN/LTE/HCA/Cache

WWAN/LTE/HCA/CacheWWAN/LTE/HCA/Cache

NGFF slot_2 Key B

SLOT2_CONFIG_3<45>

USB20_P8<20 > USB20_N8<20>

SLOT2_CONFIG_0<45>

WWAN_WAKE#<45>

USB3_PR X_L_DT X_N2 USB3_PR X_L_DT X_P2

USB3_PT X_L_DR X_N2

SLOT2_CONFIG_1<45>

SLOT2_CONFIG_2<45>

0

8

USB3_PT X_L_DR X_P2

PCIE_P TX_C_D RX_N13 PCIE_PTX_C_DRX_P 13

CONFIG_0

0

1

3

PCIE_PRX_DTX_P1 3<19>

PCIE_PRX_DTX_N13<19>

1 2 1 2

CLK_PCIE_N2<21> CLK_PCIE_P2<21>

STATE #

14

12

WLAN_W IGIG6 0GHZ_D IS# <45>

D31RB75 1S40T 1G_SOD 523-2

12

BT_RAD IO_DIS # <45>

D36RB75 1S40T 1G_SOD 523-2

WWAN_RADIO_DIS #_R

11

67

69

CONFIG_1

0

JNGFF2

1

3

5

7

7 9910 11

13 151516 171718 191920 212122 232324 252526 272728 292930 313132 333334 353536 373738 393940 414142 434344 454546 474748 494950 515152 535354 555556 575758 595960 616162 636364 656566 67

GND

BELLW _80149 -4221

CONN@

2 4 6 8

12 14

GND

CIS link OK

CIS link OKCIS link OK Net on platform

Net on platform

Net on platformNet on platform

CONFIG_2

0

1

2 4 6 8 10

12

16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66

68

+3.3V_WWAN

WWAN_PWR_EN WWAN_RADIO_DIS #_R

HW_GPS_DISABLE#_ R

PCH_PLT RST#_E C

CONFIG_3

UIM_RESET UIM_CLK UIM_DATA

PCIE_W AKE#

0

1

SIM_DET

HW_GPS_DISABLE#_ R

10/23

+SIM_PWR

CLKREQ_PCIE#2 <21>

SUSCLK <23,38,39>

Module Type

SSD-SATA

WWAN

HCA-PCIE

1 Cache15 1 11

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

2

12

DZ1

RB751S 40T1G_ SOD52 3-2

DZ2

RB751S 40T1G_ SOD52 3-2

SIM Card Push-Push

JSIM1

2

NC

UIM_DATA

I/O

6

VPP

8

GND

10

NC

12

GND

14

GND

16

GND

18

GND

T-SOL_1 59-1000 30260 2

CONN@

CIS link

CIS linkCIS link OK

OK

OKOK

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Numbe r Rev

Date: Sheet of

WWAN_RADIO_DIS # <45>

12

HW_GPS_DISABLE# <45>

1

1 2

DETECT

RZ113 0_0402 _5%

NC

UIM_CLK

5

CLK

UIM_RESET

7

RST

9

VCC

11

GND

13

GND

15

GND

17

GND

UIM_RESE T

UIM_CLK

UIM_DATA

For RF Team request

33P_0402_50V8J

@EMC@

1

CZ65

2

Compal Electronics, Inc.

M.2 Card-1/2

LA-C551P

1

SIM_DET

+SIM_PWR

1U_0402_6.3V6K

12

C1356

33P_0402_50V8J

@EMC@

1

CZ67

CZ66

2

38 74Tuesday, Aug ust 18, 20 15

1.0

5

4

SSD

SSDSSD

3

2

1

NGFF slot_3 Key M

JNGFF3

10/24

PCIE_PTX_DRX_N12<19>

D D

+3.3V_RUN

10K_0402_5%

R363

1 2

M2_SLOT3_PEDET<19>

C C

1 2

R372 0_04 02_5%@

DMN65D8LW-7_SOT323-3

13

D

@

2

QN5

G

S

PCIE_PTX_DRX_P12<19>

PCIE_PTX_DRX_N11<19> PCIE_PTX_DRX_P11<19>

PCIE_PTX_DRX_N10<19> PCIE_PTX_DRX_P10<19>

PCIE_PTX_DRX_N9<19> PCIE_PTX_DRX_P9<19>

PEDET3

@

12

R364

20K_0402_5%

PCIE_PRX_DTX_N12<19> PCIE_PRX_DTX_P12<19>

PCIE_PRX_DTX_N11<19> PCIE_PRX_DTX_P11<19>

PCIE_PRX_DTX_N10<19> PCIE_PRX_DTX_P10<19>

PCIE_PRX_DTX_P9<19> PCIE_PRX_DTX_N9<19>

PEDET Module Type

0

1 2 1 2

CLK_PCIE_N7<21> CLK_PCIE_P7<21>

SATA

PCIE_PRX_DTX_N12 PCIE_PRX_DTX_P12

PCIE_PTX_C_DRX_N12

CN950 .22U_0402_10V6K

PCIE_PTX_C_DRX_P12

CN970 .22U_0402_10V6K

PCIE_PRX_DTX_N11 PCIE_PRX_DTX_P11

PCIE_PTX_C_DRX_N11

CN910 .22U_0402_10V6K

PCIE_PTX_C_DRX_P11

CN920 .22U_0402_10V6K

PCIE_PRX_DTX_N10 PCIE_PRX_DTX_P10

PCIE_PTX_C_DRX_N10

CN880 .22U_0402_10V6K

PCIE_PTX_C_DRX_P10

CN870 .22U_0402_10V6K

PCIE_PRX_DTX_P9 PCIE_PRX_DTX_N9

PCIE_PTX_C_DRX_N9

CN850 .22U_0402_10V6K

PCIE_PTX_C_DRX_P9

CN830 .22U_0402_10V6K

PEDET3

CONN@

1

GND

3

GND

5

PERn3

7

PERp3

9

GND

11

PETn3

13

PETp3

15

GND

17

PERn2

19

PERp2

21

GND

23

PETn2

25

PETp2

27

GND

29

PERn1

31

PERp1

33

GND

35

PETn1

37

PETp1

39

GND

41

PERn0/SATA-B+

43

PERp0/SATA-B-

45

GND

47

PETn0/SATA-A-

49

PETp0/SATA-A+

51

GND

53

REFCLKN

55

REFCLKP

57

GND

59

NC PEDET(NC-PCIE/GND-SATA)613P3VAUX

63

GND

65

GND

67

GND

BELLW_SD-80159-4221

Net name on Platform

Net name on PlatformNet name on Platform Need update symbol

Need update symbol

Need update symbolNeed update symbol

DAS/DSS#

CLKREQ#

SUSCLK(32kHz)

PCIE1

SSD

SSDSSD

3P3VAUX 3P3VAUX

3P3VAUX 3P3VAUX 3P3VAUX 3P3VAUX

DEVSLP

PERST#

PEWake#

3P3VAUX 3P3VAUX

GND1 GND2

+3.3V_SSD1

2 4 6

NC

8

NC

10 12 14 16 18 20

NC

22

NC

24

NC

26

NC

28

NC

30

NC

32

NC

34

NC

36

NC

38 40

NC

42

NC

44

NC

46

NC

48

NC

50 52 54 56

NC

58

NC

60 62 64 66

68 69

SLOT3_SATA_LED# <47>

PCIE_WAKE# <18,38,39,44,45>

SUSCLK_R

1 2

R360 0_0402_5%

PCH_PLTRST#_EC <22,38,39,45,46>

CLKREQ_PCIE#7 <21>

SUSCLK

SUSCLK <23,38>

+3.3V_SSD1

0.047U_0402_16V4Z

33P_0402_50V8J

1

C623

C621

2

C618

2

330U_D2E_6.3VM_R25M

33P_0402_50V8J

22U_0805_6.3VAM

1

C619

1

+

C617

C622

2

NGFF slot_4 Key M

DEVSLP

PERST#

+3.3V_SSD2

2 4 6

NC

8

NC

10 12 14 16 18 20

NC

22

NC

24

NC

26

NC

28

NC

30

NC

32

NC

34

NC

36

NC

38 40

NC

42

NC

44

NC

46

NC

48

NC

50 52 54 56

NC

58

NC

60 62 64 66

68

GND1

69

GND2

SLOT4_SATA_LED# <47>

CLKREQ_PCIE#8 <21> PCIE_WAKE# <18,38,39,44,45>

SUSCLK_R

1 2

R3756 0_0402_5%

PCH_PLTRST#_EC <22,38,39,45,46>

SUSCLK

+3.3V_SSD2

0.047U_0402_16V4Z

33P_0402_50V8J

1

C1440

C1422

C1441

2

330U_D2E_6.3VM_R25M

22U_0805_6.3VAM

33P_0402_50V8J

@

1

2

C1442

1

+

C1439

C1443

2

JNGFF4

CONN@

1

GND

3

10/24

PCIE_PTX_DRX_N20<19> PCIE_PTX_DRX_P20<19>

PCIE_PTX_DRX_N19<19> PCIE_PTX_DRX_P19<19>

B B

+3.3V_RUN

10K_0402_5%

R3742

1 2

M2_SLOT4_PEDET<19>

1 2

R3751 0_0402_5%@

DMN65D8LW-7_SOT323-3

13

D

@

2

QN6

G

S

PCIE_PTX_DRX_N18<19> PCIE_PTX_DRX_P18<19>

PCIE_PTX_DRX_N17<19> PCIE_PTX_DRX_P17<19>

PEDET4

@

12

R3743

20K_0402_5%

PEDET

PCIE_PRX_DTX_N20<19> PCIE_PRX_DTX_P20<19>

PCIE_PRX_DTX_N19<19> PCIE_PRX_DTX_P19<19>

PCIE_PRX_DTX_N18<19> PCIE_PRX_DTX_P18<19>

PCIE_PRX_DTX_P17<19> PCIE_PRX_DTX_N17<19>

0

1

A A

PCIE_PRX_DTX_N20 PCIE_PRX_DTX_P20

PCIE_PTX_C_DRX_N20

CN1130.22U_040 2_10V6K

1 2

PCIE_PTX_C_DRX_P20

CN1120.22U_040 2_10V6K

1 2

PCIE_PRX_DTX_N19 PCIE_PRX_DTX_P19

PCIE_PTX_C_DRX_N19

CN1080.22U_040 2_10V6K

1 2

PCIE_PTX_C_DRX_P19

CN1090.22U_040 2_10V6K

1 2

PCIE_PRX_DTX_N18 PCIE_PRX_DTX_P18

PCIE_PTX_C_DRX_N18

CN1030.22U_040 2_10V6K

1 2

PCIE_PTX_C_DRX_P18

CN1060.22U_040 2_10V6K

1 2

PCIE_PRX_DTX_P17 PCIE_PRX_DTX_N17

PCIE_PTX_C_DRX_N17

CN990 .22U_0402_10V6K

1 2

PCIE_PTX_C_DRX_P17

CN1020.22U_040 2_10V6K

1 2

CLK_PCIE_N8<21> CLK_PCIE_P8<21>

Module Type

SATA

PCIE

PEDET4

GND

5

PERn3

7

PERp3

9

GND

11

PETn3

13

PETp3

15

GND

17

PERn2

19

PERp2

21

GND

23

PETn2

25

PETp2

27

GND

29

PERn1

31

PERp1

33

GND

35

PETn1

37

PETp1

39

GND

41

PERn0/SATA-B+

43

PERp0/SATA-B-

45

GND

47

PETn0/SATA-A-

49

PETp0/SATA-A+

51

GND

53

REFCLKN

55

REFCLKP

57

GND

59

NC PEDET(NC-PCIE/GND-SATA)613P3VAUX

63

GND

65

GND

67

GND

BELLW_SD-80159-4221

3P3VAUX 3P3VAUX

DAS/DSS#

3P3VAUX 3P3VAUX 3P3VAUX 3P3VAUX

CLKREQ# PEWake#

SUSCLK(32kHz)

3P3VAUX 3P3VAUX

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

M.2 Card-2/2

LA-C551P

1

39 74Tuesday, August 18, 2015

1.0

5

D D

Power Control for M.2 slot 1.

Power Control for M.2 slot 1.Power Control for M.2 slot 1. & +3.3V_RUN Source

& +3.3V_RUN Source

& +3.3V_RUN Source& +3.3V_RUN Source

AUX_EN_WOWL<45>

SIO_SLP_WLAN#<23,45>

C C

R840 0_0402_5%@

R820 0_0402_5%@

1 2

AUX_EN_WOWL_R

SIO_SLP_LAN#<23,46>

100K_0402_5%

12

R723

+3.3V_ALW

+5V_ALW

+3.3V_ALW

4

UZ25

1

VIN1

2

VIN1

3

ON1

4

VBIAS

5

ON2

6

VIN2

7

VIN2

EM5209VF_DFN14_3X2

VOUT1 VOUT1

VOUT2 VOUT2

GPAD

3

+3.3V_WLAN_PWR +3.3V_WLAN

PJP10

+3.3V_WLAN_PWR

14 13

12

CT1

11

GND

10

CT2

9 8

470P_0402_50V7K

15

2

1

@

2

112

10U_0603_6.3V6M

JUMP_43X79

C536

1

2

470P_0402_50V7K

2

C538

C436

1

+3.3V_LAN_PWR +3.3V_LAN

+3.3V_LAN_PWR

@

2

JUMP_43X79

PJP11

112

3.3V_WWAN_EN<45>

2

Power Control for M.2 slot 2.

Power Control for M.2 slot 2.Power Control for M.2 slot 2.

+3.3V_ALW

UZ24

1 2

100K_0402_5%

12

R720

+5V_ALW

3

4

AOZ1336_DFN8_2X2

VIN VIN

ON

VBIAS

VOUT VOUT

1

+3.3V_WWAN

7 8

6

CT

5

GND

9

GND

10U_0603_6.3V6M

1

C762

470P_0402_50V7K

C541

1

2

Power Control for M.2 slot 3. Source

B B

A A

Power Control for M.2 slot 3. SourcePower Control for M.2 slot 3. Source Power Control for M.2 slot 4. Source

Power Control for M.2 slot 4. Source

Power Control for M.2 slot 4. SourcePower Control for M.2 slot 4. Source

UZ21

+3.3V_ALW

SLOT3_SSD_PWR_EN<45>

SLOT4_SSD_PWR_EN<45>

+5V_ALW

+3.3V_ALW

1

VIN1

2

VIN1

3

ON1

4

VBIAS

5

ON2

6

VIN2 VIN27VOUT2

EM5209VF_SON14_2X3

VOUT1 VOUT1

VOUT2

GPAD

+3.3V_SSD1_PWR +3.3V_SSD1

14 13

12

CT1

11

GND

10

CT2

9 8

15

470P_0402_50V7K

2

C476

1

PJP9

@

2

112

10U_0603_6.3V6M

JUMP_43X79

1

C400

2

C477

1

2

+3.3V_SSD2+3.3V_SSD2_PWR

PJP1

@

2

112

10U_0603_6.3V6M

JUMP_43X79

C475

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

M.2 Card PWR

LA-C551P

40 74Tuesday , August 18, 2015

1

1.0

5

4

3

2

1

+3.3V_RUN

R513

DMN66D0LDW-7_SOT363-6

Q29A

R501 10K_0402_5%

R502 10K_0402_5%

R503 100K_0402_5%

R504 100K_0402_5%

+5V_HDD

100K_0402_5%

12

3

5

4

D D

C C

+3.3V_RUN

100K_0402_5%

12

61

FFS_INT2<22>

B B

2

1 2

@

R506

FFS_INT2_QR

DMN66D0LDW-7_SOT363-6

Q29B

DDR_XDP_WAN_SMBDAT

DDR_XDP_WAN_SMBCLK

HDD_FALL_INT

FFS_INT2

+3.3V_HDD

R3753 100K_0 402_5%

1 2

CLKDET#

+3.3V_RUN

10U_0603_6.3V6M

0.1U_0402_25V6K

1

C392

C391

2

DDR_XDP_WAN_SMBDAT<7,14,15,16,17,23> DDR_XDP_WAN_SMBCLK<7,14,15,16,17,23>

PCIE_PTX_C_DRX_P16<42> PCIE_PTX_C_DRX_N16<4 2>

PCIE_PRX_C_DTX_N16<4 2> PCIE_PRX_C_DTX_P16<42>

PCIE_PTX_C_DRX_P15<42> PCIE_PTX_C_DRX_N15<4 2>

PCIE_PRX_C_DTX_N15<4 2> PCIE_PRX_C_DTX_P15<42>

CLK_PCIE_P5<21> CLK_PCIE_N5<21> CLKDET#<24> PLTRST_HDD#<22>

CLKREQ_PCIE#5<2 1>

HDD_DET#< 19>

PJP4@

1 2

+5V_RUN

PAD-OPEN1x1m

PJP5

@

+3.3V_HDD

112

JUMP_43X79

2

CLK_PCIE_P5 CLK_PCIE_N5 CLKDET#

HDD_IFDET HDD_DET#

FFS_INT2_Q

+5V_HDD

+3.3V_HDD1

HDD1 CONN

HDD1 CONNHDD1 CONN

Free Fall Sensor

Free Fall SensorFree Fall Sensor

U88

LNG2DM

10

VDD_IO

9

VDD

3

SDO/SA0

4

SDA/SDI/SDO SCL/SPC1GND

2

CS

LNG2DMTR_LGA12_2X2

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

CIS link OK

CIS link OKCIS link OK

5

RES

12

INT 1

11

INT 2

6 7

GND

8

GND

JSATA1

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

31

GND

27

32

28

GND

33

29

GND

34

30

GND

STARC_7300L30-100000-G4

HDD_FALL_INT FFS_INT2

HDD_FALL_INT <23>

+3.3V_HDD1

22U_0603_6.3V6M

0.1U_0402_25V6

1

C403

C404

2

Pleace near JSATA1 CONN

Pleace near JSATA1 CONNPleace near JSATA1 CONN

A A

+5V_HDD

0.1U_0402_25V6K

1000P_0402_50V7K

1

C406

C395

2

Pleace near JSATA1 CONN

Pleace near JSATA1 CONNPleace near JSATA1 CONN

FFS_INT2_QR

SATAE_LED#<47>

SATA_EXP_IFDET

0

1

R386 0_0402_5%@

SN74LVC1G3157DCKR_SC70-6

10U_0603_6.3V6M

C5

HDD_IFDET DEVICE interface

R317

SATA

PCIE

U6

1

NC

2

A

3

GND

74AUP1G07GW_TSSOP5

5

VCC

4

Y

0

1

HDD_IFDET

20K_0402_5%

12

11/21

+1.0V_RUN

1 2

C401 0.1U_0402_25V6K

SATA_EXP_IFDET

0

1

SATA_EXP_IFDET <19,42>

DEVICE interface

SATA

PCIE

1 2

U639

B13A

2

GND

1

B2

VCC

S

channel on

A-->B1

A-->B2

4 5

SATA_EXP_IFDET

6

+3.3V_RUN

FFS_INT2_Q

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

HDD CONN

LA-C551P

41 74Tuesday, August 18, 2015

1

1.0

5

+3.3V_RUN +3.3V_HDD

D D

C C

PJP3

@

2

112

JUMP_43X 79

PCIE_PTX_ DRX_P15<1 9> PCIE_PTX_ DRX_N15<19 >

PCIE_PRX _DTX_P15<19 > PCIE_PRX _DTX_N15<19>

1 2 1 2

1

2

+3.3V_HDD

0.1U_0402_10V6K

CN67

CN700.22U_040 2_10V6K CN630.22U_040 2_10V6K

CN690.22U_040 2_10V6K CN760.22U_040 2_10V6K

PWD

0.01U_0402_16V7K

1

2

CN75

PCIE_PTX_ C_RD_DRX_P15 PCIE_PTX_ C_RD_DRX_N15

PCIE_PRX _C_RD_DTX_P15 PCIE_PRX _C_RD_DTX_N15

EQ0_A_U N8 EQ1_A_U N8 EQ2_A_U N8

EQ0_B_U N8 EQ1_B_U N8 EQ2_B_U N8

Funtion

Normal mode(Def ault)0

1

Chip power down

+3.3V_HDD

0.1U_0402_10V6K

0.01U_0402_16V7K

1

CN73

CN71

2

B B

PCIE_PTX_ DRX_P16<1 9> PCIE_PTX_ DRX_N16<19 >

PCIE_PRX _DTX_P16<19 > PCIE_PRX _DTX_N16<19>

1 2 1 2

PCIE_PTX_ C_RD_DRX_P16

CN790.22U_040 2_10V6K

PCIE_PTX_ C_RD_DRX_N16

CN650.22U_040 2_10V6K

PCIE_PRX _C_RD_DTX_P16

CN740.22U_040 2_10V6K

PCIE_PRX _C_RD_DTX_N16

CN800.22U_040 2_10V6K

PCIE/SATA Repeater

PCIE/SATA RepeaterPCIE/SATA Repeater

EQ0_A_U N9 EQ1_A_U N9 EQ2_A_U N9

EQ0_B_U N9 EQ1_B_U N9 EQ2_B_U N9

4

PCIE/SATA Repeater

PCIE/SATA RepeaterPCIE/SATA Repeater

UN8

12

VDD_3.3

24

VDD_3.3

1

A_INP

2

A_INN

5

B_OUTP

4

B_OUTN

23

A_EQ0

22

A_EQ1

19

A_EQ2

11

B_EQ0

21

B_EQ1

16

B_EQ2

7

GND

25

EPAD

PS8558B TQFN24GTR2-A_TQFN 24_4X4

A_OUTP A_OUTN

B_INP B_INN

A_DE0 A_DE1

B_DE0 B_DE1

PWD

REXT

MODE

PCIE_PTX_ RD_DRX_P15

18

PCIE_PTX_ RD_DRX_N15

17

PCIE_PRX _RD_DTX_P15

14

PCIE_PRX _RD_DTX_N15

15

DE0_A_UN 8

6

DE1_A_UN 8

8

DE0_B_UN 8

13

DE1_B_UN 8

9

PWD_UN8

3

M_REXT_UN8

10

SATA_EXP _IFDET

20

SATA_EXP_IFDET DEVICE interface

UN9

12

VDD_3.3

24

VDD_3.3

1

A_INP

2

A_INN

5

B_OUTP

4

B_OUTN

23

A_EQ0

22

A_EQ1

19

A_EQ2

11

B_EQ0

21

B_EQ1

16

B_EQ2

7

GND

25

EPAD

PS8558B TQFN24GTR2-A_TQFN 24_4X4

A_OUTP A_OUTN

B_INP B_INN

A_DE0 A_DE1

B_DE0 B_DE1

PWD

REXT

MODE

PCIE_PTX_ RD_DRX_P16

18

PCIE_PTX_ RD_DRX_N16

17

PCIE_PRX _RD_DTX_P16

14

PCIE_PRX _RD_DTX_N16

15

DE0_A_UN 9

6

DE1_A_UN 9

8

DE0_B_UN 9

13

DE1_B_UN 9

9

PWD_UN9

3

M_REXT_UN9

10

SATA_EXP _IFDET

20

SATA_EXP _IFDET <19 ,41>

0

1

+3.3V_HDD

PWD_UN8

12

CN64 0.22U_0402 _10V6K

12

CN72 0.22U_0402 _10V6K

1 2

12 12

RN131 0_0402_ 5% RN132 0_0402_ 5%

RN53 4.99K _0402_1%

SATA

PCIE

+3.3V_HDD

10K_0402_5%

12

PWD_UN9

12

CN66 0.22U_0402 _10V6K

12

CN81 0.22U_0402 _10V6K

RN133 0_0402_ 5% RN134 0_0402_ 5%

12 12

1 2

RN58 4.99K_ 0402_1%

3

10K_0402_5%

12

@

RN78

@

RN79

PCIE_PTX_ C_DRX_P15 <41>

PCIE_PTX_ C_DRX_N15 <41>

PCIE_PRX _C_DTX_P15 <41> PCIE_PRX _C_DTX_N15 <41>

PCIE_PTX_ C_DRX_P16 <41>

PCIE_PTX_ C_DRX_N16 <41>

PCIE_PRX _C_DTX_P16 <41> PCIE_PRX _C_DTX_N16 <41>

2

+3.3V_HDD

10K_0402_5%

@

12

RN52

RN54

RN50

RN99

DE0_A_UN 8

DE1_A_UN 8

DE0_B_UN 8

DE1_B_UN 8 EQ2_A_UN8

10K_0402_5%

@

12

RN100

Programmable output de-emphasis level setting for channel A . A_DE0: internally pulled up at ~150K; A_DE1 internally pulled down at ~150K

[A_DE1,A_DE0] == LL: -7.5dB HL: -2dB LH: -3.5dB (default) HH: -6dB

Programmable output de-emphasis level setting for channel B. B_DE0: internally pulled up at ~150K; B_DE1 internally pulled down at ~150K

[B_DE1,B_DE0] == LL: -7.5dB HL: -2dB LH: -3.5dB (default) HH: -6dB

+3.3V_HDD

10K_0402_5%

@

12

RN116

10K_0402_5%

@

12

RN117

10K_0402_5%

@

12

RN101

RN103

RN102

10K_0402_5%

@

12

RN59

RN62

RN61

DE0_A_UN 9

DE1_A_UN 9

DE0_B_UN 9

10K_0402_5%

12

DE1_B_UN 9

10K_0402_5%

@

12

RN119

RN118

RN120

+3.3V_HDD +3.3V_HDD

10K_0402_5%

@

12

RN104

RN109

RN108

EQ0_A_U N8

EQ1_A_U N8

10K_0402_5%

@

12

RN106

RN105

RN107

Equalizer control and program for channel A. A_EQ0, A_EQ1 and A_EQ2: internally pulled down at ~150K

[A_EQ2,A_EQ1,A_EQ0] == LLL: EQ Level1(default) LHL: EQ Level2 HLL: EQ Level3 HHL: EQ Level4 LLH: EQ Level5 LHH: EQ Level6 HLH: EQ Level7 HHH: EQ Level8

Equalizer control and program for channel B. B_EQ0, B_EQ1 and B_EQ2: internally pulled down at ~150K

[B_EQ2,B_EQ1,B_EQ0] == LLL: EQ Level1(default) LHL: EQ Level2 HLL: EQ Level3 HHL: EQ Level4 LLH: EQ Level5 LHH: EQ Level6 HLH: EQ Level7 HHH: EQ Level8

+3.3V_HDD +3.3V_HDD

10K_0402_5%

@

12

RN121

RN122

RN123

EQ0_A_U N9

EQ1_A_U N9

10K_0402_5%

@

12

RN124

EQ2_A_U N9 EQ 2_B_UN9

10K_0402_5%

@

12

RN126

RN125

12

1

10K_0402_5%

@

12

RN114

RN115

RN110

EQ0_B_U N8

EQ1_B_U N8

EQ2_B_U N8

10K_0402_5%

@

12

RN60

RN51

RN111

10K_0402_5%

@

12

RN127

RN130

RN129

EQ0_B_U N9

EQ1_B_U N9

10K_0402_5%

@

12

RN128

RN57

RN55

PWD

A A

5

1

Funtion

Normal mode(Def ault)0

Chip power down

DEVICE interfac eSATA_EXP_IFD ET

0

1

4

SATA

PCIE

PROPRIETARY NOTE: THIS SHEET O F ENGINEERING DRAWING AND SPEC IFICATIONS CONTAINS CONFIDENTI AL TRADE SECRET AND OTHER PROPRIE TARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHO UT THE EXPRESS WRITTEN AUTHORI ZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS WAY BE US ED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT DELL'S EXPRESS W RITTEN CONSENT.

3

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

Size Document Nu mber Rev

Date: Sheet of

2

Compal Electronics, Inc.

HDD PCIE/SATA repeater

LA-C541P

42 74Tuesday, Au gust 18, 20 15

1

1.0

5

4

3

2

1

1 2

R492 1M_0402_5%

C366 0.1U_0402_10V7K

SW2_DP_P0<31>

C367 0.1U_0402_10V7K

D D

C C

B B

A A

SW2_DP_N0<31>

SW2_DP_P1<31> SW2_DP_N1<31>

SW2_DP_P2<31> SW2_DP_N2<31>

SW2_DP_P3<31> SW2_DP_N3<31>

C368 0.1U_0402_10V7K C369 0.1U_0402_10V7K

C424 0.1U_0402_10V7K C425 0.1U_0402_10V7K

C426 0.1U_0402_10V7K C427 0.1U_0402_10V7K

DPD_CA_DET

12 12

Close to DOCK Its for Enhance ESD on dock issue.

SW2_DP_HPD

100K_0402_5%

12

R757

SW2_DP_P0_C SW2_DP_N0_C

SW2_DP_P1_C SW2_DP_N1_C

SW2_DP_P2_C SW2_DP_N2_C

SW2_DP_P3_C SW2_DP_N3_C

SW2_DP_HPD<31> SW3_DP1_HPD <32>

Dock DPD (Port 1)

Dock DPD (Port 1)Dock DPD (Port 1)

DOCK_LOM_SPD10LED_GRN#<35>

1 2

R2164 33_0402_5%EMC@

1 2

R2165 33_0402_5%EMC@

1 2

R2166 33_0402_5%EMC@

1 2

R2167 33_0402_5%EMC@

1 2

R2168 33_0402_5%EMC@

1 2

R2169 33_0402_5%EMC@

1 2

R2170 33_0402_5%EMC@

1 2

R2171 33_0402_5%EMC@

SW2_DP_AUXP<31>

SW2_DP_AUXN<31>

0.033U_0402_16V7K

+NBDOCK_DC_IN_SS

@

1

C695

2

DOCK_TNY_SMB_CLK<44,46>

DOCK_TNY_SMB_DAT<44,46>

DOCK_TNY_SMBUS_ALRT#<44,45,50>

DOCK_PWR_BTN#<46>

SLICE_BAT_PRES#<45,50,60> DOCK_DET# <45>

+DOCK_PWR_BAR +DOCK_PWR_BAR

SW2_DP_HPD

BLUE_DOCK<18>

RED_DOCK<18>

GREEN_DOCK<18>

HSYNC_DOCK<18> VSYNC_DOCK<18>

CLK_MSE<46> DAT_MSE<46>

DAI_BCLK#<44> DAI_LRCK#<44>

DAI_DI<44> DAI_DO#< 44>

DAI_12MHZ#<44>

D_LAD0<45> D_LAD1<45>

D_LAD2<45> D_LAD3<45>

D_LFRAME#<45>

D_CLKRUN#<45>

D_DLDRQ1#<45>

CLK_PCI_DOCK<23>

DOCK_PSID<50>

D_SERIRQ<45>

1

2

4.7U_0805_25V6-K

@

CE6

SW2_DP_AUXP SW2_DP_AUXN

1

2

EMI request add 33ohm for DOCK DVI signals.

DOCK_DET_1

SW2_DP_P0_R SW2_DP_N0_R

SW2_DP_P1_R SW2_DP_N1_R

SW2_DP_P2_R SW2_DP_N2_R

SW2_DP_P3_R SW2_DP_N3_R

BLUE_DOCK

RED_DOCK

GREEN_DOCK

0.1U_0603_50V7K

@

C702

12

1

2

L30ESD24VC3-2_SOT23-3

@

2

3

D33

1

DAI_12MHZ#

EMC@

RE11 10_0402_1%

EMC@

CE8

4.7P_0402_50V8C

JDOCK1

1

3

5

7

9

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

41

43

45

47

49

51

53

55

57

59

61

63

65

67

69

71

73

75

77

79

81

83

85

87

89

91

93

95

97

99

101

103

105

107

109

111

113

115

117

119

121

123

125

127

129

131

133

135

137

139

141

143

145

GND1

146

PWR1

147

PWR1

148

PWR1

153

Shield_G

154

Shield_G

155

Shield_G

156

Shield_G

157

Shield_G

158

Shield_G

JAE_WD2F144WB5R 400

CONN@

PN change to SP0300019A0

PN change to SP0300019A0PN change to SP0300019A0

DAI_BCLK#

12

EMC@

RE12 10_0402_1%

1

EMC@

CE9

4.7P_0402_50V8C

2

PWR2 PWR2 PWR2 GND2

Shield_G Shield_G Shield_G Shield_G Shield_G Shield_G

Dock DPC (Port 2)

2

4

6

8

SW3_DP1_P0_R

10

SW3_DP1_N0_R

12

14

SW3_DP1_P1_R

16

SW3_DP1_N1_R

18

20

SW3_DP1_P2_R

22

SW3_DP1_N2_R

24

26

SW3_DP1_P3_R

28

SW3_DP1_N3_R

30

32

SW3_DP1_AUXP

34

SW3_DP1_AUXN

36

38

40

42

44

46

48

50

52

54

56

58

60

62

64

66

68

70

72

74

76

78

80

82

84

86

88

90

92

94

96

98

100

102

104

106

108

110

112

114

116

118

120

122

124

126

128

130

132

134

136

138

140

142

144

149 150 151 152

159 160 161 162 163 164

SW3_DP1_HPD

SATA_PRX_C_DTX_P1 SATA_PRX_C_DTX_N1

SATA_PTX_C_DRX_P1 SATA_PTX_C_DRX_N1

DOCK_DET_R#

1

2

CLK_PCI_DOCK

12

EMC@

R756 33_0402_5%

1

EMC@

C704 12P_0402_50V8J

2

0.1U_0603_50V7K

@

C703

C697 0.01U_0402_16V7K C698 0.01U_0402_16V7K

C700 0.01U_0402_16V7K C699 0.01U_0402_16V7K

DOCK_AC_OFF <60> DOCK_LOM_SPD100LED_ORG# <35> DPC_CA_DET <32>DPD_CA_DET<31>

1 2

R2172 33_0402_5%EMC@

1 2

R2173 33_0402_5%EMC@

1 2

R2174 33_0402_5%EMC@

1 2

R2175 33_0402_5%EMC@

1 2

R2176 33_0402_5%EMC@

1 2

R2177 33_0402_5%EMC@

1 2

R2178 33_0402_5%EMC@

1 2

R2179 33_0402_5%EMC@

SW3_DP1_AUXP <32> SW3_DP1_AUXN < 32>

ACAV_DOCK_SRC# <57,60>

DAT_DDC2_DOCK <18>

CLK_DDC2_DOCK <18>

12 12

1 2 1 2

USB20_P5 <20>

USB20_N5 <20>

USB20_P7 <20>

USB20_N7 <20>

CLK_KBD <46> DAT_KBD <46>

USB3_PRX_DTX_N6 <23> USB3_PRX_DTX_P6 <23>

USB3_PTX_DRX_N6 <23> USB3_PTX_DRX_P6 <23>

BREATH_LED# <46,47> DOCK_LOM_ACTLED_YEL# <35>

SW1_LAN1_MDIP0 <35>

SW1_LAN1_MDIN0 <35>

SW1_LAN1_MDIP1 <35>

SW1_LAN1_MDIN1 <35>

+LOM_VCT

SW1_LAN1_MDIP2 <35> SW1_LAN1_MDIN2 <35>

SW1_LAN1_MDIP3 <35> SW1_LAN1_MDIN3 <35>

DOCK_DCIN_IS+ <57> DOCK_DCIN_IS- <57>

DOCK_POR_RST# <46>

Dock DPC (Port 2)Dock DPC (Port 2)

SW3_DP1_P0_C SW3_DP1_N0_C

SW3_DP1_P1_C SW3_DP1_N1_C

SW3_DP1_P2_C SW3_DP1_N2_C

SW3_DP1_P3_C SW3_DP1_N3_C

SATA_PRX_DTX_P1 <19> SATA_PRX_DTX_N1 <19>

SATA_PTX_DRX_P1 <19> SATA_PTX_DRX_N1 <19>

+LOM_VCT

1U_0402_6.3V6K

@

1

C701

2

D32

21

RB751S40T1G_SOD523-2

1 2

C4310.1U_0402_10V7K C4380.1U_0402_10V7K

C4390.1U_0402_10V7K C4400.1U_0402_10V7K

C4410.1U_0402_10V7K C4420.1U_0402_10V7K

C4430.1U_0402_10V7K C4440.1U_0402_10V7K

SW3_DP1_P0 <32> SW3_DP1_N0 <32>

SW3_DP1_P1 <32> SW3_DP1_N1 <32>

SW3_DP1_P2 <32> SW3_DP1_N2 <32>

SW3_DP1_P3 <32> SW3_DP1_N3 <32>

100K_0402_5%

12

R2160

12

+3.3V_ALW

R75510K_0402_5%

1 2

1 2 1 2

0.033U_0402_16V7K

@

C696

1

2

Close to DOCK Its for Enhance ESD on dock issue.

SW3_DP1_HPD

audio not transfer to DP display if

audio not transfer to DP display if audio not transfer to DP display if play movie when attached external DP

play movie when attached external DP

play movie when attached external DPplay movie when attached external DP display

display

displaydisplay

DOCK_DET#

System hangs after hot dock.

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

Docking

LA-C551P

43 74Tuesday , August 18, 2015

1

1.0

5

USB/Codec/Card reader IO/B

D D

Right Side JUSB1----->

C C

B B

USB3_PTX_DRX_N3<23> USB3_PTX_DRX_P3<2 3>

USB3_PRX_DTX_N3<23> USB3_PRX_DTX_P3<2 3>

USB20_N2<20>

USB20_P2<20>

USB_OC1#<20> USB_OC3#<20>

USB20_N4<20> USB20_P4<20>

PCIE_PTX_DRX_P3<20> PCIE_PTX_DRX_N3<20>

PCIE_PRX_DTX_P3<20>

PCIE_PRX_DTX_N3<20>

USB_PWR_SHR_VBUS _RHT_EN1<45>

USB_PWR_SHR_RHT_EN1#<45>

USB_PWR_SHR_VBUS _RHT_EN2<4 5>

USB_PWR_SHR_RHT_EN2#<45>

USB_PWR_SHR_VBUS _RHT_EN3<4 5>

USB_PWR_SHR_RHT_EN3#<45>

+RTC_CELL +3.3V_ALW +3.3V_RUN

+5V_ALW

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

42

44

46

48

50

52

54

56

58

60

62

64

66

68

70

72

74

76

78

80

82

84

86

88

90

92

94

96

98

100

102

GND

FOX_QT50A01-29100-9H

Footprint change to "-S"

Footprint change to "-S"Footprint change to "-S"

+5V_ALW + 3.3V_RUN +3.3V_ALW+5V_RUN

0.1U_0402_10V6K

@

1

C763

2

4

3

2

1

Display daughter /B

JIO2

G1

G2

159

160

157

158

155

156

153

154

151

152

149

150

147

148

145

146

143

144

141

142

139

140

137

138

135

136

133

134

131

132

129

130

127

128

125

126

123

124

121

122

119

120

117

118

115

116

113

114

111

112

109

110

107

108

105

106

103

104

101

102

99

100

97

98

95

96

93

94

91

92

89

90

87

88

85

86

83

84

81

82

79

80

77

78

75

76

73

74

71

72

69

70

67

68

65

66

63

64

61

62

59

60

57

58

55

56

53

54

51

52

49

50

47

48

45

46

43

44

41

42

39

40

37

38

35

36

33

34

31

32

29

30

27

28

25

26

23

24

21

22

19

20

17

18

15

16

13

14

11

12

9

10

7

8

5

6

3

4

1

2

FOX_QT50A61-29100-9H

CONN@

161 159

SW4_DP_P0

157

SW4_DP_N0

155 153

SW4_DP_P1

151

SW4_DP_N1

149 147

SW4_DP_P2

145

SW4_DP_N2

143 141

SW4_DP_P3

139

SW4_DP_N3

137 135

SW4_DP_AUXP

133

SW4_DP_AUXN

131 129

SW5_DP_P0

127

SW5_DP_N0

125 123

SW5_DP_P1

121

SW5_DP_N1

119 117

SW5_DP_P2

115

SW5_DP_N2

113 111

SW5_DP_P3

109

SW5_DP_N3

107 105

SW5_DP_AUXP

103

SW5_DP_AUXN

101 99

USB3_PTX_DRX_N1

97

USB3_PTX_DRX_P1

95 93

USB3_PRX_DTX_N1

91

USB3_PRX_DTX_P1

89 87 85 83 81

TRIN_DOCK_DET

79

TCABLE_ID

77 75 73 71

TDOCK_BATLOW#

69

LPS_PROTECT#

67

DOCK_5V_IS

65

UPD_EN1_4#

63 61 59 57 55 53 51 49 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1

SW4_DP_P0 <34> SW4_DP_N0 <34>

SW4_DP_P1 <34> SW4_DP_N1 <34>

SW4_DP_P2 <34> SW4_DP_N2 <34>

SW4_DP_P3 <34> SW4_DP_N3 <34>

SW4_DP_AUXP <34> SW4_DP_AUXN <34>

SW5_DP_P0 <33> SW5_DP_N0 <33>

SW5_DP_P1 <33> SW5_DP_N1 <33>

SW5_DP_P2 <33> SW5_DP_N2 <33>

SW5_DP_P3 <33> SW5_DP_N3 <33>

SW5_DP_AUXP <33> SW5_DP_AUXN <33>

USB3_PTX_DRX_N1 <23>

USB3_PTX_DRX_P1 <23>

USB3_PRX_DTX_N1 <23> USB3_PRX_DTX_P1 <23>

USB20_N1 <20> USB20_P1 <20>

TRIN_DOCK_DET <45> TCABLE_ID <4 6>

DOCK_TNY_SMB_DAT <43,46> DOCK_TNY_SMB_CLK <43,46> DOCK_TNY_SMBUS_ALRT# <43,45,50>

TDOCK_BATLOW# <45> LPS_PROTECT# <45> DOCK_5V_IS <45> UPD_EN1_4# <45> EN_PIC_LDO <45>

MID1_CA_DET <32,34>

+5V_RUN

+5V_ALW

+NBDOCK_DC_IN_SS +DC_IN_SS +VBUS_DC_SS +PWR_SRC

Add for PS8407 (LS-C552P)

TO TBT

TO DP

162 160 158 156 154 152 150 148 146 144 142 140 138 136 134 132 130 128 126 124 122 120 118 116 114 112 110 108 106 104 102 100

98 96 94 92 90 88 86 84 82 80 78 76 74 72 70 68 66 64 62 60 58 56 54 52 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10

8 6 4 2

Footprint change to "-S"

Footprint change to "-S"Footprint change to "-S"

USB_OC0#<20>

PBAT_PRES#<46,50,57>

LID_CL#<45,47>

SS1_ON<45>

+3.3V_RUN

+3.3V_ALW2

+3.3V_ALW

+SDC_IN

PCIE_PRX_DTX_P8 PCIE_PRX_DTX_N8

PCIE_PTX_DRX_P8 PCIE_PTX_DRX_N8

PCIE_PRX_DTX_P7 PCIE_PRX_DTX_N7

PCIE_PTX_DRX_P7 PCIE_PTX_DRX_N7

PCIE_PRX_DTX_P6 PCIE_PRX_DTX_N6

PCIE_PTX_DRX_P6 PCIE_PTX_DRX_N6

PCIE_PRX_DTX_P5 PCIE_PRX_DTX_N5

PCIE_PTX_DRX_P5 PCIE_PTX_DRX_N5

CLK_PCIE_N4 CLK_PCIE_P4

CLKREQ_PCIE#4 PCIE_WAKE# PLTRST_TBT# TBT_FORCE_PWR SIO_SLP_S3# TBT_CIO_PLUG_EVENT# RTD3_USB_PWR_EN RTD3_CIO_PWR_EN TBT_DP0_HPD SW5_DP_HPD MID2_CA_DET TBT_PWR_EN USB_OC0# USB_PWR_SHR_LFT_EN# USB_PWR_SHR_VBUS _LFT_EN

1 2

R388 0_0402_5%@

PCIE_PRX_DTX_P8<20> PCIE_PRX_DTX_N8<20>

PCIE_PTX_DRX_P8<20>

JIO1CONN@

1

3

5

7

9

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

41

43

45

47

49

51

53

55

57

59

61

63

65

67

69

71

73

75

77

79

81

83

85

87

89

91

93

95

97

99

101

GND

0.1U_0402_10V6K

@

C721

@

1

C723

C722

2

USB3_PRX_DTX_N4 < 23> USB3_PRX_DTX_P4 <23>

USB3_PTX_DRX_N4 < 23> USB3_PTX_DRX_P4 <23>

USB20_N3 <20> USB20_P3 <20>

USB_OC2# <20>

USB3_PRX_DTX_N5 < 23> USB3_PRX_DTX_P5 <23>

USB3_PTX_DRX_N5 < 23> USB3_PTX_DRX_P5 <23>

DAI_DI <43>

DAI_DO# <43> DAI_BCLK# <43> DAI_LRCK# <43> EN_I2S_NB_CODEC# <45> DMIC_CLK <30>

DMIC0 <30> AUD_NB_MUTE# <45> BEEP < 46> SPKR <23>

CLK_PCIE_P1 <21>

CLK_PCIE_N1 <21>

CLKREQ_PCIE#1 <21>

MEDIACARD_IRQ# <22>

PLTRST_MMI# <22>

HOST_SD_WP# <24> HDA_BIT_CLK_R <23>

HDA_SDIN0 <23>

HDA_SDOUT_R <23>

HDA_SYNC_R <23>

HDA_RST#_R <23>

DAI_12MHZ# <43>

DOCK_HP_DET <45> DOCK_MIC_DET <45> AUD_HP_NB_SENSE <45>

+5V_RUN

<----- Right Side JUSB2

<----- Right Side JUSB3

TBT GOIP/HPD

USB GPIO/OC

PD GPIO/SMBUS

Miramar17 only

PCIE_PTX_DRX_N8<20>

PCIE_PRX_DTX_P7<20> PCIE_PRX_DTX_N7<20>

PCIE_PTX_DRX_P7<20> PCIE_PTX_DRX_N7<20>

PCIE_PRX_DTX_P6<20> PCIE_PRX_DTX_N6<20>

PCIE_PTX_DRX_P6<20> PCIE_PTX_DRX_N6<20>

PCIE_PRX_DTX_P5<20> PCIE_PRX_DTX_N5<20>

PCIE_PTX_DRX_P5<20> PCIE_PTX_DRX_N5<20>

CLK_PCIE_N4<21> CLK_PCIE_P4<21>

CLKREQ_PCIE#4<21>

PCIE_WAKE#<18,38,3 9,45> PLTRST_TBT#<22>

TBT_FORCE_PWR<22>

SIO_SLP_S3#<7,11,23,37,46>

TBT_CIO_PLUG_EVENT#<19>

RTD3_USB_PWR_EN< 45> RTD3_CIO_PWR_EN<22,45> SW4_DP_HPD<34> SW5_DP_HPD<33> MID2_CA_DET<3 3>

TBT_PWR_EN<45>

USB_PWR_SHR_LFT_EN#<45>

USB_PWR_SHR_VBUS _LFT_EN<45>

UPD_GPU_SMBDAT<18,46>

UPD_GPU_SMBCLK<18,46>

UPD_SMBUS_ALERT#<45>

5VUSB_OFF<45> PWR_SRC_ON<45>

SIO_SLP_S5#<23,37,46>

TDOCK_PWR_BTN#<46>

DETECT_PWR_EN<45>

DCIN_ACOK#<57> PD_ACE_DET#<45>

+3.3V_RUN+5V_ALW +3.3V_ALW+5V_RUN

0.1U_0402_10V6K

@

1

C766

C724

2

SW1

@

SKRBAAE010_4P

2

1

3

Power Switch for

Power Button CONN

Power Button CONNPower Button CONN

POWER_SW #_MB

+5V_ALW

BREATH_WHITE_LED<47>

A A

5

JPB1

1

2

3

4

5

6

7

GND

8

GND

ACES_50228-0067N-001

CONN@

Link CIS OK

Link CIS OKLink CIS OK

4

Power Switch forPower Switch for

debug

debugdebug

POWER_SW #_MB<37,46>

100P_0402_50V8J

@

1

C759

2

112

PWRSW 1

@

@SHORT PADS~D

Place on Bottom

Place on BottomPlace on Bottom

2

POWER_SW #_MB

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

4

0.1U_0402_10V6K

@

1

C1431

2

+NBDOCK_DC_IN_SS +PWR_SRC +SDC_IN

0.1U_0402_10V6K

@

C725

@

1

C1430

C726

2

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet of

@

C1425

0.1U_0402_10V6K

1

2

Compal Electronics, Inc.

@

C1426

IO / PWR Button

@

1

C1427

2

LA-C551P

1

@

1

C1428

2

0.1U_0402_10V6K

@

1

C1456

2

1.0

44 74Tuesday, August 18, 2015

1.0

5

+3.3V_ALW

USB_PWR_SHR_LFT_EN#

1 2

RE72 100K_0402_5%

RE69 100K_0402_5%

RE70 100K_0402_5%

RE71 100K_0402_5%

RE14 100K_0402_5%

R763 10K_0402_5%

D D

R779 10K_0402_5%

R2158 100K_0 402_5%

R759 10K_0402_5%

R773 10K_0402_5%

R3740 100K_ 0402_5%

RE73 100K_0402_5%

RE74 100K_0402_5%

RE75 100K_0402_5%

RE76 100K_0402_5%

RE77 100K_0402_5%

R415 100K_0402_5%@

C C

+3.3V_RUN

R782 100K_0402_5%

R783 100K_0402_5%

RH318 10K_0402 _5%

R379 10K_0402_5%

B B

A A

USB_PWR_SHR_RHT_EN1#

1 2

USB_PWR_SHR_RHT_EN2#

1 2

USB_PWR_SHR_RHT_EN3#

1 2

1 8 2 7 3 6 4 5

1 2

1 8 2 7 3 6 4 5

1 2

+3.3V_ALW

WWAN_RA DIO_DIS#

DOCK_TNY_SMBUS_ALRT#

HW_GPS_DISABLE#

SLICE_BAT_PRES#

PCIE_WAKE#

WWAN_W AKE#

UPD_SMBUS_ALERT#

12

RP9

100K_0804_8P4R_5%

RP3

100K_0804_8P4R_5%

100K_0402_5%

12

100K_0402_5%

12

SLOT2_CONFIG_0 SLOT2_CONFIG_1 SLOT2_CONFIG_2 SLOT2_CONFIG_3

USB_PWR_SHR_VBUS _LFT_EN

USB_PWR_SHR_VBUS _RHT_EN1

USB_PWR_SHR_VBUS _RHT_EN2

USB_PWR_SHR_VBUS _RHT_EN3

PD_ACE_DET#

PROCHOT_GATE

D_CLKRUN#

D_SERIRQ

D_DLDRQ1# DGPU_ALERT#

GPU_PWR_LEVEL

12

LPC_LDRQ1#

12

M2_SLOT2_PCIE#_SATA

USH_DET#

Tell EC don't read GFX Temp.in GC6 High: Read; Low: Don`t read

@

R800

VGA_ID

R803

Discrete

UMA 1

5

VGA_ID0

0

1 2

R3748 10K_0402_5%@

RTD3_CIO_PWR_EN<22,44>

LAN_DISABLE#_R<35>

DOCK_TNY_SMBUS_ALRT#< 43,44,50>

USB_PWR_SHR_RHT_EN2#<44>

USB_PWR_SHR_RHT_EN1#<44>

USB_PWR_SHR_VBUS _LFT_EN<44>

USB_PWR_SHR_RHT_EN3#<44>

USB_PWR_SHR_VBUS _RHT_EN1<4 4>

AC_DIS<50,60>

GPU_PWR_LEVEL<18>

EN_I2S_NB_CODEC#<44> USH_PWR_STATE#< 37>

EN_DOCK_PWR_BAR<60>

HW_GPS_DISABLE#<38>

PANEL_BKEN_EC<30>

LCD_TST<30>

PSID_DISABLE#<50 >

SLOT4_SSD_PWR_EN<40>

DOCKED<35>

DOCK_DET#<43>

AUD_NB_MUTE#<44>

3.3V_WW AN_EN<4 0>

LCD_VCC_TEST_EN<30>

WWAN_W AKE#< 38>

AUD_HP_NB_SENSE<44>

SLOT3_SSD_PWR_EN<40>

SLICE_BAT_ON<60>

SLICE_BAT_PRES#<43,50,60>

TB_STAT#<57> PBA_GPU_SEL#<31> SLOT2_CONFIG_1 <38> MXM_VGA_DIS#<18>

USH_DET#<37>

WLAN_W IGIG60GHZ_DIS#<38>

EC5048_TX<46>

UPD_EN1_4#<44>

DETECT_PWR_EN<44>

DOCK_5V_IS<44>

DGPU_PWR_EN<18>

DGPU_ALERT#<18> MXM_DP_HDMI_HPD<18>

TRIN_DOCK_DET<44> BCM5882_ALERT#<37>

UPD_SMBUS_ALERT#<44>

DGPU_PWROK<18,23>

3.3V_RUN_GFX_ON<21,49> TDOCK_BATLOW#<44>

SYS_LED_MASK#<35,47> 5VUSB_OFF<44> DP1_GPU_SEL#<34> EN_PIC_LDO<44>

GC6_THM_ON< 19>

PWR_SRC_ON<44>

BT_RADIO_DIS#<38>

WWAN_RA DIO_DIS#<38>

DGPU_SELECT#<29,30>

SIO_SLP_WLAN#<23,40>

4

+3.3V_ALW_U46 +3.3V_ALW

CIS LINK OK

U46

B52

RTD3_CIO_PWR_EN

LAN_DISABLE#_R AC_DIS LID_CL_SIO# DOCK_TNY_SMBUS_ALRT#

GPU_PWR_LEVEL

USB_PWR_SHR_RHT_EN2# EN_I2S_NB_CODEC# USH_PWR_STATE# EN_DOCK_PWR_BAR HW_GPS_DISABLE# PANEL_BKEN_EC LCD_TST PSID_DISABLE# SLOT4_SSD_PWR_EN DOCKED DOCK_DET# AUD_NB_MUTE#

3.3V_WW AN_EN LCD_VCC_TEST_EN WWAN_W AKE# AUD_HP_NB_SENSE

USB_PWR_SHR_RHT_EN1#

SLOT3_SSD_PWR_EN SLICE_BAT_ON SLICE_BAT_PRES# TB_STAT# PBA_GPU_SEL# SLOT2_CONFIG_1 MXM_VGA_DIS# USH_DET#

WLAN_W IGIG60GHZ_DIS# EC5048_TX UPD_EN1_4# DETECT_PWR_EN DOCK_5V_IS DGPU_PWR_EN DGPU_ALERT# MXM_DP_HDMI_HPD

TRIN_DOCK_DET BCM5882_ALERT# UPD_SMBUS_ALERT#

DGPU_PWROK VGA_ID

3.3V_RUN_GFX_ON TDOCK_BATLOW#

M2_SLOT2_PCIE#_SATA SYS_LED_MASK# 5VUSB_OFF DP1_GPU_SEL# EN_PIC_LDO

USB_PWR_SHR_VBUS _LFT_EN

GC6_THM_ON

PWR_SRC_ON BT_RADIO_DIS# WWAN_RA DIO_DIS#

DGPU_SELECT# SIO_SLP_WLAN# USB_PWR_SHR_RHT_EN3# USB_PWR_SHR_VBUS _RHT_EN1

CLK_PCI_5048

GPIOA0

A49

GPIOA1

B53

GPIOA2

A50

GPIOA3

B54

GPIOA4

A51

GPIOA5

B55

GPIOA6

A52

GPIOA7

A33

GPIOB0

B36

GPIOB1

A34

GPOC2

B37

GPOC3

A35

GPOC4

B38

GPOC5

A36

GPOC6/TACH4

A37

GPIOC7

B40

GPIOD0

A38

GPIOC1

B41

GPIOC0

A39

GPIOB7

B42

GPIOB6

A40

GPIOB5

B43

GPIOB4

A41

GPIOB3

B44

GPIOB2

B32

GPIOD1

A31

GPIOD2

B33

GPIOD3

B15

GPIOD4

A15

GPIOD5

B16

GPIOD6

A16

GPIOD7

A1

GPIOE0/RXD

B2

GPIOE1/TXD

A2

GPIOE2/RTS#

B3

GPIOE3/DSR#

A3

GPIOE4/CTS#

B45

GPIOE5/DTR#

A42

GPIOE6/RI#

B4

GPIOE7/DCD#

A59

GPIOF0

B62

GPIOF1

A58

GPIOF2

B61

GPIOF3/TACH8

A56

GPIOF4/TACH7

B59

GPIOF5

A55

GPIOF6

B58

GPIOF7

B47

GPIOG0/TACH5

A45

GPIOG1

B48

GPIOG2

A46

GPIOG3

B49

GPIOG4

A47

GPIOG5

B50

GPIOG6

A48

GPIOG7/TACH6

B13

GPIOH0

A13

GPIOH1

A53

SYSOPT1/GPIOH2

B57

SYSOPT0/GPIOH3

B14

GPIOH4

A14

GPIOH5

B17

GPIOH6

B18

GPIOH7

10_0402_1%

12

@

R795

4.7P_0402_50V8C

@

1

C713

2

4

B5

A17

B30

VCC1

ECE5048-LZY_DQFN132_11X11~D

+3.3V_ALW

LID_CL_SIO#

A43

A54

VCC1

100K_0402_5%

12

R805

R807 10_0402_1 %

0.047U_0402_16V4Z

C716

1

2

3

0.1U_0402_25V6K

1

C710

2

GPIOI0 GPIOI1

GPIOI2/TACH0

GPIOI3 GPIOI4 GPIOI5 GPIOI6 GPIOI7

GPIOJ0 GPIOJ1/TACH1 GPIOJ2/TACH2

GPIOJ3

GPIOJ4

GPIOJ5

GPIOJ6

GPIOJ7

GPIOK0

GPIOK1/TACH3

GPIOK2

GPIOK3

GPIOK4

GPIOK5

GPIOK6

GPIOK7

GPIOL0/PWM7 GPIOL1/PWM8 GPIOL2/PWM0 GPIOL3/PWM1 GPIOL4/PWM3 GPIOL5/PWM2

GPIOL6 GPIOL7/PWM5

GPIOM1 GPIOM3/PWM4 GPIOM4/PWM6

LAD0 LAD1 LAD2 LAD3

LFRAME#

LRESET#

PCICLK

CLKRUN#

LDRQ1#

SER_IRQ

14.318MHZ/GPIOM0 CLK32/GPIOM2

DLAD0 DLAD1 DLAD2

DLAD3 DLFRAME# DCLKRUN#

DLDRQ1#

DSER_IRQ

BC_INT#

BC_DAT BC_CLK

PWRGD

OUT65

TEST_PIN

CAP_LDO

DB Version 0.4

12

3

0.1U_0402_25V6K

0.1U_0402_10V7K

C709

C708

1

2

A23 B63 A60 A61 B65 A62 B66 A63

B67 A64 A5 B6 A6 B7 A7 B8

A8 B9 B10 A10 B11 A11 B12 A12

B60 A57 B64 B68 A9 B1 A18 A44

B34 B39 B51

A27 A26 B26 B25 A21 B22 A28 B20

A22 B21 A32 B35

B29 B28 A25 A24 B23 A19 B24 A20

A29 B31 A30

A4

B56

B19

B46

B27

VSS

C1

EP

2

PJP12

@

PAD-OPEN1x1m

0.1U_0402_10V7K

SHORT DEFAULT

C719

1

2

C714

WLAN_DISBL# <35>

SLOT2_CONFIG_2 <38>

SLOT2_CONFIG_3 <38>

LPC_FRAME# < 23,46>

12

TBT_PWR_EN <44> SS1_ON <44> PD_ACE_DET# <44> PROCHOT_GATE <57>

PLTRST_USH#_EC <22> LPS_PROTECT# <44>

DOCK_AC_OFF_EC <60>

AUX_EN_WOW L <40>

ME_FWP_EC <23>

AAEN <28> GPIO_PSID_SELECT <50>

DP2_GPU_SEL# <33> DOCK_HP_DET <44> DOCK_MIC_DET <44>

USB_PWR_SHR_LFT_EN# <44>

MASK_SATA_LED# <47>

PCIE_WAKE# <18,38,39,44> LED_SATA_DIAG_OUT# <47> RTD3_USB_PWR_EN <44>

USB_PWR_SHR_VBUS _RHT_EN2 <44>

SLOT2_CONFIG_0 <38>

USB_PWR_SHR_VBUS _RHT_EN3 <44>

T213PAD~D @

T165PAD~D @

LPC_AD0 <23,46> LPC_AD1 <23,46> LPC_AD2 <23,46> LPC_AD3 <23,46>

PCH_PLTRST#_EC <22,38,39,46> CLK_PCI_5048 <23>

CLKRUN# <23,46>

IRQ_SERIRQ <23,46>

T214PAD~D @

EC_32KHZ_ECE5048 < 46>

D_LAD0 <43> D_LAD1 <43> D_LAD2 <43> D_LAD3 <43> D_LFRAME# <4 3> D_CLKRUN# <43> D_DLDRQ1# <43> D_SERIRQ <43>

BC_INT#_ECE5048 <46>

BC_DAT_ECE5048 <46>

BC_CLK_ECE5048 <46>

RUNPWROK <46>

0.1U_0402_10V7K

C718

C717

1

2

TBT_PWR_EN SS1_ON PD_ACE_DET# PROCHOT_GATE

PLTRST_USH#_EC LPS_PROTECT#

AUX_EN_WOW L ME_FWP_EC

AAEN GPIO_PSID_SELECT DP2_GPU_SEL# DOCK_HP_DET DOCK_MIC_DET

USB_PWR_SHR_LFT_EN# MASK_SATA_LED# PCIE_WAKE# LED_SATA_DIAG_OUT# RTD3_USB_PWR_EN USB_PWR_SHR_VBUS _RHT_EN2 SLOT2_CONFIG_0 USB_PWR_SHR_VBUS _RHT_EN3

GPIOL0

WLAN_DISBL# CCD_OFF

SLOT2_CONFIG_2

SLOT2_CONFIG_3

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 LPC_FRAME# PCH_PLTRST#_EC CLK_PCI_5048 CLKRUN#

LPC_LDRQ1# IRQ_SERIRQ CLK_SIO_14M EC_32KHZ_ECE5048

D_LAD0 D_LAD1 D_LAD2 D_LAD3 D_LFRAME# D_CLKRUN# D_DLDRQ1# D_SERIRQ

BC_INT#_ECE5048 BC_DAT_ECE5048 BC_CLK_ECE5048

RUNPWROK

1 2

R804 1K_ 0402_1%

+CAP_LDO

4.7U_0603_6.3V6K

1

2

+CAP_LDO trace width 20

+CAP_LDO trace width 20+CAP_LDO trace width 20

mils

milsmils

LID_CL# < 44,47>

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

2

LCD_TST SLICE_BAT_ON MXM_DP_HDMI_HPD

GPIOL0

Reserve only

SYS_LED_MASK#

PROCHOT_GATE

1

RP4

1 8 2 7 3 6 4 5

100K_0804_8P4R_5%

1 2

R3741 100K_0402_5%@

12

R775 10K_0402_5%

1 2

R416 100K_0402_5%

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

SIO (ECE5048)

LA-C551P

45 74Tuesday, August 18, 2015

1

1.0

5

+3.3V_ALW_U51

PJP@

PJP13

1 2

PAD-OPEN1x1m

SHORT DEFAULT

10_0402_1%

+3.3V_ALW

10K_0402_5%

12

R847

CLK_PCI_LPDEBUG

10_0402_1%

12

@

R3757

4.7P_0402_50V8C

@

1

C1469

2

+RTC_CELL

1 2

R834 0_0402_5%@

+3.3V_ALW_U51

CLK_PCI_MEC

12 @

R885

4.7P_0402_50V8C

1

@

C747

2

Place close pin

Place close pinPlace close pin A29

A29

A29A29

100K_0402_5%

10K_0402_5%

12

@

R850

R849

R848

HOST_DEBUG_TX

R862 0_0402_5% R863 0_0402_5%@

1

2

1 2 1 2

SIO_SLP_SUS# SIO_SLP_SUS#_R

D D

C C

B B

A A

+3.3V_ALW

R829 2.2K_0402_5%

R822 2.2K_0402_5%

+5V_RUN

R869 10K_0402_5%

R843 8.2K_0402_5%@

R892 10K_0402_5%

R432 47K_0402_5%

R3730 100K_0402_5%

1

JTAG1

@SHORT PADS~D

1

CONN@

2

VSET_5085

0.1U_0402_25V6K

1.33K_0402_1%

12

R425

1

C320

2

Rest=1.33k, Tp=93degree

ACES_50506-01041-P01

1 2

R814 100K_0402_5%

1 2

R817 100K_0402_5%

PN change to SD309220180

RP5

1 8 2 7 3 6 4 5

2.2K_8P4R_5%

1 2

PN change to SD309470180

RP6

1 8 2 7 3 6 4 5

4.7K_0804_8P4R_5%

1 2

RP7

1 8 2 7 3 6 4 5

100K_0804_8P4R_5%

1 2

1U_0402_6.3V6K

1

C735

2

JDEG2

ACES_50506-01041-P01

CONN@

CIS link

CIS linkCIS link OK

OK

OKOK

CONN@

JLPDE1

1 2 3 4 5 6 7 8 9

10

GND1 GND2

CIS link

CIS linkCIS link OK

OK

OKOK

BC_DAT_ECE5048

BC_DAT_ECE1117

PBAT_SMBDAT PBAT_SMBCLK CHARGER_SMBDAT CHARGER_SMBCLK

UPD_GPU_SMBDAT

UPD_GPU_SMBCLK

DAT_KBD DAT_MSE CLK_KBD CLK_MSE

MSDATA

DOCK_POR_RST#

PCH_ALW_ON EN_INVPWR

RESET_OUT#

PCH_RSMRST#

A_ON

+3.3V_ALW

100K_0402_5%

12

100_0402_1%

12

1 2 3 4 5 6 7 8 9

10

GND1 GND2

+3.3V_RUN

1 2 3 4 5 6 7 8 9 10

11 12

5

RUN_ON

R1981

JTAG_RST#

@

R836

1 2 3 4 5 6

MSCLK

7

MSDATA

8 9 10

11 12

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3

LPC_FRAME#

PCH_PLTRST#_EC

CLK_PCI_LPDEBUG

+3.3V_ALW

12

49.9_0402_1%

12

R864

R37443K_0402_1%

10K_0402_5%

12

R858

R859

CLK_PCI_LPDEBUG <23>

10K_0402_5%

12

R860

10K_0402_5%

R861

JTAG_TDI JTAG_TMS JTAG_CLK JTAG_TDO

SIO_SLP_SUS#_R <23>

+3.3V_ALW

4

1 2

R1985 0_0402_5%@

0.1U_0402_25V6K

10U_0603_6.3V6M

1

C781

C1345

C782

2

DOCK_POR_RST#

0.1U_0402_25V6K

1

2

Place close pin

Place close pinPlace close pin A21

A21

A21A21

EC5048_TX SBIOS_TX

+3.3V_ALW

10K_0402_5%

12

R872

FWP#

10K_0402_5%

@

R879

1 2

0.1U_0402_25V6K

1

C1353

2

+3.3V_VTR

0.1U_0402_25V6K

1

C739

2

0.1U_0402_25V6K

1

C1355

C1348

2

C737

27P_0402_50V8J

32.768KHZ_12.5PF_Q13FC135000040

C743

1

2

EC5048_TX <45> SBIOS_TX <24>

4

+RTC_CELL_VBAT

1U_0402_6.3V4Z

+3.3V_ALW_U51

1 2

C1349

R845 0_0402_5%@

0.1U_0402_25V6K

1

2

0.1U_0402_25V6K

1

C780

C777

SML1_SMBDATA<23> SML1_SMBCLK<23>

CLK_TP_SIO<48>

2

32 KHz Clock

32 KHz Clock32 KHz Clock

DAT_TP_SIO<48> CLK_KBD<43> DAT_KBD<43> CLK_MSE<43> DAT_MSE<43>

PBAT_SMBDAT<50>

PBAT_SMBCLK<50>

FAN1_TACH_EC<28>

DOCK_POR_RST#<43>

FAN2_TACH_EC<28>

PS_ID<50> FAN2_PWM_EC<28> BIA_PWM_EC<30> FAN1_PWM_EC<28>

BC_CLK_ECE5048<45>

BC_DAT_ECE5048<45>

BC_INT#_ECE5048<45>

ACAV_IN_NB<57,60> SIO_SLP_S5#<23,37,44>

BEEP<44>

BC_CLK_ECE1117<48>

BC_DAT_ECE1117<48>

BC_INT#_ECE1117<48>

SIO_EXT_SMI#<22>

SIO_RCIN#<23>

IRQ_SERIRQ<23,45>

PCH_PLTRST#_EC<22,38,39,45>

CLK_PCI_MEC<23>

LPC_FRAME#<23,45>

LPC_AD0<23,45> LPC_AD1<23,45> LPC_AD2<23,45> LPC_AD3<23,45>

CLKRUN#<23,45>

SIO_EXT_SCI#<24>

MEC_XTAL2 MEC_XTAL2_R

R1068 0_0402_5%@

Y6

MEC_XTAL2MEC_XTAL1

1 2

33P_0402_50V8J

1

C741

2

+3.3V_ALW

6.2K_0402_5%

12

R875

BOARD_ID

4700P_0402_25V7K

1

C744

2

BOARD_ID rise time is measured from 5%~68%.

BOARD_ID rise time is measured from 5%~68%.BOARD_ID rise time is measured from 5%~68%.

RUN_ON<46,49>

B64

A22

1U_0402_6.3V4Z

+VTR_ADC

1

C736

2

12

R875 C744

33K

4.3K 2K 1K

62K 4700p

*

8.2K

A58

C757

B3 A11 A26 B35 A41 A52

SML1_SMBDATA

A5

SML1_SMBCLK

B6

CLK_TP_SIO

A37

DAT_TP_SIO

B40

CLK_KBD

A38

DAT_KBD

B41

CLK_MSE

A39

DAT_MSE

B42

PBAT_SMBDAT

B59

PBAT_SMBCLK

A56

JTAG_TDI

A51

JTAG_TDO

B55

JTAG_CLK

B56

JTAG_TMS AC_PRESENT

A53

JTAG_RST#

B47

FAN1_TACH_EC

B22

DOCK_POR_RST#

A21

FAN2_TACH_EC

B23

PS_ID

B24

FAN2_PWM_EC

A23

BIA_PWM_EC

B25

FAN1_PWM_EC

A24

BC_CLK_ECE5048

A43

BC_DAT_ECE5048

B45

BC_INT#_ECE5048

A42

ACAV_IN_NB

B20

SIO_SLP_S5#

A18 B19

BEEP BC_CLK_ECE1117

A20

BC_DAT_ECE1117

B21

BC_INT#_ECE1117

A19

SIO_EXT_SMI#

A6

SIO_RCIN#

A27

IRQ_SERIRQ

A28

PCH_PLTRST#_EC

B30

CLK_PCI_MEC

A29

LPC_FRAME#

B31

LPC_AD0

A30

LPC_AD1

B32

LPC_AD2

A31

LPC_AD3

B33 A32

CLKRUN# SIO_EXT_SCI#

A33

MEC_XTAL1

A61 A62

REV

X00

4700p240K

X01

4700p130K 4700p

X02

4700p

X03

4700p

X04

4700p

X05 A00

4700p

+3.3V_ALW

100K_0402_5%

12

RUNPWROK

RE68

RUN_ON#

DMN66D0LDW-7_SOT363-6

6

QE2A

2

1

3

+RTC_CELL

100K_0402_5%

12

R810

POWER_SW_IN#

PN change from SA00006YH00 to SA00006YH90

U51

VBAT

H_VTR

VTR_ADC

VTR VTR VTR VTR VTR VTR

GPIO007/I2C1D_DATA/PS2_CLK0B/I2C3A_DATA GPIO010/I2C1D_CLK/PS2_DAT0B/I2C3A_CLK/GANG_DATA0 GPIO110/PS2_CLK2/GPTP-IN6 GPIO111/PS2_DAT2/GPTP-OUT6 GPIO112/PS2_CLK1A GPIO113/PS2_DAT1A GPIO114/PS2_CLK0A GPIO115/PS2_DAT0A GPIO154/I2C1C_DATA/PS2_CLK1B/GANG_DATA5 GPIO155/I2C1C_CLK/PS2_DAT1B/GANG_DATA6

GPIO145/I2C1K_DATA/JTAG_TDI GPIO146/I2C1K_CLK/JTAG_TDO GPIO147/I2C1J_DATA/I2C2C_DATA/JTAG_CLK GPIO150/I2C1J_CLK/I2C2C_CLK/JTAG_TMS JTAG_RST#

GPIO050/FAN_TACH1/GTACH0/GANG_START GPIO051/FAN_TACH2/GANG _MODE GPIO052/FAN_TACH3/GTACH1/GANG_ERROR GPIO053/PWM0 GPIO054/PWM1/GPWM1 GPIO055/PWM2 GPIO056/PWM3/GPWM0

GPIO123/BCM_A_CLK GPIO122/BCM_A_DAT GPIO121/BCM_A_INT# GPIO032/BCM_E_CLK GPIO031/GPTP-OUT2/BCM_E_DAT GPIO030/GPTP-IN2/BCM_E_INT#/GANG_DATA7 GPIO047/LSBCM_D_CLK GPIO046/LSBCM_D_DAT/GANG_STROBE GPIO045/LSBCM_D_INT#

GPIO011/nSMI GPIO061/LPCPD# SER_IRQ LRESET# PCI_CLK LFRAME# LAD0 LAD1 LAD2 LAD3 CLKRUN# GPIO100/NEC_SCI

XTAL1 XTAL2

15mil

EVT DVT1.0 DVT1.1 DVT1.2 DVT2.0 DVT2.1 Pilot

+3.3V_RUN

10K_0402_5%

12

RE67

DMN66D0LDW-7_SOT363-6

34

QE2B

5

1 2

R811 10K_0402_5%

1U_0402_6.3V6K

1

C1352

2

AGND

VSS

VSS_ADC

VR_CAP

B66

VSS_RO

B11

B60

B12

B54

4.7U_0603_6.3V6K

+VR_CAP

1

C779

2

ESR

ESRESR

<2ohms

<2ohms<2ohms

PANEL_ID

3

C1354

@

1 2

1U_0402_6.3V6K

POWER_SW#_MB <37,44>

GPIO021/RC_ID1 GPIO020/RC_ID2

GPIO014/GPTP-IN7/RC_ID3

GPIO025/UART_CLK

GPIO120/UART_TX/V2P_COUT_HI1

GPIO124/GPTP-OUT5/UART_RX/V2P_COUT_LO1

GPIO116/MSDATA/V2P_COUT_LO/TAP_SEL_STRAP

GPIO125/GPTP-IN5/PECI_REQUEST#/GANG_BUSY

GPIO013/I2C1H_CLK/I2C2D_CLK/GANG_DATA3

H_VSS

B18

+3.3V_ALW

12

1

2

GPIO060/KBRST/BCM_B_INT#

GPIO117/MSCLK/V2P_COUT_HI

GPIO156/LED1/GANG_DATA1

GPIO153/LED2/GANG_DATA4

GPIO001/ECSPI_CS1/32KHZ_OUT

GPIO151/GPTP-IN4/GANG_DATA2

GPIO005/I2C1B_DATA/BCM_B_DAT

GPIO006/I2C1B_CLK/BCM_B_CLK

GPIO012/I2C1H_DATA/I2C2D_DATA

GPIO130/I2C2A_DATA/BCM_C_DAT

GPIO131/I2C2A_CLK/BCM_C_CLK

GPIO141/I2C1F_DATA/I2C2B_DATA

GPIO142/I2C1F_CLK/I2C2B_CLK

GPIO024/THSEL_STRAP

PROCHOT_IN#/PROCHOT_IO#

EP

C1

4.3K_0402_5%

R3754 C1465

R3754

33K

4.3K

*

4700P_0402_25V7K

2K

C1465

GPIO101/ECGP_SCLK GPIO103/ECGP_MISO GPIO105/ECGP_MOSI

GPIO102/BCM_C_INT#

GPIO104/SLP_S0#

GPIO027/GPTP-OUT1

GPIO026/GPTP-IN1

GPIO015/GPTP-OUT7

GPIO016/GPTP-IN8

GPIO017/GPTP-OUT8

GPIO107/NRESET_OUT

GPIO152/GPTP-OUT4

GPIO003/I2C1A_DATA

GPIO004/I2C1A_CLK

GPIO132/I2C1G_DATA

GPIO140/I2C1G_CLK

GPIO143/I2C1E_DATA

GPIO144/I2C1E_CLK

SYSPWR_PRES

DN1_DP1A/THERM DP1_DN1A/VREF_T

GPIO002/THERMTRIP3#

VCC_PWRGD

GPIO106

GPIO127/A20M

GPIO157/LED0

VCI_OVRD_IN

VCI_OUT VCI_IN0# VCI_IN1# VCI_IN2# VCI_IN3#

VREF_PECI

PECI_DAT

DN2_DP2A DP2_DN2A DN3_DP3A DP3_DN3A DN4_DP4A DP4_DN4A

THERMTRIP2#

V_ISYS0 V_ISYS1

MEC5085-LZY_DQFN132_11X11

THSEL_STRAP

1: Channel 1 will provide Thermistor

1: Channel 1 will provide Thermistor1: Channel 1 will provide Thermistor Readings

Readings

ReadingsReadings 0: Channel 1 will provide Diode Readings

0: Channel 1 will provide Diode Readings

0: Channel 1 will provide Diode Readings0: Channel 1 will provide Diode Readings

4700p240K 4700p130K 4700p 4700p 4700p 4700p

A10 B10 B8 B27 B44 B46 B26 A25 B36 B37 B38 A34 A35 A36 A40 B43 A45 B65

nFWP

B57 B1 A55 A1 B28 B2 A8 B9 A9 B39 A44

A54 B58

A3 B4 A4 B5 B7 A7 B48 B49 A47 B50 B52 A49 B53 A50

A59

B62

BGP0

A64 A60 B67 A63 B63 B68

B51 A48

B13 A13 B14 A14 A15 B16 A16 B17 B15

VIN

A17

VSET

A12

VCP

B34 A2 B29 A46 B61 A57

R1069 1K_0402_5%

REV

12" 14" 15" 17" *** ***1K

2

PANEL_ID BOARD_ID TCABLE_ID

TCABLE_ID <44>

LAN_WAKE#

LAN_WAKE# <23,35>

HOST_DEBUG_TX PCH_PCIE_WAKE# RUNPWROK EN_INVPWR SIO_SLP_S4# SIO_SLP_LAN#

SIO_SLP_S3#

MSDATA MSCLK PCH_RSMRST# FWP#

BAT1_LED# BAT2_LED# IMVP_VR_ON_EC SIO_SLP_A#

RUN_ON CV2_ON RESET_OUT# VCCST_PWRGD_EC

SIO_PWRBTN#

DOCK_TNY_SMB_DAT DOCK_TNY_SMB_CLK

SUSACK#

ENVDD_PCH UPD_GPU_SMBDAT UPD_GPU_SMBCLK CHARGER_SMBDAT CHARGER_SMBCLK SIO_SLP_SUS# PBAT_PRES# USH_SMBDAT USH_SMBCLK

SYSPWR_PRES

EC_FPM_EN ACAV_IN ALWON POWER_SW_IN# DOCK_PWR_SW# TDOCK_PWR_BTN# POA_WAKE#

+PECI_VREF PECI_EC_R

REM_DIODE1_N REM_DIODE1_P REM_DIODE2_N REM_DIODE2_P REM_DIODE3_N REM_DIODE3_P REM_DIODE4_N REM_DIODE4_P

VSET_5085

THERMATRIP2# THERMATRIP3# THSEL_STRAP H_PROCHOT# I_BATT

1 2

PCH_PCIE_WAKE# <23> RUNPWROK <45> EN_INVPWR <30>

SIO_SLP_S4# <11,23,37,52,54>

PCH_ALW_ON

BREATH_LED#

SIO_SLP_LAN# <23,40>

PCH_ALW_ON <49,58>

SIO_SLP_S3# <7,11,23,37,44>

12

R8020_0402_5% @

PCH_RSMRST# <7>

BREATH_LED# <43,47>

trace width 20 mils

BAT1_LED# <47>

trace width 20 mils

BAT2_LED# <47>

IMVP_VR_ON_EC <7> SIO_SLP_A# <23,37,49> EC_32KHZ_ECE5048 <45>

ME_SUS_PWR_ACK <23>

RUN_ON <46,49>

CV2_ON <37> RESET_OUT# <7,23>

1 2

R43 0_0402_5%@

AC_PRESENT <23> SIO_PWRBTN# <7,23>

DOCK_TNY_SMB_DAT <43,44>

DOCK_TNY_SMB_CLK <43,44>

A_ON <49>

12

R7970_0402_5% @

SIO_EXT_WAKE# <24>

SUSACK# <23>

ENVDD_PCH <19,30>

UPD_GPU_SMBDAT <18,44>

UPD_GPU_SMBCLK <18,44>

CHARGER_SMBDAT <57>

CHARGER_SMBCLK <57>

SIO_SLP_SUS# <11,49,58,59>

PBAT_PRES# <44,50,57>

USH_SMBDAT <28,37>

USH_SMBCLK <28,37>

EC_FPM_EN <37> ACAV_IN <18,57,60>

ALWON <51>

TDOCK_PWR_BTN# <44> POA_WAKE# <37>

1 2

R953 33_0402_5%

1 2

C1343 2200P_0402_50V7K

1 2

C1350 2200P_0402_50V7K

1 2

C1351 2200P_0402_50V7K

1 2

C1346 2200P_0402_50V7K

T155PAD~D @

I_ADPI_ADP_R

12

R134 4.7K_0402_5%

THERMATRIP3# <18>

H_PROCHOT# <7,57,61,64> I_BATT <57>

100P_0402_50V8J

@

C339

100P_0402_50V8J

@

C340

PROPRIETARY NOTE:

PROPRIETARY NOTE: PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS

TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS

TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THISTRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

DOCUMENT MAY NOT

DOCUMENT MAY NOTDOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL.

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL.

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL.BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,

IN ADDITION,

IN ADDITION,IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED

NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED

NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSEDNEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

TO ANY THIRD

TO ANY THIRDTO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

I_ADP <57>

C292 Place near U51.A48

C292 Place near U51.A48C292 Place near U51.A48

PECI_EC_R

DP1/DN1 for CPU OTP on Q16, place Q16

DP1/DN1 for CPU OTP on Q16, place Q16DP1/DN1 for CPU OTP on Q16, place Q16 close to CPU and C273 close to Q16.

close to CPU and C273 close to Q16.

close to CPU and C273 close to Q16.close to CPU and C273 close to Q16.

DN1a/DP1a for CPU VR on Q26, place Q26

DN1a/DP1a for CPU VR on Q26, place Q26DN1a/DP1a for CPU VR on Q26, place Q26 close to CPU and C339 close to Q26

close to CPU and C339 close to Q26

close to CPU and C339 close to Q26close to CPU and C339 close to Q26

MMBT3904WT1G_SC70-3

2

E

31

Q26

B

2

C

1

DP2/DN2 for MXM(TOP side) on Q27, place Q27

DP2/DN2 for MXM(TOP side) on Q27, place Q27DP2/DN2 for MXM(TOP side) on Q27, place Q27 close to MXM(TOP side) and C291 close to Q27.

close to MXM(TOP side) and C291 close to Q27.

close to MXM(TOP side) and C291 close to Q27.close to MXM(TOP side) and C291 close to Q27.

DN2a/DP2a for M.2 2280 on Q17, place Q17

DN2a/DP2a for M.2 2280 on Q17, place Q17DN2a/DP2a for M.2 2280 on Q17, place Q17

close to M.2 2280 and C340 close to Q17

close to M.2 2280 and C340 close to Q17close to M.2 2280 and C340 close to Q17

MMBT3904WT1G_SC70-3

1

E

31

Q17

B

2

C

2

PCH_DPWROK <23>

VCCST_PWRGD <7>

100K_0402_5%

R874 1K_0402_5%

12

R876

1 2

100P_0402_50V8J

@

1

C273

2

@

C291

1

2

0.1U_0402_25V6K

1

2

C

2

B

E

Q16

3 1

MMBT3904WT1G_SC70-3

C

2

B

E

Q27

3 1

MMBT3904WT1G_SC70-3

H_PECI <7,19>

C1343, C1350, C1351, C1346 Place

C1343, C1350, C1351, C1346 PlaceC1343, C1350, C1351, C1346 Place near U51

near U51

near U51near U51

C292 47P_0402_50V8J@

DOCK_PWR_SW#

1.2V_SUS_PWRGD<52>

1 2

R866 close to U51 at least

R866 close to U51 at leastR866 close to U51 at least

1 2

250mils

250mils250mils

R866 0_0402_5%@

C740

REM_DIODE1_P

REM_DIODE1_N

REM_DIODE2_P

REM_DIODE2_N

+RTC_CELL

100K_0402_5%

12

R819

1U_0402_6.3V6K

1

2

SIO_SLP_S3#

1.2V_SUS_PWRGD

SN74AHC1G08DCKR_SC70-5

+3.3V_ALW2

+1.0V_RUN

+VCC_IO

1 3

D

Q370

@

DMN65D8LW-7_SOT323-3

1 2

R435 0_0402_5%

DP3/DN3 for SODIMM(TOP) on Q14,

DP3/DN3 for SODIMM(TOP) on Q14, DP3/DN3 for SODIMM(TOP) on Q14, place Q14 close to SODIMM(TOP) and C272 close

place Q14 close to SODIMM(TOP) and C272 close

place Q14 close to SODIMM(TOP) and C272 closeplace Q14 close to SODIMM(TOP) and C272 close to Q14

to Q14

to Q14to Q14

100P_0402_50V8J

@

1

C272

2

DP4/DN4 for WWAN on Q15,

DP4/DN4 for WWAN on Q15, DP4/DN4 for WWAN on Q15, place Q15 close to WiGig and C288 close to

place Q15 close to WiGig and C288 close to

place Q15 close to WiGig and C288 close toplace Q15 close to WiGig and C288 close to Q15

Q15

Q15Q15

100P_0402_50V8J

@

C288

1

2

1

C733

@

1 2

1U_0402_6.3V6K

1 2

R825 10K_0402_5%

C734

TDOCK_PWR_BTN#

POA_WAKE#

SUSACK#

AC_PRESENT

DOCK_TNY_SMB_DAT

DOCK_TNY_SMB_CLK

+3.3V_ALW

@

0.1U_0402_25V6

5

1

P

IN1

O

2

IN2

G

U9

3

SIO_SLP_S3#

2

G

1 2

R399

2.2K_0402_5%

S

PCH_THERMTRIP#<7,14,15,16,17,19>

Channel

ChannelChannel

DP1/DN1

DP1/DN1DP1/DN1

DP1a/DN1a

DP1a/DN1aDP1a/DN1a

DP2/DN2

DP2/DN2DP2/DN2

DP2a/DN2a

DP2a/DN2aDP2a/DN2a

DP3/DN3

DP3/DN3DP3/DN3

DP4/DN4

DP4/DN4DP4/DN4

C

2

B

E

Q14

3 1

MMBT3904WT1G_SC70-3

C

2

B

E

Q15

3 1

MMBT3904WT1G_SC70-3

DELL CONFIDENTIAL/PROPRIETARY

Compal Electro nics, Inc.

Title

KBC (MEC5085 )

Size Document Number Rev

Date: Sheet of

1

DOCK_PWR_BTN# <43>

C787

1 2

4

+3.3V_ALW

2

B

E

LA-C551P

12

R870100K_0402_5%

12

R880100K_0402_5%

12

R83710K_0402_5% @

12

R83510K_0402_5%

12

R8382.2K_0402_5%

12

R8412.2K_0402_5%

RUN_ON_AND <53>

8.2K_0402_5%

12

R396

THERMATRIP2#

MMBT3904WT1G_SC70-3

C

Q28

3 1

Location

LocationLocation

CPU

CPUCPU OTP

OTP

OTPOTP

CPU

CPUCPU VR

VR

VRVR MXM(TOP)

MXM(TOP)

MXM(TOP)MXM(TOP)

M.2 2280

M.2 2280M.2 2280

DIMM(TOP)

DIMM(TOP)DIMM(TOP)

WWAN

WWANWWAN

REM_DIODE3_P

REM_DIODE3_N

REM_DIODE4_P

REM_DIODE4_N

+RTC_CELL

1

2

46 74Tuesday, August 18, 2015

+3.3V_ALW

0.1U_0402_25V6K C327

1.0

5

1 2

+3.3V_RUN

R383 10K_0402_5%

PCH_SATA_LED#<19>

1 2

+3.3V_SSD1

R384 10K_0402_5%

SLOT3_SATA_LED#<39>

D D

C C

+3.3V_SSD2

+3.3V_RUN

1 2

R385 10K_0402_5%

SLOT4_SATA_LED#<39>

1 2

R387 10K_0402_5%

SATAE_LED#<41>

21

D97 RB751S40T1G_SOD523-2

21

D98 RB751S40T1G_SOD523-2

21

D99 RB751S40T1G_SOD523-2

21

D100 RB751S40T1G_SOD523-2

MASK_SATA_LED#<45>

LED_SATA_DIAG_OUT#<45>

Q74B

DMN66D0LDW-7_SOT363-6

4

5

3

4

+3.3V_ALW

10K_0402_5%

12

D62

21

RB751S40T1G_SOD523-2

SYS_LED_MASK#

HDD LED

HDD LED HDD LED

R932

Q74A

DMN66D0LDW-7_SOT363-6

2

+5V_ALW

Q86

2

DDTA114EUA-7-F_SOT323-3

1 3

1 2

R943 1K_0402_5%

SATA_SIDE_LED

61

LED Circuit Control Table

SYS_LED_MASK# LID_CL#

Mask All LEDs (Sniffer Function) Mask Base MB LEDs (Lid Closed) Do not Mask LEDs (Lid Opened) 11

3

0 1 0

2

Breath LED

Breath LEDBreath LED

Q359

DMN65D8LW-7_SOT323-3

D

S

BREATH_LED#<43,46>

BATT LED

BATT LEDBATT LED

X

G

2

MASK_BASE_LEDS#

BAT2_LED#<46>

13

R956 1K_0402_5%

BREATH_WHITE_LED

1 2

R955 1K_0402_1%

1 2

R130 560_0402_5%

BREATH_LED TOP view.

BREATH_WHITE_LED <44>

BREATH_LED#_Q

BREATH_LED side view.

BATT_WHITE_LEDBAT2_LED#

1

1 2

R131 560_0402_5%

7

G1

8

G2

9

G3

10

G4

BATT_YELLOW_LED

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

LED / Screw hole

LA-C551P

1

47 74Tuesday, August 18, 2015

1.0

BAT1_LED#

BAT1_LED#<46>

To LED/B Conn

B B

SYS_LED_MASK#<35,45>

Fiducial Mark

FD1

@

1

FIDUCIAL MARK~D

FD2

@

1

FIDUCIAL MARK~D

FD3

@

1

FIDUCIAL MARK~D

A A

FD4

@

1

FIDUCIAL MARK~D

@

H_3P0

H2

@

H_3P0

1

H19

@

H_3P0

@

H_1P15

@

H18

H_3P8

H_3P0

1

H34

@

H33

@

H_1P15

H_3P8

1

H17

@

H16

H_3P8

1

H32

@

H_3P3

1

5

H7

@1H8

@

H_2P8

H_3P0

1

H20

@

H_3P0

1

@

H35

H_3P8

1

H23

@1H22

@

H21

H_2P0N

H_3P0

1

H36

H38

@

H37

@

H_3P8

1

@

H_3P0

@

H_3P3

@

H_3P0

H24

H39

H11

@

H9

H_3P8

1

@

H26

@

H_3P3

H_5P2

1

@1H43

H41

@

H40

@

H_1P2

H_3P0

1

H14

@

H_3P8

1

H28

@

H29

@

H27

H_3P3

H_5P2

1

H42

@

H44

@

H_1P2

4

H10@

H_2P8

H_2P8X2P0

1

SYS_LED_MASK#

LID_CL#

LID_CL#<44,45>

1

2

+3.3V_ALW

IN1

IN2

3

C778

@

1 2

0.1U_0402_25V6K

U58

5

SN74AHC1G08DCKR_SC70-5

P

4

O

G

3

MASK_BASE_LEDS#

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

To LED/B ConnTo LED/B Conn

+5V_ALW

0.1U_0402_10V6K

1

C6

2

JLED1

1

2

1

2

2 2

3

4

4 4

5

6

6 6

ACES_50554-00641-001

CONN@

CIS link OK

CIS link OKCIS link OK

BREATH_LED#_Q BATT_YELLOW_LED BATT_WHITE_LED SATA_SIDE_LED

5

4

3

2

1

Touch Pad

+3.3V_RUN +3.3V_TP

PJP@

PJP14

1 2

DAT_TP_SIO<46>

CLK_TP_SIO<46>

I2C_1_SDA<24>

I2C_1_SCL<24>

PAD-OPEN1x1m

D D

C C

+3.3V_TP

4.7K_0402_5%

12

RZ19

RZ18

DAT_TP_SIO

330P_0402_50V8J

12

CZ31EMC@

CZ30EMC@

EMI depop

EMI depopEMI depop location

location

locationlocation

+3.3V_TP +3.3V_TP

4.7K_0402_5%

12

RZ36

RZ37

I2C_1_SDA

I2C_1_SCL I2C_1_SCL_R

CLK_TP_SIO CLK_TP_SIO

1 2

R3752 0_0402_5%@

1 2

R3758 0_0402_5%@

10K_0402_5%

12

RZ115

RZ114

I2C_1_SDA_R

Keyboard

+3.3V_TP

KB_DET#<24>

+5V_RUN +3.3V_ALW

BC_INT#_ECE1117<46>

BC_DAT_ECE1117<46>

BC_CLK_ECE1117<46>

DAT_TP_SIO

TOUCHPAD_INTR#<22>

I2C_1_SDA_R I2C_1_SCL_R

+5V_RUN+3.3V_ALW+3.3V_TP

0.1U_0402_25V6

12

C1410@

C1414@

Place close to JKBTP1

JKBTP1

1

2

2 2

3

4

4 4

5

6

6 6

7

8

8 8

9

10

10 10

11

12

12 12

13

14

14 14

15

16

16 16

17

18

18 18

19

20

20 20

ACES_50559-02001-001

CIS link OK

CIS link OKCIS link OK

0.1U_0402_25V6

C1411@

21

G1

22

G2

23

G3

24

G4

B B

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

KB / TP / RSMRST#

LA-C551P

48 74Tuesday , August 18, 2015

1

1.0

5

+3.3V_M Source

+3.3V_M Source+3.3V_M Source

A_ON<46>

D D

SIO_SLP_A#<23,37,46>

C C

B B

A A

SIO_SLP_SUS#<11,46,58,59>

PCH_ALW_ON<46,58>

1 2

R878 0_0402_5%@

1 2

R877 0_0402_5%@

3.3V_RUN_GFX_ON

1 2

R3760 0_0402_5%@

1 2

R3759 0_0402_5%

5

+3.3V_ALW

A_ON_R

+5V_ALW

+3.3V_ALW

+5V_ALW

+1.0V_PRIM to +1.0V_RUN

+1.0V_PRIM to +1.0V_RUN+1.0V_PRIM to +1.0V_RUN

+1.0V_PRIM

RUN_ON

+5V_ALW

MXM_PWR_SRC Source

+PWR_SRC_MXM

12

13

D

2

G

S

MXM_PWR_SRC Source

MXM_PWR_SRC SourceMXM_PWR_SRC Source

+PWR_SRC_MXM +MXM_PWR_SRC+MXM_PWR

100K_0402_5%

R940

+MXM_SRC_EN#

20K_0402_5%

R944

Q87 DMN65D8LW-7_SOT323-3

UZ2@

1

VIN

2

VIN

3

ON

4

VBIAS

AOZ1336_DFN8_2X2

+3.3V_ALW_PCH Source

+3.3V_ALW_PCH Source+3.3V_ALW_PCH Source

UZ27

1

VIN

2

VIN

3

ON

4

VBIAS

AOZ1336_DFN8_2X2

UZ23

1

VOUT

VIN

2

VOUT

VIN

3

ON

4

VBIAS

GND GND

AOZ1336_DFN8_2X2

Q186

1 2 3 6

AO4435L_SO8

4

12/2 draft cost BOM

0.01U_0402_50V7K

1

C774

2

VOUT VOUT

CT

4

+3.3V_M+3.3V_M_PW R

PJP19

+3.3V_M_PWR

7

VOUT

8

VOUT

6

CT

5

GND

9

GND

7 8

6

CT

5

GND

9

GND

7 8

6

470P_0402_50V7K

1

5 9

2

PJP17

@

8 7

5

1 2

PAD-OPEN 4x4m

PJP18

@

1 2

PAD-OPEN 4x4m

@

2

112

10U_0603_6.3V6M

JUMP_43X79

@

1

C513

470P_0402_50V7K

@

2

C547

1

+3.3V_ALW_PCH+3.3V_ALW_P CH_PWR

PJP15

@

2

112

10U_0603_6.3V6M

JUMP_43X79

1

470P_0402_50V7K

2

1

C1423

C1445

2

C1444

+1.0V_RUN+1.0V_RUN_PWR

PJP16

@

2

112

10U_0603_6.3V6M

JUMP_43X79

1

C1424

2

10U_1206_25V6M

100K_0402_5%

12

R935

1

C776

2

3

+3.3V_ALW to +3.3V_MXM

+3.3V_ALW to +3.3V_MXM+3.3V_ALW to +3.3V_MXM

+5V_ALW to +5V_MXM

+5V_ALW to +5V_MXM+3.3V_M Source

+5V_ALW to +5V_MXM+5V_ALW to +5V_MXM

UZ26

1

VOUT1

VIN1

2

VOUT1

VIN1

3

CT1

ON1

4

GND

VBIAS

5

ON2

CT2

6

VIN2

VOUT2

7

VIN2

VOUT2

GPAD

EM5209VF_DFN14_3X2

+5V_RUN Source

+5V_RUN Source +3.3V_RUN Source

+5V_RUN Source+5V_RUN Source

+5V_ALW

RUN_ON_R

1 2

R881 0_0402_5%@

+5V_ALW

+3.3V_ALW

+1.8V_ALW

3.3V_RUN_GFX_ON<21,45>

+5V_ALW

+3.3V_ALW

RUN_ON<46>

14

+5V_MXM_PWR

13

12

11

10

9 8

15

2

1

+3.3V_RUN Source

+3.3V_RUN Source+3.3V_RUN Source

UZ20

1

VIN1

2

VIN1

3

ON1

4

VBIAS

5

ON2

6

VIN2

7

VIN2

EM5209VF_DFN14_3X2

RUN_ON

+5V_ALW

2

PJP20

@

2

C357

10U_0603_6.3V6M

1

JUMP_43X79

2

+3.3V_MXM_PWR

470P_0402_50V7K

2

C437

C542

1

14

VOUT1

13

VOUT1

12

CT1

11

GND

10

CT2

9

VOUT2

8

VOUT2

15

GPAD

+1.8V_RUN Source

+1.8V_RUN Source+1.8V_RUN Source

UZ22

1

VOUT

VIN

2

VOUT

VIN

3

ON

4

VBIAS

GND GND

AOZ1336_DFN8_2X2

+5V_MXM+5V_MXM_PWR

112

+3.3V_MXM_PWR +3.3V_MXM

@

2

10U_0603_6.3V6M

JUMP_43X79

C764

1

2

+5V_RUN_PWR

1

2

470P_0402_50V7K

1000P_0402_50V7K

C544

2

C543

1

7 8

6

CT

5 9

PJP21

10U_0805_10V6K

C514

1

2

112

+5V_RUN+5V_RUN_PWR

PJP22

12

PAD-OPEN 4x4m

PJP@

+3.3V_RUN_PWR +3.3V_RUN

+3.3V_RUN_PWR

+1.8V_RUN_PWR

470P_0402_50V7K

C539

1

PJP23

@

2

112

10U_0603_6.3V6M

JUMP_43X79

C450

1

2

+1.8V_RUN+1.8V_RUN_PW R

PJP24

@

2

112

10U_0603_6.3V6M

JUMP_43X79

C767

1

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

4

3

2

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

Power Control

LA-C551P

49 74Tuesday, August 18, 2015

1

1.0

5

EMI Part (47.1)

PL1

EMC@

SMB3025500YA_2P

+PWR_SRC

D D

EMI Part (47.1)

C C

Primary Battery Connector

12

PC4

EMC@

2200P_0402_50V7K

1 2

CONN@

SUYIN_200045GR009M28QZR

9

1

8

2

7

3

6

4

5

4

6

3

7

2

8

1

9

10

GND

11

GND

PBATT1

Z4304 Z4305 Z4306

PC31

@

0.1U_0603_25V7K

GND

12

PC30

@

10U_0805_25V6K

1

EMC@

PD2 TVNST52302AB0_SOT523-3

2

3

1

+

PC1

2

PR3

4 5 3 6 2 7 1 8

100_0804_8P4R_5%

100U_25V_M

EMI Part (47.1)

EMC@

B B

NB_PSID

PESD5V0U2BT_SOT23-3

@EMC@

PD4

BLM15BX102SN1D_2P

2

3

1

6/8 add diode for ESD team Matt request

EMI Part (47.1)

PL5

EMC@

SMB3025500YA_2P

1 2

PL4

EMC@

SMB3025500YA_2P

1 2

PJPDC1

A A

1

2

3

4

5

6

+DCIN_JACK

7

8

9

10

11

ACES_50493-0110N-001

CONN@

5

1

PD8

12

@

PC11

1000P_0402_50V7K

EMC@

12

2

VZ0603M260APT_0603

PC15

0.1U_0603_25V7K

@EMC@

+DC_IN

2

PQ8B

16

DCX124EK-7-F_SC74R-6

1 2

4 3

5

12

PR19

4.7K_0805_5%

@

PQ8A

4/29 PQ8 SB000009N00 is X1 code ,replaced to second source SB000009P80

4

DVT1.2 change i tem

+PWR_SRC_MXM

ESD Diodes

1

EMC@

PD3 TVNST52302AB0_SOT523-3

2

3

PL3

12

DC_IN+ Source

+DC_IN

12

PR16

1M_0402_5%

PC9 0.022U_0603_50V7K

AC_DIS <45,60>

12

PR22

4

1 2 3

PR20

1 2

10K_0402_5%

1M_0402_5%

DVT2.0 combine H42,H44e to one schematic

BOM structure a dd H42@,H44@

different betwe en H42&H44e

ESD (47.2)

DVT2.1 change i tem X-build change i tem

EMI Part (47.1)

FBMJ4516HS720NT_2P

PBATT+_C

PBAT_SMBCLK <46> PBAT_SMBDAT <46>

PR7

@

1 2

0_0402_5%

1 3

D

S

PQ2 FDV301N_G_NL_SOT23-3~D

G

2

+DC_IN_SS

12

PR18

100K_0402_5%

2

C

PQ3

B

MMST3904-7-F_SOT323-3

E

3 1

PC14

10U_0805_25V6K

12

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL

PQ5SI7149DP

4

SOFT_START_GC < 60>

PR10

1 2

100K_0402_1%

PR12

15K_0402_1%

1 2

5

3

EMC@

1 2

EMC@

1 2

PR9

33_0402_5%

1 2

PL2

PL6

+5V_ALW

12

+3.3V_ALW

12

PBATT+

PR2

100K_0402_5%

PD5

1 2

SDMK0340L-7-F_SOD323-2

SLICE_BAT_PRES#<43,45,60>

DOCK_PSID<43>

+3.3V_ALW

PESD5V0U2BT_SOT23-3

PR8

2.2K_0402_5%

1 2

NB_PSID_TS5A63157

6/8 add diode f or ESD team Ma tt request

PR11

10K_0402_1%

PR13

1 2

10K_0402_5%@

PQ1 AO3409_SOT23

1 3

D

2

0_0402_5%

1 2

PR33

@

12

3

@EMC@

PD6

PSID_DISABLE# <45>

2

+COINCELL

12

PR1

+3.3V_RTC_LDO

BAS40CW_SOT323-3

PBAT_PRES# <44,46,57>

S

G

1500P_0402_50V7K

2

1

1K_0402_5%

Z4012

2

3

+RTC_CELL

PD1

1

PC2 1U_0603_10V4Z

2

DOCK_TNY_SMBUS_ALRT# <43,44,45>

PC5

6/15 Change PU1 from SA00003DN00 to SA00001WK00(原2nd source)for ESD issue，so PD4,PD6 depop temporarily for cost

PU1

1

IN

NO

2

V+

GND

NC3COM

TS5A63157DCKR_SC70-6

DELL CONFIDENTIAL/PROPRIETARY

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

1

COIN RTC Battery

JRTC1

+COINCELL

Move to power schematic

6

GPIO_PSID_SELECT <45>

5

+5V_ALW

4

PS_ID <46>

PT1@

PAD~D

Title

Size Document Number Rev

Date: Sheet of

1

2

3

GND

4

GND

ACES_50271-0020N-001

Compal Electronics, Inc.

+DCIN

LA-C551P

1

1.0

50 74Tuesday, August 18, 2015

1.0

A

B

C

D

E

1 1

ALW_P WRGD_3V_ 5V<7 >

PL100

1UH_6.6A _20%_5X5X 3_M

1 2

2 2

+PWR_SRC

+3VALWP

3 3

3VALWP Ripple voltage Static load 3% / Dynamic load 5% Frequency 355kHz TDC 8.12 A Peak Current 11.61 A OCP current 13.93 A TYP MAX H/S Rds(on) 24mohm , 30mohm L/S Rds(on) 10.8mohm , 13.6mohm Choke DCR:15 Bulk cap ESR 25mohm

4 4

+DC1_PWR_SRC

12

@EMC@

PC103

0.1U_0402_25V6

2.2UH_12 A_20%_10X 10X4_M

1 2

1

+

PC120 330U_D2E _6.3VM_R25 M

2

12

PC105

@

2200P_0402_50V7K

PL101

680P_06 03_50V7K

12

PC101

PR111

4.7_120 6_5%

PC111

5

10U_0805_25V6K

PQ100

12

SNUB_3V

12

4

123

SIS412DN-T1-GE3_POWERPAK8-5

5

PQ102

4

FDMC7692S_MLP8-5

123

PC109

0.1U_060 3_25V7K

1 2

ALWON<46>

+3.3V_ALW

100K_04 02_1%

0_0402_ 5%

1 2

PR108

@

BST_3V_C BST_3V

3V_5V_E N

+3.3V_ALW2

PR100

6.49K_0 402_1%

1 2

PR102 10K_040 2_1%

1 2

PR105

22.1K_0402_1%

PR107

1 2

PGOOD_3 V_5V

UG_3V

PR110

2.2_060 3_5%

1 2

+DC1_PWR_SRC

PR113

0_0402_ 5%

1 2

PC119

@

12

LG_3V

12

1U_0603_10V6K

FB_3V

3V_5V_E N

SW2

+3.3V_RTC_LDO

12

PR103

0_0402_5%

@

PU101

4

5

CS2

6

EN2

7

PGOOD

10

TPS51285 BRUKR_QFN20_ 3X3

DRVH2

9

VBST2

8

SW2

DRVL211VIN12VREG5

12

PC117

0.1U_0603_25V7K

+3VALW P

PC100

4.7U_0603_10V6K

VFB2

@

12

FB_5V

2

3

VFB1

VREG3

EN1

13

20

3V_5V_EN

12

PC118

4.7U_0603_10V6K

PJP100

@

1 2

PAD-OPEN 43x118 PJP101

1 2

PAD-OPEN 43x118

PR101

15K_040 2_1%

1 2

PR104 10K_040 2_1%

1 2

1

CS1

PAD

VO1

VCLK

DRVH1

VBST1

SW1

DRVL1

15

12

PR106

22.1K_0402_1%

21

14

PR114 200_040 2_1%

1 2

19

UG_5V

16

17

18

2.2_060 3_5%

BST_5V BST_5V_C

1 2

SW1

LG_5V

+5V_ALW2

+3.3V_AL W

+5VALW P

PR109

0.1U_060 3_25V7K

@

PJP102

1 2

PAD-OPEN 43x118 PJP103

@

1 2

PAD-OPEN 43x118

PC110

1 2

+5V_ALW

+DC1_PWR_SRC

12

5

4

PQ101

123

SIS412DN-T1-GE3_POWERPAK8-5

5

PQ103

FDMC7692S_MLP8-5

123

5VALWP Ripple voltage Static load 3% / Dynamic load 5% Frequency 300kHz TDC 7.8 A Peak Current 11.15 A OCP current 13.38 A TYP MAX H/S Rds(on) 24mohm , 30mohm L/S Rds(on) 10.8mohm , 13.6mohm Choke DCR Max:11.8mohm Choke Ityp:10A / Isat:16A Bulk cap ESR 25mohm

PC102

10U_0805_25V6K

PL102

3.3UH_PIM B104T-3R3MS_1 0A_20%

1 2

12

PR112

4.7_120 6_5%

SNUB_5V

12

PC114

680P_06 03_50V7K

+5VALWP

1

+

PC121 330U_D2E _6.3VM_R25 M

2

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL

DELL CONFIDENTIAL/PROPRIETARY

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

C

D

Title

Size Document Nu mber Rev

Date: Sheet of

Compal Electronics, Inc.

+5V_ALW/3.3V_ALW

LA-C551P

51 74Tuesday, Au gust 18, 20 15

E

1.0

DELL CONFIDENTIAL/PROPRIETARY

5

PJP200

+PWR_SRC

D D

+1.2V_MEN_P

C C

1.2Volt +/- 5% TDC: 7.5 A Peak Current: 11 A OCP current: 13 .2A Rds(on): 3.5m o hm(max) Choke DCR 3.5 mohm(max)

@

PAD-OPEN 1x2m~D

21

@

1.0UH_PCMB104T-1R0MH_18A_20%

1 2

220U_D2_2VY_R17M

1

PC201

+

2

EMI Part (35.33 )

1.2V_B+

12

PC203

PC202

10U_0805_25V6K

PL201

PR202

4.7_1206_5%

EMC@

SNUB_1.35V

EMC@

PC212

680P_0603_50V7K

EMI Part (35.33 )

12

@EMC@

PC205

PC204

0.1U_0402_25V6 2200P_0402_50V7K

PQ201

12

PQ202

12

SIO_SLP_S4#<11,23,37,46,54>

4

PR200

1 2

2.2_0603_5%

PC206

5

0.22U_0603_10V7K

1 2

4

123

SIR472DP-T1-GE3_POWERPAK8-5

5

4

321

SIRA06DP-T1_POWERPAK-SO8-5

PR206

200K_0402_5%

1 2

+5V_ALW

100K_0402_1%

1.2V_SUS_PWRGD<46>

PR203

5.1_0603_5%

1 2

+3.3V_ALW

12

PR209

12

PR201

5.11K_0402_1%

1 2

12

PC210 1U_0603_10V6K

0.6V_DDR_VTT_ON<14>

@

PC215

1U_0402_6.3VX5R

BOOT_1.2V

DH_1.2V

SW_1.2V

DL_1.2V

PC213

1U_0603_10V6K

VDD_1.2V

CS_1.2V

VDDP_1.2V

12

+5V_ALW

1.2V_SUS_PWRGD

1.2V_B+

S5_1.2V

PR210

2.2_0603_5%

15

14

13

12

11

1 2

LGATE

PGND

CS

VDDP

VDD

PR205

1M_0402_1%

1 2

PR208

100K_0402_5%

+1.2V_MEN_P

3

VLDOIN_1.2V

16

18

17

19

BOOT

PHASE

UGATE

RT8207MZQW_WQFN20_3X3

S5

PGOOD

TON

8

7

9

10

S3_1.2V

@

PJP201

PAD-OPEN1x1m

12

+1.2V_MEN_P

2

0.675Volt +/- 5 % TDC 1.05A Peak Current 1 .5A OCP Current 1.8 A

1

+0.6V_P

20

PU200

21

VTT

PAD

1

VLDOIN

VTTGND

2

VTTSNS

3

GND

4

VTTREF

5

VDDQ

FB sense trace

FB

S3

6

when FB pull do wn to GND

PC211 220P_0402_50V8J@

1 2

PR204

12

12K_0402_1%

1 2

PR207 20K_0402_1%

1.2V_FB

12

PC207

22U_0805_6.3VAM

+V_DDR_REF

+1.2V_MEN_P

12

PC214 .1U_0402_16V7K

@

+V_DDR_REF

PC209

0.033U_0402_16V7K

+1.2V_MEN_P

+0.6V_P

PJP203

@

2

JUMP_1x3m

PJP204

@

2

JUMP_1x3m

@

PJP202

PAD-OPEN1x1m

112

12

+1.2V_MEM

+0.6V_DDR_VTT

FB sense trace

B B

Mode S3 S5 +1.35V_MEN +V_DDR_REF +0.675V_P S5 L L off off off S3 L H on on off(Hi-Z) S0 H H on on on

A A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DELL CONFIDENTIAL/PROPRIETARY

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

1.2VP/0.6VSP

LA-C551P

1

52 74Tuesday, August 18, 2015

1.0

5

D D

+PWR_SRC

+PWR_SRC+PWR_SRC

+3.3V_ALW

12

PR306

@

0_0402_5%

ILMT_0.95V

12

C C

PR308

0_0402_5%

@

PJP301

@

PAD-OPEN 1x2m~D

21

12

+3.3V_ALW

+VCC_IO

+VCC_IO+VCC_IO

TDC 3.85A

TDC 3.85ATDC 3.85A

Peak Current 5.5 A

Peak Current 5.5 APeak Current 5.5 A

OCP Current 8 A

OCP Current 8 AOCP Current 8 A

TYP

TYP TYP

MAX

MAXMAX

Choke DCR 13.0mohm ,

Choke DCR 13.0mohm ,Choke DCR 13.0mohm ,

14.0mohm

14.0mohm14.0mohm

12

PC311

PC300

0.1U_0402_25V6

2200P_0402_50V7K

10U_0805_25V6K

@EMC@

+V0.95SP_B+

12

PC303

1 2

PR315

@

100K_0402_1%

4

ILMT_0.95V

0.95V_MP_PWROK

PU300

8

IN

EN

GND

ILMT

PG

BS

FB

BYP

LDO

9

3

2

SYX198DQNC_QFN10_3X3

LX

1

BST_+V0.95SP

6

10

4

7

5

12

0.1U_0603_25V7K

SW_+V0.95SP

12

PC309

4.7U_0603_6.3V6K

RUN_ON_AND

PC302

1 2

+3.3V_ALW

PC310

4.7U_0603_6.3V6K

3

12

PC312

@

1000P_0402_50V7K

BST_+V0.95SP_C

12

1M_0402_1%

PR312

0_0603_5%

1 2

PR303

@

EMC@

4.7_1206_5%

1 2

1UH_6.6A_20%_5X5X3_M

FB_+V0.95SP

RUN_ON_AND <46>

PR305

EMC@

SNB_0.95V

PL301

1 2

12

PR309

1K_0402_5%

12

PR310

62K_0402_1%

2

+VCC_IOP

PC301

680P_0603_50V7K

1 2

12

PR311

PC304

10_0402_1%

330P_0402_50V7K

PR307

1 2

36.5K_0402_1%

proximal

proximalproximal PR311 0 ohm PR314 10 ohm PR316 10

PR311 0 ohm PR314 10 ohm PR316 10

PR311 0 ohm PR314 10 ohm PR316 10PR311 0 ohm PR314 10 ohm PR316 10 ohm

ohm

ohmohm

remote

remoteremote PR311 10 ohm PR314 0 ohm PR316 0

PR311 10 ohm PR314 0 ohm PR316 0

PR311 10 ohm PR314 0 ohm PR316 0PR311 10 ohm PR314 0 ohm PR316 0 ohm

ohm

ohmohm

12

47U_0805_6.3V6M

PC306

47U_0805_6.3V6M

PR314

@

1 2

0_0402_5%

PR316

@

1 2

0_0402_5%

12

PC305

12

PC307

22U_0805_6.3VAM

VCC_IO_SENSE <11>

VSS_IO_SENSE <11>

PC308

22U_0805_6.3VAM

@

PJP300

@

1 2

PAD-OPEN 43x118

+VCC_IOP

1

+VCC_IO

B B

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

3

2

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

+VCC_IO 0.95V

LA-C551P

53 74Tuesday, August 18, 2015

1

1.0

A

Note:Use VCCSA_SEL to switch High & Low Level for VID[1]

1 1

2 2

PJP400

+3.3V_ALW

3 3

@

112

JUMP_43X79

Note: When design Vin=5V, please stuff snubber to prevent Vin damage

+3.3V_ALW

12

100K_0402_5%

2

12

PC400

22U_0603_6.3V6M

B

PR400

@

PU400

1

FB

2

PG

3

IN

4

PGND

SY8003DFC_DFN8_2X2

FB=0.6V

Note:Iload(max) =3A

PGND SGND

C

PJP401

@

2

PR404

PR405

112

JUMP_43X79

12

PR402

1M_0402_5%

12

Rup

12

PR401

@

1 2

0_0402_5%

Note:Iload(max)=2.5A

12

PC402

PC403

68P_0402_50V8J

Rdown

SIO_SLP_S4# <11,23,37,46,52>

+2.5V_MEMP

12

PC404

22U_0603_6.3V6M

2.5Volt TDC 0.63A Peak Current 0.9A OCP Current 3.5A

+2.5V_MEMP +2.5V_MEM

+2.5VSP_ON

12

PC401

@

9 8

7

EN

LX

NC

LX_2.5V

6

5

0.1U_0402_16V7K

PL400

1UH_2.8A_30%_4X4X2_F

1 2

12

PR403

36.5K_0402_1%

4.7_0603_5%

@EMI@

FB_2.5V

12

11.5K_0402_1%

PC405

@EMI@

680P_0402_50V7K

D

Vout=0.6V* (1+Rup/Rdown)

4 4

A

DELL CONFIDENTIAL/PROPRIETARY

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

C

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

+2.5V_MEM

LA-C551P

D

54 74Tuesday, August 18, 2015

1.0

5

Only H44e

D D

+PWR_SRC

+PWR_SRC+PWR_SRC

IMVP_VR_ON<7,56,61,64>

C C

+3.3V_ALW

+3.3V_ALW+3.3V_ALW

PR511 10K_0402_1%

H44@

1 2

@

PR513

10K_0402_1%

1 2

H44@

HCB1608KF-121T30_0603

@EMI@

HCB1608KF-121T30_0603

12

PR512

@

10K_0402_1%

VID0_EDRAM_VR

VID1_EDRAM_VR

12

PR514

10K_0402_1%

H44@

PL500

1 2

PR507

0_0402_5%

H44@

PC508

0.1U_0402_25V6

H44@

12

PR510

1M_0402_1%

H44@

12

H44@

4

+3.3V_ALW

1 2

CPU_ZVM#<10,56>

12

PC505

PC510

PC509

@

10U_0603_25V6M

H44@

12

PC507

@

0.1U_0402_25V6

VID1_EDRAM_VR

VID0_EDRAM_VR

+3.3V_ALW

PR501

0_0402_5%

H44@

VIN_EDRAMP

EN_EDRAMP

LP#_EDRAMP

12

1 2

PR509

@

100K_0402_1%

1

5

3

4

H44@

PU500

6

VIN

EN

C1

C0

3

H44@

PR500 100K_0402_1%

12

PR502

H44@

100K_0402_5%

BST_EDRAMP BST_R_EDRAMP

9

7

LP#

MODE

PG133V3

8

BST

SW

12

VOUT

2

PGND

11

AGND

NB681GD-Z_QFN13_2X3

10

12

PC506

1U_0402_6.3V6K

H44@

SW_EDRAMP

H44@

PR503

2.2_0603_5%

1 2

+3.3V_ALW

+3.3V_ALW+3.3V_ALW

H44@

PC500

0.1U_0603_25V7K

1 2

+VCCEDRAM(+1.00V)

+VCCEDRAM(+1.00V)+VCCEDRAM(+1.00V) TDC 2.31 A

TDC 2.31 A

TDC 2.31 ATDC 2.31 A Peak Current 3.3 A

Peak Current 3.3 A

Peak Current 3.3 APeak Current 3.3 A OCP Current 8 A

OCP Current 8 A

OCP Current 8 AOCP Current 8 A MAX

MAX

MAX MAX Choke DCR 48.0mohm

Choke DCR 48.0mohm

Choke DCR 48.0mohmChoke DCR 48.0mohm

@H44@

1UH_1277AS-H-1R0N-P2_3.3A_30%

4.7_1206_5%

PR504

@EMI@

4.7_1206_5%

1 2

PL501

1 2

H44@

PR508

0_0402_5%

H44@

680P_0402_50V7K

@EMI@

680P_0402_50V7K

H44@

12

@H44@

PR504

1 2

PR505

2

PC501

12

100_0402_1%

PR506

0_0402_5%

H44@

12

PC503

PC502

22U_0603_6.3V6M

H44@

12

6/17 depop modify (5/27 RF te am Brian suggest to pop) PR112-4.7 PR111-4.7 PR202-4.7 PR305-4.7 PR504-4.7 PR1804-4.7 (PR504,PR1804 depop)

PC114 680P PC111 680P PC212 680P PC301 680P PC501 680P PC1801 680P (PC501,PC1801 depop)

12

PC504

22U_0603_6.3V6M

H44@

VCC_EDRAM_SENSE <10>

VSS_EDRAM_SENSE <10>

+VCC_EDRAM_P +VCC_EDRAM

proximal

proximalproximal

PR505 0ohm PR506 100ohm PR508 100ohm

PR505 0ohm PR506 100ohm PR508 100ohmPR505 0ohm PR506 100ohm PR508 100ohm

remote

remoteremote

PR505 100ohm PR506 0ohm PR508 0ohm

PR505 100ohm PR506 0ohm PR508 0ohmPR505 100ohm PR506 0ohm PR508 0ohm

+VCC_EDRAM_P

+VCC_EDRAM_P+VCC_EDRAM_P

JUMP_43X79

@

112

PJP500

1

2

B B

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Ele ctronics, In c.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet of

Compal Ele ctronics, In c.

+VCCEDRAM, 1V

LA-C551P

55 74Tuesday, Augus t 18, 2015

1

1.0

Only H44e

5

4

3

2

1

+3.3V_ALW

D D

PL1800

H44@

HCB1608KF-121T30_0603

PL1800

@EMI@

HCB1608KF-121T30_0603

12

@

10K_0402_1%

12

10K_0402_1%

1 2

PR1812

VID0_EOPIO_VR

VID1_EOPIO_VR

PR1814

H44@

PR1807

0_0402_5%

H44@

PC1808

0.1U_0402_25V6

H44@

12

PR1809

1M_0402_1%

H44@

12

PC1809

PC1805

10U_0603_25V6M

H44@

12

+PWR_SRC

+PWR_SRC+PWR_SRC

IMVP_VR_ON<7,55,61,64>

C C

+3.3V_ALW

+3.3V_ALW+3.3V_ALW

PR1811 10K_0402_1%

H44@

CPU_MSM#<10>

B B

PR1815

0_0402_5%

H44@

1 2

12

@

PR1813

10K_0402_1%

1 2

CPU_ZVM#<10,55>

12

PC1810

@

10U_0603_25V6M

12

PC1806

@

0.1U_0402_25V6

+3.3V_ALW

VID1_EOPIO_VR

VID0_EOPIO_VR

PR1801

0_0402_5%

H44@

VIN_EOPIOP

EN_EOPIOP

1 2

@

100K_0402_1%

LP#_EOPIOP

12

PR1810

H44@

PU1800

1

5

3

4

PR1800

H44@

100K_0402_1%

1 2

12

PR1802 100K_0402_5%

BST_EOPIOP BST_R_EOPIOP

9

7

6

LP#

BST

MODE

PG133V3

SW

VOUT

PGND

AGND

NB681GD-Z_QFN13_2X3

10

12

PC1807

1U_0402_6.3V6K

VIN

EN

C1

C0

H44@

8

12

2

11

PR1803

2.2_0603_5%

1 2

H44@

SW_EOPIOP

+3.3V_ALW

+3.3V_ALW+3.3V_ALW

PC1800

0.1U_0603_25V7K

1 2

H44@

+VCCEOPIO(+1.00V)

+VCCEOPIO(+1.00V)+VCCEOPIO(+1.00V) TDC 2.24 A

TDC 2.24 A

TDC 2.24 ATDC 2.24 A Peak Current 3.2 A

Peak Current 3.2 A

Peak Current 3.2 APeak Current 3.2 A OCP Current 8 A

OCP Current 8 A

OCP Current 8 AOCP Current 8 A MAX

MAX

MAX MAX Choke DCR 48.0mohm

Choke DCR 48.0mohm

Choke DCR 48.0mohmChoke DCR 48.0mohm

@EMI@

PR1804

@EMI@

680P_0402_50V7K

4.7_1206_5%

1 2

PL1801

1UH_1277AS-H-1R0N-P2_3.3A_30%

1 2

H44@

12

PR1808

12

0_0402_5%

H44@

PC1801

1 2

+VCC_EOPIO_P

H44@

PC1804

22U_0603_6.3V6M

+VCC_EOPIO_P+VCC_EOPIO_P

PR1805

12

100_0402_1%

PR1806

0_0402_5%

H44@

PC1802

22U_0603_6.3V6M

12

H44@

12

H44@

12

PC1803

22U_0603_6.3V6M

VCC_EOPIO_SENSE <10>

VSS_EOPIO_SENSE <10>

+VCC_EOPIO_P +VCC_EOPIO

proximal

proximalproximal

PR1805 0ohm PR1806 100ohm PR1808 100ohm

PR1805 0ohm PR1806 100ohm PR1808 100ohmPR1805 0ohm PR1806 100ohm PR1808 100ohm

remote

remoteremote

PR1805 100ohm PR1806 0ohm PR1808 0ohm

PR1805 100ohm PR1806 0ohm PR1808 0ohmPR1805 100ohm PR1806 0ohm PR1808 0ohm

PJP1800

@

JUMP_43X79

112

2

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Ele ctronics, In c.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet of

Compal Ele ctronics, In c.

+VCCEOPIO, 1V

LA-C551P

56 74Tuesday, Augus t 18, 2015

1

1.0

A

PD700@

2 1

ES2AA-13-F

PQ701 SI7149DP

+DC_IN_SS

1 1

+VBUS_DC_SS

+VBUS_DC_SS+VBUS_DC_SS

4/22 add for PD

CSS_GC<57,60>

12

PR773 0_0402_5%

PR772

1 2

100K_0402_1%

2 2

3 3

12

3

PQ1073B

4

DMN65D8LDW-7_SOT363-6

SDMK0340L-7-F_SOD323-2~D

PD704

12

+SDC_IN

12

PR768

1M_0402_5%

12

CSS_GC_1

PR767

1M_0402_5% PR771 0_0402_5%

5

Current limit Charger :7.8A Vilim=1.56V 6 Cell (0.8C ) Max Boost Charger :7.8A, Vilim=0.39V

5

PR766

1 2

0_0402_5%

12

PR769

1M_0402_5%

61

2

PQ708A

PR770

DMN65D8LDW-7_SOT363-6

PR722

100K_0402_1%

ACAV_IN<18,46,60>

PR720

121K_0402_1%

12

1M_0402_5%

BQ24780_REGN

12

GNDA_CHG

4

3

5

4

DC_BLOCK_GC<57,60>

1 2 3

@

12

PR700 0_0402_5%

6/23 change PD701 PD702 PD1010 from SCS00003800 to SCS00005400 for vendor

PQ708B

DMN65D8LDW-7_SOT363-6

AC Det (typ 2.4V) Max:16.994V Typ :16.540V Min :16.098V

GNDA_CHG

CHARGER_SMBDAT<46>

CHARGER_SMBCLK<46>

I_ADP<46>

I_BATT<46>

TSENSE_PSYS<61>

H_PROCHOT#<7,46,57,61,64>

PBAT_PRES#<44,46,50>

4/22 add for PD

DC_BLOCK_GC <57,60>

+DOCK_PWR_BAR

+VBUS_DC_SS

+VBUS_DC_SS+VBUS_DC_SS

PR718

49.9K_0402_1%

12

PC711 0.1U_0402_25V4Z~D

PR716 0_0402_5%@

1 2

@

PR726 0_0402_5%

1 2

GNDA_CHG

+DC_IN_SS

PBATT+

PBATT+PBATT+

+SDC_IN

PR719

294K_0402_1%

PC721

@

CSS_GC<57,60>

BAT54CW-7-F SOT-323

12

PR706

1 2

PC720

1 2

100P_0402_50V8J

PR728

0_0402_5%

1 2

+3.3V_ALW

B

Iada=0~12.3A(240W)

ADP_I = 40*Iadapter*Rsense

+SDC_IN

@

12

PR703

@

0_0402_5%

CSS_GC_1

PD701

2

3

PD702

2

3

PR717

10_1206_5%

PC709

1U_0603_25V6K

4.12K_0603_1%

@

PR727 0_0402_5%

1 2

@

PR729

1 2

PR721 0_0402_5%@

1 2

12

1 2

PR744

@

37.4K_0402_1%

PR757

10K_0402_5%

1

12

TB_STAT#<45,57>

12

0_0402_5%

12

PC700

0.1U_0402_25V6

+DCIN

PR730

1 2

0_0402_5%

1 2

PR725

0_0402_5%

CMPIN

CMPOUT

GNDA_CHG

0.1U_0603_25V7K

PC702

1 2

28

11

12

10

13

14

15

16

29

GNDA_CHG

3

6

5

7

8

9

2

G

PU700

BQ24780S

13

D

S

CSSP_1

12

PR710

0_0402_5%

@

0.1U_0402_25V6

VCC

CMSRC

ACDET

SDA

SCL

ACOK

IADP

IDCHG

PMON

PROCHOT#

CMPIN

CMPOUT

BATPRES#

TB_STAT#

PWPD

@

1 2

PAD-OPEN1x1m

1

2

100_0402_1%

4

PJP700

PR701

0.005_1206_1%

4

3

13

2

G

PQ700 DMP3056L-7 1P SOT23-3

CSSN_1

PR704

12

PR711

0_0402_5%

PC703

@

1 2

0.01U_0402_25V6

CSSP_2

CSSN_2

2

1

ACP

ACN

ACDRV

REGN

BTST

HIDRV

PHASE

LODRV

GND

ILIM

SRP

SRN

BATDRV

BATSRC

D

PQ702 DMP3056L-7 1P SOT23-3

S

DMP3056L-7 1P SOT23-3

12

PR709

100K_0402_1%

PC704

1 2

BQ24780_REGN

24

PR765

2.2_0603_5%

1 2

25

26

27

23

22

21

20

19

18

17

CHG

5/14 change the circuit for bettary current sense

+PWR_SRC

PQ703

S

G

2

0.047U_0603_50V7

12

PR758

20K_0402_1%

PR764

D

C

1UH_6.6A_20%_5X5X3_M

EMI Part (47.1)

13

PQ706

DMP3056L-7 1P SOT23-3

S

G

12

2

PR712

100K_0402_1%

MM3Z22VST1G_SOD323-2

PC734

12

+3.3V_ALW

12

61

PQ707A

12

DMN66D0LDW-7_SOT363-6

2.74K_0402_1%

D

13

@

PD703

1 2

PC714

1 2

2.2U_0603_10V6K

PR760

5.36K_0402_1%

2

PL700

12

PR715 20_0402_1%

1 2

PR714

@

12

0_0402_5%

UGATE_CHG

LGATE_CHG

TB_STAT# <45,57>

+CHAGER_SRC

PR713

12.1_0402_1%

DK_CSS_GC <60>

4

LX_CHG

PR761 10_0402_1%

PR762 10_0402_1%

PC705

@EMC@

PQ704

5

123

PQ705

3 5

241

12

DOCK_DCIN_IS+ <43>

DOCK_DCIN_IS- <43>

12

PC706

2200P_0402_50V7K

@EMC@

12

PC707

0.1U_0603_25V7K

DCIN_ACOK#<44>

12

PC708

10U_0805_25V6K

EMI Part (47.1)

EMI Part (35.33 )

SIR472DP-T1-GE3_POWERPAK8-5

3.3UH_6.5A_20%_7X7X3_M

1 2

12

PR724

SNUB_CHG

12

@EMC@

FDMC7692S_MLP8-5

PC717

@EMC@

0.1U_0402_25V6

GNDA_CHG GNDA_CHG

PL701

4.7_1206_5%

680P_0402_50V7K

PC712

1 2

PR723

0.01_1206_1%

1

CHG

2

CSOP_1

0.1U_0402_25V6

PC710

1 2

D

5/19 add circuit for PD

MXM_PWR_LEVEL<18>

H_PROCHOT# <7,46,57,61,64>

61

2

PQ1074A

DMN65D8LDW-7_SOT363-6

+VCHGR

4

3

CSON_1

12

PC718

10U_0805_25V5K~D

PC713

0.1U_0402_25V6

1 2

5

4

O

PC719

10U_0805_25V5K~D

34

+3.3V_ALW

0.1U_0402_10V7K

5

P

B

A

G

TC7SH08FU_SSOP5~D

3

12

PC715

@

10U_0805_25V5K~D

PQ1074B

DMN65D8LDW-7_SOT363-6

PC151

12

1

ACAV_DOCK_SRC# <43,60>

2

PROCHOT_GATE < 45>

PU105

12

+DC_IN

12

PR745

100K_0402_1%

12

3M_0402_5%

@

4 4

ACAV_IN_NB<46,60>

PR743

0_0402_5%

12

+3.3V_ALW

A

CMP_REF=2.3V +DC_IN>17.6V then ACAV_IN_NB high

PR737

665K_0402_1%

12

PC737

PR738

100P_0402_50V8J

PR740 10K_0402_1%

B

12

CMPIN

CMPOUT

PC741

100P_0402_50V8J

1 2

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

C

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PWR_Charger

LA-C551P

D

57 74Tuesday, August 18, 2015

1.0

5

D D

PR802

TRIP_+1VSP

PR804

1 2

107K_0402_1%

12

PC800

@

0.22U_0402_16V7K

12

EN_+1VSP

FB_+1VSP

RF_+1VSP

12

470K_0402_1%

PR808 12K_0402_1%

PR806

S0 mode be high level

SIO_SLP_SUS#<11,46,49,59>

PCH_ALW_ON<46,49>

C C

B B

1 2

0_0402_5%

PR809

@

1 2

0_0402_5%

+3.3V_ALW

PR800

@

100K_0402_5%

1 2

PU800

1

2

3

4

5

TPS51212DSCR_SON10_3X3

PR807

5.11K_0402_1%

1 2

4

PGOOD

TRIP

EN

VFB

TST

VBST

DRVH

DRVL

V5IN

3

+1VSP_B+

5

PC804

@

PJP801

1 2

PAD-OPEN 43x118

.1U_0603_25V7K

12

+5V_ALW

BST_+1VSP

10

UG_+1VSP

9

SW_+1VSP

8

SW

+1VSP_5V

7

LG_+1VSP

6

11

TP

PR801

1 2

2.2_0603_5%

1 2

PC805 1U_0603_10V6K

+1.0V_PRIMP

4

+1.0V_PRIM

PQ800

123

SIS412DN-T1-GE3_POWERPAK8-5

5

123

12

PQ801

12

SI7716ADN-T1-GE3_POWERPAK8-5

2

12

PC801

PC802

EMC@

0.1U_0402_25V6

2200P_0402_50V7K

EMC@

EMI Part (35.33)

PL800

1UH_6.6A_20%_5X5X3_M

1 2

PR805

@EMC@

4.7_1206_5%

PC807

@EMC@

1000P_0402_50V7K

1

PJP800

@

12

PC803

10U_0805_25V6K

2 1

PAD-OPEN 1x2m~D

+PWR_SRC

+1.0V_PRIMP

1

+

PC806 220U_D2_2VY_R17M

2

+1.0V_PRIMP Ripple voltage Static load 3% / Dynamic load 5% Frequency 290kHz TDC 5.1A Peak Current 7.33A OCP current 8.8A TYP MAX H/S Rds(on) 24mohm , 30mohm L/S Rds(on) 13.5mohm , 16.5mohm Choke DCR 11mohm Bulk cap ESR 17mohm

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

3

2

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

+1.0V_PRIM

LA-C551P

58 74Tuesday, August 18, 2015

1

1.0

5

4

3

2

1

+3.3V_ALW

7

8

@EMC@

PC902

.1U_0402_16V7K

+5V_ALW

PU900

POK

EN

PAD-OPEN1x1m

12

PC900 1U_0402_6.3V6K

6

5

VIN

4

VOUT

VCNTL

3

VOUT

2

FB

9

VIN

GND

AP7175SP-13_SO-8EP-8

1

D D

PR900

@

0_0402_5%

+1.8VSP_ON

SIO_SLP_SUS#<11,46,49,58>

C C

1 2

@

PR901

47K_0402_5%

12

@

PJP900

12

+1.8VSP_VIN

12

12.7K_0402_1%

PC901

4.7U_0805_6.3V6K

12

PR902

12

1.8VSP

PR903

10K_0402_1%

12

PC903

0.01U_0402_25V7K

12

PC904

22U_0805_6.3V6M

@

PJP901

+1.8VSP +1.8V_ALW

1 2

PAD-OPEN1x1m

+1.8VSP

+1.8VSP+1.8VSP

TDC 0.035 A

TDC 0.035 ATDC 0.035 A

Peak Current 0.05A

Peak Current 0.05APeak Current 0.05A

OCP Current 5.7 A fix by IC

OCP Current 5.7 A fix by ICOCP Current 5.7 A fix by IC

Vout=0.8V* (1+Rup/Rdown)

B B

A A

Compal Electronics, Inc.

DELL CONFIDENTIAL/PROPRIETARY

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

3

2

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

+1.8V_ALW

LA-C551P

59 74Tuesday, August 18, 2015

1

1.0

5

SDMK0340L-7-F_SOD323-2~D

+VBUS_DC_SS

+VBUS_DC_SS+VBUS_DC_SS

PD1101

1 2

12

0_0402_5%

+SDC_IN

12

D D

12

PR1034

12

+VCHGR

5/8 add circuit for avoiding type C current to flow to battery

C C

+3.3V_ALW2

B B

ACAV_DOCK_SRC#<43,57>

+SDC_IN

ACAV_IN<18,46,57>

+3.3V_ALW2

+VBUS_DC_SS

+DC_IN

PR1013 100K_0402_5%

1 2

+DOCK_PWR_BAR

+DC_IN_SS

SDMK0340L-7-F_SOD323-2

1 2

PR1011 47_ 0805_5%

SOFT_START_GC<50>

PR1015

1 2

100_0603_1%

DC_BLOCK_GC<57>

PR1021

@

1 2

0_0402_5%

PR1022

@

1 2

0_0402_5%

PD1103

12

SDMK0340L-7-F_SOD323-2

PD1102

CD3301_DCIN

PC1006

0.1U_0603_50V4Z

PR1017

@

0_0402_5%

1 2

CD3301_SDC_IN

100_0603_1%

1 2

100_0603_1%

1 2

12

PR1026

PR1007

1 2

PR1010

100_0603_1%

12

ACAVDK_SRC

ERC1

SI4835DDY-T1-E3_SO8

8 7

5

ACAVIN P33ALW2

12

PC1007

0.1U_0603_25V7K

1M_0402_5%

PR1035

1M_0402_5%

PQ1002

PU1001

1

DC_IN

2

SS_GC

3

ERC1

4

ACAVDK_SRC

5

GND

6

SDC_IN

7

DC_BLK_GC

8

ACAV_IN

9

P33ALW2

37

TP

CSS_GC<57>

DK_CSS_GC<57>

1 2 36

4

PR1006

@

0_0402_5%

1 2

DK_PWR_BAR

3301_DC_IN_SS

12

PC1008

0.047U_0603_50V7K

PR1036

2

35

36

NC

CHARGERVR_DCIN

CSS_GC10DK_CSS_GC11ERC312ERC213GND14PWR_SRC

ERC3

PC1009

@

1M_0402_5%

61

PQ1005A

DMN65D8LDW-7_SOT363-6

PBATT+

BLK_MOSFET_GC

30NC31

33

34

32

GND

DC_IN_SS

DK_PWRBAR

BLKNG_MOSFET_GC

16

15

ERC2

12

3301_PWRSRC

0.1U_0402_25V6

PR1033

5

12

PR1037

1M_0402_5%

PR1004

@

0_0402_5%

12

PR1008 100_0603_1%

DSCHRG_MOSFET_GC

28

29

PBatt+

P50ALW

PBATT_OFF

DK_AC_OFF_EN

BLK_MOSFET_GC

ACAV_IN_NB

GND

DSCHRG_MOSFET_GC

DK_AC_OFF_EN

SL_BAT_PRES#

NBDK_DCINSS

SS_DCBLK_GC

EN_DK_PWRBAR17P33ALW

CD3301BRHHR

18

@

P33ALW

EN_DK_PWRBAR

STSTART_DCBLOCK_GC

100_0603_1%

1 2

4

+DOCK_PWR_BAR

3

4

DMN65D8LDW-7_SOT363-6

STSTART_DCBLOCK_GC

1 2 3

12

27 26 25 24 23 22 21 20 19

PR1025 0_0402_5%

1 2

PR1027

@

0_0402_5%

1 2

PR1029

PQ1005B

4

PC1004

1U_0603_25V6K

AC_DIS<45,50>

SLICE_BAT_PRES#<43,45,50,60>

P50ALW

CD_PBATT_OFF

DK_AC_OFF 3301_ACAV_IN_NB

DK_AC_OFF_EN SL_BAT_PRES#

PQ1003SI7149DP

5

+3.3V_ALW2

PR1030

10K_0402_5%

SDMK0340L-7-F_SOD323-2

PR1012

@

0_0402_5%

1 2

PR1016 0_0402_5%@

1 2

PR1014

@

1 2

0_0402_5%

CD3301_NBDOCK_DC_IN_SS

+3.3V_ALW

EN_DOCK_PWR_BAR <45>

1 2

1M_0402_5%

PR1028

+PWR_SRC

12

PR1001 330K_0402_5%

12

PD1100

1 2

+5V_ALW

BLKNG_MOSFET_GC

PR1023

@

0_0402_5%

1 2

0_0402_5%

@

PBATT_IN_SS

S

12

PR1099

100K_0402_5%

2

G

1 2

SLICE_BAT_ON <45>

PR1019

@

0_0402_5%

1 2

PR1024

5

PQ1072 AO3409_SOT23

D

13

G

2

13

D

PQ1011

S

SSM3K7002FU_SC70-3~D

0_0402_5%

PR1032

@

PR1020

@

ACAV_IN_NB <46,57>

0_0402_5%

1 2

SLICE_BAT_PRES# <43,45,50,60>

+NBDOCK_DC_IN_SS

3

PD1001

2

1

3

PDS5100H-13_POWERDI5-3~D

PQ1001 SI7149DP

1 2 3

4

PR1003

330K_0402_5%

1 2

12

PR1005

1K_1206_5%

12

PC1005

1U_0603_25V6K

PD1010

3

2

BAT54CW-7-F SOT-323

2

1

12

PC1001

0.47U_0805_25V7K~D

STSTART_DCBLOCK_GC

12

PR1002

@

0_0402_5%

PD1002

2

1

3

PDS5100H-13_POWERDI5-3~D

PQ1004 SI7149DP

5

1

DOCK_AC_OFF <43>

PR1031 330K_0402_5%

1 2

1M_0402_5%

PR1018

DOCK_AC_OFF_EC <45>

1 2 3

4

PC1002

@

12

PR1009

@

0_0402_5%

+PWR_SRC

12

PC1003

@

2200P_0402_50V7K

0.1U_0402_25V6

A A

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

Selector

LA-C551P

60 74Tuesday, August 18, 2015

1

1.0

5

@

PR1106

0_0402_5%

1 2

1000P_0402_50V7K

0_0402_5%

1 2

PR1108

@

PR1121

0_0402_5%

1 2

1000P_0402_50V7K

1 2

0_0402_5%

PR1122

@

PR1130

470P_0402_50V8J

1 2

PR1131

1K_0402_1%

1 2

PC1122

CSREF_3PH_A

1000P_0402_50V7K

PC1103

1 2

1000P_0402_50V7K

PC1109

1 2

2200P_0402_50V7K

PC1114

1000P_0402_50V7K

PR1100

100_0402_1%

1 2

VSS_SA_SENSE<11>

D D

VCC_SA_SENSE<11>

+VCC_SA

+VCC_CORE

VCC_SENSE<12>

VSS_SENSE<12>

C C

Place close to Choke in VCORE first phase cir cuit

SW1_3PH_A<61,62>

SW2_3PH_A<61,62>

SW3_3PH_A<61,62>

CSREF_3PH_A<62>

SW1_3PH_A<61,62>

B B

SW2_3PH_A<61,62>

SW3_3PH_A<61,62>

PHASE DETECTION

220K_0402_5%_ERTJ0EV224J

PR1143

@DFT@

93.1K_0402_1%

1 2

PR1146

@DFT@

93.1K_0402_1%

1 2

PR1148

@DFT@

93.1K_0402_1%

1 2

PR1154

2.26K_0402_1%

1 2

CSREF_3PH_A

PR1161

2.26K_0402_1%

1 2

CSREF_3PH_A

PR1163

2.26K_0402_1%

1 2

CSREF_3PH_A

PH1101

+5V_ALW

15P_0402_50V8J

PR1133

3.65K_0402_1%

1 2

12

PC1131

0.1U_0402_25V6

1 2

PC1133

0.1U_0402_25V6

1 2

PC1135

0.1U_0402_25V6

1 2

12

@

1K_0402_1%

PC1113

1 2

2200P_0402_50V7K

PR1142

165K_0402_1%

CSP1_3PH_A

CSP2_3PH_A

CSP3_3PH_A

PR1169

CSP3_3PH_A

100_0402_1%

1 2

100_0402_1%

1 2

100_0402_1%

1 2

PC1115

12

PR1140

12

PR1111

PR1119

PR1125

49.9_0402_1%

1 2

12

75K_0402_1%

PC1121

100P_0402_50V8J

+CPU_B+

PC1140

1 2

PR1107

@

1 2

0_0402_5%

@DFT@

PR1109

1K_0402_1%

1 2

PR1123

1K_0402_1%

1 2

PC1110

CSCOMP_3PH_A CSSUM_3PH_A

@

1 2

PAD-OPEN1x1m

4

VSN_1PH

VSP_1PH

PC1105

VSP_3PH_A

VSN_3PH_A

1 2

+CPU_B+

PJP1100

PL1100

EMI@

HCB2012KF-121T50_0805

1 2

PL1101

EMI@

HCB2012KF-121T50_0805

1 2

1

+

PC1141

PC1142

2

100U_25V_M

Place close to H-side,L-side MOS in VCORE first phase

@DFT@

PR1132

25.5K_0402_1%

1 2

PC1118

470P_0402_50V8J

1 2

PR1138

12.7K_0402_1%

@DFT@

PC1123

0.1U_0402_25V7K

0.01U_0402_50V7K

Place close to Choke in VCCSA first phase ci rcuit

1 2

PH1100

100K_0402_1%_TSM0B104F4251RZ

0.01UF_0402_25V7K

PR1118

1.5K_0402_1%

1 2

1 2 3 4 5 6 7 8

9 10 11 12 13

PC1127

12

15P_0402_50V8J

VSP_3PH_A VSN_3PH_A IMON_3PH_A DIFFOUT_3PH_A FB_3PH_A COMP_3PH_A ILIM_3PH_A CSCOMP_3PH_A CSSUM_3PH_A CSREF_3PH_A CSP1_3PH_A CSP2_3PH_A CSP3_3PH_A

TSENSE_3PH_A

PC1130

1U_0603_10V6K

2200P_0402_50V7K

6800P_0402_25V7K

1 2

PC1108

DRON<62,63,65>

PR1155

DIFFOUT_3PH_A FB_3PH_A

PR1150

1K_0402_1%

1 2

PC1128

1 2

CSN_1PH<65>

VSP_3PH_A VSN_3PH_A

COMP_3PH_A

ILIM_3PH_A COMP_3PH_B

CSP1_3PH_A CSP2_3PH_A CSP3_3PH_A

0.1U_0402_25V6

1 2

+5V_ALW

PR1151

2.2_0603_5%

PWM1_3PH_A/ICCMAX3A<62>

PWM2_3PH_A/ADDR<62>

PWM3_3PH_A/VBOOT<62>

+PWR_SRC

TSENSE_3PH_A

12

PR1165

0_0402_5%

@

12

PH1103

220K_0402_5%_ERTJ0EV224J

PR1167

61.9K_0402_1%

3

PR1102

PR1101

7.5K_0603_1%

12K_0402_1%

1 2

PC1102

1 2

PC1104

PC1100

1000P_0402_50V7K

1 2

PR1116

14.3K_0402_1%

1 2

PC1107

1 2

VSN_1PH

VSP_1PH

51

52

53

TAB

VSP_1PH

15

12

52.3K_0402_1%

Place close to H-side,L-side MOS in VCCGT first phase

47

48

49

50

ILIM_1PH

VSN_1PH

CSN_1PH

COMP_1PH

PWM1_3PH_A/ICCMAX_3PH_A18PWM2_3PH_A/ADDR19PWM3_3PH_A/VBOOT20PWM3_3PH_B/ROSC_3PH21PWM2_3PH_B/ROSC_1PH22PWM1_3PH_B/ICCMAX_3PH_B23DRON

VCC16TTSENSE_3PH_A14VRMP

17

12

PR1156

3.92K_0402_1%

12

PC1106

470P_0402_50V8J

40

41

42EN43

44

45

46

SDIO

SCLK

ALRT#

VR_RDY

CSP_1PH

IMON_1PH

DIFFOUT_3PH_B

PWM_1PH/ICCMAX_1PH

CSCOMP_3PH_B

TTSENSE_1PH/PSYS24TTSENSE_3PH_B25CSP3_3PH_B

26

TSENSE_3PH_B

12

PR1158

PR1157

24.9K_0402_1%

220K_0402_5%_ERTJ0EV224J

PR1112 30K_0402_1%

COMP_3PH_B

CSSUM_3PH_B

CSREF_3PH_B

97.6K_0402_1%

SW_1PH <65>

+3.3V_RUN

12

PR1114

10K_0402_1%

81205_SCLK 81205_ALERT 81205_SDIO

PU1100 NCP81205MNTXG_QFN52_6X6

39

VRHOT#

38

VSP_3PH_B

37

VSN_3PH_B

36

IMON_3PH_B

35 34

FB_3PH_B

33 32

ILIM_3PH_B

31 30 29 28

CSP1_3PH_B

27

CSP2_3PH_B

CSP3_3PH_B

0.1U_0402_25V6

1 2

12

PR1159

97.6K_0402_1%

TSENSE_3PH_B

12

PR1166

0_0402_5%

@

12

PH1104

PC1129

12

CSP1_3PH_B CSP2_3PH_B

PR1168

61.9K_0402_1%

34.8K_0402_1%

PCH_PWROK <23,64>

1 2

0_0402_5%

@

81205_VR_HOT

DIFFOUT_3PH_B

FB_3PH_B

ILIM_3PH_B

PR1153

24.9K_0402_1%

1 2 1 2

PR1152

75K_0402_1%

@DFT@

PWM1_3PH_B/ICCMAX3B <63>

PWM2_3PH_B/DOSC1 <63>

PWM3_3PH_B/DOSC3 <63>

+1.0V_VCCST

PWM1_1PH/ICCMAX1 <65>

PR1120

1 2

IMVP_VR_ON <7,55,56,64>

PR1198

PR1127

1K_0402_1%

1 2

PC1112

2200P_0402_50V7K

@DFT@

PR1135

24.9K_0402_1%

1 2

PC1120

470P_0402_50V8J

1 2

PR1139

16.2K_0402_1%

CSSUM_3PH_B

12

PC1126

0.1U_0402_25V7K

TSENSE_PSYS <57>

4/30 PR1153 change value for pmon request

H42@

1K_0402_1%

1 2

+5V_ALW

2

81205_VR_HOT

81205_SCLK

81205_ALERT

81205_SDIO

@

0_0402_5%

1 2

PC1111

12

1000P_0402_50V7K

1 2

0_0402_5%

@

CSP1_3PH_B

CSP2_3PH_B

CSP3_3PH_B

PR1170

100_0402_1%

0_0402_5%

PR1126

PR1128

PC1124

100P_0402_50V8J

PR1110

1 2

PR1117

49.9_0402_1%

1 2

CSCOMP_3PH_B

12

CSREF_3PH_B

PR1115

PC1125

1 2

PR1199 NA, need confirm

12

PR1199

PR1103

PR1105

100_0402_1%

1 2

@

499_0402_1%

45.3_0402_1%

12

@

PR1113

10_0402_1%

PR1124 100_0402_1%

1 2

+VCC_GT

VCCGT_SENSE <12>

VSSGT_SENSE <12>

PR1129

100_0402_1%

1 2

PR1134

49.9_0402_1%

1 2

12

PR1141

75K_0402_1%

12

1000P_0402_50V7K

PR1144

165K_0402_1%

PR1160

2.26K_0402_1%

1 2

PC1132

0.1U_0402_25V6

CSREF_3PH_B

PR1162

2.26K_0402_1%

1 2

PC1134

0.1U_0402_25V6

CSREF_3PH_B

PR1164

H44@

2.26K_0402_1%

1 2

PC1136

H44@

0.1U_0402_25V6

CSREF_3PH_B

1

12

PC1101

0.1U_0402_25V6

1 2

PR1104

45.3_0402_1%

H_PROCHOT# <7,46,57,64>

VR_SVID_CLK <7,64>

VR_SVID_ALERT# <7,64>

VR_SVID_DATA <7,64>

PC1117

PC1116

15P_0402_50V8J

470P_0402_50V8J

PR1136

1K_0402_1%

12

PH1102

220K_0402_5%_ERTJ0EV224J

Place close to Choke in VCCGT first phase ci rcuit

SW1_3PH_B <61,63>

SW2_3PH_B <61,63>

SW3_3PH_B <61,63>

1 2

12

3.65K_0402_1%

PR1145 107K_0402_1%

1 2

PR1147

107K_0402_1%

1 2

PR1149

107K_0402_1%

1 2

CSREF_3PH_B <63>

1 2

PR1137

@DFT@

H44@

1 2

PC1119

2200P_0402_50V7K

SW1_3PH_B <61,63>

SW2_3PH_B <61,63>

SW3_3PH_B <61,63>

A A

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFIDENTIAL

DELL CONFIDENTIAL/PROPRIETARY

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORI ZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS

5

4

3

MAY BE USED BY OR D ISCLOSED TO ANY THIRD PA RTY WITHOUT PRIOR WRITTEN CONSENT OF COMPA L ELECTRONICS, INC.

2

Compal Electronics, Inc.

Title

+VCORE

Size Document Number Rev

Date: Sheet of

LA-C551P

1

61 74Tuesday, August 18, 2015

1.0

5

+CPU_B+ +CPU_B+

+5V_ALW

PR1200

PU1200

2_0603_5%

6

1 2

D D

PWM1_3PH_A/ICCMAX3A< 61>

+5V_ALW

12

PC1209

1U_0603_10V6K

DRON<61,62,63,65 >

VCC

7

12

VCCD

PC1212

5

1U_0603_10V6K

CGND

4

PWM

2

DISB#

31

ZOD_EN

3

SMOD#

PC1200

10U_0805_25V6K

1

25

VIN20VIN21VIN22VIN23VIN24VIN

THWN

NCP81382MNTXG_QFN39_4X6

GL8GL9GL10GL

TEST

11

32

12

PC1202

PC1201

PC1203

10U_0805_25V6K

12

PR1201

28

30

2_0603_5%

GH

BOOT

PHASED

PHASEF

1 2

29

27

12

VSW

13

VSW

14

VSW

15

VSW

16

VSW

17

VSW

18

VSW

12

PGND

19

26

12

0.1U_0402_25V6 PC1334

PC1333

2200P_0402_50V7K

PC1210

0.22U_0603_25V7-K

0.15UH_PCME064T-R15MS_36A_20%

PC1214 2200P_0603_50V7K

PR1206 2_1206_5%

4

PL1200

1

4

3

2

+VCC_CORE +VCC_CORE

PR1204

10_0402_1%

1 2

CSREF_3PH_A <61,62>

SW1_3PH_A <61>

3

12

+5V_ALW

1 2

PR1203 2_0603_5%

1

PU1201

6

THWN

VCC

PC1204

VIN20VIN21VIN22VIN23VIN24VIN

PC1205

10U_0805_25V6K

25

28

GH

12

PC1211

1U_0603_10V6K

PWM2_3PH_A/ADDR<6 1>

DRON<61,62,63,65>

+5V_ALW

7

12

VCCD

PC1213

5

CGND

4

PWM

2

DISB#

31

ZOD_EN

3

SMOD#

NCP81382MNTXG_QFN39_4X6

GL8GL9GL10GL

TEST

11

32

PGND

19

1U_0603_10V6K

2

12

PC1207

10U_0805_25V6K

1 2

12

0.1U_0402_25V6 PC1336

PC1335

2200P_0402_50V7K

PC1208

0.22U_0603_25V7-K

0.15UH_PCME064T-R15MS_36A_20%

PC1215 2200P_0603_50V7K

PR1207 2_1206_5%

PL1201

1

4

3

2

PR1205

10_0402_1%

1 2

12

PC1206

10U_0805_25V6K

12

PR1202

30

2_0603_5%

BOOT

29

PHASED

27

PHASEF

12

VSW

13

VSW

14

VSW

15

VSW

16

VSW

17

VSW

18

VSW

PGND

26

1

CSREF_3PH_A <61,62>

SW2_3PH_A < 61>

+VCC_CORE

PR1209 2_0603_5%

6

+CPU_B+

PU1202

VCC

1

C C

+5V_ALW

1 2

12

PC1249

1U_0603_10V6K

PWM3_3PH_A/VBOOT<61>

DRON<61,62,63,65>

B B

+5V_ALW

7

12

VCCD

PC1258

5

CGND

4

PWM

2

DISB#

31

ZOD_EN

3

SMOD#

NCP81382MNTXG_QFN39_4X6

1U_0603_10V6K

THWN

GL8GL9GL10GL

VIN20VIN21VIN22VIN23VIN24VIN

TEST

11

32

12

PC1216

PC1218

PC1217

10U_0805_25V6K

PR1208

25

28

30

2_0603_5%

GH

BOOT

PHASED

PHASEF

VSW VSW VSW VSW VSW VSW VSW

PGND

19

26

12

PC1219

10U_0805_25V6K

12

1 2

29

27

12 13 14 15 16 17 18

12

0.1U_0402_25V6 PC1338

PC1337

2200P_0402_50V7K

PC1250

0.22U_0603_25V7-K

0.15UH_PCME064T-R15MS_36A_20%

PC1269 2200P_0603_50V7K

PR1211 2_1206_5%

+VCC_CORE

PL1202

1

4

3

2

10_0402_1%

1 2

PR1210

+VCC_CORE

CSREF_3PH_A <61,62>

SW3_3PH_A <61>

+VCC_CORE

A A

1

PC1220

2

12

PC1238

12

PC1259

12

PC1270

12

PC1288

12

PC1306

12

PC1324

1

PC1221

2

22U_0603_6.3V6M

12

PC1239

10U_0402_6.3V6M

12

PC1260

10U_0402_6.3V6M

12

PC1271

1U_0201_4V6M

12

PC1289

1U_0201_4V6M

12

PC1307

1U_0201_4V6M

12

PC1325

1U_0201_4V6M

1

PC1222

PC1223

2

22U_0603_6.3V6M

12

PC1240

PC1241

10U_0402_6.3V6M

12

PC1262

PC1261

10U_0402_6.3V6M

12

PC1273

PC1272

1U_0201_4V6M

12

PC1291

PC1290

1U_0201_4V6M

12

PC1308

PC1309

1U_0201_4V6M

12

PC1327

PC1326

1U_0201_4V6M

1

PC1224

2

22U_0603_6.3V6M

12

PC1251

10U_0402_6.3V6M

12

PC1263

10U_0402_6.3V6M

12

PC1274

1U_0201_4V6M

12

PC1292

1U_0201_4V6M

12

PC1310

1U_0201_4V6M

12

PC1328

1U_0201_4V6M

1

PC1226

PC1225

2

22U_0603_6.3V6M

12

PC1242

PC1243

10U_0402_6.3V6M

12

PC1265

PC1264

10U_0402_6.3V6M

12

PC1276

PC1275

1U_0201_4V6M

12

PC1293

PC1294

1U_0201_4V6M

12

PC1312

PC1311

1U_0201_4V6M

12

PC1330

PC1329

1U_0201_4V6M

1

PC1228

PC1227

2

22U_0603_6.3V6M

12

PC1252

PC1244

10U_0402_6.3V6M

12

PC1267

PC1266

10U_0402_6.3V6M

12

PC1278

PC1277

1U_0201_4V6M

12

PC1296

PC1295

1U_0201_4V6M

12

PC1314

PC1313

1U_0201_4V6M

12

PC1332

PC1331

1U_0201_4V6M

DELL CONFIDENTIAL/PROPRIETARY

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

1

PC1229

PC1230

2

22U_0603_6.3V6M

12

PC1245

PC1246

10U_0402_6.3V6M

PC1268

10U_0402_6.3V6M

12

PC1279

PC1280

1U_0201_4V6M

12

PC1297

PC1298

1U_0201_4V6M

12

PC1316

PC1315

1U_0201_4V6M

Title

Size Document Number Rev

Date: Sheet of

1

PC1233

PC1232

PC1231

2

22U_0603_6.3V6M

12

PC1247

PC1253

10U_0402_6.3V6M

12

PC1282

PC1281

1U_0201_4V6M

12

PC1299

PC1300

1U_0201_4V6M

12

PC1317

PC1318

1U_0201_4V6M

Compal Electronics, Inc.

+VCC_CORE

LA-C551P

1

PC1234

2

22U_0603_6.3V6M

12

PC1254

PC1248

10U_0402_6.3V6M

12

PC1283

PC1284

1U_0201_4V6M

12

PC1301

PC1302

1U_0201_4V6M

12

PC1320

PC1319

1U_0201_4V6M

1

+

PC1235

22U_0603_6.3V6M

PC1255

PC1285

PC1303

PC1321

62 74Tuesday, August 18, 2015

PC1237

PC1236

2

330U_D2_2.5V_R6M

12

PC1257

PC1256

10U_0402_6.3V6M

12

PC1287

PC1286

1U_0201_4V6M

12

PC1304

PC1305

1U_0201_4V6M

12

PC1323

PC1322

1U_0201_4V6M

1.0

10U_0402_6.3V6M

1U_0201_4V6M

5

+CPU_B+ +CPU_B+

+5V_ALW

1

PU1400

PR1400 2_0603_5%

6

1 2

D D

PWM1_3PH_B/ICCMAX3B< 61>

+5V_ALW

12

7

PC1411

12

1U_0603_10V6K

PC1412

5

1U_0603_10V6K

4

DRON<61,62,63,65>

2

31

3

THWN

VCC

VCCD

NCP81382MNTXG_QFN39_4X6

CGND

PWM

DISB#

ZOD_EN

SMOD#

GL8GL9GL10GL

VIN20VIN21VIN22VIN23VIN24VIN

11

32

12

PC1401

PC1400

10U_0805_25V6K

25

PC1403

PC1402

10U_0805_25V6K

12

PR1401

28

30

2_0603_5%

GH

BOOT

29

PHASED

27

PHASEF

12

VSW

13

VSW

14

VSW

15

VSW

16

VSW

17

VSW

18

VSW

12

PGND

TEST

19

26

Only H44e

H44@

12

PC1436

10U_0805_25V6K

1

25

VIN20VIN21VIN22VIN23VIN24VIN

THWN

PR1409 2_0603_5%

6

+CPU_B+

H44@

PU1402

VCC

C C

+5V_ALW

H44@

1 2

12

PC1457

1U_0603_10V6K

H44@

DRON<61,62,63,65>

B B

+5V_ALW

7

12

VCCD

PC1458

5

CGND

4

PWM

2

DISB#

31

ZOD_EN

3

SMOD#

NCP81382MNTXG_QFN39_4X6

GL8GL9GL10GL

TEST

11

32

H44@

1U_0603_10V6K

H44@

12

PC1437

PC1433

PC1434

10U_0805_25V6K

12

PR1408

28

30

2_0603_5%

H44@

GH

BOOT

29

PHASED

27

PHASEF

12

VSW

13

VSW

14

VSW

15

VSW

16

VSW

17

VSW

18

VSW

12

PGND

19

26

12

0.1U_0402_25V6 PC1551

PC1550

PC1408

0.22U_0603_25V7-K

1 2

PC1414 2200P_0603_50V7K

PR1406 2_1206_5%

H44@

12

0.1U_0402_25V6

PC1554

PC1438

0.22U_0603_25V7-K

1 2

H44@

PC1477 2200P_0603_50V7K

PR1411 2_1206_5%

H44@

2200P_0402_50V7K

H44@

4

12

PL1400

0.15UH_PCME064T-R15MS_36A_20%

1

4

3

2

12

PC1555

2200P_0402_50V7K

H44@

PL1402

0.15UH_PCME064T-R15MS_36A_20%

1

4

3

2

PR1404

10_0402_1%

1 2

PR1410

10_0402_1%

1 2

H44@

+VCC_GT

CSREF_3PH_B <61,63>

SW1_3PH_B <61>

+VCC_GT

CSREF_3PH_B <61,63>PWM3_3PH_B/DOSC3<61>

SW3_3PH_B <61>

+VCC_GT

3

+5V_ALW

1

PU1401

PR1403

1 2

2_0603_5%

6

VIN20VIN21VIN22VIN23VIN24VIN

THWN

VCC

12

7

PC1409

PWM2_3PH_B/DOSC1<61>

DRON<61,62,63,65>

+5V_ALW

12

1U_0603_10V6K

1

PC1416

2

22U_0603_6.3V6M

1

PC1439

2

22U_0603_6.3V6M

12

PC1459

10U_0402_6.3V6M

12

PC1478

10U_0402_6.3V6M

12

PC1496

1U_0201_4V6M

VCCD

PC1413

5

4

2

31

3

22U_0603_6.3V6M

12

10U_0402_6.3V6M

12

10U_0402_6.3V6M

12

1U_0201_4V6M

1

2

1

2

CGND

PWM

DISB#

ZOD_EN

SMOD#

PC1418

22U_0603_6.3V6M

PC1441

22U_0603_6.3V6M

PC1461

10U_0402_6.3V6M

PC1480

10U_0402_6.3V6M

PC1498

1U_0201_4V6M

12

NCP81382MNTXG_QFN39_4X6

GL8GL9GL10GL

TEST

11

32

1

PC1420

PC1419

2

22U_0603_6.3V6M

1

12

PC1442

PC1443

2

22U_0603_6.3V6M

12

PC1463

PC1462

10U_0402_6.3V6M

12

PC1481

PC1482

1U_0201_4V6M

12

PC1499

PC1500

1U_0201_4V6M

1U_0603_10V6K

1

PC1417

2

1

PC1440

2

12

PC1460

12

PC1479

12

PC1497

2

12

PC1404

PC1405

10U_0805_25V6K

25

28

GH

PGND

19

26

1

PC1421

2

22U_0603_6.3V6M

12

PC1444

10U_0402_6.3V6M

12

PC1464

10U_0402_6.3V6M

12

PC1483

1U_0201_4V6M

12

PC1501

1U_0201_4V6M

PGND

12

PHASED

PHASEF

PC1406

30

2_0603_5%

BOOT

1

2

12

VSW VSW VSW VSW VSW VSW VSW

10U_0805_25V6K

PR1402

PC1422

PC1445

PC1465

PC1484

PC1502

22U_0603_6.3V6M

10U_0402_6.3V6M

1U_0201_4V6M

12

PC1407

10U_0805_25V6K

12

1 2

29

27

12 13 14 15 16 17 18

12

1

PC1423

2

12

PC1446

12

PC1466

12

PC1485

12

PC1503

12

0.1U_0402_25V6 PC1553

PC1552

2200P_0402_50V7K

PC1410

0.22U_0603_25V7-K

0.15UH_PCME064T-R15MS_36A_20%

PC1415 2200P_0603_50V7K

PR1407 2_1206_5%

1

PC1424

2

22U_0603_6.3V6M

12

PC1447

10U_0402_6.3V6M

12

PC1467

10U_0402_6.3V6M

12

PC1486

1U_0201_4V6M

12

PC1504

1U_0201_4V6M

PL1401

1

4

3

2

1

PC1425

2

22U_0603_6.3V6M

12

PC1448

10U_0402_6.3V6M

12

PC1468

10U_0402_6.3V6M

12

PC1487

1U_0201_4V6M

12

PC1505

1U_0201_4V6M

PR1405

10_0402_1%

1 2

1

2

1

PC1427

PC1426

2

22U_0603_6.3V6M

12

PC1450

PC1449

10U_0402_6.3V6M

12

PC1469

PC1470

10U_0402_6.3V6M

12

PC1489

PC1488

1U_0201_4V6M

12

PC1507

PC1506

1U_0201_4V6M

1

PC1428

2

22U_0603_6.3V6M

12

PC1451

10U_0402_6.3V6M

12

PC1471

10U_0402_6.3V6M

12

PC1490

1U_0201_4V6M

12

PC1508

1U_0201_4V6M

1

+VCC_GT

CSREF_3PH_B <61,63>

SW2_3PH_B <61>

1

PC1430

PC1429

2

22U_0603_6.3V6M

12

PC1453

PC1452

10U_0402_6.3V6M

12

PC1472

PC1473

10U_0402_6.3V6M

12

PC1491

PC1492

1U_0201_4V6M

12

PC1509

PC1510

1U_0201_4V6M

1

+

PC1431

2

22U_0603_6.3V6M

PC1454

10U_0402_6.3V6M

PC1474

10U_0402_6.3V6M

PC1493

1U_0201_4V6M

PC1511

1U_0201_4V6M

+

PC1549

PC1435

2

330U 2.5V M D2 LESR6M

12

PC1455

PC1456

10U_0402_6.3V6M

12

PC1476

PC1475

10U_0402_6.3V6M

12

PC1495

PC1494

1U_0201_4V6M

12

PC1512

PC1513

1U_0201_4V6M

PC1432

330U 2.5V M D2 LESR6M

+VCC_GT

A A

12

PC1514

1U_0201_4V6M

12

PC1532

1U_0201_4V6M

12

PC1516

PC1515

1U_0201_4V6M

PC1533

1U_0201_4V6M

PC1517

1U_0201_4V6M

12

PC1535

PC1534

1U_0201_4V6M

12

PC1519

PC1518

1U_0201_4V6M

12

PC1536

PC1537

1U_0201_4V6M

DELL CONFIDENTIAL/PROPRIETARY

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

12

PC1520

PC1521

1U_0201_4V6M

12

PC1538

PC1539

1U_0201_4V6M

2

12

PC1522

PC1523

1U_0201_4V6M

12

PC1541

PC1540

1U_0201_4V6M

12

PC1524

PC1525

1U_0201_4V6M

12

PC1543

PC1542

1U_0201_4V6M

Title

Size Document Number Rev

Date: Sheet of

12

PC1527

PC1526

1U_0201_4V6M

12

PC1545

PC1544

1U_0201_4V6M

Compal Electronics, Inc.

+VCC_GT

LA-C551P

1

12

PC1528

1U_0201_4V6M

12

PC1546

1U_0201_4V6M

12

PC1530

PC1529

1U_0201_4V6M

PC1531

1U_0201_4V6M

12

PC1548

PC1547

1U_0201_4V6M

1.0

63 74Tuesday, August 18, 2015

1.0

5

Only H44e

D D

H_PROCHOT#<7,46,57,61>

VR_SVID_DATA<7,61>

VR_SVID_ALERT#<7,61>

VR_SVID_CLK<7,61>

C C

VSSGTX_SENSE<12>

B B

VCCGTX_SENSE<12>

+VCC_GTU

PCH_PWROK<23,61>

+CPU_B+

0.1U_0402_25V7K

PC1642 place close to IC

PR1620

100_0402_1%

1 2

H44@

PC1627

1000P_0402_50V7K

PR1621

100_0402_1%

1 2

H44@

5/8 PR1600 from 28.7K to 27K ohm for vendor request

IMVP_VR_ON<7,55,56,61>

PR1607

H44@

100_0402_1%

12

PR1608

H44@

10_0402_1%

1 2

PR1609

H44@

0_0402_5%

1 2

PR1611

H44@

49.9_0402_1%

1 2

12

PC1642

12

H44@

PR1615 2_0603_5%

PC1613

0.22U_0603_25V7-K

H44@

12

866_0402_1%

1 2

H44@

1 2

PC1640

1000P_0402_50V7K

12

H44@

PC1614

1000P_0402_50V7K

1 2

PR1617

1K_0402_1%

1 2

H44@

PR1618

H44@

PR1619

866_0402_1%

1 2

H44@

5/8 PR1618,PR1619 from 1K to 866 ohm for vendor request

H44@

+5V_ALW

4

BST1

81210_VSN

81210_VSP

PR1600

27K_0402_1%

1 2

470P_0402_50V8J

1 2

H44@

PR1603

2_0603_5%

PC1606

1U_0603_10V6K

H44@

1 2

H44@

1

VR_HOT#

2

SDIO

3

ALERT#

4

SCLK

5

PGND

6

VR_RDY

7

VIN

8

BST

9

GH

10

SW

+CPU_B+

H44@

PC1600

H44@

12

37

38

39

40

41

EN

VCC

GND

IOUT

DOSC/ADDR/VBOOT

PU1600

NCP81210MNTWG_QFN40_5x5

VIN13PGND

VIN

VIN11VIN

VIN

15

14

12

42

H44@

PR1601

8.25K_0402_1%

1 2

PR1602

15K_0402_1%

1 2

100K_0402_1%_TSM0B104F4251RZ

H44@

1 2

4700P_0402_25V7K

1 2

PC1603

0.01UF_0402_25V7K

H44@

81210_ILIM

81210_COMP

81210_VSN

81210_VSP

10K_0402_1%

1 2

35

36

32

33

34

31

H44@

ILIM

VSP

CSP

VSN

CSN

PSYS

COMP

30 29

TSENSE

28

IMAX

27

PVCC

26

PGND

44

GL

25

GL

24

GL

23

SW

22

SW

21

SW

PGND16PGND17PGND18PGND19PGND

PGND

20

43

H44@

PH1600

PC1690

PR1606

12

@

81210_IMAX

81210_SW1

PC1615

10U_0402_6.3V6M

H44@

12

H44@

3

81210_SWN

place close to Choke

81210_SENSE_RETURN

PR1604

6.19K_0402_1%

1 2

1000P_0402_50V7K

H44@

1 2

PC1608

0.015U_0402_16V7K

H44@

+5V_ALW

81210_ADDR/VBOOT 81210_TSENSE

1 2

PR1612

10K_0402_1%

12

H44@

12

PC1616

10U_0402_6.3V6M

H44@

12

PC1628

PC1629

1U_0201_4V6M

H44@

PC1607

1 2

PR1605

H44@

1.5K_0402_1%

1 2

H44@

PC1609 15P_0402_50V8J

H44@

150K_0402_1%

1 2

+5V_ALW

PC1611

4.7U_0402_6.3V6M

12

PC1617

10U_0402_6.3V6M

H44@

12

PC1630

1U_0201_4V6M

H44@

PR1610

H44@

PC1618

1U_0201_4V6M

10U_0402_6.3V6M

H44@

2

+CPU_B+

0.47UH_MMD05CZR47M_12A_20%

81210_SW1

12

PC1610 2200P_0603_50V7K

PR1613 0_0402_5%

1 2

12

H44@

1 2

PC1612

470P_0402_50V8J

H44@

12

PC1631

1U_0201_4V6M

PR1616

1 2

PH1601

100K_0402_1%_TSM0B104F4251RZ

place close to IC

1

H44@

PC1619

2

22U_0603_6.3V6M

H44@

12

PC1632

1U_0201_4V6M

H44@

61.9K_0402_1%

H44@

PC1620

PC1633

12

H44@

PR1614 2_1206_5%

H44@

1

PC1621

PC1622

2

H44@

2

22U_0603_6.3V6M

H44@

12

PC1635

PC1634

1U_0201_4V6M

H44@

22U_0603_6.3V6M

1U_0201_4V6M

12

PC1601

PC1604

PC1605

10U_0805_25V6K

H44@

PL1600

1

4

3

2

H44@

1

PC1623

PC1624

2

22U_0603_6.3V6M

H44@

12

PC1636

PC1637

1U_0201_4V6M

H44@

PC1602

10U_0805_25V6K

H44@

81210_SENSE_RETURN

81210_SWN

1

PC1625

PC1626

2

22U_0603_6.3V6M

H44@

12

PC1639

PC1638

1U_0201_4V6M

H44@

10U_0805_25V6K

H44@

22U_0603_6.3V6M

1U_0201_4V6M

H44@

12

0.1U_0402_25V6

PC1643

PC1644

2200P_0402_50V7K

H44@

+VCC_GTU

1

+

PC1641

2

470U_X_2VM_R6M

1

12

A A

Compal Electronics, Inc.

DELL CONFIDENTIAL/PROPRIETARY

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

+VCC_GTX

LA-C551P

64 74Tuesday, August 18, 2015

1

1.0

5

+5V_ALW

D D

PWM1_1PH/ICCMAX1<61>

C C

+5V_ALW

PR1700 2_0603_5%

1 2

12

PC1702

1U_0603_10V6K

DRON<61,62,63>

12

PC1704

1U_0603_10V6K

31

+CPU_B+

PU1700

6

7

5

4

2

3

VCC

VCCD

CGND

PWM

DISB#

ZOD_EN

SMOD#

InputCapacitor: 10uF_0805_X5R_25V

1

THWN

NCP81382MNTXG_QFN39_4X6

GL8GL9GL10GL

12

PC1700

10U_0805_25V6K

VIN20VIN21VIN22VIN23VIN24VIN

TEST

11

32

4

12

PC1701

25

28

10U_0805_25V6K

GH

PGND

19

12

PR1701

2_0603_5%

12

0.1U_0402_25V6

PC1707

PC1708

2200P_0402_50V7K

30

BOOT

PHASED

PHASEF

PGND

26

PC1703

0.22U_0603_25V7-K

1 2

29

27

12

VSW

13

VSW

14

VSW

15

VSW

16

VSW

17

VSW

18

VSW

12

PC1705 2200P_0603_50V7K

12

PR1702 2_1206_5%

Total VCORE Output Capacitor: 8 X 22uF_0603_X5R

PL1700

0.47UH_MMD05CZR47M_12A_20%

1

2

3

4

3

+VCC_SA

CSN_1PH <61>

SW_1PH <61>

1

+

2

PC1706

220U_D2_2.5VY_R9M

2

+VCC_SA

1

B B

A A

Compal Electronics, Inc.

DELL CONFIDENTIAL/PROPRIETARY

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

3

2

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

+VCC_SA

LA-C551P

65 74Tuesday, August 18, 2015

1

1.0

5

4

3

2

1

C551_H44e componentC551_H42 component

@H42@

PR1153

38.3K_0402_1%

D D

H42@

PR1135

22.6K_0402_1%

H42@

PR1109

1.43K_0402_1%

H42@

PR1132

24.3K_0402_1%

@H44@

PR1153

30.1K_0402_1%

H44@

PR1135

24.9K_0402_1%

H44@

PR1109

1K_0402_1%

H44@

PR1132

25.5K_0402_1%

H42@

PR1138

14.3K_0402_1%

H42@

PR1143

82.5K_0402_1%

C C

B B

H42@

PR1152

43.2K_0402_1%

H42@

PR1146

82.5K_0402_1%

H42@

PR1145

56.2K_0402_1%

H42@

PR1148

82.5K_0402_1%

H42@

PR1147

56.2K_0402_1%

H44@

PR1138

12.7K_0402_1%

H44@

PR1143

93.1K_0402_1%

H44@

PR1152

75K_0402_1%

H44@

PR1146

93.1K_0402_1%

H44@

PR1145

107K_0402_1%

H44@

PR1148

93.1K_0402_1%

H44@

PR1147

107K_0402_1%

A A

Compal Electronics, Inc.

DELL CONFIDENTIAL/PROPRIETARY

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

4

3

2

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PWR_table

LA-C551P

66 74Tuesday, August 18, 2015

1

1.0

5

Timing Diagram for S5 to S0 mode

D D

C C

5

11

14

11

+1.0V_PRIM

+1.8V_PRIM

5

H_VCCST_PWRGD

H_PWRGD

DDR_PG_CTRL

CPU

VCCST_PWRGD

PROCPWRGD

DDR_VTT_CNTL

+PWR_SRC

TPS51212DSCR

+3.3V_ALW

SY8032ABC

VCCGTX

VCCGT

VCCSTG

VCCSA

VCCPLL_OC

VDDQC

+VCC_CORE

VCC

+1.0VS_VCCIO

VCCIO

+VCC_GTU

+VCC_GT

+1.2V_MEM

VDDQ

+1.0V_VCCST

VCCST

+1.0V_VCCSTG

+VCC_SA

+VCC_SFR_OC

+VCC_VDDQ_CLK

SIO_SLP_SUS#

4

+1.0V_PRIM

9

TPS22961

+LCDVDD

10

3

SIO_SLP_S4#

+3.3V_ALW

+3.3V_SPI

3

5

+3.3V_ALW

APL3512ABI

+3.3V_ALW

EM5209VF+3.3V_LAN

+1.0V_PRIM

5

+3.3V_ALW_DSW

+3.3V_ALW_PCH

+1.8V_PRIM

5

+RTC_CELL

+1.0V_PRIM

PCH_PLTRST#

17

PCH_DPWROK

4

ENVDD_PCH

SIO_SLP_LAN#

VCCPRIM_1P0 DCPDSW_1P0 VCCMPHY_1P0 VCCMPHYPLL_1P0 VCCAPLL_1P0 VCCCLK1~5

VCCDSW_3P3

VCCHDA VCCSPI VCCPRIM_3P3 VCCPGPPA~E VCCRTCPRIM

VCCPGPPG VCCATS

VCCRTC

VCCPRIM_CORE

PLTRST#

DSW_PWROK

EDP_VDDEN

SLP_LAN#

PCH

PWRBTN#

RSMRST#

SLP_SUS#

SLP_LAN#

SLP_WLAN#/GPD9

SYS_PWROK

PCH_PWROK

VCCST_PWRGD

PROCPWRGD

SLP_S5#

SLP_S4#

SLP_S3#

SLP_A#

GPP_D13

GPP_D18

GPP_D10

PLTRST#

2

SIO_PWRBTN#

PCH_RSMRST#

SIO_SLP_SUS#

SIO_SLP_S5#

SIO_SLP_S4#

SIO_SLP_S3#

SIO_SLP_A#

SIO_SLP_LAN#

SIO_SLP_WLAN#

RESET_OUT#

PCH_PWROK

VCCST_PWRGD

H_CPUPWRGD

11

DGPU_PWR_EN

11

DGPU_PWROK

DGPU_HOLD_RST#

PLTRST_GPU#

7

5

9

10

15

13

11

14

TC7SH08FU

MXM

1

6

8

DGPU_PEX_RST#

16

SIO 5048

SIO_SLP_WLAN#

10

+3.3V_RUN

CCD_OFF

DMG2301U+CAMERA_VDD

DGPU_PWROK

11

@SIO_SLP_WLAN#

+3.3V_ALW

+3.3V_WLAN EM5209VF

10

B B

AUX_EN_WOWL

10

RUN_ON

+5V_ALW

EM5209VF

+3.3V_ALW

EM5209VF

+PWR_SRC

TLV62130

+5V_RUN

+3.3V_RUN

+1.0VS_VCCIO

12

+VCC_EOPIO

+5V_HDD

+3.3V_HDD

+3.3V_RUN

APL5930 +1.5V_RUN

+VCC_SA

+VCC_CORE

+VCC_GT

+VCC_EDRAM

11

NCP81205MNTXG

13

PCH_PWROK

SYX198DQNC

ADAPTER

BATTERY

6

4

15

5

9

8

10

+PWR_SRC

PCH_RSMRST#

PCH_DPWROK

RESET_OUT#

SIO_SLP_SUS#

SIO_SLP_S4#

SIO_SLP_S5#

SIO_SLP_LAN#

SIO_SLP_S3#

SIO_SLP_A#

11

IMVP_VR_ON

NCP81210MNTWG+VCC_GTU

EC 5085

2AC1BAT

PCH_ALW_ON

@SIO_SLP_A#

+PWR_SRC

ALWON

TPS51225CRUKR

10

A_ON

9

SUS_ON

EN_INVPWR

9

SIO_SLP_S4#

0.6V_DDR_VTT_ON

+3.3V_ALW

EM5209VF

+3.3V_ALW

EM5209VF

+PWR_SRC

FDC654P-G

+PWR_SRC

RT8207MZ

+5V_ALW2 +5V_ALW

+3.3V_RTC_LDO +3.3V_ALW2 +3.3V_ALW

+3.3V_ALW_PCH

+3.3V_MEM5209 VF

+3.3V_SUS

+BL_PWR_SRC

+1.2V_MEM

+0.6V_DDR_VTT

11

5

Pop option

+3.3V_SPI

19

VDDQ

VTT

DDR

BC BUS

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electr onics, Inc.

Power Button

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Compal Electr onics, Inc.

Title

Size Document Number Rev

Date: Sheet of

LA-C551P

Power Sequence

1

67 74Tuesday, August 18, 2015

1.0

5

4

3

2

1

Version Change List ( P. I. R. List )

Item Issue DescriptionDate

D D

1 22,37,49 HW 12/6/2014 compal reserve SPI and TPM PWR rail optional

2

3

4

5

6

7

25,30 X01(0.2)

8

9

C C

10

11

12

19,42,41 SATA express interface change to PCIE14(match HDD port1),PCIE13(match

13

46 add R862,R863,change netname GPP_C9 to SBIOS_TX X01(0.2)

14

15

16

47,22,7,36

B B

17

18

19

20

21

HW 12/10/2014 compal add "+" on PWR trace netname and others no "+" add netname +DCPRTC on CH68.1,change netname +3.3V_CAM_EN# to

HW 12/10/2014 compal symbol CPN and Value not match. change C1176,C1402 PN to SGA00002B00,and depop C140238 X01(0.2)

HW 12/11/2014 compal align BC change Q24 main source change Q24 to SB00000QP0030 X01(0.2)

HW 12/15/2014 RF RF request change CH268 from 0.01uF to 22pF23 X01(0.2)

HW 12/17/2014 compal Gen7_GPIO121145,46 remove R851,R852,R853,R854,change netname CPU_ID to GPIOL0,U51.A40 to

HW 12/19/2014 compal SATA express HDD function issue-PCIE13~16 lane

HW 12/23/2014 compal reserve for next-gen EC that use the Intel

HW 12/29/2014 compal SB339045100 EOL46 change Q28 to SB000008P00 X01(0.2)

HW 12/30/2014 compal solve TPM PLTRST leakage22 add RH346 and depop RH187,RH196, change U638.5 to_3.3V_ALW_PCH X01(0.2)

HW 12/30/2014 compal6,39,35,

HW 12/30/2014 compal21 DG1.0 RTC Crystal MAX ESR is 50Kohm YH1 change to SJ10000LV00 X01(0.2)

HW 12/30/2014 compal42 HDD SATA/PCIE repeater change to GEN3 chip UN8,UN9 change from PS8555 to PS8558(SA00008DT00),CN75,CN71 change to

HW 12/31/2014 compal23 MOW Rev1.0-To enable Direct Connect Interface

HW37 01/05/2015 compal System will shut down as soon as system power

HW39 01/06/2015 compal no business with vender-KEMET change C619 from SGA00000N00 to SGA00002B00 X01(0.2)

Request Owner

+3.3V_ALW_PCH or +3.3V_M. GPIO MAP:Gen7_GPIO1211compal12/6/2014HW37,46

Add RH343,RH344,RZ75,TPM PWR rail change to +3.3V_ALW_PCH ,add @RH348 to +3.3V_M power rail option for +3.3V_1.8V_SPI.

netname from SUS_ON to CV2_ON for follow GPIO MAP

Solution Description Rev.Page# Title

X01(0.2)

X01(0.2)U51.B62 change netname from POA_EN to EC_FPM_EN and U51.A9 change

R3740.2(UPD_SMBUS_ALERT#) PWR rail change from +3.3V_RUN to +3.3V_ALW. X01(0.2)45 HW 12/6/2014 compal Avoid backdrive to +3.3V_RUN.

add R3752,R375848 HW 12/6/2014 compal TP I2C interface reserve 0ohm X01(0.2)

update U8 symbol for SA00007ZW00,update U31 symbol for SA000081G0L28,35 HW 12/9/2014 compal symbol link CIS normal CPN X01(0.2)

AMD12/9/2014HW24 X01(0.2)

MXM cards

Reserve a pull up 10k(RH345) to +3.3V_ALW_PCH close to PCH side on GPU_EVENT#

X01(0.2)aviod incorrect behavior when system w/AMD

3.3V_CAM_EN#

X01(0.2)

reverse

MSDATA,U51.B43 to MSCLK,U51.B46 to PCH_PCIE_WAKE#,U46.A64 to ME_FW_EC,U46.A8 to USB_PWR_SHR_LFT_EN#

HDD port0),UH1.AG39 change to HDD_DET#,UH1.AD35 to SATA_EXP_IFDET.

chipset UART TXD for the SBIOS Serouts

same Value a CPN on Board PEG 0.22UF AC CAP(CC1~CC64) and SSD 0.22UF AC

(DCI),a 150K pull up resistor will need to be added to PCHHOT# pin.

on with FPM and RFID/NFC testing result is failed

CAP(CN83,CN85~CN88,CN91,CN92,CN95,CN97)change from SE00000R700 to SE095224K00 U15,U58,U638,UC4 change from SA007080120 to SA007080180 Q327 change from SB00000ST00 to SB00000UO00 T156 change from SP050006P00 to SP050006Y00

0.01uF,CN70,CN63,CN69,CN76,CN64,CN72,CN79,CN65,CN74,CN80,CN66,CN81 change to 0.22uF,remove CN77,CN68,CN82,CN78,add RH99~RH111,RH114~RH130

RH329 change to 150kohm(SD028150380) and pop it,reserve RH347 pull up to +3.3V_RUN,add RH353,@QH5

add DZ3,RZ76,RZ72,RZ73.change JUSH1.9 from +5V_ALW2 to +5V_ALW, JUSH1.10 from +3.3V_ALW2 to +5V_ALW2,JUSH1.25 from GND to +3.3V_ALW2, JUSH1.26 from GND to +PWR_SRC.

X01(0.2)

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

EE P.I.R -01

LA-C551P

68 7 4Tuesday, August 18, 2 015

1

1.0

5

4

3

2

1

Version Change List ( P. I. R. List )

Item Issue DescriptionDate

D D

C C

B B

A A

15,17 HW 01/06/2015 compal CONN LIST1124 change JDIMM2 to ADDR0106-P005A, JDIMM4 to ADDR0107-P005A X01(0.2)

22

46 HW 01/06/2015 compal Board ID change R875 to 130Kohm(SD028130380) X01(0.2)

23

28 HW 01/08/2015 compal USH SMBUS PULL UP when wo/ USH/B remove R3738,R3739,Q366 BS AAC@(let them always pop w/USH or wo/USH) X01(0.2)

24 25

21 HW 01/08/2015 compal Crystal EA change CH13,CH14 from 22pF to 15pF,

26

27 28 29 30 31

24 BIOS3501/13/2015 compal AMI BIOS Bidirection debug remove dummy net PCH_NFC_RST,add RH351,RH352 PU to +3.3V_ALW_PCH and

32

14 HW 01/14/2015 compal MOW rev1.0 ww02- recommended not to install

33

28 HW 01/19/2015 compal resevrve AAC SMBUS control from PCH add R38,R39,@R40,@R41,and R40.2 connect to UH1.AT42, R41.2 connect

34

47 ME 01/19/2015 compal Screw hole Add H42,H43,H44

HW 01/08/2015 compal X01(0.2)18,20,30 cost saving change U17,UC3 from SA00003Y000 to SA000046R00,U33 from SA00003AR00 to

HW 01/08/2015 compal X01(0.2)46 EC5085 change CPN change U51 to SA00006YH60 HW 01/09/2015 compal22 ADD PWR net on pin16 of JSPI1 netname is +3.3V_SPI_RWR on JSPI1.16 X01(0.2) HW22 01/09/2015 compal PLTRST group change balance before AND GATE

10,11 HW 01/20/2015 intel VENDER suggestion remove RC218,@RC219,@RC311

36

47 HW 01/20/2015 COMPAL LED limit current R value change R955 to 2.21k, R956 to 3k, R130 to 1.8k, R131 to 560

31,32 HW 01/20/2015 COMPAL DOCK DP1,DP2 EA pop R119,R121(PEQ=8.5dB),RV29,RV35(PEQ=8.5dB)

37

38

37 HW 01/21/2015 COMPAL TPM improve S3 support and back drive issue Add RZ78,@RZ79,@RZ77,@RZ80,QZ2,RZ82,change U637.1 to

39

7 HW 01/26/2015 COMPAL Solving for when system force shut down,it

40 35 HW 03/18/2015 COMPAL LAN EA change L63~L70 to 0ohm(R63~R70) X02(0.3)

41

42

43 HW 03/18/2015 COMPAL

43 37 HW 03/18/2015 COMPAL reserve @RZ111 for modern standby,RZ112 for

44 46 HW 03/18/2015 COMPAL change R374 from 0603 to 0402material lack

45 30 03/18/2015HW COMPAL for AAC function Pop R40,R41, De-pop R38, R39

46 18 solve never detect Hot plug event input at

47 reserve DIMM TYPE selectionCOMPAL03/18/201524 add RC329HW

Request Owner

Solution Description

C743 from 22pF to 27pF, C741P from 22pF to 33pF

SA00006Y800 and add @R42,change Q21 from SB000009K10 to SB000010C00

and after

any capacitor on DDR Reset signal (DRAMRST)

can't power on with power botten between 1 minute.

COMPAL03/18/2015HW20

546717_SKL_PCH_H_EDS_R1_2(add a 1K PD for USB2_VBUSSENSE and USB2_ID, if the signal is not used.Else it impacts Intel DCI test with warm boot)

DOCK E-SATA signal reverse SWAP SATA_PTX_C_DRX_P1 to JDOCK1.60(C699.1),SATA_PTX_C_DRX_N1 to

TPM detect issue.

COMPAL03/18/2015HW add R71,C1470,D95,R72change U14.1,U25.1,U27.1 from DGPU_PWROK to

Optimus GPU off

add RH349,@RH350,change RH210.1 to PCH_PLTRST#,RH337.1 to PCH_PLTRST#_AND,RH195.1 to PCH_PLTRST#

add @RH354,@RH355 PU to +3.3V_RUN on UH1.AR39,UH1.AR45,add JUART1 depop CD16

to UH1.AR38

+3.3V_ALW_PCH,U637.8 to +U637_TPM,U637.12 to NC add @R43,@RC327,UC5,UC6

add RH356,RH357 pull down to GND

JDOCK1.62(C700.1)

add @RZ83 connect to SIO_SLP_S0#,RZ112 between PCH_SPI_CS#2_R and QZ2.2

DGPU_PEX_RST#_D,remove @C95,@C96

Rev.Page# Title

X01(0.2)

X02(0.3)

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

EE P.I.R -02

LA-C551P

69 7 4Tuesday, August 18, 2 015

1

1.0

5

4

Version Change List ( P. I. R. List )

3

2

1

Item Issue DescriptionDate

D D

48

46 HW compal Board ID

49

4750 screw hole Remove H15

51 7 XDP working De-pop RC314,RC315,add RC330

HW

03/18/2015

HW 03/18/2015

HW

Request Owner

compal

Solution Description

Rev.Page# Title

X02(0.3)47 HW 03/18/2015 COMPAL material lack change R374 from 0603 to 0403

change R875 to 33Kohm

X02(0.3)

change JIO2.17 from +PWR_SRC to +VBUS_DC_SSKeep VBUS PWR stable4452 compal03/18/2015

backdrive and DG1.07,2353 compal03/18/2015

IR camera detect pin for verb tablecompal03/18/201524,3054

change RC315.1,RH312.1,RH314.1,RH315.1 from +1.0V_VCCSTG to +1.0V_VCCST

add GPP_A23 to IR_CAM_DET# and connect to JEDP1 pin26,add R366 pull up to +3.3V_RUN

X02(0.3)

55 47 03/18/2015 compal LED luminance adjustHW R956 to 1k, R130 to 1k, R131 to230, R943 to 1k, R955 to 1k X02(0.3)

C C

3856 reserve SIM detection designcompal04/21/2015HW X03(0.4)add RZ113 between SIM pin1(JSIM1) to WWAN pin58(JNGFF2)

48 X03(0.4)TP module add damping R,PU and new touchpad

compal04/21/2015HW57 Depop R3752,R3758,add RZ114,RZ115 pull up to +3.3V_TP

compal04/24/201545 add RE72,RE73,RE74,RE75,RE76 pull up to +3.3V_ALW.HW58

support PS2(in DOS),I2C bus(in OS)

smart mobile device under S3/S4/S5

X03(0.4)BITS211484: Left IO/B USB port 1 can't charge

X03(0.4)AAC update BOM for micDELL04/27/2015 change C1420 and C365 from 0.1uf to 2.2uF.HW4559

X03(0.4)USH reset by BCM58102broadcom depop RH35904/27/2015HW2860

X03(0.4)Add T217 on DVI_HPDadd test pad on DVI_HPD of MXMNVIDIA05/18/2015HW1861

X03(0.4)change U51 from SA00006YH60 to SA00006YH30.common EC codeNVIDIA05/18/2015HW4662

B B

compal05/18/2015HW4763

HDD active LED behavior for PCIe M.2 SSD module

R385 PU to +3.3V_SSD2

X03(0.4)add D97,D98,D99,and add R383 PU to +3.3V_RUN,R384 PU to+3.3V_SSD1,

X03(0.4)pop CZ30,CZ31 and change them to 330pFBOM change for Touchpad functioncompal05/21/2015HW4863

compal

EC detect for AR/B or non AR/BBIOS 05/21/20154564

RE77 PU to +3.3V_ALW

compal

26 reserve 0.1uF for 5.76G noise add @CH269 X03(0.4)67 HW 05/22/2016

44 X04(0.5)06/15/2016HW68

A A

compal

limilt current

add U639,R386,D100,and add R387 PU to +3.3V_RUN X03(0.4)HDD active LED behavior for SATA EXPRESS HDD41,47 HW 05/22/201666

change R388 from 10kohm to 0ohmGPIO pin can direct PU/PD no need serise R to

depop RH334QS CPU no need PD on SPI0_IO3 for boot X04(0.5)06/15/201644 HW68

X03(0.4)change JIO1.36 from GND to DCIN_ACOK#,and add PROCHOT_GATE on U46.A61TBT PD power supportPWR 05/21/201544,4563

X03(0.4)change JIO1.34 from GND to PD_ACE_DET#,and add it on U46.A60 and

X03(0.4)change R875 from 33Kohm to 4.3Kohmboard ID05/22/2015HW4665

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

EE P.I.R -03

LA-C551P

70 7 4Tuesday, August 18, 2 015

1

1.0

5

4

Version Change List ( P. I. R. List )

3

2

1

Item Issue DescriptionDate

D D

Request Owner

compal

Temp.in GC6

Solution Description

Rev.Page# Title

remove @R6,@R1979,change JMXM1 pin268,pin270 to +3.3V_MXMMXM3.1 SPEC18 X04(0.5)06/15/2016HW69

connect RH342.1 to U46.A48,remove R3749reserve GPIO pin for tell EC don't read GFX

X04(0.5)06/15/201619,45 HW70

add @R415 PU to +3.3V_ALW,R416 PD to GND X04(0.5)PROCHOT_GATE initial status06/15/2016HW4571 compal

72

73 74

46 HW 07/05/2015 compal

37 HW 46 Board ID change R875 from 2kohm to 1kohmHW 07/05/2015 compal X05(0.6)

07/05/2015 compal TPM DS3 support change U637.1 from +3.3V_ALW_PCH to +3.3V_ALW X05(0.6)

power on/off sequence tCPU05/tPLT18/tCPU03 and global reset issue

add U9,@C787 for tCPU05 and tPLT18,add RC331,CC273 for tCPU03,add @Q370,R435 for global reset

X05(0.6)

42 SATA IEMT CTLE(change RX EQ from level 1 to 2) pop RN130HW 07/29/2015 compal A00(1.0)75

41 SATA PWR supply for over loading pop C404,change C403 for 0.1uF to 22uF,and pop it.HW 07/29/2015 compal76

11 VCCPLL_OC power gate requirement for Deep

C C

7,23 backdrive and CPU EDS0.95

HW 08/07/2015 compal78

Sleep support

depop RC302,add UZ30,@RC330,@CZ95,@CZ96,CZ97,UC7,@CZ98HW 07/31/2015 compal77

change RC135.1,RH312.1,RH314.1,RH315.1 from +1.0V_VCCST to +1.0V_VCCSTG

A00(1.0)

46 Board ID change R875 from 1kohm to 62kohmHW 08/03/2015 compal79 A00(1.0)

22,35,46 HW 08/07/2015 MP component CPN change UH1 to SA00009602L,U31 to SA000081G1L,U51 to SA00006YH9080 compal A00(1.0)

7,23,28,44,49 HW MP BOM change depop R3739,R3738,R40,R41,U8,C31~C36,R23~R30,C141,C143,C365

81 08/13/2015 compal A00(1.0)

B B

,C1420,R373,R375,R414,R410,R413,R411,R361,R362(drop AAC), SW1,SW2,R3728,UZ28,C513,C547,pop RC301

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

EE P.I.R -03

LA-C551P

71 7 4Tuesday, August 18, 2 015

1

1.0

5

4

3

2

1

Version Change List ( P. I. R. List )

1/6

Request Owner

COMPAL

BQ24780 IFAULT LOW latch off

PU101 change to TPS51285B

D D

Item Issue DescriptionDate

P57 POWER

1

2

P51 POWER

1/6

Page 1

Solution Description Rev.Page# Title

1. PC702 chagne to 0.1uF

2. PC704 change to 0.01uF

1. PU101 change to TPS51285B

2. PC100/PC118 chagne to 4.7uF

3. add PR114

4. PR105 change to 29.4k ohm

PR02

5. PR106 change to 31.6k ohm

P64

3

C C

P61

4

POWER

1/19 COMPAL

1/28

COMPAL

VCC_GTU sense Add PR1620/PR1621 100ohm

1. PR1109 change to 1.43k ohm

VCORE parameter adjust for vendor request

2. PR1137/PR1133 change to 3.65k ohm

3. PC1121/PC1124 change to 100pF

4. PR1132 change to 25.5k ohm

PR02

5. PC1123/PC1125 change to 0.1uF

6. PC1104 change to 2200pF

7. PR1112 change to 30k ohm

PR02

8. PC1107 change to 6800pF

9. PR1135 change to 24.9k ohm

10. PR1152 change to 75k ohm

P52

5

B B

P53

6

POWER

COMPAL

3/18

3/18 COMPAL

change unmount for HW request(power sequence)

Add RC for HW request(Power sequence)

PC215 change to numount

Add PR317/PC312

PR03

P57

7

8 P64

P57

9

P60

A A

5

POWER

POWER 3/18

POWER

3/18

COMPAL

3/24 COMPAL

change to connect RENG for BATTERY reverse input protection

change VCC_GTU parameter for Vendor request

Add circuit to prevent +SDC_IN oscillation

4

Add PD703 in IC RENG pin

PR1604 change to 6.19k ohm add PC1690 to 4700p F

Add PD704/PR766~PR770/PQ708 Add PD1101/1033~PR1037/PQ1005

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2013/10/01 2015/07/08

Compal Secret Data

Deciphered Date

2

PR03

Compal Electronics, Inc.

Title

PWR-PIR

Size Document Numb er Rev

LA-C541P

Date: Sheet of

1

72 74Tuesday, August 18, 2015

1.0

5

4

3

2

1

Version Change List ( P. I. R.

Request Owner

D D

Item Issue

P61

10

P57 POWER

11

POWER

12 P57 POWER

Date

3/26

4/29

4/30 COMPAL

List )

COMPAL

Description

Add PR1170 for CPU H LINE-42

change CHARGER parameter for Vendor request

Add circuit to detect type C current

Page 2

Add PR1170

PR744 change to 37.4k ohm

Add PQ1073(SB00000DH00) /PR771(SD028000080) ,PR772(SD034100380)

Solution Description

Rev.Page# Title

PR03

PR04

,PR773(SD028000080)

C C

13 P61

POWER

4/30 COMPAL

14 P60 POWER 5/8 COMPAL

15 P57 POWER 5/14 COMPAL

16 P57 POWER 5/19 COMPAL

change VCORE parameter for Vendor request

Add circuit for avoiding type C current to flow to battery

Change the charger ILIM circuit for current sense

Add circuit for the PD Add PC151(SE102104K00)/

PR1153 change to 30.1k ohm(H44e)

、

38.3kohm(H42)

Add PD1102/PD1103(SCS0340L010) /PR1026 100ohm(SD014100080)

PR758 from 18K to 20K、PR760 from 3.16K to 5.36K and PR764 from 20K to 2.74K

PQ1074(SB00000DH00)/

PR04

PU105(SA007080120)

B B

17 P50 POWER 6/8 COMPAL

Add diodes for ESD team

Add PD4/PD6(SCA00000T00) PR05

request

18 P50 POWER 6/15 COMPAL

Change PU1 for ESD issue Change PU1 from SA00003DN00

PR05

to SA00001WK00/ depop PD4/PD6

19 P61 POWER 6/23 COMPAL

20 P52

P53

A A

5

POWER 7/6

COMPAL

change VCORE parameter for IPCC solution

For tCPU05 (VDDQ 1.2V to VCCIO 1.0V) add one AGATE 7408 and control by SIO_SLP_S3# and

1.2V_SUS_PWRGD(for HW )

4

ohm(SD034249280)

Depop PC312/PR303 Remove PR317 Change EC netname(to HW) from SIO_SLP_S3# to RUN_ON_AND Pop PR209 Add offpagethe for 1.2V_SUS_PWRGD

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2013/10/01 2015/07/08

Compal Secret Data

Deciphered Date

2

PR05PR1153 change to 24.9k

PR06

Compal Electronics, Inc.

Title

PWR-PIR

Size Document Numb er Rev

LA-C551P

Date: Sheet of

1

73 74Tuesday, August 18, 2015

1.0

5

8/3

Request Owner

COMPAL

Item Issue DescriptionDate

P58 POWER

21

D D

4

3

Version Change List ( P. I. R. List )

Add circuit control line for dirty shutdown issue

2

Page 3

Solution Description Rev.Page# Title

1.pop PR804

2. add line PCH_ALW_ON and PR809 0 ohm(depop)

1

PR10

3.depop PC800

C C

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2013/10/01 2015/07/08

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

PWR-PIR

Size Document Numb er Rev

LA-C541P

Date: Sheet of

1

74 74Tuesday, August 18, 2015

1.0

Compal MIRAMAR17 Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual