COMPAL LS-8863P Schematic

A

B

C

D

E

1 1

QMLE4/5

2 2

Eureka Discrete

LA-8863P SchematicREV 0.3

3 3

4 4

AMD Trinity APU / Hudson M3 FCH

Thames XT & Chelsea PRO

2012-03-13 Rev 0.3

A

B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/11/28 2013/12/31

C

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC,MB LA-8863

4019IT

151Friday, March 23, 2012

E

of

A

B

C

D

E

VGA Thermal Sensor

ADM1032ARMZ-2

1 1

page 13

HDMI Conn.

page 24

PCI-Express X16 5GHz

AMD GPU

AMD Thames XT, 128bit with 1GB/2GB DDR3 AMD Chelsea PRO, 128bit with 1GB/2GB DDR3

page 12,13,14,15,16,17,18,19,20

2 2

DP2 X4

LVDS Translator RTD2136S

page 21

LVDS Conn.

page 22

DP0 (X2)

PCIe X1

1.1V 5GT/s

AMD APU FS1 Processor

Trinity uPGA-722

35mm*35mm

page 5,6,7,8,9

DP1 (X4)

UMI X4

2.5GT/s

Memory BUS(DDRIII)

Dual Channel

1.5V DDRIII 1066/1333/1600 MT/s

PCIe X1 X1

1.1V 5GT/s

USB3.0

5V 5GT/s

USB

5V 480MHz

USB

5V 480MHz

CRT

page 23

page 5

USB/B Right

USB port 0,1

page 31

USB 3.0

USB3.0 port 0,1 USB2.0 port 10,11

PCIeMini Card WLAN/BT

AMD FCH

Fan Control

RJ45

page 34

ODD/B

3 3

Audio + CR/B

TP/B

page 30

page 33

page 38

RTL8111F-VB 1G

APU PCIe port 0

page 32

SPI Bus

3.3V 33 MHz

RTL8105E-VD 10/100M

Hudson M3

FCBGA-656

24.5mm*24.5mm

page 25,26,27,28,29

LPC Bus

3.3V 33 MHz

HD Audio

SATA port 0

5V 6GHz(600MB/s)

SATA port 1

5V 6GHz(600MB/s)

3.3V 24MHz

APU PCIe port 1

SATA HDD

SATA ODD

GCLK

SLG3NB270VTR page 31

200pin DDRIII-SO-DIMM X2

BANK 0, 1, 2, 3

Cardreader

Int. Camera

page 34

USB port 8

page 31

SATA port 0

page 30

SATA port 1

page 30

page 10,11

USB port 9

page 33

USB port 5

page 22

HDA Codec

RUSB + Power/B

page 30

SPI ROM (4MB)

page 27

Debug Port

page 37

ENE KB9012

page 36

ALC259

page 35

RTC CKT.

page 25

Touch Pad

page 38

Int.KBD

page 37

DC/DC Interface CKT.

page 39

4 4

SPK Conn

page 35

JPIO (HP & MIC)

page 35

Power Circuit DC/DC

page 40,41,42,43,44,45 ,46,47,48,49

Power On/Off CKT.

page 30

A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2011/11/28 2013/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC,MB LA-8863

4019IT

251Friday, March 23, 2012

E

A

of

5

B+

D D

Ipeak=5A, Imax=3.5A, Iocp min=7.9A

SUSP

N-CHANNEL

SI4800

TPS51125A

Ipeak=5A, Imax=3.5A, Iocp min=7.7A

C C

SUSP

N-CHANNEL

SI4800

4

+5VS

LDO

G9191

ODD_PWR

P-CHANNEL

AO-3413

WOL_EN#

P-CHANNEL

AO-3413

SYSON

P-CHANNEL

AO-3413

GPU_PWREN

SY8033BDBC

LCD_ENVDD

P-CHANNEL

AO-3413

DESIGN CURRENT 0.1A

DESIGN CURRENT 5A

DESIGN CURRENT 4A

DESIGN CURRENT 300mA

DESIGN CURRENT 1.6A

DESIGN CURRENT 5A

DESIGN CURRENT 330mA

DESIGN CURRENT 0.2A

DESIGN CURRENT 1.65A

DESIGN CURRENT 4A

DESIGN CURRENT 1.5A

+3VL

+5VALW

+5VS

+3VS_HDP

+5VS_ODD

+3VALW

+3V_LAN

+3V

+1.8VSG

+3VS

+LCD_VDD

3

2

1

PXS_PWREN

POK

G5603RU1U

VR_ON

Ipeak=5.3A, Imax=3.71A, Iocp min=6.814A

P-CHANNEL

AO-3413

SUSP

N-CHANNEL FDS6676AS

Ipeak=54A, Imax=36A, Iocp min=65A

B B

ISL6267HRZ-T

VR_ON

G5603RU1U

SYSON

G5603RU1U

Ipeak=27.5A, Imax=22A, Iocp min=35A

Ipeak=6.5A, Imax=4.55A, Iocp min=8.553A

Ipeak=20A, Imax=11.2A, Iocp min=24.136A

SUSP

N-CHANNEL FDS6676AS

+3V

LDO

APL5930KAI-TRG

SUSP

G2992F1U

VGA_PWRGD

A A

VGACORE_EN

N-CHANNEL FDS6676AS

GPU_PWREN

LDO

APL5930KAI

Ipeak=32.6A, Imax=20.3A, Iocp min=36A

RT8237CZQW

5

4

DESIGN CURRENT 0.3A

DESIGN CURRENT 5.3A

DESIGN CURRENT 4A

DESIGN CURRENT 50A

DESIGN CURRENT 23A

DESIGN CURRENT 6.5A

DESIGN CURRENT 20A

DESIGN CURRENT 2A

DESIGN CURRENT 1A

DESIGN CURRENT 1.5A

DESIGN CURRENT 11A

DESIGN CURRENT 3A

DESIGN CURRENT 32.6A

+3VGS

+1.1VALW

+1.1VS

+CPU_CORE +CPU_CORE_NB

+1.2VS

+1.5V

+1.5VS

+1.05V

+0.75VS

+1.5VSG

+1.0VSG

+VGA_CORE

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/11/28 2013/12/31

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

SCHEMATIC,MB LA-8863

4019IT

1

351Friday, March 23, 2012

of

A

B

C

D

E

Voltage Rails

1 1

power plane

State

S0

S1

2 2

S3

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery don't exist

( O MEANS ON X MEANS OFF )

+RTCVCC

O O O O O O

B+

O O O O O

X

+5VL +3VL

O O O O O

X

+5VALW +3VALW +1.1VALW +VSB

O O O O

X X

+1.5V +3V +1.05V

+5VS +3VS +2.5VS +1.5VS +1.2VS +1.1VS +0.75VS +CPU_CORE +CPU_CORE_NB +VGA_CORE +3VGS +1.8VSG +1.5VSG +1.0VSG

OO OO

O

X XX X

X XX

BTO Option Table

Function

description

explain

BTO

Function

description

explain

BTO

Function

description

explain

BTO

Function

description

explain

BTO

UMA PowerXpress

IHDMI@

MINI PCI-E SLOT

PowerXpress Enable

HDMI

8105ELDO@ 8111E@

GPIO for PowerXpress

PowerXpress (PXS@)

PXSEN@

COMMON

HDMI@

LAN

10/100M GIGA

8105ESWR@

Cam & Mic

CAM@

Crossfire Enable

CROSSEN@

SKU

UMA

UMA@ UMA@+VGA@+PXS@

FCH GPU

Hudson-M3 Whistler Pro

PowerXpress Discrete

VGA@+DIS@

Panel

Panel (DIS@)

Chipset

WHPROR1@ WHPROR3@HUDM3R1@ HUDM3R3@

Function

FCH SM Bus Address (SCL0/SDA0)

description

explain

HEX

Power

3 3

+3VS +3VS +3VS

Device

DDR SO-DIMM 0 DDR SO-DIMM 1 WLAN

EC SM Bus1 Address

HEX HEX

16 H

+3VL +3VL

Device Address Address

Charger IC 0001 001x b12 H

EC SM Bus3 Address

4 4

+3VS

A8 H

Address

1001 000xb90 H 1001 001xb92 H

BTO

EC SM Bus2 Address

PowerPower

0001 011x bSmart Battery

1010 1000 bLVDS EEPROM

+3VS +3VS +3VS GPU External Thermal +3VS GPU External Thermal

Device

APU Thermal Sensor GPU Internal Thermal

98 H 82 H 9A H 9A H

1001 100x b 1000 001x b 1001 101x b 1001 101x b

PowerXpress

BACO mode

BACO@

Non-BACO

NOBACO@

Hudson-M2 Hudson-M3

SIGNAL

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

G3 LOW LOW

SLP_S3#

FCH

M2@ M3@

SLP_S5#

HIGHHIGH

HIGH HIGH

HIGH

LOW

HIGH

LOW

LOWLOW

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/11/28 2013/12/31

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC,MB LA-8863

4019IT

451Friday, March 23, 2012

E

A

of

A

B

C

D

E

1 1

2 2

LAN WLAN

PCIE_GTX_C_CRX_P[0..15]<12>

JAPUA

PCI EXPRESS

PCIE_GTX_C_CRX_P0 PCIE_GTX_C_CRX_N0 PCIE_GTX_C_CRX_P1 PCIE_GTX_C_CRX_N1 PCIE_GTX_C_CRX_P2 PCIE_GTX_C_CRX_N2 PCIE_GTX_C_CRX_P3 PCIE_GTX_C_CRX_N3 PCIE_GTX_C_CRX_P4 PCIE_GTX_C_CRX_N4 PCIE_GTX_C_CRX_P5 PCIE_GTX_C_CRX_N5 PCIE_GTX_C_CRX_P6 PCIE_GTX_C_CRX_N6 PCIE_GTX_C_CRX_P7 PCIE_GTX_C_CRX_N7 PCIE_GTX_C_CRX_P8 PCIE_GTX_C_CRX_N8 PCIE_GTX_C_CRX_P9 PCIE_GTX_C_CRX_N9 PCIE_GTX_C_CRX_P10 PCIE_GTX_C_CRX_N10 PCIE_GTX_C_CRX_P11 PCIE_GTX_C_CRX_N11 PCIE_GTX_C_CRX_P12 PCIE_GTX_C_CRX_N12 PCIE_GTX_C_CRX_P13 PCIE_GTX_C_CRX_N13 PCIE_GTX_C_CRX_P14 PCIE_GTX_C_CRX_N14 PCIE_GTX_C_CRX_P15 PCIE_GTX_C_CRX_N15

+1.2VS

PCIE_FRX_C_LANTX_P0 PCIE_FRX_C_LANTX_N0 PCIE_FRX_WLANTX_P1 PCIE_FRX_WLANTX_N1

UMI_MTX_C_FRX_P0 UMI_MTX_C_FRX_N0 UMI_MTX_C_FRX_P1 UMI_MTX_C_FRX_N1 UMI_MTX_C_FRX_P2 UMI_MTX_C_FRX_N2 UMI_MTX_C_FRX_P3 UMI_MTX_C_FRX_N3

1 2

R1 196_0402_1%R1 196_0402_1%

PCIE_FRX_C_LANTX_P0<32> PCIE_FRX_C_LANTX_N0<32> PCIE_FRX_WLANTX_P1<31> PCIE_FRX_WLANTX_N1<31>

UMI_MTX_C_FRX_P0<25> UMI_MTX_C_FRX_N0<25> UMI_MTX_C_FRX_P1<25> UMI_MTX_C_FRX_N1<25> UMI_MTX_C_FRX_P2<25> UMI_MTX_C_FRX_N2<25> UMI_MTX_C_FRX_P3<25> UMI_MTX_C_FRX_N3<25>

AB8 AB7 AA9 AA8 AA5 AA6

Y8

Y7 W9 W8 W5 W6

V8

V7

U9

U8

U5

U6

T8

T7

R9

R8

R5

R6

P8

P7

N9

N8

N5

N6

M8

M7

AE5 AE6 AD8 AD7 AC9 AC8 AC5 AC6

AG8 AG9 AG6 AG5 AF7 AF8 AE8 AE9

P_ZVDDP P_ZVSS

AG11

PCI EXPRESS

P_GFX_RXP0 P_GFX_RXN0 P_GFX_RXP1 P_GFX_RXN1 P_GFX_RXP2 P_GFX_RXN2 P_GFX_RXP3 P_GFX_RXN3 P_GFX_RXP4 P_GFX_RXN4 P_GFX_RXP5 P_GFX_RXN5 P_GFX_RXP6 P_GFX_RXN6 P_GFX_RXP7 P_GFX_RXN7 P_GFX_RXP8 P_GFX_RXN8 P_GFX_RXP9 P_GFX_RXN9 P_GFX_RXP10 P_GFX_RXN10 P_GFX_RXP11 P_GFX_RXN11 P_GFX_RXP12 P_GFX_RXN12 P_GFX_RXP13 P_GFX_RXN13 P_GFX_RXP14 P_GFX_RXN14 P_GFX_RXP15 P_GFX_RXN15

P_GPP_RXP0 P_GPP_RXN0 P_GPP_RXP1 P_GPP_RXN1 P_GPP_RXP2 P_GPP_RXN2 P_GPP_RXP3 P_GPP_RXN3

P_UMI_RXP0 P_UMI_RXN0 P_UMI_RXP1 P_UMI_RXN1 P_UMI_RXP2 P_UMI_RXN2 P_UMI_RXP3 P_UMI_RXN3

P_ZVDDP

LOTES_ACA-ZIF-109-P12-A_FS1R2

GPP GRAPHICS

UMI

P_GFX_TXP0 P_GFX_TXN0 P_GFX_TXP1 P_GFX_TXN1 P_GFX_TXP2 P_GFX_TXN2 P_GFX_TXP3 P_GFX_TXN3 P_GFX_TXP4 P_GFX_TXN4 P_GFX_TXP5 P_GFX_TXN5 P_GFX_TXP6 P_GFX_TXN6 P_GFX_TXP7 P_GFX_TXN7 P_GFX_TXP8 P_GFX_TXN8 P_GFX_TXP9 P_GFX_TXN9

P_GFX_TXP10

P_GFX_TXN10

P_GFX_TXP11

P_GFX_TXN11

P_GFX_TXP12

P_GFX_TXN12

P_GFX_TXP13

P_GFX_TXN13

P_GFX_TXP14

P_GFX_TXN14

P_GFX_TXP15

P_GFX_TXN15

P_GPP_TXP0 P_GPP_TXN0 P_GPP_TXP1 P_GPP_TXN1 P_GPP_TXP2 P_GPP_TXN2 P_GPP_TXP3 P_GPP_TXN3

P_UMI_TXP0 P_UMI_TXN0 P_UMI_TXP1 P_UMI_TXN1 P_UMI_TXP2 P_UMI_TXN2 P_UMI_TXP3 P_UMI_TXN3

P_ZVSS

@

PCIE_CTX_GRX_P0

AB2

PCIE_CTX_GRX_N0

AB1

PCIE_CTX_GRX_P1

AA3

PCIE_CTX_GRX_N1

AA2

PCIE_CTX_GRX_P2

Y5

PCIE_CTX_GRX_N2

Y4

PCIE_CTX_GRX_P3

Y2

PCIE_CTX_GRX_N3

Y1

PCIE_CTX_GRX_P4

W3

PCIE_CTX_GRX_N4

W2

PCIE_CTX_GRX_P5

V5

PCIE_CTX_GRX_N5

V4

PCIE_CTX_GRX_P6

V2

PCIE_CTX_GRX_N6

V1

PCIE_CTX_GRX_P7

U3

PCIE_CTX_GRX_N7

U2

PCIE_CTX_GRX_P8

T5

PCIE_CTX_GRX_N8

T4

PCIE_CTX_GRX_P9

T2

PCIE_CTX_GRX_N9

T1

PCIE_CTX_GRX_P10

R3

PCIE_CTX_GRX_N10

R2

PCIE_CTX_GRX_P11

P5

PCIE_CTX_GRX_N11

P4

PCIE_CTX_GRX_P12

P2

PCIE_CTX_GRX_N12

P1

PCIE_CTX_GRX_P13

N3

PCIE_CTX_GRX_N13

N2

PCIE_CTX_GRX_P14

M5

PCIE_CTX_GRX_N14

M4

PCIE_CTX_GRX_P15

M2

PCIE_CTX_GRX_N15

M1

PCIE_FTX_LANRX_P0

AD5

PCIE_FTX_LANRX_N0

AD4

PCIE_FTX_WLANRX_P1

AD2

PCIE_FTX_WLANRX_N1

AD1 AC3 AC2 AB5 AB4

UMI_FTX_MRX_P0

AG2

UMI_FTX_MRX_N0

AG3

UMI_FTX_MRX_P1

AF4

UMI_FTX_MRX_N1

AF5

UMI_FTX_MRX_P2

AF1

UMI_FTX_MRX_N2

AF2

UMI_FTX_MRX_P3

AE2

UMI_FTX_MRX_N3

AE3 AH11

1 2

R2 196_0402_1%R2 196_0402_1%

PCIE_CTX_C_GRX_P[0..15] <12> PCIE_CTX_C_GRX_N[0..15] <12>PCIE_GTX_C_CRX_N[0..15]<12>

C1 0.1U_0402_16V7KC1 0.1U_0402_16V7K

1 2

C2 0.1U_0402_16V7KC2 0.1U_0402_16V7K

1 2

C3 0.1U_0402_16V7KC3 0.1U_0402_16V7K

1 2

C4 0.1U_0402_16V7KC4 0.1U_0402_16V7K

1 2

C5 0.1U_0402_16V7KC5 0.1U_0402_16V7K

1 2

C6 0.1U_0402_16V7KC6 0.1U_0402_16V7K

1 2

C7 0.1U_0402_16V7KC7 0.1U_0402_16V7K

1 2

C8 0.1U_0402_16V7KC8 0.1U_0402_16V7K

1 2

C9 0.1U_0402_16V7KC9 0.1U_0402_16V7K

1 2

C10 0.1U_0402_16V7KC10 0.1U_0402_16V7K

1 2

C11 0.1U_0402_16V7KC11 0.1U_0402_16V7K

1 2

C37 0.1U_0402_16V7KC37 0.1U_0402_16V7K

1 2

C29 0.1U_0402_16V7KC29 0.1U_0402_16V7K

1 2

C35 0.1U_0402_16V7KC35 0.1U_0402_16V7K

1 2

C18 0.1U_0402_16V7KC18 0.1U_0402_16V7K

1 2

C16 0.1U_0402_16V7KC16 0.1U_0402_16V7K

1 2

C22 0.1U_0402_16V7KC22 0.1U_0402_16V7K

1 2

C38 0.1U_0402_16V7KC38 0.1U_0402_16V7K

1 2

C34 0.1U_0402_16V7KC34 0.1U_0402_16V7K

1 2

C20 0.1U_0402_16V7KC20 0.1U_0402_16V7K

1 2

C21 0.1U_0402_16V7KC21 0.1U_0402_16V7K

1 2

C23 0.1U_0402_16V7KC23 0.1U_0402_16V7K

1 2

C33 0.1U_0402_16V7KC33 0.1U_0402_16V7K

1 2

C24 0.1U_0402_16V7KC24 0.1U_0402_16V7K

1 2

C25 0.1U_0402_16V7KC25 0.1U_0402_16V7K

1 2

C26 0.1U_0402_16V7KC26 0.1U_0402_16V7K

1 2

C27 0.1U_0402_16V7KC27 0.1U_0402_16V7K

1 2

C28 0.1U_0402_16V7KC28 0.1U_0402_16V7K

1 2

C31 0.1U_0402_16V7KC31 0.1U_0402_16V7K

1 2

C30 0.1U_0402_16V7KC30 0.1U_0402_16V7K

1 2

C36 0.1U_0402_16V7KC36 0.1U_0402_16V7K

1 2

C32 0.1U_0402_16V7KC32 0.1U_0402_16V7K

1 2

C50 0.1U_0402_16V7KC50 0.1U_0402_16V7K

1 2

C55 0.1U_0402_16V7KC55 0.1U_0402_16V7K

1 2

C51 0.1U_0402_16V7KC51 0.1U_0402_16V7K

1 2

C54 0.1U_0402_16V7KC54 0.1U_0402_16V7K

1 2

C59 0.1U_0402_16V7KC59 0.1U_0402_16V7K

1 2

C60 0.1U_0402_16V7KC60 0.1U_0402_16V7K

1 2

C61 0.1U_0402_16V7KC61 0.1U_0402_16V7K

1 2

C62 0.1U_0402_16V7KC62 0.1U_0402_16V7K

1 2

C122 0.1U_0402_16V7KC122 0.1U_0402_16V7K

1 2

C123 0.1U_0402_16V7KC123 0.1U_0402_16V7K

1 2

C120 0.1U_0402_16V7KC120 0.1U_0402_16V7K

1 2

C121 0.1U_0402_16V7KC121 0.1U_0402_16V7K

1 2

PCIE_CTX_C_GRX_P0 PCIE_CTX_C_GRX_N0 PCIE_CTX_C_GRX_P1 PCIE_CTX_C_GRX_N1 PCIE_CTX_C_GRX_P2 PCIE_CTX_C_GRX_N2 PCIE_CTX_C_GRX_P3 PCIE_CTX_C_GRX_N3 PCIE_CTX_C_GRX_P4 PCIE_CTX_C_GRX_N4 PCIE_CTX_C_GRX_P5 PCIE_CTX_C_GRX_N5 PCIE_CTX_C_GRX_P6 PCIE_CTX_C_GRX_N6 PCIE_CTX_C_GRX_P7 PCIE_CTX_C_GRX_N7 PCIE_CTX_C_GRX_P8 PCIE_CTX_C_GRX_N8 PCIE_CTX_C_GRX_P9 PCIE_CTX_C_GRX_N9 PCIE_CTX_C_GRX_P10 PCIE_CTX_C_GRX_N10 PCIE_CTX_C_GRX_P11 PCIE_CTX_C_GRX_N11 PCIE_CTX_C_GRX_P12 PCIE_CTX_C_GRX_N12 PCIE_CTX_C_GRX_P13 PCIE_CTX_C_GRX_N13 PCIE_CTX_C_GRX_P14 PCIE_CTX_C_GRX_N14 PCIE_CTX_C_GRX_P15 PCIE_CTX_C_GRX_N15

PCIE_FTX_C_LANRX_P0 <32> PCIE_FTX_C_LANRX_N0 <32> PCIE_FTX_C_WLANRX_P1 <31> PCIE_FTX_C_WLANRX_N1 <31>

UMI_FTX_C_MRX_P0 <25> UMI_FTX_C_MRX_N0 <25> UMI_FTX_C_MRX_P1 <25> UMI_FTX_C_MRX_N1 <25> UMI_FTX_C_MRX_P2 <25> UMI_FTX_C_MRX_N2 <25> UMI_FTX_C_MRX_P3 <25> UMI_FTX_C_MRX_N3 <25>

LAN WLAN

3 3

FAN Control Circuit

+5VS

1A

C13

10U_0603_6.3V6M

U2

1

EN

2

EN_DFAN1<36>

4 4

A

B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2011/11/28 2013/12/31

Compal Secret Data

+FAN

10mil

Deciphered Date

3 4

1

C17

APL5607KI-TRG_SO8

10U_0603_6.3V6M

2

D

VIN VOUT VSET

GND GND GND GND

8 7 6 5

+FAN

2

C15

C15 1000P_0402_50V7K

1000P_0402_50V7K @

@

1

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC,MB LA-8863

1 2 3

4 5

ACES_85204-0300N

R59 10K_0402_5%R59 10K_0402_5%

1

C14

0.01U_0402_25V7K

0.01U_0402_25V7K @

@

2

4019IT

JFAN

E

1 2 3

GND GND

12

@JFAN

@

+3VS

FAN_SPEED1 <36>

551Friday, March 23, 2012

A

of

A

B

C

D

E

DDR_A_DQS[0..7]<10>

DDR_A_DQS#[0..7]<10>

1 1

JAPUB

MEMORY CHANNEL A

DDR_A_MA[0..15]<10>

DDR_A_BS0<10> DDR_A_BS1<10> DDR_A_BS2<10> DDR_A_DM[0..7]<10>

2 2

DDR_A_CLK0<10> DDR_A_CLK0#<10> DDR_A_CLK1<10> DDR_A_CLK1#<10>

DDR_A_CKE0<10> DDR_A_CKE1<10>

DDR_A_ODT0<10> DDR_A_ODT1<10>

3 3

DDR_A_SCS0#<10> DDR_A_SCS1#<10>

DDR_A_RAS#<10> DDR_A_CAS#<10> DDR_A_WE#<10>

MEM_MA_RST#<10> MEM_MA_EVENT#<10>

+1.5V

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15

DDR_A_BS0 DDR_A_BS1 DDR_A_BS2

DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7

DDR_A_DQS0 DDR_A_DQS#0 DDR_A_DQS1 DDR_A_DQS#1 DDR_A_DQS2 DDR_A_DQS#2 DDR_A_DQS3 DDR_A_DQS#3 DDR_A_DQS4 DDR_A_DQS#4 DDR_A_DQS5 DDR_A_DQS#5 DDR_A_DQS6 DDR_A_DQS#6 DDR_A_DQS7 DDR_A_DQS#7

DDR_A_CLK0 DDR_A_CLK0# DDR_A_CLK1 DDR_A_CLK1#

DDR_A_CKE0 DDR_A_CKE1

DDR_A_ODT0 DDR_A_ODT1

DDR_A_SCS0# DDR_A_SCS1#

DDR_A_RAS# DDR_A_CAS#

MEM_MA_RST# MEM_MA_EVENT#

15mil

+MEM_VREF

M_ZVDDIO

1 2

R60 39.2_0402_1%R60 39.2_0402_1%

M21 M22

AA25

AD27 AC23 AD19 AC15

AE26 AD26 AB22 AA22 AB18 AA18 AA14 AA15

AA27

AA26

W24 W23

W20 W21

U20 R20 R21 P22 P21 N24 N23 N20 N21

U23 L24 L21

L20 U24

U21 L23

E14

J17 E21 F25

G14 H14 G18 H18

J21 H21 E27 E26

T21 T22 R23 R24

H28 H27

Y25

V22

V21

H25 T24

MEMORY CHANNEL A

MA_ADD0 MA_ADD1 MA_ADD2 MA_ADD3 MA_ADD4 MA_ADD5 MA_ADD6 MA_ADD7 MA_ADD8 MA_ADD9 MA_ADD10 MA_ADD11 MA_ADD12 MA_ADD13 MA_ADD14 MA_ADD15

MA_BANK0 MA_BANK1 MA_BANK2

MA_DM0 MA_DM1 MA_DM2 MA_DM3 MA_DM4 MA_DM5 MA_DM6 MA_DM7

MA_DQS_H0 MA_DQS_L0 MA_DQS_H1 MA_DQS_L1 MA_DQS_H2 MA_DQS_L2 MA_DQS_H3 MA_DQS_L3 MA_DQS_H4 MA_DQS_L4 MA_DQS_H5 MA_DQS_L5 MA_DQS_H6 MA_DQS_L6 MA_DQS_H7 MA_DQS_L7

MA_CLK_H0 MA_CLK_L0 MA_CLK_H1 MA_CLK_L1

MA_CKE0 MA_CKE1

MA_ODT0 MA_ODT1

MA_CS_L0 MA_CS_L1

MA_RAS_L MA_CAS_L MA_WE_L

MA_RESET_L MA_EVENT_L

M_VREF M_ZVDDIO

LOTES_ACA-ZIF-109-P12-A_FS1R2 @

MA_DATA0 MA_DATA1 MA_DATA2 MA_DATA3 MA_DATA4 MA_DATA5 MA_DATA6 MA_DATA7

MA_DATA8

MA_DATA9 MA_DATA10 MA_DATA11 MA_DATA12 MA_DATA13 MA_DATA14 MA_DATA15

MA_DATA16 MA_DATA17 MA_DATA18 MA_DATA19 MA_DATA20 MA_DATA21 MA_DATA22 MA_DATA23

MA_DATA24 MA_DATA25 MA_DATA26 MA_DATA27 MA_DATA28 MA_DATA29 MA_DATA30 MA_DATA31

MA_DATA32 MA_DATA33 MA_DATA34 MA_DATA35 MA_DATA36 MA_DATA37 MA_DATA38 MA_DATA39

MA_DATA40 MA_DATA41 MA_DATA42 MA_DATA43 MA_DATA44 MA_DATA45 MA_DATA46 MA_DATA47

MA_DATA48 MA_DATA49 MA_DATA50 MA_DATA51 MA_DATA52 MA_DATA53 MA_DATA54 MA_DATA55

MA_DATA56 MA_DATA57 MA_DATA58 MA_DATA59 MA_DATA60 MA_DATA61 MA_DATA62 MA_DATA63

E13 J13 H15 J15 H13 F13 F15 E15

H17 F17 E19 J19 G16 H16 H19 F19

H20 F21 J23 H23 G20 E20 G22 H22

G24 E25 G27 G26 F23 H24 E28 F27

AB28 AC27 AD25 AA24 AE28 AD28 AB26 AC25

Y23 AA23 Y21 AA20 AB24 AD24 AA21 AC21

AA19 AC19 AC17 AA17 AB20 Y19 AD18 AD17

AA16 Y15 AA13 AC13 Y17 AB16 AB14 Y13

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7

DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15

DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23

DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31

DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39

DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47

DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55

DDR_A_D56DDR_A_WE# DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

DDR_A_D[0..63] <10>

DDR_B_DQS[0..7]<11>

DDR_B_DQS#[0..7]<11>

JAPUC

MEMORY CHANNEL B

DDR_B_MA[0..15]<11>

DDR_B_BS0<11> DDR_B_BS1<11> DDR_B_BS2<11> DDR_B_DM[0..7]<11>

DDR_B_CLK0<11> DDR_B_CLK0#<11> DDR_B_CLK1<11> DDR_B_CLK1#<11>

DDR_B_CKE0<11> DDR_B_CKE1<11>

DDR_B_ODT0<11> DDR_B_ODT1<11>

DDR_B_SCS0#<11> DDR_B_SCS1#<11>

DDR_B_RAS#<11> DDR_B_CAS#<11> DDR_B_WE#<11>

MEM_MB_RST#<11> MEM_MB_EVENT#<11>

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15

DDR_B_BS0 DDR_B_BS1 DDR_B_BS2

DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7

DDR_B_DQS0 DDR_B_DQS#0 DDR_B_DQS1 DDR_B_DQS#1 DDR_B_DQS2 DDR_B_DQS#2 DDR_B_DQS3 DDR_B_DQS#3 DDR_B_DQS4 DDR_B_DQS#4 DDR_B_DQS5 DDR_B_DQS#5 DDR_B_DQS6 DDR_B_DQS#6 DDR_B_DQS7 DDR_B_DQS#7

DDR_B_CLK0 DDR_B_CLK0# DDR_B_CLK1 DDR_B_CLK1#

DDR_B_CKE0 DDR_B_CKE1

DDR_B_ODT0 DDR_B_ODT1

DDR_B_SCS0# DDR_B_SCS1#

DDR_B_RAS# DDR_B_CAS# DDR_B_WE#

MEM_MB_RST# MEM_MB_EVENT#

M28 M27 M24 M25

W26

AF25 AG22 AH18 AD14

AG24 AG25 AG21 AF21 AG17 AG18 AH14 AG14

W27

T27 P24 P25 N27 N26

L26 U26 L27 K27

K25 K24

U27 T28 K28

D14 A18 A22 C25

C15 B15 E18 D18 E22 D22 B26 A26

R26 R27 P27 P28

J26 J27

Y28 V25

Y27 V24

V27 V28

J25 T25

MEMORY CHANNEL B

MB_ADD0 MB_ADD1 MB_ADD2 MB_ADD3 MB_ADD4 MB_ADD5 MB_ADD6 MB_ADD7 MB_ADD8 MB_ADD9 MB_ADD10 MB_ADD11 MB_ADD12 MB_ADD13 MB_ADD14 MB_ADD15

MB_BANK0 MB_BANK1 MB_BANK2

MB_DM0 MB_DM1 MB_DM2 MB_DM3 MB_DM4 MB_DM5 MB_DM6 MB_DM7

MB_DQS_H0 MB_DQS_L0 MB_DQS_H1 MB_DQS_L1 MB_DQS_H2 MB_DQS_L2 MB_DQS_H3 MB_DQS_L3 MB_DQS_H4 MB_DQS_L4 MB_DQS_H5 MB_DQS_L5 MB_DQS_H6 MB_DQS_L6 MB_DQS_H7 MB_DQS_L7

MB_CLK_H0 MB_CLK_L0 MB_CLK_H1 MB_CLK_L1

MB_CKE0 MB_CKE1

MB_ODT0 MB_ODT1

MB_CS_L0 MB_CS_L1

MB_RAS_L MB_CAS_L MB_WE_L

MB_RESET_L MB_EVENT_L

LOTES_ACA-ZIF-109-P12-A_FS1R2 @

MB_DATA0 MB_DATA1 MB_DATA2 MB_DATA3 MB_DATA4 MB_DATA5 MB_DATA6 MB_DATA7

MB_DATA8

MB_DATA9 MB_DATA10 MB_DATA11 MB_DATA12 MB_DATA13 MB_DATA14 MB_DATA15

MB_DATA16 MB_DATA17 MB_DATA18 MB_DATA19 MB_DATA20 MB_DATA21 MB_DATA22 MB_DATA23

MB_DATA24 MB_DATA25 MB_DATA26 MB_DATA27 MB_DATA28 MB_DATA29 MB_DATA30 MB_DATA31

MB_DATA32 MB_DATA33 MB_DATA34 MB_DATA35 MB_DATA36 MB_DATA37 MB_DATA38 MB_DATA39

MB_DATA40 MB_DATA41 MB_DATA42 MB_DATA43 MB_DATA44 MB_DATA45 MB_DATA46 MB_DATA47

MB_DATA48 MB_DATA49 MB_DATA50 MB_DATA51 MB_DATA52 MB_DATA53 MB_DATA54 MB_DATA55

MB_DATA56 MB_DATA57 MB_DATA58 MB_DATA59 MB_DATA60 MB_DATA61 MB_DATA62 MB_DATA63

A14 B14 D16 E16 B13 C13 B16 A16

C17 B18 B20 A20 E17 B17 B19 C19

C21 B22 C23 A24 D20 B21 E23 B23

E24 B25 B27 D28 B24 D24 D26 C27

AG26 AH26 AF23 AG23 AG27 AF27 AH24 AE24

AE22 AH22 AE20 AH20 AD23 AD22 AD21 AD20

AF19 AE18 AE16 AH16 AG20 AG19 AF17 AD16

AG15 AD15 AG13 AD13 AG16 AF15 AE14 AF13

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7

DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15

DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23

DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31

DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39

DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47

DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55

DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

DDR_B_D[0..63] <11>

EVENT# pull high 0.75V Reference Voltage

+1.5V

4 4

MEM_MA_EVENT# MEM_MB_EVENT#

A

R15 1K_0402_5%R15 1K_0402_5%

1 2

R61 1K_0402_5%R61 1K_0402_5%

1 2

R64

1K_0402_1%

R65

1K_0402_1%

+1.5V

1 2

B

1

C124

C124 1000P_0402_50V7K

1000P_0402_50V7K

2

15mil

+MEM_VREF

2

C125

0.1U_0402_16V7K

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2011/11/28 2013/12/31

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC,MB LA-8863

4019IT

651Friday, March 23, 2012

E

of

A

Close to APU

C56 0.1U_0402_16V7KC56 0.1U_0402_16V7K

1 2

C48 0.1U_0402_16V7KC48 0.1U_0402_16V7K

1 2

C58 0.1U_0402_16V7KC58 0.1U_0402_16V7K

1 2

C53 0.1U_0402_16V7KC53 0.1U_0402_16V7K

1 2

LVDS

DP0_TXP0_C<21> DP0_TXN0_C<21>

DP0_TXP1_C<21> DP0_TXN1_C<21>

C63 0.1U_0402_16V7KC63 0.1U_0402_16V7K

1 1

CRT (To FCH)

HDMI

ML_VGA_TXP0<27> ML_VGA_TXN0<27>

ML_VGA_TXP1<27> ML_VGA_TXN1<27>

ML_VGA_TXP2<27> ML_VGA_TXN2<27>

ML_VGA_TXP3<27> ML_VGA_TXN3<27>

UMA_HDMI_TX2+<24> UMA_HDMI_TX2-<24>

UMA_HDMI_TX1+<24> UMA_HDMI_TX1-<24>

UMA_HDMI_TX0+<24> UMA_HDMI_TX0-<24>

UMA_HDMI_TXC+<24>

UMA_HDMI_TXC-<24>

100MHz (SS)

100MHz (NSS)

APU_SVC<47>

2 2

3 3

APU_SVD<47> APU_SVT<47>

APU_VDD_RUN_FB_L<47>

APU_VDDNB_SEN<47>

APU_VDD_SEN<47>

1 2

C64 0.1U_0402_16V7KC64 0.1U_0402_16V7K

1 2

C65 0.1U_0402_16V7KC65 0.1U_0402_16V7K

1 2

C66 0.1U_0402_16V7KC66 0.1U_0402_16V7K

1 2

C67 0.1U_0402_16V7KC67 0.1U_0402_16V7K

1 2

C68 0.1U_0402_16V7KC68 0.1U_0402_16V7K

1 2

C69 0.1U_0402_16V7KC69 0.1U_0402_16V7K

1 2

C70 0.1U_0402_16V7KC70 0.1U_0402_16V7K

1 2

APU_CLKP<25> APU_CLKN<25>

APU_DISP_CLKP<25> APU_DISP_CLKN<25>

R31 0_0402_5%@R31 0_0402_5%@

1 2

R32 0_0402_5%@R32 0_0402_5%@

1 2

R33 0_0402_5%@R33 0_0402_5%@

1 2

APU_SIC<9> APU_SID<9>

APU_RST#<25> APU_PWRGD<25,47>

APU_ALERT#<27>

R212 0_0402_5%R212 0_0402_5%

1 2

R214 0_0402_5%R214 0_0402_5%

1 2

R215 0_0402_5%R215 0_0402_5%

1 2

APU_PROCHOT# APU_THERMTRIP# APU_ALERT#

APU_TDI APU_TDO APU_TCK APU_TMS APU_TRST# APU_DBRDY APU_DBREQ#

T9T9 T10T10 T13T13

UMA_HDMI_TX2+ UMA_HDMI_TX2-

UMA_HDMI_TX1+ UMA_HDMI_TX1-

UMA_HDMI_TX0+ UMA_HDMI_TX0-

UMA_HDMI_TXC+ UMA_HDMI_TXC-

APU_CLKP APU_CLKN

APU_DISP_CLKP APU_DISP_CLKN

APU_SVC_R APU_SVD_R

APU_SVT_R

APU_SIC APU_SID

APU_RST# APU_PWRGD

VDDNB_SENSE VDD_SENSE

DP0_TXP0 DP0_TXN0

DP0_TXN1

DP1_TXP0 DP1_TXN0

DP1_TXP1 DP1_TXN1

DP1_TXP2 DP1_TXN2

DP1_TXP3 DP1_TXN3

VSS_SENSE

B

JAPUD

ANALOG/DISPLAY/MISC

DP0_TXP0 DP0_TXN0

DP0_TXP1 DP0_TXN1

DP0_TXP2 DP0_TXN2

DP0_TXP3 DP0_TXN3

DP1_TXP0 DP1_TXN0

DP1_TXP1 DP1_TXN1

DP1_TXP2 DP1_TXN2

DP1_TXP3 DP1_TXN3

DP2_TXP0 DP2_TXN0

DP2_TXP1 DP2_TXN1

DP2_TXP2 DP2_TXN2

DP2_TXP3 DP2_TXN3

CLKIN_H CLKIN_L

DISP_CLKIN_H DISP_CLKIN_L

SVC SVD

SVT SIC

SID RESET_L

PWROK PROCHOT_L

THERMTRIP_L ALERT_L

TDI TDO TCK TMS TRST_L DBRDY DBREQ_L

VSS_SENSE VDDP_SENSE VDDNB_SENSE VDDIO_SENSE VDD_SENSE VDDR_SENSE

LOTES_ACA-ZIF-109-P12-A_FS1R2 @

DISPLAY PORT 0

DISPLAY PORT MISC.

DISPLAY PORT 2 DISPLAY PORT 1

TEST

CTRL SER. CLK

JTAG

SENSE

AE11 AD11

AB11 AA11

AG12 AH12

AF10 AB12

AC10 AE12 AF12

L3 L2

K5 K4

K2 K1

J3 J2

H5 H4

H2 H1

G3 G2

F2 F1

L9 L8

L5 L6

K8 K7

J6 J5

B3 A3

C3

H10

J10 F10 G10

F9 G9 H9

B4 C5 A4 A5 C4 B5

DP0_AUXP DP0_AUXN

DP1_AUXP DP1_AUXN

DP2_AUXP DP2_AUXN

DP3_AUXP DP3_AUXN

DP4_AUXP DP4_AUXN

DP5_AUXP DP5_AUXN

DP0_HPD DP1_HPD DP2_HPD DP3_HPD DP4_HPD DP5_HPD

DP_BLON

DP_DIGON

DP_VARY_BL

DP_AUX_ZVSS

TEST10 TEST14 TEST15 TEST16 TEST17 TEST18 TEST19 TEST20

TEST24 TEST25_H TEST25_L TEST28_H TEST28_L TEST30_H TEST30_L

TEST31 TEST32_H TEST32_L

TEST35

DMAACTIVE_L

RSVD

TEST6 TEST9

FS1R2

TEST4 TEST5

RSVD1 RSVD2 RSVD3 RSVD4

DP0_AUXP

D1

DP0_AUXN

D2

DP1_AUXP

E1

DP1_AUXN

E2

UMA_HDMI_CLK

D5

UMA_HDMI_DATA

D6 E5

E6 F5

F6 G5

G6

LVDS_HPD

D3

FCH_CRT_HPD

E3

HDMI_HPD

D7 E7 F7 G7

C6 B6 A6

DP_AUX_ZVSS

C1 AD12

M18 N18 F11 G11 H11 J11

APU_TEST18

F12

APU_TEST19

G12

APU_TEST20

J12

APU_TEST24

H12

TEST25_H

AE10

TEST25_L

AD10 L10 M10 P19 R19

APU_TEST31

K22 T19 N19

APU_TEST35

AA12

FS1R2

W10

DMA_ACTIVE#

AC12 P18

R18

Y10 AA10 Y12 K21

C

C47 0.1U_0402_16V7KC47 0.1U_0402_16V7K

1 2

C49 0.1U_0402_16V7KC49 0.1U_0402_16V7K

1 2

C57 0.1U_0402_16V7KC57 0.1U_0402_16V7K

1 2

C52 0.1U_0402_16V7KC52 0.1U_0402_16V7K

1 2

LVDS_HPD <21> FCH_CRT_HPD <27> HDMI_HPD <24>

DP_INT_PWM <9>

1 2

R16 150_0402_1%R16 150_0402_1%

T5T5 T6T6 T1T1 T2T2 T3T3 T4T4

R18 1K_0402_5%R18 1K_0402_5%

1 2

R19 1K_0402_5%R19 1K_0402_5%

1 2

R21 1K_0402_5%R21 1K_0402_5%

1 2

R22 1K_0402_5%R22 1K_0402_5%

1 2

R23 510_0402_1%R23 510_0402_1%

1 2

R24 510_0402_1%R24 510_0402_1%

1 2 T7T7 T8T8

R27 39.2_0402_1%R27 39.2_0402_1%

1 2

R28 300_0402_5%R28 300_0402_5%

1 2

R29 300_0402_5%@R29 300_0402_5%@

1 2

R30 10K_0402_5%R30 10K_0402_5%

1 2

DMA_ACTIVE# <25>

T11T11 T12T12

DP0_AUXP_C <21> DP0_AUXN_C <21>

ML_VGA_AUXP <27> ML_VGA_AUXN <27>

UMA_HDMI_CLK <24> UMA_HDMI_DATA <24>

3.3V Tolerance

+1.2VS

Change TEST35 to pull-high

+1.5V

for HDMI issue

+3VALW

D

LVDS CRT (To FCH) HDMI

E

DP0_AUXP DP0_AUXNDP0_TXP1 DP1_AUXP DP1_AUXN LVDS_HPD FCH_CRT_HPD HDMI_HPD

APU_SVT_R APU_SVC_R APU_SVD_RDP_INT_PWM APU_SIC APU_SID APU_ALERT# DMA_ACTIVE#

DMA_ACTIVE# APU_RST# APU_PWRGD

UMA_HDMI_CLK UMA_HDMI_DATA

Aux signal are re-configured as I2C signals for DDC APU AUX pin are 3.3V tolerant

+1.5V

R25 1.8K_0402_5%R25 1.8K_0402_5% R58 1.8K_0402_5%R58 1.8K_0402_5% R10 1.8K_0402_5%R10 1.8K_0402_5% R11 1.8K_0402_5%R11 1.8K_0402_5% R74 100K_0402_5%R74 100K_0402_5% R75 100K_0402_5%R75 100K_0402_5% R95 100K_0402_5%R95 100K_0402_5%

R36 1K_0402_5%@R36 1K_0402_5%@ R39 1K_0402_5%@R39 1K_0402_5%@ R41 1K_0402_5%@R41 1K_0402_5%@ R42 1K_0402_5%R42 1K_0402_5% R44 1K_0402_5%R44 1K_0402_5% R46 1K_0402_5%R46 1K_0402_5% R48 1K_0402_5%R48 1K_0402_5%

R57 1K_0402_5%@R57 1K_0402_5%@ R52 300_0402_5%R52 300_0402_5% R54 300_0402_5%R54 300_0402_5%

APU_RST#

APU_PWRGD

1 2

C126 1000P_0402_50V7K

1 2

C127 1000P_0402_50V7K

R66 4.7K_0402_5%R66 4.7K_0402_5% R67 4.7K_0402_5%R67 4.7K_0402_5%

12 12 12 12 12 12 12

+1.5V

12 12 12 12 12 12 12

+1.5VS

12 12 12

@

+3VS

12 12

R55

1K_0402_5%

+1.5V

Close to JHDT

R97 1K_0402_5%R97 1K_0402_5%

1 2

R100 1K_0402_5%R100 1K_0402_5%

1 2

R110 1K_0402_5%R110 1K_0402_5%

1 2

R116 1K_0402_5%R116 1K_0402_5%

1 2

R117 1K_0402_5%R117 1K_0402_5%

1 2

4 4

APU_TDI APU_TCK APU_TMS APU_TRST# APU_DBREQ#

@

1 2

R121 0_0402_5%

@

1 2

R122 10K_0402_5%

@

1 2

R123 10K_0402_5%

@

1 2

R124 10K_0402_5%

A

HDT Debug conn

+1.5V

JHDT

1

3

5

7

9

11

13

15

17

19

SAMTE_ASP-136446-07-B

B

@JHDT

@

2 4 6

8 10 12 14 16 18 20

2 4 6 8 10 12 14 16 18 20

APU_TCK APU_TMS APU_TDI APU_TDO APU_PWRGD_RR APU_RST#_R APU_DBRDY APU_DBREQ#

Close to APU side, Debug Stuff

R125 0_0402_5%

R125 0_0402_5% R127 0_0402_5%

R127 0_0402_5%

@

1 2

R118 0_0402_5%

@

1 2

R119 0_0402_5%

@

1 2

@

1 2

APU_TEST19 APU_TEST18

Security Classification

APU_PWRGDAPU_TRST# APU_RST#

2011/11/28 2013/12/31

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2011/11/28 2013/12/31

Asserted as an input to force the processor into the HTC-active state

APU_PROCHOT#

Thermal Shutdown Temperature: 115 degree

Compal Secret Data

Deciphered Date

D

APU_THERMTRIP#

1K_0402_5%

@

1 2

R136 0_0402_5%

+1.5V

R68

1K_0402_5%

1 2

MMBT3904_NL_SOT23-3

Title

Size Document Number Rev

Custom

Date: Sheet

1 2

12

R69

R69 10K_0402_5%

10K_0402_5%

B

2

Q5

E

3 1

C

Compal Electronics, Inc.

SCHEMATIC,MB LA-8863

4019IT

H_PROCHOT# <36,47>APU_PROCHOT#<25>

H_THERMTRIP# <26>

751Friday, March 23, 2012

E

A

of

A

+APU_CORE

1 1

2 2

3 3

+2.5VS

L1

1 2

FBMA-L11-201209-300LMA30T

C165

4 4

C165

1

2

C170

4.7U_0603_6.3V6K

+APU_CORE_NB

+1.2VS

C164

0.22U_0402_6.3V6K

1

12

2

+1.5V

3300P_0402_50V7K

40mil

+VDDA+VDDA

JAPUE

F8

VDD_1

H6

VDD_2

J1

VDD_3

J14

VDD_4

P6

VDD_5

P10

VDD_6

J16

VDD_7

J18

VDD_8

J9

VDD_9

K19

VDD_10

K3

VDD_11

K17

VDD_12

M3

VDD_13

K6

VDD_14

V10

VDD_15

V18

VDD_16

V3

VDD_17

50A

VDD_18 VDD_19 VDD_20 VDD_21 VDD_22 VDD_23 VDD_24 VDD_25 VDD_26 VDD_27 VDD_28 VDD_29 VDD_30 VDD_31

VDDNB_1 VDDNB_2 VDDNB_3 VDDNB_4 VDDNB_5 VDDNB_6

33A

VDDNB_7 VDDNB_8 VDDNB_9 VDDNB_10 VDDNB_11 VDDNB_12

VDDIO_1 VDDIO_2 VDDIO_3 VDDIO_4 VDDIO_5 VDDIO_6 VDDIO_7 VDDIO_8 VDDIO_9 VDDIO_10 VDDIO_11

3.2A

VDDIO_12 VDDIO_13 VDDIO_14 VDDIO_15 VDDIO_16 VDDIO_17 VDDIO_18

VDDP_1 VDDP_2 VDDP_3 VDDP_4 VDDP_5

VDDA

0.75A

LOTES_ACA-ZIF-109-P12-A_FS1R2

AA28

AB10

F3

L18

V6 W1 T18

Y14 AA1 AB6 AC1

R1

P3

K10

H3

M19

C8

D10

B8

B12

C9

A9

A10

A8

A11 E10 E11 C10

H26 K20

J28

K23 K26

L22 L25 L28

M20 M23 M26 N22 N25 N28 P20 P23 P26

AH6 AH5 AH4 AH3 AH7

VDD_32 VDD_33 VDD_34 VDD_35 VDD_36 VDD_37 VDD_38 VDD_39 VDD_40 VDD_41 VDD_42 VDD_43 VDD_44 VDD_45 VDD_46 VDD_47 VDD_48 VDD_49 VDD_50 VDD_51 VDD_52 VDD_53 VDD_54 VDD_55 VDD_56 VDD_57 VDD_58 VDD_59 VDD_60 VDD_61 VDD_62

VDDNB_13 VDDNB_14 VDDNB_15 VDDNB_16 VDDNB_17 VDDNB_18 VDDNB_19 VDDNB_20 VDDNB_21 VDDNB_22 VDDNB_23

VDDNB_CAP_1 VDDNB_CAP_2

VDDIO_19 VDDIO_20 VDDIO_21 VDDIO_22 VDDIO_23 VDDIO_24 VDDIO_25 VDDIO_26 VDDIO_27 VDDIO_28 VDDIO_29 VDDIO_30 VDDIO_31 VDDIO_32 VDDIO_33 VDDIO_34 VDDIO_35 VDDIO_36

VDDR_1 VDDR_2 VDDR_3

3.5A5A

VDDR_4

A

+APU_CORE

R11 T10 H8 G1 U11 W11 W13 W15 W17 W19 AB3 AD3 AD6 AE1 L1 Y6 M6 N11 N1 T3 T6 U19 U1 Y16 Y18 Y3 D4 F4 AF6 AF3 L11

C11 C12 D9 D8 D12 D11 B11 A12 B10 E12 B9

K13 K12

T23 T26 U22 U25 U28 Y26 T20 R28 R25 R22 V20 V23 V26 W22 W25 W28 Y24 G28

AG10 AH8 AH9 AH10

@

B

C76

B

+1.2VS

+APU_CORE_NB

+VDDNB_CAP

+1.5V

C109

1

2

C72

22U_0805_6.3V6M

1

2

C117

C110

180P_0402_50V8J

1

2

C73

10U_0603_6.3V6M

1

2

+1.5V

C85

1

2

C119

22U_0805_6.3V6M

1

2

VDDR Decoupling

C115

C111

180P_0402_50V8J

1000P_0402_50V7K

1

2

VDDP Decoupling

C146

C74

10U_0603_6.3V6M

1

2

C

C91

C89

C88

C86

22U_0805_6.3V6M

1

2

C141

180P_0402_50V8J

1

2

C116

0.22U_0402_6.3V6K

1

2

C88

C87

22U_0805_6.3V6M

C77

22U_0805_6.3V6M

1

2

+1.5V

1

C102

2

+1.2VS

C78

C79

10U_0603_6.3V6M

1

2

1

2

C91

C90

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K 1

1

2

C104

C103

180P_0402_50V8J

0.22U_0402_6.3V6K

10U_0603_6.3V6M

180P_0402_50V8J

0.22U_0402_6.3V6K

0.22U_0402_6.3V6K 1

1

2

C93

C94

C92

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K 1

2

C131

1

2

C94

0.22U_0402_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K 1

1

2

180P_0402_50V8J

If the VSS plane is cut to create a VDDIO plane, place across the VDDIO and VSS plane split

C96

C95

0.22U_0402_6.3V6K

0.22U_0402_6.3V6K 1

1

2

D

Co-layout with C100 on PVT

+1.5V

1

+

C147

C147 330U_D2_2V_Y

330U_D2_2V_Y

2

C98

C97

0.22U_0402_6.3V6K

0.22U_0402_6.3V6K 1

1

2

C130

C99

0.22U_0402_6.3V6K

180P_0402_50V8J

1

2

+

C100

C100 330U_2.5V_M_R17

330U_2.5V_M_R17 @

@

2

H=4.2mm

E

JAPUF

J20

VSS_1

L4

VSS_2

R7

VSS_3

W18

VSS_4

A15

VSS_5

AB17

VSS_6

AC22

VSS_7

AE21

VSS_8

AF24

VSS_9

AH23

VSS_10

AH25

VSS_11

B7

VSS_12

C14

VSS_13

C16

VSS_14

C2

VSS_15

C20

VSS_16

C22

VSS_17

C24

VSS_18

C26

VSS_19

C28

VSS_20

D13

VSS_21

D15

VSS_22

D17

VSS_23

D19

VSS_24

D23

VSS_25

D25

VSS_26

D27

VSS_27

E4

VSS_28

E9

VSS_29

F14

VSS_30

F16

VSS_31

F18

VSS_32

F20

VSS_33

F22

VSS_34

F26

VSS_35

F28

VSS_36

G13

VSS_37

G15

VSS_38

G17

VSS_39

G19

VSS_40

G21

VSS_41

G23

VSS_42

G25

VSS_43

G4

VSS_44

J22

VSS_45

J24

VSS_46

J4

VSS_47

J7

VSS_48

K11

VSS_49

K14

VSS_50

K9

VSS_51

AC11

VSS_52

L19

VSS_53

L7

VSS_54

M11

VSS_55

AF11

VSS_56

V19

VSS_57

V9

VSS_58

W16

VSS_59

W4

VSS_60

W7

VSS_61

Y11

VSS_62

Y20

VSS_63

Y22

VSS_64

Y9

VSS_65

A17

VSS_66

A13

VSS_67

K16

VSS_68

F24

VSS_69

G8

VSS_70

H7

VSS_71

J8

VSS_72

LOTES_ACA-ZIF-109-P12-A_FS1R2

VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143

VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99

A19 A21 A23 A25 A7 AA4 AA7 AB13 AB15 AB19 AB21 AB23 AB25 AB27 AB9 AC14 AC16 AC18 AC20 AC24 AC26 AC28 AC4 AC7 AD9 AE13 AE15 AE17 M9 N10 N4 N7 R10 R4 T11 T9 U10 U18 U4 U7 V11 AE19 AE23 AE25 AE27 AE4 AE7 AF14 AF16 AF18 AF20 AF22 AF26 AF28 AF9 AG4 AG7 AH13 AH15 AH17 AH19 AH21 P9 C18 D21 W14 P11 C7 E8 K18 W12

@

Demo Board Capacitor

CORE_NB_CAP 22uF x 2 180pF x 1

VDDA

4.7uF x 1

0.22uF x 1

3.3nF x 1

Compal Electronics, Inc.

SCHEMATIC,MB LA-8863

4019IT

VDDIO_SUS (CPU side) 22uF x 4

4.7uF x 4

0.22uF x 6 +2(split) 180pF x 1 + 2(split)

VDDIO_SUS (DIMM x2) 100uF x 2

0.1uF x 12

E

851Friday, March 23, 2012

A

of

C143

C144

C145

180P_0402_50V8J

1

2

C144

C75

0.22U_0402_6.3V6K

180P_0402_50V8J

0.22U_0402_6.3V6K

1000P_0402_50V7K

1

@

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2011/11/28 2013/12/31

Compal Secret Data

Deciphered Date

APU_CORE 22uF x 10

0.22uF x 2

0.01uF x 3 180pF x 2

VDDP

0.22uF x 2 180pF x 2

D

CORE_NB 22uF x 2 10uF x 1

0.22uF x 2 180pF x 3

VDDR

0.22uF x 2 1nF x 1 180pF x 2

Title

Size Document Number Rev

Custom

Date: Sheet

5

4

3

2

1

SB-TSI

CPU TSI interface level shift

D D

APU_SID<7>

APU_SIC<7>

C C

+3VS

BSH111_SOT23-3

APU_SIC

BSH111_SOT23-3

R535

1 2

31.6K_0402_1%

@

C935 0.1U_0402_16V4Z

1 2

R536

1 2

30K_0402_1%

Vg = 1.607 V

G

2

Q14

EC_SMB_DA2APU_SID

13

D

S

D

S

G

2

Q15

EC_SMB_CK2

13

D

S

D

S

When APU High -> MOS OFF (Vgs < 0.4V ) APU Low -> MOS ON (Vgs > 1.3V)

BSH111, the Vgs is: min = 0.4V Max = 1.3V

EC_SMB_DA2 <13,36>

EC_SMB_CK2 <13,36>

Panel PWM

B B

DP_INT_PWM<7>

A A

1 2

R89 2.2K_0402_5%R89 2.2K_0402_5%

12

R76

4.7K_0402_5%

5

+3VS

12

R92

R92 47K_0402_5%

47K_0402_5%

C

Q21

2

B

MMBT3904_NL_SOT23-3

E

3 1

2

G

12

R93

4.7K_0402_5%

13

D

Q26

Q26 2N7002_SOT23-3

2N7002_SOT23-3

S

APU_INVT_PWM <21>

Security Classification

2011/11/28 2013/12/31

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/11/28 2013/12/31

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC,MB LA-8863

4019IT

951Friday, March 23, 2012

1

A

of

5

+VREF_DQA

D D

C C

B B

A A

+3VS

DDR_A_SCS1#<6>

C181

DDR_A_BS2<6>

DDR_A_CLK0<6> DDR_A_CLK0#<6>

DDR_A_BS0<6>

DDR_A_WE#<6>

DDR_A_CAS#<6>

@

1 C182

C182

2

2.2U_0603_6.3V6K

R90

R90 10K_0402_5%

10K_0402_5%

1

@

2

DDR_A_D0 DDR_A_D1

DDR_A_DM0 DDR_A_D2

DDR_A_D3 DDR_A_D8

DDR_A_D9 DDR_A_DQS#1

DDR_A_DQS1 DDR_A_D10

DDR_A_D11 DDR_A_D16

DDR_A_D17 DDR_A_DQS#2

DDR_A_DQS2 DDR_A_D18

DDR_A_D19 DDR_A_D24

DDR_A_D25 DDR_A_DM3 DDR_A_D26

DDR_A_D27

DDR_A_CKE0

DDR_A_BS2 DDR_A_MA12

DDR_A_MA9 DDR_A_MA8

DDR_A_MA5 DDR_A_MA3

DDR_A_MA1 DDR_A_CLK0

DDR_A_CLK0# DDR_A_MA10

DDR_A_BS0 DDR_A_WE#

DDR_A_CAS# DDR_A_MA13

DDR_A_SCS1#

DDR_A_D32 DDR_A_D33

DDR_A_DQS#4 DDR_A_DQS4

DDR_A_D34 DDR_A_D35

DDR_A_D40 DDR_A_D41

DDR_A_DM5 DDR_A_D42

DDR_A_D43 DDR_A_D48

DDR_A_D49 DDR_A_DQS#6

DDR_A_DQS6 DDR_A_D50

DDR_A_D51 DDR_A_D56

DDR_A_D57 DDR_A_DM7 DDR_A_D58

DDR_A_D59

1 2

0.1U_0402_16V4Z

5

+0.75VS

12

R91

R91 10K_0402_5%

10K_0402_5%

+1.5V

JDDR3H

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1 DQS129RESET#

31

VSS11

33

DQ10

35

DQ11

37

VSS13

39

DQ16

41

DQ17

43

VSS15

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25 VSS2261DQS#3

63

DM3

65

VSS23

67

DQ26

69

DQ27

71

VSS25

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

LCN_DAN06-K4806-0102

@

DQ4 DQ5

VSS3

DQS#0

DQS0

VSS6

DQ6 DQ7

VSS8 DQ12 DQ13

VSS10

DM1

VSS12

DQ14 DQ15

VSS14

DQ20 DQ21

VSS16

DM2

VSS17

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21

DQS3

VSS24

DQ30 DQ31

VSS26

CKE1 VDD2

VDD4

VDD6

VDD8

VDD10

CK1

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

NC2

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30

DM4

VSS31

DQ38 DQ39

VSS33

DQ44 DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46 DQ47

VSS40

DQ52 DQ53

VSS42

DM6

VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62 DQ63

VSS52

EVENT#

SDA SCL

VTT2

BA1

S0#

A15 A14

A11

A7 A6

A4 A2

A0

G2

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206

4

+1.5V

DDR_A_D4 DDR_A_D5

DDR_A_DQS#0 DDR_A_DQS0

DDR_A_D6 DDR_A_D7

DDR_A_D12 DDR_A_D13

DDR_A_DM1 MEM_MA_RST#

DDR_A_D14 DDR_A_D15

DDR_A_D20 DDR_A_D21

DDR_A_DM2 DDR_A_D22

DDR_A_D23 DDR_A_D28

DDR_A_D29 DDR_A_DQS#3

DDR_A_DQS3 DDR_A_D30

DDR_A_D31

DDR_A_CKE1 DDR_A_MA15

DDR_A_MA14 DDR_A_MA11

DDR_A_MA7 DDR_A_MA6

DDR_A_MA4 DDR_A_MA2

DDR_A_MA0 DDR_A_CLK1

DDR_A_CLK1# DDR_A_BS1

DDR_A_RAS# DDR_A_SCS0#

DDR_A_ODT0 DDR_A_ODT1

+VREF_CAA DDR_A_D36

DDR_A_D37 DDR_A_DM4 DDR_A_D38

DDR_A_D39 DDR_A_D44

DDR_A_D45 DDR_A_DQS#5

DDR_A_DQS5 DDR_A_D46

DDR_A_D47 DDR_A_D52

DDR_A_D53 DDR_A_DM6 DDR_A_D54

DDR_A_D55 DDR_A_D60

DDR_A_D61 DDR_A_DQS#7

DDR_A_DQS7 DDR_A_D62

DDR_A_D63

MEM_MA_EVENT#

FCH_SDATA0 FCH_SCLK0

+0.75VS

4

DDR3 SO-DIMM A Standard Type

MEM_MA_RST# <6>

DDR_A_CKE1 <6>DDR_A_CKE0<6>

DDR_A_CLK1 <6> DDR_A_CLK1# <6>

DDR_A_BS1 <6> DDR_A_RAS# <6>

DDR_A_SCS0# <6> DDR_A_ODT0 <6>

DDR_A_ODT1 <6>

@

1

C162

C101

1000P_0402_50V7K

Close to JDDR3H.126

MEM_MA_EVENT# <6> FCH_SDATA0 <11,26,31> FCH_SCLK0 <11,26,31>

C161

0.1U_0402_16V7K

0.1U_0402_16V7K 2

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+1.5V

12

1K_0402_1%

12

1

1K_0402_1%

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K 2

3

DDR_A_DQS[0..7] <6> DDR_A_DQS#[0..7] <6>

DDR_A_D[0..63] <6> DDR_A_MA[0..15] <6> DDR_A_DM[0..7] <6>

+VREF_DQA

@

1

C157

C156

C71

1000P_0402_50V7K

2

2.2U_0603_6.3V6K

0.1U_0402_16V7K

0.1U_0402_16V7K 2

2

Close to JDDR3H.1

Co-layout with C218 on PVT

+1.5V

1

+

R80

R82

Compal Secret Data

2011/11/28 2013/12/31

3

Compal Secret Data

+

C148

C148 330U_D2_2V_Y

330U_D2_2V_Y

2

Layout Note: Place near JDDR3H

+1.5V

Deciphered Date

@

+

C218 330U_6.3V_M_R15

1 2

C166 0.1U_0402_16V4ZC166 0.1U_0402_16V4Z

1 2

C168 0.1U_0402_16V4ZC168 0.1U_0402_16V4Z

1 2

C171 0.1U_0402_16V4ZC171 0.1U_0402_16V4Z

1 2

C174 0.1U_0402_16V4ZC174 0.1U_0402_16V4Z

1 2

C173 0.1U_0402_16V4ZC173 0.1U_0402_16V4Z

1 2

C176 0.1U_0402_16V4ZC176 0.1U_0402_16V4Z

1 2

C179 0.1U_0402_16V4ZC179 0.1U_0402_16V4Z

1 2

C178 0.1U_0402_16V4ZC178 0.1U_0402_16V4Z

1 2

C185 0.1U_0402_16V4ZC185 0.1U_0402_16V4Z

1 2

C180 0.1U_0402_16V4ZC180 0.1U_0402_16V4Z

1 2

+1.5V

12

1K_0402_1%

12

1K_0402_1%

R79

R81

2

Layout Note: Place near JDDR3H.203 and 204

+0.75VS

@

C114 0.1U_0402_16V4Z

1 2

C84 4.7U_0603_6.3V6KC84 4.7U_0603_6.3V6K

1 2

C186 0.1U_0402_16V4ZC186 0.1U_0402_16V4Z

1 2

C205 0.1U_0402_16V4ZC205 0.1U_0402_16V4Z

1 2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC,MB LA-8863

4019IT

1

+1.5V

A

10 51Friday, March 23, 2012

1

A

of

A

+VREF_DQB

1 1

2 2

3 3

4 4

2.2U_0603_6.3V6K

DDR_B_CKE0<6>

DDR_B_BS2<6>

DDR_B_CLK0<6> DDR_B_CLK0#<6>

DDR_B_WE#<6> DDR_B_CAS#<6>

DDR_B_SCS1#<6>

+3VS

Change SODIMM1 SMbus address to A2(SA0=1, SA1=0) on DVT

C207

1

2

1

C208

2

0.1U_0402_16V4Z

DDR_B_D0 DDR_B_D1

DDR_B_DM0 DDR_B_D2

DDR_B_D3 DDR_B_D8

DDR_B_D9 DDR_B_DQS#1

DDR_B_DQS1 DDR_B_D10

DDR_B_D11 DDR_B_D16

DDR_B_D17 DDR_B_DQS#2

DDR_B_DQS2 DDR_B_D18

DDR_B_D19 DDR_B_D24

DDR_B_D25 DDR_B_DM3 DDR_B_D26

DDR_B_D27

DDR_B_CKE0

DDR_B_BS2 DDR_B_MA12

DDR_B_MA9 DDR_B_MA8

DDR_B_MA5 DDR_B_MA3

DDR_B_MA1 DDR_B_CLK0

DDR_B_CLK0# DDR_B_MA10

DDR_B_BS0 DDR_B_WE#

DDR_B_CAS# DDR_B_MA13

DDR_B_SCS1#

DDR_B_D37 DDR_B_D36

DDR_B_DQS#4 DDR_B_DQS4

DDR_B_D34 DDR_B_D35

DDR_B_D40 DDR_B_D41

DDR_B_DM5 DDR_B_D42

DDR_B_D43 DDR_B_D48

DDR_B_D49 DDR_B_DQS#6

DDR_B_DQS6 DDR_B_D54

DDR_B_D55 DDR_B_D56

DDR_B_D57 DDR_B_DM7 DDR_B_D58

DDR_B_D59

R98

1 2

10K_0402_5%

A

+0.75VS

R99

R99 10K_0402_5%

10K_0402_5%

1 2

+1.5V

JDDR3L

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1 DQS129RESET#

31

VSS11

33

DQ10

35

DQ11

37

VSS13

39

DQ16

41

DQ17

43

VSS15

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25 VSS2261DQS#3

63

DM3

65

VSS23

67

DQ26

69

DQ27

71

VSS25

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

LCN_DAN06-K4406-0102

@

DQ4 DQ5

VSS3

DQS#0

DQS0

VSS6

DQ6 DQ7

VSS8 DQ12 DQ13

VSS10

DM1

VSS12

DQ14 DQ15

VSS14

DQ20 DQ21

VSS16

DM2

VSS17

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21

DQS3

VSS24

DQ30 DQ31

VSS26

CKE1 VDD2

VDD4

VDD6

VDD8

VDD10

CK1

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

NC2

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30

DM4

VSS31

DQ38 DQ39

VSS33

DQ44 DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46 DQ47

VSS40

DQ52 DQ53

VSS42

DM6

VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62 DQ63

VSS52

EVENT#

SDA SCL

VTT2

A15 A14

A11

BA1

S0#

A7 A6

A4 A2

A0

G2

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206

B

+1.5V

DDR_B_D4 DDR_B_D5

DDR_B_DQS#0 DDR_B_DQS0

DDR_B_D6 DDR_B_D7

DDR_B_D12 DDR_B_D13

DDR_B_DM1 MEM_MB_RST#

DDR_B_D14 DDR_B_D15

DDR_B_D20 DDR_B_D21

DDR_B_DM2 DDR_B_D22

DDR_B_D23 DDR_B_D28

DDR_B_D29 DDR_B_DQS#3

DDR_B_DQS3 DDR_B_D30

DDR_B_D31

DDR_B_CKE1 DDR_B_MA15

DDR_B_MA14 DDR_B_MA11

DDR_B_MA7 DDR_B_MA6

DDR_B_MA4 DDR_B_MA2

DDR_B_MA0 DDR_B_CLK1

DDR_B_CLK1# DDR_B_BS1

DDR_B_RAS# DDR_B_SCS0#

DDR_B_ODT0 DDR_B_ODT1

+VREF_CAB DDR_B_D32

DDR_B_D33 DDR_B_DM4 DDR_B_D38

DDR_B_D39 DDR_B_D44

DDR_B_D45 DDR_B_DQS#5

DDR_B_DQS5 DDR_B_D46

DDR_B_D47 DDR_B_D52

DDR_B_D53 DDR_B_DM6 DDR_B_D50

DDR_B_D51 DDR_B_D60

DDR_B_D61 DDR_B_DQS#7

DDR_B_DQS7 DDR_B_D62

DDR_B_D63

MEM_MB_EVENT#

FCH_SDATA0 FCH_SCLK0

+0.75VS

B

DDR3 SO-DIMM B Standard Type

MEM_MB_RST# <6>

DDR_B_CKE1 <6>

DDR_B_CLK1 <6> DDR_B_CLK1# <6>

DDR_B_BS1 <6> DDR_B_RAS# <6>DDR_B_BS0<6>

DDR_B_SCS0# <6> DDR_B_ODT0 <6>

DDR_B_ODT1 <6>

@

1

C113

C188

1000P_0402_50V7K

2

Close to JDDR3L.126

MEM_MB_EVENT# <6> FCH_SDATA0 <10,26,31> FCH_SCLK0 <10,26,31>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

C187

2.2U_0603_6.3V6K

0.1U_0402_16V7K

0.1U_0402_16V7K 2

2

C

DDR_B_DQS#[0..7] <6> DDR_B_DQS[0..7] <6> DDR_B_D[0..63] <6> DDR_B_MA[0..15] <6> DDR_B_DM[0..7] <6>

+VREF_DQB

1

C184

C112

0.1U_0402_16V7K

1000P_0402_50V7K

2

Close to JDDR3L.1

+1.5V

12

R86

1K_0402_1%

12

R94

1K_0402_1%

Compal Secret Data

2011/11/28 2013/12/31

C

Compal Secret Data

Layout Note: Place near JDDR3L

+1.5V

Deciphered Date

@

+

C189 330U_B2_2.5VM_R15M

1 2

C167 0.1U_0402_16V4ZC167 0.1U_0402_16V4Z

1 2

C169 0.1U_0402_16V4ZC169 0.1U_0402_16V4Z

1 2

C172 0.1U_0402_16V4ZC172 0.1U_0402_16V4Z

1 2

C175 0.1U_0402_16V4ZC175 0.1U_0402_16V4Z

1 2

C195 0.1U_0402_16V4ZC195 0.1U_0402_16V4Z

1 2

C177 0.1U_0402_16V4ZC177 0.1U_0402_16V4Z

1 2

C190 0.1U_0402_16V4ZC190 0.1U_0402_16V4Z

1 2

C191 0.1U_0402_16V4ZC191 0.1U_0402_16V4Z

1 2

C192 0.1U_0402_16V4ZC192 0.1U_0402_16V4Z

1 2

C193 0.1U_0402_16V4ZC193 0.1U_0402_16V4Z

1 2

@

1

C183

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K 2

D

+1.5V

12

1K_0402_1%

12

1K_0402_1%

D

R83

R84

E

Layout Note: Place near JDDRL.203 and 204

+0.75VS

@

C118 0.1U_0402_16V4Z

1 2

C142 4.7U_0603_6.3V6KC142 4.7U_0603_6.3V6K

1 2

C194 0.1U_0402_16V4ZC194 0.1U_0402_16V4Z

1 2

C206 0.1U_0402_16V4ZC206 0.1U_0402_16V4Z

1 2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC,MB LA-8863

4019IT

+1.5V

11 51Friday, March 23, 2012

of

E

of

A

B

C

D

E

PCIE_CTX_C_GRX_P[0..15]<5> PCIE_CTX_C_GRX_N[0..15]<5>

1 1

2 2

3 3

CLK_PCIE_VGA<25> CLK_PCIE_VGA#<25>

GPU_RST#<25>

PCIE_CTX_C_GRX_P[0..15] PCIE_CTX_C_GRX_N[0..15]

PCIE_CTX_C_GRX_P0 PCIE_CTX_C_GRX_N0

PCIE_CTX_C_GRX_P1 PCIE_CTX_C_GRX_N1

PCIE_CTX_C_GRX_P2 PCIE_CTX_C_GRX_N2

PCIE_CTX_C_GRX_P3 PCIE_CTX_C_GRX_N3

PCIE_CTX_C_GRX_P4 PCIE_CTX_C_GRX_N4

PCIE_CTX_C_GRX_P5 PCIE_CTX_C_GRX_N5

PCIE_CTX_C_GRX_P6 PCIE_CTX_C_GRX_N6

PCIE_CTX_C_GRX_P7 PCIE_CTX_C_GRX_N7

PCIE_CTX_C_GRX_P8 PCIE_CTX_C_GRX_N8

PCIE_CTX_C_GRX_P9 PCIE_CTX_C_GRX_N9

PCIE_CTX_C_GRX_P10 PCIE_CTX_C_GRX_N10

PCIE_CTX_C_GRX_P11 PCIE_CTX_C_GRX_N11

PCIE_CTX_C_GRX_P12 PCIE_CTX_C_GRX_N12

PCIE_CTX_C_GRX_P13 PCIE_CTX_C_GRX_N13

PCIE_CTX_C_GRX_P14 PCIE_CTX_C_GRX_N14

PCIE_CTX_C_GRX_P15 PCIE_CTX_C_GRX_N15

CLK_PCIE_VGA CLK_PCIE_VGA#

1 2

RV64 1K_0402_5%RV64 1K_0402_5%

GPU_RST#

RV436

RV436 100K_0402_5%

100K_0402_5%

1 2

UV1A

AA38

PCIE_RX0P

Y37

PCIE_RX0N

Y35

PCIE_RX1P

W36

PCIE_RX1N

W38

PCIE_RX2P

V37

PCIE_RX2N

V35

PCIE_RX3P

U36

PCIE_RX3N

U38

PCIE_RX4P

T37

PCIE_RX4N

T35

PCIE_RX5P

R36

PCIE_RX5N

R38

PCIE_RX6P

P37

PCIE_RX6N

P35

PCIE_RX7P

N36

PCIE_RX7N

N38

PCIE_RX8P

M37

PCIE_RX8N

M35

PCIE_RX9P

L36

PCIE_RX9N

L38

PCIE_RX10P

K37

PCIE_RX10N

K35

PCIE_RX11P

J36

PCIE_RX11N

J38

PCIE_RX12P

H37

PCIE_RX12N

H35

PCIE_RX13P

G36

PCIE_RX13N

G38

PCIE_RX14P

F37

PCIE_RX14N

F35

PCIE_RX15P

E37

PCIE_RX15N

CLOCK

AB35

PCIE_REFCLKP

AA36

PCIE_REFCLKN

AH16

PWRGOOD

AA30

PERSTB

THAMES XT M2 THR3@

PCIE_TX0P PCIE_TX0N

PCIE_TX1P PCIE_TX1N

PCIE_TX2P PCIE_TX2N

PCIE_TX3P PCIE_TX3N

PCIE_TX4P

PCI EXPRESS INTERFACE

PCIE_TX4N

PCIE_TX5P PCIE_TX5N

PCIE_TX6P PCIE_TX6N

PCIE_TX7P PCIE_TX7N

PCIE_TX8P PCIE_TX8N

PCIE_TX9P PCIE_TX9N

PCIE_TX10P

PCIE_TX10N

PCIE_TX11P

PCIE_TX11N

PCIE_TX12P

PCIE_TX12N

PCIE_TX13P

PCIE_TX13N

PCIE_TX14P

PCIE_TX14N

PCIE_TX15P

PCIE_TX15N

CALIBRATION

PCIE_CALRP

PCIE_CALRN

Need to modify P/N

PCIE_GTX_C_CRX_P[0..15] PCIE_GTX_C_CRX_N[0..15]

PCIE_GTX_CRX_P0

Y33

PCIE_GTX_CRX_N0

Y32

PCIE_GTX_CRX_P1

W33

PCIE_GTX_CRX_N1

W32

PCIE_GTX_CRX_P2

U33

PCIE_GTX_CRX_N2

U32

PCIE_GTX_CRX_P3

U30

PCIE_GTX_CRX_N3

U29

PCIE_GTX_CRX_P4

T33

PCIE_GTX_CRX_N4

T32

PCIE_GTX_CRX_P5

T30

PCIE_GTX_CRX_N5

T29

PCIE_GTX_CRX_P6

P33

PCIE_GTX_CRX_N6

P32

PCIE_GTX_CRX_P7

P30

PCIE_GTX_CRX_N7

P29

PCIE_GTX_CRX_P8

N33

PCIE_GTX_CRX_N8

N32

PCIE_GTX_CRX_P9

N30

PCIE_GTX_CRX_N9

N29

PCIE_GTX_CRX_P10

L33

PCIE_GTX_CRX_N10

L32

PCIE_GTX_CRX_P11

L30

PCIE_GTX_CRX_N11

L29

PCIE_GTX_CRX_P12

K33

PCIE_GTX_CRX_N12

K32

PCIE_GTX_CRX_P13

J33

PCIE_GTX_CRX_N13

J32

PCIE_GTX_CRX_P14

K30

PCIE_GTX_CRX_N14

K29

PCIE_GTX_CRX_P15

H33

PCIE_GTX_CRX_N15

H32

Chelsea Only

CH@

1 2

RV198 1.69K_0402_1%

Y30 Y29

1 2 1 2

RV631.27K_0402_1% TH@ RV631.27K_0402_1% TH@ RV652K_0402_1% TH@ RV652K_0402_1% TH@

Install 2K for Thames/Seymour

RV65

RV65 1K_0402_1%

1K_0402_1% CH@

CH@

PCIE_GTX_C_CRX_P[0..15] <5> PCIE_GTX_C_CRX_N[0..15] <5>

Close to UV1

CV730.1U_0402_16V7K CV730.1U_0402_16V7K

12

CV740.1U_0402_16V7K CV740.1U_0402_16V7K

12

CV710.1U_0402_16V7K CV710.1U_0402_16V7K

12

CV720.1U_0402_16V7K CV720.1U_0402_16V7K

12

CV690.1U_0402_16V7K CV690.1U_0402_16V7K

12

CV700.1U_0402_16V7K CV700.1U_0402_16V7K

12

CV670.1U_0402_16V7K CV670.1U_0402_16V7K

12

CV680.1U_0402_16V7K CV680.1U_0402_16V7K

12

CV650.1U_0402_16V7K CV650.1U_0402_16V7K

12

CV660.1U_0402_16V7K CV660.1U_0402_16V7K

12

CV630.1U_0402_16V7K CV630.1U_0402_16V7K

12

CV640.1U_0402_16V7K CV640.1U_0402_16V7K

12

CV610.1U_0402_16V7K CV610.1U_0402_16V7K

12

CV620.1U_0402_16V7K CV620.1U_0402_16V7K

12

CV590.1U_0402_16V7K CV590.1U_0402_16V7K

12

CV600.1U_0402_16V7K CV600.1U_0402_16V7K

12

CV570.1U_0402_16V7K CV570.1U_0402_16V7K

12

CV580.1U_0402_16V7K CV580.1U_0402_16V7K

12

CV550.1U_0402_16V7K CV550.1U_0402_16V7K

12

CV560.1U_0402_16V7K CV560.1U_0402_16V7K

12

CV530.1U_0402_16V7K CV530.1U_0402_16V7K

12

CV540.1U_0402_16V7K CV540.1U_0402_16V7K

12

CV510.1U_0402_16V7K CV510.1U_0402_16V7K

12

CV520.1U_0402_16V7K CV520.1U_0402_16V7K

12

CV490.1U_0402_16V7K CV490.1U_0402_16V7K

12

CV500.1U_0402_16V7K CV500.1U_0402_16V7K

12

CV470.1U_0402_16V7K CV470.1U_0402_16V7K

12

CV480.1U_0402_16V7K CV480.1U_0402_16V7K

12

CV450.1U_0402_16V7K CV450.1U_0402_16V7K

12

CV460.1U_0402_16V7K CV460.1U_0402_16V7K

12

CV430.1U_0402_16V7K CV430.1U_0402_16V7K

12

CV440.1U_0402_16V7K CV440.1U_0402_16V7K

12

+1.0VGS

Thames Only

+1.0VGS

PCIE_GTX_C_CRX_P0 PCIE_GTX_C_CRX_N0

PCIE_GTX_C_CRX_P1 PCIE_GTX_C_CRX_N1

PCIE_GTX_C_CRX_P2 PCIE_GTX_C_CRX_N2

PCIE_GTX_C_CRX_P3 PCIE_GTX_C_CRX_N3

PCIE_GTX_C_CRX_P4 PCIE_GTX_C_CRX_N4

PCIE_GTX_C_CRX_P5 PCIE_GTX_C_CRX_N5

PCIE_GTX_C_CRX_P6 PCIE_GTX_C_CRX_N6

PCIE_GTX_C_CRX_P7 PCIE_GTX_C_CRX_N7

PCIE_GTX_C_CRX_P8 PCIE_GTX_C_CRX_N8

PCIE_GTX_C_CRX_P9 PCIE_GTX_C_CRX_N9

PCIE_GTX_C_CRX_P10 PCIE_GTX_C_CRX_N10

PCIE_GTX_C_CRX_P11 PCIE_GTX_C_CRX_N11

PCIE_GTX_C_CRX_P12 PCIE_GTX_C_CRX_N12

PCIE_GTX_C_CRX_P13 PCIE_GTX_C_CRX_N13

PCIE_GTX_C_CRX_P14 PCIE_GTX_C_CRX_N14

PCIE_GTX_C_CRX_P15 PCIE_GTX_C_CRX_N15

LVDS Interface

UV1G

LVDS CONTROL

TXCLK_UN_DPF3N

TXOUT_U0P_DPF2P

TXOUT_U0N_DPF2N

TXOUT_U1P_DPF1P

TXOUT_U1N_DPF1N

TXOUT_U2P_DPF0P

TXOUT_U2N_DPF0N

LVTMDP

TXOUT_L0P_DPE2P TXOUT_L0N_DPE2N

TXOUT_L1P_DPE1P TXOUT_L1N_DPE1N

TXOUT_L2P_DPE0P TXOUT_L2N_DPE0N

THAMES XT M2 TH@

TXCLK_UP_DPF3P

TXOUT_U3N

TXCLK_LP_DPE3P TXCLK_LN_DPE3N

VARY_BL

DIGON

TXOUT_U3P

TXOUT_L3P TXOUT_L3N

AK27 AJ27

AK35 AL36

AJ38 AK37

AH35 AJ36

AG38 AH37

AF35 AG36

AP34 AR34

AW37 AU35

AR37 AU39

AP35 AR35

AN36 AP37

4 4

A

B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2011/11/28 2013/12/31

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC,MB LA-8863

4019IT

12 51Friday, March 23, 2012

E

of

A

1 1

VRAM_ID0<20> VRAM_ID1<20> VRAM_ID2<20>

DV1

@ DV1

2 2

3 3

4 4

STRAPS

+3VGS

+1.8VGS

LV14

BLM15BD121SN1D_0402

LV14

LV14 0_0402_5%

0_0402_5% CH@

CH@

+1.0VGS

LV15

BLM15BD121SN1D_0402

LV15

LV15 0_0402_5%

0_0402_5% CH@

CH@

NOGCLK@ CV94

NOGCLK@

18P_0402_50V8J

1 2 1 2 1 2

1 2

1 2 1 2

1 2 1 2 1 2

1 2

1 2 1 2 1 2

1 2

(Thames 75mA)

TH@LV14

TH@

12

1

CV82

2

1U_0402_6.3V6K

10U_0603_6.3V6M

TH@LV15

TH@

(Thames 125mA)

12

1

CV86

2

1U_0402_6.3V6K

10U_0603_6.3V6M

RV97

1M_0402_5%

YV1

NOGCLK@YV1

NOGCLK@

2 1

27MHZ_16PF_X5H027000FG1H

CV94

CLOSE TO YV1

VGA_X1<31>

RV8510K_0402_5% @ RV8510K_0402_5% @ RV8610K_0402_5% @ RV8610K_0402_5% @ RV8710K_0402_5% @ RV8710K_0402_5% @

RV8810K_0402_5% @ RV8810K_0402_5% @

1

CV83

2

0.1U_0402_16V7K

1

CV87

2

0.1U_0402_16V7K

NOGCLK@

XTALINXTALOUT

CV95

18P_0402_50V8J

RV7510K_0402_5% RV7510K_0402_5% RV7610K_0402_5% RV7610K_0402_5% RV7710K_0402_5% @ RV7710K_0402_5% @

RV78100K_0402_5% @ RV78100K_0402_5% @

RV7910K_0402_5% @ RV7910K_0402_5% @ RV8010K_0402_5% @ RV8010K_0402_5% @

RV8110K_0402_5% RV8110K_0402_5% RV8210K_0402_5% @ RV8210K_0402_5% @ RV8310K_0402_5% @ RV8310K_0402_5% @

RV9610K_0402_5% @ RV9610K_0402_5% @

+DPLL_PVDD

1

CV84

2

+DPLL_VDDC

1

CV88

2

NOGCLK@CV95

NOGCLK@

R802 place near YV1

A

@

RB751V40_SC76-2

ACIN<36,41>

GPU_GPIO0 GPU_GPIO1 GPU_GPIO2

AC_BATT

GPU_GPIO8 GPU_GPIO9

GPU_GPIO11 GPU_GPIO12 GPU_GPIO13

PEG_CLKREQ#

GPIO24_TRSTB

GPIO25_TDI GPIO27_TMS

GPIO26_TCK

21

GPU_VID1<49>

GPU_VID3<49> GPU_VID2<49>

GPU_VID4<49>

+1.8VGS

(Thames 5mA)

1 2

+1.8VGS

BLM15BD121SN1D_0402

R802

1 2

0_0402_5%

0_0402_5% GCLK@

GCLK@

BLM15BD121SN1D_0402

XTALIN

SM010009U00 300mA 120ohm@100mhz DCR 0.3

VDDCI_VID<45>

1 2

RV13 0_0402_5%

1 2

RV14 0_0402_5%

RV89 10K_0402_5%CH@RV89 10K_0402_5%CH@

PEG_CLKREQ#<26>

RV93 499_0402_1%RV93 499_0402_1%

12

RV95 249_0402_1%RV95 249_0402_1%

12

CV81 0.1U_0402_16V7KCV81 0.1U_0402_16V7K

XTALIN Voltage Swing: 1.8 V

TS_FDO<20>

LV16

VRAM_ID0 VRAM_ID1 VRAM_ID2

GPU_GPIO0 GPU_GPIO1

GPU_GPIO2 VGA_SMB_DA2_R VGA_SMB_CK2_R

AC_BATT

VDDCI_VID

GPU_GPIO8

GPU_GPIO9

GPU_GPIO10

GPU_GPIO11

T772T772

GPU_GPIO12

CH@

GPU_GPIO13

GPU_VID3

GPIO_16

CH@

THM_ALERT#

1 2

GPU_VID4

GPIO21_BBEN

GPIO22_ROMCSB

T781T781

PEG_CLKREQ#

T782T782

GPIO24_TRSTB

GPIO25_TDI

GPIO26_TCK

GPIO27_TMS

GPIO28_TDO

T791T791

0.60 V level, Please VREFG Divider ans cap close to ASIC

RV11

1 2 1 2

RV12 0_0402_5%

GPU_THERMAL_D+ GPU_THERMAL_D-

TS_FDO

(1.8V@20mA TSVDD)

+TSVDD

1

CV91

CV92

2

10U_0603_6.3V6M

B

R02

15mil

+VREFG_GPU

10mil

+DPLL_PVDD

10mil

+DPLL_VDDC

XTALIN XTALOUT

@RV11

@

0_0402_5%

@

1

CV93

2

1U_0402_6.3V6K

B

AW8

AW3 AW5

AW6

AR10

AW10

AU10 AP10 AV11 AT11 AR12

AW12

AU12 AP12

AJ21 AK21

AK26 AJ26

AH20 AH18 AN16 AH23 AJ23 AH17 AJ17 AK17 AJ13 AH15 AJ16 AK16 AL16 AM16 AM14 AM13 AK14 AG30 AN14 AM17 AL13 AJ14 AK13 AN13 AM23 AN23 AK23 AL24 AM24 AJ19 AK19 AJ20 AK20 AJ24 AH26 AH24

AK24

AH13

AM32 AN32

AN31

AV33 AU34

AW34 AW35

AF29 AG29

AK32 AL31

10mil

AJ32 AJ33

0.1U_0402_16V4Z

UV1B

MUTI GFX

AR8

DVPCNTL_MVP_0

AU8

DVPCNTL_MVP_1

AP8

DVPCNTL_0 DVPCNTL_1

AR3

DVPCNTL_2

AR1

DVPCLK

AU1

DVPDATA_0

AU3

DVPDATA_1 DVPDATA_2

AP6

DVPDATA_3 DVPDATA_4

AU5

DVPDATA_5

AR6

DVPDATA_6 DVPDATA_7

AU6

DVPDATA_8

AT7

DVPDATA_9

AV7

DVPDATA_10

AN7

DVPDATA_11

AV9

DVPDATA_12

AT9

DVPDATA_13 DVPDATA_14 DVPDATA_15 DVPDATA_16 DVPDATA_17 DVPDATA_18 DVPDATA_19 DVPDATA_20 DVPDATA_21 DVPDATA_22 DVPDATA_23

SWAPLOCKA SWAPLOCKB

I2C

SCL SDA

GENERAL PURPOSE I/O

GPIO_0 GPIO_1 GPIO_2 GPIO_3_SMBDATA GPIO_4_SMBCLK GPIO_5_AC_BATT GPIO_6 GPIO_7_BLON GPIO_8_ROMSO GPIO_9_ROMSI GPIO_10_ROMSCK GPIO_11 GPIO_12 GPIO_13 GPIO_14_HPD2 GPIO_15_PWRCNTL_0 GPIO_16 GPIO_17_THERMAL_INT GPIO_18_HPD3 GPIO_19_CTF GPIO_20_PWRCNTL_1 GPIO_21_BB_EN GPIO_22_ROMCSB GPIO_23_CLKREQB JTAG_TRSTB JTAG_TDI JTAG_TCK JTAG_TMS JTAG_TDO GENERICA GENERICB GENERICC GENERICD GENERICE_HPD4 GENERICF_HPD5 GENERICG_HPD6

HPD1

VREFG

DPLL_PVDD DPLL_PVSS

DPLL_VDDC

XTALIN XTALOUT

XO_IN XO_IN2

DPLUS DMINUS

TS_FDO TS_A/NC

TSVDD TSVSS

THAMES XT M2 THR3@

PLL/CLOCK

THERMAL

TXCAP_DPA3P

TXCAM_DPA3N

TX0P_DPA2P

TX0M_DPA2N

DPA

TX1P_DPA1P

TX1M_DPA1N

TX2P_DPA0P

TX2M_DPA0N

TXCBP_DPB3P

TXCBM_DPB3N

TX3P_DPB2P

TX3M_DPB2N

DPB

TX4P_DPB1P

TX4M_DPB1N

TX5P_DPB0P

TX5M_DPB0N

TXCCP_DPC3P TXCCM_DPC3N

TX0P_DPC2P

TX0M_DPC2N

DPC

TX1P_DPC1P

TX1M_DPC1N

TX2P_DPC0P

TX2M_DPC0N

TXCDP_DPD3P TXCDM_DPD3N

TX3P_DPD2P

TX3M_DPD2N

DPD

TX4P_DPD1P

TX4M_DPD1N

TX5P_DPD0P

TX5M_DPD0N

DAC1

HSYNC VSYNC

RSET AVDD

AVSSQ VDD1DI

VSS1DI

R2/NC

R2B/NC

G2/NC

G2B/NC

B2/NC

B2B/NC

COMP/NC

DAC2

H2SYNC/GENLK_CLK

V2SYNC/GENLK_VSYNC

VDD2DI/NC

VSS2DI/NC

A2VDD/NC

A2VDDQ/NC

A2VSSQ/TSVSSQ

R2SET/NC

DDC/AUX

DDC1CLK

DDC1DATA

AUX1P AUX1N

DDC2CLK

DDC2DATA

AUX2P AUX2N

DDCCLK_AUX3P

DDCDATA_AUX3N

DDCCLK_AUX4P

DDCDATA_AUX4N

DDCCLK_AUX5P

DDCDATA_AUX5N

DDC6CLK

DDC6DATA

DDCCLK_AUX7P

DDCDATA_AUX7N

AU24 AV23

AT25 AR24

AU26 AV25

AT27 AR26

AR30 AT29

AV31 AU30

AR32 AT31

AT33 AU32

AU14 AV13

AT15 AR14

AU16 AV15

AT17 AR16

AU20 AT19

AT21 AR20

AU22 AV21

AT23 AR22

AD39

R

AD37

RB

AE36

G

AD35

GB

AF37

B

AE38

BB

AC36 AC38

AB34 AD34

AE34 AC33

AC34

AC30 AC31

AD30 AD31

AF30 AF31

AC32

C/NC

AD32

Y/NC

AF32

AD29 AC29

AG31 AG32

AG33 AD33 AF33

AA29

AM26 AN26

AM27 AL27

AM19 AL19

AN20 AM20

AL30 AM30

AL29 AM29

AN21 AM21

AJ30 AJ31

AK30 AK29

RV9 RV10 0_0402_5%

RV10 0_0402_5%

C

VGA_CRT_R <23>

VGA_CRT_G <23>

VGA_CRT_B <23>

VGA_CRT_HSYNC <23>

RV84 499_0402_1%RV84 499_0402_1%

VGA_CRT_VSYNC <23>

1 2

10mil

+AVDDGPU

(1.8V@65mA AVDD)

10mil

+VDD1DI

PS_1 <20>

+DPLL_PVDD

@RV9

@

1 2

@

0_0402_5%

1 2

GENLK_CLK GENLK_VSYNC

PS_2 <20>

PS_3 <20>

TH@

1 2

RV200 0_0402_5%

NC_TSVSSQ should be tied to GND on Thames

Not Share via for other GND

Reserved test pad of CRT Signals for debug

100mA

1

CV79

2

1U_0402_6.3V6K

1 2

LV13

BLM15BD121SN1D_0402

1

CV80

2

10U_0603_6.3V6M

(1.8V@100mA VDD1DI)

1

CV78

2

0.1U_0402_16V7K

GENLK_CLK <20> GENLK_VSYNC <20>

Reserved test pad of CRT Signals for debug

VGA_CRT_CLK VGA_CRT_DATA

VGA_CRT_VSYNC VGA_CRT_HSYNC VGA_CRT_CLK VGA_CRT_DATA

VGA_CRT_R VGA_CRT_G VGA_CRT_B

VGA_CRT_CLK <23> VGA_CRT_DATA <23>

T792T792 T793T793

for debug CRT

RV216 10K_0402_5%@RV216 10K_0402_5%@

1 2

RV217 10K_0402_5%@RV217 10K_0402_5%@

1 2

RV218 10K_0402_5%@RV218 10K_0402_5%@

1 2

RV219 10K_0402_5%@RV219 10K_0402_5%@

1 2

RV220 150_0402_1%@RV220 150_0402_1%@

1 2

RV221 150_0402_1%@RV221 150_0402_1%@

1 2

RV222 150_0402_1%@RV222 150_0402_1%@

1 2

C

CRT

+3VGS

D

TX_PWRS_ENB GPIO0

65mA

1

+1.8VGS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

CV76

CV75

2

1U_0402_6.3V6K

0.1U_0402_16V7K

2011/11/28 2013/12/31

+1.8VGS

1 2

LV12

LV12 BLM15BD121SN1D_0402

BLM15BD121SN1D_0402

1

CV77

2

10U_0603_6.3V6M

RV90

10K_0402_5%

VGA_SMB_CK2_R

VGA_SMB_DA2_R

VGA Thermal Sensor ADM1032ARMZ

VGA_SMB_CK2

TH@

1 2

RV15 0_0402_5%

VGA_SMB_DA2

TH@

1 2

RV16 0_0402_5%

Closed to GPU

0.1U_0402_16V7K

GPU_THERMAL_D+ VGA_SMB_DA2

GPU_THERMAL_D-

Compal Secret Data

D

CV89

1 2

2200P_0402_50V7K

CH@

1 2

RV106 4.7K_0402_5%

Deciphered Date

+3VGS

Reserve External Thermal Sensor for AMD FAE strong suggest

GPIO1TX_DEEMPH_EN

+3VGS

Internal VGA Thermal Sensor

12

RV91

RV91 10K_0402_5%

10K_0402_5%

2N7002KDWH_SOT363-6

+3VGS

2

CV85

1

CH@

CH@CV89

CH@

E

Transmitter Power Saving Enable 0: 50% Tx output swing for mobile mode 1: full Tx output swing (Default setting for Desktop)

PCI Express Transmitter De-emphasis Enable 0: Tx de-emphasis diabled for mobile mode 1: Tx de-emphasis enabled (Defailt setting for desktop)

+3VGS

2

61

5

QV15A

QV15B

UV14

1

VDD

SCLK

2

D+

SDATA

3

ALERT#

DTHERM#4GND

ADM1032ARMZ-2REEL_MSOP8

CH@

Address:100_1101

Title

Size Document Number Rev

Custom

Date: Sheet

EC_SMB_CK2 <9,36>

34

EC_SMB_DA2 <9,36>

+3VGS

RV98

CH@RV98

CH@

4.7K_0402_5%

1 2

VGA_SMB_CK2

8 7

THM_ALERT#

6 5

Compal Electronics, Inc.

SCHEMATIC,MB LA-8863

4019IT

E

A

13 51Friday, March 23, 2012

A

of

A

B

C

D

E

1 1

@

1 2

RV102 0_0402_5%

for PX5.0

2 2

3 3

4 4

PX_MODEPXS_PWREN

PX_MODE <45,49>PXS_PWREN<25,26,44,49>

PX_MODE=1 for Normal Operation PX_MODE=0 to shut down VDDR3, PCIE_VDDC, 1.5VGS and 1.8VGS power rails

+5VALW

R424

R424 100K_0402_5%

100K_0402_5%

+BIF_VDDC +VGA_CORE

1 2

RV204 0_0805_5%

RV204 0_0805_5% TH@

TH@

1 2

RV205 0_0805_5%

RV205 0_0805_5% CH@

CH@

1

CV97

CV97 22U_0805_6.3V6MPX4@

22U_0805_6.3V6MPX4@

2

+1.0VGS

Only stuff at PX5.0 and Thames XT,

+1.5V

Q43

Q43 8 7 6 5

FDS6676AS_SO8

1

C473

2

4.7U_0805_10V4Z

+1.5VGS

+1.5V to +1.5VGS

PX_MODE#

Vgs=10V,Id=14.5A,Rds=6mohm

1

C478

1

S

D

2

S

D

S

D

G

D

C481

3 4

1

2

1U_0402_6.3V6K

12

0.1U_0402_25V6

R430

R430 820K_0402_5%

820K_0402_5%

2N7002DW-T/R7_SOT363-6

1

C475

4.7U_0805_10V4Z

2

R431

1 2

220K_0402_5%

61

Q13A

2

+VSB

PX_MODE#

R429

470_0805_5%

1 2 3

Q13B

Q13B 2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

5

4

PX_MODE

2N7002DW-T/R7_SOT363-6

+1.0VGS

R475

R475 470_0805_5%

470_0805_5%

1 2 3

Q188B

2N7002DW-T/R7_SOT363-6

5

4

2

PXS_PWREN#

1 2 61

Q188A

un-stuff on PX4.0

+3VS to +3VGS

+3VALW

R433

R433 100K_0402_5%

100K_0402_5%

1 2

R426

1 2 47K_0402_5%

47K_0402_5%

61

2

C491

0.1U_0402_16V7K

1

AO3413_SOT23

2

C492

0.01U_0402_25V7K

1

4.7U_0805_10V4Z

+3VS

Vgs=-4.5V,Id=3A,Rds<97mohm

12

S

R104

R104 0_0805_5%

0_0805_5% @

@

D

1 3

1

C684

1

1U_0402_6.3V6K

2

C683

Q54

G

2

@

+3VGS

R458

470_0805_5%

Q206B

2N7002DW-T/R7_SOT363-6

Q206B

+3VGS

1 2 3

4

PXS_PWREN

PXS_PWREN#

5

Q206A

2N7002DW-T/R7_SOT363-6

A

B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2011/11/28 2013/12/31

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC,MB LA-8863

4019IT

E

of

14 51Friday, March 23, 2012

A

+1.5VGS

1 1

330U_D2_2V_Y

CV401

1

+

2

(Thames 1.7)A

CV420

1U_0402_6.3V6K

CV420

1U_0402_6.3V6K

CV406

1U_0402_6.3V6K

CV406

1U_0402_6.3V6K

1

2

CV367

1U_0402_6.3V6K

CV367

1U_0402_6.3V6K

1

2

For DDR3, MVDDQ = 1.5V

1U_0402_6.3V6K

CV409

1U_0402_6.3V6K

CV409

1U_0402_6.3V6K

CV413

1U_0402_6.3V6K

CV413

1U_0402_6.3V6K

1

2

CV412

1

2

CV410

1U_0402_6.3V6K

CV410

1U_0402_6.3V6K

CV368

1U_0402_6.3V6K

CV368

1U_0402_6.3V6K

CV417

1U_0402_6.3V6K

CV417

1U_0402_6.3V6K

1

2

+1.5VGS

@

CV402

330U_D2_2V_Y

2 2

3 3

4 4

SM010009U00 300mA 120ohm@100mhz DCR 0.3

+3VGS

(Thames 50mA)

+1.8VGS

BLM18AG121SN1D_2P

SM010009U00 300mA 120ohm@100mhz DCR 0.3

SM01000BL00 1000mA 470ohm@100mhz DCR 0.2

BLM18AG121SN1D_2P

+1.0VGS

(Thames 100mA)

MCK1608471YZF 0603

2

1

+

2

+1.8VGS

(Thames 250mA)

LV19

1 2

BLM18AG121SN1D_2P

(Thames 60mA)

1

CV188

CV187

CV189

CV190

2

1U_0402_6.3V6K

10U_0603_6.3V6M

1 2

LV23

1 2

1U_0402_6.3V6K

SM010009U00 300mA 120ohm@100mhz DCR 0.3

SM01000BL00 1000mA 470ohm@100mhz DCR 0.2

+1.8VGS

LV22

(1.8V@75mA SPV18)

CV200

10U_0603_6.3V6M

(120mA SPV10)

1

CV215

2

10U_0603_6.3V6M

(Thames 150mA)

(M97, Broadway and Madison: 1.8V@150mA MPV18)

MCK1608471YZF 0603

1

2

1U_0402_6.3V6K

VSSSENSE_VGA<49>

A

10U_0603_6.3V6M

CV421

10U_0603_6.3V6M

CV421

10U_0603_6.3V6M

1

2

(1.8V@110mA VDD_CT)

1

CV170

2

1U_0402_6.3V6K

10U_0603_6.3V6M

+1.8VGS

1 2

BLM18AG121SN1D_2P

LV21

1 2

1

CV201

CV202

2

1U_0402_6.3V6K

0.1U_0402_16V7K

1

CV217

CV216

2

0.1U_0402_16V7K

VCCSENSE_VGA<49>

VDDCI_SEN<45>

CV418

LV20

1

CV171

2

1

2

CV377

10U_0603_6.3V6M

CV377

10U_0603_6.3V6M

1

CV172

2

1U_0402_6.3V6K

10_0402_5%

CV375

10U_0603_6.3V6M

CV375

10U_0603_6.3V6M

CV376

10U_0603_6.3V6M

CV376

10U_0603_6.3V6M

1

2

+VDDC_CT

1

CV173

CV174

2

1U_0402_6.3V6K

0.1U_0402_16V7K

1

CV194

CV193

2

1U_0402_6.3V6K

0.1U_0402_16V7K

1

CV198

CV197

2

1U_0402_6.3V6K

10U_0603_6.3V6M

20mil

+MPV18

0.1U_0402_16V7K

(1.8V@300mA VDDR4)

10mil 20mil

+VGA_CORE

+VDDCI

12

RV215

CV369

1U_0402_6.3V6K

CV369

1U_0402_6.3V6K

1

2

CV419

10U_0603_6.3V6M

CV419

10U_0603_6.3V6M

1

2

20mil

10mil

+VDDR4

1

CV199

2

20mil

+SPV18 +SPV10

12

RV22

RV22 10_0402_5%

10_0402_5%

10mil

VDDCI_SEN

12

RV23

10_0402_5%

B

AC7

AD11 AG10

AK8 G11

G14 G17 G20 G23 G26 G29

M11

AF26 AF27 AG26 AG27

AF23 AF24 AG23 AG24

AF13 AF15 AG13 AG15

AD12 AF11 AF12 AG11

M20 M21

AM10

AN9

AN10

AF28

AG28

AH29

B

AF7 AJ7 AL9

H10

J7

J9 K11 K13

K8 L12 L16 L21 L23 L26

L7 N11

P7 R11 U11

U7 Y11

Y7

V12 U12

H7

H8

UV1E

MEM I/O

VDDR1#1 VDDR1#2 VDDR1#3 VDDR1#4 VDDR1#5 VDDR1#6 VDDR1#7 VDDR1#8 VDDR1#9 VDDR1#10 VDDR1#11 VDDR1#12 VDDR1#13 VDDR1#14 VDDR1#15 VDDR1#16 VDDR1#17 VDDR1#18 VDDR1#19 VDDR1#20 VDDR1#21 VDDR1#22 VDDR1#23 VDDR1#24 VDDR1#25 VDDR1#26 VDDR1#27 VDDR1#28 VDDR1#29 VDDR1#30 VDDR1#31 VDDR1#32 VDDR1#33 VDDR1#34

LEVEL

LEVEL TRANSLATION

TRANSLATION

VDD_CT#1 VDD_CT#2 VDD_CT#3 VDD_CT#4

I/O

VDDR3#1 VDDR3#2 VDDR3#3 VDDR3#4

VDDR4#4 VDDR4#5 VDDR4#7 VDDR4#8

VDDR4#1 VDDR4#2 VDDR4#3 VDDR4#6

NC_VDDRHA NC_VSSRHA

NC_VDDRHB NC_VSSRHB

PLL

MPV18#1 MPV18#2

SPV18 SPV10 SPVSS

VOLTAGE

VOLTAGE SENESE

SENESE

FB_VDDC

FB_VDDCI

FB_GND

THAMES XT M2

THAMES XT M2 THR3@

THR3@

PCIE

PCIE_VDDR#1 PCIE_VDDR#2 PCIE_VDDR#3 PCIE_VDDR#4 PCIE_VDDR#5 PCIE_VDDR#6 PCIE_VDDR#7 PCIE_VDDR#8

PCIE_VDDR/PCIE_PVDD

PCIE_VDDC#1 PCIE_VDDC#2 PCIE_VDDC#3 PCIE_VDDC#4 PCIE_VDDC#5 PCIE_VDDC#6 PCIE_VDDC#7 PCIE_VDDC#8

PCIE_VDDC#9 PCIE_VDDC#10 PCIE_VDDC#11 PCIE_VDDC#12

VDDC#1

CORE

VDDC#2 VDDC#3 VDDC#4 VDDC#5 VDDC#6 VDDC#7 VDDC#8

VDDC#9 VDDC#10 VDDC#11 VDDC#12 VDDC#13 VDDC#14 VDDC#15

POWER

VDDC#16 VDDC#17 VDDC#18 VDDC#19 VDDC#20 VDDC#21 VDDC#22 VDDC#23 VDDC#24 VDDC#25 VDDC#26 VDDC#27 VDDC#28 VDDC#29 VDDC#30 VDDC#31 VDDC#32

VDDC/BIF_VDDC#33

VDDC#34 VDDC#35 VDDC#36 VDDC#37 VDDC#38 VDDC#39 VDDC#40 VDDC#41

VDDC/BIF_VDDC#42

VDDC#43 VDDC#44 VDDC#45 VDDC#46 VDDC#47 VDDC#48 VDDC#49 VDDC#50 VDDC#51 VDDC#52 VDDC#53 VDDC#54 VDDC#55 VDDC#56 VDDC#57 VDDC#58

VDDCI#1 VDDCI#2 VDDCI#3 VDDCI#4 VDDCI#5 VDDCI#6 VDDCI#7 VDDCI#8

VDDCI#9 VDDCI#10 VDDCI#11 VDDCI#12 VDDCI#13 VDDCI#14 VDDCI#15

ISOLATED

VDDCI#16

CORE I/O

VDDCI#17 VDDCI#18 VDDCI#19 VDDCI#20 VDDCI#21 VDDCI#22

+PCIE_VDDR

0.1U_0402_16V7K

40mil

AA31 AA32 AA33 AA34 V28 W29 W30 Y31 AB37

G30 G31 H29 H30 J29 J30 L28 M28 N28 R28 T28 U28

AA15 AA17 AA20 AA22 AA24 AA27 AB16 AB18 AB21 AB23 AB26 AB28 AC17 AC20 AC22 AC24 AC27 AD18 AD21 AD23 AD26 AF17 AF20 AF22 AG16 AG18 AG21 AH22 AH27 AH28 M26 N24 N27 R18 R21 R23 R26 T17 T20 T22 T24 T27 U16 U18 U21 U23 U26 V17 V20 V22 V24 V27 Y16 Y18 Y21 Y23 Y26 Y28

AA13 AB13 AC12 AC15 AD13 AD16 M15 M16 M18 M23 N13 N15 N17 N20 N22 R12 R13 R16 T12 T15 V15 Y13

0.1U_0402_16V7K

+PCIE_PVDD

(Thames 20.5A)

10U_0603_6.3V6M

55mA

1

CV195

2

1U_0402_6.3V6K

(GDDR3/DDR3 1.12V@4A VDDCI)

4A

C

(1.8V@504mA PCIE_VDDR)

1

CV126

2

1

CV191

2

+BIF_VDDC

1U_0402_6.3V6K

(Thames 440mA)

1

CV128

CV127

CV129

CV130

2

1U_0402_6.3V6K

0.1U_0402_16V7K

1

2

1

CV196

2

1U_0402_6.3V6K

(Thames 1.1A)

(1.0V@1920mA PCIE_VDDC)

1

CV146

CV147

CV148

2

1U_0402_6.3V6K

+VGA_CORE

CV192

22U_0805_6.3V6M

For non-BACO designs, connect BIF_VDDC to VDDC. For BACO designs - see BACO reference schematics

LV17

FBMA-L11-201209-221LMA30T_0805

1

CV131

2

10U_0603_6.3V6M

(1.8V@40mA PCIE_PVDD)

+1.0VGS

1

CV150

CV149

2

1U_0402_6.3V6K

10U_0603_6.3V6M

+VDDCI

1

CV132

2

0.1U_0402_16V7K

1

CV151

2

+1.8VGS

12

1

CV133

2

1U_0402_6.3V6K

1

CV134

2

10U_0603_6.3V6M

D

40mA

LV18

MBK1608121YZF_0603

12

+1.8VGS

VDDCI and VDDC should have seperate regulators with a merge option on PCB For Madison, Park, Capilano, Robson, Seymour and Whistler, VDDCI and VDDC

can share one common regulator

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2011/11/28 2013/12/31

Compal Secret Data

Deciphered Date

D

E

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC,MB LA-8863

4019IT

E

15 51Friday, March 23, 2012

of

A

UV1F

A

B

C

D

E

AB39

PCIE_VSS#1

E39

PCIE_VSS#2

F34

PCIE_VSS#3

F39

PCIE_VSS#4

G33 G34 H31 H34 H39

J31

W31 W34

J34 K31 K34 K39

L31

L34 M34 M39 N31 N34 P31 P34 P39 R34 T31 T34 T39 U31 U34 V34 V39

Y34 Y39

F15 F17 F19 F21 F23 F25 F27 F29 F31 F33

F7 F9 G2 G6 H9

J27

K14

K7 L11 L17

L22 L24

M17 M22 M24 N16 N18

N2

N21 N23 N26

N6

R15 R17

R2

R20 R22 R24 R27

R6

T11 T13 T16 T18 T21 T23 T26 U15 U17

U2

U20 U22 U24 U27

U6

V11 V16 V18 V21 V23 V26

W2 W6

Y15 Y17 Y20 Y22 Y24 Y27 U13 V13

1 1

2 2

3 3

4 4

PCIE_VSS#5 PCIE_VSS#6 PCIE_VSS#7 PCIE_VSS#8 PCIE_VSS#9 PCIE_VSS#10 PCIE_VSS#11 PCIE_VSS#12 PCIE_VSS#13 PCIE_VSS#14 PCIE_VSS#15 PCIE_VSS#16 PCIE_VSS#17 PCIE_VSS#18 PCIE_VSS#19 PCIE_VSS#20 PCIE_VSS#21 PCIE_VSS#22 PCIE_VSS#23 PCIE_VSS#24 PCIE_VSS#25 PCIE_VSS#26 PCIE_VSS#27 PCIE_VSS#28 PCIE_VSS#29 PCIE_VSS#30 PCIE_VSS#31 PCIE_VSS#32 PCIE_VSS#33 PCIE_VSS#34 PCIE_VSS#35

GND#100 GND#101 GND#102 GND#103 GND#104 GND#105 GND#106 GND#107 GND#108 GND#109 GND#110 GND#111 GND#112 GND#113 GND#114

J2

GND#115 GND#116

J6

GND#117

J8

GND#118 GND#119 GND#120 GND#121 GND#122

L2

GND#123 GND#124 GND#125

L6

GND#126 GND#127 GND#128 GND#129 GND#130 GND#131 GND#132 GND#133 GND#134 GND#135 GND#136 GND#137 GND#138 GND#139 GND#140 GND#141 GND#142 GND#143 GND#144 GND#145 GND#146 GND#147 GND#148 GND#149 GND#150 GND#151 GND#153 GND#154 GND#155 GND#156 GND#157 GND#158 GND#159 GND#160 GND#161 GND#163 GND#164 GND#165 GND#166 GND#167 GND#168 GND#169 GND#170 GND#171 GND#172 GND#173 GND#174 GND#175 GND#152 GND#162

THAMES XT M2

THAMES XT M2 THR3@

THR3@

GND

A

GND/PX_EN#61

VSS_MECH#1 VSS_MECH#2 VSS_MECH#3

GND#1 GND#2 GND#3 GND#4 GND#5 GND#6 GND#7 GND#8

GND#9 GND#10 GND#11 GND#12 GND#13 GND#14 GND#15 GND#16 GND#17 GND#18 GND#19 GND#20 GND#21 GND#22 GND#23 GND#24 GND#25 GND#26 GND#27 GND#28 GND#29 GND#30 GND#31 GND#32 GND#33 GND#34 GND#35 GND#36 GND#37 GND#38 GND#39 GND#40 GND#41 GND#42 GND#43 GND#44 GND#45 GND#46 GND#47 GND#48 GND#49 GND#50 GND#51 GND#52 GND#53 GND#54 GND#55 GND#56 GND#57 GND#58 GND#59 GND#60

GND#62 GND#63 GND#64 GND#65 GND#66 GND#67 GND#68 GND#69 GND#70 GND#71 GND#72 GND#73 GND#74 GND#75 GND#76 GND#77 GND#78 GND#79 GND#80 GND#81 GND#82 GND#83 GND#84 GND#85 GND#86 GND#87 GND#88 GND#89 GND#90 GND#91 GND#92 GND#93 GND#94 GND#95 GND#96 GND#97 GND#98

A3 A37 AA16 AA18 AA2 AA21 AA23 AA26 AA28 AA6 AB12 AB15 AB17 AB20 AB22 AB24 AB27 AC11 AC13 AC16 AC18 AC2 AC21 AC23 AC26 AC28 AC6 AD15 AD17 AD20 AD22 AD24 AD27 AD9 AE2 AE6 AF10 AF16 AF18 AF21 AG17 AG2 AG20 AG22 AG6 AG9 AH21 AJ10 AJ11 AJ2 AJ28 AJ6 AK11 AK31 AK7 AL11 AL14 AL17 AL2 AL20 AL21 AL23 AL26 AL32 AL6 AL8 AM11 AM31 AM9 AN11 AN2 AN30 AN6 AN8 AP11 AP7 AP9 AR5 B11 B13 B15 B17 B19 B21 B23 B25 B27 B29 B31 B33 B7 B9 C1 C39 E35 E5 F11 F13

A39 AW1 AW39

MECH#1 MECH#2 MECH#3

12

RV125

4.7K_0402_5%

(Thames 220mA)

1.0V@220mA DPCD_VDD10)

1.8V@300mA DPEF_VDD18)

(Thames 330mA)

1.0V@240mA DPEF_VDD10)

(Thames 220mA)

Thames/Seymour Only

Do not install for Heathrow/Chelsea

PS_0 Should be tied to GND on Thames/Seymour

T821PADT821PAD T831PADT831PAD T841PADT841PAD

B

UV1H

(Thames 330mA)

1.8V@300mA DPCD_VDD18)

+1.8VGS

RV119 0_0402_5%RV119 0_0402_5%

+1.0VGS

+1.8VGS

+1.0VGS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

RV121 0_0402_5%RV121 0_0402_5%

+DPCD_VDD18

+DPCD_VDD10

1 2

RV124 0_0402_5%RV124 0_0402_5%

1 2

RV126 0_0402_5%RV126 0_0402_5%

+DPEF_VDD18

+DPEF_VDD10

PS_0<20>

C

+DPCD_VDD18

1 2

20mil

12

+DPEF_VDD18

20mil

+DPEF_VDD10

20mil

PS_0

RV199

RV199 0_0402_5%

0_0402_5% TH@

TH@

1 2

RV127

150_0402_1%

2011/11/28 2013/12/31

UV1H

20mil

AP20

DPCD/DPC_VDD18#1

AP21

DPCD/DPC_VDD18#2

AP13

DPCD/DPC_VDD10#1

AT13

DPCD/DPC_VDD10#2

AN17

DP/DPC_VSSR#1

AP16

DP/DPC_VSSR#2

AP17

DP/DPC_VSSR#3

AW14

DP/DPC_VSSR#4

AW16

DP/DPC_VSSR#5

AP22

DPCD/DPD_VDD18#1

AP23

DPCD/DPD_VDD18#2

AP14

DPCD/DPD_VDD10#1

AP15

DPCD/DPD_VDD10#2

AN19

DP/DPD_VSSR#1

AP18

DP/DPD_VSSR#2

AP19

DP/DPD_VSSR#3

AW20

DP/DPD_VSSR#4

AW22

DP/DPD_VSSR#5

RV122150_0402_1% RV122150_0402_1%

AW18

DPCD_CALR

20mil

20mA

12

DP E/F POWER

AH34

DPEF/DPE_VDD18#1

AJ34

DPEF/DPE_VDD18#2

AL33

DPEF/DPE_VDD10#1

AM33

DPEF/DPE_VDD10#2

AN34

DP/DPE_VSSR#1

AP39

DP/DPE_VSSR#2

AR39

DP/DPE_VSSR#3

AU37

DP/DPE_VSSR#4

AF34

DPEF/DPF_VDD18#1

AG34

DPEF/DPF_VDD18#2

AK33

DPEF/DPF_VDD10#1

AK34

DPEF/DPF_VDD10#2

AF39

DP/DPF_VSSR#1

AH39

DP/DPF_VSSR#2

AK39

DP/DPF_VSSR#3

AL34

DP/DPF_VSSR#4

AM34

DP/DPF_VSSR#5

AM39

DPEF_CALR

THAMES XT M2 THR3@

Compal Secret Data

Deciphered Date

DP C/D POWER

DP A/B POWER

DPAB/DPA_VDD18#1 DPAB/DPA_VDD18#2

DPAB/DPA_VDD10#1 DPAB/DPA_VDD10#2

DP/DPA_VSSR#1 DP/DPA_VSSR#2 DP/DPA_VSSR#3 DP/DPA_VSSR#4 DP/DPA_VSSR#5

DPAB/DPB_VDD18#1 DPAB/DPB_VDD18#2

DPAB/DPB_VDD10#1 DPAB/DPB_VDD10#2

DP/DPB_VSSR#1 DP/DPB_VSSR#2 DP/DPB_VSSR#3 DP/DPB_VSSR#4 DP/DPB_VSSR#5

DPAB_CALR

DP PLL POWER

DPAB_VDD18/DPA_PVDD

DP_VSSR/DPA_PVSS

DPAB_VDD18/DPB_PVDD

DP_VSSR/DPB_PVSS

DPCD_VDD18/DPC_PVDD

DP_VSSR/DPC_PVSS

DPCD_VDD18/DPD_PVDD

DP_VSSR/DPD_PVSS

DPEF_VDD18/DPE_PVDD

DP_VSSR/DPE_PVSS

DPEF_VDD18/DPF_PVDD

DP_VSSR/DPF_PVSS

D

20mil

130mA

20mil

110mA

20mA

(Thames 330mA)

1.8V@300mA DPAB_VDD18)

+DPAB_VDD18

AN24 AP24

1 2

RV118 0_0402_5%RV118 0_0402_5%

+1.8VGS

(1.0V@220mA DPAB_VDD10)

+DPAB_VDD10+DPCD_VDD10

AP31 AP32

AN27 AP27 AP28 AW24 AW26

130mA

AP25 AP26

110mA

AN33 AP33

AN29 AP29 AP30 AW30 AW32

RV123 150_0402_1%RV123 150_0402_1%

AW28

10mil

AU28 AV27

10mil

AV29 AR28

10mil

AU18 AV17

10mil

AV19 AR18

10mil

AM37 AN38

10mil

AL38 AM35

1 2

RV120 0_0402_5%RV120 0_0402_5%

20mil

+DPAB_VDD18

20mil

+DPAB_VDD10

1 2

+DPAB_VDD18

+DPCD_VDD18

+DPEF_VDD18

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC,MB LA-8863

4019IT

+1.0VGS

E

A

of

16 51Friday, March 23, 2012

A

UV1C

DDR2

DDR2 GDDR3/GDDR5

GDDR3/GDDR5 DDR3

AG12

AH12

C37 C35 A35 E34 G32 D33 F32 E32 D31 F30 C30 A30 F28 C28 A28 E28 D27 F26 C26 A26 F24 C24 A24 E24 C22 A22 F22 D21 A20 F20 D19 E18 C18 A18 F18 D17 A16 F16 D15 E14 F14 D13 F12 A12 D11 F10 A10 C10 G13 H13 J13 H11 G10

G8 K9

K10

G9 A8 C8 E8 A6 C6 E6 A5

L18 L20

L27 N12

M12 M27

DDR3

DQA0_0/DQA_0 DQA0_1/DQA_1 DQA0_2/DQA_2 DQA0_3/DQA_3 DQA0_4/DQA_4 DQA0_5/DQA_5 DQA0_6/DQA_6 DQA0_7/DQA_7 DQA0_8/DQA_8 DQA0_9/DQA_9 DQA0_10/DQA_10 DQA0_11/DQA_11 DQA0_12/DQA_12 DQA0_13/DQA_13 DQA0_14/DQA_14 DQA0_15/DQA_15 DQA0_16/DQA_16 DQA0_17/DQA_17 DQA0_18/DQA_18 DQA0_19/DQA_19 DQA0_20/DQA_20 DQA0_21/DQA_21 DQA0_22/DQA_22 DQA0_23/DQA_23 DQA0_24/DQA_24 DQA0_25/DQA_25 DQA0_26/DQA_26 DQA0_27/DQA_27 DQA0_28/DQA_28 DQA0_29/DQA_29 DQA0_30/DQA_30 DQA0_31/DQA_31 DQA1_0/DQA_32 DQA1_1/DQA_33 DQA1_2/DQA_34 DQA1_3/DQA_35 DQA1_4/DQA_36 DQA1_5/DQA_37 DQA1_6/DQA_38 DQA1_7/DQA_39 DQA1_8/DQA_40 DQA1_9/DQA_41 DQA1_10/DQA_42 DQA1_11/DQA_43 DQA1_12/DQA_44 DQA1_13/DQA_45 DQA1_14/DQA_46 DQA1_15/DQA_47 DQA1_16/DQA_48 DQA1_17/DQA_49 DQA1_18/DQA_50 DQA1_19/DQA_51 DQA1_20/DQA_52 DQA1_21/DQA_53 DQA1_22/DQA_54 DQA1_23/DQA_55 DQA1_24/DQA_56 DQA1_25/DQA_57 DQA1_26/DQA_58 DQA1_27/DQA_59 DQA1_28/DQA_60 DQA1_29/DQA_61 DQA1_30/DQA_62 DQA1_31/DQA_63

MVREFDA MVREFSA

MEM_CALRN0 MEM_CALRN1 MEM_CALRN2

MEM_CALRP1 MEM_CALRP0 MEM_CALRP2

THAMES XT M2

THAMES XT M2 THR3@

THR3@

40.2_0402_1%

100_0402_1%

RV140

RV147

MDA0 MDA1 MDA2 MDA3 MDA4 MDA5 MDA6 MDA7 MDA8 MDA9 MDA10

1 1

2 2

+1.5VGS

RV129 240_0402_1%TH@RV129 240_0402_1%TH@

1 2

RV130 240_0402_1%@RV130 240_0402_1%@

1 2

RV131 240_0402_1%TH@RV131 240_0402_1%TH@

1 2

RV132 240_0402_1%@RV132 240_0402_1%@

1 2

RV134 240_0402_1%TH@RV134 240_0402_1%TH@

1 2

RV135 240_0402_1%TH@RV135 240_0402_1%TH@

1 2

RV135

RV135 120_0402_1%

120_0402_1% CH@

CH@

3 3

+1.5VGS +1.5VGS

RV139

40.2_0402_1%

4 4

RV146

100_0402_1%

MDA11 MDA12 MDA13 MDA14 MDA15 MDA16 MDA17 MDA18 MDA19 MDA20 MDA21 MDA22 MDA23 MDA24 MDA25 MDA26 MDA27 MDA28 MDA29 MDA30 MDA31 MDA32 MDA33 MDA34 MDA35 MDA36 MDA37 MDA38 MDA39 MDA40 MDA41 MDA42 MDA43 MDA44 MDA45 MDA46 MDA47 MDA48 MDA49 MDA50 MDA51 MDA52 MDA53 MDA54 MDA55 MDA56 MDA57 MDA58 MDA59 MDA60 MDA61 MDA62 MDA63

+VDD_MEM15_REFDA +VDD_MEM15_REFSA

RV134

RV134 120_0402_1%

120_0402_1% CH@

CH@

12

+VDD_MEM15_REFDA

12

CV220

0.1U_0402_16V7K

DDR2

DDR2 GDDR5/GDDR3

GDDR5/GDDR3 DDR3

DDR3

MAA0_0/MAA_0 MAA0_1/MAA_1 MAA0_2/MAA_2 MAA0_3/MAA_3 MAA0_4/MAA_4 MAA0_5/MAA_5 MAA0_6/MAA_6 MAA0_7/MAA_7 MAA1_0/MAA_8

MAA1_1/MAA_9 MAA1_2/MAA_10 MAA1_3/MAA_11 MAA1_4/MAA_12

MAA1_5/MAA_13_BA2 MAA1_6/MAA_14_BA0

MAA1_7/MAA_A15_BA1

WCKA0_0/DQMA_0

WCKA0B_0/DQMA_1

WCKA0_1/DQMA_2

WCKA0B_1/DQMA_3

WCKA1_0/DQMA_4

WCKA1B_0/DQMA_5

WCKA1_1/DQMA_6

WCKA1B_1/DQMA_7

GDDR5/DDR2/GDDR3

MEMORY INTERFACE A

EDCA0_0/QSA_0/RDQSA_0 EDCA0_1/QSA_1/RDQSA_1 EDCA0_2/QSA_2/RDQSA_2 EDCA0_3/QSA_3/RDQSA_3 EDCA1_0/QSA_4/RDQSA_4 EDCA1_1/QSA_5/RDQSA_5 EDCA1_2/QSA_6/RDQSA_6 EDCA1_3/QSA_7/RDQSA_7

DDBIA0_0/QSA_0B/WDQSA_0 DDBIA0_1/QSA_1B/WDQSA_1 DDBIA0_2/QSA_2B/WDQSA_2 DDBIA0_3/QSA_3B/WDQSA_3 DDBIA1_0/QSA_4B/WDQSA_4 DDBIA1_1/QSA_5B/WDQSA_5 DDBIA1_2/QSA_6B/WDQSA_6 DDBIA1_3/QSA_7B/WDQSA_7

ADBIA0/ODTA0 ADBIA1/ODTA1

CLKA0

CLKA0B

CLKA1

CLKA1B

RASA0B RASA1B

CASA0B CASA1B

CSA0B_0 CSA0B_1

CSA1B_0 CSA1B_1

CKEA0 CKEA1

WEA0B WEA1B

MAA0_8 MAA1_8

GDDR5

12

+VDD_MEM15_REFSA

12

CV221

0.1U_0402_16V7K

B

MDA[0..63]<18> MDB[0..63]<19>

MAA0

G24

MAA1

J23

MAA2

H24

MAA3

J24

MAA4

H26

MAA5

J26

MAA6

H21

MAA7

G21

MAA8

H19

MAA9

H20

MAA10

L13

MAA11

G16

MAA12

J16

A_BA2

H16

A_BA0

J17

A_BA1

H17

DQMA#0

A32

DQMA#1

C32

DQMA#2

D23

DQMA#3

E22

DQMA#4

C14

DQMA#5

A14

DQMA#6

E10

DQMA#7

D9

QSA0

C34

QSA1

D29

QSA2

D25

QSA3

E20

QSA4

E16

QSA5

E12

QSA6

J10

QSA7

D7

QSA#0

A34

QSA#1

E30

QSA#2

E26

QSA#3

C20

QSA#4

C16

QSA#5

C12

QSA#6

J11

QSA#7

F8

ODTA0

J21

ODTA1

G19

CLKA0

H27

CLKA0#

G27

CLKA1

J14

CLKA1#

H14

RASA0#

K23

RASA1#

K19

CASA0#

K20

CASA1#

K17

CSA0#_0

K24 K27

CSA1#_0

M13 K16

CKEA0

K21

CKEA1

J20

WEA0#

K26

WEA1#

L15

MAA13

H23

MAA14

J19

This basic topology should be used for DRAM_RST for DDR3/GDDR5.These Capacitors and Resistor values are an example only. The Series R and || Cap values will depend on the DRAM load and will have to be calculated for different Memory ,DRAM Load and board to pass Reset Signal Spec. Place all these components very close to GPU (Within 25mm) and keep all component close to each Other (within 5mm) except Rser2

DRAM_RST#<18,19>

ODTA0 <18> ODTA1 <18>

CLKA0 <18> CLKA0# <18>

CLKA1 <18> CLKA1# <18>

RASA0# <18> RASA1# <18>

CASA0# <18> CASA1# <18>

CSA0#_0 <18>

CSA1#_0 <18>

CKEA0 <18> CKEA1 <18>

WEA0# <18> WEA1# <18>

MAA13 <18> MAA14 <18> MAB14 <19>

+1.5VGS

RV138

4.7K_0402_5%

4.7K_0402_5% @

@

RV143

1 2

51.1_0402_1%

MDA[0..63] MDB[0..63]

MAA[12..0] MAB[12..0] A_BA[2..0] B_BA[2..0]

DQMA#[7..0] <18>

QSA[7..0] <18>

QSA#[7..0] <18>

12

CV222

120P_0402_50V9

12

RV144

1 2

10_0402_5%

MAA[12..0] <18>

A_BA[2..0] <18>

DRAM_RST#_R

RV145

4.99K_0402_1%

1 2

+3VGS

C

@

1 2 1 2

0.1U_0402_16V7K

+VDD_MEM15_REFDB +VDD_MEM15_REFSB

RV1335.11K_0402_1%@RV1335.11K_0402_1% RV2061K_0402_1% RV2061K_0402_1%

@

CV218

@

RV136

51.1_0402_1%

RV141

40.2_0402_1%

RV148

100_0402_1%

D

UV1D

DDR2

DDR2 GDDR3/GDDR5

GDDR3/GDDR5 DDR3

C5 C3 E3 E1

F1 F3

F5 G4 H5 H6

J4 K6 K5

L4

M6 M1 M3 M5

N4 P6 P5 R4

T6

T1 U4 V6 V1 V3 Y6 Y1 Y3 Y5

AA4 AB6 AB1 AB3 AD6 AD1 AD3 AD5 AF1 AF3 AF6

AG4

AH5 AH6 AJ4 AK3 AF8

AF9 AG8 AG7

AK9

AL7 AM8 AM7

AK1

AL4 AM6 AM1

AN4

AP3

AP1

AP5

Y12

AA12

AD28 AK10

AL10

12

@

@ CV219

CV219

0.1U_0402_16V7K

12

@

@ RV137

RV137

51.1_0402_1%

12

DDR3

DQB0_0/DQB_0 DQB0_1/DQB_1 DQB0_2/DQB_2 DQB0_3/DQB_3 DQB0_4/DQB_4 DQB0_5/DQB_5 DQB0_6/DQB_6 DQB0_7/DQB_7 DQB0_8/DQB_8 DQB0_9/DQB_9 DQB0_10/DQB_10 DQB0_11/DQB_11 DQB0_12/DQB_12 DQB0_13/DQB_13 DQB0_14/DQB_14 DQB0_15/DQB_15 DQB0_16/DQB_16 DQB0_17/DQB_17 DQB0_18/DQB_18 DQB0_19/DQB_19 DQB0_20/DQB_20 DQB0_21/DQB_21 DQB0_22/DQB_22 DQB0_23/DQB_23 DQB0_24/DQB_24 DQB0_25/DQB_25 DQB0_26/DQB_26 DQB0_27/DQB_27 DQB0_28/DQB_28 DQB0_29/DQB_29 DQB0_30/DQB_30 DQB0_31/DQB_31 DQB1_0/DQB_32 DQB1_1/DQB_33 DQB1_2/DQB_34 DQB1_3/DQB_35 DQB1_4/DQB_36 DQB1_5/DQB_37 DQB1_6/DQB_38 DQB1_7/DQB_39 DQB1_8/DQB_40 DQB1_9/DQB_41 DQB1_10/DQB_42 DQB1_11/DQB_43 DQB1_12/DQB_44 DQB1_13/DQB_45 DQB1_14/DQB_46 DQB1_15/DQB_47 DQB1_16/DQB_48 DQB1_17/DQB_49 DQB1_18/DQB_50 DQB1_19/DQB_51 DQB1_20/DQB_52 DQB1_21/DQB_53 DQB1_22/DQB_54 DQB1_23/DQB_55 DQB1_24/DQB_56 DQB1_25/DQB_57 DQB1_26/DQB_58 DQB1_27/DQB_59 DQB1_28/DQB_60 DQB1_29/DQB_61 DQB1_30/DQB_62 DQB1_31/DQB_63

MVREFDB MVREFSB

TESTEN CLKTESTA

CLKTESTB

THAMES XT M2

THAMES XT M2 THR3@

THR3@

route 50ohms single-ended/100ohms diff and keep short Debug only, for clock observation, if not needed, DNI 5mil 5mil

+VDD_MEM15_REFDB

12

CV223

0.1U_0402_16V7K

MDB0 MDB1 MDB2 MDB3 MDB4 MDB5 MDB6 MDB7 MDB8 MDB9 MDB10 MDB11 MDB12 MDB13 MDB14 MDB15 MDB16 MDB17 MDB18 MDB19 MDB20 MDB21 MDB22 MDB23 MDB24 MDB25 MDB26 MDB27 MDB28 MDB29 MDB30 MDB31 MDB32 MDB33 MDB34 MDB35 MDB36 MDB37 MDB38 MDB39 MDB40 MDB41 MDB42 MDB43 MDB44 MDB45 MDB46 MDB47 MDB48 MDB49 MDB50 MDB51 MDB52 MDB53 MDB54 MDB55 MDB56 MDB57 MDB58 MDB59 MDB60 MDB61 MDB62 MDB63

TESTEN

12

+1.5VGS +1.5VGS

DDR2

DDR2 GDDR5/GDDR3

GDDR5/GDDR3 DDR3

DDR3

MAB0_0/MAB_0 MAB0_1/MAB_1 MAB0_2/MAB_2 MAB0_3/MAB_3 MAB0_4/MAB_4 MAB0_5/MAB_5 MAB0_6/MAB_6 MAB0_7/MAB_7 MAB1_0/MAB_8

MAB1_1/MAB_9 MAB1_2/MAB_10 MAB1_3/MAB_11 MAB1_4/MAB_12

MAB1_5/BA2 MAB1_6/BA0 MAB1_7/BA1

WCKB0_0/DQMB_0

WCKB0B_0/DQMB_1

WCKB0_1/DQMB_2

WCKB0B_1/DQMB_3

WCKB1_0/DQMB_4

WCKB1B_0/DQMB_5

WCKB1_1/DQMB_6

WCKB1B_1/DQMB_7

GDDR5/DDR2/GDDR3

EDCB0_0/QSB_0/RDQSB_0

MEMORY INTERFACE B

EDCB0_1/QSB_1/RDQSB_1 EDCB0_2/QSB_2/RDQSB_2 EDCB0_3/QSB_3/RDQSB_3 EDCB1_0/QSB_4/RDQSB_4 EDCB1_1/QSB_5/RDQSB_5 EDCB1_2/QSB_6/RDQSB_6 EDCB1_3/QSB_7/RDQSB_7

DDBIB0_0/QSB_0B/WDQSB_0 DDBIB0_1/QSB_1B/WDQSB_1 DDBIB0_2/QSB_2B/WDQSB_2 DDBIB0_3/QSB_3B/WDQSB_3 DDBIB1_0/QSB_4B/WDQSB_4 DDBIB1_1/QSB_5B/WDQSB_5 DDBIB1_2/QSB_6B/WDQSB_6 DDBIB1_3/QSB_7B/WDQSB_7

ADBIB0/ODTB0 ADBIB1/ODTB1

CLKB0B

CLKB1B RASB0B

RASB1B CASB0B

CASB1B

CSB0B_0 CSB0B_1

CSB1B_0 CSB1B_1

WEB0B WEB1B

MAB0_8 MAB1_8

DRAM_RST

GDDR5

RV142

40.2_0402_1%

RV149

100_0402_1%

CLKB0

CLKB1

CKEB0 CKEB1

12

MAB0

P8

MAB1

T9

MAB2

P9

MAB3

N7

MAB4

N8

MAB5

N9

MAB6

U9

MAB7

U8

MAB8

Y9

MAB9

W9

MAB10

AC8

MAB11

AC9

MAB12

AA7

B_BA2

AA8

B_BA0

Y8

B_BA1

AA9

DQMB#0

H3

DQMB#1

H1

DQMB#2

T3

DQMB#3

T5

DQMB#4

AE4

DQMB#5

AF5

DQMB#6

AK6

DQMB#7

AK5

QSB0

F6

QSB1

K3

QSB2

P3

QSB3

V5

QSB4

AB5

QSB5

AH1

QSB6

AJ9

QSB7

AM5

QSB#0

G7

QSB#1

K1

QSB#2

P1

QSB#3

W4

QSB#4

AC4

QSB#5

AH3

QSB#6

AJ8

QSB#7

AM3

ODTB0

T7

ODTB1

W7

CLKB0

L9

CLKB0#

L8

CLKB1

AD8

CLKB1#

AD7

RASB0#

T10

RASB1#

Y10

CASB0#

W10

CASB1#

AA10

CSB0#_0

P10 L10

CSB1#_0

AD10 AC10

CKEB0

U10

CKEB1

AA11

WEB0#

N10

WEB1#

AB11

MAB13

T8

MAB14

W8

DRAM_RST#_R

AH11

+VDD_MEM15_REFSB

12

CV224

0.1U_0402_16V7K

DQMB#[7..0] <19>

QSB[7..0] <19>

QSB#[7..0] <19>

ODTB0 <19> ODTB1 <19>

CLKB0 <19> CLKB0# <19>

CLKB1 <19> CLKB1# <19>

RASB0# <19> RASB1# <19>

CASB0# <19> CASB1# <19>

CSB0#_0 <19>

CSB1#_0 <19>

CKEB0 <19> CKEB1 <19>

WEB0# <19> WEB1# <19>

MAB13 <19>

E

MAB[12..0] <19>

B_BA[2..0] <19>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2011/11/28 2013/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC,MB LA-8863

4019IT

E

17 51Friday, March 23, 2012

A

of

A

B

C

D

E

CHANNEL A: 512MB/1024MB DDR3

UV18

+VREFC_A1

A_BA0<17> A_BA1<17> A_BA2<17>

CLKA0<17> CLKA0#<17> CKEA0<17>

ODTA0<17> CSA0#_0<17> RASA0#<17> CASA0#<17> WEA0#<17>

DRAM_RST#<17,19>

RV150

240_0402_1%

+VREFD_Q1

QSA3 QSA0

DQMA#3 DQMA#0

QSA#3 QSA#0

1 1

MDA[0..63]<17>

MAA[14..0]<17>

DQMA#[7..0]<17>

QSA[7..0]<17>

QSA#[7..0]<17>

2 2

CLKA0

RV154 40.2_0402_1%RV154 40.2_0402_1%

CLKA0#

RV155 40.2_0402_1%RV155 40.2_0402_1%

3 3

CLKA1

RV164 40.2_0402_1%RV164 40.2_0402_1%

CLKA1#

RV165 40.2_0402_1%RV165 40.2_0402_1%

1 2

MDA[0..63]

MAA[14..0]

DQMA#[7..0]

QSA[7..0]

QSA#[7..0]

12

CV225

0.01U_0402_16V7K

12

CV234

0.01U_0402_16V7K

UV18

M8

VREFCA

H1

VREFDQ

MAA0

N3

A0

MAA1

P7

A1

MAA2

P3

A2

MAA3

N2

A3

MAA4

P8

A4

MAA5

P2

A5

MAA6

R8

A6

MAA7

R2

A7

MAA8

T8

A8

MAA9

R3

A9

MAA10

L7

A10/AP

MAA11

R7

A11

MAA12

N7

A12

MAA13

T3

A13

MAA14

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

12

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

K4W1G1646G-BC11_FBGA96

+1.5VGS +1.5VGS+1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS

12

RV156

4.99K_0402_1%

15mil 15mil 15mil 15mil 15mil 15mil 15mil 15mil

12

RV166

4.99K_0402_1%

12

CV226

MDA29

E3

DQL0

MDA25

F7

DQL1

MDA30

F2

DQL2

MDA24

F8

DQL3

MDA31

H3

DQL4

MDA26

H8

DQL5

MDA28

G2

DQL6

MDA27

H7

DQL7

MDA0

D7

DQU0

MDA5

C3

DQU1

MDA1

C8

DQU2

MDA6

C2

DQU3

MDA3

A7

DQU4

MDA4

A2

DQU5

MDA2

B8

DQU6

MDA7

A3

DQU7

VDD VDD VDD VDD VDD VDD VDD VDD VDD

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

+VREFD_Q1 +VREFD_Q2

0.1U_0402_16V7K

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

@

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

4.99K_0402_1%

+1.5VGS

RV157

RV167

12

+VREFC_A2 +VREFD_Q2

A_BA0 A_BA0 A_BA0 A_BA1 A_BA1 A_BA1 A_BA2 A_BA2 A_BA2

CLKA0 CLKA0# CKEA0 CKEA1

ODTA0 ODTA1 CSA0#_0 CSA1#_0 RASA0# RASA1# CASA0# CASA1# WEA0# WEA1#

QSA2 QSA4 QSA1

DQMA#2 DQMA#4 DQMA#1

QSA#2 QSA#4 QSA#1

DRAM_RST# DRAM_RST# DRAM_RST#

12

RV151

240_0402_1%

+VREFC_A1 +VREFC_A2

0.1U_0402_16V7K

12

CV227

UV19

M8

VREFCA

H1

VREFDQ

MAA0 MAA0 MAA0

N3

A0

MAA1 MAA1 MAA1

P7

A1

MAA2 MAA2 MAA2

P3

A2

MAA3 MAA3 MAA3

N2

A3

MAA4 MAA4 MAA4

P8

A4

MAA5 MAA5 MAA5

P2

A5

MAA6 MAA6 MAA6

R8

A6

MAA7 MAA7 MAA7

R2

A7

MAA8 MAA8 MAA8

T8

A8

MAA9 MAA9 MAA9

R3

A9

MAA10 MAA10 MAA10

L7

A10/AP

MAA11 MAA11 MAA11

R7

A11

MAA12 MAA12 MAA12

N7

A12

MAA13 MAA13 MAA13

T3

A13

MAA14 MAA14 MAA14

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

K4W1G1646G-BC11_FBGA96

12

RV158

4.99K_0402_1%

12

RV168

CV228

4.99K_0402_1%

CV228

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDD VDD VDD VDD VDD VDD VDD VDD VDD

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

@

0.1U_0402_16V7K

12

MDA18

E3

MDA20

F7

MDA16

F2

MDA23

F8

MDA19

H3

MDA22

H8

MDA17

G2

MDA21

H7

MDA15

D7

MDA10

C3

MDA14

C8

MDA11

C2

MDA13

A7

MDA9

A2

MDA12

B8

MDA8

A3

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

RV159

4.99K_0402_1%

RV169

4.99K_0402_1%

+1.5VGS

12

RV152

240_0402_1%

0.1U_0402_16V7K

12

CV229

CLKA1<17> CLKA1#<17> CKEA1<17>

ODTA1<17> CSA1#_0<17> RASA1#<17> CASA1#<17> WEA1#<17>

+VREFC_A3 +VREFD_Q3

12

QSA5

DQMA#5

QSA#5

4.99K_0402_1%

UV20

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

K4W1G1646G-BC11_FBGA96

12

RV160

12

RV170

12

CV230

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDD VDD VDD VDD VDD VDD VDD VDD VDD

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

@

4.99K_0402_1%

+VREFC_A3

0.1U_0402_16V7K

4.99K_0402_1%

+1.5VGS

240_0402_1%

CV231

RV153

+VREFD_Q3

0.1U_0402_16V7K

12

+VREFC_A4 +VREFD_Q4

CLKA1 CLKA1#

QSA6 QSA7

DQMA#6 DQMA#7

QSA#6 QSA#7

12

MDA35

E3

MDA36

F7

MDA38

F2

MDA34

F8

MDA39

H3

MDA33

H8

MDA37

G2

MDA32

H7

MDA42

D7

MDA44

C3

MDA40

C8

MDA46

C2

MDA43

A7

MDA45

A2

MDA41

B8

MDA47

A3

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

12

RV161

12

RV171

UV21

M8 H1

N3 P7 P3 N2 P8 P2 R8 R2 T8 R3

L7 R7 N7 T3 T7 M7

M2 N8 M3

J7

K7

K9

K1

L2

J3

K3

L3

F3 C7

E7 D3

G3

B7

T2

L8

J1

L1

J9

L9

K4W1G1646G-BC11_FBGA96

RV162

4.99K_0402_1%

RV172

4.99K_0402_1%

VREFCA VREFDQ

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3

BA0 BA1 BA2

CK CK CKE/CKE0

ODT/ODT0 CS/CS0 RAS CAS WE

DQSL DQSU

DML DMU

DQSL DQSU

RESET ZQ/ZQ0

NC/ODT1 NC/CS1 NC/CE1 NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

12

CV232

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDD VDD VDD VDD VDD VDD VDD VDD VDD

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

@

+VREFC_A4

0.1U_0402_16V7K

12

E3 F7 F2 F8 H3 H8 G2 H7

D7 C3 C8 C2 A7 A2 B8 A3

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

RV163

4.99K_0402_1%

RV173

4.99K_0402_1%

MDA50 MDA51 MDA55 MDA52 MDA48 MDA53 MDA49 MDA54

MDA60 MDA58 MDA63 MDA59 MDA61 MDA56 MDA62 MDA57

+1.5VGS

12

CV233

+VREFD_Q4

0.1U_0402_16V7K

+1.5VGS

1

CV236

2

0.1U_0402_16V7K

1 CV237

CV237

2

0.1U_0402_16V7K

1

CV238

2

0.1U_0402_16V7K

1

CV239

2

0.1U_0402_16V7K

1

CV240

2

0.1U_0402_16V7K

1

CV241

2

0.1U_0402_16V7K

1 CV242

CV242

2

0.1U_0402_16V7K

1

CV243

2

0.1U_0402_16V7K

1 CV244

CV244

2

0.1U_0402_16V7K

1

CV245

2

0.1U_0402_16V7K

1 CV246

CV246

2

0.1U_0402_16V7K

1

CV247

2

0.1U_0402_16V7K

1 CV235

CV235

2

0.1U_0402_16V7K

4 4

0.1U_0402_16V7K

+1.5VGS

1

CV248

2

10U_0603_6.3V6M

1 CV249

CV249

2

10U_0603_6.3V6M

1

CV250

2

1

CV251

2

10U_0603_6.3V6M

+1.5VGS +1.5VGS

1

CV252

2

1U_0402_6.3V6K

1

CV253

2

1U_0402_6.3V6K

1 CV254

CV254

2

1U_0402_6.3V6K

1

CV255

2

1U_0402_6.3V6K

1 CV256

CV256

2

1

CV257

2

1U_0402_6.3V6K

1 CV258

CV258

2

1

CV259

2

1U_0402_6.3V6K

1 CV260

CV260

2

1

CV261

2

1U_0402_6.3V6K

1 CV262

CV262

2

1U_0402_6.3V6K

1 CV263

CV263

2

1U_0402_6.3V6K

1

CV264

2

1

CV265

2

1U_0402_6.3V6K

1 CV266

CV266

2

1 CV267

CV267

2

1U_0402_6.3V6K

1

CV268

2

1U_0402_6.3V6K

1

CV269

2

1

CV270

2

1U_0402_6.3V6K

1

CV271

2

1U_0402_6.3V6K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2011/11/28 2013/12/31

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

SCHEMATIC,MB LA-8863

Size Document Number Rev

C A

Date: Sheet of

4019IT

E

18 51Friday, March 23, 2012

5

4

3

2

1

CHANNEL B: 512MB/1024MB DDR3

UV25

UV22

+VREFC_A1_B +VREFD_Q1_B

D D

MDB[0..63]<17>

MAB[14..0]<17>

DQMB#[7..0]<17>

QSB[7..0]<17>

QSB#[7..0]<17>

C C

CLKB0

RV174 40.2_0402_1%RV174 40.2_0402_1%

CLKB0#

RV175 40.2_0402_1%RV175 40.2_0402_1%

CLKB1

1 2

RV180 40.2_0402_1%RV180 40.2_0402_1%

CLKB1#

1 2

RV181 40.2_0402_1%RV181 40.2_0402_1%

1 2

MDB[0..63]

MAB[14..0]

DQMB#[7..0]

QSB[7..0]

QSB#[7..0]

12

CV272

0.01U_0402_16V7K

CV273

0.01U_0402_16V7K

B_BA0<17> B_BA1<17> B_BA2<17>

CLKB0<17> CLKB0#<17> CKEB0<17>

ODTB0<17> CSB0#_0<17> RASB0#<17> CASB0#<17> WEB0#<17>

QSB3 QSB2 QSB4 QSB0 QSB1

DQMB#3 DQMB#2 DQMB#4 DQMB#0 DQMB#1

QSB#3 QSB#2 QSB#4 QSB#0 QSB#1

DRAM_RST#<17,18>

12

RV176

240_0402_1%

UV22

M8

VREFCA

H1

VREFDQ

MAB0 MAB0 MAB0 MAB0

N3

A0

MAB1 MAB1 MAB1 MAB1

P7

A1

MAB2 MAB2 MAB2 MAB2

P3

A2

MAB3 MAB3 MAB3 MAB3

N2

A3

MAB4 MAB4 MAB4 MAB4

P8

A4

MAB5 MAB5 MAB5 MAB5

P2

A5

MAB6 MAB6 MAB6 MAB6

R8

A6

MAB7 MAB7 MAB7 MAB7

R2

A7

MAB8 MAB8 MAB8 MAB8

T8

A8

MAB9 MAB9 MAB9 MAB9MDB1

R3

A9

MAB10 MAB10 MAB10 MAB10

L7

A10/AP

MAB11 MAB11 MAB11 MAB11

R7

A11

MAB12 MAB12 MAB12 MAB12

N7

A12

MAB13 MAB13 MAB13 MAB13

T3

A13

MAB14 MAB14 MAB14 MAB14

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

K4W1G1646G-BC11_FBGA96

MDB29

E3

DQL0

MDB26

F7

DQL1

MDB30

F2

DQL2

MDB27

F8

DQL3

MDB31

H3

DQL4

MDB25

H8

DQL5

MDB28

G2

DQL6

MDB24

H7

DQL7

MDB3

D7

DQU0

MDB5

C3

DQU1

C8

DQU2

MDB6

C2

DQU3

MDB2

A7

DQU4

MDB7 MDB9

A2

DQU5

MDB0

B8

DQU6

MDB4

A3

DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

+1.5VGS

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

@

+1.5VGS

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

+VREFC_A2_B +VREFD_Q2_B

B_BA0 B_BA0 B_BA0 B_BA1 B_BA1 B_BA1 B_BA2 B_BA2 B_BA2

CLKB0 CLKB0# CKEB0 CKEB1

ODTB0 ODTB1 CSB0#_0 CSB1#_0 RASB0# RASB1# CASB0# CASB1# WEB0# WEB1#

DRAM_RST# DRAM_RST# DRAM_RST#

12

RV177

240_0402_1%

UV23

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

K4W1G1646G-BC11_FBGA96

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

RV178

240_0402_1%

CLKB1<17> CLKB1#<17> CKEB1<17>

ODTB1<17> CSB1#_0<17> RASB1#<17> CASB1#<17> WEB1#<17>

12

+VREFC_A3_B +VREFD_Q3_B

QSB5

DQMB#5

QSB#5

MDB17

E3

MDB19

F7

MDB16

F2

MDB22

F8

MDB20

H3

MDB21

H8

MDB18

G2

MDB23

H7

MDB15

D7

MDB10

C3

MDB12

C8 C2

MDB13

A7 A2

MDB14

B8

MDB11

A3

+1.5VGS

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

@

+1.5VGS

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

UV24

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

K4W1G1646G-BC11_FBGA96

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

MDB33

E3

MDB37

F7

MDB35

F2

MDB39

F8

MDB32

H3

MDB36

H8

MDB34

G2

MDB38

H7

MDB45

D7

MDB43

C3

MDB47

C8

MDB42MDB8

C2 A7

MDB40

A2

MDB46

B8

MDB41

A3

+1.5VGS

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

@

+1.5VGS

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

RV179

240_0402_1%

+VREFC_A4_B +VREFD_Q4_B

CLKB1 CLKB1#

QSB6 QSB7

DQMB#6 DQMB#7

QSB#6 QSB#7

12

UV25

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

K4W1G1646G-BC11_FBGA96

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

MDB53

E3

MDB50

F7

MDB52

F2

MDB51

F8

MDB55

H3

MDB49

H8

MDB54

G2

MDB48

H7

MDB57

D7

MDB59

C3

MDB63

C8

MDB62

C2

MDB56MDB44

A7

MDB61

A2

MDB58

B8

MDB60

A3

+1.5VGS

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

@

+1.5VGS

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

B B

+1.5VGS

1

CV283

CV282

2

A A

2

0.1U_0402_16V7K

1 CV284

CV284

2

0.1U_0402_16V7K

1

CV285

2

0.1U_0402_16V7K

1

CV286

2

0.1U_0402_16V7K

1

CV287

2

0.1U_0402_16V7K

1

CV288

2

0.1U_0402_16V7K

+1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS

RV182

4.99K_0402_1%

RV190

4.99K_0402_1%

1

CV289

2

0.1U_0402_16V7K

12

15mil 15mil 15mil 15mil 15mil 15mil 15mil 15mil

+VREFD_Q1_B +VREFD_Q2_B

12

1

CV274

2

0.1U_0402_16V7K

1

CV290

2

1 CV291

CV291

2

0.1U_0402_16V7K

CV292

2

0.1U_0402_16V7K

1

CV293

2

0.1U_0402_16V7K

RV183

4.99K_0402_1%

RV191

4.99K_0402_1%

1 CV294

CV294

2

0.1U_0402_16V7K

12

+VREFC_A1_B

1 CV275

CV275

2

0.1U_0402_16V7K

RV184

4.99K_0402_1%

RV192

4.99K_0402_1%

+1.5VGS

1 CV295

CV295

2

10U_0603_6.3V6M

12

1

CV296

2

10U_0603_6.3V6M

+VREFC_A2_B

1

CV276

2

0.1U_0402_16V7K

1

CV297

2

10U_0603_6.3V6M

1

CV298

2

RV185

4.99K_0402_1%

RV193

4.99K_0402_1%

12

1

CV277

2

0.1U_0402_16V7K

+1.5VGS +1.5VGS

1

CV299

CV300

2

1U_0402_6.3V6K

RV186

4.99K_0402_1%

RV194

4.99K_0402_1%

1

CV301

2

1U_0402_6.3V6K

12

1

CV302

2

1U_0402_6.3V6K

1

CV278

2

0.1U_0402_16V7K

1

CV303

2

1U_0402_6.3V6K

+VREFC_A3_B

1

CV304

2

RV187

4.99K_0402_1%

RV195

4.99K_0402_1%

1

CV305

2

1U_0402_6.3V6K

12

1

CV306

2

1U_0402_6.3V6K

1

CV279

2

0.1U_0402_16V7K

1

CV307

2

1U_0402_6.3V6K

+VREFD_Q3_B

1

CV308

2

RV188

4.99K_0402_1%

RV196

4.99K_0402_1%

1

CV309

2

1U_0402_6.3V6K

12

1

CV310

2

1U_0402_6.3V6K

1

CV280

2

0.1U_0402_16V7K

1

CV311

2

4.99K_0402_1%

+VREFC_A4_B

4.99K_0402_1%

1

CV312

2

1U_0402_6.3V6K

RV189

RV197

1 CV313

CV313

2

1U_0402_6.3V6K

12

1 CV314

CV314

2

1

CV281

2

0.1U_0402_16V7K

1 CV315

CV315

2

1U_0402_6.3V6K

+VREFD_Q4_B

1 CV316

CV316

2

1U_0402_6.3V6K

1

CV317

2

1U_0402_6.3V6K

1 CV318

CV318

2

1U_0402_6.3V6K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/11/28 2013/12/31

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

SCHEMATIC,MB LA-8863

Size Document Number Rev

C A

Date: Sheet of

4019IT

1

19 51Friday, March 23, 2012

5

Bits[5:4] Bits[3:1]

1 1 0 0 1 PS_1 PS_2 PS_3

D D

1 1 0 0 0

0 0 0 0 0

1 1 0 0 0

PS_0<16> PS_1<13> PS_2<13> PS_3<13>

C C

TS_FDO<13>

B B

+1.8VGS

@

CV103

0.01U_0402_25V7K

CH@

12

CV102

TS_FDO

@

12

CV101

0.01U_0402_25V7K

+3VGS

12

CV90

RV92

RV92 10K_0402_5%

10K_0402_5%

@

1 2

RV94

RV94 10K_0402_5%

10K_0402_5%

CH@

1 2

@

12

0.01U_0402_25V7K

Capacitor R_pu

NC

RV212

8.45K_0402_1%

8.45K_0402_1% @

@

RV213

4.75K_0402_1%

4.75K_0402_1% CH@

CH@

NC

680 nF

NC

12

NC 4.75k NC NC

RV207

8.45K_0402_1%

8.45K_0402_1% @

@

RV209

4.75K_0402_1%

4.75K_0402_1% CH@

CH@

Disable MLPS for Chelsea PRO

Enable MLPS for Chelsea PRO

4

R_pd

4.75k

12

8.45K_0402_1%

12

4.75K_0402_1%

2k8.45kPS_0

RV208

RV208 @

@

RV210

RV210 CH@

CH@

12

8.45K_0402_1%

12

GENLK_CLK<13>

GENLK_VSYNC<13>

+1.8VGS

RV211

RV211 CH@

CH@

RV203

2K_0402_1%

CH@

12

GENLK_CLK GENLK_VSYNC

3

@

CH@

12 12

RV107 10K_0402_5%

RV107 10K_0402_5% RV108 10K_0402_5%

RV108 10K_0402_5%

+3VGS

2

CONFIGURATION STRAPS

ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET

MLPS Bit

PS_0[3:1]

PS_0[4] N/A GENLK_VSYNC 1

PS_1[1] GPIO2

PS_1[2]

PS_1[3]

PS_1[4]

PS_1[5] PS_2[1]

PS_2[2]

PS_2[3]

PS_2[4] PS_2[5]

PS_3[3:1]

PS_0[5]

PS_3[4]

PS_3[5]

AUD[1] AUD[0]

STRAPS DESCRIPTION OF DEFAULT SETTINGS

ROMIDCFG(2:0)

STRAP_BIF_ GEN3_EN_A

STRAP_BIF_ CLK_PM_EN

N/A

TX_PWRS_ENB GPIO0

TX_DEEMPH_EN GPIO1

N/A

BIOS_ROM_EN GPIO_22_ROMCSB

VGA DIS GPIO9

N/A

AUD_PORT_CONN _PINSTRAP[0]

AUD_PORT_CONN _PINSTRAP[1]

AUD_PORT_CONN _PINSTRAP[2]

HSYNC VSYNC

AMD RESERVED CONFIGURATION STRAPS

ALLOW FOR PULLUP PADS FOR THESE STRAPS BUT DO NOT INSTALL RESISTOR. IF THESE GPIOS ARE USED, THEY MUST KEEP "LOW" AND NOT CONFLICT DURING RESET

Conventional Pin Strap Equivalent

GPIO[13:11]

Memory aperture size select

Must be 1 at rest. (Chelsea PRO)

PCIE Gen3 capability

GPIO8

PCIE clock power management capability.

Must be 0 at rest. (Chelsea PRO)

PCIE full TX output swing

PCIE transmitter de-emphsis enable

N/A

Reserved

Enable external BIOS ROM

VGA disable

N/A

Reserved

Audio-capable display outputs

N/A

H2SYNC GENERICC

GPIO21 GPIO2

0 0 0 All endpoints are usable 1 1 1 No usable endpoints.

AUD[1] AUD[0] 0 0 No audio function 0 1 Audio for DisplayPort and HDMI if dongle is detected 1 0 Audio for DisplayPort only 1 1 Audio for both DisplayPort and HDMI

GPIO8

0: 2.5GT/s 1: 5GT/s

0: Enable 1: Disable

1

RECOMMENDED SETTINGS 0= DO NOT INSTALL RESISTOR 1 = INSTALL 10K RESISTOR X = DESIGN DEPENDANT NA = NOT APPLICABLE

RECOMMENDED SETTINGS

256MB: 0 0 1

0: Half swing 1: Full swing

0: Disable 1: Enable

0 0 1

0

0GENLK_CLK

1

N/A

0

N/A

1 1 1

0 0

12

RV67

RV67 10K_0402_5%

10K_0402_5% @

@

12

RV68

RV68 10K_0402_5%

10K_0402_5% @

@

A A

12

RV69

RV69 10K_0402_5%

10K_0402_5% @

@

12

RV70

RV70 10K_0402_5%

10K_0402_5% @

@

12

RV71

RV71 10K_0402_5%

10K_0402_5% @

@

12

RV72

RV72 10K_0402_5%

10K_0402_5% @

@

VRAM_ID2 VRAM_ID1 VRAM_ID0

VRAM_ID2 <13> VRAM_ID1 <13> VRAM_ID0 <13>

5

4

VRAM Straps

Vendor VRAM_ID0 VRAM_ID1 VRAM_ID2

64MX16 (1G)

*

128M16 (2G)

*

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

H5TQ1G63DFR-11C

Hynix 1GB SA000041S20

K4W1G1646G-BC11

Samsung 1GB SA00004GS00

H5TQ2G63BFR-11C

Hynix 2GB SA00003YO00

K4W2G1646C-HC11

Samsung 2GB SA000047Q00

3

RV68

RV67

RV68

RV67

2011/11/28 2013/12/31

RV70

00

RV70

10

00

1

0

RV69

1

RV69

10

Compal Secret Data

RV72

Deciphered Date

0

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom A

Date: Sheet of

Compal Electronics, Inc.

SCHEMATIC,MB LA-8863

4019IT

20 51Friday, March 23, 2012

1

5

+3VS

30mil 30mil

@

1 2

RV277 0_0805_5%

+3VS_RT

+AVCC33

D D

+DVCC33

10U_0603_6.3V6M

Close to LV10

C C

1

2

10U_0603_6.3V6M

0.1U_0402_16V4Z

CV322

+SWR_V12

0.1U_0402_16V4Z

0.1U_0402_16V4Z 1

1

CV343

2

Close to LV9

22U_0805_6.3V6M

1

CV323

2

22U_0805_6.3V6M

CV344

1

CV324

2

60 mils

0.1U_0402_16V4Z

1

CV327

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z 1

CV321

2

Close to 5 pin

0.1U_0402_16V4Z

0.1U_0402_16V4Z 1

CV325

2

1

CV328

2

Power Consumption:

Pin5 (DPV33) < 20mA Pin 11 (DPV12) < 100mA Pin 15 (SWR_VCCK) < 100mA (layout trace > 60 mil) Pin 17 (SWR_LX) < 600mA (layout trace > 60 mil) Pin 18 (SWR_VDD) < 200mA (layout trace > 40 mil) Pin 22 (PVCC) < 50 mA Pin 43 (VCCK) < 50mA

0.1U_0402_16V4Z

0.1U_0402_16V4Z 1

CV326

2

Close to 22 pinClose to 18 pin

0.1U_0402_16V4Z

1

2

1

CV330

CV329

CV330

2

4

+3VS_RT

+SWR_V12

DP0_TXP0_C<7> DP0_TXN0_C<7>

DP0_TXP1_C<7> DP0_TXN1_C<7>

DP0_AUXP_C<7> DP0_AUXN_C<7>

LVDS_HPD<7>

APU_INVT_PWM<9>

CSCL CSDA

LV25

FBMA-L11-201209-221LMA30T_0805

LV24

FBMA-L11-201209-221LMA30T_0805

LV26

1 2

4.7UH_PG031B-4R7MS_1.1A_20%

DP0_TXP0_C DP0_TXN0_C

DP0_TXP1_C DP0_TXN1_C

DP0_AUXP_C DP0_AUXN_C

RV327 1K_0402_5%RV327 1K_0402_5%

1 2

RV280 12K_0402_1%RV280 12K_0402_1%

1 2

RV284 0_0402_5%

1 2

RV287 0_0402_5%

+DVCC33

12

+AVCC33

12

+SW_LX

LVDS_HPD_OUT

TP2TP2

MIIC_SCL MIIC_SDA

@

@ @

@

CIICSCL CIICSDA

40 mils

60 mils 60 mils

3

UV27

RTD2136S

22

PVCC

18

SWR_VDD

5

DP_V33

17

SWR_LX

15

SWR_VCCK

43

VCCK

11

DP_V12

7

LANE0P

8

LANE0N

9

LANE1P

10

LANE1N

4

AUX-CH_P

3

AUX-CH_N

1

DP_HPD

21

PWMIN

2

TESTMODE

12

DP_REXT

48

MIICSCL0

47

MIICSDA0

13

CIICSCL1

14

CIICSDA1

TXOC+

TXOC-

PWR

DP

OTHERS

TXO0+

TXO0-

TXO1+

TXO1-

TXO2+

TXO2-

TXO3+

TXO3-

TXEC+

TXEC-

LVDSGND

TXE0+

TXE0-

TXE1+

TXE1-

TXE2+

TXE2-

TXE3+

TXE3-

MIICSCL1

MIICSDA1

PANEL_VCC

PWMOUT

BL_EN

DP_GND

GND

RTD2136S-CG_QFN48_6X6

PAD

35 36

41 42

39 40

37 38

33 34

25 26

31 32

29 30

27 28

23 24

LCD_EDID_CLK

46

LCD_EDID_DATA

45

LCD_ENVDD

20

TL_INVT_PWM

19

EC_ENBKL

44

6

UTLGND

16

1 2

RV288 0_0402_5%RV288 0_0402_5%

49

2

LCD_TXCLK+ <22> LCD_TXCLK- <22>

LCD_TXOUT0+ <22> LCD_TXOUT0- <22>

LCD_TXOUT1+ <22> LCD_TXOUT1- <22>

LCD_TXOUT2+ <22> LCD_TXOUT2- <22>

LCD_TZCLK+ <22> LCD_TZCLK- <22>

LCD_TZOUT0+ <22> LCD_TZOUT0- <22>

LCD_TZOUT1+ <22> LCD_TZOUT1- <22>

LCD_TZOUT2+ <22> LCD_TZOUT2- <22>

LCD_EDID_CLK <22> LCD_EDID_DATA <22>

LCD_ENVDD <22> TL_INVT_PWM <22>

EC_ENBKL <36>

+DVCC33

MIIC_SCL MIIC_SDA

MIIC_SCL

LCD_EDID_DATA LCD_EDID_CLK

MIIC_SDA CSCL CSDA

1

EEROM

UV26 8 7 6 5

CAT24C64WI-GT3_SO8

Addr: A8 (1010 100X)

RV281 4.7K_0402_5%RV281 4.7K_0402_5%

1 2

RV282 4.7K_0402_5%RV282 4.7K_0402_5%

1 2

RV283 4.7K_0402_5%RV283 4.7K_0402_5%

1 2

RV285 4.7K_0402_5%RV285 4.7K_0402_5%

1 2

RV289 4.7K_0402_5%RV289 4.7K_0402_5%

1 2

VCC WP SCL SDA

+DVCC33

1 2

@UV26

@

A0 A1 A2

GND

RV278

@RV278

@

4.7K_0402_5%

RV279

4.7K_0402_5%

1 2 3 4

EEPROM

ROMLESS

+DVCC33

Close to LV11 Close to 11 pin

B B

Close to 43 pin

Pull-Low 100K

+3VS_RT

2

CSDA

2N7002KDWH_SOT363-6

CSCL

A A

2N7002KDWH_SOT363-6

1 2

RV290 0_0402_5%RV290 0_0402_5%

1 2

RV291 0_0402_5%RV291 0_0402_5%

5

4

61

QV28A

5

@QV28A

@

QV28B

2N7002KDWH_SOT363-6

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

EC_SMB_DA3

EC_SMB_CK3

34

@QV28B

@

3

EC_SMB_DA3 <36>

EC_SMB_CK3 <36>

Compal Secret Data

2011/11/28 2013/12/31

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Custom

Date: Sheet

EC_ENBKL

100K_0402_5%

Compal Electronics, Inc.

SCHEMATIC,MB LA-8863

RV295

4019IT

12

A

of

21 51Friday, March 23, 2012

1

21 51Friday, March 23, 2012

A

B

C

D

E

100_0805_5%

@

+LCD_VDD

R109

Q1A

LCD_ENVDD

12

100K_0402_5%

61

47K_0402_5%

LCD_TXOUT0+<21>

LCD_TXOUT0-<21>

LCD_TXOUT1+<21>

LCD_TXOUT1-<21>

1 1

LCD_TXOUT2+<21>

LCD_TXOUT2-<21> LCD_TXCLK+<21> LCD_TXCLK-<21>

LCD_EDID_CLK<21> LCD_EDID_DATA<21>

LCD_TXOUT0+ LCD_TXOUT0LCD_TXOUT1+ LCD_TXOUT1LCD_TXOUT2+

LCD_TXOUT2LCD_TXCLK+

LCD_TXCLK- LCDPWR_GATE LCD_EDID_CLK LCD_EDID_DATA

LCD_TZOUT0+<21>

LCD_TZOUT0-<21>

LCD_TZOUT1+<21>

LCD_TZOUT1-<21>

LCD_TZOUT2+<21>

LCD_TZOUT2-<21>

LCD_TZCLK+<21>

LCD_TZCLK-<21>

For RF

W=20mils

+3VS_LVDS_CAM

CAM@

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

1 2

R388 0_0603_5%

USB20_N4_R USB20_P4_R

INT_MIC_CLK INT_MIC_DATA

LCD_EDID_CLK LCD_EDID_DATA

LCD_TXOUT0LCD_TXOUT0+

LCD_TXOUT1LCD_TXOUT1+

LCD_TXOUT2LCD_TXOUT2+

LCD_TXCLKLCD_TXCLK+ LED_PWM DISPOFF#

1.5A

1 2

C263 47P_0402_50V8J

@

For RF

+3VS

JLVDS

2 2

JLVDS1

12

GND

11

GND

10

9 8 7 6 5 4 3 2 1

ACES_87036-1001-CP

3 3

@

LCD_TZOUT0-

10

LCD_TZOUT0+

9

LCD_TZOUT1-

8

LCD_TZOUT1+

7

LCD_TZOUT2-

6

LCD_TZOUT2+

5

LCD_TZCLK-

4

LCD_TZCLK+

3 2 1

31 32 33 34 35 36

STARC_107K30-000001-G2

GND1 GND2 GND3 GND4 GND5 GND6

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

+3VS

+LCD_INV

0.1U_0402_10V7K

0.1U_0402_10V7K C225

C225

1

C226

0.1U_0402_10V7K

2

LCD_TZOUT0+ LCD_TZOUT0LCD_TZOUT1+ LCD_TZOUT1LCD_TZOUT2+ LCD_TZOUT2LCD_TZCLK+ LCD_TZCLK-

@

C262 47P_0402_50V8J

1 2

CAM@

1 2

2 3

D84 AZ5125-02S.R7G_SOT23-3@ D84 AZ5125-02S.R7G_SOT23-3@

68P_0402_50V8J

1

INT_MIC_CLK <35> INT_MIC_DATA <35>

1

C227

4.7U_0805_10V4Z

2

1.5A

+LCD_INV

C234

1

C236

@

2

LCD_ENVDD<21>

+LCD_VDD

2A

+LCD_VDD

+3VS

1

C232

0.1U_0402_10V7K

2

L2

FBMA-L11-201209-221LMA30T_0805

1

C235

0.1U_0402_25V6

2

For EMI

1

C489

C268

C489

@

2

1

2

For RF

12

C490

2N7002KDWH_SOT363-6

C258 47P_0402_50V8J

1 2

B+

1

@

2

R108

2

5

R112

R112 100K_0402_5%

100K_0402_5%

1 2

LED_PWM

R135

DISPOFF#

+3VALW

12

0.047U_0402_25V7K

R133

1 2

68K_0402_5%

34

4700P_0402_25V7K

Q1B

Q1B 2N7002KDWH_SOT363-6

2N7002KDWH_SOT363-6

USB20_P4_R

USB20_N4_R

Reserve for EMI request

1 2

D19 RB751V40_SC76-2D19 RB751V40_SC76-2

12

1 2

D20 RB751V40_SC76-2D20 RB751V40_SC76-2

12

R730

R730 10K_0402_5%

10K_0402_5%

2

C228

G

1

2

1

C231

2

1 2

R78 0_0402_5%CAM@R78 0_0402_5%CAM@

@ L55

3

2

1 2

R96 0_0402_5%CAM@R96 0_0402_5%CAM@

@

3

2

WCM-2012-900T_0805

+3VS

W=80mils

S

Q17

Q17 AO3413_SOT23

AO3413_SOT23

D

1 3

+LCD_VDD

W=80mils

1

C233

0.1U_0402_10V7K

2

L55

4

1

12

R70

R70 300_0402_5%

300_0402_5% @

@

1

C287

C287 10P_0402_50V8J

10P_0402_50V8J @

@

2

Reserved for EHCI CRC errors

TL_INVT_PWM <21>

BKOFF# <36>

USB20_P4 <26>

USB20_N4 <26>

0.1U_0402_25V6

4 4

A

B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

0.1U_0402_25V6

2011/11/28 2013/12/31

C

0.1U_0402_25V6

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC,MB LA-8863

4019IT

22 51Friday, March 23, 2012

E

A

of

A

B

C

D

E

CRT CONNECTOR

1 1

For PowerXpress

UMA_CRT_R<27> UMA_CRT_G<27> UMA_CRT_B<27>

UMA_CRT_HSYNC<27> UMA_CRT_VSYNC<27>

UMA_CRT_CLK<27>

2 2

UMA_CRT_DATA<27>

1 2

R200 0_0402_5%R200 0_0402_5%

1 2

R204 0_0402_5%R204 0_0402_5%

1 2

R211 0_0402_5%R211 0_0402_5%

1 2

R213 0_0402_5%R213 0_0402_5%

1 2

R235 0_0402_5%R235 0_0402_5%

1 2

R236 0_0402_5%R236 0_0402_5%

1 2

R261 0_0402_5%R261 0_0402_5%

Close to CRT Connector

For Debug

@

VGA_CRT_R<13>

VGA_CRT_G<13>

VGA_CRT_B<13>

VGA_CRT_HSYNC<13> VGA_CRT_VSYNC<13>

VGA_CRT_CLK<13> VGA_CRT_DATA<13>

1 2

R178 0_0402_5%

@

1 2

R181 0_0402_5%

@

1 2

R167 0_0402_5%

@

1 2

R177 0_0402_5%

@

1 2

R179 0_0402_5%

@

1 2

R354 0_0402_5%

@

1 2

R353 0_0402_5%

CRT_R CRT_G

CRT_B CRT_HSYNC CRT_VSYNC

CRT_CLK CRT_DATA

CRT_R

CRT_G

CRT_B

CRT_HSYNC

CRT_VSYNC

CRT_CLK CRT_DATA

CRT_R CRT_G CRT_B

R138

R139

R140

12

C238

150_0402_1%

+CRT_VCC

1 2

C244 0.1U_0402_16V4ZC244 0.1U_0402_16V4Z

SN74AHCT1G125GW_SOT353-5

CRT_VSYNC

5

P

A2Y

G

3

1

4

OE#

U6

1

C239

2

2.2P_0402_50V8C

L3 NBQ100505T-800Y_0402L3 NBQ100505T-800Y_0402

1 2

L4 NBQ100505T-800Y_0402L4 NBQ100505T-800Y_0402

1 2

L5 NBQ100505T-800Y_0402L5 NBQ100505T-800Y_0402

1 2

1

C240

2

2.2P_0402_50V8C

+CRT_VCC

1 2

C247

0.1U_0402_16V4Z

SN74AHCT1G125GW_SOT353-5

1

C241

2

R141 10K_0402_5%R141 10K_0402_5%

1

5

P

4

OE#

A2Y

G

U7

3

1

C242

2

2.2P_0402_50V8C

12

D_CRT_HSYNCCRT_HSYNC

D_CRT_VSYNC

C243

1

2

2.2P_0402_50V8C

1 2

Close to CRT Connector

3 3

+3VS

2

Q205A

CRT_DATA

33P_0402_50V8K

C282

C282 @

@

1

2

1

C285

C285 33P_0402_50V8K

33P_0402_50V8K

2

@

Q205A

5

2N7002DW-T/R7_SOT363-6

Q205B

4

2N7002DW-T/R7_SOT363-6

61

3

470P_0402_50V8J

CRT_R_L CRT_G_L

CRT_B_L

L6 10_0402_5%L6 10_0402_5%

L7 10_0402_5%L7 10_0402_5%

+CRT_VCC

R153

4.7K_0402_5%

1 2

1

C284

2

@

+5VS +CRT_VCC_R +CRT_VCC

1

C245

C245 @

@

2

10P_0402_50V8J

R159

4.7K_0402_5%

1 2

CRT_DDC_CLKCRT_CLK

CRT_DDC_DAT

1

C283

C283 470P_0402_50V8J

470P_0402_50V8J

2

@

C246

C246 @

@

If=1A

D6

2 3

RB491D_SOT23-3

+CRT_VCC

HSYNC

VSYNC

1

2

10P_0402_50V8J

F1

40 mils

1

CRT_R_L CRT_DDC_DAT

CRT_G_L HSYNC

CRT_B_L VSYNC

CRT_DDC_CLK

+CRT_VCC

CRT_DDC_CLK HSYNC

+CRT_VCC

CRT_DDC_DAT

21

0.5A_8V_KMC3S050RY

0.1U_0402_16V4Z

T75 PADT75 PAD

T76 PADT76 PAD

CRT_R_L

CRT_G_L

D98

6

5

4

AZC099-04S.R7G_SOT23-6

D97

6

5

4

AZC099-04S.R7G_SOT23-6

1

C237

2

@

JCRT

6

11

1 7

12

2 8

13

3 9

14

4 10 15

5

SUYIN_070546FR015S251ZR

SUYIN_070546FR015S251ZR @

@

@D98

@

I/O4

VDD

GND

I/O3

@D97

@

I/O4

VDD

GND

I/O3

I/O2

I/O1

I/O2

I/O1

16

G

17

G

3

2

1

3

2

1

2/9: Add for ESD request

CRT_B_L

VSYNC

4 4

A

B

Security Classification

2011/11/28 2013/12/31

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/11/28 2013/12/31

C

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC,MB LA-8863

4019IT

E

of

23 51Friday, March 23, 2012

of

23 51Friday, March 23, 2012

of

23 51Friday, March 23, 2012

A

5

4

3

2

1

OE# A Y

L

D D

C310 0.1U_0402_16V7K HDMI@C310 0.1U_0402_16V7K HDMI@

UMA_HDMI_TXC+<7> UMA_HDMI_TXC-<7> UMA_HDMI_TX0+<7>

UMA_HDMI_TX0-<7>

UMA_HDMI_TX1+<7>

UMA_HDMI_TX1-<7>

UMA_HDMI_TX2+<7>

UMA_HDMI_TX2-<7>

C C

VGA_DVI_TXC-

KINGCORE WCM-2012HS-670T

VGA_DVI_TXC+

VGA_DVI_TXD0-

B B

A A

VGA_DVI_TXD0+

VGA_DVI_TXD1-

VGA_DVI_TXD1+

VGA_DVI_TXD2-

VGA_DVI_TXD2+

KINGCORE WCM-2012HS-670T

1 2

C321 0.1U_0402_16V7K HDMI@C321 0.1U_0402_16V7K HDMI@

1 2

C326 0.1U_0402_16V7K HDMI@C326 0.1U_0402_16V7K HDMI@

1 2

C313 0.1U_0402_16V7K HDMI@C313 0.1U_0402_16V7K HDMI@

1 2

C309 0.1U_0402_16V7K HDMI@C309 0.1U_0402_16V7K HDMI@

1 2

C314 0.1U_0402_16V7K HDMI@C314 0.1U_0402_16V7K HDMI@

1 2

C318 0.1U_0402_16V7K HDMI@C318 0.1U_0402_16V7K HDMI@

1 2

C322 0.1U_0402_16V7K HDMI@C322 0.1U_0402_16V7K HDMI@

1 2

@

1 2

R157 0_0402_5%

L8

HDMI@L8

HDMI@

1

4

@

1 2

R173 0_0402_5%

@

1 2

R175 0_0402_5%

L9

HDMI@L9

HDMI@

1

4

@

1 2

R180 0_0402_5%

@

1 2

R182 0_0402_5%

L10

HDMI@L10

HDMI@

1

4

@

1 2

R183 0_0402_5%

@

1 2

R187 0_0402_5%

L11

HDMI@L11

HDMI@

1

4

@

1 2

R188 0_0402_5%

HDMI_R_CK-

2

3

HDMI_R_CK+

HDMI_R_D0-

2

3

HDMI_R_D0+

HDMI_R_D1-

2

3

HDMI_R_D1+

HDMI_R_D2-

2

3

HDMI_R_D2+

VGA_DVI_TXC+

VGA_DVI_TXCVGA_DVI_TXD0+

VGA_DVI_TXD0-

VGA_DVI_TXD1+

VGA_DVI_TXD1VGA_DVI_TXD2+ VGA_DVI_TXD2-

UMA_HDMI_CLK<7>

UMA_HDMI_DATA<7>

D95

@

HDMI_R_D0+ HDMI_R_D0-

HDMI_R_D2+

HDMI_R_D2-

HDMI_R_D1+

HDMI_R_D1-

HDMI_R_CK+

HDMI_R_CK-

AZ1045-04F_DFN2510P10E-10-9

@

1

2

4

4 5

3

8

AZ1045-04F_DFN2510P10E-10-9

D94

1

2

4

4 5

3

8

10

10 9

9 7

7 65

65

@

10

9

8

7

65

6

2/9: Add for ESD request

2

3 1

SGD

BSH111_SOT23-3

HDMI_R_D0+

9

HDMI_R_D0-

8

HDMI_R_D2+

7

HDMI_R_D2-

6

HDMI_R_D1+ HDMI_R_D1- HDMI_SDATAHDMI_HPD_C

HDMI_R_CK+

HDMI_R_CK-

+HDMI_5V_OUT

Change R184 and R185 from 2K to 4.7K for HDMI detect issue on preMP

+3VS

3 1

SGD

BSH111_SOT23-3

Q19

HDMI@

HDMI_R_CK+ HDMI_R_CKHDMI_R_D1HDMI_R_D1+ HDMI_R_D0+ HDMI_R_D0HDMI_R_D2HDMI_R_D2+

+5VS

4.7K_0402_5%

2

+HDMI_5V_OUT

12

R184

HDMI@

Q18

HDMI@

1 2

R195 604_0402_1%

R195 604_0402_1% R197 604_0402_1%

R197 604_0402_1% R198 604_0402_1%

R198 604_0402_1% R202 604_0402_1%

R202 604_0402_1% R201 604_0402_1%

R201 604_0402_1% R203 604_0402_1%

R203 604_0402_1% R205 604_0402_1%

R205 604_0402_1% R206 604_0402_1%

R206 604_0402_1%

1 2 1 2 1 2 1 2 1 2 1 2 1 2

+5VS

D96

6

I/O4

5

VDD

4

I/O3

AZC099-04S.R7G_SOT23-6

HDMI@

HDMI@ HDMI@

HDMI@

12

R185

4.7K_0402_5%

4.7K_0402_5% HDMI@

HDMI@

HDMI_SCLK

HDMI_SDATA

2

G

@D96

@

I/O2

GND

I/O1

13

D

S

2/9: Add for ESD request

Q24

Q24 2N7002_SOT23-3

2N7002_SOT23-3 HDMI@

HDMI@

3

2

HDMI_SCLK

1

+HDMI_5V_OUT

2

C264

0.1U_0402_16V4Z

0.1U_0402_16V4Z HDMI@

HDMI@

5

1

P

A2Y

G

74AHCT1G125GW_SOT353-5

74AHCT1G125GW_SOT353-5 HDMI@

HDMI@

3

1

U9

OE#

Add C201 and C214 for EMI request on PVT

HDMI@

D53

2 1

PMEG2010AEH_SOD123

1

C201

C201 560P_0402_50V7K

560P_0402_50V7K @

@

2

+HDMI_5V_OUT_F

0.5A_8V_KMC3S050RY

HDMI Connector

+HDMI_5V_OUT

HDMI_HPD_C

HDMI_SDATA HDMI_SCLK

HDMI_R_CK-

HDMI_R_CK+

HDMI_R_D0-

HDMI_R_D0+

HDMI_R_D1-

HDMI_R_D1+

HDMI_R_D2-

HDMI_R_D2+

L H

HDMI_HPD

4

HDMI_HPD

HDMI@

LL HH XZ

HDMI@

HDMI@ R145

R145

1 2

1K_0402_5%

100K_0402_5%

HDMI@

R571

2.2K_0402_5%

F2

21

1

C259

C259 HDMI@

HDMI@

2

JHDMI

19

HP_DET

18

+5V

17

DDC/CEC_GND

16

SDA

15

SCL

14

Reserved

13

CEC

12

CK-

11

CK_shield

10

CK+

9

D0-

8

D0_shield

7

D0+

6

D1-

5

D1_shield

4

D1+

3

D2-

2

D2_shield

1

D2+

HONGL_13-13201904CP

HDMI_HPD_CHDMI_HPD_U

R186

1 2

12

1

C214

C214 560P_0402_50V7K

560P_0402_50V7K

0.1U_0402_16V4Z

0.1U_0402_16V4Z @

@

2

@JHDMI

@

GND GND GND GND

2

C265

0.1U_0402_16V4Z

0.1U_0402_16V4Z HDMI@

HDMI@

1

+3VS

HDMI_HPD <7>

+HDMI_5V_OUT+5VS

20 21 22 23

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/11/28 2013/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC,MB LA-8863

4019IT

24 51Friday, March 23, 2012

1

A

of

A

APU_PCIE_RST#_R LPC_RST#_R

C202 0.1U_0402_16V7KC202 0.1U_0402_16V7K

UMI_MTX_C_FRX_P0<5> UMI_MTX_C_FRX_N0<5> UMI_MTX_C_FRX_P1<5> UMI_MTX_C_FRX_N1<5> UMI_MTX_C_FRX_P2<5> UMI_MTX_C_FRX_N2<5> UMI_MTX_C_FRX_P3<5>

1 1

2 2

UMI_MTX_C_FRX_N3<5> UMI_FTX_C_MRX_P0<5>

UMI_FTX_C_MRX_N0<5> UMI_FTX_C_MRX_P1<5> UMI_FTX_C_MRX_N1<5> UMI_FTX_C_MRX_P2<5> UMI_FTX_C_MRX_N2<5> UMI_FTX_C_MRX_P3<5> UMI_FTX_C_MRX_N3<5>

+PCIE_VDDR_FCH

+1.1VS_CKVDD

SS

APU Display

1 2

C203 0.1U_0402_16V7KC203 0.1U_0402_16V7K

1 2

C204 0.1U_0402_16V7KC204 0.1U_0402_16V7K

1 2

C209 0.1U_0402_16V7KC209 0.1U_0402_16V7K

1 2

C210 0.1U_0402_16V7KC210 0.1U_0402_16V7K

1 2

C211 0.1U_0402_16V7KC211 0.1U_0402_16V7K

1 2

C213 0.1U_0402_16V7KC213 0.1U_0402_16V7K

1 2

C212 0.1U_0402_16V7KC212 0.1U_0402_16V7K

1 2

R220 590_0402_1%R220 590_0402_1%

1 2

R221 2K_0402_1%R221 2K_0402_1%

1 2

R228 2K_0402_1%R228 2K_0402_1%

1 2

Input from external clock generator NC for internal clock generator

APU_DISP_CLKP<7> APU_DISP_CLKN<7>

UMI_MTX_FRX_P0 UMI_MTX_FRX_N0 UMI_MTX_FRX_P1 UMI_MTX_FRX_N1 UMI_MTX_FRX_P2 UMI_MTX_FRX_N2 UMI_MTX_FRX_P3 UMI_MTX_FRX_N3

UMI_FTX_C_MRX_P0 UMI_FTX_C_MRX_N0 UMI_FTX_C_MRX_P1 UMI_FTX_C_MRX_N1 UMI_FTX_C_MRX_P2 UMI_FTX_C_MRX_N2 UMI_FTX_C_MRX_P3 UMI_FTX_C_MRX_N3

PCIE_CALRP PCIE_CALRN

CLK_CALRN

APU_DISP_CLKP APU_DISP_CLKN

NSS

APU GPU

WLAN

SS

LAN

3 3

FCH_RTCX1_R<31>

FCH_X1_R<31>

APU_CLKP<7> APU_CLKN<7>

CLK_PCIE_VGA<12> CLK_PCIE_VGA#<12>

CLK_WLAN<31> CLK_WLAN#<31>

CLK_LAN<32> CLK_LAN#<32>

Place close to Y2

GCLK@

1 2

R207 0_0402_5%

GCLK@

1 2

R208 0_0402_5%

Place close to Y1

C220 27P_0402_50V8JNOGCLK@ C220 27P_0402_50V8JNOGCLK@

1 2

25MHZ_20PF_7A25000012

1 2

C230 27P_0402_50V8JNOGCLK@ C230 27P_0402_50V8JNOGCLK@

4 4

C248 18P_0402_50V8JNOGCLK@ C248 18P_0402_50V8JNOGCLK@

1 2

20M_0402_5%

NOGCLK@

1 2

C249 18P_0402_50V8JNOGCLK@ C249 18P_0402_50V8JNOGCLK@

Change C248/C249 to 18P for RTC issue on pre-MP

A

Y1

NOGCLK@

R230

12

1 2

APU_CLKP APU_CLKN

CLK_PCIE_VGA CLK_PCIE_VGA#

CLK_WLAN CLK_WLAN#

CLK_LAN CLK_LAN#

32K_X1

25M_X1

R229

R229 1M_0402_5%

1M_0402_5% NOGCLK@

NOGCLK@

Y2

32.768KHZ_12.5P_1TJF125DP1A000D

32.768KHZ_12.5P_1TJF125DP1A000D NOGCLK@

NOGCLK@

25M_X1

25M_X2

B

32K_X1

32K_X2

B

AD5

AE30 AE32 AD33 AD31 AD28 AD29 AC30 AC32

AB33 AB31 AB28 AB29

AF29 AF31

W30

W32 AB26 AB27 AA24 AA23

AA27 AA26

W27

W26

W24

W23

M23 M24

M27 M26

AE2

Y33 Y31 Y28 Y29

V33 V31

V27 V26

F27

G30 G28

R26 T26

H33 H31

T24 T23

J30

K29 H27

H28

J27

K26 F33

F31 E33

E31

N25 N26

R23 R24

N27 R27

J26

C31

C33

U1A

PCIE_RST# A_RST#

UMI_TX0P UMI_TX0N UMI_TX1P UMI_TX1N UMI_TX2P UMI_TX2N UMI_TX3P UMI_TX3N

UMI_RX0P UMI_RX0N UMI_RX1P UMI_RX1N UMI_RX2P UMI_RX2N UMI_RX3P UMI_RX3N

PCIE_CALRP PCIE_CALRN

GPP_TX0P GPP_TX0N GPP_TX1P GPP_TX1N GPP_TX2P GPP_TX2N GPP_TX3P GPP_TX3N

GPP_RX0P GPP_RX0N GPP_RX1P GPP_RX1N GPP_RX2P GPP_RX2N GPP_RX3P GPP_RX3N

CLK_CALRN

PCIE_RCLKP PCIE_RCLKN

DISP_CLKP DISP_CLKN

DISP2_CLKP DISP2_CLKN

APU_CLKP APU_CLKN

SLT_GFX_CLKP SLT_GFX_CLKN

GPP_CLK0P GPP_CLK0N

GPP_CLK1P GPP_CLK1N

GPP_CLK2P GPP_CLK2N

GPP_CLK3P GPP_CLK3N

GPP_CLK4P GPP_CLK4N

GPP_CLK5P GPP_CLK5N

GPP_CLK6P GPP_CLK6N

GPP_CLK7P GPP_CLK7N

GPP_CLK8P GPP_CLK8N

14M_25M_48M_OSC

25M_X1

25M_X2

HUDSON-M3_FCBGA656

HUDSON-2

PCI CLKS

PCICLK4/14M_OSC/GPO39

PCI EXPRESS INTERFACES

PCI INTERFACE

REQ2#/CLK_REQ8#/GPIO41 REQ3#/CLK_REQ5#/GPIO42

GNT2#/SD_LED/GPO45

GNT3#/CLK_REQ7#/GPIO46

CLOCK GENERATOR

LPCAPUS5 PLUS

LDRQ1#/CLK_REQ6#/GPIO49

C

HUDM3R3@

PCICLK0 PCICLK1/GPO36 PCICLK2/GPO37 PCICLK3/GPO38

PCIRST#

AD0/GPIO0 AD1/GPIO1 AD2/GPIO2 AD3/GPIO3 AD4/GPIO4 AD5/GPIO5 AD6/GPIO6 AD7/GPIO7 AD8/GPIO8

AD9/GPIO9 AD10/GPIO10 AD11/GPIO11 AD12/GPIO12 AD13/GPIO13 AD14/GPIO14 AD15/GPIO15 AD16/GPIO16 AD17/GPIO17 AD18/GPIO18 AD19/GPIO19 AD20/GPIO20 AD21/GPIO21 AD22/GPIO22 AD23/GPIO23 AD24/GPIO24 AD25/GPIO25 AD26/GPIO26 AD27/GPIO27 AD28/GPIO28 AD29/GPIO29 AD30/GPIO30 AD31/GPIO31

CBE0# CBE1# CBE2# CBE3#

FRAME#

DEVSEL#

IRDY#

TRDY#

PAR

STOP# PERR# SERR#

REQ0#

REQ1#/GPIO40

GNT0#

GNT1#/GPO44

CLKRUN#

LOCK#

INTE#/GPIO32 INTF#/GPIO33

INTG#/GPIO34

INTH#/GPIO35

LPCCLK0 LPCCLK1

LAD0 LAD1 LAD2 LAD3

LFRAME#

LDRQ0#

SERIRQ/GPIO48

DMA_ACTIVE#

PROCHOT#

APU_PG

LDT_STP#

APU_RST#

S5_CORE_EN

RTCCLK

INTRUDER_ALERT#

VDDBT_RTC_G

32K_X1

32K_X2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PCI_CLK1

AF1 AF5

PCI_CLK3

AG2

PCI_CLK4

AF6 AB5

AJ3 AL5 AG4 AL6 AH3 AJ5 AL1 AN5 AN6 AJ1 AL8 AL3 AM7 AJ6 AK7 AN8 AG9 AM11 AJ10 AL12 AK11 AN12 AG12

PCI_AD23

AE12

PCI_AD24

AC12

PCI_AD25

AE13

PCI_AD26

AF13

PCI_AD27

AH13

VGA_PWRGD_R

AH14 AD15

GPIO30

AC15

GPIO31

AE16 AN3 AJ8 AN10 AD12 AG10 AK9 AL10 AF10 AE10 AH1 AM9 AH8 AG15 AG13 AF15 AM17 AD16 AD13 AD21 AK17 AD19 AH9

AF18 AE18 AC16 AD18

LPC_CLK0

B25

LPC_CLK1

D25

LPC_AD0

D27

LPC_AD1

C28

LPC_AD2

A26

LPC_AD3

A29

LPC_FRAME#

A31 B27 AE27

SERIRQ

AE19

DMA_ACTIVE#

G25

APU_PROCHOT#

E28

APU_PWRGD

E26 G26

APU_RST#

F26

H7

RTC_CLK_R

F1 F3

+RTCVCC_R

E6

32K_X1

G2

32K_X2

G4

C

PCI_CLK0

AF3

R257 22_0402_5%R257 22_0402_5%

1 2

PCI_CLK1 <28> PCI_CLK3 <28>

PCI_CLK4 <28>

RV61 0_0402_5%@RV61 0_0402_5%@

+3VGS

PXS_RST# APU_PCIE_RST#

R227 0_0402_5%@R227 0_0402_5%@

1 2

R252 0_0402_5%@R252 0_0402_5%@

1 2

2

B

1

A

PCI_AD23 <28> PCI_AD24 <28> PCI_AD25 <28> PCI_AD26 <28> PCI_AD27 <28>

@

1 2

R254 0_0402_5%

Change to GPIO51

R255 22_0402_5%R255 22_0402_5%

1 2

R258 22_0402_5%R258 22_0402_5%

1 2

T25T25

1 2

R260 0_0402_5%R260 0_0402_5%

20 mils

C250

0.1U_0402_16V4Z

Compal Secret Data

2011/11/28 2013/12/31

Compal Secret Data

Strap

12

C251 0.1U_0402_16V4ZC251 0.1U_0402_16V4Z

1 2

5

UV13

P

4

Y

G

3

MC74VHC1G08DFT2G SC70 5P

Strap

PXS_PWREN <14,26,44,49>

1 2

120_0402_5%

1

C252

C252 1U_0402_6.3V6K

1U_0402_6.3V6K

2

Deciphered Date

D

CLK_PCI_TPM_FCH <33>

APU_PCIE_RST#_R

LPC_RST#_R

VGA_PWRGD <26,49>

PXS_RST# <26>

CLK_PCI_EC <28,36> CLK_PCI_DDR <28,37>

LPC_AD0 <33,36,37> LPC_AD1 <33,36,37> LPC_AD2 <33,36,37> LPC_AD3 <33,36,37> LPC_FRAME# <33,36,37>

SERIRQ <33,36>

DMA_ACTIVE# <7> APU_PROCHOT# <7> APU_PWRGD <7,47>

APU_RST# <7>

RTC_CLK <28,36>

R271

CMOS Setting Place under DDR Door

D

+RTCVCC

12

GPU_RST# <12>

Strap

R277

1 2

120_0402_5%

JCMOS@JCMOS @

E

R225 33_0402_5%R225 33_0402_5%

1 2

150P_0402_50V8J

R226 33_0402_5%R226 33_0402_5%

1 2

150P_0402_50V8J

PCIE_RST# is for PCIE devices on APU

1

C221

2

R223

R223 100K_0402_5%

100K_0402_5% @

@

1 2

A_RST# is for LPC devices

1

R224

C222

R224 100K_0402_5%

100K_0402_5% @

@

2

1 2

R337 10K_0402_5%R337 10K_0402_5%

1 2

R340 10K_0402_5%R340 10K_0402_5%

GPIO30

GPIO31

APU_PCIE_RST# <31,32>

LPC_RST# <33,36,37>

1 2

R332 10K_0402_5%

1 2

R339 10K_0402_5%

Function GPIO30 GPIO31

PowerXpress

00 Reserved Discrete

UMA

+RTCBATT_D +RTCBATT

1

C256

2

+RTCBATT

11

12

NOGCLK@D14

NOGCLK@

D14

0.1U_0402_10V7K

0.1U_0402_10V7K RB751V-40_SOD323-2

RB751V-40_SOD323-2

If use GCLK, please delete D14

DMA active. The FCH drives the DMA_ACTIVE# to APU to notify DMA activity. This will cause the APU to reestablish the UMI link quicker.

S5_CORE_EN is for S5+ mode used to turn off +1.1VALW and +3VALW of FCH on S5+ mode

+RTCBATT_D

R268

+RTCBATT_R

R268

1 2 1K_0402_5%

1K_0402_5%

1

C295

0.1U_0402_16V4Z

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC,MB LA-8863

4019IT

E

@

10 01

12

D13

D13 RB751V-40_SOD323-2

RB751V-40_SOD323-2

+3VL

25 51Friday, March 23, 2012

+3VS

A

of

A

B

C

D

E

U1D

R21610K_0402_5% R21610K_0402_5%

12

U1D

AB6

PCIE_RST2#/PCI_PME#/GEVENT4#

R2

RI#/GEVENT22#

W7

SPI_CS3#/GBE_STAT1/GEVENT21#

T3

SLP_S3#

W2

SLP_S5#

J4

PWR_BTN#

N7

PWR_GOOD

T9

TEST0

T10

TEST1/TMS

V9

TEST2

AE22

GA20IN/GEVENT0#

AG19

KBRST#/GEVENT1#

R9

LPC_PME#/GEVENT3#

C26

LPC_SMI#/GEVENT23#

T5

LPC_PD#/GEVENT5#

U4

SYS_RESET#/GEVENT19#

K1

WAKE#/GEVENT8#

V7

IR_RX1/GEVENT20#

R10

THRMTRIP#/SMBALERT#/GEVENT2#

AF19

WD_PWRGD

U2

RSMRST#

AG24

CLK_REQ4#/SATA_IS0#/GPIO64

AE24

CLK_REQ3#/SATA_IS1#/GPIO63

AE26

SMARTVOLT1/SATA_IS2#/GPIO50

AF22

CLK_REQ0#/SATA_IS3#/GPIO60

AH17

SATA_IS4#/FANOUT3/GPIO55

AG18

SATA_IS5#/FANIN3/GPIO59

AF24

SPKR/GPIO66

AD26

SCL0/GPIO43

AD25

SDA0/GPIO47

T7

SCL1/GPIO227

R7

SDA1/GPIO228

AG25

CLK_REQ2#/FANIN4/GPIO62

AG22

CLK_REQ1#/FANOUT4/GPIO61

J2

IR_LED#/LLB#/GPIO184

AG26

SMARTVOLT2/SHUTDOWN#/GPIO51

V8

DDR3_RST#/GEVENT7#/VGA_PD

W8

GBE_LED0/GPIO183

Y6

SPI_HOLD#/GBE_LED1/GEVENT9#

V10

GBE_LED2/GEVENT10#

AA8

GBE_STAT0/GEVENT11#

AF25

CLK_REQG#/GPIO65/OSCIN/IDLEEXIT#

M7

BLINK/USB_OC7#/GEVENT18#

R8

USB_OC6#/IR_TX1/GEVENT6#

T1

USB_OC5#/IR_TX0/GEVENT17#

P6

USB_OC4#/IR_RX0/GEVENT16#

F5

USB_OC3#/AC_PRES/TDO/GEVENT15#

P5

USB_OC2#/TCK/GEVENT14#

J7

USB_OC1#/TDI/GEVENT13#

T8

USB_OC0#/SPI_TPM_CS#/TRST#/GEVENT12#

AB3

AZ_BITCLK

AB1

AZ_SDOUT

AA2

AZ_SDIN0/GPIO167

Y5

AZ_SDIN1/GPIO168

Y3

AZ_SDIN2/GPIO169

Y1

AZ_SDIN3/GPIO170

AD6

AZ_SYNC

AE4

AZ_RST#

K19

PS2_DAT/SDA4/GPIO187

J19

PS2_CLK/CEC/SCL4/GPIO188

J21

SPI_CS2#/GBE_STAT2/GPIO166

D21

PS2KB_DAT/GPIO189

C20

PS2KB_CLK/GPIO190

D23

PS2M_DAT/GPIO191

C22

PS2M_CLK/GPIO192

F21

KSO_0/GPIO209

E20

KSO_1/GPIO210

F20

KSO_2/GPIO211

A22

KSO_3/GPIO212

E18

KSO_4/GPIO213

A20

KSO_5/GPIO214

J18

KSO_6/GPIO215

H18

KSO_7/GPIO216

G18

KSO_8/GPIO217

B21

KSO_9/GPIO218

K18

KSO_10/GPIO219

D19

KSO_11/GPIO220

A18

KSO_12/GPIO221

C18

KSO_13/GPIO222

B19

KSO_14/GPIO223

B17

KSO_15/GPIO224

A24

KSO_16/GPIO225

D17

KSO_17/GPIO226

HUDSON-M3_FCBGA656

HUDSON-2

EMBEDDED CTRL

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

USBCLK/14M_25M_48M_OSC

USB MISCUSB 1.1USB 2.0USB 3.0

USB OC GPIO ACPI / WAKE UP EVENTSHD AUDIO

EC_PWM0/EC_TIMER0/GPIO197 EC_PWM1/EC_TIMER1/GPIO198

EC_PWM2/EC_TIMER2/WOL_EN/GPIO199

EC_PWM3/EC_TIMER3/GPIO200

2011/11/28 2013/12/31

PCIE_RST2# is for PCIE devices on FCH

T50T50

12

EC_LID_OUT#

T57T57 SLP_S3# SLP_S5# PBTN_OUT# FCH_PWRGD

TEST0 TEST1 TEST2

GATEA20 KB_RST#

EC_SCI# EC_SMI#

T31T31 FCH_PCIE_WAKE#

T55T55 H_THERMTRIP# WD_PWRGD

EC_RSMRST#

CLKREQ_LAN#

FCH_SPKR FCH_SCLK0 FCH_SDATA0 FCH_SCLK1 FCH_SDATA1 CLKREQ_WLAN#

T30T30

LAN_EN

T54T54

ODD_DA#_FCH

T59T59 ODD_PLUGIN#

T58T58

T56T56 USB_OC1# USB_OC0#

HDA_BITCLK HDA_SDOUT AZ_SDIN0_HD AZ_SDIN1_HD AZ_SDIN2_HD AZ_SDIN3_HD HDA_SYNC HDA_RST#

T26T26

T27T27

T33T33 T32T32 T35T35 T34T34 T37T37 T36T36 T38T38 T39T39 T45T45 T44T44 T46T46 T47T47 T41T41 T40T40 T42T42 T43T43 T49T49 T48T48

+3VALW_FCH

EC_PXCONTROL <36>

B

EC_LID_OUT#<36>

+3VALW_FCH

1 1

2 2

VGA_PD: Support CRT power saving L: MLDAC power on H: MLDAC power off

USB_OC1# is for left USB3.0 ports USB_OC0# is for right USB2.0 ports

3 3

+3VALW_FCH

1 2

R278 10K_0402_5%

1 2

R272 10K_0402_5%

1 2

R276 10K_0402_5%R276 10K_0402_5%

1 2

R318 10K_0402_5%R318 10K_0402_5%

1 2

R319 10K_0402_5%R319 10K_0402_5%

1 2

R288 10K_0402_5%R288 10K_0402_5%

1 2

R289 10K_0402_5%R289 10K_0402_5%

1 2

R292 10K_0402_5%R292 10K_0402_5%

1 2

R293 10K_0402_5%

4 4

R293 10K_0402_5% R280 100K_0402_5%R280 100K_0402_5%

1 2

R324 10K_0402_5%

1 2

R325 10K_0402_5%

1 2

R290 1K_0402_5%

1 2

R331 10K_0402_5%

1 2

R333 10K_0402_5%

1 2

R335 10K_0402_5%

For FCH internal debug use (Internal 10K pull-down)

@

1 2

R273 2.2K_0402_5%

@

1 2

R274 2.2K_0402_5%

@

1 2

R275 2.2K_0402_5%

@

@ @

@

12

@

@ @

@

A

TEST0 TEST1 TEST2

H_THERMTRIP#<7>

CLKREQ_LAN#<32>

SM Bus 0-->S0 PWR domain SM Bus 1-->S5 PWR domain (for ASF device only)

PEG_CLKREQ#<13>

AZ_BITCLK_HD<35> AZ_SDOUT_HD<35>

AZ_SDIN0_HD<35>

AZ_SYNC_HD<35> AZ_RST_HD#<35>

H_THERMTRIP# EC_LID_OUT# FCH_PCIE_WAKE# USB_OC0# USB_OC1# FCH_SCLK1 FCH_SDATA1 PXS_PWREN

PXS_PWREN EC_RSMRST# HDA_BITCLK AZ_SDIN0_HD PXS_RST# AZ_SDIN1_HD AZ_SDIN2_HD AZ_SDIN3_HD

+3VS

R320 33_0402_5%R320 33_0402_5% R321 33_0402_5%R321 33_0402_5%

R322 33_0402_5%R322 33_0402_5% R323 33_0402_5%R323 33_0402_5%

PXS_RST#<25> PXS_PWREN<14,25,44,49>

1 2

R286 2.2K_0402_5%R286 2.2K_0402_5%

1 2

R287 2.2K_0402_5%R287 2.2K_0402_5%

@

1 2

R291 8.2K_0402_5%

@

1 2

R284 8.2K_0402_5%

2N7002KDWH_SOT363-6

PXS_PWREN

SLP_S3#<36>

SLP_S5#<36> PBTN_OUT#<36> FCH_PWRGD<36>

GATEA20<36> KB_RST#<36>

EC_SCI#<36> EC_SMI#<36>

FCH_PCIE_WAKE#<32>

1 2

+3VS

R279 10K_0402_5%R279 10K_0402_5% EC_RSMRST#<36>

FCH_SPKR<35> FCH_SCLK0<10,11,31> FCH_SDATA0<10,11,31>

CLKREQ_WLAN#<31>

VGA_PWRGD<25,49>

LAN_EN<32>

R295 0_0402_5%R295 0_0402_5%

1 2

R113 100K_0402_5%@R113 100K_0402_5%@

ODD_PLUGIN#<30>

USB_OC1#<34> USB_OC0#<30>

1 2 1 2

PXS_PWREN

FCH_SCLK0 FCH_SDATA0 CLKREQ_WLAN# CLKREQ_LAN#

Q5530A

6 1

Q5530B

Q5530B 2N7002KDWH_SOT363-6

2N7002KDWH_SOT363-6

34

EC_PXCONTROL

5

2

HUDM3R3@

USB_RCOMP

USB_FSD1P/GPIO186

USB_FSD1N

USB_FSD0P/GPIO185

USB_FSD0N

USB_HSD13P USB_HSD13N

USB_HSD12P USB_HSD12N

USB_HSD11P USB_HSD11N

USB_HSD10P USB_HSD10N

USB_HSD9P USB_HSD9N

USB_HSD8P USB_HSD8N

USB_HSD7P USB_HSD7N

USB_HSD6P USB_HSD6N

USB_HSD5P USB_HSD5N

USB_HSD4P USB_HSD4N

USB_HSD3P USB_HSD3N

USB_HSD2P USB_HSD2N

USB_HSD1P USB_HSD1N

USB_HSD0P USB_HSD0N

USBSS_CALRP USBSS_CALRN

USB_SS_TX3P USB_SS_TX3N

USB_SS_RX3P

USB_SS_RX3N

USB_SS_TX2P USB_SS_TX2N

USB_SS_RX2P

USB_SS_RX2N

USB_SS_TX1P USB_SS_TX1N

USB_SS_RX1P

USB_SS_RX1N

USB_SS_TX0P USB_SS_TX0N

USB_SS_RX0P

USB_SS_RX0N

SCL2/GPIO193

SDA2/GPIO194 SCL3_LV/GPIO195 SDA3_LV/GPIO196

KSI_0/GPIO201

KSI_1/GPIO202

KSI_2/GPIO203

KSI_3/GPIO204

KSI_4/GPIO205

KSI_5/GPIO206

KSI_6/GPIO207

KSI_7/GPIO208

Compal Secret Data

G8

USB_RCOMP

B9 H1

H3 H6

H5 H10

G10 K10

J12

USB20_P11

G12

USB20_N11

F12

USB20_P10

K12

USB20_N10

K13 B11

D11 E10

F10 C10

A10 H9

G9 A8

C8

USB20_P4

F8

USB20_N4

E8

USB20_P3

C6

USB20_N3

A6

USB20_P2

C5

USB20_N2

A5

USB20_P1

C1

USB20_N1

C3

USB20_P0

E1

USB20_N0

E3

USBSS_CALRP

C16

USBSS_CALRN

A16 A14

C14 C12

A12 D15

B15 E14

F14

USB30_TX1P

F15

USB30_TX1N

G15

USB30_RX1P

H13

USB30_RX1N

G13

USB30_TX0P

J16

USB30_TX0N

H16

USB30_RX0P

J15

USB30_RX0N

K15

R326 10K_0402_5%R326 10K_0402_5%

H19

R328 10K_0402_5%R328 10K_0402_5%

G19

R338 10K_0402_5%R338 10K_0402_5%

G22

R343 10K_0402_5%R343 10K_0402_5%

G21 E22 H22

EC_PWM2

J22 H21

K21 K22 F22 F24 E24 B23 C24 F18

Deciphered Date

R329 11.8K_0402_1%R329 11.8K_0402_1%

1 2

USB20_P11 <34> USB20_N11 <34>

USB20_P10 <34> USB20_N10 <34>

USB20_P4 <22> USB20_N4 <22>

USB20_P3 <31> USB20_N3 <31>

USB20_P2 <33> USB20_N2 <33>

USB20_P1 <30> USB20_N1 <30>

USB20_P0 <30> USB20_N0 <30>

R330 1K_0402_1%R330 1K_0402_1%

1 2

R334 1K_0402_1%R334 1K_0402_1%

1 2

USB30_TX1P <34> USB30_TX1N <34>

USB30_RX1P <34> USB30_RX1N <34>

USB30_TX0P <34> USB30_TX0N <34>

USB30_RX0P <34> USB30_RX0N <34>

1 2 1 2 1 2 1 2

EC_PWM2 <28>

Place R425 and C363 close to FCH for ESD

ODD_DA#_FCH

R425 0_0402_5%

1

C363

0.1U_0402_16V4Z

0.1U_0402_16V4Z @

@

2

D

@

1 2

Hudson-M2/M3 OHCI (DEV-20, FUN-5)

Hudson-M2 OHCI (DEV-22, FUN-0) EHCI (DEV-22, FUN-2)

USB 3.0-Left2 USB 3.0-Left1

Hudson-M3 XHCI (DEV-16, FUN-0) XHCI (DEV-16, FUN-1)

Hudson-M2/M3 OHCI (DEV-19, FUN-0) EHCI (DEV-19, FUN-2)

Int. Camera WLAN (BT) Cardreader USB-Right2

USB-Right1 (Debug Port)

+FCH_VDD_11_SSUSB_S

Hudson-M2/M3 OHCI (DEV-18, FUN-0) EHCI (DEV-18, FUN-2)

Hudson-M3 XHCI (DEV-16, FUN-0) XHCI (DEV-16, FUN-1)

USB 3.0-Left2

USB 3.0-Left1

SM Bus 2-->S5 PWR domain

Strap

+3VALW_FCH

R312

R312 10K_0402_5%

10K_0402_5% @

@

1 2

ODD_DA#_Q

6 1

2N7002DW-T/R7_SOT363-6

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC,MB LA-8863

+3VS

2

Q32A

4019IT

+3VS

1 2

R311

R311 10K_0402_5%

10K_0402_5%

E

ODD_DA# <30>

A

26 51Friday, March 23, 2012

A

of

A

SATA_FTX_DRX_P0<30>

HDD

14" ODD

1 1

15"/17" ODD

SATA_FTX_DRX_N0<30>

SATA_FRX_C_DTX_N0<30> SATA_FRX_C_DTX_P0<30>

SATA_FTX_DRX_P1<30> SATA_FTX_DRX_N1<30>

SATA_FRX_C_DTX_N1<30> SATA_FRX_C_DTX_P1<30>

SATA_FTX_DRX_P2<30> SATA_FTX_DRX_N2<30>

SATA_FRX_C_DTX_N2<30> SATA_FRX_C_DTX_P2<30>

+1.5V

E

APU_ALERT#<7>

3 1

MMBT3904_NL_SOT23-3

To avoid LED flashing

2 2

+5VS

1 2

R444 10K_0402_5%R444 10K_0402_5%

12

R446 20K_0402_5%R446 20K_0402_5%

ODD_SEL SKU

High

Low

3 3

SATA port

Port 1

Port 2

SATA_LED#

15"/17"

12

R285

R285 10K_0402_5%

10K_0402_5% @

@

B

2

14"

+3VALW_FCH

12

R437

R437 10K_0402_5%

10K_0402_5%

@

@ Q33

Q33

C

+AVDD_SATA

FCH_ALERT#

SATA_LED#<38>

ODD_SEL<30>

ODD_PWR<39>

12

R336 1K_0402_1%R336 1K_0402_1%

12

R130 931_0402_1%R130 931_0402_1%

R146

10K_0402_5%

T16T16

1 2

R111 10K_0402_5%R111 10K_0402_5%

1 2

R103 10K_0402_5%R103 10K_0402_5%

SATA_FTX_DRX_P0 SATA_FTX_DRX_N0

SATA_FRX_C_DTX_N0 SATA_FRX_C_DTX_P0

SATA_FTX_DRX_P1 SATA_FTX_DRX_N1

SATA_FRX_C_DTX_N1 SATA_FRX_C_DTX_P1

SATA_FTX_DRX_P2 SATA_FTX_DRX_N2

SATA_FRX_C_DTX_N2 SATA_FRX_C_DTX_P2

SATA_CALRP SATA_CALRN

SATA_LED#

+3VS

1 2

ODD_SEL

ODD_PWR

FCH_ALERT#

B

U1B

AK19

SATA_TX0P

AM19

SATA_TX0N

AL20

SATA_RX0N

AN20

SATA_RX0P

AN22

SATA_TX1P

AL22

SATA_TX1N

AH20

SATA_RX1N

AJ20

SATA_RX1P

AJ22

SATA_TX2P

AH22

SATA_TX2N

AM23

SATA_RX2N

AK23

SATA_RX2P

AH24

SATA_TX3P

AJ24

SATA_TX3N

AN24

SATA_RX3N

AL24

SATA_RX3P

AL26

SATA_TX4P

AN26

SATA_TX4N

AJ26

SATA_RX4N

AH26

SATA_RX4P

AN29

SATA_TX5P

AL28

SATA_TX5N

AK27

SATA_RX5N

AM27

SATA_RX5P

AL29

NC6

AN31

NC7

AL31

NC8

AL33

NC9

AH33

NC10

AH31

NC11

AJ33

NC12

AJ31

NC13

AF28

SATA_CALRP

AF27

SATA_CALRN

AD22

SATA_ACT#/GPIO67

AF21

SATA_X1

AG21

SATA_X2

AH16

FANOUT0/GPIO52

AM15

FANOUT1/GPIO53

AJ16

FANOUT2/GPIO54

AK15

FANIN0/GPIO56

AN16

FANIN1/GPIO57

AL16

FANIN2/GPIO58

K6

TEMPIN0/GPIO171

K5

TEMPIN1/GPIO172

K3

TEMPIN2/GPIO173

M6

TEMPIN3/TALERT#/GPIO174

HUDSON-M3_FCBGA656

HUDSON-2

SERIAL ATA

HW MONITOR

SD_CLK/SCLK_2/GPIO73

SD_CMD/SLOAD_2/GPIO74

SD_DATA0/SDATI_2/GPIO77

SD_DATA1/SDATO_2/GPIO78

SD CARDGBE LANSPI ROMVGA DACVGA MAINLINK

SD_DATA2/GPIO79 SD_DATA3/GPIO80

GBE_RXCTL/RXDV

GBE_TXCTL/TXEN

SPI_CLK/GPIO162

SPI_CS1#/GPIO165

ROM_RST#/SPI_WP#/GPIO161

VGA_HSYNC/GPO68 VGA_VSYNC/GPO69

VGA_DDC_SDA/GPO70

VGA_DDC_SCL/GPO71

ML_VGA_HPD/GPIO229

VIN2/SDATI_1/GPIO177 VIN3/SDATO_1/GPIO178 VIN4/SLOAD_1/GPIO179

VIN5/SCLK_1/GPIO180

VIN6/GBE_STAT3/GPIO181

VIN7/GBE_LED3/GPIO182

HUDM3R3@

SD_CD/GPIO75

SD_WP/GPIO76

GBE_COL

GBE_CRS

GBE_MDCK

GBE_MDIO

GBE_RXCLK

GBE_RXD3 GBE_RXD2 GBE_RXD1 GBE_RXD0

GBE_RXERR

GBE_TXCLK

GBE_TXD3 GBE_TXD2 GBE_TXD1 GBE_TXD0

GBE_PHY_PD

GBE_PHY_RST#

GBE_PHY_INTR

SPI_DI/GPIO164

SPI_DO/GPIO163

VGA_RED

VGA_GREEN

VGA_BLUE

VGA_DAC_RSET

AUX_VGA_CH_P AUX_VGA_CH_N

AUXCAL

ML_VGA_L0P ML_VGA_L0N ML_VGA_L1P ML_VGA_L1N ML_VGA_L2P ML_VGA_L2N ML_VGA_L3P ML_VGA_L3N

VIN0/GPIO175 VIN1/GPIO176

C

HDMI@

HDMI_EN#

AL14 AN14 AJ12 AH12 AK13 AM13 AH15 AJ14

AC4 AD3 AD9 W10 AB8 AH7 AF7 AE7 AD7 AG8 AD1 AB7 AF9 AG6 AE8 AD8 AB9 AC2 AA7

GBE_PHY_INTR

W9

FCH_SPI_MISO

V6

FCH_SPI_MOSI

V5

FCH_SPI_CLK

V3

FCH_SPI_CS1#

T6 V1

UMA_CRT_R

L30

UMA_CRT_G

L32

UMA_CRT_B

M29

UMA_CRT_HSYNC

M28

UMA_CRT_VSYNC

N30

UMA_CRT_DATA

M33

UMA_CRT_CLK

N32

VGA_DAC_RSET

K31

ML_VGA_AUXP

V28

ML_VGA_AUXN

V29

AUXCAL

U28

ML_VGA_TXP0

T31

ML_VGA_TXN0

T33

ML_VGA_TXP1

T29

ML_VGA_TXN1

T28

ML_VGA_TXP2

R32

ML_VGA_TXN2

R30

ML_VGA_TXP3

P29

ML_VGA_TXN3

P28

FCH_CRT_HPD

C29

N2 M3 L2 N4 P1

SLP_CHG#

P3 M1 M5

AG16

NC1

AH10

NC2

A28

NC3

G27

NC4

L4

NC5

HDMI@

12

R443 1K_0402_1%

1 2

R352 10K_0402_5%R352 10K_0402_5%

1 2

R366 715_0402_1%R366 715_0402_1%

1 2

R364 100_0402_1%R364 100_0402_1%

1 2

R101 10K_0402_5%R101 10K_0402_5%

1 2

R102 10K_0402_5%R102 10K_0402_5%

1 2

R105 10K_0402_5%R105 10K_0402_5%

1 2

R106 10K_0402_5%R106 10K_0402_5%

1 2

R128 10K_0402_5%R128 10K_0402_5%

1 2

R134 10K_0402_5%R134 10K_0402_5%

1 2

R115 10K_0402_5%R115 10K_0402_5%

1 2

R114 10K_0402_5%R114 10K_0402_5%

Need HDMI_EN# Strap ?

+3VALW_FCH

UMA_CRT_R <23>

UMA_CRT_G <23>

UMA_CRT_B <23>

UMA_CRT_HSYNC <23> UMA_CRT_VSYNC <23>

UMA_CRT_DATA <23> UMA_CRT_CLK <23>

ML_VGA_AUXP <7> ML_VGA_AUXN <7>

+VDDAN_11_ML

ML_VGA_TXP0 <7> ML_VGA_TXN0 <7> ML_VGA_TXP1 <7> ML_VGA_TXN1 <7> ML_VGA_TXP2 <7> ML_VGA_TXN2 <7> ML_VGA_TXP3 <7> ML_VGA_TXN3 <7>

FCH_CRT_HPD <7>

Enable integrated pull-down/up and leave unconnected

D

HDMI_EN#

(Internal 8.2K PU)

HDMI_EN#

SKU

If an SPI ROM is shared between FCH and the Embedded Controller, a 10-k pull-up resistor to +3.3V_S5 is installed

FCH_SPI_CS1#

UMA_CRT_DATA UMA_CRT_CLK

UMA_CRT_R UMA_CRT_G UMA_CRT_B

FCH_CRT_HPD

@

1 2

R137 10K_0402_5%

1 2

R454 2.2K_0402_5%R454 2.2K_0402_5%

1 2

R455 2.2K_0402_5%R455 2.2K_0402_5%

1 2

R367 150_0402_1%R367 150_0402_1%

1 2

R368 150_0402_1%R368 150_0402_1%

1 2

R369 150_0402_1%R369 150_0402_1%

1 2

R365 10K_0402_5%R365 10K_0402_5%

E

HL

Non-HDMI SKU

HDMI SKU

+3VALW_FCH

+3VS

+FCH_VDDAN_33_DAC_R

SLP_CHG#<34>

8

VCC

7 6

SCLK

5

FCH_SPI_CLK

+3VALW_FCH

0.1U_0402_16V4Z

FCH_SPI_CLK FCH_SPI_MOSI

For EMI

@

R402

10_0402_5%

C498

1 2

@

C257

12

10P_0402_50V8J

4M Byte

U13

FCH_SPI_CS1#

+3VALW_FCH

4 4

FCH_SPI_MISO

U13

1

CS#

2

SO/SIO1

HOLD#

3

WP#

4

GND

SI/SIO0

MX25L3206EM2I-12G_SO8

SLP_CHG#

@

1 2

R126 10K_0402_5%

+3VALW_FCH

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2011/11/28 2013/12/31

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC,MB LA-8863

4019IT

E

27 51Friday, March 23, 2012

of

A

B

C

D

E

STRAP PINS

12

R238

R238 10K_0402_5%

10K_0402_5%

12

R244

R244 @

@ 10K_0402_5%

10K_0402_5%

EC_PWM2

LPC ROM (INTERNAL 10K PULL-UP)

SPI ROM

DEFAULT

EC_PWM2

PCI_CLK1

1 1

PULL HIGH

PULL LOW

PCI_CLK1<25>

2 2

PCI_CLK3<25> PCI_CLK4<25> CLK_PCI_EC<25,36> CLK_PCI_DDR<25,37> EC_PWM2<26> RTC_CLK<25,36>

ALLOW PCIE GEN2

DEFAULT

FORCE PCIE GEN1

PCI_CLK1

12

R231

R231 10K_0402_5%

10K_0402_5%

12

R232

R232 @

@ 10K_0402_5%

10K_0402_5%

PCI_CLK3

ENABLE DEBUG STRAP

DISABLE DEBUG STRAP

DEFAULT

PCI_CLK3

PCI_CLK4 LPC_CLK0

NON_FUSION CLOCK MODE

FUSION CLOCK MODE

DEFAULT

12

R241

R241 @

@ 10K_0402_5%

10K_0402_5%

PCI_CLK4

12

R233

R233 10K_0402_5%

10K_0402_5%

12

R242

R242 @

@ 10K_0402_5%

10K_0402_5%

CLK_PCI_EC

12

R234

R234 10K_0402_5%

10K_0402_5%

EC ENABLED

EC DISABLED

DEFAULT

12

CLKGEN ENABLED

DEFAULT

CLKGEN DISABLE

R243

R243 @

@ 10K_0402_5%

10K_0402_5%

CLK_PCI_DDR

R237

R237 10K_0402_5%

10K_0402_5%

12

R245

R245 @

@ 10K_0402_5%

10K_0402_5%

RTC_CLK

12

R239

2.2K_0402_5%

RTC_CLKLPC_CLK1

S5 PLUS MODE DISABLED

DEFAULT

S5 PLUS MODE ENABLED

+3VALW_FCH+3VALW_FCH+3VALW_FCH+3VALW_FCH+3VS+3VS+3VS

12

R240

R240 10K_0402_5%

10K_0402_5%

12

R246

R246 @

@

2.2K_0402_5%

CRT Power Down Circuit

+3VS +FCH_VDDAN_33_DAC_R

L32

1 2

MBK1608221YZF_2P

C277

2.2U_0603_6.3V6K

0.1U_0402_16V7K

1

C276

2

DEBUG STRAPS

FCH HAS 15K INTERNAL PU-UP FOR PCI_AD[27:23]

3 3

PCI_AD27<25> PCI_AD26<25> PCI_AD25<25> PCI_AD24<25> PCI_AD23<25>

4 4

PULL HIGH

PULL LOW

PCI_AD27

PCI_AD27 PCI_AD26

PCI_AD26

R247

R247 @

@

2.2K_0402_5%

DISABLE ILA AUTORUN

DEFAULT

ENABLE ILA AUTORUN

12

USE PCI PLL

DEFAULT

BYPASS PCI PLL

12

A

PCI_AD25

R248

R248 @

@

2.2K_0402_5%

PCI_AD25 PCI_AD24

USE FC PLL

BYPASS FC PLL

12

PCI_AD24

R249

R249 @

@

2.2K_0402_5%

B

USE DEFAULT PCIE STRAPS

DEFAULT

USE EEPROM PCIE STRAPS

12

R250

R250 @

@

2.2K_0402_5%

PCI_AD23

DISABLE PCI MEM BOOT

DEFAULTDEFAULT

ENABLE PCI MEM BOOT

12

R251

R251 @

@

2.2K_0402_5%

2

C523

0.1U_0402_10V7K

R5

FCH_PWR_EN#<39>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2011/11/28 2013/12/31

Compal Secret Data

Deciphered Date

1 2

47K_0402_5%

1

AO3413_SOT23

2

C521

0.01U_0402_25V7K

1

4.7U_0805_10V4Z

D

+3VALW

Vgs=-4.5V,Id=3A,Rds<97mohm

2

S

Q3

C522

Q3

G

2

1 3

PJ2

2

JUMP_43X79

@

1

D

1

2

Title

Size Document Number Rev

Custom

Date: Sheet

+3VALW_FCH

1

2

C520

C520 1U_0402_6.3V6K

1U_0402_6.3V6K

1

Compal Electronics, Inc.

SCHEMATIC,MB LA-8863

4019IT

E

A

of

28 51Friday, March 23, 2012

A

B

C

D

E

C334

C336

C338

C340

C506

1

2

1

2

1

2

1

2

1

2

0.1U_0402_16V7K

1

C335

2

0.1U_0402_16V7K

1

C337

2

0.1U_0402_16V7K

1

C339

2

0.1U_0402_16V7K

1

C341

2

2.2U_0603_6.3V6K

1

2

0.1U_0402_16V7K

1

C509

2

1U_0402_6.3V6K

1

C518

2

0.1U_0402_16V7K

1

C513

2

0.1U_0402_16V7K

1

C515

2

0.1U_0402_16V7K

1

C517

2

+VCC_FCH_R

2.2U_0603_6.3V6K

0.1U_0402_16V7K

1

C315

2

+1.1VS_CKVDD

2.2U_0603_6.3V6K

0.1U_0402_16V7K

1

C323

2

+PCIE_VDDR_FCH

2.2U_0603_6.3V6K

0.1U_0402_16V7K

1

C499

2

+AVDD_SATA

2.2U_0603_6.3V6K

0.1U_0402_16V7K

1

C505

2

1 2

R26 0_0402_5%R26 0_0402_5%

1 2

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K MBK1608221YZF_2P

MBK1608221YZF_2P

1 2

R373 0_0603_5%R373 0_0603_5%

1U_0402_6.3V6K

1 2

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K MBK1608221YZF_2P

MBK1608221YZF_2P

1 2

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K R51 0_0402_5%R51 0_0402_5%

1 2

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K R53 0_0402_5%R53 0_0402_5%

D

1

C317

2

1

C500

2

L28

220 ohm

L29

220 ohm

22U_0805_6.3V6M

U1C

+3VS

MBK1608221YZF_2P

1 1

+FCH_VDDAN_33_DAC_R

1 2

R49 0_0603_5%R49 0_0603_5%

1 2

+3VS

MBK1608221YZF_2P

+3VALW_FCH

1 2

MBK1608221YZF_2P

2 2

+3VALW_FCH

1 2

MBK1608221YZF_2P

+3VS

1 2

MBK1608221YZF_2P

+3VS

1 2

MBK1608221YZF_2P

3 3

4 4

MBK1608221YZF_2P

L30

1 2

220 ohm

L33

@

L34

220 ohm

L35

220 ohm

L36

220 ohm

L22

220 ohm

+VDDPL_3.3V

2.2U_0603_6.3V6K

1

C272

C273

2

+FCH_VDDPL_33_MLDAC

2.2U_0603_6.3V6K

1

C275

C274

2

+FCH_VDDPL_33_SSUSB

2.2U_0603_6.3V6K

1

C278

C279

2

+FCH_VDDPL_33_USB

2.2U_0603_6.3V6K

1

C281

2

+VDDPL_33_PCIE

2.2U_0603_6.3V6K

1

C293

2

+VDDPL_33_SATA

2.2U_0603_6.3V6K

1

C296

2

1

2

1

2

1

2

C280

C294

C297

0.1U_0402_16V7K

1

2

0.1U_0402_16V7K

1

2

0.1U_0402_16V7K

+1.1VALW

A

+3VS

1 2

R20 0_0603_5%R20 0_0603_5%

+FCH_VDDPL_33_MLDAC

VDDPL_33_SSUSB_S For Hudson M3 USB3.0 only For Hudson M2, connect to GND

LDO_CAP: Internally generated 1.8V supply for the RGB output

+1.1VS

30mils

L24

1 2

MBK1608221YZF_2P

220 ohm/2A

+3VALW_FCH

FBMA-L11-201209-221LMA30T_0805

+1.1VALW

L56

1 2

220 ohm/3A

L58

1 2

MBK1608221YZF_2P

220 ohm

L59

1 2

MBK1608221YZF_2P

220 ohm

+FCH_VDD_11_SSUSB_S

40mils

L61

FBMA-L11-201209-221LMA30T_0805

12

42 ohm/4A

22U_0805_6.3V6M

1

C267

C266

2

R34 0_0402_5%R34 0_0402_5% R35 0_0402_5%R35 0_0402_5%

1 2

R37 0_0402_5%R37 0_0402_5%

1 2

R12 0_0603_5%R12 0_0603_5%

1

C133

2

1

C303

2

1

C316

2

1 2

R131 0_0603_5%R131 0_0603_5%

+FCH_VDD_11_SSUSB_S

1 2

R132 0_0603_5%R132 0_0603_5%

1U_0402_6.3V6K

1

C269

2

+VDDPL_3.3V

1 2 1 2

+FCH_VDDAN_33_DAC_R +FCH_VDDPL_33_SSUSB +FCH_VDDPL_33_USB +VDDPL_33_PCIE +VDDPL_33_SATA

1

C128

2

R129 0_0402_5%R129 0_0402_5%

1U_0402_6.3V6K

1

C134

C135

2

2.2U_0603_6.3V6K

0.1U_0402_16V7K

1

C302

2

2.2U_0603_6.3V6K

0.1U_0402_16V7K

1

C304

C324

2

1U_0402_6.3V6K

1

C138

2

C140

B

+VDDIO_33_PCIGP

1U_0402_6.3V6K

1

C271

2

+VDDPL_33_DAC +VDDPL_33_ML

@

0.1U_0402_16V7K

1

C132

2

10U_0603_6.3V6M

1

C136

2

0.1U_0402_16V7K

1

C331

2

1U_0402_6.3V6K

1

C332

2

1U_0402_6.3V6K

1

2

LDO_CAP

+VDDPL_11_DAC

+VDDAN_11_ML

0.1U_0402_16V7K

1

2

10U_0603_6.3V6M

1

C137

2

10mils

0.1U_0402_16V7K

1

C333

2

1

C270

2

1 2

C298 2.2U_0603_6.3V6K

4.7U_0603_6.3V6K

C129

1 2

+VDDAN_33_USB

1

2

+VDDANCR_11_USB

+VDDCR_1.1V_USB+VDDCR_1.1V_USB

1

2

+VDDAN_SSUSB

1

C325

2

+VDDCR_11_SSUSB

10U_0603_6.3V6M

1

C139

2

10mils

AB17 AB18

AD10 AC13

AB12 AB13 AB14 AB16

10mils 10mils 10mils 10mils 10mils 10mils 10mils

AH29

10mils

AG28

15mils

10mils

20mils

AB10 AB11

AA11

AA10

30mils

0.1U_0402_16V7K

20mils

30mils

0.1U_0402_16V7K

1

2

U1C

VDDIO_33_PCIGP_1 VDDIO_33_PCIGP_2

AE9

VDDIO_33_PCIGP_3 VDDIO_33_PCIGP_4

AG7

VDDIO_33_PCIGP_5 VDDIO_33_PCIGP_6 VDDIO_33_PCIGP_7 VDDIO_33_PCIGP_8 VDDIO_33_PCIGP_9 VDDIO_33_PCIGP_10

H24

VDDPL_33_SYS

V22

VDDPL_33_DAC

U22

VDDPL_33_ML

T22

VDDAN_33_DAC

L18

VDDPL_33_SSUSB_S

D7

VDDPL_33_USB_S VDDPL_33_PCIE VDDPL_33_SATA

M31

LDO_CAP

V21

VDDPL_11_DAC

Y22

VDDAN_11_ML_1

V23

VDDAN_11_ML_2

V24

VDDAN_11_ML_3

V25

VDDAN_11_ML_4

VDDIO_33_GBE_S VDDCR_11_GBE_S_1

VDDCR_11_GBE_S_2

AA9

VDDIO_GBE_S_1 VDDIO_GBE_S_2

G7

VDDAN_33_USB_S_1

H8

VDDAN_33_USB_S_2

J8

VDDAN_33_USB_S_3

K8

VDDAN_33_USB_S_4

K9

VDDAN_33_USB_S_5

M9

VDDAN_33_USB_S_6

M10

VDDAN_33_USB_S_7

N9

VDDAN_33_USB_S_8

N10

VDDAN_33_USB_S_9

M12

VDDAN_33_USB_S_10

N12

VDDAN_33_USB_S_11

M11

VDDAN_33_USB_S_12

U12

VDDAN_11_USB_S_1

U13

VDDAN_11_USB_S_2

T12

VDDCR_11_USB_S_1

T13

VDDCR_11_USB_S_2

P16

VDDAN_11_SSUSB_S_1

M14

VDDAN_11_SSUSB_S_2

N14

VDDAN_11_SSUSB_S_3

P13

VDDAN_11_SSUSB_S_4

P14

VDDAN_11_SSUSB_S_5

N16

VDDCR_11_SSUSB_S_1

N17

VDDCR_11_SSUSB_S_2

P17

VDDCR_11_SSUSB_S_3

M17

VDDCR_11_SSUSB_S_4

HUDSON-M3_FCBGA656

HUDSON-2

102mA

PCI/GPIO I/O

CORE S0

47mA 20mA 12mA 30mA

340mA

CLKGEN I/OPCI EXPRESSSERIAL ATA3.3V_S5 I/O

11mA 14mA 11mA 12mA

1088mA

7mA

226mA

1337mA

470mA

140mA

42mA

187mA

70mA

12mA

282mA

USB SS USB MAIN LINKGBE LAN

424mA

POWER

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

HUDM3R3@

50mils

VDDCR_11_1 VDDCR_11_2 VDDCR_11_3 VDDCR_11_4

1007mA

VDDCR_11_5 VDDCR_11_6 VDDCR_11_7 VDDCR_11_8 VDDCR_11_9

VDDAN_11_CLK_1 VDDAN_11_CLK_2 VDDAN_11_CLK_3 VDDAN_11_CLK_4 VDDAN_11_CLK_5 VDDAN_11_CLK_6 VDDAN_11_CLK_7 VDDAN_11_CLK_8

VDDAN_11_PCIE_1 VDDAN_11_PCIE_2 VDDAN_11_PCIE_3 VDDAN_11_PCIE_4 VDDAN_11_PCIE_5 VDDAN_11_PCIE_6 VDDAN_11_PCIE_7 VDDAN_11_PCIE_8

VDDAN_11_SATA_1 VDDAN_11_SATA_4 VDDAN_11_SATA_2 VDDAN_11_SATA_3 VDDAN_11_SATA_5 VDDAN_11_SATA_6 VDDAN_11_SATA_7 VDDAN_11_SATA_8 VDDAN_11_SATA_9

VDDAN_11_SATA_10

VDDIO_33_S_1 VDDIO_33_S_2 VDDIO_33_S_3 VDDIO_33_S_4

59mA

VDDIO_33_S_5 VDDIO_33_S_6 VDDIO_33_S_7 VDDIO_33_S_8

5mA

VDDXL_33_S

VDDCR_11_S_1 VDDCR_11_S_2

VDDPL_11_SYS_S

VDDAN_33_HWM_S

26mA

VDDIO_AZ_S

T14 T17 T20 U16 U18 V14 V17 V20 Y17

20mils

H26 J25 K24 L22 M22 N21 N22 P22

50mils

AB24 Y21 AE25 AD24 AB23 AA22 AF26 AG27

60mils

AA21 Y20 AB21 AB22 AC22 AC21 AA20 AA18 AB20 AC19

10mils

N18 L19 M18 V12 V13 Y12 Y13 W11

10mils

G24

10mils

N20 M20

10mils

J24

10mils

M8

10mils

AA4

2011/11/28 2013/12/31

+VCC_FCH_R

1U_0402_6.3V6K

1

C311

C312

2

+1.1VS_CKVDD

1U_0402_6.3V6K

1

C320

C319

2

+PCIE_VDDR_FCH

1U_0402_6.3V6K

1

C328

C327

2

+AVDD_SATA

1U_0402_6.3V6K

1

C502

C501

2

+VDDIO_33_S

0.1U_0402_16V7K

1

C343

C342

2

+VDDXL_3.3V

C510

+VDDCR_1.1V

C512

+VDDPL_1.1V

C514

+VDDAN_33_HWM

C516

+VDDIO_AZ

C519

Compal Secret Data

Deciphered Date

1 2

R193 0_0805_5%R193 0_0805_5%

1 2

R371 0_0603_5%R371 0_0603_5%

1 2

R194 0_0805_5%R194 0_0805_5%

1 2

R370 0_0805_5%R370 0_0805_5%

+3VALW_FCH

+1.1VALW

+3VALW_FCH

+3VS

+1.1VS

U1E

A3

VSS

A33

VSS

B7

VSS

B13

VSS

D9

VSS

D13

VSS

E5

VSS

E12

VSS

E16

VSS

E29

VSS

F7

VSS

F9

VSS

F11

VSS

F13

VSS

F16

VSS

F17

VSS

F19

VSS

F23

VSS

F25

VSS

F29

VSS

G6

VSS

G16

VSS

G32

VSS

H12

VSS

H15

VSS

H29

VSS

J6

VSS

J9

VSS

J10

VSS

J13

VSS

J28

VSS

J32

VSS

K7

VSS

K16

VSS

K27

VSS

K28

VSS

L6

VSS

L12

VSS

L13

VSS

L15

VSS

L16

VSS

L21

VSS

M13

VSS

M16

VSS

M21

VSS

M25

VSS

N6

VSS

N11

VSS

N13

VSS

N23

VSS

N24

VSS

P12

VSS

P18

VSS

P20

VSS

P21

VSS

P31

VSS

P33

VSS

R4

VSS

R11

VSS

R25

VSS

R28

VSS

T11

VSS

T16

VSS

T18

VSS

N8

VSSAN_HWM

K25

VSSXL

H25

VSSPL_SYS

HUDSON-M3_FCBGA656

HUDSON-2

HUDM3R3@

GROUND

VSSPL_DAC

VSSAN_DAC

VSSANQ_DAC

VSSIO_DAC

EFUSE

T25

VSS

T27

VSS

U6

VSS

U14

VSS

U17

VSS

U20

VSS

U21

VSS

U30

VSS

U32

VSS

V11

VSS

V16

VSS

V18

VSS

W4

VSS

W6

VSS

W25

VSS

W28

VSS

Y14

VSS

Y16

VSS

Y18

VSS

AA6

VSS

AA12

VSS

AA13

VSS

AA14

VSS

AA16

VSS

AA17

VSS

AA25

VSS

AA28

VSS

AA30

VSS

AA32

VSS

AB25

VSS

AC6

VSS

AC18

VSS

AC28

VSS

AD27

VSS

AE6

VSS

AE15

VSS

AE21

VSS

AE28

VSS

AF8

VSS

AF12

VSS

AF16

VSS

AF33

VSS

AG30

VSS

AG32

VSS

AH5

VSS

AH11

VSS

AH18

VSS

AH19

VSS

AH21

VSS

AH23

VSS

AH25

VSS

AH27

VSS

AJ18

VSS

AJ28

VSS

AJ29

VSS

AK21

VSS

AK25

VSS

AL18

VSS

AM21

VSS

AM25

VSS

AN1

VSS

AN18

VSS

AN28

VSS

AN33

VSS

T21 L28 K33 N28

R6

Connect to GND through a dedicated via

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC,MB LA-8863

4019IT

E

29 51Friday, March 23, 2012

of

A

SATA HDD Conn.

JHDD

1 1

23 24

SUYIN_127043FB022G278ZR

GND GND

GND

3.3V

3.3V GND GND GND

GND

Reserved

GND

RX+

TX+

@JHDD

@

1

SATA_FTX_C_DRX_P0

2

SATA_FTX_C_DRX_N0

3

RX-

4

SATA_FRX_DTX_N0

5

TX-

5V 5V 5V

12V 12V 12V

6 7

8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

SATA_FRX_DTX_P0

+5VS

1

C356

C356 10U_0603_6.3V6M

10U_0603_6.3V6M

2

Close to JHDD

C369 0.01U_0402_25V7KC369 0.01U_0402_25V7K

1 2

C367 0.01U_0402_25V7KC367 0.01U_0402_25V7K

1 2

C368 0.01U_0402_25V7KC368 0.01U_0402_25V7K

1 2

C370 0.01U_0402_25V7KC370 0.01U_0402_25V7K

1 2

+3VS

+5VS

Place closely JHDD SATA CONN.

1.2A

1

C357

0.1U_0402_10V7K

2

1

C358

0.1U_0402_10V7K

2

B

SATA_FTX_DRX_P0 <27> SATA_FTX_DRX_N0 <27>

SATA_FRX_C_DTX_N0 <27> SATA_FRX_C_DTX_P0 <27>

1

C359

0.1U_0402_10V7K

2

SATA ODD Conn

JODD

@JODD

@

GND

A+

A-

GND

B-

B+

GND

DP +5V +5V

GND1

GND

GND2

GND

SANTA_206001-1

MD

14 15

C

1 2 3 4 5 6 7

8 9 10 11 12 13

SATA_FTX_C_DRX_P1 SATA_FTX_C_DRX_N1

SATA_FRX_DTX_N1 SATA_FRX_DTX_P1

ODD_PLUGIN#

+5VS_ODD

ODD_DA#

1

2

C376 0.01U_0402_25V7KC376 0.01U_0402_25V7K C377 0.01U_0402_25V7KC377 0.01U_0402_25V7K

C378 0.01U_0402_25V7KC378 0.01U_0402_25V7K C375 0.01U_0402_25V7KC375 0.01U_0402_25V7K

ODD_DA# <26>

C364

0.1U_0402_10V7K

0.1U_0402_10V7K @

@

1 2 1 2

1

C365

0.1U_0402_10V7K

0.1U_0402_10V7K @

@

2

Add C364 and C365 for EMI request on PVT

D

SATA_FTX_DRX_P1 <27> SATA_FTX_DRX_N1 <27>

SATA_FRX_C_DTX_N1 <27>

SATA_FRX_C_DTX_P1 <27>

ODD_PLUGIN# <26>

+5VS_ODD

1

2

1.1A

C355

C355 10U_0603_6.3V6M

10U_0603_6.3V6M

E

Place components closely ODD CONN.

1

C354

@

10U_0603_6.3V6M

2

1

C379

C379 @

@

1U_0402_6.3V6K

1U_0402_6.3V6K 2

1

C380

0.1U_0402_10V7K

2

1

C360

2

0.1U_0402_10V7K

SATA ODD Conn (for 15"/17")

2 2

JODDB

@JODDB

@

1

1 2 3 4 5 6 7 8

9 10 11 12

GND GND

ACES_88058-120N

3 3

2 3 4 5 6 7 8 9 10 11 12 13 14

SATA_FTX_C_DRX_P2 SATA_FTX_C_DRX_N2

SATA_FRX_DTX_N2 SATA_FRX_DTX_P2

ODD_PLUGIN#

+5VS_ODD

ODD_DA#

C384 0.01U_0402_25V7KC384 0.01U_0402_25V7K

1 2

C382 0.01U_0402_25V7KC382 0.01U_0402_25V7K

1 2

C381 0.01U_0402_25V7KC381 0.01U_0402_25V7K

1 2

C383 0.01U_0402_25V7KC383 0.01U_0402_25V7K

1 2

ODD_SEL <27>

SATA_FTX_DRX_P2 <27> SATA_FTX_DRX_N2 <27>

SATA_FRX_C_DTX_N2 <27>

SATA_FRX_C_DTX_P2 <27>

Power Button & RUSB connector

JUSIO

1

2

3

4

5

6

7

8

9

10

11

12

13

GND

14

GND

ACES_88058-120N

@

USB20_P1_R USB20_N1_R

USB20_P0_R USB20_N0_R

ON/OFFBTN#

+5VS_PWR_ON_LED

+USB_VCCA

R4

390_0402_5%

ON/OFFBTN# <36,38>

12

+5VS

OUT OUT OUT OCB

W=80mils

+USB_VCCA

6

C361 1000P_0402_50V7KC361 1000P_0402_50V7K

7 8 5

1

C362

4.7U_0805_10V4Z

2

@

For EMI

12

USB_OC0# <26>

+5VALW

2.5A

U14

2

IN

3

USB_EN#<34,36>

USB_EN#

IN

4

EN/ENB

1

GND

SY6288DCAC_MSOP8

SA00004KB00 SA00003TV00

USB20_P1<26>

USB20_N1<26>

4 4

A

B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

USB20_P1

USB20_N1

Reserved for EHCI CRC errors Reserved for EHCI CRC errors

2011/11/28 2013/12/31

@ RR48

@

1 2

0_0402_5%

4

1

WCM-2012-900T_0805

1 2

0_0402_5%@

12

R77

R77 300_0402_5%

300_0402_5% @

@

1

C291

C291 10P_0402_50V8J

10P_0402_50V8J @

@

2

Compal Secret Data

0_0402_5%@

Deciphered Date

USB20_P1_R

RR48

LR8

3

2

USB20_N1_R

RR47

D

USB20_P0<26>

USB20_N0<26>

USB20_P0

USB20_N0

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC,MB LA-8863

4

1

WCM-2012-900T_0805

12

R85

R85 300_0402_5%

300_0402_5% @

@

1

C292

C292 10P_0402_50V8J

10P_0402_50V8J @

@

2

4019IT

@ RR31

@

1 2

4

1

1 2

E

0_0402_5%

0_0402_5%@

USB20_P0_R

RR31

LR7

3

2

USB20_N0_R

RR30

A

of

30 51Friday, March 23, 2012

of

30 51Friday, March 23, 2012

of

30 51Friday, March 23, 2012

Slot 1 Half PCIe Mini Card-WLAN

BT_CTRL BT_CTRL_R

0_0402_5%

1 2

R1443

@ R1443

CLKREQ_WLAN#<26>

CLK_WLAN#<25> CLK_WLAN<25>

PCIE_FRX_WLANTX_N1<5> PCIE_FRX_WLANTX_P1<5>

PCIE_FTX_C_WLANRX_N1<5> PCIE_FTX_C_WLANRX_P1<5>

WLAN/ WiFi

E51_TXD<36> E51_RXD<36>

Debug card using

@

+3V_WLAN

R45

R45 0_0402_5%

0_0402_5%

1 2 1 2

0_0402_5%

0_0402_5% R47

R47

E51_RXD_R

40 mils Enable Disable

+3V_WLAN +1.5VS_WLAN

0.1U_0402_10V7K

0.01U_0402_25V7K

JWLAN

1

3

5

7

9

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

41

43

45

47

49

51

53

GND1

BELLW_80003-7041

CM1

+1.5VS_WLAN

@JWLAN

@

2 4 6

8 10 12 14 16

18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52

GND2

1

CM2

2

2 4 6 8 10 12 14 16

18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52

54

1

CM3

2

4.7U_0805_10V4Z

+1.5VS

PJ33

PJ33 PAD-OPEN 2x2m

PAD-OPEN 2x2m @

@

2 1

+3V_WLAN

Reserved for EHCI CRC errors

For SED

12

C253

47P_0402_50V8J

@

WLAN_OFF# WLAN_RST#_R

12

R63

R63 300_0402_5%

300_0402_5% @

@

1

C286

C286 10P_0402_50V8J

10P_0402_50V8J @

@

2

0.1U_0402_10V7K

1

CM7

CM8

@

2

0.01U_0402_25V7K

R62

0_0402_5%

@

1 2

FCH_SCLK0 <10,11,26> FCH_SDATA0 <10,11,26>

USB20_N3 <26> USB20_P3 <26>

For SED

1

CM9

@

2

4.7U_0805_10V4Z

WL_OFF# <36>

12

C254

47P_0402_50V8J

@

For RF

+3V_WLAN

12

C261

47P_0402_50V8J

@

+1.5VS_WLAN

12

C260

47P_0402_50V8J

@

WLAN&BT Combo module circuits

BT_CTRL<36>

BT on module

BT_CTRL

For isolate BT_CTRL and Compal Debug Card.

HL

R327

1 2

1K_0402_5%

E51_RXD_R

+3VALW TO +3V_WLAN

+3VS

12

R142

R142 100K_0402_5%

100K_0402_5%

R143

WLAN_PWR#<36>

Add WLAN power circuit on DVT

1 2

47K_0402_5%

BT on module

2

1

2

1

C907

0.1U_0402_10V7K

2

C908

0.01U_0402_25V7K

APU_PCIE_RST#<25,32>

WLAN_RST#<36>

Add WLAN_RST# on DVT

+3VS

Vgs=-4.5V,Id=3A,Rds<97mohm

21

S

G

Q212

Q212 AO3413_SOT23

AO3413_SOT23

D

1 3

WLAN_RST#

@

PJ26

PJ26 PAD-OPEN 2x2m

PAD-OPEN 2x2m

+3V_WLAN

5

UM5

1

P

IN1

O

2

IN2

SN74AHC1G08DCKR_SC70-5

G

3

@

1 2

RM19 0_0402_5%

4

WLAN_RST#_R

RM21

RM21 100K_0402_5%

100K_0402_5%

1 2

1

CCL2

GCLK@

2

0.1U_0402_10V7K

+3VL +3VS+3V_LAN

1

GCLK@

2

0.1U_0402_10V7K

CCL1

+1.8VGS

1

CCL7

GCLK@

2

0.1U_0402_10V7K

change part number to SJ10000EF00

GCLK@

YCL1 25MHZ 12PF X3G025000DK1H-X

1

CCL4

CCL4 18P_0402_50V8J

18P_0402_50V8J

GCLK@

GND

2

1

2

GND

3

4

CLK_X2CLK_X1

1

CCL3

GCLK@

2

0.1U_0402_10V7K

2

CCL5

CCL5 18P_0402_50V8J

18P_0402_50V8J

1

GCLK@

22U_0805_6.3V6M

GCLK@

+RTCBATT

+3VL

+3VALW

+1.8VGS

+3V_LAN

+3VS

1

CCL12

2

CLK_X1 CLK_X2

SLG3NB270VTR_TQFN16_2X3

Change to GCLK to SLG3NB270V SA00005DP00 for 27MHz for VGA

1

CCL6

2.2U_0603_6.3V6K

UCL1

GCLK@

10

VBAT

15

16

VDD_RTC_OUT

+V3.3A

2

VDD

VDDIO_27M1127MHz

8

VDDIO_25M_A

3

VDDIO_25M_B

1

XTAL_IN XTAL_OUT

GND1

4

25MHz_A 25MHz_B

GND2

GND3

7

13

32kHz

GND4

17

2.2U_0603_6.3V6K

2

GCLK@

14

FCH_RTCX1_R_R

9

VGA_X1_R

12

LAN_X1_R_R

6

FCH_X1_R_R

5

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

+RTCBATT_D

1 2

RCL9 0_0402_5%GCLK@RCL9 0_0402_5%GCLK@

1 2

R799 33_0402_5%GCLK@R799 33_0402_5%GCLK@

1 2

RCL2 33_0402_5%GCLK@RCL2 33_0402_5%GCLK@

1 2

RCL1 33_0402_5%GCLK@RCL1 33_0402_5%GCLK@

FCH_RTCX1_R <25>

VGA_X1 <13>

FCH_X1_R <25>

Compal Secret Data

2011/11/28 2013/12/31

Compal Secret Data

Deciphered Date

1

2

LAN_X1_R <32>

CCL10

5P_0402_50V8C

@

EMI request 11/06

Reserved for Swing Level adjustment ( Close GCLK side )

LAN_X1_R_R

RCL5 0_0402_5%

@

1 2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC,MB LA-8863

4019IT

Friday, March 23, 2012

of

31 51

of

31 51

of

31 51

A

B

C

D

E

UL1

CL1 0.1U_0402_10V7KCL1 0.1U_0402_10V7K

PCIE_FRX_C_LANTX_P0<5> PCIE_FRX_C_LANTX_N0<5>

LAN_EN<26>

CLKREQ_LAN#<26>

1 1

+3VS

RL24 10K_0402_5%RL24 10K_0402_5%

+3V_LAN

RL25 10K_0402_5%@RL25 10K_0402_5%@

+3VS

12

1K_0402_5%

1K_0402_5% RL6

RL6 @

@

2 2

RL7

15K_0402_5%

LAN_EN

12

+3V_LAN

1 2

RL433 0_0402_5%RL433 0_0402_5%

WOL_EN#

1 3

D

1 2

RL28 0_0402_5%

LANCLK_REQ#

FCH_PCIE_WAKE#

RL22 1K_0402_5%@RL22 1K_0402_5%@

LAN_EN

RL26 0_0402_5%

WOL_EN#ISOLATE#

Sx Enable Wake up

LOW

@

1 2

CL2 0.1U_0402_10V7KCL2 0.1U_0402_10V7K

1 2

PCIE_FTX_C_LANRX_P0<5>

2

PCIE_FTX_C_LANRX_N0<5>

G

2N7002_SOT23-3

LANCLK_REQ#CLKREQ_LAN#

QL53

S

APU_PCIE_RST#<25,31>

CLK_LAN<25> CLK_LAN#<25>

FCH_PCIE_WAKE#<26>

@

Sx Disable Wake up

HIGH

S0

HIGH

PCIE_FRX_LANTX_P0 PCIE_FRX_LANTX_N0 PCIE_FTX_C_LANRX_P0

PCIE_FTX_C_LANRX_N0

APU_PCIE_RST# CLK_LAN

CLK_LAN#

LAN_X1 LAN_X2

FCH_PCIE_WAKE# ISOLATE#

RL21 10K_0402_5%@RL21 10K_0402_5%@

ENSWREG

+LAN_VDDREG

1 2

RL5 2.49K_0402_1%RL5 2.49K_0402_1%

RTL8105ENCRTL8111E/F Pin14 Pin15 Pin38

NC 10K ohm PD NC 1K ohm PH

12

+3VALW TO +3V_LAN

@

2

AO3413_SOT23

CL681

+3VALW

Vgs=-4.5V,Id=3A,Rds<97mohm

2

S

QL51

G

@

D

PAD-OPEN 2x2m

1 3

1

2

PJ29

2

@

1

+3VALW_FCH

2

PJ31

2

+3V_LAN

@

1

PAD-OPEN 2x2m

1

2

CL682

CL682 1U_0402_6.3V6K

1U_0402_6.3V6K

1

LAN_MDI1+

+3V_LAN

LAN_MDI1-

LAN_MDI2+ LAN_MDI3+

+3V_LAN

LAN_MDI2-

B

+3VALW

12

RL147

RL147 100K_0402_5%

100K_0402_5% @

@

RL432

@RL432

@

WOL_EN#<36>

3 3

1 2

47K_0402_5%

2

CL483

CL483 @

@

0.1U_0402_10V7K

1

2

@

@ CL482

CL482

0.01U_0402_25V7K

1

4.7U_0805_10V4Z

+3V_LAN rising time (10%~90%) need > 1ms and <100ms.

LAN WOL LAN_EN ISOLATEB S0 Sx S0 Sx

--------------------------------------------- 0 0 0 0 1 1 0 1 0 0 1 1 1 0 1 1 1 1 1 1 1 1 1 0*

4 4

* S3: after SUSP# assert low over 100ms S4/S5: after SYSON assert low over 100ms

A

UL1

22

HSOP

23

HSON

17

HSIP

18

HSIN

16

CLKREQB

25

PERSTB

19

REFCLK_P

20

REFCLK_N

43

CKXTAL1

44

CKXTAL2

28

LANWAKEB

26

ISOLATEB

14

NC/SMBCLK

15

NC/SMBDATA

38

GPO/SMBALERT

33

ENSWREG

34

VDDREG

35

VDDREG

46

RSET

24

GND

49

PGND

RTL8111F-CGT_QFN48_6x6

RTL8111F-CGT_QFN48_6x6 8111FVB@

8111FVB@

NC

D99

6

I/O4

5

VDD

4

I/O3

AZC099-04S.R7G_SOT23-6

D100

@D100

@

6

I/O4

5

VDD

4

I/O3

AZC099-04S.R7G_SOT23-6

LAN_X1_R<31>

CL43 10PF_0402_50V9

1 2

GCLK@

1

2

@D99

@

I/O2

GND

I/O1

3

I/O2

2

GND

1

I/O1

LED3/EEDO LED1/EESK

NC/MDIP2

NC/MDIN2

NC/MDIP3

NC/MDIN3

REGOUT

CL26

CL26 27P_0402_50V8J

27P_0402_50V8J NOGCLK@

NOGCLK@

3

2

1

2/9: Add for ESD request

31 37 40

LED0

RL2 10K_0402_5%@RL2 10K_0402_5%@

30

EECS

RL1 10K_0402_5%@RL1 10K_0402_5%@

32

EEDI

LAN_MDI0+

1

MDIP0

LAN_MDI0-

2

MDIN0

LAN_MDI1+

4

MDIP1

LAN_MDI1-

5

MDIN1

LAN_MDI2+

7

LAN_MDI2-

8

LAN_MDI3+

10

LAN_MDI3-

11

13 29 41

27 39

12 42 47 48

21 3

6 9 45

+LAN_REGOUT

36

GND

2

+LAN_VDD10

+3V_LAN

+LAN_EVDD10 +LAN_VDD10

60 mils

RL8

GCLK@RL8

GCLK@

1 2

0_0402_5%

GND

4

3

27P_0402_50V8J

DVDD10 DVDD10 DVDD10

DVDD33 DVDD33

AVDD33 AVDD33 AVDD33 AVDD33

EVDD10 AVDD10

AVDD10 AVDD10 AVDD10

1 2

RL29 22_0402_5%

GCLK@

YL1 25MHZ_20PF_7V25000016NOGCLK@ YL1 25MHZ_20PF_7V25000016NOGCLK@

1

Placement near to YH2

LAN_MDI1+ LAN_MDI1-

LAN_MDI0+ LAN_MDI0-

LAN_MDI0+

LAN_MDI2+ LAN_MDI2-

LAN_MDI0-

LAN_MDI3-

LAN_MDI3+ LAN_MDI3-

1

CL34

0.1U_0402_25V6

2

Place CL34 colse to LAN chip

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

12 12

LAN_X2

LAN_X2LAN_X1

3

1

CL27

NOGCLK@

2

Main: SP050006N00 2nd: SP050005W00

UL3

1

TD+

2

TD-

3

CT

4

NC

5

NC

6

CT

7

RD+ RD-8RX-

10/100M transformer_NS681695

UL4

1

TD+

2

TD-

3

CT

4

NC

5

NC

6

CT

7

RD+ RD-8RX-

10/100M transformer_NS681695

C

LL1

8111FVB@LL1

+LAN_REGOUT

2.2UH +-5% NLC252018T-2R2J-N

Layout Note: LL1 must be within 200mil to Pin36, CL13,CL9 must be within 200mil to LL1

8111FVB@

1 2

4.7U_0603_6.3V6K

1 2

LL2 0_0603_5%LL2 0_0603_5%

1U_0402_6.3V6K

8111FVB@

CL18

CL13

1

2

+LAN_EVDD10+LAN_VDD10

Close to Pin 21

+3V_LAN

1 2

LL3 0_0603_5%8111FVB@ LL3 0_0603_5%8111FVB@

4.7U_0603_6.3V6K

+3V_LAN

12

RL4

RL4 0_0402_5%

0_0402_5% 8111FVB@

ENSWREG

16

TX+

15

TX-

14

CT

13

NC

12

NC

11

CT

10

RX+

9

8111FVB@UL4

8111FVB@

16

TX+

15

TX-

14

CT

13

NC

12

NC

11

CT

10

RX+

9

2011/11/28 2013/12/31

8111FVB@

12

RL23

RL23 0_0402_5%

0_0402_5% 8105ELDO@

8105ELDO@

RJ45_MIDI1+ RJ45_MIDI1-

RJ45_MIDI0+ RJ45_MIDI0-

RJ45_MIDI2+ RJ45_MIDI2-

RJ45_MIDI3+ RJ45_MIDI3-

Compal Secret Data

CL39 1000P_0402_50V7KCL39 1000P_0402_50V7K

CL40 1000P_0402_50V7KCL40 1000P_0402_50V7K

CL41 1000P_0402_50V7K

CL42 1000P_0402_50V7K

CL28

8111FVB@

8105E-VL/VD 8111F/F-VB PWM Mode

RL4

0 ohm (Pull High)

NC 0 ohm

RL23

12

8111FVB@

12

8111FVB@

Deciphered Date

1

2

1 2

RL11 75_0402_1%RL11 75_0402_1%

1 2

RL12 75_0402_1%RL12 75_0402_1%

1 2

RL13 75_0402_1%

1 2

RL15 75_0402_1%

1

2

1

CL17

0.1U_0402_10V7K

2

+LAN_VDDREG

1

CL29

0.1U_0402_10V7K

2

8111FVB@

8105E-VL/VD

LDO Mode

(Pull Down)

8111FVB@

D

+LAN_VDD10

CL9

0.1U_0402_10V7K

0.1U_0402_10V7K 8111FVB@

8111FVB@

NC

RJ45_GND

+3V_LAN

+LAN_VDD10

For P/N and footprint Please place them to ISPD page

CL3 to CL6 close to Pin 27,39,47,48 CL7 to CL8 close to Pin 12,42

1 2

CL3 0.1U_0402_10V7KCL3 0.1U_0402_10V7K

1 2

CL4 0.1U_0402_10V7KCL4 0.1U_0402_10V7K

1 2

CL5 0.1U_0402_10V7KCL5 0.1U_0402_10V7K

1 2

CL6 0.1U_0402_10V7KCL6 0.1U_0402_10V7K

1 2

CL7 0.1U_0402_10V7K8111FVB@ CL7 0.1U_0402_10V7K8111FVB@

1 2

CL8 0.1U_0402_10V7K8111FVB@ CL8 0.1U_0402_10V7K8111FVB@

CL19, CL20,CL21 close to pin 13,29,45, respectively CL22 close to pin 3, respectively CL23,CL24,CL25 close to pin 6,9,41, respectively

1 2

CL19 0.1U_0402_10V7KCL19 0.1U_0402_10V7K

1 2

CL20 0.1U_0402_10V7KCL20 0.1U_0402_10V7K

1 2

CL21 0.1U_0402_10V7KCL21 0.1U_0402_10V7K

1 2

CL22 0.1U_0402_10V7K8111FVB@ CL22 0.1U_0402_10V7K8111FVB@

1 2

CL23 0.1U_0402_10V7K8111FVB@ CL23 0.1U_0402_10V7K8111FVB@

1 2

CL24 0.1U_0402_10V7K8111FVB@ CL24 0.1U_0402_10V7K8111FVB@

1 2

CL25 0.1U_0402_10V7K8111FVB@ CL25 0.1U_0402_10V7K8111FVB@

UL1

8105E-VD 10/100M

8105E-VD 10/100M 8105ELDO@

8105ELDO@

LAN Conn.

JRJ45

@JRJ45

RJ45_MIDI0+

1

RJ45_MIDI0-

2

RJ45_MIDI1+

3

RJ45_MIDI2+

4

RJ45_MIDI2-

5

RJ45_MIDI1-

6

RJ45_MIDI3+

7

RJ45_MIDI3-

8

CL36 1000P_1808_3KV7KCL36 1000P_1808_3KV7K

1 2

1

CL37

CL37 220P_0402_50V6K

220P_0402_50V6K

2

Title

SCHEMATIC,MB LA-8863

Size Document Number Rev

Custom

Date: Sheet

@

PR1+ PR1PR2+ PR3+ PR3PR2PR4+ PR4-

SANTA_130452-S

9

GND

10

GND

Compal Electronics, Inc.

4019IT

1

CL38

CL38 @

@

4.7U_0603_6.3V6K

2

E

3

LANGND

For ESD

1

D92

1

AZC199-02SPR7G_SOT23-3

@

223

3

D93

223

AZC199-02SPR7G_SOT23-3

AZC199-02SPR7G_SOT23-3 @

@

1

For ESD

32 51Friday, March 23, 2012

A

of

A

B

C

D

E

CardReader Conn.

JCRIO

@JCRIO

@

12

14 13 12 11 10

9 8 7 6 5 4 3 2 1

ACES_88058-120N

YT1

TPM9635@

GND GND 12 11 10 9 8 7 6 5 4 3 2 1

1 2

CLK_PCI_TPM_FCH<25>

RT8

TPM9655@

RT8

TPM9655@

0_0402_5%

TPM_XTALI

12

RT1

@RT1

@

10M_0402_5%

TPM_XTALO

LPC_AD0<25,36,37> LPC_AD1<25,36,37> LPC_AD2<25,36,37> LPC_AD3<25,36,37>

LPC_FRAME#<25,36,37>

LPC_RST#<25,36,37>

SERIRQ<25,36>

@

1 2

CT710P_0402_50V8J@CT710P_0402_50V8J RT11 0_0402_5%

RT11 0_0402_5%

B

CT2

0.1U_0402_10V7K

0.1U_0402_10V7K TPM9655@

TPM9655@

0.1U_0402_10V7K

2

CT2

TPM9635@

1

0.1U_0402_10V7K

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 LPC_FRAME# LPC_RST# LPC_PD# SERIRQ

@

1 2

RT4 10_0402_5%

1 2

TPM9635@

TPM_XTALO TPM_XTALI

USB20_P2<26>

USB20_N2<26>

USB20_P2

USB20_N2

1 2

0_0402_5%

@ LR9

@

4

1

WCM-2012-900T_0805

1 2

0_0402_5%

@

300_0402_5%

1 2

R73

RR67

LR9

3

2

RR66

@

10P_0402_50V8J

1 2

C290

USB20_P2_R

USB20_N2_R

Reserved for EHCI CRC errors

CT4

0.1U_0402_10V7K

0.1U_0402_10V7K TPM9655@

TPM9655@ CT5

CT5

0.1U_0402_10V7K

0.1U_0402_10V7K TPM9655@

TPM9655@

0.1U_0402_10V7K

2

1

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

CT4

TPM9635@

UT1

26

LAD0

23

LAD1

20

LAD2

17

LAD3

22

LFRAME#

16

LRESET#

28

LPCPD#

27

SERIRQ

21

LCLK

15

CLKRUN#

7

PP

14

XTALO

13

XTALI/32K IN

Issued Date

2

CT5

TPM9635@

1

24

VDD

SLB 9635 TT 1.2

GND

25

+3VS

12

RT13

RT13 0_0603_5%

0_0603_5% TPM9655@

+VDD_TPM

10

19

VDD

TESTB1/BADD

GND

11

18

TPM9655@

+VSB_TPM

5

VSB

6

GPIO

2

GPIO2

Base I/O Address 0 = 02Eh 1 = 04Eh*

RT5

8

TEST1

9

3

NC

12

NC

1

NC

GND

SLB 9635 TT 1.2_TSSOP28

4

TPM9635@

2011/11/28 2013/12/31

C

+VSB_TPM

TPM_GPIO TPM_GPIO2

TPM9635@

TPM9635@ 0_0402_5%

0_0402_5%

1 2

Compal Secret Data

2

CT8

TPM9635@

1

0.1U_0402_10V7K

TPM9655@

TPM9655@ 0_0402_5%

0_0402_5%

RT14

1 2

Deciphered Date

T61PAD @ T61PAD @ T62PAD @ T62PAD @

RT12 0_0603_5%

RT10 0_0603_5%

LPC_RST#

TPM9655@

TPM9635@

CT8

0.1U_0402_10V7K

0.1U_0402_10V7K TPM9655@

TPM9655@

TPM9635@

4.7K_0402_5%

12

+3VS

RT3

D

12

RT6

4.7K_0402_5%

4.7K_0402_5% @

@

1 2

+3VS

+3VALW

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC,MB LA-8863

4019IT

E

A

33 51Friday, March 23, 2012

of

1 1

+3VS

2 2

1 2

0_0603_5%

MIC_SENSE<35> NBA_PLUG<35>

HP_R<35> HP_L<35>

MIC1_L<35> MIC1_R<35>

@R3

@

R3

+3VS_CR USB20_N2_R

USB20_P2_R HP_R

HP_L MIC1_L

MIC1_R MIC_SENSE NBA_PLUG

TPM1.2 on board

1 2

CT1 22P_0402_50V8J

CT1 22P_0402_50V8J TPM9635@

TPM9635@

32.768KHZ_12.5P_1TJF125DP1A000D

3 3

+3VS

12

RT2

RT2 TPM9635@

TPM9635@

4.7K_0402_5%

4 4

4.7K_0402_5%

LPC_PD#

A

1 2

CT6 22P_0402_50V8J

CT6 22P_0402_50V8J TPM9635@

TPM9635@

+VSB_TPM

RT7

4.7K_0402_5%@

RT8

TPM9635@

TPM9635@ 0_0402_5%

0_0402_5%

+5VALW

RB73

4.7K_0402_5%

4.7K_0402_5% @

@

RB74

4.7K_0402_5%

4.7K_0402_5% @

D D

C C

@

SELCDP

SLP_CHG#1SELCDP

0

1

B B

USB30_TX0N<26>

USB30_TX0P<26>

5

12

USB20_DN10 USB20_DP10

CEN USB20_DN10 USB20_DP10 SELCDP

+5VALW

Pull-up for SLGC55584AV

12

RB75

4.7K_0402_5%

@

12

RB76

4.7K_0402_5%

1 2 3 4 9

U15

SLG55584AVTR_TDFN8_2X2

Pull-down for SLGC55584V

Function DCP autodetect with

X

mouse/keyboard wakeup

S0 charging with SDP only

0

S0 charging with CDP or SDP only

1

USB30_RX0N<26>

USB30_RX0P<26>

USB30_RX0P

1 2

CB22 0.1U_0402_16V7KCB22 0.1U_0402_16V7K

1 2

CB21 0.1U_0402_16V7KCB21 0.1U_0402_16V7K

USB30_TX0N_C

USB30_TX0P_C

1 2 1 2

@U15

@

CEN DM DP SELCDP Thermal Pad

0_0402_5% 0_0402_5%

0_0402_5%

CB

TDM

TDP

VDD

USB20_P10

RR45

SLP_CHG#

8

USB20_N10

7

USB20_P10

6 5

0.1U_0402_16V7K

1 2

LR1

4

1

KINGCORE WCM-2012HS-670T

1 2

LR2

4

1

KINGCORE WCM-2012HS-670T

1 2

USB20_N10

RR44

0_0402_5%

USB20_DP10

USB20_DN10

Reserved for EHCI CRC errors Reserved for EHCI CRC errors

@ RR19

@

@ RR32

@

@ CB25

CB25

RR19

0_0402_5%

3

2

RR20

0_0402_5%@

RR32

0_0402_5%

3

2

RR22

0_0402_5%@

4

SLP_CHG# <27> USB20_N10 <26> USB20_P10 <26>

1

2

4

1

12

R71

300_0402_5%

@

1

C288

10P_0402_50V8J

@

2

USB30_RX0N_LUSB30_RX0N

3

2

USB30_RX0P_L

USB30_TX0N_C_L

3

2

USB30_TX0P_C_L

+5VALW

1

@

CB49

10U_0603_6.3V6M

2

RR26

@ RR26

@

1 2

0_0402_5%

LR3

4

1

WCM-2012-900T_0805

1 2

3

2

RR25

0_0402_5%@

3

+5VALW

USB_CHG_EN#<36>

USB20_P10_L

3

2

USB20_N10_L USB20_N11_L

USB20_P10_L USB20_N10_L

USB_CHG_EN#

USB20_P11<26>

USB20_N11<26>

DR1

@

2

1

3

AZC199-02SPR7G_SOT23-3

2.5A

UR3

2 3 4 1

SY6288DCAC_MSOP8

SA00004KB00 SA00003TV00

1

IN IN EN/ENB GND

Change ESD Diode for EMI request

W=60mils

+USB_VCCB

6

OUT

7

OUT

8

OUT

5

OCB

USB20_P11

USB20_N11

USB30_TX0P_C_L USB30_TX0N_C_L USB30_RX0P_L USB30_RX0N_L

For EMI

12

CR38 1000P_0402_50V7KCR38 1000P_0402_50V7K

1

2

12

R72

R72 300_0402_5%

300_0402_5% @

@

1

C289

C289 10P_0402_50V8J

10P_0402_50V8J @

@

2

USB_OC1# <26>

CR39

4.7U_0805_10V4Z

4.7U_0805_10V4Z @

@

1 2

0_0402_5%@

WCM-2012-900T_0805

4

1

1 2 4 5 3

YSCLAMP0524P_SLP2510P8-10-9

@ RR39

@

1 2

0_0402_5%

DR7

1

1 2

2 4

4

3

8

LR4

RR38

3

2

RR39

@

3

2

10

10 9

9 7

7 65

65

USB20_P11_L

USB30_TX0P_C_L

9

USB30_TX0N_C_L

8

USB30_RX0P_L

7

USB30_RX0N_L

6

2

USB_EN#<30,36>

150uFx2 or 220uFx1

+USB_VCCB

+5VALW

+USB_VCCB

220U_6.3V_M

+USB_VCCC

1

+

CR47

CR47 @

@

2

220U_6.3V_M

1

@

PJ30

2

112

PAD-OPEN 2x2m

Q8

@

Q8

@

D

S

D

S

+USB_VCCC +USB_VCCB

@

1 2

R568 100K_0402_5%

USB_EN#

1 3

2

AO3413_SOT23

G

W=80mils

4.7U_0805_10V4Z

1

+

CR40

2

4.7U_0805_10V4Z

1

CR46

2

1000P_0402_50V7K

0.1U_0402_10V7K

1

CR45

2

1

CR44

2

W=80mils

4.7U_0805_10V4Z

1

CR42

2

USB30_TX0P_C_L USB30_TX0N_C_L

USB20_N10_L USB20_P10_L

USB30_RX0P_L USB30_RX0N_L

1

CR43

2

0.1U_0402_10V7K

1

CR41

CR41 1000P_0402_50V7K

1000P_0402_50V7K

2

JUSBA

9

SSTX+

1

VBUS

8

SSTX-

2

D-

7

GND

3

D+

6

SSRX+

4

GND

5

SSRX-

OCTEK_USB-09EAEB

OCTEK_USB-09EAEB @

@

GND GND GND GND

10 11 12 13

DR8

@

1

2

4

4 5

3

8

YSCLAMP0524P_SLP2510P8-10-9

Deciphered Date

10

9

8

7

65

6

USB30_TX1P_C_L USB30_TX1N_C_L USB30_RX1P_L USB30_RX1N_L

2

JUSBB

+USB_VCCC

USB30_TX1P_C_L USB30_TX1N_C_L

USB20_N11_L USB20_P11_L

USB30_RX1P_L USB30_RX1N_L

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC,MB LA-8863

4019IT

JUSBB

9

SSTX+

1

VBUS

8

SSTX-

2

D-

7

GND

3

D+

6

SSRX+

4

GND

5

SSRX-

OCTEK_USB-09EAEB

OCTEK_USB-09EAEB @

@

1

GND GND GND GND

10 11 12 13

A

34 51Friday, March 23, 2012

of

1 2

USB30_RX1N

USB30_RX1P

USB30_TX1N_C

USB30_TX1P_C

USB30_RX1N<26>

USB30_RX1P<26>

USB30_TX1N<26>

A A

USB30_TX1P<26>

CB24 0.1U_0402_16V7KCB24 0.1U_0402_16V7K

CB23 0.1U_0402_16V7KCB23 0.1U_0402_16V7K

5

@ RR42

@

1 2

0_0402_5%

LR5

4

1

KINGCORE WCM-2012HS-670T

1 2

0_0402_5%@

@ RR43

@

1 2

0_0402_5%

LR6

4

1

KINGCORE WCM-2012HS-670T

1 2

0_0402_5%@

RR42

3

2

RR40

RR43

3

2

RR41

3

2

3

2

4

USB30_RX1N_L

USB30_RX1P_L

USB30_TX1N_C_L

USB30_TX1P_C_L

USB30_TX1P_C_L USB30_TX1N_C_L USB30_RX1P_L USB30_RX1N_L

USB20_P11_L USB20_N11_L

DR4

@

2

1

3

AZC199-02SPR7G_SOT23-3

Change ESD Diode for EMI request

Security Classification

2011/11/28 2013/12/31

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/11/28 2013/12/31

3

Compal Secret Data

A

UA1

MIC2_R MIC2_L

UA1

22 21

17 16

31 30 29

15 14

20 12 10 11

19 28 27 34 35 36

2 3

13 18

47

4

MIC1_R_R MIC1_R_L

+MIC1_VREFO_L +MIC1_VREFO_R

1 1

+MIC2_VREFO

CA584.7U_0603_6.3V6K CA584.7U_0603_6.3V6K CA574.7U_0603_6.3V6K CA574.7U_0603_6.3V6K

MIC1_R_C_R MIC1_R_C_L

MONO_IN

1 2

0.01U_0402_25V7K

0.01U_0402_25V7K CA65

@CA65

@

AZ_RST_HD#<26>

1 2

close to pin 28

CA6010U_0603_6.3V6M CA6010U_0603_6.3V6M

1 2

AC_VREF

1

CA55

0.1U_0402_10V7K

2 2

2

INT_MIC_CLK<22>

CA56

2.2U_0603_6.3V6K

2

@

RA34 20K_0402_1%

@

CA59 100P_0402_50V8JCA59 100P_0402_50V8J

AZ_SYNC_HD<26>

INT_MIC_DATA<22>

12

EC_MUTE#<36>

For EMI

RA42

FBMA-10-100505-301T

1

2

INT_MIC_CLK_R

CAM@

CA52

CAM@CA52

CAM@

220P_0402_50V7K

close to pin19

AC_JDREF

RA30

12

20K_0402_1%

CPVEE

12

CA54 2.2U_0603_10V6KCA54 2.2U_0603_10V6K

12

CA53 2.2U_0603_10V6KCA53 2.2U_0603_10V6K

INT_MIC_CLK_R

SENSE_A SENSE_B

+MIC2_VREFO

Analog MIC

12

RA24

4.7K_0402_5%

4.7K_0402_5% AMIC@

AMIC@

AMIC@ CA26

3 3

MIC2_L

MIC2_R

CA26 1U_0402_6.3V4Z

1U_0402_6.3V4Z

12

1U_0402_6.3V4Z

12

CA28

CA28 AMIC@

AMIC@

AMIC@ RA25

RA25 1K_0402_5%

1K_0402_5%

12

1K_0402_5%

12

RA26

RA26 AMIC@

AMIC@

close to Codec

INT_MIC

CA27

1 2

220P_0402_50V7K

AMIC@

1

@

470P_0402_50V8J

2

B

MIC1_R MIC1_L

MIC2_R MIC2_L

MIC1_VREFO_L MIC1_VREFO_R MIC2_VREFO

LINE2_R LINE2_L

MONO_OUT PCBEEP SYNC RESET#

JDREF LDO_CAP VREF CPVEE CBN CBP

GPIO0/DMIC_DATA GPIO1/DMIC_CLK

SENSE_A SENSE_B

EAPD PD#

ALC259-VC2-CG_MQFN48_6X6

CA6

@

@ 470P_0402_50V8J

470P_0402_50V8J

DVDD_IO

SPK_OUT_R+

SPK_OUT_R-

SPK_OUT_L+

SPK_OUT_L-

HPOUT_R

HPOUT_L

SDATA_OUT

SDATA_IN

Thermal Pad

JMIC

1

2

3

GND

4

GND

ACES_50271-0020N-001

@

1

CA5

2

DVDD

AVDD1 AVDD2

PVDD1 PVDD2

BCLK

AVSS1 AVSS2 PVSS1 PVSS2

DVSS

1 9

25 38

39 46

45 44

40 41

33 32

5 8

6

23

NC

24

NC

48

NC

26 37 42 43 7

49

+DVDD_IO +3VS_DVDD

+AVDD +AVDD

+PVDD +PVDD

SPKR+ SPKR-

SPKL+ SPKL-

75_0402_1%

RA19

RA19 RA20

RA20

75_0402_1%

AZ_SDIN0_HD_R

AZ_BITCLK_HD

DGND

2W 4ohm =40mil 1W 8ohm =20mil

C

35mA for 3.3V level

1 2

+3VS

RA28 0_0603_5%RA28 0_0603_5%

10U_0603_6.3V6M

RA17

12

0_0603_5%

10U_0603_6.3V6M

place close to chip

AZ_SDOUT_HD <26>

AZ_SDIN0_HD <26>

AZ_BITCLK_HD <26>

@

AZ_BITCLK_HD

HP_R <33> HP_L <33>

12

RA23 33_0402_5%RA23 33_0402_5%

@

12

RA2910_0402_5%@RA2910_0402_5%

+3VS

CA51

1 2

10P_0402_50V8J

AGND

placement near Audio Codec

LA7

SPKL+

SPKL-

SPKR+

SPKR- SPK_R2

LA7

0_0603_5%

LA8

0_0603_5%

LA9

0_0603_5%

LA10

0_0603_5%

12

2 CA71

CA71

@

10U_0603_6.3V6M

1 2

CA72

@

10U_0603_6.3V6M

1

12

2 CA76

CA76

@

10U_0603_6.3V6M

1 2

CA75

@

10U_0603_6.3V6M

1

12

SPK_L1SPK_L1

2

CA74

CA74 1U_0402_6.3V4Z

1U_0402_6.3V4Z @

@

1

SPK_L2

SPK_R1

2

CA73

CA73 1U_0402_6.3V4Z

1U_0402_6.3V4Z @

@

1

SPK_R2

0.1U_0402_16V4Z

1

CA3

2

1

CA46

2

For EMI please place near codec

1

CA4

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z 1

CA45

2

+DVDD_IO

+3VS_DVDD

D

+AVDD

1

CA33 0.1U_0402_10V7KCA33 0.1U_0402_10V7K

close to pin39

2

1

CA32 0.1U_0402_10V7KCA32 0.1U_0402_10V7K

2

EC Beep

EC_BEEP#<36>

PCI Beep

FCH_SPKR<26>

EC_MUTE#

To solve noise issue

close to pin 25 close to pin 38

2

CA42

1

10U_0603_6.3V6M

+PVDD

CA35

Internal AMP

EC_MUTE#

Enable

Hight

Disable

LOW

RA50

4.7K_0402_5%

1 2

Ext.MIC/LINE IN JACK

MIC1_R_R

MIC1_R_L

0.1U_0402_10V7K

0.1U_0402_10V7K 1

CA47

2

1 10U_0603_6.3V6M

10U_0603_6.3V6M

2

CA37

2

1

10U_0603_6.3V6M

LA6

1 2

PBY160808T-601Y-N_2P

RA51

1 2 47K_0402_5%

47K_0402_5%

RA52

1 2 47K_0402_5%

47K_0402_5%

4.7K_0402_5%

RA47

1K_0402_5%

RA48 2.2K_0402_5%RA48 2.2K_0402_5%

12

1K_0402_5%

RA45

RA46 2.2K_0402_5%RA46 2.2K_0402_5%

0.1U_0402_10V7K

0.1U_0402_10V7K 1

CA50

2

0.1U_0402_10V7K

CA34

RA49

1 2

12

E

1 2

0_0603_5%

1

CA39

@

10U_0603_6.3V6M

2

1

CA36

10U_0603_6.3V6M

2

Beep sound

CA70

1 2

0.1U_0402_10V7K

CA69

100P_0402_50V8J

+MIC1_VREFO_R

+MIC1_VREFO_L

RA18

+5VS

MONO_IN

MIC1_R <33>

MIC1_L <33>

+5VS

Add CA5 and CA6 for EMI request on PVT

SPK Conn.

Sense Pin

SENSE A

4 4

Impedance

39.2K 20K 10K

5.1K

39.2K 20K 10K

A

Codec Signals

PORT-I (PIN 32, 33) PORT-B (PIN 21, 22) PORT-C (PIN 23, 24) (PIN 48) PORT-E (PIN 14, 15) PORT-F (PIN 16, 17)SENSE B PORT-H (PIN 20)

Function

Headphone out Ext. MIC

Analog MIC

B

place close to chip

MIC_SENSE<33>

NBA_PLUG<33>

RA32 20K_0402_1%RA32 20K_0402_1%

RA33 39.2K_0402_1%RA33 39.2K_0402_1%

CA63 0.1U_0603_50V7KCA63 0.1U_0603_50V7K

SENSE_A

12

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1 2

CA61 0.1U_0603_50V7KCA61 0.1U_0603_50V7K

1 2

CA66 0.1U_0603_50V7KCA66 0.1U_0603_50V7K

1 2

CA62 0.1U_0603_50V7KCA62 0.1U_0603_50V7K

1 2

RA31 0_0603_5%RA31 0_0603_5%

2011/11/11 2012/12/31

C

Compal Secret Data

Deciphered Date

D

Add bypass caps for EMI request on PVT

@

CA64 0.1U_0603_50V7K

1 2

@

CA67 0.1U_0603_50V7K

1 2

SPK_R1 SPK_R2 SPK_L1 SPK_L2

@

CA77 0.1U_0603_50V7K

1 2

@

CA68 0.1U_0603_50V7K

1 2

Title

Size Document Number Rev

Custom

Date: Sheet

DA10 AZ5125-02S.R7G_SOT23-3

2

1

3

@

2

1

3

DA11 AZ5125-02S.R7G_SOT23-3

DA11 AZ5125-02S.R7G_SOT23-3 @

@

Compal Electronics, Inc.

SCHEMATIC,MB LA-8863

4019IT

E

JSPK

1

2

3

4

ACES_85204-0400N

ACES_85204-0400N @

@

of

35 51Friday, March 23, 2012

A

5

0.1U_0402_10V7K

1

CB1

0.1U_0402_10V7K

For EMI

0.1U_0402_10V7K 2

12

RB3

10_0402_5%

@

D D

+3VL

C C

+3VL +3VL

+3VS

B B

@

1

CB11

22P_0402_50V8J

@

2

RB2

47K_0402_5%

1 2

CB12 0.1U_0402_10V7KCB12 0.1U_0402_10V7K

RP7

RP7 1 8 2 7 3 6 4 5

2.2K_0804_8P4R_5%

1 2

RB135 2.2K_0402_5%RB135 2.2K_0402_5%

1 2

RB136 2.2K_0402_5%RB136 2.2K_0402_5%

@

LPC_RST#

1 2

CB13 1U_0402_6.3V6K

@

1 2

CB14 180P_0402_50V8J

EC_RST#

EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2

EC_SMB_CK3 EC_SMB_DA3

SUSP#

Add WLAN_PWR# on DVT

KSI[0..7]<37>

KSO[0..15]<37>

RTC_CLK<25,28>

GATEA20<26>

KB_RST#<26>

SERIRQ<25,33>

LPC_FRAME#<25,33,37>

LPC_AD3<25,33,37> LPC_AD2<25,33,37> LPC_AD1<25,33,37> LPC_AD0<25,33,37>

CLK_PCI_EC<25,28>

LPC_RST#<25,33,37>

EC_SCI#<26>

WLAN_PWR#<31>

KSI[0..7] KSO[0..15]

EC_SMB_CK1<40,41> EC_SMB_DA1<40,41> EC_SMB_CK2<9,13> EC_SMB_DA2<9,13>

EC_SMI#<26>

EC_PXCONTROL<26> USB_CHG_EN#<34>

BT_CTRL<31>

FAN_SPEED1<5>

WL_OFF#<31> E51_TXD<31>

E51_RXD<31>

FCH_PWRGD<26>

PWR_SUSP_LED#<38>

RB20 0_0402_5%

1 CB2

CB2

CB4

2

0.1U_0402_10V7K

SLP_S3#<26> SLP_S5#<26>

@

1 2

0.1U_0402_10V7K

1

2

EC_PXCONTROL

T14T14

100K_0402_5%

Close to EC

RB27

100K_0402_5%

1 2

A A

E51_TXD

Voltage Comparator Pins FOR 9012 A3

VCIN0 pin109 VCIN1 pin102

VCOUT0 pin104

VCOUT1 pin103

5

4

1

1 CB5

CB5

CB6

CB6 2

2

1000P_0402_50V7K

GATEA20 KB_RST# SERIRQ LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0

CLK_PCI_EC LPC_RST# EC_RST# EC_SCI# WLAN_PWR#

KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6

KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9

KSO10 KSO11 KSO12 KSO13 KSO14 KSO15

EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2

SLP_S3# SLP_S5# EC_SMI#

USB_CHG_EN# BT_CTRL

FAN_SPEED1 WL_OFF# E51_TXD E51_RXD FCH_PWRGD PWR_SUSP_LED#

XCLKO

12

1

RB22

2

>1.2V <1.2V

HIGH

LOW

4

1000P_0402_50V7K

1 CB7

CB7

2

UB1

1

GATEA20/GPIO00

2

KBRST#/GPIO01

3

SERIRQ

4

LPC_FRAME#

5

LPC_AD3

7

LPC_AD2

8

LPC_AD1

10

LPC & MISC

LPC_AD0

12

CLK_PCI_EC

13

PCIRST#/GPIO05

37

EC_RST#

20

EC_SCII#/GPIO0E

38

GPIO1D

55

KSI0/GPIO30

56

KSI1/GPIO31

57

KSI2/GPIO32

58

KSI3/GPIO33

59

KSI4/GPIO34

60

KSI5/GPIO35

61

KSI6/GPIO36

62

KSI7/GPIO37

39

KSO0/GPIO20

40

KSO1/GPIO21

41

KSO2/GPIO22

42

KSO3/GPIO23

43

KSO4/GPIO24

44

KSO5/GPIO25

45

KSO6/GPIO26

46

KSO7/GPIO27

47

KSO8/GPIO28

48

KSO9/GPIO29

49

KSO10/GPIO2A

50

KSO11/GPIO2B

51

KSO12/GPIO2C

52

KSO13/GPIO2D

53

KSO14/GPIO2E

54

KSO15/GPIO2F

81

KSO16/GPIO48

82

KSO17/GPIO49

77

EC_SMB_CK1/GPIO44

78

EC_SMB_DA1/GPIO45

79

EC_SMB_CK2/GPIO46

80

EC_SMB_DA2/GPIO47

6

PM_SLP_S3#/GPIO04

14

PM_SLP_S5#/GPIO07

15

EC_SMI#/GPIO08

16

GPIO0A

17

GPIO0B

18

GPIO0C

19

GPIO0D

25

EC_INVT_PWM/GPIO11

28

FAN_SPEED1/GPIO14

29

EC_PME#/GPIO15

30

EC_TX/GPIO16

31

EC_RX/GPIO17

32

PCH_PWROK/GPIO18

34

SUSP_LED#/GPIO19

36

NUM_LED#/GPIO1A

122

XCLKI/GPIO5D

123

XCLKO/GPIO5E

CB16

CB16 20P_0402_50V8

20P_0402_50V8

LOW

HIGH

+3VL

Int. K/B

Int. K/B Matrix

Matrix

9

EC_VDD/VCC

PS2 Interface

SM Bus

+3VL

22

33

96

125

67

111

EC_VDD0

EC_VDD/VCC

EC_VDD/AVCC

PWM Output

AD Input

DA Output

CPU1.5V_S3_GATE/GPXIOA00

SPI Device Interface

SPI Flash ROM

BATT_CHG_LED#/GPIO52

GPIO

BATT_LOW_LED#/GPIO55

EC_RSMRST#/GPXIOA03 EC_LID_OUT#/GPXIOA04

PROCHOT_IN/GPXIOA05

H_PROCHOT#_EC/GPXIOA06

VCOUT0_PH/GPXIOA07

GPO

GPIO

PBTN_OUT#/GPXIOA09

PCH_APWROK/GPXIOA10

SA_PGOOD/GPXIOA11

GPI

PECI_KB9012/GPXIOD07

GND/GND

AGND/AGND

GND/GND

GND0

11

24

35

69

94

113

RB36

EC_ON_R

RB36

1 2

2.2K_0402_5%

CB3

0.1U_0402_10V7K

1 2

GPIO0F

BEEP#/GPIO10

GPIO12

ACOFF/GPIO13

BATT_TEMP/GPIO38

GPIO39

ADP_I/GPIO3A

GPIO3B GPIO42

IMON/GPIO43

DAC_BRIG/GPIO3C

EN_DFAN1/GPIO3D

IREF/GPIO3E

CHGVADJ/GPIO3F

EC_MUTE#/GPIO4A

USB_EN#/GPIO4B

CAP_INT#/GPIO4C

EAPD/GPIO4D

TP_CLK/GPIO4E

TP_DATA/GPIO4F

WOL_EN/GPXIOA01

ME_EN/GPXIOA02

VCIN0_PH/GPXIOD00

SPIDI/GPIO5B

SPIDO/GPIO5C SPICLK/GPIO58 SPICS#/GPIO5A

ENBKL/GPIO40

PECI_KB930/GPIO41

FSTCHG/GPIO50

CAPS_LED#/GPIO53

PWR_LED#/GPIO54

SYSON/GPIO56 VR_ON/GPIO57

PM_SLP_S4#/GPIO59

BKOFF#/GPXIOA08

AC_IN/GPXIOD01

EC_ON/GPXIOD02

ON/OFF/GPXIOD03

LID_SW#/GPXIOD04

SUSP#/GPXIOD05

GPXIOD06

V18R

KB9012QF-A3_LQFP128_14X14

1

2

For KB9012 EC_ON low pulse work around

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

WL_BT_LED#

21

EC_BEEP#

23 26 27

BATT_TEMPA

63 64

ADP_I

65 66 75

EC_ENBKL

76

68

EN_DFAN1

70 71 72

EC_MUTE#

83

USB_EN#

84

EC_SMB_CK3

85

EC_SMB_DA3

86

TP_CLK

87

TP_DATA

88

VGATE

97

WOL_EN#

98 99

VCIN0_PH

109

119 120 126 128

73 74 89

BATT_FULL_LED#

90

WLAN_RST#

91 92

BATT_CHG_LOW_LED#

93

SYSON

95

VR_ON

121 127

EC_RSMRST#

100

EC_LID_OUT#

101

PROCHOT_IN

102

H_PROCHOT_EC

103

VCOUT0_PH_L

104

BKOFF#

105

PBTN_OUT#

106

FCH_PWR_EN

107 108

ACIN_D

110

EC_ON_R

112

ON/OFFBTN#

114

LID_SW#

115

SUSP#

116

VGA_SEL

117 118

+EC_V18R

124

EC_ON <42>

1U_0402_6.3V6K

1U_0402_6.3V6K CB50

CB50

3

2

WL_BT_LED# <38> EC_BEEP# <35>

BATT_TEMPA <40> ADP_I <40,41>

EC_ENBKL <21>

EN_DFAN1 <5>

EC_MUTE# <35>

USB_EN# <30,34>

EC_SMB_CK3 <21> EC_SMB_DA3 <21>

TP_CLK <38>

TP_DATA <38>

VGATE <47>

WOL_EN# <32>

VCIN0_PH <40>

BATT_FULL_LED# <38> WLAN_RST# <31>

SYSON <39,43> VR_ON <39,46,47>

EC_RSMRST# <26> EC_LID_OUT# <26> PROCHOT_IN <40>

BKOFF# <22>

PBTN_OUT# <26>

ON/OFFBTN# <30,38> LID_SW# <38>

SUSP# <39,43,44>

1

CB15

4.7U_0805_10V4Z

2

2011/11/28 2013/12/31

VCIN0_PH connect to power portion (9012 only)

Add WLAN_RST# on DVT

BATT_CHG_LOW_LED# <38>

PROCHOT_IN connect to power portion (9012 only)

+3VL

VGA_SEL

Pin117

Address

High Low

HIGH

82h

Compal Secret Data

Deciphered Date

FCH_PWR_EN <39,44>

RB24

RB24 10K_0402_5%

10K_0402_5%

TH@

1 2

RB25

RB25 10K_0402_5%

10K_0402_5%

CH@

1 2

LOW

9Ah

2

H_PROCHOT_EC

High Active

H_PROCHOT_EC

1

BATT_TEMPACLK_PCI_EC

ACIN_D

LID_SW#

TP_CLK

TP_DATA

SYSON

VCOUT0_PH_L

VCOUT0_PH connect to power portion (9012 only)

ACIN_D

SUSP#

VR_ON

2

G

@

1 2

RB6 10K_0402_5%

Title

Size Document Number Rev

Date: Sheet

1 2

CB9 100P_0402_50V8JCB9 100P_0402_50V8J

1 2

CB10 100P_0402_50V8JCB10 100P_0402_50V8J

1 2

RB35 47K_0402_5%RB35 47K_0402_5%

1 2

RB8 4.7K_0402_5%RB8 4.7K_0402_5%

1 2

RB9 4.7K_0402_5%RB9 4.7K_0402_5%

1 2

RB10 4.7K_0402_5%RB10 4.7K_0402_5%

@

1 2

RB34 0_0402_5%

RB18

330K_0402_5%

12

+3VL

12

DB1RB751V40_SC76-2 DB1RB751V40_SC76-2

1 2

RB21 10K_0402_5%RB21 10K_0402_5%

1 2

RB23 10K_0402_5%RB23 10K_0402_5%

13

D

Q34

Q34 2N7002K_SOT23-3

2N7002K_SOT23-3

S

Compal Electronics, Inc.

Friday, March 23, 2012

H_PROCHOT# <7,47>

Low Active (+1.5V)

+3VS

SCHEMATIC,MB LA-8863

4019IT

1

+3VL

+5VS

VS_ON <42>

ACIN <13,41>

36 51

A

of

1

2

3

4

5

6

7

8

LPC Debug Port

JDB

@JDB

@

1

2

GND GND

3

4

5

6

7

8

9

10

11 12

A A

E-T_3801K-F10N-01L

+3VS

CLK_PCI_DDR

LPC_RST# <25,33,36> CLK_PCI_DDR <25,28>

LPC_FRAME# <25,33,36> LPC_AD3 <25,33,36> LPC_AD2 <25,33,36> LPC_AD1 <25,33,36> LPC_AD0 <25,33,36>

C457

1 2

22P_0402_50V8J

@

For EMI

R393

1 2

22_0402_5%

22_0402_5% @

@

CLK_PCI_DDR

B B

C C

D D

KEYBOARD CONN.

JKB

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

26

GND

24

27

GND

25

ACES_50524-02501-001

ACES_50524-02501-001 @

@

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

KSI[0..7]

KSO[0..15]

KSO15 KSO14 KSO13 KSO12 KSO11 KSO10 KSO9 KSO8 KSO7 KSI7 KSI6 KSO6 KSI5 KSO5 KSI4 KSI3 KSI2 KSI1 KSO4 KSI0 KSO3 KSO2 KSO1 KSO0

KSI[0..7] <36>

KSO[0..15] <36>

KSO2 KSO1 KSO0 KSO4 KSO3 KSO5

KSO14

KSO6 KSO7

KSO13

KSO8

KSO9 KSO10 KSO11 KSO12 KSO15 KSI7 KSI2 KSI3 KSI4 KSI0 KSI5 KSI6 KSI1

For EMI

Close to JKB

1 2

C404 100P_0402_50V8JC404 100P_0402_50V8J

1 2

C405 100P_0402_50V8JC405 100P_0402_50V8J

1 2

C406 100P_0402_50V8JC406 100P_0402_50V8J

1 2

C407 100P_0402_50V8JC407 100P_0402_50V8J

1 2

C408 100P_0402_50V8JC408 100P_0402_50V8J

1 2

C409 100P_0402_50V8JC409 100P_0402_50V8J

1 2

C410 100P_0402_50V8JC410 100P_0402_50V8J

1 2

C411 100P_0402_50V8JC411 100P_0402_50V8J

1 2

C412 100P_0402_50V8JC412 100P_0402_50V8J

1 2

C413 100P_0402_50V8JC413 100P_0402_50V8J

1 2

C415 100P_0402_50V8JC415 100P_0402_50V8J

1 2

C416 100P_0402_50V8JC416 100P_0402_50V8J

1 2

C417 100P_0402_50V8JC417 100P_0402_50V8J

1 2

C418 100P_0402_50V8JC418 100P_0402_50V8J

1 2

C419 100P_0402_50V8JC419 100P_0402_50V8J

1 2

C420 100P_0402_50V8JC420 100P_0402_50V8J

1 2

C421 100P_0402_50V8JC421 100P_0402_50V8J

1 2

C422 100P_0402_50V8JC422 100P_0402_50V8J

1 2

C423 100P_0402_50V8JC423 100P_0402_50V8J

1 2

C424 100P_0402_50V8JC424 100P_0402_50V8J

1 2

C425 100P_0402_50V8JC425 100P_0402_50V8J

1 2

C427 100P_0402_50V8JC427 100P_0402_50V8J

1 2

C429 100P_0402_50V8JC429 100P_0402_50V8J

1 2

C431 100P_0402_50V8JC431 100P_0402_50V8J

1

2

3

Security Classification

2011/11/28 2013/12/31

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

2011/11/28 2013/12/31

Compal Secret Data

Deciphered Date

5

6

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC,MB LA-8863

4019IT

Friday, March 23, 2012

7

of

37 51

of

37 51

of

37 51

8

A

5

4

3

2

1

Power Button

D D

TOP side

BOT side

C C

For debug

SW4

1 2

SW3

SMT1-05-A_4P

5

6

SMT1-05-A_4P

5

6

HDD LED

R404

+3VS

HDD_LED#

12

10K_0402_5%

5

3

Q9B 2N7002DW-T/R7_SOT363-6Q9B 2N7002DW-T/R7_SOT363-6

+3VL

R395

R395 100K_0402_5%

100K_0402_5%

3 4

6 1

4

1 2

R50 0_0402_5%

1 2

1

C458

0.1U_0402_25V6

0.1U_0402_25V6 @

@

2

For EMI request

2

Q9A

Q9A 2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

@

ON/OFFBTN#

ON/OFFBTN# <30,36>

SATA_LED# <27>

Touchpad Connector

+5VS +5VALW+3VL

TP_CLK<36> TP_DATA<36>

LID_SW#<36>

BATT_FULL_LED#<36>

BATT_CHG_LOW_LED#<36>

PWR_SUSP_LED#<36>

WL_BT_LED#<36>

Screw Hole

TP

H17

H_3P0N

H_3P0N @

@

1

TP_CLK TP_DATA

LID_SW# BATT_FULL_LED# BATT_CHG_LOW_LED# PWR_SUSP_LED# HDD_LED# WL_BT_LED#

H20

H_3P0N

H_3P0N @

@

1

H1

H_4P2

H_4P2 @

@

1

JTP

@JTP

@

1

2

3

4

5

6

7

8

9

10

11 12

13

G1

11

14

G2

12

ACES_50504-0120N-001

H2

1

H_4P6

H_4P6 @

@

H3

1

H_4P2x4P6

H_4P2x4P6 @

@

VGACPU

H5

1

H_3P5

H_3P5 @

@

H5

H_3P0

H_3P0 @

@

1

H4

FCH

H8

1

H_3P0

H_3P0 @

@

PTH

H12

H10

H11

H7

B B

ISPD

U1

HUDM3R1@U1

HUDM3R1@

SA000043IN0

218-0755042 A13 HUDSON-M3

U1

HUDM3UNBW@U1

UV1

CHUNBW@UV1

CHUNBW@

SA000056220

CHELSEA PRO

UV1

THUNBW@UV1

THUNBW@

SA00004WI70

THAMES XT

A A

THAMES XT

SA000043IO0

DA80000ST00

5

4

HUDM3UNBW@

218-0755042 A13 HUDSON-M3

ZZZ

PCB LA-7291P

PJP1

45@PJP1

45@

H18

H_3P0

H_3P0 @

@

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

H7

H_3P0

H_3P0 @

@

1

2011/11/28 2013/12/31

3

H11

H_3P0

H_3P0 @

@

1

PCB Fedical Mark PAD

FD1@FD1

@

Compal Secret Data

H12

H_3P0

H_3P0 @

@

1

FD2@FD2

@

1

Deciphered Date

1

@

H_3P0

H_3P0 @

@

FD3@FD3

1

H13

FD4@FD4

@

1

H_3P0

H_3P0 @

@

H14

2

1

H_3P0

H_3P0 @

@

H15

H21

H_3P0

1

H_3P0 @

@

H_3P0

H_3P0 @

@

1

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

SCHEMATIC,MB LA-8863

4019IT

Monday, March 26, 2012

H9

1

NPTH

H_3P0x4P0N

H_3P0x4P0N @

@

1

H16

H_3P0N

H_3P0N @

@

1

of

38 51

of

38 51

of

38 51

A

+3VALW TO +3VS +5VALW TO +5VS

+3VALW +3VS

Q29

1

8

S

D

2

7

S

D

3

6

S

D

4

5

G

1 1

D

SI4800BDY_SO8

1

C465

2

4.7U_0805_10V4Z

1

2

0.022U_0402_25V7K

Vgs=10V,Id=9A,Rds=18.5mohm

1

C459

2

1U_0402_6.3V6K

12

C466

R412

R412 820K_0402_5%

820K_0402_5%

4.7U_0805_10V4Z

1

C460

2

R409

1 2

61

+VSB

120K_0402_5%

Q10A

SUSP SUSP SUSP

2

2N7002DW-T/R7_SOT363-6

R406

470_0805_5%

1 2 3

Q10B

5

4

B

C

D

E

+1.5V to +1.5VS

+5VALW

8 7 6 5

SI4800BDY_SO8

1

C467

2

4.7U_0805_10V4Z

Q30

1

S

D D D D

S S G

1U_0402_6.3V6K

2 3 4

1

C468

2

0.01U_0402_25V7K

12

Vgs=10V,Id=9A,Rds=18.5mohm

+5VS

1

C461

2

1 2

61

R413

R413 820K_0402_5%

820K_0402_5%

4.7U_0805_10V4Z

1

C462

2

R418

+VSB

120K_0402_5%

Q11A

2

2N7002DW-T/R7_SOT363-6

+5VS

R407

470_0805_5%

1 2 3

0.1U_0402_16V4Z

Q11B

5

4

For EMI

2

C821

C822

@

1

0.1U_0402_16V4Z

Vgs=10V,Id=9A,Rds=18.5mohm

+1.5V

8 7 6 5

SI4800BDY_SO8

1

C469

2

4.7U_0805_10V4Z

Q31

D D D D

S S S G

C470

1 2 3 4

1

2

+1.5VS

1

C463

2

1U_0402_6.3V6K

0.1U_0402_25V6

12

R414

R414 820K_0402_5%

820K_0402_5%

4.7U_0805_10V4Z

1

C464

2

R411

1 2

220K_0402_5%

61

2N7002DW-T/R7_SOT363-6

+VSB

Q12A

2

2N7002DW-T/R7_SOT363-6

R408

5

470_0805_5%

1 2 3

Q12B

4

+1.1VALW to +1.1VS

+1.1VS

R417

Vgs=10V,Id=14.5A,Rds=6mohm

+1.1VALW

Q44

8

D

7

D

6

D

5

D

FDS6676AS_SO8

2 2

3 3

4 4

1

C474

2

4.7U_0805_10V4Z

G

S S S

C477

1 2 3 4

1

2

+1.1VS

1

C476

2

1U_0402_6.3V6K

0.1U_0402_25V6

12

R416

R416 820K_0402_5%

820K_0402_5%

2N7002DW-T/R7_SOT363-6

4.7U_0805_10V4Z

1

C472

2

R415

1 2

220K_0402_5%

61

Q209A

2

SUSP

+VSB

1 2

R385 0_0402_5%R385 0_0402_5%

2

C200

0.1U_0402_16V4Z

0.1U_0402_16V4Z @

@

1

Need to delay after +3VS ramp up

R417 470_0805_5%

470_0805_5%

1 2 3

Q209B

5

2N7002DW-T/R7_SOT363-6

4

SUSP

+5VALW

R5545

100K_0402_5%

5

R5529

100K_0402_5%

1 2

3

Q32B

2N7002DW-T/R7_SOT363-6

4

Q210B

2N7002DW-T/R7_SOT363-6

+5VS_ODD

R457

R457 470_0805_5%

470_0805_5%

1 2 61

Q53A

2

2N7002DW-T/R7_SOT363-6

ODD_PWR<27>

ODD_PWR#

FCH_PWR_EN#<28>

FCH_PWR_EN<36,44>

FCH_PWR_EN#

12

+0.75VS

R477

R477 470_0805_5%

470_0805_5%

1 2 3

Q6B

2N7002DW-T/R7_SOT363-6

+1.5V

R478

R478 470_0805_5%

470_0805_5%

1 2 3

100K_0402_5%

SYSON# VR_ON#

5

4

SYSON<36,43> VR_ON<36,46,47>

SUSP

5

4

+5VALW

R432

1 2 61

Q210A

2

2N7002DW-T/R7_SOT363-6

SUSP#<36,43,44>

2N7002DW-T/R7_SOT363-6

+5VS TO +5VS_ODD

Vgs=-4.5V,Id=3A,Rds<97mohm

+5VALW

2

C471

R441

R441 100K_0402_5%

100K_0402_5%

1 2

ODD_PWR#

3

Q53B

Q53B 2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

5

4

R440

1 2

47K_0402_5%

C471

0.1U_0402_16V7K

1

2

C217

0.01U_0402_25V7K

1

4.7U_0805_10V4Z

Q211B

SUSP

2

2N7002DW-T/R7_SOT363-6

+1.2VS

R479

R479 470_0805_5%

470_0805_5%

1 2 3

5

4

+5VS

S

Q45

G

2

D

1 3

AO3413_SOT23

1

C679

2

@

+5VALW

R422

R422 100K_0402_5%

100K_0402_5%

1 2 61

Q6A

+5VALW

R448

100K_0402_5%

2

2N7002DW-T/R7_SOT363-6

2

PJ28

2

JUMP_43X79

JUMP_43X79 @

@

1

C680

C680 1U_0402_6.3V6K

1U_0402_6.3V6K

2

1 2 61

Q211A

+5VS_ODD

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2011/11/28 2013/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC,MB LA-8863

4019IT

E

39 51Friday, March 23, 2012

A

of

A

PL1

HCB2012KF-121T50_0805

1 2

PL2

HCB2012KF-121T50_0805

1 2

HCB2012KF-121T50_0805

1 2

12

PC2

100P_0402_50V8J

VMB

12

PC5

PC5 1000P_0402_50V7K

1000P_0402_50V7K

PD2

@PD2

@

PJSOT24CW_SOT323-3

2

1

3

12

PC3

1000P_0402_50V7K

PL3

HCB2012KF-121T50_0805

1 2

PL4

HCB2012KF-121T50_0805

1 2

ADPIN

@

PJP1

1 1

SINGA_2DW-0005-B03

2 2

CCM_C250137GR007M262ZR

1

+

2

+

3

-

4

-

PJP2

1

2

EC_SMCA

3

EC_SMDA

4

TS_A

5

6

7

12

1

2

3

PC1

1000P_0402_50V7K

PD1

@

PJSOT24CW_SOT323-3

PR10 100_0402_1%PR10 100_0402_1%

PR11 100_0402_1%PR11 100_0402_1%

PR12 100K_0402_1%PR12 100K_0402_1%

B

VIN

12

PC6

10U_0805_25V6K

+3VL

BATT_TEMPA <36>

12

PC4

100P_0402_50V8J

12

PC7

0.01U_0402_25V7K

EC_SMB_CK1 <36,41>

EC_SMB_DA1 <36,41>

BATT+

C

PH1 under CPU botten side : CPU thermal protection at 93 +-3 degree C Recovery at 56 +-3 degree C

ADP_I<36,41>

PR2

0_0402_5%

PROCHOT_IN<36> VCIN0_PH<36>

1 2

B+

100K_0402_1%

POK<42,44>

PR8

VL

1 2

PR9

0_0402_5%

1 2

VSB_N_002

12

PC10

VSB_N_003

13

D

2

G

S

.1U_0402_16V7K

PR7

22K_0402_1%

1 2

PQ2

PQ2 SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

1 2

Please locate these parts Near EC chip

+3VL

PR1

1K_0402_1%

PR3

20K_0402_1%

12

PR6

PC8

100K_0402_1%

0.22U_0603_25V7K

VSB_N_001

+VSBP +VSB

PR5

0_0402_5%

0_0402_5% 1 2

13

2

PQ1

TP0610K-T1-E3_SOT23-3

PJP3

2 1

PAD-OPEN 2x2m

12

PR4

12

PH1

12

PC9

12.1K_0402_1%

100K_0402_1%_TSM0B104F4251RZ

+VSBP

0.1U_0603_25V7K

D

3 3

RTC Battery

PBJ1

-+

MAXEL_ML1220T10@

PR14

560_0603_5%

12

1 2

PR15

560_0603_5%

1 2

+RTCBATT

SP093MX0000

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Secret Data

Deciphered Date

C

Compal Electronics, Inc.

Title

2010/01/232009/01/23

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC,MB LA-8863

4019IT

D

A

of

40 51Friday, March 23, 2012

of

40 51Friday, March 23, 2012

of

40 51Friday, March 23, 2012

A

B

C

D

for reverse input protection

1

D

PQ209

2

SI1304BDL-T1-E3_SC70-3

G

1 2 3

PR226

1 2

3M_0402_5%

P1VIN

12

G

PR231@

0_0402_5%

S

3

12

PC231

0.1U_0402_25V6

12

PR234

4.12K_0603_1%

DMG4406LSS_SO8

1 2 3

PR235

4.12K_0603_1%

PQ205

4

ACIN<13,36>

8 7 6 5

+3VALW

+3VL

P2

PC238

0.1U_0603_25V7K

1 2

PR238 10K_0402_1%@ PR238 10K_0402_1%@

1 2

PR239 10K_0402_1%PR239 10K_0402_1%

1 2

PR240 10K_0402_1%PR240 10K_0402_1%

VIN

1 2

270K_0402_1%

PR211

0.01_1206_1%

1 2

PC236

0.1U_0402_25V6

12

BQ24725_ACP

BQ24725_CMSRC

BQ24725_ACDRV

BQ24725_ACOK

PR243

1UH_NRS4018T1R0NDGJ_3.2A_30%

B+ CHG_B+

PL201

4

1 2

3

BQ24725_ACN

12

PC235

0.1U_0402_25V6

PC239

PC239 1 2

1U_0603_25V6K

PU200

21

1

2

3

4

5

12

PR244

154K_0402_1%

VIN

PAD ACN

ACP

CMSRC

ACDRV

ACOK

12

PC211

@

2

3

PD230

PD230 BAS40CW_SOT323-3

BAS40CW_SOT323-3

0.047U_0402_25V7K

1 12

PC237

1 2

PR228

10_1206_1%

PR229

BQ24725_VCC

BQ24725_LX

DH_CHG

19

20

18

VCC

HIDRV

PHASE

BQ24725RGRR_VQFN20_3P5X3P5

ACDET6IOUT7SDA8SCL9ILIM

BQ24725_ACDET

10U_0805_25V6K

2.2_0603_5%

12

@

12

BQ24725_BST

17

BTST

12

PC213

PC212

10U_0805_25V6K

12

PD231

PD231 RB751V-40_SOD323-2

RB751V-40_SOD323-2

PC205

1 2

BQ24725_REGN

1U_0603_25V6K

16

REGN

15

LODRV

14

GND

13

SRP

12

SRN

11

BATDRV

10

BQ24725_ILIM

12

PR242

100K_0402_1%

12

PC214

10U_0805_25V6K

DH_CHG

FDMC7692S_MLP8-5

DL_CHG

PR236

10_0603_1%

SRP

1 2

PR237

6.8_0603_5%

SRN

1 2

BQ24725_BATDRV

PR241

1 2

150K_0402_1%

PC243

0.01U_0402_25V7K

12

@

12

PC215

0.1U_0402_25V6

PQ202

CSOP1

CSON1

0.1U_0603_16V7K

+3VALW

PC216

0.1U_0402_25V6

4

12

PC242

5

PQ201

PQ201 AON7408L

AON7408L

4.7UH_ETQP3W4R7WFN_5.5A_20%

123

BQ24725_LX

5

123

BQ24725_BATDRV

PL202

1 2

12

PR206

@

4.7_1206_5%

12

PC206

@

680P_0402_50V7K

1 2

PR233

4.12K_0603_1%

CHG

CSOP1

12

PQ207

DMG4406LSS_SO8

8 7 6 5

4

BQ24725_BATDRV_1

PR222

0.02_1206_1%

1 2

PC240

0.1U_0402_25V6

1 2 3

12

4 3

CSON1

12

@

PC241

0.1U_0402_25V6

PC234

0.01U_0402_50V7K

12

PC221

10U_0805_25V6K

PR232

0_0402_5%

@

12

PC222

10U_0805_25V6K

12

PC223

10U_0805_25V6K

BATT+

12

PC224

PC225

2200P_0402_50V7K

0.01U_0402_50V7K

PR225

1 2

1M_0402_5%

1 1

2 2

3 3

1M_0402_5%

PQ203

TPCA8057-H_PPAK56-8-5

5

12

PC230

2200P_0402_50V7K

4

BQ24725_ACDRV_1

Vin Dectector

12

Min. Typ Max. H-->L 17.23V L--> H 17.63V

ILIM and external DPM

3.97A

4 4

12

PC244

0.1U_0402_25V6

12

PR245

PC246

66.5K_0402_1%

66.5K_0402_1% 100P_0402_50V8J

100P_0402_50V8J

Please locate the RC Near EC chip 2011-02-22

PC245

PR246

1 2

100_0402_5%

12

EC_SMB_CK1 <36,40>

EC_SMB_DA1 <36,40>

ADP_I <36,40>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/01/23 2010/01/23

Compal Secret Data

Deciphered Date

C

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC,MB LA-8863

4019IT

D

of

41 51Friday, March 23, 2012

of

41 51Friday, March 23, 2012

of

41 51Friday, March 23, 2012

A

B

C

D

E

2VREF_8205

12

PC333

1U_0603_16V6K

13.7K_0402_1%

13.7K_0402_1% 1 2

20K_0402_1%

1 2

120K_0402_1%

1 2

BST_3V

UG_3V

12

PC342

PC342 1U_0603_10V6K

1U_0603_10V6K

2VREF_8205

1U_0603_16V6K

PR330

PR331

PR337

PU330

25

P PAD

7

VO2

8

VREG3

9

BOOT2

10

UGATE2

11

PHASE2

12

LGATE2

FB_3V

ENTRIP2

6

ENTRIP2

EN

13

3/5V_B+

5

14

FB2

SKIPSEL

4

TONSEL

15

30K_0402_1%

1 2

20K_0402_1%

FB_5V

1 2

120K_0402_1%

ENTRIP1

1 2

3

1

2

FB1

REF

ENTRIP1

VO1

PGOOD

BOOT1

UGATE1

PHASE1 LGATE1

NC18VREG5

VIN16GND

17

RT8205LZQW(2)_WQFN24_4X4

12

PC359

4.7U_0805_10V6K

12

PC360

0.1U_0603_25V7K

PR350

PR351

PR357

VL

3/5V_B+

12

PC353

PC354

PC358

0.1U_0402_25V6

24 23 22 21 20 19

BST_5V

UG_5V LX_5V LG_5V

PR355

2.2_0402_5%

1 2

0.1U_0402_10V7K

BST1_5VBST1_3V

PC355

1 2

POK <40,44>

10U_0805_25V6K

2200P_0402_50V7K

FDMC7692S_MLP8-5

PQ352

5

PQ351

4

AON7408L

123

5

4

123

PL352

2.2UH_ETQP3W2R2WFN_8.5A_20%

2.2UH_ETQP3W2R2WFN_8.5A_20% 1 2

12

PR356

SNUB_5V

12

PC356

4.7_1206_5%

680P_0402_50V7K

+

PC351

+5VALWP

1

220U_6.3V_M+PC351

220U_6.3V_M

2

1 1

PC338

0.1U_0402_25V6

3/5V_B+

12

PC339

+3VALWP

2200P_0402_50V7K

12

PC340

4.7U_0805_25V6-K

SSM6N7002FU_US6

PL332

4.7UH_ETQP3W4R7WFN_5.5A_20%

1

+

PC331

2

220U_D2_4VY_R15M

PQ333A

12

@

ENTRIP1

61

D

S

AON7408L

PR336

4.7_1206_5%

PC336

@

680P_0402_50V7K

N_3_5V_001

2

G

PQ331

12

SNUB_3V

12

5

123

5

123

FDMC7692S_MLP8-5

5

G

PQ332

4

ENTRIP2

34

D

S

PC341

10U_0805_6.3V6M

PC335

0.1U_0402_10V7K

0.1U_0402_10V7K 1 2

3/5V_B+

PQ333B

SSM6N7002FU_US6

LX_3V

+3VLP

12

PR334

499K_0402_1%

1 2

100K_0402_1%

PR333

1 2

2.2_0402_5%

LG_3V

PR338

12

B+

2 2

3 3

PL331

HCB2012KF-121T50_0805

1 2

PR339

100K_0402_5%

PR340

2.2K_0402_1%

EC_ON<36>

VS_ON<36>

4 4

1 2

PR341

0_0402_5%

1 2

2

12

PC343

4.7U_0805_25V6-K

A

100K_0402_5%

1 2

13

PQ334

PQ334 DRC5115E0L_SOD323-3

DRC5115E0L_SOD323-3

B

VL

+5VALWP

+3VALWP

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

PJP352

1 2

PAD-OPEN 4x4m

PAD-OPEN 4x4m PJP332

PJP332

1 2

PAD-OPEN 4x4m

C

(7A,280mils ,Via NO.= 14)

+5VALW

(5A,200mils ,Via NO.= 10)

+3VALW

Compal Secret Data

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

+3VLP

D

PJP333

2 1

PAD-OPEN 2x2m

Title

Size Document Number Rev

Custom

Date: Sheet

+3VL

Compal Electronics, Inc.

SCHEMATIC,MB LA-8863

4019IT

42 51Friday, March 23, 2012

E

A

of

5

4

3

2

1

PL151

HCB1608KF-121T30_0603

D D

B+

HCB1608KF-121T30_0603

1 2

12

PL152

PC152

330U_D2_2V_Y

PL152

1UH_VMPI0703AR-1R0M-Z01_11A_20%

+1.5VP

C C

Mode Level +0.75VSP VTTREF_1.5V S5 L off off S3 L off on S0 H on on

Note: S3 - sleep ; S5 - power off

B B

1

+

2

PC153

0.1U_0402_25V6

12

1.5V_B+

12

PC154

2200P_0402_50V7K

12

SNUB_+1.5VP

12

PC157

10U_0805_25V6K

PR156

@PR156

@

4.7_1206_5%

4.7_1206_5% FDMC7692S_MLP8-5

FDMC7692S_MLP8-5

PC156

@PC156

@ 680P_0402_50V7K

680P_0402_50V7K

12

PC158

@

4.7U_0805_25V6-K

PQ151

AON7408L

PQ152

SYSON<36,39>

123

PR155

PC160

PR155

1 2

2.2_0402_5%

SW_1.5V

DL_1.5V

20K_0402_1%

1U_0603_10V6K

12

EN_1.5V

PR152

1 2

PC159

1 2

VDD_1.5V

BOOT_1.5V

CS_1.5V

+5VALW

1.5V_B+

15

LGATE

14

PGND

13

CS

12

VDDP

11

VDD

PR158

887K_0402_1%

1 2

17

9

UGATE

TON

19

18

BOOT

VLDOIN

S5

S3

8

7

EN_0.75VSP

16

PHASE

RT8207MZQW_WQFN20_3X3

PGOOD

10

TON_1.5V

20

PU150

VTT

PAD

VTTGND

VTTSNS

GND

VTTREF

VDDQ

FB

6

FB_1.5V

21 1

2

3

4

5

VTTREF_1.5V

PR160

PR160 10K_0402_1%

10K_0402_1%

1 2

+1.5V

PR154

10.2K_0402_1%

+1.5VP

12

BST_1.5V

DH_1.5V

PC155

5

1 2

0.22U_0402_10V6K

4

PR157

5.1_0603_5%

4

1 2

+5VALW

1U_0603_10V6K

PR159

0_0402_5%

1 2

12

PC163

@PC163

@

0.1U_0402_10V7K

0.75Volt +/- 5% TDC 0.7A Peak Current 1A

12

PC260

10U_0805_6.3V6K

PC261

+1.5VP

PC162

PC162 .1U_0402_16V7K

.1U_0402_16V7K

12

@

10U_0805_6.3V6K

12

+0.75VSP

PC262

10U_0805_6.3V6K

PC161

0.033U_0402_16V7K

PR162

0_0402_5%

PJP152

1 2

PAD-OPEN 4x4m

PJP153

+1.5VP

+0.75VSP

A A

1 2

PAD-OPEN 4x4m

PJP76

1 2

PAD-OPEN 3x3m

5

(12A,480mils ,Via NO.= 24)

+1.5V

(1A,40mils ,Via NO.= 3)

+0.75VS

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/07/20

3

SUSP#<36,39,44>

Compal Secret Data

0_0402_5%

Deciphered Date

12

PC164

@PC164

@

0.1U_0402_10V7K

Compal Electronics, Inc.

2012/12/31

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC,MB LA-8863

Friday, March 23, 2012

4019IT

1

43 51

of

ACustom

5

4

3

2

1

1.1valwp

PC116

SNUB_+1.1VALWP

D D

1 2

680P_0402_50V7K

Peak Current 4A current limited 6A

PU110

SY8036LDBC_DFN10_3x3

PR106

+1.1VALW+1.1VALWP

SY8036LDBC_DFN10_3x3

(4A,240mils ,Via NO.= 8)

PL111

HCB1608KF-121T30_0603

+5VALW

C C

1 2

12

PC106@

PC107@

68P_0402_50V8J

100P_0402_25V8K

1.1VALWP_B+

0_0402_5%

12

PC108@

PC109

220P_0402_25V8K

2200P_0402_50V7K

12

PC110

FCH_PWR_EN<36,39>

PC111

22U_0805_6.3V6K

POK<40,42>

PJP112

1 2

PAD-OPEN 4x4m

0_0402_5%

1 2

PR107

@

0_0402_5%

1 2

10

9 8

EN_1.1VALWP

5

12

PC119

@PC119

@

0.1U_0402_10V7K

PU110

PVIN PVIN SVIN

EN

4

LX

PG

LX

FB

TP

SS

7

1

11

PR116

4.7_1206_5%

4.7_1206_5% 2 3

6

LX

1 2

PL112

0.47UH_FDVE0630-H-R47M=P3_17.7A_20%

0.47UH_FDVE0630-H-R47M=P3_17.7A_20% 1 2

PR108

1 2

10K_0402_1%

PR109

1 2

12K_0402_1%

+1.1VALWP

12

PC104

12

22P_0402_50V8J

12

PC113

PC114

PC112

22U_0805_6.3V6K

PC114

PC115

22U_0805_6.3V6K

PC115

22U_0805_6.3V6K

12

PC117@

PC118@

68P_0402_50V8J

22U_0805_6.3V6K

220P_0402_25V8K

PU180

SY8033BDBC_DFN10_3X3

PL182

PL181

HCB1608KF-121T30_0603

B B

+5VALW

SUSP#<36,39,43>

PXS_PWREN<14,25,26,49>

A A

1 2

PR183

@PR183

@ 0_0402_5%

0_0402_5%

1 2

PR718

47K_0402_1%

5

4

12

PC184

PC184 22U_0805_6.3V6M

22U_0805_6.3V6M

EN_1.8VSP

47K_0402_5%

VIN_1.8VSP

PR184

@PR184

@

12

PC187

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

10

PVIN

PG

9

PVIN

8

SVIN

5

EN

TP

NC

7

11

0.1U_0402_10V7K

LX_1.8VSP

2

LX

3

LX

FB_1.8VSP

6

FB

NC

1

+1.8VGSP

2011/07/29

3

1UH_NRS4018T1R0NDGJ_3.2A_30%

1 2

Compal Secret Data

1 2

12

PR186

4.7_1206_5%

SNUB_1.8VSP

12

PC186

680P_0603_50V7K

PJP182

PAD-OPEN 4x4m

Deciphered Date

PL182

PR181

20K_0402_1%

FB_1.8VSP

PR182

10K_0402_1%

12

PC188

68P_0402_50V8J

12

(3A,120mils ,Via NO.= 6)

+1.8VGS

2

+1.8VGSP

12

PC183

PC182

22U_0805_6.3V6M

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC,MB LA-8863

4019IT

1

of

44 51Friday, March 23, 2012

of

44 51Friday, March 23, 2012

of

44 51Friday, March 23, 2012

A

B

C

D

1 1

PL1001

+5VALW

2 2

PL1001

HCB1608KF-121T30_0603

1 2

PX_MODE<14,49>

12

PC1001

PC1001 22U_0805_6.3V6M

22U_0805_6.3V6M

PR1002

1 2

0_0402_5%

@

12

PR1005

EN_VDDCIP

12

PC1004

@

47K_0402_5%

PU1000

10

PVIN

9

PVIN

8

SVIN

5

EN

0.1U_0402_10V7K

4

LX

PG

LX

FB

TP

NC

7

1

11

LX_VDDCIP

2 3

FB_VDDCIP

6

NC

SY8033BDBC_DFN10_3X3

PL1000

1UH_NRS4018T1R0NDGJ_3.2A_30%

12

PR1001

FB=0.6Volt

12

PC1002

1 2

PC1000

4.7_0805_5%

680P_0603_50V7K

PR1000

10K_0402_1%

12

22P_0402_50V8J

12

1 2

T@

PR1003

4.99K_0402_1%

PR1006

PR1006 10_0402_5%

10_0402_5%

1 2

12

T@

PR1007

29.4K_0402_1%

13

D

2

G

S

PQ1000

PQ1000 2N7002W-T/R7_SOT323-3

2N7002W-T/R7_SOT323-3

PR1004

0_0402_5%

12

@ PC1006

@ 4700P_0402_25V7K

4700P_0402_25V7K

12

PC1003

22U_0805_6.3V6M

PR1009

PR1009 10K_0402_5%

10K_0402_5%

PC1006

12

PC1005

22U_0805_6.3V6M

+3VGS

12

PR1008

PR1008 10K_0402_5%

10K_0402_5%

12

PR1010 100K_0402_5%

100K_0402_5%

@PR1010

@

+VDDCI TDC 2.2A

OCP current 3A

+VDDCIP

VDDCI_SEN <15>

VDDCI_VID <13>

VDDCI_VID

PR1003

PR1003 C@

C@

PR1007

PR1007 C@

C@

5.23K_0402_1%

86.6K_0402_1%

High

Low

1V

PR1003 4.99K SD034499180 PR1007 29.4K SD034294280

0.9V

PR1003 4.99K SD034499180

Thames

0.95V

PR1003 5.23K SD034523180 PR1007 86.6K SD034866280

0.91V

PR1003 5.23K SD034523180

Chelsea

3 3

+VDDCIP

PJP102

@PJP102

@

1 2

JUMP_43X118

+VDDCI

(2.2A,100mils ,Via NO.= 5)

PJP103

@ PJP103

@

2

+VDDCI

4 4

112

JUMP_43X39

+1.0VGS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/08/16 2012/08/15

Compal Secret Data

Deciphered Date

C

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC,MB LA-8863

SCHEMATIC,MB LA-8863 4019IT

4019IT

D

45 51Friday, March 23, 2012

of

A

5

4

3

+1.2VSP_B+

2

PL121

HCB1608KF-121T30_0603

12

1

B+

5

PQ121

123

5

123

PQ121

AON7408L_DFN8-5

PQ122

FDMC7692S_MLP8-5

D D

PR125

2.2_0603_5%

PU120

PR127

0.1U_0402_16V7K

PR132

PR132 10K_0402_1%

10K_0402_1%

1 2

TRIP_+1.2VSP EN_+1.2VSP

FB_+1.2VSP RF_+1.2VSP

12

PR129

470K_0402_1%

1 2

105K_0402_1%

1 2

105K_0402_1%

12

PC127 @PC127

@

PR120

VR_ON<36,39,47>

C C

PR120

0_0402_5%

1 2

PR121

47K_0402_1%

@

1 2 3 4 5

PR131

7.15K_0402_1%

VBST

PGOOD TRIP

DRVH

EN

SW

V5IN

VFB

DRVL

TST

TPS51212DSCR_SON10_3X3

@

PC129

12

1000P_0402_50V7K

12

BST_+1.2VSP

10

UG_+1.2VSP

9

SW_+1.2VSP

8

+1.2VSP_5V

7

LG_+1.2VSP

6 11

TP

@

PR130

12

1.2K_0402_1%

2.2_0603_5%

1 2

0.1U_0603_25V7K

12

PC128

PC128 1U_0603_6.3V6M

1U_0603_6.3V6M

PC125

+5VALW

4

PC120

2.2UH_ETQP3W2R2WFN_8.5A_20%

1 2

12

PR126

4.7_1206_5%

12

PC126

1000P_0603_50V7K

12

PC121

0.1U_0402_25V6

PL122

12

2200P_0402_50V7K

PC124

PC123

10U_0805_25V6K

12

68P_0402_50V8J

1

+

PC122

2

330U_D2_2.5VY_R15M

+1.2VSP

Ipeak=8.5A Imax=5.95A F=290K

PJP122

+1.2VSP

(8.5A,340mils ,Via NO.=17)

PJP122

2

JUMP_43X118@

+1.2VSP Iocp=13A

112

+1.2VS

B B

PU25

APL5508-25DC-TRL_SOT89-3

+3VS

PC250

1U_0603_10V6K

A A

5

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

APL5508-25DC-TRL_SOT89-3

2

12

2011/07/29

3

IN

GND

1

3

OUT

12

PC251

4.7U_0805_6.3V6K

Compal Secret Data

Deciphered Date

12

PR250

@PR250

@ 10K_1206_5%

10K_1206_5%

+2.5VSP

2

PJP252

2

112

JUMP_43X39@

(0.75A,40mils ,Via NO.=22)

Title

Size Document Number Rev

Date: Sheet

JUMP_43X39@

Compal Electronics, Inc.

SCHEMATIC,MB LA-8863

4019IT

+2.5VS+2.5VSP

of

46 51Friday, March 23, 2012

of

46 51Friday, March 23, 2012

of

46 51Friday, March 23, 2012

1

A

5

PC501

330P_0402_50V7K

PR531

0_0402_5%

@

PC531

1000P_0402_50V7K

PR535

634_0402_1%

@

220P_0402_50V7K

12

330P_0402_50V7K

1000P_0402_50V7K

12

PC541

12

APU_VDDNB_SEN<7>

PR500

10_0402_5%

PR534

11K_0402_1%

10_0402_5%

12

1 2

PC538

PC539

0.1U_0402_25V6

0.047U_0402_16V7-K

0.047U_0402_16V7-K PR537

@PR537

@ 100_0402_1%

100_0402_1%

D D

VSUMP_NB

+APU_CORE_NB

12

PR533

12

2.61K_0402_1%

PH2

1 2

10K_0402_5%_ERTJ0ER103J

12

PC540

0.1U_0603_50V7K

PC528

12

2.8K_0402_1%

12

2K_0402_1%

PR528

PR527

12

PR532

301_0402_1%

12

PR539

10K_0402_1%

PR529

137K_0402_1%

100P_0402_50V8J

12

After rev1.1 must change to 133k

48

PU500

12

12 12 12

12

PC551

PR568

1 2

SVC

SVD

SVT ENABLE PWROK

12

PC552

0.22U_0402_10V6K

1 2

11K_0402_1%

PU500

1

ISEN2_NB

2

NTC_NB

3

IMON_NB

4

SVC

5

VR_HOT_L

6

SVD

7

VDDIO

8

SVT

9

ENABLE

10

PWROK

11

IMON

12

NTC

ISEN3 ISEN2 ISEN1

0.22U_0402_10V6K

1 2

PC556

0.022U_0402_16V7K

@

PR573

100_0402_1%

ISEN1_NB

ISEN3

13

@

PR563

10K_0402_1%

PC560

PR572

0.22U_0402_10V6K

0.22U_0402_10V6K 604_0402_1%

604_0402_1%

820P_0402_50V7K

12

@

PR541

127K_0402_1%

PR543 27.4K_0402_1%PR543 27.4K_0402_1%

12

PH3

470K_0402_5%_TSM0B474J4702RE

C C

After rev1.1 must change to 133k

B B

12

PR547

10.5K_0402_1%

PR554

118K_0402_1%

1 2

PC550

1000P_0402_25V6K

1 2

PR555 27.4K_0402_1%PR555 27.4K_0402_1%

PH4

470K_0402_5%_TSM0B474J4702RE

12

PR562

10.5K_0402_1%

H_PROCHOT#<7,36>

12

PC542

1000P_0402_25V6K

1 2

+1.5VP

PC568 1U_0603_16V6KPC568 1U_0603_16V6K

APU_SVC<7>

APU_SVD<7>

PR549 0_0402_5%PR549 0_0402_5%

12

APU_SVT<7>

VR_ON<36,39,46>

APU_PWRGD<7,25>

+5VS

0_0402_5%

@

@ 10_0402_5%

10_0402_5%

VSUM-

VSUM+

10K_0402_5%_ERTJ0ER103J

VSUM-

12

PR557

PR560

+5VS

VDDIO

PH5

PR542

10_0402_5%

0_0402_5%

PR545

0_0402_5%

PR546

PR546 PR548 0_0402_5%PR548 0_0402_5%

PR550 0_0402_5%PR550 0_0402_5% PR552 0_0402_5%PR552 0_0402_5% PR553 0_0402_5%PR553 0_0402_5%

12 12

12

PR565

12

2.61K_0402_1%

12

PC565

0.1U_0603_50V7K

PC527

390P_0402_50V7K

12

PC529

12

44

46

45

47

FB_NB

VSEN_NB

ISUMP_NB

ISUMN_NB

ISL6277HRTZ-T_TQFN48_6X6

ISUMP16ISEN2

15

14

12

PC566

12

4

43

COMP_NB

VSEN

18

1 2

PR530

@ PR530

@

32.4K_0402_1%

32.4K_0402_1% 12

40

42

41

FCCM_NB

PWM2_NB

PGOOD_NB

RTN19ISUMN17ISEN1

FB21PGOOD

FB2

20

1000P_0402_50V7K

PC557

330P_0402_50V7K

1 2

PC567

0.01U_0402_25V7K

39

38

LGATEX

COMP

22

23

PC554

PR577

0_0402_5%

PR580

0_0402_5%

FCCM_NBVSUMN_NB

37

PHASEX

UGATEX

BOOT1

24

BOOT1

301_0402_1%

12

PR569

2.26K_0402_1%

12

LGATE_NB1 PHASE_NB1 UGATE_NB1

BOOTX

VIN

BOOT2 UGATE2 PHASE2 LGATE2

VDDP

VDD

PWM_Y LGATE1 PHASE1 UGATE1

TP

49

PR566

12

10_0402_5%

12

PR575

PR581

36 35 34 33 32 31 30 29 28 27 26 25

12

PR536

@

0_0603_5%

BOOT_NB1

BOOT2 UGATE2 PHASE2 LGATE2

PR582 0_0402_5%PR582 0_0402_5%

PR583

0_0402_5%

LGATE1 PHASE1 UGATE1

PR558

100K_0402_5%

PC553

10P_0402_25V8K

PC555

100P_0402_50V8J

PR570

137K_0402_1%

12

PR571

2K_0402_1%

12

+APU_CORE

12

CPU_B+

PR544

12

0_0603_5%

12

PC543

0.22U_0603_25V7K

+5VALW

12

PR551

12

1_0603_5%

12

PC548

1U_0603_16V6K

+3VS

12

VGATE <36>

12

@

PR567

32.4K_0402_1%

12

PC561

390P_0402_50V7K

12

PC564

680P_0402_50V7K

12

APU_VDD_SEN <7>

APU_VDD_RUN_FB_L <7>

PC549

1U_0603_16V6K

12

3

UGATE_NB1

PHASE_NB1

BOOT_NB1

UGATE1 UGATE1-1

UGATE2

PR505

0_0603_5%

LGATE_NB1

PHASE1

BOOT1

LGATE1

0_0603_5%

PHASE2

BOOT2

PR509

PC505

0.22U_0603_25V7K

0.22U_0603_25V7K 12

12

PR508

12

0_0603_5%

PR515

12

0_0603_5%

TPCA8059-H_PPAK56-8-5

UGATE2-1

12

0.22U_0603_25V7K

PR525

12

0_0603_5%

LGATE2

TPCA8059-H_PPAK56-8-5

5

4

5

4

PC515

0.22U_0603_25V7K

0.22U_0603_25V7K 12

4

PQ506

4

PC525

12

4

PQ508

PC532

PQ501

123

TPCA8065-H_SOP-ADV8-5

PQ502

PQ502 TPCA8057-H_PPAK56-8-5

TPCA8057-H_PPAK56-8-5

123

5

PQ503

123

TPCA8065-H_SOP-ADV8-5

5

123

5

PQ505

123

TPCA8065-H_SOP-ADV8-5

12

5

12

123

12

PC570

10U_0805_25V6K

@

560P_0402_50V7K

12

PR516

4.7_1206_5%

PC516

12

680P_0603_50V7K

ISEN2

PR526

4.7_1206_5%

4.7_1206_5% VSUM+

PC526

680P_0603_50V7K

VSUM-

2

CPU_B+

12

PC533

10U_0805_25V6K

12

PR506

4.7_1206_5%

12

PC506

680P_0603_50V7K

PC544

ISEN1

VSUM+

VSUM-

PR574

10K_0402_1%

PR578

3.65K_0402_1%

PR579

1_0402_1%

12

PC534

0.1U_0402_25V6

VSUMP_NB

VSUMN_NB

12

10U_0805_25V6K

PR556

10K_0402_1%

PR561

3.65K_0402_1%

PR564

1_0402_1%

12

PC558

10U_0805_25V6K

12

+

PC535

PC537

CPU_B+

PC547

10U_0805_25V6K

PC559

0.36UH_FDUE1030D-H-R36M=P3_32A_20%

PC535

PC530

100U_25V_M

2

100U_25V_M

2

2200P_0402_50V7K

0.36UH_MMD10DZR36MS1_24A_20%

PR538

3.65K_0402_1%

3.65K_0402_1% 12

PR540

1_0402_1%

12

CPU_B+

10U_0805_25V6K

12

PC546

PC545

0.01U_0402_25V7K

2200P_0402_50V7K

PL504

0.36UH_FDUE1030D-H-R36M=P3_32A_20%

1

12

2

12

PC562

PC563

0.01U_0402_25V7K

2200P_0402_50V7K

PL505

1 2

1

12

+

PC569

1 2

12

4 3

HCB2012KF-121T50_0805

1

12

+

100U_25V_M

2

68P_0402_50V8J

PL503

4 3

1 2

PR559

PR559 10K_0402_1%

10K_0402_1%

1 2

PR576

PR576 10K_0402_1%

10K_0402_1%

1

PL501

1 2

PL502

1 2

PC536

4 3

APU_CORE_NB TDC 25A Peak Current 33A OCP current 40A Load line -4mV/A FSW=300kHz DCR 1.1mohm +/-5% TYP MAX H/S Rds(on) :11.7mohm , 14.5mohm L/S Rds(on) :2.6mohm , 3.2mohm

ISEN2

APU_core TDC 36A Peak Current 50A OCP current 60A Load line -2.1mV/A FSW=300kHz DCR 1.1mohm +/-5% TYP MAX H/S Rds(on) :11.7mohm , 14.5mohm L/S Rds(on) :2.6mohm , 3.2mohm

ISEN1

B+

+APU_CORE_NB

+APU_CORE

A A

5

4

3

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/04/18 2015/07/08

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Custom Date: Sheet

Date: Sheet

SCHEMATIC,MB LA-8863

4019IT

1

of

47 51Friday, March 23, 2012

A

5

4

3

2

1

+APU_CORE

PC801

D D

PC801

12

22U_0805_6.3V6M

12

PC802

22U_0805_6.3V6M

12

PC803

22U_0805_6.3V6M

12

PC804

22U_0805_6.3V6M

12

PC805

22U_0805_6.3V6M

+APU_CORE_NB

12

PC808

22U_0805_6.3V6M

12

PC817

0.01U_0402_50V7K

12

PC806

22U_0805_6.3V6M

C C

12

PC813

0.22U_0402_16V7K

PC814

0.22U_0402_16V7K

12

PC807

22U_0805_6.3V6M

12

PC815

0.01U_0402_50V7K

PC816

0.01U_0402_50V7K

12

PC809

22U_0805_6.3V6M

12

PC811

@

22U_0805_6.3VAM

12

PC818

180P_0402_50V8J

@

12

PC819

180P_0402_50V8J

12

PC810

22U_0805_6.3V6M

12

PC812

22U_0805_6.3V6M

12

PC820

180P_0402_50V8J

12

PC827

22U_0805_6.3V6M

capacitors under processor on bottom side of board

12

PC832

0.22U_0402_16V7K

+VGA_CORE

+APU_CORE_NB

12

PC830

PC829

PC828

22U_0805_6.3V6M

12

PC834

PC833

0.22U_0402_16V7K

PC835

180P_0402_50V8J

12

PC831

@

10U_0805_6.3V6K

22U_0805_6.3V6M

12

PC836

180P_0402_50V8J

+APU_CORE_NB

1

+

PC825

12

2

330U_D2_2V_Y

1

+

2

Local

PC826

330U_D2_2V_Y

+VGA_CORE

+APU_CORE

Local

PC932

1

+

PC821

2

330U_D2_2V_Y

B B

A A

1

+

PC822

2

330U_D2_2V_Y

1

+

PC823

2

330U_D2_2V_Y

1

+

PC824

2

330U_D2_2V_Y

PC932

10U_0603_6.3V6M

PC965

1U_0402_6.3V6K

PC944

1U_0402_6.3V6K

PC970

1U_0402_6.3V6K

12

PC931

10U_0603_6.3V6M

12

PC966

1U_0402_6.3V6K

12

PC945

1U_0402_6.3V6K

12

PC955

1U_0402_6.3V6K

5

4

+VDDC +VDDCI

12

PC925

10U_0603_6.3V6M

12

PC938

1U_0402_6.3V6K

12

PC948

1U_0402_6.3V6K

12

PC958

1U_0402_6.3V6K

3

12

PC926

10U_0603_6.3V6M

12

PC969

1U_0402_6.3V6K

12

PC949

1U_0402_6.3V6K

12

PC959

1U_0402_6.3V6K

2011/07/29

PC928

10U_0603_6.3V6M

PC940

1U_0402_6.3V6K

PC950

1U_0402_6.3V6K

PC960

1U_0402_6.3V6K

12

PC923

PC924

10U_0603_6.3V6M

12

PC937

PC964

1U_0402_6.3V6K

12

PC947

PC946

1U_0402_6.3V6K

12

PC957

PC971

1U_0402_6.3V6K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

12

PC927

10U_0603_6.3V6M

12

PC941

1U_0402_6.3V6K

12

PC951

1U_0402_6.3V6K

12

PC961

1U_0402_6.3V6K

Compal Secret Data

PC929

PC933

10U_0603_6.3V6M

12

PC942

PC943

1U_0402_6.3V6K

12

PC953

PC952

1U_0402_6.3V6K

12

PC962

PC963

1U_0402_6.3V6K

Deciphered Date

12

10U_0603_6.3V6M

12

1U_0402_6.3V6K

12

1U_0402_6.3V6K

12

1U_0402_6.3V6K

12

PC934

1U_0402_6.3V6K

12

PC921

10U_0603_6.3V6M

PC939

PC922

2

12

PC935

1U_0402_6.3V6K

12

PC930

10U_0603_6.3V6M

12

1U_0402_6.3V6K

12

10U_0603_6.3V6M

+VDDCI

12

PC936

1U_0402_6.3V6K

4019IT

PC967

1U_0402_6.3V6K

1

12

PC968

PC954

1U_0402_6.3V6K

Title

Size Document Number Rev

A3

Date: Sheet

PC956

1U_0402_6.3V6K

Compal Electronics, Inc.

SCHEMATIC,MB LA-8863

12

PC972

1U_0402_6.3V6K

48 51Friday, March 23, 2012

PC973

1U_0402_6.3V6K

of

12

A

B

C

D

E

F

G

H

@

1 2

1 2 1 2 1 2

GPU_VID1

GPU_VID2 GPU_VID3 GPU_VID4

1 1

PR72410K_0402_1%PR72410K_0402_1%

PR72610K_0402_1%PR72610K_0402_1% PR72810K_0402_1%PR72810K_0402_1%

@

PR73010K_0402_1%@PR73010K_0402_1%

@

PR725 10K_0402_1%

12

@

PR727 10K_0402_1%

12

@

PR729 10K_0402_1%

12

PR731 10K_0402_1%PR731 10K_0402_1%

12

+3VGS

<13>

<14,45>

PX_MODE

GPU_VID1

GPU_VID2

<13>

+3VGS

GPU_VID4

GPU_VID3

+5VS

PR732

@

80.6K_0402_1%

+3VS

12

PR742

PR742 1K_0402_1%

1K_0402_1%

PC748

1000P_0402_50V7K

PR744

2 2

VSSSENSE_VGA<15>

VCCSENSE_VGA<15>

PR744

0_0402_5%

PR746

0_0402_5%

12

PR743

40.2K_0402_1%

1 2

PC749

220P_0402_50V7K

1 2

PR747

1K_0402_1%

VGA_PWRGD<25,26>

VGA_COMP-1

1 2

PC756

470P_0402_50V8J

PC751

47P_0402_50V8J

1 2

PR748

20K_0402_1%

3.92K_0402_1%

PR707

12

VGA_FB VGA_COMP

1 2

VGA_CSCOMP

Connect to input caps

3 3

1U_0603_6.3V6M

1 2

PR720 1K_0402_1%

1K_0402_1%

+5VALW+1.1VALW

12

PC708

PU701

6

VCNTL

5

VIN

VOUT

9

VIN

VOUT

8

EN

7

POK

GND

1

APL5916KAI-TRL_SO8

12

PL101

PC706

PC736

@ PC736

@

PL101

12

+3VS

@ PR720

@

12

HCB1608KF-121T30_0603

22U_0805_6.3V6M

PR719

0_0402_5%

PXS_PWREN<14,25,26,44>

4 4

1 2

0.01U_0402_25V7K

+VGA_B+

3 4

2

FB

PR721

12K_0402_1%

T@

PR722

47.5K_0402_1%

12

@

1 2

VGA_VCC VGA_ILIM

PC739

1 2

0.1U_0402_16V7K

PU700

1 2 3 4 5 6 7 8

PR749

80.6K_0402_1%

PR755

1K_0402_1%

12

PR733

PR734 0_0402_5%PR734 0_0402_5%

0_0402_5%

1 2

VID1

VGA_EN

32

EN

VID031VID130VID229VID328VID427VID526VID6 PWRGD IMON CLKEN# FBRTN

ADP3211AMNR2G_QFN32_5X5

FB COMP GPU ILIM

IREF9RPM10RT11RAMP12LLINE13CSREF14CSFB15CSCOMP

VGA_RPM

PR750

1 2

237K_0402_1%

VGA_RAMP-1

12

PC759

12

PC738

39P_0402_50V8J

VGA_RT

PR751

301K_0402_1%

PC731

VGA_IREF

1 2

1000P_0402_50V7K

PR736 0_0402_5%PR736 0_0402_5%

PR737 0_0402_5%PR737 0_0402_5%

PR738 0_0402_5%PR738 0_0402_5%

PR735 0_0402_5%PR735 0_0402_5%

1 2

22U_0805_6.3V6M

1 2

VID2

VID3

VID4

VGA_CSFB

VGA_RAMP

12

PR752 422K_0402_1%PR752 422K_0402_1%

12

1000P_0402_50V7K

12

PR757

0_0402_5%

VGA_CSCOMP

+1.0VGSP

12

+VGA_PCIE

PC732

TDC 3.6A

22U_0805_6.3V6M

Peak Current 5.2A

PR739 0_0402_5%PR739 0_0402_5%

PR740 0_0402_5%PR740 0_0402_5%

1 2

25

VCC BST

DRVH

SW

PVCC

DRVL PGND AGND AGND

16

VGA_CSCOMP

PC760

1 2

@

PR756

0_0402_5%

PR741

PR741 10_0603_1%

10_0603_1%

1 2

VGA_VCC

24

VGA_BOOST

23

VGA_DRVH

22

VGA_SW

21 20

VGA_DRVL

19 18 17 33

12

PC757

1000P_0402_50V7K

12

PC747

PC747 1U_0603_10V6K

1U_0603_10V6K

2.2_0603_5%

2.2_0603_5% 1 2

12

PC758

PC758 1200P_0402_50V7K

1200P_0402_50V7K

PR705

PR723

0_0603_5%

PR745

0_0603_5%

0.22U_0603_25V7K

VGA_BOOST-1

VGA_DRVH1

12

2.2U_0603_10V6K

PC705

1 2

+5VS

PC750

12

PR753

PR753 220K_0402_1%

220K_0402_1%

12

4

PR754

107K_0603_1%

5

PQ701

123

5

123

12

5

4

S TR AON7518 1N DFN

5

PQ702

4

123

TPCA8059-H_PPAK56-8-5

123

PQ704

PQ703

12

TPCA8059-H_PPAK56-8-5

+VGA_B+

12

PC740

PC741

10U_0805_25V6K

S TR AON7518 1N DFN

0.36UH_FDUE1040J-H-R36M-P3_33A_20%

0.36UH_FDUE1040J-H-R36M-P3_33A_20% 3

4

PR706

4.7_1206_5%

PC716

680P_0603_50V8J

PC742

10U_0805_25V6K

PL703

PL701

HCB2012KF-121T50_0805

1 2

PL702

HCB2012KF-121T50_0805

12

2 1

12

1

+

PC796

2

330U_D2_2V_Y

VID4

1 2

12

PC746

PC745

0.1U_0402_25V6

0.1U_0402_25V6 2200P_0402_25V7K

2200P_0402_25V7K

1

+

PC798

PC797

2

Thames XT

00

01

1

330U_D2_2V_Y

VID3

330U_D2_2V_Y

VID1

0

1

0

1

2

+

PC799

330U_D2_2V_Y

1.0V

0.9V

0.875V

B+

+VGA_CORE

Ipeak=59A Imax=45.7A F=300kHZ Total capacitor 1320u ESR=2.25m ohm

X

+1.0VGSP

PR722 63.4K_0402_1%

PR722 63.4K_0402_1% C@

C@

PJP702

@PJP702

@

1 2

JUMP_43X118

A

+1.0VGS

B

Thames XT

PR722 47.5K

SD034475280

C

1.0VVGA_PCIE

Chelsea Pro

0.95V

63.4K SD03463K280

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

E

2009/10/02 2010/10/02

Compal Secret Data

Deciphered Date

F

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

G

Compal Electronics, Inc.

SCHEMATIC,MB LA-8863

4019IT

49 51Friday, March 23, 2012

H

of

A

5

4

3

2

1

HW PIR (Product Improve Record)

QMLE4 LA-8863P SCHEMATIC CHANGE LIST REVISION CHANGE: 0.1 TO 0.2 GERBER-OUT DATE: 2012/02/10 Item Date Page Solution Request

--------------------------------------------------------------------------------------------------------------------------

1. 1/10 P32 Add PJ31 For saving power consumption

D D

2. 1/12 P38 Change JTP symbol to SP01001BF10 For ME request

3. 1/30 P35 Add internal MIC to MB For customer request

4. 2/2 P14 Remove PX4.0 circuit Support PX5.0

5. 2/2 P31 Add PJ26,PJ33, WLAN power circuit and reset pin For customer request

6. 2/2 P33 Update JCRIO pin definition Change int. MIC to MB

7. 2/2 P35 Remove CA64, add RA32 and RA33 Move sense resistors to MB

8. 2/3 P31 Change JWLAN symbol to SP07000TB00 For ME request

9. 2/3 P31 Add WLAN_PWR# and WLAN_RST# For customer request

10. 2/7 P32 Change UL3 and UL4 PN to SP050005V00 For shortage

--------------------------------------------------------------------------------------------------------------------------

REVISION CHANGE: 0.2 TO 0.3 GERBER-OUT DATE: 2012/03/12 Item Date Page Solution

--------------------------------------------------------------------------------------------------------------------------

1. 3/1 P12 Update RTC scematic For avoiding +3VL short to GND

2. 2/29 P22 Change R108 pull-high from +3VS to +3VALW For LVDS sequence issue

C C

3. 3/7 P26 Add R292 and reserve R293 To avoid PXS_PWREN floating

4. 3/7 P7 Unstuff R121~R124,R118,R119 For debug use

5. 3/7 P27 Update U13 footprint

6. 3/7 P27/30 Connect SATA port2 to 15"ODD connector, and add GPIO54 To solve SATA EA fail issue

7. 3/8 Change RB20,RB34,R3,RV102,R425,R136,R31,R32,R33,RV284,RV287 R62,RV277 to short pad

8. 3/12 P24 Add C201 and C214 For EMI request

9. 3/12 P30 Add C364 and C365 For EMI request

10. 3/12 P35 Add CA5, CA6, CA64, CA67, CA68 and CA77 For EMI request

11. 3/14 P8 Add C147 co-layout with C100 To avoid damage by SMT process

12. 3/14 P10 Add C148 co-layout with C218 To avoid damage by SMT process

--------------------------------------------------------------------------------------------------------------------------

B B

A A

5

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/11/28 2013/12/31

3

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC,MB LA-8863

4019IT

50 51Friday, March 23, 2012

1

of

A

5

4

3

2

1

NO DATE PAGE MODIFICATION LIST PURPOSE

----------------------------------------------------------------------------------------------------------------------------------------

1. 2012/02/14 P40-PWR-DCIN/BATT CONN/OTP Delete PR12,PR13 Circuit modify

2. 2012/02/14 P41-PWR-CHARGER Change PR211 to 0.01_1206_1%,PL201 to1UH 4*4*2 Circuit modify Add PC207,PC208,PC217,PC218,Delete PC232,PC233

3. 2012/02/14 P43-PWR-1.5VP/+0.75VSP Change PL152 to SH00000KS00 Circuit modify

4. 2012/02/14 P44-PWR-+1.1VALWP/+1.8VSP Change PR718 to 47K,add PC187 HW request

5. 2012/02/14 P46-+1.2VSP/+2.5VSP Change PL122 to 2.2uH(SH00000MR00), Circuit modify PR127 to SD034105380

D D

6. 2012/02/14 P37-PWR +CPU_CORE Change PQ502 to TPCA8057 Circuit modify

7. 2012/03/06 P40-PWR-DCIN/BATT CONN/OTP Add PR12(100KΩ) Circuit modify

C C

B B

A A

5

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/09/15 2012/12/31

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC,MB LA-8863

4019IT

51 51Friday, March 23, 2012

1

of

A

COMPAL LS-8863P Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual