COMPAL LS-5588P Schematics

A

1 1

B

C

D

E

Compal confidential

Schematics Document

2 2

Mobile Penryn uFCPGA with Intel Cantiga_GM+ICH9-M SFF core logic

3 3

ULV core logic HDI board DISCRETE VGA M92

4 4

Security Classification Compal Secret Data

A

Security Classification Compal Secret Data

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2009/04/20 2010/04/30

2009-06-19 V.03

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

Cover Sheet

LS-5588

E

1 35Wednesday, July 01, 2009

0.3

A

Compal confidential

Model Name : NAW20 File Name : LS-5588P

B

ULV

C

D

E

ZZZ

1 1

Thermal Sensor

Mobile Peryn

LV/ULV Dual Core

uFCPGA-956 CPU - SFF

page 4

DISCRETE VGA HDI BRD

page 17,18,19,20,21

ATI M92 S2

Intel Cantiga GS

600MHz

VRAM DDR3 512MB(64Mx16)

2 2

page 4,5,6,7

H_A#(3..35) H_D#(0..63)

FSB

667/800/1066MHz 1.05V

FCBGA 1363 - SFF

page 8,9,10,11,12,13

DDR3 1066MHz 1.5V

Dual Channel

CK505

Clock Generator ICS9LPRS387BKLFT MLF 72P

page 16

DDR3-SO-DIMM X 2

BANK 0, 1, 2, 3

page 14,15

PCB-MB

DMI X4

RGB

Single Channel

3 3

SATA x3 USB x9 PCIE*3 LPC

Intel ICH9-M

WBMMAP-569 - SFF

page 22,23,24,25

HDA

HDMI

CRT

Golden finger

LPC

PCIE

HDI to I/O board

miniPCIE*1

page 26

EC

HDA

AUDIO

USB

LVDS

SATA

ODD

4 4

HDD

USB*2

CardReader

BT

ESATA

A

B

CMOS

miniPCIE *2

LAN

I/O BRD PORTION

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2009/04/20 2010/04/30

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

Block Diagram

LS-5588

E

2 35Wednesday, July 01, 2009

0.3

A

Voltage Rails

State

S0

S1

S3

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery don't exist

1 1

( O MEANS ON X MEANS OFF )

+B

+3VL

power plane

O O O O O

X

+5VALW +3VALW

+1.5V

O O O O

X

O

X X X

+5VS +3VS +1.5VS +0.75VS +VCCP +CPU_CORE +VGA_CORE +1.1VS +1.8VS

OO OO

X

SMBUS Control Table

SOURCE

SMB_EC_CK1 SMB_EC_DA1

SMB_EC_CK2 SMB_EC_DA2

SMB_CK_CLK1 SMB_CK_DAT1ICH9

LCD_CLK LCD_DAT

KB926

Cantiga

Symbol Note :

: means Digital Ground

: means Analog Ground

@ : means just reserve , no build ME@ : means ME part. 45@ : means install after SMT.

INVERTERBATTEEPROM

X X

X XX

SERIAL

VV

XX X

X XX

THERMAL SENSOR

SODIMMCLK CHIP

(CPU)

XX

X

V

X

V V V

X X

MINI CARD

LCD

XX X

X X

X

V

I2C / SMBUS ADDRESSING

DEVICE

DDR SO-DIMM 0 CLOCK GENERATOR (EXT.)

HEX ADDRESS

A0 D2

1 0 1 0 0 0 0 0 1 1 0 1 0 0 1 0

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

2009/04/20 2010/04/30

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

Notes List

LS-5588

3 35Wednesday, July 01, 2009

0.3

5

4

3

2

1

XDP_TDI XDP_DBRESET# XDP_TDO XDP_TMS

0518/'09

H_RESET# [8]

@

R03

H_THERMDA H_THERMDC

XDP_TRST# XDP_TCK XDP_BPM#5

For ESD

XDP_BPM#5

R03

For EMI

H_PROCHOT#

R03

2

3

1

@

D12

D12 PJDLC05_SOT23-3

PJDLC05_SOT23-3

@

1

C1045

2

0.1U_0402_16V4Z

3

1

@

2

D9

D9 PJDLC05_SOT23-3

PJDLC05_SOT23-3

+3VS

C1035

1 2

2200P_0402_50V7K

R306

1 2

10K_0402_5%

+3VS

0.1U_0402_16V4Z

1

2

C1034

@

2

3

1

H_THERMDA H_THERMDC THERM#

D10

D10 PJDLC05_SOT23-3

PJDLC05_SOT23-3

U7

1 2 3 4

EMC1402-1-ACZL-TR_MSOP8

Address:100_1100

VDD DP DN THERM#

3

1

@

2

D11

D11 PJDLC05_SOT23-3

PJDLC05_SOT23-3

SMCLK

SMDATA

ALERT#

GND

8 7 6 5

D D

H_A#[3..16][8]

H_A#[17..35][8]

C C

B B

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16

H_ADSTB#0[8]

H_REQ#0[8] H_REQ#1[8] H_REQ#2[8] H_REQ#3[8] H_REQ#4[8]

H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35

H_ADSTB#1[8]

H_A20M#[23]

H_FERR#[23]

H_IGNNE#[23] H_STPCLK#[23]

H_INTR[23]

H_NMI[23] H_SMI#[23]

U1A

P2

A[3]#

V4

A[4]#

W1

A[5]#

T4 AA1 AB4

T2 AC5 AD2 AD4 AA5 AE5 AB2 AC1

Y4

R1

R5

U1

P4

W5

AN1 AK4 AG1

AT4

AK2

AT2 AH2 AF4

AJ5 AH4 AM4 AP4 AR5

AJ1

AL1 AM2 AU5 AP2 AR1 AN5

C7 D4

F10

F8 C9 C5 E5

V2 Y2

AG5

AL5

J9 F4 H8

A[6]# A[7]# A[8]# A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# ADSTB[0]#

REQ[0]# REQ[1]# REQ[2]# REQ[3]# REQ[4]#

A[17]# A[18]# A[19]# A[20]# A[21]# A[22]# A[23]# A[24]# A[25]# A[26]# A[27]# A[28]# A[29]# A[30]# A[31]# A[32]# A[33]# A[34]# A[35]# ADSTB[1]#

A20M# FERR# IGNNE#

STPCLK# LINT0 LINT1 SMI#

RSVD01 RSVD02 RSVD03 RSVD04 RSVD05 RSVD06 RSVD07

ADDR GROUP 0 ADDR GROUP 1

ICH

ADS# BNR# BPRI#

DEFER#

DRDY# DBSY#

BR0#

IERR#

INIT#

CONTROL

LOCK#

RESET#

RS[0]# RS[1]# RS[2]#

TRDY#

HITM#

BPM[0]# BPM[1]# BPM[2]# BPM[3]#

PRDY# PREQ#

TDO TMS

TRST#

DBR#

XDP/ITP SIGNALS

THERMAL

PROCHOT#

THERMDA THERMDC

THERMTRIP#

H CLK

BCLK[0] BCLK[1]

M4 J5 L5

N5 F38 J1

M2 B40

D8 N1 G5

K2 H4 K4 L1

H2

HIT#

F2 AY8

BA7 BA5 AY2 AV10 AV2 AV4

TCK

AW7

TDI

AU1 AW5 AV8 J7

D38 BB34 BD34

B10

A35 C35

RESERVED

H_BPRI# [8] H_DEFER# [8]

H_INIT# [23] H_LOCK# [8]

H_RESET#

H_TRDY# [8]

XDP_BPM#5_R XDP_TCK XDP_TDI XDP_TDO XDP_TMS XDP_TRST# XDP_DBRESET#

H_PROCHOT#

Place Close to U1.

H_THERMDA_R H_THERMDC_R

H_THERMTRIP#

H_THERMDA, H_THERMDC routing together, Trace width / Spacing = 10 / 10 mil

CLK_CPU_BCLK [16] CLK_CPU_BCLK# [16]

Place close to U1.

+VCCP

H_ADS# [8] H_BNR# [8]

H_DRDY# [8] H_DBSY# [8]

H_BR0# [8]

H_RS#0 [8] H_RS#1 [8] H_RS#2 [8]

H_HIT# [8] H_HITM# [8]

R22 68_0402_5%

R22 68_0402_5% R23 0_0402_5%R23 0_0402_5% R24 0_0402_5%R24 0_0402_5%

R25

1 2

1 2 1 2 1 2

1 2

R9

56_0402_5%

0.1U_0402_16V4Z

0_0402_5%

XDP_DBRESET# [24]

H_PROCHOT# [31]

H_THERMTRIP# [8,23]

R10

R10 51_0402_1%

51_0402_1%

9/20

1 2

1

C1251

2

Add 0 ohm per EMI request. 10/17

+VCCP

XDP_TDI XDP_TMS XDP_TDO

XDP_BPM#5

XDP_TRST# XDP_TCK

This shall place near CPU

SMB_EC_CK2 SMB_EC_DA2

R305 10K_0402_5%

1 2

R1 54.9_0402_1%R1 54.9_0402_1%

1 2

R2 54.9_0402_1%R2 54.9_0402_1%

1 2

R3 54.9_0402_1%R3 54.9_0402_1%

1 2

R4 54.9_0402_1%R4 54.9_0402_1%

1 2

R03

R6 51_0402_1%

1 2

R7 54.9_0402_1%R7 54.9_0402_1%

1 2

EC_SMB_CK2 [17,26]

EC_SMB_DA2 [17,26]

+3VS

+VCCP

PENRYN SFF_UFCBGA956

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/04/20 2010/04/30

H_A20M# H_FERR# H_IGNNE# H_INIT# H_STPCLK# H_INTR H_NMI H_SMI#

For ESD 4/21

Compal Secret Data

Deciphered Date

1

C1037

C1036

2

0.1U_0402_16V4Z

@

2

1

C1038

C1039

2

0.1U_0402_16V4Z

@

Title

Size Document Number Rev

Custom

LS-5588

Date: Sheet of

1

C1041

C1040

2

0.1U_0402_16V4Z

@

Compal Electronics, Inc.

Penryn(1/3)-AGTL+/ITP-XDP

1

C1043

C1042

2

0.1U_0402_16V4Z

@

0.3

4 35Wednesday, July 01, 2009

1

0.3

5

4

3

2

1

H_D#[0..15][8]

D D

H_DSTBN#0[8] H_DSTBP#0[8] H_DINV#0[8] H_D#[16..31][8]

C C

layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs

H_DSTBN#1[8] H_DSTBP#1[8] H_DINV#1[8]

CPU_BSEL0[16] CPU_BSEL1[16] CPU_BSEL2[16]

V_CPU_GTLREF

T8T8

T9T9 T10T10

H_D#0 H_D#1

H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_DSTBN#0 H_DSTBP#0 H_DINV#0

H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_DSTBN#1 H_DSTBP#1 H_DINV#1

TEST2

TEST5 TEST6

CPU_BSEL CPU_BSEL2 CPU_BSEL1

B B

166

200

0 1

0

1

U1B

F40

D[0]#

G43

D[1]#

E43

D[2]#

J43

D[3]#

H40

D[4]#

H44

D[5]#

G39

D[6]#

E41

D[7]#

L41

D[8]#

K44

D[9]#

N41

D[10]#

T40

D[11]#

M40

D[12]#

G41

D[13]#

M44

D[14]#

L43

D[15]#

K40

DSTBN[0]#

J41

DSTBP[0]#

P40

DINV[0]#

P44

D[16]#

V40

D[17]#

V44

D[18]#

AB44

D[19]#

R41

D[20]#

W41

D[21]#

N43

D[22]#

U41

D[23]#

AA41

D[24]#

AB40

D[25]#

AD40

D[26]#

AC41

D[27]#

AA43

D[28]#

Y40

D[29]#

Y44

D[30]#

T44

D[31]#

U43

DSTBN[1]#

W43

DSTBP[1]#

R43

DINV[1]#

AW43

GTLREF

E37

TEST1

D40

TEST2

C43

TEST3

AE41

TEST4

AY10

TEST5

AC43

TEST6

A37

BSEL[0]

C37

BSEL[1]

B38

BSEL[2]

PENRYN SFF_UFCBGA956

CPU_BSEL0

1

0

D[32]# D[33]# D[34]#

DATA GROUP 0 DATA GROUP 1

D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]#

DATA GROUP 2DATA GROUP 3

D[45]# D[46]#

D[47]# DSTBN[2]# DSTBP[2]#

DINV[2]#

D[48]#

D[49]#

D[50]#

D[51]#

D[52]#

D[53]#

D[54]#

D[55]#

D[56]#

D[57]#

D[58]#

D[59]#

D[60]#

D[61]#

D[62]#

D[63]# DSTBN[3]# DSTBP[3]#

DINV[3]# COMP[0]

MISC

COMP[1] COMP[2] COMP[3]

DPRSTP#

DPSLP#

DPWR#

PWRGOOD

SLP#

PSI#

Cause CPU core power change to 1 phase, and not need support the pin, leave it as TP. 10/02

AR43 AH40 AF40 AJ43 AG41 AF44 AH44 AM44 AN43 AM40 AK40 AG43 AP40 AN41 AL41 AK44 AL43 AJ41

AV38 AT44 AV40 AU41 AW41 AR41 BA37 BB38 AY36 AT40 BC35 BC39 BA41 BB40 BA35 AU43 AY40 AY38 BC37

AE43 AD44 AE1 AF2

G7 B8 C41 E7 D10 BD10

H_PSI#

H_D#33 H_D#34H_D#2 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_DSTBN#2 H_DSTBP#2 H_DINV#2

H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_DSTBN#3 H_DSTBP#3 H_DINV#3

COMP0 COMP1 COMP2 COMP3

H_D#32

AP44

H_DPRSTP# [8,23,31]

H_DPSLP# [23] H_DPWR# [8] H_PWRGOOD [23]

H_CPUSLP# [8]

T11T11

H_D#[32..47] [8]

H_DSTBN#2 [8] H_DSTBP#2 [8] H_DINV#2 [8] H_D#[48..63] [8]

H_DSTBN#3 [8] H_DSTBP#3 [8] H_DINV#3 [8]

R32

R33

R31

R30

12

27.4_0402_1%

54.9_0402_1%

27.4_0402_1%

54.9_0402_1%

Resistor placed within

0.5" of CPU pin.Trace should be at least 25 mils away from any other toggling signal. COMP[0,2] trace width is 18 mils. COMP[1,3] trace width is 4 mils.

266 0 0 0

+VCC_CORE +VCC_CORE

U1C

F32

VCC[001]

G33

VCC[002]

H32

VCC[003]

J33

VCC[004]

K32

VCC[005]

L33

VCC[006]

M32

VCC[007]

N33

VCC[008]

P32

VCC[009]

R33

VCC[010]

T32

VCC[011]

U33

VCC[012]

V32

VCC[013]

W33

VCC[014]

Y32

VCC[015]

AA33

VCC[016]

AB32

VCC[017]

AC33

VCC[018]

AD32

VCC[019]

AE33

VCC[020]

AF32

VCC[021]

AG33

VCC[022]

AH32

VCC[023]

AJ33

VCC[024]

AK32

VCC[025]

AL33

VCC[026]

AM32

VCC[027]

AN33

VCC[028]

AP32

VCC[029]

AR33

VCC[030]

AT34

VCC[031]

AT32

VCC[032]

AU33

VCC[033]

AV32

VCC[034]

AY32

VCC[035]

BB32

VCC[036]

BD32

VCC[037]

B28

VCC[038]

B30

VCC[039]

B26

VCC[040]

D28

VCC[041]

D30

VCC[042]

F30

VCC[043]

F28

VCC[044]

H30

VCC[045]

H28

VCC[046]

D26

VCC[047]

F26

VCC[048]

H26

VCC[049]

K30

VCC[050]

K28

VCC[051]

M30

VCC[052]

M28

VCC[053]

K26

VCC[054]

M26

VCC[055]

P30

VCC[056]

P28

VCC[057]

T30

VCC[058]

T28

VCC[059]

V30

VCC[060]

V28

VCC[061]

P26

VCC[062]

T26

VCC[063]

V26

VCC[064]

Y30

VCC[065]

Y28

VCC[066]

AB30

VCC[067]

PENRYN SFF_UFCBGA956

VCC[068] VCC[069] VCC[070] VCC[071] VCC[072] VCC[073] VCC[074] VCC[075] VCC[076] VCC[077] VCC[078] VCC[079] VCC[080] VCC[081] VCC[082] VCC[083] VCC[084] VCC[085] VCC[086] VCC[087] VCC[088] VCC[089] VCC[090] VCC[091] VCC[092] VCC[093] VCC[094] VCC[095] VCC[096] VCC[097] VCC[098] VCC[099] VCC[100]

VCCP_001 VCCP_002 VCCP_003 VCCP_004 VCCP_005 VCCP_006 VCCP_007 VCCP_008 VCCP_009 VCCP_010 VCCP_011 VCCP_012 VCCP_013 VCCP_014 VCCP_015 VCCP_016

VCCA[01] VCCA[02]

VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6]

VCCSENSE

VSSSENSE

AB28 AD30 AD28 Y26 AB26 AD26 AF30 AF28 AH30 AH28 AF26 AH26 AK30 AK28 AM30 AM28 AP30 AP28 AK26 AM26 AP26 AT30 AT28 AV30 AV28 AY30 AY28 AT26 AV26 AY26 BB30 BB28 BD30

R27 0_0402_5%R27 0_0402_5%

1 2

J11

R28 0_0402_5% R28 0_0402_5%

1 2

E11

R29 0_0402_5% R29 0_0402_5%

1 2

G11 J37 K38 L37 N37 P38 R37 U37 V38 W37 AA37 AB38 AC37 AE37

B34 D34

BD8 BC7 BB10 BB8 BC5 BB4 AY4

VCCSENSE

BD12

VSSSENSE

BC13

Length match within 25 mils. The trace width/space/other is 20/7/25.

+VCCP

1

+

330U_D2E_2.5VM_R9M

2

CPU_VID0 [31] CPU_VID1 [31] CPU_VID2 [31] CPU_VID3 [31] CPU_VID4 [31] CPU_VID5 [31] CPU_VID6 [31]

VCCSENSE [31]

VSSSENSE [31]

C5

0.01U_0402_16V7K

Near pin B34

Change to 330u_R9, casue high limitation. 12/14

1

C6

2

10U_0805_6.3V6M

+1.5VS

C7

Near pin D34

+VCC_CORE

R34

+VCCP

12

R36

Z=55 ohm

V_CPU_GTLREF

A A

Close to CPU pin AW43 within 500mils.

R36 1K_0402_1%

1K_0402_1%

12

R37

R37 2K_0402_1%

2K_0402_1%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/04/20 2010/04/30

Compal Secret Data

Deciphered Date

2

1 2

100_0402_1%

100_0402_1% R35

R35

1 2

100_0402_1%

Close to CPU pin within 500mils.

Title

Size Document Number Rev

Custom

Date: Sheet of

VCCSENSE

VSSSENSE

Compal Electronics, Inc.

Penryn(2/3)-AGTL+/ITP-XDP

LS-5588

1

0.3

5 35Wednesday, July 01, 2009

0.3

5

D D

AL37

AN37

AP38

B32

C33

D32

E35

E33

F34

G35

F36

H36

J35

L35

N35

K36

R35

U35

P36

V36

W35

AA35

AC35

AB36

AE35

C C

VCCP_021

VCCP_022

VCCP_023

VCCP_024

VCCP_025

VCCP_026

VCCP_027

VCCP_028

VCCP_029

VCCP_030

VCCP_031

VCCP_032

VCCP_033

VCCP_034

VCCP_035

VCCP_036

VCCP_037

VCCP_038

VCC_101

VCC_102

VCC_103

VCC_104

VCC_105

VCC_106

VCC_107

VCC_108

VCC_109

VCC_110

VCC_111

VCC_112

VCC_113

VCC_114

VCC_115

VCC_116

VCC_117

VCC_118

F24

F22

B22

B24

D22

D24

BD28

BB26

H24

BD26

T24

H22

K24

K22

P24

P22

M24

M22

AG35

VCCP_039

VCCP_040

VCCP_041

VCCP_042

VCCP_043

VCCP_044

VCCP_045

VCCP_046

VCC_119

VCC_120

VCC_121

VCC_122

VCC_123

VCC_124

VCC_125

VCC_126

T22

V24

V22

Y24

Y22

AB24

AB22

AD24

4

AJ35

AF36

AL35

AN35

AK36

AP36

B12

B14

C13

D12

D14

E13

F14

F12

G13

H14

H12

J13

K14

K12

L13

L11

M14

N13

N11

K10

P14

P12

R13

R11

T14

U13

U11

V14

V12

VCCP_047

VCCP_048

VCCP_049

VCCP_050

VCCP_051

VCCP_052

VCCP_053

VCCP_054

VCCP_055

VCCP_056

VCCP_057

VCCP_058

VCCP_059

VCCP_060

VCCP_061

VCCP_062

VCCP_063

VCCP_064

VCCP_065

VCCP_066

VCCP_067

VCCP_068

VCCP_069

VCCP_070

VCCP_071

VCCP_072

VCCP_073

VCCP_074

VCCP_075

VCCP_076

VCCP_077

VCCP_078

VCCP_079

VCCP_080

VCC_127

VCC_128

VCC_129

VCC_130

VCC_131

VCC_132

VCC_133

VCC_134

VCC_135

VCC_136

VCC_137

VCC_138

VCC_139

VCC_140

VCC_141

VCC_142

VCC_143

VCC_144

VCC_145

VCC_146

VCC_147

VCC_148

VCC_149

VCC_150

VCC_151

VCC_152

VCC_153

VCC_154

VCC_155

VCC_156

VCC_157

VCC_158

VCC_159

VCC_160

F18

F16

B16

B18

AF24

AF22

AD22

AH24

AT24

AH22

AT22

AK24

AK22

AP24

AP22

AV24

AV22

AM24

AY24

AM22

B20

AY22

BB24

BB22

BD24

BD22

F20

D16

D18

H18

H16

D20

H20

K18

K16

VCCP_081

VCC_161

3

W13

W11

P10

V10

Y14

AA13

AA11

AB14

AB12

AC13

AC11

AD14

AB10

AE13

AE11

AF14

AF12

AG13

AG11

AH14

AJ13

AJ11

AF10

AK14

AK12

AL13

AL11

AN13

AN11

AP12

AR13

AR11

AK10

AP10

VCCP_082

VCCP_083

VCCP_084

VCCP_085

VCCP_086

VCCP_087

VCCP_088

VCCP_089

VCCP_090

VCCP_091

VCCP_092

VCCP_093

VCCP_094

VCCP_095

VCCP_096

VCCP_097

VCCP_098

VCCP_099

VCCP_100

VCCP_101

VCCP_102

VCCP_103

VCCP_104

VCCP_105

VCCP_106

VCCP_107

VCCP_108

VCCP_109

VCCP_110

VCCP_111

VCCP_112

VCCP_113

VCCP_114

VCCP_115

VCC_162

VCC_163

VCC_164

VCC_165

VCC_166

VCC_167

VCC_168

VCC_169

VCC_170

VCC_171

VCC_172

VCC_173

VCC_174

VCC_175

VCC_176

VCC_177

VCC_178

VCC_179

VCC_180

VCC_181

VCC_182

VCC_183

VCC_184

VCC_185

VCC_186

VCC_187

VCC_188

VCC_189

VCC_190

VCC_191

VCC_192

VCC_193

VCC_194

VCC_195

T18

T16

K20

M18

M16

M20

T20

P18

P16

V18

V16

P20

V20

Y18

Y16

Y20

AF18

AF16

AB18

AB16

AD18

AD16

AF20

AB20

AD20

AH18

AH16

AH20

AK18

AK16

AP18

AP16

AM18

AM16

2

AU13

AU11

VCCP_116

VCCP_117

VCCP_118L9VCCP_119L7VCCP_120N9VCCP_121N7VCCP_122R9VCCP_123R7VCCP_124U9VCCP_125U7VCCP_126W9VCCP_127W7VCCP_128

VCC_196

VCC_197

VCC_198

VCC_199

VCC_200

VCC_201

VCC_202

VCC_203

AT18

AT16

AK20

AP20

AV18

AV16

AY18

AM20

1

+VCCP

AA9

AA7

AC9

AC7

AE9

AE7

AG9

AG7

AJ9

AJ7

AL9

AL7

AN9

AN7

AR9

AR7

A33

A13

U1F

U1F PENRYN SFF_UFCBGA956

PENRYN SFF_UFCBGA956

VCCP_129

VCCP_130

VCCP_131

VCCP_132

VCCP_133

VCCP_134

VCCP_135

VCCP_136

VCCP_137

VCCP_138

VCCP_139

VCCP_140

VCCP_141

VCCP_142

VCCP_143

VCCP_144

VCCP_145

VCC_204

VCC_205

VCC_206

VCC_207

VCC_208

VCC_209

VCC_210

VCC_211

VCC_212

VCC_213

VCC_214

VCC_215

VCC_216

VCC_217

VCC_218

VCC_219

VCC_220

VCCP_020

VCCP_018

VCCP_019

VCCP_017

AT20

AY16

AV20

AY20

BB18

AT14

BB16

BD18

BD16

BB20

BD20

AP14

AM14

AJ37

AF38

AV14

AY14

BB14

BD14

AK38

AG37

+VCC_CORE +VCCP

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/04/20 2010/04/30

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

Penryn(3/3)-Power

LS-5588

1

0.3

6 35Wednesday, July 01, 2009

0.3

5

U1E

U1D

B42

VSS[001]

F44

VSS[002]

D44

VSS[003]

D42

VSS[004]

F42

VSS[005]

H42

VSS[006]

K42

VSS[007]

M42

VSS[008]

P42

VSS[009]

T42

VSS[010]

V42

VSS[011]

Y42

D D

C C

B B

A A

VSS[012]

AB42

VSS[013]

AD42

VSS[014]

AF42

VSS[015]

AH42

VSS[016]

AK42

VSS[017]

AM42

VSS[018]

AP42

VSS[019]

AY44

VSS[020]

AV44

VSS[021]

AT42

VSS[022]

AV42

VSS[023]

AY42

VSS[024]

BA43

VSS[025]

BB42

VSS[026]

C39

VSS[027]

E39

VSS[028]

G37

VSS[029]

H38

VSS[030]

J39

VSS[031]

L39

VSS[032]

M38

VSS[033]

N39

VSS[034]

R39

VSS[035]

T38

VSS[036]

U39

VSS[037]

W39

VSS[038]

Y38

VSS[039]

AA39

VSS[040]

AC39

VSS[041]

AD38

VSS[042]

AE39

VSS[043]

AG39

VSS[044]

AH38

VSS[045]

AJ39

VSS[046]

AL39

VSS[047]

AM38

VSS[048]

AN39

VSS[049]

AR39

VSS[050]

AR37

VSS[051]

AT38

VSS[052]

AU39

VSS[053]

AU37

VSS[054]

AW39

VSS[055]

AW37

VSS[056]

BA39

VSS[057]

BC41

VSS[058]

BD40

VSS[059]

BD38

VSS[060]

B36

VSS[061]

H34

VSS[062]

D36

VSS[063]

K34

VSS[064]

M34

VSS[065]

M36

VSS[066]

P34

VSS[067]

T34

VSS[068]

V34

VSS[069]

T36

VSS[070]

Y34

VSS[071]

AB34

VSS[072]

AD34

VSS[073]

Y36

VSS[074]

AD36

VSS[075]

AF34

VSS[076]

AH34

VSS[077]

AH36

VSS[078]

AK34

VSS[079]

AM34

VSS[080]

AP34

VSS[081]

PENRYN SFF_UFCBGA956

VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163]

5

AM36 AR35 AU35 AV34 AW35 AW33 AY34 AT36 AV36 BA33 BC33 BB36 BD36 C27 C29 C31 E29 E27 G29 G27 E31 G31 J29 J27 L29 L27 N29 N27 J31 L31 N31 R29 R27 U29 U27 R31 U31 W29 W27 W31 AA29 AA27 AC29 AC27 AA31 AC31 AE29 AE27 AG29 AG27 AJ29 AJ27 AE31 AG31 AJ31 AL29 AL27 AN29 AN27 AL31 AN31 AR29 AR27 AR31 AU29 AU27 AW29 AW27 AU31 AW31 BA29 BA27 BC29 BC27 BA31 BC31 C21 C23 C25 E25 E23 E21

U1E

G25

VSS_164

G23

VSS_165

G21

VSS_166

J25

VSS_167

J23

VSS_168

J21

VSS_169

L25

VSS_170

L23

VSS_171

L21

VSS_172

N25

VSS_173

N23

VSS_174

N21

VSS_175

R25

VSS_176

R23

VSS_177

R21

VSS_178

U25

VSS_179

U23

VSS_180

U21

VSS_181

W25

VSS_182

W23

VSS_183

W21

VSS_184

AA25

VSS_185

AA23

VSS_186

AA21

VSS_187

AC25

VSS_188

AC23

VSS_189

AC21

VSS_190

AE25

VSS_191

AE23

VSS_192

AE21

VSS_193

AG25

VSS_194

AG23

VSS_195

AG21

VSS_196

AJ25

VSS_197

AJ23

VSS_198

AJ21

VSS_199

AL25

VSS_200

AL23

VSS_201

AL21

VSS_202

AN25

VSS_203

AN23

VSS_204

AN21

VSS_205

AR25

VSS_206

AR23

VSS_207

AR21

VSS_208

AU25

VSS_209

AU23

VSS_210

AU21

VSS_211

AW25

VSS_212

AW23

VSS_213

AW21

VSS_214

BA25

VSS_215

BA23

VSS_216

BA21

VSS_217

BC25

VSS_218

BC23

VSS_219

BC21

VSS_220

C17

VSS_221

C19

VSS_222

E19

VSS_223

E17

VSS_224

G19

VSS_225

G17

VSS_226

J19

VSS_227

J17

VSS_228

L19

VSS_229

L17

VSS_230

N19

VSS_231

N17

VSS_232

R19

VSS_233

R17

VSS_234

U19

VSS_235

U17

VSS_236

W19

VSS_237

W17

VSS_238

AA19

VSS_239

AA17

VSS_240

AC19

VSS_241

AC17

VSS_242

AE19

VSS_243

AE17

VSS_244

AG19

VSS_245

AG17

VSS_246

AJ19

VSS_247

AJ17

VSS_248

AL19

VSS_249

AL17

VSS_250

AN19

VSS_251

AN17

VSS_252

AR19

VSS_253

AR17

VSS_254

AU19

VSS_255

AU17

VSS_256

AW19

VSS_257

AW17

VSS_258

BA19

VSS_259

BA17

VSS_260

BC19

VSS_261

BC17

VSS_262

C11

VSS_263

C15

VSS_264

E15

VSS_265

G15

VSS_266

H10

VSS_267

M12

VSS_268

J15

VSS_269

L15

VSS_270

N15

VSS_271

M10

VSS_272

T12

VSS_273

R15

VSS_274

U15

VSS_275

W15

VSS_276

T10

VSS_277

Y12

VSS_278

AD12

VSS_279

PENRYN SFF_UFCBGA956

VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286 VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296 VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305 VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313 VSS_314 VSS_315 VSS_316 VSS_317 VSS_318 VSS_319 VSS_320 VSS_321 VSS_322 VSS_323 VSS_324 VSS_325 VSS_326 VSS_327 VSS_328 VSS_329 VSS_330 VSS_331 VSS_332 VSS_333 VSS_334 VSS_335 VSS_336 VSS_337 VSS_338 VSS_339 VSS_340 VSS_341 VSS_342 VSS_343 VSS_344 VSS_345 VSS_346 VSS_347 VSS_348 VSS_349 VSS_350 VSS_351 VSS_352 VSS_353 VSS_354 VSS_355 VSS_356 VSS_357 VSS_358 VSS_359 VSS_360 VSS_361 VSS_362 VSS_363 VSS_364 VSS_365 VSS_366 VSS_367 VSS_368 VSS_369 VSS_370 VSS_371 VSS_372 VSS_373 VSS_374 VSS_375 VSS_376 VSS_377 VSS_378 VSS_379 VSS_380 VSS_381 VSS_382 VSS_383 VSS_384 VSS_385 VSS_386 VSS_387 VSS_388 VSS_389 VSS_390 VSS_391 VSS_392 VSS_393 VSS_394 VSS_395

AA15 AC15 Y10 AD10 AH12 AE15 AG15 AJ15 AH10 AM12 AL15 AN15 AR15 AM10 AT12 AV12 AW13 AW11 AY12 AU15 AW15 AT10 BA13 BA11 BB12 BC11 BA15 BC15 B6 D6 E9 F6 G9 H6 K8 K6 M8 M6 P8 P6 T8 T6 V8 V6 U5 Y8 Y6 AB8 AB6 AD8 AD6 AF8 AF6 AH8 AH6 AK8 AK6 AM8 AM6 AP8 AP6 AT8 AT6 AU9 AV6 AU7 AW9 AY6 BA9 BB6 BC9 BD6 B4 C3 E3 G3 J3 L3 N3 R3 U3 W3 AA3 AC3 AE3 AG3 AJ3 AL3 AN3 AR3 AU3 AW3 BA3 BC3 D2 E1 G1 AW1 BA1 BB2 A41 A39 A29 A27 A31 A25 A23 A21 A19 A17 A11 A15 A7 A5 A9 BD4

4

+VCC_CORE

10U_0603_6.3V6M

C8

+VCC_CORE

1U_0402_6.3V6K

C32

Mid Frequence Decoupling

10U_0603_6.3V6M

1

2

1

2

1

C9

C10

2

1U_0402_6.3V6K

1

C33

C34

2

3

10U_0603_6.3V6M

1

C11

2

High Frequence Decoupling

1U_0402_6.3V6K

1

C35

2

10U_0603_6.3V6M

1

C13

C12

2

1U_0402_6.3V6K

1

C37

C36

2

10U_0603_6.3V6M

1

C14

2

1

C38

2

1

C16

C15

2

1U_0402_6.3V6K

1

C39

C40

2

10U_0603_6.3V6M

1U_0402_6.3V6K

10U_0603_6.3V6M

1

C17

C18

2

1U_0402_6.3V6K

1

C41

C42

2

10U_0603_6.3V6M

1

C19

C20

2

1U_0402_6.3V6K

1

C44

C43

2

10U_0603_6.3V6M

1

C21

C22

2

1U_0402_6.3V6K

1

C46

C45

2

10U_0603_6.3V6M

1

C24

C23

2

1U_0402_6.3V6K

1

C48

C47

2

10U_0603_6.3V6M

1

C25

2

1

C49

2

1

C27

C26

2

1U_0402_6.3V6K

1

C51

C50

2

1

10U_0603_6.3V6M

1

C28

2

1U_0402_6.3V6K

1

C52

2

10U_0603_6.3V6M

1

C29

2

1

C53

2

1

C30

C31

2

1U_0402_6.3V6K

1

C54

C55

2

6/14 :Replace 12pcs 10uF_0805 to 24 pcs 1uF_0402 for CPU transient fail issue.

ESR <= 1.5m ohm

Near CPU CORE regulator

+VCC_CORE

220U_D2_2VK_R9

1

+

C56

2

Del C37 to improve power plan. 6/14

+VCCP

1U_0402_6.3V6K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/04/20 2010/04/30

1U_0402_6.3V6K

1

C60

C59

2

1U_0402_6.3V6K

1

C63

C61

2

C63

C62

2

Compal Secret Data

Deciphered Date

1U_0402_6.3V6K

1

2

220U_D2_2VK_R9

1

C57

2

1

C64

2

220U_D2_2VK_R9

1

+

C58

2

1U_0402_6.3V6K

1

C65

2

1U_0402_6.3V6K

1

C66

C67

2

1U_0402_6.3V6K

1

C68

2

1

C70

C69

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

Penryn(3/3)-GND/Bypass

LS-5588

1

0.3

7 35Wednesday, July 01, 2009

0.3

5

U3A

H_D#[0..63][5]

D D

C C

H_RESET#[4]

H_CPUSLP#[5]

layout note:

B B

Route H_SCOMP and H_SCOMP# with trace width, spacing and impedance (55 ohm) same as FSB data traces

Layout Note: H_RCOMP / H_VREF / H_SWNG

trace width and spacing is 10/20

+VCCP

12

R55

1K_0402_1%

H_VREF

12

R592K_0402_1%

1

C78

A A

C78

2

0.1U_0402_16V4Z

@

within 100 mils from NB

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

H_SWNG H_RCOMP

H_VREF

Trace < = 500mils

H_RCOMP

12

R60

24.9_0402_1%

U3A

J7

H_D#_0

H6

H_D#_1

L11

H_D#_2

J3

H_D#_3

H4

H_D#_4

G3

H_D#_5

K10

H_D#_6

K12

H_D#_7

L1

H_D#_8

M10

H_D#_9

M6

H_D#_10

N11

H_D#_11

L7

H_D#_12

K6

H_D#_13

M4

H_D#_14

K4

H_D#_15

P6

H_D#_16

W9

H_D#_17

V6

H_D#_18

V2

H_D#_19

P10

H_D#_20

W7

H_D#_21

N9

H_D#_22

P4

H_D#_23

U9

H_D#_24

V4

H_D#_25

U1

H_D#_26

W3

H_D#_27

V10

H_D#_28

U7

H_D#_29

W11

H_D#_30

U11

H_D#_31

AC11

H_D#_32

AC9

H_D#_33

Y4

H_D#_34

Y10

H_D#_35

AB6

H_D#_36

AA9

H_D#_37

AB10

H_D#_38

AA1

H_D#_39

AC3

H_D#_40

AC7

H_D#_41

AD12

H_D#_42

AB4

H_D#_43

Y6

H_D#_44

AD10

H_D#_45

AA11

H_D#_46

AB2

H_D#_47

AD4

H_D#_48

AE7

H_D#_49

AD2

H_D#_50

AD6

H_D#_51

AE3

H_D#_52

AG9

H_D#_53

AG7

H_D#_54

AE11

H_D#_55

AK6

H_D#_56

AF6

H_D#_57

AJ9

H_D#_58

AH6

H_D#_59

AF12

H_D#_60

AH4

H_D#_61

AJ7

H_D#_62

AE9

H_D#_63

B6

H_SWING

D4

H_RCOMP

J11

H_CPURST#

G9

H_CPUSLP#

L17

H_AVREF

K18

H_DVREF

CANTIGA GMCH SFF_FCBGA1363

+VCCP

12

221_0603_1%

12

100_0402_1%

R56

R61

0.1U_0402_16V4Z

Near B6 pin

H_SWNG

1

2

H_ADSTB#_0 H_ADSTB#_1

HOST

H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3

H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3

layout note: Place them close to U4 pin BC51.

Layout Note: V_DDR_MCH_REF trace width and spacing is 20/20.

C79

H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8

H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35

H_ADS#

H_BNR# H_BPRI#

H_BREQ#

H_DEFER#

H_DBSY#

HPLL_CLK

HPLL_CLK#

H_DPWR#

H_DRDY#

H_HIT#

H_HITM#

H_LOCK# H_TRDY#

H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3

H_REQ#_0 H_REQ#_1

H_REQ#_2 H_REQ#_3

H_REQ#_4

H_RS#_0 H_RS#_1 H_RS#_2

PM_EXTTS#0 PM_EXTTS#1

4

H_A#3

L15

H_A#4

B14

H_A#5

C15

H_A#6

D12

H_A#7

F14

H_A#8

G17

H_A#9

B12

H_A#10

J15

H_A#11

D16

H_A#12

C17

H_A#13

D14

H_A#14

K16

H_A#15

F16

H_A#16

B16

H_A#17

C21

H_A#18

D18

H_A#19

J19

H_A#20

J21

H_A#21

B18

H_A#22

D22

H_A#23

G19

H_A#24

J17

H_A#25

L21

H_A#26

L19

H_A#27

G21

H_A#28

D20

H_A#29

K22

H_A#30

F18

H_A#31

K20

H_A#32

F20

H_A#33

F22

H_A#34

B20

H_A#35

A19 F10

A15 C19 C9 B8 C11 E5 D6 AH10 AJ11 G11 H2 C7 F8 A11 D8

L9 N7 AA7 AG3

K2 N3 AA3 AF4

L3 M2 Y2 AF2

J13 L13 C13 G13 G15

F4 F2 G7

R62 10K_0402_5%

1 2

R63 10K_0402_5%R63 10K_0402_5%

1 2

Del R48. 9/27

H_A#[3..35] [4]

H_ADS# [4] H_ADSTB#0 [4] H_ADSTB#1 [4] H_BNR# [4] H_BPRI# [4] H_BR0# [4] H_DEFER# [4] H_DBSY# [4] CLK_MCH_BCLK [16] CLK_MCH_BCLK# [16] H_DPWR# [5] H_DRDY# [4] H_HIT# [4] H_HITM# [4] H_LOCK# [4] H_TRDY# [4]

H_DINV#0 [5] H_DINV#1 [5] H_DINV#2 [5] H_DINV#3 [5]

H_DSTBN#0 [5] H_DSTBN#1 [5] H_DSTBN#2 [5] H_DSTBN#3 [5]

H_DSTBP#0 [5] H_DSTBP#1 [5] H_DSTBP#2 [5] H_DSTBP#3 [5]

H_REQ#0 [4] H_REQ#1 [4] H_REQ#2 [4] H_REQ#3 [4] H_REQ#4 [4]

H_RS#0 [4] H_RS#1 [4] H_RS#2 [4]

DDR3_NB_REF

3

Add them for Boundary Scan. 10/23

R38 1K_0402_5%@R38 1K_0402_5%@

1 2

R39 4.7K_0402_5%@R39 4.7K_0402_5%@

1 2

R40 4.7K_0402_5%@R40 4.7K_0402_5%@

1 2

R41 1K_0402_5%@R41 1K_0402_5%@

+3VS

H_THERMTRIP#[4,23] PM_DPRSLPVR[24,31]

+1.5V

C77

1

2

0.1U_0402_16V4Z

+3VS

1 2

2.2U_0603_6.3V4Z

SMRCOMP_VOH

SMRCOMP_VOL

2.2U_0603_6.3V4Z

PM_BMBUSY#[24]

H_DPRSTP#[5,23,31] PM_EXTTS#0[14] PM_EXTTS#1[15] PM_PWROK[24,26,31] PLT_RST#[17,22,26]

1 2

R51 0_0402_5%R51 0_0402_5%

Add R428 in 9/26

12

R54

R54 10K_0402_1%

10K_0402_1%

12

R57

R57 10K_0402_1%

10K_0402_1%

1

C71

C72

2

1

C73

C74

2

+1.5V

1

12

R42

0.01U_0402_25V7K

2

1K_0402_1%

12

R45

3.01K_0402_1%

12

R48

1

1K_0402_1%

2

0.01U_0402_25V7K

MCH_CLKSEL0[16] MCH_CLKSEL1[16] MCH_CLKSEL2[16]

T30T30

T31T31

CFG5[10] CFG6[10] CFG7[10]

T32T32

CFG9[10]

CFG10[10]

T33T33

CFG12[10] CFG13[10]

T34T34

T35T35

CFG16[10]

T36T36

T37T37

CFG19[10] CFG20[10]

PM_EXTTS#0 PM_EXTTS#1

R49 0_0402_5%R49 0_0402_5%

1 2

R50 100_0402_1% R50 100_0402_1%

1 2

T12T12 T13T13 T14T14 T15T15 T16T16 T17T17 T18T18 T19T19 T20T20

TCK TDI TDO TMS

T21T21 T22T22

T23T23

T24T24

T25T25 T26T26 T27T27 T28T28

C750.1U_0402_16V4Z@ C750.1U_0402_16V4Z@

1

2

RSVD1

L43

RSVD2

J41

RSVD3

L41

RSVD4

AN11

RSVD5

AM10

RSVD6

AK10

RSVD7

AL11

RSVD8

F12

RSVD9

AN45

RSVD10

AP44

RSVD11

AT44

RSVD12

AN47

RSVD13

C27

RSVD14

D30

RSVD15

J9

RSVD17

AW42

RSVD20

BB20

RSVD22

BE19

RSVD23

BF20

RSVD24

BF18

RSVD25

K26

CFG_0

G23

CFG_1

G25

CFG_2

J25

CFG_3

L25

CFG_4

L27

CFG_5

F24

CFG_6

D24

CFG_7

D26

CFG_8

J23

CFG_9

B26

CFG_10

A23

CFG_11

C23

CFG_12

B24

CFG_13

B22

CFG_14

K24

CFG_15

C25

CFG_16

L23

CFG_17

L33

CFG_18

K32

CFG_19

K34

CFG_20

J35

PM_SYNC#

F6

PM_DPRSTP#

J39

PM_EXT_TS#_0

L39

PM_EXT_TS#_1

AY39

PWROK

BB18

RSTIN#

K28

THERMTRIP#

K36

DPRSLPVR

A7

NC_1

A49

NC_2

A52

NC_3

A54

NC_4

B54

NC_5

D55

NC_6

G55

NC_7

BE55

NC_8

BH55

NC_9

BK55

NC_10

BK54

NC_11

BL54

NC_12

BL52

NC_13

BL49

NC_14

BL7

NC_15

BL4

NC_16

BL2

NC_17

BK2

NC_18

BK1

NC_19

BH1

NC_20

BE1

NC_21

G1

NC_22

CANTIGA GMCH SFF_FCBGA1363

U3B

J43

2

BB32

SA_CK_0

BA25

SA_CK_1

BA33

SB_CK_0

BA23

SB_CK_1

BA31

SA_CK#_0

BC25

SA_CK#_1

BC33

SB_CK#_0

BB24

SB_CK#_1

BC35

SA_CKE_0

BE33

SA_CKE_1

BE37

SB_CKE_0

BC37

SB_CKE_1

BK18

SA_CS#_0

BK16

SA_CS#_1

BE23

SB_CS#_0

BC19

SB_CS#_1

BJ17

SA_ODT_0

BJ19

SA_ODT_1

BC17

SB_ODT_0

BE17

SB_ODT_1

SM_RCOMP

SM_RCOMP#

SM_RCOMP_VOH SM_RCOMP_VOL

SM_VREF

SM_PWROK

SM_REXT

SM_DRAMRST#

DPLL_REF_CLK

DPLL_REF_CLK#

DDR CLK/ CONTROL/COMPENSATION

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

PEG_CLK

PEG_CLK#

CLK

DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3

DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3

DMI_TXN_0 DMI_TXN_1 DMI_TXN_2

CFGRSVD

PM

NC

DMI_TXN_3 DMI_TXP_0

DMI_TXP_1

DMI

DMI_TXP_2 DMI_TXP_3

GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3 GFX_VID_4

GFX_VR_EN

GRAPHICS VID

CL_CLK

CL_DATA

CL_PWROK

CL_RST#

CL_VREF

ME

DDPC_CTRLCLK

DDPC_CTRLDATA

SDVO_CTRLCLK

SDVO_CTRLDATA

CLKREQ#

ICH_SYNC#

MISC

TSATN#

HDA_BCLK HDA_RST#

HDA_SDI

HDA_SDO

HDA_SYNC

HDA

BL25 BK26

BK32 BL31

BC51 AY37 BH20 BA37

B42 D42 B50 D50

R49 P50

AG55 AL49 AH54 AL47

AG53 AK50 AH52 AL45

AG49 AJ49 AJ47 AG47

AF50 AH50 AJ45 AG45

G33 G37 F38 F36 G35

G39

AK52 AK54 AW40 AL53 AL55

F34 F32 B38 A37 C31 K42

D10

C29 B30 D28 A27 B28

SMRCOMP SMRCOMP#

SMRCOMP_VOH SMRCOMP_VOL

DDR3_NB_REF SM_PWROK SM_REXT SM_DRAMRST#

CLK_MCH_3GPLL [16] CLK_MCH_3GPLL# [16]

DMI_TXN0 [24] DMI_TXN1 [24] DMI_TXN2 [24] DMI_TXN3 [24]

DMI_TXP0 [24] DMI_TXP1 [24] DMI_TXP2 [24] DMI_TXP3 [24]

DMI_RXN0 [24] DMI_RXN1 [24] DMI_RXN2 [24] DMI_RXN3 [24]

DMI_RXP0 [24] DMI_RXP1 [24] DMI_RXP2 [24] DMI_RXP3 [24]

CL_VREF

TSATN#

R58 54.9_0402_1%R58 54.9_0402_1%

1 2

T38T38 T39T39

R46 10K_0402_1%@R46 10K_0402_1%@ R47 499_0402_1%R47 499_0402_1%

1

M_CLK_DDR0 [14] M_CLK_DDR1 [14] M_CLK_DDR2 [15] M_CLK_DDR3 [15]

M_CLK_DDR#0 [14] M_CLK_DDR#1 [14] M_CLK_DDR#2 [15] M_CLK_DDR#3 [15]

DDR_CKE0_DIMMA [14] DDR_CKE1_DIMMA [14] DDR_CKE2_DIMMB [15] DDR_CKE3_DIMMB [15]

DDR_CS0_DIMMA# [14] DDR_CS1_DIMMA# [14] DDR_CS2_DIMMB# [15] DDR_CS3_DIMMB# [15]

M_ODT0 [14] M_ODT1 [14] M_ODT2 [15] M_ODT3 [15]

R43 80.6_0402_1%

1 2

R44 80.6_0402_1%R44 80.6_0402_1%

R429 0_0402_5%R429 0_0402_5%

SM_DRAMRST# [14,15]

1 2

1 2 1 2

1 2

1.5V_PGOOD [28]

Modify in 9/26

+VCCP

CL_CLK0 [24] CL_DATA0 [24] M_PWROK [24] CL_RST# [24]

1

C76

0.1U_0402_16V4Z

CLKREQ#_B [16] MCH_ICH_SYNC# [24]

2

+VCCP

+1.5V

12

R52

R52 1K_0402_1%

1K_0402_1%

12

R53

R53 499_0402_1%

499_0402_1%

5

Security Classification Compal Secret Data

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/04/20 2010/04/30

3

Deciphered Date

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

Title

Cantiga(1/6)-AGTL/DMI/DDR

Size Document Number Rev

LS-5588

8 35Wednesday, July 01, 2009

1

0.3

5

D D

DDR_A_D[0..63][14]

C C

B B

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

U3D

AP46

SA_DQ_0

AU47

SA_DQ_1

AT46

SA_DQ_2

AU49

SA_DQ_3

AR45

SA_DQ_4

AN49

SA_DQ_5

AV50

SA_DQ_6

AP50

SA_DQ_7

AW47

SA_DQ_8

BD50

SA_DQ_9

AW49

SA_DQ_10

BA49

SA_DQ_11

BC49

SA_DQ_12

AV46

SA_DQ_13

BA47

SA_DQ_14

AY50

SA_DQ_15

BF46

SA_DQ_16

BC47

SA_DQ_17

BF50

SA_DQ_18

BF48

SA_DQ_19

BC43

SA_DQ_20

BE49

SA_DQ_21

BA43

SA_DQ_22

BE47

SA_DQ_23

BF42

SA_DQ_24

BC39

SA_DQ_25

BF44

SA_DQ_26

BF40

SA_DQ_27

BB40

SA_DQ_28

BE43

SA_DQ_29

BF38

SA_DQ_30

BE41

SA_DQ_31

BA15

SA_DQ_32

BE11

SA_DQ_33

BE15

SA_DQ_34

BF14

SA_DQ_35

BB14

SA_DQ_36

BC15

SA_DQ_37

BE13

SA_DQ_38

BF16

SA_DQ_39

BF10

SA_DQ_40

BC11

SA_DQ_41

BF8

SA_DQ_42

BG7

SA_DQ_43

BC7

SA_DQ_44

BC9

SA_DQ_45

BD6

SA_DQ_46

BF12

SA_DQ_47

AV6

SA_DQ_48

BB6

SA_DQ_49

AW7

SA_DQ_50

AY6

SA_DQ_51

AT10

SA_DQ_52

AW11

SA_DQ_53

AU11

SA_DQ_54

AW9

SA_DQ_55

AR11

SA_DQ_56

AT6

SA_DQ_57

AP6

SA_DQ_58

AL7

SA_DQ_59

AR7

SA_DQ_60

AT12

SA_DQ_61

AM6

SA_DQ_62

AU7

SA_DQ_63

CANTIGA GMCH SFF_FCBGA1363

DDR SYSTEM MEMORY A

SA_BS_0 SA_BS_1 SA_BS_2

SA_RAS# SA_CAS#

SA_WE#

SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7

SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6

SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7

SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8

SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14

4

BC21 BJ21 BJ41

BH22 BK20 BL15

AT50 BB50 BB46 BE39 BB12 BE7 AV10 AR9

AR47 BA45 BE45 BC41 BC13 BB10 BA7 AN7 AR49 AW45 BC45 BA41 BA13 BA11 BA9 AN9

BC23 BF22 BE31 BC31 BH26 BJ35 BB34 BH32 BB26 BF32 BA21 BG25 BH34 BH18 BE25

DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7

DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14

DDR_A_BS0 [14] DDR_A_BS1 [14] DDR_A_BS2 [14]

DDR_A_RAS# [14] DDR_A_CAS# [14]

DDR_A_WE# [14]

DDR_A_DM[0..7] [14]

DDR_A_DQS[0..7] [14]

DDR_A_DQS#[0..7] [14]

DDR_A_MA[0..14] [14]

3

DDR_B_D[0..63][15]

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8

DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

AP54 AM52 AR55 AV54

AM54

AN53 AT52 AU53

AW53

AY52 BB52 BC53 AV52

AW55

BD52 BC55 BF54 BE51 BH48 BK48 BE53 BH52 BK46

BJ47

BL45

BJ45 BL41 BH44 BH46 BK44 BK40

BJ39 BK10 BH10

BL11

BK6 BH6

BJ9

BG5

BJ5 BG3 BF4 BD4 BA3 BE5 BF2 BB4 AY4 BA1 AP2 AU1 AT2 AT4 AV4 AU3 AR3 AN1 AP4 AL3

AJ1 AK4 AM4 AH2 AK2

2

U3E

SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63

CANTIGA GMCH SFF_FCBGA1363

1

BJ13

SB_BS_0

BK12

SB_BS_1

BK38

SB_BS_2

BE21

SB_RAS#

BH14

SB_CAS#

BK14

SB_WE#

DDR_B_DM0

AP52

SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7

SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6

SB_DQS_7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7

SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8

SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14

DDR SYSTEM MEMORY B

AY54 BJ49 BJ43 BH12 BD2 AY2 AJ3

AR53 BA53 BH50 BK42 BH8 BB2 AV2 AM2 AT54 BB54 BJ51 BH42 BK8 BC3 AW3 AN3

BJ15 BJ33 BH24 BA17 BF36 BH36 BF34 BK34 BJ37 BH40 BH16 BK36 BH38 BJ11 BL37

DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7

DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6

DDR_B_DQS7 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8

DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14

DDR_B_BS0 [15] DDR_B_BS1 [15] DDR_B_BS2 [15]

DDR_B_RAS# [15] DDR_B_CAS# [15] DDR_B_WE# [15]

DDR_B_DM[0..7] [15]

DDR_B_DQS[0..7] [15]

DDR_B_DQS#[0..7] [15]

DDR_B_MA[0..14] [15]

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/04/20 2010/04/30

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

Cantiga(2/6)-DDR2 A/B CH

LS-5588

1

0.3

9 35Wednesday, July 01, 2009

0.3

5

D D

R68 75_0402_5%R68 75_0402_5%

1 2

R69 75_0402_5%R69 75_0402_5%

C C

1 2

R70 75_0402_5%R70 75_0402_5%

1 2

Tie to GND. 9/28

B B

4

U3C

D38

L_BKLT_CTRL

C37

L_BKLT_EN

K38

L_CTRL_CLK

L37

L_CTRL_DATA

J37

L_DDC_CLK

L35

L_DDC_DATA

B36

L_VDD_EN

F50

LVDS_IBG

H46

LVDS_VBG

P44

LVDS_VREFH

K46

LVDS_VREFL

D46

LVDSA_CLK#

B46

LVDSA_CLK

D44

LVDSB_CLK#

B44

LVDSB_CLK

G45

LVDSA_DATA#_0

F46

LVDSA_DATA#_1

G41

LVDSA_DATA#_2

C45

LVDSA_DATA#_3

F44

LVDSA_DATA_0

G47

LVDSA_DATA_1

F40

LVDSA_DATA_2

A45

LVDSA_DATA_3

B40

LVDSB_DATA#_0

A41

LVDSB_DATA#_1

F42

LVDSB_DATA#_2

D48

LVDSB_DATA#_3

D40

LVDSB_DATA_0

C41

LVDSB_DATA_1

G43

LVDSB_DATA_2

B48

LVDSB_DATA_3

J27

TVA_DAC

E27

TVB_DAC

G27

TVC_DAC

F26

TVA_RTN

B34

TV_DCONSEL_0

D34

TV_DCONSEL_1

J29

CRT_BLUE

G29

CRT_GREEN

F30

CRT_RED

E29

CRT_IRTN

D36

CRT_DDC_CLK

C35

CRT_DDC_DATA

J33

CRT_HSYNC

D32

CRT_TVO_IREF

G31

CRT_VSYNC

CANTIGA GMCH SFF_FCBGA1363

3

PEGCOMP trace width and spacing is 20/25 mils.

PEGCOMP

U45

PEG_COMPI

PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6 PEG_RX#_7 PEG_RX#_8 PEG_RX#_9

PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8

PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15

PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8

PEG_TX#_9 PEG_TX#_10 PEG_TX#_11 PEG_TX#_12 PEG_TX#_13 PEG_TX#_14 PEG_TX#_15

PEG_TX_0 PEG_TX_1 PEG_TX_2 PEG_TX_3 PEG_TX_4 PEG_TX_5 PEG_TX_6 PEG_TX_7 PEG_TX_8

PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15

T44

D52 G49 K54 H50 M52 N49 P54 V46 Y50 V52 W49 AB54 AD46 AC55 AE49 AF54

E51 F48 J55 J49 M54 M50 P52 U47 AA49 V54 V50 AB52 AC47 AC53 AD50 AF52

L47 F52 P46 H54 L55 T46 R53 U49 T54 Y46 AB46 W53 Y54 AC49 AF46 AD54

J47 F54 N47 H52 L53 R47 R55 T50 T52 W47 AA47 W55 Y52 AB50 AE47 AD52

PEG_COMPO

LVDS

PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15

TV

PCI-EXPRESS GRAPHICS

VGA

R64 49.9_0402_1%R64 49.9_0402_1%

PCIE_MTX_GRX_N0 PCIE_MTX_GRX_N1 PCIE_MTX_GRX_N2 PCIE_MTX_GRX_N3 PCIE_MTX_GRX_N4 PCIE_MTX_GRX_N5 PCIE_MTX_GRX_N6 PCIE_MTX_GRX_N7 PCIE_MTX_GRX_N8 PCIE_MTX_GRX_N9 PCIE_MTX_GRX_N10 PCIE_MTX_GRX_N11 PCIE_MTX_GRX_N12 PCIE_MTX_GRX_N13 PCIE_MTX_GRX_N14 PCIE_MTX_GRX_N15

PCIE_MTX_GRX_P0 PCIE_MTX_GRX_P1 PCIE_MTX_GRX_P2 PCIE_MTX_GRX_P3 PCIE_MTX_GRX_P4 PCIE_MTX_GRX_P5 PCIE_MTX_GRX_P6 PCIE_MTX_GRX_P7 PCIE_MTX_GRX_P8 PCIE_MTX_GRX_P9 PCIE_MTX_GRX_P10 PCIE_MTX_GRX_P11 PCIE_MTX_GRX_P12 PCIE_MTX_GRX_P13 PCIE_MTX_GRX_P14 PCIE_MTX_GRX_P15

1 2

C500 0.1U_0402_16V7KC500 0.1U_0402_16V7K

1 2

C501 0.1U_0402_16V7KC501 0.1U_0402_16V7K

1 2

C502 0.1U_0402_16V7KC502 0.1U_0402_16V7K

1 2

C503 0.1U_0402_16V7KC503 0.1U_0402_16V7K

1 2

C504 0.1U_0402_16V7KC504 0.1U_0402_16V7K

1 2

C505 0.1U_0402_16V7KC505 0.1U_0402_16V7K

1 2

C506 0.1U_0402_16V7KC506 0.1U_0402_16V7K

1 2

C507 0.1U_0402_16V7KC507 0.1U_0402_16V7K

1 2

C508 0.1U_0402_16V7KC508 0.1U_0402_16V7K

1 2

C509 0.1U_0402_16V7KC509 0.1U_0402_16V7K

1 2

C510 0.1U_0402_16V7KC510 0.1U_0402_16V7K

1 2

C511 0.1U_0402_16V7KC511 0.1U_0402_16V7K

1 2

C512 0.1U_0402_16V7KC512 0.1U_0402_16V7K

1 2

C513 0.1U_0402_16V7KC513 0.1U_0402_16V7K

1 2

C514 0.1U_0402_16V7KC514 0.1U_0402_16V7K

1 2

C515 0.1U_0402_16V7KC515 0.1U_0402_16V7K

1 2

C516 0.1U_0402_16V7KC516 0.1U_0402_16V7K

1 2

C517 0.1U_0402_16V7KC517 0.1U_0402_16V7K

1 2

C518 0.1U_0402_16V7KC518 0.1U_0402_16V7K

1 2

C519 0.1U_0402_16V7KC519 0.1U_0402_16V7K

1 2

C520 0.1U_0402_16V7KC520 0.1U_0402_16V7K

1 2

C521 0.1U_0402_16V7KC521 0.1U_0402_16V7K

1 2

C522 0.1U_0402_16V7KC522 0.1U_0402_16V7K

1 2

C523 0.1U_0402_16V7KC523 0.1U_0402_16V7K

1 2

C524 0.1U_0402_16V7KC524 0.1U_0402_16V7K

1 2

C525 0.1U_0402_16V7KC525 0.1U_0402_16V7K

1 2

C526 0.1U_0402_16V7KC526 0.1U_0402_16V7K

1 2

C527 0.1U_0402_16V7KC527 0.1U_0402_16V7K

1 2

C528 0.1U_0402_16V7KC528 0.1U_0402_16V7K

1 2

C529 0.1U_0402_16V7KC529 0.1U_0402_16V7K

1 2

C530 0.1U_0402_16V7KC530 0.1U_0402_16V7K

1 2

C531 0.1U_0402_16V7KC531 0.1U_0402_16V7K

1 2

+VCC_PEG

PCIE_GTX_C_MRX_N0 [17] PCIE_GTX_C_MRX_N1 [17] PCIE_GTX_C_MRX_N2 [17] PCIE_GTX_C_MRX_N3 [17] PCIE_GTX_C_MRX_N4 [17] PCIE_GTX_C_MRX_N5 [17] PCIE_GTX_C_MRX_N6 [17] PCIE_GTX_C_MRX_N7 [17] PCIE_GTX_C_MRX_N8 [17] PCIE_GTX_C_MRX_N9 [17] PCIE_GTX_C_MRX_N10 [17] PCIE_GTX_C_MRX_N11 [17] PCIE_GTX_C_MRX_N12 [17] PCIE_GTX_C_MRX_N13 [17] PCIE_GTX_C_MRX_N14 [17] PCIE_GTX_C_MRX_N15 [17]

PCIE_GTX_C_MRX_P0 [17] PCIE_GTX_C_MRX_P1 [17] PCIE_GTX_C_MRX_P2 [17] PCIE_GTX_C_MRX_P3 [17] PCIE_GTX_C_MRX_P4 [17] PCIE_GTX_C_MRX_P5 [17] PCIE_GTX_C_MRX_P6 [17] PCIE_GTX_C_MRX_P7 [17] PCIE_GTX_C_MRX_P8 [17] PCIE_GTX_C_MRX_P9 [17] PCIE_GTX_C_MRX_P10 [17] PCIE_GTX_C_MRX_P11 [17] PCIE_GTX_C_MRX_P12 [17] PCIE_GTX_C_MRX_P13 [17] PCIE_GTX_C_MRX_P14 [17] PCIE_GTX_C_MRX_P15 [17]

2

PCIE_MTX_C_GRX_N0 [17] PCIE_MTX_C_GRX_N1 [17] PCIE_MTX_C_GRX_N2 [17] PCIE_MTX_C_GRX_N3 [17] PCIE_MTX_C_GRX_N4 [17] PCIE_MTX_C_GRX_N5 [17] PCIE_MTX_C_GRX_N6 [17] PCIE_MTX_C_GRX_N7 [17] PCIE_MTX_C_GRX_N8 [17] PCIE_MTX_C_GRX_N9 [17] PCIE_MTX_C_GRX_N10 [17] PCIE_MTX_C_GRX_N11 [17] PCIE_MTX_C_GRX_N12 [17] PCIE_MTX_C_GRX_N13 [17] PCIE_MTX_C_GRX_N14 [17] PCIE_MTX_C_GRX_N15 [17]

PCIE_MTX_C_GRX_P0 [17] PCIE_MTX_C_GRX_P1 [17] PCIE_MTX_C_GRX_P2 [17] PCIE_MTX_C_GRX_P3 [17] PCIE_MTX_C_GRX_P4 [17] PCIE_MTX_C_GRX_P5 [17] PCIE_MTX_C_GRX_P6 [17] PCIE_MTX_C_GRX_P7 [17] PCIE_MTX_C_GRX_P8 [17] PCIE_MTX_C_GRX_P9 [17] PCIE_MTX_C_GRX_P10 [17] PCIE_MTX_C_GRX_P11 [17] PCIE_MTX_C_GRX_P12 [17] PCIE_MTX_C_GRX_P13 [17] PCIE_MTX_C_GRX_P14 [17] PCIE_MTX_C_GRX_P15 [17]

Strap Pin Table

CFG[2:0] FSB Freq select

CFG[4:3] Reserved

CFG5 (DMI select)

CFG6

CFG7 (Intel Management Engine Crypto strap)

CFG8

CFG9 (PCIE Graphics Lane Reversal)

CFG10 (PCIE Lookback enable)

CFG11 CFG[13:12] (XOR/ALLZ)

CFG16 (FSB Dynamic ODT)

CFG19 (DMI Lane Reversal)

CFG20 (PCIE/SDVO concurrent)

000 = FSB 1066MHz 010 = FSB 800MHz 011 = FSB 667MHz Others = Reserved

0 = DMI x 2 1 = DMI x 4 0 = The iTPM Host Interface is enable

1 = The iTPM Host Interface is disable 0 =(TLS)chiper suite with no confidentiality 1 =(TLS)chiper suite with confidentiality

Reserved

0 = Reverse Lane,15->0, 14->1 1 = Normal Operation,Lane Number in order

0 = Enable 1 = Disable Reserved 00 = Reserved

01 = XOR Mode Enabled 10 = All Z Mode Enabled

ReservedCFG[15:14]

0 = Disabled 1 = Enabled

ReservedCFG[18:17]

0 = Normal Operation

(Lane number in Order)

1 = Reverse Lane

0 = Only PCIE or SDVO is operational. 1 = PCIE/SDVO are operating simu.

CFG5[8] CFG6[8] CFG7[8]

CFG9[8] CFG10[8] CFG12[8] CFG13[8] CFG16[8]

1

*

(Default)11 = Normal Operation

*

R72 2.21K_0402_1%@R72 2.21K_0402_1%@

1 2

R74 2.21K_0402_1%@R74 2.21K_0402_1%@

1 2

R75 2.21K_0402_1%@R75 2.21K_0402_1%@

1 2

R77 2.21K_0402_1%@R77 2.21K_0402_1%@

1 2

R78 2.21K_0402_1%@R78 2.21K_0402_1%@

1 2

R79 2.21K_0402_1%@R79 2.21K_0402_1%@

1 2

R80 2.21K_0402_1%@R80 2.21K_0402_1%@

1 2

R81 2.21K_0402_1%@R81 2.21K_0402_1%@

1 2

*

+3VS

R82 4.02K_0402_1%@ R82 4.02K_0402_1%@

CFG19[8] CFG20[8]

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/04/20 2010/04/30

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

Cantiga(3/6)-VGA/LVDS/TV

LS-5588

1 2

R83 4.02K_0402_1%@R83 4.02K_0402_1%@

1 2

1

0.3

10 35Wednesday, July 01, 2009

0.3

5

D D

install 0.1U & 10U for wavy issue. 7/29

change 0.1U to 22U for wavy issue. 5/20

R94 0_0603_5% R94 0_0603_5%

0.1U_0402_16V4Z

+VCCP

+1.05VM_PEGPLL

1

C125

2

1 2

R100 0_0603_5%

+1.5VS

C C

B B

+1.05VM_HPLL

+1.5VS_PEG_BG

C105

0.1U_0402_16V4Z

R97 0_0805_5% R97 0_0805_5%

1 2

1

+

2

C110

100U_D2_6.3VM

1 2

1

C126

2

0.1U_0402_16V4Z

For disable internal graphics.

1

+1.05VM_PEGPLL

2

10U_0805_6.3V6M

1

2

C111

+1.05VM_A_SM_CK

For disable internal graphics.

+1.05VM_A_SM

4.7U_0805_10V4Z

C112

10U_0805_6.3V6M

C119

+1.05VM_HPLL +1.05VM_MPLL

1U_0603_10V4Z

1

2

C113

0.1U_0402_16V4Z

1

C120

2

1

2

1

2

4

U3H

J31

VCCA_CRT_DAC

L31

VCCA_DAC_BG

M33

VSSA_DAC_BG

J45

VCCA_DPLLA

L49

VCCA_DPLLB

AF10

VCCA_HPLL

AE1

VCCA_MPLL

U43

VCCA_LVDS1

U41

VCCA_LVDS2

V44

VSSA_LVDS

AJ43

VCCA_PEG_BG

AG43

VCCA_PEG_PLL

AW24

VCCA_SM_1

AU24

VCCA_SM_2

AW22

VCCA_SM_3

AU22

VCCA_SM_4

AU21

VCCA_SM_5

AW20

VCCA_SM_6

AU19

VCCA_SM_7

AW18

VCCA_SM_8

AU18

VCCA_SM_9

AW16

VCCA_SM_10

AU16

VCCA_SM_11

AT16

VCCA_SM_12

AR16

VCCA_SM_13

AU15

VCCA_SM_14

AT15

VCCA_SM_15

AR15

VCCA_SM_16

AW14

VCCA_SM_17

AT24

VCCA_SM_NCTF_1

AR24

VCCA_SM_NCTF_2

AT22

VCCA_SM_NCTF_3

AR22

VCCA_SM_NCTF_4

AT21

VCCA_SM_NCTF_5

AR21

VCCA_SM_NCTF_6

AT19

VCCA_SM_NCTF_7

AR19

VCCA_SM_NCTF_8

AT18

VCCA_SM_NCTF_9

AR18

VCCA_SM_NCTF_10

AU27

VCCA_SM_CK_4

AU28

VCCA_SM_CK_3

AU29

VCCA_SM_CK_2

AU31

VCCA_SM_CK_1

AT31

VCCA_SM_CK_NCTF_1

AR31

VCCA_SM_CK_NCTF_2

AT29

VCCA_SM_CK_NCTF_3

AR29

VCCA_SM_CK_NCTF_4

AT28

VCCA_SM_CK_NCTF_5

AR28

VCCA_SM_CK_NCTF_6

AT27

VCCA_SM_CK_NCTF_7

AR27

VCCA_SM_CK_NCTF_8

AH12

VCCD_HPLL

AE43

VCCD_PEG_PLL

M46

VCCD_LVDS_1

L45

VCCD_LVDS_2

CANTIGA GMCH SFF_FCBGA1363

CRTPLLA PEGA SM

A LVDS

POWER

LVDS

VTT_1 VTT_2 VTT_3 VTT_4 VTT_5 VTT_6 VTT_7 VTT_8

VTT_9 VTT_10 VTT_11 VTT_12 VTT_13

VTT

VCCA_TV_DAC

TVD TV/CRT

VCC_HDA

HDA

VCCD_QDAC

VCCD_TVDAC

VCC_AXF_1 VCC_AXF_2 VCC_AXF_3

AXF

VCC_SM_CK_1 VCC_SM_CK_2 VCC_SM_CK_3 VCC_SM_CK_4

SM CK

VCC_TX_LVDS

VCC_HV_1 VCC_HV_2

HV

VCC_PEG_1 VCC_PEG_2 VCC_PEG_3 VCC_PEG_4

PEG

VCC_DMI_1 VCC_DMI_2 VCC_DMI_3

DMI

VTTLF1 VTTLF2 VTTLF3

VTTLF

3

Change to 330u_R9, casue high limitation. 12/14

R13 T12 R11 T10 R9 T8 R7 T6 R5 T4 R3 T2 R1

K30

R92

R92 0_0402_5%

0_0402_5%

1 2

A31

N34

+1.5VS_QDAC

N32

M25

+V1.05VM_AXF

N24 M23

BK24

+1.5V_SM_CK

BL23 BJ23 BK22

T41 C33

A33

AB44

+VCC_PEG

Y44 AC43 AA43

AM44

+1.05VM_DMI

AN43 AL43

K14 Y12 P2

0.47U_0603_10V7K

1

C128

2

2.2U_0805_16V4Z

4.7U_0805_10V4Z

0.47U_0603_10V7K

4.7U_0805_10V4Z

1

C85

C87

2

C86

C85

For HDMI Disable.

+3VS_HV

0.1U_0402_16V4Z

1

2

C121

0.47U_0603_10V7K

1

C130

C129

2

+VCCP

1

+

2

C84

C88

330U_D2E_2.5VM_R9M

It can be "no-stuff".

+VCCP

+3VS

+VCCP

0.1U_0402_16V4Z

0.1U_0402_16V4Z C1258

C1258

1

2

2 1

For ESD

+1.05VM_HPLL

1

2

C103

0.1U_0402_16V4Z

+1.05VM_MPLL

1

C106

2

0.1U_0402_16V4Z

+1.05VM_PEGPLL

0.1U_0402_16V4Z

1

C122

2

+VCCP_D

+1.5VS_QDAC

C131

0.022U_0402_16V7K

1

C131

2

@

D1 CH751H-40_SC76

1 2

BLM18PG181SN1D_0603

1

2

C104

4.7U_0805_10V4Z

1 2

BLM18PG181SN1D_0603

1

C107

2

10U_0805_6.3V6M

1 2

BLM18PG121SN1D_0603

10U_0805_10V4Z

1

C123

2

R103 10_0402_5% R103 10_0402_5%

1 2

0.1U_0402_16V4Z

1

C132

C133

2

R93

R95

L1

BLM18PG181SN1D_0603

10U_0603_6.3V6M

+VCCP

R105

1 2

4.7U_0805_10V4Z

C117

+1.05VM_DMI

0.1U_0402_16V4Z

R104 0_0402_5% R104 0_0402_5%

1 2

+1.5VS

R90

+VCC_PEG

1

2

C124

+V1.05VM_AXF

10U_0805_10V4Z

1

C82

2

+1.5V_SM_CK

0.1U_0402_16V4Z

1

0_0603_5%

C97

1 2

10U_0805_6.3V6M

2

1

C99

2

10U_0805_6.3V6M

220U_D2_4VM_R15

1

+

C118

C116

2

R101 0_0603_5% R101 0_0603_5%

1 2

1

2

1U_0603_10V4Z

1

R85 0_0603_5%

1 2

1

C83

2

R89 0_0805_5%

1 2

10U_0805_6.3V6M

1

C98

2

R99 0_0805_5%R99 0_0805_5%

1 2

+VCCP

+3VS_HV

+VCCP

+1.5V

+VCCP

A A

Security Classification Compal Secret Data

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/04/20 2010/04/30

3

Deciphered Date

4.7UF issues probabiliy.

2

Compal Electronics, Inc.

Title

Cantiga(4/6)-PWR

Size Document Number Rev

Custom

LS-5588

Date: Sheet of

11 35Wednesday, July 01, 2009

1

0.3

5

4

3

U3G

2

1

Extnal Graphic: 1210.34mA integrated Graphic: 1930.4mA

U3F

D D

0.22U_0402_10V4Z

220U_D2_4VM_R15

10U_0805_6.3V6M

1

C141

+

2

C C

B B

A A

0.22U_0402_10V4Z

C142

C143

1

2

+VCCP

AT41

VCC_1

AR41

VCC_2

AN41

VCC_3

AJ41

VCC_4

AH41

VCC_5

AD41

VCC_6

AC41

VCC_7

Y41

VCC_8

W41

VCC_9

0.1U_0402_16V4Z

C144

1

2

AT40

VCC_10

AM40

VCC_11

AL40

C145

VCC_12

AJ40

VCC_13

AH40

VCC_14

AG40

VCC_15

AE40

VCC_16

AD40

VCC_17

AC40

VCC_18

AA40

VCC_19

Y40

VCC_20

AN35

VCC_21

AM35

VCC_22

AJ35

VCC_23

AH35

VCC_24

AD35

VCC_25

AC35

VCC_26

W35

VCC_27

AM34

VCC_28

AL34

VCC_29

AJ34

VCC_30

AH34

VCC_31

AG34

VCC_32

AE34

VCC_33

AD34

VCC_34

AC34

VCC_35

AA34

VCC_36

Y34

VCC_37

W34

VCC_38

AM32

VCC_39

AL32

VCC_40

AJ32

VCC_41

AH32

VCC_42

AE32

VCC_43

AD32

VCC_44

AA32

VCC_45

AM31

VCC_46

AL31

VCC_47

AJ31

VCC_48

AH31

VCC_49

AM29

VCC_50

AL29

VCC_51

AM28

VCC_52

AL28

VCC_53

AJ28

VCC_54

AM27

VCC_55

AL27

VCC_56

AM25

VCC_57

AL25

VCC_58

AJ25

VCC_59

AM24

VCC_60

N36

VCC_61

CANTIGA GMCH SFF_FCBGA1363

VCC CORE

POWER

VCC_NCTF_1 VCC_NCTF_2 VCC_NCTF_3 VCC_NCTF_4 VCC_NCTF_5 VCC_NCTF_6 VCC_NCTF_7 VCC_NCTF_8

VCC_NCTF_9 VCC_NCTF_10 VCC_NCTF_11 VCC_NCTF_12 VCC_NCTF_13 VCC_NCTF_14 VCC_NCTF_15 VCC_NCTF_16 VCC_NCTF_17 VCC_NCTF_18 VCC_NCTF_19 VCC_NCTF_20 VCC_NCTF_21 VCC_NCTF_22 VCC_NCTF_23 VCC_NCTF_24 VCC_NCTF_25 VCC_NCTF_26 VCC_NCTF_27 VCC_NCTF_28 VCC_NCTF_29 VCC_NCTF_30 VCC_NCTF_31

VCC NCTF

VCC_NCTF_32 VCC_NCTF_33 VCC_NCTF_34 VCC_NCTF_35 VCC_NCTF_36 VCC_NCTF_37 VCC_NCTF_38

AT38 AR38 AN38 AM38 AL38 AG38 AE38 AA38 Y38 W38 U38 T38 R38 AT37 AR37 AN37 AM37 AL37 AJ37 AH37 AG37 AE37 AD37 AC37 AA37 Y37 W37 U37 T37 R37 AT35 AR35 U35 AT34 AR34 U34 T34 R34

+VCCP

+1.5V

330U_D2E_2.5VM_R9

10U_0805_6.3V6M

1

C137

C138

1

+

2

6326.84mA

For disable internal graphics VCC_AXG to GND.

10U_0805_6.3V6M

0.01U_0402_16V7K

C139

1

2

T43PAD T43PAD T44PAD T44PAD

BB36

VCC_SM_1

BE35

VCC_SM_2

AW34

VCC_SM_3

AW32

VCC_SM_4

BK30

VCC_SM_5

BH30

VCC_SM_6

BF30

C140

2

1

BD30 BB30

AW30

BL29

BJ29 BG29 BE29 BC29 BA29 AY29 BK28 BH28 BF28 BD28 BB28 BL27

BJ27 BG27 BE27 BC27 BA27 AY27

AW26

BF24 BL19 BB16

AG31 AE31 AD31 AC31 AA31

AH29 AG29 AE29 AD29 AC29 AA29

AH28 AG28 AE28 AA28 AH27 AG27 AE27 AD27 AC27 AA27

AH25 AD25 AC25

AJ24 AH24 AG24 AE24 AD24 AC24 AA24

AM22

AL22

AJ22 AH22 AG22 AE22 AD22 AC22 AA22

AM21

AL21

AJ21 AH21 AD21 AC21 AA21

AM16

AL16

AG13 AE13

W32

Y31

W31

Y29

W29

Y27

W27

W25

Y24

W24

Y21

W21

VCC_SM_7 VCC_SM_8 VCC_SM_9 VCC_SM_10 VCC_SM_11 VCC_SM_12 VCC_SM_13 VCC_SM_14 VCC_SM_15 VCC_SM_16 VCC_SM_17 VCC_SM_18 VCC_SM_19 VCC_SM_20 VCC_SM_21 VCC_SM_22 VCC_SM_23 VCC_SM_24 VCC_SM_25 VCC_SM_26 VCC_SM_27 VCC_SM_28 VCC_SM_29 VCC_SM_30 VCC_SM_31 VCC_SM_32 VCC_SM_33

VCC_AXG_1 VCC_AXG_2 VCC_AXG_3 VCC_AXG_4 VCC_AXG_5 VCC_AXG_6 VCC_AXG_7 VCC_AXG_8 VCC_AXG_9 VCC_AXG_10 VCC_AXG_11 VCC_AXG_12 VCC_AXG_13 VCC_AXG_14 VCC_AXG_15 VCC_AXG_16 VCC_AXG_17 VCC_AXG_18 VCC_AXG_19 VCC_AXG_20 VCC_AXG_21 VCC_AXG_22 VCC_AXG_23 VCC_AXG_24 VCC_AXG_25 VCC_AXG_26 VCC_AXG_27 VCC_AXG_28 VCC_AXG_29 VCC_AXG_30 VCC_AXG_31 VCC_AXG_32 VCC_AXG_33 VCC_AXG_34 VCC_AXG_35 VCC_AXG_36 VCC_AXG_37 VCC_AXG_38 VCC_AXG_39 VCC_AXG_40 VCC_AXG_41 VCC_AXG_42 VCC_AXG_43 VCC_AXG_44 VCC_AXG_45 VCC_AXG_46 VCC_AXG_47 VCC_AXG_48 VCC_AXG_49 VCC_AXG_50 VCC_AXG_51 VCC_AXG_52 VCC_AXG_53 VCC_AXG_54 VCC_AXG_55 VCC_AXG_56 VCC_AXG_57 VCC_AXG_58 VCC_AXG_59 VCC_AXG_60 VCC_AXG_61

VCC_AXG_SENSE VSS_AXG_SENSE

VCC_AXG_NCTF_1 VCC_AXG_NCTF_2 VCC_AXG_NCTF_3 VCC_AXG_NCTF_4 VCC_AXG_NCTF_5 VCC_AXG_NCTF_6 VCC_AXG_NCTF_7 VCC_AXG_NCTF_8

VCC_AXG_NCTF_9 VCC_AXG_NCTF_10 VCC_AXG_NCTF_11 VCC_AXG_NCTF_12 VCC_AXG_NCTF_13 VCC_AXG_NCTF_14 VCC_AXG_NCTF_15 VCC_AXG_NCTF_16 VCC_AXG_NCTF_17 VCC_AXG_NCTF_18 VCC_AXG_NCTF_19 VCC_AXG_NCTF_20 VCC_AXG_NCTF_21 VCC_AXG_NCTF_22 VCC_AXG_NCTF_23

POWER

VCC_AXG_NCTF_24 VCC_AXG_NCTF_25 VCC_AXG_NCTF_26 VCC_AXG_NCTF_27 VCC_AXG_NCTF_28 VCC_AXG_NCTF_29 VCC_AXG_NCTF_30 VCC_AXG_NCTF_31

VCC SMVCC GFX

VCC_AXG_NCTF_32 VCC_AXG_NCTF_33 VCC_AXG_NCTF_34 VCC_AXG_NCTF_35 VCC_AXG_NCTF_36 VCC_AXG_NCTF_37 VCC_AXG_NCTF_38 VCC_AXG_NCTF_39

VCC GFX NCTF

VCC_AXG_NCTF_40 VCC_AXG_NCTF_41 VCC_AXG_NCTF_42 VCC_AXG_NCTF_43 VCC_AXG_NCTF_44

VCC GFX

VCC_AXG_62 VCC_AXG_63 VCC_AXG_64 VCC_AXG_65 VCC_AXG_66 VCC_AXG_67 VCC_AXG_68 VCC_AXG_69 VCC_AXG_70 VCC_AXG_71 VCC_AXG_72 VCC_AXG_73 VCC_AXG_74 VCC_AXG_75 VCC_AXG_76 VCC_AXG_77 VCC_AXG_78 VCC_AXG_79 VCC_AXG_80

VCC_SM_LF1 VCC_SM_LF2 VCC_SM_LF3 VCC_SM_LF4 VCC_SM_LF5 VCC_SM_LF6 VCC_SM_LF7

VCC SM LF

3000mA

T32 U31 T31 R31 U29 T29 R29 U28 U27 T27 R27 U25 T25 R25 U24 U22 T22 R22 U21 T21 R21 AM19 AL19 AH19 AG19 AE19 AD19 AC19 W19 U19 AM18 AL18 AJ18 AH18 AG18 AE18 AD18 AC18 AA18 Y18 W18 U18 T18 R18

AJ16 AH16 AD16 AC16 AA16 U16 T16 R16 AM15 AL15 AJ15 AH15 AG15 AE15 AA15 Y15 W15 U15 T15

AU45 BF52 BB38 BA19 BE9 AU9 AL9

For disable internal graphics VCC_AXG_NCTFto GND.

VCCSM_LF1 VCCSM_LF2 VCCSM_LF3 VCCSM_LF4 VCCSM_LF5 VCCSM_LF6 VCCSM_LF7

C151 0.22U_0603_10V7K C151 0.22U_0603_10V7K

1

C156 0.1U_0402_16V4Z C156 0.1U_0402_16V4Z

1

2

1

C157 0.1U_0402_16V4Z C157 0.1U_0402_16V4Z

1

2

C153 0.47U_0402_6.3V6KC153 0.47U_0402_6.3V6K

C155 1U_0603_10V4Z C155 1U_0603_10V4Z

C154 1U_0603_10V4Z C154 1U_0603_10V4Z

C152 0.22U_0603_10V7K C152 0.22U_0603_10V7K

1

2

5

CANTIGA GMCH SFF_FCBGA1363

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/04/20 2010/04/30

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

Cantiga(5/6)-PWR/GND

LS-5588

1

0.3

12 35Wednesday, July 01, 2009

0.3

5

U3I

BA55

VSS_1

AU55

VSS_2

AN55

VSS_3

AJ55

VSS_4

AE55

VSS_5

AA55

VSS_6

U55

VSS_7

N55

VSS_8

BD54

VSS_9

BG53

VSS_10

AJ53

VSS_11

AE53

D D

C C

B B

A A

VSS_12

AA53

VSS_13

U53

VSS_14

N53

VSS_15

J53

VSS_16

G53

VSS_17

E53

VSS_18

K52

VSS_19

BG51

VSS_20

BA51

VSS_21

AW51

VSS_22

AU51

VSS_23

AR51

VSS_24

AN51

VSS_25

AL51

VSS_26

AJ51

VSS_27

AG51

VSS_28

AE51

VSS_29

AC51

VSS_30

AA51

VSS_31

W51

VSS_32

U51

VSS_33

R51

VSS_34

N51

VSS_35

L51

VSS_36

J51

VSS_37

G51

VSS_38

C51

VSS_39

BK50

VSS_40

AM50

VSS_41

K50

VSS_42

BG49

VSS_43

E49

VSS_44

C49

VSS_45

BD48

VSS_46

BB48

VSS_47

AY48

VSS_48

AV48

VSS_49

AT48

VSS_50

AP48

VSS_51

AM48

VSS_52

AK48

VSS_53

AH48

VSS_54

AF48

VSS_55

AD48

VSS_56

AB48

VSS_57

Y48

VSS_58

V48

VSS_59

T48

VSS_60

P48

VSS_61

M48

VSS_62

K48

VSS_63

H48

VSS_64

BL47

VSS_65

BG47

VSS_66

E47

VSS_67

C47

VSS_68

A47

VSS_69

BD46

VSS_70

AY46

VSS_71

AM46

VSS_72

AK46

VSS_73

AH46

VSS_74

BG45

VSS_75

AE45

VSS_76

AC45

VSS_77

AA45

VSS_78

W45

VSS_79

R45

VSS_80

N45

VSS_81

E45

VSS_82

BD44

VSS_83

BB44

VSS_84

AV44

VSS_85

AK44

VSS_86

AH44

VSS_87

AF44

VSS_88

AD44

VSS_89

K44

VSS_90

H44

VSS_91

BL43

VSS_92

BG43

VSS_93

AY43

VSS_94

AR43

VSS_95

W43

VSS_96

R43

VSS_97

M43

VSS_98

E43

VSS_99

CANTIGA GMCH SFF_FCBGA1363

VSS

VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198

C43 A43 BD42 H42 BG41 AY41 AU41 AM41 AL41 AG41 AE41 AA41 R41 M41 E41 BD40 AU40 AR40 AN40 W40 U40 T40 R40 K40 H40 BL39 BG39 BA39 E39 C39 A39 BD38 AU38 H38 BG37 AU37 M37 E37 BD36 AW36 H36 BL35 BG35 AY35 AU35 AL35 AG35 AE35 AA35 Y35 M35 E35 A35 BD34 AU34 AN34 H34 BL33 BG33 AY33 E33 BD32 AU32 AN32 AG32 AC32 Y32 H32 B32 BJ31 BG31 AY31 AN31 M31 E31 N30 H30 AN29 AJ29 M29 A29 AW28 AN28 AD28 AC28 Y28 W28 H28 F28 AN27 AJ27 M27 BF26 BD26 N26 H26 BJ25 AY25 AU25

4

3

U3J

AN25

VSS_199

AG25

VSS_200

AE25

VSS_201

AA25

VSS_202

Y25

VSS_203

E25

VSS_204

A25

VSS_205

BD24

VSS_206

AN24

VSS_207

AL24

VSS_208

H24

VSS_209

BG23

VSS_210

AY23

VSS_211

E23

VSS_212

BD22

VSS_213

BB22

VSS_214

AN22

VSS_215

Y22

VSS_216

W22

VSS_217

H22

VSS_218

BL21

VSS_219

BG21

VSS_220

AY21

VSS_221

AN21

VSS_222

AG21

VSS_223

AE21

VSS_224

M21

VSS_225

E21

VSS_226

A21

VSS_227

BD20

VSS_228

H20

VSS_229

BG19

AY19

BD18

BL17

BG17

AY17

BD16 AN16 AG16 AE16

BG15

AY15 AN15 AD15 AC15

BD14

BL13 BG13

AY13 AU13 AR13

AJ13 AC13 AA13

BD12 AV12 AP12 AM12 AK12 AB12

BG11 AG11

BD10

AY10 AP10

M19

E19 N18

H18

M17

E17 A17

Y16

W16

N16 H16

R15

M15

E15 H14

W13

U13

M13

E13 A13

V12 P12 H12

E11

H10 BL9

BG9

E9

A9 BD8 BB8

AY8

AV8

AT8

AP8

VSS

VSS_230 VSS_231 VSS_232 VSS_233 VSS_234 VSS_235 VSS_236 VSS_237 VSS_238 VSS_239 VSS_240 VSS_241 VSS_242 VSS_243 VSS_244 VSS_245 VSS_246 VSS_247 VSS_248 VSS_249 VSS_250 VSS_251 VSS_252 VSS_253 VSS_254 VSS_255 VSS_256 VSS_257 VSS_258 VSS_259 VSS_260 VSS_261 VSS_262 VSS_263 VSS_264 VSS_265 VSS_266 VSS_267 VSS_268 VSS_269 VSS_270 VSS_271 VSS_272 VSS_273 VSS_274 VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286 VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296 VSS_297 VSS_298 VSS_299

CANTIGA GMCH SFF_FCBGA1363

VSS NCTF

VSS SCB

VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305 VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313 VSS_314 VSS_315 VSS_316 VSS_317 VSS_318 VSS_319 VSS_320 VSS_321 VSS_322 VSS_323 VSS_324 VSS_325 VSS_326 VSS_327 VSS_328 VSS_329 VSS_330 VSS_331 VSS_332 VSS_333 VSS_334 VSS_335 VSS_336 VSS_337 VSS_338 VSS_339 VSS_340 VSS_341 VSS_342 VSS_343 VSS_344 VSS_345 VSS_346 VSS_347 VSS_348 VSS_349 VSS_350 VSS_351 VSS_352 VSS_353 VSS_354 VSS_355 VSS_356 VSS_357 VSS_358

VSS_359 VSS_360 VSS_361 VSS_362

VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8

VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 VSS_NCTF_15 VSS_NCTF_16 VSS_NCTF_17 VSS_NCTF_18 VSS_NCTF_19 VSS_NCTF_20 VSS_NCTF_21 VSS_NCTF_22 VSS_NCTF_23

VSS_SCB_1 VSS_SCB_2 VSS_SCB_3 VSS_SCB_4 VSS_SCB_5 VSS_SCB_6 VSS_SCB_7

2

AM8 AK8 AH8 AF8 AD8 AB8 Y8 V8 P8 M8 K8 H8 BJ7 E7 BF6 BC5 BA5 AW5 AU5 AR5 AN5 AL5 AJ5 AG5 AE5 AC5 AA5 W5 U5 N5 L5 J5 G5 C5 BH4 BE3 U3 E3 BC1 AW1 AR1 AL1 AG1 AC1 W1 N1 J1 AU43 BB42 AW38 BA35 L29 N28 N22 N20 N14 AL13 B10 AN13

N42 N40 N38 M39

AJ38 AH38 AD38 AC38 T35 R35 AT32 AR32 U32 R32 T28 R28 AT25 AR25 T24 R24 AN19 AJ19 AA19 Y19 T19 R19 AN18

BL55 BL1 A55 D1 B55 B2 A4

1

5

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/04/20 2010/04/30

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

Cantiga(6/6)-PWR/GND

LS-5588

1

0.3

13 35Wednesday, July 01, 2009

0.3

5

DDR_A_DQS#[0..7][9]

DDR_A_D[0..63][9]

DDR_A_DM[0..7][9]

DDR_A_DQS[0..7][9]

DDR_A_MA[0..14][9]

D D

Layout Note:

C C

B B

A A

Place near JP4

+1.5V

10U_0805_6.3V6M

1

C602

2

Layout Note: Place near JP4.203 & JP4.204

1

C604

C603

2

+0.75VS

1U_0603_10V4Z

2

C614

1

5

10U_0805_6.3V6M

1

C605

2

1U_0603_10V4Z

2

C615

1

+V_DDR3_DIMM_REF[15]

0.1U_0402_16V4Z

Layout Note: Place these 4 Caps near Command and Control signals of DIMMA

0.1U_0402_16V4Z

10U_0805_6.3V6M

1U_0603_10V4Z

C616

1

C607

C606

2

10U_0805_6.3V6M

1

2

C618

C617

2

1

C609

C608

1

2

+V_DDR3_DIMM_REF

C600

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z C610

C610

1

2

4

+1.5V

12

R431

R431 100_0402_1%

100_0402_1%

+V_DDR3_DIMM_REF

12

R432

R432 100_0402_1%

100_0402_1%

DDR_CKE0_DIMMA[8]

DDR_A_BS2[9]

0.1U_0402_16V4Z

1

C611

1

+

C601

C601 470U_D2_2.5VM_R15

470U_D2_2.5VM_R15

@

2

4

M_CLK_DDR0[8] M_CLK_DDR#0[8]

DDR_A_BS0[9]

DDR_A_WE#[9]

DDR_CS1_DIMMA#[8]

+3VS

C619

2.2U_0603_6.3V4Z

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+V_DDR3_DIMM_REF

DDR_A_D0 DDR_A_D1

DDR_A_DM0 DDR_A_D2

DDR_A_D3 DDR_A_D8

DDR_A_D9 DDR_A_DQS#1

DDR_A_DQS1 DDR_A_D10

DDR_A_D11 DDR_A_D16

DDR_A_D17 DDR_A_DQS#2

DDR_A_DQS2 DDR_A_D18

DDR_A_D19 DDR_A_D24

DDR_A_D25 DDR_A_DM3 DDR_A_D26

DDR_A_D27

DDR_CKE0_DIMMA

DDR_A_BS2 DDR_A_MA12

DDR_A_MA9 DDR_A_MA8

DDR_A_MA5 DDR_A_MA3

DDR_A_MA1 M_CLK_DDR0

M_CLK_DDR#0 DDR_A_MA10

DDR_A_BS0 DDR_A_WE#

DDR_A_CAS# M_ODT0 DDR_A_MA13

DDR_CS1_DIMMA#

DDR_A_D32 DDR_A_D33

DDR_A_DQS#4 DDR_A_DQS4

DDR_A_D34 DDR_A_D35

DDR_A_D40 DDR_A_D41

DDR_A_DM5 DDR_A_D42

DDR_A_D43 DDR_A_D48

DDR_A_D49 DDR_A_DQS#6

DDR_A_DQS6 DDR_A_D50

DDR_A_D51 DDR_A_D56

DDR_A_D57 DDR_A_DM7 DDR_A_D58

DDR_A_D59

1 2

10K_0402_5%

1

2

C620

0.1U_0402_16V4Z

Issued Date

3

+1.5V +1.5V

JP3

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1 VSS49DQS#0

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1 DQS129RESET# VSS1131VSS12

33

DQ10

35

DQ11 VSS1337VSS14

39

DQ16

41

DQ17 VSS1543VSS16

45

DQS#2 DQS247VSS17

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25 VSS2261DQS#3

63

DM3 VSS2365VSS24

67

DQ26

69

DQ27 VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3 A12/BC#83A11

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1 VDD999VDD10

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

R434

R435

10K_0402_5%

12

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

FOX_AS0A626-U4SN-7F

FOX_AS0A626-U4SN-7F ME@

ME@

2009/04/20 2010/04/30

VSS3

DQS0

VSS6

VSS8 DQ12 DQ13

VSS10

DQ14 DQ15

DQ20 DQ21

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21

DQS3

DQ30 DQ31

CKE1 VDD2

VDD4

VDD6

VDD8

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30 VSS31

DQ38 DQ39

VSS33

DQ44 DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46 DQ47

VSS40

DQ52 DQ53

VSS42 VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62 DQ63

VSS52

EVENT#

Compal Secret Data

2 4

DQ4

6

DQ5

8 10 12 14 16

DQ6

18

DQ7

20 22 24 26 28

DM1

30 32 34 36 38 40 42 44 46

DM2

48 50 52 54 56 58 60 62 64 66 68 70 72

74 76 78

A15

80

A14

82 84 86

A7

88 90

A6

92

A4

94 96

A2

98

A0

100 102

CK1

104 106 108

BA1

110 112 114

S0#

116 118 120 122

NC2

124 126 128 130 132 134 136

DM4

138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170

DM6

172 174 176 178 180 182 184 186 188 190 192 194 196 198 200

SDA

202

SCL

204

VTT2

206

G2

Deciphered Date

DDR_A_D4 DDR_A_D5

DDR_A_DQS#0 DDR_A_DQS0

DDR_A_D6 DDR_A_D7

DDR_A_D12 DDR_A_D13

DDR_A_DM1 SM_DRAMRST#

DDR_A_D14 DDR_A_D15

DDR_A_D20 DDR_A_D21

DDR_A_DM2 DDR_A_D22

DDR_A_D23 DDR_A_D28

DDR_A_D29 DDR_A_DQS#3

DDR_A_DQS3 DDR_A_D30

DDR_A_D31

DDR_CKE1_DIMMA

DDR_A_MA14 DDR_A_MA11

DDR_A_MA7 DDR_A_MA6

DDR_A_MA4 DDR_A_MA2

DDR_A_MA0 M_CLK_DDR1

M_CLK_DDR#1 DDR_A_BS1

DDR_A_RAS# DDR_CS0_DIMMA#

M_ODT1

DDR_VREF_CA_DIMMA DDR_A_D36

DDR_A_D37 DDR_A_DM4 DDR_A_D38

DDR_A_D39 DDR_A_D44

DDR_A_D45 DDR_A_DQS#5

DDR_A_DQS5 DDR_A_D46

DDR_A_D47 DDR_A_D52

DDR_A_D53 DDR_A_DM6 DDR_A_D54

DDR_A_D55 DDR_A_D60

DDR_A_D61 DDR_A_DQS#7

DDR_A_DQS7 DDR_A_D62

DDR_A_D63 PM_EXTTS#0

CLK_SMBDATA CLK_SMBCLK

+0.75VS

2

SM_DRAMRST# [8,15]

DDR_CKE1_DIMMA [8]

M_CLK_DDR1 [8] M_CLK_DDR#1 [8]

DDR_A_BS1 [9] DDR_A_RAS# [9]

DDR_CS0_DIMMA# [8] M_ODT0 [8]DDR_A_CAS#[9]

+0.75VS

M_ODT1 [8]

R433

1 2

PM_EXTTS#0 [8] ICH_SMBDATA [15,16,24,26] ICH_SMBCLK [15,16,24,26]

0_0402_5%

+V_DDR3_DIMM_REF

0.1U_0402_16V4Z

2.2U_0805_16V4Z

1

C612

2

1

C613

2

1

DDR3 SO-DIMM A Standard 4.2mm

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

DDR3-SODIMM SLOT1

LS-5588

14 35Wednesday, July 01, 2009

1

0.3

5

DDR_B_DQS#[0..7][9]

DDR_B_D[0..63][9]

DDR_B_DM[0..7][9]

DDR_B_DQS[0..7][9]

DDR_B_MA[0..14][9]

D D

Layout Note: Place near JP5

+1.5V

10U_0805_6.3V6M

1

C622

C623

2

C C

Layout Note: Place near JP5.203 & JP5.204

+0.75VS

1U_0603_10V4Z

2

1

B B

A A

10U_0805_6.3V6M

1

C624

2

1U_0603_10V4Z

2

C632

C633

1

10U_0805_6.3V6M

1

C626

C625

2

10U_0805_6.3V6M

1U_0603_10V4Z

1

2

C635

C634

2

1

Layout Note: Place these 4 Caps near Command and Control signals of DIMMA

0.1U_0402_16V4Z

10U_0805_6.3V6M

1

2

C636

1

C627

2

0.1U_0402_16V4Z

C628

C629

1

2

4

+V_DDR3_DIMM_REF[14]

0.1U_0402_16V4Z

1

C631

C630

1

2

+

C621

C621 470U_D2_2.5VM_R15

470U_D2_2.5VM_R15

@

2

DDR_CKE2_DIMMB[8]

DDR_B_BS2[9]

DDR_CS3_DIMMB#[8]

M_CLK_DDR2[8] M_CLK_DDR#2[8]

DDR_B_BS0[9]

DDR_B_WE#[9] DDR_B_CAS#[9]

+3VS

0.1U_0402_16V4Z

+V_DDR3_DIMM_REF

C639

1

2

3

DDR_B_D0 DDR_B_D1

DDR_B_DM0 DDR_B_D2

DDR_B_D3 DDR_B_D8

DDR_B_D9 DDR_B_DQS#1

DDR_B_DQS1 DDR_B_D10

DDR_B_D11 DDR_B_D16

DDR_B_D17 DDR_B_DQS#2

DDR_B_DQS2 DDR_B_D18

DDR_B_D19 DDR_B_D24

DDR_B_D25 DDR_B_DM3 DDR_B_D26

DDR_B_D27

DDR_B_BS2 DDR_B_MA12

DDR_B_MA9 DDR_B_MA8

DDR_B_MA5 DDR_B_MA3

DDR_B_MA1 M_CLK_DDR2

M_CLK_DDR#2 DDR_B_MA10

DDR_B_BS0 DDR_B_WE#

DDR_B_CAS# DDR_B_MA13

DDR_CS3_DIMMB#

DDR_B_D32 DDR_B_D33

DDR_B_DQS#4 DDR_B_DQS4

DDR_B_D34 DDR_B_D35

DDR_B_D40 DDR_B_D41

DDR_B_DM5 DDR_B_D42

DDR_B_D43 DDR_B_D48

DDR_B_D49 DDR_B_DQS#6

DDR_B_DQS6 DDR_B_D50

DDR_B_D51 DDR_B_D56

DDR_B_D57 DDR_B_DM7 DDR_B_D58

DDR_B_D59

1 2

R437

R437 10K_0402_5%

10K_0402_5%

1 2

R438

R438 10K_0402_5%

10K_0402_5%

+1.5V +1.5V

JP4

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1 VSS49DQS#0

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1 DQS129RESET# VSS1131VSS12

33

DQ10

35

DQ11 VSS1337VSS14

39

DQ16

41

DQ17 VSS1543VSS16

45

DQS#2 DQS247VSS17

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25 VSS2261DQS#3

63

DM3 VSS2365VSS24

67

DQ26

69

DQ27 VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3 A12/BC#83A11

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1 VDD999VDD10

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

FOX_AS0A626-U4RN-7F

FOX_AS0A626-U4RN-7F ME@

ME@

VSS3

DQS0

VSS6

VSS8 DQ12 DQ13

VSS10

DM1

DQ14 DQ15

DQ20 DQ21

DM2

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21

DQS3

DQ30 DQ31

CKE1 VDD2

VDD4

VDD6

VDD8

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30

DM4

VSS31

DQ38 DQ39

VSS33

DQ44 DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46 DQ47

VSS40

DQ52 DQ53

VSS42

DM6

VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62 DQ63

VSS52

EVENT#

SDA

VTT2

2 4

DQ4

6

DQ5

8 10 12 14 16

DQ6

18

DQ7

20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

74 76 78

A15

80

A14

82 84 86

A7

88 90

A6

92

A4

94 96

A2

98

A0

100 102

CK1

104 106 108

BA1

110 112 114

S0#

116 118 120 122

NC2

124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202

SCL

204 206

G2

DDR_B_D4 DDR_B_D5

DDR_B_DQS#0 DDR_B_DQS0

DDR_B_D6 DDR_B_D7

DDR_B_D12 DDR_B_D13

DDR_B_DM1 SM_DRAMRST#

DDR_B_D14 DDR_B_D15

DDR_B_D20 DDR_B_D21

DDR_B_DM2 DDR_B_D22

DDR_B_D23 DDR_B_D28

DDR_B_D29 DDR_B_DQS#3

DDR_B_DQS3 DDR_B_D30

DDR_B_D31

DDR_CKE3_DIMMBDDR_CKE2_DIMMB

DDR_B_MA14 DDR_B_MA11

DDR_B_MA7 DDR_B_MA6

DDR_B_MA4 DDR_B_MA2

DDR_B_MA0 M_CLK_DDR3

M_CLK_DDR#3 DDR_B_BS1

DDR_B_RAS# DDR_CS2_DIMMB#

M_ODT2 M_ODT3

DDR_VREF_CA_DIMMB

DDR_B_D36 DDR_B_D37

DDR_B_DM4 DDR_B_D38

DDR_B_D39 DDR_B_D44

DDR_B_D45 DDR_B_DQS#5

DDR_B_DQS5 DDR_B_D46

DDR_B_D47 DDR_B_D52

DDR_B_D53 DDR_B_DM6 DDR_B_D54

DDR_B_D55 DDR_B_D60

DDR_B_D61 DDR_B_DQS#7

DDR_B_DQS7 DDR_B_D62

DDR_B_D63 PM_EXTTS#1

CLK_SMBDATA CLK_SMBCLK

+0.75VS

2

SM_DRAMRST# [8,14]

DDR_CKE3_DIMMB [8]

M_CLK_DDR3 [8] M_CLK_DDR#3 [8]

DDR_B_BS1 [9] DDR_B_RAS# [9]

DDR_CS2_DIMMB# [8]

+0.75VS

M_ODT2 [8] M_ODT3 [8]

R436 0_0402_5%R436 0_0402_5%

1 2

1

2

PM_EXTTS#1 [8] ICH_SMBDATA [14,16,24,26] ICH_SMBCLK [14,16,24,26]

C637

0.1U_0402_16V4Z

+V_DDR3_DIMM_REF

1

C638

2.2U_0805_16V4Z

2

1

DDR3 SO-DIMM B Reverse 4.0mm

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/04/20 2010/04/30

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

DDR3-SODIMM SLOT2

LS-5588

15 35Wednesday, July 01, 2009

1

0.3

5

PCI

CLKSEL1

FSLA

CLKSEL0

MHz

FSLC1FSLB

CLKSEL2

CPU

0 1000 2660 33.3

1

0

D D

FSA

CPU_BSEL0[5]

C C

CPU_BSEL1[5]

B B

FSC

CPU_BSEL2[5]

200

166

12

R130 2.2K_0402_5%

1 2

R134 0_0402_5%R134 0_0402_5%

FSB

1 2

R138

R138 0_0402_5%

0_0402_5%

9/20

12

R146 10K_0402_5%

1 2

R148 0_0402_5%R148 0_0402_5%

SRC

FSB

MHz

1066

1000

800

100

667

+VCCP

R123

56_0402_5%@

1 2

R131 1K_0402_5%

12

R135

1K_0402_5%@

+VCCP

R136

1K_0402_5%@

R137

1 2

1K_0402_5%

1 2

12

R141

0_0402_5%@

1 2

R147 1K_0402_5% R147 1K_0402_5%

12

R150

R150 0_0402_5%

0_0402_5%

MHz

33.30

33.3

MCH_CLKSEL1 [8]

MCH_CLKSEL2 [8]

Install. 11/06

14.31818MHZ_20P_1BX14318BE1A

CLK_XTAL_OUT

CLK_XTAL_IN

Y1

A A

C233

22P_0402_50V8J

12

2

C234

C234 22P_0402_50V8J

22P_0402_50V8J

1

5

+3VS

1 2

R153

R153 10K_0402_5%

10K_0402_5%

R156

@

10K_0402_5%

4

+3VS

R121 0_1206_5%

MCH_CLKSEL0 [8]

CLK_PCI_EC[26]

CLK_PCI_ICH[22]

CLK_48M_ICH[24] CLK_48M_CR[26]

CLK_14M_ICH[24]

+3VS +3VS

R154

10K_0402_5%

1 2

27_SELITP_EN

R157

@ R157

@

10K_0402_5%

1 2

4

3

+3VM_CK505

1 2

1

2

C216

10U_0805_10V4Z

CLKREQ#_B_R CLKREQG_WWAN#_R

CLK_PCI_EC PCI_CLK1 VGA_CLK_REQ#

CLK_PCI_ICH

CLK_48M_ICH

CLK_14M_ICH FSC

R155

R155 10K_0402_5%

10K_0402_5%

1 2

PCI2_TME

R158

@

10K_0402_5%

1 2

1

2

C218

C217

0.1U_0402_16V4Z

9/14

+1.05VM_CK505

1 2

1 2 1 2

1 2

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

2

C219

0.1U_0402_16V4Z

R126 475_0402_1%

R126 475_0402_1% R127 475_0402_1%

R127 475_0402_1%

R14233_0402_1%

R14533_0402_1%

Issued Date

2

C220

0.1U_0402_16V4Z

+3VM_CK505

+1.05VM_CK505

PCI2_TME

27_SEL ITP_EN

CLK_XTAL_IN CLK_XTAL_OUT

R14915_0402_1% R14915_0402_1% R17715_0402_1% R17715_0402_1%

R15133_0402_1%

3

1

2

C221

0.1U_0402_16V4Z

12 12

FSA

FSB

1

2

C222

0.1U_0402_16V4Z

R124 10K_0402_5% R124 10K_0402_5%

1 2

R132 10K_0402_5%

1 2

Modify PN directly, from SA00001YJ20(HP) to SA000020H10(General)

U4

6

VDDREF

12

VDDPCI

19

VDD48

23

VDD96_IO

27

VDDPLL3

55

VDDSRC

72

VDDCPU

31

VDDPLL3_IO

38

VDDSRC_IO

52

VDDSRC_IO

62

VDDSRC_IO

66

VDDCPU_IO

13

PCI

14

PCI2/TME

15

PCI3

16

PCI4/27_Select

17

PCI_F5/ITP_EN

5

X1

4

X2

20

USB_48MHz/FSLA

2

FSLB/TEST_MODE

7

FSLC/TEST_SEL/REF0

59

GNDSRC

18

GNDPCI

22

GND48

26

GND

30

GND

69

GNDCPU

34

GNDSRC

42

GNDSRC

3

GNDREF

ICS9LPRS387BKLFT MLF 72P

2009/04/20 2010/04/30

1 2

R122 0_1206_5%

CLKREQ#_B [8] CLKREQG_WWAN# [26] CLKREQ_WLAN# [26]

PCI_STOP#

CPU_STOP#

CPUT0_LPR_F

CPUC0_LPR_F

CPUT1_LPR_F

CPUC1_LPR_F

CPUT2_ITP_LPR/SRCT8_LPR

CPUC2_ITP_LPR/SRCC8_LPR

27MHz_NonSS/SRCT1_LPR/SE1

Compal Secret Data

SRCT7_LPR

SRCC7_LPR

SRCT6_LPR

SRCC6_LPR

SRCT10_LPR

SRCC10_LPR

SRCT11_LPR

SRCC11_LPR

SRCT9_LPR

SRCC9_LPR

SRCT4_LPR

SRCC4_LPR

SRCT3_LPR

SRCC3_LPR

SRCT2_LPR/SATAT_LPR

SRCC2_LPR/SATAC_LPR

SRCT0_LPR/DOTT_96_LPR

SRCC0_LPR/DOTC_96_LPR

27MHz_SS/SRCC1_LPR/SE2

CK_PWRGD/PD#

Deciphered Date

+3VS

SDATA

T_PAD

SCLK

CR7#

CR#6

CR10#

CR#11

CR#9

CR#4

CR#3

CR#A

REF1

+1.05VM_CK505+VCCP

NC

1

2

C223

10U_0805_10V4Z

11

10 9

54 53

71 70

68 67

65 64

63 61

60 58 57

56 49 50

51 46 48

47 43 44

45

41 39

40 37 35

36

32 33

24 25

28 29

1

21

8 73

2

1

2

C224

0.1U_0402_16V4Z

CLKREQ_WLAN#_R CLKSATAREQ#_R

CLKREQ#_B_R

CLKREQ_WLAN#_R

CLKREQG_WWAN#_R

CLKSATAREQ#_R

2

1

2

C225

0.1U_0402_16V4Z

R_PCIE_ICH R_PCIE_ICH#

1

2

C227

C226

10U_0805_10V4Z

ICH_SMBCLK [14,15,24,26] ICH_SMBDATA [14,15,24,26]

H_STP_PCI# [24] H_STP_CPU# [24]

CLK_CPU_BCLK [4] CLK_CPU_BCLK# [4]

CLK_MCH_BCLK [8] CLK_MCH_BCLK# [8]

CLK_MCH_3GPLL [8] CLK_MCH_3GPLL# [8]

CLK_PCIE_VGA [17] CLK_PCIE_VGA# [17]

CLK_PCIE_MCARD [26] CLK_PCIE_MCARD# [26]

CLK_PCIE_WAN [26] CLK_PCIE_WAN# [26]

CLK_PCIE_LAN [26] CLK_PCIE_LAN# [26]

CLK_PCIE_SATA [23] CLK_PCIE_SATA# [23]

27M_NSSC [18] 27M_SSC [18]

CK_PWRGD [24]

C228

0.1U_0402_16V4Z

R128 475_0402_1% R128 475_0402_1% R129 475_0402_1% R129 475_0402_1%

VGA_CLK_REQ# [18]

CLKREQA# [26]

RP28 0_0404_4P2R_5%RP28 0_0404_4P2R_5%

1 4 2 3

Title

Size Document Number Rev

Date: Sheet of

C212

C212 C213

C213 C214

C214

1

2

C229

Place close to U5

R125 10K_0402_5%

12 12

LS-5588

R125 10K_0402_5%

R133 10K_0402_5% R133 10K_0402_5%

Compal Electronics, Inc.

CLOCK GENERATOR

1

CLK_48M_ICH

12

5P_0402_50V8C@

CLK_14M_ICH

1 2

12P_0402_50V8J@

CLK_PCI_ICH

12

4.7P_0402_50V8C@

CLK_PCI_EC

12

4.7P_0402_50V8C@

1 2

CLKSATAREQ# [24]

1 2

CLK_PCIE_ICH [24] CLK_PCIE_ICH# [24]

1

+3VS

0.3

16 35Wednesday, July 01, 2009

0.3

5

PCIE_MTX_C_GRX_N[0..15][10] PCIE_MTX_C_GRX_P[0..15][10] PCIE_GTX_C_MRX_N[0..15][10] PCIE_GTX_C_MRX_P[0..15][10]

U64A

PLT_RST#[8,22,26]

1 2

@

PCIE_MTX_C_GRX_P0 PCIE_MTX_C_GRX_N0

PCIE_MTX_C_GRX_P1 PCIE_MTX_C_GRX_N1

PCIE_MTX_C_GRX_P2 PCIE_MTX_C_GRX_N2

PCIE_MTX_C_GRX_P3 PCIE_MTX_C_GRX_N3

PCIE_MTX_C_GRX_P4 PCIE_MTX_C_GRX_N4

PCIE_MTX_C_GRX_P5 PCIE_MTX_C_GRX_N5

PCIE_MTX_C_GRX_P6 PCIE_MTX_C_GRX_N6

PCIE_MTX_C_GRX_P7 PCIE_MTX_C_GRX_N7

PCIE_MTX_C_GRX_P8 PCIE_MTX_C_GRX_N8

PCIE_MTX_C_GRX_P9 PCIE_MTX_C_GRX_N9

PCIE_MTX_C_GRX_P10 PCIE_MTX_C_GRX_N10

PCIE_MTX_C_GRX_P11 PCIE_MTX_C_GRX_N11

PCIE_MTX_C_GRX_P12 PCIE_MTX_C_GRX_N12

PCIE_MTX_C_GRX_P13 PCIE_MTX_C_GRX_N13

PCIE_MTX_C_GRX_P14 PCIE_MTX_C_GRX_N14

PCIE_MTX_C_GRX_P15 PCIE_MTX_C_GRX_N15

CLK_PCIE_VGA CLK_PCIE_VGA#

For Future ASIC Pin N10 need pull down

T77

PLT_RST#

R347 10K_0402_5%

D D

C C

B B

CLK_PCIE_VGA[16] CLK_PCIE_VGA#[16]

A A

PAD

R892

1 2

0_0402_5%

AF30

PCIE_RX0P

AE31

PCIE_RX0N

AE29

PCIE_RX1P

AD28

PCIE_RX1N

AD30

PCIE_RX2P

AC31

PCIE_RX2N

AC29

PCIE_RX3P

AB28

PCIE_RX3N

AB30

PCIE_RX4P

AA31

PCIE_RX4N

AA29

PCIE_RX5P

Y28

PCIE_RX5N

Y30

PCIE_RX6P

W31

PCIE_RX6N

W29

PCIE_RX7P

V28

PCIE_RX7N

V30

PCIE_RX8P

U31

PCIE_RX8N

U29

PCIE_RX9P

T28

PCIE_RX9N

T30

PCIE_RX10P

R31

PCIE_RX10N

R29

PCIE_RX11P

P28

PCIE_RX11N

P30

PCIE_RX12P

N31

PCIE_RX12N

N29

PCIE_RX13P

M28

PCIE_RX13N

M30

PCIE_RX14P

L31

PCIE_RX14N

L29

PCIE_RX15P

K30

PCIE_RX15N

CLOCK

AK30

PCIE_REFCLKP

AK32

PCIE_REFCLKN

L9

NC#1

N9

NC#2

N10

NC_PWRGOOD

AL27

PERSTB

216-0728002 A11 M92-S2_FCBGA631

NOTE: Change part number directly, from SA00002ZM10 to SA000030O20 M92XT -> LP, 2009/05/20

5

PCIE_MTX_C_GRX_N[0..15]

PCIE_MTX_C_GRX_P[0..15]

PCIE_GTX_C_MRX_N[0..15]

PCIE_GTX_C_MRX_P[0..15]

PCIE_GTX_MRX_P0

AH30

PCIE_TX0P PCIE_TX0N

PCIE_TX1P PCIE_TX1N

PCIE_TX2P PCIE_TX2N

PCIE_TX3P PCIE_TX3N

PCI EXPRESS INTERFACE

PCIE_TX4P PCIE_TX4N

PCIE_TX5P PCIE_TX5N

PCIE_TX6P PCIE_TX6N

PCIE_TX7P PCIE_TX7N

PCIE_TX8P PCIE_TX8N

PCIE_TX9P PCIE_TX9N

PCIE_TX10P PCIE_TX10N

PCIE_TX11P PCIE_TX11N

PCIE_TX12P PCIE_TX12N

PCIE_TX13P PCIE_TX13N

PCIE_TX14P PCIE_TX14N

PCIE_TX15P PCIE_TX15N

CALIBRATION

PCIE_CALRP PCIE_CALRN

PCIE_GTX_MRX_N0

AG31

PCIE_GTX_MRX_P1

AG29

PCIE_GTX_MRX_N1

AF28

PCIE_GTX_MRX_P2

AF27

PCIE_GTX_MRX_N2

AF26

PCIE_GTX_MRX_P3

AD27

PCIE_GTX_MRX_N3

AD26

PCIE_GTX_MRX_P4

AC25 AB25

PCIE_GTX_MRX_P5

Y23

PCIE_GTX_MRX_N5

Y24

PCIE_GTX_MRX_P6

AB27

PCIE_GTX_MRX_N6

AB26

PCIE_GTX_MRX_P7 PCIE_GTX_C_MRX_P7

Y27

PCIE_GTX_MRX_N7

Y26

PCIE_GTX_MRX_P8

W24

PCIE_GTX_MRX_N8

W23

PCIE_GTX_MRX_P9

V27

PCIE_GTX_MRX_N9

U26

PCIE_GTX_MRX_P10

U24

PCIE_GTX_MRX_N10

U23

PCIE_GTX_MRX_P11

T26

PCIE_GTX_MRX_N11

T27

PCIE_GTX_MRX_P12

T24

PCIE_GTX_MRX_N12

T23

PCIE_GTX_MRX_P13

P27

PCIE_GTX_MRX_N13

P26

P24

PCIE_GTX_MRX_N14

P23

M27

PCIE_GTX_MRX_N15

N26

R864 1.27K_0402_1%R864 1.27K_0402_1%

Y22

1 2

R865 2K_0402_1%R865 2K_0402_1%

AA22

1 2

4

PCIE_GTX_C_MRX_P0

C10460.1U_0402_16V7K C10460.1U_0402_16V7K

12

PCIE_GTX_C_MRX_N0

C10470.1U_0402_16V7K C10470.1U_0402_16V7K

12

PCIE_GTX_C_MRX_P1

C10480.1U_0402_16V7K C10480.1U_0402_16V7K

12

PCIE_GTX_C_MRX_N1

C10490.1U_0402_16V7K C10490.1U_0402_16V7K

12

PCIE_GTX_C_MRX_P2

C10500.1U_0402_16V7K C10500.1U_0402_16V7K

12

PCIE_GTX_C_MRX_N2

C10510.1U_0402_16V7K C10510.1U_0402_16V7K

12

PCIE_GTX_C_MRX_P3

C10520.1U_0402_16V7K C10520.1U_0402_16V7K

12

PCIE_GTX_C_MRX_N3

C10530.1U_0402_16V7K C10530.1U_0402_16V7K

12

PCIE_GTX_C_MRX_P4

C10540.1U_0402_16V7K C10540.1U_0402_16V7K

12

PCIE_GTX_C_MRX_N4PCIE_GTX_MRX_N4

C10550.1U_0402_16V7K C10550.1U_0402_16V7K

12

PCIE_GTX_C_MRX_P5

C10560.1U_0402_16V7K C10560.1U_0402_16V7K

12

PCIE_GTX_C_MRX_N5

C10570.1U_0402_16V7K C10570.1U_0402_16V7K

12

PCIE_GTX_C_MRX_P6

C10580.1U_0402_16V7K C10580.1U_0402_16V7K

12

PCIE_GTX_C_MRX_N6

C10590.1U_0402_16V7K C10590.1U_0402_16V7K

12

C10600.1U_0402_16V7K C10600.1U_0402_16V7K

12

PCIE_GTX_C_MRX_N7

C10610.1U_0402_16V7K C10610.1U_0402_16V7K

12

PCIE_GTX_C_MRX_P8

C10620.1U_0402_16V7K C10620.1U_0402_16V7K

12

PCIE_GTX_C_MRX_N8

C10630.1U_0402_16V7K C10630.1U_0402_16V7K

12

PCIE_GTX_C_MRX_P9

C10640.1U_0402_16V7K C10640.1U_0402_16V7K

12

PCIE_GTX_C_MRX_N9

C10650.1U_0402_16V7K C10650.1U_0402_16V7K

12

PCIE_GTX_C_MRX_P10

C10660.1U_0402_16V7K C10660.1U_0402_16V7K

12

PCIE_GTX_C_MRX_N10

C10670.1U_0402_16V7K C10670.1U_0402_16V7K

12

PCIE_GTX_C_MRX_P11

C10690.1U_0402_16V7K C10690.1U_0402_16V7K

12

PCIE_GTX_C_MRX_N11

C10700.1U_0402_16V7K C10700.1U_0402_16V7K

12

PCIE_GTX_C_MRX_P12

C10710.1U_0402_16V7K C10710.1U_0402_16V7K

12

PCIE_GTX_C_MRX_N12

C10720.1U_0402_16V7K C10720.1U_0402_16V7K

12

PCIE_GTX_C_MRX_P13

C10730.1U_0402_16V7K C10730.1U_0402_16V7K

12

PCIE_GTX_C_MRX_N13

C10740.1U_0402_16V7K C10740.1U_0402_16V7K

12

PCIE_GTX_C_MRX_P14PCIE_GTX_MRX_P14

C10750.1U_0402_16V7K C10750.1U_0402_16V7K

12

PCIE_GTX_C_MRX_N14

C10760.1U_0402_16V7K C10760.1U_0402_16V7K

12

PCIE_GTX_C_MRX_P15PCIE_GTX_MRX_P15

C10770.1U_0402_16V7K C10770.1U_0402_16V7K

12

PCIE_GTX_C_MRX_N15

C10780.1U_0402_16V7K C10780.1U_0402_16V7K

12

+1.1VS

VGA Thermal Sensor ADM1032ARMZ-2

GPU_THERMAL_D+[18]

GPU_THERMAL_D-[18]

Closed to GPU

1 2

R951 4.7K_0402_5%R951 4.7K_0402_5%

4

1 2

2200P_0402_50V7K

0.1U_0402_16V4Z

C1371

+3.3V_DELAY

C1372

+3.3V_DELAY

2

1

U69

1

VDD

2

D+

3

DTHERM#4GND

ADM1032ARMZ REEL_MSOP8

EC_SMB_CK2_PX

EC_SMB_DA2_PX

SCLK

SDATA

ALERT#

3

+3.3V_DELAY

12

R948

10K_0402_5%

8 7 6 5

12

R949

R949 10K_0402_5%

10K_0402_5%

6 1

2N7002DW-T/R7_SOT363-6

GPU_GPIO0[18] GPU_GPIO1[18] GPU_GPIO2[18] SOUT_GPIO8[18]

GPU_GPIO9[18] GPU_GPIO11[18] GPU_GPIO12[18] GPU_GPIO13[18]

CRT_VSYNC[18,26] CRT_HSYNC[18,26] VSYNC_DAC2[18] HSYNC_DAC2[18]

GPU_GPIO0 GPU_GPIO1 GPU_GPIO2 SOUT_GPIO8

GPU_GPIO9 GPU_GPIO11 GPU_GPIO12 GPU_GPIO13

VSYNC_DAC1 and HSYNC_DAC1 pull up to HDMI & DISPLAYPORT AUDIO funciton

EC_SMB_CK2_PX EC_SMB_DA2_PX

+3.3V_DELAY

1 2

R950 4.7K_0402_5%R950 4.7K_0402_5%

3

+3VS

2

Q75A

354

Q75B

2N7002DW-T/R7_SOT363-6

THM_ALERT# [18]

2

CONFIGURATION STRAPS

ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET

STRAPS

GPIO0 PCIE FULL TX OUTPUT SWINGTX_PWRS_ENB

GPIO1TX_DEEMPH_EN PCIE TRANSMITTER DE-EMPHASIS ENABLED

GPIO2

BIF_CLK_PM_EN GPIO8 BIF_CLK_PM_EN 0

GPIO9 VGA ENABLEDBIF_VGA DIS

EC_SMB_CK2 [4,26]

EC_SMB_DA2 [4,26]

BIF_RX_PLL_CALIB_BP

BIOS_ROM_EN

VIP_DEVICE_STRAP_ENA V2SYNC

SMS_EN_HARD

AUD[1]

GPIO21

GPIO_22_ROMCSB

GPIO[13:11]ROMIDCFG(2:0)

H2SYNC

GENERICC 0CCBYPASS

HSYNC VSYNCAUD[0]

AMD RESERVED CONFIGURATION STRAPS

STRAPS

R936 10K_0402_5%

R936 10K_0402_5% R937 10K_0402_5%

R937 10K_0402_5% R938 10K_0402_5%

R938 10K_0402_5%

@

R939 10K_0402_5%

@

@ @

@

R940 10K_0402_5%

R940 10K_0402_5% R941 10K_0402_5%R941 10K_0402_5% R942 10K_0402_5%

R942 10K_0402_5%

@

R943 10K_0402_5%

@

@ @

@

R944 10K_0402_5%R944 10K_0402_5% R945 10K_0402_5%R945 10K_0402_5% R946 10K_0402_5%

R946 10K_0402_5% R947 10K_0402_5%

R947 10K_0402_5%

@

@ @

@

GPIO5_AC_BATT TEST

+3.3V_DELAY

12 12 12 12

M92 S2-XT

VRAM_ID[2:0]

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DVPDATA

3.2.1

2009/04/20 2010/04/30

ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET

H2SYNC

GENERICC

PULLUP PADS ARE NOT REQUIRED FOR THESE STRAPS BUT IF THESE GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET

GPIO21_BB_ENGPIO_28_TDO

Project

GPU VRAM size

JM51_PU

512MB(x4) 256MB(X2)

JM51_PU

512MB(x4)

JM51_PU JM51_PU

256MB(X2)

Compal Secret Data

Deciphered Date

2

DESCRIPTION OF DEFAULT SETTINGSPIN

PCIE GNE2 ENABLEDBIF_GEN2_EN_A

BIF_RX_PLL_CALIB_BP

ENABLE EXTERNAL BIOS ROM

SERIAL ROM TYPE OR MEMORY APERTURE SIZE SELECT IGNORE VIP DEVICE STRAPS

AUD[1] AUD[0] 0 0 No audio function 0 1 Audio for DisplayPort and HDMI if dongle is detected 1 0 Audio for DisplayPort only 1 1 Audio for both DisplayPort and HDMI

Vendor Part Number#STRAPS

Samsung 64Mx16x4 DDR3 Samsung 64Mx16x2 DDR3 Hynix 64Mx16x4 DDR3 Hynix 64Mx16x2 DDR3

Compal Part Number#

SA000035700

SA000032400

Title

M92-S2 PCIE,STRAP

Size Document Number Rev

Custom

Date: Sheet of

1

RECOMMENDED SETTINGS

1

0 0

1

00

0

X X

VRAM_ID 2,1,0

1 0 0 1 0 1 0 0 0 0 1 0

Compal Electronics, Inc.

LS-5588

1

17 35Wednesday, July 01, 2009

0.3

+1.8VS

+3.3V_DELAY

D D

C C

B B

A A

CLK_GPIO10 R_CLK_GPIO10

R895 10K_0402_5%@R895 10K_0402_5%@

R883 10K_0402_5%@R883 10K_0402_5%@

R891 10K_0402_5%R891 10K_0402_5%

R889 1K_0402_5%R889 1K_0402_5%

R882 10K_0402_5%@R882 10K_0402_5%@

5

Internal pull low

1 2

R952 10K_0402_5%@R952 10K_0402_5%@

1 2

R953 10K_0402_5%@R953 10K_0402_5%@

1 2

R954 10K_0402_5%@R954 10K_0402_5%@

DDC2_CLK

1 2

R871 4.7K_0402_5%R871 4.7K_0402_5%

R873 4.7K_0402_5%R873 4.7K_0402_5%

R875 10K_0402_5%R875 10K_0402_5%

R878 4.7K_0402_5%R878 4.7K_0402_5%

R893 4.7K_0402_5%R893 4.7K_0402_5%

R894 4.7K_0402_5%R894 4.7K_0402_5%

R900 4.7K_0402_5%R900 4.7K_0402_5%

R905 10K_0402_5%@R905 10K_0402_5%@

R890 10K_0402_5%@R890 10K_0402_5%@

R960 10K_0402_5%@R960 10K_0402_5%@

27M_NSSC_R

1 2

R1002

0_0402_5%

GPIO24_TRSTB

12

ENAVDD

12

ENABLT

12

TESTEN

12

BB_EN

12

DDC2_DATA

VGA_PWRSEL0

12

CRT_DDC_CLK

CRT_DDC_DATA

HDMI_SCL

HDMI_SDA

GPIO23_CLKREQB

12

GPIO24_TRSTB

ROMSE_GPIO22

12

BB_EN[20]

499_0402_1%

249_0402_1%

1 2

R887

75_0402_1%

100_0402_5%

+1.8VS

BLM18PG121SN1D_0603

(1.8V@20mA TSVDD)

VRAM_ID0

VRAM_ID1

VRAM_ID2

EMI

+1.8VS

R884

R886

DDC2_CLK[26] DDC2_DATA[26]

ENABLT[26] SOUT_GPIO8[17] GPU_GPIO9[17]

GPU_GPIO11[17] GPU_GPIO12[17] GPU_GPIO13[17]

VGA_PWRSEL0[33]

27M_SSC[16]

THM_ALERT#[17]

ROMSE_GPIO22

12

R888

1 2

L109

10U_0603_6.3V

VGA_CLK_REQ#[16]

12

HDMI_HPD#[26]

GPU_THERMAL_D+[17] GPU_THERMAL_D-[17]

1

C1114

2

GPU_GPIO0[17] GPU_GPIO1[17] GPU_GPIO2[17]

R877 0_0402_5%@R877 0_0402_5%@

ENABLT SOUT_GPIO8 GPU_GPIO9

GPU_GPIO11 GPU_GPIO12 GPU_GPIO13

R880 10K_0402_5%

BB_EN

0.1U_0402_10V6K

1

C1110

2

1U_0402_6.3V4Z

1

C1115

2

VRAM_ID0 VRAM_ID1 VRAM_ID2

LCD

0_0402_5%

R881

1 2 1 2

R959

0_0402_5%

1 2

VGA_PWRSEL0

1 2

R879 0_0402_5%@R879 0_0402_5%@

@

1 2

VGA_PWRSEL1

T42PADT42PAD

GPIO23_CLKREQB

GPIO24_TRSTB

T5 PADT5 PAD C1099 T6 PADT6 PAD T7 PADT7 PAD T76PADT76PAD

TESTEN

+DPLL_PVDD

+DPLL_VDDC

1.8V

27MCLK XTALOUT

T45PADT45PAD

1

C1116

0.1U_0402_10V6K

2

27M_NSSC_R

LCDI2C_CLK LCDI2C_DAT

GPU_GPIO0 GPU_GPIO1 GPU_GPIO2

R_CLK_GPIO10

R_27M_SSC

GPU_CTF

4

U64B

MUTI GFX

AA1

DVPCNTL_MVP_0

Y4

DVPCNTL_MVP_1

AC7

DVPCNTL_0

Y2

DVPCNTL_1

U5

DVPCNTL_2

U1

DVPCLK

Y7

DVPDATA_0

V2

DVPDATA_1

Y8

DVPDATA_2

V4

DVPDATA_3

AB7

DVPDATA_4

W1

DVPDATA_5

AB8

DVPDATA_6

W3

DVPDATA_7

AB9

DVPDATA_8

W5

DVPDATA_9

AC6

DVPDATA_10

W6

DVPDATA_11

AD7

DVPDATA_12

AA3

DVPDATA_13

AC8

DVPDATA_14

AA5

DVPDATA_15

AE8

DVPDATA_16

AA6

DVPDATA_17

AE9

DVPDATA_18

AB4

DVPDATA_19

AD9

DVPDATA_20

AB2

DVPDATA_21

AC10

DVPDATA_22

AC5

DVPDATA_23

R1

SCL

R3

SDA

GENERAL PURPOSE I/O

U6

GPIO_0

U10

GPIO_1

T10

GPIO_2

U8

GPIO_3_SMBDATA

U7

GPIO_4_SMBCLK

T9

GPIO_5_AC_BATT

T8

GPIO_6

T7

GPIO_7_BLON

P10

GPIO_8_ROMSO

P4

GPIO_9_ROMSI

P2

GPIO_10_ROMSCK

N6

GPIO_11

N5

GPIO_12

N3

GPIO_13

Y9

GPIO_14_HPD2

N1

GPIO_15_PWRCNTL_0

M4

GPIO_16_SSIN

R6

GPIO_17_THERMAL_INT

W10

GPIO_18_HPD3

M2

GPIO_19_CTF

P8

GPIO_20_PWRCNTL_1

P7

GPIO_21_BB_EN

N8

GPIO_22_ROMCSB

N7

GPIO_23_CLKREQB

T11

GPIO_29_DRM_0

R11

GPIO_30_DRM_1

L6

JTAG_TRSTB

L5

JTAG_TDI

L3

JTAG_TCK

L1

JTAG_TMS

K4

JTAG_TDO

AF24

TESTEN

AB13

GENERICA

W8

GENERICB

W9

GENERICC

W7

GENERICD

AD10

GENERICE_HPD4

AC14

HPD1

AC16

VREFG

PLL/CLOCK

AF14

DPLL_PVDD

AE14

DPLL_PVSS

AD14

DPLL_VDDC

AM28

XTALIN

AK28

XTALOUT

T4

DPLUS

T2

DMINUS

R5

TS_FDO

AD17

TSVDD

AC17

TSVSS

216-0728002 A11 M92-S2_FCBGA631

3

U64F

AF2

TXCAP_DPA3P

AF4

TXCAM_DPA3N

AG3

TX0P_DPA2P

AG5

TX0M_DPA2N

DPA

TXCBP_DPB3P TXCBM_DPB3N

DPB

DAC1

I2C

DAC2

DDC/AUX

THERMAL

NC_DDCAUX7P NC_DDCAUX7N

TX1P_DPA1P TX1M_DPA1N

TX2P_DPA0P TX2M_DPA0N

TX3P_DPB2P TX3M_DPB2N

TX4P_DPB1P TX4M_DPB1N

TX5P_DPB0P TX5M_DPB0N

HSYNC

VSYNC

RSET AVDD

AVSSQ VDD1DI

VSS1DI

COMP

H2SYNC V2SYNC

VDD2DI VSS2DI

A2VDD

A2VDDQ

A2VSSQ

R2SET

DDC1CLK

DDC1DATA

AUX1P AUX1N

DDC2CLK

DDC2DATA

AUX2P AUX2N

DDCAUX5P DDCAUX5N

DDC6CLK

DDC6DATA

AH3 AH1

AK3 AK1

AK5 AM3

D_RED

AK6 AM5

D_GREEN

AJ7

D_BLUE

AH6 AK8

AL7

AM26

R

AK26

RB

AL25

G

AJ25

GB

AH24

B

AG25

BB

AH26 AJ27

R876

AD22

1 2

499_0402_1%

+AVDD

AG24 AE22

+VDD1DI

AE23 AD23

AM12

R2

AK12

R2B

AL11

G2

AJ11

G2B

AK10

B2

AL9

B2B

AH12

C

AM10

Y

AJ9

AL13 AJ13

+VDD2DI

AD19 AC19

+A2VDD

AE20

+A2VDDQ

AE17 AE19

R885

1 2

AG13

715_0402_1%

CRT_DDC_CLK

AE6

CRT_DDC_DATA

AE5 AD2

AD4

HDMI_SCL

AC11

HDMI_SDA

AC13 AD13

AD11

AB22

NC1

AC22

NC2

AE16 AD16

AC1 AC3

AD20 AC20

R870 150_0402_1%R870 150_0402_1% R872 150_0402_1%R872 150_0402_1% R874 150_0402_1%R874 150_0402_1%

T2PAD T2PAD T3PAD T3PAD T4PAD T4PAD

1 2

R956 0_0402_5%R956 0_0402_5%

1 2

R957 0_0402_5%R957 0_0402_5%

1 2

R955 0_0402_5%R955 0_0402_5%

R901 0_0402_5%R901 0_0402_5%

1 2 1 2

R903 0_0402_5%R903 0_0402_5%

T41PAD T41PAD T40PAD T40PAD

TXCD+ [26] TXCD- [26]

TX0D+ [26] TX0D- [26]

TX1D+ [26] TX1D- [26]

TX2D+ [26] TX2D- [26]

1 2 1 2 1 2

D_RED [26]

D_GREEN [26]

D_BLUE [26]

CRT_HSYNC [17,26] CRT_VSYNC [17,26]

STRAP

+1.8VS +1.1VS

HSYNC_DAC2 [17] VSYNC_DAC2 [17]

+3.3V_DELAY

CRT_DDC_CLK [26] CRT_DDC_DATA [26]

U64F

216-0728002 A11 M92-S2_FCBGA631

L102

1 2

MCK1608471YZF 0603

10U_0603_6.3V6M

+VDD1DI

CRT

HDMI

VGA_HDMI_SCL [26] VGA_HDMI_SDA [26]

LVDS CONTROL

TXOUT_U0P_DPF2P TXOUT_U0N_DPF2N

TXOUT_U1P_DPF1P TXOUT_U1N_DPF1N

TXOUT_U2P_DPF0P TXOUT_U2N_DPF0N

LVTMDP

TXOUT_L0P_DPE2P TXOUT_L0N_DPE2N

TXOUT_L1P_DPE1P TXOUT_L1N_DPE1N

TXOUT_L2P_DPE0P TXOUT_L2N_DPE0N

(1.8V@120mA +DPLL_PVDD) (1.1V@300mA +DPLL_VDDC)

1

C1092

2

1

2

VARY_BL

DIGON

TXCLK_UP_DPF3P TXCLK_UN_DPF3N

TXOUT_U3P TXOUT_U3N

TXCLK_LP_DPE3P TXCLK_LN_DPE3N

TXOUT_L3P TXOUT_L3N

1U_0402_6.3V4Z

1

C1093

2

1 2

R143

@R143

@

33_0402_1%

33_0402_1% C1209

C1209 22P_0402_50V8J

22P_0402_50V8J

@

EMI

2

27MCLK_XTL

ENAVDD

T29PAD T29PAD

ENAVDD [26]

TXCLK_L+ [26] TXCLK_L- [26]

TXOUT_L0+ [26] TXOUT_L0- [26]

TXOUT_L1+ [26] TXOUT_L1- [26]

TXOUT_L2+ [26] TXOUT_L2- [26]

1

27MHz_16PF_6P27000126

@

C1117

2

22P_0402_50V8J

R03

27MCLK_SSIC

XTALOUT_XTL

AB11 AB12

AH20 AJ19

AL21 AK20

AH22 AJ21

AL23 AK22

AK24 AJ23

AL15 AK14

AH16 AJ15

AL17 AK16

AH18 AJ17

AL19 AK18

4 1

@ Y6

@

GND IN

1 2 3

R1005 0_0402_5%

@

R1005 0_0402_5%

@

R1006 0_0402_5%

@

R1006 0_0402_5%

@

Y6

3

OUT

2

GND

U71

REFOUT XOUT XIN/CLKIN

ASM3P2872AF-06OR_TSOT-23-6@

R_27M_SSC

R03

MODOUT

04/22 Spread Spectrum For EMI

L103

+DPLL_PVDD +DPLL_VDDC

1

C1094

0.1U_0402_10V6K

2

L103

1 2

MCK1608471YZF 0603

10U_0603_6.3V6M

+1.8VS +AVDD

L104

BLM18PG121SN1D_0603

10U_0603_6.3V

L105

BLM18PG121SN1D_0603

10U_0603_6.3V

1

C1095

2

(1.8V@70mA AVDD)

12

1

C1098

2

(1.8V@45mA VDD1DI)

12

1

C1101

2

1U_0402_6.3V4Z

1

C1096

2

1U_0402_6.3V4Z

1

2

1U_0402_6.3V4Z

1

2

C1099

0.1U_0402_10V6K

C1102

0.1U_0402_10V6K

(1.8V@1mA A2VDDQ)

FLASH ROM

U70

@U70

@

5

CLK_GPIO10

+3.3V_DELAY

0_0402_5%

CLK_GPIO10

ROMSE_GPIO22

R1000

R1000 R1001

R1001

@

6 1 7 3 8

R03

M25P10-AVMN6P

C1390

0.1U_0402_16V7K

D C S HOLD W VCC

1

12

@ R896

@

1

@

C1118

2

22P_0402_50V8J

6

VSS

5 4

VDD

R144

1 2

33_0402_1% @

0.1U_0402_10V6K

0.1U_0402_10V6K 1U_0402_6.3V4Z

1U_0402_6.3V4Z

1

C1097

0.1U_0402_10V6K

2

1

2

1

2

Q

TYPE 1

4

VSS

27MCLK

XTALOUTXTALOUT_XTL

27MCLK_XTL

R896 1M_0402_5%

1M_0402_5%

XTALOUT_XTL

Close to M92

+3.3V_DELAY

1

C1105

2

C1104

@

C1100

+VDD1DI

C1103

SOUT_GPIO8GPU_GPIO9

1

2

@

EMI

Security Classification Compal Secret Data

R1003

R1004 0_0402_5%R1004 0_0402_5%

27M_NSSC[16]

5

27M_NSSC_R

R1003 0_0402_5%

0_0402_5%

@

27MCLK_SSIC

4

Security Classification Compal Secret Data

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/04/20 2010/04/30

3

Deciphered Date

2

Compal Electronics, Inc.

Title

M92-S2 LVDS,CRT,HDMI

Size Document Number Rev

Custom

Date: Sheet of

LS-5588

18 35Wednesday, July 01, 2009

1

0.3

5

4

3

2

1

MAA_0 MAA_1 MAA_2 MAA_3 MAA_4 MAA_5 MAA_6 MAA_7 MAA_8 MAA_9

ODTA0 ODTA1

CLKA0

CLKA1

CKEA0 CKEA1

WEA0B WEA1B

K17 J20 H23 G23 G24 H24 J19 K19 J14 K14 J11 J13 H11 G11 J16 L15

E32 E30 A21 C21 E13 D12 E3 F4

H28 C27 A23 E19 E15 D10 D6 G5

H27 A27 C23 C19 C15 E9 C5 H4

L18 K16

H26 H25

G9 H9

G22 G17

G19 G16

H22 J22

G13 K13

K20 J17

G25 H10

AB16 G14 G20

MDA[0..63]

DRAM_RST#[21]

MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8 MAA9 MAA10 MAA11 MAA12 BA2 BA0 BA1

DQMA#0 DQMA#1 DQMA#2 DQMA#3 DQMA#4 DQMA#5 DQMA#6 DQMA#7

QSA0 QSA1 QSA2 QSA3 QSA4 QSA5 QSA6 QSA7

QSA#0 QSA#1 QSA#2 QSA#3 QSA#4 QSA#5 QSA#6 QSA#7

ODTA0 ODTA1

CLKA0 CLKA0#

CLKA1 CLKA1#

RASA#0 RASA#1

CASA#0 CASA#1

CSA0#

CSA1#

CKEA0 CKEA1

WEA#0 WEA#1

T74PADT74PAD T75PADT75PAD T71PADT71PAD

MDA[0..63] [21]

ODTA0 [21] ODTA1 [21]

CLKA0 [21] CLKA0# [21]

CLKA1 [21] CLKA1# [21]

RASA#0 [21] RASA#1 [21]

CASA#0 [21] CASA#1 [21]

CSA0# [21]

CSA1# [21]

CKEA0 [21] CKEA1 [21]

WEA#0 [21] WEA#1 [21]

4.7K_0402_5%

DRAM_RST#

R316

+1.5VS

+1.8VS

BLM18PG121SN1D_0603

DQMA#[7..0] [21]

(1.1V@170mA +DPF_VDD10)

QSA[7..0] [21]

QSA#[7..0] [21]

12

R3174.7K_0402_5%@R3174.7K_0402_5%

1

C337

2

1U_0402_6.3V4Z

1 2

U64G

1

C1259

2

U64G

AG15

DPE_VDD18#1

AG16

DPE_VDD18#2

AG20

DPE_VDD10#1

AG21

DPE_VDD10#2

AG14

DPE_VSSR#1

AH14

DPE_VSSR#2

AM14

DPE_VSSR#3

AM16

DPE_VSSR#4

AM18

DPE_VSSR#5

AF16

DPF_VDD18#1

AG17

DPF_VDD18#2

AF22

DPF_VDD10#1

AG22

DPF_VDD10#2

AF23

DPF_VSSR#1

AG23

DPF_VSSR#2

AM20

DPF_VSSR#3

AM22

DPF_VSSR#4

AM24

DPF_VSSR#5

AF17

DPEF_CALR

AG18

DPE_PVDD

AF19

DPE_PVSS

AG19

NC_DPF_PVDD

AF20

NC_DPF_PVSS

216-0728002 A11 M92-S2_FCBGA631

R907

100_0402_1%

R909

100_0402_1%

1U_0402_6.3V4Z

1

C1260

2

@

DP PLL POWER

12

+DPA_VDD18

1

C1261

0.1U_0402_10V6K

2

@

DP A/B POWERDP E/F POWER

NC_DPA_VDD18#1 NC_DPA_VDD18#2

DPA_VDD10#1 DPA_VDD10#2

DPA_VSSR#1 DPA_VSSR#2 DPA_VSSR#3 DPA_VSSR#4 DPA_VSSR#5

NC_DPB_VDD18#1 NC_DPB_VDD18#2

DPB_VDD10#1 DPB_VDD10#2

DPB_VSSR#1 DPB_VSSR#2 DPB_VSSR#3 DPB_VSSR#4 DPB_VSSR#5

DPAB_CALR

DPA_PVDD DPA_PVSS

DPB_PVDD DPB_PVSS

+VDD_MEM15_REF1

1

C1141

0.1U_0402_16V4Z

2

+DPA_VDD18

AE11 AF11

(1.1V@200mA +DPA_VDD10)

+DPA_VDD10+DPA_VDD10

AF6 AF7

AE1 AE3 AG1 AG6 AH5

AE13 AF13

AF8 AF9

AF10 AG9 AH8 AM6 AM8

AE10

AG8 AG7

AG10 AG11

R899

150_0402_1%

1 2

+DPA_PVDD

+DPB_PVDD

1

C1122

10U_0603_6.3V

2

1U_0402_6.3V4Z

1

C1123

2

(1.8V@20mA +DPA_PVDD)

1U_0402_6.3V4Z

1

C113410U_0603_6.3V C113410U_0603_6.3V

C1135

2

(1.8V@20mA +DPB_PVDD)

1U_0402_6.3V4Z

1

C1137

10U_0603_6.3V

2

(1.8V@200mA +DPE_VDD18)

+1.8VS +DPE_VDD18

+DPE_VDD18

BLM18PG121SN1D_0603

L110

BLM18PG121SN1D_0603

10U_0603_6.3V

R897

1 2

12

L112

10U_0603_6.3V

@

+1.1VS

BLM18PG121SN1D_0603

10U_0603_6.3V

+1.8VS +1.8VS

10U_0603_6.3V

R906

100_0402_1%

R908

100_0402_1%

1U_0402_6.3V4Z

12

1

C1119

C1120

2

1U_0402_6.3V4Z

0_0402_5%

1

C1125

C1126

2

0.1U_0402_10V6K

L2

1U_0402_6.3V4Z

12

1

C1129

C1128

2

(1.8V@20mA +DPE_PVDD)

L113

1U_0402_6.3V4Z

12

1

C1132

C1131

2

+1.5VS +1.5VS

12

Close to K26 Close to J26

+VDD_MEM15_REFD

1

12

C1140

0.1U_0402_16V4Z

2

(For future use only)

+1.8VS

MCK1608471YZF 0603@

+DPF_VDD10

C1121

0.1U_0402_10V6K

2

1

C1127

+DPF_VDD18

2

+DPF_VDD10

1

C1130

0.1U_0402_10V6K

2

150_0402_1%

1 2

+DPE_PVDD

1

+DPE_PVDD

C1133

0.1U_0402_10V6K

2

L126

1 2

10U_0603_6.3V6M

R898

(1.8V@120mA +DPLL_PVDD)

@

L111

BLM18PG121SN1D_0603

C1124

0.1U_0402_10V6K

BLM18PG121SN1D_0603

1

C1136

0.1U_0402_10V6K

2

1

C1138

C1139

0.1U_0402_10V6K

2

+1.1VS

12

L114

12

+1.8VS

L115

12

BLM18PG121SN1D_0603

BA[2..0]

D D

C C

B B

4.7K_0402_5%

+VDD_MEM15_REFD +VDD_MEM15_REF1

T78PADT78PAD T79PADT79PAD

T80PADT80PAD

R321

BA[2..0] [21]

MDA0 MDA1 MDA2 MDA3 MDA4 MDA5 MDA6 MDA7 MDA8

MDA9 MDA10 MDA11 MDA12 MDA13 MDA14 MDA15 MDA16 MDA17 MDA18 MDA19 MDA20 MDA21 MDA22 MDA23 MDA24 MDA25 MDA26 MDA27 MDA28 MDA29 MDA30 MDA31 MDA32 MDA33 MDA34 MDA35 MDA36 MDA37 MDA38 MDA39 MDA40 MDA41 MDA42 MDA43 MDA44 MDA45 MDA46 MDA47 MDA48 MDA49 MDA50 MDA51 MDA52 MDA53 MDA54 MDA55 MDA56 MDA57 MDA58 MDA59 MDA60 MDA61 MDA62 MDA63

R902243_0402_1% R902243_0402_1%

1 2

DRAM_RST#

12

R322

4.7K_0402_5%

MAA[12..0]

U64C

K27

DQA_0

J29

DQA_1

H30

DQA_2

H32

DQA_3

G29

DQA_4

F28

DQA_5

F32

DQA_6

F30

DQA_7

C30

DQA_8

F27

DQA_9

A28

DQA_10

C28

DQA_11

E27

DQA_12

G26

DQA_13

D26

DQA_14

F25

DQA_15

A25

DQA_16

C25

DQA_17

E25

DQA_18

D24

DQA_19

E23

DQA_20

F23

DQA_21

D22

DQA_22

F21

DQA_23

E21

DQA_24

D20

DQA_25

F19

DQA_26

A19

DQA_27

D18

DQA_28

F17

DQA_29

A17

DQA_30

C17

DQA_31

E17

DQA_32

D16

DQA_33

F15

DQA_34

A15

DQA_35

D14

DQA_36

F13

DQA_37

A13

DQA_38

C13

DQA_39

E11

DQA_40

A11

DQA_41

C11

DQA_42

F11

DQA_43

A9

DQA_44

C9

DQA_45

F9

DQA_46

D8

DQA_47

E7

DQA_48

A7

DQA_49

C7

DQA_50

F7

DQA_51

A5

DQA_52

E5

DQA_53

C3

DQA_54

E1

DQA_55

G7

DQA_56

G6

DQA_57

G1

DQA_58

G3

DQA_59

J6

DQA_60

J1

DQA_61

J3

DQA_62

J5

DQA_63

K26

MVREFDA

J26

MVREFSA

J25

NC_MEM_CALRN0

K7

NC_MEM_CALRN1

J8

MEM_CALRP1

K25

NC_MEM_CALRP0

L10

DRAM_RST

K8

CLKTESTA

L7

CLKTESTB

12

216-0728002 A11 M92-S2_FCBGA631

MAA[12..0] [21]

MAA_10 MAA_11

MAA_12 MAA_13/BA2 MAA_14/BA0 MAA_15/BA1

DQMA_0 DQMA_1 DQMA_2 DQMA_3 DQMA_4 DQMA_5 DQMA_6

MEMORY INTERFACE

DQMA_7

RDQSA_0 RDQSA_1 RDQSA_2 RDQSA_3 RDQSA_4 RDQSA_5 RDQSA_6 RDQSA_7

WDQSA_0 WDQSA_1 WDQSA_2 WDQSA_3 WDQSA_4 WDQSA_5 WDQSA_6 WDQSA_7

CLKA0B

CLKA1B

RASA0B

RASA1B

CASA0B

CASA1B

CSA0B_0 CSA0B_1

CSA1B_0 CSA1B_1

RSVD#1

RSVD#2

RSVD#3

A A

@

5

4

Security Classification Compal Secret Data

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/04/20 2010/04/30

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

M92-S2 MEMORY

LS-5588

1

19 35Wednesday, July 01, 2009

0.3

5

+1.5VS

(1.5V@2200mA)

1

C1365

2

D D

1

C1142

2

1U_0402_6.3V4Z

10U_0603_6.3V

+1.8VS

L117

BLM18PG121SN1D_0603

10U_0603_6.3V

+3.3V_DELAY

10U_0603_6.3V

C C

B B

C1177

1

2

1U_0402_6.3V4Z

+1.5VS

BLM18PG121SN1D_0603

+1.8VS

BLM18PG121SN1D_0603

+VGA_CORE

C1178

1

2

L119

L121

10U_0603_6.3V

MCK1608471YZF 0603

C1366

2

0.1U_0402_10V6K

1

C1143

2

1U_0402_6.3V4Z

C1155

1

2

12

C1163

1

2

1U_0402_6.3V4Z

1

2

12

L122

1 2

10U_0603_6.3V

C1368

2

0.1U_0402_10V6K

1

C1144

2

1U_0402_6.3V4Z

10U_0603_6.3V

(1.8V@110mA +VDDC_CT)

1

2

1U_0402_6.3V4Z

C1179

1

2

1U_0402_6.3V4Z

VDD_RHA1.5

C1196

1

2

+BBP

Back Biasing

12

L130

BLM18PG121SN1D_0603

G

2

S

BLM18PG121SN1D_0603

+VGA_CORE

R2129

10K_0402_5%

5

Q2

SSM3K7002FU_SC70-3

D

1 3

A A

BB_EN[18]

1

C1370

2

0.1U_0402_10V6K

1

C1146

2

1U_0402_6.3V4Z

10U_0603_6.3V

C1153

1

2

C1164

C1180

1U_0402_6.3V4Z

1

2

1U_0402_6.3V4Z

C1203

1

2

+BBP

SI2301BDS_SOT23

2

G

1 2

1

2

1

C1147

2

1U_0402_6.3V4Z

C1154

1

2

LV_TRANS1.8

C1165

1

2

0.1U_0402_10V6K

+VDDR5

+VDDR4

1U_0402_6.3V4Z

C1197

C1204

1

2

0.1U_0402_10V6K

S

13

D

Q4

Q4 SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

S

1

C1374

2

1U_0402_6.3V4Z

1

C1148

2

1U_0402_6.3V4Z

10U_0603_6.3V

C1194

1

2

C1198

1

2

0.1U_0402_10V6K

C1205

1

2

1U_0402_6.3V4Z

Q3

G

2

1

C1375

2

1U_0402_6.3V4Z

1

C1149

2

1U_0402_6.3V4Z

C1156

1

2

1U_0402_6.3V4Z

+PCIE_PVDD

+SPV10

C1206

1

2

0.1U_0402_10V6K

D

13

R2128

100K_0402_5%

1

C1376

2

1U_0402_6.3V4Z

C1150

1U_0402_6.3V4Z

+VDDC_CT

C1195

1

2

C1207

1

2

C1391

1

1U_0402_6.3V4Z

2

+1.8VS

+5VS

12

C1377

AA20 AA21 AB20 AB21

AA17 AA18 AB17 AB18

AA11 AA12

AM30

1U_0402_6.3V4Z

H13 H16 H19

J10 J23 J24

J9 K10 K23 K24

K9 L11 L12 L13 L20 L21 L22

U11 U12 V11 V12

Y11 Y12

L17 L16

L8

H7

H8

J7

M11 M12

4

U64D

MEM I/O

VDDR1#1 VDDR1#2 VDDR1#3 VDDR1#4 VDDR1#5 VDDR1#6 VDDR1#7 VDDR1#8 VDDR1#9 VDDR1#10 VDDR1#11 VDDR1#12 VDDR1#13 VDDR1#14 VDDR1#15 VDDR1#16 VDDR1#17

LEVEL

LEVEL TRANSLATION

TRANSLATION

VDD_CT#1 VDD_CT#2 VDD_CT#3 VDD_CT#4

I/O

VDDR3#1 VDDR3#2 VDDR3#3 VDDR3#4

VDDR5#1 VDDR5#2 VDDR5#3 VDDR5#4

VDDR4#1 VDDR4#2 VDDR4#3 VDDR4#4

MEM CLK

VDDRHA VSSRHA

PLL

PCIE_PVDD

NC_MPV18

NC_SPV18

PCIE

PCIE_VDDR#1 PCIE_VDDR#2 PCIE_VDDR#3 PCIE_VDDR#4 PCIE_VDDR#5 PCIE_VDDR#6 PCIE_VDDR#7 PCIE_VDDR#8

PCIE_VDDC#1 PCIE_VDDC#2 PCIE_VDDC#3 PCIE_VDDC#4 PCIE_VDDC#5 PCIE_VDDC#6 PCIE_VDDC#7 PCIE_VDDC#8

PCIE_VDDC#9 PCIE_VDDC#10 PCIE_VDDC#11 PCIE_VDDC#12

CORE

POWER

ISOLATED

ISOLATED CORE I/O

CORE I/O

VDDC#1 VDDC#2 VDDC#3 VDDC#4 VDDC#5 VDDC#6 VDDC#7 VDDC#8

VDDC#9 VDDC#10 VDDC#11 VDDC#12 VDDC#13 VDDC#14 VDDC#15 VDDC#16 VDDC#17 VDDC#18 VDDC#19 VDDC#20 VDDC#21 VDDC#22 VDDC#23

VDDCI#1 VDDCI#2 VDDCI#3 VDDCI#4 VDDCI#5 VDDCI#6 VDDCI#7 VDDCI#8

AB23 AC23 AD24 AE24 AE25 AE26 AF25 AG26

L23 L24 L25 L26 M22 N22 N23 N24 R22 T22 U22 V22

AA15 N15 N17 R13 R16 R18 R21 T12 T15 T17 T20 U13 U16 U18 U21 V15 V17 V20 V21 Y13 Y16 Y18 Y21

M13 M15 M16 M17 M18 M20 M21 N20

SPV10 SPVSS

BACK BIAS

BBP#1 BBP#2

216-0728002 A11 M92-S2_FCBGA631

+1.8VS

L123

12

BLM18PG121SN1D_0603

10U_0603_6.3V

+1.8VS

L128

BLM18PG121SN1D_0603

BB_EN=0V,for Back Biasing Disabled, Q2004=OFF,Q2005=OFF and Q2006=ON, +BBP=+GPU_CORE BB_EN=+3.3V,for Back Biasing Enabled, Q2004=ON,Q2005=ON and Q2006=OFF, +BBP=+1.8VSDGPU

4

10U_0603_6.3V

12

10U_0603_6.3V

3

1U_0402_6.3V4Z

1

2

1U_0402_6.3V4Z

C1167

1

2

1U_0402_6.3V4Z

10U_0603_6.3V

1

2

C1292

1

2

1U_0402_6.3V4Z

C1199

1

2

+VDDR4

C1303

1

2

+VDDR5

C1278

1

2

1U_0402_6.3V4Z

1

C1151

2

1U_0402_6.3V4Z

1

C1158

2

1U_0402_6.3V4Z

C1169

C1168

1

2

1U_0402_6.3V4Z

1

C1186

2

10U_0603_6.3V

1U_0402_6.3V4Z

C1380

C1379

1

2

1U_0402_6.3V4Z

10U_0603_6.3V

C1200

C1201

1

2

1U_0402_6.3V4Z

SUSP#

3

1

C1299

2

1U_0402_6.3V4Z

C1159

1U_0402_6.3V4Z

C1170

1

2

1U_0402_6.3V4Z

10U_0603_6.3V

C1187

C1248

1

2

1U_0402_6.3V4Z

C1202

1

2

2009/04/20 2010/04/30

+PCIE_GDDR

1

C1145

0.1U_0402_10V6K

2

+PCIE_VDDC

1

C1157

C1157 1U_0402_6.3V4Z

1U_0402_6.3V4Z

2

1U_0402_6.3V4Z

C1166

1

2

1U_0402_6.3V4Z

1

C1185

C1185 10U_0603_6.3V

10U_0603_6.3V

2

1U_0402_6.3V4Z

+VDDCI

1U_0402_6.3V4Z

C1281

C1298

1

2

0.1U_0402_10V6K

1U_0402_6.3V4Z

C1280

C1277

1

2

0.1U_0402_10V6K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

(1.8V@500mA +PCIE_GDDR)

1U_0402_6.3V4Z

1

C1301

C1300

2

(1.1V@2000mA +PCIE_VDDC)

1U_0402_6.3V4Z

1

C1160

2

1U_0402_6.3V4Z

C1171

1

2

1

C1304

2

10U_0603_6.3V

C1381

(+VGA_CORE@2000mA +VDDCI)

R03

1

C1162

C1161

10U_0603_6.3V

2

(+VGA_CORE@9000mA +VDDC)

1U_0402_6.3V4Z

C1174

C1173

C1172

1

2

1U_0402_6.3V4Z

1

C1188

1

C1305

2

1U_0402_6.3V4Z

For S2: Install L124 and DO not Install L127

For S3: Install L127 and DO not Install L124

1 2

L120

MCK2012221YZF 0805

+3.3V_DELAY

CH751H-40_SC76

CH751H-40_SC76 D7

D7

1 2

R911 100K_0402_5%R911 100K_0402_5%

Compal Secret Data

1

C1152

C1152 10U_0603_6.3V

10U_0603_6.3V

2

1

C1175

+

C1176

C1176 330U_D2E_2.5VM_R9M

330U_D2E_2.5VM_R9M

2

1U_0402_6.3V4Z

C1189

1

2

SI2301BDS_SOT23

21

Deciphered Date

1 2

MCK2012221YZF 0805

C1190

1

2

1U_0402_6.3V4Z

Q73

1 3

D

2

1

C1208

0.1U_0402_10V6K

2

L116

C1191

G

+1.8VS

+1.1VS

+VGA_CORE

C1192

1

2

S

G

2

13

D

Q74

Q74 2N7002_SOT23

2N7002_SOT23

S

2

1U_0402_6.3V4Z

R910

R910 100K_0402_5%

100K_0402_5%

1 2

2

+3VS

1

U64E

AA27

PCIE_VSS#1

AB24

PCIE_VSS#2

AB32

PCIE_VSS#3

AC24

PCIE_VSS#4

AC26

PCIE_VSS#5

AC27

PCIE_VSS#6

AD25

PCIE_VSS#7

AD32

PCIE_VSS#8

AE27

PCIE_VSS#9

AF32

PCIE_VSS#10

AG27

PCIE_VSS#11

AH32

PCIE_VSS#12

K28

PCIE_VSS#13

K32

PCIE_VSS#14

L27

PCIE_VSS#15

M32

PCIE_VSS#16

N25

PCIE_VSS#17

N27

PCIE_VSS#18

P25

PCIE_VSS#19

P32

PCIE_VSS#20

R27

PCIE_VSS#21

T25

PCIE_VSS#22

T32

PCIE_VSS#23

U25

PCIE_VSS#24

U27

PCIE_VSS#25

V32

PCIE_VSS#26

W25

PCIE_VSS#27

W26

PCIE_VSS#28

W27

PCIE_VSS#29

Y25

PCIE_VSS#30

Y32

PCIE_VSS#31

M6

GND#56

N11

GND#57

N12

GND#58

N13

GND#59

N16

GND#60

N18 N21

P6

P9 R12 R15 R17 R20 T13 T16 T18 T21

T6 U15 U17 U20

U3

U9 V13 V16 V18

V6 Y10 Y15 Y17 Y20

Y6

Title

Size Document Number Rev

B

Date: Sheet of

GND

GND#61 GND#62 GND#63 GND#64 GND#65 GND#66 GND#67 GND#68 GND#69 GND#70 GND#71 GND#72 GND#73 GND#74 GND#75 GND#76 GND#77 GND#78 GND#79 GND#80 GND#81 GND#82 GND#83 GND#84 GND#85 GND#86 GND#87

216-0728002 A11 M92-S2_FCBGA631

VSS_MECH#1 VSS_MECH#2 VSS_MECH#3

+VGASENSE[33]

VGA_CORE sense for Power Termination of VGA_CORE

Compal Electronics, Inc.

M92-S2 PWR,GND

GND#1 GND#2 GND#3 GND#4 GND#5 GND#6 GND#7 GND#8

GND#9 GND#10 GND#11 GND#12 GND#13 GND#14 GND#15 GND#16 GND#17 GND#18 GND#19 GND#20 GND#21 GND#22 GND#23 GND#24 GND#25 GND#26 GND#27 GND#28 GND#29 GND#30 GND#31 GND#32 GND#33 GND#34 GND#35 GND#36 GND#37 GND#38 GND#39 GND#40 GND#41 GND#42 GND#43 GND#44 GND#45 GND#46 GND#47 GND#48 GND#49 GND#50 GND#51 GND#52 GND#53 GND#54 GND#55

+VGA_CORE

LS-5588

A3 A30 AA13 AA16 AB10 AB15 AB6 AC9 AD6 AD8 AE7 AG12 AH10 AH28 B10 B12 B14 B16 B18 B20 B22 B24 B26 B6 B8 C1 C32 E28 F10 F12 F14 F16 F18 F2 F20 F22 F24 F26 F6 F8 G10 G27 G31 G8 H14 H17 H2 H20 H6 J27 J31 K11 K2 K22 K6

A32 AM1 AM32

+VGASENSE

R444

R444 0_0402_5%

0_0402_5%

1 2

20 35Wednesday, July 01, 2009

1

0.3

5

U65

VREFC_A1

M8

MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8

MAA9 MAA10 MAA11 MAA12

12

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

K4W1G1646E-HC12_FBGA96

VREFD_Q1

0.1U_0402_10V6K

1

C1212

2

+1.5VS

4.99K_0402_1%

VREFD_Q1

D D

BA0[19] BA1[19] BA2[19]

CLKA0[19] CLKA0#[19] CKEA0[19]

ODTA0[19] CSA0#[19] RASA#0[19] CASA#0[19] WEA#0[19]

QSA0 QSA2

DQMA#0

DRAM_RST#[19]

R912

R912 240_0402_1%

240_0402_1%

4.99K_0402_1%

DQMA#2

QSA#0 QSA#2

12

R916

R924

C C

1

C1246

0.01U_0402_25V7K

2

1

C1247

0.01U_0402_25V7K

2

MDA[0..63]

MAA[12..0]

DQMA#[7..0]

QSA[7..0]

QSA#[7..0]

MDA[0..63][19]

MAA[12..0][19]

DQMA#[7..0][19]

QSA[7..0][19]

QSA#[7..0][19]

B B

CLKA0

1 2

R932 56_0402_1%R932 56_0402_1%

CLKA0#

1 2

R934 56_0402_1%R934 56_0402_1%

CLKA1

1 2

R933 56_0402_1%R933 56_0402_1%

CLKA1#

1 2

R935 56_0402_1%R935 56_0402_1%

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

VDD VDD VDD VDD VDD VDD VDD VDD VDD

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

+1.5VS+1.5VS

R917

R925

4

MDA5

E3

MDA6

F7

MDA0

F2

MDA7

F8

MDA1

H3

MDA2

H8

MDA3

G2

MDA4

H7

MDA18

D7

MDA19

C3

MDA16

C8

MDA22

C2

MDA20

A7

MDA23

A2

MDA17

B8

MDA21

A3

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

12

C1213

10U_0603_6.3V6M

1

C1220

2

+1.5VS

R913

R913 240_0402_1%

240_0402_1%

VREFC_A1

0.1U_0402_10V6K

1

2

C1221

10U_0603_6.3V6M

12

4.99K_0402_1%

10U_0603_6.3V6M

1

C1222

2

VREFC_A2 VREFD_Q2

MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8

MAA9 MAA10 MAA11 MAA12

BA0 BA1 BA2

CLKA0 CLKA0# CKEA0

ODTA0 CSA0# RASA#0 CASA#0 WEA#0

QSA1 QSA3

DQMA#1 DQMA#3

QSA#1 QSA#3

DRAM_RST#

1

C1223

2

10U_0603_6.3V6M

R918

R926

M8 H1

N3 P7 P3 N2 P8 P2 R8 R2 T8 R3

L7 R7 N7 T3 T7 M7

M2 N8 M3

J7 K7 K9

K1

L2

J3 K3

L3

F3 C7

E7 D3

G3 B7

T2

L8

J1

L1

J9

L9

12

10U_0603_6.3V6M

1

C1224

2

3

U66

VREFCA VREFDQ

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3

BA0 BA1 BA2

CK CK CKE/CKE0

ODT/ODT0 CS/CS0 RAS CAS WE

DQSL DQSU

DML DMU

DQSL DQSU

RESET ZQ/ZQ0

NC/ODT1 NC/CS1 NC/CE1 NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

K4W1G1646E-HC12_FBGA96

VREFC_A2 VREFD_Q2 VREFD_Q3VREFC_A3

0.1U_0402_10V6K

1

C1214

2

1

C1237

2

10U_0603_6.3V6M

MDA10

E3

DQL0

MDA12

F7

DQL1

MDA8

F2

DQL2

MDA13

F8

DQL3

MDA11

H3

DQL4

MDA15

H8

DQL5

MDA9

G2

DQL6

MDA14

H7

DQL7

MDA30

D7

DQU0

MDA24

C3

DQU1

MDA31

C8

DQU2

MDA25

C2

DQU3

MDA27

A7

DQU4

MDA26

A2

DQU5

MDA28

B8

DQU6

MDA29

A3

DQU7

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

+1.5VS

A1

VDDQ

A8

VDDQ

C1

VDDQ

C9

VDDQ

D2

VDDQ

E9

VDDQ

F1

VDDQ

H2

VDDQ

H9

VDDQ

A9

VSS

B3

VSS

E1

VSS

G8

VSS

J2

VSS

J8

VSS

M1

VSS

M9

VSS

P1

VSS

P9

VSS

T1

VSS

T9

VSS

B1

VSSQ

B9

VSSQ

D1

VSSQ

D8

VSSQ

E2

VSSQ

E8

VSSQ

F9

VSSQ

G1

VSSQ

G9

VSSQ

+1.5VS+1.5VS +1.5VS+1.5VS +1.5VS+1.5VS

12

R919

4.99K_0402_1%

12

R927

C1215

1

C1289

2

10U_0603_6.3V6M

C1215

1

2

4.99K_0402_1%

10U_0603_6.3V6M

1

C1328

2

+1.5VS

R914

R914 240_0402_1%

240_0402_1%

0.1U_0402_10V6K

1

2

VREFC_A3 VREFD_Q3

MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8

MAA9 MAA10 MAA11 MAA12

BA0 BA1 BA2

CLKA1[19] CLKA1#[19] CKEA1[19]

ODTA1[19] CSA1#[19] RASA#1[19] CASA#1[19] WEA#1[19]

QSA5 QSA4

DQMA#5 DQMA#4

QSA#5 QSA#4

DRAM_RST# DRAM_RST#

12

R920

4.99K_0402_1%

R928

4.99K_0402_1%

+1.5VS

1U_0402_6.3V4Z

C1225

C1238

1

2

1U_0402_6.3V4Z

U67

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

K4W1G1646E-HC12_FBGA96

12

0.1U_0402_10V6K

1

C1216

2

1U_0402_6.3V4Z

C1240

C1241

C1239

1

2

1U_0402_6.3V4Z

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDD VDD VDD VDD VDD VDD VDD VDD VDD

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

R929

4.99K_0402_1%

1U_0402_6.3V4Z

C1226

1

2

1U_0402_6.3V4Z

E3 F7 F2 F8 H3 H8 G2 H7

D7 C3 C8 C2 A7 A2 B8 A3

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

12

R921

4.99K_0402_1%

12

C1228

C1227

1

2

1U_0402_6.3V4Z

MDA45 MDA41 MDA47 MDA40 MDA44 MDA43 MDA46 MDA42

MDA33 MDA38 MDA32 MDA39 MDA35 MDA37 MDA34 MDA36

+1.5VS

R915

R915 240_0402_1%

240_0402_1%

1

C1217

2

1U_0402_6.3V4Z

C1242

1

2

0.1U_0402_10V6K

+1.5VS

C1229

2

VREFC_A4 VREFD_Q4

BA0 BA1 BA2

CLKA1 CLKA1# CKEA1

ODTA1 CSA1# RASA#1 CASA#1 WEA#1

QSA7 QSA6

DQMA#7 DQMA#6

QSA#7 QSA#6

12

4.99K_0402_1%

1U_0402_6.3V4Z

C1230

1

2

1U_0402_6.3V4Z

MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8

MAA9 MAA10 MAA11 MAA12

C1243

1

2

1U_0402_6.3V4Z

U68

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

K4W1G1646E-HC12_FBGA96

12

R922

4.99K_0402_1%

12

R930

1U_0402_6.3V4Z

C1232

C1231

1

2

1U_0402_6.3V4Z

MDA63

E3

DQL0

MDA59

F7

DQL1

MDA60

F2

DQL2

MDA62

F8

DQL3

MDA57

H3

DQL4

MDA58

H8

DQL5

MDA56

G2

DQL6

MDA61

H7

DQL7

MDA53

D7

DQU0

MDA48

C3

DQU1

MDA55

C8

DQU2

MDA50

C2

DQU3

MDA52

A7

DQU4

MDA51

A2

DQU5

MDA54

B8

DQU6

MDA49

A3

DQU7

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

A1

VDDQ

A8

VDDQ

C1

VDDQ

C9

VDDQ

D2

VDDQ

E9

VDDQ

F1

VDDQ

H2

VDDQ

H9

VDDQ

A9

VSS

B3

VSS

E1

VSS

G8

VSS

J2

VSS

J8

VSS

M1

VSS

M9

VSS

P1

VSS

P9

VSS

T1

VSS

T9

VSS

B1

VSSQ

B9

VSSQ

D1

VSSQ

D8

VSSQ

E2

VSSQ

E8

VSSQ

F9

VSSQ

G1

VSSQ

G9

VSSQ

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

12

R923

4.99K_0402_1%

VREFC_A4 VREFD_Q4

0.1U_0402_10V6K

1

C1218

2

1U_0402_6.3V4Z

C1244

1

2

1U_0402_6.3V4Z

C1233

R931

4.99K_0402_1%

1U_0402_6.3V4Z

C1245

1

2

1U_0402_6.3V4Z

12

1U_0402_6.3V4Z

C1234

C1235

1

2

1

2

+1.5VS

0.1U_0402_10V6K

1

C1219

2

1U_0402_6.3V4Z

C1236

C1383

1

2

1U_0402_6.3V4Z

C1385

1

2

1U_0402_6.3V4Z

1

1U_0402_6.3V4Z

C1386

C1388

1

2

1U_0402_6.3V4Z

C1384

C1387

1

2

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/04/20 2010/04/30

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

C

VRAM DDR3

LS-5588

1

0.3

21 35Wednesday, July 01, 2009

0.3

5

+3VS

1 2

R159 8.2K_0402_5%

1 2

R160 8.2K_0402_5%

1 2

R161 8.2K_0402_5%

1 2

R162 8.2K_0402_5%

D D

C C

1 2

R163 8.2K_0402_5%

1 2

R164 8.2K_0402_5%

1 2

R165 8.2K_0402_5%

1 2

R166 8.2K_0402_5%

+3VS

1 2

R167 8.2K_0402_5%

1 2

R168 8.2K_0402_5%

1 2

R169 8.2K_0402_5%

1 2

R170 8.2K_0402_5%

1 2

R171 8.2K_0402_5%

1 2

R172 47K_0402_5%R172 47K_0402_5%

1 2

R173 8.2K_0402_5%

R173 8.2K_0402_5% R174 8.2K_0402_5%

R174 8.2K_0402_5%

1 2

R175 8.2K_0402_5%

1 2

R176 8.2K_0402_5%

1 2

R178 8.2K_0402_5%R178 8.2K_0402_5%

1 2

R179 8.2K_0402_5%

12

PCI_DEVSEL# PCI_STOP# PCI_TRDY# PCI_FRAME# PCI_PLOCK# PCI_IRDY# PCI_SERR# PCI_PERR#

PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD# PCI_PIRQE# PCI_PIRQF# PCI_PIRQG# PCI_PIRQH# PCI_REQ0# PCI_REQ1# PCI_REQ2# PCI_REQ3#

4

U5B

A11

AD0

PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD#

B12 A10 C12

A12 E10 C11

D11

PCI

AD1 AD2 AD3

A8

AD4 AD5 AD6 AD7

B9

AD8

D8

AD9

A4

AD10

E8

AD11

A3

AD12

D9

AD13

C8

AD14

C2

AD15

D7

AD16

B3

AD17 AD18

B6

AD19

D5

AD20

D3

AD21

F4

AD22

E3

AD23

E4

AD24

B2

AD25

C4

AD26

C1

AD27

D1

AD28

E2

AD29

J4

AD30

H2

AD31

Interrupt I/F

F1

PIRQA#

F5

PIRQB#

F2

PIRQC#

C7

PIRQD#

ICH9-M SFF ES_FCBGA569

REQ0#

GNT0# REQ1#/GPIO50 GNT1#/GPIO51 REQ2#/GPIO52 GNT2#/GPIO53 REQ3#/GPIO54 GNT3#/GPIO55

C/BE0# C/BE1# C/BE2# C/BE3#

IRDY#

PCIRST#

DEVSEL#

PERR#

PLOCK#

SERR# STOP#

TRDY#

FRAME#

PLTRST#

PCICLK

PME#

PIRQE#/GPIO2 PIRQF#/GPIO3 PIRQG#/GPIO4 PIRQH#/GPIO5

PAR

3

PCI_REQ0#

G4

PCI_GNT0#

E1

PCI_REQ1#

A9 E12

PCI_REQ2#

B11 C10

PCI_REQ3#

D6

PCI_GNT3#

C6 D10

A5 E6 C9

PCI_IRDY#

C3 B1 T3

PCI_DEVSEL#

A7

PCI_PERR#

D4

PCI_PLOCK#

C5

PCI_SERR#

H5

PCI_STOP#

A6

PCI_TRDY#

A2

PCI_FRAME#

B8

PLT_RST#

A21 B5 T1

G3 G1 F3 H4

CLK_PCI_ICH PCI_PME#

PCI_PIRQE# PCI_PIRQF# PCI_PIRQG# PCI_PIRQH#

PLT_RST# [8,17,26] CLK_PCI_ICH [16] PCI_PME# [26]

2

1

B B

PCI_GNT3#

A A

A16 swap override Strap

Low= A16 swap override Enble High= Default

PCI_GNT3#

5

*

12

R181

1K_0402_5%@

Boot BIOS Strap

PCI_GNT0# SPI_CS#1

12

R182

R182 1K_0402_5%

1K_0402_5%

@

1

0

1

0

1

PCI_GNT0#

DEL J3. 9/29

4

Boot BIOS Location

SPI

PCI

LPC

*

KBC_SPI_CS1#[24]

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

Place closely pin B10

CLK_PCI_ICH

12

R183

1K_0402_5%@

2009/04/20 2010/04/30

12

@

R180

R180 10_0402_5%

10_0402_5%

1

@

C235

8.2P_0402_50V

2

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

ICH9(1/4)-PCI/INT

LS-5588

22 35Wednesday, July 01, 2009

1

0.3

+RTCVCC

R184 330K_0402_1%

1 2

R185 1M_0402_5%R185 1M_0402_5%

1 2

R186 330K_0402_1%R186 330K_0402_1%

1 2

R187 20K_0402_5%

Change from 180K to 20K & 0.1u to 1u. 9/29

D D

5

1 2

LAN100_SLP SM_INTRUDER# ICH_INTVRMEN ICH_SRTCRST#

C236

1U_0603_10V4Z

R189

R188

1

2

@

1 2

0_0402_5%

@

1 2

0_0402_5%

+RTCVCC

1

C1250

2.2U_0603_6.3V4Z

2

4

3

2

1

ICH_RSVDHDA_SDOUT_CODEC

0 0 0 1 1 1

XOR CHAIN ENTRANCE STRAP:RSVD

+3VS

1 2

R191 1K_0402_5%@R191 1K_0402_5%@

1 2

R193 1K_0402_5%@R193 1K_0402_5%@

C C

Remove R227 & C199

B B

1 0

HDA_SDOUT ICH_RSVD

Add C599 ~ C602 to solve WWAN noise issue. 1/23

Description

RV

XOR Normal(D) PCIE Bit1

ICH_RSVD [24]

ICH_RTCRST#[26]

U5A

ICH_RTCX1

R318

IDE_LED#[26]

1 2

20K_0402_5%

HDA_BITCLK[26] HDA_SYNC[26]

HDA_RST#[26]

HDA_SDIN0[26] HDA_SDIN1[26]

SATA_RXN0_C SATA_RXP0_C SATA_TXN0_CR SATA_TXP0_CR

SATA_RXN1_C SATA_RXP1_C SATA_TXN1_CR SATA_TXP1_CR

C1044

1U_0603_10V4Z

R198 24.9_0402_1% R198 24.9_0402_1%

+1.5VS

HDA_SDOUT[26]

+3VS

R209 10K_0402_5% R209 10K_0402_5%

C1079 0.01U_0402_16V7KC1079 0.01U_0402_16V7K C1080 0.01U_0402_16V7KC1080 0.01U_0402_16V7K

C1081 0.01U_0402_16V7KC1081 0.01U_0402_16V7K C1082 0.01U_0402_16V7KC1082 0.01U_0402_16V7K

+RTCVCC

SATA_RXN0_C[26]

SATA_RXP0_C[26] SATA_TXN0_CR[26] SATA_TXP0_CR[26]

SATA_RXN1_C[26]

SATA_RXP1_C[26] SATA_TXN1_CR[26] SATA_TXP1_CR[26]

1

2

HDA_BITCLK

HDA_SDIN2

ICH_RTCRST#

12

1 2

12

1 2 1 2

CLRP1

CLRP1 SHORT PADS

SHORT PADS

ICH_RTCX2

ICH_SRTCRST# SM_INTRUDER#

ICH_INTVRMEN LAN100_SLP

T47PAD T47PAD

GLAN_COMP

R1007 0_0402_5%R1007 0_0402_5%

HDA_SDOUT

T49PAD T49PAD

SATA_TXN0_R SATA_TXP0_R

SATA_TXN1_R SATA_TXP1_R

HDA_SYNC HDA_RST#

U5A

F25

RTCX1

G25

RTCX2

G24

RTCRST#

C24

SRTCRST#

C23

INTRUDER#

E25

INTVRMEN

D25

LAN100_SLP

G22

GLAN_CLK

D14

LAN_RSTSYNC

A14

LAN_RXD0

D12

LAN_RXD1

B14

LAN_RXD2

D13

LAN_TXD0

C13

LAN_TXD1

A13

LAN_TXD2

D15

GPIO56

H22

GLAN_COMPI

H21

GLAN_COMPO

AE7

HDA_BIT_CLK

AB7

HDA_SYNC

AA7

HDA_RST#

AB6

HDA_SDIN0

AE6

HDA_SDIN1

AC6

HDA_SDIN2

AA5

HDA_SDIN3

AC7

HDA_SDOUT

AD8

HDA_DOCK_EN#/GPIO33

AB8

HDA_DOCK_RST#/GPIO34

AC9

SATALED#

AE14

SATA0RXN

AD14

SATA0RXP

AC15

SATA0TXN

AD15

SATA0TXP

AD13

SATA1RXN

AC13

SATA1RXP

AA14

SATA1TXN

AB14

SATA1TXP

ICH9-M SFF ES_FCBGA569

RTCLAN / GLANIHDASATA

FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3

FWH4/LFRAME#

LPCCPU

LDRQ1#/GPIO23

CPUPWRGD

THRMTRIP#

SATA4RXN SATA4RXP SATA4TXN SATA4TXP

SATA5RXN SATA5RXP SATA5TXN SATA5TXP

SATA_CLKN SATA_CLKP

SATARBIAS#

SATARBIAS

C24615P_0402_50V8J C24615P_0402_50V8J

1

2

LDRQ0#

A20GATE

A20M#

DPRSTP#

DPSLP#

FERR#

IGNNE#

INIT# INTR

RCIN#

SMI#

STPCLK#

TP11

10M_0402_5%

NMI

1 2

1 4 2 3

R215

LPC_AD0

H3

LPC_AD1

J3

LPC_AD2

K5

LPC_AD3

L3 J2 H1

J1

GATEA20

N3 AB23

H_DPRSTP_R#

AE23 AE24

H_FERR#_R

AD25 AE22 AD23 AE21

AD24

KB_RST#

L1 AD21

H_SMI#

AC21

H_STPCLK#

AC25

THRMTRIP_ICH#

AC23 AC22

T48 PADT48 PAD

AD12 AE12

SATA_TXN2_R

AB12

SATA_TXP2_R

AA12 AC11

AD11 AB10 AA10

CLK_PCIE_SATA#

AC16

CLK_PCIE_SATA

AB16 AD10

R212 24.9_0402_1%

AE10

Within 500 mils

ICH_RTCX1

ICH_RTCX2

C24715P_0402_50V8J C24715P_0402_50V8J

1

Y2

2

32.768KHZ_12.5P_MC-146

LPC_AD[0..3] [26]

LPC_FRAME# [26]

T46PADT46PAD

GATEA20 [26] H_A20M# [4]

R194 0_0402_5% R194 0_0402_5%

1 2

H_DPSLP# [5]

R195 56_0402_5%R195 56_0402_5%

1 2

H_PWRGOOD [5] H_IGNNE# [4] H_INIT# [4]

H_INTR [4]

KB_RST# [26]

H_NMI [4] H_SMI# [4]

H_STPCLK# [4]

R206 54.9_0402_1%R206 54.9_0402_1%

1 2

placed within 2" from ICH9M

1 2 1 2

C1083

0.01U_0402_16V7K

CLK_PCIE_SATA# [16] CLK_PCIE_SATA [16]

1 2

C1084

0.01U_0402_16V7K

9/27

for H_DPRSTP# & H_DPSLP#.

H_DPRSTP# [5,8,31]

H_FERR#

Place Close to U8.

+VCCP

12

R201

R201 56_0402_5%

56_0402_5%

SATA_RXN2_C

SATA_RXP2_C SATA_TXN2_CR SATA_TXP2_CR

9/27Del PU R203~R204

GATEA20 KB_RST#

H_THERMTRIP# [4,8]

SATA_RXN2_C [26] SATA_RXP2_C [26] SATA_TXN2_CR [26] SATA_TXP2_CR [26]

+VCCP

R192

R192 56_0402_5%

56_0402_5%

1 2

H_FERR# [4]

R196 10K_0402_5%R196 10K_0402_5%

1 2

R197 10K_0402_5%R197 10K_0402_5%

1 2

+3VS

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/04/20 2010/04/30

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

ICH9(2/4)_LAN,HD,IDE,LPC

LS-5588

1

0.3

23 35Wednesday, July 01, 2009

0.3

PM_CLKRUN#

THERM_SCI#

GPIO22

NPCI_RST#

GPIO17

GPIO37 GPIO18 GPIO57

LINKALERT# PCIE_WAKE# EC_SWI# XDP_DBRESET# S4_STATE# ICH_LOW_BAT#

GPIO24 AC_IN ME__EC_CLK1 ME__EC_DATA1

USB_OC#7 USB_OC#5 USB_OC#0 USB_OC#4

USB_OC#1 USB_OC#6 GPIO44 USB_OC#2

LID_SW# GPIO42 WOL_EN

USB_OC#9 USB_OC#10 USB_OC#11

1 2 1 2 1 2 1 2

5

GPIO48 GPIO1 SIRQ

2.2K_0402_5%

ICH_SMBDATA

GPIO38 GPIO21 HDD_HALTLED GPIO39

5

R274

+3VS

Add R621 in 12/03.

+3VS

12

R275

12

2.2K_0402_5%

S

G

H_STP_PCI#[16] H_STP_CPU#[16]

Q8

Q8 RHU002N06_SOT323

RHU002N06_SOT323

D

13

S

2

G

2

VGATE[26,31]

D

13

9/21

+3VS

R235

10K_0402_5%@

R264 1K_0402_5%@R264 1K_0402_5%@

+3VS

ICH_SMB_DATA ICH_SMB_CLKICH_SMBCLK

Q9

Q9 RHU002N06_SOT323

RHU002N06_SOT323

12

R236

R247 0_0402_5% R247 0_0402_5% R248 100K_0402_5% R248 100K_0402_5%

GPIO1[26] GPIO6[26]

1 2

KBC_SPI_CS1#[22]

+3VS

1 2

R271 10K_0402_5%R271 10K_0402_5%

1 2

R220 10K_0402_5%

1 2

R222 10K_0402_5%

1 2

R225 8.2K_0402_5%

1 2

R227 8.2K_0402_5%@ R227 8.2K_0402_5%@

1 2

R231 8.2K_0402_5%

D D

C C

B B

A A

1 2

R232 10K_0402_5%

1 2

R233 8.2K_0402_5%@ R233 8.2K_0402_5%@

1 2

R237 8.2K_0402_5%

1 2

R238 10K_0402_5%

1 2

R239 10K_0402_5%@ R239 10K_0402_5%@

+3VALW

1 2

R244 10K_0402_5%R244 10K_0402_5%

1 2

R245 10K_0402_5%

1 2

R246 10K_0402_5%

1 2

R250 1K_0402_5%R250 1K_0402_5%

1 2

R252 10K_0402_5%@R252 10K_0402_5%@

1 2

R254 10K_0402_5%

Add R321 in 10/03.

1 2

R256 10K_0402_5%R256 10K_0402_5%

1 2

R258 100K_0402_5%@R258 100K_0402_5%@

1 2

R259 10K_0402_5%R259 10K_0402_5%

1 2

R261 10K_0402_5%R261 10K_0402_5%

+3VALW

RP29

10K_1206_8P4R_5%

RP30

10K_1206_8P4R_5%

1 2

R269 10K_0402_5%R269 10K_0402_5%

1 2

R270 10K_0402_5%R270 10K_0402_5%

1 2

R277 10K_0402_5%R277 10K_0402_5%

1 2

R278 10K_0402_5%R278 10K_0402_5%

1 2

R279 10K_0402_5%R279 10K_0402_5%

1 2

R280 10K_0402_5%R280 10K_0402_5%

ICH_SMBDATA[14,15,16,26]

ICH_SMBCLK[14,15,16,26]

+3VS

R262 8.2K_0402_5% R262 8.2K_0402_5%

R03

R255 8.2K_0402_5%R255 8.2K_0402_5% R230 47K_0402_5%R230 47K_0402_5% R249 8.2K_0402_5%@R249 8.2K_0402_5%@

45 36 27 18

1 2 1 2 1 2 1 2

R281 10K_0402_5%@ R281 10K_0402_5%@ R282 10K_0402_5%@ R282 10K_0402_5%@ R242 47K_0402_5%@ R242 47K_0402_5%@ R285 10K_0402_5%@ R285 10K_0402_5%@

4

2.2K_0402_5%

XDP_DBRESET#[4]

10K_0402_5%@

GPIO48[26]

PM_BMBUSY#[8]

R445 0_0402_5%R445 0_0402_5%

1 2

R240 0_0402_5%R240 0_0402_5%

1 2

PCIE_WAKE#[26]

THERM_SCI#[26]

1 2 1 2

EC_SMI#[26] EC_SCI#[26]

R03

CLKSATAREQ#[16]

SB_SPKR[26]

MCH_ICH_SYNC#[8]

ICH_RSVD[23]

GLAN_RXN[26] GLAN_RXP[26] GLAN_TXN[26]

GLAN_TXP[26]

PCIE_RXN2[26] PCIE_RXP2[26] PCIE_TXN2[26]

PCIE_TXP2[26]

PCIE_RXN4[26] PCIE_RXP4[26] PCIE_TXN4[26]

PCIE_TXP4[26]

GPIO42[26]

GPIO44[26]

4

12

R223

EC_SWI#[26]

LID_SW#[26]

SIRQ[26]

PAD

T51

PAD

T65

T52PAD T52PAD T53PAD T53PAD

T54PAD T54PAD

T55PAD T55PAD

T59PAD T59PAD

C271 0.1U_0402_10V7K C271 0.1U_0402_10V7K

1 2

C272 0.1U_0402_10V7K C272 0.1U_0402_10V7K

1 2

C265 0.1U_0402_10V7K

1 2

C266 0.1U_0402_10V7K

1 2

C269 0.1U_0402_10V7K

1 2

C270 0.1U_0402_10V7K

1 2

USB_OC#0[26] USB_OC#1[26] USB_OC#2[26]

+3VALW

12

R224

2.2K_0402_5%

ICH_SMB_CLK ICH_SMB_DATA LINKALERT# ME__EC_CLK1 ME__EC_DATA1

EC_SWI#

XDP_DBRESET# PM_BMBUSY# LID_SW# H_STP_PCI#_R

R_STP_CPU# PM_CLKRUN# PCIE_WAKE#

SIRQ THERM_SCI#

VRMPWRGD

GPIO22

GPIO38 GPIO39 GPIO48

GPIO57

SB_SPKR MCH_ICH_SYNC# ICH_RSVD

GPIO1 GPIO6

GPIO17 GPIO18

12

R287

22.6_0402_1%

U5C

C18

SMBCLK

C15

SMBDATA

B21

LINKALERT#/GPIO60/CLGPIO4

E18

SMLINK0

A24

SMLINK1

C20

RI#

T5

SUS_STAT#/LPCPD#

C25

SYS_RESET#

L2

PMSYNC#/GPIO0

A23

SMBALERT#/GPIO11

B15

STP_PCI#/GPIO15

A20

STP_CPU#/GPIO25

M5

CLKRUN#/GPIO32

C21

WAKE#

L4

SERIRQ

AD20

THRM#

B24

VRMPWRGD

A19

TP12

AE16

GPIO1

AE18

GPIO6

AD18

GPIO7

B25

GPIO8

C14

GPIO12

D20

GPIO13

AE17

GPIO17

K3

GPIO18

AC8

GPIO20

AC19

SCLOCK/GPIO22

D17

GPIO27

E20

GPIO28

M4

SATACLKREQ#/GPIO35

AB18

SLOAD/GPIO38

AC18

SDATAOUT0/GPIO39

AB19

SDATAOUT1/GPIO48

AC20

GPIO49

A16

GPIO57/CLGPIO5

K4

SPKR

AB20

MCH_SYNC#

C19

TP3

AB17

TP8

AC17

TP9

AD17

TP10

ICH9-M SFF ES_FCBGA569

GLAN_RXN GLAN_RXP GLAN_TXN_C GLAN_TXP_C

PCIE_RXN2 PCIE_RXP2 PCIE_C_TXN2 PCIE_C_TXP2

PCIE_RXN4 PCIE_RXP4 PCIE_C_TXN4 PCIE_C_TXP4

USB_OC#0 USB_OC#1 USB_OC#2 GPIO42 USB_OC#4 USB_OC#5 USB_OC#6 USB_OC#7 GPIO44 USB_OC#9 USB_OC#10 USB_OC#11

USBRBIAS

Within 500 mils

3

GPIO21

CLK14 CLK48

SUSCLK

SLP_S3# SLP_S4# SLP_S5#

PWROK

BATLOW# PWRBTN#

LAN_RST#

RSMRST#

CK_PWRGD

CLPWROK

SLP_M#

CL_CLK0 CL_CLK1

CL_DATA0 CL_DATA1

CL_VREF0 CL_VREF1

CL_RST0# CL_RST1#

AE19

HDD_HALTLED

AA18

NPCI_RST#

AE20

GPIO37

AA20

CLK_14M_ICH

K1

CLK_48M_ICH

AB5

ICH_SUSCLK

R3

SLP_S3#

D18

SLP_S4#

B20

SLP_S5#

D16

S4_STATE#

E14 D23

DPRSLPVR

M1

ICH_LOW_BAT#

C16 U4

LAN_RST

D22

EC_RSMRST#R

D19

CK_PWRGD_R

U1

M_PWROK

T4 B23

CL_CLK0

C22 A18

CL_DATA0

E22 B18

CL_VREF0_ICH

F21 A17

CL_RST#

C17 B17

GPIO24

A22 E16

AC_IN

A15

WOL_EN

D21

Add WOL_EN back. 10/10

DMI_RXN0

V25

DMI_RXP0

V24

DMI_TXN0

U24

DMI_TXP0

U23

DMI_RXN1

W23

DMI_RXP1

W24

DMI_TXN1

V21

DMI_TXP1

V22

DMI_RXN2

Y24

DMI_RXP2

Y25

DMI_TXN2

Y21

DMI_TXP2

Y22

DMI_RXN3

AB24

DMI_RXP3

AB25

DMI_TXN3

AA23

DMI_TXP3

AA24

CLK_PCIE_ICH#

T21

CLK_PCIE_ICH

T22 AB21

AB22 AE2

AD1 AD3 AD4 AC2 AC3 AC5 AB4 AB2 AB1 AA3 AA2 Y1 Y2 W2 W3 V1 V2 Y5 Y4 U3 U2 V4 V5

DMI_IRCOMP

Compal Secret Data

Deciphered Date

R243 0_0402_5%R243 0_0402_5%

R253 0_0402_5%R253 0_0402_5%

SATA0GP/GPIO21 SATA1GP/GPIO19 SATA4GP/GPIO36 SATA5GP/GPIO37

GPIO

SATA

SMBSYS GPIO

Clocks

S4_STATE#/GPIO26

DPRSLPVR/GPIO16

Power MGTController Link

GPIO

MEM_LED/GPIO24

GPIO10/SUS_PWR_ACK

GPIO14/AC_PRESENT

WOL_EN/GPIO9

MISC

U5D

T25

PERN1

T24

PERP1

R24

PETN1

R23

PETP1

P25

PERN2

P24

PERP2

P21

WLAN

PETN2

P22

PETP2

N23

PERN3

N24

PERP3

M21

EXP

PETN3

M22

PETP3

M25

PERN4

M24

PERP4

L24

WWAN

PETN4

L23

PETP4

K24

PERN5

K25

PERP5

K21

PETN5

K22

PETP5

H24

PERN6/GLAN_RXN

H25

PERP6/GLAN_RXP

J24

PETN6/GLAN_TXN

J23

PETP6/GLAN_TXP

E24

SPI_CLK

E23

SPI_CS0#

F23

SPI_CS1#/GPIO58/CLGPIO6

F22

SPI_MOSI

G23

SPI_MISO

P4

OC0#/GPIO59

N4

OC1#/GPIO40

N1

OC2#/GPIO41

P5

OC3#/GPIO42

P1

OC4#/GPIO43

P2

OC5#/GPIO29

M3

OC6#/GPIO30

M2

OC7#/GPIO31

P3

OC8#/GPIO44

R1

OC9#/GPIO45

R4

OC10#/GPIO46

R2

OC11#/GPIO47

AE5

USBRBIAS

AD5

USBRBIAS#

ICH9-M SFF ES_FCBGA569

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

DMI0RXN DMI0RXP

DMI0TXN DMI0TXP

DMI1RXN DMI1RXP

DMI1TXN DMI1TXP

DMI2RXN DMI2RXP

DMI2TXN DMI2TXP

DMI3RXN DMI3RXP

DMI3TXN DMI3TXP

DMI_CLKN

PCI-Express

DMI_CLKP

Direct Media Interface

DMI_ZCOMP

DMI_IRCOMP

USBP0N USBP0P USBP1N

GLAN

USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N

SPI

USBP5P USBP6N

USB

USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N

USBP9P USBP10N USBP10P USBP11N USBP11P

2009/04/20 2010/04/30

CLK_14M_ICH [16] CLK_48M_ICH [16]

T50 PADT50 PAD

SLP_S3# [26] SLP_S4# [26] SLP_S5# [26]

R241 100K_0402_5% R241 100K_0402_5%

1 2

ON/OFFBTN# [26]

R251 10K_0402_5%R251 10K_0402_5%

1 2

M_PWROK [8]

CL_CLK0 [8]

CL_DATA0 [8]

CL_RST# [8]

GPIO24 [26] AC_IN [26]

DMI_RXN0 [8] DMI_RXP0 [8] DMI_TXN0 [8] DMI_TXP0 [8]

DMI_RXN1 [8] DMI_RXP1 [8] DMI_TXN1 [8] DMI_TXP1 [8]

DMI_RXN2 [8] DMI_RXP2 [8] DMI_TXN2 [8] DMI_TXP2 [8]

DMI_RXN3 [8] DMI_RXP3 [8] DMI_TXN3 [8] DMI_TXP3 [8]

CLK_PCIE_ICH# [16] CLK_PCIE_ICH [16]

R276 24.9_0402_1% R276 24.9_0402_1%

USB20_N0 [26] USB20_P0 [26] USB20_N1 [26] USB20_P1 [26] USB20_N2 [26] USB20_P2 [26] USB20_N3 [26] USB20_P3 [26] USB20_N4 [26] USB20_P4 [26] USB20_N5 [26] USB20_P5 [26] USB20_N6 [26] USB20_P6 [26] USB20_N7 [26] USB20_P7 [26] USB20_N8 [26] USB20_P8 [26]

2

1 2

2

PM_PWROK [8,26,31]

PM_DPRSLPVR [8,31]

CK_PWRGD [16]

1

2

C263

0.1U_0402_16V4Z

EC_RSMRST#[26]

Within 500 mils

1

LAN_RST

M_PWROKPM_PWROK

12

R27310K_0402_5% R27310K_0402_5%

1 2

12

R260

453_0402_1%

R257

3.24K_0402_1%

1 2

R221 0_0402_5%R221 0_0402_5%

+3VS

RSMRST circuit

R454

@R454

@

0_0402_5%

1 2

C

EC_RSMRST#R

123

E

Q26

BAV99DW-7_SOT363

5

D13B

@

R456

2.2K_0402_5%

1 2

R457

1 2

2.2K_0402_5%

+1.5VS

12

@

R283

R283 10_0402_5%

10_0402_5%

@

1

C273

4.7P_0402_50V8C

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

ICH9(3/4)_DMI,USB,GPIO,PCIE

LS-5588

Q26 MMBT3906_SOT23-3

MMBT3906_SOT23-3

B

1 2

R455 4.7K_0402_5%R455 4.7K_0402_5%

4

1

2

D13A

D13A BAV99DW-7_SOT363

BAV99DW-7_SOT363

3

6

Place closely pin H1Place closely pin AF3

CLK_14M_ICHCLK_48M_ICH

12

@

R284

R284 10_0402_5%

10_0402_5%

@

1

C274

4.7P_0402_50V8C

2

24 35Wednesday, July 01, 2009

1

0518/'09

+3VALW

0.3

5

+RTCVCC

C275

R289

21

1

2

1 2

BLM18PG181SN1D_0603

D5

D5 CH751H-40_SC76

CH751H-40_SC76

ICH_V5REF_RUN

20 mils

C291

C291 1U_0402_6.3V6K

1U_0402_6.3V6K

R296

1 2

MBK1608301YZF 0603

1U_0402_6.3V6K

D D

C C

+1.5VS

+5VS +3VS +3VALW+5VALW

12

R293

100_0402_5%

9/19

+1.5VS

1

2

0.1U_0402_16V4Z

1

C296

2

1

C276

2

1

+

2

C282

220U_D2_4VM_R15

R294

100_0402_5%

1

2

C297

20 mils

+1.5VS_PCIE_ICH

0.1U_0402_16V4Z

40 mils

1

2

C279

C280

10U_0603_6.3V6M

12

+1.5VS

10U_0603_6.3V6M

ICH_V5REF_RUN ICH_V5REF_SUS

1

2

C281

2.2U_0402_6.3V6M

21

D6

D6 CH751H-40_SC76

CH751H-40_SC76

ICH_V5REF_SUS

20 mils

1

C292

0.1U_0402_16V4Z

2

+1.5VS_VCCSATAPLL

C298

1U_0603_10V4Z

1

2

1

2

C299

1U_0603_10V4Z

B B

+1.5VS_USBPLL

R298

1 2

+1.5VS

MBK1608301YZF 0603

+3VS

R303

1 2

MBK1608301YZF 0603

A A

0.1U_0402_16V4Z

1

2

C308

C307

C306

0.1U_0402_16V4Z

+1.5VS

1

2

C309

5

0.1U_0402_16V4Z

R304

R304 MBK1608301YZF 0603

MBK1608301YZF 0603

1 2

0.1U_0402_16V4Z

12

1

2

C310

+1.5VS_PCIE_ICH

10U_0603_6.3V6M

1

2

C303

0.1U_0402_16V4Z

VCC_LAN1_05_INT_ICH

+1.5VS_GLAN

1

2

C311

10U_0603_6.3V6M

+3VS

4

U5F

G17

VCCRTC

G7

V5REF

U7

V5REF_SUS

J19

VCC1_5_B[01]

K18

VCC1_5_B[02]

K19

VCC1_5_B[03]

L18

VCC1_5_B[04]

L19

VCC1_5_B[05]

M18

VCC1_5_B[06]

M19

VCC1_5_B[07]

N18

VCC1_5_B[08]

N19

VCC1_5_B[09]

P18

VCC1_5_B[10]

R18

VCC1_5_B[11]

T18

VCC1_5_B[12]

T19

VCC1_5_B[13]

U18

VCC1_5_B[14]

U19

VCC1_5_B[15]

W17

VCCSATAPLL

U13

VCC1_5_A[01]

V13

VCC1_5_A[02]

W13

VCC1_5_A[03]

U12

VCC1_5_A[04]

V12

VCC1_5_A[05]

W12

VCC1_5_A[06]

W10

VCC1_5_A[07]

U15

VCC1_5_A[08]

V15

VCC1_5_A[09]

W18

VCC1_5_A[10]

G9

VCC1_5_A[11]

H9

VCC1_5_A[12]

V11

VCC1_5_A[13]

U11

VCC1_5_A[14]

U8

VCCUSBPLL

T9

VCC1_5_A[15]

U9

VCC1_5_A[16]

G11

VCCLAN1_05[1]

H11

VCCLAN1_05[2]

G12

VCCLAN3_3[1]

H13

VCCLAN3_3[2]

J17

VCCGLANPLL

H19

VCCGLAN1_5[1]

J18

VCCGLAN1_5[2]

K16

VCCGLAN3_3

ICH9-M SFF ES_FCBGA569

4

CORE

VCCA3GP ATXARX USB CORE

VCCP_CORE

PCI

VCCSUS1_05[1] VCCSUS1_05[2]

VCCSUS1_5[1] VCCSUS1_5[2]

VCCSUS3_3[01] VCCSUS3_3[02] VCCSUS3_3[03]

VCCPSUSVCCPUSB

VCCSUS3_3[04] VCCSUS3_3[05]

VCCSUS3_3[06] VCCSUS3_3[07] VCCSUS3_3[08] VCCSUS3_3[09] VCCSUS3_3[10] VCCSUS3_3[11] VCCSUS3_3[12] VCCSUS3_3[13] VCCSUS3_3[14] VCCSUS3_3[15] VCCSUS3_3[16]

GLAN POWER

VCC1_05[01] VCC1_05[02] VCC1_05[03] VCC1_05[04] VCC1_05[05] VCC1_05[06] VCC1_05[07] VCC1_05[08] VCC1_05[09] VCC1_05[10] VCC1_05[11] VCC1_05[12] VCC1_05[13] VCC1_05[14] VCC1_05[15] VCC1_05[16]

VCCDMIPLL

VCC_DMI[1] VCC_DMI[2]

V_CPU_IO[1] V_CPU_IO[2]

VCC3_3[01] VCC3_3[02]

VCC3_3[03] VCC3_3[04] VCC3_3[05]

VCC3_3[06] VCC3_3[07] VCC3_3[08]

VCCHDA

VCCSUSHDA

VCCCL1_05

VCCCL1_5

VCCCL3_3[1] VCCCL3_3[2]

1

2

C277

0.1U_0402_16V4Z

9/29

VCC_DMI

(DMI)

+3VS

1

2

C293

+3VALW

C304

0.1U_0402_16V4Z

1 2

+3VS

Issued Date

0.1U_0402_16V4Z

C283

0.01U_0402_16V7K

0.1U_0402_16V4Z

T60T60

T61T61 T62T62 T63T63

C302

4.7U_0603_6.3V6K

1

2

C278

1

2

1

2

9/21

3

1U_0603_10V4Z

9/21

3

R290

1 2

MBK1608301YZF 0603

1

2

C284

R292

1 2

MBK1608301YZF 0603

0.1U_0402_16V4Z

1

2

C290

C289

C288

R03

R319 180_0402_1%@ R319 180_0402_1%@

1 2

12

@

1

2

C295

0.1U_0402_16V4Z

1 2

R325 0_0603_5%R325 0_0603_5%

R320

R320 150_0402_1%

150_0402_1%

+3VALW

1

2

C300

C301

0.1U_0402_16V4Z

2009/04/20 2010/04/30

9/29

+1.5VS

VCC_DMI

1

2

C285

1U_0603_10V4Z

9/29

+3VS

R323 0_0603_5%R323 0_0603_5% R324 0_0603_5%@R324 0_0603_5%@

1U_0603_10V4Z

+VCCP

0.1U_0402_16V4Z

1 2 1 2

+3VALW +3VALW

+1.5VALW

Compal Secret Data

Deciphered Date

1

2

C286

+VCCP

1

2

C287

4.7U_0603_6.3V6K

C294

0.1U_0402_16V4Z

+3VS +1.5VS

1

2

+VCCP

L11 L12 L13 L14 L15 M11 M15 N11 N15 P11 P15 R11 R12 R13 R14 R15

+1.5VS_DMIPLL

P19 T17

U17 V16

U16 V18 AE9

AA9 V14 W14

G8 H7 H8

AD7 V10

VCCSUS1_05_ICH_1

T7

VCCSUS1_05_ICH_2

H15

VCCSUS1_5_ICH_1

H16

VCCSUS1_5_ICH_2

V7

G14 G15 H14

W8 J7

J8 K7 K8 L7 L8 M7 M8 N7 N8 P7 P8

VCCCL1_05_ICH

G18

1 2

H17

C305 1U_0402_6.3V6K

J14 K14

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

U5E

B4

VSS[001]

B7

VSS[002]

B10

VSS[003]

B13

VSS[004]

B16

VSS[005]

B19

VSS[006]

B22

VSS[007]

D2

VSS[008]

D24

VSS[009]

E5

VSS[010]

E7

VSS[011]

E9

VSS[012]

E11

VSS[013]

E13

VSS[014]

E15

VSS[015]

E17

VSS[016]

E19

VSS[017]

E21

VSS[018]

F24

VSS[019]

G2

VSS[020]

G5

VSS[021]

G10

VSS[022]

G13

VSS[023]

G16

VSS[024]

G19

VSS[025]

G21

VSS[026]

H10

VSS[027]

H12

VSS[028]

H18

VSS[029]

H23

VSS[030]

J5

VSS[031]

J9

VSS[032]

J10

VSS[033]

J11

VSS[034]

J12

VSS[035]

J13

VSS[036]

J15

VSS[037]

J21

VSS[038]

J22

VSS[039]

J25

VSS[040]

K2

VSS[041]

K9

VSS[042]

K10

VSS[043]

K11

VSS[044]

K12

VSS[045]

K13

VSS[046]

K15

VSS[047]

K17

VSS[048]

K23

VSS[049]

L5

VSS[050]

L9

VSS[051]

L10

VSS[052]

L16

VSS[053]

L17

VSS[054]

L21

VSS[055]

L22

VSS[056]

L25

VSS[057]

M9

VSS[058]

M10

VSS[059]

M12

VSS[060]

M13

VSS[061]

M14

VSS[062]

M16

VSS[063]

M17

VSS[064]

M23

VSS[065]

N2

VSS[066]

N5

VSS[067]

N9

VSS[068]

N10

VSS[069]

N12

VSS[070]

N13

VSS[071]

N14

VSS[072]

N16

VSS[073]

N17

VSS[074]

N21

VSS[075]

N22

VSS[076]

N25

VSS[077]

P9

VSS[078]

P10

VSS[079]

P12

VSS[080]

P13

VSS[081]

P14

VSS[082]

P16

VSS[083]

P17

VSS[084]

P23

VSS[085]

R5

VSS[086]

R7

VSS[087]

R8

VSS[088]

R9

VSS[089]

R10

VSS[090]

R16

VSS[091]

R17

VSS[092]

R19

VSS[093]

R21

VSS[094]

R22

VSS[095]

R25

VSS[096]

T2

VSS[097]

T8

VSS[098]

T10

VSS[099]

T11

VSS[100]

T12

VSS[101]

T13

VSS[102]

T14

VSS[103]

T15

VSS[104]

T16

VSS[105]

T23

VSS[106]

ICH9-M SFF ES_FCBGA569

2

1

U5

VSS[107]

U10

VSS[108]

W11

VSS[109]

U14

VSS[110]

W16

VSS[111]

U21

VSS[112]

U22

VSS[113]

U25

VSS[114]

V3

VSS[115]

V8

VSS[116]

V19

VSS[117]

V23

VSS[118]

W1

VSS[119]

W4

VSS[120]

W5

VSS[121]

W7

VSS[122]

W9

VSS[123]

W15

VSS[124]

W19

VSS[125]

W21

VSS[126]

W22

VSS[127]

W25

VSS[128]

Y3

VSS[129]

Y23

VSS[130]

AA1

VSS[131]

AA4

VSS[132]

AA6

VSS[133]

AA8

VSS[134]

AA11

VSS[135]

AA13

VSS[136]

AA15

VSS[137]

AA16

VSS[138]

AA17

VSS[139]

AA19

VSS[140]

AA21

VSS[141]

AA22

VSS[142]

AA25

VSS[143]

AB3

VSS[144]

AB9

VSS[145]

AB11

VSS[146]

AB13

VSS[147]

AB15

VSS[148]

AC24

VSS[149]

AC1

VSS[150]

AC4

VSS[151]

AC10

VSS[152]

AC12

VSS[153]

AC14

VSS[154]

AD2

VSS[155]

AD6

VSS[156]

AD9

VSS[157]

AD16

VSS[158]

AD19

VSS[159]

AD22

VSS[160]

AE3

VSS[161]

AE4

VSS[162]

AE11

VSS[163]

AE13

VSS[164]

AE15

VSS[165]

V17

VSS[166]

AE8

VSS[167]

V9

VSS[168]

J16

VSS[169]

VSS_NCTF[01] VSS_NCTF[02] VSS_NCTF[03] VSS_NCTF[04]

A1 A25 AE1 AE25

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

ICH9(4/4)_POWER&GND

LS-5588

1

0.3

25 35Wednesday, July 01, 2009

0.3

5

D D

EC_SMB_DA2[4,17]

GPIO

EC_SMB_CK2[4,17]

WWAN

WLAN

LAN

C C

B B

EC_RSMRST#[24]

GPIO24[24] PM_PWROK[8,24,31]

USB_OC#2[24] USB_OC#1[24] USB_OC#0[24]

ON/OFFBTN#[24]

LPC_FRAME#[23]

CLKREQG_WWAN#[16]

VGA_HDMI_SDA[18] VGA_HDMI_SCL[18]

HDMI

CLKREQ_WLAN#[16]

PCIE_WAKE#[24]

CLK_PCIE_WAN#[16]

WWAN_CLK

WLAN_CLK

LAN_CLK

CLK_PCIE_WAN[16]

CLK_PCIE_MCARD#[16] CLK_PCIE_MCARD[16]

CLK_PCIE_LAN#[16] CLK_PCIE_LAN[16]

+RTCVCC

MAINPWON[31]

GPIO1[24]

GPIO6[24] GPIO48[24]

EC_SMI#[24]

PCIE_TXP4[24] PCIE_TXN4[24]

PCIE_RXP4[24] PCIE_RXN4[24]

PCIE_TXP2[24] PCIE_TXN2[24]

PCIE_RXP2[24] PCIE_RXN2[24]

GLAN_TXN[24] GLAN_TXP[24]

GLAN_RXN[24] GLAN_RXP[24]

SLP_S4#[24]

VGATE[24,31]

LID_SW#[24]

EC_SWI#[24]

SUSP#[20] AC_IN[24]

SLP_S5#[24]

SLP_S3#[24] EC_SCI#[24]

PLT_RST#[8,17,22]

SYSON[27,28] LPC_AD0[23] LPC_AD1[23] LPC_AD2[23] LPC_AD3[23]

SIRQ[24] KB_RST#[23] GATEA20[23]

HDMI_HPD#[18] CLK_PCI_EC[16]

TX2D+[18] TX2D-[18]

TX1D+[18] TX1D-[18]

TX0D+[18] TX0D-[18]

TXCD+[18] TXCD-[18]

ICH_SMBDATA[14,15,16,24]

ICH_SMBCLK[14,15,16,24]

PCI_PME#[22]

CLK_48M_CR[16]

CLKREQA#[16]

ICH_RTCRST#[23]

4

B+

0.1U_0603_50V4Z

VS

C1033

1

2

JP6

1

B+

3

B+

5

B+

7

B+

9

B+

11

B+

13

B+

15

RESERVED

17

GND

19

GND

21

GND

23

B+_BIAS

25

+RTCVCC

27

ICH_RTCRST#

29

GPIO1

31

EC_SMB_DA2

33

EC_SMB_CK2

35

GPIO6

37

GPIO48

39

EC_SMI#

41

NC

43

PCIE_ITX_EXPRX_P2

45

PCIE_ITX_EXPRX_N2

47

GND

49

PCIE_IRX_EXPTX_P2

51

PCIE_IRX_EXPTX_N2

53

GND

55

PCIE_ITX_WLANRX_P1

57

PCIE_ITX_WLANRX_N1

59

GND

61

PCIE_IRX_WLANTX_P1

63

PCIE_IRX_WLANTX_N1

65

GND

67

PCIE_ITX_LANRX_N0

69

PCIE_ITX_LANRX_P0

71

GND

73

PCIE_IRX_LANTX_N0

75

PCIE_IRX_LANTX_P0

77

GND

79

PM_SLP_S4#

81

VGATE

83

EC_RSMRST#

85

EC_LID_OUT#

87

GPIO24

89

PWRGD

91

EC_SWI#

93

SUSP#

95

AC_IN

97

EC_USB_OC3#

99

EC_USB_OC2#

101

EC_USB_OC1#

103

PWRBTN#

105

PM_SLP_S5#

107

PM_SLP_S3#

109

EC_SCI#

111

PLT_RST#

113

SYSON

115

LPC_AD0

117

LPC_AD1

119

LPC_AD2

121

LPC_AD3

123

LPC_FRAME#

125

SIRQ

127

EC_KBRST#

129

EC_GA20

131

EXP_REQ#

133

RESERVED

135

HDMI_HP

137

LPC_CLK0

139

GND

141

HDMI_SDA

143

HDMI_SCL

145

GND

147

TX2D+

149

TX2D-

151

GND

153

TX1D+

155

TX1D-

157

GND

159

TX0D+

161

TX0D-

163

GND

165

TXCD+

167

TXCD-

169

GND

171

WLAN_REQ#

173

WLAN_SMDATA

175

WLAN_SMCLK

177

PCIE_WAKE#

179

PCIE_PME

181

CLK_48M_CR

183

LAN_REQ#

185

CLK_PCIE_EXP

187

CLK_PCIE_EXP#

189

GND

191

CLK_PCIE_MINI

193

CLK_PCIE_MINI#

195

HDI_B_DET/GND

197

CLK_PCIE_LAN#

199

CLK_PCIE_LAN

HDI_B_DET/GND

PSATA_ITX_DRX_P0 PSATA_ITX_DRX_N0

PSATA_ITX_DRX_P1 PSATA_ITX_DRX_N1

PSATA_ITX_DRX_P2 PSATA_ITX_DRX_N2

PSATA_IRX_DTX_P2_C PSATA_IRX_DTX_N2_C

PSATA_IRX_DTX_P0_C PSATA_IRX_DTX_N0_C

PSATA_IRX_DTX_P1_C PSATA_IRX_DTX_N1_C

PANEL_BKEN_MCH

LDDC_DATA_MCH

LDDC_CLK_MCH

LCD_ACLK+_MCH

LCD_ACLK-_MCH

+5VS

+5VALW +3VALW

+3VS +3VS +3VS

VR_ON

GND GND GND

PC Beep

HDA_RST

HDA_SDOUT

HDA_SYNC

HDA_BIT_CLK

HDA_SDIN0 HDA_SDIN1

SATA_ACT#

GND

EC_THERM#

GPIO42

GND

1.5VS

1.5VS GND

GND

USB20_P7 USB20_N7

GND

USB20_P5 USB20_N5

GND

USB20_P4 USB20_N4

GND

USB20_P3 USB20_N3

GND

GPIO44

GND

USB20_P8 USB20_N8

GND

USB20_P6 USB20_N6

GND

USB20_P1 USB20_N1

GND

USB20_P2 USB20_N2

GND

USB20_P0 USB20_N0

GND

ENVDD

CRT_VSYNC CRT_HSYNC

GND

G_DAT_DDC2 G_CLK_DDC2

GND

CRT_RED

GND

CRT_GRN

GND

CRT_BLU

GND

LCD_A1+_MCH

LCD_A1-_MCH

GND

LCD_A0+_MCH

LCD_A0-_MCH

GND

LCD_A2+_MCH

LCD_A2-_MCH

GND

3

2

1

HDI_B_DET

2 4 6

+VL

8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200

+1.5VS

+5VS +5VALW VL +3VALW +3VS

VR_ON [31]

SB_SPKR [24] HDA_RST# [23] HDA_SDOUT [23] HDA_SYNC [23] HDA_BITCLK [23] HDA_SDIN0 [23] HDA_SDIN1 [23]

IDE_LED# [23]

SATA_TXP0_CR [23] SATA_TXN0_CR [23]

THERM_SCI# [24]

GPIO42 [24] SATA_TXP1_CR [23]

SATA_TXN1_CR [23]

SATA_TXP2_CR [23] SATA_TXN2_CR [23]

SATA_RXP2_C [23] SATA_RXN2_C [23]

SATA_RXP0_C [23] SATA_RXN0_C [23]

USB20_P7 [24]

USB20_N7 [24]

SATA_RXP1_C [23] SATA_RXN1_C [23]

USB20_P5 [24] USB20_N5 [24]

USB20_P4 [24] USB20_N4 [24]

USB20_P3 [24]

USB20_N3 [24]

GPIO44 [24] USB20_P8 [24]

USB20_N8 [24] USB20_P6 [24]

USB20_N6 [24] USB20_P1 [24]

USB20_N1 [24] USB20_P2 [24]

USB20_N2 [24] USB20_P0 [24]

USB20_N0 [24]

ENABLT [18] ENAVDD [18]

DDC2_DATA [18] DDC2_CLK [18] CRT_VSYNC [17,18] CRT_HSYNC [17,18]

CRT_DDC_DATA [18] CRT_DDC_CLK [18]

D_RED [18]

D_GREEN [18]

D_BLUE [18] TXOUT_L1+ [18]

TXOUT_L1- [18] TXOUT_L0+ [18]

TXOUT_L0- [18] TXOUT_L2+ [18]

TXOUT_L2- [18] TXCLK_L+ [18]

TXCLK_L- [18]

HDA

GPIO

SATA

USB

LVDS

A A

5

HDI_B_DET

4

FPC_O0P45X2P35

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/04/20 2010/04/30

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

Golden finger

LS-5588

26 35Wednesday, July 01, 2009

1

0.3

5

4

3

2

1

+1.5V to +1.5VS

+1.5V

U13

8

S

1 2

7 6 5

R443

R443 0_0402_5%

0_0402_5%

@

D

S

D

S

D

G

D

SI4800BDY-T1-E3_SO8

C1184

0.1U_0603_25V7K

D D

1

C1183

2

10U_0805_10V4Z

B+

R396

R396 100K_0402_5%

100K_0402_5%

SUSP

Q25

Q25 2N7002_SOT23

2N7002_SOT23

C C

+1.5VS_GATE

13

D

2

G

S

1

2

1 2 3 4

@

+1.5VS

C1193

1

C1182

0.1U_0603_25V7K

2

1

C1181

2

1U_0603_10V4Z

10U_0805_10V4Z

H_3P2

H_4P2

H_1P8N

H1 HOLEAH1HOLEA

H6 HOLEAH6HOLEA

H10

H10 HOLEA

HOLEA

1

H3

H2

HOLEAH3HOLEA

HOLEAH2HOLEA

1

H7

H8

HOLEAH7HOLEA

HOLEAH8HOLEA

1

H11

H11 HOLEA

HOLEA

1

FM2FM2

FM1FM1

1

H5

H4

HOLEAH5HOLEA

HOLEAH4HOLEA

1

FM3FM3

1

H9 HOLEAH9HOLEA

1

FM4FM4

1

R311

470_0402_5%

Q19A

2

+1.5V

12

61

+1.8VS

12

R309

470_0402_5%

B B

470_0402_5%

61

Q18A

SUSP SUSPSYSON#SUSP

2

R310

470_0402_5%

Q18B

5

12

3

4

2N7002DW-7-F_SOT363-6

A A

5

2N7002DW-7-F_SOT363-6

R312

470_0402_5%

Q19B

5

4

+0.75VS+VCCP

12

3

4

2N7002DW-7-F_SOT363-6

+1.5VS +1.1VS +3.3V_DELAY

R314

470_0402_5%

Q20A

2

12

61

470_0402_5%

SUSPSUSP

Q20B

12

R313

3

5

4

2N7002DW-7-F_SOT363-6

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2N7002DW-7-F_SOT363-6

SUSP#

3

12

R315

470_0402_5%

13

D

SUSP

Q77

2

G

2N7002_SOT23

S

R03

R326

D8

CH751H-40_SC76

2009/04/20 2010/04/30

R326

1 2

21

470_0402_5%

Compal Secret Data

Deciphered Date

SYSON[26,28] SUSP# [20]

+1.8VSPEN [32]

12

R307

100K_0402_5%

SYSON# SUSP

61

Q17A

SYSON

2

2N7002DW-7-F_SOT363-6

2

+5VALW+5VALW

12

R308

R308 100K_0402_5%

100K_0402_5%

3

Q17B

SUSP#

5

4

2N7002DW-7-F_SOT363-6

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

DC/DC Interface

LS-5588

1

27 35Wednesday, July 01, 2009

0.3

A

1 1

PR400

0_0402_5%

+1.5VP

1 2

@0.1U_0402_16V7K

10K_0402_1%

PR407

1 2

PC408

@10P_0402_50V8J

PR409

10K_0402_1%

PC400

12

+1.5VP

12

1 2

PR404 0_0402_5%PR404 0_0402_5%

PC412

1 2

@22P_0402_50V8J

1.5V_PGOOD[8]

PR402

255K_0402_1%

1 2

1.5V_VOUT

1.5V_VF5FILT+5VALW

1.5V_VFB

SYSON[26,27]

2 2

PR405

100_0402_1%

+5VALW

3 3

1 2

PC406

4.7U_0805_6.3V6K

12

2 3 4 5 6

1 2

12

PC413

0.47U_0402_6.3V6K@

1.5V_EN

PU400

TON VOUT V5FILT VFB PGOOD

PR410

PR410 100K_0402_1%

100K_0402_1%

B

1

EN_PSV

GND7PGND

TPS51117RGYR_QFN14_3.5x3.5

8

+1.5VP

14TP15

VBST

V5DRV

DRVH

TRIP

DRVL

PR401

0_0402_5%

1 2

13 12

LL

11 10 9

BST_1.5V-1BST_1.5V

UG_1.5V LX_1.5V

1.5V_TRIP +5VALW LG_1.5V

PC405

0.1U_0402_10V7K

1 2

PR406

1 2

0_0402_5%

1 2

10.7K_0402_1%

12

PC407

4.7U_0805_10V6K

PR403

UG1_1.5V

C

PL400

+1.5V_B+

12

758

4

123 6

PC401

PC402

PC403

0.1U_0402_25V6

2200P_0402_50V7K

PQ400

NTMS4816NR2G_SO8

1UH_PCMB103E-1R0MS_20A_20%

4.7U_0805_25V6-K

PL401

1 2

PL400

HCB1608KF-121T30_0603

1 2

12

PC404

4.7U_0805_25V6M

D

B+

+1.5VP

12

PR408

4.7_1206_5%

PQ401

3 5

241

NTMFS4946NT1G_SO8FL-5

+1.5VP

12

PC411

PC411 680P_0603_50V8J

680P_0603_50V8J

PJP400

2

JUMP_43X118@

112

PC409

4.7U_0805_6.3V6K

+1.5V

1

12

+

PC410

2

220U_B2_2.5VM_R25M

(8A,320mils ,Via NO.= 16)

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

2008/10/31 2009/10/31

Compal Secret Data

Deciphered Date

C

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

1.5VP

LS5588P

D

28 35Wednesday, July 01, 2009

0.3

5

PR516

PC520

0_0402_5%

+1.05VCCP

12

+VCCP

SUSP#[20]

D D

PR518

100_0402_1%

+5VALW

C C

+1.05VCCP

1 2

4.7U_0805_6.3V6K

PJP500

1 2

PAD-OPEN 4x4m

4

PC519

12

@1000P_0402_50V7K

PR524

PR524 255K_0402_1%

255K_0402_1%

1 2

PR519 0_0402_5%PR519 0_0402_5%

PR503

1 2

4.12K_0402_1%

1 2

PC526

@10P_0402_50V8J

PR504

10K_0402_1%

2 3 4 5 6

12

PC527

1 2

(8A,120mils ,Via NO.= 6)

PU501

TON VOUT V5FILT VFB PGOOD

@22P_0402_50V8J

1

EN_PSV

GND7PGND

TPS51117RGYR_QFN14_3.5x3.5

8

BST_VCCP

14TP15

VBST

DRVH

TRIP

V5DRV

DRVL

LL

PR511

0_0402_5%

1 2

UG_VCCP

13

LX_VCCP

12

1 2

11

+5VALW

10

LG_VCCP

9

0.1U_0402_10V7K

PR517

PC511

1 2

13.7K_0402_1%

12

PC521

4.7U_0805_10V6K

3

PR509

0_0402_5%

1 2

UG1_VCCP

2

PL501

VCCP_B+

12

578

3 6

5

241

786

PQ502

PQ502 AO4466_SO8

AO4466_SO8

PQ504

PC504

4

AO4710_SO8

123

12

PC506

PC505

0.1U_0402_25V6

2200P_0402_50V7K

2.2UH_PCMC063T-2R2MN_8A_20%

1 2

12

PR513

4.7_1206_5%

12

PC517

PC517 680P_0603_50V8J

680P_0603_50V8J

HCB1608KF-121T30_0603

1 2

12

PC507

4.7U_0805_25V6-K

PL503

PC514

4.7U_0805_6.3V6K

PL501

12

B+

+1.05VCCP

1

+

2

PC515

PC515 220U_B2_2.5VM_R25M

220U_B2_2.5VM_R25M

1

B B

A A

Security Classification Compal Secret Data

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/11/23 2007/11/23

Deciphered Date

2

Date: Sheet of

Compal Electronics, Inc.

Title

1.05VCCP

Size Document Number Rev

LS5588P

29 35Wednesday, July 01, 2009

1

29 35Wednesday, July 01, 2009

0.3

A

1 1

+1.5V

12

PC600

10U_0805_6.3V6M

12

PR601

PR601 10K_0402_5%

10K_0402_5%

13

D

S

PQ601

PQ601 RHU002N06_SOT323-3

RHU002N06_SOT323-3

10U_0805_6.3V6M

2

G

PQ600

+5VALW

2 2

SUSP#[20]

1 2

PR603

0_0402_5%

@0.1U_0402_16V7K

PC605

2

G

12

B

PU600

VIN1VCNTL

2

0.1U_0402_10V7K

GND

3

VREF

4

VOUT

G2992F1U_SO8

12

PC604

PC604 10U_0805_6.3V6M

10U_0805_6.3V6M

12

PC601

PR600

10U_0805_10V4Z

1K_0402_1%

12

13

D

PR602

PR602 1K_0402_1%

1K_0402_1%

S

RHU002N06_SOT323-3

12

PC603

NC NC NC

TP

+0.75VSP

6 5 7 8 9

12

PC602

PC602 1U_0603_10V6K

1U_0603_10V6K

+5VALW

C

D

PJP600

+0.75VSP

3 3

4 4

A

1 2

PAD-OPEN 3x3m

B

(2A,80mils ,Via NO.= 4)

+0.75VS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/09/15 2009/09/15

Compal Secret Data

Deciphered Date

C

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

0.75VSP

LS5588P

D

30 35Wednesday, July 01, 2009

0.3

+VCCP

5

4

3

2

1

D D

C C

B B

A A

@

68_0402_5%

PM_PWROK[8,24,26]

H_PROCHOT#[4]

PR200

VGATE[24,26]

1 2

H_PROCHOT#

@

VCCSENSE[5]

VSSSENSE[5]

PR229

0_0402_5%

PR209

0_0402_5%

@4.22K_0402_1%

5

VR_ON[26]

12

PR215

1 2

6.81K_0402_1%

PC215

PM_DPRSLPVR[8,24]

H_DPRSTP#[5,8,23]

+3VALW

PR211147K_0402_1%PR211147K_0402_1%

1 2

PH201

1 2

14.7K_0402_1%

1 2

PR217

1 2

PR218464K_0402_1%PR218464K_0402_1%

1 2

12

150P_0402_50V8J

1 2

PC216 47P_0402_50V8JPC216 47P_0402_50V8J

1 2

0_0402_5%

1 2

0_0402_5%

330P_0402_50V7K

12

PC200

PC200 @0.1U_0402_16V7K

@0.1U_0402_16V7K

PR210

1 2

H_PROCHOT#

@100K_0603_1%_TH11-4H104FT

1 2

PC212

0.015U_0603_25V7K

PR216

PC214

1000P_0402_50V7K

1 2

PR221

330_0402_1%

1 2

2.21K_0402_1%

1 2

PR223

PR225

12

PC222

0.22U_0603_10V7K

PR205

0_0402_5%

1 2

12

PR207

1.91K_0402_1%

@40.2K_0402_1%

PC218

390P_0402_50V7K

1 2

PR222

PC220 1000P_0603_50V7KPC220 1000P_0603_50V7K

1 2

12

PC221

PC221 1000P_0402_50V7K

1000P_0402_50V7K

PC223330P_0402_50V7KPC223330P_0402_50V7K

1 2

PR227

1K_0402_1%

PC226

PR203

0_0402_5%

1 2

PU200

1

FDE

2

PMON

3

RBIAS

4

VR_TT#

5

NTC

6

SOFT

7

OCSET

8

VW

9

COMP

10

FB

1 2

12

PC208

40

41

GND PAD

11

1 2

PR228

11K_0402_1%

4

PR202

PR202 0_0402_5%

0_0402_5%

1 2

1U_0603_6.3V6M

39

3V3

PGOOD

VSEN12VDIFF

12

PC211

1 2

PC210

+5VALW

1U_0603_10V6K

PR204

PR204 1_0603_5%

1_0603_5%

1 2

12

4

758

PQ200

PQ200 NTMS4816NR2G_SO8

NTMS4816NR2G_SO8

123 6

PQ201

PQ201 NTMFS4946NT1G_SO8FL-5

NTMFS4946NT1G_SO8FL-5

3 5

241

PH3 under CPU botten side :

12

0.1U_0603_50V7K

[5]

[26]

CPU_VID5

CPU_VID6

CPU_VID3

CPU_VID4

VR_ON

CPU_VID2

[5]

CPU_VID0

CPU_VID1

[5]

12

PC209

1 2

PR212

0_0603_5%

PC209

0.01U_0402_16V7K

0.22U_0603_10V7K

0_0402_5%

PR208

34

35

36

37

38

VR_ON

CLK_EN

DPRSTP#

DPRSLPVR

DFB

VO

DROOP

RTN

15

16

14

13

VID331VID432VID533VID6

30

VID2

29

VID1

28

VID0

27

VCCP

LGATE_CPU1

26

LGATE

25

VSSP

PHASE_CPU1

24

PHASE

UGATE_CPU1

23

UGATE

BOOT_CPU1

22

BOOT

21

NC

VSS

VSUM

VDD

VIN

17

18

19

20

ISL6261ACRZ-T_QFN40_6X6

+CPU_B+

12

PC201

PC202

2200P_0402_50V7K

12

PR213

4.7_1206_5%

12

PC205

PC206

4.7U_0805_25V6-K

12

PR214

7.68K_0805_1%

VSUM

12

PC204

4.7U_0805_25V6-K

12

PL200

HCB2012KF-121T50_0805

1 2

PL201

0.45UH_ETQP4LR45XFC_25A_-25+20%

1 2

B+

+VCC_CORE

12

PC213

PC213 680P_0603_50V8J

680P_0603_50V8J

CPU thermal protection at 85 degree C

Recovery at 45 degree C

12

PC219

0.22U_0603_25V7K

1 2

PC224 0.1U_0402_10V7KPC224 0.1U_0402_10V7K

2008-07-17

1 2

12

PC217

PC217 1U_0603_10V6K

1U_0603_10V6K PR220

PR220 10_0603_5%

10_0603_5%

1 2

12

0.1U_0402_10V7K

PC225

PR219

PR219 10_0603_5%

10_0603_5%

+5VALW

VL

12

PH1

+CPU_B+

VSUM

12

PR224

12

3.57K_0402_1%

4.53K_0402_1%

4.53K_0402_1% PH200

PH200

10KB_0603_5%_ERTJ1VR103J

PR226

1 2

+VCC_CORE

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/06/23 2006/10/22

PH1

100K_0603_1%_TH11-4H104FT

PH

12

PC18

0.22U_0402_6.3V6K

Compal Secret Data

Deciphered Date

PR33

21.5K_0402_1%

PR30

13.7K_0402_1%

1 2

12

2

12

TM_REF1

PC19

PC64

1000P_0402_50V7K

0.01U_0402_25V7K

TM-2

12

VL

8

3

+

2

-

4

PR34

PR34 100K_0402_1%

100K_0402_1%

PR35

PR35 100K_0402_1%

100K_0402_1%

VL

PR28

PR28 47K_0402_1%

PR29

47K_0402_1%

1 2

P

1

O

G

PU7A

PU7A LM393DG_SO8

LM393DG_SO8

12

VL

Title

Size Document Number Rev

Custom

Date: Sheet of

47K_0402_1%

1 2

13

D

2

G

7

O

PU7B

PU7B LM393DG_SO8

LM393DG_SO8

D

S

1

TM-3

8

5

P

+

6

-

G

4

Compal Electronics, Inc.

CPU_CORE

IAX00

Wednesday, July 01, 2009

MAINPWON [26]

PQ4

PQ4 2N7002KW_SOT323-3

2N7002KW_SOT323-3

31 35

0.3

A B C

+3VS

+5VS

12

+1.8VSPEN

PC703

+1.8VSP

12

PC702

PC702 1U_0402_6.3V6K

1U_0402_6.3V6K

12

PU701

6

VCNTL

5

VIN

9

VIN

8

EN

7

POK

PJP701

1 2

PAD-OPEN 4x4m

3

VOUT

4

VOUT

2

FB

GND

APL5913-KAC-TRL_SO8

1

+1.8VS

+1.8VSP

12

PR702

4.64K_0402_1%

12

PR703

3.65K_0402_1%

12

PC705

PC705 10U_0805_6.3V6M

PC704

0.01U_0402_25V7K

10U_0805_6.3V6M

PC701

10U_0805_6.3V6M

1 1

SUSP#[20]

+1.8VSPEN[27]

2 2

10U_0805_6.3V6M

R03

PR701

PR701 100K_0402_5%

100K_0402_5%

1 2

0.47U_0402_6.3V6K

D

3 3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/10/31 2009/10/31

Compal Secret Data

Deciphered Date

C

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

1.8VSP

LS5588P

D

32 35Wednesday, July 01, 2009

0.3

5 4 3

PL801

PR801

205K_0402_1%

2 3 4 5 6

VGA_FB1

TON VOUT V5FILT VFB PGOOD

205K_0402_1%

1 2

1

EN_PSV

GND7PGND

DGPU_RUN_PWROK

DGPU_PWR_EN

PR803

0_0402_5%

1 2

14TP15

UG_VGA

VBST

13

DRVH

SW_VGA

12

LL

VGA_TRIP

11

1 2

TRIP

V5DRV

DRVL

8

PU801

PU801 TPS51117RGYR_QFN14_3.5x3.5

TPS51117RGYR_QFN14_3.5x3.5

SUSP#[20]

10

LG_VGA

9

PR807

9.1K_0402_1%

10U_0805_6.3V6M

PD801

PD801 1SS355_SOD323-2

1SS355_SOD323-2

1 2

BST_VGA-1

1 2

0.1U_0603_25V7K

PC707

PR707

0_0402_5%@

1 2

PR705

PR705 0_0402_5%

0_0402_5%

1 2

0.47U_0402_6.3V6K

PC803

+1.5VS

+5VALW

12

+5VS

12

PC810

4.7U_0805_6.3V6K

+5VS

12

PC706

+1.1VSP

12

PC710

PC710 1U_0402_6.3V6K

1U_0402_6.3V6K

1 2

578

3 6

241

786

5

4

PU702

6

VCNTL

5

VIN

9

VIN

8

EN

7

POK

PJP702

PAD-OPEN 4x4m

VGA_IN

PQ801

PQ801 SI4686DY-T1-E3_SO8

SI4686DY-T1-E3_SO8

5

4

PQ802

123

SI4634DY-T1-E3_SO8

VOUT VOUT

FB

GND

APL5913-KAC-TRL_SO8

1

+1.1VS

12

PC801

10U_1206_25V6M

786

PQ803

123

SI4634DY-T1-E3_SO8

3 4

2

VGA_TON

D D

DGPU_PWR_EN

SUSP#[20]

+5VALW

C C

VGA_PWRSEL0[18]

B B

PR814

PR814 10K_0402_1%

10K_0402_1%

PR815

0_0402_5%

1 2

PR802

0_0402_5%

1 2

PR806

100_0402_1%

1 2

+5VS

12

PR816

10K_0402_1%

GVID1-2

13

D

GVID1-1

2

12

G

S

12

PC813

0.022U_0402_16V7K

VGA_PWRSEL0

0

1

@

12

PC804

0.1U_0402_16V7K

@

12

PC809

4.7U_0805_6.3V6K

PR812

115K_0402_1%

1 2 13

D

2

G

PQ805

S

SSM3K7002FU_SC70-3

PQ804

PQ804 SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

VGA_CORE

0.95V

PR804

PR804 0_0402_5%

0_0402_5%

VGA_FB

PC812

47P_0402_50V8J@

1 2

PR810

10K_0402_1%

1 2

1V

VGA_EN BST_VGA

VGA_VOUT+VGA_COREP

12

VGA_V5FILT

12

PR809

0_0402_5%

@

1 2

PR813

36.5K_0402_1%

PL801

HCB1608KF-121T30_0603

1 2

PC802

10U_1206_25V6M

1UH_PCMB103E-1R0MS_20A_20%

1 2

12

PR805

4.7_1206_5%

VGA_SNB

12

PC811

680P_0603_50V7K

12

PR706

12

PR704

3.65K_0402_1%

PL802

1.43K_0402_1%

2

B+

+VGA_COREP

1

12

+

PC805

2

PR808

10_0402_5%

330U_D2_2.5VY_R15M

PR811

PR811 0_0402_5%

0_0402_5%

12

PC708

0.01U_0402_25V7K

12

PC806

10U_0805_6.3V6M

12

+1.1VSP

PC709

10U_0805_6.3V6M

12

PC807

PC808

10U_0805_6.3V6M

+VGASENSE [20]

+VGA_COREP +VGA_CORE

2

PJP802

JUMP_43X118@

PJP803

JUMP_43X118@

1

112

A A

Security Classification Compal Secret Data

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

Deciphered Date

2008/11/122007/11/12

2

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

VGA_CORE/1.1V

33 35Wednesday, July 01, 2009

1

0.3

5

4

3

2

1

Version change list (P.I.R. List) Page 1 of 1 for PWR

Reason for change Rev. PG# Modify List Date PhaseFixed IssueItem

D D

1

2

3

4

5

6

7

C C

8

9

10

11

12

13

14

B B

15

16

17

18

19

20

21

A A

22

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/09/20 2008/09/20

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PIR (PWR)

<Doc>

0.3

34 35Wednesday, July 01, 2009

1

0.3

5

4

3

2

1

Date Phase

1.0

Rev.Fixed Issue

add PU7,PH1,PC18,PC19,PC64,PR33,PR30,PR34,PR35,PR29,PR28,PQ4

Reason for change PG# Modify ListItem

Change OVT Circuit

1

D D

2

3

4

5 6

7

8

C C

9 10

11

12

13

14 15

16

B B

17

18

19 20

21

22

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/04/20 2010/04/30

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

HW Changed-List History-1

LS-5588

35 35Wednesday, July 01, 2009

1

0.3

COMPAL LS-5588P Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual