Page 1
5
D D
4
3
2
1
C C
Mini (EFL50) ATI VGA/B M52-P
Revision 1.0
B B
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2005/12/22
3
Compal Secret Data
Deciphered Date
2006/12/22
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Cover Sheet
EFL50 LS-2766P
12/23/05 14:40:19
1
of
113
1.0
Page 2
GDDR1
5
4
3
2
1
M54P/M52P BLOCK DIAGRAM
D D
DDRA M54P/M52P PCIE
K4D553235F-GC2A
Samsung
DDRB
C C
K4D553235F-GC2A
Samsung
B B
A A
8M*32
DQ[0:31]
A[0:11]
CLK/CLK#
PAGE 8
8M*32
DQ[0:31]
A[0:11]
CLK/CLK#
PAGE 9
27MHz
SPREAD
CLOCK
ASM3P1819N-SR
PAGE 4
THERMAL
SENSOR
MAX6649MUA
PAGE 4
MDA[0:63]
NMAA[0:13]
NMCLKA0/A0#
NMCLKA1/A1#
MDB[0:63]
NMAB[0:13]
NMCLKB0/B0#
NMCLKB1/B1#
OSC_IN
OSC_SPREAD
D+/D-
THERM_SDA, THERM_SCL
THER_ALERT
DQA[0:63]
MAA[0:13]
CLKA[0:1]
CLKA[0:1]#
MDB[0:63]
NMAB[0:13]
CLKB[0:1]
CLKB[0:1]#
GPIO_AUXWIN
PAGE 4,5,6,7
PCIE_TX[0:15]P, PCIE_TX[0:15]N
PCIE_RX[0:15]P, PCIE_RX[0:15]N
PCIE_REFCLKP, PCIE_REFCLKN
DVPDATA[18:19]
VDD25, LVDDR,
TXVDDR, AVDD,
A2VDD
PWRGD
DVI
TV_OUT
VGA_OUT
DDC1_I2C
PCIE_VDDR
PCIE_PVDD
VDDC
GPIO5
VDDR3
VDDR4
VDDR5
VDDR1
PCIE_MTX_C_GRX_P[0:15], PCIE_MTX_C_GRX_N[0:15]
PCIE_GT_MRX_P[0:15], PCIE_GTX_MRX_N[0:15]
CLK_PCIE_VGA CLK_PCIE_VGA# PLTRST_VGA#
DVI_TXD[0:2](+,-); DVI_TXC+(-)
VGA_TV_LUMA,VGA_TV_CRMA
VGA_CRT_R, VGA_CRT_G, VGA_CRT_B, DACA_HSYNC, DACA_VSYNC
VGA_DDC_CLK, VGA_DDC_DAT
LVDS Bus
I2CC_SCL
I2CC_SDA
VGA_ENVDDDIGON
VGA_ENBKLBLON
+1.2VS
+VDD_CORE
POWER_SEL
+3.3VS
+1.8VS
+2.5VS
+1.2VS
APW7057KC-TR
PAGE 11
+VDD_CORE
SL6225BCA-T
PAGE 11
+1.5VS
+5VS
B+
Connector
+1.5VS
+5VS
B+
+3VS
+1.8VS
+2.5VS
ACES 88069-1600A
PAGE 3
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2005/12/22
3
Compal Secret Data
Deciphered Date
2006/12/22
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Block Diagram
EFL50 LS-2766P
12/23/05 14:40:19
1
of
213
1.0
Page 3
5
PCIE_GTX_MRX_P[0:15]
PCIE_GTX_MRX_N[0:15]
PCIE_MTX_C_GRX_P[0:15]
PCIE_MTX_C_GRX_N[0:15]
D D
C C
B B
A A
PCIE_GTX_MRX_P[0:15] <4>
PCIE_GTX_MRX_N[0:15] <4>
PCIE_MTX_C_GRX_P[0:15] <4>
PCIE_MTX_C_GRX_N[0:15] <4>
VGA_CRT_R<4>
VGA_CRT_G<4>
VGA_CRT_B<4>
CRT_VSYNC<4>
CRT_HSYNC<4>
VGA_CRT_CLK<4>
VGA_CRT_DAT<4>
DVI_TXC+<5>
DVI_TXC-<5>
DVI_TX0+<5>
DVI_TX0-<5>
DVI_TX1+<5>
DVI_TX1-<5>
DVI_TX2+<5>
DVI_TX2-<5>
CLK_PCIE_VGA<4>
CLK_PCIE_VGA#<4>
+5VALW
+2.5VS
+1.8VS_D
VGA_CRT_R
VGA_CRT_G
VGA_CRT_B
CRT_VSYNC
CRT_HSYNC
PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_N0
PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_N1
PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_N2
PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_N3
PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_N4
PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_N5
PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_N7
PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_N8
PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_N9
PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_N10
PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_N11
PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_N12
PCIE_MTX_C_GRX_P13
PCIE_MTX_C_GRX_N13
PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_N14
PCIE_MTX_C_GRX_P15
PCIE_MTX_C_GRX_N15
VGA_CRT_CLK
VGA_CRT_DAT
4
161
JP1
2
2
4
4
6
6
8
8
10
10
12
12
14
14
16
16
18
18
20
20
22
22
24
24
26
26
28
28
30
30
32
32
34
34
36
36
38
38
40
40
42
42
44
44
46
46
48
48
50
50
52
52
54
54
56
56
58
58
60
60
62
62
64
64
66
66
68
68
70
70
72
72
74
74
76
76
78
78
80
80
82
82
84
84
86
86
88
88
90
90
92
92
94
94
96
96
98
98
100
100
102
102
104
104
106
106
108
108
110
110
112
112
114
114
116
116
118
118
120
120
122
122
124
124
126
126
128
128
130
130
132
132
134
134
136
136
138
138
140
140
142
142
144
144
146
146
148
148
150
150
152
152
154
154
156
156
158
158
160
160
ACES_88396-1G41
1
1
G1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
41
41
43
43
45
45
47
47
49
49
51
51
53
53
55
55
57
57
59
59
61
61
63
63
65
65
67
67
69
69
71
71
73
73
75
75
77
77
79
79
81
81
83
83
85
85
87
87
89
89
91
91
93
93
95
95
97
97
99
99
101
101
103
103
105
105
107
107
109
109
111
111
113
113
115
115
117
117
119
119
121
121
123
123
125
125
127
127
129
129
131
131
133
133
135
135
137
137
139
139
141
141
143
143
145
145
147
147
149
149
151
151
153
153
155
155
157
157
159
159
G2
162
3
VGA_TV_Y
VGA_TV_C
VGA_TV_COMP
PCIE_GTX_C_MRX_P0
PCIE_GTX_C_MRX_N0
PCIE_GTX_C_MRX_P1
PCIE_GTX_C_MRX_N1
PCIE_GTX_C_MRX_P2
PCIE_GTX_C_MRX_N2
PCIE_GTX_C_MRX_P3
PCIE_GTX_C_MRX_N3
PCIE_GTX_C_MRX_P4
PCIE_GTX_C_MRX_N4
PCIE_GTX_C_MRX_P5
PCIE_GTX_C_MRX_N5
PCIE_GTX_C_MRX_P6
PCIE_GTX_C_MRX_N6
PCIE_GTX_C_MRX_P7
PCIE_GTX_C_MRX_N7
PCIE_GTX_C_MRX_P8
PCIE_GTX_C_MRX_N8
PCIE_GTX_C_MRX_P9
PCIE_GTX_C_MRX_N9
PCIE_GTX_C_MRX_P10
PCIE_GTX_C_MRX_N10
PCIE_GTX_C_MRX_P11
PCIE_GTX_C_MRX_N11
PCIE_GTX_C_MRX_P12
PCIE_GTX_C_MRX_N12
PCIE_GTX_C_MRX_P13
PCIE_GTX_C_MRX_N13
PCIE_GTX_C_MRX_P14
PCIE_GTX_C_MRX_N14
PCIE_GTX_C_MRX_P15
PCIE_GTX_C_MRX_N15
VGA_DVI_CLK
VGA_DVI_DAT
DAC_BRIG
DISPOFF#
INVT_PWM
PCIE_RST#
VGA_ENBKL
LCD_ID#
+1.8VS_D
B+
VGA_TV_Y <4>
VGA_TV_C <4>
VGA_TV_COMP <4>
C2
C3
1 2
C4
C5
1 2
C6
C7
1 2
C8
C9
1 2
C10
C11
1 2
C12
C13
1 2
C14
C15
1 2
C16
C17
1 2
C18
C19
1 2
C20
C21
1 2
C22
C23
1 2
C24
C25
1 2
C26
C27
1 2
C28
C29
1 2
C30
C31
1 2
C32
C33
1 2
VGA_DVI_DET <5>
VGA_DVI_CLK <5>
VGA_DVI_DAT <5>
DAC_BRIG <10>
DISPOFF# <10>
INVT_PWM <10>
PCIE_RST# <4>
susp# <10,11>
VGA_ENBKL <4>
LCD_ID# <10>
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+3VS_D
2
PCIE_GTX_MRX_P0
PCIE_GTX_MRX_N0
PCIE_GTX_MRX_P1
PCIE_GTX_MRX_N1
PCIE_GTX_MRX_P2
PCIE_GTX_MRX_N2
PCIE_GTX_MRX_P3
PCIE_GTX_MRX_N3
PCIE_GTX_MRX_P4
PCIE_GTX_MRX_N4
PCIE_GTX_MRX_P5
PCIE_GTX_MRX_N5
PCIE_GTX_MRX_P6
PCIE_GTX_MRX_N6
PCIE_GTX_MRX_P7
PCIE_GTX_MRX_N7
PCIE_GTX_MRX_P8
PCIE_GTX_MRX_N8
PCIE_GTX_MRX_P9
PCIE_GTX_MRX_N9
PCIE_GTX_MRX_P10
PCIE_GTX_MRX_N10
PCIE_GTX_MRX_P11
PCIE_GTX_MRX_N11
PCIE_GTX_MRX_P12
PCIE_GTX_MRX_N12
PCIE_GTX_MRX_P13
PCIE_GTX_MRX_N13
PCIE_GTX_MRX_P14
PCIE_GTX_MRX_N14
PCIE_GTX_MRX_P15
PCIE_GTX_MRX_N15
TP7
+1.5VS
1
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2005/12/22 2006/12/22
3
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
Custom
2
Date: Sheet
Compal Electronics, Inc.
VGA Connector
PCIE Connector
EFL50 LS-2766P
1.0
31312/23/05 14:40:19
1
of
Page 4
5
PCIE_GTX_MRX_P[0:15]<3>
PCIE_GTX_MRX_N[0:15]<3>
PCIE_MTX_C_GRX_P[0:15]<3>
PCIE_MTX_C_GRX_N[0:15]<3>
D D
C C
+3VS
12
R51
2.2K_0402_5%
THM@
D+
D-
C121
1 2
2200P_0402_50V7K
THM@
PCIE_GTX_MRX_P[0:15]
PCIE_GTX_MRX_N[0:15]
PCIE_MTX_C_ GRX_P[0:15]
PCIE_MTX_C_GRX_N[0:15]
Thermal sensor
U7
1
VDD
2
3
4
SCLK
D+
SDATA
D-
ALERT#
OVERT#
GND
MAX6649MUA_8UMAX
THM@
8
7
6
5
THERM_SCL
THERM_SDA
1 2
R48
0_0402_5%
THM@
+3VS
1 2
THM@
R50
2.2K_0402_5%
PCI-Express Data Bus Lane Reversal and Polarity Inversion
B B
PCIE_RST#<3>
+3VS
12
R22
0_0603_5%
SSC@
1
C38
2
A A
+3VS
0.1U_0402_16V4Z
SSC@
1K_0402_5%
Spread spectrum
+SSVDD
12
R34
U6
7
1
8
2
ASM3P1819N-SR_SO8
SSC@
1 2
C50
0.1U_0402_16V4Z
X1
4
VDD
1
OE
27MHZ_15P
5
VDD
XIN
XOUT
VSS
4
MODOUT
3
NC
6
PD#
Minimize dis t a n ce from X1 pin3 to U3 pin1
OSC_IN
3
OUT
2
GND
Keep away from other signal at last 25mils
5
REF
1 2
R17
OSC_SPREAD
22_0402_5%
SSC@
CLK_PCIE_VGA<3>
CLK_PCIE_VGA#<3>
THER_ALERT#
+3VS
4
CLK_PCIE_VGA
CLK_PCIE_VGA#
PCIE_GTX_MRX_P0
PCIE_GTX_MRX_N0
PCIE_GTX_MRX_P1
PCIE_GTX_MRX_N1
PCIE_GTX_MRX_P2
PCIE_GTX_MRX_N2
PCIE_GTX_MRX_P3
PCIE_GTX_MRX_N3
PCIE_GTX_MRX_P4
PCIE_GTX_MRX_N4
PCIE_GTX_MRX_P5
PCIE_GTX_MRX_N5
PCIE_GTX_MRX_P6
PCIE_GTX_MRX_N6
PCIE_GTX_MRX_P7
PCIE_GTX_MRX_N7
PCIE_GTX_MRX_P8
PCIE_GTX_MRX_N8
PCIE_GTX_MRX_P9
PCIE_GTX_MRX_N9
PCIE_GTX_MRX_P10
PCIE_GTX_MRX_N10
PCIE_GTX_MRX_P11
PCIE_GTX_MRX_N11
PCIE_GTX_MRX_P12
PCIE_GTX_MRX_N12
PCIE_GTX_MRX_P13
PCIE_GTX_MRX_N13
PCIE_GTX_MRX_P14
PCIE_GTX_MRX_N14
PCIE_GTX_MRX_P15
PCIE_GTX_MRX_N15
PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_N0
PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_N1
PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_N2
PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_N3
PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_N4
PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_N5
PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_N7
PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_N8
PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_N9
PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_N10
PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_N11
PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_N12
PCIE_MTX_C_GRX_P13
PCIE_MTX_C_GRX_N13
PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_N14
PCIE_MTX_C_GRX_P15
+1.2VS
R6
R7
OSC_IN
4
PCIE_MTX_C_GRX_N15
R26 2K_0402_1%
1 2
R2
1 2
R3
1 2
R1
1 2
R24
1 2
4.7K_0402_5%
1 2
1 2
4.7K_0402_5%
1 2
R25
121_0402_1%
71.5_0402_1%
562_0402_1%
1.47K_0402_1%
10K_0402_5%
D+
D-
THERM_SDA
THERM_SCL
12
R23
3
U2A
AL28
PCIE_REFCLKP
AK28
PCIE_REFCLKN
AK27
PCIE_TX0P
AJ27
PCIE_TX0N
AJ25
PCIE_TX1P
AH25
PCIE_TX1N
AH28
PCIE_TX2P
AG28
PCIE_TX2N
AG27
PCIE_TX3P
AF27
PCIE_TX3N
AF25
PCIE_TX4P
AE25
PCIE_TX4N
AE28
PCIE_TX5P
AD28
PCIE_TX5N
AD27
PCIE_TX6P
AC27
PCIE_TX6N
AC25
PCIE_TX7P
AB25
PCIE_TX7N
AB28
PCIE_TX8P
AA28
PCIE_TX8N
AA27
PCIE_TX9P
Y27
PCIE_TX9N
Y25
PCIE_TX10P
W25
PCIE_TX10N
W28
PCIE_TX11P
V28
PCIE_TX11N
V27
PCIE_TX12P
U27
PCIE_TX12N
U25
PCIE_TX13P
T25
PCIE_TX13N
T28
PCIE_TX14P
R28
PCIE_TX14N
R27
PCIE_TX15P
P27
PCIE_TX15N
AJ31
PCIE_RX0P
AH31
PCIE_RX0N
AH30
PCIE_RX1P
AG30
PCIE_RX1N
AG32
PCIE_RX2P
AF32
PCIE_RX2N
AF31
PCIE_RX3P
AE31
PCIE_RX3N
AE30
PCIE_RX4P
AD30
PCIE_RX4N
AD32
PCIE_RX5P
AC32
PCIE_RX5N
AC31
PCIE_RX6P
AB31
PCIE_RX6N
AB30
PCIE_RX7P
AA30
PCIE_RX7N
AA32
PCIE_RX8P
Y32
PCIE_RX8N
Y31
PCIE_RX9P
W31
PCIE_RX9N
W30
PCIE_RX10P
V30
PCIE_RX10N
V32
PCIE_RX11P
U32
PCIE_RX11N
U31
PCIE_RX12P
T31
PCIE_RX12N
T30
PCIE_RX13P
R30
PCIE_RX13N
R32
PCIE_RX14P
P32
PCIE_RX14N
P31
PCIE_RX15P
N31
PCIE_RX15N
AE24
PCIE_CALRN
AD24
PCIE_CALRP
AB24
PCIE_CALI
0_0402_5%
AG24
PERST#
AA24
PCIE_TEST
AF24
PERST#_MASK
AG12
DPLUS
AH12
DMINUS
AE12
DDC3DATA
AF12
DDC3CLK
AL26
XTALIN
AM26
XTALOUT
M52-P
GPIO
NC_DVOVMODE_0
NC_DVOVMODE_1
PCI EXPRESS
THERMAL
XTAL
GPIO_7_BLON
DVPDATA_10
DVPDATA_11
DVPDATA_12
DVPDATA_13
DVPDATA_14
DVPDATA_15
DVPDATA_16
DVPDATA_17
DVPDATA_18
DVPDATA_19
DVPDATA_20
DVPDATA_21
DVPDATA_22
VIP HOST/ EXTERNAL TMDS
DVPDATA_23
CRT
TV
DVPCNTL_0
DVPCNTL_1
DVPCNTL_2
DVPDATA_0
DVPDATA_1
DVPDATA_2
DVPDATA_3
DVPDATA_4
DVPDATA_5
DVPDATA_6
DVPDATA_7
DVPDATA_8
DVPDATA_9
DDC1DATA
GENERICA
GENERICB
GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
GPIO_6
GPIO_8
GPIO_9
GPIO_10
GPIO_11
GPIO_12
GPIO_13
GPIO_14
GPIO_15
GPIO_16
GPIO_17
VREFG
DVPCLK
HSYNC
VSYNC
DDC1CLK
RSET
H2SYNC
V2SYNC
COMP
R2SET
ROMCS#
PLLTEST
TESTEN
AD4
AD2
AD1
AD3
AC1
AC2
AC3
AB2
AC6
AC5
AC4
AB3
AB4
AB5
AD5
AB8
AA8
AB7
AB6
NC
AC8
AK4
AL4
AF2
AF1
AF3
AG1
AG2
AG3
AH2
AH3
AJ2
AJ1
AK2
AK1
AK3
AL2
AL3
AM3
AE6
AF4
AF5
AG4
AJ3
AH4
AJ4
AG5
AH5
AF6
AE7
AG6
AK24
R
AM24
G
AL24
B
AJ23
AJ22
AH22
AH23
AK22
AF23
AL22
AK15
R2
AM15
G2
AL15
B2
AF15
AG15
AJ15
Y
AJ13
C
AH15
AK14
AC7
AG14
AG22
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2005/12/22
3
R63
1 2
R14
1 2
R13
1 2
R80
1 2
R16
1 2
GPIO9
TP4
GPIO11
GPIO12
GPIO13
POWER_SEL
OSC_SPREAD
THER_ALERT#
R53
R54
VGA_CRT_R
VGA_CRT_G
VGA_CRT_B
CRT_HSYNC
CRT_VSYNC
R28
R33
VGA_TV_COMP
R39
R31
12
1 2
Low -> VDDC=1.0V+-5% Performance Mode for M52
High -> VDDC=0.95V+-5% Battery Mode for M52
TP6
TP3
MEMID0
MEMID1
MEMID2
TP1
R32
1 2
R27
1 2
VGA_TV_Y
VGA_TV_C
1 2
Compal Secret Data
Deciphered Date
VGA_ENBKL
10K_0402_5%
499_0402_1%
499_0402_1%
C130
1 2
POWER_SEL
R12
1 2
R10
1 2
R11
1 2
R9
1 2
R8
1 2
VGA_CRT_R <3>
VGA_CRT_G <3>
VGA_CRT_B <3>
CRT_HSYNC <3>
CRT_VSYNC <3>
4.7K_0402_5%
4.7K_0402_5%
1K_0402_5%
12
499_0402_1%
12
R35
715_0402_1%
12
10K_0402_5%
@
VGA_TV_Y <3>
VGA_TV_C <3>
VGA_TV_COMP <3>
10K_0402_5%@
10K_0402_5%
10K_0402_5%
10K_0402_5%
+3VS
0.1U_0402_16V4Z
R97
1 2
+3VS
4.7K_0402_5%
4.7K_0402_5%
10K_0402_5%R128@
10K_0402_5%X76@
10K_0402_5%HYN@
150_0402_1%
12
2006/12/22
2
+3VS
VGA_ENBKL <3>
POWER_SEL <11>
10K_0402_5%
I2C_DAT
I2C_CLK
+3VS
VGA_CRT_DAT
VGA_CRT_CLK
Internal SS, P r o g r a mmed via register-GENERICA = NC
GENERICB = GND.
2
I2C_DAT <10>
I2C_CLK <10>
+3VS
VGA_CRT_DAT <3>
VGA_CRT_CLK <3>
1
Straps: (Internal pull down)
Transmitter power
saving enable
Transmitter
de-emphasis enable
GPIO[0]
GPIO[1] 0: TX de-emphasis disable
Debug Access GPIO[4]
Current bias for
the PCI Express PHY PLL
ROM ID Config GPIO[9,
GPIO[5]
13:11]
(Internal
Pull-down)
VSYNCVIP_DEVICE
GPIO9
R78
GPIO11
R79
GPIO12
R76
GPIO13
R77
GPIO12 GPIO13 SIZE
00
0
1
11
0: 50% TX output swing
1: Full TX output swing
1: TX de-emphasis enable
0: OFF
1: ON
GPIO5 = 1
(must be pulled t o 3 . 3 V at reset using)
GPIO[9]=1 External ROM Attached
GPIO[9]=0 No External ROM
For No External ROM:
GPIO[13,12] is for MEM_AP_SIZE[1,0]
GPIO[11] do n 't care
0: Slave VIP h o s t d e vi c e p r e sent
1: No slave VIP host d evice p resent
* The readback of this strap is the
inverted with respect to the value
on the pin
10K_0402_5%
1
0
@
10K_0402_5%
@
10K_0402_5%
R256@
10K_0402_5%
R64@
128MB
64MB
256MB
Reserve
1 2
1 2
1 2
1 2
+3VS
Memory Aperture Size Select
For DDRII
Vedio Memory Config. (VGA Internal PD)
MEMID[2:0]
0 0 0
0 0 1
1 0 0
1 0 1
VGA_CRT_R
VGA_CRT_G
VGA_CRT_B
VGA_TV_Y
VGA_TV_C
Title
Size Document Number Rev
Custom
Date: Sheet
Compal Electronics, Inc.
EFL50 LS-2766P
12/23/05 14:40:18
Size (Speed) Vender Chips
Size
64MB 16M16 (300MHz) Samsung 2
128MB 16M16 (300MHz) Samsung 4
64MB
16M16 (300MHz) Hynix 2
128MB
16M16 (300MHz) Hynix 4
Close to VGA Cbip
R56
R30
R29
R36
R45
150_0402_1%@
12
150_0402_1%@
12
150_0402_1%@
12
150_0402_1%@
12
150_0402_1%@
12
M52-P Main
413
1
of
1.0
Page 5
5
U2B
VARY_BL
DIGON
TXCM
TXCP
TX0M
TX0P
TX1M
TX1P
TX2M
TX2P
TX3M
TX3P
TX4M
TX4P
TX5M
TX5P
DDC2CLK
HPD1
AJ21
AK21
AG18
AH18
AK20
AJ20
AG20
AH20
AH21
AG21
AL18
AM18
AL19
AK19
AM20
AL20
AM21
AL21
AJ18
AK18
AD12
AE11
AD23
AL9
AM9
AK10
AL10
AL11
AM11
AL12
AM12
AK9
AJ9
AK11
AJ11
AK12
AJ12
AH13
AG13
AF11
AE13
GPIO_18
AF13
GPIO_19
AF9
GPIO_20
AG7
GPIO_21
AE10
GPIO_22
AE9
GPIO_23
AF7
GPIO_24
AF8
GPIO_25
0.1U_0402_16V4Z
AH6
GPIO_26
AF10
GPIO_27
AG10
GPIO_28
AH9
GPIO_29
AJ8
GPIO_30
AH8
GPIO_31
AG9
GPIO_32
AH7
GPIO_33
AG8
GPIO_34
AE23
GENERICC
Y23
BBN
K15
BBN
R10
BBN
AC17
BBN
AC14
BBP
M23
BBP
V10
BBP
K18
BBP
L10
VDD25
K22
VDD25
AA10
VDD25
1
C81
2
D D
C C
+VDD25
1
C66
2
0.1U_0402_16V4Z
TXCLK_UP
TXCLK_UN
TXOUT_U0P
TXOUT_U0N
TXOUT_U1P
TXOUT_U1N
TXOUT_U2P
TXOUT_U2N
TXOUT_U3P
TXOUT_U3N
TXCLK_LN
TXCLK_LP
TXOUT_L0P
LVDS
TXOUT_L0N
EXPAND GPIO
TXOUT_L1P
TXOUT_L1N
TXOUT_L2P
TXOUT_L2N
TXOUT_L3P
TXOUT_L3N
GENERICD
FOREARD
COMPATIBILITY
INTERGRATED TMDS
DDC2DATA
M52-P
B B
4
VGA_LVDSBC+
VGA_LVDSBCVGA_LVDSB0+
VGA_LVDSB0VGA_LVDSB1+
VGA_LVDSB1VGA_LVDSB2+
VGA_LVDSB2-
VGA_LVDSACVGA_LVDSAC+
VGA_LVDSA0+
VGA_LVDSA0VGA_LVDSA1+
VGA_LVDSA1VGA_LVDSA2+
VGA_LVDSA2-
R44
1 2
VGA_ENVDD
R52
1 2
R49
1 2
R46
1 2
R43
1 2
12
R114
100K_0402_5%
if no DVI , dvi_det pull low
10K_0402_5%
180_0402_5%
180_0402_5%
180_0402_5%
180_0402_5%
VGA_DVI_DAT
VGA_DVI_CLK
VGA_DVI_DET
VGA_LVDSBC+ <10>
VGA_LVDSBC- <10>
VGA_LVDSB0+ <10>
VGA_LVDSB0- <10>
VGA_LVDSB1+ <10>
VGA_LVDSB1- <10>
VGA_LVDSB2+ <10>
VGA_LVDSB2- <10>
VGA_LVDSAC- <10>
VGA_LVDSAC+ <10>
VGA_LVDSA0+ <10>
VGA_LVDSA0- <10>
VGA_LVDSA1+ <10>
VGA_LVDSA1- <10>
VGA_LVDSA2+ <10>
VGA_LVDSA2- <10>
VGA_ENVDD <10>
DVI_TXCDVI_TXC+
DVI_TX0DVI_ TX0 +
DVI_TX1DVI_ TX1 +
DVI_TX2DVI_ TX2 +
DVI_TXC- <3>
DVI_TXC+ <3>
DVI_TX0- <3>
DVI_TX0+ <3>
DVI_TX1- <3>
DVI_TX1+ <3>
DVI_TX2- <3>
DVI_TX2+ <3>
VGA_DVI_DAT <3>
VGA_DVI_CLK <3>
VGA_DVI_DET <3>
3
U2G
AH27
PCIE_VSS
AC23
PCIE_VSS
AL27
PCIE_VSS
R23
PCIE_VSS
P25
PCIE_VSS
R25
PCIE_VSS
T26
PCIE_VSS
AB26
AC26
AD25
AE26
AF26
AD26
AG25
AH26
AC28
AH29
AF28
AC29
W27
AB27
AJ26
AJ32
AK29
W29
AA29
AB29
AD29
AE29
AF29
AG29
AJ29
AK26
AK30
AG26
AF30
AC30
AA31
AD31
AK32
AJ28
AJ30
AK31
U26
PCIE_VSS
Y26
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
Y28
PCIE_VSS
U28
PCIE_VSS
P28
PCIE_VSS
PCIE_VSS
PCIE_VSS
V29
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
V26
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
P26
PCIE_VSS
P29
PCIE_VSS
R29
PCIE_VSS
T29
PCIE_VSS
U29
PCIE_VSS
PCIE_VSS
Y29
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
N30
PCIE_VSS
R31
PCIE_VSS
PCIE_VSS
PCIE_VSS
V31
PCIE_VSS
P30
PCIE_VSS
PCIE_VSS
U30
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
Y30
PCIE_VSS
PCIE_VSS
PCIE_VSS
M52-P
PCIE GND
TMDS GNDCRT GNDTV GNDPLL GNDLVDS PLL&I/O GND
PCIE_PVSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
TXVSSR
TXVSSR
TXVSSR
TXVSSR
TXVSSR
TPVSS
AVSSQ
AVSSN
AVSSN
VSS1DI
A2VSSQ
A2VSSN
A2VSSN
VSS2DI
PVSS
MPVSS
LPVSS
LVSSR
LVSSR
LVSSR
LVSSR
LVSSR
LVSSR
LVSSR
LVSSR
LVSSR
LVSSR
2
AJ7
AK7
AL7
AM7
AK8
AL8
AK23
AK25
AJ24
AL23
AK13
AM17
AL17
AJ17
AH14
A5
AE18
AK17
AJ19
AF18
AH17
AG17
AG19
AH19
AF22
AF17
AF21
W23
AB23
P24
R24
T24
U24
V24
W24
Y24
AC24
AH24
V25
AA25
R26
AA26
T27
AE27
AG31
W26
N24
AA23
Use 15mils trace
connect to GND
AD7
AE8
AL1
AM2
AD10
AC9
AF14
AD8
AA4
AG11
AG16
AD16
AA6
AD17
AH11
AM13
AC10
AL13
AD6
AD14
AD13
W18
1
U2F
B1
VSS
H1
VSS
L1
VSS
P1
VSS
U1
VSS
Y1
VSS
VSS
VSS
VSS
A2
VSS
VSS
VSS
E8
VSS
H5
VSS
K10
VSS
M8
VSS
T10
VSS
E12
VSS
VSS
VSS
VSS
C5
VSS
F10
VSS
J3
VSS
L6
VSS
M6
VSS
P6
VSS
VSS
VSS
V3
VSS
VSS
CORE
R3
VSS
C6
VSS
C9
VSS
F6
VSS
H7
VSS
GND
J6
VSS
VSS
VSS
P7
VSS
P5
VSS
M3
VSS
M9
VSS
L7
VSS
M7
VSS
VSS
VSS
A8
VSS
U7
VSS
C10
VSS
E9
VSS
F3
VSS
J9
VSS
N7
VSS
N3
VSS
Y5
VSS
VSS
VSS
Y6
VSS
U6
VSS
E5
VSS
VSS
A11
VSS
U8
VSS
U9
VSS
U10
VSS
R6
VSS
VSS
V6
VSS
VSS
VSS
D11
VSS
J12
VSS
K12
VSS
A13
VSS
F13
VSS
E13
VSS
F15
VSS
K16
VSS
VSS
M52-P
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
C27
E32
H28
J30
K17
K27
M32
A22
C20
E19
H20
J24
M28
J28
J16
F30
L29
A31
B32
E30
AE15
AG23
AD9
AF16
AH10
AJ10
AD15
AH16
K23
U18
AE16
AE17
A19
H32
F19
G19
N8
Y7
T19
V19
G21
C21
F21
AE14
AK16
U5
F22
F18
K30
C24
F24
M24
A25
D30
E25
G25
G20
G22
F27
E28
H21
J21
H16
T15
V17
C15
C4
U14
P15
A16
E16
G13
G16
P17
R16
R14
W16
C18
F16
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2005/12/22
3
Compal Secret Data
Deciphered Date
2006/12/22
2
Title
Size Document Number Rev
Custom
Date: Sheet
Compal Electronics, Inc.
M52-P LVD,DVI,GND,Screw
EFL50 LS-2766P
12/23/05 14:40:18
1
513
of
1.0
Page 6
5
U2C
M31
DQA_0
M30
DQA_1
L31
DQA_2
L30
DQA_3
H30
DQA_4
G31
DQA_5
DQA_6
DQA_7
DQA_8
DQA_9
DQA_10
DQA_11
DQA_12
DQA_13
DQA_14
DQA_15
DQA_16
DQA_17
DQA_18
DQA_19
DQA_20
DQA_21
DQA_22
DQA_23
DQA_24
DQA_25
DQA_26
DQA_27
DQA_28
DQA_29
DQA_30
DQA_31
DQA_32
DQA_33
DQA_34
DQA_35
DQA_36
DQA_37
DQA_38
DQA_39
DQA_40
DQA_41
DQA_42
DQA_43
DQA_44
DQA_45
DQA_46
DQA_47
DQA_48
DQA_49
DQA_50
DQA_51
DQA_52
DQA_53
DQA_54
DQA_55
DQA_56
DQA_57
DQA_58
DQA_59
DQA_60
DQA_61
DQA_62
DQA_63
MVREFD_0
MVREFS_0
M52-P
MEMORY A
G30
F31
M27
M29
(15mils)
(15mils)
H29
G29
G27
M26
M25
G28
H27
H26
G26
H25
H24
H23
H22
D22
D23
D19
D18
D17
D13
H18
H17
G18
G17
G15
G14
H14
L28
L27
J27
L26
L25
J25
F26
J23
J22
E23
E22
E20
F20
B19
B18
C17
B17
C14
B14
C13
B13
E18
E17
F17
E15
E14
F14
J14
C31
C30
D D
+1.8VS
12
R19
100_0402_1%
C40
0.1U_0402_16V4Z
+1.8VS
C39
0.1U_0402_16V4Z
1
2
12
R18
100_0402_1%
1
2
+MVREFD_0
(15mils)
12
R21
100_0402_1%
(15mils)
12
R20
100_0402_1%
+MVREFD_0
+MVREFS_0
C C
B B
4
MAA_0
MAA_1
MAA_2
MAA_3
MAA_4
MAA_5
MAA_6
MAA_7
MAA_8
MAA_9
MAA_10
MAA_11
MAA_12
MAA_13
MAA_14
MAA_15
DQMA#_0
DQMA#_1
DQMA#_2
DQMA#_3
DQMA#_4
DQMA#_5
DQMA#_6
DQMA#_7
QSA_0
QSA_1
QSA_2
QSA_3
QSA_4
QSA_5
QSA_6
QSA_7
QSA_0#
QSA_1#
QSA_2#
QSA_3#
QSA_4#
QSA_5#
QSA_6#
QSA_7#
ODTA0
ODTA1
CLKA0
CLKA0#
CKEA0
RASA0#
CASA0#
WEA0#
CSA0#_0
CSA0#_1
CLKA1
CLKA1#
CKEA1
RASA1#
CASA1#
WEA1#
CSA1#_0
CSA1#_1
3
D26
F28
D28
D25
E24
E26
D27
F25
C26
B26
D29
B27
B25
C25
E27
E29
H31
J29
J26
G23
E21
B15
D14
J17
J31
K29
K25
F23
D20
B16
D16
H15
K31
K28
K26
G24
D21
C16
D15
J15
F29
D24
D31
E31
B30
B28
C29
B31
B29
C28
B20
C19
C22
B24
B22
B21
B23
C23
MDA[0..63]<8,9>
DQSA[0..7]<8,9>
DQSA#[0..7]<8,9>
DQMA#[0..7]<8,9>
MAA[0..12]<8,9>
A_BA[0..1]<8,9>
MDA[0..63]
DQSA[0..7]
DQSA#[0..7]
DQMA#[0..7]
MAA[0..12]
A_BA[0..1]
+1.8VS
C145
0.1U_0402_16V4Z
+1.8VS
C147
12
R61
100_0402_1%
1
2
12
R57
100_0402_1%
1
2
0.1U_0402_16V4Z
+MVREFD_1
(15mils)
12
R62
100_0402_1%
(15mils)
12
R59
100_0402_1%
R58
4.7K_0402_5%
R55
4.7K_0402_5%
R60
4.7K_0402_5%
R15
243_0603_1%
1 2
1 2
1 2
1 2
(15mil)
MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63
+MVREFD_1
+MVREFS_1
MEM_RST
MEMTEST
2
U2D
AA3
AA5
AA2
AA7
B12
C12
B11
C11
F12
D12
E11
F11
G12
G11
H12
H11
C8
B7
C7
B6
F9
D8
D7
F7
H9
E7
F8
G8
G6
G7
H8
J8
K8
L8
K9
L9
K5
L4
K4
L5
N5
N6
P4
R4
P2
R2
T3
T2
W3
W2
Y3
Y2
T4
R5
T5
T6
V5
W5
W6
Y4
R8
T8
R7
T7
V7
W7
W8
W9
B3
C3
DQB_0
DQB_1
DQB_2
DQB_3
DQB_4
DQB_5
DQB_6
DQB_7
DQB_8
DQB_9
DQB_10
DQB_11
DQB_12
DQB_13
DQB_14
DQB_15
DQB_16
DQB_17
DQB_18
DQB_19
DQB_20
DQB_21
DQB_22
DQB_23
DQB_24
DQB_25
DQB_26
DQB_27
DQB_28
DQB_29
DQB_30
DQB_31
DQB_32
DQB_33
DQB_34
DQB_35
DQB_36
DQB_37
DQB_38
DQB_39
DQB_40
DQB_41
DQB_42
DQB_43
DQB_44
DQB_45
DQB_46
DQB_47
DQB_48
DQB_49
DQB_50
DQB_51
DQB_52
DQB_53
DQB_54
DQB_55
DQB_56
DQB_57
DQB_58
DQB_59
DQB_60
DQB_61
DQB_62
DQB_63
MVREFD_1
MVREFS_1
DRAM_RST
TEST_MCLK
TEST_YCLK
MEMTEST
M52-P
MEMORY B
MAB_0
MAB_1
MAB_2
MAB_3
MAB_4
MAB_5
MAB_6
MAB_7
MAB_8
MAB_9
MAB_10
MAB_11
MAB_12
MAB_13
MAB_14
MAB_15
DQMB#_0
DQMB#_1
DQMB#_2
DQMB#_3
DQMB#_4
DQMB#_5
DQMB#_6
DQMB#_7
QSB_0
QSB_1
QSB_2
QSB_3
QSB_4
QSB_5
QSB_6
QSB_7
QSB_0#
QSB_1#
QSB_2#
QSB_3#
QSB_4#
QSB_5#
QSB_6#
QSB_7#
ODTB0
ODTB1
CLKB0
CLKB0#
CKEB0
RASB0#
CASB0#
WEB0#
CSB0#_0
CSB0#_1
CLKB1
CLKB1#
CKEB1
RASB1#
CASB1#
WEB1#
CSB1#_0
CSB1#_1
G4
E6
E4
H4
J5
G5
F4
H6
G3
G2
D4
F2
H2
H3
F5
D5
B8
D9
G9
K7
M5
V2
W4
T9
B9
D10
H10
K6
N4
U2
U4
V8
B10
E10
G10
J7
M4
U3
V4
V9
D6
J4
B4
B5
C2
E2
D3
B2
D2
E3
N2
P3
L3
J2
L2
M2
K2
K3
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
A_BA0
A_BA1
MAA12
DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7
DQSA0
DQSA1
DQSA2
DQSA3
DQSA4
DQSA5
DQSA6
DQSA7
DQSA#0
DQSA#1
DQSA#2
DQSA#3
DQSA#4
DQSA#5
DQSA#6
DQSA#7
MCLKA0
MCLKA0#
MCKEA0
MRASA0#
MCASA0#
MWEA0#
MCSA0#0
MCLKA1
MCLKA1#
MCKEA1
MRASA1#
MCASA1#
MWEA1#
MCSA1#0
1
ODTA0 <8>
ODTA1 <9>
MCLKA0 <8>
MCLKA0# <8>
MCKEA0 <8>
MRASA0# <8>
MCASA0# <8>
MWEA0# <8>
MCSA0#0 <8>
MCLKA1 <9>
MCLKA1# <9>
MCKEA1 <9>
MRASA1# <9>
MCASA1# <9>
MWEA1# <9>
MCSA1#0 <9>
A A
GDDR2
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2005/12/22
3
Compal Secret Data
Deciphered Date
2006/12/22
2
Title
Size Document Number Rev
Custom
Date: Sheet
Compal Electronics, Inc.
M52-P Memory Interface
EFL50 LS-2766P
12/23/05 14:40:18
1
613
of
1.0
Page 7
5
C37
1 2
0.1U_0402_16V4Z
C54
1 2
D D
C C
L10
1 2
+1.8VS
BLM18PG121SN1D_0603
22U_0805_6.3V6M
L16
1 2
+1.8VS
B B
BLM18PG121SN1D_0603
+2.5VS
@
+VDDRH
2
1
+VDDRH0
22U_0805_6.3V6M
BLM15AG102SN1D_0402
L5
1 2
330U_V_6.3VM_R25
C268
0.1U_0402_16V4Z
2
C159
1
0.1U_0402_16V4Z
2
2
C270
1
1
22U_0805_6.3V6M
1
+
C154
0.1U_0402_16V4Z
2
L9
1 2
+2.5VS
BLM15AG102SN1D_0402
0.1U_0402_16V4Z
C149
0.1U_0402_16V4Z
C117
0.1U_0402_16V4Z
C107
0.1U_0402_16V4Z
C131
0.1U_0402_16V4Z
C122
0.1U_0402_16V4Z
C36
0.1U_0402_16V4Z
C103
0.1U_0402_16V4Z
C140
0.1U_0402_16V4Z
2
C153
1
2
C272
C271
1
0.1U_0402_16V4Z
+AVDD
2
C125
1
0.1U_0402_16V4Z
330U_V_6.3VM_R25
@
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
2
1
C129
+A2VDD
22U_0805_6.3V6M
1
+
C269
2
A A
4
C118
1 2
0.1U_0402_16V4Z
C67
1 2
0.1U_0402_16V4Z
C71
1 2
0.1U_0402_16V4Z
C60
1 2
0.1U_0402_16V4Z
C86
1 2
0.1U_0402_16V4Z
C82
1 2
0.1U_0402_16V4Z
C98
1 2
0.1U_0402_16V4Z
C126
1 2
0.1U_0402_16V4Z
C128
1 2
0.1U_0402_16V4Z
C84
1 2
0.1U_0402_16V4Z
C63
1 2
0.1U_0402_16V4Z
C127
1 2
0.1U_0402_16V4Z
C64
1 2
0.1U_0402_16V4Z
BLM15AG102SN1D_0402
+2.5VS
2
C144
1
0.1U_0402_16V4Z
1000mA for GDDR1
2400mA for GDDR3
+VDDRH0
+VDDRH
L6
1 2
C132
2
C143
1
C106
1 2
22U_0805_6.3V6M
C62
1 2
22U_0805_6.3V6M
C148
1 2
0.1U_0402_16V4Z
C112
1 2
0.1U_0402_16V4Z
C74
1 2
0.1U_0402_16V4Z
C124
1 2
0.1U_0402_16V4Z
C120
1 2
0.1U_0402_16V4Z
C123
1 2
0.1U_0402_16V4Z
C116
1 2
0.1U_0402_16V4Z
C156
1 2
22U_0805_6.3V6M
C146
1 2
0.1U_0402_16V4Z
C136
1 2
0.1U_0402_16V4Z
C139
1 2
0.1U_0402_16V4Z
+VDDID
12
0.1U_0402_16V4Z
+VDDID
C142
0.1U_0402_16V4Z
3
+1.8VS+1.8VS
+3VS+3VS
50mA
50mA
50mA
400mA
65mA
20mA
130mA
20mA
U2E
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR3
VDDR3
VDDR3
VDDR3
VDDR3
VDDR3
VDDR3
VDDR3
VDDR4
VDDR4
VDDR4
VDDR4
VDDR5
VDDR5
VDDR5
VDDR5
VDDRH0
VDDRH1
VSSRH0
VSSRH1
AVDD
AVDD
VDD1DI
A2VDD
A2VDD
NC_A2VDDQ
VDD2DI
M52-P
POWER
PCI EXPRESSCOREI/O INTERNALLVDS PLL, I/O
MEMORY I/OI/O
CLOCK
MEM I/O
CRT
TMDS
TV
PLL
PCIE_PVDD_12
PCIE_PVDD_12
PCIE_PVDD_12
PCIE_PVDD_12
PCIE_VDDR_12
PCIE_VDDR_12
PCIE_VDDR_12
PCIE_VDDR_12
PCIE_VDDR_12
PCIE_VDDR_12
PCIE_VDDR_12
PCIE_VDDR_12
PCIE_VDDR_12
PCIE_VDDR_12
PCIE_VDDR_12
PCIE_VDDR_12
PCIE_VDDR_12
PCIE_VDDR_12
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDD25
VDD25
VDD25
VDDPLL
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
LPVDD/VDDL0
LVDDR/VDDL0
LVDDR/VDDL0
LVDDR/VDDL0
LVDDR/VDDL1
LVDDR/VDDL1
LVDDR/VDDL1
LVDDR/VDDL2
LVDDR/VDDL2
LVDDR/VDDL2
TPVDD
TXVDDR
TXVDDR
TXVDDR
TXVDDR
PVDD
MPVDD
C1
J1
M1
R1
V1
AA1
A3
P9
J10
N9
P10
A9
Y10
P8
R9
Y9
J11
A21
M10
N10
Y8
J18
J19
K21
A12
H13
A15
J20
J13
K11
K19
A18
L23
K20
K24
L24
H19
A24
K13
J32
A30
C32
F32
L32
AB9
AB10
AA9
AC19
AD18
AC20
AD19
AD20
AJ5
AM5
AL5
AK5
AE2
AE3
AE4
AE5
A27
F1
A28
E1
AL25
AM25
AM23
AM16
AL16
AL14
AJ16
2
1
100mA
V23
N23
P23
U23
2000mA
N29
N28
N27
N26
N25
AL31
AM31
AM30
AL32
AL30
AM28
AL29
AM29
AM27
AC11
AC12
P14
U15
W14
W15
R17
R15
V15
V16
T16
U16
T17
U17
V14
R18
T18
V18
P18
P19
R19
W19
AD11
AC13
AC16
AC18
AC15
500mA
W10
T14
W17
P16
T23
K14
U19
AE19
AF20
AE20
AF19
AC21
AC22
AD22
AE21
AD21
AE22
20mA
AM8
150mA
AJ6
AK6
AL6
AM6
100mA
AJ14
20mA
A6
22U_0805_6.3V6M
2
C35
22U_0805_6.3V6M
1
22U_0805_6.3V6M
2
C59
1U_0603_10V6K
1
22U_0805_6.3V6M
2
C34
Close to U2.AL29
1
+VGA_CORE +VGA_CORE +VGA_CORE
50mA
20mA
+LPVDD
20mA
200mA
22U_0805_6.3V6M
2
1
VDDC+VDDCI=18A
C61
1 2
22U_0805_6.3V6M
C56
1 2
22U_0805_6.3V6M
C113
1 2
22U_0805_6.3V6M
C115
1 2
22U_0805_6.3V6M
C68
1 2
0.1U_0402_16V4Z
+VDDPLL
2
C267
1
22U_0805_6.3V6M
C135
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C55
1
22U_0805_6.3V6M
2
1
+MPVDD
BLM15AG102SN1D_0402
2
C138
1
2
1
C155
0.1U_0402_16V4Z
1 2
C137
0.1U_0402_16V4Z
2
1
Close to U2.N26
2
C193
1
1U_0603_10V6K
C72
1 2
0.1U_0402_16V4Z
C89
1 2
0.1U_0402_16V4Z
C104
1 2
0.1U_0402_16V4Z
C83
1 2
0.1U_0402_16V4Z
C102
1 2
0.1U_0402_16V4Z
L2
1 2
BLM15AG102SN1D_0402
C101
1U_0402_6.3V4Z
12
2
2
C85
1
1
0.1U_0402_16V4Z
2
C134
1
L8
2
C46
1U_0402_6.3V4Z
2
C51
1U_0402_6.3V4Z
1
2
C194
1
+1.2VS
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
2
C65
1
+2.5VS
2
0.1U_0402_16V4Z
C133
1
+VGA_CORE
1U_0402_6.3V4Z
2
1
2
C42
1U_0402_6.3V4Z
1
C70
1 2
0.1U_0402_16V4Z
C94
1 2
0.1U_0402_16V4Z
C119
1 2
0.1U_0402_16V4Z
C69
1 2
0.1U_0402_16V4Z
C99
1 2
0.1U_0402_16V4Z
22U_0805_6.3V6M
2
1
2
C88
1
0.1U_0402_16V4Z
2
C57
C58
1
0.1U_0402_16V4Z
22U_0805_6.3V6M
+PCIE_PVDD12
2
C53
C47
1U_0603_10V6K
1
2
C45
1U_0402_6.3V4Z
1
C87
0.1U_0402_16V4Z
C97
0.1U_0402_16V4Z
C44
2
C80
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C105
C75
1
0.1U_0402_16V4Z
+2.5VS
2
C73
0.1U_0402_16V4Z
1
+LPVDD
1 2
BLM15AG102SN1D_0402
1
C141
0.1U_0402_16V4Z
2
+PVDD
2
2
C96
1
1
1 2
BLM18PG121SN1D_0603
+PCIE_VDDR12B
+PCIE_VDDR12A
1 2
1 2
+
330U_D2E_2.5VM_R9
+VDD25
2
C108
0.1U_0402_16V4Z
1
+VDDCI
1 2
BLM18PG121SN1D_0603
2
C95
1
L7
L3
1 2
BLM15AG102SN1D_0402
C100
0.1U_0402_16V4Z
L13
L14
1 2
BLM18PG121SN1D_0603
L15
1 2
BLM18PG121SN1D_0603
12
L1
1 2
CHB1608U301_0603
C93
L4
1
+1.2VS
+1.2VS
+1.2VS
+2.5VS
+VGA_CORE
+2.5VS
+2.5VS
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2005/12/22
3
Compal Secret Data
Deciphered Date
2006/12/22
2
Title
Size Document Number Rev
Custom
Date: Sheet
Compal Electronics, Inc.
M52-P Power
EFL50 LS-2766P
12/23/05 14:40:19
1
713
of
1.0
Page 8
5
MCLKA0#
MCLKA0
R37
56_0402_1%
D D
C C
B B
@
R38
56_0402_1%
@
1 2
1 2
1
C92
470P_0402_50V7K
2
@
1K_0402_1%
64@
1K_0402_1%
64@
+1.8VS +1.8VS
1 2
10K_0402_5%
64@
12
R42
12
R47
MCLKA0#<6>
MCLKA0<6>
MCKEA0<6>
MCSA0#0<6>
MWEA0#<6>
MRASA0#<6>
MCASA0#<6>
ODTA0<6>
R98
(25mil)
1
C114
0.1U_0402_16V4Z
2
64@
MDA[0..63]<6,9>
DQSA[0..7]<6,9>
DQSA#[0..7]<6,9>
DQMA#[0..7]<6,9>
MAA[0..12]<6,9>
A_BA[0..1]<6,9>
A_BA0
A_BA1
MAA12
MAA11
MAA10
MAA9
MAA8
MAA7
MAA6
MAA5
MAA4
MAA3
MAA2
MAA1
MAA0
MCLKA0#
MCLKA0
MCKEA0
MCSA0#0
MWEA0#
MRASA0#
MCASA0#
DQMA#0
DQMA#1
ODTA0 ODTA0
DQSA0
DQSA#0
DQSA1
DQSA#1
+VR_VREF_0 +VR_VREF_1
4
MDA[0..63]
DQSA[0..7]
DQSA#[0..7]
DQMA#[0..7]
MAA[0..12]
A_BA[0..1]
U8
L2
BA0
L3
BA1
R2
A12
P7
A11
M2
A10/AP
P3
A9
P8
A8
P2
A7
N7
A6
N3
A5
N8
A4
N2
A3
M7
A2
M3
A1
M8
A0
K8
CK
J8
CK
K2
CKE
L8
CS
K3
WE
K7
RAS
L7
CAS
F3
LDM
B3
UDM
K9
ODT
F7
LDQS
E8
LDQS
B7
UDQS
A8
UDQS
J2
VREF
A2
NC#A2
E2
NC#E2
L1
NC#L1
R3
NC#R3
R7
NC#R7
R8
NC#R8
K4N56163QF-ZC33_FBGA84SAM64@
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDD1
VDD2
VDD3
VDD4
VDD5
VDDL
VSSDL
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10
VSS1
VSS2
VSS3
VSS4
VSS5
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
3
Default VRAM chip is SAM: SA00000YC00.
MDA8
B9
MDA9
B1
MDA11
D9
MDA10
D1
MDA12
D3
MDA13
D7
MDA14
C2
MDA15
C8
MDA2
F9
MDA1
F1
MDA0
H9
MDA3
H1
MDA5
H3
MDA7
H7
MDA6
G2
MDA4
G8
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
A1
E1
J9
M9
R1
J1
J7
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
A3
E3
J3
N1
P9
+1.8VS +1.8VS
+1.8VS +1.8VS
R108
0_0402_5%
64@
1 2
1
C234
0.1U_0402_16V4Z
2
64@
2
C235
1U_0603_10V6K64@
1
R100
1K_0402_1%
64@
R101
1K_0402_1%
64@
12
12
1 2
10K_0402_5%
64@
1
C231
0.1U_0402_16V4Z
2
64@
R99
A_BA0
A_BA1
MAA12
MAA11
MAA10
MAA9
MAA8
MAA7
MAA6
MAA5
MAA4
MAA3
MAA2
MAA1
MAA0
MCLKA0#
MCLKA0
MCKEA0
MCSA0#0
MWEA0#
MRASA0#
MCASA0#
DQMA#2
DQMA#3
DQSA2
DQSA#2
DQSA3
DQSA#3
2
U9
L2
BA0
L3
BA1
R2
A12
P7
A11
M2
A10/AP
P3
A9
P8
A8
P2
A7
N7
A6
N3
A5
N8
A4
N2
A3
M7
A2
M3
A1
M8
A0
K8
CK
J8
CK
K2
CKE
L8
CS
K3
WE
K7
RAS
L7
CAS
F3
LDM
B3
UDM
K9
ODT
F7
LDQS
E8
LDQS
B7
UDQS
A8
UDQS
J2
VREF
A2
NC#A2
E2
NC#E2
L1
NC#L1
R3
NC#R3
R7
NC#R7
R8
NC#R8
K4N56163QF-ZC33_FBGA84SAM64@
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDD1
VDD2
VDD3
VDD4
VDD5
VDDL
VSSDL
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10
VSS1
VSS2
VSS3
VSS4
VSS5
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
MDA29
B9
MDA28
B1
MDA31
D9
MDA30
D1
MDA27
D3
MDA24
D7
MDA26
C2
MDA25
C8
MDA19
F9
MDA18
F1
MDA17
H9
MDA16
H1
MDA20
H3
MDA23
H7
MDA22
G2
MDA21
G8
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
A1
E1
J9
M9
R1
J1
J7
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
A3
E3
J3
N1
P9
+VDDL1+VDDL0
1
C236
0.1U_0402_16V4Z
2
64@
R109
0_0402_5%
64@
1 2
2
C237
1
1
1U_0603_10V6K64@
+1.8VS +1.8VS
1
C49
A A
2
10U_0805_10V4Z
64@
64@
10U_0805_10V4Z
1
C48
2
5
64@
0.1U_0402_16V4Z
As close as ppossible to related pin
64@
0.1U_0402_16V4Z
1
C90
2
1
C77
2
0.1U_0402_16V4Z
64@
1
C78
2
1
C111
2
0.1U_0402_16V4Z
64@
4
64@
0.1U_0402_16V4Z
1
C76
2
1
C110
2
0.1U_0402_16V4Z
64@
64@
0.1U_0402_16V4Z
C109
0.1U_0402_16V4Z
64@
1
C91
2
1
2
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
10U_0805_10V4Z64@
2005/12/22
1
C167
2
10U_0805_10V4Z
64@
1
C166
2
0.1U_0402_16V4Z
64@
Compal Secret Data
Deciphered Date
1
C151
2
64@
0.1U_0402_16V4Z
1
C161
2
1
2
0.1U_0402_16V4Z
64@
2006/12/22
2
C163
64@
0.1U_0402_16V4Z
1
C162
2
64@
0.1U_0402_16V4Z
1
C152
2
0.1U_0402_16V4Z
64@
Title
Size Document Number Rev
Custom
Date: Sheet
1
C164
2
0.1U_0402_16V4Z
64@
Compal Electronics, Inc.
External GDDR2 A0
EFL50 LS-2766P
12/23/05 14:40:19
1
C158
2
64@
0.1U_0402_16V4Z
1
2
813
1
C157
0.1U_0402_16V4Z
64@
of
1
2
C150
1.0
Page 9
5
MCLKA1#
MCLKA1
R112
@
56_0402_1%
D D
R113
56_0402_1%@
1 2
1 2
MDA[0..63]<6,8>
DQSA[0..7]<6,8>
DQSA#[0..7]<6,8>
DQMA#[0..7]<6,8>
MAA[0..12]<6,8>
A_BA[0..1]<6,8>
MDA[0..63]
DQSA[0..7]
DQSA#[0..7]
DQMA#[0..7]
MAA[0..12]
A_BA[0..1]
4
3
2
1
Default VRAM chip is SAM: SA00000YC00.
1
C266
470P_0402_50V7K@
2
A_BA0
R115
1 2
A_BA1
R116
1 2
MAA12
R117
1 2
MAA11
R118
1 2
MAA10
R119
1 2
MAA9
R120
1 2
MAA8
R121
1 2
MAA7
R122
1 2
MAA6
R123
1 2
MAA5
R124
1 2
MAA4
R125
1 2
MAA3
R126
1 2
MAA2
R127
1 2
MAA1
R128
1 2
MAA0
R129
C C
B B
1 2
B1_A_BA0
0_0402_5%128@
B1_A_BA1
0_0402_5%128@
B1_MAA12
0_0402_5%128@
B1_MAA11
0_0402_5%128@
B1_MAA10
0_0402_5%128@
B1_MAA9
0_0402_5%128@
B1_MAA8
0_0402_5%128@
B1_MAA7
0_0402_5%128@
B1_MAA6
0_0402_5%128@
B1_MAA5
0_0402_5%128@
B1_MAA4
0_0402_5%128@
B1_MAA3
0_0402_5%128@
B1_MAA2
0_0402_5%128@
B1_MAA1
0_0402_5%128@
B1_MAA0
0_0402_5%128@
+1.8VS +1.8VS
12
R104
1K_0402_1%
128@
(25mil)
12
128@
R106
1K_0402_1%
1
2
MCLKA1#<6>
MCLKA1<6>
MCKEA1<6>
MCSA1#0<6>
MWEA1#<6>
MRASA1#<6>
MCASA1#<6>
ODTA1<6>
1 2
R102
10K_0402_5%128@
C232
0.1U_0402_16V4Z
128@
B1_A_BA0
B1_A_BA1
B1_MAA12
B1_MAA11
B1_MAA10
B1_MAA9
B1_MAA8
B1_MAA7
B1_MAA6
B1_MAA5
B1_MAA4
B1_MAA3
B1_MAA2
B1_MAA1
B1_MAA0
MCLKA1#
MCLKA1
MCKEA1
MCSA1#0
MWEA1#
MRASA1#
MCASA1#
DQMA#5
DQMA#4
ODTA1 ODTA1
DQSA5
DQSA#5
DQSA4
DQSA#4
+VR_VREF_2 +VR_VREF_3
U10
L2
BA0
L3
BA1
R2
A12
P7
A11
M2
A10/AP
P3
A9
P8
A8
P2
A7
N7
A6
N3
A5
N8
A4
N2
A3
M7
A2
M3
A1
M8
A0
K8
CK
J8
CK
K2
CKE
L8
CS
K3
WE
K7
RAS
L7
CAS
F3
LDM
B3
UDM
K9
ODT
F7
LDQS
E8
LDQS
B7
UDQS
A8
UDQS
J2
VREF
A2
NC#A2
E2
NC#E2
L1
NC#L1
R3
NC#R3
R7
NC#R7
R8
NC#R8
K4N56163QF-ZC33_FBGA84SAM128@
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDD1
VDD2
VDD3
VDD4
VDD5
VDDL
VSSDL
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10
VSS1
VSS2
VSS3
VSS4
VSS5
MDA38
B9
MDA32
B1
MDA39
D9
MDA34
D1
MDA35
D3
MDA36
D7
MDA33
C2
MDA37
C8
MDA45
F9
MDA41
F1
MDA46
H9
MDA40
H1
MDA43
H3
MDA44
H7
MDA42
G2
MDA47
G8
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
A1
E1
J9
M9
R1
J1
J7
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
A3
E3
J3
N1
P9
+1.8VS +1.8VS
+1.8VS +1.8VS
R110
0_0402_5%128@
1 2
+VDDL2 +VDDL3
1
128@
2
C238
0.1U_0402_16V4Z
2
C239
128@
1
1U_0603_10V6K
128@
128@
R105
1K_0402_1%
R107
1K_0402_1%
12
12
1
128@
2
B1_A_BA0
B1_A_BA1
B1_MAA12
B1_MAA11
B1_MAA10
B1_MAA9
B1_MAA8
B1_MAA7
B1_MAA6
B1_MAA5
B1_MAA4
B1_MAA3
B1_MAA2
B1_MAA1
B1_MAA0
1 2
R103
10K_0402_5%128@
C233
0.1U_0402_16V4Z
MCLKA1#
MCLKA1
MCKEA1
MCSA1#0
MWEA1#
MRASA1#
MCASA1#
DQMA#6
DQMA#7
DQSA6
DQSA#6
DQSA7
DQSA#7
U11
L2
BA0
L3
BA1
R2
A12
P7
A11
M2
A10/AP
P3
A9
P8
A8
P2
A7
N7
A6
N3
A5
N8
A4
N2
A3
M7
A2
M3
A1
M8
A0
K8
CK
J8
CK
K2
CKE
L8
CS
K3
WE
K7
RAS
L7
CAS
F3
LDM
B3
UDM
K9
ODT
F7
LDQS
E8
LDQS
B7
UDQS
A8
UDQS
J2
VREF
A2
NC#A2
E2
NC#E2
L1
NC#L1
R3
NC#R3
R7
NC#R7
R8
NC#R8
K4N56163QF-ZC33_FBGA84SAM128@
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDD1
VDD2
VDD3
VDD4
VDD5
VDDL
VSSDL
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10
VSS1
VSS2
VSS3
VSS4
VSS5
MDA57
B9
MDA59
B1
MDA56
D9
MDA58
D1
MDA61
D3
MDA62
D7
MDA60
C2
MDA63
C8
MDA53
F9
MDA50
F1
MDA55
H9
MDA49
H1
MDA51
H3
MDA52
H7
MDA48
G2
MDA54
G8
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
A1
E1
J9
M9
R1
J1
J7
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
A3
E3
J3
N1
P9
1
C240
128@
2
0.1U_0402_16V4Z
R111
128@
0_0402_5%
1 2
2
C241
128@
1
1U_0603_10V6K
+1.8VS +1.8VS
10U_0805_10V4Z128@
C242
1
2
C243
0.1U_0402_16V4Z
128@
5
1
2
A A
10U_0805_10V4Z128@
1
2
128@
C244
0.1U_0402_16V4Z
As close as ppossible to related pin
0.1U_0402_16V4Z
1
C245
2
128@
1
C246
2
0.1U_0402_16V4Z
128@
1
C247
2
128@
1
C248
2
0.1U_0402_16V4Z
128@
4
0.1U_0402_16V4Z
1
C249
2
128@
128@
1
C250
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C251
0.1U_0402_16V4Z
1
C252
2
1
2
128@
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
10U_0805_10V4Z128@
2005/12/22
1
C253
2
10U_0805_10V4Z128@
1
C254
2
Compal Secret Data
128@
1
C255
2
0.1U_0402_16V4Z
128@
Deciphered Date
1
C256
2
1
2
0.1U_0402_16V4Z
128@
2006/12/22
2
128@
C257
0.1U_0402_16V4Z
1
C258
2
128@
0.1U_0402_16V4Z
1
C259
2
0.1U_0402_16V4Z
128@
Title
Size Document Number Rev
Custom
Date: Sheet
1
C260
2
0.1U_0402_16V4Z
128@
Compal Electronics, Inc.
External GDDR2 A0
EFL50 LS-2766P
12/23/05 14:40:19
1
C261
2
128@
0.1U_0402_16V4Z
1
2
913
1
C262
0.1U_0402_16V4Z
128@
of
1
2
C263
1.0
Page 10
5
4
3
2
1
2
G
Q4
2N7002_SOT23
2
C225
22U_0805_6.3V6M@
1
Q6
+5VALW
12
1 2
13
D
S
BSS84_SOT23-3@
R131
1K_0402_5%@
1 2
1 3
R82
100K_0402_5%
R83
10K_0402_5%
0.01U_0402_16V7K
+3VS
2
1
Q5
2
1
C228
2
C226
10U_0805_10V4Z
@
R130
1 2
1K_0402_5%@
1 3
B+
susp#
2
4
Q3
G
2
+3VS
S
D
AOS3401_SOT23
1 3
1
C229
4.7U_0805_10V4Z
2
B+
susp#
+LCDVDD
susp# <3,11>
CHB2012U121_0805
1
C227
4.7U_0805_10V4Z
2
1
C230
0.1U_0402_16V4Z
2
B+
VGA_LVDSB0-<5>
VGA_LVDSB0+<5>
VGA_LVDSB1+<5>
VGA_LVDSB1-<5>
VGA_LVDSB2+<5>
VGA_LVDSB2-<5>
VGA_LVDSBC-<5>
VGA_LVDSBC+<5>
1 2
1 2
CHB2012U121_0805
I2C_CLK<4>
I2C_DAT<4>
LCD_ID#<3>
L11
L12
+3VS
H1
H_C236B276D157
@
LCD/PANEL BD. CONN.
I2C_CLK
I2C_DAT
VGA_LVDSB0VGA_LVDSB0+
VGA_LVDSB1+
VGA_LVDSB1-
VGA_LVDSB2+
VGA_LVDSB2-
VGA_LVDSBC- VGA_LVDSACVGA_LVDSBC+
LCD_ID#
H4
H_C315D157
@
1
Those are at button side
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2005/12/22 2006/12/22
3
Compal Secret Data
Deciphered Date
1
FIDUCAL
@
2
JP2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
ACES_88326-4000
H5
H_C315D157
@
FD1
1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
@
DAC_BRIG
1
@
2
2
4
4
6
6
8
8
10
10
12
12
14
14
16
16
18
18
20
20
22
22
24
24
26
26
28
28
30
30
32
32
34
34
36
36
38
38
40
40
CF2
SMD40M80
1
INVT_PWM
DISPOFF#
VGA_LVDSA0VGA_LVDSA0+
VGA_LVDSA1VGA_LVDSA1+
VGA_LVDSA2+
VGA_LVDSA2-
VGA_LVDSAC+
H2
H_C315D122
@
CF3
SMD40M80
@
AT LEAST 60 MIL
1
1
H3
H_C315D122
@
DAC_BRIG <3>
INVT_PWM <3>
DISPOFF# <3>
+LCDVDD
VGA_LVDSA0- <5>
VGA_LVDSA0+ <5>
VGA_LVDSA1- <5>
VGA_LVDSA1+ <5>
VGA_LVDSA2+ <5>VGA_ENVDD<5>
VGA_LVDSA2- <5>
VGA_LVDSAC- <5>
VGA_LVDSAC+ <5>
1
H6
H_C315D122
@
1
For IC FIXED
FD2
FIDUCAL
1
FIDUCAL
@
FD3
FD4
FIDUCAL
@
1
FD5
FIDUCAL
@
1
1
FIDUCAL
@
FD6
For Board FIXED
Title
LVDS Conn/ Screw Hole
Size Document Number Rev
Custom
Date: Sheet
Compal Electronics, Inc.
LVDS Connector & Screw
EFL50 LS-2766P
1
H7
H_C315D122
@
1
1
1.0
10 1312/23/05 14:40:19
of
+LCDVDD
12
R81
+3VS_D
JUMP_43X79
8
7
6
5
1
C274
2
2
8
D
7
D
6
D
5
D
SI4800DY_SO8
C276
10U_1206_16V4Z@
300_0402_5%
PJ6
112
U12
S
D
S
D
S
D
G
D
SI4800DY_SO8
10U_1206_16V4Z@
+1.8VS+1.8VS_D
PJ7
112
JUMP_43X79
U13
S
S
S
G
5
2
1
2
3
4
1
2
3
4
D D
C C
B B
1
2
A A
13
D
Q2
S
2
G
2N7002_SOT23
VGA_ENVDD
12
R84
10K_0402_5%
+3VS Delay
3VS_DELAY
2
C273
0.1U_0402_25V4K@
1
+1.8VS Delay
1.8VS_DELAY
2
C275
0.1U_0402_25V4K@
1
BSS84_SOT23-3@
Page 11
5
PJ1
2
112
JUMP_43X118
PJ2
+VGA_COREP
D D
+1.2VSP +1.2VS
2
JUMP_43X118
PJ5
2
JUMP_43X79
112
112
+VGA_CORE
+VGA_CORE
+VGA_COREP
1
C C
220U_6.3VM_R15
POWER_SEL
B B
0_0402_5%
@
1 2
PC12
PR20
PC18
+
2
<4>
1 2
0.1U_0402_16V7K
@
2
PQ6
G
PR23
0_0402_5%@
+5VALW
PR27
1 2
10K_0402_5%
1 2
13
D
S
+VGA_CORE
12
10K_0402_5%
PR26
PC20
RHU002N06_SOT323
@
2
G
12
0.01U_0402_25V7K
1.4UH_CEP125-1R4_15.5A_20%
12
PR25
0_0402_5%
12
12
PR5
1.15K_0402_1%
12
12
PR13
13
D
19.6K_0402_1%
PQ5
S
RHU002N06_SOT323
PC13
0.01U_0402_25V7K
PR16
20K_0402_1%
PL1
1 2
3
12
PR6
0_0402_5%
@
12
PR17
0_0402_5%
12
PR24
4.7_1206_5%
@
12
PC19
680P_0402_50V7K
@
susp#<3,10>
POWER_SEL Low
+VGA_CORE
PQ3
IRF7832_SO8
4
10U_1206_25VAK
4.7U_0805_6.3V6K
5
D8D7D6D
PQ1
IRF7821_SO8
S1S2S3G
4
5
D8D7D6D
S1S3G
S
4
2
PR11 10K_0402_1%
@
12
PC1
PC5
DAP202U_SOT323
0.1U_0402_16V7K
LX_VGA
1 2
PR21
1 2
0_0402_5%
W/O POWER PLAY
1.0V
12
PD1
PC10
1.27K_0402_1%
12
PC2
10U_1206_25VAK
2
BST_VGA
12
1 2
PR3
0_0603_5%
PR7
1 2
VSE_VGA
PC17
12
0.1U_0402_16V7K
3
12
PR1
51_1206_5%
1
3
PC8
0.01U_0402_25V7K
PC6
0.1U_0603_25V7K
PU1
12
12
SOFT1
6
BOOT1
DH_VGA
5
UGATE1
4
PHASE1
ISE_VGA
7
12
PR19
75K_0402_1%
ISEN1
2
LGATE1
3
PGND1
9
VOUT1
10
VSEN1
8
EN1
15
PG1
11
OCSET1
DL_VGA DL_1.2V
+5VALW
12
14
VIN
GND
1
PR2
2.2_0603_5%
1 2
28
SOFT2
VCC
BOOT2
UGATE2
PHASE2
ISEN2
LGATE2
PGND2
VOUT2
VSEN2
EN2
PG2/REF
OCSET2
DDR
13
ISL6227CA-T_SSOP28
17
0.01U_0402_25V7K
23
24
25
22
27
26
20
19
21
16
18
With POWER PLAY
High
0.95V
BST_1.2V
PC9
BST_1.2V-1B ST_VGA-1
ISE_1.2V
12
PC7
2.2U_0805_10V6K
12
1 2
PR4
0_0603_5%
DH_1.2V
LX_1.2V
1.27K_0402_1%
1 2
VSE_1.2V
12
PR18
100K_0402_1%
PR8
PC11
0.1U_0402_16V7K
12
12
PC16
0.1U_0402_16V7K
2
ISL6227B+
PC3
4.7U_1206_25V6K
5
4
5
4
PR12
1 2
68K_0402_1%
PR22
1 2
0_0402_5%
@
12
12
PC4
4.7U_1206_25V6K
D8D7D6D
PQ2
SI4800BDY_SO8
S1S2S3G
PL2
1 2
3UH_SPC-07040-3R0_5A_30%
D8D7D6D
PQ4
SI4810BDY-T1_SO8
S1S2S3G
+3VS_D+3VS_D
susp# <3,10>
PR9
0_0402_5%
PJ3
2
JUMP_43X118
PL3
1 2
FBMA-L11-322513-151LMA50T_1210
12
12
PC15
0.01U_0402_25V7K
12
PR15
0_0402_5%@
112
1
+1.2V
12
PR10
3.4K_0402_1%
12
PR14
10K_0402_1%
B+
+1.2VSP
1
+
PC14
220U_6.3VM_R15
2
PR5=1.15K,PR16=20K,PR13=19.6K PR5=1.15K,PR16=20K
A A
5
PJ3,PJ1,PJ2,PJ4 short
4
PJ3,PJ1,PJ2,PJ4 short
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2005/12/22 2006/12/22
3
Compal Secret Data
Deciphered Date
2
Title
Size Document Number Rev
Custom
Date: Sheet
Compal Electronics, Inc.
Power
Power
EFL50 LS-2766P
11 1312/23/05 14:40:19
1
of
1.0
Page 12
5
4
Version change list (P.I.R. List)
3
2
1
D D
=========== 2005/12 R0.2 ==================
01. Reserve +3VS and +1.8VS delay circuit and reserve Jump.
== To meet ATI PWR sequence.
Reserve PJ6, PJ7, U12, U13, C273, C274, C275, C276,
Q5, Q6, R130 and R131.
02. Change C42, C45, C46, C47 and C51, from 0.1U to 1U.
== For 3D hang issue.
03. Change C101, from 0.1U to 1U. == For 3D hang issue.
04. Add C44 as 330U == For 3D hang issue.
05. Delet e R63, 10K_0402_5% == PCIE TX power saving.
C C
B B
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2005/12/22
3
Compal Secret Data
Deciphered Date
2006/12/22
2
Title
Size Document Number Rev
Custom
Date: Sheet
Compal Electronics, Inc.
P.I.R.
EFL50 LS-2766P
12/23/05 14:40:19
1
12 13
of
1.0
Page 13
5
4
3
2
1
ZZZ
DA800005F10
--PCB ZKD LS-2766P
REV1 VGA/B
D D
DA800005F10
U8
SA00000JW00
--S IC D2 16M16/600
HY5PS561621AFP-33
FBGA
SA00000JW00
HYN64@
U9
SA00000JW00
--S IC D2 16M16/600
HY5PS561621AFP-33
FBGA
SA00000JW00
HYN64@
U10
SA00000JW00
--S IC D2 16M16/600
HY5PS561621AFP-33
FBGA
SA00000JW00
HYN128@
U11
SA00000JW00
--S IC D2 16M16/600
C C
HY5PS561621AFP-33
FBGA
SA00000JW00
HYN128@
B B
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2005/12/22
3
Compal Secret Data
Deciphered Date
2006/12/22
2
Title
Size Document Number Rev
Custom
Date: Sheet
Compal Electronics, Inc.
For BOM
EFL50 LS-2766P
12/23/05 14:40:19
1
13 13
of
1.0
Page 14
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