A
B
C
D
E
COMPAL CONFIDENTIAL
COVER SHEET
MODEL NAME :
1 1
COMPAL P/N :
PCB NO :
Revision :
DATE :
2 2
LS-1971
1.0
2003/10/22
DAT20
DA8AT20L110
DAT20 VGA Board Schematics Document
nVIDIA NV34M GeForce FX Go5200 Graphics Controller
3 3
4 4
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
D
DAT20 VGA Board Cover Sheet
Size Document Number Rev
Custom
DAT20 LS-1971
Date: Sheet
113Tuesday, November 11, 2003
E
of
1.0
A
B
C
D
E
BLOCK DIAGRAM
nVIDIA Graphic Controller
1 1
TV-OUT
AGP CONN.
PAGE 3
CRT
AGP
nVIDIA NV34M
AGP, DAC & LVDS
INTERFACE
PAGE 4
LVDS
LCD
CONNECTOR
PAGE 10
2 2
nVIDIA NV34M
POWER REGULATOR
+VGA_CORE
POWER INTERFACE
PAGE 6,7
+2.5VS
PAGE 11
nVIDIA NV34M
3 3
MEMORY INTERFACE
PAGE 5
CHANNEL A,B
4M32x4
64MB DDR SDRAM
NV34M (GeForce FX Go5200)
NV34U (GeForce FX Go5250)
NV31M (GeForce FX Go5600)
4 4
(BGA144)
PAGE 8,9
NV31FC (GeForce FX Go5650)
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
D
DAT20 VGA Board Block Diagram
Size Document Number Rev
Custom
DAT20 LS-1971
Date: Sheet
213Wednesday, October 22, 2003
E
of
1.0
A
B
C
D
E
ON/OFFBTN#
AGP_ST[0..2]4
AGP_AD[0..31]4
AGP_C/BE#[0..3]4
1 1
2 2
3 3
4 4
AGP_SBA[0..7]4
H2
H_S473X473D138L
1
H3
H_R315X310D138
1
H5
H_R250X245D158
1
H7
H_C166D166N
1
Change 08/15
(New add)
(EMI request)
AGP_ST[0..2]
AGP_AD[0..31]
AGP_C/BE#[0..3]
AGP_SBA[0..7]
PID310
PID210
PID110
PID010
H1
H_R473X315D138
1
H4
H_R315X345D177
1
H6
H_R354X355D158
1
A
DACA_VSYNC4
DACA_HSYNC4
DDC_CLK4
DDC_DATA4
AGP_PIPE#4
AGP_GNT#4
AGP_REQ#4
AGP_RBF#4
AGP_WBF#4
AGP_ADSTB14
AGP_ADSTB1#4
AGP_STOP#4
AGP_PAR4
AGP_DEVSEL#4
C3_STAT#4
PCI_PIRQA#4
B_PCIRST#4,10
SUS_STAT#4
R112 0_0402_5%
R113 0_0402_5%
R114 0_0402_5%
R115 0_0402_5%
VS_ON7,11
1 2
1 2
1 2
1 2
+5VALW
+12VALW
+5VS
+3VS
CF5
SMD40M80
CF2
SMD40M80
FD2
FIDUCAL
AGP_ST0
AGP_ST2
AGP_ST1
AGP_AD30
AGP_AD28
AGP_AD27
AGP_AD22
AGP_C/BE#3
AGP_AD26
AGP_AD18
AGP_C/BE#2
AGP_AD16
AGP_AD15
AGP_AD8
AGP_AD13
AGP_AD6
AGP_AD10
AGP_AD2
AGP_AD5
AGP_AD3
AGP_AD0
AGP_AD1
1
1
1
AGP 120 Pin Connector to M/B
JP5
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
41
41
43
43
45
45
47
47
49
49
51
51
53
53
55
55
57
57
59
59
61
61
63
63
65
65
67
67
69
69
71
71
73
73
75
75
77
77
79
79
81
81
83
83
85
85
87
87
89
89
91
91
93
93
95
95
97
97
99
99
101
101
103
103
105
105
107
107
109
109
111
111
113
113
115
115
117
117
119
119
QTC_CA-P4-010-120-SVN322
New : QTC_CA-P4-010-120-SVN322_120P
CF1
SMD40M80
CF9
SMD40M80
FD5
FIDUCAL
1
CF10
SMD40M80
1
1
CF7
SMD40M80
FD6
FIDUCAL
1
1
1
FD1
FIDUCAL
1
B
100
102
104
106
108
110
112
114
116
118
120
CF8
SMD40M80
1
CF3
SMD40M80
1
FD4
FIDUCAL
1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
CF6
SMD40M80
1
CF4
SMD40M80
1
FD3
FIDUCAL
1
AGP_SBA1
AGP_SBA0
AGP_SBA3
AGP_SBA2
AGP_SBA6
AGP_SBA7
AGP_SBA5
AGP_SBA4
AGP_AD31
AGP_AD29
AGP_AD24
AGP_AD19
AGP_AD20
AGP_AD25
AGP_AD21
AGP_AD23
AGP_AD17
AGP_C/BE#1
AGP_C/BE#0
AGP_AD9
AGP_AD11
AGP_AD14
AGP_AD7
AGP_AD12
AGP_AD4
LUMA 4
COMPS 4
CRMA 4
B4
G4
R4
AGP_SBSTB# 4
AGP_SBSTB 4
+5VALW
AGP_FRAME# 4
AGP_TRDY# 4
AGP_IRDY# 4
AGP_BUSY# 4
AGP_ADSTB0# 4
AGP_ADSTB0 4
CLK_AGP_66M 4
DAC_BRIG 10
ENBKL 4,10
BKOFF# 10
+1.5VS
B+B+
B+
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
+AGP_VREF
R116 0_0402_5%
1 2
Change 08/15 (New add)
C
LEOS_CD-ON_BTN#
HDD_LED#
CD_FDD_LED#
CAPS_LED#
PADS_LED#
NUM_LED#
LID_SW#
KSI2
KSO5
KSI3
KSO14
KSI7
KSI6
KSI5
KSI4
KSO9
KSI1
Switch Board CONN.
16
EC_UTXD/KSO17
KSI4
LEOS_CD-ON_BTN#
ON/OFFBTN#
14
12
10
8
6
4
2
ACES_88018-1610
INT_KBD CONN.
INVT_PWM 4,10
(Right)
KSO15
KSO10
KSO11
KSO14
KSO13
KSO12
KSO3
KSO6
KSO8
KSO7
KSO4
KSO2
KSI0
KSO1
KSO5
KSI3
KSI2
KSO0
KSI5
KSI4
KSO9
KSI6
KSI7
KSI1
(Left)
JP3
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
ACES_85202-2405
JP6
12
34
56
78
910
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
QTC_CA-P4-010-40-SVN322
(USERBTN_1) EC_UTXD/KSO17+KSI4
(USERBTN_2) EC_UTXD/KSO17+KSI5
JP1
KSI5
15
PWR_LED#
13
LID_SW#
11
NUM_LED#
9
PADS_LED#
7
CAPS_LED#
5
CD_FDD_LED#
3
HDD_LED#
1
D
PWR_LED#
TP_CLK
TP_DATA
EC_UTXD/KSO17
KSO3
KSO4
KSI0
KSO0
KSO1
KSO7
KSO2
KSO15
KSO6
KSO8
KSO13
KSO12
KSO11
KSO10
+5VS
New : QTC_CA-P4-010-40-SVN322_40P
(BLUE)/(GREEN)
(BLUE)/(GREEN)
(BLUE)/(GREEN)
(BLUE)/(GREEN)
(BLUE)/(GREEN)
(BLUE)/(GREEN)
(C38 / 030)
+5VALW
1
C1
0.1U_0402_16V4Z
2
Touch Pad Connector
+5VS
+5VS
1
C32
0.1U_0402_16V4Z
2
KSO8
KSO7
KSO4
KSO2
100P_1206_8P4C_50V8
KSI0
KSO1
KSO5
KSI3
100P_1206_8P4C_50V8
KSI2
KSO0
KSI5
KSI4
100P_1206_8P4C_50V8
Title
Size Document Number Rev
Custom
Date: Sheet
TP_DATA
TP_CLK
CP2
8 1
2
7
3
6
45
CP3
8 1
2
7
3
6
45
CP4
8 1
2
7
3
6
45
Compal Electronics, Inc.
DAT20 AGP CONNECTOR
DAT20 LS-1971
JP4
6
5
4
3
2
1
ACES_85201-0605
KSO15
8 1
KSO10
7
KSO11
6
KSO14
100P_1206_8P4C_50V8
KSO13
8 1
KSO12
7
KSO3
6
KSO6
100P_1206_8P4C_50V8
KSO9
8 1
KSI6
7
KSI7
6
KSI1
100P_1206_8P4C_50V8
E
CP6
CP1
CP5
2
3
45
2
3
45
2
3
45
313Wednesday, October 22, 2003
1.0
of
A
+3VS+3VS
12
12
Place close
to U2
Pin 2 & 3
@2200P_0402_50V7K
1 1
2 2
C36
AGP_AD[0..31]3
AGP_SBA[0..7]3
AGP_C/BE#[0..3]3
AGP_ST[0..2]3
+3VS
1
NV_THERMDA
2
NV_THERMDC
I2CC_SCL
I2CC_SDA
R86
10K_0402_5%
1 2
1 2
R90
@10K_0402_5%
0.1U_0402_16V4Z
1
C9
2
R27
2.2K_0402_5%
I2CC_SCL
I2CC_SDA
U4
2
D+
3
D-
8
SCLK
7
SDATA
@ADM1032ARM_RM8
AGP_AD[0..31]
AGP_SBA[0..7]
AGP_C/BE#[0..3]
AGP_ST[0..2]
STP_AGP#
AGP_BUSY#
(20mil)
1
C3
2
4.7U_0805_10V4Z
1 2
R102 220K_0402_5%
1 2
R97 220K_0402_5%
Selection Table For W180
3 3
Modulation
Setting
SST
Ratio
SS%
0
1
XTALOUTBUFF
+3VS
R10
1K_0402_5%
1 2
1 2
4 4
R9
1K_0402_5%
1.25%
3.75%
+SVDD
PLACE COLSE TO VGA
6
VDD
CLKOUT
X2FS1
SS%
GND
W180-01GT_SO8
3
A
Pin AJ5, AJ7,
U5
1
X1/CLK
8
FS2
R28
2.2K_0402_5%
1
VDD1
6
ALERT#
4
THERM#
5
GND
+SVDD
L1
1 2
FCM2012C-800_0805
1
C11
0.1U_0402_16V4Z
2
AGP_ADSTB0#
AGP_ADSTB1#
Close VGA ball
(AK29)
less than 250mils
+AGP_VREF
(20mil)
1
C124
0.1U_0402_16V4Z
2
1 2
5
R82 22_0402_5%
27
SPREAD_RATE
4
XTALSSIN
12
R14
10K_0402_5%
+3VS
NV_THERCTL#
+3VS
1 2
R11
@1K_0402_5%
+3VS
12
R30
10K_0402_5%
@0.1U_0402_16V4Z
Thermal
C81
1 2
10P_0402_50V8K
CLK_AGP_66M3
+3VS
AF26
Pull high
Support
AGP4X
63.4_0603_1%
+3VS
SWAPRDY_B
NV31,NV34 use.
NV18 not use.
+SVDD
R109 2.2K_0402_5%
1 2
R110 2.2K_0402_5%
1 2
B
AGP_AD0
AGP_AD1
AGP_AD2
12
12
I2CB_SCL
I2CB_SDA
AGP_AD3
AGP_AD4
AGP_AD5
AGP_AD6
AGP_AD7
AGP_AD8
AGP_AD9
AGP_AD10
AGP_AD11
AGP_AD12
AGP_AD13
AGP_AD14
AGP_AD15
AGP_AD16
AGP_AD17
AGP_AD18
AGP_AD19
AGP_AD20
AGP_AD21
AGP_AD22
AGP_AD23
AGP_AD24
AGP_AD25
AGP_AD26
AGP_AD27
AGP_AD28
AGP_AD29
AGP_AD30
AGP_AD31
AGP_C/BE#0
AGP_C/BE#1
AGP_C/BE#2
AGP_C/BE#3
CLK_AGP_66M
B_PCIRST#
AGP_REQ#
AGP_GNT#
AGP_PAR
AGP_STOP#
AGP_DEVSEL#
AGP_TRDY#
AGP_IRDY#
AGP_FRAME#
PCI_PIRQA#
AGP_WBF#
AGP_RBF#
AGP_SBSTB
AGP_SBSTB#
AGP_ADSTB0
AGP_ADSTB0#
AGP_ADSTB1
AGP_ADSTB1#
AGP_SBA0
AGP_SBA1
AGP_SBA2
AGP_SBA3
AGP_SBA4
AGP_SBA5
AGP_SBA6
AGP_SBA7
AGP_ST0
AGP_ST1
AGP_ST2
AGP_BUSY#
STP_AGP#
CRMA
LUMA
COMPS
DACB_HSYNC
DACB_VSYNC
DACB_RSET
XTALIN
XTALOUT
XTALSSIN
XTALOUTBUFF
NV_THERMDA
NV_THERMDC
+3VS
12
R26
@200_0402_5%
1
C33
2
R85
1 2
10_0402_5%
B_PCIRST#3,10
AGP_REQ#3
AGP_GNT#3
AGP_PAR3
AGP_STOP#3
AGP_DEVSEL#3
AGP_TRDY#3
AGP_IRDY#3
AGP_FRAME#3
PCI_PIRQA#3
AGP_WBF#3
AGP_RBF#3
AGP_PIPE#3
AGP_SBSTB3
AGP_SBSTB#3
AGP_ADSTB03
AGP_ADSTB0#3
AGP_ADSTB13
AGP_ADSTB1#3
R93 10K_0402_5%
AGP_BUSY#3
C3_STAT#3
CRMA3
LUMA3
COMPS3
R39
1 2
R59 10K_0402_5%
B
+AGP_VREF
I2CB_SCL
I2CB_SDA
AJ28
AK28
AH27
AK27
AJ27
AH26
AJ26
AH25
AH23
AJ23
AH22
AJ22
AJ21
AK21
AH20
AJ20
AG26
AE24
AG25
AG24
AF24
AG23
AE22
AF22
AE21
AG20
AG19
AF19
AE19
AF18
AG18
AE18
AJ24
AH19
AF25
AG22
AG12
AF15
AF13
AE15
AK18
AH17
AJ16
AJ17
AG16
AK16
AG15
AE10
AG17
AG14
AJ18
AJ19
AK13
AJ13
AK24
AJ25
AG21
AF21
AJ11
AH11
AJ12
AH12
AJ14
AH14
AJ15
AH15
AG13
AE16
AE13
AK29
AF16
AF12
AG11
AE2
AD2
AD1
AF3
AE3
AD3
AE7
AF6
AD4
Y5
AC4
AJ6
AH6
AJ7
AJ5
H2
H3
C2
C1
D1
E2
D2
I2CB_SCL 10
I2CB_SDA 10
DAC2
SSC
C
CLK
C
FPBCLKOUT#
FPBCLKOUT
DVOHSYNC
DVOVSYNC
DVOCLKOUT
DVOCLKOUT#
I2CC_SCL
I2CC_SDA
ZV PORT / EXT TMDS / GPIO / ROMLVDSTMDS
DVOCLKIN
IFPATXDO#
IFPATXDO
IFPATXD1#
IFPATXD1
IFPATXD2#
IFPATXD2
IFPATXD3#
IFPATXD3
IFPATXC#
IFPBTXD4#
IFPBTXD4
IFPBTXD5#
IFPBTXD5
IFPBTXD6#
IFPBTXD6
IFPBTXD7#
IFPBTXD7
IFPBTXC#
DACA_RED
DACA_GREEN
DACA_BLUE
DACA_HSYNC
DACA_VSYNC
DACA_RSET
I2CA_SCL
DAC1
I2CA_SDA
SWAPRDY_A
DACA_IDUMP
IFPCTXD0#
IFPCTXD0
IFPCTXD1#
IFPCTXD1
IFPCTXD2#
IFPCTXD2
IFPCTXC#
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
ROMA14
ROMA15
ROMCS#
VIPPCLK
VIPHCTL
VIPHCLK
VIPHAD0
VIPHAD1
VIPD0
VIPD1
VIPD2
VIPD3
VIPD4
VIPD5
VIPD6
VIPD7
DVOD0
DVOD1
DVOD2
DVOD3
DVOD4
DVOD5
DVOD6
DVOD7
DVOD8
DVOD9
DVOD10
DVOD11
DVODE
BUFRST#
STRAP0
STRAP1
STRAP2
STRAP3
IFPATXC
IFPBTXC
IFPCTXC
G5
F4
G4
H5
H4
J4
J5
J6
K4
K6
M2
M3
R2
R1
AF2
L4
M4
M5
P3
P2
J3
J2
K2
K1
L3
L2
N2
N1
AG2
AH1
AG3
AJ1
AH2
AK1
AJ3
AK3
AH4
AK4
AJ4
AH5
AD5
AD6
AE4
AJ2
AK2
AG6
AG7
B1
AG1
G1
G2
F2
F3
T4
U4
AA1
Y2
W3
V3
V4
U5
V1
W2
V5
W4
AB2
AB3
W6
Y6
AC2
AC3
Y3
AA2
AK10
AJ10
AJ9
DACA_HSYNC
AH9
DACA_VSYNC
AJ8
AG8
AG5
AF7
AF9
AG10
T2
R3
T3
U2
V2
U3
P4
P5
SPREAD_RATE
ENVDD
SUS_STAT#
POWER_SEL
NV_THERCTL#
GPIO9
TXOUT0ÂTXOUT0+
TXOUT1ÂTXOUT1+
TXOUT2ÂTXOUT2+
TXCLKÂTXCLK+
TZOUT0ÂTZOUT0+
TZOUT1ÂTZOUT1+
TZOUT2ÂTZOUT2+
TZCLKÂTZCLK+
DACA_RSET
DDC_CLK
DDC_DATA
ROMA14
ROMA15
VIPHCTL
VIPD2
VIPD3
VIPD4
VIPD5
VIPD6
VIPD7
DVOD2
DVOD3
DVOD8
DVOD9
DVO_HSYNC
I2CC_SCL
I2CC_SDA
DVOCLKIN
STRAP0
STRAP1
R
G
B
R80 10K_0402_5%
SWAPRDY_A
NV31,NV34 use.
NV18 not use.
R56
10K_0402_5%
Delete R38 & add R50.
TXOUT0- 10
TXOUT0+ 10
TXOUT1- 10
TXOUT1+ 10
TXOUT2- 10
TXOUT2+ 10
TXCLK- 10
TXCLK+ 10
TZOUT0- 10
TZOUT0+ 10
TZOUT1- 10
TZOUT1+ 10
TZOUT2- 10
TZOUT2+ 10
TZCLK- 10
TZCLK+ 10
R3
G3
B3
DACA_HSYNC 3
DACA_VSYNC 3
1 2
R83 130_0603_1%
12
U1A
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
C/BE#0
C/BE#1
C/BE#2
C/BE#3
PCICLK
PCIRST#
PCIREQ#
PCIGNT#
PCIPAR
PCISTOP#
PCIDEVSEL#
PCITRDY#
PCIIRDY#
PCIFRAME#
PCIINTA#
NC
AGPWBF#
AGPRBF#
AGPPIPE/ DBI_HI
NC/ DBI_LO
AGPSB_STB/ ADSTBF
AGPSB_STB#/ ADSTBS
AGPADSTB0/ ADSTBF0
AGPADSTB0#/ADSTBS0
AGPADSTB1/ ADSTBF1
AGPADSTB1#/ADSTBS1
AGPSBA0
AGPSBA1
AGPSBA2
AGPSBA3
AGPSBA4
AGPSBA5
AGPSBA6
AGPSBA7
AGPST0
AGPST1
AGPST2
AGPVREF
NC/AGPMBDET#
AGP_BUSY#
STP_AGP#
DACB_RED/CHROMA
DACB_GREEN/LUMA
DACB_BLUE/COMPOSITE
DACB_HSYNC
DACB_VSYNC
DACB_RSET
I2CB_SCL
I2CB_SDA
SWAPRDY_B
STEREO
DACB_IDUMP
XTALIN
XTALOUT
XTALSSIN
XTALOUTBUFF
THERMDA
THERMDC
JTAG[0]
JTAG[1]
JTAG[2]
JTAG[3]
JTAG[4]
NV34M_EPBGA701
nVIDIA
NV31/34
PCI/AGP
AGP4X/8X
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D
R118 @0_0402_5%
1 2
R117 0_0402_5%
1 2
ENVDD 10
R69 10K_0402_5%
DDC_CLK 3
DDC_DATA 3
ENBKLGPIO2
12
R119 @0_0402_5%
1 2
R73 10K_0402_5%
Change 08/15 (New add)
Low
High
Low
High
Low
High
12
Low
High
Low
High
+3VS
D
E
INVT_PWM 3,10
ENBKL 3,10
POWER_SEL 11
+3VS
ENBKLGPIO9
12
PCI_AD_SWAP: 0-RVSERSED 1-NORMAL
1
SUB_VENDOR: 0-SYSTEM BIOS 1-ADAPTER BIOS
2
R42 10K_0402_5%
RAM_CFG[3:0]
3
R48 @10K_0402_5%
0
R49 10K_0402_5%
4
SUS_STAT#
ENBKL
R41 10K_0402_5%
ENVDD
R43 10K_0402_5%
POWER_SEL
R66 @10K_0402_5%
L: Maximum battery savings
H: Maximum performance
STRAP0
12
12
12
STRAP1
(1101 = 4Mx32 DDR, DQS per byte)
(X000 = 8Mx32 DDR, DQS per byte) -Samsung
(X001 = 8Mx32 DDR, DQS per byte) -Hynix
DVOD2
DVOD3
12
R60 10K_0402_5%
1 2
1 2
1 2
SUS_STAT# 3
R4 10K_0402_5%
R36 10K_0402_5%
R37 @10K_0402_5%
1
5
R29 @10K_0402_5%
2
R53 @10K_0402_5%
3
CRYSTAL: (10)-27MHz
6
R44 10K_0402_5%
0
12
12
12
1
TVMODE: (01)-NTSC
7
0
R47 10K_0402_5%
1
AGP8X/4X: (0)-8X / (1)-4X
8
R50 10K_0402_5%
AGP_SIDEBAND: (0)-ENABLE
9
R6 10K_0402_5%
AGP_FASTWRITE: (0)-ENABLE
10
R65 10K_0402_5%
PCI_DEVID[3:0]
11
R45 10K_0402_5%
0
R7 10K_0402_5%
1
R8 @10K_0402_5%
2
R51 10K_0402_5%
3
BUS_TYPE: (1)-AGP
12
13
ROM TYPE: (00)-PARALLEL
0
R46 10K_0402_5%
1
R5 10K_0402_5%
12
12
12
12
(0100 NV34M / 1101 NV33M)
12
12
12
12
12
12
Compal Electronics, Inc.
Title
Size Document Number Rev
Custom
Date: Sheet
(0101 NV34M-Ultra / 1010 NV31M)
1
C41
22P_0402_50V8J
2
nVIDIA NV34M GeForce FX Go5200 AGP Interface
DAT20 LS-1971
DACA_VSYNC
DACA_HSYNC
VIPD2
VIPD6
DACB_VSYNC
DACB_HSYNC
DVOD9
VIPD7
DVOD8
VIPD4
VIPD5
VIPD3
DVO_HSYNC
VIPHCTL
ROMA14
ROMA15
1 2
27MHZ_16PF
1 2
R54 @2M_0402_5%
R31 10K_0402_5%
R57 10K_0402_5%
R34 10K_0402_5%
R35 10K_0402_5%
R38 @10K_0402_5%
R1 @10K_0402_5%
R63 @10K_0402_5%
R33 @10K_0402_5%
R2 @10K_0402_5%
R3 10K_0402_5%
R40 @10K_0402_5%
R55 10K_0402_5%
Y1
XTALOUTXTALIN
1
2
E
C38
22P_0402_50V8J
+3VS
+3VS
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
1.0
413Wednesday, October 22, 2003
of
A
B
C
D
E
NMDA0
NMDA1
NMDA2
NMDA3
NMDA4
NMDA5
NMDA6
NMDA7
NMDA8
NMDA9
NMDA10
NMDA11
NMDA12
NMDA13
NMDA14
NMDA15
NMDA16
NMDA17
NMDA18
NMDA19
NMDA20
NMDA21
NMDA22
NMDA23
NMDA24
NMDA25
NMDA26
NMDA27
NMDA28
NMDA29
NMDA30
NMDA31
NMDA32
NMDA33
NMDA34
NMDA35
NMDA36
NMDA37
NMDA38
NMDA39
NMDA40
NMDA41
NMDA42
NMDA43
NMDA44
NMDA45
NMDA46
NMDA47
NMDA48
NMDA49
NMDA50
NMDA51
NMDA52
NMDA53
NMDA54
NMDA55
NMDA56
NMDA57
NMDA58
NMDA59
NMDA60
NMDA61
NMDA62
NMDA63
NDQMA[0..7]
NDQSA[0..7]
NMAA[0..11]
NMDA[0..63]
U1B
N25
N27
N26
M25
K26
K27
J27
H27
N29
M29
M28
L29
J29
J28
H29
G30
K25
J26
J25
G26
F28
F26
E27
D27
H28
G29
F29
E29
C30
C29
B30
A30
AJ29
AJ30
AH29
AH30
AF29
AE29
AD29
AC28
AG28
AF27
AE26
AE28
AD25
AB25
AB26
AA25
AD30
AC29
AB28
AB29
Y29
W28
W29
V29
AC27
AB27
AA27
AA26
W25
V26
V27
V25
NV34M_EPBGA701
FBAD0
FBAD1
FBAD2
FBAD3
FBAD4
FBAD5
FBAD6
FBAD7
FBAD8
FBAD9
FBAD10
FBAD11
FBAD12
FBAD13
FBAD14
FBAD15
FBAD16
FBAD17
FBAD18
FBAD19
FBAD20
FBAD21
FBAD22
FBAD23
FBAD24
FBAD25
FBAD26
FBAD27
FBAD28
FBAD29
FBAD30
FBAD31
FBAD32
FBAD33
FBAD34
FBAD35
FBAD36
FBAD37
FBAD38
FBAD39
FBAD40
FBAD41
FBAD42
FBAD43
FBAD44
FBAD45
FBAD46
FBAD47
FBAD48
FBAD49
FBAD50
FBAD51
FBAD52
FBAD53
FBAD54
FBAD55
FBAD56
FBAD57
FBAD58
FBAD59
FBAD60
FBAD61
FBAD62
FBAD63
FBAA0
FBAA1
FBAA2
FBAA3
FBAA4
FBAA5
FBAA6
FBAA7
FBAA8
FBAA9
FBAA10
FBAA11
FBAA12
FBADQM0
FBADQM1
FBADQM2
FBADQM3
FBADQM4
FBADQM5
FBADQM6
FBADQM7
FBADQS0
FBADQS1
FBADQS2
FBADQS3
FBADQS4
FBADQS5
FBADQS6
FBADQS7
FBARAS#
MEMORY
INTERFACE A
FBACAS#
FBAWE#
FBACS0#
FBACS1#
FBACKE
FBACLK0
FBACLK0#
FBACLK1
FBACLK1#
FBABA0
FBABA1
FB_VREF
V30
U28
U29
T28
T29
T27
T30
T26
T25
R27
R25
R30
U24
L27
K29
G25
E28
AF28
AD27
AA30
Y27
M27
K30
G27
D30
AG30
AD26
AA29
W27
P28
P29
R28
U27
P27
N30
U21
V21
N21
P21
R26
R29
C28
NMAA0
NMAA1
NMAA2
NMAA3
NMAA4
NMAA5
NMAA6
NMAA7
NMAA8
NMAA9
NMAA10
NMAA11
NDQMA0
NDQMA1
NDQMA2
NDQMA3
NDQMA4
NDQMA5
NDQMA6
NDQMA7
NDQSA0
NDQSA1
NDQSA2
NDQSA3
NDQSA4
NDQSA5
NDQSA6
NDQSA7
NMRASA#
NMCASA#
NMWEA#
NMCSA0#
NMCSA1#
NMCKEA
NMCLKA0
NMCLKA0#
NMCLKA1
NMCLKA1#
NMA_BA0
NMA_BA1
A_REF
(20 mil)
NMRASA# 8
NMCASA# 8
NMWEA# 8
NMCSA0# 8
NMCSA1# 8
NMCKEA 8
NMA_BA0 8
NMA_BA1 8
1
C123
0.1U_0402_16V4Z
2
NDQMA[0..7]8
NDQSA[0..7]8
NMAA[0..11]8
1 1
2 2
3 3
4 4
NMDA[0..63]8
+2.5VS
12
12
NDQMB[0..7]9
NDQSB[0..7]9
NMDB[0..63]9
12
R99
@120_0402_5%
12
R98
@120_0402_5%
R104
1K_0402_1%
R103
1K_0402_1%
NMAB[0..11]9
NDQMB[0..7]
NDQSB[0..7]
NMAB[0..11]
NMDB[0..63]
NMCLKA0 8
NMCLKA0# 8
NMCLKA1 8
NMCLKA1# 8
1 2
R105 1K_0402_5%
1 2
R87 1K_0402_5%
NMDB0
NMDB1
NMDB2
NMDB3
NMDB4
NMDB5
NMDB6
NMDB7
NMDB8
NMDB9
NMDB10
NMDB11
NMDB12
NMDB13
NMDB14
NMDB15
NMDB16
NMDB17
NMDB18
NMDB19
NMDB20
NMDB21
NMDB22
NMDB23
NMDB24
NMDB25
NMDB26
NMDB27
NMDB28
NMDB29
NMDB30
NMDB31
NMDB32
NMDB33
NMDB34
NMDB35
NMDB36
NMDB37
NMDB38
NMDB39
NMDB40
NMDB41
NMDB42
NMDB43
NMDB44
NMDB45
NMDB46
NMDB47
NMDB48
NMDB49
NMDB50
NMDB51
NMDB52
NMDB53
NMDB54
NMDB55
NMDB56
NMDB57
NMDB58
NMDB59
NMDB60
NMDB61
NMDB62
NMDB63
F13
D13
E13
F12
E10
D10
D9
D8
B13
B12
C12
B11
B9
C9
B8
A7
F10
E9
F9
F7
C6
E6
D5
C4
C8
B7
B6
B5
A3
B3
A2
B2
B29
A29
B28
A28
B26
B25
B24
C23
E26
D26
E25
C25
E24
F22
E22
F21
A24
B23
C22
B22
B20
C19
B19
B18
D23
D22
D21
E21
F19
E18
D18
F18
NMCKEA
NMCKEB
U1C
FBCD0
FBCD1
FBCD2
FBCD3
FBCD4
FBCD5
FBCD6
FBCD7
FBCD8
FBCD9
FBCD10
FBCD11
FBCD12
FBCD13
FBCD14
FBCD15
FBCD16
FBCD17
FBCD18
FBCD19
FBCD20
FBCD21
FBCD22
FBCD23
FBCD24
FBCD25
FBCD26
FBCD27
FBCD28
FBCD29
FBCD30
FBCD31
FBCD32
FBCD33
FBCD34
FBCD35
FBCD36
FBCD37
FBCD38
FBCD39
FBCD40
FBCD41
FBCD42
FBCD43
FBCD44
FBCD45
FBCD46
FBCD47
FBCD48
FBCD49
FBCD50
FBCD51
FBCD52
FBCD53
FBCD54
FBCD55
FBCD56
FBCD57
FBCD58
FBCD59
FBCD60
FBCD61
FBCD62
FBCD63
NV34M_EPBGA701
FBCA0
FBCA1
FBCA2
FBCA3
FBCA4
FBCA5
FBCA6
FBCA7
FBCA8
FBCA9
FBCA10
FBCA11
FBCA12
FBCDQM0
FBCDQM1
FBCDQM2
FBCDQM3
FBCDQM4
FBCDQM5
FBCDQM6
FBCDQM7
FBCDQS0
FBCDQS1
FBCDQS2
FBCDQS3
FBCDQS4
FBCDQS5
FBCDQS6
FBCDQS7
FBCRAS#
FBCCAS#
MEMORY INTERFACE
B
FBCWE#
FBCCS0#
FBCCS1#
FBCCKE
FBCCLK0
FBCCLK0#
FBCCLK1
FBCCLK1#
FBCBA0
FBCBA1
C17
B17
C16
B16
D16
A16
E16
F16
D15
F15
A15
G17
D11
B10
D7
C5
C26
F24
B21
D20
D12
A10
E7
A4
A27
D24
A21
D19
C14
B14
C15
D17
D14
A13
K18
K17
K13
K14
E15
B15
NMAB1
NMAB2
NMAB3
NMAB4
NMAB5
NMAB6
NMAB7
NMAB8
NMAB9
NMAB10
NMAB11
NDQMB0
NDQMB1
NDQMB2
NDQMB3
NDQMB4
NDQMB5
NDQMB6
NDQMB7
NDQSB0
NDQSB1
NDQSB2
NDQSB3
NDQSB4
NDQSB5
NDQSB6
NDQSB7
NMRASB#
NMCASB#
NMWEB#
NMCSB0#
NMCSB1#
NMCKEB
NMCLKB0
NMCLKB0#
NMCLKB1
NMCLKB1#
NMB_BA0
NMB_BA1
NMAB0
A18
NMB_BA0 9
NMB_BA1 9
NMRASB# 9
NMCASB# 9
NMWEB# 9
NMCSB0# 9
NMCSB1# 9
NMCKEB 9
12
R94
@120_0402_5%
12
R88
@120_0402_5%
NMCLKB0 9
NMCLKB0# 9
NMCLKB1 9
NMCLKB1# 9
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
D
nVIDIA NV34M GeForce FX Go5200 DDR Interface
Size Document Number Rev
Custom
DAT20 LS-1971
Date: Sheet
513Wednesday, October 22, 2003
E
of
1.0
A
B
C
D
E
U1D
AA4
V6
U10
V10
T5
T6
Y4
W5
AA3
R4
P10
N10
R5
R6
L6
L7
M7
P6
P7
AD8
AD9
AE8
AB6
AB7
AF4
AE5
G24
AB4
AB5
AG9
AH8
F5
E4
D3
E3
C27
AK7
B4
B27
C11
C20
D6
D25
D29
E12
E19
F27
L28
M26
N5
W7
W26
Y7
IFABVPROBE
IFPABREST
+IFPABPLLVDD
+IFPABIOVDD
IFPCVPROBE
+IFPCPLLVDD
+IFPCIOVDD
VIPCAL_1
VIPCAL_2
DVOCAL_1
DVOCAL_2
R67 10K_0402_5%
1 2
R101 10K_0402_5%
1 2
+DACA/BVDD
DACAVREF
DACBVREF
1
C48
0.01U_0402_16V7K
2
+FB_DLLVDD
+PLLVDD
FBCAL_PD_VDDQ
NV31,NV34 use.
NV18 not use.
FBCAL_PU_GND
NV31,NV34 use.
NV18 not use.
FBCAL_TERM_GND
NV31 use (tie to GND).
NV18,NV34 not use.
FBCAL_CLK_GND
NV31 use.
NV18,NV34 not use.
AGP_VDD1
AGP_VDD2
AD11
AGPVDDQ
AD14
AGPVDDQ
AD17
AGPVDDQ
AD20
AGPVDDQ
AD23
AGPVDDQ
AE11
AGPVDDQ
AE14
AGPVDDQ
AE17
AGPVDDQ
AE20
AGPVDDQ
AE23
AGPVDDQ
L11
VDD
L13
VDD
L14
VDD
L17
VDD
L18
VDD
L20
VDD
N6
VDD
N11
VDD
N20
VDD
P11
VDD
P20
VDD
U11
VDD
U20
VDD
V11
VDD
V20
VDD
Y11
VDD
Y13
VDD
Y14
VDD
Y17
VDD
Y18
VDD
Y20
VDD
AA17
VDD
AA18
VDD
G14
VDD33
H6
VDD33
H7
VDD33
M6
VDD33
P24
VDD33
U6
VDD33
U7
VDD33
AC6
VDD33
AC7
VDD33
AD12
VDD33
AD15
VDD33
AD19
VDD33
AD22
VDD33
AD16
VDD33
N4
VD50CLAMP0
AE9
VD50CLAMP1
AA13
AGPCALPD_VDDQ
AA14
AGPCALPU_GND
AE12
AGP_PLLVDD
F8
FBVDDQ
F11
FBVDDQ
F14
FBVDDQ
F17
FBVDDQ
F20
FBVDDQ
F23
FBVDDQ
G8
FBVDDQ
G11
FBVDDQ
G20
FBVDDQ
G23
FBVDDQ
H24
FBVDDQ
H25
FBVDDQ
L24
FBVDDQ
L25
FBVDDQ
P25
FBVDDQ
U25
FBVDDQ
Y24
FBVDDQ
Y25
FBVDDQ
AC24
FBVDDQ
AC25
FBVDDQ
AA6
NC
AC5
NC
AF10
NC
AG29
NC
AE27
NC
G9
NC
Y28
NC
NV34M_EPBGA701
IFPABVPROBE
IFPABRSET
IFPABPLLVDD
IFPABPLLGND
IFPAIOVDD
IFPAIOGND
IFPBIOVDD
IFPBIOGND
IFPCVPROBE
IFPCRSET
IFPCPLLVDD
IFPCPLLGND
IFPCIOVDD
IFPCIOGND
VIPCAL_PD_VDDQ
VIPCAL_PU_GND
DVOVDDQ
DVOVDDQ
DVOVDDQ
DVOCAL_PD_VDDQ
DVOCAL_PU_GND
DVO_VREF
TESTMODE
TESTMECLK
I/O
POWER
DACB_VDD
DACB_VREF
DACA_VDD
DACA_VREF
FBCAL_PD_VDDQ
FBCAL_PU_GND
FBCAL_TERM_GND
FBCAL_CLK_GND
FB_DLLVDD
VIPVDDQ
VIPVDDQ
VIPVDDQ
PLLVDD
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
+1.5VS
1 1
+VGA_CORE
1 2
R75 0_0402_5%
2 2
+3VS
1 2
R74 0_0402_5%
+1.5VS
R84 49.9_0402_1%
1 2
1 2
R89 49.9_0402_1%
3 3
4 4
(15mil)
(15mil)
+5VS
AGPCALPD_VDDQ
AGPCALPU_GND
+AGP_PLLVDD
+2.5VS
C44 0.1U_0402_16V4Z
1 2
1 2
R71 1K_0402_5%
C39 0.1U_0402_16V4Z
1 2
1 2
R61 1K_0402_5%
1 2
R81 10K_0402_5%
1 2
R64 10K_0402_5%
+VIP/DVOVDDQ
R76 @49.9_0402_1%
R79 @49.9_0402_1%
NV31 use only.
NV18,NV34 not use.
NV31 use only.
NV18,NV34 not use.
R72 @49.9_0402_1%
R78 @49.9_0402_1%
12
1 2
1 2
1 2
TESTMECLK
NV31,NV34 use.
NV18 not use.
1
C47
0.01U_0402_16V7K
2
12
12
12
12
R7049.9_0402_1%
R6249.9_0402_1%
R68@0_0402_5%
R52@549_0402_1%
+DVO_VREF
+2.5VS
1
2
C120
4700P_0402_25V7K
+1.5VS
1
C89
4.7U_0805_10V4Z
2
(20mil)
1
C45
0.1U_0402_16V4Z
2
(15mil)
1
2
1
C62
0.1U_0402_16V4Z
2
+VIP/DVOVDDQ
12
R77
1K_0402_1%
12
R58
1K_0402_1%
L10
1 2
KC FBM-L11-201209-221LMAT_0805
C119
470P_0402_50V7K
+FB_DLLVDD
NV31,NV34 use.
NV18 not use.
1
2
+3VS
C110
0.022U_0402_16V7K
1
C76
0.022U_0402_16V7K
2
+IFPABPLLVDD
1
C64
470P_0402_50V7K
2
+IFPABIOVDD
1
C42
470P_0402_50V7K
2
+VIP/DVOVDDQ
1
C58
470P_0402_50V7K
2
+DACA/BVDD
1
C34
4.7U_0805_10V4Z
2
+PLLVDD
1
C17
4.7U_0805_10V4Z
2
+AGP_PLLVDD+FB_DLLVDD
1
C86
4.7U_0805_10V4Z
2
1
C98
0.022U_0402_16V7K
2
(15mil)
1
C63
4700P_0402_25V7K
2
(15mil)
1
C43
2
4700P_0402_25V7K
(20mil)
1
C52
4700P_0402_25V7K
2
(20mil)
1
C61
2
4700P_0402_25V7K
(15mil)
1
C14
2
4700P_0402_25V7K
(15mil)
1
C82
2
4700P_0402_25V7K
+5VS
1
C46
0.1U_0402_16V4Z
2
L8
1 2
KC FBM-L11-201209-221LMAT_0805
L3
1 2
KC FBM-L11-201209-221LMAT_0805
1
C35
4.7U_0805_10V4Z
2
L7
1 2
KC FBM-L11-201209-221LMAT_0805
L4
1 2
KC FBM-L11-201209-221LMAT_0805
1
C40
470P_0402_50V7K
2
L2
1 2
KC FBM-L11-201209-221LMAT_0805
1
C55
470P_0402_50V7K
2
L9
1 2
KC FBM-L11-201209-221LMAT_0805
1
C70
470P_0402_50V7K
2
1
2
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+AGP_PLLVDD
NV31,NV34 use.
NV18 not use.
C57
0.1U_0402_16V4Z
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
D
nVIDIA NV34M GeForce FX Go5200 Power Interface
Size Document Number Rev
Custom
DAT20 LS-1971
Date: Sheet
613Wednesday, October 22, 2003
E
of
1.0
A
B
C
D
E
B
+VGA_CORE
1
C83
4.7U_0805_10V4Z
2
+VGA_CORE
1
C73
470P_0402_50V7K
2
+2.5VS
1
C105
1U_0603_10V4Z
2
+2.5VS
1
C60
2
4700P_0402_25V7K
+3VS
1
C79
1U_0603_10V4Z
2
+3VS
1
C92
0.022U_0402_16V7K
2
+VGA_CORE
12
R20
@470_0402_5%
13
D
S
1
2
1
2
Q3
@2N7002_SOT23
VS_ON#
2
G
1
C93
4.7U_0805_10V4Z
2
1
C68
470P_0402_50V7K
2
C106
1U_0603_10V4Z
4700P_0402_25V7K
1
C77
2
C59
1U_0603_10V4Z
1
C101
2
4700P_0402_25V7K
+5VALW
12
13
D
S
1
C65
4.7U_0805_10V4Z
2
1
C69
470P_0402_50V7K
2
1
C74
1U_0603_10V4Z
2
1
C88
2
4700P_0402_25V7K
1
C51
0.1U_0402_16V4Z
2
4700P_0402_25V7K
1
C108
2
R21
@10K_0402_5%
Q4
@2N7002_SOT23
2
G
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1
C99
1U_0603_10V4Z
2
1
C95
470P_0402_50V7K
2
1
C104
0.1U_0402_16V4Z
2
1
2
1
C54
0.1U_0402_16V4Z
2
1
2
VS_ON 3,11
C
1
C66
1U_0603_10V4Z
2
1
C75
2
4700P_0402_25V7K
1
C56
0.1U_0402_16V4Z
2
C97
0.022U_0402_16V7K
1
C50
0.1U_0402_16V4Z
2
C49
4700P_0402_25V7K
1
C94
1U_0603_10V4Z
2
1
2
1
C111
0.1U_0402_16V4Z
2
1
C116
0.022U_0402_16V7K
2
1
C67
0.1U_0402_16V4Z
2
4700P_0402_25V7K
C90
1
2
1
C71
0.022U_0402_16V7K
2
1
C80
0.022U_0402_16V7K
2
1
C84
1U_0603_10V4Z
2
1
C96
4700P_0402_25V7K
2
C109
0.1U_0402_16V4Z
1
2
1
2
D
1
C87
0.1U_0402_16V4Z
2
C107
0.1U_0402_16V4Z
C85
0.022U_0402_16V7K
1
C91
0.1U_0402_16V4Z
2
1
C115
0.1U_0402_16V4Z
2
Compal Electronics, Inc.
Title
nVIDIA NV34M GeForce FX Go5200 Decoupling
Size Document Number Rev
Custom
1
C72
0.1U_0402_16V4Z
2
1
C114
0.1U_0402_16V4Z
2
DAT20 LS-1971
Date: Sheet
1
C78
0.1U_0402_16V4Z
2
1
C113
0.1U_0402_16V4Z
2
E
713Wednesday, October 22, 2003
of
1.0
U1E
A9
GND
A12
GND
A19
GND
A22
GND
A25
GND
C3
GND
C7
GND
C10
GND
1 1
2 2
3 3
C13
C18
C21
C24
D28
E11
E14
E17
E20
E23
F25
F30
G28
H11
H20
H26
K28
M30
N28
P26
U26
V28
W30
Y23
Y26
AA5
AA28
AB1
AB30
AC11
AC20
AC26
AD28
AE1
AE6
AE25
AE30
AF5
AF8
AF11
AF14
AF17
AF20
AF23
AF26
AG4
AG27
AH3
AH7
AH10
R24
T24
W24
AB24
AK30
GND
GND
GND
GND
D4
GND
GND
E5
GND
E8
GND
GND
GND
GND
GND
GND
F1
GND
F6
GND
GND
GND
G3
GND
GND
GND
GND
GND
J1
GND
J7
GND
J30
GND
K3
GND
K5
GND
GND
L5
GND
L8
GND
L23
GND
L26
GND
M1
GND
GND
N3
GND
GND
GND
T1
GND
GND
GND
W1
GND
GND
Y8
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
A6
GND
NC
NC
NC
NC
A1
NC1
NC2
G6
NC3
R7
NC4
T7
NC5
GROUND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
M12
M13
M14
M15
M16
M17
M18
M19
N12
N13
N14
N15
N16
N17
N18
N19
P12
P13
P14
P15
P16
P17
P18
P19
R12
R13
R14
R15
R16
R17
R18
R19
T12
T13
T14
T15
T16
T17
T18
T19
U12
U13
U14
U15
U16
U17
U18
U19
V12
V13
V14
V15
V16
V17
V18
V19
W12
W13
W14
W15
W16
W17
W18
W19
AH13
AH16
AH18
AH21
AH24
AH28
AK6
AK9
AK12
AK15
AK19
AK22
AK25
G12
NC
G15
NC
G16
NC
G19
NC
G22
NC
J24
NC
M24
NC
NV34M_EPBGA701
4 4
A
A
B
C
D
E
22U_1206_16V4Z Mitsubishi H=1.15mm
+2.5VS +2.5VS
0.1U_0402_16V4Z
1
C26
2
D10
D11E6E9F5F10G5G10H5H10J5J10K5K10
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
F6F7F8F9G6G7G8G9H6H7H8H9J6J7J8
NMAA0
NMAA1
NMAA2
NMAA3
NMAA4
NMAA5
NMAA6
NMAA7
NMAA8
NMAA9
NMAA10
NMAA11
NMA_BA0
NMA_BA1
NDQMA2
NDQMA1
NDQMA3
NDQMA0
NDQSA2
NDQSA1
NDQSA3
NDQSA0
NMRASA#
NMCASA#
NMWEA#
NMCSA0#
NMCKEA
22U_1206_16V4Z
1
C22
2
0.1U_0402_16V4Z
B4
B11D4D5D6D9
U7
VSSQ
N5
A0
N6
A1
M6
A2
N7
A3
N8
A4
M9
A5
N9
A6
N10
A7
N11
A8/AP
M8
A9
L6
A10
M7
A11
N4
BA0
M5
BA1
B3
DM0
H12
DM1
H3
DM2
B12
DM3
B2
DQS0
H13
DQS1
H2
DQS2
B13
DQS3
N13
VREF
M13
MCL
L9
RFU1
M10
RFU2
M2
RAS#
L2
CAS#
L3
WE#
N2
CS#
N12
CKE
M11
CK
M12
CK#
C4
NC
C11
NC
H4
NC
H11
NC
L12
NC
L13
NC
M3
NC
M4
NC
N3
NC
E7
VSS
E8
VSS
E10
VSS
K6
VSS
K7
VSS
K8
VSS
K9
VSS
L5
VSS
L10
VSS
E5
VSS
NDQMA[0..7]5
NDQSA[0..7]5
NMAA[0..11]5
+2.5VS
NMDA[0..63]5
12
R25
1K_0402_1%
12
R24
1K_0402_1%
1
2
1 1
2 2
3 3
NDQMA[0..7]
NDQSA[0..7]
NMAA[0..11]
NMDA[0..63]
NMA_BA05
NMA_BA15
(25mil) (25mil)
C30
0.1U_0402_16V4Z
NMCLKA0#5 NMCLKA1#5
NMCSA1#5
NMRASA#5
NMCASA#5
NMWEA#5
NMCSA0#5
NMCKEA5
NMCLKA0
NMCLKA0#
NMCSA1# CSA1# CSA1#
Reserved for
Hynix 8Mx32
12
R23
@120_0402_5%
1 2
R22
@0_0402_5%
1
C31
2
22U_1206_16V4Z
VR_VREF_1
As close as ppossible to related pin
0.1U_0402_16V4Z
VSSQ
VSSQ
B7
C6
B6
B5
C2
D3
D2
E2
K13
K12
J13
J12
G13
G12
F13
F12
F3
F2
G3
G2
J3
J2
K2
K3
E13
D13
D12
C13
B10
B9
C9
B8
C3
C5
C7
C8
C10
C12
E3
E12
F4
F11
G4
G11
J4
J11
K4
K11
D7
D8
E4
E11
L4
L7
L8
L11
1
2
NMDA21
NMDA22
NMDA20
NMDA23
NMDA19
NMDA18
NMDA17
NMDA16
NMDA8
NMDA9
NMDA10
NMDA11
NMDA15
NMDA14
NMDA12
NMDA13
NMDA25
NMDA24
NMDA27
NMDA26
NMDA28
NMDA29
NMDA30
NMDA31
NMDA0
NMDA3
NMDA2
NMDA1
NMDA4
NMDA6
NMDA5
NMDA7
1
C25
2
0.01U_0402_16V7K
+2.5VS +2.5VS
1
2
VSSQ
VSSQ
VSS TH
VSS TH
C28
VSSQ
VSSQ
VSS TH
VSS TH
VSSQ
VSS TH
1
C29
2
0.1U_0402_16V4Z
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
K4D263238E-GC36_FBGA144
J9
0.01U_0402_16V7K
C27
1
C23
2
0.01U_0402_16V7K
+2.5VS
12
R108
1K_0402_1%
12
R107
1K_0402_1%
1
C131
2
NMAA0
NMAA1
NMAA2
NMAA3
NMAA4
NMAA5
NMAA6
NMAA7
NMAA8
NMAA9
NMAA10
NMAA11
NMA_BA0
NMA_BA1
NDQMA5
NDQMA6
NDQMA4
NDQMA7
NDQSA5
NDQSA6
NDQSA4
NDQSA7
VR_VREF_2
NMRASA#
NMCASA#
NMWEA#
NMCSA0#
NMCKEA
0.1U_0402_16V4Z
1
C133
2
U3
N5
N6
M6
N7
N8
M9
N9
N10
N11
M8
L6
M7
N4
M5
B3
H12
H3
B12
B2
H13
H2
B13
N13
M13
L9
M10
M2
L2
L3
N2
N12
M11
M12
C4
C11
H4
H11
L12
L13
M3
M4
N3
E7
E8
E10
K6
K7
K8
K9
L5
L10
E5
0.1U_0402_16V4Z
1
C129
2
0.1U_0402_16V4Z
B4
B11D4D5D6D9
VSSQ
VSSQ
VSSQ
VSSQ
A0
A1
A2
A3
A4
A5
A6
A7
A8/AP
A9
A10
A11
BA0
BA1
DM0
DM1
DM2
DM3
DQS0
DQS1
DQS2
DQS3
VREF
MCL
RFU1
RFU2
RAS#
CAS#
WE#
CS#
CKE
CK
CK#
NC
NC
NC
NC
NC
NC
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS TH
VSS TH
F6F7F8F9G6G7G8G9H6H7H8H9J6J7J8
1
2
D10
D11E6E9F5F10G5G10H5H10J5J10K5K10
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
C134
0.01U_0402_16V7K
VSSQ
VSSQ
VSSQ
VSSQ
VSS TH
VSS TH
VSS TH
VSS TH
0.01U_0402_16V7K
1
C128
2
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B7
DQ0
C6
DQ1
B6
DQ2
B5
DQ3
C2
DQ4
D3
DQ5
D2
DQ6
E2
DQ7
K13
DQ8
K12
DQ9
J13
DQ10
J12
DQ11
G13
DQ12
G12
DQ13
F13
DQ14
F12
DQ15
F3
DQ16
F2
DQ17
G3
DQ18
G2
DQ19
J3
DQ20
J2
DQ21
K2
DQ22
K3
DQ23
E13
DQ24
D13
DQ25
D12
DQ26
C13
DQ27
B10
DQ28
B9
DQ29
C9
DQ30
B8
DQ31
C3
VDDQ
C5
VDDQ
C7
VDDQ
C8
VDDQ
C10
VDDQ
C12
VDDQ
E3
VDDQ
E12
VDDQ
F4
VDDQ
F11
VDDQ
G4
VDDQ
G11
VDDQ
J4
VDDQ
J11
VDDQ
K4
VDDQ
K11
VDDQ
D7
VDD
D8
VDD
E4
VDD
E11
VDD
L4
VDD
L7
VDD
L8
VDD
L11
VDD
VSS TH
VSS TH
VSS TH
K4D263238E-GC36_FBGA144
J9
1
C130
2
NMDA47
NMDA46
NMDA45
NMDA44
NMDA43
NMDA42
NMDA40
NMDA41
NMDA53
NMDA55
NMDA52
NMDA54
NMDA51
NMDA50
NMDA48
NMDA49
NMDA38
NMDA37
NMDA39
NMDA36
NMDA34
NMDA35
NMDA32
NMDA33
NMDA56
NMDA59
NMDA60
NMDA63
NMDA58
NMDA57
NMDA61
NMDA62
1
C132
2
0.01U_0402_16V7K
22U_1206_16V4Z
1
2
NMCLKA15NMCLKA05
1
C136
2
22U_1206_16V4Z
C135
0.1U_0402_16V4Z
1
C24
2
NMCLKA1
NMCLKA1#
1
C127
2
12
0.1U_0402_16V4Z
R106
@120_0402_5%
4 4
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
D
nVIDIA NV34M GeForce FX5200 DDR Channel A
Size Document Number Rev
Custom
DAT20 LS-1971
Date: Sheet
813Wednesday, October 22, 2003
E
of
1.0
A
B
C
D
E
+2.5VS +2.5VS
NDQMB[0..7]5
NDQSB[0..7]5
NMAB[0..11]5
1 1
2 2
NMDB[0..63]5
+2.5VS
12
R12
1K_0402_1%
12
R15
1K_0402_1%
1
2
NMCLKB05 NMCLKB15
3 3
NMCLKB0#5
NMCSB1#5
NDQMB[0..7]
NDQSB[0..7]
NMAB[0..11]
NMDB[0..63]
(25mil)
C16
0.1U_0402_16V4Z
NMCLKB0
NMCLKB0#
NMCSB1# CSB1# CSB1#
NMB_BA05
NMB_BA15
NMRASB#5
NMCASB#5
NMWEB#5
NMCSB0#5
NMCKEB5
12
R16
@120_0402_5%
1 2
R17
@0_0402_5%
Reserved for
Hynix 8Mx32
NMAB0
NMAB1
NMAB2
NMAB3
NMAB4
NMAB5
NMAB6
NMAB7
NMAB8
NMAB9
NMAB10
NMAB11
NMB_BA0
NMB_BA1
NDQMB2
NDQMB1
NDQMB3
NDQMB0
NDQSB2
NDQSB1
NDQSB3
NDQSB0
VR_VREF_3
NMRASB#
NMCASB#
NMWEB#
NMCSB0#
NMCKEB
22U_1206_16V4Z
1
C6
2
22U_1206_16V4Z
U6
N5
N6
M6
N7
N8
M9
N9
N10
N11
M8
L6
M7
N4
M5
B3
H12
H3
B12
B2
H13
H2
B13
N13
M13
L9
M10
M2
L2
L3
N2
N12
M11
M12
C4
C11
H4
H11
L12
L13
M3
M4
N3
E7
E8
E10
K6
K7
K8
K9
L5
L10
E5
1
C2
2
B4
B11D4D5D6D9
VSSQ
VSSQ
A0
A1
A2
A3
A4
A5
A6
A7
A8/AP
A9
A10
A11
BA0
BA1
DM0
DM1
DM2
DM3
DQS0
DQS1
DQS2
DQS3
VREF
MCL
RFU1
RFU2
RAS#
CAS#
WE#
CS#
CKE
CK
CK#
NC
NC
NC
NC
NC
NC
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
0.1U_0402_16V4Z
VSSQ
VSSQ
VSS TH
VSS TH
F6F7F8F9G6G7G8G9H6H7H8H9J6J7J8
As close as ppossible to related pin
0.1U_0402_16V4Z
1
C10
2
D10
D11E6E9F5F10G5G10H5H10J5J10K5K10
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
1
C7
2
0.1U_0402_16V4Z
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
K4D263238E-GC36_FBGA144
J9
VSSQ
B7
C6
B6
B5
C2
D3
D2
E2
K13
K12
J13
J12
G13
G12
F13
F12
F3
F2
G3
G2
J3
J2
K2
K3
E13
D13
D12
C13
B10
B9
C9
B8
C3
C5
C7
C8
C10
C12
E3
E12
F4
F11
G4
G11
J4
J11
K4
K11
D7
D8
E4
E11
L4
L7
L8
L11
1
C4
2
0.1U_0402_16V4Z
NMDB16
NMDB18
NMDB17
NMDB20
NMDB19
NMDB23
NMDB22
NMDB21
NMDB10
NMDB8
NMDB11
NMDB9
NMDB13
NMDB12
NMDB14
NMDB15
NMDB25
NMDB24
NMDB27
NMDB26
NMDB30
NMDB28
NMDB31
NMDB29
NMDB0
NMDB3
NMDB2
NMDB1
NMDB4
NMDB6
NMDB5
NMDB7
1
C5
2
1
C8
2
0.01U_0402_16V7K
+2.5VS
0.01U_0402_16V7K
1
C12
2
0.01U_0402_16V7K
+2.5VS
12
R95
1K_0402_1%
12
R96
1K_0402_1%
0.01U_0402_16V7K
1
C102
2
1
C118
2
1
C117
2
1
C122
2
0.1U_0402_16V4Z
1
C103
2
0.1U_0402_16V4Z
22U_1206_16V4Z
1
C13
2
1
C125
2
22U_1206_16V4Z
1
C126
2
0.1U_0402_16V4Z
1
C121
2
0.1U_0402_16V4Z
1
C112
2
0.01U_0402_16V7K
0.01U_0402_16V7K
B4
B11D4D5D6D9
D10
U2
VSSQ
NMAB0
NMAB1
NMAB2
NMAB3
NMAB4
NMAB5
NMAB6
NMAB7
NMAB8
NMAB9
NMAB10
NMAB11
NMB_BA0 NMDB51
NMB_BA1
NDQMB5
NDQMB6
NDQMB4
NDQMB7
NDQSB5
NDQSB6
NDQSB4
(25mil)
NDQSB7
VR_VREF_4
1
C100
0.1U_0402_16V4Z
2
NMRASB#
NMCASB#
NMWEB#
NMCSB0#
NMCKEB
NMCLKB1
12
R100
@120_0402_5%
NMCLKB1#5
NMCLKB1#
N10
N11
H12
B12
H13
B13
N13
M13
M10
N12
M11
M12
C11
H11
L12
L13
E10
L10
N5
A0
N6
A1
M6
A2
N7
A3
N8
A4
M9
A5
N9
A6
A7
A8/AP
M8
A9
L6
A10
M7
A11
N4
BA0
M5
BA1
B3
DM0
DM1
H3
DM2
DM3
B2
DQS0
DQS1
H2
DQS2
DQS3
VREF
MCL
L9
RFU1
RFU2
M2
RAS#
L2
CAS#
L3
WE#
N2
CS#
CKE
CK
CK#
C4
NC
NC
H4
NC
NC
NC
NC
M3
NC
M4
NC
N3
NC
E7
VSS
E8
VSS
VSS
K6
VSS
K7
VSS
K8
VSS
K9
VSS
L5
VSS
VSS
E5
VSS
D11E6E9F5F10G5G10H5H10J5J10K5K10
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
F6F7F8F9G6G7G8G9H6H7H8H9J6J7J8
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B7
DQ0
C6
DQ1
B6
DQ2
B5
DQ3
C2
DQ4
D3
DQ5
D2
DQ6
E2
DQ7
K13
DQ8
K12
DQ9
J13
DQ10
J12
DQ11
G13
DQ12
G12
DQ13
F13
DQ14
F12
DQ15
F3
DQ16
F2
DQ17
G3
DQ18
G2
DQ19
J3
DQ20
J2
DQ21
K2
DQ22
K3
DQ23
E13
DQ24
D13
DQ25
D12
DQ26
C13
DQ27
B10
DQ28
B9
DQ29
C9
DQ30
B8
DQ31
C3
VDDQ
C5
VDDQ
C7
VDDQ
C8
VDDQ
C10
VDDQ
C12
VDDQ
E3
VDDQ
E12
VDDQ
F4
VDDQ
F11
VDDQ
G4
VDDQ
G11
VDDQ
J4
VDDQ
J11
VDDQ
K4
VDDQ
K11
VDDQ
D7
VDD
D8
VDD
E4
VDD
E11
VDD
L4
VDD
L7
VDD
L8
VDD
L11
VDD
VSS TH
VSS TH
VSS TH
VSS TH
K4D263238E-GC36_FBGA144
J9
NMDB47
NMDB46
NMDB45
NMDB44
NMDB43
NMDB41
NMDB42
NMDB40
NMDB53
NMDB54
NMDB55
NMDB50
NMDB52
NMDB48
NMDB49
NMDB38
NMDB39
NMDB36
NMDB37
NMDB34
NMDB35
NMDB33
NMDB32
NMDB62
NMDB63
NMDB58
NMDB61
NMDB60
NMDB57
NMDB59
NMDB56
+2.5VS
4 4
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
D
nVIDIA NV34M GeForce FX5200 DDR Channel B
Size Document Number Rev
Custom
DAT20 LS-1971
Date: Sheet
913Wednesday, October 22, 2003
E
of
1.0
A
1 1
New add 08/08
ENVDD4
B_PCIRST#3,4
2 2
+3VS
5
U8
1
P
IN1
O
2
IN2
G
SN74AHC1G08DCKR_SC70
3
B
+12VALW
+LCDVDD
12
R13
100_0402_5%
Q1
13
D
2N7002_SOT23
2
G
S
LCDVDD_EN
4
2N7002_SOT23
R111
@100K_0402_5%
@
New add 08/08
1 2
+5VALW
1 2
R91
100K_0402_5%
1 2
2N7002_SOT23
13
D
2
G
S
Q5
13
2
G
Q6
R19
100K_0402_5%
D
S
C
12
R18
200K_0402_5%
SI2302DS_SOT23
1
C19
1000P_0402_50V7K
2
Q2
2
G
+3VS
13
D
S
1
C15
0.1U_0402_16V4Z
2
1
C20
4.7U_0805_10V4Z
2
+LCDVDD
1
2
D
C18
4.7U_0805_10V4Z
E
L5
LVDS Conn.
CHB2012U170_0805
B+
DAC_BRIGINVT_PWM
1
C137
680P_0402_50V7K
3 3
nVidia SmartDimmer Technology
680P_0402_50V7K
2
C138
1
2
BKOFF#3
ENBKL3,4
ENBKL
1 2
1 2
L6 CHB2012U170_0805
DAC_BRIG3
INVT_PWM3,4
I2CB_SDA4
I2CB_SCL4
TZOUT2+4
TZOUT2-4
TXOUT2+4
TXOUT2-4
TXCLK+4
TXCLK-4
TZOUT1+4
TZOUT1-4
D2
RB751V_SOD323
D1
@RB751V_SOD323
INVPWR_B+
DAC_BRIG
INVT_PWM
DISPOFF#
I2CB_SDA
I2CB_SCL
R32
10K_0402_5%
1 2
DISPOFF#
21
21
GPIO2 : PWM control signal.
GPIO9 : Backlight On/Off control signal.
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
ACES_88019-4000
ACES_88019-4000
1
C37
220P_0402_50V7K
2
JP2
12
34
56
78
910
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31
32
33
34
35
36
37
38
39
40
C
40mil
PID0 3
PID1 3
PID2 3
PID3 3
TZCLK+ 4
TZCLK- 4
TXOUT1+ 4
TXOUT1- 4
TZOUT0+ 4
TZOUT0- 4
TXOUT0+ 4
TXOUT0- 4
B++3VS
1
C53
0.1U_0603_50V4Z
2
+LCDVDD
1
C21
10U_1210_35V4Z
2
Compal Electronics, Inc.
Title
LVDS Connector
Size Document Number Rev
Custom
DAT20 LS-1971
D
Date: Sheet
10 13Thursday, October 23, 2003
E
of
1.0
A
1 1
12
12
5
D
G
4
5
D
G
4
PC2
876
PQ1
DDD
SI4800DY-T1_SO8
SSS
123
876
DDD
SSS
123
VS_ON3,7
PC1
2200P_0402_50V7K
+VGA_COREP
2 2
1
1
+
+
PD2
EP10QY03
POWER_SEL4
3 3
PC12
2
2
220U_D2_4VM
2 1
PR9
100K_0402_1%@
PC22
220U_D2_4VM
@RHU002N06_SOT323
12
12
PC13
4.7U_0805_6.3V6K
PR5
PQ4
2
G
12
PC17
@0.01U_0402_50V7K
1 2
@
@76.8K_0402_1%
1 2
1 2
13
D
S
PL2
1.8UH_D104C-919AS-1R8N_9.5A_20%
1 2
PQ3
SI4810DY_SO8
PR8
10K_0402_1%
12
PR12
PC19
100P_0402_50V8K
66.5K_0402_1%
4.7U_1206_25V6K
PD1
DAP202U_SOT323
0.1U_0603_25V7K
PC10
B
3
12
PR7
0_0402_5%
1 2
VS_ON
1
2
1 2
PR2
0_0402_5%
1 2
PR10
0_0402_5%
B++++
PR1
0_0402_5%
1U_0805_50V4Z
PC4
0.1U_0603_25V7K
PC8
25
26
27
24
28
1
2 12
11
1 2
12
1U_0805_50V4Z
PC9
12
12
423
BST1
V+GND
DH1
LX1
PU1
DL1
MAX1845EEI_QSOP28
CS1
OUT1
FB1 ON2
ON1
OVP
8
PC21
0.22U_0603_10V7K
SKIP
6
22
VCC
PR3
20_0603_5%
1 2
9
VDD
UVP
BST2
DH2
LX2
DL2
CS2
OUT2
FB2
PGOOD
TON
ILIM2
ILIM1
REF
PR13
10
249K_0402_1%
PR14
100K_0402_1%
12
21
19
18
17
20
16
15
14
7
5
13
3
+5VALW
12
12
12
PC3
4.7U_1206_25V6K
PR4
0_0402_5%
1 2
BST2.5A
DH2.5
12
PR15
100K_0402_1%
BST2.5B
12
C
0_0402_5%
1 2
PR16
100K_0402_1%
PC11
0.1U_0603_25V7K
12
PR6
DL2.5
12
PR11
0_0402_5%
VS_ON
LX2.5
8
G1
7
S1/D2
6
S1/D2
5
S1/D2
AO4912_SO8
PQ2
D1
D1
G2
S2
D
PL1
FBM-L18-453215-900LMA90T_1812
1 2
12
12
12
PC5
1
2
3
4
2200P_0402_50V7K
PL3
4.7UH_FDV0630-4.7UH_5.5A_20%
1 2
PC7
PC6
4.7U_1206_25V6K
4.7U_1206_25V6K
1
1
12
PC16
4.7U_0805_6.3V6K
+
+
2
PC15
PC14
2
220U_D2_4VM
+2.5VSP
2 1
220U_D2_4VM
B+
PD3
EP10QY03
VGA_CORE for NV34M
Delete PR5,PR9,PC17 and PQ4.
Fix 1.15V
Fix
POWER_SEL
H
4 4
L
POWER_SEL
H
L
PR12 =66.5K_00402_1%
PR8=10K_0402_1%
X6369438001
VGA_CORE for NV31M-FC(GF-FX-5650)
Delete PR5,PR9,PC17 and PQ4.
PR12 =66.5K_00402_1%
1.18V
PR8=12K_0402_1%
X6369430013
VGA_CORE for NV34M-Ultra.
PR5 =76.8K_0402_1%
1.28V
PR12 =66.5K_00402_1%
PR8=10K_0402_1% PR9=100K_0402_5%
1.15V
PQ4=RHU002N06_SOT323.
X6369430011
VGA_CORE for NV31M(GF-FX-5600)
PR5 =37.4K_0402_1%
1.27V
PR12 = Delete
PR8=10K_0402_1% PR9=100K_0402_5%
1.0V
PQ4=RHU002N06_SOT323.
A
X6369430012
PJP1
3MM
21
+VGA_CORE+VGA_COREP
PJP2
3MM
21
+2.5VS+2.5VSP
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
VGA_CORE Power
Size Document Number Rev
Custom
DAT20 LS-1971
Date: Sheet
D
11 13Wednesday, October 22, 2003
of
1.0
A
B
C
D
E
Version change list (P.I.R. List)
1 1
2003/08/01 Add U8 & reserved R111
Delete R38 & Add R50 for AGP 4X/2X.
2003/08/15 Reserved nVIDIA SmartDimmer Technology
Add R116 / R117 / R118 / R119
Add R112 / R113 / R114 / R115 (For EMI request)
HW
2003/08/19 Delete R33, add R45 for NV34M.
2 2
3 3
4 4
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
D
DAT20 VGA Board PIR List
Size Document Number Rev
Custom
DAT20 LS-1971
Date: Sheet
12 13Wednesday, October 22, 2003
E
of
1.0
A
B
C
D
E
Version change list (P.I.R. List) Page 1 of 1
Reason for change Rev. PG# Modify List B.Ver# PhaseFixed IssueItem
1 1
1
1.Change PQ4 from TR 2N7002 to RUH002N06_SOT23. DVT0.20.2 11None. Change size.
2
None. Change size from 0603 to 0402. 11
0.2
1.Change PC1,PC5,PR8,PR5 and PR12 size from R_0603 0.2 DVT
to R_0402.
1.Change PR15 from 200K to 100K.
3
Set O.C.P. point. No O.C.P. function.
0.2
11
2.Change PR14 from 22.1K to 100K.
3.Change PR13 from 0 to 249K.
0.2 DVT
4.Add 100K on PR16.
2 2
4
5
6
3 3
Transient fail.
The choke cannot meet spec.
For NV34M-Ultra and NV31M(GF-FX-5600),
The IC happen O.V.P. when POWER_SEL H to L.
Transient fail.
The choke cannot meet spec.
For NV34M-Ultra and NV31M(GF-FX-5600),
The IC happen O.V.P. when POWER_SEL H to L.
0.2 DVT1.Change PL2 from TMP 5UH to Toko 4.7UH.
11
0.2
0.21.Change PL3 from Toko 4.7UH to Toko 1.8UH. 110.2
DVT
0.3 11 1.Change PR17(100K) to PC17(0.01U). 0.3 PVT
4 4
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
D
PWR-PIR
Size Document Number Rev
Custom
DAT20 LS-1971
Date: Sheet
13 13Wednesday, October 22, 2003
E
of
1.0
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