Compal LA-H901P Schematics

A

1 1

B

C

D

E

Compal Confidential

2 2

FH50P MB Schematics Document

AMD Picasso Platform

AMD R18M-G1-90

3 3

LA-H901P REV:1A

2019-05-13

4 4

Security Classif ication

Security Classif ication

Security Classif ication

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Shared with Comp al

Shared with Comp al

A

B

Shared with Comp al

2018/ 12 /18 2019/12/ 18

2018/ 12 /18 2019/12/ 18

2018/ 12 /18 2019/12/ 18

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

COVER PAGE

COVER PAGE

COVER PAGE

FH50P M/B LA-H901P

FH50P M/B LA-H901P

FH50P M/B LA-H901P

E

1A

1A

1A

1 99Wednesd ay, May 15, 2019

1 99Wednesd ay, May 15, 2019

1 99Wednesd ay, May 15, 2019

A

Compal Confidential

Model Name : FH50P

B

C

D

E

(Channel A)

1 1

GPU

GDDR5 x4pcs

page 35~36

2 2

128-bits

S4 Package
RX560X : R18M-G1-90

page 27~33

Port 1

eDP Conn.

page 38 page 40

PEG x8

Display Port

Port 0

HDMI Conn.

AMD

Picasso

Memory BUS(DDR4)

1.2V DDRIV
2400Mhz

USB2.0

Port 3

USB3.0

260pin DDRIV SO-DIMM

Port 1

Type-C
Conn.

page 42~43

Type-A (CHG)
Conn.

Port 1

page 71

page 23

Port 2

Type-A
Conn.

Port 2Port 3

AMD FP5 APU

GA 1140-balls

PCIE

page 68~70

SSD1
NGFF Conn.

Port 4

LAN
RTL8118ASA

page 51

Port 5Port 0, 1, 2, 3

WLAN/BT
NGFF Conn.

page 52

SPI

Transformer

RJ45

page 51

3 3

page 10

BIOS (8M, 1.8V)

Fan Control

page 77

B

page 6~12

ENE
KBC9022

page 63

Int.KBD

LPC

page 58

PS2

I2C

Port 3

HD Audio

SATA III

PTP

page 63

HDD
Conn.

Port 0

page 67

Port 1

page 68

SSD2
NGFF Conn.

page 72

(Channel B)

260pin DDRIV SO-DIMM

Port 4

Type-A
(SUB)

page 38

Int. DMIC
on Camera

page 73

Port 0

Camera

Finger
Print

page 66

Audio
ALC255

page 38

Touch
Screen

Int. Speaker
Conn.

page 56

page 24

Port 5

page 38

page 56

USB2.0 Hub

page 75

WLAN/BT
NGFF Conn.

UAJ
on Sub/B

Port 1Port 2Port 3

page 52

page 73

RTC CKT.

Power On/Off CKT.

4 4

DC/DC Interface CKT.

Power Circuit DC/DC

VRAM Config Table

page 11

page 63

page 78

page 82~96

page 29

A

Sub Board

LS-H901 IO/B

LS-H502 Hall Sensor/B

page 73

page 66

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2018/ 12/18 2019/12/18

2018/ 12/18 2019/12/18

2018/ 12/18 2019/12/18

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

BLOCK DIAGRAMS

BLOCK DIAGRAMS

BLOCK DIAGRAMS

FH50P M/B LA-H901P

FH50P M/B LA-H901P

FH50P M/B LA-H901P

E

1A

1A

2 99Wednesday, May 15, 20 19

2 99Wednesday, May 15, 20 19

2 99Wednesday, May 15, 20 19

1A

A

B

C

D

E

Voltage Rails

+19V_VIN

+19VB

+APU_CORE OFFON

1 1

2 2

+1.8VALW

+1.8VS

+2.5V 2.5V power rail for APU and DDR ON ON

+1.2V

+0.6VS

+3VALW

+3VS

+5VALW ONONON

+5VS

+RTC_APU

+3VSDGPU

+1.8VSDGPU

+1.5VSDGPU VGA power

+VDDCI

+VGA_CORE

APU SMBus/I2C Address Table

Master

I2C Port 0
(+1.8VS)

I2C Port 1
(+1.8VS)

I2C Port 2
(+3VS)

SBMus Port 0

3 3

(+3VS)

I2C Port 3
(+3VALW)

SMBus Port 1
(+3VALW)

DescriptionPower Plane

Adapter power supply (19V)

AC or battery power rail for power circuit.

Core voltage for APU

Core voltage for APU ON+APU_CORE_SOC

1.8V always on power rail

1.8V switched power rail

0.6V switched power rail for DDR terminator

3.3V always on power rail

3.3V switched power rail

5V always on power rail

5V switched power rail

RTC power

VGA power

VGA power

VGA power

VGA power

Device

JDIMM1

JDIMM2

PTP
(Synaptics)

PTP
(ELAN)

Address[7:1]

0101 0000b
50h

0101 0001b
51h

0010 1100b
2Ch

0001 1111b
15h

Address [7:0]

Write

1010 0000b
A0h

1010 0010b
A2h

0101 1000b
58h

0011 1110b
3Eh

ON

ON ON

ON

ON

ON

ON

ON

ON

ON

1010 0001b
A1h

1010 0011b
A3h

0101 1001b
59h

0011 1111b
3Fh

ON ON

OFF OFF

OFF OFF

ONON1.2V power rail for APU and DDR

OFF OFF

ONON

OFF OFF

OFF OFF

OFF OFF

Read

BOARD ID Table

S5S3S0

ONONON

OFF

OFF

OFF

OFF

OFF

ON

ONONON

OFF+3V_LAN 3.3V LAN IC power ON ON

OFF+TP_VCC 3.3V Touch Pad power ON ON

OFFOFF

OFFOFFON

OFFOFF

OFFOFF

OFFON3.3V Finger Print power+FP_VCC ON

Board ID

0

PCB Revision

EVT

1 PVT

MP2

9 With RGB BL

BOM Structure Table

BTO ItemBOM Structure

@
EMC@/@EMC@
45@
CONN@
JP@
RS@
TP@
LDO@/SWR@
R5/R7APUQC@
HDT@
DIS@
RX560@
EVT@/PVT@/MP@

TMS@
KBLED@/LED14P@

X76_S4G@
X76_H4G@

Unpop

EMI/ESD Pop/Unpop

HDMI Royalty

Mechanical Connector

Jump

R-Short

Test Point

RTL8118ASA Switching-Mode only

APU PN Refer p.6

HDT Circuits

VGA Circuits

R18M-G1-90 GPU / Circuit

Test BOM for EVT/PVT/MP

Thermal Sensor

Keyboard back light / RGB back light

VRAM Config Refer p.33

VRAM Config Refer p.33

EC SMBus Address Table

SMBus Port 1
(+3VALW)

4 4

SMBus Port 2
(+3VS)

SMBus Port 3
(+3VALW)

Smart Battery

Charger IC
(BQ24735)

APU Temp.
(TSI)

GPU Temp.

Thermal Sensor
(Remote1 GPU)
(Remote2 APU)

LED driver 1100 0000b

A

0000 1011b
0Bh

0000 1001b
09h

0100 1100b
4Ch

0100 0001b
41h

0001 0110b
16h

0001 0010b
12h

1001 1000b
98h

1000 0010b
82h

1001 1010b
9Ah

C0h

0001 0111b
17h

0001 0011b
13h

1001 1001b
99h

1000 0011b
83h

1001 1011b
9Bh

1100 0001b
C1h

B

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

Board ID / SKU ID Table for AD channel

POWER SEQUENCE

G-A

G-B

G-C

G-D

+RTCBATT

EC_ON

+5VALW

3V_EN

+3VALW

0.9_1.8VALW_PWREN

+1.8VALW/+0.9VALW

SYSON

+1.2V/+2.5V

SUSP#

+5VS/+3VS/+1.8VS/+0.6VS

0.9VS_PWR_EN#

+0.9VS

VR_ON

+APU_CORE

+APU_CORE_SOC

VGA POWER SEQUENCE

PE_GPIO1/VGA_ON

+3VSDGPU

+1.8VSDGPU

VGA_ON_B

+VDDCI

+VGA_CORE

DGPU_PWRGOOD

+1.5VSDGPU

PE_GPIO0

Compal Secret Data

Compal Secret Data

2018/ 12/18 2019/12/18

2018/ 12/18 2019/12/18

2018/ 12/18 2019/12/18

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

NOTES LIST

NOTES LIST

NOTES LIST

FH50P M/B LA-H901P

FH50P M/B LA-H901P

FH50P M/B LA-H901P

E

3 99Wednesday, May 15, 20 19

3 99Wednesday, May 15, 20 19

3 99Wednesday, May 15, 20 19

1A

1A

1A

5

PJP101
AC-IN

+19V_VIN

+17.4V_BATT

D D

P

JP201

DC-IN

C C

24810mA

+

19VB

P

U301

5243mA

638mA

237mA

2311mA

PU801

PU501

PU601

PU401

+APU_CORE

+

APU_CORE_SOC

+1.2V

+0.6VS

5000mA

+

0.9VALW

9500mA

1200mA

+3VLP

KB9022

B B

+5VALW

14700mA3869mA

PU401

To VGA
+VGA_CORE
+VDDCI/VDD_08
+1.35VSDGPU

A A

2000mA

5

3579mA
169mA
474mA

+INVPWR_B+

L

X1

Panel BackLight

13347mA

+

4

3VALW

4

2026mA

8330mA

4200mA

PU602

U2

U3

+1.8VALW

2

T

o VGA10mA

+

3VS_SSD1

+5VS

660mA

3

A

+

2.5V

+

1.2V

+0.6VS

+3VS_SSD1

+

3V_LAN

+TP_VCC

+

3VS_WLAN

+

3V_HUB

+LCDVDD

1.2V_HDMI

+3VS_CAM

+

5VS_BL

5VALW_MUX

+5VS_HDD

+VCC_FAN1
+VCC_FAN2

+5VS_PVDD

+

FP_VCC

+TS_PWR

PU Power Rail

VDDCR_VDD @0.65-TBD

VDDCR_SOC @0.72-TBD

VDD_33 @0.25A

VDD_18 @2.0A

VDDP @4.0A

VDDIO_MEM_S3 @6.0A

VDD_33_S5 @0.25A

VDD_18_S5 @0.5A

VDDIO_AUDIO @0.2A

VDDP_S5 @1.0A

VDDBT_RTC_G @0.045mA

DDR4 SO-DIMM1/SO-DIMM2

+2.5V

+1.2V

+0.6VS

S

ATA Redriver*2 (M.2 & HDD)

M

.2 PCIE SSD

LAN RTL8118ASA

Touch Pad

WLAN

U

SB HUB

P

anel Logic

M

.2 SATA SSD

H

DMI Retimer

Camera

KB Light

T

ype C

RTS5441E

USB3.0(Charger)

U

SB3.0US13

USB/B

HDD

FAN1/FAN2

Audio

Finger Print

Touch Screen

2

2

2

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

70000mA

+APU_CORE

13000mA

+APU_CORE_SOC

250mA

+3VS

2000mA

+1.8VS

4

000mA

2200mA

528mA

+

3VS

U4

T

UV8

J

RTC1

PU502

U

L1

RL2

U13

R

M101

UM3

R

S148

U

R

X18

U

2616

US14

U

S11

US12

JIO2

RO4

RF4/RF7

LA1

UK6

R

X17

o VGA

X1

+0.9VS

+

1.8VS

+

RTCVCC

+2.5V

3

1013mA

U

C8

+RTC_APU_R

U

1302

4000mA

+0.9VS

6000mA

+1.2V

250mA

+3VALW

500mA

+1.8VALW

200mA

+1.8VS

1000mA

+0.9VALW

0.045mA

+RTC_APU_R

528mA

4160mA

1500mA

280mA

2790mA

300mA

30mA

1500mA

5

9mA

1500mA

+

200mA

200mA

200mA

+

250mA

3000mA

+USB3_VCCC

2000mA

+USB3_VCCA

2

000mA +USB3_VCCB

2500mA

1500mA

1000mA

1500mA

1

00mA

100mA

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

R18M-G1-90

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Group C, S0 dom ain

Group B, S0 dom ain

Group B, S3 dom ain

Group A, S5 dom ain

+19VB

PU1401

3579mA

+3VALW 10mA

U

3VALW

V8

PU701

PU1001

10mA

+

1013mA

+19VB

474mA

140000mA

12000mA

1013mA

6720mA

1

GPU Power Rail (R18M-G1-90)

+

VGA_CORE

VDDC

@140A

+

VDDCI

V

DDCI

@12A

+VDDCI

V

DD_08

@4A

+3VSDGPU

+

2000mA

+1.5VSDGPU

4

+1.5VSDGPU

T

T

T

itle

itle

itle

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

ustom

ustom

ustom

Date: Sheet

Date: Sheet

Date: Sheet

VDD_GPIO33

1.8VSDGPU

VDD_18

T

SVDD

VMEMIO

720mA

V

RAM x4pcs

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

ompal Electronics, Inc.

P

P

P

OWER MAP

OWER MAP

OWER MAP

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

@0.01A

@1A

@0.013A

@2A

o

o

o

f

4 99Wednesday, May 15, 2019

f

4 99Wednesday, May 15, 2019

f

1

4 99Wednesday, May 15, 2019

1

1

1

A

A

A

5

A

MD Picasso Platform Power Sequence

A

C-IN G3 --> S0

+3VLP

ACIN

EC_ON

D D

+5VALW

ON/OFFBTN#

3

V_EN

+

3VALW

41.49ms

41.49ms

2.32ms, Tr = 555us

9.608us

197.4ms

93.85ms

1.124ms, Tr = 1.075ms

4

S

0 --> S3 S3 --> S0

3

2

1

S0 --> S5

+3VLP

ACIN

EC_ON

+5VALW

ON/OFFBTN#

8.190s

5.228ms, Tf = 4.973ms

3V_EN

+

3VALW

8.190s

8.190s

9.166ms

1.525ms, Tf = 9.252ms

0.9_1.8VALW_PWREN

+1.8VALW

+0.9VALW

PBTN_OUT#

EC_RSMRST#

SLP_S5#

SLP_S3#

SYSON

+1.2V

+2.5V

SUSP#

+5VS

+3VS

+1.8VS

+0.6VS

KBRST#

0.9VS_PWR_EN#

+0.9VS

VR_ON

+APU_CORE

+APU_CORE_NB

VGATE

SYS_PWRGD_EC

APU_PWROK

LPC_RST#

APU_PCIE_RST#

APU_RST#

V

GA Sequence

P

E_GPIO1

+3VSDGPU

+1.8VSDGPU

0.9_1.8VALW_PWREN

+1.8VALW

+0.9VALW

PBTN_OUT#

EC_RSMRST#

SLP_S5#

SLP_S3#

SYSON

+1.2V

+2.5V

SUSP#

C C

+5VS

+3VS

+1.8VS

+0.6VS

KBRST#

0.9VS_PWR_EN#

+0.9VS

VR_ON

+APU_CORE

+APU_CORE_SOC

VGATE

SYS_PWRGD_EC

APU_PWROK

LPC_RST#

APU_PCIE_RST#

B B

APU_RST#

V

GA Sequence

PE_GPIO1

+3VSDGPU

+1.8VSDGPU

93.9ms

2.560ms, Tr = 1.418ms

820.9us, Tr = 358us

199.4ms

99.42ms

5.422ms

132.6ms

168us

168us

119ms

721.4us, Tr = 193.8us

1.695ms, Tr = 1.431ms

19.85ms

643.7us, Tr = 540.1us

683.4us, Tr = 525.9us

321us, Tr = 205.1us

16us, Tr = 17.18us

19.92ms

39.66ms

335.9us, Tr = 132.1us 331.1us, Tr = 127.2us2.3ms, Tf = 2.246ms 2.221ms, Tf = 2.165us

19.77ms

2.186ms, Tr = 295.7us

2.212ms, Tr = 316.7us

2.393ms

41.59ms

15.02ms

10.39ms

12.24ms

21.36ms

1.93s

1.153ms, Tr = 955.4us

1.306ms

4.826ms

4.956ms

4.956ms

56.14ms

4.415ms. Tf = 4.407ms

33.12ms, Tf = 32.78ms

12.87ms, Tf = 12.59ms

2.716ms, Tf = 2.480ms 837.7us, Tf = 772.7us

60.86ms

60.92ms

90.80ms

339.7us, Tf = 267.5us

338.9us, Tf = 284.6us

27.25ms

11.1ms

77us, Tf = 266.8us

13.44ms, Tf = 3.396ms

20.48ms

696.6us, Tr = 591.2us

716.1us, Tr = 555.7us

327.7us, Tr = 211.1us

15.42us, Tr = 15.38us

19.34ms

39.45ms

19.77ms

2.190ms, Tr = 299.8us

2.210ms, Tr = 313.4us

2.391ms

41.56ms

15.10ms

10.61ms

12.64ms

21.60ms

211.1ms

1.31ms

4.837ms

4.92ms

4.92ms

1.158ms, Tr = 956.5us

4.496ms, Tr = 1.374ms4.470ms, Tr = 1.359ms

51.70ms

51.69ms

58.19ms

58.25ms

24.92ms

1

.575s

10.96ms

75.49us, Tf = 2.634ms

13.39ms, Tf = 3.463ms

7.537ms, Tf = 9.313ms

2.353ms, Tf = 38.51us

5.143ms, Tf = 20.32ms

6.756ms, Tf = 6.739ms

28.36ms, Tf = 28.04ms

13.95ms, Tf = 13.67ms

87.99ms

335.2us, Tf = 247.5us

329.9us, Tf = 273.3us

ssued Date

ssued Date

ssued Date

10.97ms

1.665ms, Tf = 19.63ms

653.5ms, Tf = 4.784ms

10.97ms

1.758ms, Tf = 17.78ms

C

C

C

ompal Secret Data

ompal Secret Data

2

2

2

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

2

ompal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

VGA_ON_B

+VDDCI

+VGA_CORE

DGPU_PWRGOOD

+1.5VSDGPU

PE_GPIO0

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheetof

Date: Sheetof

Date: Sheetof

ompal Electronics, Inc.

itle

itle

itle

C

C

C

ustom

ustom

ustom

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

1

P

P

P

OWER SEQUENCE

OWER SEQUENCE

OWER SEQUENCE

5 99Wednesday, May 15, 2019

5 99Wednesday, May 15, 2019

5 99Wednesday, May 15, 2019

1

1

1

VGA_ON_B

+

VDDCI

+VGA_CORE

DGPU_PWRGOOD

+1.5VSDGPU

PE_GPIO0

P

LT_RST_VGA# PLT_RST_VGA#

A A

5

5.351ms

6.218ms, Tr = 84.15us

6.218ms, Tr = 85.54us

6.174ms

772.6us, Tr = 416.8us 830.8us, Tr = 480.8us

139.7ms

5.036ms

4

11.1ms

1.652ms, Tf = 21.21ms

894us, Tf = 5.296ms

11.1ms

1.746ms, Tf = 18.06ms

5.354ms

6.173ms, Tr = 84.5us

6.173ms, Tr = 86.28us

6.216ms

96.42ms

5.032ms

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

A

A

5

M

ain Func = CPU

4

3

2

1

UC1B

D D

P

EG_ARX_ GTX_P027

P

EG_ARX_ GTX_N027

P

EG_ARX_ GTX_P127

P

PEG

EG_ARX_ GTX_N127

P

EG_ARX_ GTX_P227

P

EG_ARX_ GTX_N227

P

EG_ARX_ GTX_P327

P

EG_ARX_ GTX_N327

P

EG_ARX_ GTX_P427

P

EG_ARX_ GTX_N427

P

EG_ARX_ GTX_P527

P

EG_ARX_ GTX_N527

P

EG_ARX_ GTX_P627

P

EG_ARX_ GTX_N627

P

EG_ARX_ GTX_P727

P

EG_ARX_ GTX_N727

EG_ARX_ GTX_P0

P

EG_ARX_ GTX_N0

P

EG_ARX_ GTX_P1

P

EG_ARX_ GTX_N1

P

EG_ARX_ GTX_P2

P

EG_ARX_ GTX_N2

P

EG_ARX_ GTX_P3

P

EG_ARX_ GTX_N3

P

EG_ARX_ GTX_P4

P

EG_ARX_ GTX_N4

P

EG_ARX_ GTX_P5

P

EG_ARX_ GTX_N5

P

EG_ARX_ GTX_P6

P

EG_ARX_ GTX_N6

P

EG_ARX_ GTX_P7

P

EG_ARX_ GTX_N7

P

P

8

P

_GFX_RXP0

P

9

P

_GFX_RXN0

N

6

P

_GFX_RXP1

N

7

P

_GFX_RXN1

M

8

P

_GFX_RXP2

M

9

P

_GFX_RXN2

L

6

P

_GFX_RXP3

L

7

P

_GFX_RXN3

K

11

P

_GFX_RXP4

J

11

P

_GFX_RXN4

H

6

P

_GFX_RXP5

H

7

P

_GFX_RXN5

G

6

P

_GFX_RXP6

F

7

P

_GFX_RXN6

G

8

P

_GFX_RXP7

F

8

P

_GFX_RXN7

PCIE

EG_ATX_ GRX_P0

P

1

N

_GFX_TXP0

P

_GFX_TXN0

P

_GFX_TXP1

P

_GFX_TXN1

P

_GFX_TXP2

P

_GFX_TXN2

P

_GFX_TXP3

P

_GFX_TXN3

P

_GFX_TXP4

P

_GFX_TXN4

P

_GFX_TXP5

P

_GFX_TXN5

P

_GFX_TXP6

P

_GFX_TXN6

P

_GFX_TXP7

P

_GFX_TXN7

P

3

N

2

M

4

M

2

L

4

L

1

L

3

L

2

K

4

K

2

J

4

J

1

H

3

H

2

H

4

H

EG_ATX_ GRX_N0

P

EG_ATX_ GRX_P1

P

EG_ATX_ GRX_N1

P

EG_ATX_ GRX_P2

P

EG_ATX_ GRX_N2

P

EG_ATX_ GRX_P3

P

EG_ATX_ GRX_N3

P

EG_ATX_ GRX_P4

P

EG_ATX_ GRX_N4

P

EG_ATX_ GRX_P5

P

EG_ATX_ GRX_N5

P

EG_ATX_ GRX_P6

P

EG_ATX_ GRX_N6

P

EG_ATX_ GRX_P7

P

EG_ATX_ GRX_N7

P

P

EG_ATX_ GRX_P0 27

P

EG_ATX_ GRX_N0 27

P

EG_ATX_ GRX_P1 27

P

EG_ATX_ GRX_N1 27

P

EG_ATX_ GRX_P2 27

P

EG_ATX_ GRX_N2 27

P

EG_ATX_ GRX_P3 27

P

EG_ATX_ GRX_N3 27

P

EG_ATX_ GRX_P4 27

P

EG_ATX_ GRX_N4 27

P

EG_ATX_ GRX_P5 27

P

EG_ATX_ GRX_N5 27

P

EG_ATX_ GRX_P6 27

P

EG_ATX_ GRX_N6 27

P

EG_ATX_ GRX_P7 27

P

EG_ATX_ GRX_N7 27

PEG

CIE_ARX_D TX_P0

P

C C

M.2 SSD1

LAN

WLAN

M.2 SSD2

B B

CIE_ARX_D TX_P068

P

CIE_ARX_D TX_N068

P

CIE_ARX_D TX_P168

P

CIE_ARX_D TX_N168

P

CIE_ARX_D TX_P268

P

CIE_ARX_D TX_N268

P

CIE_ARX_D TX_P368

P

CIE_ARX_D TX_N368

P

CIE_ARX_D TX_P451

P

CIE_ARX_D TX_N451

P

CIE_ARX_D TX_P552

P

CIE_ARX_D TX_N552

S

ATA_ARX _DTX_P067

S

ATA_ARX _DTX_N067

S

ATA_ARX _DTX_P169

S

ATA_ARX _DTX_N169

P

CIE_ARX_D TX_N0

P

CIE_ARX_D TX_P1

P

CIE_ARX_D TX_N1

P

CIE_ARX_D TX_P2

P

CIE_ARX_D TX_N2

P

CIE_ARX_D TX_P3

P

CIE_ARX_D TX_N3

P

CIE_ARX_D TX_P4

P

CIE_ARX_D TX_N4

P

CIE_ARX_D TX_P5

P

CIE_ARX_D TX_N5

P

ATA_ARX _DTX_P0

S

ATA_ARX _DTX_N0

S

ATA_ARX _DTX_P1

S

ATA_ARX _DTX_N1

S

N

10

P

_GPP_RXP0

N

9

P

_GPP_RXN0

L

10

P

_GPP_RXP1

L

9

P

_GPP_RXN1

L

12

P

_GPP_RXP2

M

11

P

_GPP_RXN2

P

12

P

_GPP_RXP3

P

11

P

_GPP_RXN3

V

6

P

_GPP_RXP4

V

7

P

_GPP_RXN4

T

8

P

_GPP_RXP5

T

9

P

_GPP_RXN5

R

6

P

_GPP_RXP6/SATA_RXP0

R

7

P

_GPP_RXN6/SATA_RXN0

R

9

P

_GPP_RXP7/SATA_RXP1

R

10

P

_GPP_RXN7/SATA_RXN1

@

FP5 REV 0.90
P

ART 2 OF 13

F

P5_BGA_ 1140P

_GPP_TXP0

P

_GPP_TXN0

P

_GPP_TXP1

P

_GPP_TXN1

P

_GPP_TXP2

P

P

_GPP_TXN2

P

_GPP_TXP3

P

_GPP_TXN3

P

_GPP_TXP4

P

_GPP_TXN4

P

_GPP_TXP5

P

_GPP_TXN5

P

_GPP_TXP6/SATA_TXP0

P

_GPP_TXN6/SATA_TXN0

P

_GPP_TXP7/SATA_TXP1

P

_GPP_TXN7/SATA_TXN1

2

N

3

P

4

P

2

P

3

R

R

1

T

4

T

2

W

2

W

4

W

3

V

2

V

1

V

3

U

2

U

4

CIE_ATX_D RX_P0

P

CIE_ATX_D RX_N0

P

CIE_ATX_D RX_P1

P

CIE_ATX_D RX_N1

P

CIE_ATX_D RX_P2

P

CIE_ATX_D RX_N2

P

CIE_ATX_D RX_P3

P

CIE_ATX_D RX_N3

P

CIE_ATX_D RX_P4

P

CIE_ATX_D RX_N4

P

CIE_ATX_D RX_P5

P

CIE_ATX_D RX_N5

P

ATA_ATX _DRX_P0

S

ATA_ATX _DRX_N0

S

ATA_ATX _DRX_P1

S

ATA_ATX _DRX_N1

S

1 2

C1204 0.22U_04 02_16V7K

C

1 2

C1203 0.22U_04 02_16V7K

C

1 2

C

C1206 0.22U_04 02_16V7K

C

C1205 0.22U_04 02_16V7K

C1212 0.22U_04 02_16V7K

C

C1211 0.22U_04 02_16V7K

C

C1214 0.22U_04 02_16V7K

C

C1213 0.22U_04 02_16V7K

C

2

1

2

1

2

1

2

1

2

1

2

1

C1 .1U_ 0402_16V7K

C

2

1

C2 .1U_ 0402_16V7K

C

2

1

C3 .1U_ 0402_16V7K

C

2

1

C4 .1U_ 0402_16V7K

C

P

CIE_ATX_C _DRX_P0 68

P

CIE_ATX_C _DRX_N0 68

P

CIE_ATX_C _DRX_P1 68

P

CIE_ATX_C _DRX_N1 68

P

CIE_ATX_C _DRX_P2 68

P

CIE_ATX_C _DRX_N2 68

P

CIE_ATX_C _DRX_P3 68

P

CIE_ATX_C _DRX_N3 68

P

CIE_ATX_C _DRX_P4 51

P

CIE_ATX_C _DRX_N4 51

P

CIE_ATX_C _DRX_P5 52

P

CIE_ATX_C _DRX_N5 52

S

ATA_ATX _DRX_P0 67

S

ATA_ATX _DRX_N0 67

S

ATA_ATX _DRX_P1 69

S

ATA_ATX _DRX_N1 69

M.2 SSD1

LAN

WLAN

HDDHDD

M.2 SSD2

APU PN Table

A

PU Platform

C1 R7APU@

U

IC RYZEN7 YM3700C4T4MFG 2.3G APU AB O!

S

A0000C7680

S

P

icasso

U

C1 R5APUQC@

S

IC RYZEN5 YM3500C4T4MFG 2.1G BGA AP U

S

A0000CCR20

U

C1 R7APUQC@

S

IC RYZEN7 YM3700C4T4MFG 2.3G BGA AP U

S

A0000C7640

U

C1 R5APU@

S

IC RYZEN5 YM3500C4T4MFG 2.1G APU AB O!

S

A0000CCR60

PCB Number

A A

ZZ

EVT@

Z
PCB 2QE L A-H901P REV0 MB 2

DA8001J M000

Z

ZZ

PVT@

PCB FH50 P LA-H901P LS-H9 01P/H502P

DAZ2QE0 0100

P

CB: DAZ2QE00100, DA8001JM010 REV: 1.0/1.0/1.0

ZZ

MP@

Z
PCB FH50 P LA-H901P LS-H9 01P/H502P

DAZ2QE0 0101

PCB: DAZ2QE00101, DA8001JM01A REV: 1.A/1.0/1.0

5

S

S

S

ecurity Classif ication

ecurity Classif ication

ecurity Classif ication

2

2

2

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

018/ 12/1 8 2019/12/18

3

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered D ate

eciphered D ate

eciphered D ate

Compal PNCustomer PNCustomer PNCustomer PNCustomer PN Compal PN

C

C

T

T

Title

itle

itle

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

C

C

C

ustom

ustom

ustom

Date: Sheet

Date: Sheet

2

Date: Sheet

C

F

F

F

P5_(1/7)_PEG/PCIE/SATA

P5_(1/7)_PEG/PCIE/SATA

P5_(1/7)_PEG/PCIE/SATA

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

ompal Electronics, Inc.

ompal Electronics, Inc.

ompal Electronics, Inc.

6 99Wednesd ay, May 15, 2019

6 99Wednesd ay, May 15, 2019

6 99Wednesd ay, May 15, 2019

1

1

1

1

A

A

A

o

o

o

f

f

f

5

M

ain Func = CPU

4

3

2

1

MEMORY B

FP5 REV 0.90

ART 9 OF 13

P

P5_BGA_1140P

F

UC1I

M

M

M

M

M

M

M

M

M

M

M

B_DATA10

M

B_DATA11

M

B_DATA12

M

B_DATA13

M

B_DATA14

M

B_DATA15

M

B_DATA16

M

B_DATA17

M

B_DATA18

M

B_DATA19

M

B_DATA20

M

B_DATA21

M

B_DATA22

M

B_DATA23

M

B_DATA24

M

B_DATA25

M

B_DATA26

M

B_DATA27

M

B_DATA28

M

B_DATA29

M

B_DATA30

M

B_DATA31

M

B_DATA32

M

B_DATA33

M

B_DATA34

M

B_DATA35

M

B_DATA36

M

B_DATA37

M

B_DATA38

M

B_DATA39

M

B_DATA40

M

B_DATA41

M

B_DATA42

M

B_DATA43

M

B_DATA44

M

B_DATA45

M

B_DATA46

M

B_DATA47

M

B_DATA48

M

B_DATA49

M

B_DATA50

M

B_DATA51

M

B_DATA52

M

B_DATA53

M

B_DATA54

M

B_DATA55

M

B_DATA56

M

B_DATA57

M

B_DATA58

M

B_DATA59

M

B_DATA60

M

B_DATA61

M

B_DATA62

M

B_DATA63

M

B_PAROUT

B_DATA0

B_DATA1

B_DATA2

B_DATA3

B_DATA4

B_DATA5

B_DATA6

B_DATA7

B_DATA8

B_DATA9

R

SVD_17

R

SVD_19

R

SVD_26

R

SVD_29

R

SVD_16

R

SVD_15

R

SVD_25

R

SVD_24

D

DR_B_DQ0

D

B

21

DR_B_DQ1

D

D

21

DR_B_DQ2

D

B

23

DR_B_DQ3

D

D

23

DR_B_DQ4

D

A

20

DR_B_DQ5

D

C

20

DR_B_DQ6

D

A

22

DR_B_DQ7

D

C

22

DR_B_DQ8

D

D

24

DR_B_DQ9

D

A

25

DR_B_DQ10

D

D

27

DR_B_DQ11

D

C

27

DR_B_DQ12

D

C

23

DR_B_DQ13

D

B

24

DR_B_DQ14

D

C

26

DR_B_DQ15

D

B

27

D

DR_B_DQ16

C

30

DR_B_DQ17

D

E

29

DR_B_DQ18

D

H

29

DR_B_DQ19

D

H

31

DR_B_DQ20

D

A

28

DR_B_DQ21

D

D

28

DR_B_DQ22

D

F

31

DR_B_DQ23

D

G

30

DR_B_DQ24

D

J

29

DR_B_DQ25

D

J

31

DR_B_DQ26

D

L

29

DR_B_DQ27

D

L

31

DR_B_DQ28

D

H

30

DR_B_DQ29

D

H

32

DR_B_DQ30

D

L

30

DR_B_DQ31

D

L

32

DR_B_DQ32

D

A

P29

DR_B_DQ33

D

A

P32

DR_B_DQ34

D

A

T29

DR_B_DQ35

D

A

U32

DR_B_DQ36

D

A

N30

DR_B_DQ37

D

A

P31

DR_B_DQ38

D

A

R30

DR_B_DQ39

D

A

T31

DR_B_DQ40

D

A

U29

DR_B_DQ41

D

A

V30

DR_B_DQ42

D

B

B30

DR_B_DQ43

D

B

A28

DR_B_DQ44

D

A

U30

DR_B_DQ45

D

A

U31

DR_B_DQ46

D

A

Y32

DR_B_DQ47

D

A

Y29

DR_B_DQ48

D

B

A27

DR_B_DQ49

D

B

C27

DR_B_DQ50

D

B

A24

DR_B_DQ51

D

B

C24

DR_B_DQ52

D

B

D28

DR_B_DQ53

D

B

B27

DR_B_DQ54

D

B

B25

DR_B_DQ55

D

B

D25

DR_B_DQ56

D

B

C23

DR_B_DQ57

D

B

B22

DR_B_DQ58

D

B

C21

DR_B_DQ59

D

B

D20

DR_B_DQ60

D

B

B23

DR_B_DQ61

D

B

A23

DR_B_DQ62

D

B

B21

DR_B_DQ63

D

B

A21

M

31

N

30

P

31

R

32

M

30

M

29

P

30

P

29

DR_B_PAR

D

A

G31

DR_B_DQ[63..0] 24

D

DR_B_PAR 24

UC1A

D

DR_A_MA[13..0]23

D D

D

DR_A_MA14_W E#23

D

DR_A_MA15_CAS#23

D

DR_A_MA16_RAS#23

D

DR_A_BA023

D

DR_A_BA123

D

DR_A_BG023

D

DR_A_BG123

D

DR_A_ACT#23

D

DR_A_DM[7..0]23

D

DR_A_DQS023

D

DR_A_DQS0#23

D

DR_A_DQS123

D

DR_A_DQS1#23

D

DR_A_DQS223

D

C C

B B

DR_A_DQS2#23

D

DR_A_DQS323

D

DR_A_DQS3#23

D

DR_A_DQS423

D

DR_A_DQS4#23

D

DR_A_DQS523

D

DR_A_DQS5#23

D

DR_A_DQS623

D

DR_A_DQS6#23

D

DR_A_DQS723

D

DR_A_DQS7#23

D

DR_A_CLK023

D

DR_A_CLK0#23

D

DR_A_CLK123

D

DR_A_CLK1#23

D

DR_A_CS0#23

D

DR_A_CS1#23

D

DR_A_CKE023

D

DR_A_CKE123

D

DR_A_ODT023

D

DR_A_ODT123

D

DR_A_ALERT#23

D

DR_A_EVENT#23

D

DR_A_RST#2 3

D

DR_A_MA0

D

DR_A_MA1

D

DR_A_MA2

D

DR_A_MA3

D

DR_A_MA4

D

DR_A_MA5

D

DR_A_MA6

D

DR_A_MA7

D

DR_A_MA8

D

DR_A_MA9

D

DR_A_MA10

D

DR_A_MA11

D

DR_A_MA12

D

DR_A_MA13

D

DR_A_MA14_W E#

D

DR_A_MA15_CAS#

D

DR_A_MA16_RAS#

D

DR_A_BA0

D

DR_A_BA1

DR_A_BG0

D

DR_A_BG1

D

DR_A_ACT#

D

D

DR_A_DM0

D

DR_A_DM1

D

DR_A_DM2

D

DR_A_DM3

D

DR_A_DM4

D

DR_A_DM5

D

DR_A_DM6

D

DR_A_DM7

D

DR_A_DQS0

D

DR_A_DQS0#

D

DR_A_DQS1

D

DR_A_DQS1#

D

DR_A_DQS2

D

DR_A_DQS2#

D

DR_A_DQS3

D

DR_A_DQS3#

D

DR_A_DQS4

D

DR_A_DQS4#

D

DR_A_DQS5

D

DR_A_DQS5#

D

DR_A_DQS6

D

DR_A_DQS6#

D

DR_A_DQS7

D

DR_A_DQS7#

D

DR_A_CLK0

D

DR_A_CLK0#

D

DR_A_CLK1

D

DR_A_CLK1#

D

DR_A_CS0#

D

DR_A_CS1#

D

DR_A_CKE0

D

DR_A_CKE1

D

DR_A_ODT0

D

DR_A_ODT1

D

DR_A_ALERT#

D

DR_A_EVENT#

D

DR_A_RST#

F25

A

A_ADD0

M

E23

A

A_ADD1

M

D27

A

A_ADD2

M

E21

A

A_ADD3

M

C24

A

A_ADD4

M

C26

A

A_ADD5

M

D21

A

A_ADD6

M

C27

A

A_ADD7

M

D22

A

A_ADD8

M

C21

A

A_ADD9

M

F22

A

A_ADD10

M

A24

A

A_ADD11

M

C23

A

A_ADD12

M

J25

A

A_ADD13_BANK2

M

G27

A

A_WE_L_ADD14

M

G23

A

A_CAS_L_ADD15

M

G26

A

A_RAS_L_ADD16

M

F21

A

A_BANK0

M

F27

A

A_BANK1

M

A21

A

A_BG0

M

A27

A

A_BG1

M

A22

A

A_ACT_L

M

21

F

A_DM0

M

27

G

A_DM1

M

24

N

A_DM2

M

23

N

A_DM3

M

L24

A

A_DM4

M

N27

A

A_DM5

M

W25

A

A_DM6

M

T21

A

A_DM7

M

T

27

R

SVD_36

F

22

M

A_DQS_H0

G

22

M

A_DQS_L0

H

27

M

A_DQS_H1

H

26

M

A_DQS_L1

N

27

M

A_DQS_H2

N

26

M

A_DQS_L2

R

21

M

A_DQS_H3

P

21

M

A_DQS_L3

A

M26

M

A_DQS_H4

A

M27

M

A_DQS_L4

A

N24

M

A_DQS_H5

A

N25

M

A_DQS_L5

A

U23

M

A_DQS_H6

A

T23

M

A_DQS_L6

A

V20

M

A_DQS_H7

A

W20

M

A_DQS_L7

V

24

R

SVD_41

V

23

R

SVD_40

A

D25

M

A_CLK_H0

A

D24

M

A_CLK_L0

A

E26

M

A_CLK_H1

A

E27

M

A_CLK_L1

A

G21

M

A_CS_L0

A

J27

M

A_CS_L1

Y

23

M

A_CKE0

Y

26

M

A_CKE1

A

G24

M

A_ODT0

A

J22

M

A_ODT1

A

A25

M

A_ALERT_L

A

E24

M

A_EVENT_L

Y

24

M

A_RESET_L

@

MEMORY A

FP5 REV 0.90
P

ART 1 OF 13

F

P5_BGA_1140P

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

A_PAROUT

M

A_DATA0

A_DATA1

A_DATA2

A_DATA3

A_DATA4

A_DATA5

A_DATA6

A_DATA7

A_DATA8

A_DATA9

A_DATA10

A_DATA11

A_DATA12

A_DATA13

A_DATA14

A_DATA15

A_DATA16

A_DATA17

A_DATA18

A_DATA19

A_DATA20

A_DATA21

A_DATA22

A_DATA23

A_DATA24

A_DATA25

A_DATA26

A_DATA27

A_DATA28

A_DATA29

A_DATA30

A_DATA31

A_DATA32

A_DATA33

A_DATA34

A_DATA35

A_DATA36

A_DATA37

A_DATA38

A_DATA39

A_DATA40

A_DATA41

A_DATA42

A_DATA43

A_DATA44

A_DATA45

A_DATA46

A_DATA47

A_DATA48

A_DATA49

A_DATA50

A_DATA51

A_DATA52

A_DATA53

A_DATA54

A_DATA55

A_DATA56

A_DATA57

A_DATA58

A_DATA59

A_DATA60

A_DATA61

A_DATA62

A_DATA63

SVD_34

R

SVD_35

R

SVD_51

R

SVD_52

R

SVD_27

R

SVD_28

R

SVD_43

R

SVD_42

R

D

D

DR_A_DQ0

21

J

DR_A_DQ1

D

21

H

DR_A_DQ2

D

23

F

D

DR_A_DQ3

23

H

D

DR_A_DQ4

20

G

DR_A_DQ5

D

20

F

DR_A_DQ6

D

22

J

DR_A_DQ7

D

23

J

DR_A_DQ8

D

25

G

DR_A_DQ9

D

26

F

DR_A_DQ10

D

24

L

DR_A_DQ11

D

26

L

DR_A_DQ12

D

23

L

D

DR_A_DQ13

25

F

DR_A_DQ14

D

25

K

DR_A_DQ15

D

27

K

DR_A_DQ16

D

25

M

DR_A_DQ17

D

27

M

DR_A_DQ18

D

27

P

D

DR_A_DQ19

24

R

DR_A_DQ20

D

27

L

DR_A_DQ21

D

24

M

DR_A_DQ22

D

24

P

DR_A_DQ23

D

25

P

DR_A_DQ24

D

22

M

DR_A_DQ25

D

21

N

DR_A_DQ26

D

22

T

DR_A_DQ27

D

21

V

D

DR_A_DQ28

21

L

D

DR_A_DQ29

20

M

DR_A_DQ30

D

23

R

DR_A_DQ31

D

21

T

DR_A_DQ32

D

L27

A

DR_A_DQ33

D

L25

A

D

DR_A_DQ34

P26

A

DR_A_DQ35

D

R27

A

D

DR_A_DQ36

K26

A

DR_A_DQ37

D

K24

A

DR_A_DQ38

D

M24

A

D

DR_A_DQ39

P27

A

D

DR_A_DQ40

M23

A

DR_A_DQ41

D

M21

A

DR_A_DQ42

D

R25

A

D

DR_A_DQ43

U27

A

DR_A_DQ44

D

L22

A

DR_A_DQ45

D

L21

A

D

DR_A_DQ46

P24

A

D

DR_A_DQ47

P23

A

DR_A_DQ48

D

W26

A

DR_A_DQ49

D

V25

A

DR_A_DQ50

D

V22

A

DR_A_DQ51

D

W22

A

DR_A_DQ52

D

U26

A

DR_A_DQ53

D

V27

A

DR_A_DQ54

D

W23

A

DR_A_DQ55

D

T22

A

DR_A_DQ56

D

W21

A

DR_A_DQ57

D

U21

A

DR_A_DQ58

D

P21

A

D

DR_A_DQ59

N20

A

D

DR_A_DQ60

R22

A

D

DR_A_DQ61

N22

A

DR_A_DQ62

D

T20

A

DR_A_DQ63

D

R20

A

24

T

25

T

25

W

27

W

26

R

27

R

27

V

26

V

DR_A_PAR

D

F24

A

DR_A_DQ[63..0] 23

D

DR_A_PAR 23

D

DR_B_MA[13..0]24

D

DR_B_MA14_W E#24

D

DR_B_MA15_C AS#24

D

DR_B_MA16_R AS#24

D

DR_B_BA024

D

DR_B_BA124

D

DR_B_BG024

D

DR_B_BG124

D

DR_B_ACT#2 4

D

DR_B_DM[7..0]24

D

DR_B_DQS024

D

DR_B_DQS0#24

D

DR_B_DQS124

D

DR_B_DQS1#24

D

DR_B_DQS224

D

DR_B_DQS2#24

D

DR_B_DQS324

D

DR_B_DQS3#24

D

DR_B_DQS424

D

DR_B_DQS4#24

D

DR_B_DQS524

D

DR_B_DQS5#24

D

DR_B_DQS624

D

DR_B_DQS6#24

D

DR_B_DQS724

D

DR_B_DQS7#24

D

DR_B_CLK024

D

DR_B_CLK0#24

D

DR_B_CLK124

D

DR_B_CLK1#24

D

DR_B_CS0#24

D

DR_B_CS1#24

D

DR_B_CKE024

D

DR_B_CKE124

D

DR_B_ODT024

D

DR_B_ODT124

D

DR_B_ALERT#24

D

DR_B_EVENT#24

D

DR_B_RST#2 4

DR_B_MA0

D

DR_B_MA1

D

DR_B_MA2

D

DR_B_MA3

D

DR_B_MA4

D

DR_B_MA5

D

DR_B_MA6

D

DR_B_MA7

D

DR_B_MA8

D

DR_B_MA9

D

DR_B_MA10

D

DR_B_MA11

D

DR_B_MA12

D

DR_B_MA13

D

D

DR_B_MA14_W E#

D

DR_B_MA15_C AS#

D

DR_B_MA16_R AS#

D

DR_B_BA0

D

DR_B_BA1

DR_B_BG0

D

DR_B_BG1

D

DR_B_ACT#

D

DR_B_DM0

D

DR_B_DM1

D

DR_B_DM2

D

DR_B_DM3

D

DR_B_DM4

D

DR_B_DM5

D

DR_B_DM6

D

DR_B_DM7

D

D

DR_B_DQS0

D

DR_B_DQS0#

D

DR_B_DQS1

D

DR_B_DQS1#

D

DR_B_DQS2

D

DR_B_DQS2#

D

DR_B_DQS3

D

DR_B_DQS3#

D

DR_B_DQS4

D

DR_B_DQS4#

D

DR_B_DQS5

D

DR_B_DQS5#

D

DR_B_DQS6

D

DR_B_DQS6#

D

DR_B_DQS7

D

DR_B_DQS7#

D

DR_B_CLK0

D

DR_B_CLK0#

D

DR_B_CLK1

D

DR_B_CLK1#

D

DR_B_CS0#

D

DR_B_CS1#

D

DR_B_CKE0

D

DR_B_CKE1

DR_B_ODT0

D

DR_B_ODT1

D

DR_B_ALERT#

D

DR_B_EVENT#

D

DR_B_RST#

D

A

G30

M

B_ADD0

A

C32

M

B_ADD1

A

C30

M

B_ADD2

A

B29

M

B_ADD3

A

B31

M

B_ADD4

A

A30

M

B_ADD5

A

A29

M

B_ADD6

Y

30

M

B_ADD7

A

A31

M

B_ADD8

W

29

M

B_ADD9

A

H29

M

B_ADD10

Y

32

M

B_ADD11

W

31

M

B_ADD12

A

L30

M

B_ADD13_BANK2

A

K30

M

B_WE_L_ADD14

A

K32

M

B_CAS_L_ADD15

A

J30

M

B_RAS_L_ADD16

A

H31

M

B_BANK0

A

G32

M

B_BANK1

V

31

M

B_BG0

V

29

M

B_BG1

V

30

M

B_ACT_L

C

21

M

B_DM0

C

25

M

B_DM1

E

32

M

B_DM2

K

30

M

B_DM3

A

P30

M

B_DM4

A

W31

M

B_DM5

B

B26

M

B_DM6

B

D22

M

B_DM7

N

32

R

SVD_21

D

22

M

B_DQS_H0

B

22

M

B_DQS_L0

D

25

M

B_DQS_H1

B

25

M

B_DQS_L1

F

29

B_DQS_H2

M

F

30

B_DQS_L2

M

K

31

M

B_DQS_H3

29

K

B_DQS_L3

M

R29

A

B_DQS_H4

M

R31

A

B_DQS_L4

M

W30

A

B_DQS_H5

M

W29

A

B_DQS_L5

M

C25

B

B_DQS_H6

M

A25

B

B_DQS_L6

M

C22

B

B_DQS_H7

M

A22

B

B_DQS_L7

M

31

N

SVD_20

R

29

N

SVD_18

R

C31

A

B_CLK_H0

M

D30

A

B_CLK_L0

M

D29

A

B_CLK_H1

M

D31

A

B_CLK_L1

M

E30

A

B_CLK_H2

M

E32

A

B_CLK_L2

M

F29

A

B_CLK_H3

M

F31

A

B_CLK_L3

M

J31

A

B0_CS_L0

M

M31

A

B0_CS_L1

M

J29

A

B1_CS_L0

M

M29

A

B1_CS_L1

M

29

U

B0_CKE0

M

30

T

B0_CKE1

M

32

V

B1_CKE0

M

31

U

B1_CKE1

M

L31

A

B0_ODT0

M

M32

A

B0_ODT1

M

L29

A

B1_ODT0

M

M30

A

B1_ODT1

M

30

W

B_ALERT_L

M

G29

A

B_EVENT_L

M

31

T

B_RESET_L

M

@

E

VENT# pull high

+

1.2V

D

1 2

C1 1K_0402_5%

R

+

1.2V

1 2

C2 1K_0402_5%

A A

5

R

DR_B_EVENT#

DR_A_EVENT#

D

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

2

2

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered Date

eciphered Date

eciphered Date

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

ustom

ustom

ustom

Date: Sheet

Date: Sheet

2

Date: Sheet

ompal Electronics, Inc.

F

F

F

P5_(2/7)_DDR4

P5_(2/7)_DDR4

P5_(2/7)_DDR4

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

1

7 99Wednesday, May 15, 201 9

1

1

1

A

A

A

o

o

o

f

7 99Wednesday, May 15, 201 9

f

7 99Wednesday, May 15, 201 9

f

A

M

ain Func = CPU

EC/THERM

+

3VS

C105 1K_0402_ 5%

R

C106 1K_0402_ 5%

R

C107 1K_0402_ 5%

R

C108 1K_0402_ 5%

R

1 1

E

C_SMB_CK228,58,66

E

C_SMB_DA228,58,66

2 2

+

3VS

R

C664 1K_0402_5%

1

@EMC@

C1202

C
.1U_0402_1 6V7K

2

1
1 2
1 2
1 2

1

2

2

1

EMC@

C5

C
33P_0402_5 0V8J

2

C_SMB_CK2

E

C_SMB_DA2

E

A

PU_SID

A

PU_ALERT#

A

PU_SIC

A

PU_PROCHOT #

1 2

C616 0_0402_ 5%

R

1 2

R

C617 0_0402_ 5%

T

HERMTRIP#

1

EMC@

C

C6

33P_0402_5 0V8J

2

A

PU_PROCHOT #

A

PU_RST#

A

PU_PWROK

PU_SIC

A

PU_SID

A

Close to APU

SVID

+

1.8VS

A

1
1 2
1

2

2

C109 1K_0402_ 5%@

3 3

R

C110 1K_0402_ 5%@

R

C111 1K_0402_ 5%@

R

PU_SVT_R

A

PU_SVC

A

PU_SVD

A

B

A

A

PU_DP0_P040

A

PU_DP0_N040

A

PU_DP0_P140

A

H

DMI

EDP

+

1.8VS

+

1.8VS

A

PU_PWROK88

A

PU_SVC88

A

PU_SVD88

PU_SVT_R88

PU_DP0_N140

A

PU_DP0_P240

A

PU_DP0_N240

A

PU_DP0_P340

A

PU_DP0_N340

E

DP_TXP03 8

E

DP_TXN038

E

DP_TXP13 8

E

DP_TXN138

E

DP_TXP23 8

E

DP_TXN238

E

DP_TXP33 8

E

DP_TXN338

1 2

C80 300_0402_5%

R
R

2

1

C81 300_0402_5%

T

HERMTRIP#58

A

PU_PROCHOT #58,84,88

1 2

C669 0_0402_5%

R

1 2

C670 0_0402_5%

R

PU_DP0_P0

A

PU_DP0_N0

A

PU_DP0_P1

A

PU_DP0_N1

A

PU_DP0_P2

A

PU_DP0_N2

A

PU_DP0_P3

A

PU_DP0_N3

E

DP_TXP0

E

DP_TXN0

E

DP_TXP1

E

DP_TXN1

E

DP_TXP2

E

DP_TXN2

E

DP_TXP3

E

DP_TXN3

A

PU_TDI

A

PU_TDO

A

PU_TCK

A

PU_TMS

A

PU_TRST#

A

PU_DBREQ#

A

PU_RST#

A

PU_PWROK

A

PU_SIC

A

PU_SID

A

PU_ALERT#

T

HERMTRIP#

A

PU_PROCHOT #

A

PU_SVC_R

A

PU_SVD_R

A

PU_SVT_R

C

8

D

P0_TXP0

A

8

D

P0_TXN0

D

8

D

P0_TXP1

B

8

D

P0_TXN1

B

6

D

P0_TXP2

C

7

D

P0_TXN2

C

6

D

P0_TXP3

D

6

D

P0_TXN3

E

6

D

P1_TXP0

D

5

D

P1_TXN0

E

1

D

P1_TXP1

1

C

D

P1_TXN1

3

F

P1_TXP2

D

E

4

P1_TXN2

D

4

F

P1_TXP3

D

2

F

P1_TXN3

D

U2

A

DI

T

U4

A

DO

T

U1

A

CK

T

U3

A

MS

T

V3

A

RST_L

T

W3

A

BREQ_L

D

W4

A

ESET_L

R

W2

A

WROK

P

14

H

IC

S

14

J

ID

S

15

J

LERT_L

A

P16

A

HERMTRIP_L

T

19

L

ROCHOT_L

P

16

F

VC0

S

IO18

16

H

VD0

S

16

J

VT0

S

@

UC1C

DISPLAY/SVI2/JTAG/TEST

D

P3:
DP2:
DP1: eDP
DP0: HDMI

IO18S5

IO18

IO33

FP5 REV 0.90

ART 3 OF 13

P

P5_BGA_1140P

F

C

IO18

D

D

P_STEREOSYNC

V

V

DDCR_SOC_SENSE

V

DDCR_SENSE

V

SS_SENSE_A

V

SS_SENSE_B

D

P_BLON

D

P_DIGON

P_VARY_BL

D

P0_AUXP

D

P0_AUXN

D

P0_HPD

D

P1_AUXP

D

P1_AUXN

D

P1_HPD

D

P2_AUXP

D

P2_AUXN

D

P2_HPD

D

P3_AUXP

D

P3_AUXN

D

P3_HPD

R

SVD_4

R

SVD_3

R

SVD_2

T

T

T

T

EST14

T

EST15

T

EST16

T

EST17

T

EST31

T

EST41

T

EST470

T

EST471

S

MU_ZVDD

C

ORETYPE

DDP_SENSE

EST4

EST5

EST6

E

NBKL_R

G

15

E

NVDD_R

F

15

I

NVTPWM_R

L

14

A

PU_DP0_CT RL_CLK

D

9

A

PU_DP0_CT RL_DATA

B

9

A

PU_DP0_HPD

C

10

E

DP_AUXP

G

11

E

DP_AUXN

F

11

E

DP_HPD

G

13

J

12

H

12

K

13

J

10

H

10

K

8

D

P_STEREOSYNC

K

15

F

14

F

12

F

10

A

P14

A

N14

F

13

G

18

H

19

F

18

F

19

W

24

A

R11

A

J21

A

K21

S

V

4

A

W11

C

A

PU_VDDP_SEN_ H

A

N11

A

PU_CORESOC_ SEN_H

J

19

A

PU_CORE_SEN _H

K

18

A

PU_VSS_SEN_L

J

18

A

PU_VDDP_SEN_ L

A

M11

A

PU_TEST4

A

PU_TEST5

A

PU_TEST14

A

PU_TEST15

A

PU_TEST16

A

PU_TEST17

A

PU_TEST31

A

PU_TEST41

A

PU_TEST47 0

A

PU_TEST47 1

MU_ZVDDP

ORETYPE

R

R

A

PU_DP0_CT RL_CLK 40

A

PU_DP0_CT RL_DATA 40

A

PU_DP0_HPD 40

E

DP_AUXP 38

E

DP_AUXN 38

E

DP_HPD 38

TP@

T

4949

TP@

4948

T

TP@

4942

T

TP@

T

4941

TP@

4940

T

TP@

4939

T

1 2

C1682 196_0402_1 %

2

1

C1681 1K_0402_5%@

A

PU_VDDP_SEN_ H 87

A

PU_CORESOC_ SEN_H 88

A

PU_CORE_SEN _H 88

A

PU_VSS_SEN_L 88

A

PU_VDDP_SEN_ L 87

D

HDMI

EDP

+

0.9VS

+

3VALW

Leakage prevent from power side

D

ISP

E

NBKL_R

E

NVDD_R

E

NVDD_R

I

NVTPWM_R

E

NBKL

E

NVDD

I

NVTPWM

E

NBKL_R

E

NVDD_R

I

NVTPWM_R

+

1.8VALW

5

C66

U

1

P

C

N

4

Y

2

A

G

NL17SZ07DFT 2G_SC70-5

3

A00004BV00

S

+

1.8VALW

5

U

C64

1

P

N

C

4

Y

2

A

G

NL17SZ07DFT 2G_SC70-5

3

S

@

A00004BV00

1 2

C690 0_0402_5%RS@

R

+

1.8VALW

5

C65

U

1

P

C

N

4

Y

2

A

G

NL17SZ07DFT 2G_SC70-5

3

A00004BV00

S

1

R

C3 4.7K_0402_5 %

1 2

R

C4 4.7K_0402_5 %@

1 2

C5 4.7K_0402_5 %

R

1 2

C6130 100K_0402_5 %

R

1 2

R

C6131 100K_0402_5 %

1 2

C6132 100K_0402_5 %@

R

E

E

NBKL

I

NVTPWM

E

NVDD

E

NBKL 58

E

NVDD 38

E

NVDD

I

NVTPWM 3 8

+

3VS

2

H

DT+

+

+

1.8VALW

J

HDT1

CONN@

PU_TCK_R

A

1

3

5

PU_TRST#

A

H2

C

0.01U_0402 _16V7K

4 4

1 2

H21 33_0402_5%

R

H38 10K_0402_5%

R

2

2

H39 10K_0402_5%

R

1

H40 10K_0402_5%

R

12

1

12

A

PU_TRST# _R

DT_P11

H

DT_P13

H

DT_P15

H

7

9

11

13

15

17

19

A

2

2

1

4

4

3

6

6

5

8

8

7

10

1

9

0

12

1

1

1

2

14

1

1

3

4

16

1

1

5

6

18

1

1

7

8

20

2

1

9

0

SAMTE_ASP-13644 6-07-B

PU_TMS_R

A

PU_TDI_R

A

PU_TDO_R

A

PU_PWROK _R

A

A

PU_RST#_R

A

PU_DBREQ#_R

H27 0_0402_5%H DT@

R

H28 0_0402_5%H DT@

R

R

H29 0_0402_5%H DT@

H30 0_0402_5%H DT@

R

H31 0_0402_5%H DT@

R

H32 0_0402_5%H DT@

R

R

H33 33_0402_5%

B

1 2

1

1 2

1 2

1

1 2

1 2

2

2

Follow C5V08

PU_TCK

A

PU_TMS

A

PU_TDI

A

PU_TDO

A

PU_PWROK

A

PU_RST#

A

PU_DBREQ#

A

A

PU_TCK

A

PU_TMS

A

PU_TDI

A

PU_DBREQ#

A

PU_TRST#

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

1

H34 1K_0402_5%

R

1 2

H35 1K_0402_5%

R

1 2

H36 1K_0402_5%

R

1 2

H37 1K_0402_5%

R

1

H26 1K_0402_5%

R

1.8VALW

2

2

C

C

C

ompal Secret Data

ompal Secret Data

2

2

2

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

ompal Secret Data

D

D

D

eciphered Date

eciphered Date

eciphered Date

D

TESTPOINT

D

P_STEREOSYNC

A

PU_TEST14

A

PU_TEST15

A

PU_TEST16

A

PU_TEST17

T

T

T

itle

itle

itle

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

ustom

ustom

ustom

Date: Sheet

Date: Sheet

Date: Sheet

1 2

C155 1K_0402_5%

R

1 2

C154 1K_0402_5%@

R

R

C112 10K_0402 _5%@

R

C113 10K_0402 _5%@

R

C114 10K_0402 _5%@

C115 10K_0402 _5%@

R

12
12

2

1

12

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

ompal Electronics, Inc.

(

(

(

3/7)_DISP/MISC/HDT

3/7)_DISP/MISC/HDT

3/7)_DISP/MISC/HDT

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

E

+

1.8VS

+

1.8VS

1

1

1

A

A

A

o

o

o

f

8 99Wednesday, May 15, 201 9

f

8 99Wednesday, May 15, 201 9

f

8 99Wednesday, May 15, 201 9

C28

S

YS_PWRGD_EC

C8

C6160

A

A

C700 0_0402_5%RS@

R

R

C701 0_0402_5%@

R

C30 0_0402_5%RS@

1

2

PU_PCIE_WAKE#

+

1.8VALW

1 2

1 2

1 2

+

3VALW

N1

I

N2

I

@

Reserve for MBDG/CRB

C1210

C
10U_0402_6.3V6M

1 2

@

1

R

C54

22K_0402_1%

2

E

C_RSMRST#

1

C

C16

1U_0201_6.3V6M

2

C14

C

0.1U_0201_10V6K

1 2

@

5

P

A

PU_PCIE_RST#

4

O

G

C4

U

A00000OH00

S

3

MC74VHC1G08DFT2G_SC70-5

A

PU_PCIE_RST#_U

A

PU_PCIE_RST#

A

PU_PCIE_RST# 27,51,52,68

A

PU_PCIE_RST#_C

A

PU_PCIE1_RST#_C

M

ain Func = CPU

1 1

A

CPI

+

3VALW

1 2

C6133 10K_0402_5%@

R

CRB use S0-rail

+

2 2

3 3

3VALW

12

C6165

R
10K_0402_1%@

A

PU_PCIE_RST#_U

+

3VS

12

R
10K_0402_1%

2

C

0.22U_0402_16V7K

1

A

PU_PCIE_RST#_C

A

PU_PCIE1_RST#_C

A

PU_PCIE_RST#_U

R

10K_0402_5% @

1 2

B

1 2

C

C7 150P_0402_50V 8J

1 2

C100 150P_0402_50V8J@

C

1 2

R

C29 33_0402_5%

1 2

C704 33_0402_5%@

R

E

C_RSMRST#58

P

BTN_OUT#58

S

YS_PWRGD_EC58

S

LP_S3#58

S

LP_S5#58,84

H

DA_SDIN056

A

PU_PCIE_RST#_R

A

PU_PCIE1_RST#_R

E

C_RSMRST#

P

BTN_OUT#

S

YS_PWRGD_EC

S

YS_RST#

A

PU_PCIE_WAKE#

S

LP_S3#

S

LP_S5#

A

GPIO10

A

GPIO23

A

GPIO12

H

DA_BIT_CLK

H

DA_SDIN0

H

DA_SDIN1

H

DA_SDIN2

H

DA_RST#

H

DA_SYNC

H

DA_SDOUT

A

GPIO7

D5

B

CIE_RST0_L/EGPIO26

P

B6

B

CIE_RST1_L/EGPIO27

P

T16

A

SMRST_L

R

R15

A

WR_BTN_L/AGPIO0

P

V6

A

WR_GOOD

P

P10

A

YS_RESET_L/AGPIO1

S

V11

A

AKE_L/AGPIO2

W

V13

A

LP_S3_L

S

T14

A

LP_S5_L

S

R8

A

0A3_GPIO/AGPIO10

S

T10

A

C_PRES/AGPIO23

A

A

N6

L

LB_L/AGPIO12

A

W8

E

GPIO42

A

R2

A

Z_BITCLK/TDM_BCLK_MIC

A

P7

A

Z_SDIN0/CODEC_GPI

A

P1

A

Z_SDIN1/SW_DATA1B/TDM_BCLK_PLAYBACK

A

P4

A

Z_SDIN2/SW_DATA2/TDM_DATA_PLAYBACK

A

P3

A

Z_RST_L/SW_DATA1A/SW_DATA3/TDM_DATA_MIC

A

R4

A

Z_SYNC/TDM_FRM_MIC

A

R3

A

Z_SDOUT/TDM_FRM_PLAYBACK

A

T2

S

W_MCLK/TDM_BCLK_BT

A

T4

S

W_DATA0/TDM_DOUT_BT

A

R6

A

GPIO7/FCH_ACP_I2S_SDIN_BT

A

P6

A

GPIO8/FCH_ACP_I2S_LRCLK_BT

@

SW PU/PD

SW PU/PD

C

UC1D

ACPI/AUDIO/I2C/GPIO/MISC

SW PU/PD
SW PU/PD

SW PU/PD
SW PU/PD

SW PU/PD
SW PU/PD

SW PU/PD

FP5 REV 0.90
P

ART 4 OF 13

F

P5_BGA_1140P

1.8V_S5

1.8V_S5

SW PU/PD

2C0_SCL/SFI0_I2C_SCL/EGPIO151

I

2C0_SDA/SFI0_I2C_SDA/EGPIO152

I

2C1_SCL/SFI1_I2C_SCL/EGPIO149

I

2C1_SDA/SFI1_I2C_SDA/EGPIO150

I

3.3V

3.3V_S5

3.3VALW input

3.3VS input

3.3VS input

3.3VS Output

3.3VS input

3.3VS input

3.3VS input

3.3VS input

G

A

GPIO41/SFI_S5_EGPIO41

E

A

GPIO39/SFI_S5_AGPIO39

A

A
A

A
A

B

2C2_SCL/EGPIO113/SCL0

I

B

2C2_SDA/EGPIO114/SDA0

I

A

2C3_SCL/AGPIO19/SCL1

I

A

2C3_SDA/AGPIO20/SDA1

I

L

SA_I2C_SCL

P

M

SA_I2C_SDA

P

A

GPIO3

A

A

GPIO4/SATAE_IFDET

A

A

GPIO5/DEVSLP0

A

A

GPIO6/DEVSLP1

A

A

ATA_ACT_L/AGPIO130

S

A

GPIO9

A

A

GPIO40

A

A

GPIO69

A

A

GPIO86

A

A

NTRUDER_ALERT

I

A

PKR/AGPIO91

S

A

LINK/AGPIO11

B

A

ENINT1_L/AGPIO89

G

B

ENINT2_L/AGPIO90

G

A

ANIN0/AGPIO84

F

A

ANOUT0/AGPIO85

F

PIO Table

D

I

2C_0_SCL
I

2C_0_SDA

I

W12
U12

I

2C_0_SCL

R13

I

2C_0_SDA

T13

I

2C_1_SCL

N8

I

2C_1_SDA

N9

S

MB_0_SCL

C20

S

MB_0_SDA

A20

I

2C_3_SCL

M9

I

2C_3_SDA

M10

16

16

T15

A

GPIO3

W10

A

GPIO4

P9

A

GPIO5

U10

D

EVSLP1

P

ANEL_OD#

V15

U7

A

GPIO9

U6

A

GPIO40

W13
W15

U14

A

PU_SPKR

U16
V8

A

GPIO11

W16

T

P_I2C_INT#_APU

D15

R18
T18

S

MB_0_SCL 23,24

S

MB_0_SDA 23,24

I

2C_3_SCL 63

I

2C_3_SDA 63

D

EVSLP1 68

P

ANEL_OD# 38

A

GPIO40 68

A

PU_SPKR 56

T

P_I2C_INT#_APU 63

DDR4

T

ouch Pad

2C_1_SCL
I

2C_1_SDA

S

MB_0_SCL

S

MB_0_SDA

I

2C_3_SCL
I

2C_3_SDA

D

EVSLP1

1 2

R

C6139 2.2K_0402_5%@

1

2

C6140 2.2K_0402_5%@

R

1 2

R

C6176 2.2K_0402_5%@

1 2

R

C6177 2.2K_0402_5%@

1 2

R

C6157 2.2K_0402_5%

1 2

C6156 2.2K_0402_5%

R

2

1

R

C6159 2.2K_0402_5%

1 2

C6158 2.2K_0402_5%

R

12

C663 10K_0402_5%@

R

A

GPIO40

RSV

H

L

12

@

R

C693

10K_0402_5%

10K_0402_5%

A

GPIO40

A

GPIO9

A

GPIO12

A

GPIO23

12

@

C692

R

10K_0402_5%

10K_0402_5%

A

GPIO9

DIS
Type1

RSVRSV

R

C6147

@

C6148

R

+

1.8VALW

+

3VS

+

3VALW

+

3VS

1

10K_0402_5%

2

1

10K_0402_5%

2

A

GPIO12

RSV

DMIC x2

@

R

C6135

R

C6136

E

12

10K_0402_5%

12

10K_0402_5%

AGPIO23

R

SV

RSV

+

@

R

C6175

@

R

C6174

3VALW

1

2

1

2

AGPIO10 AGPIO11

AGPIO3 AGPIO4AGPIO7AGPIO5

HDA

H

H

DA_SDIN1

H

DA_SDIN2

H

DA_SDIN0

DA_RST#

H

DA_BIT_CLK

H

DA_SYNC

H

DA_SDOUT

1 2

C116 33_0402_5%EMC@

H

DA_RST#_R56

H

DA_BIT_CLK_R56

H

DA_SYNC_R56

H

DA_SDOUT_R56

4 4

R

1 2

C117 33_0402_5%EMC@

R

1 2

R

C118 33_0402_5%EMC@

2

1

R

C119 33_0402_5%EMC@

2

1

R

C120 1K_04 02_5%

2

1

C121 1K_04 02_5%

R

2

1

C122 1K_04 02_5%

R

1 2

C123 1K_04 02_5%

R

2

1

R

C695 10K_0 402_5%@

1 2

C696 10K_0 402_5%@

R

R

1

C703 10K_0 402_5%@

A

2

Strap Pin

A

PU_SPI_CLK_R SYS_RST#

USE 48MHZ CRYSTAL

H

CLOCK
(Default)

U

SE 100MHZ PCIE

L

CLOCK AS
REFERENCE CLOCK

A

PU_SPI_CLK_R10

B

NORMAL RESET MODE
(Default)

SHORT RESET MODE

+

1.8VS+1.8VALW+3VALW

12

C622

R

10K_0402_5%

10K_0402_5% @

A

PU_SPI_CLK_R

S

YS_RST#

2K_0402_5% @

+

3VALW

12

12

@

@

C6137

C6145

R

R

10K_0402_5%

10K_0402_5%

A

12

R

10K_0402_5%

1

C951

C47

R

2

1

1

C929

R

R

C1703

2K_0402_5% @

2

2

C

GPIO5

A

GPIO7

12

12

@

@

C6138

C6146

R

R

10K_0402_5%

10K_0402_5%

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

2

2

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

C

C

C

D

R

10K_0402_5%

A

GPIO3

A

GPIO4

R

10K_0402_5%

ompal Secret Data

ompal Secret Data

ompal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

C6170

C6171

+

3VALW

1

1

@

@

R

C6168

10K_0402_5%

2

2

12

1

@

@

C6169

R

10K_0402_5%

2

@

C619

R

10K_0402_5%

A

GPIO10

A

GPIO11

@

R

C6134

10K_0402_5%

T

T

T

itle

itle

itle

F

F

F

P5_(4/7)_GPIO/HDA/STRAP

P5_(4/7)_GPIO/HDA/STRAP

P5_(4/7)_GPIO/HDA/STRAP

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

ustom

ustom

ustom

Date: Sheet

Date: Sheet

Date: Sheet

+

3VALW

12

12

@

C6172

R

10K_0402_5%

12

12

@

C6173

R

10K_0402_5%

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

ompal Electronics, Inc.

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

E

1

1

1

o

o

o

f

9 99Wednesday, May 15, 2019

f

9 99Wednesday, May 15, 2019

f

9 99Wednesday, May 15, 2019

A

A

A

Main Func = CPU

A

+

3VS

C

10K_0402_5%

C

10K_0402_5%

C

10K_0402_5%

C

10K_0402_5%

4

8M_X2

4

8M_X1

Y

C2

48MHZ_8PF_7V48000010

S

J10000JP00

1

797

C

3.9P_0402_50V8C

2

3

2K_X1

12

Y

C3

3

2K_X2

A

PU_USBC_SCL

A

PU_USBC_SDA

LKREQ_PCIE#0

LKREQ_PCIE#2
LKREQ_PEG#4
LKREQ_PCIE#3

1 1

R
R
R

C1696
C1697

2

1

2

1

2

1

R

C1695

2

1

C6149

48MHz CRYSTAL

1 2

R

C939

1M_0402_5%

J10000PW00

12

2

4.7K_0402_5%

2

4.7K_0402_5%

1

1

4

4

1

C682

C
10P_0402_50V8J

2

2

2

3

3

1

C

796

3.9P_0402_50V8C

2

2 2

3

2.768KHz CRYSTAL

S

32.768KHZ_9PF_X1A000141000200

R

C914

20M_0402_5%

1

C

C686

12P_0402_50V8J

2

U

SB Function

+

1.8VALW

1

C94

3 3

4 4

R

1

R

C95

M.2 SSD1

M.2 WLAN
LAN
DGPU

M

.2 SSD1

WLAN

LAN

DGPU

CAMERA

T

ype-A MB CHG

Type-A MB

T

ype-C MB

Type-A SUB

U

SB Hub

B

68CLKREQ_PCIE#0

52CLKREQ_PCIE#2
51CLKREQ_PCIE#3
28CLKREQ_PEG#4

68CLK_PCIE_P0
68CLK_PCIE_N0

52CLK_PCIE_P2
52CLK_PCIE_N2

51CLK_PCIE_P3
51CLK_PCIE_N3

27CLK_PEG_P4
27CLK_PEG_N4

38USB20_P0
38USB20_N0

71USB20_P1
71USB20_N1

72USB20_P2
72USB20_N2

43USB20_P3
43USB20_N3

73USB20_P4
73USB20_N4

52USB20_P5
52USB20_N5

115 TP@

T

C

LKREQ_PCIE#0

C

LKREQ_PCIE#2

C

LKREQ_PCIE#3

C

LKREQ_PEG#4

C

LK_PCIE_P0

C

LK_PCIE_N0

C

LK_PCIE_P2

C

LK_PCIE_N2

C

LK_PCIE_P3

C

LK_PCIE_N3

C

LK_PEG_P4

C

LK_PEG_N4

4

8M_X1

4

8M_X2

R

TCCLK

3

2K_X1

3

2K_X2

U

SB20_P0

U

SB20_N0

U

SB20_P1

U

SB20_N1

U

SB20_P2

U

SB20_N2

U

SB20_P3

U

SB20_N3

U

SB20_P4

U

SB20_N4

U

SB20_P5

U

SB20_N5

A

PU_USBC_SCL

A

PU_USBC_SDA

V18

A

LK_REQ0_L/SATA_IS0_L/SATA_ZP0_L/AGPIO92

C

N19

A

LK_REQ1_L/AGPIO115

C

P19

A

LK_REQ2_L/AGPIO116

C

T19

A

LK_REQ3_L/SATA_IS1_L/SATA_ZP1_L/EGPIO131

C

U19

A

LK_REQ4_L/OSCIN/EGPIO132

C

W18

A

LK_REQ5_L/EGPIO120

C

W19

A

LK_REQ6_L/EGPIO121

C

K1

A

PP_CLK0P

G

K3

A

PP_CLK0N

G

M2

A

PP_CLK1P

G

M4

A

PP_CLK1N

G

M1

A

PP_CLK2P

G

M3

A

PP_CLK2N

G

L2

A

PP_CLK3P

G

L4

A

PP_CLK3N

G

N2

A

PP_CLK4P

G

N4

A

PP_CLK4N

G

N3

A

PP_CLK5P

G

P2

A

PP_CLK5N

G

J2

A

PP_CLK6P

G

J4

A

PP_CLK6N

G

J3

A

8M_OSC

4

B3

B

48M_X1

X

A5

B

48M_X2

X

F8

A

SVD_76

R

F9

A

SVD_77

R

W14

A

TCCLK

R

Y1

A

32K_X1

X

Y4

A

32K_X2

X

@

E7

A

U

E6

A

U

G10

A

U

G9

A

U

F12

A

U

F11

A

U

E10

A

U

E9

A

U

J12

A

U

J11

A

U

D9

A

U

D8

A

U

M6

A

U

M7

A

U

K10

A

U

K9

A

U

L9

A

U

L8

A

U

W7

A

A

T12

A

A

@

M.2 WLAN/BT

GBE LAN

WWANM.2

M.2 WLAN

EVAL SLOT GFX

SB_0_DP0

SB_0_DM0

SB_0_DP1

SB_0_DM1

SB_0_DP2

SB_0_DM2

SB_0_DP3

SB_0_DM3

SB_1_DP0

SB_1_DM0

SB_1_DP1

SB_1_DM1

SBC_I2C_SCL

SBC_I2C_SDA

SB_OC0_L/AGPIO16

SB_OC1_L/AGPIO17

SB_OC2_L/AGPIO18

SB_OC3_L/AGPIO24

GPIO14/USB_OC4_L

GPIO13/USB_OC5_L

CLK/LPC/EMMC/SD/SPI/eSPI/UART

SW PU/PD

X4 DT SLOT PCIE

SSD PCIE M.2

Controller 0

Controller 1

SW PU/PD

C

FP5 REV 0.90

ART 5 OF 13

P

FP5 REV 0.90

P

UC1E

P5_BGA_1140P

F

UC1J

USB

Port 0

Port 3

ART 10 OF 13

P5_BGA_1140P

F

SW PU/PD

SW PU/PD

SW PU/PD

SW PU/PD

SW PU/PD

SW PU/PD

GPIO70/SD_CLK

E

PC_PD_L/SD_CMD/AGPIO21

L

AD0/SD_DATA0/EGPIO104

L

AD1/SD_DATA1/EGPIO105

L

AD2/SD_DATA2/EGPIO106

L

AD3/SD_DATA3/EGPIO107

L

PCCLK0/EGPIO74

L

PC_CLKRUN_L/AGPIO88

L

PCCLK1/EGPIO75

L

ERIRQ/AGPIO87

S

FRAME_L/EGPIO109

L

PC_RST_L/SD_WP_L/AGPIO32

L

GPIO68/SD_CD

A

PC_PME_L/SD_PWR_CTRL/AGPIO22

L

PI_ROM_REQ/EGPIO67

S

PI_ROM_GNT/AGPIO76

S

SPI_RESET_L/KBRST_L/AGPIO129

E

SPI_ALERT_L/LDRQ0_L/EGPIO108

E

PI_CLK/ESPI_CLK

S

PI_DI/ESPI_DATA

S

PI_WP_L/ESPI_DAT2

S

PI_HOLD_L/ESPI_DAT3

S

PI_CS1_L/EGPIO118

S

PI_CS2_L/ESPI_CS_L/AGPIO30

S

PI_CS3_L/AGPIO31

S

PI_TPM_CS_L/AGPIO29

S

ART0_RXD/EGPIO136

U

ART0_TXD/EGPIO138

U

ART0_RTS_L/UART2_RXD/EGPIO137

U

ART0_CTS_L/UART2_TXD/EGPIO135

U

ART0_INTR/AGPIO139

U

GPIO141/UART1_RXD

E

GPIO143/UART1_TXD

E

GPIO142/UART1_RTS_L/UART3_RXD

E

GPIO140/UART1_CTS_L/UART3_TXD

E

GPIO144/UART1_INTR

A

U

SBC0_A2/USB_0_TXP0/DP3_TXP2

U

SBC0_A3/USB_0_TXN0/DP3_TXN2

U

SBC0_B11/USB_0_RXP0/DP3_TXP3

U

SBC0_B10/USB_0_RXN0/DP3_TXN3

U

SBC0_B2/DP3_TXP1

U

SBC0_B3/DP3_TXN1

U

SBC0_A11/DP3_TXP0

U

SBC0_A10/DP3_TXN0

USB_0_TXP1

Port 1

USB_0_TXN1

USB_0_RXP1

USB_0_RXN1

USB_0_TXP2

Port 2

USB_0_TXN2

USB_0_RXP2

USB_0_RXN2

USBC1_A2/USB_0_TXP3/DP2_TXP2

SBC1_A3/USB_0_TXN3/DP2_TXN2

U

SBC1_B11/USB_0_RXP3/DP2_TXP3

U

SBC1_B10/USB_0_RXN3/DP2_TXN3

U

SBC1_B2/DP2_TXP1

U

SBC1_B3/DP2_TXN1

U

SBC1_A11/DP2_TXP0

U

SBC1_A10/DP2_TXN0

U

SB_1_TXP0

U

Port 4

SB_1_TXN0

U

SB_1_RXP0

U

SB_1_RXN0

U

D

R

C602

33_0402_5%

LPC_RST_A#

1 2

E

C_SCI#

D13

B

B14

B

L

PCPD#

L

PC_AD0

B12

B

L

PC_AD1

C11

B

L

PC_AD2

B15

B

L

PC_AD3

C15

B

L

PC_CLK0

A15

B

C13

B

L

PC_CLK1

B13

B

C12

B

S

ERIRQ

L

PC_FRAME#

A12

B

L

PC_RST_A#

D11

B

A11

B

E

C_SCI#

A13

B

C8

B

B8

B

B11

B

K

BRST#

E

SPI_ALERT_L

C6

B

A

PU_SPI_CLK

B7

B

A

PU_SPI_MISO

A9

B

A

PU_SPI_MOSI

B10

B

PI_DO

S

A

PU_SPI_WP#

A10

B

A

PU_SPI_HOLD#

C10

B

A

PU_SPI_CS#1

C9

B

A8

B

A6

B

A

PU_SPI_TPMCS#

D8

B

U

ART_0_ARXD_DTXD

A16

B

U

ART_0_ATXD_DRXD

B18

B

C17

B

A18

B

D18

B

P

E_GPIO1

C18

B

D

GPU_PWRGOOD

A17

B

C16

B

P

E_GPIO0

B19

B

B16

B

A

D2

A

D4

A

C2

A

C4

A

F4

A

F2

A

E3

A

E1

U

SB3_ATX_DRX_P1

AG3

U

SB3_ATX_DRX_N1

AG1

U

SB3_ARX_DTX_P1

AJ9

U

SB3_ARX_DTX_N1

AJ8

U

SB3_ATX_DRX_P2

AG4

U

SB3_ATX_DRX_N2

AG2

U

SB3_ARX_DTX_P2

G7

A

U

SB3_ARX_DTX_N2

AG6

U

SB3_ATX_DRX_P3

AA2

U

SB3_ATX_DRX_N3

A4

A

U

SB3_ARX_DTX_P3

1

Y

U

SB3_ARX_DTX_N3

3

Y

C1

A

C3

A

B2

A

B4

A

H4

A

H2

A

K7

A

K6

A

R

C101

R

C102

R

C103

R

C104

C449

R

103TP@

T

1

1
1
1

1

S

ERIRQ 58
L

E

C_SCI# 58

K

BRST# 58

1

R

C74

EMC@210_0402_5%

U

P

E_GPIO1 37

D

GPU_PWRGOOD 27,92,94

P

E_GPIO0 27

U
U

U
U

U
U

2

10_0402_5%

2

10_0402_5%

2

10_0402_5%

2

10_0402_5%

2

22_0402_5%

PC_FRAME# 58

ART_0_ARXD_DTXD 52
U

ART_0_ATXD_DRXD 52

U

SB3_ATX_DRX_P1 71

U

SB3_ATX_DRX_N1 71

SB3_ARX_DTX_P1 71
SB3_ARX_DTX_N1 7 1

U

SB3_ATX_DRX_P2 72

U

SB3_ATX_DRX_N2 72

SB3_ARX_DTX_P2 72
SB3_ARX_DTX_N2 7 2

U

SB3_ATX_DRX_P3 42

U

SB3_ATX_DRX_N3 42

SB3_ARX_DTX_P3 42
SB3_ARX_DTX_N3 4 2

L

PC_AD0_R 58

L

PC_AD1_R 58

L

PC_AD2_R 58

L

PC_AD3_R 58

L

PC_CLK0_EC 58

A

PU_SPI_CLK_R 9

8

Type-A MB CHG

Type-A MB

T

ype-C MB

P

E_GPIO1

E

SPI_ALERT_L

L

PC_CLK1

MB SPI ROM

A

PU_SPI_CS#1

A

PU_SPI_MISO

A

PU_SPI_WP#

A

PU_SPI_CLK_R

2

R

C6154

2

C6166

R

2

R

C6181

R

C6180

A

PU_SPI_MISO

A

PU_SPI_WP#

A

PU_SPI_HOLD#

A

PU_SPI_CS#1

A

PU_SPI_TPMCS#

U

C7

1

C

S#

2

OLD#(IO3)

O(IO1)

H

D

3

P#(IO2)

W

4

ND

G

GD25LB64CSIGR_SOIC_8P

S

A00008K400

1

@EMC@

C680

R
10_0402_5%

1

2

2

R

R

R

R

R

+

1.8VALW

CC

V

C

I(IO0)

D

CC615
150P_0402_50V8J

1

10K_0402_5%

1

10K_0402_5%@

1

10K_0402_5%

1

1

C1706

1

C640

1

C642

1

C639

1

C646

8
7
6

LK

5

@EMC@

1 2

2

C

C636

10P_0402_50V8J

E

10K_0402_5%@

R

C1672

0_0603_5%

1

RS@

+

SPI_VCC

A

PU_SPI_HOLD#

A

PU_SPI_CLK_R

A

PU_SPI_MOSI

LPC_RST# 58

+

3VALW

+

3VS

2

10K_0402_5%@

2

10K_0402_5%

2

10K_0402_5%

2

10K_0402_5%

2

10K_0402_5%@

2

+

SPI_VCC

+

SPI_VCC

@

2

C635

C

0.1U_0201_10V6K

1

S

S

S

eeecccuuurrriiitttyyy CCClllaaassssssiiifffiiicccaaattt iiiooonnn

I

I

I

ssssssuuueeeddd DDDaaattteee

T

T

T

HHHIIISSS SSSHHHEEEEEETTT OOOFFF EEENNNGGGIIINNNEEEEEERRRIIINNNGGG DDDRRRAAAWWWIIINNNGGG IIISSS TTTHHHEEE PPPRRROOOPPPRRRIIIEEETTTAAARRRYYY PPPRRROOOPPPEEERRRTTTYYY OOOFFF CCCOOOMMMPPPAAALLL EEELLLEEECCCTTTRRROOONNNIIICCCSSS,,, IIINNNCCC... AAANNNDDD CCCOOONNNTTTAAAIIINNNSSS CCCOOONNNFFFIIIDDDEEENNNTTTIIIAAALLL
AAANNNDDD TTTRRRAAADDDEEE SSSEEECCCRRREEETTT IIINNNFFFOOORRRMMMAAATTTIIIOOONNN... TTTHHHIIISSS SSSHHHEEEEEETTT MMMAAAYYY NNNOOOTTT BBBEEE TTTRRRAAANNNSSSFFFEEERRREEEDDD FFFRRROOOMMM TTTHHHEEE CCCUUUSSSTTTOOODDDYYY OOOFFF TTTHHHEEE CCCOOOMMMPPPEEETTTEEENNNTTT DDDIIIVVVIIISSSIIIOOONNN OOOFFF RRR&&&DDD
DDDEEEPPPAAARRRTTTMMMEEENNNTTT EEEXXXCCCEEEPPPTTT AAASSS AAAUUUTTTHHHOOORRRIIIZZZEEEDDD BBBYYY CCCOOOMMMPPPAAALLL EEELLLEEECCCTTTRRROOONNNIIICCCSSS,,, IIINNNCCC... NNNEEEIIITTTHHHEEERRR TTTHHHIIISSS SSSHHHEEEEEETTT NNNOOORRR TTTHHHEEE IIINNNFFFOOORRRMMMAAATTTIIIOOONNN IIITTT CCCOOONNNTTTAAAIIINNNSSS

A

B

C

MMMAAAYYY BBBEEE UUUSSSEEEDDD BBBYYY OOORRR DDDIIISSSCCCLLLOOOSSSEEEDDD TTTOOO AAANNNYYY TTTHHHIIIRRRDDD PPPAAARRRTTTYYY WWWIIITTTHHHOOOUUUTTT PPPRRRIIIOOORRR WWWRRRIIITTTTTTEEENNN CCCOOONNNSSSEEENNNTTT OOOFFF CCCOOOMMMPPPAAALLL EEELLLEEECCCTTTRRROOONNNIIICCCSSS,,, IIINNNCCC...

2

2

2

000111888/// 111222///111888 222000111999///111222///111888

C

C

C

ooommmpppaaalll SSSeeecccrrreeettt DDDaaatttaaa

DDDeeeccciiippphhheeerrreeeddd DDDaaattt eee

D

C

C

C

T

T

T

iiitttllleee

SSSiiizzzeee DDDooocccuuummmeeennnttt NNNuuummmbbbeeerrr RRReeevvv

C

C

C

DDDaaattteee::: SSShhheeeeeettt

ooommmpppaaalll EEEllleeeccctttrrrooonnniiicccsss,,, IIInnnccc...

F

F

F

PPP555___(((555///777)))___CCCLLLKKK///UUUSSSBBB///SSSPPPIII///LLLPPPCCC

uuu ssstttooommm

F

F

F

HHH555000PPP MMM///BBB LLLAAA---HHH999000111PPP

E

o

o

o

111 000 999999WWWeeedddnnneeesssdddaaayyy,,, MMMaaayyy 111555,,, 222000111999

fff

1

1

1

AAA

A

M

ain Func = CPU

B

C

D

E

UC1F

T

o=1.5V

S

C8

A000066U00

V

out

G

ND

680P_0402_ 50V7K

V

EDC: 70A

in

DC: 53A

1

C

C120

SCL/MBDG:
16*22uF (BU)
1*180pF (BU)

+

RTCVCC

1

2

+

APU_CORE

D

C1

1

CHN202UPT _SC70-3

+

APU_CORE Cap place at Power Side

+

RTCBATT

J

RTC1

1

1

2

2

3

G

ND

4

G

ND

ACES_50271-00 20N-001

CONN@

S

P02000RO00

3

R

C6161

1K_0402_5%

1 2

+

RTCBATT

+

CHGRTC

2

TDC: 10A

+

APU_CORE_SOC

SCL/MBDG:
7*22uF (BU)
1*1uF (BU)

1 1

+APU_CORE_SOC Cap
place at Power Side

+

1.2V

C

C

C

C1059 22U_0603_6.3V6M

1

2

C
C1207 22U_0603_6.3V6M

C1060 22U_0603_6.3V6M

C1061 22U_0603_6.3V6M

1

2

+

VDDIO_AUDIO

C
C1192 1U_0201_6.3V6M

1

2

1

2

1

2

C
C1062 22U_0603_6.3V6M

1

2

C

C
C1063 22U_0603_6.3V6M

C1163 22U_0603_6.3V6M

1

1

2

2

SCL/MBDG:
1 *22uF (BO)
1*1uF (BU)

C

C

C
C1057 22U_0603_6.3V6M

C1058 22U_0603_6.3V6M

C1008 22U_0603_6.3V6M

1

1

1

2

2

2

2 2

A

ll BU(on bottom side under SOC)

+

1.8VS

R

C1677

0_0402_5%

2

1

RS@

1*180pF (BU)

SCL/MBDG:
9*22uF (BU)

+

1.2V

C

C

C

C

C1165 1U_0201_6.3V6M

C1093 180P_0402_50V8J

C1164 1U_0201_6.3V6M

1

1

1

2

2

2

+

3VS

R

C1676

0_0402_5%

1

RS@

C

C

C
C1078 0.22U_0402_16V7K

C1079 0.22U_0402_16V7K

C1081 0.22U_0402_16V7K

C1082 0.22U_0402_16V7K

1

1

1

1

2

2

2

2

A

CROSS VDDIO AND VSS SPLIT

SCL/MBDG:
1 *22uF (BO)
2*1uF (BO+BU)

+

3VS_APU

2

C

C

C

C1208 1U_0201_6.3V6M

C1137 22U_0603_6.3V6M

C1209 1U_0201_6.3V6M

1

1

1

2

2

2

2*1uF (BU)
4*0.22uF
1*180pF (BU)
2*180pF

C

C
C1167 180P_0402_50V8J

C1166 180P_0402_50V8J

1

1

2

2

+

+

B

O BU BUBO BO

3 3

+

1.8VS

C
C1189 22U_0603_6.3V6M

1

2

B

O

+

0.9VS

C

C

C1169 22U_0603_6.3V6M

C1168 22U_0603_6.3V6M

1

1

4 4

2

2

C

C
C1191 1U_0201_6.3V6M

C1190 1U_0201_6.3V6M

1

2

BO BU

C
C1170 1U_0201_6.3V6M

1

2

C
C1171 1U_0201_6.3V6M

1

2

SCL/MBDG:
1 *22uF (BO)
2*1uF (BO+BU)

C

C

C1177 1U_0201_6.3V6M

C1172 1U_0201_6.3V6M

1

1

2

2

C

C
C1187 1U_0201_6.3V6M

C1188 1U_0201_6.3V6M

1

1

2

2

1

2

SCL/MBDG:
1 *22uF (BO)
2*1uF (BO+BU)

SCL/MBDG:
2 *22uF (BO)
8*1uF (BOx4+BUx4)
1*180pF (BU)

+

3VALW

C
C1183 22U_0603_6.3V6M

+

0.9VALW

1

2

B

O BUBO

C
C1179 22U_0603_6.3V6M

1

2

+

1.8VALW

C
C1186 22U_0603_6.3V6M

1

2

B

O BUBO

C

C

C

C

C

C1174 1U_0201_6.3V6M

C1175 1U_0201_6.3V6M

C1173 1U_0201_6.3V6M

C1176 1U_0201_6.3V6M

1

1

2

2

C1178 180P_0402_50V8J

1

1

1

2

2

2

SCL/MBDG:
1 *22uF (BO)
2*1uF (BO+BU)

C

C
C1184 1U_0201_6.3V6M

C1185 1U_0201_6.3V6M

1

1

2

2

SCL/MBDG:
1 *22uF (BO)
3*1uF (BOx1+BUx2)

C

C

C
C1181 1U_0201_6.3V6M

C1180 1U_0201_6.3V6M

C1182 1U_0201_6.3V6M

1

1

1

2

2

2

+

EDC: 13A

TDC: 6A

+

1.2V

TDC :0.2A

+

VDDIO_AUDIO

TDC :0.25A

3VS_APU

TDC :2A

+

1.8VS

TDC :0.5A

1.8VALW

TDC :0.25A

+

3VALW

TDC :1A

0.9VALW

TDC :4A

+

0.9VS

TDC :4.5uA

+

RTC_APU_R

R

TC OF APU

close to UC1

C

C166

0.22U_0402 _16V7K

+

RTC_APU_R

1

2

A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A

A

A

A

A

A

A

A

A
A
A
A

A

W

=20mils

C

C923

1U_0201_6 .3V6M

M
M
M
N
N
N
P
P
R
R
T
U
U

V
W
W

Y

T

V
W
W

Y

Y

Y

A20

A23

A26

A28

A32

C20

C22

C25

C28

D23

D26

D28

D32

E20

E22

E25

E28

F23

F26

F28

F32

G20

G22

G25

G28

J20

A

J23

A

J26

A

J28

A

J32

A

K28

L28

A

L32

A

P12

L18

A

M17

L20

A

M19

L19

A

M18

L17

A

M16

L14

A

L15

A

M14

L13

A

M12

M13

N12

N13

T11

15
18
19
16
18
20
17
19
18
20
19
18
20
19
18
20
19

32
28
28
32
22
25
28

1

2

DDCR_SOC_1

V

DDCR_SOC_2

V

DDCR_SOC_3

V

DDCR_SOC_4

V

DDCR_SOC_5

V

DDCR_SOC_6

V

DDCR_SOC_7

V

DDCR_SOC_8

V

DDCR_SOC_9

V

DDCR_SOC_10

V

DDCR_SOC_11

V

DDCR_SOC_12

V

DDCR_SOC_13

V

DDCR_SOC_14

V

DDCR_SOC_15

V

DDCR_SOC_16

V

DDCR_SOC_17

V

DDIO_MEM_S3_1

V

DDIO_MEM_S3_2

V

DDIO_MEM_S3_3

V

DDIO_MEM_S3_4

V

DDIO_MEM_S3_5

V

DDIO_MEM_S3_6

V

DDIO_MEM_S3_7

V

DDIO_MEM_S3_8

V

DDIO_MEM_S3_9

V

DDIO_MEM_S3_10

V

DDIO_MEM_S3_11

V

DDIO_MEM_S3_12

V

DDIO_MEM_S3_13

V

DDIO_MEM_S3_14

V

DDIO_MEM_S3_15

V

DDIO_MEM_S3_16

V

DDIO_MEM_S3_17

V

DDIO_MEM_S3_18

V

DDIO_MEM_S3_19

V

DDIO_MEM_S3_20

V

DDIO_MEM_S3_21

V

DDIO_MEM_S3_22

V

DDIO_MEM_S3_23

V

DDIO_MEM_S3_24

V

DDIO_MEM_S3_25

V

DDIO_MEM_S3_26

V

DDIO_MEM_S3_27

V

DDIO_MEM_S3_28

V

DDIO_MEM_S3_29

V

DDIO_MEM_S3_30

V

DDIO_MEM_S3_31

V

DDIO_MEM_S3_32

V

DDIO_MEM_S3_33

V

DDIO_MEM_S3_34

V

DDIO_MEM_S3_35

V

DDIO_MEM_S3_36

V

DDIO_MEM_S3_37

V

DDIO_MEM_S3_38

V

DDIO_MEM_S3_39

V

DDIO_MEM_S3_40

V

DDIO_AUDIO

V

DD_33_1

V

DD_33_2

V

DD_18_1

V

DD_18_2

V

DD_18_S5_1

V

DD_18_S5_2

V

DD_33_S5_1

V

DD_33_S5_2

V

DDP_S5_1

V

DDP_S5_2

V

DDP_S5_3

V

DDP_1

V

DDP_2

V

DDP_3

V

DDP_4

V

DDP_5

V

DDBT_RTC_G

V

@

0_0603_5%

POWER

FP5 REV 0.90

ART 6 OF 13

P

P5_BGA_1140P

F

R

C6164

1K_0402_5%

1 2

12

@

0.1U_0201_ 10V6K

C

C119

C

LRP1

+

RTC_APU

V

DDCR_1

V

DDCR_2

V

DDCR_3

V

DDCR_4

V

DDCR_5

V

DDCR_6

V

DDCR_7

V

DDCR_8

V

DDCR_9

V

DDCR_10

V

DDCR_11

V

DDCR_12

V

DDCR_13

DDCR_14

V

V

DDCR_15

DDCR_16

V

DDCR_17

V

DDCR_18

V

DDCR_19

V

DDCR_20

V

DDCR_21

V

DDCR_22

V

DDCR_23

V

DDCR_24

V

DDCR_25

V

DDCR_26

V

DDCR_27

V

DDCR_28

V

DDCR_29

V

DDCR_30

V

DDCR_31

V

DDCR_32

V

DDCR_33

V

DDCR_34

V

DDCR_35

V

DDCR_36

V

DDCR_37

V

DDCR_38

V

DDCR_39

V

DDCR_40

V

DDCR_41

V

DDCR_42

V

DDCR_43

V

DDCR_44

V

DDCR_45

V

DDCR_46

V

DDCR_47

V

DDCR_48

V

DDCR_49

V

DDCR_50

V

DDCR_51

V

DDCR_52

V

DDCR_53

V

DDCR_54

V

DDCR_55

V

DDCR_56

V

DDCR_57

V

DDCR_58

V

DDCR_59

V

DDCR_60

V

DDCR_61

V

DDCR_62

V

DDCR_63

V

DDCR_64

V

DDCR_65

V

DDCR_66

V

DDCR_67

V

DDCR_68

V

DDCR_69

V

DDCR_70

V

DDCR_71

V

DDCR_72

V

DDCR_73

V

DDCR_74

V

DDCR_75

V

DDCR_76

V

DDCR_77

V

DDCR_78

V

DDCR_79

V

DDCR_80

V

DDCR_81

V

DDCR_82

V

DDCR_83

V

1

2

G

7

G

10

G

12

G

14

H

8

H

11

H

15

K

7

K

12

K

14

L

8

M

7

M

10

N

14

P

7

P

10
13

P

15

P

8

R

14

R

16

R

7

T

10

T

13

T

15

T

17

T

14

U

16

U

13

V

15

V

17

V

7

W

10

W

14

W

16

W

8

Y

13

Y

15

Y

17

Y

A7

A

A10

A

A14

A

A16

A

A18

A

B13

A

B15

A

B17

A

B19

A

C14

A

C16

A

C18

A

D7

A

D10

A

D13

A

D15

A

D17

A

D19

A

E8

A

E14

A

E16

A

E18

A

F7

A

F10

A

F13

A

F15

A

F17

A

F19

A

G14

A

G16

A

G18

A

H13

A

H15

A

H17

A

H19

A

J7

A

J10

A

J14

A

J16

A

J18

A

K13

A

K15

A

K17

A

K19

A

V

U

AP2138N-1.5TR G1_SOT23-3

3

2

B

Ox4

N

eed OPEN

BUx4 BO BU

A

B

UBO

B

O

B

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

for Clear CMOS

C

C

C

ompal Secret Data

ompal Secret Data

2

2

2

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

ompal Secret Data

D

D

D

eciphered Date

eciphered Date

eciphered Date

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

ustom

ustom

ustom

Date: Sheet

Date: Sheet

D

Date: Sheet

ompal Electronics, Inc.

(

(

(

6/7)_PWR

6/7)_PWR

6/7)_PWR

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

E

o

o

o

11 99Wednesday, May 15, 201 9

11 99Wednesday, May 15, 201 9

11 99Wednesday, May 15, 201 9

1

1

1

A

A

A

f

f

f

5

M

ain Func = CPU

N

12

V

A

3

V

A

5

V

A

7

V

A

10

V

A

12

V

A

14

V

A

16

V

A

19

D D

C C

B B

V

A

21

V

A

23

V

A

26

V

A

30

V

C

3

V

C

32

V

D

16

V

D

18

V

D

20

V

E

7

V

E

8

V

E

10

V

E

11

V

E

12

V

E

13

V

E

14

V

E

15

V

E

16

V

E

18

V

E

19

V

E

20

V

E

21

V

E

22

V

E

23

V

E

25

V

E

26

V

E

27

V

F

5

V

F

28

V

G

1

V

G

5

V

G

16

V

G

19

V

G

21

V

G

23

V

G

26

V

G

28

V

G

32

V

H

5

V

H

13

V

H

18

V

H

20

V

H

22

V

H

25

V

H

28

V

K

1

V

K

5

V

K

16

V

K

19

V

K

21

V

K

22

V

K

26

V

K

28

V

@

SS_316

SS_1

SS_2

SS_3

SS_4

SS_5

SS_6

SS_7

SS_8

SS_9

SS_10

SS_11

SS_12

SS_13

SS_14

SS_15

SS_16

SS_17

SS_18

SS_19

SS_20

SS_21

SS_22

SS_23

SS_24

SS_25

SS_26

SS_27

SS_28

SS_29

SS_30

SS_31

SS_32

SS_33

SS_34

SS_35

SS_36

SS_37

SS_38

SS_39

SS_40

SS_41

SS_42

SS_43

SS_44

SS_45

SS_46

SS_47

SS_48

SS_49

SS_50

SS_51

SS_52

SS_53

SS_54

SS_55

SS_56

SS_57

SS_58

SS_59

SS_60

SS_61

GND

FP5 REV 0.90
P

ART 7 OF 13

F

UC1G

SS_62

V

SS_63

V

SS_64

V

SS_65

V

SS_66

V

SS_67

V

SS_68

V

SS_69

V

V

SS_70

V

SS_71

V

SS_72

V

SS_73

V

SS_74

V

SS_75

V

SS_76

V

SS_77

V

SS_78

V

SS_79

V

SS_80

V

SS_81

V

SS_82

V

SS_83

V

SS_84

V

SS_85

V

SS_86

V

SS_87

V

SS_88

V

SS_89

V

SS_90

V

SS_91

V

SS_92

V

SS_93

V

SS_94

V

SS_95

V

SS_96

V

SS_97

V

SS_98

V

SS_99

V

SS_100

V

SS_101

V

SS_102

V

SS_103

V

SS_104

V

SS_105

V

SS_106

V

SS_107

V

SS_108

V

SS_109

V

SS_110

V

SS_111

V

SS_112

V

SS_113

V

SS_114

V

SS_115

V

SS_116

V

SS_117

V

SS_118

V

SS_119

V

SS_120

V

SS_121

V

SS_122

V

SS_123

P5_BGA_ 1140P

32

K

5

L

13

L

15

L

18

L

20

L

25

L

28

L

M

1

M

5

M

12

M

21

M

23

M

26

M

28

M

32

N

4

N

5

N

8

N

11

N

13

N

15

N

17

N

19

N

22

N

25

N

28

P

1

P

5

P

14

P

16

P

18

P

20

P

23

P

26

P

28

P

32

R

5

R

11

R

12

R

13

R

15

R

17

R

19

R

22

R

25

R

28

R

30

T

1

T

5

T

14

T

16

T

18

T

20

T

23

T

26

T

28

U

13

U

15

U

17

U

19

V

5

UC1M

18

A

AM0_CSI2_CLOCKP

C

18

C

AM0_CSI2_CLOCKN

C

15

A

AM0_CSI2_DATAP0

C

15

C

AM0_CSI2_DATAN0

C

16

B

AM0_CSI2_DATAP1

C

16

C

AM0_CSI2_DATAN1

C

19

C

AM0_CSI2_DATAP2

C

18

B

AM0_CSI2_DATAN2

C

17

B

AM0_CSI2_DATAP3

C

17

D

AM0_CSI2_DATAN3

C

12

D

AM1_CSI2_CLOCKP

C

12

B

AM1_CSI2_CLOCKN

C

13

C

AM1_CSI2_DATAP0

C

13

A

AM1_CSI2_DATAN0

A A

11

B

12

C

13

J

C

AM1_CSI2_DATAP1

C

AM1_CSI2_DATAN1

C

SVD_6

R

@

5

CAMERAS

FP5 REV 0.90

ART 13 OF 13

P

F

P5_BGA_ 1140P

AM0_CLK

C

AM0_I2C_SCL

C

AM0_I2C_SDA

C

AM0_SHUTDOWN

C

AM1_CLK

C

AM1_I2C_SCL

C

AM1_I2C_SDA

C

AM1_SHUTDOWN

C

AM_PRIV_LED

C

AM_IR_ILLU

C

B

D
C

B

B

A
C

D

D
D

4

8

V

11

V

12

V

14

V

16

V

18

V

20

V

22

V

25

V

1

W

5

W

13

W

15

W

17

W

19

W

23

W

26

W

5

Y

11

Y

12

Y

14

Y

16

Y

18

Y

20

Y

A1

A

A5

A
A13

A

A15

A

A17

A

A19

A

B14

A

B16

A

B18

A

B20

A

C5

A

C8

A

C11

A

C12

A

C13

A

C15

A

C17

A

C19

A

D1

A

D5

A

D14

A

D16

A

D18

A

D20

A

E5

A
E11

A

E12

A

E13

A

E15

A

E17

A

E19

A

F1

A

F5

A
F14

A

F16

A

F18

A

F20

A

G5

A

@

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

SS_124

SS_125

SS_126

SS_127

SS_128

SS_129

SS_130

SS_131

SS_132

SS_133

SS_134

SS_135

SS_136

SS_137

SS_138

SS_139

SS_140

SS_141

SS_142

SS_143

SS_144

SS_145

SS_146

SS_147

SS_148

SS_149

SS_150

SS_151

SS_152

SS_153

SS_154

SS_155

SS_156

SS_157

SS_158

SS_159

SS_160

SS_161

SS_162

SS_163

SS_164

SS_165

SS_166

SS_167

SS_168

SS_169

SS_170

SS_171

SS_172

SS_173

SS_174

SS_175

SS_176

SS_177

SS_178

SS_179

SS_180

SS_181

SS_182

SS_183

SS_184

SS_185

3

UC1H

GND

FP5 REV 0.90

ART 8 OF 13

P

F

V

SS_186

V

SS_187

V

SS_188

V

SS_189

V

SS_190

V

SS_191

V

SS_192

V

SS_193

V

SS_194

V

SS_195

V

SS_196

V

SS_197

V

SS_198

V

SS_199

V

SS_200

V

SS_201

V

SS_202

V

SS_203

V

SS_204

V

SS_205

V

SS_206

V

SS_207

V

SS_208

V

SS_209

V

SS_210

V

SS_211

V

SS_212

V

SS_213

V

SS_214

V

SS_215

V

SS_216

V

SS_217

V

SS_218

V

SS_219

V

SS_220

V

SS_221

V

SS_222

V

SS_223

V

SS_224

V

SS_225

SS_226

V

SS_227

V

SS_228

V

SS_229

V

SS_230

V

SS_231

V

SS_232

V

SS_233

V

SS_234

V

SS_235

V

SS_236

V

SS_237

V

SS_238

V

SS_239

V

SS_240

V

SS_241

V

SS_242

V

SS_243

V

SS_244

V

SS_245

V

SS_246

V

SS_247

V

P5_BGA_ 1140P

2

1

UC1K

A

G8

A

G11

A

G12

A

G13

A

G15

A

G17

A

G19

A

H14

A

H16

A

H18

A

H20

A

J1

A

J5

A

J13

A

J15

A

J17

A

J19

A

K5

A

K8

A

K11

A

K12

A

K14

A

K16

A

K18

A

K20

A

K22

A

K25

A

L1

A

L5

A

L7

A

L10

A

L12

A

L16

A

L23

A

L26

A

M5

A

M8

A

M15

A

M20

A

M22
M25

A

M28

A

N1

A

N5

A

N7

A

N10

A

N15

A

N18

A

N21

A

N23

A

N26

A

N28

A

N32

A

P5

A

P8

A

P13

A

P15

A

P18

A

P20

A

P25

A

P28

A

R1

A

A

R5

A

R7

A

R12

A

R14

A

R16

A

R19

A

R21

A

R26

A

R28

A

R32
A

U5

A

U8

A

U11

A

U13

A

U15

A

U18

A

U20

A

U22

A

U25

A

U28
A

V1

A

V5

A

V7

A

V10

A

V12

A

V14

A

V16

A

V19

A

V21

A

V23

A

V26

A

V28

A

V32

A

W5

A

W28

A

Y6

A

Y7

A

Y8

A

Y10

A

Y11

A

Y12

A

Y13

A

Y14

A

Y15

A

Y16

A

Y18

A

Y19

A

Y20

A

Y21

A

Y22

A

Y23

A

Y25

A

Y26

A

Y27
B

B1

B

B20

B

B32
B

D3

B

D7

B

D10

B

D12

B

D14

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

@

SS_248

SS_249

SS_250

SS_251

SS_252

SS_253

SS_254

SS_255

SS_256

SS_257

SS_258

SS_259

SS_260

SS_261

SS_262

SS_263

SS_264

SS_265

SS_266

SS_267

SS_268

SS_269

SS_270

SS_271

SS_272

SS_273

SS_274

SS_275

SS_276

SS_277

SS_278

SS_279

SS_280

SS_281

SS_282

SS_283

SS_284

SS_285

SS_286

SS_287

SS_288

SS_289

SS_290

SS_291

SS_292

SS_293

SS_294

SS_295

SS_296

SS_297

SS_298

SS_299

SS_300

SS_301

SS_302

SS_303

SS_304

SS_305

SS_306

SS_307

SS_308

SS_309

GND/RSVD

FP5 REV 0.90

P

ART 11 OF 13

V

SS_310

V

SS_311

V

SS_312

V

SS_313

V

SS_314

V

SS_315

R

SVD_1

R

SVD_5

R

SVD_7

R

SVD_8

R

SVD_9

R

SVD_10

R

SVD_11

R

SVD_12

R

SVD_13

R

SVD_22

R

SVD_23

R

SVD_30

R

SVD_31

R

SVD_37

R

SVD_44

R

SVD_49

R

SVD_50

R

SVD_57

R

SVD_58

R

SVD_59

R

SVD_60

R

SVD_69

R

SVD_70

R

SVD_71

R

SVD_74

R

SVD_75

R

SVD_78

R

SVD_79

R

SVD_80

R

SVD_81

R

SVD_82

R

SVD_83

R

SVD_87

R

SVD_88

R

SVD_14

R

SVD_84

R

SVD_85

R

SVD_86

F

P5_BGA_ 1140P

B

D16

B

D19

B

D21

B

D23

B

D26

B

D30

B

20

G

3

J

20

K

3

K

6

K

20

M

3

M

6

M

13

P

6

P

22

T

3

T

6

T

29

W

6

W

21

W

22

Y

21

Y

27

A

A3

A

A6

A

C29

A

D3

A

D6

A

F3

A

F6

A

F30

A

J6

A

J24

A

K23

A

K27

A

L3

A

N29

A

N31

M

14

A

L6

A

L11

A

N16

UC1L

11

T

SVD_32

15

15
14

13

10

11
11

R

C7

A

SVD_66

R

9

Y

SVD_55

R

10

Y

SVD_56

R

11

W

SVD_47

R

12

W

SVD_48

R

9

V

SVD_38

R

10

V

SVD_39

R

A12

A

SVD_64

R

C10

A

SVD_68

R

11

13
10

4

@

S

S

S

ecurity Classif ication

ecurity Classif ication

ecurity Classif ication

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

RSVD

FP5 REV 0.90

ART 12 OF 13

P

P5_BGA_ 1140P

F

2

2

2

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

3

R

R

R

R

R

R

R

R

R

R

R

R

SVD_62

SVD_61

SVD_65

SVD_72

SVD_67

SVD_63

SVD_33

SVD_73

SVD_53

SVD_54

SVD_45

SVD_46

A
A
A

A

A
A

T
A

Y
Y

W
W

A9
A8
C6

D11

C9
A11

12
D12

6
7

8
9

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered D ate

eciphered D ate

eciphered D ate

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

C

C

C

ustom

ustom

ustom

Date: Sheet

Date: Sheet

2

Date: Sheet

ompal Electronics, Inc.

F

F

F

P5_(7/7)_GND/RSVD/CSI

P5_(7/7)_GND/RSVD/CSI

P5_(7/7)_GND/RSVD/CSI

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

1

1

1

1

A

A

A

o

o

o

f

12 99Wed nesday, May 15, 2019

f

12 99Wed nesday, May 15, 2019

f

12 99Wed nesday, May 15, 2019

5

D D

C C

4

3

2

1

R

B B

A A

5

4

eserve Page

S

S

S

ecurity Classif ication

ecurity Classif ication

ecurity Classif ication

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

2

2

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

3

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered D ate

eciphered D ate

eciphered D ate

2

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

Reserve Page

Reserve Page

Reserve Page

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

o

o

o

f

13 99Wed nesday, May 15, 2019

f

13 99Wed nesday, May 15, 2019

f

13 99Wed nesday, May 15, 2019

1

1

1

1

A

A

A

5

D D

C C

4

3

2

1

R

B B

A A

5

4

eserve Page

S

S

S

ecurity Classif ication

ecurity Classif ication

ecurity Classif ication

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

2

2

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

3

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered D ate

eciphered D ate

eciphered D ate

2

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

Reserve Page

Reserve Page

Reserve Page

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

o

o

o

f

14 99Wed nesday, May 15, 2019

f

14 99Wed nesday, May 15, 2019

f

14 99Wed nesday, May 15, 2019

1

1

1

1

A

A

A

5

D D

C C

4

3

2

1

R

B B

A A

5

4

eserve Page

S

S

S

ecurity Classif ication

ecurity Classif ication

ecurity Classif ication

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

2

2

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

3

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered D ate

eciphered D ate

eciphered D ate

2

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

Reserve Page

Reserve Page

Reserve Page

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

o

o

o

f

15 99Wed nesday, May 15, 2019

f

15 99Wed nesday, May 15, 2019

f

15 99Wed nesday, May 15, 2019

1

1

1

1

A

A

A

5

D D

C C

4

3

2

1

R

B B

A A

5

4

eserve Page

S

S

S

ecurity Classif ication

ecurity Classif ication

ecurity Classif ication

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

2

2

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

3

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered D ate

eciphered D ate

eciphered D ate

2

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

Reserve Page

Reserve Page

Reserve Page

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

o

o

o

f

16 99Wed nesday, May 15, 2019

f

16 99Wed nesday, May 15, 2019

f

16 99Wed nesday, May 15, 2019

1

1

1

1

A

A

A

5

D D

C C

4

3

2

1

R

B B

A A

5

4

eserve Page

S

S

S

ecurity Classif ication

ecurity Classif ication

ecurity Classif ication

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

2

2

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

3

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered D ate

eciphered D ate

eciphered D ate

2

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

Reserve Page

Reserve Page

Reserve Page

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

o

o

o

f

17 99Wed nesday, May 15, 2019

f

17 99Wed nesday, May 15, 2019

f

17 99Wed nesday, May 15, 2019

1

1

1

1

A

A

A

5

D D

C C

4

3

2

1

R

B B

A A

5

4

eserve Page

S

S

S

ecurity Classif ication

ecurity Classif ication

ecurity Classif ication

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

2

2

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

3

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered D ate

eciphered D ate

eciphered D ate

2

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

Reserve Page

Reserve Page

Reserve Page

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

o

o

o

f

18 99Wed nesday, May 15, 2019

f

18 99Wed nesday, May 15, 2019

f

18 99Wed nesday, May 15, 2019

1

1

1

1

A

A

A

5

D D

C C

4

3

2

1

R

B B

A A

5

4

eserve Page

S

S

S

ecurity Classif ication

ecurity Classif ication

ecurity Classif ication

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

2

2

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

3

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered D ate

eciphered D ate

eciphered D ate

2

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

Reserve Page

Reserve Page

Reserve Page

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

o

o

o

f

19 99Wed nesday, May 15, 2019

f

19 99Wed nesday, May 15, 2019

f

19 99Wed nesday, May 15, 2019

1

1

1

1

A

A

A

5

D D

C C

4

3

2

1

R

B B

A A

5

4

eserve Page

S

S

S

ecurity Classif ication

ecurity Classif ication

ecurity Classif ication

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

2

2

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

3

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered D ate

eciphered D ate

eciphered D ate

2

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

Reserve Page

Reserve Page

Reserve Page

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

o

o

o

f

20 99Wed nesday, May 15, 2019

f

20 99Wed nesday, May 15, 2019

f

20 99Wed nesday, May 15, 2019

1

1

1

1

A

A

A

5

D D

C C

4

3

2

1

R

B B

A A

5

4

eserve Page

S

S

S

ecurity Classif ication

ecurity Classif ication

ecurity Classif ication

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

2

2

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

3

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered D ate

eciphered D ate

eciphered D ate

2

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

Reserve Page

Reserve Page

Reserve Page

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

o

o

o

f

21 99Wed nesday, May 15, 2019

f

21 99Wed nesday, May 15, 2019

f

21 99Wed nesday, May 15, 2019

1

1

1

1

A

A

A

5

D D

C C

4

3

2

1

R

B B

A A

5

4

eserve Page

S

S

S

ecurity Classif ication

ecurity Classif ication

ecurity Classif ication

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

2

2

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

3

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered D ate

eciphered D ate

eciphered D ate

2

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

Reserve Page

Reserve Page

Reserve Page

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

o

o

o

f

22 99Wed nesday, May 15, 2019

f

22 99Wed nesday, May 15, 2019

f

22 99Wed nesday, May 15, 2019

1

1

1

1

A

A

A

A

B

C

D

E

Reverse Type-4H

2-3A to 1 DIMMs/channel

DR_A_CLK0

7DDR_A_CLK0
7DDR_A_CLK0#
7DDR_A_CLK1

7DDR_A_MA14_W E#
7DDR_A_MA15_CAS#
7DDR_A_MA16_RAS#

9,24SMB_0_SDA
9,24SMB_0_SCL

B

7DDR_A_CLK1#

7DDR_A_CKE0
7DDR_A_CKE1

7DDR_A_CS0#
7DDR_A_CS1#

7DDR_A_ODT0
7DDR_A_ODT1

7DDR_A_BG0

7DDR_A_BG1
7DDR_A_BA0
7DDR_A_BA1

7DDR_A_MA[13..0]

7DDR_A_ACT#

7DDR_A_PAR
7DDR_A_ALERT#

7DDR_A_EVENT#

7DDR_A_RST#

7DDR_A_DM[7..0]

Address : A0

1 1

+

3VS

12

12

12

RD50_0402_5%

@

12

12

R

0_0402_5%

RS@

D8

Layout Note:
Place near JDIMM1

2 2

+

1.2V

1U_0201_6.3V6M

C

1

D2

2

+

1.2V

10U_0402_6.3

C

1

D10

2

V6M

3 3

+

1.2V

0.1U_0201_10V6K
C

2

D61

1

Layout Note:
Place near JDIMM1.257,259

4 4

10U_0402_6.3

C

1

D23

2

V6M

R

0_0402_5%

RD60_0402_5%

D7

@

@

DR_A_SA2

D

DR_A_SA1

D

DR_A_SA0

D

12

R

0_0402_5%

RS@

R

0_0402_5%

RS@

D10

D9

N

ote:
Check voltage tolerance of
VREF_DQ at the DIMM socket

CRB use 0.1uF x12 (6 pop,6 unpop),180pF x1,100uF x2

1U_0201_6.3V6M

1U_0201_6.3V6M

C

1

1

D3

2

2

10U_0402_6.3

10U_0402_6.3

C

1

1

D11

2

2

V6M

V6M

0.1U_0201_10V6K

0.1U_0201_10V6K
C

2

2

D62

1

1

CRB use 0.1uF x2,180pF x1

+

2.5V

10U_0402_6.3

C

1

D24

2

V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

C

1

D4

2

10U_0402_6.3

C

1

D12

2

V6M

0.1U_0201_10V6K

C

2

D63

1

1U_0201_6.3V6M

C

1

D25

2

A

1U_0201_6.3V6M

C
D5

C
D13

C
D64

C

C

1

1

D6

D7

2

2

10U_0402_6.3

1

2

V6M

10U_0402_6.3

10U_0402_6.3

C
D14

C

C

1

1

D98

D15

2

2

V6M

V6M

180P_0402_50V8J

C

2

D65

1

Layout Note:
Place near JDIMM1.255

D1

@EMC@

C
.1U_0402_1 6V7K

DDR4 support Even Parity check in DRAMs.

DR_A_RST#

D

12

Follow MA51

1

@

+

D18

C
330U_D2_2 V_Y

2

SGA00009S00
330U 2V H1.9
9mohm POLY

CRB use 1uF x1

+

3VS

1U_0201_6.3V6M

C

1

D26

2

D

DR_A_CLK0#

D

DR_A_CLK1

D

DR_A_CLK1#

D

DR_A_CKE0

D

DR_A_CKE1

D

DR_A_CS0#

D

DR_A_CS1#

D

DR_A_ODT0

D

DR_A_ODT1

D

DR_A_BG0

D

DR_A_BG1

D

DR_A_BA0

D

DR_A_BA1

D

DR_A_MA0

D

DR_A_MA1

D

DR_A_MA2

D

DR_A_MA3

D

DR_A_MA4

D

DR_A_MA5

D

DR_A_MA6

D

DR_A_MA7

D

DR_A_MA8

D

DR_A_MA9

D

DR_A_MA10

D

DR_A_MA11

D

DR_A_MA12

D

DR_A_MA13

D

DR_A_MA14_W E#

D

DR_A_MA15_CAS#

D

DR_A_MA16_RAS#

D

DR_A_ACT#

D

DR_A_PAR

D

DR_A_ALERT#

D

DR_A_EVENT#

D

DR_A_RST#

D

MB_0_SDA

S

MB_0_SCL

S

DR_A_SA2

D

DR_A_SA1

D

DR_A_SA0

D

DR_A_DM0

D

DR_A_DM1

D

DR_A_DM2

D

DR_A_DM3

D

DR_A_DM4

D

DR_A_DM5

D

DR_A_DM6

D

DR_A_DM7

D

JDIMM1A

REVERSE

137

C

K0(T)

139

C

K0#(C)

138

C

K1(T)

140

C

K1#(C)

109

C

KE0

110

C

KE1

149

S

0#

157

S

1#

162

2#/C0

S

165

S

3#/C1

155

O

DT0

161

O

DT1

115

B

G0

113

B

G1

150

B

A0

145

B

A1

144

A

0

133

A

1

132

A

2

131

A

3

128

A

4

126

A

5

127

A

6

122

A

7

125

A

8

121

A

9

146

A

10_AP

120

A

11

119

A

12

158

A

13

151

A

14_WE#

156

A

15_CAS#

152

A

16_RAS#

114

A

CT#

143

P

ARITY

116

A

LERT#

134

E

VENT#

108

ESET#

R

254

DA

S

253

S

CL

166

A2

S

260

A1

S

256

A0

S

92

C

B0_NC

91

C

B1_NC

101

C

B2_NC

105

C

B3_NC

88

C

B4_NC

87

C

B5_NC

100

C

B6_NC

104

C

B7_NC

97

D

QS8(T)

95

D

QS8#(C)

12

D

M0#/DBI0#

33

D

M1#/DBI1#

54

D

M2#/DBI2#

75

D

M3#/DBI3#

178

D

M4#/DBI4#

199

D

M5#/DBI5#

220

D

M6#/DBI6#

241

D

M7#/DBI7#

96

D

M8#/DBI8#

LOTES_ADDR02 06-P001A

CONN@

S

P07001EGA0

D

Q0

D

Q1

D

Q2

D

Q3

D

Q4

D

Q5

D

Q6

D

Q7

D

QS0(T)

D

QS0#(C)

D

Q8

D

Q9

D

Q10

D

Q11

D

Q12

D

Q13

D

Q14

D

Q15

D

QS1(T)

D

QS1#(C)

D

Q16

D

Q17

D

Q18

D

Q19

D

Q20

D

Q21

D

Q22

D

Q23

D

QS2(T)

D

QS2#(C)

D

Q24

D

Q25

D

Q26

D

Q27

D

Q28

D

Q29

D

Q30

D

Q31

D

QS3(T)

D

QS3#(C)

D

Q32

D

Q33

D

Q34

D

Q35

D

Q36

D

Q37

D

Q38

D

Q39

D

QS4(T)

D

QS4#(C)

D

Q40

D

Q41

D

Q42

D

Q43

D

Q44

D

Q45

D

Q46

D

Q47

D

QS5(T)

D

QS5#(C)

D

Q48

D

Q49

D

Q50

D

Q51

D

Q52

D

Q53

D

Q54

D

Q55

D

QS6(T)

D

QS6#(C)

D

Q56

D

Q57

D

Q58

D

Q59

D

Q60

D

Q61

D

Q62

D

Q63

D

QS7(T)

D

QS7#(C)

S

S

S

eeecccuuurrriii tttyyy CCClllaaassssssiii fffiiicccaaatttiiiooonnn

T

T

T

HHHIIISSS SSSHHHEEEEEETTT OOOFFF EEENNNGGGIIINNNEEEEEERRRIIINNNGGG DDDRRRAAAWWWIIINNNGGG IIISSS TTTHHHEEE PPPRRROOOPPPRRRIIIEEETTTAAARRRYYY PPPRRROOOPPPEEERRRTTTYYY OOOFFF CCCOOOMMMPPPAAALLL EEELLLEEECCCTTTRRROOONNNIIICCCSSS,,, IIINNNCCC... AAANNNDDD CCCOOONNNTTTAAAIIINNNSSS CCCOOONNNFFFIIIDDDEEENNNTTTIIIAAALLL
AAANNNDDD TTTRRRAAADDDEEE SSSEEECCCRRREEETTT IIINNNFFFOOORRRMMMAAATTTIIIOOONNN... TTTHHHIIISSS SSSHHHEEEEEETTT MMMAAAYYY NNNOOOTTT BBBEEE TTTRRRAAANNNSSSFFFEEERRREEEDDD FFFRRROOOMMM TTTHHHEEE CCCUUUSSSTTTOOODDDYYY OOOFFF TTTHHHEEE CCCOOOMMMPPPEEETTTEEENNNTTT DDDIIIVVVIIISSSIIIOOONNN OOOFFF RRR&&&DDD
DDDEEEPPPAAA RRRTTTMMMEEENNNTTT EEEXXXCCCEEEPPPTTT AAASSS AAAUUUTTTHHHOOORRRIIIZZZEEEDDD BBBYYY CCCOOOMMMPPPAAALLL EEELLLEEECCCTTTRRROOONNNIIICCCSSS,,, IIINNNCCC... NNNEEEIIITTTHHHEEERRR TTTHHHIIISSS SSSHHHEEEEEETTT NNNOOORRR TTTHHHEEE IIINNNFFFOOORRRMMMAAATTTIIIOOONNN IIITTT CCCOOONNNTTTAAA IIINNNSSS
MMMAAAYYY BBBEEE UUUSSSEEEDDD BBBYYY OOORRR DDDIIISSSCCCLLLOOOSSSEEEDDD TTTOOO AAANNNYYY TTTHHHIIIRRRDDD PPPAAARRRTTTYYY WWWIIITTTHHHOOOUUUTTT PPPRRRIIIOOORRR WWWRRRIIITTTTTTEEENNN CCCOOONNNSSSEEENNNTTT OOOFFF CCCOOOMMMPPPAAALLL EEELLLEEECCCTTTRRROOONNNIIICCCSSS,,, IIINNNCCC...

C

8
7
20
21
4
3
16
17
13
11

28
29
41
42
24
25
38
37
34
32

50
49
62
63
46
45
58
59
55
53

70
71
83
84
66
67
79
80
76
74

174
173
187
186
170
169
183
182
179
177

195
194
207
208
191
190
203
204
200
198

216
215
228
229
211
212
224
225
221
219

237
236
249
250
232
233
245
246
242
240

I

I

I

ssssssuuueeeddd DDDaaattteee

DR_A_DQ0

D

DR_A_DQ1

D

DR_A_DQ2

D

DR_A_DQ3

D

DR_A_DQ4

D

DR_A_DQ5

D

DR_A_DQ6

D

DR_A_DQ7

D

DR_A_DQS0

D

DR_A_DQS0#

D

DR_A_DQ8

D

DR_A_DQ9

D

DR_A_DQ10

D

DR_A_DQ11

D

DR_A_DQ12

D

DR_A_DQ13

D

DR_A_DQ14

D

DR_A_DQ15

D

DR_A_DQS1

D

DR_A_DQS1#

D

DR_A_DQ16

D

DR_A_DQ17

D

DR_A_DQ18

D

DR_A_DQ19

D

DR_A_DQ20

D

DR_A_DQ21

D

DR_A_DQ22

D

DR_A_DQ23

D

DR_A_DQS2

D

DR_A_DQS2#

D

DR_A_DQ24

D

DR_A_DQ25

D

DR_A_DQ26

D
DDR_A_DQ27

DR_A_DQ28

D

DR_A_DQ29

D
DDR_A_DQ30

DR_A_DQ31

D

DR_A_DQS3

D

DR_A_DQS3#

D

DDR_A_DQ32
DDR_A_DQ33
DDR_A_DQ34
DDR_A_DQ35
DDR_A_DQ36
DDR_A_DQ37
DDR_A_DQ38
DDR_A_DQ39

DR_A_DQS4

D

DR_A_DQS4#

D

DDR_A_DQ40
D

DR_A_DQ41

D

DR_A_DQ42

D

DR_A_DQ43

D

DR_A_DQ44

D

DR_A_DQ45

D

DR_A_DQ46

D

DR_A_DQ47
DR_A_DQS5

D

DR_A_DQS5#

D

D

DR_A_DQ48

D

DR_A_DQ49

D

DR_A_DQ50

D

DR_A_DQ51

D

DR_A_DQ52

D

DR_A_DQ53

D

DR_A_DQ54

D

DR_A_DQ55
DR_A_DQS6

D

DR_A_DQS6#

D

D

DR_A_DQ56

D

DR_A_DQ57

D

DR_A_DQ58

D

DR_A_DQ59

D

DR_A_DQ60

D

DR_A_DQ61

D

DR_A_DQ62

D

DR_A_DQ63
DR_A_DQS7

D

DR_A_DQS7#

D

DDR_A_DQ[7..0] 7

Follow CRB design

+

RD3

1K_0402_1%

R

D4

1K_0402_1%

1.2V

1 2

1

5mil

C
D20 4.7U_0402_6.3V6M

2

1

2

1

D

DR_A_DQS0 7

D

DR_A_DQS0# 7

D

DR_A_DQ[15..8] 7

D

DR_A_DQS1 7

D

DR_A_DQS1# 7

D

DR_A_DQ[23..16] 7

D

DR_A_DQS2 7

D

DR_A_DQS2# 7

D

DR_A_DQ[31..24] 7

Place near to SO-DIMM connector.

D

DR_A_DQS3 7

D

DR_A_DQS3# 7

D

DR_A_DQ[39..32] 7

D

DR_A_DQS4 7

D

DR_A_DQS4# 7

D

DR_A_DQ[47..40] 7

D

DR_A_DQS5 7

D

DR_A_DQS5# 7

D

DR_A_DQ[55..48] 7

D

DR_A_DQS6 7

D

DR_A_DQS6# 7

D

DR_A_DQ[63..56] 7

D

DR_A_DQS7 7

D

DR_A_DQS7# 7

C

C

C

2

2

2

000111888/// 111222///111888 222000111999///111222///111888

ooommmpppaaalll SSSeeecccrrreeettt DDDaaatttaaa

D

D

D

eeeccciiippphhheeerrreeeddd DDDaaattteee

D

+

1.2V

DIMM1B

J

REVERSE

111

DD1

V

V

112

DD2

V

V

117

DD3

V

V

118

DD4

V

V

123

DD5

V

V

124

DD6

V

V

129

DD7

V

V

130

DD8

V

+

+

VREFA_CA

C
D22 0.1U_0201_10V6K

2

1

3VS

C

C

D19 1000P_0402_50V7K

D21 0.1U_0201_10V6K

1

2

2

1

T

T

T

iiitttllleee

SSSiiizzz eee DDDooocccuuummmeeennnttt NNNuuummmbbbeeerrr RRReeevvv

C

C

C

uuussstttooommm

DDDaaattteee::: SSShhheeeeeettt

V

135

DD9

V

V

136

DD10

V

255

DDSPD

V

164

REFCA

V

1

SS

V

2

SS

V

5

SS

V

6

SS

V

9

SS

V

10

SS

V

14

SS

V

15

SS

V

18

SS

V

19

SS

V

22

SS

V

23

SS

V

26

SS

V

27

SS

V

30

SS

V

31

SS

V

35

SS

V

36

SS

V

39

SS

V

40

SS

V

43

SS

V

44

SS

V

47

SS

V

48

SS

V

51

SS

V

52

SS

V

56

SS

V

57

SS

V

60

SS

V

61

SS

V

64

SS

V

65

SS

V

68

SS

V

69

SS

V

72

SS

V

73

SS

V

77

SS

V

78

SS

V

81

SS

V

82

SS

V

85

SS

V

86

SS

V

89

SS

V

90

SS

V

93

SS

V

94

SS

V

98

SS

V

262

ND

G

LOTES_ADDR02 06-P001A

CONN@

P07001EGA0

S

Layout Note:
Place near JDIMM1.258

CRB use 4.7uF x1,0.1uF x1

+

0.6VS

10U_0402_6.3

10U_0402_6.3

C

C

1

1

D28

D27

2

2

V6M

V6M

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

DDR4_DIMMA

DDR4_DIMMA

DDR4_DIMMA

FH50P M/B LA-H901P

FH50P M/B LA-H901P

FH50P M/B LA-H901P

DD11
DD12
DD13
DD14
DD15
DD16
DD17
DD18
DD19

V
V

G

E

+

1.2V

141
142
147
148
153
154
159
160

+

0.6VS

163

258

TT

V

257

PP1

259

PP2

99

SS

V

102

SS

V

103

SS

V

106

SS

V

107

SS

V

167

SS

V

168

SS

V

171

SS

V

172

SS

V

175

SS

V

176

SS

V

180

SS

V

181

SS

V

184

SS

V

185

SS

V

188

SS

V

189

SS

V

192

SS

V

193

SS

V

196

SS

V

197

SS

V

201

SS

V

202

SS

V

205

SS

V

206

SS

V

209

SS

V

210

SS

V

213

SS

V

214

SS

V

217

SS

V

218

SS

V

222

SS

V

223

SS

V

226

SS

V

227

VSS

230

VSS

231

VSS

234

VSS

235

VSS

238

VSS

239

VSS

243

VSS

244

VSS

247

V

SS

248

V

SS

251

V

SS

252

V

SS

261

ND

1U_0201_6.3V6M

1U_0201_6.3V6M

C

1

1

D29

2

2

C
D30

222333 999999WWWeeedddnnn eeesssdddaaayyy,,, MMMaaayyy 111555,,, 222000111999

+

2.5V

C
D31 1U_0201_6.3V6M

1

2

CRB use 1uF x1

o

o

o

fff

1

1

1

AAA

A

A

ddress : A2

1 1

+

3VS

10K_0402_5%

12

1

R

0_0402_5%

D247

@

2

12

12

R

0_0402_5%

RS@

D252

Layout Note:
Place near JDIMM2

2 2

+

1.2V

1U_0201_6.3V6M

C

1

D86

2

+

1.2V

10U_0402_6.3V6M

C

1

D82

2

3 3

+

1.2V

0.1U_0201_10V6K
C

2

D91

1

R

1

D244

0_0402_5%

R
D248

@

2

DR_B_SA2

D

DR_B_SA1

D

DR_B_SA0

D

12

R

0_0402_5%

RS@

R

0_0402_5%

D246

D249

@

N

ote:
Check voltage tolerance of
VREF_DQ at the DIMM socket

CRB use 0.1uF x12 (6 pop,6 unpop),180pF x1,100uF x2

1U_0201_6.3V6M

1U_0201_6.3V6M

1

2

10U_0402_6.3V6M

1

2

0.1U_0201_10V6K

2

1

1U_0201_6.3V6M

C

C

1

1

D78

D67

2

2

10U_0402_6.3V6M

10U_0402_6.3V6M

C

C

1

1

D96

D90

2

2

0.1U_0201_10V6K

0.1U_0201_10V6K

C

C

2

2

D94

D97

1

1

1U_0201_6.3V6M

1U_0201_6.3V6M

C

C

C

1

1

D93

C
D77

C
D66

D81

D71

2

2

10U_0402_6.3V6M

10U_0402_6.3V6M

1

2

10U_0402_6.3V6M

C
D68

C

C

1

1

D88

D99

2

2

180P_0402_50V8J

C

2

D85

1

D73

@EMC@

C
.1U_0402_1 6V7K

2

1

DR_B_RST#

D

B

DR_B_CLK0

D

DR_B_CLK07

D

DR_B_CLK0#7

D

DR_B_CLK17

D

DR_B_CLK1#7

D

DR_B_CKE07

D

DR_B_CKE17

D

DR_B_CS0#7

D

DR_B_CS1#7

D

DR_B_ODT07

D

DR_B_ODT17

D

DR_B_BG07

D

DR_B_BG17

D

DR_B_BA07

D

DR_B_BA17

D

DR_B_MA[13..0]7

D

DR_B_MA14_W E#7

D

DR_B_MA15_C AS#7

D

DR_B_MA16_R AS#7

D

DR_B_ACT#7

D

DR_B_PAR7

D

DR_B_ALERT#7

D

DR_B_EVENT#7

D

DR_B_RST#7

S

MB_0_SDA9 ,23

S

MB_0_SCL9,23

D

DR_B_DM[7..0]7

D

DR_B_CLK0#

D

DR_B_CLK1

D

DR_B_CLK1#

D

DR_B_CKE0

D

DR_B_CKE1

D

DR_B_CS0#

D

DR_B_CS1#

D

DR_B_ODT0

D

DR_B_ODT1

D

DR_B_BG0

D

DR_B_BG1

D

DR_B_BA0

D

DR_B_BA1

D

DR_B_MA0

D

DR_B_MA1

D

DR_B_MA2

D

DR_B_MA3

D

DR_B_MA4

D

DR_B_MA5

D

DR_B_MA6

D

DR_B_MA7

D

DR_B_MA8

D

DR_B_MA9

D

DR_B_MA10

D

DR_B_MA11

D

DR_B_MA12

D

DR_B_MA13

D

DR_B_MA14_W E#

D

DR_B_MA15_C AS#

D

DR_B_MA16_R AS#

D

DR_B_ACT#

D

DR_B_PAR

D

DR_B_ALERT#

D

DR_B_EVENT#

D

DR_B_RST#

D

MB_0_SDA

S

MB_0_SCL

S

DR_B_SA2

D

DR_B_SA1

D

DR_B_SA0

D

DR_B_DM0

D

DR_B_DM1

D

DR_B_DM2

D

DR_B_DM3

D

DR_B_DM4

D

DR_B_DM5

D

DR_B_DM6

D

DR_B_DM7

D

137
139
138
140

109
110

149
157
162
165

155
161

115
113
150
145

144
133
132
131
128
126
127
122
125
121
146
120
119
158
151
156
152

114

143
116
134
108

254
253

166
260
256

92

91
101
105

88

87
100
104

97

95

12

33

54

75
178
199
220
241

96

261
262

C

DIMM2A

J

STD

K0(T)

C

K0#(C)

C

K1(T)

C

K1#(C)

C

C

KE0

C

KE1

0#
1#
2#/C0
3#/C1

DT0
DT1

G0
G1
A0
A1

0
1
2
3
4
5
6
7
8
9
10_AP
11
12
13
14_WE#
15_CAS#
16_RAS#

CT#

ARITY
LERT#
VENT#
ESET#

DA
CL

A2
A1
A0

B0_NC
B1_NC
B2_NC
B3_NC
B4_NC
B5_NC
B6_NC
B7_NC
QS8(T)
QS8#(C)

M0#/DBI0#
M1#/DBI1#
M2#/DBI2#
M3#/DBI3#
M4#/DBI4#
M5#/DBI5#
M6#/DBI6#
M7#/DBI7#
M8#/DBI8#

ND1
ND2

D

D

QS0#(C)

D

D

QS1#(C)

D

D

QS2#(C)

D

D

QS3#(C)

D

D

QS4#(C)

D

D

QS5#(C)

D

D

QS6#(C)

D

D

QS7#(C)

QS0(T)

QS1(T)

QS2(T)

QS3(T)

QS4(T)

QS5(T)

QS6(T)

QS7(T)

S
S
S
S

O
O

B
B
B
B

A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A

A

P
A
E
R

S
S

S
S
S

C
C
C
C
C
C
C
C
D
D

D
D
D
D
D
D
D
D
D

G
G

LOTES_ADDR02 05-P001A

CONN@

D

S

2

-3A to 1 DIMMs/channel

D

Q0

D

Q1

D

Q2

D

Q3

D

Q4

D

Q5

D

Q6

D

Q7

D

Q8

D

Q9

D

Q10

D

Q11

D

Q12

D

Q13

D

Q14

D

Q15

D

Q16

D

Q17

D

Q18

D

Q19

D

Q20

D

Q21

D

Q22

D

Q23

D

Q24

D

Q25

D

Q26

D

Q27

D

Q28

D

Q29

D

Q30

D

Q31

D

Q32

D

Q33

D

Q34

D

Q35

D

Q36

D

Q37

D

Q38

D

Q39

D

Q40

D

Q41

D

Q42

D

Q43

D

Q44

D

Q45

D

Q46

D

Q47

D

Q48

D

Q49

D

Q50

D

Q51

D

Q52

D

Q53

D

Q54

D

Q55

D

Q56

D

Q57

D

Q58

D

Q59

D

Q60

D

Q61

D

Q62

D

Q63

DR_B_DQ1

D

7

DR_B_DQ2

D

20

DR_B_DQ3

D

21

DR_B_DQ4

D

4

DR_B_DQ5

D

3

DR_B_DQ6

D

16

DR_B_DQ7

D

17

DR_B_DQS0

D

13

DR_B_DQS0#

D

11

DR_B_DQ8

D

28

DR_B_DQ9

D

29

D

DR_B_DQ10

41

D

DR_B_DQ11

42

DR_B_DQ12

D

24

DR_B_DQ13

D

25

D

DR_B_DQ14

38

DR_B_DQ15

D

37

DR_B_DQS1

D

34

DR_B_DQS1#

D

32

D

DR_B_DQ16

50

D

DR_B_DQ17

49

D

DR_B_DQ18

62

DR_B_DQ19

D

63

D

DR_B_DQ20

46

D

DR_B_DQ21

45

D

DR_B_DQ22

58

D

DR_B_DQ23

59

DR_B_DQS2

D

55

DR_B_DQS2#

D

53

DR_B_DQ24

D

70

DR_B_DQ25

D

71

DR_B_DQ26

D

83

D

DR_B_DQ27

84

DR_B_DQ28

D

66

DR_B_DQ29

D

67

D

DR_B_DQ30

79

DR_B_DQ31

D

80

DR_B_DQS3

D

76

DR_B_DQS3#

D

74

DR_B_DQ32

D

174

DR_B_DQ33

D

173

DR_B_DQ34

D

187

D

DR_B_DQ35

186

DR_B_DQ36

D

170

D

DR_B_DQ37

169

DR_B_DQ38

D

183

DR_B_DQ39

D

182

DR_B_DQS4

D

179

DR_B_DQS4#

D

177

DR_B_DQ40

D

195

D

DR_B_DQ41

194

DR_B_DQ42

D

207

DR_B_DQ43

D

208

DR_B_DQ44

D

191

D

DR_B_DQ45

190

DR_B_DQ46

D

203

DR_B_DQ47

D

204

DR_B_DQS5

D

200

DR_B_DQS5#

D

198

DR_B_DQ48

D

216

D

DR_B_DQ49

215

DR_B_DQ50

D

228

DR_B_DQ51

D

229

D

DR_B_DQ52

211

DR_B_DQ53

D

212

DR_B_DQ54

D

224

DR_B_DQ55

D

225

DR_B_DQS6

D

221

DR_B_DQS6#

D

219

D

DR_B_DQ56

237

D

DR_B_DQ57

236

D

DR_B_DQ58

249

D

DR_B_DQ59

250

D

DR_B_DQ60

232

D

DR_B_DQ61

233

D

DR_B_DQ62

245

D

DR_B_DQ63

246

DR_B_DQS7

D

242

DR_B_DQS7#

D

240

DR_B_DQ0

D

8

D

DR_B_DQ[7..0] 7

D

DR_B_DQS0 7

D

DR_B_DQS0# 7

D

DR_B_DQ[15..8] 7

D

DR_B_DQS1 7

D

DR_B_DQS1# 7

D

DR_B_DQ[23..16 ] 7

D

DR_B_DQS2 7

D

DR_B_DQS2# 7

D

DR_B_DQ[31..24 ] 7

D

DR_B_DQS3 7

D

DR_B_DQS3# 7

D

DR_B_DQ[39..32 ] 7

D

DR_B_DQS4 7

D

DR_B_DQS4# 7

D

DR_B_DQ[47..40 ] 7

D

DR_B_DQS5 7

D

DR_B_DQS5# 7

D

DR_B_DQ[55..48 ] 7

D

DR_B_DQS6 7

D

DR_B_DQS6# 7

D

DR_B_DQ[63..56 ] 7

D

DR_B_DQS7 7

D

DR_B_DQS7# 7

Follow CRB design

+

1.2V

D243

R

1K_0402_1%

R

D251

1K_0402_1%

1 2

C
D84 4.7U_0402_6.3V6M

2

1

+

VREFB_CA

1

5mil

C

C

C
D87 1000P_0402_50V7K

D80 0.1U_0201_10V6K

D76 0.1U_0201_10V6K

1

2

2

1

2

1

1

2

Place near to SO-DIMM connector.

+

1.2V

J

111
112
117
118
123
124
129
130

+

3VS

135
136

255

164

1
2
5
6

9
10
14

15
18
19
22
23
26
27
30
31
35
36
39
40
43
44
47
48
51
52
56
57
60
61
64
65
68
69
72
73
77
78
81
82
85
86
89
90
93
94
98

262

LOTES_ADDR02 05-P001A

CONN@

Layout Note:
Place near JDIMM2.258

E

tand Type-4H

+

DIMM2B

V

DD1

V

DD2

V

DD3

V

DD4

V

DD5

V

DD6

V

DD7

V

DD8

V

DD9

V

DD10

V

DDSPD

V

REFCA

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

ND

G

STD

DD11

V

DD12

V

DD13

V

DD14

V

DD15

V

DD16

V

DD17

V

DD18

V

DD19

V

V
V

1.2V

141
142
147
148
153
154
159
160

+

163

258

TT

V

257

PP1

259

PP2

99

SS

V

102

SS

V

103

SS

V

106

SS

V

107

SS

V

167

SS

V

168

SS

V

171

SS

V

172

SS

V

175

SS

V

176

SS

V

180

SS

V

181

SS

V

184

SS

V

185

SS

V

188

SS

V

189

SS

V

192

SS

V

193

SS

V

196

SS

V

197

SS

V

201

SS

V

202

SS

V

205

SS

V

206

SS

V

209

SS

V

210

SS

V

213

SS

V

214

SS

V

217

SS

V

218

SS

V

222

SS

V

223

SS

V

226

SS

V

227

SS

V

230

SS

V

231

SS

V

234

SS

V

235

SS

V

238

SS

V

239

SS

V

243

SS

V

244

SS

V

247

SS

V

248

SS

V

251

SS

V

252

SS

V

261

ND

G

0.6VS

CRB use 1uF x1

+

2.5V

C
D89 1U_0201_6.3V6M

1

2

CRB use 4.7uF x1,0.1uF x1

+

Layout Note:
Place near JDIMM2.257,259

CRB use 0.1uF x2,180pF x1

+

4 4

10U_0402_6.3V6M

C

1

D79

2

2.5V

1U_0201_6.3V6M

10U_0402_6.3V6M

C

C

1

1

D75

D83

2

2

A

Layout Note:
Place near JDIMM2.255

CRB use 1uF x1

+

3VS

1U_0201_6.3V6M

C

1

D95

2

1

2

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2

2

2

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered Date

eciphered Date

eciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

T

T

T

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

itle

itle

itle

C

C

C

ustom

ustom

ustom

0.6VS

1U_0201_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

C

C

C

1

1

D74

D70

DDR4_DIMMB

DDR4_DIMMB

DDR4_DIMMB

FH50P M/B LA-H901P

FH50P M/B LA-H901P

FH50P M/B LA-H901P

D92

2

2

E

1U_0201_6.3V6M

C

1

D72

2

1

1

1

A

A

A

o

o

o

f

24 99Wednesday, May 15, 201 9

f

24 99Wednesday, May 15, 201 9

f

24 99Wednesday, May 15, 201 9

5

D D

C C

4

3

2

1

R

B B

A A

5

4

eserve Page

S

S

S

ecurity Classif ication

ecurity Classif ication

ecurity Classif ication

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

2

2

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

3

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered D ate

eciphered D ate

eciphered D ate

2

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

Reserve Page

Reserve Page

Reserve Page

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

o

o

o

f

25 99Wed nesday, May 15, 2019

f

25 99Wed nesday, May 15, 2019

f

25 99Wed nesday, May 15, 2019

1

1

1

1

A

A

A

5

D D

C C

4

3

2

1

R

B B

A A

5

4

eserve Page

S

S

S

ecurity Classif ication

ecurity Classif ication

ecurity Classif ication

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

2

2

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

3

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered D ate

eciphered D ate

eciphered D ate

2

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

Reserve Page

Reserve Page

Reserve Page

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

o

o

o

f

26 99Wed nesday, May 15, 2019

f

26 99Wed nesday, May 15, 2019

f

26 99Wed nesday, May 15, 2019

1

1

1

1

A

A

A

5

4

3

2

1

D D

EG_ATX_ GRX_P0

P

EG_ATX_ GRX_P06

P

EG_ATX_ GRX_N06

P

EG_ATX_ GRX_P16

P

EG_ATX_ GRX_N16

P

EG_ATX_ GRX_P26

P

EG_ATX_ GRX_N26

P

EG_ATX_ GRX_P36

P

EG_ATX_ GRX_N36

P

EG_ATX_ GRX_P46

P

EG_ATX_ GRX_N46

P

EG_ATX_ GRX_P56

P

EG_ATX_ GRX_N56

P

EG_ATX_ GRX_P66

P

EG_ATX_ GRX_N66

P

EG_ATX_ GRX_P76

P

EG_ATX_ GRX_N76

C C

A

B B

PU_PCIE_R ST#9,51,52,68

P

E_GPIO010

P

EG_ATX_ GRX_N0

P

EG_ATX_ GRX_P1

P

EG_ATX_ GRX_N1

P

EG_ATX_ GRX_P2

P

EG_ATX_ GRX_N2

P

EG_ATX_ GRX_P3

P

EG_ATX_ GRX_N3

P

EG_ATX_ GRX_P4

P

EG_ATX_ GRX_N4

P

EG_ATX_ GRX_P5

P

EG_ATX_ GRX_N5

P

EG_ATX_ GRX_P6

P

EG_ATX_ GRX_N6

P

EG_ATX_ GRX_P7

P

EG_ATX_ GRX_N7

P

12

V370

R

2.2K_040 2_5%

DIS@

+

3VSDGPU

5

1

I

N1

2

I

N2

3

1 2

V312 0.22U_0 402_16V7KDIS@

C

1 2

C

V306 0.22U_0 402_16V7KDIS@

1 2

V308 0.22U_0 402_16V7KDIS@

C

2

1

C

V305 0.22U_0 402_16V7KDIS@

1 2

V307 0.22U_0 402_16V7KDIS@

C

1 2

C

V309 0.22U_0 402_16V7KDIS@

1 2

C

V313 0.22U_0 402_16V7KDIS@

2

1

V304 0.22U_0 402_16V7KDIS@

C

2

1

V2710 0.22U_0402 _16V7KDIS@

C

2

1

C

V2707 0.22U_0402 _16V7KDIS@

1 2

V2711 0.22U_0402 _16V7KDIS@

C

1 2

C

V2709 0.22U_0402 _16V7KDIS@

1 2

C

V2717 0.22U_0402 _16V7KDIS@

1 2

V2714 0.22U_0402 _16V7KDIS@

C

1 2

C

V2704 0.22U_0402 _16V7KDIS@

1 2

V2706 0.22U_0402 _16V7KDIS@

C

U

V2

SA00000OH00

MC74VHC 1G08DFT2G_SC 70-5

D

IS@

P

O

G

4

P

12

V4

R
100K_04 02_5%

IS@

D

LT_RST_ VGA#

C

LK_PEG_ P410

C

LK_PEG_ N410

EG_ATX_ C_GRX_P0

P

EG_ATX_ C_GRX_N0

P

P

EG_ATX_ C_GRX_P1

P

EG_ATX_ C_GRX_N1

P

EG_ATX_ C_GRX_P2

P

EG_ATX_ C_GRX_N2

P

EG_ATX_ C_GRX_P3

P

EG_ATX_ C_GRX_N3

P

EG_ATX_ C_GRX_P4

P

EG_ATX_ C_GRX_N4

P

EG_ATX_ C_GRX_P5

P

EG_ATX_ C_GRX_N5

P

EG_ATX_ C_GRX_P6

P

EG_ATX_ C_GRX_N6

P

EG_ATX_ C_GRX_P7

P

EG_ATX_ C_GRX_N7

LK_PEG_ P4

C

LK_PEG_ N4

C

V

DDCI_PG92

D

GPU_PW RGOOD1 0,92,94

V1B

U

@

ymbol2

AT41
AT40

AR41
AR40

AP41
AP40

AM41
AM40

AL41
AL40

AK41
AK40

AJ41
AJ40

AH41
AH40

AV33
AU33

s

CIE_RX0P

P

CIE_RX0N

P

CIE_RX1P

P

CIE_RX1N

P

CIE_RX2P

P

CIE_RX2N

P

CIE_RX3P

P

CIE_RX3N

P

CIE_RX4P

P

CIE_RX4N

P

CIE_RX5P

P

CIE_RX5N

P

CIE_RX6P

P

CIE_RX6N

P

CIE_RX7P

P

CIE_RX7N

P

CIE_REFCLKP

P

CIE_REFCLKN

P

REV 0.91

2160896 088A1R16M_FC BGA769P-NH

+

3VSDGPU

5

1

P

N1

I

2

N2

I

G

3

P

CIE_TX0N

P

CIE_TX1P

P

CIE_TX1N

P

CIE_TX2P

P

CIE_TX2N

P

CIE_TX3P

P

CIE_TX3N

P

CIE_TX4P

P

CIE_TX4N

P

CIE_TX5P

P

CIE_TX5N

P

CIE_TX6P

P

CIE_TX6N

P

CIE_TX7P

P

CIE_TX7N

P

ERSTB

P

X_EN

P

CIE_ZVSS

P

V1005

U
MC74VHC 1G08DFT2G_SC 70-5

IS@

D

4

O

EG_ARX_ C_GTX_N0

P

AU35

EG_ARX_ C_GTX_P1

P

AU38

EG_ARX_ C_GTX_N1

P

AU39

P

EG_ARX_ C_GTX_P2

AR37

P

EG_ARX_ C_GTX_N2

AR38

P

EG_ARX_ C_GTX_P3

AN37

P

EG_ARX_ C_GTX_N3

AN38

P

EG_ARX_ C_GTX_P4

AL37

P

EG_ARX_ C_GTX_N4

AL38

P

EG_ARX_ C_GTX_P5

AJ37

P

EG_ARX_ C_GTX_N5

AJ38

P

EG_ARX_ C_GTX_P6

AG37

P

EG_ARX_ C_GTX_N6

AG38

P

EG_ARX_ C_GTX_P7

AE37

P

EG_ARX_ C_GTX_N7

AE38

AV41

AC41

F

AU41

1 2

SA00000OH00

D

GPU_PW RGOOD_R

12

R

V1659
100K_04 02_5%

D

IS@

P

P

EG_ARX_ C_GTX_P0

P

AV35

CIE_TX0P

2

1

V1 0.22U_04 02_16V7KDIS@

C

2

1

C

V2 0.22U_04 02_16V7KDIS@

1 2

C

V3 0.22U_04 02_16V7KDIS@

1 2

C

V4 0.22U_04 02_16V7KDIS@

2

1

V5 0.22U_04 02_16V7KDIS@

C

2

1

V6 0.22U_04 02_16V7KDIS@

C

1 2

C

V7 0.22U_04 02_16V7KDIS@

1 2

C

V8 0.22U_04 02_16V7KDIS@

1 2

V2715 0.22U_0402 _16V7KDIS@

C

1 2

C

V2708 0.22U_0402 _16V7KDIS@

1 2

C

V2713 0.22U_0402 _16V7KDIS@

1 2

C

V2703 0.22U_0402 _16V7KDIS@

2

1

V2705 0.22U_0402 _16V7KDIS@

C

1 2

V2712 0.22U_0402 _16V7KDIS@

C

2

1

C

V2716 0.22U_0402 _16V7KDIS@

1 2

V2702 0.22U_0402 _16V7KDIS@

C

LT_RST_ VGA#

X_EN

1

TP@

T

R

D

V371

200_040 2_1%

IS@

218

P

LT_RST_ VGA#

D

GPU_PW RGOOD_R

or BACO mode(AMD PowerXpress) use, NC if not use

EG_ARX_ GTX_P0

P

EG_ARX_ GTX_N0

P

EG_ARX_ GTX_P1

P

EG_ARX_ GTX_N1

P

EG_ARX_ GTX_P2

P

EG_ARX_ GTX_N2

P

EG_ARX_ GTX_P3

P

EG_ARX_ GTX_N3

P

EG_ARX_ GTX_P4

P

EG_ARX_ GTX_N4

P

EG_ARX_ GTX_P5

P

EG_ARX_ GTX_N5

P

EG_ARX_ GTX_P6

P

EG_ARX_ GTX_N6

P

EG_ARX_ GTX_P7

P

EG_ARX_ GTX_N7

P

+

3VSDGPU

U

V3

MC74VHC 1G08DFT2G_SC 70-5

5

D

IS@

1

P

I

N1

4

O

2

I

N2

G

3

SA00000OH00

12

P

EG_ARX_ GTX_P0 6

P

EG_ARX_ GTX_N0 6

P

EG_ARX_ GTX_P1 6

P

EG_ARX_ GTX_N1 6

P

EG_ARX_ GTX_P2 6

P

EG_ARX_ GTX_N2 6

P

EG_ARX_ GTX_P3 6

P

EG_ARX_ GTX_N3 6

P

EG_ARX_ GTX_P4 6

P

EG_ARX_ GTX_N4 6

P

EG_ARX_ GTX_P5 6

P

EG_ARX_ GTX_N5 6

P

EG_ARX_ GTX_P6 6

P

EG_ARX_ GTX_N6 6

P

EG_ARX_ GTX_P7 6

P

EG_ARX_ GTX_N7 6

R

V374
100K_04 02_5%

D

IS@

D

GPU_PW ROK 92

P

D

GPU_PW RGOOD

V

DDCI_PG

A A

S

S

S

T

T

T
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1 2

V1660 0_0402_5 %@

R

1 2

R

V1661 0_0402_5 %@

ecurity Classif ication

ecurity Classif ication

ecurity Classif ication

I

I

I

ssued Date

ssued Date

ssued Date

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

D

GPU_PW RGOOD_R

C

C

C

ompal Secret Data

ompal Secret Data

2

2

2

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

3

ompal Secret Data

D

D

D

eciphered D ate

eciphered D ate

eciphered D ate

LT_RST_ VGA#

2

1 2

V1654 0_0402_5 %@

R

T

T

T

itle

itle

itle

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

C

C

C

ustom

ustom

ustom

Date: Sheet

Date: Sheet

Date: Sheet

D

GPU_PW ROK

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

ompal Electronics, Inc.

R

R

R

18M-G1-90_(1/9)_PCIE

18M-G1-90_(1/9)_PCIE

18M-G1-90_(1/9)_PCIE

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

1

1

1

A

A

A

o

o

o

f

27 99Wed nesday, May 15, 2019

f

27 99Wed nesday, May 15, 2019

f

27 99Wed nesday, May 15, 2019

1

5

+

3VSDGPU

12

S

2

G

6 1

D

V1A

Q

DIS@

Vgs=1.0-2.5V

0

0

12

V429

V426

RX560@

R

R

5.1K_0201_1%

12

@

V427

V428

R

R

5.1K_0201_1%

R
47K_0402_5%

DIS@

S

V314
C

1U_0201_6.3V6M

Voltage
Selected (V)

1.1

1.01

0.9

0.81

12

V432

RX560@

R

5.1K_0201_1%

12

@

V431
R

5.1K_0201_1%

5

G

E

C_SMB_DA28,58,66

D D

E

C_SMB_CK28,58,66

+

1.8VSDGPU

V87

V84

@

R

R

DIS@

10K_0402_5%

10K_0402_5%

1 2

1 2

2

V88

V89

C C

@

R

R

DIS@

10K_0402_5%

10K_0402_5%

1 2

1

2N7002KDW_SOT363-6

B00000EO00

S

@

V410
R

10K_0402_5%

1 2

@

V411
R

10K_0402_5%

1 2

3 4

D

V1B

Q

DIS@

2N7002KDW_SOT363-6

B00000EO00

S

G

PU_SVC

G

PU_SVD

G

PU_SVT

Boot-VID Code

SVD

SVC

0
0
1
1

R

X560 Strap

+

3VSDGPU

B B

12

@

V416
R

5.1K_0201_1%

12

V417

RX560@

R

5.1K_0201_1%

V414
R

5.1K_0201_1%

V415
R

5.1K_0201_1%

12

V418

RX560@

R

5.1K_0201_1%

12

@

V419
R

5.1K_0201_1%

G

PIO_2 can't use on R535

12

12

@

V422

V420

RX560@

R

R

5.1K_0201_1%

5.1K_0201_1%

12

12

@

V423

V421

RX560@

R

R

5.1K_0201_1%

5.1K_0201_1%

12

12

@

@

V424
R

5.1K_0201_1%

12

12

@

V425

RX560@

R

5.1K_0201_1%

V507

+

1.8VSDGPU

V412
R

1K_0402_5%

1

@

2

V1653
R

1K_0402_5%

12

12

@

@

V434
R

5.1K_0201_1%

5.1K_0201_1%

12

12

V433

RX560@

RX560@

R

5.1K_0201_1%

5.1K_0201_1%

SCL use 47k, CRB use 4.7k
AMD Confirm List_1027 use PU-47k

12

V508

R
47K_0402_5%

DIS@

V

GA_SMB_DA3

V

GA_SMB_CK3

SCL PU-1k

12

12

RX560@

12

@

V436
R

V435
R

V413

DIS@

R

1K_0402_5%

T

1

@

56109_Compatible List:

V315

2

R535 don't care, and Lexa PU.

C

1U_0201_6.3V6M

12

12

@

@

V438
R

5.1K_0201_1%

5.1K_0201_1%

1

12

@

@

V437
R

2

5.1K_0201_1%

5.1K_0201_1%

CRB PU-10k/PD-1uF
56109_Compatible List:
R535 PD, and Lexa PU.

T

EST_PG

EST_PG_BACO

12

@

V440
R

5.1K_0201_1%

12

V439

RX560@

R

5.1K_0201_1%

G
G

G
G
G

G
G
G
H
V
G
G
G

PIO_0
PIO_2

PIO_11
PIO_12
PIO_13

PIO_15
PIO_20
PIO_29
SYNC
SYNC
PIO_8
PIO_9
PIO_22

4

G

PU_SVC

G

G
G
G

TX_HALF_SWING[0:disable,1:enable]
BIF_GEN3_EN_A[0:disable,1:enable]

ROM_CONFIG_[0]/MemoryAperture
ROM_CONFIG_[1]/MemoryAperture
ROM_CONFIG_[2]/MemoryAperture

Reserved [PD for default]
TX_DEEMPH_EN[0:disable,1:enable]
BIF_VGA_DIS[0:VGA,1:Headless]
Special Usage[1] GPUdefault
Special Usage[0] GPUdefault
BIF_CLK_PM_EN[0:disable,1:enable]
Reserved [PD for production]
BIOS_ROM_EN[0:disable,1:enable]

PU_SVD

PU_SVC92
PU_SVD92

G

PU_SVT

PU_SVT92

1U_0201_6.3V6M

R

V155 0_0402_5%DIS@

V156 0_0402_5%DIS@

R

R

V157 0_0402_5%DIS@

+

DIS@

C

V26

1 2

1

1

3VSDGPU

1

2

V

GA_SMB_CK3

V

GA_SMB_DA3

2

2

T

EST_PG

T

EST_PG_BACO

3

V1E

U

1

0mA

@

AM31

AW40
AW41

AC35
AC34

AU17
AV17
AR17

AN34
AP31

AY13
BA13

K41
R34

s

DD_33

V

PIO_5_REG_HOT_AC_BATT

G

PIO_16_8P_DETECT

G

PIO_17_THERMAL_INT

G

CL

S

DA

S

MBCLK

S

MBDAT

S

PIO_SVC

G

PIO_SVD

G

PIO_SVT

G

DCVGACLK

D

DCVGADATA

D

EST_PG

T

EST_PG_BACO

T

SVD#K41

R

SVD#R34

R

REV 0.91

2160896088A1R16M_FCBGA769P-NH

ymbol5

PIO_6_TACH

G

PIO_8_ROMSO

G

PIO_9_ROMSI

G

PIO_10_ROMSCK

G

PIO_14_HPD2

G

PIO_18_HPD3

G

PIO_19_CTF

G

PIO_22_ROMCSB

G

ENERICA

G

ENERICB

G

ENERICC

G

ENERICD

G

ENERICE_HPD4

G

ENERICF_HPD5

G

ENERICG

G

C

L_ENABLE

B

L_PWM_DIM

B

WAPLOCKA

S

WAPLOCKB

S

ENLK_CLK

G

ENLK_VSYNC

G

PIO_0

G

PIO_1

G

PIO_2

G

PIO_11

G

PIO_12

G

PIO_13

G

PIO_15

G

PIO_20

G

PIO_21

G

PIO_29

G

PIO_30

G

H

LKREQB

AKEB

W

IGON

D

SYNC

H

SYNC

V

G

PIO_0

W40
AA40

G

PIO_2

AA35

V

GA_AC_BATT

AA34

G

PIO_6_TACH#

U35

G

PIO_8

AP25

G

PIO_9

AM25

G

PIO_10

AM27

G

PIO_11

W41

G

PIO_12

Y40

G

PIO_13

Y41
AU21

G

PIO_15

AA41
U34
R37
AV25

G

PIO_19_CTF

R38

G

PIO_20

AB40

G

PIO_21_PCC#

AB41

G

PIO_22

AP27

G

PIO_29

W37
W38

P

LL_ANALOG_IN

BA38
AV29
AU31
AV31
AU25
AV23
AM29

AV21

PD1

C

LKREQ_PEG#4_R

AV40
AU40

W

AKEB

AC40

AC37
AC38

W34

H

SYNC

W35

V

SYNC

AG34
AE34
AR29
AP29

1 2

R

D

V409 5.1K_0402_1%

IS@

1 2

V1652 5.1K _0402_1%

IS@

R

D

1 2

V1644 33_04 02_5%@

R

1 2

R

V1645 33_04 02_5%@

1 2

V1646 33_04 02_5%@

R

1

TP@

237

T

1

TP@

T

239

1 2

R

D

V91 5.1K_040 2_1%

IS@

1 2

R

V1647 33_04 02_5%@

1

TP@

T

231

1

TP@

241

T

1

TP@

T

240

1

TP@

T

234

V153

R
0_0402_5%

R

V368

10K_0402_5%

2

+

3VSDGPU

+

3VSDGPU

12

@

@

C

LKREQ_PEG#4 10

1

2

Function Support Pin

V

GA_AC_BATT

G

PIO_6_TACH#

G

PIO_21_PCC#

G

PIO_19_CTF

AC/DC Mode
H:AC L:DC

Thermal VR_HOT#
(Fan tachometer)

Peak Current Control

+

3VSDGPU+1.8VSDGPU

R

V502

10K_0201_5%@

1 2

DIS@

V151

R
10K_0201_5%

1 2

R

V1650

0_0402_5%

RX560@

V1651

R
0_0402_5%

@

1 2

GPIO5

GPIO6

GPIO21

RB751V-40_SOD323-2

D

RB751V-40_SOD323-2

D
RB751V-40_SOD323-2

12

12

R

V152

10K_0201_5%@

SCL can leave ncVDD_33

D

V1

V2

V4

R

18M-M2-60

Yes

No

No

DIS@

DIS@

DIS@

1

R17M-G1-50/70
R17M-P1-50/70
R18M-G1-90

Yes

Yes

Yes

12

12

12

W

AKEB

+

3VSDGPU

12

V162

R

4.7K_0402_5%

@

12

R

V430

4.7K_0402_5%

@

G

PU_ACIN 58

G

PU_PROCHOT# 92

A

PU_PROCHOT#_D 84

G

PU_THERMAL# 58

G

PU_PCC# 58

A A

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

2

2

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

R

R

R

18M-G1-90_(2/9)_MSIC-1

18M-G1-90_(2/9)_MSIC-1

18M-G1-90_(2/9)_MSIC-1

ustom

ustom

ustom

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

1

o

o

o

f

28 99Wednesday, May 15, 2019

f

28 99Wednesday, May 15, 2019

f

28 99Wednesday, May 15, 2019

1

1

1

A

A

A

5

+

1.8VSDGPU

V468

DIS@

R

10K_0201_5%

1 2

D D

U

V1F

@

s

ymbol6

X

P

REV 0.91

LLCHARZ_L

P

LLCHARZ_H

A

NALOGIO

C C

2160896088 A1R16M_FCBGA769P-NH

V467
R

X

TALIN

TALOUT

10K_0201_5%

2

DIS@

1

4

V101 33_02 01_5%

R

R

V100 33_02 01_5%

R

V469

BA39

AY39

AV15
AU15

AY38

1 2

DIS@

1 2

DIS@

1

DIS@

10K_0402_5%

TALIN

X

1

TP@

1

TP@

12

V83

R

16.2K_0402_1 %@

DNI

AA38
AA37

2

B2

229

T

T

230

U

V1A

@

s

ymbol1

J

TAG_TDO
J

TAG_TDI

J

TAG_TMS

J

TAG_TCK

T

J

TAG_TRSTB

EV 0.91

ESTEN

AF41
AD40
AD41
AE41

AE40
AF40

X

B

P_0

B

P_1

T

EST6

R

2160896088 A1R16M_FCBGA769P-NH

TAG_TDO_GPU

J

TAG_TDI_GPU

J

TAG_TMS_GPU

J

TAG_TCK_GPU

J

TAG_TESTEN_GPU

J

TAG_TRSTB_GPU

J

TALIN

15P_0402_50 V8J

R

V506

0_0402_5%

2

R

X560@

3

TAG_TDI_GPU

J

TAG_TDO_GPU

J

TAG_TMS_GPU

J

TAG_TCK_GPU

J

TAG_TRSTB_GPU

J

TAG_TESTEN_GPU

J

DIS@

C

V450

1

R

V1655 10K_0201_5%@

R

V1656 10K_0201_5%@

V1657 10K_0201_5%@

R

V1658 10K_0201_5%@

R

R
R

TALIN_R

X

2

7MHZ_10PF_XRCGB27 M000F2P18R0

12

TALOUT_R

X

TALIN_100M

X

12
12

12
12

V369 10K_0201_5%DIS@
V1630 10K_0201_5%@

3

12
12

R
R

Y

12

V470 5.1K_0201_1 %@

2

1

V471 1K_0201_5 %DIS@

X

D

V1

IS@

S

J10000UI00

3

1

N

N

C

C

2

4

X560@

R

UV4

3

OUT

X

4

SCLK1/REFCLK/FSEL/SSONb/OE

S

I51214-A1FAGMR_TDFN6_ 1P2X1P4

S

A0000A4K00

S

S IC SI51214-A1FAGMR TDFN 6P CLK GEN

TALOUT_R

1

+

3VSDGPU

+

3VSDGPU

+

3VSDGPU

ESR:40ohm (Max)

12

DIS@

V451

C
15P_0402_50 V8J

IN/CLKIN

X

SCLK2/OE/SSONb/PD

S

2

+

1.8VSDGPU

I_SS_SEL

S

2

1

DD

V

5

6

SS

V

1 2

R

D

V154 5.1K_0402_1 %

IS@

1 2

R

@

V505 5.1K_0402_1 %

TALIN_R

X

1.8VSDGPU_VDD

+

I_SS_SEL

S

C

0.1U_0201_10V6K
V2723

1

2

@

+

V7

X560@

L

R

BLM15BD121SN 1D_0402

1 2

C

10U_0402_6.3V6M

V449

1

2

RX560@

1.8VSDGPU

1

+

B B

V1K

U

@

ymbol11

s

BGDATA_0

D

BGDATA_1

D

BGDATA_2

D

BGDATA_3

D

BGDATA_4

D

BGDATA_5

D

BGDATA_6

D

BGDATA_7

D

BGDATA_8

D

BGDATA_9

D

BGDATA_10

D

BGDATA_11

D

BGDATA_12

D

BGDATA_13

D

BGDATA_14

D

BGDATA_15

D

REV 0.91

2160896088 A1R16M_FCBGA769P-NH

A A

BGDATA_0

D

L40

BGDATA_1

D

L41

BGDATA_2

D

M40

BGDATA_3

D

M41

BGDATA_4

D

N40

BGDATA_5

D

N41

BGDATA_6

D

P40

BGDATA_7

D

P41

BGDATA_8

D

R40
R41
T40
T41
U40
U41
V40
V41

5

BGDATA_9

D

BGDATA_10

D

BGDATA_11

D

BGDATA_12

D

BGDATA_13

D

BGDATA_14

D

BGDATA_15

D

1

TP@

T

221

1

TP@

T

222

1

TP@

223

T

1

TP@

224

T

1

TP@

225

T

1

TP@

T

226

1

TP@

T

227

1

TP@

228

T

1.8VSDGPU

1

V456

RX560@

R

5.1K_0201_1%

2

12

@

V455
R

5.1K_0201_1%

A

UD_PORT_CONN[2:0]

111: No usable endpoints

1

12

12

V457

V453

RX560@

RX560@

R

R

5.1K_0201_1%

5.1K_0201_1%

1

12

@

@

V454

V458
R

R

5.1K_0201_1%

5.1K_0201_1%

2

4

12

1

@

@

V459
R

5.1K_0201_1%

2

12

@

V460
R

5.1K_0201_1%

@

V461

V463
R

R

5.1K_0201_1%

5.1K_0201_1%

2

12

12

@

@

V464

V462
R

R

5.1K_0201_1%

5.1K_0201_1%

12

12

@

V465

V442

RX560@

R

R

5.1K_0201_1%

5.1K_0201_1%

BGDATA_0

D

AUD_PORT_CONN[0]

BGDATA_1

D

AUD_PORT_CONN[1]

BGDATA_2

D

AUD_PORT_CONN[2]

BGDATA_3

D

BOARD_CONFIG[0]

BGDATA_4

D

BOARD_CONFIG[1]

BGDATA_5

D

BOARD_CONFIG[2]

BGDATA_6

D

SMBUS_ADDR[0]

BGDATA_7

D

SMBUS_ADDR[1]

12

12

@

V466

V441

RX560@

R

R

5.1K_0201_1%

5.1K_0201_1%

*

110: One usable endpoint
101: Two usable endpoints
100: Three usable endpoints
011: Four usable endpoints
010: Five usable endpoints
001: Six usable endpoints
000: All endpoints are usable

B

OARD_CONFIG[2:0]

000:SAM 256Mx32 (8Gb)
001:Hynix 256Mx32 (8Gb)
010:
011:
100:
101:
110:
111:

(BOM at Page33)

D

BGDATA_[7:6]

00: 0×40
01: 0×41

*

10: 0×42
11: 0×43

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

2

2

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered Date

eciphered Date

eciphered Date

2

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

ustom

ustom

ustom

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

R

R

R

18M-G1-90_(3/9)_MSIC-2

18M-G1-90_(3/9)_MSIC-2

18M-G1-90_(3/9)_MSIC-2

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

1

o

o

o

f

29 99Wednesday, May 15, 2019

f

29 99Wednesday, May 15, 2019

f

29 99Wednesday, May 15, 2019

1

1

1

A

A

A

5

U

V1C

M

A0_D[0..31]35

D D

M

A0_A[0..8]35

C C

M

A0_WCK0135

M

A0_WCK01#35

M

A0_WCK2335

M

A0_WCK23#35

M

A0_EDC03 5

M

A0_EDC13 5

M

A0_EDC23 5

M

A0_EDC33 5

M

A0_DBI#035

M

A0_DBI#135

M

A0_DBI#235

M

A0_DBI#335

M

A0_ADBI35

M

A0_CS#35

A0_D0

M

A0_D1

M

A0_D2

M

A0_D3

M

A0_D4

M

A0_D5

M

A0_D6

M

A0_D7

M

A0_D8

M

A0_D9

M

A0_D10

M

A0_D11

M

A0_D12

M

A0_D13

M

A0_D14

M

A0_D15

M

A0_D16

M

A0_D17

M

A0_D18

M

A0_D19

M

A0_D20

M

A0_D21

M

A0_D22

M

A0_D23

M

A0_D24

M

A0_D25

M

A0_D26

M

A0_D27

M

A0_D28

M

A0_D29

M

A0_D30

M

A0_D31

M

A0_A0

M

A0_A1

M

A0_A2

M

A0_A3

M

A0_A4

M

A0_A5

M

A0_A6

M

A0_A7

M

A0_A8

M

A0_WCK01

M

A0_WCK01#

M

A0_WCK23

M

A0_WCK23#

M

A0_EDC0

M

A0_EDC1

M

A0_EDC2

M

A0_EDC3

M

M

A0_DBI#0

A0_DBI#1

M

A0_DBI#2

M

A0_DBI#3

M

M

A0_ADBI

M

A0_CS#

@

L34

D

QA0_0

L37

D

QA0_1

L38

D

QA0_2

J35

D

QA0_3

G37

D

QA0_4

E38

D

QA0_5

E35

D

QA0_6

D35

D

QA0_7

H41

D

QA0_8

H40

D

QA0_9

G41

D

QA0_10

G40

D

QA0_11

E40

D

QA0_12

D41

D

QA0_13

D40

D

QA0_14

C41

D

QA0_15

C40

D

QA0_16

B39

D

QA0_17

A39

D

QA0_18

B38

D

QA0_19

B36

D

QA0_20

A36

D

QA0_21

B35

D

QA0_22

A35

D

QA0_23

B33

D

QA0_24

B32

D

QA0_25

A32

D

QA0_26

B31

D

QA0_27

A30

D

QA0_28

B29

D

QA0_29

B28

D

QA0_30

A28

D

QA0_31

G25

M

AA0_0

H25

M

AA0_1

E27

M

AA0_2

D27

M

AA0_3

D29

M

AA0_4

H27

M

AA0_5

H23

M

AA0_6

E23

M

AA0_7

D25

M

AA0_8

H29

M

AA0_9

D33

W

CKA0_0

E33

W

CKA0B_0

A34

W

CKA0_1

B34

W

CKA0B_1

G38

E

DCA0_0

F41

E

DCA0_1

B37

E

DCA0_2

A31

E

DCA0_3

J38

D

DBIA0_0

F40

D

DBIA0_1

A38

D

DBIA0_2

B30

D

DBIA0_3

H21

A

DBIA0

H31

C

SA0B_0

s

ymbol3

D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D

W

W

CKA1B_0

W

W

CKA1B_1

E
E
E
E

D
D
D
D

C

D

QA1_0

D

QA1_1

D

QA1_2

D

QA1_3

D

QA1_4

D

QA1_5

D

QA1_6

D

QA1_7

D

QA1_8

D

QA1_9
QA1_10
QA1_11
QA1_12
QA1_13
QA1_14
QA1_15
QA1_16
QA1_17
QA1_18
QA1_19
QA1_20
QA1_21
QA1_22
QA1_23
QA1_24
QA1_25
QA1_26
QA1_27
QA1_28
QA1_29
QA1_30
QA1_31

M

AA1_0
M

AA1_1
M

AA1_2
M

AA1_3
M

AA1_4
M

AA1_5
M

AA1_6
M

AA1_7
M

AA1_8
M

AA1_9

CKA1_0

CKA1_1

DCA1_0
DCA1_1
DCA1_2
DCA1_3

DBIA1_0
DBIA1_1
DBIA1_2
DBIA1_3

A

DBIA1

SA1B_0

4

M

A1_D0

B27
A27
B26
A26
A24
B23
A23
B22
B20
A20
B19
A19
B17
A16
B16
A15
B15
A14
B14
B13
A11
B11
A10
B10
B8
A7
B7
A6
A4
B4
A3
B3

E15
H15
G13
D13
H11
H13
H17
G17
D15
E11

A22
B21

A8
B9

B24
A18
B12
B6

B25
B18
A12
B5

H19

E7

M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M

M
M
M
M
M
M
M
M
M

A1_WCK01

M

A1_WCK01#

M

A1_WCK23

M

A1_WCK23#

M

M

A1_EDC0

A1_EDC1

M

A1_EDC2

M

A1_EDC3

M

M

A1_DBI#0

A1_DBI#1

M

A1_DBI#2

M

A1_DBI#3

M

M

A1_ADBI

M

A1_CS#

A1_D1
A1_D2
A1_D3
A1_D4
A1_D5
A1_D6
A1_D7
A1_D8
A1_D9
A1_D10
A1_D11
A1_D12
A1_D13
A1_D14
A1_D15
A1_D16
A1_D17
A1_D18
A1_D19
A1_D20
A1_D21
A1_D22
A1_D23
A1_D24
A1_D25
A1_D26
A1_D27
A1_D28
A1_D29
A1_D30
A1_D31

A1_A0
A1_A1
A1_A2
A1_A3
A1_A4
A1_A5
A1_A6
A1_A7
A1_A8

A1_D[0..31] 35

M

A1_A[0..8] 35

M

A1_WCK01 35

M

A1_WCK01# 3 5

M

A1_WCK23 35

M

A1_WCK23# 3 5

M

A1_EDC0 35

M

A1_EDC1 35

M

A1_EDC2 35

M

A1_EDC3 35

M

A1_DBI#0 35

M

A1_DBI#1 35

M

A1_DBI#2 35

M

A1_DBI#3 35

M

A1_ADBI 35

M

A1_CS# 35

3

M

B0_D[0..31]36

M

B0_A[0..8]36

M

B0_WCK0136

M

B0_WCK01 #36

M

B0_WCK2336

M

B0_WCK23 #36

M

B0_EDC03 6

M

B0_EDC13 6

M

B0_EDC23 6

M

B0_EDC33 6

M

B0_DBI#036

M

B0_DBI#136

M

B0_DBI#236

M

B0_DBI#336

M

B0_ADBI36

M

B0_CS#36

B0_D0

M

B0_D1

M

B0_D2

M

B0_D3

M
M

B0_D4

M

B0_D5

M

B0_D6

M

B0_D7

M

B0_D8

M

B0_D9

M

B0_D10

M

B0_D11

M

B0_D12

M

B0_D13

M

B0_D14

M

B0_D15

M

B0_D16

M

B0_D17

M

B0_D18

M

B0_D19

M

B0_D20

M

B0_D21

M

B0_D22

M

B0_D23

M

B0_D24

M

B0_D25

M

B0_D26

M

B0_D27

M

B0_D28

M

B0_D29

M

B0_D30

M

B0_D31

B0_A0

M
M

B0_A1

M

B0_A2

M

B0_A3

M

B0_A4

M

B0_A5

M

B0_A6

M

B0_A7

M

B0_A8

B0_WCK01

M

B0_WCK01 #

M

B0_WCK23

M

B0_WCK23 #

M

B0_EDC0

M

B0_EDC1

M
M

B0_EDC2

M

B0_EDC3

B0_DBI#0

M
M

B0_DBI#1

M

B0_DBI#2

M

B0_DBI#3

B0_ADBI

M

B0_CS#

M

2

U

V1D

@

s

ymbol4

C2

QB0_0

D

C1

QB0_1

D

D2

QB0_2

D

D1

QB0_3

D

F1

QB0_4

D

G2

QB0_5

D

G1

QB0_6

D

H2

QB0_7

D

K2

QB0_8

D

K1

QB0_9

D

L2

QB0_10

D

L1

QB0_11

D

N2

QB0_12

D

P2

QB0_13

D

P1

QB0_14

D

R2

QB0_15

D

R1

QB0_16

D

T2

QB0_17

D

T1

QB0_18

D

U2

QB0_19

D

W1

QB0_20

D

W2

QB0_21

D

Y1

QB0_22

D

Y2

QB0_23

D

AB2

QB0_24

D

AC1

QB0_25

D

AC2

QB0_26

D

AD1

QB0_27

D

AF1

QB0_28

D

AF2

QB0_29

D

AG1

QB0_30

D

AG2

QB0_31

D

R5

AB0_0

M

R8

AB0_1

M

N7

AB0_2

M

N4

AB0_3

M

L8

AB0_4

M

N8

AB0_5

M

U8

AB0_6

M

U7

AB0_7

M

R4

AB0_8

M

L5

AB0_9

M

H1

CKB0_0

W

J2

CKB0B_0

W

AB1

CKB0_1

W

AA2

CKB0B_1

W

F2

E

DCB0_0

M2

DCB0_1

E

V1

DCB0_2

E

AD2

DCB0_3

E

E2

D

DBIB0_0

M1

D

DBIB0_1

V2

D

DBIB0_2

AE2

D

DBIB0_3

W8

A

DBIB0

G5

C

SB0B_0

D
D
D
D
D
D
D
D
D

D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D

M

M

M

M

M

M

M

M

M

M

W

CKB1B_0

W

W

CKB1B_1

W

E
E
E
E

D

DBIB1_0

D

DBIB1_1

D

DBIB1_2

D

DBIB1_3

C

QB1_0
QB1_1
QB1_2
QB1_3
QB1_4
QB1_5
QB1_6
QB1_7
QB1_8

QB1_9
QB1_10
QB1_11
QB1_12
QB1_13
QB1_14
QB1_15
QB1_16
QB1_17
QB1_18
QB1_19
QB1_20
QB1_21
QB1_22
QB1_23
QB1_24
QB1_25
QB1_26
QB1_27
QB1_28
QB1_29
QB1_30
QB1_31

AB1_0
AB1_1
AB1_2
AB1_3
AB1_4
AB1_5
AB1_6
AB1_7
AB1_8
AB1_9

CKB1_0

CKB1_1

DCB1_0
DCB1_1
DCB1_2
DCB1_3

A

DBIB1

SB1B_0

AH1
AH2
AJ2
AK1
AL2
AM1
AM2
AN2
AR1
AR2
AT1
AT2
AV2
AW1
AW2
AY3
BA3
AY4
BA4
AY5
BA7
AY7
AY8
BA8
AR4
AR5
AU4
AU7
AN8
AV11
AU11
AP11

AE7
AE8
AG5
AG4
AJ4
AG8
AC8
AC5
AE4
AJ8

AP1
AP2

AN4
AN5

AL1
AU2
BA6
AV7

AK2
AV1
AY6
AV9

AA8

AL8

B1_D0

M
M

B1_D1

M

B1_D2

M

B1_D3

M

B1_D4

M

B1_D5

M

B1_D6

M

B1_D7

M

B1_D8

M

B1_D9

M

B1_D10

M

B1_D11

M

B1_D12

M

B1_D13

M

B1_D14

M

B1_D15

M

B1_D16

M

B1_D17

M

B1_D18

M

B1_D19

M

B1_D20

M

B1_D21

M

B1_D22

M

B1_D23

M

B1_D24

M

B1_D25

M

B1_D26

M

B1_D27

M

B1_D28

M

B1_D29

M

B1_D30

M

B1_D31

B1_A0

M
M

B1_A1

M

B1_A2

M

B1_A3

M

B1_A4

M

B1_A5

M

B1_A6

M

B1_A7

M

B1_A8

B1_WCK01

M

B1_WCK01 #

M

B1_WCK23

M

B1_WCK23 #

M

B1_EDC0

M
M

B1_EDC1

M

B1_EDC2

M

B1_EDC3

B1_DBI#0

M
M

B1_DBI#1

M

B1_DBI#2

M

B1_DBI#3

B1_ADBI

M

B1_CS#

M

M
M

M
M

M
M
M
M

M
M
M
M

M

M

M

B1_D[0..31] 36

M

B1_A[0..8] 36

B1_WCK01 36
B1_WCK01 # 36

B1_WCK23 36
B1_WCK23 # 36

B1_EDC0 36
B1_EDC1 36
B1_EDC2 36
B1_EDC3 36

B1_DBI#0 36
B1_DBI#1 36
B1_DBI#2 36
B1_DBI#3 36

B1_ADBI 36

B1_CS# 36

1

B0_CAS#

M

M

A0_CAS#35

M

B B

M

A_VRAMRST#35

A A

A0_RAS#35

M

A0_WE#35

M

A0_CKE35

M

A0_CLK35

M

A0_CLK#35

R

49.9_0402_1%

1

120P_0402_5 0V8J

Place close to GPU (within 25mm)
and place componment within (5mm) close to each other

5

A0_CAS#

M

A0_RAS#

A0_WE#

M

M

A0_CKE

M

A0_CLK

M

A0_CLK#

1 2

V39 120_0402_1%

IS@

R

D

A_VRAMRST#_G

M

V36

IS@

D

V37

R
10_0402_1%

2

IS@

D

1

IS@

D

V96

C

2

12

IS@

D

V38

R

5.1K_0402_1%

D23

C

D21

R

G29

W

G21

C

E31

C

D31

C

K15

M

L32

D

2160896088 A1R16M_FCBGA769P-NH

ASA0B
ASA0B

EA0B

KEA0

LKA0
LKA0B

EM_CALRA

RAM_RSTA

A_VRAMRST#_G

M

C
R

C

M

VREFDA

REV 0.91

ASA1B

W

C

C
LKA1B

1

2

ASA1B

EA1B

KEA1

LKA1

D17
D19
D11

E19

D7
D9

K17

4

M

A_VREFD

M

A1_CAS#

M

A1_RAS#

A1_WE#

M

A1_CKE

M

M

A1_CLK

M

A1_CLK#

A_VREFD

M

40.2_0402_1%

100_0402_1 %

D

R

D

R

IS@

V32

IS@

V35

+

1.5VSDGPU

12

1

2

M

A1_CAS# 35

M

A1_RAS# 35

M

A1_WE# 35

M

A1_CKE 35

M

A1_CLK 35

M

A1_CLK# 35

DIS@

1

C

V486

1U_0201_6.3V6M

2

M

B0_CAS#36

M

B0_RAS#36

M

B0_WE#36

M

B0_CKE36

M

B0_CLK36

M

B0_CLK#36

M

B_VRAMRST#36

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

1 2

Place close to GPU (within 25mm)
and place componment within (5mm) close to each other

M

B0_RAS#

M

B0_WE#

M

B0_CKE

M

B0_CLK

M

B0_CLK#

M

2

1

V1633 120_0402_1%

X560@

R

R

B_VRAMRST#_G

M

V1641

R

49.9_0402_1%

X560@

R

120P_0402_5 0V8J

2

2

2

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

V1642

R
10_0402_1%

2

X560@

R

1

X560@

R

V2720

C

2

C

C

C

U4

W4

L4

W5

G4

J4

R10

AM11

1

12

X560@

R

V1643

R

5.1K_0402_1%

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered Date

eciphered Date

eciphered Date

C

ASB0B

ASB0B

R

EB0B

W

C

KEB0

C

LKB0

C

LKB0B

EM_CALRB

M

RAM_RSTB

D

2160896088 A1R16M_FCBGA769P-NH

M

B_VRAMRST#_G

2

M

REV 0.91

C

ASB1B

ASB1B

R

EB1B

W

C

KEB1

C

LKB1

C

LKB1B

VREFDB

AC4

AA4
AJ7

AA7

AL5
AL4

U10

B1_CAS#

M

B1_RAS#

M

B1_WE#

M

B1_CKE

M

B1_CLK

M

B1_CLK#

M

B_VREFD

M

40.2_0402_1%

M

B_VREFD

100_0402_1 %

T

T

T

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet

Date: Sheet

Date: Sheet

M

B1_CAS# 36

M

B1_RAS# 36

M

B1_WE# 36

M

B1_CKE 36

M

B1_CLK 36

M

B1_CLK# 36

+

1.5VSDGPU

12

IS@

D

V1635

R

1

IS@

D

V1634

R

itle

itle

itle

R

R

R

18M-G1-90_(4/9)_MEM

18M-G1-90_(4/9)_MEM

18M-G1-90_(4/9)_MEM

ustom

ustom

ustom

DIS@

1

V487

C
1U_0201_6.3V6M

2

2

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

ompal Electronics, Inc.

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

1

1

1

1

A

A

A

o

o

o

f

30 99Wednesday, May 15, 2019

f

30 99Wednesday, May 15, 2019

f

30 99Wednesday, May 15, 2019