Compal LA-H901P Schematics

A

1 1

B

C

D

E

Compal Confidential

2 2

FH50P MB Schematics Document

AMD Picasso Platform

AMD R18M-G1-90

3 3

LA-H901P REV:1A

2019-05-13

4 4

Security Classif ication

Security Classif ication

Security Classif ication

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Shared with Comp al

Shared with Comp al

A

B

Shared with Comp al

2018/ 12 /18 2019/12/ 18

2018/ 12 /18 2019/12/ 18

2018/ 12 /18 2019/12/ 18

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

COVER PAGE

COVER PAGE

COVER PAGE

FH50P M/B LA-H901P

FH50P M/B LA-H901P

FH50P M/B LA-H901P

E

1A

1A

1A

1 99Wednesd ay, May 15, 2019

1 99Wednesd ay, May 15, 2019

1 99Wednesd ay, May 15, 2019

A

Compal Confidential

Model Name : FH50P

B

C

D

E

(Channel A)

1 1

GPU

GDDR5 x4pcs

page 35~36

2 2

128-bits

S4 Package
RX560X : R18M-G1-90

page 27~33

Port 1

eDP Conn.

page 38 page 40

PEG x8

Display Port

Port 0

HDMI Conn.

AMD

Picasso

Memory BUS(DDR4)

1.2V DDRIV
2400Mhz

USB2.0

Port 3

USB3.0

260pin DDRIV SO-DIMM

Port 1

Type-C
Conn.

page 42~43

Type-A (CHG)
Conn.

Port 1

page 71

page 23

Port 2

Type-A
Conn.

Port 2Port 3

AMD FP5 APU

GA 1140-balls

PCIE

page 68~70

SSD1
NGFF Conn.

Port 4

LAN
RTL8118ASA

page 51

Port 5Port 0, 1, 2, 3

WLAN/BT
NGFF Conn.

page 52

SPI

Transformer

RJ45

page 51

3 3

page 10

BIOS (8M, 1.8V)

Fan Control

page 77

B

page 6~12

ENE
KBC9022

page 63

Int.KBD

LPC

page 58

PS2

I2C

Port 3

HD Audio

SATA III

PTP

page 63

HDD
Conn.

Port 0

page 67

Port 1

page 68

SSD2
NGFF Conn.

page 72

(Channel B)

260pin DDRIV SO-DIMM

Port 4

Type-A
(SUB)

page 38

Int. DMIC
on Camera

page 73

Port 0

Camera

Finger
Print

page 66

Audio
ALC255

page 38

Touch
Screen

Int. Speaker
Conn.

page 56

page 24

Port 5

page 38

page 56

USB2.0 Hub

page 75

WLAN/BT
NGFF Conn.

UAJ
on Sub/B

Port 1Port 2Port 3

page 52

page 73

RTC CKT.

Power On/Off CKT.

4 4

DC/DC Interface CKT.

Power Circuit DC/DC

VRAM Config Table

page 11

page 63

page 78

page 82~96

page 29

A

Sub Board

LS-H901 IO/B

LS-H502 Hall Sensor/B

page 73

page 66

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2018/ 12/18 2019/12/18

2018/ 12/18 2019/12/18

2018/ 12/18 2019/12/18

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

BLOCK DIAGRAMS

BLOCK DIAGRAMS

BLOCK DIAGRAMS

FH50P M/B LA-H901P

FH50P M/B LA-H901P

FH50P M/B LA-H901P

E

1A

1A

2 99Wednesday, May 15, 20 19

2 99Wednesday, May 15, 20 19

2 99Wednesday, May 15, 20 19

1A

A

B

C

D

E

Voltage Rails

+19V_VIN

+19VB

+APU_CORE OFFON

1 1

2 2

+1.8VALW

+1.8VS

+2.5V 2.5V power rail for APU and DDR ON ON

+1.2V

+0.6VS

+3VALW

+3VS

+5VALW ONONON

+5VS

+RTC_APU

+3VSDGPU

+1.8VSDGPU

+1.5VSDGPU VGA power

+VDDCI

+VGA_CORE

APU SMBus/I2C Address Table

Master

I2C Port 0
(+1.8VS)

I2C Port 1
(+1.8VS)

I2C Port 2
(+3VS)

SBMus Port 0

3 3

(+3VS)

I2C Port 3
(+3VALW)

SMBus Port 1
(+3VALW)

DescriptionPower Plane

Adapter power supply (19V)

AC or battery power rail for power circuit.

Core voltage for APU

Core voltage for APU ON+APU_CORE_SOC

1.8V always on power rail

1.8V switched power rail

0.6V switched power rail for DDR terminator

3.3V always on power rail

3.3V switched power rail

5V always on power rail

5V switched power rail

RTC power

VGA power

VGA power

VGA power

VGA power

Device

JDIMM1

JDIMM2

PTP
(Synaptics)

PTP
(ELAN)

Address[7:1]

0101 0000b
50h

0101 0001b
51h

0010 1100b
2Ch

0001 1111b
15h

Address [7:0]

Write

1010 0000b
A0h

1010 0010b
A2h

0101 1000b
58h

0011 1110b
3Eh

ON

ON ON

ON

ON

ON

ON

ON

ON

ON

1010 0001b
A1h

1010 0011b
A3h

0101 1001b
59h

0011 1111b
3Fh

ON ON

OFF OFF

OFF OFF

ONON1.2V power rail for APU and DDR

OFF OFF

ONON

OFF OFF

OFF OFF

OFF OFF

Read

BOARD ID Table

S5S3S0

ONONON

OFF

OFF

OFF

OFF

OFF

ON

ONONON

OFF+3V_LAN 3.3V LAN IC power ON ON

OFF+TP_VCC 3.3V Touch Pad power ON ON

OFFOFF

OFFOFFON

OFFOFF

OFFOFF

OFFON3.3V Finger Print power+FP_VCC ON

Board ID

0

PCB Revision

EVT

1 PVT

MP2

9 With RGB BL

BOM Structure Table

BTO ItemBOM Structure

@
EMC@/@EMC@
45@
CONN@
JP@
RS@
TP@
LDO@/SWR@
R5/R7APUQC@
HDT@
DIS@
RX560@
EVT@/PVT@/MP@

TMS@
KBLED@/LED14P@

X76_S4G@
X76_H4G@

Unpop

EMI/ESD Pop/Unpop

HDMI Royalty

Mechanical Connector

Jump

R-Short

Test Point

RTL8118ASA Switching-Mode only

APU PN Refer p.6

HDT Circuits

VGA Circuits

R18M-G1-90 GPU / Circuit

Test BOM for EVT/PVT/MP

Thermal Sensor

Keyboard back light / RGB back light

VRAM Config Refer p.33

VRAM Config Refer p.33

EC SMBus Address Table

SMBus Port 1
(+3VALW)

4 4

SMBus Port 2
(+3VS)

SMBus Port 3
(+3VALW)

Smart Battery

Charger IC
(BQ24735)

APU Temp.
(TSI)

GPU Temp.

Thermal Sensor
(Remote1 GPU)
(Remote2 APU)

LED driver 1100 0000b

A

0000 1011b
0Bh

0000 1001b
09h

0100 1100b
4Ch

0100 0001b
41h

0001 0110b
16h

0001 0010b
12h

1001 1000b
98h

1000 0010b
82h

1001 1010b
9Ah

C0h

0001 0111b
17h

0001 0011b
13h

1001 1001b
99h

1000 0011b
83h

1001 1011b
9Bh

1100 0001b
C1h

B

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

Board ID / SKU ID Table for AD channel

POWER SEQUENCE

G-A

G-B

G-C

G-D

+RTCBATT

EC_ON

+5VALW

3V_EN

+3VALW

0.9_1.8VALW_PWREN

+1.8VALW/+0.9VALW

SYSON

+1.2V/+2.5V

SUSP#

+5VS/+3VS/+1.8VS/+0.6VS

0.9VS_PWR_EN#

+0.9VS

VR_ON

+APU_CORE

+APU_CORE_SOC

VGA POWER SEQUENCE

PE_GPIO1/VGA_ON

+3VSDGPU

+1.8VSDGPU

VGA_ON_B

+VDDCI

+VGA_CORE

DGPU_PWRGOOD

+1.5VSDGPU

PE_GPIO0

Compal Secret Data

Compal Secret Data

2018/ 12/18 2019/12/18

2018/ 12/18 2019/12/18

2018/ 12/18 2019/12/18

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

NOTES LIST

NOTES LIST

NOTES LIST

FH50P M/B LA-H901P

FH50P M/B LA-H901P

FH50P M/B LA-H901P

E

3 99Wednesday, May 15, 20 19

3 99Wednesday, May 15, 20 19

3 99Wednesday, May 15, 20 19

1A

1A

1A

5

PJP101
AC-IN

+19V_VIN

+17.4V_BATT

D D

P

JP201

DC-IN

C C

24810mA

+

19VB

P

U301

5243mA

638mA

237mA

2311mA

PU801

PU501

PU601

PU401

+APU_CORE

+

APU_CORE_SOC

+1.2V

+0.6VS

5000mA

+

0.9VALW

9500mA

1200mA

+3VLP

KB9022

B B

+5VALW

14700mA3869mA

PU401

To VGA
+VGA_CORE
+VDDCI/VDD_08
+1.35VSDGPU

A A

2000mA

5

3579mA
169mA
474mA

+INVPWR_B+

L

X1

Panel BackLight

13347mA

+

4

3VALW

4

2026mA

8330mA

4200mA

PU602

U2

U3

+1.8VALW

2

T

o VGA10mA

+

3VS_SSD1

+5VS

660mA

3

A

+

2.5V

+

1.2V

+0.6VS

+3VS_SSD1

+

3V_LAN

+TP_VCC

+

3VS_WLAN

+

3V_HUB

+LCDVDD

1.2V_HDMI

+3VS_CAM

+

5VS_BL

5VALW_MUX

+5VS_HDD

+VCC_FAN1
+VCC_FAN2

+5VS_PVDD

+

FP_VCC

+TS_PWR

PU Power Rail

VDDCR_VDD @0.65-TBD

VDDCR_SOC @0.72-TBD

VDD_33 @0.25A

VDD_18 @2.0A

VDDP @4.0A

VDDIO_MEM_S3 @6.0A

VDD_33_S5 @0.25A

VDD_18_S5 @0.5A

VDDIO_AUDIO @0.2A

VDDP_S5 @1.0A

VDDBT_RTC_G @0.045mA

DDR4 SO-DIMM1/SO-DIMM2

+2.5V

+1.2V

+0.6VS

S

ATA Redriver*2 (M.2 & HDD)

M

.2 PCIE SSD

LAN RTL8118ASA

Touch Pad

WLAN

U

SB HUB

P

anel Logic

M

.2 SATA SSD

H

DMI Retimer

Camera

KB Light

T

ype C

RTS5441E

USB3.0(Charger)

U

SB3.0US13

USB/B

HDD

FAN1/FAN2

Audio

Finger Print

Touch Screen

2

2

2

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

70000mA

+APU_CORE

13000mA

+APU_CORE_SOC

250mA

+3VS

2000mA

+1.8VS

4

000mA

2200mA

528mA

+

3VS

U4

T

UV8

J

RTC1

PU502

U

L1

RL2

U13

R

M101

UM3

R

S148

U

R

X18

U

2616

US14

U

S11

US12

JIO2

RO4

RF4/RF7

LA1

UK6

R

X17

o VGA

X1

+0.9VS

+

1.8VS

+

RTCVCC

+2.5V

3

1013mA

U

C8

+RTC_APU_R

U

1302

4000mA

+0.9VS

6000mA

+1.2V

250mA

+3VALW

500mA

+1.8VALW

200mA

+1.8VS

1000mA

+0.9VALW

0.045mA

+RTC_APU_R

528mA

4160mA

1500mA

280mA

2790mA

300mA

30mA

1500mA

5

9mA

1500mA

+

200mA

200mA

200mA

+

250mA

3000mA

+USB3_VCCC

2000mA

+USB3_VCCA

2

000mA +USB3_VCCB

2500mA

1500mA

1000mA

1500mA

1

00mA

100mA

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

R18M-G1-90

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Group C, S0 dom ain

Group B, S0 dom ain

Group B, S3 dom ain

Group A, S5 dom ain

+19VB

PU1401

3579mA

+3VALW 10mA

U

3VALW

V8

PU701

PU1001

10mA

+

1013mA

+19VB

474mA

140000mA

12000mA

1013mA

6720mA

1

GPU Power Rail (R18M-G1-90)

+

VGA_CORE

VDDC

@140A

+

VDDCI

V

DDCI

@12A

+VDDCI

V

DD_08

@4A

+3VSDGPU

+

2000mA

+1.5VSDGPU

4

+1.5VSDGPU

T

T

T

itle

itle

itle

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

ustom

ustom

ustom

Date: Sheet

Date: Sheet

Date: Sheet

VDD_GPIO33

1.8VSDGPU

VDD_18

T

SVDD

VMEMIO

720mA

V

RAM x4pcs

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

ompal Electronics, Inc.

P

P

P

OWER MAP

OWER MAP

OWER MAP

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

@0.01A

@1A

@0.013A

@2A

o

o

o

f

4 99Wednesday, May 15, 2019

f

4 99Wednesday, May 15, 2019

f

1

4 99Wednesday, May 15, 2019

1

1

1

A

A

A

5

A

MD Picasso Platform Power Sequence

A

C-IN G3 --> S0

+3VLP

ACIN

EC_ON

D D

+5VALW

ON/OFFBTN#

3

V_EN

+

3VALW

41.49ms

41.49ms

2.32ms, Tr = 555us

9.608us

197.4ms

93.85ms

1.124ms, Tr = 1.075ms

4

S

0 --> S3 S3 --> S0

3

2

1

S0 --> S5

+3VLP

ACIN

EC_ON

+5VALW

ON/OFFBTN#

8.190s

5.228ms, Tf = 4.973ms

3V_EN

+

3VALW

8.190s

8.190s

9.166ms

1.525ms, Tf = 9.252ms

0.9_1.8VALW_PWREN

+1.8VALW

+0.9VALW

PBTN_OUT#

EC_RSMRST#

SLP_S5#

SLP_S3#

SYSON

+1.2V

+2.5V

SUSP#

+5VS

+3VS

+1.8VS

+0.6VS

KBRST#

0.9VS_PWR_EN#

+0.9VS

VR_ON

+APU_CORE

+APU_CORE_NB

VGATE

SYS_PWRGD_EC

APU_PWROK

LPC_RST#

APU_PCIE_RST#

APU_RST#

V

GA Sequence

P

E_GPIO1

+3VSDGPU

+1.8VSDGPU

0.9_1.8VALW_PWREN

+1.8VALW

+0.9VALW

PBTN_OUT#

EC_RSMRST#

SLP_S5#

SLP_S3#

SYSON

+1.2V

+2.5V

SUSP#

C C

+5VS

+3VS

+1.8VS

+0.6VS

KBRST#

0.9VS_PWR_EN#

+0.9VS

VR_ON

+APU_CORE

+APU_CORE_SOC

VGATE

SYS_PWRGD_EC

APU_PWROK

LPC_RST#

APU_PCIE_RST#

B B

APU_RST#

V

GA Sequence

PE_GPIO1

+3VSDGPU

+1.8VSDGPU

93.9ms

2.560ms, Tr = 1.418ms

820.9us, Tr = 358us

199.4ms

99.42ms

5.422ms

132.6ms

168us

168us

119ms

721.4us, Tr = 193.8us

1.695ms, Tr = 1.431ms

19.85ms

643.7us, Tr = 540.1us

683.4us, Tr = 525.9us

321us, Tr = 205.1us

16us, Tr = 17.18us

19.92ms

39.66ms

335.9us, Tr = 132.1us 331.1us, Tr = 127.2us2.3ms, Tf = 2.246ms 2.221ms, Tf = 2.165us

19.77ms

2.186ms, Tr = 295.7us

2.212ms, Tr = 316.7us

2.393ms

41.59ms

15.02ms

10.39ms

12.24ms

21.36ms

1.93s

1.153ms, Tr = 955.4us

1.306ms

4.826ms

4.956ms

4.956ms

56.14ms

4.415ms. Tf = 4.407ms

33.12ms, Tf = 32.78ms

12.87ms, Tf = 12.59ms

2.716ms, Tf = 2.480ms 837.7us, Tf = 772.7us

60.86ms

60.92ms

90.80ms

339.7us, Tf = 267.5us

338.9us, Tf = 284.6us

27.25ms

11.1ms

77us, Tf = 266.8us

13.44ms, Tf = 3.396ms

20.48ms

696.6us, Tr = 591.2us

716.1us, Tr = 555.7us

327.7us, Tr = 211.1us

15.42us, Tr = 15.38us

19.34ms

39.45ms

19.77ms

2.190ms, Tr = 299.8us

2.210ms, Tr = 313.4us

2.391ms

41.56ms

15.10ms

10.61ms

12.64ms

21.60ms

211.1ms

1.31ms

4.837ms

4.92ms

4.92ms

1.158ms, Tr = 956.5us

4.496ms, Tr = 1.374ms4.470ms, Tr = 1.359ms

51.70ms

51.69ms

58.19ms

58.25ms

24.92ms

1

.575s

10.96ms

75.49us, Tf = 2.634ms

13.39ms, Tf = 3.463ms

7.537ms, Tf = 9.313ms

2.353ms, Tf = 38.51us

5.143ms, Tf = 20.32ms

6.756ms, Tf = 6.739ms

28.36ms, Tf = 28.04ms

13.95ms, Tf = 13.67ms

87.99ms

335.2us, Tf = 247.5us

329.9us, Tf = 273.3us

ssued Date

ssued Date

ssued Date

10.97ms

1.665ms, Tf = 19.63ms

653.5ms, Tf = 4.784ms

10.97ms

1.758ms, Tf = 17.78ms

C

C

C

ompal Secret Data

ompal Secret Data

2

2

2

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

2

ompal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

VGA_ON_B

+VDDCI

+VGA_CORE

DGPU_PWRGOOD

+1.5VSDGPU

PE_GPIO0

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheetof

Date: Sheetof

Date: Sheetof

ompal Electronics, Inc.

itle

itle

itle

C

C

C

ustom

ustom

ustom

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

1

P

P

P

OWER SEQUENCE

OWER SEQUENCE

OWER SEQUENCE

5 99Wednesday, May 15, 2019

5 99Wednesday, May 15, 2019

5 99Wednesday, May 15, 2019

1

1

1

VGA_ON_B

+

VDDCI

+VGA_CORE

DGPU_PWRGOOD

+1.5VSDGPU

PE_GPIO0

P

LT_RST_VGA# PLT_RST_VGA#

A A

5

5.351ms

6.218ms, Tr = 84.15us

6.218ms, Tr = 85.54us

6.174ms

772.6us, Tr = 416.8us 830.8us, Tr = 480.8us

139.7ms

5.036ms

4

11.1ms

1.652ms, Tf = 21.21ms

894us, Tf = 5.296ms

11.1ms

1.746ms, Tf = 18.06ms

5.354ms

6.173ms, Tr = 84.5us

6.173ms, Tr = 86.28us

6.216ms

96.42ms

5.032ms

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

A

A

5

M

ain Func = CPU

4

3

2

1

UC1B

D D

P

EG_ARX_ GTX_P027

P

EG_ARX_ GTX_N027

P

EG_ARX_ GTX_P127

P

PEG

EG_ARX_ GTX_N127

P

EG_ARX_ GTX_P227

P

EG_ARX_ GTX_N227

P

EG_ARX_ GTX_P327

P

EG_ARX_ GTX_N327

P

EG_ARX_ GTX_P427

P

EG_ARX_ GTX_N427

P

EG_ARX_ GTX_P527

P

EG_ARX_ GTX_N527

P

EG_ARX_ GTX_P627

P

EG_ARX_ GTX_N627

P

EG_ARX_ GTX_P727

P

EG_ARX_ GTX_N727

EG_ARX_ GTX_P0

P

EG_ARX_ GTX_N0

P

EG_ARX_ GTX_P1

P

EG_ARX_ GTX_N1

P

EG_ARX_ GTX_P2

P

EG_ARX_ GTX_N2

P

EG_ARX_ GTX_P3

P

EG_ARX_ GTX_N3

P

EG_ARX_ GTX_P4

P

EG_ARX_ GTX_N4

P

EG_ARX_ GTX_P5

P

EG_ARX_ GTX_N5

P

EG_ARX_ GTX_P6

P

EG_ARX_ GTX_N6

P

EG_ARX_ GTX_P7

P

EG_ARX_ GTX_N7

P

P

8

P

_GFX_RXP0

P

9

P

_GFX_RXN0

N

6

P

_GFX_RXP1

N

7

P

_GFX_RXN1

M

8

P

_GFX_RXP2

M

9

P

_GFX_RXN2

L

6

P

_GFX_RXP3

L

7

P

_GFX_RXN3

K

11

P

_GFX_RXP4

J

11

P

_GFX_RXN4

H

6

P

_GFX_RXP5

H

7

P

_GFX_RXN5

G

6

P

_GFX_RXP6

F

7

P

_GFX_RXN6

G

8

P

_GFX_RXP7

F

8

P

_GFX_RXN7

PCIE

EG_ATX_ GRX_P0

P

1

N

_GFX_TXP0

P

_GFX_TXN0

P

_GFX_TXP1

P

_GFX_TXN1

P

_GFX_TXP2

P

_GFX_TXN2

P

_GFX_TXP3

P

_GFX_TXN3

P

_GFX_TXP4

P

_GFX_TXN4

P

_GFX_TXP5

P

_GFX_TXN5

P

_GFX_TXP6

P

_GFX_TXN6

P

_GFX_TXP7

P

_GFX_TXN7

P

3

N

2

M

4

M

2

L

4

L

1

L

3

L

2

K

4

K

2

J

4

J

1

H

3

H

2

H

4

H

EG_ATX_ GRX_N0

P

EG_ATX_ GRX_P1

P

EG_ATX_ GRX_N1

P

EG_ATX_ GRX_P2

P

EG_ATX_ GRX_N2

P

EG_ATX_ GRX_P3

P

EG_ATX_ GRX_N3

P

EG_ATX_ GRX_P4

P

EG_ATX_ GRX_N4

P

EG_ATX_ GRX_P5

P

EG_ATX_ GRX_N5

P

EG_ATX_ GRX_P6

P

EG_ATX_ GRX_N6

P

EG_ATX_ GRX_P7

P

EG_ATX_ GRX_N7

P

P

EG_ATX_ GRX_P0 27

P

EG_ATX_ GRX_N0 27

P

EG_ATX_ GRX_P1 27

P

EG_ATX_ GRX_N1 27

P

EG_ATX_ GRX_P2 27

P

EG_ATX_ GRX_N2 27

P

EG_ATX_ GRX_P3 27

P

EG_ATX_ GRX_N3 27

P

EG_ATX_ GRX_P4 27

P

EG_ATX_ GRX_N4 27

P

EG_ATX_ GRX_P5 27

P

EG_ATX_ GRX_N5 27

P

EG_ATX_ GRX_P6 27

P

EG_ATX_ GRX_N6 27

P

EG_ATX_ GRX_P7 27

P

EG_ATX_ GRX_N7 27

PEG

CIE_ARX_D TX_P0

P

C C

M.2 SSD1

LAN

WLAN

M.2 SSD2

B B

CIE_ARX_D TX_P068

P

CIE_ARX_D TX_N068

P

CIE_ARX_D TX_P168

P

CIE_ARX_D TX_N168

P

CIE_ARX_D TX_P268

P

CIE_ARX_D TX_N268

P

CIE_ARX_D TX_P368

P

CIE_ARX_D TX_N368

P

CIE_ARX_D TX_P451

P

CIE_ARX_D TX_N451

P

CIE_ARX_D TX_P552

P

CIE_ARX_D TX_N552

S

ATA_ARX _DTX_P067

S

ATA_ARX _DTX_N067

S

ATA_ARX _DTX_P169

S

ATA_ARX _DTX_N169

P

CIE_ARX_D TX_N0

P

CIE_ARX_D TX_P1

P

CIE_ARX_D TX_N1

P

CIE_ARX_D TX_P2

P

CIE_ARX_D TX_N2

P

CIE_ARX_D TX_P3

P

CIE_ARX_D TX_N3

P

CIE_ARX_D TX_P4

P

CIE_ARX_D TX_N4

P

CIE_ARX_D TX_P5

P

CIE_ARX_D TX_N5

P

ATA_ARX _DTX_P0

S

ATA_ARX _DTX_N0

S

ATA_ARX _DTX_P1

S

ATA_ARX _DTX_N1

S

N

10

P

_GPP_RXP0

N

9

P

_GPP_RXN0

L

10

P

_GPP_RXP1

L

9

P

_GPP_RXN1

L

12

P

_GPP_RXP2

M

11

P

_GPP_RXN2

P

12

P

_GPP_RXP3

P

11

P

_GPP_RXN3

V

6

P

_GPP_RXP4

V

7

P

_GPP_RXN4

T

8

P

_GPP_RXP5

T

9

P

_GPP_RXN5

R

6

P

_GPP_RXP6/SATA_RXP0

R

7

P

_GPP_RXN6/SATA_RXN0

R

9

P

_GPP_RXP7/SATA_RXP1

R

10

P

_GPP_RXN7/SATA_RXN1

@

FP5 REV 0.90
P

ART 2 OF 13

F

P5_BGA_ 1140P

_GPP_TXP0

P

_GPP_TXN0

P

_GPP_TXP1

P

_GPP_TXN1

P

_GPP_TXP2

P

P

_GPP_TXN2

P

_GPP_TXP3

P

_GPP_TXN3

P

_GPP_TXP4

P

_GPP_TXN4

P

_GPP_TXP5

P

_GPP_TXN5

P

_GPP_TXP6/SATA_TXP0

P

_GPP_TXN6/SATA_TXN0

P

_GPP_TXP7/SATA_TXP1

P

_GPP_TXN7/SATA_TXN1

2

N

3

P

4

P

2

P

3

R

R

1

T

4

T

2

W

2

W

4

W

3

V

2

V

1

V

3

U

2

U

4

CIE_ATX_D RX_P0

P

CIE_ATX_D RX_N0

P

CIE_ATX_D RX_P1

P

CIE_ATX_D RX_N1

P

CIE_ATX_D RX_P2

P

CIE_ATX_D RX_N2

P

CIE_ATX_D RX_P3

P

CIE_ATX_D RX_N3

P

CIE_ATX_D RX_P4

P

CIE_ATX_D RX_N4

P

CIE_ATX_D RX_P5

P

CIE_ATX_D RX_N5

P

ATA_ATX _DRX_P0

S

ATA_ATX _DRX_N0

S

ATA_ATX _DRX_P1

S

ATA_ATX _DRX_N1

S

1 2

C1204 0.22U_04 02_16V7K

C

1 2

C1203 0.22U_04 02_16V7K

C

1 2

C

C1206 0.22U_04 02_16V7K

C

C1205 0.22U_04 02_16V7K

C1212 0.22U_04 02_16V7K

C

C1211 0.22U_04 02_16V7K

C

C1214 0.22U_04 02_16V7K

C

C1213 0.22U_04 02_16V7K

C

2

1

2

1

2

1

2

1

2

1

2

1

C1 .1U_ 0402_16V7K

C

2

1

C2 .1U_ 0402_16V7K

C

2

1

C3 .1U_ 0402_16V7K

C

2

1

C4 .1U_ 0402_16V7K

C

P

CIE_ATX_C _DRX_P0 68

P

CIE_ATX_C _DRX_N0 68

P

CIE_ATX_C _DRX_P1 68

P

CIE_ATX_C _DRX_N1 68

P

CIE_ATX_C _DRX_P2 68

P

CIE_ATX_C _DRX_N2 68

P

CIE_ATX_C _DRX_P3 68

P

CIE_ATX_C _DRX_N3 68

P

CIE_ATX_C _DRX_P4 51

P

CIE_ATX_C _DRX_N4 51

P

CIE_ATX_C _DRX_P5 52

P

CIE_ATX_C _DRX_N5 52

S

ATA_ATX _DRX_P0 67

S

ATA_ATX _DRX_N0 67

S

ATA_ATX _DRX_P1 69

S

ATA_ATX _DRX_N1 69

M.2 SSD1

LAN

WLAN

HDDHDD

M.2 SSD2

APU PN Table

A

PU Platform

C1 R7APU@

U

IC RYZEN7 YM3700C4T4MFG 2.3G APU AB O!

S

A0000C7680

S

P

icasso

U

C1 R5APUQC@

S

IC RYZEN5 YM3500C4T4MFG 2.1G BGA AP U

S

A0000CCR20

U

C1 R7APUQC@

S

IC RYZEN7 YM3700C4T4MFG 2.3G BGA AP U

S

A0000C7640

U

C1 R5APU@

S

IC RYZEN5 YM3500C4T4MFG 2.1G APU AB O!

S

A0000CCR60

PCB Number

A A

ZZ

EVT@

Z
PCB 2QE L A-H901P REV0 MB 2

DA8001J M000

Z

ZZ

PVT@

PCB FH50 P LA-H901P LS-H9 01P/H502P

DAZ2QE0 0100

P

CB: DAZ2QE00100, DA8001JM010 REV: 1.0/1.0/1.0

ZZ

MP@

Z
PCB FH50 P LA-H901P LS-H9 01P/H502P

DAZ2QE0 0101

PCB: DAZ2QE00101, DA8001JM01A REV: 1.A/1.0/1.0

5

S

S

S

ecurity Classif ication

ecurity Classif ication

ecurity Classif ication

2

2

2

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

018/ 12/1 8 2019/12/18

3

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered D ate

eciphered D ate

eciphered D ate

Compal PNCustomer PNCustomer PNCustomer PNCustomer PN Compal PN

C

C

T

T

Title

itle

itle

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

C

C

C

ustom

ustom

ustom

Date: Sheet

Date: Sheet

2

Date: Sheet

C

F

F

F

P5_(1/7)_PEG/PCIE/SATA

P5_(1/7)_PEG/PCIE/SATA

P5_(1/7)_PEG/PCIE/SATA

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

ompal Electronics, Inc.

ompal Electronics, Inc.

ompal Electronics, Inc.

6 99Wednesd ay, May 15, 2019

6 99Wednesd ay, May 15, 2019

6 99Wednesd ay, May 15, 2019

1

1

1

1

A

A

A

o

o

o

f

f

f

5

M

ain Func = CPU

4

3

2

1

MEMORY B

FP5 REV 0.90

ART 9 OF 13

P

P5_BGA_1140P

F

UC1I

M

M

M

M

M

M

M

M

M

M

M

B_DATA10

M

B_DATA11

M

B_DATA12

M

B_DATA13

M

B_DATA14

M

B_DATA15

M

B_DATA16

M

B_DATA17

M

B_DATA18

M

B_DATA19

M

B_DATA20

M

B_DATA21

M

B_DATA22

M

B_DATA23

M

B_DATA24

M

B_DATA25

M

B_DATA26

M

B_DATA27

M

B_DATA28

M

B_DATA29

M

B_DATA30

M

B_DATA31

M

B_DATA32

M

B_DATA33

M

B_DATA34

M

B_DATA35

M

B_DATA36

M

B_DATA37

M

B_DATA38

M

B_DATA39

M

B_DATA40

M

B_DATA41

M

B_DATA42

M

B_DATA43

M

B_DATA44

M

B_DATA45

M

B_DATA46

M

B_DATA47

M

B_DATA48

M

B_DATA49

M

B_DATA50

M

B_DATA51

M

B_DATA52

M

B_DATA53

M

B_DATA54

M

B_DATA55

M

B_DATA56

M

B_DATA57

M

B_DATA58

M

B_DATA59

M

B_DATA60

M

B_DATA61

M

B_DATA62

M

B_DATA63

M

B_PAROUT

B_DATA0

B_DATA1

B_DATA2

B_DATA3

B_DATA4

B_DATA5

B_DATA6

B_DATA7

B_DATA8

B_DATA9

R

SVD_17

R

SVD_19

R

SVD_26

R

SVD_29

R

SVD_16

R

SVD_15

R

SVD_25

R

SVD_24

D

DR_B_DQ0

D

B

21

DR_B_DQ1

D

D

21

DR_B_DQ2

D

B

23

DR_B_DQ3

D

D

23

DR_B_DQ4

D

A

20

DR_B_DQ5

D

C

20

DR_B_DQ6

D

A

22

DR_B_DQ7

D

C

22

DR_B_DQ8

D

D

24

DR_B_DQ9

D

A

25

DR_B_DQ10

D

D

27

DR_B_DQ11

D

C

27

DR_B_DQ12

D

C

23

DR_B_DQ13

D

B

24

DR_B_DQ14

D

C

26

DR_B_DQ15

D

B

27

D

DR_B_DQ16

C

30

DR_B_DQ17

D

E

29

DR_B_DQ18

D

H

29

DR_B_DQ19

D

H

31

DR_B_DQ20

D

A

28

DR_B_DQ21

D

D

28

DR_B_DQ22

D

F

31

DR_B_DQ23

D

G

30

DR_B_DQ24

D

J

29

DR_B_DQ25

D

J

31

DR_B_DQ26

D

L

29

DR_B_DQ27

D

L

31

DR_B_DQ28

D

H

30

DR_B_DQ29

D

H

32

DR_B_DQ30

D

L

30

DR_B_DQ31

D

L

32

DR_B_DQ32

D

A

P29

DR_B_DQ33

D

A

P32

DR_B_DQ34

D

A

T29

DR_B_DQ35

D

A

U32

DR_B_DQ36

D

A

N30

DR_B_DQ37

D

A

P31

DR_B_DQ38

D

A

R30

DR_B_DQ39

D

A

T31

DR_B_DQ40

D

A

U29

DR_B_DQ41

D

A

V30

DR_B_DQ42

D

B

B30

DR_B_DQ43

D

B

A28

DR_B_DQ44

D

A

U30

DR_B_DQ45

D

A

U31

DR_B_DQ46

D

A

Y32

DR_B_DQ47

D

A

Y29

DR_B_DQ48

D

B

A27

DR_B_DQ49

D

B

C27

DR_B_DQ50

D

B

A24

DR_B_DQ51

D

B

C24

DR_B_DQ52

D

B

D28

DR_B_DQ53

D

B

B27

DR_B_DQ54

D

B

B25

DR_B_DQ55

D

B

D25

DR_B_DQ56

D

B

C23

DR_B_DQ57

D

B

B22

DR_B_DQ58

D

B

C21

DR_B_DQ59

D

B

D20

DR_B_DQ60

D

B

B23

DR_B_DQ61

D

B

A23

DR_B_DQ62

D

B

B21

DR_B_DQ63

D

B

A21

M

31

N

30

P

31

R

32

M

30

M

29

P

30

P

29

DR_B_PAR

D

A

G31

DR_B_DQ[63..0] 24

D

DR_B_PAR 24

UC1A

D

DR_A_MA[13..0]23

D D

D

DR_A_MA14_W E#23

D

DR_A_MA15_CAS#23

D

DR_A_MA16_RAS#23

D

DR_A_BA023

D

DR_A_BA123

D

DR_A_BG023

D

DR_A_BG123

D

DR_A_ACT#23

D

DR_A_DM[7..0]23

D

DR_A_DQS023

D

DR_A_DQS0#23

D

DR_A_DQS123

D

DR_A_DQS1#23

D

DR_A_DQS223

D

C C

B B

DR_A_DQS2#23

D

DR_A_DQS323

D

DR_A_DQS3#23

D

DR_A_DQS423

D

DR_A_DQS4#23

D

DR_A_DQS523

D

DR_A_DQS5#23

D

DR_A_DQS623

D

DR_A_DQS6#23

D

DR_A_DQS723

D

DR_A_DQS7#23

D

DR_A_CLK023

D

DR_A_CLK0#23

D

DR_A_CLK123

D

DR_A_CLK1#23

D

DR_A_CS0#23

D

DR_A_CS1#23

D

DR_A_CKE023

D

DR_A_CKE123

D

DR_A_ODT023

D

DR_A_ODT123

D

DR_A_ALERT#23

D

DR_A_EVENT#23

D

DR_A_RST#2 3

D

DR_A_MA0

D

DR_A_MA1

D

DR_A_MA2

D

DR_A_MA3

D

DR_A_MA4

D

DR_A_MA5

D

DR_A_MA6

D

DR_A_MA7

D

DR_A_MA8

D

DR_A_MA9

D

DR_A_MA10

D

DR_A_MA11

D

DR_A_MA12

D

DR_A_MA13

D

DR_A_MA14_W E#

D

DR_A_MA15_CAS#

D

DR_A_MA16_RAS#

D

DR_A_BA0

D

DR_A_BA1

DR_A_BG0

D

DR_A_BG1

D

DR_A_ACT#

D

D

DR_A_DM0

D

DR_A_DM1

D

DR_A_DM2

D

DR_A_DM3

D

DR_A_DM4

D

DR_A_DM5

D

DR_A_DM6

D

DR_A_DM7

D

DR_A_DQS0

D

DR_A_DQS0#

D

DR_A_DQS1

D

DR_A_DQS1#

D

DR_A_DQS2

D

DR_A_DQS2#

D

DR_A_DQS3

D

DR_A_DQS3#

D

DR_A_DQS4

D

DR_A_DQS4#

D

DR_A_DQS5

D

DR_A_DQS5#

D

DR_A_DQS6

D

DR_A_DQS6#

D

DR_A_DQS7

D

DR_A_DQS7#

D

DR_A_CLK0

D

DR_A_CLK0#

D

DR_A_CLK1

D

DR_A_CLK1#

D

DR_A_CS0#

D

DR_A_CS1#

D

DR_A_CKE0

D

DR_A_CKE1

D

DR_A_ODT0

D

DR_A_ODT1

D

DR_A_ALERT#

D

DR_A_EVENT#

D

DR_A_RST#

F25

A

A_ADD0

M

E23

A

A_ADD1

M

D27

A

A_ADD2

M

E21

A

A_ADD3

M

C24

A

A_ADD4

M

C26

A

A_ADD5

M

D21

A

A_ADD6

M

C27

A

A_ADD7

M

D22

A

A_ADD8

M

C21

A

A_ADD9

M

F22

A

A_ADD10

M

A24

A

A_ADD11

M

C23

A

A_ADD12

M

J25

A

A_ADD13_BANK2

M

G27

A

A_WE_L_ADD14

M

G23

A

A_CAS_L_ADD15

M

G26

A

A_RAS_L_ADD16

M

F21

A

A_BANK0

M

F27

A

A_BANK1

M

A21

A

A_BG0

M

A27

A

A_BG1

M

A22

A

A_ACT_L

M

21

F

A_DM0

M

27

G

A_DM1

M

24

N

A_DM2

M

23

N

A_DM3

M

L24

A

A_DM4

M

N27

A

A_DM5

M

W25

A

A_DM6

M

T21

A

A_DM7

M

T

27

R

SVD_36

F

22

M

A_DQS_H0

G

22

M

A_DQS_L0

H

27

M

A_DQS_H1

H

26

M

A_DQS_L1

N

27

M

A_DQS_H2

N

26

M

A_DQS_L2

R

21

M

A_DQS_H3

P

21

M

A_DQS_L3

A

M26

M

A_DQS_H4

A

M27

M

A_DQS_L4

A

N24

M

A_DQS_H5

A

N25

M

A_DQS_L5

A

U23

M

A_DQS_H6

A

T23

M

A_DQS_L6

A

V20

M

A_DQS_H7

A

W20

M

A_DQS_L7

V

24

R

SVD_41

V

23

R

SVD_40

A

D25

M

A_CLK_H0

A

D24

M

A_CLK_L0

A

E26

M

A_CLK_H1

A

E27

M

A_CLK_L1

A

G21

M

A_CS_L0

A

J27

M

A_CS_L1

Y

23

M

A_CKE0

Y

26

M

A_CKE1

A

G24

M

A_ODT0

A

J22

M

A_ODT1

A

A25

M

A_ALERT_L

A

E24

M

A_EVENT_L

Y

24

M

A_RESET_L

@

MEMORY A

FP5 REV 0.90
P

ART 1 OF 13

F

P5_BGA_1140P

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

M

A_PAROUT

M

A_DATA0

A_DATA1

A_DATA2

A_DATA3

A_DATA4

A_DATA5

A_DATA6

A_DATA7

A_DATA8

A_DATA9

A_DATA10

A_DATA11

A_DATA12

A_DATA13

A_DATA14

A_DATA15

A_DATA16

A_DATA17

A_DATA18

A_DATA19

A_DATA20

A_DATA21

A_DATA22

A_DATA23

A_DATA24

A_DATA25

A_DATA26

A_DATA27

A_DATA28

A_DATA29

A_DATA30

A_DATA31

A_DATA32

A_DATA33

A_DATA34

A_DATA35

A_DATA36

A_DATA37

A_DATA38

A_DATA39

A_DATA40

A_DATA41

A_DATA42

A_DATA43

A_DATA44

A_DATA45

A_DATA46

A_DATA47

A_DATA48

A_DATA49

A_DATA50

A_DATA51

A_DATA52

A_DATA53

A_DATA54

A_DATA55

A_DATA56

A_DATA57

A_DATA58

A_DATA59

A_DATA60

A_DATA61

A_DATA62

A_DATA63

SVD_34

R

SVD_35

R

SVD_51

R

SVD_52

R

SVD_27

R

SVD_28

R

SVD_43

R

SVD_42

R

D

D

DR_A_DQ0

21

J

DR_A_DQ1

D

21

H

DR_A_DQ2

D

23

F

D

DR_A_DQ3

23

H

D

DR_A_DQ4

20

G

DR_A_DQ5

D

20

F

DR_A_DQ6

D

22

J

DR_A_DQ7

D

23

J

DR_A_DQ8

D

25

G

DR_A_DQ9

D

26

F

DR_A_DQ10

D

24

L

DR_A_DQ11

D

26

L

DR_A_DQ12

D

23

L

D

DR_A_DQ13

25

F

DR_A_DQ14

D

25

K

DR_A_DQ15

D

27

K

DR_A_DQ16

D

25

M

DR_A_DQ17

D

27

M

DR_A_DQ18

D

27

P

D

DR_A_DQ19

24

R

DR_A_DQ20

D

27

L

DR_A_DQ21

D

24

M

DR_A_DQ22

D

24

P

DR_A_DQ23

D

25

P

DR_A_DQ24

D

22

M

DR_A_DQ25

D

21

N

DR_A_DQ26

D

22

T

DR_A_DQ27

D

21

V

D

DR_A_DQ28

21

L

D

DR_A_DQ29

20

M

DR_A_DQ30

D

23

R

DR_A_DQ31

D

21

T

DR_A_DQ32

D

L27

A

DR_A_DQ33

D

L25

A

D

DR_A_DQ34

P26

A

DR_A_DQ35

D

R27

A

D

DR_A_DQ36

K26

A

DR_A_DQ37

D

K24

A

DR_A_DQ38

D

M24

A

D

DR_A_DQ39

P27

A

D

DR_A_DQ40

M23

A

DR_A_DQ41

D

M21

A

DR_A_DQ42

D

R25

A

D

DR_A_DQ43

U27

A

DR_A_DQ44

D

L22

A

DR_A_DQ45

D

L21

A

D

DR_A_DQ46

P24

A

D

DR_A_DQ47

P23

A

DR_A_DQ48

D

W26

A

DR_A_DQ49

D

V25

A

DR_A_DQ50

D

V22

A

DR_A_DQ51

D

W22

A

DR_A_DQ52

D

U26

A

DR_A_DQ53

D

V27

A

DR_A_DQ54

D

W23

A

DR_A_DQ55

D

T22

A

DR_A_DQ56

D

W21

A

DR_A_DQ57

D

U21

A

DR_A_DQ58

D

P21

A

D

DR_A_DQ59

N20

A

D

DR_A_DQ60

R22

A

D

DR_A_DQ61

N22

A

DR_A_DQ62

D

T20

A

DR_A_DQ63

D

R20

A

24

T

25

T

25

W

27

W

26

R

27

R

27

V

26

V

DR_A_PAR

D

F24

A

DR_A_DQ[63..0] 23

D

DR_A_PAR 23

D

DR_B_MA[13..0]24

D

DR_B_MA14_W E#24

D

DR_B_MA15_C AS#24

D

DR_B_MA16_R AS#24

D

DR_B_BA024

D

DR_B_BA124

D

DR_B_BG024

D

DR_B_BG124

D

DR_B_ACT#2 4

D

DR_B_DM[7..0]24

D

DR_B_DQS024

D

DR_B_DQS0#24

D

DR_B_DQS124

D

DR_B_DQS1#24

D

DR_B_DQS224

D

DR_B_DQS2#24

D

DR_B_DQS324

D

DR_B_DQS3#24

D

DR_B_DQS424

D

DR_B_DQS4#24

D

DR_B_DQS524

D

DR_B_DQS5#24

D

DR_B_DQS624

D

DR_B_DQS6#24

D

DR_B_DQS724

D

DR_B_DQS7#24

D

DR_B_CLK024

D

DR_B_CLK0#24

D

DR_B_CLK124

D

DR_B_CLK1#24

D

DR_B_CS0#24

D

DR_B_CS1#24

D

DR_B_CKE024

D

DR_B_CKE124

D

DR_B_ODT024

D

DR_B_ODT124

D

DR_B_ALERT#24

D

DR_B_EVENT#24

D

DR_B_RST#2 4

DR_B_MA0

D

DR_B_MA1

D

DR_B_MA2

D

DR_B_MA3

D

DR_B_MA4

D

DR_B_MA5

D

DR_B_MA6

D

DR_B_MA7

D

DR_B_MA8

D

DR_B_MA9

D

DR_B_MA10

D

DR_B_MA11

D

DR_B_MA12

D

DR_B_MA13

D

D

DR_B_MA14_W E#

D

DR_B_MA15_C AS#

D

DR_B_MA16_R AS#

D

DR_B_BA0

D

DR_B_BA1

DR_B_BG0

D

DR_B_BG1

D

DR_B_ACT#

D

DR_B_DM0

D

DR_B_DM1

D

DR_B_DM2

D

DR_B_DM3

D

DR_B_DM4

D

DR_B_DM5

D

DR_B_DM6

D

DR_B_DM7

D

D

DR_B_DQS0

D

DR_B_DQS0#

D

DR_B_DQS1

D

DR_B_DQS1#

D

DR_B_DQS2

D

DR_B_DQS2#

D

DR_B_DQS3

D

DR_B_DQS3#

D

DR_B_DQS4

D

DR_B_DQS4#

D

DR_B_DQS5

D

DR_B_DQS5#

D

DR_B_DQS6

D

DR_B_DQS6#

D

DR_B_DQS7

D

DR_B_DQS7#

D

DR_B_CLK0

D

DR_B_CLK0#

D

DR_B_CLK1

D

DR_B_CLK1#

D

DR_B_CS0#

D

DR_B_CS1#

D

DR_B_CKE0

D

DR_B_CKE1

DR_B_ODT0

D

DR_B_ODT1

D

DR_B_ALERT#

D

DR_B_EVENT#

D

DR_B_RST#

D

A

G30

M

B_ADD0

A

C32

M

B_ADD1

A

C30

M

B_ADD2

A

B29

M

B_ADD3

A

B31

M

B_ADD4

A

A30

M

B_ADD5

A

A29

M

B_ADD6

Y

30

M

B_ADD7

A

A31

M

B_ADD8

W

29

M

B_ADD9

A

H29

M

B_ADD10

Y

32

M

B_ADD11

W

31

M

B_ADD12

A

L30

M

B_ADD13_BANK2

A

K30

M

B_WE_L_ADD14

A

K32

M

B_CAS_L_ADD15

A

J30

M

B_RAS_L_ADD16

A

H31

M

B_BANK0

A

G32

M

B_BANK1

V

31

M

B_BG0

V

29

M

B_BG1

V

30

M

B_ACT_L

C

21

M

B_DM0

C

25

M

B_DM1

E

32

M

B_DM2

K

30

M

B_DM3

A

P30

M

B_DM4

A

W31

M

B_DM5

B

B26

M

B_DM6

B

D22

M

B_DM7

N

32

R

SVD_21

D

22

M

B_DQS_H0

B

22

M

B_DQS_L0

D

25

M

B_DQS_H1

B

25

M

B_DQS_L1

F

29

B_DQS_H2

M

F

30

B_DQS_L2

M

K

31

M

B_DQS_H3

29

K

B_DQS_L3

M

R29

A

B_DQS_H4

M

R31

A

B_DQS_L4

M

W30

A

B_DQS_H5

M

W29

A

B_DQS_L5

M

C25

B

B_DQS_H6

M

A25

B

B_DQS_L6

M

C22

B

B_DQS_H7

M

A22

B

B_DQS_L7

M

31

N

SVD_20

R

29

N

SVD_18

R

C31

A

B_CLK_H0

M

D30

A

B_CLK_L0

M

D29

A

B_CLK_H1

M

D31

A

B_CLK_L1

M

E30

A

B_CLK_H2

M

E32

A

B_CLK_L2

M

F29

A

B_CLK_H3

M

F31

A

B_CLK_L3

M

J31

A

B0_CS_L0

M

M31

A

B0_CS_L1

M

J29

A

B1_CS_L0

M

M29

A

B1_CS_L1

M

29

U

B0_CKE0

M

30

T

B0_CKE1

M

32

V

B1_CKE0

M

31

U

B1_CKE1

M

L31

A

B0_ODT0

M

M32

A

B0_ODT1

M

L29

A

B1_ODT0

M

M30

A

B1_ODT1

M

30

W

B_ALERT_L

M

G29

A

B_EVENT_L

M

31

T

B_RESET_L

M

@

E

VENT# pull high

+

1.2V

D

1 2

C1 1K_0402_5%

R

+

1.2V

1 2

C2 1K_0402_5%

A A

5

R

DR_B_EVENT#

DR_A_EVENT#

D

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

2

2

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered Date

eciphered Date

eciphered Date

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

ustom

ustom

ustom

Date: Sheet

Date: Sheet

2

Date: Sheet

ompal Electronics, Inc.

F

F

F

P5_(2/7)_DDR4

P5_(2/7)_DDR4

P5_(2/7)_DDR4

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

1

7 99Wednesday, May 15, 201 9

1

1

1

A

A

A

o

o

o

f

7 99Wednesday, May 15, 201 9

f

7 99Wednesday, May 15, 201 9

f

A

M

ain Func = CPU

EC/THERM

+

3VS

C105 1K_0402_ 5%

R

C106 1K_0402_ 5%

R

C107 1K_0402_ 5%

R

C108 1K_0402_ 5%

R

1 1

E

C_SMB_CK228,58,66

E

C_SMB_DA228,58,66

2 2

+

3VS

R

C664 1K_0402_5%

1

@EMC@

C1202

C
.1U_0402_1 6V7K

2

1
1 2
1 2
1 2

1

2

2

1

EMC@

C5

C
33P_0402_5 0V8J

2

C_SMB_CK2

E

C_SMB_DA2

E

A

PU_SID

A

PU_ALERT#

A

PU_SIC

A

PU_PROCHOT #

1 2

C616 0_0402_ 5%

R

1 2

R

C617 0_0402_ 5%

T

HERMTRIP#

1

EMC@

C

C6

33P_0402_5 0V8J

2

A

PU_PROCHOT #

A

PU_RST#

A

PU_PWROK

PU_SIC

A

PU_SID

A

Close to APU

SVID

+

1.8VS

A

1
1 2
1

2

2

C109 1K_0402_ 5%@

3 3

R

C110 1K_0402_ 5%@

R

C111 1K_0402_ 5%@

R

PU_SVT_R

A

PU_SVC

A

PU_SVD

A

B

A

A

PU_DP0_P040

A

PU_DP0_N040

A

PU_DP0_P140

A

H

DMI

EDP

+

1.8VS

+

1.8VS

A

PU_PWROK88

A

PU_SVC88

A

PU_SVD88

PU_SVT_R88

PU_DP0_N140

A

PU_DP0_P240

A

PU_DP0_N240

A

PU_DP0_P340

A

PU_DP0_N340

E

DP_TXP03 8

E

DP_TXN038

E

DP_TXP13 8

E

DP_TXN138

E

DP_TXP23 8

E

DP_TXN238

E

DP_TXP33 8

E

DP_TXN338

1 2

C80 300_0402_5%

R
R

2

1

C81 300_0402_5%

T

HERMTRIP#58

A

PU_PROCHOT #58,84,88

1 2

C669 0_0402_5%

R

1 2

C670 0_0402_5%

R

PU_DP0_P0

A

PU_DP0_N0

A

PU_DP0_P1

A

PU_DP0_N1

A

PU_DP0_P2

A

PU_DP0_N2

A

PU_DP0_P3

A

PU_DP0_N3

E

DP_TXP0

E

DP_TXN0

E

DP_TXP1

E

DP_TXN1

E

DP_TXP2

E

DP_TXN2

E

DP_TXP3

E

DP_TXN3

A

PU_TDI

A

PU_TDO

A

PU_TCK

A

PU_TMS

A

PU_TRST#

A

PU_DBREQ#

A

PU_RST#

A

PU_PWROK

A

PU_SIC

A

PU_SID

A

PU_ALERT#

T

HERMTRIP#

A

PU_PROCHOT #

A

PU_SVC_R

A

PU_SVD_R

A

PU_SVT_R

C

8

D

P0_TXP0

A

8

D

P0_TXN0

D

8

D

P0_TXP1

B

8

D

P0_TXN1

B

6

D

P0_TXP2

C

7

D

P0_TXN2

C

6

D

P0_TXP3

D

6

D

P0_TXN3

E

6

D

P1_TXP0

D

5

D

P1_TXN0

E

1

D

P1_TXP1

1

C

D

P1_TXN1

3

F

P1_TXP2

D

E

4

P1_TXN2

D

4

F

P1_TXP3

D

2

F

P1_TXN3

D

U2

A

DI

T

U4

A

DO

T

U1

A

CK

T

U3

A

MS

T

V3

A

RST_L

T

W3

A

BREQ_L

D

W4

A

ESET_L

R

W2

A

WROK

P

14

H

IC

S

14

J

ID

S

15

J

LERT_L

A

P16

A

HERMTRIP_L

T

19

L

ROCHOT_L

P

16

F

VC0

S

IO18

16

H

VD0

S

16

J

VT0

S

@

UC1C

DISPLAY/SVI2/JTAG/TEST

D

P3:
DP2:
DP1: eDP
DP0: HDMI

IO18S5

IO18

IO33

FP5 REV 0.90

ART 3 OF 13

P

P5_BGA_1140P

F

C

IO18

D

D

P_STEREOSYNC

V

V

DDCR_SOC_SENSE

V

DDCR_SENSE

V

SS_SENSE_A

V

SS_SENSE_B

D

P_BLON

D

P_DIGON

P_VARY_BL

D

P0_AUXP

D

P0_AUXN

D

P0_HPD

D

P1_AUXP

D

P1_AUXN

D

P1_HPD

D

P2_AUXP

D

P2_AUXN

D

P2_HPD

D

P3_AUXP

D

P3_AUXN

D

P3_HPD

R

SVD_4

R

SVD_3

R

SVD_2

T

T

T

T

EST14

T

EST15

T

EST16

T

EST17

T

EST31

T

EST41

T

EST470

T

EST471

S

MU_ZVDD

C

ORETYPE

DDP_SENSE

EST4

EST5

EST6

E

NBKL_R

G

15

E

NVDD_R

F

15

I

NVTPWM_R

L

14

A

PU_DP0_CT RL_CLK

D

9

A

PU_DP0_CT RL_DATA

B

9

A

PU_DP0_HPD

C

10

E

DP_AUXP

G

11

E

DP_AUXN

F

11

E

DP_HPD

G

13

J

12

H

12

K

13

J

10

H

10

K

8

D

P_STEREOSYNC

K

15

F

14

F

12

F

10

A

P14

A

N14

F

13

G

18

H

19

F

18

F

19

W

24

A

R11

A

J21

A

K21

S

V

4

A

W11

C

A

PU_VDDP_SEN_ H

A

N11

A

PU_CORESOC_ SEN_H

J

19

A

PU_CORE_SEN _H

K

18

A

PU_VSS_SEN_L

J

18

A

PU_VDDP_SEN_ L

A

M11

A

PU_TEST4

A

PU_TEST5

A

PU_TEST14

A

PU_TEST15

A

PU_TEST16

A

PU_TEST17

A

PU_TEST31

A

PU_TEST41

A

PU_TEST47 0

A

PU_TEST47 1

MU_ZVDDP

ORETYPE

R

R

A

PU_DP0_CT RL_CLK 40

A

PU_DP0_CT RL_DATA 40

A

PU_DP0_HPD 40

E

DP_AUXP 38

E

DP_AUXN 38

E

DP_HPD 38

TP@

T

4949

TP@

4948

T

TP@

4942

T

TP@

T

4941

TP@

4940

T

TP@

4939

T

1 2

C1682 196_0402_1 %

2

1

C1681 1K_0402_5%@

A

PU_VDDP_SEN_ H 87

A

PU_CORESOC_ SEN_H 88

A

PU_CORE_SEN _H 88

A

PU_VSS_SEN_L 88

A

PU_VDDP_SEN_ L 87

D

HDMI

EDP

+

0.9VS

+

3VALW

Leakage prevent from power side

D

ISP

E

NBKL_R

E

NVDD_R

E

NVDD_R

I

NVTPWM_R

E

NBKL

E

NVDD

I

NVTPWM

E

NBKL_R

E

NVDD_R

I

NVTPWM_R

+

1.8VALW

5

C66

U

1

P

C

N

4

Y

2

A

G

NL17SZ07DFT 2G_SC70-5

3

A00004BV00

S

+

1.8VALW

5

U

C64

1

P

N

C

4

Y

2

A

G

NL17SZ07DFT 2G_SC70-5

3

S

@

A00004BV00

1 2

C690 0_0402_5%RS@

R

+

1.8VALW

5

C65

U

1

P

C

N

4

Y

2

A

G

NL17SZ07DFT 2G_SC70-5

3

A00004BV00

S

1

R

C3 4.7K_0402_5 %

1 2

R

C4 4.7K_0402_5 %@

1 2

C5 4.7K_0402_5 %

R

1 2

C6130 100K_0402_5 %

R

1 2

R

C6131 100K_0402_5 %

1 2

C6132 100K_0402_5 %@

R

E

E

NBKL

I

NVTPWM

E

NVDD

E

NBKL 58

E

NVDD 38

E

NVDD

I

NVTPWM 3 8

+

3VS

2

H

DT+

+

+

1.8VALW

J

HDT1

CONN@

PU_TCK_R

A

1

3

5

PU_TRST#

A

H2

C

0.01U_0402 _16V7K

4 4

1 2

H21 33_0402_5%

R

H38 10K_0402_5%

R

2

2

H39 10K_0402_5%

R

1

H40 10K_0402_5%

R

12

1

12

A

PU_TRST# _R

DT_P11

H

DT_P13

H

DT_P15

H

7

9

11

13

15

17

19

A

2

2

1

4

4

3

6

6

5

8

8

7

10

1

9

0

12

1

1

1

2

14

1

1

3

4

16

1

1

5

6

18

1

1

7

8

20

2

1

9

0

SAMTE_ASP-13644 6-07-B

PU_TMS_R

A

PU_TDI_R

A

PU_TDO_R

A

PU_PWROK _R

A

A

PU_RST#_R

A

PU_DBREQ#_R

H27 0_0402_5%H DT@

R

H28 0_0402_5%H DT@

R

R

H29 0_0402_5%H DT@

H30 0_0402_5%H DT@

R

H31 0_0402_5%H DT@

R

H32 0_0402_5%H DT@

R

R

H33 33_0402_5%

B

1 2

1

1 2

1 2

1

1 2

1 2

2

2

Follow C5V08

PU_TCK

A

PU_TMS

A

PU_TDI

A

PU_TDO

A

PU_PWROK

A

PU_RST#

A

PU_DBREQ#

A

A

PU_TCK

A

PU_TMS

A

PU_TDI

A

PU_DBREQ#

A

PU_TRST#

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

1

H34 1K_0402_5%

R

1 2

H35 1K_0402_5%

R

1 2

H36 1K_0402_5%

R

1 2

H37 1K_0402_5%

R

1

H26 1K_0402_5%

R

1.8VALW

2

2

C

C

C

ompal Secret Data

ompal Secret Data

2

2

2

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

ompal Secret Data

D

D

D

eciphered Date

eciphered Date

eciphered Date

D

TESTPOINT

D

P_STEREOSYNC

A

PU_TEST14

A

PU_TEST15

A

PU_TEST16

A

PU_TEST17

T

T

T

itle

itle

itle

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

ustom

ustom

ustom

Date: Sheet

Date: Sheet

Date: Sheet

1 2

C155 1K_0402_5%

R

1 2

C154 1K_0402_5%@

R

R

C112 10K_0402 _5%@

R

C113 10K_0402 _5%@

R

C114 10K_0402 _5%@

C115 10K_0402 _5%@

R

12
12

2

1

12

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

ompal Electronics, Inc.

(

(

(

3/7)_DISP/MISC/HDT

3/7)_DISP/MISC/HDT

3/7)_DISP/MISC/HDT

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

E

+

1.8VS

+

1.8VS

1

1

1

A

A

A

o

o

o

f

8 99Wednesday, May 15, 201 9

f

8 99Wednesday, May 15, 201 9

f

8 99Wednesday, May 15, 201 9

C28

S

YS_PWRGD_EC

C8

C6160

A

A

C700 0_0402_5%RS@

R

R

C701 0_0402_5%@

R

C30 0_0402_5%RS@

1

2

PU_PCIE_WAKE#

+

1.8VALW

1 2

1 2

1 2

+

3VALW

N1

I

N2

I

@

Reserve for MBDG/CRB

C1210

C
10U_0402_6.3V6M

1 2

@

1

R

C54

22K_0402_1%

2

E

C_RSMRST#

1

C

C16

1U_0201_6.3V6M

2

C14

C

0.1U_0201_10V6K

1 2

@

5

P

A

PU_PCIE_RST#

4

O

G

C4

U

A00000OH00

S

3

MC74VHC1G08DFT2G_SC70-5

A

PU_PCIE_RST#_U

A

PU_PCIE_RST#

A

PU_PCIE_RST# 27,51,52,68

A

PU_PCIE_RST#_C

A

PU_PCIE1_RST#_C

M

ain Func = CPU

1 1

A

CPI

+

3VALW

1 2

C6133 10K_0402_5%@

R

CRB use S0-rail

+

2 2

3 3

3VALW

12

C6165

R
10K_0402_1%@

A

PU_PCIE_RST#_U

+

3VS

12

R
10K_0402_1%

2

C

0.22U_0402_16V7K

1

A

PU_PCIE_RST#_C

A

PU_PCIE1_RST#_C

A

PU_PCIE_RST#_U

R

10K_0402_5% @

1 2

B

1 2

C

C7 150P_0402_50V 8J

1 2

C100 150P_0402_50V8J@

C

1 2

R

C29 33_0402_5%

1 2

C704 33_0402_5%@

R

E

C_RSMRST#58

P

BTN_OUT#58

S

YS_PWRGD_EC58

S

LP_S3#58

S

LP_S5#58,84

H

DA_SDIN056

A

PU_PCIE_RST#_R

A

PU_PCIE1_RST#_R

E

C_RSMRST#

P

BTN_OUT#

S

YS_PWRGD_EC

S

YS_RST#

A

PU_PCIE_WAKE#

S

LP_S3#

S

LP_S5#

A

GPIO10

A

GPIO23

A

GPIO12

H

DA_BIT_CLK

H

DA_SDIN0

H

DA_SDIN1

H

DA_SDIN2

H

DA_RST#

H

DA_SYNC

H

DA_SDOUT

A

GPIO7

D5

B

CIE_RST0_L/EGPIO26

P

B6

B

CIE_RST1_L/EGPIO27

P

T16

A

SMRST_L

R

R15

A

WR_BTN_L/AGPIO0

P

V6

A

WR_GOOD

P

P10

A

YS_RESET_L/AGPIO1

S

V11

A

AKE_L/AGPIO2

W

V13

A

LP_S3_L

S

T14

A

LP_S5_L

S

R8

A

0A3_GPIO/AGPIO10

S

T10

A

C_PRES/AGPIO23

A

A

N6

L

LB_L/AGPIO12

A

W8

E

GPIO42

A

R2

A

Z_BITCLK/TDM_BCLK_MIC

A

P7

A

Z_SDIN0/CODEC_GPI

A

P1

A

Z_SDIN1/SW_DATA1B/TDM_BCLK_PLAYBACK

A

P4

A

Z_SDIN2/SW_DATA2/TDM_DATA_PLAYBACK

A

P3

A

Z_RST_L/SW_DATA1A/SW_DATA3/TDM_DATA_MIC

A

R4

A

Z_SYNC/TDM_FRM_MIC

A

R3

A

Z_SDOUT/TDM_FRM_PLAYBACK

A

T2

S

W_MCLK/TDM_BCLK_BT

A

T4

S

W_DATA0/TDM_DOUT_BT

A

R6

A

GPIO7/FCH_ACP_I2S_SDIN_BT

A

P6

A

GPIO8/FCH_ACP_I2S_LRCLK_BT

@

SW PU/PD

SW PU/PD

C

UC1D

ACPI/AUDIO/I2C/GPIO/MISC

SW PU/PD
SW PU/PD

SW PU/PD
SW PU/PD

SW PU/PD
SW PU/PD

SW PU/PD

FP5 REV 0.90
P

ART 4 OF 13

F

P5_BGA_1140P

1.8V_S5

1.8V_S5

SW PU/PD

2C0_SCL/SFI0_I2C_SCL/EGPIO151

I

2C0_SDA/SFI0_I2C_SDA/EGPIO152

I

2C1_SCL/SFI1_I2C_SCL/EGPIO149

I

2C1_SDA/SFI1_I2C_SDA/EGPIO150

I

3.3V

3.3V_S5

3.3VALW input

3.3VS input

3.3VS input

3.3VS Output

3.3VS input

3.3VS input

3.3VS input

3.3VS input

G

A

GPIO41/SFI_S5_EGPIO41

E

A

GPIO39/SFI_S5_AGPIO39

A

A
A

A
A

B

2C2_SCL/EGPIO113/SCL0

I

B

2C2_SDA/EGPIO114/SDA0

I

A

2C3_SCL/AGPIO19/SCL1

I

A

2C3_SDA/AGPIO20/SDA1

I

L

SA_I2C_SCL

P

M

SA_I2C_SDA

P

A

GPIO3

A

A

GPIO4/SATAE_IFDET

A

A

GPIO5/DEVSLP0

A

A

GPIO6/DEVSLP1

A

A

ATA_ACT_L/AGPIO130

S

A

GPIO9

A

A

GPIO40

A

A

GPIO69

A

A

GPIO86

A

A

NTRUDER_ALERT

I

A

PKR/AGPIO91

S

A

LINK/AGPIO11

B

A

ENINT1_L/AGPIO89

G

B

ENINT2_L/AGPIO90

G

A

ANIN0/AGPIO84

F

A

ANOUT0/AGPIO85

F

PIO Table

D

I

2C_0_SCL
I

2C_0_SDA

I

W12
U12

I

2C_0_SCL

R13

I

2C_0_SDA

T13

I

2C_1_SCL

N8

I

2C_1_SDA

N9

S

MB_0_SCL

C20

S

MB_0_SDA

A20

I

2C_3_SCL

M9

I

2C_3_SDA

M10

16

16

T15

A

GPIO3

W10

A

GPIO4

P9

A

GPIO5

U10

D

EVSLP1

P

ANEL_OD#

V15

U7

A

GPIO9

U6

A

GPIO40

W13
W15

U14

A

PU_SPKR

U16
V8

A

GPIO11

W16

T

P_I2C_INT#_APU

D15

R18
T18

S

MB_0_SCL 23,24

S

MB_0_SDA 23,24

I

2C_3_SCL 63

I

2C_3_SDA 63

D

EVSLP1 68

P

ANEL_OD# 38

A

GPIO40 68

A

PU_SPKR 56

T

P_I2C_INT#_APU 63

DDR4

T

ouch Pad

2C_1_SCL
I

2C_1_SDA

S

MB_0_SCL

S

MB_0_SDA

I

2C_3_SCL
I

2C_3_SDA

D

EVSLP1

1 2

R

C6139 2.2K_0402_5%@

1

2

C6140 2.2K_0402_5%@

R

1 2

R

C6176 2.2K_0402_5%@

1 2

R

C6177 2.2K_0402_5%@

1 2

R

C6157 2.2K_0402_5%

1 2

C6156 2.2K_0402_5%

R

2

1

R

C6159 2.2K_0402_5%

1 2

C6158 2.2K_0402_5%

R

12

C663 10K_0402_5%@

R

A

GPIO40

RSV

H

L

12

@

R

C693

10K_0402_5%

10K_0402_5%

A

GPIO40

A

GPIO9

A

GPIO12

A

GPIO23

12

@

C692

R

10K_0402_5%

10K_0402_5%

A

GPIO9

DIS
Type1

RSVRSV

R

C6147

@

C6148

R

+

1.8VALW

+

3VS

+

3VALW

+

3VS

1

10K_0402_5%

2

1

10K_0402_5%

2

A

GPIO12

RSV

DMIC x2

@

R

C6135

R

C6136

E

12

10K_0402_5%

12

10K_0402_5%

AGPIO23

R

SV

RSV

+

@

R

C6175

@

R

C6174

3VALW

1

2

1

2

AGPIO10 AGPIO11

AGPIO3 AGPIO4AGPIO7AGPIO5

HDA

H

H

DA_SDIN1

H

DA_SDIN2

H

DA_SDIN0

DA_RST#

H

DA_BIT_CLK

H

DA_SYNC

H

DA_SDOUT

1 2

C116 33_0402_5%EMC@

H

DA_RST#_R56

H

DA_BIT_CLK_R56

H

DA_SYNC_R56

H

DA_SDOUT_R56

4 4

R

1 2

C117 33_0402_5%EMC@

R

1 2

R

C118 33_0402_5%EMC@

2

1

R

C119 33_0402_5%EMC@

2

1

R

C120 1K_04 02_5%

2

1

C121 1K_04 02_5%

R

2

1

C122 1K_04 02_5%

R

1 2

C123 1K_04 02_5%

R

2

1

R

C695 10K_0 402_5%@

1 2

C696 10K_0 402_5%@

R

R

1

C703 10K_0 402_5%@

A

2

Strap Pin

A

PU_SPI_CLK_R SYS_RST#

USE 48MHZ CRYSTAL

H

CLOCK
(Default)

U

SE 100MHZ PCIE

L

CLOCK AS
REFERENCE CLOCK

A

PU_SPI_CLK_R10

B

NORMAL RESET MODE
(Default)

SHORT RESET MODE

+

1.8VS+1.8VALW+3VALW

12

C622

R

10K_0402_5%

10K_0402_5% @

A

PU_SPI_CLK_R

S

YS_RST#

2K_0402_5% @

+

3VALW

12

12

@

@

C6137

C6145

R

R

10K_0402_5%

10K_0402_5%

A

12

R

10K_0402_5%

1

C951

C47

R

2

1

1

C929

R

R

C1703

2K_0402_5% @

2

2

C

GPIO5

A

GPIO7

12

12

@

@

C6138

C6146

R

R

10K_0402_5%

10K_0402_5%

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

2

2

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

C

C

C

D

R

10K_0402_5%

A

GPIO3

A

GPIO4

R

10K_0402_5%

ompal Secret Data

ompal Secret Data

ompal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

C6170

C6171

+

3VALW

1

1

@

@

R

C6168

10K_0402_5%

2

2

12

1

@

@

C6169

R

10K_0402_5%

2

@

C619

R

10K_0402_5%

A

GPIO10

A

GPIO11

@

R

C6134

10K_0402_5%

T

T

T

itle

itle

itle

F

F

F

P5_(4/7)_GPIO/HDA/STRAP

P5_(4/7)_GPIO/HDA/STRAP

P5_(4/7)_GPIO/HDA/STRAP

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

ustom

ustom

ustom

Date: Sheet

Date: Sheet

Date: Sheet

+

3VALW

12

12

@

C6172

R

10K_0402_5%

12

12

@

C6173

R

10K_0402_5%

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

ompal Electronics, Inc.

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

E

1

1

1

o

o

o

f

9 99Wednesday, May 15, 2019

f

9 99Wednesday, May 15, 2019

f

9 99Wednesday, May 15, 2019

A

A

A

Main Func = CPU

A

+

3VS

C

10K_0402_5%

C

10K_0402_5%

C

10K_0402_5%

C

10K_0402_5%

4

8M_X2

4

8M_X1

Y

C2

48MHZ_8PF_7V48000010

S

J10000JP00

1

797

C

3.9P_0402_50V8C

2

3

2K_X1

12

Y

C3

3

2K_X2

A

PU_USBC_SCL

A

PU_USBC_SDA

LKREQ_PCIE#0

LKREQ_PCIE#2
LKREQ_PEG#4
LKREQ_PCIE#3

1 1

R
R
R

C1696
C1697

2

1

2

1

2

1

R

C1695

2

1

C6149

48MHz CRYSTAL

1 2

R

C939

1M_0402_5%

J10000PW00

12

2

4.7K_0402_5%

2

4.7K_0402_5%

1

1

4

4

1

C682

C
10P_0402_50V8J

2

2

2

3

3

1

C

796

3.9P_0402_50V8C

2

2 2

3

2.768KHz CRYSTAL

S

32.768KHZ_9PF_X1A000141000200

R

C914

20M_0402_5%

1

C

C686

12P_0402_50V8J

2

U

SB Function

+

1.8VALW

1

C94

3 3

4 4

R

1

R

C95

M.2 SSD1

M.2 WLAN
LAN
DGPU

M

.2 SSD1

WLAN

LAN

DGPU

CAMERA

T

ype-A MB CHG

Type-A MB

T

ype-C MB

Type-A SUB

U

SB Hub

B

68CLKREQ_PCIE#0

52CLKREQ_PCIE#2
51CLKREQ_PCIE#3
28CLKREQ_PEG#4

68CLK_PCIE_P0
68CLK_PCIE_N0

52CLK_PCIE_P2
52CLK_PCIE_N2

51CLK_PCIE_P3
51CLK_PCIE_N3

27CLK_PEG_P4
27CLK_PEG_N4

38USB20_P0
38USB20_N0

71USB20_P1
71USB20_N1

72USB20_P2
72USB20_N2

43USB20_P3
43USB20_N3

73USB20_P4
73USB20_N4

52USB20_P5
52USB20_N5

115 TP@

T

C

LKREQ_PCIE#0

C

LKREQ_PCIE#2

C

LKREQ_PCIE#3

C

LKREQ_PEG#4

C

LK_PCIE_P0

C

LK_PCIE_N0

C

LK_PCIE_P2

C

LK_PCIE_N2

C

LK_PCIE_P3

C

LK_PCIE_N3

C

LK_PEG_P4

C

LK_PEG_N4

4

8M_X1

4

8M_X2

R

TCCLK

3

2K_X1

3

2K_X2

U

SB20_P0

U

SB20_N0

U

SB20_P1

U

SB20_N1

U

SB20_P2

U

SB20_N2

U

SB20_P3

U

SB20_N3

U

SB20_P4

U

SB20_N4

U

SB20_P5

U

SB20_N5

A

PU_USBC_SCL

A

PU_USBC_SDA

V18

A

LK_REQ0_L/SATA_IS0_L/SATA_ZP0_L/AGPIO92

C

N19

A

LK_REQ1_L/AGPIO115

C

P19

A

LK_REQ2_L/AGPIO116

C

T19

A

LK_REQ3_L/SATA_IS1_L/SATA_ZP1_L/EGPIO131

C

U19

A

LK_REQ4_L/OSCIN/EGPIO132

C

W18

A

LK_REQ5_L/EGPIO120

C

W19

A

LK_REQ6_L/EGPIO121

C

K1

A

PP_CLK0P

G

K3

A

PP_CLK0N

G

M2

A

PP_CLK1P

G

M4

A

PP_CLK1N

G

M1

A

PP_CLK2P

G

M3

A

PP_CLK2N

G

L2

A

PP_CLK3P

G

L4

A

PP_CLK3N

G

N2

A

PP_CLK4P

G

N4

A

PP_CLK4N

G

N3

A

PP_CLK5P

G

P2

A

PP_CLK5N

G

J2

A

PP_CLK6P

G

J4

A

PP_CLK6N

G

J3

A

8M_OSC

4

B3

B

48M_X1

X

A5

B

48M_X2

X

F8

A

SVD_76

R

F9

A

SVD_77

R

W14

A

TCCLK

R

Y1

A

32K_X1

X

Y4

A

32K_X2

X

@

E7

A

U

E6

A

U

G10

A

U

G9

A

U

F12

A

U

F11

A

U

E10

A

U

E9

A

U

J12

A

U

J11

A

U

D9

A

U

D8

A

U

M6

A

U

M7

A

U

K10

A

U

K9

A

U

L9

A

U

L8

A

U

W7

A

A

T12

A

A

@

M.2 WLAN/BT

GBE LAN

WWANM.2

M.2 WLAN

EVAL SLOT GFX

SB_0_DP0

SB_0_DM0

SB_0_DP1

SB_0_DM1

SB_0_DP2

SB_0_DM2

SB_0_DP3

SB_0_DM3

SB_1_DP0

SB_1_DM0

SB_1_DP1

SB_1_DM1

SBC_I2C_SCL

SBC_I2C_SDA

SB_OC0_L/AGPIO16

SB_OC1_L/AGPIO17

SB_OC2_L/AGPIO18

SB_OC3_L/AGPIO24

GPIO14/USB_OC4_L

GPIO13/USB_OC5_L

CLK/LPC/EMMC/SD/SPI/eSPI/UART

SW PU/PD

X4 DT SLOT PCIE

SSD PCIE M.2

Controller 0

Controller 1

SW PU/PD

C

FP5 REV 0.90

ART 5 OF 13

P

FP5 REV 0.90

P

UC1E

P5_BGA_1140P

F

UC1J

USB

Port 0

Port 3

ART 10 OF 13

P5_BGA_1140P

F

SW PU/PD

SW PU/PD

SW PU/PD

SW PU/PD

SW PU/PD

SW PU/PD

GPIO70/SD_CLK

E

PC_PD_L/SD_CMD/AGPIO21

L

AD0/SD_DATA0/EGPIO104

L

AD1/SD_DATA1/EGPIO105

L

AD2/SD_DATA2/EGPIO106

L

AD3/SD_DATA3/EGPIO107

L

PCCLK0/EGPIO74

L

PC_CLKRUN_L/AGPIO88

L

PCCLK1/EGPIO75

L

ERIRQ/AGPIO87

S

FRAME_L/EGPIO109

L

PC_RST_L/SD_WP_L/AGPIO32

L

GPIO68/SD_CD

A

PC_PME_L/SD_PWR_CTRL/AGPIO22

L

PI_ROM_REQ/EGPIO67

S

PI_ROM_GNT/AGPIO76

S

SPI_RESET_L/KBRST_L/AGPIO129

E

SPI_ALERT_L/LDRQ0_L/EGPIO108

E

PI_CLK/ESPI_CLK

S

PI_DI/ESPI_DATA

S

PI_WP_L/ESPI_DAT2

S

PI_HOLD_L/ESPI_DAT3

S

PI_CS1_L/EGPIO118

S

PI_CS2_L/ESPI_CS_L/AGPIO30

S

PI_CS3_L/AGPIO31

S

PI_TPM_CS_L/AGPIO29

S

ART0_RXD/EGPIO136

U

ART0_TXD/EGPIO138

U

ART0_RTS_L/UART2_RXD/EGPIO137

U

ART0_CTS_L/UART2_TXD/EGPIO135

U

ART0_INTR/AGPIO139

U

GPIO141/UART1_RXD

E

GPIO143/UART1_TXD

E

GPIO142/UART1_RTS_L/UART3_RXD

E

GPIO140/UART1_CTS_L/UART3_TXD

E

GPIO144/UART1_INTR

A

U

SBC0_A2/USB_0_TXP0/DP3_TXP2

U

SBC0_A3/USB_0_TXN0/DP3_TXN2

U

SBC0_B11/USB_0_RXP0/DP3_TXP3

U

SBC0_B10/USB_0_RXN0/DP3_TXN3

U

SBC0_B2/DP3_TXP1

U

SBC0_B3/DP3_TXN1

U

SBC0_A11/DP3_TXP0

U

SBC0_A10/DP3_TXN0

USB_0_TXP1

Port 1

USB_0_TXN1

USB_0_RXP1

USB_0_RXN1

USB_0_TXP2

Port 2

USB_0_TXN2

USB_0_RXP2

USB_0_RXN2

USBC1_A2/USB_0_TXP3/DP2_TXP2

SBC1_A3/USB_0_TXN3/DP2_TXN2

U

SBC1_B11/USB_0_RXP3/DP2_TXP3

U

SBC1_B10/USB_0_RXN3/DP2_TXN3

U

SBC1_B2/DP2_TXP1

U

SBC1_B3/DP2_TXN1

U

SBC1_A11/DP2_TXP0

U

SBC1_A10/DP2_TXN0

U

SB_1_TXP0

U

Port 4

SB_1_TXN0

U

SB_1_RXP0

U

SB_1_RXN0

U

D

R

C602

33_0402_5%

LPC_RST_A#

1 2

E

C_SCI#

D13

B

B14

B

L

PCPD#

L

PC_AD0

B12

B

L

PC_AD1

C11

B

L

PC_AD2

B15

B

L

PC_AD3

C15

B

L

PC_CLK0

A15

B

C13

B

L

PC_CLK1

B13

B

C12

B

S

ERIRQ

L

PC_FRAME#

A12

B

L

PC_RST_A#

D11

B

A11

B

E

C_SCI#

A13

B

C8

B

B8

B

B11

B

K

BRST#

E

SPI_ALERT_L

C6

B

A

PU_SPI_CLK

B7

B

A

PU_SPI_MISO

A9

B

A

PU_SPI_MOSI

B10

B

PI_DO

S

A

PU_SPI_WP#

A10

B

A

PU_SPI_HOLD#

C10

B

A

PU_SPI_CS#1

C9

B

A8

B

A6

B

A

PU_SPI_TPMCS#

D8

B

U

ART_0_ARXD_DTXD

A16

B

U

ART_0_ATXD_DRXD

B18

B

C17

B

A18

B

D18

B

P

E_GPIO1

C18

B

D

GPU_PWRGOOD

A17

B

C16

B

P

E_GPIO0

B19

B

B16

B

A

D2

A

D4

A

C2

A

C4

A

F4

A

F2

A

E3

A

E1

U

SB3_ATX_DRX_P1

AG3

U

SB3_ATX_DRX_N1

AG1

U

SB3_ARX_DTX_P1

AJ9

U

SB3_ARX_DTX_N1

AJ8

U

SB3_ATX_DRX_P2

AG4

U

SB3_ATX_DRX_N2

AG2

U

SB3_ARX_DTX_P2

G7

A

U

SB3_ARX_DTX_N2

AG6

U

SB3_ATX_DRX_P3

AA2

U

SB3_ATX_DRX_N3

A4

A

U

SB3_ARX_DTX_P3

1

Y

U

SB3_ARX_DTX_N3

3

Y

C1

A

C3

A

B2

A

B4

A

H4

A

H2

A

K7

A

K6

A

R

C101

R

C102

R

C103

R

C104

C449

R

103TP@

T

1

1
1
1

1

S

ERIRQ 58
L

E

C_SCI# 58

K

BRST# 58

1

R

C74

EMC@210_0402_5%

U

P

E_GPIO1 37

D

GPU_PWRGOOD 27,92,94

P

E_GPIO0 27

U
U

U
U

U
U

2

10_0402_5%

2

10_0402_5%

2

10_0402_5%

2

10_0402_5%

2

22_0402_5%

PC_FRAME# 58

ART_0_ARXD_DTXD 52
U

ART_0_ATXD_DRXD 52

U

SB3_ATX_DRX_P1 71

U

SB3_ATX_DRX_N1 71

SB3_ARX_DTX_P1 71
SB3_ARX_DTX_N1 7 1

U

SB3_ATX_DRX_P2 72

U

SB3_ATX_DRX_N2 72

SB3_ARX_DTX_P2 72
SB3_ARX_DTX_N2 7 2

U

SB3_ATX_DRX_P3 42

U

SB3_ATX_DRX_N3 42

SB3_ARX_DTX_P3 42
SB3_ARX_DTX_N3 4 2

L

PC_AD0_R 58

L

PC_AD1_R 58

L

PC_AD2_R 58

L

PC_AD3_R 58

L

PC_CLK0_EC 58

A

PU_SPI_CLK_R 9

8

Type-A MB CHG

Type-A MB

T

ype-C MB

P

E_GPIO1

E

SPI_ALERT_L

L

PC_CLK1

MB SPI ROM

A

PU_SPI_CS#1

A

PU_SPI_MISO

A

PU_SPI_WP#

A

PU_SPI_CLK_R

2

R

C6154

2

C6166

R

2

R

C6181

R

C6180

A

PU_SPI_MISO

A

PU_SPI_WP#

A

PU_SPI_HOLD#

A

PU_SPI_CS#1

A

PU_SPI_TPMCS#

U

C7

1

C

S#

2

OLD#(IO3)

O(IO1)

H

D

3

P#(IO2)

W

4

ND

G

GD25LB64CSIGR_SOIC_8P

S

A00008K400

1

@EMC@

C680

R
10_0402_5%

1

2

2

R

R

R

R

R

+

1.8VALW

CC

V

C

I(IO0)

D

CC615
150P_0402_50V8J

1

10K_0402_5%

1

10K_0402_5%@

1

10K_0402_5%

1

1

C1706

1

C640

1

C642

1

C639

1

C646

8
7
6

LK

5

@EMC@

1 2

2

C

C636

10P_0402_50V8J

E

10K_0402_5%@

R

C1672

0_0603_5%

1

RS@

+

SPI_VCC

A

PU_SPI_HOLD#

A

PU_SPI_CLK_R

A

PU_SPI_MOSI

LPC_RST# 58

+

3VALW

+

3VS

2

10K_0402_5%@

2

10K_0402_5%

2

10K_0402_5%

2

10K_0402_5%

2

10K_0402_5%@

2

+

SPI_VCC

+

SPI_VCC

@

2

C635

C

0.1U_0201_10V6K

1

S

S

S

eeecccuuurrriiitttyyy CCClllaaassssssiiifffiiicccaaattt iiiooonnn

I

I

I

ssssssuuueeeddd DDDaaattteee

T

T

T

HHHIIISSS SSSHHHEEEEEETTT OOOFFF EEENNNGGGIIINNNEEEEEERRRIIINNNGGG DDDRRRAAAWWWIIINNNGGG IIISSS TTTHHHEEE PPPRRROOOPPPRRRIIIEEETTTAAARRRYYY PPPRRROOOPPPEEERRRTTTYYY OOOFFF CCCOOOMMMPPPAAALLL EEELLLEEECCCTTTRRROOONNNIIICCCSSS,,, IIINNNCCC... AAANNNDDD CCCOOONNNTTTAAAIIINNNSSS CCCOOONNNFFFIIIDDDEEENNNTTTIIIAAALLL
AAANNNDDD TTTRRRAAADDDEEE SSSEEECCCRRREEETTT IIINNNFFFOOORRRMMMAAATTTIIIOOONNN... TTTHHHIIISSS SSSHHHEEEEEETTT MMMAAAYYY NNNOOOTTT BBBEEE TTTRRRAAANNNSSSFFFEEERRREEEDDD FFFRRROOOMMM TTTHHHEEE CCCUUUSSSTTTOOODDDYYY OOOFFF TTTHHHEEE CCCOOOMMMPPPEEETTTEEENNNTTT DDDIIIVVVIIISSSIIIOOONNN OOOFFF RRR&&&DDD
DDDEEEPPPAAARRRTTTMMMEEENNNTTT EEEXXXCCCEEEPPPTTT AAASSS AAAUUUTTTHHHOOORRRIIIZZZEEEDDD BBBYYY CCCOOOMMMPPPAAALLL EEELLLEEECCCTTTRRROOONNNIIICCCSSS,,, IIINNNCCC... NNNEEEIIITTTHHHEEERRR TTTHHHIIISSS SSSHHHEEEEEETTT NNNOOORRR TTTHHHEEE IIINNNFFFOOORRRMMMAAATTTIIIOOONNN IIITTT CCCOOONNNTTTAAAIIINNNSSS

A

B

C

MMMAAAYYY BBBEEE UUUSSSEEEDDD BBBYYY OOORRR DDDIIISSSCCCLLLOOOSSSEEEDDD TTTOOO AAANNNYYY TTTHHHIIIRRRDDD PPPAAARRRTTTYYY WWWIIITTTHHHOOOUUUTTT PPPRRRIIIOOORRR WWWRRRIIITTTTTTEEENNN CCCOOONNNSSSEEENNNTTT OOOFFF CCCOOOMMMPPPAAALLL EEELLLEEECCCTTTRRROOONNNIIICCCSSS,,, IIINNNCCC...

2

2

2

000111888/// 111222///111888 222000111999///111222///111888

C

C

C

ooommmpppaaalll SSSeeecccrrreeettt DDDaaatttaaa

DDDeeeccciiippphhheeerrreeeddd DDDaaattt eee

D

C

C

C

T

T

T

iiitttllleee

SSSiiizzzeee DDDooocccuuummmeeennnttt NNNuuummmbbbeeerrr RRReeevvv

C

C

C

DDDaaattteee::: SSShhheeeeeettt

ooommmpppaaalll EEEllleeeccctttrrrooonnniiicccsss,,, IIInnnccc...

F

F

F

PPP555___(((555///777)))___CCCLLLKKK///UUUSSSBBB///SSSPPPIII///LLLPPPCCC

uuu ssstttooommm

F

F

F

HHH555000PPP MMM///BBB LLLAAA---HHH999000111PPP

E

o

o

o

111 000 999999WWWeeedddnnneeesssdddaaayyy,,, MMMaaayyy 111555,,, 222000111999

fff

1

1

1

AAA

A

M

ain Func = CPU

B

C

D

E

UC1F

T

o=1.5V

S

C8

A000066U00

V

out

G

ND

680P_0402_ 50V7K

V

EDC: 70A

in

DC: 53A

1

C

C120

SCL/MBDG:
16*22uF (BU)
1*180pF (BU)

+

RTCVCC

1

2

+

APU_CORE

D

C1

1

CHN202UPT _SC70-3

+

APU_CORE Cap place at Power Side

+

RTCBATT

J

RTC1

1

1

2

2

3

G

ND

4

G

ND

ACES_50271-00 20N-001

CONN@

S

P02000RO00

3

R

C6161

1K_0402_5%

1 2

+

RTCBATT

+

CHGRTC

2

TDC: 10A

+

APU_CORE_SOC

SCL/MBDG:
7*22uF (BU)
1*1uF (BU)

1 1

+APU_CORE_SOC Cap
place at Power Side

+

1.2V

C

C

C

C1059 22U_0603_6.3V6M

1

2

C
C1207 22U_0603_6.3V6M

C1060 22U_0603_6.3V6M

C1061 22U_0603_6.3V6M

1

2

+

VDDIO_AUDIO

C
C1192 1U_0201_6.3V6M

1

2

1

2

1

2

C
C1062 22U_0603_6.3V6M

1

2

C

C
C1063 22U_0603_6.3V6M

C1163 22U_0603_6.3V6M

1

1

2

2

SCL/MBDG:
1 *22uF (BO)
1*1uF (BU)

C

C

C
C1057 22U_0603_6.3V6M

C1058 22U_0603_6.3V6M

C1008 22U_0603_6.3V6M

1

1

1

2

2

2

2 2

A

ll BU(on bottom side under SOC)

+

1.8VS

R

C1677

0_0402_5%

2

1

RS@

1*180pF (BU)

SCL/MBDG:
9*22uF (BU)

+

1.2V

C

C

C

C

C1165 1U_0201_6.3V6M

C1093 180P_0402_50V8J

C1164 1U_0201_6.3V6M

1

1

1

2

2

2

+

3VS

R

C1676

0_0402_5%

1

RS@

C

C

C
C1078 0.22U_0402_16V7K

C1079 0.22U_0402_16V7K

C1081 0.22U_0402_16V7K

C1082 0.22U_0402_16V7K

1

1

1

1

2

2

2

2

A

CROSS VDDIO AND VSS SPLIT

SCL/MBDG:
1 *22uF (BO)
2*1uF (BO+BU)

+

3VS_APU

2

C

C

C

C1208 1U_0201_6.3V6M

C1137 22U_0603_6.3V6M

C1209 1U_0201_6.3V6M

1

1

1

2

2

2

2*1uF (BU)
4*0.22uF
1*180pF (BU)
2*180pF

C

C
C1167 180P_0402_50V8J

C1166 180P_0402_50V8J

1

1

2

2

+

+

B

O BU BUBO BO

3 3

+

1.8VS

C
C1189 22U_0603_6.3V6M

1

2

B

O

+

0.9VS

C

C

C1169 22U_0603_6.3V6M

C1168 22U_0603_6.3V6M

1

1

4 4

2

2

C

C
C1191 1U_0201_6.3V6M

C1190 1U_0201_6.3V6M

1

2

BO BU

C
C1170 1U_0201_6.3V6M

1

2

C
C1171 1U_0201_6.3V6M

1

2

SCL/MBDG:
1 *22uF (BO)
2*1uF (BO+BU)

C

C

C1177 1U_0201_6.3V6M

C1172 1U_0201_6.3V6M

1

1

2

2

C

C
C1187 1U_0201_6.3V6M

C1188 1U_0201_6.3V6M

1

1

2

2

1

2

SCL/MBDG:
1 *22uF (BO)
2*1uF (BO+BU)

SCL/MBDG:
2 *22uF (BO)
8*1uF (BOx4+BUx4)
1*180pF (BU)

+

3VALW

C
C1183 22U_0603_6.3V6M

+

0.9VALW

1

2

B

O BUBO

C
C1179 22U_0603_6.3V6M

1

2

+

1.8VALW

C
C1186 22U_0603_6.3V6M

1

2

B

O BUBO

C

C

C

C

C

C1174 1U_0201_6.3V6M

C1175 1U_0201_6.3V6M

C1173 1U_0201_6.3V6M

C1176 1U_0201_6.3V6M

1

1

2

2

C1178 180P_0402_50V8J

1

1

1

2

2

2

SCL/MBDG:
1 *22uF (BO)
2*1uF (BO+BU)

C

C
C1184 1U_0201_6.3V6M

C1185 1U_0201_6.3V6M

1

1

2

2

SCL/MBDG:
1 *22uF (BO)
3*1uF (BOx1+BUx2)

C

C

C
C1181 1U_0201_6.3V6M

C1180 1U_0201_6.3V6M

C1182 1U_0201_6.3V6M

1

1

1

2

2

2

+

EDC: 13A

TDC: 6A

+

1.2V

TDC :0.2A

+

VDDIO_AUDIO

TDC :0.25A

3VS_APU

TDC :2A

+

1.8VS

TDC :0.5A

1.8VALW

TDC :0.25A

+

3VALW

TDC :1A

0.9VALW

TDC :4A

+

0.9VS

TDC :4.5uA

+

RTC_APU_R

R

TC OF APU

close to UC1

C

C166

0.22U_0402 _16V7K

+

RTC_APU_R

1

2

A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A

A

A

A

A

A

A

A

A
A
A
A

A

W

=20mils

C

C923

1U_0201_6 .3V6M

M
M
M
N
N
N
P
P
R
R
T
U
U

V
W
W

Y

T

V
W
W

Y

Y

Y

A20

A23

A26

A28

A32

C20

C22

C25

C28

D23

D26

D28

D32

E20

E22

E25

E28

F23

F26

F28

F32

G20

G22

G25

G28

J20

A

J23

A

J26

A

J28

A

J32

A

K28

L28

A

L32

A

P12

L18

A

M17

L20

A

M19

L19

A

M18

L17

A

M16

L14

A

L15

A

M14

L13

A

M12

M13

N12

N13

T11

15
18
19
16
18
20
17
19
18
20
19
18
20
19
18
20
19

32
28
28
32
22
25
28

1

2

DDCR_SOC_1

V

DDCR_SOC_2

V

DDCR_SOC_3

V

DDCR_SOC_4

V

DDCR_SOC_5

V

DDCR_SOC_6

V

DDCR_SOC_7

V

DDCR_SOC_8

V

DDCR_SOC_9

V

DDCR_SOC_10

V

DDCR_SOC_11

V

DDCR_SOC_12

V

DDCR_SOC_13

V

DDCR_SOC_14

V

DDCR_SOC_15

V

DDCR_SOC_16

V

DDCR_SOC_17

V

DDIO_MEM_S3_1

V

DDIO_MEM_S3_2

V

DDIO_MEM_S3_3

V

DDIO_MEM_S3_4

V

DDIO_MEM_S3_5

V

DDIO_MEM_S3_6

V

DDIO_MEM_S3_7

V

DDIO_MEM_S3_8

V

DDIO_MEM_S3_9

V

DDIO_MEM_S3_10

V

DDIO_MEM_S3_11

V

DDIO_MEM_S3_12

V

DDIO_MEM_S3_13

V

DDIO_MEM_S3_14

V

DDIO_MEM_S3_15

V

DDIO_MEM_S3_16

V

DDIO_MEM_S3_17

V

DDIO_MEM_S3_18

V

DDIO_MEM_S3_19

V

DDIO_MEM_S3_20

V

DDIO_MEM_S3_21

V

DDIO_MEM_S3_22

V

DDIO_MEM_S3_23

V

DDIO_MEM_S3_24

V

DDIO_MEM_S3_25

V

DDIO_MEM_S3_26

V

DDIO_MEM_S3_27

V

DDIO_MEM_S3_28

V

DDIO_MEM_S3_29

V

DDIO_MEM_S3_30

V

DDIO_MEM_S3_31

V

DDIO_MEM_S3_32

V

DDIO_MEM_S3_33

V

DDIO_MEM_S3_34

V

DDIO_MEM_S3_35

V

DDIO_MEM_S3_36

V

DDIO_MEM_S3_37

V

DDIO_MEM_S3_38

V

DDIO_MEM_S3_39

V

DDIO_MEM_S3_40

V

DDIO_AUDIO

V

DD_33_1

V

DD_33_2

V

DD_18_1

V

DD_18_2

V

DD_18_S5_1

V

DD_18_S5_2

V

DD_33_S5_1

V

DD_33_S5_2

V

DDP_S5_1

V

DDP_S5_2

V

DDP_S5_3

V

DDP_1

V

DDP_2

V

DDP_3

V

DDP_4

V

DDP_5

V

DDBT_RTC_G

V

@

0_0603_5%

POWER

FP5 REV 0.90

ART 6 OF 13

P

P5_BGA_1140P

F

R

C6164

1K_0402_5%

1 2

12

@

0.1U_0201_ 10V6K

C

C119

C

LRP1

+

RTC_APU

V

DDCR_1

V

DDCR_2

V

DDCR_3

V

DDCR_4

V

DDCR_5

V

DDCR_6

V

DDCR_7

V

DDCR_8

V

DDCR_9

V

DDCR_10

V

DDCR_11

V

DDCR_12

V

DDCR_13

DDCR_14

V

V

DDCR_15

DDCR_16

V

DDCR_17

V

DDCR_18

V

DDCR_19

V

DDCR_20

V

DDCR_21

V

DDCR_22

V

DDCR_23

V

DDCR_24

V

DDCR_25

V

DDCR_26

V

DDCR_27

V

DDCR_28

V

DDCR_29

V

DDCR_30

V

DDCR_31

V

DDCR_32

V

DDCR_33

V

DDCR_34

V

DDCR_35

V

DDCR_36

V

DDCR_37

V

DDCR_38

V

DDCR_39

V

DDCR_40

V

DDCR_41

V

DDCR_42

V

DDCR_43

V

DDCR_44

V

DDCR_45

V

DDCR_46

V

DDCR_47

V

DDCR_48

V

DDCR_49

V

DDCR_50

V

DDCR_51

V

DDCR_52

V

DDCR_53

V

DDCR_54

V

DDCR_55

V

DDCR_56

V

DDCR_57

V

DDCR_58

V

DDCR_59

V

DDCR_60

V

DDCR_61

V

DDCR_62

V

DDCR_63

V

DDCR_64

V

DDCR_65

V

DDCR_66

V

DDCR_67

V

DDCR_68

V

DDCR_69

V

DDCR_70

V

DDCR_71

V

DDCR_72

V

DDCR_73

V

DDCR_74

V

DDCR_75

V

DDCR_76

V

DDCR_77

V

DDCR_78

V

DDCR_79

V

DDCR_80

V

DDCR_81

V

DDCR_82

V

DDCR_83

V

1

2

G

7

G

10

G

12

G

14

H

8

H

11

H

15

K

7

K

12

K

14

L

8

M

7

M

10

N

14

P

7

P

10
13

P

15

P

8

R

14

R

16

R

7

T

10

T

13

T

15

T

17

T

14

U

16

U

13

V

15

V

17

V

7

W

10

W

14

W

16

W

8

Y

13

Y

15

Y

17

Y

A7

A

A10

A

A14

A

A16

A

A18

A

B13

A

B15

A

B17

A

B19

A

C14

A

C16

A

C18

A

D7

A

D10

A

D13

A

D15

A

D17

A

D19

A

E8

A

E14

A

E16

A

E18

A

F7

A

F10

A

F13

A

F15

A

F17

A

F19

A

G14

A

G16

A

G18

A

H13

A

H15

A

H17

A

H19

A

J7

A

J10

A

J14

A

J16

A

J18

A

K13

A

K15

A

K17

A

K19

A

V

U

AP2138N-1.5TR G1_SOT23-3

3

2

B

Ox4

N

eed OPEN

BUx4 BO BU

A

B

UBO

B

O

B

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

for Clear CMOS

C

C

C

ompal Secret Data

ompal Secret Data

2

2

2

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

ompal Secret Data

D

D

D

eciphered Date

eciphered Date

eciphered Date

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

ustom

ustom

ustom

Date: Sheet

Date: Sheet

D

Date: Sheet

ompal Electronics, Inc.

(

(

(

6/7)_PWR

6/7)_PWR

6/7)_PWR

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

E

o

o

o

11 99Wednesday, May 15, 201 9

11 99Wednesday, May 15, 201 9

11 99Wednesday, May 15, 201 9

1

1

1

A

A

A

f

f

f

5

M

ain Func = CPU

N

12

V

A

3

V

A

5

V

A

7

V

A

10

V

A

12

V

A

14

V

A

16

V

A

19

D D

C C

B B

V

A

21

V

A

23

V

A

26

V

A

30

V

C

3

V

C

32

V

D

16

V

D

18

V

D

20

V

E

7

V

E

8

V

E

10

V

E

11

V

E

12

V

E

13

V

E

14

V

E

15

V

E

16

V

E

18

V

E

19

V

E

20

V

E

21

V

E

22

V

E

23

V

E

25

V

E

26

V

E

27

V

F

5

V

F

28

V

G

1

V

G

5

V

G

16

V

G

19

V

G

21

V

G

23

V

G

26

V

G

28

V

G

32

V

H

5

V

H

13

V

H

18

V

H

20

V

H

22

V

H

25

V

H

28

V

K

1

V

K

5

V

K

16

V

K

19

V

K

21

V

K

22

V

K

26

V

K

28

V

@

SS_316

SS_1

SS_2

SS_3

SS_4

SS_5

SS_6

SS_7

SS_8

SS_9

SS_10

SS_11

SS_12

SS_13

SS_14

SS_15

SS_16

SS_17

SS_18

SS_19

SS_20

SS_21

SS_22

SS_23

SS_24

SS_25

SS_26

SS_27

SS_28

SS_29

SS_30

SS_31

SS_32

SS_33

SS_34

SS_35

SS_36

SS_37

SS_38

SS_39

SS_40

SS_41

SS_42

SS_43

SS_44

SS_45

SS_46

SS_47

SS_48

SS_49

SS_50

SS_51

SS_52

SS_53

SS_54

SS_55

SS_56

SS_57

SS_58

SS_59

SS_60

SS_61

GND

FP5 REV 0.90
P

ART 7 OF 13

F

UC1G

SS_62

V

SS_63

V

SS_64

V

SS_65

V

SS_66

V

SS_67

V

SS_68

V

SS_69

V

V

SS_70

V

SS_71

V

SS_72

V

SS_73

V

SS_74

V

SS_75

V

SS_76

V

SS_77

V

SS_78

V

SS_79

V

SS_80

V

SS_81

V

SS_82

V

SS_83

V

SS_84

V

SS_85

V

SS_86

V

SS_87

V

SS_88

V

SS_89

V

SS_90

V

SS_91

V

SS_92

V

SS_93

V

SS_94

V

SS_95

V

SS_96

V

SS_97

V

SS_98

V

SS_99

V

SS_100

V

SS_101

V

SS_102

V

SS_103

V

SS_104

V

SS_105

V

SS_106

V

SS_107

V

SS_108

V

SS_109

V

SS_110

V

SS_111

V

SS_112

V

SS_113

V

SS_114

V

SS_115

V

SS_116

V

SS_117

V

SS_118

V

SS_119

V

SS_120

V

SS_121

V

SS_122

V

SS_123

P5_BGA_ 1140P

32

K

5

L

13

L

15

L

18

L

20

L

25

L

28

L

M

1

M

5

M

12

M

21

M

23

M

26

M

28

M

32

N

4

N

5

N

8

N

11

N

13

N

15

N

17

N

19

N

22

N

25

N

28

P

1

P

5

P

14

P

16

P

18

P

20

P

23

P

26

P

28

P

32

R

5

R

11

R

12

R

13

R

15

R

17

R

19

R

22

R

25

R

28

R

30

T

1

T

5

T

14

T

16

T

18

T

20

T

23

T

26

T

28

U

13

U

15

U

17

U

19

V

5

UC1M

18

A

AM0_CSI2_CLOCKP

C

18

C

AM0_CSI2_CLOCKN

C

15

A

AM0_CSI2_DATAP0

C

15

C

AM0_CSI2_DATAN0

C

16

B

AM0_CSI2_DATAP1

C

16

C

AM0_CSI2_DATAN1

C

19

C

AM0_CSI2_DATAP2

C

18

B

AM0_CSI2_DATAN2

C

17

B

AM0_CSI2_DATAP3

C

17

D

AM0_CSI2_DATAN3

C

12

D

AM1_CSI2_CLOCKP

C

12

B

AM1_CSI2_CLOCKN

C

13

C

AM1_CSI2_DATAP0

C

13

A

AM1_CSI2_DATAN0

A A

11

B

12

C

13

J

C

AM1_CSI2_DATAP1

C

AM1_CSI2_DATAN1

C

SVD_6

R

@

5

CAMERAS

FP5 REV 0.90

ART 13 OF 13

P

F

P5_BGA_ 1140P

AM0_CLK

C

AM0_I2C_SCL

C

AM0_I2C_SDA

C

AM0_SHUTDOWN

C

AM1_CLK

C

AM1_I2C_SCL

C

AM1_I2C_SDA

C

AM1_SHUTDOWN

C

AM_PRIV_LED

C

AM_IR_ILLU

C

B

D
C

B

B

A
C

D

D
D

4

8

V

11

V

12

V

14

V

16

V

18

V

20

V

22

V

25

V

1

W

5

W

13

W

15

W

17

W

19

W

23

W

26

W

5

Y

11

Y

12

Y

14

Y

16

Y

18

Y

20

Y

A1

A

A5

A
A13

A

A15

A

A17

A

A19

A

B14

A

B16

A

B18

A

B20

A

C5

A

C8

A

C11

A

C12

A

C13

A

C15

A

C17

A

C19

A

D1

A

D5

A

D14

A

D16

A

D18

A

D20

A

E5

A
E11

A

E12

A

E13

A

E15

A

E17

A

E19

A

F1

A

F5

A
F14

A

F16

A

F18

A

F20

A

G5

A

@

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

SS_124

SS_125

SS_126

SS_127

SS_128

SS_129

SS_130

SS_131

SS_132

SS_133

SS_134

SS_135

SS_136

SS_137

SS_138

SS_139

SS_140

SS_141

SS_142

SS_143

SS_144

SS_145

SS_146

SS_147

SS_148

SS_149

SS_150

SS_151

SS_152

SS_153

SS_154

SS_155

SS_156

SS_157

SS_158

SS_159

SS_160

SS_161

SS_162

SS_163

SS_164

SS_165

SS_166

SS_167

SS_168

SS_169

SS_170

SS_171

SS_172

SS_173

SS_174

SS_175

SS_176

SS_177

SS_178

SS_179

SS_180

SS_181

SS_182

SS_183

SS_184

SS_185

3

UC1H

GND

FP5 REV 0.90

ART 8 OF 13

P

F

V

SS_186

V

SS_187

V

SS_188

V

SS_189

V

SS_190

V

SS_191

V

SS_192

V

SS_193

V

SS_194

V

SS_195

V

SS_196

V

SS_197

V

SS_198

V

SS_199

V

SS_200

V

SS_201

V

SS_202

V

SS_203

V

SS_204

V

SS_205

V

SS_206

V

SS_207

V

SS_208

V

SS_209

V

SS_210

V

SS_211

V

SS_212

V

SS_213

V

SS_214

V

SS_215

V

SS_216

V

SS_217

V

SS_218

V

SS_219

V

SS_220

V

SS_221

V

SS_222

V

SS_223

V

SS_224

V

SS_225

SS_226

V

SS_227

V

SS_228

V

SS_229

V

SS_230

V

SS_231

V

SS_232

V

SS_233

V

SS_234

V

SS_235

V

SS_236

V

SS_237

V

SS_238

V

SS_239

V

SS_240

V

SS_241

V

SS_242

V

SS_243

V

SS_244

V

SS_245

V

SS_246

V

SS_247

V

P5_BGA_ 1140P

2

1

UC1K

A

G8

A

G11

A

G12

A

G13

A

G15

A

G17

A

G19

A

H14

A

H16

A

H18

A

H20

A

J1

A

J5

A

J13

A

J15

A

J17

A

J19

A

K5

A

K8

A

K11

A

K12

A

K14

A

K16

A

K18

A

K20

A

K22

A

K25

A

L1

A

L5

A

L7

A

L10

A

L12

A

L16

A

L23

A

L26

A

M5

A

M8

A

M15

A

M20

A

M22
M25

A

M28

A

N1

A

N5

A

N7

A

N10

A

N15

A

N18

A

N21

A

N23

A

N26

A

N28

A

N32

A

P5

A

P8

A

P13

A

P15

A

P18

A

P20

A

P25

A

P28

A

R1

A

A

R5

A

R7

A

R12

A

R14

A

R16

A

R19

A

R21

A

R26

A

R28

A

R32
A

U5

A

U8

A

U11

A

U13

A

U15

A

U18

A

U20

A

U22

A

U25

A

U28
A

V1

A

V5

A

V7

A

V10

A

V12

A

V14

A

V16

A

V19

A

V21

A

V23

A

V26

A

V28

A

V32

A

W5

A

W28

A

Y6

A

Y7

A

Y8

A

Y10

A

Y11

A

Y12

A

Y13

A

Y14

A

Y15

A

Y16

A

Y18

A

Y19

A

Y20

A

Y21

A

Y22

A

Y23

A

Y25

A

Y26

A

Y27
B

B1

B

B20

B

B32
B

D3

B

D7

B

D10

B

D12

B

D14

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

@

SS_248

SS_249

SS_250

SS_251

SS_252

SS_253

SS_254

SS_255

SS_256

SS_257

SS_258

SS_259

SS_260

SS_261

SS_262

SS_263

SS_264

SS_265

SS_266

SS_267

SS_268

SS_269

SS_270

SS_271

SS_272

SS_273

SS_274

SS_275

SS_276

SS_277

SS_278

SS_279

SS_280

SS_281

SS_282

SS_283

SS_284

SS_285

SS_286

SS_287

SS_288

SS_289

SS_290

SS_291

SS_292

SS_293

SS_294

SS_295

SS_296

SS_297

SS_298

SS_299

SS_300

SS_301

SS_302

SS_303

SS_304

SS_305

SS_306

SS_307

SS_308

SS_309

GND/RSVD

FP5 REV 0.90

P

ART 11 OF 13

V

SS_310

V

SS_311

V

SS_312

V

SS_313

V

SS_314

V

SS_315

R

SVD_1

R

SVD_5

R

SVD_7

R

SVD_8

R

SVD_9

R

SVD_10

R

SVD_11

R

SVD_12

R

SVD_13

R

SVD_22

R

SVD_23

R

SVD_30

R

SVD_31

R

SVD_37

R

SVD_44

R

SVD_49

R

SVD_50

R

SVD_57

R

SVD_58

R

SVD_59

R

SVD_60

R

SVD_69

R

SVD_70

R

SVD_71

R

SVD_74

R

SVD_75

R

SVD_78

R

SVD_79

R

SVD_80

R

SVD_81

R

SVD_82

R

SVD_83

R

SVD_87

R

SVD_88

R

SVD_14

R

SVD_84

R

SVD_85

R

SVD_86

F

P5_BGA_ 1140P

B

D16

B

D19

B

D21

B

D23

B

D26

B

D30

B

20

G

3

J

20

K

3

K

6

K

20

M

3

M

6

M

13

P

6

P

22

T

3

T

6

T

29

W

6

W

21

W

22

Y

21

Y

27

A

A3

A

A6

A

C29

A

D3

A

D6

A

F3

A

F6

A

F30

A

J6

A

J24

A

K23

A

K27

A

L3

A

N29

A

N31

M

14

A

L6

A

L11

A

N16

UC1L

11

T

SVD_32

15

15
14

13

10

11
11

R

C7

A

SVD_66

R

9

Y

SVD_55

R

10

Y

SVD_56

R

11

W

SVD_47

R

12

W

SVD_48

R

9

V

SVD_38

R

10

V

SVD_39

R

A12

A

SVD_64

R

C10

A

SVD_68

R

11

13
10

4

@

S

S

S

ecurity Classif ication

ecurity Classif ication

ecurity Classif ication

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

RSVD

FP5 REV 0.90

ART 12 OF 13

P

P5_BGA_ 1140P

F

2

2

2

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

3

R

R

R

R

R

R

R

R

R

R

R

R

SVD_62

SVD_61

SVD_65

SVD_72

SVD_67

SVD_63

SVD_33

SVD_73

SVD_53

SVD_54

SVD_45

SVD_46

A
A
A

A

A
A

T
A

Y
Y

W
W

A9
A8
C6

D11

C9
A11

12
D12

6
7

8
9

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered D ate

eciphered D ate

eciphered D ate

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

C

C

C

ustom

ustom

ustom

Date: Sheet

Date: Sheet

2

Date: Sheet

ompal Electronics, Inc.

F

F

F

P5_(7/7)_GND/RSVD/CSI

P5_(7/7)_GND/RSVD/CSI

P5_(7/7)_GND/RSVD/CSI

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

1

1

1

1

A

A

A

o

o

o

f

12 99Wed nesday, May 15, 2019

f

12 99Wed nesday, May 15, 2019

f

12 99Wed nesday, May 15, 2019

5

D D

C C

4

3

2

1

R

B B

A A

5

4

eserve Page

S

S

S

ecurity Classif ication

ecurity Classif ication

ecurity Classif ication

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

2

2

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

3

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered D ate

eciphered D ate

eciphered D ate

2

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

Reserve Page

Reserve Page

Reserve Page

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

o

o

o

f

13 99Wed nesday, May 15, 2019

f

13 99Wed nesday, May 15, 2019

f

13 99Wed nesday, May 15, 2019

1

1

1

1

A

A

A

5

D D

C C

4

3

2

1

R

B B

A A

5

4

eserve Page

S

S

S

ecurity Classif ication

ecurity Classif ication

ecurity Classif ication

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

2

2

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

3

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered D ate

eciphered D ate

eciphered D ate

2

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

Reserve Page

Reserve Page

Reserve Page

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

o

o

o

f

14 99Wed nesday, May 15, 2019

f

14 99Wed nesday, May 15, 2019

f

14 99Wed nesday, May 15, 2019

1

1

1

1

A

A

A

5

D D

C C

4

3

2

1

R

B B

A A

5

4

eserve Page

S

S

S

ecurity Classif ication

ecurity Classif ication

ecurity Classif ication

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

2

2

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

3

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered D ate

eciphered D ate

eciphered D ate

2

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

Reserve Page

Reserve Page

Reserve Page

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

o

o

o

f

15 99Wed nesday, May 15, 2019

f

15 99Wed nesday, May 15, 2019

f

15 99Wed nesday, May 15, 2019

1

1

1

1

A

A

A

5

D D

C C

4

3

2

1

R

B B

A A

5

4

eserve Page

S

S

S

ecurity Classif ication

ecurity Classif ication

ecurity Classif ication

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

2

2

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

3

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered D ate

eciphered D ate

eciphered D ate

2

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

Reserve Page

Reserve Page

Reserve Page

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

o

o

o

f

16 99Wed nesday, May 15, 2019

f

16 99Wed nesday, May 15, 2019

f

16 99Wed nesday, May 15, 2019

1

1

1

1

A

A

A

5

D D

C C

4

3

2

1

R

B B

A A

5

4

eserve Page

S

S

S

ecurity Classif ication

ecurity Classif ication

ecurity Classif ication

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

2

2

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

3

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered D ate

eciphered D ate

eciphered D ate

2

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

Reserve Page

Reserve Page

Reserve Page

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

o

o

o

f

17 99Wed nesday, May 15, 2019

f

17 99Wed nesday, May 15, 2019

f

17 99Wed nesday, May 15, 2019

1

1

1

1

A

A

A

5

D D

C C

4

3

2

1

R

B B

A A

5

4

eserve Page

S

S

S

ecurity Classif ication

ecurity Classif ication

ecurity Classif ication

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

2

2

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

3

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered D ate

eciphered D ate

eciphered D ate

2

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

Reserve Page

Reserve Page

Reserve Page

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

o

o

o

f

18 99Wed nesday, May 15, 2019

f

18 99Wed nesday, May 15, 2019

f

18 99Wed nesday, May 15, 2019

1

1

1

1

A

A

A

5

D D

C C

4

3

2

1

R

B B

A A

5

4

eserve Page

S

S

S

ecurity Classif ication

ecurity Classif ication

ecurity Classif ication

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

2

2

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

3

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered D ate

eciphered D ate

eciphered D ate

2

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

Reserve Page

Reserve Page

Reserve Page

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

o

o

o

f

19 99Wed nesday, May 15, 2019

f

19 99Wed nesday, May 15, 2019

f

19 99Wed nesday, May 15, 2019

1

1

1

1

A

A

A

5

D D

C C

4

3

2

1

R

B B

A A

5

4

eserve Page

S

S

S

ecurity Classif ication

ecurity Classif ication

ecurity Classif ication

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

2

2

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

3

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered D ate

eciphered D ate

eciphered D ate

2

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

Reserve Page

Reserve Page

Reserve Page

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

o

o

o

f

20 99Wed nesday, May 15, 2019

f

20 99Wed nesday, May 15, 2019

f

20 99Wed nesday, May 15, 2019

1

1

1

1

A

A

A

5

D D

C C

4

3

2

1

R

B B

A A

5

4

eserve Page

S

S

S

ecurity Classif ication

ecurity Classif ication

ecurity Classif ication

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

2

2

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

3

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered D ate

eciphered D ate

eciphered D ate

2

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

Reserve Page

Reserve Page

Reserve Page

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

o

o

o

f

21 99Wed nesday, May 15, 2019

f

21 99Wed nesday, May 15, 2019

f

21 99Wed nesday, May 15, 2019

1

1

1

1

A

A

A

5

D D

C C

4

3

2

1

R

B B

A A

5

4

eserve Page

S

S

S

ecurity Classif ication

ecurity Classif ication

ecurity Classif ication

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

2

2

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

3

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered D ate

eciphered D ate

eciphered D ate

2

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

Reserve Page

Reserve Page

Reserve Page

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

o

o

o

f

22 99Wed nesday, May 15, 2019

f

22 99Wed nesday, May 15, 2019

f

22 99Wed nesday, May 15, 2019

1

1

1

1

A

A

A

A

B

C

D

E

Reverse Type-4H

2-3A to 1 DIMMs/channel

DR_A_CLK0

7DDR_A_CLK0
7DDR_A_CLK0#
7DDR_A_CLK1

7DDR_A_MA14_W E#
7DDR_A_MA15_CAS#
7DDR_A_MA16_RAS#

9,24SMB_0_SDA
9,24SMB_0_SCL

B

7DDR_A_CLK1#

7DDR_A_CKE0
7DDR_A_CKE1

7DDR_A_CS0#
7DDR_A_CS1#

7DDR_A_ODT0
7DDR_A_ODT1

7DDR_A_BG0

7DDR_A_BG1
7DDR_A_BA0
7DDR_A_BA1

7DDR_A_MA[13..0]

7DDR_A_ACT#

7DDR_A_PAR
7DDR_A_ALERT#

7DDR_A_EVENT#

7DDR_A_RST#

7DDR_A_DM[7..0]

Address : A0

1 1

+

3VS

12

12

12

RD50_0402_5%

@

12

12

R

0_0402_5%

RS@

D8

Layout Note:
Place near JDIMM1

2 2

+

1.2V

1U_0201_6.3V6M

C

1

D2

2

+

1.2V

10U_0402_6.3

C

1

D10

2

V6M

3 3

+

1.2V

0.1U_0201_10V6K
C

2

D61

1

Layout Note:
Place near JDIMM1.257,259

4 4

10U_0402_6.3

C

1

D23

2

V6M

R

0_0402_5%

RD60_0402_5%

D7

@

@

DR_A_SA2

D

DR_A_SA1

D

DR_A_SA0

D

12

R

0_0402_5%

RS@

R

0_0402_5%

RS@

D10

D9

N

ote:
Check voltage tolerance of
VREF_DQ at the DIMM socket

CRB use 0.1uF x12 (6 pop,6 unpop),180pF x1,100uF x2

1U_0201_6.3V6M

1U_0201_6.3V6M

C

1

1

D3

2

2

10U_0402_6.3

10U_0402_6.3

C

1

1

D11

2

2

V6M

V6M

0.1U_0201_10V6K

0.1U_0201_10V6K
C

2

2

D62

1

1

CRB use 0.1uF x2,180pF x1

+

2.5V

10U_0402_6.3

C

1

D24

2

V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

C

1

D4

2

10U_0402_6.3

C

1

D12

2

V6M

0.1U_0201_10V6K

C

2

D63

1

1U_0201_6.3V6M

C

1

D25

2

A

1U_0201_6.3V6M

C
D5

C
D13

C
D64

C

C

1

1

D6

D7

2

2

10U_0402_6.3

1

2

V6M

10U_0402_6.3

10U_0402_6.3

C
D14

C

C

1

1

D98

D15

2

2

V6M

V6M

180P_0402_50V8J

C

2

D65

1

Layout Note:
Place near JDIMM1.255

D1

@EMC@

C
.1U_0402_1 6V7K

DDR4 support Even Parity check in DRAMs.

DR_A_RST#

D

12

Follow MA51

1

@

+

D18

C
330U_D2_2 V_Y

2

SGA00009S00
330U 2V H1.9
9mohm POLY

CRB use 1uF x1

+

3VS

1U_0201_6.3V6M

C

1

D26

2

D

DR_A_CLK0#

D

DR_A_CLK1

D

DR_A_CLK1#

D

DR_A_CKE0

D

DR_A_CKE1

D

DR_A_CS0#

D

DR_A_CS1#

D

DR_A_ODT0

D

DR_A_ODT1

D

DR_A_BG0

D

DR_A_BG1

D

DR_A_BA0

D

DR_A_BA1

D

DR_A_MA0

D

DR_A_MA1

D

DR_A_MA2

D

DR_A_MA3

D

DR_A_MA4

D

DR_A_MA5

D

DR_A_MA6

D

DR_A_MA7

D

DR_A_MA8

D

DR_A_MA9

D

DR_A_MA10

D

DR_A_MA11

D

DR_A_MA12

D

DR_A_MA13

D

DR_A_MA14_W E#

D

DR_A_MA15_CAS#

D

DR_A_MA16_RAS#

D

DR_A_ACT#

D

DR_A_PAR

D

DR_A_ALERT#

D

DR_A_EVENT#

D

DR_A_RST#

D

MB_0_SDA

S

MB_0_SCL

S

DR_A_SA2

D

DR_A_SA1

D

DR_A_SA0

D

DR_A_DM0

D

DR_A_DM1

D

DR_A_DM2

D

DR_A_DM3

D

DR_A_DM4

D

DR_A_DM5

D

DR_A_DM6

D

DR_A_DM7

D

JDIMM1A

REVERSE

137

C

K0(T)

139

C

K0#(C)

138

C

K1(T)

140

C

K1#(C)

109

C

KE0

110

C

KE1

149

S

0#

157

S

1#

162

2#/C0

S

165

S

3#/C1

155

O

DT0

161

O

DT1

115

B

G0

113

B

G1

150

B

A0

145

B

A1

144

A

0

133

A

1

132

A

2

131

A

3

128

A

4

126

A

5

127

A

6

122

A

7

125

A

8

121

A

9

146

A

10_AP

120

A

11

119

A

12

158

A

13

151

A

14_WE#

156

A

15_CAS#

152

A

16_RAS#

114

A

CT#

143

P

ARITY

116

A

LERT#

134

E

VENT#

108

ESET#

R

254

DA

S

253

S

CL

166

A2

S

260

A1

S

256

A0

S

92

C

B0_NC

91

C

B1_NC

101

C

B2_NC

105

C

B3_NC

88

C

B4_NC

87

C

B5_NC

100

C

B6_NC

104

C

B7_NC

97

D

QS8(T)

95

D

QS8#(C)

12

D

M0#/DBI0#

33

D

M1#/DBI1#

54

D

M2#/DBI2#

75

D

M3#/DBI3#

178

D

M4#/DBI4#

199

D

M5#/DBI5#

220

D

M6#/DBI6#

241

D

M7#/DBI7#

96

D

M8#/DBI8#

LOTES_ADDR02 06-P001A

CONN@

S

P07001EGA0

D

Q0

D

Q1

D

Q2

D

Q3

D

Q4

D

Q5

D

Q6

D

Q7

D

QS0(T)

D

QS0#(C)

D

Q8

D

Q9

D

Q10

D

Q11

D

Q12

D

Q13

D

Q14

D

Q15

D

QS1(T)

D

QS1#(C)

D

Q16

D

Q17

D

Q18

D

Q19

D

Q20

D

Q21

D

Q22

D

Q23

D

QS2(T)

D

QS2#(C)

D

Q24

D

Q25

D

Q26

D

Q27

D

Q28

D

Q29

D

Q30

D

Q31

D

QS3(T)

D

QS3#(C)

D

Q32

D

Q33

D

Q34

D

Q35

D

Q36

D

Q37

D

Q38

D

Q39

D

QS4(T)

D

QS4#(C)

D

Q40

D

Q41

D

Q42

D

Q43

D

Q44

D

Q45

D

Q46

D

Q47

D

QS5(T)

D

QS5#(C)

D

Q48

D

Q49

D

Q50

D

Q51

D

Q52

D

Q53

D

Q54

D

Q55

D

QS6(T)

D

QS6#(C)

D

Q56

D

Q57

D

Q58

D

Q59

D

Q60

D

Q61

D

Q62

D

Q63

D

QS7(T)

D

QS7#(C)

S

S

S

eeecccuuurrriii tttyyy CCClllaaassssssiii fffiiicccaaatttiiiooonnn

T

T

T

HHHIIISSS SSSHHHEEEEEETTT OOOFFF EEENNNGGGIIINNNEEEEEERRRIIINNNGGG DDDRRRAAAWWWIIINNNGGG IIISSS TTTHHHEEE PPPRRROOOPPPRRRIIIEEETTTAAARRRYYY PPPRRROOOPPPEEERRRTTTYYY OOOFFF CCCOOOMMMPPPAAALLL EEELLLEEECCCTTTRRROOONNNIIICCCSSS,,, IIINNNCCC... AAANNNDDD CCCOOONNNTTTAAAIIINNNSSS CCCOOONNNFFFIIIDDDEEENNNTTTIIIAAALLL
AAANNNDDD TTTRRRAAADDDEEE SSSEEECCCRRREEETTT IIINNNFFFOOORRRMMMAAATTTIIIOOONNN... TTTHHHIIISSS SSSHHHEEEEEETTT MMMAAAYYY NNNOOOTTT BBBEEE TTTRRRAAANNNSSSFFFEEERRREEEDDD FFFRRROOOMMM TTTHHHEEE CCCUUUSSSTTTOOODDDYYY OOOFFF TTTHHHEEE CCCOOOMMMPPPEEETTTEEENNNTTT DDDIIIVVVIIISSSIIIOOONNN OOOFFF RRR&&&DDD
DDDEEEPPPAAA RRRTTTMMMEEENNNTTT EEEXXXCCCEEEPPPTTT AAASSS AAAUUUTTTHHHOOORRRIIIZZZEEEDDD BBBYYY CCCOOOMMMPPPAAALLL EEELLLEEECCCTTTRRROOONNNIIICCCSSS,,, IIINNNCCC... NNNEEEIIITTTHHHEEERRR TTTHHHIIISSS SSSHHHEEEEEETTT NNNOOORRR TTTHHHEEE IIINNNFFFOOORRRMMMAAATTTIIIOOONNN IIITTT CCCOOONNNTTTAAA IIINNNSSS
MMMAAAYYY BBBEEE UUUSSSEEEDDD BBBYYY OOORRR DDDIIISSSCCCLLLOOOSSSEEEDDD TTTOOO AAANNNYYY TTTHHHIIIRRRDDD PPPAAARRRTTTYYY WWWIIITTTHHHOOOUUUTTT PPPRRRIIIOOORRR WWWRRRIIITTTTTTEEENNN CCCOOONNNSSSEEENNNTTT OOOFFF CCCOOOMMMPPPAAALLL EEELLLEEECCCTTTRRROOONNNIIICCCSSS,,, IIINNNCCC...

C

8
7
20
21
4
3
16
17
13
11

28
29
41
42
24
25
38
37
34
32

50
49
62
63
46
45
58
59
55
53

70
71
83
84
66
67
79
80
76
74

174
173
187
186
170
169
183
182
179
177

195
194
207
208
191
190
203
204
200
198

216
215
228
229
211
212
224
225
221
219

237
236
249
250
232
233
245
246
242
240

I

I

I

ssssssuuueeeddd DDDaaattteee

DR_A_DQ0

D

DR_A_DQ1

D

DR_A_DQ2

D

DR_A_DQ3

D

DR_A_DQ4

D

DR_A_DQ5

D

DR_A_DQ6

D

DR_A_DQ7

D

DR_A_DQS0

D

DR_A_DQS0#

D

DR_A_DQ8

D

DR_A_DQ9

D

DR_A_DQ10

D

DR_A_DQ11

D

DR_A_DQ12

D

DR_A_DQ13

D

DR_A_DQ14

D

DR_A_DQ15

D

DR_A_DQS1

D

DR_A_DQS1#

D

DR_A_DQ16

D

DR_A_DQ17

D

DR_A_DQ18

D

DR_A_DQ19

D

DR_A_DQ20

D

DR_A_DQ21

D

DR_A_DQ22

D

DR_A_DQ23

D

DR_A_DQS2

D

DR_A_DQS2#

D

DR_A_DQ24

D

DR_A_DQ25

D

DR_A_DQ26

D
DDR_A_DQ27

DR_A_DQ28

D

DR_A_DQ29

D
DDR_A_DQ30

DR_A_DQ31

D

DR_A_DQS3

D

DR_A_DQS3#

D

DDR_A_DQ32
DDR_A_DQ33
DDR_A_DQ34
DDR_A_DQ35
DDR_A_DQ36
DDR_A_DQ37
DDR_A_DQ38
DDR_A_DQ39

DR_A_DQS4

D

DR_A_DQS4#

D

DDR_A_DQ40
D

DR_A_DQ41

D

DR_A_DQ42

D

DR_A_DQ43

D

DR_A_DQ44

D

DR_A_DQ45

D

DR_A_DQ46

D

DR_A_DQ47
DR_A_DQS5

D

DR_A_DQS5#

D

D

DR_A_DQ48

D

DR_A_DQ49

D

DR_A_DQ50

D

DR_A_DQ51

D

DR_A_DQ52

D

DR_A_DQ53

D

DR_A_DQ54

D

DR_A_DQ55
DR_A_DQS6

D

DR_A_DQS6#

D

D

DR_A_DQ56

D

DR_A_DQ57

D

DR_A_DQ58

D

DR_A_DQ59

D

DR_A_DQ60

D

DR_A_DQ61

D

DR_A_DQ62

D

DR_A_DQ63
DR_A_DQS7

D

DR_A_DQS7#

D

DDR_A_DQ[7..0] 7

Follow CRB design

+

RD3

1K_0402_1%

R

D4

1K_0402_1%

1.2V

1 2

1

5mil

C
D20 4.7U_0402_6.3V6M

2

1

2

1

D

DR_A_DQS0 7

D

DR_A_DQS0# 7

D

DR_A_DQ[15..8] 7

D

DR_A_DQS1 7

D

DR_A_DQS1# 7

D

DR_A_DQ[23..16] 7

D

DR_A_DQS2 7

D

DR_A_DQS2# 7

D

DR_A_DQ[31..24] 7

Place near to SO-DIMM connector.

D

DR_A_DQS3 7

D

DR_A_DQS3# 7

D

DR_A_DQ[39..32] 7

D

DR_A_DQS4 7

D

DR_A_DQS4# 7

D

DR_A_DQ[47..40] 7

D

DR_A_DQS5 7

D

DR_A_DQS5# 7

D

DR_A_DQ[55..48] 7

D

DR_A_DQS6 7

D

DR_A_DQS6# 7

D

DR_A_DQ[63..56] 7

D

DR_A_DQS7 7

D

DR_A_DQS7# 7

C

C

C

2

2

2

000111888/// 111222///111888 222000111999///111222///111888

ooommmpppaaalll SSSeeecccrrreeettt DDDaaatttaaa

D

D

D

eeeccciiippphhheeerrreeeddd DDDaaattteee

D

+

1.2V

DIMM1B

J

REVERSE

111

DD1

V

V

112

DD2

V

V

117

DD3

V

V

118

DD4

V

V

123

DD5

V

V

124

DD6

V

V

129

DD7

V

V

130

DD8

V

+

+

VREFA_CA

C
D22 0.1U_0201_10V6K

2

1

3VS

C

C

D19 1000P_0402_50V7K

D21 0.1U_0201_10V6K

1

2

2

1

T

T

T

iiitttllleee

SSSiiizzz eee DDDooocccuuummmeeennnttt NNNuuummmbbbeeerrr RRReeevvv

C

C

C

uuussstttooommm

DDDaaattteee::: SSShhheeeeeettt

V

135

DD9

V

V

136

DD10

V

255

DDSPD

V

164

REFCA

V

1

SS

V

2

SS

V

5

SS

V

6

SS

V

9

SS

V

10

SS

V

14

SS

V

15

SS

V

18

SS

V

19

SS

V

22

SS

V

23

SS

V

26

SS

V

27

SS

V

30

SS

V

31

SS

V

35

SS

V

36

SS

V

39

SS

V

40

SS

V

43

SS

V

44

SS

V

47

SS

V

48

SS

V

51

SS

V

52

SS

V

56

SS

V

57

SS

V

60

SS

V

61

SS

V

64

SS

V

65

SS

V

68

SS

V

69

SS

V

72

SS

V

73

SS

V

77

SS

V

78

SS

V

81

SS

V

82

SS

V

85

SS

V

86

SS

V

89

SS

V

90

SS

V

93

SS

V

94

SS

V

98

SS

V

262

ND

G

LOTES_ADDR02 06-P001A

CONN@

P07001EGA0

S

Layout Note:
Place near JDIMM1.258

CRB use 4.7uF x1,0.1uF x1

+

0.6VS

10U_0402_6.3

10U_0402_6.3

C

C

1

1

D28

D27

2

2

V6M

V6M

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

DDR4_DIMMA

DDR4_DIMMA

DDR4_DIMMA

FH50P M/B LA-H901P

FH50P M/B LA-H901P

FH50P M/B LA-H901P

DD11
DD12
DD13
DD14
DD15
DD16
DD17
DD18
DD19

V
V

G

E

+

1.2V

141
142
147
148
153
154
159
160

+

0.6VS

163

258

TT

V

257

PP1

259

PP2

99

SS

V

102

SS

V

103

SS

V

106

SS

V

107

SS

V

167

SS

V

168

SS

V

171

SS

V

172

SS

V

175

SS

V

176

SS

V

180

SS

V

181

SS

V

184

SS

V

185

SS

V

188

SS

V

189

SS

V

192

SS

V

193

SS

V

196

SS

V

197

SS

V

201

SS

V

202

SS

V

205

SS

V

206

SS

V

209

SS

V

210

SS

V

213

SS

V

214

SS

V

217

SS

V

218

SS

V

222

SS

V

223

SS

V

226

SS

V

227

VSS

230

VSS

231

VSS

234

VSS

235

VSS

238

VSS

239

VSS

243

VSS

244

VSS

247

V

SS

248

V

SS

251

V

SS

252

V

SS

261

ND

1U_0201_6.3V6M

1U_0201_6.3V6M

C

1

1

D29

2

2

C
D30

222333 999999WWWeeedddnnn eeesssdddaaayyy,,, MMMaaayyy 111555,,, 222000111999

+

2.5V

C
D31 1U_0201_6.3V6M

1

2

CRB use 1uF x1

o

o

o

fff

1

1

1

AAA

A

A

ddress : A2

1 1

+

3VS

10K_0402_5%

12

1

R

0_0402_5%

D247

@

2

12

12

R

0_0402_5%

RS@

D252

Layout Note:
Place near JDIMM2

2 2

+

1.2V

1U_0201_6.3V6M

C

1

D86

2

+

1.2V

10U_0402_6.3V6M

C

1

D82

2

3 3

+

1.2V

0.1U_0201_10V6K
C

2

D91

1

R

1

D244

0_0402_5%

R
D248

@

2

DR_B_SA2

D

DR_B_SA1

D

DR_B_SA0

D

12

R

0_0402_5%

RS@

R

0_0402_5%

D246

D249

@

N

ote:
Check voltage tolerance of
VREF_DQ at the DIMM socket

CRB use 0.1uF x12 (6 pop,6 unpop),180pF x1,100uF x2

1U_0201_6.3V6M

1U_0201_6.3V6M

1

2

10U_0402_6.3V6M

1

2

0.1U_0201_10V6K

2

1

1U_0201_6.3V6M

C

C

1

1

D78

D67

2

2

10U_0402_6.3V6M

10U_0402_6.3V6M

C

C

1

1

D96

D90

2

2

0.1U_0201_10V6K

0.1U_0201_10V6K

C

C

2

2

D94

D97

1

1

1U_0201_6.3V6M

1U_0201_6.3V6M

C

C

C

1

1

D93

C
D77

C
D66

D81

D71

2

2

10U_0402_6.3V6M

10U_0402_6.3V6M

1

2

10U_0402_6.3V6M

C
D68

C

C

1

1

D88

D99

2

2

180P_0402_50V8J

C

2

D85

1

D73

@EMC@

C
.1U_0402_1 6V7K

2

1

DR_B_RST#

D

B

DR_B_CLK0

D

DR_B_CLK07

D

DR_B_CLK0#7

D

DR_B_CLK17

D

DR_B_CLK1#7

D

DR_B_CKE07

D

DR_B_CKE17

D

DR_B_CS0#7

D

DR_B_CS1#7

D

DR_B_ODT07

D

DR_B_ODT17

D

DR_B_BG07

D

DR_B_BG17

D

DR_B_BA07

D

DR_B_BA17

D

DR_B_MA[13..0]7

D

DR_B_MA14_W E#7

D

DR_B_MA15_C AS#7

D

DR_B_MA16_R AS#7

D

DR_B_ACT#7

D

DR_B_PAR7

D

DR_B_ALERT#7

D

DR_B_EVENT#7

D

DR_B_RST#7

S

MB_0_SDA9 ,23

S

MB_0_SCL9,23

D

DR_B_DM[7..0]7

D

DR_B_CLK0#

D

DR_B_CLK1

D

DR_B_CLK1#

D

DR_B_CKE0

D

DR_B_CKE1

D

DR_B_CS0#

D

DR_B_CS1#

D

DR_B_ODT0

D

DR_B_ODT1

D

DR_B_BG0

D

DR_B_BG1

D

DR_B_BA0

D

DR_B_BA1

D

DR_B_MA0

D

DR_B_MA1

D

DR_B_MA2

D

DR_B_MA3

D

DR_B_MA4

D

DR_B_MA5

D

DR_B_MA6

D

DR_B_MA7

D

DR_B_MA8

D

DR_B_MA9

D

DR_B_MA10

D

DR_B_MA11

D

DR_B_MA12

D

DR_B_MA13

D

DR_B_MA14_W E#

D

DR_B_MA15_C AS#

D

DR_B_MA16_R AS#

D

DR_B_ACT#

D

DR_B_PAR

D

DR_B_ALERT#

D

DR_B_EVENT#

D

DR_B_RST#

D

MB_0_SDA

S

MB_0_SCL

S

DR_B_SA2

D

DR_B_SA1

D

DR_B_SA0

D

DR_B_DM0

D

DR_B_DM1

D

DR_B_DM2

D

DR_B_DM3

D

DR_B_DM4

D

DR_B_DM5

D

DR_B_DM6

D

DR_B_DM7

D

137
139
138
140

109
110

149
157
162
165

155
161

115
113
150
145

144
133
132
131
128
126
127
122
125
121
146
120
119
158
151
156
152

114

143
116
134
108

254
253

166
260
256

92

91
101
105

88

87
100
104

97

95

12

33

54

75
178
199
220
241

96

261
262

C

DIMM2A

J

STD

K0(T)

C

K0#(C)

C

K1(T)

C

K1#(C)

C

C

KE0

C

KE1

0#
1#
2#/C0
3#/C1

DT0
DT1

G0
G1
A0
A1

0
1
2
3
4
5
6
7
8
9
10_AP
11
12
13
14_WE#
15_CAS#
16_RAS#

CT#

ARITY
LERT#
VENT#
ESET#

DA
CL

A2
A1
A0

B0_NC
B1_NC
B2_NC
B3_NC
B4_NC
B5_NC
B6_NC
B7_NC
QS8(T)
QS8#(C)

M0#/DBI0#
M1#/DBI1#
M2#/DBI2#
M3#/DBI3#
M4#/DBI4#
M5#/DBI5#
M6#/DBI6#
M7#/DBI7#
M8#/DBI8#

ND1
ND2

D

D

QS0#(C)

D

D

QS1#(C)

D

D

QS2#(C)

D

D

QS3#(C)

D

D

QS4#(C)

D

D

QS5#(C)

D

D

QS6#(C)

D

D

QS7#(C)

QS0(T)

QS1(T)

QS2(T)

QS3(T)

QS4(T)

QS5(T)

QS6(T)

QS7(T)

S
S
S
S

O
O

B
B
B
B

A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A

A

P
A
E
R

S
S

S
S
S

C
C
C
C
C
C
C
C
D
D

D
D
D
D
D
D
D
D
D

G
G

LOTES_ADDR02 05-P001A

CONN@

D

S

2

-3A to 1 DIMMs/channel

D

Q0

D

Q1

D

Q2

D

Q3

D

Q4

D

Q5

D

Q6

D

Q7

D

Q8

D

Q9

D

Q10

D

Q11

D

Q12

D

Q13

D

Q14

D

Q15

D

Q16

D

Q17

D

Q18

D

Q19

D

Q20

D

Q21

D

Q22

D

Q23

D

Q24

D

Q25

D

Q26

D

Q27

D

Q28

D

Q29

D

Q30

D

Q31

D

Q32

D

Q33

D

Q34

D

Q35

D

Q36

D

Q37

D

Q38

D

Q39

D

Q40

D

Q41

D

Q42

D

Q43

D

Q44

D

Q45

D

Q46

D

Q47

D

Q48

D

Q49

D

Q50

D

Q51

D

Q52

D

Q53

D

Q54

D

Q55

D

Q56

D

Q57

D

Q58

D

Q59

D

Q60

D

Q61

D

Q62

D

Q63

DR_B_DQ1

D

7

DR_B_DQ2

D

20

DR_B_DQ3

D

21

DR_B_DQ4

D

4

DR_B_DQ5

D

3

DR_B_DQ6

D

16

DR_B_DQ7

D

17

DR_B_DQS0

D

13

DR_B_DQS0#

D

11

DR_B_DQ8

D

28

DR_B_DQ9

D

29

D

DR_B_DQ10

41

D

DR_B_DQ11

42

DR_B_DQ12

D

24

DR_B_DQ13

D

25

D

DR_B_DQ14

38

DR_B_DQ15

D

37

DR_B_DQS1

D

34

DR_B_DQS1#

D

32

D

DR_B_DQ16

50

D

DR_B_DQ17

49

D

DR_B_DQ18

62

DR_B_DQ19

D

63

D

DR_B_DQ20

46

D

DR_B_DQ21

45

D

DR_B_DQ22

58

D

DR_B_DQ23

59

DR_B_DQS2

D

55

DR_B_DQS2#

D

53

DR_B_DQ24

D

70

DR_B_DQ25

D

71

DR_B_DQ26

D

83

D

DR_B_DQ27

84

DR_B_DQ28

D

66

DR_B_DQ29

D

67

D

DR_B_DQ30

79

DR_B_DQ31

D

80

DR_B_DQS3

D

76

DR_B_DQS3#

D

74

DR_B_DQ32

D

174

DR_B_DQ33

D

173

DR_B_DQ34

D

187

D

DR_B_DQ35

186

DR_B_DQ36

D

170

D

DR_B_DQ37

169

DR_B_DQ38

D

183

DR_B_DQ39

D

182

DR_B_DQS4

D

179

DR_B_DQS4#

D

177

DR_B_DQ40

D

195

D

DR_B_DQ41

194

DR_B_DQ42

D

207

DR_B_DQ43

D

208

DR_B_DQ44

D

191

D

DR_B_DQ45

190

DR_B_DQ46

D

203

DR_B_DQ47

D

204

DR_B_DQS5

D

200

DR_B_DQS5#

D

198

DR_B_DQ48

D

216

D

DR_B_DQ49

215

DR_B_DQ50

D

228

DR_B_DQ51

D

229

D

DR_B_DQ52

211

DR_B_DQ53

D

212

DR_B_DQ54

D

224

DR_B_DQ55

D

225

DR_B_DQS6

D

221

DR_B_DQS6#

D

219

D

DR_B_DQ56

237

D

DR_B_DQ57

236

D

DR_B_DQ58

249

D

DR_B_DQ59

250

D

DR_B_DQ60

232

D

DR_B_DQ61

233

D

DR_B_DQ62

245

D

DR_B_DQ63

246

DR_B_DQS7

D

242

DR_B_DQS7#

D

240

DR_B_DQ0

D

8

D

DR_B_DQ[7..0] 7

D

DR_B_DQS0 7

D

DR_B_DQS0# 7

D

DR_B_DQ[15..8] 7

D

DR_B_DQS1 7

D

DR_B_DQS1# 7

D

DR_B_DQ[23..16 ] 7

D

DR_B_DQS2 7

D

DR_B_DQS2# 7

D

DR_B_DQ[31..24 ] 7

D

DR_B_DQS3 7

D

DR_B_DQS3# 7

D

DR_B_DQ[39..32 ] 7

D

DR_B_DQS4 7

D

DR_B_DQS4# 7

D

DR_B_DQ[47..40 ] 7

D

DR_B_DQS5 7

D

DR_B_DQS5# 7

D

DR_B_DQ[55..48 ] 7

D

DR_B_DQS6 7

D

DR_B_DQS6# 7

D

DR_B_DQ[63..56 ] 7

D

DR_B_DQS7 7

D

DR_B_DQS7# 7

Follow CRB design

+

1.2V

D243

R

1K_0402_1%

R

D251

1K_0402_1%

1 2

C
D84 4.7U_0402_6.3V6M

2

1

+

VREFB_CA

1

5mil

C

C

C
D87 1000P_0402_50V7K

D80 0.1U_0201_10V6K

D76 0.1U_0201_10V6K

1

2

2

1

2

1

1

2

Place near to SO-DIMM connector.

+

1.2V

J

111
112
117
118
123
124
129
130

+

3VS

135
136

255

164

1
2
5
6

9
10
14

15
18
19
22
23
26
27
30
31
35
36
39
40
43
44
47
48
51
52
56
57
60
61
64
65
68
69
72
73
77
78
81
82
85
86
89
90
93
94
98

262

LOTES_ADDR02 05-P001A

CONN@

Layout Note:
Place near JDIMM2.258

E

tand Type-4H

+

DIMM2B

V

DD1

V

DD2

V

DD3

V

DD4

V

DD5

V

DD6

V

DD7

V

DD8

V

DD9

V

DD10

V

DDSPD

V

REFCA

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

ND

G

STD

DD11

V

DD12

V

DD13

V

DD14

V

DD15

V

DD16

V

DD17

V

DD18

V

DD19

V

V
V

1.2V

141
142
147
148
153
154
159
160

+

163

258

TT

V

257

PP1

259

PP2

99

SS

V

102

SS

V

103

SS

V

106

SS

V

107

SS

V

167

SS

V

168

SS

V

171

SS

V

172

SS

V

175

SS

V

176

SS

V

180

SS

V

181

SS

V

184

SS

V

185

SS

V

188

SS

V

189

SS

V

192

SS

V

193

SS

V

196

SS

V

197

SS

V

201

SS

V

202

SS

V

205

SS

V

206

SS

V

209

SS

V

210

SS

V

213

SS

V

214

SS

V

217

SS

V

218

SS

V

222

SS

V

223

SS

V

226

SS

V

227

SS

V

230

SS

V

231

SS

V

234

SS

V

235

SS

V

238

SS

V

239

SS

V

243

SS

V

244

SS

V

247

SS

V

248

SS

V

251

SS

V

252

SS

V

261

ND

G

0.6VS

CRB use 1uF x1

+

2.5V

C
D89 1U_0201_6.3V6M

1

2

CRB use 4.7uF x1,0.1uF x1

+

Layout Note:
Place near JDIMM2.257,259

CRB use 0.1uF x2,180pF x1

+

4 4

10U_0402_6.3V6M

C

1

D79

2

2.5V

1U_0201_6.3V6M

10U_0402_6.3V6M

C

C

1

1

D75

D83

2

2

A

Layout Note:
Place near JDIMM2.255

CRB use 1uF x1

+

3VS

1U_0201_6.3V6M

C

1

D95

2

1

2

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2

2

2

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered Date

eciphered Date

eciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

T

T

T

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

itle

itle

itle

C

C

C

ustom

ustom

ustom

0.6VS

1U_0201_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

C

C

C

1

1

D74

D70

DDR4_DIMMB

DDR4_DIMMB

DDR4_DIMMB

FH50P M/B LA-H901P

FH50P M/B LA-H901P

FH50P M/B LA-H901P

D92

2

2

E

1U_0201_6.3V6M

C

1

D72

2

1

1

1

A

A

A

o

o

o

f

24 99Wednesday, May 15, 201 9

f

24 99Wednesday, May 15, 201 9

f

24 99Wednesday, May 15, 201 9

5

D D

C C

4

3

2

1

R

B B

A A

5

4

eserve Page

S

S

S

ecurity Classif ication

ecurity Classif ication

ecurity Classif ication

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

2

2

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

3

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered D ate

eciphered D ate

eciphered D ate

2

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

Reserve Page

Reserve Page

Reserve Page

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

o

o

o

f

25 99Wed nesday, May 15, 2019

f

25 99Wed nesday, May 15, 2019

f

25 99Wed nesday, May 15, 2019

1

1

1

1

A

A

A

5

D D

C C

4

3

2

1

R

B B

A A

5

4

eserve Page

S

S

S

ecurity Classif ication

ecurity Classif ication

ecurity Classif ication

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

2

2

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

3

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered D ate

eciphered D ate

eciphered D ate

2

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

Reserve Page

Reserve Page

Reserve Page

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

o

o

o

f

26 99Wed nesday, May 15, 2019

f

26 99Wed nesday, May 15, 2019

f

26 99Wed nesday, May 15, 2019

1

1

1

1

A

A

A

5

4

3

2

1

D D

EG_ATX_ GRX_P0

P

EG_ATX_ GRX_P06

P

EG_ATX_ GRX_N06

P

EG_ATX_ GRX_P16

P

EG_ATX_ GRX_N16

P

EG_ATX_ GRX_P26

P

EG_ATX_ GRX_N26

P

EG_ATX_ GRX_P36

P

EG_ATX_ GRX_N36

P

EG_ATX_ GRX_P46

P

EG_ATX_ GRX_N46

P

EG_ATX_ GRX_P56

P

EG_ATX_ GRX_N56

P

EG_ATX_ GRX_P66

P

EG_ATX_ GRX_N66

P

EG_ATX_ GRX_P76

P

EG_ATX_ GRX_N76

C C

A

B B

PU_PCIE_R ST#9,51,52,68

P

E_GPIO010

P

EG_ATX_ GRX_N0

P

EG_ATX_ GRX_P1

P

EG_ATX_ GRX_N1

P

EG_ATX_ GRX_P2

P

EG_ATX_ GRX_N2

P

EG_ATX_ GRX_P3

P

EG_ATX_ GRX_N3

P

EG_ATX_ GRX_P4

P

EG_ATX_ GRX_N4

P

EG_ATX_ GRX_P5

P

EG_ATX_ GRX_N5

P

EG_ATX_ GRX_P6

P

EG_ATX_ GRX_N6

P

EG_ATX_ GRX_P7

P

EG_ATX_ GRX_N7

P

12

V370

R

2.2K_040 2_5%

DIS@

+

3VSDGPU

5

1

I

N1

2

I

N2

3

1 2

V312 0.22U_0 402_16V7KDIS@

C

1 2

C

V306 0.22U_0 402_16V7KDIS@

1 2

V308 0.22U_0 402_16V7KDIS@

C

2

1

C

V305 0.22U_0 402_16V7KDIS@

1 2

V307 0.22U_0 402_16V7KDIS@

C

1 2

C

V309 0.22U_0 402_16V7KDIS@

1 2

C

V313 0.22U_0 402_16V7KDIS@

2

1

V304 0.22U_0 402_16V7KDIS@

C

2

1

V2710 0.22U_0402 _16V7KDIS@

C

2

1

C

V2707 0.22U_0402 _16V7KDIS@

1 2

V2711 0.22U_0402 _16V7KDIS@

C

1 2

C

V2709 0.22U_0402 _16V7KDIS@

1 2

C

V2717 0.22U_0402 _16V7KDIS@

1 2

V2714 0.22U_0402 _16V7KDIS@

C

1 2

C

V2704 0.22U_0402 _16V7KDIS@

1 2

V2706 0.22U_0402 _16V7KDIS@

C

U

V2

SA00000OH00

MC74VHC 1G08DFT2G_SC 70-5

D

IS@

P

O

G

4

P

12

V4

R
100K_04 02_5%

IS@

D

LT_RST_ VGA#

C

LK_PEG_ P410

C

LK_PEG_ N410

EG_ATX_ C_GRX_P0

P

EG_ATX_ C_GRX_N0

P

P

EG_ATX_ C_GRX_P1

P

EG_ATX_ C_GRX_N1

P

EG_ATX_ C_GRX_P2

P

EG_ATX_ C_GRX_N2

P

EG_ATX_ C_GRX_P3

P

EG_ATX_ C_GRX_N3

P

EG_ATX_ C_GRX_P4

P

EG_ATX_ C_GRX_N4

P

EG_ATX_ C_GRX_P5

P

EG_ATX_ C_GRX_N5

P

EG_ATX_ C_GRX_P6

P

EG_ATX_ C_GRX_N6

P

EG_ATX_ C_GRX_P7

P

EG_ATX_ C_GRX_N7

LK_PEG_ P4

C

LK_PEG_ N4

C

V

DDCI_PG92

D

GPU_PW RGOOD1 0,92,94

V1B

U

@

ymbol2

AT41
AT40

AR41
AR40

AP41
AP40

AM41
AM40

AL41
AL40

AK41
AK40

AJ41
AJ40

AH41
AH40

AV33
AU33

s

CIE_RX0P

P

CIE_RX0N

P

CIE_RX1P

P

CIE_RX1N

P

CIE_RX2P

P

CIE_RX2N

P

CIE_RX3P

P

CIE_RX3N

P

CIE_RX4P

P

CIE_RX4N

P

CIE_RX5P

P

CIE_RX5N

P

CIE_RX6P

P

CIE_RX6N

P

CIE_RX7P

P

CIE_RX7N

P

CIE_REFCLKP

P

CIE_REFCLKN

P

REV 0.91

2160896 088A1R16M_FC BGA769P-NH

+

3VSDGPU

5

1

P

N1

I

2

N2

I

G

3

P

CIE_TX0N

P

CIE_TX1P

P

CIE_TX1N

P

CIE_TX2P

P

CIE_TX2N

P

CIE_TX3P

P

CIE_TX3N

P

CIE_TX4P

P

CIE_TX4N

P

CIE_TX5P

P

CIE_TX5N

P

CIE_TX6P

P

CIE_TX6N

P

CIE_TX7P

P

CIE_TX7N

P

ERSTB

P

X_EN

P

CIE_ZVSS

P

V1005

U
MC74VHC 1G08DFT2G_SC 70-5

IS@

D

4

O

EG_ARX_ C_GTX_N0

P

AU35

EG_ARX_ C_GTX_P1

P

AU38

EG_ARX_ C_GTX_N1

P

AU39

P

EG_ARX_ C_GTX_P2

AR37

P

EG_ARX_ C_GTX_N2

AR38

P

EG_ARX_ C_GTX_P3

AN37

P

EG_ARX_ C_GTX_N3

AN38

P

EG_ARX_ C_GTX_P4

AL37

P

EG_ARX_ C_GTX_N4

AL38

P

EG_ARX_ C_GTX_P5

AJ37

P

EG_ARX_ C_GTX_N5

AJ38

P

EG_ARX_ C_GTX_P6

AG37

P

EG_ARX_ C_GTX_N6

AG38

P

EG_ARX_ C_GTX_P7

AE37

P

EG_ARX_ C_GTX_N7

AE38

AV41

AC41

F

AU41

1 2

SA00000OH00

D

GPU_PW RGOOD_R

12

R

V1659
100K_04 02_5%

D

IS@

P

P

EG_ARX_ C_GTX_P0

P

AV35

CIE_TX0P

2

1

V1 0.22U_04 02_16V7KDIS@

C

2

1

C

V2 0.22U_04 02_16V7KDIS@

1 2

C

V3 0.22U_04 02_16V7KDIS@

1 2

C

V4 0.22U_04 02_16V7KDIS@

2

1

V5 0.22U_04 02_16V7KDIS@

C

2

1

V6 0.22U_04 02_16V7KDIS@

C

1 2

C

V7 0.22U_04 02_16V7KDIS@

1 2

C

V8 0.22U_04 02_16V7KDIS@

1 2

V2715 0.22U_0402 _16V7KDIS@

C

1 2

C

V2708 0.22U_0402 _16V7KDIS@

1 2

C

V2713 0.22U_0402 _16V7KDIS@

1 2

C

V2703 0.22U_0402 _16V7KDIS@

2

1

V2705 0.22U_0402 _16V7KDIS@

C

1 2

V2712 0.22U_0402 _16V7KDIS@

C

2

1

C

V2716 0.22U_0402 _16V7KDIS@

1 2

V2702 0.22U_0402 _16V7KDIS@

C

LT_RST_ VGA#

X_EN

1

TP@

T

R

D

V371

200_040 2_1%

IS@

218

P

LT_RST_ VGA#

D

GPU_PW RGOOD_R

or BACO mode(AMD PowerXpress) use, NC if not use

EG_ARX_ GTX_P0

P

EG_ARX_ GTX_N0

P

EG_ARX_ GTX_P1

P

EG_ARX_ GTX_N1

P

EG_ARX_ GTX_P2

P

EG_ARX_ GTX_N2

P

EG_ARX_ GTX_P3

P

EG_ARX_ GTX_N3

P

EG_ARX_ GTX_P4

P

EG_ARX_ GTX_N4

P

EG_ARX_ GTX_P5

P

EG_ARX_ GTX_N5

P

EG_ARX_ GTX_P6

P

EG_ARX_ GTX_N6

P

EG_ARX_ GTX_P7

P

EG_ARX_ GTX_N7

P

+

3VSDGPU

U

V3

MC74VHC 1G08DFT2G_SC 70-5

5

D

IS@

1

P

I

N1

4

O

2

I

N2

G

3

SA00000OH00

12

P

EG_ARX_ GTX_P0 6

P

EG_ARX_ GTX_N0 6

P

EG_ARX_ GTX_P1 6

P

EG_ARX_ GTX_N1 6

P

EG_ARX_ GTX_P2 6

P

EG_ARX_ GTX_N2 6

P

EG_ARX_ GTX_P3 6

P

EG_ARX_ GTX_N3 6

P

EG_ARX_ GTX_P4 6

P

EG_ARX_ GTX_N4 6

P

EG_ARX_ GTX_P5 6

P

EG_ARX_ GTX_N5 6

P

EG_ARX_ GTX_P6 6

P

EG_ARX_ GTX_N6 6

P

EG_ARX_ GTX_P7 6

P

EG_ARX_ GTX_N7 6

R

V374
100K_04 02_5%

D

IS@

D

GPU_PW ROK 92

P

D

GPU_PW RGOOD

V

DDCI_PG

A A

S

S

S

T

T

T
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1 2

V1660 0_0402_5 %@

R

1 2

R

V1661 0_0402_5 %@

ecurity Classif ication

ecurity Classif ication

ecurity Classif ication

I

I

I

ssued Date

ssued Date

ssued Date

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

D

GPU_PW RGOOD_R

C

C

C

ompal Secret Data

ompal Secret Data

2

2

2

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

3

ompal Secret Data

D

D

D

eciphered D ate

eciphered D ate

eciphered D ate

LT_RST_ VGA#

2

1 2

V1654 0_0402_5 %@

R

T

T

T

itle

itle

itle

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

C

C

C

ustom

ustom

ustom

Date: Sheet

Date: Sheet

Date: Sheet

D

GPU_PW ROK

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

ompal Electronics, Inc.

R

R

R

18M-G1-90_(1/9)_PCIE

18M-G1-90_(1/9)_PCIE

18M-G1-90_(1/9)_PCIE

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

1

1

1

A

A

A

o

o

o

f

27 99Wed nesday, May 15, 2019

f

27 99Wed nesday, May 15, 2019

f

27 99Wed nesday, May 15, 2019

1

5

+

3VSDGPU

12

S

2

G

6 1

D

V1A

Q

DIS@

Vgs=1.0-2.5V

0

0

12

V429

V426

RX560@

R

R

5.1K_0201_1%

12

@

V427

V428

R

R

5.1K_0201_1%

R
47K_0402_5%

DIS@

S

V314
C

1U_0201_6.3V6M

Voltage
Selected (V)

1.1

1.01

0.9

0.81

12

V432

RX560@

R

5.1K_0201_1%

12

@

V431
R

5.1K_0201_1%

5

G

E

C_SMB_DA28,58,66

D D

E

C_SMB_CK28,58,66

+

1.8VSDGPU

V87

V84

@

R

R

DIS@

10K_0402_5%

10K_0402_5%

1 2

1 2

2

V88

V89

C C

@

R

R

DIS@

10K_0402_5%

10K_0402_5%

1 2

1

2N7002KDW_SOT363-6

B00000EO00

S

@

V410
R

10K_0402_5%

1 2

@

V411
R

10K_0402_5%

1 2

3 4

D

V1B

Q

DIS@

2N7002KDW_SOT363-6

B00000EO00

S

G

PU_SVC

G

PU_SVD

G

PU_SVT

Boot-VID Code

SVD

SVC

0
0
1
1

R

X560 Strap

+

3VSDGPU

B B

12

@

V416
R

5.1K_0201_1%

12

V417

RX560@

R

5.1K_0201_1%

V414
R

5.1K_0201_1%

V415
R

5.1K_0201_1%

12

V418

RX560@

R

5.1K_0201_1%

12

@

V419
R

5.1K_0201_1%

G

PIO_2 can't use on R535

12

12

@

V422

V420

RX560@

R

R

5.1K_0201_1%

5.1K_0201_1%

12

12

@

V423

V421

RX560@

R

R

5.1K_0201_1%

5.1K_0201_1%

12

12

@

@

V424
R

5.1K_0201_1%

12

12

@

V425

RX560@

R

5.1K_0201_1%

V507

+

1.8VSDGPU

V412
R

1K_0402_5%

1

@

2

V1653
R

1K_0402_5%

12

12

@

@

V434
R

5.1K_0201_1%

5.1K_0201_1%

12

12

V433

RX560@

RX560@

R

5.1K_0201_1%

5.1K_0201_1%

SCL use 47k, CRB use 4.7k
AMD Confirm List_1027 use PU-47k

12

V508

R
47K_0402_5%

DIS@

V

GA_SMB_DA3

V

GA_SMB_CK3

SCL PU-1k

12

12

RX560@

12

@

V436
R

V435
R

V413

DIS@

R

1K_0402_5%

T

1

@

56109_Compatible List:

V315

2

R535 don't care, and Lexa PU.

C

1U_0201_6.3V6M

12

12

@

@

V438
R

5.1K_0201_1%

5.1K_0201_1%

1

12

@

@

V437
R

2

5.1K_0201_1%

5.1K_0201_1%

CRB PU-10k/PD-1uF
56109_Compatible List:
R535 PD, and Lexa PU.

T

EST_PG

EST_PG_BACO

12

@

V440
R

5.1K_0201_1%

12

V439

RX560@

R

5.1K_0201_1%

G
G

G
G
G

G
G
G
H
V
G
G
G

PIO_0
PIO_2

PIO_11
PIO_12
PIO_13

PIO_15
PIO_20
PIO_29
SYNC
SYNC
PIO_8
PIO_9
PIO_22

4

G

PU_SVC

G

G
G
G

TX_HALF_SWING[0:disable,1:enable]
BIF_GEN3_EN_A[0:disable,1:enable]

ROM_CONFIG_[0]/MemoryAperture
ROM_CONFIG_[1]/MemoryAperture
ROM_CONFIG_[2]/MemoryAperture

Reserved [PD for default]
TX_DEEMPH_EN[0:disable,1:enable]
BIF_VGA_DIS[0:VGA,1:Headless]
Special Usage[1] GPUdefault
Special Usage[0] GPUdefault
BIF_CLK_PM_EN[0:disable,1:enable]
Reserved [PD for production]
BIOS_ROM_EN[0:disable,1:enable]

PU_SVD

PU_SVC92
PU_SVD92

G

PU_SVT

PU_SVT92

1U_0201_6.3V6M

R

V155 0_0402_5%DIS@

V156 0_0402_5%DIS@

R

R

V157 0_0402_5%DIS@

+

DIS@

C

V26

1 2

1

1

3VSDGPU

1

2

V

GA_SMB_CK3

V

GA_SMB_DA3

2

2

T

EST_PG

T

EST_PG_BACO

3

V1E

U

1

0mA

@

AM31

AW40
AW41

AC35
AC34

AU17
AV17
AR17

AN34
AP31

AY13
BA13

K41
R34

s

DD_33

V

PIO_5_REG_HOT_AC_BATT

G

PIO_16_8P_DETECT

G

PIO_17_THERMAL_INT

G

CL

S

DA

S

MBCLK

S

MBDAT

S

PIO_SVC

G

PIO_SVD

G

PIO_SVT

G

DCVGACLK

D

DCVGADATA

D

EST_PG

T

EST_PG_BACO

T

SVD#K41

R

SVD#R34

R

REV 0.91

2160896088A1R16M_FCBGA769P-NH

ymbol5

PIO_6_TACH

G

PIO_8_ROMSO

G

PIO_9_ROMSI

G

PIO_10_ROMSCK

G

PIO_14_HPD2

G

PIO_18_HPD3

G

PIO_19_CTF

G

PIO_22_ROMCSB

G

ENERICA

G

ENERICB

G

ENERICC

G

ENERICD

G

ENERICE_HPD4

G

ENERICF_HPD5

G

ENERICG

G

C

L_ENABLE

B

L_PWM_DIM

B

WAPLOCKA

S

WAPLOCKB

S

ENLK_CLK

G

ENLK_VSYNC

G

PIO_0

G

PIO_1

G

PIO_2

G

PIO_11

G

PIO_12

G

PIO_13

G

PIO_15

G

PIO_20

G

PIO_21

G

PIO_29

G

PIO_30

G

H

LKREQB

AKEB

W

IGON

D

SYNC

H

SYNC

V

G

PIO_0

W40
AA40

G

PIO_2

AA35

V

GA_AC_BATT

AA34

G

PIO_6_TACH#

U35

G

PIO_8

AP25

G

PIO_9

AM25

G

PIO_10

AM27

G

PIO_11

W41

G

PIO_12

Y40

G

PIO_13

Y41
AU21

G

PIO_15

AA41
U34
R37
AV25

G

PIO_19_CTF

R38

G

PIO_20

AB40

G

PIO_21_PCC#

AB41

G

PIO_22

AP27

G

PIO_29

W37
W38

P

LL_ANALOG_IN

BA38
AV29
AU31
AV31
AU25
AV23
AM29

AV21

PD1

C

LKREQ_PEG#4_R

AV40
AU40

W

AKEB

AC40

AC37
AC38

W34

H

SYNC

W35

V

SYNC

AG34
AE34
AR29
AP29

1 2

R

D

V409 5.1K_0402_1%

IS@

1 2

V1652 5.1K _0402_1%

IS@

R

D

1 2

V1644 33_04 02_5%@

R

1 2

R

V1645 33_04 02_5%@

1 2

V1646 33_04 02_5%@

R

1

TP@

237

T

1

TP@

T

239

1 2

R

D

V91 5.1K_040 2_1%

IS@

1 2

R

V1647 33_04 02_5%@

1

TP@

T

231

1

TP@

241

T

1

TP@

T

240

1

TP@

T

234

V153

R
0_0402_5%

R

V368

10K_0402_5%

2

+

3VSDGPU

+

3VSDGPU

12

@

@

C

LKREQ_PEG#4 10

1

2

Function Support Pin

V

GA_AC_BATT

G

PIO_6_TACH#

G

PIO_21_PCC#

G

PIO_19_CTF

AC/DC Mode
H:AC L:DC

Thermal VR_HOT#
(Fan tachometer)

Peak Current Control

+

3VSDGPU+1.8VSDGPU

R

V502

10K_0201_5%@

1 2

DIS@

V151

R
10K_0201_5%

1 2

R

V1650

0_0402_5%

RX560@

V1651

R
0_0402_5%

@

1 2

GPIO5

GPIO6

GPIO21

RB751V-40_SOD323-2

D

RB751V-40_SOD323-2

D
RB751V-40_SOD323-2

12

12

R

V152

10K_0201_5%@

SCL can leave ncVDD_33

D

V1

V2

V4

R

18M-M2-60

Yes

No

No

DIS@

DIS@

DIS@

1

R17M-G1-50/70
R17M-P1-50/70
R18M-G1-90

Yes

Yes

Yes

12

12

12

W

AKEB

+

3VSDGPU

12

V162

R

4.7K_0402_5%

@

12

R

V430

4.7K_0402_5%

@

G

PU_ACIN 58

G

PU_PROCHOT# 92

A

PU_PROCHOT#_D 84

G

PU_THERMAL# 58

G

PU_PCC# 58

A A

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

2

2

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

R

R

R

18M-G1-90_(2/9)_MSIC-1

18M-G1-90_(2/9)_MSIC-1

18M-G1-90_(2/9)_MSIC-1

ustom

ustom

ustom

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

1

o

o

o

f

28 99Wednesday, May 15, 2019

f

28 99Wednesday, May 15, 2019

f

28 99Wednesday, May 15, 2019

1

1

1

A

A

A

5

+

1.8VSDGPU

V468

DIS@

R

10K_0201_5%

1 2

D D

U

V1F

@

s

ymbol6

X

P

REV 0.91

LLCHARZ_L

P

LLCHARZ_H

A

NALOGIO

C C

2160896088 A1R16M_FCBGA769P-NH

V467
R

X

TALIN

TALOUT

10K_0201_5%

2

DIS@

1

4

V101 33_02 01_5%

R

R

V100 33_02 01_5%

R

V469

BA39

AY39

AV15
AU15

AY38

1 2

DIS@

1 2

DIS@

1

DIS@

10K_0402_5%

TALIN

X

1

TP@

1

TP@

12

V83

R

16.2K_0402_1 %@

DNI

AA38
AA37

2

B2

229

T

T

230

U

V1A

@

s

ymbol1

J

TAG_TDO
J

TAG_TDI

J

TAG_TMS

J

TAG_TCK

T

J

TAG_TRSTB

EV 0.91

ESTEN

AF41
AD40
AD41
AE41

AE40
AF40

X

B

P_0

B

P_1

T

EST6

R

2160896088 A1R16M_FCBGA769P-NH

TAG_TDO_GPU

J

TAG_TDI_GPU

J

TAG_TMS_GPU

J

TAG_TCK_GPU

J

TAG_TESTEN_GPU

J

TAG_TRSTB_GPU

J

TALIN

15P_0402_50 V8J

R

V506

0_0402_5%

2

R

X560@

3

TAG_TDI_GPU

J

TAG_TDO_GPU

J

TAG_TMS_GPU

J

TAG_TCK_GPU

J

TAG_TRSTB_GPU

J

TAG_TESTEN_GPU

J

DIS@

C

V450

1

R

V1655 10K_0201_5%@

R

V1656 10K_0201_5%@

V1657 10K_0201_5%@

R

V1658 10K_0201_5%@

R

R
R

TALIN_R

X

2

7MHZ_10PF_XRCGB27 M000F2P18R0

12

TALOUT_R

X

TALIN_100M

X

12
12

12
12

V369 10K_0201_5%DIS@
V1630 10K_0201_5%@

3

12
12

R
R

Y

12

V470 5.1K_0201_1 %@

2

1

V471 1K_0201_5 %DIS@

X

D

V1

IS@

S

J10000UI00

3

1

N

N

C

C

2

4

X560@

R

UV4

3

OUT

X

4

SCLK1/REFCLK/FSEL/SSONb/OE

S

I51214-A1FAGMR_TDFN6_ 1P2X1P4

S

A0000A4K00

S

S IC SI51214-A1FAGMR TDFN 6P CLK GEN

TALOUT_R

1

+

3VSDGPU

+

3VSDGPU

+

3VSDGPU

ESR:40ohm (Max)

12

DIS@

V451

C
15P_0402_50 V8J

IN/CLKIN

X

SCLK2/OE/SSONb/PD

S

2

+

1.8VSDGPU

I_SS_SEL

S

2

1

DD

V

5

6

SS

V

1 2

R

D

V154 5.1K_0402_1 %

IS@

1 2

R

@

V505 5.1K_0402_1 %

TALIN_R

X

1.8VSDGPU_VDD

+

I_SS_SEL

S

C

0.1U_0201_10V6K
V2723

1

2

@

+

V7

X560@

L

R

BLM15BD121SN 1D_0402

1 2

C

10U_0402_6.3V6M

V449

1

2

RX560@

1.8VSDGPU

1

+

B B

V1K

U

@

ymbol11

s

BGDATA_0

D

BGDATA_1

D

BGDATA_2

D

BGDATA_3

D

BGDATA_4

D

BGDATA_5

D

BGDATA_6

D

BGDATA_7

D

BGDATA_8

D

BGDATA_9

D

BGDATA_10

D

BGDATA_11

D

BGDATA_12

D

BGDATA_13

D

BGDATA_14

D

BGDATA_15

D

REV 0.91

2160896088 A1R16M_FCBGA769P-NH

A A

BGDATA_0

D

L40

BGDATA_1

D

L41

BGDATA_2

D

M40

BGDATA_3

D

M41

BGDATA_4

D

N40

BGDATA_5

D

N41

BGDATA_6

D

P40

BGDATA_7

D

P41

BGDATA_8

D

R40
R41
T40
T41
U40
U41
V40
V41

5

BGDATA_9

D

BGDATA_10

D

BGDATA_11

D

BGDATA_12

D

BGDATA_13

D

BGDATA_14

D

BGDATA_15

D

1

TP@

T

221

1

TP@

T

222

1

TP@

223

T

1

TP@

224

T

1

TP@

225

T

1

TP@

T

226

1

TP@

T

227

1

TP@

228

T

1.8VSDGPU

1

V456

RX560@

R

5.1K_0201_1%

2

12

@

V455
R

5.1K_0201_1%

A

UD_PORT_CONN[2:0]

111: No usable endpoints

1

12

12

V457

V453

RX560@

RX560@

R

R

5.1K_0201_1%

5.1K_0201_1%

1

12

@

@

V454

V458
R

R

5.1K_0201_1%

5.1K_0201_1%

2

4

12

1

@

@

V459
R

5.1K_0201_1%

2

12

@

V460
R

5.1K_0201_1%

@

V461

V463
R

R

5.1K_0201_1%

5.1K_0201_1%

2

12

12

@

@

V464

V462
R

R

5.1K_0201_1%

5.1K_0201_1%

12

12

@

V465

V442

RX560@

R

R

5.1K_0201_1%

5.1K_0201_1%

BGDATA_0

D

AUD_PORT_CONN[0]

BGDATA_1

D

AUD_PORT_CONN[1]

BGDATA_2

D

AUD_PORT_CONN[2]

BGDATA_3

D

BOARD_CONFIG[0]

BGDATA_4

D

BOARD_CONFIG[1]

BGDATA_5

D

BOARD_CONFIG[2]

BGDATA_6

D

SMBUS_ADDR[0]

BGDATA_7

D

SMBUS_ADDR[1]

12

12

@

V466

V441

RX560@

R

R

5.1K_0201_1%

5.1K_0201_1%

*

110: One usable endpoint
101: Two usable endpoints
100: Three usable endpoints
011: Four usable endpoints
010: Five usable endpoints
001: Six usable endpoints
000: All endpoints are usable

B

OARD_CONFIG[2:0]

000:SAM 256Mx32 (8Gb)
001:Hynix 256Mx32 (8Gb)
010:
011:
100:
101:
110:
111:

(BOM at Page33)

D

BGDATA_[7:6]

00: 0×40
01: 0×41

*

10: 0×42
11: 0×43

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

2

2

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered Date

eciphered Date

eciphered Date

2

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

ustom

ustom

ustom

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

R

R

R

18M-G1-90_(3/9)_MSIC-2

18M-G1-90_(3/9)_MSIC-2

18M-G1-90_(3/9)_MSIC-2

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

1

o

o

o

f

29 99Wednesday, May 15, 2019

f

29 99Wednesday, May 15, 2019

f

29 99Wednesday, May 15, 2019

1

1

1

A

A

A

5

U

V1C

M

A0_D[0..31]35

D D

M

A0_A[0..8]35

C C

M

A0_WCK0135

M

A0_WCK01#35

M

A0_WCK2335

M

A0_WCK23#35

M

A0_EDC03 5

M

A0_EDC13 5

M

A0_EDC23 5

M

A0_EDC33 5

M

A0_DBI#035

M

A0_DBI#135

M

A0_DBI#235

M

A0_DBI#335

M

A0_ADBI35

M

A0_CS#35

A0_D0

M

A0_D1

M

A0_D2

M

A0_D3

M

A0_D4

M

A0_D5

M

A0_D6

M

A0_D7

M

A0_D8

M

A0_D9

M

A0_D10

M

A0_D11

M

A0_D12

M

A0_D13

M

A0_D14

M

A0_D15

M

A0_D16

M

A0_D17

M

A0_D18

M

A0_D19

M

A0_D20

M

A0_D21

M

A0_D22

M

A0_D23

M

A0_D24

M

A0_D25

M

A0_D26

M

A0_D27

M

A0_D28

M

A0_D29

M

A0_D30

M

A0_D31

M

A0_A0

M

A0_A1

M

A0_A2

M

A0_A3

M

A0_A4

M

A0_A5

M

A0_A6

M

A0_A7

M

A0_A8

M

A0_WCK01

M

A0_WCK01#

M

A0_WCK23

M

A0_WCK23#

M

A0_EDC0

M

A0_EDC1

M

A0_EDC2

M

A0_EDC3

M

M

A0_DBI#0

A0_DBI#1

M

A0_DBI#2

M

A0_DBI#3

M

M

A0_ADBI

M

A0_CS#

@

L34

D

QA0_0

L37

D

QA0_1

L38

D

QA0_2

J35

D

QA0_3

G37

D

QA0_4

E38

D

QA0_5

E35

D

QA0_6

D35

D

QA0_7

H41

D

QA0_8

H40

D

QA0_9

G41

D

QA0_10

G40

D

QA0_11

E40

D

QA0_12

D41

D

QA0_13

D40

D

QA0_14

C41

D

QA0_15

C40

D

QA0_16

B39

D

QA0_17

A39

D

QA0_18

B38

D

QA0_19

B36

D

QA0_20

A36

D

QA0_21

B35

D

QA0_22

A35

D

QA0_23

B33

D

QA0_24

B32

D

QA0_25

A32

D

QA0_26

B31

D

QA0_27

A30

D

QA0_28

B29

D

QA0_29

B28

D

QA0_30

A28

D

QA0_31

G25

M

AA0_0

H25

M

AA0_1

E27

M

AA0_2

D27

M

AA0_3

D29

M

AA0_4

H27

M

AA0_5

H23

M

AA0_6

E23

M

AA0_7

D25

M

AA0_8

H29

M

AA0_9

D33

W

CKA0_0

E33

W

CKA0B_0

A34

W

CKA0_1

B34

W

CKA0B_1

G38

E

DCA0_0

F41

E

DCA0_1

B37

E

DCA0_2

A31

E

DCA0_3

J38

D

DBIA0_0

F40

D

DBIA0_1

A38

D

DBIA0_2

B30

D

DBIA0_3

H21

A

DBIA0

H31

C

SA0B_0

s

ymbol3

D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D

W

W

CKA1B_0

W

W

CKA1B_1

E
E
E
E

D
D
D
D

C

D

QA1_0

D

QA1_1

D

QA1_2

D

QA1_3

D

QA1_4

D

QA1_5

D

QA1_6

D

QA1_7

D

QA1_8

D

QA1_9
QA1_10
QA1_11
QA1_12
QA1_13
QA1_14
QA1_15
QA1_16
QA1_17
QA1_18
QA1_19
QA1_20
QA1_21
QA1_22
QA1_23
QA1_24
QA1_25
QA1_26
QA1_27
QA1_28
QA1_29
QA1_30
QA1_31

M

AA1_0
M

AA1_1
M

AA1_2
M

AA1_3
M

AA1_4
M

AA1_5
M

AA1_6
M

AA1_7
M

AA1_8
M

AA1_9

CKA1_0

CKA1_1

DCA1_0
DCA1_1
DCA1_2
DCA1_3

DBIA1_0
DBIA1_1
DBIA1_2
DBIA1_3

A

DBIA1

SA1B_0

4

M

A1_D0

B27
A27
B26
A26
A24
B23
A23
B22
B20
A20
B19
A19
B17
A16
B16
A15
B15
A14
B14
B13
A11
B11
A10
B10
B8
A7
B7
A6
A4
B4
A3
B3

E15
H15
G13
D13
H11
H13
H17
G17
D15
E11

A22
B21

A8
B9

B24
A18
B12
B6

B25
B18
A12
B5

H19

E7

M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M

M
M
M
M
M
M
M
M
M

A1_WCK01

M

A1_WCK01#

M

A1_WCK23

M

A1_WCK23#

M

M

A1_EDC0

A1_EDC1

M

A1_EDC2

M

A1_EDC3

M

M

A1_DBI#0

A1_DBI#1

M

A1_DBI#2

M

A1_DBI#3

M

M

A1_ADBI

M

A1_CS#

A1_D1
A1_D2
A1_D3
A1_D4
A1_D5
A1_D6
A1_D7
A1_D8
A1_D9
A1_D10
A1_D11
A1_D12
A1_D13
A1_D14
A1_D15
A1_D16
A1_D17
A1_D18
A1_D19
A1_D20
A1_D21
A1_D22
A1_D23
A1_D24
A1_D25
A1_D26
A1_D27
A1_D28
A1_D29
A1_D30
A1_D31

A1_A0
A1_A1
A1_A2
A1_A3
A1_A4
A1_A5
A1_A6
A1_A7
A1_A8

A1_D[0..31] 35

M

A1_A[0..8] 35

M

A1_WCK01 35

M

A1_WCK01# 3 5

M

A1_WCK23 35

M

A1_WCK23# 3 5

M

A1_EDC0 35

M

A1_EDC1 35

M

A1_EDC2 35

M

A1_EDC3 35

M

A1_DBI#0 35

M

A1_DBI#1 35

M

A1_DBI#2 35

M

A1_DBI#3 35

M

A1_ADBI 35

M

A1_CS# 35

3

M

B0_D[0..31]36

M

B0_A[0..8]36

M

B0_WCK0136

M

B0_WCK01 #36

M

B0_WCK2336

M

B0_WCK23 #36

M

B0_EDC03 6

M

B0_EDC13 6

M

B0_EDC23 6

M

B0_EDC33 6

M

B0_DBI#036

M

B0_DBI#136

M

B0_DBI#236

M

B0_DBI#336

M

B0_ADBI36

M

B0_CS#36

B0_D0

M

B0_D1

M

B0_D2

M

B0_D3

M
M

B0_D4

M

B0_D5

M

B0_D6

M

B0_D7

M

B0_D8

M

B0_D9

M

B0_D10

M

B0_D11

M

B0_D12

M

B0_D13

M

B0_D14

M

B0_D15

M

B0_D16

M

B0_D17

M

B0_D18

M

B0_D19

M

B0_D20

M

B0_D21

M

B0_D22

M

B0_D23

M

B0_D24

M

B0_D25

M

B0_D26

M

B0_D27

M

B0_D28

M

B0_D29

M

B0_D30

M

B0_D31

B0_A0

M
M

B0_A1

M

B0_A2

M

B0_A3

M

B0_A4

M

B0_A5

M

B0_A6

M

B0_A7

M

B0_A8

B0_WCK01

M

B0_WCK01 #

M

B0_WCK23

M

B0_WCK23 #

M

B0_EDC0

M

B0_EDC1

M
M

B0_EDC2

M

B0_EDC3

B0_DBI#0

M
M

B0_DBI#1

M

B0_DBI#2

M

B0_DBI#3

B0_ADBI

M

B0_CS#

M

2

U

V1D

@

s

ymbol4

C2

QB0_0

D

C1

QB0_1

D

D2

QB0_2

D

D1

QB0_3

D

F1

QB0_4

D

G2

QB0_5

D

G1

QB0_6

D

H2

QB0_7

D

K2

QB0_8

D

K1

QB0_9

D

L2

QB0_10

D

L1

QB0_11

D

N2

QB0_12

D

P2

QB0_13

D

P1

QB0_14

D

R2

QB0_15

D

R1

QB0_16

D

T2

QB0_17

D

T1

QB0_18

D

U2

QB0_19

D

W1

QB0_20

D

W2

QB0_21

D

Y1

QB0_22

D

Y2

QB0_23

D

AB2

QB0_24

D

AC1

QB0_25

D

AC2

QB0_26

D

AD1

QB0_27

D

AF1

QB0_28

D

AF2

QB0_29

D

AG1

QB0_30

D

AG2

QB0_31

D

R5

AB0_0

M

R8

AB0_1

M

N7

AB0_2

M

N4

AB0_3

M

L8

AB0_4

M

N8

AB0_5

M

U8

AB0_6

M

U7

AB0_7

M

R4

AB0_8

M

L5

AB0_9

M

H1

CKB0_0

W

J2

CKB0B_0

W

AB1

CKB0_1

W

AA2

CKB0B_1

W

F2

E

DCB0_0

M2

DCB0_1

E

V1

DCB0_2

E

AD2

DCB0_3

E

E2

D

DBIB0_0

M1

D

DBIB0_1

V2

D

DBIB0_2

AE2

D

DBIB0_3

W8

A

DBIB0

G5

C

SB0B_0

D
D
D
D
D
D
D
D
D

D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D

M

M

M

M

M

M

M

M

M

M

W

CKB1B_0

W

W

CKB1B_1

W

E
E
E
E

D

DBIB1_0

D

DBIB1_1

D

DBIB1_2

D

DBIB1_3

C

QB1_0
QB1_1
QB1_2
QB1_3
QB1_4
QB1_5
QB1_6
QB1_7
QB1_8

QB1_9
QB1_10
QB1_11
QB1_12
QB1_13
QB1_14
QB1_15
QB1_16
QB1_17
QB1_18
QB1_19
QB1_20
QB1_21
QB1_22
QB1_23
QB1_24
QB1_25
QB1_26
QB1_27
QB1_28
QB1_29
QB1_30
QB1_31

AB1_0
AB1_1
AB1_2
AB1_3
AB1_4
AB1_5
AB1_6
AB1_7
AB1_8
AB1_9

CKB1_0

CKB1_1

DCB1_0
DCB1_1
DCB1_2
DCB1_3

A

DBIB1

SB1B_0

AH1
AH2
AJ2
AK1
AL2
AM1
AM2
AN2
AR1
AR2
AT1
AT2
AV2
AW1
AW2
AY3
BA3
AY4
BA4
AY5
BA7
AY7
AY8
BA8
AR4
AR5
AU4
AU7
AN8
AV11
AU11
AP11

AE7
AE8
AG5
AG4
AJ4
AG8
AC8
AC5
AE4
AJ8

AP1
AP2

AN4
AN5

AL1
AU2
BA6
AV7

AK2
AV1
AY6
AV9

AA8

AL8

B1_D0

M
M

B1_D1

M

B1_D2

M

B1_D3

M

B1_D4

M

B1_D5

M

B1_D6

M

B1_D7

M

B1_D8

M

B1_D9

M

B1_D10

M

B1_D11

M

B1_D12

M

B1_D13

M

B1_D14

M

B1_D15

M

B1_D16

M

B1_D17

M

B1_D18

M

B1_D19

M

B1_D20

M

B1_D21

M

B1_D22

M

B1_D23

M

B1_D24

M

B1_D25

M

B1_D26

M

B1_D27

M

B1_D28

M

B1_D29

M

B1_D30

M

B1_D31

B1_A0

M
M

B1_A1

M

B1_A2

M

B1_A3

M

B1_A4

M

B1_A5

M

B1_A6

M

B1_A7

M

B1_A8

B1_WCK01

M

B1_WCK01 #

M

B1_WCK23

M

B1_WCK23 #

M

B1_EDC0

M
M

B1_EDC1

M

B1_EDC2

M

B1_EDC3

B1_DBI#0

M
M

B1_DBI#1

M

B1_DBI#2

M

B1_DBI#3

B1_ADBI

M

B1_CS#

M

M
M

M
M

M
M
M
M

M
M
M
M

M

M

M

B1_D[0..31] 36

M

B1_A[0..8] 36

B1_WCK01 36
B1_WCK01 # 36

B1_WCK23 36
B1_WCK23 # 36

B1_EDC0 36
B1_EDC1 36
B1_EDC2 36
B1_EDC3 36

B1_DBI#0 36
B1_DBI#1 36
B1_DBI#2 36
B1_DBI#3 36

B1_ADBI 36

B1_CS# 36

1

B0_CAS#

M

M

A0_CAS#35

M

B B

M

A_VRAMRST#35

A A

A0_RAS#35

M

A0_WE#35

M

A0_CKE35

M

A0_CLK35

M

A0_CLK#35

R

49.9_0402_1%

1

120P_0402_5 0V8J

Place close to GPU (within 25mm)
and place componment within (5mm) close to each other

5

A0_CAS#

M

A0_RAS#

A0_WE#

M

M

A0_CKE

M

A0_CLK

M

A0_CLK#

1 2

V39 120_0402_1%

IS@

R

D

A_VRAMRST#_G

M

V36

IS@

D

V37

R
10_0402_1%

2

IS@

D

1

IS@

D

V96

C

2

12

IS@

D

V38

R

5.1K_0402_1%

D23

C

D21

R

G29

W

G21

C

E31

C

D31

C

K15

M

L32

D

2160896088 A1R16M_FCBGA769P-NH

ASA0B
ASA0B

EA0B

KEA0

LKA0
LKA0B

EM_CALRA

RAM_RSTA

A_VRAMRST#_G

M

C
R

C

M

VREFDA

REV 0.91

ASA1B

W

C

C
LKA1B

1

2

ASA1B

EA1B

KEA1

LKA1

D17
D19
D11

E19

D7
D9

K17

4

M

A_VREFD

M

A1_CAS#

M

A1_RAS#

A1_WE#

M

A1_CKE

M

M

A1_CLK

M

A1_CLK#

A_VREFD

M

40.2_0402_1%

100_0402_1 %

D

R

D

R

IS@

V32

IS@

V35

+

1.5VSDGPU

12

1

2

M

A1_CAS# 35

M

A1_RAS# 35

M

A1_WE# 35

M

A1_CKE 35

M

A1_CLK 35

M

A1_CLK# 35

DIS@

1

C

V486

1U_0201_6.3V6M

2

M

B0_CAS#36

M

B0_RAS#36

M

B0_WE#36

M

B0_CKE36

M

B0_CLK36

M

B0_CLK#36

M

B_VRAMRST#36

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

1 2

Place close to GPU (within 25mm)
and place componment within (5mm) close to each other

M

B0_RAS#

M

B0_WE#

M

B0_CKE

M

B0_CLK

M

B0_CLK#

M

2

1

V1633 120_0402_1%

X560@

R

R

B_VRAMRST#_G

M

V1641

R

49.9_0402_1%

X560@

R

120P_0402_5 0V8J

2

2

2

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

V1642

R
10_0402_1%

2

X560@

R

1

X560@

R

V2720

C

2

C

C

C

U4

W4

L4

W5

G4

J4

R10

AM11

1

12

X560@

R

V1643

R

5.1K_0402_1%

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered Date

eciphered Date

eciphered Date

C

ASB0B

ASB0B

R

EB0B

W

C

KEB0

C

LKB0

C

LKB0B

EM_CALRB

M

RAM_RSTB

D

2160896088 A1R16M_FCBGA769P-NH

M

B_VRAMRST#_G

2

M

REV 0.91

C

ASB1B

ASB1B

R

EB1B

W

C

KEB1

C

LKB1

C

LKB1B

VREFDB

AC4

AA4
AJ7

AA7

AL5
AL4

U10

B1_CAS#

M

B1_RAS#

M

B1_WE#

M

B1_CKE

M

B1_CLK

M

B1_CLK#

M

B_VREFD

M

40.2_0402_1%

M

B_VREFD

100_0402_1 %

T

T

T

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet

Date: Sheet

Date: Sheet

M

B1_CAS# 36

M

B1_RAS# 36

M

B1_WE# 36

M

B1_CKE 36

M

B1_CLK 36

M

B1_CLK# 36

+

1.5VSDGPU

12

IS@

D

V1635

R

1

IS@

D

V1634

R

itle

itle

itle

R

R

R

18M-G1-90_(4/9)_MEM

18M-G1-90_(4/9)_MEM

18M-G1-90_(4/9)_MEM

ustom

ustom

ustom

DIS@

1

V487

C
1U_0201_6.3V6M

2

2

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

ompal Electronics, Inc.

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

1

1

1

1

A

A

A

o

o

o

f

30 99Wednesday, May 15, 2019

f

30 99Wednesday, May 15, 2019

f

30 99Wednesday, May 15, 2019

5

4

3

2

1

U

V1G

@

s

D D

C C

U

V1O

@

s

ymbol15

T

X2P_DPE0P

T

X2M_DPE0N

T

X1P_DPE1P

T

X1M_DPE1N

T

X0P_DPE2P

T

X0M_DPE2N

T

XCEP_DPE3P

T

XCEM_DPE3N

B B

REV 0.91

2160896 088A1R16M_FC BGA769P-NH

D

DCAUX5P

D

DCAUX5N

AY18

BA18

AY16

BA16

AY15

BA15

AY14

BA14

AU27

AV27

1

1

TP@

TP@

2

T

243

T

242

DIS@

R

V372

150_040 2_1%

1

BA12

ymbol7

T

X2P_DPB0P

T

X2M_DPB0N

T

X1P_DPB1P

T

X1M_DPB1N

T

X0P_DPB2P

T

X0M_DPB2N

T

XCBP_DPB3P

T

XCBM_DPB3N

D

DCAUX3P

D

DCAUX3N

T

X5P_DPA0P

T

X5M_DPA0N

T

X4P_DPA1P

T

X4M_DPA1N

T

X3P_DPA2P

T

X3M_DPA2N

T

XCAP_DPA3P

T

XCAM_DPA3N

A

UX_ZVSS

D

REV 0.91

2160896 088A1R16M_FC BGA769P-NH

DCAUX4P

D

DCAUX4N

AY32

BA32

AY31

BA31

AY30

BA30

AY28

BA28

AM21

AP21

AY36

BA36

AY35

BA35

AY34

BA34

AY33

BA33

AR23

AP23

1

TP@

U

V1H

@

s

ymbol8

T

238

R

EV 0.91

2160896 088A1R16M_FC BGA769P-NH

T

X2P_DPD0P

T

X2M_DPD0N

T

X1P_DPD1P

T

X1M_DPD1N

T

X0P_DPD2P

T

X0M_DPD2N

T

XCDP_DPD3P

T

XCDM_DPD3N

A

A

D

DC1CLK

D

DC1DATA

T

X5P_DPC0P

T

X5M_DPC0N

T

X4P_DPC1P

T

X4M_DPC1N

T

X3P_DPC2P

T

X3M_DPC2N

T

XCCP_DPC3P

T

XCCM_DPC3N

A

A

D

DC2CLK

D

DC2DATA

UX1P

UX1N

UX2P

UX2N

AY22

BA22

AY21

BA21

AY20

BA20

AY19

BA19

AY11

BA11

AY10

BA10

AY27

BA27

AY26

BA26

AY25

BA25

AY24

BA24

AP19

AM19

AV19

AU19

1

TP@

1

TP@

1

TP@

1

TP@

T

236

T

232

T

235

T

233

D

ata Book:need
config even if not
use display function

A A

S

S

S

eeecccuuurrriiitttyyy CCClllaaasss sssiiifffiiicccaaatttiiiooonnn

2

2

2

I

I

I

ssussussueeeddd DDDaaattteee

T

T

T

HHHIIISSS SSSHHHEEEEEETTT OOOFFF EEENNNGGGIIINNNEEEEEERRRIIINNNGGG DDDRRRAAAWWWIIINNNGGG IIISSS TTTHHHEEE PPPRRROOOPPPRRRIIIEEETTTAAARRRYYY PPPRRROOOPPPEEERRRTTTYYY OOOFFF CCCOOOMMMPPPAAALLL EEELLLEEECCCTTTRRROOONNNIIICCCSSS,,, IIINNNCCC... AAANNNDDD CCCOOONNNTTTAAAIIINNNSSS CCCOOONNNFFFIIIDDDEEENNNTTTIIIAAALLL
AAANNNDDD TTTRRRAAADDDEEE SSSEEECCCRRREEETTT IIINNNFFFOOORRRMMMAAATTTIIIOOONNN... TTTHHHIIISSS SSSHHHEEEEEETTT MMMAAAYYY NNNOOOTTT BBBEEE TTTRRRAAANNNSSSFFFEEERRREEEDDD FFFRRROOOMMM TTTHHHEEE CCCUUUSSSTTTOOODDDYYY OOOFFF TTTHHHEEE CCCOOOMMMPPPEEETTTEEENNNTTT DDDIIIVVVIIISSSIIIOOONNN OOOFFF RRR&&&DDD
DDDEEEPPPAAARRRTTTMMMEEENNNTTT EEEXXXCCCEEEPPPTTT AAASSS AAAUUUTTTHHHOOORRRIIIZZZEEEDDD BBBYYY CCCOOOMMMPPPAAALLL EEELLLEEECCCTTTRRROOONNNIIICCCSSS,,, IIINNNCCC... NNNEEEIIITTTHHHEEERRR TTTHHHIIISSS SSSHHHEEEEEETTT NNNOOORRR TTTHHHEEE IIINNNFFFOOORRRMMMAAATTTIIIOOONNN IIITTT CCCOOONNNTTTAAAIIINNNSSS

5

4

MMMAAAYYY BBBEEE UUUSSSEEEDDD BBBYYY OOORRR DDDIIISSSCCCLLLOOOSSSEEEDDD TTTOOO AAANNNYYY TTTHHHIIIRRRDDD PPPAAARRRTTTYYY WWWIIITTTHHHOOOUUUTTT PPPRRRIIIOOORRR WWWRRRIIITTTTTTEEENNN CCCOOONNNSSSEEENNNTTT OOOFFF CCCOOOMMMPPPAAALLL EEELLLEEECCCTTTRRROOONNNIIICCCSSS,,, IIINNNCCC...

000111888/// 111222///111888 222000 111999///111222///111888

3

C

C

C

ooommmpppaaalll SSSeeecccrrreeettt DDDaaatttaaa

D

D

D

eeeccciiippphhheeerrreeeddd DDDaaattteee

C

C

C

T

T

T

iiitttllleee

R

R

R

SSSiiizzzeee DDDooocccuuummmeeennnttt NNNuuu mmmbbbeeerrr RRReeevvv

C

C

C

uuussstttooommm

2

DDDaaattteee::: SSShhh eeeeeettt

ooommmpppaaalll EEEllleeeccctttrrrooonnniiicccsss,,, IIInnnccc...

111888MMM---GGG111---999000___(((555///999)))___DIDIDISSSPPPLLLAAAYYY

F

F

F

H5H5H5000PPP MMM///BBB LLLAAA---H9H9H9000111PPP

1

1

1

1

AAA

o

o

o

fff

333111 999999WWWeeedddnnneeesssdddaaayyy,,, MMMaaayyy 111555,,, 222 000111999

5

4

3

2

1

1

V3311 U_0201_6.3V6M
C

DIS@

2

G

PU_VDDCI_SEN 92

G

PU_VDDC_SEN 92

G

PU_VSS_SEN_L 92

SCL:1u x7

1

1

V3561U_0201_6 .3V6M
C

DIS@

2

2

+

VDDCI

V33622U_0603_6.3V6M

V33522U_0603_6.3V6M

C

C

IS@

IS@

1 2

1 2

D

D

+

1.8VSDGPU

Close to AM15, AP15, AR15

1

1

1

V3511U_0201_6 .3V6M

V3501U_0201_6 .3V6M

V3491U_0201_6 .3V6M

C

C

C

DIS@

DIS@

DIS@

2

2

+

VDDCI

1

1

V3581U_0201_ 6.3V6M

V3571U_0201_6 .3V6M

C

C

DIS@

DIS@

2

2

3

2

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

2

2

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

V1L

U

@

ymbol12

s

A2

SS#0

V

A5

SS#1

V

A9

SS#2

V

A13

SS#3

V

A17

SS#4

V

A21

SS#5

V

A25

SS#6

V

A29

SS#7

V

A33

SS#8

V

A37

SS#9

V

A40

SS#10

V

B1

SS#11

V

B40

SS#12

V

B41

SS#13

V

C5

SS#14

V

C7

SS#15

V

C9

SS#16

V

C11

SS#17

V

C13

SS#18

V

C15

SS#19

V

C17

SS#20

V

C19

SS#21

V

C21

SS#22

V

C23

SS#23

V

C25

SS#24

V

C27

SS#25

V

C29

SS#26

V

C31

SS#27

V

C33

SS#28

V

C35

SS#29

V

C37

SS#30

V

C39

SS#31

V

E1

SS#32

V

E3

SS#33

V

E4

SS#34

V

E9

SS#35

V

E13

SS#36

V

E17

SS#37

V

E21

SS#38

V

E25

SS#39

V

E29

SS#40

V

E39

SS#41

V

E41

SS#42

V

G3

SS#43

V

G7

SS#44

V

G11

SS#45

V

G15

SS#46

V

G19

SS#47

V

G23

SS#48

V

G27

SS#49

V

G31

SS#50

V

G35

SS#51

V

G39

SS#52

V

J1

SS#53

V

J3

SS#54

V

J5

SS#55

V

J34

SS#56

V

J37

SS#57

V

REV 0.91

2160896088A1R16M_FCBGA769P-NH

U

V1M

@

s

AA10

AA17
AA19
AA25
AA27
AA32
AA39

AC11
AC17
AC19
AC25
AC27
AC39

AE10
AE17
AE19
AE25
AE27
AE32
AE35
AE39

AG11
AG17
AG19
AG25
AG27
AG39
AG40
AG41

AN35
AN39

AA5

AC3
AC7

AE1
AE3
AE5

AG3
AG7

AJ1
AJ3

AJ5
AJ10
AJ11
AJ35
AJ39

AL3

AL7
AL10
AL11
AL32
AL35
AL39

AN1

AN3

AN7

ymbol13

SS#115

V

SS#116

V

V

SS#117

V

SS#118

V

SS#119

V

SS#120

V

SS#121

V

SS#122

V

SS#123

V

SS#124

V

SS#125

V

SS#126

V

SS#127

V

SS#128

V

SS#129

V

SS#130

V

SS#131

V

SS#132

V

SS#133

V

SS#134

V

SS#135

V

SS#136

V

SS#137

V

SS#138

V

SS#139

V

SS#140

V

SS#141

V

SS#142

V

SS#143

V

SS#144

V

SS#145

V

SS#146

V

SS#147

V

SS#148

V

SS#149

V

SS#150

V

SS#151

V

SS#152

V

SS#153

V

SS#154

V

SS#155

V

SS#156

V

SS#157

V

SS#158

V

SS#159

V

SS#160

V

SS#161

V

SS#162

V

SS#163

V

SS#164

V

SS#165

V

SS#166

V

SS#167

V

SS#168

V

SS#169

V

SS#170

REV 0.91

2160896088A1R16M_FCBGA769P-NH

T

T

T

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

J39

SS#58

V

J40

SS#59

V

J41

SS#60

V

K21

SS#61

V

K25

SS#62

V

K29

SS#63

V

K40

SS#64

V

L3

SS#65

V

L7

SS#66

V

L11

SS#67

V

L15

SS#68

V

L19

V

SS#69

L23

SS#70

V

L27

V

SS#71

L31

V

SS#72

L35

V

SS#73

L39

V

SS#74

N1

V

SS#75

N3

V

SS#76

N5

V

SS#77

N17

V

SS#78

N19

V

SS#79

N25

V

SS#80

N27

V

SS#81

N32

V

SS#82

N37

V

SS#83

N39

V

SS#84

R3

V

SS#85

R7

V

SS#86

R11

V

SS#87

R17

V

SS#88

R19

V

SS#89

R25

V

SS#90

R27

V

SS#91

R32

V

SS#92

R35

V

SS#93

R39

V

SS#94

U1

V

SS#95

U3

V

SS#96

U5

V

SS#97

U17

V

SS#98

U19

V

SS#99

U25

V

SS#100

U27

V

SS#101

U32

V

SS#102

U37

V

SS#103

U39

V

SS#104

W3

V

SS#105

W7

V

SS#106

W11

V

SS#107

W17

V

SS#108

W19

V

SS#109

W25

V

SS#110

W27

V

SS#111

W39

V

SS#112

AA1

V

SS#113

AA3

V

SS#114

AN40

V

SS#171

AN41

V

SS#172

AP13

V

SS#173

AP17

V

SS#174

AR3

SS#175

V

AR7

SS#176

V

AR11

SS#177

V

AR19

SS#178

V

AR21

SS#179

V

AR25

SS#180

V

AR27

SS#181

V

AR31

SS#182

V

AR35

SS#183

V

AR39

SS#184

V

AU1

SS#185

V

AU3

SS#186

V

AU9

SS#187

V

AU23

SS#188

V

AU29

SS#189

V

AW3

SS#190

V

AW5

SS#191

V

AW7

SS#192

V

AW9

SS#193

V

AW11

SS#194

V

AW13

SS#195

V

AW15

SS#196

V

AW17

SS#197

V

AW19

SS#198

V

AW21

SS#199

V

AW23

SS#200

V

AW25

SS#201

V

AW27

SS#202

V

AW29

SS#203

V

AW31

SS#204

V

AW33

SS#205

V

AW35

SS#206

V

AW37

SS#207

V

AW39

SS#208

V

AY1

SS#209

V

AY2

SS#210

V

AY9

SS#211

V

AY12

SS#212

V

AY17

SS#213

V

AY23

SS#214

V

AY29

SS#215

V

AY37

SS#216

V

AY40

SS#217

V

AY41

SS#218

V

BA2

SS#219

V

BA5

SS#220

V

BA9

SS#221

V

BA17

SS#222

V

BA23

SS#223

V

BA29

SS#224

V

BA37

SS#225

V

BA40

SS#226

V

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

itle

itle

itle

C

C

C

ompal Electronics, Inc.

R

R

R

18M-G1-90_(6/9)_PWR/GND

18M-G1-90_(6/9)_PWR/GND

18M-G1-90_(6/9)_PWR/GND

ustom

ustom

ustom

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

1

1

1

1

A

A

A

o

o

o

f

32 99Wednesday, May 15, 2019

f

32 99Wednesday, May 15, 2019

f

32 99Wednesday, May 15, 2019

+

VGA_CORE

V32322U_0603_6.3V6M

V32522U_0603_6.3V6M

V32622U_0603_6.3V6M

V32422U_0603_6.3V6M

C

C

C

IS@
D

D D

C C

B B

A A

1 2

C

IS@

IS@

IS@
D

1 2

IS@

D

D

D

1 2

1 2

1 2

+

1.5VSDGPU

V34722U_0603_6.3V6M
C

IS@
D

1 2

FH50P 2019/01/2 2
R

eplace 22U_0603 to 10U_0402 x 2 for layout pl acement

SCL:22u x8, 1u x7

V621U_0201_6 .3V6M

1

V33022U_0603_6.3V6M

V32922U_0603_6.3V6M

V32722U_0603_6.3V6M

V32822U_0603_6.3V6M

C

C

C

C

IS@

IS@

IS@

D

D

D

1 2

1 2

1 2

V34810U_040 2_6.3V6M

V273010U_0402_6.3V6M

C

1

1

1

V3371U_0201_6 .3V6M

C

C

DIS@

2

2

2

DIS@

DIS@

5

1

V3171 U_0201_6.3V6M

C

C

DIS@

DIS@

2

2

SCL:22u x2, 1u x10 SCL:1u x3

1

1

1

V3401U_0201_ 6.3V6M

V3381U_0201_6 .3V6M

V3391U_0201_6 .3V6M

C

C

C

DIS@

DIS@

DIS@

2

2

2

1

1

V3191 U_0201_6.3V6M

V3201 U_0201_6.3V6M

V3181 U_0201_6.3V6M

C

C

C

DIS@

DIS@

DIS@

2

2

R17M-P1-50(25W) :2A(1.35V)
R18M-M2-60:2A(1 .35V)
R18M-G1-90:2A(1 .5V)

1

1

1

V3431U_0201_6 .3V6M

V3421U_0201_6 .3V6M

V3411U_0201_6 .3V6M

C

C

C

DIS@

DIS@

DIS@

2

2

2

C

V316

1U_0201_6.3V6M

1 2

R

17M-P1-50(25W): 30A
R18M-M2-60:25A
R18M-G1-90:60A

1

1

1

V3211 U_0201_6.3V6M

V3221 U_0201_6.3V6M

C

C

DIS@

DIS@

2

2

2

1

1

1

V3451U_0201_6 .3V6M

V3441U_0201_ 6.3V6M

V3461U_0201_6 .3V6M

C

C

C

DIS@

DIS@

DIS@

2

2

2

+

1.8VSDGPU

DIS@

SCL:No need to implement.

R

17M-P1-50(25W): 8A

U

V1I

@

N13

s

ymbol9

V

DDC#0

N15

V

DDC#1

N21

V

DDC#2

N23

V

DDC#3

N29

V

DDC#4

N31

V

DDC#5

R13

V

DDC#6

R15

V

DDC#7

R21

V

DDC#8

R23

V

DDC#9

R29

V

DDC#10

R31

V

DDC#11

U13

V

DDC#12

U15

V

DDC#13

U21

DDC#14

V

U23

DDC#15

V

U29

DDC#16

V

U31

DDC#17

V

W13

DDC#18

V

W15

DDC#19

V

W21

DDC#20

V

W23

DDC#21

V

W29

DDC#22

V

W31

DDC#23

V

AA13

DDC#24

V

AA15

DDC#25

V

AA21

DDC#26

V

AA23

DDC#27

V

AA29

DDC#28

V

AA31

DDC#29

V

AC13

DDC#30

V

AC15

DDC#31

V

AC21

DDC#32

V

AC23

DDC#33

V

AC29

DDC#34

V

AC31

DDC#35

V

AE13

DDC#36

V

AE15

DDC#37

V

AE21

DDC#38

V

AE23

DDC#39

V

AE29

DDC#40

V

AE31

DDC#41

V

AG13

DDC#42

V

AG15

DDC#43

V

AG21

DDC#44

V

AG23

DDC#45

V

AG29

DDC#46

V

AG31

DDC#47

V

AJ13

DDC#48

V

AJ15

DDC#49

V

AJ17

DDC#50

V

AJ19

DDC#51

V

AJ21

DDC#52

V

AJ23

DDC#53

V

AJ25

DDC#54

V

AJ27

DDC#55

V

AJ29

DDC#56

V

AJ31

DDC#57

V

AL13

DDC#58

V

AL15

DDC#59

V

AL17

DDC#60

V

AL19

DDC#61

V

AL21

DDC#62

V

AL23

DDC#63

V

AL25

DDC#64

V

AL27

DDC#65

V

AL29

DDC#66

V

AL31

DDC#67

V

2160896088A1R16M_FCBGA769P-NH

U

V1N

K11

V

MEMIO#0

K13

V

MEMIO#1

K19

V

MEMIO#2

K23

V

MEMIO#3

K27

V

MEMIO#4

K31

V

MEMIO#5

L10

V

MEMIO#6

N10

V

MEMIO#7

W10

V

MEMIO#8

AC10

V

MEMIO#9

AG10

V

MEMIO#10

2160896088A1R16M_FCBGA769P-NH

1

3mA

U

AM13

J8

J7

N38

2160896088A1R16M_FCBGA769P-NH

4

REV 0.91

@

V1J

@

s

ymbol10

T

SVDD

T

EMPIN0

T

EMPINRETURN

T

S_A

s

ymbol14

REV 0.91

D

G

PIO_28_FDO

R

EV 0.91

F

D

PLUS

MINUS

V

DDCI#0

V

DDCI#1

V

DDCI#2

V

DDCI#3

V

DDCI#4

V

DDCI#5

V

DDCI#6

V

DDCI#7

V

DDCI#8

B_VMEMIO

F

B_VDDCI

F

B_VDDC

F

B_VSS

V

DD_18#0

V

DD_18#1

V

DD_18#2

V

DD_08#0

V

DD_08#1

V

DD_08#2

V

DD_08#3

V

DD_08#4

V

DD_08#5

V

DD_08

V

SS

V

SS

N35

N34

U38

R18M-M2-60:Merg e-VDDC
R18M-G1-90:12A

L13
L17
L21
L25
L29
N11
U11
AA11
AE11

C3

G

AV13

G

AR13

G

AU13

1A

AM15
AP15
AR15

R17M-P1-50(25W) :Merge-VDDCI
R18M-M2-60:2A
R18M-G1-90:Merg e-VDDCI

AC32
AG32
AG35
AJ32
AJ34
AL34

W32

AM23
AM17

DG:Thermal Die Temperature

PIO_28_FDO

G

1

V3341 U_0201_6.3V6M
C

DIS@

DIS@

2

PU_VDDCI_SEN
PU_VDDC_SEN
PU_VSS_SEN_L

1

1

V3531U_0201_6 .3V6M

V3521U_0201_6 .3V6M
C

C

DIS@

DIS@

2

2

Fan Drive Out option

R

V21

10K_0201_5%

@

1 2

SCL:22u x2, 1u x4

1

1

V3321 U_0201_6.3V6M

V3331 U_0201_6.3V6M
C

C

DIS@

2

2

1

V3551U_0201_6 .3V6M

V3541U_0201_6 .3V6M

C

C

DIS@

DIS@

2

5

D D

V

GA_ON

+3VSDGPU

+

1.8VSDGPU

VGA_ON_B

+

VDDCI

(0.8VSDGPU merge VDDCI)

+VGA_CORE

DGPU_PWRGOOD

C C

+1.5VSDGPU

4

R18M-G1-90

P

ower Up
Ready within
20ms

D

elay 3ms

Delay +3VSDGPU 7ms

3

A

PU_PCIE_RST#

PCIE_RST_L

APU

EGPIO140

EGPIO141

EGPIO143

P

P

E_GPIO0

E_GPIO1

AND
GATE

VGA_ON

AND
GATE

2

P

D

elay 3ms

+3VALW

+3VALW

LT_RST_VGA#

DL SW

L

PERSTB

GPU

+3VSDGPU

1

DO

+1.8VSDGPU

2

1

+VDDCI

VGA_ON

+3VSDGPU

A

ND

GATE

V

GA_ON_B

D

elay +3VSDGPU 7ms

D

GPU_PWRGOOD

+19VB

+19VB

P

P

+VGA_CORE

WM

4

D

GPU_PWROK

D

GPU_PWRGOOD

+1.5VSDGPU

WM

5

AND
GATE

DGPU_PWRGOOD

P

LT_RST_VGA#

For AMD R18M-G1-90 VRAM

Memory ID/Vendor/Size

000
SAMSUNG
256M x32

0

01
HYNIX
256M x32

0

10
SAMSUNG
128M x32

B B

011
HYNIX
128M x32

1

00
MICRON
256M x32

A A

(

8Gb)

(

8Gb)

Memory PN R3(ABO!)

U

V1001

U

V1002 X76_S4G@

U

V1003 X76_S4G@

U

V1004 X76_S4G@

S

IC D5 256M32 K4G80325FB-HC25 FBGA ABO!

S

A00009TA10

U

V1001

U

V1002 X76_H4G@

U

V1003 X76_H4G@

U

V1004 X76_H4G@

S

IC D5 256M32 H5GC8H24AJR-R2C BGA ABO!

S

A0000C1700

Device ID: 67EF/C0

X

76_S4G@

X

76_H4G@

BOARD_CONFIG[2:0]

R

X

V464

76_S4G@

R

V462 X76_S4G@

R

V460 X76_S4G@

S

RES 1/20W 5.1K +-1% 0201

S

D000008900

R

X

V464

76_H4G@

R

V462 X76_H4G@

R

V459 X76_H4G@

S

RES 1/20W 5.1K +-1% 0201

S

D000008900

D

BGDATA_5
DBGDATA_4
DBGDATA_3

(H: RV463, L: RV464)
(H: RV461, L: RV462)
(H: RV459, L: RV460)

AMD GPU PN

R18M-G1-90 PN R1(ROH)

U

V1 RX560@

S

IC 215-0908004 A1 R18M-G1-90 ABO!

S

A0000BFF10

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

2

2

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

itle

itle

itle

R

R

R

18M-G1-90_(7/9)_NOTE

18M-G1-90_(7/9)_NOTE

18M-G1-90_(7/9)_NOTE

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

1

3

o

3

3

o

o

f

3 99Wednesday, May 15, 2019

f

3 99Wednesday, May 15, 2019

f

3 99Wednesday, May 15, 2019

1

1

1

A

A

A

5

D D

C C

4

3

2

1

R

B B

A A

5

4

eserve Page

S

S

S

ecurity Classif ication

ecurity Classif ication

ecurity Classif ication

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

2

2

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

3

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered D ate

eciphered D ate

eciphered D ate

2

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

Reserve Page

Reserve Page

Reserve Page

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

o

o

o

f

34 99Wed nesday, May 15, 2019

f

34 99Wed nesday, May 15, 2019

f

34 99Wed nesday, May 15, 2019

1

1

1

1

A

A

A

5

M

M

A0_D[0..31]30

M

A0_A[0..8]30

M

A1_D[0..31]30

M

A1_A[0..8]30

+

1.5VSDGPU

D D

R

V79

60.4_0402_1%

1 2

DIS@

R

V80

60.4_0402_1%

1 2

DIS@

Can NC For GDDR5 Spec. Can NC For GDDR5 Spec.

C C

+

1.5VSDGPU

1

R

V52 2.37K_0402_1 %DIS@

1 2

R

V53 5.49K_0402_1 %DIS@

DIS@

1

C

V394 1U_0 201_6.3V6M

+

1.5VSDGPU

1 2

R

V478 2.37K_0402_1%DIS@

1 2

R

V479 5.49K_0402_1%DIS@

DIS@

1 2

C

V403 1U_0 201_6.3V6M

+

1.5VSDGPU

1

R

V480 2.37K_0402_1%DIS@

1 2

R

V481 5.49K_0402_1%DIS@

DIS@

1

V404 1U_0 201_6.3V6M

C

B B

A0_D[0..31]

M

A0_A[0..8]

M

A1_D[0..31]

M

A1_A[0..8]

M

M

A0_EDC030

M

A0_EDC130

M

A0_EDC230

M

A0_EDC330

M

A0_DBI#030

M

M

A0_CLK

M

A0_CLK#

V

2

2

2

2

REFD1_A0

V

REFD2_A0

V

REFC_A0

A0_DBI#130

M

A0_DBI#230

M

A0_DBI#330

M

A0_CLK30

M

A0_CLK#30

M

A0_CKE30

M

A0_ADBI30

M

A0_RAS#30

M

A0_CS#30

M

A0_CAS#30

M

A0_WE#30

M

A0_WCK01#30

M

A0_WCK0130

M

A0_WCK23#30

M

A0_WCK2330

M

A_VRAMRST#30

A0_EDC0

M

A0_EDC1

M

A0_EDC2

M

A0_EDC3

M

A0_DBI#0

M

A0_DBI#1

M

A0_DBI#2

M

A0_DBI#3

M

A0_CLK

M

A0_CLK#

M

A0_CKE

M

A0_A2

M

A0_A5

M

A0_A4

M

A0_A3

M

A0_A7

M

A0_A1

M

A0_A0

M

A0_A6

M

A0_A8

R

V134 1K_0402_1%DIS@

R

V474 1K_0402_1%DIS@

1 2

R

D

V123 120_0402_1%

IS@

M

A0_ADBI

M

A0_RAS#

M

A0_CS#

M

A0_CAS#

M

A0_WE#

M

A0_WCK01#

M

A0_WCK01

M

A0_WCK23#

M

A0_WCK23

V

REFD1_A0

V

REFD2_A0

V

REFC_A0

M

A_VRAMRST#

+

1.5VSDGPU

C2
C13
R13

R2

D2
D13
P13

P2

J12
J11

J3

H11
K10
K11
H10

K4

H5

H4

K5

J5

A5

U5

12
12

J1
J10
J13

J4

G3

G12

L3
L12

D5
D4

P5
P4

A10
U10

J14

J2

H1
K1
B5
G5

L5

T5

B10
D10

G10

L10
P10
T10
H14
K14

G1

L1

G4

L4

C5

R5
C10
R10
D11

G11

L11
P11

G14

L14

A

V1001

@

U

MF=0

DC0 EDC3

E

DC1 EDC2

E

DC2 EDC1

E
E

DC3 EDC0

D

BI0# DBI3#

D

BI1# DBI2#

D

BI2# DBI1#

D

BI3# DBI0#

K

C

K#

C

KE#

C

A0/A2 BA2/A4

B

A1/A5 BA3/A3

B

A2/A4 BA0/A2

B

A3/A3 BA1/A5

B

A

8/A7 A10/A0

A

9/A1 A11/A6

A

10/A0 A8/A7

A

11/A6 A9/A1

A

12/RFU/NC

PP/NC

V

PP/NC

V

M

F

S

EN
Q

Z

BI#

A

AS# CAS#

R

S# WE#

C

AS# RAS#

C

E# CS#

W

CK01# WCK23#

W

CK01 WCK23

W

CK23# WCK01#

W

CK23 WCK01

W

REFD

V

REFD

V
V

REFC

ESET#

R

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V
V

SS

V

SS

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V
V

DD

V

DD

V

DD

V

DD

V

DD

70-BALL

1

SGRAM GDDR5

4

0 Channel

M

F=0

MF=1

H5GC4H24AJR-R0C_BGA170

MF=0MF=1

Q24 DQ0

D

Q25 DQ1

D

Q26 DQ2

D

Q27 DQ3

D

Q28 DQ4

D

Q29 DQ5

D

Q30 DQ6

D

Q31 DQ7

D

Q16 DQ8

D

Q17 DQ9

D

Q18 DQ10

D

Q19 DQ11

D

Q20 DQ12

D

Q21 DQ13

D

Q22 DQ14

D

Q23 DQ15

D
D

Q8 DQ16

D

Q9 DQ17

D

Q10 DQ18

D

Q11 DQ19

D

Q12 DQ20

D

Q13 DQ21

D

Q14 DQ22

D

Q15 DQ23

D

Q0 DQ24

D

Q1 DQ25

D

Q2 DQ26

D

Q3 DQ27

D

Q4 DQ28

D

Q5 DQ29

D

Q6 DQ30

D

Q7 DQ31

V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V

V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
VSSQ
V
V
V
V
V
V
V
V
V

3

2

1

A1 Channel

M

V1002

U

A0_D6

+

1.5VSDGPU

M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M

M

M
M
M
M
M
M
M

A0_D7
A0_D5
A0_D4
A0_D2
A0_D0
A0_D1
A0_D3
A0_D10
A0_D9
A0_D11
A0_D8
A0_D15
A0_D12
A0_D14
A0_D13
A0_D23
A0_D21
A0_D22
A0_D20
A0_D19
A0_D18
A0_D16
A0_D17

A0_D24

A0_D26
A0_D25
A0_D27
A0_D28
A0_D29
A0_D31
A0_D30

Byte 0

Byte 1

Byte 2

Byte 3

+

1.5VSDGPU

R

V1637

60.4_0402_1%

2

1

DIS@

R

V1636

60.4_0402_1%

1 2

DIS@

+

1.5VSDGPU

1 2

R

V486 2.37K_0402_1%DIS@

1

R

V487 5.49K_0402_1%DIS@

DIS@

1 2

C

V407 1U_0 201_6.3V6M

+

1.5VSDGPU

1 2

R

V482 2.37K_0402_1%DIS@

1 2

R

V483 5.49K_0402_1%DIS@

DIS@

1 2

C

V405 1U_0 201_6.3V6M

+

1.5VSDGPU

1

R

V484 2.37K_0402_1%DIS@

1 2

R

V485 5.49K_0402_1%DIS@

DIS@

1 2

C

V406 1U_0 201_6.3V6M

M

M

A1_EDC030

M

A1_EDC130

M

A1_EDC330

M

A1_EDC230

M

A1_DBI#030

M

+

1.5VSDGPU

A1_DBI#130

M

A1_DBI#330

M

A1_DBI#230

M

A1_CLK30

M

A1_CLK#30

M

A1_CKE30

M

A1_ADBI30

M

A1_CAS#30

M

A1_WE#30

M

A1_RAS#30

M

A1_CS#30

M

A1_WCK01#3 0

M

A1_WCK0130

M

A1_WCK23#3 0

M

A1_WCK2330

M

A1_CLK

M

A1_CLK#

V

2

2

REFD1_A1

V

REFD2_A1

V

REFC_A1

A1_EDC0

M

A1_EDC1

M

A1_EDC3

M

A1_EDC2

M

A1_DBI#0

M

A1_DBI#1

M

A1_DBI#3

M

A1_DBI#2

M

A1_CLK

M

A1_CLK#

M

A1_CKE

M

A1_A4

M

A1_A3

M

A1_A2

M

A1_A5

M

A1_A0

M

A1_A6

M

A1_A7

M

A1_A1

M

A1_A8

12

R

V131 1K_0402_1%DIS@

12

R

V475 1K_0402_1%DIS@

1 2

V132 120_0402_1%

IS@

R

D

M

A1_ADBI

M

A1_CAS#

M

A1_WE#

M

A1_RAS#

M

A1_CS#

M

A1_WCK01#

M

A1_WCK01

A1_WCK23#

M

A1_WCK23

M

V

REFD1_A1

V

REFD2_A1

V

REFC_A1

M

A_VRAMRST#

+

1.5VSDGPU

A4
A2
B4
B2
E4
E2
F4
F2
A11
A13
B11
B13
E11
E13
F11
F13
U11
U13
T11
T13
N11
N13
M11
M13
U4
U2
T4
T2
N4
N2
M4
M2

B1

DDQ

D1

DDQ

F1

DDQ

M1

DDQ

P1

DDQ

T1

DDQ

G2

DDQ

L2

DDQ

B3

DDQ

D3

DDQ

F3

DDQ

H3

DDQ

K3

DDQ

M3

DDQ

P3

DDQ

T3

DDQ

E5

DDQ

N5

DDQ

E10

DDQ

N10

DDQ

B12

DDQ

D12

DDQ

F12

DDQ

H12

DDQ

K12

DDQ

M12

DDQ

P12

DDQ

T12

DDQ

G13

DDQ

L13

DDQ

B14

DDQ

D14

DDQ

F14

DDQ

M14

DDQ

P14

DDQ

T14

DDQ

A1

SSQ

C1

SSQ

E1

SSQ

N1

SSQ

R1

SSQ

U1

SSQ

H2

SSQ

K2

SSQ

A3

SSQ

C3

SSQ

E3

SSQ

N3

SSQ

R3

SSQ

U3

SSQ

C4

SSQ

R4

SSQ

F5

SSQ

M5

SSQ

F10

SSQ

M10

SSQ

C11

SSQ

R11

SSQ

A12

SSQ

C12

SSQ

E12

SSQ

N12

SSQ

R12
U12

SSQ

H13

SSQ

K13

SSQ

A14

SSQ

C14

SSQ

E14

SSQ

N14

SSQ

R14

SSQ

U14

SSQ

C2

DC0 EDC3

E

C13

DC1 EDC2

E

R13

DC2 EDC1

E

R2

E

DC3 EDC0

D2

D

BI0# DBI3#

D13

D

BI1# DBI2#

P13

D

BI2# DBI1#

P2

D

BI3# DBI0#

J12

K

C

J11

K#

C

J3

KE#

C

H11

A0/A2 BA2/A4

B

K10

A1/A5 BA3/A3

B

K11

A2/A4 BA0/A2

B

H10

A3/A3 BA1/A5

B

K4

A

8/A7 A10/A0

H5

A

9/A1 A11/A6

H4

A

10/A0 A8/A7

K5

A

11/A6 A9/A1

J5

A

12/RFU/NC

A5

PP/NC

V

U5

PP/NC

V

J1

M

F

J10

S

EN

J13

Q

Z

J4

BI#

A

G3

AS# CAS#

R

G12

S# WE#

C

L3

AS# RAS#

C

L12

E# CS#

W

D5

CK01# WCK23#

W

D4

CK01 WCK23

W

P5

CK23# WCK01#

W

P4

CK23 WCK01

W

A10

REFD

V

U10

REFD

V

J14

V

REFC

J2

ESET#

R

H1

SS

V

K1

SS

V

B5

SS

V

G5

SS

V

L5

SS

V

T5

SS

V

B10

SS

V

D10

SS

V

G10

SS

V

L10

SS

V

P10

SS

V

T10

SS

V

H14

SS

V

K14

SS

V

G1

DD

V

L1

DD

V

G4

DD

V

L4

DD

V

C5

DD

V

R5

DD

V

C10

DD

V

R10

DD

V

D11

DD

V

G11

DD

V

L11

DD

V

P11

DD

V

G14

DD

V

L14

DD

V

SGRAM GDDR5

1

MF=0

70-BALL

F=1

@

MF=1

H5GC4H24AJR-R0C_BGA170

Q24 DQ0

D

Q25 DQ1

D

Q26 DQ2

D

Q27 DQ3

D

Q28 DQ4

D

Q29 DQ5

D

Q30 DQ6

D

Q31 DQ7

D

Q16 DQ8

D

Q17 DQ9

D

Q18 DQ10

D

Q19 DQ11

D

Q20 DQ12

D

Q21 DQ13

D

Q22 DQ14

D

Q23 DQ15

D

Q8 DQ16

D

Q9 DQ17

D
D

Q10 DQ18

D

Q11 DQ19

D

Q12 DQ20

D

Q13 DQ21

D

Q14 DQ22

D

Q15 DQ23

D

Q0 DQ24

D

Q1 DQ25

D

Q2 DQ26

D

Q3 DQ27

D

Q4 DQ28

D

Q5 DQ29

D

Q6 DQ30

D

Q7 DQ31

MF=0MF=1

A4
A2
B4
B2
E4
E2
F4
F2
A11
A13
B11
B13
E11
E13
F11
F13
U11
U13
T11
T13
N11
N13
M11
M13
U4
U2
T4
T2
N4
N2
M4
M2

B1

DDQ

V

D1

DDQ

V

F1

DDQ

V

M1

DDQ

V

P1

DDQ

V

T1

DDQ

V

G2

DDQ

V

L2

DDQ

V

B3

DDQ

V

D3

DDQ

V

F3

DDQ

V

H3

DDQ

V

K3

DDQ

V

M3

DDQ

V

P3

DDQ

V

T3

DDQ

V

E5

DDQ

V

N5

DDQ

V

E10

DDQ

V

N10

DDQ

V

B12

DDQ

V

D12

DDQ

V

F12

DDQ

V

H12

DDQ

V

K12

DDQ

V

M12

DDQ

V

P12

DDQ

V

T12

DDQ

V

G13

DDQ

V

L13

DDQ

V

B14

DDQ

V

D14

DDQ

V

F14

DDQ

V

M14

DDQ

V

P14

DDQ

V

T14

DDQ

V

A1

SSQ

V

C1

SSQ

V

E1

SSQ

V

N1

SSQ

V

R1

SSQ

V

U1

SSQ

V

H2

SSQ

V

K2

SSQ

V

A3

SSQ

V

C3

SSQ

V

E3

SSQ

V

N3

SSQ

V

R3

SSQ

V

U3

SSQ

V

C4

SSQ

V

R4

SSQ

V

F5

SSQ

V

M5

SSQ

V

F10

SSQ

V

M10

SSQ

V

C11

SSQ

V

R11

SSQ

V

A12

SSQ

V

C12

SSQ

V

E12

SSQ

V

N12

SSQ

V

R12

SSQ

V

U12

SSQ

V

H13

SSQ

V

K13

SSQ

V

A14

SSQ

V

C14

SSQ

V

E14

SSQ

V

N14

SSQ

V

R14

SSQ

V

U14

SSQ

V

+

1.5VSDGPU

A1_D7

M

A1_D5

M

A1_D6

M

A1_D4

M

A1_D3

M

Byte 0

A1_D2

M

A1_D0

M

A1_D1

M

A1_D8

M

A1_D10

M

A1_D9

M

A1_D11

M

A1_D12

M

Byte 1

A1_D13

M

A1_D15

M

A1_D14

M

A1_D31

M

A1_D30

M

A1_D28

M

A1_D29

M

A1_D25

M

Byte 3

A1_D26

M

A1_D24

M

A1_D27

M

A1_D16

M

A1_D17

M

A1_D19

M

A1_D18

M

A1_D21

M

Byte 2

A1_D22

M

A1_D20

M

A1_D23

M

Decoupling Caps for single-sided
1x 10uF /per DRAM
8x 1uF /per DRAM

+

1.5VSDGPU

V23810U_040 2_6.3V6M
C

1

A A

2

DIS@

8x 0.1uF /per DRAM

V44510U_040 2_6.3V6M
C

1

1

1

V2431U_0201_6.3V6M

V2421U_0201_6.3V6M

C

C

2

2

2

DIS@

DIS@

1

1

1

V3921U_0201_6.3V6M

V2471U_0201_6.3V6M

V2481U_0201_6.3V6M

C

C

C

2

2

2

DIS@

DIS@

DIS@

DIS@

5

1

1

V3961U_0201_6.3V6M

V3971U_0201_6.3V6M

C

C

2

2

DIS@

DIS@

Decoupling Caps for Clamshell
1x 10uF /per Clamshell DRAM
8x 1uF /per Clamshell DRAM

1

1

1

V3981U_0201_6.3V6M
C

V4150.1U_0201_10V6K

V4140.1U_0201_10V6K

C

C

2

2

2

DIS@

DIS@

DIS@

+

1.5VSDGPU

1

1

1

V4180.1U_0201_10V6K

V4170.1U_0201_10V6K

V4160.1U_0201_10V6K

C

C

C

2

2

2

DIS@

DIS@

DIS@

1

1

1

V4190.1U_0201_10V6K

V4210.1U_0201_10V6K

V4200.1U_0201_10V6K

C

C

C

2

2

2

DIS@

DIS@

DIS@

1

1

V1570.1U_0201_10V6K

V1550.1U_0201_10V6K

C

C

2

2

DIS@

4

1

1

1

1

V2100.1U_0201_10V6K

V1580.1U_0201_10V6K
C

2

DIS@

V2110.1U_0201_10V6K

V1980.1U_0201_10V6K

C

C

C

2

2

2

DIS@

DIS@

DIS@

1

1

1

V2300.1U_0201_10V6K

V2330.1U_0201_10V6K

V2130.1U_0201_10V6K

C

C

C

2

2

2

DIS@

DIS@

DIS@

+

1.5VSDGPU

V46510U_040 2_6.3V6M

V272810U_0402_6.3V6M

C

1

1

1

V2350.1U_0201_10V6K
C

2

DIS@

1

V4601U_0201_6 .3V6M

C

C

2

2

2

DIS@

DIS@

DIS@

1

1

1

V4611U_0201_6 .3V6M

V4631U_0201_6 .3V6M

V4621U_0201_6 .3V6M

C

C

C

2

2

2

DIS@

DIS@

DIS@

3

1

1

1

V4641U_0201_6 .3V6M
C

2

DIS@

1

V4671U_0201_ 6.3V6M

V4661U_0201_6 .3V6M

V4681U_0201_6 .3V6M

C

C

C

2

2

2

DIS@

DIS@

DIS@

DIS@

1

1

1

1

V4540.1U_0201_10V6K

V4520.1U_0201_10V6K

V4530.1U_0201_10V6K

V4550.1U_0201_10V6K

C

C

C

C

2

2

2

2

DIS@

DIS@

DIS@

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

1

1

1

V4580.1U_0201_10V6K

V4590.1U_0201_10V6K

V4570.1U_0201_10V6K

V4560.1U_0201_10V6K

C

C

C

C

2

2

2

2

DIS@

DIS@

DIS@

DIS@

DIS@

C

C

C

ompal Secret Data

ompal Secret Data

2

2

2

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

ompal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

Title

itle

itle

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

R

R

R

18M-G1-90_(8/9)_CH A

18M-G1-90_(8/9)_CH A

18M-G1-90_(8/9)_CH A

ustom

ustom

ustom

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

1

o

o

o

f

35 99Wednesday, May 15, 2019

f

35 99Wednesday, May 15, 2019

f

35 99Wednesday, May 15, 2019

1

1

1

A

A

A

5

M

M

B0_D[0..31]30

M

B0_A[0..8]30

M

B1_D[0..31]30

M

B1_A[0..8]30

+

1.5VSDGPU

D D

R

V473

60.4_0402_1%

2

1

RX560@

R

V472

60.4_0402_1%

2

1

RX560@

Can NC For GDDR5 Spec.

C C

+

1.5VSDGPU

1

R

V498 2.37K_0402_1%RX560@

1 2

R

V499 5.49K_0402_1%RX560@

RX560@

1 2

V413 1U_0 201_6.3V6M

C

+

1.5VSDGPU

1 2

V494 2.37K_0402_1%RX560@

R

1

R

V495 5.49K_0402_1%RX560@

RX560@

1

V411 1U_0 201_6.3V6M

C

+

1.5VSDGPU

1

R

V496 2.37K_0402_1%RX560@

1

R

V497 5.49K_0402_1%RX560@

RX560@

1 2

V412 1U_0 201_6.3V6M

C

B B

B0_D[0..31]

M

B0_A[0..8]

M

B1_D[0..31]

M

B1_A[0..8]

M

M

B0_EDC130

M

B0_EDC030

M

B0_EDC230

M

B0_EDC330

M

B0_DBI#130

M

M

B0_CLK

M

B0_CLK#

V

2

2

REFD1_B0

V

REFD2_B0

B0_DBI#030

M

B0_DBI#230

M

B0_DBI#330

M

B0_CLK30

M

B0_CLK#30

M

B0_CKE30

M

B0_ADBI30

M

B0_RAS#30

M

B0_CS#30

M

B0_CAS#30

M

B0_WE#30

M

B0_WCK01#30

M

B0_WCK0130

M

B0_WCK23#30

M

B0_WCK2330

M

B_VRAMRST#30

B0_EDC1

M

B0_EDC0

M

B0_EDC2

M

B0_EDC3

B0_DBI#1

M

B0_DBI#0

M

M

B0_DBI#2

M

B0_DBI#3

M

B0_CLK

M

B0_CLK#

M

B0_CKE

M

B0_A2

M

B0_A5

M

B0_A4

M

B0_A3

M

B0_A7

M

B0_A1

M

B0_A0

M

B0_A6

M

B0_A8

2

R

V116 1K_0402_1%RX560@

V476 1K_0402_1%RX560@

R

1 2

V120 120_0402_1%

X560@

R

R

M

B0_ADBI

M

B0_RAS#

M

B0_CS#

M

B0_CAS#

M

B0_WE#

M

B0_WCK01#

M

B0_WCK01

M

B0_WCK23#

M

B0_WCK23

V

REFD1_B0

V

REFD2_B0

V

REFC_B0

M

B_VRAMRST#

2

V

2
2

REFC_B0

+

1.5VSDGPU

C2
C13

R13

R2

D2
D13
P13

P2

J12
J11

J3

H11
K10
K11
H10

K4

H5

H4

K5

J5

A5

U5

1

12

J1
J10
J13

J4

G3

G12

L3

L12

D5
D4

P5
P4

A10
U10

J14

J2

H1
K1
B5
G5

L5

T5

B10
D10

G10

L10
P10

T10

H14
K14

G1

L1

G4

L4

C5

R5
C10
R10
D11

G11

L11
P11

G14

L14

B

U

V1003

@

MF=0

E

DC0 EDC3

E

DC1 EDC2

DC2 EDC1

E

DC3 EDC0

E

BI0# DBI3#

D

BI1# DBI2#

D

BI2# DBI1#

D

BI3# DBI0#

D

C

K

C

K#

C

KE#

A0/A2 BA2/A4

B

A1/A5 BA3/A3

B

A2/A4 BA0/A2

B

A3/A3 BA1/A5

B

8/A7 A10/A0

A
A

9/A1 A11/A6

A

10/A0 A8/A7

A

11/A6 A9/A1

A

12/RFU/NC

PP/NC

V

V

PP/NC

M

F

EN

S

Q

Z

BI#

A

R

AS# CAS#

C

S# WE#

C

AS# RAS#

W

E# CS#

CK01# WCK23#

W

CK01 WCK23

W

CK23# WCK01#

W

CK23 WCK01

W

REFD

V

REFD

V

REFC

V

ESET#

R

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

V

SS

SS

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

1

70-BALL

SGRAM GDDR5

4

3

2

0 Channel

M

F=0 MF=1

MF=1

H5GC4H24AJR-R0C_BGA170

MF=0MF=1

D

Q24 DQ0

D

Q25 DQ1

D

Q26 DQ2

D

Q27 DQ3

D

Q28 DQ4

D

Q29 DQ5

D

Q30 DQ6

D

Q31 DQ7

Q16 DQ8

D

Q17 DQ9

D

Q18 DQ10

D

Q19 DQ11

D

Q20 DQ12

D

Q21 DQ13

D

Q22 DQ14

D

Q23 DQ15

D

Q8 DQ16

D

Q9 DQ17

D

Q10 DQ18

D

Q11 DQ19

D

Q12 DQ20

D

Q13 DQ21

D

Q14 DQ22

D

Q15 DQ23

D

Q0 DQ24

D

Q1 DQ25

D

Q2 DQ26

D

Q3 DQ27

D

Q4 DQ28

D

Q5 DQ29

D

Q6 DQ30

D

Q7 DQ31

D

B0_D15

+

1.5VSDGPU

M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M

B0_D14
B0_D12
B0_D13
B0_D10
B0_D9
B0_D11
B0_D8
B0_D0
B0_D1
B0_D3
B0_D2
B0_D6
B0_D5
B0_D7
B0_D4
B0_D23
B0_D21
B0_D22
B0_D20
B0_D19
B0_D18
B0_D16
B0_D17
B0_D24
B0_D26
B0_D25
B0_D27
B0_D28
B0_D29
B0_D31
B0_D30

Byte 1

Byte 0

Byte 2

Byte 3

+

1.5VSDGPU

V1638

R

60.4_0402_1%

1 2

RX560@

V1639

R

60.4_0402_1%

1 2

RX560@

Can NC For GDDR5 Spec.

+

1.5VSDGPU

1

R

V492 2.37K_0402_1%RX560@

1

R

V493 5.49K_0402_1%RX560@

RX560@

1

C

V410 1U_0 201_6.3V6M

+

1.5VSDGPU

1 2

R

V488 2.37K_0402_1%RX560@

1 2

R

V489 5.49K_0402_1%RX560@

RX560@

1

C

V408 1U_0 201_6.3V6M

+

1.5VSDGPU

1 2

V490 2.37K_0402_1%RX560@

R

1 2

V491 5.49K_0402_1%RX560@

R

RX560@

1

C

V409 1U_0 201_6.3V6M

M

M

B1_EDC030

M

B1_EDC130

M

B1_EDC230

M

B1_EDC330

M

B1_DBI#030

M

+

1.5VSDGPU

B1_DBI#130

M

B1_DBI#230

M

B1_DBI#330

M

B1_CLK30

M

B1_CLK#30

M

B1_CKE30

M

B1_ADBI30

M

B1_CAS#30

M

B1_WE#30

M

B1_RAS#30

M

B1_CS#30

M

B1_WCK01#3 0

M

B1_WCK0130

M

B1_WCK23#3 0

M

B1_WCK2330

M

B1_CLK

M

B1_CLK#

V

2

2

REFD1_B1

2

V

REFD2_B1

B1_EDC0

M

B1_EDC1

M

B1_EDC2

M

B1_EDC3

M

B1_DBI#0

M

B1_DBI#1

M

B1_DBI#2

M

B1_DBI#3

M

B1_CLK

M

B1_CLK#

M

B1_CKE

M

B1_A4

M

B1_A3

M

B1_A2

M

B1_A5

M

B1_A0

M

B1_A6

M

B1_A7

M

B1_A1

M

B1_A8

2

1

R

V117 1K_0402_1%RX560@

2

1

R

V477 1K_0402_1%RX560@

1 2

V121 120_0402_1%

X560@

R

R

M

B1_ADBI

M

B1_CAS#

M

B1_WE#

M

B1_RAS#

M

B1_CS#

M

B1_WCK01#

M

B1_WCK01

M

B1_WCK23#

M

B1_WCK23

V

REFD1_B1

V

REFD2_B1

V

REFC_B1

M

B_VRAMRST#

2

V

REFC_B1

+

1.5VSDGPU

2

A4
A2
B4
B2
E4
E2
F4
F2

A11
A13
B11
B13
E11
E13
F11
F13
U11
U13
T11
T13
N11
N13
M11
M13
U4
U2
T4
T2
N4
N2
M4
M2

B1

DDQ

V

D1

DDQ

V

F1

DDQ

V

M1

DDQ

V

P1

DDQ

V

T1

DDQ

V

G2

DDQ

V

L2

DDQ

V

B3

DDQ

V

D3

DDQ

V

F3

DDQ

V

H3

DDQ

V

K3

DDQ

V

M3

DDQ

V

P3

DDQ

V

T3

DDQ

V

E5

DDQ

V

N5

DDQ

V

E10

DDQ

V

N10

DDQ

V

B12

DDQ

V

D12

DDQ

V

F12

DDQ

V

H12

DDQ

V

K12

DDQ

V

M12

DDQ

V

P12

DDQ

V

T12

DDQ

V

G13

DDQ

V

L13

DDQ

V

B14

DDQ

V

D14

DDQ

V

F14

DDQ

V

M14

DDQ

V

P14

DDQ

V

T14

DDQ

V

A1

SSQ

V

C1

SSQ

V

E1

V

SSQ

N1

SSQ

V

R1

SSQ

V

U1

SSQ

V

H2

SSQ

V

K2

SSQ

V

A3

SSQ

V

C3

SSQ

V

E3

SSQ

V

N3

SSQ

V

R3

SSQ

V

U3

SSQ

V

C4

SSQ

V

R4

SSQ

V

F5

SSQ

V

M5

SSQ

V

F10

SSQ

V

M10

SSQ

V

C11

SSQ

V

R11

SSQ

V

A12

SSQ

V

C12

SSQ

V

E12

SSQ

V

N12

SSQ

V

R12

SSQ

V

U12

SSQ

V

H13

SSQ

V

K13

SSQ

V

A14

SSQ

V

C14

SSQ

V

E14

SSQ

V

N14

SSQ

V

R14

SSQ

V

U14

SSQ

V

U

V1004

C2

E

DC0 EDC3

C13

E

DC1 EDC2

R13

E

DC2 EDC1

R2

DC3 EDC0

E

D2

BI0# DBI3#

D

D13

BI1# DBI2#

D

P13

BI2# DBI1#

D

P2

BI3# DBI0#

D

J12

C

K

J11

C

K#

J3

C

KE#

H11

B

A0/A2 BA2/A4

K10

B

A1/A5 BA3/A3

K11

B

A2/A4 BA0/A2

H10

B

A3/A3 BA1/A5

K4

8/A7 A10/A0

A

H5

9/A1 A11/A6

A

H4

10/A0 A8/A7

A

K5

11/A6 A9/A1

A

J5

12/RFU/NC

A

A5

V

PP/NC

U5

V

PP/NC

J1

F

M

J10

EN

S

J13

Z

Q

J4

A

BI#

G3

R

AS# CAS#

G12

C

S# WE#

L3

C

AS# RAS#

L12

W

E# CS#

D5

W

CK01# WCK23#

D4

W

CK01 WCK23

P5

W

CK23# WCK01#

P4

W

CK23 WCK01

A10

V

REFD

U10

V

REFD

J14

REFC

V

J2

R

ESET#

H1

V

SS

K1

V

SS

B5

V

SS

G5

V

SS

L5

V

SS

T5

V

SS

B10

V

SS

D10

V

SS

G10

V

SS

L10

V

SS

P10

V

SS

T10

V

SS

H14

SS

V

K14

SS

V

G1

V

DD

L1

V

DD

G4

V

DD

L4

V

DD

C5

V

DD

R5

V

DD

C10

V

DD

R10

V

DD

D11

V

DD

G11

DD

V

L11

DD

V

P11

DD

V

G14

DD

V

L14

DD

V

SGRAM GDDR5

1

70-BALL

B1 Channel

@

MF=0

MF=1

H5GC4H24AJR-R0C_BGA170

D

Q24 DQ0

D

Q25 DQ1

D

Q26 DQ2

D

Q27 DQ3

D

Q28 DQ4

D

Q29 DQ5

D

Q30 DQ6

D

Q31 DQ7

D

Q16 DQ8

D

Q17 DQ9

D

Q18 DQ10

D

Q19 DQ11

D

Q20 DQ12

D

Q21 DQ13

D

Q22 DQ14

D

Q23 DQ15

Q8 DQ16

D

Q9 DQ17

D

Q10 DQ18

D

Q11 DQ19

D

Q12 DQ20

D

Q13 DQ21

D

Q14 DQ22

D

Q15 DQ23

D

Q0 DQ24

D

Q1 DQ25

D

Q2 DQ26

D

Q3 DQ27

D

Q4 DQ28

D

Q5 DQ29

D

Q6 DQ30

D

Q7 DQ31

D

1

MF=0MF=1

A4
A2
B4
B2
E4
E2
F4
F2
A11
A13
B11
B13
E11
E13
F11
F13

U11
U13
T11
T13
N11
N13
M11
M13
U4
U2
T4
T2
N4
N2
M4
M2

B1

V

DDQ

D1

V

DDQ

F1

V

DDQ

M1

V

DDQ

P1

V

DDQ

T1

V

DDQ

G2

V

DDQ

L2

V

DDQ

B3

V

DDQ

D3

V

DDQ

F3

V

DDQ

H3

V

DDQ

K3

V

DDQ

M3

V

DDQ

P3

V

DDQ

T3

V

DDQ

E5

V

DDQ

N5

V

DDQ

E10

V

DDQ

N10

V

DDQ

B12

V

DDQ

D12

V

DDQ

F12

V

DDQ

H12

V

DDQ

K12

V

DDQ

M12

V

DDQ

P12

V

DDQ

T12

V

DDQ

G13

V

DDQ

L13

V

DDQ

B14

V

DDQ

D14

V

DDQ

F14

V

DDQ

M14

V

DDQ

P14

V

DDQ

T14

DDQ

V

A1

V

SSQ

C1

V

SSQ

E1

V

SSQ

N1

V

SSQ

R1

V

SSQ

U1

V

SSQ

H2

V

SSQ

K2

V

SSQ

A3

V

SSQ

C3

V

SSQ

E3

V

SSQ

N3

V

SSQ

R3

SSQ

V

U3

SSQ

V

C4

SSQ

V

R4

SSQ

V

F5

SSQ

V

M5

SSQ

V

F10

SSQ

V

M10

SSQ

V

C11

SSQ

V

R11

SSQ

V

A12

SSQ

V

C12

SSQ

V

E12

SSQ

V

N12

SSQ

V

R12

SSQ

V

U12

SSQ

V

H13

SSQ

V

K13

SSQ

V

A14

SSQ

V

C14

SSQ

V

E14

SSQ

V

N14

SSQ

V

R14

SSQ

V

U14

SSQ

V

+

1.5VSDGPU

B1_D7

M

B1_D5

M

B1_D6

M

B1_D4

M

B1_D3

M

Byte 0

B1_D2

M

B1_D0

M

B1_D1

M

B1_D8

M

B1_D10

M

B1_D9

M

B1_D11

M

B1_D12

M

Byte 1

B1_D13

M

B1_D15

M

B1_D14

M

B1_D20

M

B1_D22

M

B1_D21

M

B1_D23

M

B1_D16

M

Byte 2

B1_D19

M

B1_D17

M

B1_D18

M

B1_D25

M

B1_D24

M

B1_D26

M

B1_D27

M

B1_D29

M

Byte 3

B1_D31

M

B1_D30

M

B1_D28

M

Decoupling Caps for single-sided
1x 10uF /per DRAM
8x 1uF /per DRAM

+

1.5VSDGPU

1

V48110U_0402_6.3V6M
C

A A

2

RX560@

8x 0.1uF /per DRAM

V272710U_0402_6.3V6M

1

1

1

1

V4411U_0201_6.3V6M

V4401U_0201_6.3V6M

C

C

C

2

2

2

RX560@

RX560@

1

1

V4421U_0201_6.3V6M

V4431U_0201_6.3V6M

V4441U_0201_6.3V6M

C

C

C

2

2

2

RX560@

RX560@

RX560@

RX560@

5

1

1

V4461U_0201_6.3V6M

V4471U_0201_6.3V6M
C

C

2

2

RX560@

RX560@

Decoupling Caps for Clamshell
1x 10uF /per Clamshell DRAM
8x 1uF /per Clamshell DRAM

1

1

V4481U_0201_6.3V6M
C

2

1

V4330.1U_0201_10V6K

V4320.1U_0201_10V6K
C

C

2

2

RX560@

RX560@

RX560@

+

1.5VSDGPU

1

1

1

1

V4350.1U_0201_10V6K

V4360.1U_0201_10V6K

V4340.1U_0201_10V6K

C

C

C

2

2

2

RX560@

RX560@

RX560@

1

1

V4370.1U_0201_10V6K

V4390.1U_0201_10V6K

V4380.1U_0201_10V6K
C

C

C

2

2

2

RX560@

RX560@

1

1

1

V4240.1U_0201_10V6K

V4220.1U_0201_10V6K

V4230.1U_0201_10V6K

C

C

C

2

2

2

RX560@

RX560@

RX560@

RX560@

4

For Layout Antenna Effect For Layout Antenna Effect

1

1

1

1

1

V4250.1U_0201_10V6K

V4260.1U_0201_10V6K

C

C

2

2

RX560@

1

V4300.1U_0201_10V6K

V4280.1U_0201_10V6K

V4270.1U_0201_10V6K

V4290.1U_0201_10V6K

C

C

C

C

2

2

2

2

DIS@

RX560@

RX560@

RX560@

+

1.5VSDGPU

V272910U_0402_6.3V6M

V272610U_0402_6.3V6M

1

1

V4310.1U_0201_10V6K
C

2

RX560@

RX560@

1

1

C

C

2

2

@

RX560@

1

1

V4801U_0201_ 6.3V6M

V4851U_0201_ 6.3V6M

V4821U_0201_ 6.3V6M
C

C

C

2

2

2

RX560@

RX560@

3

1

1

1

V4771U_0201_ 6.3V6M

V4831U_0201_ 6.3V6M
C

C

2

2

RX560@

RX560@

1

1

V4841U_0201_ 6.3V6M

V4791U_0201_6 .3V6M

V4781U_0201_6 .3V6M

C

C

C

2

2

2

RX560@

RX560@

RX560@

1

1

1

V4690.1U_0201_10V6K

V4700.1U_0201_10V6K
C

C

2

2

RX560@

RX560@

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

1

1

V4720.1U_0201_10V6K

V4710.1U_0201_10V6K

C

C

2

2

RX560@

RX560@

1

1

V4750.1U_0201_10V6K

V4740.1U_0201_10V6K

V4730.1U_0201_10V6K
C

RX560@

V4760.1U_0201_10V6K

C

C

C

2

2

2

2

DIS@

RX560@

RX560@

RX560@

C

C

C

ompal Secret Data

ompal Secret Data

2

2

2

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

ompal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

R

R

R

18M-G1-90_(9/9)_CH B

18M-G1-90_(9/9)_CH B

18M-G1-90_(9/9)_CH B

ustom

ustom

ustom

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

1

o

o

o

f

36 99Wednesday, May 15, 2019

f

36 99Wednesday, May 15, 2019

f

36 99Wednesday, May 15, 2019

1

1

1

A

A

A

5

R

V807

@

R

V913

R

V833

33K_040 2_5%

1

DIS@

DIS@

0_0402_ 5%

1 2

RS@

2

0.22U_04 02_16V7K

1

2

1

C

V2701

2

P

E_GPIO1_R

C

V626

V

GA_ON

V

ih 2.1V

Delay 7ms

1

@

2

D D

C C

+

3VSDGPU

P

E_GPIO110

100K_04 02_5%

0.22U_04 02_16V7K

4

R

V406

0_0402_ 5%

12

@

+

3VALW

U

V5

MC74VHC 1G08DFT2G_SC 70-5

5

D

IS@

1

P

I

N1

O

2

I

N2

G

3

+

3VALW

U

V6

MC74VHC 1G08DFT2G_SC 70-5

5

D

IS@

1

P

I

N1

O

2

I

N2

G

3

4

4

SA00000OH00

V

GA_ON

1

D

IS@

C

V2698

0.1U_020 1_10V6K

2

SA00000OH00

V

GA_ON_B

2

@

C

V2722

1U_0201 _6.3V6M

1

3

V

GA_ON 96

V

GA_ON_B 92

+

3VALW TO +3VSDGPU

2

1

IMAX(per channe l)=6A,Rds=18mohm

+

UV8

+

C

2751

S

USP#58 ,78,84,86

V

B B

A A

5

GA_ON

0.1U_020 1_10V6K

R

V1648 0_0402_5 %RS@

C

@

0.22U_04 02_16V7K

2

@

1

RS@

R

1669 0 _0402_5%

1

2

V2724

1

1.8VALW

1

2

2

+

3VALW

1

.8VS_ON

V

GA_ON_R

C

V260

1U_0201 _6.3V6M

4

C

24

1U_0201 _6.3V6M

+

5VALW

1 2

1

1

V

V

OUT1

2

IN1

2

V

V

OUT1

IN1

3

O

4

V

5

O

6

V

7

V

E

M5209VF _DFN14_3X2

DIS@

S

A00007PM00

S

S

S

ecurity Classif ication

ecurity Classif ication

ecurity Classif ication

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

N1

BIAS

N2

IN2
IN2

V
V

G

OUT2
OUT2

G

C

C

PAD

T1

ND

T2

+

1.8VS_LS

14
13

2

1

12

C

21 47 00P_0402_50V 7K

11

1 2

10

9
8

15

DIS@

C

V621 1000 P_0402_50V7K

+

3VSDGPU _LS

2

2

2

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

3

J

9

JUMP_43 X79

J

2504

1

1

JUMP_43 X39

2

0mil(10mA)

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

1.8VS

JP@

JP@

2

2

eciphered D ate

eciphered D ate

eciphered D ate

1

C

26

0.1U_020 1_10V6K

2

+

3VSDGPU

2

C

0.1U_020 1_10V6K

1

V2725

DIS@

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

Title

itle

itle

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Date: Sheet

Date: Sheet

2

Date: Sheet

ompal Electronics, Inc.

R18M-G1-90_DC/DC Interface

R18M-G1-90_DC/DC Interface

R18M-G1-90_DC/DC Interface

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

37 99Wed nesday, May 15, 2019

37 99Wed nesday, May 15, 2019

37 99Wed nesday, May 15, 2019

1

1

1

1

A

A

A

o

o

o

f

f

f

5

LCD POWER CIRCUIT

+

3VS

1U_0201_6.3V6M

C
X22

1

2

D D

E

NVDD8

C C

E

DP_TXP08

E

DP_TXN08

E

DP_TXP18

E

DP_TXN18

E

DP_TXP28

E

DP_TXN28

E

DP_TXP38

E

DP_TXN38

E

DP_AUXP8

E

DP_AUXN8

X1

U

5

N

I

4

N

E

SY6288C20 AAC_SOT23-5

A000079400

S

V

ih=1.5

DP_HPD

E

NVTPW M

I

KOFF#

B

1

UT

O

2

ND

G

3

C

O

1 2

R

X13 100K_0402_ 5%

R

X14 100K_0402_ 5%@

X27 220P_0402_5 0V7K

C

C

X28 220P_0402_5 0V7K

X15 10K_0402_5 %@

R

C

X11 0.1U _0201_10V6K

C

X12 0.1U _0201_10V6K

C

X13 0.1U _0201_10V6K

C

X14 0.1U _0201_10V6K

C

X15 0.1U _0201_10V6K

C

X16 0.1U _0201_10V6K

C

X17 0.1U _0201_10V6K

X18 0.1U _0201_10V6K

C

C

X19 0.1U _0201_10V6K

C

X20 0.1U _0201_10V6K

1

@EMC@

1

@EMC@

1

1

1 2
1 2
1
1
1
1
1

1

1 2
1 2

2

2

2

2

2
2
2
2
2

2

+

LCDVDD

1

2

C

X23

4.7U_040 2_6.3V6M

DP_TXP0 _C

E

DP_TXN0 _C

E

DP_TXP1 _C

E

DP_TXN1 _C

E

DP_TXP2 _C

E

DP_TXN2 _C

E

DP_TXP3 _C

E

DP_TXN3 _C

E

DP_AUXP _C

E

DP_AUXN _C

E

1

X21

C

0.1U_020 1_10V6K

2

@

4

Place closed to JEDP1

+

LCDVDD

10U_0402_6.3V6M

1

C
X1

2

P

ANEL_OD #9

+

3VS

1

C

X26

0.1U_020 1_10V6K

2

@

+

+

5VS

R

1

R

X21 0_0402_5%R S@

1

X2

D

@

RB751V-4 0_SOD323-2

Touch Screen

3VS

1

R

X16 0_0603_5%@

1 2

R

X17 0_0603_5%R S@

1

X18 0_0603_5%R S@

2

+

19VB_CP U

2

2

2

W=20mils

3

+

TS_PW R

R

2

R

1

0.1U_0201_10V6K

W=60mils

HCB2012 KF-221T30_080 5

1 2

S

M01000EJ00 3000ma
220ohm@100mhz
DCR 0.04

X11 10 K_0402_5%

1

@

X12 10 K_0402_5%

2

@

ANEL_OD #_R

P

+

3VS_CAM

C

C

1U_0201_6.3V6M

X30

X31

1

1

2

2

L

+

LCDVDD

@

2

+

X1

INVPWR _B+

C

68P_0402_50V8J

1

X24

@EMC@

2

W=60milsW=60mils

C

1000P_0402_50V7K

1

X25

@EMC@

2

For Camera

I

E

D

MIC_CLK_R56

D

MIC_DATA_ R56

LED PANEL Conn.

+

INVPWR _B+

NVTPW M8

B

KOFF#58

DP_HPD8

+

LCDVDD

+

TS_PW R

T

S_EN58

+

3VS_CAM

YSLC05CH_ SOT23-3

W=

NVTPW M

I

KOFF#

B

DP_HPD

E

ANEL_OD #_R

P

DP_AUXN _C

E

DP_AUXP _C

E

DP_TXP0 _C

E

DP_TXN0 _C

E

DP_TXP1 _C

E

DP_TXN1 _C

E

DP_TXP2 _C

E

DP_TXN2 _C

E

DP_TXP3 _C

E

DP_TXN3 _C

E

S_EN

T

SB20_N0 _L

U

SB20_P0 _L

U

MIC_CLK_R

D

MIC_DATA_ R

D

CA00000U10

S

60mils

X1

D

@EMC@

2

3

1

1

EDP1

J

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

0

1

11

1

1

12

2

1

13

3

1

14

4

1

15

5

1

16

6

1

17

7

1

18

8

1

19

9

1

20

0

2

21

1

2

22

2

2

23

3

2

24

4

2

25

5

2

26

6

2

27

7

2

28

8

2

29

9

2

30

0

3

31

1

3

32

2

3

33

3

3

34

4

3

35

5

ND

G

3

36

6

ND

G

3

37

7

ND

G

3

38

8

ND

G

3

39

9

ND

G

3

40

0

ND

G

4

ACES_50 203-04001-002

CONN@

P010014B10

S

41
42
43
44
45
46

B B

Place closed to JEDP1

2

1

R

X19 15_0402 _1%

1 2

C

U

SB20_P010

U

SB20_N010

A A

5

X32 470P_0402_5 0V8J

2

1

C

X33 470P_0402_5 0V8J

R

X20 15_0402 _1%

2

1

SB20_P0 _RC

U

SB20_N0 _RC

U

4

L

X2

1

DLM0NSN 900HY2D_4P

EMC@

S

M070005U00

SB20_P0 _L

U

34

SB20_N0 _L

U

2

S

S

S

ecurity Classif ication

ecurity Classif ication

ecurity Classif ication

2

2

2

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

018/ 12/1 8 2019/12/18

3

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered D ate

eciphered D ate

eciphered D ate

2

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

Title

itle

itle

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

C

C

C

ustom

ustom

ustom

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

E

E

E

DP/CAMERA/DMIC

DP/CAMERA/DMIC

DP/CAMERA/DMIC

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

1

o

o

o

f

38 99Wed nesday, May 15, 2019

f

38 99Wed nesday, May 15, 2019

f

38 99Wed nesday, May 15, 2019

1

1

1

A

A

A

5

D D

C C

4

3

2

1

R

B B

A A

5

4

eserve Page

S

S

S

ecurity Classif ication

ecurity Classif ication

ecurity Classif ication

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

2

2

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

3

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered D ate

eciphered D ate

eciphered D ate

2

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

Reserve Page

Reserve Page

Reserve Page

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

o

o

o

f

39 99Wed nesday, May 15, 2019

f

39 99Wed nesday, May 15, 2019

f

39 99Wed nesday, May 15, 2019

1

1

1

1

A

A

A

5

+

C
10U_0402_6 .3V6M

D D

1

1

2740

2

C

0.1U_0201_10V6K

R

4004

10K_0402_5%

1 2

R

ESET#

1

C

2747

1U_0201_6.3V6M

2

H

DMI_DCIN_EN

1

@

R

4005

4.7K_0402_5%

2

12

@

R

4009

4.7K_0402_5%

H

DMI_EQ

12

@

R

4010

4.7K_0402_5%

12

@

R

4011

4.7K_0402_5%

H

DMI_I2C_ADDR

2748

2

C

0.1U_0201_10V6K

A
A

A
A

A
A

A
A

2739
C

C C

+

3VS

B B

+

3VS

+

3VS

3VS

2736

12

2737

C
1U_0201_6.3V6M

12

+

3VS

1

2

0.1U_0201_10V6K

PU_DP0_P08
PU_DP0_N08

PU_DP0_P18
PU_DP0_N18

PU_DP0_P28
PU_DP0_N28

PU_DP0_P38
PU_DP0_N38

DC coupling enable; Internal pull up, 3.3V I/O.
L: DC coupling input
H: Default,AC coupling input

R

eceiver equalization setting(Internal 150K PD)
(*) L: programmable EQ for channel loss up to 5.3dB
( ) H: programmable EQ for channel loss up to 10dB
( ) M: programmable EQ for channel loss up to 14dB

I2C Slave Address selection; Internal pull down;3.3V I/O

L: Default, Slave address 0x10-0x2F.

H: Alternative salve address 0x90-0x9F, 0xD0-0xDF.

8

V

+

5VALW

2741
C

0.01U_0402_16V7K

R4006 should be placed close to REXT pin.

Enhance Vswing

IN

7

N

C

6

V

DD

5

E

N

U1302

R

T9041E-15GQW _WDFN8_2X2

S

A00006K300

1

1

2

2

2742

2743

C

C

0.01U_0402_16V7K

0.01U_0402_16V7K

1 2

505 .1U_0402_16V7K

C

1

C

506 .1U_0402_16V7K

1 2

C

507 .1U_0402_16V7K

1 2

C

508 .1U_0402_16V7K

1 2

509 .1U_0402_16V7K

C

1 2

C

510 .1U_0402_16V7K

1 2

511 .1U_0402_16V7K

C

1

512 .1U_0402_16V7K

C

1 2

4006 4.99K_0402 _1%

R

1

2

2

2

P

GOOD

+

1.2V_HDMI

1

V

OUT

2

A

DJ

3

4

G

ND

9

P

GND

H

DMI_DCIN_EN

H

DMI_EQ

H

DMI_I2C_ADDR

H

DMI_TX_P2

H

DMI_TX_N2

H

DMI_TX_P1

H

DMI_TX_N1

H

DMI_TX_P0

H

DMI_TX_N0

H

DMI_CLKP

H

DMI_CLKN

R

ESET#

H

DMI_PRE

R

4.99K_0402_1 %

R

10K_0402_1%

2615

U

6

DD12

V

30

DD12

V

11

DDA12

V

43

DDRX12

V

46

DDRX12

V

15

DDTX12

V

18

DDTX12

V

37

OWERSWI TCH

P

38

N_D2p

I

39

N_D2n

I

41

N_D1p

I

42

N_D1n

I

44

N_D0p

I

45

N_D0n

I

47

N_CLKp

I

48

N_CLKn

I

3

CIN_ENB

D

5

Q

E

31

2C_ADDR

I

10

SV1

R

25

C

N

26

SV2

R

36

EXT

R

4

DB

P

35

ESETB

R

27

RE

P

2

ESTMODEB

T

PS8409AQFN48GTR2 -A0_QFN48_6X6

A0000AC320

S

S IC PS8409AQFN48GTR2-A2 QFN48P REPEATER

4012

4013

12

12

1

@

2

+

3VS

12

4

+

1.2V_HDMI

2738
C

10U_0402_6.3V6M

O
O

O
O

O
O

UT_CLKp

O

UT_CLKn

O

DA_SRC/AUXN

S

CL_SRC/AUXP

S

DA_SNK

S

CL_SNK

S

PD_SRC

H

PD_SNK

H

H

DMI_CEC

H

C

H

DMI_PRE

R

4007

4.7K_0402_5%

@

R

4008

4.7K_0402_5%

H

DMI_ID

1

1

2752
C

2

2

10U_0402_6.3V6M

+

3VS

1

1

2746

2

2

C

2745

2744

C

C

DD33

V

DD33

V

UT_D2p
UT_D2n

UT_D1p
UT_D1n

UT_D0p
UT_D0n

DMI_ID

EC_EN

C

SDA

C

PAD

E

1
24

23
22

20
19

17
16

14
13

33
34
8
7

40
21

32
9
12

29

SCL

28

49

0.01U_0402_16V7K

H

DMI_RT_TX_P2

H

DMI_RT_TX_N2

H

DMI_RT_TX_P1

H

DMI_RT_TX_N1

H

DMI_RT_TX_P0

H

DMI_RT_TX_N0

H

DMI_RT_CLKP

H

DMI_RT_CLKN

A

PU_DP0_CTR L_DATA

A

PU_DP0_CTR L_CLK

H

DMI_CTRL_DAT

H

DMI_CTRL_CLK

H

DMI_HPD

H

DMI_RT_HPD

H

PD_SNK internal PD 150K ohm

H

DMI_ID

Output pre-emphasis setting;Internal pull-up 3.3V I/O
L: Pre-emphasis =2.5dB
H: Default, No Pre-emphasis

HDMI_ID enable ; Internal pull down;3.3V I/O
L: Default, HDMI ID enable
H: HDMI ID disable

0.01U_0402_16V7K

4018 0_04 02_5%

R

RS@

T

4958

T

4959

0.1U_0201_10V6K

12

1

2

A

PU_DP0_CTR L_DATA 8

A

PU_DP0_CTR L_CLK 8

A

PU_DP0_HPD 8

3

+

5VS_DISP

W=40mils

3

UT

2

ND

1 2

L

2512

S

@

M070003V00

3

HCM1012GH90 0BP_4P

1 2

1 2

2513

L

M070003V00

S

@

2

3

HCM1012GH90 0BP_4P

2

1

1 2

2514

L

M070003V00

S

@

3

HCM1012GH90 0BP_4P

1 2

2

1

L

2515

S

@

M070003V00

2

3 4

HCM1012GH90 0BP_4P

1 2

1

543

C

0.1U_0201_10 V6K

2

12

4

1

4

12

4

1

+

5VS

H

DMI_RT_CLKN

H

DMI_RT_CLKP

H

DMI_RT_TX_N0

H

DMI_RT_TX_P0

H

DMI_RT_TX_N1

H

DMI_RT_TX_P1

H

DMI_RT_TX_N2

H

DMI_RT_TX_P2

U

74

1

I

N

AP2330W-7_SC 59-3

S

A00004ZA00

O

G

R

756 0_0402_5%RS@

R

765 0_0402_5%RS@

R

769 0_0402_5%RS@

R

779 0_0402_5%RS@

781 0_0402_5%RS@

R

R

782 0_0402_5%RS@

R

783 0_0402_5%RS@

794 0_0402_5%RS@

R

H

2

@

1

H

H

H

H

H

H

H

Z

HDMI_ROYALTY

R

R

45@

DMI_L_CLKN

2749

C

3.3P_0402_50 V8

DMI_L_CLKP

DMI_L_TX_N0

DMI_L_TX_P0

DMI_L_TX_N1

DMI_L_TX_P1

DMI_L_TX_N2

DMI_L_TX_P2

2

ZZ

OYALTY HDMI W/LOGO+HDCP

O0000003HM

Improve Intra-pair Skew on CLK+/-

+

5VS_DISP

H

DMI_RT_HPD

H

DMI_L_CLKN

H

DMI_L_CLKP

H

DMI_L_TX_N0

H

DMI_L_TX_P0

H

DMI_L_TX_N1

H

DMI_L_TX_P1

H

DMI_L_TX_N2

H

DMI_L_TX_P2

1

For HDMI DDC Capacitance Leakage issue

2016

@EMC@

D

6

/O4

I

5

DD

V

4

/O3

I

AZC099-04S.R7G_SOT 23-6

C300001G00

S

2017

D

1

1

2

2

4

4

5

3

3

8

L05ESDL5V0NA-4 SLP2 510P8

C300003Z00

S

D

2018

1

1

2

2

4

4

5

3

3

8

L05ESDL5V0NA-4 SLP2 510P8

S

C300003Z00

3

/O2

I

2

ND

G

1

/O1

I

MC@

@E

9

10

8

9

7

7

6

65

@E

MC@

9

10

8

9

7

7

6

65

H

DMI_CTRL_CLK

H

DMI_CTRL_DAT

H

DMI_L_CLKN

H

DMI_L_CLKP

H

DMI_L_TX_N0

H

DMI_L_TX_P0

H

DMI_L_TX_N1

H

DMI_L_TX_P1

H

DMI_L_TX_N2

H

DMI_L_TX_P2

HDMI connector

HDMI1

J

19

P_DET

H

18

5V

+

17

DC/CEC_GND

D

16

DA

S

15

CL

S

14

eserved

R

13

EC

C

12

K-

C

11

K_shield

C

10

K+

C

9

0-

D

8

0_shield

D

7

0+

D

6

1-

D

5

1_shield

D

4

1+

D

3

2-

D

2

2_shield

D

1

2+

D

ACON_HMR2E-AK120D

CONN@

C232000Y00

D

20

ND

G

21

ND

G

22

ND

G

23

ND

G

2K_0402_5%

H

DMI_CTRL_DAT

H

DMI_CTRL_CLK

H

+

5VS_DISP

R

2K_0402_5%

4015

12

A

A

4016

R

47K_0402_5% @

PU_DP0_CTR L_DATA

PU_DP0_CTR L_CLK

12

R

4014

12

47K_0402_5% @

+

3VS

1

R

4017

2

+

5VS_DISP

DMI_RT_HPD

H

DMI_CTRL_DAT

H

DMI_CTRL_CLK

H

DMI_L_CLKN

H

DMI_L_CLKP

H

DMI_L_TX_N0

H

DMI_L_TX_P0

H

DMI_L_TX_N1

H

DMI_L_TX_P1

H

DMI_L_TX_N2

H

DMI_L_TX_P2

A A

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

2

2

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered Date

eciphered Date

eciphered Date

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

Title

itle

itle

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

ustom

ustom

ustom

Date: Sheet

Date: Sheet

2

Date: Sheet

ompal Electronics, Inc.

H

H

H

DMI REDRIVER (PS8409)

DMI REDRIVER (PS8409)

DMI REDRIVER (PS8409)

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

1

1

1

1

A

A

A

o

o

o

f

40 99Wednesday, May 15, 2019

f

40 99Wednesday, May 15, 2019

f

40 99Wednesday, May 15, 2019

5

D D

C C

4

3

2

1

R

B B

A A

5

4

eserve Page

S

S

S

ecurity Classif ication

ecurity Classif ication

ecurity Classif ication

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

2

2

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

3

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered D ate

eciphered D ate

eciphered D ate

2

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

Reserve Page

Reserve Page

Reserve Page

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

o

o

o

f

41 99Wed nesday, May 15, 2019

f

41 99Wed nesday, May 15, 2019

f

41 99Wed nesday, May 15, 2019

1

1

1

1

A

A

A

5

4

3

2

1

+

5VALW

S14

U

5

N

I

D D

C C

B B

+

5VALW _MUX

12

R

4.7K_040 2_5%

O

12

R
10K_040 2_1%

R

S114

10K_040 2_5%

R

S115

10K_040 2_5%

U

SB_EN58,72,73

S20

CP_DET#

S128

+

3VO_MUX

12

12

@

LUG_ORI

P

+

USB3_VC CC

12

R

S134

200K_04 02_1%

MON

V

12

R

S135

10K_040 2_1%

4

N

E

SY6288C20 AAC_SOT23-5

U

SB3_ARX _DTX_P310

U

SB3_ARX _DTX_N310

U

SB3_ATX _DRX_P310

U

SB3_ATX _DRX_N310

10K_040 2_5%

10K_040 2_5%

1

UT

O

2

ND

G

3

C

O

U

SB3.0 (Port 3)

+

3VO_MUX

12

R

S1

R

S2

10K_040 2_5%

1

M

12

@

10K_040 2_5%

+

5VALW _MUX

0.1U_0201_10V6K

10U_0402_6.3V6M

1

1

C

C
S15

S116

2

2

C

lose to Pin19

C1_VCON N

C

C

C2_VCON N

C

C

U

S3

C1_VCON N

V

CP_DET#

O

CP_DET#4 3

U

SBC_EN43

1 2

C

S125 0.22U_02 01_6.3V6K

1 2

C

S126 0.22U_02 01_6.3V6K

1 2

C

S127 0.22U_02 01_6.3V6K

1 2

C

S128 0.22U_02 01_6.3V6K

1

S3

R

2

0

M

12

R

S4

@

2

1

S137 0_04 02_5%

R

U
U

U
U

O

SBC_EN

U

SB3_ARX _C_DTX_P3
SB3_ARX _C_DTX_N3

SB3_ATX _C_DRX_P3
SB3_ATX _C_DRX_N3

LUG_ORI

P

1

M

0

M

12

R

S129

6.2K_040 2_1%

4.7U_040 2_6.3V6M

T

YPEC_1P5A 43,58

C

16

15

4
5

6
7

23
21
22

18

25

+

S14

V

MON

O

CP_DET

V

BUS_EN

System side

S

SRX_1P/2N

S

SRX_1N/2P

S

STX_1P/2N

S

STX_1N/2P

G

PIO

C

URRENT_M1

C

URRENT_M0

R

EXT

E

-PAD

3VO_MUX

1

2

DO_3V3
L

20

10 Gbps 2:1 MUX

V_IN
5

19

C
C

T

ype-C Port Side

C

_TX2_1P/2N

C

_TX2_1N/2P

C

_RX2_1P/2N

C

_RX2_1N/2P

C

_TX1_1P/2N

C

_TX1_1N/2P

C

_RX1_1P/2N

C

_RX1_1N/2P

CON_IN
V

RTS5441 E-GRT_QFN24_4 X4

13

+

5VALW _MUX

1

C

0.1U_020 1_10V6K

2

Close to Pin13

17

MON

C1
C2

S117

12
14

11
10

24
1

8
9

2
3

C

C2_VCON N

C

SB3_CC_ TX_P2

U

SB3_CC_ TX_N2

U

SB3_CC_ RX_P2

U

SB3_CC_ RX_N2

U

SB3_CC_ TX_P1

U

SB3_CC_ TX_N1

U

SB3_CC_ RX_P1

U

SB3_CC_ RX_N1

U

C

C1_VCON N 43

C

C2_VCON N 43

1 2

C

S112 .1U _0402_16V7K

2

1

S113 .1U _0402_16V7K

C

1 2

C

S121 0.3 3U_0201_6.3V6 M

1 2

C

S122 0.3 3U_0201_6.3V6 M

2

1

S114 .1U _0402_16V7K

C

1 2

C

S115 .1U _0402_16V7K

1 2

C

S123 0.3 3U_0201_6.3V6 M

2

1

S124 0.3 3U_0201_6.3V6 M

C

SB3_CC_ RX_P2_C

U

SB3_CC_ RX_N2_C

U

R

S130

220K_02 01_1%

SB3_CC_ RX_P1_C

U

SB3_CC_ RX_N1_C

U

R

S132

220K_02 01_1%

1 2

1 2

SB3_CC_ TX_P2_C

U

SB3_CC_ TX_N2_C

U

SB3_CC_ RX_P2_C

U

SB3_CC_ RX_N2_C

U

SB3_CC_ TX_P1_C

U

SB3_CC_ TX_N1_C

U

SB3_CC_ RX_P1_C

U

SB3_CC_ RX_N1_C

U

R

S131

220K_02 01_1%

1 2

S133

R
220K_02 01_1%

1 2

2

1

S130 220P_04 02_50V8J

2

1

S129 220P_04 02_50V8J

U

SB3_CC_ TX_P2_C 43

U

SB3_CC_ TX_N2_C 43

U

SB3_CC_ RX_P2_C 43

U

SB3_CC_ RX_N2_C 43

U

SB3_CC_ TX_P1_C 43

U

SB3_CC_ TX_N1_C 43

U

SB3_CC_ RX_P1_C 43

U

SB3_CC_ RX_N1_C 43

5441E Current Limit

M0M1

L

A A

H

c

onfirm realtek hand-shake

5

0.9A

LH

1.5A

H

3A

MODE

H

TYPEC_1P5A_EC

RTS5441 M0 truth table by 2018 BIOS spec

limit point

MODE

H

L

4

3A

1.5A

3.5A

1.92A

AC mode or Battery >30%

Battery <30% when DC mode

Condition

S

S

S

ecurity Classif ication

ecurity Classif ication

ecurity Classif ication

2

2

2

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

018/ 12/1 8 2019/12/18

3

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered D ate

eciphered D ate

eciphered D ate

2

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

Title

itle

itle

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

C

C

C

ustom

ustom

ustom

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

C

C

C

C+ USB MUX

C+ USB MUX

C+ USB MUX

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

1

o

o

o

f

42 99Wed nesday, May 15, 2019

f

42 99Wed nesday, May 15, 2019

f

42 99Wed nesday, May 15, 2019

1

1

1

A

A

A

5

4

3

2

1

+

5VALW

C

150U_D2_6.3VY_R15M

SGA00003700

S95

1

+

2

D D

U

SBC_EN42

F

or ESD request

D

S3

EMC@

U

SB3_CC_ TX_P1_C42

U

SB3_CC_ TX_N1_C42

C1_VCON N

C

BTA_SBU 1

T

C C

U

SB3_CC_ TX_N2_C42

U

SB3_CC_ TX_P2_C42

1

2

4

5

3

TVW DF1004AD0_DF N9

SC300003Z00

S4

EMC@

D

1

2

4

5

SB3_CC_ TX_P1_C

U

9

SB3_CC_ TX_N1_C

U

8

C1_VCON N

C

7

BTA_SBU 1

T

6

9

8

SB3_CC_ TX_N2_C

U

7

SB3_CC_ TX_P2_C

U

6

12

B77

R
47K_040 2_5%

0.1U_0201_10V6K
C

1

S96

2

U

S11

6

I

O

UT

N

5

SET

R

S

G

ND

ET

4

F

E

LAG

N

SY6861B1A BC_TSOT23-6

footprint : G518
PN : SA0000BDN00(SILERGY SY6861B1)

+

USB3_VC CC

SET

22U_0805_25V6M

22U_0805_25V6M

0.1U_0402_25V6
C

C

1

1

S97

@

2

2

1

2

3

1 2

@

R

S136 0_04 02_5%

1

S100

C

0.1U_020 1_10V6K

2

@

C

1

S99

S98

@

@

2

O

CP_DET# 42

R

R

S113

6.2K_040 2_5%

1

R

4.3K_040 2_5%

2

S109

1

2

61

D

S

1

R

S110

8.2K_040 2_5%

2
3

D

S

Q

4

2N7002K DW_SOT36 3-6

2

G

S2A

Q

2N7002K DW_SOT36 3-6

S2B

5

G

T

YPEC_3A 58

T

YPEC_1P5A 42,58

SILERGY SY6861B1 MOS Current Limit

+

USB3_VC CC

TYPEC_1P5A

L

H

*H

+

USB3_VC CC

TYPEC_3A

LL

H

L

H

6.2

3.53

2.54

MODERSET(kΩ)

0.9A

1.5A

limit point

1.09A

1.92A

2.67A

2A

3.5A1.94

3A

3

TVW DF1004AD0_DF N9

SC300003Z00

D

S6

SB20_P3 _L

U

SB20_N3 _L

B B

A A

U

SB20_P310

U

SB20_N310

U

U

SB3_CC_ RX_N2_C42

U

SB3_CC_ RX_P2_C42

C2_VCON N

C

BTA_SBU 2

T

U

SB3_CC_ RX_N1_C42

U

SB3_CC_ RX_P1_C42

1

R

S144 15_0402 _1%

S141 470P_04 02_50V8J

C

C

S142 470P_04 02_50V8J

S145 15_0402 _1%

R

5

2

1

2

1

1 2

EMC@

1

2

4

5

3

TVW DF1004AD0_DF N9

SC300003Z00

S5

EMC@

D

1

2

4

5

3

TVW DF1004AD0_DF N9

SC300003Z00

2

U

9

U

8

U

7

U

6

C

9

T

8

U

7

U

6

SB20_P3 _RC

U

SB20_N3 _RC

U

SB20_P3 _L

SB20_N3 _L

SB3_CC_ RX_N2_C

SB3_CC_ RX_P2_C

C2_VCON N

BTA_SBU 2

SB3_CC_ RX_N1_C

SB3_CC_ RX_P1_C

2

3

S10

EMC@

L

2

3

DLM0NSN 900HY2D_4P

SM070005U00

1

4

4

10U_060 3_25V6M

D

S19
PESD24V S2UT_SOT23-3

SCA0000 4500

SB20_P3 _L

U

1

SB20_N3 _L

U

4

2

2

3

EMC@

1

S

S

S

ecurity Classif ication

ecurity Classif ication

ecurity Classif ication

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

C

S13

SB3_CC_ TX_P1_C

U

SB3_CC_ TX_N1_C

U

C

C1_VCON N42

0.1U_040 2_25V6

SB3_CC_ RX_N2_C

U

SB3_CC_ RX_P2_C

U

2

2

2

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

3

2

1

C

S840.1U_040 2_25V6

SB20_P3 _L

U

SB20_N3 _L

U

BTA_SBU 1

T

12

C

S86

C

C1_VCONN & CC2_VCONN need 20miil trace width.

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered D ate

eciphered D ate

eciphered D ate

J

TYPEC1

A1

G

ND

A2

S

STXP1

A3

S

STXN1

A4

BUS

V

A5

C1

C

A6

D

P1

A7

N1

D

A8

BU1

S

A9

V

BUS

A10

S

SRXN2

A11

S

SRXP2

A12

G

ND

1

ND

G

2

ND

G

3

ND

G

4

ND

G

DEREN_4 0-42407-024630 0RHF

CONN@

D

C23300RC00

12

B

ND

G

B11

S

SRXP1

B10

S

SRXN1

B9

BUS

V

B8

BU2

S

B7

N2

D

B6

P2

D

B5

C2

C

B4

BUS

V

B3

STXN2

S

B2

STXP2

S

B1

G

ND

5

ND

G

6

ND

G

7

ND

G

8

ND

G

2

SB3_CC_ RX_P1_C

U

SB3_CC_ RX_N1_C

U

1 2

C

S87 0.1U_0402 _25V6

BTA_SBU 2

T

SB20_N3 _L

U

SB20_P3 _L

U

C

1 2

C

S85 0.1U_0402 _25V6

SB3_CC_ TX_N2_C

U

SB3_CC_ TX_P2_C

U

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

C

C

C

ustom

ustom

ustom

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

U

U

U

SB TYPE C

SB TYPE C

SB TYPE C

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

C2_VCON N 42

1

o

o

o

f

43 99Wed nesday, May 15, 2019

f

43 99Wed nesday, May 15, 2019

f

43 99Wed nesday, May 15, 2019

1

1

1

A

A

A

5

D D

C C

4

3

2

1

R

B B

A A

5

4

eserve Page

S

S

S

ecurity Classif ication

ecurity Classif ication

ecurity Classif ication

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

2

2

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

3

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered D ate

eciphered D ate

eciphered D ate

2

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

Reserve Page

Reserve Page

Reserve Page

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

o

o

o

f

44 99Wed nesday, May 15, 2019

f

44 99Wed nesday, May 15, 2019

f

44 99Wed nesday, May 15, 2019

1

1

1

1

A

A

A

5

D D

C C

4

3

2

1

R

B B

A A

5

4

eserve Page

S

S

S

ecurity Classif ication

ecurity Classif ication

ecurity Classif ication

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

2

2

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

3

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered D ate

eciphered D ate

eciphered D ate

2

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

Reserve Page

Reserve Page

Reserve Page

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

o

o

o

f

45 99Wed nesday, May 15, 2019

f

45 99Wed nesday, May 15, 2019

f

45 99Wed nesday, May 15, 2019

1

1

1

1

A

A

A

5

D D

C C

4

3

2

1

R

B B

A A

5

4

eserve Page

S

S

S

ecurity Classif ication

ecurity Classif ication

ecurity Classif ication

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

2

2

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

3

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered D ate

eciphered D ate

eciphered D ate

2

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

Reserve Page

Reserve Page

Reserve Page

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

o

o

o

f

46 99Wed nesday, May 15, 2019

f

46 99Wed nesday, May 15, 2019

f

46 99Wed nesday, May 15, 2019

1

1

1

1

A

A

A

5

D D

C C

4

3

2

1

R

B B

A A

5

4

eserve Page

S

S

S

ecurity Classif ication

ecurity Classif ication

ecurity Classif ication

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

2

2

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

3

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered D ate

eciphered D ate

eciphered D ate

2

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

Reserve Page

Reserve Page

Reserve Page

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

o

o

o

f

47 99Wed nesday, May 15, 2019

f

47 99Wed nesday, May 15, 2019

f

47 99Wed nesday, May 15, 2019

1

1

1

1

A

A

A

5

D D

C C

4

3

2

1

R

B B

A A

5

4

eserve Page

S

S

S

ecurity Classif ication

ecurity Classif ication

ecurity Classif ication

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

2

2

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

3

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered D ate

eciphered D ate

eciphered D ate

2

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

Reserve Page

Reserve Page

Reserve Page

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

o

o

o

f

48 99Wed nesday, May 15, 2019

f

48 99Wed nesday, May 15, 2019

f

48 99Wed nesday, May 15, 2019

1

1

1

1

A

A

A

5

D D

C C

4

3

2

1

R

B B

A A

5

4

eserve Page

S

S

S

ecurity Classif ication

ecurity Classif ication

ecurity Classif ication

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

2

2

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

3

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered D ate

eciphered D ate

eciphered D ate

2

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

Reserve Page

Reserve Page

Reserve Page

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

o

o

o

f

49 99Wed nesday, May 15, 2019

f

49 99Wed nesday, May 15, 2019

f

49 99Wed nesday, May 15, 2019

1

1

1

1

A

A

A

5

D D

C C

4

3

2

1

R

B B

A A

5

4

eserve Page

S

S

S

ecurity Classif ication

ecurity Classif ication

ecurity Classif ication

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

2

2

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

3

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered D ate

eciphered D ate

eciphered D ate

2

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

Reserve Page

Reserve Page

Reserve Page

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

o

o

o

f

50 99Wed nesday, May 15, 2019

f

50 99Wed nesday, May 15, 2019

f

50 99Wed nesday, May 15, 2019

1

1

1

1

A

A

A

A

B

C

D

E

+3V_LAN Rising time (10%~90%) must >0.5mS and <100mS

+

3VALW

6

0mil

1 1

2

C

L16

1U_0201_6.3V6M

+

3VS

2 2

1

F

rom EC

H

igh active.
EN threshold vo ltage min:1.2V
typ:1.6V max:2 .0V
Current limit t hreshold 1.5~2.8A

+

3V_LAN Rising t ime must >0.5ms an d <100ms

12

L3

R
1K_0402_5%

SOLATEB

I

L5

R
15K_0402_5%

1 2

L2

R
0_0805_5%

1

U

L1

5

I

N

4

E

N

SY6288C20AAC_SOT23-5

L

AN_PWR_EN

@

2

O

UT

G

ND

O

C

1

2

3

L

+

3V_LAN

AN_PWR_EN 58

6

0mil

LAN_CLKREQ# pull up at PCH side

L1

Y

C

18P_0402_50V8J

25MHZ_20PF_XRCGB25M000F2P 34R0

3

TLI

X

3

C

C

N

1

L21

2

N

2

4

TLO_R

X

1

1

R

L14

1

L22

C
18P_0402_50V8J

2

1

2

680_0402_5%

P/N: SJ10000UP00 (S CRYSTAL 25MHZ 10PF XRCGB25M000F2P34R0)

3 3

R

RTL8118ASA SWR mode

W

=60mil

+

REGOUT

C

0.1U_0201_10V6K

1

L1

LDO@

2

X

TLO

TL8111H LDO mode

LDO@

1 2

R

L1 0_0603_5%

SWR@

1 2

L1

L

2.2UH_HPC252012NF-2R2M_20%

I

DC=1200mA

U

sing for Switch mode

T

he trace length from
Lx to PIN48 (R EGOUT)
and from C to L x must
< 200mils.

11/27: P/N change to SH00000RT00
( S COIL 2.2UH +-20%
HPC252012NF-2R2M 1.3A)

+

3V_LAN

C

LKREQ_PCIE#310

P

CIE_ATX_C_DRX_P46

P

CIE_ATX_C_DRX_N46

4.7U_0402_6.3V6M

1

2

+

LAN_VDD

C

LK_PCIE_P310

C

LK_PCIE_N310

W

=60mil

300mA

0.1U_0201_10V6K

C

C

1

L3

L2

SWR@

SWR@

2

C

C

0.1U_0201_10V6K

0.1U_0201_10V6K

1

1

L4

L5

2

2

0.1U_0201_10V6K

0.1U_0201_10V6K

C

C

1

1

L7

L6

2

2

+

LAN_VDD

0.1U_0201_10V6K

C

C

1U_0201_6.3V6M

1

1

L8

L9

2

2

Place near Pin 22Place near Pin 3,8,22,30

+

3V_LAN

300mA

0.1U_0201_10V6K

C

1

L10

2

Place near Pin 11,32

Using for Switch mode

The trace length
from C to
PIN46,47(VDDREG)
must < 200mils.

L2

U

AN_MIDI0+

L

AN_MIDI0-

L

AN_MIDI1+

L

AN_MIDI1-

L

AN_MIDI2+

L

AN_MIDI2-

L

AN_MIDI3+

L

AN_MIDI3-

L

1

DIP0

M

2

DIN0

M

3

VDD10

A

4

DIP1

M

5

DIN1

M

6

DIP2

M

7

DIN2

M

8

VDD10

A

9

DIP3

M

10

DIN3

M

11

VDD33

A

12

LKREQB

C

13

SIP

H

14

SIN

H

15

EFCLK_P

R

16

EFCLK_N

R

RTL8118ASA-CG_QFN32_4X4

A0000B9F20

S

H

ERSTB

P

SOLATEB

I

ANWAKEB

L

VDD10

D

DDREG

V

EGOUT

R

ED1/GPIO

L

KXTAL1

C

KXTAL2

C

VDD10

A

VDD33

A

SOP

H

SON

ED2

L

ED0

L

SET

R

ND

G

17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33

CIE_ARX_C_DTX_P4

P
P

CIE_ARX_C_DTX_N4

I

SOLATEB

AN_PME#

L

REGOUT

+

AN_LED2

L

AN_LED1_GPO

L

AN_LED0

L

TLI

X

TLO

X

AN_RST

L

T

4963 @

T

4964 @

1

2.49K_0402_1%

Place near Pin 11,32

W=60mil

0.1U_0201_10V6K

C

1

L11

2

+

LAN_VDD

+

3V_LAN

12

@

L70_0402_5%

R

2

L8

R

C

C

0.1U_0201_10V6K

4.7U_0402_6.3V6M

1

1

L13

L12

SWR@

SWR@

2

2

C

4.7U_0402_6.3V6M

1

L14

@

2

Reserve for surge improvement

P

lace near Pin 11,32

12

L17.1U_0402_16V7K

C

12

C

r

eserve EC_PME# pull high 47K to +3VLP_EC

L18.1U_0402_16V7K

L

AN_GPO 58

f

or disable PHY

reserve 0 ohm

AN_LED1_GPO

L

P

CIE_ARX_DTX_P4 6

P

CIE_ARX_DTX_N4 6

A

PU_PCIE_RST# 9,27,52,68

1 2

R

L40_0402_5% RS@

12

R

L610K_0402_5%

+

3V_LAN

4.7U_0402_6.3V6M

1

2

C
L15

@

L

AN_WAKE# 58

12

+

3V_LAN

L910K_0402_5% @

R

SA0000B9F20, S IC RTL8118ASA-CG QFN 32P E-LAN CTRL

LAN Connector

T

AN_TERMAL

AN_MIDI3-

L

AN_MIDI3+

L

AN_MIDI2-

L

AN_MIDI2+

L

AN_MIDI1-

L

AN_MIDI1+

L

AN_MIDI0-

L

AN_MIDI0+

L

0.1U_0201_10V6K

4 4

L

1

L24

C

2

L1

1

T

2

T

3

T

4

T

5

T

6

T

7

T

8

T

9

T

10

T

11

T

12

T

GST5009-E

SP050006B10

24

M

CT1

CT1

23

M

D1+

X1+

22

M

D1-

X1-

21

M

CT2

CT2

20

M

D2+

X2+

19

M

D2-

X2-

18

M

CT3

CT3

17

M

D3+

X3+

16

M

D3-

X3-

15

M

CT4

CT4

14

M

D4+

X4+

13

M

D4-

X4-

12

12

L11

L12
R

R

75_0402_1%

75_0402_1%

J45_MIDI3-

R

J45_MIDI3+

R

J45_MIDI2-

R

J45_MIDI2+

R

J45_MIDI1-

R

J45_MIDI1+

R

J45_MIDI0-

R

J45_MIDI0+

R

12

12

L10

L13
R

R

75_0402_1%

75_0402_1%

J45_GND

R

R

J45_MIDI3-

R

J45_MIDI3+

R

J45_MIDI1-

R

J45_MIDI2-

R

J45_MIDI2+

R

J45_MIDI1+

R

J45_MIDI0-

R

J45_MIDI0+

JRJ45

8

P

R4-

7

P

R4+

6

P

R2-

5

P

R3-

4

P

R3+

3

P

R2+

2

P

R1-

1

P

R1+

S

ANTA_130460-5

CONN@

D

C234007W00

L23

12

G

ND

11

G

ND

10

G

ND

9

G

ND

L

ANGND

L

ANGND

C
10P_0402_50V8J

3

1

4

0mil40mil

R

J45_GND

12

2

A
Z5125-02S_SOT23-3

D

L1

E

MC@

JP@

PL1

J

JUMP_43X118

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2

2

2

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered Date

eciphered Date

eciphered Date

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

ustom

ustom

ustom

Date: Sheet

Date: Sheet

D

Date: Sheet

ompal Electronics, Inc.

L

L

L

AN RTL8118ASA

AN RTL8118ASA

AN RTL8118ASA

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

E

1

1

1

A

A

A

o

o

o

f

51 99Wednesday, May 15, 2019

f

51 99Wednesday, May 15, 2019

f

51 99Wednesday, May 15, 2019

A

B

C

D

E

Wireless LAN

1 2

S146 15_0402 _1%

R

1 2

S143 470P_04 02_50V8J

6

0mil

+

3VS

1 2

@

R

1 1

2 2

M101

0_0805_ 5%

+

3VALW

C

1U_0201_6.3V6M

M71

1

2

W

LAN_ON58

N

GFF WL+BT (KEY E)

+

3VS_W LAN

1

C

4.7U_040 2_6.3V6M

2

5

4

1

O

UT

G

ND

O

C

@

C

0.1U_020 1_10V6K

2

1

2

3

M68

U

M3

I

N

E

N

SY6288C20 AAC_SOT23-5

S

A000079400

V

ih=1.5

M69

W=60mils

1

M70

C

0.1U_020 1_10V6K

2

+

3VS_W LAN

+

P
P

P
P

C

3VS_W LAN

U

SB20_P510

U

SB20_N510

CIE_ATX_C _DRX_P56
CIE_ATX_C _DRX_N56

CIE_ARX_D TX_P56
CIE_ARX_D TX_N56

C

LK_PCIE_P 210

C

LK_PCIE_N 210

LKREQ_P CIE#210

C

1 2

C

S144 470P_04 02_50V8J

1 2

R

S147 15_0402 _1%

SB20_P5 _RC

U

SB20_N5 _RC

U

R

M110

12

10K_040 2_5%

SB20_P5 _RC

U

SB20_N5 _RC

U

J

NGFF1

1

G

ND_1

3

U

SB_D+

5

U

SB_D-

7

G

ND_7

9

S

DIO_CLK

11

S

DIO_CMD

13

S

DIO_DAT0

15

S

DIO_DAT1

17

S

DIO_DAT2

19

S

DIO_DAT3

21

S

DIO_WAKE

23

S

DIO_RST

25

G

ND_33

27

P

ET_RX_P0

29

P

ET_RX_N0

31

G

ND_39

33

P

ER_TX_P0

35

P

ER_TX_N0

37

G

ND_45

39

R

EFCLK_P0

41

R

EFCLK_N0

43

G

ND_51

45

C

LKREQ0#

47

P

EWAKE0#

49

G

ND_57

51

R

SVD/PCIE_RX_P1

53

R

SVD/PCIE_RX_N1

55

G

ND_63

57

R

SVD/PCIE_TX_P1

59

R

SVD/PCIE_TX_N1

61

G

ND_69

63

R

SVD_71

65

R

SVD_73

67

G

ND_75

69

ND2

G

BELLW _80152-3221

CONN@

S

P070013E00

KEY E

U

USCLK(32KHz)

S

W
W

3

.3VAUX_2

3

.3VAUX_4

L

ED1#

CM_CLK

P
CM_SYNC

P

CM_OUT

P

CM_IN

P

ED2#

L
ND_18

G

ART_WAKE

ART_TX

U

ART_RX

U
ART_RTS

U

ART_CTS

U

Link_RST

C

Link_DATA

C

Link_CLK

C

OEX3

C

OEX2

C

OEX1

C

ERST0#

P
_DISABLE2#
_DISABLE1#

2C_DAT

I

2C_CLK

I

2C_IRQ

I

SVD_64

R

SVD_66

R

SVD_68

R

SVD_70

R

.3VAUX_72

3

.3VAUX_74

3

ND1

G

2
4
6

8
10
12
14
16
18
20
22

24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66

68

+

3VS_W LAN

U

U

E
E

W
B
W

C

M79

@

10U_060 3_6.3V6M

1 2

ART_0_A RXD_R_DTXD

ART_0_A TXD_R_DRXD

51TXD_P 80DATA_R
51RXD_P 80CLK_R

T

L_RST#_ R

T_ON

L_OFF#

C

M80

10U_060 3_6.3V6M

1 2

4947

@

ART_0_A TXD_R_DRXD

U

ART_0_A RXD_R_DTXD

U

1 2

R

M114 0_ 0402_5%@

1 2

R

M115 0_ 0402_5%@

R

M106 0_0 402_5%RS@

R

M107 0_0 402_5%RS@

TP@

2

R

M109 0_0 402_5%RS@

12
12

2

1

R

M108 100K_0402_5%

1

1 2

R

M112 1K _0402_5%@

1 2

R

M113 1K _0402_5%@

U

ART_0_A RXD_DTXD 10

U

ART_0_A TXD_DRXD 10

E

C_TX 58

E

C_RX 58

A

PU_PCIE_R ST# 9 ,27,51,68

B

T_ON 58

W

L_OFF# 58

+

1.8VS

3 3

4 4

S

S

S

ecurity Classif ication

ecurity Classif ication

ecurity Classif ication

2

2

2

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

018/ 12/1 8 2019/12/18

C

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered D ate

eciphered D ate

eciphered D ate

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

C

C

C

ustom

ustom

ustom

Date: Sheet

Date: Sheet

D

Date: Sheet

ompal Electronics, Inc.

M

M

M

.2 KEY-E (WLAN)

.2 KEY-E (WLAN)

.2 KEY-E (WLAN)

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

E

1

1

1

A

A

A

o

o

o

f

52 99Wed nesday, May 15, 2019

f

52 99Wed nesday, May 15, 2019

f

52 99Wed nesday, May 15, 2019

5

D D

C C

4

3

2

1

R

B B

A A

5

4

eserve Page

S

S

S

ecurity Classif ication

ecurity Classif ication

ecurity Classif ication

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

2

2

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

3

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered D ate

eciphered D ate

eciphered D ate

2

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

Reserve Page

Reserve Page

Reserve Page

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

o

o

o

f

53 99Wed nesday, May 15, 2019

f

53 99Wed nesday, May 15, 2019

f

53 99Wed nesday, May 15, 2019

1

1

1

1

A

A

A

5

D D

C C

4

3

2

1

R

B B

A A

5

4

eserve Page

S

S

S

ecurity Classif ication

ecurity Classif ication

ecurity Classif ication

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

2

2

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

3

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered D ate

eciphered D ate

eciphered D ate

2

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

Reserve Page

Reserve Page

Reserve Page

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

o

o

o

f

54 99Wed nesday, May 15, 2019

f

54 99Wed nesday, May 15, 2019

f

54 99Wed nesday, May 15, 2019

1

1

1

1

A

A

A

5

D D

C C

4

3

2

1

R

B B

A A

5

4

eserve Page

S

S

S

ecurity Classif ication

ecurity Classif ication

ecurity Classif ication

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

2

2

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

3

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered D ate

eciphered D ate

eciphered D ate

2

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

Reserve Page

Reserve Page

Reserve Page

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

o

o

o

f

55 99Wed nesday, May 15, 2019

f

55 99Wed nesday, May 15, 2019

f

55 99Wed nesday, May 15, 2019

1

1

1

1

A

A

A

A

B

C

D

E

HD Audio Codec

1 1

Reserved for RF

2 2

+

3VS

A13 100K_0402_1%

R

3 3

S

ENSE_A

12

H

DA_RST#_R9

H

P_PLUG#7 3

2000mA 600ohm@100MHz
DCR 0.1

+

5VS

Pin9 need to matching with SOC HDA
interface.

2

@EMC@

1

TAI-TECH HCB1608K F-601T20

1 2

SM01000UN00

C

A2710P_0402_50 V8J

A1

L

A2 0_0402_5%RS@

R

+

1.8VS

+

3VS

A4 0_0402_5%RS@

R

D

MIC_CLK

4

E

C_MUTE#58

C

lose codec

A12 200K_0402 _1%

R

A17 20K_0402_ 5%@

R

G

NDA

1

C

2.2U_0402_6.3 V6M

2

G

ND

1

1 2

+

MICBIAS

0mil

12

12

A15

+

3VS_DVDD

G

NDA

A19 0_0402_5 %RS@

R

10U_0402_6.3V6M

C

1

A1

2

2

20mil

near Pin1

L

INE1_L

L

INE1_R

R

ING2

S

LEEVE

D

MIC_DATA

D

MIC_CLK

M

ONO_IN

+

3VALW

A19

C

10U_0402_6 .3V6M

40mil

0.1U_0201_10V6K

C

1

A2

2

near Pin9

1 2

A7 0.1U_0201_10V6K

C

1 2

A8 10U_0402_6.3V6M

C

10U_0402_6.3V6M

1

2

22
21

24
23

31
30

17
18

2
3

47

11

12

S

ENSE_A

13
14
15

37
35

36

20

2

1

19

12

4

49

0.1U_0201_10V6K

C

C

10U_0402_6.3V6M

1

1

A3

A29

2

2

near Pin46near Pin41

+

1.8VS_DVDDIO

+

3VS_DVDD

0.1U_0201_10V6K

C

C

1

A9

A10

2

U

A1

L

INE1-L(PORT-C-L)

L

INE1-R(PORT-C-R)

L

INE2-L(PORT-E-L)

L

INE2-R(PORT-E-R)

L

INE1-VREFO-L

L

INE1-VREFO-R

M

IC2-L(PORT-F-L) /RING

M

IC2-R(PORT-F-R) /SLEEVE

G

PIO0/DMIC-DATA

G

PIO1/DMIC-CLK

P

DB

R

ESETB

P

CBEEP

H

P/LINE1 JD(JD1)

M

IC2/LINE2 JD(JD2)

S

PDIFO/FRONT JD(JD3)/GPIO3

C

BP

C

BN

C

PVDD

V

D33 STB

M

IC CAP

D

C DET

T

hermal PAD

ALC255-CG_MQFN48 _6X6

SA000082700

+

5VS_PVDD

+

+

5VS_AVDD

41

46

9

1

VDD

VDD1

VDD2

D

P

P

VDD-IO
D

26

40

VDD1
A

H

POUT-L(PORT-I-L)

H

POUT-R(PORT-I-R)

S

2

0mil

G

near Pin26

+

1.8VS_VDDA

G

VDD2
A

S

PK-OUT-L-

S

PK-OUT-L+

S

PK-OUT-R+

S

PK-OUT-R-

S
B

S

DATA-OUT

S

DATA-IN

PDIF-OUT/GPIO2

M

ONO-OUT

M

IC2-VREFO

L

DO3-CAP

L

DO2-CAP

L

DO1-CAP

V

C

PVEE

A

VSS1

A

VSS2

C

0.1U_0201_10V6K

1

A5

2

NDA

1

2

NDA

P

lace near Pin40

43
42

45
44

32
33

10

YNC

6

CLK

5
8

48

16

29

7
39
27

28

REF

34

25
38

1

2

C

0.1U_0201_10V6K
A11

S
S

S
S

H
H

10mil

C

ODEC_VREF

C

PVEE

G

NDA

1 2

A1

R

C

10U_0402_6.3V6M

A6

10U_0402_6.3V6M

1

2

PKL­PKL+

PKR+
PKR-

P_LEFT
P_RIGHT

H

DA_SYNC_R

H

DA_BIT_CLK_R

H

DA_SDOUT_R

H

DA_SDIN0_AUDIO

+

MIC2_VREFO

5VS

RS@

0_0402_5%

1 2

A3 0_0402_5%RS@

R

C
A12

H

DA_BIT_CLK_R

S

PKR+ 73

S

PKR- 73

1 2

A10 33 _0402_5%

R

1

A14 10U_0402_6 .3V6M

C

1 2

A16 10U_0402_6 .3V6M

C

1 2

A17 10U_0402_6 .3V6M

C

1 2

A14 100 K_0402_5%

R

1 2

A20 2.2U_0402_6.3 V6M

C

1

C

A21 0.1U_0201_10 V6K@

C

1U_0201_6.3V6M

A22

1

2

+

1.8VS

Int. Speaker Conn.

4

0mil

S
S

A5

R
0_0402_5%

1 2

@EMC@

2

A13

C
22P_0402_50 V8J

1

@EMC@

H

DA_SYNC_R 9

H

DA_BIT_CLK_R 9

H

DA_SDOUT_R 9

H

DA_SDIN0 9

S

PKL+

S

PKL-

Digital MIC

1 2

A4 EMC @ PBY160 808T-121Y-N_2P

L

A5 EMC @ PBY160 808T-121Y-N_2P

L

2

1

MIC BOM upload by Audio Team

2

2

G

ND

G

NDA

G

NDA

D

MIC_DATA

R

A7 0_0402_5%

D

MIC_CLK

A6 BLM15 PX221SN1D_2PEMC@

L

SM01000Q500

change PN to SM01000Q500

D

MIC_DATA_R

12

D

MIC_CLK_R

12

PK_L+
PK_L-

J

SPK2

1

1

2

2

3

G

1

4

G

2

CVILU_CI4202M2HR0-N H

CONN@

SP02001CK00

TO eDP cable

D

MIC_DATA_R 38

D

MIC_CLK_R 38

G

ND

Headphone Out

+

MIC2_VREFO

A15 2.2K_0402_5%

R

A18 2.2K_0402_5%

R

1 2

1 2

TO IO/B

S

R

LEEVE

ING2

S

LEEVE 73

R

ING2 73

H

P_LEFT

1

A20 0_0 603_5%@

R

H

P_RIGHT

1 2

A21 0_0 603_5%@

R

L

A22

R

22K_0402_5%

R

A27

22K_0402_5%

2

12

1

E

C_BEEP#58

4 4

A

PU_SPKR9

B

EEP#_R

MC@

@E

1

C

100P_0402_50V8J

A26

2

G

A

A24

R

4.7K_0402_5%

1 2

ND

A25

C

1U_0201_6.3V6M

2

1

M

ONO_IN

G

ND

1

A25 0_0 402_5%RS@

R

1

R

A29 0_0 402_5%RS@

1 2

R

A31 0_0 402_5%RS@

1 2

A33 0_0 402_5%RS@

R

B

2

2

G

NDA

G

ND

1 2

A26 0_0 402_5%RS@

R

1 2

A30 0_0 402_5%RS@

R

1 2

A32 0_0 402_5%RS@

R

1 2

A34 0_0 402_5%RS@

R

+

MICBIAS

G

NDA

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2

2

2

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered Date

eciphered Date

eciphered Date

D

INE1_L

L

INE1_R

D

A3

1

BAT54A-7-F_SOT23-3

S

CSBAT54100

2

3

2

1

C

A23 4.7U _0402_6.3V6M

1 2

A24 4.7U _0402_6.3V6M

C

A23

R

4.7K_0402_5%

A28

R

4.7K_0402_5%

T

T

Title

itle

itle

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

ustom

ustom

ustom

Date: Sheet

Date: Sheet

Date: Sheet

H

POUT_L_1

2

H

POUT_R_1

12

12

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

ompal Electronics, Inc.

H

H

H

D Audio Codec ALC255

D Audio Codec ALC255

D Audio Codec ALC255

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

E

H

POUT_L_1 73

H

POUT_R_1 73

o

o

o

f

56 99Wednesday, May 15, 2019

f

56 99Wednesday, May 15, 2019

f

56 99Wednesday, May 15, 2019

1

1

1

A

A

A

5

D D

C C

4

3

2

1

R

B B

A A

5

4

eserve Page

S

S

S

ecurity Classif ication

ecurity Classif ication

ecurity Classif ication

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

2

2

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

3

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered D ate

eciphered D ate

eciphered D ate

2

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

Reserve Page

Reserve Page

Reserve Page

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

o

o

o

f

57 99Wed nesday, May 15, 2019

f

57 99Wed nesday, May 15, 2019

f

57 99Wed nesday, May 15, 2019

1

1

1

1

A

A

A

5

D D

L

@EMC@

@EMC@

PC_CLK0_EC

C_RST#

E

PC_RST#

L

S

YS_PWRGD_EC is OD-Pin

1 2

1 2

1263

@EMC@

1560

C
22P_0402_50 V8J

819 0.1U_0201_10V6K

C

C C

B B

R
10_0402_1%

1 2

EMC@

1 2

@

R

207 100K_0402_5%

1 2

C

1279 100P_0402_50V8J

4

+

3VLP

J

P2

112

JUMP_43X39

JP@

S

POK_5V85

K

BRST#10

S

ERIRQ10

L

PC_FRAME#10

L

PC_AD3_R1 0

L

PC_AD2_R1 0

L

PC_AD1_R1 0

L

PC_AD0_R1 0

L

PC_CLK0_EC1 0

L

PC_RST#1 0

E

C_RST#77

E

C_SCI#10

W

LAN_ON52

K

SI[0..7]63

K

SO[0..17]6 3

E

C_SMB_CK183,84

E

C_SMB_DA183,84

E

C_SMB_CK28,28,66

E

C_SMB_DA28,28,66

S

LP_S3#9

T

P_I2C_INT#63

C

HG_CTL37 1

T

P_3V_EN63

W

L_OFF#52

E

C_MUTE#56

U

SB_EN42,7 2,73

K

BL_EN63

F

AN_SPEED177

F

AN_SPEED277

E

C_TX52

E

C_RX52

S

YS_PWRGD_EC9

P

WR_SUSP_L ED#73

G

PU_PCC#28

P

BTN_OUT#9

S

LP_S5#9,84

2

+

EC_VCC

C

C

0.1U_0201_10V6K

0.1U_0201_10V6K
1256

1255

2

1

POK_5V

S

BRST#

K

S

ERIRQ

L

PC_FRAME#

PC_AD3_R

L

PC_AD2_R

L

PC_AD1_R

L

PC_AD0_R

L

L

PC_CLK0_EC

L

PC_RST#

E

C_RST#

E

C_SCI#

LAN_ON

W

K

SI0

K

SI1

K

SI2

K

SI3

K

SI4

K

SI5

K

SI6

K

SI7

K

SO0

K

SO1

K

SO2

K

SO3

K

SO4

K

SO5

K

SO6

K

SO7

K

SO8

K

SO9

K

SO10

K

SO11

K

SO12

K

SO13

K

SO14

K

SO15

SO16

K

SO17

K

E

C_SMB_CK1

E

C_SMB_DA1

E

C_SMB_CK2

E

C_SMB_DA2

S

LP_S3#

P_I2C_INT#

T

HG_CTL3

C

P_3V_EN

T

L_OFF#

W

C_MUTE#

E

SB_EN

U

BL_EN

K

F

AN_SPEED1

AN_SPEED2

F

E

C_TX

E

C_RX

YS_PWRGD_EC

S

P

WR_SUSP_L ED#

PU_PCC#

G

BTN_OUT#

P

LP_S5#

S

0.1U_0201_10V6K

C

C

0.1U_0201_10V6K

1258

1257

2

2

@

@

1

1

1

G

2

BRST#/GPIO01

K

3

ERIRQ

S

4

PC_FRAME#

L

5

PC_AD3

L

7

PC_AD2

L

8

PC_AD1

L

10

PC_AD0

L

12

LK_PCI_EC

C

13

CIRST#/GPIO05

P

37

C_RST#

E

20

C_SCI#/GPIO0E

E

38

LKRUN#/GPIO1D

C

55

SI0/GPIO30

K

56

SI1/GPIO31

K

57

SI2/GPIO32

K

58

SI3/GPIO33

K

59

SI4/GPIO34

K

60

SI5/GPIO35

K

61

SI6/GPIO36

K

62

SI7/GPIO37

K

39

SO0/GPIO20

K

40

SO1/GPIO21

K

41

SO2/GPIO22

K

42

SO3/GPIO23

K

43

SO4/GPIO24

K

44

SO5/GPIO25

K

45

SO6/GPIO26

K

46

SO7/GPIO27

K

47

SO8/GPIO28

K

48

SO9/GPIO29

K

49

SO10/GPIO2A

K

50

SO11/GPIO2B

K

51

SO12/GPIO2C

K

52

SO13/GPIO2D

K

53

SO14/GPIO2E

K

54

SO15/GPIO2F

K

81

SO16/GPIO48

K

82

SO17/GPIO49

K

77

C_SMB_CLK1/GPIO44

E

78

C_SMB_DAT1/GPIO45

E

79

C_SMB_CLK2/GPIO46

E

80

C_SMB_DAT2/GPIO47

E

6

M_SLP_S3#/GPIO04

P

14

G

15

G

16

G

17

G

18

G

19

C_PRESENT/GPIO0D

A

25

WM2/GPIO11

P

28

AN_SPEED1/GPIO14

F

29

ANFB1/GPIO15

F

30

C_TX/GPIO16

E

31

C_RX/GPIO17

E

32

CH_PWROK/GPIO18

P

34

USP_LED#/GPIO19

S

36

UM_LED#/GPIO1A

N

122

P

BTN_OUT#/GPIO5D

123

P

M_SLP_S4#/GPIO5E

44

U

KB9022QD_LQFP12 8_14X14

1000P_0402_50V7K

1000P_0402_50V7K

C
1261

1

2

2

1

ATEA20/GPIO00

PC & MISC

L

PIO07
PIO08
PIO0A
PIO0B
PIO0C

FBM-11-160808- 601-T_0603

C
1259

1

2

nt. K/B

I
Matrix

SM Bus

3

44

L

1 2

125

9

22

33

67

96

111

CC

CC

CC

CC

CC0

V

V

V

V

VCC

V

CC_LPC
V

PWM Output

PS2 Interface

A

C_VCCST_PG/GPIO0F

E

E

CIN1_BATT_TEMP/AD0/GPIO38

V

CIN1_BATT_DROP/AD1/GPIO39

V

AD Input

DA Output

N_DFAN1/DA1/GPIO3D

E

E

C_MUTE#/PSCLK1/GPIO4A
U

SB_EN#/PSDAT1/GPIO4B

V

SPI Device Interface

SPI Flash ROM

C_CIR_RX/AD6/GPIO40

E

YS_PWROK/AD7/GPIO41

S

B

ATT_CHG_LED#/GPIO52

GPIO

B

ATT_LOW_LED#/GPIO55

D

E

C_RSMRST#/GPXIOA03

V

CIN1_ADP_PROCHOT/GPXIOA05

V

COUT1_PROCHOT#/GPXIOA06

V

COUT0_MAIN_PWR_ON/GPXIOA07

GPIO

GPO

P

CH_PWR_EN/GPXIOA10

P

WR_VCCST_PG/GPXIOA11

V

CIN1_AC_IN/GPXIOD01

GPI

ND

ND

ND

ND

ND

GND

G

G

A

G

G

G

11

24

35

69

94

113

E

CAGND

+

EC_VCCA

2

C

1262

0.1U_0201_10 V6K

1

E

CAGND

EEP#/GPIO10

B

C_FAN_PWM/GPIO12

C_OFF/GPIO13

A

DP_I/AD2/GPIO3A

A
D_BID/AD3/GPIO3B

A

D4/GPIO42

A

D5/GPIO43

A

A0/GPIO3C

D

A2/GPIO3E

D

A3/GPIO3F

D

P

SCLK2/GPIO4C

P

SDAT2/GPIO4D

T

P_CLK/GPIO4E

T

P_DATA/GPIO4F

E

NKBL/GPXIOA00

W

OL_EN/GPXIOA01

M

E_EN/GPXIOA02

CIN0_PH1/GPXIOD00

M

ISO/GPIO5B

M

OSI/GPIO5C

S

PICLK/GPIO58

S

PICS#/GPIO5A

G

PIO50

C

APS_LED#/GPIO53

P

WR_LED#/GPIO54

S

YSON/GPIO56

V

R_ON/GPIO57

PWROK_EC/GPIO59

G

PXIOA04

B

KOFF#/GPXIOA08

G

PXIOA09

E

C_ON/GPXIOD02

O

N/OFF#/GPXIOD03

L

ID_SW#/GPXIOD04

S

USP#/GPXIOD05

G

PXIOD06

P

ECI/GPXIOD07

V

18R/VCC_IO2

L

43

FBM-11-160808- 601-T_0603

2

0mil

12

21
23
26
27

63
64
65
66
75
76

68
70
71
72

83
84
85
86
87
88

97
98
99
109

119
120
126
128

73
74
89
90
91
92
93
95
121
127

100
101
102
103
104
105
106
107
108

110
112
114
115
116
117
118

124

E

CAGND 83

AN_PWR_EN

L

E

C_BEEP#

AN_PWM1

F

AN_PWM2

F

B

ATT_TEMP

CIN1_BATT_DROP

V

A

DP_I

D_BID

A

RAM_TEMP

V

AN_WAKE#

L

S_EN

T

PU_THERMAL#

G

P_SENOFF#

T

POK_3V

S

YPEC_1P5A

T

YPEC_3A

T

C_SMB_CK3

E

C_SMB_DA3

E

T

P_CLK

T

P_DATA

HG_CTL1

C

PU_ACIN

G

0

.9VS_PWR_EN#

022_PH1

9

C_RTCRST

E

T_ON

B

P_PWR_EN

F

HG_EN

C

V

GATE

ATT_4S

B

B

ATT_BLUE_LED #

PU_ALERT#

G

P

WR_LED#

B

ATT_AMB_LED#

S

YSON

V

R_ON

0

.9_1.8VALW_PW REN

E

C_RSMRST#

HG_ILMSEL

C

022_VCIN

9

E

C_THERM

M

AINPWON

B

KOFF#

AN_GPO

L

V_EN_R_EC

3

HERMTRIP#

T

A

CIN

E

C_ON

O

N/OFFBTN#

L

ID_SW#

S

USP#

NBKL

E

HERMAL_ALERT#

T

L

AN_PWR_EN 51

E

C_BEEP# 56

F

AN_PWM1 77

F

AN_PWM2 77

B

ATT_TEMP 83,84

V

CIN1_BATT_DROP 83

A

DP_I 83,84

V

RAM_TEMP 83

L

AN_WAKE# 5 1

T

S_EN 38

G

PU_THERMAL# 28

T

P_SENOFF# 63
S

POK_3V 85

T

YPEC_1P5A 42,43

T

YPEC_3A 43

E

C_SMB_CK3 63

E

C_SMB_DA3 63

T

P_CLK 63

T

P_DATA 63

C

HG_CTL1 71

G

PU_ACIN 28

0

.9VS_PWR_EN# 7 8

9

022_PH1 83

B

T_ON 52

F

P_PWR_EN 66

C

HG_EN 7 1

V

GATE 88

B

ATT_4S 84

B

ATT_BLUE_LED # 73

G

PU_ALERT# 8 3

P

WR_LED# 73

B

ATT_AMB_LED# 73

S

YSON 86

V

R_ON 87,8 8

0

.9_1.8VALW_PW REN 87

E

C_RSMRST# 9

C

HG_ILMSEL 71

9

022_VCIN 83

M

AINPWON 77,85

B

KOFF# 38

L

AN_GPO 51

T

HERMTRIP# 8

A

CIN 84

E

C_ON 85

O

N/OFFBTN# 63

L

ID_SW# 6 6

S

USP# 37,78,84,86

E

NBKL 8

T

HERMAL_ALERT# 6 6

+

EC_VCC

2

B

oard ID / Rb

0

E

VT

1

P

VT

2

MP

Reserve TS_EN

New Add for GPU Thermal

New Add for PW I Limit

P

S2

Change for New Charger IC

Reserve for FP

Change for New Charger IC

Change for New Charger IC

1564

VT@

R

E

_0402_5%

0

SD028000080

1564

VT@

R

P

2K_0402_1%

1

SD034120280

1564

P@

R

M

5K_0402_1%

1

SD034150280

+

R

a

Rb

C_RTCRST

E

C_MUTE#

E

P_I2C_INT#

T

E

C_SMB_DA1

E

C_SMB_CK1

L

ID_SW#

+

5VALW

R

B79 4.7K_0402_5%

R

B80 4.7K_0402_5%

B

ATT_TEMP

A

CIN

C_RSMRST#

E

YSON

S

V_EN

3

C_THERM

E

M

3

AINPWON

V_EN_R_EC

1 2

3926 1K_0402_5 %

R

EC_VCC

12

1562

R
100K_0402_5 %

A

D_BID

12

1564

R
20K_0402_1%@

1

1563

R
10K_0402_5%

2

1565 10K_ 0402_5%@

R

116 1K_0402_5%@

R

R

1577 2.2K_ 0402_5%

1574 2.2K_ 0402_5%

R

344 47K_0402_5%

R

1 2
1 2

R

3907 47K_0402_ 5%@
1675 100K_0402 _5%@

R
R

940 1M_0402_5%

1 2

2012

D
RB751V-40_SOD32 3-2

1 2

2

1

+

RTC_APU_R

1

D

2

G

S

3

2

1

2

1

1 2

2

1
1 2

1 2

C

1265 100P _0402_50V8J

1 2

C

1266 100P _0402_50V8J

1 2

2

1

1 2

R

1690

0_0402_5%RS@

@

1

1269

C

0.1U_0201_10 V6K

@

91

Q
L2N7002W T1G_SC-70-3

B00001GE00

S

+

+

EC_VCC

C_SMB_CK3

E

C_SMB_DA3

E

A

PU_PROCHOT# 8,8 4,88

V_EN

3

3VS

3

V_EN 85

POK_3V

S

A A

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

2

2

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered Date

eciphered Date

eciphered Date

2

1 2

D

2013

RB751V-40_SOD32 3-2

1 2

2014

D
RB751V-40_SOD32 3-2

T

T

T

itle

itle

itle

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

ustom

ustom

ustom

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

Date: Sheet

Date: Sheet

Date: Sheet

C_RSMRST#

E

@

YS_PWRGD_EC

S

@

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

ompal Electronics, Inc.

E

E

E

C ENE-KB9022

C ENE-KB9022

C ENE-KB9022

1

1

1

1

A

A

A

o

o

o

f

58 99Wednesday, May 15, 2019

f

58 99Wednesday, May 15, 2019

f

58 99Wednesday, May 15, 2019

5

D D

C C

4

3

2

1

R

B B

A A

5

4

eserve Page

S

S

S

ecurity Classif ication

ecurity Classif ication

ecurity Classif ication

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

2

2

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

3

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered D ate

eciphered D ate

eciphered D ate

2

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

Reserve Page

Reserve Page

Reserve Page

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

o

o

o

f

59 99Wed nesday, May 15, 2019

f

59 99Wed nesday, May 15, 2019

f

59 99Wed nesday, May 15, 2019

1

1

1

1

A

A

A

5

D D

C C

4

3

2

1

R

B B

A A

5

4

eserve Page

S

S

S

ecurity Classif ication

ecurity Classif ication

ecurity Classif ication

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

2

2

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

3

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered D ate

eciphered D ate

eciphered D ate

2

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

Reserve Page

Reserve Page

Reserve Page

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

o

o

o

f

60 99Wed nesday, May 15, 2019

f

60 99Wed nesday, May 15, 2019

f

60 99Wed nesday, May 15, 2019

1

1

1

1

A

A

A

5

2

.2K

+

3VS

2

I2C2_SCL/EGPIO113/SCL0

D D

I2C2_SDA/EGPIO114/SDA0

P

icasso

SMB_0_SCL

S

MB_0_SDA

APU

A

PU_SIC

SIC

APU_SID

SID

.2K

1K

+

1

3VS

K

(

RC616,RC617)

R-short

4

E

C_SMB_CK2

EC_SMB_DA2

UM4
PCIE Clock Buffer

S

O-DIMM A & B

+

3VSDGPU

(

QV1)

2N7002KDW

3

V

GA_SMB_CK3

VGA_SMB_DA3

47K

4

2

+3VSDGPU

7K

A

MD

1

R18M-G1-90

T

HERMAL SENSOR

2.2K

2.2K

E

C_SMB_CK1

C C

EC_SMB_DA1

KB9022

E

C_SMB_CK2

EC_SMB_DA2

EC_SMB_CK3

EC_SMB_DA3

4

.7K

4

.7K

+

EC_VCC

1

00 ohm

100 ohm

(PR316,PR314)
R-short

+

5VALW

(QE62)
2N7002DW

+

5VS_BL

E

C_SMB_CK1-1

EC_SMB_DA1-1

EC_SMB_CK1-R

EC_SMB_DA1-R

E

C_SMB_CK3_LEDDRV

EC_SMB_DA3_LEDDRV

BATTERY

CONN

Charger

2

.2K

+

2

.2K

5VS_BL

LED driver

(RE1,RE2)
R-short

B B

A A

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONFI DENTIAL

HIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONFI DENTIAL

HIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONFI DENTIAL

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

5

4

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

3

2

2

2

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered Date

eciphered Date

eciphered Date

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

2

Date: Sheet

ompal Electronics, Inc.

SMBUS Diagram

SMBUS Diagram

SMBUS Diagram

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

1

1

1

1

A

A

A

o

o

o

f

61 99Wednesday, May 15, 2019

f

61 99Wednesday, May 15, 2019

f

61 99Wednesday, May 15, 2019

5

D D

C C

4

3

2

1

R

B B

A A

5

4

eserve Page

S

S

S

ecurity Classif ication

ecurity Classif ication

ecurity Classif ication

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

2

2

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

3

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered D ate

eciphered D ate

eciphered D ate

2

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

Reserve Page

Reserve Page

Reserve Page

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

o

o

o

f

62 99Wed nesday, May 15, 2019

f

62 99Wed nesday, May 15, 2019

f

62 99Wed nesday, May 15, 2019

1

1

1

1

A

A

A

ON/OFF BTN

R

534

+3VLP

ON/OFFBTN#5 8

Test Only

100K_0402_5 %

4

BOT

LED driver

E62B

Q

E

C_SMB_CK3

E

C_SMB_DA3

2N7002KDW _SOT363-6

2

E1 0_0402_5%RS@

R

E2 0_0402_5%RS@

R

EC_SMB_CK358

EC_SMB_DA358

set RE7 to 10k / output = 1.875mA

12

N/OFFBTN#

O

3

WK1

EVT@

S
NTC013-AA1J-A160T _4P

12

N10000CV00

S

+

5VS_BL

G

5

@

S

4

3

D

2

G

S

E62A

Q

2N7002KDW _SOT363-6

+

E

1
12

C_SMB_CK3_LE DDRV

E

C_SMB_DA3_LEDD RV

@

Raptor: NC for 59116F

+

5VS_BL

61

D

@

5VS_BL

12

1

E64

R
10K_0402_5%

2

R

2.2K_0402_5%

12

E69

@

E65

LED14P@

R

4.7K_0402_1%

A

D0

A

D1

A

D2

A

D3

TP/B Conn.

R

2.2K_0402_5%

12

E70

@

E

C_SMB_CK3_LE DDRV

E

C_SMB_DA3_LEDD RV

U

E4

24

R

ESET

25

CL

S

26

DA

S

31

A

0

32

A

1

1

A

2

2

A

3

12

N

.C.

13

N

.C.

28

N

.C.

29

N

.C.

30

N

.C.

7

G

ND

18

ND

G

TLC59116FIRHBR _VQFN32_5X5

LED14P@

G

S

P010020L00

V

cc

O

UT0

O

UT1

O

UT2

O

UT3

UT4

O

O

UT5

O

UT6

O

UT7

O

UT8

UT9

O

UT10

O

UT11

O

O

UT12

O

UT13

O

UT14

O

UT15

G

ND

ND

G

G

CONN@

27

K

B_A_LED_R_DRV#

3

K

B_A_LED_G_DRV#

4

K

B_A_LED_B_DRV#

5

K

B_B_LED_R_D RV#

6

K

B_B_LED_G_DR V#

8

K

B_B_LED_B_DR V#

9

K

B_C_LED_R_D RV#

10

K

B_C_LED_G_DR V#

11

K

B_C_LED_B_D RV#

14

K

B_D_LED_R_D RV#

15

K

B_D_LED_G_DR V#

16

K

B_D_LED_B_D RV#

17

19
20
21
22

23

33

JXT_FP202DH-00 8M10M

20mil 0.1A

+

J

TP1

1

1

P_CLK

T

2

2

P_DATA

T

3

3

4

4

2C_3_SDA_R

I

5

5

2C_3_SCL_R

I

6

6

P_I2C_INT#

T

7

7

P_SENOFF#

T

8

8

9

ND

10

ND

+

5VALW

change to @ at EVT only

+

5VS_BL

1

E3

C

0.1U_0201_10 V6K

2

TP_VCC

1 2

+

5VS

R

41 0_0603_5%

R

42 0_0603_5%LED14P@

KBL_EN58

LED14P@

663

C

0.1U_0201_10 V6K

@

TP_SENOFF# 58

1 2

KBLED@

1 2

4.7K_0402_5%

P_CLK

T

P_DATA

T

A

D0

A

D1

A

D2

A

D3

I

2C_3_SDA_R

I

+

3VALW

1U_0201_6.3V6M

C
2562

2

1

+

TP_VCC

12

1

2507

R

R

2509

4.7K_0402_5%

2

13

A000079400

U

S

SY6288C20AAC_SOT23 -5

5

N

I

O

G

4

N

E

Vih=1.5

TP_3V_EN 58

TP_CLK 5 8
TP_DATA 58

+

TP_VCC

1

UT

2

ND

3

C

O

4.7U_0402_6.3V6M

C

1

2563

2

2C_3_SCL_R

I

2C_3_SDA_R

I

2C_3_SCL_R

T

T

P_I2C_INT#

T

P_I2C_INT#_APU

P_I2C_INT#

S

1 2

2622 0_0402_5 %@

R

1

R

2623 0_0402_5 %@

KB Conn. / Backlight

+

2616

U

5

N

I

O

G

4

N

E

O

SY6288C20AAC_SOT23 -5

1

2

12

E75

R

4.7K_0402_1%

LED14P@

E74

R

4.7K_0402_1%

LED14P@

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5VS_BL

1

UT

2

ND

3

C

0.1U_0201_10V6K
C

32

1

@

2

12

1

E73

R

4.7K_0402_1%

LED14P@

R

E72

4.7K_0402_1%

LED14P@

2

C

C

C

ompal Secret Data

ompal Secret Data

2

2

2

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

ompal Secret Data

D

D

D

eciphered Date

eciphered Date

eciphered Date

+

5VS_BL

+

5VS_BL

B_A_LED_R_DRV#

K

B_A_LED_G_DRV#

K

B_A_LED_B_DRV#

K

B_B_LED_R_D RV#

K

B_B_LED_G_DR V#

K

B_B_LED_B_DR V#

K
K

B_C_LED_R_D RV#

K

B_C_LED_G_DR V#

K

B_C_LED_B_D RV#

K

B_D_LED_R_D RV#

K

B_D_LED_G_DR V#

K

B_D_LED_B_D RV#

1 2

812 2.2K_0402_5%

R

1 2

813 2.2K_0402_5%

R

1

814 2.2K_0402_5%

R

R

633 10K_0402_5%

1 2

22

D
RB751V-40_SOD32 3-2

+

TP_VCC

5

G

S

G

2

D

2509A

Q

2N7002KDW _SOT363-6

61

B00000EO00

S

D

2

K

SI[0..7]

K

SO[0..17]

J

BL1

1

1

2

2

3

3

4

4

5

G

ND

6

G

ND

ACES_51524-004 0N-001

CONN@

S

P010022M00

J

16
15

14
13
12
11
10

9
8
7
6
5
4
3
2
1

ACES_51522-014 01-P01

CONN@

S

+

TP_VCC

+

3VS

+

2

12

P_I2C_INT#_APU

T

Vgs=1.0-2.5V

Q

2509B

2N7002KDW _SOT363-6

S

B00000EO00

34

TP_VCC

TP_I2C_INT# 58

TP_I2C_INT#_APU 9

I2C_3_SCL 9

To APU

I2C_3_SDA 9

K

KSI[0..7] 58

KSO[0..17] 58

BL2

ND

G

ND

G

4

1

3

1

2

1

1

1

0

1
9
8
7
6
5
4
3
2
1

KB Conn.

KB BackLight

P01001R800

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

Title

itle

itle

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

ustom

ustom

ustom

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

K

K

K

B/TP

B/TP

B/TP

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

K

K
K
K
K
K
K

N/OFFBTN#

O

To EC

To APU

30
29
28

SO16

27

SO17

26

K

SO0

25

K

SO1

24

K

SO2

23

K

SO3

22

K

SO4

21

K

SO5

20

K

SO6

19

K

SO7

18

K

SO8

17

K

SO9

16

SO10

15

SO11

14

SO12

13

SO13

12

SO14

11

SO15

10

SI0

K

9

SI1

K

8

SI2

K

7

SI3

K

6

SI4

K

5

SI5

K

4

SI6

K

3

SI7

K

2
1

ACES_85201-280 5

S

P01000GO00

J

KB1

G

ND2

G

ND1

2

8

2

7

2

6

2

5

2

4

2

3

2

2

2

1

2

0

1

9

1

8

1

7

1

6

1

5

1

4

1

3

1

2

1

1

1

0
9
8
7
6
5
4
3
2
1

CONN@

1

1

1

A

A

A

o

o

o

f

63 99Wednesday, May 15, 2019

f

63 99Wednesday, May 15, 2019

f

63 99Wednesday, May 15, 2019

5

D D

C C

4

3

2

1

R

B B

A A

5

4

eserve Page

S

S

S

ecurity Classif ication

ecurity Classif ication

ecurity Classif ication

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

2

2

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

3

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered D ate

eciphered D ate

eciphered D ate

2

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

Reserve Page

Reserve Page

Reserve Page

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

o

o

o

f

64 99Wed nesday, May 15, 2019

f

64 99Wed nesday, May 15, 2019

f

64 99Wed nesday, May 15, 2019

1

1

1

1

A

A

A

5

D D

C C

4

3

2

1

R

B B

A A

5

4

eserve Page

S

S

S

ecurity Classif ication

ecurity Classif ication

ecurity Classif ication

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

2

2

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

3

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered D ate

eciphered D ate

eciphered D ate

2

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

Reserve Page

Reserve Page

Reserve Page

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

o

o

o

f

65 99Wed nesday, May 15, 2019

f

65 99Wed nesday, May 15, 2019

f

65 99Wed nesday, May 15, 2019

1

1

1

1

A

A

A

5

To Hall sensor/B

+

3VLP

J

HS1

1

L

L

D D

C C

ID_SW#58

+

3VLP

ID_SW#

L

ID_SW#

E

MC@

1 2

C

2754 0.1U_0201_10 V6K

E

MC@

1 2

C

2753 0.1U_0201_10 V6K

Close to JHS1
R

eserved for ESD require at 2019

1

2

2

3

3

4

4

5

G

ND

6

G

ND

ACES_51 524-0040N-001

CONN@

S

P010022M00

4

T

HERMAL SENSOR

Close to UF2

EMOTE1+

R

1

C

F21

TMS@

2200P_0 402_50V7K

2

EMOTE1-

R

EMOTE2+

R

1

C

F22

TMS@

2200P_0 402_50V7K

2

EMOTE2-

R

Place near UV1

R

C

E

3 1

EMOTE1+

2

Q

F1

B

MMBT390 4WH_SOT32 3-3

EMOTE1-

R

Place near UC1

EMOTE2+

2

B

E

R

Q

F2

MMBT390 4WH_SOT32 3-3

EMOTE2-

R

C

3 1

TMS@

TMS@

3

+

3VS

C

F20

TMS@

0.1U_020 1_10V6K

12

R

EMOTE1+

R

EMOTE1-

R

EMOTE2+

R

EMOTE2-

R

EMOTE1,2(+/-):

U

F2

1

V

CC

2

D

P1

3

D

N1

4

D

P2

5

D

N2

F75303M _MSOP10

TMS@

SMBUS ADDRESS
1001_101xb

A

LERT#

T

HERM#

2

R

F24

E

C_SMB_C K2 8,28,58

E

C_SMB_D A2 8,28,58

T

HERMAL_ALERT# 58

1

+

3VS

R

F2310K_040 2_5%

10K_040 2_5%

TMS@

T

HERMAL_ ALERT#

P

U +3VS with 1K at APU side

10

S

CL

9

S

DA

T

HERMAL_ ALERT#

8

T

H1_THER M#

7

6

G

ND

2

TMS@

1

+

3VS

12

Trace length: <8"

ETU801 FA577E-1200

IN

+

FP_VCC(5V) +FP_VCC(3V)

1

U

SBP

2

USBN

3

GND

4

NC

5

NC

6
7
8

D+
D­GND
NC
NC
NC
NC

Finger Print

P

ower Souce Check

P

EGIS ETU801 +FP_VCC=5V
ELAN SA464K-2200 +FP_VCC=3.3V

1 2

R

3VALW
5VALW

+

FP_VCC

K16 0_0603_5%F P@

1 2

R

K17 0_0603_5%@

2

F

6

5

4

FP@

C

K11

1U_0201 _6.3V6M

P_PWR_EN58

1

R

K19 0_0402_5%R S@

1 2

R

K18 0_0402_5%R S@

D

K2

@EMC@

I

V

I

AZC099-0 4S.R7G_SOT23-6

S

C300001G00

I

/O4

DD

/O3

/O2

G

ND

I

/O1

T

T

T

itle

itle

itle

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Date: Sheet

Date: Sheet

Date: Sheet

2

1

3

2

1

B B

A A

S

S

S

ecurity Classif ication

ecurity Classif ication

ecurity Classif ication

2

2

2

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

018/ 12/1 8 2019/12/18

3

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered D ate

eciphered D ate

eciphered D ate

+
+

U

K6

5

I

O

UT

N

G

4

SY6288C20 AAC_SOT23-5

2

H

UB_USB2 0_N3_L

H

UB_USB2 0_P3_L

C

C

C

Sensors/FP

Sensors/FP

Sensors/FP

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

ND

E

O

C

N

FP@

S

A000079400

H

UB_USB2 0_P3_L

H

UB_USB2 0_N3_L

ompal Electronics, Inc.

ompal Electronics, Inc.

ompal Electronics, Inc.

1

2

3

+

FP_VCC

+

1

FP_VCC

1

FP@

C

K12

4.7U_040 2_6.3V6M

2

J

FP1

8

8

7

10

G

7

2

6

9

G

6

1

5

5

4

4

3

3

2

2

1

1

ACES_51 522-00801-001

CONN@

S

P01001AE00

o

o

o

f

66 99Wed nesday, May 15, 2019

f

66 99Wed nesday, May 15, 2019

f

66 99Wed nesday, May 15, 2019

1

1

1

A

A

A

A

S

ATA Re-Driver and cable HDD Conn.

1 1

ATA_ATX_DRX_P0

S

ATA_ATX_DRX_P06

S

ATA_ATX_DRX_N06

S

ATA_ARX_DTX_N06

S

ATA_ARX_DTX_P06

+

3VS

2

1 2

R

O6 4.7K_0402_5%@

1 2

R

O15 4.7K_0402_5%@

1

R

O11 4.7K_0402_5%@

1

R

O18 4.7K_0402_5%

1

R

O12 4.7K_0402_5%@

1 2

O19 4.7K_0402_5%@

R

1 2

O8 4.7K_0402_5%@

R

1 2

O16 4.7K_0402_5%@

R

1 2

R

O10 4.7K_0402_5%@

1 2

R

O17 4.7K_0402_5%

1

R

O13 4.7K_0402_5%@

1 2

O20 4.7K_0402_5%

R

1 2

O14 4.7K_0402_5%@

R

S

ATA_ATX_DRX_N0

S

ATA_ARX_DTX_N0

S

ATA_ARX_DTX_P0

S

2

2

2

2

B

_DE

A

_DE

A

_EQ1

A

_EQ1

A

_EQ2

A

_EQ2

A

_DE

B

_DE

B

_EQ1

B

_EQ1

B

_EQ2

B

_EQ2

B

EW

D

2

1

C

O4 0.01U_0402_16V7K

12

O5 0.01U_0402_16V7K

C

12

O8 0.01U_0402_16V7K

C

2

1

C

O14 0.01U_0 402_16V7K

A

DE: M -3.5dB

A EQ: 9.4dB (ML)

B DE: M -3.5dB

B EQ: 7.4dB (LL)

C

ATA_ATX_C_RD_DRX_P0

S

ATA_ATX_C_RD_DRX_N0

S

ATA_ARX_C_RD_DTX_N0

S

ATA_ARX_C_RD_DTX_P0

S

+

3VS

C

O1

0.01U_0402_16V7K

2

1

1
2
3
4
5

21

R

O7

4.99K_0402_1%

1

O9

R

4.7K_0402_5%

+

3VS

20

19

DD2
V

A

_INP

A

_INN

G

ND1

B

_OUTN

B

_OUTP

G

ND2

EXT
R

6

7

12

2

@

12

C

O15

0.1U_0201_10V6K

@

D

EW

_EQ2B_EQ1A_EQ1
A

D

18

17

16

EW
D

_EQ1

_EQ2

_EQ1

A

A

B

A

_OUTP

A

_OUTN

B

_EQ2

B

_INN

B

_INP

N

_DE

_DE

DD1
V

E

B

A

8

9

10

0.1U_0201_10V6K

1

_DEA_DE
B

C
O10

2

ATA_ATX_RD_DRX_P0

S

15

ATA_ATX_RD_DRX_N0

S

14

_EQ2

B

13

ATA_ARX_RD_DTX_N0

S

12

ATA_ARX_RD_DTX_P0

S

11

U

O1

PS8527CTQFN20GTR2A_TQFN20_4X4

S

A00007JU10

+

3VS

E

F

+

5VS_HDD

1

C

10U_0402_6.3V6M

O12

12

ATA_ARX_RD_DTX_P0

S

ATA_ARX_RD_DTX_N0

S

ATA_ATX_RD_DRX_N0

S

ATA_ATX_RD_DRX_P0

S

00mils

1

2

C

O13

0.1U_0201_10V6K

@

C

O7 0.01U_0402_16V7K

C

O6 0.01U_0402_16V7K

C

O3 0.01U_0402_16V7K

C

O2 0.01U_0402_16V7K

G

F

FC Type

+

5VS

1 2

O4 0_0805_5%@

R

1 2

R

O25 0_0402_5%

12
12

2

1

2

1

+

+

5VS_HDD

5VS_HDD

HDD_P9

J

ATA_ARX_C_DTX_P0

S

ATA_ARX_C_DTX_N0

S

ATA_ATX_C_DRX_N0

S

ATA_ATX_C_DRX_P0

S

H

J

HDD1

14

G

ND

13

G

ND

12

1

2

11

1

1

10

1

0

9

9

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

ACES_51625-01201-001

CONN@

S

P010028W00

2

3 3

4 4

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

A

B

C

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

D

2

2

2

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

E

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered Date

eciphered Date

eciphered Date

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

ustom

ustom

ustom

Date: Sheet

Date: Sheet

F

Date: Sheet

G

ompal Electronics, Inc.

H

H

H

DD/SSD

DD/SSD

DD/SSD

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

1

1

1

A

A

A

o

o

o

f

67 99Wednesday, May 15, 2019

f

67 99Wednesday, May 15, 2019

f

67 99Wednesday, May 15, 2019

H

5

S

ATA SSD Conn.

4

3

2

1

+

+

3VS_SSD2

M

.2 SSD2

SSD2

J

1

ND

G

3

ND

G

5

ERn3

P

7

ERp3

P

9

ND

D D

ATA_ARX_C_DTX_P1

1 2

M7 0.01U_0402_16V7K

S

ATA_ARX_RD_DTX_P169

S

SATA SSD

C C

ATA_ARX_RD_DTX_N169

S

ATA_ATX_RD_DRX_N169

S

ATA_ATX_RD_DRX_P169

C

1 2

C

M8 0.01U_0402_16V7K

2

1

M9 0.01U_0402_16V7K

C

1 2

C

M10 0.01U_0402_16V7K

S

ATA_ARX_C_DTX_N1

S

ATA_ATX_C_DRX_N1

S

ATA_ATX_C_DRX_P1

S

210 @

T

SD2_DET#

S

M.2 SSD1

J

SSD1

1

G

ND

3

G

CIE_ARX_DTX_N3

P

CIE_ARX_DTX_N36

P

CIE_ARX_DTX_P36

P

CIE_ATX_C_DRX_N36

P

CIE_ATX_C_DRX_P36

P

CIE_ARX_DTX_N26

P

B B

P

CIE SSD

CIE_ARX_DTX_P26

P

CIE_ATX_C_DRX_N26

P

CIE_ATX_C_DRX_P26

P

CIE_ARX_DTX_N16

P

CIE_ARX_DTX_P16

P

CIE_ATX_C_DRX_N16

P

CIE_ATX_C_DRX_P16

P

CIE_ARX_DTX_N06

P

CIE_ARX_DTX_P06

P

CIE_ATX_C_DRX_N06

P

CIE_ATX_C_DRX_P06

C

LK_PCIE_N010

C

LK_PCIE_P010

P

CIE_ARX_DTX_P3

P

CIE_ATX_C_DRX_N3

P

CIE_ATX_C_DRX_P3

P

CIE_ARX_DTX_N2

P

CIE_ARX_DTX_P2

P

CIE_ATX_C_DRX_N2

P

CIE_ATX_C_DRX_P2

P

CIE_ARX_DTX_N1

P

CIE_ARX_DTX_P1

P

CIE_ATX_C_DRX_N1

P

CIE_ATX_C_DRX_P1

P

CIE_ARX_DTX_N0

P

CIE_ARX_DTX_P0

P

CIE_ATX_C_DRX_N0

P

CIE_ATX_C_DRX_P0

P

LK_PCIE_N0

C

LK_PCIE_P0

C

5
7

9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

53
55
57

ND

P

ERn3

P

ERp3

G

ND

P

ETn3

P

ETp3

G

ND

P

ERn2

P

ERp2

G

ND

P

ETn2

P

ETp2

G

ND

P

ERn1

P

ERp1

G

ND

P

ETn1

P

ETp1

G

ND

P

ERn0/SATA-B+

P

ERp0/SATA-B-

G

ND

P

ETn0/SATA-A-

P

ETp0/SATA-A+

G

ND

EFCLKN

R

EFCLKP

R

ND

G

G

11

P

13

P

15

G

17

P

19

P

21

G

23

P

25

P

27

G

29

P

31

P

33

G

35

P

37

P

39

G

41

P

43

P

45

G

47

P

49

P

51

G

53

R

55

R

57

G

67

N

69

P

71

G

73

G

75

G

LOTES_APCI0079-P005A

CONN@

P07001EZ00

S

3

P3VAUX

3

P3VAUX

N

C

N

C

D

AS/DSS#

3

P3VAUX

3

P3VAUX

3

P3VAUX

3

P3VAUX

N

C

N

C

N

C

N

C

N

C

N

C

N

C

N

C

N

C

D

EVSLP

N

C

N

C

N

C

N

C

N

C

P

ERST#

C

LKREQ#

EWake#

P

C

N

C

N

ETn3
ETp3
ND
ERn2
ERp2
ND
ETn2
ETp2
ND
ERn1
ERp1
ND
ETn1
ETp1
ND
ERn0/SATA-B+
ERp0/SATA-B­ND
ETn0/SATA-A­ETp0/SATA-A+
ND
EFCLKN
EFCLKP
ND

C
EDET(NC-PCIE/GND-SATA)
ND
ND
ND

+

3VS_SSD1+3VS_SSD1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

54
56
58

SD1_PCIE_RST#

S

LKREQ_PCIE#0_R

C

USCLK(32kHz)

S

1

M18
C

2

P3VAUX

3

P3VAUX

3

AS/DSS#

D

P3VAUX

3

P3VAUX

3

P3VAUX

3

P3VAUX

3

D

P
LKREQ#

C

EWake#

P

P3VAUX

3

P3VAUX

3

P3VAUX

3

22U_0603_6.3V6M

EVSLP

ERST#

G
G

R

2
4
6

C

N

8

C

N

10
12
14
16
18
20

C

N

22

C

N

24

C

N

26

C

N

28

C

N

30

C

N

32

C

N

34

C

N

36

C

N

38
40

C

N

42

C

N

44

C

N

46

C

N

48

C

N

50
52
54
56

C

N

58

C

N

68
70
72
74

76

ND1

77

ND2

1

M20
C

2

0.1U_0201_10V6K

M17 100P_0402_50V8J@EMC@

C

1

M27 0_0402_5%RS@

1

+

2

1

3VS_SSD2

1

O26 0_0805_5%@

R

1

1

M13

M14
C

2

L

ON:If system didn't support DEVSLP, set Device Sleep Signal high and

keep (from power on), device will ignore.

EVSLP1_R

D

USCLK_SSD2

S

M59

C
150U_D2_6.3VY_R15M

SGA00003700

2

2

C

2

0.1U_0201_10V6K

22U_0603_6.3V6M

1 2

R

M21 0_0402_5%

1 2

M20 0_0402_5%@

R

4962@

T

S

A00000OH00

MC74VHC1G08DFT2G_SC70-5

S

SD1_PCIE_RST#

R

100K_0402_5%

1 2

P

lace close to JSSD pin 50

ESD request to reserve.

C

LKREQ_PCIE#0 10

M135

@

+

3VS

2

1

+

C

M58

150U_D2_6.3VY_R15M

SGA00003700

2

@

D

EVSLP1 9

+

3VALW

U

M5

5

@

1

P

I

N1

4

O

1

PU_PCIE_RST#

A

2

I

N2

G

3

R

M28

2

0_0402_5%

A

GPIO40 9

A

PU_PCIE_RST# 9,27,51,52

USCLK_SSD1

67

C

N

69

EDET(NC-PCIE/GND-SATA)

P

71

ND

G

73

ND

G

75

ND

G

A A

5

LOTES_APCI0079-P005A

CONN@

S

P07001EZ00

4

USCLK(32kHz)

S

P3VAUX

3

P3VAUX

3

P3VAUX

3

ND1

G

ND2

G

S

68
70
72
74

76
77

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

I

I

I

ssued Date

ssued Date

ssued Date

T

4961@

C

C

C

ompal Secret Data

ompal Secret Data

2

2

2

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

3

ompal Secret Data

D

D

D

eciphered Date

eciphered Date

eciphered Date

2

T

T

T

itle

itle

itle

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

ompal Electronics, Inc.

M.2 SSD

M.2 SSD

M.2 SSD

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

1

1

1

1

A

A

A

o

o

o

f

68 99Wednesday, May 15, 2019

f

68 99Wednesday, May 15, 2019

f

68 99Wednesday, May 15, 2019

5

S

ATA Re-Driver for M.2 Connector

D D

S

ATA_ATX _DRX_P16

S

ATA_ATX _DRX_N16

S

ATA_ARX _DTX_N16

S

ATA_ARX _DTX_P16

+

3VS

A

1 2

R

M126 4.7 K_0402_5%@

1 2

R

M120 4.7 K_0402_5%@

1 2

R

M129 4.7 K_0402_5%@

R

M123 4.7 K_0402_5%

R

M130 4.7 K_0402_5%@

R

C C

M124 4.7 K_0402_5%@

R

M127 4.7 K_0402_5%@

R

M121 4.7 K_0402_5%@

R

M128 4.7 K_0402_5%@

R

M122 4.7 K_0402_5%@

R

M131 4.7 K_0402_5%@

R

M125 4.7 K_0402_5%

R

M132 4.7 K_0402_5%@

1

1 2
1 2

1
1 2

1 2
1 2

1 2
1 2

1 2

2

2

A

A
A

A
A

B
B

B
B

B
B

D

2_DE
2_DE

2_EQ1
2_EQ1

2_EQ2
2_EQ2

2_DE
2_DE

2_EQ1
2_EQ1

2_EQ2
2_EQ2

EW2

A

DE: M -3.5dB

A EQ: 9.4dB (ML)

B DE: M -3.5dB

B EQ: 2.4dB (LM)

ATA_ATX _DRX_P1

S

ATA_ATX _DRX_N1

S

ATA_ARX _DTX_N1

S

ATA_ARX _DTX_P1

S

4

ATA_ATX _C_RD_DRX_P1

12

C

M73 0.01U_0 402_16V7K

12

C

M74 0.01U_0 402_16V7K

12

C

M75 0.01U_0 402_16V7K

12

C

M76 0.01U_0 402_16V7K

S

ATA_ATX _C_RD_DRX_N1

S

S

ATA_ARX _C_RD_DTX_N1

S

ATA_ARX _C_RD_DTX_P1

3

+

3VS

C

M72

0.01U_02 01_6.3V7K

21

R

M133

4.99K_04 02_1%

1 2

4.7K_040 2_5%
R

M134

2

+

3VS

12

1

A

_INP

2

A

_INN

3

G

ND1

4

B

_OUTN

5

B

_OUTP

G

ND2

12

@

1

C

M78

0.1U_020 1_10V6K

@

20

6

2_EQ1A2_EQ1
B

19

DD2
V

EXT
R

7

2

EW2

2_EQ2
A

D

18

17

16

EW
D

_EQ1

_EQ2

_EQ1

B

A

A

A

_OUTP

A

_OUTN

B

_EQ2

B

_INN

B

_INP

N

_DE

_DE

DD1

E

B

A

V

8

9

10

0.1U_0201_10V6K

1

2_DEA2_DE
B

C
M77

2

ATA_ATX _RD_DRX_P1

S

15

ATA_ATX _RD_DRX_N1

S

14

2_EQ2

B

13

ATA_ARX _RD_DTX_N1

S

12

ATA_ARX _RD_DTX_P1

S

11

U

M4

PS8527C TQFN20GTR2A_ TQFN20_4X4

S

A00007JU10

+

3VS

S

ATA_ATX _RD_DRX_P1 68

S

ATA_ATX _RD_DRX_N1 68

S

ATA_ARX _RD_DTX_N1 68

S

ATA_ARX _RD_DTX_P1 68

1

B B

A A

S

S

S

ecurity Classif ication

ecurity Classif ication

ecurity Classif ication

2

2

2

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

018/ 12/1 8 2019/12/18

3

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered D ate

eciphered D ate

eciphered D ate

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Date: Sheet

Date: Sheet

2

Date: Sheet

ompal Electronics, Inc.

M.2 SATA Redriver

M.2 SATA Redriver

M.2 SATA Redriver

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

1

1

1

A

A

A

o

o

o

f

69 99Wed nesday, May 15, 2019

f

69 99Wed nesday, May 15, 2019

f

69 99Wed nesday, May 15, 2019

1

5

D D

C C

4

3

2

1

R

B B

A A

5

4

eserve Page

S

S

S

ecurity Classif ication

ecurity Classif ication

ecurity Classif ication

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

2

2

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

3

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered D ate

eciphered D ate

eciphered D ate

2

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

Reserve Page

Reserve Page

Reserve Page

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

o

o

o

f

70 99Wed nesday, May 15, 2019

f

70 99Wed nesday, May 15, 2019

f

70 99Wed nesday, May 15, 2019

1

1

1

1

A

A

A

A

B

C

D

E

USB3.0

D

S1

SB3_ATX _C_DRX_P1

1 2

C

U

SB3_ATX _DRX_P110

U

SB3_ATX _DRX_N110

U

1 1

2 2

SB3_ARX _DTX_P110

U

SB3_ARX _DTX_N110

U

SB20_P110

U

SB20_N110

S2 0 .22U_0402_16V 7K

2

1

C

S3 0 .22U_0402_16V 7K

2

1

C

S131 0.3 3U_0402_10V6 K

1 2

C

S132 0.3 3U_0402_10V6 K

1 2

R

S138 15_0402 _1%

1 2

C

S135 470P_04 02_50V8J

2

1

C

S136 470P_04 02_50V8J

1 2

R

S139 15_0402 _1%

U

SB3_ATX _C_DRX_N1

U

SB3_ARX _C_DTX_P1

U

SB3_ARX _C_DTX_N1

U

SB20_P1 _RC

U

SB20_N1 _RC

U

1 2

R

S86 0_0402_ 5%RS@

1 2

R

S89 0_0402_ 5%RS@

1

R

S90 0_0402_ 5%RS@

1 2

R

S91 0_0402_ 5%RS@

HR_USB2 0_P1

C

HR_USB2 0_N1

C

2

2

3

SB3_ATX _L_DRX_P1

U

SB3_ATX _L_DRX_N1

U

SB3_ARX _L_DTX_P1

U

SB3_ARX _L_DTX_N1

U

L

S3

EMC@

2

3

DLM0NSN 900HY2D_4P

S

M070005U00

1

4

C

1

C

4

HR_USB2 0_P1_R

HR_USB2 0_N1_R

SB3_ATX _L_DRX_P1

U

SB3_ATX _L_DRX_N1

U

SB3_ARX _L_DTX_P1

U

SB3_ARX _L_DTX_N1

U

+

USB3_VC CA

HR_USB2 0_P1_R

C

EMC@

1

2

4

5

3

TVW DF1004AD0_DF N9

S

C300003Z00

D

S2

6

I

/O4

5

V

DD

4

I

/O3

AZC099-0 4S.R7G_SOT23-6

S

C300001G00

EMC@

U

9

U

8

U

7

U

6

I

/O2

G

ND

I

/O1

SB3_ATX _L_DRX_P1

SB3_ATX _L_DRX_N1

SB3_ARX _L_DTX_P1

SB3_ARX _L_DTX_N1

HR_USB2 0_N1_R

C

3

2

1

S5

C

150U_D2 _6.3VY_R15M

SGA0000 3700

W

=100mils

1

2

+

1

2

HR_USB2 0_N1_R

C

HR_USB2 0_P1_R

C

SB3_ARX _L_DTX_N1

U

SB3_ARX _L_DTX_P1

U

SB3_ATX _L_DRX_N1

U

SB3_ATX _L_DRX_P1

U

+

USB3_VC CA

C

S6

EMC@

0.1U_020 1_10V6K

U

SB3.0 Conn.

J

USB1

1

V

BUS

2

D

-

3

D

+

4

G

ND

5

S

tdA-SSRX-

6
7
8
9

ACON_TA RAC-9V1391

CONN@

D

S

tdA-SSRX+

G

ND-DRAIN

S

tdA-SSTX-

S

tdA-SSTX+

C23300AG00

G

ND

G

ND

G

ND

G

ND

10
11
12
13

+

5VALW

3 3

U

SB Host Charger

+

5VALW

HG_CTL2

101

C

HG_ILMSEL

C

SDP1-OFF

SDP1

DCP
Auto

CDP

Setting

ILIM_H

ILIM_H

ILIM_H

Note

Port power off

Data Lines Connected

Data Lines Disconnected

Data Lines Connected

B

S

S

S

ecurity Classif ication

ecurity Classif ication

ecurity Classif ication

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1 2

R

S14 10K_040 2_5%

1 2

R

S15 10K_040 2_5%@

U

SB Host Charger Truth Table

4 4

CHG_EN

0

1

1

1

C

CTL1

TL2 CTL3 ILIM_SEL MODE Current Limit

0 1 10 ILIM_H

0

0 1 1 1

1 111

A

22U_0603_6.3V6M

1

@

2

2

2

2

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

C

0.1U_0201_10V6K

1

2

U
U

C

HG_EN5 8

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

C
S7

SB20_N1 _RC
SB20_P1 _RC

C

C

D

D

D

eciphered D ate

eciphered D ate

eciphered D ate

HG_ILMSEL

HG_CTL2

U

S12

1

V

IN

2

D

M_OUT

3

D

P_OUT

13

F

AULT#

4

I

LIM_SEL

5

E

N

6

C

TL1

7

C

TL2

8

C

TL3

SLGC555 44CVTR_TQFN1 6_3X3

C
S9

C

HG_ILMSEL58

C

HG_CTL158

C

HG_CTL358

T

hermal Pad

D

V

D

D

M_IN

I

LIM_L

I

LIM_HI

OUT

P_IN

G

+

USB3_VC CA

12

HR_USB2 0_P1

C

10

HR_USB2 0_N1

C

11

15
16

9

N

C

14

ND

17

1

22.1K_0402_1%
R

S12

2

T

T

Title

itle

itle

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

C

C

C

ustom

ustom

ustom

Date: Sheet

Date: Sheet

Date: Sheet

12

39K_0402_1%

R
S13

I

LM R vaule

@

Ios(mA)=50250/R(Kohm)
ILIM_Hi=2273mA
ILIM_L=1288mA(reserve)

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

ompal Electronics, Inc.

U

U

U

SB3.0 Conn/USB Charger

SB3.0 Conn/USB Charger

SB3.0 Conn/USB Charger

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

E

1

1

1

A

A

A

o

o

o

f

71 99Wed nesday, May 15, 2019

f

71 99Wed nesday, May 15, 2019

f

71 99Wed nesday, May 15, 2019

5

4

3

2

1

USB3.0

+

F

D D

U

SB3_ATX_DRX_P210

U

SB3_ATX_DRX_N210

U

SB3_ARX_DTX_P210

U

SB3_ARX_DTX_N210

2

1

C

S109 0.22U_0402_16V7K

2

1

C

S108 0.22U_0402_16V7K

2

1

C

S133 0.33U_0402_10V6K

1 2

C

S134 0.33U_0402_10V6K

SB3_ATX_C_DRX_P2

U

SB3_ATX_C_DRX_N2

U

SB3_ARX_C_DTX_P2

U

SB3_ARX_C_DTX_N2

U

1 2

R

S124 0_0402_5%RS@

1 2

R

S123 0_0402_5%RS@

1 2

R

S126 0_0402_5%RS@

1 2

R

S125 0_0402_5%RS@

U

SB3_ATX_L_DRX_P2

U

SB3_ATX_L_DRX_N2

U

SB3_ARX_L_DTX_P2

U

SB3_ARX_L_DTX_N2

U

SB3_ATX_L_DRX_P2

U

SB3_ATX_L_DRX_N2

U

SB3_ARX_L_DTX_P2

U

SB3_ARX_L_DTX_N2

or ESD request

D

S20

EMC@

1

2

4

5

3

TVWDF1004AD0_DFN 9

SC300003Z00

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SB3_ATX_L_DRX_P2

9

U

SB3_ATX_L_DRX_N2

8

U

SB3_ARX_L_DTX_P2

7

U

SB3_ARX_L_DTX_N2

6

U

SB_EN42,58,73

5VALW

C

S107

EMC@

0.1U_0201_10V6K

1 2

U

S13

5

I

N

4

E

N

SY6288C20AAC_SOT23-5

W=100mils

1

+

C

S111

150U_D2_6.3VY_R15M

SGA00003700

D

S21

2DN2_L

1 2

R

C C

U

SB20_P210

U

SB20_N210

S142 15_0402_1%

1 2

C

S139 470P_0402_5 0V8J

1 2

C

S140 470P_0402_5 0V8J

R

S143 15_0402_1%

2

1

SB20_P2_RC

U

SB20_N2_RC

U

SB20_N2_RC

U

SB20_P2_RC

U

L

S13

EMC@

3

3

2

2

DLM0NSN900HY2D_4P

SM070005U00

2DN2_L

U

4

4

2DP2_L

U

1

1

U

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EMC@

6

5

4

AZC099-04S.R7G_SOT23-6

S

I

/O4

V

DD

I

/O3

C300001G00

I

/O2

G

ND

I

/O1

3

2

2DP2_L

U

1

2

U

SB3_ARX_L_DTX_N2

U

SB3_ARX_L_DTX_P2

U

SB3_ATX_L_DRX_N2

U

SB3_ATX_L_DRX_P2

1

O

UT

2

G

ND

3

O

C

+

USB3_VCCB

2

C

S110

EMC@

0.1U_0201_10V6K

1

U

2DN2_L

U

2DP2_L

+

USB3_VCCB

W

=60mils

USB3.0 Conn.

J

USB2

1

V

BUS

2

D

-

3

D

+

4

G

ND

5

S

tdA-SSRX-

6

S

tdA-SSRX+

7

G

ND-DRAIN

8

S

tdA-SSTX-

9

S

tdA-SSTX+

ACON_TARAC-9V1391

CONN@

D

C23300AG00

10

G

ND

11

G

ND

12

G

ND

13

G

ND

B B

A A

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2

2

2

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered Date

eciphered Date

eciphered Date

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

2

Date: Sheet

ompal Electronics, Inc.

USB3.0 Conn

USB3.0 Conn

USB3.0 Conn

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

1

1

1

1

A

A

A

o

o

o

f

72 99Wednesday, May 15, 2019

f

72 99Wednesday, May 15, 2019

f

72 99Wednesday, May 15, 2019

A

B

C

D

E

IO/B CONN

J

IO2

26

G

ND2

25

G

H

H

POUT_L_ 156

H

POUT_R_ 156

S

1 1

1 2

R

S140 15_0402 _1%

1 2

C

U

SB20_P410

U

SB20_N410

2 2

S137 470P_04 02_50V8J

1 2

C

S138 470P_04 02_50V8J

1 2

R

S141 15_0402 _1%

U

SB20_P4 _RC

U

SB20_N4 _RC

L

S12

EMC@

DLM0NSN 900HY2D_4P

1

1

4

4

S

M070005U00

U

SB20_P4 _L

2

2

U

SB20_N4 _L

3

3

LEEVE56

R

ING256

H

P_PLUG#56

G

NDA

S

PKR+56

S

PKR-56

B

ATT_AMB _LED#58

B

ATT_BLU E_LED#5 8

P

WR_ SUSP_LED#58

P

WR_ LED#5 8

+

5VALW

U

SB_EN42,58,72

POUT_L_ 1

H

POUT_R_ 1

S

LEEVE

R

ING2

H

P_PLUG#

B

ATT_AMB_LED#

B

ATT_BLUE_LED#

P

WR_SUSP_L ED#

P

WR_ LED#

U

SB_EN

U

SB20_P4 _L

U

SB20_N4 _L

ND1

24

2

4

23

2

3

22

2

2

21

2

1

20

2

0

19

1

9

18

1

8

17

1

7

16

1

6

15

1

5

14

1

4

13

1

3

12

1

2

11

1

1

10

1

0

9

9

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

CVILU_CF3 5242D0RD-NH

CONN@

3 3

4 4

S

S

S

ecurity Classif ication

ecurity Classif ication

ecurity Classif ication

2

2

2

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

018/ 12/1 8 2019/12/18

C

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered D ate

eciphered D ate

eciphered D ate

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Date: Sheet

Date: Sheet

D

Date: Sheet

ompal Electronics, Inc.

IO/B Interface

IO/B Interface

IO/B Interface

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

1

1

1

A

A

A

o

o

o

f

73 99Wed nesday, May 15, 2019

f

73 99Wed nesday, May 15, 2019

f

73 99Wed nesday, May 15, 2019

E

5

D D

C C

4

3

2

1

R

B B

A A

5

4

eserve Page

S

S

S

ecurity Classif ication

ecurity Classif ication

ecurity Classif ication

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

2

2

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

3

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered D ate

eciphered D ate

eciphered D ate

2

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

Reserve Page

Reserve Page

Reserve Page

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

o

o

o

f

74 99Wed nesday, May 15, 2019

f

74 99Wed nesday, May 15, 2019

f

74 99Wed nesday, May 15, 2019

1

1

1

1

A

A

A

5

D D

C C

4

3

2

1

R

B B

A A

5

4

eserve Page

S

S

S

ecurity Classif ication

ecurity Classif ication

ecurity Classif ication

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

2

2

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

3

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered D ate

eciphered D ate

eciphered D ate

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Date: Sheet

Date: Sheet

2

Date: Sheet

ompal Electronics, Inc.

Reserve Page

Reserve Page

Reserve Page

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

1

1

1

A

A

A

o

o

o

f

75 99Wed nesday, May 15, 2019

f

75 99Wed nesday, May 15, 2019

f

75 99Wed nesday, May 15, 2019

1

5

D D

C C

4

3

2

1

R

B B

A A

5

4

eserve Page

S

S

S

ecurity Classif ication

ecurity Classif ication

ecurity Classif ication

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

2

2

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

3

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered D ate

eciphered D ate

eciphered D ate

2

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

Reserve Page

Reserve Page

Reserve Page

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

o

o

o

f

76 99Wed nesday, May 15, 2019

f

76 99Wed nesday, May 15, 2019

f

76 99Wed nesday, May 15, 2019

1

1

1

1

A

A

A

FAN Conn

Screw Hole

Stand Off

1000P_0 402_50V7K

FAN_SPE ED158

FAN_SPE ED258

+5VS

C

F6

@

+3VS

+3VS

1

1

2

2

@

1

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F3

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1

C

F7
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1

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+

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@

+

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@

1

2

+

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F

40mil

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1

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1

1

2

2

3

3

4

4

5

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1

6

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1

2

2

3

3

4

4

5

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1

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H

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3

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1

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8

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@

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1

6

1

11

1

14

1

Reset Circuit

BI_GATE PH to +RTCVCC at PWR
side

B

BI_GATE83

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H

@

H_3P0

H

@

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H

5

1

9

1

Q

1B

5

G

H

@

H_2P5N

+3VLP

1 2

34

D

2N7002K DW_SOT36 3-6

S

17

1

R

25

10K_040 2_5%

B

I_GATE#

1

C

40

0.1U_020 1_10V6K

2

H

20

@

H_3P0X2 P5N

1

Q

1A

2

G

R

23 0_04 02_5%

R

24 0_04 02_5%

6

D

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S

1

18

@

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1

1

@

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H

@

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2

19

1

B

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F

D1

@

1

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F

D3

@

1

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MAINPWON 58,85

EC_RST# 58

Reset Button

@

S

W3

1

3 4

SKRPABE 010_4P

S

N10000CV00

F

D2

@

1

FIDUCIAL_C40 M80

F

D4

@

1

FIDUCIAL_C40 M80

B

I_GATE

2

change PN to SN10000CV00

S

S

Security Class ification

ecurity Classif ication

ecurity Classif ication

2

2

2

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

I

I

Issued Date

ssued Date

ssued Date

T

T

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

018/ 12/1 8 2019/12/18

C

C

Compal Secret Data

ompal Secret Data

ompal Secret Data

D

D

Deciphered Date

eciphered D ate

eciphered D ate

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

Title

itle

itle

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

C

C

C

ustom

ustom

ustom

Date: Sheet of

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

F

F

F

AN & Screw Hole

AN & Screw Hole

AN & Screw Hole

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

o

o

77 99Wed nesday, May 15, 2019

f

77 99Wed nesday, May 15, 2019

f

77 99Wed nesday, May 15, 2019

1

1

1

A

A

A

A

B

C

D

E

(VBIAS=5V),IMAX (per channel)=6A,R ds=18mohm

C

2750

@

12

0.1U_020 1_10V6K

2

1

R

S

USP#37 ,58,84,86

1 1

1667 0 _0402_5%RS@

VS_ON

3

+

3VALW

+

5VALW

1 2

C

12

1U_0201 _6.3V6M

U2

1

V

IN1

2

V

IN1

3

O

N1

4

V

BIAS

5

O

N2

6

V

IN2

7

V

IN2

E

M5209VF _DFN14_3X2

S

A00007PM00

V
V

V
V

OUT1
OUT1

G

OUT2
OUT2

G

C

C

PAD

3VS_LS

+

14
13

12

T1

11

ND

10

T2

9
8

15

1 2

C

10

560P_04 02_50V7K

J

JUMP_43 X118

+

JP@

3VS

1

C

13

0.1U_020 1_10V6K

2

7

+5VALW TO +5VS
+

3VALW TO +3VS_SSD1

+

3VALW

+3VALW TO +3VS

C

M33

1U_0201 _6.3V6M

+

5VALW

+

5VALW

1 2

3V_NGFF _GATE

+

1 2

C

11

1U_0201 _6.3V6M

C

M32

@

12

0.1U_020 1_10V6K

2

USP#

S

2 2

1

R

M53 0_0402_ 5%R S@

USP#

S

1

R

1668 0_ 0402_5%RS@

2

(VBIAS=5V),IMAX (per channel)=6A,R ds=18mohm

VS_ON

5

U3

1

V

IN1

2

V

IN1

3

O

N1

4

V

BIAS

5

O

N2

6

V

IN2

7

V

IN2

E

M5209VF _DFN14_3X2

S

A00007PM00

V
V

V
V

OUT1
OUT1

G

OUT2
OUT2

G

C

C

PAD

T1

ND

T2

14
13

12

C

M38

11

1000P_0 402_50V7K

10

9
8

15

3VS_SSD _1

+

1 2

1 2

C

9

330P_04 02_50V7K

5VS_LS

+

J

10

JP@

JUMP_43 X118

J

8

JP@

JUMP_43 X118

2

C

0.1U_020 1_10V6K

1

+

5VS

1

C

0.1U_020 1_10V6K

2

M35

14

+

3VS_SSD 1

SB00001IY00

S

8
7

1

6
5

2

.9VS_GAT E

0

2

13

D

2

G

S

TR EMB04N03G 1N SOP-8

U

4

EMB04N0 3G 1N SOIC8

Q

84

L2N7002 WT1G_SC-70 -3

S

B00001GE00

1
2
3

4

1

C

16

0.1U_020 1_10V6K

2

+

0.9VS

1U_0201_6.3V6M

1

2

B

160mils(4.0A)

C
46

1

2

@

S

S

S

ecurity Classif ication

ecurity Classif ication

ecurity Classif ication

2

2

2

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

018/ 12/1 8 2019/12/18

C

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered D ate

eciphered D ate

eciphered D ate

D

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

C

C

C

ustom

ustom

ustom

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

D

D

D

C INTERFACE

C INTERFACE

C INTERFACE

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

E

o

o

o

f

78 99Wed nesday, May 15, 2019

f

78 99Wed nesday, May 15, 2019

f

78 99Wed nesday, May 15, 2019

1

1

1

A

A

A

C

4.7U_0402_6.3V6M
939

+

0.9VALW

C

940

4.7U_040 2_6.3V6M

3 3

+

5VALW

1

R

1674

4.7K_040 2_5%

0

.9VS_PW R_EN#58

4 4

A

5

D D

C C

4

3

2

1

R

B B

A A

5

4

eserve Page

S

S

S

ecurity Classif ication

ecurity Classif ication

ecurity Classif ication

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

2

2

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

3

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered D ate

eciphered D ate

eciphered D ate

2

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

Reserve Page

Reserve Page

Reserve Page

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

o

o

o

f

79 99Wed nesday, May 15, 2019

f

79 99Wed nesday, May 15, 2019

f

79 99Wed nesday, May 15, 2019

1

1

1

1

A

A

A

5

D D

C C

4

3

2

1

R

B B

A A

5

4

eserve Page

S

S

S

ecurity Classif ication

ecurity Classif ication

ecurity Classif ication

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

2

2

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

3

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered D ate

eciphered D ate

eciphered D ate

2

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

Reserve Page

Reserve Page

Reserve Page

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

o

o

o

f

80 99Wed nesday, May 15, 2019

f

80 99Wed nesday, May 15, 2019

f

80 99Wed nesday, May 15, 2019

1

1

1

1

A

A

A

5

D D

C C

4

3

2

1

R

B B

A A

5

4

eserve Page

S

S

S

ecurity Classif ication

ecurity Classif ication

ecurity Classif ication

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

2

2

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

3

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered D ate

eciphered D ate

eciphered D ate

2

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

Reserve Page

Reserve Page

Reserve Page

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

o

o

o

f

81 99Wed nesday, May 15, 2019

f

81 99Wed nesday, May 15, 2019

f

81 99Wed nesday, May 15, 2019

1

1

1

1

A

A

A

A

B

C

D

1 1

+

@

ACES_50299-00601-001

1

1

2

2

3

3

4

4

P

G

7

G

8

JP101

5

5

6

6

7
8

2 2

3 3

19V_ADPIN

4.7_1206_5%

1 2

EMI@

0.1U_0603_25V7K

1 2

+

19V_ADPIN

P

R102

P

C103

12

P

C101

100P_0402_50V8J

EMI@

P

EMI@

NA_2P

1 2

P

L102

EMI@

NA_2P

1 2

L101

+

19V_VIN

P

C102

EMI@

1000P_0402_50V7K

P

R103

12

4.7_1206_5%

1 2

EMI@

0.1U_0603_25V7K

1 2

P

C104

P

R101

@

0_0603_5%

+

3VLP

4 4

A

1 2

+

CHGRTC

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

2

2

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered Date

eciphered Date

eciphered Date

C

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

ustom

ustom

ustom

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

D

D

D

CIN

CIN

CIN

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

D

o

o

o

f

82 99Wednesday, May 15, 2019

f

82 99Wednesday, May 15, 2019

f

82 99Wednesday, May 15, 2019

1

1

1

A

A

A

A

P

R201 100_0402_1%

1 2

P

R202 100_0402_1%

1 2

P

R203

200K_0402_1%

@

P

JP201

1

1

1 1

CVILU_CI9908M2HR0-NH

2 2

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

G

ND

10

G

ND

C_SMB_DA1-1

E

C_SMB_CK1-1

E

ATT_TS

B

ATT_B/I

B

P

C201

EMI@

1000P_0402_50V7K

+

17.4V_BATT+

12

1 2

1 2

P

R204 1K_0402_1%

P

L201

EMI@

NA_2P

2

1

P

L202

EMI@

NA_2P

1 2

C203

EMI@

P

1000P_0402_50V7K

+

3VLP

B

ATT_TEMP 58,84

+

RTCVCC

1

P

R208

100K_0402_5%

B

I_GATE77

12

+

17.4V_BATT

2

2

G

B

E

C_SMB_DA1 58,84

E

C_SMB_CK1 58,84

13

D

P

Q201

LBSS139LT1G_SOT23-3

S

1

P

R212

0_0402_5%

2

C

+

3VLP

VGA@

1

P

C202

0.1U_0603_25V7K

VGA@

100K_0402_1%

PU_ALERT#

F

or KB9022

OTP

G

G

PU_ALERT#58

12

P

R207

2

VGA@

P

1

V

CC

2

G

3

O

4

O

G718TM1U_SOT23-8

R

ecoveryActive

10K_0402_1%

U201

MSNS1

T

HYST1

R

ND

MSNS2

T

T1

R

HYST2

T2

1

@

P

R205

2

8

7

6

5

VGA@

47K_0402_1%

1

2

12

12

P

R209

F

or KB9012

sense 20mΩ

VGA@

10K_0402_1%

100K_0402_1%_NCP15WF104F0 3RC

P

R206

VGA@

P

H201

D

R

ecoveryActive

9

2C, 1V 56C, 2.VVCIN0_PH(V)

PH202(ohm) 7.3092K 26.11K

SR 45W

BR 65W

58.5W, 0.61V

8

4.5W, 0.61V

58.5W, 0.61V

84.5W, 0.61V

PH202 under CPU botten side :
CPU thermal protection at 96 degree C ( shutdown )
R

ecovery at 56 degree C

R

2013/10/02

3 3

4 4

Add for ENE9022 Battery Voltage drop detection.
Connect to ENE9022 pin64 AD1.

R

eserve for 2-cell design

+

19VB_5V

12

Metapod@

P

R213

750K_0402_1%

Metapod@

P

R214

0_0402_5%

2

1

Metapod@

P

C204

0.1U_0402_25V6

1 2

12

Metapod@

P

R216

150K_0402_1%

A

ecovery at 56 degree C

V

RAM_TEMP58

V

CIN1_BATT_DROP 58

+

EC_VCCA

12

P

R218

VGA@

16.5K_0402_1%

1

P

H203

VGA@

100K_0402_1%_B25/50 4250K

B

value:4250K±1%

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

2

9

022_PH158

100K_0402_1%_B25/50 4250K

B

value:4250K±1%

C

C

C

ompal Secret Data

ompal Secret Data

2

2

2

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

ompal Secret Data

D

D

D

eciphered Date

eciphered Date

eciphered Date

C

P

H202

+

EC_VCCA

1

2

12

1

2

E

CAGND

R210

P

16.9K_0402_1%

@

T

1

@

T

2

R217
P

@

0_0402_5%

A

DP_I 58,84

1

P

R211

10K_0402_1%

2

9

022_VCIN 58

1

P

R215

10K_0402_1%

2

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

Title

itle

itle

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

ustom

ustom

ustom

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

B

B

B

ATTERY CONN / OTP

ATTERY CONN / OTP

ATTERY CONN / OTP

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

D

83 99Wednesday, May 15, 2019

83 99Wednesday, May 15, 2019

83 99Wednesday, May 15, 2019

1

1

1

A

A

A

o

o

o

f

f

f

5

P

rotection for reverse input

V

gs = 20V
Vds = 60V
Id = 250mA

D D

Need check the SOA for inrush

+

19V_VIN

Range:2V~3.5V
20*49.9/(392+49.9)=2.55V

0x3CH <BIT9> PSYS current gain
Rs1 = 10mΩ and Rs2 = 5mΩ or Rs1 = 10mΩ and Rs2 = 10mΩ
BIT0 = 1.14uA/W
BIT1 = 0.285uA/W
=========================================================
Rs1 = 20mΩ and Rs2 = 10mΩ or Rs1 = 20mΩ and Rs2 = 20mΩ
BIT0 = 2.28uA/W
BIT1 = 0.57uA/W

C C



Ipsys = KPSYS x ( VADP x IADP + VBAT x IBAT )
R

_Psys = 1.2V / Ipsys
KPSYS = 1.14uA/W
adapter wattage = 45W
Battery wattage = 40Wh
Ipsys = 1.14 x (45+40) = 96.9uA
R_Psys = 1.2V / 96.9uA = 12.3K-ohm.
=====================================
adapter wattage = 65W
Battery wattage = 40Wh
Ipsys = 1.14 x (65+40) = 119.7uA
R_Psys = 1.2V / 96.9uA = 10K-ohm.

**Design Notes* *
For 45W/65W /90 W system, 2S/3S/4 S battery
Maximum Chargin g current 3.5A
Maximum Battery discharge power 55W
#Register Setti ng

1. 0X3DH bit10 set 0 (default 1) to enable turbo b oost function

2. Disable turb o when AC only
#Circuit Design

1. ACLIM and CC LIM are devider v oltage control.

2. Use 7X7 chok e and 3X3 H/L sid e MOSFET
Charge current 3A
Power loss : 1. 79W (H/S=0.227W,L /S=1.2738W,Choke=0 .297W)
Power density : 0.61 (23X16)
#Protect functi on

1. ACOVP : VCC voltage > 24V

2. SMBus timeou t : 0X3DH bit15 s et 0 (default 0) t o enable 175s(defa ult).

3. ACOC : OX3CH bit4 set1 releas e adapter limit fu nction (default:E nable).

4. CHGOCP : bas ed on charge curr ent setting

5. BATOVP : 4.6 V/Cell

6. BATLOWV : No .

7. TSHUT : 150C

B B

B

attery current limimed by CCLIm ~ 3.89A.
Adapter current limimed by ACLIm ~ 4.33A.
(PR779 and PQ741 are for change ACLIm when AC in)

(

Rs1 = 10mΩ and Rs2 = 5mΩ or Rs1 = 20mΩ and Rs2 = 10mΩ).
CC_LIM = VccLIM / 64 x Rs2
=============================================================
(Rs1 = 10mΩ and Rs2 = 10mΩ or Rs1 = 20mΩ and Rs2 = 20mΩ).
CC_LIM = VccLIM / 32 x Rs2
=============================================================
AC_LIM = Vac_LIM / 32 x Rs1

A A

 

F

or 4S per cell 4.35V battery

B

ATT_4S58

S

USP#37,58,78,86

100K_0402_1%

1

P

R340

2

2

G

1

D

S

3

5

A

CIN58

2

Q308

P
L2N7002WT1G_SC70-3

A

CIN_CHG

12

2

1

13

DD_CHG
V

12

R311
P

100K_0402_1%

12

R313
P

158K_0402_1%

R339

P

2M_0402_1%

P

R341

@

0_0402_5%

Q307

P
LTC015EUBFS8TL_UMT3F

1 2

R301

P

1M_0402_1%

E

C_SMB_DA158,83

E

C_SMB_CK158,83

A

PU_PROCHOT#8,58,88

1

3M_0402_5%

P

EMP21N03HC_EDFN5X6-8-5

5

12

R306

P
499K_0402_1%

1

R310
P

2

64.9K_0402_1%

A

DP_I58,83

P

0.1U_0402_25V6

Close to EC.

A

CIN

L2N7002WT1G_SC70-3

65W@

80.6K_0402_1%

45W@

57.6K_0402_1%

R302

P

Q310

4

12

C316

@

Q316

P

2

G

R336

P

P

R336

4

1

D

2

P

Q301

L2N7002WT1G_SC70-3

G

S

3

2

+

19V_P1

1
2
3

C322

@

P

2

1

1000P_0402_25V

12

12

R308 4.02K_0402_1%

R307 4.02K_0402_1%

P

P

C301
P

2200P_0402_50V7K

support Turbo boost : 2200P
no support Turbo boost : 0.1u

P

R314 0_0402_5%@

1 2

P

R316 0_0402_5%@

1 2

R317 0_0402_5%@

P

1 2

1 2

P

R318 1K_0402_1%

1

P

R321 1K_0402_1%

C

lose to EC.

1

1

C317

P

0.1U_0402_25V6

2

2

V

DD=5V

1

R328
P

2

200K_0402_1%

@

R331

P

76.8K_0402_1%

2

1

1

D

S

3

12

R336
P

232K_0402_1%

135W@

Hybrid boost power mode
Cell = 4s

ICClimit : 7.73A
Delta I : 1.44A
1C charge current :6.48A

4

V

DD_CHG

R329
P

O

CCP setting

R337
P

@

AON7380_DFN3X3-8-5

1
2
3

4

0.033U_0402_25V7K

2

@

0_0402_5%

12

200K_0402_1%

1

100K_0402_1%

2

Q311

P

A

P

P

C

MSRC_CHG

A

SGATE_CHG

A

CIN_CHG

E

C_SMB_DA1-R

E

C_SMB_CK1-R

MON_ISL95520

R322

3

max Power loss 0.22W for 90W;0.1 2W for 65W system; 0.05W for 45W
CSR rating: 1W
VCSIP-VCSIN spe c < 81mV

M

󱌳󳑱󱙱

U

B1.0

MA (ISN Chock

MB1.B ISN Chock

R303

P

+

19V_P2

0.005_1206_1%

1

5

2

SIP_CHG_R
C

1

R304

P

1_0402_5%

2

P

C306

0.1U_0402_25V6

C

CLIM_CHG

A

CLIM_CHG

P

ROG_CHG

R335
P

4 cell@

12

P

U301

1

A

CIN

2

A

COK

3

S

DA

4

S

CL

5

P

ROCHOT#

6

A

MON

7

B

MON

8

N

C

GND
A

33

C

12

150K_0402_1%

1 2

SIN_CHGCSIP_CHG
C

31

32

SIP

SIN

C

C

ISL88739AHRZ-T_QFN32_4X4

OMP

ROG

C

P

9

10

OMP_CHG

1

R332
P

2

1

C320

2

P

@

560P_0402_50V7K

30

SGATE
A

CLIM
C

11

100_0402_1%

C321
P

C323

1

2

1

2

EMI@

FBMA-L11-201209-800LMA50T

4

3

Isat: 10A
DCR: 14mohm
6 VIA

SIN_CHG_R
C

1

R305
P

2_0402_5%

2

C324

@

P

1

0.1U_0402_25V6

2

1

C307 0.22U_0603_25V7K

2

P

PCP_CHGOPCN_CHG

BAT_CHGBGATE_CHG
V

O

28

25

26

27

29

BAT

PCP

PCN

V

GATE

Q

O

MSRC

B

C

B

OOT

U

GATE

P

HASE

L

GATE

V

DDP

V

DD

D

CIN

N

TC

SON

SOP

ATGONE

CLIM

SET

C

A

F

B

C

12

13

14

15

16

1

P

R325

SET_CHG
F

10K_0402_1%

2

C

SOP_CHG

PR333=0 ohm, Fs=500KHZ ~ +/- 15%

C

SON_CHG

12

R333

P
0_0402_5%

@

0.015U_0402_25V7K

A

PU_PROCHOT#

2

1 2

24

23

22

21

20

19

18

17

1

3

A

CIN

󴿍󲯛󲒂

󲒂

b

󱌳󰵓

D

ead

IS

P

L302

P

R309

100_0402_1%

2

1

P

R312

@

0_0603_5%

B

ST_CHG

2

1

U

G_CHG

L

X_CHG

L

G_CHG

V

DDP_CHG

V

DD_CHG

1

2

R323

P

1

100K_0402_1%

P

R324
10_1206_5%

1

2

2

VF = 0.38V

1

C318
P

1U_0603_25V6

B

ATT_TEMP 58,83

BATGONE(BATT_TEMP)
logic high: above 2.4V
logic low: under 0.8V

+

3VS

1

10K_0402_1%

2

P

Q314

@

RUM001L02_VMT3

@

34

D

2N7002KDW_SOT363-6

5

G

S

3

b

ead)

+

19VB_CHG

EMI@

1

1

@EMI@

1

1

C304

C303

C305

C302

2

P

2

10U_0805_25V6K

+

P

D302

1

RB751V-40_SOD323-2

C309

P

0.47U_0603_16V7K

B

ST_CHG_R

1

1 2

R319 4.7_0402_5%

P

P

C313

1U_0402_16V6K

2

1

S SCH DIO BAS40CW SOT-323

P

R330

2_0402_5%

1 2

C319

P

1

0.1U_0402_25V6

@

2

0_0402_5%

1 2

P

R343

@

2

G

P

Q315B

S

S

S

T

T

T
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORI ZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORI ZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORI ZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR D ISCLOSED TO ANY THIRD PA RTY WITHOUT PRIOR WRITTEN CONSENT OF COMPA L ELECTRONICS, INC.

MAY BE USED BY OR D ISCLOSED TO ANY THIRD PA RTY WITHOUT PRIOR WRITTEN CONSENT OF COMPA L ELECTRONICS, INC.

MAY BE USED BY OR D ISCLOSED TO ANY THIRD PA RTY WITHOUT PRIOR WRITTEN CONSENT OF COMPA L ELECTRONICS, INC.

2

P

P

P

2

10U_0805_25V6K

2200P_0402_25V7K

0.1U_0402_25V7K

17.4V_BATT

V

DDP_CHG

2

2

1

2

3

2

D301

P

P

R334

1

@

10K_0402_1%

2

@

61

D

2N7002KDW_SOT363-6

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIE TARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAIN S CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIE TARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAIN S CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIE TARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAIN S CONFIDENTIAL

4

4

C314

P

2.2U_0402_16V6K

+

P

R342

P

Q315A

19V_VIN

C

SOP_CHG_R

C

SON_CHG_R

Q305

P

5

123

P

Q306

5

123

A

2

2

2

2

M

odule model inf ormation

I

SL95520_Hybrid_Boost_V2.mdd

+

19VB

P

Q312

AON7380_DFN3X3-8-5

1
2
3

5

4

1 2

P

@

C308

0.1U_0402_25V7K

C

hoke 4.7uH SH00 000YC00
(Common Part)
(Size:6.6 x 7.3 x 3 mm)
(DCR:28m~33m)

ON7506_DFN33-8-5
A

L301

P

4.7UH_PCMB063T-4R7MS_8A_20%

1

R320
P

2

EMI@

1

C315

ON7506_DFN33-8-5

P

A

2

EMI@

R326

P
0_0603_5%

1 2

P

R327

@

0_0603_5%

1 2

PU_PROCHOT#_D 28

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

4.7_1206_5%

680P_0402_50V7K

1

+

B

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

+

17.4V_BATT_CHG

2

17.4V_BATT

A

R315

P

0.01_1206_1%

134

2

1

Support max cha rge 3.5A
Power loss: 0.2 45W
CSR rating: 1W
VCSPP-VCSON spe c < 81mV

+

17.4V_BATT

1

12

12

C311

C312

C310

P

P

P

2

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

P

Q309

@

LMUN5113T1G_SOT323-3

2

1

S

LP_S5#9,58

2

P

Q313

@

LTC015EUBFS8TL_UMT3F

T

T

T

itle

itle

itle

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheetof

Date: Sheetof

Date: Sheetof

1 3

A
B

3

B

A

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

ompal Electronics, Inc.

PWR_CHARGER

PWR_CHARGER

PWR_CHARGER

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

1

1

1

1

84 99Wednesday, May 15, 2019

84 99Wednesday, May 15, 2019

84 99Wednesday, May 15, 2019

A

A

A

A

1 1

C

heck pull up resistor of SPOK at HW side

+

19VB

L401

EMI@

P

HCB2012KF-121T50_0805

1 2

S

POK_3V58

C431
P

EMI@

1

2

0.1U_0402_25V6

1

C403
P

2

0.1U_0402_25V6

@EMI@

+

P

R406

100K_0402_5%

3VALWP

B

E

N1 and EN2 dont't floating

P

U401

X_3V

L

10

NLDO_3V5V

E

6

7

8

9

SY8288BRAC_QFN20_3X3

4

5

N

I

L

X

G

ND

G

ND

P

G

N

C

N2
E

12

11

19VB_3V

+

1

12

C404
P

2

C405
P

2200P_0402_50V7K

EMI@

10U_0805_25V6K

12

3

V_EN58

N

I

N1
E

ST_3V

B

2

1

3

S

N

N

I

I

B

L

X

L

X

G

ND

L

DO

N

C

UT

C

F

G

ND

N

F

O

13

14

15

3.3V LDO 150mA~300mA

P

C402

1000P_0402_25V8J

V_FB

3

1

R401

@

P

0_0603_5%

1 2

20

19

18

17

1

16

21

2

C411

P

4.7U_0402_6.3V6M

2

P

R403

1K_0402_5%

1 2

+

3VLP

C

C401

P

0.1U_0603_25V7K

2

1

X_3V

L

1

R405
P

@EMI@

2

V_SN
3

1

2

C412
P

@EMI@

NLDO_3V5V

E

L402

P

1 2

2.2UH_9A_20%_7X7X3_M

4.7_1206_5%

680P_0402_50V7K

P

R402

499K_0402_1%

1 2

12

R404
P

150K_0402_1%

Choke 2.2uH SH00000YV00 (Common Part)
(Size:7.3 x 6.6 x 3 mm)
(DCR:14m~16m)

1

12

2

C407
P

22U_0603_6.3V6M

Vout is 3.234V~3.366V
I

peak=4.65A
Imax=3.25A
Iocp=10A

C408
P

+

22U_0603_6.3V6M

D

19VB

12

E

+

3VALWP

12

12

C409
P

22U_0603_6.3V6M

1

2

C410
P

22U_0603_6.3V6M

C430

C429
P

P

@

@

22U_0603_6.3V6M

22U_0603_6.3V6M

2 2

3 3

E

M

AINPWON58,77

+

19VB

S

POK_5V58

C_ON58

L403

EMI@

P

HCB2012KF-121T50_0805

1 2

100K_0402_5%

2.2K_0402_5%

1 2

P

R411

@

0_0402_5%

1 2

+

19VB_5V

19VB_5V

+

1

C432
P

2

EMI@

0.1U_0402_25V6

+

3VLP

12

P

R413

P

R410

12

R412
P

1M_0402_1%

1

12

C414
P

10U_0805_25V6K

V_EN

5

1

C428
P

2

4.7U_0402_6.3V6M

12

C415

C416

P

P

2

10U_0805_25V6K

2200P_0402_50V7K

EMI@

X_5V

L

1

C417
P

2

0.1U_0402_25V6

@EMI@

NLDO_3V5V

E

5

V_EN

6

X

L

7

ND

G

8

ND

G

9

G

P

10

C

N

U402

P
SY8288CRAC_QFN20_3X3

2

1

3

4

5

11

N

N

N

N

I

I

I

I

UT

N1

N2

F
F

O

E

E

12

13

14

15

1

2

1000P_0402_25V8J

V_FB

5

B

S
B

20

X

L

19

X

L

18

ND

G

17

CC

V

16

C

N

21

DO

ND

G

L

5

P

C427

4.7U_0402_6.3V6M

C413

P

1 2

R408

@

P

0_0603_5%

ST_5V

V LDO 150mA~300mA

1

X_5V

L

C419

P

1 2

4.7U_0402_6.3V6M

V

L

P

R407

1K_0402_5%

1 2

2

P

C418

0.1U_0603_25V7K

2

1

C

hoke 1.5uH SH000016700 (Common Part)
(Size:7.3 x 6.6 x 3 mm)
(DCR:14m~15m)

1.5UH_9A_20%_7X7X3_M

12

R409
P

@EMI@

V_SN
5

1

2

C426
P

@EMI@

L404

P

2

1

4.7_1206_5%

680P_0402_50V7K

12

12

12

C420
P

22U_0603_6.3V6M

C422

C421

P

P

22U_0603_6.3V6M

12

12

C423
P

22U_0603_6.3V6M

22U_0603_6.3V6M

Vout is 4.998V~5.202V
I

peak=9A
Imax=6.6A
Iocp=10A

+

3VALWP

+

5VALWP

+

5VALWP

12

C425

C424
P

P

@

@

22U_0603_6.3V6M

22U_0603_6.3V6M

P

J401

@

2

1

1

JUMP_43X118

P

J402

@

112

JUMP_43X118

2

2

+

3VALW

+

5VALW

4 4

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2

2

2

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered Date

eciphered Date

eciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

T

T

T

itle

itle

itle

3.3VALWP/5VALWP

3.3VALWP/5VALWP

3.3VALWP/5VALWP

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

ustom

ustom

ustom

FH50P M/B LA-H901P

FH50P M/B LA-H901P

FH50P M/B LA-H901P

Date: Sheet

Date: Sheet

D

Date: Sheet

85 99Wednesday, May 15, 2019

85 99Wednesday, May 15, 2019

85 99Wednesday, May 15, 2019

E

1

1

1

A

A

A

o

o

o

f

f

f

5

P

J504

12

@

1

1

JUMP_43X39

YSON

C512
P

P

J505

1

2

22U_0603_6.3V6M

2

@

1

1

JUMP_43X79

12

C513
P

22U_0603_6.3V6M

2

P

R515

@

0_0402_5%

1

2

2

1

2

C515

C514
P

P

22U_0603_6.3V6M

P

C521

4.7U_0402_6.3V6M

2

12

C520
P

@

0.1U_0402_16V7K

1

12

C525
P

2

EMI@

0.1U_0402_25V6

1UH_6.6A_20%_5X5X3_M

1

12

C516
P

22U_0603_6.3V6M

22U_0603_6.3V6M

IN_2.5VVIN_2.5V

V

12

N_2.5V

E

1

2

+

12

C501
P

0.1U_0402_25V6

@EMI@

P

L503

2

@EMI@

4.7_1206_5%

@EMI@

680P_0402_50V7K

H/S AON7408 Rds(on) :typ:27mOhm, max:34mOhm
Idsm(TA=25)=7.5A, Idsm(TA=70)=5.5A

L/S AON7506 Rds(on) :typ:13mOhm, max:15.8mOhm
Idsm(TA=25)=12A, Idsm(TA=70)=10.5A

Choke: 5x5x3
Rdc=13mohm(Typ), 14mohm(Max)

Switching Frequency: 530kHz
Ipeak=9.5A
Iocp~11.4A
OVP: 110%~120%

+

R511

P

1M_0402_5%

D D

+

1.2VP

C C

+

19VB

1

2

C511
P

22U_0603_6.3V6M

M

ode Level +0.6VSP VTTREF_1.2V
S5 L off off
S3 L off on
S0 H on on

Note: S3 - sleep ; S5 - power off

B B

A A

+

3VALW

S

19VB_1.2V

C502
P

2200P_0402_50V7K

EMI@

R503

P

C517

P

5VALW

4
3
2
1

4

12

C503
P

10U_0805_25V6K

1

2
12

1

P

C524

1U_0201_6.3V6M

2

DD

V

IN

V

N

E

GOOD

P

3

P

R501

2.2_0603_5%

ST_1.2V_R

1

2

C504
P

10U_0805_25V6K

5

4

Q501
P

AON7408L_DFN8-5

123

5

Q502
P

9661MF11U_SO8PU502

G

5

C

N

6

OUT

V

7

DJ

A

8

ND

ND

G

G

9

4

AON7506_DFN3X3-8-5

123

D

ue to buyer command.
PC508,PC510 need change to SE00000QL10.
Because 0603 change to 0402, PVT need change footprint.

21.5K_0402_1%

10K_0402_1%

P

F

P

R512

B_2.5V

R513

C505
P

+

5VALW

1

Rup

2

1

2

12

0.1U_0603_25V7K

1U_0402_10V6K

1

2

Rdown

V

B

R504

P

5.1_0603_5%

1 2

C510

P

2

1

12

C522
P

C523
P

0.01U_0402_25V7K

out=0.8V* (1+(21.5/10)) = 2.52V 0.8%

P

24.9K_0402_1%

1 2

P

@

RB751V-40_SOD323-2

S

+

2.5VP

22U_0603_6.3V6M

1 2

L

R502

C

P

C508

1U_0402_10V6K

1 2

DD_1.2V

V

2

D501

+

5VALW

19VB_1.2V

+

YSON58

S

USP#37,58,78,84

G_1.2V

S_1.2V

1

15

14

13

12

11

2

R505

P

2.2_0603_5%

1

P
470K_0402_1%

1 2

0_0402_5%

1

ST_1.2V

B

G_1.2V

U

X_1.2V

L

16

P

U501

HASE
P

L

GATE

P

GND

C

S

RT8207PGQW_WQFN20_3X 3

V

DDP

V

DD

GOOD
P

10

R507

P

R509

@

0_0402_5%

2

1

C518

@

P

0.1U_0402_10V7K

P

R510

@

2

17

GATE
U

ON
T

9

ON_1.2V
T

18

8

N_1.2V
E

1

2

OOT
B

5
S

2

20

19

LDOIN
V

V

V

V

3
S

6

7

N_0.6VSP
E

12

@

P

0.1U_0402_10V7K

TT
V

P

TTGND

TTSNS

G

TTREF

V

DDQ

B
F

B_1.2V
F

C519

+

0.6VSP

AD

ND

+

+

1.2VP

2.5VP

21

1

2

3

4

5

TTREF_1.2V

V

6.19K_0402_1%

1

P

R508

10K_0402_1%

2

R506

P

1 2

+

1.2VP

12

+

1.2VP

0

.75*(1+6.19/10)=1.21

P

J501

@

112

JUMP_43X118

J502

@

P

112

JUMP_43X39

P

@

1

1

JUMP_43X39

C506
P

J503

10U_0603_6.3V6M

2

0
TDC 0.7A
Peak Current 1A

1

2

C507
P

10U_0603_6.3V6M

1

P

C509

0.033U_0402_16V7K

2

+

1.2VP

2

2

2

1

.6Volt +/- 5%

+

0.6VSP

+

1.2V

+

0.6VS

+

2.5V

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

2

2

2

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

3

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered Date

eciphered Date

eciphered Date

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

ustom

ustom

ustom

Date: Sheet

Date: Sheet

2

Date: Sheet

ompal Electronics, Inc.

1

1

1

.2VP/0.6VSP/2.5VP

.2VP/0.6VSP/2.5VP

.2VP/0.6VSP/2.5VP

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

1

1

1

A

A

A

o

o

o

f

86 99Wednesday, May 15, 2019

f

86 99Wednesday, May 15, 2019

f

86 99Wednesday, May 15, 2019

1

5

4

3

2

1

D D

EN pin don't floating
If have pull down resistor at HW side, pls delete PR2

+

LDO_VDDP

12

R604

@

P

0_0402_5%

LMT_VDDP

I

1

R605

@

P

0_0402_5%

2

C C

B B

+

3VALW

19VB

0

.9_1.8VALW_PWREN58

J602

@

P

N_1.8VALW

I

2

112

JUMP_43X79

22U_0603_6.3V6M

Note:
When design Vin =5V, please stuff snubber
to prevent Vin damage

12

P

C617

J604

@

P

2

1

2

1

JUMP_43X79

@

P
0_0402_5%

1

FB=0.6V
Note:Iload(max) =3.5A

F

B=0.6V

N

ote:Iload(max)=3A

R601

2

P

R607

1M_0402_1%

P

U602

1

F

B

2

P

G

3

I

N

4

P

GND

SY8003ADFC_DFN8_2X2

C623
P

EMI@

0.1U_0402_25V6

12

P

GND

S

GND

E

N

L

X

N

C

12

12

12

C604

P
C601
P

0.1U_0402_25V6

@EMI@

EMI@

2200P_0402_50V7K

12

P

C614

@

0.22U_0402_10V6K

9
8

7

X_1.8VALW

L

6

5

19VB_VDDP

+

12

C605

C622
P

P

10U_0805_25V6K

@

1UH_2.8A_30%_4X4X2_F

12

R613
P

@EMI@

1

C621
P

2

@EMI@

U601

P

2

N

I

LMT_VDDP

I

1

2

12

P

R612

1M_0402_5%

12

1

2

3

N

I

4

N

I

5

N

I

7

ND

G

8

ND

G

18

ND

G

11

N

E

13

LMT

I

15

YP

B

SY8288RAC_QFN20_3X3

P

C615

1U_0201_6.3V6M

0_0402_5%

1 2

Note:Iload(max) =2.5A

12

C618

Rup

P

68P_0402_50V8J

Rdown

12

10U_0805_25V6K

+

3VALW

12

C616
P

0.1U_0402_16V7K

P

L603

1 2

P

20K_0402_1%

4.7_0603_5%

B_1.8VALW

F

P

10K_0402_1%

680P_0402_50V7K

R614

R615

Vout=0.6V* (1+R up/Rdown)

9

G

P

1

S

B

6

X

L

19

X

L

20

X

L

14

B

F

17

CC

V

10

C

N

12

C

N

16

C

N

21

AD

P

ST_VDDP

B

X_VDDP

L

B_VDDP

F

DO_VDDP

L

P

R603

@

0_0603_5%

1 2

12

P

2.2U_0402_6.3V6M

C612

P

C602

0.1U_0603_25V7K

1 2

F

B = 0.6V

R602

@EMI@

P

4.7_1206_5%

S

2

1

P

L602

1UH_6.6A_20%_5X5X3_M

1 2

NB_VDDP

(R2)

R611

P

@

1

2

C619
P

22U_0603_6.3V6M

1

2

C620
P

22U_0603_6.3V6M

0

.9_1.8VALW_PWREN 58,87

+

1.8VALWP

+

1.8VALWP

P

J603

@

112

JUMP_43X79

@EMI@

680P_0402_50V7K

1 2

1

C613
P

2

330P_0402_50V7K

13.7K_0402_1%

1 2

(

12

R609

P

24.3K_0402_1%

2

P

R606

R1)

C603

P

P

R610

10_0402_1%

+

1.8VALW

+

0.9VALWP

12

C606
P

1

P

R622

@

0_0402_5%

1

@

0_0402_5%

12

C607
P

22U_0603_6.3V6M

22U_0603_6.3V6M

1

2

2

P

R621

1

2

J601

@

P

112

JUMP_43X118

1

1

2

2

C609

C608

P

P

22U_0603_6.3V6M

1 2

@

2

0_0402_5%

3

Q601

@

P

LSK3541G1ET2L_VMT3

2

+

0.9VALW

+0.9VALWP

12

1

2

C611

C610

P

P

22U_0603_6.3V6M

P

R623

22U_0603_6.3V6M

22U_0603_6.3V6M

V

R_ON 58,88

A

PU_VDDP_SEN_H 8

A

PU_VDDP_SEN_L 8

VFB=0.6V
V

out=0.6V*(1+R1/ R2)=0.9V

A A

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONFI DENTIAL

HIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONFI DENTIAL

HIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONFI DENTIAL

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

5

4

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

3

2

2

2

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered Date

eciphered Date

eciphered Date

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet

Date: Sheet

2

Date: Sheet

ompal Electronics, Inc.

0

0

0

.9VALW/1.8VALW

.9VALW/1.8VALW

.9VALW/1.8VALW

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

1

1

1

1

A

A

8

8

8

7 99Wednesday, May 15, 2019

7 99Wednesday, May 15, 2019

7 99Wednesday, May 15, 2019

A

o

o

o

f

f

f

5

R801

2

1

2

1

V

12

@

330P_0 402_50 V7K

REF_CP U

C827
P

0.47U_0402_6.3V6K

A

PU_CORE_SEN_H 8

LL CORE(Rdroop)=2.079m

1 2

C801

@

P

A

PU_PWR OK8

A

PU_SVC8

A

PU_SVD8

A

PU_SVT_R8

R818

P

25.5K_0 402_1%

1 2

P

R822

5.9K_04 02_1%

1 2

P

R823

20.5K_0 402_1%

1 2

12

C828
P

@

0.47U_0402_6.3V6K

ET1_CPU
S

ET2_CPU
S

R802

P

10_040 2_5%

1 2

10K_04 02_1%

1

270P_0 402_50 V7K

P

R835

124K_0 402_1%

1 2

P

R837

33K_04 02_1%

1 2

R805

P

1

2

P

1 2

12

C807

1 2

H802
P

100K_0402_1%_B25/50 4250K

0.01U_04 02_50V 7K

2

P

C802

+

APU_COR E

P

R806

52.3K_0 402_1%

1

P

C808

68P_04 02_50V 8J

2

1

14

MON_CPU

I

15

REF_CP U

V

16

+

1.8VS

MONA_CPU

I

17

18

C813

P
1U_0201 _6.3V6M

19

PU_SVC

A

20

PU_SVD

A

21

PU_SVT

A

1 2

22

23

R815 0_0402 _5%

P

24

ET1_CP U

S

25

ET2_CP U

S

26

A

PU_PROCHOT# 8,58,84

Pull high at HW side

L

L_SOC(Rdroop)=3.992m

V

CC_CPU

2

R

GND

I

MON

V

064/SET3

I

MONA

V

DDIO

P

WROK

S

VC

S

VD

S

VT

O

FS

O

FSA

S

ET1

S

ET2

+

R844
P

0_0402_5%

15W_CPU@

OMP_CPU
C

13

OMP
C

CP_L
O

27

C829

P

68P_04 02_50V 8J

1 2

P

R831

110K_0 402_1%

1

5VS

2

1

B_CPU
F

12

B
F

CC
V

28

CC_CPU
V

R827
P

100K_0402_1%

2

+

APU_COR E_SOC

SEN3N_CPUISEN3P_CPU

I

R843
P

0_0402_5%

1 2

35W_CPU@

SEN3N_CPU_IC

I

11

10

SEN
V

SEN3N
I

OMPA
BIAS
I

C

29

30

BIAS_CPU

I

OMPA_CPU

1

C

2

0.01U_04 02_50V 7K

+

5VS

R845

2

P

0_0402_5%

1

35W_CPU@

SEN1P_CPUISEN1N_CPU

SEN3P_CPU_IC

I

I

8

9

SEN1P

SEN3P
I

I

SENA

BA
F

V

31

32

BA_CPU
F

+

5VS

P

C838

A

PU_VSS_SEN_L8

P

10_040 2_5%

1 2

D D

I

ocp_spikea = (3.19375 - 0.64)* PR755/ (2*DCR*Rimona)

Iocp_TDCA has relation between ocp_spikea and ΔVSET1

ΔVSET1 = +5VS*( PR788//PR784 )

S

VD_CPU and SVC_CPURC filter put CPU side.

SVT_CPU RC filter put controller side.

C C

V

CC_CPU

B B

A A

15W_C PU@

P

R816

16.5K_0 402_1%

15W_C PU@

P

35W_C PU@

R821

8.66K_0 402_1%

15W_C PU@

P

R825

17.8K_0 402_1%

P

R859

43K_04 02_1%

2

1

R858
P

1 2

48.7K_0402_1%

P

󵚩

I

C852

SVD and SVC RC filter put CPU side.
SVT RC filter put controller s ide.

A

PU_SVC

A

PU_SVD

12

P

C854

@

10P_04 02_25V 8J

A

PU_SVT_ R

12

P

C853

10P_04 02_25V 8J

R816

P

7.87K_0 402_1%

35W_C PU@

P

R821

12.1K_0 402_1%

1 2

12

35W_C PU@

P
H801
P

14.3K_0 402_1%

1

100K_0402_1%_B25/50 4250K

C852

P

0.022U_0 402_25 V7K

2

C Pin16

Iocp_spike = (3.19375 - 0.64)* PR709/ (DCR*Rimon)

Iocp_TDC has relation between ocp_spike and ΔVSET1

ΔVSET1 = +5VS*( PR788//PR784 )

12

P

C855

@

10P_04 02_25V 8J

@

P

8.2K_04 02_1%

P

470_04 02_1%

R825

R834

1 2

R836

1 2

5

+

19VB_CPU

R846
P

0_0402_5%

1 2

15W_CPU@

SEN2P_CPUISEN2N_CPU

I

5

6

7

SEN2N

SEN1N
I

I

SENA2P

SENA2N

I

I

33

34

35

C830

P

330P_0 402_50 V7K

1

R832

P

10K_04 02_1%

1

P

10_040 2_5%

1 2

12

4

C

ORE SW= 430KHz

R807
P

1 2

88.7K_0402_1%

15W_C PU@

P

0_0402 _5%

2

P

35W_C PU@

0_0402 _5%

G2_CPU

WM3_CPU_IC

ST2_CPU

ONSET_CPU

U

B

P

T

3

4

1

2

WM3

OOT2

P

G

ND

GATE2

SEN2P

B

ONSET

I

U

T

P

HASE2

L

GATE2

P

VCC

L

GATE1

P

HASE1

U

GATE1

B

OOT1

L

GATEA1

P

HASEA1

U

GATEA1

B

OOTA1

P

WMA2

T

ONSETA

N

GOODA

GOOD

SENA1N

SENA1P

P

I

I

E

P

36

37

38

39

C

onfirm HW side the pull high resistor

1 2

SENA1P_CPUISENA1N_CPU

I

R828

P

100K_0 402_5%

2

2

C833

@

P

330P_0 402_50 V7K

1 2

R833

A
PU_CORESOC_SEN_H

4

M

odule model inf ormation

RT8880C_CZ35W_V2A.mdd for IC portion

R

T8880C_CZ35W_V2B.mdd for SW portion

12

+

5VS

R848

P

WM3_CP U

1

R847

P

U801

RT3663 BCGQW _WQF N52_6X6

53

X2_CPU

L

52

G2_CPU

L

51

VCC_CP U

P

50

G1_CPU

L

49

X1_CPU

L

48

G1_CPU

U

47

ST1_CP U

B

46

G1_NB

L

45

X1_NB

L

44

G1_NB

U

43

ST1_NB

B

42

41

R819

P

+

5VS

100K_0 402_1%

19VB_C PU

P

R829

1 2

V

R_ON 5 8,87

E
Can't be floating.

+

N: high > 2V, Low < 0.8V

40

V

GATE 58

+

3VS

12

12

@

10K_04 02_5%

C831
P

@

0.1U_0402_25V6

A
PU_VSS_SEN_L

8

VCC_CP U

P

CC_CPU

V

C814
P

12

C815
P

2.2U_0603_10V6K

G1_CPU

U

ST1_CP U

B

X1_CPU

L

G1_CPU

L

P

R811

2.2_040 2_5%

1 2

1 2

P

R812

12

10_060 3_5%

2.2U_0603_10V6K

0_0603 _5%

1

R839

P

2.2_060 3_5%

ST1_CP U_R

B

1 2

G1_NB

U

1 2

R804

P

2.2_060 3_5%

ST1_NBBST1_NB1 _R

B

2

1

X1_NB

L

G1_NB

L

G2_CPU

U

ST2_CP U

B

X2_CPU

L

G2_CPU

L

+

5VALW

R838

P

2

P

C841

0.22U_06 03_25V 7K

1

R803

P
0_0603 _5%

C805

P

0.22U_06 03_25V 7K

1 2

2

G1_NB_R

U

P

R820

2.2_060 3_5%

1 2

G1_CPU_ R

U

P

R817

0_0603 _5%

1 2

3

3

ST2_CP U_R

B

7

7

P

C824

0.22U_06 03_25V 7K

1

1

1
G

2/S1

D

2

2
S

G

4

5

6

1

1
G

D

2/S1

2

2

G

S

4

5

6

2

2
S

2

2
S

G2_CPU_ R

U

2

1
D

3

1
D

3

PQ804
A

2
S

PQ801
A

2
S

1

7

2/S1

D

2
G

6

ON6962_ DFN5X6D -8-7

ON6962_ DFN5X6D -8-7

1
G

5

C803
P

R808
P

@EMI@

C811
P

@EMI@

2
S

4

C809
P

0.1U_0402_25V6

@EMI@

1

2

10U_0805_25V6K

1

2

4.7_1206_5%

12

680P_0402_50V7K

SENA1P_ CPU

I

SENA1N_C PU

I

2

1
D

2
S

12

NB_APU_NB

S

2
S

3

C810
P

@EMI@

C804
P

10U_0805_25V6K

C819
P

PQ802

ON6962_ DFN5X6D -8-7

A

C826
P

@EMI@

680P_0402_50V7K

12

C839
P

10U_0805_25V6K

2200P_0402_50V7K

C843
P

@EMI@

+

19VB_C PU

12

SENA1P_ CPU_R

I

R809

P

2.7K_04 02_1%

1

1

P

R810

845_04 02_1%

+

19VB_CPU

C821

1

12

P

C818
P

2

@EMI@

10U_0805_25V6K

10U_0805_25V6K

SEN2P_C PU_R

I

R824

12

P

P

2.7K_04 02_1%

1 2

4.7_1206_5%

@EMI@

NB_APU

S

1

2

SEN2P_C PU

I

SEN2N_CP U

I

+

19VB_CPU

12

1

C840
P

2

10U_0805_25V6K

SEN1P_C PU_R

I

R840

12

P

2.7K_04 02_1%

1 2

4.7_1206_5%

@EMI@

NB_APU2

S

12

680P_0402_50V7K

SEN1P_C PU

I

SEN1N_CP U

I

L803

P

0.22UH_24 A_20%_ 7X7X4 _M

1

1 2

2

C806

P

0.1U_040 2_25V6

2

1

2

@

C822

1

12

P

2

0.1U_0402_25V6

@EMI@

2200P_0402_50V7K

0.22UH_24 A_20%_ 7X7X4 _M

1

2

R826

0.1U_040 2_25V6

P

R830

1.1K_04 02_1%

1 2

0.22UH_24 A_20%_ 7X7X4 _M

1

2

R841

P

P

R842

1.1K_04 02_1%

1 2

+

APU_COR E_SOC

342

SENA1N_CPU-1

I

C812
P

0.1U_0402_25V6

1

+

2

P

L804

1 2

C825

P

12

C832
P

@

0.1U_0402_25V6

L805

P

1 2

C842

P

0.1U_040 2_25V6

1

C844
P

2

@

2

P

L801

EMI@

NA_2P

1 2

L802

EMI@

P

1

+

C820
P

2

33U_25V_NC_6.3X4.5

4

3

4

3

0.1U_0402_25V6

NA_2P

1 2

C834
P

33U_25V_NC_6.3X4.5

+

APU_COR E

SEN2N_CPU_R

I

+

APU_COR E

WM3_CP U

P

+

5VS

2

35W_C PU@

1U_0603 _10V6K

1

SEN1N_CPU_R

I

+

APU_CORE_SOC
TDC 10A (15W & 25W &35W)
EDC 13A (15W & 25W &35W)
OCP current 18.2A (15W & 25W &35W)
Load line -2.1mV/A
FSW=400kHz
DCR 0.98mohm +/-5%

H/S Rds(on) :11.7mohm , 14mohm
L/S Rds(on) :2.7mohm , 3.3mohm

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

35W_C PU@

P

R860

2.2_060 3_5%

2

1

35W_C PU@

U802

P

ST3_CPU
B

4

B

5

P

1

E

8

V

RT9610 CGQW_ WDFN8 _2X2

P

C845

TYP MAX

+

19VB

A

PU_core
TDC 35A (15W & 25W), 53A (35W)
EDC 45A (15W & 25W), 70A (35W)
OCP current 63A (15W & 25W), 98A (35W)
Load line -0.7mV/A
FSW=430kHz
DCR 0.98mohm +/-5%

H/S Rds(on) :11.7mohm , 14mohm
L/S Rds(on) :2.7mohm , 3.3mohm

35W_C PU@

R853

P

0_0603 _5%

G3_CPU

U

35W_C PU@

P

0.22U_06 03_25V 7K

B

ST3_CP U_R

1

3

OOT

GATE

U

2

WM

HASE

P

6

N

GND

P

7

CC

GATE

L

9

ND

G

2

2

2

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

1 2

C846

2

X3_CPU

L

L

G3_CPU

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered Date

eciphered Date

eciphered Date

TYP MAX

G3_CPU_ R

U

PQ80535W_C PU@

A

ON6962_ DFN5X6D -8-7

7

1

1
G

D

2/S1

2

2

2

S

S

G

4

5

6

1

C847

C848

P

P

C816

C817

12

2

10U_0805_25V6K

35W_CPU@

1
D

2
S

3

T

T

T

itle

itle

itle

Size Document Num ber Rev

Size Document Num ber Rev

Size Document Num ber Rev

Date: Sheetof

Date: Sheetof

Date: Sheetof

12

12

1

P

P

2

0.1U_0402_25V6

10U_0805_25V6K

@EMI@

@EMI@

2200P_0402_50V7K

35W_CPU@

I

SEN3P_C PU_R

R855
P

35W_C PU@

1

P

R856

2.7K_04 02_1%

1

@EMI@

4.7_1206_5%

2

S

NB_APU3

12

C849

P

680P_0402_50V7K

@EMI@

I

SEN3P_C PU

35W_C PU@

1.1K_04 02_1%

I

SEN3N_CP U

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

ompal Electronics, Inc.

+APU_CORE

+APU_CORE

+APU_CORE

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

1

+

19VB_CPU

35W_C PU@

0.22UH_24 A_20%_ 7X7X4 _M

134

2

1

2

35W_C PU@

P

0.1U_040 2_25V6

R857

P

2

1

1

2

L806

P

+

APU_COR E

2

C850

SEN3N_CPU_R

I

C851
P

0.1U_0402_25V6

@35W_CPU@

88 99W ednesday, May 1 5, 2019

88 99W ednesday, May 1 5, 2019

88 99W ednesday, May 1 5, 2019

1

1

1

A

A

A

5

D D

C C

4

3

2

1

R

B B

A A

5

4

eserve Page

S

S

S

ecurity Classif ication

ecurity Classif ication

ecurity Classif ication

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

2

2

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

3

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered D ate

eciphered D ate

eciphered D ate

2

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

Reserve Page

Reserve Page

Reserve Page

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

o

o

o

f

89 99Wed nesday, May 15, 2019

f

89 99Wed nesday, May 15, 2019

f

89 99Wed nesday, May 15, 2019

1

1

1

1

A

A

A

+

APU_CORE

5

+

APU_CORE +APU_CORE_SOC

4

3

+

APU_CORE_SOC

2

1

D D

C C

B B

1

2

C9001
P

22U_0603_6.3V6M

12

C9029
P

22U_0603_6.3V6M

12

C9048
P

22U_0603_6.3V6M

12

1

2

+

APU_CORE

12

12

C9003

C9002
P

P

22U_0603_6.3V6M

22U_0603_6.3V6M

12

1

C9030
P

C9052
P

C9056
P

C9081
P

2

C9031
P

22U_0603_6.3V6M

22U_0603_6.3V6M

12

1

2

C9046
P

22U_0603_6.3V6M

22U_0603_6.3V6M

1

12

C9057

2

P

0.22U_0402_16V7K

0.22U_0402_16V7K

180P_0402_50V8J

12

12

C9004

C9005
P

P

22U_0603_6.3V6M

22U_0603_6.3V6M

12

1

2

C9033

C9032
P

P

22U_0603_6.3V6M

22U_0603_6.3V6M

12

12

C9050

C9051
P

P

22U_0603_6.3V6M

22U_0603_6.3V6M

12

12

C9058

C9059
P

P

0.22U_0402_16V7K

0.22U_0402_16V7K

1

1

2

2

C9007

C9006
P

22U_0603_6.3V6M

1

2

C9034
P

22U_0603_6.3V6M

1

2

C9047
P

22U_0603_6.3V6M

12

C9060
P

0.22U_0402_16V7K

C9008

P

P

22U_0603_6.3V6M

12

C9036

C9035
P

P

22U_0603_6.3V6M

12

C9049
P

22U_0603_6.3V6M

12

C9061

C9062
P

P

0.22U_0402_16V7K

1

12

C9009
P

22U_0603_6.3V6M

12

C9037
P

22U_0603_6.3V6M

1

C9063

2

P

0.22U_0402_16V7K

1

2

2

C9010
P

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

2

2

C9038
P

22U_0603_6.3V6M

22U_0603_6.3V6M

0.22U_0402_16V7K

1

+

2

1

12

C9012

C9011

P

P

22U_0603_6.3V6M

12

C9039

C9040
P

P

22U_0603_6.3V6M

1

2

1

2

1

+

C9099

C9100
P

P

2

330U_D2_2V_Y

12

2

C9013

C9014
P

P

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

1

12

2

22U_0603_6.3V6M

C9064
P

C9082
P

C9042

C9041
P

P

22U_0603_6.3V6M

22U_0603_6.3V6M

12

1

C9065

2

0.22U_0402_16V7K

180P_0402_50V8J

C9066
P

P

0.22U_0402_16V7K

APU_CORE_SOC
330uF*2
22uF*18

0.22uF*8

330U_D2_2V_Y

12

1

2

1

2

0.22U_0402_16V7K

1

1

2

2

C9015
P

22U_0603_6.3V6M

12

C9043
P

22U_0603_6.3V6M

C9067
P

0.22U_0402_16V7K

C9017

C9016
P

P

22U_0603_6.3V6M

12

C9045

C9044
P

P

22U_0603_6.3V6M

12

12

C9068
P

0.22U_0402_16V7K

1

1

2

C9018
P

22U_0603_6.3V6M

12

C9053
P

22U_0603_6.3V6M

1

C9069

2

P

0.22U_0402_16V7K

1

12

2

2

C9020

C9019
P

P

22U_0603_6.3V6M

12

22U_0603_6.3V6M

1

C9070

2

P

0.22U_0402_16V7K

22U_0603_6.3V6M

22U_0603_6.3V6M

C9071
P

0.22U_0402_16V7K

180pF*1

n

ear CPU

330u is common part SGA00009S00

A

1

1

+

C9095
P

2

A A

1

+

+

C9097

C9096
P

P

2

2

330U_D2_2V_Y

@

220U_D7_2VM_R4.5M

ot
B

1

1

+

+

C9094
P

C9098
P

2

2

330U_D2_2V_Y

330U_D2_2V_Y

330U_D2_2V_Y

1

+

C9021
P

2

220U_D7_2VM_R4.5M

3

30u is common part SGA00009S00

PU_CORE
330uF*5
22uF*27

0.22uF*8
180pF*1

Under CPU

5

Under CPU

4

S

S

S

ecurity Classif ication

ecurity Classif ication

ecurity Classif ication

2

2

2

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

018/ 12/1 8 2019/12/18

3

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered D ate

eciphered D ate

eciphered D ate

2

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

C

C

C

ustom

ustom

ustom

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

+

+

+

APU_CORE Cap

APU_CORE Cap

APU_CORE Cap

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

o

o

o

f

90 99Wed nesday, May 15, 2019

f

90 99Wed nesday, May 15, 2019

f

90 99Wed nesday, May 15, 2019

1

1

1

1

A

A

A

5

D D

C C

4

3

2

1

B B

A A

S

S

S

ecurity Classif ication

ecurity Classif ication

ecurity Classif ication

2

2

2

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

018/ 12/1 8 2019/12/18

3

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered D ate

eciphered D ate

eciphered D ate

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Date: Sheet

Date: Sheet

2

Date: Sheet

ompal Electronics, Inc.

Reserve Page

Reserve Page

Reserve Page

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

1

1

1

A

A

A

o

o

o

f

91 99Wed nesday, May 15, 2019

f

91 99Wed nesday, May 15, 2019

f

91 99Wed nesday, May 15, 2019

1

5

C1401

VGA@

P

P

R1405

VGA@

330P_0 402_50 V7K

2K_040 2_1%

12

G

PU_VDDC I_SEN32

VGA@

R1401

P

P

R1410

@VGA@

100_04 02_1%

2

+

SUMP_NB

V

D D

SUMN_NB

V

VGA@

27.4K_0 402_1%

VGA@

470K_0 402_5% _TSM0B 474J47 02RE

G

PU_PROC HOT#28

+

VGA@

After rev1.1 must change to 13 3k

C C

470K_0 402_5% _TSM0B 474J47 02RE

S

VD and SVC RC filter put VGA side.

SVT RC filter put controller side.

G

PU_SVC28

G

PU_SVD28

B B

@

10P_04 02_25V 8J

G

PU_SVT28

VDDCI

12

R1412

2

P

2

C1413

R1413
P

1

VGA@

P

C1422

VGA@

133K_0 402_1%

R1422

VGA@

P

10.5K_0 402_1%

VGA@

2.2_040 2_5%

1 2

+

1.8VSDG PU

VGA@

1U_0402 _10V6K

C1469

P
10P_04 02_25V 8J

@

1

11K_0402_1%

R1418

P

12

R1467

P

P

C1468

@

G

PU_SVT-1

C1414

P

P

1 2

VGA@

VGA@

0.022U_0402_25V7K

2

1 2

1 2

12

VGA@

10.5K_0 402_1%

40W_5 0W_60 W_VG A@

P

C1444

0.22U_06 03_25V 7K

12

2.61K_0402_1%

VGA@

H1401

VGA@

P

12

10K +-5% 0402 B25/50 4250K

VGA@

0.1U_060 3_25V7 K

A

fter rev1.1 must change to 133 k

R1421

P

12

P

H1402

12

P

R1427

VGA@

100K_0 402_1%

1 2

3VS

P

R1433

133K_0 402_1%

2

1

C1434

VGA@

P

1000P_ 0402_2 5V6K

2

1

R1435

VGA@

P

27.4K_0 402_1%

2

1

H1403

VGA@

P

2

1

12

12

C1471

P

1 2

R1469 0_0 402_5 %

P

12

C1470

P
10P_04 02_25V 8J

@

100_04 02_1%

0_0402 _5%

1

1 2

.047U_0402_16V7K

R1416

P

1

VGA@

P

1000P_ 0402_2 5V6K

+

5VALW

V

GA_VDD IO

V

GA_ON_B37

D

GPU_PW ROK27

12

R1434

P

+

5VALW

V

SUM+

V

SUM-

C1412

@

P

1000P_ 0402_5 0V7K

2

60W@

P

R1414

2.74K_0 402_1%

12

P

C1423

@

220P_0 402_50 V7K

2

C1424

25W_V GA@

H1404
P

VGA@

1.13K_0 402_1%

1000P_ 0402_5 0V7K

1

1

+

5VALW

G

PU_SVC

PU_SVD

G

G

PU_SVT-1

@VGA@

0_0402 _5%

40W_5 0W_60 W_VG A@

VGA@

0.22U_04 02_6.3V 6K

1

2

12

10K +-5% 0402 B25/50 4250K

1

2

40W_V GA@

P

732_04 02_1%

50W_V GA@

P

825_04 02_1%

60W_V GA@

P

P

VGA@

1K_040 2_1%

C1410

VGA@

P

12

VGA@

301_04 02_1%

25W_4 0W_50 W_60 W_VG A@

P

R1417 10K _0402 _1%

M260_VG A@

P

P

R1431

1 2

E

D

GPU_PW ROK

P

R1465

0_0402 _5%

1

C1436

P

0.22U_04 02_6.3V 6K

12

C1437

VGA@

P

0.22U_04 02_6.3V 6K

2

1

C1438

P

12

R1439
P

R1443
P

2.61K_0402_1%

VGA@

1 2

VGA@

11K_0402_1%

P

C1448

VGA@

0.1U_060 3_25V7 K

R1448

R1448

R1448

R1407

12

R1411

P

2

R1466 0_ 0402_ 5%

1 2

P

1

I

2

N

3

I

4

S

5

V

6

S

7

V

8

S

9

NABLE

E

10

P

11

I

12

N

2

C1443

2

P

1

VGA@

0.047U_0402_25V7K

P

@

100_04 02_1%

2

40W_V GA@

P

R1446

1.24K_0 402_1%

50W_V GA@

R1446

P

1.43K_0 402_1%

60W_V GA@

R1446

P

1.87K_0 402_1%

12

VGA@

37.4K_0 402_1%

12

1

U1401

SEN2_NB

TC_NB

MON_NB

VC

R_HOT_L

VD

DDIO

VT

NABLE

WROK

MON

TC

2

25W_V GA@

P

C1444

0.15U_06 03_25V 7K

1

R1450

1

VGA@

P

R1408

390P_0 402_50 V7K

12

VGA@

220P_0 402_50 V8J

46

47

48

SEN1_NB

SUMP_NB

I

I

SEN2

SEN3
I

I

15

14

13

PU_ISEN1

PU_ISEN2

PU_ISEN3
G

G

G

25W_V GA@

P

R1448
665_04 02_1%

2

P

C1449

@

820P_0 402_50 V7K

2

@

P

P

C1409

32.4K_0 402_1%

12

P

C1411

12

42

43

44

45

B_NB
F

SEN_NB

OMP_NB

V

SUMN_NB

C

GOOD_NB

I

P

S IC ISL 6277AHR Z-T QFN 4 8P

TN

SEN

SUMN

SEN1

SUMP

V

R

I

I

I

19

17

16

18

VGA@

1000P_ 0402_2 5V6K

2

C1446
P

1

330P_0402_50V7K

VGA@

1

1

12

C1450
P

GA@
V

0.01UF_0402_25V7K

R1409

41

20

40

CCM_NB
F

B2
F

21

2

@VGA@

1 2

@VGA@

1 2

12

39

WM2_NB
P

B
F

22

P

C1439

0_0402 _5%

0_0402 _5%

GATEX
L

OMP
C

1

38

HASEX
P

GOOD
P

23

25W_V GA@

1K_040 2_1%

P

R1452

P

R1453

37

24

P

R1446

G

G

G

GATEX

B

U

B

GATE2

U

HASE2

P

GATE2

L

P

GATE1

L

HASE1

P

GATE1

U

OOT1
B

G

PU_BOOT 1

VGA@

301_04 02_1%

12

F

CCM_NB

PU_LGAT E3

PU_PHASE 3

PU_UGATE 3

OOTX

V

OOT2

DDP

V

DD

V

WM_Y

P
T

49

P

VGA@

100_04 02_1%

VGA@

100_04 02_1%

2

VGA@

100K_0 402_1%

IN

R1440

1 2

36

35

34

33

32

31

30

29

28

27

26

25

12

P

R1451

R1454

P

4

R1468

P

+

3VS

V

DDCI_P G 27

1

P

R1415

VGA@

41.2K_0 402_1%

2

Due to buyer command.
PC1428,PC1429 need change to S E00000QL10.
Because 0603 change to 0402, P VT need change footprint.

PU_BOOT 3

G

G

PU_BOOT 2

G

PU_UGATE 2

G

PU_PHASE 2

G

PU_LGAT E2

G

PU_PWM3

G

PU_LGAT E1

GPU_PHASE 1

G

PU_UGATE 1

VGA@

180P_0 402_50 V8J

VGA@

137K_0 402_1%

2

VGA@

2K_040 2_1%

2

12

1

VGA@

100K_0 402_1%

1 2

P

C1440

2

P

R1447

1

P

R1449

1

+

VGA_CO RE

G

PU_VDDC _SEN 32

G

PU_VSS_ SEN_L 32

@VGA@

2

12

0.22U_06 03_25V 7K

1

2

R1436

P

1

C1445

VGA@

P

390P_0 402_50 V7K

2

1

C1447

VGA@

P

680P_0 402_50 V7K

2

1

P

R1424

0_0603 _5%

C1427

VGA@

P

R1430

VGA@

P

1_0603 _5%

C1428
P

VGA@

1U_0402_10V6K

+

3VS

D

GPU_PW RGOOD 10,2 7,94

@

P

32.4K_0 402_1%

G

PU_B+

1

P

R1428

@VGA@

0_0603 _5%

12

12

1

C1429
P

2

VGA@

1U_0402_10V6K

R1441

12

+

5VALW

G

G

G

+

5VS

F

CCM_NB

G

PU_PWM3

PU_BOOT 2

PU_PHASE 2

PU_LGAT E2

PU_BOOT 3

G

PU_PHASE 3

G

PU_LGAT E3

G

12

25W_4 0W_50 W_60 W_VG A@

1U_0402 _10V6K

P

R1425

VGA@

2.2_060 3_5%

1 2

40W_5 0W_60 W_VG A@

P

R1404

2.2_060 3_5%

1 2

P

C1465

C1425

VGA@

P

0.22U_06 03_25V 7K

1 2

40W_5 0W_60 W_VG A@

P

C1407

0.22U_06 03_25V 7K

1 2

25W_4 0W_50 W_60 W_VG A@

25W_4 0W_50 W_60 W_VG A@

P

U1402

6

U

V

GATE

CC

7

B

F

CCM

OOT

3

P

P

WM

HASE

4

L

G

GATE

ND

9

T

P

ISL620 8BCRZ-T _QFN8_ 2X2

7

2/S1

D

2
G

6

P

C1466

0.22U_06 03_16V 7K

U

GATE_NB 1

1

B

OOT_NB1

2

P

HASE_NB1

8

L

GATE_NB 1

5

PU_UGATE2
G

1

2

1

1

D

G

2

2

2

S

S

S

4

5

3

PU_UGATE3
G

1

1
G

7

2/S1

D

2

2
S

G

5

6

1 2
1

25W_4 0W_50 W_60 W_VG A@

P

2.2_060 3_5%

2

3

PQ1402VG A@

ON6962_ DFN5X6D -8-7

A

2

1
D

40W_5 0W_60 W_VG A@

PQ1401

ON6962_ DFN5X6D -8-7

A

2

2

S

S

4

3

R1464

12

EMI@

4.7_120 6_5%

1

EMI@

680P_0 402_50 V7K

2

12

12

1

C1417

C1418

P

P

2

10U_0805_25V6K

VGA@

VGA@

R1419

P

C1426

P

12

C1403
P

10U_0805_25V6K

40W_50W_60W_VGA@

R1402

EMI@

P

4.7_120 6_5%

P

C1408

EMI@

680P_0 402_50 V7K

U

GATE_NB 1

2

C1435
P

VGA@

12

EMI@

4.7_120 6_5%

12

EMI@

680P_0 402_50 V7K

G

PU_B+

1

12

C1431

2

P

10U_0805_25V6K

10U_0805_25V6K

VGA@

R1437

P

C1442

P

G

PU_B+

C1420
P

1

1

1

C1419
P

2

2

2

0.1U_0402_25V6K

@EMI@

2200P_0402_50V7K

10U_0805_25V6K

VGA_EMI@

P

R1420

VGA@

10K_04 02_1%

PU_ISEN2

G

1

R1423

VGA@

P

3.65K_0 603_1%

1

SUM+

V

R1426

P

10_040 2_1%

1 2

SUM-

V

VGA@

G

PU_B1+

C1405

12

12

1

P

C1404

C1406

2

P

P

@EMI@

2200P_0402_50V7K

0.1U_0402_25V6

10U_0805_25V6K

40W_50W_60W_VGA@

40W_50W_60W_VGA_EMI@

40W_5 0W_60 W_VG A@

10K_04 02_1%

G

PU_ISEN3

1

40W_5 0W_60 W_VG A@

3.65K_0 603_1%

1 2

V

SUM+

10_040 2_1%

1

V

SUM-

5

25W_4 0W_50 W_60 W_VG A@

P

Q1404

AON6380 _DFN5X6 -8-5

4

123

5

25W_4 0W_50 W_60 W_VG A@

Q1405

P
AON6314 _N_DFN56 -8-5

4

2

3

1

L1403

60W_V GA@

P

0.22UH_MMD-06 DZER2 2MEM2L__ 32A_2 0%

(DCR:0.98± 5%)

25W_4 0W_50 W_VG A@

P

L1403

0.22UH_24 A_20%_ 7X7X4 _M

134

2

2

2

P

L1407

VGA_EMI @

FBMA-L11 -201209 -800LMA 50T

1 2

P

60W_V GA@

0.22UH_MMD-06 DZER2 2MEM2L__ 32A_2 0%

(DCR:0.98± 5%)

40W_5 0W_VG A@

L1405

P

0.22UH_24 A_20%_ 7X7X4 _M

1

R1460

P

2

R1461

P

P

R1462

2

VGA@

G

PU_VDDCI

12

1

C1462

C1463

2

P

P

10U_0805_25V6K

10U_0805_25V6K

25W_40W_50W_60W_VGA@

25W_40W_50W_60W_VGA@

1

EMI@

4.7_120 6_5%

2
1

EMI@

680P_0 402_50 V7K

2

L1405

342

C1461

P

@EMI@

2200P_0402_50V7K

R1463

P

C1467

P

+

VGA_CORE

1

12

C1460

2

P

0.1U_0402_25V6

25W_40W_50W_60W_VGA_EMI@

V

SUMP_NB

V

SUMN_NB

PU_BOOT 1

G

PU_PHASE 1

G

PU_LGAT E1

G

+

19VB

+

VGA_CORE

P

L1408

VGA_EMI @

FBMA-L11 -201209 -800LMA 50T

1

25W_4 0W_50 W_60 W_VG A@

R1403

P

3.65K_0 603_1%

2

1

R1406

P

10_040 2_1%

1 2

VGA@

VGA@

P

P

R1444

VGA@

0.22U_06 03_25V 7K

2.2_060 3_5%

1 2

1 2

2

+

19VB

+VDDCI
TDC 8A (25W & 40W & 50W & 60W)
EDC 12A (25W & 40W & 50W & 60W)
OCP current 18A (25W &50W)
FSW=400kHz
DCR 8.4mohm +/-5%

H/S Rds(on) :8.2mohm , 10.5mohm
L/S Rds(on) :2.8mohm , 3.5mohm

25W_4 0W_50 W_60 W_VG A@

0.47UH_PC MB061H-R4 7MS_11A _20%

P

L1402

1 2

󱻧󰵶󵓜󱹞󳴣

PU_UGATE1
G

1

2

1

1

D

C1441

G

7

PQ1403VG A@

A

ON6962_ DFN5X6D -8-7

D

2/S1

2

2

2

2

S

S

S

G

4

5

3

6

V

GA_CORE
TDC 30A (25W), 47A (40W), 55A (50W), 60A (60W)
EDC 45A (25W), 80A (40W), 105A (50W), 140A (60W)
OCP current 63A (25W), 120A (40W), 147A (50W), 200A (60W)
Load line -0.6mV/A
FSW=400kHz
DCR 0.98mohm +/-5%

TYP MAX
H/S Rds(on) :11.7mohm , 14mohm
L/S Rds(on) :2.7mohm , 3.3mohm

TYP MAX

c

hock 7*7*1.8 SH00000PX00 SH 000016400

+

VDDCI

G

V

V

C1432
P

2200P_0402_50V7K

@EMI@

PU_ISEN1

SUM+

SUM-

1

2

VGA@

VGA@

12

C1433
P

0.1U_0402_25V6

VGA_EMI@

P

R1438

10K_04 02_1%

1 2

R1442

P

3.65K_0 603_1%

1

P

R1445

10_040 2_1%

1

VGA@

1

VGA_EMI @

FBMA-L11 -201209 -800LMA 50T

1

(DCR:0.98± 5%)

25W_4 0W_50 W_VG A@

0.22UH_24 A_20%_ 7X7X4 _M

1

2

2

P

L1406

2

60W_V GA@

0.22UH_MMD-06 DZER2 2MEM2L__ 32A_2 0%

P

L1404

342

+

19VB

L1404

P

+

VGA_CORE

A A

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

2

2

2

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

D

D

D

eciphered Date

eciphered Date

eciphered Date

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

+VGA_CORE / +VDDCI

+VGA_CORE / +VDDCI

+VGA_CORE / +VDDCI

Size Document Num ber Rev

Size Document Num ber Rev

Size Document Num ber Rev

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

Date: Sheetof

Date: Sheetof

Date: Sheetof

1

92 99W ednesday, May 1 5, 2019

92 99W ednesday, May 1 5, 2019

92 99W ednesday, May 1 5, 2019

1

1

1

A

A

A

+

VGA_CORE

5

4

3

+

VDDCI

2

1

D D

C C

B B

+

VGA_CORE

12

C1508

C1507
P

P

22U_0603_6.3V6M

VGA@

VGA@

1

2

C1518

C1517
P

P

22U_0603_6.3V6M

VGA@

VGA@

12

C1523

C1525
P

P

22U_0603_6.3V6M

@VGA@

@VGA@

12

12

C1509
P

22U_0603_6.3V6M

VGA@

12

C1519
P

22U_0603_6.3V6M

VGA@

1

2

C1524
P

22U_0603_6.3V6M

@VGA@

12

C1510

C1511
P

P

22U_0603_6.3V6M

22U_0603_6.3V6M

VGA@

VGA@

1

1

2

2

22U_0603_6.3V6M

1

2

22U_0603_6.3V6M

C1521

C1520
P

P

22U_0603_6.3V6M

VGA@

VGA@

1

2

C1522
P

22U_0603_6.3V6M

@VGA@

1

12

2

C1513

C1512
P

P

22U_0603_6.3V6M

22U_0603_6.3V6M

VGA@

VGA@

1

12

C1543

2

22U_0603_6.3V6M

C1544
P

P

2.2U_0402_6.3V6M

VGA@

VGA@

12

12

C1515

C1514
P

P

22U_0603_6.3V6M

22U_0603_6.3V6M

VGA@

VGA@

1

2

2.2U_0402_6.3V6M

1

1

2

2

C1516
P

22U_0603_6.3V6M

22U_0603_6.3V6M

VGA@

1

+

C1545
P

25W_40W_50W_60W _VGA@

C1546
P

2

330U_D1_2VY_R9M

22U_0603_6.3V6M

@25W_40W_50W_60W_ VGA@

1

1

C1547
P

2

2

22U_0603_6.3V6M

@25W_40W_50W_60W_ VGA@

1

1

+

C1540
P

C1539
P

2

VGA@

220U_D2 SX_2VY_R9M

330U_D1_2VY_R9M

60W_VGA@

A A

5

1

+

+

C1502

C1501
P

2

P

2

VGA@

VGA@

220U_D2 SX_2VY_R9M

220U_D2 SX_2VY_R9M

1

1

+

+

C1504
P

2

2

VGA@

220U_D2 SX_2VY_R9M

C1505
P

Non 60W_VGA@

60W_VGA@

1

330U_D1_2VY_R9M

+

2

220U_D2 SX_2VY_R9M

P

C1505

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

2

2

2

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

018/ 12/18 2019/12/18

3

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered Date

eciphered Date

eciphered Date

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document Num ber Rev

Size Document Num ber Rev

Size Document Num ber Rev

Date: Sheet

Date: Sheet

2

Date: Sheet

ompal Electronics, Inc.

+VGA_CORE CAP

+VGA_CORE CAP

+VGA_CORE CAP

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

1

1

1

A

A

A

o

o

o

f

93 99Wednesday, May 15, 2019

f

93 99Wednesday, May 15, 2019

f

93 99Wednesday, May 15, 2019

1

5

4

3

2

1

EN pin don't floating
If have pull down resistor at HW side, pls delete PR2

D D

1

VGA@

P

C1016

1U_0201_6.3V6M

2

VGA@

P

U1001

2

I

N

3

I

N

4

I

N

5

I

N

7

G

ND

8

G

ND

18

G

ND

11

E

N

13

I

LMT

15

B

YP

SY8288RAC_QFN20_3X3

9

P

G

1

B

S

6

L

X

19

L

X

20

L

X

14

F

B

17

V

CC

10

N

C

12

N

C

16

N

C

21

P

AD

ST_1.5V

B

L

X_1.5V

F

B_1.5V

DO_3V_1.5

L

@VGA@

0_0603_5%

1

P

R1001

12

VGA@

0.1U_0603_25V7K

2

1

P

VGA@

2.2U_0402_6.3V6M

C1013

P

C1003

2

P

R1002

VGA_EMI@

4.7_1206_5%

NUB_1.5V

S

2

1

VGA@

P

L1002

0.68UH_PCMC063T-R68MN_15.5A_20%

F

B = 0.6V

2

1

VGA_EMI@

680P_0402_50V7K

1 2

(

R1)

1

VGA@

P

R1006

15.4K_0402_1%

2

12

VGA@

10K_0402_1%

(R2)

P

P

C1004

R1009

+

19VB

LDO_3V_1.5

C C

B B

12

@VGA@

0_0402_5%

12

@VGA@

0_0402_5%

LMT_1.5V

I

P

P

R1003

R1005

D

GPU_PWRGOOD10,27,92

P

J1001

@

112

JUMP_43X79

2

@VGA@

0_0402_5%

1

C1017
P

VGA_EMI@

P

R1004

2

P

VGA@

1M_0402_1%

0.1U_0402_25V6

R1007

+

19VB_1.5V

1

2

1

1

C1005

P
C1001
P

2

2

0.1U_0402_25V6

2200P_0402_50V7K

@VGA_EMI@

VGA_EMI@

1

12

2

1

C1002

C1006

2

P

P

VGA@

VGA@

10U_0805_25V6K

@VGA@

P

C1015

0.22U_0402_16V7K

1

2

10U_0805_25V6K

1

.5V_EN

+

3VALW

I

LMT_1.5V

M

odule model information

S

Y8208D_V1.mdd

c

hock 7*7*3

1

1

C1014

C1007
P

P

2

12

330P_0402_50V7K

VGA@

VGA@

12

C1009

C1008
P

P

2

22U_0603_6.3V6M

22U_0603_6.3V6M

VGA@

+

1.5VSDGPUP

VGA@

V

FB=0.6V

22U_0603_6.3V6M

Vout=0.6V*(1+R1/R2)=1.524V

+1.5VSDGPUP

1

2

12

12

C1011
P

22U_0603_6.3V6M

VGA@

@

JUMP_43X118

P

J1002

112

C1012
P

22U_0603_6.3V6M

VGA@

2

+

1.5VSDGPU

C1010
P

22U_0603_6.3V6M

VGA@

A A

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

2

2

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

ustom

ustom

ustom

Date: Sheet

Date: Sheet

2

Date: Sheet

ompal Electronics, Inc.

+

+

+

1.35VSDGPUP

1.35VSDGPUP

1.35VSDGPUP

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

1

1

1

1

A

A

A

o

o

o

f

94 99Wednesday, May 15, 2019

f

94 99Wednesday, May 15, 2019

f

94 99Wednesday, May 15, 2019

5

D D

C C

4

3

2

1

R

B B

A A

5

4

eserve Page

S

S

S

ecurity Classif ication

ecurity Classif ication

ecurity Classif ication

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

2

2

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

018/ 12/1 8 2019/12/18

3

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered D ate

eciphered D ate

eciphered D ate

2

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

Reserve Page

Reserve Page

Reserve Page

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

o

o

o

f

95 99Wed nesday, May 15, 2019

f

95 99Wed nesday, May 15, 2019

f

95 99Wed nesday, May 15, 2019

1

1

1

1

A

A

A

5

D D

4

+

VGA@

P

R704

1M_0402_5%

5VALW

4
3
2
1

+

3VALW

P

J701

@

112

JUMP_43X39

V

GA_ON37

1

33K_0402_1%

2

4.7U_0402_6.3 V6M

P

R701

2

VGA@

V

IN_1.8VSDGPUP

VGA@

P

C703

E

N_1.8V

12

C704
P

0.33U_0402_10V6K

VGA@

1

2

1

2

1

VGA@

P

C701

1U_0402_6.3V6K

2

VGA@

V

DD

V

IN

E

N

P

GOOD

3

G

9661MF11U_SO8P U701

5

N

C

6

V

OUT

7

A

DJ

ND

8

G

ND

G

9

VGA@

P

R702

12.7K_0402_1 %

F

B_1.8V

P

R703

10K_0402_1%

VGA@

12

1

C702

Rup

P

2

1

2

0.01U_0402_25V7K

VGA@

R

down

V

out=0.8V* (1+(12.4/10)) = 1.792V

+

1.8VSDGPUP

1

C705
P

2

22U_0603_6.3V6M

VGA@

2

+

1.8VSDGPUP

@

1

P

J702

2

1

JUMP_43X39

1

2

+

1.8VSDGPU

Vout=0.8V* (1+(12.7/10)) = 1.816V

Vout=0.8V* (1+(13/10)) = 1.84V

C C

B B

A A

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

2

2

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered Date

eciphered Date

eciphered Date

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

2

Date: Sheet

ompal Electronics, Inc.

+1.8VSDGPUP

+1.8VSDGPUP

+1.8VSDGPUP

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

1

1

1

1

A

A

A

o

o

o

f

96 99Wednesday, May 15, 2019

f

96 99Wednesday, May 15, 2019

f

96 99Wednesday, May 15, 2019

5

Version change
list (P.I.R. List)

Reason for change

D

esign Update POWER Module design Change

01

02

D D

Design Update CPU_CORE transient and load line tes t

03

Design Update reduce part count

04

Design Update reduce part cou nt 0.1

05

06

07

Design Update

Design Update

prochot

EMI

󴨈󲒽

󵙉󲮋

4

3

Page 1 of 1 for
PWR

2

Rev. PG# Modify List Date PhaseFixed IssueItem

P

Q310: EMB04N03H_SB00001C500__->__ EMP21N03HC_SB00001LC00

P

C313: 1U_0402_10V6K_SE00000QL10 __->__1U 16V K X5R 0402_SE00000OU00

0.1

0.1

0.1

P

C314: 1U_0402_10V6K_SE00000QL10 __->__2.2U 16V K X5R 0402_SE000013780

P

C830: 270P_0402_50V7K_SE0742 71K80__->__330P_0402_50V7K_SE074331K80

P

R831: 97.6K_0402_1%_SD034976280__ ->__110K_0402_1%_SD034110380

P

r806: 34.8K_0402_1%_SD034348280__ ->__52.3K_0402_1%_SD034523280

P

C9097: 330U_D2_2V_Y_SGA00009S00__->__Unpop

P

R212: 0_0402_5%_SD028000080__->_ _R-SHORT

P

R333: 0_0402_5%_SD028000080__->_ _R-SHORT

P

R314: 0_0402_5%_SD028000080__->_ _R-SHORT

P

R316: 0_0402_5%_SD028000080__->_ _R-SHORT

P

R317: 0_0402_5%_SD028000080__->_ _R-SHORT

Del colay PJ1401 PJ1402 PJ140 3

P

R304:change R-SHORT SD028000080 0_0402_5 %_ --> SD028100B80 1_0402_5%

P

0

.3

0

.3 2019/05/07 C

C323: add NA _--> SE000006O00 0.033U_0402_2 5V7K

P

C324: add NA _-->@ SE00000G880 0.1U_0402_25V6

P

R211: change SD034200280 20K_0402_1 % _ --> SD034100280 10K_0402_1%

P

R310: change SD034665280 66 .5K_0402_1% _--> SD034649280 64.9K_0402_1%

P

R1437,PR1419,PR1402,PR1463: unpop_ -->SD001470B804.7_1206_5%

P

C1442,PC1426,PC1408,PC1467: unpop_ -->SE074681K80680P_0402_50V7K

1

2019/03/22 A

2

019/03/22

2019/03/22

2019/03/22 A

2019/04/26 C

A

A

08

09

C C

10

11

12

13

14

15

16

B B

17

18

19

20

21

22

23

24

A A

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIE TARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAIN S CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIE TARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAIN S CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIE TARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAIN S CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORI ZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORI ZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORI ZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR D ISCLOSED TO ANY THIRD PA RTY WITHOUT PRIOR WRITTEN CONSENT OF COMPA L ELECTRONICS, INC.

MAY BE USED BY OR D ISCLOSED TO ANY THIRD PA RTY WITHOUT PRIOR WRITTEN CONSENT OF COMPA L ELECTRONICS, INC.

5

4

MAY BE USED BY OR D ISCLOSED TO ANY THIRD PA RTY WITHOUT PRIOR WRITTEN CONSENT OF COMPA L ELECTRONICS, INC.

3

C

C

C

ompal Secret Data

ompal Secret Data

2

2

2

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

ompal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

ustom

ustom

ustom

Date: Sheetof

Date: Sheetof

Date: Sheetof

P

P

P

WR_PIR1

WR_PIR1

WR_PIR1

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

97 99Wednesday, May 15, 2019

97 99Wednesday, May 15, 2019

97 99Wednesday, May 15, 2019

1

1

1

1

A

A

A

5

Version change
list (P.I.R. List)

Reason for change

4

3

Page 1 of 1 for
PWR

2

1

Rev. PG# Modify List Date PhaseFixed IssueItem

01

02

D D

03

04

05

06

07

08

09

C C

10

11

12

13

14

15

16

B B

17

18

19

20

21

22

23

24

A A

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIE TARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAIN S CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIE TARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAIN S CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIE TARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAIN S CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORI ZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORI ZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORI ZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR D ISCLOSED TO ANY THIRD PA RTY WITHOUT PRIOR WRITTEN CONSENT OF COMPA L ELECTRONICS, INC.

MAY BE USED BY OR D ISCLOSED TO ANY THIRD PA RTY WITHOUT PRIOR WRITTEN CONSENT OF COMPA L ELECTRONICS, INC.

5

4

MAY BE USED BY OR D ISCLOSED TO ANY THIRD PA RTY WITHOUT PRIOR WRITTEN CONSENT OF COMPA L ELECTRONICS, INC.

3

C

C

C

ompal Secret Data

ompal Secret Data

2

2

2

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

ompal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

ustom

ustom

ustom

Date: Sheetof

Date: Sheetof

Date: Sheetof

P

P

P

WR_PIR2

WR_PIR2

WR_PIR2

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

98 99Wednesday, May 15, 2019

98 99Wednesday, May 15, 2019

98 99Wednesday, May 15, 2019

1

1

1

1

A

A

A

A

B

C

D

E

Page 1 of 2 for HWVersion change list (P.I.R. List)

Item

Page PhaseSolution DescriptionTitle

1 C

2 ESPI_ALERT_L PU to VDD Add RC6168 and PU to +3VS

1 1

3

4

5

6

7

38 Panel 03/28 144Hz Panel OD Function Circuit Update Rename PANEL_OD_EN to PANEL_OD#

40 HDMI 03/28 Mask un-use co-lay component L2512, L2513, L2514, L2515 footprint change to INPAQ_HCM1012GH900BP_4P-NPM

43

TypeC 03/28 TypeC current limiting adjust

51 LAN 03/28

M.2 SSD1 03/28

8

2 2

68

M.2 SSD2 M.2 SSD2 power need a break point03/28

9

10

11

75 HUB 03/28 BOM change Change RS154, RS152 with HUB@

77 Others 03/28 Screw hole change H11, H12, H13 change from H_3P8 to H_3P3

78 U4 change to SB00001IY00

DC-DC 03/28 Material Change

12 06 CPU 03/29 Add R5/ R7 CPU PN Add SA0000CCR60/ SA0000C7680

06 CPU13 04/01 Material Change YC2 Change from SJ10000AF00 to SJ10000JP00

CPU1015 04/02 BOM change YC3 change to SJ10000PW00

3 3

58,63

17 58 04/26EC Add Board ID for MP Add R1564 15K_0402_1% for MP

18 04/30HUB

75 Delete RS148 ~ RS158, CS145 ~ CS153, YS1, US15

52

38
66

Date Issue Description Rev.

hange 0 ohm to R-Short03/28

03/2810 CPU

R1667, R1669, RM53, RX21 change to R-Short

CV450,CV451 change to 15P_040227MHz Crystal Correlation Update29 CLK GEN 03/28

UN-POP RX11

1.0PVT

1.0PVT

PVT 1.0

PVT 1.0

PVT 1.0

RS109 change to 4.3K_0402
RS110 change to 8.2K_0402

PVT 1.0

YL1 update vale to XRCGB25M000F2P34R0Correct YL1 Value

Change DL1 Material DL1 change from SCA00002M00 to SCA00001A00

Reserved Circuit for PCIE compatibility

BOM change

Change RM28 to 0_0402
Add RM135, UM5

Pop RM21, un-pop RM20, CM58

PVT 1.0

1.0PVT

Add RO26, JSSD2 power change to +3VS_SSD2

PVT 1.0

PVT 1.0

PVT 1.0

PVT 1.0

PVT 1.0

Un-Pop RC693BOM change04/02CPU0914

CC686 change to 12P_0402
CC682 change to 10P_0402

Material Change04/0216 28,38,

DV1,DV2,DV4, DX2, D2012,D2013,D2014,D22 change to SCS00009P00

PVT 1.0

PVT 1.0

PVT 1.0

MP 1A

Remove Hub and other component/net

1AMP

Move RS146, RS147, CS143, CS144 to page52 and POP

Delete net HUB_USB20_P2/HUB_USB20_N2 (JEDP1 pin 29,30)
Delete net HUB_USB20_P3/HUB_USB20_N3 (RK19, RK18 pin 1)
Delete net USB_HUB_RESET# (U44 pin 126)58

5219 M.2 SSD1 04/30 Reserved 10U_0603 on WLAN Power Reserved CM79, CM80

M.2 SSD25220

21 DC-DC

4 4

05/14

05/14

WLAN power path change

Un-Pop RM101
POP UM3, CM71

Change C21 to 4700pF37 Adjust C21 for +1.8VS Sequence

MP 1A

1AMP

1AMP

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2

2

2

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

018/ 12/18 2019/12/18

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered Date

eciphered Date

eciphered Date

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

ustom

ustom

ustom

Date: Sheet

Date: Sheet

D

Date: Sheet

ompal Electronics, Inc.

H

H

H

W PIR

W PIR

W PIR

F

F

F

H50P M/B LA-H901P

H50P M/B LA-H901P

H50P M/B LA-H901P

E

1

1

1

A

A

A

o

o

o

f

99 99Wednesday, May 15, 2019

f

99 99Wednesday, May 15, 2019

f

99 99Wednesday, May 15, 2019