COMPAL LA-H431P Schematics

A

1 1

B

C

D

E

Compal Confidential

2 2

MB Schematic Document

EH50F/EH70F/EH51F/EH5VF/EH53F/EH73F

3 3

4 4

A

B

LA-H431P

Rev:1.0

2018.01.22

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2019/12/ 28 2019/12/ 28

2019/12/ 28 2019/12/ 28

2019/12/ 28 2019/12/ 28

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Cover Sheet

Cover Sheet

Cover Sheet

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

EH50F M/B LA-H431PR10

EH50F M/B LA-H431PR10

EH50F M/B LA-H431PR10

Date : Sheet o f

Date : Sheet o f

Date : Sheet o f

1 1 00Wednesd ay, February 13, 201 9

1 1 00Wednesd ay, February 13, 201 9

1 1 00Wednesd ay, February 13, 201 9

E

1.0

1.0

1.0

A

B

C

D

E

RTC circuit

eDP

eDP Panel

Conn.

1 1

page 38

4 lane

eDPx4

page 20

Memory BUS

Fan Control

page 77

260pin DDR4-SO-DIMM

Thermal sensor

page 66

page 23

Dual Channel

HDMI

HDMI 2.0

Conn.

page 40

Display Port

Conn.

page 39

4 lane

DP
4 lane

<N18E-G1
witih GDDR6 *6>

page 25~37

PEG X16 (0~15)
8GT/s

VBIOS ROM

1.8V 8Mbit

page 31

2 2

page 68 page 68

PCIe x4 PCIe x4
SATA3.0 SATA3.0

M.2 WLAN
Dual Band

page 52

802.11 ac/agn

LAN(GbE)

Killer Ethernet

E2500

PCIe x1PCIe x1

page 51

M.2 SSDM.2 SSD

Conn.Conn.

Flexible I/O

SATAx1

SATA HDD

page 67

6.0 Gb/s

CoffeeLake H PROCESSOR
BGA1440
(42X28) (CFL-H_6+2)

Processor

page 06~13

X4 DMI

Cannonlake PCH - H
FCBGA(23X23)

837pin FCBGA

1.2V DDR4 2400

USB Bus

FHD CAM

Conn.

Offline USB Charger

USB3.0

Conn.(M/B)

USB3.0

page 71

Silego USB charger

SLGC55544

page 71

page 38

USB2.0

M.2

Blue Tooth

page 52

260pin DDR4-SO-DIMM

USB3.0

Conn.(M/B)

page 72

USB3.0

Touch Screen

USB2.0

page 38

USB2.0

page 24

USB Type-C

Conn.(M/B)

page 43

USB3.0

Finger Print

page 66

USB2.0

3.3V 24MHz

SPI

SPI ROM

16M

page 16

HD Audio

HDA Codec

ALC255

page 56

Speaker

Conn.

page 56

Head Phone

Jack
Conn.

MIC Jack

Conn.

ON USB2.0_Audio/B

page 73

RJ45

Conn.

3 3

page 51

page 14~21

LED driver

SUB/B

TLC5 9116

4 4

USB 2.0_Audio/B

Hall/B

page 73

page 66

A

page 63

B

SMBUS

ENE

KB9022

page 58

Touch Pad

page 63

I2C/PS2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2019/12/28 2019/12/28

2019/12/28 2019/12/28

2019/12/28 2019/12/28

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Date : Sheet of

Date : Sheet of

Date : Sheet of

Compal Electronics, Inc.

Block Diagrams

Block Diagrams

Block Diagrams

EH50F M/B LA-H431PR10

EH50F M/B LA-H431PR10

EH50F M/B LA-H431PR10

E

2 100Wednesday, February 13, 2 019

2 100Wednesday, February 13, 2 019

2 100Wednesday, February 13, 2 019

1.0

1.0

1.0

A

B

C

D

E

Board ID Table for AD channel

Vcc 3.3 V

Board ID

1 1

2 2

100K +/- 1%Ra

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

0
12K +/- 1% 0.347 V 0.345 V 0.360 V
15K +/- 1%
20K +/- 1%
27K +/- 1%
33K +/- 1%
43K +/- 1%
56K +/- 1%
75K +/- 1%
100K +/- 1%
130K +/- 1%
160K +/- 1%
200K +/- 1%
240K +/- 1%
270K +/- 1%
330K +/- 1%
430K +/- 1%
560K +/- 1%
750K +/- 1%

NC

Rb V min

BID

0.423 V 0.430 V 0.438 V

1.398 V

1.634 V

1.849 V

2.015 V

2.185 V

2.316 V

2.395 V

2.521 V

2.667 V

2.791 V

2.905 V

3.000 V

V typ

BID

0.000 V

1.414 V

1.650 V

1.865 V

2.031 V

2.200 V

2.329 V

2.408 V

2.533 V

2.677 V

2.800 V

2.912 V

3.000 V

V

BID

0.300 V

1.430 V

1.667 V

1.881 V

2.046 V

2.215 V

2.343 V

2.421 V

2.544 V

2.687 V

2.808 V

2.919 V

max

EC AD

0x00 - 0x13
0x14 - 0x1E
0x1F - 0x25
0x26 - 0x300.541 V 0.550 V 0.559 V
0x31 - 0x3A0.691 V 0.702 V 0.713 V
0x3B - 0x450.807 V 0.819 V 0.831 V
0x46 - 0x540.978 V 0.992 V 1.006 V
0x55 - 0x641.169 V 1.185 V 1.200 V
0x65 - 0x76
0x77 - 0x87
0x88 - 0x96
0x97 - 0xA4
0xA5 - 0xAF
0xB0 - 0xB7
0xB8 - 0xBF
0xC0 - 0xC9
0xCA - 0xD4
0xD5 - 0xDD
0xDE - 0xF0
0xF1 - 0xFF

I2C Address Table

BUS

Device

Address(7 bit)

I2C_0 (+3VS)
I2C_1 (+3VS)

TM-P3393-003 (Touch Pad)
SA577C-12A0 (Touch Pad)

PCH_SMBCLK

(+3VS)

PCH_SML1CLK
EC_SMB_CK2
(+3VALW)

EC_SMB_CK1
(+3VLP)

3 3

EC_SMB_CK3
(+3VALW)

DIMM1
DIMM2

N18E-G0/G1 (VGA)
Thermal Sensor (NCT7718W)

0x9E

1001_100xb

PCH 0x90

ISL88739 (Charger IC)

BATTERY PACK

0x12
0x16

LED driver 0xC0

Address( 8bit)

Write Rea d

1001_1001b 1001_1000b

BOM Structure Table

BOM Option Table

BOM StructureIte m

Unpop

Connector

i5 CPU
i7 CPU
PCH PCH@
CMC CMC@
dGPU circuit VGA@
VGA GC6 3.0 NFGC6@
VGA GC63.0+FGPC6 FGC6@
Intel CNVi CNVI@
USB charger CH G@
EMI/ESD requirement EMC@
EMI/ESD require reserve XEMC@
With TPM

Without TPM NTPM@

OVRM with uPI
OVRM with ON
With SATA redriver
Without SATA redriver NORD@
Thermal sensor
With FingerPrint
FingerPrint ESD
With G-SYNC panel GSYNC@
Without G-SYNC panel NGSYNC@
RF requirement reserve @RF@
for SW debug board UART@
UMA sku

HDMI cost 45@
VRAM BOM

@

CONN@

I5@
I7@

TPM@

uPI@

ON@
SATARD@

TMS@
FP@

FPESD@

UMA@

X76@

Power State

STATE

S0 (Full ON) ON ON ON ONHIGH HIGH HIGH

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

SIGNA L

SLP_S3 # SLP_S4 # SLP_S5 # + VALW +V +VS Clock

LOW HIGH

HIGH

LOWLOW

HIGH

Voltage Rails

Power Plane

+RTCVCC

+19V_VIN

+12.6V_B ATT Battery power supply

+19VB

+3VLP

+5VALW

+3VALW System +3VALW always on power rail

+3VALW_DSW +3VALW power for PCH DSW rails

+3VALW_PCH_PRIM

+3VALW_SPI

+1.05VALW +1.05V Always power rail

+1.05V_VCCST

+5VS System +5V power rail

+3VS

+1.05VS_VCCSTG +1.05VALW_PRIM Gated version of VCCST

+0.6VS_VTT DDR +0.6VS power rail for DDR terminator .

+VCC_CORE

+VCC_GT

+VCCIO

+VCC_SA

+1.8VSDGPU_AON

+VGA_CORE

+1.35VSDGPU +1.35VS power rail for GPU

+1.0VSDGPU

+1.8VALW System +1.8VALW always on power rail

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

Description

RTC Battery Power

Adapter power supply

AC or battery power r ail for power circuit.

+19VB to +3VLP power rail for suspend power

+5V Always power rail

+3VALW power for PCH power rails

+3VALW_PRIM supply for the SPI IO

DDR4 +1.2V power rail+1.2V_VDDQ

Sustain voltage for processor in Standby modes

System +3V power rail

Core voltage for CPU

Sliced graphics power r ail

CPU IO +0.95VS power r ail

System Agent power rail

+1.8VS power rail for GPU(AON rails)

+1.8VS power rail for GPU GC6+1.8VSDGPU_MAIN

Core voltage for VGA (merge core & core_s)

+1.0VS power rail for GPU

ONONON

ON

OFF

OFFLOW LOW LOW

OFF

OFF

OFF

OFF

OFF

OFF

S0

S3

ON

ON

N/A N/A N/A

N/A

N/A

N/A

N/A

ON

ON

ON

ON

ON

ON

ON

ON

ON

ON

ON ON ONON

ON

ON

ON

ON ON

ON

ON

ON

ON

ON

ON

ON

ON

ON

ON

ON

ON

ON

ON

ON

OFF

OFF

OFF

OFF

OFF OFF

OFF OFF OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF OFF OFF

OFF

OFF

OFF OFF

OFF

OFF OFF

OFF OFF

OFF OFF OFF

OFF OFF OFF

ONON

S4

ON ON

N/A N/A

ON ON

ON ON

ON

ON ON

ON

S5

N/AN/AN/A

ON*

ON*ON

ON

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFFOFF

OFF

ON*

BOARD ID Table

43 level BOM table

431AH3BO L01 SMT MB AH431 EH50F N18EG1Q 6G QP89 HDMI

CHG@/EMC@/ CMC@/CNVI@/ FGC6@/NGSY NC@/PCH@/NO RD@/TMS@/ TPM@ /UPI @/VG A@/i 5@/F P@/F PESD @

BOM Structure43 Level Desc riptio n

Board ID

0
1
2
3
4
5
6
7
8

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

C

2019/12/28 2019/12/28

2019/12/28 2019/12/28

2019/12/28 2019/12/28

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

9

PCB Revision

2050 Rev0.1
2050 Rev0.2
2050 Rev0.3
2050 Rev1.0
2060 Rev0.1
2060 Rev0.2
2060 Rev0.3
2060 Rev1.0

Board ID

10
11
12
13
14
15
16
17
18

PCB Revision

19

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Notes List

Notes List

Notes List

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

EH50F M/B LA-H431PR10

EH50F M/B LA-H431PR10

EH50F M/B LA-H431PR10

Date : Sheet of

Date : Sheet of

Date : Sheet of

E

1.0

1.0

3 100Wednesday, February 13, 2 019

3 100Wednesday, February 13, 2 019

3 100Wednesday, February 13, 2 019

1.0

5

Vinafix

4

3

DC_IN

PJP101

AC CONN.

D D

C C

B B

PL101

PU301

CHARGER

+19V_V IN

+12.6V _BAT T

+19VB

+19VB

+19VB

+19VB

+19VB

+19VB

+19VB

PL201,PL202

IMVP8

PU1802
PU8103
PU8104
PU8105

EN:VR_ ON

PU8106

EN:DR ON

PU8301

EN:DR ON

EN:3V_ EN

PU401

EN:SYS ON

PU501

PU601

EN:+3V ALW

PU7201 PJ720 1

EN:SUS P#

PJP201

PL8101,PL8104,PL81 05,PL8106

PL8107

PL8301

+3VALWP

PJ401

+1.2VP

PJ501

EN:SM_P G_CT RL

+0.6VSP

PJ502

+1.05VAL WP

PJ601

+0.95VS_V CCIOP

+12.6V_BATT+

BATTERY

+VCC_ GT

+VCC_ SA

+3VAL W

EC,LID

+3VLP

+1.2V_ VDDQ

+0.6VS _VTT

+1.05V ALW

+VCCI O

CPU

CPU

CPU

+VCC_C ORE

JPC1,C2

RC24

CPU

+1.2V_V DDQ_ CPU

+1.2V_V CCPL L_OC

CPU

CPU

PU7105

PU7102

PU1401

UQ1

R19

UM1

UL2

UK1

RH97

RS1

RH101

RH99

UK2

RH92

RH94

RH93

UQ2

UC4

+1.8VA LWP

PJ7107

+2.5V P

PJ7103

+1.0VS DGPU P

PJ1401

JPQ1

+3VALW _TPM

+3VS_W LAN

+3V_L AN

+3V_P TP

+3VALW_ PCH_ PRIM

+3.3V_ CC

+3VALW _HDA

+3VALW _DSW

+FP_V CC

+1.05VALW _VCCMPH Y

RQ61

+1.8VA LW

+2.5V

+1.0VS DGPU

+3VS

+1.05VA LW_P RIM

+1.05VA LW_P CH

RH102

RH103

RH105

+1.05V_ VCCS T

+1.05VS _VCC STG

UQ2

RH100

U5

JNGFF1

UL2

JTP1

RH98

PCH

PCH

FP

PCH

PCH

PCH

+1.8V S

+ 1.8VALW _PRIM

GPU

TPM

WLAN CARD (IOAC)

LAN

TP

+3VALW _SPI

CPU

UG27

RA3

DIMM1

DIMM2

UH2

PCH

2

EN:DGPU _PWR _EN

+1.8VSD GPU_ AON

+1.8VSD GPU_ MAIN

+1.8VD DA

PCH

DDR4

SPI

GPU

CODEC

UO1

RZ1

RM1

R20

UX1

RA2

RA4

+3VS_SS D_NG FF

+3VS_T PM

+LCDV DD

+3VS_D VDDI O

+3VS_D VDD

SATA Re-driver

G-SENSOR

JSSD1

U5

JEDP1

+3VS_DVDDIO

+3VS_DVDD

1

SSD

TPM

PANEL

CODEC

CODEC

US2

JIO3

+5VALWP

+19VB

+19VB

A A

+19VB

PU402

PL1502
PL1503

PL1301

+19VB → +19V_CPU

5

PJ402

+19VB_NV VDD

PU1501
PU1502

EN:1.35 VS_DG PU_P G

+1.35VS DGPU P

PJ1302
PJ1303

LX1

+5VAL W

PL1501
PL1502

GPU

+1.35V SDGP U

+INVPW R_B+

GPU

+VGA_C ORE

PANEL

4

US11

US1

JPQ2

+5V_C C

+USB3_ VCCC

+USB_V CCA

+5VS

USB2.0 Conn/ IOB.

US2

JTYPEC1

Type C Conn.

USB3.0 Conn.

UQ1

RF4

RF7

JPA1

U4

RO4

UY2

RX7 JEDP1

3

+VCC_F AN1

+VCC_F AN2

+VDDA

+5VS_ BL

+5VS_H DD

+HDMI_5 V_OU T

+TS_P WR

FAN1

FAN2

UA1

JBL1

JHDD1

JHDMI1

CODEC

KB BackLight

HDD

HDMI

TS

2

Security Classificati on

Security Classificati on

Security Classificati on

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY O F THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY O F THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY O F THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WR ITTEN CONSENT O F CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WR ITTEN CONSENT O F CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WR ITTEN CONSENT O F CO MPAL ELECTRONICS, INC.

Compal Secret Data

Compal Secret Data

Compal Secret Data

2019/12/28 2019/12/28

2019/12/28 2019/12/28

2019/12/28 2019/12/28

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Power Map

Power Map

Power Map

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

EH50F M/B LA-H431PR10

EH50F M/B LA-H431PR10

EH50F M/B LA-H431PR10

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

1

4 100Wednesday, February 13, 2019

4 100Wednesday, February 13, 2019

4 100Wednesday, February 13, 2019

1.0

1.0

1.0

A

EH50F_EVT Power Sequence
BIOS : 0.02T3
AC mode

Power On

B

C

S3 S3 Resume

D

Power Off

E

Plug in

+3VLP

1 1

EC_ON

+5VALW

→

330.8ms

→

2.64ms

ON/OFFBT N#

→

+3VALW

+1.8VALW

+1.05ALW

EC_RSMRS T#

PBTN_OUT #

PM_SLP_S 4#

PM_SLP_S 3#

2 2

SYSON

+1.05V_V CCST

+1.2V_VD DQ

+2.5V

SUSP#

+1.05VS_V CCSTG

+VCCIO

+5VS

+3VS

+1.8VS

EC_VCCST _PG

SM_PG_CT RL

3 3

+0.6VS_V TT

VR_ON

+VCC_SA

PCH_PWRO K

SYS_PWRO K

PLT_RST#

+VCC_COR E

+VCC_GT

92.2ms

→

→

105.1ms

106.3ms

→

→

1.8ms

→

129.6m s

20ms

→

←

←

21.1ms

→

18.96ms

→

26us

1.494ms

→

→

586.5us

→

978.5us

→

2.058ms

→

11.84ms

11us

→

395us

→

→

→

→

→

1.459ms

749us

2.299ms

20.55ms

9us

→

→

9us

21.99ms

→

→

→

→

→

2.146ms

9.75ms

140.7ms

→

1.1ms

145.1ms

708.8ms

→

→

→

→

→

→

←

←

→

→

←

16.6us

203.5us

489us

-6.1us

-6.1us

7.65us

→

→

49.65us

→

-283us

→

-547.3ms

←

←

2.07ms

889us

5.589ms

5.25ms

476.6us

67.5us

1.492ms

→

→

→

→

→

→

→

→

32.22ms

9us

475us

765us

2.305ms

1.495ms

20.71ms

12.8us

→

6.8us

→

20.23ms

2.066ms

→

→

→

→

→

10.07ms

142.1ms

55.9ms

→

202.3ms

553.8ms

→

→

→

←

→

→

→

→

→

146us

154us

457us

→

→

→

17.6us

→

→

→

→

→

←

←

→

→

1.897ms

223.6us

235us

-7us

-7us

8.65us

→

52.65us

→

63.5us

→

-281us

→

-6.353s

←

9.235s

9.235s

9.235s

8.782S

8.782S

10.46ms

2.268ms

865us

5.995ms

1.73ms

458.6us

1.492ms

+3VLP

EC_ON

+5VALW

ON/OFFBT N#

+3VALW

+1.8VALW

+1.05ALW

EC_RSMRS T#

PBTN_OUT #

PM_SLP_S 4#

PM_SLP_S 3#

SYSON

+1.05V_V CCST

+1.2V_VD DQ

+2.5V

SUSP

+1.05VS_V CCSTG

+VCCIO→

+5VS

+3VS

+1.8VS

EC_VCCST _PG

SM_PG_CT RL

+0.6VS_V TT

VR_ON

+VCC_SA

PCH_PWRO K

SYS_PWRO K

PLT_RST#

+VCC_COR E

+VCC_GT

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

C

2019/12/28 2019/12/28

2019/12/28 2019/12/28

2019/12/28 2019/12/28

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Power Sequence

Power Sequence

Power Sequence

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

C

C

C

EH50F M/B LA-H431PR10

EH50F M/B LA-H431PR10

EH50F M/B LA-H431PR10

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

E

5 100Wednesday, February 13, 2019

5 100Wednesday, February 13, 2019

5 100Wednesday, February 13, 2019

1.0

1.0

1.0

A

1 1

2 2

Coffee Lake-H CPU SKU

UC1

3 3

CFL-H_BGA1440

S IC CL8068 403373522 SR3 Z0 U0 2.3G ABO!
SA0000B PJ40
i5@

UC1

CFL-H_BGA1440

S IC CL8068 403359524 SR3 YY U0 2.2G ABO !
SA0000B PZ40
i7@

B

CFL-H

UC1D

EDP_AUXP
EDP_AUXN

D29

E29
F28

E28
A29

B29
C28

B28

C26

B26

A33

D37

G27

G25
G29

K36

DDI1_TXP_0

K37

DDI1_TXN_0

J35

DDI1_TXP_1

J34

DDI1_TXN_1

H37

DDI1_TXP_2

H36

DDI1_TXN_2

J37

DDI1_TXP_3

J38

DDI1_TXN_3

D27

DDI1_AUXP

E27

DDI1_AUXN

H34

DDI2_TXP_0

H33

DDI2_TXN_0

F37

DDI2_TXP_1

G38

DDI2_TXN_1

F34

DDI2_TXP_2

F35

DDI2_TXN_2

E37

DDI2_TXP_3

E36

DDI2_TXN_3

F26

DDI2_AUXP

E26

DDI2_AUXN

C34

DDI3_TXP_0

D34

DDI3_TXN_0

B36

DDI3_TXP_1

B34

DDI3_TXN_1

F33

DDI3_TXP_2

E33

DDI3_TXN_2

C33

DDI3_TXP_3

B33

DDI3_TXN_3

A27

DDI3_AUXP

B27

DDI3_AUXN

CFL-H_BG A1440

EDP_TXP_0
EDP_TXN_0

EDP_TXP_1
EDP_TXN_1

EDP_TXP_2
EDP_TXN_2

EDP_TXP_3
EDP_TXN_3

EDP_DISP_UTIL

DISP_RCOMP

PROC_AUDIO_CLK

PROC_AUDIO_SDI

PROC_AUDIO_SDO

4 of 13

Cannon Lake PCH SKU

UH1

C

EDP_TXP 0

EDP_TXN 0

EDP_TXP 1

EDP_TXN 1

EDP_TXP 2
EDP_TXN 2

EDP_TXP 3
EDP_TXN 3

EDP_AUX P
EDP_AUX N

DP_RCOM P

Trace Width/Space: 15 mil/ 20 mil
Max Trace Length: 600 mil

CPU_DISPA _SDI

RC1 24.9_04 02_1%

RC2 20_040 2_5%

RC2 close to CPU

1 2

follow CRB

12

EDP_TXP 0 <3 8>
EDP_TXN 0 <3 8>

EDP_TXP 1 <3 8>
EDP_TXN 1 <3 8>

EDP_TXP 2 <3 8>
EDP_TXN 2 <3 8>

EDP_TXP 3 <3 8>
EDP_TXN 3 <3 8>

EDP_AUX P <38>
EDP_AUX N <38>

+VCCIO

CPU_DISPA _BCLK_R

CPU_DISPA _SDO_R

CPU_DISPA _SDI_R

D

eDP

CPU_DISPA _BCLK_R <18>

CPU_DISPA _SDO_R <18>

CPU_DISPA _SDI_R <18>

E

CFL-H_BGA1440

S IC FH82HM3 70 SR40B B0 BGA 874P PCH-H ABO!
SA0000B VP10
PCH@

NV N18E-G1

UG9

4 4

VGA@

S IC N18E-G1-K D-A1 QS FCBG A 2228 G PU

SA0000CFC00

A

B

Security Classification

Security Classification

Security Classification

2019/12/ 28 2019/12/ 28

2019/12/ 28 2019/12/ 28

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2019/12/ 28 2019/12/ 28

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

CFL-H(1/8)DDI/eDP

CFL-H(1/8)DDI/eDP

CFL-H(1/8)DDI/eDP

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

EH50F M/B LA-H431PR10

EH50F M/B LA-H431PR10

EH50F M/B LA-H431PR10

Date : Sheet o f

Date : Sheet o f

Date : Sheet o f

6 1 00Wednesd ay, February 13, 201 9

6 1 00Wednesd ay, February 13, 201 9

6 1 00Wednesd ay, February 13, 201 9

E

1.0

1.0

1.0

A

B

C

D

E

CHANNEL-A

Interleaved Memory

UC1A

1 1

2 2

3 3

DDR_A_D [0..63]<23>

For ECC DIMM

DDR_A_D 0
DDR_A_D 1

DDR_A_D 2
DDR_A_D 3

DDR_A_D 4
DDR_A_D 5

DDR_A_D 6

DDR_A_D 7

DDR_A_D 8
DDR_A_D 9

DDR_A_D 10

DDR_A_D 11

DDR_A_D 12

DDR_A_D 13
DDR_A_D 14

DDR_A_D 15

DDR_A_D 16

DDR_A_D 17

DDR_A_D 18

DDR_A_D 19

DDR_A_D 20

DDR_A_D 21

DDR_A_D 22

DDR_A_D 23

DDR_A_D 24
DDR_A_D 25

DDR_A_D 26
DDR_A_D 27

DDR_A_D 28
DDR_A_D 29

DDR_A_D 30

DDR_A_D 31
DDR_A_D 32

DDR_A_D 33

DDR_A_D 34

DDR_A_D 35

DDR_A_D 36
DDR_A_D 37

DDR_A_D 38
DDR_A_D 39

DDR_A_D 40

DDR_A_D 41

DDR_A_D 42

DDR_A_D 43

DDR_A_D 44

DDR_A_D 45

DDR_A_D 46
DDR_A_D 47

DDR_A_D 48

DDR_A_D 49
DDR_A_D 50

DDR_A_D 51
DDR_A_D 52

DDR_A_D 53
DDR_A_D 54

DDR_A_D 55
DDR_A_D 56

DDR_A_D 57

DDR_A_D 58

DDR_A_D 59

DDR_A_D 60
DDR_A_D 61

DDR_A_D 62

DDR_A_D 63

DDR4(IL)/LP3-DDR4(NIL) LP3/DDR4

BR6

DDR0_DQ_0/DDR0_DQ_0

BT6

DDR0_DQ_1/DDR0_DQ_1

BP3

DDR0_DQ_2/DDR0_DQ_2

BR3

DDR0_DQ_3/DDR0_DQ_3

BN5

DDR0_DQ_4/DDR0_DQ_4

BP6

DDR0_DQ_5/DDR0_DQ_5

BP2

DDR0_DQ_6/DDR0_DQ_6

BN3

DDR0_DQ_7/DDR0_DQ_7

BL4

DDR0_DQ_8/DDR0_DQ_8

BL5

DDR0_DQ_9/DDR0_DQ_9

BL2

DDR0_DQ_10/DDR0_DQ_10

BM1

DDR0_DQ_11/DDR0_DQ_11

BK4

DDR0_DQ_12/DDR0_DQ_12

BK5

DDR0_DQ_13/DDR0_DQ_13

BK1

DDR0_DQ_14/DDR0_DQ_14

BK2

DDR0_DQ_15/DDR0_DQ_15

BG4

DDR0_DQ_16/DDR0_DQ_32

BG5

DDR0_DQ_17/DDR0_DQ_33

BF4

DDR0_DQ_18/DDR0_DQ_34

BF5

DDR0_DQ_19/DDR0_DQ_35

BG2

DDR0_DQ_20/DDR0_DQ_36

BG1

DDR0_DQ_21/DDR0_DQ_37

BF1

DDR0_DQ_22/DDR0_DQ_38

BF2

DDR0_DQ_23/DDR0_DQ_39

BD2

DDR0_DQ_24/DDR0_DQ_40

BD1

DDR0_DQ_25/DDR0_DQ_41

BC4

DDR0_DQ_26/DDR0_DQ_42

BC5

DDR0_DQ_27/DDR0_DQ_43

BD5

DDR0_DQ_28/DDR0_DQ_44

BD4

DDR0_DQ_29/DDR0_DQ_45

BC1

DDR0_DQ_30/DDR0_DQ_46

BC2

DDR0_DQ_31/DDR0_DQ_47

AB1

DDR0_DQ_32/DDR1_DQ_0

AB2

DDR0_DQ_33/DDR1_DQ_1

AA4

DDR0_DQ_34/DDR1_DQ_2

AA5

DDR0_DQ_35/DDR1_DQ_3

AB5

DDR0_DQ_36/DDR1_DQ_4

AB4

DDR0_DQ_37/DDR1_DQ_5

AA2

DDR0_DQ_38/DDR1_DQ_6

AA1

DDR0_DQ_39/DDR1_DQ_7

V5

DDR0_DQ_40/DDR1_DQ_8

V2

DDR0_DQ_41/DDR1_DQ_9

U1

DDR0_DQ_42/DDR1_DQ_10

U2

DDR0_DQ_43/DDR1_DQ_11

V1

DDR0_DQ_44/DDR1_DQ_12

V4

DDR0_DQ_45/DDR1_DQ_13

U5

DDR0_DQ_46/DDR1_DQ_14

U4

DDR0_DQ_47/DDR1_DQ_15

R2

DDR0_DQ_48/DDR1_DQ_32

P5

DDR0_DQ_49/DDR1_DQ_33

R4

DDR0_DQ_50/DDR1_DQ_34

P4

DDR0_DQ_51/DDR1_DQ_35

R5

DDR0_DQ_52/DDR1_DQ_36

P2

DDR0_DQ_53/DDR1_DQ_37

R1

DDR0_DQ_54/DDR1_DQ_38

P1

DDR0_DQ_55/DDR1_DQ_39

M4

DDR0_DQ_56/DDR1_DQ_40

M1

DDR0_DQ_57/DDR1_DQ_41

L4

DDR0_DQ_58/DDR1_DQ_42

L2

DDR0_DQ_59/DDR1_DQ_43

M5

DDR0_DQ_60/DDR1_DQ_44

M2

DDR0_DQ_61/DDR1_DQ_45

L5

DDR0_DQ_62/DDR1_DQ_46

L1

DDR0_DQ_63/DDR1_DQ_47

LP3/DDR4

BA2

NC/DDR0_ECC_0

BA1

NC/DDR0_ECC_1

AY4

NC/DDR0_ECC_2

AY5

NC/DDR0_ECC_3

BA5

NC/DDR0_ECC_4

BA4

NC/DDR0_ECC_5

AY1

NC/DDR0_ECC_6

AY2

NC/DDR0_ECC_7

CFL-H_BG A1440

CFL-H

DDR CHANNEL A

DDR0_CKP_0/DDR0_CKP_0

DDR0_CKN_0/DDR0_CKN_0

DDR0_CKP_1/DDR0_CKP_1

DDR0_CKN_1/DDR0_CKN_1

NC/DDR0_CKP_2

NC/DDR0_CKN_2

NC/DDR0_CKP_3

NC/DDR0_CKN_3

DDR0_CKE_0/DDR0_CKE_0

DDR0_CKE_1/DDR0_CKE_1

DDR0_CKE_2/DDR0_CKE_2

DDR0_CKE_3/DDR0_CKE_3

DDR0_CS#_0/DDR0_CS#_0

DDR0_CS#_1/DDR0_CS#_1

NC/DDR0_CS#_2

NC/DDR0_CS#_3

DDR0_ODT_0/DDR0_ODT_0

NC/DDR0_ODT_1

NC/DDR0_ODT_2

NC/DDR0_ODT_3

DDR0_CAB_4/DDR0_BA_0

DDR0_CAB_6/DDR0_BA_1

DDR0_CAA_5/DDR0_BG_0

DDR0_CAB_3/DDR0_MA_16

DDR0_CAB_2/DDR0_MA_14

DDR0_CAB_1/DDR0_MA_15

DDR0_CAB_9/DDR0_MA_0

DDR0_CAB_8/DDR0_MA_1

DDR0_CAB_5/DDR0_MA_2

NC/DDR0_MA_3

NC/DDR0_MA_4

DDR0_CAA_0/DDR0_MA_5

DDR0_CAA_2/DDR0_MA_6

DDR0_CAA_4/DDR0_MA_7

DDR0_CAA_3/DDR0_MA_8

DDR0_CAA_1/DDR0_MA_9

DDR0_CAB_7/DDR0_MA_10

DDR0_CAA_7/DDR0_MA_11

DDR0_CAA_6/DDR0_MA_12

DDR0_CAB_0/DDR0_MA_13

DDR0_CAA_9/DDR0_BG_1

DDR0_CAA_8/DDR0_ACT#

NC/DDR0_PAR

NC/DDR0_ALERT#

DDR4(IL)/LP3-DDR4(NIL)

DDR0_DQSN_0/DDR0_DQSN_0

DDR0_DQSN_1/DDR0_DQSN_1

DDR0_DQSN_2/DDR0_DQSN_4

DDR0_DQSN_3/DDR0_DQSN_5

DDR0_DQSN_4/DDR1_DQSN_0

DDR0_DQSN_5/DDR1_DQSN_1

DDR0_DQSN_6/DDR1_DQSN_4

DDR0_DQSN_7/DDR1_DQSN_5

DDR0_DQSP_0/DDR0_DQSP_0

DDR0_DQSP_1/DDR0_DQSP_1

DDR0_DQSP_2/DDR0_DQSP_4

DDR0_DQSP_3/DDR0_DQSP_5

DDR0_DQSP_4/DDR1_DQSP_0

DDR0_DQSP_5/DDR1_DQSP_1

DDR0_DQSP_6/DDR1_DQSP_4

DDR0_DQSP_7/DDR1_DQSP_5

DDR0_DQSP_8/DDR0_DQSP_8

DDR0_DQSN_8/DDR0_DQSN_8

1 OF 13

AG1

AG2

AK2

AK1

AL3

AK3

AL2

AL1

AT1

AT2

AT3

AT5

AD5

AE2

AD2

AE5

AD3

AE4

AE1

AD4

AH5

AH1

AU1

AH4

AG4

AD1

AH3

AP4
AN4

AP5

AP2

AP1

AP3

AN1

AN3

AT4

AH2
AN2

AU4

AE3

AU2

AU3

AG3

AU5

BR5

BL3

BG3

BD3

AA3

U3

P3

L3

BP5

BK3

BF3

BC3

AB3

V3

R3

M3

AY3

BA3

DDR_A_C LK0
DDR_A_C LK#0

DDR_A_C LK1
DDR_A_C LK#1

DDR_A_C KE0
DDR_A_C KE1

DDR_A_C S#0
DDR_A_C S#1

DDR_A_O DT0
DDR_A_O DT1

DDR_A_B A0

DDR_A_B A1
DDR_A_B G0

DDR_A_M A16_RAS#

DDR_A_M A14_WE#
DDR_A_M A15_CAS#

DDR_A_M A0
DDR_A_M A1

DDR_A_M A2

DDR_A_M A3
DDR_A_M A4

DDR_A_M A5

DDR_A_M A6

DDR_A_M A7

DDR_A_M A8

DDR_A_M A9

DDR_A_M A10

DDR_A_M A11
DDR_A_M A12

DDR_A_M A13

DDR_A_B G1
DDR_A_A CT#

DDR_A_P AR
DDR_A_A LERT#

DDR_A_D QS#0
DDR_A_D QS#1

DDR_A_D QS#2
DDR_A_D QS#3

DDR_A_D QS#4

DDR_A_D QS#5

DDR_A_D QS#6

DDR_A_D QS#7

DDR_A_D QS0

DDR_A_D QS1

DDR_A_D QS2
DDR_A_D QS3

DDR_A_D QS4

DDR_A_D QS5

DDR_A_D QS6
DDR_A_D QS7

DDR_A_C LK0 <23 >

DDR_A_C LK#0 <2 3>

DDR_A_C LK1 <23 >

DDR_A_C LK#1 <2 3>

DDR_A_C KE0 <23 >

DDR_A_C KE1 <23 >

DDR_A_C S#0 <23 >
DDR_A_C S#1 <23 >

DDR_A_O DT0 <23>

DDR_A_O DT1 <23>

DDR_A_B A0 <23>
DDR_A_B A1 <23>

DDR_A_B G0 <23>

DDR_A_M A16_RAS# <23>
DDR_A_M A14_WE# <23>

DDR_A_M A15_CAS# <23>

DDR_A_M A0 < 23>
DDR_A_M A1 < 23>

DDR_A_M A2 < 23>

DDR_A_M A3 < 23>

DDR_A_M A4 < 23>

DDR_A_M A5 < 23>

DDR_A_M A6 < 23>

DDR_A_M A7 < 23>
DDR_A_M A8 < 23>

DDR_A_M A9 < 23>

DDR_A_M A10 <23>

DDR_A_M A11 <23>
DDR_A_M A12 <23>

DDR_A_M A13 <23>

DDR_A_B G1 <23>
DDR_A_A CT# <23>

DDR_A_P AR <23>

DDR_A_A LERT# <23 >

DDR_A_D QS#0 < 23>

DDR_A_D QS#1 < 23>

DDR_A_D QS#2 < 23>

DDR_A_D QS#3 < 23>

DDR_A_D QS#4 < 23>

DDR_A_D QS#5 < 23>
DDR_A_D QS#6 < 23>

DDR_A_D QS#7 < 23>

DDR_A_D QS0 <2 3>

DDR_A_D QS1 <2 3>

DDR_A_D QS2 <2 3>
DDR_A_D QS3 <2 3>

DDR_A_D QS4 <2 3>

DDR_A_D QS5 <2 3>

DDR_A_D QS6 <2 3>

DDR_A_D QS7 <2 3>

For ECC DIMM

4 4

Security Classification

Security Classification

Security Classification

2019/12/ 28 2019/12/ 28

2019/12/ 28 2019/12/ 28

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

2019/12/ 28 2019/12/ 28

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

CFL-H(2/8)DIMMA

CFL-H(2/8)DIMMA

CFL-H(2/8)DIMMA

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

EH50F M/B LA-H431PR10

EH50F M/B LA-H431PR10

EH50F M/B LA-H431PR10

Date : S heet o f

Date : S heet o f

D

Date : S heet o f

7 1 00Wednesd ay, February 13, 201 9

7 1 00Wednesd ay, February 13, 201 9

7 1 00Wednesd ay, February 13, 201 9

E

1.0

1.0

1.0

A

B

C

D

E

CHANNEL-B

Interleaved Memory

1 1

2 2

3 3

DDR_B_D [0..63]<24>

For ECC DIMM

DDR_B_D 0

DDR_B_D 1
DDR_B_D 2

DDR_B_D 3
DDR_B_D 4

DDR_B_D 5
DDR_B_D 6

DDR_B_D 7
DDR_B_D 8

DDR_B_D 9
DDR_B_D 10

DDR_B_D 11
DDR_B_D 12

DDR_B_D 13
DDR_B_D 14

DDR_B_D 15
DDR_B_D 16

DDR_B_D 17
DDR_B_D 18

DDR_B_D 19
DDR_B_D 20

DDR_B_D 21
DDR_B_D 22

DDR_B_D 23
DDR_B_D 24

DDR_B_D 25
DDR_B_D 26

DDR_B_D 27
DDR_B_D 28

DDR_B_D 29
DDR_B_D 30

DDR_B_D 31
DDR_B_D 32

DDR_B_D 33
DDR_B_D 34

DDR_B_D 35
DDR_B_D 36

DDR_B_D 37
DDR_B_D 38

DDR_B_D 39

DDR_B_D 40

DDR_B_D 41
DDR_B_D 42

DDR_B_D 43
DDR_B_D 44

DDR_B_D 45
DDR_B_D 46

DDR_B_D 47
DDR_B_D 48

DDR_B_D 49
DDR_B_D 50

DDR_B_D 51
DDR_B_D 52

DDR_B_D 53
DDR_B_D 54

DDR_B_D 55
DDR_B_D 56

DDR_B_D 57
DDR_B_D 58

DDR_B_D 59
DDR_B_D 60

DDR_B_D 61
DDR_B_D 62

DDR_B_D 63

UC1B

DDR4(IL)/LP3-DDR4(NIL)

BT11

DDR1_DQ_0/DDR0_DQ_16

BR11

DDR1_DQ_1/DDR0_DQ_17

BT9

DDR1_DQ_2/DDR0_DQ_18

BR8

DDR1_DQ_3/DDR0_DQ_19

BP11

DDR1_DQ_4/DDR0_DQ_20

BN11

DDR1_DQ_5/DDR0_DQ_21

BP8

DDR1_DQ_6/DDR0_DQ_22

BN8

DDR1_DQ_7/DDR0_DQ_23

BL12

DDR1_DQ_8/DDR0_DQ_24

BL11

DDR1_DQ_9/DDR0_DQ_25

BL8

DDR1_DQ_10/DDR0_DQ_26

BJ8

DDR1_DQ_11/DDR0_DQ_27

BJ11

DDR1_DQ_12/DDR0_DQ_28

BJ10

DDR1_DQ_13/DDR0_DQ_29

BL7

DDR1_DQ_14/DDR0_DQ_30

BJ7

DDR1_DQ_15/DDR0_DQ_31

BG11

DDR1_DQ_16/DDR0_DQ_48

BG10

DDR1_DQ_17/DDR0_DQ_49

BG8

DDR1_DQ_18/DDR0_DQ_50

BF8

DDR1_DQ_19/DDR0_DQ_51

BF11

DDR1_DQ_20/DDR0_DQ_52

BF10

DDR1_DQ_21/DDR0_DQ_53

BG7

DDR1_DQ_22/DDR0_DQ_54

BF7

DDR1_DQ_23/DDR0_DQ_55

BB11

DDR1_DQ_24/DDR0_DQ_56

BC11

DDR1_DQ_25/DDR0_DQ_57

BB8

DDR1_DQ_26/DDR0_DQ_58

BC8

DDR1_DQ_27/DDR0_DQ_59

BC10

DDR1_DQ_28/DDR0_DQ_60

BB10

DDR1_DQ_29/DDR0_DQ_61

BC7

DDR1_DQ_30/DDR0_DQ_62

BB7

DDR1_DQ_31/DDR0_DQ_63

AA11

DDR1_DQ_32/DDR1_DQ_16

AA10

DDR1_DQ_33/DDR1_DQ_17

AC11

DDR1_DQ_34/DDR1_DQ_18

AC10

DDR1_DQ_35/DDR1_DQ_19

AA7

DDR1_DQ_36/DDR1_DQ_20

AA8

DDR1_DQ_37/DDR1_DQ_21

AC8

DDR1_DQ_38/DDR1_DQ_22

AC7

DDR1_DQ_39/DDR1_DQ_23

DDR4(IL)/LP3-DDR4(NIL)

W8

DDR1_DQ_40/DDR1_DQ_24

W7

DDR1_DQ_41/DDR1_DQ_25

V10

DDR1_DQ_42/DDR1_DQ_26

V11

DDR1_DQ_43/DDR1_DQ_27

W11

DDR1_DQ_44/DDR1_DQ_28

W10

DDR1_DQ_45/DDR1_DQ_29

V7

DDR1_DQ_46/DDR1_DQ_30

V8

DDR1_DQ_47/DDR1_DQ_31

R11

DDR1_DQ_48/DDR1_DQ_48

P11

DDR1_DQ_49/DDR1_DQ_49

P7

DDR1_DQ_50/DDR1_DQ_50

R8

DDR1_DQ_51/DDR1_DQ_51

R10

DDR1_DQ_52/DDR1_DQ_52

P10

DDR1_DQ_53/DDR1_DQ_53

R7

DDR1_DQ_54/DDR1_DQ_54

P8

DDR1_DQ_55/DDR1_DQ_55

L11

DDR1_DQ_56/DDR1_DQ_56

M11

DDR1_DQ_57/DDR1_DQ_57

L7

DDR1_DQ_58/DDR1_DQ_58

M8

DDR1_DQ_59/DDR1_DQ_59

L10

DDR1_DQ_60/DDR1_DQ_60

M10

DDR1_DQ_61/DDR1_DQ_61

M7

DDR1_DQ_62/DDR1_DQ_62

L8

DDR1_DQ_63/DDR1_DQ_63

LP3/DDR4

AW11

NC/DDR1_ECC_0

AY11

NC/DDR1_ECC_1

AY8

NC/DDR1_ECC_2

AW8

NC/DDR1_ECC_3

AY10

NC/DDR1_ECC_4

AW10

NC/DDR1_ECC_5

AY7

NC/DDR1_ECC_6

AW7

NC/DDR1_ECC_7

CFL-H

DDR CHANNEL B

DDR1_CKP_0/DDR1_CKP_0

DDR1_CKN_0/DDR1_CKN_0

DDR1_CKP_1/DDR1_CKP_1

DDR1_CKN_1/DDR1_CKN_1

DDR1_CKE_0/DDR1_CKE_0

DDR1_CKE_1/DDR1_CKE_1

DDR1_CKE_2/DDR1_CKE_2

DDR1_CKE_3/DDR1_CKE_3

DDR1_CS#_0/DDR1_CS#_0

DDR1_CS#_1/DDR1_CS#_1

DDR1_ODT_0/DDR1_ODT_0

DDR1_CAB_3/DDR1_MA_16

DDR1_CAB_2/DDR1_MA_14

DDR1_CAB_1/DDR1_MA_15

DDR1_CAB_4/DDR1_BA_0

DDR1_CAB_6/DDR1_BA_1

DDR1_CAA_5/DDR1_BG_0

DDR1_CAB_9/DDR1_MA_0

DDR1_CAB_8/DDR1_MA_1

DDR1_CAB_5/DDR1_MA_2

DDR1_CAA_0/DDR1_MA_5

DDR1_CAA_2/DDR1_MA_6

DDR1_CAA_4/DDR1_MA_7

DDR1_CAA_3/DDR1_MA_8

DDR1_CAA_1/DDR1_MA_9

DDR1_CAB_7/DDR1_MA_10

DDR1_CAA_7/DDR1_MA_11

DDR1_CAA_6/DDR1_MA_12

DDR1_CAB_0/DDR1_MA_13

DDR1_CAA_9/DDR1_BG_1

DDR1_CAA_8/DDR1_ACT#

DDR1_DQSN_0/DDR0_DQSN_2

DDR1_DQSN_1/DDR0_DQSN_3

DDR1_DQSN_2/DDR0_DQSN_6

DDR1_DQSN_3/DDR0_DQSN_7

DDR1_DQSN_4/DDR1_DQSN_2

DDR1_DQSN_5/DDR1_DQSN_3

DDR1_DQSN_6/DDR1_DQSN_6

DDR1_DQSN_7/DDR1_DQSN_7

DDR1_DQSP_0/DDR0_DQSP_2

DDR1_DQSP_1/DDR0_DQSP_3

DDR1_DQSP_2/DDR0_DQSP_6

DDR1_DQSP_3/DDR0_DQSP_7

DDR1_DQSP_4/DDR1_DQSP_2

DDR1_DQSP_5/DDR1_DQSP_3

DDR1_DQSP_6/DDR1_DQSP_6

DDR1_DQSP_7/DDR1_DQSP_7

DDR1_DQSP_8/DDR1_DQSP_8

DDR1_DQSN_8/DDR1_DQSN_8

LP3/DDR4

NC/DDR1_CKP_2

NC/DDR1_CKN_2

NC/DDR1_CKP_3

NC/DDR1_CKN_3

NC/DDR1_CS#_2

NC/DDR1_CS#_3

NC/DDR1_ODT_1

NC/DDR1_ODT_2

NC/DDR1_ODT_3

NC/DDR1_MA_3

NC/DDR1_MA_4

NC/DDR1_PAR

NC/DDR1_ALERT#

DDR4(IL)/LP3-DDR4(NIL)

AM9

AN9

AM7

AM8

AM11

AM10

AJ10

AJ11

AT8

AT10

AT7

AT11

AF11

AE7

AF10

AE10

AF7

AE8

AE9

AE11

AH10

AH11

AF8

AH8

AH9

AR9

AJ9

AK6

AK5

AL5

AL6

AM6

AN7

AN10

AN8

AR11

AH7

AN11

AR10

AF9

AR7
AT9

AJ7

AR8

BN9

BL9

BG9

BC9

AC9

W9

R9

M9

BP9

BJ9

BF9

BB9

AA9

V9

P9

L9

AW9

AY9

DDR_B_C LK0

DDR_B_C LK#0
DDR_B_C LK1

DDR_B_C LK#1

DDR_B_C KE0

DDR_B_C KE1

DDR_B_C S#0

DDR_B_C S#1

DDR_B_O DT0

DDR_B_O DT1

DDR_B_M A16_RAS#

DDR_B_M A14_WE#
DDR_B_M A15_CAS#

DDR_B_B A0

DDR_B_B A1
DDR_B_B G0

DDR_B_M A0

DDR_B_M A1

DDR_B_M A2

DDR_B_M A3

DDR_B_M A4

DDR_B_M A5

DDR_B_M A6

DDR_B_M A7

DDR_B_M A8

DDR_B_M A9

DDR_B_M A10

DDR_B_M A11

DDR_B_M A12

DDR_B_M A13

DDR_B_B G1

DDR_B_A CT#

DDR_B_P AR
DDR_B_A LERT#

DDR_B_D QS#0

DDR_B_D QS#1

DDR_B_D QS#2

DDR_B_D QS#3
DDR_B_D QS#4

DDR_B_D QS#5

DDR_B_D QS#6

DDR_B_D QS#7

DDR_B_D QS0

DDR_B_D QS1

DDR_B_D QS2

DDR_B_D QS3
DDR_B_D QS4

DDR_B_D QS5

DDR_B_D QS6

DDR_B_D QS7

DDR_B_C LK0 <24 >

DDR_B_C LK#0 <2 4>
DDR_B_C LK1 <24 >

DDR_B_C LK#1 <2 4>

DDR_B_C KE0 <24 >
DDR_B_C KE1 <24 >

DDR_B_C S#0 <24 >
DDR_B_C S#1 <24 >

DDR_B_O DT0 <24>
DDR_B_O DT1 <24>

DDR_B_M A16_RAS# <24>
DDR_B_M A14_WE# <24>

DDR_B_M A15_CAS# <24>

DDR_B_B A0 <24>
DDR_B_B A1 <24>

DDR_B_B G0 <24>

DDR_B_M A0 < 24>
DDR_B_M A1 < 24>

DDR_B_M A2 < 24>

DDR_B_M A3 < 24>
DDR_B_M A4 < 24>

DDR_B_M A5 < 24>

DDR_B_M A6 < 24>

DDR_B_M A7 < 24>

DDR_B_M A8 < 24>

DDR_B_M A9 < 24>

DDR_B_M A10 <24>

DDR_B_M A11 <24>

DDR_B_M A12 <24>

DDR_B_M A13 <24>

DDR_B_B G1 <24>

DDR_B_A CT# <24>

DDR_B_P AR <24>

DDR_B_A LERT# <24 >

DDR_B_D QS#0 < 24>

DDR_B_D QS#1 < 24>

DDR_B_D QS#2 < 24>

DDR_B_D QS#3 < 24>

DDR_B_D QS#4 < 24>

DDR_B_D QS#5 < 24>

DDR_B_D QS#6 < 24>

DDR_B_D QS#7 < 24>

DDR_B_D QS0 <2 4>

DDR_B_D QS1 <2 4>

DDR_B_D QS2 <2 4>

DDR_B_D QS3 <2 4>

DDR_B_D QS4 <2 4>

DDR_B_D QS5 <2 4>

DDR_B_D QS6 <2 4>

DDR_B_D QS7 <2 4>

For ECC DIMM

1 2

RC3 121_0 402_1%

1 2

RC4 75_040 2_1%

1 2

RC5 100_04 02_1%

Trace Width/Space: 15 mil/ 25 mil

4 4

A

Max Trace Length: 500 mil

B

SM_RCOM P0

SM_RCOM P1
SM_RCOM P2

G1

DDR_RCOMP_0

H1

DDR_RCOMP_1

J2

DDR_RCOMP_2

CFL-H_BG A1440

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2 OF 13

DDR_VREF_CA

DDR0_VREF_DQ

DDR1_VREF_DQ

Compal Secret Data

Compal Secret Data

2019/12/ 28 2019/12/ 28

2019/12/ 28 2019/12/ 28

2019/12/ 28 2019/12/ 28

C

Compal Secret Data

BN13

BP13

BR13

Deciphered Date

Deciphered Date

Deciphered Date

+0.6V_VR EFCA

+0.6V_B_ VREFDQ

+0.6V_VR EFCA

+0.6V_B_ VREFDQ

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

CFL-H(3/8)DIMMB

CFL-H(3/8)DIMMB

CFL-H(3/8)DIMMB

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

EH50F M/B LA-H431PR10

EH50F M/B LA-H431PR10

EH50F M/B LA-H431PR10

Date : S heet o f

Date : S heet o f

Date : S heet o f

8 1 00Wednesd ay, February 13, 201 9

8 1 00Wednesd ay, February 13, 201 9

8 1 00Wednesd ay, February 13, 201 9

E

1.0

1.0

1.0

A

PEG&DMI

B

C

D

E

1 1

2 2

3 3

To DGPU
PEG Lane Reversed

PEG_CRX _C_GTX_P15<25>

PEG_CRX _C_GTX_N15<25>

PEG_CRX _C_GTX_P14<25>

PEG_CRX _C_GTX_N14<25>

PEG_CRX _C_GTX_P13<25>

PEG_CRX _C_GTX_N13<25>

PEG_CRX _C_GTX_P12<25>

PEG_CRX _C_GTX_N12<25>

PEG_CRX _C_GTX_P11<25>

PEG_CRX _C_GTX_N11<25>

PEG_CRX _C_GTX_P10<25>

PEG_CRX _C_GTX_N10<25>

PEG_CRX _C_GTX_P9<25>

PEG_CRX _C_GTX_N9<25>

PEG_CRX _C_GTX_P8<25>

PEG_CRX _C_GTX_N8<25>

PEG_CRX _C_GTX_P7<25>

PEG_CRX _C_GTX_N7<25>

PEG_CRX _C_GTX_P6<25>

PEG_CRX _C_GTX_N6<25>

PEG_CRX _C_GTX_P5<25>

PEG_CRX _C_GTX_N5<25>

PEG_CRX _C_GTX_P4<25>

PEG_CRX _C_GTX_N4<25>

PEG_CRX _C_GTX_P3<25>

PEG_CRX _C_GTX_N3<25>

PEG_CRX _C_GTX_P2<25>

PEG_CRX _C_GTX_N2<25>

PEG_CRX _C_GTX_P1<25>

PEG_CRX _C_GTX_N1<25>

PEG_CRX _C_GTX_P0<25>

PEG_CRX _C_GTX_N0<25>

+VCCIO

To PCH

1 2

CC1 0.22U_020 1_6.3V6MVGA@

1 2

CC3 0.22U_020 1_6.3V6MVGA@

1 2

CC5 0.22U_020 1_6.3V6MVGA@

1 2

CC6 0.22U_020 1_6.3V6MVGA@

1 2

CC7 0.22U_020 1_6.3V6MVGA@

1 2

CC14 0.22U_02 01_6.3V6MVGA@

1 2

CC16 0.22U_02 01_6.3V6MVGA@

1 2

CC17 0.22U_02 01_6.3V6MVGA@

1 2

CC19 0.22U_02 01_6.3V6MVGA@

1 2

CC20 0.22U_02 01_6.3V6MVGA@

1 2

CC10 0.22U_02 01_6.3V6MVGA@

1 2

CC23 0.22U_02 01_6.3V6MVGA@

1 2

CC25 0.22U_02 01_6.3V6MVGA@

1 2

CC27 0.22U_02 01_6.3V6MVGA@

1 2

CC29 0.22U_02 01_6.3V6MVGA@

1 2

CC31 0.22U_02 01_6.3V6MVGA@

1 2

CC33 0.22U_02 01_6.3V6MVGA@

1 2

CC35 0.22U_02 01_6.3V6MVGA@

1 2

CC37 0.22U_02 01_6.3V6MVGA@

1 2

CC39 0.22U_02 01_6.3V6MVGA@

1 2

CC41 0.22U_02 01_6.3V6MVGA@

1 2

CC43 0.22U_02 01_6.3V6MVGA@

1 2

CC45 0.22U_02 01_6.3V6MVGA@

1 2

CC47 0.22U_02 01_6.3V6MVGA@

1 2

CC49 0.22U_02 01_6.3V6MVGA@

1 2

CC51 0.22U_02 01_6.3V6MVGA@

1 2

CC53 0.22U_02 01_6.3V6MVGA@

1 2

CC55 0.22U_02 01_6.3V6MVGA@

1 2

CC57 0.22U_02 01_6.3V6MVGA@

1 2

CC59 0.22U_02 01_6.3V6MVGA@

1 2

CC61 0.22U_02 01_6.3V6MVGA@

1 2

CC63 0.22U_02 01_6.3V6MVGA@

1 2

RC6 24.9_04 02_1%

DMI_CRX_P TX_P0<14>

DMI_CRX_P TX_N0<14>

DMI_CRX_P TX_P1<14>

DMI_CRX_P TX_N1<14>

DMI_CRX_P TX_P2<14>

DMI_CRX_P TX_N2<14>

DMI_CRX_P TX_P3<14>

DMI_CRX_P TX_N3<14>

PEG_CRX _GTX_P15

PEG_CRX _GTX_N15

PEG_CRX _GTX_P14

PEG_CRX _GTX_N14

PEG_CRX _GTX_P13

PEG_CRX _GTX_N13

PEG_CRX _GTX_P12

PEG_CRX _GTX_N12

PEG_CRX _GTX_P11

PEG_CRX _GTX_N11

PEG_CRX _GTX_P10

PEG_CRX _GTX_N10

PEG_CRX _GTX_P9

PEG_CRX _GTX_N9

PEG_CRX _GTX_P8

PEG_CRX _GTX_N8

PEG_CRX _GTX_P7

PEG_CRX _GTX_N7

PEG_CRX _GTX_P6

PEG_CRX _GTX_N6

PEG_CRX _GTX_P5

PEG_CRX _GTX_N5

PEG_CRX _GTX_P4

PEG_CRX _GTX_N4

PEG_CRX _GTX_P3

PEG_CRX _GTX_N3

PEG_CRX _GTX_P2

PEG_CRX _GTX_N2

PEG_CRX _GTX_P1

PEG_CRX _GTX_N1

PEG_CRX _GTX_P0

PEG_CRX _GTX_N0

PEG_RCO MP

Trace Width/Space: 15 mil/ 15 mil
Max Trace Length: 600 mil

DMI_CRX_P TX_P0
DMI_CRX_P TX_N0

DMI_CRX_P TX_P1
DMI_CRX_P TX_N1

DMI_CRX_P TX_P2
DMI_CRX_P TX_N2

DMI_CRX_P TX_P3
DMI_CRX_P TX_N3

E25

PEG_RXP_0

D25

PEG_RXN_0

E24

PEG_RXP_1

F24

PEG_RXN_1

E23

PEG_RXP_2

D23

PEG_RXN_2

E22

PEG_RXP_3

F22

PEG_RXN_3

E21

PEG_RXP_4

D21

PEG_RXN_4

E20

PEG_RXP_5

F20

PEG_RXN_5

E19

PEG_RXP_6

D19

PEG_RXN_6

E18

PEG_RXP_7

F18

PEG_RXN_7

D17

PEG_RXP_8

E17

PEG_RXN_8

F16

PEG_RXP_9

E16

PEG_RXN_9

D15

PEG_RXP_10

E15

PEG_RXN_10

F14

PEG_RXP_11

E14

PEG_RXN_11

D13

PEG_RXP_12

E13

PEG_RXN_12

F12

PEG_RXP_13

E12

PEG_RXN_13

D11

PEG_RXP_14

E11

PEG_RXN_14

F10

PEG_RXP_15

E10

PEG_RXN_15

G2

PEG_RCOMP

D8

DMI_RXP_0

E8

DMI_RXN_0

E6

DMI_RXP_1

F6

DMI_RXN_1

D5

DMI_RXP_2

E5

DMI_RXN_2

J8

DMI_RXP_3

J9

DMI_RXN_3

CFL-H_BG A1440

UC1C

CFL-H

PEG_TXP_0
PEG_TXN_0

PEG_TXP_1
PEG_TXN_1

PEG_TXP_2
PEG_TXN_2

PEG_TXP_3
PEG_TXN_3

PEG_TXP_4
PEG_TXN_4

PEG_TXP_5
PEG_TXN_5

PEG_TXP_6
PEG_TXN_6

PEG_TXP_7
PEG_TXN_7

PEG_TXP_8
PEG_TXN_8

PEG_TXP_9
PEG_TXN_9

PEG_TXP_10

PEG_TXN_10

PEG_TXP_11

PEG_TXN_11

PEG_TXP_12

PEG_TXN_12

PEG_TXP_13

PEG_TXN_13

PEG_TXP_14

PEG_TXN_14

PEG_TXP_15

PEG_TXN_15

3 OF 13

DMI_TXP_0
DMI_TXN_0

DMI_TXP_1
DMI_TXN_1

DMI_TXP_2
DMI_TXN_2

DMI_TXP_3
DMI_TXN_3

B25

A25

B24

C24

B23

A23

B22

C22

B21

A21

B20

C20

B19

A19

B18

C18

A17

B17

C16

B16

A15

B15

C14

B14

A13

B13

C12

B12

A11

B11

C10

B10

B8

A8

C6

B6

B5

A5

D4

B4

PEG_CTX _GRX_P15

PEG_CTX _GRX_N15

PEG_CTX _GRX_P14

PEG_CTX _GRX_N14

PEG_CTX _GRX_P13

PEG_CTX _GRX_N13

PEG_CTX _GRX_P12

PEG_CTX _GRX_N12

PEG_CTX _GRX_P11

PEG_CTX _GRX_N11

PEG_CTX _GRX_P10

PEG_CTX _GRX_N10

PEG_CTX _GRX_P9

PEG_CTX _GRX_N9

PEG_CTX _GRX_P8

PEG_CTX _GRX_N8

PEG_CTX _GRX_P7

PEG_CTX _GRX_N7

PEG_CTX _GRX_P6

PEG_CTX _GRX_N6

PEG_CTX _GRX_P5

PEG_CTX _GRX_N5

PEG_CTX _GRX_P4

PEG_CTX _GRX_N4

PEG_CTX _GRX_P3

PEG_CTX _GRX_N3

PEG_CTX _GRX_P2

PEG_CTX _GRX_N2

PEG_CTX _GRX_P1

PEG_CTX _GRX_N1

PEG_CTX _GRX_P0

PEG_CTX _GRX_N0

DMI_CTX_P RX_P0
DMI_CTX_P RX_N0

DMI_CTX_P RX_P1
DMI_CTX_P RX_N1

DMI_CTX_P RX_P2
DMI_CTX_P RX_N2

DMI_CTX_P RX_P3
DMI_CTX_P RX_N3

12

CC20.22U_02 01_6.3V6M VGA@

12

CC40.22U_02 01_6.3V6M VGA@

12

CC110.22U_02 01_6.3V6M VGA@

12

CC120.22U_02 01_6.3V6M VGA@

12

CC130.22U_02 01_6.3V6M VGA@

12

CC150.22U_02 01_6.3V6M VGA@

12

CC80.22U_02 01_6.3V6M VGA@

12

CC180.22U_02 01_6.3V6M VGA@

12

CC90.22U_02 01_6.3V6M VGA@

12

CC210.22U_02 01_6.3V6M VGA@

12

CC220.22U_02 01_6.3V6M VGA@

12

CC240.22U_02 01_6.3V6M VGA@

12

CC260.22U_02 01_6.3V6M VGA@

12

CC280.22U_02 01_6.3V6M VGA@

12

CC300.22U_02 01_6.3V6M VGA@

12

CC320.22U_02 01_6.3V6M VGA@

12

CC340.22U_02 01_6.3V6M VGA@

12

CC360.22U_02 01_6.3V6M VGA@

12

CC380.22U_02 01_6.3V6M VGA@

12

CC400.22U_02 01_6.3V6M VGA@

12

CC420.22U_02 01_6.3V6M VGA@

12

CC440.22U_02 01_6.3V6M VGA@

12

CC460.22U_02 01_6.3V6M VGA@

12

CC480.22U_02 01_6.3V6M VGA@

12

CC500.22U_02 01_6.3V6M VGA@

12

CC520.22U_02 01_6.3V6M VGA@

12

CC540.22U_02 01_6.3V6M VGA@

12

CC560.22U_02 01_6.3V6M VGA@

12

CC580.22U_02 01_6.3V6M VGA@

12

CC600.22U_02 01_6.3V6M VGA@

12

CC620.22U_02 01_6.3V6M VGA@

12

CC640.22U_02 01_6.3V6M VGA@

DMI_CTX_P RX_P0 <14>

DMI_CTX_P RX_N0 <14 >

DMI_CTX_P RX_P1 <14>

DMI_CTX_P RX_N1 <14 >

DMI_CTX_P RX_P2 <14>

DMI_CTX_P RX_N2 <14 >

DMI_CTX_P RX_P3 <14>

DMI_CTX_P RX_N3 <14 >

PEG_CTX _C_GRX_P15 <2 5>

PEG_CTX _C_GRX_N15 <25>

PEG_CTX _C_GRX_P14 <2 5>

PEG_CTX _C_GRX_N14 <25>

PEG_CTX _C_GRX_P13 <2 5>

PEG_CTX _C_GRX_N13 <25>

PEG_CTX _C_GRX_P12 <2 5>

PEG_CTX _C_GRX_N12 <25>

PEG_CTX _C_GRX_P11 <2 5>

PEG_CTX _C_GRX_N11 <25>

PEG_CTX _C_GRX_P10 <2 5>

PEG_CTX _C_GRX_N10 <25>

PEG_CTX _C_GRX_P9 <25 >

PEG_CTX _C_GRX_N9 <25>

PEG_CTX _C_GRX_P8 <25 >

PEG_CTX _C_GRX_N8 <25>

PEG_CTX _C_GRX_P7 <25 >

PEG_CTX _C_GRX_N7 <25>

PEG_CTX _C_GRX_P6 <25 >

PEG_CTX _C_GRX_N6 <25>

PEG_CTX _C_GRX_P5 <25 >

PEG_CTX _C_GRX_N5 <25>

PEG_CTX _C_GRX_P4 <25 >

PEG_CTX _C_GRX_N4 <25>

PEG_CTX _C_GRX_P3 <25 >

PEG_CTX _C_GRX_N3 <25>

PEG_CTX _C_GRX_P2 <25 >

PEG_CTX _C_GRX_N2 <25>

PEG_CTX _C_GRX_P1 <25 >

PEG_CTX _C_GRX_N1 <25>

PEG_CTX _C_GRX_P0 <25 >

PEG_CTX _C_GRX_N0 <25>

To PCH

To DGPU
PEG Lane Reversed

4 4

Security Classification

Security Classification

Security Classification

2019/12/ 28 2019/12/ 28

2019/12/ 28 2019/12/ 28

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

2019/12/ 28 2019/12/ 28

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

CFL-H(4/8)PEG/DMI

CFL-H(4/8)PEG/DMI

CFL-H(4/8)PEG/DMI

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

EH50F M/B LA-H431PR10

EH50F M/B LA-H431PR10

EH50F M/B LA-H431PR10

Date : S heet o f

Date : S heet o f

D

Date : S heet o f

9 1 00Wednesd ay, February 13, 201 9

9 1 00Wednesd ay, February 13, 201 9

9 1 00Wednesd ay, February 13, 201 9

E

1.0

1.0

1.0

C

UC1E

BCLKP

BCLKN

PCI_BCLKP

PCI_BCLKN

CLK24P

CLK24N

VIDALERT#

VIDSCK

VIDSOUT

PROCHOT#

DDR_VTT_CNTL

VCCST_PWRGD

PROCPWRGD

RESET#

PM_SYNC

PM_DOWN
PECI

THERMTRIP#

SKTOCC#

PROC_SELECT#

CATERR#

ZVM#

MSM#

RSVD1

RSVD2

CFL-H_BG A1440

+1.2V_VD DQ

SM_PG_C TRL

CFL-H

PROC_TDO

PROC_TDI

PROC_TMS

PROC_TCK

PROC_TRST#

PROC_PREQ#

PROC_PRDY#

CFG_RCOMP

5 OF 13

CC69

12

0.1U_020 1_10V6K

BN25

CFG_0

BN27

CFG_1

BN26

CFG_2

BN28

CFG_3

BR20

CFG_4

BM20

CFG_5

BT20

CFG_6

BP20

CFG_7

BR23

CFG_8

BR22

CFG_9

BT23

CFG_10

BT22

CFG_11

BM19

CFG_12

BR19

CFG_13

BP19

CFG_14

BT19

CFG_15

BN23

CFG_17

BP23

CFG_16

BP22

CFG_19

BN22

CFG_18

BR27

BPM#_0

BT27

BPM#_1

BM31

BPM#_2

BT30

BPM#_3

BT28

BL32

BP28

BR28

BP30

BL30

BP27

CFG_RCO MP

BT25

+3VS

12

PU 330K follow CRB
8/21

CFG0

CFG2

CFG3

CFG4

CFG5
CFG6

CFG7

XDP_BPM #0

XDP_BPM #1
XDP_BPM #2

XDP_BPM #3

CPU_XDP _TDO

CPU_XDP _TDI

CPU_XDP _TMS
CPU_XDP _TCK0

CPU_XDP _TRST#

XDP_PRE Q#

XDP_PRD Y#

RC18

1 2

Trace Width/Space: 4 mil/ 12 mil
Max Trace Length: 600 mil

RC23
330K_04 02_5%

PCH_CPU _24M_CLK_P<15>
PCH_CPU _24M_CLK_N<15>

PCH_CPU _PCIBCLK_P<15>

PCH_CPU _PCIBCLK_N<1 5>

PCH_CPU _BCLK_P<15>
PCH_CPU _BCLK_N<15>

CPU_SVID_ CLK<89>

RC17 0_0402_ 5%@

B

1 2

PCH_CPU _BCLK_P
PCH_CPU _BCLK_N

PCH_CPU _PCIBCLK_P
PCH_CPU _PCIBCLK_N

PCH_CPU _24M_CLK_P
PCH_CPU _24M_CLK_N

TP@

TC5

TC6TP@

CPU_SVID_ ALERT#

CPU_SVID_ CLK

CPU_SVID_ DAT

H_PROCH OT#_R

DDR_PG_ CTRL

EC_VCCS T_PG

H_CPUPW RGD
H_PLTRS T_CPU#

H_PM_SYNC _R
H_PM_DO WN

H_PECI
H_THERM TRIP#

SKTOCC#

CATERR#

BH31

BH32

BH29

BR30

BT13

BT31

BP35

BM34
BP31

BT34

BR33

BN1

BM30

AT13

AW13

AU13

AY13

B31

A32

D35

C36

E31

D31

H13

J31

A

571391_CFL_H_PDG_Rev0p5

1. The total Length of Data and Clock (from CPU to each VR) must be equal (± 0.1 inch).

2. Route the Alert signal between the Clock and the Data signals.

1 1

3. Place those resistors close CPU side.

Sensitive

Sensitive

H_CPUPW RGD<18>

H_PLTRS T_CPU#<17>
H_PM_SYNC _R<17>

H_PECI<17,58>

PCH_THE RMTRIP#_R<17>

PROC_S ELEC T#

2 2

should be unconnected on CFL processor
EDS1.2 8/21

XEMC@

1 2

EMC@

1 2

XEMC@

1 2

EMC@

1 2

CC65.1U_0402 _16V7K

CC661000P_0402 _50V7K

CC67.1U_0402 _16V7K

CC681000P_0402 _50V7K

H_CPUPW RGD

H_PROCH OT#_R

H_THERM TRIP#

EC_VCCS T_PG

Near CPU side

follow 1050 Request

+1.05V_V CCST

3 3

8/21

1 2

RH1 1K_040 2_5%

+1.05VS_ VCCSTG

12

RC21
1K_0402 _5%

H_THERM TRIP#

DDR_PG_ CTRL

NC

A

GND

UC3

VCC

Y

1

2

3

74AUP1G 07GW_TSSO P5

5

4

D

TC22 TP@

TP@

TC1

TC2 TP @

TC3 TP @

TC4 TP @

CPU_XDP _TDO <1 8>

CPU_XDP_TDI <18 >
CPU_XDP_TMS <18 >

CPU_XDP_TCK0 <18>

CPU_XDP_TRST# <21>

TC19 TP@

TC20 TP@

49.9_040 2_1%

SM_PG_C TRL <85>

+1.05VS_ VCCSTG

RC76 51_0402 _5%CMC@

RC77 51_0402 _5%CMC@

RC78 51_0402 _5%CMC@

RC79 51_0402 _5%CMC@

RC81 51_0402 _5%@

RC80 51_0402 _5%@

CFG0

CFG2
CFG4

CFG5

CFG6
CFG7

The CFG signals have a default value of '1' if not terminated on the board.

CFG[0]: Stall reset sequence after PCU PLL lock until de-asserted

1 = (Default) Normal Operation;

*

0 = Stall.

CFG[2]: PCI Express* Static x16 Lane Numbering Reversal.

1 = Normal operation
0 = Lane numbers reversed.

*

CFG[4]: eDP enable:

1 = Disabled.
0 = Enabled.

*

CFG[6:5]: PCI Express* Bifurcation:

00 = 1 x8, 2 x4 PCI Express*
01 = reserved
10 = 2 x8 PCI Express*
11 = 1 x16 PCI Express*

*

CFG[7]: PEG Training:

1 = (default) PEG Train immediately following RESET# de assertion.

*

0 = PEG Wait for BIOS for training.

*CFG Pin Use CMC debug on DDX03 R02 Schematic.

To be confirm

XDP_PRE Q#

XDP_PRD Y#

1 2

RC8 1K_040 2_5%

1 2

RC9 1K_040 2_5%

1 2

RC10 1K_0 402_5%@

1 2

RC11 1K_0 402_5%@

1 2

RC12 1K_0 402_5%@

1 2

RC7 1K_040 2_5%@

Place to CPU side

12

12

12

CPU_XDP _TMS

CPU_XDP _TDI

CPU_XDP _TDO

Place to CPU side

12

12

12

CPU_XDP _TCK0

CPU_XDP _TRST#

PCH_JTA G_TCK1

Place to PCH side

E

XDP_PREQ# <21>

XDP_PRD Y# <21>

PCH_JTA G_TCK1 <18 >

SVID

1 2

H_PROCH OT#<58,83>

EC_VCCS T_PG_R<58,78>

H_PM_DO WN_R<17>

4 4

A

RC14 499_ 0402_1%

+1.05V_V CCST

12

RC22
1K_0402 _5%

1 2

RC15 60.4_040 2_1%

1 2

RC16 20_0 402_5%

12

RH2

@

13_0402 _5%

H_PROCH OT#_R

+1.05V_V CCST

12

12

RC19

Issued Date

Issued Date

Issued Date

56_0402 _1%

EC_VCCS T_PG

H_PM_DO WN CPU_SVID_ ALERT#

B

CPU_SVID_ALERT#_R<89>

CPU_SVID_ DAT<89>

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

RC20
100_040 2_1%

1 2

RC13 220_ 0402_5%

CPU_SVID_ DAT

Compal Secret Data

Compal Secret Data

2019/12/ 28 2019/12/ 28

2019/12/ 28 2019/12/ 28

2019/12/ 28 2019/12/ 28

C

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

CFL-H(5/8)CFG,SVID

CFL-H(5/8)CFG,SVID

CFL-H(5/8)CFG,SVID

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

EH50F M/B LA-H431PR10

EH50F M/B LA-H431PR10

EH50F M/B LA-H431PR10

Date : Sheet o f

Date : Sheet o f

D

Date : Sheet o f

10 100Wednesd ay, February 13, 201 9

10 100Wednesd ay, February 13, 201 9

10 100Wednesd ay, February 13, 201 9

E

1.0

1.0

1.0

A

B

C

D

E

GT
32000mA(Hexa Core GT2)

AT14

AT31

AT32

AT33

AT34

AT35

AT36

AT37

1 1

2 2

3 3

4 4

AT38

AU14

AU29

AU30

AU31

AU32

AU35

AU36

AU37

AU38

AV29

AV30

AV31

AV32

AV33

AV34

AV35

AV36

AW14

AW31

AW32

AW33

AW34

AW35

AW36

AW37

AW38

AY29

AY30

AY31

AY32

AY35

AY36

AY37

AY38

BA13

BA14

BA29

BA30

BA31

BA32

BA33

BA34

BA35

BA36

BB13

BB14

BB31

BB32

BB33

BB34

BB35

BB36

BB37

BB38

BC29
BC30

BC31
BC32

BC35
BC36

BC37
BC38

BD13
BD14

BD29
BD30

BD31
BD32

BD33
BD34

BP37

BP38
BR15

BR16
BR17

CFL-H

UC1K

VCCGT1

VCCGT2

VCCGT3

VCCGT4

VCCGT5

VCCGT6

VCCGT7

VCCGT8

VCCGT9

VCCGT10

VCCGT11

VCCGT12

VCCGT13

VCCGT14

VCCGT15

VCCGT16

VCCGT17

VCCGT18

VCCGT19

VCCGT20

VCCGT21

VCCGT22

VCCGT23

VCCGT24

VCCGT25

VCCGT26

VCCGT27

VCCGT28

VCCGT29

VCCGT30

VCCGT31

VCCGT32

VCCGT33

VCCGT34

VCCGT35

VCCGT36

VCCGT37

VCCGT38

VCCGT39

VCCGT40

VCCGT41

VCCGT42

VCCGT43

VCCGT44

VCCGT45

VCCGT46

VCCGT47

VCCGT48

VCCGT49

VCCGT50

VCCGT51

VCCGT52

VCCGT53

VCCGT54

VCCGT55

VCCGT56

VCCGT57

VCCGT58

VCCGT59

VCCGT60

VCCGT61

VCCGT62

VCCGT63
VCCGT64

VCCGT65
VCCGT66

VCCGT67
VCCGT68

VCCGT69
VCCGT70

VCCGT71
VCCGT72

VCCGT73
VCCGT74

VCCGT75
VCCGT76

VCCGT77
VCCGT78

VCCGT79

VCCGT159
VCCGT160

VCCGT161
VCCGT162

VCCGT163

11 OF 13

CFL-H_BG A1440

+VCC_GT+VCC_GT

BD35

VCCGT80

BD36

VCCGT81

BE31

VCCGT82

BE32

VCCGT83

BE33

VCCGT84

BE34

VCCGT85

BE35

VCCGT86

BE36

VCCGT87

BE37

VCCGT88

BE38

VCCGT89

BF13

VCCGT90

BF14

VCCGT91

BF29

VCCGT92

BF30

VCCGT93

BF31

VCCGT94

BF32

VCCGT95

BF35

VCCGT96

BF36

VCCGT97

BF37

VCCGT98

BF38

VCCGT99

BG29

VCCGT100

BG30

VCCGT101

BG31

VCCGT102

BG32

VCCGT103

BG33

VCCGT104

BG34

VCCGT105

BG35

VCCGT106

BG36

VCCGT107

BH33

VCCGT108

BH34

VCCGT109

BH35

VCCGT110

BH36

VCCGT111

BH37

VCCGT112

BH38

VCCGT113

BJ16

VCCGT114

BJ17

VCCGT115

BJ19

VCCGT116

BJ20

VCCGT117

BJ21

VCCGT118

BJ23

VCCGT119

BJ24

VCCGT120

BJ26

VCCGT121

BJ27

VCCGT122

BJ37

VCCGT123

BJ38

VCCGT124

BK16

VCCGT125

BK17

VCCGT126

BK19

VCCGT127

BK20

VCCGT128

BK21

VCCGT129

BK23

VCCGT130

BK24

VCCGT131

BK26

VCCGT132

BK27

VCCGT133

BL15

VCCGT134

BL16

VCCGT135

BL17

VCCGT136

BL23

VCCGT137

BL24

VCCGT138

BL25

VCCGT139

BL26

VCCGT140

BL27

VCCGT141

BL28

VCCGT142

BL36

VCCGT143

BL37

VCCGT144

BM15

VCCGT145

BM16

VCCGT146

BM17

VCCGT147

BM36

VCCGT148

BM37

VCCGT149

BN15

VCCGT150

BN16

VCCGT151

BN17

VCCGT152

BN36

VCCGT153

BN37

VCCGT154

BN38

VCCGT155

BP15

VCCGT156

BP16

VCCGT157

BP17

VCCGT158

BR37

VCCGT164

BT15

VCCGT165

BT16

VCCGT166

BT17

VCCGT167

BT37

VCCGT168

VSSGT_S ENSE

VSSGT_SENSE
VCCGT_SENSE

AH37

VCCGT_S ENSE

AH38

1. VccGT_S ENSE / VssGT_SENSE Trace Lengt h Match < 25 mils

2. Ma intain 25-mil sep aration distance away f rom any oth er d ynamic signals.

+VCC_CO RE +VCC_CO RE

AA13

AA31

AA32

AA33

AA34

AA35

AA36

AA37

AA38

AB29

AB30

AB31

AB32

AB35

AB36

AB37

AB38

AC13

AC14

AC29

AC30

AC31

AC32

AC33

AC34

AC35

AC36

AD13

AD14

AD31

AD32

AD33

AD34

AD35

AD36

AD37

AD38

AE13

AE14

AE30

AE31

AE32

AE35

AE36

AE37

AE38

AF29

AF30

AF31

AF32

AF33

AF34

AF35

AF36

AF37

AF38

AG14

AG31

AG32

AG33

AG34

AG35

AG36

CFL-H_BG A1440

VSSGT_S ENSE <89 >

VCCGT_S ENSE <89>

UC1I

VCC1

VCC2

VCC3

VCC4

VCC5

VCC6

VCC7

VCC8

VCC9

VCC10

VCC11

VCC12

VCC13

VCC14

VCC15

VCC16

VCC17

VCC18

VCC19

VCC20

VCC21

VCC22

VCC23

VCC24

VCC25

VCC26

VCC27

VCC28

VCC29

VCC30

VCC31

VCC32

VCC33

VCC34

VCC35

VCC36

VCC37

VCC38

VCC39

VCC40

VCC41

VCC42

VCC43

VCC44

VCC45

VCC46

VCC47

VCC48

VCC49

VCC50

VCC51

VCC52

VCC53

VCC54

VCC55

VCC56

VCC57

VCC58

VCC59

VCC60

VCC61

VCC62

VCC63

CFL-H

AH13

VCC64

AH14

VCC65

AH29

VCC66

AH30

VCC67

AH31

VCC68

AH32

VCC69

AJ14

VCC70

AJ29

VCC71

AJ30

VCC72

AJ31

VCC73

AJ32

VCC74

AJ33

VCC75

AJ34

VCC76

AJ35

VCC77

AJ36

VCC78

AK31

VCC79

AK32

VCC80

AK33

VCC81

AK34

VCC82

AK35

VCC83

AK36

VCC84

AK37

VCC85

AK38

VCC86

AL13

VCC87

AL29

VCC88

AL30

VCC89

AL31

VCC90

AL32

VCC91

AL35

VCC92

AL36

VCC93

AL37

VCC94

AL38

VCC95

AM13

VCC96

AM14

VCC97

AM29

VCC98

AM30

VCC99

AM31

VCC100

AM32

VCC101

AM33

VCC102

AM34

VCC103

AM35

VCC104

AM36

VCC105

AN13

VCC106

AN14

VCC107

AN31

VCC108

AN32

VCC109

AN33

VCC110

AN34

VCC111

AN35

VCC112

AN36

VCC113

AN37

VCC114

AN38

VCC115

AP13

VCC116

AP30

VCC117

AP31

VCC118

AP32

VCC119

AP35

VCC120

AP36

VCC121

AP37

VCC122

AP38

VCC123

K13

VCC124

VCC_SENSE

9 OF 13

VSS_SENSE

1. Vcc_S ENSE/ Vss _SENSE Tr ace Length Match < 25 mils

2. Ma intain 25-mil sep aration distance away f rom any oth er d ynamic signals.

AG37

AG38

128000mA(Hexa Core GT2)

VCCSENS E
VSSSENS E

VCCSENS E <89>

VSSSENS E <89>

+VCC_CO RE +VCC_CO RE

K14

L13

L14

N13

N14

N30

N31

N32

N35

N36

N37

N38

P13

P14

P29

P30

P31

P32

P33

P34

P35

P36

R13

R31

R32

R33

R34

R35

R36

R37

R38

T29

T30

T31

T32

T35

T36

T37

T38

U29

U30

U31

U32

U33

U34

U35

U36

V13

V14

V31

V32

V33

V34

V35

V36

V37

V38

W13

W14

W29

W30

W31

W32

CFL-H_BG A1440

UC1J

VCC1

VCC2

VCC3
VCC4

VCC5

VCC6

VCC7

VCC8

VCC9

VCC10

VCC11

VCC12

VCC13

VCC14

VCC15

VCC16

VCC17

VCC18

VCC19

VCC20

VCC21

VCC22

VCC23

VCC24

VCC25

VCC26

VCC27

VCC28

VCC29

VCC30

VCC31

VCC32

VCC33

VCC34

VCC35

VCC36

VCC37

VCC38

VCC39

VCC40

VCC41

VCC42

VCC43

VCC44

VCC45

VCC46

VCC47

VCC48

VCC49

VCC50

VCC51

VCC52

VCC53

VCC54

VCC55

VCC56

VCC57

VCC58

VCC59

VCC60

VCC61

VCC62

VCC63

CFL-H

10 OF 13

VCC64

VCC65

VCC66

VCC67

VCC68

VCC69

VCC70

VCC71

VCC72

VCC73

VCC74

VCC75

W35

W36

W37

W38

Y29

Y30

Y31

Y32

Y33

Y34

Y35

Y36

Security Classification

Security Classification

Security Classification

2019/12/ 28 2019/12/ 28

2019/12/ 28 2019/12/ 28

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

2019/12/ 28 2019/12/ 28

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

CFL-H(6/8)VCC_CORE/GT

CFL-H(6/8)VCC_CORE/GT

CFL-H(6/8)VCC_CORE/GT

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

EH50F M/B LA-H431PR10

EH50F M/B LA-H431PR10

EH50F M/B LA-H431PR10

Date : Sheet o f

Date : Sheet o f

D

Date : Sheet o f

11 100Wednesd ay, February 13, 201 9

11 100Wednesd ay, February 13, 201 9

11 100Wednesd ay, February 13, 201 9

E

1.0

1.0

1.0

E

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

2

CC85

CC82

2

10U_0402_6.3V6M

1

2

1U_0201_6.3V6M

1

CC86

2

RC25 0_04 02_5%@

D

EH50F red-ink issue , 22uF 0603*2 change to 10uF 0402*4

1

CC78

2

1U_0201_6.3V6M

1

2

1 2

10U_0402_6.3V6M

10U_0402_6.3V6M

CC79

CC87

10U_0402_6.3V6M

1

1

CC80

CC81

2

2

+VCCIO

1

2

+1.05V_V CCSFR

150mA

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

1

1

2

CC84

CC83

2

10U_0402_6.3V6M

10U_0402_6.3V6M

1

1

CC89

CC88

2

2

571483_CFL_H_RVP_CRB_TDK_Rev0p5
+0.95VS_VCCIO: 10uF * 12 22uF * 4

1U_0201_6.3V6M

1

CC93

2

571483_CFL_H_RVP_CRB_TDK_Rev0p5
+1.05V_VCCSFR: 1uF * 1

10U_0402_6.3V6M

1

1

CC95

CC96

2

2

10U_0402_6.3V6M

10U_0402_6.3V6M

@

1

CC90

CC91

2

A

+1.2V_VDDQ_CPU
Max: 3300mA

+VCC_SA

+VCC_SA
Max: 11100mA

1 1

+VCC_IO
Max: 6400mA

2 2

+VCCIO

K29
K30

K31
K32

K33
K34

K35

M29

M30
M31

M32
M33

M34
M35

M36

AG12

G15
G17

G19
G21

H15
H16

H17
H19

H20
H21

H26
H27

J30

L31

L32
L35

L36
L37

L38

J15
J16

J17
J19

J20
J21

J26
J27

CFL-H_BG A1440

UC1L

VCCSA1
VCCSA2

VCCSA3
VCCSA4

VCCSA5
VCCSA6

VCCSA7
VCCSA8

VCCSA9
VCCSA10

VCCSA11
VCCSA12

VCCSA13
VCCSA14

VCCSA15
VCCSA16

VCCSA17
VCCSA18

VCCSA19
VCCSA20

VCCSA21
VCCSA22

VCCIO1
VCCIO2

VCCIO3
VCCIO4

VCCIO5
VCCIO6

VCCIO7
VCCIO8

VCCIO9
VCCIO10

VCCIO11
VCCIO12

VCCIO13
VCCIO14

VCCIO15
VCCIO16

VCCIO17
VCCIO18

VCCIO19
VCCIO20

VCCIO21

CFL-H

12 OF 13

VDDQ1

VDDQ2

VDDQ3

VDDQ4

VDDQ5

VDDQ6

VDDQ7

VDDQ8

VDDQ9

VDDQ10

VDDQ11

VDDQ12

VDDQ13

VDDQ14

VDDQ15
VDDQ16

VDDQ17

VDDQ18

VDDQ19

VDDQ20

VDDQ21

VDDQ22

VDDQ23

VDDQ24

VDDQ25

VCCPLL_OC1

VCCPLL_OC2

VCCPLL_OC3

VCCST

VCCSTG2

VCCSTG1

VCCPLL1

VCCPLL2

VCCSA_SENSE

VSSSA_SENSE

VCCIO_SENSE

VSSIO_SENSE

+1.2V_VD DQ_CPU

AA6

AE12

AF5

AF6

AG5

AG9

AJ12
AL11

AP6

AP7

AR12

AR6

AT12

AW6

AY6

J5

J6

K12

K6

L12

L6

R6

T6

W6

Y12

+1.2V_VC CPLL_OC

BH13

BJ13
G11

H30

H29

G30

H28

J28

M38

M37

H14

J14

B

+1.2V_VD DQ_CPU

1

1

JPC1

JPC2

2

2

+1.2V_VD DQ

2

2

VCCSA_S ENSE <89 >

VSSSA_S ENSE < 89>

VCCIO_SEN SE <8 8>

VSSIO_SEN SE <88>

+1.2V_VDDQ_CPU

3.3A

@

1

JUMP_43 X118

@

1

JUMP_43 X118

+1.2V_VCCPLL_OC
Max: 130mA

+1.05V_V CCST

Max: 60mA

Max: 20mA

Max: 150mA

VCCIO_SEN SE
VSSIO_SEN SE

1. VccGT_S ENSE / VssGT_SENSE Trace Lengt h Match < 25 mils

2. Ma intain 25-mil sep aration distance away f rom any oth er d ynamic signals.

+1.05VS_ VCCSTG

+1.05V_V CCSFR

VCCSA_S ENSE
VSSSA_S ENSE

C

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

1

1

CC70

2

2

571483_CFL_H_RVP_CRB_TDK_Rev0p5
+1.2V_VDDQ_CPU: 10uF * 12 22uF * 4

1

1

CC71

CC72

2

2

10U_0402_6.3V6M

1

CC73

2

+1.2V_VD DQ

RC24 0_0 402_5%@

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

1

1

CC74

CC75

CC76

2

2

PLACE CAP BACKSIDE

1 2

571483_CFL_H_RVP_CRB_TDK_Rev0p5
+1.2V_VCCPLL_OC: 1uF * 2

PLACE CAP BACKSIDE

+1.05V_V CCST

10U_0402_6.3V6M

1

CC77

2

+1.2V_VC CPLL_OC

1U_0201_6.3V6M

1

CC92

2

571483_CFL_H_RVP_CRB_TDK_Rev0p5
+1.05V_VCCST: 1uF * 1

PLACE CAP BACKSIDE PLACE CAP BACKSIDE

3 3

4 4

Security Classification

Security Classification

Security Classification

2019/12/ 28 2019/12/ 28

2019/12/ 28 2019/12/ 28

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

2019/12/ 28 2019/12/ 28

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

+1.05VS_ VCCSTG

1U_0201_6.3V6M

1

CC94

2

571483_CFL_H_RVP_CRB_TDK_Rev0p5
+1.05VS_VCCSTG: 1uF * 1

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

CFL-H(7/8)VCCSA/VCCIO/VDDQ

CFL-H(7/8)VCCSA/VCCIO/VDDQ

CFL-H(7/8)VCCSA/VCCIO/VDDQ

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

EH50F M/B LA-H431PR10

EH50F M/B LA-H431PR10

EH50F M/B LA-H431PR10

Date : Sheet o f

Date : Sheet o f

Date : Sheet o f

12 100Wednesd ay, February 13, 201 9

12 100Wednesd ay, February 13, 201 9

12 100Wednesd ay, February 13, 201 9

E

1.0

1.0

1.0

A

B

C

D

E

CFL-H

UC1F

A10

VSS_1

A12

VSS_2

A16

VSS_3

A18

VSS_4

A20

VSS_5

A22

VSS_6

A24

VSS_7

A26

VSS_8

1 1

2 2

3 3

A28

A30

AA12

AA29
AA30

AB33
AB34

AB6

AC1

AC12

AC2

AC3

AC37

AC38

AC4

AC5
AC6

AD10
AD11

AD12
AD29

AD30

AD6

AD8
AD9

AE33
AE34

AE6
AF1

AF12
AF13

AF14

AF2

AF3
AF4

AG10
AG11

AG13
AG29

AG30

AG6

AG7
AG8

AH12
AH33

AH34
AH35

AH36

AH6

AJ1

AJ13

AJ2
AJ3

AJ37
AJ38

AJ4
AJ5

AJ6

Y10

Y11
Y13

Y14
Y37

Y38

AK29
AK30

A6

A9

W4

W5

Y7

Y8
Y9

VSS_9
VSS_10

VSS_11
VSS_12

VSS_13
VSS_14

VSS_15
VSS_16

VSS_17
VSS_18

VSS_19
VSS_20

VSS_21
VSS_22

VSS_23
VSS_24

VSS_25
VSS_26

VSS_27
VSS_28

VSS_29
VSS_30

VSS_31
VSS_32

VSS_33
VSS_34

VSS_35
VSS_36

VSS_37
VSS_38

VSS_39
VSS_40

VSS_41
VSS_42

VSS_43
VSS_44

VSS_45
VSS_46

VSS_47
VSS_48

VSS_49
VSS_50

VSS_51
VSS_52

VSS_53
VSS_54

VSS_55
VSS_56

VSS_57
VSS_58

VSS_59
VSS_60

VSS_61
VSS_62

VSS_63
VSS_64

VSS_65
VSS_66

VSS_67
VSS_68

VSS_69
VSS_70

VSS_71
VSS_72

VSS_73
VSS_74

VSS_75
VSS_76

VSS_77
VSS_78

VSS_79
VSS_80

6 OF 13

VSS_81

CFL-H_BG A1440

VSS_82

VSS_83
VSS_84

VSS_85
VSS_86

VSS_87
VSS_88

VSS_89
VSS_90

VSS_91
VSS_92

VSS_93
VSS_94

VSS_95
VSS_96

VSS_97
VSS_98

VSS_99

VSS_100

VSS_101
VSS_102

VSS_103
VSS_104

VSS_105
VSS_106

VSS_107
VSS_108

VSS_109
VSS_110

VSS_111
VSS_112

VSS_113
VSS_114

VSS_115
VSS_116

VSS_117
VSS_118

VSS_119
VSS_120

VSS_121
VSS_122

VSS_123
VSS_124

VSS_125
VSS_126

VSS_127
VSS_128

VSS_129
VSS_130

VSS_131
VSS_132

VSS_133
VSS_134

VSS_135
VSS_136

VSS_137
VSS_138

VSS_139
VSS_140

VSS_141
VSS_142

VSS_143
VSS_144

VSS_145
VSS_146

VSS_147
VSS_148

VSS_149
VSS_150

VSS_151
VSS_152

VSS_153
VSS_154

VSS_155
VSS_156

VSS_157
VSS_158

VSS_159
VSS_160

VSS_161
VSS_162

AK4
AL10

AL12
AL14

AL33
AL34

AL4
AL7

AL8
AL9

AM1
AM12

AM2
AM3

AM37
AM38

AM4
AM5

AN12
AN29

AN30
AN5

AN6
AP10

AP11
AP12

AP33
AP34

AP8
AP9

AR1
AR13

AR14
AR2

AR29
AR3

AR30
AR31

AR32
AR33

AR34
AR35

AR36
AR37

AR38
AR4

AR5
AT29

AT30
AT6

AU10
AU11

AU12
AU33

AU34
AU6

AU7
AU8

AU9
AV37

AV38
AW1

AW12
AW2

AW29
AW3

AW30
AW4

U6
V12

V29
V30

A14
AD7

V6
W1

W12
W2

W3
W33

W34

AW5

AY12
AY33

AY34

BA10
BA11

BA12
BA37

BA38

BA6

BA7
BA8

BA9
BB1

BB12

BB2

BB29

BB3

BB30

BB4

BB5
BB6

BC12
BC13

BC14
BC33

BC34

BC6

BD10
BD11

BD12
BD37

BD6
BD7

BD8
BD9

BE1
BE2

BE29

BE3

BE30

BE4

BE5
BE6

BF12
BF33

BF34

BF6

BG12
BG13

BG14
BG37

BG38

BG6

BH1

BH10

BH11
BH12

BH14

BH2

BH3
BH4

BH5
BH6

BH7
BH8

BH9

T33

T34

U37
U38

BJ12
BJ14

UC1G

VSS_163
VSS_164

VSS_165
VSS_166

B9

VSS_167
VSS_168

VSS_169
VSS_170

VSS_171
VSS_172

VSS_173
VSS_174

VSS_175
VSS_176

VSS_177
VSS_178

VSS_179
VSS_180

VSS_181
VSS_182

VSS_183
VSS_184

VSS_185
VSS_186

VSS_187
VSS_188

VSS_189
VSS_190

VSS_191
VSS_192

VSS_193
VSS_194

VSS_195
VSS_196

VSS_197
VSS_198

VSS_199
VSS_200

VSS_201
VSS_202

VSS_203
VSS_204

VSS_205
VSS_206

VSS_207
VSS_208

VSS_209
VSS_210

VSS_211
VSS_212

VSS_213
VSS_214

VSS_215
VSS_216

VSS_217
VSS_218

VSS_219
VSS_220

VSS_221
VSS_222

VSS_223
VSS_224

VSS_225
VSS_226

VSS_227
VSS_228

VSS_229
VSS_230

T2

VSS_231

T3

VSS_232

VSS_233
VSS_234

T4

VSS_235

T5

VSS_236

T7

VSS_237

T8

VSS_238

T9

VSS_239
VSS_240

VSS_241
VSS_242

VSS_243

CFL-H_BG A1440

CFL-H

7 OF 13

VSS_244

VSS_245
VSS_246

VSS_247
VSS_248

VSS_249
VSS_250

VSS_251
VSS_252

VSS_253
VSS_254

VSS_255
VSS_256

VSS_257
VSS_258

VSS_259
VSS_260

VSS_261
VSS_262

VSS_263
VSS_264

VSS_265
VSS_266

VSS_267
VSS_268

VSS_269
VSS_270

VSS_271
VSS_272

VSS_273
VSS_274

VSS_275
VSS_276

VSS_277
VSS_278

VSS_279
VSS_280

VSS_281
VSS_282

VSS_283
VSS_284

VSS_285
VSS_286

VSS_287
VSS_288

VSS_289
VSS_290

VSS_291
VSS_292

VSS_293
VSS_294

VSS_295
VSS_296

VSS_297
VSS_298

VSS_299
VSS_300

VSS_301
VSS_302

VSS_303
VSS_304

VSS_305
VSS_306

VSS_307
VSS_308

VSS_309
VSS_310

VSS_311
VSS_312

VSS_313
VSS_314

VSS_315
VSS_316

VSS_317
VSS_318

VSS_319
VSS_320

VSS_321
VSS_322

VSS_323
VSS_324

BJ15
BJ18

BJ22
BJ25

BJ29
BJ30

BJ31
BJ32

BJ33
BJ34

BJ35
BJ36

BK13
BK14

BK15
BK18

BK22
BK25

BK29
BK6

BL13
BL14

BL18
BL19

BL20
BL21

BL22
BL29

BL33
BL35

BL38
BL6

BM11
BM12

BM13
BM14

BM18
BM2

BM21
BM22

BM23
BM24

BM25
BM26

BM27
BM28

BM29
BM3

BM33
BM35

BM38
BM5

BM6
BM7

BM8
BM9

BN12
BN14

BN18
BN19

BN2
BN20

BN21
BN24

BN29
BN30

BN31
BN34

P38
P6

R12
R29

AY14
BD38

R30
T1

T10
T11

T12
T13

T14

BN4

BN7

BP12

BP14
BP18

BP21
BP24

BP25
BP26

BP29
BP33

BP34

BP7

BR12
BR14

BR18
BR21

BR24
BR25

BR26
BR29

BR34
BR36

BR7

BT12

BT14
BT18

BT21
BT24

BT26
BT29

BT32

BT5

C11
C13

C15
C17

C19
C21

C23
C25

C27
C29

C31
C37

D10

D12
D14

D16
D18

D20
D22

D24
D26

D28

D30
D33

E34
E35

E38

N33
N34

P12
P37

M14

M6

F11

F13

UC1H

VSS_325
VSS_326

VSS_327
VSS_328

VSS_329
VSS_330

VSS_331
VSS_332

VSS_333
VSS_334

VSS_335
VSS_336

VSS_337
VSS_338

VSS_339
VSS_340

VSS_341
VSS_342

VSS_343
VSS_344

VSS_345
VSS_346

VSS_347
VSS_348

VSS_349
VSS_350

VSS_351
VSS_352

VSS_353
VSS_354

VSS_355
VSS_356

VSS_357
VSS_358

VSS_359
VSS_360

VSS_361
VSS_362

VSS_363
VSS_364

VSS_365
VSS_366

VSS_367
VSS_368

VSS_369

C5

VSS_370

C8

VSS_371

C9

VSS_372

VSS_373
VSS_374

VSS_375
VSS_376

VSS_377
VSS_378

VSS_379
VSS_380

VSS_381
VSS_382

D3

VSS_383
VSS_384

VSS_385

D6

VSS_386

D9

VSS_387
VSS_388

VSS_389
VSS_390

E4

VSS_391

E9

VSS_392

N3

VSS_393
VSS_394

VSS_395

N4

VSS_396

N5

VSS_397

N6

VSS_398

N7

VSS_399

N8

VSS_400

N9

VSS_401
VSS_402

VSS_403
VSS_404

VSS_405

N1

VSS_406

VSS_407
VSS_408

CFL-H_BG A1440

CFL-H

VSS_409
VSS_410

VSS_411
VSS_412

VSS_413
VSS_414

VSS_415
VSS_416

VSS_417
VSS_418

VSS_419
VSS_420

VSS_421
VSS_422

VSS_423
VSS_424

VSS_425
VSS_426

VSS_427
VSS_428

VSS_429
VSS_430

VSS_431
VSS_432

VSS_433
VSS_434

VSS_435
VSS_436

VSS_437
VSS_438

VSS_439
VSS_440

VSS_441
VSS_442

VSS_443
VSS_444

VSS_445
VSS_446

VSS_447
VSS_448

VSS_449
VSS_450

VSS_451
VSS_452

VSS_453
VSS_454

VSS_455
VSS_456

VSS_457
VSS_458

VSS_459
VSS_460

VSS_461
VSS_462

VSS_463
VSS_464

VSS_465
VSS_466

VSS_467
VSS_468

VSS_469
VSS_470

VSS_471
VSS_472

VSS_473
VSS_474

VSS_475
VSS_476

VSS_477
VSS_478

VSS_479

VSS_A34

VSS_B37

VSS_BR38

VSS_BT3

VSS_BT35

VSS_BT36

VSS_BT4

8 OF 13

VSS_D38

VSS_A3

VSS_A4

VSS_B3

VSS_C2

F15

F17
F19

F2
F21

F23
F25

F27
F29

F3
F31

F36
F4

F5
F8

F9
G10

G12
G14

G16
G18

G20
G22

G23
G24

G26
G28

G4
G5

G6
G8

G9
H11

H12
H18

H22
H25

H32
H35

J10
J18

J22
J25

J32
J33

J36
J4

J7
K1

K10
K11

K2
K3

K38
K4

K5
K7

K8
K9

L29
L30

L33
L34

M12
M13

N10
N11

N12
N2

BT8
BR9

A3

A34
A4

B3

B37
BR38

BT3

BT35
BT36

BT4

C2
D38

Impedance Spectrum Tool Trigger

PCH_TRIGO UT_R<21>

CPU_TRIGO UT_R<21>

1 2

RC26 30_0 402_5%

TC7TP@

TC8TP@

TC9TP@

TC10TP @

TP@

TC11

TC12TP @

PCH_TRIGO UT_R
CPU_TRIGO UT

IST_TRIG

BR1

BN35

BN33

BL34

N29

R14

AE29

AA14

AP29

AP14

H23

C30

BR35

BR31
BH30

BT2

H24

A36

A37

F30

E30

B30

E2

E3

E1

D1

J24

J23

G3

J3

UC1M

RSVD_TP5

IST_TRIG

RSVD_TP4

RSVD_TP3

RSVD_TP1

RSVD_TP2

RSVD15

RSVD28

RSVD27

RSVD14

RSVD13

RSVD30

RSVD31

RSVD2

RSVD1

RSVD5

RSVD4

VSS_A36

VSS_A37

PROC_TRIGIN

PROC_TRIGOUT

RSVD24

RSVD23

RSVD7

RSVD21

RSVD26

RSVD29

RSVD19

RSVD18

RSVD9

CFL-H_BG A1440

CFL-H

13 OF 13

BK28

RSVD11

BJ28

RSVD10

BL31

RSVD12

AJ8

RSVD3

G13

RSVD25

C38

RSVD22

C1

RSVD20

BR2

RSVD17

BP1

RSVD16

B38

RSVD8

B2

RSVD6

Add for Corner NCTF testing

TC13 TP@

TC14 TP@

TP@

TC15

TP@

TC16

TP@

TC17

TP@

TC18

4 4

Security Classification

Security Classification

Security Classification

2019/12/ 28 2019/12/ 28

2019/12/ 28 2019/12/ 28

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

2019/12/ 28 2019/12/ 28

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

CFL-H(8/8)GND/RSVD

CFL-H(8/8)GND/RSVD

CFL-H(8/8)GND/RSVD

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

EH50F M/B LA-H431PR10

EH50F M/B LA-H431PR10

EH50F M/B LA-H431PR10

Date : Sheet o f

Date : Sheet o f

D

Date : Sheet o f

13 100Wednesd ay, February 13, 201 9

13 100Wednesd ay, February 13, 201 9

13 100Wednesd ay, February 13, 201 9

E

1.0

1.0

1.0

A

DMI_CTX_P RX_N0<9>

DMI_CTX_P RX_P0< 9>

DMI_CRX_P TX_N0<9>

DMI_CRX_P TX_P0< 9>

DMI_CTX_P RX_N1<9>

DMI_CTX_P RX_P1< 9>

DMI_CRX_P TX_N1<9>

DMI_CRX_P TX_P1< 9>

DMI_CTX_P RX_N2<9>

DMI_CTX_P RX_P2< 9>

1 1

The 30 HSIO lanes on PCH-H supports the following configurations:

1. Up to 24 PCIe* Lanes

— A maximum of 16 PCIe* Ports (or devices) can be enabled

When a GbE Port is enabled, the maximum number of PCIe* Ports (or

‧

devices) that can be enabled reduces based off the following:
Max PCIe* Ports (or devices) = 16 - GbE (0 or 1)
— PCIe* Lanes 1-4 (PCIe* Controller #1), 5-8 (PCIe* Controller #2), 9-12 (PCIe*
Controller #3), 13-16 (PCIe* Controller #4), 17-20 (PCIe* Controller #5), and
21-24 (PCIe* Controller #6) can be individually configured

2. Up to 6 SATA Lanes
— A maximum of 6 SATA Ports (or devices) can be enabled
— SATA Lane 0 has the flexibility to be mapped to Flex I/O Lane 16 or 18
— SATA Lane 1 has the flexibility to be mapped to Flex I/O Lane 17 or 19

3. Up to 10 USB 3.1 Lanes
— A maximum of 10 USB 3.1 Ports (or devices) can be enabled

4. Up to 4 GbE Lanes
— A maximum of 1 GbE Port (or device) can be enabled

5. Supports up to 3 Remapped (IntelR Rapid Storage Technology) PCIe* storage
devices
— x2 and x4 PCIe* NVMe SSD
— x2 IntelR Optane? Memory Device
— See the “ PC I Express* (PCIe*)” chapt er for t he P CH PCIe* Controllers,configurations
, and lanes that can be used for IntelR Rapid Storage Technology PCIe* storage support

6. For unused SATA/PCIe* Combo Lanes, Flex I/O Lanes that can be configured as PCIe* or SATA,
the lanes must be statically assigned to SATA or PCIe* via the SATA/PCIe Combo Port Soft
Straps discussed in the SPI Programming Guide and
through the IntelR Flash Image Tool (FIT) tool.

2 2

3 3

DMI_CRX_P TX_N2<9>

DMI_CRX_P TX_P2< 9>

DMI_CTX_P RX_N3<9>

DMI_CTX_P RX_P3< 9>

DMI_CRX_P TX_N3<9>

DMI_CRX_P TX_P3< 9>

B

DMI_CTX_P RX_N0
DMI_CTX_P RX_P0

DMI_CRX_P TX_N0
DMI_CRX_P TX_P0

DMI_CTX_P RX_N1
DMI_CTX_P RX_P1

DMI_CRX_P TX_N1
DMI_CRX_P TX_P1

DMI_CTX_P RX_N2
DMI_CTX_P RX_P2

DMI_CRX_P TX_N2
DMI_CRX_P TX_P2

DMI_CTX_P RX_N3
DMI_CTX_P RX_P3

DMI_CRX_P TX_N3
DMI_CRX_P TX_P3

UH1B

K34

DMI0_RXN

J35

DMI0_RXP

C33

DMI0_TXN

B33

DMI0_TXP

G33

DMI1_RXN

F34

DMI1_RXP

C32

DMI1_TXN

B32

DMI1_TXP

K32

DMI2_RXN

J32

DMI2_RXP

C31

DMI2_TXN

B31

DMI2_TXP

G30

DMI3_RXN

F30

DMI3_RXP

C29

DMI3_TXN

B29

DMI3_TXP

A25

RSVD

B25

RSVD

P24

RSVD

R24

RSVD

C26

RSVD

B26

RSVD

F26

RSVD

G26

RSVD

B27

RSVD

C27

RSVD

L26

RSVD

M26

RSVD

D29

RSVD

E28

RSVD

K29

RSVD

M29

RSVD

G17

PCIE1_RXN/USB31_7_RXN

F16

PCIE1_RXP/USB31_7_RXP

A17

PCIE1_TXN/USB31_7_TXN

B17

PCIE1_TXP/USB31_7_TXP

R21

PCIE2_RXN/USB31_8_RXN

P21

PCIE2_RXP/USB31_8_RXP

B18

PCIE2_TXN/USB31_8_TXN

C18

PCIE2_TXP/USB31_8_TXP

K18

PCIE3_RXN/USB31_9_RXN

J18

PCIE3_RXP/USB31_9_RXP

B19

PCIE3_TXN/USB31_9_TXN

C19

PCIE3_TXP/USB31_9_TXP

N18

PCIE4_RXN/USB31_10_RXN

R18

PCIE4_RXP/USB31_10_RXP

D20

PCIE4_TXN/USB31_10_TXN

C20

PCIE4_TXP/USB31_10_TXP

F20

PCIE5_RXN

G20

PCIE5_RXP

B21

PCIE5_TXN

A22

PCIE5_TXP

K21

PCIE6_RXN

J21

PCIE6_RXP

D21

PCIE6_TXN

C21

PCIE6_TXP

B23

PCIE7_TXP

C23

PCIE7_TXN

J24

PCIE7_RXP

L24

PCIE7_RXN

F24

PCIE8_RXN

G24

PCIE8_RXP

B24

PCIE8_TXN

C24

PCIE8_TXP

CNP-H_BG A874

C

CNP-H

GPP_E9/USB2_OC0#

GPP_E10/USB2_OC1#

GPP_E11/USB2_OC2#

GPP_E12/USB2_OC3#

GPP_F15/USB2_OC4#

GPP_F16/USB2_OC5#

GPP_F17/USB2_OC6#

GPP_F18/USB2_OC7#

USB2_VBUSSENSE

2 OF 13

USB2N_1
USB2P_1

USB2N_2
USB2P_2

USB2N_3
USB2P_3

USB2N_4
USB2P_4

USB2N_5
USB2P_5

USB2N_6
USB2P_6

USB2N_7
USB2P_7

USB2N_8
USB2P_8

USB2N_9
USB2P_9

USB2N_10
USB2P_10

USB2N_11
USB2P_11

USB2N_12
USB2P_12

USB2N_13
USB2P_13

USB2N_14
USB2P_14

USB2_COMP

RSVD1

USB2_ID

GPD7

PCIE24_TXP

PCIE24_TXN

PCIE24_RXP

PCIE24_RXN

PCIE23_TXP

PCIE23_TXN

PCIE23_RXP

PCIE23_RXN

PCIE22_TXP

PCIE22_TXN

PCIE22_RXP

PCIE22_RXN

PCIE21_TXP

PCIE21_TXN

PCIE21_RXP

PCIE21_RXN

Rev1.0

J3

J2
N13

N15
K4

K3
M10

L9
M1

L2
K7

K6
L4

L3
G4

G5
M6

N8
H3

H2
R10

P9
G1

G2
N3

N2
E5

F6

AH36

AL40

AJ44

AL41

AV47

AR35

AR37

AV43

F4

F3

U13

G3

BE41

G45

G46

Y41

Y40

G48

G49

W44

W43

H48

H47

U41

U40

F46

G47

R44

T43

USB20_N 1

USB20_P 1

USB20_N 2

USB20_P 2

USB20_N 3

USB20_P 3

USB20_N 4

USB20_P 4

USB20_N 5

USB20_P 5

USB20_N 6

USB20_P 6

USB20_N 8

USB20_P 8

USB20_N 14

USB20_P 14

USB_OC0 #
USB_OC1 #

USB2_RC OMP
USB2_VB US_SENSE

USB2_ID

GPD_7

PCIE_PTX_ DRX_P24

PCIE_PTX_ DRX_N24
PCIE_PRX_ DTX_P24

PCIE_PRX_ DTX_N24

PCIE_PTX_ DRX_P23

PCIE_PTX_ DRX_N23
PCIE_PRX_ DTX_P23

PCIE_PRX_ DTX_N23

PCIE_PTX_ DRX_P22

PCIE_PTX_ DRX_N22

PCIE_PRX_ DTX_P22

PCIE_PRX_ DTX_N22

PCIE_PTX_ DRX_P21

PCIE_PTX_ DRX_N21

PCIE_PRX_ DTX_P21

PCIE_PRX_ DTX_N21

D

USB20_N 1 <7 1>
USB20_P 1 <71>

USB20_N 2 <4 3>
USB20_P 2 <43>

USB20_N 3 <7 2>
USB20_P 3 <72>

USB20_N 4 <7 3>
USB20_P 4 <73>

USB20_N 5 <3 8>
USB20_P 5 <38>

USB20_N 6 <3 8>
USB20_P 6 <38>

USB20_N 8 <6 6>
USB20_P 8 <66>

USB20_N 14 < 52>
USB20_P 14 <52>

USB_OC0 # <43 >

USB_OC1 # <71 >

1 2

RH4 113_040 2_1%

1 2

RH5 0_0402_ 5%@

1 2

RH6 0_0402_ 5%@

USB3 MB

USB3 MB TypeC

USB3 MB

USB3 SUB

Camera

TS

USB_OC0 #

RH213 10K_ 0402_5%

USB_OC1 #

RH214 10K_ 0402_5%

FingerPrint

FOR CNVI follow 571906_CNL_PCH_TA_WW11.pdf

X'tal Input:
High: Differential

BT

Low: Single ended

STRAP

PCIE_PTX_ DRX_P24 < 68>
PCIE_PTX_ DRX_N24 <68>

PCIE_PRX_DTX_P24 <68>

PCIE_PRX_DTX_N24 <68>

PCIE_PTX_ DRX_P23 < 68>
PCIE_PTX_ DRX_N23 <68>

PCIE_PRX_DTX_P23 <68>

PCIE_PRX_DTX_N23 <68>

PCIE_PTX_ DRX_P22 < 68>

PCIE_PTX_ DRX_N22 <68>

PCIE_PRX_DTX_P22 <68>

PCIE_PRX_DTX_N22 <68>

PCIE_PTX_ DRX_P21 < 68>

PCIE_PTX_ DRX_N21 <68>

PCIE_PRX_DTX_P21 <68>

PCIE_PRX_DTX_N21 <68>

E

+3VALW _PCH_PRIM

1 2

1 2

+3VALW

12

RH3

GPD_7

10K_040 2_5%

12

RH7
10K_040 2_5%

@

M.2 SSD-1 PCIE L3

M.2 SSD-1 PCIE L2

M.2 SSD-1 PCIE L1

M.2 SSD-1 PCIE L0

4 4

Security Classification

Security Classification

Security Classification

2019/12/ 28 2019/12/ 28

2019/12/ 28 2019/12/ 28

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

2019/12/ 28 2019/12/ 28

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

PCH(1/8)DMI/PCIE/USB2

PCH(1/8)DMI/PCIE/USB2

PCH(1/8)DMI/PCIE/USB2

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

EH50F M/B LA-H431PR10

EH50F M/B LA-H431PR10

EH50F M/B LA-H431PR10

Date : Sheet o f

Date : Sheet o f

D

Date : Sheet o f

14 100Wednesd ay, February 13, 201 9

14 100Wednesd ay, February 13, 201 9

14 100Wednesd ay, February 13, 201 9

E

1.0

1.0

1.0

A

B

C

D

E

PCH-H XTAL_IN/OUT POR is 24MHz for 571697_CNL_MOW_WW16_2017.pdf

RH8 1M_040 2_5%

YH1
24MHZ_1 8PF_XRCGB24M 000F2P51R0

1 1

2 2

3 3

4 4

+3VS

+1.8VALW _PRIM

+1.8VALW _PRIM

+1.8VALW _PRIM

3

33P_0402_50V8J

3

CH5

10P_0402_50V8J

1

32.768KH Z_9PF_X1A000 141000200

CH7

2

Trace Space: 15 mil
Max Trace Length: 1000 mil

RH217 10K_ 0402_5%

RH218 10K_ 0402_5%

RH219 10K_ 0402_5%

RH220 10K_ 0402_5%

For DDX03 R02

RH15 4.7K_0 402_5%

This signal has a weak internal pull-down 20K.
0 = 38.4/19.2MHz XTAL frequency selected.
1 = 24MHz XTAL frequency selected. (DDX03)
Notes:

1. The internal pull-down is disabled after RSMRST#
de-asserts.

2. This signal is in the primary well.

RH21 4.7K_0 402_5%

The signal has a weak internal pull-down 20K
0 = VCCPSPI is connected to 3.3V rail
1 = VCCPSPI is connected to 1.8V rail
Note: If VCCPSPI is connected to 1.8V rail, this pin

strap must be a ‘ 1’ fo r the prope r functionality
of the SPI (Flash) I/Os

RH22 10K_040 2_5%

RH23 10K_040 2_5%@

XTAL_24 M_PCH_OUT

4

NC

2

XTAL_24 M_PCH_IN

1

1 2

NC

1 2

RH12 10M_ 0402_5%

YH2

1 2

1

1 2

EMC@

RH11 33_04 02_1%

1 2

EMC@

RH9 33_040 2_1%

18P_0402_50V8J

CH6

PCH_RTC X1

PCH_RTC X2

10P_0402_50V8J

1

CH8

2

use same part w C5MMH

1 2

1 2

1 2

1 2

XTAL Frequency Select

1 2

VCCPSPI Select

@

1 2

M.2 CNV Mode Select

12

An external pull-up or pull-down is required.
0 = Integrated CNVi enable.
1 = Integrated CNVi disable.

Pulled down by CRF CNVi RGI_DT pin

12

A

LAN_CLK REQ#

VGA_CLK REQ#

WLA N_CLKREQ#

SSD1_CL KREQ#

CNV_BRI_P TX_DRX

GPP_J9

CNV_RGI_P TX_DRX

XTAL_24 M_PCH_OUT_R

XTAL_24 M_PCH_IN_R

+3VS

1 2

RH221 10K_ 0402_5%

STRAP

STRAP

STRAP

PCH_CPU _24M_CLK_P<10>
PCH_CPU _24M_CLK_N<10>

PCH_CPU _BCLK_P<10>
PCH_CPU _BCLK_N<10>

1 2

XCLK_BIASREF (PDG)
Trace Width/Space: 15mil /15 mil
Max Trace Length: 1000 mil
8/24

RH10 60.4_ 0402_1%

Raptor

remove no use srcclkreq

VGA_CLK REQ#<2 5>

LAN_CLK REQ#<51>

WLA N_CLKREQ#<52>

SSD1_CL KREQ#<68>

SSD2_CL KREQ#<68>

Raptor

SSD2_CL KREQ#

remove SD signal from PCH

remove CPU_C10_GATE#

CNV_BRI_P TX_DRX<52>

CNV_BRI_P RX_DTX<52>

CNV_RGI_P TX_DRX<52>
CNV_RGI_P RX_DTX<52>

+1.8VALW _PRIM

1 2

RH181 20K_04 02_1%CNVI@

1 2

571391_CFL_H_PDG_Rev0p71
To avoid floating input at the I/O pin BRI_RSP and RGI_RSP it is recommended to add
a weak pull up resistor to the SoC pin with a recommended value of 20K ohm.

B

RH182 20K_04 02_1%CNVI@

remove TP as C5PRH

PCH_CPU _24M_CLK_P
PCH_CPU _24M_CLK_N

PCH_CPU _BCLK_P
PCH_CPU _BCLK_N

XTAL_24 M_PCH_OUT_R
XTAL_24 M_PCH_IN_R

XCLK_BIAS REF

PCH_RTC X1

PCH_RTC X2

VGA_CLK REQ#
LAN_CLK REQ#

WLA N_CLKREQ#

SSD1_CL KREQ#

SSD2_CL KREQ#

AW13

BE9

BF8

BF9

BG8

BE8

BD8

AV13

AP3

AP2

AN4

AM7

AV6

AY3

AR13

AV7

AW3

CNV_BRI_P TX_DRX

CNV_BRI_P RX_DTX

CNV_RGI_P TX_DRX
CNV_RGI_P RX_DTX

GPP_J9

CNV_BRI_P RX_DTX

CNV_RGI_P RX_DTX

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

AT10

AV4

AY2

BA4

AV3

AW2

AU9

2019/12/ 28 2019/12/ 28

2019/12/ 28 2019/12/ 28

2019/12/ 28 2019/12/ 28

C

UH1G

BE33

GPP_A16/CLKOUT_48

D7

CLKOUT_CPUNSSC_P

C6

CLKOUT_CPUNSSC#

B8

CLKOUT_CPUBCLK_P

C8

CLKOUT_CPUBCLK#

U9

XTAL_OUT

U10

XTAL_IN

T3

XCLK_BIASREF

BA49

RTCX1

BA48

RTCX2

BF31

GPP_B5/SRCCLKREQ0#

BE31

GPP_B6/SRCCLKREQ1#

AR32

GPP_B7/SRCCLKREQ2#

BB30

GPP_B8/SRCCLKREQ3#

BA30

GPP_B9/SRCCLKREQ4#

AN29

GPP_B10/SRCCLKREQ5#

AE47

GPP_H0/SRCCLKREQ6#

AC48

GPP_H1/SRCCLKREQ7#

AE41

GPP_H2/SRCCLKREQ8#

AF48

GPP_H3/SRCCLKREQ9#

AC41

GPP_H4/SRCCLKREQ10#

AC39

GPP_H5/SRCCLKREQ11#

AE39

GPP_H6/SRCCLKREQ12#

AB48

GPP_H7/SRCCLKREQ13#

AC44

GPP_H8/SRCCLKREQ14#

AC43

GPP_H9/SRCCLKREQ15#

V2

CLKOUT_PCIE_N15

V3

CLKOUT_PCIE_P15

T2

CLKOUT_PCIE_N14

T1

CLKOUT_PCIE_P14

AA1

CLKOUT_PCIE_N13

Y2

CLKOUT_PCIE_P13

AC7

CLKOUT_PCIE_N12

AC6

CLKOUT_PCIE_P12

CNP-H_BG A874

UH1M

GPP_G0/SD_CMD

GPP_G1/SD_DATA0

GPP_G2/SD_DATA1

GPP_G3/SD_DATA2

GPP_G4/SD_DATA3

GPP_G5/SD_CD#

GPP_G6/SD_CLK

GPP_G7/SD_WP

GPP_I11/M2_SKT2_CFG0

GPP_I12/M2_SKT2_CFG1

GPP_I13/M2_SKT2_CFG2

GPP_I14/M2_SKT2_CFG3

GPP_J0/CNV_PA_BLANKING

GPP_J1/CPU_C10_GATE#

GPP_J11/A4WP_PRESENT

GPP_J10

GPP_J_2
GPP_J_3

GPP_J4/CNV_BRI_DT/UART0B_RTS#

GPP_J5/CNV_BRI_RSP/UART0B_RXD
GPP_J6/CNV_RGI_DT/UART0B_TXD

GPP_J7/CNV_RGI_RSP/UART0B_CTS#

GPP_J8/CNV_MFUART2_RXD

GPP_J9/CNV_MFUART2_TXD

CNP-H_BG A874

Compal Secret Data

Compal Secret Data

Compal Secret Data

CNP-H

CLKOUT_ITPXDP#

CLKOUT_ITPXDP_P

CLKOUT_CPUPCIBCLK#

CLKOUT_CPUPCIBCLK_P

CLKOUT_PCIE_N0

CLKOUT_PCIE_P0

CLKOUT_PCIE_N1

CLKOUT_PCIE_P1

CLKOUT_PCIE_N2

CLKOUT_PCIE_P2

CLKOUT_PCIE_N3

CLKOUT_PCIE_P3

CLKOUT_PCIE_N4

CLKOUT_PCIE_P4

CLKOUT_PCIE_N5

CLKOUT_PCIE_P5

CLKOUT_PCIE_N6

CLKOUT_PCIE_P6

CLKOUT_PCIE_N7

CLKOUT_PCIE_P7

CLKOUT_PCIE_N8

CLKOUT_PCIE_P8

CLKOUT_PCIE_N9

CLKOUT_PCIE_P9

CLKOUT_PCIE_N10

CLKOUT_PCIE_P10

CLKOUT_PCIE_N11

CLKOUT_PCIE_P11

7 OF 13

CNP-H

3.3V

1.8V

13 OF 13

Deciphered Date

Deciphered Date

Deciphered Date

Y3

Y4

B6

A6

AJ6

AJ7

AH9

AH10

AE14

AE15

AE6

AE7

AC2

AC3

AB2

AB3

W4

W3

W7

W6

AC14

AC15

U2

U3

AC9

AC11

AE9

AE11

CLKIN_XTAL

GPPJ_RCOMP_1P81
GPPJ_RCOMP_1P82

GPPJ_RCOMP_1P83

R6

Rev1.0

CNV_WR_CLKN

CNV_WR_CLKP

CNV_WR_D0N

CNV_WR_D0P
CNV_WR_D1N

CNV_WR_D1P

CNV_WT_CLKN

CNV_WT_CLKP

CNV_WT_D0N

CNV_WT_D0P
CNV_WT_D1N

CNV_WT_D1P

CNV_WT_RCOMP

PCIE_RCOMPN

PCIE_RCOMPP

SD_1P8_RCOMP

SD_3P3_RCOMP

RSVD2

RSVD3

RSVD1

TP

Rev1.0

BD4
BE3

BB3
BB4

BA3
BA2

BC5
BB6

BE6
BD7

BG6
BF6

BA1

B12

A13

BE5

BE4

BD1

BE1
BE2

Y35

Y36

BC1

AL35

D

TH2TP@

PCH_CPU _PCIBCLK_N

PCH_CPU _PCIBCLK_P

CLK_PEG _VGA#
CLK_PEG _VGA

CLK_PCIE_ LAN#
CLK_PCIE_ LAN

CLK_PCIE_ WLAN#
CLK_PCIE_ WLAN

CLK_PCIE_ NGFF1#

CLK_PCIE_ NGFF1

CLK_PCIE_ NGFF2#

CLK_PCIE_ NGFF2

TH3TP@

REFCLK_ CNV

12

RH14

10K_040 2_5%

CLK_CNV _PRX_DTX_N
CLK_CNV _PRX_DTX_P

CNV_PRX _DTX_N0
CNV_PRX _DTX_P0

CNV_PRX _DTX_N1
CNV_PRX _DTX_P1

CLK_CNV _PTX_DRX_N
CLK_CNV _PTX_DRX_P

CNV_PTX _DRX_N0
CNV_PTX _DRX_P0

CNV_PTX _DRX_N1
CNV_PTX _DRX_P1

CNV_W T_RCOMP

PCIE_RCOM PN
PCIE_RCOM PP

SD_RCOM P_1P8
SD_RCOM P_3P3

GPPJ_RC OMP_1P8

#571483_CFL_H_RVP_CRB_TDK_Rev0p5
Recommend external test point

PCH_CPU _PCIBCLK_N <10>
PCH_CPU _PCIBCLK_P <10>

CLK_PEG_VGA# <25>

CLK_PEG_VGA <25>

CLK_PCIE_ LAN# <51>

CLK_PCIE_ LAN < 51>

CLK_PCIE_ WLAN# <52 >

CLK_PCIE_ WLAN <52>

CLK_PCIE_ NGFF1# < 68>
CLK_PCIE_ NGFF1 <6 8>

CLK_PCIE_ NGFF2# < 68>

CLK_PCIE_ NGFF2 <6 8>

DGPU

GLAN

NGFF WL+BT(KEY E)

M2-1 SSD

M2-2 SSD

Raptor

REFCLK_ CNV <52>

CLK_CNV _PRX_DTX_N <5 2>
CLK_CNV _PRX_DTX_P <52>

CNV_PRX _DTX_N0 < 52>
CNV_PRX _DTX_P0 <52 >

CNV_PRX _DTX_N1 < 52>
CNV_PRX _DTX_P1 <52 >

CLK_CNV _PTX_DRX_N <5 2>
CLK_CNV _PTX_DRX_P <52>

CNV_PTX _DRX_N0 < 52>

CNV_PTX _DRX_P0 <52 >

CNV_PTX _DRX_N1 < 52>

RH16

1 2

1 2

RH17 100_ 0402_1%

1 2

RH18 200_ 0402_1%

1 2

RH19 200_ 0402_1%

1 2

RH20 200_ 0402_1%

TH4TP@

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Date : Sheet o f

Date : Sheet o f

Date : Sheet o f

150_040 2_1%

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

PCH(2/8)CLK/CNVI/SD

PCH(2/8)CLK/CNVI/SD

PCH(2/8)CLK/CNVI/SD

EH50F M/B LA-H431PR10

EH50F M/B LA-H431PR10

EH50F M/B LA-H431PR10

CNV_PTX _DRX_P1 <52 >

checked CRB

15 100Wednesd ay, February 13, 201 9

15 100Wednesd ay, February 13, 201 9

15 100Wednesd ay, February 13, 201 9

E

1.0

1.0

1.0

A

Vinafix

Raptor

can remove if no use DP
08/1 8

DP0_HPD _PCH<25,39 >

HDMI_HPD_ PCH<2 5,40>

DP0_HPD _PCH

HDMI_HPD_ PCH

RT881 0_0402_ 5%@

EDP_HPD<38>

1 2

EDP_HPD

UH1E

AT6

GPP_I0/DDPB_HPD0/DISP_MISC0

AN10

GPP_I1/DDPC_HPD1/DISP_MISC1

AP9

GPP_I2/DDPD_HPD2/DISP_MISC2

AL15

GPP_I3/DDPF_HPD3/DISP_MISC3

AN6

GPP_I4/EDP_HPD/DISP_MISC4

remove PCH DP SCLK/SDATA

DDP[B..F]CTRLDATA

no follow naming

This signal has a weak internal Pull-down.
0 = Port B~D is not detected.
1 = Port B,C,D is detected. (Default)
Notes:

1. The internal Pull-down is disabled after
PCH_PWROK de-asserts.

2. This signal is in the primary well.

EC_PME#<51,58>

1 2

RH24 0_040 2_5%

EC_PME# _R

@

CRB connect GND

1 2

RH186 0_0402 _5%@

PCH_SPI_S I_R<66>

PCH_SPI_S O_R<66>

PCH_SPI_IO2

PCH_SPI_IO3

PCH_SPI_S I

GPP_H15

PCH_SPI_C LK_R<66>

STRAP

intel critical net recommend

PCH_SPI_C LK

* wait confirm CG7
PDG P348 quad mode support PH1K

+3VALW _SPI

1 1

+3VALW _PCH_PRIM

CRB PU 20k
#571182_CFL_PCH _EDS_Rev1.0 rec ommend 100k

#571391_CFL_H_PDG_Rev0p71

RH25 1K_040 2_5%

RH26 1K_040 2_5%

RH27 1K_0402 _5%

RH29 100K _0402_5%

#571182_CNL_PCH_H_EDS_V1_Rev0.7
External pull-up is required. Recommend 100K if pulled
up to 3.3V or 75K if pulled up to 1.8V.
571007_CFL_MOW_Archive_WW22_2017
STUFF R on GPP_H15

1 2

RH195 100K_0 201_5%@

12

12

12

12

RH258 0_04 02_5%NTPM@

1 2

RH259 0_04 02_5%NTPM@

1 2

RH260 0_04 02_5%NTPM@

PCH_SPI_C S#2<6 6>

R2 = 5ohm for SPI dual-load

RH258

4.99_040 2_1%

SD03449 9B80
TPM@

RH259

4.99_040 2_1%

SD03449 9B80
TPM@

TH6 TP@

1 2

PCH_SPI_S I
PCH_SPI_S O

PCH_SPI_C S#0

PCH_SPI_C LK

PCH_SPI_IO2

PCH_SPI_IO3

RH260

4.99_040 2_1%

SD03449 9B80
TPM@

CNP-H_BG A874

UH1A

BE36

GPP_A11/PME#/SD_VDD2_PWR_EN#

R15

RSVD2

R13

RSVD1

AL37

VSS

AN35

TP

AU41

SPI0_MOSI

BA45

SPI0_MISO

AY47

SPI0_CS0#

AW47

SPI0_CLK

AW48

SPI0_CS1#

AY48

SPI0_IO2

BA46

SPI0_IO3

AT40

SPI0_CS2#

BE19

GPP_D1/SPI1_CLK/SBK1_BK1

BF19

GPP_D0/SPI1_CS#/SBK0_BK0

BF18

GPP_D3/SPI1_MOSI/SBK3_BK3

BE18

GPP_D2/SPI1_MISO/SBK2_BK2

BC17

GPP_D22/SPI1_IO3

BD17

GPP_D21/SPI1_IO2

CNP-H_BG A874

CNP-H

5 OF 13

CNP-H

GPP_K15/GSXSRESET#

GPP_H18/SML4ALERT#

GPP_H15/SML3ALERT#

GPP_H12/SML2ALERT#

1 OF 13

GPP_I5/DDPB_CTRLCLK

GPP_I6/DDPB_CTRLDATA

GPP_I7/DDPC_CTRLCLK

GPP_I8/DDPC_CTRLDATA

GPP_I9/DDPD_CTRLCLK

GPP_I10/DDPD_CTRLDATA

GPP_F23/DDPF_CTRLDATA

GPP_F22/DDPF_CTRLCLK

GPP_F14/PS_ON#

GPP_K23/IMGCLKOUT1

GPP_K22/IMGCLKOUT0

GPP_H23/TIME_SYNC0

GPP_B13/PLTRST#

GPP_K16/GSXCLK

GPP_K12/GSXDOUT

GPP_K13/GSXSLOAD

GPP_K14/GSXDIN

GPP_E3/CPU_GP0

GPP_E7/CPU_GP1

GPP_B3/CPU_GP2

GPP_B4/CPU_GP3

GPP_H17/SML4DATA

GPP_H16/SML4CLK

GPP_H14/SML3DATA

GPP_H13/SML3CLK

GPP_H11/SML2DATA

GPP_H10/SML2CLK

INTRUDER#

Rev1.0

GPP_K21

GPP_K20

AL13

AR8

AN13

AL10

AL9

AR3

AN40

AT49

AP41

M45

L48

T45

T46

AJ47

Rev1.0

PLT_RST #

AV29

Y47

Y46

Y48

W46

AA45

AL47

AM45
BF32

BC33

AE44

AJ46

AE43

AC47

AD48

AF47

AB47

AD47
AE48

BB44

TP_INT#

GPP_H15

GPP_H12

SM_INTRUD ER#

RVP: 330K
A 1 M pull-up is used on the customer reference
board (CRB). This is needed to reduce leakage
from Coin Cell Battery in G3 state.

PLT_RST # <58,6 6>

GPIO Serial Expander (GSX) is the capability
provided by the PCH to expand the GPIOs
on a platform that needs more GPIOs than the
ones provided by the PCH.

12

DH1
RB751V-4 0_SOD323-2

GPP_H12 <1 9>

EC_TP_INT# <58,63>

+RTCVCC

12

RH301M_0402 _5%

intel critical net recommend

1 2

RH198 100K_0 201_5%

PLT_RST #

1 2

CH9 100P_0402_5 0V8J

XEMC@

TP_INT#

RH28 100 K_0402_5%

+3VS

12

SPI ROM ( 16MByte )

PCH_SPI_IO2_ 0_R

note : 1050 Use 8M rom

PCH_SPI_C S#0

PCH_SPI_C LK_0_R

+3VALW _SPI

UH2

1

/CS

2

DO(IO1)

3

/WP(IO2)

4

GND

W25 Q128FVSIQ_SO8

/HOLD(IO3)

VCC

CLK

DI(IO0)

8

7
6

5

P/N: SA0000B8400 , XMC

@

1 2

@

RH33
0_0402_ 5%

1 2

CH12
68P_040 2_50V8J

CH10 0.1U_ 0201_10V6K

1 2

PCH_SPI_IO3_ 0_RPCH_SPI_S O_0_R

PCH_SPI_C LK_0_R

PCH_SPI_S I_0_R

PCH_SPI_C S#0

PCH_SPI_S I_0_R
PCH_SPI_S O_0_R

PCH_SPI_IO3_ 0_R
PCH_SPI_C LK_0_R

intel PDG 1.8
33 ohm for 3.3V for singel load
place 500 mil from PCH

RH107 33_0 402_1%

RH108 33_0 402_1%

RH109 33_0 402_1%

RH110 33_0 402_1%

RH111 33_0 402_1%

1 2

RH31 4.7K_0 402_5%

1 2

1 2

1 2

1 2

1 2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+3VALW _SPI

@

PCH PLTRST Buffer

PLT_RST #

PCH_SPI_S I_R

PCH_SPI_S O_R

PCH_SPI_IO3

PCH_SPI_C LK_R

PCH_SPI_IO2PCH_SPI_IO2_ 0_R

Compal Secret Data

Compal Secret Data

2019/12/ 28 2019/12/ 28

2019/12/ 28 2019/12/ 28

2019/12/ 28 2019/12/ 28

A

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

1 2

RH32 0_0 402_5%@

+3VS

1

B

2

A

1 2

CH11

0.1U_020 1_10V6K

5

UH3

P

4

Y

G

TC7SH08 FU_SSOP5

3

SA00000 OH00

PLT_RST _BUF# <2 5,51,52,68>

EH50F:main source change to SA00000OH00

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

PCH(3/8)DDC/SPI

PCH(3/8)DDC/SPI

PCH(3/8)DDC/SPI

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

EH50F M/B LA-H431PR10

EH50F M/B LA-H431PR10

EH50F M/B LA-H431PR10

Date : Sheet o f

Date : Sheet o f

Date : Sheet o f

1.0

1.0

1.0

16 100Wednesd ay, February 13, 201 9

16 100Wednesd ay, February 13, 201 9

16 100Wednesd ay, February 13, 201 9

A

Raptor:conf ir m wt ih SW

USB3 MB

1 1

USB3 Type C

USB3 MB

USB3 SUB

B

UH1F

USB3_PT X_DRX_N1<71>
USB3_PT X_DRX_P1<71>

USB3_PR X_DTX_N1<71>
USB3_PR X_DTX_P1<71>

USB3_PT X_DRX_N2<42>
USB3_PT X_DRX_P2<42>

USB3_PR X_DTX_N2<42>
USB3_PR X_DTX_P2<42>

USB3_PT X_DRX_P3<72>
USB3_PT X_DRX_N3<72>

USB3_PR X_DTX_P3<72>
USB3_PR X_DTX_N3<72>

USB3_PT X_DRX_P4<73>
USB3_PT X_DRX_N4<73>

USB3_PR X_DTX_P4<73>
USB3_PR X_DTX_N4<73>

F9

F7

D11

C11

C3

D4
B9

C9

C17

C16

G14

F14
C15

B15

J13

K13

G12

F11
C10

B10

C14

B14

J15

K16

CNP-H_BG A874

USB31_1_TXN
USB31_1_TXP

USB31_1_RXN
USB31_1_RXP

USB31_2_TXN
USB31_2_TXP

USB31_2_RXN
USB31_2_RXP

USB31_6_TXN
USB31_6_TXP

USB31_6_RXN
USB31_6_RXP

USB31_5_TXN
USB31_5_TXP

USB31_5_RXN
USB31_5_RXP

USB31_3_TXP
USB31_3_TXN

USB31_3_RXP
USB31_3_RXN

USB31_4_TXP
USB31_4_TXN

USB31_4_RXP
USB31_4_RXN

1.8V
(eSPI)

GPP_A7/PIRQA#/ESPI_ALERT0#

GPP_A14/SUS_STAT#/ESPI_RESET#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

6 OF 13

C

CNP-H

GPP_A1/LAD0/ESPI_IO0

GPP_A2/LAD1/ESPI_IO1

GPP_A3/LAD2/ESPI_IO2

GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS0#

GPP_A6/SERIRQ/ESPI_CS1#

GPP_A0/RCIN#/ESPI_ALERT1#

GPP_A10/CLKOUT_LPC1

GPP_K19/SMI#

GPP_K18/NMI#

GPP_E6/SATA_DEVSLP2

GPP_E5/SATA_DEVSLP1

GPP_E4/SATA_DEVSLP0

GPP_F9/SATA_DEVSLP7

GPP_F8/SATA_DEVSLP6

GPP_F7/SATA_DEVSLP5

GPP_F6/SATA_DEVSLP4

GPP_F5/SATA_DEVSLP3

Rev1.0

BB39

AW37

AV37

BA38

BE38

AW35

BA36
BE39

BF38

BB36

BB34

T48

T47

AH40

AH35

AL48

AP47

AN37

AN46

AR47

AP48

#571391_CFL_H_PDG_Rev0p5

eSPI clock and eSPI data mismatched: <500 mils.

‧

eSPI clock and eSPI chip select mismatched: <500 mils.

‧

eSPI signal maximum 9 Vias

‧

* If DATA signals are entirely routed on MS, stuff the resistor with 15 Ohm.

LPC_AD0

LPC_AD1

LPC_AD2

LPC_AD3

LPC_FRA ME#

TPM_SER IRQ

LPC_PIRQA #

KBRST#

ESPI_RST#

CLK_LPC

SSD_DEV SLP1

1 2

RH262 0_04 02_5%@

RH35 22_0402 _5%

D

LPC_AD0 <58>

LPC_AD1 <58>
LPC_AD2 <58>

LPC_AD3 <58>

LPC_FRA ME# <58>

TPM_SER IRQ <58 ,66>

12

SSD_DEV SLP1 <68>

CONFIRM WITH SW

LPC Bus

LPC : +3.3V

OVRM_EN < 22,58>

CLK_LPC _R <58>

check straps

TPM_SER IRQ

LPC_PIRQA #

Raptor

KBRST#

E

10K_040 2_5%

1 2

10K_040 2_5%

1 2

10K_040 2_5%

+3VS

12

RH37

RH38

RH248

Raptor

2 2

For Intel CLINK

TH10 TP@

TH11 TP@

TH12 TP@

CL_CLK
CL_DATA

CL_RST#

HDD

Raptor

PCIE_PTX_ DRX_P11<68>

M.2 SSD-1 PCIE L1

Raptor

3 3

GLAN

+3VALW _PCH_PRIM

12

RH43

10K_040 2_5%

4 4

UMA@

PCIE_PTX_ DRX_N14<51>

PCIE_PTX_ DRX_P14<51>

PCIE_PRX_DTX_N14<51>
PCIE_PRX_DTX_P14<51>

M.2 SSD-1 PCIE L0

DGPU_PR SNT#

PCIE_PTX_ DRX_N11<68>

PCIE_PRX_ DTX_P11<68>

PCIE_PRX_ DTX_N11<68>

DGPU_PR SNT#

PCIE_PTX_ DRX_N14
PCIE_PTX_ DRX_P14

PCIE_PRX_ DTX_N14
PCIE_PRX_ DTX_P14

PCIE_PTX_ DRX_P12<68>

PCIE_PTX_ DRX_N12<68>

PCIE_PRX_ DTX_P12<68>

PCIE_PRX_ DTX_N12<68>

UH1C

AR2

CL_CLK

AT5

CL_DATA

AU4

CL_RST#

P48

GPP_K8

V47

GPP_K9

V48

GPP_K10

W47

GPP_K11

L47

GPP_K0

L46

GPP_K1

U48

GPP_K2

U47

GPP_K3

N48

GPP_K4

N47

GPP_K5

P47

GPP_K6

R46

GPP_K7

C36

PCIE11_TXP/SATA0A_TXP

B36

PCIE11_TXN/SATA0A_TXN

F39

PCIE11_RXP/SATA0A_RXP

G38

PCIE11_RXN/SATA0A_RXN

AR42

GPP_F10/SATA_SCLOCK

AR48

GPP_F11/SATA_SLOAD

AU47

GPP_F13/SATA_SDATAOUT0

AU46

GPP_F12/SATA_SDATAOUT1

C39

PCIE14_TXN/SATA1B_TXN

D39

PCIE14_TXP/SATA1B_TXP

D46

PCIE14_RXN/SATA1B_RXN

C47

PCIE14_RXP/SATA1B_RXP

B38

PCIE13_TXN/SATA0B_TXN

C38

PCIE13_TXP/SATA0B_TXP

C45

PCIE13_RXN/SATA0B_RXN

C46

PCIE13_RXP/SATA0B_RXP

E37

PCIE12_TXP/SATA1A_TXP

D38

PCIE12_TXN/SATA1A_TXN

J41

PCIE12_RXP/SATA_1A_RXP

H42

PCIE12_RXN/SATA1A_RXN

B44

PCIE20_TXP/SATA7_TXP

A44

PCIE20_TXN/SATA7_TXN

R37

PCIE20_RXP/SATA7_RXP

R35

PCIE20_RXN/SATA7_RXN

D43

PCIE19_TXP/SATA6_TXP

C44

PCIE19_TXN/SATA6_TXN

N42

PCIE19_RXP/SATA6_RXP

M44

PCIE19_RXN/SATA6_RXN

CNP-H_BG A874

CNP-H

PCIE9_RXN

PCIE9_RXP

PCIE9_TXN

PCIE9_TXP

PCIE10_RXN

PCIE10_RXP

PCIE10_TXN

PCIE10_TXP

PCIE15_RXN/SATA2_RXN

PCIE15_RXP/SATA2_RXP

PCIE_15_SATA_2_TXN

PCIE15_TXP/SATA2_TXP

PCIE16_RXN/SATA3_RXN

PCIE16_RXP/SATA3_RXP

PCIE16_TXN/SATA3_TXN

PCIE16_TXP/SATA3_TXP

PCIE17_RXN/SATA4_RXN

PCIE17_RXP/SATA4_RXP

PCIE17_TXN/SATA4_TXN

PCIE17_TXP/SATA4_TXP

PCIE18_RXN/SATA5_RXN

PCIE18_RXP/SATA5_RXP

PCIE18_TXN/SATA5_TXN

PCIE18_TXP/SATA5_TXP

GPP_E8/SATA_LED#

GPP_E0/SATAXPCIE0/SATAGP0

GPP_E1/SATAXPCIE1/SATAGP1

GPP_E2/SATAXPCIE2/SATAGP2

GPP_F0/SATAXPCIE3/SATAGP_3

GPP_F1/SATAXPCIE4/SATAGP4

GPP_F2/SATAXPCIE5/SATAGP5

GPP_F3/SATAXPCIE6/SATAGP6

GPP_F4/SATAXPCIE7/SATAGP7

GPP_F21/EDP_BKLTCTL

GPP_F20/EDP_BKLTEN

GPP_F19/EDP_VDDEN

THRMTRIP#

PECI

PM_SYNC

3 OF 13

PLTRST_CPU#

PM_DOWN

Rev1.0

G36

F36
C34

D34

K37

J37

C35

B35

F44

E45

B40

C40

L41

M40

B41

C41

K43

K44

A42

B42

P41

R40

C42

D42

AK48

AH41

AJ43

AK47

AN47

RH187 10K_0402_ 5%@

AM46

AM43

AM47

AM48

AU48

AV46

AV44

AD3

AF2
AF3

AG5

AE2

PCIE_PRX_ DTX_N9

PCIE_PRX_ DTX_P9

PCIE_PTX_ DRX_N9

PCIE_PTX_ DRX_P9

PCIE_PRX_ DTX_N10

PCIE_PRX_ DTX_P10

PCIE_PTX_ DRX_N10

PCIE_PTX_ DRX_P10

PCIE_PRX_ DTX_N15
PCIE_PRX_ DTX_P15

PCIE_PTX_ DRX_N15
PCIE_PTX_ DRX_P15

SATA_GP 1

1 2

SATA_GP 5

PCH_BKL _PWM

ENBKL

PCH_ENV DD

PCH_THE RMTRIP#

PCH_PEC I

H_PM_SYNC

H_PLTRS T_CPU#

H_PM_DO WN_R

PCIE_PRX_ DTX_N9 <68>
PCIE_PRX_ DTX_P9 <6 8>

PCIE_PTX_ DRX_N9 <68>
PCIE_PTX_ DRX_P9 <6 8>

PCIE_PRX_ DTX_N10 <68>
PCIE_PRX_ DTX_P10 < 68>

PCIE_PTX_ DRX_N10 <68>
PCIE_PTX_ DRX_P10 < 68>

SATA_PR X_DTX_N4 <67>

SATA_PR X_DTX_P4 <6 7>
SATA_PT X_DRX_N4 <67>

SATA_PT X_DRX_P4 <6 7>

SATA_GP 1 <68 >

TP@

TH13

PCH_BKL _PWM <38>

ENBKL <58>

1 2

RH40 620_0 402_5%

1 2

RH41 13_04 02_5%@

1 2

RH42 30_0 402_5%

PCH_ENV DD <38>

M.2 SSD-1 PCIE L3

M.2 SSD-1 PCIE L2

PCIE_PRX_DTX_N15 <52>
PCIE_PRX_DTX_P15 <52>

PCIE_PTX_ DRX_N15 <52>

PCIE_PTX_ DRX_P15 < 52>

HDD

#571391_CFL_H_PDG_Rev0p5.pdf

H_PECI

H_PM_SYNC _R

NGFF
WL+BT(KEY E)

SATA_GP 1

RH201 10K_04 02_5%

M.2 SSD PCIE/SATA select pin

PCH_THE RMTRIP#_R <10 >

H_PECI <10,58>

H_PM_SYNC _R <10>

H_PLTRS T_CPU# <10>

H_PM_DO WN_R < 10>

H_PECI

XEMC@

1 2

+3VS

12

CH50.1U_0402 _16V7K

12

RH44

10K_040 2_5%

VGA@

DIS,Optimus10

A

UMA

GPP_F13

DGPU_PRSNT#

Raptor

Security Classification

Security Classification

Security Classification

2019/12/ 28 2019/12/ 28

2019/12/ 28 2019/12/ 28

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

2019/12/ 28 2019/12/ 28

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

PCIE/SATA/USB3/eSPI

PCIE/SATA/USB3/eSPI

PCIE/SATA/USB3/eSPI

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

EH50F M/B LA-H431PR10

EH50F M/B LA-H431PR10

EH50F M/B LA-H431PR10

Date : S heet o f

Date : Sheet o f

D

Date : Sheet o f

17 100Wednesd ay, February 13, 201 9

17 100Wednesd ay, February 13, 201 9

17 100Wednesd ay, February 13, 201 9

E

1.0

1.0

1.0

E

Raptor TBT

1 2

1 2

+3VALW _PCH_PRIM

12

DDR_DRA MRST#_R <2 3,24>

AC_PRES ENT <58>

PBTN_OU T# <58>

Connect CPU & PCH

PCH_DPW ROK

BF36

AV32

BF41

BD42

BB46

BE32

BF33

BE29

R47

AP29

AU3

BB47

BE40

BF40

BC28

BF42

BE42

BC42

BE45

BF44

BE35

BC37

BG44
BG42

BD39

BE46

AU2

AW29

AE3

AL3

AH4

AJ4

AH3

AH2

AJ3

12

CH20.1U_0402 _16V7K

CH21.1U_0402 _16V7K

CH22.1U_0402 _16V7K

CH51.1U_0402 _16V7K

D

DRAM_RE SET#

PM_CLKR UN#

LAN_DISAB LE_N

SLP_W LAN#

DRAM_RE SET#

PCH_VRA LERT#

TYPEC_3A

PCH_GPP _K17
PCH_GPP _B11

SYS_PW ROK

WAKE #

PM_SLP_ A#
SLP_LAN #

PM_SLP_ S3#

PM_SLP_ S4#
PM_SLP_ S5#

SUSCLK

PM_BATL OW#

SUSACK# _R

RH51 0_040 2_5%

LAN_W AKE#

AC_PRES ENT_R
SLP_SUS #

PBTN_OU T#_R

SYS_RESET #

PCH_SPK R
H_CPUPW RGD

XDP_ITP_P MODE

CPU_XDP _TCK0
CPU_XDP _TMS

CPU_XDP _TDO
CPU_XDP _TDI

PCH_JTA G_TCK1

LAN_W AKE#

SYS_RESET #

SYS_PW ROK

RH184100K_04 02_5% @

PCH_DPW ROK

RH61100K_0402_ 5%

SYS_RESET #

SYS_PW ROK

PCH_PW ROK

EC_RSMR ST#

1 2

@

+1.2V_VD DQ

RH46
470_040 2_1%

1 2

1 2

RH47 0_0402_ 5%

CH13 1U_0 201_6.3V6M

TH14TP@

TH15TP@

TYPEC_3A <43>

TH19TP@

TH20TP@

SYS_PW ROK <58 ,78>

TH37TP@

TH21TP@

PM_SLP_ S3# < 58,78>
PM_SLP_ S4# < 58,78>

TH23TP@

T207TP@

SUSPW RDNACK <58 >

1 2

@

RH53 0_040 2_5%

TP@

1 2

T208

@

RH54 0_040 2_5%

PCH_SPK R <19,56>

H_CPUPW RGD <10>

T209

TP@

CPU_XDP _TCK0 < 10>

CPU_XDP _TMS <10>
CPU_XDP _TDO <1 0>

CPU_XDP _TDI <10>

PCH_JTA G_TCK1 <10>

PM_SLP_ S3#

PM_SLP_ S4#

intel critical net recommend

EC_RSMR ST#

PCH_VRA LERT#

1 2

RH59 0_040 2_5%

PCH_PW ROK

EC_RSMR ST#

RH62 10K_ 0402_5%@

12

@

SUSCLK < 52,68>

AC_PRES ENT

--No Support Deep Sx

PBTN_OU T#

RH193 100K_0 201_5%

RH194 100K_0 201_5%

@

1 2

RH223 10K_ 0402_5%

1 2

RH224 10K_ 0402_5%

A

1 2

ME_EN<58>

1 2

HDA_RST #_R<56>

HDA_BIT_C LK_R<5 6>

HDA_SDO UT_R<56>

HDA_SYNC_ R< 56>

1 1

RH226 33_0 402_5%

1 2

RH227 33_0 402_5%

1 2

RH228 33_0 402_5%

1 2

RH229 33_0 402_5%

HDA_BIT_C LK

12

RH196100K_0201 _5%

HDA_RST #

12

RH197100K_0201 _5%

@

RH45 0_040 2_5%

HDA_RST #

HDA_BIT_C LK

HDA_SDO UT

HDA_SYNC

intel critical net recommend

del RF reserve cap on HDA

RH48,49 close to PCH

CPU_DISPA _SDO_R< 6>

CPU_DISPA _SDI_R<6>

FOR Jefferson Peak RESET pin is glitch free,it
is recommended that a pull-down resistor of 75K
ohm on GPP_D5(CNV_RF_RESET#)

+RTCVCC

1 2

RH50 20K_ 0402_1%

1 2

2 2

3 3

+3VS

+3VALW _PCH_PRIM

4 4

CH18 1U_0201_6.3 V6M

1 2

RH52 20K_ 0402_1%

1 2

CH19 1U_0201_6.3 V6M

1 2

JCMOS1 0_0603_5%@

+3VALW _DSW

RH55 1K_0 402_5%

RH56 8.2K_ 0402_5%

RH57 100K _0402_5%@

@

RH58 100K _0402_5%

RH60 10K_040 2_5%

RH191 2.2K_ 0402_5%

RH192 2.2K_ 0402_5%

RH230 2.2K_ 0402_5%

RH231 2.2K_ 0402_5%

RH232 2.2K_ 0402_5%

RH233 2.2K_ 0402_5%

12

12

12

12

12

12

12

12

12

12

12

CPU_DISPA _BCLK_R<6>

PCH_SRT CRST#

CLR ME
Delay 18~25 ms

PCH_RTC RST#

ECLR CMOS
Delay 18~25 ms

WAKE #

PM_BATL OW#

AC_PRES ENT_R

PBTN_OU T#_R

PM_CLKR UN#

D_CK_SC LK
D_CK_SD ATA

PCH_SMB CLK

PCH_SMB DATA

PCH_SML 1CLK

PCH_SML 1DATA

PCH_SML 1CLK <25,58,66 >

PCH_SML 1DATA < 25,58,66>

B

HDA_SDIN0<56>

RH48

1 2

RH49

1 2

CLKREQ_ CNV#<5 2>

CNV_RF_ RESET#< 52>

PCH_DMIC_ DATA0<56>
PCH_DMIC_ CLK0<56>

TH22 TP@

TH24 TP@

PCH_RTC RST#<58>

PCH_PW ROK<58,78>

EC_RSMR ST#< 58>

PCH_SMB ALERT#<19>

PCH_SML 0ALERT#<19>

PCH_SML 1ALERT#<19>

2N7002K DW_SOT36 3-6

PCH_SMB CLK

PCH_SMB DATA

Raptor

HDA_BIT_C LK

HDA_SDIN0
HDA_SDO UT

HDA_SYNC

HDA_RST #

D

+3VS

5

G

CPU_DISPA _SDO

CPU_DISPA _SDI_R
CPU_DISPA _BCLK

CLKREQ_ CNV#
CNV_RF_ RESET#

PCH_RTC RST#

PCH_SRT CRST#

PCH_PW ROK
EC_RSMR ST#

PCH_DPW ROK

PCH_SMB ALERT#

PCH_SMB CLK

PCH_SMB DATA

PCH_SML 0ALERT#
PCH_SML 0CLK

PCH_SML 0DATA
PCH_SML 1ALERT#

PCH_SML 1CLK
PCH_SML 1DATA

S

2

QH7A

6 1

D

G

D_CK_SC LK

D_CK_SD ATA

S

30_0402 _5%

30_0402 _5%

QH7B

3 4

2N7002K DW_SOT36 3-6

(EC, VGA, Thermal Sensor)

UH1D

BD11

HDA_BCLK/I2S0_SCLK

BE11

HDA_SDI0/I2S0_RXD

BF12

HDA_SDO/I2S0_TXD

BG13

HDA_SYNC/I2S0_SFRM

BE10

HDA_RST#/I2S1_SCLK

BF10

HDA_SDI1/I2S1_RXD

BE12

I2S1_TXD/SNDW2_DATA

BD12

I2S1_SFRM/SNDW2_CLK

AM2

HDACPU_SDO

AN3

HDACPU_SDI

AM3

HDACPU_SCLK

AV18

GPP_D8/I2S2_SCLK

AW18

GPP_D7/I2S2_RXD

BA17

GPP_D6/I2S2_TXD/MODEM_CLKREQ

BE16

GPP_D5/I2S2_SFRM/CNV_RF_RESET#

BF15

GPP_D20/DMIC_DATA0/SNDW4_DATA

BD16

GPP_D19/DMIC_CLK0/SNDW4_CLK

AV16

GPP_D18/DMIC_DATA1/SNDW3_DATA

AW15

GPP_D17/DMIC_CLK1/SNDW3_CLK

BE47

RTCRST#

BD46

SRTCRST#

AY42

PCH_PWROK

BA47

RSMRST#

AW41

DSW_PWROK

BE25

GPP_C2/SMBALERT#

BE26

GPP_C0/SMBCLK

BF26

GPP_C1/SMBDATA

BF24

GPP_C5/SML0ALERT#

BF25

GPP_C3/SML0CLK

BE24

GPP_C4/SML0DATA

BD33

GPP_B23/SML1ALERT#/PCHHOT#

BF27

GPP_C6/SML1CLK

BE27

GPP_C7/SML1DATA

CNP-H_BG A874

(DDR,G- Sens or)

D_CK_SC LK <23,24>

D_CK_SD ATA <23,24>

C

CNP-H

GPP_A12/BM_BUSY#/ISH_GP6/SX_EXIT_HOLDOFF#

GPP_B1/GSPI1_CS1#/TIME_SYNC1

GPP_K17/ADR_COMPLETE

1.8V

GPP_A13/SUSWARN#/SUSPWRDNACK

4 OF 13

+3VALW _DSW

+3VALW _PCH_PRIM

GPP_A8/CLKRUN#

GPD11/LANPHYPC

GPD9/SLP_WLAN#

DRAM_RESET#

GPP_B2/VRALERT#

GPP_B0/GSPI0_CS1#

GPP_B11/I2S_MCLK

SYS_PWROK

WAKE#

GPD6/SLP_A#

SLP_LAN#

GPP_B12/SLP_S0#

GPD4/SLP_S3#

GPD5/SLP_S4#

GPD10/SLP_S5#

GPD8/SUSCLK

GPD0/BATLOW#

GPP_A15/SUSACK#

GPD2/LAN_WAKE#

GPD1/ACPRESENT

SLP_SUS#

GPD3/PWRBTN#

SYS_RESET#

GPP_B14/SPKR

CPUPWRGD

ITP_PMODE

PCH_JTAGX

PCH_JTAG_TMS

PCH_JTAG_TDO

PCH_JTAG_TDI

PCH_JTAG_TCK

Rev1.0

1 2

RH225 10K_ 0402_5%

RH183 10K_ 0402_5%

1 2

1 2

@

XEMC@

1 2

XEMC@

1 2

XEMC@

1 2

XEMC@

1 2

From ESD Team Request

Near PCH side

1 2

RH63 499_040 2_1%

1 2

RH64 499_040 2_1%

A

PCH_SML 0CLK

PCH_SML 0DATA

Security Classification

Security Classification

Security Classification

2019/12/ 28 2019/12/ 28

2019/12/ 28 2019/12/ 28

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

2019/12/ 28 2019/12/ 28

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

PCH(5/8)PMU/HDA/SMBUS/DMIC

PCH(5/8)PMU/HDA/SMBUS/DMIC

PCH(5/8)PMU/HDA/SMBUS/DMIC

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

EH50F M/B LA-H431PR10

EH50F M/B LA-H431PR10

EH50F M/B LA-H431PR10

Date : S heet o f

Date : S heet o f

D

Date : S heet o f

18 100Wednesd ay, February 13, 201 9

18 100Wednesd ay, February 13, 201 9

18 100Wednesd ay, February 13, 201 9

E

1.0

1.0

1.0

A

+3VALW _PCH_PRIM

RH234 2.2K_ 0402_5%

RH235 2.2K_ 0402_5%

RH236 2.2K_ 0402_5%

RH237 2.2K_ 0402_5%

+3VS

RH66 10K_040 2_5%@

1 1

+3VALW _PCH_PRIM

2 2

RH68 49.9K_ 0402_1%

RH69 49.9K_ 0402_1%

RH70 49.9K_ 0402_1%@

RH71 49.9K_ 0402_1%@

1 2

RH72 10K_040 2_5%VGA@

1 2

RH73 10K_040 2_5%VGA@

1 2

RH74 4.7K_ 0402_5%@

This signal has a weak internal pull-down.
0 = Master Attached Flash Sharing (MAFS) enabled (Default)
1 = Slave Attached Flash Sharing (SAFS) enabled.
Notes:

1. This signal is in the primary well.

Warning: This strap must be configured to ‘ 0’ if th e
eSPI or LPC strap is configured to ‘ 0’

+3VALW _PCH_PRIM

12

12

12

12

12

12

12

12

12

I2C_1_SCL
I2C_1_SDA

I2C_0_SCL

I2C_0_SDA

EC_SCI# GC6_FB_ EN

UART_2_ PRXD_DTXD

UART_2_ PTXD_DRXD

UART_2_ PRTS_DCTS

UART_2_ PCTS_DRTS

DGPU_PW R_EN

DGPU_HO LD_RST#

GPP_H12

check needed?

CG11 connect to GPP_B15

GPP_H12 <1 6>

STRAP

B

Raptor

DGPU_AC _DETECT<25 ,58,83>

DGPU_HO LD_RST#<25>

DGPU_PW R_EN<25,37>

UART_2_ PTXD_DRXD<52>

UART_2_ PRXD_DTXD<52>

<Touch PAD>

Raptor:delete needless vga/project id

GSPI1_MOS I

EC_SCI#<58>

TS_EN<38,58>

I2C_1_SCL<6 3>

I2C_1_SDA<63>

GPU_EVE NT_R# CPU_ID

EC_SCI#

GSPI0_MOS I

TS_EN SUB_DET

DGPU_AC _DETECT

GPU_EVE NT_R#

DGPU_HO LD_RST#
DGPU_PW R_EN

UART_2_ PCTS_DRTS
UART_2_ PRTS_DCTS

UART_2_ PTXD_DRXD
UART_2_ PRXD_DTXD

I2C_1_SCL
I2C_1_SDA

I2C_0_SCL

I2C_0_SDA

1 2

RH200 0_04 02_5%

RH199 0_04 02_5%

@

1 2

@

C

UH1K

BA26

GPP_B22/GSPI1_MOSI

BD30

GPP_B21/GSPI1_MISO

AU26

GPP_B20/GSPI1_CLK

AW26

GPP_B19/GSPI1_CS0#

BE30

GPP_B18/GSPI0_MOSI

BD29

GPP_B17/GSPI0_MISO

BF29

GPP_B16/GSPI0_CLK

BB26

GPP_B15/GSPI0_CS0#

BB24

GPP_C9/UART0A_TXD

BE23

GPP_C8/UART0A_RXD

AP24

GPP_C11/UART0A_CTS#

BA24

GPP_C10/UART0A_RTS#

BD21

GPP_C15/UART1_CTS#/ISH_UART1_CTS#

AW24

GPP_C14/UART1_RTS#/ISH_UART1_RTS#

AP21

GPP_C13/UART1_TXD/ISH_UART1_TXD

AU24

GPP_C12/UART1_RXD/ISH_UART1_RXD

AV21

GPP_C23/UART2_CTS#

AW21

GPP_C22/UART2_RTS#

BE20

GPP_C21/UART2_TXD

BD20

GPP_C20/UART2_RXD

BE21

GPP_C19/I2C1_SCL

BF21

GPP_C18/I2C1_SDA

BC22

GPP_C17/I2C0_SCL

BF23

GPP_C16/I2C0_SDA

BE15

GPP_D4/ISH_I2C2_SDA/I2C3_SDA/SBK4_BK4

BE14

GPP_D23/ISH_I2C2_SCL/I2C3_SCL

CNP-H_BG A874

GPU_EVE NT#

GC6_FB_ EN3V3G C6_FB_EN

GPU_EVE NT# <25 >

GC6_FB_ EN3V3 <25 ,37>

CNP-H

GPP_D9/ISH_SPI_CS#/GSPI2_CS0#

GPP_D11/ISH_SPI_MISO/GP_BSSB_CLK/GSPI2_MISO

GPP_D12/ISH_SPI_MOSI/GP_BSSB_DI/GSPI2_MOSI

GPP_D15/ISH_UART0_RTS#/GSPI2_CS1#/CNV_WFEN

GPP_D10/ISH_SPI_CLK/GSPI2_CLK

GPP_D16/ISH_UART0_CTS#/CNV_WCEN

GPP_D14/ISH_UART0_TXD/I2C2_SCL

GPP_D13/ISH_UART0_RXD/I2C2_SDA

GPP_A17/SD_VDD1_PWR_EN#/ISH_GP7

11 OF 13

D

GPP_H20/ISH_I2C0_SCL

GPP_H19/ISH_I2C0_SDA

GPP_H22/ISH_I2C1_SCL

GPP_H21/ISH_I2C1_SDA

GPP_A23/ISH_GP5

GPP_A22/ISH_GP4

GPP_A21/ISH_GP3

GPP_A20/ISH_GP2

GPP_A19/ISH_GP1

GPP_A18/ISH_GP0

Rev1.0

BA20

BB20

BB16

AN18

BF14

AR18

BF17

BE17

AG45

AH46

AH47

AH48

AV34

AW32

BA33

BE34

BD34

BF35

BD38

VGA_ID1

VGA_ID2

PROJECT _ID0

PROJECT _ID1

CPU_ID

PANEL_O D_EN

PANEL_O D_EN <38>

1 2

RH208 1K_0 402_5%H82@

1 2

RH207 10K_ 0402_5%H6 2@

E

Raptor: delete needless strap

+1.8VALW _PRIM

RH112 4.7K_04 02_5%@

SMBALERT# / GPP_C2 has a weak internal Pull-down.
0 = Disable Intel ME (TLS) (Default)
1 = Enable Intel ME (TLS)

1 2

RH113 4.7K_04 02_5%@

SML0ALERT# / GPP_C5 has a weak internal Pull-down.
0 = LPC is selected (for EC 9022).
1 = eSPI is selected

3 3

+3VS

RH77 4.7K_ 0402_5%@

The signal has a weak internal Pull-down.

0 = Disable “ No Reboot” mode . (Default)
1 = Enable “ No Reboot” mod e (PCH wil l disable th e
TCO Timer system reboot feature). This function is
useful when running ITP/XDP.
Notes:

1. The internal Pull-down is disabled after
PCH_PWROK is high.

2. This signal is in the primary well.

RH80 150K_ 0402_1%

4 4

This Signal has a weak internal Pull-down.
0: SPI (Default)
1: LPC
Notes:

1. The internal Pull-down is disabled after PCH_PWROK is high.

2. This signal is in the primary well.

RH83 100 K_0402_5%@

Top Swap Override

0 = Disable “ Top Swap” mode . (Default)
1 = Enable “ Top Swap” mode.
The internal Pull-down is disabled after PCH_PWROK is high.

1 2

RH114 150 K_0402_1%

SML1ALERT# / GPP_B23 has an internal pull-down.
0 = Disable IntelR DCI-OOB (Default)
1 = Enable IntelR DCI-OOB

1 2

@

1 2

12

A

GSPI0_MOS I

GSPI1_MOS I

PCH_SPK R

PCH_SMB ALERT# <18>

PCH_SML 0ALERT# <18>

PCH_SML 1ALERT# <18>

STRAP

STRAP

STRAP

PCH_SPK R <18,56>

STRAP

VBIOS select

VGA_ID1

VGA_ID2

VGA ID

1 2

RH84 1K_0402 _5%@

1 2

RH85 10K_040 2_5%

1 2

RH86 1K_0402 _5%@

1 2

RH87 10K_040 2_5%

VGA_ID2 VGA_ID1

GPP_D10 GPP_D9
Default
Reserved

0
Reserved
Reserved

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

+1.8VALW _PRIM +1.8VALW _PRIM

00
1
01
11

2019/12/ 28 2019/12/ 28

2019/12/ 28 2019/12/ 28

2019/12/ 28 2019/12/ 28

C

PROJECT _ID0

PROJECT _ID1

RH88 1K_0402 _5%@

RH89 10K_040 2_5%

RH90 1K_0402 _5%@

RH91 10K_040 2_5%

Project ID

EH50F(2060 WO RD)
EH50F(2060 W RD)
EH5VF(2050 WO RD)
EH5VF(2050 W RD)

SCI capability is available on all GPIOs
PCH GPIOs that can be routed to generate SMI# or NMI:

GPP_B14, GPP_B20, GPP_B23

‧

GPP_C[23:22]

‧

GPP_D[4:0]

‧

GPP_E[8:0]

‧

GPP_I[3:0]

‧

GPP_G[7:0] (support SMI# only).

‧

The voltage of all GPIO pads in each GPP group is determined by the voltage supplied to the group (either 3.3V or 1.8V),
except for GPP_I and GPD group, (which are 3.3V only), and GPP_J group (which is 1.8V only).

All GPIOs have programmable internal pull-up/pull-down resistors which are off by default.
The internal pull-up/pull-down for each GPIO can be enabled by BIOS programming.

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

1 2

1 2

1 2

1 2

Project_ID0Project_ID1

GPP_D11GPP_D12
0 0
0
1
1 1

D

1
0

Custom

Custom

Custom

Date : Sheet o f

Date : Sheet o f

Date : Sheet o f

SUB_DET

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

PCH(6/8)GPIO/I2C/UART/STRAP

PCH(6/8)GPIO/I2C/UART/STRAP

PCH(6/8)GPIO/I2C/UART/STRAP

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

EH50F M/B LA-H431PR10

EH50F M/B LA-H431PR10

EH50F M/B LA-H431PR10

1 2

RH185 1K_0 402_5%@

E

1 2

FOR 40 PIN SUB/B

+1.8VALW _PRIM

19 100Wednesd ay, February 13, 201 9

19 100Wednesd ay, February 13, 201 9

19 100Wednesd ay, February 13, 201 9

1.0

1.0

1.0

A

B

C

D

E

GPIO Group V olt age

+1.05VALW

@

JPH1

2

1

2

1

JUMP_43X79

1 1

@

JPH2

2

1

2

1

JUMP_43X79

+1.05VALW_PC H_PRIM

5.95A

1U_0201_6.3V6M

1

CH23

2

+1.05VALW_VCC MPHY

6.6A

22U_0603_6.3V6M

12

CH25

HSIO for DMIU/USB3.1/PCIE=4162mA

+1.05VALW_VCC MPHY

1U_0201_6.3V6M

1

CH26

2

+1.05VALW_PC H

3-5MM FROM PACKAGE EDGE

1 2

RH94 0_0603 _5%

+1.05VALW_PC H

2 2

place near VCCDUSB
FOR W22/W23

1-5MM FROM PACKAGE EDGE
FOR VCCAPLL C1/C2

3 3

+1.05VALW_PC H

0.1U_0201_10V6K

CH29

1

2

+1.05VALW_PC H

1U_0201_6.3V6M

1

CH33

2

RH102 0_0 402_5%

1P_0402_50V8

1

2

1-3MM FROM PACKAGE EDGE
FOR VCCA_BCLK V19

1 2

CH43

@

+1.05VALW_PC H

+1.05VALW_PC H +1.05V_VCCDSW

0.1U_0201_10V6K

CH30

1

2

1-3MM FROM PACKAGE
VCCPRIM_MPHY W31

+1.05VALW_PC H

0.1U_0201_10V6K

CH34

1

2

+1.05VALW_VCC AZPLL

1P_0402_50V8

1

CH44

2

@

1-3MM FROM PACKAGE EDGE

1-5MM FROM PACKAGE EDGE
FOR VCCAPLL B1/B2/B3

1U_0201_6.3V6M

1

2

+1.05VALW_PC H

1U_0201_6.3V6M

1

2

CH31

CH35

+1.05V_VCCDSW

+1.05VALW_VCC AZPLL

+1.05VALW_VCC AMPHYPLL

+1.05VALW_XTAL

+1.05VALW_PC H_PRIM

5.95A

6.6A

0.0012A

0.2A

0.42A

0.109A

0.015A

0.213A

0.00428A

0.169A

0.0198A

0.0085A

0.021A

+3VALW

RH99 0_0402 _5%

1P_0402_50V8

1

CH41

2

@

UH1H

AA22

VCCPRIM_1P051

AA23

VCCPRIM_1P052

AB20

VCCPRIM_1P053

AB22

VCCPRIM_1P054

AB23

VCCPRIM_1P055

AB27

VCCPRIM_1P056

AB28

VCCPRIM_1P057

AB30

VCCPRIM_1P058

AD20

VCCPRIM_1P059

AD23

VCCPRIM_1P0510

AD27

VCCPRIM_1P0511

AD28

VCCPRIM_1P0512

AD30

VCCPRIM_1P0513

AF23

VCCPRIM_1P0516

AF27

VCCPRIM_1P0517

AF30

VCCPRIM_1P0518

U26

VCCPRIM_1P0523

U29

VCCPRIM_1P0524

V25

VCCPRIM_1P0525

V27

VCCPRIM_1P0526

V28

VCCPRIM_1P0527

V30

VCCPRIM_1P0528

V31

VCCPRIM_1P0529

AD31

VCCPRIM_1P0514

AE17

VCCPRIM_1P0515

W22

VCCDUSB_1P051

W23

VCCDUSB_1P052

BG45

VCCDSW_1P051

BG46

VCCDSW_1P052

W31

VCCPRIM_MPHY_1P05

D1

VCCPRIM_1P0521

E1

VCCPRIM_1P0522

C49

VCCAMPHYPLL_1P051

D49

VCCAMPHYPLL_1P052

E49

VCCAMPHYPLL_1P053

P2

VCCA_XTAL_1P051

P3

VCCA_XTAL_1P052

W19

VCCA_SRC_1P051

W20

VCCA_SRC_1P052

C1

VCCAPLL_1P054

C2

VCCAPLL_1P055

V19

VCCA_BCLK_1P05

B1

VCCAPLL_1P051

B2

VCCAPLL_1P052

B3

VCCAPLL_1P053

CNP-H_BGA874

1 2

RH97 0_0805_5%

1 2

+3VALW_HDA

12

RH1010_0402_5% @

CH42

@

1-3MM FROM PACKAGE EDGE

A

+1.05VALW_VCC AMPHYPLL

22U_0603_6.3V6M

1

1

CH45

2

2

@

+1.05VALW_XTAL

22U_0603_6.3V6M

1

CH49

2

@

1U_0201_6.3V6M

CH46

1 2

RH103 0_0 402_5%

LC filter colse to pin

4 4

1uF 1-3MM FROM PACKAGE EDGE

1 2

RH105 0_0 402_5%

V/VX : use un-chargeable RTC

RTC Battery

+CHGRTC

+RTCBATT

B

RH104 1K_0 402_5%

12

EH50F :
change to 1k
(follow Intel DG)

BAV70W_SOT32 3-3

DH2

2

3

+RTCVCC

1

0.1U_0201_10V6K

1U_0201_6.3V6M

CH48

1

1

CH47

2

2

CNP-H

VCCPRIM_3P32

VCCPRIM_3P35

VCCPGPPG_3P3

VCCPRIM_3P33

VCCPRIM_3P34

VCCPGPPHK1

VCCPGPPHK2
VCCPGPPEF1

VCCPGPPEF2

VCCPGPPBC1
VCCPGPPBC2

VCCPRIM_3P31

VCCDSW_3P31

VCCDSW_3P32

VCCPRIM_1P83

VCCPRIM_1P84
VCCPRIM_1P85

VCCPRIM_1P86

VCCPRIM_1P87

VCCPRIM_1P81

VCCPRIM_1P82

VCCPRIM_1P0520

VCCPRIM_1P0519

VCCPRIM_1P241

VCCPRIM_1P242

VCCDPHY_1P241
VCCDPHY_1P242

VCCDPHY_1P243

VCCMPHY_SENSE

VSSMPHY_SENSE

8 OF 13

+3VALW_PCH_ PRIM

+3VALW_DSW

0.1U_0201_10V6K

CH40

1

2

1P_0402_50V8

1

2

reserve filter folloe CRB
8/21

+RTCBATT

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

AW9

BF47

DCPRTC1

BG47

DCPRTC2

V23

AN44

VCCSPI

BC49

VCCRTC1

BD49

VCCRTC2

AN21

AY8

BB7

AC35
AC36

AE35
AE36

AN24

VCCPGPPD

AN26

AP26

AN32

VCCPGPPA

AT44

BE48

BE49

BB14

VCCHDA

AG19
AG20

AN15

AR15

BB11

AF19
AF20

AG31

AF31

AK22
AK23

AJ22

AJ23
BG5

K47
K46

Rev1.0

+3VALW_PCH_ PRIM

RH98 0_0603 _5%

+1.8VALW

RH100 0_0 603_5%@

JRTC1

1

1

2

2

3

GND

4

GND

ACES_50271-00 20N-001

CONN@

SP02000RO00

2019/12/28 2019/12/28

2019/12/28 2019/12/28

2019/12/28 2019/12/28

0.182A

+VCCRTCEXT

0.095A

0.05A

0.145A

0.97A

0.262A

0.174A

0.14A

0.343A

0.101A

0.106A

0.113A

0.00767A

0.766A

0.882A

+1.8V_PHVLDO

0.193A

0.0895A

VCCMPHY_SENSE
VSSMPHY_SENSE

1 2

1 2

Compal Secret Data

Compal Secret Data

Compal Secret Data

Internal LDO

+3VALW_PCH_ PRIM

+1.8VALW_PRIM

+1.8V_PHVLDO

RH242 0_0603_5%@

TH27TP@

TH28TP@

+3VALW_SPI

+1.8VALW_PRIM

Deciphered Date

Deciphered Date

Deciphered Date

D

+VCCRTCEXT

+3VALW_SPI

+RTCVCC

+1.8VALW_PRIM

+3VALW_DSW

1 2

+1.05VALW_PC H

+1.05VALW_PC H

+1.24V_VCCLDOSR AM_IN

+1.24V_PRIM_DPHY

+1.24V_PRIM_MAR

1-3MM FROM PACKAGE
FOR PGPPEF AE35/AE37

+VCCRTCEXT

+1.8VALW_PRIM

4.7U_0402_6.3V6M

1

CH27

+3VALW_HDA

+1.8VALW_PRIM

Short pins AJ22,AJ23,AK22,AK23 together
at surface layer from PDG Rev0.71

0.1U_0201_10V6K

CH36

1

2

@

2

VCCPHVLDO_1P8
(RH242 unpop when External VRM mode )

For DDX03 R02

+1.24V_PRIM_MAR

4.7U_0402_6.3V6M

1

CH32

2

+3VALW_PCH_ PRIM+3VALW_PCH_ PRIM

1-3MM FROM PACKAGE
FOR PGPPHK AC35/AC36

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

PCH(7/8)Power

PCH(7/8)Power

PCH(7/8)Power

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Date : Sheet of

Date : Sheet of

Date : Sheet of

0.1U_0201_10V6K

1

2

1

2

0.1U_0201_10V6K

1

2

EH50F M/B LA-H431PR10

EH50F M/B LA-H431PR10

EH50F M/B LA-H431PR10

GPP A

GPP B
GPP C

GPP D

GPP E

CH24

GPP F

GPP G

GPP H
GPP K

GPP I

GPP J

GPD

1U_0201_6.3V6M

CH28

Close to BB11

+1.24V_VCCLDOSR AM_IN +1.24 V_PRIM_DPHY

RH96 0_0402 _5%@

RH96 pop if CNVi is used
571391_CFL_H_PDG_Rev1p8.pdf

CH39

@

1-3MM FROM PACKAGE
FOR VCCPRIM AY8/BB7

E

1 2

+3VALW_PCH_ PRIM

1U_0201_6.3V6M

1

CH37

2

3.3 V

3.3 V

3.3 V

*

1.8 V

3.3 V

3.3 V

3.3 V

3.3V Only

1.8V Only

3.3V Only

0.1U_0201_10V6K

CH38

1

2

20 100W ednesday, February 13, 2019

20 100W ednesday, February 13, 2019

20 100W ednesday, February 13, 2019

1.0

1.0

1.0

A

B

C

D

E

CNP-H

CNP-H

UH1I

A2

VSS

1 1

2 2

3 3

A28

A33

A37

A45

A46

A47

A48

AA19

AA20

AA25

AA27

AA28

AA30

AA31

AA49

AA5

AB19

AB25

AB31

AC12

AC17

AC33

AC38

AC4

AC46

AD1

AD19

AD2

AD22

AD25

AD49

AE12

AE33

AE38

AE4

AE46

AF22

AF25

AF28

AG1

AG22

AG23

AG25

AG27

AG28

AG30

AG49

AH12

AH17

AH33

AH38

AJ19

AJ20

AJ25

AJ27

AJ28

AJ30

AJ31

AK19

AK20

AK25

AK27

AK28

AK30

AK31

AK4

AK46

A3

A4

A5

A8

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

9 OF 13

VSS

CNP-H_BG A874

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

Rev1.0

AL12

AL17

AL21

AL24

AL26

AL29

AL33

AL38

AM1

AM18

AM32

AM49

AN12

AN16

AN34

AN38

AP4

AP46

AR12

AR16

AR34

AR38

AT1

AT16

AT18

AT21

AT24

AT26

AT29

AT32

AT34

AT45

AV11

AV39

AW10

AW4

AW40

AW46

B47

B48

B49

BA12

BA14

BA44

BA5

BA6

BB41

BB43

BB9

BC10

BC13

BC15

BC19

BC24

BC26

BC31

BC35

BC40

BC45

BC8

BD43

BE44

BF1

BF2

BF3

BF48

BF49

BG17

BG2

BG22

BG25

BG28

BG3

BG33

BG37

BG4

BG48

C12

C25

C30

C48

D12

D16

D17

D30

D33

G44

M16

M18

M21

E10

E13

E15

E17

E19

E22

E24

E26

E31

E33

E35

E40

E42

F41

F43

F47

J10

J26

J29

J40

J46

J47

J48

K11

K39

C4

C5

D8

E8

G6

H8

J4

J9

UH1L

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

12 OF 13

VSS

CNP-H_BG A874

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

Rev1.0

M24

M32

M34

M49

M5

N12

N16

N34

N35

N37

N38

P26

P29

P4

P46

R12

R16

R26

R29

R3

R34

R38

R4

T17

T18

T32

T4

T49

T5

T7

U12

U15

U17

U21

U24

U33

U38

V20

V22

V4

V46

W25

W27

W28

W30

Y10

Y12

Y17

Y33

Y38

Y9

CNP-H

UH1J

RSVD7
RSVD8

RSVD6
RSVD5

RSVD3
RSVD4

RSVD2

RSVD1

PREQ#

PRDY#

CPU_TRST#

TRIGGER_OUT

TRIGGER_IN

10 OF 13

CNP-H_BG A874

Rev1.0

Y14

Y15

U37

U35

N32

R32

AH15
AH14

AL2

AM5

AM4

AK3

AK2

XDP_PRE Q#
XDP_PRD Y#

CPU_XDP _TRST#

PCH_TRIGO UT
CPU_TRIGO UT_R

1 2

RH106 30_040 2_5%

PCH_TRIGO UT_R

XDP_PRE Q# <10>

XDP_PRD Y# <10>
CPU_XDP _TRST# <1 0>

PCH_TRIGO UT_R <13>
CPU_TRIGO UT_R <13>

4 4

Security Classification

Security Classification

Security Classification

2019/12/ 28 2019/12/ 28

2019/12/ 28 2019/12/ 28

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

2019/12/ 28 2019/12/ 28

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

PCH(8/8)GND/RSVD

PCH(8/8)GND/RSVD

PCH(8/8)GND/RSVD

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

EH50F M/B LA-H431PR10

EH50F M/B LA-H431PR10

EH50F M/B LA-H431PR10

Date : Sheet o f

Date : Sheet o f

D

Date : Sheet o f

21 100Wednesd ay, February 13, 201 9

21 100Wednesd ay, February 13, 201 9

21 100Wednesd ay, February 13, 201 9

E

1.0

1.0

1.0

12

Vinafix

RG2975

2K_0402_5%

RG2910

215_040 2_1%

SD00000 0180
uPI@

RG2911

215_040 2_1%

SD00000 0180
uPI@

E

VGA@

E

12

RG2976

2K_0402_5%

VGA@

12

RG2977

2K_0402_5%

R2917

324K_04 02_1%

SD03432 4380
uPI@

22 100Wednesd ay, February 13, 201 9

22 100Wednesd ay, February 13, 201 9

22 100Wednesd ay, February 13, 201 9

VGA@

12

RG2978

2K_0402_5%

1.0

1.0

1.0

A

CSSP_B+

1 1

CSSP_NV VDD

1 2

RG2910 287_ 0402_1%ON@

1 2

2 2

3 3

RG2911 287_ 0402_1%ON@

1 2

RG2912 169_ 0402_1%@

1 2

RG2914 169_ 0402_1%

+3V_OVR M

12

@

12

UPI@

@

RG2923
10K_040 2_1%

PFM_ADC _FILTER_EN

RG2925
10K_040 2_1%

GPIO28_OC _WARN#<25>

13

D

S

1 2

RG2895 75K_ 0402_1%VG A@

CG2780

12

1000P_0 402_50V7K

VGA@

1 2

VGA@

RG2897 75K_ 0402_1%

CG2781

12

1000P_0 402_50V7K

VGA@

0.015U_0402_16V7K

0.015U_0402_16V7K

0.015U_0402_16V7K

1

CG2786

2

@

OVRM_EN

2

G

QG549
L2N7002 WT1G_SC-70 -3

ON@

1

2

@

1

CG2787

2

VGA@

GPIO28_OC _WARN#

12

SB00001GE00

RG2896

1 2

649_040 2_1%

ON@

RG2898

1 2

649_040 2_1%

ON@

RG2906

1 2

@

0_0402_ 5%

0.015U_0402_16V7K

1

CG2789

CG2788

2

VGA@

RG3020
100K_04 02_5%

ON@

OVRM_EN < 17,58>

B

PFM_CH1 _BS_IN1

PFM_CH1 _BS_IN2

RG2900

0_0402_5%

RG2903

0_0402_5%

@

@

1 2

1 2

PFM_CH1 _BS_IN3

PFM_CH1 _BS_IN4

PFM_FILTE R_GND_FET

RG2916

@

0_0402_ 5%

PFM_ADC _MUX_SEL_R

PFM_ADC _FILTER_EN

PFM_SKIP_ R

PFM_ADC _FILTER_MODE

1 2

0730 FAE CF suggest

UG108

3

BS_IN1

6

BS_IN2

11

BS_IN3

14

BS_IN4

9

GND_FET

32

SH_O1

7

SH_O2

10

SH_O3

17

SH_O4

29

MUX_SEL

28

ENABLE

25

SKIP

26

MODE_SEL

NCP4549 1XMNTWG_Q FN32_4X4

SA0000C9Q00

ON@

DIFF_OUT_P

DIFF_OUT_N

BG_REF_OUT

ON semi : Add QG549 for S3/S4/S5
reduce power consumption when S3/S4/S5

+3V_OVR M

+3V_OVR M

12

RG2928

@

10K_040 2_1%

4 4

PFM_ADC _FILTER_MODE

12

RG2929

@

10K_040 2_1%

A

B

12

RG2924
1K_0402 _1%

VGA@

PFM_SKIP_ R

0727 FAE CF suggest

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

+3V_OVR M

1 2

RG2899 0_0402_ 5%

1 2

RG3019 0_0402_ 5%

1

VGA@

CG2782
1U_0201 _6.3V6M

12

RG2926
10K_040 2_1%

2

VCC

SH_IN_P1

SH_IN_N1

SH_IN_P2
SH_IN_N2

SH_IN_P3
SH_IN_N3

SH_IN_P4

SH_IN_N4

BS_OK

BS_REF

CM_REF_IN

GND

27

PFM_CH1 _SH_IN_P1 CSSP_B+

2

PFM_CH1 _SH_IN_N1 CSSN_B+

1

PFM_CH1 _SH_IN_P2 CSSP_NV VDD

5

PFM_CH1 _SH_IN_N2 CSSN_NVVD D

4

PFM_CH1 _SH_IN_P3

12

PFM_CH1 _SH_IN_N3

13

SNN_PFM _CH1_SH_IN_P4

15

SNN_PFM _CH1_SH_IN_N4

16

ADC_IN_P

20

ADC_IN_N

19

PFM_PF_ BSOK_R

30

SNN_ADC _CUSTOM8

8

NC

SNN_ADC _CUSTOM18

18

NC

SNN_ADC _CUSTOM21

21

NC

SNN_ADC _CUSTOM31

31

NC

PFM_BG_ REF_OUT

23

PFM_BS_ REF

24

PFM_CM_ REF_IN

22

33

+3V_OVR M

VGA@

PFM_PF_ BSOK_R

0730 FAE CF suggest ,
reserve pull high only

Compal Secret Data

Compal Secret Data

2019/12/ 28 2019/12/ 28

2019/12/ 28 2019/12/ 28

2019/12/ 28 2019/12/ 28

C

Compal Secret Data

UPI@

ON@

1 2

RG2902 100_ 0402_1%VGA@

1 2

RG2904 0_04 02_5%@

1 2

RG2905 100_ 0402_1%VGA@

1 2

RG2907 0_04 02_5%@

RG2913 0_04 02_5%@

RG2915 0_04 02_5%@

CG2790

1000P_0402_50V7K

1

2

VGA@

VGA@

Deciphered Date

Deciphered Date

Deciphered Date

1000P_0402_50V7K

1

2

+3VS

+3VLP

1 2

1 2

CG2791

1

2

VGA@

D

VGA@

1 2

CG2784 47P_040 2_50V8J

1 2

CG2785 47P_040 2_50V8J

1 2

RG2918

VGA@

365K_04 02_1%

681K_0402_1%

VGA@

RG2920

ADC_IN_P < 25>

ADC_IN_N <25>

R2917 243K_04 02_1%ON @

CG2792

1000P_0402_50V7K

1 2

uPI sku

UG108

US5650Q QKI

S IC US5650 QQKI WQFN 32P P OWER MONITOR

SA0000C MA00
uPI@

D

+3V_OVR M

PFM_CH1 _SH_IN_P3

PFM_CH1 _SH_IN_N3

SNN_PFM _CH1_SH_IN_P4

SNN_PFM _CH1_SH_IN_N4

VGA@

0727 FAE CF suggest

CSSP_B+ <9 6>

CSSN_B+ <96>
CSSP_NV VDD <9 6>

CSSN_NV VDD <96>

12

12

RG2921

10K_0402_1%

CG2793

1000P_0402_50V7K

VGA@

VGA@

1

2

VGA@

RG2896

487_040 2_1%

SD00000 EL80
uPI@

RG2898

487_040 2_1%

SD00000 EL80
uPI@

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

OVR-M

OVR-M

OVR-M

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

EH50F M/B LA-H431PR10

EH50F M/B LA-H431PR10

EH50F M/B LA-H431PR10

Date : Sheet o f

Date : Sheet o f

Date : Sheet o f

5

4

3

2

1

CHANNEL-A

TOP: JDIMM1 CONN Non-ECC DIMM

D D

12

RD4

@

0_0402_5%

SA0_CHA_DIM1

12

RD3
0_0402_5%

PLACE ALL THE BELOW RESISTORS CLOSE TO SODIMM

SPD ADDRESS FOR CHANNEL A :
WRITE ADDRESS: 0XA0
READ ADDRESS: 0XA1
SA0 = 0; SA1 = 0; SA2 = 0.
DDR4 POR OPERATING SPEED: 1867 MT/S

C C

STRETCH GOAL IS 2133 MT/S

Layout Note:
Place near JDIMM1.257,259

+2.5V + 0.6VS_VTT

10U_0402_6.3V6M

10U_0402_6.3V6M

1

CD3

CD4

2

2

CD11

0.1U_0201_ 10V6K

1

1U_0201_6.3V6M

1

2

1

2

Layout Note:
PLACE THE CAP near JDIMM1. 164

B B

+0.6V_DDR_VREFC A

1

CD5

2

2

1

+3VS+3VS

12

@

12

10uF* 2
1uF*2

1U_0201_6.3V6M

CD6

2.2uF* 1

0.1uF* 1

CD12

2.2U_0402_ 6.3V6M

RD1
0_0402_5%

RD6
0_0402_5%

+3VS

12

RD5

@

0_0402_5%

SA2_CHA_DIM1S A1_CHA_DIM1

12

RD2
0_0402_5%

Layout Note:
Place near JDIMM1.258

10U_0402_6.3V6M

10U_0402_6.3V6M

1

1

CD7

CD8

2

2

BOT REVERSE (4mm)

Interleaved Memory

DDR_A_D[0..15]<7 >

DDR_A_D[16..31 ]<7>

DDR_A_D[32..47 ]<7>

DDR_A_D[48..63 ]<7>

JDIMM1B

+3VS

0.1U_0201_10V6K

2

CD1

1

PLACE NEAR TO PIN

10uF* 2
1uF*1

1U_0201_6.3V6M

1

CD9

2

Part Number:SP07001CY00
Part Value:S SOCKET LOTES ADDR0206-P001A 260P DDR4

+1.2V_VDDQ

2.2U_0402_6.3V6M

+0.6V_DDR_VREFC A

2

CD2

1

REVERSE

111

VDD1

112

VDD2

117

VDD3

118

VDD4

123

VDD5

124

VDD6

129

VDD7

130

VDD8

135

VDD9

136

VDD10

255

VDDSPD

164

VREFCA

1

VSS

2

VSS

5

VSS

6

VSS

9

VSS

10

VSS

14

VSS

15

VSS

18

VSS

19

VSS

22

VSS

23

VSS

26

VSS

27

VSS

30

VSS

31

VSS

35

VSS

36

VSS

39

VSS

40

VSS

43

VSS

44

VSS

47

VSS

48

VSS

51

VSS

52

VSS

56

VSS

57

VSS

60

VSS

61

VSS

64

VSS

65

VSS

68

VSS

69

VSS

72

VSS

73

VSS

77

VSS

78

VSS

81

VSS

82

VSS

85

VSS

86

VSS

89

VSS

90

VSS

93

VSS

94

VSS

98

VSS

262

GND

LOTES_ADDR02 06-P001A

CONN@

VDD11
VDD12

VDD13
VDD14

VDD15
VDD16

VDD17
VDD18

VDD19

VPP1
VPP2

VSS
VSS

VSS
VSS

VSS
VSS

VSS
VSS

VSS
VSS

VSS
VSS

VSS
VSS

VSS
VSS

VSS
VSS

VSS
VSS

VSS
VSS

VSS
VSS

VSS
VSS

VSS
VSS

VSS
VSS

VSS
VSS

VSS
VSS

VSS
VSS

VSS
VSS

VSS
VSS

VSS
VSS

VSS
VSS

VSS
VSS

VSS

GND

141

142
147

148
153

154
159

160
163

258

VTT

257

259

99

102
103

106
107

167
168

171
172

175
176

180
181

184
185

188
189

192
193

196
197

201
202

205
206

209
210

213
214

217
218

222
223

226
227

230
231

234
235

238
239

243
244

247
248

251
252

261

+1.2V_VDDQ

+0.6VS_VTT

+2.5V

+1.2V_VDDQ

DDR_DRAMRST #_R

EMC@

DDR_A_CLK0<7>

DDR_A_CLK#0<7>
DDR_A_CLK1<7>

DDR_A_CLK#1<7>

DDR_A_CKE0<7>

DDR_A_CKE1<7>

DDR_A_CS#0<7>

DDR_A_CS#1<7>

DDR_A_ODT0<7>

DDR_A_ODT1<7>

DDR_A_BG0<7>

DDR_A_BG1<7>
DDR_A_BA0< 7>

DDR_A_BA1< 7>

DDR_A_MA0<7>

DDR_A_MA1<7>
DDR_A_MA2<7>

DDR_A_MA3<7>
DDR_A_MA4<7>

DDR_A_MA5<7>
DDR_A_MA6<7>

DDR_A_MA7<7>
DDR_A_MA8<7>

DDR_A_MA9<7>
DDR_A_MA10<7>

DDR_A_MA11<7>
DDR_A_MA12<7>

DDR_A_MA13<7>
DDR_A_MA14_W E#<7>

DDR_A_MA15_CAS#<7>
DDR_A_MA16_RAS#<7>

DDR_A_ACT#<7>

DDR_A_PAR<7>

DDR_A_ALERT#<7>

RD7 240_0 402_1%

12

DDR_DRAMRST #_R<18,24>

D_CK_SDATA<18,24>
D_CK_SCLK<18,24>

For ECC DIMM

+1.2V_VDDQ

33P_0402_50V8J

2

CD10

1

PLACE NEAR TO SODIMM

+1.2V_VDDQ

DDR_A_CLK0

DDR_A_CLK#0
DDR_A_CLK1

DDR_A_CLK#1

DDR_A_CKE0

DDR_A_CKE1

DDR_A_CS#0

DDR_A_CS#1

DDR_A_ODT0

DDR_A_ODT1

DDR_A_BG0

DDR_A_BG1

DDR_A_BA0

DDR_A_BA1

DDR_A_MA0

DDR_A_MA1

DDR_A_MA2

DDR_A_MA3

DDR_A_MA4

DDR_A_MA5

DDR_A_MA6

DDR_A_MA7

DDR_A_MA8

DDR_A_MA9

DDR_A_MA10

DDR_A_MA11
DDR_A_MA12

DDR_A_MA13
DDR_A_MA14_W E#

DDR_A_MA15_CAS#
DDR_A_MA16_RAS#

DDR_A_ACT#

DDR_A_PAR

DDR_A_ALERT#

DIMM1_CHA_EVENT#

DDR_DRAMRST #_R

SA2_CHA_DIM1

SA1_CHA_DIM1
SA0_CHA_DIM1

JDIMM1A

REVERSE

137

CK0(T)

139

CK0#(C)

138

CK1(T)

140

CK1#(C)

109

CKE0

110

CKE1

149

S0#

157

S1#

162

S2#/C0

165

S3#/C1

155

ODT0

161

ODT1

115

BG0

113

BG1

150

BA0

145

BA1

144

A0

133

A1

132

A2

131

A3

128

A4

126

A5

127

A6

122

A7

125

A8

121

A9

146

A10_AP

120

A11

119

A12

158

A13

151

A14_WE#

156

A15_CAS#

152

A16_RAS#

114

ACT#

143

PARITY

116

ALERT#

134

EVENT#

108

RESET#

254

SDA

253

SCL

166

SA2

260

SA1

256

SA0

92

CB0_NC

91

CB1_NC

101

CB2_NC

105

CB3_NC

88

CB4_NC

87

CB5_NC

100

CB6_NC

104

CB7_NC

97

DQS8(T)

95

DQS8#(C)

12

DM0#/DBI0#

33

DM1#/DBI1#

54

DM2#/DBI2#

75

DM3#/DBI3#

178

DM4#/DBI4#

199

DM5#/DBI5#

220

DM6#/DBI6#

241

DM7#/DBI7#

96

DM8#/DBI8#

LOTES_ADDR02 06-P001A

CONN@

DQS0(T)

DQS0#(C)

DQ10

DQ11
DQ12

DQ13
DQ14

DQ15

DQS1(T)

DQS1#(C)

DQ16

DQ17
DQ18

DQ19

DQ20
DQ21

DQ22
DQ23

DQS2(T)

DQS2#(C)

DQ24
DQ25

DQ26
DQ27

DQ28
DQ29

DQ30

DQ31

DQS3(T)

DQS3#(C)

DQ32

DQ33
DQ34

DQ35
DQ36

DQ37
DQ38

DQ39

DQS4(T)

DQS4#(C)

DQ40
DQ41

DQ42
DQ43

DQ44
DQ45

DQ46
DQ47

DQS5(T)

DQS5#(C)

DQ48
DQ49

DQ50

DQ51
DQ52

DQ53
DQ54

DQ55

DQS6(T)

DQS6#(C)

DQ56

DQ57
DQ58

DQ59

DQ60
DQ61

DQ62
DQ63

DQS7(T)

DQS7#(C)

DDR_A_D0

8

DQ0

DDR_A_D1

7

DQ1

DDR_A_D2

20

DQ2

DDR_A_D3

21

DQ3

DDR_A_D4

4

DQ4

DDR_A_D5

3

DQ5

DDR_A_D6

16

DQ6

DDR_A_D7

17

DQ7

DDR_A_DQS0

13

DDR_A_DQS#0

11

DDR_A_D8

28

DQ8

DDR_A_D9

29

DQ9

DDR_A_D10

41

DDR_A_D11

42

DDR_A_D12

24

DDR_A_D13

25

DDR_A_D14

38

DDR_A_D15

37

DDR_A_DQS1

34

DDR_A_DQS#1

32

DDR_A_D16

50

DDR_A_D17

49

DDR_A_D18

62

DDR_A_D19

63

DDR_A_D20

46

DDR_A_D21

45

DDR_A_D22

58

DDR_A_D23

59

DDR_A_DQS2

55

DDR_A_DQS#2

53

DDR_A_D24

70

DDR_A_D25

71

DDR_A_D26

83

DDR_A_D27

84

DDR_A_D28

66

DDR_A_D29

67

DDR_A_D30

79

DDR_A_D31

80

DDR_A_DQS3

76

DDR_A_DQS#3

74

DDR_A_D32

174

DDR_A_D33

173

DDR_A_D34

187

DDR_A_D35

186

DDR_A_D36

170

DDR_A_D37

169

DDR_A_D38

183

DDR_A_D39

182

DDR_A_DQS4

179

DDR_A_DQS#4

177

DDR_A_D40

195

DDR_A_D41

194

DDR_A_D42

207

DDR_A_D43

208

DDR_A_D44

191

DDR_A_D45

190

DDR_A_D46

203

DDR_A_D47

204

DDR_A_DQS5

200

DDR_A_DQS#5

198

DDR_A_D48

216

DDR_A_D49

215

DDR_A_D50

228

DDR_A_D51

229

DDR_A_D52

211

DDR_A_D53

212

DDR_A_D54

224

DDR_A_D55

225

DDR_A_DQS6

221

DDR_A_DQS#6

219

DDR_A_D56

237

DDR_A_D57

236

DDR_A_D58

249

DDR_A_D59

250

DDR_A_D60

232

DDR_A_D61

233

DDR_A_D62

245

DDR_A_D63

246

DDR_A_DQS7

242

DDR_A_DQS#7

240

DDR_A_DQS0 <7>

DDR_A_DQS#0 <7>

DDR_A_DQS1 <7>

DDR_A_DQS#1 <7>

DDR_A_DQS2 <7>

DDR_A_DQS#2 <7>

DDR_A_DQS3 <7>

DDR_A_DQS#3 <7>

DDR_A_DQS4 <7>

DDR_A_DQS#4 <7>

DDR_A_DQS5 <7>

DDR_A_DQS#5 <7>

DDR_A_DQS6 <7>

DDR_A_DQS#6 <7>

DDR_A_DQS7 <7>

DDR_A_DQS#7 <7>

DIMM Side

+0.6V_DDR_VREFC A

Layout Note:
Place near JDIMM1

10uF* 6
1uF*8
330uF* 1

10U_0402_6.3V6M

10U_0402_6.3V6M

A A

1

2

10U_0402_6.3V6M

10U_0402_6.3V6M

CD16

CD17

1

1

2

2

10U_0402_6.3V6M

10U_0402_6.3V6M

CD18

CD19

1

2

5

CD21

CD20

1

1

2

1

2

2

+1.2V_VDDQ+1.2V_VDDQ

10U_0402_6.3V6M

10U_0402_6.3V6M

CD23

CD22

1

2

@

@

1U_0201_6.3V6M

1U_0201_6.3V6M

1

1

CD24

2

2

1U_0201_6.3V6M

1U_0201_6.3V6M

1

1

CD25

CD26

2

2

1U_0201_6.3V6M

1U_0201_6.3V6M

1

CD27

2

4

1U_0201_6.3V6M

1

1

CD29

CD28

CD30

2

2

+1.2V_VDDQ

1U_0201_6.3V6M

1

2

1

+

2

CD32
330U_D2_2 V_Y

CD31

2

@

CD13

0.1U_0201_ 10V6K

1

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

RD8
1K_0402_1%

1 2

1 2

2

RD10
1K_0402_1%

1 2

2019/12/28 2019/12/28

2019/12/28 2019/12/28

2019/12/28 2019/12/28

CD14

0.1U_0201_ 10V6K

1

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

RD9

2_0402_1%

2

CPU Side

+0.6V_VREFCA

VREF traces should be at least 20 mils
wide with 20 mils spacing to other

1

sign al s

CD15

0.022U_040 2_16V7K

2

RD11

24.9_0402_1 %

1 2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date : Sheet of

Date : Sheet of

Date : Sheet of

Compal Electronics, Inc.

DDRIV_CHA: DIMM0

DDRIV_CHA: DIMM0

DDRIV_CHA: DIMM0

EH50F M/B LA-H431PR10

EH50F M/B LA-H431PR10

EH50F M/B LA-H431PR10

1

23 100W ednesday, February 13, 2019

23 100W ednesday, February 13, 2019

23 100W ednesday, February 13, 2019

1.0

1.0

1.0

5

4

3

2

1

CHANNEL-B

TOP: JDIMM2 CONN

D D

PLACE ALL THE BELOW RESISTORS CLOSE TO SODIMM

SPD ADDRESS FOR CHANNEL B :
WRITE ADDRESS: 0XA4
READ ADDRESS: 0XA3
SA0 = 0; SA1 = 1; SA2 = 0.
DDR4 POR OPERATING SPEED: 1867 MT/S
STRETCH GOAL IS 2133 MT/S

C C

B B

A A

12

RD12

0_0402_5%

@

SA0_CHB_DIM3

12

RD15
0_0402_5%

Layout Note:
Place near JDIMM2.257,259

10uF* 2
1uF*2

10U_0402_6.3V6M

1

2

Layout Note:
PLACE THE CAP WITHIN 200 MILS
FROM THE JDIMM2

+0.6V_DDRB_VRE FCA

1U_0201_6.3V6M

10U_0402_6.3V6M

1

1

CD35

2

2

CD42

0.1U_0201_ 10V6K

1

Layout Note:
Place near JDIMM2

1

2

1

CD37

CD36

2

2

2

1

10U_0402_6.3V6M

10U_0402_6.3V6M

CD46

CD47

1

1

2

2

1U_0201_6.3V6M

CD38

2.2uF* 1

0.1uF* 1

CD43

2.2U_0402_ 6.3V6M

10U_0402_6.3V6M

CD48

1

2

Non-ECC DIMM

+3VS+3VS

12

RD13
0_0402_5%

12

RD16

@

0_0402_5%

10uF* 6
1uF*8
330uF* 1

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

CD49

CD50

CD52

1

1

2

2

+3VS

12

RD14

@

0_0402_5%

SA2_CHB_DIM3SA1_CHB_DIM3

12

RD17
0_0402_5%

Layout Note:
Place near JDIMM2.258

+0.6VS_VTT+2.5V

1

2

10uF* 2
1uF*1

10U_0402_6.3V6M

10U_0402_6.3V6M

1U_0201_6.3V6M

1

1

CD39

CD40

CD41

2

2

Raptor

DDR_DRAMRST #_R

2

XEMC@

1

PLACE NEAR TO JDIMM2

+1.2V_VDDQ+1.2V_VDDQ

10U_0402_6.3V6M

10U_0402_6.3V6M

CD53

1

1

2

2

@

1U_0201_6.3V6M

CD54

1

1

CD56

2

2

@

.1U_0402_16V7K

CD64

1U_0201_6.3V6M

CD57

BOT STD (4mm)

Interleaved Memory

+3VS

0.1U_0201_10V6K

2

CD33

1

PLACE NEAR TO PIN

1U_0201_6.3V6M

1U_0201_6.3V6M

1

1

CD58

2

2

1U_0201_6.3V6M

1U_0201_6.3V6M

1

1

CD59

CD60

2

2

DDR_B_D[0..15 ]<8>

DDR_B_D[16 ..31]<8>

DDR_B_D[32 ..47]<8>

DDR_B_D[48 ..63]<8>

+1.2V_VDDQ +1.2V_V DDQ

2.2U_0402_6.3V6M

+0.6V_DDRB_VRE FCA

2

CD34

1

Part Number: SP07001HW00
Part Value: S SOCKET LOTES ADDR0205-P001A DDR4 STD

1U_0201_6.3V6M

1U_0201_6.3V6M

1

1

CD62

CD61

CD63

2

2

111

112
117

118
123

124
129

130
135

136

255

164

10
14

15
18

19
22

23
26

27
30

31
35

36
39

40
43

44
47

48
51

52
56

57
60

61
64

65
68

69
72

73
77

78
81

82
85

86
89

90
93

94
98

262

JDIMM2B

STD

VDD1
VDD2

VDD3
VDD4

VDD5
VDD6

VDD7
VDD8

VDD9
VDD10

VDDSPD

VREFCA

1

VSS

2

VSS

5

VSS

6

VSS

9

VSS
VSS

VSS
VSS

VSS
VSS

VSS
VSS

VSS
VSS

VSS
VSS

VSS
VSS

VSS
VSS

VSS
VSS

VSS
VSS

VSS
VSS

VSS
VSS

VSS
VSS

VSS
VSS

VSS
VSS

VSS
VSS

VSS
VSS

VSS
VSS

VSS
VSS

VSS
VSS

VSS
VSS

VSS

GND

LOTES_ADDR02 05-P001A

CONN@

VDD11
VDD12

VDD13
VDD14

VDD15
VDD16

VDD17
VDD18

VDD19

VPP1
VPP2

VSS
VSS

VSS
VSS

VSS
VSS

VSS
VSS

VSS
VSS

VSS
VSS

VSS
VSS

VSS
VSS

VSS
VSS

VSS
VSS

VSS
VSS

VSS
VSS

VSS
VSS

VSS
VSS

VSS
VSS

VSS
VSS

VSS
VSS

VSS
VSS

VSS
VSS

VSS
VSS

VSS
VSS

VSS
VSS

VSS
VSS

VSS

GND

DDR_B_CLK 0<8>

DDR_B_CLK #0<8>

DDR_B_CLK 1<8>

DDR_B_CLK #1<8>

DDR_B_CKE0<8>

DDR_B_CKE1<8>

DDR_B_CS# 0<8>

DDR_B_ALERT #< 8>

RD18

240_0402_ 1%

DDR_DRAMRST #_R<18,23>

DDR_B_CS# 1<8>

DDR_B_ODT 0<8>

DDR_B_ODT 1<8>

DDR_B_BG0<8>

DDR_B_BG1<8>
DDR_B_BA0<8>

DDR_B_BA1<8>

DDR_B_MA0<8>
DDR_B_MA1<8>

DDR_B_MA2<8>
DDR_B_MA3<8>

DDR_B_MA4<8>
DDR_B_MA5<8>

DDR_B_MA6<8>
DDR_B_MA7<8>

DDR_B_MA8<8>
DDR_B_MA9<8>

DDR_B_MA10<8>
DDR_B_MA11<8>

DDR_B_MA12<8>
DDR_B_MA13<8>

DDR_B_MA14_ WE#<8>

DDR_B_MA15_ CAS#<8>
DDR_B_MA16_ RAS#<8>

DDR_B_ACT#<8>

DDR_B_PAR<8>

12

D_CK_SDATA<18,23>
D_CK_SCLK<18,23>

For ECC DIMM

141

142
147

148
153

154
159

160
163

258

VTT

257

259

99

102
103

106
107

167
168

171
172

175
176

180
181

184
185

188
189

192
193

196
197

201
202

205
206

209
210

213
214

217
218

222
223

226
227

230
231

234
235

238
239

243
244

247
248

251
252

261

+0.6VS_VTT

+2.5V

+1.2V_VDDQ

+1.2V_VDDQ

DDR_B_CLK 0

DDR_B_CLK #0
DDR_B_CLK 1

DDR_B_CLK #1

DDR_B_CKE0

DDR_B_CKE1

DDR_B_CS# 0

DDR_B_CS# 1

DDR_B_ODT 0

DDR_B_ODT 1

DDR_B_BG0
DDR_B_BG1

DDR_B_BA0
DDR_B_BA1

DDR_B_MA0
DDR_B_MA1

DDR_B_MA2
DDR_B_MA3

DDR_B_MA4
DDR_B_MA5

DDR_B_MA6
DDR_B_MA7

DDR_B_MA8
DDR_B_MA9

DDR_B_MA10

DDR_B_MA11

DDR_B_MA12

DDR_B_MA13

DDR_B_MA14_ WE#
DDR_B_MA15_ CAS#

DDR_B_MA16_ RAS#

DDR_B_ACT#

DDR_B_PAR
DDR_B_ALERT #

DIMM3_CHB_EVENT #

DDR_DRAMRST #_R

SA2_CHB_DIM3

SA1_CHB_DIM3
SA0_CHB_DIM3

+1.2V_VDDQ

2

CD44

0.1U_0201_ 10V6K@

1

2

CD51

0.1U_0201_ 10V6K

1

1 2

1 2

RD19
1K_0402_1%

RD21
1K_0402_1%

DIMM Side

+0.6V_DDRB_VRE FCA

1 2

RD20

2_0402_1%

2

CD45

0.1U_0201_ 10V6K

1

1

CD55

0.022U_040 2_16V7K

2

RD22

24.9_0402_1 %

1 2

JDIMM2A

STD

137

CK0(T)

139

CK0#(C)

138

CK1(T)

140

CK1#(C)

109

CKE0

110

CKE1

149

S0#

157

S1#

162

S2#/C0

165

S3#/C1

155

ODT0

161

ODT1

115

BG0

113

BG1

150

BA0

145

BA1

144

A0

133

A1

132

A2

131

A3

128

A4

126

A5

127

A6

122

A7

125

A8

121

A9

146

A10_AP

120

A11

119

A12

158

A13

151

A14_WE#

156

A15_CAS#

152

A16_RAS#

114

ACT#

143

PARITY

116

ALERT#

134

EVENT#

108

RESET#

254

SDA

253

SCL

166

SA2

260

SA1

256

SA0

92

CB0_NC

91

CB1_NC

101

CB2_NC

105

CB3_NC

88

CB4_NC

87

CB5_NC

100

CB6_NC

104

CB7_NC

97

DQS8(T)

95

DQS8#(C)

12

DM0#/DBI0#

33

DM1#/DBI1#

54

DM2#/DBI2#

75

DM3#/DBI3#

178

DM4#/DBI4#

199

DM5#/DBI5#

220

DM6#/DBI6#

241

DM7#/DBI7#

96

DM8#/DBI8#

261

GND1

262

GND2

LOTES_ADDR02 05-P001A

CONN@

DQS0(T)

DQS0#(C)

DQS1(T)

DQS1#(C)

DQS2(T)

DQS2#(C)

DQS3(T)

DQS3#(C)

DQS4(T)

DQS4#(C)

DQS5(T)

DQS5#(C)

DQS6(T)

DQS6#(C)

DQS7(T)

DQS7#(C)

CPU Side

+0.6V_B_VREFDQ

VREF traces should be at least 20 mils
wide with 20 mils spacing to other
sign al s

DQ10

DQ11
DQ12

DQ13
DQ14

DQ15

DQ16

DQ17
DQ18

DQ19

DQ20
DQ21

DQ22
DQ23

DQ24
DQ25

DQ26
DQ27

DQ28
DQ29

DQ30

DQ31

DQ32

DQ33
DQ34

DQ35
DQ36

DQ37
DQ38

DQ39

DQ40
DQ41

DQ42
DQ43

DQ44
DQ45

DQ46
DQ47

DQ48
DQ49

DQ50

DQ51
DQ52

DQ53
DQ54

DQ55

DQ56

DQ57
DQ58

DQ59

DQ60
DQ61

DQ62
DQ63

DDR_B_D0

8

DQ0

DDR_B_D1

7

DQ1

DDR_B_D3

20

DQ2

DDR_B_D7

21

DQ3

DDR_B_D4

4

DQ4

DDR_B_D5

3

DQ5

DDR_B_D2

16

DQ6

DDR_B_D6

17

DQ7

DQ8

DQ9

DDR_B_DQS0

13

DDR_B_DQS# 0

11

DDR_B_D8

28

DDR_B_D9

29

DDR_B_D11

41

DDR_B_D15

42

DDR_B_D14

24

DDR_B_D10

25

DDR_B_D12

38

DDR_B_D13

37

DDR_B_DQS1

34

DDR_B_DQS# 1

32

DDR_B_D16

50

DDR_B_D17

49

DDR_B_D19

62

DDR_B_D20

63

DDR_B_D22

46

DDR_B_D18

45

DDR_B_D23

58

DDR_B_D21

59

DDR_B_DQS2

55

DDR_B_DQS# 2

53

DDR_B_D30

70

DDR_B_D27

71

DDR_B_D26

83

DDR_B_D24

84

DDR_B_D25

66

DDR_B_D28

67

DDR_B_D29

79

DDR_B_D31

80

DDR_B_DQS3

76

DDR_B_DQS# 3

74

DDR_B_D34

174

DDR_B_D35

173

DDR_B_D36

187

DDR_B_D32

186

DDR_B_D39

170

DDR_B_D38

169

DDR_B_D37

183

DDR_B_D33

182

DDR_B_DQS4

179

DDR_B_DQS# 4

177

DDR_B_D40

195

DDR_B_D41

194

DDR_B_D42

207

DDR_B_D43

208

DDR_B_D44

191

DDR_B_D45

190

DDR_B_D46

203

DDR_B_D47

204

DDR_B_DQS5

200

DDR_B_DQS# 5

198

DDR_B_D48

216

DDR_B_D52

215

DDR_B_D50

228

DDR_B_D55

229

DDR_B_D51

211

DDR_B_D54

212

DDR_B_D49

224

DDR_B_D53

225

DDR_B_DQS6

221

DDR_B_DQS# 6

219

DDR_B_D61

237

DDR_B_D57

236

DDR_B_D60

249

DDR_B_D56

250

DDR_B_D59

232

DDR_B_D62

233

DDR_B_D63

245

DDR_B_D58

246

DDR_B_DQS7

242

DDR_B_DQS# 7

240

DDR_B_DQS0 <8>

DDR_B_DQS# 0 <8>

DDR_B_DQS1 <8>

DDR_B_DQS# 1 <8>

DDR_B_DQS2 <8>

DDR_B_DQS# 2 <8>

DDR_B_DQS3 <8>

DDR_B_DQS# 3 <8>

DDR_B_DQS4 <8>

DDR_B_DQS# 4 <8>

DDR_B_DQS5 <8>

DDR_B_DQS# 5 <8>

DDR_B_DQS6 <8>

DDR_B_DQS# 6 <8>

DDR_B_DQS7 <8>

DDR_B_DQS# 7 <8>

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2019/12/28 2019/12/28

2019/12/28 2019/12/28

2019/12/28 2019/12/28

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date : Sheet of

Date : Sheet of

2

Date : Sheet of

Compal Electronics, Inc.

DDRIV_CHB: DIMM0

DDRIV_CHB: DIMM0

DDRIV_CHB: DIMM0

EH50F M/B LA-H431PR10

EH50F M/B LA-H431PR10

EH50F M/B LA-H431PR10

1

24 100W ednesday, February 13, 2019

24 100W ednesday, February 13, 2019

24 100W ednesday, February 13, 2019

1.0

1.0

1.0

3

Raptor:Low acti ve

+1.8VSDG PU_AON

VGA@

RG3
10K_02 01_5%

1 2

2

PEX_CL KREQ#

3

NV_PGOOD

1VSDGP U_PG

NVVDD1_ PG<9 5>

PG pull up at PWR side

1.35VSD GPU_PG<37 ,93>

+3VS

12

RG2850

100K_0 201_5%

VGA@

34

D

G

5

S

QG542A
PJT138 KA_SOT 363-6

VGA@

RG3005
100K_0 201_5%

@

1 2

3

+3VS +3VS

12

RG2840

RG2841

@

@

10K_0201_5%

NVVDD1_ PG

1.35VSD GPU_PG

+3VS

12

RG2851

10K_02 01_5%

VGA@

61

D

G

2

S

DGPU_PE X_RST#

PEX_CL KREQ#

PEG_CR X_C_GT X_P0<9>

PEG_CR X_C_GT X_N0<9>

PEG_CT X_C_GR X_P0<9>

PEG_CT X_C_GR X_N0< 9>

PEG_CR X_C_GT X_P1<9>

PEG_CR X_C_GT X_N1<9>

PEG_CT X_C_GR X_P1<9>

PEG_CT X_C_GR X_N1< 9>

PEG_CR X_C_GT X_P2<9>

PEG_CR X_C_GT X_N2<9>

PEG_CT X_C_GR X_P2<9>

PEG_CT X_C_GR X_N2< 9>

PEG_CR X_C_GT X_P3<9>

PEG_CR X_C_GT X_N3<9>

PEG_CT X_C_GR X_P3<9>

PEG_CT X_C_GR X_N3< 9>

PEG_CR X_C_GT X_P4<9>

PEG_CR X_C_GT X_N4<9>

PEG_CT X_C_GR X_P4<9>

PEG_CT X_C_GR X_N4< 9>

PEG_CR X_C_GT X_P5<9>

PEG_CR X_C_GT X_N5<9>

PEG_CT X_C_GR X_P5<9>

PEG_CT X_C_GR X_N5< 9>

PEG_CR X_C_GT X_P6<9>

PEG_CR X_C_GT X_N6<9>

PEG_CT X_C_GR X_P6<9>

PEG_CT X_C_GR X_N6< 9>

PEG_CR X_C_GT X_P7<9>

PEG_CR X_C_GT X_N7<9>

PEG_CT X_C_GR X_P7<9>

PEG_CT X_C_GR X_N7< 9>

PEG_CR X_C_GT X_P8<9>

PEG_CR X_C_GT X_N8<9>

PEG_CT X_C_GR X_P8<9>

PEG_CT X_C_GR X_N8< 9>

PEG_CR X_C_GT X_P9<9>

PEG_CR X_C_GT X_N9<9>

PEG_CT X_C_GR X_P9<9>

PEG_CT X_C_GR X_N9< 9>

PEG_CR X_C_GT X_P10<9>

PEG_CR X_C_GT X_N10<9>

PEG_CT X_C_GR X_P10<9>

PEG_CT X_C_GR X_N10<9>

PEG_CR X_C_GT X_P11<9>

PEG_CR X_C_GT X_N11<9>

PEG_CT X_C_GR X_P11<9>

PEG_CT X_C_GR X_N11<9>

PEG_CR X_C_GT X_P12<9>

PEG_CR X_C_GT X_N12<9>

PEG_CT X_C_GR X_P12<9>

PEG_CT X_C_GR X_N12<9>

PEG_CR X_C_GT X_P13<9>

PEG_CR X_C_GT X_N13<9>

PEG_CT X_C_GR X_P13<9>

PEG_CT X_C_GR X_N13<9>

PEG_CR X_C_GT X_P14<9>

PEG_CR X_C_GT X_N14<9>

PEG_CT X_C_GR X_P14<9>

PEG_CT X_C_GR X_N14<9>

PEG_CR X_C_GT X_P15<9>

PEG_CR X_C_GT X_N15<9>

PEG_CT X_C_GR X_P15<9>

PEG_CT X_C_GR X_N15<9>

12

10K_0201_5%

1

B

2

A

+3VSDGP U

RG2844

10K_02 01_5%

@

GPU_FB_ EN_FGC6 _AND_3V 3

QG542B

VGA@

PJT138 KA_SOT 363-6

1 2

RG4 0_04 02_5%

CLK_PE G_VGA<15>

CLK_PE G_VGA#<15>

1

VGA@

CG1180

0.1U_020 1_10V6 K

2

UG110

VGA@

5

MC74VHC1 G09DFT 2G_SC 70-5

4

Y

VCC
G

3

+3VSDGP U

RG2845

12

10K_02 01_5%

VGA@

G

5

GPU_FB_ EN_FGC6 _AND_3V 3 <37>

@

12

2

34

D

QG539A

S

PJT138 KA_SOT 363-6

VGA@

DGPU_PE X_RST# _R

+1.8VS

RG2842

VGA@

61

D

G

QG539B

S

PJT138 KA_SOT 363-6

VGA@

12

10K_0201_5%

1VSDGP U_EN_1V8

BK44

BK26

BL26

BM26

BM27

BG26

BH26

BL27

BK27

BF26

BE26

BK29

BL29

BF27

BG27

BM29

BM30

BG29

BH29

BL30

BK30

BF29

BE29

BK32

BL32

BF30

BG30

BM32

BM33

BG32

BH32

BL33

BK33

BF32

BE32

BK35

BL35

BF33

BG33

BM35

BM36

BG35

BH35

BL36

BK36

BF35

BE35

BK38

BL38

BF36

BG36

BM38

BM39

BG38

BH38

BL39

BK39

BF38

BE38

BK41

BL41

BF39

BG39

BM41

BM42

BH41

BG41

BL42

BK42

NV_PGOO D

RG3006
100K_0 201_5%

@

1 2

UG9A

PEX_WAKE

PEX_RST

PEX_CLKREQ

PEX_REFCLK

PEX_REFCLK

PEX_TX0

PEX_TX0

PEX_RX0

PEX_RX0

PEX_TX1

PEX_TX1

PEX_RX1

PEX_RX1

PEX_TX2

PEX_TX2

PEX_RX2

PEX_RX2

PEX_TX3

PEX_TX3

PEX_RX3

PEX_RX3

PEX_TX4

PEX_TX4

PEX_RX4

PEX_RX4

PEX_TX5

PEX_TX5

PEX_RX5

PEX_RX5

PEX_TX6

PEX_TX6

PEX_RX6

PEX_RX6

PEX_TX7

PEX_TX7

PEX_RX7

PEX_RX7

PEX_TX8

PEX_TX8

PEX_RX8

PEX_RX8

PEX_TX9

PEX_TX9

PEX_RX9

PEX_RX9

PEX_TX10

PEX_TX10

PEX_RX10

PEX_RX10

PEX_TX11

PEX_TX11

PEX_RX11

PEX_RX11

PEX_TX12

PEX_TX12

PEX_RX12

PEX_TX13

PEX_TX13

PEX_RX13

PEX_RX13

PEX_TX14

PEX_TX14

PEX_RX14

PEX_RX14

PEX_TX15

PEX_TX15

PEX_RX15

PEX_RX15

COMMON

100K_0 201_5%

1/22 PCI_EXPRESS

PEX_RX12

RG2853

VGA@

5

1.8VSDG PU_MAIN_E N

1

CG920

0.1U_020 1_10V6 K

2

1 2

1

12

RG3007
100K_0 201_5%

@

1 2

VGA@

1.35VSD GPU_EN <37,93 >

VGA@

RG29
100K_0 201_5%

DG2
RB751S 40T1G_ SOD52 3-2

VGA@

4

RG2878

100K_0 201_5%

VGA@

+1.8VSDG PU_AON

12

4

+3VS

12

RG2879

+3VS

10K_02 01_5%

VGA@

12

61

D

G

2

S

34

D

G

5

S

VGA@

QG545A
PJT138 KA_SOT 363-6

1VSDGP U_EN_1V8

VGA_I2 CC_SCL

VGA_I2 CC_SDA

GPU_EVE NT# <19 >

N17E 1M

NV checking funct i on

1.8VSDG PU_MAIN_E N3V3

QG545B

VGA@

PJT138 KA_SOT 363-6

1.8VSDG PU_MAIN_E N3V3 <37 >

VGA_CL KREQ#<15>

NFGC6@

1 2

RG3015 0 _0201_ 5%

1VSDGP U_EN_3V3

GPU_FB_ EN_FGC6 _AND_3V 3

DG28

2

3

BAV70W _SOT3 23-3

FGC6@

1.0VSDGPU_EN_FGC6

+1.8VSDG PU_MAIN

VGA_SMB _CK2

2

VGA@

G

GPU_GC6 _FB_EN

GPU_GPI O20_FG C6

2

G

QG547B

61

PJT138 KA 2N SOT 363-6

D

S

QG6B

61

PJT138 KA 2N SOT 363-6

D

S

VGA@

+1.8VSDG PU_AON

1

IN B

2

IN A

to NVVDD controller

5

QG547A

G

PJT138 KA 2N SOT 363-6

34

D

S

VGA@

1 2

RG2884 10K_ 0201_5 %VGA@

1 2

RG8 10 K_0201 _5%VGA@

1 2

RG2887 10K_ 0201_5 %VGA@

1 2

RG17 1.8K_04 02_5%V GA@

1 2

RG18 1.8K_04 02_5%V GA@

1 2

RG15 10K_02 01_5%VGA@

1 2

RG504 10K_02 01_5%VGA@

1 2

RG692 10K_02 01_5%VGA@

1 2

RG2952 10K_ 0201_5 %VGA@

1 2

RG2953 10K_ 0201_5 %@

1 2

RG3002 10K_ 0201_5 %VGA@

RG3003 2.2K_ 0402_5 %VGA@

1 2

RG2954 10K_ 0201_5 %@

1 2

RG2888 10K_ 0201_5 %VGA@

1 2

RG22 10K_02 01_5%VGA@

1 2

RG2885 1K_0 402_1%VGA@

1 2

RG25 100K_0 201_5%VGA@

1 2

RG3004 100K _0201_ 5%VGA @

1 2

RG2883 10K_ 0201_5 %VGA@

VGA_SMB _DA2

+1.8VSDG PU_MAIN

VGA@

1.8VSDG PU_MAIN_E N

GPU_EVE NT#_D

GPIO12

VGA_SMB _CK2

VGA_SMB _DA2

NVVDD_P SI

ALERT#

GPIO28 _OC_W ARN#

FBVDDQ _PSIVRAM_VD D_CTL

VRAM_VD D_CTL

GPU_GPI O15

GPU_GPI O22

VRAM_VD D_CTL

GPU_GPI O20_FG C6

GPU_GC6 _FB_EN

MEM_VREF

DGPU_PE X_RST#

GPU_GPI O23

GPIO29 _IDLE_ IN_SW

1

5

QG6A

G

PJT138 KA 2N SOT 363-6

34

D

S

5

VCC

OUT Y

GND

3

UG109
NL17SZ0 8DFT2G _SC70 -5

12

0809 NV PGOOD change to +1.8VS

NV_PGOO D

Gate

1

Drain

Source

QG16

LBSS13 9WT1G _SC70 -3

VGA@

1VSDGP U_EN <3 7,94>

to EC

PCH_SML1 CLK < 18,58,66 >

PCH_SML1 DATA < 18,58,66 >

0.1U_0201_10V6K
CG2812

1

FGC6@

2

GPU_FB_ EN_FGC6 _AND

4

FGC6@

VGA_I2 CC_SCL _PWR <95>

VGA_I2 CC_SDA _PWR <95>

+1.8VSDG PU_AON

GPU_FB_ EN_FGC6 _AND

Raptor: use 1060 sequence

5

+1.8VSDG PU_AON

1

VGA@

CG942

0.1U_020 1_10V6 K

2

10K_02 01_5%

61

D

G

2

S

QG12A
PJT138 KA_SOT 363-6

VGA@

CG1176

VGA@

GPIO26 _FP_FUS E_R

1

@

CG1179

0.1U_020 1_10V6 K

2

BG5

BF12

BJ1

BJ2

BJ9

BJ11

BK24

BL23

BM23

BM24

BL24

BK23

5

5

1

IN B

2

IN A

3

+3VS

RG183

VGA@

1 2

QG12B
PJT138 KA_SOT 363-6

VGA@

+1.8VSDG PU_AON

1

2

UG9T

COMMON

12/22 MISC 1

OVERT

TS_VREF

THERMDN

THERMDP

ADC_IN

ADC_IN

JTAG_TCK

JTAG_TMS

JTAG_TDI

JTAG_TDO

JTAG_TRST

NVJTAG_SEL

VCC

4

OUT Y

UG105

GND

NL17SZ0 8DFT2G _SC70 -5

VGA@

1.8VSDG PU_MAIN_E N3V3

DG4

RB751S 40T1G_ SOD52 3-2

1 2

VGA@

UC5

1

IN

2

IN

3

VCC_PAD

VBIAS

4

ON

AOZ133 4DI-02_ DFN8-7_ 3X3

SA0000 70V00
VGA@

DGPU_PE X_RST#

GPU_GC6 _FB_EN

VGA@

PJT138 KA_SOT 363-6

OUT

GND

100K_0 201_5%

+FP_FUSE _GPU

6

7
5

I2CS_SCL

I2CS_SDA

I2CC_SCL

I2CC_SDA

I2CB_SCL

I2CB_SDA

GPIO10

GPIO11

GPIO12

GPIO13

GPIO14

GPIO15

GPIO16

GPIO17

GPIO18

GPIO19

GPIO20

GPIO21

GPIO22

GPIO23

GPIO24

GPIO25

GPIO26

GPIO27

GPIO28

GPIO29

GPIO30

1 2

DG3
RB751S 40T1G_ SOD52 3-2

1 2

10K_04 02_5%

1 2

6.2K_04 02_1%

1VSDGP U_PG<94>

+3VS

12

RG34

VGA@

34

G

5

QG14A

2.2U_040 2_6.3V6 M

+1.8VSDG PU_AON+5VAL W

BJ8

BH8

BG9

BH9

BG8

BF8

BD6

GPIO0

BB5

GPIO1

BD1

GPIO2

BE4

GPIO3

BE1

GPIO4

BG2

GPIO5

BD2

GPIO6

BD7

GPIO7

BH4

GPIO8

BJ3

GPIO9

BD3

BH3

BE6

BB1

BG4

BG1

BE2

BH1

BE3

BD4

BE5

BA5

BB6

BG3

BD5

BB2

BE7

BA4

BB4

BA3

BB3

DGPU_PE X_RST# <37 >

UG103
NL17SZ0 8DFT2G _SC70 -5

DGPU_PW R_EN<19,37>

VGA@

RG190

1

VGA@

2

DG23
RB751S 40T1G_ SOD52 3-2

@

12

RG191

1

VGA@

CG929

VGA@

0.1U_020 1_10V6 K

2

+3VS

12

RG31

10K_02 01_5%

VGA@

61

G

2

D

S

1

CG1178

VGA@

2

VGA_SMB _CK2

VGA_SMB _DA2

VGA_I2 CC_SCL
VGA_I2 CC_SDA

NVVDD_V ID

GPU_GC6 _FB_EN

GPU_EVE NT#_D

1.8VSDG PU_MAIN_E N

NVVDD_P SI

ALERT#

MEM_VREF

GPIO12

GPU_DP0 _HPD#

GPU_GPI O15

GPU_GPI O20_FG C6

GPU_GPI O22

GPU_GPI O23

FBVDDQ _PSI

GPIO26 _FP_FUS E

HDMI_HPD_G PU#

GPIO28 _OC_W ARN#

GPIO29 _IDLE_ IN_SW

+1.8VSDG PU_AON

VGA@

5

1

IN B

VCC

OUT Y

2

IN A

GND

3

VGA@

CG928

0.22U_04 02_16V 7K

NVVDD1_ EN < 37,95>

DG22

1VSDGP U_PG

2

GC6_FB _EN3V3

3

BAV70W _SOT3 23-3

VGA@

GC6_FB _EN3V3 <19,37>

D

QG14B

VGA@

S

PJT138 KA_SOT 363-6

12

RG2836

2.21K_0 402_1%

VGA@

RG11 2.2K_0 402_5%VGA @

VGA@

RG12 2.2K_0 402_5%

RG19 2.2K_0 402_5%VGA @

RG20 2.2K_0 402_5%VGA @

DG use 2.2K

NVVDD_V ID < 95>

1.8VSDG PU_MAIN_E N <37>

NVVDD_P SI <9 5>

VRAM_VD D_CTL < 93>

PWR check the FBVDDQ_PSI if need

FBVDDQ _PSI < 93>

GPIO28 _OC_W ARN# <22>

4

12

12

12

12

RG202 0 _0201 _5%@

DGPU_HOL D_RST#<1 9>

PLT_RS T_BUF#<1 6,51,52,6 8>

D D

DGPU_HOL D_RST#

PLT_RS T_BUF#

GPU_OVE RT#<58>

+1.8VSDG PU_AON +1 .8VSDG PU_MAIN

12

RG182

RG39

100K_0 201_5%

10K_02 01_5%

VGA@

VGA@

OVERT#

0803 NV reivew del NVPG protect circuit

C C

1 2

34

D

G

5

S

FP_FUSE, E H50F change to AOZ1334DI-02

2.2U_040 2_6.3V6 M

RG10

GPIO26 _FP_FUS E

B B

OVERT#<37>

ADC_IN_ P< 22>
ADC_IN_ N<22 >

T59 PAD~D@

T60 PAD~D@

T61 PAD~D@

T62 PAD~D@

A A

Check N18E-G3 PN

UG9

S IC N17E-G3-A1/8GB BGA 2152 GPU ABO !

SA0000 9PS20
@

1 2

RG518
10K_02 01_5%

VGA@

0_0402 _5%

VGA@

OVERT#

JTAG_T CLK

JTAG_T MS
JTAG_T DI

JTAG_T DO

JTAG_T RST#

12

1 2

12

RG26
10K_02 01_5%

VGA@

VGA@

RG2837

10K_0201_5%

2

1

PEX_DVDD

PEX_DVDD

PEX_DVDD

PEX_DVDD

PEX_DVDD

PEX_DVDD

PEX_CVDD

PEX_CVDD

PEX_HVDD

PEX_HVDD

PEX_HVDD

PEX_HVDD

PEX_HVDD

PEX_HVDD

PEX_HVDD

PEX_HVDD

PEX_HVDD

PEX_HVDD

PEX_HVDD

PEX_PLL_HVDD

BB35

BB36

BC35

BC36

BD33

BD36

BB33

BC33

BB26

BB27

BB29

BB32

BC26

BC27

BC29

BC30

BC32

BD27

BD30

BB30

1

CG1060

CG1068

VGA@

VGA@

VGA@

2

2

1U_0201_6.3V6M

1U_0201_6.3V6M

1

1

CG1062

CG1061

@

@

@

2

2

1U_0201_6.3V6M

1U_0201_6.3V6M

1

1

1

CG1081

CG1084

@

@

@

2

2

2

1U_0201_6.3V6M

1U_0201_6.3V6M

+PEX_PLL_HVDD

1

1

1

CG1096

CG1095

VGA@

VGA@

PEX_TERMP

@

BL44

2

2

1U_0201_6.3V6M

RG23

2.49K_0 402_1%

VGA@

CG1097

2

1U_0201_6.3V6M

12

DP0_HPD _PCH<16,39>

+3VS

12

RG2852

+3VS

10K_02 01_5%

VGA@

12

1VSDGP U_EN_3V3

61

D

G

2

QG543B

VGA@

S

PJT138 KA_SOT 363-6

34

D

G

S

VGA@

QG543A
PJT138 KA_SOT 363-6

Security C lassification

Security C lassification

Security C lassification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I NC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I NC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I NC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

HDMI_HPD_P CH<16,4 0>

Compal Secret Data

Compal Secret Data

Compal Secret Data

2019/12/28 2019/12/28

2019/12/28 2019/12/28

2019/12/28 2019/12/28

1

CG1069

VGA@

2

1U_0201_6.3V6M

1

CG1070

@

2

1U_0201_6.3V6M

1

CG1086

@

2

1U_0201_6.3V6M

1

VGA@

2

RG3001 0_0402_ 5%

4.7U_0402_6.3V6M

DP0_HPD _PCH

DGPU_PE X_RST#

NL17SZ0 8DFT2G _SC70 -5

RG198 0_0402 _5%@

HDMI_HPD_P CH

DGPU_PE X_RST#

NL17SZ0 8DFT2G _SC70 -5

RG2979 0_04 02_5%@

Deciphered Date

Deciphered Date

Deciphered Date

1

CG1063

2

1U_0201_6.3V6M

1

CG1073

2

1U_0201_6.3V6M

CG1087

@

1U_0201_6.3V6M

CG20

VGA@

4.7U_0402_6.3V6M

1 2

@

0.1U_020 1_10V6 K

DP@

1 2

VGA@

0.1U_020 1_10V6 K

VGA@

1 2

1

CG5

VGA@

2

4.7U_0402_6.3V6M

1

CG1072

@

2

1U_0201_6.3V6M

1

CG1090

VGA@

2

1U_0201_6.3V6M

1

CG11

VGA@

2

4.7U_0402_6.3V6M

+1.8VSDG PU_AON

DP@

CG340

12

1

IN B

2

IN A

UG28

+1.8VSDG PU_AON

CG2795

12

1

IN B

2

IN A

UG111

1

CG14

VGA@

2

1

CG1075

@

2

1

CG1082

2

1U_0201_6.3V6M

2

CG12

1

10U_0402_6.3V6M

+1.8VSDG PU_MAIN

5

VCC

OUT Y

GND

3

5

VCC

OUT Y

GND

3

1

VGA@

CG1076

2

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

1

CG1064

@

2

1U_0201_6.3V6M

1U_0201_6.3V6M

1

CG1083

VGA@

VGA@

2

1U_0201_6.3V6M

2

CG21

VGA@

VGA@

1

10U_0402_6.3V6M

GPIO12

4

4

1

2

2

2

12

CG7

CG1078

CG1077

CG1079

VGA@

VGA@

1

1

CG1065

@

2

VGA@

VGA@

1

1

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

1

1

1

CG1074

CG1071

CG1066

VGA@

VGA@

VGA@

2

2

2

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

+1.8VSDG PU_MAIN

1

1

1

2

2

1

CG1089

CG1088

CG1085

VGA@

VGA@

2

2

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

12

12

CG24

VGA@

VGA@

CG1094

CG1093

22U_0603_6.3V6M

22U_0603_6.3V6M

10U_0402_6.3V6M

12

DG18

RB751S 40T1G_ SOD52 3-2

VGA@

+1.8VSDG PU_AON

12

DP@

RG180

2

3

2

3

10K_04 02_5%

Gate

1

Drain

DP@

Source

QG5
LBSS13 9WT1G _SC70 -3

+1.8VSDG PU_AON

12

RG2980

10K_04 02_5%

Gate

1

Drain

VGA@

Source

QG548
LBSS13 9WT1G _SC70 -3

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

N18E-G3(1/8) PCIE,GPIO

N18E-G3(1/8) PCIE,GPIO

N18E-G3(1/8) PCIE,GPIO

Size

Size

Size

Document Number Rev

Document Number Rev

Document Number Rev

EH50F M/B LA-H431PR10

EH50F M/B LA-H431PR10

EH50F M/B LA-H431PR10

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

1

+1.0VSDG PU

12

VGA@

CG1080

22U_0603_6.3V6M

22U_0603_6.3V6M

1

CG1067

VGA@

2

1U_0201_6.3V6M

1U_0201_6.3V6M

DGPU_AC _DETEC T <19,5 8,83>

GPU_DP0 _HPD#

VGA@

HDMI_HPD_G PU#

25 100Wednes day, February 13 , 2019

25 100Wednes day, February 13 , 2019

25 100Wednes day, February 13 , 2019

1.0

1.0

1.0

BL8

BK8

BG14

BH14

BF14

BE14

BF15

BG15

BG17

BH17

1

VGA@

2

UG9Q

COMMON

10/22 IFPE

BD17

IFPE_RSET

BD15

IFPE_PLLVDD

IFPE

BC21

IFP_IOVDD

BC23

1

2

IFP_IOVDD

CG1198

1U_0201_6.3V6M

DVI/HDMI

SDA
SCL

TXC
TXC

TXD0
TXD0

TXD1
TXD1

TXD2
TXD2

DP

IFPE_AUX

IFPE_AUX

IFPE_L3

IFPE_L3

IFPE_L2

IFPE_L2

IFPE_L1

IFPE_L1

IFPE_L0

IFPE_L0

3

DP0-DP

12

RG2839
100K_0402_ 5%

VGA@

+GPU_PLLVDD_ XS_SP

+1.0VSDGPU

12

RG2838
100K_0402_ 5%

VGA@

VGA@

VGA@

RG38
1K_0402_1%

IFPEF_RSET

12

1

CG1228

VGA@

2

1U_0201_6.3V6M

1

1

CG1195

2

4.7U_0402_6.3V6M

VGA@

1

CG1196

CG1197

VGA@

2

2

1U_0201_6.3V6M

1U_0201_6.3V6M

DL-DVI

4

SDA
SCL

TXC
TXC

TXD0
TXD0

TXD1
TXD1

TXD2
TXD2

TXD3
TXD3

TXD4
TXD4

TXD5
TXD5

DVI/HDMI D P

SDA
SCL

TXC
TXC

TXD0
TXD0

TXD1
TXD1

TXD2
TXD2

SDA
SCL

TXC
TXC

IFPB_L2

TXD0

IFPB_L2

TXD0

TXD1
TXD1

TXD2
TXD2

IFPA_AUX

IFPA_AUX

IFPA_L3

IFPA_L3

IFPA_L2

IFPA_L2

IFPA_L1

IFPA_L1

IFPA_L0

IFPA_L0

IFPB_AUX

IFPB_AUX

IFPB_L3

IFPB_L3

IFPB_L1

IFPB_L1

IFPB_L0

IFPB_L0

BH11

BG11

BF21

BG21

BG23

BH23

BF23

BE23

BF24

BG24

BG12

BH12

BL18

BK18

BK20

BL20

BM21

BL21

BK21

BM20

DP0_AUXN

DP0_AUXP

DP0_AUXN <39>
DP0_AUXP <3 9>

DP0_TXN3 <39>
DP0_TXP3 <39>

DP0_TXN2 <39>
DP0_TXP2 <39>

DP0_TXN1 <39>
DP0_TXP1 <39>

DP0_TXN0 <39>
DP0_TXP0 <39>

5

RG679
1K_0402_1%

IFPAB_RSET

12

D D

+GPU_PLLVDD_ XS_SP

VGA@

VGA@

1

CG1227

2

1U_0201_6.3V6M

BD23

BD21

UG9N

COMMON

7/22 IFPAB

IFPAB_RSET

IFPAB_PLLVDD

Under GPU

BB18

+1.0VSDGPU

C C

VGA@

1

VGA@

1

CG1184

CG1185

VGA@

2

2

1U_0201_6.3V6M

1U_0201_6.3V6M

1

CG1188

2

4.7U_0402_6.3V6M

VGA@

1

1

CG1186

VGA@

2

2

1U_0201_6.3V6M

IFP_IOVDD

BB17

IFP_IOVDD

BB20

IFP_IOVDD

BB21

IFP_IOVDD

CG1187

1U_0201_6.3V6M

IFPAB

+1.0VSDGPU

+1.8VSDGPU_AON

B B

+3VSDGPU

A A

5

1 2

RG3008 0 _0603_5%@

1 2

RG3011 0 _0603_5%@

+1.8VSDGPU_AON

1 2

RG3013 0 _0603_5%@

12

12

12

1 2

RG2854 2 .49K_0402_1%@

1 2

RG2855 2 .49K_0402_1%@

1 2

RG2856 1 K_0402_5%@

RG3009
10K_0402_5 %

VGA@

RG3010
10K_0402_5 %

VGA@

VGA@

RG3012
10K_0402_5 %

VGA@

UG9R

COMMON

6/22 IFPF/USB-C

BB15

USB_DVDD

BC15

USB_DVDD

AW10

USB_HVDD

AW11

USB_HVDD

AW9

1

1

CG1214

VGA@

2

2

1U_0201_6.3V6M

USB_PLL_HVDD

CG1215

1U_0201_6.3V6M

BE12

USB_VDDP

BG6

USB_TERMP0

BH6

USB_TERMP1

BA6

USB_RBIAS

4

USB-C

SBU2
SBU1

RX1
RX1

TX1
TX1

TX2
TX2

RX2
RX2

IFPF/USB-C

DP

IFPF_AUX

IFPF_AUX

USB_SCL

USB_SDA

IFPF_L3

IFPF_L3

IFPF_L2

IFPF_L2

IFPF_L1

IFPF_L1

IFPF_L0

IFPF_L0

USB_L0

USB_L0

USB_L1

USB_L1

BM9

BM8

BK11

BL11

BM11

BM12

BL12

BK12

BK14

BL14

BA1

BA2

BA7

BA8

BB8

BB7

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2019/12/28 2019/12/28

2019/12/28 2019/12/28

2019/12/28 2019/12/28

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date : Sheet of

Date : Sheet of

Date : Sheet of

Compal Electronics, Inc.

N18E-G3(2/8) DP

N18E-G3(2/8) DP

N18E-G3(2/8) DP

EH50F M/B LA-H431PR10

EH50F M/B LA-H431PR10

EH50F M/B LA-H431PR10

1

26 100W ednesday, February 13, 2019

26 100W ednesday, February 13, 2019

26 100W ednesday, February 13, 2019

1.0

1.0

1.0

2

HDMI 2.0

DP

IFPC_AUX

IFPC_AUX

IFPD_L3

IFPD_L3

IFPD_L2

IFPD_L2

IFPD_L1

IFPD_L1

IFPD_L0

IFPD_L0

IFPC_L3

IFPC_L3

IFPC_L2

IFPC_L2

IFPC_L1

IFPC_L1

IFPC_L0

IFPC_L0

3

BF11

BE11

BM14

BM15

BL15

BK15

BK17

BL17

BM17

BM18

BL9

BK9

BF17

BE17

BF18

BG18

BG20

BH20

BF20

BE20

GPU_DP2 _CTRL_DAT <40>

GPU_DP2 _CTRL_CLK <40>

GPU_DP2 _N3 <40>

GPU_DP2 _P3 <40>

GPU_DP2 _N2 <40>

GPU_DP2 _P2 <40>

GPU_DP2 _N1 <40>

GPU_DP2 _P1 <40>

GPU_DP2 _N0 <40>

GPU_DP2 _P0 <40>

BC18

BC20

4

BD20

BD18

BB23

BC17

UG9P

COMMON

IFP_IOVDD

IFP_IOVDD

UG9O

COMMON

8/22 IFPC

IFPCD_RSET

IFPCD_PLLVDD

IFPC

IFP_IOVDD

IFP_IOVDD

9/22 IFPD

IFPD

DVI/HDMI

DVI/HDMI

SDA
SCL

TXC
TXC

TXD0
TXD0

TXD1
TXD1

TXD2
TXD2

SDA
SCL

TXC
TXC

TXD0
TXD0

TXD1
TXD1

TXD2
TXD2

DP

IFPD_AUX

IFPD_AUX

5

RG37
1K_0402 _1%

VGA@

D D

C C

+GPU_PL LVDD_XS_SP

+1.0VSDG PU

VGA@

1

1

VGA@

CG1190

2

2

4.7U_0402_6.3V6M

IFPCD_RSE T

12

1

CG1229

VGA@

2

1U_0201_6.3V6M

1

CG1191

CG1189

VGA@

2

1U_0201_6.3V6M

1U_0201_6.3V6M

Under GPU

B B

+1.0VSDG PU

VGA@

1

1

CG1194

CG1192

VGA@

2

2

1U_0201_6.3V6M

1U_0201_6.3V6M

1

A A

Security Classification

Security Classification

Security Classification

2019/12/ 28 2019/12/ 28

2019/12/ 28 2019/12/ 28

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

2019/12/ 28 2019/12/ 28

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date : Sheet o f

Date : Sheet o f

2

Date : Sheet o f

Compal Electronics, Inc.

N18E-G3(3/8) eDP,HDMI

N18E-G3(3/8) eDP,HDMI

N18E-G3(3/8) eDP,HDMI

EH50F M/B LA-H431PR10

EH50F M/B LA-H431PR10

EH50F M/B LA-H431PR10

27 100Wednesd ay, February 13, 201 9

27 100Wednesd ay, February 13, 201 9

27 100Wednesd ay, February 13, 201 9

1

1.0

1.0

1.0

5

D D

4

3

2

1

UG9B

COMMON

2/22 FBA

U51

FBA_D0<33>
FBA_D1<33>

FBA_D2<33>
FBA_D3<33>

FBA_D4<33>
FBA_D5<33>

FBA_D6<33>
FBA_D7<33>

FBA_D8<33>

FBA_D9<33>

FBA_D10<33>

FBA_D11<33>

FBA_D12<33>

FBA_D13<33>
FBA_D14<33>

FBA_D15<33>

FBA_D16<33>

FBA_D17<33>
FBA_D18<33>

FBA_D19<33>

FBA_D20<33>

FBA_D21<33>
FBA_D22<33>

FBA_D23<33>

FBA_D24<33>

FBA_D25<33>
FBA_D26<33>

FBA_D27<33>

FBA_D28<33>

FBA_D29<33>
FBA_D30<33>

FBA_D31<33>

FBA_D32<33>
FBA_D33<33>

FBA_D34<33>
FBA_D35<33>

FBA_D36<33>
FBA_D37<33>

FBA_D38<33>
FBA_D39<33>

FBA_D40<33>
FBA_D41<33>

C C

FBA_D42<33>
FBA_D43<33>

FBA_D44<33>
FBA_D45<33>

FBA_D46<33>
FBA_D47<33>

FBA_D48<33>
FBA_D49<33>

FBA_D50<33>
FBA_D51<33>

FBA_D52<33>
FBA_D53<33>

FBA_D54<33>
FBA_D55<33>

FBA_D56<33>
FBA_D57<33>

FBA_D58<33>
FBA_D59<33>

FBA_D60<33>
FBA_D61<33>

FBA_D62<33>
FBA_D63<33>

FBA_DBI0<33>
FBA_DBI1<33>

FBA_DBI2<33>
FBA_DBI3<33>

FBA_DBI4<33>
FBA_DBI5<33>

FBA_DBI6<33>
FBA_DBI7<33>

FBA_EDC0<33>

FBA_EDC1<33>

FBA_EDC2<33>

FBA_EDC3<33>
FBA_EDC4<33>

FBA_EDC5<33>

FBA_EDC6<33>
FBA_EDC7<33>

+FBX_PLLAVDD

1

CG1100

VGA@

VGA@

2

1U_0201_6.3V6M

B B

FBA_D0

U48

FBA_D1

U50

FBA_D2

U49

FBA_D3

R51

FBA_D4

R50

FBA_D5

R47

FBA_D6

U46

FBA_D7

V46

FBA_D8

Y45

FBA_D9

Y47

FBA_D10

Y46

FBA_D11

V50

FBA_D12

V47

FBA_D13

U52

FBA_D14

V51

FBA_D15

AJ44

FBA_D16

AG48

FBA_D17

AJ45

FBA_D18

AG49

FBA_D19

AF46

FBA_D20

AF47

FBA_D21

AF48

FBA_D22

AD47

FBA_D23

AD49

FBA_D24

AD48

FBA_D25

AC46

FBA_D26

AC47

FBA_D27

AA47

FBA_D28

AA46

FBA_D29

AA45

FBA_D30

Y44

FBA_D31

AW51

FBA_D32

BA52

FBA_D33

AW50

FBA_D34

BA51

FBA_D35

BA50

FBA_D36

BB50

FBA_D37

BA49

FBA_D38

AW49

FBA_D39

AV48

FBA_D40

AT49

FBA_D41

AT47

FBA_D42

AT48

FBA_D43

AT46

FBA_D44

AV51

FBA_D45

AV52

FBA_D46

AV49

FBA_D47

AJ48

FBA_D48

AJ46

FBA_D49

AJ47

FBA_D50

AK49

FBA_D51

AM47

FBA_D52

AM46

FBA_D53

AN48

FBA_D54

AN49

FBA_D55

AM44

FBA_D56

AM45

FBA_D57

AN45

FBA_D58

AN46

FBA_D59

AR48

FBA_D60

AN47

FBA_D61

AR47

FBA_D62

AR46

FBA_D63

U47

FBA_DQM0

Y48

FBA_DQM1

AG47

FBA_DQM2

AC48

FBA_DQM3

BB51

FBA_DQM4

AV50

FBA_DQM5

AM48

FBA_DQM6

AR49

FBA_DQM7

R48

FBA_DQS_WP0

V48

FBA_DQS_WP1

AF44

FBA_DQS_WP2

AA48

FBA_DQS_WP3

BB52

FBA_DQS_WP4

AT50

FBA_DQS_WP5

AK48

FBA_DQS_WP6

AR51

FBA_DQS_WP7

W45

GND

W47

GND

W49

GND

W51

GND

W6

GND

W8

GND

Y14

GND

Y15

GND

AF42

FB_REFPLL_AVDD0

L29

FB_REFPLL_AVDD1

1

CG1101

2

1U_0201_6.3V6M

10K_0402_5%

VGA@

RG53

1 2

FBA_CMD10

FBA_CMD26

FBA_CMD2

FBA_CMD18

10K_0402_5%

VGA@

RG47

1 2

FBA_DBG_RFU1

FBA_DBG_RFU2

FBA_PLL_AVDD

+1.35VSDGPU

1 2

1 2

FBA_CMD0

FBA_CMD1

FBA_CMD2

FBA_CMD3

FBA_CMD4

FBA_CMD5

FBA_CMD6

FBA_CMD7

FBA_CMD8

FBA_CMD9

FBA_CMD10

FBA_CMD11

FBA_CMD12

FBA_CMD13

FBA_CMD14

FBA_CMD15

FBA_CMD16

FBA_CMD17

FBA_CMD18

FBA_CMD19

FBA_CMD20

FBA_CMD21

FBA_CMD22

FBA_CMD23

FBA_CMD24

FBA_CMD25

FBA_CMD26

FBA_CMD27

FBA_CMD28

FBA_CMD29

FBA_CMD30

FBA_CMD31

FBA_CMD32

FBA_CMD33

FBA_CMD34

FBA_CMD35

FBA_CLK0

FBA_CLK0

FBA_CLK1

FBA_CLK1

FBA_WCK01

FBA_WCK01

FBA_WCKB01

FBA_WCKB01

FBA_WCK23

FBA_WCK23

FBA_WCKB23

FBA_WCKB23

FBA_WCK45

FBA_WCK45

FBA_WCKB45

FBA_WCKB45

FBA_WCK67

FBA_WCK67

FBA_WCKB67

FBA_WCKB67

10K_0402_5%
RG54

VGA@

10K_0402_5%
RG48

VGA@

Y51

Y52

Y49

AA52

AA51

AA50

AC50

AC51

AC52

AC49

AD52

AD51

AD50

AF50

AF51

AF52

AN50

AN51

AN52

AM49

AM52

AM51

AM50

AK50

AK51

AK52

AJ49

AJ52

AJ51

AJ50

AG50

AG51

AF49

AG52

FBA_DEBUG0

Y50

FBA_DEBUG1

AR50

AA44

AN44

AG45

AG46

AK46

AK45

U45

U44

V45

V44

AC45

AC44

AD46

AD45

AV47

AV46

AW48

AW47

AR45

AR44

AT45

AT44

+FBX_PLLAVDD

AN42

VGA@

Under GPU

CKE

FBA_CMD1

FBA_CMD0 <33>

FBA_CMD2

FBA_CMD1 <33>

FBA_CMD2 <33>

FBA_CMD3 <33>
FBA_CMD4 <33>

FBA_CMD5 <33>
FBA_CMD6 <33>

FBA_CMD7 <33>

FBA_CMD8 <33>
FBA_CMD9 <33>

FBA_CMD10 <33>
FBA_CMD11 <33>

FBA_CMD12 <33>
FBA_CMD13 <33>

FBA_CMD14 <33>
FBA_CMD15 <33>

FBA_CMD17

FBA_CMD16 <33>

FBA_CMD18

FBA_CMD17 <33>
FBA_CMD18 <33>

FBA_CMD19 <33>

FBA_CMD20 <33>
FBA_CMD21 <33>

FBA_CMD22 <33>

FBA_CMD23 <33>
FBA_CMD24 <33>

FBA_CMD25 <33>
FBA_CMD26 <33>

FBA_CMD27 <33>

FBA_CMD28 <33>

FBA_CMD29 <33>
FBA_CMD30 <33>

FBA_CMD31 <33>

FBA_CMD32 <33>
FBA_CMD33 <33>

12

RG2930 60.4_0201_1%@

12

RG2931 60.4_0201_1%@

0803 NV review 0803 NV review 0803 NV review

FBA_CLK0 <33>

FBA_CLK0# <33>

FBA_CLK1 <33>
FBA_CLK1# <33>

FBA_WCK01 <33>

FBA_WCK01# <33>

FBA_WCKB01 <33>

FBA_WCKB01# <33>

FBA_WCK23 <33>

FBA_WCK23# <33>

FBA_WCKB23 <33>

FBA_WCKB23# <33>

FBA_WCK45 <33>

FBA_WCK45# <33>

FBA_WCKB45 <33>

FBA_WCKB45# <33>

FBA_WCK67 <33>

FBA_WCK67# <33>

FBA_WCKB67 <33>
FBA_WCKB67# <33>

1

CG54

2

1U_0201_6.3V6M

1

1

VGA@

VGA@

CG1098

CG1099

2

2

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

+1.35VSDGPU

12

VGA@

CG55

22U_0603_6.3V6M

VGA@

1 2

LG6
PBY160808T-300Y-N_2P

FBB_D0<34>
FBB_D1<34>

FBB_D2<34>
FBB_D3<34>

FBB_D4<34>
FBB_D5<34>

FBB_D6<34>
FBB_D7<34>

FBB_D8<34>

FBB_D9<34>

FBB_D10<34>

FBB_D11<34>

FBB_D12<34>

FBB_D13<34>
FBB_D14<34>

FBB_D15<34>

FBB_D16<34>

FBB_D17<34>
FBB_D18<34>

FBB_D19<34>

FBB_D20<34>

FBB_D21<34>
FBB_D22<34>

FBB_D23<34>

FBB_D24<34>

FBB_D25<34>
FBB_D26<34>

FBB_D27<34>

FBB_D28<34>

FBB_D29<34>
FBB_D30<34>

FBB_D31<34>

FBB_D32<34>
FBB_D33<34>

FBB_D34<34>
FBB_D35<34>

FBB_D36<34>
FBB_D37<34>

FBB_D38<34>
FBB_D39<34>

FBB_D40<34>
FBB_D41<34>

FBB_D42<34>
FBB_D43<34>

FBB_D44<34>
FBB_D45<34>

FBB_D46<34>
FBB_D47<34>

FBB_D48<34>
FBB_D49<34>

FBB_D50<34>
FBB_D51<34>

FBB_D52<34>
FBB_D53<34>

FBB_D54<34>
FBB_D55<34>

FBB_D56<34>
FBB_D57<34>

FBB_D58<34>
FBB_D59<34>

FBB_D60<34>
FBB_D61<34>

FBB_D62<34>
FBB_D63<34>

FBB_DBI0<34>
FBB_DBI1<34>

FBB_DBI2<34>
FBB_DBI3<34>

FBB_DBI4<34>
FBB_DBI5<34>

FBB_DBI6<34>
FBB_DBI7<34>

FBB_EDC0<34>

FBB_EDC1<34>

FBB_EDC2<34>

FBB_EDC3<34>
FBB_EDC4<34>

FBB_EDC5<34>

FBB_EDC6<34>
FBB_EDC7<34>

+1.8VSDGPU_MAIN

Reset

at the end of this trace. (VRAM)

H32

D32

A33

B32

E32

G32

J30

F32

H36

G36

J36

F36

F33

D33

J32

G33

E45

D45

F45

G45

D42

E42

F42

H41

E41

F39

E39

D39

F38

E38

D36

E36

M50

P48

M51

M49

P47

P52

R46

P46

L50

L51

L52

L49

M46

L47

M48

M47

D48

C50

C48

C49

E49

E50

F49

F48

F50

D52

J50

H48

H51

J51

H49

H52

C32

E33

E44

G39

P49

L48

D50

H50

B33

E35

G44

H38

P50

J48

D51

F51

Y16

Y17

Y18

Y19

Y20

Y21

Y22

Y23

UG9C

COMMON

3/22 FBB

FBB_D0

FBB_D1

FBB_D2

FBB_D3

FBB_D4

FBB_D5

FBB_D6

FBB_D7

FBB_D8

FBB_D9

FBB_D10

FBB_D11

FBB_D12

FBB_D13

FBB_D14

FBB_D15

FBB_D16

FBB_D17

FBB_D18

FBB_D19

FBB_D20

FBB_D21

FBB_D22

FBB_D23

FBB_D24

FBB_D25

FBB_D26

FBB_D27

FBB_D28

FBB_D29

FBB_D30

FBB_D31

FBB_D32

FBB_D33

FBB_D34

FBB_D35

FBB_D36

FBB_D37

FBB_D38

FBB_D39

FBB_D40

FBB_D41

FBB_D42

FBB_D43

FBB_D44

FBB_D45

FBB_D46

FBB_D47

FBB_D48

FBB_D49

FBB_D50

FBB_D51

FBB_D52

FBB_D53

FBB_D54

FBB_D55

FBB_D56

FBB_D57

FBB_D58

FBB_D59

FBB_D60

FBB_D61

FBB_D62

FBB_D63

FBB_DQM0

FBB_DQM1

FBB_DQM2

FBB_DQM3

FBB_DQM4

FBB_DQM5

FBB_DQM6

FBB_DQM7

FBB_DQS_WP0

FBB_DQS_WP1

FBB_DQS_WP2

FBB_DQS_WP3

FBB_DQS_WP4

FBB_DQS_WP5

FBB_DQS_WP6

FBB_DQS_WP7

GND

GND

GND

GND

GND

GND

GND

GND

FBB_CMD10

FBB_CMD26

FBB_CMD2

FBB_CMD18

FBB_CMD0

FBB_CMD1

FBB_CMD2

FBB_CMD3

FBB_CMD4

FBB_CMD5

FBB_CMD6

FBB_CMD7

FBB_CMD8

FBB_CMD9

FBB_CMD10

FBB_CMD11

FBB_CMD12

FBB_CMD13

FBB_CMD14

FBB_CMD15

FBB_CMD16

FBB_CMD17

FBB_CMD18

FBB_CMD19

FBB_CMD20

FBB_CMD21

FBB_CMD22

FBB_CMD23

FBB_CMD24

FBB_CMD25

FBB_CMD26

FBB_CMD27

FBB_CMD28

FBB_CMD29

FBB_CMD30

FBB_CMD31

FBB_CMD32

FBB_CMD33

FBB_CMD34

FBB_CMD35

FBB_DBG_RFU1

FBB_DBG_RFU2

FBB_CLK0

FBB_CLK0

FBB_CLK1

FBB_CLK1

FBB_WCK01

FBB_WCK01

FBB_WCKB01

FBB_WCKB01

FBB_WCK23

FBB_WCK23

FBB_WCKB23

FBB_WCKB23

FBB_WCK45

FBB_WCK45

FBB_WCKB45

FBB_WCKB45

FBB_WCK67

FBB_WCK67

FBB_WCKB67

FBB_WCKB67

FBB_PLL_AVDD

+1.35VSDGPU

10K_0402_5%

10K_0402_5%

VGA@

RG55

RG56

VGA@

1 2

1 2

10K_0402_5%

10K_0402_5%

VGA@

RG50

RG49

VGA@

1 2

1 2

at the end of this trace. (VRAM)

B35

FBB_CMD1

VGA@

FBB_CMD2

FBB_CMD17

FBB_CMD18

1

2

CG1102

1U_0201_6.3V6M

RG2932 60.4_0201_1%@

RG2933 60.4_0201_1%@

FBB_CMD0 <34>
FBB_CMD1 <34>

FBB_CMD2 <34>
FBB_CMD3 <34>

FBB_CMD4 <34>
FBB_CMD5 <34>

FBB_CMD6 <34>
FBB_CMD7 <34>

FBB_CMD8 <34>
FBB_CMD9 <34>

FBB_CMD10 <34>
FBB_CMD11 <34>

FBB_CMD12 <34>
FBB_CMD13 <34>

FBB_CMD14 <34>
FBB_CMD15 <34>

FBB_CMD16 <34>
FBB_CMD17 <34>

FBB_CMD18 <34>
FBB_CMD19 <34>

FBB_CMD20 <34>
FBB_CMD21 <34>

FBB_CMD22 <34>
FBB_CMD23 <34>

FBB_CMD24 <34>
FBB_CMD25 <34>

FBB_CMD26 <34>
FBB_CMD27 <34>

FBB_CMD28 <34>
FBB_CMD29 <34>

FBB_CMD30 <34>

+1.35VSDGPU +1.35VSDGPU

FBB_CMD31 <34>

FBB_CMD32 <34>
FBB_CMD33 <34>

12

12

FBB_CLK0 <34>
FBB_CLK0# <34>

FBB_CLK1 <34>
FBB_CLK1# <34>

FBB_WCK01 <34>
FBB_WCK01# <34>

FBB_WCKB01 <34>
FBB_WCKB01# <34>

FBB_WCK23 <34>
FBB_WCK23# <34>

FBB_WCKB23 <34>
FBB_WCKB23# <34>

FBB_WCK45 <34>
FBB_WCK45# <34>

FBB_WCKB45 <34>
FBB_WCKB45# <34>

FBB_WCK67 <34>
FBB_WCK67# <34>

FBB_WCKB67 <34>
FBB_WCKB67# <34>

A35

D35

A36

B36

C36

C38

B38

A38

D38

A39

B39

C39

C41

B41

A41

B49

A49

A48

D47

A47

B47

C47

C45

B45

A45

D44

A44

B44

C44

C42

B42

D41

A42

FBB_DEBUG0

C35

FBB_DEBUG1

B50

J35

J41

H42

G42

F47

E47

J33

H33

G35

H35

J39

H39

F41

G41

L46

L45

M44

M45

H47

H46

J47

J46

+FBX_PLLAVDD +FBX_PLLAVDD

L38

FBC_D0<35>
FBC_D1<35>

FBC_D2<35>
FBC_D3<35>

FBC_D4<35>
FBC_D5<35>

FBC_D6<35>
FBC_D7<35>

FBC_D8<35>
FBC_D9<35>

FBC_D10<35>
FBC_D11<35>

FBC_D12<35>
FBC_D13<35>

FBC_D14<35>
FBC_D15<35>

FBC_D16<35>
FBC_D17<35>

FBC_D18<35>
FBC_D19<35>

FBC_D20<35>
FBC_D21<35>

FBC_D22<35>
FBC_D23<35>

FBC_D24<35>
FBC_D25<35>

FBC_D26<35>
FBC_D27<35>

FBC_D28<35>
FBC_D29<35>

FBC_D30<35>
FBC_D31<35>

FBC_D32<35>
FBC_D33<35>

FBC_D34<35>
FBC_D35<35>

FBC_D36<35>
FBC_D37<35>

FBC_D38<35>
FBC_D39<35>

FBC_D40<35>
FBC_D41<35>

FBC_D42<35>
FBC_D43<35>

FBC_D44<35>
FBC_D45<35>

FBC_D46<35>
FBC_D47<35>

FBC_D48<35>
FBC_D49<35>

FBC_D50<35>
FBC_D51<35>

FBC_D52<35>
FBC_D53<35>

FBC_D54<35>
FBC_D55<35>

FBC_D56<35>
FBC_D57<35>

FBC_D58<35>
FBC_D59<35>

FBC_D60<35>
FBC_D61<35>

FBC_D62<35>
FBC_D63<35>

FBC_DBI0<35>
FBC_DBI1<35>

FBC_DBI2<35>
FBC_DBI3<35>

FBC_DBI4<35>
FBC_DBI5<35>

FBC_DBI6<35>
FBC_DBI7<35>

FBC_EDC0<35>
FBC_EDC1<35>

FBC_EDC2<35>
FBC_EDC3<35>

FBC_EDC4<35>
FBC_EDC5<35>

FBC_EDC6<35>
FBC_EDC7<35>

Under GPU Under GPU

CKE

Reset

UG9D

COMMON

4/22 FBC

C6

FBC_D0

D6

FBC_D1

A6

FBC_D2

B6

FBC_D3

B4

FBC_D4

A4

FBC_D5

B3

FBC_D6

C4

FBC_D7

D9

FBC_D8

C9

FBC_D9

E9

FBC_D10

B9

FBC_D11

B8

FBC_D12

A8

FBC_D13

F6

FBC_D14

E6

FBC_D15

F18

FBC_D16

G18

FBC_D17

E18

FBC_D18

H18

FBC_D19

D15

FBC_D20

E15

FBC_D21

G17

FBC_D22

H17

FBC_D23

J15

FBC_D24

H15

FBC_D25

E14

FBC_D26

F14

FBC_D27

H11

FBC_D28

G11

FBC_D29

F11

FBC_D30

E11

FBC_D31

J29

FBC_D32

F30

FBC_D33

H29

FBC_D34

G30

FBC_D35

B30

FBC_D36

A30

FBC_D37

H30

FBC_D38

C30

FBC_D39

D27

FBC_D40

J26

FBC_D41

F27

FBC_D42

G27

FBC_D43

C27

FBC_D44

B27

FBC_D45

A27

FBC_D46

G29

FBC_D47

H20

FBC_D48

D18

FBC_D49

G20

FBC_D50

E20

FBC_D51

F23

FBC_D52

E21

FBC_D53

D21

FBC_D54

E23

FBC_D55

G24

FBC_D56

H26

FBC_D57

F24

FBC_D58

G26

FBC_D59

F26

FBC_D60

D26

FBC_D61

B26

FBC_D62

C26

FBC_D63

A5

FBC_DQM0

C8

FBC_DQM1

J18

FBC_DQM2

F12

FBC_DQM3

FBC_DQM4

D29

E27

FBC_DQM5

F20

FBC_DQM6

E26

FBC_DQM7

D5

FBC_DQS_WP0

D8

FBC_DQS_WP1

E17

FBC_DQS_WP2

E12

FBC_DQS_WP3

E30

FBC_DQS_WP4

B29

FBC_DQS_WP5

G21

FBC_DQS_WP6

E24

FBC_DQS_WP7

Y24

GND

Y25

GND

Y26

GND

Y27

GND

Y28

GND

Y29

GND

Y30

GND

Y31

GND

10K_0402_5%

VGA@

RG57

1 2

FBC_CMD10

FBC_CMD26

FBC_CMD2

FBC_CMD18

10K_0402_5%

VGA@

RG51

1 2

FBC_CMD0

FBC_CMD1

FBC_CMD2

FBC_CMD3

FBC_CMD4

FBC_CMD5

FBC_CMD6

FBC_CMD7

FBC_CMD8

FBC_CMD9

FBC_CMD10

FBC_CMD11

FBC_CMD12

FBC_CMD13

FBC_CMD14

FBC_CMD15

FBC_CMD16

FBC_CMD17

FBC_CMD18

FBC_CMD19

FBC_CMD20

FBC_CMD21

FBC_CMD22

FBC_CMD23

FBC_CMD24

FBC_CMD25

FBC_CMD26

FBC_CMD27

FBC_CMD28

FBC_CMD29

FBC_CMD30

FBC_CMD31

FBC_CMD32

FBC_CMD33

FBC_CMD34

FBC_CMD35

FBC_DBG_RFU1

FBC_DBG_RFU2

FBC_WCK01

FBC_WCK01

FBC_WCKB01

FBC_WCKB01

FBC_WCK23

FBC_WCK23

FBC_WCKB23

FBC_WCKB23

FBC_WCK45

FBC_WCK45

FBC_WCKB45

FBC_WCKB45

FBC_WCK67

FBC_WCK67

FBC_WCKB67

FBC_WCKB67

FBC_PLL_AVDD

+1.35VSDGPU

1 2

1 2

FBC_CLK0

FBC_CLK0

FBC_CLK1

FBC_CLK1

10K_0402_5%
RG58

VGA@

10K_0402_5%
RG52

VGA@

C11

FBC_CMD1

VGA@

FBC_CMD2

FBC_CMD17
FBC_CMD18

1

2

CG1103

1U_0201_6.3V6M

RG2934 60.4_0201_1%@

RG2935 60.4_0201_1%@

FBC_CMD0 <35>
FBC_CMD1 <35>

FBC_CMD2 <35>
FBC_CMD3 <35>

FBC_CMD4 <35>
FBC_CMD5 <35>

FBC_CMD6 <35>
FBC_CMD7 <35>

FBC_CMD8 <35>
FBC_CMD9 <35>

FBC_CMD10 <35>
FBC_CMD11 <35>

FBC_CMD12 <35>
FBC_CMD13 <35>

FBC_CMD14 <35>
FBC_CMD15 <35>

FBC_CMD16 <35>
FBC_CMD17 <35>

FBC_CMD18 <35>
FBC_CMD19 <35>

FBC_CMD20 <35>
FBC_CMD21 <35>

FBC_CMD22 <35>
FBC_CMD23 <35>

FBC_CMD24 <35>
FBC_CMD25 <35>

FBC_CMD26 <35>
FBC_CMD27 <35>

FBC_CMD28 <35>
FBC_CMD29 <35>

FBC_CMD30 <35>
FBC_CMD31 <35>

FBC_CMD32 <35>
FBC_CMD33 <35>

12

12

FBC_CLK0 <35>
FBC_CLK0# <35>

FBC_CLK1 <35>
FBC_CLK1# <35>

FBC_WCK01 <35>
FBC_WCK01# <35 >

FBC_WCKB01 <35>
FBC_WCKB01# <35>

FBC_WCK23 <35>
FBC_WCK23# <35 >

FBC_WCKB23 <35>
FBC_WCKB23# <35>

FBC_WCK45 <35>
FBC_WCK45# <35 >

FBC_WCKB45 <35>
FBC_WCKB45# <35>

FBC_WCK67 <35>
FBC_WCK67# <35 >

FBC_WCKB67 <35>
FBC_WCKB67# <35>

B11

A11

D11

A12

B12

C12

C14

B14

A14

D14

A15

B15

C15

C17

B17

B24

A24

D23

A23

B23

C23

C21

B21

A21

D20

A20

B20

C20

C18

B18

A18

A17

D17

FBC_DEBUG0

A9

FBC_DEBUG1

C24

J14

J23

G15

F15

H21

J21

F8

G8

G9

F9

H12

G12

G14

H14

J27

H27

E29

F29

G23

H23

H24

J24

L17

CKE

Reset

UG9E

COMMON

5/22 FBD

AK8

FBD_D0

AK4

FBD_D1

AK2

FBD_D2

AK3

FBD_D3

AK5

FBD_D4

AK6

FBD_D5

AK9

FBD_D6

AK7

FBD_D7

AG4

FBD_D8

AF9

FBD_D9

AG6

FBD_D10

AG7

FBD_D11

AJ4

FBD_D12

AJ5

FBD_D13

AJ6

FBD_D14

AG5

FBD_D15

Y6

FBD_D16

Y5

FBD_D17

V5

FBD_D18

Y4

FBD_D19

AA6

FBD_D20

AA5

FBD_D21

AC5

FBD_D22

AC4

FBD_D23

AD7

FBD_D24

AC6

FBD_D25

AF6

FBD_D26

AD6

FBD_D27

AF7

FBD_D28

AF8

FBD_D29

AF2

FBD_D30

AF3

FBD_D31

F4

FBD_D32

E1

FBD_D33

F3

FBD_D34

F5

FBD_D35

D2

FBD_D36

D1

FBD_D37

C3

FBD_D38

C2

FBD_D39

J5

FBD_D40

J4

FBD_D41

L8

FBD_D42

J2

FBD_D43

F1

FBD_D44

F2

FBD_D45

H4

FBD_D46

H5

FBD_D47

V7

FBD_D48

V8

FBD_D49

V6

FBD_D50

V9

FBD_D51

U4

FBD_D52

R5

FBD_D53

R6

FBD_D54

U8

FBD_D55

P6

FBD_D56

R9

FBD_D57

P4

FBD_D58

P5

FBD_D59

L7

FBD_D60

L6

FBD_D61

L4

FBD_D62

L5

FBD_D63

AJ1

FBD_DQM0

AG1

FBD_DQM1

AA7

FBD_DQM2

AD5

FBD_DQM3

D3

FBD_DQM4

H3

FBD_DQM5

U5

FBD_DQM6

M9

FBD_DQM7

AJ3

FBD_DQS_WP0

AG2

FBD_DQS_WP1

AA9

FBD_DQS_WP2

AF4

FBD_DQS_WP3

E3

FBD_DQS_WP4

H2

FBD_DQS_WP5

U6

FBD_DQS_WP6

M5

FBD_DQS_WP7

Y32

GND

Y33

GND

Y34

GND

Y35

GND

Y36

GND

Y37

GND

Y38

GND

Y39

GND

N18E-G3

FBD_CMD0

FBD_CMD1

FBD_CMD2

FBD_CMD3

FBD_CMD4

FBD_CMD5

FBD_CMD6

FBD_CMD7

FBD_CMD8

FBD_CMD9

FBD_CMD10

FBD_CMD11

FBD_CMD12

FBD_CMD13

FBD_CMD14

FBD_CMD15

FBD_CMD16

FBD_CMD17

FBD_CMD18

FBD_CMD19

FBD_CMD20

FBD_CMD21

FBD_CMD22

FBD_CMD23

FBD_CMD24

FBD_CMD25

FBD_CMD26

FBD_CMD27

FBD_CMD28

FBD_CMD29

FBD_CMD30

FBD_CMD31

FBD_CMD32

FBD_CMD33

FBD_CMD34

FBD_CMD35

FBD_DBG_RFU1

FBD_DBG_RFU2

FBD_CLK0

FBD_CLK0

FBD_CLK1

FBD_CLK1

FBD_WCK01

FBD_WCK01

FBD_WCKB01

FBD_WCKB01

FBD_WCK23

FBD_WCK23

FBD_WCKB23

FBD_WCKB23

FBD_WCK45

FBD_WCK45

FBD_WCKB45

FBD_WCKB45

FBD_WCK67

FBD_WCK67

FBD_WCKB67

FBD_WCKB67

FBD_PLL_AVDD

N/AFBD

AD2

AD1

AD4

AC1

AC2

AC3

AA3

AA2

AA1

AA4

Y1

Y2

Y3

V3

V2

V1

L3

L2

L1

M4

M1

M2

M3

P3

P2

P1

R4

R1

R2

R3

U3

U2

V4

U1

AD3

J3

AC9

P9

Y8

Y7

R8

R7

AJ8

AJ7

AG8

AG9

AD8

AD9

AC7

AC8

J6

J7

H7

H6

P8

P7

M7

M8

V11

+FBX_PLLAVDD

1

CG1104

VGA@

2

1U_0201_6.3V6M

Under GPU

at the end of this trace. (VRAM)

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2

Compal Secret Data

Compal Secret Data

Compal Secret Data

2019/12/28 2019/12/28

2019/12/28 2019/12/28

2019/12/28 2019/12/28

Deciphered Date

Deciphered Date

Deciphered Date

Compal El ectronics, I nc.

Compal El ectronics, I nc.

Compal El ectronics, I nc.

Title

Title

Title

N18E-G3( 4/8) MEM

N18E-G3( 4/8) MEM

N18E-G3( 4/8) MEM

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

EH50F M/B LA-H431PR10

EH50F M/B LA-H431PR10

EH50F M/B LA-H431PR10

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

28 100Wednesday, February 13, 2019

28 100Wednesday, February 13, 2019

28 100Wednesday, February 13, 2019

1.0

1.0

1.0

2

VGA@

RG2881

49.9_0402_1%

N18E CRB probe circuit

Place under GPU

+1.35VSDGPU

1

1

1

CG21810U_0 402_6.3V6M

CG21710U_0 402_6.3V6M

CG21610U_0 402_6.3V6M

VGA@

VGA@

VGA@

VGA@

2

2

2

1

CG21910U_0 402_6.3V6M

VGA@

2

1

1

1

1

CG22022U_06 03_6.3V6M

VGA@

2

1

CG22322U_0 603_6.3V6M

CG22122U_0 603_6.3V6M

CG22222U_0 603_6.3V6M

CG22422U_06 03_6.3V6M

VGA@

VGA@

VGA@

VGA@

2

2

2

2

1

1

1

1

CG22822U_0 603_6.3V6M

CG22722U_0 603_6.3V6M

CG22622U_0 603_6.3V6M

CG22522U_06 03_6.3V6M

VGA@

VGA@

VGA@

2

2

2

2

FBVDDQ

FBVDDQ

FBVDDQ

FBVDDQ

FBVDDQ

FBVDDQ

FBVDDQ

FBVDDQ

FBVDDQ

FBVDDQ

FBVDDQ

FBVDDQ

FBVDDQ

FBVDDQ

FBVDDQ

FBVDDQ

FBVDDQ

FBVDDQ

FBVDDQ

FBVDDQ

FBVDDQ

FBVDDQ

FBVDDQ

FBVDDQ

FBVDDQ

FBVDDQ

FBVDDQ

FBVDDQ

FBVDDQ

FBVDDQ

FBVDDQ

FBVDDQ

FBVDDQ

FBVDDQ

FBVDDQ

FBVDDQ

FBVDDQ

FBVDDQ

FBVDDQ

FBVDDQ

FBVDDQ

FBVDDQ

FBVDDQ

FBVDDQ

3

+1.35VSDGPU

AT43

K12

K14

K15

K17

K18

K20

K21

K23

K24

K26

K27

K29

K30

K32

K33

K35

K36

K38

K39

K41

L14

L15

L18

L20

L21

L23

L24

L26

L27

L30

L32

L33

L35

L36

L39

M10

M43

P10

P11

P42

P43

R10

R11

E52

FB_VREF

P45

R44

P44

R45

FBCAL_VDDQ

FBCAL_GND

FBCAL_TERM

1

RG67 40.2_0402_1%VGA@

1

RG68 40.2_0402_1%VGA@

1

RG69 40.2_0402_1%VGA@

2

2

2

N18E CRB change to 40.2

FB_VDDQ_SENSE <93>

+1.35VSDGPU

FB_VREF

VGA@

TC23

TP@

1

3.9P_0402_50V8C
CG2778

2

1 2

5

UG9J

+NVVDD1

COMMON

18/22 VDD_2/3

AH39

VDD

AH40

VDD

AJ13

VDD

AJ40

VDD

AK13

VGA@

VDD

AK14

VDD

AK15

VDD

AK16

VDD

AK17

VDD

AK18

VDD

AK19

VDD

AK20

VDD

AK21

VDD

AK22

VDD

AK23

VDD

AK24

VDD

AK25

VDD

AK26

VDD

AK27

VDD

AK28

VDD

AK29

VDD

AK30

VDD

AK31

VDD

AK32

VDD

AK33

VDD

AK34

VDD

AK35

VDD

AK36

VDD

AK37

VDD

AK38

VDD

AK39

VDD

AK40

VDD

AL13

VDD

AL40

VDD

AM13

VDD

AM14

VDD

AM15

VDD

AM16

VDD

AM17

VDD

AM18

VDD

AM19

VDD

AM20

VDD

AM21

VDD

AM22

VDD

AM23

VDD

AM24

VDD

AM25

VDD

AM26

VDD

AM27

VDD

AM28

VDD

AM29

VDD

AM30

VDD

AM31

VDD

AM32

VDD

AM33

VDD

AM34

VDD

AM35

VDD

AM36

VDD

AM37

VDD

AM38

VDD

AM39

VDD

AM40

VDD

AN13

VDD

AN40

VDD

AP13

VDD

AP14

VDD

AP15

VDD

AP16

VDD

AP17

VDD

AP18

VDD

AP19

VDD

AP20

VDD

AP21

VDD

AP22

VDD

BD41

VDD

BD46

VDD

BD47

VDD

BD48

VDD

BD49

VDD

BD50

VDD

BD51

VDD

BE41

VDD

BE42

VDD

BE43

VDD

BE46

VDD

BE47

VDD

10U_0402_6.3V6M

CG245

1

NVVDD_SENSE

GND_SENSE

2

D D

C C

B B

+NVVDD1

AP23

VDD

AP24

VDD

AP25

VDD

AP26

VDD

AP27

VDD

AP28

VDD

AP29

VDD

AP30

VDD

AP31

VDD

AP32

VDD

AP33

VDD

AP34

VDD

AP35

VDD

AP36

VDD

AP37

VDD

AP38

VDD

AP39

VDD

AP40

VDD

AR13

VDD

AR40

VDD

AT13

VDD

AT14

VDD

AT15

VDD

AT16

VDD

AT17

VDD

AT18

VDD

AT19

VDD

AT20

VDD

AT21

VDD

AT22

VDD

AT23

VDD

AT24

VDD

AT25

VDD

AT26

VDD

AT27

VDD

AT28

VDD

AT29

VDD

AY26

VDD

AY27

VDD

AY28

VDD

AY29

VDD

AY30

VDD

AY31

VDD

AY32

VDD

AY33

VDD

AY34

VDD

AY35

VDD

AY36

VDD

AY37

VDD

AY38

VDD

AY39

VDD

AY40

VDD

AY43

VDD

AY45

VDD

BA43

VDD

BA44

VDD

BA45

VDD

BA46

VDD

BA47

VDD

BB38

VDD

BB39

VDD

BB45

VDD

BB46

VDD

BB47

VDD

BB48

VDD

BC38

VDD

BC39

VDD

BC40

VDD

BC41

VDD

BC45

VDD

BC47

VDD

BC49

VDD

BD39

VDD

BE48

VDD

BE49

VDD

BE50

VDD

BE51

VDD

BE52

VDD

BF42

VDD

BF44

VDD

BF45

VDD

BF47

VDD

BF49

VDD

BF51

VDD

BG43

VDD

BG44

VDD

BK45

BL45

NVVDD1_VCC_SENSE <95>
NVVDD1_VSS_SENSE <95>

+NVVDD1

UG9M

COMMON

22/22 VDD_3/3

BG45

VDD

BG46

VDD

BG47

VDD

BG48

VDD

BG49

VDD

BG50

VDD

BG51

VDD

BG52

VDD

BH44

VDD

BH45

VDD

BH47

VDD

BH48

VDD

BH49

VDD

BH50

VDD

BH51

VDD

BH52

VDD

BJ44

VDD

BJ45

VDD

BJ46

VDD

BJ47

VDD

BJ48

VDD

BJ49

VDD

BJ50

VDD

BJ51

VDD

BJ52

VDD

BK47

VDD

BK48

VDD

BK49

VDD

BK50

VDD

BK51

VDD

BK52

VDD

BL46

VDD

BL47

VDD

BL48

VDD

BL49

VDD

BL50

VDD

BL51

VDD

BL52

VDD

BM47

VDD

BM48

VDD

BM49

VDD

BM50

VDD

BM51

VDD

N13

VDD

N14

VDD

N15

VDD

N16

VDD

N17

VDD

N18

VDD

N19

VDD

N20

VDD

N21

VDD

N22

VDD

N23

VDD

N24

VDD

N25

VDD

N26

VDD

N27

VDD

N28

VDD

N29

VDD

N30

VDD

N31

VDD

N32

VDD

N33

VDD

N34

VDD

N35

VDD

N36

VDD

N37

VDD

N38

VDD

N39

VDD

N40

VDD

P13

VDD

P40

VDD

R13

VDD

R14

VDD

R15

VDD

R16

VDD

R17

VDD

R18

VDD

R19

VDD

R20

VDD

R21

VDD

R22

VDD

4

+NVVDD1

R23

VDD

R24

VDD

R25

VDD

R26

VDD

R27

VDD

R28

VDD

R29

VDD

R30

VDD

R31

VDD

R32

VDD

R33

VDD

R34

VDD

R35

VDD

R36

VDD

R37

VDD

R38

VDD

R39

VDD

R40

VDD

T13

VDD

T40

VDD

U13

VDD

U14

VDD

U15

VDD

U16

VDD

U17

VDD

U18

VDD

U19

VDD

U20

VDD

U21

VDD

U22

VDD

U23

VDD

U24

VDD

U25

VDD

U26

VDD

U27

VDD

U28

VDD

U29

VDD

U30

VDD

U31

VDD

U32

VDD

U33

VDD

U34

VDD

U35

VDD

U36

VDD

U37

VDD

U38

VDD

U39

VDD

U40

VDD

V13

VDD

V40

VDD

W13

VDD

W14

VDD

W15

VDD

W16

VDD

W17

VDD

W18

VDD

W19

VDD

W20

VDD

W21

VDD

W22

VDD

W23

VDD

W24

VDD

W25

VDD

W26

VDD

W27

VDD

W28

VDD

W29

VDD

W30

VDD

W31

VDD

W32

VDD

W33

VDD

W34

VDD

W35

VDD

W36

VDD

W37

VDD

W38

VDD

W39

VDD

W40

VDD

Y13

VDD

Y40

VDD

+1.35VSDGPU

VGA@

eagle HW reserved

UG9L

COMMON

19/22 FBVDDQ

AA10

FBVDDQ

AA11

FBVDDQ

AA42

FBVDDQ

AA43

FBVDDQ

AC10

FBVDDQ

AC11

FBVDDQ

AC42

FBVDDQ

AC43

FBVDDQ

AD10

FBVDDQ

AD11

FBVDDQ

AD42

FBVDDQ

AD43

FBVDDQ

AF10

FBVDDQ

AF43

FBVDDQ

AG10

FBVDDQ

AG11

FBVDDQ

AG42

FBVDDQ

AG43

FBVDDQ

AJ10

FBVDDQ

AJ11

FBVDDQ

AJ42

FBVDDQ

AJ43

FBVDDQ

AK10

FBVDDQ

AK11

FBVDDQ

AK42

FBVDDQ

AK43

FBVDDQ

AM42

FBVDDQ

AM43

FBVDDQ

AN43

FBVDDQ

AR42

FBVDDQ

AR43

FBVDDQ

R42

FBVDDQ

R43

FBVDDQ

U10

FBVDDQ

U11

FBVDDQ

U43

FBVDDQ

V10

FBVDDQ

V42

FBVDDQ

V43

FBVDDQ

Y10

FBVDDQ

Y11

FBVDDQ

Y42

FBVDDQ

Y43

FBVDDQ

10U_0402_6.3V6M

CG243

1

2

FBVDDQ_SENSE

FB_VREF

FB_CAL_PD_VDDQ

FB_CAL_PU_GND

FB_CALTERM_GND

1

eagle HW reserved

VGA@

VGA@

+1.35VSDGPU

1

1

2

CG1118

@

1

2

10U_0402_6.3V6M

1

CG1150

CG1149

@

@

2

2

1U_0201_6.3V6M

1U_0201_6.3V6M

1

1

CG1148

CG1147

CG1155

VGA@

VGA@

2

2

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

VGA@

FBC

1

1

2

1

CG1152

CG1151

VGA@

VGA@

2

2

1U_0201_6.3V6M

1U_0201_6.3V6M

1

1

CG1153

CG1154

VGA@

VGA@

2

2

1U_0201_6.3V6M

1U_0201_6.3V6M

1

2

1

CG1156

CG1157

VGA@

VGA@

2

2

1U_0201_6.3V6M

1U_0201_6.3V6M

2

CG1158

CG1159

CG1160

VGA@

VGA@

1

1

1U_0201_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

+1.35VSDGPU

1

2

1

1

1

CG1132

10U_0402_6.3V6M

CG1134

@

@

2

2

1U_0201_6.3V6M

4

1

1

CG1135

CG1136

@

@

2

2

1U_0201_6.3V6M

1U_0201_6.3V6M

1

1

CG1140

CG1138

CG1144

@

@

@

2

2

2

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1

1

CG1133

CG1143

VGA@

VGA@

2

2

1U_0201_6.3V6M

1U_0201_6.3V6M

1

1

CG1137

CG1139

VGA@

VGA@

2

2

1U_0201_6.3V6M

1U_0201_6.3V6M

2

1

CG1141

VGA@

2

1U_0201_6.3V6M

3

2

CG1145

CG1142

CG1146

VGA@

VGA@

1

1

1U_0201_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2019/12 /28 2019/12 /28

2019/12 /28 2019/12 /28

2019/12 /28 2019/12 /28

2

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal El ectronics, Inc.

Compal El ectronics, Inc.

Compal El ectronics, Inc.

Title

Title

Title

N18E-G3(5/8) Pow er

N18E-G3(5/8) Pow er

N18E-G3(5/8) Pow er

Size

Size

Size

Document N umber Rev

Document N umber Rev

Document N umber Rev

EH50F M/B LA -H431PR10

EH50F M/B LA -H431PR10

EH50F M/B LA -H431PR10

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

29 100Wednesday, February 13, 2019

29 100Wednesday, February 13, 2019

29 100Wednesday, February 13, 2019

1.0

1.0

1.0

+1.35VSDGPU

1

@

2

A A

1

1

CG1107

CG1108

@

@

2

2

1U_0201_6.3V6M

1U_0201_6.3V6M

1

1

CG1111

CG1112

@

@

2

2

1U_0201_6.3V6M

1U_0201_6.3V6M

+1.35VSDGPU

1

@

2

1

1

CG1119

@

2

1U_0201_6.3V6M

1

1

CG1121

CG1120

CG1124

@

@

@

2

2

2

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

5

FBA

1

1

CG1114

CG1115

CG1105

@

1U_0201_6.3V6M

CG1125

@

1U_0201_6.3V6M

VGA@

VGA@

2

2

1U_0201_6.3V6M

1U_0201_6.3V6M

FBB FBD

1

1

CG1126

CG1128

@

@

2

2

1U_0201_6.3V6M

1U_0201_6.3V6M

1

1

1

CG1106

VGA@

2

2

1U_0201_6.3V6M

1

1

CG1130

VGA@

2

2

1U_0201_6.3V6M

1

CG1110

CG1109

VGA@

VGA@

2

2

1U_0201_6.3V6M

1U_0201_6.3V6M

1

1

CG1123

CG1122

VGA@

VGA@

2

2

1U_0201_6.3V6M

1U_0201_6.3V6M

2

1

CG1117

CG1116

CG1113

VGA@

VGA@

1

2

1U_0201_6.3V6M

1U_0201_6.3V6M

CG1127

1U_0201_6.3V6M

VGA@

10U_0402_6.3V6M

1

2

CG1129

CG1131

VGA@

2

1

1U_0201_6.3V6M

10U_0402_6.3V6M

5

4

3

2

1

UG9H

COMMON

21/22 GND_3/3

BL40

GND

BL43

GND

BL5

GND

BL7

GND

BM2

GND

BM3

GND

C1

GND

C29

GND

C33

GND

C5

GND

C51

GND

C52

GND

D10

GND

D12

GND

D13

GND

D16

GND

D19

GND

D22

GND

D24

GND

D25

GND

D28

GND

D30

GND

D31

GND

D34

GND

D37

GND

D4

GND

D40

GND

D43

GND

D46

GND

D49

GND

D7

GND

E2

GND

E4

GND

E48

GND

E5

GND

E51

GND

E8

GND

F10

GND

F13

GND

F16

GND

F17

GND

F19

GND

F21

GND

F22

GND

F25

GND

F28

GND

F31

GND

F34

GND

F35

GND

F37

GND

F40

GND

F43

GND

F44

GND

F46

GND

F52

GND

F7

GND

G2

GND

G38

GND

G4

GND

G47

GND

G49

GND

G51

GND

G6

GND

H1

GND

H10

GND

H13

GND

H16

GND

H19

GND

H22

GND

H25

GND

H28

GND

H31

GND

H34

GND

H37

GND

H40

GND

H43

GND

J1

GND

J12

GND

J17

GND

J20

GND

J38

GND

J49

GND

J52

GND

K13

GND

K16

GND

K19

GND

K2

GND

K22

GND

K25

GND

K28

GND

K31

GND

K34

GND

K37

GND

K4

GND

K40

GND

K45

GND

K47

GND

K49

GND

K51

GND

K6

GND

K8

GND

M52

GND

M6

GND

N10

GND

N2

GND

N4

GND

N43

GND

N45

GND

N47

GND

N49

GND

BL37

GND

N51

GND

N6

GND

N8

GND

P14

GND

P15

GND

P16

GND

P17

GND

P18

GND

P19

GND

P20

GND

P21

GND

P22

GND

P23

GND

P24

GND

P25

GND

P26

GND

P27

GND

P28

GND

P29

GND

P30

GND

P31

GND

P32

GND

P33

GND

P34

GND

P35

GND

P36

GND

P37

GND

P38

GND

P39

GND

P51

GND

R49

GND

R52

GND

T10

GND

T14

GND

T15

GND

T16

GND

T17

GND

T18

GND

T19

GND

T2

GND

T20

GND

T21

GND

T22

GND

T23

GND

T24

GND

T25

GND

T26

GND

T27

GND

T28

GND

T29

GND

T30

GND

T31

GND

T32

GND

T33

GND

T34

GND

T35

GND

T36

GND

T37

GND

T38

GND

T39

GND

T4

GND

T43

GND

T45

GND

T47

GND

T49

GND

T51

GND

T6

GND

T8

GND

U7

GND

U9

GND

V14

GND

V15

GND

V16

GND

V17

GND

V18

GND

V19

GND

V20

GND

V21

GND

V22

GND

V23

GND

V24

GND

V25

GND

V26

GND

V27

GND

V28

GND

V29

GND

V30

GND

V31

GND

V32

GND

V33

GND

V34

GND

V35

GND

V36

GND

V37

GND

V38

GND

V39

GND

V49

GND

V52

GND

W10

GND

W2

GND

W4

GND

W43

GND

Y9

GND

AW14

AW15

AW16

AW17

AW18

AW19

AW20

AW21

AW22

AW23

AW24

AW25

AW26

AW27

AW28

AW29

AW30

AW31

AW32

AW33

AW34

AW35

AW36

AW37

AW38

AW39

AW46

AW52

AR20

AR21

AR22

AR23

AR24

AR25

AR26

AR27

AR28

AR29

AR30

AR31

AR32

AR33

AR34

AR35

AR36

AR37

AR38

AR39

AR52

AT51

AT52

AU10

AU14

AU15

AU16

AU17

AU18

AU19

AU20

AU21

AU22

AU23

AU24

AU25

AU26

AU27

AU28

AU29

AU30

AU31

AU32

AU33

AU34

AU35

AU36

AU37

AU38

AU39

AU45

AU47

AU49

AU51

AV45

AW4

AW5

AW8

AY10

AY47

AY49

AY51

UG9G

COMMON

16/22 GND_2/3

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

AR4

GND

GND

AR9

GND

AT4

GND

AT5

GND

GND

GND

AT8

GND

GND

GND

GND

GND

GND

GND

GND

AU2

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

AU4

GND

GND

GND

GND

GND

AU6

GND

AU8

GND

AV4

GND

GND

AV9

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

AY2

GND

AY4

GND

GND

GND

GND

AY6

GND

AY8

GND

B1

GND

B10

GND

B13

GND

B16

GND

B19

GND

B2

GND

B22

GND

B25

GND

B28

GND

B31

GND

B34

GND

B37

GND

B40

GND

B43

GND

B46

GND

B48

GND

B52

GND

B7

GND

BA48

GND

BA9

GND

BB49

GND

BC13

GND

BC16

GND

BC19

GND

BC2

GND

BC22

GND

BC25

GND

BC28

GND

BC31

GND

BC34

GND

BC37

GND

BC4

GND

BC51

GND

BC6

GND

BC8

GND

BD26

GND

BD29

GND

BD32

GND

BD35

GND

BD38

GND

BD52

GND

BE10

GND

BE13

GND

BE15

GND

BE16

GND

BE18

GND

BE19

GND

BE21

GND

BE22

GND

BE24

GND

BE25

GND

BE27

GND

BE28

GND

BE30

GND

BE31

GND

BE33

GND

BE34

GND

BE36

GND

BE37

GND

BE39

GND

BE40

GND

BF2

GND

BF4

GND

BF41

GND

BF6

GND

BG10

GND

BG13

GND

BG16

GND

BG19

GND

BG22

GND

BG25

GND

BG28

GND

BG31

GND

BG34

GND

BG37

GND

BG40

GND

BG42

GND

BG7

GND

BH15

GND

BH18

GND

BH2

GND

BH21

GND

BH24

GND

BH27

GND

BH30

GND

BH33

GND

BH36

GND

BH39

GND

BH42

GND

BH5

GND

BJ10

GND

BJ12

GND

BJ13

GND

BJ14

GND

BJ15

GND

BJ16

GND

BJ17

GND

BJ18

GND

BJ19

GND

BJ20

GND

BJ21

GND

BJ22

GND

BJ23

GND

BJ24

GND

BJ25

GND

BJ26

GND

BJ27

GND

BJ28

GND

BJ29

GND

BJ30

GND

BJ31

GND

BJ32

GND

BJ33

GND

BJ34

GND

BJ35

GND

BJ36

GND

BJ37

GND

BJ38

GND

BJ39

GND

BJ40

GND

BJ41

GND

BJ42

GND

BJ43

GND

BJ7

GND

BK1

GND

BL1

GND

BL10

GND

BL13

GND

BL16

GND

BL19

GND

BL2

GND

BL22

GND

BL25

GND

BL28

GND

BL31

GND

B5

GND

B51

GND

UG9F

AD35

AA49

AB10

AB14

AB15

AB16

AB17

AB18
AB19

AB20

AB21

AB22

AB23

AB24

AB25

AB26

AB27

AB28

AB29

AB30

AB31

AB32

AB33

AB34

AB35

AB36

AB37

AB38

AB39

AB43

AB45

AB47

AB49

AB51

AD14

AD15

AD16

AD17

AD18

AD19

AD20

AD21

AD22

AD23

AD24

AD25

AD26

AD27

AD28

AD29

AD30

AD31

AD32

AD33

AD34

AD36

AD37

AD38

AD39

AD44

AE10

AE43

AE45

AE47

AE49

AE51

AG14

AG15

AG16

AG17

AG18

AG24

AG25

AG26

AG30

AG31

AG32

AG33

AG34

AG44

AH10

AH43

AH45

AH47

AH49

AH51

AF19

AF20

AF21

AF22

AF23

AF27

AF28

AF29

AF35

AF36

AF37

AF38

AF39

AF45

COMMON

15/22 GND_1/3

A2

GND

A26

GND

A29

GND

A3

GND

A32

GND

A50

GND

A51

GND

GND

AA8

GND

GND

GND

GND

GND

GND

GND

GND

AB2

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

AB4

GND

GND

GND

GND

GND

GND

AB6

GND

AB8

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

AE2

GND

AE4

GND

GND

GND

GND

GND

GND

AE6

GND

AE8

GND

AF1

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

AF5

GND

GND

GND

GND

GND

GND

GND

GND

GND

AG3

GND

GND

GND

GND

GND

GND

GND

GND

AH2

GND

AH4

GND

GND

GND

GND

GND

GND

AH6

GND

AH8

GND

AJ14

GND

AJ15

GND

AJ16

GND

AJ17

GND

AJ18

GND

AJ19

GND

AJ2

GND

AJ20

GND

AJ21

GND

AJ22

GND

AJ23

GND

AJ24

GND

AJ25

GND

AJ26

GND

AJ27

GND

AJ28

GND

AJ29

GND

AJ30

GND

AJ31

GND

AJ32

GND

AJ33

GND

AJ34

GND

AJ35

GND

AJ36

GND

AJ37

GND

AJ38

GND

AJ39

GND

AJ9

GND

AK1

GND

AK44

GND

AK47

GND

AL10

GND

AL14

GND

AL15

GND

AL16

GND

AL17

GND

AL18

GND

AL19

GND

AL2

GND

AL20

GND

AL21

GND

AL22

GND

AL23

GND

AL24

GND

AL25

GND

AL26

GND

AL27

GND

AL28

GND

AL29

GND

AL30

GND

AL31

GND

AL32

GND

AL33

GND

AL34

GND

AL35

GND

AL36

GND

AL37

GND

AL38

GND

AL39

GND

AL4

GND

AL43

GND

AL45

GND

AL47

GND

AL49

GND

AL51

GND

AL6

GND

AL8

GND

AM4

GND

AM9

GND

AN14

GND

AN15

GND

AN16

GND

AN17

GND

AN18

GND

AN19

GND

AN20

GND

AN21

GND

AN22

GND

AN23

GND

AN24

GND

AN25

GND

AN26

GND

AN27

GND

AN28

GND

AN29

GND

AN30

GND

AN31

GND

AN32

GND

AN33

GND

AN34

GND

AN35

GND

AN36

GND

AN37

GND

AN38

GND

AN39

GND

AN4

GND

AN5

GND

AN8

GND

AP10

GND

AP2

GND

AP4

GND

AP43

GND

AP45

GND

AP47

GND

AP49

GND

AP51

GND

AP6

GND

AP8

GND

AR14

GND

AR15

GND

AR16

GND

AR17

GND

AR18

GND

AR19

GND

BL34

GND

BC24

GND

AA13

AA14

AA15

AA16

AA17

AA18

AA19

AA20

AA21

AA22

AA23

AA24

AA25

AA26

AA27

AA28

AA29

AA30

AA31

AA32

AA33

AA34

AA35

AA36

AA37

AA38

AA39

AA40

AB13

AB40

AC13

AC14

AC15

AC16

AC17

AC18

AC19

AC20

AC21

AC22

AC23

AC24

AC25

AC26

AC27

AC28

AC29

AC30

AC31

AC32

AC33

AC34

AC35

AC36

AC37

AC38

AC39

AC40

AD13

AD40

AE13

AE14

AE15

AE16

AE17

AE18

AE19

AE20

AE21

AE22

AE23

AE24

AE25

AE26

AE27

AT30

AT31

AT32

AT33

AT34

AT35

AT36

AT37

AT38

AT39

AT40

AT42

AU13

AU40

AU43

AV13

AV14

AV15

AV16

AV17

AV18

AV19

AV20

AV21

AV22

AV23

AV24

AV25

AV26

AV27

UG9I

COMMON

17/22 VDD_1/3

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

UG9K

COMMON

+FP_FUSE_GPU

20/22 NC/1V8

D D

+FP_FUSE_ GPU

BD14

FP_FUSE_SRC

1V8_AON

1V8_AON

1V8_AON

+1.8VSDGP U_AON

BA10

BB14

BC14

SNN_SYM21_ NC1

BD24

NC

SNN_SYM21_ NC2

BM44

NC

SNN_SYM21_ NC3

BM45

NC

+NVVDD1

+1.8VSDGP U_AON

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

VGA@

4.7U_0402_6.3V6M

CG1173

CG1174

1

1

VGA@

2

2

1

1

CG1161

VGA@

2

C C

B B

A A

1

1

CG1163

CG1162

VGA@

VGA@

2

2

1U_0201_6.3V6M

1U_0201_6.3V6M

1

CG1181

CG1182

VGA@

2

1U_0201_6.3V6M

VGA@

VGA@

2

1U_0201_6.3V6M

1U_0201_6.3V6M

CG291

1

1

CG1183

VGA@

2

2

1U_0201_6.3V6M

AE28

AE29

AE30

AE31

AE32

AE33

AE34

AE35

AE36

AE37

AE38

AE39

AE40

AF13

AF14

AF15

AF16

AF17

AF18

AF24

AF25

AF26

AF30

AF31

AF32

AF33

AF34

AF40

AG13

AG19

AG20

AG21

AG22

AG23

AG27

AG28

AG29

AG35

AG36

AG37

AG38

AG39

AG40

AH13

AH14

AH15

AH16

AH17

AH18

AH19

AH20

AH21

AH22

AH23

AH24

AH25

AH26

AH27

AH28

AH29

AH30

AH31

AH32

AH33

AH34

AH35

AH36

AH37

AH38

AV28

AV29

AV30

AV31

AV32

AV33

AV34

AV35

AV36

AV37

AV38

AV39

AV40

AV42

AV43

AV44

AW13

AW40

AW42

AW43

AW44

AW45

AY13

AY14

AY15

AY16

AY17

AY18

AY19

AY20

AY21

AY22

AY23

AY24

AY25

+NVVDD1

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2019/12/28 2019/12/28

2019/12/28 2019/12/28

2019/12/28 2019/12/28

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size

Size

Size

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

Compal Electronics, Inc.

N18E-G3(6/8) Power,GND

N18E-G3(6/8) Power,GND

N18E-G3(6/8) Power,GND

Document Number Re v

Document Number Re v

Document Number Re v

EH50F M/B LA-H431PR10

EH50F M/B LA-H431PR10

EH50F M/B LA-H431PR10

1

30 100Wednesday, F ebruary 13, 2019

30 100Wednesday, F ebruary 13, 2019

30 100Wednesday, F ebruary 13, 2019

1.0

1.0

1.0