Compal LA-H271P Schematics Rev1.0

A

COMPAL CONFIDENTIAL

B

C

D

E

MODEL NAME :

1 1

PCB NO :

LA-H271P

BOM P/N : GPIO MAP:

EDA50

451AG331L01

X10_CFLH_GPIO map Rev1.5_20181224

WHITEHAVEN MLK 15

2 2

3 3

Coffee Lake H-type (2 chip)

REV : 1.0(A00)

2019.4.10

Pop Component

EMI@, RF@, ESD@ : EMI/ESD/RF part POP

CONN@ : Connector Component XDP@ : Total debug Component (pop them until ST) NDS3@ : non Deep sleep support eSPI@ : eSPI interface RTD3@ : TBT RTD3 support

Layout Dell logo

@ : Nopop Component

@EMI@, @RF@, @ESD@ : EMI/ESD/RF part nopop

DS3@ : Deep sleep support

4 4

DATE: 1707-03

PCB 26J LA-H271P REV0 MB 3

Part Number

DAB0004C000

Power CKT: 0108

Description

PCB 26J LA-H271P REV0 MB 3

A

B

LPC@ : LPC interface NRTD3@ : non TBT RTD3 support

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2016/01/01

Compal Secret Data

Deciphered Date

D

2017/01/01

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

Cover

Size Document Number Rev

Custom

LA-H271P

Tuesday, April 09, 2019

Date: Sheet of

E

1 103

1.0

A

B

C

D

E

SW3_DP1

SW4_DP2

DGFF CARD

I_eDP

D_eDP

A=C, N=D

DP MUX1 PS8461 DP1.4

DP MUX2 PS8461 DP1.4

UMA

PS175

PS8330

P.31

P.28

CPU_DP1

GPU_DP1

SW2_DP2_2_1

GPU_DP2

JIO1

HDMI

mDP

CPU_DP2

PEG x8

HDMI

DSC

CPU_DP3

JDGFF2

(0~7)

PEG x8 (8~15)

JDGFF3

DP DEMUX PS8338

P.30

mDP

SW2_DP2_2_2

JDGFF1 JDGFF2 JDGFF3

JDGFF1

HDMI2.0 Conn

mDP 1.4 Conn

JDGFF4

P.27

DGFF CARD

A=E, N=C

A=D, N=E

eDP Panel Conn

1 1

Type-C Conn

2 2

SW1_eDP

P.38

P.45

PD Cypress

CCG5

CYPD5225

eDP MUX PS8331

P.44

USB2 Port4~ 5

P.29

TBT Titan Ridge DP

P.42~45

HDMI2.0 Conn

mDP 1.2 Conn

eDP

DDI1

Intel

DDI2

CoffeeLake-H

DDI3

6+2e BGA CPU

PEG

1440 Pins

42X28mm 45W

P.6~13

DMI x4 gen 3

Intel CannonLake-H CM246 BGA

(DDR4) Memory Bus

1.2V DDR4 2400/2667 MHz (Overclocking)

USB3 Port 1

USB2 Port 1

USB3 Port 3

USB2 Port 2

USB3.1

DDR4 ECC-SO-DIMM X4

USB Power Share SLGC55544CVTR

P.23~26BANK 0, 1, 2, 3, 4 ,5 ,6 ,7

USB 3.1 JUSB1 Right side

P.71

P.71 P.71

USB Charger

USB 3.1 JUSB2 Right Side

P.71

USB Charger

874 Pins

Port 5 Port8Port 6

P.70

Intel Jacksonville WGI219LM

RJ45

P.51

RTS5243 SD5.1/MMC

SDXC

3 3

4 4

Port 1~4 Port 7

TBT DP Titan Ridge

P.42~45

Port 13~16

SATA Interposer board

SATA redriver PI3EQX6741ST

Port 21~24

M.2 Card slot_5 SSD/ Optane

P.68

Golden Finger

M.2 Card slot_4 SSD/ Optane

SATA Port4 SATA Port1A

GPIO Expander ITE IT8306

Port 17~20

P.67

PCIE BUS

Port 9~12

M.2 Card slot_3 SSD/ Optane

P.67

P.59

M.2 Card slot_2 WWAN/LTE /Cache

M.2 Card slot_1 WLAN/BT /WiGig

P.52

USB2 Port8 USB2 Port 6

USB3 Port2

Micro SIM Card

P.52

I2C BUS

SMSC KBC MEC5106

change model name

FAN CONN

P.77

P.52

P.58

KB/TP CONN

I2C BUS

P.62

24X25mm

eSPI

SPI

Free Fall Sensor

LNG2DMTR

P.14~22

Winbon sop8

W25Q256FVFIQ

256Mb 4K sector

TPM2.0 NPCT750JABYXF

change model name

P.54

USB2.0

HD Audio

P.17

P.65

Audio Codec ALC3281

P.56

USB2 Port 11

USB2 Port 9

USB Port 10

P.41

On USH/B

Universal Jack

Digital Camera

Touch screen

LYNX(CV2) BRCM58102

Int. Speaker

P.56

P.38

TDA8034HN

Smart Card

SPI

RFID/NFC

SPI

Fingerprint CONN

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

C

2016/01/01

Compal Secret Data

Deciphered Date

D

2017/01/01

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

Block Diagram

Size Document Number Rev

Custom

LA-H271P

Tuesday, April 09, 2019

Date: Sheet of

E

2 103

1.0

5

4

3

2

1

POWER STATES

State

S0 (Full ON) / M0

D D

S3 (Suspend to RAM) / M1 LOW HIGH HIGH HIGH

S4 (Suspend to DISK) / M1 LOW HIGH LOW

S5 (SOFT OFF) / M1 LOW LOWLOW

S3 (Suspend to RAM) / M-OFF

S4 (Suspend to DISK) / M-OFF HIGH

S5 (SOFT OFF) / M-OFF

Signal

SLP S3#

HIGH

LOW HIGH HIGH HIGH

LOW LOW LOW

LOW LOW LOW LOW

SLP

SLP S4#

HIGH HIGH HIGH

LOW

S5#

S4 STATE#

ALWAYS PLANE

ON

RUN

CLOCKS

PLANE

ON ON

OFF

OFF OFF

OFF

OFF OFF

PCH

PM TABLE

+PWR_SRC

C C

State

S0

S3

S5 S4/AC

S5 S4/AC don't exist

B B

power plane

+5V_ALW

+3.3V_ALW

+3.3V_ALW2 +1.0V_VCCST

+3.3V_ALW_DSW

+3.3V_ALW_PCH

+3.3V_RTC_LDO

+1.8V_ALW

+1.0V_PRIM

+1.8V_PRIM

ON

OFF

+3.3V_SUS

+1.2V_MEM

+2.5V_MEM +VCC_GT

ON ON

ON

OFF

+5V_RUN

+3.3V_RUN

+1.2V_RUN

+3.3V_DGFF

+5V_DGFF +VCC_SA

+DGFF_PWR_SRC

+0.675V_DDR_VTT

OFFON

OFF

(M-OFF)

+VCC_CORE

+VCC_IO

+1.0V_VCCSTG

+1.8V_RUN

ON

OFF

USH

USB2 PORT# DESTINATION

1

2

3

4

5

6

7

JUSB1

JUSB2

NA

Cypress PD

NA

M.2 Slot-2 (WWAN/LTE)8

9

10

11

12

13

14

0

1

PCI EXPRESS

PORT 1~4

17" NA/ 15" Touch screen

USH

Camera

NA

M.2 Slot-1 (BT)

BIO

NA

DESTINATION

TBT-Titan Ridge

USB3.0 DESTINATION

Port 1

Port 2

Port 3

Port 4

Port 5

A A

5

Port 6

JUSB1

M.2 Slot-2 (WWAN/LTE)

JUSB2

NA

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

SATA

SATA 0B

SATA 1A

SATA 2

SATA 3

SATA 4

SATA 5

2016/01/01

DESTINATION

NA

SLOT3 SSD

NA

SATA HDD

NA

Compal Secret Data

Deciphered Date

PORT 5

PORT 6

PORT 7

PORT 8

PORT9~12

PORT13~16

PORT17~20

PORT21~24

2017/01/01

2

10/100/1G LOM

MMI(Card reader)

M.2 Slot-1 (WLAN/Wigig)

M.2 Slot-2 (WWAN/LTE)

SLOT3 SSD 2280/ Optane

NA

SLOT4 SSD 2280/ Optane

SLOT5 PCIE ONLY 2280/ Optane

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

Notes List

Size Document Number Rev

Custom

LA-H271P

Tuesday, April 09, 2019

Date: Sheet of

1

3 103

1.0

5

4

3

2

1

TYPE-C

+5V_ALW

+Vbus_1(5V~20V) +Vbus_2(5V~20V)

CYPD5225 (UT5)

+TBTB_VBUS(5V~20V)

+TBTA_VBUS(5V~20V)

D D

ADAPTER

BATTERY

C C

CHARGER

+PWR_SRC

EN_INVPWR

3.3V_RUN_GFX_ON

IMVP_VR_ON

RUN_ON_EC

SIO_SLP_S3#

PCH_PRIM_EN

+3.3V_ALW_R

SIO_SLP_S4#

RT8207 (PU200)

SLOT5_SSD_PWR_EN

+3.3V_SSD5

SLOT4_SSD_PWR_EN

AOZ1336 (UZ58)

+3.3V_SSD4

3.3V_RUN_GFX_ON_EC

EM5209VF

(UZ41)

+3.3V_DGFF

B B

+0.6V_DDR_VTT

+1.2V_MEM

SLOT3_SSD_PWR_EN

EM5209VF

(UZ9)

+3.3V_SSD3

NCP81215MNTXG

SY8288BRAC

(PU501)

EM5209VF

(UZ40)

+3.3V_RUN

DMP3050LVT

(QV1)

AO4435L

(QZ19)

(PU1100)

RUN_ON

TPS51212

(PU800)

+3.3V_ALW

RUN_ON

ALWON

TPS51285B

(PU100)

SIO_SLP_LAN#

SIO_SLP_WLAN#

AUX_EN_WOWL

EM5209VF

(UZ44)

+3.3V_WWAN

+3.3V_WLAN

+BL_PWR_SRC

+DGFF_PWR_SRC

+VCC_CORE

SY8288RAC

(PU300)

ALWON

PCH_ALW_ON

AOZ1336

(UZ42)

+3.3V_ALW_PCH

+VCC_GT

3.3V_WWAN_EN

AOZ1336

(UZ7)

+3.3V_LAN

+1.0VS_VCCIO

+1.0V_PRIM

TPS51285B

(PU101)

+5V_ALW2 +3.3V_ALW2

(PU500)

+VCC_SA

SIO_SLP_S0#

RUN_ON

SIO_SLP_S4#

+5V_ALW

+5V_ALW_RSY8288CRAC

ENVDD_PCH

DGFF_ENVDD

LCD_VCC_TEST_EN

G524B1T11U

(UV24)

+LCDVDD

TPS22961

(UZ21)

PCH_PRIM_EN

SY8003DFC

(PU900)

+1.8V_PRIM

+3.3V_ALW

+3.3V_TBT_SX

+1.0V_VCCSTG(UZ19)

+1.0V_VCCST

RUN_ON

USB_POWERSHARE_E N#

EM5209VF

HDD_IFDET RUN_ON

3.3V_RUN_GFX_ON_EC

SIO_SLP_S4#

SY8003DFC

(PU400)

+2.5V_MEM

(UZ40)

AOZ1336

SLGC55544CVTR

+TBTA_VBUS

+TBTB_VBUS

+DC_IN

+PWR_SRC

(UZ23)

(UI3)

EM5209VF

(UZ41)

(UI1)

(UI2)

+5V_RUN

+5V_HDD

RT9069 (UT7)

+5V_RUN_AUDIO

+5V_USB_PWR1

+5V_DGFF

+5V_USB_PWR2

+5V_USB_PWR3

+3.3V_VDD_PIC

PCH_PRIM_EN

SIO_SLP_S4#

AOZ1336 (UZ26)

+VCC_SFR_OC

SIO_SLP_S4#

AOZ1336

(UZ43)

+1.2V_RUN

3.3V_CAM_EN#

LP2301ALT1G

(QZ1)

RUN_ON

+3.3V_RUN_AUDIO

AOZ1336

(UZ45)

+1.8V_RUN

+CAMERA_VDD

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2016/01/01

Compal Secret Data

Deciphered Date

2

2017/01/01

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

Power MAP

Size Document Number Rev

Custom

LA-H271P

Tuesday, April 09, 2019

Date: Sheet of

1

4 103

1.0

5

4

3

2

1

Timing Diagram for S5 to S0 mode

VCCST_PWRGD

D D

12

15

17

12

H_PWRGD

PCH_PLTRST#

0.6V_DDR_VTT_ON

CPU

VCCST_PWRGD

PROCPWRGD

PLTRST#

DDR_VTT_CNTL

VDDQ VDDQC VCCPLL_OC

+1.0V_PRIM

VCCPRIM_1P0 VCCPRIM_CORE DCPDSW_1P0

VCCAPLL_1P0 VCCCLK1~6 VCCMPHYGT_1P0

C C

3

+3.3V_ALW

+3.3V_SPI

+3.3V_ALW_DSW

+3.3V_ALW_PCH

5

+1.8V_PRIM

6

+RTC_CELL

PCH_PLTRST#

17

PCH_DPWROK

4

VCCSRAM_1P0 VCCAMPHYPLL_1P0 VCCAPLLEBB

VCCDSW_3P3

VCCHDA VCCSPI VCCPRIM_3P3 VCCPGPPA~E VCCRTCPRIM

VCCPGPPA

VCCRTC

PLTRST#

DSW_PWROK

PCH

+VCC_CORE

VCC

+1.0VS_VCCIO

VCCIO

+VCC_GT

VCCGT

+1.35V_MEM

+1.0V_VCCST

VCCST VCCSTG VCCPLL

+VCC_SA

VCCSA

PWRBTN#

RSMRST#

SLP_SUS#

SLP_S5#

SLP_S4#

SLP_S3#

SLP_A#

SLP_LAN#

SLP_WLAN#/GPD9

SYS_PWROK

PCH_PWROK

VCCST_PWRGD

PROCPWRGD

SIO_PWRBTN#

PCH_RSMRST#

SIO_SLP_SUS#

SIO_SLP_S5#

SIO_SLP_S4#

SIO_SLP_S3#

SIO_SLP_LAN#

SIO_SLP_WLAN#

RESET_OUT#

PCH_PWROK

VCCST_PWRGD

H_PWRGD

11

+1.0V_PRIM

8

5

10

11

16

14

12

15

TPS22961

7

9

SIO_SLP_S0#

RUN_ON

13

+VCC_SA

+VCC_CORE

+VCC_GT

10

+PWR_SRC

ISL95857

PCH_PWROK

14

ADAPTER

BATTERY

7

4

16

SIO_SLP_SUS#

5

SIO_SLP_S4#

SIO_SLP_S5#

9

SIO_SLP_LAN#

SIO_SLP_S3#

11

SIO_SLP_A#SIO_SLP_A#

PCH_RSMRST#

PCH_DPWROK

RESET_OUT#

IMVP_VR_ON

12

Power Button

2AC1BAT

+PWR_SRC

ALWON

+PWR_SRC

5

SIO_SLP_SUS#

@PCH_ALW_ON

EN_INVPWR

SIO_SLP_S4#

0.6V_DDR_VTT_ON

SYX198EC 5105

SYX198

+3.3V_ALW

EM5209VF

+PWR_SRC

AO6405

+5V_ALW2 +5V_ALW

+3.3V_ALW2 +3.3V_ALW

+PWR_SRC

RT8207MZ

+3.3V_RTC_LDO

+3.3V_ALW_PCH

+BL_PWR_SRC

+1.2V_MEM

+0.6V_DDR_VTT

12

1BAT

2AC

5

Pop option

+3.3V_SPI

18

VDDQ

VTT

DDR

+3.3V_ALW

B B

+LCDVDD

AP2821K

ENVDD_PCH

+3.3V_ALW

11

EM5209VF+3.3V_LAN

SIO_SLP_LAN#

+3.3V_RUN

LP2301ALT1G+3.3V_CAM

3.3V_CAM_EN#

EDP_VDDEN

SLP_LAN#

GPD7

11

SIO_SLP_WLAN#

EC 5105

11

RUN_ON

+5V_ALW

EM5209VF

+3.3V_ALW

EM5209VF

+5V_RUN

+3.3V_RUN

+5V_HDD

+3.3V_HDD

+PWR_SRC

+1.0V_PRIM

6

A A

5

6

+1.8V_PRIM

TLV62130

+3.3V_ALW

TLV62130

SIO_SLP_SUS#

4

+3.3V_WLAN EM5209VF

11

3

+3.3V_ALW

@SIO_SLP_WLAN#

AUX_EN_WOWL

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2016/01/01

Compal Secret Data

2

Deciphered Date

TLV62130

2017/01/01

+1.0VS_VCCIO

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

Power Sequence

Size Document Number Rev

Custom

LA-H271P

Tuesday, April 09, 2019

Date: Sheet of

1

5 103

1.0

5

4

3

2

1

D D

PEG_CRX _GTX_P[0..15]

PEG_CRX _GTX_N[0..15]

PEG_CTX _C_GRX_P[0..15]

PEG_CTX _C_GRX_N[0..15]

C C

+1.0VS_V CCIO

RC2 24.9_040 2_1%

Trace width=5 mils ,Spacing=15mil

B B

Max length= 600 mils.

PEG_CRX _GTX_P[0..15] <27>

PEG_CRX _GTX_N[0..15] <27>

PEG_CTX _C_GRX_P[0..15] <27>

PEG_CTX _C_GRX_N[0..15] <27>

1 2

PEG_COM P

DMI_CRX_P TX_P0<15> DMI_CRX_P TX_N0<15>

DMI_CRX_P TX_P1<15> DMI_CRX_P TX_N1<15>

DMI_CRX_P TX_P2<15> DMI_CRX_P TX_N2<15>

DMI_CRX_P TX_P3<15> DMI_CRX_P TX_N3<15>

PEG_CRX _GTX_P15 PEG_CRX _GTX_N15

PEG_CRX _GTX_P14 PEG_CRX _GTX_N14

PEG_CRX _GTX_P13 PEG_CRX _GTX_N13

PEG_CRX _GTX_P12 PEG_CRX _GTX_N12

PEG_CRX _GTX_P11 PEG_CRX _GTX_N11

PEG_CRX _GTX_P10 PEG_CRX _GTX_N10

PEG_CRX _GTX_P9 PEG_CRX _GTX_N9

PEG_CRX _GTX_P8 PEG_CRX _GTX_N8

PEG_CRX _GTX_P7 PEG_CRX _GTX_N7

PEG_CRX _GTX_P6 PEG_CRX _GTX_N6

PEG_CRX _GTX_P5 PEG_CRX _GTX_N5

PEG_CRX _GTX_P4 PEG_CRX _GTX_N4

PEG_CRX _GTX_P3 PEG_CRX _GTX_N3

PEG_CRX _GTX_P2 PEG_CRX _GTX_N2

PEG_CRX _GTX_P1 PEG_CRX _GTX_N1

PEG_CRX _GTX_P0 PEG_CRX _GTX_N0

DMI_CRX_P TX_P0 DMI_CRX_P TX_N0

DMI_CRX_P TX_P1 DMI_CRX_P TX_N1

DMI_CRX_P TX_P2 DMI_CRX_P TX_N2

DMI_CRX_P TX_P3 DMI_CRX_P TX_N3

E25 D25

E24

F24

E23 D23

E22

F22

E21 D21

E20

F20

E19 D19

E18

F18

D17 E17

F16

E16

D15 E15

F14

E14

D13 E13

F12

E12

D11 E11

F10

E10

G2

D8 E8

E6 F6

D5 E5

J8 J9

CFL-H_BG A1440

UC1C

PEG_RXP_0 PEG_RXN_0

PEG_RXP_1 PEG_RXN_1

PEG_RXP_2 PEG_RXN_2

PEG_RXP_3 PEG_RXN_3

PEG_RXP_4 PEG_RXN_4

PEG_RXP_5 PEG_RXN_5

PEG_RXP_6 PEG_RXN_6

PEG_RXP_7 PEG_RXN_7

PEG_RXP_8 PEG_RXN_8

PEG_RXP_9 PEG_RXN_9

PEG_RXP_10 PEG_RXN_10

PEG_RXP_11 PEG_RXN_11

PEG_RXP_12 PEG_RXN_12

PEG_RXP_13 PEG_RXN_13

PEG_RXP_14 PEG_RXN_14

PEG_RXP_15 PEG_RXN_15

PEG_RCOMP

DMI_RXP_0 DMI_RXN_0

DMI_RXP_1 DMI_RXN_1

DMI_RXP_2 DMI_RXN_2

DMI_RXP_3 DMI_RXN_3

CFL-H

PEG_TXP_10 PEG_TXN_10

PEG_TXP_11 PEG_TXN_11

PEG_TXP_12 PEG_TXN_12

PEG_TXP_13 PEG_TXN_13

PEG_TXP_14 PEG_TXN_14

PEG_TXP_15 PEG_TXN_15

3 OF 13

PEG_TXP_0 PEG_TXN_0

PEG_TXP_1 PEG_TXN_1

PEG_TXP_2 PEG_TXN_2

PEG_TXP_3 PEG_TXN_3

PEG_TXP_4 PEG_TXN_4

PEG_TXP_5 PEG_TXN_5

PEG_TXP_6 PEG_TXN_6

PEG_TXP_7 PEG_TXN_7

PEG_TXP_8 PEG_TXN_8

PEG_TXP_9 PEG_TXN_9

DMI_TXP_0 DMI_TXN_0

DMI_TXP_1 DMI_TXN_1

DMI_TXP_2 DMI_TXN_2

DMI_TXP_3 DMI_TXN_3

B25 A25

B24 C24

B23 A23

B22 C22

B21 A21

B20 C20

B19 A19

B18 C18

A17 B17

C16 B16

A15 B15

C14 B14

A13 B13

C12 B12

A11 B11

C10 B10

B8 A8

C6 B6

B5 A5

D4 B4

PEG_CTX _GRX_P15 PEG_CTX _GRX_N15

PEG_CTX _GRX_P14 PEG_CTX _GRX_N14

PEG_CTX _GRX_P13 PEG_CTX _GRX_N13

PEG_CTX _GRX_P12 PEG_CTX _GRX_N12

PEG_CTX _GRX_P11 PEG_CTX _GRX_N11

PEG_CTX _GRX_P10 PEG_CTX _GRX_N10

PEG_CTX _GRX_P9 PEG_CTX _GRX_N9

PEG_CTX _GRX_P8 PEG_CTX _GRX_N8

PEG_CTX _GRX_P7 PEG_CTX _GRX_N7

PEG_CTX _GRX_P6 PEG_CTX _GRX_N6

PEG_CTX _GRX_P5 PEG_CTX _GRX_N5

PEG_CTX _GRX_P4 PEG_CTX _GRX_N4

PEG_CTX _GRX_P3 PEG_CTX _GRX_N3

PEG_CTX _GRX_P2 PEG_CTX _GRX_N2

PEG_CTX _GRX_P1 PEG_CTX _GRX_N1

PEG_CTX _GRX_P0 PEG_CTX _GRX_N0

DMI_CTX_P RX_P0 DMI_CTX_P RX_N0

DMI_CTX_P RX_P1 DMI_CTX_P RX_N1

DMI_CTX_P RX_P2 DMI_CTX_P RX_N2

DMI_CTX_P RX_P3 DMI_CTX_P RX_N3

1 2

CC34 0.22U_040 2_16V7K

1 2

CC35 0.22U_040 2_16V7K

1 2

CC36 0.22U_040 2_16V7K

1 2

CC37 0.22U_040 2_16V7K

1 2

CC38 0.22U_040 2_16V7K

1 2

CC39 0.22U_040 2_16V7K

1 2

CC40 0.22U_040 2_16V7K

1 2

CC41 0.22U_040 2_16V7K

1 2

CC42 0.22U_040 2_16V7K

1 2

CC43 0.22U_040 2_16V7K

1 2

CC44 0.22U_040 2_16V7K

1 2

CC45 0.22U_040 2_16V7K

1 2

CC46 0.22U_040 2_16V7K

1 2

CC47 0.22U_040 2_16V7K

1 2

CC48 0.22U_040 2_16V7K

1 2

CC49 0.22U_040 2_16V7K

1 2

CC50 0.22U_040 2_16V7K

1 2

CC51 0.22U_040 2_16V7K

1 2

CC52 0.22U_040 2_16V7K

1 2

CC53 0.22U_040 2_16V7K

1 2

CC54 0.22U_040 2_16V7K

1 2

CC55 0.22U_040 2_16V7K

1 2

CC56 0.22U_040 2_16V7K

1 2

CC57 0.22U_040 2_16V7K

1 2

CC58 0.22U_040 2_16V7K

1 2

CC59 0.22U_040 2_16V7K

1 2

CC60 0.22U_040 2_16V7K

1 2

CC61 0.22U_040 2_16V7K

1 2

CC62 0.22U_040 2_16V7K

1 2

CC63 0.22U_040 2_16V7K

1 2

CC64 0.22U_040 2_16V7K

1 2

CC65 0.22U_040 2_16V7K

DMI_CTX_P RX_P0 <15> DMI_CTX_P RX_N0 <15>

DMI_CTX_P RX_P1 <15> DMI_CTX_P RX_N1 <15>

DMI_CTX_P RX_P2 <15> DMI_CTX_P RX_N2 <15>

DMI_CTX_P RX_P3 <15> DMI_CTX_P RX_N3 <15>

PEG_CTX _C_GRX_P15 PEG_CTX _C_GRX_N15

PEG_CTX _C_GRX_P14 PEG_CTX _C_GRX_N14

PEG_CTX _C_GRX_P13 PEG_CTX _C_GRX_N13

PEG_CTX _C_GRX_P12 PEG_CTX _C_GRX_N12

PEG_CTX _C_GRX_P11 PEG_CTX _C_GRX_N11

PEG_CTX _C_GRX_P10 PEG_CTX _C_GRX_N10

PEG_CTX _C_GRX_P9 PEG_CTX _C_GRX_N9

PEG_CTX _C_GRX_P8 PEG_CTX _C_GRX_N8

PEG_CTX _C_GRX_P7 PEG_CTX _C_GRX_N7

PEG_CTX _C_GRX_P6 PEG_CTX _C_GRX_N6

PEG_CTX _C_GRX_P5 PEG_CTX _C_GRX_N5

PEG_CTX _C_GRX_P4 PEG_CTX _C_GRX_N4

PEG_CTX _C_GRX_P3 PEG_CTX _C_GRX_N3

PEG_CTX _C_GRX_P2 PEG_CTX _C_GRX_N2

PEG_CTX _C_GRX_P1 PEG_CTX _C_GRX_N1

PEG_CTX _C_GRX_P0 PEG_CTX _C_GRX_N0

A A

Security Class ification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2016/01/ 01

3

Compal Secret Data

Deciphered Date

2017/01/ 01

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

CFL-H(1/8) DMI,PEG

Size Doc ument Number Rev

A

LA-H271P

Tuesday, April 09, 2019

Date: Sheet of

1

6 103

1.0

5

+1.05V_PRIM

1 2

+3.3V_ALW_PCH

XDP@

1.5K_0402_5%

12

RC133

SYS_PWROK_R

0.1U_0402_25V6

@

1

D D

CC33

Place near JXDP1.47

2

RC216 0_0603_5%@

+1.0V_PRIM_XDP

0.1U_0402_25V6

@

1

CC28

2

+1.0V_PRIM_XDP

0.1U_0402_25V6

@

1

CC29

2

Place near JXDP1

+3.3V_ALW

1.5K_0402_5%

XDP@

12

RC241

SIO_PWRBTN#

XDP@

0.1U_0402_25V6

1

Place near JXDP1.41

CC269

2

C C

+1.0V_PRIM_XDP

CPU_XDP_PREQ#

1 2

RC138 51 _0402_5%@

+1.0VS_VCCIO

FIVR_EN_R

1 2

RC132 150_0402_ 5%

+1.0V_VCCSTG

1 2

VR_SVID_DATA

VR_SVID_ALERT#

100P_0402_50V8J

12

CC301ESD@

ESD Request:place near CPU side

PROCHOT#

H_THERMT RIP#

PCH_JTAGX

VCCST_PWR GD

H_CATERR#

FIVR_EN

+1.0V_VCCST

5

RC83 1K_0402_5%

+1.0V_VCCST

RC80 1K_0402_5%

RC166 1K_0402_5%@

RC71 1K_0402_5%

RC79 49.9_0402_1%@

+1.0V_VCCST

RC218 15 0_0402_5%@

B B

A A

RC219 10 K_0402_5%@

VR_SVID_DATA<90>

VR_SVID_ALERT#<90>

H_PWRGD VCCST_PW RGD

100P_0402_50V8J

12

CC300ESD@

56.2_0402_1%

12

220_0402_5%

12

H_THERMT RIP#

12

RC152

RC153

@ESD@

0.1U_0402_25V6

CC323

PCH_RSMRST #_AND<18,62>

SIO_PWRBTN#<18,58>

PCH_SPI_D0<17> SYS_PWROK<18,58 >

CPU_XDP_TMS

CPU_XDP_TDI

CPU_XDP_TDO

CPU_XDP_TCLK

CPU_XDP_PRDY#

CPU_XDP_PREQ#

100_0402_5%

12

RC157

VR_SVID_DATA

CPU_VIDALERT#

FIVR_EN CFG0

CPU_XDP_TDO H_VCCST_PWRGD_ XDP CPU_XDP_TRS T#

@ESD@

0.1U_0402_25V6

12

CC306

PCH_JTAG_TMS PCH_XDP_PR DY# P CH_XDP_PREQ#

@ESD@

0.1U_0402_25V6

12

CC336

ESD request,Place near JXDP1 side.

1 2

@

RC228

1 2

@

RC229

1 2

@

RC230

1 2

@

RC143

1 2

@

RC314

1 2

@

RC315

PCH_JTAGX

PCH_JTAG_TD I

PCH_JTAG_TD O

12

1 2

CC305 0.1U_0201_ 25V6K@ESD@

1 2

CC304 0.1U_0201_ 25V6K@ESD@

1 2

CC303 0.1U_0201_ 25V6K@ESD@

ESD request,Place near JXDP1 side

PROCHOT#

@ESD@

0.1U_0402_25V6

CC324

12

0.1U_0402_25V6

12

PCH_JTAG_TMS

0_0402_5%

PCH_XDP_PRDY#

0_0402_5%

PCH_XDP_PREQ#

0_0402_5%

VR_SVID_CLK

@ESD@

0.1U_0402_25V6

CC307

@ESD@

CC337

4

CPU_XDP_PREQ# CPU_XDP_PRDY#

XDP_OBS0_R XDP_OBS1_R

12

0.1U_0402_25V6

@ESD@

0.1U_0402_25V6

CC308

@ESD@

CC338

Add ESD part

VR_SVID_CLK<90>

PROCHOT#<27,58,82,85,90>

DDR_VTT_CTRL<2 3>

VCCST_PWRGD<5 9>

H_PWRGD<18> PLTRST_CPU#<14> H_PM_SYNC<14> H_PM_DOWN<14> H_PECI<14,58> H_THERMTRIP#<14,23,24,25,26,59>

H_VCCST_PWRGD_XDP

SIO_PWRBTN#

1 2

RC124 1K_0402_5%XDP@

1 2

RC217 0_0402_5%@

1 2

RC126 1K_0402_5%XDP@

1 2

RC128 1K_0402_5%XDP@

1 2

RC129 0_0402_5%@

DDR_XDP_WAN_SMBDAT<18,23,24,25,26,54> DDR_XDP_WAN_SMBCLK<18,23,24,25,26,54> PCH_JTAG_TCK<1 8>

12

PCH_JTAG_TMS <18>

PCH_JTAG_TDI <18>

PCH_JTAG_TDO < 18>

PCH_JTAGX <18>

PCH_XDP_PRDY# <20>

PCH_XDP_PREQ# <20>

pop RC171 for CNL depop RC171 for SKL & KBL (CFL CRB rev0.7)

RF Request

1 2

CC325@RF@ 33P_ 0402_50V8J

Place close CPU side

4

CPU XDP

+1.0V_PRIM_XDP

XDP_PRSNT_PIN1

CFG0 CFG1

CFG2 CFG3

CFG4 CFG5

CFG6 CFG7

FIVR_EN_R SYS_PWROK_R

CPU_XDP_TCLK

PCH_CPU_BCLK_R_D<16> PCH_CPU_BCLK_R_D#<16>

PCH_CPU_PCIBCLK_R_D<16> PCH_CPU_PCIBCLK_R_D#<16>

CPU_24MHZ_R_D<16> CPU_24MHZ_R_D#<16>

VR_SVID_CLK

PROCHOT#

RC84 499_0402_1%

DDR_VTT_C TRL

VCCST_PWR GD VCCST_PWR GD_CPU

RC78 60.4_0402_1%

H_PWRGD PLTRST_C PU# H_PM_SYNC

H_PECI

RC168 20_0402_5 %

H_THERMT RIP# H_TH ERMTRIP#_R

RC169 0_0402_5%@ RC319 0_0402_5%@

RC171 0_0402_5%@

XDP@

1 2

RC121 1K _0402_5%

1 2

RC122 0_0 402_5%@

CONN@

JXDP1

112 334 556 778 9910 111112

13

14

13

15

16

15

17

18

17

19

20

19

21

22

21

23

24

23

25

26

25

27

28

27

29

30

29

31

32

31

33

34

33

35

36

35

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

595960

61

GND62GND

JXT_FP270H-06 1G1AM

PCH_CPU_BC LK_R_D PCH_CPU_BC LK_R_D#

PCH_CPU_PC IBCLK_R_D PCH_CPU_PC IBCLK_R_D#

CPU_24MHZ_ R_D CPU_24MHZ_ R_D#

CPU_VIDALERT#

VR_SVID_DATA

1 2

1 2 1 2

H_PROCHOT# _R

T26PAD~D @ T25PAD~D @

T31PAD~D @ T32PAD~D @

CFG3

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60

63

CPU_XDP_HOOK6

XDP_DBRESET#

CPU_XDP_TDO

CPU_XDP_TRST#

CPU_XDP_TCLK

1 1

3

CFG11

12

@

RC441 1K_0402_5%

+1.0V_PRIM_XDP

CFG17 CFG16

CFG8 CFG9

CFG10 CFG11

CFG19 CFG18

CFG12 CFG13

CFG14 CFG15

PCH_XDP_CLK_ DP PCH_XDP_CLK_ DN

CPU_XDP_HOOK6 XDP_DBRESET#

CPU_XDP_TDO CPU_XDP_TRST# CPU_XDP_TDI CPU_XDP_TMS CPU_XDP_PRS

1 2

B31 A32

D35 C36

E31 D31

BH31 BH32 BH29 BR30

BT13

H13

BT31 BP35

BM34

BP31 BT34

J31

BR33

BN1

BM30

AT13

AW13

AU13 AY13

+1.0V_PRIM_XDP

+3.3V_ALW_PCH

+1.0V_VCCSTG

UC1E

BCLKP BCLKN

PCI_BCLKP PCI_BCLKN

CLK24P CLK24N

VIDALERT# VIDSCK VIDSOUT PROCHOT#

DDR_VTT_CNTL

VCCST_PWRGD

PROCPWRGD RESET# PM_SYNC PM_DOWN PECI THERMTRIP#

SKTOCC# PROC_SELECT#

CATERR#

ZVM# MSM#

RSVD1 RSVD2

CFL-H_BGA1440

CFL-H

5 OF 13

1 2

RC115 2.2K_ 0402_5%XDP@

1 2

RC137 3K_0 402_5%

RC135 51 _0402_5%

RC136 51 _0402_5%@

RC139 51 _0402_5%

H_PM_DOW N_RH_PM_DOW N

H_SKTOCC# SKL_CNL#

H_CATERR#

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

CFG12

PCH_XDP_CLK_DP <16> PCH_XDP_CLK_DN <16>

1 2

RC144 0_0402_5%

@XDP@

XDP_DBRESET# <15>

CPU_XDP_TRST# <20>

1 2

RC127 0_0402_5%

XDP@

Change to 0 ohm 3/29

CFG13

BN25

CFG_0

BN27

CFG_1

BN26

CFG_2

BN28

CFG_3

BR20

CFG_4

BM20

CFG_5

BT20

CFG_6

BP20

CFG_7

BR23

CFG_8

BR22

CFG_9

BT23

CFG_10

BT22

CFG_11

BM19

CFG_12

BR19

CFG_13

BP19

CFG_14

BT19

CFG_15

BN23

CFG_17

BP23

CFG_16

BP22

CFG_19

BN22

CFG_18

BR27

BPM#_0

BT27

BPM#_1

BM31

BPM#_2

BT30

BPM#_3

BT28

PROC_TDO

BL32

PROC_TDI

BP28

PROC_TMS

BR28

PROC_TCK

CFG_RCOMP

2016/01/01

BP30 BL30 BP27

BT25

PROC_TRST# PROC_PREQ# PROC_PRDY#

12

@

RC442 1K_0402_5%

ITP_PMODE_CPU

PCH_SPI_D2_XDP

12

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15

CFG17 CFG16 CFG19 CFG18

XDP_OBS0 XDP_OBS1

CPU_XDP_TDO CPU_XDP_TDI CPU_XDP_TMS CPU_XDP_TCL K

CPU_XDP_TRST# CPU_XDP_PREQ# CPU_XDP_PRDY#

Compal Secret Data

*

@

RC443

*

1K_0402_5%

12

RC114

49.9_0402_1 %

Deciphered Date

2

RC239 0_0402_5%@ RC240 0_0402_5%@

1 1 1 1

1 1 1

2

DMI_AC_coupled

HALF-SWING DC coupled

FULL-SWING AC coupling

PMSYNC2.0

LEGACY

ITP_PMODE_CPU <18>

PCH_SPI_D2_XDP <17>

SYNC & AYNC MODE

ASYNCHRONOUS

SYNCHRONOUS

XDP_DBRESET#

1 2 1 2

@

T184

PAD~D

@

T185

PAD~D

@

T180

PAD~D

@

T181

PAD~D

@

T179

PAD~D

@

T190

PAD~D

@

T189

PAD~D

2017/01/01

1

0

1

0

1

0

0.1U_0402_25V6

1

2

XDP_OBS0_R XDP_OBS1_R

1

CFG10

12

@

RC440 1K_0402_5%

SAFE mode boot

enable

*

disable

CFG9

1K_0402_5%

12

RC438

@

1K_0402_5%

SVID NOT Present

*

Present

+1.0VS_VCCIO

RC439

@

1 2

Not presnet10

CFG8

12

@

RC437 1K_0402_5%

*

CFG UNLOCK

disable

enable10

CFG1

12

PCHLESS MODE (CRB) Reserved CFG lane (EDS)

@

RC436

*

1K_0402_5%

NORMAL

PCHLESS

CFG0

12

Stall reset sequence after PCU PLL lock until de-asserted

@

RC321

*

1K_0402_5%

No Stall

Stall

CFG2

CFG4

CFG5

CFG6

CFG7

12

XDP@

CC32

RC181 1K_0402_5%

RC322 1K_0402_5%

@

RC323 1K_0402_5%

@

RC324 1K_0402_5%

@

RC325 1K_0402_5%

*

PEG LANE REVERSAL

NORMAL

LANE REVERSED

eDP enable

Disabled

Enabled

PCI Express* Bifurcation

1x8, 2x4

Reserved

2x8

1x16

PEG Training

(default) PEG Train immediately following RESET# de-assertion

PEG Wait for BIOS for training

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

CFL-H(2/8) XDP

Size Document Number Rev

B

LA-H271P

Tuesday, April 09, 2019

Date: Sheet of

1

0

1

0

1

0

1

0

[6:5]

00

01

10

11

7 103

1

0

1

0

1.0

5

4

3

2

1

D D

UC1A

DDR_A_D[0..63]<23,24>

C C

B B

DDR_A_CB[0..7]< 23,24>

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

DDR_A_CB0 DDR_A_CB1 DDR_A_CB2 DDR_A_CB3 DDR_A_CB4 DDR_A_CB5 DDR_A_CB6 DDR_A_CB7

DDR4(IL)/LP3-DDR4(NIL) LP3/DDR4

BR6

DDR0_DQ_0/DDR0_DQ_0

BT6

DDR0_DQ_1/DDR0_DQ_1

BP3

DDR0_DQ_2/DDR0_DQ_2

BR3

DDR0_DQ_3/DDR0_DQ_3

BN5

DDR0_DQ_4/DDR0_DQ_4

BP6

DDR0_DQ_5/DDR0_DQ_5

BP2

DDR0_DQ_6/DDR0_DQ_6

BN3

DDR0_DQ_7/DDR0_DQ_7

BL4

DDR0_DQ_8/DDR0_DQ_8

BL5

DDR0_DQ_9/DDR0_DQ_9

BL2

DDR0_DQ_10/DDR0_DQ_10

BM1

DDR0_DQ_11/DDR0_DQ_11

BK4

DDR0_DQ_12/DDR0_DQ_12

BK5

DDR0_DQ_13/DDR0_DQ_13

BK1

DDR0_DQ_14/DDR0_DQ_14

BK2

DDR0_DQ_15/DDR0_DQ_15

BG4

DDR0_DQ_16/DDR0_DQ_32

BG5

DDR0_DQ_17/DDR0_DQ_33

BF4

DDR0_DQ_18/DDR0_DQ_34

BF5

DDR0_DQ_19/DDR0_DQ_35

BG2

DDR0_DQ_20/DDR0_DQ_36

BG1

DDR0_DQ_21/DDR0_DQ_37

BF1

DDR0_DQ_22/DDR0_DQ_38

BF2

DDR0_DQ_23/DDR0_DQ_39

BD2

DDR0_DQ_24/DDR0_DQ_40

BD1

DDR0_DQ_25/DDR0_DQ_41

BC4

DDR0_DQ_26/DDR0_DQ_42

BC5

DDR0_DQ_27/DDR0_DQ_43

BD5

DDR0_DQ_28/DDR0_DQ_44

BD4

DDR0_DQ_29/DDR0_DQ_45

BC1

DDR0_DQ_30/DDR0_DQ_46

BC2

DDR0_DQ_31/DDR0_DQ_47

AB1

DDR0_DQ_32/DDR1_DQ_0

AB2

DDR0_DQ_33/DDR1_DQ_1

AA4

DDR0_DQ_34/DDR1_DQ_2

AA5

DDR0_DQ_35/DDR1_DQ_3

AB5

DDR0_DQ_36/DDR1_DQ_4

AB4

DDR0_DQ_37/DDR1_DQ_5

AA2

DDR0_DQ_38/DDR1_DQ_6

AA1

DDR0_DQ_39/DDR1_DQ_7

V5

DDR0_DQ_40/DDR1_DQ_8

V2

DDR0_DQ_41/DDR1_DQ_9

U1

DDR0_DQ_42/DDR1_DQ_10

U2

DDR0_DQ_43/DDR1_DQ_11

V1

DDR0_DQ_44/DDR1_DQ_12

V4

DDR0_DQ_45/DDR1_DQ_13

U5

DDR0_DQ_46/DDR1_DQ_14

U4

DDR0_DQ_47/DDR1_DQ_15

R2

DDR0_DQ_48/DDR1_DQ_32

P5

DDR0_DQ_49/DDR1_DQ_33

R4

DDR0_DQ_50/DDR1_DQ_34

P4

DDR0_DQ_51/DDR1_DQ_35

R5

DDR0_DQ_52/DDR1_DQ_36

P2

DDR0_DQ_53/DDR1_DQ_37

R1

DDR0_DQ_54/DDR1_DQ_38

P1

DDR0_DQ_55/DDR1_DQ_39

M4

DDR0_DQ_56/DDR1_DQ_40

M1

DDR0_DQ_57/DDR1_DQ_41

L4

DDR0_DQ_58/DDR1_DQ_42

L2

DDR0_DQ_59/DDR1_DQ_43

M5

DDR0_DQ_60/DDR1_DQ_44

M2

DDR0_DQ_61/DDR1_DQ_45

L5

DDR0_DQ_62/DDR1_DQ_46

L1

DDR0_DQ_63/DDR1_DQ_47

LP3/DDR4

BA2

NC/DDR0_ECC_0

BA1

NC/DDR0_ECC_1

AY4

NC/DDR0_ECC_2

AY5

NC/DDR0_ECC_3

BA5

NC/DDR0_ECC_4

BA4

NC/DDR0_ECC_5

AY1

NC/DDR0_ECC_6

AY2

NC/DDR0_ECC_7

CFL-H_BGA1440

CFL-H

DDR CHANNEL A

DDR0_CKP_0/DDR0_CKP_0 DDR0_CKN_0/DDR0_CKN_0 DDR0_CKP_1/DDR0_CKP_1 DDR0_CKN_1/DDR0_CKN_1

NC/DDR0_CKP_2 NC/DDR0_CKN_2 NC/DDR0_CKP_3 NC/DDR0_CKN_3

DDR0_CKE_0/DDR0_CKE_0 DDR0_CKE_1/DDR0_CKE_1 DDR0_CKE_2/DDR0_CKE_2 DDR0_CKE_3/DDR0_CKE_3

DDR0_CS#_0/DDR0_CS#_0 DDR0_CS#_1/DDR0_CS#_1

NC/DDR0_CS#_2 NC/DDR0_CS#_3

DDR0_ODT_0/DDR0_ODT_0

NC/DDR0_ODT_1 NC/DDR0_ODT_2 NC/DDR0_ODT_3

DDR0_CAB_4/DDR0_BA_0 DDR0_CAB_6/DDR0_BA_1 DDR0_CAA_5/DDR0_BG_0

DDR0_CAB_3/DDR0_MA_16 DDR0_CAB_2/DDR0_MA_14 DDR0_CAB_1/DDR0_MA_15

DDR0_CAB_9/DDR0_MA_0 DDR0_CAB_8/DDR0_MA_1 DDR0_CAB_5/DDR0_MA_2

NC/DDR0_MA_3

NC/DDR0_MA_4 DDR0_CAA_0/DDR0_MA_5 DDR0_CAA_2/DDR0_MA_6 DDR0_CAA_4/DDR0_MA_7 DDR0_CAA_3/DDR0_MA_8 DDR0_CAA_1/DDR0_MA_9

DDR0_CAB_7/DDR0_MA_10 DDR0_CAA_7/DDR0_MA_11 DDR0_CAA_6/DDR0_MA_12 DDR0_CAB_0/DDR0_MA_13

DDR0_CAA_9/DDR0_BG_1 DDR0_CAA_8/DDR0_ACT#

NC/DDR0_ALERT#

DDR4(IL)/LP3-DDR4(NIL)

DDR0_DQSN_0/DDR0_DQSN_0 DDR0_DQSN_1/DDR0_DQSN_1 DDR0_DQSN_2/DDR0_DQSN_4 DDR0_DQSN_3/DDR0_DQSN_5 DDR0_DQSN_4/DDR1_DQSN_0 DDR0_DQSN_5/DDR1_DQSN_1 DDR0_DQSN_6/DDR1_DQSN_4 DDR0_DQSN_7/DDR1_DQSN_5

DDR0_DQSP_0/DDR0_DQSP_0 DDR0_DQSP_1/DDR0_DQSP_1 DDR0_DQSP_2/DDR0_DQSP_4 DDR0_DQSP_3/DDR0_DQSP_5 DDR0_DQSP_4/DDR1_DQSP_0 DDR0_DQSP_5/DDR1_DQSP_1 DDR0_DQSP_6/DDR1_DQSP_4 DDR0_DQSP_7/DDR1_DQSP_5

DDR0_DQSP_8/DDR0_DQSP_8 DDR0_DQSN_8/DDR0_DQSN_8

1 OF 13

NC/DDR0_PAR

AG1 AG2 AK2 AK1 AL3 AK3 AL2 AL1

AT1 AT2 AT3 AT5

AD5 AE2 AD2 AE5

AD3 AE4 AE1 AD4

AH5 AH1 AU1

AH4 AG4 AD1

AH3 AP4 AN4 AP5 AP2 AP1 AP3 AN1 AN3 AT4 AH2 AN2 AU4 AE3 AU2 AU3

AG3 AU5

BR5 BL3 BG3 BD3 AA3 U3 P3 L3

BP5 BK3 BF3 BC3 AB3 V3 R3 M3

AY3 BA3

DDR_A_CLK0 DDR_A_CLK#0 DDR_A_CLK1 DDR_A_CLK#1 DDR_A_CLK2 DDR_A_CLK#2 DDR_A_CLK3 DDR_A_CLK#3

DDR_A_CKE0 DDR_A_CKE1 DDR_A_CKE2 DDR_A_CKE3

DDR_A_CS#0 DDR_A_CS#1 DDR_A_CS#2 DDR_A_CS#3

DDR_A_ODT0 DDR_A_ODT1 DDR_A_ODT2 DDR_A_ODT3

DDR_A_BA0 DDR_A_BA1 DDR_A_BG0

DDR_A_MA16 DDR_A_MA14 DDR_A_MA15

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_BG1 DDR_A_ACT#

DDR_A_PARITY DDR_A_ALERT#

DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7

DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7

DDR_A_DQS8 DDR_A_DQS#8

DDR_A_CLK0 <24> DDR_A_CLK#0 <24 > DDR_A_CLK1 <24> DDR_A_CLK#1 <24 > DDR_A_CLK2 <23> DDR_A_CLK#2 <23 > DDR_A_CLK3 <23> DDR_A_CLK#3 <23 >

DDR_A_CKE0 <24 > DDR_A_CKE1 <24 > DDR_A_CKE2 <23 > DDR_A_CKE3 <23 >

DDR_A_CS#0 <24> DDR_A_CS#1 <24> DDR_A_CS#2 <23> DDR_A_CS#3 <23>

DDR_A_ODT0 <24> DDR_A_ODT1 <24> DDR_A_ODT2 <23> DDR_A_ODT3 <23>

DDR_A_BA0 <23,24> DDR_A_BA1 <23,24> DDR_A_BG0 <23,24>

DDR_A_MA16 <23,24> DDR_A_MA14 <23,24> DDR_A_MA15 <23,24> DDR_A_MA[0..13] <23 ,24>

DDR_A_BG1 <23,24> DDR_A_ACT# <23,24>

DDR_A_PARITY <23,24 > DDR_A_ALERT# <23 ,24>

DDR_A_DQS#[0..3] <23,24 >

DDR_A_DQS#[4..7] <23,24 >

DDR_A_DQS[0..3] <23,24>

DDR_A_DQS[4..7] <23,24>

DDR_A_DQS8 <23 ,24> DDR_A_DQS#8 <2 3,24>

DDR_B_D[0..63 ]<25,26>

DDR_B_CB[0..7 ]<25,26>

RC5 121_0402_1% RC6 75_0402_1% RC7 100_0402_1%

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39

DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

1 2 1 2 1 2

Trace width=12-15 mils ,Spacing=20mil Max length= 500 mils.

DDR_B_CB0 DDR_B_CB1 DDR_B_CB2 DDR_B_CB3 DDR_B_CB4 DDR_B_CB5 DDR_B_CB6 DDR_B_CB7

DDR_RCOMP0 DDR_RCOMP1 DDR_RCOMP2

UC1B

DDR4(IL)/LP3-DDR4(NIL)

BT11

DDR1_DQ_0/DDR0_DQ_16

BR11

DDR1_DQ_1/DDR0_DQ_17

BT9

DDR1_DQ_2/DDR0_DQ_18

BR8

DDR1_DQ_3/DDR0_DQ_19

BP11

DDR1_DQ_4/DDR0_DQ_20

BN11

DDR1_DQ_5/DDR0_DQ_21

BP8

DDR1_DQ_6/DDR0_DQ_22

BN8

DDR1_DQ_7/DDR0_DQ_23

BL12

DDR1_DQ_8/DDR0_DQ_24

BL11

DDR1_DQ_9/DDR0_DQ_25

BL8

DDR1_DQ_10/DDR0_DQ_26

BJ8

DDR1_DQ_11/DDR0_DQ_27

BJ11

DDR1_DQ_12/DDR0_DQ_28

BJ10

DDR1_DQ_13/DDR0_DQ_29

BL7

DDR1_DQ_14/DDR0_DQ_30

BJ7

DDR1_DQ_15/DDR0_DQ_31

BG11

DDR1_DQ_16/DDR0_DQ_48

BG10

DDR1_DQ_17/DDR0_DQ_49

BG8

DDR1_DQ_18/DDR0_DQ_50

BF8

DDR1_DQ_19/DDR0_DQ_51

BF11

DDR1_DQ_20/DDR0_DQ_52

BF10

DDR1_DQ_21/DDR0_DQ_53

BG7

DDR1_DQ_22/DDR0_DQ_54

BF7

DDR1_DQ_23/DDR0_DQ_55

BB11

DDR1_DQ_24/DDR0_DQ_56

BC11

DDR1_DQ_25/DDR0_DQ_57

BB8

DDR1_DQ_26/DDR0_DQ_58

BC8

DDR1_DQ_27/DDR0_DQ_59

BC10

DDR1_DQ_28/DDR0_DQ_60

BB10

DDR1_DQ_29/DDR0_DQ_61

BC7

DDR1_DQ_30/DDR0_DQ_62

BB7

DDR1_DQ_31/DDR0_DQ_63

AA11

DDR1_DQ_32/DDR1_DQ_16

AA10

DDR1_DQ_33/DDR1_DQ_17

AC11

DDR1_DQ_34/DDR1_DQ_18

AC10

DDR1_DQ_35/DDR1_DQ_19

AA7

DDR1_DQ_36/DDR1_DQ_20

AA8

DDR1_DQ_37/DDR1_DQ_21

AC8

DDR1_DQ_38/DDR1_DQ_22

AC7

DDR1_DQ_39/DDR1_DQ_23

DDR4(IL)/LP3-DDR4(NIL)

W8

DDR1_DQ_40/DDR1_DQ_24

W7

DDR1_DQ_41/DDR1_DQ_25

V10

DDR1_DQ_42/DDR1_DQ_26

V11

DDR1_DQ_43/DDR1_DQ_27

W11

DDR1_DQ_44/DDR1_DQ_28

W10

DDR1_DQ_45/DDR1_DQ_29

V7

DDR1_DQ_46/DDR1_DQ_30

V8

DDR1_DQ_47/DDR1_DQ_31

R11

DDR1_DQ_48/DDR1_DQ_48

P11

DDR1_DQ_49/DDR1_DQ_49

P7

DDR1_DQ_50/DDR1_DQ_50

R8

DDR1_DQ_51/DDR1_DQ_51

R10

DDR1_DQ_52/DDR1_DQ_52

P10

DDR1_DQ_53/DDR1_DQ_53

R7

DDR1_DQ_54/DDR1_DQ_54

P8

DDR1_DQ_55/DDR1_DQ_55

L11

DDR1_DQ_56/DDR1_DQ_56

M11

DDR1_DQ_57/DDR1_DQ_57

L7

DDR1_DQ_58/DDR1_DQ_58

M8

DDR1_DQ_59/DDR1_DQ_59

L10

DDR1_DQ_60/DDR1_DQ_60

M10

DDR1_DQ_61/DDR1_DQ_61

M7

DDR1_DQ_62/DDR1_DQ_62

L8

DDR1_DQ_63/DDR1_DQ_63

LP3/DDR4

AW11

NC/DDR1_ECC_0

AY11

NC/DDR1_ECC_1

AY8

NC/DDR1_ECC_2

AW8

NC/DDR1_ECC_3

AY10

NC/DDR1_ECC_4

AW10

NC/DDR1_ECC_5

AY7

NC/DDR1_ECC_6

AW7

NC/DDR1_ECC_7

G1

DDR_RCOMP_0

H1

DDR_RCOMP_1

J2

DDR_RCOMP_2

CFL-H_BGA1440

CFL-H

DDR CHANNEL B

DDR1_CKP_0/DDR1_CKP_0 DDR1_CKN_0/DDR1_CKN_0 DDR1_CKP_1/DDR1_CKP_1 DDR1_CKN_1/DDR1_CKN_1

DDR1_CKE_0/DDR1_CKE_0 DDR1_CKE_1/DDR1_CKE_1 DDR1_CKE_2/DDR1_CKE_2 DDR1_CKE_3/DDR1_CKE_3

DDR1_ODT_0/DDR1_ODT_0

DDR1_CAB_3/DDR1_MA_16 DDR1_CAB_2/DDR1_MA_14 DDR1_CAB_1/DDR1_MA_15

DDR1_CAB_7/DDR1_MA_10 DDR1_CAA_7/DDR1_MA_11 DDR1_CAA_6/DDR1_MA_12 DDR1_CAB_0/DDR1_MA_13

DDR1_DQSN_0/DDR0_DQSN_2 DDR1_DQSN_1/DDR0_DQSN_3 DDR1_DQSN_2/DDR0_DQSN_6 DDR1_DQSN_3/DDR0_DQSN_7 DDR1_DQSN_4/DDR1_DQSN_2 DDR1_DQSN_5/DDR1_DQSN_3 DDR1_DQSN_6/DDR1_DQSN_6 DDR1_DQSN_7/DDR1_DQSN_7

DDR1_DQSP_0/DDR0_DQSP_2 DDR1_DQSP_1/DDR0_DQSP_3 DDR1_DQSP_2/DDR0_DQSP_6 DDR1_DQSP_3/DDR0_DQSP_7 DDR1_DQSP_4/DDR1_DQSP_2 DDR1_DQSP_5/DDR1_DQSP_3 DDR1_DQSP_6/DDR1_DQSP_6 DDR1_DQSP_7/DDR1_DQSP_7

DDR1_DQSP_8/DDR1_DQSP_8 DDR1_DQSN_8/DDR1_DQSN_8

2 OF 13

LP3/DDR4

NC/DDR1_CKP_2 NC/DDR1_CKN_2 NC/DDR1_CKP_3 NC/DDR1_CKN_3

DDR1_CS#_0/DDR1_CS#_0 DDR1_CS#_1/DDR1_CS#_1

NC/DDR1_CS#_2 NC/DDR1_CS#_3

NC/DDR1_ODT_1 NC/DDR1_ODT_2 NC/DDR1_ODT_3

DDR1_CAB_4/DDR1_BA_0 DDR1_CAB_6/DDR1_BA_1 DDR1_CAA_5/DDR1_BG_0

DDR1_CAB_9/DDR1_MA_0 DDR1_CAB_8/DDR1_MA_1 DDR1_CAB_5/DDR1_MA_2

NC/DDR1_MA_3

NC/DDR1_MA_4 DDR1_CAA_0/DDR1_MA_5 DDR1_CAA_2/DDR1_MA_6 DDR1_CAA_4/DDR1_MA_7

DDR1_CAA_3/DDR1_MA_8 DDR1_CAA_1/DDR1_MA_9

DDR1_CAA_9/DDR1_BG_1 DDR1_CAA_8/DDR1_ACT#

NC/DDR1_PAR

NC/DDR1_ALERT#

DDR4(IL)/LP3-DDR4(NIL)

DDR_VREF_CA DDR0_VREF_DQ DDR1_VREF_DQ

AM9 AN9 AM7 AM8 AM11 AM10 AJ10 AJ11

AT8 AT10 AT7 AT11

AF11 AE7 AF10 AE10

AF7 AE8 AE9 AE11

AH10 AH11 AF8

AH8 AH9 AR9

AJ9 AK6 AK5 AL5 AL6 AM6 AN7 AN10

AN8 AR11 AH7 AN11 AR10 AF9 AR7 AT9

AJ7 AR8

BN9 BL9 BG9 BC9 AC9 W9 R9 M9

BP9 BJ9 BF9 BB9 AA9 V9 P9 L9

AW9 AY9

BN13 BP13 BR13

DDR_B_CLK 0 DDR_B_CLK #0 DDR_B_CLK 1 DDR_B_CLK #1 DDR_B_CLK 2 DDR_B_CLK #2 DDR_B_CLK 3 DDR_B_CLK #3

DDR_B_CKE0 DDR_B_CKE1 DDR_B_CKE2 DDR_B_CKE3

DDR_B_CS# 0 DDR_B_CS# 1 DDR_B_CS# 2 DDR_B_CS# 3

DDR_B_ODT 0 DDR_B_ODT 1 DDR_B_ODT 2 DDR_B_ODT 3

DDR_B_MA16 DDR_B_MA14 DDR_B_MA15

DDR_B_BA0 DDR_B_BA1 DDR_B_BG0

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7

DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_BG1 DDR_B_ACT#

DDR_B_PARITY DDR_B_ALERT #

DDR_B_DQS# 0 DDR_B_DQS# 1 DDR_B_DQS# 2 DDR_B_DQS# 3 DDR_B_DQS# 4 DDR_B_DQS# 5 DDR_B_DQS# 6 DDR_B_DQS# 7

DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7

DDR_B_DQS8 DDR_B_DQS# 8

+DDR_VREF_C A

1

PAD~D

+DDR_VREF_B_ DQ

DDR_B_CLK 0 <2 6> DDR_B_CLK #0 < 26> DDR_B_CLK 1 <2 6> DDR_B_CLK #1 < 26> DDR_B_CLK 2 <2 5> DDR_B_CLK #2 < 25> DDR_B_CLK 3 <2 5> DDR_B_CLK #3 < 25>

DDR_B_CKE0 <26 > DDR_B_CKE1 <26 > DDR_B_CKE2 <25 > DDR_B_CKE3 <25 >

DDR_B_CS# 0 <2 6> DDR_B_CS# 1 <2 6> DDR_B_CS# 2 <2 5> DDR_B_CS# 3 <2 5>

DDR_B_ODT 0 <26> DDR_B_ODT 1 <26> DDR_B_ODT 2 <25> DDR_B_ODT 3 <25>

DDR_B_MA16 <25,26> DDR_B_MA14 <25,26> DDR_B_MA15 <25,26>

DDR_B_BA0 <25,26> DDR_B_BA1 <25,26> DDR_B_BG0 <25,26>

DDR_B_MA[0..13] <25 ,26>

DDR_B_BG1 <25,26> DDR_B_ACT# <25,26>

DDR_B_PARITY <25,26 > DDR_B_ALERT # <25,2 6>

DDR_B_DQS# [0..7] <25,26>

DDR_B_DQS[0..7 ] < 25,26>

DDR_B_DQS8 <2 5,26> DDR_B_DQS# 8 < 25,26>

@

T199

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2016/01/01

Compal Secret Data

Deciphered Date

2017/01/01

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

CFL-H(3/8) DDR4

Size Document Number Rev

B

LA-H271P

Tuesday, April 09, 2019

Date: Sheet of

1

8 103

1.0

5

D D

4

3

2

1

UC1D

CPU_DP1 _P0<31> CPU_DP1 _N0<3 1> CPU_DP1 _P1<31> CPU_DP1 _N1<3 1>

MUX PS8461

C C

DEMUX PS8338

UMA DGFF

B B

CPU_DP1 _P2<31> CPU_DP1 _N2<3 1> CPU_DP1 _P3<31> CPU_DP1 _N3<3 1>

CPU_DP1 _AUXP<31 > CPU_DP1 _AUXN<31>

CPU_DP2 _P0<30> CPU_DP2 _N0<3 0> CPU_DP2 _P1<30> CPU_DP2 _N1<3 0> CPU_DP2 _P2<30> CPU_DP2 _N2<3 0> CPU_DP2 _P3<30> CPU_DP2 _N3<3 0>

CPU_DP2 _AUXP<30 > CPU_DP2 _AUXN<30>

CPU_DP3 _P0<28> CPU_DP3 _N0<2 8> CPU_DP3 _P1<28> CPU_DP3 _N1<2 8> CPU_DP3 _P2<28> CPU_DP3 _N2<2 8> CPU_DP3 _P3<28> CPU_DP3 _N3<2 8>

CPU_DP3 _AUXP<28 > CPU_DP3 _AUXN<28>

CPU_DP1 _P0 CPU_DP1 _N0 CPU_DP1 _P1 CPU_DP1 _N1 CPU_DP1 _P2 CPU_DP1 _N2 CPU_DP1 _P3 CPU_DP1 _N3

CPU_DP1 _AUXP CPU_DP1 _AUXN

CPU_DP2 _P0 CPU_DP2 _N0 CPU_DP2 _P1 CPU_DP2 _N1 CPU_DP2 _P2 CPU_DP2 _N2 CPU_DP2 _P3 CPU_DP2 _N3

CPU_DP2 _AUXP CPU_DP2 _AUXN

CPU_DP3 _P0 CPU_DP3 _N0 CPU_DP3 _P1 CPU_DP3 _N1 CPU_DP3 _P2 CPU_DP3 _N2 CPU_DP3 _P3 CPU_DP3 _N3

CPU_DP3 _AUXP CPU_DP3 _AUXN

K36

DDI1_TXP_0

K37

DDI1_TXN_0

J35

DDI1_TXP_1

J34

DDI1_TXN_1

H37

DDI1_TXP_2

H36

DDI1_TXN_2

J37

DDI1_TXP_3

J38

DDI1_TXN_3

D27

DDI1_AUXP

E27

DDI1_AUXN

H34

DDI2_TXP_0

H33

DDI2_TXN_0

F37

DDI2_TXP_1

G38

DDI2_TXN_1

F34

DDI2_TXP_2

F35

DDI2_TXN_2

E37

DDI2_TXP_3

E36

DDI2_TXN_3

F26

DDI2_AUXP

E26

DDI2_AUXN

C34

DDI3_TXP_0

D34

DDI3_TXN_0

B36

DDI3_TXP_1

B34

DDI3_TXN_1

F33

DDI3_TXP_2

E33

DDI3_TXN_2

C33

DDI3_TXP_3

B33

DDI3_TXN_3

A27

DDI3_AUXP

B27

DDI3_AUXN

CFL-H_BG A1440

CFL-H

EDP_TXP_0 EDP_TXN_0 EDP_TXP_1 EDP_TXN_1 EDP_TXP_2 EDP_TXN_2 EDP_TXP_3 EDP_TXN_3

EDP_AUXP EDP_AUXN

EDP_DISP_UTIL

DISP_RCOMP

PROC_AUDIO_CLK

PROC_AUDIO_SDI

PROC_AUDIO_SDO

4 of 13

D29 E29 F28 E28 A29 B29 C28 B28

C26 B26

A33

D37

G27 G25 G29

EDP_TXP 0 EDP_TXN 0 EDP_TXP 1 EDP_TXN 1 EDP_TXP 2 EDP_TXN 2 EDP_TXP 3 EDP_TXN 3

EDP_AUX P EDP_AUX N

1

PAD~D

EDP_COM P

AUD_AZA CPU_SCLK AUD_AZA CPU_SDO AUD_AZA CPU_SDI

EDP_TXP 0 <29> EDP_TXN 0 <29> EDP_TXP 1 <29> EDP_TXN 1 <29> EDP_TXP 2 <29> EDP_TXN 2 <29> EDP_TXP 3 <29> EDP_TXN 3 <29>

EDP_AUX P <29> EDP_AUX N <29 >

@

T194

AUD_AZA CPU_SCLK <18> AUD_AZA CPU_SDO <18>

AUD_AZA CPU_SDI

RC66 20_0402_ 5%

1 2

MUX PS8331

AUD_AZA CPU_SDI_R

EDP_COM P

min Trace width=5 mils ,Spacing=20mil Max length= 600 mils.

AUD_AZA CPU_SDI_R <18>

+1.0VS_V CCIO

1 2

RC1 2 4.9_0402_1%

A A

Security Class ification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2016/01/ 01

3

Compal Secret Data

Deciphered Date

2017/01/ 01

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

CFL-H(4/8) DDI,eDP

Size Doc ument Number Rev

A

LA-H271P

Tuesday, April 09, 2019

Date: Sheet of

1

9 103

1.0

5

VSS_A36

VSS_A37

BR1 BT2

BN35

H24 BN33 BL34

N29

R14 AE29 AA14 AP29 AP14

A36

H23

F30

E30

B30

C30

BR35 BR31 BH30

J24

A37

J23

E2

E3

E1

D1

G3

J3

1

T4PAD~D @ T3PAD~D @ T2PAD~D @

D D

PCH_2_C PU_TRIGGER<20>

C C

T1PAD~D @

T5PAD~D @ T6PAD~D @

T7PAD~D @

T9PAD~D @ T10PAD~D @ T11PAD~D @ T8PAD~D @

T14PAD~D @ T13PAD~D @ T15PAD~D @

T12PAD~D @ T28PAD~D @ T27PAD~D @

T285PAD~D @

T281PAD~D @

T18PAD~D @ T19PAD~D @

T21PAD~D @ T20PAD~D @

T23PAD~D @ T24PAD~D @ T22PAD~D @

IST_TRIG

1 1 1

1 1

1

1 1 1 1

1 1 1 1 1 1

PCH_2_C PU_TRIGGER CPU_2_P CH_TRIGGER_R

TP_SKL_ F30

1

TP_SKL_ E30

1

1 1

1 1 1

4

UC1M

RSVD_TP5 IST_TRIG RSVD_TP4 RSVD_TP3

RSVD_TP1 RSVD_TP2

RSVD15

RSVD28 RSVD27 RSVD14 RSVD13

RSVD30 RSVD31 RSVD2 RSVD1 RSVD5 RSVD4 VSS_A36

VSS_A37

PROC_TRIGIN PROC_TRIGOUT

RSVD24

RSVD23

RSVD7 RSVD21

RSVD26 RSVD29

RSVD19 RSVD18 RSVD9

CFL-H_BG A1440

CFL-H

13 OF 13

RSVD11 RSVD10

RSVD12

RSVD3

RSVD25

RSVD22 RSVD20 RSVD17 RSVD16

RSVD8 RSVD6

BK28 BJ28

BL31 AJ8 G13

C38 C1 BR2 BP1 B38 B2

1 1

1 1 1

1 1 1 1 1 1

T29 PAD~D@ T30 PAD~D@

T297 PAD~ D

@

T298 PAD~ D

@

T299 PAD~ D

@

T300 PAD~ D

@

T301 PAD~ D

@

T302 PAD~ D

@

T303 PAD~ D

@

T304 PAD~ D

@

T305 PAD~ D

@

3

FOLLOW PDG V1P8 P.616 downsize to SE00000UD00 11x 10uF 0402

close to UC1.Y12

10U_0402_6.3V6M

1

CC185

2

+1.0VS_V CCIO

PLACE CAP BACKSIDE

10U_0603_6.3V6M

12

+1.0V_VC CST

1U_0201_10V6M

2

1

2

1U_0201_6.3V6M

2

1

10U_0603_6.3V6M

1U_0201_6.3V6M

2

CC186

1

10U_0603_6.3V6M

CC187

12

PLACE CAP BACKSIDE

1U_0201_6.3V6M

@

2

CC195

1

+1.0V_VCCSFR

@

CC272

1

CC192

2

PLACE CAP BACKSIDE or BOARD EDGE

+1.0V_VC CSTG +1.0V_VCCSF R_R +1.0V _VCCST

10U_0603_6.3V6M

CC188

CC189

12

1U_0201_10V6M

2

CC193

CC194

1

22U_0603_6.3V6M

1U_0201_6.3V6M

CC333

2

CC191

1

follow Berlineeta add 22uF to solve PS4 idle hang location:CC568 CC569 3/21

LC562

BLM18EG 221TN1D_2P~D

1 2

Change LC422 from 0_0603_5% to Beads

@

1

CC569

2

+VCC_SF R_OC+1.2V_ME M

22U_0603_6.3V6M

+1.0V_VC CSFR_R

1

22U_0603_6.3V6M

1U_0201_6.3V6M

2

CC210

1

22U_0603_6.3V6M

2

1

@

1

2

CC568

CC209

2

1

CC335

downsize

+1.2V_ME M

B B

A A

5

CPU_2_P CH_TRIGGER<20>

VSS_A36 VSS_A37

1 2

RC177 30_0402 _5%

1 2

RC178 0_0402_ 5%@

1 2

RC179 0_0402_ 5%@

4

CPU_2_P CH_TRIGGER_RCPU_2_P CH_TRIGGER

Security Class ification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2016/01/ 01

3

+1.2V_MEM DECOUPLING

10U_0402_6.3V6M

1

CC161

2

22U_0603_6.3V6M

12

CC81

Compal Secret Data

Deciphered Date

1

CC170

CC164

2

22U_0603_6.3V6M

12

CC83

CC82

CC168

12

10U_0402_6.3V6M

1

CC163

2

22U_0603_6.3V6M

CC84

PLACE CAP BACKSIDE

10U_0402_6.3V6M

1

CC166

CC171

2

2017/01/ 01

2

10U_0402_6.3V6M

1

CC165

CC172

CC167

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

CFL-H(5/8) RSVD,Decoupling

Size Doc ument Number Rev

Custom

LA-H271P

Tuesday, April 09, 2019

Date: Sheet of

1

10 103

1.0

5

4

3

2

1

+VCCPLL_OC source

+VCC_GT

AT14

D D

C C

B B

AT31 AT32 AT33 AT34 AT35 AT36 AT37

AT38 AU14 AU29 AU30 AU31 AU32 AU35 AU36 AU37 AU38 AV29 AV30 AV31 AV32 AV33 AV34 AV35 AV36

AW14 AW31 AW32 AW33 AW34 AW35 AW36 AW37 AW38

AY29 AY30 AY31 AY32 AY35 AY36 AY37 AY38 BA13 BA14 BA29 BA30 BA31 BA32 BA33 BA34 BA35 BA36 BB13 BB14 BB31 BB32 BB33 BB34 BB35 BB36 BB37 BB38 BC29 BC30 BC31 BC32 BC35 BC36 BC37 BC38 BD13 BD14 BD29 BD30 BD31 BD32 BD33 BD34 BP37 BP38 BR15 BR16 BR17

UC1K

VCCGT1 VCCGT2 VCCGT3 VCCGT4 VCCGT5 VCCGT6 VCCGT7 VCCGT8 VCCGT9 VCCGT10 VCCGT11 VCCGT12 VCCGT13 VCCGT14 VCCGT15 VCCGT16 VCCGT17 VCCGT18 VCCGT19 VCCGT20 VCCGT21 VCCGT22 VCCGT23 VCCGT24 VCCGT25 VCCGT26 VCCGT27 VCCGT28 VCCGT29 VCCGT30 VCCGT31 VCCGT32 VCCGT33 VCCGT34 VCCGT35 VCCGT36 VCCGT37 VCCGT38 VCCGT39 VCCGT40 VCCGT41 VCCGT42 VCCGT43 VCCGT44 VCCGT45 VCCGT46 VCCGT47 VCCGT48 VCCGT49 VCCGT50 VCCGT51 VCCGT52 VCCGT53 VCCGT54 VCCGT55 VCCGT56 VCCGT57 VCCGT58 VCCGT59 VCCGT60 VCCGT61 VCCGT62 VCCGT63 VCCGT64 VCCGT65 VCCGT66 VCCGT67 VCCGT68 VCCGT69 VCCGT70 VCCGT71 VCCGT72 VCCGT73 VCCGT74 VCCGT75 VCCGT76 VCCGT77 VCCGT78 VCCGT79 VCCGT159 VCCGT160 VCCGT161 VCCGT162 VCCGT163

CFL-H_BGA1440

CFL-H

VSSGT_SENSE

11 OF 13

VCCGT_SENSE

VCCGT80 VCCGT81 VCCGT82 VCCGT83 VCCGT84 VCCGT85 VCCGT86 VCCGT87 VCCGT88 VCCGT89 VCCGT90 VCCGT91 VCCGT92 VCCGT93 VCCGT94 VCCGT95 VCCGT96 VCCGT97 VCCGT98

VCCGT99 VCCGT100 VCCGT101 VCCGT102 VCCGT103 VCCGT104 VCCGT105 VCCGT106 VCCGT107 VCCGT108 VCCGT109 VCCGT110 VCCGT111 VCCGT112 VCCGT113 VCCGT114 VCCGT115 VCCGT116 VCCGT117 VCCGT118 VCCGT119 VCCGT120 VCCGT121 VCCGT122 VCCGT123 VCCGT124 VCCGT125 VCCGT126 VCCGT127 VCCGT128 VCCGT129 VCCGT130 VCCGT131 VCCGT132 VCCGT133 VCCGT134 VCCGT135 VCCGT136 VCCGT137 VCCGT138 VCCGT139 VCCGT140 VCCGT141 VCCGT142 VCCGT143 VCCGT144 VCCGT145 VCCGT146 VCCGT147 VCCGT148 VCCGT149 VCCGT150 VCCGT151 VCCGT152 VCCGT153 VCCGT154 VCCGT155 VCCGT156 VCCGT157 VCCGT158 VCCGT164 VCCGT165 VCCGT166 VCCGT167 VCCGT168

BD35 BD36 BE31 BE32 BE33 BE34 BE35 BE36 BE37 BE38 BF13 BF14 BF29 BF30 BF31 BF32 BF35 BF36 BF37 BF38 BG29 BG30 BG31 BG32 BG33 BG34 BG35 BG36 BH33 BH34 BH35 BH36 BH37 BH38 BJ16 BJ17 BJ19 BJ20 BJ21 BJ23 BJ24 BJ26 BJ27 BJ37 BJ38 BK16 BK17 BK19 BK20 BK21 BK23 BK24 BK26 BK27 BL15 BL16 BL17 BL23 BL24 BL25 BL26 BL27 BL28 BL36 BL37 BM15 BM16 BM17 BM36 BM37 BN15 BN16 BN17 BN36 BN37 BN38 BP15 BP16 BP17 BR37 BT15 BT16 BT17 BT37

AH37 AH38

+VCC_GT

+1.0VS_VCCIO

VSS_GT_SENSE <90> VCC_GT_SENSE <90>

+VCC_SA

CFL-H

UC1L

J30

VCCSA1

K29

VCCSA2

K30

VCCSA3

K31

VCCSA4

K32

VCCSA5

K33

VCCSA6

K34

VCCSA7

K35

VCCSA8

L31

VCCSA9

L32

VCCSA10

L35

VCCSA11

L36

VCCSA12

L37

VCCSA13

L38

VCCSA14

M29

VCCSA15

M30

VCCSA16

M31

VCCSA17

M32

VCCSA18

M33

VCCSA19

M34

VCCSA20

M35

VCCSA21

M36

VCCSA22

AG12

VCCIO1

G15

VCCIO2

G17

VCCIO3

G19 G21 H15 H16 H17 H19 H20 H21 H26 H27

J15 J16 J17 J19 J20 J21 J26 J27

CFL-H_BGA1440

VCCIO4 VCCIO5 VCCIO6 VCCIO7 VCCIO8 VCCIO9 VCCIO10 VCCIO11 VCCIO12 VCCIO13 VCCIO14 VCCIO15 VCCIO16 VCCIO17 VCCIO18 VCCIO19 VCCIO20 VCCIO21

VCCPLL_OC1 VCCPLL_OC2 VCCPLL_OC3

VCCSA_SENSE VSSSA_SENSE

VCCIO_SENSE VSSIO_SENSE

12 OF 13

+1.0V_VCCSTG +1.0V_VCCST

RZ151 0_0402_5%@

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8

VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16 VDDQ17 VDDQ18 VDDQ19 VDDQ20 VDDQ21 VDDQ22 VDDQ23 VDDQ24 VDDQ25

VCCST

VCCSTG2

VCCSTG1

VCCPLL1 VCCPLL2

1 2

AA6 AE12 AF5 AF6 AG5 AG9 AJ12 AL11 AP6 AP7 AR12 AR6 AT12 AW6 AY6 J5 J6 K12 K6 L12 L6 R6 T6 W6 Y12

BH13 BJ13 G11

H30

H29

G30

H28 J28

M38 M37

H14 J14

12A

+1.2V_MEM

+VCC_SFR_OC

0.1U_0402_25V6

12

+VCC_SFR_OC

+1.0V_VCCST

+1.0V_VCCSTG

+VCC_FUSEPRG

+1.0V_VCCSFR_R

VCC_SA_SENSE <90 > VSS_SA_SENSE <90>

VCC_IO_SENSE < 89> VSS_IO_SENSE <89>

+VCC_SFR_OC

RF Request

1 2

CZ102 1U_0 201_10V6M

VCCSTG_EN

ESD@

CC334

RZ543 10K_0402_5 %

1 2

CPU_C10_GATE#<14,89>

PCH_PRIM_EN<18 ,22,89>

SIO_SLP_S4#<11,18,19,88 >

0.1U_0201_ 25V6K

1

2

3

RC562 0_0201_5%

@

CZ544

12

UZ61

NC

A

GND

74AUP1G07GW _TSSOP5

1 2

@

1 2

RZ120 0_04 02_5%@

1

2

1U_0201_1 0V6M

+1.8V_PRIM

5

VCC

4

Y

+5V_ALW_R

+3.3V_ALW

5

IN1

IN2

3

CZ105

+3.3V_RUN+1.8V_PRIM

Reserve for SIO_SLP_S0#

+1.05V_PRIM

1

2

1U_0201_10V6M

CZ100

+5V_ALW_R

2

CC322

RF@

2.2P_0402_50V8C

+1.2V_MEM

@

CZ200

1 2

0.1U_0201_ 10V6K

VCC

4

OUT

GND

UZ34

@

MC74VHC1G08D FT2G_SC70-5

+1.0V_VCCSTG source

12

+5V_ALW_R

RZ542

10K_0402_5 %

1 2

C10_PWR _GATE#

RUN_ON<22,58,59,67,70,89>

+3.3V_ALW

1

IN1

2

IN2

+1.0V_VCCST source

Change CPN from SA00007XR00 to SA00008R600 3/12

UZ21

1

VIN1

2

VIN2

7

VIN thermal

3

VBIAS

4

ON

EM5201V_DFN3X3- 8-X

4.4mohm/6A TR=12.5us@Vin=1.05V

PDDG page19, if don`t support DS3, connect to VDDQ directly

+VCC_SFR_OC

1 2

RZ119 0_0402_5%@

Change CPN from SA00007XR00 to SA00008R600 3/12

UZ26

1

VIN1

2

VIN2

7

VIN thermal

3

VBIAS

4

ON

EM5201V_DFN3X3- 8-X

+1.05V_PRIM

Change CPN from SA00007XR00 to SA00008R600 3/12

5

VCC

VCCSTG_EN

4

OUT

GND

UZ35

3

MC74VHC1G08D FT2G_SC70-5

6

VOUT

5

GND

6

VOUT

5

GND

UZ19

1

VIN1

2

VIN2

7

VIN thermal

3

VBIAS

4

ON

EM5201V_DFN3X3- 8-X

4.4mohm/6A TR=12.5us@Vin=1.05V

+1.0V_VCCST_C

VOUT

0.1U_0201_10V6K

1

CZ101

2

6

5

GND

JUMP@

PJP1

PAD-OPEN1x1m

1 2

CZ199 0.1U_0 201_10V6K

+1.0V_VCCSTG

12

JUMP@

PJP2

PAD-OPEN1x1m

+1.0V_VCCSTG_C

1 2

12

RC304

@

+VCC_FUSEPRG

12

RC3260_0402_5% @

1 2

CZ106

0.1U_0201_ 10V6K

+1.0V_VCCSFR+1.0V_VCCST

0_0402_5%

SIO_SLP_S4#<11,18,19,88 >

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2016/01/01

Compal Secret Data

Deciphered Date

2017/01/01

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

CFL-H(6/8) PWR

Size Document Number Rev

B

LA-H271P

Tuesday, April 09, 2019

Date: Sheet of

1

11 103

1.0

5

4

3

2

1

+VCC_CO RE

AA13 AA31 AA32 AA33 AA34 AA35 AA36 AA37 AA38 AB29 AB30 AB31 AB32 AB35 AB36 AB37 AB38 AC13 AC14 AC29 AC30 AC31 AC32 AC33 AC34 AC35 AC36 AD13 AD14 AD31 AD32 AD33 AD34 AD35 AD36 AD37 AD38 AE13 AE14 AE30 AE31 AE32 AE35 AE36 AE37 AE38 AF29 AF30 AF31 AF32 AF33 AF34 AF35 AF36 AF37 AF38 AG14 AG31 AG32 AG33 AG34 AG35 AG36

UC1I

VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50 VCC51 VCC52 VCC53 VCC54 VCC55 VCC56 VCC57 VCC58 VCC59 VCC60 VCC61 VCC62 VCC63

CFL-H_BG A1440

CFL-H

9 OF 13

VCC64 VCC65 VCC66 VCC67 VCC68 VCC69 VCC70 VCC71 VCC72 VCC73 VCC74 VCC75 VCC76 VCC77 VCC78 VCC79 VCC80 VCC81 VCC82 VCC83 VCC84 VCC85 VCC86 VCC87 VCC88 VCC89 VCC90 VCC91 VCC92 VCC93 VCC94 VCC95 VCC96 VCC97 VCC98

VCC99 VCC100 VCC101 VCC102 VCC103 VCC104 VCC105 VCC106 VCC107 VCC108 VCC109 VCC110 VCC111 VCC112 VCC113 VCC114 VCC115 VCC116 VCC117 VCC118 VCC119 VCC120 VCC121 VCC122 VCC123 VCC124

VCC_SENSE VSS_SENSE

W35 W36 W37 W38 Y29 Y30 Y31 Y32 Y33 Y34 Y35 Y36

+VCC_CO RE

CFL-H

D D

C C

B B

K14

L13

L14 N13 N14 N30 N31 N32 N35 N36 N37 N38 P13 P14 P29 P30 P31 P32 P33 P34 P35 P36 R13 R31 R32 R33 R34 R35 R36 R37 R38 T29 T30 T31 T32 T35 T36 T37 T38 U29 U30 U31 U32 U33 U34 U35 U36 V13 V14 V31 V32 V33 V34 V35 V36 V37 V38

W13 W14 W29 W30 W31 W32

CFL-H_BG A1440

UC1J

VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50 VCC51 VCC52 VCC53 VCC54 VCC55 VCC56 VCC57 VCC58 VCC59 VCC60 VCC61 VCC62 VCC63

10 OF 13

VCC64 VCC65 VCC66 VCC67 VCC68 VCC69 VCC70 VCC71 VCC72 VCC73 VCC74 VCC75

AH13 AH14 AH29 AH30 AH31 AH32 AJ14 AJ29 AJ30 AJ31 AJ32 AJ33 AJ34 AJ35 AJ36 AK31 AK32 AK33 AK34 AK35 AK36 AK37 AK38 AL13 AL29 AL30 AL31 AL32 AL35 AL36 AL37 AL38 AM13 AM14 AM29 AM30 AM31 AM32 AM33 AM34 AM35 AM36 AN13 AN14 AN31 AN32 AN33 AN34 AN35 AN36 AN37 AN38 AP13 AP30 AP31 AP32 AP35 AP36 AP37 AP38 K13

AG37 AG38

+VCC_CO RE

VCC_SEN SE

VSS_SEN SE

VCC_SEN SE <90> VSS_SEN SE <90>

CFL change form +VCCGT to +VCC_CORE

A A

VSS_SEN SE VCC _SENSE

RC221 49.9_040 2_1%@

1 2

DELL CONFIDENTIAL/PROPRIETARY

Security Class ification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2016/01/ 01

3

Compal Secret Data

Deciphered Date

2017/01/ 01

2

Compal Electronics, Inc.

Title

CFL-H(7/8) +VCC_CORE

Size Doc ument Number Rev

Custom

LA-H271P

Tuesday, April 09, 2019

Date: Sheet of

1

12 103

1.0

5

4

3

2

1

CFL-H

UC1F

A10

VSS_1

A12

VSS_2

A16

VSS_3

A18

VSS_4

A20

VSS_5

A22

VSS_6

A24

VSS_7

A26

VSS_8

D D

C C

B B

A28 A30

AA12 AA29 AA30 AB33 AB34

AB6 AC1

AC12

AC2

AC3 AC37 AC38

AC4

AC5

AC6 AD10 AD11 AD12 AD29 AD30

AD6

AD8

AD9 AE33 AE34

AE6

AF1 AF12 AF13 AF14

AF2

AF3

AF4 AG10 AG11 AG13 AG29 AG30

AG6 AG7

AG8 AH12 AH33 AH34 AH35 AH36

AH6

AJ1

AJ13

AJ2

AJ3 AJ37 AJ38

AJ4

AJ5

AJ6

Y10 Y11 Y13 Y14 Y37 Y38

AK29 AK30

A6 A9

W4 W5

Y7 Y8 Y9

VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80

6 OF 13

VSS_81

CFL-H_BG A1440

VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98

VSS_99 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162

AK4 AL10 AL12 AL14 AL33 AL34 AL4 AL7 AL8 AL9 AM1 AM12 AM2 AM3 AM37 AM38 AM4 AM5 AN12 AN29 AN30 AN5 AN6 AP10 AP11 AP12 AP33 AP34 AP8 AP9 AR1 AR13 AR14 AR2 AR29 AR3 AR30 AR31 AR32 AR33 AR34 AR35 AR36 AR37 AR38 AR4 AR5 AT29 AT30 AT6 AU10 AU11 AU12 AU33 AU34 AU6 AU7 AU8 AU9 AV37 AV38 AW1 AW12 AW2 AW29 AW3 AW30 AW4 U6 V12 V29 V30 A14 AD7 V6 W1 W12 W2 W3 W33 W34

AW5 AY12 AY33 AY34

BA10 BA11 BA12 BA37 BA38

BA6 BA7 BA8 BA9 BB1

BB12

BB2

BB29

BB3

BB30

BB4 BB5

BB6 BC12 BC13 BC14 BC33 BC34

BC6 BD10 BD11 BD12 BD37

BD6

BD7

BD8

BD9

BE1

BE2 BE29

BE3 BE30

BE4

BE5

BE6 BF12 BF33 BF34

BF6 BG12 BG13 BG14 BG37 BG38

BG6

BH1 BH10 BH11 BH12 BH14

BH2

BH3

BH4

BH5

BH6

BH7

BH8

BH9

T33 T34

U37

U38 BJ12 BJ14

UC1G

VSS_163 VSS_164 VSS_165 VSS_166

B9

VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198 VSS_199 VSS_200 VSS_201 VSS_202 VSS_203 VSS_204 VSS_205 VSS_206 VSS_207 VSS_208 VSS_209 VSS_210 VSS_211 VSS_212 VSS_213 VSS_214 VSS_215 VSS_216 VSS_217 VSS_218 VSS_219 VSS_220 VSS_221 VSS_222 VSS_223 VSS_224 VSS_225 VSS_226 VSS_227 VSS_228 VSS_229 VSS_230

T2

VSS_231

T3

VSS_232 VSS_233 VSS_234

T4

VSS_235

T5

VSS_236

T7

VSS_237

T8

VSS_238

T9

VSS_239 VSS_240 VSS_241 VSS_242 VSS_243

CFL-H_BG A1440

CFL-H

7 OF 13

VSS_244 VSS_245 VSS_246 VSS_247 VSS_248 VSS_249 VSS_250 VSS_251 VSS_252 VSS_253 VSS_254 VSS_255 VSS_256 VSS_257 VSS_258 VSS_259 VSS_260 VSS_261 VSS_262 VSS_263 VSS_264 VSS_265 VSS_266 VSS_267 VSS_268 VSS_269 VSS_270 VSS_271 VSS_272 VSS_273 VSS_274 VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286 VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296 VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305 VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313 VSS_314 VSS_315 VSS_316 VSS_317 VSS_318 VSS_319 VSS_320 VSS_321 VSS_322 VSS_323 VSS_324

BJ15 BJ18 BJ22 BJ25 BJ29 BJ30 BJ31 BJ32 BJ33 BJ34 BJ35 BJ36 BK13 BK14 BK15 BK18 BK22 BK25 BK29 BK6 BL13 BL14 BL18 BL19 BL20 BL21 BL22 BL29 BL33 BL35 BL38 BL6 BM11 BM12 BM13 BM14 BM18 BM2 BM21 BM22 BM23 BM24 BM25 BM26 BM27 BM28 BM29 BM3 BM33 BM35 BM38 BM5 BM6 BM7 BM8 BM9 BN12 BN14 BN18 BN19 BN2 BN20 BN21 BN24 BN29 BN30 BN31 BN34 P38 P6 R12 R29 AY14 BD38 R30 T1 T10 T11 T12 T13 T14

BN4

BN7 BP12 BP14 BP18 BP21 BP24 BP25 BP26 BP29 BP33 BP34

BP7 BR12 BR14 BR18 BR21 BR24 BR25 BR26 BR29 BR34 BR36

BR7

BT12 BT14 BT18 BT21 BT24 BT26 BT29 BT32

M14

BT5 C11 C13 C15 C17 C19 C21 C23 C25 C27 C29 C31 C37

D10 D12 D14 D16 D18 D20 D22 D24 D26 D28

D30 D33

E34 E35 E38

N33 N34

P12 P37

F11 F13

UC1H

VSS_325 VSS_326 VSS_327 VSS_328 VSS_329 VSS_330 VSS_331 VSS_332 VSS_333 VSS_334 VSS_335 VSS_336 VSS_337 VSS_338 VSS_339 VSS_340 VSS_341 VSS_342 VSS_343 VSS_344 VSS_345 VSS_346 VSS_347 VSS_348 VSS_349 VSS_350 VSS_351 VSS_352 VSS_353 VSS_354 VSS_355 VSS_356 VSS_357 VSS_358 VSS_359 VSS_360 VSS_361 VSS_362 VSS_363 VSS_364 VSS_365 VSS_366 VSS_367 VSS_368 VSS_369

C5

VSS_370

C8

VSS_371

C9

VSS_372 VSS_373 VSS_374 VSS_375 VSS_376 VSS_377 VSS_378 VSS_379 VSS_380 VSS_381 VSS_382

D3

VSS_383 VSS_384 VSS_385

D6

VSS_386

D9

VSS_387 VSS_388 VSS_389 VSS_390

E4

VSS_391

E9

VSS_392

N3

VSS_393 VSS_394 VSS_395

N4

VSS_396

N5

VSS_397

N6

VSS_398

N7

VSS_399

N8

VSS_400

N9

VSS_401 VSS_402 VSS_403 VSS_404

M6

VSS_405

N1

VSS_406 VSS_407 VSS_408

CFL-H_BG A1440

CFL-H

VSS_409 VSS_410 VSS_411 VSS_412 VSS_413 VSS_414 VSS_415 VSS_416 VSS_417 VSS_418 VSS_419 VSS_420 VSS_421 VSS_422 VSS_423 VSS_424 VSS_425 VSS_426 VSS_427 VSS_428 VSS_429 VSS_430 VSS_431 VSS_432 VSS_433 VSS_434 VSS_435 VSS_436 VSS_437 VSS_438 VSS_439 VSS_440 VSS_441 VSS_442 VSS_443 VSS_444 VSS_445 VSS_446 VSS_447 VSS_448 VSS_449 VSS_450 VSS_451 VSS_452 VSS_453 VSS_454 VSS_455 VSS_456 VSS_457 VSS_458 VSS_459 VSS_460 VSS_461 VSS_462 VSS_463 VSS_464 VSS_465 VSS_466 VSS_467 VSS_468 VSS_469 VSS_470 VSS_471 VSS_472 VSS_473 VSS_474 VSS_475 VSS_476 VSS_477 VSS_478 VSS_479

VSS_A34

VSS_B37

VSS_BR38

VSS_BT3 VSS_BT35 VSS_BT36

VSS_BT4

8 OF 13

VSS_D38

VSS_A3

VSS_A4 VSS_B3

VSS_C2

F15 F17 F19 F2 F21 F23 F25 F27 F29 F3 F31 F36 F4 F5 F8 F9 G10 G12 G14 G16 G18 G20 G22 G23 G24 G26 G28 G4 G5 G6 G8 G9 H11 H12 H18 H22 H25 H32 H35 J10 J18 J22 J25 J32 J33 J36 J4 J7 K1 K10 K11 K2 K3 K38 K4 K5 K7 K8 K9 L29 L30 L33 L34 M12 M13 N10 N11 N12 N2 BT8 BR9

A3 A34 A4 B3 B37 BR38 BT3 BT35 BT36 BT4 C2 D38

A A

Security Class ification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2016/01/ 01

3

Compal Secret Data

Deciphered Date

2017/01/ 01

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

CFL-H(8/8) GND

Size Doc ument Number Rev

A

LA-H271P

Tuesday, April 09, 2019

Date: Sheet of

1

13 103

1.0

5

4

3

2

1

38.4/19.2MHz (default)

Integrated CNVi disable

Integrated CNVi enable

+1.8V_PRIM

12

RH604

4.7K_0201_5%

12

@

RH603

10K_0201_5%

+1.8V_PRIM

1 2

RH605

20K_0201_5%

12

@

RH606

100K_0201_5%

0=SATA

1=PCIE

0=SATA 1=PCIE

+1.8V_PRIM

12

@

RH607

CNV_COEX1

D D

1 2

@

CNV_COEX2<52> CNV_COEX1<52>

1 2

RH6 0_0402_ 5%@

CAM_MIC_CBL _DET#

CONTACTLESS_DET#

HOST_SD_W P#

1 2

RH616 0_0402_5%@

CNV_BRI_PTX_D RX

CNV_BRI_PRX _DTX

CNV_RGI_PTX_DR X

CNV_RGI_PRX_ DTX

BIOS_REC

GPP_J1 CNV_W T_RCOMP

CAM_MIC_CBL _DET#<38>

GPU_EVENT#<27 >

TBT_CIO_PLUG_EVE NT#<42>

GPU_GC6_FB_EN<27>

CONTACTLESS_DE T#<65>

HOST_SD_W P#<7 0>

SMART_SPK_DET0#<56>

FOLLOW X10 H Dell GPIO map

CNV_COEX3<52>

CPU_C10_GA TE#<11,89>

RH446

SIO_SLP_S0#<1 8,19,65>

+1.8V_PRIM

RH614 20K_0 402_5%@

RH613 20K_0 402_5%@

CFL PDG rev0.5 To avoid floating input at the I/O pin it is recommended to add a weak pull up resistor to the SOC pi n with a recommended value of 20K ohm.

C C

+3.3V_RUN

1 2

RH319 10K_ 0201_5%

1 2

RH214 100K _0402_5%

1 2

RH324 10K_ 0402_5%

1 2

RH76 10K_0402_5 %

@RTD3@

RT644 100K_0402_5 %

1 2

RH90 10K_0402_5 %

1 2

RH380 10K_ 0402_5%

B B

1 2

RH325 10K_ 0201_5%@

1 2

RH326 10K_ 0201_5%@

1 2

RH344 10K_ 0402_5%

1 2

RT616 100K_0402_5%@

+3.3V_ALW _PCH

RTD3@

RT615 100K_0402_5 %

1 2

CAM_MIC_CBL _DET#

HOST_SD_W P#

HDD_DET#

BIOS_REC

Reserve +3.3V_RUN for PCH_TBT_PERST# 4/8

1 2

CONTACTLESS_DE T#

SATALED#

SATAGP5

SATAGP6

SATAGP0

PCH_TBT_PERST#

FOLLOW X10 H Dell GPIO map

1 2

CNV_BRI_PRX _DTX

CNV_RGI_PRX_ DTX

PCH_TBT_PERST#

M.2 SSD Slot#3

Tell EC don't read GFX Temp.in GC6 High: Read; Low: Don`t read

M.2 SSD Slot#6

HDD

M.2 SSD Slot#3

M.2 SSD Slot#4

0_0201_5%

CNV_BRI_PTX_D RX<52>

CNV_BRI_PRX_DTX< 52>

CNV_RGI_PTX_DR X<52 >

CNV_RGI_PRX_DTX<52>

PCH_CL_CLK 1<52>

PCH_CL_DA TA1<52>

PCH_CL_RS T1#<52>

PCIE_PTX_DRX _P11<67> PCIE_PTX_DRX _N11<67>

PCIE_PRX_DTX _P11<67> PCIE_PRX_DTX _N11<67>

GC6_THM_ON< 59>

PCIE_PTX_DRX _P12<67> PCIE_PTX_DRX _N12<67>

PCIE_PRX_DTX _P12<67> PCIE_PRX_DTX _N12<67>

PCIE_PTX_DRX _P20<67> PCIE_PTX_DRX _N20<67> PCIE_PRX_DTX _P20<67> PCIE_PRX_DTX _N20<67> PCIE_PTX_DRX _P19<67> PCIE_PTX_DRX _N19<67> PCIE_PRX_DTX _P19<67> PCIE_PRX_DTX _N19<67>

UH1M

AW13

GPP_G0/SD_CMD

BE9

GPP_G1/SD_DATA0

BF8

GPP_G2/SD_DATA1

BF9

GPP_G3/SD_DATA2

BG8

GPP_G4/SD_DATA3

BE8

GPP_G5/SD_CD#

BD8

GPP_G6/SD_CLK

AV13

GPP_G7/SD_WP

AP3

GPP_I11/M2_SKT2_CFG0

AP2

GPP_I12/M2_SKT2_CFG1

AN4

GPP_I13/M2_SKT2_CFG2

AM7

GPP_I14/M2_SKT2_CFG3

AV6

GPP_J0/CNV_PA_BLANKING

AY3

GPP_J1/CPU_C10_GATE#

AR13

GPP_J11/A4WP_PRESENT

AV7

GPP_J10

AW3

GPP_J_2

AT10

GPP_J_3

AV4

GPP_J4/CNV_BRI_DT/UART0B_RTS#

AY2

GPP_J5/CNV_BRI_RSP/UART0B_RXD

BA4

GPP_J6/CNV_RGI_DT/UART0B_TXD

AV3

GPP_J7/CNV_RGI_RSP/UART0B_CTS#

AW2

GPP_J8/CNV_MFUART2_RXD

AU9

GPP_J9/CNV_MFUART2_TXD

CNP-H_BGA87 4

UH1C

AR2

CL_CLK

AT5

CL_DATA

AU4

CL_RST#

P48

GPP_K8

V47

GPP_K9

V48

GPP_K10

W47

GPP_K11

L47

GPP_K0

L46

GPP_K1

U48

GPP_K2

U47

GPP_K3

N48

GPP_K4

N47

GPP_K5

P47

GPP_K6

R46

GPP_K7

C36

PCIE11_TXP/SATA0A_TXP

B36

PCIE11_TXN/SATA0A_TXN

F39

PCIE11_RXP/SATA0A_RXP

G38

PCIE11_RXN/SATA0A_RXN

AR42

GPP_F10/SATA_SCLOCK

AR48

GPP_F11/SATA_SLOAD

AU47

GPP_F13/SATA_SDATAOUT0

AU46

GPP_F12/SATA_SDATAOUT1

C39

PCIE14_TXN/SATA1B_TXN

D39

PCIE14_TXP/SATA1B_TXP

D46

PCIE14_RXN/SATA1B_RXN

C47

PCIE14_RXP/SATA1B_RXP

B38

PCIE13_TXN/SATA0B_TXN

C38

PCIE13_TXP/SATA0B_TXP

C45

PCIE13_RXN/SATA0B_RXN

C46

PCIE13_RXP/SATA0B_RXP

E37

PCIE12_TXP/SATA1A_TXP

D38

PCIE12_TXN/SATA1A_TXN

J41

PCIE12_RXP/SATA_1A_RXP

H42

PCIE12_RXN/SATA1A_RXN

B44

PCIE20_TXP/SATA7_TXP

A44

PCIE20_TXN/SATA7_TXN

R37

PCIE20_RXP/SATA7_RXP

R35

PCIE20_RXN/SATA7_RXN

D43

PCIE19_TXP/SATA6_TXP

C44

PCIE19_TXN/SATA6_TXN

N42

PCIE19_RXP/SATA6_RXP

M44

PCIE19_RXN/SATA6_RXN

CNP-H_BGA87 4

CNP-H

CNV_WR_CLKN

CNV_WR_CLKP

CNV_WR_D0N CNV_WR_D0P CNV_WR_D1N CNV_WR_D1P

CNV_WT_CLKN CNV_WT_CLKP

CNV_WT_D0N CNV_WT_D0P CNV_WT_D1N CNV_WT_D1P

CNV_WT_RCOMP

PCIE_RCOMPN

PCIE_RCOMPP SD_1P8_RCOMP SD_3P3_RCOMP

GPPJ_RCOMP_1P81 GPPJ_RCOMP_1P82 GPPJ_RCOMP_1P83

RSVD2 RSVD3

13 OF 13

CNP-H

GPP_E0/SATAXPCIE0/SATAGP0 GPP_E1/SATAXPCIE1/SATAGP1 GPP_E2/SATAXPCIE2/SATAGP2

GPP_F0/SATAXPCIE3/SATAGP_3

GPP_F1/SATAXPCIE4/SATAGP4 GPP_F2/SATAXPCIE5/SATAGP5 GPP_F3/SATAXPCIE6/SATAGP6 GPP_F4/SATAXPCIE7/SATAGP7

3 OF 13

RSVD1

PCIE9_RXN PCIE9_RXP PCIE9_TXN PCIE9_TXP

PCIE10_RXN PCIE10_RXP PCIE10_TXN PCIE10_TXP

PCIE15_RXN/SATA2_RXN PCIE15_RXP/SATA2_RXP

PCIE_15_SATA_2_TXN

PCIE15_TXP/SATA2_TXP

PCIE16_RXN/SATA3_RXN PCIE16_RXP/SATA3_RXP PCIE16_TXN/SATA3_TXN

PCIE16_TXP/SATA3_TXP

PCIE17_RXN/SATA4_RXN PCIE17_RXP/SATA4_RXP PCIE17_TXN/SATA4_TXN

PCIE17_TXP/SATA4_TXP

PCIE18_RXN/SATA5_RXN PCIE18_RXP/SATA5_RXP PCIE18_TXN/SATA5_TXN

PCIE18_TXP/SATA5_TXP

GPP_E8/SATA_LED#

GPP_F21/EDP_BKLTCTL

GPP_F20/EDP_BKLTEN

GPP_F19/EDP_VDDEN

THRMTRIP#

PM_SYNC

PLTRST_CPU#

PM_DOWN

BD4 BE3

BB3 BB4 BA3 BA2

BC5 BB6

BE6 BD7 BG6 BF6 BA1

B12

PCIECOMP#

A13

PCIECOMP SD_RCOMP_1 P8

BE5

SD_RCOMP_3 P3

BE4 BD1

GPPJ_RCOMP

BE1 BE2

Y35 Y36

BC1 AL35

TP

Rev1.0

G36 F36 C34 D34

K37 J37 C35 B35

F44 E45 B40 C40

L41 M40 B41 C41

K43 K44 A42 B42

P41 R40 C42 D42

AK48

AH41 AJ43 AK47 AN47 AM46 AM43 AM47 AM48

AU48 AV46 AV44

AD3 AF2

PECI

AF3 AG5 AE2

Rev1.0

CLK_CNV_PRX_DTX_N <52> CLK_CNV_PRX_DTX_P <52>

CNV_PRX_DTX_N0 <52>

CNV_PRX_DTX_P0 <52>

CNV_PRX_DTX_N1 <52>

CNV_PRX_DTX_P1 <52>

CLK_CNV_P TX_DRX_N <5 2> CLK_CNV_P TX_DRX_P <52>

CNV_PTX_DRX _N0 <52> CNV_PTX_DRX _P0 <52> CNV_PTX_DRX _N1 <52> CNV_PTX_DRX _P1 <52>

12

RH612 150_0402_1%

12

RH192 100_0402_1%

12 12

RH611 200_040 2_1%

200_0402_1 %

RH610

12

RH609 200_0402_1 %

1

T34 PAD ~D@

1

T33 PAD ~D@

1

T36 PAD ~D@

1

T35 PAD ~D@

PCIE_PRX_DTX _N9 <67> PCIE_PRX_DTX _P9 <67> PCIE_PTX_DRX _N9 <67> PCIE_PTX_DRX _P9 <67>

PCIE_PRX_DTX _N10 <67>

PCIE_PRX_DTX _P10 <67> PCIE_PTX_DRX _N10 <67> PCIE_PTX_DRX _P10 <67>

PCIE_PRX_DTX _N17 <67>

PCIE_PRX_DTX _P17 <67> PCIE_PTX_DRX _N17 <67> PCIE_PTX_DRX _P17 <67>

PCIE_PRX_DTX _N18 <67>

PCIE_PRX_DTX _P18 <67> PCIE_PTX_DRX _N18 <67>

SATALED#

SATAGP0

HDD_DET#

SATAGP5 SATAGP6 PCH_TBT_PERST#

PCH_THERMTRIP# PCH_PECI H_PECI H_PM_SYNC_ R H_PM_SYNC

PCIE_PTX_DRX _P18 <67>

SATALED# <67,68>

M2_SLOT3_PE DET <67>

HDD_DET# <67 >

M2_SLOT5_PE DET <68>

M2_SLOT4_PE DET <67>

Reserved

PCH_TBT_PERST# <42>

FOLLOW X10 H Dell GPIO map

BIA_PW M_PCH <38> PANEL_BK EN_PCH <3 8> ENVDD_PCH <38>

1 2 1 2

RH75 620_0402_5 %

1 2

RH73 13_0402_5% RH156 30_040 2_5%

PLTRST_CPU# <7>

H_PM_DOW N <7>

PCH_PECI

VCCSPI hard strap

LOW

*

M.2 SSD Slot#3

M.2 SSD Slot#6

M.2 SSD Slot#4

H_THERMTRIP# <7,23,24,25,26,59 > H_PECI <7,58>

H_PM_SYNC < 7>

12

RH74

@

10K_0402_5 %

1.8VHIGH

3.3V

100K_0201_5%

12

RH608

100K_0201_5%

SPSGP0

SPSGP1

10M2_SLOT3_PEDET

SPSGP2

1

SPSGP3

1 0=SATA 1=PCIE

SPSGP4 M2_SLOT4_PEDET

CNV_BRI_PTX_D RX

Xtal Frequency select

HIGH 24MHz

*

LOW

CNP EDS rev0.7 An external pull-up is required on this strap since 38.4 MHz XTAL is not supported on the PCH.

CNV_RGI_PTX_DR X

M.2 CNV Mode Select

HIGH

*

LOW

SATAGP0

HDD_DET#

M2_SLOT5_PEDET

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2016/01/01

Compal Secret Data

Deciphered Date

2

2017/01/01

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

CNP-H(1/9) PCIE,CNV

Size Docum ent Number Rev

C

LA-H271P

Tuesday, April 09, 2019

Date: Sheet of

1

14 103

1.0

5

D D

XDP_DBRESET#<7>

RH70 8.2K_0402_5%@

4

ME_RESET#

12

CIS LINK OK

UC3

@

1

IN B

VCC

2

IN A

GND3OUT Y

TC7SH09FU_SSOP5

12

RH660_0402_5% @

+3.3V_RUN

5

4

CH10

@

1 2

0.1U_0201_25V6K

3

SYS_RESET#

SYS_RESET# <18,19>

2

1

UH1B

DMI_CTX_PRX_N0<6> DMI_CTX_PRX_P0<6> DMI_CRX_PTX_N0<6> DMI_CRX_PTX_P0<6> DMI_CTX_PRX_N1<6> DMI_CTX_PRX_P1<6> DMI_CRX_PTX_N1<6>

C C

B B

TR TBT

LAN

SD CARD

WLAN

WWAN

DMI_CRX_PTX_P1<6> DMI_CTX_PRX_N2<6> DMI_CTX_PRX_P2<6> DMI_CRX_PTX_N2<6> DMI_CRX_PTX_P2<6> DMI_CTX_PRX_N3<6> DMI_CTX_PRX_P3<6> DMI_CRX_PTX_N3<6> DMI_CRX_PTX_P3<6>

PCIE_PRX_TTX_N1<42> PCIE_PRX_TTX_P1<42> PCIE_PTX_TRX_N1<42> PCIE_PTX_TRX_P1<42> PCIE_PRX_TTX_N2<42> PCIE_PRX_TTX_P2<42> PCIE_PTX_TRX_N2<42> PCIE_PTX_TRX_P2<42> PCIE_PRX_TTX_N3<42> PCIE_PRX_TTX_P3<42> PCIE_PTX_TRX_N3<42> PCIE_PTX_TRX_P3<42> PCIE_PRX_TTX_N4<42> PCIE_PRX_TTX_P4<42> PCIE_PTX_TRX_N4<42> PCIE_PTX_TRX_P4<42> PCIE_PRX_DTX_N5<51> PCIE_PRX_DTX_P5<51> PCIE_PTX_DRX_N5<51> PCIE_PTX_DRX_P5<51> PCIE_PRX_DTX_N6<70> PCIE_PRX_DTX_P6<70> PCIE_PTX_DRX_N6<70> PCIE_PTX_DRX_P6<70> PCIE_PTX_DRX_P7<52> PCIE_PTX_DRX_N7<52> PCIE_PRX_DTX_P7<52> PCIE_PRX_DTX_N7<52> PCIE_PRX_DTX_N8<52> PCIE_PRX_DTX_P8<52> PCIE_PTX_DRX_N8<52> PCIE_PTX_DRX_P8<52>

1

@

T286PAD~D

1

@

T78PAD~D

1

@

T79PAD~D

1

@

T80PAD~D

1

@

T81PAD~D

1

@

T82PAD~D

1

@

T83PAD~D

1

@

T84PAD~D

1

@

T85PAD~D

1

@

T86PAD~D

1

@

T87PAD~D

1

@

T88PAD~D

1

@

T89PAD~D

1

@

T90PAD~D

1

@

T91PAD~D

1

@

T92PAD~D

K34

DMI0_RXN

J35

DMI0_RXP

C33

DMI0_TXN

B33

DMI0_TXP

G33

DMI1_RXN

F34

DMI1_RXP

C32

DMI1_TXN

B32

DMI1_TXP

K32

DMI2_RXN

J32

DMI2_RXP

C31

DMI2_TXN

B31

DMI2_TXP

G30

DMI3_RXN

F30

DMI3_RXP

C29

DMI3_TXN

B29

DMI3_TXP

A25

RSVD1

B25

RSVD2

P24

RSVD3

R24

RSVD4

C26

RSVD5

B26

RSVD6

F26

RSVD7

G26

RSVD8

B27

RSVD9

C27

RSVD10

L26

RSVD11

M26

RSVD12

D29

RSVD13

E28

RSVD14

K29

RSVD15

M29

RSVD16

G17

PCIE1_RXN/USB31_7_RXN

F16

PCIE1_RXP/USB31_7_RXP

A17

PCIE1_TXN/USB31_7_TXN

B17

PCIE1_TXP/USB31_7_TXP

R21

PCIE2_RXN/USB31_8_RXN

P21

PCIE2_RXP/USB31_8_RXP

B18

PCIE2_TXN/USB31_8_TXN

C18

PCIE2_TXP/USB31_8_TXP

K18

PCIE3_RXN/USB31_9_RXN

J18

PCIE3_RXP/USB31_9_RXP

B19

PCIE3_TXN/USB31_9_TXN

C19

PCIE3_TXP/USB31_9_TXP

N18

PCIE4_RXN/USB31_10_RXN

R18

PCIE4_RXP/USB31_10_RXP

D20

PCIE4_TXN/USB31_10_TXN

C20

PCIE4_TXP/USB31_10_TXP

F20

PCIE5_RXN

G20

PCIE5_RXP

B21

PCIE5_TXN

A22

PCIE5_TXP

K21

PCIE6_RXN

J21

PCIE6_RXP

D21

PCIE6_TXN

C21

PCIE6_TXP

B23

PCIE7_TXP

C23

PCIE7_TXN

J24

PCIE7_RXP

L24

PCIE7_RXN

F24

PCIE8_RXN

G24

PCIE8_RXP

B24

PCIE8_TXN

C24

PCIE8_TXP

CNP-H_BGA874

CNP-H

GPP_E9/USB2_OC0# GPP_E10/USB2_OC1# GPP_E11/USB2_OC2# GPP_E12/USB2_OC3#

GPP_F15/USB2_OC4# GPP_F16/USB2_OC5# GPP_F17/USB2_OC6# GPP_F18/USB2_OC7#

USB2_VBUSSENSE

2 OF 13

USB2N_1

USB2P_1

USB2N_2

USB2P_2

USB2N_3

USB2P_3

USB2N_4

USB2P_4

USB2N_5

USB2P_5

USB2N_6

USB2P_6

USB2N_7

USB2P_7

USB2N_8

USB2P_8

USB2N_9

USB2P_9 USB2N_10 USB2P_10 USB2N_11 USB2P_11 USB2N_12 USB2P_12 USB2N_13 USB2P_13 USB2N_14 USB2P_14

USB2_COMP

RSVD_1

USB2_ID

GPD7

PCIE24_TXP PCIE24_TXN PCIE24_RXP PCIE24_RXN PCIE23_TXP PCIE23_TXN PCIE23_RXP PCIE23_RXN PCIE22_TXP PCIE22_TXN PCIE22_RXP PCIE22_RXN PCIE21_TXP PCIE21_TXN PCIE21_RXP PCIE21_RXN

Rev1.0

J3 J2 N13 N15 K4 K3 M10 L9 M1 L2 K7 K6 L4 L3 G4 G5 M6 N8 H3 H2 R10 P9 G1 G2 N3 N2 E5 F6

AH36 AL40 AJ44 AL41 AV47 AR35 AR37 AV43

F4 F3 U13 G3

BE41

G45 G46 Y41 Y40 G48 G49 W44 W43 H48 H47 U41 U40 F46 G47 R44 T43

USB20_N6

1

USB20_P6

1

USB_OC0# USB_OC1# USB_OC2# USB_OC3#

USB_OC4# USB_OC5# USB_OC6# USB_OC7#

USB2_COMP

USB2_VBUSSENSE

1

USB2_ID

TBT_RTD3_WAKE#_GPD 7

T40 PAD~D@

USB20_N1 <71> USB20_P1 <71> USB20_N2 <71> USB20_P2 <71>

USB20_N4 <44> USB20_P4 <44> USB20_N5 <44>

USB20_P5 <44>

T313 PAD~D@ T314 PAD~D@

USB20_N8 <52>

USB20_P8 <52> USB20_N9 <38>

USB20_P9 <38>

USB20_N10 <65>

USB20_P10 <65>

USB20_N11 <38>

USB20_P11 <38>

USB20_N14 <52>

USB20_P14 <52>

Reserve Reserve

RH735 0_0402_5%@

----->JUSB1

----->JUSB2

----->Cypress PD

-----> M.2 2230 (BT)

----->M.2 Slot-2 (WWAN/LTE/HCA)

----->Touch Screen

----->USH

----->Camera

CNVi

Reserve

USB_OC1# <71> USB_OC2# <71>

Reserve

USB_OC4# <44> USB_OC5# <44>

1 2

RH193 113_0402_1%

1 2

RH364 1K_0402_5%

1 2

RH365 0_0402_5%@

1 2

PCIE_PTX_DRX_P24 <68> PCIE_PTX_DRX_N24 <68>

PCIE_PRX_DTX_P24 <68> PCIE_PRX_DTX_N24 <68> PCIE_PTX_DRX_P23 <68> PCIE_PTX_DRX_N23 <68>

PCIE_PRX_DTX_P23 <68> PCIE_PRX_DTX_N23 <68> PCIE_PTX_DRX_P22 <68> PCIE_PTX_DRX_N22 <68>

PCIE_PRX_DTX_P22 <68> PCIE_PRX_DTX_N22 <68>

PCIE_PTX_DRX_P21 <68> PCIE_PTX_DRX_N21 <68>

PCIE_PRX_DTX_P21 <68>

PCIE_PRX_DTX_N21 <68>

----->M.2 Slot-1 (WLAN/BT/WiGig)

----->JUSB1

----->JUSB2

----->TypeC PortA

----->TypeC PortB

TBT_RTD3_WAKE# <18,42>

M.2 SSD Slot#5

USB_OC1# USB_OC2# USB_OC3# USB_OC0#

RH710 10K_0402_5%1 2 RH711 10K_0402_5% RH712 10K_0402_5% RH713 10K_0402_5%1 2

USB_OC4#

RH714 10K_0402_5%

USB_OC5#

RH715 10K_0402_5%

USB_OC6#

RH716 10K_0402_5%

USB_OC7#

RH717 10K_0402_5%1 2

1 2 1 2

1 2 1 2 1 2

RP change to single Resistor

USB_OC3# USB_OC1# USB_OC0# USB_OC2#

TBT_RTD3_WAKE#_GPD 7

HIGH(DEFAULT) LOW

CFL CRB rev0.5 Xtal input High : differential Low : single-end

CNL- PCH EDS rev0.5 External pull-up is required. Recommend 100K if pulled up to 3.3V

1 2 1 2

RH718 15K_0402_5%@

1 2

RH719 15K_0402_5%@

1 2

RH720 15K_0402_5%@ RH721 15K_0402_5%@

RP change to single Resistor

1 2

RH602

Xtal input

100K_0402_5%

differential single-end

+3.3V_ALW_PCH

+3.3V_DSW

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

5

4

3

2016/01/01

Compal Secret Data

Deciphered Date

2

2017/01/01

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

CNP-H(2/9) PCIE,DMI,USB

Size Document Number Rev

Custom

LA-H271P

Tuesday, April 09, 2019

Date: Sheet of

15 103

1

1.0

5

4

3

2

1

UH1G

BE33

CPU_24MHZ_R_D P CH_CPU_NSSC_CLK_D CPU_24MHZ_R_D#

PCH_CPU_BCLK_R_D PCH_CPU_BCLK_R_D#

+1.0V_ALW_PCH

RH123 10K_0201_5%

+3.3V_RUN

RH124 10K_0201_5%

+3.3V_RUN

RH126 10K_0201_5%

+3.3V_RUN

RH127 10K_0201_5%

+3.3V_RUN

RH128 10K_0201_5%

+3.3V_RUN

RH130 10K_0201_5%

+3.3V_RUN

RH131 10K_0201_5%

+3.3V_RUN

RH132 10K_0201_5%

+3.3V_RUN

RH133 10K_0201_5%

+3.3V_RUN

RH134 10K_0201_5%

+3.3V_RUN

CH4

CH5

PCH_RTCX1_R

@

RH43 0_0402_5%

12

YH1

32.768KHZ_12.5PF_9H03200042

1 2

LAN

TBT

CPU_24MHZ_R_D<7> CPU_24MHZ_R_D#<7>

PCH_CPU_BCLK_R_D<7> PCH_CPU_BCLK_R_D#<7>

CLKREQ_PEG#0<27>

CLKREQ_PCIE#1<70>

CLKREQ_PCIE#2<52>

CLKREQ_PCIE#3<51>

CLKREQ_PCIE#4<42>

CLKREQ_PCIE#6<52>

CLKREQ_PCIE#7<67>

CLKREQ_PCIE#8<67>

CLKREQ_PCIE#9<68>

change from 15P to 18P 1/15

18P_0402_50V8J

D D

DGFF

Card reader

M.2 Slot2 WWAN

M.2 Slot1 WLAN

M.2 Slot3

M.2 Slot4

C C

B B

M.2 Slot5

1 2

RH169 0_0402_5%@

1 2

RH170 0_0402_5%@

1 2

RH161 0_0402_5%@

1 2

RH166 0_0402_5%@

pop RH171 for KBL-H pop RH435 for CFL-H , PDG 0.5

RH171 2.7K_0402_1%@

1 2 1 2

RH435

12

1 2

CLKREQ_PEG#0

CLKREQ_PCIE#1

CLKREQ_PCIE#2

CLKREQ_PCIE#3

CLKREQ_PCIE#4

CLKREQ_PCIE#6

CLKREQ_PCIE#7

CLKREQ_PCIE#8

CLKREQ_PCIE#9

CLKREQ_PCIE#10

60.4_0402_1%

PCH_RTCX1

12

RH44 10M_0402_5%

PCH_RTCX2

PCH_CPU_NSSC_CLK_D #

PCH_CPU_BCLK_D PCH_CPU_BCLK_D#

XTAL24_OUT_R1 XTAL24_IN_R1

XCLK_RBIAS

PCH_RTCX1 PCH_RTCX2

FOLLOW X10 H Dell GPIO map

GPP_A16/CLKOUT_48

D7

CLKOUT_CPUNSSC_P

C6

CLKOUT_CPUNSSC#

B8

CLKOUT_CPUBCLK_P

C8

CLKOUT_CPUBCLK#

U9

XTAL_OUT

U10

XTAL_IN

T3

XCLK_BIASREF

BA49

RTCX1

BA48

RTCX2

BF31

GPP_B5/SRCCLKREQ0#

BE31

GPP_B6/SRCCLKREQ1#

AR32

GPP_B7/SRCCLKREQ2#

BB30

GPP_B8/SRCCLKREQ3#

BA30

GPP_B9/SRCCLKREQ4#

AN29

GPP_B10/SRCCLKREQ5#

AE47

GPP_H0/SRCCLKREQ6#

AC48

GPP_H1/SRCCLKREQ7#

AE41

GPP_H2/SRCCLKREQ8#

AF48

GPP_H3/SRCCLKREQ9#

AC41

GPP_H4/SRCCLKREQ10#

AC39

GPP_H5/SRCCLKREQ11#

AE39

GPP_H6/SRCCLKREQ12#

AB48

GPP_H7/SRCCLKREQ13#

AC44

GPP_H8/SRCCLKREQ14#

AC43

GPP_H9/SRCCLKREQ15#

V2

CLKOUT_PCIE_N15

V3

CLKOUT_PCIE_P15

T2

CLKOUT_PCIE_N14

T1

CLKOUT_PCIE_P14

AA1

CLKOUT_PCIE_N13

Y2

CLKOUT_PCIE_P13

AC7

CLKOUT_PCIE_N12

AC6

CLKOUT_PCIE_P12

CNP-H_BGA874

XTAL24_IN_R1

XTAL24_OUT_R1

RH152 0_0201_5%

CNP-H

CLKOUT_ITPXDP#

CLKOUT_ITPXDP_P

CLKOUT_CPUPCIBCLK#

CLKOUT_CPUPCIBCLK_P

CLKOUT_PCIE_N0 CLKOUT_PCIE_P0

CLKOUT_PCIE_N1 CLKOUT_PCIE_P1

CLKOUT_PCIE_N2 CLKOUT_PCIE_P2

CLKOUT_PCIE_N3 CLKOUT_PCIE_P3

CLKOUT_PCIE_N4 CLKOUT_PCIE_P4

CLKOUT_PCIE_N5 CLKOUT_PCIE_P5

CLKOUT_PCIE_N6 CLKOUT_PCIE_P6

CLKOUT_PCIE_N7 CLKOUT_PCIE_P7

CLKOUT_PCIE_N8 CLKOUT_PCIE_P8

CLKOUT_PCIE_N9 CLKOUT_PCIE_P9

CLKOUT_PCIE_N10

CLKOUT_PCIE_P10

CLKOUT_PCIE_N11

CLKOUT_PCIE_P11

7 OF 13

CLKIN_XTAL

1 2

RH436 0_0201_5%

1 2

Rev1.0

Y3 Y4

B6 A6

AJ6 AJ7

AH9 AH10

AE14 AE15

AE6 AE7

AC2 AC3

AB2 AB3

W4 W3

W7 W6

AC14 AC15

U2 U3

AC9 AC11

AE9 AE11

R6

12

XTAL24_IN_R

RH153 1M_0402_1%

Remove RH437

PCH_XDP_CLK_DN_R PCH_XDP_CLK_DP_R

PCH_CPU_PCIBCLK_D# PCH_CPU_PCIBCLK_D

RH110 10K_0402_5%

1 2

XTAL24_OUT

1 2

RH154 0_0402_5%@

1 2

RH155 0_0402_5%@

1 2

RH168 0_0402_5%@

1 2

RH167 0_0402_5%@

CLK_PEG_N0 <27> CLK_PEG_P0 <27>

CLK_PCIE_N1 <70> CLK_PCIE_P1 <70>

CLK_PCIE_N2 <52> CLK_PCIE_P2 <52>

CLK_PCIE_N3 <51> CLK_PCIE_P3 <51>

CLK_PCIE_N4 <42> CLK_PCIE_P4 <42>

CLK_PCIE_N6 <52> CLK_PCIE_P6 <52>

CLK_PCIE_N7 <67> CLK_PCIE_P7 <67>

CLK_PCIE_N8 <67> CLK_PCIE_P8 <67>

CLK_PCIE_N9 <68> CLK_PCIE_P9 <68>

REFCLK_CNV <52>

XTAL downsize

YH2 24MHZ_12PF_8Y24000034

DGFF

Card reader

M.2 Slot2 WWAN

LAN

TBT

M.2 Slot1 WLAN

M.2 Slot3

M.2 Slot4

M.2 Slot5

M.2 Slot6

123

4

PCH_XDP_CLK_DN PCH_XDP_CLK_DP

PCH_CPU_PCIBCLK_R_D# PCH_CPU_PCIBCLK_R_D

PCH_XDP_CLK_DN <7> PCH_XDP_CLK_DP <7>

PCH_CPU_PCIBCLK_R_D# <7> PCH_CPU_PCIBCLK_R_D <7>

follow intel CFL-H PDG rev0.5, but CRB rev0.5

1

CH14

15P_0402_50V8J

2

CH13 change from 12P to 15P

1

CH13 15P_0402_50V8J

2

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2016/01/01

Compal Secret Data

Deciphered Date

2

2017/01/01

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

CNP-H(3/9) CLK

Size Document Number Rev

Custom

LA-H271P

Tuesday, April 09, 2019

Date: Sheet of

1

16 103

1.0

5

4

3

2

1

+3.3V_ALW_PC H

100K_0402_ 5%

RTC_DET#

TOUCH_SCR EEN_PD#

TOUCHPAD_INTR #

SIO_EXT_SMI#

RTD3_CIO_PW R_EN

3.3V_CAM_EN#

PCH_SPI_D2_XDP<7>

CFL-H PDG rev0.7 pop 20K for SPI0_IO2/3

CNL- PCH EDS rev0.5 Reserved External pull-up is required. Recommend 100K if pulled up to 3.3V

Change to 1K 3/29

RH180 1K_0402_5%XDP@

Change net location from EC to PCH GPP_D3

PCH_SPI_D0<7>

1 2

PCH_SPI_CS#2<65>

WWAN_FULL_PWR_ EN<52>

3.3V_CAM_EN#< 38>

RTC_DET#<8 4>

1

PME#

T178PAD~D @

1

T60PAD~D @

1

T61PAD~D @

1

T63PAD~D @

1

T62PAD~D @

PCH_SPI_D0 PCH_SPI_D1 PCH_SPI_CS#0 PCH_SPI_CLK PCH_SPI_CS#1

PCH_SPI_D2PCH_SPI_D2_XDP PCH_SPI_D3

Add WWAN_FULL_PWR_EN 3/6 Change net name 3/20

WWAN_FU LL_PWR_EN RTC_DET#

3.3V_CAM_EN#

Change net location from BE41 to BE18

PCH_SPI_D1_R1<65> PCH_SPI_D0_R1<65> PCH_SPI_CLK_R1<65>

PCH_PLTRS T#

BE36

R15 R13

AL37

AN35

AU41

BA45

AY47 AW47 AW48

AY48

BA46

AT40

BE19

BF19

BF18

BE18

BC17 BD17

PCH_SPI_D1_R1 PCH_SPI_D0_R1 PCH_SPI_CLK_R1 PCH_SPI_D3_R1

PCH_SPI_D1_R1 PCH_SPI_D1_1_R PCH_SPI_D0_R1 PCH_SPI_CLK_R1 PCH_SPI_D3_R1

1 2

RH310 10 K_0402_5%LPC@

1 2

RH730 10 K_0402_5%LPC@

FOLLOW X10 H Dell GPIO map

1 2

D D

+3.3V_RUN

C C

9/5 MOW Option 1: Implement a 1 kOhm pull-down resistor on the signal and de-populate the required 1 kOhm pull-up resistor. In this case, customers must ensure that the SPI flash device on the platform has HOLD functionality disabled by default.

Note that the pull down resistor on SPI0_IO3 is only needed for SKL U/Y platforms with ES and SKL S/H platforms with pre-ES1/ES1 samples.

RH736

1 2

RH734 10 K_0402_5%

for RTC_DET#

TOUCH_SCREEN_PD# don't move to RPC,

1 2

RH348 10K_ 0402_5%@

1 2

RH402 10K_ 0402_5%

+3.3V_SPI

GPP_H12

1 2

2.2K_0402_5 %@

RH615

eSPI Flash sharing mode (GPP_H12) 0 = Master Attached Flash Sharing (MAFS) enabled (Default) 1 = Slave Attached Flash Sharing (SAFS) enabled.

RH601

RH600

RH30 20K_0402_ 5%

RH335 20K_040 2_5%

RH334 1K_0402 _5%@

1 2

GPP_H15

100K_0402_ 5%

PCH_SPI_D0

100K_0402_ 5%

PCH_SPI_D2

PCH_SPI_D3

+3.3V_ALW_PC H

5

1

IN1

VCC

4

OUT

2

IN2

GND

3

UH7

MC74VHC1G08D FT2G_SC70-5

1 2 1 2 1 2 1 2

CNP-H

1 OF 13

UH1A

GPP_A11/PME#/SD_VDD2_PWR_EN#

RSVD2 RSVD1

VSS TP

SPI0_MOSI SPI0_MISO SPI0_CS0# SPI0_CLK SPI0_CS1#

SPI0_IO2 SPI0_IO3 SPI0_CS2#

GPP_D1/SPI1_CLK/SBK1_BK1 GPP_D0/SPI1_CS#/SBK0_BK0 GPP_D3/SPI1_MOSI/SBK3_BK3 GPP_D2/SPI1_MISO/SBK2_BK2 GPP_D22/SPI1_IO3 GPP_D21/SPI1_IO2

CNP-H_BGA874

RH722 33_0402_5 % RH723 33_0402_5 % RH724 33_0402_5 % RH725 33_0402_5 %

RH726 33_0402_5 %@ RH727 33_0402_5 %@ RH728 33_0402_5 %@ RH729 33_0402_5 %@

PCH_PLTRS T#_AND

12

RH65

@

GPP_B13/PLTRST#

GPP_K16/GSXCLK

GPP_K12/GSXDOUT

GPP_K13/GSXSLOAD

GPP_K14/GSXDIN

GPP_K15/GSXSRESET#

GPP_E3/CPU_GP0 GPP_E7/CPU_GP1 GPP_B3/CPU_GP2 GPP_B4/CPU_GP3

GPP_H18/SML4ALERT#

GPP_H17/SML4DATA

GPP_H16/SML4CLK

GPP_H15/SML3ALERT#

GPP_H14/SML3DATA

GPP_H13/SML3CLK

GPP_H12/SML2ALERT#

GPP_H11/SML2DATA

GPP_H10/SML2CLK

PCH_SPI_D1_0_R PCH_SPI_D0_0_R PCH_SPI_CLK_0_R PCH_SPI_D3_0_R

PCH_SPI_D0_1_R PCH_SPI_CLK_1_R PCH_SPI_D3_1_R

100K_0402_5%

INTRUDER#

Rev1.0

1 2

RH619 0_0402_5%@

1

CH350

2

ESD@

0.047U_0201_10V6K

AV29

Y47 Y46 Y48 W46 AA45

AL47 AM45 BF32 BC33

AE44 AJ46 AE43 AC47 AD48 AF47 AB47 AD47 AE48

BB44

1 2

RH622 0_0402_5%@

PCH_PLTRS T#

SIO_EXT_SMI# TOUCH_SCR EEN_PD# TOUCHPAD_INTR #

RTD3_CIO_PW R_EN

GPP_H15

GPP_H12

PCH_INTRUDE R_HDR#

FOLLOW X10 H Dell GPIO map

PCH_PLTRST#_R < 42,52,67,68>

PLTRST_T PM#

1

CH349

2

ESD@

0.047U_0201_10V6K

TOUCH_SCREEN_PD# < 38>

TOUCHPAD_INTR # <58,62>

TOUCH_SCREEN_DET# <38>

RTD3_CIO_PWR_EN <42 >

RH623

@

RH624 0_0201_5%@ RH625 0_0201_5%@ RH626 0_0201_5%@

+RTC_CEL L_PCH

1 2

12

RH198 1M_0402_5 %

12 12 12

0_0201_5%

PLTRST_TPM# <65> PLTRST_LAN# <51> PLTRST_GPU# <27> PLTRST_MMI# <70>

PCH Signal Glitch Free Implementation Requirements

PCH_PLTRS T#

PCH_SPI_CLK

RH641 100K_0201_5%@

RH640 100K_0201_5%@

1 2

RP change to single Resistor

256Mb Flash ROM

PCH_SPI_CS#0_R1

B B

ESPI LPC

RH37 0_0402_5%@

RH351

1 2

33_0402_5 %

PCH_SPI_CS#0_R2 PCH_SPI_D1_0_R PCH_SPI_D3_0_R PCH_SPI_D2_0_R

15 ohm33 ohmRH351

RPC1

RH178,RH179,RH181, RH182,RH183,RH184

A A

0 ohm

15 ohm33 ohm

25 ohm

PCH_SPI_CS#0_R1

PCH_SPI_CLK_0_RPCH_SPI_CLK_1_R

33_0402_5%

@EMI@

12

RH28

33P_0402_50V8J

@EMI@

12

CH321

33_0402_5%

@EMI@

12

RH29

33P_0402_50V8J

@EMI@

12

CH322

PCH_SPI_D2_R1

RH352 0_0402_5%@

RH353 33_0402_5 %@

1 2

PCH_SPI_CS#0_R3

PCH_SPI_D1_1_R PCH_SPI_D3_1_R

PCH_SPI_D2_1_R

UC5

1

CS#

2

DO

3

IO2

4

GND

ThemalPad

W25Q256J VEIQ_WSON8_8X6

reserve SO8 Flash ROM for colay

UC6

@

1

CS#

2

RESET#/SIO3

SO/SIO1

3

WP#/SIO2

4

GND

MX25L25645GM2 I-10G_SO8

VCC

SCLK

SI/SIO0

IO3

CLK

VCC

DI

+3.3V_SPI

8 7

PCH_SPI_CLK_0_RPCH_SPI_D2_R1

6

PCH_SPI_D0_0_R

5 9

+3.3V_SPI

8

7

PCH_SPI_CLK_1_R

6

PCH_SPI_D0_1_R

5

CH9

1 2

0.1U_0201_ 10V6K

CH270

@

1 2

0.1U_0201_ 10V6K

+3.3V_SPI

+3.3V_ALW_PC H

12

RH1850_0402_5%

RH1770_0201_5% @

RH1784.99_0402_1%

RH1794.99_0402_1%

RH1814.99_0402_1%

RH1820_0201_5% @

RH1834.99_0402_1%

RH1844.99_0402_1%

PCH_SPI_CS#1_ R1

PCH_SPI_CS#1

PCH_SPI_D0_R1

PCH_SPI_D0

PCH_SPI_D1_R1

PCH_SPI_D1

PCH_SPI_CLK_R 1

PCH_SPI_CLK

PCH_SPI_CS#0_ R1

PCH_SPI_CS#0

PCH_SPI_D2_R1

PCH_SPI_D2

PCH_SPI_D3_R1

PCH_SPI_D3

CONN@

JSPI1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

GND1

22

GND2

CVILU_CF5020FD0 R0-05-NH

CIS link OK

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2016/01/01

Compal Secret Data

Deciphered Date

2017/01/01

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

CNP-H(4/9) SPI,PLTRST

Size Document Number Rev

B

LA-H271P

Tuesday, April 09, 2019

Date: Sheet of

1

17 103

1.0

+3.3V_ALW_PC H

1 2

RH56 1K_0 402_5%

1 2

RH57 1K_0 402_5%

1 2

RH67 49 9_0402_1%

1 2

RH77 49 9_0402_1%

1 2

RH80 1K_ 0402_5%

1 2

RH81 1K_ 0402_5%

1 2

RH731 10 K_0402_5%

D D

correct status is 10K 3/29

+3.3V_ALW_PC H

1 2

RH61 4.7K _0402_5%

TLS CONFIDENTIALITY HIGH LOW(DEFAULT)

+3.3V_ALW_PC H

1 2

RH78 4.7K _0402_5%ESPI@

EC interface HIGH LOW(DEFAULT)

+3.3V_ALW_PC H

1 2

RH86 4.7K _0402_5%@

TOP SWAP STRAP HIGH LOW(DEFAULT)

C C

+3.3V_ALW_PCH

1 2

RC74 10K_0402_5%

Add pull down 75K

If USB 3.0 Port 1 is used for 4-wire DCI.OOB (BSSB), and alternate functionality is also used on the pin, pull up to V3.3S with >100K resistor to avoid noise.

B B

If USB 3.0 Port 1 is used for DCI.OOB (BSSB) 4-wire BSSB, and NO alternate functionalityis used, leave float.

If DCI.OOB (BSSB) 2+2 functionality is used, pull up to V3.3S with a 4.7K resistor.

1 2

CH41 1U_0 201_6.3V6M

1 2

CH40 1U_0 201_6.3V6M

PCH_RTCRST#<19,58>

1

CMOS1 SHORT PADS~D@

RH215

NO Support Deep sleep

POP

Support Deep sleep

DE-POP

1 2

RH215 0_0402_ 5%

@NDS3@

100K_0402_5%

0.01U_0402_16V7K

12

1

A A

@

RH308

CH266

2

5

MEM_SMBCLK

MEM_SMBDATA

SML0_SMBCLK

SML0_SMBDATA

SML1_SMBCLK

SML1_SMBDATA

TBT_RTD 3_WAKE#_R

PCH_SMB_ALERT #

ENABLE DISABLE

GPP_C5

ESPI LPC

SPKR

ENABLE DISABLE

KB_DET#

12

RH61775K_0402_5 %

12

RH73375K_0402_5 %

GPP_B23

WEAK INTERNAL PD ~20K

Intel DCI-OOB

HIGH LOW(DEFAULT)

2

PCH_RSMRST #_ANDPCH_DPW ROK

5

CNV_RF_RESET#

CLKREQ_CNV

+3.3V_ALW_PCH

ENABLED DIABLED

SRTCRST#

PCH_RTCR ST#

10K_0402_5%

12

RC75

JUSB1

WWAN

JUSB2

1 2

RF@

HDA_BIT_CLK_R<56>

HDA_SDIN0<56>

HDA_SDOUT_R<56>

HDA_SYNC_R<56> HDA_RST#_R<56>

AUD_AZACPU_SDO<9 > AUD_AZACPU_SDI_R<9> AUD_AZACPU_SCLK<9>

RH329 150K_0402_ 5%

1 2

HDA_SDIN0 HDA_SYNC HDA_SDOUT

@

2P_0402_50V8C

12

CA73

place close to UH1 place close to UH1 place close to UH1 place close to UH1

Service Mode Switch: Add a switch to ME_FWP signal to unlock the ME region and allow the entire region of the SPI flash to be updated using FPT.

12

de-pop for MP 3/6

RH101

@

1K_0402_5%

pop for MP 3/6

ME_FWP

ME_FWP<58>

+3.3V_ALW_PCH

ME_FWP PCH has internal 20K PD. (suspend power rail)

FLASH DESCRIPTOR SECURITY OVERRIDE

LOW = ENABLE (DEFAULT) -->Pin1 & Pin3 short HIGH = DISABLE (ME can update) -->Pin2 & Pin3 short

CH268 47P_0 402_50V8J

ME_FWP_PC H

+RTC_CEL L_PCH

@

2P_0402_50V8C

12

CA74

ME_FWP_PCH

1 2

RH100 0_04 02_5%@

PT,ST pop RH101 and SW1; MP pop RH100

ME_FWP_PCH

4

USB3_PTX_DR X_N1<71> USB3_PTX_DR X_P1<71> USB3_PRX_DT X_N1<71> USB3_PRX_DT X_P1<71>

USB3_PTX_DR X_N2<52> USB3_PTX_DR X_P2<52> USB3_PRX_DT X_N2<52> USB3_PRX_DT X_P2<52>

USB3_PTX_DR X_P3<71> USB3_PTX_DR X_N3<71> USB3_PRX_DT X_P3<71> USB3_PRX_DT X_N3<71>

RH46 33_0402_5%EMI@

RH45 33_0402_5% RH328 1K_0402_5% RH48 33_0402_5% RH50 33_0402_5%

RH39 30 _0402_5%

RH38 30 _0402_5%

CLKREQ_CNV<52>

CNV_RF_RESET#<52>

RH200 20 K_0402_5% RH201 20 K_0402_5%

SW1

@

1

A

2

B

3

C

4

G1

5

G2

SS3-CMFTQR9_ 3P

4

1 2

1 2 1 2 1 2 1 2

1 2

T269

IR_CAM_DET#<38 > DGPU_PWR OK<27,58>

KB_DET#<62>

1 2 1 2

PCH_PWR OK<90> PCH_RSMRST #_AND<7,62>

PCH_DPW ROK<58>

SML0_SMBCLK<42,51> SML0_SMBDATA<42,51>

SML1_SMBCLK<58> SML1_SMBDATA<58>

@

PAD~D

USB3_PTX_DR X_P3 USB3_PTX_DR X_N3 USB3_PRX_DT X_P3 USB3_PRX_DT X_N3

1 2

RH637 100K_02 01_5%@

1 2

RH636 100K_02 01_5%@

CLKREQ_CNV

CNV_RF_RESET#

1

PCH_DPW ROK PCH_SMB_ALERT # MEM_SMBCLK MEM_SMBDATA GPP_C5 SML0_SMBCLK SML0_SMBDATA GPP_B23 SML1_SMBCLK SML1_SMBDATA

@

2P_0402_50V8C

12

CA76

HDA_BIT_CLK HDA_SDIN0 HDA_SDOUT

HDA_SYNC HDA_RST#

AUD_AZACPU_SDO_RAUD_AZACPU_SDO

AUD_AZACPU_SCLK_RAUD_AZACPU_SCLK

TBT_PW R_EN IR_CAM_DET#

KB_DET#

PCH_RTCR ST# SRTCRST#

PCH_PWR OK PCH_RSMRST #_AND

MEM_SMBCLK

MEM_SMBDATA

UH1F

F9

USB31_1_TXN

F7

USB31_1_TXP

D11

USB31_1_RXN

C11

USB31_1_RXP

C3

USB31_2_TXN

D4

USB31_2_TXP

B9

USB31_2_RXN

C9

USB31_2_RXP

C17

USB31_6_TXN

C16 G14

F14 C15 B15

J13 K13

G12

F11 C10 B10

C14 B14

J15 K16

CNP-H_BGA874

BD11

BE11 BF12

BG13

BE10 BF10 BE12

BD12

AM2 AN3 AM3

AV18

AW18

BA17 BE16 BF15

BD16

AV16

AW15

BE47

BD46

AY42 BA47

AW41

BE25 BE26 BF26 BF24 BF25 BE24

BD33

BF27 BE27

+3.3V_RUN

QH4B L2N7002DW 1T1G_SC88-6

GPP_A14/SUS_STAT#/ESPI_RESET# USB31_6_TXP USB31_6_RXN USB31_6_RXP USB31_5_TXN USB31_5_TXP USB31_5_RXN USB31_5_RXP

USB31_3_TXP USB31_3_TXN USB31_3_RXP USB31_3_RXN

USB31_4_TXP USB31_4_TXN USB31_4_RXP USB31_4_RXN

UH1D

HDA_BCLK/I2S0_SCLK HDA_SDI0/I2S0_RXD HDA_SDO/I2S0_TXD HDA_SYNC/I2S0_SFRM

HDA_RST#/I2S1_SCLK HDA_SDI1/I2S1_RXD I2S1_TXD/SNDW2_DATA I2S1_SFRM/SNDW2_CLK

HDACPU_SDO HDACPU_SDI HDACPU_SCLK

GPP_D8/I2S2_SCLK GPP_D7/I2S2_RXD GPP_D6/I2S2_TXD/MODEM_CLKREQ GPP_D5/I2S2_SFRM/CNV_RF_RESET# GPP_D20/DMIC_DATA0/SNDW4_DATA GPP_D19/DMIC_CLK0/SNDW4_CLK GPP_D18/DMIC_DATA1/SNDW3_DATA GPP_D17/DMIC_CLK1/SNDW3_CLK

RTCRST# SRTCRST#

PCH_PWROK RSMRST#

DSW_PWROK GPP_C2/SMBALERT# GPP_C0/SMBCLK GPP_C1/SMBDATA GPP_C5/SML0ALERT# GPP_C3/SML0CLK GPP_C4/SML0DATA GPP_B23/SML1ALERT#/PCHHOT# GPP_C6/SML1CLK GPP_C7/SML1DATA

CNP-H_BGA874

VCCDSW_EN_GPIO<20 >

VCCDSW_EN<58>

ALW_PWR GD_3V_5V<43,62,8 6>

2

5

QH4A L2N7002DW 1T1G_SC88-6

43

3

For DATA lines: microstrip routing, R1 = 15 Ohm. Otherwise, R1 = 0 Ohm For Clock line: R1 = 33 Ohm

CNP-H

GPP_A1/LAD0/ESPI_IO0 GPP_A2/LAD1/ESPI_IO1 GPP_A3/LAD2/ESPI_IO2 GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS0#

GPP_A6/SERIRQ/ESPI_CS1#

GPP_A7/PIRQA#/ESPI_ALERT0#

GPP_A0/RCIN#/ESPI_ALERT1#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

GPP_A10/CLKOUT_LPC1

GPP_K19/SMI# GPP_K18/NMI#

GPP_E6/SATA_DEVSLP2 GPP_E5/SATA_DEVSLP1 GPP_E4/SATA_DEVSLP0

GPP_F9/SATA_DEVSLP7 GPP_F8/SATA_DEVSLP6 GPP_F7/SATA_DEVSLP5 GPP_F6/SATA_DEVSLP4 GPP_F5/SATA_DEVSLP3

6 OF 13

GPP_A12/BM_BUSY#/ISH_GP6/SX_EXIT_HOLDOFF#

16

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

Rev1.0

CNP-H

GPP_B1/GSPI1_CS1#/TIME_SYNC1

GPP_A13/SUSWARN#/SUSPW RDNACK

4 OF 13

1 2

RH445 0_0402_ 5%@

DDR_XDP_W AN_SMBCLK <7,23 ,24,25,26,54>

DDR_XDP_W AN_SMBDAT <7,23,24,2 5,26,54>

Issued Date

571391_CFL_H_PDG_Rev1p8 Table 26-2. 9/5

ESPI_IO0_R

BB39

ESPI_IO1_R

AW37

ESPI_IO2_R

AV37

ESPI_IO3_R

BA38

BE38

ESPI_ALERT#

AW35 BA36

SIO_RCIN#

BE39

ESPI_RESET#

BF38

ESPI_CLK

BB36

PCI_CLK_LPC1

BB34

T48

TBT_RTD 3_WAKE#_R

T47

AH40 AH35 AL48 AP47 AN37 AN46 AR47 AP48

BF36

SYS_PWROK

WAKE#

GPD6/SLP_A#

SLP_LAN#

SLP_SUS#

SYS_RESET#

CPUPWRGD

ITP_PMODE PCH_JTAGX

DH1

DH2

2016/01/01

Rev1.0

21

AV32

BF41

BD42

BB46 BE32 BF33 BE29 R47 AP29 AU3

BB47 BE40 BF40 BC28 BF42 BE42 BC42

BE45 BF44 BE35 BC37

BG44 BG42 BD39 BE46 AU2 AW29 AE3

AL3 AH4 AJ4 AH3 AH2 AJ3

SIO_SLP_SUS#

VCCDSW_EN _Q

GPP_A8/CLKRUN#

GPD11/LANPHYPC

GPD9/SLP_WLAN#

DRAM_RESET#

GPP_B2/VRALERT#

GPP_B0/GSPI0_CS1#

GPP_K17/ADR_COMPLETE

GPP_B11/I2S_MCLK

GPP_B12/SLP_S0#

GPD4/SLP_S3# GPD5/SLP_S4#

GPD10/SLP_S5#

GPD8/SUSCLK

GPD0/BATLOW#

GPP_A15/SUSACK#

GPD2/LAN_WAKE#

GPD1/ACPRESENT

GPD3/PWRBTN#

GPP_B14/SPKR

PCH_JTAG_TMS PCH_JTAG_TDO

PCH_JTAG_TDI

PCH_JTAG_TCK

NDS3@

2 1

RB751S-40_S OD523-2

NDS3@

RB751S-40_S OD523-2

For DS3: Pop RE349, RE536, RH439, RH441, RH443 Depop DH1, RH215, RH440, RH442

For NDS3 : Pop DH1, RH215, RH440, RH442 Depop RE349, RE536, RH439, RH441, RH443

RC366 15_0402_5% RC367 15_0402_5% RC368 15_0402_5% RC369 15_0402_5%

RH97 33_0402_5%EMI@ RH99 22_0402_5%@

RH732 0_04 02_5%@

FOLLOW X10 H Dell GPIO map

SLOT3_DEVSLP <67>

SLOT4_DEVSLP <67>

CLKRUN#

VRALERT#

SYS_PWROK

PCH_PCIE_W AKE# SIO_SLP_A# SIO_SLP_LAN#

SUSCLK PCH_BATLOW # SUSACK#_R ME_SUS_PW R_ACK_R

LAN_WAKE# AC_PRESENT

SYS_RESET# SPKR

PCH_JTAGX PCH_JTAG_TMS PCH_JTAG_TD O PCH_JTAG_TD I PCH_JTAG_TC K

Compal Secret Data

2

1 2 1 2 1 2 1 2

1 2 1 2

CHECK,LPC_CLK FOR DEBUG CARD?

1 2

@

RH443

RH441 0_0402_5%

1 2

DS3@

1 2

RH442 0_0402_5%

@NDS3@

Deciphered Date

2

ESPI_IO0 <58,59> ESPI_IO1 <58,59> ESPI_IO2 <58,59> ESPI_IO3 <58,59>

ESPI_CS# <58,59> ESPI_ALERT# <58>

ESPI_RESET# <58,59>

ESPI_CLK_5105 <58,59>

TBT_RTD3_WAKE# <15,42>

PM_LANPHY_ENABLE <51>

SIO_SLP_WLAN# <5 4,58>

DDR4_DRAMR ST#_PCH <23>

MACO_EN <27>

SYS_PWROK <7,58 >

PCH_PCIE_W AKE# <42,58,59> SIO_SLP_A# <19,58> SIO_SLP_LAN# <54,58> SIO_SLP_S0# <14,19,65> SIO_SLP_S3# <19,42,59> SIO_SLP_S4# <11,19,88> SIO_SLP_S5# <19>

SUSCLK < 52,67,68>

1 2

1

PAD~D

CFL-H CRB rev0.5

LAN_WAKE# <51,58> AC_PRESENT <58> SIO_SLP_SUS# <58> SIO_PWRBTN# <7,58> SYS_RESET# <15,19> SPKR <56> H_PWRGD <7>

ITP_PMODE_CPU <7> PCH_JTAGX <7> PCH_JTAG_TMS <7> PCH_JTAG_TD O <7> PCH_JTAG_TD I <7> PCH_JTAG_TC K <7>

2017/01/01

0_0402_5%

@

T319

PCH_PRIM_EN <11,22,89>

SIO_SLP_S3#

CH341 0.033U _0402_16V7@

SIO_SLP_S4#

CH342 0.033U _0402_16V7@

SIO_SLP_A#

CH343 0.033U _0402_16V7@

SIO_SLP_WLAN#

CH344 0.033U _0402_16V7@

SIO_SLP_SUS#

CH345 0.033U _0402_16V7@

SIO_SLP_LAN#

CH346 0.033U _0402_16V7@

SIO_SLP_S5#

CH347 0.033U _0402_16V7@

ESPI_RESET#

CH348 0.033U _0402_16V7@

1

ESPI_RESET#

ESPI_ALERT#

SUSACK#_R

1 2

RH95 10K_0402_ 5%@

1 2

RH340 8.2K_040 2_1%

1 2

RH327 1K_0402 _5%@

SYS_RESET#

ESD Request:place near PCH side

RF Request

SML0_SMBCLK

SML1_SMBCLK

MEM_SMBCLK

VRALERT#

SIO_SLP_LAN#

PCH_PCIE_W AKE#

LAN_WAKE#

SUSACK# <58>

PCH Signal Glitch Free Implementation Requirements

1 2

PCH_BATLOW #

AC_PRESENT

SIO_RCIN#

CLKRUN#

SYS_PWROK

IR_CAM_DET#

PCH_JTAG_TC K

PCH_PWR OK

SUSCLK

PCH_JTAG_TMS

PCH_JTAG_TDI

PCH_JTAG_TDO

DDR_XDP_WAN_SMBDAT

DDR_XDP_WAN_SMBCLK

SIO_SLP_S3#

SIO_SLP_S4#

SIO_SLP_A#

SIO_SLP_WLAN#

SIO_SLP_SUS#

SIO_SLP_LAN#

SIO_SLP_S5#

ESPI_RESET#

1 2

CC318@RF@ 33P_04 02_50V8J

1 2

CC319@RF@ 33P_04 02_50V8J

1 2

CC320@RF@ 33P_04 02_50V8J

Place close PCH side

1 2

RH203 10K_040 2_5%@

1 2

RH204 10K_040 2_5%@

1 2

RH92 1K_0201_5 %

1 2

RH93 10K_ 0201_5%

1 2

RH94 8.2K_0402_5 %

1 2

RH243 10K_040 2_5%

1

PAD~D

1

PAD~D

1 2

RH199 100K_04 02_5%

1 2

RH373 100K_04 02_5%

1 2

RH313 51_0402 _5%@

1 2

RH424 10K_040 2_5%@

1 2

RH83 1K_0402_5 %@

1 2

RH312 51_04 02_5%

1 2

RH314 51_04 02_5%

1 2

RH315 51_04 02_5%

1 2

RH374 2.2K_ 0402_5%

1 2

RH333 2.2K_ 0402_5%

1 2

RH634 100K_ 0201_5%@

1 2

RH635 100K_ 0201_5%@

1 2

RH638 100K_ 0201_5%@

1 2

RH629 100K_ 0201_5%@

1 2

RH639 100K_ 0201_5%@

1 2

RH631 100K_ 0201_5%@

1 2

RH632 100K_ 0201_5%@

1 2

RH633 75K_0201_5%@

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

CNP-H(5/9) USB,HDA,SMB

Size Document Number Rev

B

LA-H271P

Tuesday, April 09, 2019

Date: Sheet of

1

18 103

+3.3V_1.8V_GPPA

@ESD@

0.1U_0201_25V6K

12

CC302

+3.3V_ALW_PCH

+3.3V_DSW

+3.3V_RUN

@

T317

@

T318

+1.0V_VCCSTG

+3.3V_RUN

1.0

5

+3.3V_RUN

1 2

RH378 10K_0 402_5%

1 2

RH375 100K_ 0402_5%@

1 2

RH360 49.9K_0 402_1%@

1 2

D D

RH361 49.9K_0 402_1%@

1 2

RH355 10K_0 402_1%

1 2

RH339 10K_0 402_5%

1 2

RH331 4.7K_04 02_5%@

PCH STRAPS IF SAMPLED HIGH[ NO REBOOT ]

+3.3V_ALW_PCH

1 2

RH309 10K_0 402_5%

1 2

RH330 49.9K_0 402_1%

1 2

RH376 49.9K_0 402_1%

1 2

RH1 100K_0402_5%

FFS_INT2

PCH_3.3V_TS_ EN

UART2_TXD

UART2_RXD

HDD_FALL_INT

SIO_EXT_SCI#

NRB_BIT

SIO_EXT_WAKE#

UART2_TXD

UART2_RXD

CPU_EDP_HP D

PCH_3.3V_TS_ EN<38>

RC561 0_0402_5%@

TPM_PIRQ#< 65>

8/20

RC560 0_ 0402_5%

MEDIACARD_IRQ#<70>

SBIOS_TX<59>

LCD_CBL_D ET#<38>

SIO_EXT_WAKE#<5 8>

UART2_TXD<44>

UART2_RXD<44 >

I2C1_SCK_TP<6 2> I2C1_SDA_TP<6 2>

T307 T306

TBT_FORCE_ PWR<42>

FFS_INT2<54>

4

BBS_BIT6

NRB_BIT

TPM_PIRQ#_R

TBT_ID

TYPEC_CON_SEL 2 TYPEC_CON_SEL 1

Align BH 1/221

LCD_CBL_D ET#

SIO_EXT_WAKE#

UART2_TXD UART2_RXD

1 1

FFS_INT2

SIO_EXT_SCI# HDD_FALL_INT

12

HDD_FALL_INT<54>

12

@

PAD~D

@

PAD~D

UH1K

BA26

GPP_B22/GSPI1_MOSI

BD30

GPP_B21/GSPI1_MISO

AU26

GPP_B20/GSPI1_CLK

AW26

GPP_B19/GSPI1_CS0#

BE30

GPP_B18/GSPI0_MOSI

BD29

GPP_B17/GSPI0_MISO

BF29

GPP_B16/GSPI0_CLK

BB26

GPP_B15/GSPI0_CS0#

BB24

GPP_C9/UART0A_TXD

BE23

GPP_C8/UART0A_RXD

AP24

GPP_C11/UART0A_CTS#

BA24

GPP_C10/UART0A_RTS#

BD21

GPP_C15/UART1_CTS#/ISH_UART1_CTS#

AW24

GPP_C14/UART1_RTS#/ISH_UART1_RTS#

AP21

GPP_C13/UART1_TXD/ISH_UART1_TXD

AU24

GPP_C12/UART1_RXD/ISH_UART1_RXD

AV21

GPP_C23/UART2_CTS#

AW21

GPP_C22/UART2_RTS#

BE20

GPP_C21/UART2_TXD

BD20

GPP_C20/UART2_RXD

BE21

GPP_C19/I2C1_SCL

BF21

GPP_C18/I2C1_SDA

BC22

GPP_C17/I2C0_SCL

BF23

GPP_C16/I2C0_SDA

BE15

GPP_D4/ISH_I2C2_SDA/I2C3_SDA/SBK4_BK4

BE14

GPP_D23/ISH_I2C2_SCL/I2C3_SCL

CNP-H_BGA874

GPP_D11/ISH_SPI_MISO/GP_BSSB_CLK/GSPI2_MISO

GPP_D12/ISH_SPI_MOSI/GP_BSSB_DI/GSPI2_MOSI

GPP_D15/ISH_UART0_RTS#/GSPI2_CS1#/CNV_WFEN

3

CNP-H

GPP_D9/ISH_SPI_CS#/GSPI2_CS0# GPP_D10/ISH_SPI_CLK/GSPI2_CLK

GPP_D16/ISH_UART0_CTS#/CNV_WCEN

GPP_D14/ISH_UART0_TXD/I2C2_SCL

GPP_D13/ISH_UART0_RXD/I2C2_SDA

GPP_H20/ISH_I2C0_SCL GPP_H19/ISH_I2C0_SDA

GPP_H22/ISH_I2C1_SCL GPP_H21/ISH_I2C1_SDA

GPP_A23/ISH_GP5 GPP_A22/ISH_GP4 GPP_A21/ISH_GP3 GPP_A20/ISH_GP2 GPP_A19/ISH_GP1

GPP_A17/SD_VDD1_PWR_EN#/ISH_GP7

11 OF 13

GPP_A18/ISH_GP0

Rev1.0

BA20 BB20 BB16 AN18

BF14 AR18 BF17 BE17

AG45 AH46

AH47 AH48

AV34 AW32 BA33 BE34 BD34 BF35 BD38

MEM_INTERLEAVED DGPU_HOLD_R ST# AR_DET# GPP_D12

LID_CL#_PCH TPM_TYPE

CLKDET#

2

DGPU_HOLD_R ST# <27>

ISH_UART0_CTS # <5 2> ISH_UART0_RTS# <52> ISH_UART0_TXD <52> ISH_UART0_RXD <52>

1

PAD~D

1

PAD~D

1

+3.3V_RUN

LCD_CBL_D ET#

PCH_DPB_CT RL_CLK PCH_DPB_CT RL_DATA PCH_DPC_C TRL_CLK PCH_DPC_C TRL_DATA PCH_DPD_C TRL_CLK PCH_DPD_C TRL_DATA

DGPU_HOLD_R ST#

@

T268

@

T258

Reserved

GPP_D12

TPM_TYPE

1 2

RC370 10K_0201_5%

1 2

RH628 2.2K_0402_5%

1 2

RH221 2.2K_0402_5%

1 2

RH222 2.2K_0402_5%

1 2

RH223 2.2K_0402_5%

1 2

RH224 2.2K_0402_5%

1 2

RH225 2.2K_0402_5%

Change to pop 4/1

1 2

RH350 100K_0402_5 %@

1 2

RH349 100K_0402_5 %@

1 2

RH379 100_0402_1%@

C C

B B

A A

+3.3V_ALW_PC H

12

RH311

@

8.2K_0402_5 %

BBS_BIT6

BOOT BIOS Destination(Bit 6)

HIGH LOW(DEFAULT)

LPC SPI

TBT_ID

HIGH LOW

+3.3V_RUN

1 2

12

10K_0402_5%

RH267@

RH268

TBT_ID

Alpine Redge Titan Redge

PCH_DPB_HP D<31> PCH_DPC_H PD<3 0> PCH_DPD_H PD<2 8>

1 2

RH630 100K_0402_ 5%@

CPU_EDP_HP D<29>

MEM_INTERLEAVED

CPU_EDP_HP D

1 2

12

RH371 10K_0402_5 %

@

RH372 10K_0402_5 %

UH1E

AT6

GPP_I0/DDPB_HPD0/DISP_MISC0

AN10

GPP_I1/DDPC_HPD1/DISP_MISC1

AP9

GPP_I2/DDPD_HPD2/DISP_MISC2

AL15

GPP_I3/DDPF_HPD3/DISP_MISC3

AN6

GPP_I4/EDP_HPD/DISP_MISC4

CNP-H_BGA874

DIMM TYPE

HIGH Interleave

Non-InterleaveLOW

CNP-H

GPP_I6/DDPB_CTRLDATA

GPP_I8/DDPC_CTRLDATA

GPP_I10/DDPD_CTRLDATA

GPP_F23/DDPF_CTRLDATA

GPP_F22/DDPF_CTRLCLK

5 OF 13

AR_DET#

GPP_I5/DDPB_CTRLCLK

GPP_I7/DDPC_CTRLCLK

GPP_I9/DDPD_CTRLCLK

GPP_F14/PS_ON#

GPP_K23/IMGCLKOUT1 GPP_K22/IMGCLKOUT0

GPP_K21 GPP_K20

GPP_H23/TIME_SYNC0

+3.3V_ALW_PCH+3.3V_ALW_PCH

Rev1.0

1 2

12

AL13 AR8 AN13 AL10 AL9 AR3 AN40 AT49

AP41

M45 L48 T45 T46 AJ47

RH400

@

10K_0402_5 %

RH401

10K_0402_5 %

PCH_DPB_CT RL_CLK PCH_DPB_CT RL_DATA PCH_DPC_C TRL_CLK PCH_DPC_C TRL_DATA PCH_DPD_C TRL_CLK PCH_DPD_C TRL_DATA

GPP_F22

RC444 10K_0402_5 %@

AR_DET#

1 2

NON TBTHIGH

TBTLOW

PCH_DPC_C TRL_CLK <1 9,30>

PCH_DPC_C TRL_DATA <19,30 >

+3.3V_RUN

1 2

12

CRB RV0.7

Align BH 1/221

Vendor FOXCON TBD TBD

TYPEC_CON_SEL2

Check ME about wire to board PN

+3.3V_ALW_PC H

SIO_SLP_S3#<18,42,59>

+3.3V_ALW

SIO_SLP_S5#<18> SIO_SLP_S4#<11,18,88> SIO_SLP_A#<18,58>

+3.3V_ALW

PCH_RTCR ST#< 18,58>

POWER_SW #_MB<59,7 7>

SYS_RESET#<15,18>

SIO_SLP_S0#<14,18,65>

Intel Management Engine Test Suite

RH555

@

10K_0402_5 %

TYPEC_CON_SEL 2TYPEC_CON_SEL 1

RH556

@

10K_0402_5 %

JAE

LOWTYPEC_CON_SEL1

LOW

+3.3V_ALW_PCH+3.3V_ALW_PCH

RH553

@

10K_0402_5 %

1 2

12

RH554

@

10K_0402_5 %

LOW

HIGH

LOWHIGH

JAPS1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

GND_1

20

GND_2

CONN@

ACES_50506-01 841-P01

HIGH

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2016/01/01

Compal Secret Data

Deciphered Date

2017/01/01

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

CNP-H(5/9) USB,HDA,SMB

Size Document Number Rev

Custom

LA-H271P

Tuesday, April 09, 2019

Date: Sheet of

1

19 103

1.0

5

1 2

@ESPI@

RH294 0_040 2_5%

RH296 0_0402_5%@

1 2

RH250 0_0402_5%@

RH295 0_040 2_5%@

+1.8V_PRIM

+1.8V_ALW_PC HRES

+1.0V_ALW_PC H+1.05V_PRIM

1 2

RH254 0_ 1206_5%@

+1.0V_ALW_PC H

0.0454A

@

RH255 0_ 0402_5%@

RH256

RH257

RH258

RH259

RH286

RH287

RH288

RH290

RH260

RH240

1 2

JUMP@

PJP3

2

JUMP_43X79

1 2

112

0.0012A

0_0402_5%

0.0085A

0_0402_5%

D D

C C

B B

+3.3V_ALW_PC HRES

+1.0V_DSW

+1.0V_PRIM_FUSE

+1.0V_PRIM_CNV_HVLO

0.2A

+1.0V_SRC

0.169A

+1.0V_BCLKPLL 2

0.021A

+1.0V_DUSB

0.42A

+2.8V_FHV0

0.0859A

+2.8V_FHV1

0.193A

+1.0V_MPHY

6.66A

+1.0V_CLPLLEB B

0.109A

+1.0V_OC

+1.0V_OCPLL1

0.0198A

RH279 0_ 1206_5%@

RH291 0_0402_5%

LPC@

@

RH304

@

RH293

@

RH303

@

RH305

@

RH306

@

RH246

@

RH292

@

RH300

@

RH299

RH298 0_ 0603_5%@

@

RH302

571182-cnl-pch-h-eds-rev2p2 P65 Table 10-6.

+3.3V_ALW_PC HRES+3.3V_ALW_P CH +RTC_CEL L_PCH

1 2

eSPI Power

+3.3V_1.8V_GPPA

0.101A

1 2

+3.3V_PGPPBC

0.343A

1 2

0_0402_5%

+3.3V_1.8V_GPPD

0.14A

1 2

0_0402_5%

+3.3V_PGPPEF

0.174A

1 2

0_0402_5%

+3.3V_PGPPG

0.145A

1 2

0_0402_5%

+3.3V_PGPPHK

0.262A

1 2

0_0402_5%

+3.3V_1.8V_SPI

0.05A

1 2

0_0402_5%

+3.3V_1.8V_AZIO

0.00767A

1 2

0_0402_5%

+3.3V_FUSE

0.106A

1 2

0_0402_5%

+3.3V_PHVC

0.182A

1 2

0_0402_5%

+3.3V_PHVLDO

0.97A

1 2

+3.3V_PUSB2

0.536A

1 2

0_0402_5%

RF Request

+3.3V_1.8V_AZIO_R +1.0V_CLPLLEBB

1

2

CC327

RF@

1

2

CC328

2.2P_0402_50V8C

RF@

2.2P_0402_50V8C

1 2

RH247 0_06 03_5%@

+1.8V_ALW_PC HRES

12

+3.3V_DSW

4

+1.8V_ALW_PC HRES

0.113A

@NDS3@

RH440

DS3@

+3.3V_ALW_DS W_R

1 2

RH439 0_040 2_5%

1 2

+1.8V_PRIM

+1.8V_PHVLDO

+1.24V_DPHY

0_0402_5%

12

1 2

@

RH297

1 2

RH242 0_ 0603_5%@

0.882A

1 2

RH239 0_0603_ 5%@

1 2

@

RH237

+1.0V_OCPLL1

+1.0V_BCLKPLL 2

+3.3V_ALW_PC H

+3.3V_ALW

Material shortage SB00000QP00 change to SB00000T900 1/15

QH7

DS3@

PJ2301_SOT2 3-3

1 3

S

D

0.1U_0201_25V6K

@

CH340

DS3@

L2N7002WT1G_SC-70-3

QH6

G

2

DS3@

49.9K_0402_1%

12

RH433

13

D

2

G

S

Change to DS3 4/1

499K_0402_1%

12

+3.3V_PRTC

0.000416A

0_0402_5%

+1.8V_PRIM_PCH

+1.24V_LDOSRAM

0_0402_5%

1

2

@

1

2

@

DS3@

RH432

100K_0402_5%

1 2

BLM15GA750SN1 D_2P

CC332

BLM15GA750SN1 D_2P

CC330

RH431

3

1 2

LC3

0.1U_0201_10V6K

1 2

LC2

0.1U_0201_10V6K

VCCDSW_EN_GPIO <18 >

1

CC331

2

1

CC311

2

571182-cnl-pch-h-eds-rev2p2 P65 Table 10-6.

+1.0V_PRIM_CNV_HVLO

+1.0V_OCPLL1_ R

0.1U_0201_10V6K

+1.0V_BCLKPLL 2_R

0.1U_0201_10V6K

+1.05V_PRIM

+1.0V_MPHY

+1.0V_PRIM_FUSE

+1.0V_DUSB

+1.0V_DSW

+1.0V_CLPLLEB B

+1.0V_AZPLL

+1.0V_AMPHYPLL

+1.0V_XTAL

+1.0V_SRC

+1.0V_OCPLL1_ R

+1.0V_OC

8.21A

UH1H

AA22

VCCPRIM_1P051

AA23

VCCPRIM_1P052

AB20

VCCPRIM_1P053

AB22

VCCPRIM_1P054

AB23

VCCPRIM_1P055

AB27

VCCPRIM_1P056

AB28

VCCPRIM_1P057

AB30

VCCPRIM_1P058

AD20

VCCPRIM_1P059

AD23

VCCPRIM_1P0510

AD27

VCCPRIM_1P0511

AD28

VCCPRIM_1P0512

AD30

VCCPRIM_1P0513

AF23

VCCPRIM_1P0516

AF27

VCCPRIM_1P0517

AF30

VCCPRIM_1P0518

U26

VCCPRIM_1P0523

U29

VCCPRIM_1P0524

V25

VCCPRIM_1P0525

V27

VCCPRIM_1P0526

V28

VCCPRIM_1P0527

V30

VCCPRIM_1P0528

V31

VCCPRIM_1P0529

AD31

VCCPRIM_1P0514

AE17

VCCPRIM_1P0515

W22

VCCDUSB_1P051

W23

VCCDUSB_1P052

BG45

VCCDSW_1P051

BG46

VCCDSW_1P052

W31

VCCPRIM_MPHY_1P05

D1

VCCPRIM_1P0521

E1

VCCPRIM_1P0522

C49

VCCAMPHYPLL_1P051

D49

VCCAMPHYPLL_1P052

E49

VCCAMPHYPLL_1P053

P2

VCCA_XTAL_1P051

P3

VCCA_XTAL_1P052

W19

VCCA_SRC_1P051

W20

VCCA_SRC_1P052

C1

VCCAPLL_1P054

C2

VCCAPLL_1P055

V19

VCCA_BCLK_1P05

B1

VCCAPLL_1P051

B2

VCCAPLL_1P052

B3

VCCAPLL_1P053

CNP-H_BGA874

CNP-H

UH1J

RSVD7 RSVD8 RSVD6 RSVD5

RSVD3 RSVD4

RSVD2 RSVD1

PREQ# PRDY#

CPU_TRST#

TRIGGER_OUT

TRIGGER_IN

10 OF 13

CNP-H_BGA874

RH42 30 _0402_5%

Y14 Y15 U37 U35

N32 R32

AH15 AH14

AL2 AM5 AM4 AK3 AK2

Rev1.0

1 2

2

CNP-H

VCCPRIM_3P32

VCCPRIM_3P35

VCCPGPPG_3P3

VCCPRIM_3P33 VCCPRIM_3P34

VCCPGPPHK1 VCCPGPPHK2

VCCPGPPEF1 VCCPGPPEF2

VCCPGPPD VCCPGPPBC1 VCCPGPPBC2

VCCPGPPA

VCCPRIM_3P31 VCCDSW_3P31 VCCDSW_3P32

VCCPRIM_1P83 VCCPRIM_1P84 VCCPRIM_1P85 VCCPRIM_1P86 VCCPRIM_1P87

VCCPRIM_1P81 VCCPRIM_1P82

VCCPRIM_1P0520 VCCPRIM_1P0519

VCCPRIM_1P241 VCCPRIM_1P242

VCCDPHY_1P241 VCCDPHY_1P242 VCCDPHY_1P243

VCCMPHY_SENSE VSSMPHY_SENSE

8 OF 13

1

PAD~D

1

PAD~D

1

PAD~D

1

PAD~D

1

PAD~D

1

PAD~D

1

PAD~D

1

PAD~D

PCH_XDP_PREQ# PCH_XDP_PRDY# CPU_XDP_TRS T# PCH_2_CPU _TRIGGER_R CPU_2_PCH _TRIGGER

PCH_2_CPU _TRIGGERPCH_2_CPU _TRIGGER_R

DCPRTC1 DCPRTC2

VCCSPI

VCCRTC1 VCCRTC2

VCCHDA

@ @ @ @

@ @

Rev1.0

T288 T289 T290 T291

T292 T293

T294 T295

AW9

BF47 BG47

+VCCRTCEXT

V23

AN44

BC49 BD49

AN21 AY8 BB7

AC35 AC36 AE35 AE36

AN24 AN26 AP26

AN32

AT44 BE48 BE49

BB14 AG19 AG20 AN15 AR15 BB11

AF19 AF20

AG31 AF31 AK22 AK23

AJ22 AJ23 BG5

K47 K46

+1.8V_PRIM_PCH

0.766A

+1.8V_PHVLDO

+2.8V_FHV1

+1.24V_DPHY

1 1

PCH_XDP_PREQ# <7> PCH_XDP_PRDY# <7> CPU_XDP_TRS T# <7>

CPU_2_PCH _TRIGGER <10>

PCH_2_CPU _TRIGGER < 10>

+3.3V_PHVC

+3.3V_PUSB2

+3.3V_1.8V_SPI

+3.3V_PRTC

+3.3V_PGPPG

+3.3V_PHVLDO

+3.3V_PGPPHK

+3.3V_PGPPEF

+3.3V_1.8V_GPPD

+3.3V_PGPPBC

+3.3V_1.8V_GPPA

+3.3V_FUSE

+3.3V_DSW

+2.8V_FHV0

+1.24V_DPHY_MAR

VCCMPHY_SENSE <89> VSSMPHY_SENSE <89>

@

T76

PAD~D

@

T77

PAD~D

+3.3V_1.8V_AZIO_R

0.1U_0201_10V6K

+1.24V_LDOSRAM

1

0.1U_0201_10V6K

CH68

1

2

BLM15GA750SN1 D_2P

1

CC310

2

1

12

PAD~D

0.1U_0201_10V6K

CC329

@

+3.3V_1.8V_AZIO

1

2

T287

T75

LC1

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2016/01/01

Compal Secret Data

Deciphered Date

2017/01/01

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

CNP-H(7/9) PWR,RSVD

Size Document Number Rev

Custom

LA-H271P

Tuesday, April 09, 2019

Date: Sheet of

1

20 103

1.0

5

4

3

2

1

CNP-H

UH1I

AA19 AA20 AA25 AA27 AA28 AA30 AA31 AA49

AB19 AB25

AB31 AC12 AC17 AC33 AC38

AC46

AD19

AD22 AD25 AD49

AE12

AE33

AE38

AE46

AF22

AF25

AF28

AG1 AG22 AG23 AG25 AG27 AG28 AG30 AG49 AH12 AH17 AH33 AH38

AJ19 AJ20 AJ25 AJ27 AJ28 AJ30 AJ31 AK19 AK20 AK25 AK27 AK28 AK30 AK31

AK46

A28

A33 A37

A45 A46 A47 A48

AA5

AC4

AD1

AD2

AE4

AK4

A2

A3

A4

A5 A8

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71

9 OF 13

VSS72

CNP-H_BGA874

PDG V1P8 Table 50-8 +1.0V_AMPHYPLL

D D

C C

B B

+1.0V_ALW_PCH +1.0V_AMPHYPLL

Align Northbay pop LH423,CH560,CH324 RH289 change to LH423 CH324 change to pop Add CH560 11/28

PDG V1P8 Table 50-8 +1.05V_PRIM 1x 1uF, 0402, close PCH 3mm

8/17 downsize to SE00000UC00

PDG V1P8 Table 50-8 +VCCRTC 1x 0.1uF 0402, close PCH 3mm 1x 1uF 0402, close PCH 5mm

+3.3V_PRTC

1x 1uF 0402, close PCH 3mm

LH423

1 2

+1.05V_PRIM

1U_0201_6.3V6M

1

CH36

2

1U_0201_6.3V6M

1

CH33

2

8/17 downsize to SE00000UC00

LQM18PN2R2NC0L_2P~D

22U_0603_6.3V6M

1

2

0.1U_0201_10V6K

1

CH65

2

8/17 downsize to SE00000SV00

0.213A

22U_0603_6.3V6M

1

CH560

CH324

2

PDG V1P8 Table 50-8 +VCCPRIM_1P8 1x 4.7uF 0603, close PCH 3mm 1x 1uF 0402, close PCH 3mm

PDG V1P8 Table 50-8 +VCCDPHY_1P24 1x 4.7uF 0402, close PCH 5mm

+1.24V_DPHY_MAR

1U_0201_6.3V6M

CH555

CH267

1

2

8/17 downsize to SE00000UC01, and add 1 uF

+1.8V_PRIM_PCH

4.7U_0402_6.3V6M

1U_0201_6.3V6M

1

CH21

2

8/17 downsize to SE00000UC00

4.7U_0402_6.3V6M

1

CH30

2

8/17 Add CH559

1

2

CH22

CH559

PDG V1P8 Table 50-8. +1.0V_AZPLL 1x 4.7uF, 0402, close PCH 5mm

1 2

RH241 0_0603_5%

1U_0201_6.3V6M

@

CH29

PDG V1P8 Table 50-8 VCCAPLL_1P05 1x 1uF, 0402, close PCH 5mm

+1.0V_OCPLL1_R

1

2

8/17 downsize to SE00000UC00

PDG V1P8 Table 50-8 +VCCPRIM_3P3 1x 1uF, 0603, close PCH 3mm Place close to AY8, BB7 pins.

+3.3V_PHVLDO

1

2

8/17 downsize to SE00000UC00

CFL-H PDG rev0.5 4.7uF x1 CRB-H rev0.7 0.1uF x1, 1uF x1

0.0015A

8/17 downsize to SE00000UC00

1U_0201_6.3V6M

CH20

8/17 downsize to SE00000UC00

1U_0201_6.3V6M

1

CH37

2

8/17 downsize to SE00000SV00

PDG V1P8 Table 50-9. +1.0V_XTAL

+1.0V_AZPLL+1.0V_ALW_PCH

1U_0201_6.3V6M

4.7U_0402_6.3V6M

1

@

CH46

CH32

2

PDG V1P8 Table 50-8 +VCCPRIM_1P05 1x 1uF 0402, 3mm, close PCH 5mm 1x 22uF 0805, 5mm, close PCH 5mm

+1.0V_MPHY+1.0V_BCLKPLL2_R

1U_0201_6.3V6M

1

CH31

2

8/17 downsize to SE00000UC00

4.7U_0402_6.3V6M

0.1U_0201_10V6K

@

1

CH323

CH67

2

1x 22uF 0603 depop

+1.0V_ALW_PCH

LQM18PN2R2NC0L_2P~D

LH421

1 2

Intel recommend to follow 2% spec

22U_0603_6.3V6M

1U_0201_6.3V6M

1

2

CH47

CH34

2

+1.0V_XTAL

0.00428A

47U_0603_6.3V6M

CH45

2

1

VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98

VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144

Rev1.0

AL12 AL17 AL21 AL24 AL26 AL29 AL33 AL38 AM1 AM18 AM32 AM49 AN12 AN16 AN34 AN38 AP4 AP46 AR12 AR16 AR34 AR38 AT1 AT16 AT18 AT21 AT24 AT26 AT29 AT32 AT34 AT45 AV11 AV39 AW10 AW4 AW40 AW46 B47 B48 B49 BA12 BA14 BA44 BA5 BA6 BB41 BB43 BB9 BC10 BC13 BC15 BC19 BC24 BC26 BC31 BC35 BC40 BC45 BC8 BD43 BE44 BF1 BF2 BF3 BF48 BF49 BG17 BG2 BG22 BG25 BG28

BG33 BG37

BG48

BG3

BG4

C12 C25 C30

C4

C48

C5 D12 D16 D17 D30 D33

D8 E10 E13 E15 E17 E19 E22 E24 E26 E31 E33 E35 E40 E42

E8 F41 F43 F47 G44

G6

H8

J10 J26 J29

J4 J40 J46 J47 J48

J9

K11 K39 M16 M18 M21

CNP-H_BGA874

UH1L

VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160 VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191 VSS192 VSS193 VSS194 VSS195

CNP-H

12 OF 13

VSS196 VSS197 VSS198 VSS199 VSS200 VSS201 VSS202 VSS203 VSS204 VSS205 VSS206 VSS207 VSS208 VSS209 VSS210 VSS211 VSS212 VSS213 VSS214 VSS215 VSS216 VSS217 VSS218 VSS219 VSS220 VSS221 VSS222 VSS223 VSS224 VSS225 VSS226 VSS227 VSS228 VSS229 VSS230 VSS231 VSS232 VSS233 VSS234 VSS235 VSS236 VSS237 VSS238 VSS239 VSS240 VSS241 VSS242 VSS243 VSS244 VSS245 VSS246

Rev1.0

M24 M32 M34 M49 M5 N12 N16 N34 N35 N37 N38 P26 P29 P4 P46 R12 R16 R26 R29 R3 R34 R38 R4 T17 T18 T32 T4 T49 T5 T7 U12 U15 U17 U21 U24 U33 U38 V20 V22 V4 V46 W25 W27 W28 W30 Y10 Y12 Y17 Y33 Y38 Y9

+1.0V_OC

5

0.1U_0201_10V6K

1

2

+3.3V_PGPPHK

@

CH44

+3.3V_PGPPEF

0.1U_0201_10V6K

@

CH62

1

2

A A

0.1U_0201_10V6K

@

CH64

1

2

8/17 downsize to SE00000SV00

+3.3V_DSW

1

2

0.1U_0201_10V6K

@

CH63

PDG V1P8 Table 50-8 depop, but reserved

+1.0V_DSW +1.0V_CLPLLEBB+1.0V_DUSB

1U_0201_6.3V6M

1

CH35

2

8/17 downsize to SE00000UC00

4

0.1U_0201_10V6K

1

CH38

2

8/17 downsize to SE00000SV00

0.1U_0201_10V6K

1

CH66

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2016/01/01

Compal Secret Data

Deciphered Date

2

2017/01/01

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

CNP-H(8/9) PWR,CAP

Size Document Number Rev

Custom

LA-H271P

Tuesday, April 09, 2019

Date: Sheet of

1

21 103

1.0

5

4

3

2

1

+1.2V_RUN Source

UZ43

+1.2V_MEM

RUN_ON

D D

PCH_PRIM_EN<11,18,89>

C C

B B

1 2

@

RZ509

3.3V_RUN_GFX_ON

0_0402_5%

follow naming rule

+19.5VB_DGFF + 19.5VB_DGFF

QZ20

2

100K_0402_5%

G

12

RZ547

+5V_ALW_R

+3.3V_ALW

+5V_ALW

100K_0402_5%

0.47U_0402_25V6K

12

RZ512

20K_0402_5%

12

RZ514

Material shortage SB00000J500 change to SB00001OO00 1/15

13

D

DMN3150LW -7_SOT323-3

S

VGS max =1.4V Special for EC VTR3 rail 1.8V.

1 2

3

4

AOZ1336DI_DFN8_2 X2

+3.3V_ALW_PCH Source

UZ42

1 2

3

4

AOZ1336DI_DFN8_2 X2

DGFF_PWR_SRC Source

QZ19 AOSP21357L_SO8

12

1 2

CZ526

3 6

+DGFF_SRC_EN #

7

VOUT1

VIN1

8

VOUT2

VIN2

6

CT

ON

VBIAS

5

GND1

9

GND2

7

VOUT1

VIN1

8

VOUT2

VIN2

6

CT

ON

VBIAS

5

GND1

9

GND2

8 7

5

4

PWR change AO4455 to AOSP21357L

+1.2V_RUN_PW R + 1.2V_RUN

470P_0402_50V7K

2

1

470P_0402_50V7K

2

1

2

CZ515

CZ521

JUMP@

PJP67

JUMP_43X118

112

0.1U_0201_10V6K

JUMP@

2

JUMP_43X79

CZ514

0.1U_0201_10V6K

1

2

82P_0402_50V8J

PJP66

2

CZ520

1

2

112

JUMP@

PJP38

JUMP_43X79

RF@

12

CZ545

+5V_ALW_R

RUN_ON<11,22,58,59,6 7,70,89>

3.3V_RUN_GFX_ON<58>

+3.3V_ALW_PC H+3.3V_ALW _PCH_PWR

112

+DGFF_PWR _SRC+DGFF_PWR

0.1U_0201_25V6K

100K_0402_5%

12

CZ525

RZ513

+3.3V_RUN /+5V_RUN Source

RUN_ON<11,22,58,59,6 7,70,89>

@

RZ549

RZ548 0 _0402_5%@

+5V_ALW_R

+3.3V_ALW_R

+5V_ALW_R

1 2

@

RZ510

+5V_ALW_R

+3.3V_ALW_R

+1.8V_PRIM

1 2

RUN_ON

+5V_ALW_R

+3.3V_ALW to +3.3V_DGFF +5V_ALW to +5V_DGFF

UZ41

1

VIN1_1

2

VIN1_2

RUN_ON_R

3

ON1

4

VBIAS

5

ON2

6

VIN2_1

7

VIN2_2

EM5209VF_DFN14 _3X2

UZ40

1

VIN1_1

2

VIN1_2

3

ON1

4

VBIAS

5

ON2

6

VIN2_1

7

VIN2_2

EM5209VF_DFN14 _3X2

0_0402_5%

+1.8V_RUN Source

UZ45

1

VIN1

2

VIN2

3

ON

4

VBIAS

AOZ1336DI_DFN8_2 X2

VOUT1_1 VOUT1_2

GND

VOUT2_1 VOUT2_2

GPAD

VOUT1_1 VOUT1_2

GND

VOUT2_1 VOUT2_2

GPAD

VOUT1 VOUT2

CT

GND1 GND2

+5V_DGFF+ 5V_DGFF_PWR

14

+5V_DGFF_PWR

13

12

CT1

11

10

CT2

9 8

15

14 13

12

CT1

11

10

CT2

9 8

15

7 8

6

5 9

0.1U_0201_10V6K CZ513

470P_0402_50V7K

2

CZ516

1

+5V_RUN_PW R

1000P_0402_50V7K

CZ522

2

1

+1.8V_RUN_PW R

470P_0402_50V7K

CZ121

1

2

JUMP@

PJP65

2

82P_0402_50V8J

1

2

470P_0402_50V7K

2

1

470P_0402_50V7K

2

1

112

1

JUMP_43X79

CZ529

RF@

2

+3.3V_DGFF_PW R +3.3V_DGFF

+3.3V_DGFF_PW R

82P_0402_50V8J

CZ517

CZ523

1

2

+5V_RUN+5V_RUN_ PWR

PJP40

PAD-OPEN 4x4m

JUMP@

CZ519

0.1U_0201_10V6K

1

2

12

+3.3V_RUN_PW R

JUMP@

2

JUMP_43X79

CZ120

0.1U_0201_10V6K

1

2

+1.8V_RUN_PW R + 1.8V_RUN

JUMP@

PJP43

2

112

0.1U_0201_10V6K JUMP_43X79

RF@

CZ518

1

CZ528

2

+3.3V_RUN_PW R +3.3V_RU N

JUMP@

PJP39

2

112

0.1U_0201_10V6K JUMP_43X79

CZ524

1

2

PJP42

112

Discharg Circuit

+5V_RUN

12

RZ518 20_0603_5 %

+5V_RUN_CHG

13

D

2

RUN_ON#<58>

A A

5

QZ21

G

L2N7002W T1G_SC-70-3

S

change SB00000UO00 to SB000009Q80/ SB00000ST00 as main source, SB00000UO00 as 3rd source

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2016/01/01

Compal Secret Data

Deciphered Date

2017/01/01

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

CNP-H(9/9) Power Control

Size Document Number Rev

Custom

LA-H271P

Tuesday, April 09, 2019

Date: Sheet of

1

22 103

1.0

5

4

3

2

1

All VREF traces should have 10 mil trace width

DDR_A_CB[0 ..7]<8,24>

DDR_A_DQS# [0..3]<8 ,24>

DDR_A_DQS[0 ..3]< 8,24>

D D

C C

B B

*

A A

DDR_A_DQS# [4..7]<8 ,24>

DDR_A_DQS[4 ..7]< 8,24>

DDR_A_D[0..6 3]<8,24>

DDR_A_MA[ 0..13]<8,24>

+2.5V_MEM

+1.2V_MEM

DIMM Select

SA0 SA1

0

DIMM4

DIMM1

1100

1

DIMM3

10U_0603_6.3V6M

1U_0201_10V6M

1

CD3

CD1

CD2

2

downsize

change package to 0603

10U_0603_6.3V6M

CD7

CD6

CD8

1

2

1U_0201_10V6M

1

2

downsize

Layout Note: Place near JDIMM1.258

0DIMM2

1

CD18

CD17

2

+0.6V_DDR_ VTT

10U_0603_6.3V6M

1

2

SA2

0

2

CD27

downsize

1

2

1 2

12

CD19

1U_0201_10V6M

@

0_0402_5%

@

0_0402_5%

10U_0603_6.3V6M

1

CD4

2

CD14 change to SGA20331E10

10U_0603_6.3V6M

CD10

1U_0201_10V6M

CD21

RD14

@

0_0402_5%

@

RD79

0_0402_5%

10U_0603_6.3V6M

CD12

CD11

1

2

1U_0201_10V6M

1

CD23

CD22

2

+3.3V_RUN+3.3V_RUN +3.3V_ RUN

12

RD15

@

0_0402_5%

DIMM1_SA0 DIMM1_SA1 DIMM1_SA2

@

RD80

0_0402_5%

1 2

10U_0603_6.3V6M

CD9

1

2

1U_0201_10V6M

1

CD20

2

1U_0201_10V6M

1

CD30

CD31

2

12

RD78

RD18

1 2

10U_0603_6.3V6M

330U_D2_2V_Y

1

CD13

1

+

2

1U_0201_10V6M

1

CD24

2

+V_DDR_RE FCA_A

1

2

+3.3V_RUN

CD14

0.1U_0402_10V6K

CD28

1 2

1

2

DDR_A_CB0<8, 24>

DDR_A_CB5<8, 24>

DDR_A_DQS# 8<8,24> DDR_A_DQS8<8,24>

DDR_A_CB3<8, 24>

DDR_A_CB2<8, 24>

DDR_A_CKE 2<8>

DDR_A_BG0<8,24>

DDR_A_CLK 2<8> DDR_A_CLK #2<8>

DDR_A_PAR ITY<8,24>

DDR_A_BA1< 8,24>

DDR_A_CS# 2<8>

DDR_A_MA1 4<8,24 >

DDR_A_ODT2<8>

2.2U_0402_6.3V6M

@

1

CD29

2

RD16

@

0_0603_5%

+3.3V_RUN_ DIMM1

0.1U_0402_10V6K

2.2U_0603_10V7K

1

CD32

2

DDR_A_CS# 3<8>

DDR_A_ODT3<8>

T47PAD~D @

CD33

DDR_XDP_W AN_SMB CLK<7 ,18,24,25,26,54 > DDR_XDP_W AN_SMB DAT <7,18,2 4,25,26,54>

JDIMM1 REV Type H=5.2

+1.2V_MEM +1.2V_MEM

JDIMM1

1

DDR_A_D4

DDR_A_D0

DDR_A_DQS# 0 DDR_A_DQS0

DDR_A_D7

DDR_A_D3

DDR_A_D13

DDR_A_D12

DDR_A_D15

DDR_A_D14

DDR_A_D21

DDR_A_D20

DDR_A_DQS# 2 DDR_A_DQS2

DDR_A_D22

DDR_A_D18

DDR_A_D29

DDR_A_D28

DDR_A_D27

DDR_A_D30

DDR_A_CB0

DDR_A_CB5

DDR_A_DQS# 8 DDR_A_DQS8

DDR_A_CB3

DDR_A_CB2

DDR_A_CKE 2

DDR_A_BG1 DDR_A_BG0

DDR_A_MA1 2 DDR_A_MA9

DDR_A_MA8 DDR_A_MA6

DDR_A_MA3 DDR_A_MA1

DDR_A_CLK 2 DDR_A_CLK #2

DDR_A_PAR ITY

DDR_A_BA1

DDR_A_CS# 2 DDR_A_MA1 4

DDR_A_ODT2 DDR_A_CS# 3

DDR_A_ODT3

1

DDR_A_D33

DDR_A_D37

DDR_A_DQS# 4 DDR_A_DQS4

DDR_A_D38

DDR_A_D39

DDR_A_D44

DDR_A_D41

DDR_A_D43

DDR_A_D46

DDR_A_D50

DDR_A_D52

DDR_A_DQS# 6 DDR_A_DQS6

DDR_A_D54

DDR_A_D51

DDR_A_D57

DDR_A_D61

DDR_A_D62

DDR_A_D58

+3.3V_RUN_ DIMM1

VSS1

3

DQ5

5

VSS3

7

DQ1

9

VSS5 DQS0_c11DM0_n/DBI0_n

13

DQS0_t

15

VSS8

17

DQ7

19

VSS10

21

DQ3

23

VSS12

25

DQ13

27

VSS14

29

DQ9

31

VSS16 DM1_n/DBI_n33DQS1_t

35

VSS17

37

DQ15

39

VSS19

41

DQ10

43

VSS21

45

DQ21

47

VSS23

49

DQ17

51

VSS25 DQS2_c53DM2_n/DBI2_n

55

DQS2_t

57

VSS28

59

DQ23

61

VSS30

63

DQ19

65

VSS32

67

DQ29

69

VSS34

71

DQ25

73

VSS36 DM3_n/DBI3_n75DQS3_t

77

VSS37

79

DQ30

81

VSS39

83

DQ26

85

VSS41

87

CB5/NC

89

VSS43

91

CB1/NC

93

VSS45 DQS8_c95DM8_n/DBI_n/NC

97

DQS8_t

99

VSS48

101

CB2/NC

103

VSS50

105

CB3/NC

107

VSS52

109

CKE0

111

VDD1

113

BG1

115

BG0

117

VDD3

119

A12

121

A9

123

VDD5

125

A8

127

A6

129

VDD7

131

A3

133

A1

135

VDD9

137

CK0_t

139

CK0_c

141

VDD11

143

PARITY

145

BA1

147

VDD13

149

CS0_n

151

WE_n/A14

153

VDD15

155

ODT0

157

CS1_n

159

VDD17

161

ODT1

163

VDD19

165

C1, CS3_n,NC

167

VSS53

169

DQ37

171

VSS55

173

DQ33

175

VSS57

177

DQS4_c

179

DQS4_t

181

VSS60

183

DQ38

185

VSS62

187

DQ34

189

VSS64

191

DQ44

193

VSS66

195

DQ40

197

VSS68

199

DM5_n/DBI5_n

201

VSS69

203

DQ46

205

VSS71

207

DQ42

209

VSS73

211

DQ52

213

VSS75

215

DQ49

217

VSS77

219

DQS6_c

221

DQS6_t

223

VSS80

225

DQ55

227

VSS82

229

DQ51

231

VSS84

233

DQ61

235

VSS86

237

DQ56

239

VSS88

241

DM7_n/DBI7_n

243

VSS89

245

DQ62

247

VSS91

249

DQ58

251

VSS93

253

SCL

255

VDDSPD

257

VPP1

259

VPP2

261

GND1

263

NPTH1

ADDR0208-P0 01A02

CONN@

SP07001 JH0L

DM4_n/DBI4_n

DM6_n/DBI6_n

VSS2

VSS4

VSS6

VSS7

VSS9

VSS11

DQ12

VSS13

VSS15

DQS1_c

VSS18

DQ14

VSS20

DQ11

VSS22

DQ20

VSS24

DQ16

VSS26

VSS27

DQ22

VSS29

DQ18

VSS31

DQ28

VSS33

DQ24

VSS35

DQS3_c

VSS38

DQ31

VSS40

DQ27

VSS42

CB4/NC

VSS44

CB0/NC

VSS46

VSS47

CB6/NC

VSS49

CB7/NC

VSS51

RESET_n

CKE1 VDD2

ACT_n

ALERT_n

VDD4

VDD6

VDD8

EVENT_n/NF

VDD10

CK1_t/NF

CK1_c/NF

VDD12

A10/AP VDD14

RAS_n/A16

VDD16

CAS_n/A15

VDD18

C0/CS2_n/NC

VREFCA

VSS54

DQ36

VSS56

DQ32

VSS58

VSS59

DQ39

VSS61

DQ35

VSS63

DQ45

VSS65

DQ41

VSS67

DQS5_c

DQS5_t

VSS70

DQ47

VSS72

DQ43

VSS74

DQ53

VSS76

DQ48

VSS78

VSS79

DQ54

VSS81

DQ50

VSS83

DQ60

VSS85

DQ57

VSS87

DQS7_c

DQS7_t

VSS90

DQ63

VSS92

DQ59

VSS94

GND2

NPTH2

2

DDR_A_D1

4

DQ4

6

DDR_A_D5

8

DQ0

10 12 14

DDR_A_D6

16

DQ6

18

DDR_A_D2

20

DQ2

22

DDR_A_D9

24 26

DDR_A_D8

28

DQ8

30

DDR_A_DQS# 1

32

DDR_A_DQS1

34 36

DDR_A_D10

38 40

DDR_A_D11

42 44

DDR_A_D16

46 48

DDR_A_D17

50 52 54 56

DDR_A_D19

58 60

DDR_A_D23

62 64

DDR_A_D24

66 68

DDR_A_D25

70 72

DDR_A_DQS# 3

74

DDR_A_DQS3

76 78

DDR_A_D26

80 82

DDR_A_D31

84 86

DDR_A_CB1

88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120

A11

122

A7

124 126

A5

128

A4

130 132

A2

134 136 138 140 142 144

A0

146 148 150

BA0

152 154 156 158

A13

160 162 164 166

SA2

168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 206 208 210 212 214 216 218 220 222 224 226 228 230 232 234 236 238 240 242 244 246 248 250 252 254

SDA

256

SA0

258

VTT

260

SA1

262

264

DDR_A_CB4

DDR_A_CB7

DDR_A_CB6

DDR_A_DRA MRST# DDR_A_CKE 3

DDR_A_ACT# DDR_A_ALE RT#

DDR_A_MA1 1 DDR_A_MA7

DDR_A_MA5 DDR_A_MA4

DDR_A_MA2 JDIMM1_EVE NT#

DDR_A_CLK 3 DDR_A_CLK #3

DDR_A_MA0

DDR_A_MA1 0

DDR_A_BA0 DDR_A_MA1 6

DDR_A_MA1 5 DDR_A_MA1 3

1

DIMM1_SA2

DDR_A_D36

DDR_A_D32

DDR_A_D35

DDR_A_D34

DDR_A_D40

DDR_A_D45

DDR_A_DQS# 5 DDR_A_DQS5

DDR_A_D47

DDR_A_D42

DDR_A_D48

DDR_A_D49

DDR_A_D53

DDR_A_D55

DDR_A_D56

DDR_A_D60

DDR_A_DQS# 7 DDR_A_DQS7

DDR_A_D59

DDR_A_D63

DIMM1_SA0

DIMM1_SA1

DDR_A_CB1 <8,24>

DDR_A_CB4 <8,24>

DDR_A_CB7 <8,24>

DDR_A_CB6 <8,24>

1 2

CD15 0.1U_0201 _10V6K@

DDR_A_CKE 3 <8>

DDR_A_ACT# <8,24>DDR_A_BG1<8,24> DDR_A_ALE RT# <8,24>

DDR_A_CLK 3 <8> DDR_A_CLK #3 <8>

DDR_A_BA0 < 8,24> DDR_A_MA1 6 <8,2 4>

DDR_A_MA1 5 <8,24 >

T46 PAD ~D@

+V_DDR_RE FCA_A

+0.6V_DDR_ VTT+2.5V_MEM

+V_DDR_RE FCA_A

DDR_VTT_CTRL<7>

CPU

JDIMM4

B A

JDIMM3

+1.2V_MEM

JDIMM1_EVE NT#

+DDR_VREF _CA

STD

12

1

2

12

REV

D

C

RD4 470_0402_1 %

0.1U_0402_10V6K

@

CD5

RD7 1K_0402 _5%@

0.022U_0402_16V7K

1

2

24.9_0402_1%

CH-ACH-B

STD

-->CKE0,1-->CKE0,1

JDIMM2

Top Side

B

A

JDIMM1

REV

H_THERMTRIP#

+V_DDR_RE FCA_B

+V_DDR_RE FCA_A

5

VCC

4

Y

Bottom Side

DDR_A_DRA MRST# DDR_B_DRA MRST#

+V_DDR_RE FCA_B

+3.3V_RUN

330K_0402_5%

12

-->CKE2,3 -->CKE2,3

@

1 2

RD76 0_0402_5%

@

1 2

RD77 0_0402_5%

1 2

RD9 2_0 402_1%@

1 2

RD10 2_0402 _1%

CD25

RD12

UD1

1

NC

2

A

3

GND

74AUP1G07GW _TSSOP5

DDR_A_DRA MRST# <24>DDR4_DRAMR ST#_PCH<1 8> DDR_B_DRA MRST# <25,26>

H_THERMTRIP# <7,14,24,25,26,59 >

+1.2V_MEM

12

0.1U_0402_10V6K

@

12

CD26

1

2

RD17

+1.2V_MEM

1 2

CD34@ 0.1U_0402_2 5V6

0.6V_DDR_VTT_ON

0.1U_0402_10V6K

@

1K_0402_5%

CD16

RD8

1

2

1K_0402_5%

RD11

0.6V_DDR_VTT_ON <88>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2016/01/01

Compal Secret Data

Deciphered Date

2

2017/01/01

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

DDR4_DIMM1

Size Docum ent Number Rev

Custom

LA-H271P

Tuesday, April 09, 2019

Date: Sheet of

1

23 103

1.0

5

4

3

2

1

JDIMM2 STD Type H=4

DDR_A_CB[0. .7]<8,23>

DDR_A_DQS #[0..3]<8,23>

DDR_A_DQS [0..3]<8,23>

DDR_A_DQS #[4..7]<8,23>

DDR_A_DQS [4..7]<8,23>

D D

C C

B B

DIMM2

*

DIMM4

DIMM1

DIMM3

A A

5

DDR_A_D[0..63 ]<8,23>

DDR_A_MA[0..13]<8,23>

+2.5V_MEM

1

2

downsize

+1.2V_MEM

1

2

1

2

downsize

Layout Note: Place near JDIMM2.258

DIMM Select

SA2

SA0 SA1

0

0 1

1

0

1 1

1U_0201_10V6M

1

CD36

2

10U_0603_6.3V6M

CD39

1

2

1U_0201_10V6M

1

CD49

2

+0.6V_DDR_VT T

0

10U_0603_6.3V6M

1U_0201_10V6M

10U_0603_6.3V6M

1

CD35

CD37

CD38

2

CD25 change to SGA20331E10

10U_0603_6.3V6M

CD41

CD42

CD40

1

2

1U_0201_10V6M

1

CD50

CD51

CD52

2

1U_0201_10V6M

10U_0603_6.3V6M

CD57

1

CD58

2

downsize

12

RD22

@

0_0402_5%

@

RD81

0_0402_5%

1 2

1

2

1

2

CD59

12

1 2

10U_0603_6.3V6M

CD43

1U_0201_10V6M

CD53

RD23

@

0_0402_5%

@

RD82

0_0402_5%

1

2

1

2

+3.3V_RUN+3.3V_R UN+3.3V_RUN

10U_0603_6.3V6M

CD44

1U_0201_10V6M

CD54

12

1 2

10U_0603_6.3V6M

CD45

1

2

1U_0201_10V6M

1

CD55

2

+V_DDR_RE FCA_A

RD24

@

0_0402_5%

DIMM2_SA0 DIMM2_SA1 DIMM2_SA2

@

RD83

0_0402_5%

10U_0603_6.3V6M

330U_D2_2V_Y

@

1

CD46

CD47

+

2

1U_0201_10V6M

CD56

0.1U_0402_10V6K

2.2U_0402_6.3V6M

@

1

CD60

CD61

2

+3.3V_RUN

RD92

@

0_0603_5%

1 2

+3.3V_RUN_D IMM2

0.1U_0402_10V6K

2.2U_0603_10V7K

1

CD62

2

4

DDR_A_CB0<8,23>

DDR_A_CB5<8,23>

DDR_A_DQS #8<8,23> DDR_A_DQS 8<8,23>

DDR_A_CB3<8,23>

DDR_A_CB2<8,23>

DDR_A_CKE 0<8>

DDR_A_BG1<8,23> DDR_A_BG0<8,23>

DDR_A_CLK0<8> DDR_A_CLK# 0<8>

DDR_A_PAR ITY<8,23>

DDR_A_BA1<8,23>

DDR_A_CS#0<8>

DDR_A_MA14<8,23>

DDR_A_ODT 0<8>

DDR_A_CS#1<8>

DDR_A_ODT 1<8>

T49PAD~D @

CD63

DDR_XDP_W AN_SMBCLK<7,18,23,25,26,54>

+2.5V_MEM

+1.2V_MEM +1.2V_MEM

DDR_A_D1

DDR_A_D5

DDR_A_DQS #0 DDR_A_DQS 0

DDR_A_D6

DDR_A_D2

DDR_A_D9

DDR_A_D8

DDR_A_D10

DDR_A_D11

DDR_A_D16

DDR_A_D17

DDR_A_DQS #2 DDR_A_DQS 2

DDR_A_D19

DDR_A_D23

DDR_A_D24

DDR_A_D25

DDR_A_D26

DDR_A_D31

DDR_A_CB0

DDR_A_CB5

DDR_A_DQS #8 DDR_A_DQS 8

DDR_A_CB3

DDR_A_CB2

DDR_A_CKE 0

DDR_A_BG1 DDR_A_BG0

DDR_A_MA12 DDR_A_MA9

DDR_A_MA8 DDR_A_MA6

DDR_A_MA3 DDR_A_MA1

DDR_A_CLK0 DDR_A_CLK# 0

DDR_A_PAR ITY

DDR_A_BA1

DDR_A_CS#0 DDR_A_MA14

DDR_A_ODT 0 DDR_A_CS#1

DDR_A_ODT 1

1

DDR_A_D36

DDR_A_D32

DDR_A_DQS #4 DDR_A_DQS 4

DDR_A_D35

DDR_A_D34

DDR_A_D40

DDR_A_D45

DDR_A_D47

DDR_A_D42

DDR_A_D48

DDR_A_D49

DDR_A_DQS #6 DDR_A_DQS 6

DDR_A_D53

DDR_A_D55

DDR_A_D56

DDR_A_D60

DDR_A_D59

DDR_A_D63

+3.3V_RUN_D IMM2

JDIMM2

1

VSS1

3

DQ5

5

VSS3

7

DQ1

9

VSS5 DQS0_c11DM0_n/DBI0_n

13

DQS0_t

15

VSS8

17

DQ7

19

VSS10

21

DQ3

23

VSS12

25

DQ13

27

VSS14

29

DQ9

31

VSS16

33

DM1_n/DBI_n

35

VSS17

37

DQ15

39

VSS19

41

DQ10

43

VSS21

45

DQ21

47

VSS23

49

DQ17

51

VSS25 DQS2_c53DM2_n/DBI2_n

55

DQS2_t

57

VSS28

59

DQ23

61

VSS30

63

DQ19

65

VSS32

67

DQ29

69

VSS34

71

DQ25

73

VSS36 DM3_n/DBI3_n75DQS3_t

77

VSS37

79

DQ30

81

VSS39

83

DQ26

85

VSS41

87

CB5/NC

89

VSS43

91

CB1/NC

93

VSS45 DQS8_c95DM8_n/DBI_n/NC

97

DQS8_t

99

VSS48

101

CB2/NC

103

VSS50

105

CB3/NC

107

VSS52

109

CKE0

111

VDD1

113

BG1

115

BG0

117

VDD3

119

A12

121

A9

123

VDD5

125

A8

127

A6

129

VDD7

131

A3

133

A1

135

VDD9

137

CK0_t

139

CK0_c

141

VDD11

143

PARITY

145

BA1

147

VDD13

149

CS0_n

151

WE_n/A14

153

VDD15

155

ODT0

157

CS1_n

159

VDD17

161

ODT1

163

VDD19

165

C1, CS3_n,NC

167

VSS53

169

DQ37

171

VSS55

173

DQ33

175

VSS57

177

DQS4_c

179

DQS4_t

181

VSS60

183

DQ38

185

VSS62

187

DQ34

189

VSS64

191

DQ44

193

VSS66

195

DQ40

197

VSS68

199

DM5_n/DBI5_n

201

VSS69

203

DQ46

205

VSS71

207

DQ42

209

VSS73

211

DQ52

213

VSS75

215

DQ49

217

VSS77

219

DQS6_c

221

DQS6_t

223

VSS80

225

DQ55

227

VSS82

229

DQ51

231

VSS84

233

DQ61

235

VSS86

237

DQ56

239

VSS88

241

DM7_n/DBI7_n

243

VSS89

245

DQ62

247

VSS91

249

DQ58

251

VSS93

253

SCL

255

VDDSPD

257

VPP1

259

VPP2

261

GND1

263

NPTH1

BELLW_80888-20 21 CONN@

SP07001GA0L

3

VSS2

VSS4

VSS6

VSS7

VSS9

VSS11

DQ12

VSS13

VSS15

DQS1_c

DQS1_t

VSS18

DQ14

VSS20

DQ11

VSS22

DQ20

VSS24

DQ16

VSS26

VSS27

DQ22

VSS29

DQ18

VSS31

DQ28

VSS33

DQ24

VSS35

DQS3_c

VSS38

DQ31

VSS40

DQ27

VSS42

CB4/NC

VSS44

CB0/NC

VSS46

VSS47

CB6/NC

VSS49

CB7/NC

VSS51

RESET_n

CKE1 VDD2

ACT_n

ALERT_n

VDD4

VDD6

VDD8

EVENT_n/NF

VDD10

CK1_t/NF

CK1_c/NF

VDD12

A10/AP VDD14

RAS_n/A16

VDD16

CAS_n/A15

VDD18

C0/CS2_n/NC

VREFCA

VSS54

DQ36

VSS56

DQ32

VSS58

DM4_n/DBI4_n

VSS59

DQ39

VSS61

DQ35

VSS63

DQ45

VSS65

DQ41

VSS67

DQS5_c

DQS5_t

VSS70

DQ47

VSS72

DQ43

VSS74

DQ53

VSS76

DQ48

VSS78

DM6_n/DBI6_n

VSS79

DQ54

VSS81

DQ50

VSS83

DQ60

VSS85

DQ57

VSS87

DQS7_c

DQS7_t

VSS90

DQ63

VSS92

DQ59

VSS94

GND2

NPTH2

2

DDR_A_D4

4

DQ4

6

DDR_A_D0

8

DQ0

10 12 14

DDR_A_D7

16

DQ6

18

DDR_A_D3

20

DQ2

22

DDR_A_D13

24 26

DDR_A_D12

28

DQ8

30

DDR_A_DQS #1

32

DDR_A_DQS 1

34 36

DDR_A_D15

38 40

DDR_A_D14

42 44

DDR_A_D21

46 48

DDR_A_D20

50 52 54 56

DDR_A_D22

58 60

DDR_A_D18

62 64

DDR_A_D29

66 68

DDR_A_D28

70 72

DDR_A_DQS #3

74

DDR_A_DQS 3

76 78

DDR_A_D27

80 82

DDR_A_D30

84 86

DDR_A_CB1

88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120

A11

122

A7

124 126

A5

128

A4

130 132

A2

134 136 138 140 142 144

A0

146 148 150

BA0

152 154 156 158

A13

160 162 164 166

SA2

168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 206 208 210 212 214 216 218 220 222 224 226 228 230 232 234 236 238 240 242 244 246 248 250 252 254

SDA

256

SA0

258

VTT

260

SA1

262

264

DDR_A_CB1 <8,23>

DDR_A_CB4

DDR_A_CB4 <8,23>

DDR_A_CB7

DDR_A_CB7 <8,23>

DDR_A_CB6

DDR_A_CB6 <8,23> DDR_A_DR AMRST# DDR_A_CKE 1

DDR_A_ACT # DDR_A_ALER T#

DDR_A_MA11 DDR_A_MA7

DDR_A_MA5 DDR_A_MA4

DDR_A_MA2 JDIMM2_EVENT#

DDR_A_CLK1 DDR_A_CLK# 1

DDR_A_MA0

DDR_A_MA10

DDR_A_BA0 DDR_A_MA16

DDR_A_MA15 DDR_A_MA13

DIMM2_SA2

DDR_A_D33

DDR_A_D37

DDR_A_D38

DDR_A_D39

DDR_A_D44

DDR_A_D41

DDR_A_DQS #5 DDR_A_DQS 5

DDR_A_D43

DDR_A_D46

DDR_A_D50

DDR_A_D52

DDR_A_D54

DDR_A_D51

DDR_A_D57

DDR_A_D61

DDR_A_DQS #7 DDR_A_DQS 7

DDR_A_D62

DDR_A_D58

DIMM2_SA0

DIMM2_SA1

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1 2

CD48 0.1U_0201_10V6K@

DDR_A_CKE 1 <8>

DDR_A_ACT # <8,23> DDR_A_ALER T# <8,23>

DDR_A_CLK1 <8> DDR_A_CLK# 1 <8>

DDR_A_BA0 <8,23> DDR_A_MA16 <8,23>

DDR_A_MA15 <8,23>

1

T48 P AD~D@

+V_DDR_RE FCA_A

DDR_XDP_W AN_SMBDAT <7,18,23,25,26,54>

+0.6V_DDR_VT T

Issued Date

+V_DDR_RE FCA_A

2016/01/01

CPU

Compal Secret Data

2

REV

JDIMM4

D

B A

C

JDIMM3

STD REV

RD21 1K_0402_5%@

Deciphered Date

CH-ACH-B

JDIMM1

DDR_A_DR AMRST#

H_THERMT RIP#JDIMM2_EVENT#

2017/01/01

STD

JDIMM2

B

A

DDR_A_DR AMRST# <23>

Top Side

Bottom Side

-->CKE2,3-->CKE2,3

-->CKE0,1 -->CKE0,1

1 2

H_THERMT RIP# <7,14,23,25,26,59>

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

DDR4_DIMM2

Size Docum ent Number Rev

Custom

LA-H271P

Tuesday, April 09, 2019

Date: Sheet of

1

24 103

1.0

5

4

3

2

1

JDIMM3 STD Type H=5.2

JDIMM3

1

DDR_B_D4

DDR_B_D1

DDR_B_BA1<8,26>

DDR_B_MA1 4<8, 26>

+2.5V_MEM

DDR_B_DQS# 0 DDR_B_DQS0

DDR_B_D6

DDR_B_D3

DDR_B_D10

DDR_B_D9

DDR_B_D12

DDR_B_D13

DDR_B_D18

DDR_B_D22

DDR_B_DQS# 2 DDR_B_DQS2

DDR_B_D19

DDR_B_D20

DDR_B_D25

DDR_B_D30

DDR_B_D29

DDR_B_D31

DDR_B_CB4

DDR_B_CB2

DDR_B_DQS# 8 DDR_B_DQS8

DDR_B_CB7

DDR_B_CB5

DDR_B_CKE 2

DDR_B_BG1 DDR_B_BG0

DDR_B_MA1 2 DDR_B_MA9

DDR_B_MA8 DDR_B_MA6

DDR_B_MA3 DDR_B_MA1

DDR_B_CLK 2 DDR_B_CLK #2

DDR_B_PAR ITY

DDR_B_BA1

DDR_B_CS# 2 DDR_B_MA1 4

DDR_B_ODT2 DDR_B_CS# 3

DDR_B_ODT3

1

T51PAD~D @

DDR_B_D35

DDR_B_D34

DDR_B_DQS# 4 DDR_B_DQS4

DDR_B_D33

DDR_B_D32

DDR_B_D40

DDR_B_D41

DDR_B_D42

DDR_B_D46

DDR_B_D48

DDR_B_D52

DDR_B_DQS# 6 DDR_B_DQS6

DDR_B_D50

DDR_B_D55

DDR_B_D57

DDR_B_D61

DDR_B_D56

DDR_B_D60

+3.3V_RUN_ DIMM3

DDR_B_CB[0 ..7]<8,26>

DDR_B_DQS# [0..7]<8 ,26>

D D

C C

B B

A A

DDR_B_DQS[0 ..7]<8 ,26>

DDR_B_D[0..6 3]<8,26>

DDR_B_MA[ 0..13]<8,26>

DIMM Select

SA0 SA1

DIMM2

DIMM4

DIMM1

DIMM3

*

+2.5V_MEM

1U_0201_10V6M

1

CD64

2

downsize

+1.2V_MEM

10U_0603_6.3V6M

CD68

1

2

1U_0201_10V6M

1

CD79

2

downsize

Layout Note: Place near JDIMM3.258

+0.6V_DDR_ VTT

SA2

0

0 1

0

1

0

1 1

10U_0603_6.3V6M

1U_0201_10V6M

1

CD67

CD66

CD65

2

10U_0603_6.3V6M

CD69

CD70

1

2

1U_0201_10V6M

1

CD80

CD81

2

1U_0201_10V6M

10U_0603_6.3V6M

CD91

1

CD92

2

downsize

@

0_0402_5%

1 2

12

@

0_0402_5%

10U_0603_6.3V6M

CD72

CD71

1

2

1U_0201_10V6M

1

CD82

CD83

2

1U_0201_10V6M

1

CD93

2

@

RD85

RD86

0_0402_5%

1 2

12

RD42

RD43

@

0_0402_5%

CD73

1U_0201_10V6M

CD84

+3.3V_RUN+3.3 V_RUN+3.3V_RU N

10U_0603_6.3V6M

CD74

1

2

1U_0201_10V6M

1

CD85

2

+V_DDR_RE FCA_B

12

RD40

@

0_0402_5%

DIMM3_SA0 DIMM3_SA1 DIMM3_SA2

@

RD87

0_0402_5%

1 2

10U_0603_6.3V6M

330U_D2_2V_Y

1

CD76

CD75

+

2

1U_0201_10V6M

CD86

0.1U_0402_10V6K

2.2U_0402_6.3V6M

@

1

CD95

CD94

2

+3.3V_RUN

RD93

@

0_0603_5%

1 2

+3.3V_RUN_ DIMM3

0.1U_0402_10V6K

2.2U_0603_10V7K

1

CD98

2

DDR_B_CB4<8, 26>

DDR_B_CB2<8, 26>

DDR_B_DQS# 8<8,26> DDR_B_DQS8<8,26>

DDR_B_CB7<8, 26>

DDR_B_CB5<8, 26>

DDR_B_CKE 2<8>

DDR_B_BG1<8,26> DDR_B_BG0<8,26>

DDR_B_CLK 2<8> DDR_B_CLK #2<8>

DDR_B_PAR ITY<8,26>

DDR_B_CS# 2<8>

DDR_B_ODT2<8>

DDR_B_CS# 3<8>

DDR_B_ODT3<8>

CD99

VSS1

3

DQ5

5

VSS3

7

DQ1

9

VSS5 DQS0_c11DM0_n/DBI0_n

13

DQS0_t

15

VSS8

17

DQ7

19

VSS10

21

DQ3

23

VSS12

25

DQ13

27

VSS14

29

DQ9

31

VSS16 DM1_n/DBI_n33DQS1_t

35

VSS17

37

DQ15

39

VSS19

41

DQ10

43

VSS21

45

DQ21

47

VSS23

49

DQ17

51

VSS25 DQS2_c53DM2_n/DBI2_n

55

DQS2_t

57

VSS28

59

DQ23

61

VSS30

63

DQ19

65

VSS32

67

DQ29

69

VSS34

71

DQ25

73

VSS36 DM3_n/DBI3_n75DQS3_t

77

VSS37

79

DQ30

81

VSS39

83

DQ26

85

VSS41

87

CB5/NC

89

VSS43

91

CB1/NC

93

VSS45 DQS8_c95DM8_n/DBI_n/NC

97

DQS8_t

99

VSS48

101

CB2/NC

103

VSS50

105

CB3/NC

107

VSS52

109

CKE0

111

VDD1

113

BG1

115

BG0

117

VDD3

119

A12

121

A9

123

VDD5

125

A8

127

A6

129

VDD7

131

A3

133

A1

135

VDD9

137

CK0_t

139

CK0_c

141

VDD11

143

PARITY

145

BA1

147

VDD13

149

CS0_n

151

WE_n/A14

153

VDD15

155

ODT0

157

CS1_n

159

VDD17

161

ODT1

163

VDD19

165

C1, CS3_n,NC

167

VSS53

169

DQ37

171

VSS55

173

DQ33

175

VSS57

177

DQS4_c

179

DQS4_t

181

VSS60

183

DQ38

185

VSS62

187

DQ34

189

VSS64

191

DQ44

193

VSS66

195

DQ40

197

VSS68

199

DM5_n/DBI5_n

201

VSS69

203

DQ46

205

VSS71

207

DQ42

209

VSS73

211

DQ52

213

VSS75

215

DQ49

217

VSS77

219

DQS6_c

221

DQS6_t

223

VSS80

225

DQ55

227

VSS82

229

DQ51

231

VSS84

233

DQ61

235

VSS86

237

DQ56

239

VSS88

241

DM7_n/DBI7_n

243

VSS89

245

DQ62

247

VSS91

249

DQ58

251

VSS93

253

SCL

255

VDDSPD

257

VPP1

259

VPP2

261

GND1

263

NPTH1

BELLW _80888-2021

CONN@

SP07001GT0L

EVENT_n/NF

RAS_n/A16

CAS_n/A15

C0/CS2_n/NC

DM4_n/DBI4_n

DM6_n/DBI6_n

VSS2

VSS4

VSS6

VSS7

VSS9

VSS11

DQ12

VSS13

VSS15

DQS1_c

VSS18

DQ14

VSS20

DQ11

VSS22

DQ20

VSS24

DQ16

VSS26

VSS27

DQ22

VSS29

DQ18

VSS31

DQ28

VSS33

DQ24

VSS35

DQS3_c

VSS38

DQ31

VSS40

DQ27

VSS42

CB4/NC

VSS44

CB0/NC

VSS46

VSS47

CB6/NC

VSS49

CB7/NC

VSS51

RESET_n

CKE1 VDD2

ACT_n

ALERT_n

VDD4

VDD6

VDD8

VDD10

CK1_t/NF

CK1_c/NF

VDD12

A10/AP

VDD14

VDD16

VDD18

VREFCA

VSS54

DQ36

VSS56

DQ32

VSS58

VSS59

DQ39

VSS61

DQ35

VSS63

DQ45

VSS65

DQ41

VSS67 DQS5_c DQS5_t

VSS70

DQ47

VSS72

DQ43

VSS74

DQ53

VSS76

DQ48

VSS78

VSS79

DQ54

VSS81

DQ50

VSS83

DQ60

VSS85

DQ57

VSS87 DQS7_c DQS7_t

VSS90

DQ63

VSS92

DQ59

VSS94

GND2

NPTH2

+1.2V_MEM+1.2V_MEM

2

DDR_B_D5

4

DQ4

6

DDR_B_D0

8

DQ0

10 12 14

DDR_B_D2

16

DQ6

18

DDR_B_D7

20

DQ2

22

DDR_B_D8

24 26

DDR_B_D14

28

DQ8

30

DDR_B_DQS# 1

32

DDR_B_DQS1

34 36

DDR_B_D11

38 40

DDR_B_D15

42 44

DDR_B_D17

46 48

DDR_B_D16

50 52 54 56

DDR_B_D23

58 60

DDR_B_D21

62 64

DDR_B_D28

66 68

DDR_B_D27

70 72

DDR_B_DQS# 3

74

DDR_B_DQS3

76 78

DDR_B_D26

80 82

DDR_B_D24

84 86

DDR_B_CB1

88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120

A11

122

A7

124 126

A5

128

A4

130 132

A2

134 136 138 140 142 144

A0

146 148 150

BA0

152 154 156 158

A13

160 162 164 166

SA2

168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 206 208 210 212 214 216 218 220 222 224 226 228 230 232 234 236 238 240 242 244 246 248 250 252 254

SDA

256

SA0

258

VTT

260

SA1

262

264

DDR_B_CB3

DDR_B_CB6

DDR_B_CB0

DDR_B_DRA MRST# DDR_B_CKE 3

DDR_B_ACT# DDR_B_ALE RT#

DDR_B_MA1 1 DDR_B_MA7

DDR_B_MA5 DDR_B_MA4

DDR_B_MA2 JDIMM3_EVE NT#

DDR_B_CLK 3 DDR_B_CLK #3

DDR_B_MA0

DDR_B_MA1 0

DDR_B_BA0 DDR_B_MA1 6

DDR_B_MA1 5 DDR_B_MA1 3

1

DIMM3_SA2

DDR_B_D38

DDR_B_D39

DDR_B_D36

DDR_B_D37

DDR_B_D44

DDR_B_D45

DDR_B_DQS# 5 DDR_B_DQS5

DDR_B_D47

DDR_B_D43

DDR_B_D51

DDR_B_D54

DDR_B_D53

DDR_B_D49

DDR_B_D59

DDR_B_D62

DDR_B_DQS# 7 DDR_B_DQS7

DDR_B_D58

DDR_B_D63

DIMM3_SA0

DIMM3_SA1

DDR_B_CB1 <8,26>

DDR_B_CB3 <8,26>

DDR_B_CB6 <8,26>

DDR_B_CB0 <8,26>

1 2

CD78 0.1U_0201 _10V6K@

DDR_B_CKE 3 <8>

DDR_B_ACT# <8,26> DDR_B_ALE RT# <8,26>

DDR_B_CLK 3 <8> DDR_B_CLK #3 <8>

DDR_B_BA0 < 8,26> DDR_B_MA1 6 <8,2 6>

DDR_B_MA1 5 <8,2 6>

T50 PAD ~D@

+V_DDR_RE FCA_B

DDR_XDP_W AN_SMB DAT <7,18,2 3,24,26,54>DDR_XDP_W AN_SMB CLK< 7,18,23,24,26, 54>

+0.6V_DDR_ VTT

+V_DDR_RE FCA_B

CH-B CH-A

REV

CPU

B A

JDIMM3

D

C

-->CKE0,1 -->CKE0,1

JDIMM4

STD REV

RD29 1K_0402 _5%@

+DDR_VREF _B_DQ

RD31 2_0402 _1%

0.022U_0402_16V7K

1

CD87

2

24.9_0402_1%

12

RD33

@

+DIMM_DQ_R_V REF_B +V_DDR_REFCA_B

RD84

0_0402_5%

JDIMM2

JDIMM1

DDR_B_DRA MRST#

1 2

12

1

2

STD

Top Side

B

A

Bottom Side

-->CKE2,3-->CKE2,3

DDR_B_DRA MRST# <23,26>

H_THERMTRIP#JDIMM3_EVE NT#

+DIMM_DQ_R_V REF_B

0.1U_0402_10V6K

@

CD88

1

2

1 2

RD36 0_040 2_5%@

0.1U_0402_10V6K

@

CD97

H_THERMTRIP# <7,14,23,24,26 ,59>

+1.2V_MEM

0.1U_0402_10V6K

1K_0402_5%

12

RD30

1

2

0.1U_0402_10V6K

@

1K_0402_5%

12

RD32

CD89

1

2

+1.2V_MEM

1K_0402_5%

12

1K_0402_5%

12

@

CD77

@

CD90

0.1U_0402_10V6K

@

CD96

RD34

1

2

@

RD37

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2016/01/01

Compal Secret Data

Deciphered Date

2

DELL CONFIDENTIAL/PROPRIETARY

2017/01/01

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

DDR4_DIMM3

Size Docum ent Number Rev

Custom

LA-H271P

Tuesday, April 09, 2019

Date: Sheet of

1

25 103

1.0

5

4

3

2

1

JDIMM4 REV Type H=4

+1.2V_MEM

JDIMM4

1

VSS1

3

DQ5

5

VSS3

7

DQ1

9

VSS5 DQS0_c11DM0_n/DBI0_n

13

DQS0_t

15

VSS8

17

DQ7

19

VSS10

21

DQ3

23

VSS12

25

DQ13

27

VSS14

29

DQ9

31

VSS16 DM1_n/DBI_n33DQS1_t

35

VSS17

37

DQ15

39

VSS19

41

DQ10

43

VSS21

45

DQ21

47

VSS23

49

DQ17

51

VSS25 DQS2_c53DM2_n/DBI2_n

55

DQS2_t

57

VSS28

59

DQ23

61

VSS30

63

DQ19

65

VSS32

67

DQ29

69

VSS34

71

DQ25

73

VSS36 DM3_n/DBI3_n75DQS3_t

77

VSS37

79

DQ30

81

VSS39

83

DQ26

85

VSS41

87

CB5/NC

89

VSS43

91

CB1/NC

93

VSS45 DQS8_c95DM8_n/DBI_n/NC

97

DQS8_t

99

VSS48

101

CB2/NC

103

VSS50

105

CB3/NC

107

VSS52

109

CKE0

111

VDD1

113

BG1

115

BG0

117

VDD3

119

A12

121

A9

123

VDD5

125

A8

127

A6

129

VDD7

131

A3

133

A1

135

VDD9

137

CK0_t

139

CK0_c

141

VDD11

143

PARITY

145

BA1

147

VDD13

149

CS0_n

151

WE_n/A14

153

VDD15

155

ODT0

157

CS1_n

159

VDD17

161

ODT1

163

VDD19

165

C1, CS3_n,NC

167

VSS53

169

DQ37

171

VSS55

173

DQ33

175

VSS57

177

DQS4_c

179

DQS4_t

181

VSS60

183

DQ38

185

VSS62

187

DQ34

189

VSS64

191

DQ44

193

VSS66

195

DQ40

197

VSS68

199

DM5_n/DBI5_n

201

VSS69

203

DQ46

205

VSS71

207

DQ42

209

VSS73

211

DQ52

213

VSS75

215

DQ49

217

VSS77

219

DQS6_c

221

DQS6_t

223

VSS80

225

DQ55

227

VSS82

229

DQ51

231

VSS84

233

DQ61

235

VSS86

237

DQ56

239

VSS88

241

DM7_n/DBI7_n

243

VSS89

245

DQ62

247

VSS91

249

DQ58

251

VSS93

253

SCL

255

VDDSPD

257

VPP1

259

VPP2

261

GND1

263

NPTH1

ADDR0206-P0 01A02

CONN@

SP07001 CY0L

EVENT_n/NF

RAS_n/A16

CAS_n/A15

C0/CS2_n/NC

DM4_n/DBI4_n

DM6_n/DBI6_n

DDR_B_BA1<8,25>

DDR_B_MA1 4<8, 25>

+2.5V_MEM

DDR_B_D5

DDR_B_D0

DDR_B_DQS# 0 DDR_B_DQS0

DDR_B_D2

DDR_B_D7

DDR_B_D8

DDR_B_D14

DDR_B_D11

DDR_B_D15

DDR_B_D17

DDR_B_D16

DDR_B_DQS# 2 DDR_B_DQS2

DDR_B_D23

DDR_B_D21

DDR_B_D28

DDR_B_D27

DDR_B_D26

DDR_B_D24

DDR_B_CB4

DDR_B_CB2

DDR_B_DQS# 8 DDR_B_DQS8

DDR_B_CB7

DDR_B_CB5

DDR_B_CKE 0

DDR_B_BG1 DDR_B_BG0

DDR_B_MA1 2 DDR_B_MA9

DDR_B_MA8 DDR_B_MA6

DDR_B_MA3 DDR_B_MA1

DDR_B_CLK 0 DDR_B_CLK #0

DDR_B_PAR ITY

DDR_B_BA1

DDR_B_CS# 0 DDR_B_MA1 4

DDR_B_ODT0 DDR_B_CS# 1

DDR_B_ODT1

1

T53PAD~D @

DDR_B_D38

DDR_B_D39

DDR_B_DQS# 4 DDR_B_DQS4

DDR_B_D36

DDR_B_D37

DDR_B_D44

DDR_B_D45

DDR_B_D47

DDR_B_D43

DDR_B_D51

DDR_B_D54

DDR_B_DQS# 6 DDR_B_DQS6

DDR_B_D53

DDR_B_D49

DDR_B_D59

DDR_B_D62

DDR_B_D58

DDR_B_D63

+3.3V_RUN_ DIMM4

DDR_B_CB[0 ..7]<8,25>

DDR_B_DQS# [0..7]<8 ,25>

DDR_B_DQS[0 ..7]< 8,25>

DDR_B_D[0..6 3]<8,25>

D D

C C

B B

A A

DDR_B_MA[ 0..13]<8,25>

DIMM Select

SA0 SA1

DIMM2

DIMM4

*

DIMM1

DIMM3

+2.5V_MEM

1U_0201_10V6M

1

CD100

2

downsize

+1.2V_MEM

10U_0603_6.3V6M

CD104

1

2

1U_0201_10V6M

1

CD114

2

downsize

Layout Note: Place near JDIMM4.258

+0.6V_DDR_ VTT

SA2

0

0 1

0

1

0

1 1

10U_0603_6.3V6M

1U_0201_10V6M

10U_0603_6.3V6M

1

CD102

CD101

CD103

2

10U_0603_6.3V6M

CD108

CD106

CD107

CD105

1

2

1U_0201_10V6M

1

CD115

2

10U_0603_6.3V6M

CD122

1

2

1

2

1U_0201_10V6M

1

2

1

2

downsize

12

1 2

CD116

1U_0201_10V6M

CD123

@

0_0402_5%

@

0_0402_5%

1

2

1U_0201_10V6M

1

CD118

CD117

2

1U_0201_10V6M

1

CD124

2

@

RD88

RD46

0_0402_5%

1 2

12

RD51

@

RD89

0_0402_5%

10U_0603_6.3V6M

1U_0201_10V6M

CD119

+3.3V_RUN+3 .3V_RUN+3.3V_RU N

CD109

1

2

1

2

12

1 2

10U_0603_6.3V6M

CD110

1

2

1U_0201_10V6M

1

CD120

2

+V_DDR_RE FCA_B

RD48

@

0_0402_5%

DIMM4_SA0 DIMM4_SA1 DIMM4_SA2

@

RD90

0_0402_5%

330U_D2_2V_Y

@

1

CD112

CD111

+

2

CD121

0.1U_0402_10V6K

2.2U_0402_6.3V6M

@

1

CD125

CD126

2

+3.3V_RUN

RD94

@

0_0603_5%

1 2

+3.3V_RUN_ DIMM4

0.1U_0402_10V6K

2.2U_0603_10V7K

1

CD128

CD127

2

DDR_B_CB4<8, 25>

DDR_B_CB2<8, 25>

DDR_B_DQS# 8<8,25> DDR_B_DQS8<8,25>

DDR_B_CB7<8, 25>

DDR_B_CB5<8, 25>

DDR_B_CKE 0<8>

DDR_B_BG1<8,25> DDR_B_BG0<8,25>

DDR_B_CLK 0<8> DDR_B_CLK #0<8>

DDR_B_PAR ITY<8,25>

DDR_B_CS# 0<8>

DDR_B_ODT0<8>

DDR_B_CS# 1<8>

DDR_B_ODT1<8>

DDR_XDP_W AN_SMB CLK< 7,18,23,24,25, 54>

VSS2

VSS4

VSS6

VSS7

VSS9

VSS11

DQ12

VSS13

VSS15

DQS1_c

VSS18

DQ14

VSS20

DQ11

VSS22

DQ20

VSS24

DQ16

VSS26

VSS27

DQ22

VSS29

DQ18

VSS31

DQ28

VSS33

DQ24

VSS35

DQS3_c

VSS38

DQ31

VSS40

DQ27

VSS42

CB4/NC

VSS44

CB0/NC

VSS46

VSS47

CB6/NC

VSS49

CB7/NC

VSS51

RESET_n

CKE1 VDD2

ACT_n

ALERT_n

VDD4

VDD6

VDD8

VDD10

CK1_t/NF

CK1_c/NF

VDD12

A10/AP

VDD14

VDD16

VDD18

VREFCA

VSS54

DQ36

VSS56

DQ32

VSS58

VSS59

DQ39

VSS61

DQ35

VSS63

DQ45

VSS65

DQ41

VSS67 DQS5_c DQS5_t

VSS70

DQ47

VSS72

DQ43

VSS74

DQ53

VSS76

DQ48

VSS78

VSS79

DQ54

VSS81

DQ50

VSS83

DQ60

VSS85

DQ57

VSS87 DQS7_c DQS7_t

VSS90

DQ63

VSS92

DQ59

VSS94

GND2

NPTH2

+1.2V_MEM

2

DDR_B_D4

4

DQ4

6

DDR_B_D1

8

DQ0

10 12 14

DDR_B_D6

16

DQ6

18

DDR_B_D3

20

DQ2

22

DDR_B_D10

24 26

DDR_B_D9

28

DQ8

30

DDR_B_DQS# 1

32

DDR_B_DQS1

34 36

DDR_B_D12

38 40

DDR_B_D13

42 44

DDR_B_D18

46 48

DDR_B_D22

50 52 54 56

DDR_B_D19

58 60

DDR_B_D20

62 64

DDR_B_D25

66 68

DDR_B_D30

70 72

DDR_B_DQS# 3

74

DDR_B_DQS3

76 78

DDR_B_D29

80 82

DDR_B_D31

84 86

DDR_B_CB1

88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120

A11

122

A7

124 126

A5

128

A4

130 132

A2

134 136 138 140 142 144

A0

146 148 150

BA0

152 154 156 158

A13

160 162 164 166

SA2

168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 206 208 210 212 214 216 218 220 222 224 226 228 230 232 234 236 238 240 242 244 246 248 250 252 254

SDA

256

SA0

258

VTT

260

SA1

262

264

DDR_B_CB3

DDR_B_CB6

DDR_B_CB0

DDR_B_DRA MRST# DDR_B_CKE 1

DDR_B_ACT# DDR_B_ALE RT#

DDR_B_MA1 1 DDR_B_MA7

DDR_B_MA5 DDR_B_MA4

DDR_B_MA2 JDIMM4_EVE NT#

DDR_B_CLK 1 DDR_B_CLK #1

DDR_B_MA0

DDR_B_MA1 0

DDR_B_BA0 DDR_B_MA1 6

DDR_B_MA1 5 DDR_B_MA1 3

1

DIMM4_SA2

DDR_B_D35

DDR_B_D34

DDR_B_D33

DDR_B_D32

DDR_B_D40

DDR_B_D41

DDR_B_DQS# 5 DDR_B_DQS5

DDR_B_D42

DDR_B_D46

DDR_B_D48

DDR_B_D52

DDR_B_D50

DDR_B_D55

DDR_B_D57

DDR_B_D61

DDR_B_DQS# 7 DDR_B_DQS7

DDR_B_D56

DDR_B_D60

DIMM4_SA0

DIMM4_SA1

DDR_B_CB1 <8,25>

DDR_B_CB3 <8,25>

DDR_B_CB6 <8,25>

DDR_B_CB0 <8,25>

1 2

CD113 0.1U_02 01_10V6K@

DDR_B_CKE 1 <8>

DDR_B_ACT# <8,25> DDR_B_ALE RT# <8,25>

DDR_B_CLK 1 <8> DDR_B_CLK #1 <8>

DDR_B_BA0 < 8,25> DDR_B_MA1 6 <8,2 5>

DDR_B_MA1 5 <8,2 5>

+V_DDR_RE FCA_B

T52 PAD ~D@

+V_DDR_RE FCA_B

DDR_XDP_W AN_SMB DAT <7,18,2 3,24,25,54>

+0.6V_DDR_ VTT

CPU

B A

REV

JDIMM4

RD45 1K_0402 _5%@

D

C

CH-ACH-B

JDIMM1JDIMM3

DDR_B_DRA MRST#

STD

JDIMM2

B

A

H_THERMTRIP#JDIMM4_EVEN T#

REVSTD

-->CKE0,1

Top Side

Bottom Side

DDR_B_DRA MRST# < 23,25>

-->CKE0,1

-->CKE2,3 -->CKE2,3

1 2

H_THERMTRIP# <7,14,23,24,25,59 >

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2016/01/01

Compal Secret Data

Deciphered Date

2

2017/01/01

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

DDR4_DIMM4

Size Docum ent Number Rev

Custom

LA-H271P

Tuesday, April 09, 2019

Date: Sheet of

1

26 103

1.0

5

40mil(1A)

+5V_DGFF

0.1U_0201_16V6K

82P_0402_50V8J

RF@

1

CV957

2

D D

100mil(2.5A, 5VIA)

+3.3V_DGFF

JDG1

CV806

1

CV805

1

2

1

CV903

CV902

2

0.1U_0201_10V6K

10U_0402_6.3V6M

CONN@

GND_1 GND_2 GND_3 GND_4

1

2

3

4

5

6 7 8 9

82P_0402_50V8J

RF@

CV956

BELLW _80252-0521

2 DP channels from GPU

4

+DGFF_PW R_SRC

+3.3V_DGFF

Cancel double pull high

1 2

RV806 10K_0402_5%@

1 2

RV807 10K_0402_5%@

DGPU_PW ROK

DGFF_CLK_RE Q#

DGFF_ALERT#

3

+3.3V_DGFF

10K_0402_5%

RV803

+3.3V_RUN

12

DGPU_PEX_RST#

G

2

13

D

S

QV41 L2N7002W T1G_SC-70-3

change SB00000UO00 to SB000009Q80/ SB00000ST00 as main source, SB00000UO00 as 3rd source

100K_0402_5%

12

RV904

DGPU_ALERT# <5 9>

GPU_SMBDA T_R

GPU_SMBCL K_R

2

+3.3V_DGFF

4.7K_0402_5%

12

@

RV804

4.7K_0402_5%

12

@

RV805

S

QV30B 2N7002KDW _SOT363-6

+3.3V_DGFF

S

G

5

34

D

G

2

61

D

QV30A

2N7002KDW _SOT363-6

CLKREQ_PE G#0<16>

GPU_SMDAT <58>

GPU_SMCLK <58>

1

CLKREQ_PE G#0

L2N7002W T1G_SC-70-3

DGPU_PWROK

2

G

DGFF_CLK_RE Q#

1 3

D

S

QV42

change SB00000UO00 to SB000009Q80/ SB00000ST00 as main source, SB00000UO00 as 3rd source

( A & B & EDP)

PCIe x8 Lanes 0-7

PEG_CRX_C_ GTX_P7 PEG_CRX_C_ GTX_N7

PEG_CRX_C_ GTX_P6 PEG_CRX_C_ GTX_N6

PEG_CRX_C_ GTX_P5 PEG_CRX_C_ GTX_N5

PEG_CRX_C_ GTX_P4 PEG_CRX_C_ GTX_N4

PEG_CRX_C_ GTX_P3 PEG_CRX_C_ GTX_N3

PEG_CRX_C_ GTX_P1 PEG_CRX_C_ GTX_N1

GPU_SMBCL K_R GPU_SMBDA T_R

PEG_CRX_C_ GTX_P2 PEG_CRX_C_ GTX_N2

PEG_CRX_C_ GTX_P0 PEG_CRX_C_ GTX_N0 DGFF_CLK_RE Q#

DGFF_ENVDD< 38>

DGFF_PANEL_ BKEN<3 8>

+5V_DGFF +3.3V_DGFF

DV43

DV32

DV33

DGPU_HOLD_R ST# < 19>

PLTRST_GPU# <17>

5

4

M74VHC1GT125 DF2G_SC70-5

12

ACAV_IN<58 ,62,85>

UV68

1

OE

Vcc

2

IN A

GND3OUT Y

3

PEG_CRX_GTX_ P[0..15]<6>

PEG_CRX_GTX_ N[0..15]<6>

A1 A2 A3 A4 A5 A6 A7 A8 A9

A10

B1 B2 B3 B4 B5 B6 B7 B8 B9

B10

C1 C2 C3 C4 C5 C6 C7 C8 C9

C10

D1 D2 D9

D10

1 2

PEG_CTX_C_GRX _P[0..15]< 6>

PEG_CTX_C_GRX _N[0..15]<6>

JDGFF1

P

A1

N

A2

G

A3

P

A4

N

A5

G

A6

P

A7

N

A8

G

A9 A10

B1

P

B2

N

B3

G

B4

P

B5

N

B6

G

B7

P

B8

N

B9

G

B10

P

C1

N

C2

G

C3

P

C4

N

C5

G

C6

P

C7

N

C8 C9 C10

D1 D2 D9 D10

NPTH1

NPTH3

NPTH2

NPTH4

UNIMI_FBGCAX01 1

CONN@

PEG_CRX_C_ GTX_P0

PEG_CRX_C_ GTX_N0

PEG_CRX_C_ GTX_N1

PEG_CRX_C_ GTX_P2

PEG_CRX_C_ GTX_N2

PEG_CRX_C_ GTX_P3

PEG_CRX_C_ GTX_N3

PEG_CRX_C_ GTX_P4 PEG_CRX_C_ GTX_N4

PEG_CRX_C_ GTX_P5 PEG_CRX_C_ GTX_N5

PEG_CRX_C_ GTX_P6 PEG_CRX_C_ GTX_N6

PEG_CRX_C_ GTX_P7 PEG_CRX_C_ GTX_N7

PEG_CRX_C_ GTX_P8 PEG_CRX_C_ GTX_N8

PEG_CRX_C_ GTX_P9 PEG_CRX_C_ GTX_N9

PEG_CRX_C_ GTX_P10 PEG_CRX_C_ GTX_N10

PEG_CRX_C_ GTX_P11 PEG_CRX_C_ GTX_N11

PEG_CRX_C_ GTX_P12 PEG_CRX_C_ GTX_N12

PEG_CRX_C_ GTX_P13 PEG_CRX_C_ GTX_N13

PEG_CRX_C_ GTX_P14 PEG_CRX_C_ GTX_N14

PEG_CRX_C_ GTX_P15 PEG_CRX_C_ GTX_N15

H1

P

H1

H2

N

H2

H3

G

H3

H4

P

H4

H5

N

H5

H6

G

H6

H7

P

H7

H8

N

H8

H9

G

H9

H10

G1

GG

G1

G2

P

G2

G3

N

G3

G4

G

G4

G5

P

G5

G6

N

G6

G7

G

G7

G8

P

G8

G9

N

G9

G10

G

G10

F1

P

F1

F2

N

F2

F3

G

F3

F4

P

F4

F5

N

F5

F6

G

F6

F7

P

F7

F8

N

F8

F9

F10

E1

E2

E9

E10

3 4

GPU_DP2_P1 GPU_DP2_N1

GPU_DP2_P2 GPU_DP2_N2

GPU_DP2_HP D_GATE

GPU_DP1_P2 GPU_DP1_N2

GPU_DP1_P3 GPU_DP1_N3

GPU_EDP_P 0 GPU_EDP_N0

DGPU_PEX_ RST#

GPU_DP1_AU XP GPU_DP1_AU XN

GPU_DP1_P0 GPU_DP1_N0

GPU_EDP_HP D

PEG_CRX_GTX_ P[0..15]

PEG_CRX_GTX_ N[0..15]

PEG_CTX_C_GRX _P[0..15]

PEG_CTX_C_GRX _N[0..15]

GPU_EDP_HP D <29>

DGPU_PEX_ RST#

12

DGFF_PW R_LEVEL

4

GPU_DP2_P1 <3 1> GPU_DP2_N1 < 31>

GPU_DP2_P2 <3 1> GPU_DP2_N2 < 31>

CLK_PEG_P 0 <16> CLK_PEG_N0 <16>

GPU_DP1_P2 <3 1>

GPU_DP1_N2 <31>

GPU_DP1_P3 <31> GPU_DP1_N3 < 31>

GPU_EDP_P 0 <29> GPU_EDP_N0 < 29>

GPU_DP1_AU XP <3 1> GPU_DP1_AU XN <31>

GPU_DP1_P0 <3 1>

GPU_DP1_N0 <31>

DGPU_PW ROK <18,58>

PCIE_WA KE# <42 ,52,59,67,68>

+3.3V_ALW

4

100K_0402_5%

O

RV813

+3.3V_ALW _R

+3.3V_DGFF

12

RV819

4.7K_0402_5%

4

Y

UV60

MC74VHC1G0 9DFT2G_SC70-5

DGFF_IFP_HPD

GPU_DP1_HP D

GPU_DP2_HP D

CV810

@

1 2

0.1U_0201_1 0V6K

5

1

P

IN1

2

IN2

G

UV63

3

SN74AHC1G0 8DCKR_SC70-5

CV811

@

1 2

0.1U_0201_1 0V6K

5

1

B

VCC

2

A

G

change net name

3

2 1

RB751VM-40 TE-17_SOD323-2

2 1

RB751VM-40 TE-17_SOD323-2

2 1

RB751VM-40 TE-17_SOD323-2

100K_0402_5%

12

RV821

10K_0402_5%

GPU_PW R_LEVEL <58>

RV812

GPU_DP1_P1<31> GPU_DP1_N1<31>

GPU_DP2_AU XP<31>

GPU_DP2_AU XN<31>

GPU_DP2_P0<31> GPU_DP2_N0<3 1>

GPU_EDP_P 1<2 9> GPU_EDP_N1<29>

GPU_DP2_P3<31>

GPU_DP2_N3<31>

C C

HDR monitor for AMD/NV/UMA edp output detect 1/29

GPU_EDP_A UXP<29> GPU_EDP_A UXN<29>

GPU_EDP_P 3< 29> GPU_EDP_N3<29>

GPU_EDP_P 2<2 9>

GPU_EDP_N2<29>

DGFF_VGA_DIS#<59> DGPU_TYPE#<38>

X-Beam I/per pi n=0.5A I/per connector =0.75A

TBT/DP MUX1

TBT/DP MUX2

eDP MUX

B B

PEG_CRX_GTX_ P0 PEG_CRX_GTX_ N0

PEG_CRX_GTX_ P1 PEG_CRX_C_ GTX_P1 PEG_CRX_GTX_ N1

PEG_CRX_GTX_ P2 PEG_CRX_GTX_ N2

PEG_CRX_GTX_ P3 PEG_CRX_GTX_ N3

PEG_CRX_GTX_ P4 PEG_CRX_GTX_ N4

PEG_CRX_GTX_ P5 PEG_CRX_GTX_ N5

PEG_CRX_GTX_ P6 PEG_CRX_GTX_ N6

PEG_CRX_GTX_ P7 PEG_CRX_GTX_ N7

PEG_CRX_GTX_ P8 PEG_CRX_GTX_ N8

PEG_CRX_GTX_ P9 PEG_CRX_GTX_ N9

PEG_CRX_GTX_ P10 PEG_CRX_GTX_ N10

PEG_CRX_GTX_ P11 PEG_CRX_GTX_ N11

PEG_CRX_GTX_ P12

A A

PEG_CRX_GTX_ N12

PEG_CRX_GTX_ P13 PEG_CRX_GTX_ N13

PEG_CRX_GTX_ P14 PEG_CRX_GTX_ N14

PEG_CRX_GTX_ P15 PEG_CRX_GTX_ N15

5

GPU_DP1_P1 GPU_DP1_N1 PEG_CTX_C_GRX _N13

GPU_DP2_AU XP GPU_DP2_AU XN

GPU_DP2_P0 GPU_DP2_N0

DGFF_ALERT#

GPU_EDP_P 1 GPU_EDP_N1

GPU_DP2_P3 GPU_DP2_N3

GPU_EDP_A UXP GPU_EDP_A UXN

DGFF_OVERT# DGFF_IFP_HPD

GPU_EDP_P 3 GPU_EDP_N3

GPU_EDP_P 2 GPU_EDP_N2 GPU_DP1_HP D_GATE

+5V_DGFF +3.3V_DGFF

PortA

PortB

PortC

12

CV427 0.2 2U_0201_6.3V 6K

12

CV428 0.22U_0201_6.3V6K

12

CV429 0.2 2U_0201_6.3V 6K

12

CV430 0.22U_0201_6.3V6K

12

CV431 0.2 2U_0201_6.3V 6K

12

CV432 0.22U_0201_6.3V6K

12

CV433 0.2 2U_0201_6.3V 6K

12

CV434 0.22U_0201_6.3V6K

12

CV435 0.2 2U_0201_6.3V 6K

12

CV436 0.22U_0201_6.3V6K

12

CV437 0.2 2U_0201_6.3V 6K

12

CV438 0.22U_0201_6.3V6K

12

CV439 0.2 2U_0201_6.3V 6K

12

CV440 0.22U_0201_6.3V6K

12

CV441 0.2 2U_0201_6.3V 6K

12

CV442 0.22U_0201_6.3V6K

12

CV443 0.2 2U_0201_6.3V 6K

12

CV444 0.22U_0201_6.3V6K

12

CV445 0.2 2U_0201_6.3V 6K

12

CV446 0.22U_0201_6.3V6K

12

CV447 0.2 2U_0201_6.3V 6K

12

CV448 0.22U_0201_6.3V6K

12

CV449 0.2 2U_0201_6.3V 6K

12

CV450 0.22U_0201_6.3V6K

12

CV451 0.2 2U_0201_6.3V 6K

12

CV452 0.22U_0201_6.3V6K

12

CV453 0.2 2U_0201_6.3V 6K

12

CV454 0.22U_0201_6.3V6K

12

CV455 0.2 2U_0201_6.3V 6K

12

CV456 0.22U_0201_6.3V6K

12

CV457 0.2 2U_0201_6.3V 6K

12

CV458 0.22U_0201_6.3V6K

DGFF_DP_HDM I_HPD < 58>

100K_0402_5%

RV905

+1.0V_VCCST+3.3V_ALW _R

10K_0402_5%

RV820

JDGFF2

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

B1

B2

B3

B4

B5

B6

B7

B8

B9

B10

C1

C2

C3

G

C3

C4

C5

C6

C7

C8

C9

C10

D1

D2

D9

D10

1

NPTH1

2

NPTH2

UNIMI_FBGCAX01 1

CONN@

12

5

4

74AUP1G07GW _TSSOP5

PEG_CTX_C_GRX _P3

H1

P

H1

PEG_CTX_C_GRX _N3

H2

N

H2

H3

G

H3

PEG_CTX_C_GRX _P1

H4

P

H4

PEG_CTX_C_GRX _N1

H5

N

H5

H6

G

H6

PEG_CTX_C_GRX _P0

H7

P

H7

PEG_CTX_C_GRX _N0

H8

N

H8

H9

G

H9

DGFF_PW R_LEVEL

H10

G1

GG

G1

PEG_CTX_C_GRX _P5

G2

P

G2

PEG_CTX_C_GRX _N5

G3

N

G3

G4

G

G4

PEG_CTX_C_GRX _P2

G5

P

G5

PEG_CTX_C_GRX _N2

G6

N

G6

G7

G

G7

PEG_CTX_C_GRX _P4

G8

P

G8

PEG_CTX_C_GRX _N4

G9

N

G9

G10

G

G10

F1

P

F1

F2

N

F2

F3

G

F3

PEG_CTX_C_GRX _P6

F4

P

F4

PEG_CTX_C_GRX _N6

F5

N

F5

F6

G

F6

PEG_CTX_C_GRX _P7

F7

P

F7

PEG_CTX_C_GRX _N7

F8

N

F8

MACO_EN

F9

GPU_GC6_FB_ EN_R

F10

E1

E2

E9

E10

3

NPTH3

4

NPTH4

UV69

VCC

Y

DGPU_PEX_ RST# D GPU_PEX_RS T#_D DGPU_PW ROK

1

NC

2

PROCHOT# <7,58,8 2,85,90>

A

3

GND

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

VGA_IDENTIFY <28, 58>

DGPU_PW R_EN_R <59>

MACO_EN < 18>

1 2

@

RV485 0_0402_5%

DGFF_BIA_PW M <38>

2 1

DV44

RB751VM-40 TE-17_SOD323-2

GPU_DP2_HP D_GATE

DV34

@

RB751VM-40 TE-17_SOD323-2

GPU_GC6_FB_ EN <14 >

FOR NV GC6_FB_EN

GPU_EVENT# <14>

+3.3V_DGFF

5

IN1

4

O

IN2

3

21

2016/01/01

DGPU_PEX_ RST#_D

1

P

2

G

UV61

SN74AHC1G0 8DCKR_SC70-5

12

1

2

Compal Secret Data

Deciphered Date

2

10K_0402_5%

1000P_0402_50V7K

PCIe x8 Lanes 8-15

PEG_CTX_C_GRX _P13

PEG_CTX_C_GRX _P15 PEG_CTX_C_GRX _N15

PEG_CTX_C_GRX _P14 PEG_CTX_C_GRX _N14

PEG_CTX_C_GRX _P10 PEG_CTX_C_GRX _N10

PEG_CTX_C_GRX _P11 PEG_CTX_C_GRX _N11

PEG_CTX_C_GRX _P12 PEG_CTX_C_GRX _N12

PEG_CTX_C_GRX _P9 PEG_CTX_C_GRX _N9

PEG_CTX_C_GRX _P8 PEG_CTX_C_GRX _N8

@

RV815

@

1 2

RV800

0_0402_5%

@

CV812

2017/01/01

JDGFF3

A1

P

A1

A2

N

A2

A3

G

A3

A4

P

A4

A5

N

A5

A6

G

A6

A7

P

A7

A8

N

A8

A9

G

A9

A10

B1

B2

P

B2

B3

N

B3

B4

G

B4

B5

P

B5

B6

N

B6

B7

G

B7

B8

P

B8

B9

N

B9

B10

G

B10

C1

P

C1

C2

N

C2

C3

G

C3

C4

P

C4

C5

N

C5

C6

G

C6

C7

P

C7

C8

N

C8

C9

C10

D1

D2

D9

D10

1

NPTH1

2

NPTH2

UNIMI_FBGCAX01 1

CONN@

GPU_DP1_HP D_GATE

100K_0402_5%

12

RV818

PEG_CRX_C_ GTX_P10

H1

P

H1

PEG_CRX_C_ GTX_N10

H2

N

H2

H3

G

H3

PEG_CRX_C_ GTX_P9

H4

P

H4

PEG_CRX_C_ GTX_N9

H5

N

H5

H6

G

H6

PEG_CRX_C_ GTX_P8

H7

P

H7

PEG_CRX_C_ GTX_N8

H8

N

H8

H9

G

H9

H10

G1

GG

G1

PEG_CRX_C_ GTX_P12

G2

P

G2

PEG_CRX_C_ GTX_N12

G3

N

G3

G4

G

G4

PEG_CRX_C_ GTX_P11

G5

P

G5

PEG_CRX_C_ GTX_N11

G6

N

G6

G7

G

G7

PEG_CRX_C_ GTX_P13

G8

P

G8

PEG_CRX_C_ GTX_N13

G9

N

G9

G10

G

G10

F1

P

F1

F2

N

F2

F3

G

F3

PEG_CRX_C_ GTX_P14

F4

P

F4

PEG_CRX_C_ GTX_N14

F5

N

F5

F6

G

F6

PEG_CRX_C_ GTX_P15

F7

P

F7

PEG_CRX_C_ GTX_N15

F8

N

F8

F9

F10

E1

E2

E9

E10

3

NPTH3

4

NPTH4

+3.3V_DGFF

CV809

@

1 2

0.1U_0201_1 0V6K

5

DGPU_PEX_ RST#_D

1

P

IN1

4

O

2

IN2

G

UV62

3

SN74AHC1G0 8DCKR_SC70-5

+3.3V_DGFF

10K_0402_5%

12

RV816

DGPU_PEX_RST#

DGFF_OVERT#

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Docum ent Number Rev

Custom

Date: Sheet of

G

S

QV40 L2N7002W T1G_SC-70-3

change SB00000UO00 to SB000009Q80/ SB00000ST00 as main source, SB00000UO00 as 3rd source

Compal Electronics, Inc.

DGFF CONN.

LA-H271P

Tuesday, April 09, 2019

GPU_DP1_HP D <31>GPU_DP2_HP D <31>

+3.3V_ALW+3.3V_DGFF

10K_0402_5%

12

RV817

2

13

THERMTRIP1# <58>

D

27 103

1

27 103

1.0

5

4

3

2

1

D D

CPU_DP3_P0<9> CPU_DP3_N0<9>

CPU_DP3_P1<9>

CPU

HDMI2.0

C C

PS8338

B B

mDP

CPU_DP3_N1<9>

CPU_DP3_P2<9> CPU_DP3_N2<9>

PCH_DPD_HPD<19>

CPU_DP3_P3<9> CPU_DP3_N3<9>

CPU_DP3_AUXP<9>

CPU_DP3_AUXN<9>

SW2_DP2_ 2_P0<30>

SW2_DP2_ 2_N0<30>

SW2_DP2_ 2_HPD<30>

SW2_DP2_ 2_P1<30>

SW2_DP2_ 2_N1<30>

SW2_DP2_ 2_P2<30>

SW2_DP2_ 2_N2<30>

+3.3V_RU N +3.3V_RU N

UMA DGFF CON.

CPU_DP3 _P0 CPU_DP3 _N0

CPU_DP3 _P1 CPU_DP3 _N1

CPU_DP3 _P2 CPU_DP3 _N2

CPU_DP3 _P3 CPU_DP3 _N3

JDGFF4

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

B1

B2

B3

B4

B5

B6

B7

B8

B9

B10

C1

C2

C3

C4

C5

C6

C7

C8

C9

C10

D1

D2

D9

D10

1

NPTH1

2

NPTH2

UNIMI_FBGCAX 011

CONN@

P N G P N G P N G

P N

G

P N G P N

NPTH3 NPTH4

H1

P

H1

H2

N

H2

H3

G

H3

H4

P

H4

H5

N

H5

H6

G

H6

H7

P

H7

H8

N

H8

H9

G

H9

H10

G1

GG

G1

G2

P

G2

G3

N

G3

G4

G

G4

G5

P

G5

G6

N

G6

G7

G

G7

G8

P

G8

G9

N

G9

G10

G

G10

F1

P

F1

MDP_CA_ DET

F2

N

F2

F3

G

F3

F4

P

F4

F5

N

F5

F6

G

F6

F7

P

F7

F8

N

F8

F9

F10

E1

E2

E9

E10

3 4

VGA_IDENTIFY <27,58>

MDP_CA_DET <30>

SW2_DP2_ 2_AUXP <30> SW2_DP2_ 2_AUXN <30>

SW2_DP2_ 2_P3 <30> SW2_DP2_ 2_N3 <3 0>

+3.3V_RU N

+5V_RUN+3.3V_RU N

A A

Security Class ification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2016/01/ 01

3

Compal Secret Data

Deciphered Date

2017/01/ 01

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

DGFF CONN.

Size Doc ument Number Rev

Custom

LA-H271P

Tuesday, April 09, 2019

Date: Sheet of

1

28 103

1.0

5

+3.3V_RUN

D D

EDP_TXP0<9> EDP_TXN0<9> EDP_TXP1<9> EDP_TXN1<9>

CPU

C C

DSC DGFF

EDP_TXP2<9> EDP_TXN2<9> EDP_TXP3<9> EDP_TXN3<9>

EDP_AUXP<9> EDP_AUXN<9>

GPU_EDP_P0<27> GPU_EDP_N0<27> GPU_EDP_P1<27> GPU_EDP_N1<27> GPU_EDP_P2<27> GPU_EDP_N2<27> GPU_EDP_P3<27> GPU_EDP_N3<27>

GPU_EDP_AUXP<27> GPU_EDP_AUXN<27>

EDP_TXP0 EDP_TXN0 EDP_TXP1 EDP_TXN1 EDP_TXP2 EDP_TXN2 EDP_TXP3 EDP_TXN3

EDP_AUXP EDP_AUXN

GPU_EDP_P0 GPU_EDP_N0 GPU_EDP_P1 GPU_EDP_N1 GPU_EDP_P2 GPU_EDP_N2 GPU_EDP_P3 GPU_EDP_N3

GPU_EDP_AUXP GPU_EDP_AUXN

1 2

CV829 0.1U_0201_10V6K

1 2

CV830 0.1U_0201_10V6K

1 2

CV831 0.1U_0201_10V6K

1 2

CV832 0.1U_0201_10V6K

1 2

CV833 0.1U_0201_10V6K

1 2

CV834 0.1U_0201_10V6K

1 2

CV835 0.1U_0201_10V6K

1 2

CV836 0.1U_0201_10V6K

1 2

CV837 0.1U_0201_10V6K

1 2

CV838 0.1U_0201_10V6K

1 2

CV819 0.1U_0201_10V6K

1 2

CV820 0.1U_0201_10V6K

1 2

CV821 0.1U_0201_10V6K

1 2

CV822 0.1U_0201_10V6K

1 2

CV823 0.1U_0201_10V6K

1 2

CV824 0.1U_0201_10V6K

1 2

CV825 0.1U_0201_10V6K

1 2

CV826 0.1U_0201_10V6K

1 2

CV827 0.1U_0201_10V6K

1 2

CV828 0.1U_0201_10V6K

4

4.7U_0402_6.3V6M

0.1U_0201_10V6K

1

CV813

CV814

2

CPU_EDP_HPD<19>

GPU_EDP_HPD<27>

1

2

0.1U_0201_10V6K

CV815

0.1U_0201_10V6K

1

CV816

2

EDP_IN2_PEQ EDP_IN1_PEQ EDP_IN1_AEQ# EDP_IN2_AEQ#

EDP_TXP0_C EDP_TXN0_C EDP_TXP1_C EDP_TXN1_C EDP_TXP2_C EDP_TXN2_C EDP_TXP3_C EDP_TXN3_C

EDP_AUXP_C EDP_AUXN_C

GPU_EDP_P0_C GPU_EDP_N0_C GPU_EDP_P1_C GPU_EDP_N1_C GPU_EDP_P2_C GPU_EDP_N2_C GPU_EDP_P3_C GPU_EDP_N3_C

GPU_EDP_AUXP_C GPU_EDP_AUXN_C

CPU_EDP_HPD GPU_EDP_HPD

0.1U_0201_10V6K 82P_0402_50V8J

RF@

1

CV817

CV955

2

UV64

21

VDD33_1

26

VDD33_2

35

VDD33_3

49

VDD33_4

60

VDD33_5

51

IN2_PEQ/SCL_CTL

52

IN1_PEQ/SDA_CTL

59

IN1_AEQ#

58

IN2_AEQ#

1

IN1_D0p

2

IN1_D0n

4

IN1_D1p

5

IN1_D1n

6

IN1_D2p

7

IN1_D2n

9

IN1_D3p

10

IN1_D3n

28

IN1_AUXp

27

IN1_AUXn

23

IN1_SCL

22

IN1_SDA

11

IN2_D0p

12

IN2_D0n

14

IN2_D1p

15

IN2_D1n

16

IN2_D2p

17

IN2_D2n

19

IN2_D3p

20

IN2_D3n

30

IN2_AUXp

29

IN2_AUXn

25

IN2_SCL

24

IN2_SDA

3

IN1_HPD

13

IN2_HPD

PN change to SA000060U10

3

OUT_AUXp_SCL OUT_AUXn_SDA

I2C_CTL_EN

PI0 PC0 PC1

CA_DET

OUT_D0p OUT_D0n OUT_D1p

OUT_D1n OUT2_D2p OUT2_D2n

OUT_D3p

OUT_D3n

SW

OUT_HPD

REXT CEXT

GND1 GND2 GND3 GND4 GND5

Epad

PS8331BQFN60GTR-A0_QFN60_5X9

PD

SW1_EDP_AUXP

32

SW1_EDP_AUXN

31

53

EDP_SW1_PI0

56

EDP_SW1_PC0

38

EDP_SW1_PC1

55

48

RV832 1M_0402_5%

SW1_EDP_P0

46

SW1_EDP_N0

45

SW1_EDP_P1

43

SW1_EDP_N1

42

SW1_EDP_P2

40

SW1_EDP_N2

39

SW1_EDP_P3

37

SW1_EDP_N3

36

54

SW1_EDP_HPD

44

SW1_REXT

34

SW1_CET

47

8 18 33 41 57 61 50

1 2

SW1_EDP_AUXP <38> SW1_EDP_AUXN <38>

SW1_EDP_HPD <38>

1 2

SW

H

(Default)

L

SW1_EDP_P0 <38> SW1_EDP_N0 <38> SW1_EDP_P1 <38> SW1_EDP_N1 <38> SW1_EDP_P2 <38> SW1_EDP_N2 <38> SW1_EDP_P3 <38> SW1_EDP_N3 <38>

RV835

4.99K_0402_1%

Input

IN2

IN1

2

eDP Conn

L2N7002WT1G_SC-70-3

change SB00000UO00 to SB000009Q80/ SB00000ST00 as main source, SB00000UO00 as 3rd source

QV43

+3.3V_RUN

12

10K_0402_5%

13

D

S

EDP_SW1_PC0

EDP_SW1_PC1

EDP_IN1_AEQ#

EDP_IN2_AEQ#

EDP_IN1_PEQ

EDP_IN2_PEQ

EDP_SW1_PI0

SW1_CET

EDP_SW1_PI0

EDP_SW1_PC0

EDP_SW1_PC1

EDP_IN1_PEQ

EDP_IN2_PEQ

+3.3V_RUN

RV900

2

G

DGPU_SELECT#: 0=DGFF ; 1=i-GPU

1 2

RV822 4.7K_0402_5%@

1 2

RV823 4.7K_0402_5%@

1 2

RV824 4.7K_0402_5%@

1 2

RV825 4.7K_0402_5%@

1 2

RV826 4.7K_0402_5%@

1 2

RV827 4.7K_0402_5%@

1 2

RV828 4.7K_0402_5%@

12

CV818 2.2U_0402_6.3V6M

1 2

RV829 4.7K_0402_5%@

1 2

RV830 4.7K_0402_5%@

1 2

RV831 4.7K_0402_5%@

1 2

RV833 4.7K_0402_5%@

1 2

RV834 4.7K_0402_5%@

8.2K_0402_5%

12

RV901

DGPU_SELECT# <38,59>

From EC

1

+3.3V_RUN

INy_PEQ = Programmable input equalization levels L: default, LEQ, compensate channel loss up to 11.5dB @ HBR2 H: HEQ, compensate channel loss up to 14.5dB @ HBR2 M: LLEQ, compensate channel loss up to 8.5dB @ HBR2

B B

A A

5

INy_AEQ# = Automatic EQ disable L: Automatic EQ enable (default) H: Automatic EQ disable

PI0 = Auto test enable L: Auto test disable & input offset cancellation enable (default) H: Auto test enable & input offset cancellation enable M: Auto test disable & input offset cancellation disable

PC0 = AUX interception disable L: AUX interception enable, driver configuration is set by link training (default) H: AUX interception disable, driver output with fixed 800mV and 0dB M: AUX interception disable, driver output with fixed 400mV and 0dB

PC1 = Output swing adjustment L: default H: +20% M: -16.7%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2016/01/01

Compal Secret Data

Deciphered Date

2

2017/01/01

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

eDP MUX (PS8331)

Size Document Number Rev

Custom

LA-H271P

Tuesday, April 09, 2019

Date: Sheet of

1

29 103

1.0

5

4

3

2

1

+3.3V_RUN

1 2

RV125 4.7K_0402_5%

D D

+3.3V_RUN

RV55

C C

RV56

B B

1 2

@

RV126 4.7K_0402_5%

1 2

RV127 4.7K_0402_5%

1 2

RV130 1M_0402_5%

1 2

RV131 1M_0402_5%

12

RV57

@

4.7K_0402_5%

12

RV58

@

4.7K_0402_5%

DP1_SW2_CFG0

DP1_SW2_SW

DP1_SW2_PI0

OUT1_CA_DET

MDP_CA_DET

CPU

12

RV59

RV61

@

4.7K_0402_5%

12

RV62

RV60

@

4.7K_0402_5%

12

RV65

RV63

@

4.7K_0402_5%

12

RV64

RV66

@

4.7K_0402_5%

DP1_SW2_PI1

DP1_SW2_PC10

DP1_SW2_PC11

DP1_SW2_PC20

DP1_SW2_PC21

12

4.7K_0402_5%

CPU_DP2_P0<9> CPU_DP2_N0<9>

CPU_DP2_P1<9> CPU_DP2_N1<9>

CPU_DP2_P2<9> CPU_DP2_N2<9>

CPU_DP2_P3<9> CPU_DP2_N3<9>

PCH_DPC_CTRL_CLK<19> PCH_DPC_CTRL_DATA<19>

CPU_DP2_AUXP<9> CPU_DP2_AUXN<9>

CPU_DP2_P0 CPU_DP2_N0

CPU_DP2_P1 CPU_DP2_N1

CPU_DP2_P2 CPU_DP2_N2

CPU_DP2_P3 CPU_DP2_N3

PCH_DPC_CTRL_CLK PCH_DPC_CTRL_DATA CPU_DP2_AUXP

Port switching control or priority configuration. Internal pull down ~150KΩ, 3.3V I/O For Control Switching Mode (CFG0 = L): SW = L: Port1 is selected (default) SW = H: Port2 is selected

For Automatic Switching Mode (CFG0 = H): (By OUT1_HPD and OUT2_HPD) SW = L: Port1 has higher priority when both ports are plugged (default)

SW = H: Port2 has higher priority when both ports are plugged

CV65 0.1U_0201_10V6K CV66 0.1U_0201_10V6K

CV67 0.1U_0201_10V6K CV68 0.1U_0201_10V6K

CV69 0.1U_0201_10V6K CV70 0.1U_0201_10V6K

CV71 0.1U_0201_10V6K CV72 0.1U_0201_10V6K

CV73 0.1U_0201_10V6K CV74 0.1U_0201_10V6K

CV62 CV90 close to pin30 &57 CV66,CV69,CV70 close to pin5,21,51

0.01U_0402_16V7K

12

CV61

CV60

1 2 1 2

PCH_DPC_HPD<19>

1 2 1 2

0.1U_0201_25V6K

12

CV62

CPU_DP2_P0_C CPU_DP2_N0_C

CPU_DP2_P1_C CPU_DP2_N1_C

CPU_DP2_P2_C CPU_DP2_N2_C

CPU_DP2_P3_C CPU_DP2_N3_C

CPU_DP2_AUXP_C CPU_DP2_AUXN_CCPU_DP2_AUXN

0.1U_0201_25V6K

12

CV63

DP1_SW2_PI1 DP1_SW2_PI0

DP1_SW2_CFG0

DP1_SW2_PC10 DP1_SW2_PC11 DP1_SW2_PC20 DP1_SW2_PC21

+3.3V_RUN

CV64

UV8

5

VDD33_1

21

VDD33_2

30

VDD33_3

51

VDD33_4

57

VDD33_5

6

IN_D0p

7

IN_D0n

9

IN_D1p

10

IN_D1n

12

IN_D2p

13

IN_D2n

15

IN_D3p

16

IN_D3n

4

IN_CA_DET

3

IN_HPD

2

I2C_CTL_EN

1

Pl1/SCL_CTL

60

Pl0/SDA_CTL

22

IN_DDC_SCL

23

IN_DDC_SDA

24

IN_AUXp

25

IN_AUXn

59

CFG0

58

CFG1

56

PC10

55

PC11

54

PC20

53

PC21

11

GND_1

19

GND_2

52

GND_3

61

PAD(GND)

PS8338BQFN60GTR-A1_QFN60_5X9

H L

CFG0

V

VSW

OUT1_D0p OUT1_D0n

OUT1_D1p OUT1_D1n

OUT1_D2p OUT1_D2n

OUT1_D3p OUT1_D3n

OUT2_D0p OUT2_D0n

OUT2_D1p OUT2_D1n

OUT2_D2p OUT2_D2n

OUT2_D3p OUT2_D3n

OUT1_AUXp_SCL

OUT1_AUXn_SDA

OUT2_AUXp_SCL

OUT2_AUXn_SDA

OUT1_CA_DET

OUT1_HPD

OUT2_CA_DET

OUT2_HPD

PEQ

CEXT REXT

SW

PD

50 49

47 46

45 44

42 41

40 39

37 36

35 34

32 31

26 27

28 29

43 48

33 38

18 8 14 17 20

DP1_SW2_SW DP1_SW2_PEQDP1_SW2_PEQ

RV50

SW2_DP2_1_P0 SW2_DP2_1_N0

SW2_DP2_1_P1 SW2_DP2_1_N1

SW2_DP2_1_P2 SW2_DP2_1_N2

SW2_DP2_1_P3 SW2_DP2_1_N3

SW2_DP2_1_AUXP

SW2_DP2_1_AUXN

OUT1_CA_DET SW2_DP2_1_HPD

MDP_CA_DET

2.2U_0402_6.3V6M

12

4.99K_0402_1%

SW2_DP2_1_P0 <31> SW2_DP2_1_N0 <31>

SW2_DP2_1_P1 <31> SW2_DP2_1_N1 <31>

SW2_DP2_1_P2 <31> SW2_DP2_1_N2 <31>

SW2_DP2_1_P3 <31> SW2_DP2_1_N3 <31>

SW2_DP2_2_P0 <28> SW2_DP2_2_N0 <28>

SW2_DP2_2_P1 <28> SW2_DP2_2_N1 <28>

SW2_DP2_2_P2 <28> SW2_DP2_2_N2 <28>

SW2_DP2_2_P3 <28> SW2_DP2_2_N3 <28>

SW2_DP2_1_AUXP <31> SW2_DP2_1_AUXN <31>

SW2_DP2_2_AUXP <28>

SW2_DP2_2_AUXN <28>

SW2_DP2_1_HPD <31>

MDP_CA_DET <28> SW2_DP2_2_HPD <28>

CV75

TBT/MUX2

UMA DGFF

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2016/01/01

Compal Secret Data

Deciphered Date

2

2017/01/01

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

DP DeMUX (PS8338)

Size Document Number Rev

Custom

LA-H271P

Tuesday, April 09, 2019

Date: Sheet of

1

30 103

1.0

Compal LA-H271P Schematics Rev1.0

Specifications and Main Features

Frequently Asked Questions

User Manual