Compal LA-H171P Schematics
5
smd.db-x7.ru
4
3
2
1
COMPAL CONFIDENTIAL
MODEL NAME : EDC42
D D
PCB NO : LA-H171P
BOM P/N :
GPIO MAP: X10_WHL_KBL_CFLH_GPIO map Rev1.5_20180921
PWR Circuit: 14UMA_A00_PWR_20190308A
Brook Hollow 14 UMA (TBT)
Cof f ee Lake H
2019-03-20
C C
REV : 1.0 (A00)
@ : Nopop Component
EMI@ : EMI Component
@EMI@ : EMI Nopop Component
ESD@ : ESD Component
@ESD@ : ESD Nopop Component
RF@ : RF Component
B B
@RF@ : RF Nopop Component
XDP@ : XDP Component
CONN@ : Connector Component
MB PCB
Part Number
DAA000J2000
Description
PCB 2FB LA-H171P REV0 MB 1
Layout Dell logo
A A
5105@ : EC MEC5105 IC
5106@ : EC MEC5106 IC
WWAN@ : WWAN Component
WWANRF@ : WWAN RF Component
SATAPERI@ : Pericom SATA repeater support
eSPI@ : eSPI interface
LPC@ : LPC interface
DS3@ : Deep sleep support
NDS3@ : non Deep sleep support
RTD3@ : RTD3 support
NRTD3@ : non RTD3 support
VPRO@ : VPRO support
NVPRO@ : non VPRO support
ST33@ : ST33 TPM support
750@ : NPCT750 TPM support
JUMP@ : Jump solder and short
@JUMP@ : Jump no solder
SATAPARA@ : Parade SATA repeater support
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Cover Sheet
Cover Sheet
Cover Sheet
Size
Size
Size
Document Number Re v
Document Number Re v
Document Number Re v
A
A
A
LA-H171P
LA-H171P
LA-H171P
Wednesday, March 20, 2019
Wednesday, March 20, 2019
Wednesday, March 20, 2019
Date : Sheet o f
Date : Sheet o f
Date : Sheet o f
1
1 100
1 100
1 100
0.1
0.1
0.1
COPYRIGHT 2019
ALL RIGHT RESERVED
REV: A00
PWB: J11RG
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
2018/01/01
2018/01/01
2018/01/01
3
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2020/01/01
2020/01/01
2020/01/01
2
5
smd.db-x7.ru
Brook Hollow 14 UMA TBT Block Diagram
4
3
2
1
Reverse Type
D D
EDP CONN
P38
eDP Lane x 2
eDP
Memory BUS (DDR4)
2400/2667 MHz
DDR4-SO-DIMM X2
BANK 0, 1, 2, 3
P.23/24
Intel
TBT_DP0
To AR
TBT_DP1
To AR
HDMI 2.0
CONN
C C
Card reader
RTS5242
SD4.0
PCIE[6]
P70
P70
Intel Jacksonville
WGI219LM(vpro)
WGI210V(non-vpro)
PCIE[1..4]
To AR
B B
TBT_DP0
TBT_DP1
P30~31
5
TBT
Port A
PCIE[1..4]
P46
TBT
AR-SP
USB2.0/SMB
AUX/POC
A A
I2C
PD
TPS65982DD
P44~45
SBU1/SBU2
CC1/CC2
USB3_TYPE C connector
DP1, DN1/DP2,DN2
P40
PCIE[5]
Transformer
RJ45
P51
P51
HDMI
P51
PCIE/USB3 Switch
PI3PCIE3212ZBEX
Smart Card
USH board(CV3)
4
DP to HDMI2.0
PS175
PCIE[17]
M.2,3042 Key B
WWAN/LTE
/HCA/SSD
USB2.0[8]
PCIE[18]
USB3.0[2]
TDA8034HN
RFID/NFC
Fingerprint
CONN
FPR IN PB MoCV
P52
P52
P40
PCIE[7]
M.2, 2230 Key E
WLAN+BT/CNVi
SPI
SPI
USB
DDI[1]
DDI[2]
DDI[3]
CNVi
P52
USB2.0[14]
USH
BCM58202
COFFEE LAKE-H
DDIB
BGA CPU
1440 Pins
DDIC
DDID
Intel
CannonLake-H
BGA PCH
874 Pins
SMSC KBC
MEC5106
USB2.0[10]
P66
3
eSPI
PAGE 6~13
USB2.0[1]
SLGC55544CVTR
USB POWER SHARE
DMI x4 Gen 3
USB
HD Audio I/F
PAGE 14~22
SATA[0]/PCIE[9..12]
SPI
P.58
SATA[2]
P.63
P.59
P.17
P.17
P.17
co- lay
P.66
2018/01/01
2018/01/01
2018/01/01
W25Q256JVEIQ
vPro use
256Mb 4K sector WSON8
W25Q64JVZEIQ
Non-vPro use
64Mb 4K sector WSON8
W25Q128JVSIQ
Non-vPro use
128Mb 4K sector SOP8
TPM2.0
ST33HTPH2E32AHC1
KB/TP CONN
FAN CONN
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PS8713
USB redriver
HDA Codec
ALC3204
SATA REPEATER
PI3EQX6741STZDEX
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
P71
P73
P.56
P67
I2C0
USB2.0[11]
USB2.0[1]_PS
USB3.0[1]
USB2.0[2]
USB3.0[3]
USB2.0[3]
USB3.0[4]
INT.Speaker
Universal Jack
Dig. MIC
2020/01/01
2020/01/01
2020/01/01
LCD Touch
USB3.0 Conn
PS(Ext Port 1)
USB3.0 Conn
(Ext Port 2)
USB3.0 Conn
(Ext Port 3)
M2 Key M
SSD Conn
Camera
P.56
P.56
P.56
P.68
SATA HDD
Conn
P38
P38
Trough eDP Cable
P71
P72
P72
Trough eDP Cable
P67
FP in PBTN CONN
CPU&PCH XDP Port
AUTOMATIC POWER
SWITCH(APS)
Free Fall sensor
DC/DC Interface
POWER ON/OFF
SW & LED
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Block diagram
Block diagram
Block diagram
Size
Size
Size
Document Number Re v
Document Number Re v
Document Number Re v
C
C
C
LA-H171P
LA-H171P
LA-H171P
Friday, March 08, 2019
Friday, March 08, 2019
Friday, March 08, 2019
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
LED/B
USH CONN
2 100
2 100
2 100
P65
P62
P66
P7
P19
P67
P78
P62
0.1
0.1
0.1
5
smd.db-x7.ru
4
3
2
1
POWER STATES
RUN
Signal
State
S0 (Full ON) / M0
D D
S3 (Suspend to RAM) / M3 LOW
S4 (Suspend to DISK) / M3
S5 (SOFT OFF) / M3
SLP
S3#
HIGH
LOW
SLP
SLP
S5#
S4#
HIGH HIGH
HIGH HIGH
HIGH HIGH
LOW
LOW
LOW
SLP
A#
HIGH
HIGH
HIGH
ALWAY S
PLANE
M
PLANE
ON
ON ON ON
ON ON
ON ON
ON
SUS
PLANE
ON ON ON
OFF
OFF
PLA NE
OFF
OFF
OFFLOW
CLOCKS
OFF
OFF
OFF
USB3.0
USB3.0-1
USB3.0-2
USB3.0-3
USB3.0-4
USB3.0-5
USB3.0-6
USB3.0-7
S3 (Suspend to RAM) / M-OFF
S4 (Suspend to DISK) / M-OFF
S5 (SOFT OFF) / M-OFF
HIGH HIGH
LOW
LOW LOW LOW
LOW LOW LOW LOW
LOW
HIGH
ON ON
ON
ON
OFF OFF OFF
OFF OFF OFF OFF
OFF OFF OFF OFF
USB3.0-8
USB3.0-9
USB3.0-10
PM TABLE
C C
power
plane
State
S0
B B
S3
S5 S4/AC
S5 S4/AC doesn't exist
+5V_ALW
+3.3V_ALW
+3.3V_ALW_DSW
+RTC_CELL
+1.8V_PRIM
+1.0V_PRIM
+1.0V_PRIM_CORE
+5V_ALW2
+3.3V_ALW2 +VCC_SA
+3.3V_RTC_LDO
+1.0V_MPHYGT
ON
ON
ON
OFF
+3.3V_SUS
+1.2V_MEM+3.3V_ALW_PCH
+1.0V_VCCST
+2.5V_MEM
ON
OFF
OFF
+5V_RUN
+3.3V_RUN
+0.6V_DDR_VTT
+1.2V_RUN
+VCC_CORE
+VCC_GT
+1.0VS_VCCIO
+1.8V_RUN
ONON
OFF
OFF
OFF
SSIC
SSIC-1
SSIC-2
PCIE
PCIE-1
PCIE-2
PCIE-3
PCIE-4
PCIE-5
PCIE-6
PCIE-7
PCIE-8
PCIE-9
PCIE-10
PCIE-11
PCIE-12
PCIE-13
PCIE-14
PCIE-15
PCIE-16
PCIE-17
PCIE-18
PCIE-19
PCIE-20
SATA
SATA-0A
SATA-1A
SATA-0B
SATA-1B
SATA-2
SATA-3
SATA-4
SATA-5
DESTINATION
JUSB1-->Right
JNGFF2-->M2 3042(LTE)
JUSB2-->LEFT
JUSB3-->RIGHT
NA
NA
Alpine Ridge - SP
LOM
Card Reader
JNGFF1-->M.2 2230(WLAN)
NA
M.2 Socket 3 (Key M)
M.2 2280 SSD
(PCIex4 or SATA)
NA
NA
JSATA1-->HDD SATA
NA
M.2 3042 (HCA or QCA LTE) SSD Cache
M.2 3042 (HCA or QCA LTE) SSD Cache
NA
NA
USB PORT#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
USH
VIDEO
eDP
DDI-B
DDI-C
DDI-D
DESTINATION
JUSB1-->Right
JUSB2 ->LEFT
JUSB3-->RIGHT
FP IN PB
TI PD
test point
NA
JNGFF2-->M2 3042(WWAN)
NA
JUSH1-->USH
JEDP1-->Camera
NA
NA
JNGFF1--> M.2 2230(CNVi_BT)
H BIO
DESTINATION
LCD
Alpine Ridge - SP
(Port 0)
Alpine Ridge - SP
(Port 1)
PS175 --> JHDMI1
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
2018/01/01
2018/01/01
2018/01/01
3
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2020/01/01
2020/01/01
2020/01/01
2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Port Assignment
Port Assignment
Port Assignment
Size
Size
Size
Document Number Re v
Document Number Re v
Document Number Re v
A
A
A
LA-H171P
LA-H171P
LA-H171P
Friday, March 08, 2019
Friday, March 08, 2019
Friday, March 08, 2019
Date : Sheet o f
Date : Sheet o f
Date : Sheet o f
1
3 100
3 100
3 100
0.1
0.1
0.1
5
smd.db-x7.ru
4
3
2
1
RUN_O N
3.3V_CAM_EN#
HDMI_1.2V_ EN
CPU PWR
PCH PWR
GT3 PWR
Peripheral Device PWR
TYPE-C Power
GPU PWR
+TS_PWR
+1.8V_RUN
+3.3V_CAM
+3.3V_TBT
+1.2V_RUN
@SIO_SLP_SUS#
P11
@SIO_SLP_S4#
VCCSTG_EN
SY8057QDC
(PU401)
EM5209
(UZ4)
SLGC55544C
(UI3)
SY6288D
(UI1)
SY6288D
(UI2)
RT8097ALGE
(PU501)
EM5209
(UZ2)
EM5209
(UZ3)
EM5209
(UZ4)
G524B1T11U
(UV24)
AP7361C
(PU503)
+VCC_SFR_OC
RUN_O N
P87
RUN_O N
P78
USB_PWR_S HR_EN#
P71
USB_PWR_EN 1#
P72
USB_PWR_EN 2#
P72
PCH_PRIM_ EN
@SIO_SLP_SUS#
P87
SIO_SLP_LAN#
AUX_EN_WOWL
@SIO_SLP_WLAN#
P78
PCH_PRIM_ EN
@SIO_SLP_SUS#
@PCH_ALW_O N
RUN_O N
P78
3.3V_WWAN _EN
P78
ENVDD_ PCH
P38
SIO_SLP_S4#
P87
AOZ1334DI
(UZ19)
AOZ1334DI
(UZ21)
+1.0VS_VCCIO
+5V_RUN
+5V_USB_CHG_PWR
+USB_EX2_PWR
+USB_EX3_PWR
+1.8V_PRIM
+3.3V_LAN
+3.3V_WWLAN
+3.3V_ALW_PCH
+3.3V_RUN
+3.3V_WWAN
+LCDVDD
+2.5V_MEM
for DDR4
P11
P11
RUN_O N
SIO_SLP_S0#
SIO_SLP_S4#
LP2301
(QV8)
AOZ1336
(UZ8)
LP2301A
(QZ1)
AP7361
(PU502)
+1.0V_VCCSTG
+1.0V_VCCST
3.3V_TS_EN
P38
P78
P38
P87
AOZ1334DI
(UZ26)
P86
P87
PCH_PRIM_ EN
@SIO_SLP_SUS#
P85
SIO_SLP_S4#
0.6V_DDR_VTT_ON
ALWON
D D
Barrel
ADAPTER
Type-C
ADAPTER
P82 P46
CHARGER
ISL9538
(PU700)
P84
+13.5VB
SY8210A
(PU200)
SY8286RAC
(PU301)
SY8288C
(PU102)
+1.2V_MEM
+0.6V_DDR_VTT
+1.0V_PRIM
+5V_ALW
+5V_ALW2
BATTERY
P83
C C
SY8288B
(PU100)
P85
ALWON
+3.3V_RTC_LDO
+3.3V_ALW2
+3.3V_ALW
NCP81215(PUZ1)
(PUA1)
B B
+VCC_SA
NCP302045
(PUT1)
IMVP_VR_ ON
IMVP_VR_ ON
+VCC_GT
+5V_ALW
+PP_HV(5V~20V)
AP2204
(UT8)
A A
P45
(PUH1)
(PUH2)
(PUH3)
(PUH4)
P88~89
IMVP_VR_ ON
+VCC_CORE
TPS65982DC
(UT5)
+5V_ALW
+5V_TBT_VBUS
AO6405
(QV1)
+BL_PWR_SRC
P44
AP2112K
(UT7)
P38
EN_INV PWR
+TBT_VBUS(5V~20V)
P45
TYPE-C
+3.3V_TBT_SX
+3.3V_VDD_PIC
+3.3V_TBTA_FLASH
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2018/01/01
2018/01/01
2018/01/01
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2020/01/01
2020/01/01
2020/01/01
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Power Rails
Power Rails
Power Rails
Size
Size
Size
Document Number Re v
Document Number Re v
Document Number Re v
C
C
C
LA-H171P
LA-H171P
LA-H171P
Friday, March 08, 2019
Friday, March 08, 2019
Friday, March 08, 2019
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
4 100
4 100
4 100
0.1
0.1
0.1
5
smd.db-x7.ru
Timing Diagram for S5 to S0 mode
11
CPU
VCCST_PWRGD
PROCPWRGD
PLTRST#
DDR_VTT_CNTL
+PWR_SRC
TLV62130
+3.3V_ALW
RT8097
SIO_SLP_WLAN#
D D
C C
4
4
12
15
17
12
+1.0V_PRIM
+1.8V_PRIM
VCCST_PWRGD
H_CPUPWRGD
PCH_PLTRST#
0.6V_DDR_VTT_ON
VCCIO
VCCGT
VDDQ
VDDQC
VCCPLL_OC
VCCST
VCCSTG
VCCPLL
VCCSA
@SIO_SLP_SUS#
+VCC_CORE
VCC
+1.0VS_VCCIO
+VCC_GT
+1.35V_MEM
+1.0V_VCCST
+VCC_SA
3
PCH_PRIM_EN
EC 5105
4
+1.0V_PRIM
11
TPS22961
SIO_SLP_S0#
RUN_ON
+LCDVDD
11
+5V_TSP
+3.3V_CAM
+3.3V_SPI
3
4
4
17
7
+3.3V_ALW
AP2821K
+3.3V_ALW
EM5209VF+3.3V_LAN
+5V_RUN
LP2301ALT1G
+3.3V_RUN
LP2301ALT1G
+1.0V_PRIM
+3.3V_ALW_DSW
+3.3V_ALW_PCH
+1.8V_PRIM
+RTC_CELL
PCH_PLTRST#
PCH_DPWROK
ENVDD_PCH
SIO_SLP_LAN#
3.3V_TS_EN
3.3V_CAM_EN#
VCCPRIM_1P0
VCCPRIM_CORE
DCPDSW_1P0
VCCAPLL_1P0
VCCCLK1~6
VCCMPHYGT_1P0
VCCSRAM_1P0
VCCAMPHYPLL_1P0
VCCAPLLEBB
VCCDSW_3P3
VCCHDA
VCCSPI
VCCPRIM_3P3
VCCPGPPA~E
VCCRTCPRIM
VCCPGPPA
VCCRTC
PLTRST#
DSW_PWROK
EDP_VDDEN
SLP_LAN#
GPP_B21
GPD7
PCH
PWRBTN#
RSMRST#
SLP_SUS#
SLP_S5#
SLP_S4#
SLP_S3#
SLP_LAN#
SLP_WLAN#/GPD9
SYS_PWROK
PCH_PWROK
VCCST_PWRGD
PROCPWRGD
2
SLP_A#
Power Button
SIO_PWRBTN#
PCH_RSMRST#_AND
SIO_SLP_SUS#
SIO_SLP_S5#
SIO_SLP_S4#
SIO_SLP_S3#
SIO_SLP_A#
SIO_SLP_LAN#
SIO_SLP_WLAN#
RESET_OUT#
PCH_PWROK
VCCST_PWRGD
H_CPUPWRGD
16
15
10
11
14
12
1
8
6
9
2AC1BAT
11
RUN_ON
+5V_ALW
EM5209VF
+3.3V_ALW
EM5209VF
+5V_RUN
+3.3V_RUN
+5V_HDD
+3.3V_HDD
ADAPTER
BATTERY
ALWON
+PWR_SRC
SYX198EC 5105
+PWR_SRC
SYX198
+5V_ALW2
+5V_ALW
+3.3V_RTC_LDO
+3.3V_ALW2
+3.3V_ALW
1BAT
2AC
B B
SIO_SLP_WLAN#
+3.3V_ALW
+3.3V_WLAN EM5209VF
11
AUX_EN_WOWL
A A
5
4
+5V_ALW
SY8057QDC
+1.0VS_VCCIO
13
PCH_RSMRST#
5
RESET_OUT#
16
+3.3V_ALW
SIO_SLP_SUS#
SIO_SLP_S4#
10
SIO_SLP_S5#
9
SIO_SLP_LAN#
SIO_SLP_S3#
11
SIO_SLP_A#
+VCC_SA
+VCC_CORE
+VCC_GT
+PWR_SRC
NCP81215
PCH_PWROK
12
IMVP_VR_ON
14
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2018/01/01
2018/01/01
2018/01/01
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
3
PCH_PRIM_EN
@SIO_SLP_SUS#
EN_INVPWR
SIO_SLP_S4#
0.6V_DDR_VTT_ON
2020/01/01
2020/01/01
2020/01/01
+3.3V_ALW
EM5209VF
+PWR_SRC
AO6405
+PWR_SRC
SY8210A
+3.3V_ALW_PCH
+BL_PWR_S RC
+1.2V_MEM
+0.6V_DDR_VTT
4
Pop option
+3.3V_SPI
18
12
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Power Sequence
Power Sequence
Power Sequence
Size
Size
Size
Document Number Rev
Document Number Rev
Document Number Rev
Custom
Custom
Custom
LA-H171P
LA-H171P
LA-H171P
Friday, March 08, 2019
Friday, March 08, 2019
Friday, March 08, 2019
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
VDDQ
VTT
5 100
5 100
5 100
DDR
0.1
0.1
0.1
5
smd.db-x7.ru
D D
C C
B B
+1.0VS_VCCIO
1 2
RC2 24.9_0402_1%
Trace width=5 mils
,Spacing=15mil
A A
Max length= 600 mils.
PEG_COMP
4
E25
D25
E24
F24
E23
D23
E22
F22
E21
D21
E20
F20
E19
D19
E18
F18
D17
E17
F16
E16
D15
E15
F14
E14
D13
E13
F12
E12
D11
E11
F10
E10
PEG_COMP
DMI_CRX_PTX_P0<15>
DMI_CRX_PTX_N0<15> DMI_CTX_PRX_N0 <15>
DMI_CRX_PTX_P1<15>
DMI_CRX_PTX_N1<15>
DMI_CRX_PTX_P2<15>
DMI_CRX_PTX_N2<15>
DMI_CRX_PTX_P3<15>
DMI_CRX_PTX_N3<15>
DMI_CRX_PTX_P0
DMI_CRX_PTX_N0
DMI_CRX_PTX_P1
DMI_CRX_PTX_N1
DMI_CRX_PTX_P2
DMI_CRX_PTX_N2
DMI_CRX_PTX_P3
DMI_CRX_PTX_N3
G2
D8
E8
E6
F6
D5
E5
J8
J9
CFL-H_BGA1440
UC1C
PEG_RXP_0
PEG_RXN_0
PEG_RXP_1
PEG_RXN_1
PEG_RXP_2
PEG_RXN_2
PEG_RXP_3
PEG_RXN_3
PEG_RXP_4
PEG_RXN_4
PEG_RXP_5
PEG_RXN_5
PEG_RXP_6
PEG_RXN_6
PEG_RXP_7
PEG_RXN_7
PEG_RXP_8
PEG_RXN_8
PEG_RXP_9
PEG_RXN_9
PEG_RXP_10
PEG_RXN_10
PEG_RXP_11
PEG_RXN_11
PEG_RXP_12
PEG_RXN_12
PEG_RXP_13
PEG_RXN_13
PEG_RXP_14
PEG_RXN_14
PEG_RXP_15
PEG_RXN_15
PEG_RCOMP
DMI_RXP_0
DMI_RXN_0
DMI_RXP_1
DMI_RXN_1
DMI_RXP_2
DMI_RXN_2
DMI_RXP_3
DMI_RXN_3
3
CFL-H
PEG_TXP_0
PEG_TXN_0
PEG_TXP_1
PEG_TXN_1
PEG_TXP_2
PEG_TXN_2
PEG_TXP_3
PEG_TXN_3
PEG_TXP_4
PEG_TXN_4
PEG_TXP_5
PEG_TXN_5
PEG_TXP_6
PEG_TXN_6
PEG_TXP_7
PEG_TXN_7
PEG_TXP_8
PEG_TXN_8
PEG_TXP_9
PEG_TXN_9
PEG_TXP_10
PEG_TXN_10
PEG_TXP_11
PEG_TXN_11
PEG_TXP_12
PEG_TXN_12
PEG_TXP_13
PEG_TXN_13
PEG_TXP_14
PEG_TXN_14
PEG_TXP_15
PEG_TXN_15
3 OF 13
DMI_TXP_0
DMI_TXN_0
DMI_TXP_1
DMI_TXN_1
DMI_TXP_2
DMI_TXN_2
DMI_TXP_3
DMI_TXN_3
B25
A25
B24
C24
B23
A23
B22
C22
B21
A21
B20
C20
B19
A19
B18
C18
A17
B17
C16
B16
A15
B15
C14
B14
A13
B13
C12
B12
A11
B11
C10
B10
B8
A8
C6
B6
B5
A5
D4
B4
DMI_CTX_PRX_P0
DMI_CTX_PRX_N0
DMI_CTX_PRX_P1
DMI_CTX_PRX_N1
DMI_CTX_PRX_P2
DMI_CTX_PRX_N2
DMI_CTX_PRX_P3
DMI_CTX_PRX_N3
2
DMI_CTX_PRX_P0 <15>
DMI_CTX_PRX_P1 <15>
DMI_CTX_PRX_N1 <15>
DMI_CTX_PRX_P2 <15>
DMI_CTX_PRX_N2 <15>
DMI_CTX_PRX_P3 <15>
DMI_CTX_PRX_N3 <15>
1
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
2018/01/01
2018/01/01
2018/01/01
3
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2020/01/01
2020/01/01
2020/01/01
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
CFL-H (1/8)
CFL-H (1/8)
CFL-H (1/8)
Size
Size
Size
Document Number Re v
Document Number Re v
Document Number Re v
A
A
A
LA-H171P
LA-H171P
LA-H171P
Friday, March 08, 2019
Friday, March 08, 2019
Friday, March 08, 2019
Date : Sheet o f
Date : Sheet o f
Date : Sheet o f
1
6 100
6 100
6 100
0.1
0.1
0.1
Security Classification
DELL CONFIDENTIAL/PROPRIETARY
Security Classification
5
smd.db-x7.ru
+1.0V_PRIM
@
PAD~D
DDR_XDP_WAN_SMBDAT<18,23,24,67>
DDR_XDP_WAN_SMBCLK<18,23,24,67>
PCH_JTAG_TCK<18>
+1.0V_VCCST
+1.0V_PRIM
1 2
RC216 0_0603_1%@
@ESD@
@ESD@
0.1U_0201_10V6K
0.1U_0201_10V6K
1
1
CC334
CC335
2
2
Place near JXDP1
DVT1.0
ESD request reserve,pilot remove 0 ohm
0 ohm:RC841~RC846
1 2
RC841 0_0201_5%XDP@
PCH_RSMRST#_AND_XDP
1
SIO_PWRBTN#<18,58>
PCH_SPI_D0<17>
SYS_PWROK<18,58>
CPU_XDP_TMS
CPU_XDP_TDI
CPU_XDP_TDO
CPU_XDP_TCLK
CPU_XDP_PRDY#
CPU_XDP_PREQ#
56.2_0402_1%
100_0402_5%
12
12
RC152
RC157
220_0402_5%
12
RC153
VR_SVID_DATA
CPU_VIDALERT#
+3.3V_ALW_PCH
XDP@
1.5K_0402_5%
12
RC133
SYS_PWROK_R
0.1U_0402_25V6
@
1
CC33
D D
+3.3V_ALW
C C
+1.0V_PRIM_XDP
+1.0VS_VCCIO
+1.0V_VCCSTG
+1.0V_VCCST
+1.0V_VCCST
B B
Place near JXDP1.47
2
XDP@
1.5K_0402_5%
12
RC241
SIO_PWRBTN#_XDP
0.1U_0402_25V6
ESD@
1
Place near JXDP1.41
CC269
2
1 2
RC138 51_0402_5%@
1 2
RC132 150_0402_5%
1 2
RC83 1K_0402_5%
1 2
RC80 1K_0402_5%
1 2
RC166 1K_0402_5%@
1 2
RC71 1K_0402_5%
1 2
RC79 49.9_0402_1%@
1 2
RC218 150_0402_5%@
1 2
RC219 10K_0402_5%@
VR_SVID_DATA<88>
VR_SVID_ALERT#<88>
PCH_RSMRST#_AND<18,63>
T191
CPU_XDP_PREQ#
FIVR_EN_R
PROCHOT#
H_THERMTRIP#
PCH_JTAGX
VCCST_PWRGD
H_CATERR#
FIVR_EN
FIVR_EN
VR_SVID_DATA
VR_SVID_ALERT#
+1.0V_PRIM_XDP
+1.0V_PRIM_XDP
0.1U_0402_25V6
@
1
1
CC28
2
2
FIVR_EN
CFG0
CPU_XDP_TDO H_VCCST_PWRGD_XDP CPU_XDP_TRST#_XDP
0.1U_0402_25V6
@ESD@
12
CC306
1 2
RC228 0_0402_5%@
1 2
RC229 0_0402_5%@
1 2
RC230 0_0402_5%@
1 2
RC143 0_0402_5%@
1 2
RC314 0_0402_5%@
1 2
RC315 0_0402_5%@
+1.0V_VCCSTG
0.1U_0402_25V6
@
CC29
RC124 1K_0402_5%XDP@
RC842 0_0201_5%XDP@
RC217 0_0402_5%@
RC126 1K_0402_5%XDP@
RC128 1K_0402_5%XDP@
RC129 0_0402_5%@
RC846 0_0201_5%XDP@
RC845 0_0201_5%XDP@
RC843 0_0201_5%XDP@
0.1U_0402_25V6
@ESD@
12
CC307
ESD request,Place near JXDP1 side.
just remind to check layout !!
A A
H_PWRGD VCCST_PWRGD H_THERMTRIP#
100P_0402_50V8J
12
CC300ESD@
100P_0402_50V8J
12
CC301ESD@
ESD Reques t:place near CPU side
5
@ESD@
0.1U_0402_25V6
12
CC323
PROCHOT#
12
@ESD@
0.1U_0402_25V6
CC324
VR_SVID_CLK
4
change to small XDP conn,follow merion
Link FP270H-061G1AM done
XDP_PRSNT_PIN1
@ESD@
@ESD@
0.1U_0201_10V6K
0.1U_0201_10V6K
1
1
CC336
CC337
2
2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
12
PCH_JTAG_TMS <18>
PCH_JTAG_TDI <18>
PCH_JTAG_TDO <18>
PCH_JTAGX <18>
PCH_XDP_PRDY# <20>
PCH_XDP_PREQ# <20>
VR_SVID_CLK<88>
PROCHOT#<58,84,88>
DDR_VTT_CTRL<23>
VCCST_PWRGD<59>
H_PWRGD<18>
PLTRST_CPU#<14>
H_PM_SYNC<14>
H_PM_DOWN<14>
H_PECI<14,58>
H_THERMTRIP#<14,23,24,59>
pop RC171 for CNL
depop RC171 for SKL & KBL (CFL CRB rev0.5)
RF Request
1 2
CC325@RF@ 33P_0402_50V8J
4
+1.0V_PRIM_XDP +1.0V_PRIM_XDP
CPU_XDP_PREQ#
CPU_XDP_PRDY#
CFG0
CFG1
CFG2
CFG3
XDP_OBS0_R
XDP_OBS1_R
CFG4
CFG5
CFG6
CFG7
H_VCCST_PWRGD_XDP
SIO_PWRBTN#_XDP
FIVR_EN_R
SYS_PWROK_R
DDR_XDP_WAN_SMBDAT_XDP
DDR_XDP_WAN_SMBCLK_XDP
PCH_JTAG_TCK_XDP
CPU_XDP_TCLK
0.1U_0402_25V6
@ESD@
CC308
PCH_CPU_BCLK_R_D<16>
PCH_CPU_BCLK_R_D#<16>
PCH_CPU_PCIBCLK_R_D<16>
PCH_CPU_PCIBCLK_R_D#<16>
CPU_24MHZ_R_D<16>
CPU_24MHZ_R_D#<16>
VR_SVID_CLK
PROCHOT#
DDR_VTT_CTRL
VCCST_PWRGD VCCST_PWRGD_CPU
H_PWRGD
PLTRST_CPU#
H_PM_SYNC
H_PECI
H_THERMTRIP# H_THERMTRIP#_R
Place close CPU side
XDP@
1 2
RC121 1K_0402_5%
1 2
RC122 0_0402_5%@
CPU XDP
CONN@
JXDP1
2
112
4
334
6
556
8
778
10
9910
12
111112
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
595960
61
GND62GND
1 2
1 2
1 2
1 2
1 2
1 2
PLTRST_CPU#
14
14
16
16
18
18
20
20
22
22
24
24
26
26
28
28
30
30
32
32
34
34
36
36
38
38
40
40
42
42
44
44
46
46
48
48
50
50
52
52
54
54
56
56
58
58
60
63
PCH_CPU_BCLK_R_D
PCH_CPU_BCLK_R_D#
PCH_CPU_PCIBCLK_R_D
PCH_CPU_PCIBCLK_R_D#
CPU_24MHZ_R_D
CPU_24MHZ_R_D#
CPU_VIDALERT#
VR_SVID_DATA
H_PROCHOT#_R
T26PAD~D @
T25PAD~D @
T31PAD~D @
T32PAD~D @
ESD request 7/25
Close UC1.BP35
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
61
JXT_FP270H-061G1AM
RC84 499_0402_1%
RC78 60.4_0402_1%
RC168 20_0402_5%
RC169 0_0402_5%@
RC319 0_0402_5%@
RC171 0_0402_5%@
3
CFG3
CFG17
CFG16
CFG8
CFG9
CFG10
CFG11
CFG19
CFG18
CFG12
CFG13
CFG14
CFG15
PCH_XDP_CLK_DP
PCH_XDP_CLK_DN
CPU_XDP_HOOK6
XDP_DBRESET#
CPU_XDP_TDO
CPU_XDP_TRST#_XDP
CPU_XDP_TDI
CPU_XDP_TMS
CPU_XDP_PRS
CPU_XDP_HOOK6
XDP_DBRESET#
CPU_XDP_TDO
CPU_XDP_TRST#
CPU_XDP_TCLK
H_PM_DOWN_RH_PM_DOWN
H_SKTOCC#
SKL_CNL#
H_CATERR#
1
1
1
1
0.1U_0201_10V6K
@ESD@
1
CC549
2
3
2
CFG11
CFG12
12
@
RC441
1K_0402_5%
12
@
RC442
1K_0402_5%
DMI_ AC_c oupl ed
HALF-SWI NG
DC coupled
FULL-SWI NG
AC coupling
PMSYNC2. 0
LEGACY
PCH_XDP_CLK_DP <16>
PCH_XDP_CLK_DN <16>
RC144 0_0402_5%XDP@
XDP_DBRESET# <15>
RC844 0_0201_5%XDP@
RC127 1K_0402_5%XDP@
1 2
RC115 2.2K_0402_5%XDP@
1 2
RC137 3K_0402_5%
1 2
RC135 51_0402_5%
1 2
RC136 51_0402_5%@
1 2
RC139 51_0402_5%
UC1E
B31
BCLKP
A32
BCLKN
D35
PCI_BCLKP
C36
PCI_BCLKN
E31
CLK24P
D31
CLK24N
BH31
VIDALERT#
BH32
VIDSCK
BH29
VIDSOUT
BR30
PROCHOT#
BT13
DDR_VTT_CNTL
H13
VCCST_PWRGD
BT31
PROCPWRGD
BP35
RESET#
BM34
PM_SYNC
BP31
PM_DOWN
BT34
PECI
J31
THERMTRIP#
BR33
SKTOCC#
BN1
PROC_SELECT#
BM30
CATERR#
AT13
ZVM#
AW13
MSM#
AU13
RSVD1
AY13
RSVD2
CFL-H_BGA1440
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1 2
1 2
1 2
CFL-H
ITP_PMODE_CPU
PCH_SPI_D2_XDP
+1.0V_PRIM_XDP
+3.3V_ALW_PCH
+1.0V_VCCSTG
PROC_TDO
PROC_TDI
PROC_TMS
PROC_TCK
PROC_TRST#
PROC_PREQ#
PROC_PRDY#
CFG_RCOMP
5 OF 13
CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_17
CFG_16
CFG_19
CFG_18
BPM#_0
BPM#_1
BPM#_2
BPM#_3
2018/01/01
2018/01/01
2018/01/01
ITP_PMODE_CPU <18>
CPU_XDP_TRST# <20>
PCH_SPI_D2_XDP <17>
CFG13
BN25
CFG0
BN27
CFG1
BN26
CFG2
BN28
CFG3
BR20
CFG4
BM20
CFG5
BT20
CFG6
BP20
CFG7
BR23
CFG8
BR22
CFG9
BT23
CFG10
BT22
CFG11
BM19
CFG12
BR19
CFG13
BP19
CFG14
BT19
CFG15
BN23
CFG17
BP23
CFG16
BP22
CFG19
BN22
CFG18
XDP_OBS0
BR27
XDP_OBS1
BT27
BM31
BT30
CPU_XDP_TDO
BT28
CPU_XDP_TDI
BL32
CPU_XDP_TMS
BP28
CPU_XDP_TCLK
BR28
CPU_XDP_TRST#
BP30
CPU_XDP_PREQ#
BL30
CPU_XDP_PRDY#
BP27
CFG_RCOMP
BT25
Compal Secret Data
Compal Secret Data
Compal Secret Data
12
@
RC443
1K_0402_5%
12
RC114
49.9_0402_1%
Deciphered Date
Deciphered Date
Deciphered Date
RC239 0_0402_5%@
RC240 0_0402_5%@
1
1
1
1
1
1
1
1 2
1 2
2
SYNC & AYNC MODE
ASYNCHRO NOUS
SYNCHRON OUS
XDP_DBRESET#
@
T184
PAD~D
@
T185
PAD~D
@
T180
PAD~D
@
T181
PAD~D
@
T179
PAD~D
@
T190
PAD~D
@
T189
PAD~D
XDP_OBS0_R
XDP_OBS1_R
2020/01/01
2020/01/01
2020/01/01
1
2
1
CFG10
12
@
RC440
1
1K_0402_5%
0
+1.0VS_VCCIO
RC439
@
1 2
CFG9
1K_0402_5%
12
RC438
1
@
1K_0402_5%
0
CFG8
12
@
RC437
1K_0402_5%
SAFE mode boot
active
Not active10
SVID N OT Present
Present
Not presnet10
CFG UNLOCK
disable
enable10
CFG1
12
CFG0
12
1
0
CFG2
12
0.1U_0201_10V6K
XDP@
CC32
CFG4
12
CFG5
12
CFG6
12
CFG7
12
PCHLESS MODE (CRB)
Reserved CF G lane (EDS)
@
RC436
1K_0402_5%
NORMAL
PCHLESS
Stall reset sequence after PCU
PLL lock until de-asserted
@
RC321
1K_0402_5%
No Sta ll
Stall
PEG LANE REVE RSAL
@
RC181
1K_0402_5%
NORMAL
LANE
REVERSE D
eDP enable
RC322
1K_0402_5%
Disable d
Enabled
PCI Express* Bifurcation
@
RC323
1K_0402_5%
1x8, 2 x4
Reserve d
@
RC324
1K_0402_5%
@
RC325
1K_0402_5%
2x8
1x16
PEG Training
(default) PEG Train
immediately following
RESET# de-assertion
PEG Wait for BIOS for
trai ning
1
0
1
0
1
0
1
0
[6:5 ]
00
01
10
11
1
0
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
CFL-H (2/8)
CFL-H (2/8)
CFL-H (2/8)
Size
Size
Size
Document Number Re v
Document Number Re v
Document Number Re v
B
B
B
LA-H171P
LA-H171P
LA-H171P
Tuesday, March 12, 2019
Tuesday, March 12, 2019
Tuesday, March 12, 2019
Date: Sheet o f
Date: Sheet o f
Date: Sheet o f
1
7 100
7 100
7 100
0.1
0.1
0.1
5
smd.db-x7.ru
DDR_A_DQS#[0..7]<23>
DDR_A_DQS[0..7]<23>
DDR_B_DQS#[0..7]<24>
DDR_B_DQS[0..7]<24>
4
3
2
1
D D
DDR_A_D[0..15]<23>
DDR_A_D[32..47]<23>
C C
B B
DDR_B_D[0..15]<24>
DDR_B_D[32..47]<24>
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
UC1A
DDR4(IL)/LP3-DDR4(NIL)
BR6
DDR0_DQ_0/DDR0_DQ_0
BT6
DDR0_DQ_1/DDR0_DQ_1
BP3
DDR0_DQ_2/DDR0_DQ_2
BR3
DDR0_DQ_3/DDR0_DQ_3
BN5
DDR0_DQ_4/DDR0_DQ_4
BP6
DDR0_DQ_5/DDR0_DQ_5
BP2
DDR0_DQ_6/DDR0_DQ_6
BN3
DDR0_DQ_7/DDR0_DQ_7
BL4
DDR0_DQ_8/DDR0_DQ_8
BL5
DDR0_DQ_9/DDR0_DQ_9
BL2
DDR0_DQ_10/DDR0_DQ_10
BM1
DDR0_DQ_11/DDR0_DQ_11
BK4
DDR0_DQ_12/DDR0_DQ_12
BK5
DDR0_DQ_13/DDR0_DQ_13
BK1
DDR0_DQ_14/DDR0_DQ_14
BK2
DDR0_DQ_15/DDR0_DQ_15
BG4
DDR0_DQ_16/DDR0_DQ_32
BG5
DDR0_DQ_17/DDR0_DQ_33
BF4
DDR0_DQ_18/DDR0_DQ_34
BF5
DDR0_DQ_19/DDR0_DQ_35
BG2
DDR0_DQ_20/DDR0_DQ_36
BG1
DDR0_DQ_21/DDR0_DQ_37
BF1
DDR0_DQ_22/DDR0_DQ_38
BF2
DDR0_DQ_23/DDR0_DQ_39
BD2
DDR0_DQ_24/DDR0_DQ_40
BD1
DDR0_DQ_25/DDR0_DQ_41
BC4
DDR0_DQ_26/DDR0_DQ_42
BC5
DDR0_DQ_27/DDR0_DQ_43
BD5
DDR0_DQ_28/DDR0_DQ_44
BD4
DDR0_DQ_29/DDR0_DQ_45
BC1
DDR0_DQ_30/DDR0_DQ_46
BC2
DDR0_DQ_31/DDR0_DQ_47
AB1
DDR0_DQ_32/DDR1_DQ_0
AB2
DDR0_DQ_33/DDR1_DQ_1
AA4
DDR0_DQ_34/DDR1_DQ_2
AA5
DDR0_DQ_35/DDR1_DQ_3
AB5
DDR0_DQ_36/DDR1_DQ_4
AB4
DDR0_DQ_37/DDR1_DQ_5
AA2
DDR0_DQ_38/DDR1_DQ_6
AA1
DDR0_DQ_39/DDR1_DQ_7
V5
DDR0_DQ_40/DDR1_DQ_8
V2
DDR0_DQ_41/DDR1_DQ_9
U1
DDR0_DQ_42/DDR1_DQ_10
U2
DDR0_DQ_43/DDR1_DQ_11
V1
DDR0_DQ_44/DDR1_DQ_12
V4
DDR0_DQ_45/DDR1_DQ_13
U5
DDR0_DQ_46/DDR1_DQ_14
U4
DDR0_DQ_47/DDR1_DQ_15
R2
DDR0_DQ_48/DDR1_DQ_32
P5
DDR0_DQ_49/DDR1_DQ_33
R4
DDR0_DQ_50/DDR1_DQ_34
P4
DDR0_DQ_51/DDR1_DQ_35
R5
DDR0_DQ_52/DDR1_DQ_36
P2
DDR0_DQ_53/DDR1_DQ_37
R1
DDR0_DQ_54/DDR1_DQ_38
P1
DDR0_DQ_55/DDR1_DQ_39
M4
DDR0_DQ_56/DDR1_DQ_40
M1
DDR0_DQ_57/DDR1_DQ_41
L4
DDR0_DQ_58/DDR1_DQ_42
L2
DDR0_DQ_59/DDR1_DQ_43
M5
DDR0_DQ_60/DDR1_DQ_44
M2
DDR0_DQ_61/DDR1_DQ_45
L5
DDR0_DQ_62/DDR1_DQ_46
L1
DDR0_DQ_63/DDR1_DQ_47
LP3/DDR4
BA2
NC/DDR0_ECC_0
BA1
NC/DDR0_ECC_1
AY4
NC/DDR0_ECC_2
AY5
NC/DDR0_ECC_3
BA5
NC/DDR0_ECC_4
BA4
NC/DDR0_ECC_5
AY1
NC/DDR0_ECC_6
AY2
NC/DDR0_ECC_7
CFL-H_BGA1440
CFL-H
DDR CHANNEL A
DDR0_CKP_0/DDR0_CKP_0
DDR0_CKN_0/DDR0_CKN_0
DDR0_CKP_1/DDR0_CKP_1
DDR0_CKN_1/DDR0_CKN_1
NC/DDR0_CKP_2
NC/DDR0_CKN_2
NC/DDR0_CKP_3
NC/DDR0_CKN_3
DDR0_CKE_0/DDR0_CKE_0
DDR0_CKE_1/DDR0_CKE_1
DDR0_CKE_2/DDR0_CKE_2
DDR0_CKE_3/DDR0_CKE_3
DDR0_CS#_0/DDR0_CS#_0
DDR0_CS#_1/DDR0_CS#_1
NC/DDR0_CS#_2
NC/DDR0_CS#_3
DDR0_ODT_0/DDR0_ODT_0
NC/DDR0_ODT_1
NC/DDR0_ODT_2
NC/DDR0_ODT_3
DDR0_CAB_4/DDR0_BA_0
DDR0_CAB_6/DDR0_BA_1
DDR0_CAA_5/DDR0_BG_0
DDR0_CAB_3/DDR0_MA_16
DDR0_CAB_2/DDR0_MA_14
DDR0_CAB_1/DDR0_MA_15
DDR0_CAB_9/DDR0_MA_0
DDR0_CAB_8/DDR0_MA_1
DDR0_CAB_5/DDR0_MA_2
NC/DDR0_MA_3
NC/DDR0_MA_4
DDR0_CAA_0/DDR0_MA_5
DDR0_CAA_2/DDR0_MA_6
DDR0_CAA_4/DDR0_MA_7
DDR0_CAA_3/DDR0_MA_8
DDR0_CAA_1/DDR0_MA_9
DDR0_CAB_7/DDR0_MA_10
DDR0_CAA_7/DDR0_MA_11
DDR0_CAA_6/DDR0_MA_12
DDR0_CAB_0/DDR0_MA_13
DDR0_CAA_9/DDR0_BG_1
DDR0_CAA_8/DDR0_ACT#
NC/DDR0_PAR
NC/DDR0_ALERT#
DDR4(IL)/LP3-DDR4(NIL)
DDR0_DQSN_0/DDR0_DQSN_0
DDR0_DQSN_1/DDR0_DQSN_1
DDR0_DQSN_2/DDR0_DQSN_4
DDR0_DQSN_3/DDR0_DQSN_5
DDR0_DQSN_4/DDR1_DQSN_0
DDR0_DQSN_5/DDR1_DQSN_1
DDR0_DQSN_6/DDR1_DQSN_4
DDR0_DQSN_7/DDR1_DQSN_5
DDR0_DQSP_0/DDR0_DQSP_0
DDR0_DQSP_1/DDR0_DQSP_1
DDR0_DQSP_2/DDR0_DQSP_4
DDR0_DQSP_3/DDR0_DQSP_5
DDR0_DQSP_4/DDR1_DQSP_0
DDR0_DQSP_5/DDR1_DQSP_1
DDR0_DQSP_6/DDR1_DQSP_4
DDR0_DQSP_7/DDR1_DQSP_5
DDR0_DQSP_8/DDR0_DQSP_8
DDR0_DQSN_8/DDR0_DQSN_8
1 OF 13
LP3/DDR4
UC1B
DDR_A_CLK0
AG1
DDR_A_CLK#0
AG2
AK2
DDR_A_CLK#1 DDR_B_CLK#1
AK1
AL3
AK3
AL2
AL1
DDR_A_CKE0
AT1
DDR_A_CKE1
AT2
AT3
AT5
DDR_A_CS#0
AD5
DDR_A_CS#1
AE2
AD2
AE5
DDR_A_ODT0
AD3
DDR_A_ODT1
AE4
AE1
AD4
DDR_A_BA0
AH5
DDR_A_BA1
AH1
DDR_A_BG0
AU1
DDR_A_MA16
AH4
DDR_A_MA14
AG4
DDR_A_MA15
AD1
DDR_A_MA0
AH3
DDR_A_MA1
AP4
DDR_A_MA2
AN4
DDR_A_MA3
AP5
DDR_A_MA4
AP2
DDR_A_MA5
AP1
DDR_A_MA6
AP3
DDR_A_MA7
AN1
DDR_A_MA8
AN3
DDR_A_MA9
AT4
DDR_A_MA10
AH2
DDR_A_MA11
AN2
DDR_A_MA12
AU4
DDR_A_MA13
AE3
DDR_A_BG1
AU2
DDR_A_ACT#
AU3
DDR_A_PAR
AG3
DDR_A_ALERT#
AU5
DDR_A_DQS#0
BR5
DDR_A_DQS#1
BL3
DDR_A_DQS#4
BG3
DDR_A_DQS#5
BD3
DDR_B_DQS#0
AA3
DDR_B_DQS#1
U3
DDR_B_DQS#4
P3
DDR_B_DQS#5
L3
DDR_A_DQS0
BP5
DDR_A_DQS1
BK3
DDR_A_DQS4
BF3
DDR_A_DQS5
BC3
DDR_B_DQS0
AB3
DDR_B_DQS1
V3
DDR_B_DQS4
R3
DDR_B_DQS5
M3
AY3
BA3
DDR_A_CLK0 <23>
DDR_A_CLK#0 <23>
DDR_A_CLK1 <23>
DDR_A_CLK#1 <23> DDR_B_CLK#1 <24>
DDR_A_CKE0 <23>
DDR_A_CKE1 <23>
DDR_A_CS#0 <23>
DDR_A_CS#1 <23>
DDR_A_ODT0 <23>
DDR_A_ODT1 <23>
DDR_A_BA0 <23>
DDR_A_BA1 <23>
DDR_A_BG0 <23>
DDR_A_MA[0..16] <23>
DDR_A_BG1 <23>
DDR_A_ACT# <23>
DDR_A_PAR <23>
DDR_A_ALERT# <23>
DDR_A_DQS#0 <23>
DDR_A_DQS#1 <23>
DDR_A_DQS#4 <23>
DDR_A_DQS#5 <23>
DDR_B_DQS#0 <24>
DDR_B_DQS#1 <24>
DDR_B_DQS#4 <24>
DDR_B_DQS#5 <24>
DDR_A_DQS0 <23>
DDR_A_DQS1 <23>
DDR_A_DQS4 <23>
DDR_A_DQS5 <23>
DDR_B_DQS0 <24>
DDR_B_DQS1 <24>
DDR_B_DQS4 <24>
DDR_B_DQS5 <24>
DDR_A_D[16..31]<23>
DDR_A_D[48..63]<23>
DDR_B_D[16..31]<24>
DDR_B_D[48..63]<24>
1 2
RC5 121_0402_1%
1 2
RC6 75_0402_1%
1 2
RC7 100_0402_1%
Trace width=12-15 mils
,Spacing=20mil
Max length= 500 mils.
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
DDR_RCOMP0
DDR_RCOMP1
DDR_RCOMP2
DDR4(IL)/LP3-DDR4(NIL)
BT11
DDR1_DQ_0/DDR0_DQ_16
BR11
DDR1_DQ_1/DDR0_DQ_17
BT9
DDR1_DQ_2/DDR0_DQ_18
BR8
DDR1_DQ_3/DDR0_DQ_19
BP11
DDR1_DQ_4/DDR0_DQ_20
BN11
DDR1_DQ_5/DDR0_DQ_21
BP8
DDR1_DQ_6/DDR0_DQ_22
BN8
DDR1_DQ_7/DDR0_DQ_23
BL12
DDR1_DQ_8/DDR0_DQ_24
BL11
DDR1_DQ_9/DDR0_DQ_25
BL8
DDR1_DQ_10/DDR0_DQ_26
BJ8
DDR1_DQ_11/DDR0_DQ_27
BJ11
DDR1_DQ_12/DDR0_DQ_28
BJ10
DDR1_DQ_13/DDR0_DQ_29
BL7
DDR1_DQ_14/DDR0_DQ_30
BJ7
DDR1_DQ_15/DDR0_DQ_31
BG11
DDR1_DQ_16/DDR0_DQ_48
BG10
DDR1_DQ_17/DDR0_DQ_49
BG8
DDR1_DQ_18/DDR0_DQ_50
BF8
DDR1_DQ_19/DDR0_DQ_51
BF11
DDR1_DQ_20/DDR0_DQ_52
BF10
DDR1_DQ_21/DDR0_DQ_53
BG7
DDR1_DQ_22/DDR0_DQ_54
BF7
DDR1_DQ_23/DDR0_DQ_55
BB11
DDR1_DQ_24/DDR0_DQ_56
BC11
DDR1_DQ_25/DDR0_DQ_57
BB8
DDR1_DQ_26/DDR0_DQ_58
BC8
DDR1_DQ_27/DDR0_DQ_59
BC10
DDR1_DQ_28/DDR0_DQ_60
BB10
DDR1_DQ_29/DDR0_DQ_61
BC7
DDR1_DQ_30/DDR0_DQ_62
BB7
DDR1_DQ_31/DDR0_DQ_63
AA11
DDR1_DQ_32/DDR1_DQ_16
AA10
DDR1_DQ_33/DDR1_DQ_17
AC11
DDR1_DQ_34/DDR1_DQ_18
AC10
DDR1_DQ_35/DDR1_DQ_19
AA7
DDR1_DQ_36/DDR1_DQ_20
AA8
DDR1_DQ_37/DDR1_DQ_21
AC8
DDR1_DQ_38/DDR1_DQ_22
AC7
DDR1_DQ_39/DDR1_DQ_23
DDR4(IL)/LP3-DDR4(NIL)
W8
DDR1_DQ_40/DDR1_DQ_24
W7
DDR1_DQ_41/DDR1_DQ_25
V10
DDR1_DQ_42/DDR1_DQ_26
V11
DDR1_DQ_43/DDR1_DQ_27
W11
DDR1_DQ_44/DDR1_DQ_28
W10
DDR1_DQ_45/DDR1_DQ_29
V7
DDR1_DQ_46/DDR1_DQ_30
V8
DDR1_DQ_47/DDR1_DQ_31
R11
DDR1_DQ_48/DDR1_DQ_48
P11
DDR1_DQ_49/DDR1_DQ_49
P7
DDR1_DQ_50/DDR1_DQ_50
R8
DDR1_DQ_51/DDR1_DQ_51
R10
DDR1_DQ_52/DDR1_DQ_52
P10
DDR1_DQ_53/DDR1_DQ_53
R7
DDR1_DQ_54/DDR1_DQ_54
P8
DDR1_DQ_55/DDR1_DQ_55
L11
DDR1_DQ_56/DDR1_DQ_56
M11
DDR1_DQ_57/DDR1_DQ_57
L7
DDR1_DQ_58/DDR1_DQ_58
M8
DDR1_DQ_59/DDR1_DQ_59
L10
DDR1_DQ_60/DDR1_DQ_60
M10
DDR1_DQ_61/DDR1_DQ_61
M7
DDR1_DQ_62/DDR1_DQ_62
L8
DDR1_DQ_63/DDR1_DQ_63
LP3/DDR4
AW11
NC/DDR1_ECC_0
AY11
NC/DDR1_ECC_1
AY8
NC/DDR1_ECC_2
AW8
NC/DDR1_ECC_3
AY10
NC/DDR1_ECC_4
AW10
NC/DDR1_ECC_5
AY7
NC/DDR1_ECC_6
AW7
NC/DDR1_ECC_7
G1
DDR_RCOMP_0
H1
DDR_RCOMP_1
J2
DDR_RCOMP_2
CFL-H_BGA1440
CFL-H
DDR CHANNEL B
DDR1_CKP_0/DDR1_CKP_0
DDR1_CKN_0/DDR1_CKN_0
DDR1_CKP_1/DDR1_CKP_1
DDR1_CKN_1/DDR1_CKN_1
DDR1_CKE_0/DDR1_CKE_0
DDR1_CKE_1/DDR1_CKE_1
DDR1_CKE_2/DDR1_CKE_2
DDR1_CKE_3/DDR1_CKE_3
DDR1_ODT_0/DDR1_ODT_0
DDR1_CAB_3/DDR1_MA_16
DDR1_CAB_2/DDR1_MA_14
DDR1_CAB_1/DDR1_MA_15
DDR1_CAB_7/DDR1_MA_10
DDR1_CAA_7/DDR1_MA_11
DDR1_CAA_6/DDR1_MA_12
DDR1_CAB_0/DDR1_MA_13
DDR1_DQSN_0/DDR0_DQSN_2
DDR1_DQSN_1/DDR0_DQSN_3
DDR1_DQSN_2/DDR0_DQSN_6
DDR1_DQSN_3/DDR0_DQSN_7
DDR1_DQSN_4/DDR1_DQSN_2
DDR1_DQSN_5/DDR1_DQSN_3
DDR1_DQSN_6/DDR1_DQSN_6
DDR1_DQSN_7/DDR1_DQSN_7
DDR1_DQSP_0/DDR0_DQSP_2
DDR1_DQSP_1/DDR0_DQSP_3
DDR1_DQSP_2/DDR0_DQSP_6
DDR1_DQSP_3/DDR0_DQSP_7
DDR1_DQSP_4/DDR1_DQSP_2
DDR1_DQSP_5/DDR1_DQSP_3
DDR1_DQSP_6/DDR1_DQSP_6
DDR1_DQSP_7/DDR1_DQSP_7
DDR1_DQSP_8/DDR1_DQSP_8
DDR1_DQSN_8/DDR1_DQSN_8
2 OF 13
LP3/DDR4
NC/DDR1_CKP_2
NC/DDR1_CKN_2
NC/DDR1_CKP_3
NC/DDR1_CKN_3
DDR1_CS#_0/DDR1_CS#_0
DDR1_CS#_1/DDR1_CS#_1
NC/DDR1_CS#_2
NC/DDR1_CS#_3
NC/DDR1_ODT_1
NC/DDR1_ODT_2
NC/DDR1_ODT_3
DDR1_CAB_4/DDR1_BA_0
DDR1_CAB_6/DDR1_BA_1
DDR1_CAA_5/DDR1_BG_0
DDR1_CAB_9/DDR1_MA_0
DDR1_CAB_8/DDR1_MA_1
DDR1_CAB_5/DDR1_MA_2
NC/DDR1_MA_3
NC/DDR1_MA_4
DDR1_CAA_0/DDR1_MA_5
DDR1_CAA_2/DDR1_MA_6
DDR1_CAA_4/DDR1_MA_7
DDR1_CAA_3/DDR1_MA_8
DDR1_CAA_1/DDR1_MA_9
DDR1_CAA_9/DDR1_BG_1
DDR1_CAA_8/DDR1_ACT#
NC/DDR1_PAR
NC/DDR1_ALERT#
DDR4(IL)/LP3-DDR4(NIL)
DDR_VREF_CA
DDR0_VREF_DQ
DDR1_VREF_DQ
AM9
AN9
AM7
AM8
AM11
AM10
AJ10
AJ11
AT8
AT10
AT7
AT11
AF11
AE7
AF10
AE10
AF7
AE8
AE9
AE11
AH10
AH11
AF8
AH8
AH9
AR9
AJ9
AK6
AK5
AL5
AL6
AM6
AN7
AN10
AN8
AR11
AH7
AN11
AR10
AF9
AR7
AT9
AJ7
AR8
BN9
BL9
BG9
BC9
AC9
W9
R9
M9
BP9
BJ9
BF9
BB9
AA9
V9
P9
L9
AW9
AY9
BN13
BP13
BR13
DDR_B_CLK0
DDR_B_CLK#0
DDR_B_CLK1DDR_A_CLK1
DDR_B_CKE0
DDR_B_CKE1
DDR_B_CS#0
DDR_B_CS#1
DDR_B_ODT0
DDR_B_ODT1
DDR_B_MA16
DDR_B_MA14
DDR_B_MA15
DDR_B_BA0
DDR_B_BA1
DDR_B_BG0
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_BG1
DDR_B_ACT#
DDR_B_PAR
DDR_B_ALERT#
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#6
DDR_A_DQS#7
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#6
DDR_B_DQS#7
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS6
DDR_A_DQS7
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS6
DDR_B_DQS7
+DDR_VREF_CA
1
PAD~D
+DDR_VREF_B_DQ
DDR_B_CLK0 <24>
DDR_B_CLK#0 <24>
DDR_B_CLK1 <24>
DDR_B_CKE0 <24>
DDR_B_CKE1 <24>
DDR_B_CS#0 <24>
DDR_B_CS#1 <24>
DDR_B_ODT0 <24>
DDR_B_ODT1 <24>
DDR_B_MA[0..16] <24>
DDR_B_BA0 <24>
DDR_B_BA1 <24>
DDR_B_BG0 <24>
DDR_B_BG1 <24>
DDR_B_ACT# <24>
DDR_B_PAR <24>
DDR_B_ALERT# <24>
DDR_A_DQS#2 <23>
DDR_A_DQS#3 <23>
DDR_A_DQS#6 <23>
DDR_A_DQS#7 <23>
DDR_B_DQS#2 <24>
DDR_B_DQS#3 <24>
DDR_B_DQS#6 <24>
DDR_B_DQS#7 <24>
DDR_A_DQS2 <23>
DDR_A_DQS3 <23>
DDR_A_DQS6 <23>
DDR_A_DQS7 <23>
DDR_B_DQS2 <24>
DDR_B_DQS3 <24>
DDR_B_DQS6 <24>
DDR_B_DQS7 <24>
@
T199
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2018/01/01
2018/01/01
2018/01/01
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2020/01/01
2020/01/01
2020/01/01
2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
CFL-H (3/8)
CFL-H (3/8)
CFL-H (3/8)
Size
Size
Size
Document Number Re v
Document Number Re v
Document Number Re v
B
B
B
LA-H171P
LA-H171P
LA-H171P
Friday, March 08, 2019
Friday, March 08, 2019
Friday, March 08, 2019
Date: Sheet o f
Date: Sheet o f
Date: Sheet o f
1
8 100
8 100
8 100
0.1
0.1
0.1
5
smd.db-x7.ru
D D
4
3
2
1
UC1D
CPU_DP1_P0<42>
CPU_DP1_N0<42>
CPU_DP1_P1<42>
CPU_DP1_N1<42>
AR P0
C C
AR P1
HDMI
B B
CPU_DP1_P2<42>
CPU_DP1_N2<42>
CPU_DP1_P3<42>
CPU_DP1_N3<42>
CPU_DP1_AUXP<42>
CPU_DP1_AUXN<42>
CPU_DP2_P0<42>
CPU_DP2_N0<42>
CPU_DP2_P1<42>
CPU_DP2_N1<42>
CPU_DP2_P2<42>
CPU_DP2_N2<42>
CPU_DP2_P3<42>
CPU_DP2_N3<42>
CPU_DP2_AUXP<42>
CPU_DP2_AUXN<42>
CPU_DP3_P0<40>
CPU_DP3_N0<40>
CPU_DP3_P1<40>
CPU_DP3_N1<40>
CPU_DP3_P2<40>
CPU_DP3_N2<40>
CPU_DP3_P3<40>
CPU_DP3_N3<40>
CPU_DP3_AUXP<40>
CPU_DP3_AUXN<40>
CPU_DP1_P0
CPU_DP1_N0
CPU_DP1_P1
CPU_DP1_N1
CPU_DP1_P2
CPU_DP1_N2
CPU_DP1_P3
CPU_DP1_N3
CPU_DP1_AUXP
CPU_DP1_AUXN
CPU_DP2_P0
CPU_DP2_N0
CPU_DP2_P1
CPU_DP2_N1
CPU_DP2_P2
CPU_DP2_N2
CPU_DP2_P3
CPU_DP2_N3
CPU_DP2_AUXP
CPU_DP2_AUXN
CPU_DP3_P0
CPU_DP3_N0
CPU_DP3_P1
CPU_DP3_N1
CPU_DP3_P2
CPU_DP3_N2
CPU_DP3_P3
CPU_DP3_N3
CPU_DP3_AUXP
CPU_DP3_AUXN
K36
DDI1_TXP_0
K37
DDI1_TXN_0
J35
DDI1_TXP_1
J34
DDI1_TXN_1
H37
DDI1_TXP_2
H36
DDI1_TXN_2
J37
DDI1_TXP_3
J38
DDI1_TXN_3
D27
DDI1_AUXP
E27
DDI1_AUXN
H34
DDI2_TXP_0
H33
DDI2_TXN_0
F37
DDI2_TXP_1
G38
DDI2_TXN_1
F34
DDI2_TXP_2
F35
DDI2_TXN_2
E37
DDI2_TXP_3
E36
DDI2_TXN_3
F26
DDI2_AUXP
E26
DDI2_AUXN
C34
DDI3_TXP_0
D34
DDI3_TXN_0
B36
DDI3_TXP_1
B34
DDI3_TXN_1
F33
DDI3_TXP_2
E33
DDI3_TXN_2
C33
DDI3_TXP_3
B33
DDI3_TXN_3
A27
DDI3_AUXP
B27
DDI3_AUXN
CFL-H_BGA1440
CFL-H
EDP_TXP_0
EDP_TXN_0
EDP_TXP_1
EDP_TXN_1
EDP_TXP_2
EDP_TXN_2
EDP_TXP_3
EDP_TXN_3
EDP_AUXP
EDP_AUXN
EDP_DISP_UTIL
DISP_RCOMP
PROC_AUDIO_CLK
PROC_AUDIO_SDI
PROC_AUDIO_SDO
4 of 13
D29
E29
F28
E28
A29
B29
C28
B28
C26
B26
A33
D37
G27
G25
G29
EDP_TXP0
EDP_TXN0
EDP_TXP1
EDP_TXN1
EDP_AUXP
EDP_AUXN
1
EDP_COMP
AUD_AZACPU_SCLK
AUD_AZACPU_SDO
AUD_AZACPU_SDI
@
T194
PAD~D
AUD_AZACPU_SDI AUD_AZACPU_SDI_R
EDP_TXP0 <38>
EDP_TXN0 <38>
EDP_TXP1 <38>
EDP_TXN1 <38>
EDP_AUXP <38>
EDP_AUXN <38>
AUD_AZACPU_SCLK <18>
AUD_AZACPU_SDO <18>
1 2
RC66 20_0402_5%
EDP_COMP
min Trace width=5 mils
,Spacing=20mil
Max length= 600 mils.
AUD_AZACPU_SDI_R <18>
+1.0VS_VCCIO
1 2
RC1 24.9_0402_1%
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
2018/01/01
2018/01/01
2018/01/01
3
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2020/01/01
2020/01/01
2020/01/01
2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
CFL-H (4/8)
CFL-H (4/8)
CFL-H (4/8)
Size
Size
Size
Document Number Re v
Document Number Re v
Document Number Re v
A
A
A
LA-H171P
LA-H171P
LA-H171P
Friday, March 08, 2019
Friday, March 08, 2019
Friday, March 08, 2019
Date : Sheet o f
Date : Sheet o f
Date : Sheet o f
1
9 100
9 100
9 100
0.1
0.1
0.1
5
smd.db-x7.ru
D D
C C
4
CFL-H
UC1M
1
T4PAD~D @
IST_TRIG
1
T3PAD~D @
1
T2PAD~D @
1
T1PAD~D @
1
T5PAD~D @
1
T6PAD~D @
1
T7PAD~D @
1
T9PAD~D @
1
T10PAD~D @
1
T11PAD~D @
1
T8PAD~D @
1
T14PAD~D @
1
T13PAD~D @
1
T15PAD~D @
1
T12PAD~D @
1
T28PAD~D @
1
T27PAD~D @
VSS_A36
VSS_A37
PCH_2_CPU_TRIGGER<20>
PCH_2_CPU_TRIGGER
CPU_2_PCH_TRIGGER_R
TP_SKL_F30
1
T285PAD~D @
TP_SKL_E30
1
T284PAD~D @
1
T18PAD~D @
1
T19PAD~D @
1
T21PAD~D @
1
T20PAD~D @
1
T23PAD~D @
1
T24PAD~D @
1
T22PAD~D @
BN35
BN33
BL34
AE29
AA14
AP29
AP14
BR35
BR31
BH30
E2
E3
E1
D1
BR1
BT2
J24
H24
N29
R14
A36
A37
H23
J23
F30
E30
B30
C30
G3
J3
RSVD_TP5
IST_TRIG
RSVD_TP4
RSVD_TP3
RSVD_TP1
RSVD_TP2
RSVD15
RSVD28
RSVD27
RSVD14
RSVD13
RSVD30
RSVD31
RSVD2
RSVD1
RSVD5
RSVD4
VSS_A36
VSS_A37
PROC_TRIGIN
PROC_TRIGOUT
RSVD24
RSVD23
RSVD7
RSVD21
RSVD26
RSVD29
RSVD19
RSVD18
RSVD9
CFL-H_BGA1440
13 OF 13
RSVD11
RSVD10
RSVD12
RSVD3
RSVD25
RSVD22
RSVD20
RSVD17
RSVD16
RSVD8
RSVD6
3
BK28
BJ28
BL31
AJ8
G13
C38
C1
BR2
BP1
B38
B2
1
T29 PAD~D@
1
T30 PAD~D@
1
T44 PAD~D@
1
T41 PAD~D@
1
T42 PAD~D@
1
T49 PAD~D@
1
T48 PAD~D@
1
T47 PAD~D@
1
T46 PAD~D@
1
T45 PAD~D@
1
T43 PAD~D@
2
1
B B
CPU_2_PCH_TRIGGER<20>
VSS_A36
VSS_A37
1 2
RC177 30_0402_5%
1 2
RC178 0_0402_5%@
1 2
RC179 0_0402_5%@
CPU_2_PCH_TRIGGER_RCPU_2_PCH_TRIGGER
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2018/01/01
2018/01/01
2018/01/01
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2020/01/01
2020/01/01
2020/01/01
2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
CFL-H (5/8)
CFL-H (5/8)
CFL-H (5/8)
Size
Size
Size
Document Number Re v
Document Number Re v
Document Number Re v
B
B
B
LA-H171P
LA-H171P
LA-H171P
Friday, March 08, 2019
Friday, March 08, 2019
Friday, March 08, 2019
Date: Sheet o f
Date: Sheet o f
Date: Sheet o f
1
10 100
10 100
10 100
0.1
0.1
0.1
5
smd.db-x7.ru
4
3
2
1
+GT_CORE
AT14
AT31
AT32
AT33
AT34
D D
C C
B B
AT35
AT36
AT37
AT38
AU14
AU29
AU30
AU31
AU32
AU35
AU36
AU37
AU38
AV29
AV30
AV31
AV32
AV33
AV34
AV35
AV36
AW14
AW31
AW32
AW33
AW34
AW35
AW36
AW37
AW38
AY29
AY30
AY31
AY32
AY35
AY36
AY37
AY38
BA13
BA14
BA29
BA30
BA31
BA32
BA33
BA34
BA35
BA36
BB13
BB14
BB31
BB32
BB33
BB34
BB35
BB36
BB37
BB38
BC29
BC30
BC31
BC32
BC35
BC36
BC37
BC38
BD13
BD14
BD29
BD30
BD31
BD32
BD33
BD34
BP37
BP38
BR15
BR16
BR17
UC1K
VCCGT1
VCCGT2
VCCGT3
VCCGT4
VCCGT5
VCCGT6
VCCGT7
VCCGT8
VCCGT9
VCCGT10
VCCGT11
VCCGT12
VCCGT13
VCCGT14
VCCGT15
VCCGT16
VCCGT17
VCCGT18
VCCGT19
VCCGT20
VCCGT21
VCCGT22
VCCGT23
VCCGT24
VCCGT25
VCCGT26
VCCGT27
VCCGT28
VCCGT29
VCCGT30
VCCGT31
VCCGT32
VCCGT33
VCCGT34
VCCGT35
VCCGT36
VCCGT37
VCCGT38
VCCGT39
VCCGT40
VCCGT41
VCCGT42
VCCGT43
VCCGT44
VCCGT45
VCCGT46
VCCGT47
VCCGT48
VCCGT49
VCCGT50
VCCGT51
VCCGT52
VCCGT53
VCCGT54
VCCGT55
VCCGT56
VCCGT57
VCCGT58
VCCGT59
VCCGT60
VCCGT61
VCCGT62
VCCGT63
VCCGT64
VCCGT65
VCCGT66
VCCGT67
VCCGT68
VCCGT69
VCCGT70
VCCGT71
VCCGT72
VCCGT73
VCCGT74
VCCGT75
VCCGT76
VCCGT77
VCCGT78
VCCGT79
VCCGT159
VCCGT160
VCCGT161
VCCGT162
VCCGT163
CFL-H_BGA1440
CFL-H
VSSGT_SENSE
11 OF 13
VCCGT_SENSE
VCCGT80
VCCGT81
VCCGT82
VCCGT83
VCCGT84
VCCGT85
VCCGT86
VCCGT87
VCCGT88
VCCGT89
VCCGT90
VCCGT91
VCCGT92
VCCGT93
VCCGT94
VCCGT95
VCCGT96
VCCGT97
VCCGT98
VCCGT99
VCCGT100
VCCGT101
VCCGT102
VCCGT103
VCCGT104
VCCGT105
VCCGT106
VCCGT107
VCCGT108
VCCGT109
VCCGT110
VCCGT111
VCCGT112
VCCGT113
VCCGT114
VCCGT115
VCCGT116
VCCGT117
VCCGT118
VCCGT119
VCCGT120
VCCGT121
VCCGT122
VCCGT123
VCCGT124
VCCGT125
VCCGT126
VCCGT127
VCCGT128
VCCGT129
VCCGT130
VCCGT131
VCCGT132
VCCGT133
VCCGT134
VCCGT135
VCCGT136
VCCGT137
VCCGT138
VCCGT139
VCCGT140
VCCGT141
VCCGT142
VCCGT143
VCCGT144
VCCGT145
VCCGT146
VCCGT147
VCCGT148
VCCGT149
VCCGT150
VCCGT151
VCCGT152
VCCGT153
VCCGT154
VCCGT155
VCCGT156
VCCGT157
VCCGT158
VCCGT164
VCCGT165
VCCGT166
VCCGT167
VCCGT168
A A
BD35
BD36
BE31
BE32
BE33
BE34
BE35
BE36
BE37
BE38
BF13
BF14
BF29
BF30
BF31
BF32
BF35
BF36
BF37
BF38
BG29
BG30
BG31
BG32
BG33
BG34
BG35
BG36
BH33
BH34
BH35
BH36
BH37
BH38
BJ16
BJ17
BJ19
BJ20
BJ21
BJ23
BJ24
BJ26
BJ27
BJ37
BJ38
BK16
BK17
BK19
BK20
BK21
BK23
BK24
BK26
BK27
BL15
BL16
BL17
BL23
BL24
BL25
BL26
BL27
BL28
BL36
BL37
BM15
BM16
BM17
BM36
BM37
BN15
BN16
BN17
BN36
BN37
BN38
BP15
BP16
BP17
BR37
BT15
BT16
BT17
BT37
AH37
AH38
+GT_CORE
VSS_SENSE_GT <88>
VCC_SENSE_GT <88>
+1.0VS_VCCIO
+SA_CORE
CPU_C10_GATE#<14,87>
CFL-H
UC1L
J30
VCCSA1
K29
VCCSA2
K30
VCCSA3
K31
VCCSA4
K32
VCCSA5
K33
VCCSA6
K34
VCCSA7
K35
VCCSA8
L31
VCCSA9
L32
VCCSA10
L35
VCCSA11
L36
VCCSA12
L37
VCCSA13
L38
VCCSA14
M29
VCCSA15
M30
VCCSA16
M31
VCCSA17
M32
VCCSA18
M33
VCCSA19
M34
VCCSA20
M35
VCCSA21
M36
VCCSA22
AG12
VCCIO1
G15
VCCIO2
G17
VCCIO3
G19
VCCIO4
G21
VCCIO5
H15
VCCIO6
H16
VCCIO7
H17
VCCIO8
H19
VCCIO9
H20
VCCIO10
H21
VCCIO11
H26
VCCIO12
H27
VCCIO13
J15
VCCIO14
J16
VCCIO15
J17
VCCIO16
J19
VCCIO17
J20
VCCIO18
J21
VCCIO19
J26
VCCIO20
J27
VCCIO21
CFL-H_BGA1440
+1.8V_PRIM_PCH
RZ543
10K_0402_5%
1 2
+1.0V_VCCSTG +1.0V_VCCST
RZ151 0_0402_5%@
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18
VDDQ19
VDDQ20
VDDQ21
VDDQ22
VDDQ23
VDDQ24
VDDQ25
VCCPLL_OC1
VCCPLL_OC2
VCCPLL_OC3
VCCST
VCCSTG2
VCCSTG1
VCCPLL1
VCCPLL2
VCCSA_SENSE
VSSSA_SENSE
VCCIO_SENSE
VSSIO_SENSE
12 OF 13
UZ61
1
NC
VCC
2
A
3
GND
74AUP1G07GW_TSSOP5
1 2
Y
+1.2V_MEM
12A
AA6
AE12
AF5
AF6
AG5
AG9
AJ12
AL11
AP6
AP7
AR12
AR6
AT12
AW6
AY6
J5
J6
K12
K6
L12
L6
R6
T6
W6
Y12
BH13
BJ13
G11
H30
H29
G30
H28
J28
M38
M37
H14
J14
+1.8V_PRIM +3.3V_RUN
12
@
CZ544
1 2
0.1U_0402_25V6
5
C10_PWR_GATE#
4
SIO_SLP_S0#<18,19,66,67,87>
+VCC_SFR_OC
+VCC_SFR_OC
+1.0V_VCCST
+1.0V_VCCSTG
+VCC_FUSEPRG
+1.0V_VCCSFR_R
VCC_SENSE_SA <88>
VSS_SENSE_SA <88>
VCCIO_SENSE <87>
VSSIO_SENSE <87>
RZ542
10K_0402_5%
1 2
RH620 0_0402_5%@
1 2
RH619 0_0402_5%@
1
2
CC322
RF@
2.2P_0402_50V8C
RF Request
+VCCPLL_OC source
downsize to SE00000UC00
CZ102 1U_0201_6.3V6M
VCCSTG_EN
PCH_PRIM_EN<18,78,87>
SIO_SLP_S4#<11,18,19,86,87>
RZ120 0_0402_5%@
1 2
+3.3V_ALW
5
1
B
2
A
3
+1.0V_VCCSTG source
downsize to SE00000UC00
+3.3V_ALW
RZ320 0_0402_5%@
+5V_ALW
1
CZ100
1U_0201_6.3V6M
2
1
IN1
2
IN2
1 2
+1.0V_PRIM
5
3
C10_PWR_GATE#_R
RUN_ON<58,59,78,87>
MC74VHC1G08DFT2G_SC70-5
UZ35
downsize to SE00000UC00
SIO_SLP_S4#<11,18,19,86,87>
+1.2V_MEM
1
12
+5V_ALW
@
CZ104
1 2
0.1U_0402_10V7K
P
4
Y
G
UZ34
@
MC74VHC1G08DFT2G_SC70-5
+1.0V_PRIM
+5V_ALW
1
CZ105
1U_0201_6.3V6M
2
P
VCCSTG_EN
4
O
G
2
7
3
4
material shortage
SA00007XR00 change to SA00008A800
UZ19
1
2
7
3
4
AOZ1334DI-01_DFN8-7_3X3
3.9mohm /10A
TR=11us@Vin=1.05V
+1.0V_VCCST source
UZ21
1
VIN1
2
VIN2
7
VIN thermal
3
VBIAS
4
ON
AOZ1334DI-01_DFN8-7_3X3
3.9mohm /10A
TR=11us@Vin=1.05V
material shortage
SA00007XR00 change to SA00008A800
PDDG page19, if don`t support DS3, contact to VDDQ directly
+VCC_SFR_OC
1 2
RZ119 0_0402_5%@
UZ26
VIN1
VIN2
VIN thermal
VBIAS
ON
AOZ1334DI-01_DFN8-7_3X3
VIN1
VIN2
VIN thermal
VBIAS
ON
material shortage
SA00007XR00 change to SA00008A800
6
VOUT
5
GND
6
VOUT
5
GND
+1.0V_VCCSTG
6
VOUT
5
GND
+1.0V_VCCST_C
1
2
RC326 0_0402_5%@
12
JUMP@
PAD-OPEN1x1m
+1.0V_VCCSTG_C
JUMP@
PAD-OPEN1x1m
0.1U_0402_10V7K
CZ101
CZ103 0.1U_0201_10V6K
PJP2
+1.0V_VCCST
PJP1
1 2
+VCC_FUSEPRG
12
1 2
CZ106 0.1U_0402_10V7K
+1.0V_VCCSFR
12
1 2
RC304 0_0402_5%@
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2018/01/01
2018/01/01
2018/01/01
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2020/01/01
2020/01/01
2020/01/01
2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
CFL-H (6/8)
CFL-H (6/8)
CFL-H (6/8)
Size
Size
Size
Document Number Re v
Document Number Re v
Document Number Re v
B
B
B
LA-H171P
LA-H171P
LA-H171P
Monday, March 11, 2019
Monday, March 11, 2019
Monday, March 11, 2019
Date: Sheet o f
Date: Sheet o f
Date: Sheet o f
1
11 100
11 100
11 100
0.1
0.1
0.1
5
smd.db-x7.ru
4
3
2
1
FOLLOW PDG V1P8 P.616 downsize to SE00000UD00
11x 10uF 0402
D D
For SKL-H 4+2
Remove VCCOPC/VCCEOPIO/
VCCOPC_1P8 Cap
C C
+1.2V_MEM
B B
+1.2V_MEM DECOUPLING
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
CC161
1
1
2
2
22U_0603_6.3V6M
12
CC81
10U_0402_6.3V6M
CC170
CC164
CC168
1
1
2
2
22U_0603_6.3V6M
22U_0603_6.3V6M
12
12
12
CC83
CC82
10U_0402_6.3V6M
CC163
1
2
22U_0603_6.3V6M
CC84
+1.2V_MEM +1.0V_VCCSTG +1.0V_VCCSFR_R +1.0V_VCCST +VCC_SFR_OC
10U_0402_6.3V6M
CC185
1
2
close to UC1.Y12
+1.0VS_VCCIO
PLACE CAP BACKSIDE
10U_0402_6.3V6M
10U_0402_6.3V6M
CC188
CC189
1
1
2
2
+1.0V_VCCST
1 2
FOLLOW PDG V1P8 P.616 downsize to SE00000UC00
1x 1uF 0201
PLACE CAP BACKSIDE
10U_0402_6.3V6M
10U_0402_6.3V6M
CC166
CC171
1
2
FOLLOW PDG V1P8 P.616 downsize to SE00000UD00
11x 10uF 0402
1
1
2
2
FOLLOW PDG V1P8 P.616 downsize to SE00000UD00
3x 10uF 0402
3x 0402 placeholder
1U_0201_6.3V6M
1U_0201_6.3V6M
CC193
CC194
1 2
10U_0402_6.3V6M
10U_0402_6.3V6M
CC165
CC172
1
1
2
2
10U_0402_6.3V6M
2
1
1
2
CC167
1U_0201_6.3V6M
CC186
10U_0402_6.3V6M
CC187
PLACE CAP BACKSIDE
1U_0201_6.3V6M
@
2
CC195
1
10U_0402_6.3V6M
10U_0402_6.3V6M
@
CC272
1
1
2
2
A00
follow Berlineeta add 22uF to solve PS4 idle hang
location:CC568 CC569
1U_0201_6.3V6M
2
CC192
1
10U_0402_6.3V6M
@
CC500
1
2
@
CC501
1U_0201_6.3V6M
2
1
+1.0V_VCCSFR
22U_0603_6.3V6M
@
2
CC191
CC569
1
LC562
BLM18EG221TN1D_2P~D
1 2
RC422
@
0.01_0603_1%
1 2
1U_0201_6.3V6M
1U_0201_6.3V6M
2
2
CC209
CC210
1
1
PLACE CAP BACKSIDE or BOARD EDGE
+1.0V_VCCSFR_R
PDG rev1.0
Remove to Power (+VCC_SA cap)
+1.0V_VCCSTG
0.1U_0201_10V6K
0.1U_0201_10V6K
@ESD@
@ESD@
1
1
CC557
CC558
2
2
ESD request 7/25
+IA_CORE
+IA_CORE
22U_0603_6.3V6M
@
2
CC568
1
22U_0603_6.3V6M
2
CC333
1
K14
L13
L14
N13
N14
N30
N31
N32
N35
N36
N37
N38
P13
P14
P29
P30
P31
P32
P33
P34
P35
P36
R13
R31
R32
R33
R34
R35
R36
R37
R38
T29
T30
T31
T32
T35
T36
T37
T38
U29
U30
U31
U32
U33
U34
U35
U36
V13
V14
V31
V32
V33
V34
V35
V36
V37
V38
W13
W14
W29
W30
W31
W32
UC1J
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
CFL-H_BGA1440
CFL-H
10 OF 13
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75
+IA_CORE
W35
W36
W37
W38
Y29
Y30
Y31
Y32
Y33
Y34
Y35
Y36
AA13
AA31
AA32
AA33
AA34
AA35
AA36
AA37
AA38
AB29
AB30
AB31
AB32
AB35
AB36
AB37
AB38
AC13
AC14
AC29
AC30
AC31
AC32
AC33
AC34
AC35
AC36
AD13
AD14
AD31
AD32
AD33
AD34
AD35
AD36
AD37
AD38
AE13
AE14
AE30
AE31
AE32
AE35
AE36
AE37
AE38
AF29
AF30
AF31
AF32
AF33
AF34
AF35
AF36
AF37
AF38
AG14
AG31
AG32
AG33
AG34
AG35
AG36
UC1I
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
CFL-H_BGA1440
CFL-H
9 OF 13
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75
VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC82
VCC83
VCC84
VCC85
VCC86
VCC87
VCC88
VCC89
VCC90
VCC91
VCC92
VCC93
VCC94
VCC95
VCC96
VCC97
VCC98
VCC99
VCC100
VCC101
VCC102
VCC103
VCC104
VCC105
VCC106
VCC107
VCC108
VCC109
VCC110
VCC111
VCC112
VCC113
VCC114
VCC115
VCC116
VCC117
VCC118
VCC119
VCC120
VCC121
VCC122
VCC123
VCC124
VCC_SENSE
VSS_SENSE
AH13
AH14
AH29
AH30
AH31
AH32
AJ14
AJ29
AJ30
AJ31
AJ32
AJ33
AJ34
AJ35
AJ36
AK31
AK32
AK33
AK34
AK35
AK36
AK37
AK38
AL13
AL29
AL30
AL31
AL32
AL35
AL36
AL37
AL38
AM13
AM14
AM29
AM30
AM31
AM32
AM33
AM34
AM35
AM36
AN13
AN14
AN31
AN32
AN33
AN34
AN35
AN36
AN37
AN38
AP13
AP30
AP31
AP32
AP35
AP36
AP37
AP38
K13
AG37
AG38
+IA_CORE
VCC_SENSE_IA
VSS_SENSE_IA
+IA_CORE
100_0201_1%
12
RC140
100_0201_1%
12
RC141
VCC_SENSE_IA <88>
VSS_SENSE_IA <88>
VSS_SENSE_IA VCC_SENSE_IA
RC221 49.9_0201_1%@
1 2
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2018/01/01
2018/01/01
2018/01/01
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2020/01/01
2020/01/01
2020/01/01
2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
CFL-H (7/8)
CFL-H (7/8)
CFL-H (7/8)
Size
Size
Size
Document Number Re v
Document Number Re v
Document Number Re v
B
B
B
LA-H171P
LA-H171P
LA-H171P
Wednesday, March 20, 2019
Wednesday, March 20, 2019
Wednesday, March 20, 2019
Date: Sheet o f
Date: Sheet o f
Date: Sheet o f
1
12 100
12 100
12 100
0.1
0.1
0.1
5
smd.db-x7.ru
4
3
2
1
CFL-H
UC1F
A10
VSS_1
A12
VSS_2
A16
VSS_3
A18
VSS_4
A20
VSS_5
A22
VSS_6
A24
D D
C C
B B
A26
A28
A30
AA12
AA29
AA30
AB33
AB34
AB6
AC1
AC12
AC2
AC3
AC37
AC38
AC4
AC5
AC6
AD10
AD11
AD12
AD29
AD30
AD6
AD8
AD9
AE33
AE34
AE6
AF1
AF12
AF13
AF14
AF2
AF3
AF4
AG10
AG11
AG13
AG29
AG30
AG6
AG7
AG8
AH12
AH33
AH34
AH35
AH36
AH6
AJ1
AJ13
AJ2
AJ3
AJ37
AJ38
AJ4
AJ5
AJ6
Y10
Y11
Y13
Y14
Y37
Y38
AK29
AK30
A6
A9
W4
W5
Y7
Y8
Y9
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
6 OF 13
VSS_81
CFL-H_BGA1440
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
AK4
AL10
AL12
AL14
AL33
AL34
AL4
AL7
AL8
AL9
AM1
AM12
AM2
AM3
AM37
AM38
AM4
AM5
AN12
AN29
AN30
AN5
AN6
AP10
AP11
AP12
AP33
AP34
AP8
AP9
AR1
AR13
AR14
AR2
AR29
AR3
AR30
AR31
AR32
AR33
AR34
AR35
AR36
AR37
AR38
AR4
AR5
AT29
AT30
AT6
AU10
AU11
AU12
AU33
AU34
AU6
AU7
AU8
AU9
AV37
AV38
AW1
AW12
AW2
AW29
AW3
AW30
AW4
U6
V12
V29
V30
A14
AD7
V6
W1
W12
W2
W3
W33
W34
AW5
AY12
AY33
AY34
BA10
BA11
BA12
BA37
BA38
BA6
BA7
BA8
BA9
BB1
BB12
BB2
BB29
BB3
BB30
BB4
BB5
BB6
BC12
BC13
BC14
BC33
BC34
BC6
BD10
BD11
BD12
BD37
BD6
BD7
BD8
BD9
BE1
BE2
BE29
BE3
BE30
BE4
BE5
BE6
BF12
BF33
BF34
BF6
BG12
BG13
BG14
BG37
BG38
BG6
BH1
BH10
BH11
BH12
BH14
BH2
BH3
BH4
BH5
BH6
BH7
BH8
BH9
U37
U38
BJ12
BJ14
T33
T34
UC1G
VSS_163
VSS_164
VSS_165
VSS_166
B9
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
T2
VSS_231
T3
VSS_232
VSS_233
VSS_234
T4
VSS_235
T5
VSS_236
T7
VSS_237
T8
VSS_238
T9
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
CFL-H_BGA1440
CFL-H
7 OF 13
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273
VSS_274
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
BJ15
BJ18
BJ22
BJ25
BJ29
BJ30
BJ31
BJ32
BJ33
BJ34
BJ35
BJ36
BK13
BK14
BK15
BK18
BK22
BK25
BK29
BK6
BL13
BL14
BL18
BL19
BL20
BL21
BL22
BL29
BL33
BL35
BL38
BL6
BM11
BM12
BM13
BM14
BM18
BM2
BM21
BM22
BM23
BM24
BM25
BM26
BM27
BM28
BM29
BM3
BM33
BM35
BM38
BM5
BM6
BM7
BM8
BM9
BN12
BN14
BN18
BN19
BN2
BN20
BN21
BN24
BN29
BN30
BN31
BN34
P38
P6
R12
R29
AY14
BD38
R30
T1
T10
T11
T12
T13
T14
BN4
BN7
BP12
BP14
BP18
BP21
BP24
BP25
BP26
BP29
BP33
BP34
BP7
BR12
BR14
BR18
BR21
BR24
BR25
BR26
BR29
BR34
BR36
BR7
BT12
BT14
BT18
BT21
BT24
BT26
BT29
BT32
BT5
C11
C13
C15
C17
C19
C21
C23
C25
C27
C29
C31
C37
D10
D12
D14
D16
D18
D20
D22
D24
D26
D28
D30
D33
E34
E35
E38
N33
N34
P12
P37
M14
F11
F13
M6
N1
UC1H
VSS_325
VSS_326
VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350
VSS_351
VSS_352
VSS_353
VSS_354
VSS_355
VSS_356
VSS_357
VSS_358
VSS_359
VSS_360
VSS_361
VSS_362
VSS_363
VSS_364
VSS_365
VSS_366
VSS_367
VSS_368
VSS_369
C5
VSS_370
C8
VSS_371
C9
VSS_372
VSS_373
VSS_374
VSS_375
VSS_376
VSS_377
VSS_378
VSS_379
VSS_380
VSS_381
VSS_382
D3
VSS_383
VSS_384
VSS_385
D6
VSS_386
D9
VSS_387
VSS_388
VSS_389
VSS_390
E4
VSS_391
E9
VSS_392
N3
VSS_393
VSS_394
VSS_395
N4
VSS_396
N5
VSS_397
N6
VSS_398
N7
VSS_399
N8
VSS_400
N9
VSS_401
VSS_402
VSS_403
VSS_404
VSS_405
VSS_406
VSS_407
VSS_408
CFL-H_BGA1440
CFL-H
VSS_409
VSS_410
VSS_411
VSS_412
VSS_413
VSS_414
VSS_415
VSS_416
VSS_417
VSS_418
VSS_419
VSS_420
VSS_421
VSS_422
VSS_423
VSS_424
VSS_425
VSS_426
VSS_427
VSS_428
VSS_429
VSS_430
VSS_431
VSS_432
VSS_433
VSS_434
VSS_435
VSS_436
VSS_437
VSS_438
VSS_439
VSS_440
VSS_441
VSS_442
VSS_443
VSS_444
VSS_445
VSS_446
VSS_447
VSS_448
VSS_449
VSS_450
VSS_451
VSS_452
VSS_453
VSS_454
VSS_455
VSS_456
VSS_457
VSS_458
VSS_459
VSS_460
VSS_461
VSS_462
VSS_463
VSS_464
VSS_465
VSS_466
VSS_467
VSS_468
VSS_469
VSS_470
VSS_471
VSS_472
VSS_473
VSS_474
VSS_475
VSS_476
VSS_477
VSS_478
VSS_479
VSS_A3
VSS_A34
VSS_A4
VSS_B3
VSS_B37
VSS_BR38
VSS_BT3
VSS_BT35
VSS_BT36
VSS_BT4
VSS_C2
8 OF 13
VSS_D38
F15
F17
F19
F2
F21
F23
F25
F27
F29
F3
F31
F36
F4
F5
F8
F9
G10
G12
G14
G16
G18
G20
G22
G23
G24
G26
G28
G4
G5
G6
G8
G9
H11
H12
H18
H22
H25
H32
H35
J10
J18
J22
J25
J32
J33
J36
J4
J7
K1
K10
K11
K2
K3
K38
K4
K5
K7
K8
K9
L29
L30
L33
L34
M12
M13
N10
N11
N12
N2
BT8
BR9
A3
A34
A4
B3
B37
BR38
BT3
BT35
BT36
BT4
C2
D38
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
2018/01/01
2018/01/01
2018/01/01
3
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2020/01/01
2020/01/01
2020/01/01
2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
CFL-H (8/8)
CFL-H (8/8)
CFL-H (8/8)
Size
Size
Size
Document Number Re v
Document Number Re v
Document Number Re v
A
A
A
LA-H171P
LA-H171P
LA-H171P
Friday, March 08, 2019
Friday, March 08, 2019
Friday, March 08, 2019
Date : Sheet o f
Date : Sheet o f
Date : Sheet o f
1
13 100
13 100
13 100
0.1
0.1
0.1
5
smd.db-x7.ru
D D
+1.8V_PRIM
RH614 20K_0402_5%
RH613 20K_0402_5%
CFL PDG rev0.5
To avoid floating input at the I/O pin it is recommended
to add a weak pull up resistor to the SOC pin with a recommended value of 20K ohm.
1 2
1 2
CNV_BRI_PRX_DTX
CNV_RGI_PRX_DTX
CNV_BRI_PTX_DRX_R<52>
CNV_RGI_PTX_DRX_R<52>
RZ1384 33_0402_5%
RZ1382 33_0402_5%
1 2
1 2
4
GPP_J1
AW13
AV13
AR13
AT10
BE9
BF8
BF9
BG8
BE8
BD8
AP3
AP2
AN4
AM7
AV6
AY3
AV7
AW3
AV4
AY2
BA4
AV3
AW2
AU9
UH1M
GPP_G0/SD_CMD
GPP_G1/SD_DATA0
GPP_G2/SD_DATA1
GPP_G3/SD_DATA2
GPP_G4/SD_DATA3
GPP_G5/SD_CD#
GPP_G6/SD_CLK
GPP_G7/SD_WP
GPP_I11/M2_SKT2_CFG0
GPP_I12/M2_SKT2_CFG1
GPP_I13/M2_SKT2_CFG2
GPP_I14/M2_SKT2_CFG3
GPP_J0/CNV_PA_BLANKING
GPP_J1/CPU_C10_GATE#
GPP_J11/A4WP_PRESENT
GPP_J10
GPP_J_2
GPP_J_3
GPP_J4/CNV_BRI_DT/UART0B_RTS#
GPP_J5/CNV_BRI_RSP/UART0B_RXD
GPP_J6/CNV_RGI_DT/UART0B_TXD
GPP_J7/CNV_RGI_RSP/UART0B_CTS#
GPP_J8/CNV_MFUART2_RXD
GPP_J9/CNV_MFUART2_TXD
CNP-H_BGA874
CAM_MIC_CBL_DET#<38>
TBT_CIO_PLUG_EVENT#<42>
CONTACTLESS_DET#<66>
HOST_SD_WP#<70>
CNV_COEX3<52>
CPU_C10_GATE#<11,87>
CNV_BRI_PRX_DTX<52>
CNV_RGI_PRX_DTX<52>
CNV_COEX2<52>
CNV_COEX1<52>
CAM_MIC_CBL_DET#
TBT_CIO_PLUG_EVENT#
CONTACTLESS_DET#
HOST_SD_WP#
AUD_PWR_EN
1 2
RH616@ 0_0402_5%
CNV_BRI_PTX_DRX
CNV_BRI_PRX_DTX
CNV_RGI_PTX_DRX
CNV_RGI_PRX_DTX
CNV_COEX2
CNV_COEX1
CNP-H
13 OF 13
3
CNV_WR_CLKN
CNV_WR_CLKP
CNV_WR_D0N
CNV_WR_D0P
CNV_WR_D1N
CNV_WR_D1P
CNV_WT_CLKN
CNV_WT_CLKP
CNV_WT_D0N
CNV_WT_D0P
CNV_WT_D1N
CNV_WT_D1P
CNV_WT_RCOMP
PCIE_RCOMPN
PCIE_RCOMPP
SD_1P8_RCOMP
SD_3P3_RCOMP
GPPJ_RCOMP_1P81
GPPJ_RCOMP_1P82
GPPJ_RCOMP_1P83
RSVD2
RSVD3
RSVD1
TP
Rev1.0
BD4
BE3
BB3
BB4
BA3
BA2
BC5
BB6
BE6
BD7
BG6
BF6
BA1
B12
A13
BE5
BE4
BD1
BE1
BE2
Y35
Y36
BC1
AL35
CLK_CNV_PRX_DTX_N
CLK_CNV_PRX_DTX_P
CNV_PRX_DTX_N0
CNV_PRX_DTX_P0
CNV_PRX_DTX_N1
CNV_PRX_DTX_P1
CLK_CNV_PTX_DRX_N
CLK_CNV_PTX_DRX_P
CNV_PTX_DRX_N0
CNV_PTX_DRX_P0
CNV_PTX_DRX_N1
CNV_PTX_DRX_P1CNV_COEX3
CNV_WT_RCOMP
PCIECOMP#
PCIECOMP
SD_RCOMP_1P8
SD_RCOMP_3P3
GPPJ_RCOMP
1
1
1
1
CLK_CNV_PRX_DTX_N <52>
CLK_CNV_PRX_DTX_P <52>
CNV_PRX_DTX_N0 <52>
CNV_PRX_DTX_P0 <52>
CNV_PRX_DTX_N1 <52>
CNV_PRX_DTX_P1 <52>
CLK_CNV_PTX_DRX_N <52>
CLK_CNV_PTX_DRX_P <52>
CNV_PTX_DRX_N0 <52>
CNV_PTX_DRX_P0 <52>
CNV_PTX_DRX_N1 <52>
CNV_PTX_DRX_P1 <52>
12
RH612 150_0402_1%
12
RH192 100_0402_1%
12
12
RH611 200_0402_1%
200_0402_1%
RH610
12
RH609 200_0402_1%
T34 PAD~D@
T33 PAD~D@
T36 PAD~D@
T35 PAD~D@
2
+1.8V_PRIM
@
RH607
100K_0402_5%
CNV_COEX1
VCCSPI hard strap
HIGH 1.8V
LOW
1 2
12
RH608
100K_0402_5%
3.3V
1
+1.8V_PRIM
RH604
4.7K_0402_5%
24MHz
1 2
12
+1.8V_PRIM
1 2
12
RH603
@
10K_0402_5%
RH605
20K_0402_5%
@
RH606
100K_0402_5%
CNV_BRI_PTX_DRX
Xtal Frequency select
HIGH
38.4/19.2MHz
LOW
(default)
CNP EDS rev0.7
An external pull-up is required on this strap
since 38.4 MHz XTAL is not supported on the PCH.
CNV_RGI_PTX_DRX
M.2 CNV Mode Select
Integrated CNVi
HIGH
disable
Integrated CNVi
LOW
enable
C C
+3.3V_RUN
CAM_MIC_CBL_DET#
1 2
RH319 10K_0402_5%
RH318 10K_0402_5%
RH214 100K_0402_5%
RH324 10K_0402_5%
RH76 10K_0402_5%
RH344 10K_0402_5%
RH90 10K_0402_5%
1 2
RH345 10K_0402_5%
@
B B
RH316 10K_0201_5%@
RH317 10K_0402_5%@
RH323 10K_0402_5%
RH377 10K_0402_5%
RH325 10K_0402_5%
RH326 10K_0402_5%@
RC558
@
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
12
100K_0402_5%
M2280_PCIE_SATA#
HOST_SD_WP#
HDD_DET#
BIOS_REC
m3042_PCIE#_SATA
CONTACTLESS_DET#
AUD_PWR_EN
SATAGP0
M2280_PCIE_SATA#
SATAGP3
SATAGP0
SATAGP5
SATAGP6
PCH_TBT_PERST#
M.2 Socket 3 (Key M)
M.2 Socket 3 (Key M)
PCH_CL_CLK1<52>
PCH_CL_DATA1<52>
PCH_CL_RST1#<52>
PCIE_PTX_DRX_P11<68>
PCIE_PTX_DRX_N11<68>
PCIE_PRX_DTX_P11<68>
PCIE_PRX_DTX_N11<68>
PCIE_PTX_DRX_P12<68>
PCIE_PTX_DRX_N12<68>
PCIE_PRX_DTX_P12<68>
PCIE_PRX_DTX_N12<68>
PCH_CL_CLK1
PCH_CL_DATA1
PCH_CL_RST1#
PCIE_PTX_DRX_P11
PCIE_PTX_DRX_N11
PCIE_PRX_DTX_P11
PCIE_PRX_DTX_N11
BIOS_REC
PCIE_PTX_DRX_P12
PCIE_PTX_DRX_N12
PCIE_PRX_DTX_P12
PCIE_PRX_DTX_N12
UH1C
AR2
CL_CLK
AT5
CL_DATA
AU4
CL_RST#
P48
GPP_K8
V47
GPP_K9
V48
GPP_K10
W47
GPP_K11
L47
GPP_K0
L46
GPP_K1
U48
GPP_K2
U47
GPP_K3
N48
GPP_K4
N47
GPP_K5
P47
GPP_K6
R46
GPP_K7
C36
PCIE11_TXP/SATA0A_TXP
B36
PCIE11_TXN/SATA0A_TXN
F39
PCIE11_RXP/SATA0A_RXP
G38
PCIE11_RXN/SATA0A_RXN
AR42
GPP_F10/SATA_SCLOCK
AR48
GPP_F11/SATA_SLOAD
AU47
GPP_F13/SATA_SDATAOUT0
AU46
GPP_F12/SATA_SDATAOUT1
C39
PCIE14_TXN/SATA1B_TXN
D39
PCIE14_TXP/SATA1B_TXP
D46
PCIE14_RXN/SATA1B_RXN
C47
PCIE14_RXP/SATA1B_RXP
B38
PCIE13_TXN/SATA0B_TXN
C38
PCIE13_TXP/SATA0B_TXP
C45
PCIE13_RXN/SATA0B_RXN
C46
PCIE13_RXP/SATA0B_RXP
E37
PCIE12_TXP/SATA1A_TXP
D38
PCIE12_TXN/SATA1A_TXN
J41
PCIE12_RXP/SATA_1A_RXP
H42
PCIE12_RXN/SATA1A_RXN
B44
PCIE20_TXP/SATA7_TXP
A44
PCIE20_TXN/SATA7_TXN
R37
PCIE20_RXP/SATA7_RXP
R35
PCIE20_RXN/SATA7_RXN
D43
PCIE19_TXP/SATA6_TXP
C44
PCIE19_TXN/SATA6_TXN
N42
PCIE19_RXP/SATA6_RXP
M44
PCIE19_RXN/SATA6_RXN
CNP-H_BGA874
SPSGP0
+3.3V_ALW_PCH
RTD3@
PCH_TBT_PERST#
12
RC557 100K_0402_5%
SPSGP1
SPSGP2
SPSGP3 1=SATA 0=PCIE
SPSGP5 0=PCIESPTAGP5
A A
CNP-H
PCIE15_RXN/SATA2_RXN
PCIE15_RXP/SATA2_RXP
PCIE_15_SATA_2_TXN
PCIE15_TXP/SATA2_TXP
PCIE16_RXN/SATA3_RXN
PCIE16_RXP/SATA3_RXP
PCIE16_TXN/SATA3_TXN
PCIE16_TXP/SATA3_TXP
PCIE17_RXN/SATA4_RXN
PCIE17_RXP/SATA4_RXP
PCIE17_TXN/SATA4_TXN
PCIE17_TXP/SATA4_TXP
PCIE18_RXN/SATA5_RXN
PCIE18_RXP/SATA5_RXP
PCIE18_TXN/SATA5_TXN
PCIE18_TXP/SATA5_TXP
GPP_E8/SATA_LED#
GPP_E0/SATAXPCIE0/SATAGP0
GPP_E1/SATAXPCIE1/SATAGP1
GPP_E2/SATAXPCIE2/SATAGP2
GPP_F0/SATAXPCIE3/SATAGP_3
GPP_F1/SATAXPCIE4/SATAGP4
GPP_F2/SATAXPCIE5/SATAGP5
GPP_F3/SATAXPCIE6/SATAGP6
GPP_F4/SATAXPCIE7/SATAGP7
GPP_F21/EDP_BKLTCTL
GPP_F20/EDP_BKLTEN
GPP_F19/EDP_VDDEN
3 OF 13
SATAGP0
0
1
HDD_DET#
1
0
SATAGP3
1 1=SATA 0=PCIESPSGP4 m3 042_PCIE# _SATA
0
PCIE9_RXN
PCIE9_RXP
PCIE9_TXN
PCIE9_TXP
PCIE10_RXN
PCIE10_RXP
PCIE10_TXN
PCIE10_TXP
THRMTRIP#
PECI
PM_SYNC
PLTRST_CPU#
PM_DOWN
G36
F36
C34
D34
K37
J37
C35
B35
SATA_PRX_DTX_N2
F44
SATA_PRX_DTX_P2
E45
SATA_PTX_DRX_N2
B40
SATA_PTX_DRX_P2
C40
L41
M40
B41
C41
K43
K44
A42
B42
P41
R40
C42
D42
AK48
AH41
AJ43
AK47
AN47
AM46
AM43
AM47
AM48
BIA_PWM_PCH
AU48
PANEL_BKEN_PCH
AV46
ENVDD_PCH
AV44
AD3
AF2
H_PM_SYNC_R
AF3
AG5
AE2
Rev1.0
0=SATAm2280 _PCIE_SAT A# 1=PCI E
0=SATA 1=PCIE
1=SATA
PCIE_PRX_DTX_N9
PCIE_PRX_DTX_P9
PCIE_PTX_DRX_N9
PCIE_PTX_DRX_P9
PCIE_PRX_DTX_N10
PCIE_PRX_DTX_P10
PCIE_PTX_DRX_N10
PCIE_PTX_DRX_P10
PCIE_PRX_DTX_N17
PCIE_PRX_DTX_P17
PCIE_PTX_DRX_N17
PCIE_PTX_DRX_P17
PCIE_PRX_DTX_N18
PCIE_PRX_DTX_P18
PCIE_PTX_DRX_N18
PCIE_PTX_DRX_P18
SATAGP0
M2280_PCIE_SATA#
HDD_DET#
SATAGP3
m3042_PCIE#_SATA
SATAGP5
SATAGP6
PCH_THERMTRIP#
PCH_PECI
PLTRST_CPU#
H_PM_DOWN
0=PCIE1=SATA
PCIE_PRX_DTX_N9 <68>
PCIE_PRX_DTX_P9 <68>
PCIE_PTX_DRX_N9 <68>
PCIE_PTX_DRX_P9 <68>
PCIE_PRX_DTX_N10 <68>
PCIE_PRX_DTX_P10 <68>
PCIE_PTX_DRX_N10 <68>
PCIE_PTX_DRX_P10 <68>
SATA_PRX_DTX_N2 <67>
SATA_PRX_DTX_P2 <67>
SATA_PTX_DRX_N2 <67>
SATA_PTX_DRX_P2 <67>
PCIE_PRX_DTX_N17 <52>
PCIE_PRX_DTX_P17 <52>
PCIE_PTX_DRX_N17 <52>
PCIE_PTX_DRX_P17 <52>
PCIE_PRX_DTX_N18 <52>
PCIE_PRX_DTX_P18 <52>
PCIE_PTX_DRX_N18 <52>
PCIE_PTX_DRX_P18 <52>
M2280_PCIE_SATA# <68>
HDD_DET# <67>
m3042_PCIE#_SATA <58>
Reser ve
PCH_TBT_PERST# <42>
BIA_PWM_PCH <38>
PANEL_BKEN_PCH <38>
ENVDD_PCH <38>
1 2
RH75 620_0402_5%
1 2
RH73 13_0402_5%
1 2
RH156 30_0402_5%
PLTRST_CPU# <7>
H_PM_DOWN <7>
PLTRST_CPU#
ESD request 7/25
Close UC1.AG5
H_PM_SYNC
0.1U_0201_10V6K
1
2
M.2 Socket 3 (Key M)
SATA HDD
M.2 3042 HCA or QCA LTE SSD Cache
M.2 3042 HCA or QCA LTE SSD Cache
PCH_PECI
H_THERMTRIP# <7,23,24,59>
H_PECI <7,58>
H_PM_SYNC <7>
12
RH74
@
10K_0402_5%
H_PECI
@ESD@
CH550
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2018/01/01
2018/01/01
2018/01/01
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2020/01/01
2020/01/01
2020/01/01
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
CannonLake PCH-H (1/9)
CannonLake PCH-H (1/9)
CannonLake PCH-H (1/9)
Size
Size
Size
Document Number Re v
Document Number Re v
Document Number Re v
C
C
C
LA-H171P
LA-H171P
LA-H171P
Friday, March 08, 2019
Friday, March 08, 2019
Friday, March 08, 2019
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
14 100
14 100
14 100
0.1
0.1
0.1
5
smd.db-x7.ru
D D
4
RH66@ 0_0402_5%
XDP_DBRESET#<7>
RH70 8.2K_0402_5%@
ME_RESET#
12
CIS LINK OK
1 2
+3.3V_RUN
5
1
B
2
A
3
3
CH10
@
1 2
0.1U_0402_25V6
P
4
Y
G
UC3
@
74AHC1G09GW_TSSOP5
SYS_RESET#
SYS_RESET# <18,19>
2
1
DMI_CTX_PRX_N0<6>
DMI_CTX_PRX_P0<6>
DMI_CRX_PTX_N0<6>
DMI_CRX_PTX_P0<6>
DMI_CTX_PRX_N1<6>
DMI_CTX_PRX_P1<6>
DMI_CRX_PTX_N1<6>
DMI_CRX_PTX_P1<6>
DMI_CTX_PRX_N2<6>
DMI_CTX_PRX_P2<6>
C C
support AR
B B
AR
LAN --->
Card Reader --->
WLAN --->
DMI_CRX_PTX_N2<6>
DMI_CRX_PTX_P2<6>
DMI_CTX_PRX_N3<6>
DMI_CTX_PRX_P3<6>
DMI_CRX_PTX_N3<6>
DMI_CRX_PTX_P3<6>
PCIE_PRX_TTX_N1<42>
PCIE_PRX_TTX_P1<42>
PCIE_PTX_TRX_N1<42>
PCIE_PTX_TRX_P1<42>
PCIE_PRX_TTX_N2<42>
PCIE_PRX_TTX_P2<42>
PCIE_PTX_TRX_N2<42>
PCIE_PTX_TRX_P2<42>
PCIE_PRX_TTX_N3<42>
PCIE_PRX_TTX_P3<42>
PCIE_PTX_TRX_N3<42>
PCIE_PTX_TRX_P3<42>
PCIE_PRX_TTX_N4<42>
PCIE_PRX_TTX_P4<42>
PCIE_PTX_TRX_N4<42>
PCIE_PTX_TRX_P4<42>
PCIE_PRX_DTX_N5<51>
PCIE_PRX_DTX_P5<51>
PCIE_PTX_DRX_N5<51>
PCIE_PTX_DRX_P5<51>
PCIE_PRX_DTX_N6<70>
PCIE_PRX_DTX_P6<70>
PCIE_PTX_DRX_N6<70>
PCIE_PTX_DRX_P6<70>
PCIE_PTX_DRX_P7<52>
PCIE_PTX_DRX_N7<52>
PCIE_PRX_DTX_P7<52>
PCIE_PRX_DTX_N7<52>
DMI_CTX_PRX_N0
DMI_CTX_PRX_P0
DMI_CRX_PTX_N0
DMI_CRX_PTX_P0
DMI_CTX_PRX_N1
DMI_CTX_PRX_P1
DMI_CRX_PTX_N1
DMI_CRX_PTX_P1
DMI_CTX_PRX_N2
DMI_CTX_PRX_P2
DMI_CRX_PTX_N2
DMI_CRX_PTX_P2
DMI_CTX_PRX_N3
DMI_CTX_PRX_P3
DMI_CRX_PTX_N3
DMI_CRX_PTX_P3
PCIE_PRX_TTX_N1
PCIE_PRX_TTX_P1
PCIE_PTX_TRX_N1
PCIE_PTX_TRX_P1
PCIE_PRX_TTX_N2
PCIE_PRX_TTX_P2
PCIE_PTX_TRX_N2
PCIE_PTX_TRX_P2
PCIE_PRX_TTX_N3
PCIE_PRX_TTX_P3
PCIE_PTX_TRX_N3
PCIE_PTX_TRX_P3
PCIE_PRX_TTX_N4
PCIE_PRX_TTX_P4
PCIE_PTX_TRX_N4
PCIE_PTX_TRX_P4
PCIE_PRX_DTX_N5
PCIE_PRX_DTX_P5
PCIE_PTX_DRX_N5
PCIE_PTX_DRX_P5
PCIE_PRX_DTX_N6
PCIE_PRX_DTX_P6
PCIE_PTX_DRX_N6
PCIE_PTX_DRX_P6
PCIE_PTX_DRX_P7
PCIE_PTX_DRX_N7
PCIE_PRX_DTX_P7
PCIE_PRX_DTX_N7
UH1B
K34
DMI0_RXN
J35
DMI0_RXP
C33
DMI0_TXN
B33
DMI0_TXP
G33
DMI1_RXN
F34
DMI1_RXP
C32
DMI1_TXN
B32
DMI1_TXP
K32
DMI2_RXN
J32
DMI2_RXP
C31
DMI2_TXN
B31
DMI2_TXP
G30
DMI3_RXN
F30
DMI3_RXP
C29
DMI3_TXN
B29
DMI3_TXP
A25
DMI7_TXP
B25
DMI7_TXN
P24
DMI7_RXP
R24
DMI7_RXN
C26
DMI6_TXP
B26
DMI6_TXN
F26
DMI6_RXP
G26
DMI6_RXN
B27
DMI5_TXP
C27
DMI5_TXN
L26
DMI5_RXP
M26
DMI5_RXN
D29
DMI4_TXP
E28
DMI4_TXN
K29
DMI4_RXP
M29
DMI4_RXN
G17
PCIE1_RXN/USB31_7_RXN
F16
PCIE1_RXP/USB31_7_RXP
A17
PCIE1_TXN/USB31_7_TXN
B17
PCIE1_TXP/USB31_7_TXP
R21
PCIE2_RXN/USB31_8_RXN
P21
PCIE2_RXP/USB31_8_RXP
B18
PCIE2_TXN/USB31_8_TXN
C18
PCIE2_TXP/USB31_8_TXP
K18
PCIE3_RXN/USB31_9_RXN
J18
PCIE3_RXP/USB31_9_RXP
B19
PCIE3_TXN/USB31_9_TXN
C19
PCIE3_TXP/USB31_9_TXP
N18
PCIE4_RXN/USB31_10_RXN
R18
PCIE4_RXP/USB31_10_RXP
D20
PCIE4_TXN/USB31_10_TXN
C20
PCIE4_TXP/USB31_10_TXP
F20
PCIE5_RXN
G20
PCIE5_RXP
B21
PCIE5_TXN
A22
PCIE5_TXP
K21
PCIE6_RXN
J21
PCIE6_RXP
D21
PCIE6_TXN
C21
PCIE6_TXP
B23
PCIE7_TXP
C23
PCIE7_TXN
J24
PCIE7_RXP
L24
PCIE7_RXN
F24
PCIE8_RXN
G24
PCIE8_RXP
B24
PCIE8_TXN
C24
PCIE8_TXP
CNP-H_BGA874
CNP-H
GPP_E9/USB2_OC0#
GPP_E10/USB2_OC1#
GPP_E11/USB2_OC2#
GPP_E12/USB2_OC3#
GPP_F15/USB2_OC4#
GPP_F16/USB2_OC5#
GPP_F17/USB2_OC6#
GPP_F18/USB2_OC7#
USB2_VBUSSENSE
2 OF 13
USB2N_1
USB2P_1
USB2N_2
USB2P_2
USB2N_3
USB2P_3
USB2N_4
USB2P_4
USB2N_5
USB2P_5
USB2N_6
USB2P_6
USB2N_7
USB2P_7
USB2N_8
USB2P_8
USB2N_9
USB2P_9
USB2N_10
USB2P_10
USB2N_11
USB2P_11
USB2N_12
USB2P_12
USB2N_13
USB2P_13
USB2N_14
USB2P_14
USB2_COMP
RSVD1
USB2_ID
PCIE24_TXP
PCIE24_TXN
PCIE24_RXP
PCIE24_RXN
PCIE23_TXP
PCIE23_TXN
PCIE23_RXP
PCIE23_RXN
PCIE22_TXP
PCIE22_TXN
PCIE22_RXP
PCIE22_RXN
PCIE21_TXP
PCIE21_TXN
PCIE21_RXP
PCIE21_RXN
GPD7
USB20_N1
J3
USB20_P1
J2
USB20_N2
N13
USB20_P2
N15
USB20_N3
K4
USB20_P3
K3
USB20_N4
M10
USB20_P4
L9
USB20_N5
M1
USB20_P5
L2
USB20_N6
K7
USB20_P6
K6
L4
L3
USB20_N8
G4
USB20_P8
G5
M6
N8
USB20_N10
H3
USB20_P10
H2
USB20_N11
R10
USB20_P11
P9
G1
G2
N3
N2
USB20_N14
E5
USB20_P14
F6
USB_OC0#
AH36
USB_OC1#
AL40
USB_OC2#
AJ44
USB_OC3#
AL41
USB_OC4#
AV47
USB_OC5#
AR35
USB_OC6#
AR37
USB_OC7#
AV43
USB2_COMP
F4
USB2_VBUSSENSE
F3
U13
USB2_ID
G3
BE41
TBT_RTD3_WAKE#_GPD7
G45
G46
Y41
Y40
G48
G49
W44
W43
H48
H47
U41
U40
F46
G47
R44
T43
Rev1.0
USB20_N1 <71>
-----> Ext USB Port 1 Charge(RIGHT)
USB20_P1 <71>
USB20_N2 <72>
-----> Ext USB Port 2(LEFT)
USB20_P2 <72>
USB20_N3 <72>
-----> Ext USB Port 3(RIGHT)
USB20_P3 <72>
USB20_N4 <65>
-----> FPR in PB(RESERVE FOR MOC)
USB20_P4 <65>
USB20_N5 <44>
-----> reserve for TI_PD
USB20_P5 <44>
1
T300 PAD~D@
1
TS remove USB2.0 INTERFACE
1
T40 PAD~D@
-----> M.2 2230 (BT)
T301 PAD~D@
USB20_N8 <52>
-----> M.2 3042 (WWAN)
USB20_P8 <52>
USB20_N10 <66>
-----> USH
USB20_P10 <66>
USB20_N11 <38>
-----> Camera
USB20_P11 <38>
USB20_N14 <52>
USB20_P14 <52>
----->used for CNVio wireless M.2
USB_OC0# <71>
USB_OC1# <72>
USB_OC2# <72>
Reser ve
Reser ve
Reser ve
Reser ve
Reser ve
1 2
RH193 113_0402_1%
1 2
RH364 1K_0402_5%
1 2
RH365 0_0402_5%@
1 2
RH662 0_0402_5%@
TBT_RTD3_WAKE# <18,42>
USB_OC1#
USB_OC2#
USB_OC3#
USB_OC0#
USB_OC4#
USB_OC5#
USB_OC6#
USB_OC7#
TBT_RTD3_WAKE#_GPD7
CFL CRB rev0.5
Xtal input
High : differential
Low : single-end
CNL- PCH EDS rev0.5
External pull-up is required. Recommend 100K if pulled
up to 3.3V
USB_OC3#
USB_OC1#
USB_OC0#
USB_OC2#
1 2
1 2
RH641 10K_0201_5%
1 2
RH642 10K_0201_5%
1 2
RH643 10K_0201_5%
RH644 10K_0201_5%
1 2
1 2
RH645 10K_0201_5%
1 2
RH646 10K_0201_5%
1 2
RH647 10K_0201_5%
RH648 10K_0201_5%
RP change to single Resister
1 2
RH602
Xtal input
1 2
1 2
1 2
1 2
differential
single-end
HIGH(DEFAULT)
LOW
RH649 15K_0201_5%@
RH650 15K_0201_5%@
RH651 15K_0201_5%@
RH652 15K_0201_5%@
RP change to single Resister
100K_0402_5%
+3.3V_ALW_PCH
+3.3V_DSW
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2018/01/01
2018/01/01
2018/01/01
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2020/01/01
2020/01/01
2020/01/01
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
CannonLake PCH-H (2/9)
CannonLake PCH-H (2/9)
CannonLake PCH-H (2/9)
Size
Size
Size
Document Number Re v
Document Number Re v
Document Number Re v
C
C
C
LA-H171P
LA-H171P
LA-H171P
Monday, March 11, 2019
Monday, March 11, 2019
Monday, March 11, 2019
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
15 100
15 100
15 100
0.1
0.1
0.1
5
smd.db-x7.ru
D D
4
3
2
1
1 2
1 2
CNP-H
CLKOUT_ITPXDP#
CLKOUT_ITPXDP_P
CLKOUT_CPUPCIBCLK#
CLKOUT_CPUPCIBCLK_P
CLKOUT_PCIE_N0
CLKOUT_PCIE_P0
CLKOUT_PCIE_N1
CLKOUT_PCIE_P1
CLKOUT_PCIE_N2
CLKOUT_PCIE_P2
CLKOUT_PCIE_N3
CLKOUT_PCIE_P3
CLKOUT_PCIE_N4
CLKOUT_PCIE_P4
CLKOUT_PCIE_N5
CLKOUT_PCIE_P5
CLKOUT_PCIE_N6
CLKOUT_PCIE_P6
CLKOUT_PCIE_N7
CLKOUT_PCIE_P7
CLKOUT_PCIE_N8
CLKOUT_PCIE_P8
CLKOUT_PCIE_N9
CLKOUT_PCIE_P9
CLKOUT_PCIE_N10
CLKOUT_PCIE_P10
CLKOUT_PCIE_N11
CLKOUT_PCIE_P11
7 OF 13
CLKIN_XTAL
Y3
Y4
B6
A6
AJ6
AJ7
AH9
AH10
AE14
AE15
AE6
AE7
AC2
AC3
AB2
AB3
W4
W3
W7
W6
AC14
AC15
U2
U3
AC9
AC11
AE9
AE11
R6
Rev1.0
ESD request 7/25
Close UH1.R6
XTAL24_IN
12
RH153
1M_0402_1%
XTAL24_OUT
PCH_XDP_CLK_DN_R
PCH_XDP_CLK_DP_R
PCH_CPU_PCIBCLK_D#
PCH_CPU_PCIBCLK_D
CLK_PCIE_N0
CLK_PCIE_P0
CLK_PCIE_N1
CLK_PCIE_P1
CLK_PCIE_N3
CLK_PCIE_P3
CLK_PCIE_N4
CLK_PCIE_P4
CLK_PCIE_N5
CLK_PCIE_P5
CLK_PCIE_N6
CLK_PCIE_P6
REFCLK_CNV
4.7U_0201_6.3V6M
@ESD@
12
1
CH554
2
XDP@
RH154 0_0201_5%
RH155 0_0201_5%XDP@
RH168@ 0_0402_5%
RH167@ 0_0402_5%
CLK_PCIE_N0 <52>
CLK_PCIE_P0 <52>
CLK_PCIE_N1 <52>
CLK_PCIE_P1 <52>
CLK_PCIE_N3 <68>
CLK_PCIE_P3 <68>
CLK_PCIE_N4 <51>
CLK_PCIE_P4 <51>
CLK_PCIE_N5 <70>
CLK_PCIE_P5 <70>
CLK_PCIE_N6 <42>
CLK_PCIE_P6 <42>
REFCLK_CNV <52>
RH110
10K_0201_5%
YH2
24MHZ_12PF_8Y24000034
123
1 2
1 2
1 2
1 2
4
PCH_XDP_CLK_DN
PCH_XDP_CLK_DP
PCH_CPU_PCIBCLK_R_D#
PCH_CPU_PCIBCLK_R_D
WWAN
WLAN
M.2 Socket 3 (Key M)
LAN
MMI
TBT
PCH_XDP_CLK_DN <7>
PCH_XDP_CLK_DP <7>
PCH_CPU_PCIBCLK_R_D# <7>
PCH_CPU_PCIBCLK_R_D <7>
UH1G
BE33
CPU_24MHZ_R_D<7>
CPU_24MHZ_R_D#<7>
PCH_CPU_BCLK_R_D<7>
PCH_CPU_BCLK_R_D#<7>
C C
WWAN
WLAN
M.2 Socket 3
LAN
MMI
TBT
B B
CLKREQ_PCIE#0<52>
CLKREQ_PCIE#1<52>
CLKREQ_PCIE#3<68>
CLKREQ_PCIE#4<51>
CLKREQ_PCIE#5<70>
CLKREQ_PCIE#6<42>
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
CH4
1 2
15P_0402_50V8J
CH5
1 2
15P_0402_50V8J
CPU_24MHZ_R_D PCH_CPU_NSSC_CLK_D
CPU_24MHZ_R_D#
PCH_CPU_BCLK_R_D
PCH_CPU_BCLK_R_D#
RH123 10K_0201_5%
RH10 0_0201_5%@RF@
RH124 10K_0201_5%
RH11 0_0201_5%@RF@
RH125 10K_0201_5%
RH126 10K_0201_5%
RH13 0_0201_5%@RF@
RH127 10K_0201_5%
RH14 0_0201_5%@RF@
RH131 10K_0201_5%
RH15 0_0201_5%@RF@
RH132 10K_0201_5%
RH16 0_0201_5%@RF@
RH133 10K_0201_5%
PCH_RTCX1_R
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
1 2
RH43@ 0_0402_5%
YH1
32.768KHZ_12.5PF_9H03200042
1 2
RH169@ 0_0402_5%
1 2
RH170@ 0_0402_5%
1 2
RH161@ 0_0402_5%
1 2
RH166@ 0_0402_5%
RH435
1 2
60.4_0402_1%
follow intel CFL-H PDG rev0.5, but CRB rev0.5 - CSLP1
follow intel CRB design - CSLP2, EVT
PCH_RTCX1
12
RH44
10M_0402_5%
PCH_RTCX2
PCH_CPU_NSSC_CLK_D#
PCH_CPU_BCLK_D
PCH_CPU_BCLK_D#
XTAL24_OUT_R1
XTAL24_IN_R1
XCLK_RBIAS
PCH_RTCX1
PCH_RTCX2
CLKREQ_PCIE#0_R
CLKREQ_PCIE#1_R
CLKREQ_PCIE#2_R
CLKREQ_PCIE#3_R
CLKREQ_PCIE#4_R
CLKREQ_PCIE#5_R
CLKREQ_PCIE#6_R
CLKREQ_PCIE#7_R
D7
C6
B8
C8
U9
U10
T3
BA49
BA48
BF31
BE31
AR32
BB30
BA30
AN29
AE47
AC48
AE41
AF48
AC41
AC39
AE39
AB48
AC44
AC43
V2
V3
T2
T1
AA1
Y2
AC7
AC6
XTAL24_IN_R1
XTAL24_OUT_R1
GPP_A16/CLKOUT_48
CLKOUT_CPUNSSC_P
CLKOUT_CPUNSSC#
CLKOUT_CPUBCLK_P
CLKOUT_CPUBCLK#
XTAL_OUT
XTAL_IN
XCLK_BIASREF
RTCX1
RTCX2
GPP_B5/SRCCLKREQ0#
GPP_B6/SRCCLKREQ1#
GPP_B7/SRCCLKREQ2#
GPP_B8/SRCCLKREQ3#
GPP_B9/SRCCLKREQ4#
GPP_B10/SRCCLKREQ5#
GPP_H0/SRCCLKREQ6#
GPP_H1/SRCCLKREQ7#
GPP_H2/SRCCLKREQ8#
GPP_H3/SRCCLKREQ9#
GPP_H4/SRCCLKREQ10#
GPP_H5/SRCCLKREQ11#
GPP_H6/SRCCLKREQ12#
GPP_H7/SRCCLKREQ13#
GPP_H8/SRCCLKREQ14#
GPP_H9/SRCCLKREQ15#
CLKOUT_PCIE_N15
CLKOUT_PCIE_P15
CLKOUT_PCIE_N14
CLKOUT_PCIE_P14
CLKOUT_PCIE_N13
CLKOUT_PCIE_P13
CLKOUT_PCIE_N12
CLKOUT_PCIE_P12
CNP-H_BGA874
RH436 0_0201_5%EMI@
RH152 0_0201_5%EMI@
1
A A
5
4
3
CH14
15P_0402_50V8J
2
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2018/01/01
2018/01/01
2018/01/01
Compal Secret Data
Compal Secret Data
Compal Secret Data
1
CH13
15P_0402_50V8J
2
Deciphered Date
Deciphered Date
Deciphered Date
2
2020/01/01
2020/01/01
2020/01/01
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
CannonLake PCH-H (3/9)
CannonLake PCH-H (3/9)
CannonLake PCH-H (3/9)
Size
Size
Size
Document Number Re v
Document Number Re v
Document Number Re v
B
B
B
LA-H171P
LA-H171P
LA-H171P
Tuesday, March 12, 2019
Tuesday, March 12, 2019
Tuesday, March 12, 2019
Date: Sheet o f
Date: Sheet o f
Date: Sheet o f
1
16 100
16 100
16 100
0.1
0.1
0.1
5
smd.db-x7.ru
+3.3V_ALW_PCH
1 2
RH310 10K_0402_5%
1 2
RC559 10K_0402_5%@
1 2
RC834 100K_0402_5%
D D
+3.3V_RUN
+3.3V_SPI
C C
9/5 MOW
Opt i on 1: I mpl e me nt a 1 k Oh m pull - do wn r esi stor on t he si gnal and de- popul ate t he
required 1 kOhm pull-up resistor. In this case, customers must ensure that the SPI
f l ash devi ce on t he pl at f o rm has HOLD f unct i onal it y di sabl ed by default.
Note that the pull down resistor on SPI0_IO3 is only needed for SKL U/Y plat f or ms
with ES and SKL S/H plat f or ms wi t h pre- ES1/ES1 s a mpl es.
B B
eSPI Flash sharing mode (GPP_H12)
0 = Master Attached Flash Sharing (MAFS) enabled (Default)
1 = Slave Attached Flash Sharing (SAFS) enabled.
1 2
RC840 10K_0402_5%
1 2
RC866 10K_0402_5%
TOUCH_SCREEN_PD# don't move to RPC,
1 2
RH348 10K_0201_5%@
1 2
RH402 10K_0402_5%
RC756 10K_0201_5%@
GPP_H12
1 2
2.2K_0402_5%@
RH615
GPP_H15
1 2
100K_0402_5%
RH601
RH600
RH30 20K_0402_5%
RH335 20K_0402_5%
RH334 1K_0402_5%@
1 2
1 2
1 2
1 2
PCH_SPI_D0
100K_0402_5%
PCH_SPI_D2
PCH_SPI_D3
PCH_SPI_D3
SIO_EXT_SMI#
RTD3_CIO_PWR_EN
WWAN_GPIO_WAKE#
TOUCH_SCREEN_PD#
TOUCHPAD_INTR#
WWAN_GPIO_PERST#
12
3.3V_CAM_EN#
RTC_DET#
PCH_SPI_D2_XDP<7>
CFL-H PDG rev0.7
pop 20K for SPI0_IO2/3
CNL- PCH EDS rev0.5
Reserved External pull-up is required. Recommend 100K if pulled
up to 3.3V
ESPI
VPRO NVRRO
RH178,RH 179,RH18 1,
RH183,RH 184
A A
10 ohm5 ohm
PCH_SPI_CLK_0_RPCH_SPI_CLK_1_R
33_0402_5%
@EMI@
12
RH28
33P_0402_50V8J
@EMI@
12
CH321
33_0402_5%
@EMI@
12
RH29
33P_0402_50V8J
@EMI@
12
CH322
PCH_PLTRST#
RH180 0_0402_5%XDP@
PCH_SPI_CS#0_R1
PCH_SPI_CS#1_R1
PCH_SPI_D2_R1
4
+3.3V_ALW_PCH
5
1
B
2
A
MC74VHC1G08DFT2G_SC70-5
3
WWAN_BB_RST#<52>
T60PAD~D @
T61PAD~D @
T63PAD~D @
T62PAD~D @
PCH_SPI_D0<7>
1 2
PCH_SPI_CS#2<66>
WWAN_FULL_PWR_EN<52>
RTC_DET#<83>
3.3V_CAM_EN#<38>
WWAN_GPIO_PERST#<52>
WWAN_GPIO_WAKE#<52>
1 2
RH37@ 0_0402_5%
1 2
RH351 33_0402_5%
NVPRO@
1 2
RH352 0_0402_5%
NVPRO@
1 2
RH353 33_0402_5%
UH7
P
4
Y
G
1
1
1
1
WWAN_GPIO_PERST#
WWAN_GPIO_WAKE#
PCH_PLTRST#_AND
12
RH65
@
100K_0201_5%
WWAN_BB_RST#
PCH_SPI_D0
PCH_SPI_D1
PCH_SPI_CS#0
PCH_SPI_CLK
PCH_SPI_CS#1
PCH_SPI_D2PCH_SPI_D2_XDP
PCH_SPI_D3
RTC_DET#
BE36
R15
R13
AL37
AN35
AU41
BA45
AY47
AW47
AW48
AY48
BA46
AT40
BE19
BF19
BF18
BE18
BC17
BD17
For vPro
32MB WSON8 Flash ROM
For Non-vPro
8MB WSON8 Flash ROM
PCH_SPI_CS#0_R2
PCH_SPI_D1_0_R PCH_SPI_D3_0_R
PCH_SPI_D2_0_R
PCH_SPI_CS#1_R3
PCH_SPI_D1_1_R PCH_SPI_D3_1_R
PCH_SPI_D2_1_R
RH187@ 0_0402_5%
UH1A
GPP_A11/PME#/SD_VDD2_PWR_EN#
RSVD2
RSVD1
VSS
TP
SPI0_MOSI
SPI0_MISO
SPI0_CS0#
SPI0_CLK
SPI0_CS1#
SPI0_IO2
SPI0_IO3
SPI0_CS2#
GPP_D1/SPI1_CLK/SBK1_BK1
GPP_D0/SPI1_CS#/SBK0_BK0
GPP_D3/SPI1_MOSI/SBK3_BK3
GPP_D2/SPI1_MISO/SBK2_BK2
GPP_D22/SPI1_IO3
GPP_D21/SPI1_IO2
CNP-H_BGA874
VPRO@
UC5
1
CS#
2
HOLD#_RESET#
DO
3
WP#
4
GND1
9
GND2
W25Q256JVEIQ_WSON8_8X6
For Non-vPro
16MB SOP8 Flash ROM
NVPRO@
UC6
1
VCC
CS#
2
DO(IO1)
3
CLK
IO2
4
DI(IO0)
GND
W25Q128JVSIQ_SO8
IO
3
CNP-H
1 OF 13
VCC
CLK
DI
8
7
6
5
12
GPP_B13/PLTRST#
GPP_K16/GSXCLK
GPP_K12/GSXDOUT
GPP_K13/GSXSLOAD
GPP_K14/GSXDIN
GPP_K15/GSXSRESET#
GPP_E3/CPU_GP0
GPP_E7/CPU_GP1
GPP_B3/CPU_GP2
GPP_B4/CPU_GP3
GPP_H18/SML4ALERT#
GPP_H17/SML4DATA
GPP_H16/SML4CLK
GPP_H15/SML3ALERT#
GPP_H14/SML3DATA
GPP_H13/SML3CLK
GPP_H12/SML2ALERT#
GPP_H11/SML2DATA
GPP_H10/SML2CLK
INTRUDER#
+3.3V_SPI
0.1U_0201_10V6K
8
7
PCH_SPI_CLK_0_RPCH_SPI_D2_R1
6
PCH_SPI_D0_0_R
5
+3.3V_SPI
NVPRO@
CH270
1 2
0.1U_0201_10V6K
PCH_SPI_CLK_1_R
PCH_SPI_D0_1_R
PCH_PLTRST#_AND <38,42,52,68,70>
PLTRST_TPM# <66>
PCH_PLTRST#
AV29
Y47
Y46
Y48
W46
AA45
SIO_EXT_SMI#
AL47
TOUCH_SCREEN_PD#
AM45
TOUCHPAD_INTR#
BF32
BC33
AE44
AJ46
AE43
GPP_H15
AC47
AD48
AF47
GPP_H12
AB47
AD47
AE48
PCH_INTRUDER_HDR#
BB44
Rev1.0
PCH_SPI_D1_R1
PCH_SPI_D0_R1
PCH_SPI_CLK_R1
PCH_SPI_D3_R1
PCH_SPI_D1_R1 PCH_SPI_D1_1_R
PCH_SPI_D0_R1
PCH_SPI_CLK_R1
PCH_SPI_D3_R1
CH9
1 2
PCH_SPI_D1_R1<66>
PCH_SPI_D0_R1<66>
PCH_SPI_CLK_R1<66>
2
RH62@ 0_0402_5%
TOUCHPAD_INTR# <58,63>
TOUCH_SCREEN_DET# <38>
RTD3_CIO_PWR_EN <42>
1 2
RH653 33_0402_5%
1 2
RH654 33_0402_5%
1 2
RH655 33_0402_5%
1 2
RH656 33_0402_5%
RP change to single Resister
1 2
RH657 33_0402_5%NVPRO@
1 2
RH658 33_0402_5%NVPRO@
1 2
RH659 33_0402_5%NVPRO@
1 2
RH660 33_0402_5%NVPRO@
RP change to single Resister
+3.3V_SPI
1
TOUCH_SCREEN_PD#
TOUCH_SCREEN_PD# don't move to RPC,
TOUCH_SCREEN_PD
TOUCH_SCREEN_PD#
L2N7002DW1T1G_SC88-6
RH566 0_0402_5%@
2
QH8A
@
+3.3V_RUN
1 2
12
@
RH104
10K_0402_5%
6
1
TOUCH_SCREEN_PD#_R
TOUCH_SCREEN_PD#_R <38>
34
QH8B
@
L2N7002DW1T1G_SC88-6
5
Reserve for Panel side TS PH voltage problem
12
VPRO PDG P.357 R2 5 ohm
NVPRO PDG P.359 R2 10 ohm
+3.3V_ALW_PCH
PLTRST_LAN# <51>
+RTC_CELL_PCH
12
RH198
1M_0402_5%
PCH_SPI_D1_0_R
PCH_SPI_D0_0_R
PCH_SPI_CLK_0_R
PCH_SPI_D3_0_R
PCH_SPI_D0_1_R
PCH_SPI_CLK_1_R
PCH_SPI_D3_1_R
RH178,RH179,RH181,RH 183,RH184
NVPRO BOM OPTION IN PAGE 61
DH3 RB751S40T1G_SOD523-2
RH185 0_0402_5%@
12
RH1770_0402_5% NVPRO@
12
RH1784.99_0402_1% VPRO@
12
RH1794.99_0402_1% VPRO@
12
RH1814.99_0402_1% VPRO@
12
RH1820_0402_5%
12
RH1834.99_0402_1% VPRO@
12
RH1844.99_0402_1% VPRO@
PROM_BIOS_R<63>
21
12
PCH_PLTRST#
PCH_SPI_CS#1_R1
PCH_SPI_D0_R1
PCH_SPI_D1_R1
PCH_SPI_CLK_R1
PCH_SPI_CS#0_R1
PCH_SPI_D2_R1
PCH_SPI_D3_R1
1 2
CH552 0.1U_0201_10V6K@ESD@
ESD request 7/25 Close UH1.AE3
PCH Signal Glitch Free Implementation Requirements
PCH_PLTRST#
PCH_SPI_CLK
PCH_SPI_CS#1
PCH_SPI_D0
PCH_SPI_D1
PCH_SPI_CLK
PCH_SPI_CS#0
PCH_SPI_D2
PCH_SPI_D3
1 2
RH635 100K_0201_5%@
1 2
RH634 100K_0201_5%@
JSPI1 follow KKW,for H limit
ACES_50696-0200M-P01
22
GND_2
21
GND_1
20
20
19
19
18
18
17
17
16
16
15
15
14
14
13
13
12
12
11
11
10
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
JSPI1
CONN@
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2018/01/01
2018/01/01
2018/01/01
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2020/01/01
2020/01/01
2020/01/01
2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
CannonLake PCH-H (4/9)
CannonLake PCH-H (4/9)
CannonLake PCH-H (4/9)
Size
Size
Size
Document Number Re v
Document Number Re v
Document Number Re v
B
B
B
LA-H171P
LA-H171P
LA-H171P
Monday, March 11, 2019
Monday, March 11, 2019
Monday, March 11, 2019
Date: Sheet o f
Date: Sheet o f
Date: Sheet o f
1
17 100
17 100
17 100
0.1
0.1
0.1
+3.3V_ALW_PCH
smd.db-x7.ru
1 2
RH56 1K_0402_5%
1 2
RH57 1K_0402_5%
1 2
RH67 499_0402_1%
1 2
RH77 499_0402_1%
1 2
RH80 1K_0402_5%
1 2
RH81 1K_0402_5%
D D
C C
B B
1 2
RH661 10K_0402_5%
+3.3V_ALW_PCH
1 2
RH61 4.7K_0201_5%
TLS CONFIDENTIALITY
HIGH
LOW(DEFAULT)
+3.3V_ALW_PCH
1 2
RH78 4.7K_0201_5%ESPI@
EC interface
HIGH
LOW(DEFAULT)
+3.3V_ALW_PCH
1 2
RH86 4.7K_0201_5%@
TOP SWAP STRAP
HIGH
LOW(DEFAULT)
+3.3V_ALW_PCH
1 2
RC74 10K_0402_5%
1 2
RH868 75K_0402_5%
@
1 2
RH617 75K_0402_5%
1 2
RH618
If USB 3.0 Port 1 is used for 4-wire DCI.OOB (BSSB), and alternate functionality is also used on the pin,
pull up to V3.3S with >100K resistor to avoid noise.
If USB 3.0 Port 1 is used for DCI.OOB (BSSB) 4-wire BSSB, and NO alternate functionalityis used,
leave float.
If DCI.OOB (BSSB) 2+2 functionality is used, pull up to V3.3S with a 4.7K resistor.
1 2
CH41 1U_0201_6.3V6M
1 2
CH40 1U_0201_6.3V6M
PCH_RTCRST#<19,58>
1
1
CMOS1 SHORT PADS~D@
RH215
POP
NO Support Deep sleep
DE-POP
Support Deep sleep
PCH_DPWROK PCH_RSMRST#_AND
1
A A
2
1 2
RH215 0_0402_5%
@NDS3@
100K_0402_5%
0.01U_0402_25V7K~D
12
@
RH308
CH266
5
MEM_SMBCLK
MEM_SMBDATA
SML0_SMBCLK
SML0_SMBDATA
SML1_SMBCLK
SML1_SMBDATA
TBT_RTD3_WAKE#_K18
PCH_SMB_ALERT#
ENABLE
DISABLE
GPP_C5
ESPI
LPC
SPKR
ENABLE
DISABLE
KB_DET#
CNVI_EN#
CNV_RF_RST#
CLKREQ_CNV
71.5K_0402_1%
GPP_B23
WEAK INTERNAL PD ~20K
Intel DCI-OOB
HIGH
LOW(DEFAULT)
SRTCRST#
PCH_RTCRST#
2
2
12
5
Ext USB Port 1 Charge(RIGHT)
HDA_BIT_CLK_R<56>
HDA_SDIN0<56>
HDA_SDOUT_R<56>
HDA_SYNC_R<56>
HDA_RST#_R<56>
DVT2.0
'CNVI_EN#' reserve 75K PD
DVT1.0
'CLKREQ_CNV#' change to 71.5KPD from 75K
+3.3V_ALW_PCH
RH329
150K_0402_5%
1 2
ENABLED
DIABLED
+3.3V_ALW_PCH
0.1U_0201_10V6K
@ESD@
10K_0402_5%
RC75
1
CC556
2
ME_FWP PCH has internal 20K PD.
(suspend power rail)
ESD request 7/25
FLASH DESCRIPTOR SECURITY OVERRIDE
LOW = ENABLE (DEFAULT) -->Pin2 & Pin3 short
HIGH = DISABLE (ME can update) -->Pin1 & Pin2 short
AUD_AZACPU_SDO<9>
AUD_AZACPU_SDI_R<9>
AUD_AZACPU_SCLK<9>
HDA_SDIN0 HDA_SYNC HDA_BIT_CLK HDA_SDOUT
@RF@
2P_0402_50V8C
12
CA73
place close to UH1 place close to UH1 place close to UH1 place close to UH1
Service Mode Switch:
Add a switch to ME_FWP signa l to unlock the ME region and
allow the ent ir e regi on of t he SPI f la sh to be updat ed usi ng FPT.
12
RH101
@
1K_0402_5%
ME_FWP<58>
M.2 3042 (LTE)
Ext USB Port 2(LEFT)
Ext USB Port 3(RIGHT)
1 2
@RF@
CH268 47P_0402_50V8J
ME_FWP_PCH
AUD_AZACPU_SDO AUD_AZACPU_SDO_R
AUD_AZACPU_SDI_R
AUD_AZACPU_SCLK AUD_AZACPU_SCLK_R
@RF@
2P_0402_50V8C
12
CA74
ME_FWP
1 2
RH100 0_0402_5%@
PT,ST pop RH101 and SW1; MP pop RH100
ME_FWP_PCH
Link SSAJ120100 done 0724
4
remove non AR USB3
1 2
RH46 33_0402_5%EMI@
1 2
1 2
RH45 33_0402_5%
1 2
RH328 1K_0402_5%
1 2
RH48 33_0402_5%
RH50 33_0402_5%
1 2
RH39 30_0402_5%
1 2
RH38 30_0402_5%
IR_CAM_DET#<38>
+RTC_CELL_PCH
ME_FWP_PCH
SW1
@
1
A
2
B
3
C
4
G1
5
G2
SSAJ120100_3P
KB_DET#<63>
1 2
1 2
RH200 20K_0402_5%
RH201 20K_0402_5%
PCH_PWROK<88>
PCH_RSMRST#_AND<7,63>
@RF@
2P_0402_50V8C
12
CA75
4
3
USB3_PTX_DRX_N1<71>
USB3_PTX_DRX_P1<71>
USB3_PRX_DTX_N1<71>
USB3_PRX_DTX_P1<71>
USB3_PTX_DRX_N2<52>
USB3_PTX_DRX_P2<52>
USB3_PRX_DTX_N2<52>
USB3_PRX_DTX_P2<52>
USB3_PTX_DRX_P3<73>
USB3_PTX_DRX_N3<73>
USB3_PRX_DTX_P3<73>
USB3_PRX_DTX_N3<73>
USB3_PTX_DRX_P4<72>
USB3_PTX_DRX_N4<72>
USB3_PRX_DTX_P4<72>
USB3_PRX_DTX_N4<72>
1 2
RH637 100K_0201_5%@
1 2
RH636 100K_0201_5%@
CLKREQ_CNV<52>
CNV_RF_RST#<52>
CNVI_EN#<58>
@RF@
2P_0402_50V8C
12
CA76
PCH_DPWROK
PCH_SMB_ALERT#
MEM_SMBCLK
MEM_SMBDATA
SML0_SMBCLK
SML0_SMBDATA
SML1_SMBCLK
SML1_SMBDATA
PCH_DPWROK<58>
SML0_SMBCLK<51>
SML0_SMBDATA<51>
SML1_SMBCLK<58>
SML1_SMBDATA<58>
USB3_PTX_DRX_N1
USB3_PTX_DRX_P1
USB3_PRX_DTX_N1
USB3_PRX_DTX_P1
USB3_PTX_DRX_N2
USB3_PTX_DRX_P2
USB3_PRX_DTX_N2
USB3_PRX_DTX_P2
USB3_PTX_DRX_P3
USB3_PTX_DRX_N3
USB3_PRX_DTX_P3
USB3_PRX_DTX_N3
USB3_PTX_DRX_P4
USB3_PTX_DRX_N4
USB3_PRX_DTX_P4
USB3_PRX_DTX_N4
HDA_BIT_CLK
HDA_SDIN0
HDA_SDOUT
HDA_SYNC
HDA_RST#
CNVI_EN#
IR_CAM_DET#
KB_DET#
PCH_RTCRST#
SRTCRST#
PCH_PWROK
PCH_RSMRST#_AND
GPP_C5
GPP_B23
MEM_SMBCLK
MEM_SMBDATA
L2N7002DW1T1G_SC88-6
BD11
BE11
BF12
BG13
BE10
BF10
BE12
BD12
AM2
AN3
AM3
AV18
AW18
BA17
BE16
BF15
BD16
AV16
AW15
BE47
BD46
AY42
BA47
AW41
BE25
BE26
BF26
BF24
BF25
BE24
BD33
BF27
BE27
+3.3V_RUN
L2N7002DW1T1G_SC88-6
3 4
QH4B
UH1F
F9
USB31_1_TXN
F7
USB31_1_TXP
D11
USB31_1_RXN
C11
USB31_1_RXP
C3
USB31_2_TXN
D4
USB31_2_TXP
B9
USB31_2_RXN
C9
USB31_2_RXP
C17
USB31_6_TXN
C16
USB31_6_TXP
G14
USB31_6_RXN
F14
USB31_6_RXP
C15
USB31_5_TXN
B15
USB31_5_TXP
J13
USB31_5_RXN
K13
USB31_5_RXP
G12
USB31_3_TXP
F11
USB31_3_TXN
C10
USB31_3_RXP
B10
USB31_3_RXN
C14
USB31_4_TXP
B14
USB31_4_TXN
J15
USB31_4_RXP
K16
USB31_4_RXN
CNP-H_BGA874
UH1D
HDA_BCLK/I2S0_SCLK
HDA_SDI0/I2S0_RXD
HDA_SDO/I2S0_TXD
HDA_SYNC/I2S0_SFRM
HDA_RST#/I2S1_SCLK
HDA_SDI1/I2S1_RXD
I2S1_TXD/SNDW2_DATA
I2S1_SFRM/SNDW2_CLK
HDACPU_SDO
HDACPU_SDI
HDACPU_SCLK
GPP_D8/I2S2_SCLK
GPP_D7/I2S2_RXD
GPP_D6/I2S2_TXD/MODEM_CLKREQ
GPP_D5/I2S2_SFRM/CNV_RF_RESET#
GPP_D20/DMIC_DATA0/SNDW4_DATA
GPP_D19/DMIC_CLK0/SNDW4_CLK
GPP_D18/DMIC_DATA1/SNDW3_DATA
GPP_D17/DMIC_CLK1/SNDW3_CLK
RTCRST#
SRTCRST#
PCH_PWROK
RSMRST#
DSW_PWROK
GPP_C2/SMBALERT#
GPP_C0/SMBCLK
GPP_C1/SMBDATA
GPP_C5/SML0ALERT#
GPP_C3/SML0CLK
GPP_C4/SML0DATA
GPP_B23/SML1ALERT#/PCHHOT#
GPP_C6/SML1CLK
GPP_C7/SML1DATA
CNP-H_BGA874
VCCDSW_EN_GPIO<20>
VCCDSW_EN<58>
ALW_PWRGD_3V_5V<63,85>
For DS3:
Pop RE349, RE536, RH439, RH441, RH443
Depop DH1, RH215, RH440, RH442
For NDS3 :
Pop DH1, RH215, RH440, RH442
Depop RE349, RE536, RH439, RH441, RH443
2
6 1
QH4A
5
3
CNP-H
GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1
GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3
GPP_A5/LFRAME#/ESPI_CS0#
GPP_A6/SERIRQ/ESPI_CS1#
GPP_A7/PIRQA#/ESPI_ALERT0#
GPP_A0/RCIN#/ESPI_ALERT1#
GPP_A14/SUS_STAT#/ESPI_RESET#
GPP_A9/CLKOUT_LPC0/ESPI_CLK
GPP_A10/CLKOUT_LPC1
GPP_K19/SMI#
GPP_K18/NMI#
GPP_E6/SATA_DEVSLP2
GPP_E5/SATA_DEVSLP1
GPP_E4/SATA_DEVSLP0
GPP_F9/SATA_DEVSLP7
GPP_F8/SATA_DEVSLP6
GPP_F7/SATA_DEVSLP5
GPP_F6/SATA_DEVSLP4
GPP_F5/SATA_DEVSLP3
6 OF 13
CNP-H
GPP_A12/BM_BUSY#/ISH_GP6/SX_EXIT_HOLDOFF#
GPP_A13/SUSWARN#/SUSPWRDNACK
4 OF 13
RH445
@
1 2
0_0402_5%
DDR_XDP_WAN_SMBCLK <7,23,24,67>
DDR_XDP_WAN_SMBDAT <7,23,24,67>
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev1.0
GPP_A8/CLKRUN#
GPD11/LANPHYPC
GPD9/SLP_WLAN#
GPP_B2/VRALERT#
GPP_B1/GSPI1_CS1#/TIME_SYNC1
GPP_B0/GSPI0_CS1#
GPP_K17/ADR_COMPLETE
GPP_B11/I2S_MCLK
GPP_B12/SLP_S0#
GPD10/SLP_S5#
GPD0/BATLOW#
GPP_A15/SUSACK#
GPD2/LAN_WAKE#
GPD1/ACPRESENT
GPD3/PWRBTN#
PCH_JTAG_TMS
PCH_JTAG_TDO
PCH_JTAG_TCK
NDS3@
2 1
RB751S40T1G_SOD523-2
NDS3@
2018/01/01
2018/01/01
2018/01/01
ESPI_IO0_R
BB39
ESPI_IO1_R
AW37
ESPI_IO2_R
AV37
ESPI_IO3_R
BA38
BE38
ESPI_ALERT#
AW35
BA36
SIO_RCIN#
BE39
ESPI_RESET#
BF38
ESPI_CLK
BB36
PCI_CLK_LPC1
BB34
T48
TBT_RTD3_WAKE#_K18
T47
AH40
AH35
AL48
AP47
AN37
AN46
AR47
AP48
BF36
AV32
BF41
BD42
SYS_PWROK
WAKE#
SLP_LAN#
SLP_SUS#
SYS_RESET#
CPUPWRGD
ITP_PMODE
PCH_JTAGX
Rev1.0
SIO_SLP_SUS#
VCCDSW_EN_Q
21
DDR4_DRAMRST#_PCH
BB46
BE32
BF33
BE29
R47
AP29
AU3
BB47
BE40
BF40
BC28
BF42
BE42
BC42
BE45
BF44
BE35
BC37
BG44
BG42
BD39
BE46
AU2
AW29
AE3
AL3
AH4
AJ4
AH3
AH2
AJ3
PCH_DPWROK
PCH_PWROK
H_PWRGD
PCH_JTAGX
PCH_JTAG_TDI
PCH_JTAG_TDO
Compal Secret Data
Compal Secret Data
Compal Secret Data
DRAM_RESET#
GPD6/SLP_A#
GPD4/SLP_S3#
GPD5/SLP_S4#
GPD8/SUSCLK
GPP_B14/SPKR
PCH_JTAG_TDI
DH1
RB751S40T1G_SOD523-2
DH2
ESD request,P lace near PCH side.
2
1 2
RC366 0_0402_5%@
1 2
RC367 0_0402_5%@
1 2
RC368 0_0402_5%@
1 2
RC369 0_0402_5%@
RH97
1 2
EMI@
1
PAD~D
1 2
RH663 0_0402_5%@
HDD_DEVSLP <67>
M2280_DEVSLP <68>
1
@
T302
PAD~D
m3042_DEVSLP <52>
WWAN_BB_RST#_PCH
CLKRUN#
PM_LANPHY_ENABLE
SIO_SLP_WLAN#
DDR4_DRAMRST#_PCH
VRALERT#
SYS_PWROK
PCH_PCIE_WAKE#
SIO_SLP_A#
SIO_SLP_LAN#
SIO_SLP_S0#
SIO_SLP_S3#
SIO_SLP_S4#
SIO_SLP_S5#
SUSCLK
PCH_BATLOW#
SUSACK#_R
ME_SUS_PWR_ACK_R
LAN_WAKE#
AC_PRESENT
SIO_PWRBTN#
SYS_RESET#
SPKR
H_PWRGD
ITP_PMODE_CPU
PCH_JTAGX
PCH_JTAG_TMS
PCH_JTAG_TDO
PCH_JTAG_TDI
PCH_JTAG_TCK
1 2
RH441 0_0201_5%
DS3@
1 2
RH442 0_0402_5%
@NDS3@
1 2
CH558 0.1U_0201_10V6K@ESD@
1 2
CH556 0.1U_0201_10V6K@ESD@
1 2
CH553 0.1U_0201_10V6K@ESD@
1 2
CH551 0.1U_0201_10V6K@ESD@
1 2
CC305 0.1U_0402_25V6@ESD@
1 2
CC304 0.1U_0402_25V6@ESD@
1 2
CC303 0.1U_0402_25V6@ESD@
Deciphered Date
Deciphered Date
Deciphered Date
2
ESPI_IO0 <58,59>
ESPI_IO1 <58,59>
ESPI_IO2 <58,59>
ESPI_IO3 <58,59>
ESPI_CS# <58,59>
ESPI_ALERT# <58>
33_0402_5%
@
T424
CHECK,LPC_CLK FOR DEBUG CARD?
RC847 0_0201_5%@
PM_LANPHY_ENABLE <51>
SIO_SLP_WLAN# <78>
DDR4_DRAMRST#_PCH <23>
SYS_PWROK <7,58>
PCH_PCIE_WAKE# <42,58,59>
SIO_SLP_A# <19>
SIO_SLP_LAN# <78>
SIO_SLP_S0# <11,19,66,67,87>
SIO_SLP_S3# <19,42,59>
SIO_SLP_S4# <11,19,86,87>
SIO_SLP_S5# <19>
SUSCLK <52,68>
1
1
LAN_WAKE# <51,58>
AC_PRESENT <58>
SIO_SLP_SUS# <58>
SIO_PWRBTN# <7,58>
SYS_RESET# <15,19>
SPKR <56>
H_PWRGD <7>
1
ITP_PMODE_CPU <7>
PCH_JTAGX <7>
PCH_JTAG_TMS <7>
PCH_JTAG_TDO <7>
PCH_JTAG_TDI <7>
PCH_JTAG_TCK <7>
1
1
1
1
1
2020/01/01
2020/01/01
2020/01/01
ESPI_RESET# <58,59>
ESPI_CLK_5105 <58,59>
TBT_RTD3_WAKE# <15,42>
1 2
@
T421
PAD~D
@
T422
PAD~D
@
T192
PAD~D
@
T182
PAD~D
@
T183
PAD~D
@
T186
PAD~D
@
T187
PAD~D
@
T188
PAD~D
PCH_PRIM_EN <11,78,87>
SIO_SLP_S3#
SIO_SLP_S4#
SIO_SLP_A#
SIO_SLP_WLAN#
SIO_SLP_SUS#
SIO_SLP_LAN#
SIO_SLP_S5#
ESPI_RESET#
CFL-H CRB rev0.5
1 2
CH341 0.033U_0402_16V7@
1 2
CH342 0.033U_0402_16V7@
1 2
CH343 0.033U_0402_16V7@
1 2
CH344 0.033U_0402_16V7@
1 2
CH345 0.033U_0402_16V7@
1 2
CH346 0.033U_0402_16V7@
1 2
CH347 0.033U_0402_16V7@
1 2
CH348 0.033U_0402_16V7@
1
ESPI_RESET#
ESPI_ALERT#
ESPI_CLK_5105
SML0_SMBCLK
SML1_SMBCLK
MEM_SMBCLK
WWAN_BB_RST#_R <52>
VRALERT#
SIO_SLP_LAN#
PCH_PCIE_WAKE#
LAN_WAKE#
PCH_BATLOW#
AC_PRESENT
SIO_RCIN#
CLKRUN#
SYS_PWROK
DDR_XDP_WAN_SMBDAT
DDR_XDP_WAN_SMBCLK
IR_CAM_DET#
PCH_JTAG_TCK
PCH_PWROK
SUSCLK
PCH_JTAG_TMS
PCH_JTAG_TDI
PCH_JTAG_TDO
RH95 10K_0402_5%@
RH340 8.2K_0402_1%
ESD Reques t:place near PCH side
RF Request
CC316@RF@ 33P_0402_50V8J
CC318@RF@ 33P_0402_50V8J
CC319@RF@ 33P_0402_50V8J
CC320@RF@ 33P_0402_50V8J
Place close PCH side
RH203 10K_0201_5%@
RH204 10K_0201_5%@
RH92 1K_0402_5%
RH93 10K_0402_5%
RH94 8.2K_0402_5%
RH243 10K_0402_5%
RH199 100K_0402_5%
RH374 2.2K_0402_5%
RH333 2.2K_0402_5%
RH373 100K_0402_5%
RH313 51_0402_5%@
RH424
RH83 1K_0402_5%@
1 2
RH312 51_0402_5%
1 2
RH314 51_0402_5%
1 2
RH315 51_0402_5%
PCH Signal Gl itch
SIO_SLP_S0#
PCH Signal Glitch Free Implementation Requirements
SIO_SLP_S3#
SIO_SLP_S4#
SIO_SLP_A#
SIO_SLP_WLAN#
SIO_SLP_SUS#
SIO_SLP_LAN#
SIO_SLP_S5#
ESPI_RESET#
1 2
RH640 100K_0201_5%@
RH626 100K_0201_5%@
RH627 100K_0201_5%@
RH628 100K_0201_5%@
RH629 100K_0201_5%@
RH630 100K_0201_5%@
RH631 100K_0201_5%@
RH632 100K_0201_5%@
RH633 75K_0201_5%@
1 2
1 2
SYS_RESET#
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1
PAD~D
1
PAD~D
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
+3.3V_1.8V_GPPA
0.1U_0402_25V6
12
+3.3V_ALW_PCH
+3.3V_DSW
+3.3V_RUN
@
T286
@
T287
10K_0201_5%@
+1.0V_VCCSTG
+3.3V_ALW_PCH
@ESD@
CC302
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
CannonLake PCH-H (5/9)
CannonLake PCH-H (5/9)
CannonLake PCH-H (5/9)
Size
Size
Size
Document Number Re v
Document Number Re v
Document Number Re v
B
B
B
LA-H171P
LA-H171P
LA-H171P
Monday, March 11, 2019
Monday, March 11, 2019
Monday, March 11, 2019
Date: Sheet o f
Date: Sheet o f
Date: Sheet o f
1
18 100
18 100
18 100
0.1
0.1
0.1
+3.3V_RUN
smd.db-x7.ru
1 2
RH378 10K_0201_5%
1 2
RH361 49.9K_0402_1%@
1 2
RH355 10K_0402_1%
1 2
D D
RH339 10K_0402_5%
1 2
RH331 4.7K_0402_5%@
PCH STRAPS IF SAMPLED HIGH[ NO REBOOT ]
+3.3V_ALW_PCH
1 2
RH309 10K_0201_5%
1 2
RH376 49.9K_0402_1%
1 2
RH1 100K_0402_5%
5
FFS_INT2
LPSS_UART2_RXD
HDD_FALL_INT
TPM_PIRQ#_B20
NRB_BIT
SIO_EXT_WAKE#
LPSS_UART2_RXD
EDP_HPD
PCH_3.3V_TS_EN<38>
1 2
RC561 0_0402_5%@
TPM_PIRQ#<66>
HDD_EN<67>
TS
1 2
RC560 0_0402_5%
MEDIACARD_IRQ#<70>
SBIOS_TX<59>
RH625 0_0402_5%@
LCD_CBL_DET#<38>
SIO_EXT_WAKE#<58>
I2C1_SCK_TP<63>
I2C1_SDA_TP<63>
I2C0_SCL_TS<38>
I2C0_SDA_TS<38>
TBT_FORCE_PWR<42>
FFS_INT2<67>
12
TS_INT#<38>
4
BBS_BIT6
PCH_3.3V_TS_EN
TPM_PIRQ#_B20
HDD_FALL_INT<67>
NRB_BIT
TPM_PIRQ#_R
ONE_DIMM#
MEDIACARD_IRQ#
TYPEC_CON_SEL2
TYPEC_CON_SEL1
PCH_HDD_EN
LCD_CBL_DET#
SIO_EXT_WAKE#
TS_INT#
LPSS_UART2_RXD
I2C1_SCK_TP
I2C1_SDA_TP
TBT_FORCE_PWR
FFS_INT2
UH1K
BA26
GPP_B22/GSPI1_MOSI
BD30
GPP_B21/GSPI1_MISO
AU26
GPP_B20/GSPI1_CLK
AW26
GPP_B19/GSPI1_CS0#
BE30
GPP_B18/GSPI0_MOSI
BD29
GPP_B17/GSPI0_MISO
BF29
GPP_B16/GSPI0_CLK
BB26
GPP_B15/GSPI0_CS0#
BB24
GPP_C9/UART0A_TXD
BE23
GPP_C8/UART0A_RXD
AP24
GPP_C11/UART0A_CTS#
BA24
GPP_C10/UART0A_RTS#
BD21
GPP_C15/UART1_CTS#/ISH_UART1_CTS#
AW24
GPP_C14/UART1_RTS#/ISH_UART1_RTS#
AP21
GPP_C13/UART1_TXD/ISH_UART1_TXD
AU24
GPP_C12/UART1_RXD/ISH_UART1_RXD
AV21
GPP_C23/UART2_CTS#
AW21
GPP_C22/UART2_RTS#
BE20
GPP_C21/UART2_TXD
BD20
GPP_C20/UART2_RXD
BE21
GPP_C19/I2C1_SCL
BF21
GPP_C18/I2C1_SDA
BC22
GPP_C17/I2C0_SCL
BF23
GPP_C16/I2C0_SDA
BE15
GPP_D4/ISH_I2C2_SDA/I2C3_SDA/SBK4_BK4
BE14
GPP_D23/ISH_I2C2_SCL/I2C3_SCL
CNP-H_BGA874
3
CNP-H
GPP_D9/ISH_SPI_CS#/GSPI2_CS0#
GPP_D11/ISH_SPI_MISO/GP_BSSB_CLK/GSPI2_MISO
GPP_D15/ISH_UART0_RTS#/GSPI2_CS1#/CNV_WFEN
GPP_D10/ISH_SPI_CLK/GSPI2_CLK
GPP_D12/ISH_SPI_MOSI/GP_BSSB_DI/GSPI2_MOSI
GPP_D16/ISH_UART0_CTS#/CNV_WCEN
GPP_D14/ISH_UART0_TXD/I2C2_SCL
GPP_D13/ISH_UART0_RXD/I2C2_SDA
GPP_H20/ISH_I2C0_SCL
GPP_H19/ISH_I2C0_SDA
GPP_H22/ISH_I2C1_SCL
GPP_H21/ISH_I2C1_SDA
GPP_A23/ISH_GP5
GPP_A22/ISH_GP4
GPP_A21/ISH_GP3
GPP_A20/ISH_GP2
GPP_A19/ISH_GP1
GPP_A17/SD_VDD1_PWR_EN#/ISH_GP7
11 OF 13
GPP_A18/ISH_GP0
Rev1.0
BA20
BB20
BB16
AN18
BF14
AR18
BF17
BE17
AG45
AH46
AH47
AH48
AV34
AW32
BA33
BE34
BD34
BF35
BD38
MEM_INTERLEAVED
DGPU_HOLD_RST#
AR_DET#
DGPU_PWR_EN
LID_CL#_PCH
TPM_TYPE
CLKDET#
2
1
T37 PAD~D@
1
T38 PAD~D@
LCD_CBL_DET#
PCH_DP2_CTRL_DATA
PCH_DP1_CTRL_CLK
PCH_DP1_CTRL_DATA
PCH_DP3_CTRL_CLK
PCH_DP3_CTRL_DATA
1
@
T268
PAD~D
1
@
T258
PAD~D
TPM_TYPE
Reser ved
1
1 2
RC370 10K_0402_5%
1 2
RH221 2.2K_0402_5%
1 2
RH222 2.2K_0402_5%
1 2
RH223 2.2K_0402_5%
1 2
RH224 2.2K_0402_5%
1 2
RH225 2.2K_0402_5%
1 2
RH379 100_0402_1%@
+3.3V_RUN
C C
B B
A A
+3.3V_ALW_PCH
12
RH311
@
8.2K_0201_5%
BBS_BIT6
BOOT BIOS Dest i nat i on(Bi t 6)
HIGH
LOW(DEFAULT)
LPC
SPI
+3.3V_RUN
10K_0201_5%
RH267@
1 2
ONE_DIMM#
10K_0201_5%
12
RH268
PCH_DP1_HPD<42>
PCH_DP2_HPD<42>
PCH_DP3_HPD<40>
EDP_HPD<38>
PCH_DP1_HPD
PCH_DP2_HPD
PCH_DP3_HPD
EDP_HPD
MEM_INTERLEAVED
DIMM Detect
HIGH
LOW
1 DIMM
2 DIMM
UH1E
AT6
GPP_I0/DDPB_HPD0/DISP_MISC0
AN10
GPP_I1/DDPC_HPD1/DISP_MISC1
AP9
GPP_I2/DPPD_HPD2/DISP_MISC2
AL15
GPP_I3/DPPE_HPD3/DISP_MISC3
AN6
GPP_I4/EDP_HPD/DISP_MISC4
CNP-H_BGA874
@
RH371
10K_0201_5%
1 2
12
RH372
10K_0201_5%
CNP-H
5 OF 13
DIMM TYPE
HIGH Inte rleave
Non-Inte rleaveLOW
GPP_I5/DDPB_CTRLCLK
GPP_I6/DDPB_CTRLDATA
GPP_I7/DDPC_CTRLCLK
GPP_I8/DDPC_CTRLDATA
GPP_I9/DDPD_CTRLCLK
GPP_I10/DDPD_CTRLDATA
GPP_F23/DDPF_CTRLDATA
GPP_F22/DDPF_CTRLCLK
GPP_F14/PS_ON#
GPP_K23/IMGCLKOUT1
GPP_K22/IMGCLKOUT0
GPP_K21
GPP_K20
GPP_H23/TIME_SYNC0
AR_DET#
Rev1.0
AL13
AR8
AN13
AL10
AL9
AR3
AN40
AT49
AP41
M45
L48
T45
T46
AJ47
PCH_DP1_CTRL_CLK
PCH_DP1_CTRL_DATA
PCH_DP2_CTRL_DATA
PCH_DP3_CTRL_CLK
PCH_DP3_CTRL_DATA
+3.3V_ALW_PCH+3.3V_ALW_PCH
RH400
@
10K_0201_5%
1 2
12
RH401
10K_0201_5%
AR_DET#
Check ME about wire to board PN
SIO_SLP_S3#<18,42,59>
SIO_SLP_S5#<18>
SIO_SLP_S4#<11,18,86,87>
SIO_SLP_A#<18>
PCH_RTCRST#<18,58>
POWER_SW#_MB<59,62,66>
SYS_RESET#<15,18>
SIO_SLP_S0#<11,18,66,67,87>
NON ARH IGH
ARLO W
Intel Management Engine Test Suite
JAPS1 FOLLOW MERION 14 schmatic 0529
+3.3V_ALW_PCH+3.3V_ALW_PCH
RH555
@
10K_0402_5%
1 2
TYPEC_CON_SEL2TYPEC_CON_SEL1
12
RH556
@
10K_0402_5%
Vendor FOXCON TBD TBD
JAE
LOWT YPEC_CON_SEL1
LOW
TYPEC_CON_S EL2
+3.3V_ALW_PCH
+3.3V_ALW
+3.3V_ALW
LOW
10
11
12
13
14
15
16
17
18
19
20
CVILU_CF4218FH0R0-05-NH
CONN@
1
2
3
4
5
6
7
8
9
1 2
12
JAPS1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
GND1
GND2
RH553
@
10K_0402_5%
RH554
@
10K_0402_5%
HIGH
LOWHIGH
HIGH
HIGH
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2018/01/01
2018/01/01
2018/01/01
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2020/01/01
2020/01/01
2020/01/01
2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
CannonLake PCH-H (6/9)
CannonLake PCH-H (6/9)
CannonLake PCH-H (6/9)
Size
Size
Size
Document Number Re v
Document Number Re v
Document Number Re v
B
B
B
LA-H171P
LA-H171P
LA-H171P
Friday, March 08, 2019
Friday, March 08, 2019
Friday, March 08, 2019
Date: Sheet o f
Date: Sheet o f
Date: Sheet o f
1
19 100
19 100
19 100
0.1
0.1
0.1
5
smd.db-x7.ru
4
3
2
1
+1.8V_PRIM_PCH
+3.3V_PRTC
0.000416A
1 2
BLM15GA750SN1D_2P
1
CC332
2
@
0.1U_0201_10V6K
1 2
BLM15GA750SN1D_2P
1
CC330
2
@
0.1U_0201_10V6K
+1.0V_PRIM
5.95A
+1.0V_MPHY
+1.0V_PRIM_FUSE
+1.0V_PRIM_CNV_HVLO
+1.0V_DUSB
+1.0V_DSW
+1.0V_CLPLLEBB
+1.0V_AMPHYPLL
+1.0V_BCLKPLL2_R
+1.0V_AZPLL
+1.0V_XTAL
+1.0V_SRC
+1.0V_OC
+1.0V_OCPLL1_R
LC3
1
CC331
2
0.1U_0201_10V6K
LC2
1
CC311
2
0.1U_0201_10V6K
UH1H
AA22
VCCPRIM_1P051
AA23
VCCPRIM_1P052
AB20
VCCPRIM_1P053
AB22
VCCPRIM_1P054
AB23
VCCPRIM_1P055
AB27
VCCPRIM_1P056
AB28
VCCPRIM_1P057
AB30
VCCPRIM_1P058
AD20
VCCPRIM_1P059
AD23
VCCPRIM_1P0510
AD27
VCCPRIM_1P0511
AD28
VCCPRIM_1P0512
AD30
VCCPRIM_1P0513
AF23
VCCPRIM_1P0516
AF27
VCCPRIM_1P0517
AF30
VCCPRIM_1P0518
U26
VCCPRIM_1P0523
U29
VCCPRIM_1P0524
V25
VCCPRIM_1P0525
V27
VCCPRIM_1P0526
V28
VCCPRIM_1P0527
V30
VCCPRIM_1P0528
V31
VCCPRIM_1P0529
AD31
VCCPRIM_1P0514
AE17
VCCPRIM_1P0515
W22
VCCDUSB_1P051
W23
VCCDUSB_1P052
BG45
VCCDSW_1P051
BG46
VCCDSW_1P052
W31
VCCPRIM_MPHY_1P05
D1
VCCPRIM_1P0521
E1
VCCPRIM_1P0522
C49
VCCAMPHYPLL_1P051
D49
VCCAMPHYPLL_1P052
E49
VCCAMPHYPLL_1P053
P2
VCCA_XTAL_1P051
P3
VCCA_XTAL_1P052
W19
VCCA_SRC_1P051
W20
VCCA_SRC_1P052
C1
VCCAPLL_1P054
C2
VCCAPLL_1P055
V19
VCCA_BCLK_1P05
B1
VCCAPLL_1P051
B2
VCCAPLL_1P052
B3
VCCAPLL_1P053
CNP-H_BGA874
CNP-H
8 OF 13
VCCPRIM_3P32
DCPRTC1
DCPRTC2
VCCPRIM_3P35
VCCSPI
VCCRTC1
VCCRTC2
VCCPGPPG_3P3
VCCPRIM_3P33
VCCPRIM_3P34
VCCPGPPHK1
VCCPGPPHK2
VCCPGPPEF1
VCCPGPPEF2
VCCPGPPD
VCCPGPPBC1
VCCPGPPBC2
VCCPGPPA
VCCPRIM_3P31
VCCDSW_3P31
VCCDSW_3P32
VCCHDA
VCCPRIM_1P83
VCCPRIM_1P84
VCCPRIM_1P85
VCCPRIM_1P86
VCCPRIM_1P87
VCCPRIM_1P81
VCCPRIM_1P82
VCCPRIM_1P0520
VCCPRIM_1P0519
VCCPRIM_1P241
VCCPRIM_1P242
VCCDPHY_1P241
VCCDPHY_1P242
VCCDPHY_1P243
VCCMPHY_SENSE
VSSMPHY_SENSE
Rev1.0
AW9
BF47
BG47
V23
AN44
BC49
BD49
AN21
AY8
BB7
AC35
AC36
AE35
AE36
AN24
AN26
AP26
AN32
AT44
BE48
BE49
BB14
AG19
AG20
AN15
AR15
BB11
AF19
AF20
AG31
AF31
AK22
AK23
AJ22
AJ23
BG5
K47
K46
+VCCRTCEXT
0.766A
+2.8V_FHV1
+1.24V_DPHY
+3.3V_PHVC
+3.3V_PUSB2
+3.3V_1.8V_SPI
+3.3V_PRTC
+3.3V_PGPPG
+3.3V_PHVLDO
+3.3V_PGPPHK
+3.3V_PGPPEF
+3.3V_1.8V_GPPD
+3.3V_PGPPBC
+3.3V_1.8V_GPPA
+3.3V_FUSE
+3.3V_DSW
+1.8V_PRIM_PCH
+1.8V_PHVLDO
1
PAD~D
1
PAD~D
+3.3V_1.8V_AZIO_R
+2.8V_FHV0
+1.24V_LDOSRAM
+1.24V_DPHY_MAR
VCCMPHY_SENSE <87>
VSSMPHY_SENSE <87>
@
T76
@
T77
0.1U_0201_10V6K
1
2
BLM15GA750SN1D_2P
1
CC310
2
0.1U_0201_10V6K
1
1
CH68
12
PAD~D
PAD~D
@
0.1U_0201_10V6K
@
@
1
CC329
2
T74
T75
+3.3V_1.8V_AZIO
LC1
+RTC_CELL_PCH
1 2
RH297@ 0_0402_5%
+1.8V_PRIM
1 2
RH242 0_0603_5%@
+1.8V_PHVLDO
1 2
RH239 0_0603_5%@
+1.24V_DPHY +1.24V_LDOSRAM
1 2
RH237@ 0_0402_5%
+1.0V_OCPLL1
+1.0V_BCLKPLL2
RH294
@ESPI@
RH296 0_0402_5%@
RH295 0_0402_5%@
RH250 0_0402_5%@
+1.8V_PRIM
+1.8V_ALW_PCHRES
12
0_0402_5%
+1.8V_ALW_PCHRES
12
+1.8V_ALW_PCHRES
12
+1.8V_ALW_PCHRES
12
+1.8V_ALW_PCHRES
12
RH2470_0603_5%
0.882A
+1.0V_ALW_PCH+1.0V_PRIM
1 2
RH254 0_1206_5%
+1.0V_ALW_PCH
D D
RH255 0_0402_5%@
RH256@ 0_0402_5%
RH257@ 0_0402_5%
RH258@ 0_0402_5%
RH259@ 0_0402_5%
RH286@ 0_0402_5%
RH287@ 0_0402_5%
C C
RH288@ 0_0402_5%
JUMP@
2
RH290@ 0_0402_5%
RH260@ 0_0402_5%
RH240@ 0_0402_5%
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
PJP3
112
JUMP_43X79
1 2
1 2
1 2
+1.0V_DSW
0.0454A
+1.0V_PRIM_FUSE
0.0012A
+1.0V_PRIM_CNV_HVLO
0.2A
+1.0V_SRC
0.169A
+1.0V_BCLKPLL2
0.021A
+1.0V_DUSB
0.42A
+2.8V_FHV0
0.0859A
+2.8V_FHV1
0.193A
+1.0V_MPHY
6.66A
+1.0V_CLPLLEBB
0.109A
+1.0V_OC
0.0085A
+1.0V_OCPLL1
0.0198A
RH279 0_1206_5%
+3.3V_ALW_PCHRES
RH292@ 0_0402_5%
RH300@ 0_0402_5%
RH299@ 0_0402_5%
RH298@ 0_0402_5%
RH302@ 0_0402_5%
RH291 0_0402_5%
LPC@
RH304@ 0_0402_5%
RH293@ 0_0402_5%
RH303@ 0_0402_5%
RH305@ 0_0402_5%
RH306@ 0_0402_5%
RH246@ 0_0402_5%
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
+3.3V_ALW_PCHRES+3.3V_ALW_PCH
eSPI Power
+3.3V_1.8V_GPPA
0.101A
+3.3V_PGPPBC
0.343A
+3.3V_1.8V_GPPD
0.14A
+3.3V_PGPPEF
0.174A
+3.3V_PGPPG
0.145A
+3.3V_PGPPHK
0.262A
+3.3V_1.8V_SPI
0.05A
+3.3V_1.8V_AZIO
0.00767A
+3.3V_FUSE
0.106A
+3.3V_PHVC
0.182A
+3.3V_PHVLDO
0.97A
+3.3V_PUSB2
0.095A
2018/01/01
2018/01/01
2018/01/01
CNP-H
UH1J
RSVD7
RSVD8
RSVD6
RSVD5
RSVD3
RSVD4
RSVD2
RSVD1
PREQ#
PRDY#
CPU_TRST#
TRIGGER_OUT
TRIGGER_IN
10 OF 13
Rev1.0
CNP-H_BGA874
1 2
RH42 30_0402_5%
Compal Secret Data
Compal Secret Data
Compal Secret Data
Y14
Y15
U37
U35
N32
R32
AH15
AH14
PCH_XDP_PREQ#
AL2
PCH_XDP_PRDY#
AM5
CPU_XDP_TRST#
AM4
PCH_2_CPU_TRIGGER_R
AK3
CPU_2_PCH_TRIGGER
AK2
PCH_2_CPU_TRIGGERPCH_2_CPU_TRIGGER_R
Deciphered Date
Deciphered Date
Deciphered Date
1
@
T73
PAD~D
1
@
T72
PAD~D
1
@
T71
PAD~D
1
@
T70
PAD~D
1
@
T69
PAD~D
1
@
T68
PAD~D
1
@
T67
PAD~D
1
@
T66
PAD~D
PCH_XDP_PREQ# <7>
PCH_XDP_PRDY# <7>
CPU_XDP_TRST# <7>
CPU_2_PCH_TRIGGER <10>
PCH_2_CPU_TRIGGER <10>
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
2020/01/01
2020/01/01
2020/01/01
2
Title
CannonLake PCH-H (7/9)
CannonLake PCH-H (7/9)
CannonLake PCH-H (7/9)
Size
Size
Size
Document Number Re v
Document Number Re v
Document Number Re v
B
B
B
LA-H171P
LA-H171P
LA-H171P
Monday, March 11, 2019
Monday, March 11, 2019
Monday, March 11, 2019
Date: Sheet o f
Date: Sheet o f
Date: Sheet o f
1
20 100
20 100
20 100
0.1
0.1
0.1
B B
RF Request
+3.3V_1.8V_AZIO_R +1.0V_CLPLLEBB
A A
5
1
2
CC327
RF@
1
2
CC328
RF@
2.2P_0402_50V8C
2.2P_0402_50V8C
+3.3V_DSW
0.113A
12
RH440
1 2
1 2
4
0_0402_5%
+3.3V_ALW_DSW_R
@NDS3@
RH434 0_0402_5%@
RH439 0_0402_5%
DS3@
+3.3V_ALW_PCH
QH7DS3@
LP2301ALT1G_SOT23-3
123
D
S
G
0.1U_0402_25V6K
49.9K_0402_1%
DS3@
RH433
12
12
@
CH340
L2N7002WT1G_SC-70-3
13
D
DS3@
QH6
2
G
S
12
+3.3V_ALW
499K_0402_1%
DS3@
RH432
1 2
100K_0402_5%
RH431
VCCDSW_EN_GPIO <18>
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
5
smd.db-x7.ru
4
3
2
1
+1.0V_ALW_PCH +1.0V_AMPHYPLL
PDG V1P8 Table 50-9. +1.0V_AMPHYPLL
2x 22uF 0603 pop
D D
1x 2.2 uH 0603 pop
1x 1uF 0402 pop
LH423
RH289 0_0603_5%@
LQM18PN2R2NC0L_2P~D
1 2
1 2
0.213A
1U_0201_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1
1
CH350
2
2
1U_0201_6.3V6M
CH267
CH555
1
1
CH324
2
2
1 2
RH241 0_0603_5%
1U_0201_6.3V6M
@
1
CH29
PDG V1P8
2
Table 50-8. +1.0V_AZPLL
1x 4.7uF, 0402 pop
8/15 downsize to SE00000UC00 add 1 uF
+1.0V_BCLKPLL2_R
1U_0201_6.3V6M
CH31
1
2
+1.0V_DSW +1.0V_PRIM
1U_0201_6.3V6M
CH35
1
2
1
2
+1.0V_MPHY
1U_0201_6.3V6M
CH36
1U_0201_6.3V6M
CH34
1
2
1
2
22U_0603_6.3V6M
CH47
+1.0V_CLPLLEBB
0.1U_0201_10V6K
CH66
1
2
+1.0V_AZPLL+1.0V_ALW_PCH
1U_0201_6.3V6M
4.7U_0402_6.3V6M
@
CH46
1
1
CH32
2
2
8/15 downsize to SE00000UC00
+1.0V_DUSB
0.1U_0201_10V6K
CH38
1
2
+1.0V_ALW_PCH
LQM18PN2R2NC0L_2P~D
LH421
1 2
1 2
RH238 0_0603_5%@
KBL WHEA issue INTEL recommend
2x 22uF 0603 pop
1x 2.2 uH 0603 pop
RH238 depop
+1.0V_OC
0.1U_0201_10V6K
1
2
+1.0V_OCPLL1_R
@
CH44
1
2
1U_0201_6.3V6M
CH20
+1.0V_XTAL
0.00428A0.0015A
22U_0603_6.3V6M
1
CH349
2
CH20 close PCH
22U_0603_6.3V6M
1
2
CH45
RF Request
100P_0402_50V8J
RF@
1
CH2
2
8/15 downsize to SE00000UC00
8/15 downsize to SE00000UC00
C C
+1.8V_PRIM_PCH
1U_0201_6.3V6M
CH21
1
2
8/15 downsize to SE00000UC00
+3.3V_PRTC
B B
+1.24V_DPHY_MAR
4.7U_0402_6.3V6M
1
CH22
2
8/17 add one more 4.7 uF
8/15 downsize to SE00000SV00
1U_0201_6.3V6M
CH33
1
2
8/15 downsize to SE00000UC00
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
1
1
CH559
CH30
2
2
0.1U_0201_10V6K
CH65
1
2
+3.3V_PGPPHK
0.1U_0201_10V6K
1
2
@
CH64
8/15 downsize to SE00000UC00 8/15 downsize to SE00000SV00
8/15 downsize to SE00000SV00
+3.3V_PGPPEF
0.1U_0201_10V6K
@
CH62
1
2
+3.3V_DSW
+3.3V_PHVLDO
0.1U_0201_10V6K
@
CH63
1
2
1U_0402_6.3VAK
1
CH37
2
4.7U_0402_6.3V6M
0.1U_0201_10V6K
@
CH67
1
1
2
CH323
2
8/15 downsize to SE00000SV00
CFL-H PDG rev0.5
4.7uF x1
CRB-H rev0.7
0.1uF x1, 1uF x1
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2018/01/01
2018/01/01
2018/01/01
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2020/01/01
2020/01/01
2020/01/01
2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
CannonLake PCH-H (8/9)
CannonLake PCH-H (8/9)
CannonLake PCH-H (8/9)
Size
Size
Size
Document Number Re v
Document Number Re v
Document Number Re v
B
B
B
LA-H171P
LA-H171P
LA-H171P
Monday, March 11, 2019
Monday, March 11, 2019
Monday, March 11, 2019
Date: Sheet o f
Date: Sheet o f
Date: Sheet o f
1
21 100
21 100
21 100
0.1
0.1
0.1
5
smd.db-x7.ru
D D
4
3
2
1
CNP-H
UH1I
A2
VSS_1
A28
VSS_2
A3
VSS_3
A33
VSS_4
A37
VSS_5
A4
VSS_6
A45
VSS_7
A46
VSS_8
A47
VSS_9
A48
VSS_10
A5
VSS_11
A8
VSS_12
AA19
VSS_13
AA20
VSS_14
AA25
VSS_15
AA27
VSS_16
AA28
VSS_17
AA30
VSS_18
AA31
VSS_19
AA49
VSS_20
AA5
VSS_21
AB19
VSS_22
AB25
VSS_23
AB31
VSS_24
AC12
C C
B B
AC17
AC33
AC38
AC46
AD19
AD22
AD25
AD49
AE12
AE33
AE38
AE46
AF22
AF25
AF28
AG22
AG23
AG25
AG27
AG28
AG30
AG49
AH12
AH17
AH33
AH38
AJ19
AJ20
AJ25
AJ27
AJ28
AJ30
AJ31
AK19
AK20
AK25
AK27
AK28
AK30
AK31
AK46
AC4
AD1
AD2
AE4
AG1
AK4
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
CNP-H_BGA874
9 OF 13
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
Rev1.0
AL12
AL17
AL21
AL24
AL26
AL29
AL33
AL38
AM1
AM18
AM32
AM49
AN12
AN16
AN34
AN38
AP4
AP46
AR12
AR16
AR34
AR38
AT1
AT16
AT18
AT21
AT24
AT26
AT29
AT32
AT34
AT45
AV11
AV39
AW10
AW4
AW40
AW46
B47
B48
B49
BA12
BA14
BA44
BA5
BA6
BB41
BB43
BB9
BC10
BC13
BC15
BC19
BC24
BC26
BC31
BC35
BC40
BC45
BC8
BD43
BE44
BF1
BF2
BF3
BF48
BF49
BG17
BG2
BG22
BG25
BG28
BG33
BG37
BG48
BG3
BG4
C12
C25
C30
C4
C48
C5
D12
D16
D17
D30
D33
D8
E10
E13
E15
E17
E19
E22
E24
E26
E31
E33
E35
E40
E42
E8
F41
F43
F47
G44
G6
H8
J10
J26
J29
J4
J40
J46
J47
J48
J9
K11
K39
M16
M18
M21
CNP-H
UH1L
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
12 OF 13
VSS_195
CNP-H_BGA874
VSS_196
VSS_197
VSS_198
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
Rev1.0
M24
M32
M34
M49
M5
N12
N16
N34
N35
N37
N38
P26
P29
P4
P46
R12
R16
R26
R29
R3
R34
R38
R4
T17
T18
T32
T4
T49
T5
T7
U12
U15
U17
U21
U24
U33
U38
V20
V22
V4
V46
W25
W27
W28
W30
Y10
Y12
Y17
Y33
Y38
Y9
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2018/01/01
2018/01/01
2018/01/01
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2020/01/01
2020/01/01
2020/01/01
2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
CannonLake PCH-H (9/9)
CannonLake PCH-H (9/9)
CannonLake PCH-H (9/9)
Size
Size
Size
Document Number Re v
Document Number Re v
Document Number Re v
B
B
B
LA-H171P
LA-H171P
LA-H171P
Friday, March 08, 2019
Friday, March 08, 2019
Friday, March 08, 2019
Date: Sheet o f
Date: Sheet o f
Date: Sheet o f
1
22 100
22 100
22 100
0.1
0.1
0.1
5
smd.db-x7.ru
DDR_A_DQS#[0..7]<8>
DDR_A_DQS[0..7]<8>
DDR_A_D[0..15]<8>
DDR_A_D[16..31]<8>
DDR_A_D[32..47]<8>
DDR_A_D[48..63]<8>
DDR_A_MA[0..16]<8>
D D
C C
B B
A A
Layout Note:
Place near JDIMM1
+1.2V_MEM
10U_0603_6.3V6M
10U_0603_6.3V6M
CD3
CD2
1
2
1U_0201_10V6M
1U_0201_10V6M
CD11
CD10
1
2
1U_0201_10V6M
CD23
CD22
1
1
2
2
0
0
0
1
0
1
1
DQ[7:0]
DQ[15:8]
DQ[23:16]
DQ[31:24]
DQ[39:32]
5
10U_0603_6.3V6M
10U_0603_6.3V6M
CD4
1
1
2
2
1U_0201_10V6M
1U_0201_10V6M
CD12
1
1
2
2
1U_0201_10V6M
CD24
SA2
0
0
0
0
DQS/DQS#[0]
DQS/DQS#[1]
DQS/DQS#[2]
DQS/DQS#[3]
DQS/DQS#[4]
DQS/DQS#[5]
DQS/DQS#[6]
DQS/DQS#[7]
10U_0603_6.3V6M
CD6
CD5
1
1
2
2
1U_0201_10V6M
CD13
CD14
1
1
2
2
FOLLOW PDG V1P8 P.136
VDDQ 16x 10μ F (0603)
VDDQ 16x 1μ F (0402),INTEL reply can downsize to 0201
VPP 2x 10μ F (0603)
VPP 2x 1μ F (0402),INTEL reply can downsize to 0201
12
RD4
@
0_0402_5%
12
RD5
@
0_0402_5%
10U_0603_6.3V6M
CD1
1
1
2
2
1U_0201_10V6M
CD9
1
1
2
2
Layout Note:
Place near
JDIMM1.258
+0.6V_DDR_VTT
10U_0603_6.3V6M
1
2
FOLLOW PDG V1P8 P.136
2x 10μ F (0603)
4x 1μ F (0402),INTEL reply can downsize to 0201
DIMM Select
SA01SA1
DIMM1
*
DIMM2
DIMM3
DIMM4
Byte[0]
Byte[1]
Byte[2]
Byte[3]
*
Byte[4]
Byte[5]
*
Byte[6]
Byte[7]
DQ[47:40]
DQ[55:48]
DQ[63:56]
330U_D3_2.5VY_R6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1
@
CD21
CD8
CD7
1
+
2
2
+2.5V_MEM
1U_0201_10V6M
CD15
12
12
1U_0201_10V6M
1
2
RD6
@
0_0402_5%
RD7
@
0_0402_5%
CD16
+DDR_VREF_A_CA
12
@
0_0402_5%
12
1
2
1
2
RD8
DIMM1_SA0
DIMM1_SA1
DIMM1_SA2
RD9
@
0_0402_5%
1U_0201_10V6M
1U_0201_10V6M
10U_0603_6.3V6M
CD18
CD17
1
1
CD19
2
2
0.1U_0201_6.3V6K
2.2U_0402_6.3V6M
@
1
CD25
CD26
2
+3.3V_RUN+3.3V_RUN+3.3V_RUN+3.3V_RUN
12
1
2
10U_0603_6.3V6M
1
2
RD10
@
0_0603_5%
2.2U_0402_6.3V6M
CD27
CD20
+3.3V_RUN_DIMM1
0.1U_0201_10V6K
1
CD28
2
4
3
2
1
Link LOTES_ADDR0206-P001A02 done 0718
CONN@
JDIMM1A
DDR_A_CLK0<8>
DDR_A_CLK#0<8>
DDR_A_CLK1<8>
DDR_A_CLK#1<8>
DDR_A_CKE0<8>
DDR_A_CKE1<8>
DDR_A_CS#0<8>
DDR_A_CS#1<8>
DDR_A_ODT0<8>
DDR_A_ODT1<8>
DDR_A_BG0<8>
DDR_A_BG1<8>
DDR_A_PAR<8>
1
CD29
@
0.1U_0402_25V6
4
2
DDR_A_ALERT#<8>
DDR_XDP_WAN_SMBDAT<7,18,24,67>
DDR_XDP_WAN_SMBCLK<7,18,24,67>
+1.2V_MEM
JDIMM1_EVENT#
DDR_A_CLK0
DDR_A_CLK#0
DDR_A_CLK1
DDR_A_CLK#1
DDR_A_CKE0
DDR_A_CKE1
DDR_A_CS#0
DDR_A_CS#1
1
T50PAD~D @
1
T51PAD~D @
DDR_A_ODT0
DDR_A_ODT1
DDR_A_BG0
DDR_A_BG1
DDR_A_BA0
DDR_A_BA0<8>
DDR_A_BA1
DDR_A_BA1<8>
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15
DDR_A_MA16
DDR_A_ACT#
DDR_A_ACT#<8>
DDR_A_PAR
DDR_A_ALERT#
JDIMM1_EVENT#
DDR_DRAMRST#
DIMM1_SA2
DIMM1_SA1
DIMM1_SA0
1 2
RD14 1K_0402_5%@
+1.2V_MEM
12
RD11
470_0402_1%
1 2
RD12 0_0402_5%@
12
ESD@
3
REVERSE
137
CK0(T)
139
CK0#(C)
138
CK1(T)
140
CK1#(C)
109
CKE0
110
CKE1
149
S0#
157
S1#
162
S2#/C0
165
S3#/C1
155
ODT0
161
ODT1
115
BG0
113
BG1
150
BA0
145
BA1
144
A0
133
A1
132
A2
131
A3
128
A4
126
A5
127
A6
122
A7
125
A8
121
A9
146
A10_AP
120
A11
119
A12
158
A13
151
A14_WE#
156
A15_CAS#
152
A16_RAS#
114
ACT#
143
PARITY
116
ALERT#
134
EVENT#
108
RESET#
254
SDA
253
SCL
166
SA2
260
SA1
256
SA0
92
CB0_NC
91
CB1_NC
101
CB2_NC
105
CB3_NC
88
CB4_NC
87
CB5_NC
100
CB6_NC
104
CB7_NC
97
DQS8(T)
95
DQS8#(C)
12
DM0#/DBI0#
33
DM1#/DBI1#
54
DM2#/DBI2#
75
DM3#/DBI3#
178
DM4#/DBI4#
199
DM5#/DBI5#
220
DM6#/DBI6#
241
DM7#/DBI7#
96
DM8#/DBI8#
LOTES_ADDR0206-P001A
H_THERMTRIP# <7,14,24,59>
DDR4_DRAMRST#_PCH
DD32
PESD5V0V1BDSF SOD962
DVT1.0
ESD request
8
DQ0
7
DQ1
20
DQ2
21
DQ3
4
DQ4
3
DQ5
16
DQ6
17
DQ7
13
DQS0(T)
11
DQS0#(C)
28
DQ8
29
DQ9
41
DQ10
42
DQ11
24
DQ12
25
DQ13
38
DQ14
37
DQ15
34
DQS1(T)
32
DQS1#(C)
50
DQ16
49
DQ17
62
DQ18
63
DQ19
46
DQ20
45
DQ21
58
DQ22
59
DQ23
55
DQS2(T)
53
DQS2#(C)
70
DQ24
71
DQ25
83
DQ26
84
DQ27
66
DQ28
67
DQ29
79
DQ30
80
DQ31
76
DQS3(T)
74
DQS3#(C)
174
DQ32
173
DQ33
187
DQ34
186
DQ35
170
DQ36
169
DQ37
183
DQ38
182
DQ39
179
DQS4(T)
177
DQS4#(C)
195
DQ40
194
DQ41
207
DQ42
208
DQ43
191
DQ44
190
DQ45
203
DQ46
204
DQ47
200
DQS5(T)
198
DQS5#(C)
216
DQ48
215
DQ49
228
DQ50
229
DQ51
211
DQ52
212
DQ53
224
DQ54
225
DQ55
221
DQS6(T)
219
DQS6#(C)
237
DQ56
236
DQ57
249
DQ58
250
DQ59
232
DQ60
233
DQ61
245
DQ62
246
DQ63
242
DQS7(T)
240
DQS7#(C)
DDR4_DRAMRST#_PCH <18>DDR_DRAMRST#<24>
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DDR_A_D0
DDR_A_D1
DDR_A_D7
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D2
DDR_A_DQS0
DDR_A_DQS#0
DDR_A_D13
DDR_A_D8
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D9
DDR_A_D14
DDR_A_D15
DDR_A_DQS1
DDR_A_DQS#1
DDR_A_D37
DDR_A_D36
DDR_A_D39
DDR_A_D35
DDR_A_D32
DDR_A_D33
DDR_A_D38
DDR_A_D34
DDR_A_DQS4
DDR_A_DQS#4
DDR_A_D45
DDR_A_D40
DDR_A_D43
DDR_A_D46
DDR_A_D44
DDR_A_D41
DDR_A_D42
DDR_A_D47
DDR_A_DQS5
DDR_A_DQS#5
DDR_A_D20
DDR_A_D21
DDR_A_D19
DDR_A_D18
DDR_A_D16
DDR_A_D17
DDR_A_D22
DDR_A_D23
DDR_A_DQS2
DDR_A_DQS#2
DDR_A_D26
DDR_A_D24
DDR_A_D29
DDR_A_D27
DDR_A_D25
DDR_A_D30
DDR_A_D28
DDR_A_D31
DDR_A_DQS3
DDR_A_DQS#3
DDR_A_D54
DDR_A_D50
DDR_A_D52
DDR_A_D51
DDR_A_D49
DDR_A_D48
DDR_A_D53
DDR_A_D55
DDR_A_DQS6
DDR_A_DQS#6
DDR_A_D59
DDR_A_D57
DDR_A_D58
DDR_A_D63
DDR_A_D62
DDR_A_D60
DDR_A_D61
DDR_A_D56
DDR_A_DQS7
DDR_A_DQS#7
2018/01/01
2018/01/01
2018/01/01
+DDR_VREF_A_CA
DDR_VTT_CTRL<7>
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
+3.3V_RUN_DIMM1
+DDR_VREF_A_CA
+1.2V_MEM
+1.2V_MEM
1K_0402_1%
12
RD15
1K_0402_1%
12
RD16
UD1
NC1VCC
2
A
3
GND
74AUP1G07SE-7_SOT353
2020/01/01
2020/01/01
2020/01/01
CONN@
JDIMM1B
REVERSE
111
VDD1
112
VDD2
117
VDD3
118
VDD4
123
VDD5
124
VDD6
129
VDD7
130
VDD8
135
VDD9
136
VDD10
255
VDDSPD
164
VREFCA
1
VSS1
2
VSS2
5
VSS3
6
VSS4
9
VSS5
10
VSS6
14
VSS7
15
VSS8
18
VSS9
19
VSS10
22
VSS11
23
VSS12
26
VSS13
27
VSS14
30
VSS15
31
VSS16
35
VSS17
36
VSS18
39
VSS19
40
VSS20
43
VSS21
44
VSS22
47
VSS23
48
VSS24
51
VSS25
52
VSS26
56
VSS27
57
VSS28
60
VSS29
61
VSS30
64
VSS31
65
VSS32
68
VSS33
69
VSS34
72
VSS35
73
VSS36
77
VSS37
78
VSS38
81
VSS39
82
VSS40
85
VSS41
86
VSS42
89
VSS43
90
VSS44
93
VSS45
94
VSS46
98
VSS47
262
GND1
264
NPTH2
LOTES_ADDR0206-P001A
1 2
RD17 2_0402_1%
+3.3V_RUN
5
4
Y
+1.2V_MEM
141
VDD11
142
VDD12
147
VDD13
148
VDD14
153
VDD15
154
VDD16
159
VDD17
160
VDD18
163
VDD19
258
VTT
257
VPP1
259
VPP2
99
VSS48
102
VSS49
103
VSS50
106
VSS51
107
VSS52
167
VSS53
168
VSS54
171
VSS55
172
VSS56
175
VSS57
176
VSS58
180
VSS59
181
VSS60
184
VSS61
185
VSS62
188
VSS63
189
VSS64
192
VSS65
193
VSS66
196
VSS67
197
VSS68
201
VSS69
202
VSS70
205
VSS71
206
VSS72
209
VSS73
210
VSS74
213
VSS75
214
VSS76
217
VSS77
218
VSS78
222
VSS79
223
VSS80
226
VSS81
227
VSS82
230
VSS83
231
VSS84
234
VSS85
235
VSS86
238
VSS87
239
VSS88
243
VSS89
244
VSS90
247
VSS91
248
VSS92
251
VSS93
252
VSS94
261
GND2
263
NPTH1
+DDR_VREF_CA+DDR_VREF_A_CA
0.022U_0402_16V7K
CD31
1
2
24.9_0402_1%
12
RD18
330K_0402_5%
12
RD19
+1.2V_MEM
1 2
CD32 0.1U_0402_25V6@
0.6V_DDR_VTT_ON
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
DDR4-SODIMM SLOT1
DDR4-SODIMM SLOT1
DDR4-SODIMM SLOT1
Size
Size
Size
Document Number Re v
Document Number Re v
Document Number Re v
C
C
C
LA-H171P
LA-H171P
LA-H171P
Friday, March 08, 2019
Friday, March 08, 2019
Friday, March 08, 2019
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
+0.6V_DDR_VTT
+2.5V_MEM
0.6V_DDR_VTT_ON <86>
23 100
23 100
23 100
0.1
0.1
0.1
5
smd.db-x7.ru
DDR_B_DQS#[0..7]<8>
DDR_B_DQS[0..7]<8>
DDR_B_D[0..15]<8>
DDR_B_D[16..31]<8>
DDR_B_D[32..47]<8>
DDR_B_D[48..63]<8>
DDR_B_MA[0..16]<8>
Layout Note:
Place near JDIMM2
D D
+1.2V_MEM
330U_D3_2.5VY_R6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
CD33
CD34
CD35
CD37
1
1
2
2
1U_0201_10V6M
1U_0201_10V6M
CD41
1
1
2
2
C C
Layout Note:
Place near
JDIMM2.258
+0.6V_DDR_VTT
10U_0603_6.3V6M
1U_0201_10V6M
CD54
1
1
2
2
FOLLOW PDG V1P8 P.136
2x 10μ F (0603)
4x 1μ F (0402),INTEL reply can downsize to 0201
B B
CD36
1
2
1U_0201_10V6M
CD43
CD42
1
2
1U_0201_10V6M
CD56
CD55
1
2
1
1
1
2
2
2
1U_0201_10V6M
1U_0201_10V6M
CD44
CD45
1
1
1
2
2
2
FOLLOW PDG V1P8 P.136
VDDQ 16x 10μ F (0603)
VDDQ 16x 1μ F (0402),INTEL reply can downsize to 0201
VPP 2x 10μ F (0603)
VPP 2x 1μ F (0402),INTEL reply can downsize to 0201
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1
@
CD40
CD38
1
2
1U_0201_10V6M
1U_0201_10V6M
CD46
1
2
CD49
CD39
1
+
2
2
+2.5V_MEM
CD48
+DDR_VREF_B_CA
1U_0201_10V6M
10U_0603_6.3V6M
1U_0201_10V6M
CD50
CD51
1
2
0.1U_0201_6.3V6K
CD57
1
2
1
1
1
CD52
2
2
2
2.2U_0402_6.3V6M
@
CD58
1
2
1U_0201_10V6M
CD47
1
2
4
3
2
1
Link LOTES_ADDR0206-P001A02 done 0718
CONN@
JDIMM2A
DDR_B_CLK0<8>
DDR_B_CLK#0<8>
DDR_B_CLK1<8>
DDR_B_CLK#1<8>
DDR_B_CKE0<8>
DDR_B_CKE1<8>
DDR_B_CS#0<8>
DDR_B_CS#1<8>
DDR_B_ODT0<8>
DDR_B_ODT1<8>
DDR_B_BG0<8>
DDR_B_BG1<8>
DDR_B_BA0<8>
DDR_B_BA1<8>
10U_0603_6.3V6M
CD53
DDR_DRAMRST#<23>
0.1U_0402_25V6
1
CD61
@
2
DDR_B_ACT#<8>
DDR_B_PAR<8>
DDR_B_ALERT#<8>
DDR_XDP_WAN_SMBDAT<7,18,23,67>
DDR_XDP_WAN_SMBCLK<7,18,23,67>
+1.2V_MEM
DDR_B_CLK0
DDR_B_CLK#0
DDR_B_CLK1
DDR_B_CLK#1
DDR_B_CKE0
DDR_B_CKE1
DDR_B_CS#0
DDR_B_CS#1
T52PAD~D @
T53PAD~D @
DDR_B_ODT0
DDR_B_ODT1
DDR_B_BG0
DDR_B_BG1
DDR_B_BA0
DDR_B_BA1
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15
DDR_B_MA16
DDR_B_ACT#
DDR_B_PAR
DDR_B_ALERT#
JDIMM2_EVENT#
DDR_DRAMRST#
DIMM2_SA2
DIMM2_SA1
DIMM2_SA0
1
1
REVERSE
137
CK0(T)
139
CK0#(C)
138
CK1(T)
140
CK1#(C)
109
CKE0
110
CKE1
149
S0#
157
S1#
162
S2#/C0
165
S3#/C1
155
ODT0
161
ODT1
115
BG0
113
BG1
150
BA0
145
BA1
144
A0
133
A1
132
A2
131
A3
128
A4
126
A5
127
A6
122
A7
125
A8
121
A9
146
A10_AP
120
A11
119
A12
158
A13
151
A14_WE#
156
A15_CAS#
152
A16_RAS#
114
ACT#
143
PARITY
116
ALERT#
134
EVENT#
108
RESET#
254
SDA
253
SCL
166
SA2
260
SA1
256
SA0
92
CB0_NC
91
CB1_NC
101
CB2_NC
105
CB3_NC
88
CB4_NC
87
CB5_NC
100
CB6_NC
104
CB7_NC
97
DQS8(T)
95
DQS8#(C)
12
DM0#/DBI0#
33
DM1#/DBI1#
54
DM2#/DBI2#
75
DM3#/DBI3#
178
DM4#/DBI4#
199
DM5#/DBI5#
220
DM6#/DBI6#
241
DM7#/DBI7#
96
DM8#/DBI8#
LOTES_ADDR0206-P001A
DQS0(T)
DQS0#(C)
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS1(T)
DQS1#(C)
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS2(T)
DQS2#(C)
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQS3(T)
DQS3#(C)
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS4(T)
DQS4#(C)
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQS5(T)
DQS5#(C)
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQS6(T)
DQS6#(C)
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQS7(T)
DQS7#(C)
8
DQ0
7
DQ1
20
DQ2
21
DQ3
4
DQ4
3
DQ5
16
DQ6
17
DQ7
13
11
28
DQ8
29
DQ9
41
42
24
25
38
37
34
32
50
49
62
63
46
45
58
59
55
53
70
71
83
84
66
67
79
80
76
74
174
173
187
186
170
169
183
182
179
177
195
194
207
208
191
190
203
204
200
198
216
215
228
229
211
212
224
225
221
219
237
236
249
250
232
233
245
246
242
240
DDR_B_D5
DDR_B_D4
DDR_B_D6
DDR_B_D7
DDR_B_D1
DDR_B_D0
DDR_B_D2
DDR_B_D3
DDR_B_DQS0
DDR_B_DQS#0
DDR_B_D13
DDR_B_D9
DDR_B_D10
DDR_B_D15
DDR_B_D8
DDR_B_D12
DDR_B_D14
DDR_B_D11
DDR_B_DQS1
DDR_B_DQS#1
DDR_B_D34
DDR_B_D32
DDR_B_D39
DDR_B_D37
DDR_B_D36
DDR_B_D38
DDR_B_D33
DDR_B_D35
DDR_B_DQS4
DDR_B_DQS#4
DDR_B_D41
DDR_B_D44
DDR_B_D42
DDR_B_D47
DDR_B_D45
DDR_B_D40
DDR_B_D46
DDR_B_D43
DDR_B_DQS5
DDR_B_DQS#5
DDR_B_D18
DDR_B_D23
DDR_B_D16
DDR_B_D20
DDR_B_D19
DDR_B_D22
DDR_B_D17
DDR_B_D21
DDR_B_DQS2
DDR_B_DQS#2
DDR_B_D25
DDR_B_D29
DDR_B_D27
DDR_B_D30
DDR_B_D24
DDR_B_D28
DDR_B_D26
DDR_B_D31
DDR_B_DQS3
DDR_B_DQS#3
DDR_B_D48
DDR_B_D54
DDR_B_D50
DDR_B_D49
DDR_B_D51
DDR_B_D52
DDR_B_D55
DDR_B_D53
DDR_B_DQS6
DDR_B_DQS#6
DDR_B_D59
DDR_B_D57
DDR_B_D56
DDR_B_D58
DDR_B_D61
DDR_B_D62
DDR_B_D60
DDR_B_D63
DDR_B_DQS7
DDR_B_DQS#7
+DDR_VREF_B_CA
+3.3V_RUN_DIMM2
+DDR_VREF_B_CA
CONN@
JDIMM2B
REVERSE
111
VDD1
112
VDD2
117
VDD3
118
VDD4
123
VDD5
124
VDD6
129
VDD7
130
VDD8
135
VDD9
136
VDD10
255
VDDSPD
164
VREFCA
1
VSS1
2
VSS2
5
VSS3
6
VSS4
9
VSS5
10
VSS6
14
VSS7
15
VSS8
18
VSS9
19
VSS10
22
VSS11
23
VSS12
26
VSS13
27
VSS14
30
VSS15
31
VSS16
35
VSS17
36
VSS18
39
VSS19
40
VSS20
43
VSS21
44
VSS22
47
VSS23
48
VSS24
51
VSS25
52
VSS26
56
VSS27
57
VSS28
60
VSS29
61
VSS30
64
VSS31
65
VSS32
68
VSS33
69
VSS34
72
VSS35
73
VSS36
77
VSS37
78
VSS38
81
VSS39
82
VSS40
85
VSS41
86
VSS42
89
VSS43
90
VSS44
93
VSS45
94
VSS46
98
VSS47
262
GND1
264
NPTH2
LOTES_ADDR0206-P001A
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDD19
VPP1
VPP2
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
GND2
NPTH1
+1.2V_MEM+1.2V_MEM
141
142
147
148
153
154
159
160
163
258
VTT
257
259
99
102
103
106
107
167
168
171
172
175
176
180
181
184
185
188
189
192
193
196
197
201
202
205
206
209
210
213
214
217
218
222
223
226
227
230
231
234
235
238
239
243
244
247
248
251
252
261
263
+0.6V_DDR_VTT
+2.5V_MEM
DIMM Select
SA01SA1
0
DIMM1
DIMM2
DIMM3
*
DIMM4
Byte[0]
Byte[1]
Byte[2]
A A
Byte[3]
*
Byte[4]
Byte[5]
*
Byte[6]
Byte[7]
0
0
1
0
1
1
DQ[7:0]
DQ[15:8]
DQ[23:16]
DQ[31:24]
DQ[39:32]
DQ[47:40]
DQ[55:48]
DQ[63:56]
SA2
0
0
0
0
DQS/DQS#[0]
DQS/DQS#[1]
DQS/DQS#[2]
DQS/DQS#[3]
DQS/DQS#[4]
DQS/DQS#[5]
DQS/DQS#[6]
DQS/DQS#[7]
5
12
12
RD20
@
0_0402_5%
@
0_0402_5%
12
RD22
@
0_0402_5%
12
RD23
@
RD21
0_0402_5%
+3.3V_RUN+3.3V_RUN+3.3V_RUN +3.3V_RUN
12
RD24
@
0_0402_5%
DIMM2_SA0
DIMM2_SA1
DIMM2_SA2
12
RD25
@
0_0402_5%
12
1
2
@
0_0603_5%
2.2U_0402_6.3V6M
CD59
RD26
+3.3V_RUN_DIMM2
0.1U_0201_10V6K
1
CD60
2
+1.2V_MEM
1K_0402_1%
12
RD28
1 2
RD30 2_0402_1%
1K_0402_1%
JDIMM2_EVENT#
4
RD27 1K_0402_5%@
1 2
3
H_THERMTRIP# <7,14,23,59>
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2018/01/01
2018/01/01
2018/01/01
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
12
RD29
2020/01/01
2020/01/01
2020/01/01
+DDR_VREF_B_DQ+DDR_VREF_B_CA
0.022U_0402_16V7K
CD62
1
2
24.9_0402_1%
12
RD31
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
DDR4-SODIMM SLOT2
DDR4-SODIMM SLOT2
DDR4-SODIMM SLOT2
Size
Size
Size
Document Number Re v
Document Number Re v
Document Number Re v
C
C
C
LA-H171P
LA-H171P
LA-H171P
Friday, March 08, 2019
Friday, March 08, 2019
Friday, March 08, 2019
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
24 100
24 100
24 100
0.1
0.1
0.1
5
smd.db-x7.ru
D D
C C
4
3
2
1
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size
Size
Size
Date : Sheet o f
Date : Sheet o f
Date : Sheet o f
Compal Electronics, Inc.
DDR_2
DDR_2
Document Number Re v
Document Number Re v
Document Number Re v
DDR_2
LA-H171P
LA-H171P
LA-H171P
25 100Friday, March 08, 2019
25 100Friday, March 08, 2019
25 100Friday, March 08, 2019
1
0.1
0.1
0.1
5
smd.db-x7.ru
D D
C C
4
3
2
1
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size
Size
Size
Date : Sheet o f
Date : Sheet o f
Date : Sheet o f
Compal Electronics, Inc.
DDR_3
DDR_3
Document Number Re v
Document Number Re v
Document Number Re v
DDR_3
LA-H171P
LA-H171P
LA-H171P
26 100Friday, March 08, 2019
26 100Friday, March 08, 2019
26 100Friday, March 08, 2019
1
0.1
0.1
0.1
5
smd.db-x7.ru
D D
C C
4
3
2
1
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size
Size
Size
Date : Sheet o f
Date : Sheet o f
Date : Sheet o f
Compal Electronics, Inc.
Reserve GPU
Reserve GPU
Reserve GPU
Document Number Re v
Document Number Re v
Document Number Re v
LA-H171P
LA-H171P
LA-H171P
27 100Friday, March 08, 2019
27 100Friday, March 08, 2019
27 100Friday, March 08, 2019
1
0.1
0.1
0.1
5
smd.db-x7.ru
D D
C C
4
3
2
1
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size
Size
Size
Date : Sheet o f
Date : Sheet o f
Date : Sheet o f
Compal Electronics, Inc.
Reserve GPU
Reserve GPU
Document Number Re v
Document Number Re v
Document Number Re v
Reserve GPU
LA-H171P
LA-H171P
LA-H171P
1
28 100Friday, March 08, 2019
28 100Friday, March 08, 2019
28 100Friday, March 08, 2019
0.1
0.1
0.1
5
smd.db-x7.ru
D D
C C
4
3
2
1
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size
Size
Size
Date : Sheet o f
Date : Sheet o f
Date : Sheet o f
Compal Electronics, Inc.
Reserve GPU
Reserve GPU
Document Number Re v
Document Number Re v
Document Number Re v
Reserve GPU
LA-H171P
LA-H171P
LA-H171P
1
29 100Friday, March 08, 2019
29 100Friday, March 08, 2019
29 100Friday, March 08, 2019
0.1
0.1
0.1
5
smd.db-x7.ru
D D
C C
4
3
2
1
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size
Size
Size
Date : Sheet o f
Date : Sheet o f
Date : Sheet o f
Compal Electronics, Inc.
Reserve GPU
Reserve GPU
Document Number Re v
Document Number Re v
Document Number Re v
Reserve GPU
LA-H171P
LA-H171P
LA-H171P
1
30 100Friday, March 08, 2019
30 100Friday, March 08, 2019
30 100Friday, March 08, 2019
0.1
0.1
0.1
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