Compal LA-H131P Schematic
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LA-H131P
2018-11-05
Rev : 0.4
Compal Confidential
EL432/EL532
M/B Schematic Documents
AMD Picasso FP5 APU with DDR4
Title
Document Number
Date: of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPART MENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NO R THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C D
Issued Date
Deciphered Date
LA-H131P
R e v
0.4
Cover Page
Size
B
1 46Monday,November 05, 2018 Sheet
E
2018/11/05 2019/11/05
Compal Electronics, Inc.
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AMD Picasso Ridge
1140pin BGA
eDP x2 HBR 2.7Gb/s
eDP Panel
FHD LCD
HDA
I2C
SPI
TouchPad
SPI ROM
8MB
PCIe x1 , Gen1 2.5Gb/s
Card
Reader
Realtek
RTS5232S
SDIO
SD Card Conn.
On Sub Board
CH-A DDR4-SO-DIMM X1
CH-B on board RAM x4
DDR4 2400MHz
USB3.0 Conn.
USB2.0 x1, 480Mb/s
SPK
DMIC
HP
Int. Array Mic *2
Int. Speaker
Combo Jack
FingerPrint
USB2.0 x1, 480Mb/s
USB2.0 Hub
USB3.1 x1, Gen1 5Gb/s
On Sub Board
USB3 redriver
Parade PS8713B
USB3.1 x1, 5Gb/s
NGFF (Key M)
PCIE/SATA SSD
2242/2280 conn.
PCIe x3 , Gen3 8Gb/s
DDI x4 , 2.97GT/s
LPC
Int. KBD
KBC
ENE KB9022
Hall Sensor x1
LED
Int. Camera
Touch Panel
USB2.0 x1, 480Mb/s
USB3.0 Conn.
with AOU
HDMI Conn.
HDMI1.4b
Audio Codec
Realtek
ALC3287-CG
Type-C Conn.
USB3.1 Gen1
MUX/CC
Realtek RTS5448
VBus
5V Switch
USB2.0 x1,480Mb/s
USB3.1x1, Gen1
CC/Vconn
USB3.1x1, Gen1
NGFF (Key E)
WLAN/BT5.0
2230 conn.
USB2.0 x1, 480Mb/s
PCIe x1 , Gen1 2.5Gb/s
PCIe/SATA Mux
Pericom PI3DBS12212A
PCIe x1 , Gen3 8Gb/s
SATA x1 , Gen3 6Gb/s
HDD Conn.
SATA x1 , Gen3 6Gb/s
USB3.1 x1, Gen1 5Gb/s
USB3 redriver
Parade PS8713B
USB3.1 x1, 5Gb/s
USB2.0 x1, 480Mb/s
TI SN1702001RTER
USB2.0 x1, 480Mb/s
USB Charger
Reserve
Tiiitttllle
Siiize DocumentttNumberrr
LA-H1 31P
Rev
0...4
Cover Page
D
Sheettt 2 o fff46Dattte::: Monday,,, Novemberrr 05,,,2018
Securrriiittty Clllassiiifffiiicatttiiion
Compalll Secrettt Dattta
IsII sued Datett
2018///11///05
Decipheii rrredDatett
2019/1// 1/0// 5
THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THEPROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL AND TRADE
SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIION OF R&D DEPARTMENT EXCEPT AS
AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IIINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIIT CONTAIIINS
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,,IIINC...
Compal Electronics, Inc.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
RTC_CLK RTC_CLK
T2 : 15ms~26ms
VCIN1_AC_IN
EC_ON
+3VLP
+5VALW
+3VALW
Boot
3V/5VALW_PG
+1.8VALW
+0.8VALW
AC Plug
ON/OFF#
EC_RSMRST#
PBTN_OUT#
PM_SLP_S5#
PM_SLP_S3#
SYSON
+1.2V_DDR
+2.5V_MEM
SUSP#
0.8VS_PWR_EN
+5VS
+3VS
+1.8VS
+0.8VS
+0.6VS
VR_ON
+APU_CORE
+APU_CORE_SOC
VGATE
PCH_PWROK
APU_PWRGD
PCIRST#
APU_RST#
CLK_PCIE
Power Sequence
EC Pin 110 Intput
EC Pin 112 Output
EC Pin 114 Intput
EC Pin 100 Output
EC Pin 122 Output
EC Pin 123 Intput
EC Pin 6 Intput
EC Pin 95 Output
EC Pin 116 Output
EC Pin 99 Output
EC Pin 121 Output
EC Pin 36 Intput
EC Pin 32 Output
PLT_RST#
EC Pin 13 Intput
Shut
Down
VCIN1_AC_IN
EC_ON
+3VLP
+5VALW
+3VALW
3V/5VALW_PG
+1.8VALW
+0.8VALW
ON/OFF#
EC_RSMRST#
PBTN_OUT#
PM_SLP_S5#
PM_SLP_S3#
SYSON
+1.2V_DDR
+2.5V_MEM
SUSP#
0.8VS_PWR_EN
+5VS
+3VS
+1.8VS
+0.8VS
+0.6VS
VR_ON
+APU_CORE
+APU_CORE_SOC
VGATE
PCH_PWROK
APU_PWRGD
PCIRST#
APU_RST#
CLK_PCIE
PLT_RST#
T1_Min : 10ms
T3 : 30us~64us
T5_Min : 1ms
T8 : 15ms~17ms
T9 : 12ms~14.6ms
Tiiitttllle
offf
Securiiity Clllassiiifiiicatiiion
Compal SecretData
THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL AND
TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIION OF R&D DEPARTMENT
EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IIINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIIT CONTAIIINS
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IIINC...
Issued Date
Decipherii ed Date
LA-H131P
Rev
0...4
Power Sequence
Siiize Documenttt Number C
Sheettt 4 46Dattte::: Monday,,, November 05,,, 2018
2018/11/05 2019/11/05
Compal Electronics,Inc.
A
A
B
B
C
C
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APU SM Bus address
EC SM Bus1 address EC SM Bus2 address
Voltage Rails
SIGNAL
STATE
SLP_S3#
SLP_S5#
+VALW +V +VS Clock
Full ON HIGH HIGH ON ON ON ON
S3 (Suspend to RAM) HIGH HIGH ON ON OFF OFF
S4 (Suspend to Disk) LOW HIGH ON OFF OFF OFF
S5 (Soft OFF) LOW LOW ON OFF OFF OFF
SMBUS Control Table
SOURCE
APU BATT EC S ODIMM WLAN
EC_SMB_CK1
EC_SMB_DA1
9022
+3VALW
X V
+3VALW
V
+3VALW
X X
APU_SCLK0
APU_SDATA0
APU
+3VS
X X X V
+3VS
X
EC_SMB_CK2
EC_SMB_DA2
9022
+3VS
V
+1.8VS
X V
+3VALW
X X
BOM STRUCTURE
USB2.0 Port
APU I2C Bus address
Device Address
I2C 3
Touch Pad (Synaptics ) $2C
Touch Pad (Elan)
0X15
Display Port
PORT FUNCTION
0
eDP
1
HDMI
USB3.0 Port (USB_0)
GPP Port
PORT FUNCTION
GPP0
SSD (PCIe x4)
GPP1
GPP2
GPP3
GPP4
Card Reader (PCIe x1)
GPP5
WLAN (PCIe x1)
GPP6
SSD (SATA x1)
GPP7
HDD (SATAx1)
Device
Smart Battery
Charger
Address
0001 011x b
0001 0010 b
HEX
16H
12H
Device Address HEX
SM Bus0
DDR DIMM1
1010 001Xb A2H
Device
APU
Address
1001 100X b
HEX
98H
Power Plane Description S0 S3 S5
VIN Adapter power supply
ON ON ON
B+
AC or battery power rail for power circuit.
ON ON ON
+APU_ CORE
Core voltage for APU
ON
OFF OFF
+APU _CO RE_SOC
Core voltage for APU
ON
OFF OFF
+RT C_APU
RTC power
ON ON ON
+3VALW 3.3V always on powerrail
ON ON ON
+3VS 3.3V switched power rail
ON
OFF OFF
+1.8VALW 1.8V always on powerrail
ON ON ON
+1.8VS 1.8V switched powerrail
ON
OFF OFF
+0.8VALW 0.95V always on power rail
ON ON ON
+0.8VS 0.95V switched power rail
ON
OFF OFF
+1.2V_DDR 1.2V power rail for APU and DDR
ON ON
OFF
+2.5V_MEM 2.5V power rail for DDR
ON ON
OFF
+0.6VS_VTT 0.6V switched power rail for DDRterminator
ON
OFF OFF
+5VALW 5V always on power rail
ON ON ON
+5VS 5V switched power rail
ON
OFF OFF
CARD READER (SUB BOARD)
*Main Source - Realtek
*Substitute - Genesys
PCB
CPU
PORT FUNCT ION
0
Type-C
1
Sub/B USB3.0 Type-A
2
Sub/B USB3.0 Type-A
3
Camera
4
USB2.0 Hub
5
Bluetooth
PORT FUNCT ION
1
Touch Screen
2
Finger Printer
USB2.0 Hub
PORT FUNCT ION
0
Type-C
1
Sub/B USB3.0 Type-A
2
Sub/B USB3.0 Type-A
3
4
BOM STRUCTURE D ESC RIP TIO N
14@
14" Only Components
15@
15" Only Components
OBR@
On Board RAM SKU Only
NO_OBR@
No On Board RAM SKU Only
SDP@
Memory Down - SDP Package
DDP@
Memory Down - DDP Package
SINGLE_MIC@
MIC Select Strap (1 MIC)
MULTI_MIC@
MIC Select Strap (2 MIC)
KBL@
Keyboard Backlight
TYPE2TYPE1
BOM STRUCTURE D ESCRIPTION
Ryzen5_PR@
Ryzen5 CPU (PR Sample)
Ryzen7_PR@
Ryzen7 CPU (PR Sample)
45@
HDMI Logo
14_DAZ_R0@
14" DAZ (Rev0 PCB)
15_DAZ_R0@
15" DAZ (Rev0 PCB)
X4E@
43J X4E Level
X76RAM@
On Board RAM X76 Resistors
S4G_MD@
On Board RAM (Samsung 4GB)
H4G_MD@
On Board RAM (Hynix 4GB)
M4G_MD@
On Board RAM (Micron 4GB)
HDT@
HDT Debugging
EMI@
EMI Components
ESD@
ESD Components
RF@
RF Components
TS@
Touch Screen
BOM STRUCTURE D ESCRIP TIO N
Ryzen3_PC@
Ryzen3 CPU (PC Sample)
Ryzen3_PR@
Ryzen3 CPU (PR Sample)
Ryzen5_PC@
Ryzen5 CPU (PC Sample)
Ryzen7_ES@
Ryzen7 CPU (ES Sample)
Ryzen7_PC@
Ryzen7 CPU (PC Sample)
@
Un-Mount Components
@EMI@
EMI Un-Mount Components
@ESD@
ESD Un-Mount Components
20V_PRTCT@
5448 EXT Voltage Protection
FP@
Finger Printer (Reserved)
ME@
ME Components
EX_THM@
Thermal Sensor
HUB@
USB2.0 HUB
DA_R0@
PCB Part Number (Rev0 PCB)
DA_R1@
PCB Part Number (Rev1 PCB)
14_DAZ_R1@
14" DAZ (Rev1 PCB)
15_DAZ_R1@
15" DAZ (Rev1 PCB)
RD@
USB3.0 Re-Driver BOM
TI@
TI Re-Driver Only
PARADE@
Parade Re-Driver Only
PERICOM@
Pericom Re-Driver Only
X76_TI@
TI Re-Driver X76 Level
X76_PARADE@
Parade Re-Driver X76 Level
X76_PERICOM@
Pericom Re-Driver X76 Level
Tiiitttllle
Sheettt
Securiiity Clllassiiifiiicatiiion
Compal SecretData
THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL AND
TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIION OF R&D DEPARTMENT
EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IIINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIIT CONTAIIINS
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IIINC...
Issued Date
Decipherii ed Date
LA-H131P
Rev
0...4
NOTES LIST
Siiize Documenttt Number C
3 offf 46Dattte::: Monday,,, November 05,,, 2018
2018/11/05 2019/11/05
Compal Electronics,Inc.
UC1 Ryzen7_ES@
S IC RYZEN7 2M370SC4T4MFB 2.2G ES APU
SA0000C7610
UC1 Ryzen5_PR@
S IC RYZEN5 YM3500C4T4MFG 2G BGA1140 APU
SA0000CCR20
UC1 Ryzen7_PR@
S IC RYZEN7 YM3700C4T4MFG 2.2G BGA APU
SA0000C7640
X4E EMC
X4EAF938L01
X4E
ZZZ X4E@
ZZZS4G_MD@
UC1 Ryzen7_PC@
S IC RYZEN7 ZM370SC4T4MFG 2.2G QS APU
SA0000C7620
ZZZ DA_R1@
Rev1 PCB
DA60023G010
ZZZ 14_DAZ_R0@
Rev0 DAZ_14
DAZ2GH00100
ZZZ DA_R0@
Rev0 PCB
DA60023G000
UC1 Ryzen3_PC@
S IC RYZEN3 ZM320SC4T2OFG 2.5G QS APU
SA0000CCS00
UC1 Ryzen3_PR@
S IC RYZEN3 YM3200C4T2OFG 2.5G BGA 1140 APU
SA0000CCS20
X76 HYNIX 4GB MD X76 MICRON 4GB MD X76 SAMSUNG 4GB MD
X7680438L51 X7680438L52 X7680438L53
ON BOARD RAM * 4
ZZZ H4G_MD@ ZZZM4G_MD@
ZZZ 14_DAZ_R1@
Rev1 DAZ_14
DAZ2GH00101
HDMI Logo
RO0000003HM
HDMI Logo
ZZZ 45@
ZZZ 15_DAZ_R0@
Rev0 DAZ_15
DAZ2GD00100
UC1 Ryzen5_PC@
S IC RYZEN5 ZM350SC4T4MFG 2G QS BGA APU
SA0000CCR00
ZZZ 15_DAZ_R1@
Rev1 DAZ_15
DAZ2GD00101
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
EVENT# pull high
Main Func = CPU
ESD
DDR _B_M A12
DDR _B_M A13
DDR _B_M A11
DDR _B_M A10
DDR_B_MA 6
DDR_B_MA 7
DDR_B_MA 2
DDR_B_MA 3
DDR_B_MA 8
DDR_B_MA 5
DDR_B_MA 4
DDR_B_MA 9
DDR_B_MA 0
DDR_B_MA 1
DDR_B_ DM6
DDR_B_ DM3
DDR_B_ DM5
DDR_B_ DM4
DDR_B_ DM2
DDR_B_ DM7
DDR_B_ DM0
DDR_B_ DM1
DDR _B_DQ 60
DDR _B_DQ 19
DDR _B_DQ 13
DDR _B_DQ 28
DDR _B_DQ 29
DDR _B_DQ 61
DDR _B_DQ 59
DDR _B_DQ 34
DDR _B_DQ 36
DDR_B_ DQ4
DDR_B_ DQ3
DDR _B_DQ 47
DDR _B_DQ 43
DDR _B_DQ 39
DDR _B_DQ 46
DDR _B_DQ 15
DDR _B_DQ 54
DDR_B_ DQ5
DDR_B_ DQ6
DDR _B_DQ 53
DDR_B_ DQ8
DDR_B_ DQ9
DDR _B_DQ 50
DDR _B_DQ 12
DDR _B_DQ 31
DDR _B_DQ 63
DDR _B_DQ 62
DDR _B_DQ 42
DDR _B_DQ 26
DDR _B_DQ 51
DDR_B_ DQ24
DDR_B_ DQ25
DDR_B_ DQ32
DDR_B_ DQ33
DDR_B_ DQ0
DDR_B_ DQ1
DDR _B_DQ 44
DDR_B_ DQ7
DDR _B_DQ 55
DDR_B_ DQ2
DDR _B_DQ 38
DDR _B_DQ 27
DDR _B_DQ 58
DDR _B_DQ 10
DDR _B_DQ 14
DDR_B_ DQ48
DDR_B_ DQ49
DDR _B_DQ 30
DDR _B_DQ 11
DDR _B_DQ 35
DDR _B_DQ 37
DDR _B_DQ 52
DDR _B_DQ 45
DDR_B_ DQ40
DDR_B_ DQ41
DDR_B_ DQ56
DDR_B_ DQ57
DDR _B_DQ 20
DDR _B_DQ 22
DDR _B_DQ 21
DDR _B_DQ 23
DDR_B_ DQ16
DDR_B_ DQ17
DDR _B_DQ 18
DDR _A_M A12
DDR _A_M A13
DDR _A_M A11
DDR _A_M A10
DDR_A_MA 6
DDR_A_MA 7
DDR_A_MA 2
DDR_A_MA 3
DDR_A_MA 8
DDR_A_MA 5
DDR_A_MA 4
DDR_A_MA 9
DDR_A_MA 0
DDR_A_MA 1
DDR_A_ DM6
DDR_A_ DM3
DDR_A_ DM5
DDR_A_ DM4
DDR_A_ DM2
DDR_A_ DM7
DDR_A_ DM0
DDR_A_ DM1
DDR _A_DQ 60
DDR _A_DQ 19
DDR _A_DQ 13
DDR _A_DQ 28
DDR _A_DQ 29
DDR _A_DQ 61
DDR _A_DQ 59
DDR _A_DQ 34
DDR _A_DQ 36
DDR_A_ DQ4
DDR_A_ DQ0
DDR_A_ DQ3
DDR _A_DQ 47
DDR _A_DQ 43
DDR _A_DQ 39
DDR _A_DQ 46
DDR _A_DQ 15
DDR _A_DQ 54
DDR_A_ DQ5
DDR_A_ DQ6
DDR _A_DQ 53
DDR_A_ DQ8
DDR_A_ DQ9
DDR _A_DQ 50
DDR _A_DQ 12
DDR _A_DQ 31
DDR _A_DQ 63
DDR _A_DQ 62
DDR _A_DQ 42
DDR _A_DQ 26
DDR _A_DQ 51
DDR_A_ DQ24
DDR_A_ DQ25
DDR_A_ DQ32
DDR_A_ DQ33
DDR_A_ DQ1
DDR _A_DQ 44
DDR_A_ DQ7
DDR _A_DQ 55
DDR_A_ DQ2
DDR _A_DQ 27
DDR _A_DQ 58
DDR _A_DQ 10
DDR _A_DQ 14
DDR_A_ DQ48
DDR_A_ DQ49
DDR _A_DQ 30
DDR _A_DQ 11
DDR _A_DQ 35
DDR _A_DQ 37
DDR _A_DQ 52
DDR _A_DQ 45
DDR_A_ DQ56
DDR_A_ DQ57
DDR _A_DQ 20
DDR _A_DQ 22
DDR _A_DQ 21
DDR _A_DQ 23
DDR_A_ DQ16
DDR_A_ DQ17
DDR _A_DQ 18
DDR_A_ BG0
DDR_A_ BG1
DDR_A_ ACT#
DDR_B_ BG0
DDR_B_ BG1
DDR_B_ ACT#
DDR_B_ EVENT#
DDR _A_P AR
DDR _B_P ARDDR_A_ EVENT#
DDR_B_ RST#
<13> DD R_B_ MA[1 3..0]
<13> DDR _B_B A0
<13> DDR _B_B A1
DDR _B_DQ [63. .0] < 13>
<12> DD R_A_ MA[1 3..0]
<12> DD R_A _CS0#
<12> DD R_A_ ODT0
<12> DD R_A _CKE0
<12> DDR _A_D QS0
<12> DD R_A_ DQS0#
<12> DDR _A_D QS1
<12> DD R_A_ DQS1#
<12> DDR _A_D QS2
<12> DD R_A_ DQS2#
<12> DDR _A_D QS3
<12> DD R_A_ DQS3#
<12> DDR _A_D QS4
<12> DD R_A_ DQS4#
<12> DDR _A_D QS5
<12> DD R_A_ DQS5#
<12> DDR _A_D QS6
<12> DD R_A_ DQS6#
<12> DDR _A_D QS7
<12> DD R_A_ DQS7#
<12> DDR _A_B A0
<12> DDR _A_B A1
<12> DDR _A_C LK0
<12> DDR _A_C LK0#
DDR _A_DQ [63. .0] < 12>
<12> DDR _A_B G0
<12> DDR _A_B G1
<12> D DR_A _ACT#
<12> D DR_A_DM [7..0]
<12> D DR_ A_W E#
<12> DDR _A_C AS#
<12> DDR _A_R AS#
<12> DD R_A_ RST#
<13> DDR _B_B G0
<13> DDR _B_B G1
<13> D DR_B _ACT#
<13> D DR_B_DM [7..0]
<13> DDR _B_D QS0
<13> DD R_B_ DQS0#
<13> DDR _B_D QS1
<13> DD R_B_ DQS1#
<13> DDR _B_D QS2
<13> DD R_B_ DQS2#
<13> DDR _B_D QS3
<13> DD R_B_ DQS3#
<13> DDR _B_D QS4
<13> DD R_B_ DQS4#
<13> DDR _B_D QS5
<13> DD R_B_ DQS5#
<13> DDR _B_D QS6
<13> DD R_B_ DQS6#
<13> DDR _B_D QS7
<13> DD R_B_ DQS7#
<13> DDR _B_C LK0
<13> DDR _B_C LK0#
<13> DDR _B_C LK1
<13> DDR _B_C LK1#
<13> DDR _B_C S0#
<13> DDR _B_C S1#
<13> DDR _B_C KE0
<13> DDR _B_C KE1
<13> DDR_ B_OD T0
<13> DDR_ B_OD T1
<13> D DR_ B_W E#
<13> DDR _B_C AS#
<13> DDR _B_R AS#
<13> DD R_B _EVEN T#
<13> D DR_B _RST#
<12> DD R_A_ ALER T#
<13> DD R_B_ ALER T#
DDR _A_P AR <12>
DDR _B_P AR <13>
+1.2 V
Tiiitttllle
Siiize DocumentttN umb er
Securiiity Clllassiiifiiicatiiion
Compal Secret Data
THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL AND
TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIION OF R&D
DEPARTMENT EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IIINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIIT CONTAIIINS
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IIINC...
Issued Date
Deciphii ered Date
LA-H131P
Re v
0...4
FP5 DDR4 MEMORY I/F
Custtt om
Sheettt 5 o fff46Dattte::: Monday,,, November 05,,, 2018
2018/11/05 2019/11/05
Compal Electronics, Inc.
FP5 REV 0.90
PART 1OF 13
MEMORY A
UC1A
FP5 _BGA 1140 ~D
@
Y24
MA_RE SET_ L
AE24
MA_E VENT_ L
AA25
MA_A LERT_ L
AG24
MA_OD T0
AJ22
MA_OD T1
Y23
MA_C KE0
Y26
MA_C KE1
AJ27
MA_C S_L1
AG21
MA_C S_L0
AE27
MA_C LK_L1
AD24
MA_C LK_L0
AE26
MA_C LK_H1
V23
RSVD _40
AD25
MA_C LK_H0
AW20
MA_D QS_L7
V24
RSVD _41
AV20
MA_D QS_H7
AT23
MA_D QS_L6
AU23
MA_D QS_H6
AN24
MA_D QS_H5
AN25
MA_D QS_L5
AM27
MA_D QS_L4
AM26
MA_D QS_H4
P21
MA_D QS_L3
N26
MA_D QS_L2
R21
MA_D QS_H3
N27
MA_D QS_H2
H26
MA_D QS_L1
H27
MA_D QS_H1
G22
MA_D QS_L0
F22
MA_D QS_H0
T27
RSVD _36
AT21
MA_ DM7
AW25
MA_ DM6
AN27
MA_ DM5
AL24
MA_ DM4
N23
MA_ DM3
N24
MA_ DM2
G27
MA_ DM1
F21
MA_ DM0
AA22
MA_A CT_L
AA21
MA_B G0
AA27
MA_B G1
AF27
MA_B ANK1
AF21
MA_B ANK0
AG26
MA_RA S_L_ ADD 16
AG23
MA_C AS_L_ ADD 15
AG27
MA_W E_L_ ADD1 4
AJ25
MA_A DD13_ BAN K2
AC23
MA_A DD12
AA24
MA_A DD11
AF22
MA_A DD10
AC21
MA_A DD9
AD22
MA_A DD8
AC27
MA_A DD7
AD21
MA_A DD6
AC26
MA_A DD5
AC24
MA_A DD4
AD27
MA_A DD2
AE21
MA_A DD3
AE23
MA_A DD1
AF25
MA_A DD0
MA_ PAR OUT
AF24
RSV D_34
T24
RSV D_35
T25
RSVD _51
W25
RSVD _52
W27
RSVD _27
R26
RSVD _28
R27
RSVD _43
V27
RSVD _42
V26
MA_D ATA63
AR20
MA_D ATA62
AT20
MA_D ATA61
AN22
MA_D ATA59
AN20
MA_D ATA60
AR22
MA_D ATA58
AP21
MA_D ATA57
AU21
MA_D ATA56
AW21
MA_D ATA55
AT22
MA_D ATA54
AW23
MA_D ATA53
AV27
MA_D ATA52
AU26
MA_D ATA50
AV22
MA_D ATA51
AW22
MA_D ATA49
AV25
MA_D ATA48
AW26
MA_D ATA46
AP24
MA_D ATA47
AP23
MA_D ATA45
AL21
MA_D ATA44
AL22
MA_D ATA43
AU27
MA_D ATA42
AR25
MA_D ATA41
AM21
DDR _A_DQ 41
MA_D ATA40
AM23
DDR _A_DQ 40
MA_D ATA39
AP27
MA_D ATA38
AM24
DDR _A_DQ 38
MA_D ATA37
AK24
MA_D ATA36
AK26
MA_D ATA35
AR27
MA_D ATA34
AP26
MA_D ATA33
AL25
MA_D ATA32
AL27
MA_D ATA31
T21
MA_D ATA30
R23
MA_D ATA29
M20
MA_D ATA28
L21
MA_D ATA27
V21
MA_D ATA26
T22
MA_D ATA25
N21
MA_D ATA24
M22
MA_D ATA23
P25
MA_D ATA22
P24
MA_D ATA21
M24
MA_D ATA20
L27
MA_D ATA19
R24
MA_D ATA18
P27
MA_D ATA17
M27
MA_D ATA16
M25
MA_D ATA15
K27
MA_D ATA14
K25
MA_D ATA13
F25
MA_D ATA12
L23
MA_D ATA11
L26
MA_D ATA10
L24
MA_D ATA9
F26
MA_D ATA8
G25
MA_D ATA6
J22
MA_D ATA7
J23
MA_D ATA5
F20
MA_D ATA4
G20
MA_D ATA3
H23
MA_D ATA1
H21
MA_D ATA2
F23
MA_D ATA0
J21
CC97
100 P_04 02
1
2
@ES D@
_50 V8J
RC1 1
2 1K_ 0402 _5%
DDR _B_E VENT#
RC2 1 O BR@ 2 1K _04 02_5%
DDR _A_E VENT#
FP5 REV 0.90
PART 9OF 13
MEMORY B
UC1I
FP5 _BGA 1140 ~D
@
T31
MB_RE SET_ L
AG29
MB_E VENT_ L
AL29
MB1_O DT0
AM30
MB1_O DT1
W30
MB_A LERT_ L
AM32
MB0_O DT1
V32
MB1_C KE0
U31
MB1_C KE1
AL31
MB0_O DT0
T30
MB0_C KE1
U29
MB0_C KE0
AJ29
MB1_C S_L0
AM29
MB1_C S_L1
AM31
MB0_C S_L1
AJ31
MB0_C S_L0
AE30
MB_C LK_ H2
AE32
MB_C LK_ L2
AF29
MB_C LK_ H3
AF31
MB_C LK_L3
AD31
MB_C LK_L1
AD29
MB_C LK_H1
N31
RSVD _20
N29
RSVD _18
AC31
MB_C LK_H0
AD30
MB_C LK_L0
BC22
MB_D QS_H7
BA22
MB_D QS_L7
BA25
MB_D QS_L6
BC25
MB_D QS_H6
AW29
MB_D QS_L5
AR31
MB_D QS_L4
AW30
MB_D QS_H5
AR29
MB_D QS_H4
K29
MB_D QS_L3
K31
MB_D QS_H3
F29
MB_D QS_H2
F30
MB_D QS_L2
B25
MB_D QS_L1
D25
MB_D QS_H1
B22
MB_D QS_L0
D22
MB_D QS_H0
N32
RSVD _21
BD22
MB_ DM7
BB26
MB_ DM6
AW31
MB_ DM5
AP30
MB_ DM4
K30
MB_ DM3
E32
MB_ DM2
C25
MB_ DM1
C21
MB_ DM0
V30
MB_A CT_L
V29
MB_B G1
V31
MB_B G0
AG32
MB_B ANK1
AH31
MB_B ANK0
AJ30
MB_RA S_L_ ADD 16
AK32
MB_C AS_L_ ADD 15
AK30
MB_W E_L_ ADD1 4
AL30
MB_A DD13_ BAN K2
W31
MB_A DD12
Y32
MB_A DD11
AH29
MB_A DD10
W29
MB_A DD9
AA31
MB_A DD8
Y30
MB_A DD7
AA29
MB_A DD6
AA30
MB_A DD5
AB31
MB_A DD4
AB29
MB_A DD3
AC32
MB_A DD1
AC30
MB_A DD2
AG30
MB_A DD0
MB_ PAR OUT
AG31
RSV D_19
N30
RSV D_26
P31
RSV D_29
R32
RSV D_16
M30
RSV D_15
M29
RSV D_25
P30
RSVD _24
P29
RSVD _17
M31
MB_D ATA63
BA21
MB_D ATA62
BB21
MB_D ATA61
BA23
MB_D ATA60
BB23
MB_D ATA58
BC21
MB_D ATA59
BD20
MB_D ATA57
BB22
MB_D ATA56
BC23
MB_D ATA54
BB25
MB_D ATA55
BD25
MB_D ATA53
BB27
MB_D ATA52
BD28
MB_D ATA51
BC24
MB_D ATA49
BC27
MB_D ATA50
BA24
MB_D ATA48
BA27
MB_D ATA47
AY29
MB_D ATA45
AU31
MB_D ATA46
AY32
MB_D ATA44
AU30
MB_D ATA43
BA28
MB_D ATA42
BB30
MB_D ATA40
AU29
MB_D ATA41
AV30
MB_D ATA39
AT31
MB_D ATA38
AR30
MB_D ATA36
AN30
MB_D ATA37
AP31
MB_D ATA35
AU32
MB_D ATA34
AT29
MB_D ATA33
AP32
MB_D ATA32
AP29
MB_D ATA31
L32
MB_D ATA30
L30
MB_D ATA29
H32
MB_D ATA28
H30
MB_D ATA27
L31
MB_D ATA26
L29
MB_D ATA25
J31
MB_D ATA24
J29
MB_D ATA23
G30
MB_D ATA22
F31
MB_D ATA21
D28
MB_D ATA20
A28
MB_D ATA19
H31
MB_D ATA18
H29
MB_D ATA17
E29
MB_D ATA16
C30
MB_D ATA14
C26
MB_D ATA15
B27
MB_D ATA13
B24
MB_D ATA12
C23
MB_D ATA11
C27
MB_D ATA10
D27
MB_D ATA9
A25
MB_D ATA8
D24
MB_D ATA7
C22
MB_D ATA6
A22
MB_D ATA5
C20
MB_D ATA4
A20
MB_D ATA3
D23
MB_D ATA2
B23
MB_D ATA0
B21
MB_D ATA1
D21
5
5
4
4
3 2 1
1
D D
C C
B B
A A
Main Func = CPU
CardReader
WLAN
Main_SSD
Main_SSD
CardReader
WLAN
NGFF_SATA
SATA HDD
NGFF_SATA
SATA HDD
SATA_ARX_DTX_P0
SATA_ARX_DTX_N0
PCIE_ARX_DTX_P4
PCIE_ARX_DTX_N4
PCIE_ARX_DTX_P5
PCIE_ARX_DTX_N5
PCIE_ARX_DTX_P3
PCIE_ARX_DTX_N3
PCIE_ARX_DTX_P2
PCIE_ARX_DTX_N2
PCIE_ARX_DTX_P[0..3]
PCIE_ARX_DTX_N[0..3]
SATA_ATX_DRX_P0
SATA_ATX_DRX_N0
PCIE_ATX_C_DRX_P[0..3]
PCIE_ATX_C_DRX_N[0..3]
PCIE_ARX_DTX_P1
PCIE_ARX_DTX_N1
PCIE_ARX_DTX_P0
PCIE_ARX_DTX_N0
SATA_ARX_DTX_P1
SATA_ARX_DTX_N1
SATA_ATX_DRX_P1
SATA_ATX_DRX_N1
<17> PCIE_ARX_DTX_P[0..3]
<17> PCIE_ARX_DTX_N[0..3]
PCIE_ATX_C_DRX_P[0..3] <17>
PCIE_ATX_C_DRX_N[0..3] <17>
SATA_ATX_DRX_P0 <17>
SATA_ATX_DRX_N0 <17>
PCIE_ATX_C_DRX_P4 <20>
PCIE_ATX_C_DRX_N4 <20>
PCIE_ATX_C_DRX_P5 <16>
PCIE_ATX_C_DRX_N5 <16>
<20> PCIE_ARX_DTX_P4
<20> PCIE_ARX_DTX_N4
<16> PCIE_ARX_DTX_P5
<16> PCIE_ARX_DTX_N5
<17> SATA_ARX_DTX_P0
<17> SATA_ARX_DTX_N0
<19> SATA_ARX_DTX_P1
<19> SATA_ARX_DTX_N1
SATA_ATX_DRX_P1 <19>
SATA_ATX_DRX_N1 <19>
Title
Size
Document Number
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THEINFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3 2
Issued Date
Deciphered Date
LA-H131P
Rev
0.4
FP5 PCIE/UMI
Custom
6 46Monday, November 05, 2018
2018/11/05 2019/11/05
Compal Electronics, Inc.
2 0.1U_0201_10V6K
2 0.1U_0201_10V6K
FP5 REV 0.90
PART 2 OF 13
PCIE
FP5_BGA1140~D
UC1B @
R10
P_ GP P _R X N7/ S ATA _ RX N1
R9
P_ GP P _R XP 7/ S AT A_ RX P1
R7
P_ GP P _R XN 6/ SA TA _ RX N0
R6
P_ GP P _R XP 6/ S AT A_ RX P0
T9
P_ GP P _R X N5
T8
P_ GP P _R XP 5
V7
P_ GP P _R X N4
V6
P_ GP P _R XP 4
P11
P_ GP P _R X N3
P12
P_ GP P _R XP 3
M11
P_ GP P _R X N2
L12
P_ GP P _R XP 2
L9
P_ GP P _R X N1
L10
P_ GP P _R XP 1
N9
P_ GP P _R X N0
N10
P_ GP P _R XP 0
G8
P_ GF X _R XP 7
F8
P_ GF X _R XN 7
G6
P_ GF X _R XP 6
F7
P_ GF X _R XN 6
H6
P_ GF X _R XP 5
H7
P_ GF X _R XN 5
K11
P_ GF X _R XP 4
J11
P_ GF X _R XN 4
L6
P_ GF X _R XP 3
L7
P_ GF X _R XN 3
M8
P_ GF X _R XP 2
M9
P_ GF X _R XN 2
N6
P_ GF X _R XP 1
N7
P_ GF X _R XN 1
P9
P_ GF X _R XN 0
P8
P_ GF X _R XP 0
P_ GPP _T XN 7/S AT A_ TX N1
U4
P_ GPP _T XP 7/ SA TA_ TX P1
U2
P_ GPP _T XN 6/S AT A_ TX N0
V3
P_ GPP _T XP 6/ SA TA_ TX P0
V1
P_ GP P _T XP
P_ GP P _T XN 5
V2
5
W3
PCIE_ATX_DRX_P5
CC11 1
P_ GPP_TX N
4
W4
PCIE_ATX_DRX_N4
CC10 1
P_ GP P _T XP 4
W2
PCIE_ATX_DRX_P4
CC9 1
P_ GP P _T XP 3
T4
P_ GP P _T XN 3
T2
P_ GP P _T XP 2
R3
P_ GP P _T XN 2
R1
P_ GP P _T XP 1
P4
P_ GP P _T XN 1
P2
P_ GP P _T XN 0
P3
P_ GP P _T XP 0
N2
P_ GF X _T XP 7
H2
P_ GF X _T XN 7
H4
P_ GF X _T XP 6
H1
P_ GF X _T XN 6
H3
P_ GF X _T XP 5
J2
P_ GF X _T XN 5
J4
P_ GF X _T XP 4
K2
P_ GF X _T XN 4
K4
P_ GF X _T XP 3
L1
P_ GF X _T XN 3
L3
P_ GF X _T XP 2
L2
P_ GF X _T XN 2
L4
P_ GF X _T XP 1
M2
P_ GF X _T XN 1
M4
P_ GF X _T XN 0
N3
P_ GF X _T XP 0
N1
PCIE_ATX_DRX_N5
CC12 1
2 0.1U_0201_10V6K
2 0.1U_0201_10V6K
PCIE_ATX_DRX_P1
CC3 1
PCIE_ATX_DRX_N1
CC4 1
PCIE_ATX_DRX_P3
CC7 1
PCIE_ATX_DRX_P0
CC1 1
PCIE_ATX_DRX_N3
CC8 1
PCIE_ATX_DRX_N0
CC2 1
PCIE_ATX_DRX_P2
CC5 1
PCIE_ATX_DRX_N2
CC6 1
2 0.22U_0402_6.3V6K PCIE_ATX_C_DRX_P0
2 0.22U_0402_6.3V6K
PCIE_ATX_C_DRX_N0
2
0.22U_0402_6.3V6K
PCIE_ATX_C_DRX_P1
2 0.22U_0402_6.3V6K
PCIE_ATX_C_DRX_N1
2
0.22U_0402_6.3V6K
PCIE_ATX_C_DRX_P2
2 0.22U_0402_6.3V6K PCIE_ATX_C_DRX_N2
2
0.22U_0402_6.3V6K
PCIE_ATX_C_DRX_P3
2 0.22U_0402_6.3V6K PCIE_ATX_C_DRX_N3
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
DP0: eDP
DP1: HDMI
DP2: N/A
DP3: N/A
HDT+ (debug + HDT@)
Main Func = CPU
HDMI
eDP
HDMI
eDP
+LCDVDD_CONN PWR switch enable pinVIH=1.2V
ESD
Reserve for sequence tuning
APU_TMS
APU_TDO
APU_TCK
APU_TMS
APU_TDI
APU_TDI
APU_TDO
APU_TCK
APU_TMS
APU_TRS T#
APU _DBR EQ#
INVT PW M
ENV DD
ENB KL_R
APU_TEST31
APU_PW RG D
APU_RS T#
APU_TDI
APU_TCK
INVT PW M_R
ENB KL_R
APU _VDD P_RUN _FB_ H
APU _VDD _RUN_ FB_L
APU_VDDP _RUN_FB _L
APU_TEST470
APU_TEST471
APU_TEST41
APU_TEST31
APU_TEST17
APU_TEST16
APU_TEST14
APU_TEST15
APU_TEST6
APU_TEST5
APU_TEST4
DP_ STER EOSY NC
APU _RST #
APU_PW RG D
APU_AL ERT#
APU_TDI
APU _DBR EQ#
APU_TRST#_RAPU_TRS T#
APU_TEST16
APU_TEST17
APU_TEST14
APU_TEST15
INVT PW M_R
EDP _HPD
ENBKL
CORETYPE
SMU_ ZVDDP
SMU_ ZVDDP
ENB KL_R
APU_RS T#
INVT PW M_R
INVT PW M <14 >
<15> AP U_D P1_P2
<15> AP U_DP 1_N2
<15> AP U_D P1_P3
<15> AP U_DP 1_N3
<15> AP U_D P1_P0
<15> AP U_DP 1_N0
<15> AP U_D P1_P1
<15> AP U_DP 1_N1
<14> EDP _TX P0
<14> EDP _TXN 0
<14> EDP _TX P1
<14> EDP _TXN 1
EDP _AUX N <14>
EDP _HPD <14>
APU _DP1 _CTRL _CLK <15>
APU _DP1 _CTRL _DAT <15>
APU _DP1 _HPD < 15>
<38> AP U_S VC
<38> AP U_S VD
<38> AP U_SV T
<38> AP U_P WR GD
<28> E C_THERMTR IP#
<28 ,38> H_P ROCHO T#
APU _VDD P_RUN _FB_ H < 37>
APU _VDD SOC_ SEN < 38>
APU _VDD CR_SE N <38 >
ENB KL <1 4,2 8>
ENV DD
INVT PW M_R
ENV DD < 14>
<28> A PU_ RST#_ EC
<26 ,28> E C_SMB _CK2
<26 ,28> E C_SMB _DA2
APU _VDD _RUN_ FB_L < 38>
APU _VDD P_RUN _FB_ L <37>
+3V S
+1.8 VALW
+1.8 VS
+3V S
+1.8 VS
+1.8 VALW
+1.8 VS
+1.8 VS
+1.8 VS
+3VALW
+0.8 VS
+1.8 VS
+3V S
+1.8 VS
Tiiitttllle
Securiiity Clllassiiifiiicatiiion
Compal Secret Data
THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL AND
TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIION OF R&D
DEPARTMENT EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IIINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIIT CONTAIIINS
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IIINC...
Issued Date
Deciphii ered Date
LA-H131P
Re v
0...4
FP5 DISP/MISC/HDT
Siiize Documenttt Numbe r
Custttom
Sheettt 7 o fff 46Dattte::: Monday,,, November 05,,, 2018
2018/11/05 2019/11/05
Compal Electronics, Inc.
RC4
1
2 4.7 K_0 402_5%
T15
APU _DBR EQ#
RHDT5 1 HD T@
RHDT81 HDT@ 2 10 K_04 02_5%
RC15 1 @ 2 1K _04 02_5%
APU_TRS T#
RHDT1 1 HDT@
RHDT71 HDT@ 2 10 K_04 02_5%
JHDT1
SAMTE_ASP-1 3644 6-07-B
DC0 21004 270
ME@
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
2
2
4
4
6
6
8
8
10
10
12
12
14
14
16
16
18
18
20
20
RC1 112 @ 1 0_0 402_5 %
RC31 1 2 1K _04 02_5%
APU _ALE RT#
RC28
1 2 1K _04 02_5%
H_PROC HOT#
RC5
1
2 2.2 K_04 02_5%
FP5 REV 0.90
PART 3OF 13
DISPLAY/ SVI2/JT AG/TES T
FP5 _BGA 1140 ~D
UC1 C @
J16
SVD0
SVT0
F16
SVC0
H16
L19
PROCH OT_L
AP16
THERM TRIP _L
J14
SID
J15
ALERT _L
H14
SIC
AW2
PW ROK
AW4
RESE T_L
AW3
DBRE Q_L
AV3
TRST_L
AU1
TCK
AU3
TMS
AU4
TDO
AU2
TDI
F2
DP1_ TXN3
F4
DP1_ TXP3
E4
DP1_ TXN2
F3
DP1_ TXP2
C1
DP1_ TXN1
E1
DP1_ TXP1
D5
DP1_TX N0
E6
DP1_ TXP0
C6
DP0_ TXP3
D6
DP0_ TXN3
B6
DP0_ TXP2
C7
DP0_ TXN2
B8
DP0_ TXN1
D8
DP0_ TXP1
A8
DP0_ TXN0
C8
DP0_ TXP0
AM11
VSS_ SENS E_B
J18
VSS_ SENS E_A
VDD CR _SE NSE
K18
VDDC R_SO C_S ENSE
J19
VDDP _SEN SE
AN11
CORETY PE
AW11
CORETYPE
SMU_ZV DD
V4
TEST4 71
AK21
TEST4 70
AJ21
TEST4 1
AR11
TEST3 1
W24
TEST1 6
F18
TEST1 7
F19
TEST1 5
H19
TEST1 4
G18
TEST6
F13
TEST5
AN14
TEST4
AP14
RSVD _2
F10
DP_S TERE OSY NC
K15
RSVD _4
F14
RSVD _3
F12
DP3_A UXP
J10
DP3_A UXN
H10
DP3_HPD
K8
H12
K13
DP2_A UXN
DP2_HP D
DP1_ AUXP
G11
DP1_ AUXN
F11
DP1_ HPD
G13
DP2_ AUXP
J12
DP0_ AUXN
B9
DP0_ HPD
C10
DP0_ AUXP
D9
EDP _AUX P <1 4>
DP_D IGON
F15
DP_V ARY_ BL
L14
DP_B LON
G15
QC1
LBSS139WT1 G_S C70-3
SB0 0001 GC00
Gate
2
Source
3
Drain
1
RHDT91 HDT@ 2 10 K_04 02_5%
UC22
74A UP1G 07GW _SC70 -5
SA000 07W E00
@
NC
1
A
2
3
Y
4
G P
5
T9
UC6
74A UP1G 07GW _SC70 -5
SA0 0005 U600
1
NC
A
2
3
Y
4
G P
5
RC6
1
2 100 K_0 402_5%
RC9 1
T16
RC11 1 @
RC30 1 @ 2 220_ 0402 _5%
APU _PW RGD
RC8
1
2 100 K_0 402_5%
DP_ STER EOSY NC
RC17 1
2 1K _040 2_5%
QC4
LBSS139WT1 G_S C70-3
SB0 0001 GC00
@
2
3
Gate
Drain
Source
1 IN VTPW M
RC10 1
2 100 K_0 402_5%
2 100 K_0 402_5%
T3
@
CHDT1 1 2 0 .01 U_04 02_16 V7K
ESD @ CC1 7 1
RC12 1 @
RC13 1 @
T8
T10
T11
RC24 1 2 3 00_ 0402_ 5%
APU _RST #
RC25
1 2 30 0_04 02_5%
APU_P WRGD
T1
T2
RC14 1 @
2
10K _040 2_5%
2
10K _040 2_5%
2
10K _040 2_5%
2
10K _040 2_5%
RC21 1 @ 2 0_0 402_ 5% THERMTRIP #
HDT@
APU _DBR EQ#
CHDT2 1
2 0.0 1U_0 402_1 6V7K
RHDT2 1 HDT@
T4
T5
T6
T7
RC22 1 2 196 _040 2_1%
ESD @ CC 18 1
ESD @ CC 19 1
2
100 P_04 02_50V 8J
H_P ROCH OT#
2
100 P_04 02_50V 8J
APU _PW RGD
2
100 P_04 02_50V 8J
APU _RST #
RC18 1 @ 2 1 K_0 402_5 %
HDT@
APU_TRS T#
CHDT3 1 2 0.0 1U_0 402_1 6V7K
RC23 1 @ 2 1 K_0 402_5%
RHDT3 1 HDT@
RC16 1 @ 2 1K _04 02_5%
RHDT61 HDT@ 2 33_ 0402 _5%
T12
T13
T14
RHDT4 1 HDT@
2
1K_ 0402 _5%
2
1K_ 0402 _5%21K_ 0402 _5%21K_ 0402 _5%21K_ 0402 _5%
RC29 1 2 1K _04 02_5% THE RMTRIP#
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Main Func = CPU
ESD
EMI
STRAPS
STRAPS
DEFINITION
SPI_CLK
1 : Use 48 MHZ Crystal Cl ock and Gene rate both internal
and external clocks (Default)
0 : Use 10 0MHZ PCIE clock as reference clock
and generate inter nal clocks o nly
SYS_RST#
1 : Normal reset m ode (Default) 0
: short reset mode
Not Implemented Need Pull down by SW
(
( )
( )
)
( )
___
(
( )
( )
)
Capaci
t
y
Description
WITHOUT ON-BOARD RAM
AGPIO11
MEM ID2
AGPIO9
MEM ID1
AGPIO6
MEM ID0
0 0 0
4GB
N/A 0 0 1
N/A 0 1 0
N/A 0 1 1
N/A 1 0 0
SAMSUNG 2666MHz K4A8G165WC-BCTD 1 0 1
MICRON 2666MHz MT40A512M16LY-075:E 1 1 0
HYNIX 2666MHz H5AN8G6NCJR-VKC 1 1 1
Function
MODEL ID
_
( )
S340-14
AGPIO69
0
S340-15 1
( )
Capaci
t
y
Description
WITHOUT ON-BOARD RAM
X76
N/A
PART NUMBER R1
N/A
PART NUMBER R3
N/A
4GB
SAMSUNG 2666MHz K4A8G165WC-BCTD X7680438L53 SA0000B6F00 SA0000B6F10
MICRON 2666MHz MT40A512M16LY-075:E X7680438L52 SA0000ARD20 SA0000ARD30
HYNIX 2666MHz H5AN8G6NCJR-VKC X7680438L51 SA0000BMN00 SA0000BMN10
N/A N/A N/A N/A
N/A N/A N/A N/A
N/A N/A N/A N/A
N/A N/A N/A N/A
_
( )
ON BOARD RAM ID
No On Board RAM Straps (NO_OBR@)
HDA_BIT_C LK
APU_ FCH_ PWRGD _R
SYS _PWRG D_EC
EC_RSMR ST#
SYS_RESET#
EC_RSMR ST#
PBTN_OUT#
SYS_RESET#
APU_PCIE _WAKE#
PM_SLP _S5#
HDA_BIT_ CLK
HDA_SDIN0
HDA_RST#
HDA_SYNC
HDA_SPKR
APU_PCIE0 _RST#
APU_PCIE1 _RST#
APU_PCIE _RST#_R
PM_SLP _S3#
I2C_2_SCL
I2C_2_SDA
MEM_ID 2
MEM_ID 0
MEM_ID 1
APU_PCIE _RST#_R
APU_PCIE _WAKE#
HDA_SYNC
HDA_BIT_ CLK
HDA_ SDOUT
HDA_RST#
HDA_SDIN0
SYS_RESET#
PCIE_D ET
PBTN_OUT#
MEM_ID 1
PCIE_DET
MEM_ID0
MEM_ID 2
I2C_3_SCL
I2C_3_SDA
MODEL_I D
MIC_SE LECT
MODEL_I D
I2C_3_SCL
I2C_3_SDA
I2C_3_SCL
I2C_2_SCL
I2C_2_SDAI2C_2_SDA_R
I2C_2 _SCL_R
<28> S YS_P WRGD _EC
<28> PB TN_O UT#
<28> PM_SL P_S3#
<28,3 3,36> PM_S LP_S5#
HDA_ SPKR <21>
<21> HDA_S DIN0
EC_RSMR ST# <28 >
APU_PCIE _RST# < 16,17, 20>
<21> HDA_BITC LK_AUDIO
<21> HDA_ SDOUT_AUDIO
<21> HD A_SYNC_AUDI O
<9> APU_SP I_CLK_ R
PCIE_D ET <17>
TP_INT# <27>
<27> I2C _3_SCL _R
I2C_2 _SCL <13>
I2C_2 _SDA <13>
<27> I2C _3_SDA_ R
+3VALW +3VALW
+3VALW
+1.8VALW
+3VALW
+3VALW
+3VS
+1.8VAL W +3VALW
+3VS
+3VS
Tiiitttllle
Siiize Documenttt Numberrr
SecuriiityClllassiiifiiicatiiion
Compalll Secret Data
LA-H131P
Re v
0...4
FP4 GPIO/AZ/MISC/STRAPS
Custttom
Sheettt 8 o fff 46Dattte::: Monday,,, Novemberrr 05,,,2018
Issued Date
2018/1// 1/0// 5
DeciiipheredDatett
2019///11///05
THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL AND TRADE
SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIION OF R&D DEPARTMENT EXCEPT AS
AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IIINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIITCONTAIIINS
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,,IIINC...
Compal Electronics, Inc.
Not Implemented Need Pull down by SW
T23
@
CC2 6
0.1U_0 201_1 0V6K
1
2
RC5 9
10K_0402_5%
1 2
T24
RC6 0
10K_0402_5%
1 2
RC117 1 @ 2 0_0402_5%
RC7 2
10K_0402_5%
12
RC6 5
2K_0402_5%
@
12
RC4 8 1 @ 2 10K _0402 _5%
RC6 6
2K_0402_5%
@
12
RC7 3 1 @ 2 0_0402_5%
2 1 0K_040 2_5%
2 2 .2K_04 02_5%
QC3 A
2N70 02KD W2N SC 88-6
SB000 00EO00
61
2
UC7
74AUP1G0 7GW_S C70-5
SA0000 7WE00
@
NC
1
A
2
3
Y
4
G P
5
RC5 0 1 2 1K_ 0402_ 5%
RC6 1 1
RC6 2 1
2 2 .2K_04 02_5%
RC6 8 1 2 33_0402_5%
RC6 9 1 2 33_0402_5%
RC3 8
10K_0402_5%
X76RAM@
1 2
RC112
10K_0402_5%
15@
1 2
1 2
RC5 3 1 @ 2 10K _0402 _5%
RC3 9
10K_0402_5%
X76RAM@
1 2
RC5 4 1 @ 2 10K _0402 _5%
RC6 7 1 EMI@ 2 33_0402_5%
RC118 1 @ 2 0_0402_5%
150 P_0 402 _50V 8J
@
CC2 1
1
2
RC115
10K_0402_5%
14@
1 2
FP5REV 0.90
PART 4 OF13
ACPI/AUDIO/I2C/GPIO/MISC
FP5_B GA1140~D
UC1D @
AT2
SW_MCLK/TDM_BCLK_BT
AT4
SW_DATA0/TDM_DOUT_BT
AR6
AGPIO7/FCH_ACP_I2S_SDIN_BT
AP6
AGPIO8/FCH_ACP_I2S_LRCLK_BT
HDA_ SDOUT
AR3
AZ_SDOUT/TDM_FRM_PLAYBACK
AR4
AZ_SYNC/TDM_FRM_MIC
AP3
AZ_RST_L/SW_DATA1A/SW_DATA 3/TDM_DATA_MIC
check list discuss unconnected if no used
AP4
AZ_SDIN2/SW_DATA2/TDM_DATA _PLAYBACK
AP7
AZ_SDIN0/CODEC_GPI
AP1
AZ_SDIN1/SW_DATA1B/TDM_BCL K_PLAYBACK
AR2
AZ_BITCLK/TDM_BCLK_MIC
AW 8
EGPIO42
AT10
AC_PRES/AGPIO23
AN6
LLB_L/AGPIO12
AR8
S0A3_GPIO/AGPIO10
AT14
SLP_S5_L
AV13
SLP_S3_L
AP10
SYS_RESET_L/AGPIO1
AV11
WAKE_L/AGPIO2
APU_ FCH_ PWRGD _R
AV6
PWR_GOOD
AR15
PWR_BTN_L/AGPIO0
BB6
PCIE_RST1_L/EGPIO27
AT16
RSMRST_L
BD5
PCIE_RST0_L/EGPIO26
FANOUT0/AGPIO85
AT18
FANIN0/AGPIO84
AR18
3.3VS input
GENINT1_L/AGPIO89
AW16
3.3VS input
GENINT2_L/AGPIO90
BD15
3.3VS Output
SPKR/AGPIO91
AU16
BLINK/AGPIO11
AV8
INTRUDER_ALERT
AU14
3.3VALW input
AGPIO69
AW13
3.3VS input
AGPIO86
AW15
3.3VALW input
AGPIO40
AU6
3.3VALW input
AGPIO9
AU7
3.3VALW input
AGPIO6/DEVSLP1
AU10
SATA_ACT_L/AGPIO130
AV15
AGPIO5/DEVSLP0
AP9
AGPIO4/SATAE_IFDET
AW10
AGPIO3
AT15
PSA_I2C_SCL
L16
PSA_I2C_SDA
M16
I2C3_SDA/AGPIO20/SDA1
AM10
I2C_3 _SDA
I2C3_SCL/AGPIO19/SCL1
AM9
I2C2_SDA/EGPIO114/SDA0
BA20
I2C2_SCL/EGPIO113/SCL0
BC20
I2C1_SCL/SFI1_I2C_SCL/EGPIO149
AN8
I2C1_SDA/SFI1_I2C_SDA/EGPIO150
AN9
I2C0_SCL/SFI0_I2C_SCL/EGPIO151
AR13
I2C0_SDA/SFI0_I2C_SDA/EGPIO152
AT13
AGPIO39/SFI_S5_AGPIO39
AU12
EGPIO41/SFI_S5_EGPIO41
AW12
Function MIC SELECT
AGPIO84
1 MIC 0
2 MIC 1
+3VS
RC113
10K_0402_5%
MULTI_MIC@
MIC_SE LECT
RC116
10K_0 402_5 %
SINGL E_MIC@
1 2
RC5 6 1
RC5 7 1
2 2.2 K_0402 _5%
2 2.2 K_0402 _5%
RC3 7
10K_0402_5%
X76RAM@
1 2
RC4 3
10K_0402_5%
X76RAM@
1 2
UC8
@
MC74VHC1 G08DFT2 G S C70 5P
SA0000 0OH00
B
2
A
1
Y
4
P
5
G
3
@ES D@
CC2 4 1 2 10 0P_040 2_50V8J
RC4 2
10K_0402_5%
X76RAM@
1 2
T21
150 P_0 402 _50V 8J
1
2
CC2 0
RC3 6 1 2 22K _0402_ 5%
RC64 2 @ 1 0_0402_5%
RC4 5 1
RC4 7 1
2 1 0K_040 2_5%
RC3 4 1 2 33_0402_5%
RC3 5 1 @ 2 33_0402_5%
RC41 NO_OB R@
10K_0 402_5 %
RC42 NO_OB R@
10K_0 402_5 %
RC4 3 NO_O BR@
10K_0 402_5 %
ESD @
CC2 3 1 2 10 0P_040 2_50V8J
T22
RC4 1
10K_0402_5%
X76RAM@
1 2
QC3 B
2N70 02KD W2N SC 88-6
SB000 00EO00
3
5
4
RC7 0 1
RC7 1 1
2 1K_ 0402_5 %
2 1K_ 0402_ 5%
1
CC2 2
0.1U_0 201_1 0V6K
2
RC5 5
8.2K _0402_5%
12
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Main Func = CPU
32.768KHz CRYSTAL
48MHz CRYSTAL
USB3.1 Type-A Po rt 2
USB3.1 Type-A Po rt 1
Type-A left port2
EMI
SPI ROM (XMC)
EMI
Type-A left port1
NGFF _BT
EMI
Came ra
USB3.1 Type- C
USB2.0 Hub
Main_SS D
CardReader
WLAN
TYPEC Right
Vendor Tuning Va lue was 3.9pF, Lack Source
48M_X1
48M_X2
LPC_AD0 _R
LPC_AD1 _R
LPC_AD2 _R
LPC_AD3 _R
32K_X2
32K_X1
LPC_CL K0
LPCP D#
LPC_RS T#
USB3_ARX _DTX_P2
USB3_ATX_ DRX_P2
USB20_P 1
USB20_N1
USB20_P 2
USB20_N2
RTC_CLK
USB_ OC0#
USB_ OC1#
KB_RST#
USB_ OC0#
USB_ OC1#
LPC_RS T#
APU_SPI_ MOSI
APU_SPI_ MISO
APU_SPI_ WP#
APU_SPI_HOLD#
APU_SPI_ CS1#
APU_SPI_ CLK
32K_X1
32K_X2
CLKRE Q_SSD1#
CLK REQ_S D#
CLKRE Q_W LAN#
USB3_ARX _DTX_P1
USB20_P 5
USB20_N5
USB20_P 3
USB20_N3
USB20_P 4
USB20_N4
USB20_P 0
USB20_N0
CLK_PC IE_SSD1 #
CLK_PC IE_SSD1
CLK_PC IE_SD
CLK_PC IE_SD#
CLK_PC IE_WL AN#
CLK_PC IE_WL AN
CLKRE Q_SSD1#
CLKRE Q_SD#
CLKRE Q_W LAN#
APU_BT_OF F#
SERIRQ <28>
LPC_FR AME# < 28>
LPC_RS T#_R <2 8>
USB3_ARX _DTX_N2 <20 >
USB3_ATX_ DRX_P2 <20>
USB3_ATX_ DRX_N2 <2 0>
<20> USB20 _P1
<20> USB2 0_N1
<20> USB20 _P2
<20> USB2 0_N2
<16> R TC_CLK_ R
KB_RST# <28>
EC_SCI # <28>
<20> USB_ OC0 #
<20> USB_ OC1 #
APU_SPI_ CLK_R <8 >
UART_0_ARX D_DTXD <16 >
UART_0_ATX D_DRXD <16 >
USB3_ATX_ DRX_P1 <20>
USB3_ATX_ DRX_N1 <2 0>
<16> USB20 _P5
<16> USB2 0_N5
LPC_AD0 <2 8>
LPC_AD1 <2 8>
LPC_AD2 <2 8>
LPC_AD3 <2 8>
LPC_CL K0_EC <28>
CLK RUN# <2 8>
<14> USB20 _P3
<14> USB2 0_N3
<22> USB20 _P4
<22> USB2 0_N4
<25> USB20 _P0
<25> USB2 0_N0
<17> CL K_PCIE_ SSD1
<17> CL K_PCIE_ SSD1#
<20> CLK _PCIE_ SD
<20> CLK _PCIE_ SD#
<16> CL K_PCIE_ WLAN
<16> CL K_PCIE_ WLAN#
<17> C LKRE Q_SSD 1#
<20> CLK REQ_S D#
<16> C LKRE Q_WL AN#
<16> AP U_BT_OFF #
SSD_RS T# < 17>
APU_ WL_O FF# <1 6>
USB3_ARX _DTX_P0 <24>
USB3_ARX _DTX_N0 <2 4>
USB3_ATX_ DRX_P0 <24>
USB3_ATX_ DRX_N0 <2 4>
+1.8VALW
+3VS
+3VALW
+3VS
+1.8VALW
Tiiitttllle
Siiize Documenttt Numberrr
SecuriiityClllassiiifiiicatiiion
Compalll Secret Data
LA-H131P
Re v
0...4
FP5 SATA/CLK/USB/SPI
Custttom
Sheettt 9 offf 46Dattte::: Monday,,, Novemberrr 05,,,2018
Issued Date
2018/1// 1/0// 5
DeciiipheredDatett
2019///11///05
THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL AND TRADE
SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIION OF R&D DEPARTMENT EXCEPT AS
AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IIINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIITCONTAIIINS
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,,IIINC...
Compal Electronics, Inc.
CC31
10P_0402_50V8J
1
2
FP5REV 0.90
PART 5 OF13
CLK/LPC/EMMC/SD/SPI/eSPI/UART
FP5_B GA1140~D
UC1E @
AY4
X32K_X2
AY1
X32K_X1
AW 14
RTCCLK
AF8
RSVD_76
AF9
RSVD_77
BA5
X48M_X2
BB3
X48M_X1
AN2
GPP_CLK4P
AN4
GPP_CLK4N
AN3
GPP_CLK5P
AP2
GPP_CLK5N
AJ2
GPP_CLK6P
AJ4
GPP_CLK6N
AJ3
48M_OSC
AL4
GPP_CLK3N
AL2
GPP_CLK3P
AM3
GPP_CLK2N
AM1
GPP_CLK2P
AM2
GPP_CLK1P
AM4
GPP_CLK1N
AK1
GPP_CLK0P
AK3
GPP_CLK0N
AW 18
CLK_REQ5_L/EGPIO120
AW 19
CLK_REQ6_L/EGPIO121
AU19
CLK_REQ4_L/OSCIN/EGPIO132
AT19
CLK_REQ3_L/SATA_IS1_L/SATA_Z P1_L/EGPIO131
AP19
CLK_REQ2_L/AGPIO116
AN19
CLK_REQ1_L/AGPIO115
AV18
CLK_REQ0_L/SATA_IS0_L/SATA_Z P0_L/AGPIO92
AGPIO144/UART1_INTR
BB16
APU_ WL_ OFF#
EGPIO140/UART1_CTS_L/UART3_TXD
BB19
EGPIO142/UART1_RTS_L/UART3_RXD
BC16
SSD_RS T#
EGPIO141/UART1_RXD
BC18
EGPIO143/UART1_TXD
BA17
UART0_INTR/AGPIO139
BD18
UART0_CTS_L/UART2_TXD/EGPIO135
BA18
UART0_RTS_L/UART2_RXD/EGPIO137
BC17
UART0_TXD/EGPIO138
BB18
UART_0_ATX D_DRXD
UART0_RXD/EGPIO136
BA16
UART_0_ARX D_DTXD
SPI_CS2_L/ESPI_CS_L/AGPIO30
BA8
Not Implemented Need Pull down bySW
SPI_CS3_L/AGPIO31
BA6
SPI_TPM_CS_L/AGPIO29
BD8
SPI_CS1_L/EGPIO118
BC9
APU_SPI_ CS1#
SPI_HOLD_L/ESPI_DAT3
BC10
APU_SPI_ HOLD#
SPI_WP_L/ESPI_DAT2
BA10
APU_SPI_ WP#
SPI_DO
BB10
APU_SPI_ MOSI
SPI_DI/ESPI_DATA
BA9
APU_SPI_ MISO
ESPI_RESET_L/KBRST_L/AGPIO129
BB11
ESPI_ALERT_L/LDRQ0_L/EGPIO108
BC6
SPI_ROM_REQ/EGPIO67
BC8
SPI_ROM_GNT/AGPIO76
BB8
LPC_PME_L/SD_PWR_CTRL/AGPIO22
BA13
AGPIO68/SD_CD
BA11
LPC_RST_L/SD_WP_L/AGPIO32
BD11 RC8 2 2 1 33_0402_5%
LFRAME_L/EGPIO109
BA12
SERIRQ/AGPIO87
BC12
LPCCLK1/EGPIO75
BB13
Not Implemented Need Pull down by SW
LPC_CLKRUN_L/AGPIO88
BC13 CLKRUN#
LPCCLK0/EGPIO74
BA15
LAD3/SD_DATA3/EGPIO107
BC15
LAD2/SD_DATA2/EGPIO106
BB15
LAD1/SD_DATA1/EGPIO105
BC11
LAD0/SD_DATA0/EGPIO104
BB12
EGPIO70/SD_CLK
BD13
LPC_PD_L/SD_CMD/AGPIO21
BB14
RC8 7 2 @ 1 22 +-5% 0402
1 10_0402_5%
1 10_0402_5%
RC7 7 2
RC7 8 2
48M_X2 _R
RC7 4 1 EMI@ 2 33_0402_5%
48M_X2
1 10_0402_5%RC7 9 2
CC2 9 2 1 150P_0 402_50 V8J
T17 Not Implemented Need Pull down by SW
USB
FP5REV 0.90
PART 10 OF13
FP5_B GA1140~D
UC1J @
AW 7
AGPIO14/USB_OC4_L
Not Implemented Pull down by SW
AT12
AGPIO13/USB_OC5_L
AL9
USB_OC2_L/AGPIO18
AL8
USB_OC3_L/AGPIO24
AK9
USB_OC1_L/AGPIO17
AK10
USB_OC0_L/AGPIO16
AM6
USBC_I2C_SCL
AM7
USBC_I2C_SDA
AD8
USB_1_DM1
AD9
USB_1_DP1
AJ11
USB_1_DM0
AJ12
USB_1_DP0
AE10
USB_0_DP3
AE9
USB_0_DM3
AF12
USB_0_DP2
AF11
USB_0_DM2
AG9
USB_0_DM1
AG10
USB_0_DP1
AE6
USB_0_DM0
AE7
USB_0_DP0
USB_1_RXP0
AK7
USB_1_RXN0
AK6
USB_1_TXP0
AH4
USB_1_TXN0
AH2
USBC1_A11/DP2_TXP0
AB2
USBC1_A10/DP2_TXN0
AB4
USBC1_B2/DP2_TXP1
AC1
USBC1_B3/DP2_TXN1
AC3
USB_0_RXN2
AG6
USBC1_A2/USB_0_TXP3/DP2_TXP2
AA2
USBC1_A3/USB_0_TXN3/DP2_TXNA2
A4
USBC1_B11/USB_0_RXP3/DP2_TXPY3
1
USBC1_B10/USB_0_RXN3/DP2_TXNY3
3
USB_0_RXP2
AG7
USB3_ARX _DTX_N2
USB3_ARX _DTX_P2 <20>
USB_0_TXN2
AG2
USB_0_TXP2
AG4
USB3_ATX_ DRX_N2
USB_0_RXN1
AJ8
USB3_ARX _DTX_N1 <2 0>
USB_0_RXP1
AJ9
USB3_ARX _DTX_N1
USB3_ARX _DTX_P1 <20>
USB_0_TXP1
AG3
USB3_ATX_ DRX_P1
USB_0_TXN1
AG1
USB3_ATX_ DRX_N1
USBC0_B2/DP3_TXP1
AF4
USBC0_B3/DP3_TXN1
AF2
USBC0_A11/DP3_TXP0
AE3
USBC0_A10/DP3_TXN0
AE1
USBC0_B11/USB_0_RXP0/DP3_TXPA3
C2
USB3_ARX _DTX_P0
USBC0_B10/USB_0_RXN0/DP3_TXNA3
C4
USB3_ARX _DTX_N0
USBC0_A2/USB_0_TXP0/DP3_TXP2
AD2
USB3_ATX_ DRX_P0
USBC0_A3/USB_0_TXN0/DP3_TXNA2
D4
USB3_ATX_ DRX_N0
Z_9PF_X1A0 0014100 0200
W00
1
CC30
10P_0402_50V8J
1
2
SPI_CLK/ESPI_CLK
BB7
APU_SPI_ CLK
RC8 4 2 EMI@ 1 10_0402_1%
1 10_0402_5%
1 22_0402_5%
RC8 0 2
RC8 1 2
1 1 0K_040 2_5%RC8 9 2
2 1 00K_04 02_5%
1
CC3 2
0.1U_0 201_1 0V6K
@
2
1
CC2 8
4.7P _0402_50V8C
2
SE071 47AB80
YC1
48MHZ_8PF_7V48000 010
SJ100 00JP0 0
1
1
2
2
3
3
4
4
RC8 5 2 @ 1 10K _0402_ 5%
RC8 3 2 @ 1 100 K_040 2_5%
UC2
APU_SPI_ CS1#
1
8
APU_SPI_ MISO
2
CS# VCC
7
APU_SPI_ HOLD#
APU_SPI_ WP#
3
DO(IO1) HOLD#(IO3)
6
APU_SPI_ CLK_R
4
WP#(IO2) CLK
5
APU_SPI_ MOSI GND
DI(IO0)
S IC FL 64M X M25QU64AHI GT SOP 8P SPI RO M
SA0000 BJU00
RC9 7 2 @EMI @ 1 10_0402_5%
1
CC2 7
4.7P _0402_50V8C
2
SE071 47AB80
1 10 K_0402 _5%
1 10 K_0402 _5%
RC9 0 2
RC9 1 2
T18
T19
T20
RC7 5 1M_040 2_5%
2
RC9 8 1
RC9 9 1
2 1 00K_04 02_5%
RC9 2 2 @ 1 10K _0402 _5%
1
48M_X1 _R
RC7 6 1 EMI@ 2 33_0402_5%
48M_X1
RC8 6
20
M_0402_5
2
YC2
32.768KH
SJ10000P
%
12
CC3 3
10P_0402_50V8J
@EMI @
1
2
1 10 K_0402 _5%
1 10 K_0402 _5%
1 10 K_0402 _5%
1 10 K_0402 _5%
RC9 3 2
RC9 4 2
RC9 6 2
RC9 5 2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
+VDDP_ALW
Main Func = CPU
All BU(on bottom side under SOC)
Across VDDIO & VSS split.
BO BU
BO B U BO BU
TDC: 35A
EDC: 45A
TDC :6A
TDC :10A
EDC: 13A
TDC :4A
Note : Cap placemet need to close APU
VDDIO_AUDIO
<28> EC_C LEAR_CMOS#
+1.8VALW
+3VS
+1.8VS
+0.8VALW
+1.8VS
+1.2V
+APU_CORE
+APU_CO RE_SOC
+1.2V
+1.8VS
+RTC_APU
+0.8VALW
+0.8VS
+0.8VS
+3VALW
+RTCBATT
+RTC_APU
+3VALW
+1.8VALW
+3VS
Tiiitllle
Security Classification
Compal Secret Data
THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPER TY OF COM PAL ELECTRONIIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL AND
TRADE SECRE T IIINFORMATIIION... THIIIS SH EET MAY N OT BE TR ANSFER ED FROM THE CUS TODY OF THE COMP ETENT DIIIVIIISIIION OF R& D
DEPAR TMENT EXCE PT AS AUTHORIIIZED BY COM PAL ELECTRONIIICS,,, IIINC... NEIIITHER THIIIS SHE ET NOR THE IIINFORMATIIION IIIT CONTAIIINS
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PA RTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMP AL ELECTRONIIICS,,, IIINC...
Issued Date
DecipheredDate
LA-H131P
R ev
0.4
FP4PWR
Siiize Document Number
Custom
Sheet 10 o f 46Date: Monday, November 05, 2018
2018/11/05 2019/11/05
Compal Electronics,Inc.
CC70
22U_0603_6.3
V6M
1
2
CC62 @
1U_0201_6.3V6M
1
2
1.5V
UC11
AP2138N-1.5TRG1_SOT23-3
SA000066U00
Vin
1
Vout
GND
2
CC78
10U_0402_6.3
V6M
1
2
CC74
1U_0201_6.3V6M
1
2
CC59
1U_0201_6.3V6M
1
2
CC80
1U_0201_6.3V6M
1
2
CC52
22U_0603_6.3
V6M
1
2
@
RC101 1
2 0_0402_5%
VDDIO_AU DIO
CC73
22U_0603_6.3
V6M
1
CC67
1U_0201_6.3V6M
1
2
CC79 @
1U_0201_6.3V6M
1
2
FP5 REV0.90
PART 6 OF13
POWER
FP5_BGA1140~D
UC1F @
TDC :4.5uA AT 11
VDDBT_RTC _G
AN13
VDDP_5
AN12
VDDP_4
AM13
VDDP_3
AM12
VDDP_2
AL13
VDDP_1
AM14
VDDP_S5_ 3
AL15
VDDP_S5 _2
TDC :1A AL14
VDDP_S5_1
AM16
VDD_33_ S5_2
TDC :0.25A AL17
VDD_33_ S5_1
AM18
VDD_18_ S5_2
TDC :0.5A AL1 9
VDD_18_ S5_1
AM19
VDD_18_ 2
TDC :2A AL20
VDD_18_ 1
AM17
VDD_33_ 2
TDC :0.25A AL18
VDD_33_ 1
TDC :0.2A AP12
VDDIO_AUDI O
AL32
VDDIO_ME M_S3_40
AL28
VDDIO_ME M_S3_39
AK28
VDDIO_ME M_S3_38
AJ32
VDDIO_ME M_S3_37
AJ28
VDDIO_ME M_S3_36
AJ26
VDDIO_ME M_S3_35
AJ23
VDDIO_ME M_S3_34
AJ20
VDDIO_ME M_S3_33
AG28
VDDIO_ME M_S3_32
AG25
VDDIO_ME M_S3_31
AG22
VDDIO_ME M_S3_30
AG20
VDDIO_ME M_S3_29
AF32
VDDIO_ME M_S3_2 8
AF28
VDDIO_ME M_S3_2 7
AF26
VDDIO_ME M_S3_2 6
AF23
VDDIO_ME M_S3_2 5
AE28
VDDIO_ME M_S3_24
AE25
VDDIO_ME M_S3_23
AE22
VDDIO_ME M_S3_22
AE20
VDDIO_ME M_S3_21
AD32
VDDIO_ME M_S3_20
AD28
VDDIO_ME M_S3_19
AD26
VDDIO_ME M_S3_18
AD23
VDDIO_ME M_S3_17
AC28
VDDIO_ME M_S3_16
AC25
VDDIO_ME M_S3_15
AC22
VDDIO_ME M_S3_14
AC20
VDDIO_ME M_S3_13
AA32
VDDIO_ME M_S3_12
AA28
VDDIO_ME M_S3_11
AA26
VDDIO_ME M_S3_10
AA23
VDDIO_ME M_S3_9
AA20
VDDIO_ME M_S3_8
Y28
VDDIO_ME M_S3_7
Y25
VDDIO_ME M_S3_6
Y22
VDDIO_ME M_S3_5
W3 2
VDDIO_ME M_S3_4
W2 8
VDDIO_ME M_S3_3
V28
VDDIO_ME M_S3_2
T32
VDDIO_ME M_S3_1
Y19
VDDCR_SOC _17
W2 0
VDDCR_SO C_16
W1 8
VDDCR_SO C_15
V19
VDDCR_SOC _14
U20
VDDCR_SOC _13
U18
VDDCR_SOC _12
T19
VDDCR_SOC _11
R20
VDDCR_SOC _10
R18
VDDCR_SOC _9
P19
VDDCR_SOC _8
P17
VDDCR_SOC _7
N20
VDDCR_SOC _6
N18
VDDCR_SOC _5
N16
VDDCR_SOC _4
M19
VDDCR_SO C_3
M18
VDDCR_SO C_2
M15
VDDCR_SO C_1
VDDCR_8 3
AK19
VDDCR_8 2
AK17
VDDCR_8 1
AK15
VDDCR_8 0
AK13
VDDCR_7 9
AJ18
VDDCR_7 8
AJ16
VDDCR_7 7
AJ14
VDDCR_7 6
AJ10
VDDCR_7 5
AJ7
VDDCR_7 4
AH19
VDDCR_7 3
AH17
VDDCR_7 2
AH15
VDDCR_7 1
AH13
VDDCR_7 0
AG18
VDDCR_6 9
AG16
VDDCR_6 8
AG14
VDDCR_6 7
AF19
VDDCR_6 6
AF17
VDDCR_6 5
AF15
VDDCR_6 4
AF13
VDDCR_6 3
AF10
VDDCR_6 2
AF7
VDDCR_61 AE18
VDDCR_60 AE16
VDDCR_5 9
AE14
VDDCR_5 8
AE8
VDDCR_5 7
AD19
VDDCR_5 6
AD17
VDDCR_5 5
AD15
VDDCR_5 4
AD13
VDDCR_5 3
AD10
VDDCR_5 2
AD7
VDDCR_5 1
AC18
VDDCR_50 AC16
VDDCR_49 AC14
VDDCR_4 8
AB19
VDDCR_4 7
AB17
VDDCR_4 6
AB15
VDDCR_4 5
AB13
VDDCR_4 4
AA18
VDDCR_4 3
AA16
VDDCR_4 2
AA14
VDDCR_4 1
AA10
VDDCR_4 0
AA7
VDDCR_39 Y17
VDDCR_38 Y15
VDDCR_37 Y13
VDDCR_3 6
Y8
VDDCR_3 5
W1 6
VDDCR_3 4
W1 4
VDDCR_3 3
W1 0
VDDCR_3 2
W7
VDDCR_3 1
V17
VDDCR_3 0
V15
VDDCR_29 V13
VDDCR_28 U16
VDDCR_27 U14
VDDCR_26 T17
VDDCR_2 5
T15
VDDCR_2 4
T13
VDDCR_2 3
T10
VDDCR_2 2
T7
VDDCR_2 1
R16
VDDCR_2 0
R14
VDDCR_19 R8
VDDCR_18 P15
VDDCR_17 P13
VDDCR_16 P10
VDDCR_15 P7
VDDCR_1 4
N14
VDDCR_1 3
M10
VDDCR_1 2
M7
VDDCR_1 1
L8
VDDCR_1 0
K14
VDDCR_9
K12
VDDCR_8
K7
VDDCR_7
H15
VDDCR_6
H11
VDDCR_5 H8
VDDCR_4 G14
VDDCR_3 G12
VDDCR_2 G10
VDDCR_1 G7
CC81
0.22U_0402_6.3V6K
1
2
CC43
1U_0201_6.3V6M
1
2
CC65 @
1U_0201_6.3V6M
CC63
180P_0402_50V8J
1
2
CC36
22U_0603_6.3
V6M
1
2
CC37
22U_0603_6.3
V6M
1
2
CC64
22U_0603_6.3
V6M
1 1
2 2
CC45
180P_0402_50V8J
1
2
CC75 @
22U_0603_6.3
V6M
1
2
CC40
22U_0603_6.3
V6M
1
2
CC46
180P_0402_50V8J
1
2
CC66
1U_0201_6.3V6M
1
2
CC58
1U_0201_6.3V6M
1
2
CC76
1U_0201_6.3V6M
1
2
CC56 @
1U_0201_6.3V6M
1
2
CC41
22U_0603_6.3
V6M
1
2
CC77
1U_0201_6.3V6M
1
2
CC42
22U_0603_6.3
V6M
1
2
CC57
1U_0201_6.3V6M
1
2
CC35
22U_0603_6.3
V6M
1
2
CLRP1
SHORT PADS
@
2 1
CC61 @
1U_0201_6.3V6M
1
2
CC55
1U_0201_6.3V6M
1
2
RC107 1 2 10K_0402_ 5%
+RTCBATT_R
3
CC69
1U_020 1_6.3V6M
2
CC49
.22U 6.3V K X5R 0402
1
2
CC39
22U_0603_6.3
V6M
1
2
CC72
1U_0201_6.3V6M
1
2
CC53
22U_0603_6.3
V6M
1
2
CC50
.22U 6.3V K X5R 0402
1
2
CC68
22U_06 03_6.3V6 M
1 1
2
CC60 @
1U_0201_6.3V6M
1
2
C1 @
1U_0201_6.3V6M
1
2 2
CC54
22U_0603_6.3
V6M
1
2
CC48
.22U 6.3V K X5R 0402
1
2
CC51
.22U 6.3V K X5R 0402
1
2
CC47
180P_0402_50V8J
1
2
CC71
1U_0201_6.3V6M
1
2
@
RC106 1 2 0_0402_5%
CC38
22U_0603_6.3
V6M
1
2
CC44
1U_0201_6.3V6M
1
2
CC82
1U_0201_6.3V 6M
2 1
5
5
4
4
3 2 1
1
D D
C C
B B
A A
Main Func = CPU
Title
Size
Document Number
Date: Sheet
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THEINFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3 2
Issued Date
Deciphered Date
LA-H131P
Rev
0.4
FP5 GND
Custom
11 of 46Monday, November 05, 2018
2018/11/05 2019/11/05
Compal Electronics, Inc.
GND/RS VD
FP5 REV 0.90
PART 11 OF 13
FP5_BGA1140~D
UC1K @
BD14
BD12
BD10
BD7
BD3
BB32
BB20
BB1
AY27
AY26
AY25
AY23
AY22
AY21
AY20
AY19
AY18
AY16
AY15
AY14
AY13
AY12
AY11
AY10
AY8
AY7
AY6
AW28
AW5
AV32
AV28
AV26
AV23
AV21
AV19
AV16
AV14
AV12
AV10
AV7
AV5
AV1
AU28
AU25
AU22
AU20
AU18
AU15
AU13
AU11
AU8
AU5
AR32
AR28
AR26
AR21
AR19
AR16
AR14
VS S_ 25 1
VS S_ 25 2
VS S_ 25 3
VS S_ 25 4
VS S_ 25 5
VS S_ 25 6
VS S_ 25 7
VS S_ 25 8
VS S_ 25 9
VS S_ 26 0
VS S_ 26 1
VS S_ 26 2
VS S_ 26 3
VS S_ 26 4
VS S_ 26 5
VS S_ 26 6
VS S_ 26 7
VS S_ 26 8
VS S_ 26 9
VS S_ 27 0
VS S_ 27 1
VS S_ 27 2
VS S_ 27 3
VS S_ 27 4
VS S_ 27 5
VS S_ 27 6
VS S_ 27 7
VS S_ 27 8
VS S_ 27 9
VS S_ 28 0
VS S_ 28 1
VS S_ 28 2
VS S_ 28 3
VS S_ 28 4
VS S_ 28 5
VS S_ 28 6
VS S_ 28 7
VS S_ 28 8
VS S_ 28 9
VS S_ 29 0
VS S_ 29 1
VS S_ 29 2
VS S_ 29 3
VS S_ 29 4
VS S_ 29 5
VS S_ 29 6
VS S_ 29 7
VS S_ 29 8
VS S_ 29 9
VS S_ 30 0
VS S_ 30 1
VS S_ 30 2
VS S_ 30 3
VS S_ 30 4
VS S_ 30 5
VS S_ 30 6
VS S_ 30 7
VS S_ 30 8
VSS_309
AR12
VS S _2 50
AR7
VSS_249
AR5
VS S _2 48
RS V D_ 86
AN16
RS V D_ 85
AL11
RS V D_ 14
M14
RS V D_ 84
AL6
RS V D_ 87
AN29
RS V D_ 88
AN31
RS V D_ 83
AL3
RS V D_ 81
AK23
RS V D_ 82
AK27
RS V D_ 79
AJ6
RS V D_ 80
AJ24
RS V D_ 78
AF30
RS VD _70
AD3
RS VD _71
AD6
RS VD _74
AF3
RS V D_ 75
AF6
RS V D_ 69
AC29
RS V D_ 1
B20
RS V D_ 5
G3
RS V D_ 7
J20
RS V D_ 8
K3
RS V D_ 9
K6
RS V D_ 10
K20
RS V D_ 11
M3
RS V D_ 12
M6
RS V D_ 13
M13
RS V D_ 22
P6
RS V D_ 23
P22
RS V D_ 30
T3
RS V D_ 31
T6
RS V D_ 37
T29
RS V D_ 44
W6
RS V D_ 49
W21
RS V D_ 50
W22
RS V D_ 57
Y21
RS V D_ 58
Y27
RS V D_ 59
AA3
RS V D_ 60
AA6
5
BD30
4
BD26
3
BD23
2
BD21
VS S_ 31
VS S_ 31
VS S_ 31
VS S_ 31
VSS_31
1
BD19
VS S _3 10
BD16
FP5_BGA1140~D
UC1L @
T11
RSVD
RSVD_32 RSVD_6
RSV
D_6
RSVD_66 RSV
D_6
RS V D_ 55
R
SVD_56 RSVD_7
R
SVD_47 RSVD_6
R
SVD_48 RSVD_6
R
SVD_38 RSVD_3
R
SVD_39 RSVD_7
RSV
D_5
RSV
D_5
R
SVD_64 RSVD_4
R
SVD_68 RSVD_4
FP5 REV 0.90
PART 12 OF 13
2
AA9
AC7
1
AA8
5
AC6
Y9
2
AD11
Y10
W11
7
AC9
W12
3
AA11
V9
3
T12
V10
3
AD12
AA12
3
Y6
4
Y7
5
W8
A
C10
6
W9
FP5_BGA1140~D
UC1M @
A18
CAM ERAS
CAM0_CSI2_CLOCKP CAM0_CL
CA M 0_ CS I2 _ CL OC KN
CAM0_I2C_S
C
CAM0_CSI2_DATAP0 CAM0_I2C_S
D
CA M 0_ CS I2 _D AT AN 0
CAM0_SHUTDOW
CA M 0_ CS I2 _D AT AP 1
C
AM0_CSI2_DATAN1
CA M 0_ CS I2 _D AT AP 2
C
AM0_CSI2_DATAN2
CA M 0_ CS I2 _D AT AP 3
C
AM0_CSI2_DATAN3
CAM1_CSI2_CLOCKP CAM
1_CL
CA M 1_ CS I2 _ CL OC KN
CAM1_I2C_S
C
CAM1_CSI2_DATAP0 CAM1_I2C_S
D
CA M 1_ CS I2 _D AT AN 0
CAM1_SHUTDOW
CA M 1_ CS I2 _D AT AP 1
CAM1_CSI2_DATAN1 CAM_PRIV
_LE
CAM
_IR_ILL
RS V D_ 6 FP5 REV 0.90
PART 13 OF 13
K
B15
C18
L
D15
A15
A
C14
C15
N
B13
B16
K
B10
C16
C19
B18
B17
D17
D12
B12
L
A11
C13
A
C11
A13
N
D11
B11
D
D13
C12
J13
U
D10
FP5 REV 0.90
PART 7 OF 13
GND
FP5_BGA1140~D
UC1G @
K28
K22
K21
K19
K16
K5
K1
H28
H25
H22
H20
H18
H13
G32
G28
G23
G21
G19
G16
G5
G1
F28
F5
E27
E26
E25
E23
E21
E20
E19
E18
E16
E15
E14
E13
E12
E11
E10
E8
E7
D20
D18
D16
C32
C3
A26
A23
A21
A19
A16
A14
A12
A10
A7
A3
VS S _1
A5
VS S _2
VSS_3
VSS_4
VS S_ 5
VS S_ 6
VSS_7
VSS_8
VSS_9
VSS_1 0
VSS_11
A30
VS S _1 2
VSS_1 3
VSS_14
VS S_ 15
VS S_ 16
VSS_17
VSS_1 8
VSS_19
VS S_ 20
VS S_ 21
VSS_22
VSS_2 3
VSS_24
VS S_ 25
VS S_ 26
VSS_27
VSS_2 8
VSS_29
VS S _3 0
E22
VS S _3 1
VS S _3 2
VS S_ 33
VS S_ 34
VS S_ 35
VS S_ 36
VS S_ 37
VS S_ 38
VS S_ 39
VS S_ 40
VS S_ 41
VS S_ 42
VSS_43
G26
VS S _4 4
VSS_4 5
VSS_46
H5
VS S _4 7
VSS_4 8
VSS_49
VS S_ 50
VS S_ 51
VSS_52
VSS_5 3
VSS_54
VS S_ 55
VS S_ 56
VSS_57
VSS_5 8
VSS_59
K26
VS S _6 0
VS S _6 1
N12
VS S _3 16
2
U19
1
U17
0
U15
9
U13
8
T28
7
T26
6
T23
5
T20
4
T18
3
T16
2
T14
9
R30
8
R28
7
R25
6
R22
5
R19
4
R17
3
R15
2
R13
1
R12
VS S_ 10
VS S_ 10
VS S_ 10
VS S_ 10
VS S_ 10
VS S_ 10
VS S_ 10
VS S_ 10
VS S_ 10
VSS_10
VS S _1 10
T1
VS S _1 11
T5
VS S_ 11
VS S_ 11
VSS_11
VSS_1 1
VSS_11
VS S_ 11
VS S_ 11
VSS_11
VSS_1 2
VSS_12
VS S _1 2
VS S _1 23
V5
0
R11
R5
VSS_99
P32
VSS_98
P28
VSS_97
P26
VSS_96
P23
VSS_95
P20
VSS_94
VS S _9 3
P18
P16
VSS_92
P14
VSS_91
P5
VSS_90
P1
VSS_89
N28
VSS_88
N25
VSS_87
N22
VSS_86
N19
VSS_85
N17
VSS_84
N15
VSS_83
N13
VSS_82
N11
VSS_81
N8
VSS_80
N5
VSS_79
N4
VSS_78
M32
VSS_77
M28
VSS_76
M26
VSS_75
VS S _7 4
M23
M21
VSS_73
M12
VSS_72
M5
VSS_71
M1
VSS_70
L28
VSS_69
L25
VSS_68
L20
VSS_67
L18
VSS_66
L15
VSS_65
VS S _6 4
L13
L5
VSS_63
VS S _6 2
K32
FP5 REV 0.90
PART 8 OF 13
GND
FP5_BGA1140~D
UC1H @
AG5
AF20
AF18
AF16
AF14
AF5
AF1
AE19
AE17
AE15
AE13
AE12
AE11
AE5
AD20
AD18
AD16
AD14
AD5
AD1
AC19
AC17
AC15
AC13
AC12
AC11
AC8
AC5
AB20
AB18
AB16
AB14
AA19
AA17
AA15
AA13
AA5
AA1
Y20
Y18
Y16
Y14
Y12
Y11
Y5
W26
W23
W19
W17
W13
W5
W1
V25
V22
V20
V18
V16
V14
V11
VS S _1 25
V12
VS S _1 26
VSS_1 27
VSS_128
VS S_ 12 9
VS S_ 13 0
VSS_131
VSS_1 32
VSS_133
VSS_1 34
VSS_135
W15
VS S _1 36
VSS_1 37
VSS_138
VS S_ 13 9
VS S_ 14 0
VSS_141
VSS_1 42
VSS_143
VS S_ 14 4
VS S_ 14 5
VSS_146
VSS_1 47
VSS_148
VS S_ 14 9
VS S_ 15 0
VSS_151
VSS_1 52
VSS_153
VS S_ 15 4
VS S_ 15 5
VSS_156
VSS_1 57
VSS_158
VS S_ 15 9
VS S_ 16 0
VSS_161
VSS_1 62
VSS_163
VS S_ 16 4
VS S_ 16 5
VSS_166
VSS_1 67
VSS_168
VS S_ 16 9
VS S_ 17 0
VSS_171
VSS_1 72
VSS_173
VS S_ 17 4
VS S_ 17 5
VSS_176
VSS_1 77
VSS_178
VS S_ 17 9
VS S_ 18 0
VSS_181
VSS_1 82
VSS_183
VSS_1 84
VSS_185
V8
VS S _1 24
VS S _2 4
VS S _2 47
AR1
6
AP28
VS S _2 45
AP25
4
AP20
3
AP18
2
AP15
1
AP13
0
AP8
9
AP5
8
AN32
7
AN28
6
AN26
5
AN23
4
AN21
3
AN18
2
AN15
1
AN10
0
AN7
9
AN5
8
AN1
7
AM28
6
AM25
5
AM22
4
AM20
3
AM15
2
AM8
1
AM5
0
AL26
9
AL23
8
AL16
7
AL12
6
AL10
5
AL7
VS S_ 21
VS S_ 21
VS S_ 21
VS S_ 21
VS S_ 21
VS S_ 21
VS S_ 22
VS S_ 22
VS S_ 22
VS S_ 22
VS S_ 22
VS S_ 22
VS S_ 22
VS S_ 22
VS S_ 22
VS S_ 22
VS S_ 23
VS S_ 23
VS S_ 23
VS S_ 23
VS S_ 23
VS S_ 23
VS S_ 23
VS S_ 23
VS S_ 23
VS S_ 23
VS S_ 24
VS S_ 24
VS S_ 24
VS S_ 24
VSS_24
4
AL5
2
AK25
1
AK22
0
AK20
9
AK18
8
AK16
7
AK14
6
AK12
5
AK11
4
AK8
3
AK5
2
AJ19
1
AJ17
0
AJ15
9
AJ13
8
AJ5
7
AJ1
6
AH20
5
AH18
4
AH16
3
AH14
2
AG19
1
AG17
0
AG15
9
AG13
8
AG12
VS S_ 18
VS S_ 18
VS S_ 18
VS S_ 19
VS S_ 19
VS S_ 19
VS S_ 19
VS S_ 19
VS S_ 19
VS S_ 19
VS S_ 19
VS S_ 19
VS S_ 19
VS S_ 20
VS S_ 20
VS S_ 20
VS S_ 20
VS S_ 20
VS S_ 20
VS S_ 20
VS S_ 20
VS S_ 20
VS S_ 20
VS S_ 21
VS S_ 21
VSS_21
VSS_213 AL1
7
AG11
VS S _1 86
AG8
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Memory Side
VREF traces should be at least 20mils wide
20mils spacing to other signals
DRAM DOWN DECOU PLING
Closed toUD1 Closed to UD2 Closed toU D3
Closed toUD4
DDR4 - MEMORY DOWN (MEMORY CHANNEL A, x16 x4 PCS)
DDR_A_RST#
DDR_A_PAR
DDR_A_ALERT#
DDR_A_WE#
DDR_A_CKE0
DDR_A_CLK0
DDR_A_CLK0#
DDR_A_RAS#
DDR_A_ODT0
DDR_A_CS0#
DDR_A_BA0
DDR_A_BA1
DDR_A_CAS#
DDR_A_RST#
DDR_A_PAR
DDR_A_ALERT#
DDR_A_PAR
DDR_A_ALERT#
DDR_A_RST#
DDR_A_BG1_R DDR_A_BG1_R
DDR_A_DQ[63..0]
DDR_A_MA12
DDR_A_MA13
DDR_A_MA11
DDR_A_MA10
DDR_A_MA6
DDR_A_MA7
DDR_A_MA2
DDR_A_MA3
DDR_A_MA8
DDR_A_MA5
DDR_A_MA4
DDR_A_MA9
DDR_A_MA0
DDR_A_MA1
DDR_A_MA12
DDR_A_MA13
DDR_A_MA11
DDR_A_MA10
DDR_A_MA6
DDR_A_MA7
DDR_A_MA2
DDR_A_MA3
DDR_A_MA8
DDR_A_MA5
DDR_A_MA4
DDR_A_MA9
DDR_A_MA0
DDR_A_MA1
DDR_A_MA12
DDR_A_MA13
DDR_A_MA11
DDR_A_MA10
DDR_A_MA6
DDR_A_MA7
DDR_A_MA2
DDR_A_MA3
DDR_A_MA8
DDR_A_MA5
DDR_A_MA4
DDR_A_MA9
DDR_A_MA0
DDR_A_MA1
DDR_A_WE# DDR_A_WE#
DDR_A_BA0
DDR_A_BA1
DDR_A_BA0
DDR_A_BA1
DDR_A_BG1_R DDR_A_BG1_R
DDR_A_ACT#
DDR_A_BG0
DDR_A_ACT#
DDR_A_BG0
DDR_A_DM1
DDR_A_DM0
DDR_A_DM3
DDR_A_DM2
DDR_A_DM5
DDR_A_DM4
DDR_A_DM7
DDR_A_DM6
DDR_A_CKE0
DDR_A_CLK0
DDR_A_CLK0#
DDR_A_CKE0
DDR_A_CLK0
DDR_A_CLK0#
DDR_A_ODT0
DDR_A_CS0#
DDR_A_ODT0
DDR_A_CS0#
DDR_A_DM[7..0]
DDR_A_DQ12
DDR_A_DQ16
DDR_A_DQ25
DDR_A_DQ44
DDR_A_DQ48
DDR_A_DQ1
DDR_A_DQ32
DDR_A_DQ56
DDR_A_RAS#
DDR_A_CAS#
DDR_A_RAS#
DDR_A_CAS#
<5> DDR_A_RST#
<5>DDR_A_BA0
<5>DDR_A_BA1
<5> DDR_A_CLK0
<5> DDR_A_CLK0#
<5> DDR_A_CKE0
<5>DDR_A_ODT0
<5> DDR_A_CS0#
<5>DDR_A_RAS#
<5>DDR_A_CAS#
<5> DDR_A_BG0
<5> DDR_A_ACT#
<5> DDR_A_MA0
<5>DDR_A_MA1
<5>DDR_A_MA2
<5>DDR_A_MA3
<5>DDR_A_MA4
<5>DDR_A_MA5
<5>DDR_A_MA6
<5>DDR_A_MA7
<5>DDR_A_MA8
<5>DDR_A_MA9
<5>DDR_A_MA10
<5>DDR_A_MA11
<5>DDR_A_MA12
<5>DDR_A_MA13
<5> DDR_A_WE#
<5> DDR_A_DQS1#
<5> DDR_A_DQS1
<5> DDR_A_DQS0#
<5> DDR_A_DQS0
<5> DDR_A_DQS3#
<5> DDR_A_DQS3
<5> DDR_A_DQS2#
<5> DDR_A_DQS2
<5> DDR_A_DQS5#
<5> DDR_A_DQS5
<5> DDR_A_DQS4#
<5> DDR_A_DQS4
<5> DDR_A_DQS7#
<5> DDR_A_DQS7
<5> DDR_A_DQS6#
<5> DDR_A_DQS6
<5> DDR_A_ALERT#
<5> DDR_A_PAR
DDR_A_DQ[63..0]<5>
DDR_A_DM[7..0]<5>
DDR_A_BG1 <5>
+1.2V
+1.2V
+0.6VS
+0.6VS
+1.2V
+1.2V
+1.2V
+0.6VS
+1.2V+1.2V
+1.2V+1.2V
+2.5V +2.5V +2.5V +2.5V
+0.6VS
+1.2V
+2.5V +2.5V
+2.5V +2.5V
+0.6V_DDRA_VREFCA
+0.6V_DDRA_VREFCA +0.6V_DDRA_VREFCA
+0.6V_DDRA_VREFCA +0.6V_DDRA_VREFCA
+0.6V_DDRA_VREFCA
Tiiitttllle
Siiize Documenttt Numberrr
LA-H131P
Re v
0...4
Sheettt 12 o fff46Dattte::: Monday,,, Novemberrr 05,,,2018
Securiiittty Clllassiiifffiiicatttiiion Compalll Secret Data
IsII suedDatett
2018///11///05
Deciiiphererr d Dattte
2019///11///05
THIS SHEET OF ENGINEII ERING DRAWING ISII THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,,, INC.II AND CONTAINSII CONFIDENTIALII AND TRADE SECRET
INFOII RMATIOII N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISII IOII N OF R&D DEPARTME NT EXCEPT AS
AUTHORIZED BY COMPAL ELECTRONICS,,, INC.II NEITII HER THIS SHEET NOR THE INFOII RMATIOII N ITII CONTAINSII
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,,,INC.II
Compal Electronics, Inc.
DDR4_CHAOnboard
RD14 1 OBR@ 2 39_0402_5%
DDR_A_MA11
CD47 OBR@
10U 6.3V M X5R0402
1
2
CD5
0.1U_0201_10V6K
@
1
2
CD52 @
1U_0201_6.3V6
M
CD13 0.22U_0402_6.3V6KOBR@
CD43 OBR@
1U_0201_6.3V6
M
1
2
CD8
.047U_0402_16V7K
OBR@
1
2
RD15 1 OBR@ 2 39_0402_5%
DDR_A_MA12
CD17 0.22U_0402_6.3V6KOBR@
CD19 0.22U_0402_6.3V6KOBR@
CD51 OBR@
1U_0201_6.3V6
M
1
2
RD30 1 DDP@ 2 0_0201_5%
RD5 1 OBR@ 2 39_0402_5%
DDR_A_MA2
RD16 1 OBR@ 2 39_0402_5%
DDR_A_MA13
CD24 0.22U_0402_6.3V6KOBR@
CD30 0.22U_0402_6.3V6K@
CD53 OBR@
10U 6.3V M X5R0402
1 1
2 2
@
CD4 12 0.1U_0201_10V6K
RD4 1 OBR@ 2 39_0402_5%
DDR_A_MA1
UD2
K4A8G165WB-BCPB_FBGA96
SA00008Z000
@
CAS
M8
RAS
L8
CS
CKE
K7
K2
CK_c
K8
CK_t
N2
BA1
N8
BA0
N7
A2
N3
A3
P8
A4
P2
A5
R8
A6
R2
A7
R7
A8
M3
A9
T2
A10/AP
G2
DQL0F7DDR_A_DQ19 DQL1
H3
DDR_A_DQ21 DQL2
H7
DDR_A_DQ22 DQL3
H2
DDR_A_DQ20
DQL4
H8
DDR_A_DQ23
DQL5
J3
DDR_A_DQ17
DQL7
DQL6 J7DDR_A_DQ18
C9
B2
E9
E1
L3
ACT
B3
B9
A1
A9
C1
D9
M2
T7
F8
F9
ZQ
RESET
P1
A2
A8
D2
D8
E3
B7
DQSU_c
A7
G1
E8
F1
G9
J2
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
H1
VREFCA
M1
G8
D1
L7
ODT
K3
P3
R3
A1
P7
A0
G7
M7
A11
K1
DQU7
DQU6 D7DDR_A_DQ27
DQU0B8DDR_A_DQ31 D QU1
C3
DDR_A_DQ30 DQ U2
C7
DDR_A_DQ26 DQ U3
C2
DDR_A_DQ24 DQ U4
C8
DDR_A_DQ29 DQ U5
D3
DDR_A_DQ28
A3
T8
A12/BC
A14/WE
L2
A13
B1
NC
J8
VPP
VPP
R9
J9
L1
L9
R1
K9
N1
VSS
VSS
VSS
VSS
VSS
VSS
M9
VSS
VSS
VSS
T1
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
F2
VDD
VDD
VDD
VDD
J1
VDD
VDD
VDD
VDD
VDD
VDD
T9
96-BALL
VSSQ
SDRAM DDR4
H9
F3
DQSU_t
DQSL_t
G3
DQSL_c
E2
DML/DBIL
E7
DMU/DBIU
N9
BG0
P9
TEN
ALERT
PAR
T3
240_0201_1%
DDR_A_ACT#
DDR_A_BG0
RD36 1 OBR@2
RD19 1 OBR@ 2 39_0402_5%
DDR_A_RAS#
CD18 0.22U_0402_6.3V6KOBR@
RD7 1 OBR@ 2 39_0402_5%
DDR_A_MA4
RD39 1 DDP@2 0_ 0201_5%
1 2
RD17 1 OBR@ 2 39_0402_5%
DDR_A_WE#
RD32
1K_0402_1%
OBR@
1 2
CD14 0.22U_0402_6.3V6KOBR@
CD44@
10U 6.3V M X5R0402
1
2
CD20 0.22U_0402_6.3V6KOBR@
CD25 0.22U_0402_6.3V6KOBR@
CD31 0.22U_0402_6.3V6KOBR@
UD1
K4A8G165WB-BCPB_FBGA96
SA00008Z000
@
CAS
M8
RAS
L8
CS
CKE
K7
K2
CK_c
K8
CK_t
N2
BA1
N8
BA0
N7
A2
N3
A3
P8
A4
P2
A5
R8
A6
R2
A7
R7
A8
M3
A9
T2
A10/AP
G2
DQL0F7DDR_A_DQ7 DQL1
H3
DDR_A_DQ4 DQL2H7DDR_A_DQ6
DQL3H2DDR_A_DQ5 DQL4
H8
DDR_A_DQ3 DQL5J3DDR_A_DQ0
DQL7
DQL6 J7DDR_A_DQ2
B2
VSS
E9
VSS
E1
L3
ACT
B3
VDD
B9
A1
VDDQ
A9
VDDQ
C1
VDDQ
D9
M2
T7
F9
ZQ
RESET
P1
VSSQ
C9
A2
VSSQ
A8
VSSQ
D2
VSSQ
D8
VSSQ
E3
B7
DQSU_c
A7
VDDQ
G1
VSSQ
E8
VDDQ
G9
VDDQ
J2
VREFCA
M1
VSS
G8
VDD
D1
L7
ODT
K3
P3
R3
A1
P7
A0
VDD
G7
M7
A11
VSS
K1
VDD
J1
DQU7
DQU6 D7DDR_A_DQ10
DQU0B8DDR_A_DQ11 D QU1
C3
DDR_A_DQ9 DQU2C7DDR_A_DQ14
DQU3C2DDR_A_DQ8 DQU4
C8
DDR_A_DQ15 DQ U5
D3
DDR_A_DQ13
A3
T8
A12/BC
A14/WE
L2
A13
B1
NC VSSQ
F1
VDDQ
VDDQ
J8
R9
VPP VSSQ
H1
VDD
J9
VDD
L1
VDD
L9
VDD
R1
VSS
K9
VSS
M9
VSS
N1
VSS
VSS
T1
VDDQ
F8
VDDQ
F2
VDD
VDD
T9
96-BALL
VSSQ
SDRAM DDR4
VPP VSSQ
H9
F3
DQSU_t
DQSL_t
G3
DQSL_c
E2
DML/DBIL
E7
DMU/DBIU
N9
BG0
P9
TEN
PAR
T3
ALERT
RD3 1 OBR@2 39_0402_5%
DDR_A_MA0
RD31 1 SDP@2 0_0201_5%
DDR_A_BG1_R
CD10 0.22U_0402_6.3V6KOBR@
RD18 1 OBR@ 2 39_0402_5%
DDR_A_CAS#
RD34 1 DDP@2 0_ 0201_5%
RD8 1 OBR@ 2 39_0402_5%
DDR_A_MA5
2 0.22U_0402_6.3V6K OBR@
UD3
K4A8G165WB-BCPB_FBGA96
SA00008Z000
@
L8
M8
K2
K7
K8
N2
N8
R3
N7
P2
R8
R2
R7
M3
G2
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
F7
DDR_A_DQ39
H3
DDR_A_DQ33
H7
DDR_A_DQ37
H2
DDR_A_DQ38
H8
DDR_A_DQ35
J3
DDR_A_DQ36
J7
DDR_A_DQ34
C9
B2
E9
E1
B3
B9
A1
A9
C1
D9
L3
M2
F8
ZQ
F9
P1
A2
A8
D2
D8
E3
A7
B7
G1
E8
F1
G9
J2
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
H1
M1
G8
D1
ODT
CS
RAS
CAS
K3
L7
P3
P7
G7
T2
M7
K1
J1
B8
DDR_A_DQ42
C3
DDR_A_DQ45
C7
DDR_A_DQ47
C2
DDR_A_DQ40
C8
DDR_A_DQ43
D3
DDR_A_DQ41
D7
DDR_A_DQ46
A3
VREFCA
A0
A1
A2
N3
A3
P8
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14/WE
T8
L2
T7
B1
J8
R9
J9
L1
L9
R1
K9
M9
N1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
T1
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
F2
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
T9
96-BALL
VSSQ
SDRAM DDR4
H9
DQSU_c
DQSU_t
DQSL_c
DQSL_t
RESET
F3
G3
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
BA0
BA1
DMU/DBIU
DML/DBIL
CK_t
CK_c
CKE
E2
E7
N9
P9
ACT
BG0
TEN
ALERT
PAR
NC
VPP
VPP
T3
CD11 0.22U_0402_6.3V6KOBR@
RD20 1 OBR@ 2 39_0402_5%
DDR_A_ODT0
CD32 0.22U_0402_6.3V6KOBR@
RD6 1 OBR@ 2 39_0402_5%
DDR_A_MA3
CD1.047U_0402_16V7K
OBR@
1
2
OBR@
CD3 12 0.1U_0201_10V6K RD28 1 OBR@2 39_0402_5%
DDR_A_CLK0
2 0.22U_0402_6.3V6KOBR@
RD21 1 OBR@2 39_0402_5%
DDR_A_CS0#
CD21 0.22U_0402_6.3V6KOBR@
CD26 0.22U_0402_6.3V6KOBR@
240_0201_1%
RD40 1 OBR@2
CD15 0.22U_0402_6.3V6KOBR@
UD4
K4A8G165WB-BCPB_FBGA96
SA00008Z000
@
CAS
M8
RAS
L8
CS
CKE
K7
K2
CK_c
K8
CK_t
N2
BA1
N8
BA0
N7
A2
N3
A3
P8
A4
P2
A5
R8
A6
R2
A7
R7
A8
M3
A9
T2
A10/AP
G2
DQL0F7DDR_A_DQ51 DQL1
H3
DDR_A_DQ49 DQL2
H7
DDR_A_DQ55 DQL3
H2
DDR_A_DQ53
DQL4
H8
DDR_A_DQ50
DQL5
J3
DDR_A_DQ52
DQL7
DQL6 J7DDR_A_DQ54
C9
B2
E9
E1
L3
B3
B9
A1
A9
C1
D9
M2
ACT
T7
F8
ZQ
F9
P1
A2
A8
D2
D8
E3
B7
DQSU_c
A7
G1
E8
F1
G9
J2
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
H1
VREFCA
M1
G8
D1
L7
ODT
K3
P3
R3
A1
P7
A0
G7
M7
A11
K1
J1
DQU7
DQU6 D7DDR_A_DQ59
DQU0B8DDR_A_DQ62 D QU1
C3
DDR_A_DQ60 DQ U2
C7
DDR_A_DQ63 DQ U3
C2
DDR_A_DQ57 DQ U4
C8
DDR_A_DQ58 DQ U5
D3
DDR_A_DQ61
A3
T8
A12/BC
A14/WE
L2
A13
B1
NC
J8
VPP
VPP
R9
J9
L1
L9
R1
K9
M9
N1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
T1
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
F2
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
T9
96-BALL
VSSQ
SDRAM DDR4
H9
F3
DQSU_t
DQSL_t
RESET
G3
DQSL_c
E2
DML/DBIL
E7
DMU/DBIU
N9
BG0
P9
TEN
ALERT
PAR
T3
RD27 1 DDP@ 2 39_0402_5%
2 0.22U_0402_6.3V6KOBR@
RD10 1 OBR@ 2 39_0402_5%
DDR_A_MA7
RD22 1 OBR@ 2 39_0402_5%
DDR_A_CKE0
RD37 CD7
1K_0402_1% 0.1U_0201_10V6K
OBR@ OBR@
1
2
CD9
.047U_0402_16V7K
OBR@
1
2
RD1 1 OBR@2 1K_0402_5%
DDR_A_ALERT#
2 0.22U_0402_6.3V6KOBR@
RD9 1 OBR@ 2 39_0402_5%
DDR_A_MA6
RD25 1 OBR@2 39_0402_5%
DDR_A_BA1
CD6
0.1U_0201_10V6K
OBR@
1
2
CD3
3
1
CD3
5
1
CD3
7
1
CD3
9
1
CD4
1
1
2 0.22U_0402_6.3V6KOBR@
CD22 0.22U_0402_6.3V6KOBR@
CD28 0.22U_0402_6.3V6KOBR@
240_0201_1%
RD35 1 OBR@2
CD12 0.22U_0402_6.3V6KOBR@
RD13 1 OBR@ 2 39_0402_5%
DDR_A_MA10
CD27 0.22U_0402_6.3V6KOBR@
RD23 1 OBR@2 39_0402_5%
DDR_A_ACT#
CD49 OBR@
1U_0201_6.3V6
M
1
2
RD11 1 OBR@ 2 39_0402_5%
DDR_A_MA8
CD46 OBR@
1U_0201_6.3V6
M
1
2
CD16 0.22U_0402_6.3V6KOBR@
RD26 1 OBR@ 2 39_0402_5%
DDR_A_BG0
RD29 1 OBR@2 39_0402_5%
DDR_A_CLK0#
RD38 1 DDP@2 0_0201_5%
RD33 1 DDP@2 0_ 0201_5%
CD48 OBR@
1U_0201_6.3V6
M
1
2
CD42 OBR@
1U_0201_6.3V6
M
1
2
RD12 1 OBR@ 2 39_0402_5%
DDR_A_MA9
CD34 1 2 0.1U_0201_10V6K OBR@
CD36 1 2 0.1U_0201_10V6K OBR@
CD38 1 2 0.1U_0201_10V6K OBR@
CD40 1 2 0.1U_0201_10V6K OBR@
CD23 0.22U_0402_6.3V6KOBR@
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
CD45 @
1U_0201_6.3V6
M
1
2
RD24 1 OBR@2 39_0402_5%
DDR_A_BA0
CD2
.047U_0402_16V7K
OBR@
1
2
RD2 1 OBR@ 2 39_0402_5%
DDR_A_PAR
240_0201_1%
RD41 1 OBR@2
CD29 0.22U_0402_6.3V6K@
1 1 1 1 1
2 2 2 2 2
CD50@
10U 6.3V M X5R0402
1
2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Layout Note:
Place near JDIMM1.257,259
Layout Note:
Place near JDIMM1.258
DIMM Side
ESD
DDR4 - SO-DIMM (MEMORY CHANNEL B)
DDR_B_DQ48
DDR_B_DQ53
DDR_B_DQ42
DDR_B_DQ43
DDR_B_DQ51
DDR_B_DQ61
DDR_B_DQ0
DDR_B_DQ50
DDR_B_DQ58
DDR_B_DQ45
DDR_B_DQ46
DDR_B_DQ54
DDR_B_DQ55
DDR_B_DQ56
DDR_B_DQ57
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7
DDR_B_BG0
DDR_B_BG1
DDR_B_CLK0
DDR_B_CLK0#
DDR_B_BA1
DDR_B_ODT0
DDR_B_ODT1
DDR_B_WE#
DDR_B_CAS#
DDR_B_RAS#
DDR_B_BA0
DDR_B_CLK1
DDR_B_CLK1#
DDR_B_EVENT#
DDR_B_ACT#
DDR_B_PAR
DDR_B_ALERT#
DDR_B_MA4
DDR_B_MA5
DDR_B_MA2
DDR_B_DQ14
DDR_B_MA0
DDR_B_MA1
DDR_B_DQ23
DDR_B_DQ5
DDR_B_DQ7
DDR_B_DQ1
DDR_B_DQ4
DDR_B_DQS0#
DDR_B_DQS2
DDR_B_DQS2#
DDR_B_DQS1#
DDR_B_DQS1
DDR_B_DQS3#
DDR_B_DQ2
DDR_B_DQS0
DDR_B_DQS5#
DDR_B_DQ47
DDR_B_DQS5
DDR_B_DQS7
DDR_B_DQS7#
DDR_B_DQS6
DDR_B_DQS6#
DDR_B_DQS4
DDR_B_DQS4#
DDR_B_MA13
DDR_B_DQ3
DDR_B_DQ6
DDR_B_DQ31
DDR_B_DQS3
DDR_B_DQ8
DDR_B_DQ9
DDR_B_DQ12
DDR_B_DQ13
DDR_B_DQ11
DDR_B_DQ15
DDR_B_DQ62
DDR_B_DQ63
DDR_B_DQ59
DDR_B_DQ60
DDR_B_RST#
DDR_B_CKE0
DDR_B_CKE1
DDR_B_DQ10
DDR_B_DQ20
DDR_B_DQ22
DDR_B_DQ40
DDR_B_DQ41
DDR_B_DM2
DDR_B_DM0
DDR_B_DM1
DDR_B_DM3
DDR_B_DM4
DDR_B_DQ21
DDR_B_DQ16
DDR_B_DQ35
DDR_B_DQ37
DDR_B_DQ18
DDR_B_DQ19
DDR_B_DQ17
DDR_B_DQ36
DDR_B_DQ52
DDR_B_DQ49
DDR_B_DQ24
DDR_B_DQ29
DDR_B_DQ32
DDR_B_DQ33
DDR_B_DQ25
DDR_B_DQ28
DDR_B_DQ38
DDR_B_DQ39
DDR_B_DQ30
DDR_B_DQ34
DDR_B_DQ26
DDR_B_DQ27
DDR_B_DQ44
DDR_B_MA11
DDR_B_MA12
DDR_B_MA9
DDR_B_MA10
DDR_B_MA8
DDR_B_MA6
DDR_B_MA7
DDR_B_MA3
DDR_B_DQ[0..63]
DDR_B_DM[0..7]
DDR_B_MA[0..13]
+VREFB_CA
DDR_B_RST#
DDR_B_CS0#
DDR_B_CS1#
<5> DDR_B_ODT0
<5> DDR_B_ODT1
<5> DDR_B_WE#
<5> DDR_B_CAS#
<5> DDR_B_RAS#
<5> DDR_B_BG0
<5> DDR_B_BG1
<5> DDR_B_BA0
<5> DDR_B_BA1
<5> DDR_B_CLK0
<5> DDR_B_CLK0#
<5> DDR_B_CLK1
<5> DDR_B_CLK1#
<5>DDR_B_ACT#
<8> I2C_2_SDA
<8> I2C_2_SCL
DDR_B_DQS3 <5>
DDR_B_DQS3# <5>
DDR_B_DQS1 <5>
DDR_B_DQS1# <5>
DDR_B_DQS5 <5>
DDR_B_DQS5# <5>
DDR_B_DQS7 <5>
DDR_B_DQS7# <5>
DDR_B_DQS0 <5>
DDR_B_DQS0# <5>
DDR_B_DQS2 <5>
DDR_B_DQS2# <5>
DDR_B_DQS4 <5>
DDR_B_DQS4# <5>
DDR_B_DQS6 <5>
DDR_B_DQS6# <5>
<5>DDR_B_PAR
<5> DDR_B_ALERT#
<5> DDR_B_EVENT#
<5>DDR_B_RST#
<5> DDR_B_CKE0
<5> DDR_B_CKE1
DDR_B_DQ[0..63] <5>
DDR_B_DM[0..7]<5>
DDR_B_MA[0..13]<5>
<5> DDR_B_CS0#
<5> DDR_B_CS1#
+3VS
+1.2V
+1.2V
+VREFB_CA
+3VS
+2.5V
+0.6VS
+1.2V+1.2V
+2.5V
+0.6VS
+1.2V
+VREFB_CA
+3VS
Tiiitttllle
Siiize Documenttt Number
Sheettt
Securiiity Clllassiiifiiicatiiion
Compal SecretData
THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL AND
TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIION OF R&D DEPARTMENT
EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IIINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIIT CONTAIIINS
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IIINC...
Issued Date
Decipherii ed Date
LA-H131P
Rev
0...4
DDR4SO-DIMM
C
13 o fff 46Dattte::: Monday,,, November 05,,,2018
2018/11/05 2019/11/05
Compal Electronics,Inc.
100P_0402_50V8J
1 2
CD69 ESD@
CD78
2.2U_0402_6.3V6
M
1
2
CD55 NO_OBR@
10U 6.3V M X5R 0402
1
2
RD42
1K_0402_1%
1 2
CD79 @
0.1U_0201_10V6
K
1
2
CD75
10U 6.3V M X5R 0402
1
2
1
+
CD68
330U_D3_2.5VY_R6M
@
2
CD80
0.1U_0201_10V6
K
1
2
CD61
1U_0201_6.3V6
M
12
RD43
1K_0402_1%
1 2
CD59 NO_OBR@
10U 6.3V M X5R 0402
1
2
REVE RSE
JDIMM1A
LOTES_ADDR0205-P001A02~D
SP07001HW0L
ME@
114
116
150
145
115
113
139
137
140
138
109
110
12
33
54
75
178
199
220
DM0#/DBI0#
DM1#/DBI1#
DM2#/DBI2#
DM3#/DBI3#
DM4#/DBI4#
DM5#/DBI5#
DM6#/DBI6#
DM7#/DBI7#
241
96
CB0_NC
CB1_NC
CB2_NC
CB3_NC
CB4_NC
CB5_NC
CB6_NC
CB7_NC
DQS8(T)
DQS8#(C)
92
91
101
105
88
87
100
104
97
95
155
ODT0
ODT1
BG0
BG1
BA0
BA1
161
143
149
157
253
144
133
146
120
119
158
151
156
152
132
131
128
126
127
122
125
121
8
7
41
42
24
25
38
37
50
49
62
63
20
46
45
58
59
70
71
83
84
66
67
21
79
80
174
173
187
186
170
169
183
182
4
195
194
207
208
191
190
203
204
216
215
3
228
229
211
212
224
225
237
236
249
250
16
232
233
245
246
17
28
29
11
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS0(T)
DQS0#(C)
13
32
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS1(T)
DQS1#(C)
34
53
A0
A1 DQ16
A2 DQ17
A3 DQ18
A4 DQ19
A5 DQ20
A6 DQ21
A7 DQ22
A8 DQ23
A9 DQS2(T)
A10_AP DQS2#(C)
A11
A12
A13
A14_WE#
A15_CAS#
A16_RAS#
ACT#
55
74
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQS3(T)
DQS3#(C)
76
177
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS4(T)
DQS4#(C)
179
198
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQS5(T)
DQS5#(C)
200
DM8#/DBI8# DQS6#(C)
219
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQS6(T)
221
240
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQS7(T)
DQS7#(C)
242
134
PARITY
ALERT#
EVENT#
RESET#
108
CK0(T)
CK0#(C)
CK1(T)
CK1#(C)
CKE0
CKE1
S0#
S1#
S2#/C0
S3#/C1
162
165
256
260
166
SDA
SCL
SA2
SA1
SA0
254
CD77
0.1U_0201_10V6
K
1
2
CD76 @
10U 6.3V M X5R 0402
1
2
CD72
1U_0201_6.3V6
M
2 1
CD57
10U 6.3V M X5R 0402
1
2
CD62
1U_0201_6.3V6
M
12
CD60
1U_0201_6.3V6
M
12
CD63
1U_0201_6.3V6
M
12
CD81
1000P_0402_50V
7K
1
2
CD73
0.1U_0201_10V6
K
@
1
2
CD64
1U_0201_6.3V6
M
12
CD74
1U_0201_6.3V6
M
1
2
REVE RSE
JDIMM1B
LOTES_ADDR0205-P001A02~D
SP07001HW0L
ME@
111
112
VDD1
117
VDD2
118
VDD3
123
VDD4
124
VDD5
129
VDD6
130
VDD7
135
VDD8
VDD10
136
VDD9
VDDSPD
255
VREFCA
164
1
2
VSS1
5
VSS2
6
VSS3
9
VSS4
10
VSS5
14
VSS6
15
VSS7
18
VSS8
19
VSS9
22
VSS10
23
VSS11
26
VSS12
27
VSS13
30
VSS14
31
VSS15
35
VSS16
36
VSS17
39
VSS18
40
VSS19
43
VSS20
44
VSS21
47
VSS22
48
VSS23
51
VSS24
52
VSS25
56
VSS26
57
VSS27
60
VSS28
61
VSS29
64
VSS30
65
VSS31
68
VSS32
69
VSS33
72
VSS34
73
VSS35
77
VSS36
78
VSS37
81
VSS38
82
VSS39
85
VSS40
86
VSS41
89
VSS42
90
VSS43
93
VSS44
94
VSS45
VSS47
98
VSS46
262
141
VDD11
142
VDD12
147
VDD13
148
VDD14
153
VDD15
154
VDD16
159
VDD17
160
VDD19
VDD18
163
VTT
258
257
VPP2
VPP1
259
99
VSS48
102
VSS49
103
VSS50
106
VSS51
107
VSS52
167
VSS53
168
VSS54
171
VSS55
172
VSS56
175
VSS57
176
VSS58
180
VSS59
181
VSS60
184
VSS61
185
VSS62
188
VSS63
189
VSS64
192
VSS65
193
VSS66
196
VSS67
197
VSS68
201
VSS69
202
VSS70
205
VSS71
206
VSS72
209
VSS73
210
VSS74
213
VSS75
214
VSS76
217
VSS77
218
VSS78
222
VSS79
223
VSS80
226
VSS81
227
VSS82
230
VSS83
231
VSS84
234
VSS85
235
VSS86
238
VSS87
239
VSS88
243
VSS89
244
VSS90
247
VSS91
248
VSS92
251
VSS94
VSS93
252
GND1 GND2
261
CD54
10U 6.3V M X5R 0402
1
2
CD65 NO_OBR@
1U_0201_6.3V6M
12
CD56
10U 6.3V M X5R 0402
1
2
CD67 NO_OBR@
1U_0201_6.3V6M
12
CD71
10U 6.3V M X5R 0402
@
1
2
CD58 NO_OBR@
10U 6.3V M X5R 0402
1
2
CD66 NO_OBR@
1U_0201_6.3V6M
12
CD70
10U 6.3V M X5R 0402
1
2
5
5
4
4
3 2 1
1
D D
C C
B B
A A
From EC
W=20mils
eDP
W=20mils
W=60mils
Camera
Touch Screen
Microphone
EDP CONNECTOR
LCD POWER SWITCH
CAMERA POWER CIRCUIT
DISPLAY OFF
ESD COMPONENTS
DISPOFF#
DISPOFF#
EDP_HPD
DMIC_DAT
USB20_P3
USB20_N3
DMIC_CLK
From PCH
<7,28> ENBKL
<28> BKOFF#
<7> INVTPWM
<7>EDP_AUXN
<7>EDP_AUXP
<7> ENVDD
<7> EDP_TXP0
<7> EDP_TXN0
<7> EDP_TXP1
<7> EDP_TXN1
<7> EDP_HPD
<22> HUB_USB20_N1
<22> HUB_USB20_P1
<28> TS_DISABLE#
<9> USB20_N3
<9> USB20_P3
<21>DMIC_CLK
<21>DMIC_DAT
+3VS_CMOS
+3VS
+3VS
B+ +LEDVDD +LCDVDD_CONN
TOUCH SCREEN POWER CIRCUIT
+3VS +3VS_TS
+3VS +LCDVDD_CONN
+3VS_TS
+3VS_CMOS
+3VS
Title
Document Number
Date: Sheet
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPART MENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NO R THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3 2
Issued Date
Deciphered Date
R e v
0.4
eDP/CAMERA
Size
B
14 of 46Monday, November 05,2018
2018/11/05 2019/11/05
Compal Electronics, Inc.
LA-H131P
C4
1U_0201_6.3V6M
12
2
0.1U_0201_10V K X5R
EDP_AUXN_C
2 0.1U_0201_10V K X5R
EDP_AUXP_C
C230
0.1U_0201_10V6K
1
R3 1 @ 2 0_0603_5%
C3
4.7U_0402_6.3V6M
1
2
0_0805_5%@R9
1
2
C231
10U_0603_6.3V6M
@
1
2 2
DT6
L30ESDL5V0C6-4_SOT23-6
SC300004W00
@ESD@
6
I/O4
VDD
5
4
3
I/O2
GND
2
I/O1 I/O3
1
R7
100K_0402_5%
1
2
EM5203AJ-20 SOT23 5P
SA00008R900
OUT
3
OC
GND
4
EN
U5
5
IN
R264 1 @ 20_0603_5%
2 0.1U_0201_10V K X5R
EDP_TXP1_C
2 0.1U_0201_10V K X5R
EDP_TXN1_C
C7
4.7U_0805_25V6-K
@
1
2
R265
100K_0402_5%
@
1
2
C5
0.1U_0201_10V6K
1
1
+LCDVDD R21@
2
2
0_0805_5%
W=60mils
JEDP1
CVILU_CVS3402M1RM-NH
SP01002FV00
ME@
1
1
2
3
2
4
3
5
4
6
5
7
6
8
7
9
8
10
9
11
10
12
11
13
12
14
13
15
14
16
15
17
16
18
17
19
18
41
GND
42
GND
GND
43
44
GND
45
20
19
21
20
22
21
23
22
24
23
25
24
26
25
27
26
28
27
29
28
30
29
31
30
32
31
33
32
38
34
33
35
34
36
35
37
36
38
37
39
39
40 GND
40
C8 1
C9 1
C10
1
C11 1
C12
1
C13
1
2
0.1U_0201_10V K X5R
EDP_TXP0_C
2 0.1U_0201_10V K X5R
EDP_TXN0_C
C6
10U_0603_6.3V6M
@
1
2 2
U2
U74AHC1G08G-AL5-R_SOT353-5
SA00000OH00
@
2
B
A
1
4
Y
5
G P
3
R1
1
@ 20_0402_5%
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