COMPAL LA-H101P Schematic
A
1 1
B
C
D
E
Compal
EL5C3/EL531/EL431
2 2
DIS
In
M/B Schematic Document
tel Whiskey Lake Processor with DDR4
2018-09-20
3 3
LA-H101P
REV: 0.A (EVT)
4 4
Security Classific ation
Security Classific ation
Security Classific ation
Is s u ed Date
Is s u ed Date
Is s u ed Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, IN C . AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, IN C . AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, IN C . AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETEN T D IVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETEN T D IVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETEN T D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, IN C . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, IN C . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, IN C . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR DISCLOSED TO AN Y THIRD P A R T Y WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C .
MAY BE USED B Y OR DISCLOSED TO AN Y THIRD P A R T Y WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C .
A
B
MAY BE USED B Y OR DISCLOSED TO AN Y THIRD P A R T Y WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C .
C
2018/09/21 2019/09/21
2018/09/21 2019/09/21
2018/09/21 2019/09/21
Compal S ecret Data
Compal S ecret Data
Compal S ecret Data
Deciphered Date
Deciphered Date
Deciphered Date
ompal Electronics, Inc.
ompal Electronics, Inc.
ompal Electronics, Inc.
C
C
Tit le
Tit le
Tit le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
D
Date: Sheet
C
LA-H101P
LA-H101P
LA-H101P
Cover Page
Cover Page
Cover Page
E
0.A0.A0.A
of
1 51Thursday, September 20, 2018
of
1 51Thursday, September 20, 2018
of
1 51Thursday, September 20, 2018
A
B
C
D
E
N17S-G0/G2
R4 2400MHz
PCI
TD
P:18W
1 1
FF (Key M)
NG
C
IE/SATA SSD
P
2242/2280 c o n n .
FF (Key E)
NG
WLAN/BT
2230 c o n n .
eD
2 2
FH
P P a n e l
D L C D
HDMI Conn.
H
D Conn.
D
VRAM(GDDR5) X2
2GB
for DIS
HD
MI Re-driver
8407A
PS
e x4 , Gen3 8Gb /s
PC
Ie x4 , Gen38Gb/s
SATA , Gen3 6Gb/s
PCI e x1 , Gen12.5Gb/s
U
B2.0 x1, 480Mb/s
S
eDP x2 , HBR 2.7Gb/s
I x4 , 2.97GT/s
DD
SATA , Gen3 6Gb /s
Whiskey Lake-U
15W
USB2.0 x1, 480Mb/s
3 3
T y p e - C Conn.
US
B3. 1 Gen1
B3. 1,G en1
US
CC
/Vco nn
VBus
MUX/CC
a l t e k RTS5448
R e
w i t c h
5V S
T o
u c h P a d
I2
C_3VL P
B3.1x1,Gen1
US
EC
I2
C
FAB#TA601
1528pin
BGA
DD
USB2 .0 x1, 480Mb/s
USB3.1 x1, Gen1 5Gb/s
S
B3.1 x1, Gen1 5Gb/s
U
US
B2.0 x1, 480Mb/s
US
B2.0 x1, 480Mb/s
US
B2.0 x1, 480Mb/s
B2.0 x1, 480Mb/s
US
C
I2
A
HD
Ie x1 , Gen12.5Gb/s
PC
I
SP
-A DDR4-SO-DIMM X1
CH
CH-B o n b oa rd RAM x4
B Charge r
US
TI S
N1702001
US
B3 redriver
Pa
rade PS8713B
USB3 redriver
rade PS8713B
Pa
FingerPrint
t. C amera
In
T
h P a n e l
ouc
io Codec
Aud
a l t e k ALC3287
Re
Ca
rd Reader
Re
a l t e k RTS5232S
I R O M
SP
MB
16
US
B2.0 x1, 480Mb/s
U
B3.1 x1, Gen1 5Gb/s
S
USB3.1 x1, Gen1 5Gb/s
HP
SP
K
DMIC
IO
SD
O
ub Boa rd
n S
USB Conn.
with A O U
U
B Conn.
S
Combo Jack
Int. Speaker
t. Array Mic *2
In
SD C
ard Conn.
On S
ub Boa rd
LPC
D
4 4
A
Int. KBD
Hall Sensor
B
KB
EN
E KB9022
C
C
LE
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THISSHEET OF ENGINEERING DRAWING IS THEPROPRIETARY PROPERTY OF COMPALELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THISSHEET OF ENGINEERING DRAWING IS THEPROPRIETARY PROPERTY OF COMPALELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THISSHEET OF ENGINEERING DRAWING IS THEPROPRIETARY PROPERTY OF COMPALELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND T RADE SECRET INFORMATION. THISSHEET MAYNOT BE TRANSFERED FROM THECUSTODY OFTHECOMPET ENT DIVISIONOF R&D
AND T RADE SECRET INFORMATION. THISSHEET MAYNOT BE TRANSFERED FROM THECUSTODY OFTHECOMPET ENT DIVISIONOF R&D
AND T RADE SECRET INFORMATION. THISSHEET MAYNOT BE TRANSFERED FROM THECUSTODY OFTHECOMPET ENT DIVISIONOF R&D
DEPARTMENT EXCEPT AS AUTHORIZEDBY COMPAL ELECTRONICS, I N C. NEITHER THISSHEET NOR THE INFORMATIONIT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZEDBY COMPAL ELECTRONICS, I N C. NEITHER THISSHEET NOR THE INFORMATIONIT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZEDBY COMPAL ELECTRONICS, I N C. NEITHER THISSHEET NOR THE INFORMATIONIT CONTAINS
MAYBE USED BY OR DISCLOSED TO ANY THIRD PA R T Y WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, I NC .
MAYBE USED BY OR DISCLOSED TO ANY THIRD PA R T Y WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, I NC .
MAYBE USED BY OR DISCLOSED TO ANY THIRD PA R T Y WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, I NC .
D
CompalSecret Data
CompalSecret Data
CompalSecret Data
Deciphered Date
Deciphered Date
Deciphered Date
Com
Com
Compal Electroni cs, Inc.
pal Electronic s, Inc.
Ti t l e
Ti t l e
Ti t l e
Size
Size
Size
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
pal Electronic s, Inc.
Block Diagram
Block Diagram
Block Diagram
Document N um b e r Rev
Document N um b e r Rev
Document N um b e r Rev
LA-H101P
LA-H101P
LA-H101P
E
2 51Thursday, September 20, 2018
2 51Thursday, September 20, 2018
2 51Thursday, September 20, 2018
0.A0.A0.A
of
of
of
1
V
oltage Rails
5VS
A
d d r e s s
10
01 100x 98h
A
d d r e s s
001 111x 9Eh
1
+
+
3VS
+VCCPLL_OC
1.05VS_VCCSTG
+
+
VCC_CORE
+VCC_GT
+VCC_SA
+1.05V_VCCST
+1.05VS_VCCIO
+1.8VS
+0.6VS
X
XX
X
XXX
ower
p
plane
+
CT7718W
1.2V
+2.5V
O O
O
X
+5VALW
3VALW
+
B
+
1.8VALW
A A
State
S
0
S3
S5 S4/AC
5 S4/ Battery only
S
S5 S4/AC & Battery
don't exist
B B
E
C SM Bus1 address
De vi c e
SmartBat tery
CH SM Bus address
P
De vi c e
DDR_JDIMM1
T o u c h Pad
A
d d r e s s
0001 011x 16h
Address
10 000x A0h
10
+
+1.05VALW
O
O
O
O
O
O
O
X
X
E
C SM Bus2 address
De vi c e
N
PU SM Bus address
G
De vi c e
Internalth ermal sensor
2
B
OM Structure Table
OM Structure
Item
DIS Only Components DIS@
U
MA Only Components UMA@
HDMI
Logo 45@
Memory Down - DDP Package
C
onnectors ME@
Intel CNVi
ESD Category ESD@
R
F Category RF@
Test Point TP@
Keyboard BackLight
Project select
GPU select
Memory Down select
MIC select
TypeC 20V_PRTCT 20V_PRTCT@
B
TS@Touch Screen
SDP@Memory Down - SDP Package
DDP@
GC6@GPU GC6 Components
NOGC6@Un-Mount GPU GC6 Components
CNVi@
EMI@EMI Category
KBL@
NOKBL@
S540@
S340@
C340@
S340_14@
S340_15@
N17S_G1@
N17S_G0@
N16V@
N16S@
N16@
N17@
MD@
NO_MD@
Arrary_MIC@
Single_MIC@
3
OM Structure
Item
S340_15 MD (Hynix 4GB)
S340_15 MD (Micron 4GB)
S340_15 MD (Samsung 4GB)
C340 MD (Hynix 4GB)
C340 MD (Micron 4GB)
C340 MD (Samsung 4GB)
On Board RAM X76 Resistors X76RAM@
S340_15@ VRAM (Hynix 2GB)
S340_15@ VRAM (Micron 2GB)
S340_15@ VRAM (Samsung 2GB)
C340 VRAM (Hynix 2GB)
C340 VRAM (Micron 2GB)
C340 VRAM (Samsung 2GB)
S340_14 MD (Hynix 4GB)
S340_14 MD (Micron 4GB)
S340_14 MD (Samsung 4GB)
S340_14@ VRAM (Hynix 2GB)
S340_14@ VRAM (Micron 2GB)
S340_14@ VRAM (Samsung 2GB)
B
H4G_S340_15@
M4G_S340_15@
S4G_S340_15@
H4G_C340@
M4G_C340@
S4G_C340@
VH2G_S340_15@
VM2G_S340_15@
VS2G_S340_15@
VH2G_C340@
VM2G_C340@
VS2G_C340@
H
4G_S340_14@
M4G_S340_14@
S4G_S340_14@
VH2G_S340_14@
VM2G_S340_14@
VS2G_S340_14@
4
SB 2.0 Port Table
U
External
1
SB2/3 Port (IO - 1)
U
2
USB2/3 Port (IO - 2)
3
USB2/3 Port (Type-C)
4
T
ouch Sc reen
5
6
Camer a
7
ingrt P rint
F
8
9
10
NGFF WLAN+BT
SB 3.0 Port Table PCIE Port Table
U
P
ort
1
USB2/3 Port (IO - 1)
2
USB2/3 Port (IO - 2)
3
SB2/3 Port (Type-C)
U
4
5
6
ATA Port Table
S
Port
0
1A
DD
H
1B
SSD1
USB PortPort
ON BOARD RAM * 4 (total 4GB)
340
C
ZZ
ZZ
H4G_C340@
Z
M4G_C340@
Z
ZZ
S4G_C340@
Z
5
P
ort
Lane
1
2
3
0
4
0
5
1
6
7
8
9
10
11
12
13
14
15
16
2
3
1
CardR eader
0
NG F F W L A N+ B T
0
3
2
SSD
1
0
D
GPU
X
76 SAMSUNG4GB M D
X7680538LA3
ZZZ
S4G_S340_15@ZZZ
X
76 SAMSUNG 4GB MD
X7680438L83
ZZZ
S4G_S340_14@
X76 SAMSUNG 4GB MD
XXXXXXXXX
ZZZ1
S340_14@
X4E S340-14
XXXXXXXXXX
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Ti t l e
Ti t l e
Ti t l e
otes List
otes List
otes List
N
N
N
Size
Size
Size
Document Number
Document Number
Document Number
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
LA-H101P
LA-H101P
LA-H101P
5
3 51Thursday, September 20, 2018
3 51Thursday, September 20, 2018
3 51Thursday, September 20, 2018
Rev
Rev
Rev
0.A0.A0.A
S340_15@
X
X7680538LA2
X
76 MICRON 4GB MD
X7680438L82
ZZZ
X76 MICRON 4GB MD
XXXXXXXXX
ZZZ
X4E C340
X4EAF838L01
Deciph ered Date
Deciph ered Date
Deciph ered Date
76 MI C R O N 4G B M D
M4G_S340_15@
M4G_S340_14@
C340@
X
76 HYNIX 4GB M D
MBUS Control Tab le
S
G
T
-
DGPU
SOURCE
EC_SMB_CK1
C C
D D
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
EC_SMB_CK4
EC_SMB_DA4
SOC_SMBCLK
SOC_SMBDATA
SOC_SML0CLK
SOC_SML0DATA
EC_SMB_CK2
EC_SMB_DA2
STATE
Full ON
S1(Power On Suspend)
S3 (Suspend to RAM)
S4 (Suspend to Disk)
S5 (Soft OFF)
NECP388
+3VL
N
+3VS
NECP388
+3VS
PCH
+3VALW
PCH
+3VALW
CH
P
+
SIGNAL
1
ECP388
3VS
VX X
+3VALW
X
V
X X X X X X
X
X
XX
V
X
+3VS
SLP_S1#
LOW
LOW
LOW LOW LOW
SLP_S4#SLP_S3# +V+VALWSLP_S5# Clock+VS
HIGHHIGHHIGH
HIGH HIGH HIGH
LOW
HIGH
LOWLOW
C
HARGER
V
+
19V_VIN
X
X
X
X
X
HIGH
HIGH
HIGH
N
EC P3 88 SODIMMBATT
X
V
+3VS+3VS
X
V
+3VS
ONONON
ON
ON
ON
ON
LOWLOW
ON
OFF
OFF
T
P
P
CH
X
X
X
ON
OFF
OFF
OFF
V
+
3VS
X
V
+
3VS
X
X
X
X
ONON
LOW
OFF
OFF
OFF
2
X
V
+
3VS
XX
X
SENSOR
X
X
V
+
3VS
X
X
X
HM
nsor
se
X
V
+
3VS
X
X
X
GPU
UV1
N17S_G0@
UV1
N17S_G2@
X
UC1
SRD1W i3_R1@
I3-8145U
SA0000C6R20
SRFG1 Pentium 5405U@
UC1
I3-8145U
SA0000C6R30
N17S-G0-A1
SA0000CC900
W
HL CPU
3
UC1
I5-8265U
SA0000C6Q20
SREJQi 5_R1@
N17S-G2-A1
SA0000CCB00
UC1
I7-8565U
SA0000C6P20
P
CB
SRFFW i7_R1@
ZZZ
PCB@
PCB
DA8001H6000
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THISSHEETOF ENGINEERING DRAWING IS THE PROPRIETARYPROPERTYOFCOMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
THISSHEETOF ENGINEERING DRAWING IS THE PROPRIETARYPROPERTYOFCOMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
THISSHEETOF ENGINEERING DRAWING IS THE PROPRIETARYPROPERTYOFCOMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THISSHEET MAY NOTBE T RANSFERED FROM THECUSTODY O F THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THISSHEET MAY NOTBE T RANSFERED FROM THECUSTODY O F THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THISSHEET MAY NOTBE T RANSFERED FROM THECUSTODY O F THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THISSHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THISSHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THISSHEET NOR THE INFORMATION IT CONTAINS
MAYBE USED BY OR DISCLOSED TO ANY THIRD PA R T Y WITHOUT PRIOR WRITTENCONSENT OF COMPAL ELECTRONICS, INC.
MAYBE USED BY OR DISCLOSED TO ANY THIRD PA R T Y WITHOUT PRIOR WRITTENCONSENT OF COMPAL ELECTRONICS, INC.
MAYBE USED BY OR DISCLOSED TO ANY THIRD PA R T Y WITHOUT PRIOR WRITTENCONSENT OF COMPAL ELECTRONICS, INC.
X7680538LA1
S340-15
ZZZ
H4G_S340_15@
X
76 HYNI X 4G B M D
X7680438L81
S340-14
ZZZ
H4G_S340_14@
X76 HYNI X 4GB M D
XXXXXXXXX
X
4E
S340-15 C340-14 S340-14
ZZZ
X4E S340-15
X4EAF838L51
Compal Secret Data
Compal Secret Data
2018/09/21 2019/09/21
2018/09/21 2019/09/21
2018/09/21 2019/09/21
Compal Secret Data
4
5
D D
C C
4
-
PowerMap_DDR4_Volume_NON CS]
B
+
3
2
1
B B
A A
Security Classification
Security Classification
Security Classification
IssuedDate
Issued Dat e
Issued Dat e
THISSHEETOF ENGINEE RINGD RAWING IS THE P ROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
THISSHEETOF ENGINEE RINGD RAWING IS THE P ROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
THISSHEETOF ENGINEE RINGD RAWING IS THE P ROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOTB E TRANSFE RED FROM THE CUSTODY OF THE COMPETENT DIVISIONOF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOTB E TRANSFE RED FROM THE CUSTODY OF THE COMPETENT DIVISIONOF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOTB E TRANSFE RED FROM THE CUSTODY OF THE COMPETENT DIVISIONOF R&D
DEPARTMENTEXCEPTA S AUTHORIZEDBY COMPAL ELECTRONICS,INC. NE ITHER THIS SHEET NOR THE IN FOR MAT ION ITCONTAINS
DEPARTMENTEXCEPTA S AUTHORIZEDBY COMPAL ELECTRONICS,INC. NE ITHER THIS SHEET NOR THE IN FOR MAT ION ITCONTAINS
DEPARTMENTEXCEPTA S AUTHORIZEDBY COMPAL ELECTRONICS,INC. NE ITHER THIS SHEET NOR THE IN FOR MAT ION ITCONTAINS
MAYBE USED BY OR DISCLOSED TO ANY THIRD PAR TY WITHOUT PRIORWRITTENC ONSENT OF COMPALELECTRONICS,INC .
MAYBE USED BY OR DISCLOSED TO ANY THIRD PAR TY WITHOUT PRIORWRITTENC ONSENT OF COMPALELECTRONICS,INC .
5
4
3
MAYBE USED BY OR DISCLOSED TO ANY THIRD PAR TY WITHOUT PRIORWRITTENC ONSENT OF COMPALELECTRONICS,INC .
2
Compal Secret Data
Compal Secret Data
Compal Secret Data
2018/09/21 2019/ 09/21
2018/09/21 2019/ 09/21
2018/09/21 2019/ 09/21
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Pow er M AP
Pow er M AP
Pow er M AP
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
LA-H101P
4 51Thursday, September 20, 2018
4 51Thursday, September 20, 2018
1
4 51Thursday, September 20, 2018
0.A0.A0.A
5
4
3
2
1
3->S0 S0->S3 ->S0
G
3VL_RTC
+
OC_RTCRST#
S
B+
D D
3VLP/+5VLP
+
E
C_ON
+5VALW/+3VALW/+3VALW_DSW
PM_ BAT L OW #
tPCH01_Min : 9 ms
tPCH04_Min : 9 ms
Pull-up to DSW well if not implemented.
DS3 DS3S3/
/
PCH_PWR_EN (S LP_SUS#)
+3V_PRI M
+1.8V_PRIM
EXT_PWR_GAT E#
+1.0V_MPHYPLL
+1.0V_PRIM_CORE
+1.0V_PRIM
tPCH06_Min : 200 us
SUSACK#
PCH_DPWROK
C_RSMRST#
E
C C
C_PRESENT
A
tPCH34_Max : 20 ms
tPCH02_Min : 10 ms
tPCH03_Min : 10 ms
tPLT02_Min : 0 ms Max : 90 ms
ON / O F F
P
BTN_OUT#
P
M_SLP_S5#
Minimum duration of PWRBTN# assertion = 16mS. PWRBTN# can assert before or after RSMRST#
ESPI_RST#
If EXT_PWR_GATE# Toffmin is too small, Pwr
gate may choose to completely ignore it
tPCH43_Min : 95 ms
tPCH18_Min : 90 us
PM_ SL P_ S4 #
SYSON
+1.0V_VCCST/+1.0V_V CCSFR
+1.35V_VDDQ/+1.35V_VCCSF R_OC
PM_ SL P_ S3 #
SUSP#
+1.0VS_VCCST G
+1.0VS_VCCI O
B B
+5VS/+3VS/+1.5V S/+1.05 VS
EC_VCCST_PG
VR_ON
SM_PG_CTRL
+0.675VS_VTT
+VCC_SA
+VCC_CORE
tCPU04 Min : 100 ns
tCPU10 Min : 1 ms
T <=10msec
T = 10msec
tCPU19 Max : 100 ns
tCPU18 Max : 35 us
tCPU09 Min : 1 ms
+VCC_GT
VR_PWRGD
PCH_PWROK
tCPU16 Min : 0 ns
H_CPUPWRGD
SYS_PWROK
A A
SUS_STAT#
SOC_PLTRST#
0->S5
S
+3VL_RTC
S
OC_RTCR ST#
B+
+3VLP/+ 5VLP
E
C_ON
+
5VALW/+ 3VALW/+3 VALW_D SW
PM_ BAT L OW #
PCH_PWR_EN (S LP_SUS#)
+3V_PRI M
+
1.8V_ PRIM
EXT_PWR_GAT E#
+1.0V_MPHYPLL
+1.0V_PRIM_CORE
+1.0V_P RIM
SUSACK#
PCH _DP WR OK
C_RSMR ST#
E
C_PRESENT
A
ON / O F F
P
BTN_OUT#
PM_ SL P_ S5 #
ESPI_RST#
PM_ SL P_ S4 #
SYSON
+
1.0V_VCCST/+1.0V_VCCSFR
+1.35V_VDDQ/+1.35V_VCCSF R_OC
PM_ SL P_ S3 #
SUSP#
+1.0VS_VCCST G
+1.0VS_VCCI O
+5VS/+3VS/+1.5 VS/+1. 05VS
EC_VCCST_PG
VR_ON
SM_PG_CTRL
+0.675VS_VTT
+VCC_SA
+VCC_CORE
+VCC_GT
VR_PWRGD
PCH _PW R OK
H_CPUPWRGD
SYS_PWROK
SUS_STAT#
SOC_PLTRST#
Com pal Secret Da ta
Com pal Secret Da ta
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET O F ENGINEERING DRAWING IS THEPROPRIETARY PROPERTY OF COMPAL ELECT RONICS, I N C. AN D CONTAINS CONFIDENTIAL
THIS SHEET O F ENGINEERING DRAWING IS THEPROPRIETARY PROPERTY OF COMPAL ELECT RONICS, I N C. AN D CONTAINS CONFIDENTIAL
THIS SHEET O F ENGINEERING DRAWING IS THEPROPRIETARY PROPERTY OF COMPAL ELECT RONICS, I N C. AN D CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION.THISSHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THECOMPET ENT D IVISION OF R&D
AND TRADE SECRET INFORMATION.THISSHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THECOMPET ENT D IVISION OF R&D
AND TRADE SECRET INFORMATION.THISSHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THECOMPET ENT D IVISION OF R&D
DEPARTMENT EXCEPT AS A U T H O R IZ E D BY COMPAL ELECTRONICS, IN C . NEITHER THIS SHEET NOR THE INFOR MATION IT CONTAINS
DEPARTMENT EXCEPT AS A U T H O R IZ E D BY COMPAL ELECTRONICS, IN C . NEITHER THIS SHEET NOR THE INFOR MATION IT CONTAINS
DEPARTMENT EXCEPT AS A U T H O R IZ E D BY COMPAL ELECTRONICS, IN C . NEITHER THIS SHEET NOR THE INFOR MATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TOA N Y THIRD PA R T Y WITHOUT PRIOR WRITTENCONSENT OF COMPAL ELECT RONICS, IN C .
MAY BE USED BY OR DISCLOSED TOA N Y THIRD PA R T Y WITHOUT PRIOR WRITTENCONSENT OF COMPAL ELECT RONICS, IN C .
5
4
3
MAY BE USED BY OR DISCLOSED TOA N Y THIRD PA R T Y WITHOUT PRIOR WRITTENCONSENT OF COMPAL ELECT RONICS, IN C .
2
Com pal Secret Da ta
2018/09/21 2019/09/21
2018/09/21 2019/09/21
2018/09/21 2019/09/21
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Ti t l e
Ti t l e
Ti t l e
Size Do cument Numb e r Rev
Size Do cument Numb e r Rev
Size Do cument Numb e r Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Power Sequence
Power Sequence
Power Sequence
LA-H101P
1
5 51Thursday, September 20, 2018
5 51Thursday, September 20, 2018
5 51Thursday, September 20, 2018
0.A0.A0.A
A
1 1
< Compensation PU For eDP >
+1.05VS_VCCIO
2 2
1 2
RC2 24.9_0201_1%
T r a c e width=20 mils, Spacing=25mil, M ax length=600mils
EDP_COMP
B
<HDMI>
HDMI DDC (Port2 )
<29>
<29>
<29>
<29>
CPU_DP2_CTRL_CLK<29,30>
CPU_DP2_CTRL_DATA<29,30>
CPU_DP2_N0<29>
CPU_DP2_P0
CPU_DP2_N1
CPU_DP2_P1<29>
CPU_DP2_N2
CPU_DP2_P2
CPU_DP2_N3<29>
CPU_DP2_P3<29>
TS_I2C_RST#<28>
EDP_COMP
C
UC1A
AL5
DDI1_TXN_0
AL6
DDI1_TXP_0
AJ5
DDI1_TXN_1
AJ6
DDI1_TXP_1
AF6
DDI1_TXN_2
AF5
DDI1_TXP_2
AE5
DDI1_TXN_3
AE6
DDI1_TXP_3
AC4
DDI2_TXN_0
AC3
DDI2_TXP_0
AC1
DDI2_TXN_1
AC2
DDI2_TXP_1
AE4
DDI2_TXN_2
AE3
DDI2_TXP_2
AE1
DDI2_TXN_3
AE2
DDI2_TXP_3
AM6
DIS P_ RCO MP
CC8
GPP_E18/DPPB_CTRLCLK/CNV_BT_HOST_W AKE#
CC9
GPP_E19/DPPB_CTRLDATA
CH4
GPP_E20/DPPC_CTRLCLK
CH3
GPP_E21/DPPC_CTRLDATA
CP4
GPP_E22/DPPD_CTRLCLK
CN4
GPP_E23/DPPD_CTRLDATA
CR2 6
GPP_H16/DDPF_CTRLCLK
CP2 6
GPP_H17/DDPF_CTRLDATA
WHL-U_BGA1528
1 of 2 0
EDP_TXN_0
EDP_TXP_0
EDP_TXN_1
EDP_TXP_1
EDP_TXN_2
EDP_TXP_2
EDP_TXN_3
EDP_TXP_3
EDP_AUX_N
EDP_AUX_P
DISP_UTILS
DDI1_AUX_N
DDI1_AUX_P
DDI2_AUX_N
DDI2_AUX_P
DDI3_AUX_N
DDI3_AUX_P
GPP_E13/DDPB_HPD0/DISP_MISC0
GPP_E14/DDPC_HPD1/DISP_MISC1
GPP_E15/DPPD_HPD2/DISP_MISC2
GPP_E16/DPPE_HPD3/DISP_MI SC3
GPP_E17/EDP_HPD/DISP_MIS C4
EDP_BKLTEN
EDP_VDDEN
EDP_BKLTCTL
AG4
AG3
AG2
AG1
AJ4
AJ3
AJ2
AJ1
AH4
AH3
AM7
AC7
AC6
AD4
AD3
AG7
AG6
CN6
CM6
CP7
CP6
CM7
CK1 1
CG1 1
CH11
EC_SCI#
D
EDP_TXN0 <28>
EDP_TXP0 <28>
EDP_TXN1 <28>
EDP_TXP1 <28>
EDP_AUXN <28>
EDP_AUXP <28>
CPU_DP2_HPD < 29,30>
EC_SCI# <34>
EDP_HPD <28>
ENBKL <34>
PCH_ENVDD <28>
IN V P W M <28>
<e DP >
EC_SCI#
From HDMI
From eDP
E
1 2
RC1 10K_0402_5%
+3VS
+1.05 VS_VCCST G
12
RC3
1K_0402_5%
+1.05V_VCCST
3 3
4 4
1 2
RC8 1K_0402_5%
1
2
RC10 49.9_0402_1%@
A
H_THERMTRIP#
CATERR#
H_PROCHOT#<34>
B
1 2
RC4 499_0402_1%
RC11 49.9_0402_1%
RC12 49.9_0402_1%
RC14 49.9_0402_1%@
RC15 49.9_0402_1%@
If rout ed M S, PECIrequires 18mils spacingto other signals
CB3 4
CC3 5
BP27
BW25
AA4
AR1
BJ1
CE9
CN3
CATERR#
H_PECI<34>
H_PROCHOT#_R
H_THERMTRIP#
12
12
12
12
CPU_POPIRCOMP
PCH_OPIRCOMP
EDRAM_OPIO_RCOMP
EOPIO_RCOMP
UC1D
CAT ER R#
PECI
Y4
PROCHOT#
THRMTRIP#
U1
BPM#_0
U2
BPM#_1
U3
BPM#_2
U4
BPM#_3
GPP_E3/CPU_GP0
GPP_E7/CPU_GP1
GPP_B3/CPU_GP2
GPP_B4/CPU_GP3
PROC_POPIRCOMP
PCH_OPIRCOMP
L5
OPCE_RCOMP
N5
OPC_RCOMP
WHL-U_BGA1528
Security Classificat ion
Security Classificat ion
Security Classificat ion
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I N C . AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I N C . AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I N C . AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETEN T D IVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETEN T D IVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETEN T D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, IN C . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, IN C . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, IN C . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR DISCLOSED TO AN Y THIRD P A R T Y WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C .
MAY BE USED B Y OR DISCLOSED TO AN Y THIRD P A R T Y WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C .
MAY BE USED B Y OR DISCLOSED TO AN Y THIRD P A R T Y WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C .
C
4 of 20
Is s u ed Date
Is s u ed Date
Is s u ed Date
PROC_TCK
PROC_TDI
PROC_TDO
PROC_TMS
PROC_TRST#
PCH_TCK
PCH_TDI
PCH_TDO
PCH_TMS
PCH_TRST#
PCH_JTAGX
PROC_PREQ#
PROC_PRDY#
CPU_XDP_TCK0
T6
SOC_XDP_TDI
U6
SOC_XDP_TDO
Y5
SOC_XDP_TMS
T5
SOC_XDP_TRST#
AB6
PCH_JTAG_TCK1
W6
SOC_XDP_TDI
U5
SOC_XDP_TDO
W5
SOC_XDP_TMS
P5
SOC_XDP_TRST#
Y6
CPU_XDP_TCK0
P6
W2
W1
2018/09/21 2019/09/21
2018/09/21 2019/09/21
2018/09/21 2019/09/21
T1TP@
T2TP@
Compal S ecret Data
Compal S ecret Data
Compal S ecret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
< PU/PD for CMC Debug >
SOC_XDP_TMS
SOC_XDP_TDI
SOC_XDP_TDO
CPU_XDP_TCK0
PCH_JTAG_TCK1
SOC_XDP_TRST#
RC5 51_0402_5%CMC@
RC6 51_0402_5%CMC@
RC7 51_0402_5%DCI@
RC9 51_0402_5%DCI@
RC13 51_0402_5%@
RC16 51_0402_5%@
Tit le
Tit le
Tit le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
+1.05VS_VCCSTG
1 2
1 2
1 2
1 2
1 2
1 2
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
WHL-U(1/12)DDI,EDP,MISC,CMC
WHL-U(1/12)DDI,EDP,MISC,CMC
WHL-U(1/12)DDI,EDP,MISC,CMC
LA-H101P
LA-H101P
LA-H101P
E
6 51Thursday, September 20, 2018
6 51Thursday, September 20, 2018
6 51Thursday, September 20, 2018
0.A0.A0.A
of
of
of
5
Interleaved Memory
4
3
2
1
D D
C C
B B
<18>
DDR_A_D[0..15]
DDR_A_D[16..31]<18>
DDR_A_D[32..47]<18>
DDR_A_D[48..63]<18>
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
UC1B
A26
DDR0_DQ_0/DDR0_DQ_0
D26
DDR0_DQ_1/DDR0_DQ_1
D28
DDR0_DQ_2/DDR0_DQ_2
C28
DDR0_DQ_3/DDR0_DQ_3
B26
DDR0_DQ_4/DDR0_DQ_4
C26
DDR0_DQ_5/DDR0_DQ_5
B28
DDR0_DQ_6/DDR0_DQ_6
A28
DDR0_DQ_7/DDR0_DQ_7
B30
DDR0_DQ_8/DDR0_DQ_8
D30
DDR0_DQ_9/DDR0_DQ_9
B33
DDR0_DQ_10/DDR0_DQ_10
D32
DDR0_DQ_11/DDR0_DQ_11
A30
DDR0_DQ_12/DDR0_DQ_12
C30
DDR0_DQ_13/DDR0_DQ_13
B32
DDR0_DQ_14/DDR0_DQ_14
C32
H37
DDR0_DQ_16/DDR0_DQ_32
H34
DDR0_DQ_17/DDR0_DQ_33
K34
DDR0_DQ_18/DDR0_DQ_34
K35
DDR0_DQ_19/DDR0_DQ_35
H36
DDR0_DQ_20/DDR0_DQ_36
H35
DDR0_DQ_21/DDR0_DQ_37
K36
DDR0_DQ_22/DDR0_DQ_38
K37
DDR0_DQ_23/DDR0_DQ_39
N36
DDR0_DQ_24/DDR0_DQ_40
N34
DDR0_DQ_25/DDR0_DQ_41
R37
DDR0_DQ_26/DDR0_DQ_42
R34
DDR0_DQ_27/DDR0_DQ_43
N37
DDR0_DQ_28/DDR0_DQ_44
N35
DDR0_DQ_29/DDR0_DQ_45
R36
DDR0_DQ_30/DDR0_DQ_46
R35
DDR0_DQ_31/DDR0_DQ_47
AN35
DDR0_DQ_32/DDR1_DQ_0
AN34
DDR0_DQ_33/DDR1_DQ_1
AR35
DDR0_DQ_34/DDR1_DQ_2
AR34
DDR0_DQ_35/DDR1_DQ_3
AN37
DDR0_DQ_36/DDR1_DQ_4
AN36
DDR0_DQ_37/DDR1_DQ_5
AR36
DDR0_DQ_38/DDR1_DQ_6
AR37
DDR0_DQ_39/DDR1_DQ_7
AU35
DDR0_DQ_40/DDR1_DQ_8
AU34
DDR0_DQ_41/DDR1_DQ_9
AW35
DDR0_DQ_42/DDR1_DQ_10
AW34
DDR0_DQ_43/DDR1_DQ_11
AU37
DDR0_DQ_44/DDR1_DQ_12
AU36
DDR0_DQ_45/DDR1_DQ_13
AW36
DDR0_DQ_46/DDR1_DQ_14
AW37
DDR0_DQ_47/DDR1_DQ_15
BA35
DDR0_DQ_48/DDR1_DQ_32
BA34
DDR0_DQ_49/DDR1_DQ_33
BC35
DDR0_DQ_50/DDR1_DQ_34
BC34
DDR0_DQ_51/DDR1_DQ_35
BA37
DDR0_DQ_52/DDR1_DQ_36
BA36
DDR0_DQ_53/DDR1_DQ_37
BC36
DDR0_DQ_54/DDR1_DQ_38
BC37
DDR0_DQ_55/DDR1_DQ_39
BE35
DDR0_DQ_56/DDR1_DQ_40
BE34
DDR0_DQ_57/DDR1_DQ_41
BG35
DDR0_DQ_58/DDR1_DQ_42
BG34
DDR0_DQ_59/DDR1_DQ_43
BE37
DDR0_DQ_60/DDR1_DQ_44
BE36
DDR0_DQ_61/DDR1_DQ_45
BG36
DDR0_DQ_62/DDR1_DQ_46
BG37
DDR0_DQ_63/DDR1_DQ_47
WHL-U_BGA1528
DDR0_CKN_0/DDR0_CKN_0
DDR0_CKP_0/DDR0_CKP_0
DDR0_CKN_1/DDR0_CKN_1
DDR0_CKP_1/DDR0_CKP_1
DDR0_CKE_0/DDR0_CKE_0
DDR0_CKE_1/DDR0_CKE_1
DDR0_CS#_0/DDR0_CS#_0
DDR0_CS#_1/DDR0_CS#_1
DDR0_DQ_15/DDR0_DQ_15
DDR0_ODT_0/DDR0_ODT_0
DDR0_CAB_7/DDR0_MA_10
DDR0_CAA_7/DDR0_MA_11
DDR0_CAA_6/DDR0_MA_12
DDR0_CAB_0/DDR0_MA_13
DDR0_CAB_2/DDR0_MA_14
DDR0_CAB_1/DDR0_MA_15
DDR0_CAB_3/DDR0_MA_16
DDR0_DQSN_0/DDR0_DQSN_0
DDR0_DQSP_0/DDR0_DQSP_0
DDR0_DQSN_1/DDR0_DQSN_1
DDR0_DQSP_1/DDR0_DQSP_1
DDR0_DQSN_2/DDR0_DQSN_4
DDR0_DQSP_2/DDR0_DQSP_4
DDR0_DQSN_3/DDR0_DQSN_5
DDR0_DQSP_3/DDR0_DQSP_5
DDR0_DQSN_4/DDR1_DQSN_0
DDR0_DQSP_4/DDR1_DQSP_0
DDR0_DQSN_5/DDR1_DQSN_1
DDR0_DQSP_5/DDR1_DQSP_1
DDR0_DQSN_6/DDR1_DQSN_4
DDR0_DQSP_6/DDR1_DQSP_4
DDR0_DQSN_7/DDR1_DQSN_5
DDR0_DQSP_7/DDR1_DQSP_5
2 of 20
DDR0_CKE_2/NC
DDR0_CKE_3/NC
NC/DDR0_ODT_1
DDR0_CAB_9/DDR0_MA_0
DDR0_CAB_8/DDR0_MA_1
DDR0_CAB_5/DDR0_MA_2
NC/DDR0_MA_3
NC/DDR0_MA_4
DDR0_CAA_0/DDR0_MA_5
DDR0_CAA_2/DDR0_MA_6
DDR0_CAA_4/DDR0_MA_7
DDR0_CAA_3/DDR0_MA_8
DDR0_CAA_1/DDR0_MA_9
DDR0_CAB_4/DDR0_BA_0
DDR0_CAB_6/DDR0_BA_1
DDR0_CAA_5/DDR0_BG_0
DDR0_CAA_8/DDR0_ACT#
DDR0_CAA_9/DDR0_BG_1
NC/DDR0_ALERT#
NC/DDR0_PAR
DDR_VREF_CA
DDR0_VREF_DQ_0
DDR0_VREF_DQ_1
DDR1_VREF_DQ
DDR_VTT_CNTL
V32
V31
T32
T31
U36
U37
U34
U35
AE32
AF32
AE31
AF31
AC37
AC36
AC34
AC35
AA35
AB35
AA37
AA36
AB34
W36
Y31
W34
AA34
AC32
AC31
AB32
Y32
W32
AB31
V34
V35
W35
C27
D27
D31
C31
J35
J34
P34
P35
AP35
AP34
AV34
AV35
BB35
BB34
BF34
BF35
W37
W31
F36
D35
D37
E36
C35
DDR_A_CLK#0
DDR_A_CLK0
DDR_A_CLK#1
DDR_A_CLK1
DDR_A_CKE0
DDR_A_CS#0
DDR_A_CS#1
DDR_A_ODT0
DDR_A_ODT1
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15
DDR_A_MA16
DDR_A_BA0
DDR_A_BA1
DDR_A_BG0
DDR_A_ACT#
DDR_A_BG1
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_ALERT#
DDR_A_PARITY
+0.6V_A_VREFCA
+0.6V_ B_VREFDQ
DDR_PG_CTRL
DDR_A_CLK#0 <18>
DDR_A_CLK0 <18>
TP@
T3
T4TP@
DDR_A_CKE0 <18,19>
DDR_A_CS#0 <18,19>
T5TP@
DDR_A_ODT0 <18,19>
T7TP@
DDR_A_MA0 <18,19>
DDR_A_MA1 <18,19>
DDR_A_MA2 <18,19>
DDR_A_MA3 <18,19>
DDR_A_MA4 <18,19>
DDR_A_MA5 <18,19>
DDR_A_MA6 <18,19>
DDR_A_MA7 <18,19>
DDR_A_MA8 <18,19>
DDR_A_MA9 <18,19>
DDR_A_MA10 <18,19>
DDR_A_MA11 <18,19>
DDR_A_MA12 <18,19>
DDR_A_MA13 <18,19>
DDR_A_MA14 <18,19>
DDR_A_MA15 <18,19>
DDR_A_MA16 <18,19>
DDR_A_BA0 <18,19>
DDR_A_BA1 <18,19>
DDR_A_BG0 <18,19>
DDR_A_ACT# <18,19>
DDR_A_BG1 <18>
DDR_A_DQS#0 <18>
DDR_A_DQS0 <18>
DDR_A_DQS#1 <18>
DDR_A_DQS1 <18>
DDR_A_DQS#2 <18>
DDR_A_DQS2 <18>
DDR_A_DQS#3 <18>
DDR_A_DQS3 <18>
DDR_A_DQS#4 <18>
DDR_A_DQS4 <18>
DDR_A_DQS#5 <18>
DDR_A_DQS5 <18>
DDR_A_DQS#6 <18>
DDR_A_DQS6 <18>
DDR_A_DQS#7 <18>
DDR_A_DQS7 <18>
DDR_A_ALERT# <18>
DDR_A_PARITY <18,19>
+0.6V_A_VREFCA <18>
+0.6V_B_VREFDQ <20>
DDR_B_D[0..15]
<20>
DDR_B_D[16..31]<20>
DDR_B_D[32..47]<20>
DDR_B_D[48..63]<20>
Trace width/Spacing >= 20mils
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
UC1C
J22
DDR1_DQ_0/DDR0_DQ_16
H25
DDR1_DQ_1/DDR0_DQ_17
G22
DDR1_DQ_2/DDR0_DQ_18
H22
DDR1_DQ_3/DDR0_DQ_19
F25
DDR1_DQ_4/DDR0_DQ_20
J25
DDR1_DQ_5/DDR0_DQ_21
G25
DDR1_DQ_6/DDR0_DQ_22
F22
DDR1_DQ_7/DDR0_DQ_23
D22
DDR1_DQ_8/DDR0_DQ_24
C22
DDR1_DQ_9/DDR0_DQ_25
C24
DDR1_DQ_10/DDR0_DQ_26
D24
DDR1_DQ_11/DDR0_DQ_27
A22
DDR1_DQ_12/DDR0_DQ_28
B22
DDR1_DQ_13/DDR0_DQ_29
A24
DDR1_DQ_14/DDR0_DQ_30
B24
DDR1_DQ_15/DDR0_DQ_31
G31
DDR1_DQ_16/DDR0_DQ_48
G32
DDR1_DQ_17/DDR0_DQ_49
H29
DDR1_DQ_18/DDR0_DQ_50
H28
DDR1_DQ_19/DDR0_DQ_51
G28
DDR1_DQ_20/DDR0_DQ_52
G29
DDR1_DQ_21/DDR0_DQ_53
H31
DDR1_DQ_22/DDR0_DQ_54
H32
DDR1_DQ_23/DDR0_DQ_55
L31
DDR1_DQ_24/DDR0_DQ_56
L32
DDR1_DQ_25/DDR0_DQ_57
N29
DDR1_DQ_26/DDR0_DQ_58
N28
DDR1_DQ_27/DDR0_DQ_59
L28
DDR1_DQ_28/DDR0_DQ_60
L29
DDR1_DQ_29/DDR0_DQ_61
N31
DDR1_DQ_30/DDR0_DQ_62
N32
DDR1_DQ_31/DDR0_DQ_63
AJ29
DDR1_DQ_32/DDR1_DQ_16
AJ30
DDR1_DQ_33/DDR1_DQ_17
AM32
DDR1_DQ_34/DDR1_DQ_18
AM31
DDR1_DQ_35/DDR1_DQ_19
AM30
DDR1_DQ_36/DDR1_DQ_20
AM29
DDR1_DQ_37/DDR1_DQ_21
AJ31
DDR1_DQ_38/DDR1_DQ_22
AJ32
DDR1_DQ_39/DDR1_DQ_23
AR31
DDR1_DQ_40/DDR1_DQ_24
AR32
DDR1_DQ_41/DDR1_DQ_25
AV30
DDR1_DQ_42/DDR1_DQ_26
AV29
DDR1_DQ_43/DDR1_DQ_27
AR30
DDR1_DQ_44/DDR1_DQ_28
AR29
DDR1_DQ_45/DDR1_DQ_29
AV32
DDR1_DQ_46/DDR1_DQ_30
AV31
DDR1_DQ_47/DDR1_DQ_31
BA32
DDR1_DQ_48/DDR1_DQ_48
BA31
DDR1_DQ_49/DDR1_DQ_49
BD31
DDR1_DQ_50/DDR1_DQ_50
BD32
DDR1_DQ_51/DDR1_DQ_51
BA30
DDR1_DQ_52/DDR1_DQ_52
BA29
DDR1_DQ_53/DDR1_DQ_53
BD29
DDR1_DQ_54/DDR1_DQ_54
BD30
DDR1_DQ_55/DDR1_DQ_55
BG31
DDR1_DQ_56/DDR1_DQ_56
BG32
DDR1_DQ_57/DDR1_DQ_57
BK32
DDR1_DQ_58/DDR1_DQ_58
BK31
DDR1_DQ_59/DDR1_DQ_59
BG29
DDR1_DQ_60/DDR1_DQ_60
BG30
DDR1_DQ_61/DDR1_DQ_61
BK30
DDR1_DQ_62/DDR1_DQ_62
BK29
DDR1_DQ_63/DDR1_DQ_63
WHL-U_BGA1528
DDR1_CKN_0/DDR1_CKN_0
DDR1_CKP_0/DDR1_CKP _0
DDR1_CKN_1/DDR1_CKN_1
DDR1_CKP_1/DDR1_CKP _1
DDR1_CKE_0/DDR1_CKE _0
DDR1_CKE_1/DDR1_CKE _1
DDR1_CKE_2/NC
DDR1_CKE_3/NC
DDR1_CS#_0/DDR1_CS#_0
DDR1_CS#_1/DDR1_CS#_1
DDR1_ODT_0/DDR1_ODT_0
NC/DDR1_ODT_1
DDR1_CAB_9/DDR1_MA_0
DDR1_CAB_8/DDR1_MA_1
DDR1_CAB_5/DDR1_MA_2
NC/DDR1_MA_3
NC/DDR1_MA_4
DDR1_CAA_0/DDR1_MA_5
DDR1_CAA_2/DDR1_MA_6
DDR1_CAA_4/DDR1_MA_7
DDR1_CAA_3/DDR1_MA_8
DDR1_CAA_1/DDR1_MA_9
DDR1_CAB_7/DDR1_MA_10
DDR1_CAA_7/DDR1_MA_11
DDR1_CAA_6/DDR1_MA_12
DDR1_CAB_0/DDR1_MA_13
DDR1_CAB_2/DDR1_MA_14
DDR1_CAB_1/DDR1_MA_15
DDR1_CAB_3/DDR1_MA_16
DDR1_CAB_4/DDR1_BA_0
DDR1_CAB_6/DDR1_BA_1
DDR1_CAA_5/DDR1_BG_0
DDR1_CAA_9/DDR1_BG_1
DDR1_CAA_8/DDR1_ACT#
DDR1_DQSN_0/DDR0_DQSN_2
DDR1_DQSP_0/DDR0_DQSP _2
DDR1_DQSN_1/DDR0_DQSN_3
DDR1_DQSP_1/DDR0_DQSP _3
DDR1_DQSN_2/DDR0_DQSN_6
DDR1_DQSP_2/DDR0_DQSP _6
DDR1_DQSN_3/DDR0_DQSN_7
DDR1_DQSP_3/DDR0_DQSP _7
DDR1_DQSN_4/DDR1_DQSN_2
DDR1_DQSP_4/DDR1_DQSP _2
DDR1_DQSN_5/DDR1_DQSN_3
DDR1_DQSP_5/DDR1_DQSP _3
DDR1_DQSN_6/DDR1_DQSN_6
DDR1_DQSP_6/DDR1_DQSP _6
DDR1_DQSN_7/DDR1_DQSN_7
DDR1_DQSP_7/DDR1_DQSP _7
NC/DDR1_ALERT#
NC/DDR1_PAR
DRAM_RESET#
DDR_COMP_0
DDR_COMP_1
DDR_COMP_2
3 of 20
AF28
AF29
AE28
AE29
T28
T29
V28
V29
AL37
AL35
AL36
AL34
AG36
AG35
AF34
AG37
AE35
AF35
AE37
AC29
AE36
AB29
AG34
AC28
AB28
AK35
AJ35
AK34
AJ34
AJ37
AJ36
W29
Y28
W28
H24
G24
C23
D23
G30
H30
L30
N30
AL31
AL30
AU31
AU30
BC31
BC30
BH31
BH30
Y29
AE34
BU31
BN28
BN27
BN29
DDR_B_CLK#0
DDR_B_CLK0
DDR_B_CLK#1
DDR_B_CLK1
DDR_B_CKE0
DDR_B_CKE1
DDR_B_CS#0
DDR_B_CS#1
DDR_B_ODT0
DDR_B_ODT1
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15
DDR_B_MA16
DDR_B_BA0
DDR_B_BA1
DDR_B_BG0
DDR_B_BG1
DDR_B_ACT#
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_ALERT#
DDR_B_PARITY
DDR_DRAMRST#
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
#543016 PDG1.5 P.168
W=12-15 Space= 20/25 L=500mil
DDR_B_CLK#0 <20>
DDR_B_CLK0 <20>
DDR_B_CLK#1 <20>
DDR_B_CLK1 <20>
DDR_B_CKE0 <20>
DDR_B_CKE1 <20>
DDR_B_CS#0 <20>
DDR_B_CS#1 <20>
DDR_B_ODT0 <20>
DDR_B_ODT1 <20>
DDR_B_MA0 <20>
DDR_B_MA1 <20>
DDR_B_MA2 <20>
DDR_B_MA3 <20>
DDR_B_MA4 <20>
DDR_B_MA5 <20>
DDR_B_MA6 <20>
DDR_B_MA7 <20>
DDR_B_MA8 <20>
DDR_B_MA9 <20>
DDR_B_MA10 <20>
DDR_B_MA11 <20>
DDR_B_MA12 <20>
DDR_B_MA13 <20>
DDR_B_MA14 <20>
DDR_B_MA15 <20>
DDR_B_MA16 <20>
DDR_B_BA0 <20>
DDR_B_BA1 <20>
DDR_B_BG0 <20>
DDR_B_BG1 <20>
DDR_B_ACT# <20>
DDR_B_DQS#0 <20>
DDR_B_DQS0 <20>
DDR_B_DQS#1 <20>
DDR_B_DQS1 <20>
DDR_B_DQS#2 <20>
DDR_B_DQS2 <20>
DDR_B_DQS#3 <20>
DDR_B_DQS3 <20>
DDR_B_DQS#4 <20>
DDR_B_DQS4 <20>
DDR_B_DQS#5 <20>
DDR_B_DQS5 <20>
DDR_B_DQS#6 <20>
DDR_B_DQS6 <20>
DDR_B_DQS#7 <20>
DDR_B_DQS7 <20>
DDR_B_ALERT# <20>
DDR_B_PARITY <20>
DDR_DRAMRST# <18,20>
1 2
RC17 121_0402_1%
1 2
RC18 80.6_0402_1%
1 2
RC19 100_0402_1%
< F o r ODT & VTT P o we r Control >
DDR_VTT_CNTL to DDR
VTT supplied ramped
<35uS
(tCPU18)
UC11
DDR_PG_CTRL
A A
5
NC1VCC
2
A
3
GND
74AUP1G07GW_TSSOP5
SA00005U600
Y
1
CC1
0.1U_0201_10V6K
@
2
5
4
+3VS+1.2V +1.2V
12
RC21
100K_0402_5%
DDR_DRAMRST#
DDR_VTT_PG_CTRL
Security Classificat ion
Security Classificat ion
Security Classificat ion
Is s u ed Date
Is s u ed Date
Is s u ed Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I N C . AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I N C . AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I N C . AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETEN T D IVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETEN T D IVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETEN T D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, IN C . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, IN C . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, IN C . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR DISCLOSED TO AN Y THIRD P A R T Y WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C .
MAY BE USED B Y OR DISCLOSED TO AN Y THIRD P A R T Y WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C .
4
MAY BE USED B Y OR DISCLOSED TO AN Y THIRD P A R T Y WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C .
3
2018/09/21 2019/09/21
2018/09/21 2019/09/21
2018/09/21 2019/09/21
Compal S ecret Data
Compal S ecret Data
Compal S ecret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
12
RC20
470_0402_5%
1
CC2
100P_0402_50V8J
ESD@
2
Clo se to CPU
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Tit le
Tit le
Tit le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
WHL-U(2/12)DDR4
WHL-U(2/12)DDR4
WHL-U(2/12)DDR4
LA-H101P
LA-H101P
Thursday, September 20, 2018
Thursday, September 20, 2018
Thursday, September 20, 2018
LA-H101P
51
51
51
7
7
7
of
of
1
of
0.A0.A0.A
5
4
3
2
1
+3VALW
1 2
RC23 100K_0201_5%
1 2
RC24 100K_0201_5%
1 2
RC25 100K_0201_5%
SOC_SPI_0_SI
SOC_SPI_0_IO2
SOC_SPI_0_IO3
SML0ALERT# (Internal Pull Down):
eSPI or LPC
0 = LPC is selected for EC ==> Default
1 = eSPI is selected for EC
D D
SOC_SPI_0_CLK
SOC_SPI_0_SO
SPI R O M
+3VS
1 2
RC26 10K_0402_5%
C C
+3VS
1 2
RC28 8.2K_0402_5%
KB_RST#
SERIRQ<34>
SERIRQ
SOC_SPI_0_SI
SOC_SPI_0_IO2
SOC_SPI_0_IO3
SOC_SPI_0_CS#0
SERIRQ
close to SPI ROM
SOC_SPI_0_SO
SOC_SPI_0_CLK SOC_SPI_0_CLK_R
SOC_SPI_0_SI
SOC_SPI_0_IO3
FromSOC
SOC_SPI_0_IO2
B B
FromE C
EC_SPI_CLK<34>
EC_SPI_MOSI<34>
EC_SPI_CS0#<34>
EC_SPI_MISO<34>
1 2
RC29 33_0402_5%
1 2
RC31 33_0402_5%EMI@
1 2
RC32 33_0402_5%
1 2
RC34 33_0402_5%
1 2
RC36 33_0402_5%
EC_SPI_CLK
EC_SPI_MOSI SOC_SPI_0_SI_R
EC_SPI_CS0#
EC_SPI_MISO
RC41 33_0402_5%EMI@
RC42 33_0402_5%
RC43 33_0402_5%
RC44 33_0402_5%
1 2
1 2
1 2
1 2
SOC_SPI_0_SO_R
SOC_SPI_0_SI_R
SOC_SPI_0_IO3_R
SOC_SPI_0_IO2_R
SOC_SPI_0_CLK_R
SOC_SPI_0_CS#0
SOC_SPI_0_SO_R
UC1E
CH37
SPI0_CLK
CF 37
SPI0_MISO
CF 36
SPI0_MOSI
CF 34
SPI 0_I O2
CG 34
SPI 0_I O3
CG 36
SPI0_CS0#
CG 35
SPI0_CS1#
CH34
SPI0_CS2#
CF 20
GPP_D1/SPI1_CLK/BK1/ SBK1
CG 22
GPP_D2/SPI1_MISO_I O1/BK2/SBK2
CF 22
GPP_D3/SPI1_MOSI_I O0/BK3/SBK3
CG 23
GPP_D21/SPI1_IO2
CH23
GPP_D22/SPI1_IO3
CG 20
GPP_D0/SPI1_CS0#/BK0/ SBK0
CH7
CL_CLK
CH8
CL_ DA TA
CH9
CL_ RS T#
BV29
GPP_A0/RCIN#/TIME_SYNC1
BV28
GPP_A6/SERIRQ
WHL-U_BGA1528
GPP_C5/SML0ALERT#
GPP_B23/SML1ALERT#/PCHHOT#
GPP_A1/LAD0/ESPI_I O0
GPP_A2/LAD1/ESPI_I O1
GPP_A3/LAD2/ESPI_I O2
GPP_A4/LAD3/ESPI_I O3
GPP_A5/LFRAME#/ESPI_CS#
GPP_A14/SUS_STAT#/ESPI_RESET #
GPP_A9/CLKOUT_LPC0/ESPI _CLK
GPP_A10/CLKOUT_LPC1
5 of 20
GPP_C0/SMBCLK
GPP_C1/SMBDATA
GPP_C2/SMBALERT#
GPP_C3/SML0CLK
GPP_C4/SML0DATA
GPP_C6/SML1CLK
GPP_C7/SML1DATA
GPP_A8/CLKRUN#
CK 14
CH15
CJ 15
CH14
CF 15
CG 15
CN15
CM1 5
CC34
CA 29
BY2 9
BY2 7
BV2 7
CA 28
CA 27
BV32
BV3 0
BY30
SOC_SMBCLK
SOC_SMBDATA
SOC_SMBALERT#
SOC_SML0CLK
SOC_SML0DATA
SOC_SML0ALERT#
SOC_SML1ALERT#
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
LPC_CLK0
PM_CLKRUN#KB_RST#
1 2
RC27 22_0402_5%EMI@
SOC_SMBCLK <20>
SOC_SMBDATA <20>
T8TP@
T9TP@
EC_SMB_CK2 <34>
EC_SMB_DA2 <34>
LPC_AD0 < 34>
LPC_AD1 < 34>
LPC_AD2 <34>
LPC_AD3 <34>
LPC_FRAME# <34>
EC_SMB_CK2
EC_SMB_DA2
SOC_SML1ALERT#
SOC_SMBCLK
SOC_SMBDATA
SOC_SML0CLK
SOC_SML0DATA
PM_CLKRUN#
SMB
(Link to DDR)
SML1
(Link to EC, Thermal Sensor)
CLK_LPC_EC <34>
PM_CLKRUN# <34>
1 2
RC30 1K_0402_5%
1 2
RC33 1K_0402_5%
1 2
RC35 150K_0402_5%@
1 2
RC37 1K_0402_5%
1 2
RC38 1K_0402_5%
1 2
RC39 1K_0402_5%
1 2
RC40 1K_0402_5%
1 2
RC45 8.2K_0402_5%
+3VS
< SPI RO M - 16M >
SOC_SPI_0_CS#0
SOC_SPI_0_IO2_R
A A
5
UC12
1
CS#
2
DO(IO1)
3
IO2
4
DI (I O0 )
GND
XM25QH128AHIG SOP 8P
VCC
CL K
IO
+3VALW
@
1 2
CC3 0.1U_0201_10V K X5R
8
SOC_SPI_0_IO3_RSOC_SPI_0_SO_R
7
SOC_SPI_0_CLK_R
6
SOC_SPI_0_SI_R
5
1
CC4
@EMI@
10P_0402_50V8J
2
4
Security Classification
Security Classification
Security Classification
2018/09/21 2019/09/21
2018/09/21 2019/09/21
Issued Date
Issued Date
Issued Date
THI S SHEET OF ENGINEERIN G DRAWING IS TH E PROPRI ETARY PR OPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
THI S SHEET OF ENGINEERIN G DRAWING IS TH E PROPRI ETARY PR OPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
THI S SHEET OF ENGINEERIN G DRAWING IS TH E PROPRI ETARY PR OPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET I NFORMATION.T HIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COM PETENT DIVISION OF R&D
AND TRADE SECRET I NFORMATION.T HIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COM PETENT DIVISION OF R&D
AND TRADE SECRET I NFORMATION.T HIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COM PETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEE T NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEE T NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEE T NOR T HE INFORMATION IT CONTAINS
MAYBE USED B Y OR DISCLOSED TO ANY THIRD P A R T Y WITHOUTPRIO R WRITTEN CONSENT OF COM PAL ELECTRONICS, INC.
MAYBE USED B Y OR DISCLOSED TO ANY THIRD P A R T Y WITHOUTPRIO R WRITTEN CONSENT OF COM PAL ELECTRONICS, INC.
MAYBE USED B Y OR DISCLOSED TO ANY THIRD P A R T Y WITHOUTPRIO R WRITTEN CONSENT OF COM PAL ELECTRONICS, INC.
2018/09/21 2019/09/21
3
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
WHL-U(3/12)SPI,SMB,LPC,ESPI
WHL-U(3/12)SPI,SMB,LPC,ESPI
WHL-U(3/12)SPI,SMB,LPC,ESPI
LA-H101P
LA-H101P
LA-H101P
1
o f
o f
o f
8 51Thursday, September 20, 2018
8 51Thursday, September 20, 2018
8 51Thursday, September 20, 2018
0.A0.A0.A
5
4
3
2
1
< HD A U D I O >
D D
HDA_BIT_CLK_R<33>
HDA_SYNC_R<33>
1 2
RC46 33_0402_5%
EMI@
1 2
RC48 33_0402_5%
1 2
RC47 33_0402_5%
< T o Enable ME Override>
1 2
ME_EN<34>
C C
+3VS
1 2
RC55 2.2K_0402_5%@
RC51 0_0402_5%@
HDA_SPKR
12
@
HDA_BIT_CLK
HDA_SYNC
HDA_SDOUT
RC49
499_0402_1%
HDA_SDOUT
HDA_SYNC
HDA_BIT_CLK
HDA_SDIN0<33>HDA_SDOUT_R<33>
CNV_RF_RESET#<31>
CLKREQ_CNV#<31>
HDA_SPKR<33>
HDA_SDOUT
CNV_RF_RESET#
HDA_SPKR
UC1G
BN3 4
HDA_SYNC/I2S0_SFRM
BN3 7
HDA_BCLK/I2S0_SCLK
BN3 6
HDA_SDO/I2S0_TXD
BN3 5
HDA_SDI0/I2S0_RXD
BL3 6
HDA_SDI1/I2S1_ RXD/SNDW1_DATA
BL3 5
HDA_RST#/I2S1_SCLK/SNDW1_CLK
CK 23
GPP_D23/I2S_MCLK
BL3 7
I2S1_SFRM/SNDW 2_CLK
BL3 4
I2S1_TXD/SNDW2_DATA
CJ 32
GPP_H1/I2S2_SFRM/CNV_BT_I 2S_BCLK/CNV_RF_RESET#
CH32
GPP_H0/I2S2_SCLK/CNV_BT_ I2S_SCLK
CH29
GPP_H2/I2S2_TXD/CNV_BT_I 2S_SDI/MODEM_CLKREQ
CH30
GPP_H3/I2S2_RXD/CNV_BT_I2S_SDO
CP 24
GPP_D19/DMIC_CLK0/SNDW4_CLK
CN24
GPP_D20/DMIC_DATA0/SNDW4_DATA
CK 25
GPP_D17/DMIC_CLK1/SNDW3_CLK
CJ 25
GPP_D18/DMIC_DATA1/SNDW3_DATA
CF 35
GPP_B14/SPKR
WHL-U_BGA1528
7 of 20
GPP_G0/SD_CMD
GPP_G1/SD3_DATA0
GPP_G2/SD3_DATA1
GPP_G3/SD3_DATA2
GPP_G4/SD_DATA3
GPP_G5/SD_CD#
GPP_G6/SD_CLK
GPP_G7/SD_WP
GPP_A17/SD_VDD1_PWR_EN# /ISH_GP7
GPP_A16/SD_1P8_SEL
SD_1P8_RCOMP
SD_3P3_RCOMP
CH36
CL 35
CL 36
CM3 5
CN35
CH35
CK 36
CK 34
BW 36
BY31
CK 33
CM3 4
SOC_SD_RCOMP
1 2
RC50 200_0402_1%
SPKR (Internal Pull Down):
TOP Swap Override
0 = Disable TOP Swap mode. ==> Default
1 = Enable TOP Swap Mode.
UC1I
CNV_CRX_DTX_N0<31>
1 2
RC5275K_0402_5% CNVi@
CNV_RF_RESET#
Follow Jefferson Peak schematic check list.
B B
1 2
RC164 1K_0402_5%@
WLBT_OFF#
CNV_CRX_DTX_P0<31>
CNV_CRX_DTX_N1<31>
CNV_CRX_DTX_P1<31>
CLK_CNV_CRX_DTX_N<31>
CLK_CNV_CRX_DTX_P<31>
CLK_CNV_CTX_DRX_N<31>
CLK_CNV_CTX_DRX_P<31>
For MX230
CNV_CTX_DRX_N0<31>
CNV_CTX_DRX_P0<31>
CNV_CTX_DRX_N1<31>
CNV_CTX_DRX_P1<31>
RC56
150_0402_1%
[11] GC6_FB_EN1V8
TP_INT#<35>
WLBT_OFF#<31>
1 2
CNVi@
1 2
RC57
10K_0402_5%
CNV_WT_RCOMP
GC6_FB_EN1V8
WLBT_OFF#
SOC_A4WP_PRESENT
CR30
CNV_WR_D0N
CP 30
CNV_WR_D0P
CM3 0
CNV_WR_D1N
CN30
CNV_WR_D1P
CN32
CNV_WT_D0N
CM3 2
CNV_WT_D0P
CP 33
CNV_WT_D1N
CN33
CNV_WT_D1P
CN31
CNV_WR_CLKN
CP 31
CNV_WR_CLKP
CP 34
CNV_WT_CLKN
CN34
CNV_WT_CLKP
CP 32
CNV_WT_RCOMP_0
CR32
CNV_WT_RCOMP_1
CP 20
GPP_F0/CNV_PA_BLANKI NG
CK 19
GPP_F1
CG 17
GPP_F2
CR14
GPP_C8/UART0_RXD
CP 14
GPP_C9/UART0_TXD
CN14
GPP_C10/UART0_RTS#
CM1 4
GPP_C11/UART0_CTS#
CJ 17
GPP_F8/CNV_MFUART2_RXD
CH17
GPP_F9/CNV_MFUART2_TXD
CF 17
GPP_F23/A4WP_ PRESENT
WHL-U_BGA1528
GPP_H18/CPU_C10_GATE#
GPP_H19/TIMESYNC_0
GPP_D4/IMGCLKOUT0/ BK4/SBK4
GPP_H20/IMGCLKOUT_1
GPP_F12/EMMC_DATA0
GPP_F13/EMMC_DATA1
GPP_F14/EMMC_DATA2
GPP_F15/EMMC_DATA3
GPP_F16/EMMC_DATA4
GPP_F17/EMMC_DATA5
GPP_F18/EMMC_DATA6
GPP_F19/EMMC_DATA7
GPP_F20/EMMC_RCLK
GPP_F21/EMMC_CLK
GPP_F11/EMMC_CMD
GPP_F22/EMMC_RESET#
EMMC_RCOMP
9 of 20
GPP_H21
GPP_H22
GPP_H23
GPP_F10
GPD7
GPP_F3
GPP_H21 XTAL frequency select.
0: 38.4 / 19.2 MHz
1: 24MHz XTAL select.
SOC_C10_GATE#
CN27
CM2 7
SOC_GPP_H21
CF 25
CN26
CM2 6
CK 17
SOC_GPD7
BV35
CN20
CG 25
XTAL INPUT MODE (HVM ONLY)
CH25
LOW: XTAL INPUT IS SINGLE ENDED
CR20
HIGH: XTAL IS ATTACHED
CM2 0
CN19
CM1 9
CN18
CR18
CP 18
CM1 8
CM1 6
CP 16
CR16
CN16
CK 15
1 2
RC53 4.7K_0201_5%
1 2
RC54 100K_0201_5%
SOC_SD_RCOMP
T10TP@
+3VALW
A A
T O D G P U
SOC_GPIO_C10 GPU_EVENT#
5
RC59
1
2
0_0402_5%
@
4
GPU_EVENT# [24 ]
Security Classification
Security Classification
Security Classification
2018/09/21 2019/09/21
2018/09/21 2019/09/21
Issued Date
Issued Date
Issued Date
THI S SHEET OF ENG INEERI NG DRAWING IS TH E PROPRI ETARY PR OPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THI S SHEET OF ENG INEERI NG DRAWING IS TH E PROPRI ETARY PR OPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THI S SHEET OF ENG INEERI NG DRAWING IS TH E PROPRI ETARY PR OPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET I NFORMATION.T HIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COM PETENT DIVISION OF R&D
AND TRADE SECRET I NFORMATION.T HIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COM PETENT DIVISION OF R&D
AND TRADE SECRET I NFORMATION.T HIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COM PETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEE T NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEE T NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEE T NOR T HE INFORMATION IT CONTAINS
MAYBE USED B Y OR DISCLOSED TO ANY THIRD P A R T Y WITHOUTPRIO R WRITTEN CONSENT OF COM PAL ELECTRONICS, INC.
MAYBE USED B Y OR DISCLOSED TO ANY THIRD P A R T Y WITHOUTPRIO R WRITTEN CONSENT OF COM PAL ELECTRONICS, INC.
MAYBE USED B Y OR DISCLOSED TO ANY THIRD P A R T Y WITHOUTPRIO R WRITTEN CONSENT OF COM PAL ELECTRONICS, INC.
2018/09/21 2019/09/21
3
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
WHL-U(4/12)HDA,EMMC,SDIO,CSI2
WHL-U(4/12)HDA,EMMC,SDIO,CSI2
WHL-U(4/12)HDA,EMMC,SDIO,CSI2
LA-H101P
LA-H101P
Thursday, September 20, 2018
Thursday, September 20, 2018
Thursday, September 20, 2018
LA-H101P
9
9
9
1
51
51
51
o f
o f
o f
0.A0.A0.A
5
4
3
2
1
+3VS
10K_0402_5%
SE00000UC00
SE00000UC00
SYS_RESET#
EC_RSMRST#
SYS_PWROK
CLKREQ_PCIE#1
CLKREQ_PCIE#3
CLKREQ_PCIE#4
SOC_SRTCRST#
SOC_RTCRST#
CLR CMOS
SM_INTRUDER#
SYS_RESET#
PCH_PWROK
EC_RSMRST#
WAKE#
+1.05V_VCCST
1 2
RC72 0_0402_5%@
12
RC89
1K_0402_5%
1 2
RC90 60.4_0402_1%
1
CC15
100P_0402_50V8J
ESD@
2
Card Reader
EC_VCCST_PG
1 2
RC61 10K_0402_5%
1 2
RC63 10K_0402_5%
1 2
RC64
D D
+3VL_RTC
C C
B B
1 2
RC68 10K_0402_5%@
1 2
RC70 20K_0402_5%
1 2
CC5 1U_0201_6.3V6M
1 2
RC71 20K_0402_5%
1 2
CC6 1U_0201_6.3V6M
1 2
CLRP1 SHORT PADS
1 2
RC75 1M_0402_5%
+3VALW
1 2
RC77 10K_0402_5%
1 2
RC78 10K_0402_5%
1 2
RC79 10K_0402_5%
1 2
ESD@
CC10 100P_0402_50V8J
1 2
ESD@
CC11 100P_0402_50V8J
1 2
ESD@
CC12 100P_0402_50V8J
+3VALW
1 2
RC82 1K_0402_5%
Fro m EC (Open-Drain)
VCCST_PWRGD<34>
A A
5/9 Naming Rule
DGPU
SSD
[21] CLK_PEG_N0
[21] CLK_PEG_P0
[21] CLKREQ_PEG#0
<32>
WLAN
EC_CLEAR_CMOS# <34>
EC_RSMRST#<34>
T11 TP@
SYS_PWROK<34>
PCH_PWROK<34>
CLK_PCIE_N1
CLK_PCIE_P1<32>
CLKREQ_PCIE#1<32>
CLK_PCIE_N3<31>
CLK_PCIE_P3<31>
CLKREQ_PCIE#3<31>
CLK_PCIE_N4<37>
CLK_PCIE_P4<37>
CLKREQ_PCIE#4<37>
SOC_PLTRST#
SYS_RESET#
EC_RSMRST#
H_CPUPWRGD
EC_VCCST_PG
SYS_PWROK
PCH_PWROK
EC_RSMRST#
WAKE#
UC1J
AW2
CLKREQ_PEG#0
CLKREQ_PCIE#1
CLKREQ_PCIE#3
CLKREQ_PCIE#4
CF3 2
CE3 2
CF3 0
CE3 1
CE3 0
CF3 1
AY3
BC1
BC2
BD3
BC3
BH3
BH4
BA1
BA2
BE1
BE2
WHL-U_BGA1528
< PCH PLTRSTBuffer >
SOC_PLTRST#
BJ35
CN1 0
BR36
CR1 0
BP30
BV34
BY32
BU30
BU32
BU34
1 2
RC76 0_0402_5%
UC1K
GPP_B13/PLTRST#
SYS_RESET#
RSM RST #
AR2
PROCPWRGD
BJ2
VCCST_PWRGOOD
SYS_PWROK
BP31
PCH_PWROK
DSW_PWROK
GPP_A13/SUSWARN#/SUSPWRDACK
GPP_A15/SUSACK#
WAKE#
GPD2/LAN_WAKE#
GPD11/LANPHYPC
WHL-U_BGA1528
CLKOUT_PCIE_N_0
CLKOUT_PCIE_P_0
GPP_B5/SRCCLKREQ0#
CLKOUT_PCIE_N_1
CLKOUT_PCIE_P_1
GPP_B6/SRCCLKREQ1#
CLKOUT_PCIE_N_2
CLKOUT_PCIE_P_2
GPP_B7/SRCCLKREQ2#
CLKOUT_PCIE_N_3
CLKOUT_PCIE_P_3
GPP_B8/SRCCLKREQ3#
CLKOUT_PCIE_N_4
CLKOUT_PCIE_P_4
GPP_B9/SRCCLKREQ4#
CLKOUT_PCIE_N_5
CLKOUT_PCIE_P_5
GPP_B10/SRCCLKREQ5#
10 of 2 0
12
RC80
100K_0402_5%
GPP_B11/EXT_PW R_GATE#
11 of 20
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P
GPD8/SUSCLK
CLK_BIASREF
CLKIN_XTAL
12
CC9
100P_0402_50V8J
GPP_B12/SLP_S0#
GPD4/SLP_S3#
GPD5/SLP_S4#
GPD10/SLP_S5#
SLP_SUS#
SLP_LAN#
GPD9/SLP_WLAN#
GPD6/SLP_A#
GPD3/PW RBTN#
GPD1/ACPRESENT
GPD0/BATLOW#
INTRUDER#
GPP_B2/VRALERT#
INPUT3VSEL
XTAL_IN
XTAL_OUT
RTC X1
RTC X2
SRTCRST#
RTC RST #
PCI_RST# <31,32,34,37>
ESD@
BJ37
BU36
BU27
BT29
BU29
BT31
BT30
BU37
BU28
BU35
BV36
BR35
CC3 7
CC3 6
BT27
AU1
AU2
BT32
CK3
CK2
CJ 1
CM3
BN31
BN32
BR37
BR34
PM_SLP_S0#
PM_SLP_S3#
PM_SLP_S4#
PM_SLP_S5#
SLP_WLAN#
PM_SLP_A#
PBTN_OUT#
AC_PRESENT_R
PM_BATLOW#
SM_INTRUDER#
SOC_VRALERT#
SOC_INPUT3VSEL
33E_SOC_XTAL24_IN_R
33E_SOC_XTAL24_OUT_R
XCLK_BIASREF
CLKIN_XTAL
SOC_RTCX1
SOC_RTCX2
SOC_SRTCRST#
SOC_RTCRST#
RC83 0_0402_5%@
SUSCLK <31>
CLKIN_XTAL <31>
T12TP@
PM_SLP_S3# <34>
PM_SLP_S4# <34,42,45>
T13TP@
T14TP@
T15TP@
1 2
33E_SOC_XTAL24_IN_R
33E_SOC_XTAL24_OUT_R
XCLK_BIASREF
CLKIN_XTAL
Follow CFL-U PDG_Rev_0.7
Stuff 60.4 ohm(RC110) PD for CNL-U/ WHL-U and CFL-U
RC69 33_0201_5%EMI@
RC73 33_0201_5%EMI@
SOC_RTCX2
SOC_RTCX1
PBTN_OUT# <34>
AC_PRESENT <34>
RC60
RC65
1 2
LC1
@EMI@
1
1
4
4
DLM0NSN900HY2D_4P
1 2
1 2
60.4_0402_1%
1 2
10K_0402_5%
33E_SOC_XTAL24_IN
2
2
3
3
33E_SOC_XTAL24_OUT
1 2
RC81 10M_0402_5%
YC 2
1 2
32.768KHZ_9PF_X1A000141000200
SJ10000PW00
1
CC13
8.2P_0402_50V8B
2
PM_BATLOW#
AC_PRESENT
SOC_VRALERT#
SOC_INPUT3VSEL
1 2
RC74 200K_0402_1%
YC 1
24MHZ_18PF_XRCGB24M000F2P51R0
SJ10000UJ00
3
3
NC
NC
27P_0402_50V8J
CC7
1
2
1 2
RC84 8.2K_0402_5%
1 2
RC85 10K_0402_5%@
1 2
RC86 10K_0402_5%@
1 2
RC87 4.7K_0402_5%@
1 2
RC88 4.7K_0402_5%
2
4
1
1
1
CC14
8.2P_0402_50V8B
2
+3VALW
27P_0402_50V8J
CC8
1
2
Security Classificat ion
Security Classificat ion
Security Classificat ion
Is s u ed Date
Is s u ed Date
Is s u ed Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I N C . AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I N C . AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I N C . AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETEN T D IVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETEN T D IVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETEN T D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, IN C . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, IN C . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, IN C . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR DISCLOSED TO AN Y THIRD P A R T Y WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C .
MAY BE USED B Y OR DISCLOSED TO AN Y THIRD P A R T Y WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C .
5
4
MAY BE USED B Y OR DISCLOSED TO AN Y THIRD P A R T Y WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C .
3
2018/09/21 2019/09/21
2018/09/21 2019/09/21
2018/09/21 2019/09/21
Compal S ecret Data
Compal S ecret Data
Compal S ecret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Tit le
Tit le
Tit le
WHL-U(5/12)CLK,PM,GPIO
WHL-U(5/12)CLK,PM,GPIO
WHL-U(5/12)CLK,PM,GPIO
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
2
Date: Sheet
LA-H101P
LA-H101P
LA-H101P
1
10 51Thursday, September 20, 2018
10 51Thursday, September 20, 2018
10 51Thursday, September 20, 2018
0.A0.A0.A
of
of
of
5
4
3
2
1
GSPI0_MOSI(Internal Pull Down):
No R e b o o t
0 = DisableNo R e b o o t mode. ==> Default
1 = Enable No R e b o o t Mode. (PCH will disable the TCO
Timers y s t e m re b o ot fe a t u re ) . This funct i oni s u s e f u l
when running ITP/X DP.
D D
GSPI1_MOSI (Internal Pull Down):
Boo t BI OS Strap B it
0 = SPI Mode ==> Default
1 = LPC Mode
+3VS
1 2
RC97 4.7K_0402_5%@
1 2
RC98 150K_0402_5%@
C C
+3VS
1 2
RC166 2.2K_0402_5%
1 2
RC167 2.2K_0402_5%
1 2
RC102 10K_0402_5%
1 2
RC163 4.7K_0402_5%
1 2
RC103 49.9K_0402_1%
1 2
RC108 49.9K_0402_1%
1 2
RC109 2.2K_0402_5%
1 2
RC105 2.2K_0402_5%
1 2
RC113 20K_0201_5%@
1 2
RC114 20K_0201_5%@
GSPI0_MOSI
GSPI1_MOSI
I2C1_SDA_TS
I2C1_SCL_TS
SOC_GPIO_A7
TS_INT#
UART0_RX
UART0_TX
I2C_0_SDA
I2C_0_SCL
CNV_RGI_CRX_DTX
Place close to PCH
B B
for RMT test
+1.8VALW
RC162 20K_0201_5%@
12
CNV_RGI_CTX_DRX
T o u c h P ad
T o u c h P an el
E C sensor Hub
SENSOR_EC_INT<34>
CNV_BRI_CRX_DTX<31>
CNV_RGI_CTX_DRX<31>
CNV_BRI_CTX_DRX<31>
CNV_RGI_CRX_DTX<31>
UART0_RX<31>
UART0_TX<31>
I2C_0_SDA<35>
I2C_0_SCL<35>
I2C1_SDA_TS<28>
I2C1_SCL_TS<28>
I2C_2_SDA<34>
I2C_2_SCL<34>
Capacity
Description
WITHOUT ON-BOARD RAM
HYNIX 2666MHz (H5AN8G6NCJR-VKC)S340
MICRON 2666MHz (MT40A512M16LY-075:E)S340
4GB
MICRON 2666MHz (MT40A512M16LY-075:E)C340
SAMSUNG 2666MHz (K4A8G165WC-BCTD)S340
SAMSUNG 2666MHz (K4A8G165WC-BCTD)C340
N/A
Capacity
Description
WITHOUT ON-BOARD RAM
SAMSUNG 2666MHz (K4A8G165WC-BCTD)
HYNIX 2666MHz (H5AN8G6NCJR-VKC)
MICRON 2666MHz (MT40A512M16LY-075:E)
4GB
N/A
N/A
N/A
N/A
SOC_GPIO_A7
GSPI0_MOSI
OBRAM_ID0
OBRAM_ID1
OBRAM_ID2
GSPI1_MOSI
CNV_BRI_CRX_DTX
CNV_RGI_CTX_DRX
CNV_RGI_CRX_DTXCNV_BRI_CRX_DTX
UART0_RX
UART0_TX
CC2 7
CC3 2
CE2 8
CE2 7
CE2 9
CA3 1
CA3 2
CC2 9
CC3 0
CA3 0
CK2 0
CG1 9
CH1 9
CR1 2
CP1 2
CN1 2
CM1 2
CM1 1
CN1 1
CK1 2
CF2 7
CH2 7
CJ 20
CJ 12
CJ 30
X76
NO_MD@
X7680438L81
X7680538LA1HYNIX 2666MHz (H5AN8G6NCJR-VKC)C340
X7680438L82
X7680538LA2
X7680438L83
X7680538LA3
N/A N/A
GPP_B19
OBRAM_ID0 OBRAM_ID1 OBRAM_ID2
0
0 0 1
0 1 0
0 1 1
1
1 0 1
1 1 0
1 1 1
UC1F
GPP_B15/GSPI0_CS0#
GPP_A7/PIRQA#/GSPI 0_CS1#
GPP_B16/GSPI0_CLK
GPP_B17/GSPI0_MISO
GPP_B18/GSPI0_MOSI
GPP_B19/GSPI1_CS0#
GPP_A11/PME#/GSPI1_CS1#/ SD_VDD2_PWR_EN#
GPP_B20/GSPI1_CLK
GPP_B21/GSPI1_MISO
GPP_B22/GSPI1_MOSI
GPP_F5/CNV_BRI_RSP
GPP_F6/CNV_RGI_DT
GPP_F4/CNV_BRI_DT
GPP_F7/CNV_RGI_RSP
GPP_C20/UART2_RXD
GPP_C21/UART2_TXD
GPP_C22/UART2_RTS#
GPP_C23/UART2_CTS#
GPP_C16/I2C0_SDA
GPP_C17/I2C0_SCL
GPP_C18/I2C1_SDA
GPP_C19/I2C1_SCL
GPP_H4/I2C2_SDA
CF2 9
GPP_H5/I2C2_SCL
GPP_H6/I2C3_SDA
CH2 8
GPP_H7/I2C3_SCL
GPP_H8/I2C4_SDA
CJ 31
GPP_H9/I2C4_SCL
WHL-U_BGA1528
PART NUMBER(R1)
N/A
SA0000BMN00
SA0000ARD20
SA0000B6F00
GPP_B20
GPP_B21
0 0
0 0
GPP_D9/ISH_SPI_CS#/GS PI2_CS0#
GPP_D10/ISH_SPI_CLK/GS PI2_CLK
GPP_D11/ISH_SPI_MISO/ GSPI2_MISO
GPP_D12/ISH_SPI_MOSI/ GSPI2_MOSI
GPP_D5/ISH_I 2C0_SDA
GPP_D6/ISH_I2C0_SCL
GPP_D7/ISH_I 2C1_SDA
GPP_D8/ISH_I2C1_SCL
GPP_H10/I2C5_SDA/ISH_I2C2_S DA
GPP_D13/ISH_UART0_RXD/SML0BDATA/I 2C4B_SDA
GPP_A12/ISH_GP6/BM_BUSY#/ SX_EXIT_HOLDOFF#
6 of 20
GPP_H11/I2C5_SCL/ISH_I2C2_SCL
GPP_D14/ISH_UART0_TXD/SML0BCLK/I 2C4B_SCL
GPP_D15/ISH_UART0_RTS#/GSPI 2_CS1#
GPP_D16/ISH_UART0_CTS#/SML0BALERT#
GPP_C12/UART1_RXD/ISH_UART1_RXD
GPP_C13/UART1_TXD/ISH_UART1_TXD
GPP_C14/UART1_RTS#/ISH_UART1_RTS#
GPP_C15/UART1_CTS#/ISH_UART1_CTS#
GPP_A18/ISH_GP0
GPP_A19/ISH_GP1
GPP_A20/ISH_GP2
GPP_A21/ISH_GP3
GPP_A22/ISH_GP4
GPP_A23/ISH_GP5
+3VS+3VS +3VS
12
RC91
10K_0402_5%
@
OBRAM_ID0 OBRAM_ID1 OBRAM_ID2
12
RC94
10K_0402_5%
@
RC94 NO_MD@
10K_0402_5%
CN22
CR22
CM2 2
CP2 2
CK2 2
CH20
CH22
CJ 22
CJ 27
CJ 29
CM2 4
CN23
CM2 3
CR24
CG1 2
CH12
CF1 2
CG1 4
BW35
BW34
CA3 7
CA3 6
CA3 5
CA3 4
BW37
12
RC92
10K_0402_5%
@
12
RC95
10K_0402_5%
@
RC95 NO_MD@
10K_0402_5%
MODEL_SETTING3
MODEL_SETTING2
MODEL_SETTING0
MODEL_SETTING1
DGPU_PWR_EN
DGPU_HOLD_RST #
GPU_ALL_PGOOD
DGPU_PRSNT
TS_INT#
DGPU_SEL0
DGPU_SEL1
12
12
RC93
10K_0402_5%
@
RC96
10K_0402_5%
@
RC96 NO_MD@
10K_0402_5%
DGPU_PWR_EN [26]
DGPU_HOLD_RST# [21]
GPU_ALL_PGOOD [2 6]
TS_INT# [2 8]
Function
Arrary MIC
MODEL_SETTING2
(GPP_D10)
Single MIC
+3VS
Function
C340-15
Arrary_MIC@
1 2
RC168
1 2
RC169 10K_0402_5%
Single_MIC@
MODEL_SETTING1
(GPP_D12)
S340-15
S340-14
+3VS
+3VS
Function
DIS 0
1 2
RC99 10K_0402_5%@
1 2
RC100 10K_0402_5%C340@
RC100 S340_15@
10K_0402_5%
@
1 2
RC107 10K_0402_5%
1 2
RC104 10K_0402_5%C340@
RC107 S340_15@
10K_0402_5%
DGPU_PRSNT
(GPP_C15)
UMA Only
+3VS+1.8VALW
1 2
RC115 10K_0402_5%
1
0
10K_0402_5%
MODEL_SETTING0
(GPP_D11)
0
0
1 0
RC99 S340_14@
10K_0402_5%
RC104S340_14@
10K_0402_5%
1
DGPU_PRSNT
MODEL_SETTING2
0
1
MODEL_SETTING1
MODEL_SETTING0
6 Layer / 8 Layer PCB
+3VS
1 2
RC171 10K_0402_5%@
1 2
RC172 10K_0402_5%@
A A
[9] GC6_FB_EN1V8
SOC_GPIO_B16 GC6_FB_EN
GC6_FB_EN1V8
5
1 2
RC121 0_0201_5%
N16S@
1 2
RC122 0_0201_5%
N17S@
GC6_FB_EN [24,25]
4
TO DG P U
Security Classificat ion
Security Classificat ion
Security Classificat ion
Is s u ed Date
Is s u ed Date
Is s u ed Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPALELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPALELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPALELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETEN T D IVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETEN T D IVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETEN T D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, IN C . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, IN C . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, IN C . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR DISCLOSED TO AN Y THIRD P A R T Y WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C .
MAY BE USED B Y OR DISCLOSED TO AN Y THIRD P A R T Y WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C .
MAY BE USED B Y OR DISCLOSED TO AN Y THIRD P A R T Y WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C .
3
2018/09/21 2019/09/21
2018/09/21 2019/09/21
2018/09/21 2019/09/21
Compal S ecret Data
Compal S ecret Data
Compal S ecret Data
MODEL_SETTING3
Deciphered Date
Deciphered Date
Deciphered Date
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Tit le
Tit le
Tit le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
WHL-U(6/12)GPIO,I2C,GSPI
WHL-U(6/12)GPIO,I2C,GSPI
WHL-U(6/12)GPIO,I2C,GSPI
LA-H101P
LA-H101P
LA-H101P
1
11 51Thursday, September 20, 2018
11 51Thursday, September 20, 2018
11 51Thursday, September 20, 2018
of
of
of
0.A0.A0.A
5
4
3
2
1
D D
dGPU
Card Reader
C C
NGFF WLAN+BT
HDD
SSD1
B B
Colay SATA
[21] PCIE_CRX_DTX_N5
[21] PCIE_CRX_DTX_P5
[21] PCIE_CTX_C_DRX_N5
[21] PCIE_CTX_C_DRX_P5
[21] PCIE_CRX_DTX_N6
[21] PCIE_CRX_DTX_P6
[21] PCIE_CTX_C_DRX_N6
[21] PCIE_CTX_C_DRX_P6
[21] PCIE_CRX_DTX_N7
[21] PCIE_CRX_DTX_P7
[21] PCIE_CTX_C_DRX_N7
[21] PCIE_CTX_C_DRX_P7
[21] PCIE_CRX_DTX_N8
[21] PCIE_CRX_DTX_P8
[21] PCIE_CTX_C_DRX_N8
[21] PCIE_CTX_C_DRX_P8
PCIE_CRX_DTX_N9<37>
PCIE_CRX_DTX_P9<37>
PCIE_CTX_DRX_N9<37>
PCIE_CTX_DRX_P9<37>
PCIE_CRX_DTX_N11<31>
PCIE_CRX_DTX_P11<31>
PCIE_CTX_DRX_N11<31>
PCIE_CTX_DRX_P11<31>
SATA_CRX_DTX_N1<32>
SATA_CRX_DTX_P1<32>
SATA_CTX_DRX_N1<32>
SATA_CTX_DRX_P1<32>
PCIE_CRX_DTX_N13<32>
PCIE_CRX_DTX_P13<32>
PCIE_CTX_DRX_N13<32>
PCIE_CTX_DRX_P13<32>
PCIE_CRX_DTX_N14<32>
PCIE_CRX_DTX_P14<32>
PCIE_CTX_DRX_N14<32>
PCIE_CTX_DRX_P14<32>
PCIE_CRX_DTX_N15<32>
PCIE_CRX_DTX_P15<32>
PCIE_CTX_DRX_N15<32>
PCIE_CTX_DRX_P15<32>
SATA_CRX_DTX_N2<32>
SATA_CRX_DTX_P2<32>
SATA_CTX_DRX_N2<32>
SATA_CTX_DRX_P2<32>
1
CC17 DIS@
1
CC18 DIS@
1
CC19 DIS@
1
CC20 DIS@
1
CC16 DIS@
1
CC21 DIS@
1
CC22 DIS@
1
CC23 DIS@
1 2
RC126 100_0402_1%
2
0.22U_0201_6.3V6M
2
0.22U_0201_6.3V6M
2
0.22U_0201_6.3V6M
2
0.22U_0201_6.3V6M
2
0.22U_0201_6.3V6M
2
0.22U_0201_6.3V6M
2
0.22U_0201_6.3V6M
2
0.22U_0201_6.3V6M
PCIE_RCOMPN
PCIE_RCOMPP
PCIE_CTX_DRX_N5
PCIE_CTX_DRX_P5
PCIE_CTX_DRX_N6
PCIE_CTX_DRX_P6
PCIE_CTX_DRX_N7
PCIE_CTX_DRX_P7
PCIE_CTX_DRX_N8
PCIE_CTX_DRX_P8
UC1H
BW 9
PCIE5_RXN/USB31_5_RX N
BW 8
PCIE5_RXP/USB31_5_RXP
BW 4
PCIE5_TXN/USB31_5_TXN
BW 3
PCIE5_TXP/USB31_5_TXP
BU6
PCIE6_RXN/USB31_6_RX N
BU5
PCIE6_RXP/USB31_6_RXP
BU4
PCIE6_TXN/USB31_6_ TXN
BU3
PCIE6_TXP/USB31_6_TXP
BT7
PCIE7_RXN
BT6
PCIE7_RXP
BU2
PCI E7_ TXN
BU1
PCI E7_ TXP
BU9
PCIE8_RXN
BU8
PCIE8_RXP
BT4
PCI E8_ TXN
BT3
PCI E8_ TXP
BP5
PCIE9_RXN
BP6
BR2
PCI E9_ TXN
BR1
PCI E9_ TXP
BN6
PCIE10_RXN
BN5
BR4
PCIE10_TXN
BR3
PCIE10_TXP
BN1 0
PCIE11_RXN/SATA0_RXN
BN8
PCIE11_RXP/SATA0_RXP
BN4
PCIE11_TXN/SATA0_TXN
BN3
PCIE11_TXP/SATA0_TXP
BL6
PCIE12_RXN/SATA1A_RXN
BL5
PCIE12_RXP/SATA1A_RXP
BN2
PCIE12_TXN/SATA1A_TXN
BN1
PCIE12_TXP/SATA1A_TXP
BK6
PCIE13_RXN
BK5
PCIE13_RXP
BM4
PCIE13_TXN
BM3
PCIE13_TXP
BJ6
PCIE14_RXN
BJ5
PCIE14_RXP
BL2
PCIE14_TXN
BL1
PCIE14_TXP
BG5
PCIE15_RXN/SATA1B_RXN
BG6
PCIE15_RXP/SATA1B_RXP
BL4
PCIE15_TXN/SATA1B_TXN
BL3
PCIE15_TXP/SATA1B_TXP
BE5
PCIE16_RXN/SATA2_RXN
BE6
PCIE16_RXP/SATA2_RXP
BJ4
PCIE16_TXN/SATA2_TXN
BJ3
PCIE16_TXP/SATA2_TXP
CE 6
PCIE_RCOMP_N
CE 5
PCIE_RCOMP_P
CR28
GPP_H12/M2_SKT2/CFG_0
CP 28
GPP_H13/M2_SKT2/CFG_1
CN28
GPP_H14/M2_SKT2/CFG_2
CM2 8
GPP_H15/M2_SKT2/CFG_3
PCIE9_RXP
PCIE10_RXP
WHL-U_BGA1528
When PCIE16/SATA2 is used as SATA P o r t 1 (ODD), then
PCIE15/SATA1B (M.2 SSD) cannot be used as SATA P o r t 1.
PCIE2_RXN/USB31_2_ RXN/SSIC_1_RXN
PCIE2_RXP/USB31_2_RXP/SSIC_1_RXP
PCIE2_TXN/USB31_2_TXN/SSI C_1_TXN
PCIE2_TXP/USB31_2_TXP/SSIC_1_TXP
GPP_E9/USB2_OC0#/G P_BSSB_CLK
GPP_E10/USB2_OC1#/G P_BSSB_DI
GPP_E0/SATAXPCIE0/SATAGP0
GPP_E1/SATAXPCIE1/SATAGP1
GPP_E2/SATAXPCIE2/SATAGP2
GPP_E8/SATALED#/SPI1_CS1#
8 of 20
PCIE1_RXN/USB31_1_RXN
PCIE1_RXP/USB31_1_RXP
PCIE1_TXN/USB31_1_TXN
PCIE1_TXP/USB31_1_TXP
PCIE3_RXN/USB31_3_ RXN
PCIE3_RXP/USB31_3_RXP
PCIE3_TXN/USB31_3_TXN
PCIE3_TXP/USB31_3_TXP
PCIE4_RXN/USB31_4_ RXN
PCIE4_RXP/USB31_4_RXP
PCIE4_TXN/USB31_4_TXN
PCIE4_TXP/USB31_4_TXP
USB2_1N
USB2_1P
USB2_2N
USB2_2P
USB2_3N
USB2_3P
USB2_4N
USB2_4P
USB2_5N
USB2_5P
USB2_6N
USB2_6P
USB2_7N
USB2_7P
USB2_8N
USB2_8P
USB2_9N
USB2_9P
USB2_10N
USB2_10P
USB 2_C OMP
USB 2_I D
USB2_VBUSSENSE
GPP_E11/USB2_OC2#
GPP_E12/USB2_OC3#
GPP_E4/DEVSLP0
GPP_E5/DEVSLP1
GPP_E6/DEVSLP2
UFS_RESET#
CB 5
CB 6
CA 4
CA 3
BY8
BY9
CA 2
CA 1
BY7
BY6
BY4
BY3
BW 6
BW 5
BW 2
BW 1
CE 3
CE 4
CE 1
CE 2
CG 3
CG 4
CD3
CD4
CG 5
CG 6
CC1
CC2
CG 8
CG 9
CB 8
CB 9
CH5
CH6
CC3
CC4
CC5
CE 8
CC6
CK 6
CK 5
CK 8
CK 9
CP 8
CR8
CM8
CN8
CM1 0
CP 10
CN7
AR3
USB2_COMP
USB2_ID
USB2_SENSE
USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
WL_OFF#
NGFF_SSD_PEDET
USB3_CRX_DTX_N1 <37>
USB3_CRX_DTX_P1 <37>
USB3_CTX_DRX_N1 <37>
USB3_CTX_DRX_P1 <37>
USB3_CRX_DTX_N2 <37>
USB3_CRX_DTX_P2 <37>
USB3_CTX_DRX_N2 <37>
USB3_CTX_DRX_P2 <37>
USB3_CRX_MTX_N3 <38>
USB3_CRX_MTX_P3 <38>
USB3_CTX_MRX_N3 <38>
USB3_CTX_MRX_P3 <38>
USB20_N1 <37>
USB20_P1 <37>
USB20_N2 <37>
USB20_P2 <37>
USB20_N3 <38>
USB20_P3 <38>
USB20_N4 <28>
USB20_P4 <28>
USB20_N6 <28>
USB20_P6 <28>
USB20_N7 <35>
USB20_P7 <35>
USB20_N10 <31>
USB20_P10 <31>
1 2
RC123 113_0402_1%
1 2
RC124 1K_0402_5%@
1 2
RC125 1K_0402_5%@
USB_OC0# <37>
USB_OC1# <37>
WL_OFF# <31>
DEVSLP2 <32>
NGFF_SSD_PEDET <32>
USB2.0 / 3.0 Port (IO - 1)
USB2.0 / 3.0 Port (IO - 2)
USB2.0 / 3.0 Port (Type-C)
USB2.0 / 3.0 Port (MB - 1)
USB2.0 / 3.0 Port (MB - 2)
USB2.0 / 3.0 Port (Type-C)
Touch Screen
Camera
FP
NGFF WLAN+BT
Trace length max: 450mils
WL_OFF#
USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
1 2
RC165 1K_0402_5%@
RC127 10K_0201_5%
RC128 10K_0201_5%
RC129 10K_0201_5%
RC130 10K_0201_5%
+3VALW
12
12
12
12
+3VS
A A
Security Classification
Security Classification
Security Classification
2018/09/21 2019/09/21
2018/09/21 2019/09/21
Issued Date
Issued Date
Issued Date
THI S SHEET OF ENG INEERI NG DRAWING IS TH E PROPRI ETARY PR OPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THI S SHEET OF ENG INEERI NG DRAWING IS TH E PROPRI ETARY PR OPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THI S SHEET OF ENG INEERI NG DRAWING IS TH E PROPRI ETARY PR OPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET I NFORMATION.T HIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COM PETENT DIVISION OF R&D
AND TRADE SECRET I NFORMATION.T HIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COM PETENT DIVISION OF R&D
AND TRADE SECRET I NFORMATION.T HIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COM PETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEE T NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEE T NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEE T NOR T HE INFORMATION IT CONTAINS
MAYBE USED B Y OR DISCLOSED TO ANY THIRD P A R T Y WITHOUTPRIO R WRITTEN CONSENT OF COM PAL ELECTRONICS, INC.
MAYBE USED B Y OR DISCLOSED TO ANY THIRD P A R T Y WITHOUTPRIO R WRITTEN CONSENT OF COM PAL ELECTRONICS, INC.
MAYBE USED B Y OR DISCLOSED TO ANY THIRD P A R T Y WITHOUTPRIO R WRITTEN CONSENT OF COM PAL ELECTRONICS, INC.
5
4
2018/09/21 2019/09/21
3
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
NGFF_SSD_PEDET
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
WHL-U(7/12)PCIE,USB,SATA
WHL-U(7/12)PCIE,USB,SATA
WHL-U(7/12)PCIE,USB,SATA
1 2
RC131 10K_0402_5%
LA-H101P
LA-H101P
LA-H101P
12 51Thursday, September 20, 2018
12 51Thursday, September 20, 2018
12 51Thursday, September 20, 2018
1
o f
o f
o f
0.A0.A0.A
5
+1.05VALW TO +1.05V_VCCST
D D
SYSON<34,44>
SUSP#<34,39,44>
1 2
RC134 0_0402_5%@
1 2
RC135 0_0402_5%@
+1.8VALW TO +1.8VS
+VL
1
C C
@
2
+1.05VS_VCCIO
0.1U_0201_10V K X5R
CC29
SUSP#
+1.05VALW
1
2
1U_0201_6.3V6M
CC30
+VL
1U_0201_6.3V6M
1
CC24
2
+1.05VALW
EN_1.05V_VCCSTU
EN_1.8VS
+1.8VALW
I(Max) : 0.2 A(+1.8VS)
RON(Max) : 25 mohm
V drop : 0.005 V
+1.05VALW TO +1.05VS_VCCIO
I(Max) : 3.675 A(+1.05VS_VCCIO)
RON(Max) : 6.2 mohm
V drop : 0.019 V
UC15
1
VIN 1
2
VIN 2
7
VIN thermal
3
VBIAS
4
ON
EM5201V_DFN8_3X3
SA00008R600
VOU T
GND
6
5
PSC SideBSC Side
B B
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1
CC39
2
1
1
CC40
2
2
1U_0201_6.3V6M
1
CC41
CC42
2
10U_0402_6.3V6M
10U_0402_6.3V6M
1
1
CC43
2
2
4
I(Max) : 0.16 A(+1.05V_VCCST)
RON(Max) : 25 mohm
V drop : 0.004 V
UC14
+1.05VS_VCCIO_STG
10U_0402_6.3V6M
@
1
CC45
CC44
2
1
2
3
4
5
6
7
+1.05VS_VCCIO +1.05VS_VCCSTG
VOU T1
VIN 1
VOU T1
VIN 1
ON1
VBIAS
ON2
VIN 2
VIN 2
AOZ1331 DFN 14P
SA0000BKC00
1
2
GND
VOU T2
VOU T2
GPAD
RC139 0_0402_5%
10U_0402_6.3V6M
10U_0402_6.3V6M
@
1
CC46
2
14
13
12
CT1
11
10
CT2
9
8
15
1 2
RC137 0_0805_5%
1 2
1
CC47
2
CC26
8200P_0402_25V7K
CC27
1000P_0402_50V7K
10U_0402_6.3V6M
CC48
1 2
1 2
RC136 0_0402_5%
3
1 2
RC133 0_0402_5%
1 2
+1.05VS_VCCIO
1
CC31
@
0.1U_0201_10V K X5R
2
+1.05V_VCCST
0.1U_0201_10V6K
1
2
+1.8VS
0.1U_0201_10V6K
CC28
1
@
2
2
+1.2V
UC1N
AD36
3.3A
CC25
@
+1.05V_VCCST
+VCCPLL_OC
+1.05VS_VCCSTG
0.02A
0.12A
0.19A
1uF X1
0.1uF X1
+1.05V_VCCST
10U_0402_6.3V6M
10U_0402_6.3V6M
1
1
@
CC32
2
CC33
2
Close to BP11 & BP2 Close to BG1 & BG2
1
2
10U_0402_6.3V6M
+1.2V
PSC Side
@
CC34
4.7U_0402_6.3V6M
@
1
CC49
2
10U_0402_6.3V6M
10U_0402_6.3V6M
1
1
CC35
2
CC36
2
Close to BR11 & BT11
10U_0402_6.3V6M
10U_0402_6.3V6M
@
1
1
CC50
2
2
1
CC51
2
10U_0402_6.3V6M
CC52
AH3 2
AH3 6
AM3 6
AN3 2
AW 32
AY3 6
BE3 2
BH3 6
R3 2
BC2 8
BP1 1
BP2
BG1
BG2
BL2 7
BM2 6
BR1 1
BT1 1
Y36
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
RSVD1
VCCST1
VCCST2
VCCSTG1
VCCSTG2
VCCPLL_OC1
VCCPLL_OC2
VCCPLL1
VCCPLL2
WHL-U_BGA1528
+VCCPLL_OC
1U_0201_6.3V6M
@
1
CC53
2
VCCIO_SENSE
VSSIO_SENSE
VSSSA_SENSE
VCCSA_SENSE
14 of 20
1U_0201_6.3V6M
1
2
Close to BM26
1U_0201_6.3V6M
1
2
VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8
VCCIO9
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCSA2
VCCSA1
VCCSA3
VCCSA5
VCCSA6
VCCSA4
VCCSA9
VCCSA7
VCCSA8
VCCSA13
VCCSA14
VCCSA10
VCCSA11
VCCSA12
VCCSA15
VCCSA16
PSC Side
CC37
BSC SidePSC Side
1
CC54
2
AK2 4
AK2 6
AL2 4
AL2 5
AL2 6
AL2 7
AM2 5
AM2 7
BH2 4
BH2 5
BH2 6
BH2 7
BJ2 4
BJ2 6
BP1 6
BP1 8
BG8
BG1 0
BH9
BJ8
BJ9
BJ1 0
BK8
BK2 5
BK2 7
BL8
BL9
BL1 0
BL2 4
BL2 6
BM2 4
BN2 5
BP2 8
BP2 9
BE7
BG7
1U_0201_6.3V6M
@
CC55
1
+1.05VS_VCCIO
3.679A
+VCC_SA
6A
Trace Length Match < 25 mils
VSSSA_SENSE
VCCSA_SENSE
+1.05VS_VCCSTG
1U_0201_6.3V6M
1
2
PSC Side
1U_0201_6.3V6M
1
CC38
2
1U_0201_6.3V6M
1
CC57
CC56
2
Close to CPUUnderneath CPU
Close to CPU Underneath CPU
+1.2V TO +VCCPLL_OC
+VCCPLL_OC+1.2V
A A
Security Classification
Security Classification
Security Classification
2018/09/21 2019/09/21
2018/09/21 2019/09/21
Issued Date
Issued Date
Issued Date
THI S SHEET OF ENGINEERIN G DRAWING IS TH E PROPRI ETARY PR OPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
THI S SHEET OF ENGINEERIN G DRAWING IS TH E PROPRI ETARY PR OPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
THI S SHEET OF ENGINEERIN G DRAWING IS TH E PROPRI ETARY PR OPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET I NFORMATION.T HIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COM PETENT DIVISION OF R&D
AND TRADE SECRET I NFORMATION.T HIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COM PETENT DIVISION OF R&D
AND TRADE SECRET I NFORMATION.T HIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COM PETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEE T NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEE T NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEE T NOR T HE INFORMATION IT CONTAINS
MAYBE USED B Y OR DISCLOSED TO ANY THIRD P A R T Y WITHOUTPRIO R WRITTEN CONSENT OF COM PAL ELECTRONICS, INC.
MAYBE USED B Y OR DISCLOSED TO ANY THIRD P A R T Y WITHOUTPRIO R WRITTEN CONSENT OF COM PAL ELECTRONICS, INC.
MAYBE USED B Y OR DISCLOSED TO ANY THIRD P A R T Y WITHOUTPRIO R WRITTEN CONSENT OF COM PAL ELECTRONICS, INC.
5
4
2018/09/21 2019/09/21
3
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
I(Max) : 120m A(+VCCPLL_OC)
RON(Max) : 6.2 mohm
V drop : 0.019 V
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
2
Date: Sheet
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
WHL-U(8/12)Power
WHL-U(8/12)Power
WHL-U(8/12)Power
LA-H101P
LA-H101P
LA-H101P
13 51Thursday, September 20, 2018
13 51Thursday, September 20, 2018
13 51Thursday, September 20, 2018
1
0.A0.A0.A
o f
o f
o f
+1.05VALW
1
2
@
CC61
1U_0201_6.3V6M
5
+1.05VALW
1
2
CC62
1U_0201_6.3V6M
4
3
2
1
Close to BP20Close to BV18
D D
1
CC63
1U_0201_6.3V6M
2
Close to BV2
+1.05VALW+1.05VALW
1
2
CC64
4.7U_0402_6.3V6M
Close to BV12
1
CC65
10U_0402_6.3V6M
2
+1.8VALW
Imax : 0.702A
+3VALW
Imax : 0.21A
+1.8VALW
1
CC68
1U_0201_6.3V6M
2
Close to CP17
C C
+3VALW
1
@
CC71
1U_0201_6.3V6M
2
1
@
CC72
0.1U_0201_10V KX 5R
2
Close to BT24
1 2
CC73 1U_0201_6.3V6M
Close to CP29
+3VALW
1
@
CC74
0.1U_0201_10V KX 5R
2
+3VALW
+3V_1.8V_HDA
Close to BR24
+3VALW
B B
RF@
LC2
1 2
BLM15BB221SN1D_2P
SM01000BV00
+3V_1.8V_HDA
1
CC76
0.1U_0402_25V6
2
RF@
RF request
A A
Imax: 4.982A
Internal LDO
DCPDSW
+1.05VALW
UC1P
BP20
VCCPRIM_1P05_1
BW16
VCCPRIM_1P05_9
BW18
BW19
VCCPRIM_1P05_11
BY16
VCCPRIM_1P05_12
CA1 4
VCCPRIM_1P05_14
CC1 5
VCCPRIM_1P8_1
CD1 5
VCCPRIM_1P8_4
CD1 6
VCCPRIM_1P8_5
CP1 7
VCCPRIM_1P8_8
CB2 2
VCCPRIM_3P3_4
CB2 3
VCCPRIM_3P3_5
CC2 2
VCCPRIM_3P3_6
CC2 3
VCCPRIM_3P3_7
CD2 2
VCCPRIM_3P3_8
CD2 3
VCCPRIM_3P3_9
CP2 9
VCCPRIM_3P3_10
BU15
VCCPRIM_CORE1
BU22
VCCPRIM_CORE2
BV15
VCCPRIM_CORE3
BV16
VCCPRIM_CORE4
BV18
VCCPRIM_CORE5
BV19
VCCPRIM_CORE6
BV20
VCCPRIM_CORE7
BV22
VCCPRIM_CORE8
BW20
VCCPRIM_CORE9
BW22
VCCPRIM_CORE10
CA1 2
VCCPRIM_CORE11
CA1 6
VCCPRIM_CORE12
CA1 8
VCCPRIM_CORE13
CA1 9
VCCPRIM_CORE14
CA2 0
VCCPRIM_CORE15
CB1 2
VCCPRIM_CORE16
CB1 4
VCCPRIM_CORE17
CB1 5
VCCPRIM_CORE18
BT24
VCCDSW_1P05
BU14
VCCAPLL_1P05_4
BV12
VCCPRIM_MPHY_1P05_1
BW12
VCCPRIM_MPHY_1P05_3
BW14
BY12
BY14
VCCPRIM_MPHY_1P05_6
BV2
VCCAMPHYPLL_1P05
BR15
VCCAPLL_1P05_2
CC1 2
VCCDUSB_1P05
BR24
VCCDSW_3P3_1
BT20
VCCHDA
BV23
VCCSPI
BT18
VCCPRIM_1P05_4
BT19
VCCPRIM_1P05_5
BU18
VCCPRIM_1P05_7
BU19
VCCPRIM_1P05_8
BT22
VCCPRIM_1P05_6
BP22
VCCPRIM_1P05_2
BV14
VCCPRIM_MPHY_1P05_2
WHL-U_BGA1528
K12
K14
K15
K17
K18
K20
L25
M2 4
M2 6
P24
P26
R24
R25
R26
W25
V24
Y25
Y24
VCCPRIM_1P05_10
VCCPRIM_MPHY_1P05_4
VCCPRIM_MPHY_1P05_5
UC1O
VCCOPC1
VCCOPC2
VCCOPC3
VCCOPC4
VCCOPC5
VCCOPC6
VCCOPC7
VCCOPC8
VCCOPC9
VCCOPC10
VCCOPC11
VCCOPC12
VCCOPC13
VCCOPC14
VCC_OPC_1P8_2
VCC_OPC_1P8_1
VCC_OPC_1P8_4
VCC_OPC_1P8_3
WHL-U_BGA1528
VCCPRIM_3P3_3
VCCPRIM_1P05_13
VCCPRIM_1P05_3
VCCAPLL_1P05_3
VCCA_BCLK_1P05
VCCAPLL_1P05_1
VCCA_SRC_1P05
VCCA_XTAL_1P05
VCCDPHY_1P24_2
VCCDPHY_1P24_4
VCCDPHY_1P24_1
VCCDPHY_1P24_3
VCCDPHY_EC_1P24
VCCDSW_3P3_2
VCCA_19P2_1P05
VCCPRIM_1P8_2
VCCPRIM_1P8_3
VCCPRIM_1P8_6
VCCPRIM_1P8_7
VCCPRIM_1P8_9
VCCPRIM_3P3_2
VCCPRIM_3P3_1
GPP_B0/CORE_VID0
GPP_B1/CORE_VID1
16 of 2 0
VCCEOPIO1
VCCEOPIO2
VCCEOPIO3
VCCEOPIO4
VCCEOPIO5
VCCEOPIO6
VCCEOPIO7
VCCEOPIO8
VCCEOPIO_SENSE
VSSEOPIO_SENSE
15 of 2 0
VCCRTC
DCP RTC
AA24
AA26
AB25
AC24
AC25
AC26
AD24
AD26
V25
T25
CB1 6
BR23
BY20
BP24
BR20
BT12
BP14
BR14
BU12
CP5
BY24
CA2 4
BY23
CA2 3
CP2 5
BT23
BR12
CC1 8
CC1 9
CD1 8
CD1 9
CP2 3
BW23
BP23
CB3 6
CB3 5
+1.05VALW
+3VALW
+3VL_RTC
DCPRTC
Intenal LDO
VCCDPHY_EC_1P24
Imax : 0.702A
@
1 2
CC66 1U_0201_6.3V6M
Close to BP24
+VCCDPHY_1.24V
Close to CP25
1 2
CC69 4.7U_0402_6.3V6M
+1.05VALW
+1.8VAL W
+1.8VALW
1
@
CC75
1U_0201_6.3V6M
2
Close to CP23
R T C Bat t e r y
+3VL_RTC +RTCBATT
W=20mils
1 2
RC141 0_0402_5%
1
CC67
1U_0201_6.3V6M
2
Close to BR23
Saf tysuggestio n r emove E E sid e ,KeepPWRsid e
+1.05VALW
1
CC70
1U_0201_6.3V6M
2
Close to CP5
+VCCDPHY_1.24V
VCCDPHY_EC_1P24
When CNVi is no t used in t he design:
VCCDPHY_1P24 pin shall be disconnected from t he VCCLDOSRAM_IN_1P24 pin .
The decoupling capacitor shall remain connected to t he VCCDPHY_1P24 p in.
1 2
R1 0_0201_5%CNVi@
VCCOPC and VCCEOPIO for CFL U43e only
Security Classificat ion
Security Classificat ion
Security Classificat ion
Is s u ed Date
Is s u ed Date
Is s u ed Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I N C . AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I N C . AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I N C . AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETEN T D IVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETEN T D IVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETEN T D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, IN C . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, IN C . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, IN C . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR DISCLOSED TO AN Y THIRD P A R T Y WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C .
MAY BE USED B Y OR DISCLOSED TO AN Y THIRD P A R T Y WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C .
5
4
MAY BE USED B Y OR DISCLOSED TO AN Y THIRD P A R T Y WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C .
3
2018/09/21 2019/09/21
2018/09/21 2019/09/21
2018/09/21 2019/09/21
Compal S ecret Data
Compal S ecret Data
Compal S ecret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Tit le
Tit le
Tit le
WHL-U(9/12)Power
WHL-U(9/12)Power
WHL-U(9/12)Power
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
2
Date: Sheet
LA-H101P
LA-H101P
LA-H101P
14 51Thursday, September 20, 2018
14 51Thursday, September 20, 2018
1
14 51Thursday, September 20, 2018
0.A0.A0.A
of
of
of
5
4
3
2
1
+VCC_CORE +VCC_CORE
UC1L
AN9
VCCCORE5
AN1 0
VCCCORE1
D D
C C
AN2 4
AN2 6
AN2 7
AP2
AP9
AP24
AP26
AR5
AR6
AR7
AR8
AR1 0
AR2 5
AR2 7
AT9
AT2 4
AT2 6
AU5
AU6
AU7
AU8
AU9
AU2 4
AU2 5
AU2 6
AU2 7
AV2
AV5
AV7
AV10
AV27
AW 5
AW 6
AW 7
AW 8
AW 9
AW 10
BB9
BC2 4
AY9
BB24
VCCCORE2
VCCCORE3
VCCCORE4
VCCCORE6
VCCCORE9
VCCCORE7
VCCCORE8
VCCCORE13
VCCCORE14
VCCCORE15
VCCCORE16
VCCCORE10
VCCCORE11
VCCCORE12
VCCCORE19
VCCCORE17
VCCCORE18
VCCCORE24
VCCCORE25
VCCCORE26
VCCCORE27
VCCCORE28
VCCCORE20
VCCCORE21
VCCCORE22
VCCCORE23
VCCCORE30
VCCCORE32
VCCCORE33
VCCCORE29
VCCCORE31
VCCCORE39
VCCCORE40
VCCCORE41
VCCCORE42
VCCCORE43
VCCCORE34
RSVD3
RSVD4
RSVD1
RSVD2
WHL-U_BGA1528
SVID ALERT
B B
VCCCORE35
VCCCORE36
VCCCORE37
VCCCORE38
VCCCORE44
VCCCORE45
VCCCORE48
VCCCORE49
VCCCORE50
VCCCORE46
VCCCORE47
VCCCORE51
VCCCORE52
VCCCORE56
VCCCORE57
VCCCORE58
VCCCORE59
VCCCORE53
VCCCORE54
VCCCORE55
VCCCORE63
VCCCORE64
VCCCORE60
VCCCORE61
VCCCORE62
VCCCORE69
VCCCORE65
VCCCORE66
VCCCORE67
VCCCORE68
VCCCORE70
VCCCORE73
VCCCORE71
VCCCORE72
VCCCORE74
VCC_SENSE
12 of 20
+1.05V_VCCST
12
VSS_SENSE
VIDALERT#
AW 24
AW 25
AW 26
AW 27
AY24
AY26
BA5
BA7
BA8
BA25
BA27
BB2
BB26
BC5
BC6
BC7
BC9
BC1 0
BC2 6
BC2 7
BD5
BD8
BD1 0
BD2 5
BD2 7
BE9
BE24
BE25
BE26
BE27
BF2
BF9
BF2 4
BF2 6
BG2 7
AN6
AN5
AA3
AA1
VIDSCK
AA2
VID SOU T
Y3
RSVD5
BG3
VCCSTG1
Place the PU
resistors close to CPU
RC147
56_0402_5%
SOC_SVID_ALERT#
VR_SVID_CLK
VR_SVID_DATA
VCCCORE_SENSE <47>
VSSCORE_SENSE <47>
VR_SVID_CLK <47>
+1.05VS_VCCSTG
+VCC_CORE
Trace Length Match < 25 mils
+VCC_GT +VCC_GT
UC1M
AA9
AB2
AB8
AB9
AB10
AC8
AD9
AE8
AE9
AE10
AF1 0
AG8
AG9
AH9
AJ1 0
AK2
AK9
AL1 0
AM8
A5
A6
A8
A11
A12
A14
A15
A17
A18
A20
AF2
AF8
AJ8
AL8
AL9
B3
B4
B6
B8
B11
B14
B17
B20
C2
C3
C6
C7
C8
C1 1
C1 2
C1 4
C1 5
C1 7
C1 8
C2 0
D4
D7
D1 1
D1 2
D1 4
Y10
VCCGT8
VCCGT9
VCCGT10
VCCGT1
VCCGT2
VCCGT3
VCCGT4
VCCGT5
VCCGT6
VCCGT7
VCCGT11
VCCGT13
VCCGT14
VCCGT15
VCCGT12
VCCGT16
VCCGT17
VCCGT19
VCCGT20
VCCGT18
VCCGT22
VCCGT23
VCCGT21
VCCGT24
VCCGT25
VCCGT26
VCCGT28
VCCGT27
VCCGT29
VCCGT30
VCCGT32
VCCGT33
VCCGT31
VCCGT34
VCCGT39
VCCGT40
VCCGT41
VCCGT42
VCCGT35
VCCGT36
VCCGT37
VCCGT38
VCCGT49
VCCGT51
VCCGT52
VCCGT53
VCCGT54
VCCGT43
VCCGT44
VCCGT45
VCCGT46
VCCGT47
VCCGT48
VCCGT50
VCCGT62
VCCGT63
VCCGT55
VCCGT56
VCCGT57
VCCGT119
WHL-U_BGA1528
VCCGT_SENSE
VSSGT_SENSE
13 of 20
VCCGT58
VCCGT59
VCCGT60
VCCGT61
VCCGT64
VCCGT69
VCCGT70
VCCGT71
VCCGT72
VCCGT65
VCCGT66
VCCGT67
VCCGT68
VCCGT73
VCCGT74
VCCGT75
VCCGT76
VCCGT77
VCCGT78
VCCGT79
VCCGT87
VCCGT88
VCCGT89
VCCGT90
VCCGT80
VCCGT81
VCCGT82
VCCGT83
VCCGT84
VCCGT85
VCCGT86
VCCGT95
VCCGT96
VCCGT91
VCCGT92
VCCGT93
VCCGT94
VCCGT98
VCCGT97
VCCGT100
VCCGT101
VCCGT99
VCCGT102
VCCGT104
VCCGT105
VCCGT106
VCCGT103
VCCGT107
VCCGT108
VCCGT109
VCCGT111
VCCGT112
VCCGT110
VCCGT114
VCCGT113
VCCGT115
VCCGT116
VCCGT117
VCCGT118
VCCGT120
D1 5
D1 7
D1 8
D2 0
E4
F5
F6
F7
F8
F11
F14
F17
F20
G11
G12
G14
G15
G17
G18
G20
H5
H6
H7
H8
H1 1
H1 2
H1 4
H1 5
H1 7
H1 8
H2 0
J7
J8
J11
J14
J17
J20
K2
K11
L7
L8
L10
M9
N7
N8
N9
N1 0
P2
P8
R9
T8
T9
T10
U8
U1 0
V2
V9
W8
W9
Y8
E3
D2
VCCGT_SENSE <47>
VSSGT_SENSE <47>
Trace Length Match < 25 mils
SOC_SVID_ALERT#
SVID DATA
VR_SVID_DATA
A A
5
1 2
RC148 220_0402_5%
+1.05V_VCCST
Place the PU
resistors close to CPU
12
RC149
100_0402_1%
VR_ALERT# <47>
VR_SVID_DATA <47>
4
(To VR)
(To VR)
Security Classification
Security Classification
Security Classification
2018/09/21 2019/09/21
2018/09/21 2019/09/21
Issued Date
Issued Date
Issued Date
THI S SHEET OF ENGINEERIN G DRAWING IS TH E PROPRI ETARY PR OPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
THI S SHEET OF ENGINEERIN G DRAWING IS TH E PROPRI ETARY PR OPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
THI S SHEET OF ENGINEERIN G DRAWING IS TH E PROPRI ETARY PR OPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET I NFORMATION.T HIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COM PETENT DIVISION OF R&D
AND TRADE SECRET I NFORMATION.T HIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COM PETENT DIVISION OF R&D
AND TRADE SECRET I NFORMATION.T HIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COM PETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEE T NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEE T NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEE T NOR T HE INFORMATION IT CONTAINS
MAYBE USED B Y OR DISCLOSED TO ANY THIRD P A R T Y WITHOUTPRIO R WRITTEN CONSENT OF COM PAL ELECTRONICS, INC.
MAYBE USED B Y OR DISCLOSED TO ANY THIRD P A R T Y WITHOUTPRIO R WRITTEN CONSENT OF COM PAL ELECTRONICS, INC.
MAYBE USED B Y OR DISCLOSED TO ANY THIRD P A R T Y WITHOUTPRIO R WRITTEN CONSENT OF COM PAL ELECTRONICS, INC.
2018/09/21 2019/09/21
3
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
2
Date: Sheet
WHL-U(10/12)Power,SVID
WHL-U(10/12)Power,SVID
WHL-U(10/12)Power,SVID
LA-H101P
LA-H101P
LA-H101P
15 51Thursday, September 20, 2018
15 51Thursday, September 20, 2018
15 51Thursday, September 20, 2018
1
0.A0.A0.A
o f
o f
o f
5
D D
UC1R
CR34
VSS_1
BT5
VSS_2
BY5
VSS_3
CP 35
VSS_4
CM3 7
VSS_5
CK 37
VSS_6
AW 1
VSS_7
CM1
VSS_8
BD6
VSS_9
AY4
VSS_10
B34
VSS_11
E35
VSS_12
A4
VSS_13
AE24
VSS_14
AE26
VSS_15
AF2 5
VSS_16
AG2 4
VSS_17
AG2 6
VSS_18
AH2 4
VSS_19
AH2 5
VSS_20
B2
VSS_21
B36
VSS_22
C3 6
VSS_23
C3 7
C C
B B
CN1
CN2
CN37
CP 2
A32
F33
BJ7
CJ 36
A36
BK10
CJ 4
AB27
BK2
CK 1
AB3
BK28
AB30
BK3
CK 4
AB33
BK33
CK 7
AB36
BK4
CL 2
AB4
BK7
CM1 3
AB7
BL2 5
CM1 7
AC1 0
BL2 8
CM2 1
AC2 7
BL2 9
CM2 5
AC3 0
BL3 0
CM2 9
BL3 1
CM3 1
AD3 3
BL3 2
CM3 3
AD3 5
D1
A3
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
WHL-U_BGA1528
17 of 20
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
BL7
AE25
BM3 3
CM5
AE27
BM3 5
CM9
AE30
BM3 6
CN13
AE7
BM9
CN17
AF2 7
BN3 0
CN21
AF3
BN7
CN25
AF3 0
CN29
AF3 3
BP15
AF3 6
AF4
CN5
AF7
BP25
CN9
AG1 0
BP3
CP 1
BP32
CP 11
AH2 7
BP33
CP 13
AH2 8
BP4
CP 15
AH2 9
BP7
CP 19
AH3 0
CP 21
AH3 1
BR1 9
CP 27
AH3 3
BR2 5
AH3 5
CP 37
AJ2 5
BT1 5
AJ2 8
BT1 6
CP 9
AJ7
CR2
AK3
CR36
AK33
D2 1
AK36
BT2 5
D2 5
AK4
BT2 8
AL2 8
BT3 3
D5
AL2 9
4
UC1S
BT3 5
VSS_145
D6
VSS_146
AL3 2
VSS_147
BT3 6
VSS_148
D8
VSS_149
AL7
VSS_150
D9
VSS_151
AM1 0
VSS_152
BU1 1
VSS_153
E23
VSS_154
AM2 8
VSS_155
E27
VSS_156
AM3 3
VSS_157
BU2 3
VSS_158
E29
VSS_159
AM3 5
VSS_160
BU2 4
VSS_161
E31
VSS_162
BU2 5
VSS_163
E33
VSS_164
AN2 5
VSS_165
BU7
VSS_166
E9
VSS_167
AN2 8
VSS_168
BV1 1
VSS_169
F12
VSS_170
AN2 9
VSS_171
F15
VSS_172
AN3 0
VSS_173
F18
VSS_174
AN3 1
VSS_175
BV3
VSS_176
F2
VSS_177
AN7
VSS_178
BV3 1
VSS_179
F21
VSS_180
AN8
VSS_181
BV3 3
VSS_182
F24
VSS_183
BV4
VSS_184
F3
VSS_185
AP3
VSS_186
BW 11
VSS_187
F4
VSS_188
AP3 3
VSS_189
BW 15
VSS_190
G21
VSS_191
AP3 6
VSS_192
G27
VSS_193
AP4
VSS_194
G33
VSS_195
AR2 8
VSS_196
G35
VSS_197
G36
VSS_198
AT3 3
VSS_199
BW 24
VSS_200
G9
VSS_201
AT3 5
VSS_202
H2 1
VSS_203
AT3 6
VSS_204
BW 7
VSS_205
H2 7
VSS_206
AT4
VSS_207
BY1 1
VSS_208
AU1 0
VSS_209
BY1 5
VSS_210
H9
VSS_211
AU2 8
VSS_212
BY2 2
VSS_213
J12
VSS_214
AU2 9
VSS_215
J15
VSS_216
WHL-U_BGA1528
18 of 20
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273
VSS_274
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
3
BY2 5
J18
AU3 2
BY2 8
J21
AV2 5
BY3 3
J24
AV2 8
BY3 5
J33
AV3
BY3 6
J36
AV3 3
J6
AV3 6
C1
K21
AV4
C2 1
K22
AV6
C2 5
K24
AV8
C2 9
K25
AW 28
C3 3
K27
AW 29
C4
K28
AW 3
C9
K29
AW 30
CA 11
K3
AW 31
CA 15
K30
AY3 3
CA 22
K31
AY3 5
K32
B12
K4
B15
CA 25
K9
B18
CB 11
L27
B21
L33
B23
L35
B25
CB 18
L36
B27
CB 19
L6
B29
CB 2
N2 5
B31
CB 20
N2 7
CB 25
2
UC1T
CB 3
CB 33
CB 4
CB 7
BA10
CC11
BA28
CC20
CC25
BB33
CC28
BB36
CC31
CC7
BC2 5
CD11
CD12
BC2 9
CD14
BC3 2
CD24
CD25
BC8
CE 33
BD2 8
CE 35
BD3 3
CE 36
BD3 5
CE 7
BD3 6
CF 11
BE10
CF 14
BE28
CF 19
BE29
B37
P10
P33
P36
BA3
R2 7
BB3
R2 8
R2 9
R3 0
BB4
R3 1
T27
T30
T33
T35
T36
U2 6
V26
V27
V30
V33
CF 2
V36
BE3
N6
B5
P3
B7
B9
P4
P7
T7
U7
V3
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325
VSS_326
VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350
VSS_351
VSS_352
VSS_353
VSS_354
VSS_355
VSS_356
VSS_357
VSS_358
VSS_359
VSS_360
VSS_361
WHL-U_BGA1528
19 of 20
VSS_362
VSS_363
VSS_364
VSS_365
VSS_366
VSS_367
VSS_368
VSS_369
VSS_370
VSS_371
VSS_372
VSS_373
VSS_374
VSS_375
VSS_376
VSS_377
VSS_378
VSS_379
VSS_380
VSS_381
VSS_382
VSS_383
VSS_384
VSS_385
VSS_386
VSS_387
VSS_388
VSS_389
VSS_390
VSS_391
VSS_392
VSS_393
VSS_394
VSS_395
VSS_396
VSS_397
VSS_398
VSS_399
VSS_400
VSS_401
VSS_402
VSS_403
VSS_404
VSS_405
VSS_406
VSS_407
VSS_408
VSS_409
VSS_410
VSS_411
VSS_412
VSS_413
VSS_414
VSS_415
VSS_416
VSS_417
VSS_418
VSS_419
VSS_420
VSS_421
VSS_422
VSS_423
VSS_424
VSS_425
VSS_426
VSS_427
VSS_428
VSS_429
VSS_430
VSS_431
VSS_432
VSS_433
CF 23
V4
BE30
CF 28
W10
BE31
CF 3
W27
CF 4
W30
BF3
CG 33
W7
BF3 3
CG 7
BF3 6
Y26
BF4
CH31
Y27
BG2 5
Y30
BG2 8
CJ 11
Y33
CJ 14
Y35
BH2 8
CJ 19
Y7
BH2 9
CJ 23
BH3 2
CJ 28
BH3 3
CJ 33
BH3 5
CJ 35
BP19
BR1 6
BY18
BY19
CC16
BU1 6
CC14
BR2 2
BU2 0
CD20
BT1 4
BP12
CB 24
CC24
J5
U2 4
BD7
AR4
AU4
AW 4
BA6
BC4
BE4
BE8
BA4
BD4
BG4
CJ 2
CJ 3
AM5
CM4
AC5
AG5
CR6
1
A A
Security Classification
Security Classification
Security Classification
2018/09/21 2019/09/21
2018/09/21 2019/09/21
Issued Date
Issued Date
Issued Date
THI S SHEET OF ENGINEERIN G DRAWING IS TH E PROPRI ETARY PR OPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
THI S SHEET OF ENGINEERIN G DRAWING IS TH E PROPRI ETARY PR OPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
THI S SHEET OF ENGINEERIN G DRAWING IS TH E PROPRI ETARY PR OPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET I NFORMATION.T HIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COM PETENT DIVISION OF R&D
AND TRADE SECRET I NFORMATION.T HIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COM PETENT DIVISION OF R&D
AND TRADE SECRET I NFORMATION.T HIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COM PETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEE T NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEE T NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEE T NOR T HE INFORMATION IT CONTAINS
MAYBE USED B Y OR DISCLOSED TO ANY THIRD P A R T Y WITHOUTPRIO R WRITTEN CONSENT OF COM PAL ELECTRONICS, INC.
MAYBE USED B Y OR DISCLOSED TO ANY THIRD P A R T Y WITHOUTPRIO R WRITTEN CONSENT OF COM PAL ELECTRONICS, INC.
MAYBE USED B Y OR DISCLOSED TO ANY THIRD P A R T Y WITHOUTPRIO R WRITTEN CONSENT OF COM PAL ELECTRONICS, INC.
5
4
2018/09/21 2019/09/21
3
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
2
Date: Sheet
WHL-U(11/12)GND
WHL-U(11/12)GND
WHL-U(11/12)GND
LA-H101P
LA-H101P
LA-H101P
1
0.A0.A0.A
o f
o f
o f
16 51Thursday, September 20, 2018
16 51Thursday, September 20, 2018
16 51Thursday, September 20, 2018
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