COMPAL LA-H101P Schematic

A

1 1

B

C

D

E

Compal

EL5C3/EL531/EL431

2 2

DIS

In

M/B Schematic Document

tel Whiskey Lake Processor with DDR4

2018-09-20

3 3

LA-H101P

REV: 0.A (EVT)

4 4

Security Classific ation

Is s u ed Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, IN C . AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, IN C . AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETEN T D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETEN T D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETEN T D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, IN C . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, IN C . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, IN C . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED B Y OR DISCLOSED TO AN Y THIRD P A R T Y WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C .

MAY BE USED B Y OR DISCLOSED TO AN Y THIRD P A R T Y WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C .

A

B

MAY BE USED B Y OR DISCLOSED TO AN Y THIRD P A R T Y WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C .

C

2018/09/21 2019/09/21

Compal S ecret Data

Deciphered Date

ompal Electronics, Inc.

C

Tit le

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

C

LA-H101P

Cover Page

E

0.A0.A0.A

of

1 51Thursday, September 20, 2018

of

1 51Thursday, September 20, 2018

of

1 51Thursday, September 20, 2018

A

B

C

D

E

N17S-G0/G2

R4 2400MHz

PCI

TD

P:18W

1 1

FF (Key M)

NG

C

IE/SATA SSD

P 2242/2280 c o n n .

FF (Key E)

NG

WLAN/BT 2230 c o n n .

eD

2 2

FH

P P a n e l

D L C D

HDMI Conn.

H

D Conn.

D

VRAM(GDDR5) X2 2GB

for DIS

HD

MI Re-driver

8407A

PS

e x4 , Gen3 8Gb /s

PC

Ie x4 , Gen38Gb/s

SATA , Gen3 6Gb/s

PCI e x1 , Gen12.5Gb/s

U

B2.0 x1, 480Mb/s

S

eDP x2 , HBR 2.7Gb/s

I x4 , 2.97GT/s

DD

SATA , Gen3 6Gb /s

Whiskey Lake-U

15W

USB2.0 x1, 480Mb/s

3 3

T y p e - C Conn.

US

B3. 1 Gen1

B3. 1,G en1

US

CC

/Vco nn

VBus

MUX/CC

a l t e k RTS5448

R e

w i t c h

5V S

T o

u c h P a d

I2

C_3VL P

B3.1x1,Gen1

US

EC

I2

C

FAB#TA601

1528pin

BGA

DD

USB2 .0 x1, 480Mb/s

USB3.1 x1, Gen1 5Gb/s

S

B3.1 x1, Gen1 5Gb/s

U

US

B2.0 x1, 480Mb/s

US

B2.0 x1, 480Mb/s

US

B2.0 x1, 480Mb/s

US

C

I2

A

HD

Ie x1 , Gen12.5Gb/s

PC

I

SP

-A DDR4-SO-DIMM X1

CH CH-B o n b oa rd RAM x4

B Charge r

US

TI S

N1702001

US

B3 redriver

Pa

rade PS8713B

USB3 redriver

rade PS8713B

Pa

FingerPrint

t. C amera

In

T

h P a n e l

ouc

io Codec

Aud

a l t e k ALC3287

Re

Ca

rd Reader

Re

a l t e k RTS5232S

I R O M

SP

MB

16

US

B2.0 x1, 480Mb/s

U

B3.1 x1, Gen1 5Gb/s

S

USB3.1 x1, Gen1 5Gb/s

HP

SP

K

DMIC

IO

SD

O

ub Boa rd

n S

USB Conn. with A O U

U

B Conn.

S

Combo Jack

Int. Speaker

t. Array Mic *2

In

SD C

ard Conn.

On S

ub Boa rd

LPC

D

4 4

A

Int. KBD

Hall Sensor

B

KB

EN

E KB9022

C

LE

Security Classification

Issued Date

THISSHEET OF ENGINEERING DRAWING IS THEPROPRIETARY PROPERTY OF COMPALELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THISSHEET OF ENGINEERING DRAWING IS THEPROPRIETARY PROPERTY OF COMPALELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND T RADE SECRET INFORMATION. THISSHEET MAYNOT BE TRANSFERED FROM THECUSTODY OFTHECOMPET ENT DIVISIONOF R&D

AND T RADE SECRET INFORMATION. THISSHEET MAYNOT BE TRANSFERED FROM THECUSTODY OFTHECOMPET ENT DIVISIONOF R&D

AND T RADE SECRET INFORMATION. THISSHEET MAYNOT BE TRANSFERED FROM THECUSTODY OFTHECOMPET ENT DIVISIONOF R&D DEPARTMENT EXCEPT AS AUTHORIZEDBY COMPAL ELECTRONICS, I N C. NEITHER THISSHEET NOR THE INFORMATIONIT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZEDBY COMPAL ELECTRONICS, I N C. NEITHER THISSHEET NOR THE INFORMATIONIT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZEDBY COMPAL ELECTRONICS, I N C. NEITHER THISSHEET NOR THE INFORMATIONIT CONTAINS MAYBE USED BY OR DISCLOSED TO ANY THIRD PA R T Y WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, I NC .

MAYBE USED BY OR DISCLOSED TO ANY THIRD PA R T Y WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, I NC .

D

CompalSecret Data

Deciphered Date

Com

Compal Electroni cs, Inc.

pal Electronic s, Inc.

Ti t l e

Size

Custom

Date: Sheet

pal Electronic s, Inc.

Block Diagram

Document N um b e r Rev

LA-H101P

E

2 51Thursday, September 20, 2018

0.A0.A0.A

of

1

V

oltage Rails

5VS

A

d d r e s s

10

01 100x 98h

A

d d r e s s

001 111x 9Eh

1

+

3VS

+VCCPLL_OC

1.05VS_VCCSTG

+

VCC_CORE

+VCC_GT

+VCC_SA

+1.05V_VCCST

+1.05VS_VCCIO

+1.8VS

+0.6VS

X

XX

X

XXX

ower

p plane

+

CT7718W

1.2V

+2.5V

O O

O

X

+5VALW

3VALW

+

B

+

1.8VALW

A A

State

S

0

S3

S5 S4/AC

5 S4/ Battery only

S

S5 S4/AC & Battery don't exist

B B

E

C SM Bus1 address

De vi c e

SmartBat tery

CH SM Bus address

P

De vi c e

DDR_JDIMM1 T o u c h Pad

A

d d r e s s

0001 011x 16h

Address

10 000x A0h

10

+

+1.05VALW

O

X

E

C SM Bus2 address

De vi c e

N

PU SM Bus address

G

De vi c e

Internalth ermal sensor

2

B

OM Structure Table

OM Structure

Item

DIS Only Components DIS@ U

MA Only Components UMA@

HDMI

Logo 45@

Memory Down - DDP Package

C

onnectors ME@

Intel CNVi

ESD Category ESD@ R

F Category RF@

Test Point TP@

Keyboard BackLight

Project select

GPU select

Memory Down select

MIC select

TypeC 20V_PRTCT 20V_PRTCT@

B

TS@Touch Screen SDP@Memory Down - SDP Package DDP@ GC6@GPU GC6 Components NOGC6@Un-Mount GPU GC6 Components

CNVi@ EMI@EMI Category

KBL@ NOKBL@ S540@ S340@ C340@ S340_14@ S340_15@ N17S_G1@ N17S_G0@ N16V@ N16S@ N16@ N17@ MD@ NO_MD@ Arrary_MIC@ Single_MIC@

3

OM Structure

Item

S340_15 MD (Hynix 4GB) S340_15 MD (Micron 4GB) S340_15 MD (Samsung 4GB) C340 MD (Hynix 4GB) C340 MD (Micron 4GB) C340 MD (Samsung 4GB) On Board RAM X76 Resistors X76RAM@ S340_15@ VRAM (Hynix 2GB) S340_15@ VRAM (Micron 2GB) S340_15@ VRAM (Samsung 2GB) C340 VRAM (Hynix 2GB) C340 VRAM (Micron 2GB) C340 VRAM (Samsung 2GB) S340_14 MD (Hynix 4GB) S340_14 MD (Micron 4GB) S340_14 MD (Samsung 4GB) S340_14@ VRAM (Hynix 2GB) S340_14@ VRAM (Micron 2GB) S340_14@ VRAM (Samsung 2GB)

B

H4G_S340_15@ M4G_S340_15@ S4G_S340_15@ H4G_C340@ M4G_C340@ S4G_C340@

VH2G_S340_15@ VM2G_S340_15@ VS2G_S340_15@ VH2G_C340@ VM2G_C340@ VS2G_C340@ H

4G_S340_14@ M4G_S340_14@ S4G_S340_14@ VH2G_S340_14@ VM2G_S340_14@ VS2G_S340_14@

4

SB 2.0 Port Table

U

External

1

SB2/3 Port (IO - 1)

U

2

USB2/3 Port (IO - 2)

3

USB2/3 Port (Type-C)

4

T

ouch Sc reen

5 6

Camer a

7

ingrt P rint

F

8 9 10

NGFF WLAN+BT

SB 3.0 Port Table PCIE Port Table

U

P

ort

1

USB2/3 Port (IO - 1)

2

USB2/3 Port (IO - 2)

3

SB2/3 Port (Type-C)

U

4 5 6

ATA Port Table

S

Port

0 1A

DD

H

1B

SSD1

USB PortPort

ON BOARD RAM * 4 (total 4GB)

340

C

ZZ

H4G_C340@

Z

M4G_C340@

Z

ZZ

S4G_C340@

Z

5

P

ort

Lane

1 2 3

0

4

0

5

1

6 7 8 9

10 11 12 13 14 15 16

2 3 1

CardR eader

0

NG F F W L A N+ B T

0 3 2

SSD

1 0

D

GPU

X

76 SAMSUNG4GB M D

X7680538LA3

ZZZ

S4G_S340_15@ZZZ

X

76 SAMSUNG 4GB MD

X7680438L83

ZZZ

S4G_S340_14@

X76 SAMSUNG 4GB MD

XXXXXXXXX

ZZZ1

S340_14@

X4E S340-14

XXXXXXXXXX

Compal Electronics, Inc.

Ti t l e

otes List

N

Size

Document Number

Custom

Date: Sheet of

LA-H101P

5

3 51Thursday, September 20, 2018

Rev

0.A0.A0.A

S340_15@

X

X7680538LA2

X

76 MICRON 4GB MD

X7680438L82

ZZZ

X76 MICRON 4GB MD

XXXXXXXXX

ZZZ

X4E C340

X4EAF838L01

Deciph ered Date

76 MI C R O N 4G B M D

M4G_S340_15@

M4G_S340_14@

C340@

X

76 HYNIX 4GB M D

MBUS Control Tab le

S

G

T

-

DGPU

SOURCE

EC_SMB_CK1

C C

D D

EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2 EC_SMB_CK4 EC_SMB_DA4 SOC_SMBCLK SOC_SMBDATA SOC_SML0CLK SOC_SML0DATA EC_SMB_CK2 EC_SMB_DA2

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

NECP388

+3VL

N

+3VS

NECP388

+3VS

PCH

+3VALW

PCH

+3VALW

CH

P

+

SIGNAL

1

ECP388

3VS

VX X

+3VALW

X

V

X X X X X X

X

XX

V

X

+3VS

SLP_S1#

LOW

LOW LOW LOW

SLP_S4#SLP_S3# +V+VALWSLP_S5# Clock+VS

HIGHHIGHHIGH

HIGH HIGH HIGH

LOW

HIGH

LOWLOW

C

HARGER

V

+

19V_VIN

X

HIGH

N

EC P3 88 SODIMMBATT

X

V

+3VS+3VS

X

V

+3VS

ONONON

ON

LOWLOW

ON

OFF

T

P

CH

X

ON

OFF

V

+

3VS

X

V

+

3VS

X

ONON

LOW

OFF

2

X

V

+

3VS

XX

X

SENSOR

X

V

+

3VS

X

HM

nsor

se

X

V

+

3VS

X

GPU

UV1

N17S_G0@

UV1

N17S_G2@

X

UC1

SRD1W i3_R1@

I3-8145U

SA0000C6R20

SRFG1 Pentium 5405U@

UC1

I3-8145U

SA0000C6R30

N17S-G0-A1

SA0000CC900

W

HL CPU

3

UC1

I5-8265U

SA0000C6Q20

SREJQi 5_R1@

N17S-G2-A1

SA0000CCB00

UC1

I7-8565U

SA0000C6P20

P

CB

SRFFW i7_R1@

ZZZ

PCB@

PCB

DA8001H6000

Security Classification

Issued Date

THISSHEETOF ENGINEERING DRAWING IS THE PROPRIETARYPROPERTYOFCOMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL

THISSHEETOF ENGINEERING DRAWING IS THE PROPRIETARYPROPERTYOFCOMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THISSHEET MAY NOTBE T RANSFERED FROM THECUSTODY O F THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THISSHEET MAY NOTBE T RANSFERED FROM THECUSTODY O F THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THISSHEET MAY NOTBE T RANSFERED FROM THECUSTODY O F THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THISSHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THISSHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THISSHEET NOR THE INFORMATION IT CONTAINS MAYBE USED BY OR DISCLOSED TO ANY THIRD PA R T Y WITHOUT PRIOR WRITTENCONSENT OF COMPAL ELECTRONICS, INC.

MAYBE USED BY OR DISCLOSED TO ANY THIRD PA R T Y WITHOUT PRIOR WRITTENCONSENT OF COMPAL ELECTRONICS, INC.

X7680538LA1

S340-15

ZZZ

H4G_S340_15@

X

76 HYNI X 4G B M D

X7680438L81

S340-14

ZZZ

H4G_S340_14@

X76 HYNI X 4GB M D

XXXXXXXXX

X

4E

S340-15 C340-14 S340-14

ZZZ

X4E S340-15

X4EAF838L51

Compal Secret Data

2018/09/21 2019/09/21

Compal Secret Data

4

5

D D

C C

4

-

PowerMap_DDR4_Volume_NON CS]

B

+

3

2

1

B B

A A

Security Classification

IssuedDate

Issued Dat e

THISSHEETOF ENGINEE RINGD RAWING IS THE P ROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL

THISSHEETOF ENGINEE RINGD RAWING IS THE P ROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOTB E TRANSFE RED FROM THE CUSTODY OF THE COMPETENT DIVISIONOF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOTB E TRANSFE RED FROM THE CUSTODY OF THE COMPETENT DIVISIONOF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOTB E TRANSFE RED FROM THE CUSTODY OF THE COMPETENT DIVISIONOF R&D DEPARTMENTEXCEPTA S AUTHORIZEDBY COMPAL ELECTRONICS,INC. NE ITHER THIS SHEET NOR THE IN FOR MAT ION ITCONTAINS

DEPARTMENTEXCEPTA S AUTHORIZEDBY COMPAL ELECTRONICS,INC. NE ITHER THIS SHEET NOR THE IN FOR MAT ION ITCONTAINS

DEPARTMENTEXCEPTA S AUTHORIZEDBY COMPAL ELECTRONICS,INC. NE ITHER THIS SHEET NOR THE IN FOR MAT ION ITCONTAINS MAYBE USED BY OR DISCLOSED TO ANY THIRD PAR TY WITHOUT PRIORWRITTENC ONSENT OF COMPALELECTRONICS,INC .

MAYBE USED BY OR DISCLOSED TO ANY THIRD PAR TY WITHOUT PRIORWRITTENC ONSENT OF COMPALELECTRONICS,INC .

5

4

3

MAYBE USED BY OR DISCLOSED TO ANY THIRD PAR TY WITHOUT PRIORWRITTENC ONSENT OF COMPALELECTRONICS,INC .

2

Compal Secret Data

2018/09/21 2019/ 09/21

Deciphered Date

Compal Electronics, Inc.

Title

Pow er M AP

Size Document Number Rev

Date: Sheet of

LA-H101P

4 51Thursday, September 20, 2018

1

4 51Thursday, September 20, 2018

0.A0.A0.A

5

4

3

2

1

3->S0 S0->S3 ->S0

G

3VL_RTC

+

OC_RTCRST#

S

B+

D D

3VLP/+5VLP

+

E

C_ON

+5VALW/+3VALW/+3VALW_DSW

PM_ BAT L OW #

tPCH01_Min : 9 ms

tPCH04_Min : 9 ms

Pull-up to DSW well if not implemented.

DS3 DS3S3/

/

PCH_PWR_EN (S LP_SUS#)

+3V_PRI M

+1.8V_PRIM

EXT_PWR_GAT E#

+1.0V_MPHYPLL

+1.0V_PRIM_CORE

+1.0V_PRIM

tPCH06_Min : 200 us

SUSACK#

PCH_DPWROK

C_RSMRST#

E

C C

C_PRESENT

A

tPCH34_Max : 20 ms

tPCH02_Min : 10 ms

tPCH03_Min : 10 ms

tPLT02_Min : 0 ms Max : 90 ms

ON / O F F

P

BTN_OUT#

P

M_SLP_S5#

Minimum duration of PWRBTN# assertion = 16mS. PWRBTN# can assert before or after RSMRST#

ESPI_RST#

If EXT_PWR_GATE# Toffmin is too small, Pwr gate may choose to completely ignore it

tPCH43_Min : 95 ms

tPCH18_Min : 90 us

PM_ SL P_ S4 #

SYSON

+1.0V_VCCST/+1.0V_V CCSFR

+1.35V_VDDQ/+1.35V_VCCSF R_OC

PM_ SL P_ S3 #

SUSP#

+1.0VS_VCCST G

+1.0VS_VCCI O

B B

+5VS/+3VS/+1.5V S/+1.05 VS

EC_VCCST_PG

VR_ON

SM_PG_CTRL

+0.675VS_VTT

+VCC_SA

+VCC_CORE

tCPU04 Min : 100 ns

tCPU10 Min : 1 ms

T <=10msec

T = 10msec

tCPU19 Max : 100 ns

tCPU18 Max : 35 us

tCPU09 Min : 1 ms

+VCC_GT

VR_PWRGD

PCH_PWROK

tCPU16 Min : 0 ns

H_CPUPWRGD

SYS_PWROK

A A

SUS_STAT#

SOC_PLTRST#

0->S5

S

+3VL_RTC

S

OC_RTCR ST#

B+

+3VLP/+ 5VLP

E

C_ON

+

5VALW/+ 3VALW/+3 VALW_D SW

PM_ BAT L OW #

PCH_PWR_EN (S LP_SUS#)

+3V_PRI M

+

1.8V_ PRIM

EXT_PWR_GAT E#

+1.0V_MPHYPLL

+1.0V_PRIM_CORE

+1.0V_P RIM

SUSACK#

PCH _DP WR OK

C_RSMR ST#

E

C_PRESENT

A

ON / O F F

P

BTN_OUT#

PM_ SL P_ S5 #

ESPI_RST#

PM_ SL P_ S4 #

SYSON

+

1.0V_VCCST/+1.0V_VCCSFR

+1.35V_VDDQ/+1.35V_VCCSF R_OC

PM_ SL P_ S3 #

SUSP#

+1.0VS_VCCST G

+1.0VS_VCCI O

+5VS/+3VS/+1.5 VS/+1. 05VS

EC_VCCST_PG

VR_ON

SM_PG_CTRL

+0.675VS_VTT

+VCC_SA

+VCC_CORE

+VCC_GT

VR_PWRGD

PCH _PW R OK

H_CPUPWRGD

SYS_PWROK

SUS_STAT#

SOC_PLTRST#

Com pal Secret Da ta

Security Classification

Issued Date

THIS SHEET O F ENGINEERING DRAWING IS THEPROPRIETARY PROPERTY OF COMPAL ELECT RONICS, I N C. AN D CONTAINS CONFIDENTIAL

THIS SHEET O F ENGINEERING DRAWING IS THEPROPRIETARY PROPERTY OF COMPAL ELECT RONICS, I N C. AN D CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION.THISSHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THECOMPET ENT D IVISION OF R&D

AND TRADE SECRET INFORMATION.THISSHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THECOMPET ENT D IVISION OF R&D

AND TRADE SECRET INFORMATION.THISSHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THECOMPET ENT D IVISION OF R&D DEPARTMENT EXCEPT AS A U T H O R IZ E D BY COMPAL ELECTRONICS, IN C . NEITHER THIS SHEET NOR THE INFOR MATION IT CONTAINS

DEPARTMENT EXCEPT AS A U T H O R IZ E D BY COMPAL ELECTRONICS, IN C . NEITHER THIS SHEET NOR THE INFOR MATION IT CONTAINS

DEPARTMENT EXCEPT AS A U T H O R IZ E D BY COMPAL ELECTRONICS, IN C . NEITHER THIS SHEET NOR THE INFOR MATION IT CONTAINS MAY BE USED BY OR DISCLOSED TOA N Y THIRD PA R T Y WITHOUT PRIOR WRITTENCONSENT OF COMPAL ELECT RONICS, IN C .

MAY BE USED BY OR DISCLOSED TOA N Y THIRD PA R T Y WITHOUT PRIOR WRITTENCONSENT OF COMPAL ELECT RONICS, IN C .

5

4

3

MAY BE USED BY OR DISCLOSED TOA N Y THIRD PA R T Y WITHOUT PRIOR WRITTENCONSENT OF COMPAL ELECT RONICS, IN C .

2

Com pal Secret Da ta

2018/09/21 2019/09/21

Deciphered Date

Compal Electronics, Inc.

Ti t l e

Size Do cument Numb e r Rev

Date: Sheet of

Power Sequence

LA-H101P

1

5 51Thursday, September 20, 2018

0.A0.A0.A

A

1 1

< Compensation PU For eDP >

+1.05VS_VCCIO

2 2

1 2

RC2 24.9_0201_1%

T r a c e width=20 mils, Spacing=25mil, M ax length=600mils

EDP_COMP

B

<HDMI>

HDMI DDC (Port2 )

<29> <29>

CPU_DP2_CTRL_CLK<29,30> CPU_DP2_CTRL_DATA<29,30>

CPU_DP2_N0<29> CPU_DP2_P0 CPU_DP2_N1 CPU_DP2_P1<29> CPU_DP2_N2 CPU_DP2_P2 CPU_DP2_N3<29> CPU_DP2_P3<29>

TS_I2C_RST#<28>

EDP_COMP

C

UC1A

AL5

DDI1_TXN_0

AL6

DDI1_TXP_0

AJ5

DDI1_TXN_1

AJ6

DDI1_TXP_1

AF6

DDI1_TXN_2

AF5

DDI1_TXP_2

AE5

DDI1_TXN_3

AE6

DDI1_TXP_3

AC4

DDI2_TXN_0

AC3

DDI2_TXP_0

AC1

DDI2_TXN_1

AC2

DDI2_TXP_1

AE4

DDI2_TXN_2

AE3

DDI2_TXP_2

AE1

DDI2_TXN_3

AE2

DDI2_TXP_3

AM6

DIS P_ RCO MP

CC8

GPP_E18/DPPB_CTRLCLK/CNV_BT_HOST_W AKE#

CC9

GPP_E19/DPPB_CTRLDATA

CH4

GPP_E20/DPPC_CTRLCLK

CH3

GPP_E21/DPPC_CTRLDATA

CP4

GPP_E22/DPPD_CTRLCLK

CN4

GPP_E23/DPPD_CTRLDATA

CR2 6

GPP_H16/DDPF_CTRLCLK

CP2 6

GPP_H17/DDPF_CTRLDATA

WHL-U_BGA1528

1 of 2 0

EDP_TXN_0 EDP_TXP_0 EDP_TXN_1 EDP_TXP_1 EDP_TXN_2 EDP_TXP_2 EDP_TXN_3 EDP_TXP_3

EDP_AUX_N EDP_AUX_P

DISP_UTILS

DDI1_AUX_N DDI1_AUX_P DDI2_AUX_N DDI2_AUX_P DDI3_AUX_N DDI3_AUX_P

GPP_E13/DDPB_HPD0/DISP_MISC0 GPP_E14/DDPC_HPD1/DISP_MISC1 GPP_E15/DPPD_HPD2/DISP_MISC2 GPP_E16/DPPE_HPD3/DISP_MI SC3

GPP_E17/EDP_HPD/DISP_MIS C4

EDP_BKLTEN

EDP_VDDEN

EDP_BKLTCTL

AG4 AG3 AG2 AG1 AJ4 AJ3 AJ2 AJ1

AH4 AH3

AM7

AC7 AC6 AD4 AD3 AG7 AG6

CN6 CM6 CP7 CP6 CM7

CK1 1 CG1 1 CH11

EC_SCI#

D

EDP_TXN0 <28> EDP_TXP0 <28> EDP_TXN1 <28> EDP_TXP1 <28>

EDP_AUXN <28> EDP_AUXP <28>

CPU_DP2_HPD < 29,30>

EC_SCI# <34> EDP_HPD <28>

ENBKL <34> PCH_ENVDD <28> IN V P W M <28>

<e DP >

EC_SCI#

From HDMI

From eDP

E

1 2

RC1 10K_0402_5%

+3VS

+1.05 VS_VCCST G

12

RC3 1K_0402_5%

+1.05V_VCCST

3 3

4 4

1 2

RC8 1K_0402_5%

1

2

RC10 49.9_0402_1%@

A

H_THERMTRIP#

CATERR#

H_PROCHOT#<34>

B

1 2

RC4 499_0402_1%

RC11 49.9_0402_1% RC12 49.9_0402_1% RC14 49.9_0402_1%@

RC15 49.9_0402_1%@

If rout ed M S, PECIrequires 18mils spacingto other signals

CB3 4 CC3 5

BP27

BW25

AA4 AR1

BJ1

CE9 CN3

CATERR#

H_PECI<34>

H_PROCHOT#_R H_THERMTRIP#

12 12 12

12

CPU_POPIRCOMP PCH_OPIRCOMP EDRAM_OPIO_RCOMP

EOPIO_RCOMP

UC1D

CAT ER R# PECI

Y4

PROCHOT# THRMTRIP#

U1

BPM#_0

U2

BPM#_1

U3

BPM#_2

U4

BPM#_3

GPP_E3/CPU_GP0 GPP_E7/CPU_GP1 GPP_B3/CPU_GP2 GPP_B4/CPU_GP3

PROC_POPIRCOMP PCH_OPIRCOMP

L5

OPCE_RCOMP

N5

OPC_RCOMP

WHL-U_BGA1528

Security Classificat ion

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I N C . AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I N C . AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETEN T D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETEN T D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETEN T D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, IN C . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, IN C . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, IN C . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED B Y OR DISCLOSED TO AN Y THIRD P A R T Y WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C .

MAY BE USED B Y OR DISCLOSED TO AN Y THIRD P A R T Y WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C .

C

4 of 20

Is s u ed Date

PROC_TCK

PROC_TDI PROC_TDO PROC_TMS

PROC_TRST#

PCH_TCK

PCH_TDI PCH_TDO PCH_TMS

PCH_TRST# PCH_JTAGX

PROC_PREQ# PROC_PRDY#

CPU_XDP_TCK0

T6

SOC_XDP_TDI

U6

SOC_XDP_TDO

Y5

SOC_XDP_TMS

T5

SOC_XDP_TRST#

AB6

PCH_JTAG_TCK1

W6

SOC_XDP_TDI

U5

SOC_XDP_TDO

W5

SOC_XDP_TMS

P5

SOC_XDP_TRST#

Y6

CPU_XDP_TCK0

P6

W2 W1

2018/09/21 2019/09/21

T1TP@ T2TP@

Compal S ecret Data

Deciphered Date

D

< PU/PD for CMC Debug >

SOC_XDP_TMS

SOC_XDP_TDI

SOC_XDP_TDO

CPU_XDP_TCK0

PCH_JTAG_TCK1

SOC_XDP_TRST#

RC5 51_0402_5%CMC@

RC6 51_0402_5%CMC@

RC7 51_0402_5%DCI@

RC9 51_0402_5%DCI@

RC13 51_0402_5%@

RC16 51_0402_5%@

Tit le

Size Document Number Rev

Custom

Date: Sheet

+1.05VS_VCCSTG

1 2

Compal Electronics, Inc.

WHL-U(1/12)DDI,EDP,MISC,CMC

LA-H101P

E

6 51Thursday, September 20, 2018

0.A0.A0.A

of

5

Interleaved Memory

4

3

2

1

D D

C C

B B

<18>

DDR_A_D[0..15]

DDR_A_D[16..31]<18>

DDR_A_D[32..47]<18>

DDR_A_D[48..63]<18>

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

UC1B

A26

DDR0_DQ_0/DDR0_DQ_0

D26

DDR0_DQ_1/DDR0_DQ_1

D28

DDR0_DQ_2/DDR0_DQ_2

C28

DDR0_DQ_3/DDR0_DQ_3

B26

DDR0_DQ_4/DDR0_DQ_4

C26

DDR0_DQ_5/DDR0_DQ_5

B28

DDR0_DQ_6/DDR0_DQ_6

A28

DDR0_DQ_7/DDR0_DQ_7

B30

DDR0_DQ_8/DDR0_DQ_8

D30

DDR0_DQ_9/DDR0_DQ_9

B33

DDR0_DQ_10/DDR0_DQ_10

D32

DDR0_DQ_11/DDR0_DQ_11

A30

DDR0_DQ_12/DDR0_DQ_12

C30

DDR0_DQ_13/DDR0_DQ_13

B32

DDR0_DQ_14/DDR0_DQ_14

C32

H37

DDR0_DQ_16/DDR0_DQ_32

H34

DDR0_DQ_17/DDR0_DQ_33

K34

DDR0_DQ_18/DDR0_DQ_34

K35

DDR0_DQ_19/DDR0_DQ_35

H36

DDR0_DQ_20/DDR0_DQ_36

H35

DDR0_DQ_21/DDR0_DQ_37

K36

DDR0_DQ_22/DDR0_DQ_38

K37

DDR0_DQ_23/DDR0_DQ_39

N36

DDR0_DQ_24/DDR0_DQ_40

N34

DDR0_DQ_25/DDR0_DQ_41

R37

DDR0_DQ_26/DDR0_DQ_42

R34

DDR0_DQ_27/DDR0_DQ_43

N37

DDR0_DQ_28/DDR0_DQ_44

N35

DDR0_DQ_29/DDR0_DQ_45

R36

DDR0_DQ_30/DDR0_DQ_46

R35

DDR0_DQ_31/DDR0_DQ_47

AN35

DDR0_DQ_32/DDR1_DQ_0

AN34

DDR0_DQ_33/DDR1_DQ_1

AR35

DDR0_DQ_34/DDR1_DQ_2

AR34

DDR0_DQ_35/DDR1_DQ_3

AN37

DDR0_DQ_36/DDR1_DQ_4

AN36

DDR0_DQ_37/DDR1_DQ_5

AR36

DDR0_DQ_38/DDR1_DQ_6

AR37

DDR0_DQ_39/DDR1_DQ_7

AU35

DDR0_DQ_40/DDR1_DQ_8

AU34

DDR0_DQ_41/DDR1_DQ_9

AW35

DDR0_DQ_42/DDR1_DQ_10

AW34

DDR0_DQ_43/DDR1_DQ_11

AU37

DDR0_DQ_44/DDR1_DQ_12

AU36

DDR0_DQ_45/DDR1_DQ_13

AW36

DDR0_DQ_46/DDR1_DQ_14

AW37

DDR0_DQ_47/DDR1_DQ_15

BA35

DDR0_DQ_48/DDR1_DQ_32

BA34

DDR0_DQ_49/DDR1_DQ_33

BC35

DDR0_DQ_50/DDR1_DQ_34

BC34

DDR0_DQ_51/DDR1_DQ_35

BA37

DDR0_DQ_52/DDR1_DQ_36

BA36

DDR0_DQ_53/DDR1_DQ_37

BC36

DDR0_DQ_54/DDR1_DQ_38

BC37

DDR0_DQ_55/DDR1_DQ_39

BE35

DDR0_DQ_56/DDR1_DQ_40

BE34

DDR0_DQ_57/DDR1_DQ_41

BG35

DDR0_DQ_58/DDR1_DQ_42

BG34

DDR0_DQ_59/DDR1_DQ_43

BE37

DDR0_DQ_60/DDR1_DQ_44

BE36

DDR0_DQ_61/DDR1_DQ_45

BG36

DDR0_DQ_62/DDR1_DQ_46

BG37

DDR0_DQ_63/DDR1_DQ_47

WHL-U_BGA1528

DDR0_CKN_0/DDR0_CKN_0 DDR0_CKP_0/DDR0_CKP_0 DDR0_CKN_1/DDR0_CKN_1 DDR0_CKP_1/DDR0_CKP_1

DDR0_CKE_0/DDR0_CKE_0 DDR0_CKE_1/DDR0_CKE_1

DDR0_CS#_0/DDR0_CS#_0 DDR0_CS#_1/DDR0_CS#_1

DDR0_DQ_15/DDR0_DQ_15

DDR0_ODT_0/DDR0_ODT_0

DDR0_CAB_7/DDR0_MA_10 DDR0_CAA_7/DDR0_MA_11 DDR0_CAA_6/DDR0_MA_12 DDR0_CAB_0/DDR0_MA_13

DDR0_CAB_2/DDR0_MA_14 DDR0_CAB_1/DDR0_MA_15 DDR0_CAB_3/DDR0_MA_16

DDR0_DQSN_0/DDR0_DQSN_0 DDR0_DQSP_0/DDR0_DQSP_0 DDR0_DQSN_1/DDR0_DQSN_1 DDR0_DQSP_1/DDR0_DQSP_1 DDR0_DQSN_2/DDR0_DQSN_4 DDR0_DQSP_2/DDR0_DQSP_4 DDR0_DQSN_3/DDR0_DQSN_5 DDR0_DQSP_3/DDR0_DQSP_5 DDR0_DQSN_4/DDR1_DQSN_0 DDR0_DQSP_4/DDR1_DQSP_0 DDR0_DQSN_5/DDR1_DQSN_1 DDR0_DQSP_5/DDR1_DQSP_1 DDR0_DQSN_6/DDR1_DQSN_4 DDR0_DQSP_6/DDR1_DQSP_4 DDR0_DQSN_7/DDR1_DQSN_5 DDR0_DQSP_7/DDR1_DQSP_5

2 of 20

DDR0_CKE_2/NC DDR0_CKE_3/NC

NC/DDR0_ODT_1

DDR0_CAB_9/DDR0_MA_0 DDR0_CAB_8/DDR0_MA_1 DDR0_CAB_5/DDR0_MA_2

NC/DDR0_MA_3

NC/DDR0_MA_4 DDR0_CAA_0/DDR0_MA_5 DDR0_CAA_2/DDR0_MA_6 DDR0_CAA_4/DDR0_MA_7 DDR0_CAA_3/DDR0_MA_8 DDR0_CAA_1/DDR0_MA_9

DDR0_CAB_4/DDR0_BA_0 DDR0_CAB_6/DDR0_BA_1 DDR0_CAA_5/DDR0_BG_0

DDR0_CAA_8/DDR0_ACT# DDR0_CAA_9/DDR0_BG_1

NC/DDR0_ALERT#

NC/DDR0_PAR

DDR_VREF_CA DDR0_VREF_DQ_0 DDR0_VREF_DQ_1

DDR1_VREF_DQ

DDR_VTT_CNTL

V32 V31 T32 T31

U36 U37 U34 U35

AE32 AF32 AE31 AF31

AC37 AC36 AC34 AC35 AA35 AB35 AA37 AA36 AB34 W36 Y31 W34 AA34 AC32

AC31 AB32 Y32

W32 AB31 V34

V35 W35

C27 D27 D31 C31 J35 J34 P34 P35 AP35 AP34 AV34 AV35 BB35 BB34 BF34 BF35

W37 W31 F36 D35 D37 E36 C35

DDR_A_CLK#0 DDR_A_CLK0 DDR_A_CLK#1 DDR_A_CLK1

DDR_A_CKE0

DDR_A_CS#0 DDR_A_CS#1 DDR_A_ODT0 DDR_A_ODT1

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13

DDR_A_MA14 DDR_A_MA15 DDR_A_MA16

DDR_A_BA0 DDR_A_BA1 DDR_A_BG0

DDR_A_ACT# DDR_A_BG1

DDR_A_DQS#0 DDR_A_DQS0 DDR_A_DQS#1 DDR_A_DQS1 DDR_A_DQS#2 DDR_A_DQS2 DDR_A_DQS#3 DDR_A_DQS3 DDR_A_DQS#4 DDR_A_DQS4 DDR_A_DQS#5 DDR_A_DQS5 DDR_A_DQS#6 DDR_A_DQS6 DDR_A_DQS#7 DDR_A_DQS7

DDR_A_ALERT# DDR_A_PARITY +0.6V_A_VREFCA

+0.6V_ B_VREFDQ DDR_PG_CTRL

DDR_A_CLK#0 <18> DDR_A_CLK0 <18>

TP@

T3 T4TP@

DDR_A_CKE0 <18,19>

DDR_A_CS#0 <18,19>

T5TP@

DDR_A_ODT0 <18,19>

T7TP@

DDR_A_MA0 <18,19> DDR_A_MA1 <18,19> DDR_A_MA2 <18,19> DDR_A_MA3 <18,19> DDR_A_MA4 <18,19> DDR_A_MA5 <18,19> DDR_A_MA6 <18,19> DDR_A_MA7 <18,19> DDR_A_MA8 <18,19> DDR_A_MA9 <18,19> DDR_A_MA10 <18,19> DDR_A_MA11 <18,19> DDR_A_MA12 <18,19> DDR_A_MA13 <18,19>

DDR_A_MA14 <18,19> DDR_A_MA15 <18,19> DDR_A_MA16 <18,19>

DDR_A_BA0 <18,19> DDR_A_BA1 <18,19> DDR_A_BG0 <18,19>

DDR_A_ACT# <18,19> DDR_A_BG1 <18>

DDR_A_DQS#0 <18> DDR_A_DQS0 <18> DDR_A_DQS#1 <18> DDR_A_DQS1 <18> DDR_A_DQS#2 <18> DDR_A_DQS2 <18> DDR_A_DQS#3 <18> DDR_A_DQS3 <18> DDR_A_DQS#4 <18> DDR_A_DQS4 <18> DDR_A_DQS#5 <18> DDR_A_DQS5 <18> DDR_A_DQS#6 <18> DDR_A_DQS6 <18> DDR_A_DQS#7 <18> DDR_A_DQS7 <18>

DDR_A_ALERT# <18> DDR_A_PARITY <18,19> +0.6V_A_VREFCA <18>

+0.6V_B_VREFDQ <20>

DDR_B_D[0..15]

<20>

DDR_B_D[16..31]<20>

DDR_B_D[32..47]<20>

DDR_B_D[48..63]<20>

Trace width/Spacing >= 20mils

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

UC1C

J22

DDR1_DQ_0/DDR0_DQ_16

H25

DDR1_DQ_1/DDR0_DQ_17

G22

DDR1_DQ_2/DDR0_DQ_18

H22

DDR1_DQ_3/DDR0_DQ_19

F25

DDR1_DQ_4/DDR0_DQ_20

J25

DDR1_DQ_5/DDR0_DQ_21

G25

DDR1_DQ_6/DDR0_DQ_22

F22

DDR1_DQ_7/DDR0_DQ_23

D22

DDR1_DQ_8/DDR0_DQ_24

C22

DDR1_DQ_9/DDR0_DQ_25

C24

DDR1_DQ_10/DDR0_DQ_26

D24

DDR1_DQ_11/DDR0_DQ_27

A22

DDR1_DQ_12/DDR0_DQ_28

B22

DDR1_DQ_13/DDR0_DQ_29

A24

DDR1_DQ_14/DDR0_DQ_30

B24

DDR1_DQ_15/DDR0_DQ_31

G31

DDR1_DQ_16/DDR0_DQ_48

G32

DDR1_DQ_17/DDR0_DQ_49

H29

DDR1_DQ_18/DDR0_DQ_50

H28

DDR1_DQ_19/DDR0_DQ_51

G28

DDR1_DQ_20/DDR0_DQ_52

G29

DDR1_DQ_21/DDR0_DQ_53

H31

DDR1_DQ_22/DDR0_DQ_54

H32

DDR1_DQ_23/DDR0_DQ_55

L31

DDR1_DQ_24/DDR0_DQ_56

L32

DDR1_DQ_25/DDR0_DQ_57

N29

DDR1_DQ_26/DDR0_DQ_58

N28

DDR1_DQ_27/DDR0_DQ_59

L28

DDR1_DQ_28/DDR0_DQ_60

L29

DDR1_DQ_29/DDR0_DQ_61

N31

DDR1_DQ_30/DDR0_DQ_62

N32

DDR1_DQ_31/DDR0_DQ_63

AJ29

DDR1_DQ_32/DDR1_DQ_16

AJ30

DDR1_DQ_33/DDR1_DQ_17

AM32

DDR1_DQ_34/DDR1_DQ_18

AM31

DDR1_DQ_35/DDR1_DQ_19

AM30

DDR1_DQ_36/DDR1_DQ_20

AM29

DDR1_DQ_37/DDR1_DQ_21

AJ31

DDR1_DQ_38/DDR1_DQ_22

AJ32

DDR1_DQ_39/DDR1_DQ_23

AR31

DDR1_DQ_40/DDR1_DQ_24

AR32

DDR1_DQ_41/DDR1_DQ_25

AV30

DDR1_DQ_42/DDR1_DQ_26

AV29

DDR1_DQ_43/DDR1_DQ_27

AR30

DDR1_DQ_44/DDR1_DQ_28

AR29

DDR1_DQ_45/DDR1_DQ_29

AV32

DDR1_DQ_46/DDR1_DQ_30

AV31

DDR1_DQ_47/DDR1_DQ_31

BA32

DDR1_DQ_48/DDR1_DQ_48

BA31

DDR1_DQ_49/DDR1_DQ_49

BD31

DDR1_DQ_50/DDR1_DQ_50

BD32

DDR1_DQ_51/DDR1_DQ_51

BA30

DDR1_DQ_52/DDR1_DQ_52

BA29

DDR1_DQ_53/DDR1_DQ_53

BD29

DDR1_DQ_54/DDR1_DQ_54

BD30

DDR1_DQ_55/DDR1_DQ_55

BG31

DDR1_DQ_56/DDR1_DQ_56

BG32

DDR1_DQ_57/DDR1_DQ_57

BK32

DDR1_DQ_58/DDR1_DQ_58

BK31

DDR1_DQ_59/DDR1_DQ_59

BG29

DDR1_DQ_60/DDR1_DQ_60

BG30

DDR1_DQ_61/DDR1_DQ_61

BK30

DDR1_DQ_62/DDR1_DQ_62

BK29

DDR1_DQ_63/DDR1_DQ_63

WHL-U_BGA1528

DDR1_CKN_0/DDR1_CKN_0 DDR1_CKP_0/DDR1_CKP _0 DDR1_CKN_1/DDR1_CKN_1 DDR1_CKP_1/DDR1_CKP _1

DDR1_CKE_0/DDR1_CKE _0 DDR1_CKE_1/DDR1_CKE _1

DDR1_CKE_2/NC DDR1_CKE_3/NC

DDR1_CS#_0/DDR1_CS#_0 DDR1_CS#_1/DDR1_CS#_1

DDR1_ODT_0/DDR1_ODT_0

NC/DDR1_ODT_1 DDR1_CAB_9/DDR1_MA_0 DDR1_CAB_8/DDR1_MA_1 DDR1_CAB_5/DDR1_MA_2

NC/DDR1_MA_3

NC/DDR1_MA_4 DDR1_CAA_0/DDR1_MA_5 DDR1_CAA_2/DDR1_MA_6 DDR1_CAA_4/DDR1_MA_7 DDR1_CAA_3/DDR1_MA_8 DDR1_CAA_1/DDR1_MA_9

DDR1_CAB_7/DDR1_MA_10 DDR1_CAA_7/DDR1_MA_11 DDR1_CAA_6/DDR1_MA_12 DDR1_CAB_0/DDR1_MA_13

DDR1_CAB_2/DDR1_MA_14 DDR1_CAB_1/DDR1_MA_15 DDR1_CAB_3/DDR1_MA_16

DDR1_CAB_4/DDR1_BA_0 DDR1_CAB_6/DDR1_BA_1

DDR1_CAA_5/DDR1_BG_0

DDR1_CAA_9/DDR1_BG_1 DDR1_CAA_8/DDR1_ACT#

DDR1_DQSN_0/DDR0_DQSN_2 DDR1_DQSP_0/DDR0_DQSP _2 DDR1_DQSN_1/DDR0_DQSN_3 DDR1_DQSP_1/DDR0_DQSP _3 DDR1_DQSN_2/DDR0_DQSN_6 DDR1_DQSP_2/DDR0_DQSP _6 DDR1_DQSN_3/DDR0_DQSN_7 DDR1_DQSP_3/DDR0_DQSP _7 DDR1_DQSN_4/DDR1_DQSN_2 DDR1_DQSP_4/DDR1_DQSP _2 DDR1_DQSN_5/DDR1_DQSN_3 DDR1_DQSP_5/DDR1_DQSP _3 DDR1_DQSN_6/DDR1_DQSN_6 DDR1_DQSP_6/DDR1_DQSP _6 DDR1_DQSN_7/DDR1_DQSN_7 DDR1_DQSP_7/DDR1_DQSP _7

NC/DDR1_ALERT#

NC/DDR1_PAR

DRAM_RESET#

DDR_COMP_0 DDR_COMP_1 DDR_COMP_2

3 of 20

AF28 AF29 AE28 AE29

T28 T29 V28 V29

AL37 AL35 AL36 AL34 AG36 AG35 AF34 AG37 AE35 AF35 AE37 AC29 AE36 AB29 AG34 AC28 AB28 AK35

AJ35 AK34 AJ34

AJ37 AJ36 W29

Y28 W28

H24 G24 C23 D23 G30 H30 L30 N30 AL31 AL30 AU31 AU30 BC31 BC30 BH31 BH30

Y29 AE34 BU31

BN28 BN27 BN29

DDR_B_CLK#0 DDR_B_CLK0 DDR_B_CLK#1 DDR_B_CLK1

DDR_B_CKE0 DDR_B_CKE1

DDR_B_CS#0 DDR_B_CS#1 DDR_B_ODT0 DDR_B_ODT1 DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13

DDR_B_MA14 DDR_B_MA15 DDR_B_MA16

DDR_B_BA0 DDR_B_BA1 DDR_B_BG0

DDR_B_BG1

DDR_B_ACT#

DDR_B_DQS#0 DDR_B_DQS0 DDR_B_DQS#1 DDR_B_DQS1 DDR_B_DQS#2 DDR_B_DQS2 DDR_B_DQS#3 DDR_B_DQS3 DDR_B_DQS#4 DDR_B_DQS4 DDR_B_DQS#5 DDR_B_DQS5 DDR_B_DQS#6 DDR_B_DQS6 DDR_B_DQS#7 DDR_B_DQS7

DDR_B_ALERT# DDR_B_PARITY DDR_DRAMRST#

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

#543016 PDG1.5 P.168 W=12-15 Space= 20/25 L=500mil

DDR_B_CLK#0 <20> DDR_B_CLK0 <20> DDR_B_CLK#1 <20> DDR_B_CLK1 <20>

DDR_B_CKE0 <20> DDR_B_CKE1 <20>

DDR_B_CS#0 <20> DDR_B_CS#1 <20> DDR_B_ODT0 <20> DDR_B_ODT1 <20> DDR_B_MA0 <20> DDR_B_MA1 <20> DDR_B_MA2 <20> DDR_B_MA3 <20> DDR_B_MA4 <20> DDR_B_MA5 <20> DDR_B_MA6 <20> DDR_B_MA7 <20> DDR_B_MA8 <20> DDR_B_MA9 <20> DDR_B_MA10 <20> DDR_B_MA11 <20> DDR_B_MA12 <20> DDR_B_MA13 <20>

DDR_B_MA14 <20> DDR_B_MA15 <20> DDR_B_MA16 <20>

DDR_B_BA0 <20> DDR_B_BA1 <20> DDR_B_BG0 <20>

DDR_B_BG1 <20> DDR_B_ACT# <20>

DDR_B_DQS#0 <20> DDR_B_DQS0 <20> DDR_B_DQS#1 <20> DDR_B_DQS1 <20> DDR_B_DQS#2 <20> DDR_B_DQS2 <20> DDR_B_DQS#3 <20> DDR_B_DQS3 <20> DDR_B_DQS#4 <20> DDR_B_DQS4 <20> DDR_B_DQS#5 <20> DDR_B_DQS5 <20> DDR_B_DQS#6 <20> DDR_B_DQS6 <20> DDR_B_DQS#7 <20> DDR_B_DQS7 <20>

DDR_B_ALERT# <20> DDR_B_PARITY <20> DDR_DRAMRST# <18,20>

1 2

RC17 121_0402_1%

1 2

RC18 80.6_0402_1%

1 2

RC19 100_0402_1%

< F o r ODT & VTT P o we r Control >

DDR_VTT_CNTL to DDR VTT supplied ramped <35uS (tCPU18)

UC11

DDR_PG_CTRL

A A

5

NC1VCC

2

A

3

GND

74AUP1G07GW_TSSOP5

SA00005U600

Y

1

CC1

0.1U_0201_10V6K

@

2

5

4

+3VS+1.2V +1.2V

12

RC21 100K_0402_5%

DDR_DRAMRST#

DDR_VTT_PG_CTRL

Security Classificat ion

Is s u ed Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I N C . AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I N C . AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETEN T D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETEN T D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETEN T D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, IN C . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, IN C . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, IN C . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED B Y OR DISCLOSED TO AN Y THIRD P A R T Y WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C .

MAY BE USED B Y OR DISCLOSED TO AN Y THIRD P A R T Y WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C .

4

MAY BE USED B Y OR DISCLOSED TO AN Y THIRD P A R T Y WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C .

3

2018/09/21 2019/09/21

Compal S ecret Data

Deciphered Date

2

12

RC20 470_0402_5%

1

CC2 100P_0402_50V8J

ESD@

2

Clo se to CPU

Compal Electronics, Inc.

Tit le

Size Document Number Rev

Custom

Date: Sheet

WHL-U(2/12)DDR4

LA-H101P

Thursday, September 20, 2018

LA-H101P

51

7

of

1

of

0.A0.A0.A

5

4

3

2

1

+3VALW

1 2

RC23 100K_0201_5%

1 2

RC24 100K_0201_5%

1 2

RC25 100K_0201_5%

SOC_SPI_0_SI SOC_SPI_0_IO2 SOC_SPI_0_IO3

SML0ALERT# (Internal Pull Down):

eSPI or LPC

0 = LPC is selected for EC ==> Default

1 = eSPI is selected for EC

D D

SOC_SPI_0_CLK SOC_SPI_0_SO

SPI R O M

+3VS

1 2

RC26 10K_0402_5%

C C

+3VS

1 2

RC28 8.2K_0402_5%

KB_RST#

SERIRQ<34>

SERIRQ

SOC_SPI_0_SI SOC_SPI_0_IO2 SOC_SPI_0_IO3 SOC_SPI_0_CS#0

SERIRQ

close to SPI ROM

SOC_SPI_0_SO SOC_SPI_0_CLK SOC_SPI_0_CLK_R SOC_SPI_0_SI SOC_SPI_0_IO3

FromSOC

SOC_SPI_0_IO2

B B

FromE C

EC_SPI_CLK<34> EC_SPI_MOSI<34> EC_SPI_CS0#<34>

EC_SPI_MISO<34>

1 2

RC29 33_0402_5%

1 2

RC31 33_0402_5%EMI@

1 2

RC32 33_0402_5%

1 2

RC34 33_0402_5%

1 2

RC36 33_0402_5%

EC_SPI_CLK EC_SPI_MOSI SOC_SPI_0_SI_R EC_SPI_CS0# EC_SPI_MISO

RC41 33_0402_5%EMI@ RC42 33_0402_5% RC43 33_0402_5% RC44 33_0402_5%

1 2 1 2 1 2 1 2

SOC_SPI_0_SO_R

SOC_SPI_0_SI_R SOC_SPI_0_IO3_R

SOC_SPI_0_IO2_R

SOC_SPI_0_CLK_R

SOC_SPI_0_CS#0 SOC_SPI_0_SO_R

UC1E

CH37

SPI0_CLK

CF 37

SPI0_MISO

CF 36

SPI0_MOSI

CF 34

SPI 0_I O2

CG 34

SPI 0_I O3

CG 36

SPI0_CS0#

CG 35

SPI0_CS1#

CH34

SPI0_CS2#

CF 20

GPP_D1/SPI1_CLK/BK1/ SBK1

CG 22

GPP_D2/SPI1_MISO_I O1/BK2/SBK2

CF 22

GPP_D3/SPI1_MOSI_I O0/BK3/SBK3

CG 23

GPP_D21/SPI1_IO2

CH23

GPP_D22/SPI1_IO3

CG 20

GPP_D0/SPI1_CS0#/BK0/ SBK0

CH7

CL_CLK

CH8

CL_ DA TA

CH9

CL_ RS T#

BV29

GPP_A0/RCIN#/TIME_SYNC1

BV28

GPP_A6/SERIRQ

WHL-U_BGA1528

GPP_C5/SML0ALERT#

GPP_B23/SML1ALERT#/PCHHOT#

GPP_A1/LAD0/ESPI_I O0 GPP_A2/LAD1/ESPI_I O1 GPP_A3/LAD2/ESPI_I O2 GPP_A4/LAD3/ESPI_I O3

GPP_A5/LFRAME#/ESPI_CS#

GPP_A14/SUS_STAT#/ESPI_RESET #

GPP_A9/CLKOUT_LPC0/ESPI _CLK

GPP_A10/CLKOUT_LPC1

5 of 20

GPP_C0/SMBCLK

GPP_C1/SMBDATA

GPP_C2/SMBALERT#

GPP_C3/SML0CLK

GPP_C4/SML0DATA

GPP_C6/SML1CLK

GPP_C7/SML1DATA

GPP_A8/CLKRUN#

CK 14 CH15 CJ 15

CH14 CF 15 CG 15

CN15 CM1 5 CC34

CA 29 BY2 9 BY2 7 BV2 7 CA 28 CA 27

BV32 BV3 0 BY30

SOC_SMBCLK SOC_SMBDATA SOC_SMBALERT#

SOC_SML0CLK SOC_SML0DATA SOC_SML0ALERT#

SOC_SML1ALERT#

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 LPC_FRAME#

LPC_CLK0

PM_CLKRUN#KB_RST#

1 2

RC27 22_0402_5%EMI@

SOC_SMBCLK <20> SOC_SMBDATA <20>

T8TP@

T9TP@

EC_SMB_CK2 <34> EC_SMB_DA2 <34>

LPC_AD0 < 34> LPC_AD1 < 34> LPC_AD2 <34> LPC_AD3 <34>

LPC_FRAME# <34>

EC_SMB_CK2 EC_SMB_DA2

SOC_SML1ALERT#

SOC_SMBCLK SOC_SMBDATA SOC_SML0CLK SOC_SML0DATA

PM_CLKRUN#

SMB

(Link to DDR)

SML1

(Link to EC, Thermal Sensor)

CLK_LPC_EC <34>

PM_CLKRUN# <34>

1 2

RC30 1K_0402_5%

1 2

RC33 1K_0402_5%

1 2

RC35 150K_0402_5%@

1 2

RC37 1K_0402_5%

1 2

RC38 1K_0402_5%

1 2

RC39 1K_0402_5%

1 2

RC40 1K_0402_5%

1 2

RC45 8.2K_0402_5%

+3VS

< SPI RO M - 16M >

SOC_SPI_0_CS#0

SOC_SPI_0_IO2_R

A A

5

UC12

1

CS#

2

DO(IO1)

3

IO2

4

DI (I O0 )

GND

XM25QH128AHIG SOP 8P

VCC

CL K

IO

+3VALW

@

1 2

CC3 0.1U_0201_10V K X5R

8

SOC_SPI_0_IO3_RSOC_SPI_0_SO_R

7

SOC_SPI_0_CLK_R

6

SOC_SPI_0_SI_R

5

1

CC4

@EMI@

10P_0402_50V8J

2

4

Security Classification

2018/09/21 2019/09/21

Issued Date

THI S SHEET OF ENGINEERIN G DRAWING IS TH E PROPRI ETARY PR OPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

THI S SHEET OF ENGINEERIN G DRAWING IS TH E PROPRI ETARY PR OPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET I NFORMATION.T HIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COM PETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION.T HIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COM PETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION.T HIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COM PETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEE T NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEE T NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEE T NOR T HE INFORMATION IT CONTAINS MAYBE USED B Y OR DISCLOSED TO ANY THIRD P A R T Y WITHOUTPRIO R WRITTEN CONSENT OF COM PAL ELECTRONICS, INC.

MAYBE USED B Y OR DISCLOSED TO ANY THIRD P A R T Y WITHOUTPRIO R WRITTEN CONSENT OF COM PAL ELECTRONICS, INC.

2018/09/21 2019/09/21

3

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

WHL-U(3/12)SPI,SMB,LPC,ESPI

LA-H101P

1

o f

8 51Thursday, September 20, 2018

0.A0.A0.A

5

4

3

2

1

< HD A U D I O >

D D

HDA_BIT_CLK_R<33>

HDA_SYNC_R<33>

1 2

RC46 33_0402_5%

EMI@

1 2

RC48 33_0402_5%

1 2

RC47 33_0402_5%

< T o Enable ME Override>

1 2

ME_EN<34>

C C

+3VS

1 2

RC55 2.2K_0402_5%@

RC51 0_0402_5%@

HDA_SPKR

12

@

HDA_BIT_CLK

HDA_SYNC

HDA_SDOUT

RC49 499_0402_1%

HDA_SDOUT

HDA_SYNC HDA_BIT_CLK

HDA_SDIN0<33>HDA_SDOUT_R<33>

CNV_RF_RESET#<31>

CLKREQ_CNV#<31>

HDA_SPKR<33>

HDA_SDOUT

CNV_RF_RESET#

HDA_SPKR

UC1G

BN3 4

HDA_SYNC/I2S0_SFRM

BN3 7

HDA_BCLK/I2S0_SCLK

BN3 6

HDA_SDO/I2S0_TXD

BN3 5

HDA_SDI0/I2S0_RXD

BL3 6

HDA_SDI1/I2S1_ RXD/SNDW1_DATA

BL3 5

HDA_RST#/I2S1_SCLK/SNDW1_CLK

CK 23

GPP_D23/I2S_MCLK

BL3 7

I2S1_SFRM/SNDW 2_CLK

BL3 4

I2S1_TXD/SNDW2_DATA

CJ 32

GPP_H1/I2S2_SFRM/CNV_BT_I 2S_BCLK/CNV_RF_RESET#

CH32

GPP_H0/I2S2_SCLK/CNV_BT_ I2S_SCLK

CH29

GPP_H2/I2S2_TXD/CNV_BT_I 2S_SDI/MODEM_CLKREQ

CH30

GPP_H3/I2S2_RXD/CNV_BT_I2S_SDO

CP 24

GPP_D19/DMIC_CLK0/SNDW4_CLK

CN24

GPP_D20/DMIC_DATA0/SNDW4_DATA

CK 25

GPP_D17/DMIC_CLK1/SNDW3_CLK

CJ 25

GPP_D18/DMIC_DATA1/SNDW3_DATA

CF 35

GPP_B14/SPKR

WHL-U_BGA1528

7 of 20

GPP_G0/SD_CMD GPP_G1/SD3_DATA0 GPP_G2/SD3_DATA1 GPP_G3/SD3_DATA2

GPP_G4/SD_DATA3

GPP_G5/SD_CD# GPP_G6/SD_CLK

GPP_G7/SD_WP

GPP_A17/SD_VDD1_PWR_EN# /ISH_GP7

GPP_A16/SD_1P8_SEL

SD_1P8_RCOMP SD_3P3_RCOMP

CH36 CL 35 CL 36 CM3 5 CN35 CH35 CK 36 CK 34

BW 36 BY31

CK 33 CM3 4

SOC_SD_RCOMP

1 2

RC50 200_0402_1%

SPKR (Internal Pull Down):

TOP Swap Override

0 = Disable TOP Swap mode. ==> Default

1 = Enable TOP Swap Mode.

UC1I

CNV_CRX_DTX_N0<31>

1 2

RC5275K_0402_5% CNVi@

CNV_RF_RESET#

Follow Jefferson Peak schematic check list.

B B

1 2

RC164 1K_0402_5%@

WLBT_OFF#

CNV_CRX_DTX_P0<31>

CNV_CRX_DTX_N1<31> CNV_CRX_DTX_P1<31>

CLK_CNV_CRX_DTX_N<31> CLK_CNV_CRX_DTX_P<31>

CLK_CNV_CTX_DRX_N<31> CLK_CNV_CTX_DRX_P<31>

For MX230

CNV_CTX_DRX_N0<31> CNV_CTX_DRX_P0<31>

CNV_CTX_DRX_N1<31> CNV_CTX_DRX_P1<31>

RC56

150_0402_1%

[11] GC6_FB_EN1V8

TP_INT#<35>

WLBT_OFF#<31>

1 2

CNVi@

1 2

RC57

10K_0402_5%

CNV_WT_RCOMP

GC6_FB_EN1V8

WLBT_OFF#

SOC_A4WP_PRESENT

CR30

CNV_WR_D0N

CP 30

CNV_WR_D0P

CM3 0

CNV_WR_D1N

CN30

CNV_WR_D1P

CN32

CNV_WT_D0N

CM3 2

CNV_WT_D0P

CP 33

CNV_WT_D1N

CN33

CNV_WT_D1P

CN31

CNV_WR_CLKN

CP 31

CNV_WR_CLKP

CP 34

CNV_WT_CLKN

CN34

CNV_WT_CLKP

CP 32

CNV_WT_RCOMP_0

CR32

CNV_WT_RCOMP_1

CP 20

GPP_F0/CNV_PA_BLANKI NG

CK 19

GPP_F1

CG 17

GPP_F2

CR14

GPP_C8/UART0_RXD

CP 14

GPP_C9/UART0_TXD

CN14

GPP_C10/UART0_RTS#

CM1 4

GPP_C11/UART0_CTS#

CJ 17

GPP_F8/CNV_MFUART2_RXD

CH17

GPP_F9/CNV_MFUART2_TXD

CF 17

GPP_F23/A4WP_ PRESENT

WHL-U_BGA1528

GPP_H18/CPU_C10_GATE#

GPP_H19/TIMESYNC_0

GPP_D4/IMGCLKOUT0/ BK4/SBK4

GPP_H20/IMGCLKOUT_1

GPP_F12/EMMC_DATA0 GPP_F13/EMMC_DATA1 GPP_F14/EMMC_DATA2 GPP_F15/EMMC_DATA3 GPP_F16/EMMC_DATA4 GPP_F17/EMMC_DATA5 GPP_F18/EMMC_DATA6 GPP_F19/EMMC_DATA7

GPP_F20/EMMC_RCLK

GPP_F21/EMMC_CLK

GPP_F11/EMMC_CMD

GPP_F22/EMMC_RESET#

EMMC_RCOMP

9 of 20

GPP_H21 GPP_H22 GPP_H23 GPP_F10

GPD7

GPP_F3

GPP_H21 XTAL frequency select.

0: 38.4 / 19.2 MHz

1: 24MHz XTAL select.

SOC_C10_GATE#

CN27

CM2 7

SOC_GPP_H21

CF 25 CN26 CM2 6 CK 17

SOC_GPD7

BV35 CN20

CG 25

XTAL INPUT MODE (HVM ONLY)

CH25

LOW: XTAL INPUT IS SINGLE ENDED

CR20

HIGH: XTAL IS ATTACHED

CM2 0 CN19 CM1 9 CN18 CR18 CP 18 CM1 8

CM1 6 CP 16 CR16 CN16

CK 15

1 2

RC53 4.7K_0201_5%

1 2

RC54 100K_0201_5%

SOC_SD_RCOMP

T10TP@

+3VALW

A A

T O D G P U

SOC_GPIO_C10 GPU_EVENT#

5

RC59

1

2

0_0402_5%

@

4

GPU_EVENT# [24 ]

Security Classification

2018/09/21 2019/09/21

Issued Date

THI S SHEET OF ENG INEERI NG DRAWING IS TH E PROPRI ETARY PR OPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THI S SHEET OF ENG INEERI NG DRAWING IS TH E PROPRI ETARY PR OPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET I NFORMATION.T HIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COM PETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION.T HIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COM PETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION.T HIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COM PETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEE T NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEE T NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEE T NOR T HE INFORMATION IT CONTAINS MAYBE USED B Y OR DISCLOSED TO ANY THIRD P A R T Y WITHOUTPRIO R WRITTEN CONSENT OF COM PAL ELECTRONICS, INC.

MAYBE USED B Y OR DISCLOSED TO ANY THIRD P A R T Y WITHOUTPRIO R WRITTEN CONSENT OF COM PAL ELECTRONICS, INC.

2018/09/21 2019/09/21

3

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

WHL-U(4/12)HDA,EMMC,SDIO,CSI2

LA-H101P

Thursday, September 20, 2018

LA-H101P

9

1

51

o f

0.A0.A0.A

5

4

3

2

1

+3VS

10K_0402_5%

SE00000UC00

SYS_RESET#

EC_RSMRST#

SYS_PWROK

CLKREQ_PCIE#1

CLKREQ_PCIE#3 CLKREQ_PCIE#4

SOC_SRTCRST#

SOC_RTCRST#

CLR CMOS

SM_INTRUDER#

SYS_RESET# PCH_PWROK EC_RSMRST#

WAKE#

+1.05V_VCCST

1 2

RC72 0_0402_5%@

12

RC89 1K_0402_5%

1 2

RC90 60.4_0402_1%

1

CC15 100P_0402_50V8J

ESD@

2

Card Reader

EC_VCCST_PG

1 2

RC61 10K_0402_5%

1 2

RC63 10K_0402_5%

1 2

RC64

D D

+3VL_RTC

C C

B B

1 2

RC68 10K_0402_5%@

1 2

RC70 20K_0402_5%

1 2

CC5 1U_0201_6.3V6M

1 2

RC71 20K_0402_5%

1 2

CC6 1U_0201_6.3V6M

1 2

CLRP1 SHORT PADS

1 2

RC75 1M_0402_5%

+3VALW

1 2

RC77 10K_0402_5%

1 2

RC78 10K_0402_5%

1 2

RC79 10K_0402_5%

1 2

ESD@

CC10 100P_0402_50V8J

1 2

ESD@

CC11 100P_0402_50V8J

1 2

ESD@

CC12 100P_0402_50V8J

+3VALW

1 2

RC82 1K_0402_5%

Fro m EC (Open-Drain)

VCCST_PWRGD<34>

A A

5/9 Naming Rule

DGPU

SSD

[21] CLK_PEG_N0 [21] CLK_PEG_P0

[21] CLKREQ_PEG#0

<32>

WLAN

EC_CLEAR_CMOS# <34>

EC_RSMRST#<34>

T11 TP@

SYS_PWROK<34>

PCH_PWROK<34>

CLK_PCIE_N1 CLK_PCIE_P1<32>

CLKREQ_PCIE#1<32>

CLK_PCIE_N3<31> CLK_PCIE_P3<31>

CLKREQ_PCIE#3<31>

CLK_PCIE_N4<37> CLK_PCIE_P4<37>

CLKREQ_PCIE#4<37>

SOC_PLTRST# SYS_RESET# EC_RSMRST#

H_CPUPWRGD EC_VCCST_PG

SYS_PWROK PCH_PWROK EC_RSMRST#

WAKE#

UC1J

AW2

CLKREQ_PEG#0

CLKREQ_PCIE#1

CLKREQ_PCIE#3

CLKREQ_PCIE#4

CF3 2

CE3 2

CF3 0

CE3 1

CE3 0

CF3 1

AY3

BC1 BC2

BD3 BC3

BH3 BH4

BA1 BA2

BE1 BE2

WHL-U_BGA1528

< PCH PLTRSTBuffer >

SOC_PLTRST#

BJ35 CN1 0 BR36

CR1 0

BP30

BV34 BY32

BU30 BU32 BU34

1 2

RC76 0_0402_5%

UC1K

GPP_B13/PLTRST# SYS_RESET# RSM RST #

AR2

PROCPWRGD

BJ2

VCCST_PWRGOOD

SYS_PWROK

BP31

PCH_PWROK DSW_PWROK

GPP_A13/SUSWARN#/SUSPWRDACK GPP_A15/SUSACK#

WAKE# GPD2/LAN_WAKE# GPD11/LANPHYPC

WHL-U_BGA1528

CLKOUT_PCIE_N_0 CLKOUT_PCIE_P_0 GPP_B5/SRCCLKREQ0#

CLKOUT_PCIE_N_1 CLKOUT_PCIE_P_1 GPP_B6/SRCCLKREQ1#

CLKOUT_PCIE_N_2 CLKOUT_PCIE_P_2 GPP_B7/SRCCLKREQ2#

CLKOUT_PCIE_N_3 CLKOUT_PCIE_P_3 GPP_B8/SRCCLKREQ3#

CLKOUT_PCIE_N_4 CLKOUT_PCIE_P_4 GPP_B9/SRCCLKREQ4#

CLKOUT_PCIE_N_5 CLKOUT_PCIE_P_5 GPP_B10/SRCCLKREQ5#

10 of 2 0

12

RC80

100K_0402_5%

GPP_B11/EXT_PW R_GATE#

11 of 20

CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P

GPD8/SUSCLK

CLK_BIASREF

CLKIN_XTAL

12

CC9 100P_0402_50V8J

GPP_B12/SLP_S0#

GPD4/SLP_S3# GPD5/SLP_S4#

GPD10/SLP_S5#

SLP_SUS#

SLP_LAN#

GPD9/SLP_WLAN#

GPD6/SLP_A#

GPD3/PW RBTN#

GPD1/ACPRESENT

GPD0/BATLOW#

INTRUDER#

GPP_B2/VRALERT#

INPUT3VSEL

XTAL_IN

XTAL_OUT

RTC X1 RTC X2

SRTCRST#

RTC RST #

PCI_RST# <31,32,34,37>

ESD@

BJ37 BU36 BU27 BT29

BU29 BT31 BT30 BU37

BU28 BU35 BV36

BR35

CC3 7 CC3 6

BT27

AU1 AU2

BT32

CK3 CK2

CJ 1 CM3

BN31 BN32

BR37 BR34

PM_SLP_S0# PM_SLP_S3# PM_SLP_S4# PM_SLP_S5#

SLP_WLAN# PM_SLP_A#

PBTN_OUT# AC_PRESENT_R PM_BATLOW#

SM_INTRUDER#

SOC_VRALERT#

SOC_INPUT3VSEL

33E_SOC_XTAL24_IN_R 33E_SOC_XTAL24_OUT_R

XCLK_BIASREF CLKIN_XTAL

SOC_RTCX1 SOC_RTCX2

SOC_SRTCRST# SOC_RTCRST#

RC83 0_0402_5%@

SUSCLK <31>

CLKIN_XTAL <31>

T12TP@

PM_SLP_S3# <34> PM_SLP_S4# <34,42,45>

T13TP@

T14TP@

T15TP@

1 2

33E_SOC_XTAL24_IN_R

33E_SOC_XTAL24_OUT_R

XCLK_BIASREF

CLKIN_XTAL

Follow CFL-U PDG_Rev_0.7 Stuff 60.4 ohm(RC110) PD for CNL-U/ WHL-U and CFL-U

RC69 33_0201_5%EMI@

RC73 33_0201_5%EMI@

SOC_RTCX2

SOC_RTCX1

PBTN_OUT# <34> AC_PRESENT <34>

RC60

RC65

1 2

LC1

@EMI@

1

4

DLM0NSN900HY2D_4P

1 2

60.4_0402_1%

1 2

10K_0402_5%

33E_SOC_XTAL24_IN

2

3

33E_SOC_XTAL24_OUT

1 2

RC81 10M_0402_5%

YC 2

1 2

32.768KHZ_9PF_X1A000141000200

SJ10000PW00

1

CC13

8.2P_0402_50V8B

2

PM_BATLOW#

AC_PRESENT

SOC_VRALERT#

SOC_INPUT3VSEL

1 2

RC74 200K_0402_1%

YC 1 24MHZ_18PF_XRCGB24M000F2P51R0

SJ10000UJ00

3

NC

27P_0402_50V8J

CC7

1

2

1 2

RC84 8.2K_0402_5%

1 2

RC85 10K_0402_5%@

1 2

RC86 10K_0402_5%@

1 2

RC87 4.7K_0402_5%@

1 2

RC88 4.7K_0402_5%

2

4

1

CC14

8.2P_0402_50V8B

2

+3VALW

27P_0402_50V8J

CC8

1

2

Security Classificat ion

Is s u ed Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I N C . AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I N C . AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETEN T D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETEN T D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETEN T D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, IN C . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, IN C . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, IN C . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED B Y OR DISCLOSED TO AN Y THIRD P A R T Y WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C .

MAY BE USED B Y OR DISCLOSED TO AN Y THIRD P A R T Y WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C .

5

4

MAY BE USED B Y OR DISCLOSED TO AN Y THIRD P A R T Y WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C .

3

2018/09/21 2019/09/21

Compal S ecret Data

Deciphered Date

Compal Electronics, Inc.

Tit le

WHL-U(5/12)CLK,PM,GPIO

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

LA-H101P

1

10 51Thursday, September 20, 2018

0.A0.A0.A

of

5

4

3

2

1

GSPI0_MOSI(Internal Pull Down):

No R e b o o t

0 = DisableNo R e b o o t mode. ==> Default

1 = Enable No R e b o o t Mode. (PCH will disable the TCO

Timers y s t e m re b o ot fe a t u re ) . This funct i oni s u s e f u l when running ITP/X DP.

D D

GSPI1_MOSI (Internal Pull Down):

Boo t BI OS Strap B it

0 = SPI Mode ==> Default

1 = LPC Mode

+3VS

1 2

RC97 4.7K_0402_5%@

1 2

RC98 150K_0402_5%@

C C

+3VS

1 2

RC166 2.2K_0402_5%

1 2

RC167 2.2K_0402_5%

1 2

RC102 10K_0402_5%

1 2

RC163 4.7K_0402_5%

1 2

RC103 49.9K_0402_1%

1 2

RC108 49.9K_0402_1%

1 2

RC109 2.2K_0402_5%

1 2

RC105 2.2K_0402_5%

1 2

RC113 20K_0201_5%@

1 2

RC114 20K_0201_5%@

GSPI0_MOSI

GSPI1_MOSI

I2C1_SDA_TS I2C1_SCL_TS

SOC_GPIO_A7 TS_INT#

UART0_RX UART0_TX I2C_0_SDA I2C_0_SCL

CNV_RGI_CRX_DTX

Place close to PCH

B B

for RMT test

+1.8VALW

RC162 20K_0201_5%@

12

CNV_RGI_CTX_DRX

T o u c h P ad

T o u c h P an el

E C sensor Hub

SENSOR_EC_INT<34>

CNV_BRI_CRX_DTX<31> CNV_RGI_CTX_DRX<31> CNV_BRI_CTX_DRX<31> CNV_RGI_CRX_DTX<31>

UART0_RX<31>

UART0_TX<31>

I2C_0_SDA<35> I2C_0_SCL<35>

I2C1_SDA_TS<28> I2C1_SCL_TS<28>

I2C_2_SDA<34> I2C_2_SCL<34>

Capacity

Description

WITHOUT ON-BOARD RAM

HYNIX 2666MHz (H5AN8G6NCJR-VKC)S340

MICRON 2666MHz (MT40A512M16LY-075:E)S340

4GB

MICRON 2666MHz (MT40A512M16LY-075:E)C340 SAMSUNG 2666MHz (K4A8G165WC-BCTD)S340 SAMSUNG 2666MHz (K4A8G165WC-BCTD)C340

N/A

Capacity

Description

WITHOUT ON-BOARD RAM

SAMSUNG 2666MHz (K4A8G165WC-BCTD) HYNIX 2666MHz (H5AN8G6NCJR-VKC) MICRON 2666MHz (MT40A512M16LY-075:E)

4GB

N/A N/A N/A N/A

SOC_GPIO_A7

GSPI0_MOSI

OBRAM_ID0

OBRAM_ID1 OBRAM_ID2 GSPI1_MOSI

CNV_BRI_CRX_DTX CNV_RGI_CTX_DRX

CNV_RGI_CRX_DTXCNV_BRI_CRX_DTX

UART0_RX UART0_TX

CC2 7 CC3 2 CE2 8 CE2 7 CE2 9

CA3 1 CA3 2 CC2 9 CC3 0 CA3 0

CK2 0

CG1 9

CH1 9

CR1 2 CP1 2 CN1 2

CM1 2

CM1 1

CN1 1

CK1 2

CF2 7

CH2 7

CJ 20

CJ 12

CJ 30

X76

NO_MD@

X7680438L81 X7680538LA1HYNIX 2666MHz (H5AN8G6NCJR-VKC)C340 X7680438L82 X7680538LA2 X7680438L83 X7680538LA3

N/A N/A

GPP_B19 OBRAM_ID0 OBRAM_ID1 OBRAM_ID2

0 0 0 1 0 1 0 0 1 1 1 1 0 1 1 1 0 1 1 1

UC1F

GPP_B15/GSPI0_CS0# GPP_A7/PIRQA#/GSPI 0_CS1# GPP_B16/GSPI0_CLK GPP_B17/GSPI0_MISO GPP_B18/GSPI0_MOSI

GPP_B19/GSPI1_CS0# GPP_A11/PME#/GSPI1_CS1#/ SD_VDD2_PWR_EN# GPP_B20/GSPI1_CLK GPP_B21/GSPI1_MISO GPP_B22/GSPI1_MOSI

GPP_F5/CNV_BRI_RSP GPP_F6/CNV_RGI_DT GPP_F4/CNV_BRI_DT GPP_F7/CNV_RGI_RSP

GPP_C20/UART2_RXD GPP_C21/UART2_TXD GPP_C22/UART2_RTS# GPP_C23/UART2_CTS#

GPP_C16/I2C0_SDA GPP_C17/I2C0_SCL

GPP_C18/I2C1_SDA GPP_C19/I2C1_SCL

GPP_H4/I2C2_SDA

CF2 9

GPP_H5/I2C2_SCL

GPP_H6/I2C3_SDA

CH2 8

GPP_H7/I2C3_SCL

GPP_H8/I2C4_SDA

CJ 31

GPP_H9/I2C4_SCL

WHL-U_BGA1528

PART NUMBER(R1)

N/A

SA0000BMN00

SA0000ARD20

SA0000B6F00

GPP_B20

GPP_B21

0 0

GPP_D9/ISH_SPI_CS#/GS PI2_CS0#

GPP_D10/ISH_SPI_CLK/GS PI2_CLK GPP_D11/ISH_SPI_MISO/ GSPI2_MISO GPP_D12/ISH_SPI_MOSI/ GSPI2_MOSI

GPP_D5/ISH_I 2C0_SDA

GPP_D6/ISH_I2C0_SCL

GPP_D7/ISH_I 2C1_SDA

GPP_D8/ISH_I2C1_SCL

GPP_H10/I2C5_SDA/ISH_I2C2_S DA

GPP_D13/ISH_UART0_RXD/SML0BDATA/I 2C4B_SDA

GPP_A12/ISH_GP6/BM_BUSY#/ SX_EXIT_HOLDOFF#

6 of 20

GPP_H11/I2C5_SCL/ISH_I2C2_SCL

GPP_D14/ISH_UART0_TXD/SML0BCLK/I 2C4B_SCL

GPP_D15/ISH_UART0_RTS#/GSPI 2_CS1#

GPP_D16/ISH_UART0_CTS#/SML0BALERT#

GPP_C12/UART1_RXD/ISH_UART1_RXD

GPP_C13/UART1_TXD/ISH_UART1_TXD GPP_C14/UART1_RTS#/ISH_UART1_RTS# GPP_C15/UART1_CTS#/ISH_UART1_CTS#

GPP_A18/ISH_GP0 GPP_A19/ISH_GP1 GPP_A20/ISH_GP2 GPP_A21/ISH_GP3 GPP_A22/ISH_GP4 GPP_A23/ISH_GP5

+3VS+3VS +3VS

12

RC91 10K_0402_5%

@

OBRAM_ID0 OBRAM_ID1 OBRAM_ID2

12

RC94 10K_0402_5%

@

RC94 NO_MD@ 10K_0402_5%

CN22 CR22 CM2 2 CP2 2

CK2 2 CH20

CH22 CJ 22

CJ 27 CJ 29

CM2 4 CN23 CM2 3 CR24

CG1 2 CH12 CF1 2 CG1 4

BW35 BW34 CA3 7 CA3 6 CA3 5 CA3 4 BW37

12

RC92 10K_0402_5%

@

12

RC95 10K_0402_5%

@

RC95 NO_MD@ 10K_0402_5%

MODEL_SETTING3 MODEL_SETTING2 MODEL_SETTING0 MODEL_SETTING1

DGPU_PWR_EN DGPU_HOLD_RST # GPU_ALL_PGOOD DGPU_PRSNT

TS_INT# DGPU_SEL0 DGPU_SEL1

12

RC93 10K_0402_5%

@

RC96 10K_0402_5%

@

RC96 NO_MD@ 10K_0402_5%

DGPU_PWR_EN [26] DGPU_HOLD_RST# [21] GPU_ALL_PGOOD [2 6]

TS_INT# [2 8]

Function

Arrary MIC

MODEL_SETTING2 (GPP_D10)

Single MIC

+3VS

Function

C340-15

Arrary_MIC@

1 2

RC168

1 2

RC169 10K_0402_5%

Single_MIC@

MODEL_SETTING1 (GPP_D12)

S340-15 S340-14

+3VS

Function

DIS 0

1 2

RC99 10K_0402_5%@

1 2

RC100 10K_0402_5%C340@

RC100 S340_15@ 10K_0402_5%

@

1 2

RC107 10K_0402_5%

1 2

RC104 10K_0402_5%C340@

RC107 S340_15@ 10K_0402_5%

DGPU_PRSNT (GPP_C15)

UMA Only

+3VS+1.8VALW

1 2

RC115 10K_0402_5%

1 0

10K_0402_5%

MODEL_SETTING0 (GPP_D11)

0 0 1 0

RC99 S340_14@ 10K_0402_5%

RC104S340_14@ 10K_0402_5%

1

DGPU_PRSNT

MODEL_SETTING2

0 1

MODEL_SETTING1

MODEL_SETTING0

6 Layer / 8 Layer PCB

+3VS

1 2

RC171 10K_0402_5%@

1 2

RC172 10K_0402_5%@

A A

[9] GC6_FB_EN1V8

SOC_GPIO_B16 GC6_FB_EN

GC6_FB_EN1V8

5

1 2

RC121 0_0201_5%

N16S@

1 2

RC122 0_0201_5%

N17S@

GC6_FB_EN [24,25]

4

TO DG P U

Security Classificat ion

Is s u ed Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPALELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPALELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETEN T D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETEN T D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETEN T D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, IN C . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, IN C . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, IN C . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED B Y OR DISCLOSED TO AN Y THIRD P A R T Y WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C .

MAY BE USED B Y OR DISCLOSED TO AN Y THIRD P A R T Y WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C .

3

2018/09/21 2019/09/21

Compal S ecret Data

MODEL_SETTING3

Deciphered Date

2

Compal Electronics, Inc.

Tit le

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

WHL-U(6/12)GPIO,I2C,GSPI

LA-H101P

1

11 51Thursday, September 20, 2018

of

0.A0.A0.A

5

4

3

2

1

D D

dGPU

Card Reader

C C

NGFF WLAN+BT

HDD

SSD1

B B

Colay SATA

[21] PCIE_CRX_DTX_N5

[21] PCIE_CRX_DTX_P5 [21] PCIE_CTX_C_DRX_N5 [21] PCIE_CTX_C_DRX_P5

[21] PCIE_CRX_DTX_N6

[21] PCIE_CRX_DTX_P6 [21] PCIE_CTX_C_DRX_N6 [21] PCIE_CTX_C_DRX_P6

[21] PCIE_CRX_DTX_N7

[21] PCIE_CRX_DTX_P7 [21] PCIE_CTX_C_DRX_N7 [21] PCIE_CTX_C_DRX_P7

[21] PCIE_CRX_DTX_N8

[21] PCIE_CRX_DTX_P8 [21] PCIE_CTX_C_DRX_N8 [21] PCIE_CTX_C_DRX_P8

PCIE_CRX_DTX_N9<37> PCIE_CRX_DTX_P9<37> PCIE_CTX_DRX_N9<37> PCIE_CTX_DRX_P9<37>

PCIE_CRX_DTX_N11<31> PCIE_CRX_DTX_P11<31> PCIE_CTX_DRX_N11<31> PCIE_CTX_DRX_P11<31>

SATA_CRX_DTX_N1<32> SATA_CRX_DTX_P1<32> SATA_CTX_DRX_N1<32> SATA_CTX_DRX_P1<32>

PCIE_CRX_DTX_N13<32> PCIE_CRX_DTX_P13<32> PCIE_CTX_DRX_N13<32> PCIE_CTX_DRX_P13<32>

PCIE_CRX_DTX_N14<32> PCIE_CRX_DTX_P14<32> PCIE_CTX_DRX_N14<32> PCIE_CTX_DRX_P14<32>

PCIE_CRX_DTX_N15<32> PCIE_CRX_DTX_P15<32> PCIE_CTX_DRX_N15<32> PCIE_CTX_DRX_P15<32>

SATA_CRX_DTX_N2<32> SATA_CRX_DTX_P2<32> SATA_CTX_DRX_N2<32> SATA_CTX_DRX_P2<32>

1

CC17 DIS@

1

CC18 DIS@

1

CC19 DIS@

1

CC20 DIS@

1

CC16 DIS@

1

CC21 DIS@

1

CC22 DIS@

1

CC23 DIS@

1 2

RC126 100_0402_1%

2

0.22U_0201_6.3V6M

2

0.22U_0201_6.3V6M

2

0.22U_0201_6.3V6M

2

0.22U_0201_6.3V6M

2

0.22U_0201_6.3V6M

2

0.22U_0201_6.3V6M

2

0.22U_0201_6.3V6M

2

0.22U_0201_6.3V6M

PCIE_RCOMPN PCIE_RCOMPP

PCIE_CTX_DRX_N5 PCIE_CTX_DRX_P5

PCIE_CTX_DRX_N6 PCIE_CTX_DRX_P6

PCIE_CTX_DRX_N7 PCIE_CTX_DRX_P7

PCIE_CTX_DRX_N8 PCIE_CTX_DRX_P8

UC1H

BW 9

PCIE5_RXN/USB31_5_RX N

BW 8

PCIE5_RXP/USB31_5_RXP

BW 4

PCIE5_TXN/USB31_5_TXN

BW 3

PCIE5_TXP/USB31_5_TXP

BU6

PCIE6_RXN/USB31_6_RX N

BU5

PCIE6_RXP/USB31_6_RXP

BU4

PCIE6_TXN/USB31_6_ TXN

BU3

PCIE6_TXP/USB31_6_TXP

BT7

PCIE7_RXN

BT6

PCIE7_RXP

BU2

PCI E7_ TXN

BU1

PCI E7_ TXP

BU9

PCIE8_RXN

BU8

PCIE8_RXP

BT4

PCI E8_ TXN

BT3

PCI E8_ TXP

BP5

PCIE9_RXN

BP6

BR2

PCI E9_ TXN

BR1

PCI E9_ TXP

BN6

PCIE10_RXN

BN5

BR4

PCIE10_TXN

BR3

PCIE10_TXP

BN1 0

PCIE11_RXN/SATA0_RXN

BN8

PCIE11_RXP/SATA0_RXP

BN4

PCIE11_TXN/SATA0_TXN

BN3

PCIE11_TXP/SATA0_TXP

BL6

PCIE12_RXN/SATA1A_RXN

BL5

PCIE12_RXP/SATA1A_RXP

BN2

PCIE12_TXN/SATA1A_TXN

BN1

PCIE12_TXP/SATA1A_TXP

BK6

PCIE13_RXN

BK5

PCIE13_RXP

BM4

PCIE13_TXN

BM3

PCIE13_TXP

BJ6

PCIE14_RXN

BJ5

PCIE14_RXP

BL2

PCIE14_TXN

BL1

PCIE14_TXP

BG5

PCIE15_RXN/SATA1B_RXN

BG6

PCIE15_RXP/SATA1B_RXP

BL4

PCIE15_TXN/SATA1B_TXN

BL3

PCIE15_TXP/SATA1B_TXP

BE5

PCIE16_RXN/SATA2_RXN

BE6

PCIE16_RXP/SATA2_RXP

BJ4

PCIE16_TXN/SATA2_TXN

BJ3

PCIE16_TXP/SATA2_TXP

CE 6

PCIE_RCOMP_N

CE 5

PCIE_RCOMP_P

CR28

GPP_H12/M2_SKT2/CFG_0

CP 28

GPP_H13/M2_SKT2/CFG_1

CN28

GPP_H14/M2_SKT2/CFG_2

CM2 8

GPP_H15/M2_SKT2/CFG_3

PCIE9_RXP

PCIE10_RXP

WHL-U_BGA1528

When PCIE16/SATA2 is used as SATA P o r t 1 (ODD), then PCIE15/SATA1B (M.2 SSD) cannot be used as SATA P o r t 1.

PCIE2_RXN/USB31_2_ RXN/SSIC_1_RXN

PCIE2_RXP/USB31_2_RXP/SSIC_1_RXP

PCIE2_TXN/USB31_2_TXN/SSI C_1_TXN

PCIE2_TXP/USB31_2_TXP/SSIC_1_TXP

GPP_E9/USB2_OC0#/G P_BSSB_CLK

GPP_E10/USB2_OC1#/G P_BSSB_DI

GPP_E0/SATAXPCIE0/SATAGP0 GPP_E1/SATAXPCIE1/SATAGP1 GPP_E2/SATAXPCIE2/SATAGP2

GPP_E8/SATALED#/SPI1_CS1#

8 of 20

PCIE1_RXN/USB31_1_RXN PCIE1_RXP/USB31_1_RXP

PCIE1_TXN/USB31_1_TXN PCIE1_TXP/USB31_1_TXP

PCIE3_RXN/USB31_3_ RXN PCIE3_RXP/USB31_3_RXP

PCIE3_TXN/USB31_3_TXN PCIE3_TXP/USB31_3_TXP

PCIE4_RXN/USB31_4_ RXN PCIE4_RXP/USB31_4_RXP

PCIE4_TXN/USB31_4_TXN PCIE4_TXP/USB31_4_TXP

USB2_1N USB2_1P

USB2_2N USB2_2P

USB2_3N USB2_3P

USB2_4N USB2_4P

USB2_5N USB2_5P

USB2_6N USB2_6P

USB2_7N USB2_7P

USB2_8N USB2_8P

USB2_9N USB2_9P

USB2_10N USB2_10P

USB 2_C OMP

USB 2_I D

USB2_VBUSSENSE

GPP_E11/USB2_OC2# GPP_E12/USB2_OC3#

GPP_E4/DEVSLP0 GPP_E5/DEVSLP1 GPP_E6/DEVSLP2

UFS_RESET#

CB 5 CB 6 CA 4 CA 3

BY8 BY9 CA 2 CA 1

BY7 BY6 BY4 BY3

BW 6 BW 5 BW 2 BW 1

CE 3 CE 4

CE 1 CE 2

CG 3 CG 4

CD3 CD4

CG 5 CG 6

CC1 CC2

CG 8 CG 9

CB 8 CB 9

CH5 CH6

CC3 CC4

CC5 CE 8 CC6

CK 6 CK 5 CK 8 CK 9

CP 8 CR8 CM8

CN8 CM1 0 CP 10

CN7

AR3

USB2_COMP USB2_ID USB2_SENSE

USB_OC0# USB_OC1# USB_OC2# USB_OC3#

WL_OFF#

NGFF_SSD_PEDET

USB3_CRX_DTX_N1 <37> USB3_CRX_DTX_P1 <37> USB3_CTX_DRX_N1 <37> USB3_CTX_DRX_P1 <37>

USB3_CRX_DTX_N2 <37> USB3_CRX_DTX_P2 <37> USB3_CTX_DRX_N2 <37> USB3_CTX_DRX_P2 <37>

USB3_CRX_MTX_N3 <38> USB3_CRX_MTX_P3 <38> USB3_CTX_MRX_N3 <38> USB3_CTX_MRX_P3 <38>

USB20_N1 <37> USB20_P1 <37>

USB20_N2 <37> USB20_P2 <37>

USB20_N3 <38> USB20_P3 <38>

USB20_N4 <28> USB20_P4 <28>

USB20_N6 <28> USB20_P6 <28>

USB20_N7 <35> USB20_P7 <35>

USB20_N10 <31> USB20_P10 <31>

1 2

RC123 113_0402_1%

1 2

RC124 1K_0402_5%@

1 2

RC125 1K_0402_5%@

USB_OC0# <37> USB_OC1# <37>

WL_OFF# <31>

DEVSLP2 <32>

NGFF_SSD_PEDET <32>

USB2.0 / 3.0 Port (IO - 1)

USB2.0 / 3.0 Port (IO - 2)

USB2.0 / 3.0 Port (Type-C)

USB2.0 / 3.0 Port (MB - 1)

USB2.0 / 3.0 Port (MB - 2)

USB2.0 / 3.0 Port (Type-C)

Touch Screen

Camera

FP

NGFF WLAN+BT

Trace length max: 450mils

WL_OFF#

USB_OC0# USB_OC1# USB_OC2# USB_OC3#

1 2

RC165 1K_0402_5%@

RC127 10K_0201_5% RC128 10K_0201_5% RC129 10K_0201_5% RC130 10K_0201_5%

+3VALW

12 12 12 12

+3VS

A A

Security Classification

2018/09/21 2019/09/21

Issued Date

THI S SHEET OF ENG INEERI NG DRAWING IS TH E PROPRI ETARY PR OPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THI S SHEET OF ENG INEERI NG DRAWING IS TH E PROPRI ETARY PR OPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET I NFORMATION.T HIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COM PETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION.T HIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COM PETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION.T HIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COM PETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEE T NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEE T NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEE T NOR T HE INFORMATION IT CONTAINS MAYBE USED B Y OR DISCLOSED TO ANY THIRD P A R T Y WITHOUTPRIO R WRITTEN CONSENT OF COM PAL ELECTRONICS, INC.

MAYBE USED B Y OR DISCLOSED TO ANY THIRD P A R T Y WITHOUTPRIO R WRITTEN CONSENT OF COM PAL ELECTRONICS, INC.

5

4

2018/09/21 2019/09/21

3

Compal Secret Data

Deciphered Date

2

NGFF_SSD_PEDET

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

WHL-U(7/12)PCIE,USB,SATA

1 2

RC131 10K_0402_5%

LA-H101P

12 51Thursday, September 20, 2018

1

o f

0.A0.A0.A

5

+1.05VALW TO +1.05V_VCCST

D D

SYSON<34,44>

SUSP#<34,39,44>

1 2

RC134 0_0402_5%@

1 2

RC135 0_0402_5%@

+1.8VALW TO +1.8VS

+VL

1

C C

@

2

+1.05VS_VCCIO

0.1U_0201_10V K X5R

CC29

SUSP#

+1.05VALW

1

2

1U_0201_6.3V6M

CC30

+VL

1U_0201_6.3V6M

1

CC24

2

+1.05VALW

EN_1.05V_VCCSTU

EN_1.8VS

+1.8VALW

I(Max) : 0.2 A(+1.8VS) RON(Max) : 25 mohm V drop : 0.005 V

+1.05VALW TO +1.05VS_VCCIO

I(Max) : 3.675 A(+1.05VS_VCCIO) RON(Max) : 6.2 mohm V drop : 0.019 V

UC15

1

VIN 1

2

VIN 2

7

VIN thermal

3

VBIAS

4

ON

EM5201V_DFN8_3X3

SA00008R600

VOU T

GND

6

5

PSC SideBSC Side

B B

1U_0201_6.3V6M

1

CC39

2

1

CC40

2

1U_0201_6.3V6M

1

CC41

CC42

2

10U_0402_6.3V6M

1

CC43

2

4

I(Max) : 0.16 A(+1.05V_VCCST) RON(Max) : 25 mohm V drop : 0.004 V

UC14

+1.05VS_VCCIO_STG

10U_0402_6.3V6M

@

1

CC45

CC44

2

1 2

3

4

5

6 7

+1.05VS_VCCIO +1.05VS_VCCSTG

VOU T1

VIN 1

VOU T1

VIN 1

ON1

VBIAS

ON2

VIN 2 VIN 2

AOZ1331 DFN 14P

SA0000BKC00

1

2

GND

VOU T2 VOU T2

GPAD

RC139 0_0402_5%

10U_0402_6.3V6M

@

1

CC46

2

14 13

12

CT1

11

10

CT2

9 8

15

1 2

RC137 0_0805_5%

1 2

1

CC47

2

CC26 8200P_0402_25V7K

CC27 1000P_0402_50V7K

10U_0402_6.3V6M

CC48

1 2

RC136 0_0402_5%

3

1 2

RC133 0_0402_5%

1 2

+1.05VS_VCCIO

1

CC31

@

0.1U_0201_10V K X5R

2

+1.05V_VCCST

0.1U_0201_10V6K

1

2

+1.8VS

0.1U_0201_10V6K

CC28

1

@

2

+1.2V

UC1N

AD36

3.3A

CC25

@

+1.05V_VCCST

+VCCPLL_OC

+1.05VS_VCCSTG

0.02A

0.12A

0.19A

1uF X1

0.1uF X1

+1.05V_VCCST

10U_0402_6.3V6M

1

@

CC32

2

CC33

2

Close to BP11 & BP2 Close to BG1 & BG2

1

2

10U_0402_6.3V6M

+1.2V

PSC Side

@

CC34

4.7U_0402_6.3V6M

@

1

CC49

2

10U_0402_6.3V6M

1

CC35

2

CC36

2

Close to BR11 & BT11

10U_0402_6.3V6M

@

1

CC50

2

1

CC51

2

10U_0402_6.3V6M

CC52

AH3 2 AH3 6 AM3 6 AN3 2

AW 32

AY3 6 BE3 2 BH3 6

R3 2

BC2 8

BP1 1

BP2

BG1 BG2

BL2 7

BM2 6

BR1 1

BT1 1

Y36

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 VDDQ11

RSVD1

VCCST1 VCCST2

VCCSTG1 VCCSTG2

VCCPLL_OC1 VCCPLL_OC2

VCCPLL1 VCCPLL2

WHL-U_BGA1528

+VCCPLL_OC

1U_0201_6.3V6M

@

1

CC53

2

VCCIO_SENSE

VSSIO_SENSE

VSSSA_SENSE VCCSA_SENSE

14 of 20

1U_0201_6.3V6M

1

2

Close to BM26

1U_0201_6.3V6M

1

2

VCCIO1 VCCIO2 VCCIO3 VCCIO4 VCCIO5 VCCIO6 VCCIO7 VCCIO8

VCCIO9 VCCIO10 VCCIO11 VCCIO12 VCCIO13 VCCIO14 VCCIO15 VCCIO16

VCCSA2 VCCSA1 VCCSA3 VCCSA5 VCCSA6 VCCSA4 VCCSA9 VCCSA7

VCCSA8 VCCSA13 VCCSA14 VCCSA10 VCCSA11 VCCSA12 VCCSA15 VCCSA16

PSC Side

CC37

BSC SidePSC Side

1

CC54

2

AK2 4 AK2 6 AL2 4 AL2 5 AL2 6 AL2 7 AM2 5 AM2 7 BH2 4 BH2 5 BH2 6 BH2 7 BJ2 4 BJ2 6 BP1 6 BP1 8

BG8 BG1 0 BH9 BJ8 BJ9 BJ1 0 BK8 BK2 5 BK2 7 BL8 BL9 BL1 0 BL2 4 BL2 6 BM2 4 BN2 5

BP2 8 BP2 9

BE7 BG7

1U_0201_6.3V6M

@

CC55

1

+1.05VS_VCCIO

3.679A

+VCC_SA

6A

Trace Length Match < 25 mils

VSSSA_SENSE VCCSA_SENSE

+1.05VS_VCCSTG

1U_0201_6.3V6M

1

2

PSC Side

1U_0201_6.3V6M

1

CC38

2

1U_0201_6.3V6M

1

CC57

CC56

2

Close to CPUUnderneath CPU

Close to CPU Underneath CPU

+1.2V TO +VCCPLL_OC

+VCCPLL_OC+1.2V

A A

Security Classification

2018/09/21 2019/09/21

Issued Date

THI S SHEET OF ENGINEERIN G DRAWING IS TH E PROPRI ETARY PR OPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

THI S SHEET OF ENGINEERIN G DRAWING IS TH E PROPRI ETARY PR OPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET I NFORMATION.T HIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COM PETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION.T HIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COM PETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION.T HIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COM PETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEE T NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEE T NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEE T NOR T HE INFORMATION IT CONTAINS MAYBE USED B Y OR DISCLOSED TO ANY THIRD P A R T Y WITHOUTPRIO R WRITTEN CONSENT OF COM PAL ELECTRONICS, INC.

MAYBE USED B Y OR DISCLOSED TO ANY THIRD P A R T Y WITHOUTPRIO R WRITTEN CONSENT OF COM PAL ELECTRONICS, INC.

5

4

2018/09/21 2019/09/21

3

Compal Secret Data

Deciphered Date

I(Max) : 120m A(+VCCPLL_OC) RON(Max) : 6.2 mohm V drop : 0.019 V

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

WHL-U(8/12)Power

LA-H101P

13 51Thursday, September 20, 2018

1

0.A0.A0.A

o f

+1.05VALW

1

2

@

CC61 1U_0201_6.3V6M

5

+1.05VALW

1

2

CC62 1U_0201_6.3V6M

4

3

2

1

Close to BP20Close to BV18

D D

1

CC63 1U_0201_6.3V6M

2

Close to BV2

+1.05VALW+1.05VALW

1

2

CC64

4.7U_0402_6.3V6M

Close to BV12

1

CC65 10U_0402_6.3V6M

2

+1.8VALW

Imax : 0.702A

+3VALW

Imax : 0.21A

+1.8VALW

1

CC68 1U_0201_6.3V6M

2

Close to CP17

C C

+3VALW

1

@

CC71 1U_0201_6.3V6M

2

1

@

CC72

0.1U_0201_10V KX 5R

2

Close to BT24

1 2

CC73 1U_0201_6.3V6M

Close to CP29

+3VALW

1

@

CC74

0.1U_0201_10V KX 5R

2

+3VALW

+3V_1.8V_HDA

Close to BR24

+3VALW

B B

RF@

LC2

1 2

BLM15BB221SN1D_2P

SM01000BV00

+3V_1.8V_HDA

1

CC76

0.1U_0402_25V6

2

RF@

RF request

A A

Imax: 4.982A

Internal LDO

DCPDSW

+1.05VALW

UC1P

BP20

VCCPRIM_1P05_1

BW16

VCCPRIM_1P05_9

BW18

BW19

VCCPRIM_1P05_11

BY16

VCCPRIM_1P05_12

CA1 4

VCCPRIM_1P05_14

CC1 5

VCCPRIM_1P8_1

CD1 5

VCCPRIM_1P8_4

CD1 6

VCCPRIM_1P8_5

CP1 7

VCCPRIM_1P8_8

CB2 2

VCCPRIM_3P3_4

CB2 3

VCCPRIM_3P3_5

CC2 2

VCCPRIM_3P3_6

CC2 3

VCCPRIM_3P3_7

CD2 2

VCCPRIM_3P3_8

CD2 3

VCCPRIM_3P3_9

CP2 9

VCCPRIM_3P3_10

BU15

VCCPRIM_CORE1

BU22

VCCPRIM_CORE2

BV15

VCCPRIM_CORE3

BV16

VCCPRIM_CORE4

BV18

VCCPRIM_CORE5

BV19

VCCPRIM_CORE6

BV20

VCCPRIM_CORE7

BV22

VCCPRIM_CORE8

BW20

VCCPRIM_CORE9

BW22

VCCPRIM_CORE10

CA1 2

VCCPRIM_CORE11

CA1 6

VCCPRIM_CORE12

CA1 8

VCCPRIM_CORE13

CA1 9

VCCPRIM_CORE14

CA2 0

VCCPRIM_CORE15

CB1 2

VCCPRIM_CORE16

CB1 4

VCCPRIM_CORE17

CB1 5

VCCPRIM_CORE18

BT24

VCCDSW_1P05

BU14

VCCAPLL_1P05_4

BV12

VCCPRIM_MPHY_1P05_1

BW12

VCCPRIM_MPHY_1P05_3

BW14

BY12 BY14

VCCPRIM_MPHY_1P05_6

BV2

VCCAMPHYPLL_1P05

BR15

VCCAPLL_1P05_2

CC1 2

VCCDUSB_1P05

BR24

VCCDSW_3P3_1

BT20

VCCHDA

BV23

VCCSPI

BT18

VCCPRIM_1P05_4

BT19

VCCPRIM_1P05_5

BU18

VCCPRIM_1P05_7

BU19

VCCPRIM_1P05_8

BT22

VCCPRIM_1P05_6

BP22

VCCPRIM_1P05_2

BV14

VCCPRIM_MPHY_1P05_2

WHL-U_BGA1528

K12 K14 K15 K17 K18 K20 L25 M2 4 M2 6 P24 P26 R24 R25 R26

W25

V24

Y25 Y24

VCCPRIM_1P05_10

VCCPRIM_MPHY_1P05_4 VCCPRIM_MPHY_1P05_5

UC1O

VCCOPC1 VCCOPC2 VCCOPC3 VCCOPC4 VCCOPC5 VCCOPC6 VCCOPC7 VCCOPC8 VCCOPC9 VCCOPC10 VCCOPC11 VCCOPC12 VCCOPC13 VCCOPC14

VCC_OPC_1P8_2 VCC_OPC_1P8_1

VCC_OPC_1P8_4 VCC_OPC_1P8_3

WHL-U_BGA1528

VCCPRIM_3P3_3

VCCPRIM_1P05_13

VCCPRIM_1P05_3

VCCAPLL_1P05_3

VCCA_BCLK_1P05

VCCAPLL_1P05_1

VCCA_SRC_1P05

VCCA_XTAL_1P05

VCCDPHY_1P24_2 VCCDPHY_1P24_4

VCCDPHY_1P24_1 VCCDPHY_1P24_3

VCCDPHY_EC_1P24

VCCDSW_3P3_2

VCCA_19P2_1P05

VCCPRIM_1P8_2 VCCPRIM_1P8_3 VCCPRIM_1P8_6 VCCPRIM_1P8_7 VCCPRIM_1P8_9

VCCPRIM_3P3_2

VCCPRIM_3P3_1

GPP_B0/CORE_VID0 GPP_B1/CORE_VID1

16 of 2 0

VCCEOPIO1 VCCEOPIO2 VCCEOPIO3 VCCEOPIO4 VCCEOPIO5 VCCEOPIO6 VCCEOPIO7 VCCEOPIO8

VCCEOPIO_SENSE VSSEOPIO_SENSE

15 of 2 0

VCCRTC

DCP RTC

AA24 AA26 AB25 AC24 AC25 AC26 AD24 AD26

V25 T25

CB1 6

BR23

BY20 BP24

BR20

BT12

BP14

BR14

BU12

CP5

BY24 CA2 4

BY23 CA2 3 CP2 5

BT23

BR12

CC1 8 CC1 9 CD1 8 CD1 9 CP2 3

BW23

BP23

CB3 6 CB3 5

+1.05VALW

+3VALW

+3VL_RTC

DCPRTC

Intenal LDO

VCCDPHY_EC_1P24

Imax : 0.702A

@

1 2

CC66 1U_0201_6.3V6M

Close to BP24

+VCCDPHY_1.24V

Close to CP25

1 2

CC69 4.7U_0402_6.3V6M

+1.05VALW

+1.8VAL W

+1.8VALW

1

@

CC75 1U_0201_6.3V6M

2

Close to CP23

R T C Bat t e r y

+3VL_RTC +RTCBATT

W=20mils

1 2

RC141 0_0402_5%

1

CC67 1U_0201_6.3V6M

2

Close to BR23

Saf tysuggestio n r emove E E sid e ,KeepPWRsid e

+1.05VALW

1

CC70 1U_0201_6.3V6M

2

Close to CP5

+VCCDPHY_1.24V

VCCDPHY_EC_1P24

When CNVi is no t used in t he design: VCCDPHY_1P24 pin shall be disconnected from t he VCCLDOSRAM_IN_1P24 pin . The decoupling capacitor shall remain connected to t he VCCDPHY_1P24 p in.

1 2

R1 0_0201_5%CNVi@

VCCOPC and VCCEOPIO for CFL U43e only

Security Classificat ion

Is s u ed Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I N C . AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I N C . AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETEN T D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETEN T D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETEN T D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, IN C . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, IN C . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, IN C . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED B Y OR DISCLOSED TO AN Y THIRD P A R T Y WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C .

MAY BE USED B Y OR DISCLOSED TO AN Y THIRD P A R T Y WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C .

5

4

MAY BE USED B Y OR DISCLOSED TO AN Y THIRD P A R T Y WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C .

3

2018/09/21 2019/09/21

Compal S ecret Data

Deciphered Date

Compal Electronics, Inc.

Tit le

WHL-U(9/12)Power

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

LA-H101P

14 51Thursday, September 20, 2018

1

14 51Thursday, September 20, 2018

0.A0.A0.A

of

5

4

3

2

1

+VCC_CORE +VCC_CORE

UC1L

AN9

VCCCORE5

AN1 0

VCCCORE1

D D

C C

AN2 4 AN2 6 AN2 7

AP2

AP9 AP24 AP26

AR5

AR6

AR7

AR8 AR1 0 AR2 5 AR2 7

AT9 AT2 4 AT2 6

AU5

AU6

AU7

AU8

AU9 AU2 4 AU2 5 AU2 6 AU2 7

AV2

AV5

AV7 AV10 AV27

AW 5 AW 6 AW 7 AW 8 AW 9

AW 10

BB9 BC2 4

AY9 BB24

VCCCORE2 VCCCORE3 VCCCORE4 VCCCORE6 VCCCORE9 VCCCORE7 VCCCORE8 VCCCORE13 VCCCORE14 VCCCORE15 VCCCORE16 VCCCORE10 VCCCORE11 VCCCORE12 VCCCORE19 VCCCORE17 VCCCORE18 VCCCORE24 VCCCORE25 VCCCORE26 VCCCORE27 VCCCORE28 VCCCORE20 VCCCORE21 VCCCORE22 VCCCORE23 VCCCORE30 VCCCORE32 VCCCORE33 VCCCORE29 VCCCORE31 VCCCORE39 VCCCORE40 VCCCORE41 VCCCORE42 VCCCORE43 VCCCORE34

RSVD3 RSVD4 RSVD1 RSVD2

WHL-U_BGA1528

SVID ALERT

B B

VCCCORE35 VCCCORE36 VCCCORE37 VCCCORE38 VCCCORE44 VCCCORE45 VCCCORE48 VCCCORE49 VCCCORE50 VCCCORE46 VCCCORE47 VCCCORE51 VCCCORE52 VCCCORE56 VCCCORE57 VCCCORE58 VCCCORE59 VCCCORE53 VCCCORE54 VCCCORE55 VCCCORE63 VCCCORE64 VCCCORE60 VCCCORE61 VCCCORE62 VCCCORE69 VCCCORE65 VCCCORE66 VCCCORE67 VCCCORE68 VCCCORE70 VCCCORE73 VCCCORE71 VCCCORE72 VCCCORE74

VCC_SENSE

12 of 20

+1.05V_VCCST

12

VSS_SENSE

VIDALERT#

AW 24 AW 25 AW 26 AW 27 AY24 AY26 BA5 BA7 BA8 BA25 BA27 BB2 BB26 BC5 BC6 BC7 BC9 BC1 0 BC2 6 BC2 7 BD5 BD8 BD1 0 BD2 5 BD2 7 BE9 BE24 BE25 BE26 BE27 BF2 BF9 BF2 4 BF2 6 BG2 7

AN6 AN5

AA3

AA1

VIDSCK

AA2

VID SOU T

Y3

RSVD5

BG3

VCCSTG1

Place the PU resistors close to CPU

RC147 56_0402_5%

SOC_SVID_ALERT#

VR_SVID_CLK

VR_SVID_DATA

VCCCORE_SENSE <47>

VSSCORE_SENSE <47>

VR_SVID_CLK <47>

+1.05VS_VCCSTG

+VCC_CORE

Trace Length Match < 25 mils

+VCC_GT +VCC_GT

UC1M

AA9 AB2 AB8 AB9

AB10

AC8 AD9 AE8 AE9

AE10

AF1 0

AG8 AG9 AH9

AJ1 0

AK2 AK9

AL1 0

AM8

A5 A6

A8 A11 A12 A14 A15 A17 A18 A20

AF2 AF8

AJ8

AL8 AL9

B3

B4

B6

B8 B11 B14 B17 B20

C2 C3 C6 C7

C8 C1 1 C1 2 C1 4 C1 5 C1 7 C1 8 C2 0

D4

D7 D1 1 D1 2 D1 4 Y10

VCCGT8 VCCGT9 VCCGT10 VCCGT1 VCCGT2 VCCGT3 VCCGT4 VCCGT5 VCCGT6 VCCGT7 VCCGT11 VCCGT13 VCCGT14 VCCGT15 VCCGT12 VCCGT16 VCCGT17 VCCGT19 VCCGT20 VCCGT18 VCCGT22 VCCGT23 VCCGT21 VCCGT24 VCCGT25 VCCGT26 VCCGT28 VCCGT27 VCCGT29 VCCGT30 VCCGT32 VCCGT33 VCCGT31 VCCGT34 VCCGT39 VCCGT40 VCCGT41 VCCGT42 VCCGT35 VCCGT36 VCCGT37 VCCGT38 VCCGT49 VCCGT51 VCCGT52 VCCGT53 VCCGT54 VCCGT43 VCCGT44 VCCGT45 VCCGT46 VCCGT47 VCCGT48 VCCGT50 VCCGT62 VCCGT63 VCCGT55 VCCGT56 VCCGT57 VCCGT119

WHL-U_BGA1528

VCCGT_SENSE VSSGT_SENSE

13 of 20

VCCGT58 VCCGT59 VCCGT60 VCCGT61 VCCGT64 VCCGT69 VCCGT70 VCCGT71 VCCGT72 VCCGT65 VCCGT66 VCCGT67 VCCGT68 VCCGT73 VCCGT74 VCCGT75 VCCGT76 VCCGT77 VCCGT78 VCCGT79 VCCGT87 VCCGT88 VCCGT89 VCCGT90 VCCGT80 VCCGT81 VCCGT82 VCCGT83 VCCGT84 VCCGT85 VCCGT86 VCCGT95 VCCGT96 VCCGT91 VCCGT92 VCCGT93 VCCGT94 VCCGT98

VCCGT97 VCCGT100 VCCGT101

VCCGT99 VCCGT102 VCCGT104 VCCGT105 VCCGT106 VCCGT103 VCCGT107 VCCGT108 VCCGT109 VCCGT111 VCCGT112 VCCGT110 VCCGT114 VCCGT113 VCCGT115 VCCGT116 VCCGT117 VCCGT118 VCCGT120

D1 5 D1 7 D1 8 D2 0 E4 F5 F6 F7 F8 F11 F14 F17 F20 G11 G12 G14 G15 G17 G18 G20 H5 H6 H7 H8 H1 1 H1 2 H1 4 H1 5 H1 7 H1 8 H2 0 J7 J8 J11 J14 J17 J20 K2 K11 L7 L8 L10 M9 N7 N8 N9 N1 0 P2 P8 R9 T8 T9 T10 U8 U1 0 V2 V9 W8 W9 Y8

E3 D2

VCCGT_SENSE <47> VSSGT_SENSE <47>

Trace Length Match < 25 mils

SOC_SVID_ALERT#

SVID DATA

VR_SVID_DATA

A A

5

1 2

RC148 220_0402_5%

+1.05V_VCCST

Place the PU resistors close to CPU

12

RC149 100_0402_1%

VR_ALERT# <47>

VR_SVID_DATA <47>

4

(To VR)

Security Classification

2018/09/21 2019/09/21

Issued Date

THI S SHEET OF ENGINEERIN G DRAWING IS TH E PROPRI ETARY PR OPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

THI S SHEET OF ENGINEERIN G DRAWING IS TH E PROPRI ETARY PR OPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET I NFORMATION.T HIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COM PETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION.T HIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COM PETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION.T HIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COM PETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEE T NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEE T NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEE T NOR T HE INFORMATION IT CONTAINS MAYBE USED B Y OR DISCLOSED TO ANY THIRD P A R T Y WITHOUTPRIO R WRITTEN CONSENT OF COM PAL ELECTRONICS, INC.

MAYBE USED B Y OR DISCLOSED TO ANY THIRD P A R T Y WITHOUTPRIO R WRITTEN CONSENT OF COM PAL ELECTRONICS, INC.

2018/09/21 2019/09/21

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

WHL-U(10/12)Power,SVID

LA-H101P

15 51Thursday, September 20, 2018

1

0.A0.A0.A

o f

5

D D

UC1R

CR34

VSS_1

BT5

VSS_2

BY5

VSS_3

CP 35

VSS_4

CM3 7

VSS_5

CK 37

VSS_6

AW 1

VSS_7

CM1

VSS_8

BD6

VSS_9

AY4

VSS_10

B34

VSS_11

E35

VSS_12

A4

VSS_13

AE24

VSS_14

AE26

VSS_15

AF2 5

VSS_16

AG2 4

VSS_17

AG2 6

VSS_18

AH2 4

VSS_19

AH2 5

VSS_20

B2

VSS_21

B36

VSS_22

C3 6

VSS_23

C3 7

C C

B B

CN1 CN2

CN37

CP 2

A32 F33

BJ7

CJ 36

A36

BK10

CJ 4

AB27

BK2 CK 1

AB3 BK28 AB30

BK3

CK 4 AB33 BK33

CK 7 AB36

BK4

CL 2

AB4

BK7 CM1 3

AB7

BL2 5 CM1 7 AC1 0

BL2 8 CM2 1 AC2 7

BL2 9 CM2 5 AC3 0

BL3 0 CM2 9

BL3 1 CM3 1 AD3 3

BL3 2 CM3 3 AD3 5

D1

A3

VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72

WHL-U_BGA1528

17 of 20

VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98

VSS_99 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144

BL7 AE25 BM3 3 CM5 AE27 BM3 5 CM9 AE30 BM3 6 CN13 AE7 BM9 CN17 AF2 7 BN3 0 CN21 AF3 BN7 CN25 AF3 0 CN29 AF3 3 BP15 AF3 6 AF4 CN5 AF7 BP25 CN9 AG1 0 BP3 CP 1 BP32 CP 11 AH2 7 BP33 CP 13 AH2 8 BP4 CP 15 AH2 9 BP7 CP 19 AH3 0 CP 21 AH3 1 BR1 9 CP 27 AH3 3 BR2 5 AH3 5 CP 37 AJ2 5 BT1 5 AJ2 8 BT1 6 CP 9 AJ7 CR2 AK3 CR36 AK33 D2 1 AK36 BT2 5 D2 5 AK4 BT2 8 AL2 8 BT3 3 D5 AL2 9

4

UC1S

BT3 5

VSS_145

D6

VSS_146

AL3 2

VSS_147

BT3 6

VSS_148

D8

VSS_149

AL7

VSS_150

D9

VSS_151

AM1 0

VSS_152

BU1 1

VSS_153

E23

VSS_154

AM2 8

VSS_155

E27

VSS_156

AM3 3

VSS_157

BU2 3

VSS_158

E29

VSS_159

AM3 5

VSS_160

BU2 4

VSS_161

E31

VSS_162

BU2 5

VSS_163

E33

VSS_164

AN2 5

VSS_165

BU7

VSS_166

E9

VSS_167

AN2 8

VSS_168

BV1 1

VSS_169

F12

VSS_170

AN2 9

VSS_171

F15

VSS_172

AN3 0

VSS_173

F18

VSS_174

AN3 1

VSS_175

BV3

VSS_176

F2

VSS_177

AN7

VSS_178

BV3 1

VSS_179

F21

VSS_180

AN8

VSS_181

BV3 3

VSS_182

F24

VSS_183

BV4

VSS_184

F3

VSS_185

AP3

VSS_186

BW 11

VSS_187

F4

VSS_188

AP3 3

VSS_189

BW 15

VSS_190

G21

VSS_191

AP3 6

VSS_192

G27

VSS_193

AP4

VSS_194

G33

VSS_195

AR2 8

VSS_196

G35

VSS_197

G36

VSS_198

AT3 3

VSS_199

BW 24

VSS_200

G9

VSS_201

AT3 5

VSS_202

H2 1

VSS_203

AT3 6

VSS_204

BW 7

VSS_205

H2 7

VSS_206

AT4

VSS_207

BY1 1

VSS_208

AU1 0

VSS_209

BY1 5

VSS_210

H9

VSS_211

AU2 8

VSS_212

BY2 2

VSS_213

J12

VSS_214

AU2 9

VSS_215

J15

VSS_216

WHL-U_BGA1528

18 of 20

VSS_217 VSS_218 VSS_219 VSS_220 VSS_221 VSS_222 VSS_223 VSS_224 VSS_225 VSS_226 VSS_227 VSS_228 VSS_229 VSS_230 VSS_231 VSS_232 VSS_233 VSS_234 VSS_235 VSS_236 VSS_237 VSS_238 VSS_239 VSS_240 VSS_241 VSS_242 VSS_243 VSS_244 VSS_245 VSS_246 VSS_247 VSS_248 VSS_249 VSS_250 VSS_251 VSS_252 VSS_253 VSS_254 VSS_255 VSS_256 VSS_257 VSS_258 VSS_259 VSS_260 VSS_261 VSS_262 VSS_263 VSS_264 VSS_265 VSS_266 VSS_267 VSS_268 VSS_269 VSS_270 VSS_271 VSS_272 VSS_273 VSS_274 VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286 VSS_287 VSS_288 VSS_289

3

BY2 5 J18 AU3 2 BY2 8 J21 AV2 5 BY3 3 J24 AV2 8 BY3 5 J33 AV3 BY3 6 J36 AV3 3 J6 AV3 6 C1 K21 AV4 C2 1 K22 AV6 C2 5 K24 AV8 C2 9 K25 AW 28 C3 3 K27 AW 29 C4 K28 AW 3 C9 K29 AW 30 CA 11 K3 AW 31 CA 15 K30 AY3 3 CA 22 K31 AY3 5 K32 B12 K4 B15 CA 25 K9 B18 CB 11 L27 B21 L33 B23 L35 B25 CB 18 L36 B27 CB 19 L6 B29 CB 2 N2 5 B31 CB 20 N2 7 CB 25

2

UC1T

CB 3

CB 33

CB 4

CB 7

BA10 CC11

BA28

CC20

CC25

BB33 CC28

BB36 CC31

CC7

BC2 5 CD11

CD12

BC2 9 CD14

BC3 2 CD24

CD25

BC8

CE 33

BD2 8 CE 35

BD3 3 CE 36

BD3 5

CE 7

BD3 6 CF 11

BE10 CF 14

BE28 CF 19

BE29

B37

P10

P33

P36

BA3

R2 7 BB3

R2 8

R2 9

R3 0 BB4

R3 1

T27

T30

T33 T35

T36

U2 6

V26

V27

V30

V33

CF 2 V36 BE3

N6

B5

P3 B7

B9

P4

P7

T7

U7

V3

VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296 VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305 VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313 VSS_314 VSS_315 VSS_316 VSS_317 VSS_318 VSS_319 VSS_320 VSS_321 VSS_322 VSS_323 VSS_324 VSS_325 VSS_326 VSS_327 VSS_328 VSS_329 VSS_330 VSS_331 VSS_332 VSS_333 VSS_334 VSS_335 VSS_336 VSS_337 VSS_338 VSS_339 VSS_340 VSS_341 VSS_342 VSS_343 VSS_344 VSS_345 VSS_346 VSS_347 VSS_348 VSS_349 VSS_350 VSS_351 VSS_352 VSS_353 VSS_354 VSS_355 VSS_356 VSS_357 VSS_358 VSS_359 VSS_360 VSS_361

WHL-U_BGA1528

19 of 20

VSS_362 VSS_363 VSS_364 VSS_365 VSS_366 VSS_367 VSS_368 VSS_369 VSS_370 VSS_371 VSS_372 VSS_373 VSS_374 VSS_375 VSS_376 VSS_377 VSS_378 VSS_379 VSS_380 VSS_381 VSS_382 VSS_383 VSS_384 VSS_385 VSS_386 VSS_387 VSS_388 VSS_389 VSS_390 VSS_391 VSS_392 VSS_393 VSS_394 VSS_395 VSS_396 VSS_397 VSS_398 VSS_399 VSS_400 VSS_401 VSS_402 VSS_403 VSS_404 VSS_405 VSS_406 VSS_407 VSS_408 VSS_409 VSS_410 VSS_411 VSS_412 VSS_413 VSS_414 VSS_415 VSS_416 VSS_417 VSS_418 VSS_419 VSS_420 VSS_421 VSS_422 VSS_423 VSS_424 VSS_425 VSS_426 VSS_427 VSS_428 VSS_429 VSS_430 VSS_431 VSS_432 VSS_433

CF 23 V4 BE30 CF 28 W10 BE31 CF 3 W27 CF 4 W30 BF3 CG 33 W7 BF3 3 CG 7 BF3 6 Y26 BF4 CH31 Y27 BG2 5 Y30 BG2 8 CJ 11 Y33 CJ 14 Y35 BH2 8 CJ 19 Y7 BH2 9 CJ 23 BH3 2 CJ 28 BH3 3 CJ 33 BH3 5 CJ 35 BP19 BR1 6 BY18 BY19 CC16 BU1 6 CC14 BR2 2 BU2 0 CD20 BT1 4 BP12 CB 24 CC24 J5 U2 4 BD7 AR4 AU4 AW 4 BA6 BC4 BE4 BE8 BA4 BD4 BG4 CJ 2 CJ 3 AM5 CM4 AC5 AG5 CR6

1

A A

Security Classification

2018/09/21 2019/09/21

Issued Date

THI S SHEET OF ENGINEERIN G DRAWING IS TH E PROPRI ETARY PR OPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

THI S SHEET OF ENGINEERIN G DRAWING IS TH E PROPRI ETARY PR OPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET I NFORMATION.T HIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COM PETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION.T HIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COM PETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION.T HIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COM PETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEE T NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEE T NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEE T NOR T HE INFORMATION IT CONTAINS MAYBE USED B Y OR DISCLOSED TO ANY THIRD P A R T Y WITHOUTPRIO R WRITTEN CONSENT OF COM PAL ELECTRONICS, INC.

MAYBE USED B Y OR DISCLOSED TO ANY THIRD P A R T Y WITHOUTPRIO R WRITTEN CONSENT OF COM PAL ELECTRONICS, INC.

5

4

2018/09/21 2019/09/21

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

WHL-U(11/12)GND

LA-H101P

1

0.A0.A0.A

o f

16 51Thursday, September 20, 2018

5

D D

+1.05VS_VCCIO

1 2

RC150 10K_0402_5%@

1 2

RC151 1K_0402_5%@

C C

1 2

RC152 49.9_0402_1%

1 2

RC153 1K_0402_5%

B B

CFG0

CFG3

CFG_RCOMP

CFG4

DFX Privacy Strap

1 : Disabled;

CFG 3

Set DFX disable bit in debug i nterface M SR

0 : Enabled;

Set DFX enable bit in debug i nterface M SR

Display Po r t Presence Strap

1 : Disabled;

CFG 4

A A

No Physical Display Por t at t a c h e d t o E mbed ded D i s p l a y port

0 : Enabled;

An e x te r n a l Display P ort device is connected t o the Embedded Display Po r t

4

UC1Q

CG 2 CG 1

BV2 4 BV2 5

BK3 6 BK3 5

AM4

AM3

AB5

A35 D3 4

T4

R4 T3 R3

J4

M4

J3

M3

R2 N2 R1 N1

J2

L2

J1

L1

L3 N3 L4 N4

W4

H4 H3

G3 G4

W3

G2 G1

CFG _0

CFG _1 CFG _2 CFG _3 CFG _4 CFG _5 CFG _6 CFG _7 CFG _8 CFG _9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15

CFG_16 CFG_18 CFG_17 CFG_19

CFG_RCOMP

ITP_PMODE

RSV D25 RSV D24

RSV D34 RSV D33

RSV D22 RSV D23

VSS_436 VSS_437

RSV D17 RSV D16

RSV D35 RSV D7

RSV D6

RSV D1 RSV D30

RSV D32 RSV D31

WHL-U_BGA1528

CFG0

CFG3 CFG4

CFG_RCOMP

3

F37

RSVD_TP5

F34

RSVD_TP4

CP 36

IST_TRIG

CN36

RSVD_TP3

BJ3 6

RSV D15

BJ3 4

RSV D14

BK3 4

TP_1

BR1 8

TP_3

BT9

RSV D21

BT8

RSV D20

BP8

RSV D18

BP9

RSV D19

CR4

RSV D29

CP 3

RSV D26

CR3

RSV D27

AT3

RSV D12

AU3

RSV D13

AN1

RSV D8

AN2

RSV D9

AN4

RSV D11

AN3

RSV D10

AL2

RSV D3

AL1

RSV D2

AL4

RSV D5

AL3

RSV D4

BP3 4

TP1

BP3 6

TP_2

BP3 5

TP_4

C3 4

VSS_435

A34

RSVD_TP1

B35

RSVD_TP2

20 of 20

RSV D28

ZVM# MS M#

SKTOCC#

CR35

AH2 6 AJ2 7

E1

RSVD28

Follow Intel suggetion reserve TP

2

T2407TP@

1

Security Classification

2018/09/21 2019/09/21

Issued Date

THI S SHEET OF ENG INEERI NG DRAWING IS TH E PROPRI ETARY PR OPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THI S SHEET OF ENG INEERI NG DRAWING IS TH E PROPRI ETARY PR OPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET I NFORMATION.T HIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COM PETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION.T HIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COM PETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION.T HIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COM PETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEE T NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEE T NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEE T NOR T HE INFORMATION IT CONTAINS MAYBE USED B Y OR DISCLOSED TO ANY THIRD P A R T Y WITHOUTPRIO R WRITTEN CONSENT OF COM PAL ELECTRONICS, INC.

MAYBE USED B Y OR DISCLOSED TO ANY THIRD P A R T Y WITHOUTPRIO R WRITTEN CONSENT OF COM PAL ELECTRONICS, INC.

5

4

2018/09/21 2019/09/21

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

WHL-U(12/12)CFG,RSVD

LA-H101P

17 51Thursday, September 20, 2018

1

0.A0.A0.A

o f

5

4

3

2

1

Interleaved Memory

+DDR_VREF_CA

U1

M1

DDR_A_MA0

1

CD2

MD@

.047U_0402_16V7K

D D

DDR_A_BA0<7,19> DDR_A_BA1<7,19>

DDR_A_CLK0<7> DDR_A_CLK#0<7> DDR_A_CKE0<7,19>

DDR_A_ODT0<7,19>

DDR_A_CS#0<7,19>

C C

DDR_A_ACT#<7,19>

DDR_A_ALERT#<7>

DDR_A_PARITY<7,19>

DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4

2

DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14

DDR_A_BA0 DDR_A_BA1

DDR_A_CLK0 DDR_A_CLK#0 DDR_A_CKE0

DDR_A_ODT0 DDR_A_CS#0 DDR_A_MA16 DDR_A_MA15

DDR_A_DQS#1 DDR_A_DQS1 DDR_A_DQS#0 DDR_A_DQS0

MEMRST#

RU1 240_0402_1%MD@

1 2

DDR_A_ACT# DDR_A_BG0

DDR_A_ BG0<7,19>

DDR_A_ALERT# DDR_A_PARITY

+2.5V

VR E F C A

P3

A0

P7

A1

R3

A2

N7

A3

N3

A4

P8

A5

P2

A6

R8

A7

R2

A8

R7

A9

M3

A1 0 / A P

T2

A1 1

M7

A1 2 / B C

T8

A1 3

L2

A1 4 / W E

N2

BA0

N8

BA1

E2

DMU/DBIU

E7

DML/ DB IL

K7

CK_t

K8

CK_c

K2

CKE

K3

ODT

L7

CS

L8

RAS

M8

CAS

A7

DQS U_c

B7

DQS U_t

F3

DQS L_ c

G3

DQS L_ t

P1

RESET

F9

ZQ

L3

AC T

M2

BG0

N9

TEN

P9

AL E RT

T3

PAR

T7

NC

B1

VP P

R9

VP P

96-B AL L

SDRAM DDR4

K4AAG165WB-MCRC C38

@

DDR_A_D4

G2

DQL 0

DDR_A_D2

F7

DQL 1

DDR_A_D3

H3

DQL 2

DDR_A_D5

H7

DQL 3

DDR_A_D7

H2

DQL 4

DDR_A_D0

H8

DQL 5

DDR_A_D6

J3

DQL 6

DDR_A_D1

J7

DQL 7

DDR_A_D13

A3

DQU 0

DDR_A_D9

B8

DQU 1

DDR_A_D12

C3

DQU 2

DDR_A_D15

C7

DQU 3

DDR_A_D10

C2

DQU 4

DDR_A_D14

C8

DQU 5

DDR_A_D8

D3

DQU 6

DDR_A_D11

D7

DQU 7

B3

VD D

B9

VD D

D1

VD D

G7

VD D

J1

VD D

J9

VD D

L1

VD D

L9

VD D

R1

VD D

T9

VD D

A1

VD D Q

A9

VD D Q

C1

VD D Q

D9

VD D Q

F2

VD D Q

F8

VD D Q

G1

VD D Q

G9

VD D Q

J2

VD D Q

J8

VD D Q

B2

VS S

E1

VS S

E9

VS S

G8

VS S

K1

VS S

K9

VS S

M9

VS S

N1

VS S

T1

VS S

A2

VS S Q

A8

VS S Q

C9

VS S Q

D2

VS S Q

D8

VS S Q

E3

VS S Q

E8

VS S Q

F1

VS S Q

H1

VS S Q

H9

VS S Q

+1.2V

Replace with240 OhmtoSupportDDP@ Replac ewith240 Ohmto SupportDDP@ Replace with240Ohm toSupportDDP@

RD1 240_0402_1%DDP @

1 2

DDR_A_BG1_R

+DDR_VREF_CA

1

CD3

MD@

.047U_0402_16V7K

2

DDR_A_BG1_R <19>

+2.5V

+DDR_VREF_CA

U2

M1

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14

DDR_A_BA0 DDR_A_BA1

DDR_A_CLK0 DDR_A_CLK#0 DDR_A_CKE0

DDR_A_ODT0 DDR_A_CS#0 DDR_A_MA16 DDR_A_MA16 DDR_A_MA15

DDR_A_DQS#3 DDR_A_DQS3 DDR_A_DQS#2 DDR_A_DQS2

RU2 240_0402_1%MD@

1 2

DDR_A_ACT# DDR_A_BG0

DDR_A_ALERT# DDR_A_PARITY

VR E F C A

P3

A0

P7

A1

R3

A2

N7

A3

N3

A4

P8

A5

P2

A6

R8

A7

R2

A8

R7

A9

M3

A1 0 / AP

T2

A1 1

M7

A1 2 / B C

T8

A1 3

L2

A1 4 / W E

N2

BA0

N8

BA1

E2

DMU/DBIU

E7

DML/ DBI L

K7

CK_t

K8

CK_c

K2

CKE

K3

ODT

L7

CS

L8

RAS

M8

CAS

A7

DQSU _c

B7

DQSU _t

F3

DQSL_c

G3

DQSL_t

P1

RESET

F9

ZQ

L3

AC T

M2

BG0

N9

TEN

P9

AL E R T

T3

PAR

T7

NC

B1

VP P

R9

VP P

96-B AL L

SDRAM DDR4

K4AAG165WB-MCRC C38

@

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VD D Q VD D Q VD D Q VD D Q VD D Q VD D Q VD D Q VD D Q VD D Q VD D Q

VS S Q VS S Q VS S Q VS S Q VS S Q VS S Q VS S Q VS S Q VS S Q VS S Q

DDR_A_D18

G2

DQL0

DDR_A_D19

F7

DQL1

DDR_A_D21

H3

DQL2

DDR_A_D22

H7

DQL3

DDR_A_D16

H2

DQL4

DDR_A_D23

H8

DQL5

DDR_A_D20

J3

DQL6

DDR_A_D17

J7

DQL7

DDR_A_D24

A3

DDR_A_D26

B8

DDR_A_D25

C3

DDR_A_D27

C7

DDR_A_D29

C2

DDR_A_D30

C8

DDR_A_D28

D3

DDR_A_D31

D7

B3

VD D

B9

VD D

D1

VD D

G7

VD D

J1

VD D

J9

VD D

L1

VD D

L9

VD D

R1

VD D

T9

VD D

A1 A9 C1 D9 F2 F8 G1 G9 J2 J8

B2

VS S

E1

VS S

E9

VS S

G8

VS S

K1

VS S

K9

VS S

M9

VS S

N1

VS S

T1

VS S

A2 A8 C9 D2 D8 E3 E8 F1 H1 H9

+1.2V

RD2 240_0402_1%DD P@

1 2

DDR_A_BG1_R DDR_A_BG1_R

CD1

MD@

.047U_0402_16V7K

+2.5V

1

2

+1.2V+1.2V+1.2V

RU3 240_0402_1%MD@

1 2

DDR_A _MA 0 DDR_A_MA1 DDR_A_MA2 DDR_A _MA 3 DDR_A _MA 4 DDR_A _MA 5 DDR_A _MA 6 DDR_A _MA 7 DDR_A _MA 8 DDR_A _MA 9 DDR_A _MA 10 DDR_A _MA 11 DDR_A _MA 12 DDR_A _MA 13 DDR_A _MA 14

DDR_A_BA0 DDR_A_BA1

DDR_A _CL K0 DDR_A_CLK#0 DDR_A_CKE0

DDR_A _OD T0 DDR_A_CS#0

DDR_A_MA15

DDR_A_DQS#5 DDR_A _DQ S5 DDR_A_DQS#4 DDR_A _DQ S4

MEMRST#MEMRST#

DDR_A _ACT # DDR_A _BG 0

DDR_A_ALERT# DDR_A_PARITY

U3

M1

VR E F C A

P3

A0

P7

A1

R3

A2

N7

A3

N3

A4

P8

A5

P2

A6

R8

A7

R2

A8

R7

A9

M3

A1 0 / A P

T2

A1 1

M7

A1 2 / B C

T8

A1 3

L2

A1 4 / W E

N2

BA0

N8

BA1

E2

DMU/D BIU

E7

DML/ DBIL

K7

CK_t

K8

CK_c

K2

CKE

K3

ODT

L7

CS

L8

RAS

M8

CAS

A7

DQSU _c

B7

DQSU _t

F3

DQSL_c

G3

DQSL_t

P1

RESET

F9

ZQ

L3

AC T

M2

BG0

N9

TEN

P9

AL E R T

T3

PAR

T7

NC

B1

VP P

R9

VP P

96-B ALL

SDRAM DDR4

K4AAG165WB-MCRC C38

@

+DDR_VREF_CA

DDR_A_D35

G2

DQL0

DDR_A_D33

F7

DQL1

DDR_A_D34

H3

DQL2

DDR_A_D39

H7

DQL3

DDR_A_D37

H2

DQL4

DDR_A_D38

H8

DQL5

DDR_A_D36

J3

DQL6

DDR_A_D32

J7

DQL7

DDR_A_D40

A3

DQU0

DDR_A_D44

B8

DQU1

DDR_A_D45

C3

DQU2

DDR_A_D46

C7

DQU3

DDR_A_D41

C2

DQU4

DDR_A_D42

C8

DQU5

DDR_A_D43

D3

DQU6

DDR_A_D47

D7

DQU7

B3

VDD

B9

VDD

D1

VDD

G7

VDD

J1

VDD

J9

VDD

L1

VDD

L9

VDD

R1

VDD

T9

VDD

A1

VDD Q

A9

VDD Q

C1

VDD Q

D9

VDD Q

F2

VDD Q

F8

VDD Q

G1

VDD Q

G9

VDD Q

J2

VDD Q

J8

VDD Q

B2

VS S

E1

VS S

E9

VS S

G8

VS S

K1

VS S

K9

VS S

M9

VS S

N1

VS S

T1

VS S

A2

VS S Q

A8

VS S Q

C9

VS S Q

D2

VS S Q

D8

VS S Q

E3

VS S Q

E8

VS S Q

F1

VS S Q

H1

VS S Q

H9

VS S Q

+1.2V

RD3 240_0402_1%DD P@

1 2

CD4

.047U_0402_16V7K

DDR_A_MA0

1

DDR_A_MA1

@

DDR_A_MA2 DDR_A_MA3 DDR_A_MA4

2

DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14

DDR_A_BA0 DDR_A_BA1

+1.2V

DDR_A_CLK0 DDR_A_CLK#0 DDR_A_CKE0

DDR_A_ODT0 DDR_A_CS#0 DDR_A_MA16 DDR_A_MA15

DDR_A_DQS#7 DDR_A_DQS7 DDR_A_DQS#6 DDR_A_DQS6

MEMRST#

RU4 240_0402_1%MD@

1 2

DDR_A_ACT# DDR_A_BG0

DDR_A_ALERT# DDR_A_PARITY

+2.5V

U4

M1

VRE F C A

P3

A0

P7

A1

R3

A2

N7

A3

N3

A4

P8

A5

P2

A6

R8

A7

R2

A8

R7

A9

M3

A10 / AP

T2

A11

M7

A12 / B C

T8

A13

L2

A14 / W E

N2

BA0

N8

BA1

E2

DMU/D BIU

E7

DML/D BIL

K7

CK_t

K8

CK_c

K2

CKE

K3

ODT

L7

CS

L8

RAS

M8

CAS

A7

DQSU_ c

B7

DQSU_ t

F3

DQSL _c

G3

DQSL _t

P1

RESE T

F9

ZQ

L3

ACT

M2

BG0

N9

TEN

P9

ALE RT

T3

PAR

T7

NC

B1

VP P

R9

VP P

96-BA LL

SDRAM DDR4

K4AAG165WB-MCRCC38

@

DDR_A_D50

G2

DQL0

DDR_A_D51

F7

DQL1

DDR_A_D48

H3

DQL2

DDR_A_D55

H7

DQL3

DDR_A_D53

H2

DQL4

DDR_A_D54

H8

DQL5

DDR_A_D49

J3

DQL6

DDR_A_D52

J7

DQL7

DDR_A_D56

A3

DQU0

DDR_A_D63

B8

DQU1

DDR_A_D60

C3

DQU2

DDR_A_D62

C7

DQU3

DDR_A_D57

C2

DQU4

DDR_A_D58

C8

DQU5

DDR_ A_D 61

D3

DQU6

DDR_ A_D 59

D7

DQU7

B3

VDD

B9

VDD

D1

VDD

G7

VDD

J1

VDD

J9

VDD

L1

VDD

L9

VDD

R1

VDD

T9

VDD

A1

VDD Q

A9

VDD Q

C1

VDD Q

D9

VDD Q

F2

VDD Q

F8

VDD Q

G1

VDD Q

G9

VDD Q

J2

VDD Q

J8

VDD Q

B2

VS S

E1

VS S

E9

VS S

G8

VS S

K1

VS S

K9

VS S

M9

VS S

N1

VS S

T1

VS S

A2

VS S Q

A8

VS S Q

C9

VS S Q

D2

VS S Q

D8

VS S Q

E3

VS S Q

E8

VS S Q

F1

VS S Q

H1

VS S Q

H9

VS S Q

+1.2V

Replace with240 Ohmto SupportDDP@

RD4 240_0402_1%DDP@

1 2

DDR_A_BG1_R

DDR_A_MA[0..16]<7,19>

DDR_A_DQS#[0..7]<7>

DDR_A_DQS[0..7]<7>

DDR_A_D[0..63]<7>

B B

CLOCK TERMINATION

DDR_A_CLK0

RU5 33_0402_1%MD@ RU6 33_0402_1%MD@

RD11 49.9_0402_1%MD@

5

1 2 1 2

1

@

CD5 3300P_0402_50V7K

2

12

RD14 0_0402_5%@

1 2

+1.2V

MEMRST#

1

CD7

@

100P_0402_50V8J

2

DDR_A_CLK#0

DDR_A_CLK0

DDR_A_CLK#0

DDR_A_ALERT#

A A

DDR_DRAMRST#<7,20>

CU25

MD@

1 2

0.01U_0402_16V7K

+0.6VS

4

Co-lay for SDP / DDP Memory DIE

DDR_A_BG1_R

+0.6V_A_VREFCA<7>

RD7 0_0402_5%DDP@

1 2

RD9 0_0402_5%SDP@

1 2

1

CD6

0.022U_0402_16V7K

2

12

RD15

24.9_0402_1%

RD13

2.7_0402_1%

MD@

ForSDP@

MD@

12

DDR_A_BG1 <7>

+1.2V

RD12

1.8K_0402_1%

1 2

RD16

1.8K_0402_1%

1 2

RD1 SDP@ 0_0402_5%

RD2 SDP@ 0_0402_5%

RD3 SDP@ 0_0402_5%

RD4 SDP@ 0_0402_5%

MD@

+DDR_VREF_CA

MD@

3

On Board RAM - Data Mapping

DQ

U4

DQL0

D13

DQL1

D12

DQL2

D11

DQL 3

D8

DQL4

D10

DQL 5

D9

DQL6

D14

DQL7

D15

D6

DQU0

DQU1

D1

D7

DQU2

D5

DQU3

D3

DQU4

DQU5

D4

D2

DQU6

D0

DQU7

Security Classification

Secu rit y Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS TH E PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS TH E PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION.T HI S SHEET MAY N O T BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION.T HI S SHEET MAY N O T BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION.T HI S SHEET MAY N O T BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENTEXCEPT AS AUTHORIZE D BY COMPAL ELECTRONICS, INC. NEITHER T HI S SHEET N OR T HE INFORMATION IT CONTAINS

DEPARTMENTEXCEPT AS AUTHORIZE D BY COMPAL ELECTRONICS, INC. NEITHER T HI S SHEET N OR T HE INFORMATION IT CONTAINS

DEPARTMENTEXCEPT AS AUTHORIZE D BY COMPAL ELECTRONICS, INC. NEITHER T HI S SHEET N OR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCL OSED TO ANY THIR D PA RT Y WITHOUTPRIOR WRITTENC ONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCL OSED TO ANY THIR D PA RT Y WITHOUTPRIOR WRITTENC ONSENT OF COMPAL ELECTRONICS, INC.

2018/09/21 2019/09/21

2

DQ

U2

DQL0

D29

DQL1

D25

DQL 2

D27

DQL3

D24

DQL4

D30

DQL5

D28

DQL 6

D31

DQL7

D26

DQU0

D22

DQU1

D17

DQU2

D23

DQU3

D20

DQU4

D19

DQU5

D16

DQU6

D18

DQU7

D21

Compal Secret Data

Deciphered Date

DQL0

DQL1

DQL2

DQL3

DQL4

DQL5

DQL6

DQL7

DQU0

DQU1

DQU2

DQU3

DQU4

DQU5

DQU6

DQU7

DQ

D43

D40

D42

D41

D47

D45

D46

D44

D38

D37

D35

D32

D33

D36

D39

D34

DQ

U1U 3

DQL0

D60

DQL1

D61

DQL2

D62

DQL3

D57

DQL4

D58

DQL5

D56

DQL6

D59

DQL7

D63

DQU0

D50

DQU1

D52

DQU2

D51

DQU3

D48

DQU4

D54

DQU5

D53

DQU6

D55

DQU7

D49

Ti t l e

DDR4 ON BOARD CHIPS

Document Nu mber Rev

Size

Cust om

Date: Sheet of

1

LA-H101P

0.A0.A0.A

18 51Thursday, September 20, 2018

5

4

3

2

1

D D

C C

B B

+1.2V

1U_0201_6.3V6M

CU2

CU1

12

@

12

MD@

1U_0201_6.3V6M

12

MD@CU3

1U_0201_6.3V6M

CU4

CU5

CU6

12

MD@

CU7

12

MD@

1U_0201_6.3V6M

CD34

12

MD@

4 as near each on board RA M device as possible

CD43 10U_0402_6.3V6M

CD44 10U_0402_6.3V6M

CD45 10U_0402_6.3V6M

CD46 10U_0402_6.3V6M

CD47 10U_0402_6.3V6M

1

2

MD@

+2.5V +0.6VS

1U_0201_6.3V6M

CU9

12

@

1U_0201_6.3V6M

CU10

12

MD@

1U_0201_6.3V6M

CU11

CU12

12

MD@

1U_0201_6.3V6M

CU13

12

MD@

1U_0201_6.3V6M

CU14

12

@

1U_0201_6.3V6M

CU15

CU16

12

MD@

2 as near each on board RA M device as possible

1U_0201_6.3V6M

CD36

CD35

12

MD@

@

1U_0201_6.3V6M

CD38

CD37

12

MD@

1U_0201_6.3V6M

CU17

12

MD@

1U_0201_6.3V6M

CD40

CD39

MD@

1U_0201_6.3V6M

CU18

@

12

MD@

1U_0201_6.3V6M

CU19

12

@

1U_0201_6.3V6M

CD41

CD42

12

MD@

DDR_A_PARITY<7,18>

1U_0201_6.3V6M

CU20

CU21

12

MD@

1U_0201_6.3V6M

CU22

12

MD@

1U_0201_6.3V6M

CU23

CU24

12

MD@

@

DDR_A_MA[0..16]<7,18>

+0.6VS

DDR_A_MA9 DDR_A_MA2 DDR_A_MA4

DDR_A_BA1<7,18>

DDR_A_BG0<7,18>

DDR_A_ACT#<7,18>

DDR_A_CS#0<7,18>

DDR_A_CKE0<7,18>

DDR_A_ODT0<7,18>

DDR_A_BA0<7,18>

DDR_A_BA1

DDR_A_MA10 DDR_A_MA3 DDR_A_MA12 DDR_A_BG0

DDR_A_MA16 DDR_A_ACT# DDR_A_CS#0 DDR_A_MA15

DDR_A_CKE0 DDR_A_ODT0 DDR_A_MA14

DDR_A_MA13 DDR_A_MA8 DDR_A_PARITY DDR_A_MA11

DDR_A_MA1 DDR_A_BA0 DDR_A_MA7

1 2

RD29 36_0201_5%MD@

1 2

RD30 36_0201_5%MD@

1 2

RD31 36_0201_5%MD@

1 2

RD32 36_0201_5%MD@

1 2

RD33 36_0201_5%MD@

1 2

RD34 36_0201_5%MD@

1 2

RD35 36_0201_5%MD@

1 2

RD36 36_0201_5%MD@

1 2

RD37 36_0201_5%MD@

1 2

RD38 36_0201_5%MD@

1 2

RD39 36_0201_5%MD@

1 2

RD40 36_0201_5%MD@

1 2

RD41 36_0201_5%MD@

1 2

RD42 36_0201_5%MD@

1 2

RD43 36_0201_5%MD@

1 2

RD44 36_0201_5%MD@

1 2

RD45 36_0201_5%MD@

1 2

RD46 36_0201_5%MD@

1 2

RD47 36_0201_5%MD@

1 2

RD48 36_0201_5%MD@

1 2

RD49 36_0201_5%MD@

1 2

RD50 36_0201_5%MD@

2 as near each on board RA M device as possible

DDR_A_MA5 DDR_A_MA6 DDR_A_MA0

1 2

RD51 36_0201_5%MD@

1 2

RD52 36_0201_5%MD@

1 2

RD53 36_0201_5%MD@

10U_0402_6.3V6M

CD48

1

@

2

A A

5

10U_0402_6.3V6M

CD49

@

CD50

1

@

2

10U_0402_6.3V6M

CD51

1

2

CD52

1

MD@

2

4

10U_0402_6.3V6M

CD54

CD53

1

MD@

2

@

LA-H101P

Security Classificat ion

Is s u ed Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I N C . AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I N C . AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETEN T D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETEN T D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETEN T D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, IN C . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, IN C . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, IN C . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED B Y OR DISCLOSED TO AN Y THIRD P A R T Y WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C .

MAY BE USED B Y OR DISCLOSED TO AN Y THIRD P A R T Y WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C .

3

2018/09/21 2019/09/21

Compal S ecret Data

Deciphered Date

2

DDR_A_BG1_R<18>

DDR_A_BG1_R

Tit le

DDR4 MISC

Size Document Number Rev

Custom

Date: Sheet

1 2

RD54 36_0201_5%DDP@

LA-H101PLA-H101PLA-H101P

1

19 51Thursday, September 20, 2018

0.A0.A0.A

of

A

<7>

DDR_B_DQS#[0..7]

DDR_B_D[0..63]<7>

DDR_B_DQS[0..7]<7>

DDR_B_MA[0..16]

<7>

DDR_B_BA0

<7>

DDR_B_BA1

<7>

DDR_B_BG0<7> DDR_B_BG1

<7>

DDR_B_CLK0

1 1

2 2

<7> <7>

DDR_B_CLK#0 DDR_B_CLK1

<7>

DDR_B_CLK#1

<7>

DDR_B_CKE0<7>

DDR_B_CKE1<7>

DDR_B_CS#0<7>

DDR_B_CS#1<7>

SOC_SMBDATA<8> SOC_SMBCLK<8>

DDR_B_ODT0<7>

DDR_B_ODT1<7>

Layout Note: Place near JDIMM1

+1.2V

1U_0201_6.3V6M

12

CD10

CD9

4 as near side of the DIMM close to VDD pins

+1.2V

@

CD18 10U_0402_6.3V6M

CD20 10U_0402_6.3V6M

CD19 10U_0402_6.3V6M

1

2

DDR_B_BA0 DDR_B_BA1 DDR_B_BG0 DDR_B_BG1

DDR_B_CLK0 DDR_B_CLK#0 DDR_B_CLK1 DDR_B_CLK#1

DDR_B_CKE0 DDR_B_CKE1 DDR_B_CS#0 DDR_B_CS#1

SOC_SMBDATA SOC_SMBCLK

DDR_B_ODT0 DDR_B_ODT1

Note: Check voltage tolerance of VREF_DQ at the DIMM socket

1U_0201_6.3V6M

12

CD11

CD12

CD21 10U_0402_6.3V6M

CD22 10U_0402_6.3V6M

1

2

1U_0201_6.3V6M

12

CD13

@

CD24 10U_0402_6.3V6M

CD23 10U_0402_6.3V6M

1

2

1U_0201_6.3V6M

12

CD14

CD15

CD16

CD25 10U_0402_6.3V6M

1

2

Place these caps on the V TT plane close to DIMM

+0.6VS

@

1U_0201_6.3V6M

CD26

C1

2.2U_0402_6.3V6M

1U_0201_6.3V6M

12

CD27

1

CD32

0.1U_0201_10V6K

2

12

3 3

1

2

1U_0201_6.3V6M

12

CD28

10U_0402_6.3V6M

CD31

CD30

1

CD29

@

2

+2.5V+3VS

1

C2

@

2

12

CD33 1U_0201_6.3V6M

close to DIMM

4 4

+2.5V

B

C

D

E

Standard Type

+1.2V +1.2V

DDR_B_D14 DDR_B_D15

DDR_B_D11

DDR_B_DQS#1 DDR_B_DQS1

DDR_B_D13

DDR_B_D8

DDR_B_D0

DDR_B_D7

DDR_B_D4

DDR_B_D21

DDR_B_D17

DDR_B_DQS#2 DDR_B_DQS2

DDR_B_D23

DDR_B_D22

DDR_B_D29

DDR_B_D24

DDR_B_D30

DDR_B_D26

DDR_B_CKE0 DDR_B_CKE1

DDR_B_BG1 DDR_B_BG0

DDR_B_MA9

DDR_B_MA8 DDR_B_MA6

DDR_B_MA1

DDR_B_CLK0

DDR_B_PARITY<7>

DDR_B_CLK#0

DDR_B_BA1

DDR_B_CS#0 DDR_B_MA14

DDR_B_ODT0 DDR_B_CS#1

DDR_B_ODT1

DDR_B_D33

DDR_B_D32

DDR_B_DQS#4 DDR_B_DQS4

DDR_B_D36

DDR_B_D35

DDR_B_D45

DDR_B_D44

DDR_B_D47

DDR_B_D46

DDR_B_D52

DDR_B_DQS#6 DDR_B_DQS6

DDR_B_D55

DDR_B_D50

DDR_B_D61

DDR_B_D56

DDR_B_D59

DDR_B_D58

+3VS

JDIMM1

1

VSS1

3

DQ5

5

VSS3

7

DQ1

9

1

VSS5

DQS0_c1

13

DQS0_t

15

VSS8

17

DQ7

19

VSS10

21

DQ3

23

VSS12

25

DQ13

27

VSS14

29

DQ9

31

VSS16

33

DM1_n/DBI_n

35

VSS17

37

DQ15

39

VSS19

41

DQ10

43

VSS21

45

DQ21

47

VSS23

49

DQ17

51

VSS25 DQS2_c53DM2_n/DBI2_n

55

DQS2_t

57

VSS28

59

DQ23

61

VSS30

63

DQ19

65

VSS32

67

DQ29

69

VSS34

71

DQ25

73

VSS36 DM3_n/DBI3_n75DQS3_t

77

VSS37

79

DQ30

81

VSS39

83

DQ26

85

VSS41

87

CB5/NC

89

VSS43

91

CB1/NC

93

VSS45 DQS8_c95DM8_n/DBI_n/NC

97

DQS8_t

99

VSS48

101

CB2/NC

103

VSS50

105

CB3/NC

107

VSS52

109

CKE0

111

VDD1

113

BG1

115

BG0

117

VDD3

119

A12

121

A9

123

VDD5

125

A8

127

A6

129

VDD7

131

A3

133

A1

135

VDD9

137

CK0_t

139

CK0_c

141

VDD11

143

PARITY

145

BA1

147

VDD13

149

CS0_n

151

WE_n/A14

153

VDD15

155

ODT0

157

CS1_n

159

VDD17

161

ODT1

163

VDD19

165

C1, CS3_n,NC

167

VSS53

169

DQ37

171

VSS55

173

DQ33

175

VSS57

177

DQS4_c

179

DQS4_t

181

VSS60

183

DQ38

185

VSS62

187

DQ34

189

VSS64

191

DQ44

193

VSS66

195

DQ40

197

VSS68

199

DM5_n/DBI5_n

201

VSS69

203

DQ46

205

VSS71

207

DQ42

209

VSS73

211

DQ52

213

VSS75

215

DQ49

217

VSS77

219

DQS6_c

221

DQS6_t

223

VSS80

225

DQ55

227

VSS82

229

DQ51

231

VSS84

233

DQ61

235

VSS86

237

DQ56

239

VSS88

241

DM7_n/DBI7_n

243

VSS89

245

DQ62

247

VSS91

249

DQ58

251

VSS93

253

SCL

255

VDDSPD

257

VPP1

259

VPP2

261

GND1

LOTES_ADDR0205-P002A

ME@

SP07001HW00

DM0_n/DBI0_n

VSS11

DQ12

VSS13

VSS15

DQS1_c

DQS1_t

VSS18

DQ14

VSS20

DQ11

VSS22

DQ20

VSS24

DQ16

VSS26

VSS27

DQ22

VSS29

DQ18

VSS31

DQ28

VSS33

DQ24

VSS35

DQS3_c

VSS38

DQ31

VSS40

DQ27

VSS42

CB4/NC

VSS44

CB0/NC

VSS46

VSS47

CB6/NC

VSS49

CB7/NC

VSS51

RESET_n

CKE1 VDD2

ACT_n

ALERT_n

VDD4

VDD6

VDD8

EVENT_n/ NF

VDD10

CK1_t/NF

CK1_c/NF

VDD12

A10/AP

VDD14

RAS_n/A16

VDD16

CAS_n/A15

VDD18

C0/CS2_n/NC

VREFCA

VSS54

DQ36

VSS56

DQ32

VSS58

DM4_n/DBI4_n

VSS59

DQ39

VSS61

DQ35

VSS63

DQ45

VSS65

DQ41

VSS67

DQS5_c

DQS5_t

VSS70

DQ47

VSS72

DQ43

VSS74

DQ53

VSS76

DQ48

VSS78

DM6_n/DBI6_n

VSS79

DQ54

VSS81

DQ50

VSS83

DQ60

VSS85

DQ57

VSS87

DQS7_c

DQS7_t

VSS90

DQ63

VSS92

DQ59

VSS94

GND2

VSS2

VSS4

VSS6

VSS7

VSS9

2 4

DQ4

6 8

DQ0

10 12 14 16

DQ6

18 20

DQ2

22 24 26 28

DQ8

30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120

A11

122

A7

124 126

A5

128

A4

130 132

A2

134 136 138 140 142 144

A0

146 148 150

BA0

152 154 156 158

A13

160 162 164 166

SA2

168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 206 208 210 212 214 216 218 220 222 224 226 228 230 232 234 236 238 240 242 244 246 248 250 252 254

SDA

256

SA0

258

VTT

260

SA1

262

DDR_B_D10

DDR_B_D9

DDR_B_D12

DDR_B_D2

DDR_B_D3

DDR_B_DQS#0 DDR_B_DQS0

DDR_B_D5DDR_B_D6

DDR_B_D1

DDR_B_D20

DDR_B_D16

DDR_B_D19

DDR_B_D18

DDR_B_D28

DDR_B_D25

DDR_B_DQS#3 DDR_B_DQS3

DDR_B_D31

DDR_B_D27

DDR_DRAMRST#_R

DDR_B_MA11DDR_B_MA12 DDR_B_MA7

DDR_B_MA5 DDR_B_MA4

DDR_B_MA2DDR_B_MA3

DDR_B_CLK1 DDR_B_CLK#1

DDR_B_MA0

DDR_B_MA10

DDR_B_BA0 DDR_B_MA16

DDR_B_MA15 DDR_B_MA13

DDR_B_SA2

DDR_B_D38

DDR_B_D39

DDR_B_D37

DDR_B_D34

DDR_B_D41

DDR_B_D40

DDR_B_DQS#5 DDR_B_DQS5

DDR_B_D43

DDR_B_D42

DDR_B_D53

DDR_B_D48DDR_ B_D49

DDR_B_D54

DDR_B_D51

DDR_B_D60

DDR_B_D57

DDR_B_DQS#7 DDR_B_DQS7

DDR_B_D63

DDR_B_D62

SOC_SMBDATASOC_SMBCLK DDR_B_SA0

DDR_B_SA1

DDR_B_ACT# <7>

DDR_B_ALERT# <7>

+DIMM_VREF_DQ

+0.6VS

1

CD17 100P_0402_50V8J

ESD@

2

+0.6V_B_VREFDQ<7>

JDIMM1 ADDRESS (PLACE CLOSE TO DIMM)

2-3A to 1 DIMMs/channel

20mi l

1

CD8

0.022U_0402_16V7K

DDR_DRAMRST#_R

DDR_B_SA2

2

12

RD19

24.9_0402_1%

1 2

RD24 0_0402_5%@

RD18 2_0402_1%

+1.2V

+DIMM_VREF_DQ

RD17 1K_0402_1%

1 2

12

RD20 1K_0402_1%

1 2

+1.2V

12

RD23 470_0402_1%

@

DDR_DRAMRST# <7,18>

+3VS

RD25

@

0_0402_5%

1 2

DDR_B_SA1

12

@

DDR_B_SA0

RD28 0_0402_5%

Security Cl assificat ion

Issued Date

THISSHEET OF ENGINEERINGDRAWING IS THE PROPRIETARYPROPERTYOF COMPALELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THISSHEET OF ENGINEERINGDRAWING IS THE PROPRIETARYPROPERTYOF COMPALELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRETINFORMATION. THISSHEET MAYNOT BE TRANSFERED FROM THECUSTODY OF THECOMPET ENT DIVISION OF R&D

AND TRADE SECRETINFORMATION. THISSHEET MAYNOT BE TRANSFERED FROM THECUSTODY OF THECOMPET ENT DIVISION OF R&D

AND TRADE SECRETINFORMATION. THISSHEET MAYNOT BE TRANSFERED FROM THECUSTODY OF THECOMPET ENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAYBE USED BY OR DISCLOSED TO ANY THIRD P A R T Y WITHOUT PRIORWRITTEN CONSENT OF COMPALELECTRONICS, INC.

MAYBE USED BY OR DISCLOSED TO ANY THIRD P A R T Y WITHOUT PRIORWRITTEN CONSENT OF COMPALELECTRONICS, INC.

A

B

C

MAYBE USED BY OR DISCLOSED TO ANY THIRD P A R T Y WITHOUT PRIORWRITTEN CONSENT OF COMPALELECTRONICS, INC.

2018/09/21 2019/09/21

Compal Secret Data

Deciph ered Date

D

Compal Electronics, Inc.

Ti t l e

Custom

Date: Sheet of

Size

DDR4_DIMM

Document Number

LA-H101P

20 51Thursday, September 20, 2018

E

20 51Thursday, September 20, 2018

Rev

0.A0.A0.A

1

PLT_RST_VGA_MON#

CLKREQ_PEG#0_R

PCIE CLK

A A

PCIE X4 Bus

B B

Reset Control

(From PC H)

C C

PCI_RST#[10,30,31,33,36]

[11] D GPU_HOLD_RST#

[24] PL T_RST_VGA_HOLD#

(From GPU)

CLK_ RE Q

DGPU_PWROK[25,26,50]

D D

[10] CLK_PEG_P0 [10] CLK_PEG_N0

[12] PC IE_CRX_DTX_P5 [12] PC IE_CRX_DTX_N5

[12] PCIE_CTX_C_DRX_P5 [12] PCIE_CTX_C_DRX_N5

[12] PC IE_CRX_DTX_P6 [12] PC IE_CRX_DTX_N6

[12] PCIE_CTX_C_DRX_P6 [12] PCIE_CTX_C_DRX_N6

[12] PC IE_CRX_DTX_P7 [12] PC IE_CRX_DTX_N7

[12] PCIE_CTX_C_DRX_P7 [12] PCIE_CTX_C_DRX_N7

[12] PC IE_CRX_DTX_P8 [12] PC IE_CRX_DTX_N8

[12] PCIE_CTX_C_DRX_P8 [12] PCIE_CTX_C_DRX_N8

CLKREQ_PEG#0_R

+1.8VGS_+3VGS_AON

1

2

1

+1.8VGS_+3VGS_AON

RV7

10K_0201_5%

DIS@

5

IN1

VCC

IN2

GND

3

2

0_0402_5%@RV6

12

PCIE_CRX_DTX_P5 PCIE_CRX_DTX_N5

PCIE_CTX_C_DRX_P5 PCIE_CTX_C_DRX_N5

PCIE_CRX_DTX_P6 PCIE_CRX_C_DTX_P6 PCIE_CRX_DTX_N6

PCIE_CTX_C_DRX_P6 PCIE_CTX_C_DRX_N6

PCIE_CRX_DTX_P7 PCIE_CRX_DTX_N7

PCIE_CTX_C_DRX_P7 PCIE_CTX_C_DRX_N7

PCIE_CRX_DTX_P8 PCIE_CRX_DTX_N8

PCIE_CTX_C_DRX_P8 PCIE_CTX_C_DRX_N8

UV6 MC74VHC1G08DFT 2G_SC70-5

4

OUT

DIS@

+1.8VGS_+3VGS

12

RV5 10K_0201_5%

DIS@

1U_0402_6.3V6K

CV29

1

@

2

RV10

QV150

DIS@

G

2

BSS138W-7-F_ SOT323-3

13

D

S

VGS(Max) : 1.5 V

2

1

0_0402_5%@

2

1 2

RV1 0_ 0402_5%

N17S@

2

1

2

1

CV6

2

1

CV7 CV8

CV9

+1.8VGS_+3VGS_AON

2

1

2

1

2

1

2

1

2

1

5

1

IN1

VCC

OUT

2

IN2

GND

N16S@

3

12

RV9 10K_0201_5%

@

0.22U_0402_6 .3V6KCV14 DIS@

0.22U_0402_6 .3V6KDIS@

0.22U_0402_6 .3V6KCV11 DIS@

0.22U_0402_6 .3V6KCV21 DIS@

0.22U_0402_6 .3V6KCV22 DIS@

UV7 MC74VHC1G08DFT 2G_SC70-5

PLT_RST_VGA#

4

PCIE_CRX_C_DTX_P5 PCIE_CRX_C_DTX_N5

PCIE_CRX_C_DTX_N6

PCIE_CRX_C_DTX_P7 PCIE_CRX_C_DTX_N7

PCIE_CRX_C_DTX_P8 PCIE_CRX_C_DTX_N8

PLT_RST_VGA_MON# [24]

12

RV2 10K_0201_5%

DIS@

CLKREQ_PEG#0 [10]

(To SOC)

PLT_RST_VGA#

Near U V1

UV1A

COMMON

1/14 PCI_EXPRESS

AB6

PEX_WAKE#

AC7

PEX_RST#

AC6

PEX_CLKREQ#

AE8

PEX_REFCLK

AD8

PEX_REFCLK#

AC9

PEX_TX0

AB9

PEX_TX0#

AG6

PEX_RX0

AG7

PEX_RX0#

AB10

PEX_TX1

AC10

PEX_TX1#

AF7

PEX_RX1

AE7

PEX_RX1#

AD11

PEX_TX2

AC11

PEX_TX2#

AE9

PEX_RX2

AF9

PEX_RX2#

AC12

PEX_TX3

AB12

PEX_TX3#

AG9

PEX_RX3

AG10

PEX_RX3#

AB13

PEX_TX4

AC13

PEX_TX4#

AF10

PEX_RX4

AE10

PEX_RX4#

AD14

PEX_TX5

AC14

PEX_TX5#

AE12

PEX_RX5

AF12

PEX_RX5#

AC15

PEX_TX6

AB15

PEX_TX6#

AG12

PEX_RX6

AG13

PEX_RX6#

AB16

PEX_TX7

AC16

PEX_TX7#

AF13

PEX_RX7

AE13

PEX_RX7#

AD17

PEX_TX8

AC17

PEX_TX8#

AE15

PEX_RX8

AF15

PEX_RX8#

AC18

PEX_TX9

AB18

PEX_TX9#

AG15

PEX_RX9

AG16

PEX_RX9#

AB19

PEX_TX10

AC19

PEX_TX10#

AF16

PEX_RX10

AE16

PEX_RX10#

AD20

PEX_TX11

AC20

PEX_TX11#

AE18

PEX_RX11

AF18

PEX_RX11#

AC21

PEX_TX12

AB21

PEX_TX12#

AG18

PEX_RX12

AG19

PEX_RX12#

AD23

PEX_TX13

AE23

PEX_TX13#

AF19

PEX_RX13

AE19

PEX_RX13#

AF24

PEX_TX14

AE24

PEX_TX14#

AE21

PEX_RX14

AF21

PEX_RX14#

AG24

PEX_TX15

AG25

PEX_TX15#

AG21

PEX_RX15

AG22

PEX_RX15#

N16S-GT-S-A2_BGA595

@

3

1 2

0_0402_5%

RV460

N16S@

VDD_SENSE_GPU

GND_SENSE_GPU

PEX_PLL_CLK_OUT PEX_PLL_CLK_OUT #

under GPU

1U_0402_6.3V6K

CV1

1

DIS@

2

Place under GPU

1U_0402_6.3V6K

CV15

1

DIS@

2

Place near BGA

1

2

4.7U_0402_6.3V6M CV2

1

N17S@

2

1U_0402_6.3V6K

CV16

1

N17S@

2

0.1U_0201_10V6K CV23

1

DIS@

2

AA22

PEX_IOVDD

AB23

PEX_IOVDD

AC24

PEX_IOVDD

AD25

PEX_IOVDD

AE26

PEX_IOVDD

AE27

PEX_IOVDD

AA10

PEX_IOVDDQ

AA12

PEX_IOVDDQ

AA13

PEX_IOVDDQ

AA16

PEX_IOVDDQ

AA18

PEX_IOVDDQ

AA19

PEX_IOVDDQ

AA20

PEX_IOVDDQ

AA21

PEX_IOVDDQ

AB22

PEX_IOVDDQ

AC23

PEX_IOVDDQ

AD24

PEX_IOVDDQ

AE25

PEX_IOVDDQ

AF26

PEX_IOVDDQ

AF27

PEX_IOVDDQ

NC FOR GF119

PEX_PLL_HVDD PEX_PLL_HVDD

PEX_SVDD_3V3

AA8 AA9

AB8

NC FOR GM108

F2

VDD_SENSE

F1

GND_SENSE

PEX_TSTCLK_OUT PEX_TSTCLK_OUT#

AF22 AE22

NC FOR GF117/GK208/GM108

PEX_PLLVDD_GPU

AA14

PEX_PLLVDD

AA15

PEX_PLLVDD

GPU_TESTMODE

AD9

TESTMODE

PEX_TERMP

AF25

PEX_TERMP

12

RV8

2.49K_0402_1 %

DIS@

4

Place near BGAPlace

4.7U_0402_6.3V6M

1

2

1U_0402_6.3V6K

CV734

CV733

1

N17S@

2

4.7U_0402_6.3V6M

CV24

CV25

1

DIS@

2

VDD_SENSE_GPU [50]

GND_SENSE_GPU [50]

1

200_0402_1 %@R V3

Place near BALL

GPU_TESTMODE [24]

CV12

DIS@

1

2

1 2

0_0805_5%

1 2

0_0805_5%

4.7U_0402_6.3V6M CV3

1

N17S@

2

10U_0402_6.3V6M

CV4

1

N17S@

2

Place near BGA

4.7U_0402_6.3V6M

RV445

N17S@

RV446

N16S@

CV17

DIS@

10U_0402_6.3V6M

CV19

CV18

1

N17S@

2

+1.8VGS_+3VGS

+1.8VGS_+3VGS_AON

To POWER

trace width: 16mils differential voltage sensing. differential signal routing.

0.1U_0201_10V6K

CV26

1

N16S@

2

5

+1.0VS_DGPU

1.0V

22U_0603_6.3V6M

CV5

CV13

1

N17S@

2

+1.0VS_DGPU

RV447

1.0V

22U_0603_6.3V6M

10U_0402_6.3V6M

CV20

CV10

1

DIS@

2

1U_0402_6.3V6K

CV27

1

N16S@

2

N16S@

1 2

0_0805_5%

+1.8VGS_+3VGS

RV458

N17S@

1 2

0_0805_5%

1.0V

4.7U_0402_6.3V6M CV28

1

Place near BGA

N16S@

2

RV4

N16S@

1 2

0_0805_5%

+1.0VS_DGPU

SSSeeecccuuurrriiitttyyy CCClllaaassssssiiifffiiicccaaatttiiiooonnn

IIIssssssuuueeeddd DDDaaattteee

TTTHHHIIISSS SSSHHHEEEEEETTT OOOFFF EEENNNGGGIIINNNEEEEEERRRIIINNNGGG DDDRRRAAAWWW IIINNNGGG IIISSS TTTHHHEEE PPPRRROOOPPPRRRIIIEEETTTAAARRRYYY PPPRRROOOPPPEEERRRTTTYYY OOOFFF CCCOOOMMMPPPAAALLL EEELLLEEECCCTTTRRROOONNNIIICCCSSS,,, IIINNNCCC... AAANNNDDD CCCOOONNNTTTAAAIIINNNSSS CCCOOONNNFFFIIIDDDEEENNNTTTIIIAAALLL AAANNNDDD TTTRRRAAADDDEEE SSSEEECCCRRREEETTT IIINNNFFFOOORRRMMMAAATTTIIIOOONNN... TTTHHHIIISSS SSSHHHEEEEEETTT MMMAAAYYY NNNOOOTTT BBBEEE TTTRRRAAANNNSSSFFF EEERRREEEDDD FFF RRROOOMMM TTTHHH EEE CCCUUUSSSTTTOOODDDYYY OOOFFF TTTHHHEEE CCCOOOMMMPPPEEETTTEEENNNTTT DDDIIIVVVIIISSSIIIOOONNN OOOFFF RRR&&&DDD DDDEEEPPPAAARRRTTTMMMEEENNNTTT EEEXXXCCCEEEPPPTTT AAASSS AAAUUUTTTHHHOOORRRIIIZZZEEEDDD BBBYYY CCCOOOMMMPPPAAALLL EEELLLEEECCCTTTRRROOONNNIIICCCSSS,,, IIINNNCCC... NNNEEEIIITTTHHHEEERRR TTTHHHIIISSS SSSHHHEEEEEETTT NNNOOORRR TTTHHHEEE IIINNNFFFOOORRRMMMAAATTTIIIOOONNN IIITTT CCCOOONNNTTTAAAIIINNNSSS

1

2

MMMAAAYYY BBBEEE UUUSSSEEEDDD BBBYYY OOORRR DDD IIISSSCCCLLLOOOSSSEEEDDD TTTOOO AAANNNYYY TTTHHH IIIRRRDDD PPPAAARRRTTTYYY WWWIIITTTHHHOOOUUUTTT PPPRRRIIIOOORRR WWWRRRIIITTTTTTEEENNN CCCOOONNNSSSEEENNNTTT OOOFFF CCCOOOMMMPPPAAALLL EEELLLEEECCCTTT RRROOONNNIIICCC SSS,,, IIINNNCCC...

3

222000111777///111000///222777 222000111999///000444///000999

CCCooommmpppaaalll SSSeeecrcrcr eeettt DDDaaatttaaa

DDDeeecicicippphhheeererereddd DaDaDatetete

TTTiiitttllleee

SSSiiizezeze DDDooocucucumememennnttt NNNuuumbmbmbeeerrr RRR eee vvv

4

DDDaaattteee::: SSShhheeeeee ttt ooofff

CCCooompmpmpaaalll EEEllleeeccctttrrrooonnniiicccsss,,, IIInnnccc...

NNNVVV(((111///555)))---PCPCPCIIIEEE

LA-H101PLA-H101PLA-H101P

5

222111 555333MMMooonnndddaaayyy ,,, OcOcOctttooobbb eeerrr 222222,,, 222000111 888

0.A0.A0.A

1

2

3

4

5

UV1K

COMMON

UV1G

COMMON

4/14 IFPAB

AA6

IFPAB_RSET

A A

V7

IFPAB_PLLVDD

W7

IFPAB_PLLVDD

W6

IFPA_IOVDD

Y6

IFPB_IOVDD

B B

IFPAB

N16S-GT-S-A2_BGA595

@

J7

K7

K6

C C

H6

J6

D D

IFPA/B

UV1J

COMMON

7/14 IFPEF

IFPEF_PLLVDD

IFPEF_RSET

IFPE

IFPE_IOVDD

IFPF_IOVDD

IFPF

N16S-GT-S-A2_BGA595

@

NC FOR GF117/GM108

1

NC FOR GF117/GK208/GM108

IFPA_TXC# IFPA_TXC

IFPA_TXD0# IFPA_TXD0

IFPA_TXD1# IFPA_TXD1

IFPA_TXD2# IFPA_TXD2

IFPA_TXD3# IFPA_TXD3

IFPB_TXC# IFPB_TXC

IFPB_TXD4#

NC FOR GF117/GM108

IFPB_TXD4

IFPB_TXD5# IFPB_TXD5

IFPB_TXD6# IFPB_TXD6

IFPB_TXD7# IFPB_TXD7

GF117

GPIO14

NC

IFPE/F

DVI-DL

I2CY_SDA I2CY_SCL

TXC TXC

TXD0 TXD0

TXD1

NC FOR GF117/GM108

TXD2 TXD2

HPD_E

DVI-DL

TXD3 TXD3

TXD4 TXD4

NC FOR GF117/GM108

TXD5 TXD5

AC4 AC3

Y3 Y4

AA2 AA3

AA1 AB1

AA5 AA4

AB4 AB5

AB2 AB3

AD2 AD3

AD1 AE1

AD5 AD4

B3

GF119/GK208

DVI-SL/H DMI

I2CY_SDA I2CY_SCL

TXC TXC

TXD0

TXD1TXD1

TXD1

TXD2 TXD2

NC FOR GK208

HPD_E

NC FOR GF117

GF119/GK208

DVI-SL/H DMI

I2CZ_SDA I2CZ_SCL

TXC TXC

TXD0 TXD0

TXD1 TXD1

TXD2 TXD2

NC FOR GK208

HPD_F

NC FOR GF117

3/14 DACA

W5

DACA_VDD

AE2

DACA_VREF

AF2

DACA_RSET

N16S-GT-S-A2_BGA595

@

DP

IFPE_AUX# IFPE_AUX

IFPE_L3# IFPE_L3

IFPE_L2# IFPE_L2

IFPE_L1# IFPE_L1

IFPE_L0# IFPE_L0

GPIO18

DP

IFPF_AUX# IFPF_AUX

IFPF_L3# IFPF_L3

IFPF_L2# IFPF_L2

IFPF_L1# IFPF_L1

IFPF_L0# IFPF_L0

GPIO19

J3 J2

J1 K1

K3 K2

M3 M2

M1 N1

C2

H4 H3

J5 J4

K5 K4

L4 L3

M5 M4

F7

DAC_A

GF117/GM108 GF117

NC

TSEN_VREF

NC

+1.8VGS_+3VGS

+1.0VS_DGPU

2

GM108/GK208

I2CA_SCL

NC

I2CA_SDA

NC

DACA_HSYNC

NC

DACA_VSYNC

NC

DACA_RED

NC

DACA_GREEN

NC

DACA_BLUE

NC

GM108

GK208

GF117

RV448

N17S@

1 2

0_0805_5%

N16S@

1 2

LV1 HCB1005KF-30 0T25_2P

PLLVDD

+1.0VS_DGPU

RV457

N17S@

1 2

0_0805_5%

RV456

N16S@

1 2

0_0805_5%

UV1H

COMMON

B7 A7

AE3 AE4

Note: IFPC/D/E/F interface are XVDDs pin for N17S GPU, and connect them to NVVDD power for improving NVVDD power rail routing

AG3

T6

M7 N7

5/14 IFPC

IFPC_RSET

IFPC_PLLVDD IFPC_PLLVDD

AF4

AF3

P6

IFPC_IOVDD

N16S-GT-S-A2_BGA595

@

UV1I

COMMON

6/14 IFPD

U6

IFPD_RSET

T7

IFPD_PLLVDD

R7

IFPD_PLLVDD

IFPD

GPU_PLLVDD

0.1U_0201_10V K X5R

Place near balls

Place near ballsPlace near BGA

10U_0402_6.3V6M

CV34

1

N16S@

2

IIIssssssuuueeeddd DDDaaattteee

0.1U_0201_10V K X5R

CV35

1

DIS@

2

22U_0603_6.3V6M

CV33

CV32

1

N16S@

2

SSSeeecccuuurrriiitttyyy CCClllaaassssssiiifffiiicccaaatttiiiooonnn

TTTHHHIIISSS SSSHHHEEEEEETTT OOOFFF EEENNNGGGIIINNNEEEEEERRRIIINNNGGG DDDRRRAAAWWW IIINNNGGG IIISSS TTTHHHEEE PPPRRROOOPPPRRRIIIEEETTTAAARRRYYY PPPRRROOOPPPEEERRRTTTYYY OOOFFF CCCOOOMMMPPPAAALLL EEELLLEEECCCTTTRRROOONNNIIICCCSSS,,, IIINNNCCC... AAANNNDDD CCCOOONNNTTTAAAIIINNNSSS CCCOOONNNFFFIIIDDDEEENNNTTTIIIAAALLL AAANNNDDD TTTRRRAAADDDEEE SSSEEECCCRRREEETTT IIINNNFFFOOORRRMMMAAATTTIIIOOONNN... TTTHHHIIISSS SSSHHHEEEEEETTT MMMAAAYYY NNNOOOTTT BBBEEE TTTRRRAAANNNSSSFFF EEERRREEEDDD FFF RRROOOMMM TTTHHH EEE CCCUUUSSSTTTOOODDDYYY OOOFFF TTTHHHEEE CCCOOOMMMPPPEEETTTEEENNNTTT DDDIIIVVVIIISSSIIIOOONNN OOOFFF RRR&&&DDD DDDEEEPPPAAARRRTTTMMMEEENNNTTT EEEXXXCCCEEEPPPTTT AAASSS AAAUUUTTTHHHOOORRRIIIZZZEEEDDD BBBYYY CCCOOOMMMPPPAAALLL EEELLLEEECCCTTTRRROOONNNIIICCCSSS,,, IIINNNCCC... NNNEEEIIITTTHHHEEERRR TTTHHHIIISSS SSSHHHEEEEEETTT NNNOOORRR TTTHHHEEE IIINNNFFFOOORRRMMMAAATTTIIIOOONNN IIITTT CCCOOONNNTTTAAAIIINNNSSS MMMAAAYYY BBBEEE UUUSSSEEEDDD BBBYYY OOORRR DDD IIISSSCCCLLLOOOSSSEEEDDD TTTOOO AAANNNYYY TTTHHH IIIRRRDDD PPPAAARRRTTTYYY WWWIIITTTHHHOOOUUUTTT PPPRRRIIIOOORRR WWWRRRIIITTTTTTEEENNN CCCOOONNNSSSEEENNNTTT OOOFFF CCCOOOMMMPPPAAALLL EEELLLEEECCCTTT RRROOONNNIIICCC SSS,,, IIINNNCCC...

3

22U_0603_6.3V6M

CV31

CV30

1

DIS@

N16S@

2

VID_PLLVDD

0.1U_0201_10V K X5R

CV36

1

RV12

DIS@

10K_0402_1%

DIS@

2

12

90-OHM DIFF Impedance for XTALIN & XTALOUT.

UV1M

COMMON

9/14 XTAL_PLL

L6

PLLVDD

M6

SP_PLLVDD

N6

VID_PLLVDD

GF119/GK208

A10

XTALSSIN

C11

XTALIN

N16S-GT-S-A2_BGA595

@

R6

IFPD_IOVDD

N16S-GT-S-A2_BGA595

@

NC

GF117/GM108

1

CV37

DIS@

18P_0402_50 V8J

2

222000111777///111000///222777 222000111999///000444///000999

CCCooommmpppaaalll SSSeeecrcrcr eeettt DDDaaatttaaa

DDDeeecicicippphhheeererereddd DaDaDatetete

4

X'TAL

YV1 27MHZ_10PF_XRCGB2 7M000F2P18R0

SJ10000UI00

1

DIS@

NC

2

NC FOR GF117/GM108

NC

4

IFPC

IFPD

XTALOUTBUFF

3

IFPC

GF119/GK208

DVI/HDMI

I2CW_SDA I2CW_SCL

TXD0

NC FOR GF117/GM108

TXD0

TXD1 TXD1

TXD2 TXD2

DVI/HDMI

I2CX_SDA I2CX_SCL

NC FOR GF117/GM108

C10

B10

XTALOUT

TTTiiitttllleee

SSSiiizezeze

DDDaaattteee::: SSShhheeeeee ttt

IFPC_AUX# IFPC_AUX

GF117

NC

GF119/GK208

TXC TXC

TXD0 TXD0

TXD1 TXD1

TXD2 TXD2

GF117

NC

XTAL_OUTBUFF

RV14

1.5K_0402_1%

IFPC_L3# IFPC_L3

IFPC_L2# IFPC_L2

IFPC_L1# IFPC_L1

IFPC_L0# IFPC_L0

IFPD_AUX# IFPD_AUX

TXC TXC

1 2

1

CV38 18P_0402_50 V8J

2

NNNVVV(((222///555)))---IIIFFFP_P_P_AAABBBCCCDDDEEEFFF___DDDAAACCC___XXXTATATALLL

DDDooocucucumememennnttt NNNuuumbmbmbeeerrr RRR eee vvv

DP

N5 N4

N3 N2

R3 R2

R1 T1

T3 T2

C3

GPIO15

DP

P4 P3

R5

IFPD_L3#

R4

IFPD_L3

T5

IFPD_L2#

T4

IFPD_L2

U4

IFPD_L1#

U3

IFPD_L1

V4

IFPD_L0#

V3

IFPD_L0

D4

GPIO17

+1.8VGS_+3VGS_AON

RV11

@

10K_0402_1%

1 2

RV13

DIS@

10K_0402_1%

1 2

DIS@

CCCooompmpmpaaalll EEEllleeeccctttrrrooonnniiicccsss,,, IIInnnccc...

LA-H101PLA-H101PLA-H101P

5

222222 555333MMMooonnndddaaayyy ,,, OcOcOctttooobbb eeerrr 222222,,, 222000111 888

0.A0.A0.A

ooo fff

1

2

3

4

5

CV44

10U_0402_6.3V6M

CV46

DIS@

CV725

N17S@

2

UV1D

COMMON

12/14 FBVDDQ

B26

FBVDDQ

C25

FBVDDQ

E23

FBVDDQ

E26

FBVDDQ

F14

FBVDDQ

F21

FBVDDQ

G13

FBVDDQ

G14

FBVDDQ

G15

FBVDDQ

G16

FBVDDQ

G18

FBVDDQ

G19

FBVDDQ

G20

FBVDDQ

G21

FBVDDQ

L22

FBVDDQ

L24

FBVDDQ

L26

FBVDDQ

M21

FBVDDQ

N21

FBVDDQ

R21

FBVDDQ

T21

FBVDDQ

V21

FBVDDQ

W21

FBVDDQ

H24

FBVDDQ_AON

H26

FBVDDQ_AON

J21

FBVDDQ_AON

K21

FBVDDQ_AON

N16S-GT-S-A2_BGA595

@

Under GPUNear GPU F11

0.1U_0201_10V6K

CV394

1

N17S@

2

GF117 GF119

GK208

FBVDDQ FBVDDQ FBVDDQ FBVDDQ

FB_CAL_PD_VDDQ

FB_CAL_PU_GND

FB_CALTERM_GND

UV1C

COMMON

14/14 XVDD/VDD33

AD10

NC

AD7

NC

F11

3V3AUX_NC

V5

FERMI_RSVD1_NC

V6

FERMI_RSVD2_NC

CONFIGURABLE

POWER CHANNELS

* nc on substrate

G1

XPWR_G1

G2

XPWR_G2

G3

XPWR_G3

G4

XPWR_G4

G5

XPWR_G5

G6

XPWR_G6

G7

XPWR_G7

V1

XPWR_V1

V2

XPWR_V2

W1

XPWR_W1

W2

XPWR_W2

W3

XPWR_W3

W4

XPWR_W4

N16S-GT-S-A2_BGA595

@

GM108

3V3_AON 3V3_AON

D22

C24

B25

Near Ball

1

RV15

2

RV16

2

RV17

VDD33 VDD33 VDD33 VDD33

+VGA_CORE

+1.35VS_VRAM

2

40.2_0402_1%

DIS@

1

40.2_0402_1%

DIS@

1

60.4_0402_1%

DIS@

Under GPU Near GPU

G8 G9 G10 G12

0.1U_0201_10V6K

CV48

CV47

1

DIS@

2

Near GPUUnder GPU

0.1U_0201_10V6K

CV740

CV51

1

2

N17S@

DIS@

** XPWR pins are configurable .

These pins are not connected on the substrate.

Therefore, XPW R pins can be assigned as needed,

to improve Top layer routing, power delivery.

SSSeeecccuuurrriiitttyyy CCClllaaassssssiiifffiiicccaaatttiiiooonnn

IIIssssssuuueeeddd DDDaaattteee

TTTHHHIIISSS SSSHHHEEEEEETTT OOOFFF EEENNNGGGIIINNNEEEEEERRRIIINNNGGG DDDRRRAAAWWW IIINNNGGG IIISSS TTTHHHEEE PPPRRROOOPPPRRRIIIEEETTTAAARRRYYY PPPRRROOOPPPEEERRRTTTYYY OOOFFF CCCOOOMMMPPPAAALLL EEELLLEEECCCTTTRRROOONNNIIICCCSSS,,, IIINNNCCC... AAANNNDDD CCCOOONNNTTTAAAIIINNNSSS CCCOOONNNFFFIIIDDDEEENNNTTTIIIAAALLL AAANNNDDD TTTRRRAAADDDEEE SSSEEECCCRRREEETTT IIINNNFFFOOORRRMMMAAATTTIIIOOONNN... TTTHHHIIISSS SSSHHHEEEEEETTT MMMAAAYYY NNNOOOTTT BBBEEE TTTRRRAAANNNSSSFFF EEERRREEEDDD FFF RRROOOMMM TTTHHH EEE CCCUUUSSSTTTOOODDDYYY OOOFFF TTTHHHEEE CCCOOOMMMPPPEEETTTEEENNNTTT DDDIIIVVVIIISSSIIIOOONNN OOOFFF RRR&&&DDD DDDEEEPPPAAARRRTTTMMMEEENNNTTT EEEXXXCCCEEEPPPTTT AAASSS AAAUUUTTTHHHOOORRRIIIZZZEEEDDD BBBYYY CCCOOOMMMPPPAAALLL EEELLLEEECCCTTTRRROOONNNIIICCCSSS,,, IIINNNCCC... NNNEEEIIITTTHHHEEERRR TTTHHHIIISSS SSSHHHEEEEEETTT NNNOOORRR TTTHHHEEE IIINNNFFFOOORRRMMMAAATTTIIIOOONNN IIITTT CCCOOONNNTTTAAAIIINNNSSS MMMAAAYYY BBBEEE UUUSSSEEEDDD BBBYYY OOORRR DDD IIISSSCCCLLLOOOSSSEEEDDD TTTOOO AAANNNYYY TTTHHH IIIRRRDDD PPPAAARRRTTTYYY WWWIIITTTHHHOOOUUUTTT PPPRRRIIIOOORRR WWWRRRIIITTTTTTEEENNN CCCOOONNNSSSEEENNNTTT OOOFFF CCCOOOMMMPPPAAALLL EEELLLEEECCCTTT RRROOONNNIIICCC SSS,,, IIINNNCCC...

3

GPU_Decoupling CAPs @ Power Page

UV1E

COMMON

Voltage by GPU SKU

1U_0402_6.3V6K

4.7U_0402_6.3V6M

CV49

CV50

1

DIS@

2

4.7U_0402_6.3V6M

1U_0402_6.3V6K

CV53

CV52

1

DIS@

2

11/14 NVVDD

K10

VDD

K12

VDD

K14

VDD

K16

VDD

K18

VDD

L11

VDD

L13

VDD

L15

VDD

L17

VDD

M10

VDD

M12

VDD

M14

VDD

M16

VDD

M18

VDD

N11

VDD

N13

VDD

N15

VDD

N17

VDD

P10

VDD

P12

VDD

P14

VDD

P16

VDD

P18

VDD

R11

VDD

R13

VDD

R15

VDD

R17

VDD

T10

VDD

T12

VDD

T14

VDD

T16

VDD

T18

VDD

U11

VDD

U13

VDD

U15

VDD

U17

VDD

V10

VDD

V12

VDD

V14

VDD

V16

VDD

V18

VDD

N16S-GT-S-A2_BGA595

@

+1.8VGS_+3VGS

+1.8VGS_+3VGS_AON

222000111777///111000///222777 222000111999///000444///000999

CCCooommmpppaaalll SSSeeecrcrcr eeettt DDDaaatttaaa

DDDeeecicicippphhheeererereddd DaDaDatetete

4

+1.35VS_VRAM

1U_0402_6.3V6K

CV723

1

A A

N17S@

2

1U_0402_6.3V6K

CV724

CV721

1

N17S@

2

1U_0402_6.3V6K

CV722

1

N17S@

2

1U_0402_6.3V6K

4.7U_0402_6.3V6M

CV43

CV719

CV720

1

N17S@

2

CV39

1

DIS@

N16S@

2

1

N17S@

2

B B

1U_0402_6.3V6K

CV40

1

2

22U_0603_6.3V6M

CV728

Place under GPU

1U_0402_6.3V6K

CV41

1

DIS@

N16S@

2

22U_0603_6.3V6M

CV727

1

DIS@

N17S@

2

Place near GPU

0.1U_0201_10V6K

CV42

1

N16S@

2

10U_0402_6.3V6M

CV726

1

N17S@

2

22U_0603_6.3V6M

10U_0402_6.3V6M

CV45

1

2

CIZ00 22uF x1 change to 10uF x2

C C

+1.8VGS_+3VGS PLL VDD

1 2

LV10

N17S@

HCB1005KF-300 T25_2P

D D

1

22U_0603_6.3V6M

4.7U_0402_6.3V6M

CV396

1

2

CV395

1

N17S@

2

UV1F

COMMON

13/14 GND

A2

GND

AB17

GND

AB20

GND

AB24

GND

AC2

GND

AC22

GND

AC26

GND

AC5

GND

AC8

GND

AD12

GND

AD13

GND

A26

GND

AD15

GND

AD16

GND

AD18

GND

AD19

GND

AD21

GND

AD22

GND

AE11

GND

AE14

GND

AE17

GND

AE20

GND

AB11

GND

AF1

GND

AF11

GND

AF14

GND

AF17

GND

AF20

GND

AF23

GND

AF5

GND

AF8

GND

AG2

GND

AG26

GND

AB14

GND

B1

GND

B11

GND

B14

GND

B17

GND

B20

GND

B23

GND

B27

GND

B5

GND

B8

GND

E11

GND

E14

GND

E17

GND

E2

GND

E20

GND

E22

GND

E25

GND

E5

GND

E8

GND

H2

GND

H23

GND

H25

GND

H5

GND

K11

GND

K13

GND

K15

GND

K17

GND

L10

GND

L12

GND

L14

GND

L16

GND

L18

GND

L2

GND

L23

GND

L25

GND

L5

GND

M11

GND

N16S-GT-S-A2_BGA595

@

M13

GND

M15

GND

M17

GND

N10

GND

N12

GND

N14

GND

N16

GND

N18

GND

P11

GND

P13

GND

P15

GND

P17

GND

P2

GND

P23

GND

P26

GND

P5

GND

R10

GND

R12

GND

R14

GND

R16

GND

R18

GND

T11

GND

T13

GND

T15

GND

T17

GND

U10

GND

U12

GND

U14

GND

U16

GND

U18

GND

U2

GND

U23

GND

U26

GND

U5

GND

V11

GND

V13

GND

V15

GND

V17

GND

Y2

GND

Y23

GND

Y26

GND

Y5

GND

AA7

GND

AB7

GND

TTTiiitttllleee

SSSiiizezeze

DDDaaattteee::: SSShhheeeeee ttt

CCCooompmpmpaaalll EEEllleeeccctttrrrooonnniiicccsss,,, IIInnnccc...

NNNVVV(((333///555)))---POPOPOWWWEEERRR

DDDooocucucumememennnttt NNNuuumbmbmbeeerrr RRR eee vvv

LA-H101PLA-H101PLA-H101P

5

222333 555333MMMooonnndddaaayyy ,,, OcOcOctttooobbb eeerrr 222222,,, 222000111 888

0.A0.A0.A

ooo fff

1

UV1N

GPIO

COMMON

8/14 MISC1

GM108

GPIO16 GPIO20 GPIO21

GPIO8

GF117

GK208 GF117 GF119

GPIO16 GPIO20

GPIO8

NC NC

GF117

GK208

GM108

NC

E12

THERMDN

F12

STRAP0 STRAP1 STRAP2 STRAP3 STRAP4

STRAP5

STRAPREF0

12

RV58

40.2K_0402_1%

N16S@

AE5 AD6 AE6 AF6

AG4

N16S-GT-S-A2_BGA595

@

EF1100

1 DD2 E4 E3 D3

C1

F6

F4

F5

THERMDP

JTAG_TCK JTAG_TMS JTAG_TDI JTAG_TDO JTAG_TRST#

UV1L

COMMON

10/14 MISC2

VMON_IN0_NC VMON_IN1_NC

STRAP0 STRAP1 STRAP2 STRAP3 STRAP4

STRAP5_NC

MULTISTRAP_REF0_GND

MULTISTRAP_REF1_GND

MULTISTRAP_REF2_GND

N16S-GT-S-A2_BGA595

@

NC FOR

GM108

GPU_JTAG_TCK

T231 TP@

GPU_JTAG_TMS

T232 TP@

GPU_JTAG_TDI

T242 TP@

GPU_JTAG_TDO

T243 TP@

GPU_JTAG_TRST#

A A

+1.8VGS_+3VGS_AON

RV49 0_0402_5%

1 2

@

I2CS_SCL

D9

I2CS_SCL

I2CS_SDA

D8

I2CS_SDA

A9

I2CC_SCL

B9

I2CC_SDA

C9

I2CB_SCL

NC

C8

I2CB_SDA

NC

GPU_VID0

C6

GPIO0

GPIO0_GC6_FB_EN

B2

GPIO1

GPU_EVENT#_D

D6

GPIO2

C7

GPIO3

DGPU_MAIN_EN

F9

GPIO4

A3

GPIO5

A4

PSI

GPIO6

GK208

B6

GM108

GPIO7

GPIO8_OVERT#

A6

OVERT

GPIO8

GPIO9_ALERT#

F8

GPIO9

MEM_VREF

C5

GPIO10

E7

GPIO11

VGA_AC_DET

D7

GPIO12

B4

GPIO13

D5

GPIO16

NC

E6

GPIO20

NC

PLT_RST_VGA_HOLD#

C4

GPIO21

NC

E9

NC

D12

ROM_CS#

ROM_SI

B12

ROM_SI

ROM_SO

A12

ROM_SO

ROM_SCLK

C12

ROM_SCLK

GPU_BUFRST

D11

BUFRST#

D10

PGOOD

NC

GF119GF117

2

+1.8VGS_+3VGS_AON

1

RV1922.2K_0402_5%

DIS@

1

RV2122.2K_0402_5%

DIS@

2

1

2

DV1

1

2

1 2

RV2466 0_0402_5%

N16S@

1 2

RV2467 0_0402_5%

@

I2CS SMBUS: 0x96 and 0x9E(Default)

0_0402_5%RV29 RB751V-40_SOD323-2D IS@

RB751V-40_SOD323-2DV2 DIS@

GPU_VID0 [50] GC6_FB_EN [11,25] GPU_EVENT# [9]

DGPU_MAIN_EN [26]

PSI [50]

GPU_PROHOT# [33,42] MEM_VREF [27]

PLT_RST_VGA_MON# [21]

PLT_RST_VGA_HOLD# [21]

To DGPU VR

3

[21] GPU_TESTMODE

PLT_RST_VGA_HOLD# DGPU_MAIN_EN

VPSGIA_AC_DET

GPU_EVENT#_D

GPIO8_OVERT#

GPIO9_ALERT#

GPU_JTAG_TRST#

GPU_BUFRST

MEM_VREF

PLT_RST_VGA_MON#

GC6_FB_EN

+1.8VGS_+3VGS_AON

1

RV18210K_0201_5% DIS@

1

RV20210K_0201_5% DIS@

1

RV22210K_0201_5% DIS@

1

RV23210K_0201_5% DIS@

RV261GC6@210K_0201_5%

1

RV272100K_0201_5%

DIS@

1

RV28210K_0201_5% DIS@

1

RV30210K_0201_5% DIS@

2

1

10K_0201_5%@RV36

2

10K_0201_5%RV371DIS@

2

100K_0201_5%RV381DIS@

2

1

10K_0201_5%@RV39

RV401GC6@210K_0201_5%

Internal Thermal Sensor

I2CS_SCL

I2CS_SDA

S

QV147B

S TR PJT138KA 2N SOT363-6

DIS@

+1.8VGS_+3VGS_AON

S

QV147A

S TR PJT138KA 2N SOT363-6

G

5

DIS@

34

D

4

G

2

61

D

VGS(Max) : 0.8~1.1 V

Link to PCH SML1

PU @ PCH SIDE

EC_SMB_CK2 [8,33,35]

EC_SMB_DA2 [8,33,35]

5

DV3

@

RB751V-40_SOD323-2

1

+3VS

@

10K_0201_5% RV60

1 2

12

2

0_0402_5%@RV61

AC_PRESENT [10,33]

STRAP

10/13 - Strap Pin Modify for MX110/130 (Pop RV81, Un-Pop RV64)

+1.8VGS_+3VGS_AON

+1.8VGS_+3VGS

RV473

RV474

N16S@

N17S@

0_0402_5%

1 2

4.99K_0402_1%

14.7K_0402_1%

4.99K_0402_1%

12

N16S@

RV2468

RV2469

@

4.99K_0402_1%

12

4.99K_0402_1%

12

@

N16S@

RV65

RV64

ROM_SI ROM_SO ROM_SCLK

0_0402_5%

@

+1.8VGS_+3VGS_AON

100K_0402_5%

12

RV444

@

100K_0402_5%

12

RV443

12

10K_0402_1%

RV2470

@

45.3K_0402_1%

12

RV385

@

STRAP0 : PU 49.9K (50K) STRAP[1:5] : Reserved

45.3K_0402_1%

4.99K_0402_1%

12

N16S@

RV389

RV51

RV382

@

4.99K_0402_1%

12

RV387

RV390

RV388

@

49.9K_0402_1%

12

RV384

4.99K_0402_1%

12

RV383

STRAP

RV2471

STRAP0 STRAP1 STRAP2 STRAP3 STRAP4 STRAP5

RV381

@

NV Suggest

B B

VGA_AC_DET AC_PRESENT

N16S VRAM Res.

N17S-G0/G2 VRAM Strap

C C

RAM_CFG

0x9(LML)

0xA(LMH)

STRAP0

N17_M2G@

100K_0402_5%

RV384

N17_H2G@

100K_0402_5%

NOTE

RV383

STRAP1

STRAP2

RV51

RV388

N17_M2G@

100K_0402_5%

M2G

H2G

RV388

N17_H2G@

100K_0402_5%

RV390

N17_M2G@

100K_0402_5%

RV51

N17_H2G@

100K_0402_5%

RV390

N17_H2G@

100K_0402_5%

N17S Strap

RV2469

Strap

N17S@

S RES 1/16W 100K +-5% 0402

ROM_SO ROM_SC LK STRAP4STRAP3ROM_SI STRAP5

RV2471 RV2468

N17S@

S RES 1/16W 100K +-5% 0402

N17S@

S RES 1/16W 100K +-5% 0402

RV381

N17S@

S RES 1/16W 100K +-5% 0402

RV387

N17S@

S RES 1/16W 100K +-5% 0402

RV385

N17S@

S RES 1/16W 100K +-5% 0402

RV443

N17S@

S RES 1/16W 100K +-5% 0402

N17S-G1 VRAM Strap

RAM_CFG

STRAP2

0x00(LLL)

0x01(LLH)

D D

0x02(LHL)

0x03(LHH)

0x04(HLL)

0x05(HLH)

0x06(HHL)

0x07(HHH)

0x08(LLM)

RV388

S2G

@

RV382

M2G

@

RV382

H2G

@

STRAP1

STRAP0

RV383

RV390

@

RV383

RV390

@

RV384

RV390

@

S

SSeeecccuuurrriiitttyyy CCClllaaass

ssi

ssiifffiiicccaaatttiiiooonn

n

I

IIssss

ssu

uueeeddd DDDaaatttee

e

TTT

HHH

III

SSS

HHH

EEE

TTT

OOO

FFF

EEE

NNN

GGG

III

NNN

EEE

RRR

III

NNN

GGG

DDD

RRR

AAA

NNN

DDD

TTT

RRR

AAA

DDD

EEE

SSS

EEE

CCC

RRR

EEE

TTT

III

NNN

FFF

OOO

RRR

MMM

AAA

TTT

III

OOO

NNN

DDD

EEE

PPP

AAA

RRR

TTT

MMM

EEE

NNN

TTT

EEE

XXX

CCC

EEE

PPP

TTT

AAA

SSS

AAA

UUU

TTT

HHH

OOO

RRR

1

2

3

MMMAAAYYY BBBEEE UUUSSSEEEDDD BBBYYY OOORRR DDDIIISSSCCCLLLOOOSSSEEEDDD TTTOOO AAANNNYYY TTTHHHIIIRRRDDD PPPAAARRRTTTYYY WWWIIITTTHHHOOOUUUTTT PPPRRRIIIOOORRR WWWRRRIIITTTTTTEEENNN CCCOOONNNSSSEEENNNTTT OOOFFF CCCOOOMMMPPPAAALLL EEELLLEEECCCTTTRRROOONNNIIICCCSSS,,, IIINNNCCC...

CCCooommmpppaaalll SSSeeecccrrreeettt DDDaaatttaaa

222000111777///111000///222777 222000111999///000444/// 000999

AAA

WWW

IIINNN

GGG

III

SSS

TTT

...

TTT

HHH

III

SSS

HHHEEE

III

ZZZ

EEE

DDD

BBB

YYY

CCC

DDDeeeccciiippphhheeerrreeeddd DDDaaatttee

HHH

EEE

PPP

RRR

OOO

PPP

RRR

III

EEE

TTT

AAA

RRR

YYY

EEE

TTT

MMM

AAA

YYY

NNN

OOO

TTT

BBB

EEE

TTT

RRR

OOO

MMM

PPP

AAA

LLL

EEE

LLL

EEE

CCC

TTT

RRR

OOO

NNN

III

4

e

PPP

RRR

OOO

PPP

EEE

RRR

TTT

YYY

OOO

FFF

CCC

OOO

MMM

PPP

AAA

LLL

EEE

LLL

EEE

CCC

TTT

RRR

OOO

NNN

III

CCC

AAA

NNN

CCC

SSS

SSS,,,

SSS

FFF

EEE

RRR

EEE

DDD

FFF

RRR

OOO

MMM

TTT

HHH

EEE

CCC

UUU

SSS

TTT

OOO

DDD

YYY

OOO

FFF

,,,

TTT

III

NNN

CCC

...

NNN

EEE

III

TTT

HHH

EEE

RRR

TTT

HHH

III

SSS

HHH

EEE

TTT

NNN

OOO

RRR

TTT

HHH

CCCooommmpppaaalll EEEllleeeccctttrrrooonnniiicccsss ,,, IIInnnccc...

TTTiiitttllleee

III

NNN

CCC

...

AAA

NNN

DDD

CCC

OOO

NNN

TTT

AAA

III

NNN

SSS

CCC

OOO

NNN

FFF

III

DDD

HHH

EEE

CCC

OOO

MMM

PPP

EEE

TTT

EEE

NNN

TTT

DDD

III

VVV

III

SSSIII

OOO

NNN

OOO

FFF

EEE

III

NNN

FFF

OOO

RRR

MMM

AAA

TTTIII

OOO

NNN

III

TTT

CCC

OOO

NNN

TTT

AAA

III

NNN

SSS

NNNVVV(((444 ///555)))---GGGPPPIIIOOO///SSStttrrr aaa ppp

EEENNN

TTT

III

AAALLL

SSSiiizzzeee DDDooocucucummmeeennnttt NNNuuummmbbbeeerrr RRReeevvv

RRR

&&&

DDD

DDDaaattteee::: SSShhheeeeee ttt ooofff

5

LA-H101PLA-H101PLA-H101P

0.A0.A0.A

222444 555333MMMooonnndddaaayyy,,, OOOccctttooobbbeeerrr 222222,,, 222000111888

1

2

3

4

5

For GC6

UV1B

COMMON

[27] FB_A_D[0..31]

A A

[27] FB_A_D[32..63]

B B

[27] FB_A_DBI[3..0]

[27] FB_A_DBI[7..4]

C C

D D

[27] FB_A_EDC[3..0]

[27] FB_A_EDC[7..4]

For VRAM DEBUG using

T2402 @

FB_A_D0 FB_A_D1 FB_A_D2 FB_A_D3 FB_A_D4 FB_A_D5 FB_A_D6 FB_A_D7 FB_A_D8 FB_A_D9 FB_A_D10 FB_A_D11 FB_A_D12 FB_A_D13 FB_A_D14 FB_A_D15 FB_A_D16 FB_A_D17 FB_A_D18 FB_A_D19 FB_A_D20 FB_A_D21 FB_A_D22 FB_A_D23 FB_A_D24 FB_A_D25 FB_A_D26 FB_A_D27 FB_A_D28 FB_A_D29 FB_A_D30 FB_A_D31 FB_A_D32 FB_A_D33 FB_A_D34 FB_A_D35 FB_A_D36 FB_A_D37 FB_A_D38 FB_A_D39 FB_A_D40 FB_A_D41 FB_A_D42 FB_A_D43 FB_A_D44 FB_A_D45 FB_A_D46 FB_A_D47 FB_A_D48 FB_A_D49 FB_A_D50 FB_A_D51 FB_A_D52 FB_A_D53 FB_A_D54 FB_A_D55 FB_A_D56 FB_A_D57 FB_A_D58 FB_A_D59 FB_A_D60 FB_A_D61 FB_A_D62 FB_A_D63

FB_A_DBI0 FB_A_DBI1 FB_A_DBI2 FB_A_DBI3 FB_A_DBI4 FB_A_DBI5 FB_A_DBI6 FB_A_DBI7

FB_A_EDC0 FB_A_EDC1 FB_A_EDC2 FB_A_EDC3 FB_A_EDC4 FB_A_EDC5 FB_A_EDC6 FB_A_EDC7

FB_VREF

2/14 FBA

E18

FBA_D0

F18

FBA_D1

E16

FBA_D2

F17

FBA_D3

D20

FBA_D4

D21

FBA_D5

F20

FBA_D6

E21

FBA_D7

E15

FBA_D8

D15

FBA_D9

F15

FBA_D10

F13

FBA_D11

C13

FBA_D12

B13

FBA_D13

E13

FBA_D14

D13

FBA_D15

B15

FBA_D16

C16

FBA_D17

A13

FBA_D18

A15

FBA_D19

B18

FBA_D20

A18

FBA_D21

A19

FBA_D22

C19

FBA_D23

B24

FBA_D24

C23

FBA_D25

A25

FBA_D26

A24

FBA_D27

A21

FBA_D28

B21

FBA_D29

C20

FBA_D30

C21

FBA_D31

R22

FBA_D32

R24

FBA_D33

T22

FBA_D34

R23

FBA_D35

N25

FBA_D36

N26

FBA_D37

N23

FBA_D38

N24

FBA_D39

V23

FBA_D40

V22

FBA_D41

T23

FBA_D42

U22

FBA_D43

Y24

FBA_D44

AA24

FBA_D45

Y22

FBA_D46

AA23

FBA_D47

AD27

FBA_D48

AB25

FBA_D49

AD26

FBA_D50

AC25

FBA_D51

AA27

FBA_D52

AA26

FBA_D53

W26

FBA_D54

Y25

FBA_D55

R26

FBA_D56

T25

FBA_D57

N27

FBA_D58

R27

FBA_D59

V26

FBA_D60

V27

FBA_D61

W27

FBA_D62

W25

FBA_D63

D19

FBA_DQM0

D14

FBA_DQM1

C17

FBA_DQM2

C22

FBA_DQM3

P24

FBA_DQM4

W24

FBA_DQM5

AA25

FBA_DQM6

U25

FBA_DQM7

E19

FBA_DQS_WP0

C15

FBA_DQS_WP1

B16

FBA_DQS_WP2

B22

FBA_DQS_WP3

R25

FBA_DQS_WP4

W23

FBA_DQS_WP5

AB26

FBA_DQS_WP6

T26

FBA_DQS_WP7

F19

FBA_DQS_RN0

C14

FBA_DQS_RN1

A16

FBA_DQS_RN2

A22

FBA_DQS_RN3

P25

FBA_DQS_RN4

W22

FBA_DQS_RN5

AB27

FBA_DQS_RN6

T27

FBA_DQS_RN7

D23

FB_VREF_PROBE

N16S-GT-S-A2_BGA595

@

GF117/GF119

GK208

FBA_DEBUG0 FBA_DEBUG1

FB_PLLAVDD

F3

FB_CLAMP

NC

GF119

C27

FBA_CMD0

C26

FBA_CMD1

E24

FBA_CMD2

F24

FBA_CMD3

D27

FBA_CMD4

D26

FBA_CMD5

F25

FBA_CMD6

F26

FBA_CMD7

F23

FBA_CMD8

G22

FBA_CMD9

G23

FBA_CMD10

G24

FBA_CMD11

F27

FBA_CMD12

G25

FBA_CMD13

G27

FBA_CMD14

G26

FBA_CMD15

M24

FBA_CMD16

M23

FBA_CMD17

K24

FBA_CMD18

K23

FBA_CMD19

M27

FBA_CMD20

M26

FBA_CMD21

M25

FBA_CMD22

K26

FBA_CMD23

K22

FBA_CMD24

J23

FBA_CMD25

J25

FBA_CMD26

J24

FBA_CMD27

K27

FBA_CMD28

K25

FBA_CMD29

J27

FBA_CMD30

J26

FBA_CMD31

B19

NC

GF119

GF117

FBA_CMD32

F22

FBA_CMD34

J22

FBA_CMD35

D24

FBA_CLK0

D25

FBA_CLK0#

N22

FBA_CLK1

M22

FBA_CLK1#

D18

FBA_WCK01 FBA_WCK01#

C18 D17

FBA_WCK23

D16

FBA_WCK23#

T24

FBA_WCK45

U24

FBA_WCK45#

V24

FBA_WCK67

V25

FBA_WCK67#

F16

FB_PLLAVDD

NC

FB_PLLAVDD

FB_DLLAVDD

P22

H22

Close to H22

1

2

N17S@

1 2

RV2456 10K_0402_5%

FB_A_CMD0 FB_A_CMD1 FB_A_CMD2 FB_A_CMD3 FB_A_CMD4 FB_A_CMD5 FB_A_CMD6 FB_A_CMD7 FB_A_CMD8 FB_A_CMD9 FB_A_CMD10 FB_A_CMD11 FB_A_CMD12 FB_A_CMD13 FB_A_CMD14 FB_A_CMD15 FB_A_CMD16 FB_A_CMD17 FB_A_CMD18 FB_A_CMD19 FB_A_CMD20 FB_A_CMD21 FB_A_CMD22 FB_A_CMD23 FB_A_CMD24 FB_A_CMD25 FB_A_CMD26 FB_A_CMD27 FB_A_CMD28 FB_A_CMD29 FB_A_CMD30 FB_A_CMD31

1 2 1 2

FB_A_CLK0 FB_A_CLK#0 FB_A_CLK1 FB_A_CLK#1

FB_A_WCK0 FB_A_WCK#0 FB_A_WCK1 FB_A_WCK#1 FB_A_WCK2 FB_A_WCK#2 FB_A_WCK3 FB_A_WCK#3

1.35V

60.4_0402_1%@RV73

60.4_0402_1%@RV74

FB_A_WCK0 [27] FB_A_WCK#0 [27] FB_A_WCK1 [27] FB_A_WCK#1 [27] FB_A_WCK2 [27] FB_A_WCK#2 [27] FB_A_WCK3 [27] FB_A_WCK#3 [27]

PLLAVDD

Close to P22

CV56

CV55

0.1U_0201_10V K X5R

2

1

DIS@

1

2

Close to H22

CV794

CV793

0.1U_0201_10V K X5R

2

1

N17S@

1

2

3

GC6_FB_EN[11,24]

DGPU_PWROK[21,26,50]

FB_A_CMD[0..31] [27]

FB_A_CMD14

FBA_CKE_L FBA_CKE_H

FBA_RST_L FBA_RST_H

FB_A_CMD30

FB_A_CMD13 FB_A_CMD29

RV69 RV70

RV71 RV72

1 1

GDDR5 design

FBVDDQ_GPU

+1.35VS_VRAM

FB_A_CLK0 [ 27] FB_A_CLK#0 [27] FB_A_CLK1 [ 27] FB_A_CLK#1 [27]

Close to F16

PLLAVDD +1.0VS_DGPU

0.1U_0201_10V K X5R

1

DIS@

2

SM01000NV00

1

DIS@

2

1.0V

1 2

LV3

CV58

CV57

22U_0603_6.3V6M

Near GPU

SSSeeecccuuurrriiitttyyy CCClllaaassssssiiifffiiicccaaatttiiiooonnn

IIIssssssuuueeeddd DDDaaattteee

TTTHHHIIISSS SSSHHHEEEEEETTT OOOFFF EEENNNGGGIIINNNEEEEEERRRIIINNNGGG DDDRRRAAAWWW IIINNNGGG IIISSS TTTHHHEEE PPPRRROOOPPPRRRIIIEEETTTAAARRRYYY PPPRRROOOPPPEEERRRTTTYYY OOOFFF CCCOOOMMMPPPAAALLL EEELLLEEECCCTTTRRROOONNNIIICCCSSS,,, IIINNNCCC... AAANNNDDD CCCOOONNNTTTAAAIIINNNSSS CCCOOONNNFFFIIIDDDEEENNNTTTIIIAAALLL AAANNNDDD TTTRRRAAADDDEEE SSSEEECCCRRREEETTT IIINNNFFFOOORRRMMMAAATTTIIIOOONNN... TTTHHHIIISSS SSSHHHEEEEEETTT MMMAAAYYY NNNOOOTTT BBBEEE TTTRRRAAANNNSSSFFFEEERRREEEDDD FFFRRROOOMMM TTTHHHEEE CCCUUUSSSTTTOOODDDYYY OOOFFF TTTHHHEEE CCCOOOMMMPPPEEETTTEEE NNNTTT DDDIIIVVV IIISSSIIIOOONNN OOOFFF RRR&&&DDD DDDEEEPPPAAARRRTTTMMMEEENNNTTT EEEXXXCCCEEEPPPTTT AAASSS AAAUUUTTTHHHOOORRRIIIZZZEEEDDD BBBYYY CCCOOOMMMPPPAAALLL EEELLLEEECCCTTTRRROOONNNIIICCCSSS,,, IIINNNCCC... NNNEEEIIITTTHHHEEERRR TTTHHHIIISSS SSSHHHEEEEEETTT NNNOOORRR TTTHHHEEE IIINNNFFFOOORRRMMMAAATTTIIIOOONNN IIITTT CCCOOONNNTTTAAAIIINNNSSS MMMAAAYYY BBBEEE UUUSSSEEEDDD BBBYYY OOORRR DDDIIISSSCCCLLLOOOSSSEEEDDD TTTOOO AAANNNYYY TTTHHHIIIRRRDDD PPPAAARRRTTTYYY WWWIIITTTHHHOOOUUUTTT PPPRRRIIIOOORRR WWW RRRIIITTTTTTEEENNN CCCOOONNNSSSEEENNNTTT OOOFFF CCCOOOMMMPPPAAALLL EEELLLEEE CCCTTTRRROOONNNIIICCCSSS,,, IIINNNCCC...

222000111777///111000///222777 222000111999///000444///000999

DIS@ DIS@

DIS@

+1.8VGS_+3VGS_AON

CV54

0.1U_0201_10V6K

1

@

2

RV68 0_0402_5%

2

A

1

B

1 2

NOGC6@

Stuff RV201 if not support GC6

+1.35VS_VRAM

2

10K_0201_1%

2

10K_0201_1%

2

10K_0201_1%

2

10K_0201_1%

RV2464

N16S@

015 52_H CB10 KF-300T2 2P

0_0805_5%

+1.8VGS_+3VGS

RV2465

N17S@

1 2

0_0805_5%

CCCooommmpppaaalll SSSeeecrecrecrettt DDDaaatttaaa

DDDeeeccciiippphhheeerrreeeddd DDDaaattteee

Normal:1.8V GC6:1.3V

1.8V OR GATE

UV20

@

5

74AUP1G32GW_TSSOP5

SA000054300

4

Vcc

Y

G

3

1.35V_PWR_EN [51]

SA000099200 (Main) : VIH(min) = 0.8V SA00008I400 (2nd) : VIH(min) = 0.8V

GC6_FB_EN

DGPU_PWROK

DV6

2

3

BAV70W_SOT323-3

From DG-07158-001_v05_secured(NVDIA Spec)

TTTiii tttllleee

SSS iiizzzeee

4

DDDaaattteee ::: SSShhheeeeeettt ooo fff

CCCooommmpppaaalll EEEllleeeccctttrrrooonnniiicccsss,,, IIInnnccc...

NNNVVV(((555///555)))---MMMEEEMMMOOORRRYYY FFFBBBAAA

DDDooocccuuummmeeennnttt NNNuuummmbbbeeerrr RRReeevvv

LA-H101PLA-H101PLA-H101P

5

GC6@

1.35V_PWR_EN

1

12

RV2462

16.5K_0402_5%

GC6@

222555 555333MMMooonnndddaaayyy,,, OOOccctttooobbbeeerrr 222222,,, 222000111888

0.A0.A0.A

5

+1.8VS

2

1

+3VS to +3VS_DGPU

RV75 47K_0402_5%

DIS@

1 2

DGPU_MAIN_EN#

D D

[24] DGPU_MAIN_EN

DGPU_MAIN_EN

RV81 0_0402_5%

1 2

1U_0402_6.3V6K

CV62

1

@

2

+3VS

13

D

2

G

S

RV66

RV67

1

RV77 4.7K_0201_5%

DIS@

QV148 BSS138W-7-F_SOT323-3

DIS@

1

2

N17S@

0_0603_5%

+1.8VGS_+3VSGS_S

2

N16S@

0_0402_5%

DGPU_MAIN_EN#_GATE

4

QV3

DIS@

ME2301DC-G_SOT23-3

D

S

13

G

2

1

0.1U_0201_10V K X5R

CV59

2

DIS@

3

+1.8VGS_+3VGS+5VALW

12

RV76 22_0603_1%

DIS@

1

2

4.7U_0402_6.3V6M

CV60

2

DIS@

1

0.1U_0201_10V K X5R

1U_0402_6.3V6K

1

0.1U_0201_10V K X5R

CV736

CV61

DIS@

CV737

61

2

DIS@

D

2

DIS@

S

DGPU_MAIN_EN#

2

G

QV6A 2N7002KDW_SOT363-6

DIS@

2

1

VCC

GND

OUT Y

+1.0VS_DGPU+5VALW

22_0603_1%

RV79

12

DIS@

61

D

QV5A

2

2N7002KDW_SOT363-6

G

DIS@

S

DV4

DIS@

GPUCORE_EN

4

RB751S-40_SOD523-2

1 2

RV105

DIS@

40.2K_0402_1%

1 2

DV5

DIS@

RB751S-40 SOD-523

1 2

RV103

DIS@

56K_0402_1%

1 2

Output 3.3V SA00009WE00 (Main) : VIH(min) = 1.2V

VGA_CORE_EN [5 0]

1

CV197

DIS@

2

0.1U_0201_10V6K

Output 2.6V SA0000ACG00(Main) : VIH(min) = 1.6V

1.0VS_DGPU_EN [26,46]

1

CV196

DIS@

2

0.1U_0201_10V6K

+3VS to +3VS_DGPU_AON

QV7

DIS@

ME2301DC-G_SOT23-3

D

RV83 47K_0402_5%

DIS@

1 2

DGPU_PWROK[21,25,50]

DGPU_PWR_EN#

DGPU_PWR_EN

RV86 0_0402_5%

1 2

DGPU_PWROK

+1.35VGS_PGOOD

1U_0402_6.3V6K

CV66

1

@

2

C C

DGPU_PWR_EN[1 1,26,33]

B B

+1.8VGS_+3VSGS_S

RV85

DIS@

10K_0201_5%

1 2

13

D

DIS@

2

QV149

G

BSS138W-7-F_SOT323-3

S

DIS@

1 2

DG1 RB 751V-40_SOD323-2

0_0402_5%

1 2

RG2

DGPU_PWR_EN#_GATE

S

13

G

2

1

0.1U_0201_10V K X5R

2

4.7U_0402_6.3V6M

1U_0402_6.3V6K

CV64

CV63

2

1

DIS@

10K_0201_5%

+1.8VGS_+3VGS_AON+5VALW

1

0.1U_0201_10V K X5R

CV739

CV738

CV65

0.1U_0201_10V K X5R

2

N17S@

DIS@

+1.8VGS_+3VGS_AON +3VS

RG1

N16S@

1 2

12

34

D

S

RG82 10K_0201_5%

N17S@

1 2

470_0603_5%

RV84

@

5

G

QV6B 2N7002KDW_SOT363-6

DIS@

DGPU_PWR_EN#

GPU_ALL_PGOOD [11][51] +1.35VGS_PGOOD

DGPU_MAIN_EN

QV152B

2N7002KDW_SOT363-6

[26,46] 1.0VS_DGPU_EN

+3VALW +3VS

12

61

D

G

2

S

DIS@

DGPU_PWR_EN[11 ,26,33]

RV106

DIS@

100K_0402_5%

QV152A

12

RV108 10K_0402_5%

34

D

G

5

S

DIS@

2N7002KDW_SOT363-6

DIS@

1.8VSDGPU_MAIN

5

G

100K_0402_1%

RV78

12

DIS@

1.0VS_DGPU_EN#

34

D

QV5B 2N7002KDW_SOT363-6

DIS@

S

+3VS

UV10

DIS@

NL17SZ08DFT2G_SC70-5

5

1

IN B

2

IN A

3

RV256

@

100K_0402_5%

1 2

A A

SSSeeecccuuurrriiitttyyy CCClllaaassssssiiifffiiicccaaatttiiiooonnn

IIIssssssuuueeeddd DDDaaattteee

TTTHHHIIISSS SSSHHHEEEEEETTT OOOFFF EEENNNGGGIIINNNEEEEEERRRIIINNNGGG DDDRRRAAAWWWIIINNNGGG IIISSS TTTHHHEEE PPPRRROOOPPPRRRIIIEEETTTAAARRRYYY PPPRRROOOPPPEEERRRTTTYYY OOOFFF CCCOOOMMMPPPAAALLL EEELLLEEECCCTTTRRROOONNNIIICCCSSS,,, IIINNNCCC... AAANNNDDD CCCOOONNNTTTAAAIIINNNSSS CCCOOONNNFFFIIIDDDEEENNNTTTIIIAAALLL AAANNNDDD TTTRRRAAADDDEEE SSSEEECCCRRREEETTT IIINNNFFFOOORRRMMMAAATTTIIIOOONNN... TTTHHHIIISSS SSSHHHEEEEEETTT MMMAAAYYY NNNOOOTTT BBBEEE TTTRRRAAANNNSSSFFFEEERRREEEDDD FFFRRROOOMMM TTTHHHEEE CCCUUUSSSTTTOOODDDYYY OOOFFF TTTHHHEEE CCCOOOMMMPPPEEETTTEEENNNTTT DDDIIIVVVIIISSSIIIOOONNN OOOFFF RRR&&&DDD DDDEEEPPPAAARRRTTTMMMEEENNNTTT EEEXXXCCCEEEPPPTTT AAASSS AAAUUUTTTHHHOOORRRIIIZZZEEEDDD BBBYYY CCCOOOMMMPPPAAALLL EEELLLEEECCCTTTRRROOONNNIIICCCSSS,,, IIINNNCCC... NNNEEEIIITTTHHHEEERRR TTTHHHIIISSS SSSHHHEEEEEETTT NNNOOORRR TTTHHHEEE IIINNNFFFOOORRRMMMAAATTTIIIOOONNN IIITTT CCCOOONNNTTTAAAIIINNNSSS

5

4

3

MMMAAAYYY BBBEEE UUUSSSEEEDDD BBBYYY OOORRR DDDIIISSSCCCLLLOOOSSSEEEDDD TTTOOO AAANNNYYY TTTHHHIIIRRRDDD PPPAAARRRTTTYYY WWWIIITTTHHHOOOUUUTTT PPPRRRIIIOOORRR WWWRRRIIITTTTTTEEENNN CCCOOONNNSSSEEENNNTTT OOOFFF CCCOOOMMMPPPAAALLL EEELLLEEECCCTTTRRROOONNNIIICCCSSS,,, IIINNNCCC...

222000111777///111000///222777 222000111999///000444///000999

CCCooo mmmpppaaalll SSS eeecccrrreeettt DDDaaatttaaa

DDDeeeccciiippphhheeerrreeeddd DDDaaattteee

2

CCCooommmpppaaalll EEEllleeeccctttrrrooonnniiicccsss,,, IIInnnccc...

TTTiiitttllleee

DDDGGGPPPUUU___DDDCCC///DDDCCC IIInnnttteeerrrfffaaaccceee

SSSiiizzzeee

DDDoooccc uuummmeeennnttt NNNuuummm bbbeeerrr RRReee vvv

DDDaaattteee ::: SSShhheeeeeettt ooo fff

LA-H101PLA-H101PLA-H101P

1

222666 555333MMMooonnndddaaayyy,,, OOOccctttooobbbeeerrr 222222,,, 222000111888

0.A0.A0.A

5

4

3

2

1

VRAM Memory Partition A

MF=0

UV21

2

DIS@

1

CV70

C2

EDC0 EDC3

C13

EDC1 EDC2

R13

EDC2 EDC1

R2

EDC3 EDC0

D2

DBI0# DBI3#

D13

DBI1# DBI2#

P13

DBI2# DBI1#

P2

DBI3# DBI0#

J12

CK

J11

CK#

J3

CKE#

H11

BA0/A2 BA2/A4

K10

BA1/A5 BA3/A3

K11

BA2/A4 BA0/A2

H10

BA3/A3 BA1/A5

K4

A8/A7 A10/A0

H5

A9/A1 A11/A6

H4

A10/A0 A8/A7

K5

A11/A6 A9/A1

J5

A12/RFU/NC

A5

VPP/NC

U5

VPP/NC

J1

MF

J10

SEN

J13

ZQ

J4

ABI#

G3

RAS# CAS#

G12

CS# WE#

L3

CAS# RAS#

L12

WE# CS#

D5

WCK01# WCK23#

D4

WCK01 WCK23

P5

WCK23# WCK01#

P4

WCK23 WCK01

A10

VREFD

U10

VREFD

J14

VREFC

J2

RESET#

H1

VSS

K1

VSS

B5

VSS

G5

VSS

L5

VSS

T5

VSS

B10

VSS

D10

VSS

G10

VSS

L10

VSS

P10

VSS

T10

VSS

H14

VSS

K14

VSS

G1

VDD

L1

VDD

G4

VDD

L4

VDD

C5

VDD

R5

VDD

C10

VDD

R10

VDD

D11

VDD

G11

VDD

L11

VDD

P11

VDD

G14

VDD

L14

VDD

170-BALL

SGRAM GDDR5

22U_0603_6.3V6M

MF=0 MF=1 MF=0MF=1

1

CV71

2

DIS@

10U_0402_6.3V6M

FB_A_EDC0 FB_A_EDC1 FB_A_EDC2 FB_A_EDC3

[25] FB_A_DBI0

D D

RV93

40.2_0402_1%

1 2

RV95

40.2_0402_1%

1 2

2

G

DIS@

13

D

QV8 L2N7002WT1G_SC-70-3

S

FB_A_CMD[0..15]

FB_A_CMD[16..31]

FB_A_D[0..63]

FB_A_EDC[7..0]

RV94

40.2_0402_1%

1 2

1

CV67

0.01U_0402_16V7K

2

RV96

40.2_0402_1%

1 2

1

CV68

0.01U_0402_16V7K

2

DIS@

+1.35VS_VRAM

12

RV97

DIS@

549_0402_1%

2

931_0402_1%RV981DIS@

1.33K_0402_1%

RV99

12

DIS@

+FBA_VREFC0

W=16mils

820P_0402_25V7

CV86

CV85

1

DIS@

2

[25] FB_A_CMD[0..15]

C C

[25] FB_A_CMD[16..31]

[25] FB_A_D[0..63]

[25] FB_A_EDC[7..0]

FB_A_CLK0 FB_A_CLK#0

Near to UV6

FB_A_CLK1 FB_A_CLK#1

Near to UV7

B B

[24] MEM_VREF

Place near pin J14 of each vram

[25] FB_A_DBI1 [25] FB_A_DBI2 [25] FB_A_DBI3

[25] FB_A_CLK0 [25] FB_A_CLK#0

RV87 RV89 RV91

[25] FB_A_WCK#0 [25] FB_A_WCK0

[25] FB_A_WCK#1 [25] FB_A_WCK1

+1.35VS_VRAM

2 2 2

FB_A_CLK0 FB_A_CLK#0 FB_A_CMD14

FB_A_CMD2 FB_A_CMD4 FB_A_CMD3 FB_A_CMD1

FB_A_CMD6 FB_A_CMD11 FB_A_CMD10 FB_A_CMD7 FB_A_CMD9

1 1 1

FB_A_CMD8 FB_A_CMD12 FB_A_CMD0 FB_A_CMD15 FB_A_CMD5

FB_A_WCK#0 FB_A_WCK0

FB_A_WCK#1 FB_A_WCK1

+FBA_VREFC0

FB_A_CMD13

+1.35VS_VRAM

1K_0402_1%DIS@ 1K_0402_1%DIS@ 121_0402_1%DIS@

2

DIS@

1

CV69

22U_0603_6.3V6M

DQ24 DQ0 DQ25 DQ1 DQ26 DQ2 DQ27 DQ3 DQ28 DQ4 DQ29 DQ5 DQ30 DQ6 DQ31 DQ7 DQ16 DQ8 DQ17 DQ9

DQ18 DQ10 DQ19 DQ11 DQ20 DQ12 DQ21 DQ13 DQ22 DQ14 DQ23 DQ15 DQ8 DQ16 DQ9 DQ17 DQ10 DQ18 DQ11 DQ19 DQ12 DQ20 DQ13 DQ21 DQ14 DQ22 DQ15 DQ23 DQ0 DQ24 DQ1 DQ25 DQ2 DQ26 DQ3 DQ27 DQ4 DQ28 DQ5 DQ29 DQ6 DQ30 DQ7 DQ31

K4G80325FB-HC03_FBGA170 ~D@

Near ballNear VRAM

1

2

1

CV72

DIS@

CV73

2

DIS@

10U_0402_6.3V6M

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

FB_A_D0

A4

FB_A_D1

A2

FB_A_D2

B4

FB_A_D3

B2

FB_A_D4

E4

FB_A_D5

E2

FB_A_D6

F4

FB_A_D7

F2

FB_A_D8

A11

FB_A_D9

A13

FB_A_D10

B11

FB_A_D11

B13

FB_A_D12

E11

FB_A_D13

E13

FB_A_D14

F11

FB_A_D15

F13

FB_A_D16

U11

FB_A_D17

U13

FB_A_D18

T11

FB_A_D19

T13

FB_A_D20

N11

FB_A_D21

N13

FB_A_D22

M11

FB_A_D23

M13

FB_A_D24

U4

FB_A_D25

U2

FB_A_D26

T4

FB_A_D27

T2

FB_A_D28

N4

FB_A_D29

N2

FB_A_D30

M4

FB_A_D31

M2

B1 D1 F1 M1 P1 T1 G2 L2 B3 D3 F3 H3 K3 M3 P3 T3 E5 N5 E10 N10 B12 D12 F12 H12 K12 M12 P12 T12 G13 L13 B14 D14 F14 M14 P14 T14

A1 C1 E1 N1 R1 U1 H2 K2 A3 C3 E3 N3 R3 U3 C4 R4 F5 M5 F10 M10 C11 R11 A12 C12 E12 N12 R12 U12 H13 K13 A14 C14 E14 N14 R14 U14

1

CV74

CV75

2

DIS@

10U_0402_6.3V6M

+1.35VS_VRAM

10U_0402_6.3V6M

BYTE0

BYTE1

[25] FB_A_DBI4 [25] FB_A_DBI5 [25] FB_A_DBI6 [25] FB_A_DBI7

[25] FB_A_CLK1 [25] FB_A_CLK#1

BYTE2

BYTE3

RV88 RV90 RV92

[25] FB_A_WCK#2 [25] FB_A_WCK2

[25] FB_A_WCK#3 [25] FB_A_WCK3

+1.35VS_VRAM

1

CV76

2

DIS@

10U_0402_6.3V6M

2 2 2

FB_A_EDC4 FB_A_EDC5 FB_A_EDC6 FB_A_EDC7

FB_A_CLK1 FB_A_CLK#1 FB_A_CMD30

FB_A_CMD18 FB_A_CMD20 FB_A_CMD19 FB_A_CMD17

FB_A_CMD22 FB_A_CMD27 FB_A_CMD26 FB_A_CMD23 FB_A_CMD25

1 1 1

FB_A_CMD24 FB_A_CMD28 FB_A_CMD16 FB_A_CMD31 FB_A_CMD21

FB_A_WCK#2 FB_A_WCK2

FB_A_WCK#3 FB_A_WCK3

+FBA_VREFC0

FB_A_CMD29

+1.35VS_VRAM

2

1

1K_0402_1%DIS@ 1K_0402_1%DIS@ 121_0402_1%DIS@

UV22

C2

EDC0 EDC3

C13

EDC1 EDC2

R13

EDC2 EDC1

R2

EDC3 EDC0

D2

DBI0# DBI3#

D13

DBI1# DBI2#

P13

DBI2# DBI1#

P2

DBI3# DBI0#

J12

CK

J11

CK#

J3

CKE#

H11

BA0/A2 BA2/A4

K10

BA1/A5 BA3/A3

K11

BA2/A4 BA0/A2

H10

BA3/A3 BA1/A5

K4

A8/A7 A10/A0

H5

A9/A1 A11/A6

H4

A10/A0 A8/A7

K5

A11/A6 A9/A1

J5

A12/RFU/NC

A5

VPP/NC

U5

VPP/NC

J1

MF

J10

SEN

J13

ZQ

J4

ABI#

G3

RAS# CAS#

G12

CS# WE#

L3

CAS# RAS#

L12

WE# CS#

D5

WCK01# WCK23#

D4

WCK01 WCK23

P5

WCK23# WCK01#

P4

WCK23 WCK01

A10

VREFD

U10

VREFD

J14

VREFC

J2

RESET#

H1

VSS

K1

VSS

B5

VSS

G5

VSS

L5

VSS

T5

VSS

B10

VSS

D10

VSS

G10

VSS

L10

VSS

P10

VSS

T10

VSS

H14

VSS

K14

VSS

G1

VDD

L1

VDD

G4

VDD

L4

VDD

C5

VDD

R5

VDD

C10

VDD

R10

VDD

D11

VDD

G11

VDD

L11

VDD

P11

VDD

G14

VDD

L14

VDD

SGRAM GDDR5

Near VRAM Near ball

2

DIS@

1

CV77

CV78

22U_0603_6.3V6M

MF=0

MF=0 MF=1 MF=0MF=1

170-BALL

K4G80325FB-HC03_FBGA170 ~D@

1

CV80

CV79

2

DIS@

10U_0402_6.3V6M

DQ24 DQ0 DQ25 DQ1 DQ26 DQ2 DQ27 DQ3 DQ28 DQ4 DQ29 DQ5 DQ30 DQ6 DQ31 DQ7 DQ16 DQ8 DQ17 DQ9

DQ18 DQ10 DQ19 DQ11 DQ20 DQ12 DQ21 DQ13 DQ22 DQ14 DQ23 DQ15 DQ8 DQ16 DQ9 DQ17 DQ10 DQ18 DQ11 DQ19 DQ12 DQ20 DQ13 DQ21 DQ14 DQ22 DQ15 DQ23 DQ0 DQ24 DQ1 DQ25 DQ2 DQ26 DQ3 DQ27 DQ4 DQ28 DQ5 DQ29 DQ6 DQ30 DQ7 DQ31

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

1

CV81

2

DIS@

10U_0402_6.3V6M

FB_A_D32

A4

FB_A_D33

A2

FB_A_D34

B4

FB_A_D35

B2 E4 E2 F4 F2 A11 A13 B11 B13 E11 E13 F11 F13 U11 U13 T11 T13 N11 N13 M11 M13 U4 U2 T4 T2 N4 N2 M4 M2

B1 D1 F1 M1 P1 T1 G2 L2 B3 D3 F3 H3 K3 M3 P3 T3 E5 N5 E10 N10 B12 D12 F12 H12 K12 M12 P12 T12 G13 L13 B14 D14 F14 M14 P14 T14

A1

VSSQ

C1

VSSQ

E1

VSSQ

N1

VSSQ

R1

VSSQ

U1

VSSQ

H2

VSSQ

K2

VSSQ

A3

VSSQ

C3

VSSQ

E3

VSSQ

N3

VSSQ

R3

VSSQ

U3

VSSQ

C4

VSSQ

R4

VSSQ

F5

VSSQ

M5

VSSQ

F10

VSSQ

M10

VSSQ

C11

VSSQ

R11

VSSQ

A12

VSSQ

C12

VSSQ

E12

VSSQ

N12

VSSQ

R12

VSSQ

U12

VSSQ

H13

VSSQ

K13

VSSQ

A14

VSSQ

C14

VSSQ

E14

VSSQ

N14

VSSQ

R14

VSSQ

U14

VSSQ

1

CV82

CV83

2

DIS@

10U_0402_6.3V6M

FB_A_D36 FB_A_D37 FB_A_D38 FB_A_D39 FB_A_D40 FB_A_D41 FB_A_D42 FB_A_D43 FB_A_D44 FB_A_D45 FB_A_D46 FB_A_D47 FB_A_D48 FB_A_D49 FB_A_D50 FB_A_D51 FB_A_D52 FB_A_D53 FB_A_D54 FB_A_D55 FB_A_D56 FB_A_D57 FB_A_D58 FB_A_D59 FB_A_D60 FB_A_D61 FB_A_D62 FB_A_D63

10U_0402_6.3V6M

+1.35VS_VRAM

1

CV84

2

DIS@

10U_0402_6.3V6M

BYTE4

BYTE5

BYTE6

BYTE7

+1.35VS_VRAM

Near ball

12

A A

5

12

4

12

DIS@

CV88

CV87

1U_0201_6.3V6M

12

DIS@

CV89

CV90

1U_0201_6.3V6M

12

DIS@

CV91

1U_0201_6.3V6M

12

DIS@

CV93

CV92

1U_0201_6.3V6M

12

DIS@

CV94

DIS@

CV96

CV95

1U_0201_6.3V6M

SSSeeecccuuurrriiitttyyy CCClllaaassssssiiifffiiicccaaatttiiiooonnn

IIIssussussueeeddd DDDaaattteee

TTTHHHIIISSS SSSHHHEEEEEETTT OOOFFF EEENNNGGGIIINNNEEEEEERRRIIINNNGGG DDDRRRAAAWWWIIINNNGGG IIISSS TTTHHHEEE PPPRRROOOPPPRRRIIIEEETTTAAARRRYYY PPPRRROOOPPPEEERRRTTTYYY OOOFFF CCCOOOMMMPPPAAALLL EEELLLEEECCCTTTRRROOONNNIIICCCSSS,,, IIINNNCCC... AAANNNDDD CCCOOONNNTTTAAAIIINNNSSS CCCOOONNNFFFIIIDDDEEENNNTTTIIIAAALLL AAANNNDDD TTTRRRAAADDDEEE SSSEEECCCRRREEETTT IIINNNFFFOOORRRMMMAAATTTIIIOOONNN... TTTHHHIIISSS SSSHHHEEEEEETTT MMMAAAYYY NNNOOOTTT BBBEEE TTTRRRAAANNNSSSFFFEEERRREEEDDD FFFRRROOOMMM TTTHHHEEE CCCUUUSSSTTTOOODDDYYY OOOFFF TTTHHHEEE CCCOOOMMMPPPEEETTTEEENNNTTT DDDIIIVVVIIISSSIIIOOONNN OOOFFF RRR&&&DDD DDDEEEPPPAAARRRTTTMMMEEENNNTTT EEEXXXCCCEEEPPPTTT AAASSS AAAUUUTTTHHHOOORRRIIIZZZEEEDDD BBBYYY CCCOOOMMMPPPAAALLL EEELLL EEECCCTTTRRROOONNNIIICCCSSS,,, IIINNNCCC... NNNEEEIIITTTHHHEEERRR TTTHHHIIISSS SSSHHHEEEEEETTT NNNOOORRR TTTHHHEEE IIINNNFFFOOORRRMMMAAATTTIIIOOONNN IIITTT CCCOOONNNTTTAAAIIINNNSSS

3

MMMAAAYYY BBBEEE UUUSSSEEEDDD BBBYYY OOORRR DDDIIISSSCCCLLLOOOSSSEEEDDD TTTOOO AAANNNYYY TTTHHHIIIRRRDDD PPPAAARRRTTTYYY WWWIIITTTHHHOOOUUUTTT PPPRRRIIIOOORRR WWWRRRIIITTTTTTEEENNN CCCOOONNNSSSEEENNNTTT OOOFFF CCCOOOMMMPPPAAALLL EEELLLEEECCCTTTRRROOONNNIIICCCSSS,,, IIINNNCCC...

222000111888///000444///000999 222000111999///000444///000999

2

+1.35VS_VRAM

12

DIS@

CV97

1U_0201_6.3V6M

CCCooommmpppaaalll SSSeeecccrrr eeettt DDDaaatttaaa

DDDeeecicicippphhheeerrreeeddd DDDaaattteee

Near ball

12

DIS@

CV98

1U_0201_6.3V6M

12

DIS@

CV99

1U_0201_6.3V6M

12

DIS@

CV101

CV100

1U_0201_6.3V6M

12

DIS@

CV102

CV103

1U_0201_6.3V6M

TTTiiitttllleee

NNN111666PPP___GGGDDDDDDR5R5R5___AAA

SSSiiizzzeee

DDDooocccuuummmeeennnttt NNNuuummmbbbeeerrr RRReee vvv

DaDaDattteee::: SSShhheeeeeettt ooofff

12

DIS@

CV104

DIS@

CV106

CV105

1U_0201_6.3V6M

CCCooommmpppaaalll ElElEleeeccctttrrrooonnniiicccsss,,, IIInnnccc...

LA-H101PLA-H101PLA-H101P

1

222777 555333MMMooo nnndddaaayyy,,, OOOccctttooobbbeeerrr 222222,,, 222000111888

0.A0.A0.A

5

4

3

2

L C D POWER SWITCH CAMERA POWER CIRCUIT

1

+3VS +LCDVDD_CONN

12

C4 1U_0201_6.3V6M

SE00000UC00

W=60mils

PCH_ENVDD<6>

R4

100K_0402_5%

D D

DISPLAY OFF

C C

Through E C

BKOFF#<34>

eDP CONNECTOR

B+ +LEDVDD

1 2

R9 0_0805_5%

B B

eDP

Touch Screen

Camera

G-Sensor

A A

DMIC

TS_DISABLE#<34>

+3VS_CMOS

5

USB20_N4<12>

TS_I2C_RST#<6> TS_INT#<11> I2C1_SDA_TS<11> I2C1_SCL_TS<11>

EC_SMB_DA4<34,36> EC_SMB_CK4<34,36>

EDP_AUXN<6> EDP_AUXP<6>

EDP_TXP0<6> EDP_TXN0<6>

EDP_TXP1<6> EDP_TXN1<6>

USB20_P4<12>

+3VS_TS

TAB_SW#<34>

DMIC_CLK<33> DMIC_DAT<33>

+3VALW

+3VS

1

C7

4.7U_0805_25V6-K

2

+LCDVDD_CONN

W=20mils

@

R330 0_0201_5%S340@ R331 0_0201_5%S340@

R332 0_0201_5%C340@ R333 0_0201_5%C340@

U5

5

OUT

IN

GND

4

OC

EN

EM5203AJ-20 SOT23 5P

SA00008R900

12

1 2

R5 0_0402_5%

IN V P W M<6>

W=60mils

1 2

C8 0.1U_0201_10VK X5 R

1 2

C9 0.1U_0201_10VK X5 R

1 2

C10 0.1U_0201_10VK X5 R

1 2

C11 0.1U_0201_10VK X5 R

1 2

C12 0.1U_0201_10VK X5 R

1 2

C13 0.1U_0201_10VK X5 R

1 2 1 2

USB20_N6<12> USB20_P6<12>

1

+LCDVDD

2

3

1 2

R2 0_0805_5%

W=60mils

1

C3

4.7U_0402_6.3V6M

2

HOT PLUG DETECT

DISPOFF#

R7

100K_0402_5%

1 2

T o u c h Screen POWER CIRCUIT

JEDP1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

CVILU_CVS3402M1RM-NH

ME@

SP01002FV00

GND GND GND GND GND

41 42 43 44 45

Security Classificat ion

Is s u ed Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I N C . AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I N C . AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETEN T D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETEN T D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETEN T D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, IN C . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, IN C . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, IN C . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED B Y OR DISCLOSED TO AN Y THIRD P A R T Y WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C .

MAY BE USED B Y OR DISCLOSED TO AN Y THIRD P A R T Y WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C .

3

4

DISPOFF# EDP_HPD_R

EDP_AUXN_C EDP_AUXP_C

EDP_TXP0_C EDP_TXN0_C

EDP_TXP1_C EDP_TXN1_C

USB20_N4_R USB20_P4_R

+3VS

W=20mils near JEDP1.32

EDP_HPD<6>

100K_0402_5%

+3VS

R264 0_0603_5%

Compal S ecret Data

2018/09/21 2019/09/21

Compal S ecret Data

Deciphered Date

2

12

R8

1 2

R6 0_0402_5%

1 2

1

C5

0.1U_0201_10V KX 5R

2

EDP_HPD_R

+3VS_TS

W=20milsW=20mils

1

TS@

C230

0.1U_0201_10V KX 5R

2

Tit le

Size Document Number Rev

Custom

Date: Sheet

1

C231

@

10U_0402_6.3V6M

SE00000UD00

2

Compal Electronics, Inc.

eDP / Camera / MIC

LA-H101P

1

28 51Thursday, September 20, 2018

of

0.A0.A0.A

5

4

3

2

1

+3VS

12

RLS1

LS@

4.7K_0402_5%

DDCBUF

12

D D

RLS3

@

4.7K_0402_5%

0.01U_0201_6.3V7K

CLS1

LS@

0.01U_0201_6.3V7K

CLS2

2

1

LS@

0.1U_0201_10V6K

CLS3

2

1

LS@

0.1U_0201_10V6K

2

1

Near ULS1

+3VS

12

RLS4

@

4.7K_0402_5%

EQ

12

RLS5

@

4.7K_0402_5%

C C

+3VS

12

RLS9

@

4.7K_0402_5%

I2C_CTL_EN_LS

12

RLS10

@

4.7K_0402_5%

FromCPU

CPU_DP2_P2<6> CPU_DP2_N2<6>

CPU_DP2_P1<6> CPU_DP2_N1<6>

CPU_DP2_P0<6> CPU_DP2_N0<6>

CPU_DP2_P3<6> CPU_DP2_N3<6>

CLS13 0.1U_0201_10V6KLS@ CLS14 0.1U_0201_10V6KLS@

CLS11 0.1U_0201_10V6KLS@ CLS12 0.1U_0201_10V6KLS@

CLS7 0.1U_0201_10V6KLS@ CLS10 0.1U_0201_10V6KLS@

CLS15 0.1U_0201_10V6KLS@ CLS16 0.1U_0201_10V6KLS@

+3VS

RLS6 4.7K_0402_5%LS@

RLS7 4.99K_0402_1%LS@

RLS8 4.7K_0402_5%@

CLS4

LS@

2

1

1 1

1 2

Near Pin19Near Pin31Near Pin40Near Pin12Near Pin20

0.1U_0201_10V6K

CLS5

2

LS@

1

2 2

+1.2V_HDMI

CLS6

2

LS@

1

HDMI_TX0+_C HDMI_TX0-_C

HDMI_TX1+_C HDMI_TX1-_C

HDMI_TX2+_C HDMI_TX2-_C

HDMI_CLK+_C CPU_DP2_CTRL_DATA HDMI_CLK-_C

DDCBUF

EQ ISET I2C_CTL_EN_LS

PRE

+1.2V +1.2V_HDMI

W = 40mils

RLS2

12

0_0603_5%

LS@

ULS1

LS@

19

VDDTA

20

VDDTX

31

VDDTX

12

VDDRX

40

VDDRX

1

IN_D2p

2

IN_D2n

4

IN_D1p

5

IN_D1n

6

IN_D0p

7

IN_D0n

9

IN_CKp

10

IN_CKn

14

DDCBUF/SDA_CTL

13

DCIN_EN/SCL_CTL

17

EQ/I2C_ADDR0

8

I2C_CTL_EN

18

REX T

36

PD#

23

CFG / I2C_ADDR1

16

PRE

PS8407ATQFN40GTR2A1_TQFN40_5X5

SDA_SRC

SDA_SNK

HPD_SRC

HPD_SNK

VDD33 VDD33

OUT_D2p OUT_D2n

OUT_D1p OUT_D1n

OUT_D0p OUT_D0n

OUT_CKp OUT_CKn

SCL_SRC

SCL_SNK

ISET

GND GND

EPAD

11 37

30 29

27 26

25 24

22 21

39 38 33 32

3 34 28

15 35 41

HDMI_LS_TX_P0 HDMI_LS_TX_N0

HDMI_LS_TX_P1 HDMI_LS_TX_N1

HDMI_LS_TX_P2 HDMI_LS_TX_N2

HDMI_LS_CLKP HDMI_LS_CLKN

CPU_DP2_CTRL_CLK DDC_SDA_HDMI_R DDC_SCL_HDMI_R

CPU_DP2_HPD

HDMI_HPD

HDMI_LS_TX_P0 <30> HDMI_LS_TX_N0 <30>

HDMI_LS_TX_P1 <30> HDMI_LS_TX_N1 <30>

HDMI_LS_TX_P2 <30> HDMI_LS_TX_N2 <30>

HDMI_LS_CLKP <30> HDMI_LS_CLKN <30>

CPU_DP2_CTRL_DATA <6,30> CPU_DP2_CTRL_CLK <6,30>

1 2

RLS15 0_0201_5%LS@

1 2

RLS16 0_0201_5%LS@

CPU_DP2_HPD <6,30>

HDMI_HPD <30>

T o HDMI

FromCPU

HDMI_CTRL_DAT <30> HDMI_CTRL_CLK <30>

T o CPU

FromHDMI

+3VS

Near Pin11 Near Pin37

0.01U_0201_6.3V7K

CLS8

2

LS@

1

0.1U_0201_10V6K

CLS9

2

LS@

1

T o HDMI

F o r NoLS only

@

+3VS

12

+3VS

12

RLS33

4.7K_0402_5%

PRE

RLS34

4.7K_0402_5%

RLS35

4.7K_0402_5%

ISET

RLS36

4.7K_0402_5%

Fo r NoLS Near CLS9 ~ CLS16

CPU_DP2_P0 CPU_DP2_N0 CPU_DP2_P1 CPU_DP2_N1

CPU_DP2_P2 CPU_DP2_N2 CPU_DP2_P3 CPU_DP2_N3

5

1 2

RLS17 0_0201_5%NOLS@

1 2

RLS18 0_0201_5%NOLS@

1 2

RLS19 0_0201_5%NOLS@

1 2

RLS20 0_0201_5%NOLS@

1 2

RLS25 0_0201_5%NOLS@

1 2

RLS26 0_0201_5%NOLS@

1 2

RLS27 0_0201_5%NOLS@

1 2

RLS28 0_0201_5%NOLS@

HDMI_TX2+_R HDMI_TX2-_R HDMI_TX1+_R HDMI_TX1-_R

HDMI_TX0+_R HDMI_TX0-_R HDMI_CLK+_R HDMI_CLK-_R

4

Fo r NoLS Near ULS1 pin21~30

1 2

RLS21 0_0201_5%NOLS@

1 2

RLS22 0_0201_5%NOLS@

1 2

RLS23 0_0201_5%NOLS@

1 2

RLS24 0_0201_5%NOLS@

1 2

RLS29 0_0201_5%NOLS@

1 2

RLS30 0_0201_5%NOLS@

1 2

RLS31 0_0201_5%NOLS@

1 2

RLS32 0_0201_5%NOLS@

Security Classification

THI S SHEET OF ENGINEERIN G DRAWING IS TH E PROPRI ETARY PR OPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

THI S SHEET OF ENGINEERIN G DRAWING IS TH E PROPRI ETARY PR OPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET I NFORMATION.T HIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COM PETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION.T HIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COM PETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION.T HIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COM PETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEE T NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEE T NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEE T NOR T HE INFORMATION IT CONTAINS MAYBE USED B Y OR DISCLOSED TO ANY THIRD P A R T Y WITHOUTPRIO R WRITTEN CONSENT OF COM PAL ELECTRONICS, INC.

MAYBE USED B Y OR DISCLOSED TO ANY THIRD P A R T Y WITHOUTPRIO R WRITTEN CONSENT OF COM PAL ELECTRONICS, INC.

Issued Date

HDMI_LS_TX_P2 HDMI_LS_TX_N2 HDMI_LS_TX_P1 HDMI_LS_TX_N1

HDMI_LS_TX_P0 HDMI_LS_TX_N0 HDMI_LS_CLKP HDMI_LS_CLKN

Compal Secret Data

2018/09/21 2019/09/21

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

HDMI Level shifter_PS8407A

LA-H101P

29 51Thursday, September 20, 2018

1

o f

0.A0.A0.A

B B

A A

5

4

3

2

1

HDMI

1 2

HDMI_LS_CLKP<29>

HDMI_LS_CLKN

<29>

D D

HDMI_LS_TX_P0< 29>

HDMI_LS_TX_N0<29>

HDMI_LS_TX_P1< 29>

HDMI_LS_TX_N1<29>

HDMI_LS_TX_P2< 29>

C C

HDMI_LS_TX_N2<29>

B B

CH1 0.1U_0201_10V KX 5R

1 2

CH2 0.1U_0201_10V KX 5R

1 2

CH3 0.1U_0201_10V KX 5R

1 2

CH4 0.1U_0201_10V KX 5R

1 2

CH7 0.1U_0201_10V KX 5R

1 2

CH8 0.1U_0201_10V KX 5R

1 2

CH9 0.1U_0201_10V KX 5R

1 2

CH10 0.1U_0201_10V K X5R

LS@

CH1

SD043000080

0_0201_5%

LS@

CH3

SD043000080

0_0201_5%

LS@

CH7

SD043000080

0_0201_5%

LS@

CH9

SD043000080

0_0201_5%

LS@

CH2

SD043000080

0_0201_5%

LS@

CH4

SD043000080

0_0201_5%

LS@

CH8

SD043000080

0_0201_5%

LS@

CH10

SD043000080

0_0201_5%

NOLS@

HDMI_CLKP

HDMI_CLKN

HDMI_TX_P0

HDMI_TX_N0

HDMI_TX_P1

HDMI_TX_N1

HDMI_TX_P2

HDMI_TX_N2

RH14 470_0201_5%NOLS@ RH15 470_0201_5%NOLS@ RH17 470_0201_5%NOLS@ RH18 470_0201_5%NOLS@

RH19 470_0201_5%NOLS@ RH20 470_0201_5%NOLS@ RH21 470_0201_5%NOLS@ RH22 470_0201_5%NOLS@

1 2 1 2 1 2 1 2

EMI

RH1 8.2_0402_1%EMI@

RH3 8.2_0402_1%EMI@

RH7 8.2_0402_1%EMI@

RH8 8.2_0402_1%EMI@

RH9 8.2_0402_1%EMI@

RH10 8.2_0402_1%EMI@

RH11 8.2_0402_1%EMI@

RH12 8.2_0402_1%EMI@

1 2

Near JHDMI1

34

D

S

HDMI_L_CLKP

HDMI_L_CLKN

HDMI_L_TX_P0

HDMI_L_TX_N0

HDMI_L_TX_P1

HDMI_L_TX_N1

HDMI_L_TX_P2

HDMI_L_TX_N2

+3VS

5

G

NOLS@

2N7002KDW_SOT363-6 QH1B

HDMI_L_CLKP HDMI_L_CLKN

HDMI_L_TX_P0 HDMI_L_TX_N0

HDMI_L_TX_P1 HDMI_L_TX_N1

HDMI_L_TX_P2 HDMI_L_TX_N2

EMI

1 2

RH2 150_0402_5%EMI@

1 2

RH4 150_0402_5%EMI@

1 2

RH5 150_0402_5%EMI@

1 2

RH6

CPU_DP2_HPD<6,29>

RH13

1M_0402_5%

NOLS@

2N7002KDW_SOT363-6

150_0402_5%EMI@

0.1U_0201_10V KX 5R

HDMI_HPD<29>

+3VS

12

G

2

NOLS@

S

61

D

QH1A

12

RH16 20K_0402_5%

@

CH6

HDMI_HPD

+5VS

1

2

Fo r HDMI

UH1

1

IN

S IC AP2330W-7 SC59 3PPWR SW

SA00004ZA00

+5V_Display

HDMI_CTRL_DAT HDMI_CTRL_CLK

HDMI_L_CLKN

HDMI_L_CLKP HDMI_L_TX_N0

HDMI_L_TX_P0 HDMI_L_TX_N1

HDMI_L_TX_P1 HDMI_L_TX_N2

HDMI_L_TX_P2

OUT

GND

3

2

+5V_Display

W=40mils

JHDMI1

19

HP_ DET

18

+5V

17

DDC/CEC_GND

16

SDA

15

SCL

14

Reserved

13

CEC

12

CK-

11

CK_shield

GND

10

CK+

GND

9

D0-

GND

8

D0_shield

GND

7

D0+

6

D1-

5

D1_shield

4

D1+

3

D2-

2

D2_shield

1

D2+

LOTES_AHDM0064-P001A

DC232007B00

ME@

1

CH5

0.1U_0201_10V KX 5R

2

23 22 21 20

+3VS+3VS +5V_Display

2.2K_0402_5%

12

NOLS@

RH23

RH24

CPU_DP2_CTRL_CLK<6,29>

CPU_DP2_CTRL_DATA<6,29>

A A

CPU_DP2_CTRL_CLK CPU_DP2_CTRL_DATA HDMI_CTRL_CLK HDMI_CTRL_DAT

1

CH11 10P_0402_50V8J

2

@RF@

5

3

4

QH2B 2N7002KDW 2N SC88-6

SB00000EO00

1

CH12 10P_0402_50V8J

2

@RF@

QH2A 2N7002KDW 2N SC88-6

2

SB00000EO00

61

NOLS@

1

CH13 10P_0402_50V8J

2

@RF@

2.2K_0402_5%

12

RH25

4

RH26

HDMI_CTRL_CLK

HDMI_CTRL_DAT

1

CH14 10P_0402_50V8J

2

@RF@

HDMI_CTRL_CLK <29>

HDMI_CTRL_DAT <29>

DH1

HDMI_CTRL_DAT HDMI_CTRL_DAT

HDMI_CTRL_CLK HDMI_CTRL_CLK

HDMI_HPD HDMI_HPD

+5V_Display +5V_Display

@ESD@

Is s u ed Date

1

2

4

5

3

8

9

10

8

9

7

6

L05ESDL5V0NA-4 SLP2510P8ESD

Security Classificat ion

THIS SHEET OF ENGINEERING DRAWING IS THE PROPR IETARY PROPERTY OF COMPAL ELECTRONICS, IN C . AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPR IETARY PROPERTY OF COMPAL ELECTRONICS, IN C . AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFOR MATION. THIS SHEET M AY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D

AND TRADE SECRET INFOR MATION. THIS SHEET M AY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D

AND TRADE SECRET INFOR MATION. THIS SHEET M AY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, IN C . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, IN C . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, IN C . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY O R DISCLOSED TO ANY THIRD P A R T Y WITHOUTPRIOR W RITTEN CONSENT O F COMPAL ELECTRONICS, IN C .

MAY BE USED BY O R DISCLOSED TO ANY THIRD P A R T Y WITHOUTPRIOR W RITTEN CONSENT O F COMPAL ELECTRONICS, IN C .

3

DH2

@ESD@

9

10

8

HDMI_L_TX_N2

HDMI_L_TX_P2

2018/09/21 2019/09/21

9

7

6

L05ESDL5V0NA-4 SLP2510P8ESD

Compal S ecret Data

Deciphered Date

2

HDMI_L_TX_N1HDMI_L_TX_N1

1

HDMI_L_TX_P1HDMI_L_TX_P1

2

HDMI_L_TX_N2

4

HDMI_L_TX_P2

5

3

8

DH3

@ESD@

9

10

8

9

7

6

L05ESDL5V0NA-4 SLP2510P8 ESD

Compal Electronics, Inc.

Tit le

Size Document Number Rev

Custom

Date: Sheet

HDMI

LA-H101P

HDMI_L_CLKPHDMI_L_CLKP

1

HDMI_L_CLKNHDMI_L_CLKN

2

HDMI_L_TX_P0HDMI_L_TX_P0

4

HDMI_L_TX_N0HDMI_L_TX_N0

5

3

8

30 51Thursday, September 20, 2018

of

1

of

0.A0.A0.A

A

B

C

D

E

NGFF WLAN /BT(Key E)

+3VALW +3VS_WLAN

1 1

1

CW1

4.7U_0402_6.3V6M

2

CNVi@

1

2

CW2

CNVi@

0.1U_0201_10V6K

+3VS_WLAN

1

CW3

0.01U_0402_16V7K

CNVi@

2

Close to KEY E pin72,74

+3VS_WLAN

1

CW4

4.7U_0402_6.3V6M

2

CNVi@

1

CW5

0.1U_0201_10V6K

CNVi@

2

Close to KE Y E pin2,4

Jefferson Peak:1360mA@peak current

2 2

Thunder_Peak_2:1100mA@peak current

1

CW6

2

CNVi@

0.01U_0402_16V7K

NGFF Wireless LAN / BT (Key E) [PCIE+USB/CNVi]

+3VALW

1U_0201_6.3V6M

CW61

12

CNVi@

CNVi_PWR_EN#_R

+3VS_WLAN

UW1

5

IN

4

EN(EN#)

G524B2T11U_SOT23-5

SA00007BW00 CNVi@

I (Max) : 2.0 A(+3VS_WLAN) RDS(Typ) : 70 mohm V drop : 0.14 V

1

OUT

2

GND

3

OC#

Imax : 2.0 AImax : 2.0 A

+3VS_WLAN

CNVi_PWR_EN#<34>

W=20mils

CNVi@

1 2

RW41 0_0402_5%

CNVi_PWR_EN#_R

422.18mA

QW10

S

G

2

1

2

@

D

13

PJ2301_SOT23-3

0.1U_0201_10V6K

CW9 1U_0201_6.3V6M

CNVi@

CNVi_PWR_EN#_R

W=20mils

1

CW10

2

@

2

G

1

CW11 10U_0402_6.3V6M

2

+3VS_W LAN

12

13

D

S

@

RW60 100_0402_1%

@

QW11 2N7002KW_SOT323-3

@

LED1#

PCM_IN

LED2#

GND_18

COE X3 COE X2 COE X1

I2C_DAT I2C_CLK

I2C_IRQ

GND1

+3VS_W LAN

2 4

+3P3A

6

LED#1

8

PCM_CL K

10

RF_RESET_B

12

PCM_IN

14

CLKREQ0

16

LED2#

18

GND/ LNA_ EN

20

UAR T WA K E#

22

BRI_RSP

24

RGI_DT

26

RGI_RSP

28

BRI_DT

30

Clink RE SET

32

Clink DAT A

34

Clink CLK

36

COEX3

38

COEX_RXD

40

COEX_TXD

42

C_P32K

44

PERST0#

46

W_DISABLE2#

48

W_DISABLE1#

50

A4WP_I2C_DATA

52

A4WP_I2C_CLK

54

A4WP _IR Q#

56

REFCL K0

58

PERST1#

60

CLKREQ1#

62

PEWake1#

64

+3P 3A

66

+3P 3A

68

GND

CNV_RF_RESET#_R

CLKREQ_CNV#_R

CNV_BR I_CRX_R_ DTX

CNV_RGI_CTX_R_DRX CNV_RGI_CRX_R_DTX CNV_BRI_CTX_R_DRX

CLKIN_XTAL

1 2

RW4 33_0201_5%CNVi@

1 2

RW6 33_0201_5%CNVi@

1 2

RW9 0_0201_5%@

1 2

RW11 22_0402_5%CNVi@

1 2

RW13 0_0201_5%@

1 2

RW14 33_0402_5%CNVi@

1 2

RW15 22_0402_5%CNVi@

1 2

RW16 33_0402_5%CNVi@

WLBT_OFF# WL_OFF#

EC_TX <34>

EC_RX <34>

CNV_RF_RESET# <9>

CLKREQ_CNV# <9>

UART0_RX <11> CNV_BRI_CRX_DTX <11>

UART0_TX <11>

CNV_RGI_CTX_DRX <11>

CNV_RGI_CRX_DTX <11>

CNV_BRI_CTX_DRX <11>

SUSCLK <10>

PCI_RST# <10,32,34,37>

WLBT_OFF# <9>

WL_OFF# <12>

CLKIN_XTAL <10>

+3VS_W LAN

1 2

RW58 10K_0402_5%@

1 2

RW59 10K_0402_5%@

1 2

RW61 10K_0402_5%@

WLBT_OFF#

WL_OFF#

CLKREQ_PCIE#3_R

CNViModule PIN Def i ne

JWLAN1

1

GND +3P3A

GND_1

3

USB_D+

USB _D +

5

USB_D-

USB _D -

7

GND

GND_7

9

WGR_D1N WGR_D1 P

WGR_D0N WGR_D0P

WGR_CLKN WGR_CLKP

SDIO_CLK

11

SDIO_CMD

13

GND

SDIO_DAT0

15

SDIO_DAT1

17

SDIO_DAT2

19

GND

SDIO_DAT3

21

SDIO_WAKE

23

SDIO_RST

25

GND

GND_33

27

PETp0

PET_RX_P0

29

PETn0

PET_RX_N0

31

GND

GND_39

33

PERp0

PER_TX_P0

35

PERn0

PER_TX_N0

37

GND

GND_45

39

REFCL KP0

REFCLK_P0

41

REFCLK N0

REFCLK_N0

43

GND

GND_51

45

CLKREQ0#

47

PEWake0#

PEWAKE0#

49

GND

GND_57

51

WT_D1N

RSVD/PCIE_RX_P1

53

WT_D1P

RSVD/PCIE_RX_N1

55

GND

GND_63

57

WT_D0N

RSVD/PCIE_TX_P1

59

WT_D0P

RSVD/PCIE_TX_N1

61

GND

GND_69

63

WT_CLKN

RSV D_ 71

65

WT_CLKP

RSV D_ 73

67

GND

GND_75

69

GND

GND2

BELLW_80152-3221

SP070013E00 ME@

Note: The real behavior of BT_DISABLE are BT _D I SA BL E =L OW, BT= O FF

BT _D I S A B L E = H I G H , BT =O N

PCIE_CTX_DRX_P11<12> PCIE_CTX_DRX_N11<12>

PCIE_CRX_DTX_P11<12> PCIE_CRX_DTX_N11< 12>

CLK_PCIE_P3<10>

CLK_PCIE_N3<10>

CLKREQ_PCIE#3<10>

PCIE_WAKE#<34>

USB20_P10< 12> USB20_N10<12>

CNV_CRX_DTX_N1 CNV_CRX_DTX_P1

CNV_CRX_DTX_N0 CNV_CRX_DTX_P0

CLK_C NV_CRX_D TX_N CLK_C NV_CRX_D TX_P

CNV_CTX_DRX_N1 CNV_CTX_DRX_P1

CNV_CTX_DRX_N0 CNV_CTX_DRX_P0

CLK_CNV_CTX_DRX_N CLK_CNV_CTX_DRX_P

Near JWLAN1

CC82 CC83

1 2

RWL1 0_0402_5%

1 2

RWL2 0_0402_5%@

0.1U_0201_10V6K

1 2

0.1U_0201_10V6K

1 2

PCIE_CTX_C_DRX_P11 PCIE_CTX_C_DRX_N11

CLKREQ_PCIE#3_R WAKE#_R

BT

CNV_CRX_DTX_N1<9>

CNV_CR X_DTX_P 1<9>

CNV_CRX_DTX_N0<9>

CNV_CR X_DTX_P 0<9>

CLK_CNV_CRX_DTX_N<9> CLK_CNV_CRX_DTX_P<9>

WLAN

3 3

CNV_CTX_DRX_N1<9> CNV_CTX_DRX_P1<9>

CNV_CTX_DRX_N0<9> CNV_CTX_DRX_P0<9>

CLK_CNV_CTX_DRX_N<9> CLK_CNV_CTX_DRX_P<9>

The connectivity module power supply pin shall be connected directly to thr rail DSW. From 567240_Intel_Wireless_AC_9560_Jefferson_Peak_EPS_Rev1.1

3.3VAUX_2

3.3VAUX_4

PCM_CLK

PCM_SYNC

PCM_OUT

UAR T_W A KE

UAR T_T X

UART_RX UART_RTS UART_CTS

CLink_RST

CLink_DATA

CLink_CLK

SUSCLK(32KHz)

PERST0#

W_DISABLE2# W_DISABLE1#

RSV D_6 4 RSV D_6 6 RSV D_6 8 RSV D_7 0

3.3VAUX_72

3.3VAUX_74

PCH EDS : M.2 CNV Mode Select

GPP_F6/CNV_RGI_DT

0 = Integrated CNVi enable.

1 = Integrated CNVi disable.

4 4

A

CNV_RGI_CTX_R_DRX

CNV_BRI_CTX_R_DRX

RW156 20K_0201_5%CNVi@

RW157 20K_0201_5%@

1 2

12

RW26100K_0402_5%

RW2771.5K_0402_1% CNVi@

B

EC_TX

CLKREQ_CNV#

+1.8VALW

Security Classificat ion

Is s u ed Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I N C . AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I N C . AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETEN T D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETEN T D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETEN T D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, IN C . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, IN C . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, IN C . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED B Y OR DISCLOSED TO AN Y THIRD P A R T Y WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C .

MAY BE USED B Y OR DISCLOSED TO AN Y THIRD P A R T Y WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C .

C

2018/09/21 2019/09/21

Compal S ecret Data

Deciphered Date

D

Compal Electronics, Inc.

Tit le

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

NGFF WLAN / BT

LA-H101P

E

31 51Thursday, September 20, 2018

of

0.A0.A0.A

5

SSD(TYPE M)

D D

SSD PCIE

SSD SATA

C C

0.01U_0402_16V7K

0.1U_0201_10V6K

C18

1

2

PCIE_CRX_DTX_N13<12> PCIE_CRX_DTX_P13<12>

PCIE_CTX_DRX_N13<12> PCIE_CTX_DRX_P13<12>

PCIE_CRX_DTX_N14<12> PCIE_CRX_DTX_P14<12>

PCIE_CTX_DRX_N14<12> PCIE_CTX_DRX_P14<12>

PCIE_CRX_DTX_N15<12> PCIE_CRX_DTX_P15<12>

PCIE_CTX_DRX_N15< 12> PCIE_CTX_DRX_P15<12>

SATA_CR X_DTX_P 2<12> SATA_CR X_DTX_N 2<12>

SATA_CT X_DRX_N 2<12> SATA_CT X_DRX_P 2<12>

CLK_PCIE_N1<10> CLK_PCIE_P1<10>

C19

1

2

CC84 0.22U_0402_6.3V6K CC85 0.22U_0402_6.3V6K

CC86 0.22U_0402_6.3V6K CC87 0.22U_0402_6.3V6K

CC88 0.22U_0402_6.3V6K CC89 0.22U_0402_6.3V6K

CC90 0.22U_0402_6.3V6K CC91 0.22U_0402_6.3V6K

4

+3VS_SSD

10U_0402_6.3V6M

1

C20

@

2

1 2 1 2

C21

NGFF_SSD_PEDET#

PCIE_CTX_C_DRX_N13 PCIE_CTX_C_DRX_P13

PCIE_CTX_C_DRX_N14 PCIE_CTX_C_DRX_P14

PCIE_CTX_C_DRX_N15 PCIE_CTX_C_DRX_P15

SATA_CTX_C_DRX_N2 SATA_CTX_C_DRX_P2

3

+3VS

JSSD1

1

GND

3

GND

5

PERn3

7

PERp3

9

GND

11

PETn3

13

PETp3

15

GND

17

PERn2

19

PERp2

21

GND

23

PETn2

25

PETp2

27

GND

29

PERn1

31

PERp1

33

GND

35

PETn1

37

PETp1

39

GND

41

PERn0/SATA-B+

43

PERp0/SATA-B-

45

GND

47

PETn0/SATA-A-

49

PETp0/SATA-A+

51

GND

53

REF CL KN

55

REF CL KP

57

GND

59

NC PEDET(NC-PCIE /GND-SATA)613P3VAUX

63

GND

65

GND

67

GND

BELLW_80159-3221

SP070018L00 ME@

SUSCLK(32kHz)

R10

1 2

0_0805_5%

3P3VAUX 3P3VAUX

DAS/DSS#

3P3VAUX 3P3VAUX 3P3VAUX 3P3VAUX

DEV SL P

PERST#

CLKREQ#

PEWake#

3P3VAUX 3P3VAUX

GND1 GND2

2

+3VS_SSD

1 2

2 4 6

NC

8

NC

10 12 14 16 18 20

NC

22

NC

24

NC

26

NC

28

NC

30

NC

32

NC

34

NC

36

NC

38 40

NC

42

NC

44

NC

46

NC

48

NC

50 52 54 56

NC

58

NC

60 62 64 66

68 69

DEVSLP2 <12>

PCI_RST# <10,31,34,37>

CLKREQ_PCIE#1 <10>

NGFF_SSD_PEDET#

R12 10K_0402_5%

1 2

R11 0_0402_5%@

2

G

NGFF_SSD_PEDET#

H : PCIE Interface L : SATA Interface Fe l l ow 543016_SKL_U_Y_PDG_0_9

13

D

Q1

2N7002KW_SOT323-3

S

SB000009Q80

1

NGFF_SSD_PEDET <12>

S A TA HDD

Deciphered Date

2

SATA HDD Conn.

JHDD1

1

GND

2

A+

3

A-

4

GND

5

B-

6

B+

7

GND

8

V33

9

V33

10

V33

11

GND

12

GND

13

GND

14

V5

15

V5

16

V5

17

GND

18

Reserved

19

GND

20

V12

21

V12

GND

V1222GND

SDAN_603006-022041

DC01000CE00

ME@

24 23

Compal Electronics, Inc.

Tit le

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SSD/HDD

LA-H101P

1

32 51Thursday, September 20, 2018

0.A0.A0.A

of

For Power consumption Measurement

B B

A A

5

580mA

1 2

RHD5 0_0805_5%

+5VS_HDD+5VS

1 2

SATA_CTX_DRX_P1<12> SATA_CTX_DRX_N1<12>

SATA_CRX_DTX_N1<12>

0.1U_0201_10V6K

10U_0402_6.3V6M

CHD6

CHD5

1

2

4

SATA_CRX_DTX_P1<12>

CHD9 0.01U_0402_16V7K

1 2

CHD11 0.01U_0402_16V7K

1 2

CHD13 0.01U_0402_16V7K

1 2

CHD15 0.01U_0402_16V7K

Security Classificat ion

Is s u ed Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I N C . AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I N C . AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETEN T D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETEN T D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETEN T D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, IN C . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, IN C . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, IN C . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED B Y OR DISCLOSED TO AN Y THIRD P A R T Y WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C .

MAY BE USED B Y OR DISCLOSED TO AN Y THIRD P A R T Y WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C .

3

SATA_CTX_C_DRX_P1 SATA_CTX_C_DRX_N1

SATA_CRX_C_DTX_N1 SATA_CRX_C_DTX_P1

+5VS_HDD

Compal S ecret Data

2018/09/21 2019/09/21

Compal S ecret Data

A

B

C

D

E

ALC3287

UA1

6

I2C_DATA

7

HDA_SYNC_R<9>

@EMI@

1 1

DMIC_DAT<28>

DMIC_CLK<28>

EC_MUTE#<34>

2 2

wide 40MIL

CA1 22P_0402_50V8J

HDA_BIT_CLK_R<9>

<9>

HDA_SDOUT_R

<9>

HDA_SDIN0

1 2

RA7 BLM15PX221SN1D_2PEMI@

1 2

RA8 0_0402_5%

GNDA GNDAGNDA GNDA

EXT_MIC_SLEEVE

EXT_MIC_RING2

GNDA

@EMI@

12

RA4 33_0402_5%

HDA_SDIN0_R

1 2

RA2

33_0402_5%

DMIC_DAT

DMIC_CLK_R

PDB

PLUG_IN

1 2

CA7 2.2U_0402_6.3V6M

1 2

CA8 2.2U_0402_6.3V6M

1 2

CA9 2.2U_0402_6.3V6M

1 2

RA10 2.2K_0402_5%

1 2

RA11 2.2K_0402_5%

1 2

CA10 1U_0201_6.3V6M

1 2

CA11 1U_0402_6.3V6K

1 2

CA14 2.2U_0402_6.3V6M

1 2

CA15 2.2U_0402_6.3V6M

I2C_CLK

15

SYNC

14

BCLK

17

SDATA-OUT

13

DC_DET/EPAD

16

SDATA-IN

11

NC

10

NC

9

NC

12

NC

8

NC

1

SPDIF-OUT/GPIO2/DMIC-DATA34/DMIC-CLK-IN

4

GPIO0/DMIC-DATA12

5

GPIO1/DMIC-CLK

2

PDB

48

JD1

47

JD2

38

VREF

39

LDO1-CAP

32

MIC2-CAP

29

MIC2-VREFO-R

28

MIC2-VREFO-L

25

CPVEE

24

CBN

23

CBP

21

LDO2

LDO2-CAP

19

LDO3

LDO3-CAP

ALC3287-CG_MQFN48_6X6

PCBEEP

MIC2-L/RING2

MIC2-R/SLEEVE

LINE2-L

LINE2-R

SPK-OUT-L+

SPK-OUT-L-

SPK-OUT-R-

SPK-OUT-R+

HPOUT-L

HPOUT-R

5VSTB

AVDD1

CPVDD/AVDD2

DVDD

DVDD-IO

PVDD1

PVDD2

Thermal_Pad

AVSS1

AVSS2

PC_BEEP

34

EXT_MIC_RING2

30

EXT_MIC_SLEEVE

31

36

35

SPK_L2+

42

SPK_L1-

43

SPK_R1-

44

SPK_R2+

45

HP_OUTL

27

HP_OUTR

26

33

1 2

RA9 10K_0402_5%

40

20

3

18

41

46

49

37

22

+5VS_PVDD

4.7U_0402_6.3V6M

GNDA

1

2

CA12

+1.8VDD_CODEC

+3VDD_CODEC

+IOVDD_CODEC

0.1U_0201_10V K X5R

Speaker

Headphone

+5VDDA_CODEC

1 2

RA12 0_0805_5%

Consumption Test

1

CA13

2

+1.8VDD_CODEC

1

CA6

2

2.2U_0402_6.3V6M

Plac e near Pin20

GNDA

+5VS

Speaker

W=40mils W=40mils

EM I

SPEAK 4 ohm : 40MIL SPEAK 8 ohm : 20MIL

SPK_L1SPK_L2+ SPK_R1SPK_R2+

wide 40MIL

1 2

RA5 0_0603_5%

1 2

RA6 0_0603_5%

1 2

RA1 0_0603_5%

1 2

RA3

0_0603_5%

SPK_L1-_CONN SPK_L2+_CONN SPK_R1-_CONN SPK_R2+_CONN

1

CA3

CA2

2

1000P_0402_50V7K

EMI@

1

CA4

CA5

2

1000P_0402_50V7K

EMI@

ESD protection needs to be placed near connector side

ES D

EXT_MIC_SLEEVE EXT_MIC_RING2 HP_OUTL HP_OUTR

+5VS

SPK_R1-_CONN SPK_L2+_CONN

EMI@ EMI@

6

5

4

EMI

SM010009U00

RA14 BLM15BD121SN1D_2P RA13 BLM15BD121SN1D_2P

RA17

DA2

@ESD@

I/O4

I/O2

VDD

GND

I/O3

I/O1

AZC099-04S.R7G_SOT23-6

12 12

RA15 47_0402_5%EMI@ RA16 47_0402_5%EMI@

@

RA18

1 2

10K_0402_5%

3

2

1

1 2 1 2

SD028470A80 SD028470A80

SPK_L1-_CONNSPK_R2+_CONN

1

CA18

2

EMI@

CA17

470P_0402_50V7K

1 2

220P_0402_50V7K

GNDAGNDAGNDAGNDAGNDA GNDA

EMI@

CA16

2

470P_0402_50V7K

EMI@

JSPK1

1

2

3

4

5

GND1

6

GND2

ACES_50271-0040N-001

SP02000TS00

ME@

HGNDB HGNDA

HPOUT_L HPOUT_R

CA19

1 2

220P_0402_50V7K

EMI@

+5VS --> +5VDDA_CODEC

+5VS +5V DDA_CODEC

3 3

1 2

RA19 0_0603_5%

1

CA20

2

0.1U_0201_10V K X5R

Plac e near Pin40

GNDA

+3.3VS --> +IOVDD_CODEC

+3VS

1 2

RA20 0_0603_5%

+IOVDD_CODEC

1

CA21

2

0.1U_0201_10V K X5R

Plac e n ear Pin18

1

CA28

2

2.2U_0402_6.3V6M

+1.8VS --> +1.8VDD_CODEC

+1.8VS +1.8VDD_CODE C

1 2

RA25 0_0402_5%

1

CA24

4 4

2

0.1U_0201_10V K X5R

Plac e near Pin20 Plac e n ear Pin34

GNDA

A

PC Beep

BEEP#<34>

HDA_SPKR<9 >

1 2

RA27 4.7K_0402_5%

1 2

RA29 4.7K_0402_5%

B

+3VS --> +3VDD_CODEC

+3VS +3VDD_CODEC

1 2

RA21 0_0402_5%

1

CA22

2

0.1U_0201_10V K X5R

Plac e nea r P in3

PC_BEEP

1 2

12

@

RA30 0_0402_5%

CA25 0.1U_0201_10V K X5R

GND GNDA

C

HGNDA / HGNDB , W=60mils

HGNDA

PLUG_IN

HGNDB

1 2

RA31 0_0402_5%

1 2

RA26 0_0402_5%

1 2

RA28 0_0402_5%

1 2

RA32 0_0402_5%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS T HE PROPRIETARY PROPERTY OF CO MPAL ELECTRONICS, INC. A ND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS T HE PROPRIETARY PROPERTY OF CO MPAL ELECTRONICS, INC. A ND CONTAINS CONFIDENTIAL AND TRADE SECRET INFOR MATION. TH IS SHEET M AY NOT BE TRANSFERED FROM THE CUS TODY OF TH E COMPE TENT DIVISION OF R&D

AND TRADE SECRET INFOR MATION. TH IS SHEET M AY NOT BE TRANSFERED FROM THE CUS TODY OF TH E COMPE TENT DIVISION OF R&D

AND TRADE SECRET INFOR MATION. TH IS SHEET M AY NOT BE TRANSFERED FROM THE CUS TODY OF TH E COMPE TENT DIVISION OF R&D DEPARTMENT EXCEPT A S AUTHORIZED BY COMPAL ELECTRONICS, IN C. NE ITHER T HIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT A S AUTHORIZED BY COMPAL ELECTRONICS, IN C. NE ITHER T HIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT A S AUTHORIZED BY COMPAL ELECTRONICS, IN C. NE ITHER T HIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO AN Y THIRD PA R T Y WITHOUTPRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO AN Y THIRD PA R T Y WITHOUTPRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1 2

RA22 0_0402_5%

1 2

RA23 0_0402_5%

12

CA29

@ESD@

100P_0402_50V8J

Compal Secret Data

2018/09/21 2019/09/21

Compal Secret Data

2

3

@ESD@

1

Deciphered Date

D

HPOUT_L1HPOUT_L

HPOUT_R1HPOUT_R

DA3

CEST23LC5VBC/A_SOT23-3

SCA00004300

Combo Jack (Normal Open)

JHP1

3

G/M

1

L/R

5

6

2

R/L

4

M/G

DA4

AZ5125-02S.R7G_SOT23-3

2

3

ESD@

1

33K_0402_5%

12

RA24

SCA00001A00

@ESD@

Ti t l e

Size

Document Number Rev

Custom

Date: Sheet o f

YUQIU_PJ567-F07M1BE-F

SP011609088 ME@

Compal Electronics, Inc.

HD Audio Codec_ALC3287

LA-H101P

E

7

GND

33 51Thursday, September 20, 2018

0.A0.A0.A

1

2

3

4

5

6

7

8

+3VL +3VL

1 2

R14 0_0603_5%

0.1U_0201_10V K X5R

C29

1

A A

KB_MUTLI_KEY<35>

SERIRQ<8>

LPC_FRAME#<8>

EMI

@EMI@

12

C35 22P_0402_50V8J

1 2

R22 47K_0402_5%@

+3VALW_EC

B B

KSO[0..17]<35>

KSI[0..7]<35>

+3VL

1 2

R31 2.2K_0402_5%

1 2

R32 2.2K_0402_5%

+3VS

1

R36

1

R38

1

@

+3VALW

R39

R44 10K_0402_5%@

1 2

C C

2

10K_0201_5%

2

10K_0201_5%

2

10K_0201_5%

KSO[0..17]

KSI[0..7]

EC_SMB_CK1 EC_SMB_DA1

EC_FAN_SPEED1 EC_FAN_SPEED2

GPU_PROHOT#

PBTN_OUT#

@EMI@

R19 10_0402_1%

12

2

C36

0.1U_0201_10V KX 5R

1

LPC_AD3<8> LPC_AD2<8> LPC_AD1<8> LPC_AD0<8>

CLK_LPC_EC<8>

PCI_RST#<10,31,32,37>

EC_SCI#<6>

PM_CLKRUN#<8>

[34] KB_MUTLI_KEY

[24,42] GPU_PROHOT#

EC_SMB_CK1<41,42> EC_SMB_DA1<41,42> EC_SMB_CK2<8> EC_SMB_DA2<8>

PM_SLP_S3#<10>

USB_CHG_CTL1<37>

EC_CLEAR_CMOS#<10>

USB_CHG_CTL3<37>

USB_CHG_EN<37>

USB_CHG_CTL2<37>

USB_CHG_STATUS#<37>

KB_BL_PWM<35>

EC_FAN_SPEED1<36>

EC_TX<31> EC_RX<31>

PCH_PWROK<10>

PWR_BATT_LOW#<37>

VR_ PW R GD<47>

PBTN_OUT#<10>

PM_SLP_S4#<10,42,45>

2

KB_MUTLI_KEY

PCI_RST# EC_RST#

KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15

EC_SMB_CK1 EC_SMB_DA1

EC_FAN_SPEED1

PBTN_OUT#

1000P_0402_50V7K

C30

1

2

1 2 3 4 5 7 8

10

12 13 37 20 38

55 56 57 58 59 60 61 62 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 81 82

77 78 79 80

6 14 15 16 17 18 19 25 28 29 30 31 32 34 36

122 123

+3VALW_EC

1000P_0402_50V7K

C31

C33

1

2

@

U11

GATEA20/GPIO00 KBRST#/GPIO01 SERIRQ LPC_ FRAME # LPC_ AD3 LPC_ AD2 LPC_ AD1

LPC & MI S C

LPC_ AD0

CLK_PCI_EC PCIRST#/GPIO05 EC_RST# EC_SCI#/GPIO0E CLKRUN#/GPIO1D

KSI0/GPIO30 KSI1/GPIO31 KSI2/GPIO32 KSI3/GPIO33 KSI4/GPIO34 KSI5/GPIO35 KSI6/GPIO36 KSI7/GPIO37 KSO0/GPIO20 KSO1/GPIO21 KSO2/GPIO22 KSO3/GPIO23 KSO4/GPIO24

In t . K/B

KSO5/GPIO25

Matri x

KSO6/GPIO26 KSO7/GPIO27 KSO8/GPIO28 KSO9/GPIO29 KSO10/GPIO2A KSO11/GPIO2B KSO12/GPIO2C KSO13/GPIO2D KSO14/GPIO2E KSO15/GPIO2F KSO16/GPIO48 KSO17/GPIO49

EC_SMB_CLK1/GPIO44 EC_SMB_DAT1/GPIO45 EC_SMB_CLK2/GPIO46 EC_SMB_DAT2/GPIO47

PM_SLP_S3#/GPIO04 GPI O07 GPI O08 GPI O0A GPI O0B GPI O0C AC_PRESENT/GPIO0D PWM2/GPIO11 FAN_SPEED1/GPIO14 FANFB1/GPIO15 EC_TX/GPIO16 EC_RX/GPIO17 PCH_PWROK/GPI O18 SUSP_LED#/GPIO19 NUM_LED#/GPIO1A

PBTN_OUT#/GPIO5D PM_SLP_S4#/GPIO5E

KB9022QD_LQFP128_14X14

SA000075S30

+EC_VCCA

9

22

33

96

125

111

VCC

VCC0

VCC_LPC

PWM Output

VCIN1_BATT_TEMP/AD0/GPI O38 VCIN1_BATT_DROP/AD1/GPIO39

AD Input

DA Outp ut

EC_MUTE#/PSCLK1/GPIO4A

USB_EN#/PSDAT1/GPIO4B

PS2 Interface

SPI Device Interfac e

SPI Flash ROM

GPIO

SM Bu s

VCIN1_ADP_PROCHOT/GPXIOA05

VCOUT1_PROCHOT#/GPXIOA06

VCOUT0_MAIN_PWR_ON/GPXIOA 07

GPO

GPIO

PWR_VCCST_PG/GPXIOA11

GPI

GND

11

24

35

94

113

1

C26 100P_0402_50V8J

@

2

67

AVCC

EC_VCCST_PG/GPIO0F

BEEP#/GPIO10

EC_FAN_PWM/GPIO12

AC_OFF/GPIO13

ADP_I/AD2/GPIO3A

AD_BID/AD3/GPIO3B

AD4/GPIO42 AD5/GPIO43

DA0/GPIO3C

EN_DFAN1/DA1/GPIO3D

DA2/GPIO3E DA3/GPIO3F

PSCLK2/GPIO4C PSDAT2/GPIO4D

TP_CLK/GPIO4E

TP_DATA/GPIO4F

ENKBL/GPXIOA00

WOL_EN/GPXI OA01

ME_EN/GPXIOA02

VCIN0_PH1/GPXIOD00

MISO/GPIO5B

MOSI/GPIO5C SPICLK/GPIO58 SPICS#/GPIO5A

EC_CIR_RX/AD6/GPIO40

SYS_PWROK/ AD7/GPIO41

BATT_CHG_LED#/GPIO52

BATT_LOW_LED#/GP IO55

EC_RSMRST#/GPXIOA03

PCH_PWR_EN/GPXI OA10

VCIN1_AC_IN/GPXIOD01

69

ECAGND

CAPS_LED#/GPIO53

PWR_LED#/GPIO54

SYSON/GPIO56 VR_ON/GPIO57

DPWROK_EC/GPIO59

GPXI OA04

BKOFF#/GPXIOA08

GPXI OA09

EC_ON/GPXIOD02 ON/OFF#/GPXIOD03 LID_SW#/GPXI OD04

SUSP#/GPXIOD05

GPXI OD06

PECI/GPXIOD07

V18R/VCC_IO2

AGND

GPIO 50

+3VALW_EC +EC_VCCA

21 23 26 27

63 64 65 66 75 76

68

NOVO#

70 71

USB_EN#

72

I2C_2_SCL

83

I2C_2_SDA

84

EC_SMB_CK4

85

EC_SMB_DA4

86 87

TAB_SW#

88

97 98 99 109

119 120 126 128

73 74

EC_MUTE#

89 90 91 92 93 95 121 127

100 101 102

VCOUT1_PROCHOT#

103 104 105 106 107 108

110 112 114

ON/OFF#

115 116

SUSP#

117 118

PECI

VCC_IO2

124

K e y b o a r d BackLight_SELECT

KB_BL_PWM

1

KBL_ID

R45

10K_0402_5%

NOKBL@

0

12

Security Classificat ion

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INF ORMATION . THIS SHEET MAY NOT B E TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INF ORMATION . THIS SHEET MAY NOT B E TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INF ORMATION . THIS SHEET MAY NOT B E TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, IN C . NEITHER THIS SH EET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, IN C . NEITHER THIS SH EET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, IN C . NEITHER THIS SH EET NOR THE INFORMATION IT CONTAINS MAY BE USED BY O R DISCLOSED TO A NY THIRD PA R T Y WITHOUTPR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C .

MAY BE USED BY O R DISCLOSED TO A NY THIRD PA R T Y WITHOUTPR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C .

2

3

4

MAY BE USED BY O R DISCLOSED TO A NY THIRD PA R T Y WITHOUTPR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C .

5

Funct i on

KBL 1

NO KBL

D D

PH on KB side

L1

1 2

BLM15AX601SN1D _2P

SM01000KL00

L2

1 2

BLM15AX601SN1D _2P

SM01000KL00

R37 0_0402_5%

1 2

R41 43_0402_1%

1 2

@

R43 0_0402_5%

1

C39

4.7U_0402_6.3V6M

2

2018/09/21 2019/09/21

C27

0.1U_0201_10V KX 5R

ECAGND

VC CS T_ P W RG D <10> BEEP# <33> EC_FAN_PWM1 <36>

VCIN1_BATT_TEMP <41,42>

AD P_ I <42> CUST_TEMP3 <36> TS_DISABLE# <28> CUST_TEMP2 <36>

NOVO# <37>

TP_DISABLE# <35>

DGPU_PWR_EN [11,26]

USB_EN# <37>

I2 C _ 2 _ S C L <11> I2 C _ 2 _ S D A <11> EC_SMB_CK4 <28,36> EC_SMB_DA4 <28,36>

USB_CHG_ILIM_SEL <37>

TAB_SW# <28>

ENBKL <6> SYS_PWROK <10>

ME_EN <9>

VCIN0_PH1 <41>

EC_SPI_MISO <8> EC_SPI_MOSI <8> EC_SPI_CLK <8> EC_SPI_CS0# <8>

CUST_TEMP1 <36> SENSOR_EC_INT <11> EC_MUTE# <33>

BATT_CHG_LED# <35>

CAPS_LED# <35>

PWR_LED# <37>

BATT_LOW_LED# <35>

SYSON <13,44> VR _O N <47> AC_PRESENT <10>

EC_RSMRST# <10>

3V/5VALW_PG <37,43,45>

VCOUT1_PROCHOT# <42> VCOUT0_MAIN_PWR_ON <43>

BKOFF# <28>

TYPEC_LIMIT_CTL1 <38>

CNVi_PWR_EN# <31>

1 2

VCIN1_AC_IN <42>

EC_ON <43>

ON/OFF# <37,39>

LID_SW# <36,37>

SUSP# <13,39,44> NUM_LED# <35>

+3VALW_EC

PCH_PWROK

100P_0402_50V8J

C42

1

ESD@

2

Compal S ecret Data

1

2

ECAGND

PCIE_WAKE#EC_PCIE_WAKE#

H_PECI <6>

ESD

Deciphered Date

6

1

C28 1000P_0402_50V7K

@

2

can ju st only stuff for S3 40 15"

PCIE_WAKE# <31>

VCOUT1_PROCHOT#

VR _H OT #<47>

+5VALW

USB_EN#

VCIN1_BATT_TEMP

VCIN1_AC_IN

EC_SMB_CK4 EC_SMB_DA4

I2C_2_SCL I2C_2_SDA

EC_PCIE_WAKE#

KB_MUTLI_KEY

LID_SW#

TAB_SW#

EC_MUTE#

EC_SPI_CS0#

Follow ENE suggestion fo r Auto load

KB_MUTLI_KEY

NOVO#

ON/OFF#

SUSP#

1 2

R40 0_0402_5%

1 2

R42 0_0402_5%

Tit le

Size Document Number Rev

Custom

Date: Sheet

7

1 2

R15 10K_0402_5%

1 2

C32 100P_0402_50V8J

1 2

C34 100P_0402_50V8J

1 2

R16 4.7K_0402_5%@

+3VALW

1

C38

ESD@

100P_0402_50V8J

2

LA-H101P

+3VS

+3VL

H_PROCHOT# <6>

8

1 2

R17 1K_0402_5%C340@

1 2

R18 1K_0402_5%C340@

1 2

R20 2.7K_0402_5%C340@

1 2

R21 2.7K_0402_5%C340@

1 2

R24 4.7K_0402_5%@

1 2

R25 10K_0402_5%@

1 2

R26 100K_0402_5%

1 2

R27 100K_0402_5%

1 2

R28 10K_0402_5%@

1 2

R30 100K_0402_5%

1 2

R29 10K_0402_5%

1 2

R33 100K_0402_5%

1 2

R34 100K_0402_5%

1 2

R35 100K_0402_5%@

Compal Electronics, Inc.

EC KB9022QD

ESD

34 51Thursday, September 20, 2018

0.A0.A0.A

of

A

B

C

D

E

F

G

H

Finger printer

JFP1

ME@

10

GND

9

GND

8

7

6

5

4

1 1

2 2

USB20_P7<12> USB20_N7

<12>

RFP1 0_0402_5%

+3VS

RFP2 0_0402_5%@

+3VALW

T o u c h P a d

I2C_0_SCL<11> I2C_0_SDA<11>

TP_INT#<9> TP_DISABLE#<34>

1 2

ESD

@

+3VS_FP

2

3

DFP1

ESD@

CEST23LC5VB C/A_SOT23-3

SCA00004300

1

+3VS +3VS

12

100P_0402_50V8J

CTP3

CTP2

1

@

2

RTP2

4.7K_0402_5%

RTP1

1 2

0_0402_5%

@

CTP1

0.1U_0201_10V KX 5R

2

3

DTP1

@ESD@

L03ESDL5V0CC3-2_SOT23-3

1

CFP1

0.1U_0201_10V KX 5R

+TP_VCC

3

2

1

JXT_FP201H-008G10M

SP010020S00

JTP1

ME@

8

7

10

7

G2

6

9

6

G1

5

4

3

2

1

ACES_51522-00801-001

SP01001AE00

K e y b o a r d

+5VS

C340-15 Left Pin Define

RTP4 0_0402_5%

1 2

KB_MUTLI_KEY<34> NUM_LED#<34>

+5VS_KB CAPS_LED#_R

KSO15 KSO10 KSO11 KSO14 KSO13 KSO12 KSO3 KSO6 KSO8 KSO7 KSO4 KSO2 KSI0 KSO1 KSO5 KSI3 KSI2 KSO0 KSI5 KSI4 KSO9 KSI6 KSI7 KSI1

JKB1

ME@

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

GND

28

GND

29

30

31

32

JXT_FP257H-032S10M

SP01002FA00

33 34

CAPS_LED#<34>

KSI[0..7]

KSO[0..17]

S340-14 & S340-15 Right Pin Define

R266

1 2

866_0402_5%

R265 866_0402_5%

12

S340_15@

KSI[0..7] < 34>

KSO[0..17] <34>

+5VS_KB CAPS_LED#_R

KSO15 KSO10 KSO11 KSO14 KSO13 KSO12 KSO3 KSO6 KSO8 KSO7 KSO4 KSO2 KSI0 KSO1 KSO5 KSI3 KSI2 KSO0 KSI5 KSI4 KSO9 KSI6 KSI7 KSI1 KSO16 KSO17

NUM_LED#_R

KB_MUTLI_KEY

CAPS_LED#_R

1

C229

ESD@

0.1U_0201_10V KX 5R

2

JKB2

ME@

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

ACES_51612-0320M-001

SP011410151

GND2 GND1

34 33

+5VS

KBL@

ESD

QKBL1

KBL@

S

ME2301DC-G_SOT23-3

G

2

1

2

D

13

CKBL3

KBL@

0.01U_0402_16V7K

+5VS_KBL

C

1

CKBL1

@

2

10U_0402_6.3V6M

S340-15

2

CKBL2

1

KBL@

0.1U_0201_10V K X5R

JKBL1

ME@

1

2

5

33G1

4

6

4

G2

ACES_52501-00401-W01

SP011806072

LED4

RS1

C340@

1 2

412_0402_1%

B A T T LED

BATT_CHG_LED#<34>

BATT_LOW_LED#<34>

Security Classificat ion

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INF ORMATION . THIS SHEET MAY NOT B E TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INF ORMATION . THIS SHEET MAY NOT B E TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INF ORMATION . THIS SHEET MAY NOT B E TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, IN C . NEITHER THIS SH EET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, IN C . NEITHER THIS SH EET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, IN C . NEITHER THIS SH EET NOR THE INFORMATION IT CONTAINS MAY BE USED BY O R DISCLOSED TO A NY THIRD PA R T Y WITHOUTPR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C .

MAY BE USED BY O R DISCLOSED TO A NY THIRD PA R T Y WITHOUTPR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C .

D

MAY BE USED BY O R DISCLOSED TO A NY THIRD PA R T Y WITHOUTPR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C .

2018/09/21 2019/09/21

E

Compal S ecret Data

Deciphered Date

F

RS2

C340@

1 2

523_0402_1%

RS3

S340@

1 2

412_0402_1%

RS4

S340@

1 2

523_0402_1%

Tit le

Size Document Number Rev

Date: Sheet

C340@

21

SC50000BB10

LTW-C193TS5-C_WHITE

LED5

C340@

A

SC500005930

LTST-C191KFKT-2CA_ORANGE

LED2

S340@

21

SC50000BB10

LTW-C193TS5-C_WHITE

LED3

S340@

A

SC500005930

LTST-C191KFKT-2CA_ORANGE

Compal Electronics, Inc.

KBL/KBD/LED/TP/HS Conn.

Custom

G

BOT

21

T O P

21

LA-H101P

+VL

35 51Thursday, September 20, 2018

H

0.A0.A0.A

of

3 3

Keyboard Backlight

+5VALW

12

RKBL1

KBL@

10K_0402_5%

RKBL2

KB_BL_PWM<34>

4 4

S340-14 & C340-15

JKBL2

1

2

+5VS_KBL

A

2

3

4

5

G1

6

G2

ACES_51570-00401-P02

SP01002LF00

1 2

30K_0402_1%

ME@

B

5

4

3

2

1

G-Sensor

+5VS

FAN

1

@RF@

EC_FAN_PWM 1

1

@RF@

CF4

6.8P_0402_50V8C

2

CF3

6.8P_0402_50V8C

2

D D

+3VS +3VS_GS_R

RGS1

2

CGS1

C340@

0.1U_0201_10V KX 5R

1

1 2

0_0402_5%

+3VS_GS_R

EC_SMB_DA4<28,34> EC_SMB_CK4<28,34>

UGS1

7

VDD

10

CSB

5

INT1

6

INT2

2

SDx SCx12GNDI O

BMA253_LGA12

SA000096W00

C340@

VDDIO

SDO GND

3 11

PS

4

NC

1 9 8

SMB Address: 0X18

1

@RF@

CF6

6.8P_0402_50V8C

2

Hall Sensor

C C

EC_FAN_SPEED1

1

@RF@

CF5

6.8P_0402_50V8C

2

1

+5VS

2

1

RF1

CF1 10U_0402_6.3V6M

RF2

CF2 10U_0402_6.3V6M

2

[33] EC_FAN_PWM1

[33] EC_FAN_SPEED1

2

[33] EC_FAN_PWM2

[33] EC_FAN_SPEED2

1

0_0603_5%

1

0_0603_5%

+5VS_FAN1

+5VS_FAN2

JFAN1

1

2

3

4

5

G1

6

G2

CVILU_CI4404M1HRT-NH

SP02000VH00

ME@

JFAN2

1

2

3

4

5

G1

6

G2

CVILU_CI4404M1HRT-NH

SP02000VH00

ME@

EC_FAN_PWM 2

1

@RF@

CF8

6.8P_0402_50V8C

2

EC_FAN_SPEED2

1

@RF@

CF7

6.8P_0402_50V8C

2

THERMISTOR

for S340 14"for C340

+3VALW

C340@

APX8132AI-TRG_SOT23-3UHS1

GND

VOUT

3

LID_SW#

1

CHS1 10P_0402_50V8J

2

LID_SW# <34,37>

C340@

2

VDD

2

CHS2

0.1U_0201_10V KX 5R

1

C340@

B B

1

+3VALW

2

CHS3

0.1U_0201_10V KX 5R

1

S340_14@

0.1U_0201_10V6K

1

2

1

2

CTH1

+3VS_THM

1

2

REMOTE1+

REMOTE2+

REMOTE2-

Ad d re ss 1001_101xb

TO P DD R

UTH1

1

VCC

2

DP1

3

DN1

4

DP2

5

DN2

F75303M_MSOP10

SA000046C00

SCL

SDA

ALER T#

THERM#

GND

10

9

8

7

6

EC_SMB_CK2

EC_SMB_DA2

THM_ALERT#

EC_SMB_CK2 [8,24,33]

EC_SMB_DA2 [8,24,33]

+3VS_THM

12

@

RTH2 10K_0402_5%

+3VS +3VS_THM

S340_14@

APX8132AI-TRG_SOT23-3UHS2

LID_SW#

VDD

3

VOUT

GND

1

CHS4 10P_0402_50V8J

2

S340_14@

RTH3

BOTTOM VCORE

QTH1

MMBT3904WH_SOT323-3

BOTTOM GPU

QTH2

MMBT3904WH_SOT323-3

2

0_0402_5%

1

@

REMOTE1+

12

1

C

CTH3

2

2200P_0402_25V7K

B

@

E

3

1

E

3

REMOTE1,2 (+/ -) :

REMOTE1- REMOTE1-

REMOTE2+

12

CTH5

2

2200P_0402_25V7K

B

@

REMOTE2-

T r a c e width/space:10/10 mil T r a c e length:<8"

Close UTH1

CTH4

2200P_0402_25V7K

CT114

2200P_0402_25V7K

Thermal Sensor

DDR4 GPU_CHOKE Charger CHOKE

+EC_VCCA

12

RTS1

16.5K_0402_1%

[33] CUST_TEMP1 [33] CUST_TEMP2 [33] CUST_TEMP3

A A

Security Classificat ion

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INF ORMATION . THIS SHEET MAY NOT B E TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INF ORMATION . THIS SHEET MAY NOT B E TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INF ORMATION . THIS SHEET MAY NOT B E TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, IN C . NEITHER THIS SH EET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, IN C . NEITHER THIS SH EET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, IN C . NEITHER THIS SH EET NOR THE INFORMATION IT CONTAINS MAY BE USED BY O R DISCLOSED TO A NY THIRD PA R T Y WITHOUTPR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C .

MAY BE USED BY O R DISCLOSED TO A NY THIRD PA R T Y WITHOUTPR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C .

5

4

MAY BE USED BY O R DISCLOSED TO A NY THIRD PA R T Y WITHOUTPR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C .

3

12

RTS4 100K +-1% 0402 B25/50 4250K

ECAGND

Compal S ecret Data

2018/09/21 2019/09/21

Compal S ecret Data

Deciphered Date

2

+EC_VCCA +EC_VCCA

12

RTS2

16.5K_0402_1%

12

RTS5 100K +-1% 0402B25/ 50 4250K

ECAGND

Compal Electronics, Inc.

Tit le

Size Document Number Rev

Custom

Date: Sheet

12

ECAGND

FAN / Thermal Senser

LA-H101P

RTS3

16.5K_0402_1%

RTS6 100K +-1% 0402B2 5/50 4250K

36 51Thursday, September 20, 2018

1

0.A0.A0.A

of

A

B

C

D

E

F

G

H

USB3.0_Port (AOU_Port)

USB Charge switch

+3VL +5VALW_USB1+5VALW_CHG

12

R110

1 1

USB_CHG_STATUS#

<34>

USB_OC0#

<12>

USB_CHG_ILIM_SEL<34>

USB_CHG_EN<34> USB_CHG_CTL1<34> USB_CHG_CTL2<34> USB_CHG_CTL3<34>

10K_0402_5%

1

2

R112 0_0402_5%

@

12

R117

10K_0402_5%

+5VALWP

22U_0603_6.3V6M

C55

1

@

2

2 2

2

For USB Charger to improve +5VALWP power ripple

12

R108

U7

10K_0402_5%

1

IN

9

STATUS#

13

FAULT#

4

ILIM_SEL

5

EN

6

CTL1

7

CTL2

8

CTL3

TPS2546RTER_QFN16_3X3

SA0000B0V00

22U_0603_6.3V6M

C48

1

@

2

22U_0603_6.3V6M

C56

1

@

2

C50

C49

1

2

47U_0805_6.3V6M

10U 6.3V M X5R0402

C57

C59

C58

1

@

2

80mil

12

USB20_P1_C

OUT

10

DP_IN

DM_IN DM_OUT DP_OUT

ILIM_LO

ILIM_HI

GND

T-PAD

C60

1

@

2

USB20_N1_CUSB_OC0#_R

11 2 3 15 16 14 17

22U_0603_6.3V6M

C61

@

R113 2.7M_0402_1% R114 24.9K_0402_1%

22U_0603_6.3V6M

C62

C63

1

@

2

1 2 1 2

22U_0603_6.3V6M

1

@

2

C64

USB20_N1 <12> USB20_P1 <12>

3V/5VALW_PG<34,43,45>

R118 0_0402_5%

1 2

C51 22U_0603_6.3V6M

+VL

R115 100K_0402_5%

EC_ON_R

0.1U_0201_10V K X5R

C54

1

@

2

+VL

1

2

1 2

R111

1 2

0_0603_5%

2

G

Q3

+5VALW_CHG

13

D

S

2N7002KW_SOT323-3

D

S

13

Q2

G

2

ME2301DC-G_SOT23-3

0.1U_0201_10V K X5R

1

@

2

+5VALW

22U_0603_6.3V6M

C52

1

2

C53

USB3.0_Port (Non-AOU_Port)

3 3

+5VALW +5VALW_USB2

1

C66

0.1U_0201_10V6K

4 4

A

USB_EN#<34>

2

USB20_P2<12>

USB20_N2<12>

2A/Active Low

U9

5

IN

4

EN

G524B2T11U_SOT23-5

SA00007BW00

EMI

B

1

OUT

2

GND

3

2

1

R334 0_0402_5%@

OCB

USB20_P2

USB20_N2

USB_OC1# <12>

C

D

I/O C O N N

Security Cl assificat ion

Issued Date

THISSHEET OF ENGINEERINGDRAWING IS THE PROPRIETARYPROPERTYOF COMPALELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THISSHEET OF ENGINEERINGDRAWING IS THE PROPRIETARYPROPERTYOF COMPALELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRETINFORMATION. THISSHEET MAYNOT BE TRANSFERED FROM THECUSTODY OF THECOMPET ENT DIVISION OF R&D

AND TRADE SECRETINFORMATION. THISSHEET MAYNOT BE TRANSFERED FROM THECUSTODY OF THECOMPET ENT DIVISION OF R&D

AND TRADE SECRETINFORMATION. THISSHEET MAYNOT BE TRANSFERED FROM THECUSTODY OF THECOMPET ENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAYBE USED BY OR DISCLOSED TO ANY THIRD P A R T Y WITHOUT PRIORWRITTEN CONSENT OF COMPALELECTRONICS, INC.

MAYBE USED BY OR DISCLOSED TO ANY THIRD P A R T Y WITHOUT PRIORWRITTEN CONSENT OF COMPALELECTRONICS, INC.

E

JIO1

ME@

47

G2

46

45

G1

45

+5VALW_USB1

USB20_N1_C

USB3_CRX_DTX_P1<12> USB3_CRX_DTX_N1<12>

USB3_CTX_DRX_P1<12> USB3_CTX_DRX_N1<12>

USB3_CRX_DTX_P2<12> USB3_CRX_DTX_N2<12>

USB3_CTX_DRX_P2<12> USB3_CTX_DRX_N2<12>

LID_SW#<34,36>

PCI_RST#<10,31,32,34> PCIE_CTX_DRX_P9<12> PCIE_CTX_DRX_N9<12>

PCIE_CRX_DTX_P9<12> PCIE_CRX_DTX_N9<12>

CLK_PCIE_P4<10> CLK_PCIE_N4<10>

CLKREQ_PCIE#4<10>

NOVO#<34> ON/OFF#<34,39>

PWR_LED#<34>

PWR_BATT_LOW#<34>

USB20_P1_C

USB20_N2 USB20_P2

+5VALW_USB2

+3VALW

+3VS

PCIE_CTX_C_DRX_P9

0.1U_0201_10V6K

1 2

C232

1 2

C233

2018/09/21 2019/09/21

F

PCIE_CTX_C_DRX_N9

0.1U_0201_10V6K

+VL

+CHGRTC_R

Compal Secret Data

Deciph ered Date

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

ACES_51619-04501-001

SP011807060

G

Compal Electronics, Inc.

Ti t l e

Custom

Date: Sheet of

Size

Document Number

IO board

LA-H101P

37 51Thursday, September 20, 2018

H

Rev

0.A0.A0.A

5

TYPE-C - CC+MUX (RTS5448-GR)

+5VALW +VCON_IN_5448 +5VALW +5V_IN_5448

1 2

RT1

D D

USB3_CRX_MTX_N3<12> USB3_CRX_MTX_P3<12> USB3_CTX_MRX_N3<12> USB3_CTX_MRX_P3<12>

C C

0_0603_5%

CC1_5448_CONN CC2_5448_CONN

12

CT3 220P_0402_50V8J

USB3_MRX_DTX_P2 USB3_MRX_DTX_N1 USB3_MRX_DTX_P1 USB3_CRX_MTX_N3 USB3_CRX_MTX_P3 USB3_CTX_MRX_N3 USB3_CTX_MRX_P3 USB3_MTX_C_DRX_N1 USB3_MTX_C_DRX_P1 USB3_MTX_C_DRX_P2 USB3_MTX_C_DRX_N2 CC1_5448_CONN

USB3_MRX_DTX_P2 USB3_MRX_DTX_N1 USB3_MRX_DTX_P1 USB3_MRX_DTX_N2

1 2

RT2

12

CT4 220P_0402_50V8J

1 2

CT23 0.33U_0201_6.3V6M

1 2

CT24 0.33U_0201_6.3V6M

1 2

CT25 0.33U_0201_6.3V6M

1 2

CT19 0.33U_0201_6.3V6M

1 2

CT20 0.33U_0201_6.3V6M

1 2

CT18 0.22U_0201_6.3V

1 2

CT17 0.22U_0201_6.3V

1 2

CT7 0.1U_0201_10V6K

1 2

CT8 0.1U_0201_10V6K

1 2

CT9 0.1U_0201_10V6K

1 2

CT10 0.1U_0201_10V6K

1 2

RT18 220K_0402_5%

1 2

RT19 220K_0402_5%

1 2

RT20 220K_0402_5%

1 2

RT21 220K_0402_5%

0_0603_5%

0.1U_0201_10V K X5R

USB3_MRX_C_DTX_P2 USB3_MRX_C_DTX_N1 USB3_MRX_C_DTX_P1 USB3_CRX_C_MTX_N3 USB3_CRX_C_MTX_P3 USB3_CTX_C_MRX_N3 USB3_CTX_C_MRX_P3 USB3_MTX_DRX_N1 USB3_MTX_DRX_P1 USB3_MTX_DRX_P2 USB3_MTX_DRX_N2

MUX MISC.

+LDO_3V3_5448 +LDO_3V3_5448

RT12

10K_0402_5%

1 2

TYPEC_LIMIT_CTL1 TYPEC_LIMIT_CTL2

12

RT4

@

10K_0402_5%

Rp Configuration

B B

A A

200K_0402_1%

RT9

10K_0402_1%

+VBUS_5448

12

RT6

12

RT13

10K_0402_5%

1 2

12

RT5

@

10K_0402_5%

+5V_IN_5448 +5V_IN_5448

12

RT7

4.7K_0402_5% @

VMON_5448 VBUS_EN_5448 OCP_DET_5448

For C_VBUS (Power Switch Enable Pin)

5

RT10

10K_0402_5%

12

For C_VBUS (Power Switch OCP Pin)

1

CT2

2

UT1

1

C_RX2_1N/2P

2

C_RX1_1P/2N

3

C_RX1_1N/2P

4

SSRX_1P/2N

5

SSRX_1N/2P

6

SSTX_1P/2N

7

SSTX_1N/2P

8

C_TX1_1P/2N

9

C_TX1_1N/2P

10

C_TX2_1N/2P

11

C_TX2_1P/2N

12

CC1

RTS5448-GR QFN 24P T Y P E - C

SA0000AXR00

12

RT8

4.7K_0402_5%

12

RT11

10K_0402_5%

4

13

20

19

5V_IN

VCON_IN

INPUT

RP_SEL_M1 RP_SEL_M0

C_RX2_1P/2N

RT16 0_0603_5%

@

4

VBUS_EN OCP_DET

LDO_3V3

VMON

REXT

1 2

+LDO_3V3_5448+VCON_IN_5448

CC2

NC

GND

1

CT1

4.7U_0402_6.3V6M

SE00000SO00

2

14 15 16 17 18

21 22 23 24 25

OCP_DET_5448_R

+5V_IN_5448

1

CT5 10U_0402_6.3V6M

SE00000UD00

2

CC2_5448_CONN VBUS_EN_5448 OCP_DET_5448 VMON_5448

1 2

RT3 6.2K_0402_1%

USB3_MRX_C_DTX_N2

TYPEC_LIMIT_CTL1 TYPEC_LIMIT_CTL2 DIR_SET

CT26 0.33U_0201_6.3V6M

1

CT6

0.1U_0201_10V K X5R

2

Only limit on 0.9A

TYPEC_LIMIT_CTL1 <34>

1 2

USB3_MRX_DTX_N2

USB2.0

USB20_N3<12>

USB20_P3<12>

ESD COMPONENTS

USB3_MTX_C_DRX_N1

USB3_MTX_C_DRX_P2

USB3_MTX_C_DRX_N2

USB3_MRX_DTX_N2

USB3_MRX_DTX_P2

USB3_MRX_DTX_N1

USB3_MRX_DTX_P1

3

RT17

10K_0402_5%

3

TYPE-C CONNECTOR

Over Current Protection Pin: If Over Current Occurred - From Hig h to Low.

+5VALW

OCP_DET_5448_R VBUS_EN_5448

12

LT1

EMI@

1

2

443

DLM0NSN900HY2D_4P

SM070005U00

DT1

9

10

8

9

7

6

AZ124S-04F.R7GDFN2510 US B3.1

SC300005900 ESD@

DT2

9

10

8

9

7

6

AZ124S-04F.R7GDFN2510 US B3.1

SC300005900 ESD@

USB3_MTX_C_DRX_N1

1

USB3_MTX_C_DRX_P1USB3_MTX_C_DRX_P1

2

USB3_MTX_C_DRX_P2

4

USB3_MTX_C_DRX_N2

5

3

8

USB3_MRX_DTX_N2

1

USB3_MRX_DTX_P2

2

USB3_MRX_DTX_N1

4

USB3_MRX_DTX_P1

5

3

8

Security Cl assificat ion

THISSHEET OF ENGINEERINGDRAWING IS THE PROPRIETARYPROPERTYOF COMPALELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THISSHEET OF ENGINEERINGDRAWING IS THE PROPRIETARYPROPERTYOF COMPALELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRETINFORMATION. THISSHEET MAYNOT BE TRANSFERED FROM THECUSTODY OF THECOMPET ENT DIVISION OF R&D

AND TRADE SECRETINFORMATION. THISSHEET MAYNOT BE TRANSFERED FROM THECUSTODY OF THECOMPET ENT DIVISION OF R&D

AND TRADE SECRETINFORMATION. THISSHEET MAYNOT BE TRANSFERED FROM THECUSTODY OF THECOMPET ENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAYBE USED BY OR DISCLOSED TO ANY THIRD P A R T Y WITHOUT PRIORWRITTEN CONSENT OF COMPALELECTRONICS, INC.

MAYBE USED BY OR DISCLOSED TO ANY THIRD P A R T Y WITHOUT PRIORWRITTEN CONSENT OF COMPALELECTRONICS, INC.

UT2

5

IN

3

FLAG

4

EN(#EN)

G517G1TO1U_TSOT23-5

SA00009XD00

1

CT11 10U_0402_6.3V6M

SE00000UD00

2

1 2

CT13 0.47U_0402_25V6K

1 2

CT15 0.47U_0402_25V6K

USB20_N3_R

2

USB20_P3_R

3

Issued Date

2

+VBUS_5448

1

OUT

2

GND

CT12 10U_0603_25V6M

SE00000X200

2

10U_0402_6.3V6M

20 Volts Protection Circuit

+VBUS_5448_R +VBUS_5448_R

JUSBC1

A1

USB20_P3_R

GND

A2

SSTXP1

A3

SSTXN1

A4

VBUS

A5

CC1

A6

DP1

A7

DN1

A8

SBU1

A9

VBUS

A10

SSRXN2

A11

SSRXP2

A12

GND

1

GND

2

GND

3

GND

DRAPH_UB11245-B200B-1H

SP061806060 ME@

DT3

9

10

8

9

7

6

AZ1045-04F_DFN2510P10E-10-9

SC300001Y00

ESD@

DT4

3

I/O2

2

GND

1

I/O1

AZC399-04S.R7GSOT23-6

SC300005Y00 ESD@

Compal Secret Data

Deciph ered Date

2

1

2

4

5

3

8

I/O4

VDD

I/O3

USB3_MTX_C_DRX_P1 USB3_MTX_C_DRX_N1

CC1_5448_CONN

USB20_P3_R USB20_N3_R

USB3_MRX_DTX_N2 USB3_MRX_DTX_P2

CC1_5448_CONN

2018/09/21 2019/09/21

20V_PRTCT@

+VBUS_5448

GND

SSRXP1 SSRXN1

VBUS

SBU2

DN2 DP2

CC2

VBUS

SSTXN2 SSTXP2

GND

GND GND GND

1

2

4

5

3

6

5

4

+VBUS_5448 +VBUS_5448_R

1

CT22

2

12

RT14 10K_0402_5%

20V_PRTCT@

B12

USB3_MRX_DTX_P1

B11

USB3_MRX_DTX_N1

B10

B9

B8

USB20_N3_R

B7

USB20_P3_R

B6

CC2_5448_CONN

B5

B4

USB3_MTX_C_DRX_N2

B3

USB3_MTX_C_DRX_P2

B2

B1

4 5 6

CC1_5448_CONN

CC2_5448_CONNCC2_5448_CONN

+5VALW

USB20_N3_R

@

JT1

112

JUMP_43X79

UT3

B1

VBUS

VINT

C1

VINT

VBUS

B2

VINT

VBUS

ILIM

A2

FAULT

GND

A1

EN

GND GND

NX5P3090UK_WLCSP12

SA00009LF00

20V_PRTCT@

1 2

CT14 0.47U_0402_25V6K

1 2

CT16 0.47U_0402_25V6K

Ti t l e

Size

Custom

Date: Sheet of

1

2

10U_0402_6.3V6M

20V_PRTCT@

C2 D1 D2

A3

B3 C3 D3

12

ESD

CEST23NC24VU 3P C/A SOT23

Document Number

DT5

SCA00004500

ESD@

Compal Electronics, Inc.

Type-C

LA-H101P

1

CT21

1

2

RT15 16K_0402_1%

20V_PRTCT@

3

1

150U_B2_6.3VM_R45M

CT33

1

+

2

Rev

38 51Thursday, September 20, 2018

0.A0.A0.A

A

DC t o DC

B

C

D

E

1 1

SUSP#<13,34,44>

+5VALW

0.1U_0201_10V K X5R

+3VALW

0.1U_0201_10V K X5R

1

2

1

2

C77

C71

1

C78

@

10U_0402_6.3V6M

SE00000UD00

2

1

C72

@

10U_0402_6.3V6M

SE00000UD00

2

+VL

+5VALW t o +5VS

U10

1

VIN1

2

VIN1

3

ON1

4

VBIAS

5

ON2

6

VIN2

7

VIN2

EM5209VF_DFN14_3X2

SA0000BKC00

VOUT1 VOUT1

GND

VOUT2 VOUT2

GPAD

J2

2

JUMP_43X79

10U_0402_6.3V6M

14 13

12

CT1

11

10

CT2

9 8

15

+5VALW_5VS

1 2

C76 S CERCAP2200P 25V K X7R 0402

SE075222K80

1 2

C75 S CERCAP1000P 50V K X7R 0402

+3VALW_3VS

SE074102K80

J1

2

JUMP_43X79

10U_0402_6.3V6M

112

@

SE00000UD00

112

@

SE00000UD00

+5VS

0.1U_0201_10V K X5R C80

1

+3VS

1

@

2

0.1U_0201_10V K X5R C74

1

@

2

C79

C73

+3VALW t o +3VS

2 2

DISCHARGE CIRCUIT

Fo r +1.8VALW Discharge

3 3

MISC.

CPU SSD1WLAN

H2

H1 HOLEA

H_3P3

H9 HOLEA

H_2P8

H3

HOLEA

1

H_3P3

H12

H10

HOLEA

1

H_2P5

GPU

H4

H5

HOLEA

1

H15 HOLEA

1

H_2P5

1

H_3P3

H13 HOLEA

1

H_4P6

1

H_3P3

H14 HOLEA

1

H_3P0X2P5

H5 HOLEA

1

H_3P2

H7 HOLEA

1

H_3P2

H8 HOLEA

1

H_9P0X5P0

H16 HOLEA

1

H_4P4

H17 HOLEA

1

H_6P0

ON/OFF# S HORT P A D S

@

12

ON/OFF#

JP1

SHORT PADS

@

12

ON/OFF#

JP2

SHORT PADS

ON/OFF# <34,37>

DDR Shielding Clip

Larger

CLIP1 HOLEA

Smaller

CLIP5

4 4

A

B

HOLEA

CLIP3

CLIP4

HOLEA

@

1

@

1

@

1

CLIP7

@

1

Is s u ed Date

HOLEA

@

1

CLIP8 HOLEA

CLIP6 HOLEA

Security Classificat ion

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I N C . AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I N C . AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETEN T D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETEN T D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETEN T D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, IN C . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, IN C . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, IN C . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED B Y OR DISCLOSED TO AN Y THIRD P A R T Y WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C .

MAY BE USED B Y OR DISCLOSED TO AN Y THIRD P A R T Y WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C .

C

CLIP10

CLIP11

HOLEA

@

1

@

1

2018/09/21 2019/09/21

CLIP12 HOLEA

@

1

CLIP13 HOLEA

@

1

Compal S ecret Data

Deciphered Date

CLIP2 HOLEA

@

1

D

FD2

FD1

1

FD3

FD4

1

Compal Electronics, Inc.

Tit le

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

DC to DC / Discharge / MISC

LA-H101P

E

39 51Thursday, September 20, 2018

of

0.A0.A0.A

5

D D

4

3

2

1

ACES_50278-00401-001

C C

B B

JDCIN1

CONN@

G2 G1

4 3 2 1

6 5 4 3 2 1

+RTCBATT

PF1

7A_32VDC_0437007.WRML

APDIN

PD1

LRB715FT1G_SOT323-3

1

PL1

EMI@

12

PC2

100P_0402_50V8J

EMI@

PR2

0_0603_5%

1 2

5A_Z80_0805_2P

1 2

+CHGRTC_R

+CHGRTC

PR1

@

45.3K_0603_1%

1 2

1K_0603_5%

1 2

+19V_APDIN

12

PC1

1000P_0402_50V7K

EMI@

PR3

21

2

3

12

+3VL

+19V_VIN

12

PC3

100P_0402_50V8J

EMI@

PC4

1000P_0402_50V7K

EMI@

A A

Secu rity Classification

Is s u ed Date

THIS SHEET OF ENGINEERING DRAWING IS THEPROPRIETARYPROPERTY OF COMPAL ELECTRONICS, I N C . A N D CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THEPROPRIETARYPROPERTY OF COMPAL ELECTRONICS, I N C . A N D CONTAINS CONFIDENTIAL AN D TRADE SECRET INFORMATION. THIS SHEET MAYNOT BET RANSFERED FROM THECUSTODY OF THECOMPETENTDIV ISION O F R&D

AN D TRADE SECRET INFORMATION. THIS SHEET MAYNOT BET RANSFERED FROM THECUSTODY OF THECOMPETENTDIV ISION O F R&D

AN D TRADE SECRET INFORMATION. THIS SHEET MAYNOT BET RANSFERED FROM THECUSTODY OF THECOMPETENTDIV ISION O F R&D DEPARTMENTEXCEPT AS AUTHORIZEDBY COMPAL ELECTRONICS, IN C . NEITHERTHISSHEET NOR THEINFORMATION IT CONTAINS

DEPARTMENTEXCEPT AS AUTHORIZEDBY COMPAL ELECTRONICS, IN C . NEITHERTHISSHEET NOR THEINFORMATION IT CONTAINS

DEPARTMENTEXCEPT AS AUTHORIZEDBY COMPAL ELECTRONICS, IN C . NEITHERTHISSHEET NOR THEINFORMATION IT CONTAINS MAYBE USED BY OR DISCLOSED TO A NY THIRD PA R T Y WITHOUT PRIOR WRITTENCONSENT OF COMPALELECTRONICS, IN C .

MAYBE USED BY OR DISCLOSED TO A NY THIRD PA R T Y WITHOUT PRIOR WRITTENCONSENT OF COMPALELECTRONICS, IN C .

5

4

MAYBE USED BY OR DISCLOSED TO A NY THIRD PA R T Y WITHOUT PRIOR WRITTENCONSENT OF COMPALELECTRONICS, IN C .

3

2018/04/09 2019/04/09

Compal Secret Dat a

Deciphered Date

Compal Electronics, Inc.

Tit le

PWR- DCIN / Vin Detector

Size Document Number Rev

Custom

Date: Sheet o f

2

Date: Sheet o f

LA-H101PLA-H101PLA-H101P

1

40 54Thursday, September 20, 2018

0.A0.A0.A

5

D D

4

3

2

1

PH201 under CPU botten side :

CPU thermal protection at 93 +-3 degree C Recovery at 56 +-3 degree C

+EC_VCCA

PL3

EMI@

5A_Z80_0805_2P

1 2

EMI@

5A_Z80_0805_2P

1 2

12

PC5

EMI@

1000P_0402_50V7K

EC_SMB_CK1 <34,42>

EC_SMB_DA1 <34,42>

+3VL

+3VALW

VCIN1_BATT_TEMP <34,42>

PL4

+12.6V_BATT+

12

PC6

0.01U_0402_16V7K

VCIN0_PH1<34>

EMI@

PR6 200K_0402_1%

+8.4V_VMB

C C

B B

CONN@

JBAT1

1 2 3 4 5 6 7

8 G1 G2 G3 G4

ACES_60757-00802-001

VMB2

1 2 3 4 5 6 7 8 9 10 11 12

EC_SMDA

EC_SMCA

12

PF2

F1206HB12V024TM 12A 24V UL FAST

12

PR4

100_0402_1%

PR5

100_0402_1%

1 2

PR7 200K_0402_1%@

1 2

PR8 10K_0402_5%

21

12

PR9

16.5K_0402_1%

12

ECAGND

PH1 100K +-1% 0402 B25/50 4250K

A A

Secu rity Classification

Is s u ed Date

THIS SHEET OF ENGINEERING DRAWING IS THEPROPRIETARYPROPERTY OF COMPAL ELECTRONICS, I N C . A N D CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THEPROPRIETARYPROPERTY OF COMPAL ELECTRONICS, I N C . A N D CONTAINS CONFIDENTIAL AN D TRADE SECRET INFORMATION. THIS SHEET MAYNOT BET RANSFERED FROM THECUSTODY OF THECOMPETENTDIV ISION O F R&D

AN D TRADE SECRET INFORMATION. THIS SHEET MAYNOT BET RANSFERED FROM THECUSTODY OF THECOMPETENTDIV ISION O F R&D

AN D TRADE SECRET INFORMATION. THIS SHEET MAYNOT BET RANSFERED FROM THECUSTODY OF THECOMPETENTDIV ISION O F R&D DEPARTMENTEXCEPT AS AUTHORIZEDBY COMPAL ELECTRONICS, IN C . NEITHERTHISSHEET NOR THEINFORMATION IT CONTAINS

DEPARTMENTEXCEPT AS AUTHORIZEDBY COMPAL ELECTRONICS, IN C . NEITHERTHISSHEET NOR THEINFORMATION IT CONTAINS

DEPARTMENTEXCEPT AS AUTHORIZEDBY COMPAL ELECTRONICS, IN C . NEITHERTHISSHEET NOR THEINFORMATION IT CONTAINS MAYBE USED BY OR DISCLOSED TO A NY THIRD PA R T Y WITHOUT PRIOR WRITTENCONSENT OF COMPALELECTRONICS, IN C .

MAYBE USED BY OR DISCLOSED TO A NY THIRD PA R T Y WITHOUT PRIOR WRITTENCONSENT OF COMPALELECTRONICS, IN C .

5

4

MAYBE USED BY OR DISCLOSED TO A NY THIRD PA R T Y WITHOUT PRIOR WRITTENCONSENT OF COMPALELECTRONICS, IN C .

3

2018/04/09 2019/04/09

Compal Secret Dat a

Deciphered Date

Compal Electronics, Inc.

Tit le

PWR- BATTERY CONN/OTP

Size Document Number Rev

Custom

Date: Sheet o f

2

Date: Sheet o f

LA-H101PLA-H101PLA-H101P

41 54Thursday, September 20, 2018

1

41 54Thursday, September 20, 2018

0.A0.A0.A

A

Module model information

ISL95520A_Hybrid_Boost_V2.mdd

Protection for reverse input

1 1

1 2

PR30 1

1M_0402_1%

Need check t he SOA for inrush

+19V_VIN

2 2

PR306

287K_0402_1%

PR729 and PR732 areA CD ET set t i n g b a s e o n yourproje c t to s e t.

0x3CH <BIT9> PSYS current gain Rs1 = 10mΩ and Rs2 = 5mΩ or Rs 1 = 10m Ω a nd R s2 = 10mΩ BIT0 = 1.14uA/W BIT1 = 0.285uA/W ======================================================== = Rs1 = 20mΩ and Rs2 = 10mΩ or Rs 1 = 20m Ω a nd Rs2 = 20mΩ BIT0 = 2.28uA/W BIT1 = 0.57uA/W

Ipsys = KPSYS x ( VAD P x IAD P + VBA T x IBAT ) R_Psys = 1.2V / Ipsys KPSYS = 1.14uA/W adapter wattage = 45W Battery wattage = 40Wh Ipsys = 1.14 x (45+40) = 96.9uA

3 3

R_Psys = 1.2V / 96.9uA = 12.3K-ohm. ===================================== adapter wattage = 65W Battery wattage = 40Wh Ipsys = 1.14 x (65+40) = 119.7uA R_Psys = 1.2V / 96.9uA = 10K-ohm.

**Design Notes** For 45W/65W /90W system, 2S/3S/4S battery Maximum Charging current 3.5A Maximum Battery discharge power 55W #Register Setting

1. 0X3DH bit10 s et 0 (default 1) to enable turbo boost function

2. Disable turbo when AC only #Circuit Design

1. ACLIM and CCLIM are devider voltage control.

2. Use 7X7 choke and 3X3 H/L side MOSFET Charge current 3A Power loss : 1.79W (H/S=0.227W,L/S=1.2738W,Choke=0.297W) Power density : 0.61 (23X16) #Protect function

1. ACOVP : VCC voltage > 2 4V

2. SMBus timeout : 0X3DH bit15 set 0 (default 0) to enable 175s(default).

3. ACOC : OX3CH bit4 set1 release adapter limit function (default:Enable).

4. CHGOCP : based o n charge current setting

5. BATOVP : 4.6V/Cell

6. BATLOWV : No .

4 4

7. TSHUT : 150C

  

(Rs1 = 10mΩ and Rs2 = 5mΩ or Rs 1 = 20mΩ a nd Rs2 = 10mΩ). CC_LIM = VccLIM / 64 x Rs2 =========================================================== == (Rs1 = 10mΩ and Rs2 = 10mΩ or Rs 1 = 20mΩ and Rs2 = 20mΩ ) . CC_LIM = VccLIM / 32 x Rs2 =========================================================== == AC_LIM = Vac_LIM / 32 x Rs1

VCIN1_AC_IN<34>

A

VDD_CHG

12

PR311

100K_0402_1%

12

PR314

VCOUT1_PROCHOT#<34>

158K_0402_1%

Vgs = 2 0V Vds = 60 V Id = 250mA

1 2

PR30 2

3M_0402_5%

PQ31 1 EMB04N03H 1N EDFN5X6-8

5

4

12

PR310

EC_SMB_DA1<34,41>

EC_SMB_CK1<34,41>

ASGATE_CHG_R

12

49.9K_0402_1%

ACIN_CHG BST_CHG_R

AD P _ I<34>

PC31 6

0.1U_0402_25V6

Close to EC.

13

D

2

PQ314

G

S TR2N7002KW 1N SOT323- 3

S

1 2 3

12

PR307 4.02K_0402_1%

PC306

2200P_0402_50V7K

support Turbo boost : 2200P no support Turbo boost : 0.1u

PR31 2 0_0402_5%

PR32 0 0_0402_5%

PR31 6 0_0402_5%

PR31 8 1K_0402_1%

PR32 1 1K_0402_1%

Close to EC.

12

PC31 7

0.1U_0402_25V6

Follow adapter and battery wattage in Vsys current source. Base on CPU Core VR design. The resistor is pop on CPU VR schematic.

VDD=5V

Battery current limimed by CCLIm ~ 3.89A. Adapter current limimed by ACLIm ~ 4.33A. (PR779 and PQ741 are for change ACLIm when AC in)

B

Rds(on) = 15.8mohm max Vgs = 20V Vds = 30 V ID = 10.5A (Ta=70C)

+19V_P1

PQ31 2

AON7506_DFN33-8-5

1 2 3 5

4

PR308 4.02K_0402_1%

1 2

VDD_CHG

12

PR327

PR326

PR334

200K_0402_1%

12

PR33 5 348K_0402_1%

76.8K_0402_1%

Hybrid boost power mode Cell = 3s

B

+19V_P2

@

PC32 3

1 2

0.1U_0402_25V6

CMSRC_CHG

ASGATE_CHG

BMON_ISL95520

ACLIM_CHG

PROG_CHG

12

PR333

182K_0402_1%

C

max Power loss 0.22W for 90W;0.12W for 65W system;0.05W for 45W CSR rating: 1W VCSIP-VCSIN spec < 81mV

1

ACI N

2

ACO K

3

SDA

4

SCL

5

PROCHOT#

6

AMO N

7

BMON

8

PSYS

33

CCLIM_CHG

COMP_CHG

12

1

2

CSIP_CHG_R

12

PR304

0_0402_5%

CSIP_CHG

32

CSIP

PROG

AGND

9

PC320

560P_0402_50V7K

PR30 3

0.01_1206_1%

4

3

CSIN_CHG_R

12

PR305

2_0402_5%

PC30 5

1 2

0.1U_0402_25V6

12

PC307 0.22U_0603_25V7K

CSIN_CHG

31

10

12

CSIN

PR330

30

ASGATE

CCLIM11COMP

499_0402_1%

PC321

0.015U_0402_25V7K

OPCN_CHG

28

29

OPCN

CMSRC

FSET12BATGONE13CSON14CSOP

12

FSET_CHG

12

PR331

38.3K_0402_1%

OPCP_CHG

27

PR325 10K_0402_1%

@

PC32 4

1 2

0.1U_0402_25V6

100_0402_1%

BGATE_CHG

VBAT_CHG

PU30 1

25

26

ISL95520AHRZ-T_QFN32_4X4

VBAT

QPCP

15

16

BGATE

BOOT

UGATE

PHASE

LGATE

VD DP

DCIN

ACLIM

VD D

NTC

CSOP_CHG

24

23

22

21

20

19

18

17

BST _CHG

UG_CHG

LX_CHG

LG_CHG

VDDP_CHG

VDD_CHGAMON_ISL95520

PR32 3

12

100K_0402_1%

PC318

Fs=729KHZ ~ +/- 15%

CSON_CHG

BATGONE(BATT_TEMP) logic high: above 2.4V logic low: under 0.8V

VCIN 1_BAT T_ TEMP <34,41>

Security Classification

Securit y Classification

Issued Date

THISSHEET OF ENGINEERING DRAWINGIS THE PROPRIETARYPROPER TYOF COMPALELECTRONICS,INC. AND CONTAINSCONFIDENTIAL

THISSHEET OF ENGINEERING DRAWINGIS THE PROPRIETARYPROPER TYOF COMPALELECTRONICS,INC. AND CONTAINSCONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET M AY NOT BE TRANSFERED FROMTHE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET M AY NOT BE TRANSFERED FROMTHE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET M AY NOT BE TRANSFERED FROMTHE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONI T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONI T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONI T CONTAINS MAY BE USEDB Y OR DISCLOSEDTO ANY THIRDP A R T Y WITHOUTPR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS,I N C .

MAY BE USEDB Y OR DISCLOSEDTO ANY THIRDP A R T Y WITHOUTPR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS,I N C .

PR30 9

1 2

PR31 3 0_0603_5%

1 2

PR32 4 10_1206_5%

1 2

VF = 0.38V

1 2

1U_0603_25V6

B+

12

PC301

10U_0603_25V6M

Rds(on) = 32mohm max Vgs = 20 V Vds = 30V ID = 8A (Ta=70C)

1 2

PR31 9 4.7_0402_5%

12

PC31 3 1U_0402_16V6K

PD30 1

1

LRB715FT1G_SOT323-3

1 2

12

PC31 9

0.1U_0402_25V6

1 2

2014/11/05 2014/12/15

C

12

@EMI@

PC302

PC303

0.1U_0402_25V6

10U_0603_25V6M

+12.6V_BATT+

PC30 9

0.22U_0603_25V7K

1 2

12

PC31 4 1U_0402_16V6K

3

+19V_VIN

2

BA

PR32 8 2_0402_5%

PR33 2 0_0402_5%

Compal Secret D ata

Compal Sec ret Dat a

3,42] VCOUT1_PROCHOT#

B[3+

B+

[33,42] VCIN1_AC_IN

EMI@

12

PC304

2200P_0402_25V7K

PQ31 3 AON7506_DFN33-8-5

Rds(on) = 32mohm max Vgs = 20V Vds = 30V ID = 8A (Ta=70C)

PQ30 1

AON7408L_DFN8-5

3 5

241

5

PQ30 2

4

A31 connect to BA Other team connect to bat t conn

CSOP_CHG_R

CSON_CHG_R

Deciph ered Date

123

12

PR317

RF@

12

PC315

AON7506_DFN3X3-8-5

RF@

4.7UH_5.5A_20%_7X7X3_M

4.7_1206_5%

680P_0402_50V7K

2

1 2 35

4

PC30 8

1 2

0.1U_0402_25V6

@

7X7X3 Isat: 6.5A DCR: 28mohm

PL30 1

1 2

D

+3 VS

Pul l high on H W side

12

VGA@

PR1681 10K_0402_5%

1

VGA@

PQ16 61 SSM3K35MFV 1N VESM

3

VGA@

PQ1660B

34

D

5

G

2N7002KDW_SOT363-6

S

PR31 5

+12.6V_BATT _C HG

0.01_1206_1%

1

2

PM_SLP_S4#<10,34,45>

LTC015EUBFS8TL_UMT3F

For A31 only. Turn off Charger IC on battery only. Depend on customer design for system power consumption.

Title

PWR_CHARGER

Siz e Document Numb er Rev

Size Document Number Rev

Siz e Document Numb er Rev

Date: Sheet of

Date: Sheet o f

Date: Sheet of

VGA@

PR1680 10K_0402_5%

VGA@

PQ1660A

61

D

2

G

2N7002KDW_SOT363-6

S

Support max charge 3.5A Power loss: 0.245W CSR rating: 1W VCSPP-VCSON spec < 81mV

4

3

12

PC311

PC310

Compal Electronics, Inc.

PC312

10U_0603_25V6M

PQ31 5

LMUN5113T1G_SOT323-3

2

PQ31 6

LA-H101PLA-H101PLA-H101P

D

GPU_PROHOT# [24,33]

+12.6V_BATT+

12

PC322

10U_0603_25V6M

2

13

1 3

BA

42 54Thursday, September 20, 2018

0.A0.A0.A

A

Module model information

SY8286B_V3_single.mdd SY8286B_V3_dual.mdd

B

C

D

E

EMI@

B+

1 1

Check pull up resistor of SPOK a t HW side

3V/5VALW_PG<34,37,45>

2 2

3 3

Module model information

SY8286C_V3_single.mdd SY8286C_V3_dual.mdd

PR410 499K_0402_1%

ENLDO_3V5V

2

B+

4 4

1

12

PR411 150K_0402_1%

12

EC_ON<34>

VCOUT0_MAIN_PWR_ON<34>

A

PL401

5A_Z80_0805_2P

1

2

12

PC402

@EMI@

12

PC403

PC404

2200P_0402_50V7K

EMI@

0.1U_0402_25V6

+3VL

12

PR403

100K_0402_5%

ENLDO_3V5V

Fsw : 600K Hz EN1 a nd EN2 dont't b e floating. EN :H>0.8V ; L<0.4V

B+

PC434 1U_0201_6.3V6M

PL403

EMI@

5A_Z80_0805_2P

1 2

PR413 0_0402_5%

1 2

PR412

2.2K_0402_5%

1 2

12

+19VB_5V

PC414

PR415

1M_0402_1%

10U_0603_25V6M

12

10U_0603_25V6M

12

PC439

10U_0603_25V6M

12

PC415

10U_0603_25V6M

5V_3V_EN

PC438

4.7U_0402_6.3V6M

5

LX

PU401 SY8386BRHC_QFN16_2P5X2P5

6

GND

7

PG

8

EN2

LX_5V

SPOK_5V

12

PR407

0_0402_5%

3V/5VALW_PG

ENLDO_3V5V

5V_3V_EN

4

IN3

EN1

9

6

7

8

9

10

12

LX_3V

5V_3V_EN

+19VB_5V

12

PC417

PC416

0.1U_0402_25V6

2200P_0402_50V7K

EMI@

@EMI@

EN1 a nd EN2 dont't b e floating. EN :H>0.8V ; L<0.4V

Fsw : 600K Hz

B

3

IN2

FF

10

PU402 SY8288CRAC_QFN20_3X3

5

LX

GND

PG

NC

11

2

11

EN112EN2

1

BS

IN1

EP

LX2

LX1

GND 1

LDO

TEST

OUT

12

2

1

IN

IN3IN4IN

BS

LX

GND

VCC

NC

GND

FF13OUT14LDO

15

12

PC425

4.7U_0402_6.3V6M

PC427

1000P_0402_25V8J

1

Secu rity Classification

THIS SHEET OF ENGINEERING DRAWING IS THEPROPRIETARYPROPERTY OF COMPALELECTRONICS,I N C . A ND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THEPROPRIETARYPROPERTY OF COMPALELECTRONICS,I N C . A ND CONTAINS CONFIDENTIAL AN D TRADE SECRET INFORMATION. THIS SHEET MAYNOT BETRANSFEREDFRO M THECUSTODY OF THE COMPETENT DIVISION OF R&D

AN D TRADE SECRET INFORMATION. THIS SHEET MAYNOT BETRANSFEREDFRO M THECUSTODY OF THE COMPETENT DIVISION OF R&D

AN D TRADE SECRET INFORMATION. THIS SHEET MAYNOT BETRANSFEREDFRO M THECUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENTEXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, IN C . NEITHERTHISSHEET NOR THEINFORMATION IT CONTAINS

DEPARTMENTEXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, IN C . NEITHERTHISSHEET NOR THEINFORMATION IT CONTAINS

DEPARTMENTEXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, IN C . NEITHERTHISSHEET NOR THEINFORMATION IT CONTAINS MAYBE USED BY OR DISCLOSED TO A NY THIRD PA R T Y WITHOUTPRIOR WRITTENCONSENT OF COMPALELECTRONICS, I N C .

MAYBE USED BY OR DISCLOSED TO A NY THIRD PA R T Y WITHOUTPRIOR WRITTENCONSENT OF COMPALELECTRONICS, I N C .

BST_3V

17

16

15

14

13

PC412 1000P_0402_50V7K

BST_5V

20

19

18

17

16

21

5V L DO 150mA~300mA

5V_FB_15V_FB

2

Is s u ed Date

PR401 0_0402_5%

1 2

kee p short pad, snubber is for EMI only.

12

@

PC409

4.7U_0402_6.3V6M

3.3V LDO 150mA~300mA

1 2

VCC_5V

4.7U_0402_6.3V6M

PR404

1K_0402_1%

3V_FB_13V_FB

1 2

keep short pad, snubber is for EMI only.

PR405 0_0402_5%

1 2

PC418

4.7U_0402_6.3V6M

BST_5V_RBST_5V_R

1 2

+5VL P

PR408

1K_0402_1%

1

2

2018/04/09 2019/04/09

C

BST_3V_R+19VB_3V

PC410

PC401

0.1U_0402_25V6

1

LX_3V

+3VL P

PC413

0.1U_0402_25V6

1 2

LX_5VLX_5V

RF@

2

Use 7x7x3 size when the layout space is enough.

PL402

1.5UH_6A_20%_5X5X3_M

1

2

1

RF@

PR402

4.7_1206_5%

2

3V_SN

12

4

3

12

Vout is 3.234V~3.366V

RF@

PC411

680P_0402_50V7K

PL404

S COIL2.2UH +-20% 7.8A 7X7X3 MOLDING

1

2

1

PR406

2

4.7_1206_5%

5V_SN

12

PC426

680P_0402_50V7K

+5VALWP

Compal Secret Data

Deciphered Date

4

3

TDC=6A

12

PC419

22U_0603_6.3V6M

Vout is 4.998V~5.202V

TDC=9A

D

+3VA LWP

12

PC405

22U_0603_6.3V6M

12

PC406

22U_0603_6.3V6M

PC408

PC407

22U_0603_6.3V6M

Iocp=10A

PJ401

@

2

112

JUMP_43X118

PJP401

@

JUMP_43X39

112

2

+3VALW+3VALWP

+3VL+3VLP

+5VA LWP

12

PC420

22U_0603_6.3V6M

12

PC422

PC421

22U_0603_6.3V6M

PC423

PC424

@

22U_0603_6.3V6M

Iocp>12A

PJ402

@

1

2

1

2

JUMP_43X118

PJP402

@

JUMP_43X39

2

112

Compal Electronics, Inc.

Tit le

+3VALW/+5VALW

Size Document Number Rev

Custom

Date: Sheet o f

LA-H101PLA-H101PLA-H101P

E

+5VALW+5VALWP

+VL+5VLP

43 54Thursday, September 20, 2018

0.A0.A0.A

5

4

3

2

1

Module model information

RT8207P_single_V3.mdd For Single layer RT8207P_dual_V3.mdd For Dual layer

D D

Pin19 need pull separate from +1.35VP. If you have +1.35V and +0.675V sequence question,

PL501

EMI@

22U_0603_6.3V6M

12

5A_Z80_0805_2P

1 2

12

PC511

22U_0603_6.3V6M

12

PC515

22U_0603_6.3V6M

12

PC501

0.1U_0402_25V6

@EMI@

PL502

1UH_6.6A_20%_5X5X3_M

1

2

4

3

RF@

680P_0402_50V7K

+12.6VB_DDR

12

PC504

PC503

PC502

EMI@

2200P_0402_50V7K

PR503

4.7_1206_5%

PC518

Choke: 7x7x3 Rdc=6.7mohm(Typ), 7.4mohm(Max)

Switching Frequency:540kHz Ipeak=8A Iocp~9.6A OVP: 113%~120% VFB=0.75V, Vout=1.3545V

10U_0603_25V6M

AON7408L_DFN8-5

12

AON7506_DFN3X3-8-5

PQ501

PQ502

123

3 5

241

5

4

12

0.1U_0402_25V6

+5VALW

PC505

1U_0201_6.3V6K

PR504

5.1_0603_5%

1 2

PC517

BST_DDR_R

+5VALW

12

2.2_0603_5%

1 2

PR502

14.7K_0402_1%

1 2

1U_0201_6.3V6K

1 2

PD50130MA_30V_0.5UA_0.4V_SOD323-2

2 1

VDD_DDR

1 2

2.2_0603_5%

SYSON<13,34>

SUSP#<13,34,39>

PR501

LG_DDR

CS_DDR

PC509

PR505

+12.6VB_DDR

B+

C C

+1.2VP

12

PC512

PC510

22U_0603_6.3V6M

B B

Mode Level +0.675VSP VTTREF_1.35V S5 L off off S3 L off on S0 H on on

Note: S3 - sleep ; S5 - power of f

12

PC514

PC513

22U_0603_6.3V6M

DDR_VTT_PG_CTRL

A A

you can change from +1.35VP to +1.35VS.

BST_DDR

UG_DDR

LX_DDR

16

18

PU501

15

14

13

12

11

PR507 470K_0402_1%

1 2

PHASE

LGATE

PGN D

CS

RT8207PGQW_W QFN20_3X3

VDDP

VDD

PGOOD

10

PR508

0_0402_5%

1 2

@

0.1U_0402_10V7K

@

PR510

1 2

PR511

0_0402_5%

1 2

PC519

17

UGATE

TON

9

TON_DDR

0_0402_5%

8

EN_DDR

12

19

BOOT

S5

7

EN_0.675VSP

12

20

21

VTT

PAD

VTT GND

VTT SNS

GND

VTT REF

VDDQ

FB

6

FB_DDR

1

2

3

4

5

VLDOIN

S3

+1.2VP +1.2V

PC520

@

0.1U_0402_10V7K

+0.6VSP +0.6VS

VTTREF_DDR

1 2

12

PR509 10K_0402_1%

+1.2VP

PR506

6.04K_0402_1%

JUMP_43X118

12

PC506

PJ501

@

112

PJ502

@

112

JUMP_43X39

22U_0603_6.3V6M

2

0.675Volt +/- 5% TDC 0.7A Peak Current 1A

+0.6VSP

12

PC516

0.033U_0402_16V7K

+1.2VP

Security Classification

Issued Date

THI S SHEE T OF ENGINEERING DRAWING IS THE PROPRIETARY PR OPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THI S SHEE T OF ENGINEERING DRAWING IS THE PROPRIETARY PR OPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECR ET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF T HE COM PETENT DIVISION OF R&D

AND TRADE SECR ET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF T HE COM PETENT DIVISION OF R&D

AND TRADE SECR ET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF T HE COM PETENT DIVISION OF R&D DEPARTMENT EX CEPT AS A UTHORI ZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR T HE INFORMATION IT CO NTAINS

DEPARTMENT EX CEPT AS A UTHORI ZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR T HE INFORMATION IT CO NTAINS

DEPARTMENT EX CEPT AS A UTHORI ZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR T HE INFORMATION IT CO NTAINS MAYBE USED BY OR DISCL OSED TO A NY THIRD P A R T Y WITHOUT PRI OR WRI TTEN CONSENT OF COM PAL ELECTRONICS, INC.

MAYBE USED BY OR DISCL OSED TO A NY THIRD P A R T Y WITHOUT PRI OR WRI TTEN CONSENT OF COM PAL ELECTRONICS, INC.

5

4

2018/04/09

3

Compal Secret Data

Deciphered Date

2019/04/09

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

RT8207P

Custom

Thursday, September 20, 2018

LA-H101PLA-H101PLA-H101P

1

o f

44 54

0.A0.A0.A

5

4

3

2

1

Module model information

APL5930_V2.mdd

D D

+3VALW

JUMP_43X79

PJ601

@

C C

0_0402_5%

3V/5VALW_PG<34,37,43>

1 2

PR601

PR603

1M_0402_5%

@

4.7U_0402_6.3V6M

PC602

12

PC605

@

0.1U_0402_16V7K

+3VALW

B B

JUMP_43X79

PC608

@

4.7U_0402_6.3V6M

PR606

0_0402_5%

PM_SLP_S4#<10,34,42>

A A

1 2

47K_0402_5%

PR608

12

1

2

PJ603

@

2

12

PC609

12

10U_0402_6.3V6M

PC611

0.1U_0402_16V7K

1

2

12

PC603

+5VALW

1

2

10U_0402_6.3V6M

PR604 100K_0402_5%

1 2

+5VALW

PC607

2.2U_0201_6.3V6M

1 2

PU602 IC APL5934BKAI-TRG SOP 8P LDO

4 3 2 1

PC601 1U_0402_6.3V6K

1 2

PGOOD <46>

VPP VIN VEN POK

GND

9

PU601 APL5934BKAI-TRG SOP8P

4

VPP

3

VIN

2

VEN

1

POK

GND

9

5

NC

6

VO

7

ADJ

8

GND

Ultra Low Dropout 0.23V(typical) at 3A Output Current

5

NC

6

VO

GND

ADJ

7 8

Rup

Rdown

12

PC604

PR602

12.7K_0402_1%

12

PR605

10K_0402_1%

12

0.01U_0402_16V7K

+1.8VALWP

PC606

22U_0603_6.3V6M

Vout=0.8V* (1+Rup/Rdown)

+2.5VP

PC612

22U_0603_6.3V6M

+2.5VP +2.5V

Rup

Rdown

12

PC610

PR607

3.4K_0402_1%

12

PR609

1.6K_0402_1%

12

0.01U_0402_16V7K

PJ602

+1.8VALWP +1.8VALW

PJ604

@

2

112

JUMP_43X79

@

112

JUMP_43X79

2

Secu rity Classif ication

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THEPROPRIETARYPR OPERTYOF COMPALELECTRONICS,I N C . A ND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THEPROPRIETARYPR OPERTYOF COMPALELECTRONICS,I N C . A ND CONTAINS CONFIDENTIAL AN D TRADE SECRET INFORMATION. THISSHEET MAY NOTBE TRANSFEREDFR OM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AN D TRADE SECRET INFORMATION. THISSHEET MAY NOTBE TRANSFEREDFR OM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AN D TRADE SECRET INFORMATION. THISSHEET MAY NOTBE TRANSFEREDFR OM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENTEXCEPT A S AUTHORIZED BY COMPAL ELECTRONICS, IN C . NEITHERTHISSHEET NOR THEI N F O R M A T I O N IT CONTAINS

DEPARTMENTEXCEPT A S AUTHORIZED BY COMPAL ELECTRONICS, IN C . NEITHERTHISSHEET NOR THEI N F O R M A T I O N IT CONTAINS

DEPARTMENTEXCEPT A S AUTHORIZED BY COMPAL ELECTRONICS, IN C . NEITHERTHISSHEET NOR THEI N F O R M A T I O N IT CONTAINS MAYBE USED BY OR DISCLOSED T O AN Y THIRD PA RT Y WITHOUT PRIOR WRITTEN CONSENT OF COMPALELECT RONICS, IN C .

MAYBE USED BY OR DISCLOSED T O AN Y THIRD PA RT Y WITHOUT PRIOR WRITTEN CONSENT OF COMPALELECT RONICS, IN C .

5

4

MAYBE USED BY OR DISCLOSED T O AN Y THIRD PA RT Y WITHOUT PRIOR WRITTEN CONSENT OF COMPALELECT RONICS, IN C .

3

2018/04/09 2019/ 04/09

Compal Secret Da ta

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

APL5930

LA-H101PLA-H101PLA-H101P

45 54Thursday, September 20, 2018

1

45 54Thursday, September 20, 2018

0.A0.A0.A

of

A

Module model information

SY8286_V2_single.mdd SY8286_V2_dual.mdd

B+

1 1

EN :H>0.8V ; L<0.4V

EN pin don't floating If have pull down resistor at H W side, please delete PR601.

2 2

+3VALW

Confirm H W side

12

PR701

@

100K_0402_5%

PR705

0_0402_5%

PGOOD<45>

1 2

1M_0402_1%

PR707

@

PJ701

112

JUMP_43X79

12

@

0.1U_0402_25V6

+19VB_1V

2

PC701

EMI@

PC712

12

2200P_0402_50V7K

12

PC703

0.1U_0402_25V6

@EMI@

+3VALW

12

0_0402_5%

12

@

0_0402_5%

PR709

PR710

B

+19VB_1V

12

PC705

LX_1V

10U_0603_25V6M

EN_1V

ILMT_1V

5

LX

6

GND

7

PG

8

TEST

4

PU701

S IC SY8386RHC QFN 16P PWM

EN

9

10

1

2

IN23IN3

BS

IN1

BYP

FB11ILMT

12

GND1

VCC

LX2

LX1

EP

17

16

15

14

13

+3VALW

12

PC713

2.2U_0402_6.3V6M

C

keep short pad, snubber is for EMI only.

BST_1V_RBST_1V

PC704

0.1U_0402_25V6

1 2

RF@

PR703

@

0_0402_5%

1 2

PR702

4.7_1206_5%

1 2

D

SNUB_1V

RF@

PC702

680P_0402_50V7K

1 2

E

Use 7x7x3 size when the layout space is enough.

PL701

1 2

1UH_6.6A_20%_5X5X3_M

FB=0.6V

R1

R2

12

PR704

12

PR708 22K_0402_1%

+1.05VALWP

12

PC707

PC706

330P_0402_50V7K

16.5K_0402_1%

12

PR706 1K_0402_1%

22U_0603_6.3V6M

12

PC708

22U_0603_6.3V6M

+1.05VALW P

12

PC709

PC710

22U_0603_6.3V6M

PJ702

@

JUMP_43X118

2

112

+1.05VALW

LDO_3V

PC711

4.7U_0402_6.3V6M

1 2

LX_1V

FB_1V

Vout=0.6V* (1+R1/R2)

=0.6*(1+(16.5/22))

Vout=1.05V

The current limit is se t to 6 A, 9A o r 12A when this p in is pull low, floating or pull high.

+1.2V

+5VALW

1

PJ703

@

PR712

JUMP_43X39

VGA@

PC715

10U_0402_6.3V6M

12

2

12

PC716

@

0.1U_0402_25V6

B

3 3

PR711

@VGA@

0_0402_5%

[26] 1.0VS_DGPU_EN

4 4

A

1 2

VGA@

1M_0402_5%

12

1

2

PC714

VGA@

2.2U_0201_6.3V6M

10

VPP

9

NC

8

VIN

7

VIN VEN6POK

Ultra Low Dropout 0.23V(typical) at 3A Output Current

VGA@

11

G9661MRE1U_TDFN10_3X3PU702

1

NC

2

VO

GND

3

VO

4

ADJ

5

Vout=0.8V* (1+Rup/Rdown)

12

PR713

Rup

Rdown

10K_0402_1%

VGA@

12

PR714

38.3K_0402_1%

VGA@

=0.8*(1+(10/38.3))

12

PC717

0.01U_0402_25V7K

VGA@

+1.0VS

PC718

22U_0603_6.3V6M

VGA@

Vout=1.008V

Securit y Class ificati on

Iss ued Date

TH IS SHEET OF ENGINEERING DRAWING IS TH E PROPRIETARYPROPERTY OF COMPAL ELECTRONICS, INC . AND CONTAINS CONFIDENTIAL

TH IS SHEET OF ENGINEERING DRAWING IS TH E PROPRIETARYPROPERTY OF COMPAL ELECTRONICS, INC . AND CONTAINS CONFIDENTIAL AND TR A D E SECRETINFO RMATION. TH I S SHEET MAY NOT BE TRANSFERED FROM TH E CUSTODY OF TH E COMPETENTD IVISION OF R&D

AND TR A D E SECRETINFO RMATION. TH I S SHEET MAY NOT BE TRANSFERED FROM TH E CUSTODY OF TH E COMPETENTD IVISION OF R&D

AND TR A D E SECRETINFO RMATION. TH I S SHEET MAY NOT BE TRANSFERED FROM TH E CUSTODY OF TH E COMPETENTD IVISION OF R&D DEPARTMENTEXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, I NC . NE ITHER TH I S SHEET NOR TH E INF O RM AT IO N IT CONTAINS

DEPARTMENTEXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, I NC . NE ITHER TH I S SHEET NOR TH E INF O RM AT IO N IT CONTAINS

DEPARTMENTEXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, I NC . NE ITHER TH I S SHEET NOR TH E INF O RM AT IO N IT CONTAINS MAYBE US ED BY OR DISCLOSEDT O ANY THIRD PA R T Y WITHOUTPRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC .

MAYBE US ED BY OR DISCLOSEDT O ANY THIRD PA R T Y WITHOUTPRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC .

C

2018/04/09 2019/04/09

+1.0VS

Compal Secret D ata

Deciphered Date

D

PJ704

@

112

JUMP_43X39

2

+1.0VS_DGPU

Compal Electronics, Inc.

Ti t l e

SY8286

Size

Document Number Rev

C

Date: Sh ee t

LA-H101PLA-H101PLA-H101P

E

0.A0.A0.A

of

46 54Thursday, September 20, 2018

1

2

3

4

5

Close IC

RT3602_VREF

12

953_0402_1%

A A

B B

PRZ2

12

PRZ5

5K_0402_1%

12

PRZ17

464_0402_1%

12

PRZ28

3K_0402_1%

VCCCORE_SENSE<15>

PRZ41 and PRZ21 are for debug only. VCCCORE_SENSE and VSSCORE_SENSE need other resistor at HW side.

Vref=0.6V

12

PRZ4

PRZ3

15K_0402_1%

6.8K_0402_1%

12

PRZ6

PRZ11

10_0402_1%

RT3602_SET1

11K_0402_1%

RT3602_SET2 RT3602_SET3

VR_PSYS

12

PRZ18

PRZ19

PRZ20

@

12

10K_0402_1%

1.1K_0402_1%

5.23K_0402_1%

12

PRZ30

PRZ29

499_0402_1%

2.1K_0402_1%

0.1U_0402_25V6

12

Close IC

+VCC_CORE

1 2

PCZ7

@

PRZ41 100_0402_1%

PRZ47 0_0402_5%

VSSSA_SENSE

12

VSEN _C ORE

12

PCZ196

@

0.1U_0402_25V6

VCCSA_SENSE

RGND_MAIN

PCZ204

@

0.1U_0402_25V6

Ra Rb/R c

U22

N/A

Stuff

U42

C C

N/AStuff

+VCC_SA

RT3602_VREF

PRZ40

@

PCZ8

@

10K_0402_1%

0.1U_0402_10V6K

1 2

PRZ43 10K_0402_1%

1 2

PCZ11

330P_0402_50V8J

TSEN_CORE_R TSEN _GT_ R

PRZ1

100_0402_1%

1 2

PRZ15

1 2

0_0402_5%

PRZ94

Close IC

0_0402_5%

1 2

PRZ22

1 2

100_0402_1%

Close CORE1 choke

PRZ107

0_0402_5%

1 2

U42 @

PRZ45

61.9K_0402_1%

1 2

PCZ12 82P_0402_50V8J

1 2

AVCO RE1<48>

AVCO RE2<48>

+5VALW

RT3602_VREF

12

PRZ64

8.25K_0402_1%

PRZ63

8.25K_0402_1%

12

PRZ67

PRZ68

7.68K_0402_1%

4.64K_0402_1%

12

PRZ71

PRZ70

19.1K_0402_1%

5.62K_0402_1%

12

PRZ74

PRZ73

11.5K_0402_1%

4.02K_0402_1%

VCCSA_SENSE_R

12

PCZ200

@

0.1U_0402_25V6

12

@

0.1U_0402_25V6

PHZ1

100K_0402_1%_B25/50 4250K

PHZ1_R1

Rb

1 2

PRZ105 10K_0402_1%U22 @

PRZ1 and PRZ22 are for debug only. VCCSSA_SENSE and VSSSA_SENSE need other resistor at HW side.

PRZ35

8.87K_0402_1%

Ra

ISEN1N_MAIN

Rc

PRZ52

1.65K_0402_1%

1 2

PRZ72

@

PRZ75

PCZ6 68P_0402_50V8J

FB_SAFB_SA

Close IC

PRZ95

0_0402_5%

1 2

IMON_CORE RT3602_SET1

COMP_CORE RT3602_SET2 RT3602_SET3

TSEN_CORE

12

PRZ53

2.2_0805_1%

+19VB_CPU

PRZ10

54.9K_0402_1%

1 2

PRZ21

1 2

100_0402_1%

12

PCZ201

@

0.1U_0402_25V6

1

IMON_MA IN

2

FB_CORE

SET1

3

FB_ MA IN

4

COMP_M AIN

5

SET2

6

SET3

7

ISEN1N_MAIN

8

ISEN2N_MAIN

9

ISEN2P_MAIN

10

ISEN1P_MAIN

11

RT3602_VIN

TSEN_MAIN

12

VIN

12

PCZ19

0.22U_0402_25V6K

+5VALW

PRZ65

8.2_0402_1%

1 2

4.7U_0402_6.3V6M

Close GT MOSFET

AVCC SA<48> AISPVCCSA <4 8>

RGND_MAIN

VSEN_CORE

VR_PSYS

47

48

49

GND

VSEN_MAIN

RGND_MAIN

13

RT3602_VCC

12

PCZ23

PRZ8 10K_0402_1%

1 2

PCZ5 390P_0402_50V7K

@

PCZ1

PRZ16

0.1U_0402_10V6K

VSSCORE_SENSE<15>

1 2

IMON_CORE_R

1 2

PRZ26

35.7K_0402_1%

PRZ51 110K_0402_1%

1 2

10K_0402_1%

1 2

PCZ9

@

0.1U_0402_10V6K

1 2

PRZ106

U42 @

1 2

0_0402_5%

1 2

PRZ104 10K_0402_1%U22 @

PHZ2

100K_0402_1%_B25/50 4250K

12

PCZ203

@

0.1U_0402_25V6

PCZ199

PHZ1_R

1 2

PRZ33

30.9K_0402_1%

PRZ45

U22 @

46.4K_0402_1%

PCZ13

0.1U_0402_25V6

1 2

U42 @

PCZ16 0.1U_0402_25V6

AISPCORE2<48>

+5VALW

AISPCORE1<48>

TSEN_CORE_R

Close CORE1 MOSFET

+5VALW

12

10K_0402_5%

DRVEN_SET

12

10K_0402_5%

Set DRVEN output function at PS4. Set to 5V DRVEN is floating, and set to GND DRVEN is low at PS4.

PCZ3

0.1U_0402_25V6

12

PCZ4

@

0.47U_0402_25V6K

1 2

12

1 2

PRZ13

29.4K_0402_1%

PRZ25 0_0402_5%

1 2

PCZ206

@

0.1U_0402_25V6

1 2

RT3602_EN

PUZ1

37

RT3602AJGQW_WQFN48_6X6

EN

36

PWM_SA

VR_READY

35

DRVEN

34

VCLK

33

ALERT

32

VDIO

31

VR_HOT

30

IMON_AUXI

29

ISENP_AUXI

28

ISENN_AUXI

27

VSEN_AUXI

26

COMP_AUXI

25

RGND_AUXI

FB_AUXI

<48>

PRZ66 110K_0402_1%

PRZ69

1.65K_0402_1%

1 2

PRZ14 21K_0402_1%

1 2

PRZ98 49.9_0402_1%

1 2

PRZ99 10_0402_1%

IMON_GT

VSEN _G T

COMP_GT

RGND_AUXI

PCZ193

0.47U_0402_25V6K

12

PRZ24

3.9_0402_1%

RT3602_VREF

IMON_SA

FB_SA

RGND_SA

COMP_SA

38

40

41

42

43

44

45

46

39

PSYS

FB_SA

IMON_SA

RGND_SA

ISENP_SA

ISENN_SA

COMP_SA

VREF06/PSET

NC21NC20NC19DRVEN_SET18NC15NC14VCC

PWM_AUXI22TSEN_AUXI

PWM1_MAIN17PWM2_MAIN

23

24

16

FB_GT

TSEN_ GT

DRVEN_SET

PWM_GT

<48>

PWM_CORE2

PWM_CORE1

12

1

2

12

PHZ3

100K_0402_1%_B25/50 4250K

TSEN_ GT_R

Module model information

RT3602AE_U22_RU42_colay_V1A.mdd for IC portion

RT3602AE_U22_RU42_colay_V1B.mdd for SW portion

RT3602_VREF

VR_O N <34>

+1.05V_VCCST

12

PRZ37

@

PRZ36

45.3_0402_1%

PWM_SA < 48> DRVEN <48>

PRZ100 100_0402_1%

1 2

PCZ18

0.1U_0402_25V6

EN High: > 0.7V Low: < 0.3V

110_0402_1%

1 2

PRZ23 100K_0402_1%

1 2

12

100_0402_1%

PRZ38

PCZ150.47U_0402_25V6K@

1 2

+3VS

VR_ PW R GD <34>

PCZ207

1 2

100P_0402_50V8J

ESD@

12

PCZ194

75_0402_1%

PRZ39

0.1U_0402_25V6

@

PRZ48

30.1K_0402_1%

1 2

PRZ54

17.4K_0402_1%

1 2

PCZ20 82P_0402_50V8J

VR_SVID_CLK <15> VR_ALERT# <15 > VR_SVID_DATA <15>

VR_ HOT # <34>

FB_GT

RT3602_VREF

PRZ49 20.5K_0402_1%

1 2

AISP 1 <48> AVGT1 <48>

PRZ56 10K_0402_1%

1 2

PCZ21

270P_0402_50V7K

1 2

PRZ61

@

10K_0402_1%

PRZ59 and PRZ60 are for debug only. VCCGT_SENSE and VSSGT_SENSE need other resistor at HW side.

PCZ22

@

0.1U_0402_10V6K

0.1U_0402_25V6

VSEN _G T

12

@

0.1U_0402_25V6

PCZ197

@

PRZ50 0_0402_5%

1 2

100_0402_1%

1 2

@

0.1U_0402_25V6

PCZ202

12

Close IC

PRZ59

PCZ198

+VCC_GT

12

Close IC

PRZ93

1 2

0_0402_5%

PRZ60 100_0402_1%

VCCGT_SENSE <1 5>

VSSGT_SENSE <15>

D D

Compal Secr et Data

Com pal Secret Da ta

4

Com pal Secret Da ta

Deciphered Date

Compal Electronics, Inc.

Ti t l e

2019/09/012016/09/01

Ti t l e

CPU_CORE

Size Document Number Rev

Date: Sheet

LA-H101PLA-H101PLA-H101P

Thursday, September 20, 2018

5

of

0.A0.A0.A

544 7

Security Classification

Is su e d Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION.THISSHEET MAY NOT BE TRANSFERED FROM THECUST ODY OF THECOMPET ENT D IVISION OF R&D

AND TRADE SECRET INFORMATION.THISSHEET MAY NOT BE TRANSFERED FROM THECUST ODY OF THECOMPET ENT D IVISION OF R&D

AND TRADE SECRET INFORMATION.THISSHEET MAY NOT BE TRANSFERED FROM THECUST ODY OF THECOMPET ENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RONICS, IN C . NEITHER THIS SHEET NOR THEINFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RONICS, IN C . NEITHER THIS SHEET NOR THEINFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RONICS, IN C . NEITHER THIS SHEET NOR THEINFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TOAN Y THIRD PART Y WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECT RONICS, IN C .

MAY BE USED BY OR DISCLOSED TOAN Y THIRD PART Y WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECT RONICS, IN C .

1

2

3

MAY BE USED BY OR DISCLOSED TOAN Y THIRD PART Y WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECT RONICS, IN C .

5

4

3

2

1

12

PCZ34

10U_0603_25V6M

U42@

0.1U_0402_25V6K

PCZ35

12

@

10U_0603_25V6M

PCZ39

1 2

PRZ85

@U42@

10_0402_1%

1 2

AISPCORE2 <47>

+19VB_CPU

+VCC_CORE

AVCORE2 <47>

+VCC_GT

B+

PRG11

2.2_0603_5%

CORE2_BST_RCORE2_BST

+5VALW

PWM_CORE2

<47>

AVGT1 <47>

AISP1 <47>

<47,48>

DRVEN

VCC_CORE2

1 2

PRG10

1_0402_5%

12

PCG11

4.7U_0402_6.3V6M

H/S AON6280: R DS(ON) (at V GS =10V) < 6.8m R DS(ON) (at V GS =4.5V) < 10.5m

L/S AON6214: R DS(ON) (at V GS =10V) < 2.8m? R DS(ON) (at V GS =4.5V) < 3.5m?

VCC_CORE FSW=450kHz Choke=0.15uH DCR=0.67 mohm +/- 5%

U22 LL=2.4 mohm TDC=21A ICCMAX=32A OCP=40A

U42 LL=2.4 mohm TDC=42A ICCMAX=64A OCP=70A

PUG3

RT9610CGQW_WDFN8_2X2

4

BOOT

UGATE

5

PWM

PHASE

1

EN

PGND

8

VCC

LGATE

GND

1 2

3

CORE2_LX

2

6

7 9

VCC_GT FSW=450kHz Choke=0.15uH DCR=0.67 mohm +/- 5%

U22 LL=3.1 mohm TDC=18A ICCMAX=31A OCP=39A

U42 LL=3.1 mohm TDC=12A ICCMAX=28A OCP=39A

12

CORE2_UG

CORE2_LG

PCG12

0.1U_0402_25V6

5

PQZ3

4

123

AON6380_DFN5X6-8-5

CORE2_LX

PQZ4

5

12

PRZ80

123

AON6314_N_DFN56-8-5

4.7_1206_5%

U42RF@

CORE2_SNUB

12

VCC_SA FSW=600kHz DCR=6.2 mohm +/- 5%

U22 LL=10.3 mohm TDC=4A ICCMAX=5A OCP=10A

U42 LL=10.3 mohm TDC=4A ICCMAX=5A OCP=10A

4

12

PCZ30

PCZ31

0.1U_0402_25V6

EMIU42@

2200P_0402_50V7K

@EMIU42@

Rdc=0.67m ohm± 5 %

PRZ82

AISPCORE2_R

1.05K_0402_1%

1 2

U42@

PCZ41

U42RF@

680P_0402_50V7K

PCZ32

12

10U_0603_25V6M

U42@

U42@ 134

2

0.15UH_NA__36A_20%

1.05K_0402_1%

1 2

U42@

PCZ33

12

@

U42@

10U_0603_25V6M

PLZ4

PRZ83

PLZ1 5A_Z80_0805_2P

+19VB_CPU

PRG9

RT9610CGQW_WDFN8_2X2

4

5

1

8

PCG10

2.2_0603_5%

1 2

PUG2

BOOT

UGATE

PWM

PHASE

EN

PGND

VCC

LGATE

GND

12

CORE1_UG

3

CORE1_LX

2

6

7 9

CORE1_LG

PCG9

0.1U_0402_25V6

5

PQZ1

4

123

AON6380_DFN5X6-8-5

PQZ2

5

4

123

12

PCZ28

0.1U_0402_25V6

@EMI@

CORE1_LX

12

PRZ78

RF@

4.7_1206_5%

AISPCORE1_R

AON6314_N_DFN56-8-5

CORE1_SNUB

12

PCZ40

680P_0402_50V7K

PCZ26

12

PCZ25

PCZ24

10U_0603_25V6M

EMI@

2200P_0402_50V7K

Rdc=0.67m o hm± 5%

PLZ3

134

2

0.15UH_NA__36A_20%

1 2

PRZ81

PRZ79

1.05K_0402_1%

RF@

12

10U_0603_25V6M

PCZ38

0.1U_0402_25V6K

1 2

PRZ84

@

560_0402_1%

1 2

CORE1_BST CORE1_BST_R

D D

<47>

PWM_CORE1

+5VALW

<47,48>

C C

DRVEN

1 2

PRG8

1_0402_5%

DRVEN

VCC_CORE1

12

4.7U_0402_6.3V6M

+VCC_CORE

PCZ191

1

+

2

33U_25V_NC_6.3X4.5

PCZ192

AVCORE1 <47>

AISPCORE1 <47>

EMI@

1 2

1

+

2

PCZ195

33U_25V_NC_6.3X4.5

PLZ2 5A_Z80_0805_2PEMI@

+

2

33U_25V_NC_6.3X4.5

+19VB_CPU

PRG1

4

5

1

8

PCG6

2.2_0603_5%

1 2

PUG1

RT9610CGQW_WDFN8_2X2

BOOT

UGATE

PWM

PHASE

EN

PGND

VCC

LGATE

GND

GT_BST_R

12

PCG1

GT_UG

3

GT_LX

2

6

7 9

0.1U_0402_25V6

GT_LX

GT_LG

AON6962_DFN5X6D-8- 7

PQG1

2

D1

S24S2

S23G2

PCG2

0.1U_0402_25V6

@EMI@

1

G1

GT_LX

7

D2/S1

12

PRG3

5

6

RF@

4.7_1206_5%

GT_SNUB

12

PCG8

680P_0402_50V7K

PCG5

PCG4

12

PCG3

10U_0603_25V6M

EMI@

2200P_0402_50V7K

Rdc=0.67m ohm± 5 %

PLG1

134

2

0.15UH_NA__36A_20%

PRG4

PRG5

1.4K_0402_1%

1 2

AISP1_R

RF@

0.1U_0402_25V6K

PRG6

3.48K_0402_1%

1 2

10K_0402_1%_B25/50 3370K

PCG7

1 2

PRG7

10K_0402_1%

1 2

AVGT1_R

PHG1

GT_BST

PWM_ GT<47>

+5VALW

B B

1 2

PRG2

1_0402_5%

VCC_GT

12

4.7U_0402_6.3V6M

DRVEN

PRA1

RT9610CGQW_WDFN8_2X2

4

5

1

8

PCA6

2.2_0603_5%

SA_BST_R

1 2

PUA1

SA_UG SA_UG_R

3

BOOT

UGATE

SA_LX

2

PWM

PHASE

6

EN

PGND

7

VCC

LGATE

9

GND

12

PCA4

0.1U_0402_25V6

SA_LG

1

3

D12D1

G1

9

D2/S1

7

8

4

SA_BST

PWM_ SA<47>

+5VALW

PRA2 1_0402_5%

A A

1 2

5

VCC_SA

12

DRVEN

4.7U_0402_6.3V6M

4

D1

S26S2

D1

10

S25G2

12

PCA1

PCA2

10U_0603_25V6M

PQA1 AONH36334_DFN3X3A8- 10

12

PRA3

RF@

4.7_1206_5%

SA_SNUB

12

680P_0402_50V7K

AISPVCCSA_R

PCA8

RF@

PCA3

@EMI@

0.1U_0402_25V6

1 2

PRA4 787_0402_1%

+19VB_CPU

12

PCA5

EMI@

2200P_0402_50V7K

1 2

PRA5 787_0402_1%

Rdc=0.98 mohm

PLA1

134

2

0.47UH_NA__12.2A_20%

PRA6

825_0402_1%

1 2

1K_0402_5%_TSM0B102J3652RE

0.1U_0402_25V6K

AVCCSA_R

3

PCA7

1 2

PRA7

1K_0402_1%

1 2

PHA1

+VCC_SA

AVCCSA <47>

AISPVCCSA <47>

Security Classification

Issued Date

THISSHEET OF ENGINEERINGDRAWING ISTHE PROPRIETARYPROPERTY OF COMPALELECTRONICS,INC.AND CONTAINS CONFIDENTIAL

THISSHEET OF ENGINEERINGDRAWING ISTHE PROPRIETARYPROPERTY OF COMPALELECTRONICS,INC.AND CONTAINS CONFIDENTIAL ANDTRADE SECRET INFORMATION.THISSHEET MAY N OT BETRANSFERED FROM THECUSTODY OF THECOMPETENT DIVISION OF R&D

ANDTRADE SECRET INFORMATION.THISSHEET MAY N OT BETRANSFERED FROM THECUSTODY OF THECOMPETENT DIVISION OF R&D

ANDTRADE SECRET INFORMATION.THISSHEET MAY N OT BETRANSFERED FROM THECUSTODY OF THECOMPETENT DIVISION OF R&D DEPARTMENTEXCEPT AS AUTHORIZEDBY COMPALELECTRONICS, INC.NEI T HER THISSHEET NO R THEINFORMATIONIT CONTAINS

DEPARTMENTEXCEPT AS AUTHORIZEDBY COMPALELECTRONICS, INC.NEI T HER THISSHEET NO R THEINFORMATIONIT CONTAINS

DEPARTMENTEXCEPT AS AUTHORIZEDBY COMPALELECTRONICS, INC.NEI T HER THISSHEET NO R THEINFORMATIONIT CONTAINS MAY BE US ED BYOR DISCLOSED TOANY THIRDPA RT Y WITHOUT PRIORWRITTENCONSENT OF COMPALELECTRONICS, INC.

MAY BE US ED BYOR DISCLOSED TOANY THIRDPA RT Y WITHOUT PRIORWRITTENCONSENT OF COMPALELECTRONICS, INC.

2

Com pal Secret D at a

Deciphered Date

2019/04/092018/04/09

Compal Electronics, Inc.

Title

CPU Power stage

Size

Document Number Rev

LA-H101PLA-H101PLA-H101P

Thursday, September 20, 2018

Date: Sheet

1

0.A0.A0.A

5448

of

A

B

C

D

E

+VCC_CORE

PC9002

22U_0603_6.3V6M

1 1

2 2

3 3

12

PC9027

22U_0603_6.3V6M

12

U42@

PC9053

22U_0603_6.3V6M

12

PC9170

22U_0603_6.3V6M

12

U42@

1U_0201_4V6M

PC9110

12

1U_0201_4V6M

PC9130

12

PC9004

PC9003

22U_0603_6.3V6M

12

U42@

22U_0603_6.3V6M

PC9028

12

22U_0603_6.3V6M

12

PC9054

22U_0603_6.3V6M

PC9171

12

U42@

22U_0603_6.3V6M

12

PC9174

1U_0201_4V6M

PC9111

12

1U_0201_4V6M

PC9131

12

22U_0603_6.3V6M

12

PC9029

PC9030

22U_0603_6.3V6M

12

PC9031

PC9056

PC9055

22U_0603_6.3V6M

12

PC9057

PC9167

U42@

22U_0603_6.3V6M

PC9112

PC9132

PC9169

22U_0603_6.3V6M

PC9168

12

U42@

22U_0603_6.3V6M

12

PC9173

PC9172

1U_0201_4V6M

PC9114

PC9113

12

1U_0201_4V6M

PC9133

PC9134

12

PC9008

PC9007

22U_0603_6.3V6M

12

PC9033

22U_0603_6.3V6M

PC9032

12

PC9064

PC9065

22U_0603_6.3V6M

12

PC9097

PC9166

22U_0603_6.3V6M

12

U42@

PC9101

220U 2V Y D2 H1.9

U42@

220U 2V Y D2 H1.9

1

+

PC9100

2

1U_0201_4V6M

PC9116

PC9115

12

1U_0201_4V6M

PC9136

PC9135

12

PC9006

PC9005

PC9010

22U_0603_6.3V6M

12

22U_0603_6.3V6M

12

22U_0603_6.3V6M

12

22U_0603_6.3V6M

12

22U_0603_6.3V6M

12

+VCC_CORE

1U_0201_4V6M

12

1U_0201_4V6M

12

PC9001

22U_0603_6.3V6M

12

22U_0603_6.3V6M

PC9036

12

PC9035

PC9067

22U_0603_6.3V6M

12

PC9068

U42@

PC9099

PC9098

22U_0603_6.3V6M

12

U42@

22U_0603_6.3V6M

12

PC9103

PC9104

1U_0201_4V6M

PC9118

PC9119

12

1U_0201_4V6M

PC9139

PC9138

12

PC9011

PC9012

PC9013

22U_0603_6.3V6M

12

PC9037

PC9038

22U_0603_6.3V6M

12

PC9058

PC9059

22U_0603_6.3V6M

12

22U_0603_6.3V6M

12

PC9087

PC9086

1

+

PC9105

2

220U 2V Y D2 H1.9

SGA20221D40

0.47U_0201_6.3V6K

1U_0201_4V6M

PC9120

PC9121

12

PC9014

22U_0603_6.3V6M

12

PC9040

PC9039

22U_0603_6.3V6M

12

PC9060

PC9061

22U_0603_6.3V6M

12

22U_0603_6.3V6M

12

PC9089

PC9088

@

1U_0201_4V6M

PC9123

PC9122

12

PC9016

PC9015

22U_0603_6.3V6M

12

22U_0603_6.3V6M

12

22U_0603_6.3V6M

12

22U_0603_6.3V6M

12

1U_0201_4V6M

12

22U_0603_6.3V6M

12

PC9042

PC9041

22U_0603_6.3V6M

12

PC9062

PC9063

22U_0603_6.3V6M

12

22U_0603_6.3V6M

@

12

@

PC9091

PC9090

22U_0603_6.3V6M

12

1U_0201_4V6M

0.47U_0201_6.3V6K

PC9125

PC9124

12

PC9009

22U_0603_6.3V6M

12

22U_0603_6.3V6M

12

PC9034

U42@

22U_0603_6.3V6M

12

PC9066

PC9080

22U_0603_6.3V6M

12

U42@

1

+

2

1U_0201_4V6M

PC9117

12

1U_0201_4V6M

PC9137

12

+VCC_GT

@

PC9018

PC9019

PC9017

22U_0603_6.3V6M

12

PC9044

PC9043

22U_0603_6.3V6M

12

PC9069

PC9070

22U_0603_6.3V6M

12

22U_0603_6.3V6M

12

PC9092

PC9093

PC9020

22U_0603_6.3V6M

12

PC9045

PC9046

22U_0603_6.3V6M

12

PC9071

PC9072

22U_0603_6.3V6M

12

PC9095

PC9094

22U_0603_6.3V6M

12

22U_0603_6.3V6M

12

22U_0603_6.3V6M

12

22U_0603_6.3V6M

12

PC9021

PC9047

22U_0603_6.3V6M

12

1U_0201_4V6M

PC9073

12

22U_0603_6.3V6M

12

PC9163

PC9022

@

PC9048

1U_0201_4V6M

PC9162

@

PC9049

PC9050

22U_0603_6.3V6M

12

1U_0201_4V6M

PC9075

PC9074

12

SA

22U_0603_6.3V6M

@

12

PC9106

22U_0603_6.3V6M

@

PC9107

@

12

PC9109

PC9108

pop: 22uF_0603*10 1uF_0201*7 unpop: 22uF_0603*2

1U_0201_4V6M

0.47U_0201_6.3V6K

PC9126

12

0.47U_0201_6.3V6K

PC9128

PC9127

PC9129

12

220uF*1 22uF*37 1uF*9

+VCC_SA

22U_0603_6.3V6M

12

PC9165

PC9164

PC9052

PC9051

22U_0603_6.3V6M

12

1U_0201_4V6M

PC9076

12

1U_0201_4V6M

PC9078

PC9077

PC9079

12

0.47uF*4

1U_0201_4V6M

PC9150

PC9151

1U_0201_4V6M

12

1U_0201_4V6M

PC9141

PC9140

PC9142

12

1U_0201_4V6M

PC9144

PC9143

12

1U_0201_4V6M

PC9145

12

1U_0201_4V6M

PC9147

PC9146

PC9148

12

PC9149

12

PC9152

12

1U_0201_4V6M

PC9153

unpop: 22uF *7 1uF*1

1U_0201_4V6M

12

2018/08/15

4 4

1U_0201_4V6M

PC9160

PC9161

12

1U_0201_4V6M

PC9157

PC9159

PC9158

12

VCORE Output Capacitor: U42 22uF_0603*41 1uF_0201*35 220uF *2 UNPOP 22_0603*1

A

B

Securit y Class ificati on

Iss ued Date

TH IS SHEET OF ENGINEERING DRAWING IS TH E PROPRIETARYPROPERTY OF COMPAL ELECTRONICS, INC . AND CONTAINS CONFIDENTIAL

TH IS SHEET OF ENGINEERING DRAWING IS TH E PROPRIETARYPROPERTY OF COMPAL ELECTRONICS, INC . AND CONTAINS CONFIDENTIAL AND TR A D E SECRETINFO RMATION. TH I S SHEET MAY NOT BE TRANSFERED FROM TH E CUSTODY OF TH E COMPETENTD IVISION OF R&D

AND TR A D E SECRETINFO RMATION. TH I S SHEET MAY NOT BE TRANSFERED FROM TH E CUSTODY OF TH E COMPETENTD IVISION OF R&D

AND TR A D E SECRETINFO RMATION. TH I S SHEET MAY NOT BE TRANSFERED FROM TH E CUSTODY OF TH E COMPETENTD IVISION OF R&D DEPARTMENTEXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, I NC . NE ITHER TH I S SHEET NOR TH E INF O RM AT IO N IT CONTAINS

DEPARTMENTEXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, I NC . NE ITHER TH I S SHEET NOR TH E INF O RM AT IO N IT CONTAINS

DEPARTMENTEXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, I NC . NE ITHER TH I S SHEET NOR TH E INF O RM AT IO N IT CONTAINS MAYBE US ED BY OR DISCLOSEDT O ANY THIRD PA R T Y WITHOUTPRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC .

MAYBE US ED BY OR DISCLOSEDT O ANY THIRD PA R T Y WITHOUTPRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC .

C

2018/10/10 2018/11/04

Compal Secret D ata

Deciphered Date

D

Compal Electronics, Inc.

Ti t l e

Power Train

Size

Document Number Rev

C

Date: Sh ee t

LA-H101PLA-H101PLA-H101P

E

49 54Thursday, September 20, 2018

0.A0.A0.A

of

5

R1, R2, R3, R4, R5, C are based on VGA type to set.

D D

Vboot=Vvref*Rref2/(Rref1+Rref2+Rboot)

Rt=Rrefadj // (Rboot+Rref2)

Vmin= Vvref*[Rref2/(Rref2+Rboot)]*[Rt/(Rref1+Rt)]

Vmax=Vvref*Rref2/[(Rref1//Rrefadj)+Rboot+Rref2]

Vout=Vmin+ N*Vstep

Vstep=(Vmax-Vmin)/Nmax

PR803

[24] PSI

N17_VGA @

PR809

N16_VGA @

20K_040 2_1%

N16_VGA @

2K_0402 _1%

PR814

N16_VGA @

18K_040 2_1%

C C

B B

12

N17_VGA @

R4

PR814

16.5K_0402_1%

12

N17_VG%A@

PR816

R5

309_0402_1

PR816

N16_VGA @

0_0402_ 5%

12

PC818

Close Vref pin

0.1U_040 2_25V6

N17_VGA @

VGA_B+

PC818

N16_VGA @

1U_0402 _6.3V6K

Remark:

1. Switching frequency setting:(Ton pin) Fsw=(Vin-0.5)/(2*Vin*Rton*3.2p)

=352Khz

PR809

20.5K_04 02_1%

PR812

R3

PR812

4.32K_04 02_1%

1 2

N17_VGA @

1

PC812

2

@

0.01U_0402_16V7K

RGND_NV VDDS

PR821

1 2

2.2_0805 _5%

VGA@

PC820

1U_0603 _25V6K

[21] GND_SENSE_G PU

+VGA_CORE

[21] VDD_SENSE_G PU

VGA@

1 2

0_0402_ 5%

PR813

N16_VGA @

20K_040 2_1%

12

R2

[24] GPU_VID0

R1

1 2

PR813

N17_VGA @

6.19K_04 02_1%

12

PC813

N17_VGA @

C

PC813

N16_VGA @

2700P_0 402_50V7K

4700P_0402_50V7K

PR820

N17_VGA @

1 2

432K_04 02_1%

12

N16_VGA @

499K_04 02_1%

VGA@

For debug only, HW side need other resister

Rton

PR820

PR823

@

0_0402_ 1%

1 2

PR824

10_0402 _5%

VGA@

1 2

PR827

10_0402 _5%

1 2

@

0_0402_ 1%

PR828

PSI pull up on HW side

+1.8VGS_+3VGS_AON

10K_040 2_1%

1 2

REFADJ_NVVDDS

REFIN_NVV DDS

VREF_NV VDDS

TON_NVV DDS

RGND_NVVDDS

1

PC832

E

2

@VGA@

1000P_0402_50V7K

0_0402_ 5%

N16_VGA @

1 2

NVVDDS_VSENS

1 2

0_0402_ 5%

@VGA@

PR801

PR804

@

10K_040 2_1%

PR810

@

0_0402_ 5%

6

REFADJ

7

REFIN

8

VREF

9

TON

10

RGND

GND

21

@VGA@

PR829

PR830

N17_VGA @

PC833

12

NVVDDS_VID

5

VID

RT8816B GQW_W QFN20_3X3

VSNS

11

1

2

4

+1.8VGS_+3VGS_AON

NVVDDS_PSI_R

NVVDDS_EN

3

EN

PSI

PU801

N17_VGA @

OCSET/SS

PGOOD

13

VGA@

N17_VGA @

0.01U_04 02_16V7K

1 2

OCSET_NVVDDS

1 2

N17_VGA @

90.9K_04 02_1%

2

UGATE1

UGATE2

14

DH2_VGA

10K_040 2_5%

1 2

4

12

0.01U_0402_16V7K

OpenVReg Configurations:(PSI pin)

Operation phase Number PSI Voltage setting

1 phase with DEM 0V to 0.4V

PR805

0_0402_ 5%

1 2

VGA@

BST1_VG A-R

VGA@

12

VGA@

BST2_VG A-R

0.7V to 0.88V

1.08V to 1.35V

1.6V to 5.5V

12

VGA@

PC822

0.1U_040 2_25V6

High: >1.2V

Low: <0.55V

N16_VGA @PU801

RT8812A GQW_W QFN20_3X3

PC816

0.1U_040 2_25V6

1 2

12

1 phase with CCM

2 phase with DEM

2 phase with CCM

PWM VID and Output voltage control

1.Boot mode

2.Standby mode (don't support)

3.Normal mode

12

@VGA@

PR833 10K_040 2_1%

12

PC801

@

.1U_0402 _16V7K

DH1_VGA

BST1_VG A

1 2

PR815

2.2_0603 _5%

1

PHASE1

PHASE2

15

PR826

PC851

VGA@

BOOT1

LGATE1

PVCC

LGATE2

BOOT2

BST2_VG A

DGPU_PWROK [21,25,26]

LX1_VGA

20

DL1_VGA

19

PVCC_NV VDDS

18

DL2_VGA

17

LX2_VGA

16

PR825

1 2

2.2_0603 _5%

VGA@

Current Limit threshold setting Rocset= (Ivalley * Rds(on) * 12) / Icoset

+3VS

Css

PR831

PR819

1_0402_ 1%

VGA@

PC819

2.2U_060 3_16V6K

3

Module model information: RT8816A-2P_NVVDDS_V2A.mdd for IC portion RT8816A-2P_NVVDDS_V2B.mdd for SW portion

VGA_CORE_EN [26]

VGA@

+5VALW

VGA_B+

LX2_VGA

12

PC810

PC811

10U_0603_25V6M

1

VGA_RF@

PR817

4.7_1206 _5%

BSNU _VGA2

2

12

PC817

VGA_RF@

680P_04 02_50V7K

10U_0603_25V6M

VGA@

DH2_VGA

PQ802

1

2

AON6962 _DFN5X6VDG-A8-@7

D1

G1

7

D2/S1

S24S2

S2

G2

5

3

6

DL2_VGA

4.7U_0402_6.3V 12pcs

1U_0402_16V 5pcs

+VGA_CORE

GB4-128 package

12

VGA@

12

PC847

PC846

1U_0402_16V6K

VGA@

12

PC852

PC853

12

PC848

PC849

1U_0402_16V6K

VGA@

1U_0402_16V6K

VGA@

Under GPU Core

12

PC855

PC854

VGA_B+

12

PC850

1U_0402_16V6K

PC856

PL803

1

2

VGA@

12

2

VGA_B+

DH1_VGA

PQ801

1

2

AON6962 _DFN5XV6GDA-8@-7

D1

G1

D2/S1

S24S2

S2

3

VGA@

G2

5

6

DL1_VGA

12

PR807

N16_VGA@

10.7K_0402_1%

Rocset

0.24UH_2 2A_20%_ 7X7X3 _M

4

3

+VGA_CORE

12

VGA@

12

PC834

22U_0603_6.3V6M

VGA@

12

PC858

PC857

PC859

12

PC802

PC803

10U_0603_25V6M

LX1_VGA

7

1

VGA_RF@

PR802

4.7_1206 _5%

BSNU _VGA1

2

12

PC809

VGA_RF@

680P_04 02_50V7K

+VGA_CORE

4.7U_0402_6.3V 4pcs

10U_0603_6.3V 13pcs

Near GPU Core

12

PC828

12

VGA@

PC860

4.7U_0402_6.3V6M

VGA@

PC836

12

22U_0603_6.3V6M

VGA@

PC861

PC829

4.7U_0402_6.3V6M

VGA@

12

PC837

12

PC823

4.7U_0402_6.3V6M

VGA@

PC835

22U_0603_6.3V6M

12

10U_0603_25V6M

VGA@

12

22U_0603_6.3V6M

VGA@

PC862

VGA_B+

12

PC804

VGA_EMI@

0.24UH_2 2A_20%_ 7X7X3 _M

PL802

1

2

VGA@

12

PC824

PC830

4.7U_0402_6.3V6M

VGA@

12

PC838

10U_0402_6.3V6M

VGA@

12

1

PL801 VGA_ EMI@

S SUPPRE _ 5A Z80 20M 0805

12

@VGA_EM I@

2200P_0402_50V 7K

4

3

12

PC805

0.1U_0402_25V6

1

+

PC806

2

VGA@

N16S-GTR

+VGA_CORE EDP-Continuous 26.5A EDP-Peak 53A OCP min 63.6A

N17S-G1

+VGA_CORE EDP-Continuous 29.7A EDP-Peak 59.2A OCP min 71.1A

12

10U_0402_6.3V6M

12

VGA@

PC839

10U_0402_6.3V6M

PC863

VGA@

PC831

PC825

10U_0402_6.3V6M

VGA@

12

PC841

PC840

10U_0402_6.3V6M

VGA@

B+

+VGA_CORE

1

+

PC807

PC808

2

330U_B2_2.5VM_R9M

VGA@

12

PC827

PC826

10U_0402_6.3V6M

VGA@

12

PC842

PC843

10U_0402_6.3V6M

VGA@

330U_B2_2.5VM_R9M

12

PC844

PC845

10U_0402_6.3V6M

VGA@

4.7U_0402_6.3V6M

VGA@

4.7U_0402_6.3V6M

VGA@

TTTiiitttlll eee

SSSiiizzzeee DDDooocccuuu mmmeeennnttt NNNuuummmbbbeeerrr RRR eee vvv

CCCuuussstttooommm

MMMooonnndddaaayyy,,, OOOccctttooobbbeeerrr 222222,,, 222000111888

DDD aaa ttt eee ::: SSShhheeeeeettt ooo fff

4.7U_0402_6.3V6M

VGA@

CCComomompalpalpal EEEllleeeccctttrrronononiiicccsss,,, IIInnnccc...

VVVGGGAAA_C_C_COOORRREEE

LA-H101PLA-H101PLA-H101P

1

555000 555333

0.A

2

VGA@

4.7U_0402_6.3V6M

VGA@

A A

SSSeeecccuuuritritrityyy CCClalalassssssififificicicaaatttioioionnn

IIIssussussueeeddd DDDaaattteee

TTTHHHIIISSS SSSHHHEEEEEETTT OOOFFF EEENNNGGGIIINNNEEEEEERRRIIINNNGGG DDDRRRAAAWWW IIINNNGGG IIISSS TTTHHHEEE PPPRRROOOPPPRRRIIIEEETTTAAARRRYYY PPPRRROOOPPPEEERRRTTTYYY OOOFFF CCCOOOMMMPPPAAALLL EEELLLEEECCCTTTRRROOONNNIIICCCSSS,,, IIINNNCCC... AAANNNDDD CCCOOONNNTTTAAAIIINNNSSS CCCOOONNNFFFIIIDDDEEENNNTTTIIIAAALLL AAANNNDDD TTTRRRAAADDDEEE SSSEEECCCRRREEETTT IIINNNFFFOOORRRMMMAAATTTIIIOOONNN... TTTHHHIIISSS SSSHHHEEEEEETTT MMMAAAYYY NNNOOOTTT BBBEEE TTTRRRAAANNNSSSFFFEEERRREEEDDD FFF RRROOOMMM TTTHHHEEE CCCUUUSSSTTTOOODDDYYY OOOFFF TTTHHHEEE CCCOOOMMMPPPEEETTTEEENNNTTT DDDIIIVVVIIISSSIIIOOONNN OOOFFF RRR&&&DDD DDDEEEPPPAAARRRTTTMMMEEENNNTTT EEEXXXCCCEEEPPPTTT AAASSS AAAUUUTTTHHHOOORRRIIIZZZEEEDDD BBBYYY CCCOOOMMMPPPAAALLL EEELLLEEECCCTTTRRROOONNNIIICCCSSS,,, IIINNNCCC... NNNEEEIIITTTHHHEEERRR TTTHHHIIISSS SSSHHHEEEEEETTT NNNOOORRR TTTHHHEEE IIINNNFFFOOORRRMMMAAATTTIIIOOONNN IIITTT CCCOOONNNTTTAAAIIINNNSSS MMMAAAYYY BBBEEE UUUSSSEEEDDD BBBYYY OOORRR DDDIIISSSCCCLLLOOOSSSEEEDDD TTTOOO AAANNNYYY TTTHHHIIIRRRDDD PPPAAARRRTTTYYY WWWIIITTTHHHOOOUUUTTT PPPRRRIIIOOORRR WWWRRRIIITTTTTTEEENNN CCCOOONNNSSSEEENNNTTT OOO FFF CCCOOOMMMPPPAAALLL EEELLLEEECCCTTTRRROOONNNIIICCCSSS,,, IIINNNCCC...

5

4

222000111222///000444///111999

3

VGA@

4.7U_0402_6.3V6M

VGA@

CCCooompmpmpaaalll SSSeeecrecrecret t t DaDaDatatata

DDDeeecicicippphhheeerrreeeddd DDDaaattteee

4.7U_0402_6.3V6M

VGA@

4.7U_0402_6.3V6M

VGA@

4.7U_0402_6.3V6M

VGA@

4.7U_0402_6.3V6M

VGA@

222000111555///000444///111999

5

D D

4

3

2

1

Module model information

SY8286_ V1_s ingl e.md d SY8286_ V1_d ual. mdd

B+_1.35V

PJ1201

@

+3VS

PR1206

12

112

JUMP_43X79

PR1201

@VGA@

100K_0402_5%

12

2

PC1201

VGA_EMI@

12

PC1212

0.22U_0402_16V7K

12

PC1205

0.1U_0402_25V6 10U_0603_25V6M

VGA@

2200P_0402_50V7K

@VGA_EMI@PC1203

VGA@

LX_1.35V

EN_1.35V

VGA@

PU1201

5

LX

SY8386RHC_QFN16_2P5X2P5

6

GND

7

PG

8

TEST

4

EN

9

1

2

BS

IN23IN3

IN1

17

EP

16

LX2

15

LX1

14

GND1

VCC

BYP

FB11ILMT

12

10

13

LDO_3V_1.35V

+3VALW

12

LDO_3V_1.35V

12

@VGA@

PR1208

0_0402_5%

ILMT_1.35V

VGA_B+

Confirm HW side

C C

[26] +1.35VGS_PGOOD

PD1201

VGA@

1 2

RB751V-40_SOD323-2

VGA@PR1 2054.7K_0402_5%

[25] 1.35V_PWR_EN

1 2

VGA@

1M_0402_1%

EN :H>0.8V ; L<0.4V

EN pin don't floating If have pull down resistor at HW side, please delete PR601.

EN pin don't floating If have pull down resistor at HW side, pls delete PR702

PC1213

VGA@

BST_1.35V

2.2U_0201_6.3V6M

LX_1.35V

12

VGA@

PC1211

4.7U_0402_6.3V6M

keep short pad, snubber is for EMI only.

@VGA@

PR1203

0_0402_5%

1 2

PC1204

VGA@

0.1U_0402_25V6

51VBST_1.3 _R

2

FB_1.35V

Vout=0.6V* (1+R1/R2)

Vout=1.362V

VGA_RF@

PR1202

4.7_1206_5%

SNUB_1.35V

1 2

Use 7x7x3 size when the layout space is enough.

VGA@

PL1201

1

2

1UH_6.6A_20%_5X5X3_M

VGA@

PR1204

12.7K_0402_1%

FB=0.6V

= 0.6*(1+(12.7/10 ))

4

3

VGA_RF@

R1

R2

PC1202

680P_0402_50V7K

1 2

12

PR1207 10K_0402_1%

12

VGA@

PC1206

330P_0402_50V7K

VGA@

PR1209 1K_0402_1%

+1.35VGSP

12

PC1210

PC1209

PC1208

PC1207

VGA@

22U_0603_6.3V6M

VGA@

22U_0603_6.3V6M

PJ1202

@

JUMP_43X118

2

+1.35VGSP

112

+1.35VS_VRAM

B B

A A

SSSeeecccuuurrriiitttyyy CCClllaaassssssiiifffiiicccaaatttiiiooonnn

IIIssssssuuueeeddd DDDaaattteee

TTTHHHIIISSS SSSHHHEEEEEETTT OOOFFF EEENNNGGGIIINNNEEEEEERRRIIINNNGGG DDDRRRAAAWWWIIINNNGGG IIISSS TTTHHHEEE PPPRRROOOPPPRRRIIIEEETTTAAARRRYYY PPPRRROOOPPPEEERRRTTTYYY OOOFFF CCCOOOMMMPPPAAALLL EEELLLEEECCCTTTRRROOONNNIIICCCSSS,,, IIINNNCCC... AAANNNDDD CCCOOONNNTTTAAAIIINNNSSS CCCOOONNNFFFIIIDDDEEENNNTTTIIIAAALLL AAANNNDDD TTTRRRAAADDDEEE SSSEEECCCRRREEETTT IIINNNFFFOOORRRMMMAAATTTIIIOOONNN... TTTHHHIIISSS SSSHHHEEEEEETTT MMMAAAYYY NNNOOOTTT BBBEEE TTTRRRAAANNNSSSFFFEEERRREEEDDD FFFRRROOOMMM TTTHHHEEE CCCUUUSSSTTTOOODDDYYY OOOFFF TTTHHHEEE CCCOOOMMMPPPEEETTTEEENNNTTT DDDIIIVVVIIISSSIIIOOONNN OOOFFF RRR&&&DDD DDDEEEPPPAAARRRTTTMMMEEENNNTTT EEEXXXCCCEEEPPPTTT AAASSS AAAUUUTTTHHHOOORRRIIIZZZEEEDDD BBBYYY CCCOOOMMMPPPAAALLL EEELLLEEECCCTTTRRROOONNNIIICCCSSS,,, IIINNNCCC... NNNEEEIIITTTHHHEEERRR TTTHHHIIISSS SSSHHHEEEEEETTT NNNOOORRR TTTHHHEEE IIINNNFFFOOORRRMMMAAATTTIIIOOONNN IIITTT CCCOOONNNTTTAAAIIINNNSSS

5

4

3

MMMAAAYYY BBBEEE UUUSSSEEEDDD BBBYYY OOORRR DDDIIISSSCCCLLLOOOSSSEEEDDD TTTOOO AAANNNYYY TTTHHHIIIRRRDDD PPPAAARRRTTTYYY WWWIIITTTHHHOOOUUUTTT PPPRRRIIIOOORRR WWWRRRIIITTTTTTEEENNN CCCOOONNNSSSEEENNNTTT OOOFFF CCCOOOMMMPPPAAALLL EEELLLEEECCCTTTRRROOONNNIIICCCSSS,,, IIINNNCCC...

222000111666///666///222 222000111777/// 666///222

CCCooo mmmpppaaalll SSS eeecccrrreeettt DDDaaatttaaa

DDDeeeccciiippphhheeerrreeeddd DDDaaattteee

2

TTTiiitttllleee

SSSiiizzzeee

CCCuuusss tttooommm

DDDaaattteee :::

CCCooommmpppaaalll EEEllleeeccctrtrtrooonnniiicccsss,,, IIInnnccc...

VVVRRRAAAMMM-S-S-SYYY888222888 666 RRRAAACCC

DDDoooccc uuummmeeennnttt NNNuuummm bbbeeerrr RRReee vvv

MMMooonnndddaaayyy,,, OOOccctttooobbbeeerrr 222222,,, 222000111888

1

LA-H101PLA-H101PLA-H101P

SSShhheeeeeettt ooofff

555111 555333

0.A

5

4

3

2

1

Version change list (P.I.R. List) Page 1 of 1 for

PWR

Item

Reason for change

PG#

Modify List

1

D D

2

3

4

5

6

Date

Phase

C C

7

8

9

10

11

12

B B

13

14

15

16

17

18

A A

Security Classification

Issued Da te

THIS SHEET OF ENGINEERING DRAWING IS THEPROPRIETARYPROPERTY OF COMPAL ELECTRONICS, I N C . A N D CONTAINS C ONFIDEN TIAL

THIS SHEET OF ENGINEERING DRAWING IS THEPROPRIETARYPROPERTY OF COMPAL ELECTRONICS, I N C . A N D CONTAINS C ONFIDEN TIAL AN D TRADE SECRET INFORMATION. THISSHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AN D TRADE SECRET INFORMATION. THISSHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AN D TRADE SECRET INFORMATION. THISSHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, I N C . NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, I N C . NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, I N C . NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO AN Y THIRD P A R T Y WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C .

MAY BE USED BY OR DISCLOSED TO AN Y THIRD P A R T Y WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C .

5

4

MAY BE USED BY OR DISCLOSED TO AN Y THIRD P A R T Y WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C .

2018/04/09 2019/04/09

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Docu ment Number Rev

Size Docum ent Num ber Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

PIR (PWR)

LA-H101PLA-H101PLA-H101P

52 54Thursday, September 20, 2018

1

0.A

o f

5

Version change list Page 1 of 2 for (P.I.R. List)

IIIttteee mmm

4

3

2

1

HW

PhaseDateModify Lis tPG#

1

2

3

4

D D

5

6

7

8

9

10

11

12

13

14

15

16

17

18

C C

19

20

21

22

23

24

25

26

27

28

29

30

31

B B

A A

Security Cl assificat ion

Security Classification

Issued Date

Issued Dat e

THISSHEET OF ENGINEERINGDRAWING IS THE PROPRIETARYPROPERTYOF COMPALELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THISSHEET OF ENGINEERINGDRAWING IS THE PROPRIETARYPROPERTYOF COMPALELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRETINFORMATION. THISSHEET MAYNOT BE TRANSFERED FROM THECUSTODY OF THECOMPET ENT DIVISION OF R&D

AND TRADE SECRETINFORMATION. THISSHEET MAYNOT BE TRANSFERED FROM THECUSTODY OF THECOMPET ENT DIVISION OF R&D

AND TRADE SECRETINFORMATION. THISSHEET MAYNOT BE TRANSFERED FROM THECUSTODY OF THECOMPET ENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAYBE USED BY OR DISCLOSED TO ANY THIRD P A R T Y WITHOUT PRIORWRITTEN CONSENT OF COMPALELECTRONICS, INC.

MAYBE USED BY OR DISCLOSED TO ANY THIRD P A R T Y WITHOUT PRIORWRITTEN CONSENT OF COMPALELECTRONICS, INC.

5

4

3

MAYBE USED BY OR DISCLOSED TO ANY THIRD P A R T Y WITHOUT PRIORWRITTEN CONSENT OF COMPALELECTRONICS, INC.

2018/09/21 2019/09/21

Compal Secret Data

Deciph ered Date

Deciph ered Dat e

2

Compal Electronics, Inc.

Ti t l e

Custom

Date: Sheet of

Size

Document Number

PIR (HW)

LA-H101PLA-H101PLA-H101P

1

53 51Thursday, September 20, 2018

Rev

0.1

0.A

COMPAL LA-H101P Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual