Compal LA-G716P Schematics

A

smd.db-x7.ru

B

C

D

E

COMPAL CONFIDENTIAL

MODEL NAME :

FDI40 N3-14", FDI4A V3-14", FDI43 N5-14", FDI50 N3-15", FDI5A V3-15", FDI53 N5-15", FDI70 N3-17"

1 1

PCB NO :

DA60027S000 (SBDR) DA60027S100 (NBDR)

BOM P/N :

431AJ331L51 431AJ331L52 431AJ331L53

2 2

431AJ331L54 431AJ331L55 431AJ331L56

431AJ331L01 431AJ331L02 431AJ331L03

NBDR-UMASBDR-UMA

X4E X4EAJ331L51(N3)

X4EAJ331L52(V3) X4EAJ331L01(N5)

CML-U+MEC1418

2019-06-19

REV : 1.0 (A00)

@ : Un-pop Component

PCB R1

ZZZ

DAZ2QT00100

PCB_SBD R_R1@

PCB FDI50 LA -G717P LS-F1 12P/F114P/G 711P

PCB R3

ZZZ3

DAZ2QT00101

PCB_SBD R_R3_GCE@

PCB FDI50 LA -G717P LS-F1 12P GOLD A3 1 !

ZZZ5

DAZ2QT00102

PCB_SBD R_R3_TRI@

PCB FDI50 LA -G717P LS-F1 12P TRIPOD A31 !

ZZZ7

DAZ2QT00103

PCB_SBD R_R3_HAN@

PCB FDI50 LA -G717P LS-F1 12P HANNS A3 1 !

ZZZ9

DAZ2QT00104

PCB_SBD R_R3_TMT@

PCB FDI50 LA -G717P LS-F1 12P T-MAC A31 !

ZZZ2

DAZ2SO00100

PCB_NBR D_R1@

PCB FDI53 LA -G717P LS-G7 18P

ZZZ4

DAZ2SO00101

PCB_NBR D_R3_GCE@

PCB FDI53 LA -G717P LS-G7 18P GOLD A 31 !

ZZZ6

DAZ2SO00102

PCB_NBR D_R3_TRI@

PCB FDI53 LA -G717P LS-G7 18P TRIPOD A3 1 !

ZZZ8

DAZ2SO00103

PCB_NBR D_R3_HAN@

PCB FDI53 LA -G717P LS-G7 18P HANNS A3 1 !

ZZZ10

DAZ2SO00104

PCB_NBR D_R3_TMT@

PCB FDI53 LA -G717P LS-G7 18P T-MAC A31 !

DIS@ : GPU Support N3@/V3@ : Inspiron/Vostro

CPU R1 CPU R3

UC12

S IC FJ80701 04307606 SRGL0 V0 2. 1G BGA

i3-10110U

SA0000CU31L

CML_2.1G _R1@

UC1

S IC FJ80701 04307606 SRGL0 V0 2. 1G A31!

i3-10110U

SA0000CU32L

CML_2.1G _R3@

CML@/CNL@ : CML/CNL BASE@/PREM@ : (Pentium)(Celeron)i3 i5 i7

EC@ : EC Support JP@/PJP@ : JUMP 100@/1000@: Lan

UC13

3 3

S IC FJ80701 04307504 SRGKY V0 1.6G BGA

i5-10210U

SA0000CST2L

CML_1.6G _R1@

UC1

S IC FJ80701 04307504 SRGKY V0 1.6G A31!

i5-10210U

SA0000CST3L

CML_1.6G _R3@

EMI@/ESD@/RF@ : EMI, ESD and RF Component @EMI@/@ESD@/@RF@ : EMI, ESD and RF Un-POP Component CMC@ : XDP Component CONN@ : Connector Component KBBL@ : KB Backlight

UC14

S IC FJ80701 04303905 SRGKW V 0 1.8G FCBGA

i7-10510U

SA0000CU22L

CML_1.8G _R1@

UC1

S IC FJ80701 04303905 SRGKW V 0 1.8G A31!

i7-10510U

SA0000CU21L

CML_1.8G _R3@

TPM@/FTPM@ : HW TPM/SW TPM 750_CTPM@:750 and china TPM ST_CTPM@:ST and china TPM CTPM@:China TPM FFS@ : Free Fall Sensor TYPEC@ : TypeC TYPEC@EMI@/TYPEC@ESD@: EMI, ESD ,TypeC Component

PCB@/PCB_R1@/PCB_R3_G@/PCB_R3_T@/PCB_R3_H@/PCB_R3_TM@: PCB MB

Layout Dell logo

PCB_NBDR_R1@: PCB MB for NBDR

4 4

A

B

TS_NON@/TS_USB@/TS_I2C@: Touch Screen Interface Select SBDR@/NBDR@: SBDR/ NBDR Select

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2019/06/ 19 2020/06/ 30

C

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Re v

Date : Sheet o f

Compal Electronics, Inc.

Cover Page

LA-G717P

1 1 00Wednesd ay, June 19, 20 19

E

1.0

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smd.db-x7.ru

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C

D

E

Block Diagram

DDR4

RTC

PS/2

4GB/8GB

SODIMM A

P23

DDR4 4GB/8GB

SODIMM B

P24

P71

P73

P52

P38

P65

P8

P62

P58

D

SD Card slot

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY O F COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY O F COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Secret Data

2019/06/19 2020/06/30

Deciphered Date

Compal Electronics, Inc.

Title

Block Diagram

Size Document Number Rev

LA-G717P

Date: Sheet of

E

2 100Wednesday, June 19, 2019

1 1

DDR4 2400MHz Channel A

DDR4 2400MHz Channel B

Intel CPU

USB2.0 x 1

USB3.0 x 1 (gen1)

USB2.0 x 1

USB3.0 x 1 (gen1)

USB2.0 x 1

Port 1 (USB3.0 Type-A)

Port 2 (USB3.0 Type-A)

Port 3 (USB2.0 Type-A)

VGA

Connector

# VGA converter

RTD2166

DP x 2

eDP connector

HDMI connector , 1.4a

# DP re-driver PS8330B

Comet Lake/ Whiskey Lake-U/

P38

P40

eDP 1.2

DDI x 4

DDI x 2

Cannon Lake-U

15W

BGA 1528 balls

Type-C MUX TUSB542

Reserve d

*Pentium/Celeron Only

Touch screen

LAN 10/100 # LAN 10/1 00/1000

M.2 SSD (NVMe)

ODD

2.5" HDD/SSD

# FFS

eMMC 256 GB *UMA only

Reserve d

HDA CODEC Realtek ALC3204-CG

P42

P38

P51P51P51

P67

P66

P69

P23

P43

CC

P42

2CH SPEAKER (2CH 2W/4ohm)

RING2/SLEEVE

HP_R/L

USB3.0 x 1

Universal Ja ck

USB Type-C

Connector

Reserve d

5V@3A TPS25810

Reserve d

Transformer

P24

2 2

RJ45

Connector

3 3

USB3.0 x 1 Gen1

USB2.0 x 1 (Port4)

USB2.0 x 1 (Port8)

PCIe x 1

PCIe x 4

SATA x 1 Gen1

SATA x 1

SMBu s

eMMC

HDA

# ----> Loki-L only

4 4

Battery

RTC

46 x 24 mm

PCH-LP

P6~1 7

eSPI

SMSC KBC 1418 MEC1418-NU

USB2.0 x 1 SD 3.0

USB2.0 x 1

PCIe x 1 / CNVi

USB2.0 x 1

SPI

I2C

Card reader RTS5144

BT with WLAN

Camera

Finger print

dTPM NPCT750

SPI ROM 16 MB

Precision Touchpa d Click Pad

Charger

A

Daughter board

Keyboard

B

PWM FAN

C

Thermal sensor NCT771 8W

P65P77P62

1.0

5

smd.db-x7.ru

4

3

2

1

POWER STATES

Signal

State

D D

S0 (Full ON) / M0

S3 (Suspend to RAM) / M3

S4 (Suspend to DISK) / M3

S5 (SOFT OFF) / M3

G3 OFF OFF OFF OFF OFF OFF OFF

DS3

SLP S3#

HIGH

LOW

LOW LOW

SLP

SLP S4#

HIGH HIGH

HIGH HIGH ON

LOW

S5#

HIGH

ALWAY S PLANE

ON

Voltage Rails

+19V_ADPIN +17.4V_BATT++ +19VB +RTC_C ELL RTC power ONONO N

C C

B B

+3VALW_DSW +3VALW power for PCH DSW rails ON*ONON +5VALW System +5V always on power rail ON*ONON +3VALW System +3V always on power rail ON*ONON +1.8V_PRIM System +1.8V always on power rail +1.0V_PRIM System +1.0V always on power rail ON*

+2.5V_MEM

+0.6V_DDR_VT T DDR +0.6VS power rail for DDR terminator OFFOFFON +VCCST OFFONON +VCCSTG +1.05 VCCSTG power rail ON OFF OFF +VCCI O +1.05 VCCIO power rail ON OFF OFF

+VCC_GT Sliced graphics power rail OFFOFFON +VCC_SA System Agent power rail OFFON OFF +3VLP +19VB to +3VLP power rail for suspend power ONONON +3VALW_PCH +3VALW power for PCH suspend rails

+3VS System +3VS power rail Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF

Adapter power supply

Bat t er y po wer s uppl y AC or bat t er y p o wer r ail f or Syste m

DDR4 +1.2V power rail+1.2V_DDR DDR4 +2.5V power rail ON OFFON

+1.05 VCCST power rail

System +5VS power rail+5VS

RUN

SUS

PLAN E

PLANE

ON

ON ON

ON

OFF

OFF OFF

OFF

S0 S3 S4/S5Power Plane Descript i on

N/A

ON

OFF

ON

OFF

ON

CLOCKS

OFF

------------------ ---

N/A N/A N/A

ON*

OFF

OFF+VCC_C ORE Core voltage for CPU OFFON

ON* OFF OFF

USB 2.0 DESTINATION

1

2

3

4*

5

6

7

8*

9

10

DESTINATION

USB2.0 port1

USB2.0 Port2

USB2.0 Port, IO/B

Touch screen

Finger printer

Camera

Card reader , IO/B

Reserved

NA

BT

USB3.0

USB3.0-1

USB3.0-2

USB3.0-3

USB3.0-4

USB3.0-5

USB3.0-6

PCIE

PCIE-1

PCIE-2

PCIE-3

PCIE-4

PCIE-5

PCIE-6

PCIE-7

PCIE-8

PCIE-9

PCIE-10

PCIE-11

PCIE-12

PCIE-13

PCIE-14

PCIE-15

PCIE-16

SATA

SATA-0

SATA-1A

SATA-1B

SATA-2

USB3.0 port1

NA

USB3.0 port2

TypeC

LOM

WLAN

SATA HDD

SATA ODD

NVME SSD

Board ID & Model ID Table

Pull-down#Pull-up

1

100

2

100

3

100

4

100

5

100

6

100

7

100

8

100

9

100

10

100

10.0

17.8

27.0

37.4

49.9

64.9

82.5

107.0

154.0

200.0

Voltage

3.000

2.801

2.598

2.402

2.201

2.001

1.808

1.594

1.299

1.100

Board ID

EVT

DVT1

DVT2

Pilot

Model ID

SBDR-UMA

NBDR-UMA

SBDR-DSC

NBDR-DS C

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2019/06/19 2020/06/30

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Index and Configuration

Size

Document Number Re v

LA-G717P

Date: Sheet of

1

3 100Wednesday, June 19, 2019

1.0

5

smd.db-x7.ru

D D

CPU PWR

GPU PWR

Peripheral Device PWR

ADAPTER

+PWR_S RC

C C

CHARGER ISL88739HRZ-T (PUB01)

BATTERY

(+19VB)

PJPH01

PJP501

PJP301

4

FUSE 1.5A_24V (F1)

RT6228AGQU F (PUH01)

SY8180CRAC (PU501)

SY8286BRAC (PU301)

EN_3V

+3VALWP

PJP302

+3VALW

R7

+DCBAT_LCD

PJPH02PRIM_PWR GD

PJP502 PJP503

BAS40C (D1)

+RTC_VCC

+1.05V_PRIM

+5VALW

+RTC_CELL

0ohm 0603

(RL4)

PCH_PWR _EN

+3VALW_PCH

+2.5VP +2.5V_MEM

PCH_PRIM_ EN

+1.8VALWP

SIO_SLP _S3#

+3VS

+3VALW_EC

+3.3V_W LAN

+3V_EMMC

+3VS_MO N

+LAN_VDD33

+1.05VALWP

EN_5V

+5VALWP

+3VLP

TPS22967DSGR

(UZ4)

PJP250 1 SIO_SLP_ S4# PJP2 502

RT9059GSP (PU2501)

PJP180 1

RT8061AZQW (PU1801)

EM5209VF

(UZ3)

0ohm 0603

(RE5)

0ohm 0603

(RW1)

0ohm 0603

(RM1)

JP12

SY6288C20AAC

(UL2)

+TP_VDD

3

EM5209VF

(UZ1)

TPS22961

(UZ2)

0ohm 0603 (RC128)

0ohm 0603 (RC129)

0ohm 0603 (RC130)

+RTC_CELL_VB AT

PJP180 2

+1.8V_PRIM

0ohm 0402

(R5)

0ohm 0402

(RA6)

G510F51U

(U2)

RS3

SY6288C20AAC

(U1)

0ohm 0603

(RL4)

SIO_SLP _S4#

VCCSTG_IO_ EN

SY6288D20AAC

(UU1)

SY6288D20AAC

(UU2)

EM5209VF

(UZ3)

TPS25810RVCR

(UT1)

0ohm 0402 (RC131)

0ohm 0402 (RC132)

0ohm 0603 (RC30)

LCD_VCC_TEST_ EN OR EDP_VDD_ EN

+VCCST

+VCCSTG

+VCCIO

+1.05V_MPH Y

+1.05V_MPHYPLL

+1.05V_XTAL

USB_EN#

SIO_SLP _S3#

OVP_TR IP_P1

+FP_VCC

+3V_DVD D

+3VS_CAM

+3VS_SSD

+LCDVD D

VDDREG

USB3_VCC

USB2_VCC

+5VS

+CCG_VBUS

+3V_HDA

+3VALW_DSW

+3.3V_SPI

+3VS

0ohm 0603

(RM2)

LN2306LT1G (QA1)

0ohm 0603

(RE7)

0ohm 0603

(R8)

2

G510F51U

(U2)

0ohm 0805

(RA1)

RS32

JP7

FUSE 1.5A_6V

(FI1)

FUSE 0.5A_13.2V (F3)

1

+TPAN_VDD

+5V_PVD D

+5V_HDD

+5V_ODD

+5V_HDMI

+5V_KB_B L

+1.8V_EMMC

+1.8V_AVDD

+1.8VALW_EC

+LCDVDD _LCD

B B

NCP302045MNTXG

(PUI01)

NCP302045MNTXG

(PUI02)

NCP302045MNTXG

(PUG01)

NCP81253M NTBG (PUA01)

A A

PJPM01

DRVON PWM1_2ph_CP U

DRVON PWM_1a_CPU

DRVON PWM_1b_CPU

RT8207PGQW (PUM01)

+VCC_CORE

+VCC_GT

+VCC_S A

+.2.5V_PG

0.6V_DDR_VTT_ ON

5

4

PJPM02

+1.2VP +1.2V_DDR

PJPM03

+0.6VSP

RSHUNT

+0.6V_DDR_ VTT

+VCC_CORE_GT

3

0ohm 0402 (RZ11)

+VCCPLL_OC

Security C lassification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

Compal Secret Data

2019/06/19 2020/06/30

Deciphered Date

Compal Electronics, Inc.

Title

Power Rail

Size

Document Number R ev

LA-G717P

Date: Sheet of

1

4 1 00Wednes day, June 19, 2 019

1.0

5

smd.db-x7.ru

4

3

2

1

Timing Diagram for S5 to S0 mode

10b

IMVP_VR_ON

D D

ADAPTER

a

BATTERY

C C

HW_ACAV_IN

b

SIO_PWRBTN #

6

PRIM_PWRGD

5

PCH_RSM RST#

5a

RUNPWRO K ALL_SYS_PWRG D

10a

RESET_OU T#

B B

11

12

SYS_PWROK

BAT-->1 AC-->2

POWER_SW_ IN#

EC 1416

ISL88739

ACOK

+19VB

HW_ACAV_IN

2b

EN_5V

2a

EN_3V

VCCDSW_E N

b

+19VB

AND

POK

PCH_PRIM_ EN

4

VL +5VALW

+3VLP +3VALW

c

+3VALW

5

+3VALW

3

PRIM_PWRGD

+1.8V_PRIMRT8061

+19VB

+3VALW_PCHTPS22967

SY8180

+19VB

SY8286

+19VB

NCP81218

+1.05V_PRIMRT6228

+VCC_S A +VCC_COR E +VCC_GT

DDR_VTT_ CNTL

+RTC_SOC

c

+3VALW_PCH

+1.05V_PRIM

+1.05V_PRIM +1.05V_MPHYPLL

+3VALW_DSW

+3V_HDA

+3.3V_SPI

+1.8V_PRIM

+1.05V_PRIM

+1.0V_MPHYGT

+1.05V_MPHY

+1.05V_X TAL

VCCST_PWRGD

10b

11

12

13

RESET_OU T#

SYS_PWROK

PCH_P LTRST#

CPU

DDR_VTT_ CTL

PCH

VCCRTC

VCCDSW_3 P3

VCCHDA

VCCSPI

VCCPRIM_3P3

VCCPRIM_1P8

VCCAPLL_1P 05 VCCDUSB _1P05 VCCA_BCLK_ 1P05 VCCA_SRC_ 1P05 VCCPRIM_1P0 5 VCCPRIM_CORE

VCCMPHYGT_1P0 VCCSRAM_1P0 VCCAMPHYPLL_1P0 VCCAPLLEBB

VCCAMPHYPLL_1P0 5

VCCPRIM_MPHY_1P0 5

VCCA_XTAL_1P05

VCCST_PWRGOO D

PCH_PWR OK

SYS_PWROK

PLTRST#

VDDQ VCCPLL_OC

VCC_OPC_1 P8

VCCEOPIO

CFL-U 43e only

RSMRST#

DSW_PWROK

PWRBTN#

CPU_C1 0_GATE#

VCCIO

VCCGT

VCCGTX

VCCST VCCPLL VCCSTG

VCCSA

VCCOPC

SLP_S5 #

SLP_S4 #

SLP_S3 #

VCC

+VCC_COR E

+VCCIO

+VCC_GT

+1.2V_DDR

+VCCST

+VCC_S A

PCH_RSMR ST#_Q

PCH_DPW ROK

SIO_PWRBTN #

SIO_SLP_S 5#

SIO_SLP_S 4#

0.6V_DDR_V TT_ON

SIO_SLP_S 3#

8b

+2.5V_PG

AND

VCCSTG

5b

6

7

8a

+1.05V_PRIM

EM5209

+3VALW

PGOOD

+19VB

RT8207

PGOOD

1.2V_VTT_PWRGD

+5VALW

9a

EM5209

+1.05V_PRIM

9b

EM5209

+1.05V_PRIM

TPS22961 +VCCIO

+3VALW

+VCCST

+2.5V_MEMRT905 9

+1.2V_DDR

+0.6V_DDR_ VTT

8c

+5VS

+3VS

+VCCSTG

VPP

DDR4

VDDQ

VTT

9C

A A

Security C lassification

5

4

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

Security C lassification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

Compal Secret Data

2019/06/19 2020/06/30

Deciphered Date

Compal Electronics, Inc.

Title

Platform Power Sequence

Size

Document Number R ev

LA-G717P

Date: Sheet of

1

5 1 00Wednes day, June 19, 2 019

1.0

5

smd.db-x7.ru

+VCCSTG

H_PROCHOT#

1 2

RC1 1K_040 2_5%

+VCCST

D D

RC2 1K_040 2_5%

RC3 49.9_04 02_1%

COMPENSATION FOR EDP_COMP

+VCCIO

RC4 24.9_0402_1%

CAD note: Trace width=5 mils, Spacing=25mils Max length=600mils

+3VS

RC5 10K_0402_5 %

C C

RC6 10K_0402_5 %

RC203 10K_0402_5 %

1 2

@

1 2

CML@

1 2

@

1 2

H_THERMT RIP#

CATERR#

RC4 100_0402_1%

SD0341000 80

EDP_COMP

TOUCH_PAD_INT #

TOUCH_PANEL_ PD#

TOUCH_SCR EEN_INT#

CNL@

TOUCH_SCR EEN_INT# < 38>

4

UC1A

CPU_DP1_N0<40> CPU_DP1_P0<40> CPU_DP1_N1<40> CPU_DP1_P1<40> CPU_DP1_N2<40> CPU_DP1_P2<40> CPU_DP1_N3<40> CPU_DP1_P3<40>

CPU_DP2_N0<40> CPU_DP2_P0<40> CPU_DP2_N1<40> CPU_DP2_P1<40>

EDP_COMP

CPU_DP1_CTRL_CLK<40>

CPU_DP1_C TRL_DATA<40>

TOUCH_SCREEN_RST<38>

CPU_DP1_C TRL_CLK CPU_DP1_C TRL_DATA

CPU_DP2_C TRL_DATA

AL5

DDI1_TXN_0

AL6

DDI1_TXP_0

AJ5

DDI1_TXN_1

AJ6

DDI1_TXP_1

AF6

DDI1_TXN_2

AF5

DDI1_TXP_2

AE5

DDI1_TXN_3

AE6

DDI1_TXP_3

AC4

DDI2_TXN_0

AC3

DDI2_TXP_0

AC1

DDI2_TXN_1

AC2

DDI2_TXP_1

AE4

DDI2_TXN_2

AE3

DDI2_TXP_2

AE1

DDI2_TXN_3

AE2

DDI2_TXP_3

AM6

DISP_RCOMP

CC8

GPP_E18/DPPB_CTRLCLK/CNV_BT_HOST_WAKE#

CC9

GPP_E19/DPPB_CTRLDATA

CH4

GPP_E20/DPPC_CTRLCLK

CH3

GPP_E21/DPPC_CTRLDATA

CP4

GPP_E22/DPPD_CTRLCLK

CN4

GPP_E23/DPPD_CTRLDATA

CR26

GPP_H16/DDPF_CTRLCLK

CP26

GPP_H17/DDPF_CTRLDATA

WHL-U42 _BGA1528

DDI

DISPLAY SIDEBANDS

3

EDP

GPP_E13/DDPB_HPD0/DISP_MISC0 GPP_E14/DDPC_HPD1/DISP_MISC1 GPP_E15/DPPD_HPD2/DISP_MISC2 GPP_E16/DPPE_HPD3/DISP_MISC3

GPP_E17/EDP_HPD/DISP_MISC4

1 of 20

EDP_TXN_0 EDP_TXP_0 EDP_TXN_1 EDP_TXP_1 EDP_TXN_2 EDP_TXP_2 EDP_TXN_3 EDP_TXP_3

EDP_AUX_N EDP_AUX_P

DISP_UTILS

DDI1_AUX_N DDI1_AUX_P DDI2_AUX_N DDI2_AUX_P DDI3_AUX_N DDI3_AUX_P

EDP_BKLTEN

EDP_VDDEN

EDP_BKLTCTL

2

AG4 AG3 AG2 AG1 AJ4 AJ3 AJ2 AJ1

AH4 AH3

AM7

AC7 AC6 AD4 AD3 AG7 AG6

CN6 CM6 CP7 CP6 CM7

CK11 CG11 CH11

CPU_DP2_H PD

BKLT_IN_EC

EDP_TXN0 <38> EDP_TXP0 <38> EDP_TXN1 <38> EDP_TXP1 <38>

EDP_AUXN <38> EDP_AUXP <3 8>

TP1

CPU_DP2_AUXN <4 0> CPU_DP2_AUXP <40>

CPU_DP1_H PD <40> CPU_DP2_H PD <40>

EDP_HPD <38>

BKLT_IN_EC <58> EDP_VDD_EN <38> EDP_BKLT_CTRL <3 8>

CPU_DP1_C TRL_CLK

CPU_DP1_C TRL_DATA

CPU_DP2_C TRL_DATA

RC7 2.2K_0402 _5%

RC8 2.2K_0402 _5%

RC9 2.2K_0402 _5%

1

+3VS

12

CPU_DP2_H PD

BKLT_IN_EC

UC1D

CB34 CC35

BP27

BW25

AA4 AR1

Y4

BJ1

U1 U2 U3 U4

CE9 CN3

L5 N5

CATERR# PECI PROCHOT# THRMTRIP#

BPM#_0 BPM#_1 BPM#_2 BPM#_3

GPP_E3/CPU_GP0 GPP_E7/CPU_GP1 GPP_B3/CPU_GP2 GPP_B4/CPU_GP3

PROC_POPIRCOMP PCH_OPIRCOMP

RSVD70 RSVD71

WHL-U42 _BGA1528

CPU MISC

4 of 20

JTAG

PROC_TCK

PROC_TDI PROC_TDO PROC_TMS

PROC_TRST#

PCH_TCK

PCH_TDI PCH_TDO PCH_TMS

PCH_TRST#

PCH_JTAGX

PROC_PREQ# PROC_PRDY#

49.9_0402_1%

TP2 TP3 TP4 TP5

TP6

12

TOUCH_PANEL_ PD#

RC16

49.9_0402_1%

CATERR#

H_PROCHOT# _R H_THERMT RIP#

XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3

CAM_EN# TOUCH_SCR EEN_INT# TOUCH_PAD_INT #

CPU_POPIRCOMP PCH_POPIRCOMP

H_PROCHOT#<58,82,84,88>

B B

TP_WAKE_KBC#<58,62>

TOUCH_SCREEN_PD#<38>

1 2

RC160 499 _0402_1%

DZ1 RB751S40T 1G_SOD523-2

1 2

TOUCH_SCR EEN_PD#

PECI_EC<58>

1 2

@

RC14 0_0201_5 %

12

RC15

T6 U6 Y5 T5 AB6

W6 U5 W5 P5 Y6 P6

W2 W1

CPU_XDP_TCK 0 SOC_XDP_TDI SOC_XDP_TDO SOC_XDP_TMS SOC_XDP_TRST #

SOC_XDP_TDI SOC_XDP_TDO SOC_XDP_TMS SOC_XDP_TRST# CPU_XDP_TCK 0

XDP_PREQ# XDP_PRDY#

CPU_XDP_TCK0 <79> SOC_XDP_TDI <79> SOC_XDP_TDO <79> SOC_XDP_TMS <79> SOC_XDP_TRST# <79>

PCH_JTAG_TCK1 <79>

TP7 TP8

RC12 100K_0 402_5%

RC13 100K_0 402_5%

12

L5,N5 are required for CFL U43e only.

COMPENSATION FOR OPIRCOMP

CAD Note: Min trace width=10 mi ls, Max trace length=500 mils

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2019/06/19 2020/06/30

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number R ev

Custom

Date : Sheet of

2

Date : Sheet of

Compal Electronics, Inc.

CPU(1/12))DDI,MSIC,XDP,EDP

LA-G717P

1

6 100Wednesday, June 19, 2 019

1.0

5

smd.db-x7.ru

4

3

2

1

DDR4 Interleaved Memory

D D

C C

B B

DDR_A_D[0..15]<23>

DDR_A_D[16..31]<23>

DDR_A_D[32..47]<23>

DDR_A_D[48..63]<23>

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

UC1B

Interleave / Non-Interleaved

A26

DDR0_DQ_0/DDR0_DQ_0

D26

DDR0_DQ_1/DDR0_DQ_1

D28

DDR0_DQ_2/DDR0_DQ_2

C28

DDR0_DQ_3/DDR0_DQ_3

B26

DDR0_DQ_4/DDR0_DQ_4

C26

DDR0_DQ_5/DDR0_DQ_5

B28

DDR0_DQ_6/DDR0_DQ_6

A28

DDR0_DQ_7/DDR0_DQ_7

B30

DDR0_DQ_8/DDR0_DQ_8

D30

DDR0_DQ_9/DDR0_DQ_9

B33

DDR0_DQ_10/DDR0_DQ_10

D32

DDR0_DQ_11/DDR0_DQ_11

A30

DDR0_DQ_12/DDR0_DQ_12

C30

DDR0_DQ_13/DDR0_DQ_13

B32

DDR0_DQ_14/DDR0_DQ_14

C32

DDR0_DQ_15/DDR0_DQ_15

H37

DDR0_DQ_16/DDR0_DQ_32

H34

DDR0_DQ_17/DDR0_DQ_33

K34

DDR0_DQ_18/DDR0_DQ_34

K35

DDR0_DQ_19/DDR0_DQ_35

H36

DDR0_DQ_20/DDR0_DQ_36

H35

DDR0_DQ_21/DDR0_DQ_37

K36

DDR0_DQ_22/DDR0_DQ_38

K37

DDR0_DQ_23/DDR0_DQ_39

N36

DDR0_DQ_24/DDR0_DQ_40

N34

DDR0_DQ_25/DDR0_DQ_41

R37

DDR0_DQ_26/DDR0_DQ_42

R34

DDR0_DQ_27/DDR0_DQ_43

N37

DDR0_DQ_28/DDR0_DQ_44

N35

DDR0_DQ_29/DDR0_DQ_45

R36

DDR0_DQ_30/DDR0_DQ_46

R35

DDR0_DQ_31/DDR0_DQ_47

AN35

DDR0_DQ_32/DDR1_DQ_0

AN34

DDR0_DQ_33/DDR1_DQ_1

AR35

DDR0_DQ_34/DDR1_DQ_2

AR34

DDR0_DQ_35/DDR1_DQ_3

AN37

DDR0_DQ_36/DDR1_DQ_4

AN36

DDR0_DQ_37/DDR1_DQ_5

AR36

DDR0_DQ_38/DDR1_DQ_6

AR37

DDR0_DQ_39/DDR1_DQ_7

AU35

DDR0_DQ_40/DDR1_DQ_8

AU34

DDR0_DQ_41/DDR1_DQ_9

AW35

DDR0_DQ_42/DDR1_DQ_10

AW34

DDR0_DQ_43/DDR1_DQ_11

AU37

DDR0_DQ_44/DDR1_DQ_12

AU36

DDR0_DQ_45/DDR1_DQ_13

AW36

DDR0_DQ_46/DDR1_DQ_14

AW37

DDR0_DQ_47/DDR1_DQ_15

BA35

DDR0_DQ_48/DDR1_DQ_32

BA34

DDR0_DQ_49/DDR1_DQ_33

BC35

DDR0_DQ_50/DDR1_DQ_34

BC34

DDR0_DQ_51/DDR1_DQ_35

BA37

DDR0_DQ_52/DDR1_DQ_36

BA36

DDR0_DQ_53/DDR1_DQ_37

BC36

DDR0_DQ_54/DDR1_DQ_38

BC37

DDR0_DQ_55/DDR1_DQ_39

BE35

DDR0_DQ_56/DDR1_DQ_40

BE34

DDR0_DQ_57/DDR1_DQ_41

BG35

DDR0_DQ_58/DDR1_DQ_42

BG34

DDR0_DQ_59/DDR1_DQ_43

BE37

DDR0_DQ_60/DDR1_DQ_44

BE36

DDR0_DQ_61/DDR1_DQ_45

BG36

DDR0_DQ_62/DDR1_DQ_46

BG37

DDR0_DQ_63/DDR1_DQ_47

WHL-U42_BGA1528

2 of 20

Buf f er wi t h Open Drai n Out put F or VTT po wer c ontrol

0.1U_0402_16V7K

UC2

DDR_VTT_CNTL

NC1VCC

2

A

3

GND

74AUP1G07GW_TSSOP5

LPDDR3 / DDR4

DDR0_CKN_0/DDR0_CKN_0

DDR0_CKP_0/DDR0_CKP_0

DDR0_CKN_1/DDR0_CKN_1

DDR0_CKP_1/DDR0_CKP_1

DDR0_CKE_0/DDR0_CKE_0 DDR0_CKE_1/DDR0_CKE_1

DDR0_CKE_2/NC DDR0_CKE_3/NC

DDR0_CS#_0/DDR0_CS#_0 DDR0_CS#_1/DDR0_CS#_1

DDR0_ODT_0/DDR0_ODT_0

NC/DDR0_ODT_1

DDR0_CAB_9/DDR0_MA_0 DDR0_CAB_8/DDR0_MA_1 DDR0_CAB_5/DDR0_MA_2

NC/DDR0_MA_3

NC/DDR0_MA_4 DDR0_CAA_0/DDR0_MA_5 DDR0_CAA_2/DDR0_MA_6 DDR0_CAA_4/DDR0_MA_7 DDR0_CAA_3/DDR0_MA_8 DDR0_CAA_1/DDR0_MA_9

DDR0_CAB_7/DDR0_MA_10 DDR0_CAA_7/DDR0_MA_11 DDR0_CAA_6/DDR0_MA_12 DDR0_CAB_0/DDR0_MA_13

DDR0_CAB_2/DDR0_MA_14 DDR0_CAB_1/DDR0_MA_15 DDR0_CAB_3/DDR0_MA_16

DDR0_CAB_4/DDR0_BA_0 DDR0_CAB_6/DDR0_BA_1

DDR0_CAA_5/DDR0_BG_0

DDR0_CAA_8/DDR0_ACT# DDR0_CAA_9/DDR0_BG_1

Interleave / Non-Interleaved

DDR0_DQSN_0/DDR0_DQSN_0 DDR0_DQSP_0/DDR0_DQSP_0 DDR0_DQSN_1/DDR0_DQSN_1 DDR0_DQSP_1/DDR0_DQSP_1 DDR0_DQSN_2/DDR0_DQSN_4 DDR0_DQSP_2/DDR0_DQSP_4 DDR0_DQSN_3/DDR0_DQSN_5 DDR0_DQSP_3/DDR0_DQSP_5 DDR0_DQSN_4/DDR1_DQSN_0 DDR0_DQSP_4/DDR1_DQSP_0 DDR0_DQSN_5/DDR1_DQSN_1 DDR0_DQSP_5/DDR1_DQSP_1 DDR0_DQSN_6/DDR1_DQSN_4 DDR0_DQSP_6/DDR1_DQSP_4 DDR0_DQSN_7/DDR1_DQSN_5 DDR0_DQSP_7/DDR1_DQSP_5

CC1

12

Y

NC/DDR0_ALERT#

NC/DDR0_PAR

DDR_VREF_CA DDR0_VREF_DQ_0 DDR0_VREF_DQ_1

DDR1_VREF_DQ

DDR_VTT_CTL

+1.2V_DDR +3VS

5

4

LPDDR3 / DDR4

12

1

2

V32 V31 T32 T31

U36 U37 U34 U35

AE32 AF32 AE31 AF31

AC37 AC36 AC34 AC35 AA35 AB35 AA37 AA36 AB34 W36 Y31 W34 AA34 AC32

AC31 AB32 Y32

W32 AB31 V34

V35 W35

C27 D27 D31 C31 J35 J34 P34 P35 AP35 AP34 AV34 AV35 BB35 BB34 BF34 BF35

W37 W31

F36 D35 D37 E36 C35

RC19 200K_0402_1%

0.6V_DDR_VTT_ON <86>

@

CC2 100P_0402_50V8J

DDR_A_CLK#0 DDR_A_CLK0 DDR_A_CLK#1 DDR_A_CLK1

DDR_A_CKE0 DDR_A_CKE1 DDR_A_CKE2 DDR_A_CKE3

DDR_A_CS#0 DDR_A_CS#1 DDR_A_ODT0 DDR_A_ODT1

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13

DDR_A_WE# DDR_A_CAS# DDR_A_RAS#

DDR_A_BA0 DDR_A_BA1 DDR_A_BG0

DDR_A_BG1

DDR_A_DQS#0 DDR_A_DQS0 DDR_A_DQS#1 DDR_A_DQS1 DDR_A_DQS#2 DDR_A_DQS2 DDR_A_DQS#3 DDR_A_DQS3 DDR_A_DQS#4 DDR_A_DQS4 DDR_A_DQS#5 DDR_A_DQS5 DDR_A_DQS#6 DDR_A_DQS6 DDR_A_DQS#7 DDR_A_DQS7

DDR_A_ALERT# DDR_A_PAR

+V_DDR_REFA_R

+V_DDR_REFB_R

DDR_VTT_CNTL

UC1C

DDR_A_CLK#0 <23> DDR_A_CLK0 <23> DDR_A_CLK#1 <23> DDR_A_CLK1 <23>

DDR_A_CKE0 <23> DDR_A_CKE1 <23>

TP9 TP11

DDR_A_CS#0 <23> DDR_A_CS#1 <23> DDR_A_ODT0 <23> DDR_A_ODT1 <23>

DDR_A_MA0 <23> DDR_A_MA1 <23> DDR_A_MA2 <23> DDR_A_MA3 <23> DDR_A_MA4 <23> DDR_A_MA5 <23> DDR_A_MA6 <23> DDR_A_MA7 <23> DDR_A_MA8 <23> DDR_A_MA9 <23> DDR_A_MA10 <23> DDR_A_MA11 <23> DDR_A_MA12 <23> DDR_A_MA13 <23>

DDR_A_WE# <23>

DDR_A_RAS# <23>

DDR_A_BA1 <23> DDR_A_BG0 <23>

DDR_A_BG1 <23>

DDR_A_DQS#0 <23> DDR_A_DQS0 <23> DDR_A_DQS#1 <23> DDR_A_DQS1 <23> DDR_A_DQS#2 <23> DDR_A_DQS2 <23> DDR_A_DQS#3 <23> DDR_A_DQS3 <23> DDR_A_DQS#4 <23> DDR_A_DQS4 <23> DDR_A_DQS#5 <23> DDR_A_DQS5 <23> DDR_A_DQS#6 <23> DDR_A_DQS6 <23> DDR_A_DQS#7 <23> DDR_A_DQS7 <23>

DDR_A_ALERT# <23> DDR_A_PAR <23> DDR_DRAMRST# <23>

CAD Note: Min trace width=20 mils, spacing of adjacent signal=20 mils

DDR_B_D[0..15]<24>

DDR_B_D[16..31]<24>

DDR_B_D[32..47]<24>

DDR_B_D[48..63]<24>

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

lnterleave / Non-lnterle ave d

J22

DDR1_DQ_0/DDR0_DQ_16

H25

DDR1_DQ_1/DDR0_DQ_17

G22

DDR1_DQ_2/DDR0_DQ_18

H22

DDR1_DQ_3/DDR0_DQ_19

F25

DDR1_DQ_4/DDR0_DQ_20

J25

DDR1_DQ_5/DDR0_DQ_21

G25

DDR1_DQ_6/DDR0_DQ_22

F22

DDR1_DQ_7/DDR0_DQ_23

D22

DDR1_DQ_8/DDR0_DQ_24

C22

DDR1_DQ_9/DDR0_DQ_25

C24

DDR1_DQ_10/DDR0_DQ_26

D24

DDR1_DQ_11/DDR0_DQ_27

A22

DDR1_DQ_12/DDR0_DQ_28

B22

DDR1_DQ_13/DDR0_DQ_29

A24

DDR1_DQ_14/DDR0_DQ_30

B24

DDR1_DQ_15/DDR0_DQ_31

G31

DDR1_DQ_16/DDR0_DQ_48

G32

DDR1_DQ_17/DDR0_DQ_49

H29

DDR1_DQ_18/DDR0_DQ_50

H28

DDR1_DQ_19/DDR0_DQ_51

G28

DDR1_DQ_20/DDR0_DQ_52

G29

DDR1_DQ_21/DDR0_DQ_53

H31

DDR1_DQ_22/DDR0_DQ_54

H32

DDR1_DQ_23/DDR0_DQ_55

L31

DDR1_DQ_24/DDR0_DQ_56

L32

DDR1_DQ_25/DDR0_DQ_57

N29

DDR1_DQ_26/DDR0_DQ_58

N28

DDR1_DQ_27/DDR0_DQ_59

L28

DDR1_DQ_28/DDR0_DQ_60

L29

DDR1_DQ_29/DDR0_DQ_61

N31

DDR1_DQ_30/DDR0_DQ_62

N32

DDR1_DQ_31/DDR0_DQ_63

AJ29

DDR1_DQ_32/DDR1_DQ_16

AJ30

DDR1_DQ_33/DDR1_DQ_17

AM32

DDR1_DQ_34/DDR1_DQ_18

AM31

DDR1_DQ_35/DDR1_DQ_19

AM30

DDR1_DQ_36/DDR1_DQ_20

AM29

DDR1_DQ_37/DDR1_DQ_21

AJ31

DDR1_DQ_38/DDR1_DQ_22

AJ32

DDR1_DQ_39/DDR1_DQ_23

AR31

DDR1_DQ_40/DDR1_DQ_24

AR32

DDR1_DQ_41/DDR1_DQ_25

AV30

DDR1_DQ_42/DDR1_DQ_26

AV29

DDR1_DQ_43/DDR1_DQ_27

AR30

DDR1_DQ_44/DDR1_DQ_28

AR29

DDR1_DQ_45/DDR1_DQ_29

AV32

DDR1_DQ_46/DDR1_DQ_30

AV31

DDR1_DQ_47/DDR1_DQ_31

BA32

DDR1_DQ_48/DDR1_DQ_48

BA31

DDR1_DQ_49/DDR1_DQ_49

BD31

DDR1_DQ_50/DDR1_DQ_50

BD32

DDR1_DQ_51/DDR1_DQ_51

BA30

DDR1_DQ_52/DDR1_DQ_52

BA29

DDR1_DQ_53/DDR1_DQ_53

BD29

DDR1_DQ_54/DDR1_DQ_54

BD30

DDR1_DQ_55/DDR1_DQ_55

BG31

DDR1_DQ_56/DDR1_DQ_56

BG32

DDR1_DQ_57/DDR1_DQ_57

BK32

DDR1_DQ_58/DDR1_DQ_58

BK31

DDR1_DQ_59/DDR1_DQ_59

BG29

DDR1_DQ_60/DDR1_DQ_60

BG30

DDR1_DQ_61/DDR1_DQ_61

BK30

DDR1_DQ_62/DDR1_DQ_62

BK29

DDR1_DQ_63/DDR1_DQ_63

WHL-U42_BGA1528

DDR1_DQSN_0/DDR0_DQSN_2 DDR1_DQSP_0/DDR0_DQSP_2 DDR1_DQSN_1/DDR0_DQSN_3 DDR1_DQSP_1/DDR0_DQSP_3 DDR1_DQSN_2/DDR0_DQSN_6 DDR1_DQSP_2/DDR0_DQSP_6 DDR1_DQSN_3/DDR0_DQSN_7 DDR1_DQSP_3/DDR0_DQSP_7 DDR1_DQSN_4/DDR1_DQSN_2 DDR1_DQSP_4/DDR1_DQSP_2 DDR1_DQSN_5/DDR1_DQSN_3 DDR1_DQSP_5/DDR1_DQSP_3 DDR1_DQSN_6/DDR1_DQSN_6 DDR1_DQSP_6/DDR1_DQSP_6 DDR1_DQSN_7/DDR1_DQSN_7 DDR1_DQSP_7/DDR1_DQSP_7

3 of 20

DDR4 COMPENSATION SIGNALS

SM_RCOMP0

RC17 121_ 0402_1%CML@

SM_RCOMP1

RC18 80.6 _0402_1%CML@

SM_RCOMP2

RC20 100_ 0402_1%

CAD Note: Trace width=15 mils, Spacing=25 mils(Within Group 20mils) Max trace length= 500 mils

LPDDR3 / DDR4

DDR1_CKN_0/DDR1_CKN_0

DDR1_CKP_0/DDR1_CKP_0

DDR1_CKN_1/DDR1_CKN_1

DDR1_CKP_1/DDR1_CKP_1

DDR1_CKE_0/DDR1_CKE_0 DDR1_CKE_1/DDR1_CKE_1

DDR1_CKE_2/NC DDR1_CKE_3/NC

DDR1_CS#_0/DDR1_CS#_0 DDR1_CS#_1/DDR1_CS#_1

DDR1_ODT_0/DDR1_ODT_0

NC/DDR1_ODT_1 DDR1_CAB_9/DDR1_MA_0 DDR1_CAB_8/DDR1_MA_1 DDR1_CAB_5/DDR1_MA_2

NC/DDR1_MA_3

NC/DDR1_MA_4 DDR1_CAA_0/DDR1_MA_5 DDR1_CAA_2/DDR1_MA_6 DDR1_CAA_4/DDR1_MA_7 DDR1_CAA_3/DDR1_MA_8 DDR1_CAA_1/DDR1_MA_9

DDR1_CAB_7/DDR1_MA_10 DDR1_CAA_7/DDR1_MA_11 DDR1_CAA_6/DDR1_MA_12 DDR1_CAB_0/DDR1_MA_13

DDR1_CAB_2/DDR1_MA_14 DDR1_CAB_1/DDR1_MA_15 DDR1_CAB_3/DDR1_MA_16

DDR1_CAB_4/DDR1_BA_0 DDR1_CAB_6/DDR1_BA_1 DDR1_CAA_5/DDR1_BG_0

DDR1_CAA_9/DDR1_BG_1 DDR1_CAA_8/DDR1_ACT#

lnterleave / Non-lnterleaved

NC/DDR1_ALERT#

NC/DDR1_PAR

DRAM_RESET#

DDR_RCOMP_0 DDR_RCOMP_1 DDR_RCOMP_2

1 2

AF28 AF29 AE28 AE29

T28 T29 V28 V29

AL37 AL35 AL36 AL34 AG36 AG35 AF34 AG37 AE35 AF35 AE37 AC29 AE36 AB29 AG34 AC28 AB28 AK35

AJ35 AK34 AJ34

AJ37 AJ36 W29

Y28 W28

H24 G24 C23 D23 G30 H30 L30 N30 AL31 AL30 AU31 AU30 BC31 BC30 BH31 BH30

Y29 AE34 BU31

BN28 BN27 BN29

DDR_B_CLK#0 DDR_B_CLK0 DDR_B_CLK#1 DDR_B_CLK1

DDR_B_CKE0 DDR_B_CKE1 DDR_B_CKE2 DDR_B_CKE3

DDR_B_CS#0 DDR_B_CS#1 DDR_B_ODT0 DDR_B_ODT1 DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13

DDR_B_WE# DDR_B_CAS# DDR_B_RAS#

DDR_B_BA0 DDR_B_BA1 DDR_B_BG0

DDR_B_BG1 DDR_B_ACT#DDR_A_ACT#

DDR_B_DQS#0 DDR_B_DQS0 DDR_B_DQS#1 DDR_B_DQS1 DDR_B_DQS#2 DDR_B_DQS2 DDR_B_DQS#3 DDR_B_DQS3 DDR_B_DQS#4 DDR_B_DQS4 DDR_B_DQS#5 DDR_B_DQS5 DDR_B_DQS#6 DDR_B_DQS6 DDR_B_DQS#7 DDR_B_DQS7

DDR_B_ALERT# DDR_B_PAR DDR_DRAMRST#

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

RC17 100_0402_1%

SD034100080

RC18 100_0402_1%

SD034100080

DDR_B_CLK#0 <24> DDR_B_CLK0 <24> DDR_B_CLK#1 <24> DDR_B_CLK1 <24>

DDR_B_CKE0 <24> DDR_B_CKE1 <24>

DDR_B_CS#0 <24> DDR_B_CS#1 <24> DDR_B_ODT0 <24> DDR_B_ODT1 <24> DDR_B_MA0 <24> DDR_B_MA1 <24> DDR_B_MA2 <24> DDR_B_MA3 <24> DDR_B_MA4 <24> DDR_B_MA5 <24> DDR_B_MA6 <24> DDR_B_MA7 <24> DDR_B_MA8 <24> DDR_B_MA9 <24> DDR_B_MA10 <24> DDR_B_MA11 <24> DDR_B_MA12 <24> DDR_B_MA13 <24>

DDR_B_WE# <24> DDR_B_CAS# <24> DDR_B_RAS# <24>DDR_A_CAS# <23>

DDR_B_BA0 <24> DDR_B_BA1 <24>DDR_A_BA0 <23> DDR_B_BG0 <24>

DDR_B_BG1 <24> DDR_B_ACT# <24>DDR_A_ACT# <23>

DDR_B_DQS#0 <24> DDR_B_DQS0 <24> DDR_B_DQS#1 <24> DDR_B_DQS1 <24> DDR_B_DQS#2 <24> DDR_B_DQS2 <24> DDR_B_DQS#3 <24> DDR_B_DQS3 <24> DDR_B_DQS#4 <24> DDR_B_DQS4 <24> DDR_B_DQS#5 <24> DDR_B_DQS5 <24> DDR_B_DQS#6 <24> DDR_B_DQS6 <24> DDR_B_DQS#7 <24> DDR_B_DQS7 <24>

DDR_B_ALERT# <24> DDR_B_PAR <24>

CNL@

TP10 TP12

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECT RONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECT RONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECT RONICS, INC.

2019/06/19 2020/06/30

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

CPU(2/12)DDR4

Size

Custom

Date : Sheet of

CPU(2/12)DDR4

Document Number Re v

LA-G717P

1

7 100Wednesday, June 19, 2019

1.0

5

smd.db-x7.ru

4

3

2

1

RC21~RC25 place colse to Device

CPU_SPI_0_CLK CPU_SPI_0_D1 CPU_SPI_0_D0 CPU_SPI_0_D2 CPU_SPI_0_D3 CPU_SPI_0_CS#0 CPU_SPI_0_CS#1

FFS_INT1

UC3

1

CS#

3

WP#

7

HOLD#

4

GND

W25Q64JVSSIQ_SO8

64Mb Flash ROM

UC3 place colse to UX1

UC11

1

CS#

3

WP#

7

HOLD#

4

GND

W25Q128JVSIQ_SO8

RC24

TPM@

10_0402_1%

SD034100A80

RC25

TPM@

10_0402_1%

SD034100A80

FFS_INT1

CPU_SPI_0_CS#0

CPU_SPI_0_D0

CPU_SPI_0_D2

CPU_SPI_0_D3

CPU_SPI_0_CLK

RC39 49.9_0402_1%FTPM@ RC41 49.9_0402_1%FTPM@

CPU_SPI_0_CS#1

RC177 49 .9_0402_1%FTPM@ RC181 49 .9_0402_1%FTPM@

CPU_SPI_CLK

CPU_SPI_D1 CPU_SPI_D0 CPU_SPI_D2 CPU_SPI_D3

1 2 1 2

CPU_SPI_CLK<65>

CPU_SPI_D1<65>

D D

C C

RC21 10_0402_1%

SD034100A80

RC22 10_0402_1%

SD034100A80

RC23 10_0402_1%

SD034100A80

+3VS

+3VALW_PCH +3.3V_SPI

+3.3V_SPI

Reserve For EC Auto Load Code

+3.3V_SPI

B B

A A

CPU_SPI_D0<65>

TPM@

1 2

RC27 10K_0402_5%

@

1 2

RC30 0_0603_5%

1 2

@

RC31 4.7K_0402_5%

1 2

RC35 100K_0402_5%

1 2

RC36 100K_0402_5%

1 2

RC37 100K_0402_5%

Follow 566439

1 2

RC187 100K_0402_5%

CPU_SPI_D3

+3.3V_SPI

1 2

RC207 4.7K_0402_5%

1 2

RC21 0_0402_5%

@

RC22 0_0402_5%

@

1 2 1 2

RC23 0_0402_5%

@

RC24 0_0402_5%

@

1 2

RC25 0_0402_5%

@

1 2

CPU_SPI_0_CS#2<65 >

TPM_SPI_IRQ#<65>

FFS_INT1<66>

RC21

FTPM@

S RES 1/16W 5.6 +-5% 0402

SD028560B80

RC22

FTPM@

S RES 1/16W 5.6 +-5% 0402

SD028560B80

RC23

FTPM@

S RES 1/16W 5.6 +-5% 0402

SD028560B80

RC24

FTPM@

S RES 1/16W 5.6 +-5% 0402

SD028560B80

RC25

FTPM@

S RES 1/16W 5.6 +-5% 0402

SD028560B80

CPU_SPI_0_CS#0 SPI_D2_ROMCPU_SPI_D2 SPI_D3_ROM

CPU_SPI_0_CS#1

SPI_D3_ROM2

UC1E

CH37

SPI0_CLK

CF37

SPI0_MISO

CF36

SPI0_MOSI

CF34

SPI0_IO2

CG34

SPI0_IO3

CG36

SPI0_CS0#

CG35

SPI0_CS1#

CH34

SPI0_CS2#

CF20

GPP_D1/SPI1_CLK/BK1/SBK1

CG22

GPP_D2/SPI1_MISO_IO1/BK2/SBK2

CF22

GPP_D3/SPI1_MOSI_IO0/BK3/SBK3

CG23

GPP_D21/SPI1_IO2

CH23

GPP_D22/SPI1_IO3

CG20

GPP_D0/SPI1_CS0#/BK0/SBK0

CH7

CL_CLK

CH8

CL_DATA

CH9

CL_RST#

BV29

GPP_A0/RCIN#/TIME_SYNC1

BV28

GPP_A6/SERIRQ

WHL-U42_BGA1528

XDP_HOOK3<79>

+3.3V_SPI

8

VCC

6

SCLK

5

SI/SIO0

2

SO/SIO1

+3.3V_SPI

8

VCC

6

SCLK

5

SI/SIO0

2

SO/SIO1

SPI - FLASH

SPI - TOUCH

C LINK

5 of 20

RC32 1K_0402_1%CMC@

1 2

RC40 place to within 1100 mil of SPIO_MOSI/SPI0_IO2 pin for XDP

1 2

CC4 0.1U_0402_10V7K

SPI_CLK_ROM SPI_D0_ROM SPI_D1_ROM

CC74 0.1U_0402_10V7K

SPI_CLK_ROM2CPU_SPI_D2 SPI_D2_ROM2 SPI_D0_ROM2 SPI_D1_ROM2

RC40 49.9_0402_1%FTPM@ RC42 49.9_0402_1%FTPM@ RC43 49.9_0402_1%FTPM@

1 2

RC178 49 .9_0402_1%FTPM@ RC180 49 .9_0402_1%FTPM@ RC179 49 .9_0402_1%FTPM@

1 2 1 2 1 2

CPU_SPI_D0

CPU_SPI_CLK CPU_SPI_D0 CPU_SPI_D1

CPU_SPI_CLK CPU_SPI_D0CPU_SPI_D3 CPU_SPI_D1

SMBUS , SMLINK

GPP_B23/SML1ALERT#/PCHHOT#

LPC , ESPI

GPP_A14/SUS_STAT#/ESPI_RESET#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

GPP_C0/SMBCLK

GPP_C1/SMBDATA

GPP_C2/SMBALERT#

GPP_C3/SML0CLK

GPP_C4/SML0DATA

GPP_C5/SML0ALERT#

GPP_C6/SML1CLK

GPP_C7/SML1DATA

GPP_A1/LAD0/ESPI_IO0 GPP_A2/LAD1/ESPI_IO1 GPP_A3/LAD2/ESPI_IO2 GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS#

GPP_A10/CLKOUT_LPC1

GPP_A8/CLKRUN#

RC39

TPM@

33_0402_1%

SD034330A80

RC40

TPM@

33_0402_1%

SD034330A80

RC41

TPM@

33_0402_1%

SD034330A80

RC42

TPM@

33_0402_1%

SD034330A80

RC43

TPM@

33_0402_1%

SD034330A80

CK14 CH15 CJ15

CH14 CF15 CG15

CN15 CM15 CC34

CA29 BY29 BY27 BV27 CA28 CA27

BV32 BV30 BY30

MEM_SMBCLK MEM_SMBDATA GPP_C2

SML0_SMBCLK SML0_SMBDATA GPP_C5

SML1_SMBCLK SML1_SMBDATA GPP_B23

ESPI_IO0 ESPI_IO1 ESPI_IO2 ESPI_IO3

ESPI_CLK

RC177

TPM@

33_0402_1%

SD034330A80

RC178

TPM@

33_0402_1%

SD034330A80

RC179

TPM@

33_0402_1%

SD034330A80

RC180

TPM@

33_0402_1%

SD034330A80

RC181

TPM@

33_0402_1%

SD034330A80

SML1_SMBCLK <58,65 >

SML1_SMBDATA <58,65>

ESPI_CS# <58> ESPI_RST# <58>

EMI@

1 2

RC26 33_0402_5%

1

CC3 10P_0402_50V8J

2

ESPI_RST#

RC205 100K_0402_5%

SPI_CLK_ROM

place colse to UC3

MEM_SMBCLK

MEM_SMBDATA

SML1 -> EC, THM

ESPI_CLK_R <58>

@RF@

12

33_0402_5%

RC45

@EMI@

1 2

33P_0402_50V8J

CC5

@EMI@

1 2

+3VS

5

3 4

ESPI_IO0 ESPI_IO1 ESPI_IO2 ESPI_IO3

SML0_SMBCLK

SML0_SMBDATA

QC1A

2

L2N7002DW1T1G_ SC88-6

1

6

QC1B L2N7002DW1T1G_ SC88-6

1 2 1 2

RC192 15 _0402_5% RC193 15 _0402_5%

1 2 1 2

RC194 15 _0402_5% RC195 15 _0402_5%

PCH_SMBDATA

PCH_SMBCLK

SML1_SMBCLK

SML1_SMBDATA

MEM_SMBCLK

MEM_SMBDATA

RC196 1K_0402_5%

RC197 1K_0402_5%

RC198 1K_0402_5%

RC199 1K_0402_5%

RC33 1K_0402_5%

RC34 1K_0402_5%

Weak Int. PD.

GPP_C2

TLS CONFIDENTIALITY

LOW(DEFAULT) HIGH

Weak Int. PD.

GPP_C5

EC interface

LOW(DEFAULT) HIGH

GPP_B23

Intel DCI-OOB

LOW(DEFAULT) HIGH

SMB -> DDR4, FFS, VGA

PCH_SMBCLK <23,24,40,66>

PCH_SMBDATA <23,24,40,66>

12

RC282.2 K_0402_5%

12

RC292.2 K_0402_5%

+3VALW_PCH

12

+3VALW_PCH

12

RC38 4.7K_0402_5%

DISABLE

ENABLE

+3VALW_PCH

12

RC44 4.7K_0402_5%

LPC eSPI

+3VALW_PCH

CMC@

12

RC46 4.7K_0402_5%

DISABLE

ENABLE

+3VS

ESPI_IO0_R <58> ESPI_IO1_R <58> ESPI_IO2_R <58> ESPI_IO3_R <58>

128Mb Flash ROM

UC11 place colse to UX1

5

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D DEPARTMENT E XCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT E XCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT E XCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2019/06/19 2020/06/30

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Re v

Custom

Date : Sheet o f

Compal Electronics, Inc.

CPU(3/12)SPI,ESPI,SMB,LPC

LA-G717P

1

8 1 00Wednesday, June 19, 2019

1.0

5

smd.db-x7.ru

ME_FWP

LOW = ENABLE -- >ME lock, can't update ME HIGH = DISABLE -->ME un-lock, can upd ate ME

1 2

HDA_SYNC_R<56>

HDA_BIT_CLK_R<56>

HDA_SDOUT_R<56>

ME_FWP<58>

D D

+3V_HDA

Flash Descriptor Security override

LOW(DEFAULT) HIGH

+3VALW_PCH

Weak Int. PD.

HDA_SDOUT

1 2

@

RC51 4.7K_ 0402_5%

ENABLE DISA BLE

Weak Int. PD.

1 2

RC57 4.7K_ 0402_5%

SPKR

@

RC47 33_0402_5%

1 2

RC48 33_0402_5%

1 2

RC49 33_0402_5%

1 2

RC50 1K_0402_5%

HDA_BIT_CLK

1

@RF@

CC6

2.2P_0201_2 5V8C

2

CNV_RF_RESET#<52>

CLKREQ_CNV#<5 2>

SPKR<56>

Top Swap Override

TPM_ID

1 2

@

1 2

@

DISABLE

ENABLE

BLUETOOTH_ EN

WIFI_RF_EN

COMPENSATION FOR CNV_WT_RCOMP

CAD Note: Min trace width=10 mils, Spacing=15 mils Max trace length=500 mils

LOW(DEFAULT) HIGH

C C

+3VALW_PCH

12

FTPM@

RC59 10K_0402_5 %

12

TPM@

RC63 10K_0402_5 %

B B

+3VALW

RC174 10K_0402_ 5%

RC175 10K_0402_ 5%

4

HDA_SYNC HDA_BIT_CLK HDA_SDOUT

HDA_SDIN0<56>

CNV_RF_RESET #

CLKREQ_CNV#

TPM_ID

SPKR

CNV_CRX_DTX_N0<52> CNV_CRX_DTX_P0<52>

CNV_CRX_DTX_N1<52>

CNV_CRX_DTX_P1<52> CNV_CTX_DRX_N0<52> CNV_CTX_DRX_P0<52>

CNV_CTX_DRX_N1<52> CNV_CTX_DRX_P1<52>

CLK_CNV_CRX_DTX_N<52> CLK_CNV_CRX_DTX_P<52> CLK_CNV_CTX_DRX_N<52> CLK_CNV_CTX_DRX_P<52>

1 2

RC60 150_0201_ 1%

Follow RVP

BLUETOOTH_EN<52> LCD_CBL_DET#<38>

1 2

@

RC61 10K_04 02_5%

+3VALW_PCH

UC1G

BN34

HDA_SYNC/I2S0_SFRM

BN37

HDA_BCLK/I2S0_SCLK

BN36

HDA_SDO/I2S0_TXD

BN35

HDA_SDI0/I2S0_RXD

BL36

HDA_SDI1/I2S1_RXD/SNDW1_DATA

BL35

HDA_RST#/I2S1_SCLK/SNDW1_CLK

CK23

GPP_D23/I2S_MCLK

BL37

I2S1_SFRM/SNDW2_CLK

BL34

I2S1_TXD/SNDW2_DATA

CJ32

GPP_H1/I2S2_SFRM/CNV_BT_I2S_BCLK/CNV_RF_RESET#

CH32

GPP_H0/I2S2_SCLK/CNV_BT_I2S_SCLK

CH29

GPP_H2/I2S2_TXD/CNV_BT_I2S_SDI/MODEM_CLKREQ

CH30

GPP_H3/I2S2_RXD/CNV_BT_I2S_SDO

CP24

GPP_D19/DMIC_CLK0/SNDW4_CLK

CN24

GPP_D20/DMIC_DATA0/SNDW4_DATA

CK25

GPP_D17/DMIC_CLK1/SNDW3_CLK

CJ25

GPP_D18/DMIC_DATA1/SNDW3_DATA

CF35

GPP_B14/SPKR

WHL-U42 _BGA1528

UC1I

CR30

CNV_WR_D0N

CP30

CNV_WR_D0P

CM30

CNV_WR_D1N

CN30

CNV_WR_D1P

CN32

CNV_WT_D0N

CM32

CNV_WT_D0P

CP33

CNV_WT_D1N

CN33

CNV_WT_D1P

CN31

CNV_WR_CLKN

CP31

CNV_WR_CLKP

CP34

CNV_WT_CLKN

CN34

CNV_WT_R COMP

PROJECT_ID1 PROJECT_ID2

BLUETOOTH_ EN LCD_CBL_D ET#

BOARD_ID2

A4WP_PRESEN T

CNV_WT_CLKP

CP32

CNV_WT_RCOMP_0

CR32

CNV_WT_RCOMP_1

CP20

GPP_F0/CNV_PA_BLANKING

CK19

GPP_F1

CG17

GPP_F2

CR14

GPP_C8/UART0_RXD

CP14

GPP_C9/UART0_TXD

CN14

GPP_C10/UART0_RTS#

CM14

GPP_C11/UART0_CTS#

CJ17

GPP_F8/CNV_MFUART2_RXD

CH17

GPP_F9/CNV_MFUART2_TXD

CF17

GPP_F23/A4WP_PRESENT

WHL-U42 _BGA1528

3

AUDIO SDIO / SDXC

GPP_A17/SD_VDD1_PWR_EN#/ISH_GP7

7 of 20

CNVio

GPP_H18/CPU_C10_GATE#

GPP_H19/TIMESYNC_0

GPP_H21/XTAL_FREQ_SELECT

GPP_D4/IMGCLKOUT0/BK4/SBK4

GPP_H20/IMGCLKOUT_1

GPP_F12/EMMC_DATA0 GPP_F13/EMMC_DATA1 GPP_F14/EMMC_DATA2

EMMC

GPP_F15/EMMC_DATA3 GPP_F16/EMMC_DATA4 GPP_F17/EMMC_DATA5 GPP_F18/EMMC_DATA6 GPP_F19/EMMC_DATA7

GPP_F20/EMMC_RCLK

GPP_F21/EMMC_CLK

GPP_F11/EMMC_CMD

GPP_F22/EMMC_RESET#

9 of 20

GPP_A16/SD_1P8_SEL

GPP_H22 GPP_H23 GPP_F10

GPD7

GPP_F3

EMMC_RCOMP

GPP_G0/SD_CMD GPP_G1/SD_DATA0 GPP_G2/SD_DATA1 GPP_G3/SD_DATA2 GPP_G4/SD_DATA3

GPP_G5/SD_CD# GPP_G6/SD_CLK

GPP_G7/SD_WP

SD_1P8_RCOMP SD_3P3_RCOMP

CN27

CM27

CF25 CN26 CM26 CK17

BV35 CN20

CG25 CH25

CR20 CM20 CN19 CM19 CN18 CR18 CP18 CM18

CM16 CP16 CR16 CN16

EMMC_RCOMP

CK15

CH36 CL35 CL36 CM35 CN35 CH35 CK36 CK34

BW36 BY31

CK33

SD_RCOMP

CM34

COMPENSATION FOR SD_RCOMP

CAD Note: Min trace width=10 mils, Spacing=12 mils Max trace length=500 mils

GPP_H21

GPP_H23

GPD7 PROJECT_ID3

WIFI_RF_EN

1 2

RM31 0_0402_5%

MMC@

EMMC_RST

TP13

1 2

RC64 200_0402_ 1%

COMPENSATION FOR EMMC_RCOMP

CAD Note: Min trace width=10 mils, Spacing=12 mils Max trace length=500 mils

KB_LED_BL_DET <62>

RC54 200_0402_ 1%

CPU_C10_GATE# <18>

WIFI_RF_EN <52>

EMMC_D0 <6 9> EMMC_D1 <6 9> EMMC_D2 <6 9> EMMC_D3 <6 9> EMMC_D4 <6 9> EMMC_D5 <6 9> EMMC_D6 <6 9> EMMC_D7 <6 9>

EMMC_RCLK <69>

EMMC_CLK <69> EMMC_CMD <69>

2

+1.8V_PRIM

12

PROJECT_ID1

12

PROJECT_ID3

12

RC53,RC 56 eMMC SKU Opt i onal

LOW HIGH

GPD PU to DSW PWR rail

GPD7

Weak Int. PD.

GPP_H21

1

INSPIRON@

RC52 10K_0402_5 %

VOSTRO@

RC55 10K_0402_5 %

RC58 100K _0402_5%

12

@

RC53 10K_0402_5 %

12

RC56 10K_0402_5 %

Stand ard Narrow Border

+3VALW_DSW

12

+3VALW_PCH

12

RC62 4.7K_0402 _5%

XTAL Frequency Select

LOW(DEFAULT) HIGH

Weak Int. PD.

GPP_H23

eSPI Flash Sharing Mode

LOW(DEFAULT) HIGH

38.4MHz 24MHz

+3VALW_PCH

12

@

RC65 4.7K_0402 _5%

MAF EABLE SAF EABLE

BOARD_ID2 (GPP_C 11)

---

RC69 RC71

12

RC70 10K_0402_5 %

12

@

RC72 10K_0402_5 %

BOARD_ID1 (GPP_C12 )

RC70 RC72

---

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2019/06/19 2020/06/30

Compal Secret Data

Deciphered Date

2

PROJECT_ID2

12

RC201 10K_0402_5 %

Title

Size Document Number R ev

Custom

Date : Sheet o f

LOW(DEFAULT) HIGH

Compal Electronics, Inc.

CPU(4/12)HDA,EMMC,SD

LA-G717P

1

PROJECT_ID2

UMA DIS

1.0

9 100Wednesday, June 19, 2 019

1.0

12

BASE@

RC69

BOARD_ID1<11>

CNV_RF_RESET #

1 2

CNV@

RC74 75K_0402_1 %

RC73 71.5K_0402_ 1%

1 2

@

CLKREQ_CNV#

A A

BOARD_ID2

CPU ID

CML-U

10K_0402_5 %

12

PREM@

RC71 10K_0402_5 %

WHL-U(Reserved) Pentium/Celeron

i3/i5/i7

5

4

5

smd.db-x7.ru

4

3

2

1

RC78,RC81.RC85,RC88 close to Device

CLK_PCIE_N1< 52>

WLAN--->

D D

LAN--->

SSD--->

CLK_PCIE_P1<52>

CLKREQ_PCIE#1<52>

CLKREQ_PCIE#2<51>

CLKREQ_PCIE#4<67>

+3VS

CLK_PCIE_N2< 51> CLK_PCIE_P2<51>

+3VS

CLK_PCIE_N4< 67> CLK_PCIE_P4<67>

+3VS

1 2

RC81 10K_0402_5%

1 2

RC85 10K_0402_5%

1 2

RC88 10K_0402_5%

PCH_PLTRST#

+3VS

UC4 change CPN & Description only

5

PCH_PLTRST#<69>

C C

1 2

CC79 0.1U_ 0402_10V7K

@ESD@

+3VALW_PCH

1 2

RC100 10K_0402 _5%

B B

+3VALW_DSW

1 2

RC92 4.7K_ 0402_5%

1 2

RC93 10K_ 0402_5%

PCH_PLTRS T#

UC4

MC74VHC1G08E DFT2G_SC70

SYS_PWROK

07/4 ESD require

SYS_RESET#

PCH_PCIE_W AKE#

LANWAKE#

Jason 2019-04-26

1

P

IN1

4

O

2

12

IN2

G

3

RC94

100K_0402_ 5%

TP20

H_VCCST_PW RGD<18>

PCIE_WAKE#<51,52,58,67>

PCH_RSMRST #_Q

PLTRST# <51,52,58,65,67>

PCH_RSMRST#_Q<79>

1 2

RC75 10K_0402_5%

1 2

RC76 1K_0402_5%@

1 2

RC99 62_0402_1 %

SYS_PWROK<58> RESET_OUT#<58>

1 2

@

RC101 0_0201_5%

1 2

@

RC102 0_0201_5%

LANWAKE#<58>

PCH_PLTRS T# SYS_RESET# PCH_RSMRST#_Q

H_CPUPW RGDH_CPUPW RGD_R VCCST_PWR GD

PCH_DPWROK

PCH_PCIE_W AKE#

UC1J

AW2

CLKOUT_PCIE_N_0

AY3

CLKOUT_PCIE_P_0

CF32

GPP_B5/SRCCLKREQ0#

BC1

CLKOUT_PCIE_N_1

BC2

CLKOUT_PCIE_P_1

CE32

GPP_B6/SRCCLKREQ1#

BD3

CLKOUT_PCIE_N_2

BC3

CLKOUT_PCIE_P_2

CF30

GPP_B7/SRCCLKREQ2#

BH3

CLKOUT_PCIE_N_3

BH4

CLKOUT_PCIE_P_3

CE31

GPP_B8/SRCCLKREQ3#

BA1

CLKOUT_PCIE_N_4

BA2

CLKOUT_PCIE_P_4

CE30

GPP_B9/SRCCLKREQ4#

BE1

CLKOUT_PCIE_N_5

BE2

CLKOUT_PCIE_P_5

CF31

GPP_B10/SRCCLKREQ5#

WHL-U42 _BGA1528

UC1K

BJ35

GPP_B13/PLTRST#

CN10

SYS_RESET#

BR36

RSMRST#

AR2

PROCPWRGD

BJ2

VCCST_PWRGOOD

CR10

SYS_PWROK

BP31

PCH_PWROK

BP30

DSW_PWROK

BV34

GPP_A13/SUSWARN#/SUSPW RDACK

BY32

GPP_A15/SUSACK#

BU30

WAKE#

BU32

GPD2/LAN_WAKE#

BU34

GPD11/LANPHYPC

WHL-U42 _BGA1528

CLOCK SINGNALS

10 of 20

SYSTEM POW ER MANAGEMENT

11 of 20

CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P

AU1 AU2

XTAL_IN

XTAL_OUT

CLKIN_XTAL

RTCX1 RTCX2

SRTCRST#

RTCRST#

GPP_B12/SLP_S0#

GPD4/SLP_S3# GPD5/SLP_S4#

GPD10/SLP_S5#

GPD9/SPL_WLAN#

GPD6/SLP_A#

GPD3/PWRBTN#

GPD1/ACPRESENT

GPD0/BATLOW#

GPP_B2/VRALERT#

BT32

CK3 CK2

CJ1 CM3

BN31 BN32

BR37 BR34

SLP_SUS# SLP_LAN#

INTRUDER#

INPUT3VSEL

GPD8/SUSCLK

XCLK_BIASREF

GPP_B11/EXT_PWR_GATE#

CLK_ITPXDP_N CLK_ITPXDP_P

SUSCLK

XTAL24_IN XTAL24_OUT

XCLK_BIASREF REFCLK_CNV_R

PCH_RTCX1 PCH_RTCX2

PCH_SRTCR ST# PCH_RTCR ST#

BJ37 BU36 BU27 BT29

BU29 BT31 BT30 BU37

BU28 BU35 BV36

BR35

CC37 CC36

BT27

TP14 TP15

RC79 0_020 1_5%

RC80 0_020 1_5%

1 2

RC83 60.4_0402_1 %

1 2

RC84

EMI@

BLM15BD121 SN1D_2P

12

RC86 10K_0402_5 %

COMPENSATION FOR XCLK_BIASREF

CAD Note: Min trace width=10 mils, Spacing=15 mils Max trace l ength=1000 mils

SIO_SLP_S3# SIO_SLP_S4#

SIO_SLP_S0# SIO_SLP_S3# SIO_SLP_S4# SIO_SLP_S5#

SIO_SLP_SUS# SIO_SLP_LAN# SIO_SLP_WLAN# SIO_SLP_A#

SIO_PWRBTN# AC_PRESENT PCH_BATLOW #

INTRUDER#

EXT_PWR_GAT E#

INPUT3VSEL

TP17 TP18

TP16

SIO_SLP_S3# <18,78> SIO_SLP_S4# <18,78,86> SIO_SLP_S5# <84>

TP19

TP21

TP22

TP23

SIO_PWRBTN# <58>

TP24

1 2

CNV@

1 2

@

SUSCLK_WLAN <52>

SUSCLK_EC <58>

REFCLK_CNV <52>

CLRP1, CLRP2 Always Open

XTAL24_IN XTAL24_OUT

PCH_RTCX1 PCH_RTCX2

PCH_SRTCR ST#

PCH_RTCR ST#

INTRUDER#

1 2

RC89 3 3_0402_5%EMI@

12

1 2

EMI@

RC91 3 3_0402_5%

RC95 10M_0402_ 5%

1 2

PCH_BATLOW #

AC_PRESENT

SIO_PWRBTN#

AC_PRESENT

SIO_SLP_S3#

SIO_SLP_S4#

INPUT3VSEL

RC77 20K_0402_5 %

1 2

CC7 1U_0201_6.3V6M

1 2

CLRP1 SHORT PADSJP@

RC82 20K_0402_5 %

1 2

CC8 1U_0201_6.3V6M

1 2

CLRP2 SHORT PADSJP@

RC87 1M_040 2_5%

XTAL24_IN_R

200K_0402_1%

RC90

3

4

YC1 24MHZ_12PF_X3G0 24000DC1H

1

2

XTAL24_OUT_R

CC11

1 2

6.8P_0402_5 0V8C

12

YC2

32.768KHZ_9P F_X1A000141000200

20ppm / 9pF ESR <5 0kohm (MAX)

CC12

1 2

6.8P_0402_5 0V8C

12

RC96 10K_0402_5 %

12

@

RC97 10K_0402_5 %

12

@

RC98 100K_0402_ 5%

12

RC66 10K_0402_5 %

12

RC10 100K_0402_ 5%

12

RC11 100K_0402_ 5%

1 2

CC76 0.1U _0402_10V7K

@ESD@

RC103 4.7K_0402_5%

1 2

RC104 4.7K_0402_5%

+RTC_SOC

12

CLR all register bits

12

CLR CMOS

12

CC9

1 2

15P_0201_2 5V8J

CC10

1 2

15P_0201_2 5V8J

+3VALW_DSW

CML need PD

+3VALW_DSW

12

@

3.0V Select

LOW

0: 3.3V supply is 3.3V +- 5%

HIGH

1: 3.3V supply is 3.0V +- 5%

POK

1M_0402_5%

1U_0201_6.3V6M

A A

12

RC105

CC14

5

RSMRST circuit

PCH_RSMRST#<58>

POK<78,82,85>

UC5 change CPN & Description only

Jason 2019-04-26

+3VALW

CC13

@

1 2

0.1U_0402_ 10V7K

5

1

P

IN1

2

POK

IN2

3

PCH_RSMRST #_Q

4

O

G

UC5

SN74AHC1G08D CKR_SC70-5

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2019/06/19 2020/06/30

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number R ev

Custom

Date : Sheet o f

Compal Electronics, Inc.

CPU(5/12)CLK,GPIO

LA-G717P

1

10 100Wednesday, June 19, 2019

1.0

5

smd.db-x7.ru

4

3

2

1

+1.8V_PRIM

1 2

CNV@

RC121 20K_ 0402_5%

1 2

CNV@

RC122 20K_ 0402_5%

1 2

RC202 20K_ 0402_5%

D D

+3VS

1 2

RC106 10K_ 0402_5%

+1.8V_PRIM

1 2

RC162 20K_0402 _5%

1 2

RC108 4.7K_ 0402_5%

@

CNV@

@

CNV_BRI_CRX_DTX

CNV_RGI_CRX_DTX

CNV_BRI_CTX_DRX

DBC_PANEL_EN

CNV_RGI_CTX_DRX

M.2 CNV Mode Select

LOW HIGH

+3VALW_PCH

C C

CNVi ENABLE CNVi DISABLE

Weak Int. PD.

NRB_BIT

1 2

@

RC112 4.7K_ 0402_5%

NO REBOOT Mode

LOW(DEFAULT) HIGH

+3VALW_PCH

DISABLE

ENABLE

Weak Int. PD.

SD_READ_MODE

1 2

@

RC115 4.7K_ 0402_5%

Boot BIOS Strap

LOW(DEFAULT) HIGH

B B

SPI

LPC

RC202 close JWLAN1

CNV_BRI_CRX_DTX<52> CNV_RGI_CTX_DRX<52> CNV_BRI_CTX_DRX<52>

CNV_RGI_CRX_DTX<5 2>

SIO_EXT_WAKE#<58>

UC1F

CC27

GPP_B15/GSPI0_CS0#

CC32

GPP_A7/PIRQA#/GSPI0_CS1#

CE28

GPP_B16/GSPI0_CLK

CE27

NRB_BIT

TP25

CNV_BRI_CRX_DTX

CNV_RGI_CTX_DRX CNV_BRI_CTX_DRX

CNV_RGI_CRX_DTX

SIO_EXT_WAKE# KB_DET#

DBC_PANEL_EN GPP_A11

TOUCH_I2C_D ET#

SD_READ_MODE

DBC_PANEL_EN<38>

PCH_3.3V_TS_EN<38>

KB_DET#< 62>

I2C_0_SDA<62>

I2C_0_SCL<62>

I2C_1_SDA<38>

I2C_1_SCL<38>

GPP_B17/GSPI0_MISO

CE29

GPP_B18/GSPI0_MOSI

CA31

GPP_B19/GSPI1_CS0#

CA32

GPP_A11/PME#/GSPI1_CS1#/SD_VDD2_PWR_EN#

CC29

GPP_B20/GSPI1_CLK

CC30

GPP_B21/GSPI1_MISO

CA30

GPP_B22/GSPI1_MOSI

CK20

GPP_F5/CNV_BRI_RSP

CG19

GPP_F6/CNV_RGI_DT

CJ20

GPP_F4/CNV_BRI_DT

CH19

GPP_F7/CNV_RGI_RSP

CR12

GPP_C20/UART2_RXD

CP12

GPP_C21/UART2_TXD

CN12

GPP_C22/UART2_RTS#

CM12

GPP_C23/UART2_CTS#

CM11

GPP_C16/I2C0_SDA

CN11

GPP_C17/I2C0_SCL

CK12

GPP_C18/I2C1_SDA

CJ12

GPP_C19/I2C1_SCL

CF27

GPP_H4/I2C2_SDA

CF29

GPP_H5/I2C2_SCL

CH27

GPP_H6/I2C3_SDA

CH28

GPP_H7/I2C3_SCL

CJ30

GPP_H8/I2C4_SDA

CJ31

GPP_H9/I2C4_SCL

WHL-U42 _BGA1528

+3VALW_PCH

12

TS_NON@

RC208

TOUCH_I2C_D ET#

10K_0402_5 %

12

TS_I2C@

RC209 10K_0402_5 %

I2C , UART

Change Touch screen detect strap pin define

Jason 2019-06-18

ISH

6 of 20

GPP_D9/ISH_SPI_CS#/GSPI2_CS0#

GPP_D10/ISH_SPI_CLK/GSPI2_CLK GPP_D11/ISH_SPI_MISO/GSPI2_MISO GPP_D12/ISH_SPI_MOSI/GSPI2_MOSI

GPP_D5/ISH_I2C0_SDA GPP_D6/ISH_I2C0_SCL

GPP_D7/ISH_I2C1_SDA GPP_D8/ISH_I2C1_SCL

GPP_H10/I2C5_SDA/ISH_I2C2_SDA

GPP_H11/I2C5_SCL/ISH_I2C2_SCL

GPP_D13/ISH_UART0_RXD

GPP_D14/ISH_UART0_TXD

GPP_D15/ISH_UART0_RTS#/GSPI2_CS1#

GPP_D16/ISH_UART0_CTS#/SML0BALERT#

GPP_C12/UART1_RXD/ISH_UART1_RXD

GPP_C13/UART1_TXD/ISH_UART1_TXD GPP_C14/UART1_RTS#/ISH_UART1_RTS# GPP_C15/UART1_CTS#/ISH_UART1_CTS#

GPP_A12/ISH_GP6/BM_BUSY#/SX_EXIT_HOLDOFF#

GPP_A18/ISH_GP0 GPP_A19/ISH_GP1 GPP_A20/ISH_GP2 GPP_A21/ISH_GP3 GPP_A22/ISH_GP4 GPP_A23/ISH_GP5

CN22 CR22 CM22 CP22

CK22 CH20

CH22 CJ22

CJ27 CJ29

CM24 CN23 CM23 CR24

CG12 CH12 CF12 CG14

BW35 BW34 CA37 CA36 CA35 CA34 BW37

CAM_DET# RTC_DET#

FFS_INT2 UART1_RTS# UART1_CTS#

CAM_DET# <3 8> RTC_DET# <65>

BOARD_ID1 <9>

FFS_INT2 <6 6>

TP26 TP27

CAM_DET#

FFS_INT2

KB_DET#

RTC_DET#

SIO_EXT_WAKE#

12

RC204 1 0K_0402_5%

12

RC109 1 0K_0402_5%

+3VALW_PCH

12

RC110 1 0K_0402_5%

12

RC111 1 00K_0402_5%

12

RC113 1 0K_0402_5%

+3VS

RC208,R C209 Touch panel interface

LOW HIGH

I2C

USB

VRAM ID

(PCBA VRAM Size Config.)

2G GDDR5 Reserved Reserved Reserved

VBIOS_ID2 (GPP_CN23)

0 0 1 1

VBIOS_ID1

(GPP_CE27)

0 1 0 1

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2019/06/19 2020/06/30

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number R ev

Custom

Date : Sheet o f

2

Date : Sheet o f

Compal Electronics, Inc.

CPU(6/12)GPIO

LA-G717P

1

11 100Wednesday, June 19, 2019

1.0

5

smd.db-x7.ru

4

3

2

1

UC1H

BW9

PCIE5_RXN/USB31_5_RXN

BW8

PCIE5_RXP/USB31_5_RXP

BW4

PCIE5_TXN/USB31_5_TXN

BW3

D D

PCIE_CRX_DTX_N9<51> PCIE_CRX_DTX_P9<51>

LOM --->

WLAN --->

C C

SATA HDD --->

SATA ODD --->

PCIE SSD --->

B B

PCIE_CTX_DRX_N9<51> PCIE_CTX_DRX_P9<51>

PCIE_CRX_DTX_N10<52> PCIE_CRX_DTX_P10<52> PCIE_CTX_DRX_N10<52> PCIE_CTX_DRX_P10<52>

SATA_CR X_DTX_N0<66>

SATA_CR X_DTX_P0<66> SATA_CT X_DRX_N0<66> SATA_CT X_DRX_P0<66>

SATA_CR X_DTX_N1<66>

SATA_CR X_DTX_P1<66>

SATA_CT X_DRX_N1<66> SATA_CT X_DRX_P1<66>

PCIE_CRX_ DTX_N13<67>

PCIE_CRX_ DTX_P13<67>

PCIE_CTX_ DRX_N13<67> PCIE_CTX_ DRX_P13<67>

PCIE_CRX_ DTX_N14<67>

PCIE_CRX_ DTX_P14<67>

PCIE_CTX_ DRX_N14<67> PCIE_CTX_ DRX_P14<67>

PCIE_CRX_ DTX_N15<67>

PCIE_CRX_ DTX_P15<67>

PCIE_CTX_ DRX_N15<67> PCIE_CTX_ DRX_P15<67>

PCIE_CRX_ DTX_N16<67>

PCIE_CRX_ DTX_P16<67>

PCIE_CTX_ DRX_N16<67> PCIE_CTX_ DRX_P16<67>

1 2

RC126 100_040 2_1%

PCIE_RCOM PN PCIE_RCOM PP

COMPENSATION FOR PCIE_RCOMP

CAD Note: Min trace width=10 mils Max trace mismatch=5 mils

PCIE5_TXP/USB31_5_TXP

BU6

PCIE6_RXN/USB31_6_RXN

BU5

PCIE6_RXP/USB31_6_RXP

BU4

PCIE6_TXN/USB31_6_TXN

BU3

PCIE6_TXP/USB31_6_TXP

BT7

PCIE7_RXN

BT6

PCIE7_RXP

BU2

PCIE7_TXN

BU1

PCIE7_TXP

BU9

PCIE8_RXN

BU8

PCIE8_RXP

BT4

PCIE8_TXN

BT3

PCIE8_TXP

BP5

PCIE9_RXN

BP6

PCIE9_RXP

BR2

PCIE9_TXN

BR1

PCIE9_TXP

BN6

PCIE10_RXN

BN5

PCIE10_RXP

BR4

PCIE10_TXN

BR3

PCIE10_TXP

BN10

PCIE11_RXN/SATA0_RXN

BN8

PCIE11_RXP/SATA0_RXP

BN4

PCIE11_TXN/SATA0_TXN

BN3

PCIE11_TXP/SATA0_TXP

BL6

PCIE12_RXN/SATA1A_RXN

BL5

PCIE12_RXP/SATA1A_RXP

BN2

PCIE12_TXN/SATA1A_TXN

BN1

PCIE12_TXP/SATA1A_TXP

BK6

PCIE13_RXN

BK5

PCIE13_RXP

BM4

PCIE13_TXN

BM3

PCIE13_TXP

BJ6

PCIE14_RXN

BJ5

PCIE14_RXP

BL2

PCIE14_TXN

BL1

PCIE14_TXP

BG5

PCIE15_RXN/SATA1B_RXN

BG6

PCIE15_RXP/SATA1B_RXP

BL4

PCIE15_TXN/SATA1B_TXN

BL3

PCIE15_TXP/SATA1B_TXP

BE5

PCIE16_RXN/SATA2_RXN

BE6

PCIE16_RXP/SATA2_RXP

BJ4

PCIE16_TXN/SATA2_TXN

BJ3

PCIE16_TXP/SATA2_TXP

CE6

PCIE_RCOMP_N

CE5

PCIE_RCOMP_P

CR28

GPP_H12/M2_SKT2_CFG_0

CP28

GPP_H13/M2_SKT2_CFG_1

CN28

GPP_H14/M2_SKT2_CFG_2

CM28

GPP_H15/M2_SKT2_CFG_3

WHL -U42_BGA1528

PCIE / USB3.1 / SATA

8 of 20

A A

PCIE1_RXN/USB31_1_RXN PCIE1_RXP/USB31_1_RXP PCIE1_TXN/USB31_1_TXN

PCIE1_TXP/USB31_1_TXP

PCIE2_RXN/USB31_2_RXN/SSIC_1_RXN

PCIE2_RXP/USB31_2_RXP/SSIC_1_RXP

PCIE2_TXN/USB31_2_TXN/SSIC_1_TXN

PCIE2_TXP/USB31_2_TXP/SSIC_1_TXP

PCIE3_RXN/USB31_3_RXN PCIE3_RXP/USB31_3_RXP PCIE3_TXN/USB31_3_TXN

PCIE3_TXP/USB31_3_TXP

PCIE4_RXN/USB31_4_RXN PCIE4_RXP/USB31_4_RXP PCIE4_TXN/USB31_4_TXN

PCIE4_TXP/USB31_4_TXP

USB2.0

USB2_COMP

USB2_VBUSSENSE

GPP_E9/USB2_OC0#/GP_BSSB_CLK

GPP_E10/USB2_OC1#/GP_BSSB_DI

GPP_E11/USB2_OC2# GPP_E12/USB2_OC3#

GPP_E4/DEVSLP0 GPP_E5/DEVSLP1 GPP_E6/DEVSLP2

GPP_E0/SATAXPCIE0/SATAGP0 GPP_E1/SATAXPCIE1/SATAGP1 GPP_E2/SATAXPCIE2/SATAGP2

GPP_E8/SATALED#/SPI1_CS1#

GPI O

USB_ OC0 #

USB_ OC1 #

USB_ OC2 #

USB_ OC3 #

DEVS LP0

DEVS LP1

DEVS LP2

DEVICE CONTROL

USB Port (MB)

USB Port (DB)

NA

USB P ort (T ype-C)

HDD

NA

M.2 SSD

USB2_1N USB2_1P

USB2_2N USB2_2P

USB2_3N USB2_3P

USB2_4N USB2_4P

USB2_5N USB2_5P

USB2_6N USB2_6P

USB2_7N USB2_7P

USB2_8N USB2_8P

USB2_9N USB2_9P

USB2_10N USB2_10P

USB2_ID

RSVD_69

CB5 CB6 CA4 CA3

BY8 BY9 CA2 CA1

BY7 BY6 BY4 BY3

BW6 BW5 BW2 BW1

CE3 CE4

CE1 CE2

CG3 CG4

CD3 CD4

CG5 CG6

CC1 CC2

CG8 CG9

CB8 CB9

CH5 CH6

CC3 CC4

CC5 CE8 CC6

CK6 CK5 CK8 CK9

CP8 CR8 CM8

CN8 CM10 CP10

CN7

AR3

USB2_CO MP USB2_ID USB2_VB USSENSE

USB_OC0 # USB_OC1 # USB_OC2 # USB_OC3 #

SATA_LE D#

USB3_CRX_DTX_N1 <71> USB3_CRX_DTX_P1 <71> USB3_CTX_DRX_N1 <71> USB3_CTX_DRX_P1 <71>

USB3_CRX_DTX_N2 <71> USB3_CRX_DTX_P2 <71> USB3_CTX_DRX_N2 <71> USB3_CTX_DRX_P2 <71>

USB3_CRX_MTX_N4 <42> USB3_CRX_MTX_P4 < 42> USB3_CTX_MRX_N4 <42> USB3_CTX_MRX_P4 <42>

USB20_N 1 <71> USB20_P 1 < 71>

USB20_N 2 <71> USB20_P 2 < 71>

USB20_N 3 <73> USB20_P 3 < 73>

USB20_N 4 <43> USB20_P 4 < 43>

USB20_N 5 <65> USB20_P 5 < 65>

USB20_N 6 <38> USB20_P 6 < 38>

USB20_N 7 <73> USB20_P 7 < 73>

USB20_N 8 <43> USB20_P 8 < 43>

USB20_N 10 <52> USB20_P 10 <52>

1 2

RC123 113_040 2_1%

1 2

RC124 0_0402_ 5%@

1 2

RC125 0_0201_ 5%@

USB_OC0# <71> USB_OC1# <73>

USB_OC3# <42>

HDD_DEVSLP <66>

SSD_DEVSLP <6 7>

SATA_OD D_PRSNT# <66> M2_SSD_ PEDET <67>

SATA_LED# <62,67>

SATA_LE D#

USB_OC3 # USB_OC0 # USB_OC1 # USB_OC2 #

1 2

RC127 10K_0402_5%

1 2 1 2

RC188 10K_040 2_5%

1 2

RC189 10K_040 2_5%

1 2

RC190 10K_040 2_5% RC191 10K_040 2_5%

---> USB3.0 (MB)

---> TYPE C

-----> USB2.0 (MB)

-----> USB2.0 (M/B)

-----> USB2.0 (IO/B)

-----> TYPE C

-----> Finger Printer

-----> CCD

-----> Card Reader (IO/B)

-----> Touch Screen

-----> BT

3/30 layout: RC123,RC125 change to 0201

COMPENSATION FOR USB2_COMP

CAD Note: Min trace width=50 Ohm, Spacing=15 mils Max trace length=500 mils

+3VS

+3VALW_P CH

Port 4, 8 Colay Opt i onal

Security Classification

2019/06/ 19 2020/06/ 30

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

2019/06/ 19 2020/06/ 30

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Re v

Custom

Date : Sheet o f

2

Date : Sheet o f

Compal Electronics, Inc.

CPU(7/12)PCIE,USB,SATA

LA-G717P

12 100W ednesday, June 19, 2019

1

1.0

5

smd.db-x7.ru

4

3

2

1

1 2

+VCCIO

4.06 6A

+VCC_SA

6A

VCCIO_SENSE VSSIO_SENSE

TP30 TP31

12

RC165 100_0402_1%

VSA_SEN- <88> VSA_SEN+ <88>

Trace Length Match< 25 mils

1

2

+VCCIO

10U_0402_6.3V6M

1

2

+VCCIO : 10UF/6.3V/0402 *6 1UF/6.3V/0402 * 8

+1.2V_DDR

22U_0603_6.3V6M

1

2

CC16

CC15

2

10U_0402_6.3V6M

1

CC20

2

1

CC34

2

10U_0402_6.3V6M

1

CC21

CC22

2

10U_0402_6.3V6M

1

CC35

CC36

2

0.1U_0201_6.3V6K

1U_0402_6.3V6K

1

+VCCPLL_OC +VCCST

PSC Side, BL27,BM26

1U_0402_6.3V6K

1

CC17

2

10U_0402_6.3V6M

1

CC23

2

10U_0402_6.3V6M

1

CC37

2

10U_0402_6.3V6M

1

CC25

CC24

2

10U_0402_6.3V6M

1

CC39

CC38

2

1

2

1U_0201_6.3V6M

1

CC26

2

10U_0402_6.3V6M

1

CC40

2

+VCCSTG+VCCST

PSC Side, BP11,BP2 PSC Side, BG1,BG2PSC Side, BR11,BT11

22U_0603_6.3V6M

1U_0402_6.3V6K

CC18

@

1

CC72

2

1U_0402_6.3V6K

1

CC19

2

PSC SideBSC Side

1U_0201_6.3V6M

1

CC27

2

1U_0201_6.3V6M

1

CC28

CC29

2

1U_0201_6.3V6M

@

1

2

@

1

CC30

CC31

2

1U_0201_6.3V6M

@

1

CC33

CC32

2

BSC SidePSC Side

1U_0201_6.3V6M

1

CC41

2

1U_0201_6.3V6M

1

CC42

CC43

2

10U_0402_6.3V6M

1U_0201_6.3V6M

1

CC44

2

10U_0402_6.3V6M

1

CC45

2

10U_0402_6.3V6M

1

CC46

CC47

2

+1.2V_DDR

UC1N

AD36

3.3 A

D D

+VCCST

+VCCSTG

+VCCPLL_OC

+VCCST

C C

B B

60

20

12 0

13 0

AH32

AH36 AM36 AN32

AW32

AY36

BE32 BH36

R32 Y36

BC28

BP11

BP2

BG1 BG2

BL27 BM26

BR11

BT11

WHL-U42_BGA1528

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 VDDQ11

RSVD1

VCCST1 VCCST2

VCCSTG1 VCCSTG2

VCCPLL_OC1 VCCPLL_OC2

VCCPLL1 VCCPLL2

CPU POWER 3 OF 4

14 of 20

VCCIO_SENSE

VSSIO_SENSE

VSSSA_SENSE

VCCSA_SENSE

+VCC_SA

AK24

VCCIO1

AK26

VCCIO2

AL24

VCCIO3

AL25

VCCIO4

AL26

VCCIO5

AL27

VCCIO6

AM25

VCCIO7

AM27

VCCIO8

BH24

VCCIO9

BH25

VCCIO10

BH26

VCCIO11

BH27

VCCIO12

BJ24

VCCIO13

BJ26

VCCIO14

BP16

VCCIO15

BP18

VCCIO16

BG8

VCCSA2

BG10

VCCSA1

BH9

VCCSA3

BJ8

VCCSA5

BJ9

VCCSA6

BJ10

VCCSA4

BK8

VCCSA9

BK25

VCCSA7

BK27

VCCSA8

BL8

VCCSA13

BL9

VCCSA14

BL10

VCCSA10

BL24

VCCSA11

BL26

VCCSA12

BM24

VCCSA15

BN25

VCCSA16

BP28 BP29

BE7 BG7

RC164 100_0402_1%

+1.2V_VDDQ : 22UF/6.3V/0603 *1 10UF/6.3V/0603 *9 1UF/6.3V/0402 * 4

A A

Security Classification

2019/06/19 2020/06/30

Issued Date

5

4

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2019/06/19 2020/06/30

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size

B

Date : Sheet o f

2

Date : Sheet o f

Compal Electronics, Inc.

CPU(8/12)POWER

Document Number Re v

CPU(8/12)POWER

LA-G717P

1

13 100Wednesday, June 19, 2019

1.0

5

smd.db-x7.ru

+1.05V_PRIM

1 2

@

RC128 0_0603_5%

1U_0201_6.3V6M

1

CC53

2

1U_0201_6.3V6M

1

CC56

2

Close to CP17

1U_0201_6.3V6M

1

CC64

2

1

2

1

2

1

2

1

2

1

2

D D

+1.05V_PRIM

1 2

RC129 0_0603_5%

+1.05V_PRIM

C C

+3VALW_PCH

B B

+3VALW_PCH

A A

1 2

RC130 0_0603_5%

1 2

@

RC131 0_0402_5%

1 2

@

RC132 0_0402_5%

+1.8V_PRIM

22U_0603_6.3V6M

CC49

1U_0201_6.3V6M

CC81

1U_0201_6.3V6M

CC80

1U_0201_6.3V6M

CC60

1U_0201_6.3V6M

Close to BR24

@

CC63

+1.05V_MPHY

Close to BV12

47U_0603_6.3V6M

12

CC54

47U_0603_6.3V6M

Close to CP5

12

CC57

+3V_HDA

Close to BT20

+3VALW_DSW

+3VALW_PCH

Close to CP29

1U_0201_6.3V6M

1

2

+1.05V_MPHYPLL

Close to BV2

+1.05V_XTAL

0.1U_0201_6.3V6K

1

@

CC65

2

5

4

1

2

+1.05V_PRIM

1U_0201_6.3V6M

CC82

4.26 A

24

69 6

Intenal VRM

2.87 8A

15 2

1

6

2

Close to BP20

1U_0201_6.3V6M

1

CC48

2

+1.8V_PRIM

+3VALW_PCH

+1.05V_PRIM

Close to BV18

1U_0201_6.3V6M

1

@

CC55

2

+1.05V_VCCDSW

Close to BT24

1U_0201_6.3V6M

1

+1.05V_PRIM

CC59

+1.05V_MPHY

2

+1.05V_MPHYPLL

+1.05V_PRIM

@

CC66

4

+3VALW_DSW

+3V_HDA

+3.3V_SPI

1U_0201_6.3V6M

1

CC62

2

+1.05V_MPHY

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

1.62 5A

28 0

2019/06/19 2020/06/30

UC1P

BP20

VCCPRIM_1P05_1

BW16

VCCPRIM_1P05_9

BW18

VCCPRIM_1P05_10

BW19

VCCPRIM_1P05_11

BY16

VCCPRIM_1P05_12

CA14

VCCPRIM_1P05_14

CC15

VCCPRIM_1P8_1

CD15

VCCPRIM_1P8_4

CD16

VCCPRIM_1P8_5

CP17

VCCPRIM_1P8_8

CB22

VCCPRIM_3P3_4

CB23

VCCPRIM_3P3_5

CC22

VCCPRIM_3P3_6

CC23

VCCPRIM_3P3_7

CD22

VCCPRIM_3P3_8

CD23

VCCPRIM_3P3_9

CP29

VCCPRIM_3P3_10

BU15

VCCPRIM_CORE1

BU22

VCCPRIM_CORE2

BV15

VCCPRIM_CORE3

BV16

VCCPRIM_CORE4

BV18

VCCPRIM_CORE5

BV19

VCCPRIM_CORE6

BV20

VCCPRIM_CORE7

BV22

VCCPRIM_CORE8

BW20

VCCPRIM_CORE9

BW22

VCCPRIM_CORE10

CA12

VCCPRIM_CORE11

CA16

VCCPRIM_CORE12

CA18

VCCPRIM_CORE13

CA19

VCCPRIM_CORE14

CA20

VCCPRIM_CORE15

CB12

VCCPRIM_CORE16

CB14

VCCPRIM_CORE17

CB15

VCCPRIM_CORE18

BT24

VCCDSW_1P05

BU14

VCCAPLL_1P05_4

BV12

VCCPRIM_MPHY_1P05_1

BW12

VCCPRIM_MPHY_1P05_3

BW14

VCCPRIM_MPHY_1P05_4

BY12

VCCPRIM_MPHY_1P05_5

BY14

VCCPRIM_MPHY_1P05_6

BV2

VCCAMPHYPLL_1P05

BR15

VCCAPLL_1P05_2

CC12

VCCDUSB_1P05

BR24

VCCDSW_3P3_1

BT20

VCCHDA

BV23

VCCSPI

BT18

VCCPRIM_1P05_4

BT19

VCCPRIM_1P05_5

BU18

VCCPRIM_1P05_7

BU19

VCCPRIM_1P05_8

BT22

VCCPRIM_1P05_6

BP22

VCCPRIM_1P05_2

BV14

VCCPRIM_MPHY_1P05_2

WHL-U42_BGA1528

3

CPU POWER 4 OF 4

16 of 20

Compal Secret Data

Deciphered Date

VCCPRIM_3P3_3

VCCRTC

VCCPRIM_1P05_13

DCPRTC

VCCPRIM_1P05_3

VCCAPLL_1P05_3

VCCA_BCLK_1P05

VCCAPLL_1P05_1

VCCA_SRC_1P05

VCCA_XTAL_1P05

VCCDPHY_1P24_2 VCCDPHY_1P24_4

VCCDPHY_1P24_1 VCCDPHY_1P24_3 VCCDPHY_1P24_5

VCCDSW_3P3_2

VCCA_19P2_1P05

VCCPRIM_1P8_2 VCCPRIM_1P8_3 VCCPRIM_1P8_6 VCCPRIM_1P8_7 VCCPRIM_1P8_9

VCCPRIM_3P3_2

VCCPRIM_3P3_1

GPP_B0/CORE_VID0 GPP_B1/CORE_VID1

2

CB16

BR23

BY20 BP24

Intenal VRM

BR20

BT12

BP14

BR14

BU12

CP5

BY24 CA24

BY23 CA23 CP25

BT23

BR12

CC18 CC19 CD18 CD19 CP23

BW23

BP23

CB36 CB35

2

1 2

CC50 1U_0201_6.3V6M@

+3VALW_PCH

+1.05V_PRIM

Close to BP24

+1.05V_PRIM

+RTC_SOC

Close BR23

1

2

9

10 2

42

2

+1.05V_XTAL

61 0

+VCCLDOSRAM_1P24

VCCDPHY_1P24

Intenal VRM

27

19 9

PRIMCORE_VID0 PRIMCORE_VID1

+VCCLDOSRAM_1P24 VCCDPHY_1P24

Title

Size

B

Date : Sheet o f

Close to CP25

1 2

CNV@

LA-G717P

1

2

+3VALW_DSW

+1.05V_PRIM

+1.8V_PRIM

+3VALW_PCH

TP28 TP29

RC133 0_0402_5%

Compal Electronics, Inc.

CPU(9/12)Power

Document Number Re v

1

0.1U_0402_10V7K

1U_0201_6.3V6M

CC51

1

CC52

2

CC58

4.7U_0402_6.3V6M

+1.8V_PRIM

Close to CP23

1U_0201_6.3V6M

1

@

CC61

2

1.0

14 100Wednesday, June 19, 2019

1

5

smd.db-x7.ru

+VCC_CO RE

UC1L

AN9

VCCCORE5

AN10

VCCCORE1

AN24

VCCCORE2

AN26

VCCCORE3

AN27

VCCCORE4

AP2

VCCCORE6

AP9

VCCCORE9

AP24

VCCCORE7

D D

C C

AP26

AR5 AR6 AR7

AR8 AR10 AR25 AR27

AT9

AT24 AT26

AU5

AU6

AU7

AU8

AU9 AU24 AU25 AU26 AU27

AV2

AV5

AV7 AV10 AV27

AW5 AW6 AW7 AW8 AW9

AW10

BB9 BC24

AY9 BB24

WHL -U42_BGA1528

VCCCORE8 VCCCORE13 VCCCORE14 VCCCORE15 VCCCORE16 VCCCORE10 VCCCORE11 VCCCORE12 VCCCORE19 VCCCORE17 VCCCORE18 VCCCORE24 VCCCORE25 VCCCORE26 VCCCORE27 VCCCORE28 VCCCORE20 VCCCORE21 VCCCORE22 VCCCORE23 VCCCORE30 VCCCORE32 VCCCORE33 VCCCORE29 VCCCORE31 VCCCORE39 VCCCORE40 VCCCORE41 VCCCORE42 VCCCORE43 VCCCORE34

RSVD3 RSVD4 RSVD1 RSVD2

SVID ALERT

B B

VIDALERT#

SVID DATA

CPU POWER 1 OF 4

12 of 20

1 2

RC135 220_0402_5%

VCCCORE35 VCCCORE36 VCCCORE37 VCCCORE38 VCCCORE44 VCCCORE45 VCCCORE48 VCCCORE49 VCCCORE50 VCCCORE46 VCCCORE47 VCCCORE51 VCCCORE52 VCCCORE56 VCCCORE57 VCCCORE58 VCCCORE59 VCCCORE53 VCCCORE54 VCCCORE55 VCCCORE63 VCCCORE64 VCCCORE60 VCCCORE61 VCCCORE62 VCCCORE69 VCCCORE65 VCCCORE66 VCCCORE67 VCCCORE68 VCCCORE70 VCCCORE73 VCCCORE71 VCCCORE72 VCCCORE74

VCC_SENSE

VSS_SENSE

VIDALERT#

VIDSCK

VIDSOUT

RSVD5

VCCSTG1

+VCCST

12

RC134 56_0402 _5%

+VCCST

12

RC136 100_040 2_1%

AW24 AW25 AW26 AW27 AY24 AY26 BA5 BA7 BA8 BA25 BA27 BB2 BB26 BC5 BC6 BC7 BC9 BC10 BC26 BC27 BD5 BD8 BD10 BD25 BD27 BE9 BE24 BE25 BE26 BE27 BF2 BF9 BF24 BF26 BG27

AN6 AN5

AA3

AA1

AA2

Y3

BG3

4

+VCC_CO RE

VIDALERT#

VIDSOUT

+VCCSTG

VIDALERT_N <88>

+VCC_CORE

12

RC167 100_040 2_1%

VCCSENSE <88>

12

VIDSCLK < 88>

CAD Note: Place the PU resistors close to CPU close to CPU 3000mils

VSSSENSE <88>

Trace Leng th Match< 25 mils

RC168 100_040 2_1%

(To VR)

CAD Note: Place the PU resistors close to CPU close to CPU 3000mils

3

+VCC_CO RE

+VCC_GT

RSV for +VCC_OPC

UC1M

A5

VCCGT8

A6

VCCGT9

A8

VCCGT10

A11

VCCGT1

A12

VCCGT2

A14

VCCGT3

A15

VCCGT4

A17

VCCGT5

A18

VCCGT6

A20

VCCGT7

ES1/ES 2

AA9

VCCGT11/VCCCORE75

AB2

VCCGT13/VCCCORE76

AB8

VCCGT14/VCCCORE77

AB9

VCCGT15/VCCCORE78

AB10

VCCGT12/VCCCORE79

AC8

VCCGT16/VCCCORE80

AD9

VCCGT17/VCCCORE81

AE8

VCCGT19/VCCCORE82

AE9

VCCGT20/VCCCORE83

AE10

VCCGT18/VCCCORE84

AF2

VCCGT22/VCCCORE85

AF8

VCCGT23/VCCCORE86

AF10

VCCGT21/VCCCORE87

AG8

VCCGT24/VCCCORE88

AG9

VCCGT25/VCCCORE89

AH9

VCCGT26/VCCCORE90

AJ8

VCCGT28/VCCCORE91

AJ10

VCCGT27/VCCCORE92

AK2

VCCGT29//VCCCORE93

AK9

VCCGT30/VCCCORE94

AL8

VCCGT32/VCCCORE95

AL9

VCCGT33/VCCCORE96

AL10

VCCGT31/VCCCORE97

AM8

VCCGT34/VCCCORE98

V2

VCCGT115/VCCCORE99

Y10

VCCGT119/VCCCORE100

Y8

VCCGT120/VCCCORE101

B3

VCCGT39

B4

VCCGT40

B6

VCCGT41

B8

VCCGT42

B11

VCCGT35

B14

VCCGT36

B17

VCCGT37

B20

VCCGT38

C2

VCCGT49

C3

VCCGT51

C6

VCCGT52

C7

VCCGT53

C8

VCCGT54

C11

VCCGT43

C12

VCCGT44

C14

VCCGT45

C15

VCCGT46

C17

VCCGT47

C18

VCCGT48

C20

VCCGT50

D4

VCCGT62

D7

VCCGT63

D11

VCCGT55

D12

VCCGT56

D14

VCCGT57

WHL -U42_BGA1528

UC1O

K12

RSVD48

K14

RSVD49

K15

RSVD50

K17

RSVD51

K18

RSVD52

K20

RSVD53

L25

RSVD54

M24

RSVD55

M26

RSVD56

P24

RSVD57

P26

RSVD58

R24

RSVD59

R25

RSVD60

R26

RSVD61

2

31A70A

CPU POWER 2 OF 4

13 of 20

RESERVED SIGNALS

VCCGT_SENSE VSSGT_SENSE

RSVD38 RSVD39 RSVD40 RSVD41 RSVD42 RSVD43 RSVD44 RSVD45 RSVD46 RSVD47

VCCGT58 VCCGT59 VCCGT60 VCCGT61 VCCGT64 VCCGT69 VCCGT70 VCCGT71 VCCGT72 VCCGT65 VCCGT66 VCCGT67 VCCGT68 VCCGT73 VCCGT74 VCCGT75 VCCGT76 VCCGT77 VCCGT78 VCCGT79 VCCGT87 VCCGT88 VCCGT89 VCCGT90 VCCGT80 VCCGT81 VCCGT82 VCCGT83 VCCGT84 VCCGT85 VCCGT86 VCCGT95 VCCGT96 VCCGT91 VCCGT92 VCCGT93 VCCGT94 VCCGT98

VCCGT97 VCCGT100 VCCGT101

VCCGT99 VCCGT102 VCCGT104 VCCGT105 VCCGT106 VCCGT103 VCCGT107 VCCGT108 VCCGT109 VCCGT111 VCCGT112 VCCGT110 VCCGT114 VCCGT113

VCCGT116 VCCGT117 VCCGT118

AA24 AA26 AB25 AC24 AC25 AC26 AD24 AD26 V25 T25

+VCC_GT

D15 D17 D18 D20 E4 F5 F6 F7 F8 F11 F14 F17 F20 G11 G12 G14 G15 G17 G18 G20 H5 H6 H7 H8 H11 H12 H14 H15 H17 H18 H20 J7 J8 J11 J14 J17 J20 K2 K11 L7 L8 L10 M9 N7 N8 N9 N10 P2 P8 R9 T8 T9 T10 U8 U10

V9 W8 W9

E3 D2

12

RC170 100_040 2_1%

+VCC_GT

RSV for +VCC_EDRAM_EOPIO

1

12

RC169 100_040 2_1%

VCC_GT_SENSE < 88> VSS_GT_SENSE <88>

Trace Leng th Match< 25 mils

VIDSOUT

VIDSOUT <88>

(To VR)

A A

Security Classification

2019/06/ 19 2020/06/ 30

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

2019/06/ 19 2020/06/ 30

3

Compal Secret Data

Deciphered Date

W25

RSVD62

V24

RSVD63

Y25

RSVD64

Y24

RSVD65

WHL -U42_BGA1528

2

15 of 20

Compal Electronics, Inc.

Title

Size Document Number Re v

Date : Sheet o f

Compal Electronics, Inc.

CPU(10/12)POWER,SVID

LA-G717P

15 100W ednesday, June 19, 2019

1

1.0

5

smd.db-x7.ru

UC1R

CR34

BT5 BY5

CP35

CM37

CK37

AW1

D D

C C

B B

CM1 BD6

AY4 B34 E35

AE24 AE26

AF25 AG24 AG26 AH24 AH25

B36 C36

C37 CN1 CN2

CN37

CP2

A32

F33

BJ7

CJ36

A36

BK10

CJ4

AB27

BK2 CK1

AB3

BK28 AB30

BK3 CK4

AB33 BK33

CK7

AB36

BK4

CL2

AB4

BK7

CM13

AB7

BL25

CM17

AC10

BL28

CM21

AC27

BL29

CM25

AC30

BL30

CM29

BL31

CM31

AD33

BL32

CM33

AD35

A4

B2

D1

A3

GND 1 OF 3

VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72

WHL-U42_BGA1528

17 of 20

VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98

VSS_99 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144

BL7 AE25 BM33 CM5 AE27 BM35 CM9 AE30 BM36 CN13 AE7 BM9 CN17 AF27 BN30 CN21 AF3 BN7 CN25 AF30 CN29 AF33 BP15 AF36 AF4 CN5 AF7 BP25 CN9 AG10 BP3 CP1 BP32 CP11 AH27 BP33 CP13 AH28 BP4 CP15 AH29 BP7 CP19 AH30 CP21 AH31 BR19 CP27 AH33 BR25 AH35 CP37 AJ25 BT15 AJ28 BT16 CP9 AJ7 CR2 AK3 CR36 AK33 D21 AK36 BT25 D25 AK4 BT28 AL28 BT33 D5 AL29

4

UC1S

BT35

VSS_145

D6

VSS_146

AL32

VSS_147

BT36

VSS_148

D8

VSS_149

AL7

VSS_150

D9

VSS_151

AM10

VSS_152

BU11

VSS_153

E23

VSS_154

AM28

VSS_155

E27

VSS_156

AM33

VSS_157

BU23

VSS_158

E29

VSS_159

AM35

VSS_160

BU24

VSS_161

E31

VSS_162

BU25

VSS_163

E33

VSS_164

AN25

VSS_165

BU7

VSS_166

E9

VSS_167

AN28

VSS_168

BV11

VSS_169

F12

VSS_170

AN29

VSS_171

F15

VSS_172

AN30

VSS_173

F18

VSS_174

AN31

VSS_175

BV3

VSS_176

F2

VSS_177

AN7

VSS_178

BV31

VSS_179

F21

VSS_180

AN8

VSS_181

BV33

VSS_182

F24

VSS_183

BV4

VSS_184

F3

VSS_185

AP3

VSS_186

BW11

VSS_187

F4

VSS_188

AP33

VSS_189

BW15

VSS_190

G21

VSS_191

AP36

VSS_192

G27

VSS_193

AP4

VSS_194

G33

VSS_195

AR28

VSS_196

G35

VSS_197

G36

VSS_198

AT33

VSS_199

BW24

VSS_200

G9

VSS_201

AT35

VSS_202

H21

VSS_203

AT36

VSS_204

BW7

VSS_205

H27

VSS_206

AT4

VSS_207

BY11

VSS_208

AU10

VSS_209

BY15

VSS_210

H9

VSS_211

AU28

VSS_212

BY22

VSS_213

J12

VSS_214

AU29

VSS_215

J15

VSS_216

WHL-U42_BGA1528

GND 2 OF 3

18 of 20

VSS_217 VSS_218 VSS_219 VSS_220 VSS_221 VSS_222 VSS_223 VSS_224 VSS_225 VSS_226 VSS_227 VSS_228 VSS_229 VSS_230 VSS_231 VSS_232 VSS_233 VSS_234 VSS_235 VSS_236 VSS_237 VSS_238 VSS_239 VSS_240 VSS_241 VSS_242 VSS_243 VSS_244 VSS_245 VSS_246 VSS_247 VSS_248 VSS_249 VSS_250 VSS_251 VSS_252 VSS_253 VSS_254 VSS_255 VSS_256 VSS_257 VSS_258 VSS_259 VSS_260 VSS_261 VSS_262 VSS_263 VSS_264 VSS_265 VSS_266 VSS_267 VSS_268 VSS_269 VSS_270 VSS_271 VSS_272 VSS_273 VSS_274 VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286 VSS_287 VSS_288 VSS_289

BY25 J18 AU32 BY28 J21 AV25 BY33 J24 AV28 BY35 J33 AV3 BY36 J36 AV33 J6 AV36 C1 K21 AV4 C21 K22 AV6 C25 K24 AV8 C29 K25 AW28 C33 K27 AW29 C4 K28 AW3 C9 K29 AW30 CA11 K3 AW31 CA15 K30 AY33 CA22 K31 AY35 K32 B12 K4 B15 CA25 K9 B18 CB11 L27 B21 L33 B23 L35 B25 CB18 L36 B27 CB19 L6 B29 CB2 N25 B31 CB20 N27 CB25

3

N6

B37

CB3

P10

B5

CB33

P3 B7

CB4

P33

B9

CB7

P36 BA10 CC11

P4

BA28

P7

BA3 CC20

R27

BB3 CC25

R28 BB33 CC28

R29 BB36 CC31

R30

BB4

CC7

R31 BC25 CD11

T27

CD12

T30 BC29 CD14

T33

T35 BC32 CD24

T36 CD25

T7

BC8

CE33

U26 BD28 CE35

U7 BD33 CE36

V26

BD35

CE7

V27 BD36 CF11

V3 BE10 CF14

V30 BE28 CF19

V33 BE29

CF2

V36

BE3

2

UC1T

GND 3 OF 3

VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296 VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305 VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313 VSS_314 VSS_315 VSS_316 VSS_317 VSS_318 VSS_319 VSS_320 VSS_321 VSS_322 VSS_323 VSS_324 VSS_325 VSS_326 VSS_327 VSS_328 VSS_329 VSS_330 VSS_331 VSS_332 VSS_333 VSS_334 VSS_335 VSS_336 VSS_337 VSS_338 VSS_339 VSS_340 VSS_341 VSS_342 VSS_343 VSS_344 VSS_345 VSS_346 VSS_347 VSS_348 VSS_349 VSS_350 VSS_351 VSS_352 VSS_353 VSS_354 VSS_355 VSS_356 VSS_357 VSS_358 VSS_359 VSS_360 VSS_361

WHL-U42_BGA1528

19 of 20

VSS_362 VSS_363 VSS_364 VSS_365 VSS_366 VSS_367 VSS_368 VSS_369 VSS_370 VSS_371 VSS_372 VSS_373 VSS_374 VSS_375 VSS_376 VSS_377 VSS_378 VSS_379 VSS_380 VSS_381 VSS_382 VSS_383 VSS_384 VSS_385 VSS_386 VSS_387 VSS_388 VSS_389 VSS_390 VSS_391 VSS_392 VSS_393 VSS_394 VSS_395 VSS_396 VSS_397 VSS_398 VSS_399 VSS_400 VSS_401 VSS_402 VSS_403 VSS_404 VSS_405 VSS_406 VSS_407 VSS_408 VSS_409 VSS_410 VSS_411 VSS_412 VSS_413 VSS_414 VSS_415 VSS_416 VSS_417 VSS_418 VSS_419 VSS_420 VSS_421 VSS_422 VSS_423 VSS_424 VSS_425 VSS_426 VSS_427 VSS_428 VSS_429 VSS_430 VSS_431 VSS_432 VSS_433

CF23 V4 BE30 CF28 W10 BE31 CF3 W27 CF4 W30 BF3 CG33 W7 BF33 CG7 BF36 Y26 BF4 CH31 Y27 BG25 Y30 BG28 CJ11 Y33 CJ14 Y35 BH28 CJ19 Y7 BH29 CJ23 BH32 CJ28 BH33 CJ33 BH35 CJ35 BP19 BR16 BY18 BY19 CC16 BU16 CC14 BR22 BU20 CD20 BT14 BP12 CB24 CC24 J5 U24 BD7 AR4 AU4 AW4 BA6 BC4 BE4 BE8 BA4 BD4 BG4 CJ2 CJ3 AM5 CM4 AC5 AG5 CR6

1

A A

Security Classification

2019/06/19 2020/06/30

Issued Date

5

4

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2019/06/19 2020/06/30

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size

Document Number Re v

Date : Sheet o f

2

Date : Sheet o f

Compal Electronics, Inc.

CPU(11/12)GND

LA-G717P

16 100Wednesday, June 19, 2019

1

1.0

5

smd.db-x7.ru

4

3

2

1

Ref 575418

1 2

RC137 1K_0402_1%

D D

Reset sequence af t er PC U PLL i s l ocked

1 : (DEFAULT) Normal Operat i on; No St all

CFG0

0 : Stall

1 2

RC138 1K_0402_1%

PCI Express Stat i c La ne Revers al For All PE G Port s

1 : (DEFAULT) Normal Operat i on

CFG2

0 : Lane Reversal

1 2

C C

RC140

@

CFG0

CFG2

CFG4

1K_0402_1%

TPC11

CFG3<79>

TPC12

TPC13 TPC14 TPC15 TPC16 TPC17 TPC18 TPC19 TPC20

TPC21 TPC22 TPC23 TPC24

RC139 49.9_0402_1%

XDP_ITP_PMODE<79>

12

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15

CFG16 CFG18 CFG17 CFG19

CFG_RCOMP

Display Port Presence Strap

0 : Enabled; An external Display Port device is connected to the Embedded Display Port

CFG4

1 : Disabled; No Physical Display Port at t ached t o E mbedded Di spl ay Port

1 2

RC141 1K_0402_1%

1 2

RC142 1K_0402_1%

B B

PCI Express Bifurcat i on

— 00 = 1 x 8, 2 x4 PCI Expr ess *

CFG[6:5]

— 01 = r eser ved

— 10 = 2 x8 PCI Expr ess * — 11 = 1 x16 PCI Expr ess*

1 2

RC143 1K_0402_1%

CFG6

@

CFG5

@

CFG7

@

RC171

0_0201_5%

12

PEG Training

1 : (default) PEG Train immediately following RESET# de-assert i on.

CFG7

0 : PEG Wait for BIOS for training.

UC1Q

T4

CFG_0

R4

CFG_1

T3

CFG_2

R3

CFG_3

J4

CFG_4

M4

CFG_5

J3

CFG_6

M3

CFG_7

R2

CFG_8

N2

CFG_9

R1

CFG_10

N1

CFG_11

J2

CFG_12

L2

CFG_13

J1

CFG_14

L1

CFG_15

L3

CFG_16

N3

CFG_18

L4

CFG_17

N4

CFG_19

AB5

CFG_RCOMP

W4

ITP_PMODE

CG2

RSVD25

CG1

RSVD24

H4

RSVD34

H3

RSVD33

BV24

RSVD22

BV25

RSVD23

G3

RSVD66

G4

RSVD67

BK36

RSVD17

BK35

RSVD16

W3

RSVD35

AM4

RSVD7

AM3

RSVD6

A35

RSVD1

D34

RSVD30

G2

RSVD32

G1

RSVD31

WHL-U42_BGA1528

RESERVED SIGNALS

20 of 20

RSVD_TP5 RSVD_TP4

IST_TRIG

RSVD_TP3

RSVD15 RSVD14

TP_1 TP_2

RSVD21 RSVD20

RSVD18 RSVD19

RSVD29

RSVD26 RSVD27

VSS_434

RSVD12 RSVD13

RSVD8 RSVD9

RSVD11 RSVD10

RSVD72 RSVD73

RSVD74 RSVD75

TP_4 TP_3

RSVD68

RSVD_TP1 RSVD_TP2

RSVD28

RSVD36 RSVD37

SKTOCC#

F37 F34

IST_TRIG

CP36 CN36

BJ36 BJ34

BK34 BR18

BT9 BT8

BP8 BP9

CR4

CP3 CR3

BP36

AT3 AU3

AN1 AN2

AN4 AN3

AL2 AL1

AL4 AL3

BP34 BP35

C34

RC172 0_0201_5%

A34 B35

CR35

AH26 AJ27

E1

SKTOCC#

RC173 0_0201_5%

TP32

1 2

@

TP34

1 2

@

A A

Security Classification

Issued Date

5

4

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2019/06/19 2020/06/30

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size

Date : Sheet o f

2

Date : Sheet o f

Compal Electronics, Inc.

CPU(12/12)RSVD

Document Number Re v

CPU(12/12)RSVD

LA-G717P

1

17 100Wednesday, June 19, 2019

1.0

5

smd.db-x7.ru

4

3

2

1

+1.05V_PRIM TO +VCCST /+VCCSTG

Buffer with Open Drain Output For ALL_SYS_PWRGD

D D

1U_0201_6.3V6M

DZ5

1 2

RB751S40T1G_SOD523- 2

C C

SIO_SLP_S4#<10,78,86>

1 2

RZ1 0_0402_1%

+1.05V_PRIM TO +VCCIO

B B

1U_0201_6.3V6M

1

CZ9

@

2

VCCSTG_IO_EN

A A

@

1 2

RZ3 49.9K_0402_1%

1 2

DZ6

@

RB751S40T1G_SOD523- 2

+5VALW +1.05V_PRIM

CZ1

1.0V_VCCST_EN

1

2

+1.05V_PRIM

+5VALW

CZ10

1U_0201_6.3V6M

1

@

2

VCCSTG_IO_EN_R

1

2

1

CZ4

@

0.1U_0402_10V7K

2

0.1U_0402_10V7K CZ3

UZ2 @

1

VIN1

2

VIN2

7

VIN thermal

3

VBIAS

4

ON

TPS22961DNYR_WSON8

4.4mohm/6A TR=12.5us@Vin=1.05V

1

CZ11

@

0.1U_0402_10V7K

2

DZ4

new_0824C_test

1U_0201_6.3V6M

1

CZ2

2

UZ1

1 2

3

4

5

6 7

VOUT1

VIN1

VOUT1

VIN1

ON1

VBIAS

ON2

VIN2

VOUT2

VIN2

VOUT2

EM5209VF_DFN14_3X2

GPAD

GND

CT1

CT2

14 13

12

11

10

9 8

15

+VCCSTG_OUTVC CSTG_IO_EN

1 2

CZ6 1000P_0402_50V7K@

1 2

CZ7 1000P_0402_50V7K@

+VCCST_OUT

20moh m/6A

JP3 Always Open

JP3

VOUT

5

GND

Change UZ2 & relative component to "@" for DTC Change JP3 from "Always Short" to "Always Opent" for DTC

1

CZ12

0.1U_0402_10V7K

2

+VCCIO_OUT

6

112

JUMP_43X79

@

PJP@

Jason 2019-04-25

JP1,JP2 Always Short

JP1

PJP@

1 2

PAD-OPEN1x1m

1 2

CZ5 0.1U_0402_10V7K

JP2

1 2

PAD-OPEN1x1m

1

CZ8

0.1U_0402_10V7K

2

+VCCSTG

Change JP9 from "Always Open" to "Always Shortt" for DTC

2

+VCCIO

PJP@

+VCCSTG

+VCCST

JP9

PJP@

112

JUMP_43X79

1.2V_VTT_PWRGD<86>

190mA

20mA

JP9 Always Short

2

+VCCIO

Jason 2019-04-25

4.066A

ALL_SYS_PWRGD

0.1U_0402_10V7K CC77

@ESD@

2

1

SIO_SLP_S3#<10,78>

CPU_C10_GATE#<9>

SN74AHC1G08DCKR_SC7 0-5

SIO_SLP_S3#

RC147 0_ 0201_5%

1 2

RB751S40T1G_SOD523- 2

1 2

RC144

10K_0402_1%

Buffer with Open Drain Output For H_VCCST_PWRGD

0.1U_0402_16V7K

0.1U_0402_10V7K CC78

@ESD@

2

1

+3VS

12

RC146 10K_0402_5%

1 2

@

RZ2

0_0201_5%

1 2

+3VALW

5

1

P

IN1

2

IN2

UC9

G

3

@

0.1U_0402_16V7K

UC6

1

NC

2

12

CC68

1U_0402_6.3V6K

UC8

1

NC

2

A

3

GND

74AUP1G07GW_TSSOP5

1 2

RC148 0_ 0201_5%

4

O

UC9 change CPN & Description only

Jason 2019-04-26

A

3

GND

74AUP1G07GW_TSSOP5

CC70

12

VCC

Y

ALL_SYS_PWRGD

@

VCCSTG_IO_EN

5

4

+3VALW

CC67

12

5

VCC

ALL_SYS_PWRGD

4

Y

@

+VCCST+3VALW

12

RC145 100K_0402_5%

1

CC71

@

100P_0402_50V8J

2

ALL_SYS_PWRGD <58>

IMVP_VR_ON <88>

VCCSTG_IO_EN <78>

1

CC69 100P_0402_50V8J

2

H_VCCST_PWRGD <10>

Security Classification

Issued Date

5

4

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2019/06/19 2020/06/30

3

Compal Secret Data

Deciphered Date

Title

Size

Document Number Re v

B

Date : Sheet o f

2

Date : Sheet o f

Compal Electronics, Inc.

CPU PWR GATE

LA-G717P

18 100Wednesday, June 19, 2019

1

1.0

5

smd.db-x7.ru

4

3

2

1

Main Function:

D D

C C

Reserved

B B

A A

Security Classification

Issued Date

5

4

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2019/06/19 2020/06/30

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size

Date : Sheet o f

2

Date : Sheet o f

Compal Electronics, Inc.

Reserved

Document Number Re v

LA-G717P

19 100Wednesday, June 19, 2019

1

1.0

5

smd.db-x7.ru

4

3

2

1

Main Function:

D D

C C

Reserved

B B

A A

Security Classification

Issued Date

5

4

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2019/06/19 2020/06/30

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size

Date : Sheet o f

2

Date : Sheet o f

Compal Electronics, Inc.

Reserved

Document Number Re v

LA-G717P

20 100Wednesday, June 19, 2019

1

1.0

5

smd.db-x7.ru

4

3

2

1

Main Function:

D D

C C

Reserved

B B

A A

Security Classification

Issued Date

5

4

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2019/06/19 2020/06/30

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size

Date : Sheet o f

2

Date : Sheet o f

Compal Electronics, Inc.

Reserved

Document Number Re v

LA-G717P

21 100Wednesday, June 19, 2019

1

1.0

5

smd.db-x7.ru

4

3

2

1

Main Function:

D D

C C

Reserved

B B

A A

Security Classification

Issued Date

5

4

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2019/06/19 2020/06/30

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size

Date : Sheet o f

2

Date : Sheet o f

Compal Electronics, Inc.

Reserved

Document Number Re v

LA-G717P

22 100Wednesday, June 19, 2019

1

1.0

Main Func = DDR

smd.db-x7.ru

5

Layout Note: Place near JDIMM1.257,259

+2.5V_MEM

D D

Layout Note: Place near JDIMM1

10U_0402_6.3V6M

1U_0201_6.3V6M

1

CD2

CD1

2

+1.2V_DDR

1U_0201_6.3V6M

1

CD8

2

C C

1U_0201_6.3V6M

1

CD9

CD10

2

+1.2V_DDR

10U_0402_6.3V6M

1

CD16

2

B B

DIMM_CHA_SA0 DIMM_CHA_SA1 DIMM _CHA_SA2

+3VS +3VS +3VS

@

+V_DDR_REFA_R

A A

10U_0402_6.3V6M

1

CD17

CD18

2

12

RD2 0_0201_5%

12

RD3 0_0201_5%

20mil

1 2

RD11 2_0402_1%

1

CD27

0.022U_0402_25V7K

2

12

RD13

24.9_0402_1%

5

1

2

1U_0201_6.3V6M

1

CD12

CD11

2

10U_0402_6.3V6M

1

CD19

CD20

2

12

RD4

@

0_0201_5%

12

RD5

@

0_0201_5%

+1.2V_DDR

Layout Note: Place near JDIMM1.258

+0.6V_DDR_VTT

1U_0201_6.3V6M

1

2

1U_0201_6.3V6M

1

CD13

2

10U_0402_6.3V6M

1

CD21

2

12

RD10

1K_0402_1%~D

12

RD12

1K_0402_1%~D

CD3

+V_DDR_REFA

10U_0402_6.3V6M

1

CD4

2

1U_0201_6.3V6M

1

CD15

CD14

2

10U_0402_6.3V6M

1

CD23

CD22

2

12

RD6

@

0_0201_5%

12

RD7

@

0_0201_5%

CD5

1

@

+

CD24 330U_D2_2V_Y

2

4

Layout Note: Place near JDIMM1.255

DDR_DRAMRST#_R

4

DDR_A_D[0..63]<7> DDR_A_MA[0..13]<7> DDR_A_DQS#[0..7]<7> DDR_A_DQS[0..7]<7>

+3VS

0.1U_0402_16V7K~D

2.2U_0402_6.3V6M

CD6

CD7

1

2

DDR_A_CKE0<7>

DDR_A_BG1<7> DDR_A_BG0<7>

DDR_A_CLK0<7> DDR_A_CLK#0<7>

DDR_A_PAR<7> DDR_A_BA1<7>

DDR_A_CS#0<7>

DDR_A_WE#<7>

DDR_A_ODT0<7>

DDR_A_CS#1<7>

DDR_A_ODT1<7>

+1.2V_DDR

12

RD8 470_0402_1%

1 2

@

RD9 0_0201_5%

ESD@

1

CD26 10P_0201_50V8J

2

CD26 8/27 change to pop, for ESD request

+3VS

DDR_DRAMRST# <7>

3

+1.2V_DDR

DDR_A_D10

DDR_A_D13

DDR_A_DQS#1 DDR_A_DQS1

DDR_A_D15

DDR_A_D14

DDR_A_D3

DDR_A_D7

DDR_A_D5

DDR_A_D1

DDR_A_D16

DDR_A_D21

DDR_A_DQS#2 DDR_A_DQS2

DDR_A_D22

DDR_A_D19

DDR_A_D24

DDR_A_D28

DDR_A_D26

DDR_A_D30

DDR_A_CKE0

DDR_A_BG1 DDR_A_BG0

DDR_A_MA12 DDR_A_MA9

DDR_A_MA8 DDR_A_MA6

DDR_A_MA3 DDR_A_MA1

DDR_A_CLK0 DDR_A_CLK#0

DDR_A_PAR DDR_A_BA1

DDR_A_CS#0 DDR_A_WE#

DDR_A_ODT0 DDR_A_CS#1

DDR_A_ODT1

TP47

DDR_A_D36

DDR_A_D37

DDR_A_DQS#4 DDR_A_DQS4

DDR_A_D38

DDR_A_D39

DDR_A_D45

DDR_A_D41

+1.2V_DDR

PCH_SMBCLK<8,24,40,66> PCH_SMBDATA <8,24,40,66>

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

Issued Date

DDR_A_D44

DDR_A_D42

DDR_A_D48

DDR_A_D52

DDR_A_DQS#6 DDR_A_DQS6

DDR_A_D55

DDR_A_D50

DDR_A_D57

DDR_A_D60

DDR_A_D62

DDR_A_D63

PCH_SMBCLK

JDIMM1

CONN@

1

VSS1

3

DQ5

5

VSS3

7

DQ1

9

VSS5

11

DQS0_c

13

DQS0_t

15

VSS8

17

DQ7

19

VSS10

21

DQ3

23

VSS12

25

DQ13

27

VSS14

29

DQ9

31

VSS16

33

DM1_n/DBI _n

35

VSS17

37

DQ15

39

VSS19

41

DQ10

43

VSS21

45

DQ21

47

VSS23

49

DQ17

51

VSS25

53

DQS2_c

55

DQS2_t

57

VSS28

59

DQ23

61

VSS30

63

DQ19

65

VSS32

67

DQ29

69

VSS34

71

DQ25

73

VSS36

75

DM3_n/DBI 3_n

77

VSS37

79

DQ30

81

VSS39

83

DQ26

85

VSS41

87

CB5/NC

89

VSS43

91

CB1/NC

93

VSS45

95

DQS8_c

97

DQS8_t

99

VSS48

101

CB2/NC

103

VSS50

105

CB3/NC

107

VSS52

109

CKE0

111

VDD1

113

BG1

115

BG0

117

VDD3

119

A12

121

A9

123

VDD5

125

A8

127

A6

129

VDD7

131

A3

133

A1

135

VDD9

137

CK0_t

139

CK0_c

141

VDD11

143

PARITY

145

BA1

147

VDD13

149

CS0_n

151

WE_n/ A14

153

VDD15

155

ODT0

157

CS1_n

159

VDD17

161

ODT1

163

VDD19

165

C1, CS3_n ,NC

167

VSS53

169

DQ37

171

VSS55

173

DQ33

175

VSS57

177

DQS4_c

179

DQS4_t

181

VSS60

183

DQ38

185

VSS62

187

DQ34

189

VSS64

191

DQ44

193

VSS66

195

DQ40

197

VSS68

199

DM5_n/DBI 5_n

201

VSS69

203

DQ46

205

VSS71

207

DQ42

209

VSS73

211

DQ52

213

VSS75

215

DQ49

217

VSS77

219

DQS6_c

221

DQS6_t

223

VSS80

225

DQ55

227

VSS82

229

DQ51

231

VSS84

233

DQ61

235

VSS86

237

DQ56

239

VSS88

241

DM7_n/DBI 7_n

243

VSS89

245

DQ62

247

VSS91

249

DQ58

251

VSS93

253

SCL

255

VDDSPD

257

VPP1

259

VPP2

261

GND1

LOTES_ADDR0206-P001A02~D

DEREN_40-42271-26001RHF

SP07001CY0L

Compal Secret Data

2019/06/19 2020/06/30

Compal Secret Data

VSS2

VSS4

VSS6

DM0_n/DBI 0_n

VSS7

VSS9

VSS11

DQ12

VSS13

VSS15

DQS1_c

DQS1_t

VSS18

DQ14

VSS20

DQ11

VSS22

DQ20

VSS24

DQ16

VSS26

DM2_n/DBI 2_n

VSS27

DQ22

VSS29

DQ18

VSS31

DQ28

VSS33

DQ24

VSS35

DQS3_c

DQS3_t

VSS38

DQ31

VSS40

DQ27

VSS42

CB4/NC

VSS44

CB0/NC

VSS46

DM8_n/DBI _n/NC

VSS47

CB6/NC

VSS49

CB7/NC

VSS51

RESET_n

CKE1 VDD2

ACT_n

ALERT_n

VDD4

VDD6

VDD8

EVENT_n/NF

VDD10 CK1_t/NF CK1_c/NF

VDD12

A10/AP

VDD14

RAS_n/A1 6

VDD16

CAS_n/A1 5

VDD18

C0/CS2_n /NC

VREFCA

VSS54

DQ36

VSS56

DQ32

VSS58

DM4_n/DBI 4_n

VSS59

DQ39

VSS61

DQ35

VSS63

DQ45

VSS65

DQ41

VSS67

DQS5_c

DQS5_t

VSS70

DQ47

VSS72

DQ43

VSS74

DQ53

VSS76

DQ48

VSS78

DM6_n/DBI 6_n

VSS79

DQ54

VSS81

DQ50

VSS83

DQ60

VSS85

DQ57

VSS87

DQS7_c

DQS7_t

VSS90

DQ63

VSS92

DQ59

VSS94

GND2

Deciphered Date

2

+1.2V_DDR

2

DDR_A_D8

4

DQ4

6

DDR_A_D12

8

DQ0

10 12 14

DDR_A_D9

16

DQ6

18

DDR_A_D11

20

DQ2

22

DDR_A_D6

24 26

DDR_A_D2

28

DQ8

30

DDR_A_DQS#0

32

DDR_A_DQS0

34 36

DDR_A_D0

38 40

DDR_A_D4

42 44

DDR_A_D17

46 48

DDR_A_D20

50 52 54 56

DDR_A_D18

58 60

DDR_A_D23

62 64

DDR_A_D29

66 68

DDR_A_D25

70 72

DDR_A_DQS#3

74

DDR_A_DQS3

76 78

DDR_A_D31

80 82

DDR_A_D27

84 86 88 90 92 94 96 98 100 102 104 106

DDR_DRAMRST#_R

108

DDR_A_CKE1

110 112 114

DDR_A_ALERT#

116 118

DDR_A_MA11

120

A11

A7

A5 A4

A2

A0

BA0

A13

SA2

SDA SA0 VTT SA1

2

DDR_A_MA7

122 124

DDR_A_MA5

126

DDR_A_MA4

128 130

DDR_A_MA2

132 134 136

DDR_A_CLK1

138

DDR_A_CLK#1

140 142

DDR_A_MA0

144

DDR_A_MA10

146 148

DDR_A_BA0

150

DDR_A_RAS#

152 154

DDR_A_CAS#

156

DDR_A_MA13

158 160 162 164

DIMM_CHA_SA2

166 168

DDR_A_D33

170 172

DDR_A_D32

174 176 178 180

DDR_A_D34

182 184

DDR_A_D35

186 188

DDR_A_D43

190 192

DDR_A_D40

194 196

DDR_A_DQS#5

198

DDR_A_DQS5

200 202

DDR_A_D47

204 206

DDR_A_D46

208 210

DDR_A_D53

212 214

DDR_A_D49

216 218 220 222

DDR_A_D54

224 226

DDR_A_D51

228 230

DDR_A_D56

232 234

DDR_A_D61

236 238

DDR_A_DQS#7

240

DDR_A_DQS7

242 244

DDR_A_D59

246 248

DDR_A_D58

250 252

PCH_SMBDATA

254

DIMM_CHA_SA0

256 258

DIMM_CHA_SA1

260 262

DDR_DRAMRST#_R <24> DDR_A_CKE1 <7>

DDR_A_ACT# <7> DDR_A_ALERT# <7>

12

RD1

240_0402_1%

TP46

+1.2V_DDR

DDR_A_CLK1 <7> DDR_A_CLK#1 <7>

DDR_A_BA0 <7> DDR_A_RAS# <7>

DDR_A_CAS# <7>

+V_DDR_REFA

+1.2V_DDR

Title

Size Document Number Re v

Date: Sheet of

1

All VREF traces should have 10 mil trace width

0.1U_0402_16V7K~D

CD25

1

2

+0.6V_DDR_VTT+2.5V_MEM

Compal Electronics, Inc.

DDR4 DIMMA_RVS

LA-G717P

1

1.0

23 100Wednesday, June 19, 2019

1.0

5

smd.db-x7.ru

4

3

2

1

Main Func = DDR

DDR_B_D[0..63]<7> DDR_B_MA[0..13]<7>

Layout Note: Place near JDIMM2.257,259

+2.5V_MEM

D D

Layout Note: Place near JDIMM2

10U_0402_6.3V6M

1U_0201_6.3V6M

1

CD29

CD28

2

Layout Note: Place near JDIMM2.258

+0.6V_DDR_VTT

1U_0201_6.3V6M

1

CD30

2

10U_0402_6.3V6M

1U_0201_6.3V6M

1

CD31

2

CD32

DDR_B_DQS#[0..7]<7> DDR_B_DQS[0..7]<7>

Layout Note: Place near JDIMM2.255

+3VS

0.1U_0402_16V7K~D

2.2U_0402_6.3V6M

CD33

CD34

1

2

+1.2V_DDR

1U_0201_6.3V6M

1

CD35

2

C C

1U_0201_6.3V6M

1

CD36

CD37

2

1U_0201_6.3V6M

1

CD38

2

1U_0201_6.3V6M

1

CD39

CD40

2

+1.2V_DDR

10U_0402_6.3V6M

1

CD43

2

B B

DIMM_CHB_SA0 DI MM_CHB_SA1 DIMM_CHB_SA2

10U_0402_6.3V6M

1

CD44

2

+3VS +3VS +3VS

12

RD15

@

0_0201_5%

12

RD16

@

0_0201_5%

10U_0402_6.3V6M

1

CD45

CD46

2

10U_0402_6.3V6M

1

CD47

CD48

2

12

RD17

@

0_0201_5%

12

RD18

@

0_0201_5%

1U_0201_6.3V6M

1

CD42

CD41

2

DDR_B_CKE0<7>

DDR_B_BG1< 7> DDR_B_BG0< 7>

10U_0402_6.3V6M

1

CD49

CD50

2

12

RD19

@

0_0201_5%

12

RD20

@

0_0201_5%

DDR_B_CLK0<7> DDR_B_CLK#0<7>

DDR_B_PAR<7> DDR_B_BA1<7>

DDR_B_CS#0<7>

DDR_B_WE#<7>

DDR_B_ODT0<7>

DDR_B_CS#1<7>

DDR_B_ODT1<7>

DDR_B_CLK0 DDR_B_CLK#0

DDR_B_PAR DDR_B_BA1

DDR_B_CS#0 DDR_B_WE#

DDR_B_ODT0 DDR_B_CS#1

DDR_B_ODT1

TP49

+1.2V_DDR

+V_DDR_REFB_R

A A

20mil

1 2

RD22 2_0402_1%

1

CD52

0.022U_0402_25V7K

2

12

RD24

24.9_0402_1%

5

+1.2V_DDR

12

RD21

1K_0402_1%~D

+V_DDR_REFB

RD23

1K_0402_1%~D

+3VS

+2.5V_MEM

4

PCH_SMBCLK<8,23,40,66>

3

+1.2V_DDR

DDR_B_D12

DDR_B_D9

DDR_B_DQS#1 DDR_B_DQS1

DDR_B_D15

DDR_B_D10

DDR_B_D7

DDR_B_D2

DDR_B_D1

DDR_B_D6

DDR_B_D16

DDR_B_D21

DDR_B_DQS#2 DDR_B_DQS2

DDR_B_D23

DDR_B_D22

DDR_B_D29

DDR_B_D24

DDR_B_D26

DDR_B_D30

DDR_B_CKE0

DDR_B_BG1 DDR_B_BG0

DDR_B_MA12 DDR_B_MA9

DDR_B_MA8 DDR_B_MA6

DDR_B_MA3 DDR_B_MA1

DDR_B_D38

DDR_B_D33

DDR_B_DQS#4 DDR_B_DQS4

DDR_B_D34

DDR_B_D35

DDR_B_D40

DDR_B_D44

DDR_B_D47

DDR_B_D46

DDR_B_D49

DDR_B_D52

DDR_B_DQS#6 DDR_B_DQS6

DDR_B_D50

DDR_B_D51

DDR_B_D56

DDR_B_D61

DDR_B_D59

PCH_SMBCLK

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

JDIMM2

CONN@

1

VSS1

3

DQ5

5

VSS3

7

DQ1

9

VSS5

11

DQS0_c

13

DQS0_t

15

VSS8

17

DQ7

19

VSS10

21

DQ3

23

VSS12

25

DQ13

27

VSS14

29

DQ9

31

VSS16

33

DM1_n/DBI _n

35

VSS17

37

DQ15

39

VSS19

41

DQ10

43

VSS21

45

DQ21

47

VSS23

49

DQ17

51

VSS25

53

DQS2_c

55

DQS2_t

57

VSS28

59

DQ23

61

VSS30

63

DQ19

65

VSS32

67

DQ29

69

VSS34

71

DQ25

73

VSS36

75

DM3_n/DBI 3_n

77

VSS37

79

DQ30

81

VSS39

83

DQ26

85

VSS41

87

CB5/NC

89

VSS43

91

CB1/NC

93

VSS45

95

DQS8_c

97

DQS8_t

99

VSS48

101

CB2/NC

103

VSS50

105

CB3/NC

107

VSS52

109

CKE0

111

VDD1

113

BG1

115

BG0

117

VDD3

119

A12

121

A9

123

VDD5

125

A8

127

A6

129

VDD7

131

A3

133

A1

135

VDD9

137

CK0_t

139

CK0_c

141

VDD11

143

PARITY

145

BA1

147

VDD13

149

CS0_n

151

WE_n/ A14

153

VDD15

155

ODT0

157

CS1_n

159

VDD17

161

ODT1

163

VDD19

165

C1, CS3_n ,NC

167

VSS53

169

DQ37

171

VSS55

173

DQ33

175

VSS57

177

DQS4_c

179

DQS4_t

181

VSS60

183

DQ38

185

VSS62

187

DQ34

189

VSS64

191

DQ44

193

VSS66

195

DQ40

197

VSS68

199

DM5_n/DBI 5_n

201

VSS69

203

DQ46

205

VSS71

207

DQ42

209

VSS73

211

DQ52

213

VSS75

215

DQ49

217

VSS77

219

DQS6_c

221

DQS6_t

223

VSS80

225

DQ55

227

VSS82

229

DQ51

231

VSS84

233

DQ61

235

VSS86

237

DQ56

239

VSS88

241

DM7_n/DBI 7_n

243

VSS89

245

DQ62

247

VSS91

249

DQ58

251

VSS93

253

SCL

255

VDDSPD

257

VPP1

259

VPP2

261

GND1

LOTES_ADDR0205-P001A02~D

DEREN_40-42261-26001RHF

SP07001HW0L

2019/06/19 2020/06/30

DM0_n/DBI 0_n

DM2_n/DBI 2_n

DM8_n/DBI _n/NC

EVENT_n/NF

RAS_n/A1 6

CAS_n/A1 5

C0/CS2_n /NC

DM4_n/DBI 4_n

DM6_n/DBI 6_n

Compal Secret Data

VSS2

DQ4

VSS4

DQ0

VSS6

VSS7

DQ6

VSS9

DQ2

VSS11

DQ12

VSS13

DQ8

VSS15

DQS1_c

DQS1_t

VSS18

DQ14

VSS20

DQ11

VSS22

DQ20

VSS24

DQ16

VSS26

VSS27

DQ22

VSS29

DQ18

VSS31

DQ28

VSS33

DQ24

VSS35

DQS3_c

DQS3_t

VSS38

DQ31

VSS40

DQ27

VSS42

CB4/NC

VSS44

CB0/NC

VSS46

VSS47

CB6/NC

VSS49

CB7/NC

VSS51

RESET_n

CKE1 VDD2

ACT_n

ALERT_n

VDD4

A11

A7

VDD6

A5 A4

VDD8

A2

VDD10

CK1_t/NF

CK1_c/NF

VDD12

A0

A10/AP

VDD14

BA0

VDD16

A13

VDD18

VREFCA

SA2

VSS54

DQ36

VSS56

DQ32

VSS58

VSS59

DQ39

VSS61

DQ35

VSS63

DQ45

VSS65

DQ41

VSS67

DQS5_c

DQS5_t

VSS70

DQ47

VSS72

DQ43

VSS74

DQ53

VSS76

DQ48

VSS78

VSS79

DQ54

VSS81

DQ50

VSS83

DQ60

VSS85

DQ57

VSS87

DQS7_c

DQS7_t

VSS90

DQ63

VSS92

DQ59

VSS94

SDA SA0 VTT SA1

GND2

Deciphered Date

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 206 208 210 212 214 216 218 220 222 224 226 228 230 232 234 236 238 240 242 244 246 248 250 252 254 256 258 260 262

2

+1.2V_DDR

DDR_B_D13

DDR_B_D8

DDR_B_D14

DDR_B_D11

DDR_B_D3

DDR_B_D0

DDR_B_DQS#0 DDR_B_DQS0

DDR_B_D5

DDR_B_D4

DDR_B_D17

DDR_B_D20

DDR_B_D19

DDR_B_D18

DDR_B_D25

DDR_B_D28

DDR_B_DQS#3 DDR_B_DQS3

DDR_B_D31

DDR_B_D27

DDR_DRAMRST#_R DDR_B_CKE1

DDR_B_ALERT#

DDR_B_MA11 DDR_B_MA7

DDR_B_MA5 DDR_B_MA4

DDR_B_MA2

DDR_B_CLK1 DDR_B_CLK#1

DDR_B_MA0 DDR_B_MA10

DDR_B_BA0 DDR_B_RAS#

DDR_B_CAS# DDR_B_MA13

DIMM_CHB_SA2

DDR_B_D32

DDR_B_D39

DDR_B_D37

DDR_B_D36

DDR_B_D41

DDR_B_D45

DDR_B_DQS#5 DDR_B_DQS5

DDR_B_D42

DDR_B_D43

DDR_B_D48

DDR_B_D53

DDR_B_D55

DDR_B_D54

DDR_B_D57

DDR_B_D60

DDR_B_DQS#7 DDR_B_DQS7

DDR_B_D63

DDR_B_D62DDR_B_D58

PCH_SMBDATA

DIMM_CHB_SA0

DIMM_CHB_SA1

RD14

240_0402_1%

+1.2V_DDR

DDR_DRAMRST#_R <23> DDR_B_CKE1 <7>

DDR_B_ACT# <7> DDR_B_ALERT# <7>

12

+1.2V_DDR

DDR_B_CLK1 <7> DDR_B_CLK#1 <7>

DDR_B_BA0 <7> DDR_B_RAS# <7>

DDR_B_CAS# <7>

TP48

+V_DDR_REFB

0.1U_0402_16V7K~D

CD51

1

2

PCH_SMBDATA <8,23,40,66>

+0.6V_DDR_VTT

Compal Electronics, Inc.

Title

DDR4 DIMMB_STD

Size Document Number Re v

LA-G717P

Date: Sheet of

All VREF traces should have 10 mil trace width

1

1.0

24 100Wednesday, June 19, 2019

1.0

5

smd.db-x7.ru

D D

C C

4

3

2

1

Reserved

B B

A A

Security Classification

Issued Date

5

4

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2019/06/19 2020/06/30

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size

Date : Sheet o f

2

Date : Sheet o f

Compal Electronics, Inc.

Reserved

Document Number Re v

LA-G717P

25 100Wednesday, June 19, 2019

1

1.0

5

smd.db-x7.ru

4

3

2

1

Main Function:

D D

C C

Reserved

B B

A A

Security Classification

Issued Date

5

4

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2019/06/19 2020/06/30

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size

Date : Sheet o f

2

Date : Sheet o f

Compal Electronics, Inc.

Reserved

Document Number Re v

LA-G717P

26 100Wednesday, June 19, 2019

1

1.0

5

smd.db-x7.ru

4

3

2

1

Main Function:

D D

C C

Reserved

B B

A A

Security Classification

Issued Date

5

4

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2019/06/19 2020/06/30

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size

Date : Sheet o f

2

Date : Sheet o f

Compal Electronics, Inc.

Reserved

Document Number Re v

LA-G717P

27 100Wednesday, June 19, 2019

1

1.0

5

smd.db-x7.ru

4

3

2

1

Main Function:

D D

C C

Reserved

B B

A A

Security Classification

Issued Date

5

4

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2019/06/19 2020/06/30

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size

Date : Sheet o f

2

Date : Sheet o f

Compal Electronics, Inc.

Reserved

Document Number Re v

LA-G717P

28 100Wednesday, June 19, 2019

1

1.0

5

smd.db-x7.ru

4

3

2

1

Main Function:

D D

C C

Reserved

B B

A A

Security Classification

Issued Date

5

4

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2019/06/19 2020/06/30

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size

Date : Sheet o f

2

Date : Sheet o f

Compal Electronics, Inc.

Reserved

Document Number Re v

LA-G717P

29 100Wednesday, June 19, 2019

1

1.0

5

smd.db-x7.ru

4

3

2

1

Main Function:

D D

C C

Reserved

B B

A A

Security Classification

Issued Date

5

4

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2019/06/19 2020/06/30

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size

Date : Sheet o f

2

Date : Sheet o f

Compal Electronics, Inc.

Reserved

Document Number Re v

LA-G717P

30 100Wednesday, June 19, 2019

1

1.0

Compal LA-G716P Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual