Compal LA-G202P Schematic

A

1 1

B

C

D

E

Compal Confidential

DLID4 / D5

2 2

DIS M/B Schematic Document

Intel KabyLake U/KabyLake R Processor with DDR4

3 3

LA-G202P

2018-03-09

REV 1.0

4 4

Security Classification

Issued Date Decipherii ed Date

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIETARY PROPERTY OF COMPAL ELECTRONIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL AND
TRADE SECRET IIINFORMATIIION.. THIIS S HEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIVIIISIIION OF R&D DEPARTMENT
EXCEPT AS AUTHORIIZED BY COMPAL ELECTRONIIICS,,, IIINC.. NEIIITHER THIS SHEET NOR THE IIINFORMATIIION IIIT CONTAIIINS

A

B

MAY BE USED BY OR DIISCLOSED TO ANY THIIRD PARTY WIIITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS,,, IIINC.

C

2018/03/09 2019/03/09

Compal Secret Data

Tiiittllle

Siiize Documentt Number

Custttom

D

Compal Electronics,Inc.

Cover Page

LA-G202P

R ev

Sheett 1 off 55Date: Friiiday,,, March 09,,,2018

E

1...0

A

B

C

D

E

Memory Bus (Channel A)

NVIDIA MX110

(2GB GDDR5 VRAM)

1 1

(256 x 32 x 2 PCS)

PCIe X4 Gen3

*KBL-U: DDR4 (2133MHz, 1.2V)
*KBL-R: DDR4 (2400MHz, 1.2V)

Memory Bus (Channel B)

eDP Conn.

eDP X1 (2 Lanes)

PCIe X1 (1 Lanes)

USB 2.0 X1

HDMI Conn.

DDI X1 (4 Lanes)

Intel KabyLake-U

USB3.0 x1

Intel KabyLake-R

USB2.0 x1

2 2

RJ45 Conn.

LAN

RTL8106E-CG

PCIe X1 (1 Lane)

10/100

ODD Conn.

(14" -> On Mother Board)

SATA X1

(15" -> On Sub/B through FFC)

SOC

1356 PinBGA

USB3.0 x1

USB2.0 x1

USB2.0 x1

DDR4 (On Board) X4

DDR4 (SO DIMM) X1

WLAN / BT

Left USB3.0 x1

Left USB3.0 x1

Int. Camera

3 3

HDD Conn.

(On Sub/B through FFC)

SATA X1

USB2.0 x1

Card Reader

Realtek

SD Card Conn.

RTS5146-GR

Audio Codec

HDA

I2C x1

Touch Pad

Realtek
ALC3240

Int. Speaker Conn.

4 4

A

Audio Combo Jack

Headphone / Mic

B

SPI LPC

SPI ROM

8MB, 3.3V

LED

EC

ENE
KB9022QD

Int. KBD

Securiiity Clllassiiifiiicatiiion

Issued Date

THISII SHEET OF ENGINII EERINII G DRAWINII G ISII THE PROPRIEII TARY PROPERTY OF COMPAL ELECTRONICII S,,, INII C... AND CONTAINII S CONFIDII ENTIAII L AND TRADE
SECRET INII FORMATIONII ... THISII SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVII ISII IONII OF R&D DEPARTMENT EXCEPT AS
AUTHORIZEII D BY COMPAL ELECTRONICII S,,, INII C... NEITHII ER THISII SHEET NOR THE INII FORMATIONII ITII CONTAINIIS
MAY BE USED BY OR DISII CLOSED TO ANY THIRII D PARTY WITHIIOUT PRIORII WRITTEIIN CONSENTOF COMPALELECTRONICII S,,,INII C...

C

Hall Sensor

Compal SecretData

Decipherii ed Date

D

Tiiitttllle

Siiize DocumentttNumber

C

Compal Electronics, Inc.

Block Diagram

LA-G202P

Sheettt 2 o fff55Dattte::: Friiiday,,, March 09,,,2018

E

Rev

1...0

5

4

3

2

1

-PowerMap_KBL_DDR4_Volume_NON CS]

B+

D D

C C

B B

A A

Securiiirr tytt Classiiill fffiiicatiiitton

IIIssued Dattte

THISII SHEET OF ENGINEII ERINGII DRAWINGII ISIITHE PROPRIEII TARY PROPERTY OF COMPAL ELECTRONICII S,,, INCII ... AND CONTAINSII CONFIDII ENTIAII L AND TRADE SECRET INFII
ORMATION...II THISII SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVII ISII IONII OF R&D DEPARTMENT EXCEPT AS AUTHORIZEII D
BY COMPAL ELECTRONICII S,,, INCII ... NEITHEII R THISII SHEET NOR THE INFII ORMATIONII ITII CONTAINSII

5

4

3

MAY BE USED BY OR DISII CLOSED TO ANY THIRDII PARTY WITHOUTII PRIORII WRITTEII N CONSENT OF COMPAL ELECTRONICII S,,, INCII ...

2

2018/03/09////

Compalll SecretttDattta

Deciiipherrred Dattte

2019/03/09////

Compal Electronics,Inc.

Tiiitttllle

PowerMAP

Siiize Documenttt Numberrr

LA-C071P

Dattte::: Frrriiiday,,,Marrrch09,,, 2018 Sheettt 4 o fff 55

1

Rev

1...0

5

4

3

2

1

G3->S0

+3VL_RTC

SOC_RTCRST#

B+

D D

+3VLP/+ 5VLP

EC_ON

+5VALW/+ 3VALW /+3V ALW_D SW

PM_BATLOW #

tPCH01_Min : 9 ms

tPCH04_Min : 9 ms

Pull-up to D SW well if not implemented.

S0->S3/DS3 S0/DS3->S0

PCH_PWR _EN (SLP_SUS#)

+3V_PRIM

+1.8V_PRIM

EXT_PWR_GATE#

+1.0V_M PHYPLL

+1.0V_PRIM_CORE

+1.0V_PRIM

tPCH06_Min : 200 us

SUSACK#

PCH_DPW ROK

EC_RSMRST#

C C

AC_PRESENT

tPCH34_Max : 20 ms

tPCH02_Min : 10 ms

tPCH03_Min : 10 ms

tPLT02_Min : 0 ms Max : 90 ms

ON/OFF

PBTN_OUT#

Minim um duration of PWRBTN# assertion = 16m S. PW RBTN# can assert before or after RSM RST#

PM_SLP_S 5#

ESPI_RST #

If EXT_PWR _GATE# Toffmin is too small, Pwr
gate may choose to completely ignore it

tPCH43_Min : 95 ms

tPCH18_Min : 90 us

PM_SLP_S 4#

SYSON

+1.0V_VCCST/+1 .0V_VCCSFR

+1.35V_ VDDQ/+1. 35V_VC CSFR_OC

PM_SLP_S 3#

SUSP#

+1.0VS_VCCSTG

+1.0VS_VCCIO

B B

+5VS/+3 VS/+1.5VS/+1. 05VS

EC_VCCST_PG

VR_ON

SM_PG_ CTRL

+0.675V S_VTT

+VCC_SA

tCPU04 Min : 100 ns

tCPU10 Min : 1 ms

T <=10msec

T = 10msec

tCPU19 Max : 100 ns

tCPU18 Max : 35 us

tCPU09 Min : 1 ms

+VCC_CORE

+VCC_GT

VR_PWRG D

PCH_PWR OK

tCPU16 Min : 0 ns

H_CPUPW RGD

SYS_PWR OK

A A

SUS_STAT#

SOC_PLT RST#

S0->S5

+3VL_RTC

SOC_RTCRST#

B+

+3VLP/+ 5VLP

EC_ON

+5VALW/+ 3VALW /+3V ALW_D SW

PM_BATLOW #

PCH_PWR _EN (SLP_SUS#)

+3V_PRIM

+1.8V_PRIM

EXT_PWR_GATE#

+1.0V_M PHYPLL

+1.0V_PRIM_CORE

+1.0V_PRIM

SUSACK#

PCH_DPW ROK

EC_RSMRST#

AC_PRESENT

ON/OFF

PBTN_OUT#

PM_SLP_S 5#

ESPI_RST #

PM_SLP_S 4#

SYSON

+1.0V_VCCST/+1 .0V_VCCSFR

+1.35V_ VDDQ/+1. 35V_VC CSFR_OC

PM_SLP_S 3#

SUSP#

+1.0VS_VCCSTG

+1.0VS_VCCIO

+5VS/+3 VS/+1.5VS/+1. 05VS

EC_VCCST_PG

VR_ON

SM_PG_ CTRL

+0.675V S_VTT

+VCC_SA

+VCC_CORE

+VCC_GT

VR_PWRG D

PCH_PWR OK

H_CPUPW RGD

SYS_PWR OK

SUS_STAT#

SOC_PLT RST#

Securiiittty Clllassiiifffiiicatttiiion Compalll Secret Data

IsII suedDatett

THISII SHEET OF ENGINEERINGIIII DRAWINGII ISII THE PROPRIETII ARY PROPERTY OF COMPAL ELECTRONICS,,,II INC...II AND CONTAINSII CONFIDENTII IALII AND TRADE
SECRET INFII ORMATION...II THISII SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISIONIIIIII OF R&D DEPARTMENT EXCEPT AS
AUTHORIZIIED BY COMPAL ELECTRONICS,,,II INC...II NEITII HER THISII SHEET NOR THE INFII ORMATIONII ITIICONTAINSII

5

4

3

MAY BE USED BY OR DISCLII OSED TO ANY THIRDII PARTY WITII HOUT PRIORII WRITII TEN CONSENT OF COMPAL ELECTRONICS,,,IIINC...II

2018///03///09

2

Deciiiphererr d Dattte

2019///03///09

Tiiitttllle

Siiize DocumentttNumberrr

1

Compal Electronics,Inc.

PowerSequence

Sheettt5 o fff55Dattte::: Frrriiiday,,, Marrrch 09,,,2018

Re v

1...0

1

Voltage Rails

power
plane

+5VALW

B+

A A

State

S0

S3

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery
don't exist

B B

+3VALW

O O O O

O O O

O O

O

X X X

X X X X

+1.2V

X X

+5VS

+3VS
+1.35VS

+VCC_CORE
+VGA_CORE

+VCC_GFXCORE_AXG

+1.8VS

+0.6VS

+1.0VALW

X

EC SM Bus1 address EC SM Bus2 address

Device

Smart Battery

PCH SM Bus address GPU SM Bus address

Device

DDR_J DIMM 1
Touch Pad

Address

0001 011x 16h

Address Device Address

1010 000x A0h Internal thermal sensor 1001 111x 9Eh

Device

NCT7718W

Address

1001 100x 98h

2

BOM Structure Table

Item

DIS Only Components DIS@
UMA Only Components UMA@
14" Only Components 14@
15" Only Components 15@
HDMI Logo 45@
GIGA LAN Reserved Items 8111GLDO@
Memory Down - SDP Package SDP@
Memory Down - DDP Package DDP@
GPU GC6 Components GC6@
Un-Mount GPU GC6 Components NOGC6@

GPU

EMI Category EMI@
ESD Category ESD@
RF Category RF@
EMI Un-Mount Items @EMI@
ESD Un-Mount Items @ESD@
RF Un-Mount Items @RF@
Connectors ME@
Test Point TP@
Intel Debug Components @DCI@
Un-Mount Components @
CPU Components - U22 Only U22@
CPU Components - U42 Only U42@
EMI U22 Components U22_EMI@
EMI U42 Components U42_EMI@

CPU

BOM Structure

N16S_R1@
N16S_R3@
N16V_R1@
N16V_R3@

i3_7020U_R1@
i5_8250U_R1@
i5_8250U_R3@
i7_8550U_R1@
i7_8550U_R3@
i3_8130U_R1@

3

Item

X4E

On Board RAM (Hynix 4GB) H4G_MD@
On Board RAM (Micron 4GB) M4G_MD@
On Board RAM (Samsung 4GB) S4G_MD@
On Board RAM X76 Resistors X76RAM@
Realtek Card Reader RTK_CR@
Genesys Card Reader GNS_CR@

VRAM (Hynix 2GB)

VRAM (Hynix 4GB)

VRAM (Micron 2GB)

VRAM (Micron 4GB)

VRAM (Samsung 2GB)

VRAM (Samsung 4GB)

BOM Structure

X4E_U22_14@
X4E_U22_15@
X4E_U42_14@
X4E_U42_15@

H2G_VRAM@
H2G@
H2G_R1@
H2G_R3@

H4G_VRAM@
H4G@
H4G_R1@
H4G_R3@
M2G_VRAM@
M2G@
M2G_R1@
M2G_R3@
M4G_VRAM@
M4G@
M4G_R1@
M4G_R3@
S2G_VRAM@
S2G@
S2G_R1@
S2G_R3@
S4G_VRAM@
S4G@
S4G_R1@
S4G_R3@

X4E

U42

ZZZ X4E_U42@

U22

ZZZ X4E_U22@

4

USB 2.0 Port Table

Port External USB Port

1
2

USB2/3 Port (MB-1)

3

USB2/3 Port (MB-2)

4
5

Camera

6

Card Reader

7

NGFF WLAN+BT

USB 3.0 Port Table

Port

1
2

USB2/3 Port (MB-1)

3

USB2/3 Port (MB-2)

4
5 1
6 2

SATA Port Table

Port

0

HDD

1

ODD

ON BOARD RAM * 4

ZZZ S4G_MD@ ZZZ M4G_MD@ ZZZ H4G_MD@

X76 SAMSUNG 4GB MD X76 MICRON 4GB MD X76 HYNIX 4GB MD

X7677538L13 X7677538L14 X7677538L15

5

PCIE Port Table

Lane Port

1

3
4
5

6
7
8

9
10
11
12

GPU

LAN
NGFF WLAN+BT

HDMI Logo

ZZZ 45@

HDMI Logo

RO0000003HM

X4E U42

SMBUS Control Table

X

+V3VS

X X

Thermal

DGPU

Sensor

X X

+V3VS

X X X

+V3VS

2

TP PCH

X

X X

X

X+V

X

X X

X

+V3VS

X X

+V3VS

X

X X

X

*N16V -MX110

*N16S - MX130

GPU

UV1 N16S_R1@ UV1 N16V_R1@

N16S-GTR-S-A2 BGA 595P N16V-GMR1-S-A2 BG A 595P

SA00009FP00 SA00009IT00

UV1 N16S_R3@ UV1 N16V_R3@

N16S-GTR-S-A2 BGA 595P N16V-GMR1-S-A2 BG A 595P

SA00009FP30 SA00009IT30

SOURCE VGA BATT CHARGER NECP388 SODIM M

C C

D D

SMB_EC_CK1

SMB_EC_DA1
SMB_EC_CK2

SMB_EC_DA2
SMB_EC_CK4
SMB_EC_DA4

PCH_SMBCLK
PCH_SMBDATA

SML0CLK

SML0DATA
SML1CLK

SML1DATA

STATE

Full ON HIGH HIGH HIGH HIGH ON ON ON ON

S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW

S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF

S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF

S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OF F

NECP388

+3VALW

NECP388

+3VVGS

+3VS

NECP388

+3VALW

PCH

+3VALW

PCH

+3VALW

PCH

+3VALW

SIGNAL

SLP_S1# SLP_S3# SL P_S4# SLP_S5# +VALW +V +VS Clock

1

V

X

+3VALW

+19VV_VIN

X X

X X X X X

+V3VS

X X X X X X X X

X X X X

X X X X X X X X

X X X

+V3VS

3VS

X

G­SENSOR

X

X

+V3VS

X
X

X

Device ID:0x174E

(

Device ID: 0x174D

(

)

CPU

)

KBL U22 (= U22@) KBL U42 (= U42@)

UC1 i3_7020U_R1@ UC1i5 _8250U_R1@ UC1i7_8550U_R1@ UC1 i3_8130U_R1@

QNZU H02.3G

SA0000BLH10

UC1 i3_7020U_U22@ UC1i5 _8250U_R3@ UC1i7_8550U_R3@ UC1 i3_8130U_R3@ UC1 i3_7020U_U42@

SR3TK H02.3G

SA0000BLH50

3

X4EABQ38L01

GDDR5 VRAM * 2

Securiiity Clllassiiifiiicatiiion

Issued Date

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL AND
TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIIIVIIISIIION OF R&D DEPARTMENT
EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IIINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIIT CONTAIIINS
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,,IIINC...

X4E U22

X4EABQ38L02

CARD READER

*Main Source - Realtek
*Substitute - Genesys

2GB

ZZZ H2G_VRAM@

X76 H YNIX 2GB

X7677538L06

2018/03/09 2019/03/09

ZZZ M2G_VRAM@

X76 MICRO N2GB

X7677538L05

Compalll Secret Data

Deciiiphered Date

4

ZZZ S2G_VRAM@

X76 SAMSUNG 2GB

X7677538L04

SR3LA Y0 1.6G FCBGA

SA0000AWB20

SR3LA Y0 1.6G FCBGA

SA0000AWB50

SR3LC Y0 1.8G FCBGA

SA0000AWC20

SR3LC Y0 1.8G FCBGA

SA0000AWC50

QP8K Y02.2G

SA0000BKN20

SR3W 0 Y02.2G

SA0000BKN30

Compal Electronics, Inc.

Tiiitttllle

NotesList

Siiize DocumentttNumberrr

Custttom

Dattte:::

PCB

ZZZ 14_DAZ@

PCB

DAZ29900201

ZZZ 15_DAZ@

PCB

DAZ29A00201

SR3LD Y02.3G

SA0000BLD60

LA-G202P

5

R e v

Sheettt 3 o fff55Frrriiiday,,, Marrrch 09,,, 2018

1...0

A

1 1

<HDMI>

HDMI DDC (Port C)

2 2

B

<29> HDMI_TX2-_CK
<29> HDMI_TX2+_CK
<29> HDMI_TX1-_CK
<29> HDMI_TX1+_CK
<29> HDMI_TX0-_CK
<29> HDMI_TX0+_CK
<29> HDMI_CLK-_CK
<29> HDMI_CLK+_CK

<29> HDMICLK_NB
<29> HDMIDAT_NB

EDP_COMP

C

DDI

DISPLAY SIDEBANDS

SKL-U

1 OF20

EDP

GPP_E13/DDPB_HPD0
GPP_E14/DDPC_HPD1
GPP_E15/DDPD_HPD2
GPP_E16/DDPE_HPD3

GPP_E17/EDP_HPD

UC1A

E55

DDI1_TXN[0]

F55

DDI1_TXP[0]

E58

DDI1_TXN[1]

F58

DDI1_TXP[1]

F53

DDI1_TXN[2]

G53

DDI1_TXP[2]

F56

DDI1_TXN[3]

G56

DDI1_TXP[3]

C50

DDI2_TXN[0]

D50

DDI2_TXP[0]

C52

DDI2_TXN[1]

D52

DDI2_TXP[1]

A50

DDI2_TXN[2]

B50

DDI2_TXP[2]

D51

DDI2_TXN[3]

C51

DDI2_TXP[3]

L13

GPP_E18/DDPB_CTRLCLK

L12

GPP_E19/DDPB_CTRLDAT A

N7

GPP_E20/DDPC_CTRLCLK

N8

GPP_E21/DDPC_CTRLDAT A

N11

GPP_E22

N12

GPP_E23

E52

EDP_RCOMP

SKL-U_BGA1356 @

Rev_1.0

EDP_TXN[0]
EDP_TXP[0]
EDP_TXN[1]
EDP_TXP[1]
EDP_TXN[2]
EDP_TXP[2]
EDP_TXN[3]
EDP_TXP[3]

EDP_AUXN
EDP_AUXP

EDP_DISP_ UTIL

DDI1_AUXN
DDI1_AUXP
DDI2_AUXN
DDI2_AUXP

RSVD
RSVD

EDP_BKLT EN

EDP_BKLT CTL

EDP_VDDEN

B45
B47

G46

L6

R11
U13

D

C47
C46
D46
C45

A45

A47

E45
F45

B52
G50

F50
E48

F48

F46

L9

L7
N9

L10

R12

EDP_TXN0 <28>
EDP_TXP0 <28>
EDP_TXN1 <28>
EDP_TXP1 <28>

EDP_AUXN <28>
EDP_AUXP <28>

TMDS_B_HPD <29>
EC_SCI# <10,36>

EDP_HPD <28>

ENBKL <36>
INVPWM <28>
PCH_ENVDD <28>

<eDP>

From HDMI

From eD P

E

< Compensation PU For eDP >

+1.0VS_VCCIO

EDP_COMP

2

1

1 2

24.9_0402_1%

H_THERMTRIP#

<36> H_PROCHOT#

+1.0VS_VCCIO

12

If routedMS, PECIrequires 18 milsspacingto other signals

RC4
1K_0402_5%

1 2

RC6

RC7 2
RC8 2 1 49.9_040 2_1%
RC9 2@1 49.9_0402_1%
RC10 2 @

<36> H_PECI

499_0402_1%

1

49.9_0402_1%

1 49.9_0402_1%

T99 TP@

T100 TP@

T103 T P@
T105 T P@
T107 T P@
T109 TP@

EDRAM_OPIO_RCOMP

SOC_CATERR#
H_PECI
H_PROCHOT#_R
H_THERMTRIP#
SOC_OCC#

XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3

CPU_POPIRCOMP
PCH_OPIRCOMP

EOPIO_RCOMP

PCH_OPIRCOMP

H66

UC1D

D63

CATERR#

A54

PECI

C65

PROCHOT#

C63

THERMT RIP#

A65

SKTOCC#

C55

BPM#[0]

D55

BPM#[1]

B54

BPM#[2]

C56

BPM#[3]

A6

GPP_E3/CPU_GP0

A7

GPP_E7/CPU_GP1

BA5

GPP_B3/CPU_GP2

AY5

GPP_B4/CPU_GP3

AT16

PROC_POPIRCOMP

AU16

OPCE_RCOMP

H65

OPC_RCOMP

SKL-U_BGA1356 @

SKL-U

CPUMISC

4 OF20

JTAG

PROC_T CK

PROC_T DI
PROC_T DO
PROC_T MS

PROC_T RST#

PCH_JT AG_TCK

PCH_JT AG_TDI
PCH_JT AG_TDO
PCH_JT AG_TMS

PCH_TRST#

Rev_1.0

JTAGX

D60
A61
C60
B59

D59
A56
C59
C61
A59

B61

B56

CPU_XDP_TCK0
SOC_XDP_TDI
SOC_XDP_TDO
SOC_XDP_TMS
SOC_XDP_TRST#

PCH_JTAG_TCK1
SOC_XDP_TDI
SOC_XDP_TDO
SOC_XDP_TMS
SOC_XDP_TRST#
CPU_XDP_TCK0

T116 TP@

< PU/PD for CMC Debug >

SOC_XDP_TMS
SOC_XDP_TDI
SOC_XDP_TDO

CPU_XDP_TCK0
PCH_JTAG_TCK1

SOC_XDP_TRST#

RC12 1 @
RC13 1 @DCI@

RC14 1 @DCI@ 2

RC15 1@

RC23 1@

+1.0VS_VCCIO

2

51_0402_5%

@RC11 1

2

51_0402_5%

2

51_0402_5%

51_0402_5%

2

51_0402_5%

2

51_0402_5%

RC3

Trace width=20 mils, Spacing=25mil, Maxlength=100mils

+1.0V_VCCST

RC5 1K_0402_5%

3 3

4 4

SecuriiityClllassiiifiiicatiiion

Issued Date Decipii hered Date

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL AND
TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT B E TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIIONOF R&D
DEPARTMENT EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IIINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIITCONTAIIINS

A

B

MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IIINC...

C

2018/03/09 2019/03/09

Compal Secret Data

Tiiitllle

Siiize Document Number

D

Compal Electronics,Inc.

SKL-U(1/12)DDI,EDP,MISC,CMC

Custttom

LA-G202P

E

R ev

Sheet 6 o f 55Date: Friiiday,,, March 09,,,2018

1...0

5 4 3 2 1

Interleaved Memory

@

AU53
AT53
AU55
AT55

BA56
BB56
AW 56
AY56

AU45
AU43
AT45
AT43

BA51
BB54
BA52
AY52
AW 52
AY55
AW 54
BA54
BA55
AY54
AU46
AU48
AT46
AU50
AU52
AY51
AT48
AT50
BB50
AY50

BA50
BB52
AM70
AM69
AT69
AT70

BA64
AY64
AY60
BA60
BA38
AY38
AY34
BA34
BA30
AY30
AY26
BA26

AW 50
AT52

AY67
AY68
BA67

AW 67

DDR_A_CLK0

DDR_A_CLK#0

DDR_A_CLK0

DDR_A_CLK#1
DDR_A_CLK1

DDR_A_CKE0
DDR_A_CKE1

DDR_A_CS#0

DDR_A_CS#1
DDR_A_ODT0
DDR_A_ODT1

DDR_A_MA5
DDR_A_MA9
DDR_A_MA6
DDR_A_MA8

DDR_A_MA7

DDR_A_BG0

DDR_A_MA12
DDR_A_MA11
M_A_ACT#
DDR_A_BG1
DDR_A_MA13
DDR_A_MA15
DDR_A_MA14
DDR_A_MA16
DDR_A_BA0
DDR_A_MA2
DDR_A_BA1
DDR_A_MA10
DDR_A_MA1
DDR_A_MA0

DDR_A_MA3
DDR_A_MA4
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_DQS#1
DDR_A_DQS1

DDR_A_DQS#2
DDR_A_DQS2
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_DQS#7
DDR_A_DQS7

DDR_A_ALERT#
DDR_A_PARITY

+0.6V_A_VREFCA

+0.6V_B_VREFDQ

DDR_PG_CTRL

D D

<18> DDR_A_D[0..15]

<18> DDR_A_D[16..31]

C C

<18> DDR_A_D[32..47]

<18> DDR_A_D[48..63]

B B

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8

DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15

DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

UC1B

AL71

DDR0_DQ[0]

AL68

DDR0_DQ[1]

AN68

DDR0_DQ[2]

AN69

DDR0_DQ[3]

AL70

DDR0_DQ[4]

AL69

DDR0_DQ[5]

AN70

DDR0_DQ[6]

AN71

DDR0_DQ[7]

AR70

DDR0_DQ[8]

AR68

DDR0_DQ[9]

AU71

DDR0_DQ[10]

AU68

DDR0_DQ[11]

AR71

DDR0_DQ[12]

AR69

DDR0_DQ[13]

AU70

DDR0_DQ[14]

AU69

DDR0_DQ[15]

Interleave / Non-Interleaved

BB65

DDR0_DQ[16]/DDR0_DQ[32]

AW 65

DDR0_DQ[17]/DDR0_DQ[33]

AW 63

DDR0_DQ[18]/DDR0_DQ[34]

AY63

DDR0_DQ[19]/DDR0_DQ[35]

BA65

DDR0_DQ[20]/DDR0_DQ[36]

AY65

DDR0_DQ[21]/DDR0_DQ[37]

BA63

DDR0_DQ[22]/DDR0_DQ[38]

BB63

DDR0_DQ[23]/DDR0_DQ[39]

BA61

DDR0_DQ[24]/DDR0_DQ[40]

AW 61

DDR0_DQ[25]/DDR0_DQ[41]

BB59

DDR0_DQ[26]/DDR0_DQ[42]

AW 59

DDR0_DQ[27]/DDR0_DQ[43]

BB61

DDR0_DQ[28]/DDR0_DQ[44]

AY61

DDR0_DQ[29]/DDR0_DQ[45]

BA59

DDR0_DQ[30]/DDR0_DQ[46]

AY59

DDR0_DQ[31]/DDR0_DQ[47]

AY39

DDR0_DQ[32]/DDR1_DQ[0]

AW 39

DDR0_DQ[33]/DDR1_DQ[1]

AY37

DDR0_DQ[34]/DDR1_DQ[2]

AW 37

DDR0_DQ[35]/DDR1_DQ[3]

BB39

DDR0_DQ[36]/DDR1_DQ[4]

BA39

DDR0_DQ[37]/DDR1_DQ[5]

BA37

DDR0_DQ[38]/DDR1_DQ[6]

BB37

DDR0_DQ[39]/DDR1_DQ[7]

AY35

DDR0_DQ[40]/DDR1_DQ[8]

AW 35

DDR0_DQ[41]/DDR1_DQ[9]

AY33

DDR0_DQ[42]/DDR1_DQ[10]

AW 33

DDR0_DQ[43]/DDR1_DQ[11]

BB35

DDR0_DQ[44]/DDR1_DQ[12]

BA35

DDR0_DQ[45]/DDR1_DQ[13]

BA33

DDR0_DQ[46]/DDR1_DQ[14]

BB33

DDR0_DQ[47]/DDR1_DQ[15]

AY31

DDR0_DQ[48]/DDR1_DQ[32]

AW 31

DDR0_DQ[49]/DDR1_DQ[33]

AY29

DDR0_DQ[50]/DDR1_DQ[34]

AW 29

DDR0_DQ[51]/DDR1_DQ[35]

BB31

DDR0_DQ[52]/DDR1_DQ[36]

BA31

DDR0_DQ[53]/DDR1_DQ[37]

BA29

DDR0_DQ[54]/DDR1_DQ[38]

BB29

DDR0_DQ[55]/DDR1_DQ[39]

AY27

DDR0_DQ[56]/DDR1_DQ[40]

AW 27

DDR0_DQ[57]/DDR1_DQ[41]

AY25

DDR0_DQ[58]/DDR1_DQ[42]

AW 25

DDR0_DQ[59]/DDR1_DQ[43]

BB27

DDR0_DQ[60]/DDR1_DQ[44]

BA27

DDR0_DQ[61]/DDR1_DQ[45]

BA25
BB25

DDR0_DQ[62]/DDR1_DQ[46]
DDR0_DQ[63]/DDR1_DQ[47]

SKL-U_BGA1356 @

SKL-U

DDR3L / LPDDR3 / DDR4

DDR0_MA[5]/DDR0_CAA[0]/DDR0 _MA[5]
DDR0_MA[9]/DDR0_CAA[1]/DDR0 _MA[9]
DDR0_MA[6]/DDR0_CAA[2]/DDR0 _MA[6]
DDR0_MA[8]/DDR0_CAA[3]/DDR0 _MA[8]
DDR0_MA[7]/DDR0_CAA[4]/DDR0 _MA[7]

DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]
DDR0_MA[12]/DDR0_CAA[6]/DDR 0_MA[12]
DDR0_MA[11]/DDR0_CAA[7]/DDR 0_MA[11]

DDR0_MA[15]/DDR0_CAA[8]/DDR 0_ACT#
DDR0_MA[14]/DDR0_CAA[9]/DDR 0_BG[1]

DDR0_MA[13]/DDR0_CAB[0]/DDR 0_MA[13]

DDR0_CAS#/DDR0_CAB[1]/DDR0_ MA[15]

DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]

DDR0_RAS#/DDR0_CAB[3]/DDR0_ MA[16]

DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]

DDR0_MA[2]/DDR0_CAB[5]/DDR0 _MA[2]

DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]

DDR0_MA[10]/DDR0_CAB[7]/DDR 0_MA[10]

DDR0_MA[1]/DDR0_CAB[8]/DDR0 _MA[1]
DDR0_MA[0]/DDR0_CAB[9]/DDR0 _MA[0]

Interleave / Non-Interl eaved

DDR0_DQSN[2]/DDR0_DQSN[4]
DDR0_DQSP[2 ]/DDR0_DQ SP[4]
DDR0_DQSN[3]/DDR0_DQSN[5]
DDR0_DQSP[3 ]/DDR0_DQ SP[5]
DDR0_DQSN[4]/DDR1_DQSN[0]
DDR0_DQSP[4 ]/DDR1_DQ SP[0]
DDR0_DQSN[5]/DDR1_DQSN[1]
DDR0_DQSP[5 ]/DDR1_DQ SP[1]
DDR0_DQSN[6]/DDR1_DQSN[4]
DDR0_DQSP[6 ]/DDR1_DQ SP[4]
DDR0_DQSN[7]/DDR1_DQSN[5]
DDR0_DQSP[7]/DDR1_DQSP[5]

DDR CH -A

2 OF20

DDR_VREF _CA
DDR0_VREF _DQ
DDR1_VREF_DQ

DDR_VTT_CNTL

Rev_1.0

DDR0_CKN[0]
DDR0_CKP[0]
DDR0_CKN[1]
DDR0_CKP[1]

DDR0_CKE[0]
DDR0_CKE[1]
DDR0_CKE[2]
DDR0_CKE[3]

DDR0_CS#[0]
DDR0_CS#[1 ]
DDR0_ODT[0 ]
DDR0_ODT[1]

DDR0_MA[3]

DDR0_MA[4]
DDR0_DQSN[0]
DDR0_DQSP[0]
DDR0_DQSN[1]
DDR0_DQSP[1]

DDR0_ALERT#

DDR0_PAR

DDR_A_CLK#0

1 2

CC110

3300P_0402_50V7-K

DDR_A_CLK#0 <18>

DDR_A_CLK0 <18>
TP@ T186
TP@ T189

DDR_A_CKE0 <18,20>
TP@ T190

DDR_A_CS#0 <18,20>
TP@ T187

DDR_A_ODT0 <18,20>
TP@ T188

DDR_A_MA5 <18,20>

DDR_A_MA9 <18,20>

DDR_A_MA6 <18,20>

DDR_A_MA8 <18,20>

DDR_A_MA7 <18,20>

DDR_A_BG0 <18,20>

DDR_A_MA12 <18,20>

DDR_A_MA11 <18,20>

M_A_ACT# <18,20>

DDR_A_BG1 <18>

DDR_A_MA13 <18,20>

DDR_A_MA15 <18,20>

DDR_A_MA14 <18,20>

DDR_A_MA16 <18,20>

DDR_A_BA0 <18,20>

DDR_A_MA2 <18,20>

DDR_A_BA1 <18,20>

DDR_A_MA10 <18,20>

DDR_A_MA1 <18,20>

DDR_A_MA0 <18,20>

DDR_A_MA3 <18,20>

DDR_A_MA4 <18,20>

DDR_A_DQS#0 <18>

DDR_A_DQS0 <18>

DDR_A_DQS#1 <18>

DDR_A_DQS1 <18>

DDR_A_DQS#2 <18>

DDR_A_DQS2 <18>

DDR_A_DQS#3 <18>

DDR_A_DQS3 <18>

DDR_A_DQS#4 <18>

DDR_A_DQS4 <18>

DDR_A_DQS#5 <18>

DDR_A_DQS5 <18>

DDR_A_DQS#6 <18>

DDR_A_DQS6 <18>

DDR_A_DQS#7 <18>

DDR_A_DQS7 <18>

DDR_A_ALERT# <18>

DDR_A_PARITY <18,20>

+0.6V_A_VREFCA <18> @

T25

+0.6V_B_VREFDQ <19>

<19> DDR_B_D[0..15]

<19> DDR_B_D[16..31]

<19> DDR_B_D[32..47]

<19> DDR_B_D[48..63]

Trace width/Spacing >= 20mils
Place componment near SODIMM

#543016 PDG0.9 P.163 RC place near SODIMM

DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7

DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47

DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

UC1C

Interleave / Non-Interleaved

AF65

DDR1_DQ[0]/DDR0_DQ [16]

AF64

DDR1_DQ[1]/DDR0_DQ [17]

AK65

DDR1_DQ[2]/DDR0_DQ [18]

AK64

DDR1_DQ[3]/DDR0_DQ [19]

AF66

DDR1_DQ[4]/DDR0_DQ [20]

AF67

DDR1_DQ[5]/DDR0_DQ [21]

AK67

DDR1_DQ[6]/DDR0_DQ [22]

AK66

DDR1_DQ[7]/DDR0_DQ [23]

AF70

DDR1_DQ[8]/DDR0_DQ [24]

AF68

DDR1_DQ[9]/DDR0_DQ [25]

AH71

DDR1_DQ[10]/DDR0_DQ[26]

AH68

DDR1_DQ[11]/DDR0_DQ[27]

AF71

DDR1_DQ[12]/DDR0_DQ[28]

AF69

DDR1_DQ[13]/DDR0_DQ[29]

AH70

DDR1_DQ[14]/DDR0_DQ[30]

AH69

DDR1_DQ[15]/DDR0_DQ[31]

AT66

DDR1_DQ[16]/DDR0_DQ[48]

AU66

DDR1_DQ[17]/DDR0_DQ[49]

AP65

DDR1_DQ[18]/DDR0_DQ[50]

AN65

DDR1_DQ[19]/DDR0_DQ[51]

AN66

DDR1_DQ[20]/DDR0_DQ[52]

AP66

DDR1_DQ[21]/DDR0_DQ[53]

AT65

DDR1_DQ[22]/DDR0_DQ[54]

AU65

DDR1_DQ[23]/DDR0_DQ[55]

AT61

DDR1_DQ[24]/DDR0_DQ[56]

AU61

DDR1_DQ[25]/DDR0_DQ[57]

AP60

DDR1_DQ[26]/DDR0_DQ[58]

AN60

DDR1_DQ[27]/DDR0_DQ[59]

AN61

DDR1_DQ[28]/DDR0_DQ[60]

AP61

DDR1_DQ[29]/DDR0_DQ[61]

AT60

DDR1_DQ[30]/DDR0_DQ[62]

AU60

DDR1_DQ[31]/DDR0_DQ[63]

AU40

DDR1_DQ[32]/DDR1_DQ[16]

AT40

DDR1_DQ[33]/DDR1_DQ[17]

AT37

DDR1_DQ[34]/DDR1_DQ[18]

AU37

DDR1_DQ[35]/DDR1_DQ[19]

AR40

DDR1_DQ[36]/DDR1_DQ[20]

AP40

DDR1_DQ[37]/DDR1_DQ[21]

AP37

DDR1_DQ[38]/DDR1_DQ[22]

AR37

DDR1_DQ[39]/DDR1_DQ[23]

AT33

DDR1_DQ[40]/DDR1_DQ[24]

AU33

DDR1_DQ[41]/DDR1_DQ[25]

AU30

DDR1_DQ[42]/DDR1_DQ[26]

AT30

DDR1_DQ[43]/DDR1_DQ[27]

AR33

DDR1_DQ[44]/DDR1_DQ[28]

AP33

DDR1_DQ[45]/DDR1_DQ[29]

AR30

DDR1_DQ[46]/DDR1_DQ[30]

AP30

DDR1_DQ[47]/DDR1_DQ[31]

AU27

DDR1_DQ[48]

AT27

DDR1_DQ[49]

AT25

DDR1_DQ[50]

AU25

DDR1_DQ[51]

AP27

DDR1_DQ[52]

AN27

DDR1_DQ[53]

AN25

DDR1_DQ[54]

AP25

DDR1_DQ[55]

AT22

DDR1_DQ[56]

AU22

DDR1_DQ[57]

AU21

DDR1_DQ[58]

AT21

DDR1_DQ[59]

AN22

DDR1_DQ[60]

AP22

DDR1_DQ[61]

AP21

DDR1_DQ[62]

AN21

DDR1_DQ[63]

SKL-U_BGA1356 @

SKL-U

DDR1_MA[5]/DDR1_CAA[0]/DDR1 _MA[5]
DDR1_MA[9]/DDR1_CAA[1]/DDR1 _MA[9]
DDR1_MA[6]/DDR1_CAA[2]/DDR1 _MA[6]
DDR1_MA[8]/DDR1_CAA[3]/DDR1 _MA[8]
DDR1_MA[7]/DDR1_CAA[4]/DDR1 _MA[7]

DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]
DDR1_MA[12]/DDR1_CAA[6]/DDR 1_MA[12]
DDR1_MA[11]/DDR1_CAA[7]/DDR 1_MA[11]

DDR1_MA[15]/DDR1_CAA[8]/DDR 1_ACT#
DDR1_MA[14]/DDR1_CAA[9]/DDR 1_BG[1]

DDR1_MA[13]/DDR1_CAB[0]/DDR 1_MA[13]

DDR1_CAS#/DDR1_CAB[1]/DDR1_ MA[15]

DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]

DDR1_RAS#/DDR1_CAB[3]/DDR1_ MA[16]

DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]

DDR1_MA[2]/DDR1_CAB[5]/DDR1 _MA[2]

DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]

DDR1_MA[10]/DDR1_CAB[7]/DDR 1_MA[10]

DDR1_MA[1]/DDR1_CAB[8]/DDR1 _MA[1]

DDR1_MA[0]/DDR1_CAB[9]/DDR1 _MA[0]

DDR1_DQSN[0]/DDR0_DQSN[2]
DDR1_DQSP[0 ]/DDR0_DQ SP[2]
DDR1_DQSN[1]/DDR0_DQSN[3]
DDR1_DQSP[1 ]/DDR0_DQ SP[3]
DDR1_DQSN[2]/DDR0_DQSN[6]
DDR1_DQSP[2 ]/DDR0_DQ SP[6]
DDR1_DQSN[3]/DDR0_DQSN[7]
DDR1_DQSP[3 ]/DDR0_DQ SP[7]
DDR1_DQSN[4]/DDR1_DQSN[2]
DDR1_DQSP[4 ]/DDR1_DQ SP[2]
DDR1_DQSN[5]/DDR1_DQSN[3]
DDR1_DQSP[5]/DDR1 _DQSP[3]

DDR CH- B

3 OF20

DDR1_CKN[0]
DDR1_CKN[1]
DDR1_CKP[0]
DDR1_CKP[1]

DDR1_CKE[0]
DDR1_CKE[1]
DDR1_CKE[2]
DDR1_CKE[3]

DDR1_CS#[0]
DDR1_CS#[1 ]
DDR1_ODT[0 ]
DDR1_ODT[1]

DDR3L / LPDDR3 /DDR4

DDR1_MA[3]

DDR1_MA[4]

Interleave / Non- Interleaved

DDR1_DQSN[6]
DDR1_DQSP[6]
DDR1_DQSN[7]
DDR1_DQSP[7]
DDR1_ALERT#

DDR1_PAR
DRAM_RESET#
DDR_RCOMP[0]
DDR_RCOMP[1]
DDR_RCOMP[2]

Rev_1.0

AN45
AN46
AP45
AP46

AN56
AP55
AN55
AP53

BB42
AY42
BA42
AW 42

AY48
AP50
BA48
BB48
AP48
AP52
AN50
AN48
AN53
AN52
BA43
AY43
AY44
AW 44
BB44
AY47
BA44
AW 46
AY46
BA46

BB46
BA47

AH66
AH65
AG69
AG70
AR66
AR65
AR61
AR60
AT38
AR38
AT32
AR32

AR25
AR27
AR22
AR21
AN43
AP43
AT13
AR18
AT18
AU18

DDR_B_CLK#0DDR_B_D0

DDR_B_CLK#1

DDR_B_CLK0
DDR_B_CLK1

DDR_B_CKE0

DDR_B_CKE1

DDR_B_CS#0
DDR_B_CS#1
DDR_B_ODT0

DDR_B_ODT1

DDR_B_MA5
DDR_B_MA9
DDR_B_MA6
DDR_B_MA8
DDR_B_MA7
DDR_B_BG0
DDR_B_MA12
DDR_B_MA11
M_B_ACT#
DDR_B_BG1
DDR_B_MA13
DDR_B_MA15
DDR_B_MA14

DDR_B_MA16
DDR_B_BA0
DDR_B_MA2
DDR_B_BA1

DDR_B_MA10
DDR_B_MA1
DDR_B_MA0

DDR_B_MA3
DDR_B_MA4

DDR_B_DQS#0
DDR_B_DQS0
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_DQS#5
DDR_B_DQS5

DDR_B_DQS#6
DDR_B_DQS6
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_ALERT#
DDR_B_PARITY
DDR_DRAMRST#

SM_RCOMP0

SM_RCOMP1
SM_RCOMP2

#543016 PDG0.9 P.117
W=12-15 Space= 20/25 L=500mil

RC16 1 SDP@ 2 200_0402_1%
RC17 1 2 80.6_0402_1%
RC18 1 2 100_0402_1 %

DDR_B_CLK#0 <19>
DDR_B_CLK#1 <19>
DDR_B_CLK0 <19>
DDR_B_CLK1 <19>

DDR_B_CKE0 <19>
DDR_B_CKE1 <19>

DDR_B_CS#0 <19>
DDR_B_CS#1 <19>
DDR_B_ODT0 <19>
DDR_B_ODT1 <19>

DDR_B_MA5 <19>
DDR_B_MA9 <19>
DDR_B_MA6 <19>
DDR_B_MA8 <19>
DDR_B_MA7 <19>
DDR_B_BG0 <19>
DDR_B_MA12 <19>
DDR_B_MA11 <19>
M_B_ACT# <19>
DDR_B_BG1 <19>
DDR_B_MA13 <19>
DDR_B_MA15 <19>
DDR_B_MA14 <19>
DDR_B_MA16 <19>
DDR_B_BA0 <19>
DDR_B_MA2 <19>
DDR_B_BA1 <19>
DDR_B_MA10 <19>
DDR_B_MA1 <19>
DDR_B_MA0 <19>

DDR_B_MA3 <19>
DDR_B_MA4 <19>

DDR_B_DQS#0 <19>
DDR_B_DQS0 <19>
DDR_B_DQS#1 <19>
DDR_B_DQS1 <19>
DDR_B_DQS#2 <19>
DDR_B_DQS2 <19>
DDR_B_DQS#3 <19>
DDR_B_DQS3 <19>
DDR_B_DQS#4 <19>
DDR_B_DQS4 <19>
DDR_B_DQS#5 <19>
DDR_B_DQS5 <19>

DDR_B_DQS#6 <19>
DDR_B_DQS6 <19>
DDR_B_DQS#7 <19>
DDR_B_DQS7 <19>
DDR_B_ALERT# <19>
DDR_B_PARITY <19>
DDR_DRAMRST# <18,19>

< For ODT & V TT Power Co ntrol >

DDR_VTT_CNTL to DDR
VTT supplied ramped
<35uS
(tCPU18)

UC2

1

NC

DDR_PG_CTRL

A A

VCC

2

A

3

GND

74AUP1G07SE-7 SOT353 5P LOW PW BUFF

SA00007WE00

1

CC1 RC132

0.1U_0201_10V6K 100K_0402_5%

@

2

5

4

Y

+3VS+1.2V

12

DDR_DRAMRST#

DDR_VTT_PG_CTRL <45>

Security Classification

Issued Date Decipherii ed Date

THIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIETARY P ROPERTY OF COMPAL ELECTRONIICS,,, IIINC. AND CONTAIIINS CONFIIIDENTIIIAL AND
TRADE SECRET IIINFORMATIIION. THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIIISIIION OF R& D
DEPARTMENT EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONICS,,, IIINC. NEIIITHER THIS SHEET NOR THE IIINFORMATIIION IIITCONTAIIINS

5 4 3 2 1

MAY BE USED BY OR DIISCLOSED TO ANY THIRD PARTY WIIITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONIIICS,,,IIINC.

+1.2V

12

RC20
470_0402_5%

@

1

CC96
100P_0402_50V8J

ESD@

2

Close t oCPU

2018/03/09 2019/03/09

Compal Secret Data

Recommended By Intel Max

RC16

SD034121090

121_0402_1%

DDP@

Compal Electronics,Inc.

Tiiittllle

Siiize Document Number

Custttom

Dattte::: Friiiday,,, March 09,2018

SKL-U(2/12)DDR3L

LA-G202P

Sheet 7

R ev

1...0

55

off

5 4 3 2 1

L

T

L

T

T

SML0ALERT# (Internal Pull Down):
eSPI or LPC
0 = LPC is selected for EC ==> Default

D D

+3VALW

RC21 1 @ 2 1K_0402_5%

RC22 1 @ 2 1K_0402_5%
RC24 1 @ 2 1K_0402_5%

SOC_SPI_IO2

SOC_SPI_IO3

1 = eSPI is selected for EC

SOC_SML0CLK
SOC_SML0DATA

RPC12

1 8
2 7
346

5

499_0804_8P4R_1%

+3VS

UC1E

+3VS

RC112 1 2 10K_0 402_5%

+3VS

RC25 1 2 8.2K_04 02_5%

C C

KB_RST#

SERIRQ

<36> SERIRQ

SOC_SPI_CLK
SOC_SPI_SO
SOC_SPI_SI
SOC_SPI_IO2
SOC_SPI_IO3
SOC_SPI_CS#0

KB_RST#

SERIRQ

AW 3
AW 2

AW 13

AY11

SPI - FLASH

AV2

SPI0_CLK
SPI0_MISO

AV3

SPI0_MOSI
SPI0_IO2

AU4

SPI0_IO3

AU3

SPI0_CS0#

AU2

SPI0_CS1#

AU1

SPI0_CS2#

SPI - TOUCH

M2

GPP_D1/ SPI1_CLK

M3

GPP_D2/SPI1_MISO

J4

GPP_D3/SPI1_MOSI

V1

GPP_D21 /SPI1_IO2

V2

GPP_D22 /SPI1_IO3

M1

GPP_D0/ SPI1_CS#

C LINK

G3

CL_CLK

G2

CL_DATA

G1

CL_RST#

GPP_A0/RCIN#
GPP_A6/SERIRQ

SKL-U_BGA1356 @

SKL-U

LPC

GPP_A14/SUS_ST AT#/ES PI_RESET#

5 OF20

SMBUS,SMLINK

GPP_A9/CLKOUT _LPC0/ESPI_CL K

GPP_C0/SMBC

GPP_C1/SMBDA

GPP_C2/SMBALERT

GPP_C3/SML0C

GPP_C4/SML0DA

GPP_C5/SML0ALERT

GPP_C6/SML1CL

GPP_C7/SML1DA

GPP_B23/SML1ALERT#/PCHHOT

GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1
GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ ESPI_CS#

GPP_A10/CLKOUT _LPC1

GPP_A8/CLKRUN#

Rev_1.0

K
A

#

K
A

#

K
A

#

R8
R10

W2
W1

BA13
BB13
AY12
BA12
BA11

AY9
AW 11

R7

R9

W3

V3

AM7

AY13

AW 9

SOC_SMBCLK
SOC_SMBDATA
SOC_SMBALERT#

SOC_SML0CLK
SOC_SML0DATA
SOC_SML0ALERT#

SOC_SML1ALERT#

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

LPC_FRAME#

LPC_CLK0

PM_CLKRUN#

SOC_SMBCLK <19>
SOC_SMBDATA <19>

TP@ T124

TP@ T125

EC_SMB_CK2 <24,36>
EC_SMB_DA2 <24,36>

LPC_AD0 <36>
LPC_AD1 <36>
LPC_AD2 <36>
LPC_AD3 <36>

LPC_FRAME# <36>

RC26 1 EMI@ 2 22_0402_5%

SMB

(Link to DDR)

SML1

(Link to EC,DGPU,Thermal Sensor)

CLK_LPC_EC <36>
PM_CLKRUN# <36>

SOC_SML1ALERT#

SOC_SMBCLK
SOC_SMBDATA
EC_SMB_CK2
EC_SMB_DA2

PM_CLKRUN#

RC113 1 @ 2 150K_0402_5%

RC31 1 2 8.2K_0402_5%

Follow 543016_SKL_U_Y_PDG_0_9

RPC2

1 8
2 7
3 6
4 5

1K_0804_8P4R_5%

+3VS

+3VS

RPC1, RPC3 and RC30 are close to UC3

RPC1

SOC_SPI_SO

SOC_SPI_CLK

SOC_SPI_SI

SOC_SPI_IO2

EC_SPI_CLK
EC_SPI_MOSI
EC_SPI_CS0#
EC_SPI_MISO

SOC_SPI_IO3

RC30 EMI@ 33_0402_5%

B B

From EC

<36> EC_SPI_CLK
<36> EC_SPI_MOSI
<36> EC_SPI_CS0#

<36> EC_SPI_MISO

From SOC

1 8
2 7
3 6
4 5

33_0804_8P4R _5%

EMI@

2

1

RPC3

8

1

7

2

6

3

5

4

33_0804_8P4R _5%

EMI@

SOC_SPI_SO_0_R
SOC_SPI_CLK_0_R
SOC_SPI_SI_0_R
SOC_SPI_IO3_0_R

SOC_SPI_IO2_0_R

SOC_SPI_CLK_0_R
SOC_SPI_SI_0_R
SOC_SPI_CS#0
SOC_SPI_SO_0_R

< SPI ROM - 8MB > -Main Source - XMC

+3VALW

A A

5 4 3 2 1

SOC_SPI_CS#0
SOC_SPI_SO_0_R
SOC_SPI_IO2_0_R

UC3

1

/CS VCC

2

DO(IO1) /HOLD(IO3)

3

/WP( IO2) C LK

4 5

GND DI(IO0)

S IC FL 64M XM25QH64AHIG SOP 8P

SA0000B8300

@

CC2 1 2 0.1U_0201_10V K X5R

8

SOC_SPI_IO3_0_R

7

SOC_SPI_CLK_0_R

6

SOC_SPI_SI_0_R

1

CC3

10P_0402_50 V8J

2

@EMI@

SecuriiityClllassiiifiiicatiiion

Issued Date Decipii hered Date

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL AND
TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT B E TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIIONOF R&D
DEPARTMENT EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IIINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIITCONTAIIINS
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IIINC...

2018/03/09 2019/03/09

Compal Secret Data

Tiiittllle

Siiize Documentt Number

Custttom

Compal Electronics,Inc.

SKL-U(3/12)SPI,SMB,LPC,ESPI

LA-G202P

Sheett 8 o ff 55Datte:: Friiiday,,, March 09,,,2018

R ev

1...0

5 4 3 2 1

D D

< HD AUDIO >

<30> HDA_BITCLK_AUDIO
<30> HDA_SYNC_AUDIO

<30> HDA_SDOUT_AUDIO

RPC4

8

1

7

2
3

6

4

5

33_0804_8P4R _5%

EMI@

HDA_BIT_CLK
HDA_SYNC

HDA_SDOUT

<30> HDA_SDIN0

HDA_SYNC
HDA_BIT_CLK
HDA_SDOUT

< To Enable ME Over ride >

HDA_SPKR

HDA_SDOUT

<30> HDA_SPKR

HDA_SPKR

C C

<36> ME_EN

RC116 1 2 0_0402_5%

+3VS

RC33 1 @ 2 2.2K_0402_5%

SPKR (Internal Pull Down):

B B

TOP Swap Override
0 = Disable TOP Swap mode. ==> Default
1 = Enable TOP Swap Mode.

UC1G

BA22
AY22
BB22
BA21

AY21

AW 22

AY20

AW 20

AK7
AK6
AK9
AK10

AW 5

AUDIO

HDA_SYNC/I2S0_SFRM
HDA_BLK/I2S0_SCLK
HDA_SDO /I2S0_T XD
HDA_SDI0/I2S0_RXD
HDA_SDI1/I2S1_RXD
HDA_RST #/I2S1_SCLK

J5

GPP_D23/I2S_MC LK
I2S1_SFRM
I2S1_TXD

GPP_F1/I2S2_SFRM
GPP_F0/I2S2_SCLK
GPP_F2/I2S2_TXD
GPP_F3/I2S2_RXD

H5

GPP_D19/DMIC_CLK0

D7

GPP_D20/DMIC_DATA0

D8

GPP_D17/DMIC_CLK1

C8

GPP_D18/DMIC_DATA1
GPP_B14/SPKR

SKL-U_BGA1356 @

UC1I

CSI-2

A36

CSI2_DN0

B36

CSI2_D P0

C38

CSI2_DN1

D38

CSI2_D P1

C36

CSI2_DN2

D36

CSI2_DP2

A38

CSI2_DN3

B38

CSI2_DP3

C31

CSI2_DN4

D31

CSI2_D P4

C33

CSI2_DN5

D33

CSI2_D P5

A31

CSI2_DN6

B31

CSI2_DP6

A33

CSI2_DN7

B33

CSI2_DP7

A29

CSI2_DN8

B29

CSI2_DP8

C28

CSI2_DN9

D28

CSI2_DP9

A27

CSI2_DN10

B27

CSI2_DP10

C27

CSI2_DN11

D27

CSI2_DP11

SKL-U_BGA1356 @

SKL-U

SKL-U

9 OF20

GPP_A17/SD_PW R_EN#/ISH_GP7

7 OF20

Rev_1.0

CSI2_CLKN0
CSI2_C LKP0
CSI2_CLKN1
CSI2_C LKP1
CSI2_CLKN2
CSI2_CLKP2
CSI2_CLKN3
CSI2_CLKP3

CSI2_COMP

GPP_D4/ FLASHT RIG

EMMC

GPP_F13/EMMC_DAT A0
GPP_F14/EMMC_DATA1
GPP_F15/EMMC_DATA2
GPP_F16/EMMC_DATA3
GPP_F17/EMMC_DATA4
GPP_F18/EMMC_DATA5
GPP_F19/EMMC_DAT A6
GPP_F20/EMMC_DAT A7

GPP_F21/EMMC_RCLK

GPP_F22/EMMC_CLK

GPP_F12/EMMC_CMD

EMMC_RCOMP

SDIO / SDXC

GPP_G0/SD_C MD
GPP_G1/SD_D ATA0
GPP_G2/SD_D ATA1
GPP_G3/SD_D ATA2
GPP_G4/SD_D ATA3

GPP_G5/SD_CD #
GPP_G6/SD_C LK
GPP_G7/SD_W P

GPP_A16/SD_1P 8_SEL

SD_RCOMP

GPP_F23

C37

D37
C32
D32
C29
D29

B26

A26

E13

RC80 1 @ 2 100_0402_1%

B7

AP2

AP1

AP3
AN3
AN1
AN2

AM4

AM1

AM2
AM3
AP4

AT1

RC129 1 @ 2 200_0402_1%

Rev_1.0

AB11
AB13
AB12
W12
W11
W10
W8
W7

BA9
BB9

AB7

RC76 1 @ 2 200_0402_1%

AF13

A A

SecuriiityClllassiiifiiicatiiion

IssuedDate

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL AND
TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT B E TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIIONOF R&D
DEPARTMENT EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IIINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIITCONTAIIINS

5 4 3 2

MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IIINC...

2018/03/09 2019/03/09

Compal Secret Data

Deciiiphered Date

Tiiittllle

Siiize Documentt Number

Custttom

Datte:: Friiiday,,, March 09,,,2018

Compal Electronics,Inc.

SKL-U(4/12)HDA,EMMC,SDIO,CSI2

LA-G202P

Sheett 9 o ff

1

R ev

1...0

55

5 4 3 2 1

SOC_XTAL24_IN

U22_EMI@

RC154 1 2 33_040 2_1%

XTAL24_IN

SOC_XTAL24_OUT

D D

<21> CLK_PEG_VGA#

DGPU

<21> CLK_PEG_VGA

<21> VGA_CLKREQ#
<31> CLK_PCIE_LAN#

LAN

+3VS

RPC6

8

VGA_CLKREQ#

1

7

WLANCLK_REQ#

2
3

6
5

LANCLK_REQ#

4

10K_0804_8P4R_5%

+3VL_RTC

C C

RC36 1 2 20K_0402_5%
CC6 1 2 1U_0201_6.3V6M

RC37 1 2 20K_0402_5%
CC7 1 2 1U_0201_6.3V6M
CLRP2 1 2 SHORT PADS

RC39 1 2 1M_0402_5%

+3VALW

8
7
6

B B

5 4

10K_0804_8P 4R_5%

ESD@ 1

CC97

ESD@ 1

CC94

ESD@ 1

CC95

+3VALW

1 2

RC47 1K_040 2_5%

RPC7

1
2
3

2

100P_0402_5 0V8J

2

100P_0402_5 0V8J

2

100P_0402_5 0V8J

SE00000UC00

SE00000UC00

PCH_PWROK
EC_RSMRST#
LAN_WAKE#
SYS_RESET#

SYS_RESET#
EC_RSMRST#
SYS_PWROK

WAKE#

EC_SCI# <6,36>

SOC_SRTCRST#

SOC_RTCRST#

CLR CMOS

SM_INTRUDER#

RC38 1 2 0_0402_5%

Only For Power Sequ ence Debug

From EC (Open-Drain)

A A

5 4 3 2 1

<36> VCCST_PWRGD

NGFF WL+BT

+1.0V_VCCST

<31> CLK_PCIE_LAN
<31> LANCLK_REQ#

<33> CLK_PCIE_WLAN#
<33> CLK_PCIE_WLAN
<33> WLANCLK_REQ#

EC_CLEAR_CMOS# <36>

<36> EC_RSMRST#

<36> SYS_PWROK

<36> PCH_PWROK

12

RC52
1K_0402_5%

RC53 1 2 60.4_0402_1%

1

CC117
100P_0402_50V8J

2

ESD@

T132 TP@

VGA_CLKREQ#

LANCLK_REQ#

WLANCLK_REQ#

< PCH PLTRST Buffer >

SOC_PLTRST#
SYS_RESET#
EC_RSMRST#

H_CPUPWRGD
EC_VCCST_PG

SYS_PWROK
PCH_PWROK
EC_RSMRST#

WAKE#
LAN_WAKE#

EC_VCCST_PG

SOC_PLTRST#

AY17

UC1J

D42

CLKOUT _PCIE_N0

C42

CLKOUT _PCIE_P0

AR10

GPP_B5/SRCCLKREQ0#

B42

CLKOUT _PCIE_N1

A42

CLKOUT _PCIE_P1

AT7

GPP_B6/SRCCLKREQ1#

D41

CLKOUT _PCIE_N2

C41

CLKOUT _PCIE_P2

AT8

GPP_B7/SRCCLKREQ2#

D40

CLKOUT _PCIE_N3

C40

CLKOUT _PCIE_P3

AT10

GPP_B8/SRCCLKREQ3#

B40

CLKOUT _PCIE_N4

A40

CLKOUT _PCIE_P4

AU8

GPP_B9/SRCCLKREQ4#

E40

CLKOUT _PCIE_N5

E38

CLKOUT _PCIE_P5

AU7

GPP_B10/SRCCLKREQ5#

SKL-U_BGA1356 @

RC42 1 @ 2 0_0402_5%

+3VS

5

UC4@

1

B

2

A

TC7SH08FUF_SSOP5

SA007080100

UC1K

AN10

GPP_B13/PLTRST#

B5

SYS_RESET#

RSMRST#

A68

PROCPW RGD

B65

VCCST_PW RGD

B6

SYS_PW ROK

BA20

PCH_PW ROK

BB20

DSW _PW ROK

AR13

GPP_A13/SUSW ARN#/SUSPWRD NACK

AP11

GPP_A15/SUSACK#

BB15

WA KE#

AM15

GPD2/LAN_WAKE#

AW 17

GPD11/LANPHYPC

AT15

GPD7/RSVD

SKL-U_BGA1356 @

G P

3

SYSTEM POWERMANAGEMENT

SKL-U

CLOCKSIGNALS

10 OF20

4

Y

%

12

100K_0402_5

RC44

2 1

SKL-U

11 OF20

100P_0402_50V8

J

ESD@

CC8

GPP_B11/EXT_PW R_GATE#

GPP_B2/VRALERT #

SecuriiityClllassiiifiiicatiiion

Issued Date Decipii hered Date

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL
AND TRADE SECRET IIINFORMATIIION... THIIIS SHEET MA Y NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIIONOF R&D
DEPARTMENT EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IIINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIITCONTAIIINS MAY BE USED
BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IIINC...

Rev_1.0

CLKOUT _ITPXD P_N
CLKOUT _ITPXD P_P

GPD8/SU SCLK

XCLK_BIASREF

PCI_RST# <21,31,33,36>

GPP_B12/SLP_S0#

GPD4/SL P_S3#
GPD5/SL P_S4#

GPD10/SLP_S5#

GPD9/SL P_WLAN#

GPD6/SL P_A#

GPD3/PW RBT N#

GPD1/AC PRESENT

GPD0/BATLOW#

GPP_A11/PME#

INTRUDER#

F43
E43

BA17 SUSCLK

SOC_XTAL24_IN

E37

XTAL24_IN

XTAL24_OUT

RTCX1
RTCX2

SRTCRST#

RTCRST#

Rev_1.0

SLP_SUS#

SLP_LAN#

2018/03/09 2019/03/09

AP15
BA16
AY16

AW 15

AY15
AU13

AP16

AM11

E35

AM20

AM16

AT11

AN15

BB17

AN16

BA15

AU11

AM10

E42
AM18

AN18

SOC_XTAL24_OUT
XCLK_BIASREF

SOC_RTCX1

SOC_RTCX2

SOC_SRTCRST#

SOC_RTCRST#

PM_SLP_S0#
PM_SLP_S3#
PM_SLP_S4#
PM_SLP_S5#

SLP_WLAN#
PM_SLP_A#

PBTN_OUT#
AC_PRESENT_R

PM_BATLOW#

SM_INTRUDER#

SOC_VRALERT#

TP@T130

PM_SLP_S3# <36>
PM_SLP_S4# <36,43,46>

TP@T131

TP@T133
TP@T134

RC103 1 @ 2 0_0402_5%

Compal Secret Data

SUSCLK <33>

RC155

U22_EMI@

1

XTAL24_OUT

2 33_0402_1%

27P_0402_50V8J

XCLK_BIASREF

U22@

RC34 1 2 1M_0402_5%

YC1 U22@

24MHZ_18PF_XRCG B24M000F2P51R0

SJ10000UJ00

1

1

NC NC

2 4

U22@

1

CC4

2

1

RC35

RC110 1 @ 2 60.4_0402_ 1%

2 2.7K_0402_1%

Follow 5 46765_20 14WW48_Skyla ke_MOW_Rev_1_0

Stuff 2.7 k ohm (RC 35) PU for S kyLake-U

Stuff 60. 4 ohm (RC 110) PD for CannonLa ke-U

SOC_RTCX2

SOC_RTCX1

PBTN_OUT# <36>
AC_PRESENT <24,36>

Tiiitllle

Siiize Document Number Rev

Custttom 1...0

Date: Friiiday,,, March 09,,,2018 Sheet 10 o ff 55

RC41 1 2 10M_0402_5 %

YC2

1 2

S CRYSTAL 32.768KHZ 9PF X1A00014100 0200

SJ10000PW00

6.8P_0402_50V8

C

1

CC9

2

PM_BATLOW #
AC_PRESENT
SOC_VRALERT#

RC46 1 2 8.2K_04 02_5%
RC48 1 @ 2 10K_0402_5%

RC50 1@

Compal Electronics,Inc.

SKL-U(5/12)CLK,PM,GPIO

LA-G202P

3

3

+1.0V_CLK5_F24NS

2 10K_0402_5%

U22@

27P_0402_50V8J

1

CC5

2

6.8P_0402_50V8

C

1

CC10

2

+3VALW

5 4 3 2 1

GSPI0_MOSI (Internal Pull Down):
No Reboot
0 = Disable No Reboot mode. ==> Default
1 = Enable No Reboot Mode. (PCH will disable the TCO

Timer system reboot feature). This funct i oni s us ef ul

D D

when running ITP/XDP.

Capacity Description

WITHOUT ON-BOARD RAM

SAMSUNG 2666MHz K4A8G165WC-BCTD X7677538L13 SA0000B6F10

HYNIX 2666MHzH5AN8G6NCJR-VKC X7677538L15 SA0000BMN10

MICRON 2666MHzMT40A512M16LY-075:E X7677538L14 SA0000ARD30

4GB

N/A N/A N/A

( )

( )

( )

N/A N/A N/A

N/A N/A N/A

N/A N/A N/A

GSPI1_MOSI (Internal Pull Down):

Boot BI OS Strap Bit

0 = S PI Mode ==> Default

1 = LP C Mode

+3VS

RC59 1 @ 2 4.7K_0402_5%
RC60 1 @ 2 150K_0402_5%

GSPI0_MOSI

GSPI1_MOSI

Capacity Description

WITHOUT ON-BOARD RAM

SAMSUNG 2666MHz K4A8G165WC-BCTD 0 0 1

HYNIX 2666MHzH5AN8G6NCJR-VKC 0 1 0

MICRON 2666MHzMT40A512M16LY-075:E 0 1 1

4GB

N/A 1 0 0

( )

( )

( )

N/A 1 0 1

N/A 1 1 0

X76

PART NUMBER R3

N/A

GPP B19

_ _

OBRAMID

GPP B20

_

0 OBRAM ID

_ _ _

0 0 0

( )

N/A

GPP B21

1 OBRAM ID

+3VS+3VS +3VS

12

RC135
10K_0402_5%

@

OBRAM_ID0

12

RC214

2

10K_0402_5%

X76RAM@

12

RC133
10K_0402_5%

X76RAM@

12

RC134
10K_0402_5%

X76RAM@

OBRAM_ID1

12

RC215
10K_0402_5%

X76RAM@

12

RC138
10K_0402_5%

X76RAM@

OBRAM_ID2

Function

Mount ODD

Mount 2nd HDD 1

+3VS

1

RC208

1 @

RC207

HDD ODD DETECT

(

HDD_ODD_DETECT

2

10K_0402_5%

2

10K_0402_5%

_ _

GPP D11

_ )

0

HDD_ODD_DETECT <35>

N/A 1 1 1

Function

15"

C C

+3VS

RPC10

1

8

2

7

3

6

4 5

49.9K_0804_ 8P4R_1%

RPC8

18
27

6

3

5

4

10K_0804_8P4R_5%

RPC11

1

8

2

7

3

6
5 4

2.2K_0804_8 P4R_5%

UART0_RX
UART0_TX

DGPU_PWR_EN
DGPU_HOLD_RST#

WLBT _OFF#

I2C0_SCL_TP
I2C0_SDA_TP

Touch PAD

<38> TP_INT#

<33> WLBT_OFF#

<33> UART0_RX

<33> UART0_TX

<38> I2C0_SDA_TP
<38> I2C0_SCL_TP

SOC_GPIOB17
GSPI0_MOSI

OBRAM_ID0
OBRAM_ID1
OBRAM_ID2
GSPI1_MOSI

SOC_GPIOC10

+3VS

B B

+3VS

UC1F

AN8
AP7
AP8
AR7

AM5

AN7
AP5
AN5

AB1
AB2

AB3
AD1

AD2
AD3
AD4

AH9

AH10
AH11

AH12
AF11

AF12

W 4

U7
U6

U8
U9

LPSS ISH

GPP_B15/GSPI0_CS#
GPP_B16/GSPI0_CLK
GPP_B17/GSPI0_MISO
GPP_B18/GSPI0_MOSI

GPP_B19/GSPI1_CS#
GPP_B20/GSPI1_CLK
GPP_B21/GSPI1_MISO
GPP_B22/GSPI1_MOSI

GPP_C8/ UART0_RXD
GPP_C9/ UART0_TXD GPP_F10/I2C5_SDA/ISH _I2C2 _SDA
GPP_C10 /UART0_RTS# GPP_F11/I2C5_SCL/ISH _I2C2_SCL
GPP_C11 /UART0_CTS#

GPP_C20 /UART2_RXD
GPP_C21 /UART2_TXD
GPP_C22/UART 2_RTS#
GPP_C23/UART 2_CTS#

GPP_C16/I2C0_SDA
GPP_C17/I2C0_SCL

GPP_C18 /I2C1_SD A
GPP_C19/I2C1_SCL GPP_A18/ISH_G P0

GPP_F4/I2C2_ SDA GPP_A20/ISH_GP2
GPP_F5/I2C2_ SCL G PP_A21/ISH_GP3

GPP_F6/I2C3_ SDA GPP_A23/ISH_GP5
GPP_F7/I2C3_SCL Sx_EXIT_HOLDOFF# / G PP_A12 / BM_BU SY# / ISH_GP6

GPP_F8/I2C4_ SDA
GPP_F9/I2C4_ SCL

SKL-U_BGA1356 @

SKL-U

GPP_D13/ISH_UART0_RXD/SML0BD ATA/I2C 4B_SDA

GPP_D14/ISH_UART0_T XD/SML0BCLK/I2C4B _SCL

6 OF20

GPP_D15/ISH_UART0_RT S#

GPP_D16/ISH_UART0_CT S#/SML0BALERT #

GPP_C12/UART 1_RXD/IS H_UART1_RXD

GPP_C13/UART 1_TXD/ISH_UART 1_TXD
GPP_C14/UART 1_RTS#/ISH _UART1_RTS#
GPP_C15/UART 1_CTS#/ISH _UART1_CTS#

Rev_1.0

GPP_D9
GPP_D10
GPP_D11
GPP_D12

GPP_D5/ISH_I2C0_SDA

GPP_D6/ISH_I2C0_SCL

GPP_D7/ISH_I2C1_SDA

GPP_D8/ISH_I2C1_SCL

GPP_A19/ISH_GP1

GPP_A22/ISH_GP4

P2
P3

HDD_ODD_DETECT

P4

MODEL_SETTING

P1

M4
N3

N1
N2

AD11
AD12

U1
U2
U3
U4

DGPU_PWR_EN

AC1

DGPU_HOLD_RST#

AC2

GPU_ALL_PGOOD

AC3

DGPU_PRSNT

AB4

AY8
BA8

DGPU_SEL

BB7
BA7
AY7
AW 7
AP13

DGPU_PWR_EN <26,36>
DGPU_HOLD_RST# <21>
GPU_ALL_PGOOD <26>

14" 1

+3VS

Function
DIS

UMA Only 1

+3VS

Function DGPUSEL

N16V-GMR1 MX110

N16S-GTR M X130 1

+3VS

MODEL SETTING

GPP D12

(__ )

0

RC206 1 14@ 2 10K_0402_5%
RC205 1 15@ 2 10K_0402_5%

DGPU PRSNT

_

GPP C15

_ )

(

0

RC61 1 UMA@ 2 10K_0402_5%
RC62 1 DIS@ 2 10K_040 2_5%

GPP0A20

)

)

N16S_R1@

N16V_R1@

( _

(

(

RC210 1 2 10K_0402_5 %

RC209 1 2 10K_0402_5%

MODEL_SETTING

DGPU_PRSNT

_

)

DGPU_SEL

*N16V -MX110 Device ID: 0x174E
*N16S - MX130 Device ID:0x174D

RC210 N16S_R3@
10K_0402_5%

RC209 N16V_R3@
10K_0402_5%

(
(

)
)

SOC_GPIOC10

SOC_GPIOB17

A A

RC204

RC195

1

1

GPU_EVENT#

2

0_0402_5%

GC6_FB_EN

2 0_0402_5%

5 4 3 2

GPU_EVENT# <24>

GC6_FB_EN <24,25>

TODGPU

SecuriiityClllassiiifiiicatiiion

Issued Date Decipii hered Date

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL
AND TRADE SECRET IIINFORMATIIION... THIIIS SHEET MA Y NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIIONOF R&D
DEPARTMENT EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IIINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIIT CONTAIIINS MAY BE USED
BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IIINC...

2018/03/09 2019/03/09

Compal Secret Data

Tiiittllle

Siiize Documentt Number Rev

Custttom 1...0

Datte:: Friiiday,,, March 09,,,2018

Compal Electronics,Inc.

SKL-U(6/12)GPIO,I2C,GSPI

LA-G202P

Sheett 11 o ff 55

1

5 4 3 2 1

D D

UC1H @

PCIE / USB3 / SATA

<21> PCIE_PRX_DTX_N1
<21> PCIE_PRX_DTX_P1

<21> PCIE_PTX_C_DRX_N1
<21> PCIE_PTX_C_DRX_P1

<21> PCIE_PRX_DTX_N2

<21> PCIE_PRX_DTX_P2

<21> PCIE_PTX_C_DRX_N2

LAN

HDD

ODD

<21> PCIE_PTX_C_DRX_P2

<21> PCIE_PRX_DTX_N3
<21> PCIE_PRX_DTX_P3

<21> PCIE_PTX_C_DRX_N3
<21> PCIE_PTX_C_DRX_P3

<21> PCIE_PRX_DTX_N4

<21> PCIE_PRX_DTX_P4
<21> PCIE_PTX_C_DRX_N4
<21> PCIE_PTX_C_DRX_P4

<31> PCIE_PRX_DTX_N5
<31> PCIE_PRX_DTX_P5
<31> PCIE_PTX_DRX_N5
<31> PCIE_PTX_DRX_P5

<33> PCIE_PRX_DTX_N6
<33> PCIE_PRX_DTX_P6
<33> PCIE_PTX_DRX_N6
<33> PCIE_PTX_DRX_P6

<34> SATA_PRX_DTX_N0
<34> SATA_PRX_DTX_P0
<34> SATA_PTX_DRX_N0
<34> SATA_PTX_DRX_P0

<35> SATA_PRX_DTX_N1
<35> SATA_PRX_DTX_P1
<35> SATA_PTX_DRX_N1
<35> SATA_PTX_DRX_P1

dGPU

C C

NGFF WLAN+BT

B B

CC11 DIS@ 1 2 0.22U_0402_6.3V6K
CC14 DIS@ 1 2 0.22U_0402_6.3V6K

CC15 DIS@ 1 2 0.22U_0402_6.3V6K
CC16 DIS@ 1 2 0.22U_0402_6.3V6K

CC12 DIS@ 1 2 0.22U_0402_6.3V6K
CC13 DIS@ 1 2 0.22U_0402_6.3V6K

CC17 DIS@ 1 2 0.22U_0402_6.3V6K
CC18 DIS@ 1 2 0.22U_0402_6.3V6K

RC71 1 2 100_0402_1%

T147 TP@
T148 TP@

PCIE_PTX_DRX_N1
PCIE_PTX_DRX_P1

PCIE_PTX_DRX_N2
PCIE_PTX_DRX_P2

PCIE_PTX_DRX_N3
PCIE_PTX_DRX_P3

PCIE_PTX_DRX_N4
PCIE_PTX_DRX_P4

PCIE_RCOMPN
PCIE_RCOMPP

XDP_PRDY#
XDP_PREQ#

H13

PCIE1_RXN/USB3_5_RXN

G13

PCIE1_RXP/USB3_5_R XP

B17

PCIE1_TXN/US B3_5_TXN

A17

PCIE1_T XP/USB3_ 5_TXP

G11

PCIE2_RXN/USB3_6_RXN

F11

PCIE2_RXP/USB3_6_R XP

D16

PCIE2_TXN/US B3_6_TXN

C16

PCIE2_T XP/USB3_ 6_TXP

H16

PCIE3_RXN

G16

PCIE3_RXP

D17

PCIE3_TXN

C17

PCIE3_TXP

G15

PCIE4_RXN

F15

PCIE4_RXP

B19

PCIE4_TXN

A19

PCIE4_TXP

F16

PCIE5_RXN

E16

PCIE5_RXP USB2N_2

C19

PCIE5_TXN USB2P_2

D19

PCIE5_T XP

G18

PCIE6_RXN

F18

PCIE6_RXP

D20

PCIE6_TXN

C20

PCIE6_TXP

F20

PCIE7_RXN/SATA0_RXN

E20

PCIE7_RXP/SATA0_R XP

B21

PCIE7_TXN/SATA0_T XN

A21

PCIE7_T XP/SATA0_TXP

G21

PCIE8_RXN/SATA1 A_RXN

F21

PCIE8_RXP/SATA1A _RXP USB2N_7

D21

PCIE8_TXN/SATA1A_TXN USB2P _7

C21

PCIE8_T XP/SATA 1A_TXP

E22

PCIE9_RXN

E23

PCIE9_RXP

B23

PCIE9_TXN

A23

PCIE9_TXP

F25

PCIE10_RXN

E25

PCIE10_RXP

D23

PCIE10_TXN

C23

PCIE10_TXP

F5

PCIE_RCOMPN

E5

PCIE_RCOMPP

D56

PROC_PRDY# GPP_E10/USB2_OC1#

D61

PROC_PREQ# GPP_E11/U SB2_OC2#

BB11

GPP_A7/PIRQ A# GPP_E12/USB2_OC3#

E28

PCIE11_RXN/SATA1B_R XN

E27

PCIE11_RXP/SATA1B_RX P

D24

PCIE11_T XN/SAT A1B_TXN

C24

PCIE11_T XP/SAT A1B_T XP

E30

PCIE12_RXN/SATA 2_RXN

F30

PCIE12_RXP/SATA2_RXP

A25

PCIE12_T XN/SAT A2_TXN

B25

PCIE12_T XP/SAT A2_TXP

SKL-U_BGA1356

SKL-U

USB2

8 OF20

SSIC / USB3

GPP_E 0/SAT AXPCIE0 /SAT AGP0
GPP_E 1/SAT AXPCIE1 /SAT AGP1
GPP_E2/SATAXPC IE2/SATAGP2

USB3_1_RXN
USB3_1_RXP
USB3_1_TXN
USB3_1_TXP

USB3_2 _RXN / SSIC_R XN

USB3_2 _RXP / SSIC_RXP
USB3_2 _TXN / SSIC_T XN
USB3_2_TXP /SSIC_TXP

USB3_3_RXN
USB3_3_RXP
USB3_3_TXN
USB3_3_TXP

USB3_4_RXN
USB3_4_RXP
USB3_4_TXN
USB3_4_TXP

USB2N_1
USB2P_1

USB2N_3
USB2P_3

USB2N_4
USB2P_4

USB2N_5
USB2P_5

USB2N_6
USB2P_6

USB2N_8
USB2P_8

USB2N_9
USB2P_9

USB2N_10
USB2P_10

USB2_COMP

USB2_ID

USB2_VBUSSENSE

GPP_E9/USB2_OC0#

GPP_E4/DEVSLP0
GPP_E5/DEVSLP1
GPP_E6/DEVSLP 2

GPP_E8/SATALED #

Rev_1.0

H8
G8
C13
D13

J6
H6
B13
A13

J10
H10
B15
A15

E10
F10
C15
D15

AB9
AB10

AD6
AD7

AH3
AJ3

AD9
AD10

AJ1
AJ2

AF6
AF7

AH1
AH2

AF8
AF9

AG1
AG2

AH7
AH8

AB6
AG3
AG4

A9
C9
D9
B9

J1
J2
J3

H2
H3
G4

H1

USB20_N2
USB20_P2

USB20_N3
USB20_P3

USB20_N5
USB20_P5

USB20_N6
USB20_P6

USB20_N7
USB20_P7

USB2_COMP

USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#

RC70

USB3_RX2_N <37>

USB3_RX2_P <37>

USB3_TX2_N <37>

USB3_TX2_P <37>

USB3_RX3_N <37>

USB3_RX3_P <37>

USB3_TX3_N <37>

USB3_TX3_P <37>

USB20_N2 <37>
USB20_P2 <37>

USB20_N3 <37>
USB20_P3 <37>

USB20_N5 <28>
USB20_P5 <28>

USB20_N6 <32>
USB20_P6 <32>

USB20_N7 <33>
USB20_P7 <33>

1

RC104 1 2 1K_0402_5%
RC105 1 2 1K_0402_5%

2 113_0402_1%

USB_OC1# <37>

WL_OFF# <33>

USB2.0 / 3.0 Port (MB - 1)

USB2.0 / 3.0 Port (MB - 2)

USB2.0 / 3.0 Port (MB - 1)

USB2.0 / 3.0 Port (MB - 2)

Camera

Card Reader

NGFF WLAN+BT

USB_OC1#
USB_OC3#
USB_OC0#
USB_OC2#

WL_OFF#

RPC9

18
27
36

5 4

10K_0804_8P4R_5%

RC139 1 @ 2 10K_0402_5%

+3VALW

+3VS

When PCIE8/SATA1A is use d as SATA Port 1 (ODD) , then
PCIE11/SATA1B (M.2 SSD) can not be used as SATA Port 1.

A A

SecuriiityClllassiiifiiicatiiion

Issued Date Decipii hered Date

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL
AND TRADE SECRET IIINFORMATIIION... THIIIS SHEET MA Y NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIIONOF R&D
DEPARTMENT EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IIINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIITCONTAIIINS MAY BE USED

5 4 3 2

BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IIINC...

2018/03/09 2019/03/09

Compal Secret Data

Compal Electronics,Inc.

Tiiitllle

SKL-U(7/12)PCIE,USB,SATA

Siiize Document Number Rev

Custttom 1...0

Date: Friiiday,,, March 09,,,2018

LA-G202P

1

Sheet 12 o f 55

5 4 3 2 1

+1.2V

UC1N @ SKL-U

VDDQ_AU23
VDDQ_AU28
VDDQ_AU35
VDDQ_AU42
VDDQ_BB23
VDDQ_BB32
VDDQ_BB41
VDDQ_BB47
VDDQ_BB51

VDDQC
VCCST

VCCSTG_A22
VCCPLL_OC

VCCPLL_K20
VCCPLL_K21

SKL-U_BGA1356

+1.0V_VCCST

CC128

CPUPOWER3 OF 4

14 OF20

1

2

VCCIO_SENSE
VSSIO_SENSE

VSSSA_SENSE

VCCSA_SENSE

1

CC129
10U_0603_6.3V6M

2

AU23
AU28
AU35
AU42
BB23
BB32
BB41
BB47
BB51

AM40

A18
A22

AL23

K20

K21

10U_0603_6.3V6M

Close to A18 Close to K20 Close to A22

1U_0201_6.3V6M

SE00000UC00

1 0_040 2_5%RC74 2

1 0_040 2_5%RC75 2

0.1U_0201_10V KX5R

1

CC30

2

+VL

12

CC21

1U_0201_6.3V6M

SE00000UC00

+1.0VALW

12

1 0_040 2_5%SUSP# RC81 2

+1.8VALW

@ CC26

+1.0VALW TO +1.0VS_VCCIO

CC32
1U_0201_6.3V6M

SE00000UC00 UC6

D D

+1.0VALW TO +1.0V_VCCST

<36,45> SYSON

<36,40,45> SUSP#

+1.8VALW TO +1.8VS

C C

+VL

@

B B

I(Max) : 0.16 A(+1 .0V_VCCST)
RON(Max) : 25 mo hm
V drop : 0.004 V

12

CC22 @
1U_0201_6.3V6M

SE00000UC00

UC5

1

VOUT1

VIN1

2

VOUT1

EN_1.0V_VCCSTU

EN_1.8VS

12

I(Max) : 3.04 A( +1.0VS_VCCIO)
RON(Max) : 6.2 m ohm
V drop : 0.019 V

1

VIN1

2

VIN2

7

VIN thermal

3

VBIAS

ON

AOZ1334DI-01_DFN 8P

VIN1

3

ON1

4

VBIAS

5

ON2

6

VIN2

VOUT2

7

VIN2

VOUT2

S IC JW7110DFNC#TRPBF DFN14 DUAL LOAD SW

SA0000BEL00

I(Max) : 0.2 A(+1 .8VS)
RON(Max) : 25 mo hm
V drop : 0.005 V

6

VOUT

54

GND

14

13

12 1 2

CT1

11 8200P_0402_25V7K

GND

10 1 2

CT2

9

8

15

GPAD

+1.0VS_VCCIO_STG

+1.0V_VCCST_R

CC24

CC25

1000P_0402_ 50V7K

+1.8VS_R

RC79 1 2 0_0805_5%

2

RC136 0_0402_5%

Follow 543977_SKL_PDDG_Rev0_91
CC24 10PF ->22us(Spec:<= 65us)

2

1

1 RC137

0_0402_5%

+1.0V_VCCST+1.0VALW

+1.8VS

+1.0VS_VCCIO

1

@

0.1U_0201_10V KX5R

2

0.1U_0201_10V KX5R

1

CC23

2

0.1U_0201_10V KX5R

1

CC27

2

+1.0VS_VCCIO

+1.0V_VCCST

Reserved for BSoD 0x124 Issue

CC33

+1.0VS_VCCIO

Rev_1.0

AK28

VCCIO

AK30

VCCIO

AL30

VCCIO

AL42

VCCIO

AM28

VCCIO

AM30

VCCIO

AM42

VCCIO

AK23

VCCSA

AK25

VCCSA

G23

VCCSA

G25

VCCSA

G27

VCCSA

G28

VCCSA

J22

VCCSA

J23

VCCSA

J27

VCCSA

K23

VCCSA

K25

VCCSA

K27

VCCSA

K28

VCCSA

K30

VCCSA

AM23
AM22

VSSSA_SENSE

H21

VCCSA_SENSE

H20

Trace Length Match < 25 mils

+1.0VS_VCCIO

+VCCSA

2 1

BSC SidePSC Side

CC35 @
1U_0201_6.3V6M

SE00000UC00

VSSSA_SENSE <48>
VCCSA_SENSE <48>

+1.0VS_VCCIO +1.2V

CC38 SE00000UC00

CC37 SE00000UC00

10U_0603_6.3V6

M

1

CC36

@

2

A A

5 4 3 2 1

1U_0201_6.3V6

M

1U_0201_6.3V6

M

12

12

PSC SideBSC Side BSC SidePSC Side

CC39 SE00000UC00

1U_0201_6.3V6M

12

12

CC41 SE00000UC00

1U_0201_6.3V6M

CC40 SE00000UC00

1U_0201_6.3V6M @

12

CC42 SE00000UC00

1U_0201_6.3V6M

12

@

@

BSC Side

CC43 SE00000UC00

1U_0201_6.3V6M

1U_0201_6.3V6

M

SE00000UC00

CC29

12

12

Close to CPUUnder CPU

SecuriiityClllassiiifiiicatiiion

IssuedDate

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL AND
TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT B E TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIIONOF R&D
DEPARTMENT EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IIINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIITCONTAIIINS
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IIINC...

2018/03/09 2019/03/09

22U_0603_6.3V6

M

10U_0603_6.3V6

M

1

1

CC44

2

2

Close to CPU Under CPUClose to AL23 Close to AM40

Compal Secret Data

10U_0603_6.3V6

M

1

CC45

CC46

2

Deciiiphered Date

CC49 SE00000UC00

@ 1U_0201_6.3V6M

CC50 SE00000UC00

10U_0603_6.3V6

M

10U_0603_6.3V6

M

1

1

CC47

CC48

@

2

2

@ 1U_0201_6.3V6M

12

12

Compal Electronics,Inc.

Tiiittllle

Siiize Documentt Number

Custttom

Datte:: Friiiday,,, March 09,,,2018 Sheett 13 o ff 55

SKL-U(8/12)Power

LA-G202P

R ev

1...0

5 4 3 2 1

D D

Follow 54 3016_SKL_U_ Y_PDG_1_0

+1.0VALW

LC1

MURATABLM15EG221SN1D

1 2

SM01000BV00 RF@

R_0402

+1.0V_APLL

0.1U_0201_10V KX5R

2

RF@

CC31

1

Follow 543016_SKL_U_Y_PDG_1_0

+1.0V_AMPHYPLL

SE00000UC00

CC58

12

+1.0V_CLK5_F24NS

22U_0603_6.3V6

M

1

1

CC63

@

@

2

+1.0V_CLK4_F100OC

22U_0603_6.3V6

M

1

1

CC69

@

@

2

2

+1.0V_CLK6_24TBT

1U_0201_6.3V6M

CC59 @

22U_0603_6.3V6M

CC64

2

22U_0603_6.3V6M

CC70

+3VALW

LC2

MURATABLM15EG221SN1D

1 2

SM01000BV00 RF@

R_0402

+3V_1.8V_HDA

0.1U_0201_10V KX5R

1

RF@

2

CC66

22U_0603_6.3V6

M

1

@

C C

2

Follow 543016_SKL_U_Y_PDG_1_0

Follow 543016_SKL_U_Y_PDG_1_0

B B

CC51 1 2 1U_0201_6.3V6M

@

CC54 1 2 1U_0201_6.3V6M

@

Imax : 2.57A

CC55 1 2 1U_0201_6.3V6M DCPDSW AL1
CC56 1 2 1U_0201_6.3V6M

Close toK17

CC60 1 2 22U_0603_6.3V6M

Imax : 1.54A

@

CC61 1 2 1U_0201_6.3V6M

Close to P15

+1.0V_AMPHYPLL

+1.0V_APLL

+3VALW

+3V_1.8V_HDA

CC65 1 2 1U_0201_6.3V6M

Close to AF20

@

CC67 1 2 1U_0201_6.3V6M

Close toAJ21

@

CC68 1 2 1U_0201_6.3V6M

Close toN18

Follow 543016_SKL_U_Y_PDG_1_0

22U_0603_6.3V6M

22U_0603_6.3V6

1U_0201_6.3V6M

SE00000UC00

12

1U_0201_6.3V6M

SE00000UC00

CC83 @

CC84 @

12

M

1

CC85

1

CC86

@

@

2

2

+1.0VALW +3VALW +1.8VALW

22U_0603_6.3V6M

22U_0603_6.3V6

M

22U_0603_6.3V6

M

22U_0603_6.3V6

M

1

1

CC72

CC71

@

@

@

2

2

CC74

1

1

CC73

@

2

@

2

SE00000UC00

SE00000UC00

SE00000UC00
SE00000UC00

SE00000UC00

SE00000UC00

SE00000UC00

SE00000UC00

22U_0603_6.3V6M

CC75

1

@

2

+1.0VALW

UC1O

AB19

VCCPRIM_1P0

AB20

VCCPRIM_1P0

P18

VCCPRIM_1P0

AF18

VCCPRIM_CORE

AF19

VCCPRIM_CORE

V20

VCCPRIM_CORE

V21

VCCPRIM_CORE
DCPDSW _1P0

K17

VCCMPHYAO N_1P0

L1

VCCMPHYAO N_1P0

N15

VCCMPHYG T_1P0_ N15

N16

VCCMPHYG T_1P0_ N16

N17

VCCMPHYG T_1P0_ N17

P15

VCCMPHYG T_1P0_ P15

P16

VCCMPHYG T_1P0_ P16

K15

VCCAMPHYP LL_1P0

L15

VCCAMPHYP LL_1P0

V15

VCCAPLL_1P0

AB17

VCCPRIM_1P0_AB17

Y18

VCCPRIM_1P0_Y18

AD17

VCCDSW _3P3_AD17

AD18

VCCDSW _3P3_AD18

AJ17

VCCDSW _3P3_AJ17

AJ19

VCCHDA

AJ16

VCCSPI

AF20

VCCSRAM_1P0

AF21

VCCSRAM_1P0

T19

VCCSRAM_1P0

T20

VCCSRAM_1P0

AJ21

VCCPRIM_3P3_AJ21

AK20

VCCPRIM_1P0_AK20

N18

VCCAPLLEBB_1P0

SKL-U_BGA1356

@

SKL-U

CPUPOWER4 OF 4

15 OF20

VCCPGPPA
VCCPGPPB
VCCPGPPC
VCCPGPPD
VCCPGPPE

VCCPGPPG

VCCPRIM_3P3_V19

VCCPRIM_1P0_T1

VCCATS_1P8

VCCRTCPRIM_3P3

VCCRTC_AK19
VCCRTC_BB14

GPP_B0/CORE_VID0
GPP_B1/CORE_VID1

+1.8VALW

Rev_1.0

VCCPGPPF

DCPRTC

VCCCLK1
VCCCLK2
VCCCLK3
VCCCLK4

VCCCLK5
VCCCLK6

+3VALW

AK15
AG15

Y16
Y15
T16
AF16
AD15

V19

T1

AA1

AK17

AK19

BB14

BB10 DCPRTC CC62 1 2 0.1U_0201_10V K X5R

A14

K19

L21

N20

L19

A10

AN11
AN13

VCCPGPPF support 1.8V only

+1.0VALW

CC57 1 2 1U_0201_6.3V6M

SE00000UC00

+3VL_RTC

+1.0V_CLK6_24TBT

+1.0V_APLL
+1.0V_CLK4_F100OC
+1.0V_CLK5_F24NS
+1.0V_CLK6_24TBT

RTC Battery

22U_0603_6.3V6

M

1

CC76

2

+3VALW

SE00000UC00

12

1U_0201_6.3V6M

SE00000UC00

CC80 @

12

1U_0201_6.3V6M

1U_0201_6.3V6M

SE00000UC00

SE00000UC00

1U_0201_6.3V6

M

CC78 @

CC77 @

12

1

12

CC81

2

Close to AG15 Close to Y16 Close to T16Close to AK17

+3VL_RTC +RTCBATT

W=20mils

0.1U_0201_10V KX5R

CC79

RC90 1 2 0_0402_5%

CC82
1U_0201_6.3V6M

SE00000UC00

2 1

Safty suggestion remove EE side, Keep PWR side

A A

SecuriiityClllassiiifiiicatiiion

IssuedDate

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL AND
TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT B E TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIIONOF R&D
DEPARTMENT EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IIINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIITCONTAIIINS

5 4 3 2 1

MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IIINC...

2018/03/09 2019/03/09

Compal Secret Data

Deciiiphered Date

Compal Electronics,Inc.

Tiiittllle

SKL-U(9/12)Power

Siiize Documentt Number R ev

Custttom

Datte:: Friiiday,,, March 09,,,2018 Sheett

LA-G202P

o ff 55

14

1...0

5 4 3 2 1

D D

+VCCGT +VCCGT

+VCCGT_VCCCORE

+VCCCORE +VCCCORE

C C

T157 TP@
T158 TP@

B B

VCCOPC_SENSE
VSSOPC_SENSE

UC1L

A30

VCC_A30

A34

VCC_A34

A39

VCC_A39

A44

VCC_A44

AK33

VCC_AK33

AK35

VCC_AK35

AK37

VCC_AK37

AK38

VCC_AK38

AK40

VCC_AK40

AL33

VCC_AL33

AL37

VCC_AL37

AL40

VCC_AL40

AM32

VCC_AM32

AM33

VCC_AM33

AM35

VCC_AM35

AM37

VCC_AM37

AM38

VCC_AM38

G30

VCC_G30

K32

RSVD

AK32

RSVD

AB62

VCCOPC_AB62

P62

VCCOPC_P62

V62

VCCOPC_V62

H63

VCC_OPC_1P8_H63

G61

VCC_OPC_1P8_G61

AC63

VCCOPC_SENSE

AE63

VSSOPC_SENSE

AE62

VCCEOPIO

AG62

VCCEOPIO

AL63

VCCEOPIO _SENSE

AJ62

VSSEOPIO_SENSE

SKL-U_BGA1356

@

SKL-U

CPUPOWER1 OF 4

12 OF20

Rev_1.0

VCC_G32
VCC_G33
VCC_G35
VCC_G37
VCC_G38
VCC_G40
VCC_G42

VCC_J30

VCC_J33
VCC_J37
VCC_J40
VCC_K33
VCC_K35
VCC_K37
VCC_K38
VCC_K40
VCC_K42
VCC_K43

VCC_SENSE

VSS_SENSE

VIDALERT #

VIDSCK

VIDSOUT

VCCSTG_G20

G32

G33
G35
G37
G38
G40
G42
J30
J33
J37

J40

K33
K35
K37
K38
K40
K42
K43

E32

E33

SOC_SVID_ALERT#

B63

VR_SVID_CLK

A63

VR_SVID_DATA

D64

ALERT signal must be routed between CLK and DATA signals

G20

Trace Length Match < 25 mils

VCCCORE_SENSE <48>

VSSCORE_SENSE <48>

VR_SVID_CLK <48>

+1.0VS_VCCIO

R416 1 U22@ 2 0_0603_5%

<48> VCCGT_SENSE
<48> VSSGT_SENSE

+VCCG

VCCGT_SENSE
VSSGT_SENSE

Trace Length Match < 25 mils

SVID ALERT

+1.0V_VCCST

Place the PU

resistors close to CPU

12

RC94
56_0402_5%

T_K52

AA63
AA64
AA66
AA67
AA69
AA70
AA71
AC64
AC65
AC66
AC67
AC68
AC69
AC70
AC71

A48

A53
A58
A62
A66

J43
J45
J46
J48
J50
J52
J53
J55
J56
J58

J60
K48
K50

K52

K53
K55
K56
K58
K60

L62

L63

L64

L65

L66

L67

L68

L69

L70

L71

M62

N63
N64
N66
N67
N69

J70
J69

UC1M

VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT

VCCGT_SENSE
VSSGT_SENSE

SKL-U_BGA1356

@

SKL-U

CPUPOWER2 OF 4

13 OF 20

Rev_1.0

VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT

VCCGTX_AK42
VCCGTX_AK43
VCCGTX_AK45
VCCGTX_AK46
VCCGTX_AK48
VCCGTX_AK50
VCCGTX_AK52
VCCGTX_AK53
VCCGTX_AK55
VCCGTX_AK56
VCCGTX_AK58
VCCGTX_AK60
VCCGTX_AK70
VCCGTX_AL43
VCCGTX_AL46
VCCGTX_AL50
VCCGTX_AL53
VCCGTX_AL56
VCCGTX_AL60
VCCGTX_AM48
VCCGTX_AM50
VCCGTX_AM52
VCCGTX_AM53
VCCGTX_AM56
VCCGTX_AM58
VCCGTX_AU58
VCCGTX_AU63
VCCGTX_BB57
VCCGTX_BB66

VCCGT X_SENSE

VSSGTX_SENSE

AL61

N70
N71
R63
R64
R65
R66
R67
R68
R69
R70
R71
T62
U65
U68
U71
W6 3
W6 4
W6 5
W6 6
W6 7
W6 8
W6 9
W7 0
W7 1
Y62

AK42
AK43
AK45
AK46
AK48
AK50
AK52
AK53
AK55
AK56
AK58
AK60
AK70
AL43
AL46
AL50
AL53
AL56
AL60
AM48
AM50
AM52
AM53
AM56
AM58
AU58
AU63
BB57
BB66

AK62

R417 0_0402_5%1 U22@ 2

VCCGTX_SENSE

VSSGTX_SENSE

+VCCGT_VCCCORE

T161 TP@
T162 TP@

+VCCGT

SOC_SVID_ALERT#

SVID DATA

A A

VR_SVID_DATA

1 2

RC95 220_040 2_5%

+1.0V_VCCST

Place the PU
resistors close to C PU

12

RC96
100_0402_1%

5 4 3 2 1

VR_ALERT# <48>

VR_SVID_DATA <48>

(To VR)

(To VR)

SecuriiityClllassiiifiiicatiiion

IssuedDate

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL AND
TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT B E TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIIONOF R&D
DEPARTMENT EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IIINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIITCONTAIIINS
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IIINC...

2018/03/09 2019/03/09

Compal Secret Data

Deciiiphered Date

Compal Electronics,Inc.

Tiiittllle

SKL-U(10/12)Power,SVID

Siiize Documentt Number

Custttom

Datte:: Friiiday,,, March 09,,,2018 Sheett 15 o ff

LA-G202P

Rev

1...0

55

5 4 3 2 1

D D

SKL-U

AT63
AT68
AT71
AU10
AU15
AU20
AU32
AU38

AV68
AV69
AV70

AV71
AW 10
AW 12
AW 14
AW 16
AW 18
AW 21
AW 23
AW 26
AW 28
AW 30
AW 32
AW 34
AW 36
AW 38
AW 41
AW 43
AW 45
AW 47
AW 49
AW 51
AW 53
AW 55
AW 57

AW 6
AW 60
AW 62
AW 64
AW 66

AW 8

AY66

BA10

BA14

BA18

BA23

BA28

BA32

BA36

BA45

AV1

B10
B14
B18
B22
B30
B34
B39
B44
B48
B53
B58
B62
B66
B71

BA1

BA2

F68

UC1Q

VSS
VSS

VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS
VSS

VSS

VSS

VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS

SKL-U_BGA1356

@

GND 2 OF 3

17 OF20

Rev_1.0

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS

BA53
BA57
BA6
BA62
BA66

BB26
BB34

BB38
BB43
BB55
BB6
BB60

BB67
BB70
C1
C25
C5
D10
D11
D14
D18
D22
D25
D26
D30
D34
D39
D44
D45
D47
D48
D53
D58
D6
D62
D66

E15
E21
E50

E53
E56
E6
E65
E71
F1
F13
F2
F22
F23
F27
F28
F32
F33
F35
F37
F38
F4
F40
F42
BA41

BA49

BA71
BB18

BB30

BB64

D69
E11

E18
E46

F8
G10
G22
G43
G45
G48

G5
G52
G55
G58

G6
G60
G63
G66

H15
H18
H71
J11
J13
J25
J28
J32
J35
J38
J42

J8
K16
K18
K22
K61
K63
K64
K65
K66
K67
K68
K70
K71
L11
L16
L17

UC1R

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

SKL-U_BGA1356

@

SKL-U

GND 3 OF 3

18 OF20

Rev_1.0

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

L18
L2
L20
L4
L8
N10
N13
N19
N21
N6
N65
N68
P17
P19
P20
P21
R13
R6
T15
T17
T18
T2
T21
T4
U10
U63
U64
U66
U67
U69
U70
V16
V17
V18
W1 3
W6
W9
Y17
Y19
Y20
Y21

SKL-U

UC1P

A5

VSS

A67

VSS

A70

VSS

AA2

VSS

AA4

VSS

AA65

VSS

AA68

VSS

AB15

VSS

AB16

VSS

AB18

VSS

AB21

VSS

AB8

VSS

AD13

VSS

AD16

VSS

AD19

VSS

AD20

VSS

AD21

VSS

AD62

VSS

AD8

VSS

AE64

VSS

AE65

VSS

AE66

VSS

AE67

C C

B B

AE68
AE69

AF1
AF10
AF15
AF17

AF2

AF4
AF63
AG16
AG17
AG18
AG19
AG20
AG21
AG71
AH13

AH6
AH63
AH64
AH67

AJ15
AJ18
AJ20

AJ4
AK11
AK16
AK18
AK21
AK22
AK27
AK63
AK68
AK69

AK8

AL2

AL28
AL32
AL35
AL38

AL4

AL45
AL48
AL52
AL55
AL58
AL64

VSS
VSS

VSS
VSS
VSS
VSS

VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS

VSS

VSS

VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS

VSS

VSS

VSS

VSS
VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

SKL-U_BGA1356

@

GND 1 OF 3

16 OF20

Rev_1.0

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AL66
AM13
AM21
AM25
AM27

AM46

AM60
AM61
AM68
AM71
AM8
AN20

AN28
AN30
AN32
AN33
AN35
AN37
AN38
AN40
AN42
AN58
AN63
AP10
AP18
AP20
AP23
AP28
AP32
AP35
AP38
AP42
AP58
AP63
AP68
AP70

AR16

AR23
AR28
AR35
AR42
AR43
AR45
AR46
AR48
AR5
AR50
AR52
AR53
AR55
AR58
AR63
AR8
AT2
AT20
AT23
AT28
AT35
AT4
AT42
AT56
AT58

AL65

AM43
AM45

AM55

AN23

AR11
AR15

AR20

A A

SecuriiityClllassiiifiiicatiiion

IssuedDate

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL AND
TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT B E TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIIONOF R&D
DEPARTMENT EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IIINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIITCONTAIIINS

5 4 3 2 1

MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IIINC...

2018/03/09 2019/03/09

Compal Secret Data

Deciiiphered Date

Compal Electronics,Inc.

Tiiitllle

SKL-U(11/12)GND

Siiize Document Number

Custttom

Date: Friiiday,,, March 09,,,2018 Sheet 16 o f 55

LA-G202P

R ev

1...0

5 4 3 2 1

SOC_XTAL24_IN_U42 XTAL24_IN_U42

RC106 U42_EMI@ 33_0201_5%

1 2

AU56

U12
U11
H11

C7

UC1T

RSVD_AW 69
RSVD_AW 68

RSVD_AU56
RSVD_AW 48
RSVD_C7

RSVD_U12
RSVD_U11

RSVD_H11

SKL-U_BGA1356

@

SOC_XTAL24_OUT_U42

SKL-U

SPARE

20 OF20

RSVD_E3
RSVD_C11
RSVD_B11
RSVD_A11
RSVD_D12
RSVD_C12
RSVD_F52

D D

UC1S

E68

CFG[0]

B67

CFG[1]

D65

CFG[2]

D67

CFG[3]

BA70
BA68

G69
G68

H70
G71
H69
G70

AY2
AY1

AL25
AL27

C71

G65

E70
C68
D68
C67
F71

F70

E63
F63

E66
F66

E60

K46
K45

B70
F60
A52

J71
J68

F65

F61
E61

E8

D1
D3

CFG[4]
CFG[5]
CFG[6]

CFG[7]

CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]

CFG[13]

CFG[14]

CFG[15]

CFG[16]

CFG[17]
CFG[18]

CFG[19]

CFG_RCOMP

ITP_PMODE

RSVD_AY2

RSVD_AY1

RSVD_D1

RSVD_D3
RSVD_K46

RSVD_K45
RSVD_AL25

RSVD_AL27
RSVD_C71

RSVD_B70
RSVD_F60
RSVD_A52

RSVD_T P_BA70

RSVD_T P_BA68

RSVD_J71

RSVD_J68

VSS_F65

VSS_G65

RSVD_F6 1

RSVD_E61

SKL-U_BGA1356

@

CFG4

C C

B B

CFG_RCOMP

SKL-U

RESERVED SIGNALS-1

19 OF20

Rev_1.0

RSVD_T P_BB68
RSVD_T P_BB69

RSVD_T P_AK13
RSVD_T P_AK12

RSVD_BB2
RSVD_BA3

RSVD_D5
RSVD_D4
RSVD_B2
RSVD_C2

RSVD_B3
RSVD_A3

RSVD_AW 1

RSVD_E1
RSVD_E2

RSVD_BA4
RSVD_BB4

RSVD_A4
RSVD_C4

RSVD_A69
RSVD_B69

RSVD_AY3

RSVD_D71
RSVD_C70

RSVD_C54
RSVD_D54

VSS_AY71

ZVM#

RSVD_T P
RSVD_TP

MSM#

PROC_SELECT#

BB68

BB69

AK13

AK12

BB2

BA3

AU5

TP5

AT5

TP6

D5

D4

B2

C2

B3

A3

AW 1
E1

E2

BA4

BB4

A4

C4

BB5

TP4

A69

B69

AY3 RC97 1 @2 0_0402_5%
D71

C70

C54

D54

AY4

TP1

BB3

TP2

AY71

AR56

AW 71

AW 70

C64

AP56

SKL_CNL#

PM_MSM#

T185 T P@

1 2

RC99 @ 100K_0 402_5%

+1.0V_VCCST

Follow 544669_SKL_U_DDR3L_RVP7_schematic_rev1.0

+1.8VALW

SE00000UC00

2 1

RC98 1 @ 2 0_0402_5%

RC1021

1U_0201_6.3V6M

CC98 @

SOC_XTAL24_OUT_U42

@ 2 0_0402_ 5%

AW 69
AW 68

AW 48

1 2

RC107 U42_EMI@ 33_0201_5%

Rev_1.0

F6

RSVD_F6

E3
C11

B11

A11

D12
C12
F52

SOC_XTAL24_IN_U42

XTAL24_OUT_U42

U42@

U42@

RC40 1 2 1M_0402_5%

U42@

YC3

24MHZ_18PF_XRCG B24M000F2P51R0

SJ10000UJ00

1

1

27P_0402_50V8J

NC NC

2 4

2

CC126

1

3

3

27P_0402_50V8J

CC52

2

U42@

1

Stuff 100k(RC99) for CannonLake-U
Un-stuff 100k(RC99) for SkyLake-U

1 2

RC100 49.9_0402_1%

1 2

RC101 1K_0402_5%

A A

Displa y Port Presence Strap

CFG4

CFG_RCOMP

CFG4

1 : Disabled;

No Physical Display Port attached to Embedded Display Port

0 : Enabled;

An external Display Port device is connected to the Embedded Display Port

SecuriiityClllassiiifiiicatiiion

IssuedDate

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL AND
TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT B E TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIIONOF R&D
DEPARTMENT EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IIINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIITCONTAIIINS

5 4 3 2 1

MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IIINC...

2018/03/09 2019/03/09

Compal Secret Data

Deciiiphered Date

Tiiitllle

Siiize Document Number

Custttom

Date: Friiiday,,, March 09,,,2018 Sheet 17 o ff 55

Compal Electronics,Inc.

SKL-U(12/12)CFG,RSVD

LA-G202P

Rev

1...0

5 4 3 2 1

Interleaved Memory

+DDR_VRE F_CA

U4

M1

DDR_A_MA0

1

CD271

.047U_0 402_16V7K

SE076473 K80

D D

<7,18,20> DDR_ A_BA0
<7,18,20> DDR_ A_BA1

<7,18> DDR_A_CLK0
<7,18> DDR_A_CLK# 0

<7,18,20> D DR_A_CKE0

<7,20> DDR_A_ODT0

<7,18,20> DD R_A_CS#0

C C

<7,20> M_A_ACT#

<7,20> DDR_A_BG0

<7> DDR_A_ALER T#

<7,20> DDR_A_PAR ITY

DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4

2

DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA1 0
DDR_A_MA1 1
DDR_A_MA1 2
DDR_A_MA1 3
DDR_A_MA1 4

DDR_A_BA0
DDR_A_BA1

DDR_A_C LK0
DDR_A_CLK#0
DDR_A_CKE0

DDR_A_ODT0
DDR_A_CS#0
DDR_A_MA1 6
DDR_A_MA1 5

DDR_A_DQS#0
DDR_A_D QS0
DDR_A_D QS#1
DDR_A_D QS1

MEMRST#

1 2 R U160

240_04 02_1%

M_A_ACT#
DDR_A_B G0

DDR_A_AL ERT#
DDR_A_PARITY

+2.5V

VREFCA

P3

A0

P7

A1

R3

A2

N7

A3

N3

A4

P8

A5

P2

A6

R8

A7

R2

A8

R7

A9

M3

A10/AP

T2

A11

M7

A12/BC

T8

A13

L2

A14/WE

N2

BA0

N8

BA1

E2

DMU/DBIU

E7

DML/DBI L

K7

CK_t

K8

CK_c

K2

CKE

K3

ODT

L7

CS

L8

RAS

M8

CAS

A7

DQS U_c

B7

DQS U_t

F3

DQSL_ c

G3

DQSL_t

P1

RES ET

F9

ZQ

L3

ACT

M2

BG0

N9

TEN

P9

ALERT

T3

PAR

T7

NC

B1

VPP

R9

VPP

96-BALL

SDR AM DDR4

K4AAG165 WB-MCRC C38

@

DDR_A_D13

G2

DQL0

DDR_A_D12

F7

DQL1

DDR_A_D11

H3

DQL2

DDR_A_D8

H7

DQL3

DDR_A_D10

H2

DQL4

DDR_A_D9

H8

DQL5

DDR_A_D14

J3

DQL6

DDR_A_D15

J7

DQL 7

DDR_A_D6

A3

DQU0

DDR_A_D1

B8

DQU1

DDR_A_D7

C3

DQU2

DDR_A_D5

C7

DQU3

DDR_A_D3

C2

DQU4

DDR_A_D4

C8

DQU5

DDR_A_D2

D3

DQU6

DDR_A_D0

D7

DQU7

B3

VDD

B9

VDD

D1

VDD

G7

VDD

J1

VDD

J9

VDD

L1

VDD

L9

VDD

R1

VDD

T9

VDD

A1

VDDQ

A9

VDDQ

C1

VDDQ

D9

VDDQ

F2

VDDQ

F8

VDDQ

G1

VDDQ

G9

VDDQ

J2

VDDQ

J8

VDDQ

B2

VSS

E1

VSS

E9

VSS

G8

VSS

K1

VSS

K9

VSS

M9

VSS

N1

VSS

T1

VSS

A2

VSSQ

A8

VSSQ

C9

VSSQ

D2

VSSQ

D8

VSSQ

E3

VSSQ

E8

VSSQ

F1

VSSQ

H1

VSSQ

H9

VSSQ

+1.2V

Replace with 240 Ohm to SupportDDP@ Replace with 240 Ohm to SupportDDP@ Replace with 240 Ohm to SupportDDP@

RD200 1 @ 2 0_0402_5 %

DDR_A_B G1_R

+DDR_VREF_CA

CD125

.047U_0 402_16V7K

SE076473 K80

<7,18,20> DDR_ A_BA0
<7,18,20> DDR_ A_BA1

<7,18> DDR_A_CLK0
<7,18> DDR_A_CLK# 0

<7,18,20> DD R_A_CKE0

DDR_A_B G1_R <20>

U2

M1

DDR_A_MA0

1

DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4

2

DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA1 0
DDR_A_MA1 1
DDR_A_MA1 2
DDR_A_MA1 3
DDR_A_MA1 4

DDR_A_BA0
DDR_A_BA1

DDR_A_C LK0
DDR_A_CLK#0
DDR_A_CKE0

DDR_A_ODT0
DDR_A_CS#0
DDR_A_MA1 6 DDR_A_MA1 6
DDR_A_MA1 5

DDR_A_DQS#2
DDR_A_D QS2
DDR_A_D QS#3
DDR_A_D QS3

MEMRST# P1

1 2 RU16 1 F9

240_04 02_1%

M_A_ACT#
DDR_A_BG0

DDR_A_AL ERT#
DDR_A_PARITY

+2.5V

VREFCA

P3

A0

P7

A1

R3

A2

N7

A3

N3

A4

P8

A5

P2

A6

R8

A7

R2

A8

R7

A9

M3

A10/AP

T2

A11

M7

A12/BC

T8

A13

L2

A14/WE

N2

BA0

N8

BA1

E2

DMU/DBIU

E7

DML/DBI L

K7

CK_t

K8

CK_c

K2

CKE

K3

ODT

L7

CS

L8

RAS

M8

CAS

A7

DQS U_c

B7

DQS U_t

F3

DQSL_ c

G3

DQSL_t

RES ET

ZQ

L3

ACT

M2

BG0

N9

TEN

P9

ALERT

T3

PAR

T7

NC

B1

VPP

R9

VPP

96-BALL

SDR AM DDR4

K4AAG165 WB-MCRC C38

@

DDR_A_D29

G2

DQL0

DDR_A_D25

F7

DQL1

DDR_A_D27

H3

DQL2

DDR_A_D24

H7

DQL3

DDR_A_D30

H2

DQL4

DDR_A_D28

H8

DQL5

DDR_A_D31

J3

DQL6

DDR_A_D26

J7

DQL 7

DDR_A_D22

A3

DQU0

DDR_A_D17

B8

DQU1

DDR_A_D23

C3

DQU2

DDR_A_D20

C7

DQU3

DDR_A_D19

C2

DQU4

DDR_A_D16

C8

DQU5

DDR_A_D18

D3

DQU6

DDR_A_D21

D7

DQU7

B3

VDD

B9

VDD

D1

VDD

G7

VDD

J1

VDD

J9

VDD

L1

VDD

L9

VDD

R1

VDD

T9

VDD

A1

VDDQ

A9

VDDQ

C1

VDDQ

D9

VDDQ

F2

VDDQ

F8

VDDQ

G1

VDDQ

G9

VDDQ

J2

VDDQ

J8

VDDQ

B2

VSS

E1

VSS

E9

VSS

G8

VSS

K1

VSS

K9

VSS
VSS
VSS
VSS

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

DDR_A_B G1_R DDR_A_B G1_R

M9
N1
T1

A2
A8
C9
D2
D8
E3
E8
F1
H1
H9

+1.2V

RD201 1 @ 2 0_0402_5 %

.047U_0 402_16V7K

SE076473 K80

<7,18,20> DDR_ A_BA0
<7,18,20> DDR_ A_BA1

<7,18> DDR_A_CLK0
<7,18> DDR_A_CLK# 0

<7,18,20> DD R_A_CKE0

<7,18,20> D DR_A_CS#0<7,18,20> D DR_A_CS#0

CD126

+DDR_VREF_CA

1

2

+1.2V+1.2V+1.2V

+2.5V

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA1 0
DDR_A_MA1 1
DDR_A_MA1 2
DDR_A_MA1 3
DDR_A_MA1 4

DDR_A_BA0
DDR_A_BA1

DDR_A_C LK0
DDR_A_CLK#0
DDR_A_CKE0

DDR_A_ODT0
DDR_A_CS#0

DDR_A_MA1 5

DDR_A_DQS#4
DDR_A_D QS4
DDR_A_D QS#5
DDR_A_D QS5

MEMRST# P1

1 2 RU16 2 F9

240_04 02_1%

M_A_ACT#
DDR_A_BG0

DDR_A_AL ERT#
DDR_A_PARITY

U3

M1

VREFCA

P3

A0

P7

A1

R3

A2

N7

A3

N3

A4

P8

A5

P2

A6

R8

A7

R2

A8

R7

A9

M3

A10/AP

T2

A11

M7

A12/BC

T8

A13

L2

A14/WE

N2

BA0

N8

BA1

E2

DMU/DBIU

E7

DML/DBI L

K7

CK_t

K8

CK_c

K2

CKE

K3

ODT

L7

CS

L8

RAS

M8

CAS

A7

DQS U_c

B7

DQS U_t

F3

DQSL_ c

G3

DQSL_t

RES ET

ZQ

L3

ACT

M2

BG0

N9

TEN

P9

ALERT

T3

PAR

T7

NC

B1

VPP

R9

VPP

96-BALL

SDR AM DDR4

K4AAG165 WB-MCRC C38

@

+DDR_VREF_CA

DDR_A_D43

G2

DQL0

DDR_A_D40

F7

DQL1

DDR_A_D42

H3

DQL2

DDR_A_D41

H7

DQL3

DDR_A_D47

H2

DQL4

DDR_A_D45

H8

DQL5

DDR_A_D46

J3

DQL6

DDR_A_D44

J7

DQL 7

DDR_A_D38

A3

DQU0

DDR_A_D37

B8

DQU1

DDR_A_D35

C3

DQU2

DDR_A_D32

C7

DQU3

DDR_A_D33

C2

DQU4

DDR_A_D36

C8

DQU5

DDR_A_D39

D3

DQU6

DDR_A_D34

D7

DQU7

B3

VDD

B9

VDD

D1

VDD

G7

VDD

J1

VDD

J9

VDD

L1

VDD

L9

VDD

R1

VDD

T9

VDD

A1

VDDQ

A9

VDDQ

C1

VDDQ

D9

VDDQ

F2

VDDQ

F8

VDDQ

G1

VDDQ

G9

VDDQ

J2

VDDQ

J8

VDDQ

B2

VSS

E1

VSS

E9

VSS

G8

VSS

K1

VSS

K9

VSS

M9

VSS

N1

VSS

T1

VSS

A2

VSSQ

A8

VSSQ

C9

VSSQ

D2

VSSQ

D8

VSSQ

E3

VSSQ

E8

VSSQ

F1

VSSQ

H1

VSSQ

H9

VSSQ

+1.2V

RD202 1 @ 2 0_0402_5 %

CD127

.047U_0 402_16V7K

SE076473 K80

<7,18,20> DDR _A_BA0
<7,18,20> DDR _A_BA1

<7,18> DDR_A_CLK0
<7,18> DDR_A_CLK# 0

<7,18,20> DD R_A_CKE0

<7,18,20> D DR_A_CS#0

DDR_A_MA0

1

DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4

2

@

DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA1 0
DDR_A_MA1 1
DDR_A_MA1 2
DDR_A_MA1 3
DDR_A_MA1 4

DDR_A_BA0
DDR_A_BA1

+1.2V

DDR_A_C LK0
DDR_A_CLK#0
DDR_A_CKE0

DDR_A_ODT0
DDR_A_CS#0
DDR_A_MA1 6
DDR_A_MA1 5

DDR_A_DQS#6
DDR_A_D QS6
DDR_A_D QS#7
DDR_A_D QS7

MEMRST#

1 2 R U163

240_04 02_1%

M_A_ACT#
DDR_A_BG0

DDR_A_AL ERT#
DDR_A_PARITY

+2.5V

U1

M1

VREFCA

P3

A0

P7

A1

R3

A2

N7

A3

N3

A4

P8

A5

P2

A6

R8

A7

R2

A8

R7

A9

M3

A10/AP

T2

A11

M7

A12/BC

T8

A13

L2

A14/WE

N2

BA0

N8

BA1

E2

DMU/DBIU

E7

DML/DBI L

K7

CK_t

K8

CK_c

K2

CKE

K3

ODT

L7

CS

L8

RAS

M8

CAS

A7

DQS U_c

B7

DQS U_t

F3

DQSL_ c

G3

DQSL_t

P1

RES ET

F9

ZQ

L3

ACT

M2

BG0

N9

TEN

P9

ALERT

T3

PAR

T7

NC

B1

VPP

R9

VPP

96-BALL

SDR AM DDR4

K4AAG165 WB-MCRC C38

@

DDR_A_D60

G2

DQL0

DDR_A_D61

F7

DQL1

DDR_A_D62

H3

DQL2

DDR_A_D57

H7

DQL3

DDR_A_D58

H2

DQL4

DDR_A_D56

H8

DQL5

DDR_A_D59

J3

DQL6

DDR_A_D63

J7

DQL 7

DDR_A_D50

A3

DQU0

DDR_A_D52

B8

DQU1

DDR_A_D51

C3

DQU2

DDR_A_D48

C7

DQU3

DDR_A_D54

C2

DQU4

DDR_A_D53

C8

DQU5

DDR_A_D55

D3

DQU6

DDR_A_D49

D7

DQU7

B3

VDD

B9

VDD

D1

VDD

G7

VDD

J1

VDD

J9

VDD

L1

VDD

L9

VDD

R1

VDD

T9

VDD

A1

VDDQ

A9

VDDQ

C1

VDDQ

D9

VDDQ

F2

VDDQ

F8

VDDQ

G1

VDDQ

G9

VDDQ

J2

VDDQ

J8

VDDQ

B2

VSS

E1

VSS

E9

VSS

G8

VSS

K1

VSS

K9

VSS

M9

VSS

N1

VSS

T1

VSS

A2

VSSQ

A8

VSSQ

C9

VSSQ

D2

VSSQ

D8

VSSQ

E3

VSSQ

E8

VSSQ

F1

VSSQ

H1

VSSQ

H9

VSSQ

+1.2V

Replace with 240 Ohm to SupportDDP@

RD203 1 @ 2 0_0402_5 %

DDR_A_B G1_R

<7,20> DDR_A_MA[0..16]

<7> DDR_A_DQS#[0..7]

<7> DDR_A_DQS[0..7]

<7> DDR_A_D[0..63]

B B

CLOCKTERMINATION

+0.6VS

DDR_A_C LK0

RU166 1 2 36_0402_1%

DDR_A_CLK#0

DDR_A_CLK0

DDR_A_C LK#0

DDR_A_AL ERT#

<7,19> DDR_DRAMRST#

A A

RU167 1 2 36_0402_1%

1

@

CD273
3300P_0402_50V7K

2

RD41 2

1 4 9.9_0 402_1%

DDR_DRAMR ST#

RD46 1 @ 2 0_0402_5% MEMR ST#

5 4 3 2 1

+1.2V

1

CD36
100P_0201_25 V8J

2

@

Co-lay for SDP / DDP Memory DIE

DDR_A_B G1_R

<7> +0.6V_A_VR EFCA

DDP@

RD204 1 2 0_04 02_5%

RD205 1 @ 2 0_04 02_5%

1

CD24

0.022U_ 0402_16V7K

2

12

RD11

2.7_04 02_1%

2

RD13

24.9_0402 _1%

For SDP@

1

DDR_A_B G1 <7>

+1.2V

1 2

1 2

RD195

1.8K_ 0402_1%

RD210

1.8K_04 02_1%

+DDR_VREF_CA

On Board RAM - DataMapping

DQ

U4
DQL0

D13

DQL1

D12

DQL2

D11
DQL3 D8 DQL3
DQL4

D10
DQL5 D9 DQL5
DQL6

D14
DQL7

D15
DQU0 D6 D QU0
DQU1 D1 D QU1
DQU2 D7 D QU2
DQU3 D5 D QU3
DQU4 D3 D QU4
DQU5 D4 D QU5
DQU6 D2 D QU6
DQU7 D0 D QU7

Securiiittty Clllassiiifffiiicatttiiion

IIIssued Dattte

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL AND TRADE
SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIION OF R&D DEPARTMENT EXCEPT
AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IIINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIITCONTAIIINS
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IIINC...

2018/03/09////

Compalll Secret Data

Decipii he red Dattte

U2
DQL0
DQL1
DQL2

DQL4

DQL6
DQL7

DQ
D29
D25
D27
D24
D30
D28
D31
D26
D22
D17
D23
D20
D19
D16
D18
D21

2019///03///09

U3
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

DQ

U1
DQL0

D43

DQL1

D40

DQL2

D42

DQL3

D41

DQL4

D47

DQL5

D45

DQL6

D46

DQL7

D44

DQU0

D38

DQU1

D37

DQU2

D35

DQU3

D32

DQU4

D33

DQU5

D36

DQU6

D39

DQU7

D34

Tiiitttllle

DDR4 ON BOARD CHIPS

Siiize Documenttt Numberrr

Custttom LA---G201P

DQ
D60
D61
D62
D57
D58
D56
D59
D63
D50
D52
D51
D48
D54
D53
D55
D49

Rev

Sheettt 18 o fff55Dattte::: Frrriiiday,,, Marrrch 09,,,2018

1...0

A

<7> DDR_B_DQS#[0..7]

<7> DDR_B_D[0..63]

<7> DDR_B_DQS[0..7]

<7> DDR_B_MA[0..16]

<7> DDR_B_BA0
<7> DDR_B_B A1
<7> DDR_B_BG0
<7> DDR_B_BG1

<7> DDR_B_CLK0

1 1

2 2

<7> DDR_B_CLK# 0
<7> DDR_B_CLK1

<7> DDR_B_CLK# 1

<7> DDR_B_CKE0

<7> DDR_B_C KE1

<7> DDR_B_CS#0
<7> DDR_B_CS#1

<8> SOC _SMBDATA
<8> SOC _SMBCLK

<7> DDR_B_OD T0
<7> DDR_B_OD T1

Layout Note:
Place near JDIMM1

+1.2V

1U_020 1_6.3V6M

1U_020 1_6.3V6M

SE000 00UC00

SE00000UC00

SE00000UC00

12

12

CD4

CD5

4 as near side of th e DIMM clo se to VDD pins

+1.2V

10U_0603_6.3V6M

10U_06 03_6.3V6M

10U_06 03_6.3V6M

1 1 1 1 1 1 1 1

CD11

CD10 @

2 2 2 2 2 2 2 2

Place thes e caps on the VT T plane clos e to DIM M

+0.6VS

1U_0201_6.3V6M

SE000 00UC00

SE000 00UC00

12

12

CD30

3 3

DDR_B_BA0
DDR_B_BA1
DDR_B_BG0
DDR_B_BG1

DDR_B_C LK0
DDR_B_CLK#0
DDR_B_C LK1
DDR_B_CLK#1

DDR_B_CKE0
DDR_B_CKE1
DDR_B_CS#0
DDR_B_CS#1

SOC_SMB DATA

SOC_SMB CLK

DDR_B_ODT0
DDR_B_ODT1

Note:
Check voltage to lerance of
VREF_DQ at the D IMM sock et

1U_020 1_6.3V6M

1U_020 1_6.3V6M

1U_020 1_6.3V6M

SE00000UC00

12

CD6

10U_0603_6.3V6M

CD13

CD12

1U_0201_6.3V6M

SE000 00UC00

CD31

SE00000UC00

SE00000UC00

12

12

10U_0603_6.3V6M

12

12

CD7

CD8

10U_0603_6.3V6M

10U_06 03_6.3V6M

CD14

CD19 @

1U_0201_6.3V6M

1U_0201_6.3V6M

SE000 00UC00

12

CD32 @

CD33 @

1U_020 1_6.3V6M

10U_0603_6.3V6M

CD15

1U_0201_6.3V6M

1U_020 1_6.3V6M

SE00000UC00

SE00000UC00

12

12

CD17

CD9

10U_06 03_6.3V6M

CD18

CD20

+3VS

10U_06 03_6.3V6M

1

1

CD23 @

CD22

2

2

1

C2142

2.2U_0 402_6.3V6 M

2

close to DIMM

+2.5V

10U_06 03_6.3V6M

4 4

2

1

@ C2140

12

CD29
1U_020 1_6.3V6M

SE000 00UC00

+3VS_DIMM

1

CD28

0.1U_02 01_10V6K

2

B

C

D

E

Reverse Type

+1.2V +1.2V

DDR_B_DQS#1
DDR_B_D QS1

DDR_B_D13

DDR_B_D12

DDR_B_D1

DDR_B_D5

DDR_B_D2 DDR_ B_ D7

DDR_B_DQS#2
DDR_B_D QS2

DDR_B_D23

DDR_B_D22

DDR_B_D29

DDR_B_D25

DDR_B_D30 DDR_B_D31

DDR_B_D26 DDR_B_D27

@

1 2

RD1615240_20402_1%
RD166 @ 240_040 2_1%

DDR_B_CKE0 DDR_B_CKE1

DDR_B_B G1
DDR_B_B G0

DDR_B_MA9

DDR_B_MA8
DDR_B_MA6

DDR_B_MA1

DDR_B_CLK0

<7> D DR_B_PARI TY

+2.5V

DDR_B_C LK#0

DDR_B_BA1

DDR_B_CS#0
DDR_B_MA1 4

DDR_B_O DT0
DDR_B_CS#1

DDR_B_O DT1

DDR_B_DQS#4
DDR_B_D QS4

DDR_B_D38

DDR_B_D34

DDR_B_D44

DDR_B_D40

DDR_B_D43 DDR_B_D47

DDR_B_D42 DDR_B_D46

DDR_B_D52 DDR_B_D53

DDR_B_DQS#6
DDR_B_D QS6

DDR_B_D55

DDR_B_D50

DDR_B_D61

DDR_B_D56

DDR_B_D59

DDR_B_D58 DDR_B_D62

SOC_SMB CLK
+3VS_DI MM

JDIMM1

1 2

VSS
DQ5
VSS
DQ1
VSS
DQS0 _C DM0 */DBI0*
DQS 0_T
VSS
DQ7
VSS
DQ3
VSS
DQ1 3
VSS
DQ9

VSS

DM1*/DB I1* DQS1_ T

VSS VSS
DQ1 5
VSS
DQ1 0

VSS

DQ2 1
VSS
DQ1 7

VSS

DQS2 _C DM2*/DBI 2*

DQS2 _T VS S

VSS

DQ2 3
VSS
DQ1 9

VSS

DQ2 9
VSS
DQ2 5

VSS

DM3*/DB I3* DQS 3_ T

VSS

DQ3 0

VSS

DQ2 6

VSS

CB5_NC

VSS

CB1_NC

VSS VSS

DQS8 _C DM8*/DBI 8*

DQS8 _T VS S

VSS

CB2_NC

VSS

CB3_NC

VSS

CKE 0

VDD1

BG1

BG0

VDD3

A12

A9

VDD5

A8

A6

VDD7

A3

A1

VDD9

CK0_T

CK0_C

VDD11

PARITY

BA1

VDD13

S0*

A14_W E* A16_ RAS*

VDD15

ODT0

S1*

VDD17

ODT1

VDD19

S3*/C 1

VSS

DQ3 7

VSS

DQ3 3

VSS

DQS4 _C DM4 */DBI4*

DQS 4_T

VSS

DQ3 8

VSS

DQ3 4

VSS

DQ4 4

VSS

DQ4 0

VSS

DM5*/DB I5* DQS 5_ T

VSS

DQ4 6

VSS

DQ4 2

VSS

DQ5 2

VSS

DQ4 9

VSS

DQS6 _C DM6 */DBI6*

DQS 6_T

VSS

DQ5 5

VSS

DQ5 1

VSS

DQ6 1

VSS

DQ5 6

VSS

DM7*/DB I7* DQS 7_ T

VSS

DQ6 2

VSS

DQ5 8

VSS

SCL

VDDS PD

VPP1

VPP2

FOX_AS0A827-H2SB- 7H

LTCX00 69FA0

ME@

DQ4
VSS
DQ0
VSS

DQ1 2

DQS 1_C

DQ1 4

DQ1 1

DQ2 0

DQ1 6

DQ2 2

DQ1 8

DQ2 8

DQ2 4

DQS 3_C

DQ3 1

DQ2 7

CB4 _NC

CB0 _NC

CB6 _NC
CB7 _NC
RES ET*

CKE 1
VDD2

ACT*

ALERT*

VDD4

VDD6
A5 A4
VDD8

EVENT*

VDD10
CK1_T
CK1_C
VDD12

A10_AP

VDD14

VDD16

A15_CAS *

VDD18
S2*/C0

VREFCA

DQ3 6

DQ3 2

DQ3 9

DQ3 5

DQ4 5

DQ4 1

DQS 5_C

DQ4 7

DQ4 3

DQ5 3

DQ4 8

DQ5 4

DQ5 0

DQ6 0

DQ5 7

DQS 7_C

DQ6 3

DQ5 9

GND
GND

VSS

VSS

DQ6

VSS

DQ2

VSS

VSS

DQ8

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS
VSS

116
118

A11

A7

A2

A0

BA0

A13

162
164

SA2
VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS
SDA
SA0
VTT
SA1

3 4
5 6
7 8

9
11
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77 78
79 80
81
83 84
85 86
87
89
91
93
95
97
99

101
103
105
107
109
111 112
113
115
117
119 120
121 122
123 124
125 126
127 128
129 130
131 132
133
135
137 138
139 140
141 142
143

145 146
147 148
149
151
153 154
155 156
157
159
161
163

167
169 170
171 172
173 174
175
177
179 180
181 182
183 184
185 186
187 188
189 190
191 192
193 194
195 196
197
199
201 202
203 204
205 206
207
209
211
213
215
217
219
221
223
225
227
229
231
233
235
237
239
241
243
245
247
249
251
253
255
257
259

DDR_B_D11DDR_B_D14

DDR_B_D10DDR_B_D15

10
12

DDR_B_D8

DDR_B_D9

DDR_B_D4

DDR_B_D0

DDR_B_DQS#0

32

DDR_B_D QS0

34
36

DDR_B_D6DDR_B_D3

38
40
42
44

DDR_B_D20DDR_B_D21

46
48

DDR_B_D16DDR_B_D17

50
52
54
56

DDR_B_D19

58
60

DDR_B_D18

62
64

DDR_B_D28

66
68

DDR_B_D24

70
72

DDR_B_DQS#3

74

DDR_B_D QS3

76

82

88
90
92
94

96
98

100

102
104
106
108
110

114

DDR_B_MA1 1DDR_B_MA12
DDR_B_MA7

DDR_B_MA5
DDR_B_MA4

DDR_B_MA2DDR_B_MA3

134
136

DDR_B_CLK1

DDR_B_C LK#1

DDR_B_MA0

144

DDR_B_MA1 0

DDR_B_BA0

150

DDR_B_MA1 6

152

DDR_B_MA1 5

DDR_B_MA1 3

158
160

DDR_B_SA2

166165
168

DDR_B_D36DDR_B_D37

DDR_B_D32DDR_B_D33

176
178

DDR_B_D39

DDR_B_D35

DDR_B_D45

DDR_B_D41

DDR_B_DQS#5

198

DDR_B_D QS5

200

208
210
212
214

DDR_B_D48DDR_B_D49

216
218
220
222

DDR_B_D54

224
226

DDR_B_D51

228
230

DDR_B_D60

232
234

DDR_B_D57

236
238

DDR_B_DQS#7

240

DDR_B_D QS7

242
244

DDR_B_D63

246
248
250
252

SOC_SMBDATA

254

DDR_B_S A0

256
258

DDR_B_SA1

260

261
262

DDR_DRAMR ST#_R

M_B_ACT# <7>

DDR_B_AL ERT# <7>

+DIMM_VR EF_DQ

+0.6VS

1

CD34

0.1U_02 01_10V6K

@

2

JDIMM1 ADDRESS PLACE CLOSE TO DIMM

<7> +0.6V_B_ VREFDQ

DDR_DRAMR ST#_R

(

DDR_B_SA2

2-3A to 1 DIMMs/channel

CD21

1

2

12

RD10
2_0402 _1%

RD12

24.9_0402 _1%

+1.2V

12

20mil

0.022U_0 402_16V7K

RD45 1 @ 2 0_040 2_5%

)

+3VS +3VS

RD108

@

0_040 2_5%

1 2

DDR_B_SA1

12

RD138

0_0402 _5%

@

12

RD43
470_04 02_1%

0_0402 _5%

+1.2V

1 2

1 2

RD139

RD194
1K_0402 _1%

RD199
1K_0402 _1%

DDR_DRAMR ST# <7,18>

@

1 2

12

@

0_040 2_5%

+DIMM_VR EF_DQ

DDR_B_SA0

RD140

Securiiittty Clllassiiifffiiicatttiiion

IIIssued Dattte

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL AND TRADE
SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIION OF R&D DEPARTMENT EXCEPT
AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IIINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIITCONTAIIINS

A

B

C

MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IIINC...

2018/03/09////

Compalll Secret Data

Decipii he red Dattte

D

2019///03///09

Compal Electronics,Inc.

Tiiitttllle

Siiize Documenttt Numberrr

Custttom

LA-G202P

DDR4_DIMM

E

Rev

Sheettt 19 offf 55Dattte::: Frrriiiday,,, Marrrch 09,,,2018

1...0

1 2 3 4 5

PLT_RST_VGA_MON# PLT_RST_VGA#
CLKREQ_PCIE#0_R

PCIE CLK

A A

PCIE X4 Bus

B B

Reset Control

<10> CLK_PEG_VGA
<10> CLK_PEG_VGA#

<12> PCIE_PRX_DTX_P1
<12> PCIE_PRX_DTX_N1

<12> PCIE_PTX_C_DRX_P1
<12> PCIE_PTX_C_DRX_N1

<12> PCIE_PRX_DTX_P2
<12> PCIE_PRX_DTX_N2

<12> PCIE_PTX_C_DRX_P2
<12> PCIE_PTX_C_DRX_N2

<12> PCIE_PRX_DTX_P3
<12> PCIE_PRX_DTX_N3

<12> PCIE_PTX_C_DRX_P3
<12> PCIE_PTX_C_DRX_N3

<12> PCIE_PRX_DTX_P4
<12> PCIE_PRX_DTX_N4

<12> PCIE_PTX_C_DRX_P4
<12> PCIE_PTX_C_DRX_N4

PCIE_PRX_DTX_P1
PCIE_PRX_DTX_N1

PCIE_PTX_C_DRX_P1
PCIE_PTX_C_DRX_N1

PCIE_PRX_DTX_P2
PCIE_PRX_DTX_N2

PCIE_PTX_C_DRX_P2
PCIE_PTX_C_DRX_N2

PCIE_PRX_DTX_P3
PCIE_PRX_DTX_N3

PCIE_PTX_C_DRX_P3
PCIE_PTX_C_DRX_N3

PCIE_PRX_DTX_P4
PCIE_PRX_DTX_N4

PCIE_PTX_C_DRX_P4
PCIE_PTX_C_DRX_N4

+3VS

5

1

<10,31,33,36> PCI_RST#

(From PCH)

<11> DGPU_HOLD_RST#

<24> PLT_RST_VGA_HOLD#

(From GPU)

C C

CLK_REQ

IN1

2

OUT

IN2

GND VCC

DIS@

3

+3VS_DGPU

12

RV17
10K_0402_5%

DIS@

RV3791 2 0_0402_5%

NOGC6@

CV11 DIS@ 1 2 0.22U_0402_6.3V6K
CV12 DIS@ 1 2 0.22U_0402_6.3V6K

CV13 DIS@ 1 2 0.22U_0402_6.3V6K
CV14 DIS@ 1 2 0.22U_0402_6.3V6K

CV15 DIS@ 1 2 0.22U_0402_6.3V6K
CV16 DIS@ 1 2 0.22U_0402_6.3V6K

CV17 DIS@ 1 2 0.22U_0402_6.3V6K
CV18 DIS@ 1 2 0.22U_0402_6.3V6K

UV12
MC74VHC1G08DFT2G_SC70-5

4

+3VS_DGPU_AON

5

1

IN1

OUT

2

IN2

GND VCC

GC6@

3

PCIE_PRX_C_DTX_P1
PCIE_PRX_C_DTX_N1

PCIE_PRX_C_DTX_P2

PCIE_PRX_C_DTX_N2

PCIE_PRX_C_DTX_P3
PCIE_PRX_C_DTX_N3

PCIE_PRX_C_DTX_P4
PCIE_PRX_C_DTX_N4

PLT_RST_VGA_MON# <24>

UV15
MC74VHC1G08DFT2G_SC70-5

PLT_RST_VGA#

4

12

RV378
10K_0402_5%

DIS@

Near UV 1

RV16 1 @ 2 0_0402_5%

+3VS_DGPU_AON

RV68

10K_0402_5%

DIS@

CLKREQ_PCIE#0_R

D D

12

1U_0201_6.3V6M

SE00000UC00

CV121 @

12

VGS(Max) : 2.5 V

RV375 1 @ 2 0_0402_5%

2

QV3

G

2N7002K_SOT23-3

D

S

DIS@

VGA_CLKREQ#

13

12

RV18
10K_0402_5%

@

VGA_CLKREQ# <10>

(To SOC)

UV1A

COMMON

1/14PCI_EXPRESS

AB6

PEX_WAKE#

AC7

PE X_ RST #

AC6

PE X_ CLK REQ #

AE8

PE X_ REF CLK

AD8

PE X_ REF CLK #

AC9

PE X_ TX0

AB9

PE X_ TX0 #

AG6

PE X_ RX0

AG7

PE X_ RX0 #

AB10

PE X_ TX1

AC10

PE X_ TX1 #

AF7

PE X_ RX1

AE7

PE X_ RX1 #

AD11

PE X_ TX2

AC11

PE X_ TX2 #

AE9

PE X_ RX2

AF9

PE X_ RX2 #

AC12

PE X_ TX3

AB12

PE X_ TX3 #

AG9

PE X_ RX3

AG10

PE X_ RX3 #

AB13

PE X_ TX4

AC13

PE X_ TX4 #

AF10

PE X_ RX4

AE10

PE X_ RX4 #

AD14

PE X_ TX5

AC14

PE X_ TX5 #

AE12

PE X_ RX5

AF12

PE X_ RX5 #

AC15

PE X_ TX6

AB15

PE X_ TX6 #

AG12

PE X_ RX6

AG13

PE X_ RX6 #

AB16

PE X_ TX7

AC16

PE X_ TX7 #

AF13

PE X_ RX7

AE13

PE X_ RX7 #

AD17

PE X_ TX8

AC17

PE X_ TX8 #

AE15

PE X_ RX8

AF15

PE X_ RX8 #

AC18

PE X_ TX9

AB18

PE X_ TX9 #

AG15

PE X_ RX9

AG16

PE X_ RX9 #

AB19

PEX_TX 10

AC19

PEX_TX 10#

AF16

PE X_ RX1 0

AE16

PE X_ RX1 0#

AD20

PE X_ TX1 1

AC20

PE X_ TX1 1#

AE18

PE X_ RX1 1

AF18

PE X_ RX11 #

AC21

PE X_ TX1 2

AB21

PE X_ TX1 2#

AG18

PE X_ RX1 2

AG19

PE X_ RX1 2#

AD23

PE X_ TX1 3

AE23

PE X_ TX1 3#

AF19

PEX_RX13

AE19

PE X_ RX1 3#

AF24

PE X_ TX1 4

AE24

PE X_ TX1 4#

AE21

PE X_ RX1 4

AF21

PE X_ RX14 #

AG24

PE X_ TX1 5

AG25

PE X_ TX1 5#

AG21

PE X_ RX1 5

AG22

PE X_ RX1 5#

N16S-GT-S-A2_BGA595

@

NC FOR GM108

NC FOR GF117/GK208/GM108

PE X_ IOV DD
PE X_ IOV DD
PE X_ IOV DD
PE X_ IOV DD
PE X_ IOV DD
PE X_ IOV DD

PE X_ IOV DDQ
PE X_ IOV DDQ
PE X_ IOV DDQ
PE X_ IOV DDQ
PE X_ IOV DDQ
PE X_ IOV DDQ
PE X_ IOV DDQ
PE X_ IOV DDQ
PE X_ IOV DDQ
PE X_ IOV DDQ
PE X_ IOV DDQ
PE X_ IOV DDQ
PE X_ IOV DDQ
PE X_ IOV DDQ

NC FOR GF119

PE X_ PLL _HV DD
PE X_ PLL _HV DD

PE X_ SVD D_3 V3

VD D_ SEN SE

GND _S EN SE

PE X_ TST CLK _O UT
PE X_ TST CLK _O UT#

PE X_ PLL VDD
PE X_ PLL VDD

TES TM OD E

PE X_ TER MP

AB23
AC24
AD25

AE26

AE27

AA10
AA12
AA13
AA16
AA18
AA19
AA20

AC23
AD24
AE25
AF26
AF27

F2

F1

AA8
AA9

AF25

AB8

AA22

AA21
AB22

AF22
AE22

AA14
AA15

AD9

Place near
ball s

1U_0201_6.3V6M

SE00000UC00

2 1

Place near
ball s

SE00000UC00

2 1

VDD_SENSE_GPU

GND_SENSE_GPU

PEX_PLL_CLK_OUT
PEX_PLL_CLK_OUT#

PEX_PLLVDD_GPU

GPU_TESTMODE

PEX_TERMP

1U_0201_6.3V6M

SE00000UC00

CV202 DIS@

CV205 @

2 1

1U_0201_6.3V6M

1U_0201_6.3V6M

SE00000UC00

CV201 @

CV200 @

2 1

Place near BGA

0.1U_0201_10V6K

4.7U_0402_6.3V6

M

CV207 DIS@

CV5 DIS@

1

1

1

2

2

2

RV4 2 @ 1200_0402_1%

GPU_TESTMODE <24><25,26,51> DGPU_PWROK

12

RV376

2.49K_0402_1%

DIS@

Place near BGA

4.7U_0402_6.3V6

M

10U_0603_6.3V6M

CV2 DIS@

CV199 @

1

1

2

2

4.7U_0402_6.3V6M

1

2

1

2

Place near BGA

+1.0VS_DGPU

1.0V

10U_0603_6.3V6M

CV3 @

22U_0603_6.3V6M

22U_0603_6.3V6M

CV204 @

1

2

CV7 @

1

1

CV9 @

2

2

1.0V

10U_0603_6.3V6M

10U_0603_6.3V6M

22U_0603_6.3V6M

CV203 DIS@

CV198 @

1

1

2

2

+1.0VS_DGPU

22U_0603_6.3V6M

1

CV10 @

CV8 DIS@

2

+3VS_DGPU_AON

4.7U_0402_6.3V6M
CV4 DIS@

VDD_SENSE_GPU <51>

GND_SENSE_GPU <51>

Place near BALL Place near BGA

To POWER

trace width: 16mils
differential voltage sens ing.
differential signal routing.

1.0V

0.1U_0201_10V6K

1

2

1U_0201_6.3V6M

SE00000UC00

CV208 DIS@

12

4.7U_0402_6.3V6

M

1

CV206 DIS@

2

RV377 1 2 0_0402_5%

CV6 DIS@

+1.0VS_DGPU

SecuriiityClllassiiifiiicatiiion

Issued Date Decipii hered Date

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL AND
TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT B E TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIIONOF R&D
DEPARTMENT EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IIINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIITCONTAIIINS

1 2 3 4 5

MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IIINC...

2018/03/09 2019/03/09

Compal Secret Data

Tiiitllle

NV(1/5)-PCIE

Siiize Document Number

LA-G202P

Compal Electronics, Inc.

R ev

1...0

Sheet 21 o f 55Date: Friiiday,,, March 09,,,2018

1 2 3 4 5

UV1H
UV1G

COMMON

4/14IFPAB

AA6

UV1J

COMMON

7/14IFPEF

IFPEF_ PLLV DD

IFPEF_ PLLV DD

IFPEF_RSET

IFPAB_RSET

V7

IFPAB_P LLVD D

W 7

IFPAB_P LLVD D

W 6

IFPA _IOV DD

Y6

IFPB _IOV DD

IFPAB

N16S-GT-S-A2_BGA595

@

A A

B B

J7

K7

K6

C C

IFPE

H6

IFPE _IOV DD

J6

IFPF _IOV DD

IFPF

D D

N16S-GT-S-A2_BGA595

@

IFPA/B

AC4

IFPA_T XC#

AC3

IFP A_ TX C

Y3

IFPA_T XD0#

Y4

IFP A_ TX D0

AA2

IFPA_T XD1#

AA3

IFP A_ TX D1

AA1

IFPA_T XD2#

AB1

IFP A_ TX D2

AA5

IFPA _TX D3#

AA4

IFP A_ TX D3

AB4

GF117

IFPB_T XC#

AB5

IFP B_ TX C

AB2

IFPB_T XD4#

AB3

IFP B_ TX D4

NC FOR GF117/GM108

AD2

IFPB_T XD5#

AD3

IFP B_ TX D5

AD1

IFPB_T XD6#

AE1

IFP B_ TX D6

AD5

IFPB _TX D7#

AD4

IFP B_ TX D7

B3

GP IO1 4

NC

NC FOR GF117/GM108

UV1K

COMMON

3/14DACA

W 5

DA CA _VD D

AE2

DA CA _VR EF

AF2

DA CA _RSET

N16S-GT-S-A2_BGA595

@

+1.0VS_DGPU

1V

IFPE/F

GF119/GK208
DVI-DL DVI-SL/HDM I DP
I2CY_SDA

I2CY_SCL

TXC
TXC

TXD0
TXD0

TXD1
TXD1

NC FOR GF117/GM108

TXD2
TXD2

NC FOR GF117/GK208/GM108

HPD_E

DVI-DL DVI-SL/HDMI DP

TXD3
TXD3

TXD4
TXD4

NC FOR GF117/GM108

TXD5
TXD5

1 2 3 4 5

I2CY_SDA
I2CY_SCL

TXC
TXC

TXD0
TXD0

TXD1
TXD1

TXD2
TXD2

NC FOR GK208

HPD_E

NC FOR GF117

GF119/GK208

I2CZ_SDA
I2CZ_SCL

TXC
TXC

TXD0
TXD0

TXD1
TXD1

TXD2
TXD2

NC FOR GK208

HPD_F

NC FOR GF117

IFP E_ AU X#
IFP E_ AU X

IFPE_L3#
IFPE _L3

IFPE_L2#
IFPE _L2

IFPE _L1 #
IFPE _L1

IFPE_L0#
IFPE _L0

GP IO18

IFP F_ AU X#
IFP F_ AU X

IFPF _L3#
IFPF _L3

IFPF _L2#
IFPF _L2

IFPF _L1#
IFPF _L1

IFPF _L0#
IFPF _L0

GP IO19

J3
J2

J1
K1

K3
K2

M3
M2

M1
N1

+1.0VS_DGPU

C2

1V

H4
H3

J5
J4

K5
K4

L4
L3

M5
M4

F7

DAC_A

GF117/GM108 GF117

NC

TSEN_VREF

NC

DIS@

LV5 1

Place near balls

LV6 1 2 0_0603_5%

GM108/GK208

I2CA_S CL

NC

I2CA_S DA

NC

DA CA _HSYNC

NC

DA CA _VS YN C

NC

DA CA _RE D

NC

DA CA _GR EEN

NC

DA CA _BLUE

NC

GM108

GK208

GF117

2 S SUPPRE_ MURATA BLM15PD300SN1D 0402 SM01000LX00

B7
A7

AE3
AE4

AG3
AF4
AF3

I2CA_SCL
I2CA_SDA

0.1U_0201_10V KX5R

22U_0603_6.3V6M

1

1

CV32 DIS@

2

2

Place near ballsPlace near BGA

22U_0603_6.3V6M

1

1

2

1

CV35 @

CV61 DIS@

2

2

0.1U_0201_10V KX5R

0.1U_0201_10V KX5R

1

CV30 DIS@

1

CV34 DIS@

2

2

10U_0603_6.3V6M

22U_0603_6.3V6

M

SecuriiityClllassiiifiiicatiiion

Issued Date Decipii hered Date

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL AND
TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT B E TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIIONOF R&D
DEPARTMENT EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IIINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIITCONTAIIINS
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IIINC...

I2CA_SCL <24>

I2CA_SDA <24>

GPU_PLLVDD

CV31 DIS@

L6

VID_PLLVDD

CV60 DIS@

RV21 DIS@
10K_0402_1%

2 1

M6

N6

A10

C11

90-OHM DIFF Impedan ce for XT ALIN & XTALOUT.

1

CV210 DIS@

18P_0402_50 V8J

2

2018/03/09 2019/03/09

Compal Secret Data

COMMON

5/14IFPC

T6

IFPC _R SET

M7

IFPC_P LLVD D

N7

IFPC_P LLVD D

P6

IFPC _IOV DD

N16S-GT-S-A2_BGA595

@

UV1I

COMMON

6/14IFPD

U6

IFPD _R SET

T7

IFPD _PL LVD D

R7

IFPD _PL LVD D

R6

IFPD _IOV DD

N16S-GT-S-A2_BGA595

@

UV1M

COMMON

9/14XTAL_PLL

PLLV DD
SP _P LLV DD

VID_ PLL VDD

GF119/GK208

XTA LS SI N

XTAL IN

N16S-GT-S-A2_BGA595

@

IFPD

X'TAL

NC

GF117/GM108

YV1
27MHZ_10PF_XRCGB27M000F2P18R0

SJ10000UI00

1

1

DIS@

NC NC

2 4

NC FOR GF117/GM108

NC FOR GF117/GM108

IFPC

IFPD

XTA LO UT BUF F

3

3

DVI/HDM I D P

I2CW_SDA
I2CW_SCL

NC FOR GF117/GM108

I2CX_SDA
I2CX_SCL

NC FOR GF117/GM108

C10

XTAL OUT

IFPC

GF119/GK208

N5

IFPC_A UX #

N4

IFP C_ AU X

N3

TXC
TXC

TXD0
TXD0

TXD1
TXD1

TXD2
TXD2

DVI/HDM I DP

B10

Tiiittllle

Siiize Documentt Number

IFPC _L3 #

N2

IFPC _L3

R3

IFPC _L2 #

R2

IFPC _L2

R1

IFPC _L1 #

T1

IFPC _L1

T3

IFPC _L0 #

T2

IFPC _L0

GF117

NC

GF119/GK208

TXC
TXC

TXD0
TXD0

TXD1
TXD1

TXD2
TXD2

GF117

NC

XTAL_OUTBUFF

XTAL_OUTBUFF

RV110 DIS@

1.5K_0402_1%

GP IO1 5

IFPD_A UX #
IFP D_ AU X

IFPD _L3 #
IFPD _L3

IFPD _L2 #
IFPD _L2

IFPD _L1 #
IFPD _L1

IFPD _L0 #
IFPD _L0

GP IO1 7

C3

P4
P3

R5
R4

T5
T4

U4
U3

V4
V3

D4

RV23 @
10K_0402_1%

1 2

RV20 DIS@
10K_0402_1%

1 2

+3VS_DGPU_AON

1 2

1

CV209 DIS@

18P_0402_50 V8J

2

Compal Electronics, Inc.

NV(2/5)-IFP_ABCDEF_DAC_XTAL

LA-G202P

Sheett 22 o f 55Datte:: Friiiday,,, March 09,,,2018

R ev

1...0

1 2 3 4 5

0.1U_0201_10V6

10U_0603_6.3V6

CV215

CV44

1

2

M

1

2

4.7U_0402_6.3V6M
CV213 DIS@

UV1D

COMMON

12/14 FBVDDQ

B26

FB VD DQ

C25

FBVDDQ

E23

FBVDDQ

E26

FBVDDQ

F14

FBVDDQ

F21

FBVDDQ

G13

FBVDDQ

G14

FBVDDQ

G15

FBVDDQ

G16

FBVDDQ

G18

FBVDDQ

G19

FBVDDQ

G20

FBVDDQ

G21

FBVDDQ

L22

FBVDDQ

L24

FBVDDQ

L26

FBVDDQ

M21

FBVDDQ

N21

FBVDDQ

R21

FBVDDQ

T21

FBVDDQ

V21

FBVDDQ

W2 1

FBVDDQ

H24

FBVDDQ_ AO N

H26

FBVDDQ_ AO N

J21

FBVDDQ_ AO N

K21

FBVDDQ_ AO N

N16S-GT-S-A2_BGA595

@

4.7U_0402_6.3V6
CV216 DIS@

GF117
GF119
GK208

FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ

FB _C AL_ PD_ VDD Q

FB _C AL_ PU_ GN D

FB _C ALT ERM _G ND

+3VS_DGPU

+3VS_DGPU_AON

Near Ball

+1.35VS_VRAM

D22 RV41 1 DIS@ 2 40.2_0402_1%

C24 RV42 2 DIS@ 1 40.2_0402_1%

B25 RV43 2 DIS@ 1 60.4_0402_1%

GPU_Decoupling
CAPs @ Power

Page

+VGA_CORE

Voltage by GP U SKU

SecuriiityClllassiiifiiicatiiion

Issued Date Decipii hered Date

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL AND
TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT B E TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIIONOF R&D
DEPARTMENT EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IIINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIITCONTAIIINS
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IIINC...

UV1E

COMMON

11/14NVVDD

K10

VD D

K12

VD D

K14

VD D

K16

VD D

K18

VD D

L11

VD D

L13

VD D

L15

VD D

L17

VD D

M10

VD D

M12

VD D

M14

VD D

M16

VD D

M18

VD D

N11

VD D

N13

VD D

N15

VD D

N17

VD D

P10

VD D

P12

VD D

P14

VD D

P16

VD D

P18

VD D

R11

VD D

R13

VD D

R15

VD D

R17

VD D

T10

VD D

T12

VD D

T14

VD D

T16

VD D

T18

VD D

U11

VD D

U13

VD D

U15

VD D

U17

VD D

V10

VD D

V12

VD D

V14

VD D

V16

VD D

V18

VD D

N16S-GT-S-A2_BGA595

@

2018/03/09 2019/03/09

Compal Secret Data

+1.35VS_VRAM

4.7U_0402_6.3V6

M

4.7U_0402_6.3V6

M

SE00000UC00

CV217 DIS@

A A

1

2

B B

CV38 DIS@

1

2 1

2

1U_0201_6.3V6M

CV218 DIS@

Place under GPU

1U_0201_6.3V6M

SE00000UC00

CV221 DIS@

2 1

K

0.1U_0201_10V6

K

1

1

CV222

DIS@

DIS@

2

2

M

22U_0603_6.3V6M

1

1

CV45

DIS@

DIS@

2

2

Place near GPU

CIZ00 22uF x1 change to 10uF x2

C C

D D

UV1C

COMMON

14/14 XVDD /VDD33

AD10

NC

AD7

NC

3V3_AON
3V3_AON

F11

3V 3A UX_ NC

V5

FE RM I_R SV D1_ NC

V6

FE RM I_R SV D2_ NC

CONFIGURABLE
POWERCHANNELS
* nc onsubstrate

G1

XPWR_G 1

G2

XPWR_G 2

G3

XPWR_G 3

G4

XPWR_G 4

G5

XPWR_G 5

G6

XPWR_G 6

G7

XPW R_G7

V1

XPW R_V1

V2

XPW R_V2

W 1

XPWR_W 1

W 2

XPWR_W 2

W 3

XPWR_W 3

W 4

XPW R_W4

N16S-GT-S-A2_BGA595

@

1 2 3 4 5

VD D3 3

G9

VD D3 3

GM108

VD D3 3
VD D3 3

Under GPU Near GPU

G8

G10
G12

0.1U_0201_10V6

K

0.1U_0201_10V6

K

1

1

CV220

CV211

DIS@

DIS@

2

2

0.1U_0201_10V6

K

1

CV214

2

DIS@

** XPWR pins are configurable.

These pins are not connected on thesubstrate.
Therefore, XPWR pins can be assigned as needed, to

improve Top layer routing, power delivery.

1U_0201_6.3V6M

SE00000UC00

CV219 DIS@

2 1

Near GPUUnder GPU

1U_0201_6.3V6M

SE00000UC00

CV212 DIS@

2 1

UV1F

COMMON

13/14GND

A2

GND

AB17

GND

AB20

GND

AB24

GND

AC2

GND

AC22

GND

AC26

GND

AC5

GND

AC8

GND

AD12

GND

AD13

GND

A26

GND

AD15

GND

AD16

GND

AD18

GND

AD19

GND

AD21

GND

AD22

GND

AE11

GND

AE14

GND

AE17

GND

AE20

GND

AB11

GND

AF1

GND

AF11

GND

AF14

GND

AF17

GND

AF20

GND

AF23

GND

AF5

GND

AF8

GND

AG2

GND

AG26

GND

AB14

GND

B1

GND

B11

GND

B14

GND

B17

GND

B20

GND

B23

GND

B27

GND

B5

GND

B8

GND

E11

GND

E14

GND

E17

GND

E2

GND

E20

GND

E22

GND

E25

GND

E5

GND

E8

GND

H2

GND

H23

GND

H25

GND

H5

GND

K11

GND

K13

GND

K15

GND

K17

GND

L10

GND

L12

GND

L14

GND

L16

GND

L18

GND

L2

GND

L23

GND

L25

GND

L5

GND

M11

GND

N16S-GT-S-A2_BGA595

@

M13

GND

M15

GND

M17

GND

N10

GND

N12

GND

N14

GND

N16

GND

N18

GND

P11

GND

P13

GND

P15

GND

P17

GND

P2

GND

P23

GND

P26

GND

P5

GND

R10

GND

R12

GND

R14

GND

R16

GND

R18

GND

T11

GND

T13

GND

T15

GND

T17

GND

U10

GND

U12

GND

U14

GND

U16

GND

U18

GND

U2

GND

U23

GND

U26

GND

U5

GND

V11

GND

V13

GND

V15

GND

V17

GND

Y2

GND

Y23

GND

Y26

GND

Y5

GND

AA7

GND

AB7

GND

Tiiittllle

Siiize Documentt Number

Datte:: Friiiday,,, March 09,,,2018 Sheett 23 o ff 55

Compal Electronics, Inc.

NV(3/5)-POWER

LA-G202P

R ev

1...0

1

UV1N

COMMON

E12

THE RM DN

F12

A

B B

C C

GPU_JTAG_TDO

T243 TP@

GPU_JTAG_TRST#

+3VS_DGPU_AON

RV265
0_0402_5%

1 @ 2

12

+3VS Reserve for
leakage issue

RV15 @

10K_0402_5%

VGA_AC_DET AC_PRESENT

GPU_JTAG_TCK

T231 TP@

GPU_JTAG_TMS

T232 TP@

GPU_JTAG_TDI

T242 TP@

THE RM DP

AE5

JTAG _TCK

AD6

JTAG _TMS

AE6

JTAG _TDI

AF6

JTAG _TDO

AG4

JTAG _TRS T#

N16S-GT-S-A2_BGA595

@

UV1L

COMMON

10/14MISC2

E10

VMO N_ IN0 _N C

F10

VMO N_ IN1 _N C

D1

STRAP0

STR AP 0

D2

STR AP1

STRAP1

E4

STRAP2

STR AP2

E3

STRAP3

STR AP3

D3

STRAP4

STR AP4

C1

STR AP 5_ NC

STRAPREF0 F6

MUL TI STR AP _REF 0_ GND

RV380 F4

MUL TI STR AP _REF 1_ GND

40.2K_0402_1%

DIS@ F5

MUL TI STR AP _REF 2_ GND

N16S-GT-S-A2_BGA595

@

+3VS +3VS

DV4 @

1 2

RB751V-40_SOD323-2

2 1

RV126 1@ 2 0_0402_5%

8/14 MISC1

NC FOR
GM108

1 2

GPIO

GPIO16
GPIO20
GPIO21

RV26 @
10K_0402_5%

GM108

GPIO8

GF117
GK208

GM108

I2CS_SCL

D9

I2C S_S CL

I2CS_SDA

D8

I2C S_S DA

I2CC_SCL

A9

I2C C_S CL

I2CC_SDA

B9

I2C C_ SDA

GF117

NC
NC

GK208
GM108
OVERT

GK208

GF117 GF119

GPIO16

NC

GPIO20

NC

GPIO8

NC

NC

NC

ROM _C S#

ROM _S I

ROM _S O

ROM _S CLK

BUF RS T#

PG OOD

NC

GF119GF117

GK208
GM108

NC

NC

AC_PRESENT <10,36>

I2C B_ SCL
I2C B_ SDA

GPI O0
GPI O1

GPIO2
GPI O3
GPI O4
GPI O5
GPIO6
GPI O7

GPI O8

GPI O9
GPI O10
GPI O11
GPI O12
GPIO13

GPIO16
GPIO20
GPIO21

A12

C12

D10

C6

C7
F9
A3

B6
F8

C5
E7
D7

NC

D12
B12

D11

I2CB_SCL

C9

I2CB_SDA

C8

GPIO0_GC6_FB_EN

B2
D6

DGPU_MAIN_EN

GPU_EVENT#_D

A4

GPIO8_OVERT#

A6

GPIO9_ALERT#
MEM_VREF
GPU_VID0
VGA_AC_DET

B4 PSI

D5
E6

PLT_RST_VGA_HOLD#

C4

PLT_RST_VGA_MON#

E9

ROM_SI
ROM_SO

ROM_SCLK

GPU_BUFRST

2

+3VS_DGPU_AON

RV203 1 DIS@2 2.2K_0402_5% RV204

1 DIS@2 2.2K_0402_5%

RV205 1 @2 2.2K_0402_5%
RV206 1 @2 2.2K_0402_5%

RV202 1 2 0_0402_5%

For GC6 2.0

DV1 GC6@ 2 1 S SCH DIO RB751V40SC76

DV5 DIS@ 2 1 S SCH DIO RB751V40 SC76

SCS00002G00

SCS00002G00

STRAP

14.7K_0402_1%

12

RV84

@

ROM_SI
ROM_SO
ROM_SCLK

4.99K_0402_1%

12

@

RV65

RV65 Stuff in X76.

I2CS SMBUS: 0x96
and 0x9E(Default)

GC6_FB_EN<11,25>

DGPU_MAIN_EN<26,51>
GPU_EVENT# <11>

GPU_PROHOT#<36>

MEM_VREF <27>
GPU_VID0 <51>

PSI <51>

PLT_RST_VGA_HOLD#<21>
PLT_RST_VGA_MON#<21>

+3VS_DGPU

4.99K_0402_1%

4.99K_0402_1%

12

12

RV81

DIS@

12

@

RV80

@

4.99K_0402_1%

4.99K_0402_1%

12

DIS@

RV64

RV381

To EC

To DGPU VR

From EC

To DGPU VR

STRAP

STRAP0
STRAP1
STRAP2
STRAP3
STRAP4

3

<21> GPU_TESTMODE

+3VS_DGPU_AON

12

10K_0402_1%

@

45.3K_0402_1%

12

@

<25> FB_CLAMP

<22> I2CA_SCL
<22> I2CA_SDA

STRAP0 : PU 49.9K (50K)
STRAP[1:5] : Reserved

45.3K_0402_1%

4.99K_0402_1%

12

12

RV389

RV61

@

RV385

@

RV382

@

@

4.99K_0402_1%

4.99K_0402_1%

12

1

RV388

RV387

@

2

@

PLT_RST_VGA_HOLD#
DGPU_MAIN_EN
PSI

VGA_AC_DET

GPU_EVENT#_D
GPIO8_OVERT#

GPIO9_ALERT#
GPU_JTAG_TRST#

FB_CLAMP

I2CA_SCL
I2CA_SDA
I2CB_SCL

I2CB_SDA

GPU_BUFRST
GPU_TESTMODE
MEM_VREF

PLT_RST_VGA_MON#
GC6_FB_EN

4.99K_0402_1%

12

12
DIS@

RV51

4.99K_0402_1%

12

12

RV390

@

RPV5

1 8
2 7
3 6
4 5

10K_0804_8P4R_5%

DIS@

RV72 1 GC6@ 2 10K_0402_5%
RV69 1 DIS@ 2 100K_0402_5%

RPV6

1 8
237

6

4 5

10K_0804_8P4R_5%

DIS@

RPV3

1 8
2 7
3 6
4 5

2.2K_0804_8P4R_5%

@

RV67 1 @ 2 10K_0402_5%
RV71 1 DIS@ 2 10K_0402_5%
RV102 1 DIS@2 100K_0402_5%

RV70 1 @ 2 10K_0402_5%

RV88 1 GC6@ 2 10K_0402_5%

49.9K_0402_1%
RV384

4.99K_0402_1%
RV383

RAM_CFG[3:0] BAX40

(ROM_SI)

0x0 4.99K(L)

0x1 10.0K(L)

S2G@

M2G@

4

+3VS_DGPU_AON

Internal Thermal Sensor

I2CS_SCL

I2CS_SDA

2N7002KDW_SOT363-6

2N7002KDW_SOT363-6

2

G

S

+3VS_DGPU_AON

5

G

S

34

D

DIS@

QV2A

61

D

DIS@

QV2B

Link to PCH SML1

PU @ PCH SIDE

EC_SMB_CK2 <8,36>

EC_SMB_DA2 <8,36>

5

0x2 15.0K(L)

0x3 20.0K(L)

CONFIG

RAM_CFG

0x0

4.99K(L)

0x1

10.0K(L)

0x5

30.1K(L)

D D

0x6

34.8K(L)

0x7

45.3K(L)

0x4

24.9K(L)

X76

X7677538L04

X7677538L05

X7677538L06

S2G@

M2G@

H2G@

1

ROM_SI

RV65

4.99K +-1%0402

SD034499180
S2G@

RV65
10K +-1%0402

SD034100280
M2G@

RV65

30.1K +-1%0402

SD034301280
H2G@

RV65

34.8K +-1%0402

SD034348280
@

RV65

45.3K +-1%0402

SD034453280
@

RV65

24.9K +-1%0402

SD034249280
@

UV6S2G_R1@

SA000092D10

UV6S2G_R3@

SA000092D30

UV6M2G_R1@

SA00009TV00

UV6M2G_R3@

SA00009TV20

UV6H2G_R1@

SA00009U100

UV6H2G_R3@

SA00009U130

UV7S2G_R1@

SA000092D10

UV7S2G_R3@

SA000092D30

UV7M2G_R1@

SA00009TV00

UV7M2G_R3@

SA00009TV20

UV7H2G_R1@

SA00009U100

UV7H2G_R3@

SA00009U130

K4G80325FB-HC28
K4G80325FB-HC28

MT51J256M32HF-70:A
MT51J256M32HF-70:A

H5GC8H24MJR-R0C
H5GC8H24MJR-R0C

RESE RVED

RESE RVED

RESE RVED

2

3

0x4 24.9K(L)

0x5 30.1K(L)

H2G@

0x6 34.8 K(L)

0x7

45.3K(L)

0x8 4.99 K(H)

0x9 10.0 K(H)

0xA 15.0 K(H)

0xB 20.0 K(H)

0xC 24.9 K(H)

0xD 30.1 K(H)

0xE 34.8 K(H)

0xF 45.3 K(H)

Securiiity Clllassiiifiiicatiiion

Issued Date

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL AND
TRADE SEC RET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTOD Y OF THE C OMPETENT DIIIVIIISIIION OF R&D
DEPARTMENT EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IIINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIITCONTAIIINS
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,,IIINC...

2018/03/09 2019/03/09

Compalll Secret Data

Deciiiphered Date

4

Compal Electronics, Inc.

Tiiitttllle

NV(4/5)-GPIO/Strap

Siiize DocumentttNumberrr

LA-G202P

Rev

Sheettt

5

24 offf 55Dattte::: Frrriiiday,,, Marrrch 09,,, 2018

1...0

A

1

2

3

4

5

UV1B

COMMON

AA24
AA23

AD27
AB25
AD26
AC25
AA27
AA26

W2 4

AA25

E19
C15
B16
B22
R25
W2 3
AB26
T26

D23

E18

F18

E16

F17
D20
D21

F20
E21
E15
D15

F15

F13
C13
B13
E13
D13
B15
C16
A13
A15
B18
A18
A19
C19
B24
C23
A25
A24
A21
B21
C20
C21
R22
R24

T22
R23
N25
N26
N23
N24
V23
V22

T23
U22
Y24

Y22

W2 6

Y25
R26

T25
N27
R27
V26
V27

W2 7
W2 5

D19
D14
C17
C22
P24

U25

AB27

FBA _D4 5

FBA _D4 7
FBA _D4 8
FBA _D4 9
FBA _D5 0
FBA _D5 1
FBA _D5 2
FBA _D5 3

FB A_ DQM 5

FB A_ DQM 6

FB A_ DQS _W P0
FB A_ DQS _W P1
FB A_ DQS _W P2
FB A_ DQS _W P3
FB A_ DQS _W P4

FB A_ DQS _WP 5
FB A_ DQS _W P6

FB A_ DQS _WP 7

F19
C14
A16
A22
P25

W2 2

T27

FB_ VRE F_P ROBE

2/14FBA

FBA_D 0
FB A_ D1
FB A_ D2
FB A_ D3
FB A_ D4
FB A_ D5
FB A_ D6
FB A_ D7
FB A_ D8
FB A_ D9
FB A_ D10
FB A_ D11

FB A_ D12
FB A_ D13
FB A_ D14

FB A_ D15
FB A_ D16

FB A_ D17
FB A_ D18
FB A_ D19
FB A_ D20
FB A_ D21
FB A_ D22

FB A_ D23
FB A_ D24

FB A_ D25
FB A_ D26
FB A_ D27
FB A_ D28
FB A_ D29

FB A_ D30

FB A_ D31

FB A_ D32

FB A_ D33
FB A_ D34

FB A_ D35

FB A_ D36

FB A_ D37

FB A_ D38

FB A_ D39
FB A_ D40
FB A_ D41
FB A_ D42

FB A_ D43
FB A_ D44

FB A_ D46

FB A_ D54
FB A_ D55

FB A_ D56
FB A_ D57

FB A_ D58

FB A_ D59
FB A_ D60
FB A_ D61

FB A_ D62

FB A_ D63

FB A_ DQM 0

FB A_ DQM 1

FB A_ DQM 2

FB A_ DQM 3
FB A_ DQM 4

FB A_ DQM 7

FB A_ DQS _RN 0
FB A_ DQS _R N1
FB A_ DQS _RN 2
FB A_ DQS _RN 3
FB A_ DQS _RN 4
FB A_ DQS _R N5
FB A_ DQS _R N6
FB A_ DQS _RN 7

N16S-GT-S-A2_BGA595

@

GF117/GF119

GK208

FBA_DEBUG0
FBA_DEBUG1

FB_PLLAVDD

NC

GF119

FB_CLAMP <24>

FB_CLAMP

F3

FB _C LAM P

FB_A_CMD[0..31] <27>

FB_A_CMD0

C27

FB A_ CMD 0
FB A_ CMD 1
FB A_ CMD 2
FB A_ CMD 3
FB A_ CMD 4
FB A_ CMD 5
FB A_ CMD 6
FB A_ CMD 7
FB A_ CMD 8

FB A_ CMD 9
FB A_ CMD 10
FB A_ CMD 11
FB A_ CMD 12
FB A_ CMD 13
FB A_ CMD 14
FB A_ CMD 15
FB A_ CMD 16
FB A_ CMD 17
FB A_ CMD 18
FB A_ CMD 19
FB A_ CMD 20
FB A_ CMD 21
FB A_ CMD 22
FB A_ CMD 23
FB A_ CMD 24
FB A_ CMD 25
FB A_ CMD 26
FB A_ CMD 27
FB A_ CMD 28
FB A_ CMD 29
FB A_ CMD 30
FB A_ CMD 31

NC

GF119

GF117

FB A_ CMD 32

FB A_ CMD 34
FB A_ CMD 35

FB A_ CLK 0
FB A_ CLK 0#
FB A_ CLK 1
FB A_ CLK 1#

FB A_W CK 01
FB A_W CK 01#
FB A_W CK 23
FB A_W CK 23#
FB A_W CK 45
FB A_W CK 45#
FB A_W CK 67
FB A_W CK 67#

FB _P LLA VDD

NC

FB _P LLA VDD

FB _D LLA VDD

FB_A_CMD1

C26

FB_A_CMD2

E24

FB_A_CMD3

F24

FB_A_CMD4

D27

FB_A_CMD5

D26

FB_A_CMD6

F25

FB_A_CMD7

F26

FB_A_CMD8

F23

FB_A_CMD9

G22

FB_A_CMD10

G23

FB_A_CMD11

G24

FB_A_CMD12

F27

FB_A_CMD13

G25

FB_A_CMD14

G27

FB_A_CMD15

G26

FB_A_CMD16

M24

FB_A_CMD17

M23

FB_A_CMD18

K24

FB_A_CMD19

K23

FB_A_CMD20

M27

FB_A_CMD21

M26

FB_A_CMD22

M25

FB_A_CMD23

K26

FB_A_CMD24

K22

FB_A_CMD25

J23

FB_A_CMD26

J25

FB_A_CMD27

J24

FB_A_CMD28

K27

FB_A_CMD29

K25

FB_A_CMD30

J27

FB_A_CMD31

J26

B19
F22

RV82 1 @ 2

J22

RV83 1 @ 2

FB_A_CLK0

D24

FB_A_CLK#0

D25

FB_A_CLK1

N22

FB_A_CLK#1

M22

FB_A_WCK0

D18

FB_A_WCK#0

C18

FB_A_WCK1

D17

FB_A_WCK#1

D16

FB_A_WCK2

T24

FB_A_WCK#2

U24

FB_A_WCK3

V24

FB_A_WCK#3

V25

F16

+1.0VS_PLLAVDD

P22

H22

Close to P22

0.1U_0201_10V KX5R

CV55 DIS@

1

2

1.35V

60.4_0402_1%

60.4_0402_1%

FB_A_WCK0 <27>
FB_A_WCK#0 <27>
FB_A_WCK1 <27>
FB_A_WCK#1 <27>
FB_A_WCK2 <27>
FB_A_WCK#2 <27>
FB_A_WCK3 <27>
FB_A_WCK#3 <27>

CV52 DIS@

0.1U_0201_10V KX5R

2

1

Close to H22

FB_A_CMD14

FBA_CKE_L

FB_A_CMD30

FBA_CKE_H

FB_A_CMD13

FBA_RST_L

FB_A_CMD29

FBA_RST_H

GDDR5 design

FBVDDQ_GPU

+1.35VS_VRAM

FB_A_CLK0 <27>
FB_A_CLK#0 <27>
FB_A_CLK1 <27>
FB_A_CLK#1 <27>

+1.0VS_PLLAVDD

Close to F16

CV53 DIS@

0.1U_0201_10V KX5R

CV51 DIS@

22U_0603_6.3V6

M

1

2

Near GPU

<27> FB_A_D[0..31]

A A

<27> FB_A_D[32..63]

B B

<27> FB_A_DBI[3..0]

<27> FB_A_DBI[7..4]

C C

Refer CIZ00 LA-E011

<27> FB_A_EDC[3..0]

<27> FB_A_EDC[7..4]

For VRAM DEBUG using

D D

T2401 TP@

FB_A_D0
FB_A_D1
FB_A_D2
FB_A_D3
FB_A_D4
FB_A_D5
FB_A_D6
FB_A_D7
FB_A_D8
FB_A_D9
FB_A_D10
FB_A_D11
FB_A_D12
FB_A_D13
FB_A_D14
FB_A_D15
FB_A_D16
FB_A_D17
FB_A_D18
FB_A_D19
FB_A_D20
FB_A_D21
FB_A_D22
FB_A_D23
FB_A_D24
FB_A_D25
FB_A_D26
FB_A_D27
FB_A_D28
FB_A_D29
FB_A_D30
FB_A_D31
FB_A_D32
FB_A_D33
FB_A_D34
FB_A_D35
FB_A_D36
FB_A_D37
FB_A_D38
FB_A_D39
FB_A_D40
FB_A_D41
FB_A_D42
FB_A_D43
FB_A_D44
FB_A_D45
FB_A_D46
FB_A_D47
FB_A_D48
FB_A_D49
FB_A_D50
FB_A_D51
FB_A_D52
FB_A_D53
FB_A_D54
FB_A_D55
FB_A_D56
FB_A_D57
FB_A_D58
FB_A_D59
FB_A_D60
FB_A_D61
FB_A_D62
FB_A_D63

FB_A_DBI0
FB_A_DBI1
FB_A_DBI2
FB_A_DBI3
FB_A_DBI4
FB_A_DBI5
FB_A_DBI6
FB_A_DBI7

FB_A_EDC0
FB_A_EDC1
FB_A_EDC2
FB_A_EDC3
FB_A_EDC4
FB_A_EDC5
FB_A_EDC6
FB_A_EDC7

FB_VREF

For GC6

<11,24> GC6_FB_EN

<21,26,51> DGPU_PWROK

+1.35VS_VRAM +1.35VS_VRAM

10K_0402_5%

DIS@

RV255

DIS@

1 2

1 2

10K_0402_5%

DIS@

RV253

DIS@

1 2

1 2

Refer CIZ00 LA-E011

Refer CIZ00 LA-E011

DIS@

1

LV7

SM01000LX00

+1.0VS_DGPU

2

1.0V

1

2

CV223 @

0.1U_0201_10V KX5R

GC6_FB_EN

From DG-07158-001_v05_secured(NVDIA Spec)

10K_0402_5

%

RV256

10K_0402_5

%

RV254

S SUPPRE_ MURATA BLM15PD3 00SN1D 0402

+3VS

1

2

UV23 GC6@
S IC TC7SH32FU SSOP 5P

5

SA007320120

2

B

4

Y

1

A

G Vcc

3

RV201 1 2 0_0402_5%

NOGC6@

Stuff RV201 if not support GC6

1.35V_PWR_EN <26,52>

SecuriiityClllassiiifiiicatiiion

Issued Date Decipii hered Date

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL AND
TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT B E TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIIONOF R&D
DEPARTMENT EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IIINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIITCONTAIIINS

1

2

MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IIINC...

3

2018/03/09 2019/03/09

Compal Secret Data

Tiiittllle

Siiize Documentt Number

4

Compal Electronics, Inc.

NV(5/5)-MEMORY FBA

LA-G202P

Sheett 25 o ff 55Datte:: Friiiday,,, March 09,,, 2018

5

R ev

1...0

5 4 3 2 1

I_Continuous(Max) : 0.79 A(+1.0VS_DGPU)

+3VS to +3VS_DGPU

RV261
47K_0402_5%

DIS@

1 2

DGPU_MAIN_EN# DGPU_MAIN_EN#_GATE

D D

<24,51> DGPU_MAIN_EN

DGPU_MAIN_EN

+3VS to +3VS_DGPU_AON

<11,36> DGPU_PW R_EN

C C

DGPU_PWR_EN

RV263
0_0402_5%

1

2

SE00000UC00

1U_0201_6.3V6M

12

+5VALW

RV258
47K_0402_5%

DIS@

1 2

DGPU_PWR_EN# DGPU_PWR_EN#_GATE

RV264
0_0402_5%

1

2

SE00000UC00

1U_0201_6.3V6M

12

2

CV321 @

5

CV317 @

RV262 DIS@
10K_0402_5%

61

QV30ADIS@
L2N7002DW1T1G 2N SC88-6

RV259 DIS@
10K_0402_5%

QV30BDIS@
L2N7002DW1T1G 2N SC88-6

4 3

QV26 DIS@
ME2301DC-G_SOT23-3

D

S

3 1

G

2

1

0.1U_0201_10V KX5R

2

QV20 DIS@
ME2301DC-G_SOT23-3

D

S

3 1

G

2

1

0.1U_0201_10V KX5R

2

+3VS_DGPU_AON

1

CV320 DIS@

2

1

CV313 DIS@

2

+3VS_DGPU+3VS+5VALW

RV260 @

470_0603_5%

12

SE00000UC00

CV318 @

1U_0201_6.3V6M

D

CV319

4.7U_0402_6.3V6M

@

CV312

4.7U_0402_6.3V6M

@

13

DGPU_MAIN_EN#

2

G

1 2

QV25 @

S

2N7002K_SOT23-3

+3VS_DGPU_AON+3VS

12

RV257 @

470_0603_5%

SE00000UC00

CV311 @

1U_0201_6.3V6M

D

13

DGPU_PWR_EN#

2

G

1 2

QV19 @

S

2N7002K_SOT23-3

<25,52> 1.35V_P WR_EN

RV252 @

100K_0402_1%

12

1.35V_PWR_EN#

61

D QV145A @

2N7002KDW_SOT363-6

2

G

S

+1.35VS_VRAM+5VALW +5VALW

22_0603_1%

12

34

D QV145B @

5

2N7002KDW_SOT363-6

G

S

+1.0V_PRIM to +1.0VS_DGPU

RV251 @

DGPU_MAIN_EN

DGPU_MAIN_EN#

1 @ 2

RV128 0_0402_5%

1 2

DGPU_MAIN_EN_GATE

D

2

G

S

3 1

RON(Max) : 22 mohm
V drop : 0.0175 V
Rising : ~ 208us

+1.0VALW +1.0VS_DGPU

1U_0201_6.3V6M

SE00000UC00

CV133 @

0.1U_0201_10V6K

RV266 DIS@

47K_0402_5%

QV146 DIS@

2N7002K_SOT23-3

1

2

DGPU_MAIN_EN_R_GATE RV85

2 DIS@1

47K_0402_5%

CV314 DIS@

2 1

DIS@ CV315

.047U_0402_16V7K

SE076473K80

QV5 DIS@
ME2320D-G 1NSOT-23-3

D

S

1 3

G

2

2

1

CV316 DIS@

0.1U_0201_10V KX5R

1

2

RG82
10K_0402_5%

<21,25,51> DGPU_PWROK

B B

A A

DGPU_PWROK

+1.35VGS_PGOOD

5 4

RG83 1 2 0_0402_5%

1

DG4

2 S SCH DIO RB751V40 SC76

SCS00002G00
DIS@

DIS@

1 2

GPU_ALL_PGOOD

GPU_ALL_PGOOD<11><52> +1.35VGS_PGOOD

Securiiity Clllassiiifiiicatiiion

Issued Date

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL AND
TRADE SEC RET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTOD Y OF THE COMPETENT DIIIVIIISIIION OF R&D
DEPARTMENT EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IIINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIITCONTAIIINS

3 2

MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,,IIINC...

2018/03/09 2019/03/09

Compalll Secret Data

Deciiiphered Date

Compal Electronics, Inc.

Tiiitttllle

DGPU_DC/DC Interface

DocumentttNumberrr

Siiize

LA-G202P

Dattte::: Frrriiiday,,, Marrrch 09,,, 2018

1

Sheettt 26 o fff55

Rev

1...0

5 4 3 2 1

MF=0 MF=1

MF=0 M F=1 MF =1 MF =0

EDC3
EDC2
EDC1
EDC0

DBI3#
DBI2#
DBI1#
DBI0#

BA2/A4
BA3/A3
BA0/A2
BA1/A5

A10/A0
A11/A6
A8/A7
A9/A1

CAS#
WE#
RAS#
CS#

WCK 23#

WCK 23

WCK 01#

WCK 01

170-BALL

DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

K4G80325FB-HC03_FBGA170~D@

Near b all

DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VSSQ
VSSQ
VSSQ

FB_A_D0

A4

DQ0

A2

FB_A_D1
FB_A_D2

DQ1

B4

FB_A_D3

DQ2

B2

DQ3

FB_A_D4

E4

DQ4

FB_A_D5

E2

DQ5

FB_A_D6

F4

FB_A_D7

DQ6

F2

DQ7

FB_A_D8

A11

FB_A_D9

DQ8

A13

FB_A_D10

DQ9

B11

FB_A_D11

B13

FB_A_D12

E11

FB_A_D13

E13

FB_A_D14

F11

FB_A_D15

F13

FB_A_D16

U11

FB_A_D17

U13

FB_A_D18

T11

FB_A_D19

T13

FB_A_D20

N11

FB_A_D21

N13

FB_A_D22

M11

FB_A_D23

M13

FB_A_D24

U4

FB_A_D25

U2

FB_A_D26

T4

FB_A_D27

T2

FB_A_D28

N4

FB_A_D29

N2

FB_A_D30

M4

FB_A_D31

M2

B1
D1
F1
M1
P1
T1
G2
L2
B3
D3
F3
H3
K3
M3
P3
T3
E5
N5
E10
N10
B12
D12
F12
H12
K12
M12
P12

T12
G13
L13
B14
D14
F14
M14
P14
T14

A1
C1
E1T10
N1
R1
U1
H2
K2
A3
C3
E3
N3
R3
U3
C4
R4
F5
M5
F10
M10
C11
R11
A12
C12

E12
N12
R12
U12
H13

K13

A14
C14
E14
N14

R14

U14

BYTE0

BYTE1

BYTE2

BYTE3

<25> FB_A_DBI7
<25> FB_A_DBI6
<25> FB_A_DBI5
<25> FB_A_DBI4

<25> FB_A_CLK1
<25> FB_A_CLK#1

+1.35VS_VRAM

<25> FB_A_WCK#3
<25> FB_A_WCK3

<25> FB_A_WCK#2
<25> FB_A_WCK2

RV130
RV132
RV134

FB_A_EDC7
FB_A_EDC6

FB_A_EDC5
FB_A_EDC4

FB_A_CLK1
FB_A_CLK#1

FB_A_CMD30

FB_A_CMD19
FB_A_CMD17

FB_A_CMD18
FB_A_CMD20

FB_A_CMD26
FB_A_CMD23

FB_A_CMD22
FB_A_CMD27
FB_A_CMD25

1 1K_0402_1%DIS@ 2
1 1K_0402_1%DIS@ 2
1 121_0402_1%DIS@ 2

FB_A_CMD24
FB_A_CMD31

FB_A_CMD21
FB_A_CMD28
FB_A_CMD16

FB_A_WCK#3
FB_A_WCK3

FB_A_WCK#2
FB_A_WCK2

FB_A_CMD29

+1.35VS_VRAM Near VRAM

UV7

MF=0 MF=1 MF= 1 MF=0

C2
C13
R13

R2

D2
D13
P13

P2
J12

J11

J3

H11
K10
K11
H10

K4

H5

H4

K5

J5

A5

U5

J1
J10
J13

J4

G3

G12

L3

L12

D5
D4

P5
P4

A10
U10

J14

J2

H1
K1
B5
G5

L5

T5

B10
D10
G10
L10
P10
T10
H14
K14

G1

L1

G4

L4

C5

R5
C10
R10
D11
G11
L11
P11
G14
L14

EDC0
EDC1
EDC2

EDC3

DBI0#
DBI1#
DBI2#

DBI3#

CK
CK#

CKE#

BA0/A 2
BA1/A 5
BA2/A 4

BA3/A3

A8/A7
A9/A1
A10/A 0
A11/A 6

A12/RF U/NC

VPP/N C

VPP/N C

MF
SEN

ZQ

ABI#
RAS#
CS#
CAS#

WE#

WCK 01#

WCK 01

WCK 23#

WCK 23

VREFD
VREFD

VREFC

RESET#

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VDD

170-BALL

SGRAM GDDR5

EDC3
EDC2
EDC1
EDC0

DBI3#
DBI2#
DBI1#
DBI0#

BA2/A4
BA3/A3
BA0/A2
BA1/A5

A10/A0
A11/A6
A8/A7
A9/A1

CAS#
WE#
RAS#
CS#

WCK 23#

WCK 23

WCK 01#

WCK 01

DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

K4G80325FB-HC03_FBGA170~D@

DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VSSQ

A2

FB_A_D57
FB_A_D58

DQ1

B4

DQ2

FB_A_D59

B2

FB_A_D60

DQ3

E4

FB_A_D61

DQ4

E2

FB_A_D62

DQ5

F4

FB_A_D63

DQ6

F2

FB_A_D48

DQ7

A11

FB_A_D49

DQ8

A13

FB_A_D50

DQ9

B11

FB_A_D51

B13

FB_A_D52

E11

FB_A_D53

E13

FB_A_D54

F11

FB_A_D55

F13

FB_A_D40

U11

FB_A_D41

U13

FB_A_D42

T11

FB_A_D43

T13

FB_A_D44

N11

FB_A_D45

N13

FB_A_D46

M11

FB_A_D47

M13

FB_A_D32

U4

FB_A_D33

U2

FB_A_D34

T4

FB_A_D35

T2

FB_A_D36

N4

FB_A_D37

N2

FB_A_D38

M4

FB_A_D39

M2

B1
D1
F1
M1
P1
T1
G2
L2
B3
D3
F3
H3
K3
M3
P3
T3
E5
N5
E10
N10
B12
D12
F12
H12
K12
M12
P12
T12
G13
L13
B14
D14
F14
M14
P14
T14

A1
C1
E1
N1
R1
U1
H2
K2
A3
C3
E3
N3
R3
U3
C4
R4
F5

M5
F10

M10

C11
R11
A12
C12
E12
N12
R12
U12
H13
K13
A14
C14
E14
N14
R14
U14

BYTE7

BYTE6

BYTE5

BYTE4

+1.35VS_VRAM+1.35VS_VRAM

FB_A_D56

A4

DQ0

Near b all

C13
R13

D13
P13

H11
K10
K11
H10

G12

A10
U10

C2

R2

D2

P2

J12
J11

K4
H5
H4
K5

A5
U5

J10
J13

G3

L12

D5
D4

P5
P4

J14

H1

B10
D10
G10

L10

P10
H14

K14

G1

C10
R10
D11
G11

L11
P11
G14

L14

J3

J5

J1

J4

L3

J2

K1
B5
G5
L5
T5

L1
G4
L4
C5
R5

UV6

EDC0
EDC1
EDC2

EDC3

DBI0#
DBI1#
DBI2#

DBI3#

CK
CK#

CKE#

BA0/A 2
BA1/A 5
BA2/A 4

BA3/A3

A8/A7
A9/A1
A10/A 0
A11/A 6

A12/RF U/NC

VPP/N C

VPP/N C

MF
SEN

ZQ

ABI#
RAS#
CS#
CAS#

WE#

WCK 01#

WCK 01

WCK 23#

WCK 23

VREFD
VREFD

VREFC

RESET#

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VRAM Memory Partition A

FB_A_EDC0
FB_A_EDC1

FB_A_EDC2
FB_A_EDC3

<25> FB_A_DBI0
<25> FB_A_DBI1

D D

C C

<25> FB_A_D[0..31]
<25> FB_A_D[32..63]

<25> FB_A_EDC[0..3]
<25> FB_A_EDC[4..7]

<25> FB_A_CMD[0..15]
<25> FB_A_CMD[16..31]

FB_A_D[0..31]
FB_A_D[32..63]

FB_A_EDC[0..3]
FB_A_EDC[4..7]

FB_A_CMD[0..15]
FB_A_CMD[16..31]

Near to UV6

RV1 DIS@

40.2_0402_1%

FB_A_CLK0 FB_A_CLK#0

1 2 1

B B

1

CV19 DIS@

0.01U_0402_16V7K

2

RV2 DIS@

40.2_0402_1%

2

<25> FB_A_DBI2
<25> FB_A_DBI3

<25> FB_A_CLK0
<25> FB_A_CLK#0

<25> FB_A_WCK#0
<25> FB_A_W CK0

<25> FB_A_WCK#1
<25> FB_A_W CK1

+1.35VS_VRAM +1.35VS_VRAM

FB_A_CLK0
FB_A_CLK#0

FB_A_CMD14

FB_A_CMD2
FB_A_CMD4

FB_A_CMD3
FB_A_CMD1

FB_A_CMD6
FB_A_CMD11

FB_A_CMD10
FB_A_CMD7
FB_A_CMD9

1 1K_0402_1%RV116 DIS@ 2
1 1K_0402_1%RV118 DIS@ 2
1 121_0402_1%RV120 DIS@ 2

FB_A_CMD8
FB_A_CMD12

FB_A_CMD0
FB_A_CMD15
FB_A_CMD5

FB_A_WCK#0
FB_A_WCK0

FB_A_WCK#1
FB_A_WCK1

+FBA_VREFC0 +FBA_VREFC0

FB_A_CMD13

Near to UV7

SGRAM GDDR5

1

CV20 DIS@

0.01U_0402_16V7K

2

RV5 DIS@

40.2_0402_1%

2

RV3 DIS@

40.2_0402_1%

FB_A_CLK1 FB_A_CLK#1

1 2 1

+1.35VS_VRAM Near VRAM

2

2

+1.35VS_VRAM

12

RV125 DIS@
549_0402_1%

Place near pin J14 of each vram

RV200 1 DIS@ 2 931_0402_1%

D

<24> MEM_V REF

A A

2

G

QV50

2N7002KW_SOT323-3

S

3 1

SB000009Q80
DIS@

5 4

RV127 DIS@

1.33K_0402_1%

12

+FBA_VREFC0

W=16mils

CV158 DIS@

820P_0402_25V7

CV159 DIS@

820P_0402_25V7

1

1

2

2

+FBA_VREFC0

2

1

1

CV601 DIS@

22U_0603_6.3V6M

+1.35VS_VRAM Near ball

1U_0201_6.3V6M

SE00000UC00

SE00000UC00

CV609 DIS@

12

1

2

2

1

1

CV603 @

CV602 DIS@

10U_0603_6.3V6M

1U_0201_6.3V6M

10U_0603_6.3V6M

1U_0201_6.3V6M

SE00000UC00

CV610 DIS@

1U_0201_6.3V6M

SE00000UC00

CV611 DIS@

12

12

2

1

CV604 DIS@

10U_0603_6.3V6M

1U_0201_6.3V6M

SE00000UC00

SE00000UC00

CV613 DIS@

CV612 DIS@

12

12

3 2

2

2

1

CV605 DIS@

10U_0603_6.3V6M

CV606 DIS@

1U_0201_6.3V6M

SE00000UC00

CV614 @

12

2

1

1

CV607 @

10U_0603_6.3V6M

10U_0603_6.3V6M

CV608 DIS@

10U_0603_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

SE00000UC00

CV616 @

CV615 DIS@

12

1U_0201_6.3V6M

SE00000UC00

SE00000UC00

CV617 @

12

CV618 DIS@

12

Securiiity Clllassiiifiiicatiiion

Issued Date

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL AND
TRADE SEC RET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTOD Y OF THE COMPETENT DIIIVIIISIIION OF R&D
DEPARTMENT EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IIINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIITCONTAIIINS
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,,IIINC...

2018/03/09 2019/03/09

2

1

CV701 DIS@

10U_0603_6.3V6M

+1.35VS_VRAM Near ball

1U_0201_6.3V6M

SE00000UC00

12

Compalll Secret Data

Deciiiphered Date

2

1

SE00000UC00

CV709 DIS@

2

2

1

1

CV703 @

CV702 DIS@

22U_0603_6.3V6M

1U_0201_6.3V6M

12

10U_0603_6.3V6M

CV704 DIS@

10U_0603_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

SE00000UC00

CV710 DIS@

12

SE00000UC00

SE00000UC00

CV711 DIS@

CV712 DIS@

12

12

2

1

CV705 DIS@

10U_0603_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

SE00000UC00

CV713 DIS@

12

Tiiitttllle

N16P_GDDR5_A

DocumentttNumberrr

Siiize

LA-G202P

Dattte::: Frrriiiday,,, Marrrch 09,,, 2018

2

1

SE00000UC00

CV714 DIS@

Compal Electronics, Inc.

2

2

1

1

CV708 @

CV706 DIS@

10U_0603_6.3V6M

1U_0201_6.3V6M

12

10U_0603_6.3V6M

CV707 @

10U_0603_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

SE00000UC00

SE00000UC00

CV715 DIS@

CV716 DIS@

12

Sheettt 27 o fff55

1

1U_0201_6.3V6M

SE00000UC00

CV717 DIS@

12

CV718 @

12

Rev

1...0

5 4 3 2 1

LCD POWER SWITCH CAMERA POWER CIRCUIT

+3VS +LCDVDD_CONN

12

C217
1U_0201_6.3V6M

SE00000UC00

W=60mils

<6> PCH_ENVDD

R202 @

100K_0402_5%

D D

DISPLAY OFF

C C

Throug hEC

<36> BKOFF#

12

U202

5

IN O UT

GND

4

EN O C

EM5203AJ-20 SOT23 5P

SA00008R900

R204 1 2 0_0402_5%

1

+LCDVDD R211 1 @ 2 0_0805_5%

2
3

DISPOFF#

R205

100K_0402_5%

1

2

1 2

W=60mils

C201

4.7U_0402_6.3V6M

HOT PLUG DETECT

+3VS

W=20mils W=20mils

<6> EDP_HPD

R212 1 @ 2 0_0603_5%

R207 1 2 0_0402_5%

12

R209

100K_0402_5%

1

C202

0.1U_0201_10V KX5R

2

+3VS_CMOS

EDP_HPD_R

1

@

C203
10U_0603_6.3V6M

2

B B

eDP CONNECTOR

<6> EDP_AUXN
<6> EDP_AUXP

<6> EDP_TXP0
<6> EDP_TXN0

<6> EDP_TXP1
<6> EDP_TXN1

<30> DMIC_CLK
<30> DMIC_DAT

C206 1
C207 1

1

C208
C209 1

1

C210
C211 1

@EMI@

C216 1 2 10P_0402_ 50V8J

+3VS_CMOS

2 0.1U_0201_10V K X5R
2 0.1U_0201_10V K X5R

2 0.1U_0201_10V K X5R
2 0.1U_0201_10V K X5R

2 0.1U_0201_10V K X5R
2 0.1U_0201_10V K X5R

+3VS

W=20mils

EDP_AUXN_C
EDP_AUXP_C

EDP_TXP0_C
EDP_TXN0_C

EDP_TXP1_C
EDP_TXN1_C

EMI

A A

5 4 3 2 1

JEDP1

1
3
5
7
9 10

11
13
15
17
19
21
23
25
27
29 30

31

2

1

2

4

3

4

6

5

6

8

7

8

9

10

12

11

12

14

13

14

16

15

16

18

17

18

20

19

20

22

21

22

24

23

24

26

25

26

28

27

28

29

30

32

GND GND

ACES_87242-3001-09_30P

SP02000NB00

ME@

DISPOFF#
EDP_HPD_R

SecuriiityClllassiiifiiicatiiion

Issued Date Decipii hered Date

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL AND
TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT B E TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIIONOF R&D
DEPARTMENT EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IIINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIITCONTAIIINS
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IIINC...

USB20_N5 <12>
USB20_P5 <12>

INVPWM <6>

+LCDVDD_CONN

W=60mils

2018/03/09 2019/03/09

Compal Secret Data

R203 1 @ 2 0_0805_5%

1

C205 @

4.7U_0805_25V6-K

2

W=100mil s

Tiiittllle

Siiize Documentt Number

Custttom

B++LEDVDD

Come pal Electronics, Inc.

D
P

LA-G202P

Sheett 28 o ff 55Datte:: Friiiday,,, March 09,,, 2018

R ev

1...0

5 4 3 2 1

HDMI

EMI

EMI

Near JHDMI1

D

13

G

QH17

S

2N7002K_SOT23-3

HDMI_CLK+_CONN

HDMI_CLK-_CONN

+3VS

2

HDMI_TX0+_CONN

HDMI_TX0-_CONN

HDMI_TX1+_CONN

HDMI_TX1-_CONN

HDMI_TX2+_CONN

HDMI_TX2-_CONN

HDMI_CLK+_CONN HDMI_CLK-_CONN

HDMI_TX0+_CONN HDMI_TX0-_CONN

HDMI_TX1+_CONN HDMI_TX1-_CONN

HDMI_TX2+_CONN HDMI_TX2-_CONN

<6> TMDS_B_HPD

RH12 1 EMI@ 2 150_0402 _5%

RH13 1 EMI@ 2 150_0402_5%RH15 1 EMI@2 8.2_0402_1%

RH14 1 EMI@ 2 150_0402 _5%

RH16 1 EMI@ 2 150_0402 _5%

RH23

1M_0402_5%

12

+3VS

QH14

G

2

2N7002K_SOT23-3

S

13

D

0.1U_0201_10V KX5R

12

RH24
20K_0402_5%

@

CH12

+5VS

1

1

2

For HDMI

UH11

IN

S IC AP2330W-7 SC59 3P PW R SW

SA00004ZA00

HDMI_DET

+5V_Display

HDMIDAT_R
HDMICLK_R

HDMI_CLK-_CONN
HDMI_CLK+_CONN

HDMI_TX0-_CONN
HDMI_TX0+_CONN

HDMI_TX1-_CONN
HDMI_TX1+_CONN

HDMI_TX2-_CONN
HDMI_TX2+_CONN

3

OUT

2

GND

+5V_Display

W=40mils

JHDMI1

19

HP_DET

18

+5V

17

DDC/CEC_GND

16

SDA

15

SCL

14

Reserved

13

CEC

12

CK- GN D

11

CK_shield GND

10

CK+ GND

9

D0- GND

8

D0_shield

7

D0+

6

D1-

5

D1_shield

4

D1+

3

D2-

2

D2_shield

1

D2+

ACON_HMRA4-AK120C

DC232003J00

ME@

1

CH11

0.1U_0201_10V KX5R

2

20

21

22

23

<6> HDMI_CLK+_CK

<6> HDMI_CLK-_CK

D D

<6> HDMI_TX0+_CK

<6> HDMI_TX0-_CK

<6> HDMI_TX1+_CK

<6> HDMI_TX1-_CK

<6> HDMI_TX2+_CK

C C

<6> HDMI_TX2-_CK

B B

CH13 1 2 0.1U_0201_10V K X5R

CH14 1 2 0.1U_0201_10V K X5R

CH15 1 2 0.1U_0201_10V K X5R

CH16 1 2 0.1U_0201_10V K X5R

CH17 1 2 0.1U_0201_10V K X5R

CH18 1 2 0.1U_0201_10V K X5R

CH19 1 2 0.1U_0201_10V K X5R

CH20 1 2 0.1U_0201_10V K X5R

HDMI_CLK+_CK_C

HDMI_CLK-_CK_C

HDMI_TX0+_CK_C

HDMI_TX0-_CK_C

HDMI_TX1+_CK_C

HDMI_TX1-_CK_C

HDMI_TX2+_CK_C

HDMI_TX2-_CK_C

RH11 1 EMI@2 8.2_0402_1%

RH17 1 EMI@2 8.2_0402_1%

RH18 1 EMI@2 8.2_0402_1%

RH19 1 EMI@2 8.2_0402_1%

RH20 1 EMI@ 2 8.2_0402_1%

RH21 1 2 8.2_0402_ 1%

EMI@

RH22 1 2 8.2_0402_1%

EMI@

RPH11

45
36
27
18

470 +-5% 8P4R

RPH12

45
36
27
18

470 +-5% 8P4R

+3VS +5V_Display

2.2K_0402_5

%

12

12

RH26

<6> HDMICLK_NB

<6> HDMIDAT_NB

A A

5 4 3 2 1

+3VS

2.2K_0402_5%
RH25

2

1

5

3

4

QH15B
2N7002KDW 2N SC88-6

SB00000EO00

QH15A
2N7002KDW 2N SC88-6

SB00000EO00

6

%

12

2.2K_0402_5
RH27

%

12

2.2K_0402_5
RH28

HDMICLK_R

HDMIDAT_R

HDMIDAT_R
HDMICLK_R

HDMI_DET
+5V_Display

@ESD@

DH11

9

10

8

9

7

7

6

6

L05ESDL5V0NA-4 SLP2510P8 ESD

SecuriiityClllassiiifiiicatiiion

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL AND
TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT B E TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIIONOF R&D
DEPARTMENT EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IIINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIITCONTAIIINS
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IIINC...

1

HDMIDAT_R

1

2

HDMICLK_R

2

4

HDMI_DET

4

5

+5V_Display

5

3

3

8

Issued Date Decipii hered Date

HDMI_TX1+_CONN
HDMI_TX2-_CONN
HDMI_TX2+_CONN

2018/03/09 2019/03/09

Compal Secret Data

@ESD@

DH12

9

8

9

7

6

6

L05ESDL5V0NA-4 SLP2510P8 ESD

1

10

2

7

4

5

3

8

HDMI_TX1-_CONNHDMI_TX1-_CONN

1

HDMI_TX1+_CONN

2

HDMI_TX2-_CONN

4

HDMI_TX2+_CONN

5
3

@ESD@

HDMI_TX0-_CONN HDMI_TX0-_CONN
HDMI_TX0+_CONN
HDMI_CLK-_CONN HDMI_CLK-_CONN
HDMI_CLK+_CONN

DH13

9

10

8

9

7

7

6

6

L05ESDL5V0NA-4 SLP2510P8 ESD

Compal ElecHtronics,Inc.

Tiiittllle

Siiize Documentt Number

Custttom

Datte:: Friiiday,,, March 09,,, 2018

1

2

4

5

3

8

D

LMA-G201P

I

1

HDMI_TX0+_CONN

2
4

HDMI_CLK+_CONN

5
3

Sheett

29 o ff 55

R ev

1...0

ALC3240

A

+1.8VS

2

CA40

4.7U_0402_6.3V6M

SE00000SO00

@

1 1

<9> HDA_SDIN0

22P_0402_50V8J

wide 40M IL +MIC2-VREFO

2 2

33_0402_5% 2

<9> HDA_SDOUT_AUDIO

<9> HDA_BITCLK_AUDIO

@EMI@

CA52 33_0402 _5% 2 @EMI@1 RA50

2

RA58 1
RA54 1

2.2K_0402_5%

2

2.2K_0402_5%

GNDA

CA63 2 1 2.2U_0402_6.3V6M

GNDA GNDA

2.2U_0402_6.3V6M1 2 CA61

2.2U_0402_6.3V6M1 2 CA64

2.2U_0402_6.3V6M1 2 CA51

<9> HDA_SYNC_AUDIO

HDA_SDIN0_AUDIO

1

RA52

PC_BEEP

EXT_MIC_RING2
EXT_MIC_SLEEVE

SPK_L2+
SPK_L1­SPK_R1­SPK_R2+

+5VS to +5VDDA_CODEC

+5VS

3 3

Place RA48 on G NDA moat

1 0_060 3_5%RA48 2

1U_0201_6.3V6M

SE00000UC00

Place nea r Pin20

+5VDDA_CODEC

CA58

2 1

GNDA

1

CA55

2

0.1U_0201_10V K X5R

UA1

7

SDATA- IN

4

SDATA- OUT

11

PCBEEP

5

BCLK

13

MIC2-L(PORT-F-L)/RING

14

MIC2-R(PORT-F-R)/SLEEVE

MIC2-CAP

23

MIC2-VREFO

35

SPK-OUT-LP

36

SPK-OUT-LN

37

SPK-OUT-RN

38

SPK-OUT-RP

21

LDO1

LDO1-CAP

32

LDO2

LDO2-CAP

6

LDO3

LDO3-CAP

10

DCDET

9

SYNC

ALC3240-VA3-CG_MQFN40_5X5

+5VDDA_CODEC

Each Platform Power Net Support List：

Intel Broadwell

Intel Sky lake

Each Platform HDA Link Voltage Support (Pin 8)：

Intel Bro adwell V (default) V

Intel Skylake V

+3VDD_CODEC

1

B

2

CA53

CA1

1

4.7U_0402_6.3V6M

29

1

34

39

DVDD

HPOUT-L(PORT-I-L)

PVDD1

PVDD2

CPVDD

HPOUT-R(PORT-I-R)

LINE1-R(PORT-C-R)
LINE1-L(PORT-C-L)

LINE1-VREFO-L

HP/ LINE1-JD(JD1)

GPIO0/D MIC-DATA12

GPIO1/DMIC-CLK

THERMAL PAD

VD33STB

AVDD1

AVDD2

AVSS1

AVSS2

203319

31

16

GNDA +3VALW

RA53 1 2 0_0402_ 5%

CA60 1 2 1U_0201_6.3V6M

V (default)

1

2

CPVEE

DVDD-IO

+5VS_PVDD

0.1U_0201_10V K X5R

VREF

CBN
CBP

PDB

26

27

2415

12

2

CA66

1

25

22

CPVEE CA70 1

17 LINE1-R

18 LINE1-L

2

3

8

28
30

40 PDB
41

+1.8VS

CA49

4.7U_0402_6.3V6M

DMIC_CLK_R

1

2

0.1U_0201_10V K X5R

Headphone

CA68 1

RA2 1 @ 2 0_0805 _5%

HP_OUTL

HP_OUTR

2 1U_0201_6.3V6M

SE00000UC00

2 1U_0201_6.3V6M

SE00000UC00

+LINE1-VREFO-R

PLUG_IN_R

LA9 2 EMI@ 1 220_040 2_5%

+IOVDD_CODEC

12

CA57
1U_0201_6.3V6M

RA46 1 2 0_0402_5%

SE00000UC00

Place RA53 on G NDA moat

SE00000UC00

GNDA

Place nea r Pin33

+1.5VS +1.8VS +3VS +5VS

1.5V(S0) 1.8V(S0) 3.3V(S0) 5V(S0)

X

X

V

V V

VVV

3.3V 1.5V

C

+5VS

GNDA

SM01000Q500

EMI

RA43 @
10K_0402_5%

1 2

+3VAL W

3.3V (S0~ S5 )

External DMIC

DMIC_DAT <28>
DMIC_CLK <28>

EC_MUTE# <36>

V

V

D

Input

EMI

W=40mils
W=40mils

EXT_MIC_SLEEVE
EXT_MIC_RING2
HP_OUTL
HP_OUTR

For Universal Audio Ja ck

+LINE1-VREFO-R

HGNDA / HG NDB , W=60mils

HGNDA
HPOUT_L

PLUG_IN
HPOUT_R

HGNDB

LINE1-L CA46 1 2 1U_0201_6.3V6M
LINE1-R CA54 1 2 1U_0201_6.3V6M

RA36 1 2 4.7K_0402_5%
RA49 1 2 4.7K_0402_5%

@

1

RA63

@

1

RA64

2 0_040 2_5%

2 0_040 2_5%

@ESD@

SE00000UC00
SE00000UC00

2

3

1

HPOUT_L1

HPOUT_R1

DA8 SCA00002900

L03ESDL5V0CC3-2_SOT23-3

Output

SPEAK 4 ohm : 40MIL
SPEAK 8 ohm : 20MIL

SPK_L1-

LA7 1 2 0_0603_5%

SPK_L2+

LA8 1 2 0_0603_5%
LA5 1 2 0_0603_5%

SPK_R2+ SPK_R2+_CONN

LA6 1 2 0_0603_5%

EMI

ESD protection needs to be placed near connector side

DA3

SPK_R2+_CONN

+5VS

SPK_R1-_CONN SPK_L2+_CONN

ESD

@ESD@

6

I/O4

I/O2

5

VDD

GND

4

I/O3 I/O 1

AZC099-04S.R7G_SOT23-6

3

2

1

EMI@ EMI@

CA65

470P_0402_50V7

E

Combo Jack
(Normal Open)

1 1

CA56

CA50

2 2

K

470P_0402_50V7K

place close audio codec

+3VDD_CODEC

RA51
100K_0402_1%

1 2

PLUG_IN_R PLUG_IN

1 BLM15BD121SN1D_2P SM010009U00EMI@ RA42 2
1 BLM15BD121SN1D_2P SM010009U00EMI@ RA31 2

EMI@ RA45 1 2 47_0402_5%

EMI@ RA56 1 2 47_0402_5%

2

@ @

%

10K_0402_5

%

RA44

1 2

1

10K_0402_5

RA57

GNDA GNDA GNDA GNDA GNDA GNDA

RA23 1 2 200K_0402_1%

Combo Jack

(Normal Open)

JHP1

7

GND

3

#3G/M

1

#1L

5

#5

6

#6

2

#2R

4

1

2

EMI@ CA71

#4M/G

SINGA_2SJ3095-140111F

DC231711010

ME@

1

2

1000P_0402_50V7K

1000P_0402_50V7

K EMI@ CA47

3

ESD@

1

DA9 SCA00002900

L03ESDL5V0CC3-2_SOT23-3

2

SPK_L1-_CONN
SPK_L2+_CONN
SPK_R1-_CONNSPK_R1-

SPK_L1-_CONN

33K_0402_5

%

12

@ESD@

RA62

1

1

2

2

1000P_0402_50V7K

1000P_0402_50V7

K EMI@ CA67

EMI@ CA45

HGNDB
HGNDA

HPOUT_L
HPOUT_R

EMI@ EMI@

1 2

1 2

220P_0402_50V7

K

JSPK1

1

1

2
3

2

4
G1

3

G2

4

ACES_50278-00401-001

5

SP02000RR00

ME@

6

CA59

220P_0402_50V7

K

+3VS to +IOVDD_CODEC

+3VS

2 1

4 4

RA6

0_0603_5%

Place nea rPin 8

1

CA48

2

0.1U_0201_10V KX5R

A

+3VS to +3VDD_CODEC

+3VDD_CODEC+3VS+IOVDD_CODEC

1

2

0_0603_5%RA59

Place nea rPin 1

1

CA62

2

0.1U_0201_10V KX5R

12

CA44
1U_0201_6.3V6M

SE00000UC00

B

PC Beep

EC Beep
APU Beep

<36> BEEP#

<9> HDA_SPKR

place close audio codec

RA41 1 2 47K_0 402_5%
RA55 1 2 47K_0402_5%

SecuriiityClllassiiifiiicatiiion

Issued Date Decipii hered Date

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL AND
TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT B E TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIIONOF R&D
DEPARTMENT EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IIINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIITCONTAIIINS
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IIINC...

C

BEEP_N

CA69 2 1 0.1U_0201_10V KX5R

RA47
27K_0402_5%

SE00000SV00

Compal Secret Data

CA43 @ESD@

100P_0402_50V8

J

1

12

2

GNDA

2018/03/09 2019/03/09

D

PC_BEEP

EMI

RA65 1 @ 2 0_0402 _5%

RA60 1 @ 2 0_0402_5%

RA61 1 @ 2 0_0402_5%

RA66 1 @ 2 0_0402_5%

GND

Tiiittllle

Siiize Documentt Number

Custttom

Compal Electronics, Inc.

HD Audio Codec - ALC3240

LA-G202P

GNDA

R ev

Sheett 30 o f 55Datte:: Friiiday,,, March 09,,, 2018

E

1...0

5 4 3 2 1

LAN

+3V_LAN+3VALW

D D

1K_0402_5%

+3V_LAN

15K_0402_5%

RL1

1 2

0_0603_5%

C C

Close toPin23

B B

CL1
1U_0201_6.3V6M

SE00000UC00

1 2

+3VS

12

RL8

RL10

ISOLATE#

RL18 1 @ 2 0_0603_5%

W=40mils

+LAN_VDDREG

0.1U_0201_10V K X5R

SE00000SV00

W=60mil60mil

CL13 1 2 27P_0402_50V8J

CL14 1 2 27P_0402_50V8J

1

CL10

2

<10> LANCLK_REQ#
<12> PCIE_PTX_DRX_P5
<12> PCIE_PTX_DRX_N5

<10> CLK_PCIE_LAN

<10> CLK_PCIE_LAN#

Rising time 10%~90% Should >0.5mS and <100mS.

( )

+3V_LAN

W=60mils

1

CL2 SE00000SV00

0.1U_0201_10V K X5R

2

CL2 close to Pin 11.

CL3 close to Pin32.

XTLO

YL1

1

1

3

3

NC NC

25MHZ_20PF_XRCGB25M000F2P18R0

2

4

SJ10000UH00

CL22 1 2 0.1U_0201_10V K X5RSE00000SV00
CL23 1 2 0.1U_0201_10V K X5RSE00000SV00

XTLI

1

CL3 SE00000SV00

0.1U_0201_10V K X5R

2

0.1U_0201_10V K X5R

1

2

+LAN_ VDD

CL4 SE00000SV00

1

CL21 @

CL20 @

2

CL5 SE00000SV00

0.1U_0201_10V K X5R

1

1

2

2

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

SE00000SO00

SE00000SO00

Pin3 Pin8 Pin22 Pin30 Pin22

LAN_MDIP0
LAN_MDIN0

LAN_MDIP1
LAN_MDIN1
LAN_MDIP2
LAN_MDIN2

LAN_MDIP3

+3V_LAN

UL2

SA000065Y00
S IC RTL8106E-CG QFN 32P E-LAN CTRL

UL2

SA00005O700
S IC RTL8111GS-CG QFN 32P E-LAN CTRL
8111GLDO@

LAN_MDIN3

PCIE_PTX_C_DRX_P5 13CLKREQB
PCIE_PTX_C_DRX_N5 14HSIP

GIGAOnly

CL6 SE00000SV00

0.1U_0201_10V K X5R

CL7 SE00000SV00

0.1U_0201_10V K X5R

1

1

2

2

+LAN_ VDD

1

MDIP0

2
3 MDIN0

4 AVDD10
5 MDIP1

MDIN1

6

MDIP2

7

MDIN2

8

AVDD10

9

MDIP3

10

MDIN3

11

AVDD33

12

HSIN

15

REFCLK_P

16

REFCLK_N

UL2 RTL8111GS-CG_QFN32_4X4

SA00005O700
S IC RTL8111GS-CG QFN 32P E-LAN CTRL

@

+LAN_SROUT1.05

M

SE00000UC00

12

+LAN_ VDD

RL11 8111GLDO@
0_0603_5%

1 2

1

CL15 8111GLDO@

0.1U_0201_10V K X5R

SE00000SV00

2

RJ45_TX3­RJ45_TX3+
RJ45_RX1­RJ45_TX2­RJ45_TX2+

LED1_GPIO

RJ45_RX1+
RJ45_TX0­RJ45_TX0+

1 @

RL17 10K_0402_5%

1U_0201_6.3V6

CL8

+LAN_VDD

PCIE_PRX_C_DTX_P5

HSOP
HSON

PERSTB

ISOLATEB

LANWAKEB

DVDD10

VDDREG

REGOUT

LED2

LED1/GPIO

LED0

CKXTAL1

CKXTAL2

AVDD10

RSET

AVDD33

GND

17
18
19
20
21

25
26
27
28
29

33

22
23
24

30
31
32

PCIE_PRX_C_DTX_N5
PCI_RST#

ISOLATE#
PCIE_WAKE#

+LAN_VDDREG
+LAN_SROUT1.05

XTLO
XTLI

2.49K_0402_1% 2

CL11 1 2 0.1U_0201_10V K X5R SE00000SV00
CL12 1 2 0.1U_0201_10V K X5R SE00000SV00

TPL1TP@
TPL2TP@

1 RL9

+3V_LAN

RJ-45 Connector

JLAN1

8

PR4-

7

PR4+

6

PR2-

5

PR3-

4

PR3+

3

PR2+

2

PR1-

1

PR1+

PS_601012-008041

DC234007L00

ME@

+3V_LAN

2

Reserve GPIO Pin

12

GND

11

GND

10

GND

9

GND

PCIE_PRX_DTX_P5 <12>
PCIE_PRX_DTX_N5 <12>

PCI_RST# <10,21,33,36>
PCIE_WAKE# <33,36>

LANGAN1

LANGAN

ESDEMI

RL4 1 2 0_0402_5%
RL5 1 2 0_0402_5%

LANGAN

RL6 1 2 0_0402_5%
RL7 1 2 0_0402_5%

LANGAN1

A A

5 4 3 2 1

LAN_MDIP1 LAN_MDIN0

LAN_MDIN3

LAN_MDIP3 LAN_MDIN2

DL2

1

I/O1

2

GND

3

I/O2 I/O4

AZC099-04S.R7G_SOT23-6

SC300001G00

@ESD@

DL1

1

I/O1

2

GND

3

I/O2 I/O4

AZC099-04S.R7G_SOT23-6

SC300001G00

@ESD@

LAN_MDIP0LAN_MDIN1

4

I/O3

5

VDD

6

LAN_MDIP2

4

I/O3

5

VDD

6

DL1 Only For GIGA

EMI

EMI@ CL18

0.01U_0402_16V7K

1 2

TL1
S X'FORM_ NS892404 ETHERNET 10/100

SP050003P00

TL1
S X'FORM_ NS892407 1G

SP050006800
8111GLDO@

Securiiity Clllassiiifiiicatiiion

Issued Date

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL AND
TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIION OF R&D DEPARTMENT
EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IIINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIIT CONTAIIINS
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IIINC...

+V_DAC
LAN_MDIP3
LAN_MDIN3
+V_DAC
LAN_MDIP2
LAN_MDIN2
+V_DAC
LAN_MDIP1
LAN_MDIN1
+V_DAC
LAN_MDIP0
LAN_MDIN0

TL1

1

TCT1

2

TD1+

3

TD1-

4

TCT2

5

TD2

6

TD2-

7

TCT3

8

TD3+

9

TD3-

10

TCT4

11

TD4+
TD4-12MX4-

NS892407

@

2018/03/09 2019/03/09

24

MCT1

MX1+

MCT2

MX2+

MCT3

MX3+

MCT4

MX4+

MX1-

MX2-

MX3-

MCT

RJ45_TX3+

23

RJ45_TX3-

22
21

MCT

RJ45_TX2+

20

RJ45_TX2-

19
18

MCT

RJ45_RX1+

17

RJ45_RX1-

16
15

MCT

RJ45_TX0+

14

RJ45_TX0-

13

Compal SecretData

Deciiiphered Date

EMI

1 2

75_0805_5%

EMI@

RL19

2 1

DL3
BS4200N-C-LV_SMB-F2

@EMI@

Tiiitttllle

Siiize DocumentttNumber

C

Dattte::: Friiiday,,, March 09,,,2018

CL19

1 2

1000P_0603_50V8J

EMI@

LANGAN

Compal Electronics, Inc.

LAN RTL8106E
LA-G202P

Sheettt 31 o fff55

Rev

1...0

5 4 3 2 1

CARD READER

D D

Card ReaderIC

Main

UR1
S IC RTS5146-GR QFN 24P USB2.0 CARD READ

SA0000AW900

UR1

Second

S IC GL835-OGYL3 QFN 24P CARD READER

SA0000AVM10

GEN_CR@

+Card_3V3

CR1

+3VS

<12> USB20_N6

<12> USB20_P6

1

1

CR2

4.7U_0402_6.3V6M

SE00000SO00

2

2

C C

0.1U_0201_10V K X5R

RR2 1 @ 2 0_0402_5%
RR3 1 @ 2 0_0402_5%

*Genesys Can Un-Pop ThisOne.

+3VS

1 6.19K_0402_1%RR1 2

USB20_CR_N6
USB20_CR_P6

SD_CD_N

SD_D1

RREF

UR1

3

DM

4

DP

10

SD_CD# SDREG

15

MS_INS#

9

GPIO SP2

12

SD_DAT1 SP3

2

RREF SP5

5

3V3_IN1 SP6

6

3V3_IN2 SP7

8

3V3_IN3 SP8

24

48MHz_In SP10

25

GND

RTS5146-GR_ QFN24_4X4

SA0000AW900
@

AV18

CARD_3V3

1
7

16

SDREG
SD_WP

11

SP1

SP4

SP9

SD_D0

13
14
17
18
19

SD_CMD

20
21

SD_D3

22

SD_D2

23

CR5 2 1 1U_0201_6.3V6M

RR5 1 @ 2 0_0402_5%

SE00000UC00

1 1U_0201_6.3V6MCR4 2

SE00000UC00

SD_CLKSD_CLK_R

1

@EMI@

CR3
5P_0402_50V8C

2

+Card_3V3

B B

1

1

0.1U_0201_10V K X5R

CR7

2 2

CR6

4.7U_0402_6.3V6M

SE00000SO00

Place Close to Connector

A A

5 4 3 2 1

SD_D3
SD_CMD

SD_CLK

SD_D0
SD_D1
SD_D2
SD_CD_N
SD_WP

JSD1

1

CD/DAT3

2

CMD

3

VSS1

4

VDD

5

CLK

6

VSS2

7

DAT0

8

DAT1

G1

9

DAT2

G2

10

CD

G3

11

WP G4

DEREN_43-42095 -01111RHF-R

SP07001BB00

ME@

12
13
14
15

GNDA

Securiiity Clllassiiifiiicatiiion

Issued Date

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL AND
TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIION OF R&D DEPARTMENT
EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IIINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIIT CONTAIIINS
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IIINC...

2018/03/09 2019/03/09

Compal SecretData

Deciiiphered Date

Compal Electronics,Inc.

Tiiitttllle

Card Reader

Siiize DocumentttNumber

C

Dattte::: Friiiday,,, March 09,,,2018

LA-G202P

Sheettt 32 o fff55

Rev

1...0

A B C D E

NGFF - WLAN / BT (E- KEY)

1 1

+3VS +3VS_WLAN

R242 1 @ 2 0_0805_5%

1

C243

4.7U_0402_6.3V6M

2

2 2

1

C244

0.1U_0201_10V KX5R

@

2

1

C245
22U_0603_6.3V6M

@

2

1

C246
22U_0603_6.3V6M

@

2

LED1#

PCM_IN

LED2#

GND

COEX3
COEX2
COEX1

SUSCLK

I2C_CLK

ALERT

3.3VAUX

MTG76

4
6

8
10
12
14
16
18
20

22

32

34

36

38
40
42

44
46
48
50
52

54
56
58

60
62
64
66
68
70
72
74

76

R251

100K_0402_5%

+3VS_WLAN

WL_UART_RX

WL_UART_TX

1 2

1 2

1

R243

1

R244

SUSCLK_R
WL_RST#
BT_DISABLE_R

Note: The re al behavior of BT_DISABLE are
BT_DISABLE=LOW, BT =OFF
BT_DISABLE=HIGH, BT=ON

R252

100K_0402_5%

@

R247

R245

R248

1
1

1

R254 1 2 @0_0402_5%
R253 1 2 @0_0402_5%

2 0_0402_5%
2 0_0402_5%

2 0_0402_5%
2 0_0402_5%

2 0_0402_5%

WL_RST#

EC_TX <36>
EC_RX <36>

SUSCLK <10>

WLBT_OFF# <11>

WL_OFF# <12>

R250 1 2 0_0402_5%

UART0_RX <11>

UART0_TX <11>

UART for Intel Debug

PCI_RST# <10,21,31,36>

JWLAN1

1 2

GND 3.3VAU X

BT

WLA N

3 3

4 4

<12> USB20_P7
<12> USB20_N7

<12> PCIE_PTX_DRX_P6
<12> PCIE_PTX_DRX_N6

<12> PCIE_PRX_DTX_P6
<12> PCIE_PRX_DTX_N6

<10> CLK_PCIE_WLAN

<10> CLK_PCIE_WLAN#
<10> W LANCLK_REQ#

<31,36> PCIE_WAKE#

CC102 1
CC103 1

0.1U_0201_10V K X5R

2

R246 1
R249 1 @ 2 0_0402_5%

0.1U_0201_10V K X5R

2

2

0_0402_5%

PCIE_PTX_C_DRX_P6
PCIE_PTX_C_DRX_N6

WLANCLK_REQ#_R

WAKE#_R

3

USB_D+ 3.3VAUX

5

USB_D-

7

GND

9

SIDO_CLK

11

SDIO_CMD

13

SDO_DAT0

15

SDO_DAT1

17

SDO_DAT2

19

SDO_DAT3

21

SDIO_W AKE#

23

SDIO_RES ET#

33

GND

35

PETP0

37

PETN0 RESERVED

39

GND RESERVED

41

PERP0

43

PERN0

45

GND

47

REFCLKP0

49

REFCLKN 0

51

GND PERST0#

53

CLKEQ0# W_DISABLE2#

55

PEWAK E0# W_DISABLE1#

57

GND

59

RSRVD/PETP1

61

RSRVD/PETN1

63

GND

65

RSRVD/PERP1

67

RSRVD/PERN1

69

GND

71

RESERVED

73

RESERVED 3.3VAUX

75

GND

77

MTG77

LOTES_APCI0128-P005A

SP070011H00
ME@

UART_WAKE#

UART_CTS
UART_RTS

PCM_CLK

PCM_SYNC

PCM_OUT

UART_RX

UART_TX

RESERVED

I2C_DAT A

RESERVED
RESERVED
RESERVED
RESERVED

SecuriiityClllassiiifiiicatiiion

Issued Date Decipii hered Date

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL AND
TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT B E TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIIONOF R&D
DEPARTMENT EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IIINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIITCONTAIIINS

A B C D E

MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IIINC...

2018/03/09 2019/03/09

Compal Secret Data

Tiiittllle

Siiize Documentt Number

Datte:: Friiiday,,, March0F9,,,2018

ComNpal Electronics,Inc.

G
F

LA-G202P

Sheett 33 o ff 55

R ev

1...0

A

B

C

D

E F G

H

HDD FFC Connector to Sub Board

1 1

+5V_HDD+5VS

R233 1 @ 2 0_0805_5%

1000P_0402_50V7K

1

1

C237

@

2

2

10U_0603_6.3V6

M

0.1U_0201_10V KX5R

1

C238

C232

2

2 2

<12> SATA_PRX_DTX_P0
<12> SATA_PRX_DTX_N0

<12> SATA_PTX_DRX_N0
<12> SATA_PTX_DRX_P0

ESD

3 3

+5V_HDD

C239

1 2

0.1U_0201_10V KX5R

@ESD@

Place Near Connector

C236 1 2 0.01U_0402_ 16V7K
C235 1 2 0.01U_0402_ 16V7K

C234 1 2 0.01U_0402_ 16V7K
C233 1 2 0.01U_0402_ 16V7K

+5V_HDD

SATA_PRX_C_DTX_P0
SATA_PRX_C_DTX_N0

SATA_PTX_C_DRX_N0
SATA_PTX_C_DRX_P0

JHDD1

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

G11

9

10

10 G12

ACES_51530-01001-P01

SP010025K00

ME@

11

12

4 4

SecuriiityClllassiiifiiicatiiion

Issued Date Decipii hered Date

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL AND
TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT B E TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIIONOF R&D
DEPARTMENT EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IIINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIITCONTAIIINS

A

B

C

D

MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IIINC...

2018/03/09 2019/03/09

E F

Compal Secret Data

Tiiittllle

Siiize Documentt Number

Custttom

G

ComHpal Electronics,Inc.

D
D

LA-G202P

Sheett 34 o ff 55Datte:: Friiiday,,, March 09,,,2018

H

R ev

1...0

A

B

ODD Connector (14" Only)

C

D

E F G

H

1 1

<12> SATA_PTX_DRX_P1
<12> SATA_PTX_DRX_N1

<12> SATA_PRX_DTX_N1

<12> SATA_PRX_DTX_P1

<11> HDD_ODD_DETECT

2 2

ODD FFC Connector to Sub Board (15" Only)

SATA_PTX_DRX_P1
SATA_PTX_DRX_N1

SATA_PRX_DTX_N1
SATA_PRX_DTX_P1

HDD_ODD_DETECT

SATA_PTX_DRX_P1
SATA_PTX_DRX_N1

SATA_PRX_DTX_N1
SATA_PRX_DTX_P1
HDD_ODD_DETECT

Place on TOP

C2146 1 2
C2145 1 2

C2143 1 2
C2144 1 2

0.01U_0402_16V7K14@

0.01U_0402_16V7K14@

0.01U_0402_16V7K14@

0.01U_0402_16V7K14@

+5V_ODD

+5V_ODD

SATA_PTX_C_DRX_P1
SATA_PTX_C_DRX_N1

SATA_PRX_C_DTX_N1
SATA_PRX_C_DTX_P1

JODD1

1

GND

2

A+

3

A-

4

GND

5

B-

6

B+

7

GND

8

DP

9

+5V

10

+5V

11

MD

12

GND

13

GND G ND

ALLTO_C185S1-11 3H9-L

SP011312061

ME@

JODD2

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9 G11

10

10 G12

ACES_51530-01001-P01

SP010025K00

ME@

15

GND

14

11
12

3 3

ODD MISC.

+5V_ODD+5VS

R420 1 @ 2 0_0805_5%

4 4

K

1

@

2

SecuriiityClllassiiifiiicatiiion

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL AND
TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT B E TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIIONOF R&D
DEPARTMENT EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IIINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIITCONTAIIINS

A

B

C

D

MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IIINC...

0.1U_0201_10V KX5R

1000P_0402_50V7

1

C2148

14@

2

Issued Date Decipii hered Date

10U_0603_6.3V6

M

1

C2147

C2149

14@

2

2018/03/09 2019/03/09

E F

Compal Secret Data

Tiiittllle

Siiize Documentt Number

Custttom

G

Compal Electronics, Inc.

ODD

LA-G202P

Sheett

35 off 55Datte:: Friiiday,,, March 09,,,2018

H

R ev

1...0

L101

+3VALW_EC +EC_VCCA

1 2

BLM15AX601SN1D _2P

SM010 00KL00

0.1U_0201_10V K X5R

L102

1

2 ECAGND

BLM15AX601SN1D _2P

SM01000KL00

C106

1

1

C107
1000P_0402_50V7K

@

2

2

ECAGND

EMI

<38> KSO[0..17]

<38> KSI[0..7]

+3VL

R108 1
R109 1

+3VS

R118 1 2 10K_04 02_5%

+3VALW

R106 1 @ 2 10K_040 2_5%

+3VALW_EC

2 2.2K_0402_5%
2 2.2K_0402_5%

@EMI@

1 22P_0402_50V8JC108 2

R104 1 @ 2 47K_0402_5%

KSO[0..17]
KSI[0..7]

EC_SMB_CK1
EC_SMB_DA1

EC_FAN_SPEED1

PBTN_OUT#

@EMI@

C109

0.1U_0201_10V K X5R

2

1

@

1 10_0402_1%R103 2

<8> PM_CLKRUN#

<8> SERIRQ

<8> LPC_FRAME#

<8> LPC_AD3

<8> LPC_AD2
<8> LPC_AD1
<8> LPC_AD0

<8> CLK_LPC_EC

<10,21,31,33> PCI_RST#

<6,10> EC_SCI#

<42,43> EC_SMB_CK1
<42,43> EC_SMB_DA1

<8,24> EC_SMB_CK2
<8,24> EC_SMB_DA2

<10> PM_SLP_S3#

<10> EC_CLEAR_CMOS#

<39> EC_FAN_SPEED1

<33> EC_TX
<33> EC_RX

<10> PCH_PWROK

<48> VR_PWRGD

<10> PBTN_OUT#

<10,43,46> PM_SLP_S4#

+3VL +3VL

R102 1 @ 2 0_0603_5%

1

1

C103

0.1U_0201_10V KX5R

C102

0.1U_0201_10V KX5R

2

PCI_RST#
EC_RST#

PM_CLKRUN#_R

2

1 @

R428 0_0402_5%

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17

EC_SMB_CK1
EC_SMB_DA1

EC_FAN_SPEED1
VCIN1_AC_IN_R

PCH_PWROK
VR_PWRGD

PBTN_OUT#

2

1

C104

1000P_0402_50V7

K

2

@

U11

1
2 G ATEA20/GPIO00

3 KB RST#/G PIO01
4 SE RIRQ

LPC_FRAME#

5

LPC_AD3

7

LPC_AD2

8

LPC_AD1

10

LPC_ADL0

12

CLK_PCI_EC

13

PCIRST# /GPIO05

37

EC_RST #

20

EC_SCI#/GPIO0E

38

CLKRUN#/GPIO1D

55

KSI0/GPIO 30

56

KSI1/GPIO 31

57

KSI2/GPIO 32

58

KSI3/GPIO 33

59

KSI4/GPIO 34

60

KSI5/GPIO 35

61

KSI6/GPIO 36

62

KSI7/GPIO 37

39

KSO0/GPIO20

40

KSO1/GPIO21

41

KSO2/GPIO22

42

KSO3/GPIO23

43

KSO4/GPIO24

44

KSO5/GPIO25

45

KSO6/GPIO26

46

KSO7/GPIO27

47

KSO8/GPIO28

48

KSO9/GPIO29

49

KSO10/G PIO2A

50

KSO11/G PIO2B

51

KSO12/G PIO2C

52

KSO13/G PIO2D

53

KSO14/G PIO2E

54

KSO15/G PIO2F

81

KSO16/G PIO48

82

KSO17/G PIO49

77

EC_SMB_CL K1/GPIO 44

78

EC_SMB_DA T1/GPIO45

79

EC_SMB_CL K2/GPIO 46

80

EC_SMB_DA T2/GPIO47

6

PM_SLP_S3 #/GPIO 04

14

GPIO07

15

GPIO08

16

GPIO0A

17

GPIO0B

18

GPIO0C

19

AC_PRESENT/GPIO0D

25

PWM2/GPIO11

28

FAN_SPEED1/GPIO14

29

FANFB1/GPIO15

30

EC_TX/ GPIO16

31

EC_RX/G PIO17

32

PCH_PW ROK/G PIO18

34

SUSP_LED #/GPIO19

36

NUM_LED#/GPIO 1A

122

PBTN_O UT#/G PIO5D

123

PM_SLP_S4 #/GPIO 5E

1000P_0402_50V7

K

+3VALW _EC

1

C105

2

@

PC &MISC

Int. K/B

Matrix

+EC_VCCA

9223396111

125

VCC

VCC

VCC

VCC

VCC0

CC_LPC

V

PWM Output

VCIN1_BATT_T EMP/AD0/GPIO38
VCIN1_BATT_DROP/AD1/GPIO39

AD Input

DA Output

EC_MUTE#/PSCLK1 /GPIO4A

PS2Interface

SPI Device Interface

SPI FlashROM

GPIO

SMBus

VCIN1_ADP_PROCH OT/GPXIOA05

VCOUT 1_PROCHOT#/GPXIOA06

VCOUT 0_MAIN_PW R_ON /GPXIOA0 7

GPIOGPO

PWR_VCCST_ PG/GPXIO A11

GPI

GND

GND

GND

GND

GND

112435

94

113

1

C101
100P_0402_50V8J

@

2

67

AVCC

EC_VCCST_PG/G PIO0F

BEEP#/GPIO10

EC_FAN_ PWM/G PIO12

AC_OFF /GPIO13

ADP_I/AD2/GPIO3 A

AD_BID/AD3/GPIO3 B

AD4/GPIO 42
AD5/GPIO43

DA0/GPIO 3C

EN_DFAN 1/DA1/G PIO3D

DA2/GPIO 3E

DA3/GPIO 3F

USB_EN#/PSDAT1 /GPIO4B

PSCLK2/G PIO4C
PSDAT2/GPIO4D

TP_CLK/GPIO4E

TP_DAT A/GPIO 4F

ENKBL/GPXIOA00

WOL_EN/GPXIOA01

ME_EN/GPXIOA02

VCIN0_PH1/GPXIOD 00

MISO/GPIO 5B
MOSI/GPIO 5C

SPICLK/GPIO58

SPICS#/GPIO5A

EC_CIR_R X/AD6/G PIO40

SYS_PW ROK/AD 7/GPIO41

BATT_CHG_LED#/GPIO52

BATT_LOW_LED#/GPIO55

EC_RSMRST#/GPXIOA03

PCH_PW R_EN/GPXIOA10

ECAGND 69

GPIO50

CAPS_LED #/GPIO5 3

PWR_LED#/GPIO54

SYSON/G PIO56

VR_ON/GPIO57

DPWR OK_EC/G PIO59

GPXIOA04

BKOFF#/GPXIOA08

GPXIOA09

VCIN1_AC_IN/GPXIOD01

EC_ON/GPXIOD02

ON/OFF#/GPXIO D03

LID_SW #/GPXIO D04

SUSP#/GPXIOD05

GPXIOD06

PECI/GPXIOD07

V18R/VCC_IO2

AGND

KB9022QD_LQFP128_14X14

SA000075S30

21
23
26

27

63

64
65

66
75

76

68

70

71
72

83

84

85

86

87
88

97

98
99

109

119
120
126
128

73
74
89
90
91
92
93
95
121
127

100
101
102
103
104
105
106

107
108

110

112

114 ON/OFF#
115
116
117
118

124

VCCST_PWRGD

EC_VCIN1_AC_BYPASS_R

NOVO#

USB_EN#

EC_MUTE#
BATT_CHG_LED#

BATT_LOW_LED#
SYSON

VCOUT1_PROCHOT#

EC_VCIN1_AC_BYPASS

SUSP#
PECI

VCC_IO2

1

R114 43_0402_1%

1 @

R115 0_0402_5%

1

C114

4.7U_0402_6.3V6M

2

VCCST_PWRGD <10>
BEEP# <30>
EC_FAN_PWM1 <39>

VCIN1_BATT_TEMP <42,43>
VCIN1_BATT_DROP <44>
ADP_I <43>
CUST_TEMP3 <39>

CUST_TEMP2 <39>

NOVO# <39>

TP_DISABLE# <38>

DGPU_PWR_EN <11,26>
USB_EN# <37>

GPU_PROHOT# <24>

ENBKL <6>
SYS_PWROK <10>
ME_EN <9>
VCIN0_PH1 <42>

EC_SPI_MISO <8>
EC_SPI_MOSI <8>
EC_SPI_CLK <8>
EC_SPI_CS0# <8>

CUST_TEMP1 <39>

EC_MUTE# <30>

BATT_CHG_LED# <39>
CAPS_LED# <38>

PWR_LED# <38,39>

BATT_LOW_LED# <39>

SYSON <13,45>
VR_ON <48>
AC_PRESENT <10,24>

EC_RSMRST# <10>

3V/5VALW_PG <40,44,46>

VCOUT1_PROCHOT# <43>
VCOUT0_MAIN_PWR_ON <44>

BKOFF# <28>

1 2

R1260 0_0402_5%

EC_ON <44>

ON/OFF# <38,40>

LID_SW# <38>
SUSP# <13,40,45>
NUM_LED# <38>

2

2

+3VALW_EC

PCIE_WAKE#EC_PCIE_WAKE#

H_PECI <6>

PCIE_WAKE# <31,33>

VCOUT1_PROCHOT#

<48> VR_HOT#

USB_EN#

VCIN1_BATT_TEMP
VCIN1_AC_IN

LID_SW#

EC_MUTE#

PCIE_WAKE#

NOVO#

R1259 1 2 100K_0402_5%

ON/OFF#

R170 1 2 100K_0402_5%

SUSP#

R111 1 2 0_0402_5%

R112 1 2 0_0402_5%

R105 1 2 10K_04 02_5%

C111 1 2 100P_0402_50V8J
C112 1 2 100P_0402_50V8J
R110 1 @ 2 4.7K_0402_5%

R273 1 @ 2 100K_0402_5%

R107 1 @ 2 10K_0402_5%

1 1K_0402_5%R117 2

ESD

R129 1 2 100K_04 02_5%

1

C113 ESD@
100P_0402_50V8J

2

+5VALW

+3VALW

1

C116 @ESD@

0.1U_0201_10V KX5R

2

+3VL

H_PROCHOT# <6>

ESD

<43> VCIN1_AC_IN

EC_VCIN1_AC_BYPASS_R

pin27

R425 1 @ 2 0_0402_5%

R426 1 @ 2 0_0402_5%

R4271@

2 0_0402_5%

EC_VCIN1_AC_BYPASS

VCIN1_AC_IN_R

EC_VCIN1_AC_BYPASS

pin110

pin29

pin110

ESD

3V/5VALW_PG

C122 SE00000SV00

0.1U_0201_10V K X5R

ESD@

1

2

SecuriiityClllassiiifiiicatiiion

Issued Date Decipii hered Date

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL AND
TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT B E TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIIONOF R&D
DEPARTMENT EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IIINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIITCONTAIIINS
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IIINC...

2018/03/09 2019/03/09

PCI_RST# PCH_PWROK VR_PW RGD

C110 SE00000SV00

0.1U_0201_10V K X5R

ESD@

1

2

C121 ESD@

100P_0402_50V8

J

1

2

Compal Secret Data

C119 ESD@

100P_0402_50V8

J

1

2

VCCST_PWRGD BATT_CHG_LED# BATT_LOW _LED#

C120 @ESD@

100P_0402_50V8J

1 1 1

C117 @ESD@

100P_0402_50V8

J

2

Tiiittllle

Siiize Documentt Number

Custttom
Datte:: Friiiday,,, March0K9,,,2018

2

ComE pal Electronics, Inc.

C

B

SYSON

C118 @ESD@

100P_0402_50V8

J

2

LA-G202P

Sheett 36 o ff55

C115 ESD@

0.1U_0201_10V KX5R

1

2

R ev

1...0

5

4

3

2

1

USB 3.0 (PORT 2)

Intel_PCH_USB2.0

D D

<12> USB20_N2

<12> USB20_P2

Intel_PCH_USB3.0

<12> USB3_RX2_N

<12> USB3_RX2_P

C301

0.1U_0201_10V KX5R

C C

<12> USB3_TX2_N

<12> USB3_TX2_P

1 2

C302

0.1U_0201_10V KX5R

1 2

Place TX AC coupling Cap (C172,173). Cl ose to connecto r

L301 EMI@

1

1

4

4

DLM0NSN900HY2D_4P

SM070005U00

2

2

3

3

U2DN2

U2DP2

+USB3_VCCA

W=80mils

USB3_RX2_N

USB3_RX2_P

U3TXDN2_L

U3TXDP2_L

USB3_RX2_N
USB3_RX2_P
U3TXDN2_L
U3TXDP2_L

ESD@

D301

9

10

8

9

7

7

6

6

L05ESDL5V0NA-4 SLP2510P8 ESD

SC300002C00

USB3_RX2_N

1

1

USB3_RX2_P

2

2

4

4

5

5

3

3

8

U3TXDN2_L
U3TXDP2_L

U2DP2

D302 ESD@

3

2

1

I/O4

I/O2

VDD

GND

I/O1 I/O 3

L30ESDL5V0C6-4_SOT23-6

SC300004W00

6

5

+USB3_VCCA

4

U2DN2

U3TXDP2_L
U3TXDN2_L

U2DP2
U2DN2

USB3_RX2_P
USB3_RX2_N

JUSB1

9

STDA_SST X+

1

VBUS

8

STDA_SSTX-

3

D+

4

GND_1

2

D-

6

STDA_SSRX+

7

GND_2

5

STDA_SSRX-

10

GND1

11

GND2

12

GND3

13

GND4

ACON_TARAN-9R1391

DC23300EQ00

ME@

ESD@

U2DP3

9
8
7
6

3

2

1

+USB3_VCCA

D304

10

9

7

6

L05ESDL5V0NA-4 SLP2510P8 ESD

SC300002C00

D305 ESD@

I/O2

GND

I/O1 I/O3

L30ESDL5V0C6-4_SOT23-6

SC300004W00

1

2

4

5

3

8

I/O4

VDD

USB3_RX3_N

1

USB3_RX3_P

2

4
5
3

6

5

4

U3TXDN3_L
U3TXDP3_L

W=80mils

JUSB2

9

STDA_SSTX+

1

VBUS

8

STDA_SSTX-

3

D+

4

GND_1

2

D-

6

STDA_SSRX+

7

GND_2

5

STDA_SSRX-

10

GND1

11

GND2

12

GND3

13

GND4

ACON_TARAN-9R1391

DC23300EQ00

ME@

+USB3_VCCA

U2DN3

USB 3.0 (PORT 3)

USB3_RX3_N
USB3_RX3_P
U3TXDN3_L
U3TXDP3_L

Intel_PCH_USB2.0

L304 EMI@

1

B B

<12> USB20_N3

<12> USB20_P3

1

4

4

DLM0NSN900HY2D_4P

SM070005U00

2

2

3

3

U2DN3

U2DP3

Intel_PCH_USB3.0

<12> USB3_RX3_N

<12> USB3_RX3_P

C2150

0.1U_0201_10V K X5R

<12> USB3_TX3_N

A A

<12> USB3_TX3_P

1 2

C2151

0.1U_0201_10V K X5R

1 2

USB3_RX3_N

USB3_RX3_P

U3TXDN3_L

U3TXDP3_L

U3TXDP3_L
U3TXDN3_L

U2DP3
U2DN3

USB3_RX3_P
USB3_RX3_N

Place TX AC coupling Cap (C2150,2151). C lose to connec tor

5

4

USB 3.0 MISC.

+5VALW +USB3_VCCA

2A/Active Low

W=80mil s

<36> USB_EN #

Security Classification

Issued Date Decipherii ed Date

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONICS,,, IIINC.. AND CONTAIIINS CONFIIIDENTIIIAL AND
TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT B E TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIVIIISIIION OF R&D
DEPARTMENT EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONICS,,, IIINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIIT CONTAIIINS
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IIINC..

3

2018/03/09 2019/03/09

USB_EN#

C305

0.1U_0201_10V KX5R

Compal Secret Data

U301

5

IN

4

EN

1

S IC G524B2T11U SOT-23 5P POW ER SWITCH

SA00007BW00

2

2

1

OUT

2

GND

3

OCB

W=80mil s

USB_OC1#_U301

K

220U_6.3V_M

1

C304

1

+

@

2

2

Tiiittllle

Siiize Document Number

Custttom

Datte:: Friiiday,,, March 09,,2018

470P_0402_50V7

1

C303

R301

0_0402_5%

2

@

US

LA-G202P

B

3

USB_OC1# <12>

Sheett 37 o ff 55

1

R ev

1...0

KEYBOARD

KSI[0..7]

KSO[0..17]

HALL SENSOR

KSI[0..7] <36>
KSO[0..17] <36>

<36> NUM_LED#

<36,39> PWR_LED#

<36,40> ON/OFF#

+5VALW
+3VALW

<36> CAPS_LED#

KSO16
KSO17

CAPS_LED#

R272 1
R283 1 @ 2 0_0402_5%

2

470_0402_5%

0.1U_0201_10V K X5R 2 0.1U_0201_10V K X5R

C272

@ESD@

0.1U_0201_10V KX5R

1

@ESD@

2

1

1 0_0402_5%R278 2 @

C275

@ESD@

1 0_0402_5%R271 2 @

2

1

L03ESDL5V0CC3- 2_SOT23- 3

R274 1 2 470_0402_5%

C271

R275 1 @ 2 0_0402_ 5%
R276 1 @ 2 0_0402_ 5%
R277 1 15@ 2 470_0402_5%

TOUCH PAD

PWR_CAPS_LED
CAPS_LED#_R

SCA00002900

ESD@

D303

KSO16_R
KSO17_R

NUM_LED#_R

2

3

1

KSO15
KSO10
KSO11
KSO14
KSO13
KSO12

KSO3
KSO6 10
KSO8 11
KSO7 12
KSO4 13
KSO2 14
KSI0
KSO1 16
KSO5 17
KSI3
KSI2
KSO0 20
KSI5
KSI4
KSO9 23
KSI6
KSI7
KSI1

27
28

29

JKB1

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10
11
12

13

14

15

15
16

17

18

18

19

19

20

21

21

22

22

23

24

24

25

25

26

26

27 GND

34

28 GND

29

30

30

31

31

32

32

JXT_FP257H-032S10M

SP01002FA00

ME@

33

+3VS

+3VALW

0.1U_0201_10V KX5R

C2152

1

2

2

OUTPU T

GND VDD

U282

1

APX8132 SOT-23F 3P

SA00008K800

R279 1 @ 2 0_0805_5%

+3VS

12

R280

4.7K_0402_5%

<11> I2C0_SCL_TP

3

1

C2153
10P_0402_50V8J

2

LID_SW# <36>

SecuriiityClllassiiifiiicatiiion

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL AND
TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT B E TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIIONOF R&D
DEPARTMENT EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IIINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIITCONTAIIINS
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IIINC...

<11> I2C0_SDA_TP

<11> TP_INT#

<36> TP_DISABLE#

1

1

C281

100P_0402_50V8J

Issued Date Decipii hered Date

2018/03/09 2019/03/09

C282
100P_0402_50V8J

2

2

@

@

Compal Secret Data

ESD

PSOT24C_SOT23-3

D281

@ESD@

0.1U_0201_10V KX5R

C280

@

TP_VCC

TP_INT#LID_SW#

2

3

1

Tiiitllle

Siiize Document Number

Custttom

Date: Friiiday,,, March 09,,,/2018

JTP1

6

8

6 G ND

5

7

5 GND 4

4

3

3

2

2

1

1

ACES_51522-00601-001

SP01001A800

ME@

ComKpal Electronics,Inc.

B

LA-G202P

Sheet 38 o f 55

R ev

1...0

5

THERMISTOR

4

3

2

1

CHARGER VRAM

D D

<36> CUST_TEMP1 <36> CUST_TEMP2

C C

FAN

+5VS

2

C371
10U_0603_6.3V6M

1

1 @ 2

R371
0_0603_5%

<36> EC_FAN_PWM1

<36> EC_FAN_SPEED1

+5VS_FAN

JFAN1

1

1

2

2

3

3

4

4

5

GND1

6

GND2

ACES_50271-0040N-001

SP02000TS00

ME@

+EC_VCCA

12

R364

16.5K_0402_1%

@

12

R366
100K +-1% 0402 B25/50 4250K

SL200002H00
@

ECAGND

LED

+EC_VCCA

12

R365

16.5K_0402_1%

@

12

R367
100K +-1% 0402 B25/50 4250K

SL200002H00
@

ECAGND

<36,38> PW R_LED#

CPU CHOKE

<36> CUST_TEMP3

PWR_LED#

+EC_VCCA

ECAGND

Power ( White )

LED2

1 2

LTW -C193TS5-C_WHITE

SC50000BB10

12

R368

16.5K_0402_1%

@

12

R369
100K +-1% 0402 B25/50 4250K

SL200002H00
@

R377 1 2 412_04 02_1%

+5VALW

B B

Batter y ( White )

<36> BATT_CHG_LED#

BATT_CHG_LED#

NOVO BUTTON

SW1

SN100006A10
S TACT SW TAFG1-12W QR4 SPST DIP H3.3 3P

1

2 NOVO#

3

G

7 G6 G5 G4

A A

ESD

2

3

1

NOVO# <36>

D1
L03ESDL5V0CC3- 2_SOT23- 3

SCA00002900
ESD@

SecuriiityClllassiiifiiicatiiion

Issued Date Decipii hered Date

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL AND
TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT B E TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIIONOF R&D
DEPARTMENT EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IIINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIITCONTAIIINS

5

4

MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IIINC...

3

<36> BATT_LOW_LED#

2018/03/09 2019/03/09

BATT_LOW_LED#

Compal Secret Data

LED3

1

2 R376 1

LTW -C193TS5-C_WHITE

SC50000BB10

Batter y ( Amber )

LED4

1

2 R378 1

A

LTST-C191KFKT-2CA_ORANGE

SC500005930

2

2 200_0402_1%

2 200_0402_1%

Tiiitllle

Siiize Document Number

Custttom

+VL

+VL

Compal Electronics, Inc.

FAN / Thermal / LED / NOVO

LA-G202P

1

R ev

Sheet 39 o f 55Date: Friiiday,,, March 09,,,2018

1...0

A

DC to DC

B

C

D

E

1 1

<13,36,45> SUSP#

+3VALW

0.1U_0201_10V KX5R

+5VALW

0.1U_0201_10V KX5R

1

J5

2 1

JUMP_43X79

+3VS

10U_0603_6.3V6M

0.1U_0201_10V KX5R
C385

1

C384

1

@

2

2

+5VS

1

10U_0603_6.3V6M

0.1U_0201_10V K X5R

C389

1

2

C390

1

@

2

RF By-Pass / Cross Moat Caps

+3VS +3VS +5VALW +VGA_CORE+VCCGT+3VS

@RF@12

0.1U_0201_10V KX5R

0.1U_0201_10V KX5R

@RF@12

CC53

0.1U_0201_10V KX5R

CC99

2

@RF@

1

@RF@12

CC100

0.1U_0201_10V KX5R

@RF@12

CC105

0.1U_0201_10V KX5R

0.1U_0201_10V KX5R
CC125

@RF@12

CC121

J4

10U_0603_6.3V6M

1

1

C382

C381

@

2

2

10U_0603_6.3V6M

C388

C387

1

1

@

2

2

+VL

+3VALW to +3VS

U381

1

VOUT1

VIN1

VOUT1

VIN1

3

4
5
6

7

CT1

ON1

GND

VBIAS
ON2

CT2

VIN2

VOUT2

VIN2

VOUT2

GPAD

S IC JW7110DFNC#TRPBF DFN14 DUAL LOAD SW

SA0000BEL00

+3VALW_3VS

14
132

12

C383 1 2 S CER CAP 1000P 50V K X7R 0402

11
10 C386 1 2 S CER CAP 2200P 25V K X7R 0402

+5VALW_5VS

9 2
8

15

SE074102K80

SE075222K80

122

JUMP_43X79

+5VALW to +5VS

2 2

DISCHARGE CIRCUIT MISC.

CPU

H1 H2 H3
HOLEA HOLEA HOLEA

1

H8
HOLEA

1

H_2P5

H13
HOLEA

1

H_2P5

1

H9
HOLEA

1

H_2P5

For +1.8VALWDischarge

3 3

12

R401 @
100K_0402_1%

1.8VALW_PWR_EN#

2N7002KDW_SOT363-6

61

D

<36,44,46> 3V/5VALW_PG

4 4

2

G

@ Q401A

2N7002KDW_SOT363-6

S

5

G

@ Q401B

+1.8VALW+5VALW

12

R402 @
22_0603_1%

34

D

S

1

H_3P3 H_3P3 H_3P3

DC IN

MISC.

H12
HOLEA

1

H_2P5

VGA LAN

H4
HOLEA

1

H_3P3

FAN

H10
HOLEA

1

H_2P5

H14

H15

HOLEA

HOLEA

1

H_3P5X2P5N

1

H_3P2

H5
HOLEA

1

H_3P3

H11
HOLEA

1

H_3P2N

H6
HOLEA

1

H_2P5

FD1 FD2 FD3 FD4

1

1

BATTERY

H7
HOLEA

1

H_2P5

1

1

ON/OFF# SHORT PADS

@

JP3 2 1 ON/OFF#

SHORT PADS

@

JP4 2 1 ON/OFF#

SHORT PADS

LASER BARCODE

CODE1 @

BARCODE_8X8

CODE3 @

BARCODE_20X4

ON/OFF# <36,38>

CODE2 @

BARCODE_12X4

CODE4 @

BARCODE_10X10

SecuriiityClllassiiifiiicatiiion

Issued Date Decipii hered Date

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL AND
TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT B E TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIIONOF R&D
DEPARTMENT EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IIINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIITCONTAIIINS

A

B

MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IIINC...

C

2018/03/09 2019/03/09

Compal Secret Data

Tiiittllle

Siiize Documentt Number

Custttom

D

Compal Electronics,Inc.

DC to DC / Discharge / MISC

LA-G202P

Sheett 40 o ff 55Datte:: Friiiday,,, March 09,,, 2018

E

R ev

1...0

5 4 3 2 1

EMI@ PL101

5A_Z80_0805_2P

2 1

100P_0402_50V8J

EMI@ PC102

1 2

EMI@ PL102

5A_Z80_0805_2P

1 2

+3VL

JRTC1 CONN@

1

1

2

2

3

GND

4

GND

ACES_50271-0020N-001

SINGA_2DC3169-000111F

1 APDIN

PIN+

2

SPRING-

5

SPRING-

3

SHELL

4

SHELL

JDCIN1

D D

C C

PD101

LRB715FT1G_SOT323-3

+RTCBATT

1

PF101

7A_32VDC_0437007.WRML

1 2

PR107

+CHGRTC

45.3K_0603_1%

1 2

2

3

1K_0603_5%

1 2

PR109

+19V_APDIN

2 1

1000P_0402_50V7K

EMI@ PC101

PR108

1.5K_0603_5%

1 2

+CHGRTC_R

2 1

+19V_VIN

2 1

100P_0402_50V8J

EMI@ PC103

1000P_0402_50V7K

EMI@ PC104

B B

A A

Security Classification

Issued Date

THIIS SHEET OF ENGIINEERIING DRAWIING IIS THE PROPRIIETARY PROPERTY OF COMPAL ELECTRONIICS,, IINC.. AND CONTAIINS CONFIIDENTIIAL
AND TRADE SECRET IINFORMATIION.. THIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIVIISIION OF R&D
DEPARTMENT EXCEPT AS AUTHORIIZED BY COMPAL ELECTRONIICS,, IINC.. NEIITHER THIIS SHEET NOR THE IINFORMATIION IIT CONTAIINS

5 4 3 2 1

MAY BE USED BY OR DIISCLOSED TO ANY THIIRD PARTY WIITHOUT PRIIOR WRIITTEN CONSENT OF COMPALELECTRONIICS,, IINC..

2018/03/09 2019/03/09

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Tiiitllle

PWR- DCIN / Vin Detector

Siiize Document Number

Custom

KBL

Date: Sheet 41 o f 55

Friiiday, March 09, 2018

R ev

1.0

5 4 3 2 1

EMI@ PL201

5A_Z80_0805_2P

1 2

EMI@ PL202

5A_Z80_0805_2P

1 2

12

PC201 EMI@
1000P_0402_50V7K

EC_SMB_CK1 <36,43>

EC_SMB_DA1 <36,43>
+3VL
+3VALW

VCIN1_BATT_TEMP <36,43>

+12.6V_BATT+

12

PC202 EMI@

0.01U_0402_16V7K

Change 16V for 2S1P

PH201 under CPU botten side :
CPU thermal protection at 93 +-3 degree C

PR203
200K_0402_1%

+8.4V_VMB

JBAT1

VMB2

1

1

2

2

3

3

4

4

5
6

5

7

6

8

7

9

D D

SUYIN_125022HB008M200ZL

GND
GND
GND
GND

CONN@

8

10
11
12

EC_SMDA

EC_SMCA

12

PF201

F1206HB12V024TM 12A 24V ULFAST

1 2

12

PR201

100_0402_1%

PR202

100_0402_1%

1 2

1 2

PR204

@200K_0402_1%

1 2

PR205
10K_0402_5%

Recovery at 56 +-3 degree C

+EC_VCCA

C C

<36> VCIN0_PH1

12

PR206

16.5K_0402_1%

12

PH201
100K +-1% 0402 B25/50 4250K

ECAGND

B B

A A

Security Classification

Issued Date

THIIS SHEET OF ENGIINEERIING DRAWIING IIS THE PROPRIIETARY PROPERTY OF COMPAL ELECTRONIICS,, IINC.. AND CONTAIINS CONFIIDENTIIAL
AND TRADE SECRET IINFORMATIION.. THIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIVIISIION OF R&D
DEPARTMENT EXCEPT AS AUTHORIIZED BY COMPAL ELECTRONIICS,, IINC.. NEIITHER THIIS SHEET NOR THE IINFORMATIION IIT CONTAIINS

5 4 3 2 1

MAY BE USED BY OR DIISCLOSED TO ANY THIIRD PARTY WIITHOUT PRIIOR WRIITTEN CONSENT OF COMPALELECTRONIICS,, IINC..

2018/03/09 2019/03/09

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Tiiitllle

PWR- BATTERY CONN/OTP

Siiize Document Number

Custom

KBL

Date: Sheet 42 o f 55

Friiiday, March 09, 2018

R ev

1.0

A B C D

Module model information

ISL95 52 0A_ Hy br id_ Bo ost_V 2.mdd

Protection for reverse input

1 1

1 2

PR738

1M_0402_1%

Need check the SOA for inrush

PQ740

EMB04N03H_N_DFN56-8-5 5

+19V_VIN

2 2

PR729

287K_0402_1

PR729 and PR732 are ACDET set t i ng base on your proj ect to set.

0x3CH <BIT9> PSYS current gain
Rs1 = 10mΩ and Rs2 = 5mΩ or Rs 1 = 10m Ω a nd R s2 = 10mΩ BIT0
= 1.14uA/W
BIT1 = 0.285uA/W
== == === == == == === == == == == === == == == === == == == == === == == == == ==
Rs1 = 20mΩ and Rs2 = 10mΩ or Rs 1 = 20m Ω an d R s2 = 20mΩ
BIT0 = 2.28uA/W
BIT1 = 0.57uA/W

Ipsys = KPSYS x ( VAD P x IAD P + VBA T x IBAT )
R_Psys = 1.2V / Ipsys
KPSYS = 1.14uA/W
adapter wattage = 45W
Battery wattage = 40Wh
Ipsys = 1.14 x (45+40) = 96.9uA

3 R_Psys = 1.2V / 96.9uA = 12.3K-ohm.

== == === == == == === == == == == === == == == === =
adapter wattage = 65W
Battery wattage = 40Wh
Ipsys = 1.14 x (65+40) = 119.7uA
R_Psys = 1.2V / 96.9uA = 10K-ohm.

**Design Notes**
For 45W/65W /90W system, 2S/3S/4S battery

Maximum Charging current 3.5A
Maximum Battery discharge power 55W
#Register Setting

1. 0X3DH bit10 set 0 (default 1) to enable turbo boost function

2. Disable turbo when AC only
#Circuit Design

1. ACLIM and CCLIM are devider voltage control.

2.Use 7X7 choke and 3X3 H/L side MOSFET
Charge current 3A
Power loss : 1.79W (H/S=0.227W,L/S=1.2738W,Choke=0.297W)
Power density : 0.61 (23X16)
#Protect function

1. ACOVP : VCC voltage > 24V

2. SMBus timeout : 0X3DH bit15 set 0 (default 0) to enable 175s(default).

3. ACOC : OX3CH bit4 set1 release adapter limit function (default:Enable).

4. CHGOCP : based on charge current setting

5. BATOVP : 4.6V/Cell

6. BATLOWV : No.

4 4

7. TSHUT : 150C

(Rs1 = 10mΩ and Rs2 = 5mΩ or Rs 1 = 20m Ω an d R s2 = 10mΩ).
CC_LIM = VccLIM / 64 x Rs2
== == === == == == === == == == == === == == == === == == == == === == == == == === == =
(Rs1 = 10mΩ and Rs2 = 10mΩ or Rs 1 = 20m Ω an d R s2 = 20mΩ).
CC_LIM = VccLIM / 32 x Rs2
=== === == === == == == == == == === == == == == === == == == === == == == == === == =
AC_LIM = Vac_LIM / 32 x Rs1

<36> VCIN1_AC_IN

A B C

VDD_CHG

12

PR741

100K_0402_1

%

12

<36,42> EC_SMB_DA1
<36,42> EC_SMB_CK1

PR731

<36> VCOUT1_PROCHOT#

158K_0402_1

%

<36> ADP_I

Vgs = 20V
Vds = 60V
Id = 250mA

1 2

PR737

3M_0402_5%

4

12

%

ASGATE_CHG_R

12

PR732

49.9K_0402_1

ACIN_CHG

PC715

2 1

%

Close to
EC.

VCIN1_AC_2IN

L2N7002WT 1G_SC70-3

Battery current limimed by CCLIm ~ 3.89A.
Adapter current limimed by ACLIm ~ 4.33A.
(PR779 and PQ741 are for change ACLIm when AC in)

D

13

2

PQ707

G

L2N7002WT 1G_SC70-3

S

+19V_P1

1
2
3

12

2 1

PR762 4.02K_0402_1%

PR763 4.02K_0402_1%

2200P_0402_50V7K

support Turbo boost : 2200P no
support Turbo boost : 0.1u

PR769 1 2 0_0402_5%
PR770 1 2 0_0402_5%

PR777 1

1

PR780

Close to EC.

Follow adapter and

PC748

2 1

battery wattage in
Vsys current source.

0.1U_0201_10V6K

Base on CPU Core VR design.
The resistor is pop on CPU VR schematic.

VDD_CHG

VDD=5V

12

PR749

@

PR779

76.8K_0402_1%

1 2

@

PQ741

13

D

G

1

S

PR751

2

Rds(on) = 15.8mohm max
Vgs = 20V
Vds = 30V
ID = 10.5A (Ta=70C)

PQ712

AON7506_DFN33-8-5

1
2
3

4

2 0_0402_5% 5

2

1K_0402_1%

12

PR750
200K_0402_1%

200K_0402_1%

PR752
162K_0402_1%

2 1

76.8K_0402_1%

+19V_P2 B+

5

CMSRC_CHG

ASGATE_CHG

AMON_ISL95520

12

PR727

@

10K_0402_1

%

ACLIM_CHG

PROG_CHG

PR753

2 1

165K_0402_1%

Hybrid boost power mode
Cell = 2s

max Power loss 0.22W for 90W;0.12W for 65W system;0.05W for 45W
CSR rating: 1W
VCSIP-VCSIN spec < 81mV

PR703

0.01_1206_1%

1

4
3

2

PC760

1

ACIN

2

ACOK

3

SDA

4

SCL
PROCHOT#

6

AMON

7

BMON

8

PSYS

AGND

33

CCLIM_CHG

COMP_CHG

2 1

PR772

CSIP_CHG_R

%

0_0402_5

CSIP_CHG

32

CSIP

PROG

9

PC751

560P_0402_50V7

2 1

K

PC747

1 2

0.1U_0402_25V6

CSIN_CHG

30

31

CSIN

COMP

11

10

1

499_0402_1%

PR754

PC752

2 1 2

CSIN_CHG_R

12

PR740

2_0402_5

%

1

PC750 0.22U_0603_25V7K

OPCN_CHG2OPCP_CHG

VBAT_CHG

28

26

27

29

QPCP

OPCN

CMSRC

ASGATE

CSON14CSOP

CCLIM

FSET12BATGONE

13

15

12

PR778

FSET_CHG

10K_0402_1%

Fs=729KHZ ~ +/- 15%

2 PR755 1

38.3K_0402_1%

BAT GON E( BAT T_ TEM P)
logic high: above 2.4V
logic low: under 0.8V

0.015U_0402_25V7

K

PR745

100_0402_1%

1 2

Rds(on) = 32mohm max

BST_CHG_R

1 2

12

PR743 10_1206_5%

1 2 1

VF = 0.38V

Vgs = 20V
Vds = 30V
ID = 8A (Ta=70C)

1 2

PR760 4.7_0402_5%

PC768
1U_0402_16V6K

12

2018/03/09 2019/03/09

BGATE_CHG

PU703

25

ISL88739AHRZ-T_QFN32_4X4

VBAT

BGATE

UGATE

ACLIM

16

BOOT

PHASE
LGATE

VDDP

DCIN

VDD

NTC

CSOP_CHG

CSON_CHG

PR771 0_0603_5% 0.22U_0603_25V7K

BST_CHG

24

UG_CHG

23

LX_CHG

22

LG_CHG

21

VDDP_CHG

20

VDD_CHG

19
18
17

PR757
100K_0402_1%

2 1

PC757

1 2

1U_0603_25V6

VCIN1_BATT_TEMP <36,42>

SecuriiityClllassiiifiiicatiiion

Issued Date

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL
AND TRADE SECRET IIINFORMATIIION... THIIIS SHEET MA Y NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIIONOF R&D
DEPARTMENT EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IIINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIITCONTAIIINS
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IIINC...

PC762

2 1

2 1

PC765 @EMI@

10U_0805_25V6

K

10U_0805_25V6

K

+12.6V_BATT+

PC721

1 2

12

PD703

3
2

LRB715FT1G_SOT323-3

1 2

PR742 2_0402_5%

PC708

0.1U_0402_25V6
PR776

1 2

0_0402_5%

2 1

2 1

PC705 EMI@

2200P_0402_25V7K

0.1U_0402_25V7K

Rds(on) = 32mohm max
Vgs = 20V
Vds = 30V
ID = 8A (Ta=70C)

5

PQ704

AON7408L_DFN8-5

4

321

5

PQ706

4

PC769
1U_0402_16V6K

321

+19V_VIN
BA

A31 connect to BA
Other team connect to bat t co nn

Compal Secret Data

AON7752_DFN3X3EP8-5

CSOP_CHG_R

CSON_CHG_R

Decipherii ed Date

B+

PQ705
AON7506_DFN33-8-5

4.7UH_5.5A_20%_7X7X3_M

1

2 1 2

680P_0603_50V7K 4.7_1206_5%

@EMI@ PC767 @EMI@ PR766

1
2
35

4

@PC779

1 2

0.1U_0402_25V7K

7X7X3

Isat: 6.5A
DCR: 28mohm

PL700

1 2

+17.4V_BATT_CHG

<10,36,46> PM_SLP_S4#

Support max charge 3.5A
Power loss: 0.245W
CSR rating: 1W
VCSPP-VCSON spec < 81mV

PR765

0.01_1206_1%

1

Tiiitttllle

Siiize DocumentttNumber

Dattte::: Friiiday,,, March 09,,,2018

4
3

2

PC775

PC776

2 1

10U_0805_25V6

K

LMUN5113T1G PNPSOT323-3

2

PQ711

LMUN5236T1G NPNSOT323-3

For A31 only.
Turn off Charger IC on b atter y only.
Depend on customer design for
system power consumption.

Compal Electronics, Inc.

PWR_CHARGER

D

2 1

10U_0805_25V6

K

PQ710

13

Sheettt 43 o fff 55

+12.6V_BATT+

PC761

2 1

10U_0805_25V6

K

2

1 3

BA

BA

Rev

1...0

3

A

B

C D E

Module model information

SY8 286B_ V3_si ng le.md d
SY8286B _V 3_ du al .mdd

1 1

keep short pad,
snubber is for EMI only .

B+

EMI@ PL401

5A_Z80_0805_2P

1 2

@EMI@ PC403

0.1U_0402_25V6

+19VB_3V

2 1

2 1

2 1

PC405

2200P_0402_50V7K

EMI@ PC404

10U_0805_25V6K

+3VL

Check pull up r esistor of SPO K at HW side

100K_0402_5%

2 2

<36,40,46> 3V/5VALW_PG

EN1 and EN2 dont't be floating.
EN :H>0.8V ; L<0.4V

12

PR406

Module model information

SY8 286C_ V3_si ng le.md d
SY8286C _V 3_ du al .mdd

2 Cell battery : Cin=10uF* 2pcs

B+

EMI@ PL403

5A_Z80_0805_2P

1 2

3 3

PR402
499K_0402_1%

ENLDO_3V5V

2

B+

<36> VCOUT0_MAIN_PWR_ON

1

<36> EC_ON

12

PR404
150K_0402_1%

PC429
1U_0201_6.3V6M

2 1

@PR411

0_0402_5%

1 2

2.2K_0402_5%

1 2

+19VB_5V

4 4

BATTDROP@

12

PR451
560K_0402_5%

12

BATTDROP@

PR452

105K_0402_1%

VCIN1_BATT_DROP <36>

12

BATTDROP@

PC451
1000P_0402_50V7K

A

PR410

12

PR412

1M_0402_1%

+19VB_5V

PC414

2 1

10U_0805_25V6K

5V_3V_EN

PC428

2 1

3 Cell ~ 4 Cell battery : Cin=10 uF*1pcs

+19VB_5V

LX_5V

6

12

PC415

2 1

2 1

10U_0805_25V6K

EN1 and EN2 dont't be floating.
EN :H>0.8V ; L<0.4V

0.1U_0402_25V6

2200P_0402_50V7K

EMI@ PC416

@EMI@PC417

3V/5VALW_PG

10

ENLDO_3V5V

5V_3V_EN

Fsw : 600K Hz

4.7U_0402_6.3V6M

B

PU401
SY8286BRAC_QFN20_3X3

2

5

LX_3V

6
7

8

9

10

ENLDO_3V5V

5V_3V_EN

LX
GND
GND
PG
NC

IN3IN4IN

EN112EN2

FF13OUT

11

14NC15

3V_FB

Fsw : 600K Hz

PU402 SY8286CRAC_QFN20_3X3

2

5

LX

7

GND

8

GND

9

PG
NC

11

1

IN

IN3IN4IN

BS

GND

VCC

GND

EN112EN2

FF13OUT14LDO

2 1 15

PC413 PR407

1000P_0402_50V7K 1K_0402_1%

5V_FB

1 2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONT AINS
MAYBE USED BY OR DISCLOSED TOANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.

BST_3V_R

2

PC401

0.1U_0402_25V6

1

PC418

1

LX_3V

2

1

PR405

@EMI@

2

3V_SN

1

2

@EMI@

PC412

2

PR409

@EMI@

2 1

5V_SN

1

2

PC426

@EMI@

Compal Secret Data

Deciphered Date

@ PR401

0_0402_5%

BST_3V

1

IN

BS

20

LX

19

LX

18

GND

17

LDO

16

NC

21

GND

1

12

2

+3VLP

PC411

4.7U_0603_6.3V6K

3.3V LDO 15 0mA~300mA

PC402
1000P_0402_50V7K

3V_FB_1

1 2

BST_5V

20

LX

19

LX

18

VCC_5V

17
16

NC

21

+5VLP

5V LDO 150mA ~300mA

PC427

4.7U_0603_6.3V6K

5V_FB_1

1

PR403

1K_0402_1%

1

keep short pad,
snubber is for EMI only .

@PR408

0_0402_5% 0.1U_0402_25V6

BST_5V_R

1 2

LX_5V

PC419

1 2

2.2U_0402_6.3V6M

2

2018/03/09 2019/03/09

C D

Use 7x7x3 size when the layout space is enough.

PL402

1.5UH_6A_20%_5X5X3_M

1 4
2 3

2 1

2 1

2 1

PC408

PC407

22U_0603_6.3V6M

PC409

22U_0603_6.3V6M

Vout is 3.234V~3.366V

680P_0603_50V7K 4.7_1206_5%

PL404

1.5UH_6A_20%_5X5X3_M

1 4
2 3

4.7_1206_5%

TDC =6A

2 1

PC420

22U_0603_6.3V6M

2 1

2 1

2 1

PC422

PC421

22U_0603_6.3V6M

22U_0603_6.3V6M

Vout is 4.998V~5.202V

680P_0603_50V7K

TDC=6A Iocp=10 A

Tiiitllle

Siiize Document Number

Custom

+3VALWP

2 1

PC410

22U_0603_6.3V6M

22U_0603_6.3V6M

Ioc p=10A

@PJ401

1

2

1 2

JUMP_43X118

@ PJP402

JUMP_43X39

2

1

1

2

+5VALWP

2 1

PC423

2 1

PC424

PC425

@

22U_0603_6.3V6M

@

22U_0603_6.3V6M

@PJ403

1

1 2

JUMP_43X118

@PJP404

JUMP_43X39

1

122

2

22U_0603_6.3V6M

Compal Electronics, Inc.

+3VALW/+5VALW

Sheet 44 o f 55Date: Friiiday, March 09, 2018

E

+3VALW+3VALWP

+3VL+3VLP

+5VALW+5VALWP

+VL+5VLP

R ev

1.0

5

4

3 2 1

Module model information

RT8207P_single_V3.mdd For Single layer
RT8207P_dual_V3.mdd For Dual layer

D D

Pin19 need pull separate from +1.35VP.
If you have +1.35V and +0.675V sequence question,

EMI@ PL501

22U_0603_6.3V6

2 1

M

5A_Z80_0805_2P

1 2

PC513

2 1

22U_0603_6.3V6

M

+12.6VB_DDR

BST_DDR_R

2 1

2 1

0.1U_0402_25V

6

EMI@PC502

2200P_0402_50V7

@EMI@PC501

1UH_11A_20%_7X7X3_M

1 4
2 3

12

PC514

22U_0603_6.3V6

M

K

PL502

RF@ PR503

4.7_1206_5%

RF@ PC517

680P_0402_50V7K

Choke: 7x7x3
Rdc=6.7mohm(Typ), 7.4mohm(Max)

Switching Frequency:540kHz
Ipeak=8A
Iocp~9.6A
OVP: 113%~120%
VFB=0.75V, Vout=1.3545V

2 1

PC503

10U_0805_25V6

K

AON7408L_DFN8-5

1

1 22

AON7506_DFN3X3-8-5

2 1

PC504

10U_0805_25V6

K

5

PQ501

4

123

5

4

PQ502

123

12

PC505

0.1U_0402_25V7K

30MA_30V_0.5UA_0.4V_SOD323-2

+5VALW

1U_0201_6.3V6K

PR504

5.1_0603_5%

1 2

PC516

12

<13,36> SYSON

2.2_0603_5%

1

PR502

12.7K_0402_1%

1

2

+5VALW

PR501

2

LG_DDR

CS_DDR

2

PC508

1U_0201_6.3V6K

1 2

PD501

1

VDD_DDR

PR505

2

1

2.2_0603_5%

+12.6VB_DDR

PR507 470K_0402_1%

<13,36,40> SUSP#

B+

C C

+1.2VP

PC511

PC510

PC509

2 1

22U_0603_6.3V6

M

22U_0603_6.3V6

M

B B

Mode Level +0.675VSP VTTREF_1.35V
S5 L off off
S3 L off on
S0 H on on

Note: S3 - sleep ; S5 - power off

PC512

2 1

2 1

22U_0603_6.3V6

M

<7> DDR_VTT_PG_CTRL

A A

you can change from +1.35VP to +1.35VS.

BST_DDR

UG_DDR

LX_DDR

16

18

PU501

15

LGATE

14

PGND

13

CS

12

VDDP

11

VDD

1

@ PR508

0_0402_5%

1 2

17

PHASE

UGATE

RT8207PGQW_WQFN20_3X3

PGOOD

TON

9

10

TON_DDR

2

@ PC518

0.1U_0402_10V7K

@

PR510

0_0402_5%

1 2

@ PR511

0_0402_5%

1 2

8

EN_DDR

2 1

BOOT

S5

EN_0.675VSP

20

19

21

VTT

PAD

VTTGND

VTTSNS

GND

VTTREF

VDDQ

FB

6

FB_DDR

1

2

3

4

5

VLDOIN

S3

7

+1.2VP +1.2V

@ PC519

0.1U_0402_10V7K

2 1

+0.6VSP +0.6VS

VTTREF_DDR

1 2

12

PR509
10K_0402_1%

+1.2VP

+1.2VP

PR506

6.04K_0402_1%

1

JUMP_43X118

1

2 1

PC506

10U_0603_6.3V6

@PJ501

122

PJ50@3

1

2

JUMP_43X39

M

2

0.675Volt +/- 5%
TDC 0.7A
Peak Current 1A

+0.6VSP

2 1

PC507

10U_0603_6.3V6

M

12

PC515

0.033U_0402_16V7K

+1.2VP

SecurityClassification

Issued Date

THIS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIET ARY PROPERTY O F CO MPAL ELECT RONICS, INC. AND CONT AINS CONFIDENTIAL AND
TRADE SECRET INFORMAT ION. T HIS SH EET MAY NOT BE TRANSF ERED FR OM THE CUSTODY O F THE CO MPET ENT DIVISION OF R&D
DEPART MENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RONIC S, INC. NEITH ER T HIS SHEET NO R THE INFORMATION IT CO NTAINS
MAY BE USED BY OR DISCLOS ED TO ANY THIRD PAR TY W ITHOUT PRIOR W RIT TEN CONSENT OF COMPAL ELECT RONICS , INC.

5

4

2018/03/09 Deciphered Date

3 2

Compal SecretData

2019/03/09

Tiiitllle

Siiize Document Number

Compal Electronics, Inc.

Custom

Friiiday, March 09, 2018

RT8207P

Rev

Sheet 45 of 55Date:

1

1.0

5

4

3 2 1

Module model information

APL5 93 0_ V2 .m dd

D D

+3VALW

JUMP_43X79

PJ801

@

C C

<36,40,44> 3V/5VALW_PG

@ PR801

0_0402_5%

1 2

PR803

1M_0402_5%

4.7U_0603_6.3V6K

2 1

@

2 1

PC802

PC804

0.1U_0402_16V7K

+3VALW

+3VALW

B B

JUMP_43X79

@ PR806

0_0402_5%

<10,36,43> PM_SLP_S4#

A A

1 2

47K_0402_5%

4.7U_0603_6.3V6K

PR808

2 1

1

1

PJ803

2

@

2

12

PC807

2 1

PC809

0.1U_0402_16V7K

1

1

2

2

12

1 2

+5VALW

+5VALW

PR804
100K_0402_5%

12

1U_0201_6.3V6M

PU802

G9661MF11U_SO8

4
3
2
1

12

1U_0201_6.3V6M

PGOOD <47>

PC806

VPP
VIN
VEN
POK

GND

9

PC801

NC
VO
ADJ
GND

4
3
2
1

PU801
G9661MF11U_SO8

VPP
VIN

VO

VEN

ADJ

POK

GND

GND

9

5
6
7
8

Ultra Low Dropout 0.23V(typic al) at 3A Output Current

5

NC

6
7
8

Rup

Rdow n

2 1

PC803

PR802

2 1

12.7K_0402_1%

12

PR805

10K_0402_1%

2 1

0.01U_0402_16V7K

+1.8VALWP

PC805

22U_0603_6.3V6M

Vout=0.8V* (1+Rup/R down)

Vout=0.8V* (1+Rup/R down)

+2.5VP

Rup

Rdow n

2 1

PC808

PR807

2 1

3.4K_0402_1%

PR809

2 1

1.6K_0402_1%

2 1

0.01U_0402_16V7K

PC810

22U_0603_6.3V6M

+2.5VP +2.5V

PJ802

@

1

+1.8VALWP +1.8VALW

PJ804

@

1

2

1 2

JUMP_43X79

1 2

JUMP_43X79

2

Security Classification

Issued Date Deciphered Date

THIIS SHEET OF ENGIINEERIING DRAWIING IIS THE PROPRIIETARY PROPERTY OF COMPAL ELECTRONIICS,, IINC.. AND CONTAIINS CONFIIDENTIIAL
AND TRADE SECRET IINFORMATIION.. THIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIVIISIION OF R&D
DEPARTMENT EXCEPT AS AUTHORIIZED BY COMPAL ELECTRONIICS,, IINC.. NEIITHER THIIS SHEET NOR THE IINFORMATIION IIT CONTAIINS

5

4

MAY BE USED BY OR DIISCLOSED TO ANY THIIRD PARTY WIITHOUT PRIIOR WRIITTEN CONSENT OF COMPAL ELECTRONIICS,,IINC..

3 2

2018/03/09 2019/03/09

Compal Secret Data

Tiiitllle

APL5930

Siiize Document Number

Custom

KBL

Compal Electronics,Inc.

Sheet 46 o f 55Date: Friiiday, March 09, 2018

1

R ev

1.0

A

B

C

D

E

Module model information

SY8286_V2_sin gl e.m dd
SY8286 _V2 _du al. mdd

+3VALW

Confirm HW side

1 1

B+

@ PR603

0_0402_5%

<46> PGOOD

EN :H>0.8V ; L<0.4V

EN pin don't floating
If have pull down resistor at HW side,

please delete PR601.

2 2

1 2

1M_0402_1%

PR601

12

+19VB_1V

EN_1V
ILMT_1V

2
3
4

5
7

8
18
11

13

15

12

PC614
1U_0201_6.3V6M

PU601

IN
IN
IN
IN
GND
GND
GND
EN
ILMT
BYP

SY8286RAC_QFN20_3X3

@PJ602

1

1 2

JUMP_43X79

12

@ PC601

0.1U_0402_25V6

2

2 1

0.1U_0402_25

V6

EMI@ PC604

@EMI@ PC605

2200P_0402_50V

7K

+19VB_1V

12

PC606

2 1

10U_0805_25V6

K

+3VALW

+3VALW

12

@ PR607

0_0402_5%

12

@ PR609

0_0402_5%

The current limit is set to 6A, 9A or 12A when this pin
is pull low, floating or pull high.

VCC

PAD

12

@ PR611

100K_0402_5%

9

PG

BST_1V

1

BS

LX_1V

6

LX

19

LX

20

LX

FB_1V

14

FB

LDO_3V

17
10

NC

12

NC

16

NC

21

keep short pad,
snubber is for EMI only.

@ PR606

0_0402_5%

BST_1V_R

2

1

12

PC613

2.2U_0402_6.3V6M

@EMI@ PR605

4.7_1206_5%

1

PC603

0.1U_0402_25V6

1 2

Use 7x7x3 size when the layout space is enough.

1UH_6.6A_20%_5X5X3_M

FB=0.6V

Vout=0.6V* (1+R1/R2) R2

=0.6*(1+(14/20))

SNUB_1V

2

PL602

1 2

@EMI@ PC602

680P_0603_50V7K

12

R1

12

1 2

PR608

14.3K_0402_1

%

PR610
20K_0402_1%

1 2 12

PR612
1K_0402_1%

+1.0VALWP

PC608

330P_0402_50V

7K

PC610

PC611

PC609

2 1

2 1

22U_0603_6.3V6

M

22U_0603_6.3V6

M

PC612

2 1

2 1

22U_0603_6.3V6

M

22U_0603_6.3V6

M

@ PJ601

JUMP_43X118

1

+1.0VALWP

122

+1.0VALW

Vout=1.02V

3 3

4 4

Securiiity Clllassiiifiiicatiiion

Issued Date

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL AND
TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIION OF R&D DEPARTMENT
EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IIINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIIT CONTAIIINS

A

B

MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IIINC...

C

2018/03/09 2019/03/09

Compal SecretData

Decipherii ed Date

D

CCoommppaallEElleeccttrroonniiccss,,Inc.

Tiiitttllle

SY8286

Siiize DocumentttNumber

C

Rev

Sheettt

E

47 o fff 55Dattte::: Friiiday,,, March 09,,,2018

1...0

1

RT3602_VREF

Vref=0.6V

1

02_1%102_1%

A A

B B

C C

953_0402_1%

1 2 1

PRZ6 PRZ3

PRZ5 PRZ2

2

5K_0402_1%

1

1 22

PRZ29 PRZ18

PRZ28 PRZ17

3K_0402_1% 464_0402_1%

<15> VCCCORE_SENSE

1 2

PRZ11 PRZ4

2 1 2

2

10_0402_1% 6.8K_04

RT3602_SET1

11K_0402_1% 15K_04

RT3602_SET2
RT3602_SET3

VR_PSYS

12

11 2

PRZ20

@

2 1

12

10K_0402_1

%

@ PCZ7

0.1U_0402_10V6K

1

12

PRZ31

PRZ30 PRZ19

0_0402_5

%

499_0402_1% 5.23K_0402_1%

2.1K_0402_1%1.1K_0402_1%

2

2

@PCZ8 @PRZ40

0.1U_0402_10V6K 10K_0402_1%

1 2 1

PRZ43

+VCCCORE PRZ4 1

100_0402_1%

1 2

PRZ47
0_0402_5%

1 2

VSEN_CORE

10K_0402_1%

1 2

1 2

U42@

220P_0402_50V8J

PCZ11

U22@ PCZ11

270P_0402_50V8J

Ra Rb/Rc

U22

N/A

Stuff

U42

N/AStuff

2

+VCCSA

PRZ1
100_0402_1%

1

<13>VCCSA_SENSE

colose to core1 MOSFET

RT3602_VREF

2

<49> AVCORE1

<49> AVCORE2

+5VALW

1 2

PHZ1 PRZ26

100K_0402_1%_B25/504250K 5.9K_0402_1%

PRZ45
51K_0402_1%

1 2

PCZ1282P_0402_50V8J

1 2

Rb

1 2

U22@ PRZ10510K_0402_1%

RT3602_VREF

PRZ64

1 2 1

1 2 1

PRZ68

2

2

TSEN_CORE_R

100_0402_1%9.1K_0402_1%

TSEN_GT_R

11 2

5K_0402_1%

1 2 1

PRZ74 PRZ71

PRZ73 PRZ70 PRZ67 PRZ63

2

2

3.92K_0402_1%200K_0402_1%

68.1K_0402_1% 750K_0402_1% 3.9K_0402_1%

VCCSA_SENSE_R

2

PRZ15

0_0402_5%

1 2

<49> AISPCORE1

PHZ1_R

2

1

2

1

PRZ33

17.4K_0402_1%

PCZ13

0.1U_0402_25V7K

1 2
U42@

PCZ16 0.1U_0402_25V7K

+5VALW

TSEN_CORE_R

@PCZ1 @PRZ16

0.1U_0402_10V6K10K_ 0402_1%

IMON_CORE_R

1 2

<49> AISPCORE2

U22@ PRZ10410K_0402_1%

PRZ51 PRZ52

4.3M_0402_1% 1.3M_0402_1%

1 2 1 2

1 2

PRZ8
10K_0402_1%

1 2

1 2 1 2

PCZ5 390P_0402_50V7K PCZ668P_0402_50V8J

1 2 1 2

1

@ PCZ9

0.1U_0402_10V6K

U42@ PRZ106

1

0_0402_5%

PHZ2

100K_0402_1%_B25/504250K

U22@ PRZ35

U42@ PRZ35

21.5K_0402_1%

1 2

Ra

2

Rc

1 2

20K_0402_1%

2

ISEN1N_MAIN

FB_SA

RT3602_SET2 5COMP_MAI N
RT3602_SET3 6SET2

TSEN_CORE 11ISEN1P_MAIN

PRZ53

PRZ10

48.7K_0402_1%

<15>

1 2

IMON_CORE

RT3602_SET1IMON_MAIN

FB_CORESET1

COMP_CORE 4FB_MAIN

10

RT3602_VIN12TSEN_MAIN

1

2 1

2

2.2_0805_1

%

PCZ19

0.22U_0402_25VAK

+19VB_C PU

+5VALW PRZ65

4.7U_0402_10V6M

+5VALW

1

@ PRZ72

0_0402_5%

DRVEN_SET

@ PRZ75

0_0402_5%

2 1 2

3

PRZ95

0_0402_5

1
2
3

SET3

7

ISEN1N_MAIN

8

ISEN2N_MAIN

9

ISEN2P_MAIN

10_0402_1%

1 2

VSSCORE_SENSE

%

2 1

RGND_MAIN

VIN

<49> AVCCSA

1

100_0402_1%

2

PRZ21

49

GND

PRZ62

PCZ23

4

PCZ3

0.1U_0402_25V7K

12

AISPVCCSA <49> @

PCZ4

0.47U_0402_25V6K

1 2

PRZ14

RT3602_VREF

2 1

PRZ13
59K_0402_1%

PRZ23
10K_0402_5%

1 2

PRZ25

1 2

0_0402_5%

RT3602_EN

PUZ1

RT3602AEGQW_WQFN48_6X6

37

EN

36

PWM_S A

35

VR_READY

DRVEN

34 1 2

VCLK

33 PRZ98 49.9_0402_1%

ALERT#

32 PRZ991 210_0402_1%

VDIO

31 PR1Z100100_20402_1%

VR_HOT#

30

IMON_AUXI

29

ISENP_AUXI

28

ISENN_AUXI 27VSEN_GT

VSEN_AUXI 26COMP_GT

COMP_AUXI

25

RGND_AUXI

FB_AUXI

24

RGND_AUXI

1

PRZ60

100_0402_1%

<49>

<49>

PRZ66

4.3M_0402_1%

PRZ69

1.3M_0402_1%

0_0402_5%

1 2

+3VS

VR_PWRGD <36>

PRZ93

2

VR_ON<36>

PRZ36

45.3_0402_1

PWM_SA <49>
DRVEN<49>

IMON_GT

0.1U_0402_25V7K

12

0_0402_5%

VSSGT_SENSE <15>

+1.0V_ VCCST

1

PRZ37

@

110_0402_1

%

2

%

@ PCZ150.47U_0402_25V6K

1 2

PCZ18

2 1

100_0402_1

%

PRZ38

1 2

1

2 1

2

75_0402_1

%

PRZ39

AISP1 <49>
AVGT1 <49>

PRZ54

15.8K_0402_1%

1 2

1 2

PCZ20 82P_0402_50V8J

PCZ194

0.1U_0201_10V6K

2 1

VR_SVID_CLK<15>
VR_ALERT#<15>
VR_SVID_DATA <15>

VR_HOT# <36>

PRZ48
30K_0402_1% PRZ49 17.4K_0402_1%

1 2 1 2

PRZ56
10K_0402_1%

1 2

1 2

PCZ21

270P_0402_50V7K

1 2
@ PRZ61

10K_0402_1%

FB_GT

RT3602_VREF

1 2

@ PCZ22

0.1U_0402_10V6K

VSEN_GT

PRZ50

0_0402_5%

1 2

PRZ59
100_0402_1% +VCCG T

1 2

<13

PCZ193

2 1

VSSSA_SENSE

0.47U_0402_25V6K

>

1

12

PRZ24

0_0402_5%

2 1

2

PRZ94

PRZ22100_0402_1%

RT3602_VREF 3.9_0402_1%

IMON_SA

FB_SA

VSEN_CORE

VR_PSYS

RGND_SA

COMP_SA

40

48

45

43

44

39

42

47

38

46

41

PSYS

FB_SA

IMON_SA

RGND_SA

ISENP_SA

COMP_SA

ISENN_SA

VSEN_MAIN

RGND_MAIN

VREF06/ PSET

NC

NC19DRVEN_SET20NC

VCC15NC

PWM1_ MAIN

PWM2_ MAIN

PWM_AUX I

TSEN_AUXI

17

21

18NC13

14

22

16

23

FB_GT

DRVEN_SET

TSEN_GT

RT3602_VCC

1

0_0402_5

%

<49>

2

VCC_CPU_R

PWM_GT

PWM_CORE1

PWM_CORE2

1

2 1

2 1

1 2

PHZ3

2

100K_0402_1%_B25/504250K

TSEN_GT_R

5

VCCGT_SENSE <15>

D D

Securiiittty Clllassiiifffiiicatttiiion

IIIssuedDattte

THISII SHEET OF ENGINII EERINII G DRAWINII G ISIITHE PROPRIETII ARY PROPERTY OF COMPAL ELECTRONICS,,,IIINC...II AND CONTAINSII CONFIDENTII IALII AND TRADE
SECRET INII FORMATION...II THISII SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISIONIIIIII OF R&D DEPARTMENT EXCEPT AS
AUTHORIZIIED BY COMPAL ELECTRONICS,,,II INC...II NEITII HER THISII SHEET NOR THE INFII ORMATIONII ITIICONTAINSII

1

2

3

MAY BE USED BY OR DISCII LOSED TO ANY THIRDII PARTY WITII HOUT PRIORII WRITII TEN CONSENT OF COMPAL ELECTRONICS,,,IIINII C...

2018/03/09

4

Compalll SecretData

Deciiiphererr d Dattte

2019/03/09

Compal Electronics, Inc.

Tiiitttllle

CPU_CORE

Siiize DocumentttNumberrr

Dattte::: Frrriiiday,,, Marrrch 09,,,2018

5

Sheettt 48 offf

Rev

1...0

55

5 4 3 2 1

EMI@ PLZ45A_Z80_0805_2P

+19VB_C PU

PRZ76

D D

<48> PWM_CORE1

+5VALW

<48> DRVEN

C C

1 PRZ80 2

1_0402_5%

VCC_CORE1

12

PCZ40

2.2U_0402_6.3V6M

CORE1_BST

8

2.2_0603_5%

1 2

PUZ2

RT9610CGQW_WDFN8_2X2

4 3

BOOT UGATE

5 2

PWM P HASE

1 6

EN PGND
VCC LGATE

9

GND

CORE1_BST_R

PCZ28

0.1U_0402_25V6

CORE1_UG CORE1_UG_R
CORE1_LX

7

2 1

CORE1_LG

53

PQZ1

2 1

@EMI@ PCZ29

4

4

321

0.1U_0402_25V6

2

1

AON6380_DFN5X6-8-5

PQZ2

5

1

RF@

PRZ82

4.7_1206_5%

2

AISPCORE1_R

AON6314_N_DFN56-8-5

CORE1_SNUB

1

PCZ44 RF@

680P_0402_50V7K

2

U22@ PRZ85 U22@ PRZ102

PCZ31

2 1

2 1

10U_0805_25V6

K

EMI@ PCZ30

2200P_0402_50V7K

Rdc=0.98 mohm

PLZ1

1 4
2 3

0.15UH_NA36A_20%

1 2 1 2

PRZ85 PRZ102

1.2K_0402_1%1.2K_0402_1%

U42@

U42@

1K_0402_1%1K_0402_1%

PCZ205

2 1

PCZ42

0.1U_0402_25V6K

1 2

@ PRZ88

560_0402_1%

1 2

PCZ26

10U_0805_25V6K

1

+

2

+VCCCORE

100U_25V_NC_6.3X6

1 2

1 2

EMI@ PLZ35A_Z80_0805_2P

AVCORE1 <48>

AISPCORE1 <48>

+19VB_C PU

PRG2

PUG1

RT9610CGQW_WDFN8_2X2

4

BOOT UGATE

5

PWM PHASE

EN PGND

8

VCC LGATE

2.2_0603_5%

GT_BST_R

1 2

GT_UG GT_UG_R

3

GT_LX

2
6
7

9

GND

12

GT_LG

PCG2

0.1U_0402_25V6

PCG6

4.7_1206_5%

2 1

GT_SNUB

1

2

2 1

@EMI@ PCG3

0.1U_0402_25V6

PCG9 RF@

680P_0402_50V7K

PCG

2 1

5

10U_0805_25V6K

EMI@ PCG4

2200P_0402_50V7K

PRG6 PRG9

1K_0402_1% 2.05K_0402_1%

1 2 1 2

AISP1_R

2 1

2 1

10U_0805_25V6K

Rdc=0.98 mohm

PLG1

1 4
2 3

0.15UH_NA36A_20%

0.1U_0402_25V6K

PRG7

3K_0402_1%

1 2

AVGT1_R

10K_0402_1%_B25/503370K

PCG8

1 2

PRG8

10K_0402_1%

1 2

1 2

PHG1

+VCCGT

5

PQG1

4

321

AON6380_DFN5X6-8-5

PQG2

5

RF@ PRG4

4

321

AON6314_N_DFN56-8-5

GT_BST

<48> PWM_GT

+5VALW

B B

1 PRG12

1_0402_5%

VCC_GT

PCG1

2.2U_0402_6.3V6M

2 1

DRVEN 1

B+

<48> PWM_CORE2

+5VALW

1

U42@ PRZ81

1_0402_5%

AVGT1 <48>

AISP1 <48>

U42@ PRZ77

2.2_0603_5%

1 2

U42@ PUZ3

RT9610CGQW_WDFN8_2X2

4

BOOT UGATE

5

PWM P HASE

DRVEN1

EN PGND

8

VCC LGATE

H/S AON6 280:
R DS(ON) (at V GS =10V) < 6.8m
R DS(ON) (at V GS =4.5V) < 10.5m

L/S AON6 214:
R DS(ON) (at V GS =10V) < 2.8m ?
R DS(ON) (at V GS =4.5V) < 3.5m?

VCC_ COR E
FSW=450kHz
Chok e=0 .15u H
DCR=0.67 mohm +/- 5%

U22
LL=2.4 mohm
TDC= 21A
ICCM AX= 32A
OCP= 40A

U42
LL=2.4 mohm
TDC= 42A
ICCM AX= 64A
OCP= 70A

CORE2_UG

3

CORE2_LX

2
6
7

9

GND

VCC_CORE2

2

U42@

PCZ41

2.2U_0402_6.3V6M

2 1

CORE2_BST

CORE2_BST_R

2 1

U42@

PCZ35

0.1U_0402_25V6

CORE2_LG

VCC_ GT
FSW=450kHz
Chok e=0 .15u H
DCR=0.67 mohm +/- 5%

U22
LL=3.1 mohm
TDC= 18A
ICCM AX= 31A
OCP= 39A

U42
LL=3.1 mohm
TDC= 12A
ICCM AX= 28A
OCP= 39A

CORE2_UG_R

U42@

PQZ4
AON6314_N_DFN56-8-5

5

4

3

2

5 1

4

321

2 1

2 1

EMIU42@ PCZ33

0.1U_0402_25V6

2200P_0402_50V7K

@EMIU42@ PCZ36
U42@

PQZ3
AON6380_DFN5X6-8-5

1

4.7_1206_5%

U42@ PRZ87 U42@ PRZ103 U42@PCZ43

U42RF@ PRZ84

2

1.2K_0402_1%1.2K_0402_1%

AISPCORE2_R

1 2 1 2

CORE2_SNUB

1

PCZ45 U42RF@

680P_0402_50V7K

2

VCC_ SA
FSW=600kHz
DCR=6.2 mohm +/- 5%

U22
LL=10.3 mohm
TDC= 4A
ICCM AX= 5A
OCP= 10A

U42
LL=10.3 mohm
TDC= 4A
ICCM AX= 5A
OCP= 10A

PCZ32

@

2 1

2 1

10U_0805_25V6

10U_0805_25V6K

10U_0805_25V6K

U42@ PCZ37

U42@ PCZ34

Rdc=0.98 mohm

U42@PLZ2

1 4
2 3

0.15UH_NA36A_20%

@ PCZ206

2 1

K

10U_0805_25V6K

0.1U_0402_25V6K

1 2

@ PRZ90

10_0402_1%

1 2

+19VB_C PU

2 1

+VCCCORE

AVCORE2 <48>

AISPCORE2 <48>

2 1

2 1

EMI@ PCA2

0.1U_0402_25V6

2200P_0402_50V7K

1 2 1 2

PRA6 PRA9
1K_0402_1% 1K_0402_1%

+19VB_C PU

Rdc=0.98 mohm

1 4
2 3

PLA1

0.47UH_NA12.2A_20%

0.1U_0402_25V6K

PRA7
825_0402_1%

1 2

AVCCSA_R

1K_0402_5%_TSM0B102J3652RE

PCA7

1 2

1K_0402_1%

1 2

1 2

PHA1

+VCCSA

PRA8

AVCCSA <48>

AISPVCCSA <48 >

SecuriiitttyClllassiiifffiiicatttiiion

IIIssued Dattte

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPE RTY OF COMPA L ELECTRONIIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL AND
TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANS FERED F ROM THE CUSTOD Y OF THE COMPETEN T DIIIVIIISIIION OF R&D
DEPARTME NT EXCEPT AS AUTHORIIIZED B Y COMPAL ELECTRONIIICS,,, IIINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIITCONTAIIINS
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WI IITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,,IIINC...

2018/03/09

Compalll Secret Data

DeciiipheredDatett

2019/03/09

Compal Electronics, Inc.

Tiiitttllle

CPU Powerstage

Siiize DocumentttNumberrr

Dattte::: Frrriiiday,,, Marrrch 09,,,2018

Sheettt 49 offf

Re v

1...0

55

PRA2

PUA1

RT9610CGQW_WDFN8_2X2

4

BOOT UG ATE

5

PWM PHASE
EN PGND

8

VCC LGATE

2.2_0603_5%

SA_BST_R

1 2

SA_UG SA_UG_R

3

SA_LX

2
6
7

9

GND

12

SA_LG

PCA3

0.1U_0402_25V6

1

G1

9

D2/S1 D1

8

3

D12D1

S26S2

7

SA_BST

<48> PWM_SA

+5VALW

PRA1 1_0402_5%

A A

DRVEN1

VCC_SA

2

1

PCA1

2.2U_0402_6.3V6M

2 1

5 4 3 2 1

4

D1

S25G2

PQA1
AONH36334_DFN3X3A8-10

10

12

PCA5

PCA4

2 1

10U_0805_25V6

K

@EMI@ PCA6

10U_0805_25V6K

RF@ PRA4

4.7_1206_5%

2 1

AISPVCCSA_R

SA_SNUB

1

PCA8 RF@

680P_0402_50V7K

2

5 4 3

PWM-VID Spec and component Values

PWM-VID Spec Config A ConfigB

Vmin

0.6V 0.6V

Vmax 1.2V 1.2V
Vboot 0.875V 0.9V

D D

Voltagestep 6.25mV 6.25mV
N ofVoltage level 96 96

Rrefadj PR8 39K 20K

Module model information

RT8812A-1P_V2A.mdd for IC portion

RT8812A-1P_V2B.mdd for SW portion

<24> PSI

C C

12

PR7

Rref1

Rboot

PR10

2K_0402_1%

1 2

1

Rref2

18K_0402_1%

2

0.01U_0402_16V7

K

@VGA@ PC19

0_0402_1% PR20

2 1 2 1

B B

PC10
1U_0201_6.3V6M

1 2

VGA_B+

A A

<21> VDD_SENSE_GPU

Remark: 2. Soft-Start time (Internal) is 0.7ms (PC18 un-pop)

1. Switchingfrequency setting: Tss=(Css*Vrefin)/Iss+2.3ms
Fsw=(Vin-0.5)/(2*Vin*Rton*3.2p) =0.01U*0.9V/5uA+2.3ms=4.1ms (PC18 pop)

=304.89Khz

@VGA@ PR21

@VGA@ PR26

1

0_0805_5%

@VGA@ PC42

1U_0603_25V6K

<21> GND_SENSE_GPU

+VGA_CORE

2

12

5 4 3 2 1

RGND

@VGA@PR15

1

10_0402_1%

@VGA@ PR18

N16_VGA@ PC9

0_0402_1%

1 2

PR16

10_0402_1%

1 2

1 2

0_0402_1%

<24> GPU_VID0

20K_0402_1% 1

Rrefadj

1 2

PR8
20K_0402_1%

2 1

C

2700P_0402_50V7K

PR13

1 2

499K_0402_1%

PR19

Rton

2

Rref1 PR7 39K 20K

Rboot PR10 1.5K 2K

Rref2=PR20+PR21

PR3@VGA@
0_0402_5%

1 2

+3VS_VGA

REFADJ

REFIN

VREF_VGA

TON

RGND

2 1

1000P_0402_50V7

K

@VGA@ PC17

GPU_VSENSE

C

PR4 @VGA@

1

PR1 @VGA@

PR20 30K 18K 24K
PR21 1.5K 0 3K
PC9 1.5nf 2.7nf 1.8nf

+3VS_DGPU_AON

1

PR22
10K_0402_5%

1 2

PR23
10K_0402_5%

2

0_0402_1%

2

2

1K_0402_5%

GPU_VID

5

PU1

VID

6

REFADJ

7

REFIN

8

VREF

RT8812AGQW_WQFN20_3X3

9

TON LGATE2

10

RGND

GND

SS

11

21

1

Css

2

@VGA@ PC18

OpenVRegConfigurations

Operation phase Number PSI Voltagesetting
1 phasewithDEM 0V to0.8V

1 phasewithCCM 1.2V to1.8V

Active phasewithCCM 2.4V to5.5V

2 1

GPU_PSI

GPU_EN

4

12

0.01U_0402_16V7K

2

EN

PGOOD

14

PR17

10K_0402_5%

1 2

1

UGATE1

UGATE2

15

3

PSI

VSNS

13

ConfigC

0.65V

1.15V

0.9V

25mV

20

39K
30K
3K

PR2

1K_0402_5%

1 2

PC5@VGA@

.1U_0402_16V7K

DH1_VGA

BST_VGA

BOOT1

20

PHASE1

19

LGATE1

18

PVCC

17

16

PHASE2

BOOT2

+3VS

DGPU_PWROK <21,25,26>

SecurityClassification

Issued Date

THIS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIET ARY PROPERTY O F CO MPAL ELECT RONIC S, INC. AND CONT AINS CONF IDENTIAL AND
TRADE SECRET INFORMAT ION. T HIS SH EET MAY NOT BE TRANSF ERED FR OM THE CUSTODY O F THE CO MPET ENT DIVISI ON OF R&D
DEPART MENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RONIC S, INC. NEITH ER THIS SHEET NO R THE INFORMATION IT CO NTAINS
MAY BE USED BY OR DISCLOS ED TO ANY THIRD PART Y W ITHO UT PRIOR WRITTEN CON SENT OF COMPAL EL ECTRO NICS, INC.

Current Limit threshold setting
Rocset= (Ivalley * Rds(on) + 40 mV) / 10uA

I_ripple=(19-0.9)*0.9/
(304.89Khz*0.36u*19)=7.811A

Iocp=42A per phase
Ivalley=42A-7.811A/2=38.0945A

Choke: 0.22uH (Size:10*10*4)
Rdc=0.82 ± 5 %
Heat Rating Current=40A
Saturation Current=90A

C=3*330uF (9mohm)=990uF
Vripple=Iripple*ESR(min)=7.811A*3mohm=23.4mV

Pull high on HW side

DGPU_MAIN_EN <24,26>

MX130@ PQ1202

AON6994_DFN5X6D-8-7

PR6

2.2_0603_5%

1 2

LX1_VGA

DL1_VGA

GPU_PVCC

BST_VGA-1

3

1

PC8 MX130@ PQ1201

0.22U_0603_25V7K AON6994_DFN5X6D-8-7

2

Rocset

@VGA@ PR14

0_0402_5%

1 2

PC16
1U_0402_6.3V6K

2 1

+5VALW

2018/03/09 Deciphered Date

2

S2

12

MX110@

VGA_B+

1

D1

G1

D2/S1

S24S2

G2

5

6

DL1_VGA

PR12

12.4K_0402_0.5

%

MX130@ PR12

14.3K_0402_1%

Compal SecretData

2 1

10U_0805_25V6

10U_0805_25V6

K

DH1_VGA

MX130@ PC4

MX130@ PC3

LX1_VGA

7

MX110@PQ1201

AON6962_DFN5X6D-8-7

2 1

K

2

S2

3

+VGA_CORE

2 1

Different VGA Chip (different EDP-Peak Current) need select different solution

VGAChip N14P-GV N14M-LP N14P-LP

Config B ConfigB Config B

Rated TDP Power atTj=102C

Boosted GPU Total atTj=102C

EDP-Continuous atTj=102C

EDP-Peak at Tj=102C

Istep max (Evaluation)

OCP SettingCurrent

Rocset （PR12）

Recommendation

Polymer Cap (330uF)

18W 13W 18.9W

25W 20W 23W

24A 22A 25A

35A 35A 35A

15A 20A 14A

42A 42A 42A

10.2K 10.2K 10.2K

1phase 2H2L 1phase2H2L 1phase2H2L

6mohm* 2 6mohm* 2 6mohm *2

Or OSCON (390uF) 10mohm* 3 10mohm* 3 10mohm * 3

Whether needs 3 OSCON capacitorsdepend on DC ripple test results!

VGA_B+

D1

S24S2

5

D2/S1

1

G1

7

G2

6

DL1_VGA

DH1_VGA

PC1314

10U_0805_25V6

K

PL2

0.22UH WSRPG1004-R22M-AG-R8240A

LX1_VGA

1

1

2

PR11 VRF@

UB_VGA

4.7_1206_5%

2

SN

1

PC15 VRF@

680P_0402_50V7K

2

2 1

PC1315

10U_0805_25V6

4
3

2 1

2 1

K

1

+

PC11

330U_2V_M

2

VEMI@ PC6

2200P_0402_50V7

K

Under GPU Core

PC2

2 1

2 1

2019/03/09

12

PC2

PC2

2 1

0

4.7U_0402_6.3V6M

1

4.7U_0402_6.3V6M

PC3

PC3

2 1

2 1

0

1U_0201_6.3V6M

1

1U_0201_6.3V6M

PC2

2 1

2

4.7U_0402_6.3V6M

PC3

2 1

2

1U_0201_6.3V6M

12

PC2

PC2

2 1

4

4.7U_0402_6.3V6M

3

4.7U_0402_6.3V6M

PC3

PC3

2 1

2 1

3

1U_0201_6.3V6M

4

22U_0603_6.3V6M

Tiiitllle

Siiize Document Number

Compal Electronics, Inc.

Custom

Friiiday, March 09, 2018

PC2

2 1

6

5

4.7U_0402_6.3V6M

PC3

PC3

2 1

5

22U_0603_6.3V6M

VEMI@PL1

5A_Z80_0805_2P

1 2

2 1

+VGA_CORE MX110

@VEMI@ PC7

0.1U_0402_25V

6

EDP-Continuous 18.8A
EDP-Peak 31A
OCP min 40A

+VGA_CORE

1

+

PC12

330U_2V_M

2

1

+

PC13

2

+VGA_CORE MX130

EDP-Continuous 27.2A
EDP-Peak 53A
OCP min 65A

GB2B-64 package

PC2

PC2

PC2

2 1

2 1

2 1

4.7U_0402_6.3V6M

7

4.7U_0402_6.3V6M

8

4.7U_0402_6.3V6M

9

4.7U_0402_6.3V6M

PC3

2 1

7

4.7U_0402_6.3V6M

6

4.7U_0402_6.3V6M

VGA_CORE

VGA_CORE

PC3

PC3

2 1

2 1

9

4.7U_0402_6.3V6M

8

4.7U_0402_6.3V6M

Sheet 51 o f 55Date:

B+

330U_2V_M

PC4

2 1

0

4.7U_0402_6.3V6M

Rev

1.0

A

B

C

D

E

Module model information

SY8286_V2_sin gl e.m dd
SY8286 _V2 _du al. mdd

+3VS

Confirm HW side

1 1

B+

PR1305

10K_0402_1%

<25,26> 1.35V_PWR_EN

EN :H>0.8V ; L<0.4V

EN pin don't floating
If have pull down resistor at HW side,

please delete PR601.

2 2

1 2

1M_0402_1%

PR1307

2 1

+19VB_VRAM

@

PJ1301

1

122

JUMP_43X79

12

0.1U_0402_25V6

PC1312

2 1

2 1

0.1U_0402_25V6

VEMI@ PC1301

2200P_0402_50V

7K

@VEMI@ PC1303

+19VB_VRAM

12

PC1304

10U_0805_25V6

K

+3VALW

+3VALW

12

@VGA@

PR1309

0_0402_5%

12

@VGA@

PR1310

0_0402_5%

The current limit is set to 6A, 9A or 12A when this pin
is pull low, floating or pull high.

EN_VRAM
ILMT_VRAM

2 1

2

3
4

5
7
8

18
11
13

15

BYP

PC131

3

1U_0201_6.3V6M

PU1301

IN
IN

IN
IN
GND
GND
GND
EN
ILMT

SY8286RAC_QFN20_3X3

VCC

PAD

12

PR1301
100K_0402_5%

BST_VRAM
LX_VRAM

FB_VRAM
LDO_3V_VRAM

+1.35VGS_PGOOD <26>

9

PG

1

BS

6

LX

19

LX

20

LX

14

FB

17
10

NC

12

NC

16

NC

21

keep short pad,
snubber is for EMI only.

@VGA@PR1303

0_0402_5%

BST_VRAM_R

2

1

12

PC1311

2.2U_0402_6.3V6M

@VEMI@ PR1302

4.7_1206_5%

1 1 2

PC1305

0.1U_0402_25V6

1 2

Use 7x7x3 size when the layout space is enough.

1UH_6.6A_20%_5X5X3_M

FB=0.6V

Vout=0.6V* (1+R1/R2) R2

=0.6*(1+(27/21.5))

SNUB_VRAM

2

PL1301

1 2

@VEMI@ PC1302

680P_0603_50V7K

12

R1

12

PR1304

27K_0402_1

%

1 2 12

PR1308

21.5K_0402_1%

PC1306

330P_0402_50V

7K

PR1306
1K_0402_1%

+1.35VGSP

2 1

2 1

PC1308

PC1307

22U_0603_6.3V6

M

2 1

2 1

PC1310

PC1309

22U_0603_6.3V6

M

22U_0603_6.3V6

M

22U_0603_6.3V6

M

@

PJ1302

JUMP_43X118

1

+1.35VGSP

122

+1.35VS_VRAM

Vout=1.353V

3 3

4 4

Securiiity Clllassiiifiiicatiiion

Issued Date

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL AND
TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIION OF R&D DEPARTMENT
EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IIINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIIT CONTAIIINS

A

B

MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IIINC...

C

2018/03/09 2019/03/09

Compal SecretData

Decipherii ed Date

D

CCoommppaallEElleeccttrroonniiccss,,Inc.

Tiiitttllle

SY8286

Siiize DocumentttNumber

C

Rev

Sheettt

E

52 o fff 55Dattte::: Friiiday,,, March 09,,,2018

1...0

<7,18> DDR_A_MA[0..16]

5

4

3

2

1

D D

C C

B B

+1.2V

1U_0201_6.3V6M

1U_0201_6.3V6M

SE000 00UC00

SE000 00UC00

SE000 00UC00

CU195

CU198 @

12

12

1U_0201_6.3V6M

1U_0201_6.3V6M

CU197

12

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

SE000 00UC00

SE000 00UC00

SE000 00UC00

CU200

CU199

12

CU196

12

12

1U_0201_6.3V6M

SE000 00UC00

SE000 00UC00

SE000 00UC00

CU201

CD211

12

12

12

4 as near each on bo ard RAM dev ice as po ssible

10U_06 03_6.3V6M

1

CD25

2

+2.5V +0.6VS

1U_0201_6.3V6M

SE000 00UC00

CU206 @

12

1

1

CD27

CD26

2

2

1U_0201_6.3V6M

1U_0201_6.3V6M

SE000 00UC00

SE000 00UC00

12

SE000 00UC00

CU205

CU203

12

10U_06 03_6.3V6M

10U_06 03_6.3V6M

10U_06 03_6.3V6M

1

10U_06 03_6.3V6M

1

1

CD39

CD40

+

CU89

220U_6 .3V_M

2

12

@

2

2

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

SE000 00UC00

CU207

CU208

12

1U_0201_6.3V6M

SE000 00UC00

CU204 @

12

1U_0201_6.3V6M

SE000 00UC00

SE000 00UC00

CU209

CU210

12

12

2 as near each on boa rd RAM dev ice as po ssible

10U_0603_6.3V6M

10U_06 03_6.3V6M

10U_0603_6.3V6M

SE000 005T80

1

1

CD220 @

CD41 @

2

2

10U_06 03_6.3V6M

SE000 005T80

1

2

10U_06 03_6.3V6M

1

CD219 @

1

CD42

CD43

2

2

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

SE000 00UC00

CD212

CD210 @

12

1U_0201_6.3V6M

1U_0201_6.3V6M

SE000 00UC00

SE000 00UC00

CD214

CD213

12

12

1U_0201_6.3V6M

SE000 00UC00

CU216

12

1U_0201_6.3V6M

1U_0201_6.3V6M

SE000 00UC00

SE000 00UC00

SE000 00UC00

CD216

CD215

12

12

1U_0201_6.3V6M

1U_0201_6.3V6M

SE000 00UC00

CU213 @

CU212 @

12

12

2 as near each on boa rd RAM dev ice as po ssible

10U_06 03_6.3V6M

10U_06 03_6.3V6M

1

1

CD46 @

CD47

2 2

1U_0201_6.3V6M

SE000 00UC00

SE000 00UC00

CD217

CD218

12

12

DDR_A_MA9

1

DDR_A_MA2

2

DDR_A_MA4

3

DDR_A_BA1

DDR_A_MA1 0
DDR_A_MA3
DDR_A_MA1 2
DDR_A_B G0

DDR_A_MA1 6
M_A_ACT#
DDR_A_CS#0
DDR_A_MA1 5

DDR_A_CKE0
DDR_A_O DT0

DDR_A_MA1 4

DDR_A_MA1 3
DDR_A_MA8
DDR_A_P ARITY
DDR_A_MA1 1

DDR_A_MA1
DDR_A_BA0

DDR_A_MA7

DDR_A_MA5

DDR_A_MA6
DDR_A_MA0

1 DDP@ 2

4 5

36_080 4_8P4R_5%

1

2

3

4

36_080 4_8P4R_5%

1

2
3

4

36_080 4_8P4R_5%

RD211 36 _0402_1%

1

2

3

4

36_080 4_8P4R_5%

1

2

3

4

36_080 4_8P4R_5%

1 8
2
3
4

36_080 4_8P4R_5%

1 8

3
4

36_080 4_8P4R_5%

<7,18> D DR_A_BA1

<7,18> D DR_A_BG0

<7,18> M_A_ACT#

<7,18> DDR_A_CS#0

<18> DDR_A_BG 1_R

<7,18> DDR_A_CKE0

<7,18> DDR_A_ODT0

1U_0201_6.3V6M

1U_0201_6.3V6M

SE000 00UC00

SE000 00UC00

CU218

CU215

12

12

1U_0201_6.3V6M

1U_0201_6.3V6M

SE000 00UC00

CU214

12

1U_0201_6.3V6M

SE000 00UC00

SE000 00UC00

CU217

CU211

12

12

<7,18> DD R_A_PARI TY

<7,18> D DR_A_BA0

DDR_A_B G1_R

+0.6VS

RP17

8
7
6

RP18

8
7
6
5

RP19

8
7
6
5

RP20

8
7
6
5

RP21

8
7
6
5

RP22

7
6
5

RP24

72
6
5

A A

LA---G201P

Securiiittty Clllassiiifffiiicatttiiion

IIIssued Dattte

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL AND TRADE
SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIION OF R&D DEPARTMENT EXCEPT
AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IIINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIIT CONTAIIINS

5

4

3

MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IIINC...

2018/03/09////

Compalll Secret Data

2

Decipii he red Dattte

2019///03///09

Tiiitttllle

Siiize Documenttt Numberrr

Custttom

DDR4 MISC

LA-D562P

1

Rev

Sheettt 20 offf 55Dattte::: Frrriiiday,,, Marrrch 09,,,2018

1...0

1

2

3

4

5

+VCCCORE +VCCGT

A A

1

1

1

PCZ 58

PCZ 60

PCZ 59

2

2

2

@

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

1

2

1

B B

2

1

2

2 1

C C

2 1

PCZ 80

U22@

22U_0603_6.3V6M

PCZ 100

U22B @ @

22U_0603_6.3V6M

PCZ 124

22U_0603_6.3V6M

PCZ 141

1U_0201_6.3V6M

PCZ 161

1U_0201_6.3V6M

PCZ 82

PCZ 81

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

PCZ 101

PCZ 102

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

PCZ 126

PCZ 125

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

2 1

2 1

PCZ 143

PCZ 142

1U_0201_6.3V6M

1U_0201_6.3V6M

2 1

2 1

PCZ 162

PCZ 163

1U_0201_6.3V6M

1U_0201_6.3V6M

V C C C OR E ：
U22
22uF*28
1uF*35

1

U42

+

330 uF* 1
22uF*28

2

1uF*35

U42 @ P CZ4 8

330U_D1_2VY_R9M

1

PCZ 61

2

@

22U_0603_6.3V6M

1

PCZ 83

2

22U_0603_6.3V6M

1

PCZ 103

2

@

22U_0603_6.3V6M

1

PCZ 127

2

22U_0603_6.3V6M

2 1

PCZ 144

1U_0201_6.3V6M

2 1

PCZ 164

1U_0201_6.3V6M

1

1

1

PCZ 63

PCZ 62

2

2

U22B @

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

PCZ 84

PCZ 85

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

PCZ 105

PCZ 104

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

PCZ 128

PCZ 129

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

2 1

2 1

PCZ 145

PCZ 146

1U_0201_6.3V6M

1U_0201_6.3V6M

2 1

2 1

PCZ 165

PCZ 166

1U_0201_6.3V6M

1U_0201_6.3V6M

2 1

2 1

2

U22@2@

1

2

1

2

1

2

1

1

PCZ 64

22U_0603_6.3V6M

PCZ 86

22U_0603_6.3V6M

PCZ 106

22U_0603_6.3V6M

PCZ 130

22U_0603_6.3V6M

PCZ 147

1U_0201_6.3V6M

PCZ 167

1U_0201_6.3V6M

1

PCZ 66

PCZ 65

PCZ 67

2

2

@

@

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

PCZ 87

PCZ 88

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

PCZ 108

PCZ 107

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

2 1

2 1

2 1

PCZ 149

PCZ 150

PCZ 148

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

2 1

2 1

2 1

PCZ 169

PCZ 168

PCZ 170

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1

+

PCZ 49

330U_D 1_2VY_R9 M

2

1

PCZ 50

2

1

PCZ 89

2

1

PCZ 109

2

1

PCZ 131

2

2 1

PCZ 151

2 1

PCZ 171

V C C G T ：
U22 & U42
330uF*1
22uF*33
1uF*13

+VCCSA

1

1

1

PCZ 51

PCZ 52

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

PCZ 90

PCZ 91

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

PCZ 111

PCZ 110

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

PCZ 133

PCZ 132

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

2 1

2 1

PCZ 152

PCZ 153

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

2 1

2 1

PCZ 172

PCZ 173

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1

1

PCZ 53

PCZ 55

PCZ 54

2

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

1

PCZ 92

PCZ 93

2

1

2

1

2

2 1

PCZ 94

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

PCZ 113

PCZ 112

PCZ 114

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

PCZ 134

PCZ 136

PCZ 135

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

2 1

2 1

PCZ 156

PCZ 155

PCZ 154

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

+VCCGT_VCCCORE

1

1

1

PCZ 56

2

22U_0603_6.3V6M

1

PCZ 95

2

22U_0603_6.3V6M

1

PCZ 115

2

22U_0603_6.3V6M

1

PCZ 137

2

22U_0603_6.3V6M

2 1

PCZ 157

1U_0201_6.3V6M

1

PCZ 68

PCZ 57

PCZ 69

2

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

PCZ 96

PCZ 97

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

1

PCZ 116

2

22U_0603_6.3V6M

1

1

1

PCZ 139

PCZ 140

PCZ 138

2

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

2 1

2 1

2 1

PCZ 160

PCZ 159

PCZ 158

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

U42 co-lay

V C C S A ：
U22 & U42
22uF*9
1uF*7

1

1

PCZ 70

2

2

22U_0603_6.3V6M

1

1

PCZ 98

2

2

22U_0603_6.3V6M

2 1

2 1

PCZ 117

1U_0201_6.3V6M

1

1

1

1

1

PCZ 75

PCZ 73

PCZ 71

PCZ 72

PCZ 74

2

2

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

PCZ 99

22U_0603_6.3V6M

2 1

2 1

2 1

PCZ 118

PCZ 119

1U_0201_6.3V6M

2 1

PCZ 120

PCZ 121

1U_0201_6.3V6M

PCZ 122

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1

1

PCZ 76

2

22U_0603_6.3V6M

2 1

PCZ 123

1U_0201_6.3V6M

1

PCZ 77

PCZ 78

2

PCZ 79

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

1 2

1 2

1 2

2

U42@ U42 @

U22B@

U42B@

U42B@

2 1

2 1

D D

1

PCZ 185

PCZ 182

PCZ 177

PCZ 176

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

2 1

2 1

2 1

PCZ 190

PCZ 191

PCZ 189

PCZ 188

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

2 1

2 1

2 1

2 1

2 1

2 1

2 1

1U_0201_6.3V6M

2 1

1U_0201_6.3V6M

PCZ 186

PCZ 178

PCZ 183

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

PCZ 192

1U_0201_6.3V6M

2 1

2 1

PCZ 179

PCZ 187

PCZ 180

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

KBL R@ P CZ20 2

22U_06 03_6.3V6M

KBL R@ P CZ20 3

22U_06 03_6.3V6M

U22/U42 co-lay

+VCCGT

+VCCCORE +VCC GT_V CCCO RE

PRZ 201 SX000 000300 1 2 SOLD ER_PR EFORM S_04 02

PRZ 202 SX00 0000300 1

PRZ 203 SX00 0000300 1

2

1

PCZ 202

PCZ 201

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

U42@ U 42@

2 S OLD ER_P REFOR MS_04 02

2 S OLD ER_P REFOR MS_04 02

1

PCZ 203

PCZ 204

2

22U_0603_6.3V6M

22U_0603_6.3V6M

SecuriiittyClllassiiiffiiicattiiion

IIssued Datte

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL AND TRADE
SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIION OF R&D DEPARTMENT EXCEPT AS
AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IIINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIIT CONTAIIINS

3

MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,,IIINC...

2018/03/09

4

Compalll Secret Data

DeciiipheredDatett

2019/03/09

Compal Electronics, Inc.

Tiiitttllle

PROCESSORDECOUPLING

Siiize Documenttt Numberrr

Dattte::: Frrriiiday,,, Marrrch 09,,,2018

5

Sheettt 50 offf 55

R ev

1...0

Item

5

Version change list (P.I.R. List)

Reason for change

4

3 2 1

Page 1 of 1

for PWR

PG# Modify List

Date

Phase

1

Down size for material shortage

D D

C C

2

Down size for material shortage

3

Down size for material shortage(U42 SKU)

4

Down size for material shortage

5

Down size for material shortage

6

Down size for material shortage

7

Down size for material shortage

Change size for common design

8

9

Down size for material shortage

10

Down size for material shortage

11

Down size for material shortage

P49 Change PRA6,PRA9,PRG6 from 1K +-1% 0603 to 1K +-1% 0402

P49 Change PRZ102,PRZ85 from 1.2K +-1% 0603 to 1.2K +-1% 0402

P49 Change PRZ103,PRZ87 from 1.2K +-1% 0603 to 1.2K +-1% 0402

P49 Change PRG9 from 2.05K +-1% 0603 to 2.05K +-1% 0402

P43

P50

P51

P49

P44

P48

P51

P45

Change PR404 from 499K +-1% 0402 to 150K +-1% 0402
Change PC429 from 1U 16V K X5R 0402 to 1U 6.3V M X5R 0201

Change PC10,PC1313,PC30,PC31,PC32,PC33,PC614,PC801,PC806,PCZ117,PCZ151,
PCZ166,PCZ167,PCZ170,PCZ179 from 1U 6.3V K X5R 0402 to 1U 6.3V M X5R 0201

Change PCA1,PCG1,PCZ40,PCZ41 from 2.2U 16V K X5R 0402 to

2.2U 6.3V M X5R 0402

Change PC401,PC418,PC603,PC1305 from 0.1U 10V K X5R 0201 to

0.1U 25V K X5R 0402

Change PCZ23 from 4.7U 10V K X5R 0603 to S CER CAP 4.7U 10V M X5R 0402

Change PC20,PC28,PC36,PC37,PC38,PC39,PC40 from 4.7U 6.3V K X5R 0603
to 4.7U 6.3V M X5R 0402

Change PC505 from CAP .1U 25V K X7R 0603 to 0.1U 25V K X7R 0402

2018.03.05

2018.03.05

2018.03.05

2018.03.05

2018.03.05

2018.03.05

2018.03.05

2018.03.05

2018.03.05

2018.03.05

2018.03.05

SVT

SVT

SVT

SVT

SVT

SVT

SVT

SVT

SVT

SVT

SVT

B B

16

17

A A

Security Classification

IssuedDate

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2018/03/09 2019/03/09

Compal Secret Data

DecipheredDate

Tiiitllle

Siiize Document Number

Custom

Date: Friiiday, March 09, 2018

Compal Electronics,Inc.

PIR (PWR)

Z_BDW

Sheet 53 of

1

R ev

1.0

55

5 4 3 2 1

Version change list
(P.I.R. List)

Page 1 of 2 for
HW

Item Reason for change PG# Modify List Date Phase

1

ME Request

2

ME Request

D D

3

0 Ohm Reduction

4

0 Ohm Reduction

5

0 Ohm Reduction

6

Phase Out Un-Necessary X4E Level

7

Update 14" PCB DA Part Number.

8

Cost Down Plan

9

0 Ohm Reduction

10

Cost Down Plan

11

Cost Down Plan

12

Cost Down Plan

13

14

15

16

17

18

19

20

21

Cost Down Plan

0 Ohm Reduction

0 Ohm Reduction

0 Ohm Reduction

0 Ohm Reduction

0 Ohm Reduction

0 Ohm Reduction

0 Ohm Reduction

0 Ohm Reduction

C C

41

41

31

34

29

3

3

36

36

20

19

18

13

35

39

10

19

39

37

32

40

Add Screw Hole H15. 2017/12/13 EVT -> PVT

Remove Screw Hole H16. 2017/12/15 EVT -> PVT

Replace RA2 with R-Short. 2017/12/18 EVT -> PVT

Replace R242 with R-Short. 2017/12/18 EVT -> PVT

Replace R203, R211, R212 with R-Short. 2017/12/18 EVT -> PVT

Remove X4EABQ38L51 and X4EABQ38L52. 2017/12/19 EVT -> PVT

DA6001YG000 -> DA6001YG100

2017/12/19 EVT -> PVT

C2147, C2149 -> 14" Only (BOM Structure Modify) 2017/12/20 EVT -> PVT

Replace R420 with R-Short. 2017/12/20 EVT -> PVT

Un-Pop CU206, CU204, CD41, CU198, CD210, CU213, CU212, CD46 2017/12/21 EVT -> PVT

Un-Pop C2140, CD19, CD10, CD32, CD33, CD23

2017/12/21 EVT -> PVT

Un-Pop CD127 2017/12/21 EVT -> PVT

Replace CC45 with 10uF 2017/12/21 EVT -> PVT

Replace R233 with R-Short. 2017/12/21 EVT -> PVT

Replace R275, R276, R277, R279 with R-Short. 2017/12/21 EVT -> PVT

Replace RC103 with R-Short. 2017/12/21 EVT -> PVT

Replace RD108, RD140 with R-Short. 2017/12/21 EVT -> PVT

Replace R283 with R-Short. 2017/12/21 EVT -> PVT

Replace R425, R428, R102 with R-Short. 2017/12/21 EVT -> PVT

Replace RL18 with R-Short. 2017/12/21 EVT -> PVT

Replace R371 with R-Short. 2017/12/21 EVT -> PVT

22

Cost Down Plan

B B

23

Cost Down Plan

24

Cost Down Plan

25

Cost Down Plan

26

Cost Down Plan

27

Cost Down Plan

28

Cost Down Plan

29

Cost Down Plan

30

31

Cost Down Plan

VRAM EOL

5 4

A A

28

27

22

28

27

41

13

18

20

27, 28

Un-Pop CV703, CV707, CV708, CV718 (DIS@) 2017/12/21 EVT -> PVT

Un-Pop CV603, CV607, CV614, CV616, CV617 (DIS@) 2017/12/21 EVT -> PVT

Un-Pop CV35 (DIS@) 2017/12/21 EVT -> PVT

Replace CV701 with 10uF 2017/12/21 EVT -> PVT

Replace CV602 with 10uF 2017/12/21 EVT -> PVT

Un-Pop Q401, R401, R402 2017/12/21 EVT -> PVT

Un-Pop CC40 2017/12/21 EVT -> PVT

Replace RD200, RD201, RD202, RD203, RD205 with R-Short. (SDP@/DDP@) 2017/12/21 EVT -> PVT

RD211 -> DDP Only (BOM Structure Modify) 2017/12/21 EVT -> PVT

Remove VRAM UV8, UV9 (Replace with x32 DIE *2) 2017/12/22 EVT -> PVT

Securiiity Clllassiiifiiicatiiion

Issued Date

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL AND
TRADE SEC RET IIINFORMATIIION... THIIIS SHEET MAY NO T BE TRANSFERED FROM THE CUSTOD Y OF THE COMPETENT DIIIVIIISIIION OF R&D
DEPARTMENT EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IIINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIITCONTAIIINS

3 2 1

MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,,IIINC...

2018/03/09 2019/03/09

Compalll Secret Data

Deciiiphered Date

Tiiitttllle

Siiize Documenttt Numberrr

Custttom

Compal Electronics,Inc.

PIR (HW)
LA-G202P

Sheettt 54 o fff 55Dattte::: Frrriiiday,,, Marrrch 09,,, 2018

Rev

1...0

Item

5 4 3 2 1

Version change list
(P.I.R. List)

Page 2 of 2 for
HW

PhaseDateModify ListPG#Reason for change

1

ME Request

2

VRAM EOL Replace ROM_SI (RV65) BOM Structure with 256M*32 2017/12/25 EVT -> PVT

D D

3

VRAM EOL 2017/12/25 EVT -> PVT

4

Layout Footprint Update

5

VRAM EOL

6

Fine Tune YL1 Crystal Capacitor Value

7

Card Reader IC Controlled by X76

8

EMI Cost Down Plan

9

Prevent +3VS_WLAN Drop

10

ME Request

11

12

Card Reader IC BOM Structure Update Controlled by Main/Substitute, No X76 Anymore 2018/01/08 EVT -> PVT

13

C C

VRAM BOM Structure Update

14

15

Cap P/N Update

16

Cap P/N Update

17

Dual Load Switch P/N Update

18

Update CPU R3 Part Number

19

Resistor Fine Tune - LED3 and LED4

20

21

Keyboard Resistor Value Update

38

24

3

34, 35

27

31

3, 32

30

33

34, 35

3

32

3

11

40

40

13, 40

3

39

13, 40

38

Replace Touch Pad Connector Symbol (JTP1) - SP01001A800 2017/12/22 EVT -> PVT

Replace 2GB VRAM X76 BOM Structure with @ (X7677538L01, L02, L03)

Swap JHDD1, JODD2 Pin Define 2017/12/25 EVT -> PVT

2017/12/26 EVT -> PVTReplace UV7 Data Lanes / EDC / DBI / RV130.2 - Pull High +1.35VS_VRAM

CL13 / CL14 : 10pF -> 27pF

Realtek -> X7677538LA1 , Genesys -> X7677538LA2.

2017/12/26 EVT -> PVT

2017/12/26 EVT -> PVT

2017/12/28 EVT -> PVTReplace CA41, CA42 with R-Short (Location Changed to RA65, RA66)

Reserve C245, C246 2017/12/29 EVT -> PVT

Replace JODD2, JHDD1 Symbol with SP010025K00 2017/12/31 EVT -> PVT

Replace X7677538L04, L05, L06 BOM Structure with 2GB

2018/01/08 EVT -> PVTVRAM BOM Structure Update

Delete X7677538L01, L02, L03 (EVT VRAM*4 - 2GB) 2018/01/08 EVT -> PVT

Replace On Board RAM P/N with R3On Board RAM P/N Update 2018/01/08 EVT -> PVT

Replace C383 470pF with 1nF (SE074102K80)

Replace C386 220pF with 2.2nF (SE075222K80)

2018/01/08 EVT -> PVT

2018/01/08 EVT -> PVT

Replace UC5, U381 SA00006U300 with SA00007PM00 2018/01/08 EVT -> PVT

PVT -> Pre-MP2018/02/22Add SA0000BKN30 (i3-8130U R3) and SA0000BLH50 (i3-7020U R3).

Replace R376 and R378 with 200 Ohm. (SD034200080) 2018/02/22 PVT -> Pre-MP

Replace UC5, U381 - SA00007PM00 with SA0000BEL00.

Replace R271 with 0 Ohm (@)

2018/02/22 PVT -> Pre-MPDual Load Switch P/N Update. (Source Priority Changes)

2018/02/22

PVT -> Pre-MP

22

Keyboard Resistor Value Update

B B

23

Keyboard Resistor Value Update

24

Co-Lay Remove Remove LC99

25

Replace BOM Structure

26

Add CPU

27

Replace DA Part Number with DAZ P/N

28

38

38

17

3

3

3

36

Replace R278 with R-Short.

Replace R272, R274, "R277 (15@)" with 470 Ohm.

2018/02/22

2018/02/22

PVT -> Pre-MP

PVT -> Pre-MP

2018/02/27 PVT -> Pre-MP

Replace SA0000BLH50 BOM Structure with i3_7020U_U22@. 2018/03/09 PVT -> Pre-MP

Add SA0000BLD60 (SR3LD) - i3_7020U_U42@ 2018/03/09 PVT -> Pre-MP

Replace with DAZ29900201 (14_DAZ@) & DAZ29A00201 (15_DAZ@). 2018/03/09 PVT -> Pre-MP

Add C122 (0.1uF)

2018/03/09 PVT -> Pre-MPESD Request

29

30

A A

31

5 4

SecuriityCllassiiifiicattiion

Issued Date

THIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIETARY PROPERTY OF COMPAL ELECTRONIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL AND
TRADE SEC RET IIINFORMATIIION.. THIIS SHEET MAY NOT B E TRANSFERED FROM THE C USTODY OF THE COMP ETENT DIIIVIIISIIION OF R&D
DEPARTMENT EXCEPT AS AUTHORIIZED BY COMPAL ELECTRONIICS,,, IIINC.. NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIIT CONTAIIINS

3 2 1

MAY BE USED BY OR DIISCLOSED TO ANY THIIRD PARTY WIIITHOUT PRIIOR WRIITTEN CONSENT OF COMPAL ELECTRONIICS,,,IIINC..

2018//03/09 2019//03//09

Compal Secret Data

Deciiphei red Datte

Tiiitttllle

Siiize Documentt Numberr

Custttom

Compal Electronics,Inc.

PIR (HW)
LA-G202P

Sheettt 55 o fff 55Dattte::: Frrriiiday,,, Marrch 09,,2018

Rev

1...0