Compal LA-G07EP Schematic

A

B

C

D

E

1

Intel M/B Schematics Document

Kabylake-U(2+2)-DDR4 SODIMMx2

Kabylake-U(2+2)-DDR4 SODIMMx2Kabylake-U(2+2)-DDR4 SODIMMx2

2

nVidia N16 gDDR5-2GB

(N16S-GTR : GM108-670/770: GeForce MX130) (N16V-GMR1 : GM108-626/726:GeForce MX110)

Date :

Version :

3

Project :

(Modified&Ref from:

2018OPP_Harry Potter(15.6") EPK50 :LA-G07DP

(EPK52 :LA-G07EP=>v0.2 for PV)

2018-01-08

v0.3

(EPS50 :SKLU_4G:LA-G071P) (EPS50 :SKLU_2G:LA-G072P) (EPK50 :KBLU_4G:LA-G079P)

(EPK50 :KBLU_2G:LA-G07AP)

(EPK52 :KBLR_4G:LA-G07BP)

(EPK52 :KBLR_2G:LA-G07CP)

(EPK50 :KBLU:LA-G07DP) (EPK52 :KBLR:LA-G07EP)

01."NFLC_KBLR_LAE802PR10_MV_FINAL") (02."Canadiens_LA-F035P-R10_KBL-UR_2017-06-23_CPU") (02."CNL-U ORB_DDX02_LA-F152PR01_0822B")

(1.2mm_6L)

DIS

UMA

2

3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2015/10/22 2017/10/22

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

Cover Page

LA-G07DP(KBL-U_UMA_6L)

1 59Monday, January 08, 2018

of

1 59Monday, January 08, 2018

of

1 59Monday, January 08, 2018

E

v0.3

A

UV6 UV7

UV8 UV9(for 4GB)

UV8 UV9(for 4GB)UV8 UV9(for 4GB)

VRAM gDDR5x4pcs

256Mbx32

256Mbx32256Mbx32 (8Gb)

(8Gb)

1

(8Gb)(8Gb)

P.25

P.25P.25

JLAN

RJ45 CONN

P.29

P.29P.29

2

RTL8111HSH-CG

RTL8111HSH-CGRTL8111HSH-CG

NGFF WLAN+BT (Key E)

PUB1

Charger

P.47

P.47P.47

3

MB Board Information:

01.DA8001EG000, PCB 29I LA-G071P REV0 MB 3(SKLU_4G)

4 4

02.DA6001WL000, PCB 29I LA-G072P REV0 MB 3(SKLU_2G)

03.DA8001EH000, PCB 29M LA-G079P REV0 MB 3(KBLU_4G)

04.DA6001WM000, PCB 29M LA-G07AP REV0 MB 3(KBLU_2G)

05.DA8001EI000, PCB 29L LA-G07BP REV0 MB 3(KBLR_4G)

06.DA6001WI000, PCB 29L LA-G07CP REV0 MB 3(KBLR_2G)

07.DA6001YA000, PCB 29M LA-G07DP REV0 MB 3(KBLU_UMA)

08.DA6001YB000, PCB 29L LA-G07EP REV0 MB 3(KBLR_UMA)

Sub Board Information:(EPK52)

01.DA6001WJ000, PCB 29L LS-G071P REV0 IOB(435OM832L01)

02.DA4002LZ000, PCB 29L LS-G072P REV0 HDDB(435OM932L01)

03.DA4002M0000, PCB 29L LS-G073P REV0 TOUCH PADB(435OMA32L01)

04.DA6001WR00S, PCB 29L LS-G074P REV0 SSDB(435OMB32L01)

05.DA6001WS00S, PCB 29L LS-G075P REV0 eMMCB

A

Battery

dGPU

P.22

P.22P.22

PJPB1

P.46

P.46P.46

UV1

Thermal sensor

G753T11U

P.10

P.10P.10

JFAN

Fan

P.38

P.38P.38

75x70

UC3

SMBus1

SMBus2

KB light

B

nVidia

JEDP

P.27

P.27P.27

JHDMI

P.28

P.28P.28

UL1

P.29

P.29P.29

JWLAN

JWLANJWLAN

P.30

P.30P.30

EC ENE

KB9022QD

JKB

(MX130)

(MX110)

P.19~26

P.19~26P.19~26

N16S-GTR N16V-GMR1

eDP CONN

HDMI CONN

LAN

Int.KBD TouchPad

P.34

P.34P.34

*sub board

JKBL

P.34

P.34P.34

LS-G073PR01 DA4002M0000

SPI ROM 8MBytes

TPM

SLB9670VQ2.0

SLB9670VQ2.0SLB9670VQ2.0

B

C

UV1 UC1

PCIex4 Port #1~#4 PCIe 3.0:8Gb/s

Kaby Lake-RU42

eDPx2Lane

DDI Port 1x4Lane

1356P BGA

PCIex1 Port #5

PCIe Gen1 Only:2.5Gb/s

Port #6

PCIex1

PCIe Gen1 Only:2.5Gb/s

UK1

LPC

33MHz

P.33

P.33P.33

PS2

JTP

SMBus

P.34

P.34P.34

SPI 50MHz

UC2

P.07

P.07P.07

UT1

P.35

P.35P.35

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

D

Dual Channel

Interleaved

DDR4 2133MHz 1.2V

SATA 3.0

PCIe 3.0: 8Gb/s

Port 0

Port 1

PCIe x2

Port #11~#12

JHDD

P.30

SATA ODD

M.2 SSD

*need supported Intel Optane (3D Xpoint)

SATA 3.0 Port 2

USB3.0 5Gb/s

USB2.0 480Mb/s

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

Port 7

USB3.0 port

USB2.0 Port

Card Reader

AK6485RB63-GLF-GR

(sub board)

Camera

Bluetooth

Touch Screen

UA1

HDA

24MHz

2017/08/24 2018/08/24

HDA Aduio codec

ALC3247-CG

Compal Secret Data

Deciphered Date

D

P.32

P.32P.32

ChA:JDIMM1(REV)

ChA:JDIMM1(REV)ChA:JDIMM1(REV) ChB:JDIMM2(STD)

ChB:JDIMM2(STD)

ChB:JDIMM2(STD)ChB:JDIMM2(STD)

DDR4-SO-DIMM X 2

P.17~18

P.17~18P.17~18

JODD

P.30

P.30P.30

JSSD

(Key M)

NVMe

P.19

P.19P.19

JUSB1

Port 1

P.30

P.30P.30

JUSB2

P.31

P.31P.31

Port 2

JIO

P.31

P.31P.31

*sub board LS-G071PR01 DA6001WJ000

P.29

P.29P.29

JEDP

P.27

P.27P.27

JWLAN

P.30

P.30P.30

JEDP

P.27

P.27P.27

Internal SPK

Combo Jack

E

2.5" SATA HDD

(sub board)

M.2 SATA SSD

(sub board)

eMMC

(sub board)

*sub board LS-G072P DA4002LZ000

*sub board LS-G074P DA6001WR00S

*sub board LS-G075P DA6001WS00S

JSPK

P.32

P.32P.32

JHP

P.32

P.32P.32

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Block Diagrams

LA-G07DP(KBL-U_UMA_6L)

E

2 59Monday, January 08, 2018

v0.3

of

1

2

3

Power rail

+RTCVCC

VIN

BATT+

B+

+VL

+3VL

+5VALW

+3VALW

+3VALW_EC

1

+3V_PCH

+1.2V_VDDQ

+5VS

+3VS

+1.5VS

+1.05VS

+0.6V_0.6VS

+VCC_CORE

Control (EC)

X

EC_ON

PCH_PWR_EN

SYSON

SUSP#

X

BOM Structure Table (1/2)

Function

DGPU SKU

UMA SKU UMA@

2

R_i3_7020U_QN96@

UC1

R_SI_i3_7020U_QN96 Y0 2.3G

SA0000BLD00

S IC A32 FJ8067703282620 QN96 Y0 2.3G

R_i7_8550U_QNBF@

UC1

R_SI_i7_8550U_QNBF Y0 1.8G

SA0000AWC10

S IC A32 FJ8067703281816 QNBF Y0 1.8G

UC1

3

CPU

Stuff Un-Stuff

PX@

TPM@TPM

R_i3_8130U_QP8K@

UC1

R_SI_i3-8130U_QP8K Y0 2.2G

SA0000BKN10

S IC A32 FJ8067703282227 QP8K Y0 2.2G

U_i3_7020U_QNZU@

UC1

U_SI_i3-7020U_QNZU H0 2.3G

SA0000BLH00

S IC A32 FJ8067702739769 QNZU H0 2.3G

SMBCLK

R7

SMBDATA

R8

SML0CLK

R9

SML0DATA

W2

SML1CLK

W3

SML1DATA

V3

U6 U7

A

Source (CPU)

X

PM_SLP_S5#/PM_SLP_S4#

PM_SLP_S3#

VR12.5_VR_ON

+3V_PRIM

R=1K

+3V_PRIM

R=499

+3V_PRIM

R=1K

i3_7100U_R1@

UC1

i3_7100U

SA0000A38H0 S IC FJ8067702739738 SR343 H0 2.4G BGA

U_i5_7200U_SR342@

UC1

U_SI_i5-7200U_SR342 H0 2.5G

SA0000A37H0

S IC FJ8067702739739 SR342 H0 2.5G BGA

U_i7_7500U_SR341@

UC1

U_SI_i7-7500U_SR341 H0 2.7G

SA0000A34F0

S IC FJ8067702739740 SR341 H0 2.7G BGA

R_i5_8250U_QNEF@

UC1

R_SI_i5_8250U_QNEF Y0 1.6G

SA0000AWB10

S IC FJ8067703282221 SR3LA Y0 1.6G FCBGA

R_i7_8550U_SR3LC@

UC1

R_SI_i7-8550U_SR3LC Y0 1.8G

SA0000AWC20

S IC FJ8067703281816 SR3LC Y0 1.8G FCBGA

+3V_PRIM

+3VS

R=10K

2N7002

+3V_PRIM

+3VALW

R=10K

2N7002

@

+3VS

R=2.2K

EC_SMB_CK2 EC_SMB_DA2

+3VS_DGPU_AON

PX@

2N7002

+3VS +3VS_DGPU_AON

2N7002

B

SOC SMBUS Address Table

SOC_SMBUS Net Name

SMBCLK SMBDATA

PCH_SMBCLK PCH_SMBDATA

TP_SMBCLK TP_SMBDAT

R=2.2K

I2CS_SCL I2CS_SDA

DGPU

Power Rail

+3V_PRIM

i3_7100U_R3@

UC1

i3_7100U

SA0000A38J0 S IC FJ8067702739738 SR343 H0 2.4G A32!

i5_7200U_R3@

i5_7200U

SA0000A37J0 S IC FJ8067702739739 SR342 H0 2.5G A32!

i7_7500U_R3@

UC1

i7_7500U

SA0000A34H0 S IC FJ8067702739740 SR341 H0 2.7G A32!

i5_8250U_R3@

UC1

i5_8250U

SA0000AWB30 S IC FJ8067703282221 SR3LA Y0 1.6G A32!

i7_8550U_R3@

UC1

i7_8550U

SA0000AWC30 S IC FJ8067703281816 SR3LC Y0 1.8G A32!

SO-DIMM A

SO-DIMM B

Touch Pad

Device

DIMM1

DIMM2

Touch PAD

C

Address (7 bit)

0x50 0xA0 0xA1

0x52 0xA4 0xA5

0x2C 0x590x58

MX110@

UV1

N16V-GMR1-S-A2

SA00009IT00

S IC N16V-GMR1-S-A2 BGA 595P

M2G_R3@ X7674032L06

H2G_R3@ X7674032L07

2G Samsung

S2G_R3@ X7674032L08

ZZZ

DAZ_R2G

DAZ_R2G@ DAZ23T00500

ZZZ

2G Micron

ZZZ

2G Hynix

ZZZ

2G MicronUC1

M2G_R1@ X7674032L01

ZZZ

2G Hynix

H2G_R1@ X7674032L04

ZZZ

2G Samsung

S2G_R1@ X7674032L05

DAX

KBLU-2G

KBLU_2G@

DA6001WM000

PCB 29M LA-G07AP REV0 MB 3

ZZZ

DAZ_U2G

DAZ_U2G@ DAZ23T00600

DAX

KBLU-UMA

KBLU_UMA@

DA6001YA000

PCB 29M LA-G07DP REV0 M/B 3

Address (8bit)

Read

Write

MX130@

UV1

N16S-GTR-S-A2

SA00009FP00

S IC N16S-GTR-S-A2 BGA 595P GPU

ZZZ

4G Micron

M4G_R1@ X7674032L26

ZZZ

4G Hynix

H4G_R1@ X7674032L25

ZZZ

4G Samsung

S4G_R1@ X7674032L27

DAX

KBLR-2G

KBLR_2G@

DA6001WI000

PCB 29L LA-G07CP REV0 MB 3

DAX

KBLR-UMA

KBLR_UMA@

DA6001YB000

PCB 29L LA-G07EP REV0 M/B 3

ZZZ

4G Micron

M4G_R3@ X7674032L29

ZZZ

4G Hynix

H4G_R3@ X7674032L28

ZZZ

4G Samsung

S4G_R3@ X7674032L30

DAX

KBLU-4G

KBLU_4G@ DA8001EH000

ZZZ

DAZ_U4G

DAZ_U4G@ DAZ23T00600

Part Number Description

RO0000002HM

RO0000003HM

DAX

KBLR-4G

KBLR_4G@ DA8001EI000

ZZZ

DAZ_R4G

DAZ_R4G@ DAZ23T00500

D

EC SMBUS Address Table

EC_SMBUS Port

SMBUS Port 1

SMBUS Port 2

Power State

STATE

S0 (Full ON)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

ROYALTY HDMI W/LOGO45@

HDMI W/Logo:RO0000002HM

ZZZ

EMC for EE

X4E@

X4EABB32L01

SMT EMC FOR EE AG07C EPK52

Power Rail Device Address (7 bit)

+3VL_EC

+3VS

SIGNAL

SLP_S3#

LOW HIGH

<PCI-E,SATA,USB3.0/CLK>

Lane#

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

(TBC)

BAT

CHGR 0x12

dGPU

Thermal Sensor

PCH

SLP_S4#

SLP_S5#

HIGH

LOWLOW

HIGH

<USB2.0 port>

USB2.0 port DESTINATION

1 2 3 4 5 6 7 8 9 10 X

PCI-E

SATA

USB3.0

1 2 3

1

2 3 4

5 6

7 8

10

1191b*

12

4 5 6

0 1a

2

0x16

0x90

+VALW

+V

ON ON ON ONHIGH HIGH HIGH

ONONON

OFF

ON

OFFLOW LOW LOW

USB3.0 Type-C USB2.0/USB3.0 USB2.0/USB3.0

HD/IR_1/IR_2 Camera

IR_2 Camera Card Reader

DESTINATION

USB3.0 Type-C USB3.0 Type-C USB2.0/USB3.0 USB2.0/USB3.0

GPU(DIS only) GPU(DIS only) GPU(DIS only) GPU(DIS only)

LAN

WLAN

HDD ODD CLK3

X X

NVMe x2

E

+VS Clock

OFF

BT

X X

X

SATA SSD

OFF

CLK

CLK0

CLK1 CLK2

CLK4

1

2

X X X X

3

X

X X

X

U9 U8

UK1:+3VALW_EC

4 4

EC

(+3VL)

EC_SMB_CK2 EC_SMB_DA2

79 80

EC_SMB_CK1

77

EC_SMB_DA1

78

A

+3V_SMBUS

R=2.2K

R=0

R=100

GSEN_I2DAT GSEN_I2CLK

Thermal Sensor :G753T11U

Address : 0x48

G-Sensor HP2DC

BAT

Charger

B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2016/12/15 2019/12/15

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Notes List

LA-G07DP(KBL-U_UMA_6L)

E

of

3 59Friday, January 05, 2018

of

3 59Friday, January 05, 2018

v0.3

B

C

D

E

UC1A

SKL-U

Rev_0.53

+1.0V_PRIM

2

RC11 51_0402_5%@

RC13 51_0402_5%@

RC15 51 +-1% 0402 SD000008H80

RC364 51_0402_5%@

+1.0V_PRIM

RC14 51_0402_5%@

RC31 1K_0402_5%@

4 4

A

RC365 51_0402_1%@

RC35 51_0402_1% SD000008H80

RC37 51_0402_5%@

RC366 0_0402_5%@

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

SOC_XDP_TMS

SOC_XDP_TDI

SOC_XDP_TDO

CPU_XDP_TCK0

XDP_PREQ#

XDP_ITP_PMODE

SOC_XDP_TRST#

CPU_XDP_TCK0

PCH_JTAG_TCK1

CFG3

XDP_PREQ# <11>

XDP_ITP_PMODE <16>

CFG3 <16>

B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2017/04/10 2019/12/15

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SKL-U(1/12)DDI,MSIC,XDP,EDP

LA-G07DP(KBL-U_UMA_6L)

E

5 59Friday, January 05, 2018

of

5 59Friday, January 05, 2018

of

v0.3

5

Interleaved Memory

4

3

2

1

Interleaved Memory

D

<Cocoa_1020>

D

PDG#543016, ODT: CPU side no connect, DRAM side connect to VDDQ(Memory down); FET+R(SO-DIMM)

UC1B

DDR_M0_D[0..15]<17>

DDR_M0_D0 DDR_M0_D1 DDR_M0_D2 DDR_M0_D3 DDR_M0_D4

SKL-U

DDR0_CKN[0] DDR0_CKP[0] DDR0_CKN[1] DDR0_CKP[1]

AU53 AT53 AU55 AT55

DDR_M0_CLK#0 DDR_M0_CLK0 DDR_M0_CLK#1 DDR_M0_CLK1

DDR_M0_CLK#0 <17>

DDR_M0_CLK0 <17>

DDR_M0_CLK#1 <17>

DDR_M0_CLK1 <17>

DDR_M0_CKE0 <17>

DDR_M1_D[0..15]<18>

DDR_M1_D0 DDR_M1_D1 DDR_M1_D2 DDR_M1_CLK0 DDR_M1_D3 DDR_M1_D4

UC1C

SKL-U

Rev_0.53Rev_0.53

DDR1_CKN[0] DDR1_CKN[1] DDR1_CKP[0] DDR1_CKP[1]

AN45 AN46 AP45 AP46

DDR_M1_CLK#0 DDR_M1_CLK#1

DDR_M1_CLK1

DDR_M1_CLK#0 <18>

DDR_M1_CLK#1 <18> DDR_M1_CLK0 <18> DDR_M1_CLK1 <18>

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2017/04/10 2019/12/15

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

SKL-U(2/12)DDRIII

LA-G07DP(KBL-U_UMA_6L)

Friday, January 05, 2018

1

v0.3

59

6

of

6

of

5

HOST_SPI_0_CLK

HOST_SPI_0_SO<35> HOST_SPI_0_SI<35>

D

HOST_SPI_0_CS2#<35>

HOST_SPI_0_SO HOST_SPI_0_SI HOST_SPI_0_SIO2 HOST_SPI_0_SIO3 HOST_SPI_0_CS0#

HOST_SPI_0_CS2#

AV2 AW3 AV3 AW2 AU4 AU3 AU2 AU1

UC1E

SPI0_CLK SPI0_MISO SPI0_MOSI SPI0_IO2 SPI0_IO3 SPI0_CS0# SPI0_CS1# SPI0_CS2#

SPI - TOUCH

4

SPI - FLASH

SKL-U

SMBUS, SMLINK

GPP_C0/SMBCLK

GPP_C1/SMBDATA

GPP_C2/SMBALERT#

GPP_C3/SML0CLK

GPP_C4/SML0DATA

GPP_C5/SML0ALERT#

GPP_C6/SML1CLK

GPP_C7/SML1DATA

GPP_B23/SML1ALERT#/PCHHOT#

3

Rev_0.53

R7 R8 R10

R9 W2 W1

W3 V3 AM7

SMBCLK SMBDATA SMBALERT#

SML0CLK SML0DATA SML0ALERT#

SML1CLK SML1DATA GPP_B23

1 2

RC902

0_0201_5%

@

T239TP@

SML1ALERT#

2

SML0ALERT# (Internal Pull Down): eSPI or LPC 0 = LPC is selected for EC --> For KB9022/9032 Use 1 = eSPI is selected for EC --> For KB9032 Only.

SMB

(Link to XDP, DDR, TP)

SML1

(Link to EC,DGPU, LAN, Thermal Sensor)

SML0ALERT#

SML1ALERT#

1

RC218 1K_0402_1%

2

RC903 150K_0402_1%@

1

D

+3V_PRIM

1

1 2

10P_0402_50V8J

@EMI@

EON SA000046400 S IC FL 64M EN25Q64-104HIP SOP 8P MXIC SA00006N100 S IC FL 64M MX25L6473EM2I-10G SOP 8P WINBOND SA000039A30 S IC FL 64M W25Q64FVSSIQ SOIC 8P SPI ROM Micron SA00005L100 S IC FL 64M N25Q064A13ESEC0F SO8W 8P

A A

5

4

QC7B

SB00001FF00CC9

L2N7002SDW1T1G 2N SC88-6

TP_SMBDATA <34>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/04/10 2019/12/15

Compal Secret Data

Deciphered Date

2

Follow 543016_SKL_U_Y_PDG_0_9

Compal Electronics, Inc.

Title

SKL-U(3/12)SPI,ESPI,SMB,LPC

Size Document Number Rev

Custom

LA-G07DP(KBL-U_UMA_6L)

Date: Sheet

1

v0.3

7 59Friday, January 05, 2018

v0.3

of

5

4

3

2

1

EMI request

B

CC183 22P 50V J NPO 0402

UC1I

CSI-2

SKL_ULT

Rev_0.53

PLAT_SEL0 PLAT_SEL1

PLAT_SEL1

Security Classification

2017/04/10 2019/12/15

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2017/04/10 2019/12/15

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

SKL-U(4/12)HDA,EMMC,SDIO,CSI2

Size Document Number Rev

Custom

LA-G07DP(KBL-U_UMA_6L)

Date: Sheet

Friday, January 05, 2018

Date: Sheet

Friday, January 05, 2018

Date: Sheet

2

Friday, January 05, 2018

KBLR@

KBLU@

2

RC919 10K_0402_5%

1

2

RC918 10K_0402_5%

1

SKYL@

KBLU@

8

2

RC916 10K_0402_5%

1

2

RC917

10K_0402_5%

1

KBLR@

RC917

10K_0402_5%

SD028100280

of

B

v0.3

59

D

+RTCVCC

PCH_RTCRST#

PCH_SRTCRST#

5

1 2

RC91 20K_0402_5%

1 2

CC10 1U_0402_6.3V6K

1 2

CLRP1 SHORT PADS

2

1

RC93 20K_0402_5%

1 2

CC11 1U_0402_6.3V6K

2

1

CLRP2 SHORT PADS

2

1

RC94 1M_0402_5%

2

1

R10880_0402_5%

2

1

R10890_0402_5%

JCMOS1

0_0603_5%

+3VS

PCH_SRTCRST#

CLR ME

PCH_RTCRST#

CLR CMOS

SM_INTRUDER#

CLR_CMOS# <33>

1

Clear CMOS close to RAM door

@

2

4

LAN

WLAN

PCIe SSD

3

UC1J

CLKREQ_PEG#0

CLK_PCIE_N1<29> CLK_PCIE_P1<29> CLKREQ_PCIE#1<29>

CLK_PCIE_N2<30> CLK_PCIE_P2<30> CLKREQ_PCIE#2<30>

CLK_PCIE_N4<31> CLK_PCIE_P4<31> CLKREQ_PCIE#4<31>

CLK_PCIE_N1 CLK_PCIE_P1 CLKREQ_PCIE#1

CLK_PCIE_N2 CLK_PCIE_P2 CLKREQ_PCIE#2

CLKREQ_PCIE#3

CLK_PCIE_N4 CLK_PCIE_P4 CLKREQ_PCIE#4

SKL_ULT

CLOCK SIGNALS

Rev_0.53

CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P

GPD8/SUSCLK

XTAL24_IN

XTAL24_OUT

XCLK_BIASREF

RTCX1 RTCX2

SRTCRST#

RTCRST#

F43 E43

BA17

E37 E35

E42

AM18 AM20

AN18

AM16

2

SUSCLK

PCH_KBLU24_IN PCH_KBLU24_OUT

XCLK_BIASREF

PCH_RTCX1 PCH_RTCX2

PCH_SRTCRST# PCH_RTCRST#

SUSCLK <30>

2

1

RC96 2.7K_0402_1%

+1.0V_CLK5_F24NS

1

D

CC16

6.8P 50V C NPO 0402

SE07168AC80

2

A A

From EC(open-drain)

EC_VCCST_PG_R<33,40>

+1.0V_VCCST

1

RC113 1K_0402_5%

2

RC116 60.4_0402_1%

5

2

1

EC_VCCST_PG

4

PCH_DPWROK<33>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

Rshort@

RC112 0_0402_5%

PCH_DPWROK_R

1

Compal Secret Data

2017/04/10 2019/12/15

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

SKL-U(5/12)CLK,GPIO

Size Document Number Rev

Custom

LA-G07DP(KBL-U_UMA_6L)

Date: Sheet

1

9 59Friday, January 05, 2018

of

9 59Friday, January 05, 2018

of

v0.3

5

4

3

2

1

12

GSPI0_MOSI (Internal Pull Down):

No Reboot

0 = Disable No Reboot mode. --> AAX05 Use

1 = Enable No Reboot Mode. (PCH will disable the TCO Timer system reboot feature). This function is useful when running ITP/XDP.

B

GSPI1_MOSI (Internal Pull Down):

Boot BIOS Strap Bit

0 = SPI Mode --> AAX05 Use

1 = LPC Mode

UC1F

LPSS ISH

SKL-U

Rev_0.53

<DB> Change Thermal Sensor IC

1

CC127

0.1U_0201_10V6K

2

+3VS

DGPU_PWR_EN

WL_OFF# SOC_GPIOB21

NMI_DBG#_CPU<5,33>

NMI_DBG#_CPU

DGPU_HOLD_RST#

ODD_PWR

ODD_DA#

1

RPC14

1 2 3

4

10K_0804_8P4R_5%

1

2

8 7

6 5

2

RC382 10K_0402_5%

RC923 10K_0402_5%@

RC929 10K_0402_5%

RC930 10K_0402_5%

+3V_PRIM

+3VS

B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2017/04/10 2019/12/15

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

SKL-U(6/12)GPIO

Size Document Number Rev

Custom

LA-G07DP(KBL-U_UMA_6L)

Date: Sheet

2

Date: Sheet

1

10 59Friday, January 05, 2018

v0.3

of

5

4

3

2

1

UC1H

PCIE/USB3/SATA

D

SKL-U

SSIC / USB3

Rev_0.53

USB3_CRX_DTX_N1 <38> USB3_CRX_DTX_P1 <38>

USB3_CTX_DRX_N1 <38> USB3_CTX_DRX_P1 <38>

USB3_CRX_DTX_N2 <38> USB3_CRX_DTX_P2 <38>

USB3_CTX_DRX_N2 <38> USB3_CTX_DRX_P2 <38>

USB2.0/USB3.0

D

M.2 SSD

+3VS

When PCIE8/SATA1A is used as SATA Port 1 (ODD), then PCIE11/SATA1B (M.2 SSD) cannot be used as SATA Port 1.

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

USB_OC2#

USB_OC3#

DEVSLP0

DEVSLP1

DEVSLP2

SATA_GP0

SATA_GP1

SATA_GP2

2017/04/10 2019/12/15

3

N/A

NGFF SSD KEY-

N/A

ODD_PLUG#

PCIE/SATA

Compal Secret Data

Deciphered Date

M

Custom

Date: Sheet

2

Date: Sheet

SATA_LED# SATA_GP0 SSD1_IF ODD_PLUG#

USB_OC1# USB_OC3# USB_OC0# USB_OC2#

Compal Electronics, Inc.

Title

SKL-U(7/12)PCIE,USB,SATA

Size Document Number Rev

LA-G07DP(KBL-U_UMA_6L)

RPC13

8

1

7

2

6

3

5

4

10K_0804_8P4R_5%

RPC20

1 8 2 7 3 6 4 5

10K_0804_8P4R_5%

1

11 59Friday, January 05, 2018

+3V_PRIM

of

v0.3

5

4

3

2

1

+1.0V_PRIM TO +1.0V_VCCSTU

+1.2V_VDDQ

I (Max) : 4.5 A

+1.2V_VDDQ

+1.0V_VCCST

+1.0V_PRIM

+1.2V_VCCSFR_OC

+1.0V_VCCSFR

<Cocoa_1113> Per 543977_SKL_PDDG_Rev0_91, change CC95 value from 1000pf to 10pf for meet <= 65us timing for

C

+1.0V_VCCSTU power rail.

+1.0V_VCCSTU +1.0V_VCCST

1

RC140 0_0402_5%

AU23 AU28 AU35 AU42 BB23 BB32 BB41

BB47 BB51

AM40

AL23

A18

A22

K20 K21

2

UC1N

VDDQ_AU23 VDDQ_AU28 VDDQ_AU35 VDDQ_AU42 VDDQ_BB23 VDDQ_BB32 VDDQ_BB41

VDDQ_BB47 VDDQ_BB51

VDDQC

VCCST

VCCSTG_A22

VCCPLL_OC

VCCPLL_K20 VCCPLL_K21

SKL-U_BGA1356

+1.0V_PRIM TO +1.0VS_VCCSTG / +1.0VS_VCCIO

+5VALW

+1.0V_PRIM

near pin A22

CPU POWER 3 OF 4

PSC Side

1U_0402_6.3V6K

1

2

SKL-U

CC48

Rev_0.53

+1.0V_PRIM

C

RC208 Follow 544669_SKL_U__DDR3L_RVP7_Schematic_Rev1.0

+1.0V_VCCSFR

2

1

RC143 0_0402_5%

1U_0402_6.3V6K

1

CC55

2

+1.2V_VDDQ

1

CC27

2

A A

1

CC28

2

5

10U_0402_6.3V6M

1

1U_0201_6.3V6K

1

CC29

2

1U_0201_6.3V6K

1

CC30

1

CC31

2

1U_0402_6.3V6K

1U_0201_6.3V6K

1

CC32

2

1U_0402_6.3V6K

1

CC33

1

CC34

2

4

1U_0402_6.3V6K

1

CC36

CC35

CC47 Follow 543016_SKL_U_Y_PDG_0_9

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

1U_0402_6.3V6K

1

CC47

2

Compal Secret Data

2017/04/10 2019/12/15

Compal Secret Data

Deciphered Date

10U_0603_6.3V6M

1

CC37

2

10U_0603_6.3V6M

1

CC38

2

+1.35V_VDDQ_CPU : 10UF/6.3V/0603 *6 1UF/6.3V/0402 * 4

2

10U_0603_6.3V6M

1

CC39

1

CC40

2

10U_0603_6.3V6M

1

CC42

CC41

2

Title

Size Document Number Rev

Custom

Date: Sheet

BSC SidePSC Side

1U_0402_6.3V6K

1

CC43

2

Compal Electronics, Inc.

SKL-U(8/12)Power

LA-G07DP(KBL-U_UMA_6L)

+1.0V_PRIM

BSC SidePSC Side

1U_0402_6.3V6K

1

CC56

2

1U_0402_6.3V6K

CC44

1

2

CC46

CC45

2

v0.3

12 59Friday, January 05, 2018

of

12 59Friday, January 05, 2018

1

of

+1.0V_PRIM

1 2

RC148 0_0603_5%Rshort@

D

Follow 543016_SKL_U_Y_PDG_1_0

1

RC152 0_0603_5%Rshort@

2

5

+1.0V_APLL

22U_0603_6.3V6M

CC142

1

@

2

+1.0V_CLK5_F24NS

4

+3V_PRIM

1 2

1

2

+3V_PRIM

RC197 0_0402_5%Rshort@

RC150 0_0402_5%Rshort@

1U_0402_6.3V6K

CC72

1

2

22U_0603_6.3V6M

CC134

1

2

+3V_HDA

+3V_PGPPA

1

CC63 1U_0201_6.3V6K

2

near pin K15,L15

3

22U_0603_6.3V6M

1

2

near pin N18

CC147

@

+1.0V_PRIM

22U_0603_6.3V6M

CC148

1

@

2

+1.0V_PRIM

2

+1.0V_PRIM

1U_0201_6.3V6K

1

1U_0402_6.3V6K

CC61

1

2

+1.0VO_DSW

1U_0402_6.3V6K

CC68

1

2

1

2

1U_0201_6.3V6K

CC85

+1.0V_PRIM

+1.0V_MPHYAON

+1.0V_PRIM

CC91

2

2.574A

1.87A

0.69A

AB19 AB20

P18

AF18 AF19

V20 V21

AL1

K17

N15

N16 N17 P15 P16

L1

UC1O

VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0

VCCPRIM_CORE VCCPRIM_CORE VCCPRIM_CORE VCCPRIM_CORE

DCPDSW_1P0

VCCMPHYAON_1P0 VCCMPHYAON_1P0

VCCMPHYGT_1P0_N15

VCCMPHYGT_1P0_N16 VCCMPHYGT_1P0_N17 VCCMPHYGT_1P0_P15 VCCMPHYGT_1P0_P16

CPU POWER 4 OF 4

SKL-U

Rev_0.53

VCCPGPPA VCCPGPPB VCCPGPPC VCCPGPPD

VCCPGPPE VCCPGPPF VCCPGPPG

VCCPRIM_3P3_V19

VCCPRIM_1P0_T1

VCCATS_1P8

VCCRTCPRIM_3P3

VCCRTC_AK19 VCCRTC_BB14

DCPRTC

AK15 AG15 Y16 Y15

T16 AF16 AD15

V19

T1

AA1

AK17

AK19 BB14

BB10

1

1209_follow G group GPIO powe rail to +3V_PRIM

+3V_PGPPA +3V_PGPPB +3V_PGPPC +3V_1.8V_PGPPD +3V_PGPPE +1.8V_PRIM +3V_PRIM

+3V_PRIM

+1.0V_DTS

+1.8V_PRIM

+3V_PRIM_RTC

+RTCVCC

2

1

+DCPRTC

CC71 0.1U_0201_10V6K

+1.0V_CLK6_24TBT

+1.0V_APLL

+1.0V_CLK4_F100OC

+1.0V_CLK5_F24NS

+1.0V_CLK6_24TBT

PRIMCORE_VID0 PRIMCORE_VID1

From Battery

+3V_LID

T130 TP@

T131 TP@

For SD CARD

D

1U_0402_6.3V6K

2

1

2

+3V_PRIM_RTC

1U_0402_6.3V6K

1

2

4

CC74

CC78

1

CC77

2

+3VS_PGPPA

+3VALW_DSW

BOM

BOMBOM

I (Max) : 0.1 A

0.1U_0201_10V6K

+1.2V_VCCSFR_OC

+1.2V_VDDQ

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

CC150

1U_0402_6.3V6K

1

2

RC141 0_0402_5%

2017/04/10 2019/12/15

2

1

Compal Secret Data

CC49

1

2

Deciphered Date

2

0.1U_0201_10V6K

+3VALW TO +3V_PRIM

I (Max) : 0.46 A(+3V_PRIM) RDS(Typ) : 65 mohm V drop : 0.03 V

+3VALW

1

@

CC50

1U_0402_6.3V6K

2

Compal Electronics, Inc.

Title

SKL-U(9/12)Power

Size Document Number Rev

Custom

LA-G07DP(KBL-U_UMA_6L)

Date: Sheet

2

RC393 0_0805_5%

1

+3V_PRIM

13 59Friday, January 05, 2018

0.1U_0201_10V6K

CC51

1

2

v0.3

of

RC169 0_0603_5%Rshort@

1

RC162 0_0402_5%Rshort@

2

1U_0402_6.3V6K

1

@

CC86

2

+1.0V_DTS

10U_0402_6.3V6M

22U_0603_6.3V6M

1

@

CC75

CC139

CC138

2

1

RC171 0_0402_5%Rshort@

2

1

Follow 543016_SKL_U_Y_PDG_0_9

+1.0V_PRIM +3V_PRIM +1.8V_PRIM

22U_0603_6.3V6M

A A

22U_0603_6.3V6M

CC112

CC111

1

@

2

22U_0603_6.3V6M

CC114

CC113

1

@

2

5

22U_0402_6.3V6M

CC115

CC116

1

@

2

+3VS

1

RC178 0_0402_5%Rshort@

+3VALW

1

RC173 0_0603_5%Rshort@

Follow 543016_SKL_U_Y_PDG_0_9

5

UC1L

D

SKL-U

CPU POWER 1 OF 4

Rev_0.53

4

JU42A

+VCC_CORE

+VCC_GT

JU42A/JU42B for KBLR JU221 for KBLU

112

JUMP_43X39_0805

JU22

1

2

1

JUMP_43X39_0805

2

JUMP@

2

JUMP@

+VCC_GT_VR

3

+VCC_GT

UC1M

CPU POWER 2 OF 4

SKL-U

Rev_0.53

2

+VCC_GT+VCC_CORE +VCC_CORE

1

D

C

SVID ALERT

SOC_SVID_ALERT#

1

RC180 220_0402_5%

SVID DATA

B

A A

+1.0V_VCCST

Place the PU resistors close to CPU

1

RC179 56_0402_5%

2

+1.0V_VCCST

Place the PU resistors close to CPU

1

RC181 100_0402_1%

2

VR_ALERT# <52>

VR_SVID_DATA <52>

(To VR)

VCCGT_SENSE<52> VSSGT_SENSE<52>

Trace Length < 25 mils

VCCGT_SENSE VSSGT_SENSE

SKL-U_BGA1356

13 OF 20

VCCGTX_SENSE VSSGTX_SENSE

T155 TP@ T219 TP@

C

B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2017/04/10 2019/12/15

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

SKL-U(10/12)Power,SVID

Size Document Number Rev

Custom

LA-G07DP(KBL-U_UMA_6L)

Date: Sheet

Date: Sheet of

2

14 59Friday, January 05, 2018

v0.3

of

1

5

4

3

2

1

D

A5 A67 A70 AA2 AA4

AA65 AA68 AB15

AB16 AB18 AB21

AB8

AD13 AD16 AD19 AD20 AD21 AD62

AD8

AE64 AE65 AE66 AE67

C

B

AE68 AE69

AF1

AF10 AF15 AF17

AF2 AF4

AF63 AG16 AG17 AG18

AG19 AG20 AG21 AG71

AH13

AH6 AH63 AH64 AH67 AJ15 AJ18 AJ20

AK11 AK16 AK18 AK21 AK22

AK27 AK63 AK68 AK69

AK8

AL2 AL28 AL32 AL35

AL38

AL4 AL45 AL48 AL52 AL55 AL58 AL64

AJ4

UC1P

GND 1 OF 3

VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS

SKL-U_BGA1356

SKL-U

Rev_0.53 Rev_0.53

AT63 AT68 AT71 AU10 AU15 AU20 AU32 AU38

AV1 AV68 AV69 AV70 AV71

AW10 AW12 AW14 AW16 AW18 AW21 AW23 AW26 AW28 AW30 AW32 AW34 AW36 AW38 AW41

AW43 AW45 AW47 AW49 AW51 AW53 AW55 AW57

AW6 AW60 AW62 AW64 AW66

AW8

AY66

B10 B14 B18 B22 B30 B34 B39 B44

B48 B53 B58 B62 B66 B71

BA1 BA10 BA14 BA18

BA2 BA23 BA28 BA32 BA36

F68

BA45

16 OF 20

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AL65 AL66 AM13 AM21 AM25 AM27 AM43 AM45 AM46 AM55

AM60 AM61 AM68 AM71 AM8 AN20 AN23 AN28 AN30 AN32 AN33 AN35 AN37 AN38 AN40 AN42 AN58 AN63

AP10 AP18 AP20 AP23 AP28 AP32 AP35 AP38 AP42

AP58 AP63 AP68 AP70 AR11 AR15 AR16 AR20 AR23 AR28 AR35 AR42 AR43 AR45 AR46 AR48 AR5 AR50

AR52 AR53 AR55 AR58 AR63 AR8 AT2 AT20 AT23 AT28 AT35 AT4 AT42 AT56 AT58

UC1Q

GND 2 OF 3

VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS

SKL-U_BGA1356

SKL-U

17 OF 20

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS

BA49 BA53 BA57 BA6 BA62 BA66 BA71 BB18 BB26 BB30 BB34 BB38 BB43 BB55 BB6 BB60 BB64 BB67 BB70 C1 C25 C5 D10 D11 D14 D18 D22 D25 D26 D30 D34 D39 D44 D45

D47 D48 D53 D58 D6 D62 D66 D69 E11 E15 E18 E21 E46 E50 E53 E56 E6 E65

E71 F1 F13 F2 F22 F23 F27 F28 F32 F33 F35 F37 F38 F4 F40 F42

BA41

G10 G22 G43 G45 G48

G52 G55 G58

G60 G63 G66 H15 H18 H71

K16 K18 K22 K61 K63 K64 K65 K66 K67 K68 K70 K71

F8

G5

G6

J11 J13 J25 J28 J32 J35 J38 J42

J8

L11 L16 L17

UC1R

GND 3 OF 3

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

SKL-U_BGA1356

SKL-U

18 OF 20

Rev_0.53

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

L18 L2 L20 L4 L8 N10 N13 N19 N21 N6 N65 N68 P17 P19 P20 P21 R13 R6 T15 T17 T18 T2 T21 T4 U10 U63 U64 U66 U67 U69 U70 V16 V17 V18 W13 W6 W9 Y17 Y19 Y20 Y21

D

C

B

A A

Security Classification

2017/04/10 2019/12/15

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2017/04/10 2019/12/15

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

SKL-U(11/12)GND

LA-G07DP(KBL-U_UMA_6L)

1

v0.3

15 59Friday, January 05, 2018

of

15 59Friday, January 05, 2018

of

15 59Friday, January 05, 2018

5

4

3

2

1

D

UC1S

E68

CFG[0]

B67

CFG[1]

D65

CFG[2]

CFG3<5>

CFG4

G69

D67 E70 C68 D68 C67 F71

CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9]

RESERVED SIGNALS-1

SKL-U

Rev_0.53

RSVD_TP_BB68

RSVD_TP_BB69

RSVD_TP_AK13 RSVD_TP_AK12

RSVD_BB2 RSVD_BA3

BB68

BB69

AK13 AK12

BB2 BA3

T158 TP@

T159 TP@

T162 TP@

D

<DB> Add ball E3/C7 for KBL U/R Colay

UC1T

AW69

RSVD_AW69

AW68

RSVD_AW68

AU56

RSVD_AU56

AW48

2

RSVD_AW48

C7

RSVD_C7

U12

RSVD_U12

U11

RSVD_U11

H11

RSVD_H11

SKL-U_BGA1356

PCH_KBLR24_IN

1

PCH_KBLR24_OUT

RX4 33_0402_1%KBLR@

2

J71

RSVD_J71

J68

B

SI 1/15

RSVD_J68

F65

VSS_F65

G65

VSS_G65

F61

RSVD_F61

E61

RSVD_E61

SKL-U_BGA1356

19 OF 20

RSVD_TP_AW71 RSVD_TP_AW70

PROC_SELECT#

VSS_AY71

ZVM#

MSM#

AY71

AR56

AW71 AW70

AP56

C64

Follow 544669_SKL_U_DDR3L_RVP7_schematic_rev1.0

1

PM_ZVM#

PM_MSM# SKL_CNL#

RC183 0_0402_5%

T225 TP@

T230 TP@

RC184 100K_0402_5%

For 2+3e Solution PM_ZVM#

+1.0V_VCCST

2

1

@

PM_MSM#

SKL-U

SPARE

Rev_0.53

RSVD_F6

RSVD_E3 RSVD_C11 RSVD_B11 RSVD_A11 RSVD_D12 RSVD_C12 RSVD_F52

20 OF 20

1

2

RX3 33_0402_1%KBLR@

PCH_XTAL24R_OUT

KBLR@

CC168

24MHz Part:

24MHz Part:24MHz Part: Main:SJ10000X700, S CRYSTAL 24MHZ 18PF +-20PPM

Main:SJ10000X700, S CRYSTAL 24MHZ 18PF +-20PPM

Main:SJ10000X700, S CRYSTAL 24MHZ 18PF +-20PPMMain:SJ10000X700, S CRYSTAL 24MHZ 18PF +-20PPM 8Y24000033(TXC)

8Y24000033(TXC)

8Y24000033(TXC)8Y24000033(TXC) 2nd: SJ10000TK00, S CRYSTAL 24MHZ 18PF +-20PPM

2nd: SJ10000TK00, S CRYSTAL 24MHZ 18PF +-20PPM

2nd: SJ10000TK00, S CRYSTAL 24MHZ 18PF +-20PPM2nd: SJ10000TK00, S CRYSTAL 24MHZ 18PF +-20PPM 7M24000027(TXC)

7M24000027(TXC)

7M24000027(TXC)7M24000027(TXC)

1

RC915 1M_0402_5%

KBLR@

YC3

24MHZ 18PF XRCGB24M000F2P51R0

3

27P_0402_50V8J

F6 E3 C11 B11 A11 D12 C12 F52

KBLR@

NC

4

PCH_KBLR24_IN

PCH_XTAL24R_IN

2

SJ10000UJ00

1

NC

2

1

27P_0402_50V8J

KBLR@

CC169

B

CFG_RCOMP

CFG4

A A

1 2

RC185 49.9_0402_1%

2

1

RC193 1K_0402_1%

Display Port Presence Strap

CFG4

1 : Disabled; No Physical Display Port attached to Embedded Display Port

0 : Enabled; An external Display Port device is connected to the Embedded Display Port

5

Security Classification

2017/04/10 2019/12/15

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2017/04/10 2019/12/15

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

SKL-U(12/12)RSVD

LA-G07DP(KBL-U_UMA_6L)

1

v0.3

16 59Friday, January 05, 2018

of

16 59Friday, January 05, 2018

of

5

4

3

2

1

CHANNEL-A

TOP: JDIMM1 CONN Non-ECC DIMM

D

+3VS

12

PLACE ALL THE BELOW RESISTORS CLOSE TO SODIMM

C

Layout Note: Place near JDIMM1.257,259

+2.5V

10U 6.3V M X5R 0603 H0.8

10U_0603_6.3V6M

1

CD3

2

Layout Note: PLACE THE CAP near JDIMM1. 164

B

+0.6V_DDR_VREFCA

2

CD11

0.1U_0201_10V6K

1

10uF*2 1uF*2

@ESD@

0.1U_0201_10V6K

1U_0402_6.3V6K

1

CD4

CD5

2

1

CD6

2

CD12

2.2U_0402_6.3V6M

1

CC159

1

2

2.2uF*1

0.1uF*1

+3VS

Layout Note: Place near JDIMM1.258

+0.6V_0.6VS

10U_0603_6.3V6M

1

CD7

2

+3V_PRIM

RD32 0_0402_5%

REVERSE TYPE

JDIMM1A

DDR_M0_CLK0<6> DDR_M0_CLK#0<6> DDR_M0_CLK1<6>

Interleaved Memory

DDR_M0_D[0..15]<6>

DDR_M0_D[16..31]<6>

DDR_M0_D[32..47]<6>

DDR_M0_D[48..63]<6>

+3V_PRIM_DA

0.1U_0201_10V6K

2.2U_0402_6.3V6M

CD1

+0.6V_DDR_VREFCA

2

CD2

1

10uF*2 1uF*1

1U_0402_6.3V6K

10U_0603_6.3V6M

1

CD9

CD8

2

+3V_PRIM_DA

2

1

FOX_AS0A827-H2RB-7H

CONN@

Part Number:LTCX0069GA0 Part Value:S SOCKET FOX AS0A827-H2RB-7H 260P DDR4

+0.6V_0.6VS

+2.5V

9/8 Modify

+1.2V_VDDQ

DDR_DRAMRST#_R

PLACE NEAR TO SODIMM

DDR_M0_CLK#1<6>

DDR_M0_CKE0<6> DDR_M0_CKE1<6>

DDR_M0_CS#0<6> DDR_M0_CS#1<6>

DDR_M0_ODT0<6>

DDR_M0_MA5<6> DDR_M0_MA6<6> DDR_M0_MA7<6> DDR_M0_MA8<6> DDR_M0_MA9<6>

DDR_M0_MA10<6> DDR_M0_MA11<6> DDR_M0_MA12<6>

DDR_M0_MA13<6>

DDR_M0_MA14_WE#<6> DDR_M0_MA15_CAS#<6> DDR_M0_MA16_RAS#<6>

DDR_DRAMRST#_R<6,18>

1

2

+1.2V_VDDQ

PCH_SMBDATA<7,18> PCH_SMBCLK<7,18>

@ESD@

CD10

0.1U_0402_25V6

DDR_M0_CLK0 DDR_M0_CLK#0 DDR_M0_CLK1 DDR_M0_CLK#1

DDR_M0_CKE0 DDR_M0_CKE1

DDR_M0_CS#0 DDR_M0_CS#1

DDR_M0_ODT0

DDR_M0_MA6 DDR_M0_MA7

DDR_M0_MA8 DDR_M0_MA9

DDR_M0_MA10 DDR_M0_MA11 DDR_M0_MA12 DDR_M0_MA13 DDR_M0_MA14_WE# DDR_M0_MA15_CAS# DDR_M0_MA16_RAS#

PCH_SMBDATA PCH_SMBCLK

SA2_CHA_DIM1 SA1_CHA_DIM1 SA0_CHA_DIM1

For ECC DIMM

+1.2V_VDDQ

137 139 138 140

109 110

149 157

162

165

146

120 119 158 151 156 152

254

253

166 260 256

101 105

100

104

178 199 220

241

CK0(T) CK0#(C) CK1(T) CK1#(C)

CKE0 CKE1

S0# S1#

S2#/C0

S3#/C1

A10_AP

A11 A12 A13 A14_WE# A15_CAS# A16_RAS#

SDA

SCL

SA2 SA1 SA0

92

CB0_NC

91

CB1_NC CB2_NC CB3_NC

88

CB4_NC

87

CB5_NC CB6_NC

CB7_NC

97

DQS8(T)

95

DQS8#(C)

12

DM0#/DBI0#

33

DM1#/DBI1#

54

DM2#/DBI2#

75

DM3#/DBI3# DM4#/DBI4# DM5#/DBI5# DM6#/DBI6#

DM7#/DBI7#

96

DM8#/DBI8#

FOX_AS0A827-H2RB-7H

CONN@

STD

DQS0(T)

DQS0#(C)

DQ20 DQ21 DQ22 DQ23

DQS2(T)

DQS2#(C)

DQ32 DQ33 DQ34 DQ35 DQ36 DQ37

DQ38 DQ39

DQS4(T)

DQS4#(C)

DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47

DQS5(T)

DQS5#(C)

DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55

DQS6(T)

DQS6#(C)

DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62

DQ63

DQS7(T)

DQS7#(C)

DQ0 DQ1

DQ2 DQ3

DQ4 DQ5 DQ6

DQ7

DQ8 DQ9

8 7

20 21

4 3 16

17 13 11

28 29

46 45 58 59

55 53

174 173 187 186 170 169

183 182

179 177

195 194 207 208 191 190 203 204

200 198

216 215 228 229 211 212 224 225

221 219

237 236 249 250 232 233 245

246 242 240

DDR_M0_D0 DDR_M0_D4 DDR_M0_D3 DDR_M0_D7 DDR_M0_D1 DDR_M0_D5 DDR_M0_D2 DDR_M0_D6 DDR_M0_DQS0 DDR_M0_DQS#0

DDR_M0_D8 DDR_M0_D12

DDR_M0_D14

DDR_M0_D16 DDR_M0_D20 DDR_M0_D19 DDR_M0_D22

DDR_M0_DQS2 DDR_M0_DQS#2

DDR_M0_D25

DDR_M0_D28

DDR_M0_D30 DDR_M0_D31 DDR_M0_D24

DDR_M0_D29

DDR_M0_D32 DDR_M0_D37 DDR_M0_D34 DDR_M0_D39 DDR_M0_D36 DDR_M0_D33 DDR_M0_D35 DDR_M0_D38 DDR_M0_DQS4 DDR_M0_DQS#4

DDR_M0_D44 DDR_M0_D45 DDR_M0_D42 DDR_M0_D43 DDR_M0_D41 DDR_M0_D40 DDR_M0_D46 DDR_M0_D47 DDR_M0_DQS5 DDR_M0_DQS#5

DDR_M0_D53 DDR_M0_D48 DDR_M0_D54 DDR_M0_D50 DDR_M0_D52 DDR_M0_D49 DDR_M0_D55 DDR_M0_D51 DDR_M0_DQS6 DDR_M0_DQS#6

DDR_M0_D60 DDR_M0_D57 DDR_M0_D59 DDR_M0_D62 DDR_M0_D56 DDR_M0_D61 DDR_M0_D58 DDR_M0_D63 DDR_M0_DQS7 DDR_M0_DQS#7

DDR_M0_DQS0 <6>

DDR_M0_DQS#0 <6>

DDR_M0_DQS2 <6>

DDR_M0_DQS#2 <6>

DDR_M0_DQS4 <6>

DDR_M0_DQS#4 <6>

DDR_M0_DQS5 <6>

DDR_M0_DQS#5 <6>

DDR_M0_DQS6 <6>

DDR_M0_DQS#6 <6>

DDR_M0_DQS7 <6>

DDR_M0_DQS#7 <6>

D

C

B

DIMM Side

+0.6V_DDR_VREFCA

Layout Note: Place near JDIMM1

10uF*6

+1.2V_VDDQ

10U_0603_6.3V6M

CD93

1

A A

1

2

10U_0603_6.3V6M

CD16

CD17

1

2

1uF*8 330uF*1

10U_0603_6.3V6M

CD18

CD19

1

2

5

10U_0603_6.3V6M

CD21

CD20

CD22

1

2

@

+1.2V_VDDQ

10U_0603_6.3V6M

1U_0402_6.3V6K

CD95

CD23

1

2

1U_0402_6.3V6K

1

CD96

2

1U_0402_6.3V6K

1

CD24

2

1U_0402_6.3V6K

1

CD25

CD26

2

4

1U_0402_6.3V6K

1

CD27

CD28

2

1U_0402_6.3V6K

1

CD30

CD29

2

1U_0402_6.3V6K

1

CD31

CD94

2

C174

330U_2.5V_M

1

+

Part Number = SF000006S00

2

@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

RD8 1K_0402_1%

Compal Secret Data

2017/04/10 2019/12/15

Compal Secret Data

Deciphered Date

CPU Side

2

+0.6V_VREFCA

RD11

24.9_0402_1%

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

P18-DDRIV_CHA: DIMM0

LA-G07DP(KBL-U_UMA_6L)

1

17 59Friday, January 05, 2018

of

v0.3

5

4

3

2

1

CHANNEL-B

TOP: JDIMM2 CONN

D

PLACE ALL THE BELOW RESISTORS CLOSE TO SODIMM

SPD ADDRESS FOR CHANNEL B : WRITE ADDRESS: 0XA4 READ ADDRESS: 0XA3 SA0 = 0; SA1 = 1; SA2 = 0. DDR4 POR OPERATING SPEED: 1867 MT/S STRETCH GOAL IS 2133 MT/S

C

12

RD19

0_0402_5%

@

1

RD22 0_0402_5%

2

Layout Note: Place near JDIMM2.257,259

+2.5V

10U_0603_6.3V6M

1

CD62

2

10uF*2 1uF*2

10U_0603_6.3V6M

1U_0402_6.3V6K

1

CD63

CD64

CD65

2

Non-ECC DIMM

1

RD20 0_0402_5%

2

1

RD23

@

0_0402_5%

2

+3VS+3VS+3VS

12

RD21

@

0_0402_5%

SA2_CHB_DIM2SA1_CHB_DIM2SA0_CHB_DIM2

1

RD24 0_0402_5%

2

Layout Note: Place near JDIMM2.258

+0.6V_0.6VS

10U_0603_6.3V6M

1

2

STD

2

RD25 240_0402_1%

DDR_M1_CLK0<6> DDR_M1_CLK#0<6>

DDR_M1_CLK#1<6>

DDR_M1_CKE0<6> DDR_M1_CKE1<6>

DDR_M1_CS#0<6>

DDR_M1_CS#1<6>

DDR_M1_ODT0<6> DDR_M1_ODT1<6>

DDR_M1_BG0<6> DDR_M1_BG1<6> DDR_M1_BA0<6> DDR_M1_BA1<6>

DDR_M1_MA0<6> DDR_M1_MA1<6> DDR_M1_MA2<6> DDR_M1_MA3<6> DDR_M1_MA4<6> DDR_M1_MA5<6>

DDR_M1_MA6<6> DDR_M1_MA7<6> DDR_M1_MA8<6>

DDR_M1_MA9<6>

DDR_M1_MA10<6> DDR_M1_MA11<6> DDR_M1_MA12<6> DDR_M1_MA13<6>

DDR_M1_MA14_WE#<6> DDR_M1_MA15_CAS#<6> DDR_M1_MA16_RAS#<6>

DDR_M1_ACT#<6>

DDR_M1_PAR<6> DDR_M1_ALERT#<6>

1

DDR_DRAMRST#_R<6,17>

PCH_SMBDATA<7,17> PCH_SMBCLK<7,17>

DIMM2_CHB_EVENT# DDR_DRAMRST#_R

Interleaved Memory

+3V_PRIM_DB

CD60

0.1U_0201_10V6K

DDR_M1_D[0..15]<6> DDR_M1_CLK1<6>

DDR_M1_D[16..31]<6>

DDR_M1_D[32..47]<6>

1

2

DDR_M1_D[48..63]<6>

+1.2V_VDDQ

2.2U_0402_6.3V6M

+0.6V_DDRB_VREFCA

2

CD61

1

JDIMM2B

STD

+1.2V_VDDQ

+0.6V_0.6VS

+2.5V

PLACE NEAR TO PIN

9/8 Modify

+1.2V_VDDQ

10uF*2 1uF*1

10U_0603_6.3V6M

1U_0402_6.3V6K

1

CD66

CD67

CD68

2

(5.2 mm)

DDR_M1_CLK0 DDR_M1_CLK#0 DDR_M1_CLK1 DDR_M1_CLK#1

DDR_M1_CKE0 DDR_M1_CKE1

DDR_M1_CS#0 DDR_M1_CS#1

DDR_M1_ODT0 DDR_M1_ODT1

DDR_M1_BG0 DDR_M1_BG1 DDR_M1_BA0 DDR_M1_BA1

DDR_M1_MA0 DDR_M1_MA1 DDR_M1_MA2 DDR_M1_MA3 DDR_M1_MA4 DDR_M1_MA5 DDR_M1_MA6 DDR_M1_MA7 DDR_M1_MA8 DDR_M1_MA9 DDR_M1_MA10 DDR_M1_MA11 DDR_M1_MA12 DDR_M1_MA13 DDR_M1_MA14_WE# DDR_M1_MA15_CAS# DDR_M1_MA16_RAS#

DDR_M1_ACT#

DDR_M1_PAR DDR_M1_ALERT#

PCH_SMBDATA PCH_SMBCLK

SA2_CHB_DIM2 SA1_CHB_DIM2 SA0_CHB_DIM2

JDIMM2A

137

CK0(T)

139

CK0#(C)

138

CK1(T)

140

CK1#(C)

109

CKE0

110

CKE1

149

S0#

157

S1#

162

S2#/C0

165

S3#/C1

155

ODT0

161

ODT1

115

BG0

113

BG1

150

BA0

145

BA1

144

A0

133

A1

132

A2

131

A3

128

A4

126

A5

127

A6

122

A7

125

A8

121

A9

146

A10_AP

120

A11

119

A12

158

A13

151

A14_WE#

156

A15_CAS#

152

A16_RAS#

114

ACT#

143

PARITY

116

ALERT#

134

EVENT#

108

RESET#

254

SDA

253

SCL

166

SA2

260

SA1

256

SA0

STD

DQ0 DQ1 DQ2

DQ3 DQ4

DQ5 DQ6 DQ7

DQS0(T)

DQS0#(C)

DQ8 DQ9

DQ10 DQ11 DQ12 DQ13 DQ14 DQ15

DQS1(T)

DQS1#(C)

DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23

DQS2(T)

DQS2#(C)

DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

DQS3(T)

DQS3#(C)

DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39

DQS4(T)

DQS4#(C)

8

7

20

21

4

3

16

17

13

11

28

29

41

42

24

25

38

37

34

32

50

49

62

63

46

45

58

59

55

53

70

71

83

84

66

67

79

80

76

74

174

173

187

186

170

169

183

182

179

177

DDR_M1_D15 DDR_M1_D10 DDR_M1_D11 DDR_M1_D12 DDR_M1_D14 DDR_M1_D9 DDR_M1_D8 DDR_M1_D13 DDR_M1_DQS1 DDR_M1_DQS#1

DDR_M1_D0 DDR_M1_D5 DDR_M1_D7 DDR_M1_D6 DDR_M1_D4 DDR_M1_D1 DDR_M1_D3 DDR_M1_D2 DDR_M1_DQS0 DDR_M1_DQS#0

DDR_M1_D20 DDR_M1_D17 DDR_M1_D19 DDR_M1_D22 DDR_M1_D21 DDR_M1_D16 DDR_M1_D18 DDR_M1_D23 DDR_M1_DQS2 DDR_M1_DQS#2

DDR_M1_D25 DDR_M1_D24 DDR_M1_D31 DDR_M1_D27 DDR_M1_D28 DDR_M1_D29 DDR_M1_D30 DDR_M1_D26 DDR_M1_DQS3 DDR_M1_DQS#3

DDR_M1_D37 DDR_M1_D33 DDR_M1_D35 DDR_M1_D38 DDR_M1_D32 DDR_M1_D36 DDR_M1_D34 DDR_M1_D39 DDR_M1_DQS4 DDR_M1_DQS#4

DDR_M1_D44

DDR_M1_DQS1 <6>

DDR_M1_DQS#1 <6>

DDR_M1_DQS0 <6>

DDR_M1_DQS#0 <6>

DDR_M1_DQS2 <6>

DDR_M1_DQS#2 <6>

DDR_M1_DQS3 <6>

DDR_M1_DQS#3 <6>

DDR_M1_DQS4 <6>

DDR_M1_DQS#4 <6>

D

C

Layout Note: PLACE THE CAP WITHIN 200 MILS FROM THE JDIMM2

+0.6V_DDRB_VREFCA

2

CD69

0.1U_0201_10V6K

1

Layout Note: Place near JDIMM2

+1.2V_VDDQ

10U_0603_6.3V6M

CD73

1

A A

2

1

2

10U_0603_6.3V6M

CD74

2.2uF*1

0.1uF*1

2

CD70

2.2U_0402_6.3V6M

1

10U_0603_6.3V6M

CD75

1

2

5

+3V_PRIM

RD33 0_0402_5%

10uF*6 1uF*8 330uF*1

10U_0603_6.3V6M

CD76

1

2

10U_0603_6.3V6M

CD77

1

2

10U_0603_6.3V6M

CD79

CD78

CD80

1

2

@

1

+1.2V_VDDQ

1U_0402_6.3V6K

1

2

+3V_PRIM_DB

2

1

CD83

2

CD71

@

0.1U_0402_10V6K

1

1U_0402_6.3V6K

1

CD86

CD85

CD84

2

1U_0402_6.3V6K

1

CD87

2

4

1U_0402_6.3V6K

1

CD88

CD90

CD89

2

3

2

CD81

0.1U_0402_10V6K

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

RD26 1K_0402_1%

1 2

2

RD28 1K_0402_1%

1

2017/04/10 2019/12/15

DIMM Side

+0.6V_DDRB_VREFCA

1 2

RD27

2_0402_1%

2

CD72

0.1U_0402_10V6K

1

Compal Secret Data

Deciphered Date

1

CD82

0.022U_0402_25V7K

2

RD29

24.9_0402_1%

1

2

CONN@

CPU Side

+0.6V_B_VREFDQ

VREF traces should be at least 20 mils wide with 20 mils spacing to other signals

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

P19-DDRIV_CHB: DIMM0

LA-G07DP(KBL-U_UMA_6L)

1

v0.3

18 59Friday, January 05, 2018

v0.3

of

Compal LA-G07EP Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual