Compal LA-G021P Schematics

A

1 1

B

C

D

E

Compal Confidential

2 2

DH5AV_JV_0V Schematics Document

AMD Raven Ridge Platform

AMD R17M-P1-50/R18M-M2-60/R18M-G1-90

3 3

LA-G021P REV:1.B

2017-12-25

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Shared with ACER

A

B

Shared with ACER

2017/12/ 25 2019/12/ 25

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Re v

Custom

Date : Sheet o f

D

Date : Sheet o f

Compal Electronics, Inc.

COVER PAGE

DH5AV_JV_0V_LA-G021P

E

1.B

1 4 8Thursday, January 11, 20 18

A

Compal Confidential

Model Name : DH5AV_JV_0V

B

C

D

E

(Channel A)

1 1

GPU

GDDR5 x4pcs

128- bits

S4 Package R535 : R18M-M2-60 RX540 : R17M-P1-50 RX565 : R18M-G1-90

USB2 .0

Port 1

eDP Conn.

PEG x8

page 15~23

Display Port

Port 0

page 24 page 25

HDMI Conn.

AMD

RAVEN RIDGE

Memory BUS(DDR4)

1.2V DDRIV 2400Mhz

USB2 .0

Port 0

Type-A (CHG) Conn.

Port 4

2 2

USB3 .1

Port 0

260pin DDRIV SO-DIMM

Port 1

page 33

S/B

2.0 Conn.

page 13

Port 2

Type-C Conn.

Port 2,3

AMD FP5 APU BGA 1140-balls

PCI E

Port 0, 1, 2, 3

page 28

SSD NGFF Conn.

Port 4

LAN+CR RTL8411

page 26

USB2 .0

Port 3

Transformer RJ45

page 26 page 26

3 3

Fan Control

page 32

Card Reader Conn.

Port 5

WLAN/BT NGFF Conn.

page 27

page 10

BIOS (8M)

page 31

Discrete TPM

page 6~12

HD Audio(AZ)

I2C

Port 1

Port 3

SATA III

G-Sensor

(Reserve)

PTP

page 28

page 31

HDD Conn .

Port 0

page 28

Port 1

page 28

SSD NGFF Conn.

SPI

LPC

ENE KBC9022

page 30

PS2

page 31

Int.KBD

(Channel B)

page 14

260pin DDRIV SO-DIMM

Port 5

USB2.0 Hub

Touch Screen

page 24

page 29

UAJ on Sub/B

page 29

page 33

Port 1Port 2Port 3

S/B

2.0 Conn.

page 33

page 27

Port 4

Camera

page 24

Port 3

page 34page 33

WLAN/BT Combo

Port 4

Finger Print

page 31

Audio ALC2 55/2 56

page 24

Int. DMIC on Camera

Int. Speaker Conn.

RTC CKT.

Power On/Off CKT.

4 4

DC/DC Interface CKT.

Power Circuit DC/DC

VRAM Config Table

page 11

page 32

page 35

page 36-47

page 23

A

Sub Board

LS-G021 USB2.0/B

LS-E911 Hall Sensor/B

page 33

page 31

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2017/12/25 2019/12/25

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number R ev

Custom

Date : Sheet of

D

Date : Sheet of

Compal Electronics, Inc.

BLOCK DIAGRAMS

DH5AV_JV_0V_LA-G021P

E

2 48Monday, December 25, 2017

1.B

A

B

C

D

E

Voltage Rails

Power Plane

+19V_VIN

+19VB

+APU_CORE

1 1

2 2

+0.8VALW

+0.8VS

+1.8VALW

+1.8VS

+2.5V

+1.2V

+0.6VS

+3VALW

+3VS

+5VALW

+5VS

+RTC_APU

+3V_LAN 3.3V LAN IC power

+TP_VCC 3.3V Touch Pad power

+3VSDGPU

+1.8VSDGPU

+0.8VSDGPU

+VDDCI

+VGA_CORE

+FP_VCC ON

APU SMBus/I2C Address Table

Master

I2C Port 0 (+1.8VS)

I2C Port 1 (+1.8VS)

I2C Port 2 (+3VS)

SBMus Port 0

3 3

(+3VS)

I2C Port 3 (+3VALW)

SMBus Port 1 (+3VALW)

Description

Adapter power supply (19V)

AC or battery power r ail for power circuit.

Core voltage for APU

Voltage for On-die VGA of APU

0.8V always on power rail

0.8V switched power rail

1.8V always on power rail

1.8V switched power rail

2.5V power rail for APU and DDR

1.2V power rail for APU and DDR

0.6V switched power r ail for DDR terminator

3.3V always on power rail

3.3V switched power rail

5V always on power rail

5V switched power rail

RTC power

VGA power

3.3V Finger Print power

Device

G-Sensor

(Reserver)

JDIMM1

JDIMM2

PTP

(Synaptics)

PTP (ELAN)

Address[7: 1]

0001 1000b

18h

0101 0000b

50h

0101 0001b

51h

0010 1100b 2Ch

0001 1111b

15h

Address [7:0]

Write

0011 0000b

30h

1010 0000b A0h

1010 0010b A2h

0101 1000b

58h

0011 1110b 3Eh

ON

ON+APU_CORE_NB

ON

ON ON

ON

ON ON

ON

0011 0001b

31h

1010 0001b A1h

1010 0011b A3h

0101 1001b

59h

0011 1111b 3Fh

ON ON

OFF

OFF OFF

ONON

OFF OFF

ON

OFF OFF

ONON

OFF OFF

ONON

OFF OFF

AC:ON

ON

DC:OFF

OFF OFF

Read

EC SMBus Address Table

SMBus Port 1 (+3VALW)

4 4

SMBus Port 2 (+3VS)

Smart Battery

Charger IC (BQ24735)

APU Temp.

(TSI)

GPU Temp.

CC-Logi c

A

0000 1011b 0Bh

0000 1001b

09h

0100 1100b 4Ch

0100 0001b

41h

1100 0000b C0h

0001 0110b

16h

0001 0010b

12h

1001 1000b

98h

1000 0010b

82h

1000 0000b

80h

0001 0111b

17h

0001 0011b

13h

1001 1001b

99h

1000 0011b

83h

1000 0001b

81h

B

BOARD ID Table

S5S3S0

ONONON

OFF

ONONON

OFF

OFFOFF

OFF

Board ID

0

PCB Revision

EVT 1 DH5 JV 2 3

DH5 AV

DH5 0V

BOM Structure Table

BTO ItemBOM Structure

@ EMC@ /@EM C@ 45@ CON N@ JP@ RS@ TP@ TPM @ PCIE @/T1P CIE @ SAT A@ GS@ LDO@ /SWR @ PAR@ /TI@

CHG@ /NCH G@ 255 @ 256@ /256E MC@ UMA @ R3/R 5/R7A PU@ 15W@ /25W@/35W@ T1@/ T2@ EJ@/ EA@/ VX@ DIS@ /T1D IS@

R53 5@ RX540@ RX565@ LEX A@

VRAM 7G@/VRAM6G@

HUB@ /NHU B@ FP@/ FPEM C@ DMIC 2@/DM IC4 @ HDT @ TYPEC@ TYPE CEMC @ NTYP EC@

Unpop

EMI/ESD Pop/Unpop

HDMI Royalty

Mechanical Connector

Jump

R-Shor t

Test Point

TPM Circuits

PCIE SSD/Type-1 APU PCIE SSD

SATA SSD

G-Sensor Circuits

RTL8411 LDO-Mode/Switching-Mode

SATA Redriver PARADE/TI solution

USB Charger/Non-Charger

Audio Codec AL255 Design

Audio Codec AL256 Design

UMA Config

APU PN Refer p.6

APU Watt Config

APU Type Config

EJ/EA/VX Project Config

VGA Circuits/Type1-APU VGA Circuits

GPU and VRAM Config Refer p.23

R18M-M2-60 GPU

R17M-P1-50 GPU

R18M-G1-90 GPU

LEXA Series VGA

VRAM7G and VRAM6G

USB20 HUB/Non-HUB

Finger Print

2 or 4 DMIC Design

HDT Circuits

TYPEC Circuits

TYPEC EMC Circuits

No TYPEC Circuits

@

ZZZ

DA8001E9010

PCB 28Z LA-G021P REV1 MB 2

PCB@

ZZZ

DAZ28Z00100

PCB DH5JV LA-G021P LS-G021P /E911P

PCB1A@

ZZZ

DAZ28Z00101

PCB DH5JV LA-G021P LS-G021P /E911P 1A

PCB1B@

ZZZ

DAZ28Z00102

PCB DH5JV LA-G021P LS-G021P /E911P 1B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

Board ID / SKU ID Table for AD channel

POWER SEQUENCE

G-A

G-B

G-C

G-D

+RTC BATT

EC_O N

+5VA LW

3V_E N

+3VA LW

0.9_ 1.8V ALW_P WREN

+1.8 VALW /+0.9 VALW

SYSO N

+1.2 V/+2 .5V

SUSP #

+5VS /+3V S/+1. 8VS/ +0.6V S

0.9V S_PW R_EN #

+0.9 VS

VR_O N

+APU _COR E

+APU _COR E_SO C

VGA POWER SEQUENCE

PE_G PIO1 /VGA_ ON

+3VS DGPU

+1.8 VSDG PU

+0.8 VSDG PU

VGA_ ON_B

+VDD CI

+VGA _COR E

DGPU _PWR OK

+1.3 5VSD GPU

PE_G PIO0

Compal Secret Data

2017/12/25 2019/12/25

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number R ev

Custom

Date : Sheet of

Compal Electronics, Inc.

NOTES LIST

DH5AV_JV_0V_LA-G021P

E

3 48Monday, December 25, 2017

1.B

5

PJP101 AC-IN

PU301

1802 0mA

+19V B

5243 mA

638m A

237m A

2311 mA

+19V _VIN

+17. 4V_BAT T

D D

PJP201 DC-IN

C C

PU801

PU501

PU601

PU401

+APU _CORE

+APU _CORE_ SOC

+1.2 V

9500 mA

+0.6 VS

1200 mA

5000 mA

+0.9 VALW

+3VL P

KB9022

B B

+5VA LW

1470 0mA3869 mA 7100 mA

PU401

To VGA +VGA _CORE +VDD CI/VDD _08 +1.3 5VSDGP U

A A

1500 mA

5

L11

3579 mA 169m A 474m A

+INV PWR_B +

Panel BackLight

1334 7mA

4

+3VA LW

4

2026 mA

7335 mA

PU602

+1.8 VALW

3713 mA

U2

To VGA10mA

+3VS

+5VS

4000 mA

2200 mA

304m A

U4

To VGA 1 013mA

U3

JRTC1

PU502

RM9

UL1

RL2

R463

U13

R212

U2606

R269

U8

RW2

RW1

U45

R110

U1

RS127

US12

U25

US10

JIO2

RO3

RF1/RF 7

JPA1

U73

UK6

R3986

3

+0.9 VS

+1.8 VS

+2.5 V

3

U102

+RTC _APU_ R

2

+3VS

+1.8 VS

+0.9 VS

+1.2 V

+3VA LW

+1.8 VALW

+1.8 VS

+0.9 VALW

+RTC _APU_ R

+2.5 V

+1.2 V

+0.6 VS

+3V_ LAN

+TP_ VCC

+3VS _WLAN

+3V_ HUB

+LCD VDD

+3VS _TPM

+3VA LW_TP M

+3VS _CAM

+5VS _BL

+3VA LW_CC

+USB 3_VCC C

+USB 3_VCC A

+5VS _HDD

+VCC _FAN1 +VCC _FAN2

+VDD A

+5VS _DISP

+FP_ VCC

+TS_ PWR

APU Power Rail

VDDCR_VDD @0.65-TBD

VDDCR_SOC @0.72-TBD

Group C, S0 domain

VDD_33 @0.25A

VDD_18 @2.0A

Group B, S0 domain

VDDP @4.0A

VDDIO_MEM_S3 @6.0A

VDD_33_S5 @0.25A

VDD_18_S5 @0.5A

VDDIO_AUDIO @0.2A

Group B, S3 domain

VDDP_S5 @1.0A

VDDBT_RTC_G @0.045mA

Group A, S5 domain

DDR4 SO-DIMM/MEM-DOWN

+2.5V

+1.2V

+0.6VS

SATA Redriver

SSD

LAN RTL8411

Touch Pad

WLAN

USB HUB

R18M-M2-60 R17M-P1-50 R18M-G1-90

Panel Logic

TPM

Camera

+19V B

3579 mA

KB Light

Type C EJ179F

USB3.0 (Charger )

USB/B

HDD

FAN1/FAN 2

Audio

HDMI Logic

+19V B

169m A

+3VA LW 10mA

10mA

+1.8 VALW

1013 mA

+19V B

474m A

Finger Print

Touch Screen

Compal Secret Data

2017/12/25 2019/12/25

Compal Secret Data

Deciphered Date

2

+APU _CORE

7000 0mA

+APU _CORE_ SOC

1300 0mA

250m A

2000 mA

4000 mA

6000 mA

250m A

500m A

200m A

1000 mA

0.04 5mA

400m A

3500 mA

1200 mA

125m A

3500 mA

+3VS _SSD_N GFF

1400 mA

200m A

1500 mA

53.7 mA

1500 mA

50mA

1mA

200m A

500m A

250m A

3000 mA

2000 mA

2500 mA

2000 mA

1500 mA

1000 mA

100m A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECT RONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECT RONICS, INC.

PU1401

PU1405

UV8

PU1001

6000 0mA

8000 mA

4000 mA

1013 mA

6000 mA

1

GPU Power Rail (R18M-G1-90)

+VGA _CORE

VDDC

@60A

PR1501 PR1502

+VDD CI

VDDCI

@8A

PR1503

+0.8 VSDGP U

+3VS DGPU

+1.8 VSDGP U

2000 mA

+1.3 5VSDGP U

4000 mA

+1.3 5VSDGP U

Title

Size

Custom

Date : Sheet of

VDD_08

@4A

VDD_GPIO 33

VDD_18

TSVDD

VMEMIO

@0.01A

@1A

@0.013 A

@2A

VRAM x4pcs

Compal Electronics, Inc.

POWER MAP

Document Number Re v

DH5AV_JV_0V_LA-G021P

1

1.B

4 48Monday, December 25, 2017

1.B

5

Raven Ridge Platform Power Sequence

4

3

2

1

AC-IN G3 --> S0

+3VL P

ACIN

EC_O N

D D

+5VAL W

ON/OFF BTN#

3V_E N

+3VAL W

0.9_1. 8VALW_P WREN

+1.8VA LW

+0.9VA LW

PBTN_O UT#

EC_RSM RST#

SLP_S 5#

SLP_S 3#

SYSO N

+1.2 V

+2.5 V

SUSP #

C C

+5VS

+3VS

+1.8V S

+0.6V S

KBRST #

0.9VS_ PWR_EN #

+0.9V S

VR_O N

+APU_C ORE

+APU_C ORE_SO C

VGAT E

SYS_PW RGD_E C

APU_PW ROK

LPC_RS T#

APU_PC IE_RST #

B B

APU_RS T#

VGA Sequence

PE_GPI O1

+3VSDG PU

+1.8VS DGPU

+0.8VS DGPU +0.8VS DGPU(R18M- M2-60 )

VGA_ON _B

(R18M- G1-90 )

+VDDC I

+VGA_C ORE

DGPU_P WROK

+1.35V SDGPU

PE_GPI O0

PLT_RS T_VGA # PLT_RS T_VGA #

41.37ms

3.3ms, Tr = 339us

1.905us

99ms

218.1ms

880us, Tr = 349us

2.32ms, Tr = 409us

820us, Tr = 153us

202ms

4.601ms

117ms

101ms

100us

98.84us

120.6ms

720us, Tr = 68us

1.44ms, Tr = 601us

20.16ms

620us, Tr = 289us

580us, Tr = 303us

280us, Tr = 86us

20.08ms

20.28ms

400us, Tr = 55us 400us, Tr = 50us2.3ms, Tf = 748us 1.946ms, Tf = 612us

20.22ms

2.393ms, Tr = 145us

2.333ms, Tr = 160us

2.432ms

39.45ms

17.83ms

13.21ms

15.4ms

24.39ms

1.103s

1.013ms, Tr = 472us

5.895ms, Tr = 146us 5.695ms, Tr = 151us

5.041ms

6.273ms, Tr = 31us

6.273ms, Tr = 33us

6.2ms

733us, Tr = 153us 733us, Tr = 145us

164.3ms 117.3ms

S0 --> S3 S3 --> S0

1.31ms

60.28ms

11ms. Tf = 7.276ms

7.2ms, Tf = 4.062ms

7.2ms, Tf = 3.825ms

60.24ms

60.32ms

86.74ms

303us, Tf = 143us

303us, Tf = 120us

29.63ms

3.629ms

94.99us

431.6ms

11.6ms

266us, Tf = 152us

12.99ms, Tf = 1.904ms

32.6ms, Tf = 1.524ms

2.253ms, Tf = 992us

2.253ms, Tf = 1.17ms

6.026, Tf = 2.176ms

14.72ms

620us, Tr = 270us

620us, Tr = 293us

320us, Tr = 90us

200us, Tr = 9us200us, Tr = 9us 4.8ms, Tf = 2.1ms 626us, Tf = 97us

20.2ms

18.9ms

20.2ms

2.293ms, Tr = 143us

2.293ms, Tr = 158us

2.44ms

39.49ms

17.88ms

13.24ms

15.35ms

24.53ms

295ms

953us, Tr = 437us

2.693ms, Tr = 196us2.693ms, Tr = 210us

4.985ms

6.273ms, Tr = 30us

6.723ms, Tr = 30us

6.254ms

S0 --> S5

1.3ms

60.05ms

360us, Tf = 152us

4.54ms, Tf = 1.996ms

57.42ms

11ms, Tf = 7.574ms

6.6ms, Tf = 3.982ms

5.8ms, Tf = 3.407ms

57.36ms

57.44ms

80.02ms

303us, Tf = 133us

303us, Tf = 141us

29.63ms

3.623ms

93.02us

4.56s

12.98ms

306us, Tf = 159us

12.91ms, Tf = 1.86ms

32.6ms, Tf = 1.424ms

2.253ms, Tf = 1.097ms

2.253ms, Tf = 1.175ms

6.026ms, Tf = 2.563ms

8.856s

9.13s

9.12s

21ms, Tf = 14.21ms

Tf = 2.175ms

Tf = 7.438ms

+3VL P

ACIN

EC_O N

+5VAL W

ON/OFF BTN#

3V_E N

+3VAL W

0.9_1. 8VALW_P WREN

+1.8VA LW

+0.9VA LW

PBTN_O UT#

EC_RSM RST#

SLP_S 5#

SLP_S 3#

SYSO N

+1.2 V

+2.5 V

SUSP #

+5VS

+3VS

+1.8V S

+0.6V S

KBRST #

0.9VS_ PWR_EN #

+0.9V S

VR_O N

+APU_C ORE

+APU_C ORE_N B

VGAT E

SYS_PW RGD_E C

APU_PW ROK

LPC_RS T#

APU_PC IE_RST #

APU_RS T#

VGA Sequence

PE_GPI O1

+3VSDG PU

+1.8VS DGPU

VGA_ON _B

+VDDC I

+VGA_C ORE

DGPU_P WROK

+1.35V SDGPU

PE_GPI O0

(R18M- M2-60 )

(R18M- G1-90 )

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

Compal Secret Data

2017/12/25 2019/12/25

Deciphered Date

Compal Electronics, Inc.

Title

Size

Custom

Date: Sheet of

POWER SEQUENCE

Document Number Re v

Document Number Rev

DH5AV_JV_0V_LA-G021P

1

5 48Monday, December 25, 2017

1.B

5

4

3

2

1

Main Func = CPU

UC1B

D D

PEG_ARX _GTX_P0<15> PEG_ARX _GTX_N0<15>

PEG_ARX _GTX_P1<15>

PEG PEG

C C

LAN+CR

WLAN

SSD SSD

B B

PEG_ARX _GTX_N1<15>

PEG_ARX _GTX_P2<15> PEG_ARX _GTX_N2<15>

PEG_ARX _GTX_P3<15> PEG_ARX _GTX_N3<15>

PEG_ARX _GTX_P4<15> PEG_ARX _GTX_N4<15>

PEG_ARX _GTX_P5<15> PEG_ARX _GTX_N5<15>

PEG_ARX _GTX_P6<15> PEG_ARX _GTX_N6<15>

PEG_ARX _GTX_P7<15> PEG_ARX _GTX_N7<15>

PCIE_ARX_ DTX_P0<28> PCIE_ARX_ DTX_N0<28>

PCIE_ARX_ DTX_P1<28> PCIE_ARX_ DTX_N1<28>

PCIE_ARX_ DTX_P2<28> PCIE_ARX_ DTX_N2<28>

PCIE_ARX_ DTX_P3<28> PCIE_ARX_ DTX_N3<28>

PCIE_ARX_ DTX_P4<26> PCIE_ATX_ C_DRX_P4 <26> PCIE_ARX_ DTX_N4<26>

PCIE_ARX_ DTX_N5<27>

SATA_AR X_DTX_P0<28> SATA_AR X_DTX_N0<28>

SATA_AR X_DTX_P1<28> SATA_AR X_DTX_N1<28>

PEG_ARX _GTX_P0 PEG_ARX _GTX_N0

PEG_ARX _GTX_P1 PEG_ARX _GTX_N1

PEG_ARX _GTX_P2 PEG_ARX _GTX_N2

PEG_ARX _GTX_P3 PEG_ARX _GTX_N3

PEG_ARX _GTX_P4 PEG_ARX _GTX_N4

PEG_ARX _GTX_P5 PEG_ARX _GTX_N5

PEG_ARX _GTX_P6 PEG_ARX _GTX_N6

PEG_ARX _GTX_P7 PEG_ARX _GTX_N7

PCIE_ARX_ DTX_P0 PCIE_ARX_ DTX_N0

PCIE_ARX_ DTX_P1 PCIE_ARX_ DTX_N1

PCIE_ARX_ DTX_P2 PCIE_ARX_ DTX_N2

PCIE_ARX_ DTX_P3 PCIE_ARX_ DTX_N3

PCIE_ARX_ DTX_P4 PCIE_ARX_ DTX_N4

PCIE_ARX_ DTX_P5 PCIE_ARX_ DTX_N5

SATA_AR X_DTX_P0 SATA_AT X_DRX_P0 SATA_AR X_DTX_N0

SATA_AR X_DTX_P1 SATA_AR X_DTX_N1 SATA_ATX_ DRX_N1

P8

P_GFX_RXP0

P9

P_GFX_RXN0

N6

P_GFX_RXP1

N7

P_GFX_RXN1

M8

P_GFX_RXP2

M9

P_GFX_RXN2

L6

P_GFX_RXP3

L7

P_GFX_RXN3

K11

P_GFX_RXP4

J11

P_GFX_RXN4

H6

P_GFX_RXP5

H7

P_GFX_RXN5

G6

P_GFX_RXP6

F7

P_GFX_RXN6

G8

P_GFX_RXP7

F8

P_GFX_RXN7

N10

P_GPP_RXP0

N9

P_GPP_RXN0

L10

P_GPP_RXP1

L9

P_GPP_RXN1

L12

P_GPP_RXP2

M11

P_GPP_RXN2

P12

P_GPP_RXP3

P11

P_GPP_RXN3

V6

P_GPP_RXP4

V7

P_GPP_RXN4

T8

P_GPP_RXP5

T9

P_GPP_RXN5

R6

P_GPP_RXP6/SATA_RXP0

R7

P_GPP_RXN6/SATA_RXN0

R9

P_GPP_RXP7/SATA_RXP1

R10

P_GPP_RXN7/SATA_RXN1

@

PCIE

FP5 REV 0.90

PART 2 OF 13

FP5_BGA _1140P

P_GFX_TXP0

P_GFX_TXN0

P_GFX_TXP1

P_GFX_TXN1

P_GFX_TXP2

P_GFX_TXN2

P_GFX_TXP3

P_GFX_TXN3

P_GFX_TXP4

P_GFX_TXN4

P_GFX_TXP5

P_GFX_TXN5

P_GFX_TXP6

P_GFX_TXN6

P_GFX_TXP7

P_GFX_TXN7

P_GPP_TXP0

P_GPP_TXN0

P_GPP_TXP1

P_GPP_TXN1

P_GPP_TXP2

P_GPP_TXN2

P_GPP_TXP3

P_GPP_TXN3

P_GPP_TXP4

P_GPP_TXN4

P_GPP_TXP5

P_GPP_TXN5

P_GPP_TXP6/SATA_TXP0

P_GPP_TXN6/SATA_TXN0

P_GPP_TXP7/SATA_TXP1

P_GPP_TXN7/SATA_TXN1

N1 N3

M2 M4

L2 L4

L1 L3

K2 K4

J2 J4

H1 H3

H2 H4

N2 P3

P4 P2

R3 R1

T4 T2

W2 W4

W3 V2

V1 V3

U2 U4

PEG_ATX _GRX_P0 PEG_ATX _GRX_N0

PEG_ATX _GRX_P1 PEG_ATX _GRX_N1

PEG_ATX _GRX_P2 PEG_ATX _GRX_N2

PEG_ATX _GRX_P3 PEG_ATX _GRX_N3

PEG_ATX _GRX_P4 PEG_ATX _GRX_N4

PEG_ATX _GRX_P5 PEG_ATX _GRX_N5

PEG_ATX _GRX_P6 PEG_ATX _GRX_N6

PEG_ATX _GRX_P7 PEG_ATX _GRX_N7

PCIE_ATX_ DRX_P0 PCIE_ATX_ DRX_N0

PCIE_ATX_ DRX_P1 PCIE_ATX_ DRX_N1

PCIE_ATX_ DRX_P2 PCIE_ATX_ DRX_N2

PCIE_ATX_ DRX_P3 PCIE_ATX_ DRX_N3

PCIE_ATX_ DRX_P4 PCIE_ATX_ DRX_N4

PCIE_ATX_ DRX_P5 PCIE_ATX_ DRX_N5

SATA_AT X_DRX_N0

SATA_AT X_DRX_P1

1 2

CC1204 0.22U_04 02_16V7KPCIE@

1 2

CC1203 0.22U_04 02_16V7KPCIE@

1 2

CC1206 0.22U_04 02_16V7KPCIE@

1 2

CC1205 0.22U_04 02_16V7KPCIE@

1 2

CC1212 0.22U_04 02_16V7KT1PCIE@

1 2

CC1211 0.22U_04 02_16V7KT1PCIE@

1 2

CC1214 0.22U_04 02_16V7KT1PCIE@

1 2

CC1213 0.22U_04 02_16V7KT1PCIE@

1 2

CC1 .1U_0402_16V7K

1 2

CC2 .1U_0402_16V7K

1 2

CC3 .1U_0402_16V7K

1 2

CC4 .1U_0402_16V7K

PEG_ATX _GRX_P0 <15> PEG_ATX _GRX_N0 <15>

PEG_ATX _GRX_P1 <15> PEG_ATX _GRX_N1 <15>

PEG_ATX _GRX_P2 <15> PEG_ATX _GRX_N2 <15>

PEG_ATX _GRX_P3 <15> PEG_ATX _GRX_N3 <15>

PEG_ATX _GRX_P4 <15> PEG_ATX _GRX_N4 <15>

PEG_ATX _GRX_P5 <15> PEG_ATX _GRX_N5 <15>

PEG_ATX _GRX_P6 <15> PEG_ATX _GRX_N6 <15>

PEG_ATX _GRX_P7 <15> PEG_ATX _GRX_N7 <15>

PCIE_ATX_ C_DRX_P0 <28> PCIE_ATX_ C_DRX_N0 <28>

PCIE_ATX_ C_DRX_P1 <28> PCIE_ATX_ C_DRX_N1 <28>

PCIE_ATX_ C_DRX_P2 <28> PCIE_ATX_ C_DRX_N2 <28>

PCIE_ATX_ C_DRX_P3 <28> PCIE_ATX_ C_DRX_N3 <28>

PCIE_ATX_ C_DRX_N4 <26>

PCIE_ATX_ C_DRX_P5 <27>PCIE_ARX_ DTX_P5<27> PCIE_ATX_ C_DRX_N5 <27>

SATA_AT X_DRX_P0 <28>

SATA_AT X_DRX_N0 <28>

SATA_AT X_DRX_P1 <28>

SATA_AT X_DRX_N1 <28>

SSDSSD

LAN+CR

WLAN

HDDHDD

APU PN Table

APU Platform

Rave n

A A

R3 PN R3 PN R3 PN R3 PN

UC1 R3APUDC@

S IC RAVEN3 YM2200C4T2OFB 2G BGA AB O!

SA0000BBJ30

5

UC1 R3APUQC@

S IC RAVEN3 YM2300C4T4MFB 2G BGA AB O!

SA0000BIT20

4

UC1 R5APU@

S IC RAVEN5 YM2500C4T4MFB 2G BGA AB O!

SA0000A8R30

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

UC1 R7APU@

S IC RAVEN7 YM2700C4T4MFB 2.2G BGA ABO!

SA0000ASA20

2017/12/ 25 2019/12/ 25

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Re v

Custom

Date : Sheet o f

2

Date : Sheet o f

Compal Electronics, Inc.

FP5_(1/7)_PEG/PCIE/SATA

DH5AV_JV_0V_LA-G021P

6 4 8Tuesday, December 26, 2 017

1

1.B

5

Main Func = CPU

4

3

2

1

UC1A

DDR_A_MA[13..0]<13>

D D

DDR_A_MA14_W E#< 13> DDR_A_MA15_CAS#<13> DDR_A_MA16_RAS#<13>

DDR_A_BA0<13> DDR_A_BA1<13>

DDR_A_BG0<13> DDR_A_BG1<13>

DDR_A_ACT#< 13>

DDR_A_DM[7..0]<13>

DDR_A_DQS0<13> DDR_A_DQS0#<13> DDR_A_DQS1<13> DDR_A_DQS1#<13> DDR_A_DQS2<13>

C C

B B

DDR_A_DQS2#<13> DDR_A_DQS3<13> DDR_A_DQS3#<13> DDR_A_DQS4<13> DDR_A_DQS4#<13> DDR_A_DQS5<13> DDR_A_DQS5#<13> DDR_A_DQS6<13> DDR_A_DQS6#<13> DDR_A_DQS7<13> DDR_A_DQS7#<13>

DDR_A_CLK0<13> DDR_A_CLK0#<13> DDR_A_CLK1<13> DDR_A_CLK1#<13>

DDR_A_CS0#<13> DDR_A_CS1#<13>

DDR_A_CKE0<13> DDR_A_CKE1<13>

DDR_A_ODT0<13> DDR_A_ODT1<13>

DDR_A_ALERT#<13>

DDR_A_EVENT#<13>

DDR_A_RST#<13>

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12

DDR_A_MA13 DDR_A_MA14_W E# DDR_A_MA15_CAS# DDR_A_MA16_RAS#

DDR_A_BA0 DDR_A_BA1

DDR_A_BG0 DDR_A_BG1

DDR_A_ACT#

DDR_A_DM0

DDR_A_DM1

DDR_A_DM2

DDR_A_DM3

DDR_A_DM4

DDR_A_DM5

DDR_A_DM6

DDR_A_DM7

DDR_A_DQS0 DDR_A_DQS0# DDR_A_DQS1 DDR_A_DQS1# DDR_A_DQS2 DDR_A_DQS2# DDR_A_DQS3 DDR_A_DQS3# DDR_A_DQS4 DDR_A_DQS4# DDR_A_DQS5 DDR_A_DQS5# DDR_A_DQS6 DDR_A_DQS6# DDR_A_DQS7 DDR_A_DQS7#

DDR_A_CLK0 DDR_A_CLK0# DDR_A_CLK1 DDR_A_CLK1#

DDR_A_CS0# DDR_A_CS1#

DDR_A_CKE0 DDR_A_CKE1

DDR_A_ODT0 DDR_A_ODT1

DDR_A_ALERT#

DDR_A_EVENT# DDR_A_RST#

AF25 AE23 AD27 AE21 AC24 AC26 AD21 AC27 AD22 AC21 AF22 AA24 AC23

AJ25 AG27 AG23 AG26

AF21 AF27

AA21 AA27

AA22

AL24 AN27

AW25

AT21

AM26 AM27

AN24 AN25 AU23 AT23 AV20

AW20

AD25 AD24 AE26 AE27

AG21

AJ27

AG24

AJ22

AA25

AE24

F21 G27 N24 N23

T27

F22 G22 H27 H26 N27 N26 R21 P21

V24 V23

Y23 Y26

Y24

MA_ADD0

MA_ADD1

MA_ADD2

MA_ADD3

MA_ADD4

MA_ADD5

MA_ADD6

MA_ADD7

MA_ADD8

MA_ADD9

MA_ADD10

MA_ADD11

MA_ADD12

MA_ADD13_BANK2

MA_WE_L_ADD14

MA_CAS_L_ADD15

MA_RAS_L_ADD16

MA_BANK0

MA_BANK1

MA_BG0

MA_BG1

MA_ACT_L

MA_DM0

MA_DM1

MA_DM2

MA_DM3

MA_DM4

MA_DM5

MA_DM6

MA_DM7

RSVD_36

MA_DQS_H0

MA_DQS_L0

MA_DQS_H1

MA_DQS_L1

MA_DQS_H2

MA_DQS_L2

MA_DQS_H3

MA_DQS_L3

MA_DQS_H4

MA_DQS_L4

MA_DQS_H5

MA_DQS_L5

MA_DQS_H6

MA_DQS_L6

MA_DQS_H7

MA_DQS_L7

RSVD_41

RSVD_40

MA_CLK_H0

MA_CLK_L0

MA_CLK_H1

MA_CLK_L1

MA_CS_L0

MA_CS_L1

MA_CKE0

MA_CKE1

MA_ODT0

MA_ODT1

MA_ALERT_L

MA_EVENT_L

MA_RESET_L

@

MEMORY A

FP5 REV 0.90 PART 1 OF 13

FP5_BGA_1140P

MA_DATA0

MA_DATA1

MA_DATA2

MA_DATA3

MA_DATA4

MA_DATA5

MA_DATA6

MA_DATA7

MA_DATA8

MA_DATA9

MA_DATA10

MA_DATA11

MA_DATA12

MA_DATA13

MA_DATA14

MA_DATA15

MA_DATA16

MA_DATA17

MA_DATA18

MA_DATA19

MA_DATA20

MA_DATA21

MA_DATA22

MA_DATA23

MA_DATA24

MA_DATA25

MA_DATA26

MA_DATA27

MA_DATA28

MA_DATA29

MA_DATA30

MA_DATA31

MA_DATA32

MA_DATA33

MA_DATA34

MA_DATA35

MA_DATA36

MA_DATA37

MA_DATA38

MA_DATA39

MA_DATA40

MA_DATA41

MA_DATA42

MA_DATA43

MA_DATA44

MA_DATA45

MA_DATA46

MA_DATA47

MA_DATA48

MA_DATA49

MA_DATA50

MA_DATA51

MA_DATA52

MA_DATA53

MA_DATA54

MA_DATA55

MA_DATA56

MA_DATA57

MA_DATA58

MA_DATA59

MA_DATA60

MA_DATA61

MA_DATA62

MA_DATA63

RSVD_34

RSVD_35

RSVD_51

RSVD_52

RSVD_27

RSVD_28

RSVD_43

RSVD_42

MA_PAROUT

J21 H21 F23 H23 G20 F20 J22 J23

G25 F26 L24 L26 L23 F25 K25 K27

M25 M27 P27 R24 L27 M24 P24 P25

M22 N21 T22 V21 L21 M20 R23 T21

AL27 AL25 AP26 AR27 AK26 AK24 AM24 AP27

AM23 AM21 AR25 AU27 AL22 AL21 AP24 AP23

AW26 AV25 AV22 AW22 AU26 AV27 AW23 AT22

AW21 AU21 AP21 AN20 AR22 AN22 AT20 AR20

T24 T25 W25 W27 R26 R27 V27 V26

AF24

DDR_A_DQ0 DDR_A_DQ1 DDR_A_DQ2 DDR_A_DQ3 DDR_A_DQ4 DDR_A_DQ5 DDR_A_DQ6 DDR_A_DQ7

DDR_A_DQ8 DDR_A_DQ9 DDR_A_DQ10 DDR_A_DQ11 DDR_A_DQ12 DDR_A_DQ13 DDR_A_DQ14 DDR_A_DQ15

DDR_A_DQ16 DDR_A_DQ17 DDR_A_DQ18 DDR_A_DQ19 DDR_A_DQ20 DDR_A_DQ21 DDR_A_DQ22 DDR_A_DQ23

DDR_A_DQ24 DDR_A_DQ25 DDR_A_DQ26 DDR_A_DQ27 DDR_A_DQ28 DDR_A_DQ29 DDR_A_DQ30 DDR_A_DQ31

DDR_A_DQ32 DDR_A_DQ33 DDR_A_DQ34 DDR_A_DQ35 DDR_A_DQ36 DDR_A_DQ37 DDR_A_DQ38 DDR_A_DQ39

DDR_A_DQ40 DDR_A_DQ41 DDR_A_DQ42 DDR_A_DQ43 DDR_A_DQ44 DDR_A_DQ45 DDR_A_DQ46 DDR_A_DQ47

DDR_A_DQ48 DDR_A_DQ49 DDR_A_DQ50 DDR_A_DQ51 DDR_A_DQ52 DDR_A_DQ53 DDR_A_DQ54 DDR_A_DQ55

DDR_A_DQ56 DDR_A_DQ57 DDR_A_DQ58 DDR_A_DQ59 DDR_A_DQ60 DDR_A_DQ61 DDR_A_DQ62 DDR_A_DQ63

DDR_A_PAR

DDR_A_DQ[63..0] <13>

DDR_A_PAR <13>

DDR_B_MA[13..0]<14>

DDR_B_MA14_ WE#<14> DDR_B_MA15_ CAS#<14> DDR_B_MA16_ RAS#<14>

DDR_B_BA0<14> DDR_B_BA1<14>

DDR_B_BG0<14> DDR_B_BG1<14>

DDR_B_ACT#<14>

DDR_B_DM[7 ..0]<14>

DDR_B_DQS0<14> DDR_B_DQS0 #<14> DDR_B_DQS1<14> DDR_B_DQS1 #<14> DDR_B_DQS2<14> DDR_B_DQS2 #<14> DDR_B_DQS3<14> DDR_B_DQS3 #<14> DDR_B_DQS4<14> DDR_B_DQS4 #<14> DDR_B_DQS5<14> DDR_B_DQS5 #<14> DDR_B_DQS6<14> DDR_B_DQS6 #<14> DDR_B_DQS7<14> DDR_B_DQS7 #<14>

DDR_B_CLK 0<14> DDR_B_CLK 0#<14> DDR_B_CLK 1<14> DDR_B_CLK 1#<14>

DDR_B_CS0 #<14> DDR_B_CS1 #<14>

DDR_B_CKE0<14> DDR_B_CKE1<14>

DDR_B_ODT 0<14> DDR_B_ODT 1<14>

DDR_B_ALERT #<14>

DDR_B_EVENT #<14> DDR_B_RST #<14>

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12

DDR_B_MA13 DDR_B_MA14_ WE# DDR_B_MA15_ CAS# DDR_B_MA16_ RAS#

DDR_B_BA0 DDR_B_BA1

DDR_B_BG0 DDR_B_BG1

DDR_B_ACT#

DDR_B_DM0

DDR_B_DM1

DDR_B_DM2

DDR_B_DM3

DDR_B_DM4

DDR_B_DM5

DDR_B_DM6

DDR_B_DM7

DDR_B_DQS0 DDR_B_DQS0 # DDR_B_DQS1 DDR_B_DQS1 # DDR_B_DQS2 DDR_B_DQS2 # DDR_B_DQS3 DDR_B_DQS3 # DDR_B_DQS4 DDR_B_DQS4 # DDR_B_DQS5 DDR_B_DQS5 # DDR_B_DQS6 DDR_B_DQS6 # DDR_B_DQS7 DDR_B_DQS7 #

DDR_B_CLK 0 DDR_B_CLK 0# DDR_B_CLK 1 DDR_B_CLK 1#

DDR_B_CS0 # DDR_B_CS1 #

DDR_B_CKE0 DDR_B_CKE1

DDR_B_ODT 0 DDR_B_ODT 1

DDR_B_ALERT #

DDR_B_EVENT # DDR_B_RST #

AG30 AC32 AC30 AB29 AB31 AA30 AA29

AA31

W29

AH29

W31

AL30 AK30 AK32

AJ30

AH31 AG32

AP30

AW31

BB26 BD22

AR29 AR31

AW30 AW29

BC25 BA25 BC22 BA22

AC31 AD30 AD29 AD31 AE30 AE32 AF29 AF31

AJ31 AM31

AJ29 AM29

AL31 AM32

AL29 AM30

W30

AG29

Y30

Y32

V31 V29

V30

C21 C25 E32 K30

N32

D22 B22 D25 B25 F29 F30 K31 K29

N31 N29

U29 T30 V32 U31

T31

MB_ADD0

MB_ADD1

MB_ADD2

MB_ADD3

MB_ADD4

MB_ADD5

MB_ADD6

MB_ADD7

MB_ADD8

MB_ADD9

MB_ADD10

MB_ADD11

MB_ADD12

MB_ADD13_BANK2

MB_WE_L_ADD14

MB_CAS_L_ADD15

MB_RAS_L_ADD16

MB_BANK0

MB_BANK1

MB_BG0

MB_BG1

MB_ACT_L

MB_DM0

MB_DM1

MB_DM2

MB_DM3

MB_DM4

MB_DM5

MB_DM6

MB_DM7

RSVD_21

MB_DQS_H0

MB_DQS_L0

MB_DQS_H1

MB_DQS_L1

MB_DQS_H2

MB_DQS_L2

MB_DQS_H3

MB_DQS_L3

MB_DQS_H4

MB_DQS_L4

MB_DQS_H5

MB_DQS_L5

MB_DQS_H6

MB_DQS_L6

MB_DQS_H7

MB_DQS_L7

RSVD_20

RSVD_18

MB_CLK_H0

MB_CLK_L0

MB_CLK_H1

MB_CLK_L1

MB_CLK_H2

MB_CLK_L2

MB_CLK_H3

MB_CLK_L3

MB0_CS_L0

MB0_CS_L1

MB1_CS_L0

MB1_CS_L1

MB0_CKE0

MB0_CKE1

MB1_CKE0

MB1_CKE1

MB0_ODT0

MB0_ODT1

MB1_ODT0

MB1_ODT1

MB_ALERT_L

MB_EVENT_L

MB_RESET_L

@

UC1I

MEMORY B

FP5 REV 0.90 PART 9 OF 13

FP5_BGA_1140P

MB_DATA0

MB_DATA1

MB_DATA2

MB_DATA3

MB_DATA4

MB_DATA5

MB_DATA6

MB_DATA7

MB_DATA8

MB_DATA9

MB_DATA10

MB_DATA11

MB_DATA12

MB_DATA13

MB_DATA14

MB_DATA15

MB_DATA16

MB_DATA17

MB_DATA18

MB_DATA19

MB_DATA20

MB_DATA21

MB_DATA22

MB_DATA23

MB_DATA24

MB_DATA25

MB_DATA26

MB_DATA27

MB_DATA28

MB_DATA29

MB_DATA30

MB_DATA31

MB_DATA32

MB_DATA33

MB_DATA34

MB_DATA35

MB_DATA36

MB_DATA37

MB_DATA38

MB_DATA39

MB_DATA40

MB_DATA41

MB_DATA42

MB_DATA43

MB_DATA44

MB_DATA45

MB_DATA46

MB_DATA47

MB_DATA48

MB_DATA49

MB_DATA50

MB_DATA51

MB_DATA52

MB_DATA53

MB_DATA54

MB_DATA55

MB_DATA56

MB_DATA57

MB_DATA58

MB_DATA59

MB_DATA60

MB_DATA61

MB_DATA62

MB_DATA63

RSVD_17

RSVD_19

RSVD_26

RSVD_29

RSVD_16

RSVD_15

RSVD_25

RSVD_24

MB_PAROUT

B21 D21 B23 D23 A20 C20 A22 C22

D24 A25 D27 C27 C23 B24 C26 B27

C30 E29 H29 H31 A28 D28 F31 G30

J29 J31 L29 L31 H30 H32 L30 L32

AP29 AP32 AT29 AU32 AN30 AP31 AR30 AT31

AU29 AV30 BB30 BA28 AU30 AU31 AY32 AY29

BA27 BC27 BA24 BC24 BD28 BB27 BB25 BD25

BC23 BB22 BC21 BD20 BB23 BA23 BB21 BA21

M31 N30 P31 R32 M30 M29 P30 P29

AG31

DDR_B_DQ0 DDR_B_DQ1 DDR_B_DQ2 DDR_B_DQ3 DDR_B_DQ4 DDR_B_DQ5 DDR_B_DQ6 DDR_B_DQ7

DDR_B_DQ8 DDR_B_DQ9 DDR_B_DQ10 DDR_B_DQ11 DDR_B_DQ12 DDR_B_DQ13 DDR_B_DQ14 DDR_B_DQ15

DDR_B_DQ16 DDR_B_DQ17 DDR_B_DQ18 DDR_B_DQ19 DDR_B_DQ20 DDR_B_DQ21 DDR_B_DQ22 DDR_B_DQ23

DDR_B_DQ24 DDR_B_DQ25 DDR_B_DQ26 DDR_B_DQ27 DDR_B_DQ28 DDR_B_DQ29 DDR_B_DQ30 DDR_B_DQ31

DDR_B_DQ32 DDR_B_DQ33 DDR_B_DQ34 DDR_B_DQ35 DDR_B_DQ36 DDR_B_DQ37 DDR_B_DQ38 DDR_B_DQ39

DDR_B_DQ40 DDR_B_DQ41 DDR_B_DQ42 DDR_B_DQ43 DDR_B_DQ44 DDR_B_DQ45 DDR_B_DQ46 DDR_B_DQ47

DDR_B_DQ48 DDR_B_DQ49 DDR_B_DQ50 DDR_B_DQ51 DDR_B_DQ52 DDR_B_DQ53 DDR_B_DQ54 DDR_B_DQ55

DDR_B_DQ56 DDR_B_DQ57 DDR_B_DQ58 DDR_B_DQ59 DDR_B_DQ60 DDR_B_DQ61 DDR_B_DQ62 DDR_B_DQ63

DDR_B_PAR

DDR_B_DQ[63 ..0] <14>

DDR_B_PAR <14>

EVENT# pull high

+1.2V

1 2

RC1 1K_0402_5%

+1.2V

1 2

A A

5

RC2 1K_0402_5%

DDR_B_EVENT #

DDR_A_EVENT#

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/12/25 2019/12/25

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number R ev

Custom

Date : Sheet of

2

Date : Sheet of

Compal Electronics, Inc.

FP5_(2/7)_DDR4

DH5AV_JV_0V_LA-G021P

1

1.B

7 48Monday, December 25, 2017

1.B

A

Main Func = CPU

EC/THERM

+3VS

RPC25

APU_SID

18

APU_ALERT#

27

APU_SIC

36

APU_PROCHOT#

1 1

+3VS

2 2

+3VS

Close to APU

SVID

3 3

45

1K_0804_8P 4R_5%

1 2

RC16 1K_0402_5%@

1 2

RC17 1K_0402_5%@

EC_SMB_CK2<16 ,30,34>

EC_SMB_DA2<16 ,30,34>

1 2

RC664 1K_0402_5%

1

@EMC@

CC1202 .1U_0402_1 6V7K

2

+1.8VS

1

EMC@

CC5 33P_0402_5 0V8J

2

Reserve for debug

EC_SMB_CK2 EC_SMB_DA2

EC_SMB_CK2

EC_SMB_DA2

THERMTRIP#

RPC65

@

18 27 36 45

1K_0804_8P 4R_5%

2

G

6 1

D

RC616 0_0402_ 5%NTYPEC@ RC617 0_0402_ 5%NTYPEC@

1

EMC@

CC6 33P_0402_5 0V8J

2

APU_SVT_R

APU_SVC APU_SVD

+3VS

5

G

QC1B 2N7002KDW _SOT363-6

SB00000EO00

3 4

S

D

TYPEC@

QC1A 2N7002KDW _SOT363-6

SB00000EO00

S

TYPEC@

1 2 1 2

APU_PROCHOT#

APU_RST#

APU_PWROK

APU_SIC

APU_SID

APU_SVT_R<42>

HDMI

EDP

+1.8VS +1.8VS

APU_PWROK<42>

APU_SVC<42> APU_SVD<42>

B

APU_DP0_P0<25> APU_DP0_N0<25>

APU_DP0_P1<25> APU_DP0_N1<25>

APU_DP0_P2<25> APU_DP0_N2<25>

APU_DP0_P3<25> APU_DP0_N3<25>

EDP_TXP0<24> EDP_TXN0<24>

EDP_TXP1<24> EDP_TXN1<24>

EDP_TXP2<24> EDP_TXN2<24>

EDP_TXP3<24> EDP_TXN3<24>

1 2

RC80 300_0402_ 5%

1 2

RC81 300_0402_ 5%

THERMTRIP#<30>

APU_PROCHOT#<30,38,42>

1 2

RC669 0_0402_5%

1 2

RC670 0_0402_5%

APU_DP0_P0 APU_DP0_N0

APU_DP0_P1 APU_DP0_N1

APU_DP0_P2 APU_DP0_N2

APU_DP0_P3 APU_DP0_N3

EDP_TXP0 EDP_TXN0

EDP_TXP1 EDP_TXN1

EDP_TXP2 EDP_TXN2

EDP_TXP3 EDP_TXN3

APU_TDI APU_TDO APU_TCK APU_TMS APU_TRST# APU_DBREQ#

APU_RST# APU_PWROK

APU_SIC APU_SID APU_ALERT#

THERMTRIP# APU_PROCHOT#

APU_SVC_R APU_SVD_R APU_SVT_R

AW3

AW4 AW2

AP16

AU2 AU4 AU1 AU3 AV3

H14

L19

F16 H16

C8

D8

C7

C6 D6

D5

C1

J14 J15

J16

A8

B8

B6

E6

E1

F3 E4

F4 F2

DP0_TXP0

DP0_TXN0

DP0_TXP1

DP0_TXN1

DP0_TXP2

DP0_TXN2

DP0_TXP3

DP0_TXN3

DP1_TXP0

DP1_TXN0

DP1_TXP1

DP1_TXN1

DP1_TXP2

DP1_TXN2

DP1_TXP3

DP1_TXN3

TDI

TDO

TCK

TMS

TRST_L

DBREQ_L

RESET_L

PWROK

SIC

SID

ALERT_L

THERMTRIP_L

PROCHOT_L

SVC0

SVD0

SVT0

@

DISPLAY/SVI2/ JTAG/TE ST

DP3: DP2: DP1: eDP DP0: HDMI

IO18S5

IO18

IO33

IO18

FP5_BGA_1140P

UC1C

FP5 REV 0.90 PART 3 OF 13

C

IO18

DP_DIGON

DP_VARY_BL

DP0_AUXP

DP0_AUXN

DP1_AUXP

DP1_AUXN

DP2_AUXP

DP2_AUXN

DP3_AUXP

DP3_AUXN

DP_STEREOSYNC

SMU_ZVDD

CORETYPE

VDDP_SENSE

VDDCR_SOC_SENSE

VDDCR_SENSE

VSS_SENSE_A

VSS_SENSE_B

DP_BLON

DP0_HPD

DP1_HPD

DP2_HPD

DP3_HPD

RSVD_4

RSVD_3

RSVD_2

TEST4

TEST5

TEST6

TEST14

TEST15

TEST16

TEST17

TEST31

TEST41

TEST470

TEST471

ENBKL_R

G15

ENVDD_R

F15

INVTPWM_R

L14

APU_DP0_CTR L_CLK

D9

APU_DP0_CTR L_DATA

B9

APU_DP0_HPD

C10

EDP_AUXP

G11

EDP_AUXN

F11

EDP_HPD

G13

J12 H12 K13

J10 H10 K8

DP_STEREOSYNC

K15

F14 F12

F10

APU_TEST4

AP14

APU_TEST5

AN14

F13

APU_TEST14

G18

APU_TEST15

H19

APU_TEST16

F18

APU_TEST17

F19

APU_TEST31

W24

APU_TEST41

AR11

APU_TEST470

AJ21

APU_TEST471

AK21

SMU_ZVDDP

V4

AW11

CORETYPE

APU_VDDP_SEN_H

AN11

APU_CORESOC_SE N_H

J19

APU_CORE_SEN_ H

K18

APU_VSS_SEN_L

J18

APU_VDDP_SEN_L

AM11

APU_DP0_CTR L_CLK <25> APU_DP0_CTR L_DATA <25> APU_DP0_HPD <25>

EDP_AUXP <24> EDP_AUXN <24> EDP_HPD <24>

TP@

T4949

TP@

T4948

TP@

T4942

TP@

T4941

TP@

T4940

TP@

T4939

1 2

RC1682 196_040 2_1%

1 2

RC1681 1K_0402_ 5%@

APU_VDDP_SEN_H <41> APU_CORESOC_SE N_H <42> APU_CORE_SEN_ H <4 2>

APU_VSS_SEN_L <42> APU_VDDP_SEN_L <41>

D

HDMI

EDP

+0.9VS

+3VALW

Leakage prevent from power side

DISP

ENBKL_R

ENVDD_R

INVTPWM_R

ENBKL

ENVDD

INVTPWM

ENBKL_R

ENVDD_R

INVTPWM_R

+1.8VALW

5

UC66

1

P

NC

4

ENBKL

Y

2

A

G

NL17SZ07DFT 2G_SC70-5

3

SA00004BV00

+1.8VALW

5

UC64

1

P

NC

4

Y

2

A

G

NL17SZ07DFT 2G_SC70-5

3

SA00004BV00

@

1 2

RC690 0_0402_5%RS@

+1.8VALW

5

UC65

1

P

NC

4

Y

2

A

G

NL17SZ07DFT 2G_SC70-5

3

SA00004BV00

1 2

RC3 4.7K_0402_5 %

1 2

RC4 4.7K_0402_5 %@

1 2

RC5 4.7K_0402_5 %

1 2

RC6130 100K_040 2_5%

1 2

RC6131 100K_040 2_5%

1 2

RC6132 100K_040 2_5%@

ENVDD

INVTPWM

E

ENBKL <30>

ENVDD <24>

ENVDD

INVTPWM <24>

+3VS

HDT+

+1.8VALW

RPH3

10K_0804_8 P4R_5%

APU_TRST#_R

HDT_P11

HDT_P13

HDT_P15

1 2

RH21 3 3_0402_5%

0.01U_0402 _16V7K

4 4

1

2

CH2

1 8 2 7 3 6 4 5

A

JHDT1

@

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

SAMTE_ASP-13644 6-07-B

2

4

6

8

10

12

14

16

18

20

APU_TCK_R

APU_TMS_R

APU_TDI_R

APU_TDO_R

APU_PWROK_R

APU_RST#_R

APU_DBREQ#_R

B

1 2

RH27 0 _0402_5%HDT@

1 2

RH28 0 _0402_5%HDT@

1 2

RH29 0 _0402_5%HDT@

1 2

RH30 0 _0402_5%HDT@

1 2

RH31 0 _0402_5%HDT@

1 2

RH32 0 _0402_5%HDT@

1 2

RH33 3 3_0402_5%

Follow C5V08

APU_TCK

APU_TMS

APU_TDI

APU_TDO

APU_PWROK

APU_RST#

APU_DBREQ#

APU_TCK APU_TMS APU_TDI APU_DBREQ#

APU_TRST#APU_TRST#

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

RPH1

1 8 2 7 3 6 4 5

1K_0804_8P 4R_5%

1 2

RH26 1K_0402_5%

+1.8VALW

Compal Secret Data

2017/12/25 2019/12/25

Compal Secret Data

Deciphered Date

D

TESTPOINT

DP_STEREOSYNC

Title

Size Document Number R ev

Custom

Date : Sheet of

+1.8VS

1 2

RC155 1K_0402_5%

1 2

RC154 1K_0402_5%@

+1.8VS

RPC30

APU_TEST14 APU_TEST15 APU_TEST16 APU_TEST17

Compal Electronics, Inc.

(3/7)_DISP/MISC/HDT

DH5AV_JV_0V_LA-G021P

@

10K_0804_8 P4R_5%

E

18 27 36 45

1.B

8 48Monday, December 25, 2017

1.B

Main Func = CPU

A

B

C

D

E

UC1D

SW PU/PD

ACPI/AUDIO/I2C/GPI O/MISC

SW PU/PD SW PU/PD

SW PU/PD

FP5 REV 0.90 PART 4 OF 13

FP5_BGA_1140P

1.8V_S5

SW PU/PD

EGPIO41/SFI_S5_EGPIO41

AGPIO39/SFI_S5_AGPIO39

I2C0_SCL/SFI0_I2C_SCL/EGPIO151

I2C0_SDA/SFI0_I2C_SDA/EGPIO152

I2C1_SCL/SFI1_I2C_SCL/EGPIO149

I2C1_SDA/SFI1_I2C_SDA/EGPIO150

I2C2_SCL/EGPIO113/SCL0

3.3V

I2C2_SDA/EGPIO114/SDA0

I2C3_SCL/AGPIO19/SCL1

3.3V_S5

I2C3_SDA/AGPIO20/SDA1

AGPIO4/SATAE_IFDET

SATA_ACT_L/AGPIO130

3.3VALW input

3.3VS input

3.3VS Output

3.3VS input

PSA_I2C_SCL

PSA_I2C_SDA

AGPIO5/DEVSLP0

AGPIO6/DEVSLP1

INTRUDER_ALERT

SPKR/AGPIO91

BLINK/AGPIO11

GENINT1_L/AGPIO89

GENINT2_L/AGPIO90

FANIN0/AGPIO84

FANOUT0/AGPIO85

AGPIO40

AGPIO69

AGPIO86

AW12 AU12

I2C_0_SCL

AR13

I2C_0_SDA

AT13

I2C_1_SCL

AN8

I2C_1_SDA

AN9

SMB_0_SCL

BC20

SMB_0_SDA

BA20

I2C_3_SCL

AM9

I2C_3_SDA

AM10

L16 M16

AT15

AGPIO3

AW10

AGPIO4

AP9

AGPIO5

AU10

DEVSLP1

AV15

AU7

AGPIO9

AU6

AGPIO40

AW13

G_INT#_APU

AW15

AU14

APU_SPKR

AU16 AV8

AGPIO11

AW16

TP_I2C_INT#_APU

BD15

AR18 AT18

I2C_1_SCL <28> I2C_1_SDA <28>

SMB_0_SCL <13,14> SMB_0_SDA <13,14>

I2C_3_SCL <31> I2C_3_SDA <31>

DEVSLP1 <28>

G_INT#_APU <28>

APU_SPKR <29>

TP_I2C_INT#_APU < 31>

G-SENSOR

DDR4

Touch Pad

I2C_0_SCL I2C_0_SDA

SMB_0_SCL SMB_0_SDA

I2C_3_SCL I2C_3_SDA

AGPIO8

DEVSLP1

1 2

RC6139 2.2K_0402_5%@

1 2

RC6140 2.2K_0402_5%@

1 2

RC6157 2.2K_0402_5%

1 2

RC6156 2.2K_0402_5%

1 2

RC6159 2.2K_0402_5%

1 2

RC6158 2.2K_0402_5% RC6167 10K_0402_5%@

RC663 10K_0402_5%@

AGPIO4 0

DIS

H

1 2

CC7 150P_0402_50V8J

1 2

CC100 150P_0 402_50V8J@

1 2

1 1

RC29 33_0402_5%

1 2

RC704 33_0402_5%@

EC_RSMRST#<30>

PBTN_OUT#<30>

SYS_PWRGD_EC<30>

SLP_S3#<30> SLP_S5#<30,38>

ACPI

+3VALW

1 2

RC6133 10K_0402_5%@

CRB use S0-rail

+3VALW

2 2

+3VS

12

RC6165 10K_0402_1%@

RC28 10K_0402_1%

2

CC8

0.22U_0402_16V7K

1

APU_PCIE_WAKE#

Reserve for MBDG/CRB

+1.8VALW

CC1210

10U_0603_6.3V6M

1 2

@

12

RC54 22K_0402_1%

SYS_PWRGD_EC EC_RSMRST#

1

CC16 1U_0201_6.3V6M

2

HDA_SDIN0<29>

AGPIO8<28>

APU_PCIE_RST#_RAPU_PCIE_RST#_C APU_PCIE1_RST#_RAPU_PCIE1_RST#_C EC_RSMRST#

PBTN_OUT# SYS_PWRGD_EC SYS_RST# APU_PCIE_WAKE#

SLP_S3# SLP_S5#

AGPIO10

AGPIO23 AGPIO12

HDA_BIT_CLK HDA_SDIN0 HDA_SDIN1 HDA_SDIN2 HDA_RST# HDA_SYNC HDA_SDOUT

AGPIO7 AGPIO8

BD5

PCIE_RST0_L/EGPIO26

BB6

PCIE_RST1_L/EGPIO27

AT16

RSMRST_L

AR15

PWR_BTN_L/AGPIO0

AV6

PWR_GOOD

AP10

SYS_RESET_L/AGPIO1

AV11

WAKE_L/AGPIO2

AV13

SLP_S3_L

AT14

SLP_S5_L

AR8

S0A3_GPIO/AGPIO10

AT10

AC_PRES/AGPIO23

AN6

LLB_L/AGPIO12

AW8

EGPIO42

AR2

AZ_BITCLK/TDM_BCLK_MIC

AP7

AZ_SDIN0/CODEC_GPI

AP1

AZ_SDIN1/SW_DATA1B/TDM_BCLK_PLAYBACK

AP4

AZ_SDIN2/SW_DATA2/TDM_DATA_PLAYBACK

AP3

AZ_RST_L/SW_DATA1A/SW_DATA3/TDM_DATA_MIC

AR4

AZ_SYNC/TDM_FRM_MIC

AR3

AZ_SDOUT/TDM_FRM_PLAYBACK

AT2

SW_MCLK/TDM_BCLK_BT

AT4

SW_DATA0/TDM_DOUT_BT

AR6

AGPIO7/FCH_ACP_I2S_SDIN_BT

AP6

AGPIO8/FCH_ACP_I2S_LRCLK_BT

@

L

APU_PCIE_RST#_C APU_PCIE_RST#_U APU_PCIE1_RST#_C

APU_PCIE_RST#_U APU_PCIE_RST#

APU_PCIE_RST#_U

3 3

RC6160

10K_0402_5% @

1 2

RC700 0_0402_5%RS@

1 2

RC701 0_0402_5%@

1 2

RC30 0_0402_5%RS@

+3VALW

1

IN1

2

IN2

@

CC14

0.1U_0201_10V6K

1 2

@

5

P

4

O

G

UC4

SA00000OH00

3

MC74VHC1G08DFT2G_SC70-5

APU_PCIE_RST#

APU_PCIE_RST# <15,26,27, 28>

GPIO Table

AGPIO40 AGPIO9 AGPIO12 AGPIO23

DIS@

RC693

10K_0402_5%

UMA@

RC692

10K_0402_5%

12

10K_0402_5%

12

10K_0402_5%

AGPIO9

Type1

Type2

T1@

RC6147

T2@

RC6148

+1.8VALW

+3VS

+3VALW

+3VS

12

10K_0402_5%

12

10K_0402_5%

AGPIO1 2

DMIC x4

DMIC x2

DMIC4@

RC6135

DMIC2@

RC6136

12

10K_0402_5%

12

10K_0402_5%

AGPIO2 3

RSV

RSVUMA

+3VALW

@

RC6175

@

RC6174

12

AGPIO1 0 AGPIO1 1

AGPIO7AGPI O5

35W@

15W@

L

H

15W

25W

35W

12

25W@

RC6137

10K_0402_5%

12

15W@

RC6138

10K_0402_5%

2017/12/25 2019/12/25

HDA

EMC@

RPC4

33_0804_8P4R_5%

HDA_RST#_R<29> HDA_BIT_CLK_R<29> HDA_SYNC_R<29> HDA_SDOUT_R<29>

4 4

1 8 2 7 3 6 4 5

RPC5

1K_0804_8P4R_5%

1 2

RC695 10K_0402_5 %

1 2

RC696 10K_0402_5 %

1 2

RC703 10K_0402_5 %@

A

HDA_RST# HDA_BIT_CLK HDA_SYNC HDA_SDOUT

18 27 36 45

HDA_SDIN1 HDA_SDIN2 HDA_SDIN0

Strap Pin

APU_SPI_ CLK_R S YS_RST#

USE 48MHZ CRYSTAL

H

CLOCK (Default)

USE 100MHZ PCIE

L

CLOCK AS REFERENCE CLOCK

APU_SPI_CLK_R<10>

B

NORMAL RESET MODE (Default)

SHORT RESET MODE

+1.8VS +1.8VALW +3VALW

12

RC622

10K_0402_5%

10K_0402_5% @

APU_SPI_CLK_R SYS_RST#

RC1703

2K_0402_5% @

12

RC951

RC47

10K_0402_5%

12

RC929

2K_0402_5% @

C

L

H L

RC6145

10K_0402_5%

RC6146

10K_0402_5%

RC6138

10K_0402_5%

AGPIO5

25W@

RC6146

35W@

10K_0402_5%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

AGPIO3 AGPIO4

L L

RC6171

EA@

10K_0402_5%

RC6169

VX@

10K_0402_5%

Compal Secret Data

Deciphered Date

D

10K_0402_5%

AGPIO3 AGPIO4AGPIO7

10K_0402_5%

RC6170

RC6171

EJ

EA

HL

VX

LH

+3VALW+3VALW

12

10K_0402_5%

12

10K_0402_5%

RC6168

RC6169

12

EA@

12

EJ@

VX@

EJ@

L

H L

H H

RC6172

RX540@

10K_0402_5%

RC6134

RX540@

10K_0402_5%

RC619

10K_0402_5%

RC6173

10K_0402_5%

AGPIO10 AGPIO11

RX550@

10K_0402_5%

Title

FP5_(4/7)_GPIO/HDA/STRAP

Size

Document Number Re v

Custom

Date : Sheet of

L

R535

L

RX540

H

RX550

RX565

+3VALW

12

RX565@

RC6172

RC619

10K_0402_5%

12

R535@

RC6173

RC6134

10K_0402_5%

Compal Electronics, Inc.

DH5AV_JV_0V_LA-G021P

E

9 48Monday, December 25, 2017

1.B

A

B

C

D

E

Main Func = CPU

UC1E

SW PU/PD

M.2 WLAN/BT

GBE LAN

M.2 WWAN

M.2 WLAN

PCIE X4 DT SLOT

M.2 PCIE SSD

EVAL GFX SLOT

USB_0_DP0

USB_0_DM0

USB_0_DP1

USB_0_DM1

USB_0_DP2

USB_0_DM2

USB_0_DP3

USB_0_DM3

USB_1_DP0

USB_1_DM0

USB_1_DP1

USB_1_DM1

USBC_I2C_SCL

USBC_I2C_SDA

USB_OC0_L/AGPIO16

USB_OC1_L/AGPIO17

USB_OC2_L/AGPIO18

USB_OC3_L/AGPIO24

AGPIO14/USB_OC4_L

AGPIO13/USB_OC5_L

CLK/LPC/EMMC/SD/SPI/eSPI/ UART

FP5 REV 0.90 PART 5 OF 13

Controller 0

Controller 1

SW PU/PD

FP5 REV 0.90

PART 10 OF 13

SW PU/PD

FP5_BGA_1140P

UC1J

USB

Port 0

Port 3

FP5_BGA_1140P

EGPIO70/SD_CLK

LPC_PD_L/SD_CMD/AGPIO21

LAD0/SD_DATA0/EGPIO104

LAD1/SD_DATA1/EGPIO105

LAD2/SD_DATA2/EGPIO106

LAD3/SD_DATA3/EGPIO107

LPCCLK0/EGPIO74

LPC_CLKRUN_L/AGPIO88

LPCCLK1/EGPIO75

SERIRQ/AGPIO87

LFRAME_L/EGPIO109

LPC_RST_L/SD_WP_L/AGPIO32

AGPIO68/SD_CD

LPC_PME_L/SD_PWR_CTRL/AGPIO22

SPI_ROM_REQ/EGPIO67

SPI_ROM_GNT/AGPIO76

ESPI_RESET_L/KBRST_L/AGPIO129

ESPI_ALERT_L/LDRQ0_L/EGPIO108

SPI_CLK/ESPI_CLK

SPI_DI/ESPI_DATA

SPI_WP_L/ESPI_DAT2

SPI_HOLD_L/ESPI_DAT3

SPI_CS1_L/EGPIO118

SPI_CS2_L/ESPI_CS_L/AGPIO30

SPI_CS3_L/AGPIO31

SPI_TPM_CS_L/AGPIO29

UART0_RXD/EGPIO136

UART0_TXD/EGPIO138

UART0_RTS_L/UART2_RXD/EGPIO137

UART0_CTS_L/UART2_TXD/EGPIO135

UART0_INTR/AGPIO139

EGPIO141/UART1_RXD

EGPIO143/UART1_TXD

EGPIO142/UART1_RTS_L/UART3_RXD

EGPIO140/UART1_CTS_L/UART3_TXD

AGPIO144/UART1_INTR

USBC0_A2/USB_0_TXP0/DP3_TXP2

USBC0_A3/USB_0_TXN0/DP3_TXN2

USBC0_B11/USB_0_RXP0/DP3_TXP3

USBC0_B10/USB_0_RXN0/DP3_TXN3

USBC0_B2/DP3_TXP1

USBC0_B3/DP3_TXN1

USBC0_A11/DP3_TXP0

USBC0_A10/DP3_TXN0

USB_0_TXP1

Port 1

USB_0_TXN1

USB_0_RXP1

USB_0_RXN1

USB_0_TXP2

Port 2

USB_0_TXN2

USB_0_RXP2

USB_0_RXN2

USBC1_A2/USB_0_TXP3/DP2_TXP2

USBC1_A3/USB_0_TXN3/DP2_TXN2

USBC1_B11/USB_0_RXP3/DP2_TXP3

USBC1_B10/USB_0_RXN3/DP2_TXN3

USBC1_B2/DP2_TXP1

USBC1_B3/DP2_TXN1

USBC1_A11/DP2_TXP0

USBC1_A10/DP2_TXN0

USB_1_TXP0

Port 4

USB_1_TXN0

USB_1_RXP0

USB_1_RXN0

SPI_DO

BD13 BB14 BB12 BC11 BB15 BC15 BA15 BC13 BB13 BC12 BA12

BD11 BA11 BA13

BC8 BB8

BB11 BC6

BB7 BA9 BB10 BA10 BC10 BC9 BA8 BA6 BD8

BA16 BB18 BC17 BA18 BD18

BC18 BA17 BC16 BB19 BB16

AD2 AD4

AC2 AC4

AF4 AF2

AE3 AE1

AG3 AG1

AJ9 AJ8

AG4 AG2

AG7 AG6

AA2 AA4

Y1 Y3

AC1 AC3

AB2 AB4

AH4 AH2

AK7 AK6

LPCPD# LPC_AD0

LPC_AD1 LPC_AD2 LPC_AD3 LPC_CLK0

CLKRUN# LPC_CLK1

SERIRQ LPC_FRAME#

LPC_RST_A#

EC_SCI#

KBRST#

APU_SPI_CLK APU_SPI_MISO APU_SPI_MOSI APU_SPI_WP# APU_SPI_HOLD# APU_SPI_CS#1

APU_SPI_TPMCS#

UART_0_ARXD_DTXD UART_0_ATXD_DRXD

PE_GPIO1 DGPU_PWROK

PE_GPIO0

USB3_ATX_DRX_P0 USB3_ATX_DRX_N0

USB3_ARX_DTX_P0 USB3_ARX_DTX_N0

USB3_ATX_DRX_P2 USB3_ATX_DRX_N2

USB3_ARX_DTX_P2 USB3_ARX_DTX_N2

USB3_ATX_DRX_P3 USB3_ATX_DRX_N3

USB3_ARX_DTX_P3 USB3_ARX_DTX_N3

T103TP@

1 2

RC449 22_0402_5%

1 2

RC6163 22_0402_5%TPM@

EC_SCI# <30>

KBRST# <30>

RC74 10_0402_5%

1 2

EMC@

UART_0_ARXD_DTXD <27>

UART_0_ATXD_DRXD <27>

PE_GPIO1 <35>

DGPU_PWROK <44,45>

PE_GPIO0 <15>

USB3_ATX_DRX_P0 <33> USB3_ATX_DRX_N0 <33>

USB3_ARX_DTX_P0 <33> USB3_ARX_DTX_N0 <33>

USB3_ATX_DRX_P2 <34> USB3_ATX_DRX_N2 <34>

USB3_ARX_DTX_P2 <34> USB3_ARX_DTX_N2 <34>

USB3_ATX_DRX_P3 <34> USB3_ATX_DRX_N3 <34>

USB3_ARX_DTX_P3 <34> USB3_ARX_DTX_N3 <34>

LPC_AD0 <31>

LPC_AD1 <31>

LPC_AD2 <31>

LPC_AD3 <31>

LPC_CLK0_EC <30> CLKRUN# <31> LPC_CLK1_TPM <31> SERIRQ <30,31>

LPC_FRAME# <30,31>

APU_SPI_CLK_R < 9>

8MB SPI ROM

Type-A MB CHG

Type-C MB

APU_SPI_CS#1 APU_SPI_MISO APU_SPI_WP#

LPC_RST_A#

EC_SCI#

PE_GPIO1

APU_SPI_CLK_R

RC602 33_0402_5%

1 2

RC6154 10K_0402_5%

RC6166 10K_0402_5%@

APU_SPI_MISO

RC1706 10K _0402_5%@

APU_SPI_WP#

APU_SPI_HOLD#

APU_SPI_CS#1

APU_SPI_TPMCS#

+1.8VALW

+1.8VS

UC7

1

CS#

2 3 4

VCC

DO(IO1)

HOLD#(IO3)

WP#(IO2)

CLK

GND

DI(IO0)

W25Q64FWSS IQ_SOIC_8P

SA00006ZV10

1 2

@EMC@

RC680 10_0402_5%

LPC_RST# <30,31>

1

CC615 150P_0402_50V8J

2

+3VALW

12

+3VS

12

1 2

RC640 10K_0402_5 %

1 2

RC642 10K_0402_5 %

1 2

RC639 10K_0402_5 %

1 2

RC646 10K_0402_5 %@

RC1672 0_0603_5%

1 2

RS@

RC1700 0_0603_5%

1 2

@

+SPI_VCC

8

APU_SPI_HOLD#

7

APU_SPI_CLK_R

6

APU_SPI_MOSI

5

@EMC@

1 2

CC636 10P_0402_50V8J

+SPI_VCC

@

2

CC635

0.1U_0201_10V6K

1

T115 TP@

CLKREQ_PCIE#0

CLKREQ_PCIE#4 CLKREQ_PCIE#5 CLKREQ_PEG#6

CLK_PCIE_P0 CLK_PCIE_N0

CLK_PCIE_P4 CLK_PCIE_N4

CLK_PCIE_P5 CLK_PCIE_N5

CLK_PEG_P6 CLK_PEG_N6

48M_X1

48M_X2

RTCCLK

32K_X1

32K_X2

AV18

CLK_REQ0_L/SATA_IS0_L/SATA_ZP0_L/AGPIO92

AN19

CLK_REQ1_L/AGPIO115

AP19

CLK_REQ2_L/AGPIO116

AT19

CLK_REQ3_L/SATA_IS1_L/SATA_ZP1_L/EGPIO131

AU19

CLK_REQ4_L/OSCIN/EGPIO132

AW18

CLK_REQ5_L/EGPIO120

AW19

CLK_REQ6_L/EGPIO121

AK1

GPP_CLK0P

AK3

GPP_CLK0N

AM2

GPP_CLK1P

AM4

GPP_CLK1N

AM1

GPP_CLK2P

AM3

GPP_CLK2N

AL2

GPP_CLK3P

AL4

GPP_CLK3N

AN2

GPP_CLK4P

AN4

GPP_CLK4N

AN3

GPP_CLK5P

AP2

GPP_CLK5N

AJ2

GPP_CLK6P

AJ4

GPP_CLK6N

AJ3

48M_OSC

BB3

X48M_X1

BA5

X48M_X2

AF8

RSVD_76

AF9

RSVD_77

AW14

RTCCLK

AY1

X32K_X1

AY4

X32K_X2

@

+3VS

1 2

RC1695 10K_0402_5%

1 2

RC6149 10K_0402_5%

1 2

1 1

RC1696 10K_0402_5%

1 2

RC1697 10K_0402_5%

CLKREQ_PCIE#0 CLKREQ_PCIE#5 CLKREQ_PCIE#4 CLKREQ_PEG#6

CLKREQ_PCIE#0<28>

CLKREQ_PCIE#4<26> CLKREQ_PCIE#5<27> CLKREQ_PEG#6<16>

SSD

CLK_PCIE_P0<28> CLK_PCIE_N0<28>

48MHz CRYSTAL

48M_X2

1

YC2 48MHZ_8PF_X3S048000D81H-W

SJ10000AF00

4

1

C797

3.9P_0402_50V8C

2

YC3

CC682 18P_0402_50V8J

48M_X1

LAN

WLAN

DGP U

32K_X1

12

32K_X2

1 2

RC939

1M_0402_5%

2

3

1

C796

3.9P_0402_50V8C

2

2 2

32.768KHz CRYSTAL

SJ100001K00

32.768KHZ_12.5PF_CM31532768DZFT

12

RC914 20M_0402_5%

1

CC686 18P_0402_50V8J

2

1

2

CLK_PCIE_P4<26> CLK_PCIE_N4<26>

CLK_PCIE_P5<27> CLK_PCIE_N5<27>

CLK_PEG_P6<15> CLK_PEG_N6<15>

USB Function

+1.8VALW

1 2

3 3

RC94 4.7K_0402_5%

1 2

RC95 4.7K_0402_5%

+3VALW

1 2

RC905 100K_0402_5%@

1 2

RC6162 100K_0402_5%@

4 4

APU_USBC_SCL

APU_USBC_SDA

USB_OC0#

USB_OC2#

Type-A MB CHG

Type-A SUB

Type-C MB

WLAN/B T

CAMERA

USB Hub

USB20_P0<33> USB20_N0<33>

USB20_P1<33> USB20_N1<33>

USB20_P2<34> USB20_N2<34>

USB20_P3<27> USB20_N3<27>

USB20_P4<24> USB20_N4<24>

USB20_P5<33> USB20_N5<33>

USB_OC0#<33>

USB_OC2#<34>

USB20_P0 USB20_N0

USB20_P1 USB20_N1

USB20_P2 USB20_N2

USB20_P3 USB20_N3

USB20_P4 USB20_N4

USB20_P5 USB20_N5

APU_USBC_SCL

APU_USBC_SDA

USB_OC0#

USB_OC2#

AG10

AF12 AF11

AE10

AK10

AT12

AE7 AE6

AG9

AE9

AJ12 AJ11

AD9 AD8

AM6

AM7

AK9

AL9 AL8

AW7

@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

C

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2017/12/25 2019/12/25

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

FP5_(5/7)_CLK/USB/SPI/LPC

Size

Document Number Re v

Custom

DH5AV_JV_0V_LA-G021P

Date : Sheet of

DH5AV_JV_0V_LA-G021P

E

10 48Monday, December 25, 2017

1.B

A

B

C

D

E

Main Func = CPU

UC1F

Vo=1.5 V

UC8

SA000066U00

Vout

GND

680P_0402_ 50V7K

Vin

TDC: 53A EDC: 70A

+RTCVCC

1

CC120

+APU_CORE

SCL/MBDG: 16*22uF (BU) 1*180pF (BU)

1

2

+APU_CORE Cap place at Power Side

+RTCBATT

DC1

1

CHN202UPT _SC70-3

3

2

RC6161 1K_0402_5%

1 2

+CHGRTC

JRTC1

1

2

3

GND

4

GND

ACES_50271-00 20N-001

CONN@

SP02000RO00

TDC: 10A

+APU_CORE_SOC

SCL/MBDG: 7*22uF (BU) 1*1uF (BU)

1 1

+APU_CORE_SOC Cap place at Power Side

+1.2V +1.2V

CC1057 22U_0603_6.3V6M

CC1058 22U_0603_6.3V6M

CC1008 22U_0603_6.3V6M

CC1059 22U_0603_6.3V6M

1

2

2 2

CC1063 22U_0603_6.3V6M

CC1163 22U_0603_6.3V6M

CC1062 22U_0603_6.3V6M

CC1061 22U_0603_6.3V6M

CC1060 22U_0603_6.3V6M

1

2

All BU(on bottom side under SOC)

SCL/MBDG: 1 *22uF (BO)

+1.8VS +3VS +3VS_APU

RC1677 0_0402_5%

1 2

RS@

+VDDIO_AUDIO

CC1207 22U_0603_6.3V6M

1

2

1*1uF (BU)

CC1192 1U_0201_6.3V6M

1

2

1*180pF (BU)

SCL/MBDG: 9*22uF (BU) 2*1uF (BU) 4*0.22uF 1*180pF (BU)

CC1093 180P_0402_50V8J

CC1164 1U_0201_6.3V6M

CC1165 1U_0201_6.3V6M

1

2

CC1078 0.22U_0402_16V7K

CC1079 0.22U_0402_16V7K

CC1081 0.22U_0402_16V7K

CC1082 0.22U_0402_16V7K

1

2

2*180pF

CC1167 180P_0402_50V8J

CC1166 180P_0402_50V8J

1

2

ACROSS VDDIO AND VSS SPLIT

SCL/MBDG: 1 *22uF (BO)

RC1676 0_0402_5%

1 2

RS@

CC1137 22U_0603_6.3V6M

1

2

2*1uF (BO+BU)

CC1209 1U_0201_6.3V6M

CC1208 1U_0201_6.3V6M

1

2

+3VS_APU

+1.8VALW

BO B U BUB O BO

3 3

+1.8VS +1.8VALW + 3VALW

CC1189 22U_0603_6.3V6M

1

2

BO

CC1191 1U_0201_6.3V6M

CC1190 1U_0201_6.3V6M

1

2

BO B U

1

2

SCL/MBDG: 1 *22uF (BO) 2*1uF (BO+BU)

CC1186 22U_0603_6.3V6M

1

2

BO BUBO

SCL/MBDG: 1 *22uF (BO) 2*1uF (BO+BU)

CC1187 1U_0201_6.3V6M

CC1188 1U_0201_6.3V6M

1

2

CC1183 22U_0603_6.3V6M

1

2

SCL/MBDG: 1 *22uF (BO) 2*1uF (BO+BU)

CC1184 1U_0201_6.3V6M

CC1185 1U_0201_6.3V6M

1

2

BO BUBO

+0.9VALW

EDC: 13A

TDC: 6A

+1.2V

TDC :0.2A

+VDDIO_AUDIO

TDC :0.25A

TDC :2A

+1.8VS

TDC :0.5A

TDC :0.25A

+3VALW

TDC :1A

TDC :4A

+0.9VS

TDC :4.5uA

+RTC_APU_R

RTC OF APU

W18 W20

W28 W32

AA20 AA23 AA26 AA28 AA32 AC20 AC22 AC25 AC28 AD23 AD26 AD28 AD32 AE20 AE22 AE25 AE28 AF23 AF26 AF28 AF32 AG20 AG22 AG25 AG28

AJ20 AJ23 AJ26 AJ28 AJ32

AK28

AL28 AL32

AP12

AL18

AM17

AL20

AM19

AL19

AM18

AL17

AM16

AL14 AL15

AM14

AL13 AM12 AM13 AN12 AN13

AT11

M15 M18 M19 N16 N18 N20 P17 P19 R18 R20 T19 U18 U20 V19

Y19

T32 V28

Y22 Y25 Y28

VDDCR_SOC_1

VDDCR_SOC_2

VDDCR_SOC_3

VDDCR_SOC_4

VDDCR_SOC_5

VDDCR_SOC_6

VDDCR_SOC_7

VDDCR_SOC_8

VDDCR_SOC_9

VDDCR_SOC_10

VDDCR_SOC_11

VDDCR_SOC_12

VDDCR_SOC_13

VDDCR_SOC_14

VDDCR_SOC_15

VDDCR_SOC_16

VDDCR_SOC_17

VDDIO_MEM_S3_1

VDDIO_MEM_S3_2

VDDIO_MEM_S3_3

VDDIO_MEM_S3_4

VDDIO_MEM_S3_5

VDDIO_MEM_S3_6

VDDIO_MEM_S3_7

VDDIO_MEM_S3_8

VDDIO_MEM_S3_9

VDDIO_MEM_S3_10

VDDIO_MEM_S3_11

VDDIO_MEM_S3_12

VDDIO_MEM_S3_13

VDDIO_MEM_S3_14

VDDIO_MEM_S3_15

VDDIO_MEM_S3_16

VDDIO_MEM_S3_17

VDDIO_MEM_S3_18

VDDIO_MEM_S3_19

VDDIO_MEM_S3_20

VDDIO_MEM_S3_21

VDDIO_MEM_S3_22

VDDIO_MEM_S3_23

VDDIO_MEM_S3_24

VDDIO_MEM_S3_25

VDDIO_MEM_S3_26

VDDIO_MEM_S3_27

VDDIO_MEM_S3_28

VDDIO_MEM_S3_29

VDDIO_MEM_S3_30

VDDIO_MEM_S3_31

VDDIO_MEM_S3_32

VDDIO_MEM_S3_33

VDDIO_MEM_S3_34

VDDIO_MEM_S3_35

VDDIO_MEM_S3_36

VDDIO_MEM_S3_37

VDDIO_MEM_S3_38

VDDIO_MEM_S3_39

VDDIO_MEM_S3_40

VDDIO_AUDIO

VDD_33_1

VDD_33_2

VDD_18_1

VDD_18_2

VDD_18_S5_1

VDD_18_S5_2

VDD_33_S5_1

VDD_33_S5_2

VDDP_S5_1

VDDP_S5_2

VDDP_S5_3

VDDP_1

VDDP_2

VDDP_3

VDDP_4

VDDP_5

VDDBT_RTC_G

@

+RTC_APU_R

SCL/MBDG:

CC1178 180P_0402_50V8J

1

2

2 *22uF (BO) 8*1uF (BOx4+BUx4) 1*180pF (BU)

CC1179 22U_0603_6.3V6M

CC1180 1U_0201_6.3V6M

1

2

+0.9VS +0.9VALW

CC1168 22U_0603_6.3V6M

CC1170 1U_0201_6.3V6M

CC1171 1U_0201_6.3V6M

CC1169 22U_0603_6.3V6M

1

4 4

2

CC1173 1U_0201_6.3V6M

CC1172 1U_0201_6.3V6M

CC1176 1U_0201_6.3V6M

CC1177 1U_0201_6.3V6M

CC1174 1U_0201_6.3V6M

CC1175 1U_0201_6.3V6M

1

2

CC1181 1U_0201_6.3V6M

CC1182 1U_0201_6.3V6M

1

2

1

2

SCL/MBDG: 1 *22uF (BO) 3*1uF (BOx1+BUx2)

close to UC1

CC166

0.22U_0402 _16V7K

W=20 mils

1

1U_0201_6 .3V6M

2

CC923

1

2

0_0603_5%

CLRP1

POWER

FP5 REV 0.90 PART 6 OF 13

RC6164 1K_0402_5%

1 2

12

@

0.1U_0201_ 10V6K

FP5_BGA_1140P

+RTC_APU

CC119

G7

VDDCR_1

G10

VDDCR_2

G12

VDDCR_3

G14

VDDCR_4

H8

VDDCR_5

H11

VDDCR_6

H15

VDDCR_7

K7

VDDCR_8

K12

VDDCR_9

K14

VDDCR_10

L8

VDDCR_11

M7

VDDCR_12

M10

VDDCR_13

N14

VDDCR_14

P7

VDDCR_15

P10

VDDCR_16

P13

VDDCR_17

P15

VDDCR_18

R8

VDDCR_19

R14

VDDCR_20

R16

VDDCR_21

T7

VDDCR_22

T10

VDDCR_23

T13

VDDCR_24

T15

VDDCR_25

T17

VDDCR_26

U14

VDDCR_27

U16

VDDCR_28

V13

VDDCR_29

V15

VDDCR_30

V17

VDDCR_31

W7

VDDCR_32

W10

VDDCR_33

W14

VDDCR_34

W16

VDDCR_35

Y8

VDDCR_36

Y13

VDDCR_37

Y15

VDDCR_38

Y17

VDDCR_39

AA7

VDDCR_40

AA10

VDDCR_41

AA14

VDDCR_42

AA16

VDDCR_43

AA18

VDDCR_44

AB13

VDDCR_45

AB15

VDDCR_46

AB17

VDDCR_47

AB19

VDDCR_48

AC14

VDDCR_49

AC16

VDDCR_50

AC18

VDDCR_51

AD7

VDDCR_52

AD10

VDDCR_53

AD13

VDDCR_54

AD15

VDDCR_55

AD17

VDDCR_56

AD19

VDDCR_57

AE8

VDDCR_58

AE14

VDDCR_59

AE16

VDDCR_60

AE18

VDDCR_61

AF7

VDDCR_62

AF10

VDDCR_63

AF13

VDDCR_64

AF15

VDDCR_65

AF17

VDDCR_66

AF19

VDDCR_67

AG14

VDDCR_68

AG16

VDDCR_69

AG18

VDDCR_70

AH13

VDDCR_71

AH15

VDDCR_72

AH17

VDDCR_73

AH19

VDDCR_74

AJ7

VDDCR_75

AJ10

VDDCR_76

AJ14

VDDCR_77

AJ16

VDDCR_78

AJ18

VDDCR_79

AK13

VDDCR_80

AK15

VDDCR_81

AK17

VDDCR_82

AK19

VDDCR_83

AP2138N-1.5TR G1_SOT23-3

3

2

1

2

BOx 4

Need OPEN

BUx 4 BO BU

A

BUBO

BO

B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

for Clear CMOS

Compal Secret Data

2017/12/25 2019/12/25

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number R ev

Custom

Date : Sheet of

D

Date : Sheet of

Compal Electronics, Inc.

(6/7)_PWR

DH5AV_JV_0V_LA-G021P

E

11 48Monday, December 25, 2017

1.B

5

Main Func = CPU

N12

VSS_316

A3

VSS_1

A5

VSS_2

A7

VSS_3

A10

VSS_4

A12

VSS_5

A14

VSS_6

A16

VSS_7

A19

G16 G19 G21 G23 G26 G28 G32

A21 A23 A26 A30

C32 D16 D18 D20

E10 E11 E12 E13 E14 E15 E16 E18 E19 E20 E21 E22 E23 E25 E26 E27

F28

H13 H18 H20 H22 H25 H28

K16 K19 K21 K22 K26 K28

VSS_8

VSS_9

VSS_10

VSS_11

VSS_12

C3

VSS_13

VSS_14

VSS_15

VSS_16

VSS_17

E7

VSS_18

E8

VSS_19

VSS_20

VSS_21

VSS_22

VSS_23

VSS_24

VSS_25

VSS_26

VSS_27

VSS_28

VSS_29

VSS_30

VSS_31

VSS_32

VSS_33

VSS_34

VSS_35

F5

VSS_36

VSS_37

G1

VSS_38

G5

VSS_39

VSS_40

VSS_41

VSS_42

VSS_43

VSS_44

VSS_45

VSS_46

H5

VSS_47

VSS_48

VSS_49

VSS_50

VSS_51

VSS_52

VSS_53

K1

VSS_54

K5

VSS_55

VSS_56

VSS_57

VSS_58

VSS_59

VSS_60

VSS_61

@

D D

C C

B B

UC1G

GND

FP5 REV 0.90

PART 7 OF 13

FP5_BGA _1140P

VSS_62

VSS_63

VSS_64

VSS_65

VSS_66

VSS_67

VSS_68

VSS_69

VSS_70

VSS_71

VSS_72

VSS_73

VSS_74

VSS_75

VSS_76

VSS_77

VSS_78

VSS_79

VSS_80

VSS_81

VSS_82

VSS_83

VSS_84

VSS_85

VSS_86

VSS_87

VSS_88

VSS_89

VSS_90

VSS_91

VSS_92

VSS_93

VSS_94

VSS_95

VSS_96

VSS_97

VSS_98

VSS_99

VSS_100

VSS_101

VSS_102

VSS_103

VSS_104

VSS_105

VSS_106

VSS_107

VSS_108

VSS_109

VSS_110

VSS_111

VSS_112

VSS_113

VSS_114

VSS_115

VSS_116

VSS_117

VSS_118

VSS_119

VSS_120

VSS_121

VSS_122

VSS_123

K32 L5 L13 L15 L18 L20 L25 L28 M1 M5 M12 M21 M23 M26 M28 M32 N4 N5 N8 N11 N13 N15 N17 N19 N22 N25 N28 P1 P5 P14 P16 P18 P20 P23 P26 P28 P32 R5 R11 R12 R13 R15 R17 R19 R22 R25 R28 R30 T1 T5 T14 T16 T18 T20 T23 T26 T28 U13 U15 U17 U19 V5

UC1M

A18

CAM0_CSI2_CLOCKP

C18

CAM0_CSI2_CLOCKN

A15

CAM0_CSI2_DATAP0

C15

CAM0_CSI2_DATAN0

B16

CAM0_CSI2_DATAP1

C16

CAM0_CSI2_DATAN1

C19

CAM0_CSI2_DATAP2

B18

CAM0_CSI2_DATAN2

B17

CAM0_CSI2_DATAP3

D17

CAM0_CSI2_DATAN3

D12

CAM1_CSI2_CLOCKP

B12

CAM1_CSI2_CLOCKN

C13

CAM1_CSI2_DATAP0

A13

C12

B11

J13

CAM1_CSI2_DATAN0

CAM1_CSI2_DATAP1

CAM1_CSI2_DATAN1

RSVD_6

A A

@

5

CAMERAS

FP5 REV 0.90

PART 13 OF 13

FP5_BGA _1140P

CAM0_CLK

CAM0_I2C_SCL

CAM0_I2C_SDA

CAM0_SHUTDOWN

CAM1_CLK

CAM1_I2C_SCL

CAM1_I2C_SDA

CAM1_SHUTDOWN

CAM_PRIV_LED

CAM_IR_ILLU

B15

D15 C14

B13

B10

A11 C11

D11

D13 D10

4

V8 V11 V12 V14 V16 V18 V20 V22 V25

W1

W5 W13 W15 W17 W19 W23 W26

Y5 Y11 Y12 Y14 Y16 Y18 Y20 AA1 AA5

AA13 AA15 AA17 AA19 AB14 AB16 AB18 AB20

AC5

AC8 AC11 AC12 AC13 AC15 AC17 AC19

AD1

AD5 AD14 AD16 AD18 AD20

AE5 AE11 AE12 AE13 AE15 AE17 AE19

AF1

AF5

AF14 AF16 AF18 AF20

AG5

@

VSS_124

VSS_125

VSS_126

VSS_127

VSS_128

VSS_129

VSS_130

VSS_131

VSS_132

VSS_133

VSS_134

VSS_135

VSS_136

VSS_137

VSS_138

VSS_139

VSS_140

VSS_141

VSS_142

VSS_143

VSS_144

VSS_145

VSS_146

VSS_147

VSS_148

VSS_149

VSS_150

VSS_151

VSS_152

VSS_153

VSS_154

VSS_155

VSS_156

VSS_157

VSS_158

VSS_159

VSS_160

VSS_161

VSS_162

VSS_163

VSS_164

VSS_165

VSS_166

VSS_167

VSS_168

VSS_169

VSS_170

VSS_171

VSS_172

VSS_173

VSS_174

VSS_175

VSS_176

VSS_177

VSS_178

VSS_179

VSS_180

VSS_181

VSS_182

VSS_183

VSS_184

VSS_185

3

UC1H

GND

FP5 REV 0.90

PART 8 OF 13

FP5_BGA _1140P

VSS_186

VSS_187

VSS_188

VSS_189

VSS_190

VSS_191

VSS_192

VSS_193

VSS_194

VSS_195

VSS_196

VSS_197

VSS_198

VSS_199

VSS_200

VSS_201

VSS_202

VSS_203

VSS_204

VSS_205

VSS_206

VSS_207

VSS_208

VSS_209

VSS_210

VSS_211

VSS_212

VSS_213

VSS_214

VSS_215

VSS_216

VSS_217

VSS_218

VSS_219

VSS_220

VSS_221

VSS_222

VSS_223

VSS_224

VSS_225

VSS_226

VSS_227

VSS_228

VSS_229

VSS_230

VSS_231

VSS_232

VSS_233

VSS_234

VSS_235

VSS_236

VSS_237

VSS_238

VSS_239

VSS_240

VSS_241

VSS_242

VSS_243

VSS_244

VSS_245

VSS_246

VSS_247

AG8 AG11 AG12 AG13 AG15 AG17 AG19 AH14 AH16 AH18 AH20 AJ1 AJ5 AJ13 AJ15 AJ17 AJ19 AK5 AK8 AK11 AK12 AK14 AK16 AK18 AK20 AK22 AK25 AL1 AL5 AL7 AL10 AL12 AL16 AL23 AL26 AM5 AM8 AM15 AM20 AM22 AM25 AM28 AN1 AN5 AN7 AN10 AN15 AN18 AN21 AN23 AN26 AN28 AN32 AP5 AP8 AP13 AP15 AP18 AP20 AP25 AP28 AR1

AR5

AR7 AR12 AR14 AR16 AR19 AR21 AR26 AR28 AR32

AU5

AU8 AU11 AU13 AU15 AU18 AU20 AU22 AU25 AU28

AV1

AV5

AV7 AV10 AV12 AV14 AV16 AV19 AV21 AV23 AV26 AV28 AV32

AW5

AW28

AY6

AY7

AY8 AY10 AY11 AY12 AY13 AY14 AY15 AY16 AY18 AY19 AY20 AY21 AY22 AY23 AY25 AY26 AY27

BB1 BB20 BB32

BD3

BD7 BD10 BD12 BD14

2

1

UC1K

VSS_248

VSS_249

VSS_250

VSS_251

VSS_252

VSS_253

VSS_254

VSS_255

VSS_256

VSS_257

VSS_258

VSS_259

VSS_260

VSS_261

VSS_262

VSS_263

VSS_264

VSS_265

VSS_266

VSS_267

VSS_268

VSS_269

VSS_270

VSS_271

VSS_272

VSS_273

VSS_274

VSS_275

VSS_276

VSS_277

VSS_278

VSS_279

VSS_280

VSS_281

VSS_282

VSS_283

VSS_284

VSS_285

VSS_286

VSS_287

VSS_288

VSS_289

VSS_290

VSS_291

VSS_292

VSS_293

VSS_294

VSS_295

VSS_296

VSS_297

VSS_298

VSS_299

VSS_300

VSS_301

VSS_302

VSS_303

VSS_304

VSS_305

VSS_306

VSS_307

VSS_308

VSS_309

@

GND/RSVD

FP5 REV 0.90

PART 11 OF 13

FP5_BGA _1140P

VSS_310

VSS_311

VSS_312

VSS_313

VSS_314

VSS_315

RSVD_1

RSVD_5

RSVD_7

RSVD_8

RSVD_9

RSVD_10

RSVD_11

RSVD_12

RSVD_13

RSVD_22

RSVD_23

RSVD_30

RSVD_31

RSVD_37

RSVD_44

RSVD_49

RSVD_50

RSVD_57

RSVD_58

RSVD_59

RSVD_60

RSVD_69

RSVD_70

RSVD_71

RSVD_74

RSVD_75

RSVD_78

RSVD_79

RSVD_80

RSVD_81

RSVD_82

RSVD_83

RSVD_87

RSVD_88

RSVD_14

RSVD_84

RSVD_85

RSVD_86

BD16 BD19 BD21 BD23 BD26 BD30

B20 G3 J20 K3 K6 K20 M3 M6 M13 P6 P22 T3 T6 T29 W6 W21 W22 Y21 Y27 AA3 AA6 AC29 AD3 AD6 AF3 AF6 AF30 AJ6 AJ24 AK23 AK27 AL3 AN29 AN31

M14 AL6 AL11 AN16

UC1L

T11

RSVD_32

AC7

RSVD_66

Y9

RSVD_55

Y10

RSVD_56

W11

RSVD_47

W12

RSVD_48

V9

RSVD_38

V10

RSVD_39

AA12

RSVD_64

AC10

RSVD_68

@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

RSVD

FP5 REV 0.90

PART 12 OF 13

FP5_BGA _1140P

2017/12/ 25 2019/12/ 25

3

AA9

RSVD_62

AA8

RSVD_61

AC6

RSVD_65

AD11

RSVD_72

AC9

RSVD_67

AA11

RSVD_63

T12

RSVD_33

AD12

RSVD_73

Y6

RSVD_53

Y7

RSVD_54

W8

RSVD_45

W9

RSVD_46

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Re v

Custom

Date : Sheet o f

2

Date : Sheet o f

Compal Electronics, Inc.

FP5_(7/7)_GND/RSVD/CSI

DH5AV_JV_0V_LA-G021P

12 48Monday, December 2 5, 2017

1

1.B

A

B

C

D

E

Reverse Type-4H

2-3A to 1 DIMMs/channel

DDR_A_CLK0<7> DDR_A_CLK0#<7> DDR_A_CLK1<7>

Address : A0

1 1

+3VS

12

RD5

0_0402_5%

@

12

RD8

0_0402_5%

RS@

Layout Note: Place near JDIMM1

2 2

+1.2V

1U_0201_6.3V6M

1

2

+1.2V

10U_0603_6.3V6M

1

2

3 3

+1.2V

0.1U_0201_10V6K

2

1

12

CD2

CD10

CD61

RD7

0_0402_5%

RD6

0_0402_5%

@

DDR_A_SA2 DDR_A_SA1 DDR_A_SA0

12

RD10

0_0402_5%

RS@

RD9

0_0402_5%

RS@

Note: Check voltage tolerance of VREF_DQ at the DIMM socket

CRB use 0.1uF x12 (6 pop,6 unpop),180pF x1,100uF x2

1U_0201_6.3V6M

CD3

1

2

10U_0603_6.3V6M

CD11

1

2

0.1U_0201_10V6K

CD62

2

1

1U_0201_6.3V6M

CD4

1

2

10U_0603_6.3V6M

CD12

1

2

0.1U_0201_10V6K

CD63

2

1

1U_0201_6.3V6M

CD6

CD5

CD13

CD64

CD7

1

2

10U_0603_6.3V6M

CD14

CD15

1

2

180P_0402_50V8J

2

1

CD1

@EMC@

.1U_0402_1 6V7K

DDR4 support Even Parity check in DRAMs.

DDR_A_RST#

12

Follow MA51

1

@

+

CD18 330U_D2_2 V_Y

2

SGA00009S00 330U 2V H1.9 9mohm POLY

CD65

DDR_A_CLK1#<7>

DDR_A_CKE0<7> DDR_A_CKE1<7>

DDR_A_CS0#<7> DDR_A_CS1#<7>

DDR_A_ODT0<7> DDR_A_ODT1<7>

DDR_A_BG0<7>

DDR_A_BG1<7> DDR_A_BA0<7> DDR_A_BA1<7>

DDR_A_MA[13..0]<7>

DDR_A_MA14_W E#<7> DDR_A_MA15_CAS#<7> DDR_A_MA16_RAS#<7>

DDR_A_ACT#<7>

DDR_A_PAR<7> DDR_A_ALERT#<7>

DDR_A_EVENT#<7>

DDR_A_RST#<7 >

SMB_0_SDA< 9,14> SMB_0_SCL<9,14>

DDR_A_DM[7..0]<7>

DDR_A_CLK0 DDR_A_CLK0# DDR_A_CLK1 DDR_A_CLK1#

DDR_A_CKE0 DDR_A_CKE1

DDR_A_CS0# DDR_A_CS1#

DDR_A_ODT0 DDR_A_ODT1

DDR_A_BG0 DDR_A_BG1 DDR_A_BA0 DDR_A_BA1

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12

DDR_A_MA13 DDR_A_MA14_W E# DDR_A_MA15_CAS# DDR_A_MA16_RAS#

DDR_A_ACT#

DDR_A_PAR DDR_A_ALERT# DDR_A_EVENT# DDR_A_RST#

SMB_0_SDA SMB_0_SCL

DDR_A_SA2 DDR_A_SA1 DDR_A_SA0

DDR_A_DM0

DDR_A_DM1

DDR_A_DM2

DDR_A_DM3

DDR_A_DM4

DDR_A_DM5

DDR_A_DM6

DDR_A_DM7

JDIMM1A

REVERSE

137

CK0(T)

139

CK0#(C)

138

CK1(T)

140

CK1#(C)

109

CKE0

110

CKE1

149

S0#

157

S1#

162

S2#/C0

165

S3#/C1

155

ODT0

161

ODT1

115

BG0

113

BG1

150

BA0

145

BA1

144

A0

133

A1

132

A2

131

A3

128

A4

126

A5

127

A6

122

A7

125

A8

121

A9

146

A10_AP

120

A11

119

A12

158

A13

151

A14_WE#

156

A15_CAS#

152

A16_RAS#

114

ACT#

143

PARITY

116

ALERT#

134

EVENT#

108

RESET#

254

SDA

253

SCL

166

SA2

260

SA1

256

SA0

92

CB0_NC

91

CB1_NC

101

CB2_NC

105

CB3_NC

88

CB4_NC

87

CB5_NC

100

CB6_NC

104

CB7_NC

97

DQS8(T)

95

DQS8#(C)

12

DM0#/DBI0#

33

DM1#/DBI1#

54

DM2#/DBI2#

75

DM3#/DBI3#

178

DM4#/DBI4#

199

DM5#/DBI5#

220

DM6#/DBI6#

241

DM7#/DBI7#

96

DM8#/DBI8#

LOTES_ADDR02 06-P001A

CONN@

DQS0(T)

DQS0#(C)

DQ10 DQ11 DQ12 DQ13 DQ14 DQ15

DQS1(T)

DQS1#(C)

DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23

DQS2(T)

DQS2#(C)

DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

DQS3(T)

DQS3#(C)

DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39

DQS4(T)

DQS4#(C)

DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47

DQS5(T)

DQS5#(C)

DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55

DQS6(T)

DQS6#(C)

DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

DQS7(T)

DQS7#(C)

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7

DQ8 DQ9

DDR_A_DQ1

7

DDR_A_DQ2

20

DDR_A_DQ3

21

DDR_A_DQ4

4

DDR_A_DQ5

3

DDR_A_DQ6

16

DDR_A_DQ7

17

DDR_A_DQS0

13

DDR_A_DQS0#

11

DDR_A_DQ8

28

DDR_A_DQ9

29

DDR_A_DQ10

41

DDR_A_DQ11

42

DDR_A_DQ12

24

DDR_A_DQ13

25

DDR_A_DQ14

38

DDR_A_DQ15

37

DDR_A_DQS1

34

DDR_A_DQS1#

32

DDR_A_DQ16

50

DDR_A_DQ17

49

DDR_A_DQ18

62

DDR_A_DQ19

63

DDR_A_DQ20

46

DDR_A_DQ21

45

DDR_A_DQ22

58

DDR_A_DQ23

59

DDR_A_DQS2

55

DDR_A_DQS2#

53

DDR_A_DQ24

70

DDR_A_DQ25

71

DDR_A_DQ26

83

DDR_A_DQ27

84

DDR_A_DQ28

66

DDR_A_DQ29

67

DDR_A_DQ30

79

DDR_A_DQ31

80

DDR_A_DQS3

76

DDR_A_DQS3#

74

DDR_A_DQ32

174

DDR_A_DQ33

173

DDR_A_DQ34

187

DDR_A_DQ35

186

DDR_A_DQ36

170

DDR_A_DQ37

169

DDR_A_DQ38

183

DDR_A_DQ39

182

DDR_A_DQS4

179

DDR_A_DQS4#

177

DDR_A_DQ40

195

DDR_A_DQ41

194

DDR_A_DQ42

207

DDR_A_DQ43

208

DDR_A_DQ44

191

DDR_A_DQ45

190

DDR_A_DQ46

203

DDR_A_DQ47

204

DDR_A_DQS5

200

DDR_A_DQS5#

198

DDR_A_DQ48

216

DDR_A_DQ49

215

DDR_A_DQ50

228

DDR_A_DQ51

229

DDR_A_DQ52

211

DDR_A_DQ53

212

DDR_A_DQ54

224

DDR_A_DQ55

225

DDR_A_DQS6

221

DDR_A_DQS6#

219

DDR_A_DQ56

237

DDR_A_DQ57

236

DDR_A_DQ58

249

DDR_A_DQ59

250

DDR_A_DQ60

232

DDR_A_DQ61

233

DDR_A_DQ62

245

DDR_A_DQ63

246

DDR_A_DQS7

242

DDR_A_DQS7#

240

DDR_A_DQ0

8

DDR_A_DQ[7..0] < 7>

DDR_A_DQS0 <7> DDR_A_DQS0# <7> DDR_A_DQ[15..8] <7>

DDR_A_DQS1 <7> DDR_A_DQS1# <7> DDR_A_DQ[23..16 ] <7>

DDR_A_DQS2 <7> DDR_A_DQS2# <7> DDR_A_DQ[31..24 ] <7>

DDR_A_DQS3 <7> DDR_A_DQS3# <7> DDR_A_DQ[39..32 ] <7>

DDR_A_DQS4 <7> DDR_A_DQS4# <7> DDR_A_DQ[47..40 ] <7>

DDR_A_DQS5 <7> DDR_A_DQS5# <7> DDR_A_DQ[55..48 ] <7>

DDR_A_DQS6 <7> DDR_A_DQS6# <7>

DDR_A_DQ[63..56 ] <7>

DDR_A_DQS7 <7> DDR_A_DQS7# <7>

Follow CRB design

+1.2V

RD3

1K_0402_1%

RD4

1K_0402_1%

1 2

CD20 4.7U_0402_6.3V6M

1 2

15mil

CD22 0.1U_0201_10V6K

1

2

+VREFA_CA

CD21 0.1U_0201_10V6K

CD19 1000P_0402_50V7K

2

1

2

Place near to SO-DIMM connector.

+1.2V +1.2V

JDIMM1B

REVERSE

111

VDD1

112 117 118 123 124 129 130

+3VS

135 136

255

164

1 2 5 6

9 10 14 15 18 19 22 23 26 27 30 31 35 36 39 40 43 44 47 48 51 52 56 57 60 61 64 65 68 69 72 73 77 78 81 82 85 86 89 90 93 94 98

262

Layout Note: Place near JDIMM1.258

VDD11

VDD2

VDD12

VDD3

VDD13

VDD4

VDD14

VDD5

VDD15

VDD6

VDD16

VDD7

VDD17

VDD8

VDD18

VDD9

VDD19

VDD10

VDDSPD

VTT

VREFCA

VPP1 VPP2

VSS

GND

LOTES_ADDR02 06-P001A

CONN@

GND

141 142 147 148 153 154 159 160

+0.6VS

163

258

257 259

99 102 103 106 107 167 168 171 172 175 176 180 181 184 185 188 189 192 193 196 197 201 202 205 206 209 210 213 214 217 218 222 223 226 227 230 231 234 235 238 239 243 244 247 248 251 252

261

+2.5V

CD31 1U_0201_6.3V6M

1

2

CRB use 1uF x1

CRB use 4.7uF x1,0.1uF x1

Layout Note: Place near JDIMM1.257,259

CRB use 0.1uF x2,180pF x1

4 4

10U_0603_6.3V6M

1

2

+2.5V

1U_0201_6.3V6M

10U_0603_6.3V6M

CD23

CD25

CD24

1

2

A

Layout Note: Place near JDIMM1.255

CRB use 1uF x1

+3VS

1U_0201_6.3V6M

CD26

1

2

1

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2017/12/25 2019/12/25

Compal Secret Data

Deciphered Date

Title

Size Document Number R ev

Custom

DH5AV_JV_0V_LA-G021P

Date : Sheet of

D

Date : Sheet of

+0.6VS

10U_0603_6.3V6M

CD27

CD28

1

2

Compal Electronics, Inc.

DDR4_SO-DIMM

1U_0201_6.3V6M

CD30

CD29

1

2

13 48Monday, December 25, 2017

E

13 48Monday, December 25, 2017

1.B

A

B

C

D

E

Reverse Type-8H

2-3A to 1 DIMMs/channel

DDR_B_CLK 0<7> DDR_B_CLK 0#<7> DDR_B_CLK 1<7>

Address : A2

1 1

+3VS

RD244

12

RD247

0_0402_5%

@

12

RD252

0_0402_5%

RS@

Layout Note: Place near JDIMM2

2 2

+1.2V

1U_0201_6.3V6M

CD86

1

2

+1.2V

10U_0603_6.3V6M

CD82

1

2

3 3

+1.2V

0.1U_0201_10V6K CD91

2

1

10K_0402_5%

12

RD248

0_0402_5%

@

DDR_B_SA2 DDR_B_SA1 DDR_B_SA0

12

RD249

0_0402_5%

RD246

0_0402_5%

RS@

@

Note: Check voltage tolerance of VREF_DQ at the DIMM socket

CRB use 0.1uF x12 (6 pop,6 unpop),180pF x1,100uF x2

1U_0201_6.3V6M

1

2

10U_0603_6.3V6M

1

2

0.1U_0201_10V6K

2

1

1U_0201_6.3V6M

CD78

CD67

1

2

10U_0603_6.3V6M

CD90

CD96

1

2

0.1U_0201_10V6K

CD94

CD97

2

1

1U_0201_6.3V6M

CD93

CD77

CD66

CD81

CD71

1

2

10U_0603_6.3V6M

CD68

CD88

1

2

180P_0402_50V8J

CD85

2

1

CD73

@EMC@

.1U_0402_1 6V7K

12

DDR_B_RST #

DDR_B_CLK 1#<7>

DDR_B_CKE0<7> DDR_B_CKE1<7>

DDR_B_CS0 #<7> DDR_B_CS1 #<7>

DDR_B_ODT 0<7> DDR_B_ODT 1<7>

DDR_B_BG0<7>

DDR_B_BG1<7> DDR_B_BA0< 7> DDR_B_BA1< 7>

DDR_B_MA[13..0]<7>

DDR_B_MA14_ WE#<7> DDR_B_MA15_ CAS#<7> DDR_B_MA16_ RAS#<7>

DDR_B_ACT#<7 >

DDR_B_PAR<7> DDR_B_ALERT #<7>

DDR_B_EVENT #<7>

DDR_B_RST #<7>

SMB_0_SDA< 9,13> SMB_0_SCL<9,13>

DDR_B_DM[7 ..0]<7>

DDR_B_CLK 0 DDR_B_CLK 0# DDR_B_CLK 1 DDR_B_CLK 1#

DDR_B_CKE0 DDR_B_CKE1

DDR_B_CS0 # DDR_B_CS1 #

DDR_B_ODT 0 DDR_B_ODT 1

DDR_B_BG0 DDR_B_BG1 DDR_B_BA0 DDR_B_BA1

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12

DDR_B_MA13 DDR_B_MA14_ WE# DDR_B_MA15_ CAS# DDR_B_MA16_ RAS#

DDR_B_ACT#

DDR_B_PAR DDR_B_ALERT # DDR_B_EVENT # DDR_B_RST #

SMB_0_SDA SMB_0_SCL

DDR_B_SA2 DDR_B_SA1 DDR_B_SA0

DDR_B_DM0

DDR_B_DM1

DDR_B_DM2

DDR_B_DM3

DDR_B_DM4

DDR_B_DM5

DDR_B_DM6

DDR_B_DM7

JDIMM2A

RESERVE

137

CK0(T)

139

CK0#(C)

138

CK1(T)

140

CK1#(C)

109

CKE0

110

CKE1

149

S0#

157

S1#

162

S2#/C0

165

S3#/C1

155

ODT0

161

ODT1

115

BG0

113

BG1

150

BA0

145

BA1

144

A0

133

A1

132

A2

131

A3

128

A4

126

A5

127

A6

122

A7

125

A8

121

A9

146

A10_AP

120

A11

119

A12

158

A13

151

A14_WE#

156

A15_CAS#

152

A16_RAS#

114

ACT#

143

PARITY

116

ALERT#

134

EVENT#

108

RESET#

254

SDA

253

SCL

166

SA2

260

SA1

256

SA0

92

CB0_NC

91

CB1_NC

101

CB2_NC

105

CB3_NC

88

CB4_NC

87

CB5_NC

100

CB6_NC

104

CB7_NC

97

DQS8(T)

95

DQS8#(C)

12

DM0#/DBI0#

33

DM1#/DBI1#

54

DM2#/DBI2#

75

DM3#/DBI3#

178

DM4#/DBI4#

199

DM5#/DBI5#

220

DM6#/DBI6#

241

DM7#/DBI7#

96

DM8#/DBI8#

LOTES_ADDR00 70-P009A

CONN@

DQS0(T)

DQS0#(C)

DQ10 DQ11 DQ12 DQ13 DQ14 DQ15

DQS1(T)

DQS1#(C)

DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23

DQS2(T)

DQS2#(C)

DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

DQS3(T)

DQS3#(C)

DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39

DQS4(T)

DQS4#(C)

DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47

DQS5(T)

DQS5#(C)

DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55

DQS6(T)

DQS6#(C)

DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

DQS7(T)

DQS7#(C)

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7

DQ8 DQ9

DDR_B_DQ1

7

DDR_B_DQ2

20

DDR_B_DQ3

21

DDR_B_DQ4

4

DDR_B_DQ5

3

DDR_B_DQ6

16

DDR_B_DQ7

17

DDR_B_DQS0

13

DDR_B_DQS0 #

11

DDR_B_DQ8

28

DDR_B_DQ9

29

DDR_B_DQ10

41

DDR_B_DQ11

42

DDR_B_DQ12

24

DDR_B_DQ13

25

DDR_B_DQ14

38

DDR_B_DQ15

37

DDR_B_DQS1

34

DDR_B_DQS1 #

32

DDR_B_DQ16

50

DDR_B_DQ17

49

DDR_B_DQ18

62

DDR_B_DQ19

63

DDR_B_DQ20

46

DDR_B_DQ21

45

DDR_B_DQ22

58

DDR_B_DQ23

59

DDR_B_DQS2

55

DDR_B_DQS2 #

53

DDR_B_DQ24

70

DDR_B_DQ25

71

DDR_B_DQ26

83

DDR_B_DQ27

84

DDR_B_DQ28

66

DDR_B_DQ29

67

DDR_B_DQ30

79

DDR_B_DQ31

80

DDR_B_DQS3

76

DDR_B_DQS3 #

74

DDR_B_DQ32

174

DDR_B_DQ33

173

DDR_B_DQ34

187

DDR_B_DQ35

186

DDR_B_DQ36

170

DDR_B_DQ37

169

DDR_B_DQ38

183

DDR_B_DQ39

182

DDR_B_DQS4

179

DDR_B_DQS4 #

177

DDR_B_DQ40

195

DDR_B_DQ41

194

DDR_B_DQ42

207

DDR_B_DQ43

208

DDR_B_DQ44

191

DDR_B_DQ45

190

DDR_B_DQ46

203

DDR_B_DQ47

204

DDR_B_DQS5

200

DDR_B_DQS5 #

198

DDR_B_DQ48

216

DDR_B_DQ49

215

DDR_B_DQ50

228

DDR_B_DQ51

229

DDR_B_DQ52

211

DDR_B_DQ53

212

DDR_B_DQ54

224

DDR_B_DQ55

225

DDR_B_DQS6

221

DDR_B_DQS6 #

219

DDR_B_DQ56

237

DDR_B_DQ57

236

DDR_B_DQ58

249

DDR_B_DQ59

250

DDR_B_DQ60

232

DDR_B_DQ61

233

DDR_B_DQ62

245

DDR_B_DQ63

246

DDR_B_DQS7

242

DDR_B_DQS7 #

240

DDR_B_DQ0

8

DDR_B_DQ[7..0] < 7>

DDR_B_DQS0 <7> DDR_B_DQS0 # <7> DDR_B_DQ[15 ..8] <7>

DDR_B_DQS1 <7> DDR_B_DQS1 # <7> DDR_B_DQ[23 ..16] <7>

DDR_B_DQS2 <7> DDR_B_DQS2 # <7> DDR_B_DQ[31 ..24] <7>

DDR_B_DQS3 <7> DDR_B_DQS3 # <7> DDR_B_DQ[39 ..32] <7>

DDR_B_DQS4 <7> DDR_B_DQS4 # <7> DDR_B_DQ[47 ..40] <7>

DDR_B_DQS5 <7> DDR_B_DQS5 # <7> DDR_B_DQ[55 ..48] <7>

DDR_B_DQS6 <7> DDR_B_DQS6 # <7>

DDR_B_DQ[63 ..56] <7>

DDR_B_DQS7 <7> DDR_B_DQS7 # <7>

Follow CRB design

+1.2V

RD243

1K_0402_1%

RD251

1K_0402_1%

1 2

CD84 4.7U_0402_6.3V6M

1 2

15mil

CD76 0.1U_0201_10V6K

1

2

+VREFB_CA

CD80 0.1U_0201_10V6K

CD87 1000P_0402_50V7K

2

1

2

Place near to SO-DIMM connector.

+1.2V +1.2V

JDIMM2B

RESERVE

111

VDD1

112 117 118 123 124 129 130

+3VS

135 136

255

164

1 2 5 6

9 10 14 15 18 19 22 23 26 27 30 31 35 36 39 40 43 44 47 48 51 52 56 57 60 61 64 65 68 69 72 73 77 78 81 82 85 86 89 90 93 94 98

262

Layout Note: Place near JDIMM2.258

VDD11

VDD2

VDD12

VDD3

VDD13

VDD4

VDD14

VDD5

VDD15

VDD6

VDD16

VDD7

VDD17

VDD8

VDD18

VDD9

VDD19

VDD10

VDDSPD

VTT

VREFCA

VPP1 VPP2

VSS

GND

LOTES_ADDR00 70-P009A

CONN@

GND

141 142 147 148 153 154 159 160

+0.6VS

163

258

257 259

99 102 103 106 107 167 168 171 172 175 176 180 181 184 185 188 189 192 193 196 197 201 202 205 206 209 210 213 214 217 218 222 223 226 227 230 231 234 235 238 239 243 244 247 248 251 252

261

+2.5V

CD89 1U_0201_6.3V6M

1

2

CRB use 1uF x1

CRB use 4.7uF x1,0.1uF x1

Layout Note: Place near JDIMM2.257,259

CRB use 0.1uF x2,180pF x1

4 4

10U_0603_6.3V6M

1

2

+2.5V

1U_0201_6.3V6M

10U_0603_6.3V6M

CD79

CD75

CD83

1

2

A

Layout Note: Place near JDIMM2.255

CRB use 1uF x1

+3VS

1U_0201_6.3V6M

CD95

1

2

1

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2017/12/25 2019/12/25

Compal Secret Data

Deciphered Date

Title

Size Document Number R ev

Custom

Date : Sheet of

D

Date : Sheet of

+0.6VS

1U_0201_6.3V6M

10U_0603_6.3V6M

CD74

CD70

1

2

Compal Electronics, Inc.

DDR4_SO-DIMM

DH5AV_JV_0V_LA-G021P

E

CD72

CD92

1

2

14 48Monday, December 25, 2017

1.B

5

4

3

2

1

D D

PEG_ATX _GRX_P0<6> PEG_ATX _GRX_N0<6>

PEG_ATX _GRX_P1<6> PEG_ATX _GRX_N1<6>

PEG_ATX _GRX_P2<6> PEG_ATX _GRX_N2<6>

PEG_ATX _GRX_P3<6> PEG_ATX _GRX_N3<6>

PEG_ATX _GRX_P4<6> PEG_ATX _GRX_N4<6>

PEG_ATX _GRX_P5<6> PEG_ATX _GRX_N5<6>

PEG_ATX _GRX_P6<6> PEG_ATX _GRX_N6<6>

PEG_ATX _GRX_P7<6> PEG_ATX _GRX_N7<6>

C C

B B

PEG_ATX _GRX_P0 PEG_ATX _GRX_N0

PEG_ATX _GRX_P1 PEG_ATX _GRX_N1

PEG_ATX _GRX_P2 PEG_ATX _GRX_N2

PEG_ATX _GRX_P3 PEG_ATX _GRX_N3

PEG_ATX _GRX_P4 PEG_ATX _GRX_N4

PEG_ATX _GRX_P5 PEG_ATX _GRX_N5

PEG_ATX _GRX_P6 PEG_ATX _GRX_N6

PEG_ATX _GRX_P7 PEG_ATX _GRX_N7

1 2 1 2

CV312 0.2 2U_0402_16V7 KDIS@ CV306 0.2 2U_0402_16V7 KDIS@

CV308 0.2 2U_0402_16V7 KDIS@ CV305 0.2 2U_0402_16V7 KDIS@

CV307 0.2 2U_0402_16V7 KDIS@ CV309 0.2 2U_0402_16V7 KDIS@

CV313 0.2 2U_0402_16V7 KDIS@ CV304 0.2 2U_0402_16V7 KDIS@

CV2710 0.22U_0 402_16V7KT1DIS@ CV2707 0.22U_0 402_16V7KT1DIS@

CV2711 0.22U_0 402_16V7KT1DIS@ CV2709 0.22U_0 402_16V7KT1DIS@

CV2717 0.22U_0 402_16V7KT1DIS@ CV2714 0.22U_0 402_16V7KT1DIS@

CV2704 0.22U_0 402_16V7KT1DIS@ CV2706 0.22U_0 402_16V7KT1DIS@

CLK_PEG _P6<10> CLK_PEG _N6<10>

PEG_ATX _C_GRX_P0 PEG_ATX _C_GRX_N0

PEG_ATX _C_GRX_P1 PEG_ATX _C_GRX_N1

PEG_ATX _C_GRX_P2 PEG_ATX _C_GRX_N2

PEG_ATX _C_GRX_P3 PEG_ATX _C_GRX_N3

PEG_ATX _C_GRX_P4 PEG_ATX _C_GRX_N4

PEG_ATX _C_GRX_P5 PEG_ATX _C_GRX_N5

PEG_ATX _C_GRX_P6 PEG_ATX _C_GRX_N6

PEG_ATX _C_GRX_P7 PEG_ATX _C_GRX_N7

CLK_PEG _P6 CLK_PEG _N6

APU_PCIE_ RST#<9,26,27,2 8>

PE_GPIO0<10>

UV1B

@

AT41 AT40

AR41 AR40

AP41 AP40

AM41 AM40

AL41 AL40

AK41 AK40

AJ41 AJ40

AH41 AH40

AV33 AU33

symbol2

PCIE_RX0P PCIE_RX0N

PCIE_RX1P PCIE_RX1N

PCIE_RX2P PCIE_RX2N

PCIE_RX3P PCIE_RX3N

PCIE_RX4P PCIE_RX4N

PCIE_RX5P PCIE_RX5N

PCIE_RX6P PCIE_RX6N

PCIE_RX7P PCIE_RX7N

PCIE_REFCLKP PCIE_REFCLKN

REV 0.91

2160896 088A1R16M_FC BGA769P-NH

1

2

12

RV370

2.2K_040 2_5%

DIS@

PCIE_TX0P PCIE_TX0N

PCIE_TX1P PCIE_TX1N

PCIE_TX2P PCIE_TX2N

PCIE_TX3P PCIE_TX3N

PCIE_TX4P PCIE_TX4N

PCIE_TX5P PCIE_TX5N

PCIE_TX6P PCIE_TX6N

PCIE_TX7P PCIE_TX7N

PCIE_ZVSS

AV35 AU35

AU38 AU39

AR37 AR38

AN37 AN38

AL37 AL38

AJ37 AJ38

AG37 AG38

AE37 AE38

AV41

PERSTB

AC41

PX_EN

AU41

+3VSDGP U

UV2 MC74VHC 1G08DFT2G_SC 70-5

5

DIS@

P

IN1

4

O

IN2

G

3

PEG_ARX _C_GTX_P0 PEG_ARX _C_GTX_N0

PEG_ARX _C_GTX_P1 PEG_ARX _C_GTX_N1

PEG_ARX _C_GTX_P2 PEG_ARX _C_GTX_N2

PEG_ARX _C_GTX_P3 PEG_ARX _C_GTX_N3

PEG_ARX _C_GTX_P4 PEG_ARX _C_GTX_N4

PEG_ARX _C_GTX_P5 PEG_ARX _C_GTX_N5

PEG_ARX _C_GTX_P6 PEG_ARX _C_GTX_N6

PEG_ARX _C_GTX_P7 PEG_ARX _C_GTX_N7

PLT_RST _VGA#

PX_EN

1

TP@

For BACO mode(AMD PowerXpress) use, NC if not use

1 2

SA00000OH00

12

RV4 100K_04 02_5%

DIS@

T218

RV371

DIS@

200_040 2_1%

PLT_RST _VGA#

1 2 1 2

CV1 0.22U_0402 _16V7KDIS@ CV2 0.22U_0402 _16V7KDIS@

CV3 0.22U_0402 _16V7KDIS@ CV4 0.22U_0402 _16V7KDIS@

CV5 0.22U_0402 _16V7KDIS@ CV6 0.22U_0402 _16V7KDIS@

CV7 0.22U_0402 _16V7KDIS@ CV8 0.22U_0402 _16V7KDIS@

CV2715 0.22U_0 402_16V7KT1DIS@ CV2708 0.22U_0 402_16V7KT1DIS@

CV2713 0.22U_0 402_16V7KT1DIS@ CV2703 0.22U_0 402_16V7KT1DIS@

CV2705 0.22U_0 402_16V7KT1DIS@ CV2712 0.22U_0 402_16V7KT1DIS@

CV2716 0.22U_0 402_16V7KT1DIS@ CV2702 0.22U_0 402_16V7KT1DIS@

PEG_ARX _GTX_P0 PEG_ARX _GTX_N0

PEG_ARX _GTX_P1 PEG_ARX _GTX_N1

PEG_ARX _GTX_P2 PEG_ARX _GTX_N2

PEG_ARX _GTX_P3 PEG_ARX _GTX_N3

PEG_ARX _GTX_P4 PEG_ARX _GTX_N4

PEG_ARX _GTX_P5 PEG_ARX _GTX_N5

PEG_ARX _GTX_P6 PEG_ARX _GTX_N6

PEG_ARX _GTX_P7 PEG_ARX _GTX_N7

PEG_ARX _GTX_P0 <6> PEG_ARX _GTX_N0 <6 >

PEG_ARX _GTX_P1 <6> PEG_ARX _GTX_N1 <6 >

PEG_ARX _GTX_P2 <6> PEG_ARX _GTX_N2 <6 >

PEG_ARX _GTX_P3 <6> PEG_ARX _GTX_N3 <6 >

PEG_ARX _GTX_P4 <6> PEG_ARX _GTX_N4 <6 >

PEG_ARX _GTX_P5 <6> PEG_ARX _GTX_N5 <6 >

PEG_ARX _GTX_P6 <6> PEG_ARX _GTX_N6 <6 >

PEG_ARX _GTX_P7 <6> PEG_ARX _GTX_N7 <6 >

A A

Security Classification

2017/12/ 25 2019/12/ 25

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

2017/12/ 25 2019/12/ 25

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

R18M-M260/G190_(1/9)_PCIE

Size Document Number Re v

Custom

Date : Sheet o f

2

Date : Sheet o f

Compal Electronics, Inc.

DH5AV_JV_0V_LA-G021P

15 48Monday, December 2 5, 2017

1

1.B

5

+3VSDGPU

12

S

2

6 1

D

QV1A

DIS@

Vgs=1.0-2.5V

0 1 0 1

RV507 47K_0402_5%

DIS@

G

S

CV314

1U_0201_6.3V6M

Voltage Selected (V)

1.1

1.0

0.9

0.8

5

G

EC_SMB_DA2<8,30,34>

D D

EC_SMB_CK2<8,30,34>

+1.8VSDGPU

@

RV87

RV84

DIS@

10K_0402_5%

1 2

C C

@

RV88

RV89

DIS@

10K_0402_5%

1 2

2N7002KDW_SOT363-6

SB00000EO00

@

RV410

10K_0402_5%

1 2

@

RV411

10K_0402_5%

1 2

3 4

D

QV1B

DIS@

2N7002KDW_SOT363-6

SB00000EO00

GPU_SVC GPU_SVD GPU_SVT

Boot-VID Code

SVD

SVC

0 0 1 1

+1.8VSDGPU

RV412

1K_0402_5%

1

@

2

RV1653

1K_0402_5%

SCL use 47k, CRB use 4.7k AMD Confirm List_1027 use PU-47k

12

RV508 47K_0402_5%

DIS@

VGA_SMB_DA3

VGA_SMB_CK3

12

LEXA@

12

R535@

SCL PU-1k

12

CRB PU-10k/PD-1uF 56109_Compatible List: R535 PD, and Lexa PU.

DIS@

RV413

1K_0402_5%

TEST_PG_BACO

1

@

56109_Compatible List: R535 don't care, and Lexa PU.

2

CV315

1U_0201_6.3V6M

TEST_PG

LEXA Strap

+3VSDGPU

B B

12

@

RV416

5.1K_0201_1%

12

LEXA@

RV417

5.1K_0201_1%

A A

12

LEXA@

RV414

5.1K_0201_1%

12

@

RV415

5.1K_0201_1%

GPIO_2 can't use on R535

12

@

LEXA@

RV418

RV420

5.1K_0201_1%

12

@

LEXA@

RV419

RV421

5.1K_0201_1%

12

@

RV422

5.1K_0201_1%

RV423

5.1K_0201_1%

LEXA@

RV424

RV429

RV426

5.1K_0201_1%

12

@

LEXA@

RV425

RV427

RV428

5.1K_0201_1%

12

@

LEXA@

RV432

RV434

RV436

5.1K_0201_1%

12

@

LEXA@

RV431

RV433

RV435

5.1K_0201_1%

12

@

RV440

RV438

5.1K_0201_1%

12

@

RV437

5.1K_0201_1%

GPIO_0 GPIO_2 GPIO_11 GPIO_12 GPIO_13 GPIO_15 GPIO_20 GPIO_29

HSYNC VSYNC

GPIO_8 GPIO_9 GPIO_22

12

@

LEXA@

RV439

5.1K_0201_1%

4

GPU_SVC GPU_SVD

GPU_SVC<45>

GPU_SVT

GPU_SVD<45> GPU_SVT<45>

TX_HALF_SWING[0:disable,1:enabl e] BIF_GEN3_EN_A[0:disable,1:enabl e] ROM_CONFIG_[0]/MemoryApertur e ROM_CONFIG_[1]/MemoryApertur e ROM_CONFIG_[2]/MemoryApertur e Reserved [PD for default] TX_DEEMPH_EN[0:disable,1:enable ] BIF_VGA_DIS[0:VGA,1:Headless ] Special Usage[1] GPUdefault Special Usage[0] GPUdefault BIF_CLK_PM_EN[0:disable,1:enabl e] Reserved [PD for production] BIOS_ROM_EN[0:disable,1:enabl e]

1U_0201_6.3V6M

1 2

RV155 0_0 402_5%DIS@

1 2

RV156 0_0 402_5%DIS@

1 2

RV157 0_0 402_5%DIS@

DIS@

CV26

+3VSDGPU

1

2

VGA_SMB_CK3 VGA_SMB_DA3

TEST_PG TEST_PG_BACO

10mA

UV1E

@

AM31

VDD_33

GPIO_5_REG_HOT_AC_BATT

GPIO_16_8P_DETECT

GPIO_17_THERMAL_INT

AC35

SCL

AC34

SDA

AW40

SMBCLK

AW41

SMBDAT

AU17

GPIO_SVC

AV17

GPIO_SVD

AR17

GPIO_SVT

AN34

DDCVGACLK

AP31

DDCVGADATA

AY13

TEST_PG

BA13

TEST_PG_BACO

K41

RSVD#K41

R34

RSVD#R34

REV 0.91

2160896088A1R16M_FCBGA769P-NH

R535 Strap

Resistor Divider Lookup Lable

0402 1% resistors are equired

R_pd (ohm)R_pu (ohm)

NC

4.75k

8.45k

2k

4.53k

2k

6.98k

4.99k

4.53k

4.99k

3.24k

5.62k

3.4k

10k

NC

4.75k

Capacitor Divider Lookup Lable

Cap (nF) Bitd [5:4]

680nF

00

82nF

01

10nF 10

NC

11

3

symbol5

GPIO_6_TACH

GPIO_8_ROMSO

GPIO_9_ROMSI

GPIO_10_ROMSCK

GPIO_11 GPIO_12 GPIO_13

GPIO_14_HPD2

GPIO_15

GPIO_18_HPD3

GPIO_19_CTF

GPIO_20 GPIO_21

GPIO_22_ROMCSB

GPIO_29

GPIO_30 GENERICA GENERICB

GENERICC

GENERICD GENERICE_HPD4 GENERICF_HPD5

GENERICG

CLKREQB

BL_ENABLE

BL_PWM_DIM

SWAPLOCKA SWAPLOCKB

GENLK_CLK

GENLK_VSYNC

Bitd [3:1]

GPIO_0 GPIO_1 GPIO_2

HPD1

WAKEB

DIGON

HSYNC VSYNC

000

001

010

011

100

101

110

111

2

Function Support Pin

AC/DC Mode H:AC L:DC

Thermal VR_HOT#

GPIO_0

W40 AA40

GPIO_2

AA35

VGA_AC_BATT

AA34

GPIO_6_TACH#

U35

GPIO_8

AP25

GPIO_9

AM25

GPIO_10

AM27

GPIO_11

W41

GPIO_12

Y40

GPIO_13

Y41 AU21

GPIO_15

AA41 U34 R37 AV25

GPIO_19_CTF

R38

GPIO_20

AB40

GPIO_21_PCC#

AB41

GPIO_22

AP27

GPIO_29

W37 W38

PLL_ANALOG_IN

BA38

PS_1

AV29

PS_2

AU31

PS_3

AV31 AU25 AV23

PS_0

AM29

AV21

CLKREQ_PEG#6_R

AV40 AU40

WAKEB

AC40

AC37 AC38

W34

HSYNC

W35

VSYNC

AG34 AE34 AR29 AP29

PS_0[3:1]=001

PS_0[5:4]=11

PS_0 PS_1 PS_2 PS_3

0.68U_0402_10V

1 2

RV409 5.1 K_0402_1%

DIS@

1 2

RV1652 5.1K_0402_1%

DIS@

1 2

RV1644 33_0402_5%@

1 2

RV1645 33_0402_5%@

1 2

RV1646 33_0402_5%@

1

TP@

T237

1

TP@

T239

1 2

RV91 5.1K_0402_1%

DIS@

1 2

RV1647 33_0402_5%@

1

TP@

T231

1

TP@

T241

1

TP@

T240

1

TP@

T234

RV153 0_0402_5%

RV368 10K_0402_5%

+1.8VSDGPU +1.8VSDGPU +1.8V SDGPU +1.8VSDGPU

12

R535@

RV8

8.45K_0402_1%

12

1

R535@

@

RV9

CV29

2K_0402_1%

2

Strap Name :

PS_0[1] ROM_CONFIG[0]

PS_0[2] ROM_CONFIG[1]

PS_0[3] ROM_CONFIG[2]

PS_0[4] N/A

PS_0[5] AUD_PORT_CONN_PINSTRAP[0]

+3VSDGPU

GPIO_8_ROMSO GPIO_9_ROMSI GPIO_10_ROMSCK

VGA_AC_BATT

+3VSDGPU

GPIO_22_ROMCSb

12

@

12

CLKREQ_PEG#6 <10>

PS_1[3:1]=001

PS_1[5:4]=11

CV28

0.68U_0402_10V

12

R535@

RV11

8.45K_0402_1%

12

1

@

R535@

RV12 2K_0402_1%

2

GPIO_21_PCC#

GPIO_6_TACH#

GPIO_19_CTF

Strap Name :

PS_1[1] STRAP_BIF_GEN3_EN_A

PS_1[2] TRAP_BIF_CLK_PM_EN

PS_1[3] N/A

PS_1[4] STRAP_TX_CFG_DRV_FULL_SWING

PS_1[5] STRAP_TX_DEEMPH_EN

(Fan tachometer)

Peak Current Control

RV1649 0_0402_5%

R535@

RV1651 0_0402_5%

@

RV1650 0_0402_5%

LEXA@

GPIO_22_ROMCSb GPIO_8_ROMSO

+3VSDGPU +1.8VSDGPU

RV502 10K_0201_5%@

1 2

DIS@

RV151 10K_0201_5%

1 2

PS_2[3:1]=000

PS_2[5:4]=11

CV11

12

1

@

2

0.082U_0402_16V

Strap Name :

PS_2[1] N/A

PS_2[2] N/A

PS_2[3] STRAP_BIOS_ROM_EN

PS_2[4] STRAP_BIF_VGA_DIS

PS_2[5] N/A

12

UV56

@

1

CS#

2

DO(IO1)

HOLD#(IO3)

3

WP#(IO2)

4

GND

GD25Q40CTIGR_SOIC_8P

SA0000AE400

S IC FL 4M GD25Q40CTIGR SOP 8P SPI

Follow CRB material

RV152 10K_0201_5%@

1 2

@

RV28

8.45K_0402_1%

R535@

RV13

4.75K_0402_1%

R18M-M2-60

GPIO5

Yes

GPIO6

No

GPIO21

No

DV1

DIS@

RB751V-40_SOD323-2

12

DV2

DIS@

RB751V-40_SOD323-2

12

DV4

DIS@

RB751V-40_SOD323-2

12

8

VCC

7

GPIO_10_ROMSCK

6

GPIO_9_ROMSI

CLK

5

DI(IO0)

+3VSDGPU

WAKEB

SCL can leave ncVDD_33

PS_3[3:1]=000

PS_3[5:4]=11

CV15

Strap Name :

PS_3[1] BOARD_CONFIG[0] (Memory ID)

PS_3[2] BOARD_CONFIG[1] (Memory ID)

PS_3[3] BOARD_CONFIG[2] (Memory ID)

PS_3[4] AUD_PORT_CONN_PINSTRAP[1]

PS_3[5] AUD_PORT_CONN_PINSTRAP[2]

1

R17M-G1-50/70 R17M-P1-50/70 R18M-G1-90

Yes

GPU_ACIN <30>

GPU_PROCHOT# <45>

APU_PROCHOT#_D <38>

GPU_THERMAL# <30>

+3VSDGPU+ 3VSDGPU

12

RV162

4.7K_0402_5%

@

12

RV430

4.7K_0402_5%

@

1

@

2

0.68U_0402_10V

1

@

CV2721

0.1U_0201_10V6K

2

12

@

RV15

8.45K_0402_1%

12

@

RV16

4.75K_0402_1%

Polaris Memory ID at page 17

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2017/12/25 2019/12/25

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

R18M-M260/G190_(2/9)_MSIC-1

Size

Document Number Re v

Custom

DH5AV_JV_0V_LA-G021P

Date : Sheet of

DH5AV_JV_0V_LA-G021P

1

16 48Monday, December 25, 2017

1.B

5

+1.8VSDGPU

DIS@

RV468

10K_0201_5%

1 2

D D

Polaris Memory ID

BOARD_CONFIG[2:0]

000:SAM 256Mx32 001:HYN 256Mx32 010:SAM 128Mx32 011:HYX 128Mx32 100:MIC 256Mx32 4.53k 4. 99k 10 0

RV15 PV4G_H@

C C

S RES 1/16W 8.45K +-1% 0402

SD000000680

RV15 PV2G_S@

S RES 1/16W 4.53K +-1% 0402

SD034453180

RV15 PV2G_H@

S RES 1/16W 6.98K +-1% 0402

SD000002680

RV15 PV4G_M@

R_pd (ohm)R_pu (ohm)

NC

4.75k

8.45k

2k

4.53k

2k

6.98k

4.99k

RV16 PV4G_S@

S RES 1/16W 4.75K +-1% 0402

SD034475180

RV16 PV4G_H@

S RES 1/16W 2K +-1% 0402

SD034200180

RV16 PV2G_S@

S RES 1/16W 2K +-1% 0402

SD034200180

RV16 PV2G_H@

S RES 1/16W 4.99K +-1% 0402

SD034499180

RV16 PV4G_M@

Bitd [3:1]

00 0 00 1 01 0 01 1

UV1F

@

symbol6

XTALOUT

PLLCHARZ_L

PLLCHARZ_H

REV 0.91

2160896088 A1R16M_FCBGA769P-NH

ANALOGIO

RV467

XTALIN

DIS@

10K_0201_5%

1 2

4

RV101 33_0 201_5%

1 2 1 2

RV100 33_0 201_5%

1 2

RV469

10K_0402_5%

BA39

AY39

AV15 AU15

AY38

12

DIS@ DIS@

DIS@

1

TP@

1

TP@

RV83

16.2K_0402_1 %@

XTALIN

XTALOUT

DNI

T229 T230

AA38 AA37

B2

UV1A

@

symbol1

BP_0 BP_1

TEST6

REV 0.91

2160896088 A1R16M_FCBGA769P-NH

JTAG_TDO

JTAG_TDI

JTAG_TMS

JTAG_TCK

TESTEN

JTAG_TRSTB

AF41 AD40 AD41 AE41

AE40 AF40

XTALOUT

XTALIN

3

JTAG_TDI_GPU JTAG_TDO_GPU JTAG_TMS_GPU JTAG_TCK_GPU

JTAG_TDO_GPU JTAG_TDI_GPU JTAG_TMS_GPU JTAG_TCK_GPU

JTAG_TESTEN_GPU JTAG_TRSTB_GPU

RV503 0_0402_5%R535@

RV504 0_0402_5%R535@

JTAG_TRSTB_GPU

JTAG_TESTEN_GPU

12

27MHZ_10PF_XRCGB2 7M000F2P18R0

1

DIS@

CV450

10P_0402_50 V8J

RV506 0_0402_5%

LEXA@

Close to RV504 for Reduce redundancy trace

2

XTALOUT_R

XTALIN_100M

12

RPV34

10K_0804_8P 4R_5%

RV369 10K_0201_5%DIS@ RV1630 10K_ 0201_5%@

RV470 5.1K_0201_1%@ RV471 1K_0201_5%DIS@

XTALOUT_R

XTALIN_R

YV1

3

+3VSDGPU

@

18 27 36 45

+3VSDGPU

12 12

+3VSDGPU

12 12

RV20

DIS@

1M_0402_5%

DIS@

SJ10000UI00

NC

2

4

LEXA@

UV4

3

XOUT

4

SSCLK1/REFCLK/FSEL/SSONb/OE

SI51214-A1FAGMR_TDFN6_ 1P2X1P4

SA0000A4K00

S IC SI51214-A1FAGMR TDFN 6P CLK GEN

1

ESR:40ohm (Max)

1

DIS@

CV451 10P_0402_50 V8J

2

XIN/CLKIN

SSCLK2/OE/SSONb/PD

VDD

VSS

SI_SS_SEL

2

1

5

6

2

XTALIN_R

SI_SS_SEL

+1.8VSDGPU

1 2

RV154 5.1K_0402_1%

DIS@

1 2

RV505 5.1K_0402_1%

@

0.1U_0201_10V6K

1

2

@

LV7

BLM15BD121SN 1D_0402

1 2

CV2723

10U_0603_6.3V6M

CV449

1

LEXA@

2

1

+1.8VSDGPU

LEXA@

LEXA Memory ID

S RES 1/16W 4.53K +-1% 0402

SD034453180

B B

A A

S RES 1/16W 4.99K +-1% 0402

SD034499180

UV1K

@

symbol11

DBGDATA_0 DBGDATA_1 DBGDATA_2 DBGDATA_3 DBGDATA_4 DBGDATA_5 DBGDATA_6 DBGDATA_7 DBGDATA_8

DBGDATA_9 DBGDATA_10 DBGDATA_11 DBGDATA_12 DBGDATA_13 DBGDATA_14 DBGDATA_15

REV 0.91

2160896088 A1R16M_FCBGA769P-NH

+1.8VSDGPU

AUD_PORT_CONN[2:0]

111: No usable endpoints

12

DBGDATA_0

L40

DBGDATA_1

L41

DBGDATA_2

M40

DBGDATA_3

M41

DBGDATA_4

N40

DBGDATA_5

N41

DBGDATA_6

P40

DBGDATA_7

P41

DBGDATA_8 DBGDATA_9 DBGDATA_10 DBGDATA_11 DBGDATA_12 DBGDATA_13 DBGDATA_14 DBGDATA_15

1

TP@

T221

1

TP@

T222

1

TP@

T223

1

TP@

T224

1

TP@

T225

1

TP@

T226

1

TP@

T227

1

TP@

T228

R40 R41 T40 T41 U40 U41 V40 V41

LEXA@

RV456

5.1K_0201_1%

12

@

RV455

5.1K_0201_1%

LEXA@

RV453

RV457

5.1K_0201_1%

12

@

RV454

RV458

5.1K_0201_1%

12

@

RV459

RV461

5.1K_0201_1%

12

@

RV460

RV462

5.1K_0201_1%

12

@

RV463

5.1K_0201_1%

12

@

RV464

5.1K_0201_1%

12

@

LEXA@

RV465

RV442

5.1K_0201_1%

DBGDATA_0

AUD_PORT_CONN[0]

DBGDATA_1

AUD_PORT_CONN[1]

DBGDATA_2

AUD_PORT_CONN[2]

DBGDATA_3

BOARD_CONFIG[0]

DBGDATA_4

BOARD_CONFIG[1]

DBGDATA_5

BOARD_CONFIG[2]

DBGDATA_6

SMBUS_ADDR[0]

DBGDATA_7

SMBUS_ADDR[1]

12

@

LEXA@

RV441

RV466

5.1K_0201_1%

110: One usable endpoint 101: Two usable endpoints 100: Three usable endpoints 011: Four usable endpoints 010: Five usable endpoints 001: Six usable endpoints 000: All endpoints are usable

BOARD_CONFIG[2:0]

000:SAM 256Mx32 (6Gb/7Gb) 001:HYN 256Mx32 (6Gb/7Gb) 010:SAM 128Mx32 011:HYX 128Mx32 100:MIC 256Mx32 (6Gb/7Gb) 101: 110: 111:

DBGDATA_[7:6]

00: 0× 40 01: 0× 41 10: 0× 42 11: 0× 43

RV464 V4G_S@

S RES 1/20W 5.1K +-1% 0201

SD000008900

RV464 V4G_H@

S RES 1/20W 5.1K +-1% 0201

SD000008900

RV464 V2G_S@

S RES 1/20W 5.1K +-1% 0201

SD000008900

RV464 V2G_H@

S RES 1/20W 5.1K +-1% 0201

SD000008900

RV463 V4G_M@

S RES 1/20W 5.1K +-1% 0201

SD000008900

RV464 V4G_S7 G@

RV464 V4G_H7 G@

RV463 V4G_M7 G@

RV462 V4G_S@

S RES 1/20W 5.1K +-1% 0201

SD000008900

RV462 V4G_H@

S RES 1/20W 5.1K +-1% 0201

SD000008900

RV461 V2G_S@

S RES 1/20W 5.1K +-1% 0201

SD000008900

RV461 V2G_H@

S RES 1/20W 5.1K +-1% 0201

SD000008900

S RES 1/20W 5.1K +-1% 0201

SD000008900

RV462 V4G_S7G@

RV462 V4G_H7G@

RV462 V4G_M7G@ RV460 V4G_M@

RV460 V4G_S@

S RES 1/20W 5.1K +-1% 0201

SD000008900

RV459 V4G_H@

S RES 1/20W 5.1K +-1% 0201

SD000008900

RV460 V2G_S@

S RES 1/20W 5.1K +-1% 0201

SD000008900

RV459 V2G_H@

S RES 1/20W 5.1K +-1% 0201

SD000008900

S RES 1/20W 5.1K +-1% 0201

SD000008900

RV460 V4G_S7 G@

RV459 V4G_H7 G@

RV460 V4G_M7 G@RV462 V4G_M@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/12/25 2019/12/25

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number R ev

Custom

Date : Sheet of

2

Date : Sheet of

Compal Electronics, Inc.

R18M-M260/G190_(3/9)_MSIC-2

DH5AV_JV_0V_LA-G021P

1

17 4 8Monday, December 25, 2017

1.B

5

4

3

2

1

UV1C

MA0_D[0..31]< 21> MA1_D[0..31] <2 1>

D D

MA0_A[0..8]<21> MA1_A[0..8] <21>

C C

MA0_WCK01<21>

MA0_WCK01#<21>

MA0_WCK23<21>

MA0_WCK23#<21>

MA0_EDC0<21> MA1_EDC0 <21> MA0_EDC1<21> MA0_EDC2<21> MA0_EDC3<21>

MA0_DBI#0<21> MA1_DBI#0 < 21> MA0_DBI#1<21> MA0_DBI#2<21> MA0_DBI#3<21>

MA0_ADBI< 21> MA1_ADBI <21>

MA0_CS#<21> MA1_CS# <21>

MA0_D0 MA0_D1 MA0_D2 MA0_D3 MA0_D4 MA0_D5 MA0_D6 MA0_D7 MA0_D8 MA0_D9 MA0_D10 MA0_D11 MA0_D12 MA0_D13 MA0_D14 MA0_D15 MA0_D16 MA0_D17 MA0_D18 MA0_D19 MA0_D20 MA0_D21 MA0_D22 MA0_D23 MA0_D24 MA0_D25 MA0_D26 MA0_D27 MA0_D28 MA0_D29 MA0_D30 MA0_D31

MA0_A0 MA1_A0 MA0_A1 MA0_A2 MA0_A3 MA0_A4 MA0_A5 MA0_A6 MA0_A7 MA0_A8

MA0_WCK01 MA0_WCK01# MA1_WCK01#

MA0_WCK23 MA0_WCK23#

MA0_EDC0 MA0_EDC1 MA0_EDC2 MA0_EDC3

MA0_DBI#0 MA1_DBI#0 MA0_DBI#1 MA0_DBI#2 MA0_DBI#3

MA0_ADBI MA1_ADBI

MA0_CS# MA1_CS#

@

symbol3

L34

DQA0_0

L37

DQA0_1

L38

DQA0_2

J35

DQA0_3

G37

DQA0_4

E38

DQA0_5

E35

DQA0_6

D35

DQA0_7

H41

DQA0_8

H40

DQA0_9

G41

DQA0_10

G40

DQA0_11

E40

DQA0_12

D41

DQA0_13

D40

DQA0_14

C41

DQA0_15

C40

DQA0_16

B39

DQA0_17

A39

DQA0_18

B38

DQA0_19

B36

DQA0_20

A36

DQA0_21

B35

DQA0_22

A35

DQA0_23

B33

DQA0_24

B32

DQA0_25

A32

DQA0_26

B31

DQA0_27

A30

DQA0_28

B29

DQA0_29

B28

DQA0_30

A28

DQA0_31

G25

MAA0_0

H25

MAA0_1

E27

MAA0_2

D27

MAA0_3

D29

MAA0_4

H27

MAA0_5

H23

MAA0_6

E23

MAA0_7

D25

MAA0_8

H29

MAA0_9

D33

WCKA0_0

E33

WCKA0B_0

A34

WCKA0_1

B34

WCKA0B_1

G38

EDCA0_0

F41

EDCA0_1

B37

EDCA0_2

A31

EDCA0_3

J38

DDBIA0_0

F40

DDBIA0_1

A38

DDBIA0_2

B30

DDBIA0_3

H21

ADBIA0

H31

CSA0B_0

DQA1_0 DQA1_1 DQA1_2 DQA1_3 DQA1_4 DQA1_5 DQA1_6 DQA1_7 DQA1_8

DQA1_9 DQA1_10 DQA1_11 DQA1_12 DQA1_13 DQA1_14 DQA1_15 DQA1_16 DQA1_17 DQA1_18 DQA1_19 DQA1_20 DQA1_21 DQA1_22 DQA1_23 DQA1_24 DQA1_25 DQA1_26 DQA1_27 DQA1_28 DQA1_29 DQA1_30 DQA1_31

MAA1_0

MAA1_1

MAA1_2

MAA1_3

MAA1_4

MAA1_5

MAA1_6

MAA1_7

MAA1_8

MAA1_9

WCKA1_0

WCKA1B_0

WCKA1_1

WCKA1B_1

EDCA1_0 EDCA1_1 EDCA1_2 EDCA1_3

DDBIA1_0 DDBIA1_1 DDBIA1_2 DDBIA1_3

ADBIA1

CSA1B_0

B27 A27 B26 A26 A24 B23 A23 B22 B20 A20 B19 A19 B17 A16 B16 A15 B15 A14 B14 B13 A11 B11 A10 B10 B8 A7 B7 A6 A4 B4 A3 B3

E15 H15 G13 D13 H11 H13 H17 G17 D15 E11

A22 B21

A8 B9

B24 A18 B12 B6

B25 B18 A12 B5

H19

E7

MA1_D0 MA1_D1 MA1_D2 MA1_D3 MA1_D4 MA1_D5 MA1_D6 MA1_D7 MA1_D8 MA1_D9 MA1_D10 MA1_D11 MA1_D12 MA1_D13 MA1_D14 MA1_D15 MA1_D16 MA1_D17 MA1_D18 MA1_D19 MA1_D20 MA1_D21 MA1_D22 MA1_D23 MA1_D24 MA1_D25 MA1_D26 MA1_D27 MA1_D28 MA1_D29 MA1_D30 MA1_D31

MA1_A1 MA1_A2 MA1_A3 MA1_A4 MA1_A5 MA1_A6 MA1_A7 MA1_A8

MA1_WCK01

MA1_WCK23 MA1_WCK23#

MA1_EDC0 MA1_EDC1 MA1_EDC2 MA1_EDC3

MA1_DBI#1 MA1_DBI#2 MA1_DBI#3

MA1_WCK01 <21> MA1_WCK01# <21>

MA1_WCK23 <21> MA1_WCK23# <21>

MA1_EDC1 <21> MA1_EDC2 <21> MA1_EDC3 <21>

MA1_DBI#1 < 21> MA1_DBI#2 < 21> MA1_DBI#3 < 21>

MB0_D[0..31]< 22>

MB0_A[0..8]<22>

MB0_WCK01< 22>

MB0_WCK01 #<22>

MB0_WCK23< 22>

MB0_WCK23 #<22>

MB0_EDC0<22> MB0_EDC1<22> MB0_EDC2<22> MB0_EDC3<22>

MB0_DBI#0< 22> MB0_DBI#1< 22> MB0_DBI#2< 22> MB0_DBI#3< 22>

MB0_ADBI< 22>

MB0_CS#<22>

MB0_D0 MB0_D1 MB0_D2 MB0_D3 MB0_D4 MB0_D5 MB0_D6 MB0_D7 MB0_D8 MB0_D9 MB0_D10 MB0_D11 MB0_D12 MB0_D13 MB0_D14 MB0_D15 MB0_D16 MB0_D17 MB0_D18 MB0_D19 MB0_D20 MB0_D21 MB0_D22 MB0_D23 MB0_D24 MB0_D25 MB0_D26 MB0_D27 MB0_D28 MB0_D29 MB0_D30 MB0_D31

MB0_A0 MB0_A1 MB0_A2 MB0_A3 MB0_A4 MB0_A5 MB0_A6 MB0_A7 MB0_A8

MB0_WCK01 MB0_WCK01 #

MB0_WCK23 MB0_WCK23 #

MB0_EDC0 MB0_EDC1 MB0_EDC2 MB0_EDC3

MB0_DBI#0 MB0_DBI#1 MB0_DBI#2 MB0_DBI#3

MB0_ADBI

MB0_CS#

UV1D

@

C2

DQB0_0

C1

DQB0_1

D2

DQB0_2

D1

DQB0_3

F1

DQB0_4

G2

DQB0_5

G1

DQB0_6

H2

DQB0_7

K2

DQB0_8

K1

DQB0_9

L2

DQB0_10

L1

DQB0_11

N2

DQB0_12

P2

DQB0_13

P1

DQB0_14

R2

DQB0_15

R1

DQB0_16

T2

DQB0_17

T1

DQB0_18

U2

DQB0_19

W1

DQB0_20

W2

DQB0_21

Y1

DQB0_22

Y2

DQB0_23

AB2

DQB0_24

AC1

DQB0_25

AC2

DQB0_26

AD1

DQB0_27

AF1

DQB0_28

AF2

DQB0_29

AG1

DQB0_30

AG2

DQB0_31

R5

MAB0_0

R8

MAB0_1

N7

MAB0_2

N4

MAB0_3

L8

MAB0_4

N8

MAB0_5

U8

MAB0_6

U7

MAB0_7

R4

MAB0_8

L5

MAB0_9

H1

WCKB0_0

J2

WCKB0B_0

AB1

WCKB0_1

AA2

WCKB0B_1

F2

EDCB0_0

M2

EDCB0_1

V1

EDCB0_2

AD2

EDCB0_3

E2

DDBIB0_0

M1

DDBIB0_1

V2

DDBIB0_2

AE2

DDBIB0_3

ADBIB0W8ADBIB1

CSB0B_0G5CSB1B_0

symbol4

DQB1_0 DQB1_1 DQB1_2 DQB1_3 DQB1_4 DQB1_5 DQB1_6 DQB1_7 DQB1_8

DQB1_9 DQB1_10 DQB1_11 DQB1_12 DQB1_13 DQB1_14 DQB1_15 DQB1_16 DQB1_17 DQB1_18 DQB1_19 DQB1_20 DQB1_21 DQB1_22 DQB1_23 DQB1_24 DQB1_25 DQB1_26 DQB1_27 DQB1_28 DQB1_29 DQB1_30 DQB1_31

MAB1_0

MAB1_1

MAB1_2

MAB1_3

MAB1_4

MAB1_5

MAB1_6

MAB1_7

MAB1_8

MAB1_9

WCKB1_0

WCKB1B_0

WCKB1_1

WCKB1B_1

EDCB1_0 EDCB1_1 EDCB1_2 EDCB1_3

DDBIB1_0 DDBIB1_1 DDBIB1_2 DDBIB1_3

AH1 AH2 AJ2 AK1 AL2 AM1 AM2 AN2 AR1 AR2 AT1 AT2 AV2 AW1 AW2 AY3 BA3 AY4 BA4 AY5 BA7 AY7 AY8 BA8 AR4 AR5 AU4 AU7 AN8 AV11 AU11 AP11

AE7 AE8 AG5 AG4 AJ4 AG8 AC8 AC5 AE4 AJ8

AP1 AP2

AN4 AN5

AL1 AU2 BA6 AV7

AK2 AV1 AY6 AV9

AA8

AL8

MB1_D0 MB1_D1 MB1_D2 MB1_D3 MB1_D4 MB1_D5 MB1_D6 MB1_D7 MB1_D8 MB1_D9 MB1_D10 MB1_D11 MB1_D12 MB1_D13 MB1_D14 MB1_D15 MB1_D16 MB1_D17 MB1_D18 MB1_D19 MB1_D20 MB1_D21 MB1_D22 MB1_D23 MB1_D24 MB1_D25 MB1_D26 MB1_D27 MB1_D28 MB1_D29 MB1_D30 MB1_D31

MB1_A0 MB1_A1 MB1_A2 MB1_A3 MB1_A4 MB1_A5 MB1_A6 MB1_A7 MB1_A8

MB1_WCK01 MB1_WCK01 #

MB1_WCK23 MB1_WCK23 #

MB1_EDC0 MB1_EDC1 MB1_EDC2 MB1_EDC3

MB1_DBI#0 MB1_DBI#1 MB1_DBI#2 MB1_DBI#3

MB1_ADBI

MB1_CS#

MB1_D[0..31] <2 2>

MB1_A[0..8] <22>

MB1_WCK01 <22> MB1_WCK01 # <22>

MB1_WCK23 <22> MB1_WCK23 # <22>

MB1_EDC0 <2 2> MB1_EDC1 <2 2> MB1_EDC2 <2 2> MB1_EDC3 <2 2>

MB1_DBI#0 < 22> MB1_DBI#1 < 22> MB1_DBI#2 < 22> MB1_DBI#3 < 22>

MB1_ADBI <2 2>

MB1_CS# <22>

MA0_CAS#<21> M A1_CAS# <21>

B B

MA_VRAMRST#<2 1>

A A

MA0_RAS#<21> M A1_RAS# <21>

MA0_WE#<2 1> MA1_WE# <21>

MA0_CKE<21> MA1_CKE <21>

MA0_CLK<2 1>

MA0_CLK#<21> MA1_CLK# <21>

1 2

Place close to GPU (within 25mm) and place componment within (5mm) close to each other

5

MA0_CAS# MA1_ CAS# MA0_RAS# MA1_ RAS# MA0_WE# MA1_ WE#

MA0_CKE MA1_CKE

MA0_CLK MA0_CLK# MA1_CLK#

1 2

RV39 120_0402_1 %

DIS@

MA_VRAMRST#_G

RV36

49.9_0402_1%

DIS@

120P_0402_5 0V8J

DIS@

CV96

RV37 10_0402_1%

1

2

DIS@

12

DIS@

RV38

5.1K_0402_1%

D23

CASA0B

D21

RASA0B

G29

WEA0B

G21

CKEA0

E31

CLKA0

D31

CLKA0B

K15

MEM_CALRA

L32

DRAM_RSTA

2160896088 A1R16M_FCBGA769P-NH

12

CASA1B RASA1B

CLKA1B

MVREFDA

REV 0.91

MA_VRAMRST#_G

1

@

CV97 68P_0402_50 V8J

2

WEA1B

CKEA1

CLKA1

D17 D19 D11

E19

D7 D9

K17

4

MA_VREFD

MA1_CLK

MA_VREFD

40.2_0402_1%

100_0402_1 %

DIS@

RV32

DIS@

RV35

MA1_CLK <21>

+1.35VSDGPU

12

DIS@

1

CV486 1U_0201_6.3V6M

2

MB_VRAMRST#< 22>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

MB0_CAS#<22> MB0_RAS#<22>

MB0_WE#< 22>

MB0_CKE<22>

MB0_CLK<2 2>

MB0_CLK#<22>

1 2

Place close to GPU (within 25mm) and place componment within (5mm) close to each other

MB0_CAS# MB0_RAS# MB0_WE#

MB0_CKE

MB0_CLK MB0_CLK#

1 2

RV1633 120 _0402_1%

LEXA@

MB_VRAMRST#_G

RV1641

49.9_0402_1%

LEXA@

120P_0402_5 0V8J

2017/12/25 2019/12/25

LEXA@

CV2720

RV1642 10_0402_1%

LEXA@

1

5.1K_0402_1%

2

Compal Secret Data

12

CASB0BU4CASB1B RASB0BW4RASB1B WEB0BL4WEB1B

W5

CKEB0

G4

CLKB0

J4

CLKB0B

R10

MEM_CALRB

AM11

DRAM_RSTB

2160896088 A1R16M_FCBGA769P-NH

12

LEXA@

RV1643

Deciphered Date

2

MVREFDB

MB_VRAMRST#_G

1

@

CV2719

68P_0402_50 V8J

2

CKEB1

CLKB1

CLKB1B

REV 0.91

AC4 AA4 AJ7

AA7

AL5 AL4

U10

MB1_CAS# MB1_RAS# MB1_WE#

MB1_CKE

MB1_CLK MB1_CLK#

MB_VREFD

40.2_0402_1%

MB_VREFD

100_0402_1 %

Title

Size Document Number R ev

Custom

Date : Sheet of

MB1_CAS# <22> MB1_RAS# <22> MB1_WE# <22>

MB1_CKE <22>

MB1_CLK <22> MB1_CLK# <22>

+1.35VSDGPU

12

DIS@

RV1635

12

DIS@

RV1634

R18M-M260/G190_(4/9)_MEM

DIS@

1

CV487 1U_0201_6.3V6M

2

Compal Electronics, Inc.

DH5AV_JV_0V_LA-G021P

1

1.B

18 4 8Monday, December 25, 2017

1.B

5

4

3

2

1

UV1G

@

D D

C C

UV1O

@

symbol15

TX2P_DPE0P

TX2M_DPE0N

TX1P_DPE1P

TX1M_DPE1N

TX0P_DPE2P

TX0M_DPE2N

TXCEP_DPE3P

TXCEM_DPE3N

B B

DDCAUX5P

DDCAUX5N

REV 0.91

2160896 088A1R16M_FC BGA769P-NH

AY18

BA18

AY16

BA16

AY15

BA15

AY14

BA14

AU27

AV27

1

TP@

T243

T242

DIS@

RV372

150_040 2_1%

BA12

1 2

symbol7

TX2P_DPB0P

TX2M_DPB0N

TX1P_DPB1P

TX1M_DPB1N

TX0P_DPB2P

TX0M_DPB2N

TXCBP_DPB3P

TXCBM_DPB3N

DDCAUX3P

DDCAUX3N

TX5P_DPA0P

TX5M_DPA0N

TX4P_DPA1P

TX4M_DPA1N

TX3P_DPA2P

TX3M_DPA2N

TXCAP_DPA3P

TXCAM_DPA3N

AUX_ZVSS

REV 0.91

2160896 088A1R16M_FC BGA769P-NH

DDCAUX4P

DDCAUX4N

AY32

BA32

AY31

BA31

AY30

BA30

AY28

BA28

AM21

AP21

AY36

BA36

AY35

BA35

AY34

BA34

AY33

BA33

AR23

AP23

1

TP@

UV1H

@

symbol8

T238

REV 0.91

2160896 088A1R16M_FC BGA769P-NH

TX2P_DPD0P

TX2M_DPD0N

TX1P_DPD1P

TX1M_DPD1N

TX0P_DPD2P

TX0M_DPD2N

TXCDP_DPD3P

TXCDM_DPD3N

AUX1P

AUX1N

DDC1CLK

DDC1DATA

TX5P_DPC0P

TX5M_DPC0N

TX4P_DPC1P

TX4M_DPC1N

TX3P_DPC2P

TX3M_DPC2N

TXCCP_DPC3P

TXCCM_DPC3N

AUX2P

AUX2N

DDC2CLK

DDC2DATA

AY22

BA22

AY21

BA21

AY20

BA20

AY19

BA19

AY11

BA11

AY10

BA10

AY27

BA27

AY26

BA26

AY25

BA25

AY24

BA24

AP19

AM19

AV19

AU19

1

TP@

1

TP@

1

TP@

1

TP@

T236

T232

T235

T233

Data Book:need config even if not use display function

A A

Security Classification

2017/12/ 25 2019/12/ 25

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

2017/12/ 25 2019/12/ 25

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

R18M-M260/G19_(5/9)_DISPLAY

Size Document Number Re v

Custom

Date : Sheet o f

2

Date : Sheet o f

Compal Electronics, Inc.

DH5AV_JV_0V_LA-G021P

19 48Monday, December 2 5, 2017

1

1.B

5

4

3

2

1

+VGA_CORE

CV32622U_0603_6.3V6M

CV32422U_0603_6.3V6M

CV32322U_0603_6.3V6M

CV32522U_0603_6.3V6M

DIS@

D D

C C

B B

A A

1 2

DIS@

1 2

+1.35VSDGPU

DIS@

1 2

CV34722U_0603_6.3V6M

DIS@

1 2

SCL:22u x8, 1u x7

1

CV32722U_0603_6.3V6M

CV32922U_0603_6.3V6M

CV32822U_0603_6.3V6M

DIS@

1 2

1

CV34822U_0603_6.3V6M

CV3371U_0201_6.3V6M

DIS@

2

5

CV621U_0201_6.3V6M

CV33022U_0603_6.3V6M

1 2

1

CV3381U_0201_6.3V6M

DIS@

2

CV3171U_0201_6.3V6M

DIS@

2

SCL:22u x2, 1u x10 SCL:1u x3

1

CV3411U_0201_6.3V6M

CV3401U_0201_6.3V6M

CV3391U_0201_6.3V6M

DIS@

2

R17M -P1-50 (25W): 30A R18M -M2-60 :25A R18M -G1-90 :60A

1

CV3181U_0201_6.3V6M

CV3191U_0201_6.3V6M

CV3201U_0201_6.3V6M

DIS@

2

R17M -P1-50 (25W): 2A(1. 35V) R18M -M2-60 :2A(1. 35V ) R18M -G1-90 :2A(1. 5V)

1

CV3441U_0201_6.3V6M

CV3421U_0201_6.3V6M

CV3431U_0201_6.3V6M

DIS@

2

CV316

DIS@

1U_0201_6.3V6M

1 2

1

CV3211U_0201_6.3V6M

CV3221U_0201_6.3V6M

DIS@

2

1

CV3461U_0201_6.3V6M

CV3451U_0201_6.3V6M

DIS@

2

+1.8VSDGPU

SCL:No need to implement.

13mA

UV1I

@

N13

symbol9

VDDC#0

N15

VDDC#1

N21

VDDC#2

N23

VDDC#3

N29

VDDC#4

N31

VDDC#5

R13

VDDC#6

R15

VDDC#7

R21

VDDC#8

R23

VDDC#9

R29

VDDC#10

R31

VDDC#11

U13

VDDC#12

U15

VDDC#13

U21

VDDC#14

U23

VDDC#15

U29

VDDC#16

U31

VDDC#17

W13

VDDC#18

W15

VDDC#19

W21

VDDC#20

W23

VDDC#21

W29

VDDC#22

W31

VDDC#23

AA13

VDDC#24

AA15

VDDC#25

AA21

VDDC#26

AA23

VDDC#27

AA29

VDDC#28

AA31

VDDC#29

AC13

VDDC#30

AC15

VDDC#31

AC21

VDDC#32

AC23

VDDC#33

AC29

VDDC#34

AC31

VDDC#35

AE13

VDDC#36

AE15

VDDC#37

AE21

VDDC#38

AE23

VDDC#39

AE29

VDDC#40

AE31

VDDC#41

AG13

VDDC#42

AG15

VDDC#43

AG21

VDDC#44

AG23

VDDC#45

AG29

VDDC#46

AG31

VDDC#47

AJ13

VDDC#48

AJ15

VDDC#49

AJ17

VDDC#50

AJ19

VDDC#51

AJ21

VDDC#52

AJ23

VDDC#53

AJ25

VDDC#54

AJ27

VDDC#55

AJ29

VDDC#56

AJ31

VDDC#57

AL13

VDDC#58

AL15

VDDC#59

AL17

VDDC#60

AL19

VDDC#61

AL21

VDDC#62

AL23

VDDC#63

AL25

VDDC#64

AL27

VDDC#65

AL29

VDDC#66

AL31

VDDC#67

REV 0.91

2160896088A1R16M_FCBGA769P-NH

UV1N

@

symbol14

K11

VMEMIO#0

K13

VMEMIO#1

K19

VMEMIO#2

K23

VMEMIO#3

K27

VMEMIO#4

K31

VMEMIO#5

L10

VMEMIO#6

N10

VMEMIO#7

W10

VMEMIO#8

AC10

VMEMIO#9

AG10

VMEMIO#10

REV 0.91

2160896088A1R16M_FCBGA769P-NH

UV1J

@

symbol10

AM13

TSVDD

J8

TEMPIN0

J7

TEMPINRETURN

GPIO_28_FDO

N38

TS_A

REV 0.91

2160896088A1R16M_FCBGA769P-NH

4

FB_VMEMIO

DPLUS

DMINUS

FB_VDDCI

VDDCI#0 VDDCI#1 VDDCI#2 VDDCI#3 VDDCI#4 VDDCI#5 VDDCI#6 VDDCI#7 VDDCI#8

FB_VDDC

FB_VSS

VDD_18#0 VDD_18#1 VDD_18#2

VDD_08#0 VDD_08#1 VDD_08#2 VDD_08#3 VDD_08#4 VDD_08#5

VDD_08

VSS VSS

N35

N34

U38

R17M -P1-50 (25W): 8A R18M -M2-60 :Merge -VDD C R18M -G1-90 :12A

L13 L17 L21 L25 L29 N11 U11 AA11 AE11

C3

GPU_VDDCI_SEN

AV13

GPU_VDDC_SEN

AR13

GPU_VSS_SEN_L

AU13

1A

AM15 AP15 AR15

R17M -P1-50 (25W): Merge- VDD CI R18M -M2-60 :2A R18M -G1-90 :Merge -VDD CI

AC32 AG32 AG35 AJ32 AJ34 AL34

W32

AM23 AM17

DG:Thermal Die Temperature

GPIO_28_FDO

1

CV3331U_0201_6.3V6M

CV3341U_0201_6.3V6M

DIS@

2

1

CV3521U_0201_6.3V6M

CV3531U_0201_6.3V6M

DIS@

2

Fan Drive Out option

RV21 10K_0201_5%

R535@

1 2

SCL:22u x2, 1u x4

1

CV3321U_0201_6.3V6M

DIS@

2

1

CV3551U_0201_6.3V6M

CV3541U_0201_6.3V6M

DIS@

2

1

CV3311U_0201_6.3V6M

DIS@

1 2

DIS@

2

GPU_VDDCI_SEN <45> GPU_VDDC_SEN <45> GPU_VSS_SEN_L <45>

+0.8VSDGPU

SCL:1u x7

1

CV3571U_0201_6.3V6M

CV3561U_0201_6.3V6M

DIS@

2

CV33622U_0603_6.3V6M

DIS@

+VDDCI

DIS@

1

CV3581U_0201_6.3V6M

2

UV1L

@

symbol12

A2

VSS#0

A5

VSS#1

A9

VSS#2

CV33522U_0603_6.3V6M

1 2

0.24uH,<0.15mohm CRB no use, reserve first

1

CV3501U_0201_6.3V6M

CV3511U_0201_6.3V6M

CV3491U_0201_6.3V6M

DIS@

2

3

+1.8VSDGPU

RV1632 0_0805_5%

1 2

RS@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2017/12/25 2019/12/25

Compal Secret Data

Deciphered Date

2

A13

VSS#3

A17

VSS#4

A21

VSS#5

A25

VSS#6

A29

VSS#7

A33

VSS#8

A37

VSS#9

A40

VSS#10

B1

VSS#11

B40

VSS#12

B41

VSS#13

C5

VSS#14

C7

VSS#15

C9

VSS#16

C11

VSS#17

C13

VSS#18

C15

VSS#19

C17

VSS#20

C19

VSS#21

C21

VSS#22

C23

VSS#23

C25

VSS#24

C27

VSS#25

C29

VSS#26

C31

VSS#27

C33

VSS#28

C35

VSS#29

C37

VSS#30

C39

VSS#31

E1

VSS#32

E3

VSS#33

E4

VSS#34

E9

VSS#35

E13

VSS#36

E17

VSS#37

E21

VSS#38

E25

VSS#39

E29

VSS#40

E39

VSS#41

E41

VSS#42

G3

VSS#43

G7

VSS#44

G11

VSS#45

G15

VSS#46

G19

VSS#47

G23

VSS#48

G27

VSS#49

G31

VSS#50

G35

VSS#51

G39

VSS#52

J1

VSS#53

J3

VSS#54

J5

VSS#55

J34

VSS#56

J37

VSS#57

REV 0.91

2160896088A1R16M_FCBGA769P-NH

UV1M

@

symbol13

AA5

VSS#115

AA10

VSS#116

AA17

VSS#117

AA19

VSS#118

AA25

VSS#119

AA27

VSS#120

AA32

VSS#121

AA39

VSS#122

AC3

VSS#123

AC7

VSS#124

AC11

VSS#125

AC17

VSS#126

AC19

VSS#127

AC25

VSS#128

AC27

VSS#129

AC39

VSS#130

AE1

VSS#131

AE3

VSS#132

AE5

VSS#133

AE10

VSS#134

AE17

VSS#135

AE19

VSS#136

AE25

VSS#137

AE27

VSS#138

AE32

VSS#139

AE35

VSS#140

AE39

VSS#141

AG3

VSS#142

AG7

VSS#143

AG11

VSS#144

AG17

VSS#145

AG19

VSS#146

AG25

VSS#147

AG27

VSS#148

AG39

VSS#149

AG40

VSS#150

AG41

VSS#151

AJ1

VSS#152

AJ3

VSS#153

AJ5

VSS#154

AJ10

VSS#155

AJ11

VSS#156

AJ35

VSS#157

AJ39

VSS#158

AL3

VSS#159

AL7

VSS#160

AL10

VSS#161

AL11

VSS#162

AL32

VSS#163

AL35

VSS#164

AL39

VSS#165

AN1

VSS#166

AN3

VSS#167

AN7

VSS#168

AN35

VSS#169

AN39

VSS#170

REV 0.91

2160896088A1R16M_FCBGA769P-NH

Title

Size

Date : Sheet of

Custom

J39

VSS#58

J40

VSS#59

J41

VSS#60

K21

VSS#61

K25

VSS#62

K29

VSS#63

K40

VSS#64

L3

VSS#65

L7

VSS#66

L11

VSS#67

L15

VSS#68

L19

VSS#69

L23

VSS#70

L27

VSS#71

L31

VSS#72

L35

VSS#73

L39

VSS#74

N1

VSS#75

N3

VSS#76

N5

VSS#77

N17

VSS#78

N19

VSS#79

N25

VSS#80

N27

VSS#81

N32

VSS#82

N37

VSS#83

N39

VSS#84

R3

VSS#85

R7

VSS#86

R11

VSS#87

R17

VSS#88

R19

VSS#89

R25

VSS#90

R27

VSS#91

R32

VSS#92

R35

VSS#93

R39

VSS#94

U1

VSS#95

U3

VSS#96

U5

VSS#97

U17

VSS#98

U19

VSS#99

U25

VSS#100

U27

VSS#101

U32

VSS#102

U37

VSS#103

U39

VSS#104

W3

VSS#105

W7

VSS#106

W11

VSS#107

W17

VSS#108

W19

VSS#109

W25

VSS#110

W27

VSS#111

W39

VSS#112

AA1

VSS#113

AA3

VSS#114

AN40

VSS#171

AN41

VSS#172

AP13

VSS#173

AP17

VSS#174

AR3

VSS#175

AR7

VSS#176

AR11

VSS#177

AR19

VSS#178

AR21

VSS#179

AR25

VSS#180

AR27

VSS#181

AR31

VSS#182

AR35

VSS#183

AR39

VSS#184

AU1

VSS#185

AU3

VSS#186

AU9

VSS#187

AU23

VSS#188

AU29

VSS#189

AW3

VSS#190

AW5

VSS#191

AW7

VSS#192

AW9

VSS#193

AW11

VSS#194

AW13

VSS#195

AW15

VSS#196

AW17

VSS#197

AW19

VSS#198

AW21

VSS#199

AW23

VSS#200

AW25

VSS#201

AW27

VSS#202

AW29

VSS#203

AW31

VSS#204

AW33

VSS#205

AW35

VSS#206

AW37

VSS#207

AW39

VSS#208

AY1

VSS#209

AY2

VSS#210

AY9

VSS#211

AY12

VSS#212

AY17

VSS#213

AY23

VSS#214

AY29

VSS#215

AY37

VSS#216

AY40

VSS#217

AY41

VSS#218

BA2

VSS#219

BA5

VSS#220

BA9

VSS#221

BA17

VSS#222

BA23

VSS#223

BA29

VSS#224

BA37

VSS#225

BA40

VSS#226

Compal Electronics, Inc.

R18M-M260/G19_(6/9)_PWR/GND

Document Number Re v

DH5AV_JV_0V_LA-G021P

1

20 48Monday, December 25, 2017

1.B

5

MA0_CLK

MA0_CLK#

MA0_D[0..31]

MA0_A[0..8]

MA1_D[0..31]

MA1_A[0..8]

MA0_EDC0<18> MA0_EDC1<18> MA0_EDC2<18> MA0_EDC3<18>

MA0_DBI#0<18> MA0_DBI#1<18> MA0_DBI#2<18> MA0_DBI#3<18>

MA0_CLK< 18> MA0_CLK#<18> MA0_CKE<18>

MA0_ADBI<18> MA0_RAS#<18> MA0_CS#< 18> MA0_CAS#<18> MA0_WE#<18>

MA0_WCK01#<18> MA0_WCK01<18>

MA0_WCK23#<18>

VREFD1_A0 VREFD1_A0

VREFD2_A0

VREFC_A0

MA0_WCK23<18>

MA_VRAMRST#< 18>

MA0_EDC0 MA0_EDC1 MA0_EDC2 MA0_EDC3

MA0_DBI#0 MA0_DBI#1 MA0_DBI#2 MA0_DBI#3

MA0_CLK MA0_CLK# MA0_CKE

MA0_A2 MA0_A5 MA0_A4 MA0_A3

MA0_A7 MA0_A1 MA0_A0 MA0_A6 MA0_A8

RV134 1K _0402_1%DIS@ RV474 1K _0402_1%DIS@

1 2

RV123 120 _0402_1%

DIS@

MA0_ADBI MA1_ADBI MA0_RAS# MA0_CS# MA0_CAS# MA0_WE#

MA0_WCK01# MA0_WCK01

MA0_WCK23# MA0_WCK23

VREFD2_A0 VREFC_A0

MA_VRAMRST#

+1.35VSDGPU

C2 C13 R13

R2

D2 D13 P13

P2

J12 J11

J3

H11 K10 K11 H10

K4

H5

H4

K5

J5

A5

U5

12

J1

J10

12

J13

J4

G3

G12

L3

L12

D5

D4

P5

P4

A10 U10

J14

J2

H1

K1

B5

G5

L5

T5 B10 D10

G10

L10 P10 T10 H14 K14

G1

L1

G4

L4

C5

R5 C10 R10 D11

G11

L11 P11

G14

L14

MA0_D[0..31]<18>

MA0_A[0..8]< 18>

MA1_D[0..31]<18>

MA1_A[0..8]< 18>

D D

RV79

60.4_0402_1%

1 2

DIS@

RV80

60.4_0402_1%

1 2

DIS@

Can NC For GDDR5 Spec. Can NC For GDDR5 Spec.

C C

+1.35VSDGPU

1 2

RV52 2.37K_0402_1%DIS@

1 2

RV53 5.49K_0402_1%DIS@

DIS@

1 2

CV394 1U_0201_6.3V6M

+1.35VSDGPU

1 2

RV478 2.37K_0402_1%DIS@

1 2

RV479 5.49K_0402_1%DIS@

DIS@

1 2

CV403 1U_0201_6.3V6M

+1.35VSDGPU

1 2

RV480 2.37K_0402_1%DIS@

1 2

RV481 5.49K_0402_1%DIS@

DIS@

1 2

CV404 1U_0201_6.3V6M

B B

4

A0 Channel

UV1001

EDC0 EDC3 EDC1 EDC2 EDC2 EDC1 EDC3 EDC0

DBI0# DBI3# DBI1# DBI2# DBI2# DBI1# DBI3# DBI0#

CK CK# CKE#

BA0/A2 BA2/A4 BA1/A5 BA3/A3 BA2/A4 BA0/A2 BA3/A3 BA1/A5

A8/A7 A10/A0 A9/A1 A11/A6 A10/A0 A8/A7 A11/A6 A9/A1 A12/RFU/NC

VPP/NC VPP/NC

MF SEN ZQ

ABI# RAS# CAS# CS# WE# CAS# RAS# WE# CS#

WCK01# WC K23# WCK01 WCK23

WCK23# WC K01# WCK23 WCK01

VREFD VREFD VREFC

RESET#

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

170-BALL

SGRAM GDDR5

MF=0

@

MF=0 MF=1 MF=0MF=1

DQ24 DQ0 DQ25 DQ1 DQ26 DQ2 DQ27 DQ3 DQ28 DQ4 DQ29 DQ5 DQ30 DQ6 DQ31 DQ7 DQ16 DQ8 DQ17 DQ9

DQ18 DQ10 DQ19 DQ11 DQ20 DQ12 DQ21 DQ13 DQ22 DQ14 DQ23 DQ15 DQ8 DQ16 DQ9 DQ17 DQ10 DQ18 DQ11 DQ19 DQ12 DQ20 DQ13 DQ21 DQ14 DQ22 DQ15 DQ23 DQ0 DQ24 DQ1 DQ25 DQ2 DQ26 DQ3 DQ27 DQ4 DQ28 DQ5 DQ29 DQ6 DQ30 DQ7 DQ31

H5GC4H24AJR-R0C_BGA170

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

3

2

1

A1 Channel

UV1002

+1.35VSDGPU

MA0_D6 MA0_D7 MA0_D5 MA0_D4 MA0_D2 MA0_D0 MA0_D1 MA0_D3 MA0_D10 MA0_D9 MA0_D11 MA0_D8 MA0_D15 MA0_D12 MA0_D14 MA0_D13 MA0_D23 MA0_D21 MA0_D22 MA0_D20 MA0_D19 MA0_D18 MA0_D16 MA0_D17 MA0_D24 MA0_D26 MA0_D25 MA0_D27 MA0_D28 MA0_D29 MA0_D31 MA0_D30

Byte 0

Byte 1

Byte 2

Byte 3

+1.35VSDGPU+1.35VSDGPU

RV1637

60.4_0402_1%

1 2

DIS@

RV1636

60.4_0402_1%

1 2

DIS@

+1.35VSDGPU

1 2

RV486 2.37K_0402_1%DIS@

1 2

RV487 5.49K_0402_1%DIS@

DIS@

1 2

CV407 1U_0201_6.3V6M

+1.35VSDGPU

1 2

RV482 2.37K_0402_1%DIS@

1 2

RV483 5.49K_0402_1%DIS@

DIS@

1 2

CV405 1U_0201_6.3V6M

+1.35VSDGPU

1 2

RV484 2.37K_0402_1%DIS@

1 2

RV485 5.49K_0402_1%DIS@

DIS@

1 2

CV406 1U_0201_6.3V6M

MA1_CLK

MA1_CLK#

VREFD1_A1

VREFD2_A1

VREFC_A1

+1.35VSDGPU

MA1_WCK01#<18> MA1_WCK01<18>

MA1_WCK23#<18> MA1_WCK23<18>

MA1_EDC0<18> MA1_EDC1<18> MA1_EDC3<18> MA1_EDC2<18>

MA1_DBI#0<18> MA1_DBI#1<18> MA1_DBI#3<18> MA1_DBI#2<18>

MA1_CLK< 18> MA1_CLK#<18> MA1_CKE<18>

RV131 1K _0402_1%DIS@ RV475 1K _0402_1%DIS@ RV132 120 _0402_1%

MA1_ADBI<18> MA1_CAS#<18> MA1_WE#<18> MA1_RAS#<18> MA1_CS#< 18>

MA1_EDC0 MA1_EDC1 MA1_EDC3 MA1_EDC2

MA1_DBI#0 MA1_DBI#1 MA1_DBI#3 MA1_DBI#2

MA1_CLK MA1_CLK# MA1_CKE

MA1_A4 MA1_A3 MA1_A2 MA1_A5

MA1_A0 MA1_A6 MA1_A7 MA1_A1 MA1_A8

1 2

DIS@

MA1_CAS# MA1_WE# MA1_RAS# MA1_CS#

MA1_WCK01# MA1_WCK01

MA1_WCK23# MA1_WCK23

VREFD1_A1 VREFD2_A1 VREFC_A1

MA_VRAMRST#

+1.35VSDGPU

C2

EDC0 EDC3

C13

EDC1 EDC2

R13

EDC2 EDC1

R2

EDC3 EDC0

D2

DBI0# DBI3#

D13

DBI1# DBI2#

P13

DBI2# DBI1#

P2

DBI3# DBI0#

J12

CK

J11

CK#

J3

CKE#

H11

BA0/A2 BA2/A4

K10

BA1/A5 BA3/A3

K11

BA2/A4 BA0/A2

H10

BA3/A3 BA1/A5

K4

A8/A7 A10/A0

H5

A9/A1 A11/A6

H4

A10/A0 A8/A7

K5

A11/A6 A9/A1

J5

A12/RFU/NC

A5

VPP/NC

U5

VPP/NC

J1

12 12

MF

J10

SEN

J13

ZQ

J4

ABI#

G3

RAS# CAS#

G12

CS# WE#

L3

CAS# RAS#

L12

WE# CS#

D5

WCK01# WC K23#

D4

WCK01 WCK23

P5

WCK23# WC K01#

P4

WCK23 WCK01

A10

VREFD

U10

VREFD

J14

VREFC

J2

RESET#

H1

VSS

K1

VSS

B5

VSS

G5

VSS

L5

VSS

T5

VSS

B10

VSS

D10

VSS

G10

VSS

L10

VSS

P10

VSS

T10

VSS

H14

VSS

K14

VSS

G1

VDD

L1

VDD

G4

VDD

L4

VDD

C5

VDD

R5

VDD

C10

VDD

R10

VDD

D11

VDD

G11

VDD

L11

VDD

P11

VDD

G14

VDD

L14

VDD

170-BALL

SGRAM GDDR5

A4 A2 B4 B2 E4 E2 F4 F2 A11 A13 B11 B13 E11 E13 F11 F13 U11 U13 T11 T13 N11 N13 M11 M13 U4 U2 T4 T2 N4 N2 M4 M2

B1 D1 F1 M1 P1 T1 G2 L2 B3 D3 F3 H3 K3 M3 P3 T3 E5 N5 E10 N10 B12 D12 F12 H12 K12 M12 P12 T12 G13 L13 B14 D14 F14 M14 P14 T14

A1 C1 E1 N1 R1 U1 H2 K2 A3 C3 E3 N3 R3 U3 C4 R4 F5 M5 F10 M10 C11 R11 A12 C12 E12 N12 R12 U12 H13 K13 A14 C14 E14 N14 R14 U14

MF=1

@

MF=0 MF=1 MF=0MF=1

DQ24 DQ0 DQ25 DQ1 DQ26 DQ2 DQ27 DQ3 DQ28 DQ4 DQ29 DQ5 DQ30 DQ6 DQ31 DQ7 DQ16 DQ8 DQ17 DQ9

DQ18 DQ10 DQ19 DQ11 DQ20 DQ12 DQ21 DQ13 DQ22 DQ14 DQ23 DQ15 DQ8 DQ16 DQ9 DQ17 DQ10 DQ18 DQ11 DQ19 DQ12 DQ20 DQ13 DQ21 DQ14 DQ22 DQ15 DQ23 DQ0 DQ24 DQ1 DQ25 DQ2 DQ26 DQ3 DQ27 DQ4 DQ28 DQ5 DQ29 DQ6 DQ30 DQ7 DQ31

H5GC4H24AJR-R0C_BGA170

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

+1.35VSDGPU

MA1_D7 MA1_D5 MA1_D6 MA1_D4 MA1_D3 MA1_D2 MA1_D0 MA1_D1 MA1_D8 MA1_D10 MA1_D9 MA1_D11 MA1_D12 MA1_D13 MA1_D15 MA1_D14 MA1_D31 MA1_D30 MA1_D28 MA1_D29 MA1_D25 MA1_D26 MA1_D24 MA1_D27 MA1_D16 MA1_D17 MA1_D19 MA1_D18 MA1_D21 MA1_D22 MA1_D20 MA1_D23

Byte 0

Byte 1

Byte 3

Byte 2

A4 A2 B4 B2 E4 E2 F4 F2 A11 A13 B11 B13 E11 E13 F11 F13 U11 U13 T11 T13 N11 N13 M11 M13 U4 U2 T4 T2 N4 N2 M4 M2

B1 D1 F1 M1 P1 T1 G2 L2 B3 D3 F3 H3 K3 M3 P3 T3 E5 N5 E10 N10 B12 D12 F12 H12 K12 M12 P12 T12 G13 L13 B14 D14 F14 M14 P14 T14

A1 C1 E1 N1 R1 U1 H2 K2 A3 C3 E3 N3 R3 U3 C4 R4 F5 M5 F10 M10 C11 R11 A12 C12 E12 N12 R12 U12 H13 K13 A14 C14 E14 N14 R14 U14

Decoupling Caps for single-sided 1x 10uF /per DRAM 8x 1uF /per DRAM

1

CV2421U_0201_6.3V6M

2

DIS@

8x 0.1uF /per DRAM

1

CV2431U_0201_6.3V6M

CV2471U_0201_6.3V6M

2

DIS@

1

CV2481U_0201_6.3V6M

CV3921U_0201_6.3V6M

2

DIS@

5

+1.35VSDGPU +1.35VSDGPU+1.35VSDGPU

1

CV23810U_0603_6.3V6M

A A

2

DIS@

1

CV3971U_0201_6.3V6M

CV3961U_0201_6.3V6M

2

DIS@

Decoupling Caps for Clamshell 1x 10uF /per Clamshell DRAM 8x 1uF /per Clamshell DRAM

1

CV3981U_0201_6.3V6M

2

1

CV4140.1U_0201 _10V6K

CV4150.1U_0201 _10V6K

2

DIS@

1

CV4170.1U_0201 _10V6K

CV4180.1U_0201 _10V6K

CV4160.1U_0201 _10V6K

2

DIS@

1

CV4210.1U_0201 _10V6K

CV4190.1U_0201 _10V6K

CV4200.1U_0201 _10V6K

2

DIS@

1

CV1580.1U_0201 _10V6K

CV1550.1U_0201 _10V6K

CV1570.1U_0201 _10V6K

CV1980.1U_0201 _10V6K

CV2100.1U_0201 _10V6K

2

DIS@

4

1

CV2110.1U_0201 _10V6K

2

DIS@

1

CV2300.1U_0201 _10V6K

CV2130.1U_0201 _10V6K

CV2330.1U_0201 _10V6K

CV2350.1U_0201 _10V6K

2

DIS@

1

CV46510U_0603_6.3V6M

2

DIS@

1

CV4611U_0201_6.3V6M

CV4601U_0201_6.3V6M

CV4621U_0201_6.3V6M

2

DIS@

3

1

CV4631U_0201_6.3V6M

2

DIS@

1

CV4661U_0201_6.3V6M

CV4681U_0201_6.3V6M

CV4671U_0201_6.3V6M

CV4641U_0201_6.3V6M

2

DIS@

1

CV4530.1U_0201 _10V6K

CV4520.1U_0201 _10V6K

2

DIS@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

CV4540.1U_0201 _10V6K

CV4560.1U_0201 _10V6K

CV4550.1U_0201 _10V6K

2

DIS@

1

CV4590.1U_0201 _10V6K

CV4570.1U_0201 _10V6K

CV4580.1U_0201 _10V6K

2

DIS@

Compal Secret Data

2017/12/25 2019/12/25

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

R18M-M260/G190_(7/9)_CH A

Size

Document Number Re v

Custom

DH5AV_JV_0V_LA-G021P

Date : Sheet of

DH5AV_JV_0V_LA-G021P

1

21 48Monday, December 25, 2017

1.B

5

MB0_CLK

MB0_CLK#

MB0_D[0..31]

MB0_A[0..8]

MB1_D[0..31]

MB1_A[0..8]

VREFD1_B0

VREFD2_B0

VREFC_B0

MB0_EDC1<18> MB0_EDC0<18> MB0_EDC2<18> MB0_EDC3<18>

MB0_DBI#1<18> MB0_DBI#0<18> MB0_DBI#2<18> MB0_DBI#3<18>

MB0_CLK< 18> MB0_CLK#<18> MB0_CKE<18>

MB0_ADBI<18> MB0_RAS#<18> MB0_CS#< 18> MB0_CAS#<18> MB0_WE#<18>

MB0_WCK01#<18> MB0_WCK01<18>

MB0_WCK23#<18> MB0_WCK23<18>

MB_VRAMRST#< 18>

MB0_EDC1 MB0_EDC0 MB0_EDC2 MB0_EDC3

MB0_DBI#1 MB0_DBI#0 MB0_DBI#2 MB0_DBI#3

MB0_CLK MB0_CLK# MB0_CKE

MB0_A2 MB0_A5 MB0_A4 MB0_A3

MB0_A7 MB0_A1 MB0_A0 MB0_A6 MB0_A8

RV116 1K _0402_1%LEXA@ RV476 1K _0402_1%LEXA@

1 2

RV120 120 _0402_1%

LEXA@

MB0_ADBI MB0_RAS# MB0_CS# MB0_CAS# MB0_WE#

MB0_WCK01# MB0_WCK01

MB0_WCK23# MB0_WCK23

VREFD1_B0 VREFD1_B1 VREFD2_B0 VREFC_B0

MB_VRAMRST#

+1.35VSDGPU

C2 C13 R13

R2

D2 D13 P13

P2

J12 J11

J3

H11 K10 K11 H10

K4

H5

H4

K5

J5

A5

U5

12

J1

J10

12

J13

J4

G3

G12

L3

L12

D5

D4

P5

P4

A10 U10

J14

J2

H1

K1

B5

G5

L5

T5 B10 D10

G10

L10 P10 T10 H14 K14

G1

L1

G4

L4

C5

R5 C10 R10 D11

G11

L11 P11

G14

L14

MB0_D[0..31]<18>

MB0_A[0..8]< 18>

MB1_D[0..31]<18>

MB1_A[0..8]< 18>

+1.35VSDGPU

D D

RV473

60.4_0402_1%

1 2

LEXA@

RV472

60.4_0402_1%

1 2

LEXA@

Can NC For GDDR5 Spec.

C C

+1.35VSDGPU

1 2

RV498 2.37K_0402_1%LEXA@

1 2

RV499 5.49K_0402_1%LEXA@

LEXA@

1 2

CV413 1U_0201_6.3V6M

+1.35VSDGPU

1 2

RV494 2.37K_0402_1%LEXA@

1 2

RV495 5.49K_0402_1%LEXA@

LEXA@

1 2

CV411 1U_0201_6.3V6M

+1.35VSDGPU

1 2

RV496 2.37K_0402_1%LEXA@

1 2

RV497 5.49K_0402_1%LEXA@

LEXA@

1 2

CV412 1U_0201_6.3V6M

B B

4

B0 Channel

UV1003

EDC0 EDC3 EDC1 EDC2 EDC2 EDC1 EDC3 EDC0

DBI0# DBI3# DBI1# DBI2# DBI2# DBI1# DBI3# DBI0#

CK CK# CKE#

BA0/A2 BA2/A4 BA1/A5 BA3/A3 BA2/A4 BA0/A2 BA3/A3 BA1/A5

A8/A7 A10/A0 A9/A1 A11/A6 A10/A0 A8/A7 A11/A6 A9/A1 A12/RFU/NC

VPP/NC VPP/NC

MF SEN ZQ

ABI# RAS# CAS# CS# WE# CAS# RAS# WE# CS#

WCK01# WC K23# WCK01 WCK23

WCK23# WC K01# WCK23 WCK01

VREFD VREFD VREFC

RESET#

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

170-BALL

SGRAM GDDR5

MF=0 MF=1

@

MF=0 MF=1 MF=0MF=1

DQ24 DQ0 DQ25 DQ1 DQ26 DQ2 DQ27 DQ3 DQ28 DQ4 DQ29 DQ5 DQ30 DQ6 DQ31 DQ7 DQ16 DQ8 DQ17 DQ9

DQ18 DQ10 DQ19 DQ11 DQ20 DQ12 DQ21 DQ13 DQ22 DQ14 DQ23 DQ15 DQ8 DQ16 DQ9 DQ17 DQ10 DQ18 DQ11 DQ19 DQ12 DQ20 DQ13 DQ21 DQ14 DQ22 DQ15 DQ23 DQ0 DQ24 DQ1 DQ25 DQ2 DQ26 DQ3 DQ27 DQ4 DQ28 DQ5 DQ29 DQ6 DQ30 DQ7 DQ31

H5GC4H24AJR-R0C_BGA170

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

3

2

1

B1 Channel

UV1004

@

MF=0 MF=1 MF=0MF=1

C2

EDC0 EDC3

C13

EDC1 EDC2

R13

EDC2 EDC1

R2

EDC3 EDC0

D2

DBI0# DBI3#

D13

DBI1# DBI2#

P13

DBI2# DBI1#

P2

DBI3# DBI0#

J12

CK

J11

CK#

J3

CKE#

H11

BA0/A2 BA2/A4

K10

BA1/A5 BA3/A3

K11

BA2/A4 BA0/A2

H10

BA3/A3 BA1/A5

K4

A8/A7 A10/A0

H5

A9/A1 A11/A6

H4

A10/A0 A8/A7

K5

A11/A6 A9/A1

J5

A12/RFU/NC

A5

VPP/NC

U5

VPP/NC

J1

MF

J10

SEN

J13

ZQ

J4

ABI#

G3

RAS# CAS#

G12

CS# WE#

L3

CAS# RAS#

L12

WE# CS#

D5

WCK01# WC K23#

D4

WCK01 WCK23

P5

WCK23# WC K01#

P4

WCK23 WCK01

A10

VREFD

U10

VREFD

J14

VREFC

J2

RESET#

H1

VSS

K1

VSS

B5

VSS

G5

VSS

L5

VSS

T5

VSS

B10

VSS

D10

VSS

G10

VSS

L10

VSS

P10

VSS

T10

VSS

H14

VSS

K14

VSS

G1

VDD

L1

VDD

G4

VDD

L4

VDD

C5

VDD

R5

VDD

C10

VDD

R10

VDD

D11

VDD

G11

VDD

L11

VDD

P11

VDD

G14

VDD

L14

VDD

170-BALL

SGRAM GDDR5

DQ24 DQ0 DQ25 DQ1 DQ26 DQ2 DQ27 DQ3 DQ28 DQ4 DQ29 DQ5 DQ30 DQ6 DQ31 DQ7 DQ16 DQ8 DQ17 DQ9

DQ18 DQ10 DQ19 DQ11 DQ20 DQ12 DQ21 DQ13 DQ22 DQ14 DQ23 DQ15 DQ8 DQ16 DQ9 DQ17 DQ10 DQ18 DQ11 DQ19 DQ12 DQ20 DQ13 DQ21 DQ14 DQ22 DQ15 DQ23 DQ0 DQ24 DQ1 DQ25 DQ2 DQ26 DQ3 DQ27 DQ4 DQ28 DQ5 DQ29 DQ6 DQ30 DQ7 DQ31

H5GC4H24AJR-R0C_BGA170

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

A4 A2 B4 B2 E4 E2 F4 F2 A11 A13 B11 B13 E11 E13 F11 F13 U11 U13 T11 T13 N11 N13 M11 M13 U4 U2 T4 T2 N4 N2 M4 M2

B1 D1 F1 M1 P1 T1 G2 L2 B3 D3 F3 H3 K3 M3 P3 T3 E5 N5 E10 N10 B12 D12 F12 H12 K12 M12 P12 T12 G13 L13 B14 D14 F14 M14 P14 T14

A1 C1 E1 N1 R1 U1 H2 K2 A3 C3 E3 N3 R3 U3 C4 R4 F5 M5 F10 M10 C11 R11 A12 C12 E12 N12 R12 U12 H13 K13 A14 C14 E14 N14 R14 U14

+1.35VSDGPU

MB0_D15 MB0_D14 MB0_D12 MB0_D13 MB0_D10 MB0_D9 MB0_D11 MB0_D8 MB0_D0 MB0_D1 MB0_D3 MB0_D2 MB0_D6 MB0_D5 MB0_D7 MB0_D4 MB0_D23 MB0_D21 MB0_D22 MB0_D20 MB0_D19 MB0_D18 MB0_D16 MB0_D17 MB0_D24 MB0_D26 MB0_D25 MB0_D27 MB0_D28 MB0_D29 MB0_D31 MB0_D30

Byte 1

Byte 0

Byte 2

Byte 3

+1.35VSDGPU

RV1638

60.4_0402_1%

1 2

LEXA@

RV1639

60.4_0402_1%

1 2

LEXA@

Can NC For GDDR5 Spec.

+1.35VSDGPU

1 2

RV492 2.37K_0402_1%LEXA@

1 2

RV493 5.49K_0402_1%LEXA@

LEXA@

1 2

CV410 1U_0201_6.3V6M

+1.35VSDGPU

1 2

RV488 2.37K_0402_1%LEXA@

1 2

RV489 5.49K_0402_1%LEXA@

LEXA@

1 2

CV408 1U_0201_6.3V6M

+1.35VSDGPU

1 2

RV490 2.37K_0402_1%LEXA@

1 2

RV491 5.49K_0402_1%LEXA@

LEXA@

1 2

CV409 1U_0201_6.3V6M

MB1_CLK

MB1_CLK#

VREFD1_B1

VREFD2_B1

VREFC_B1

+1.35VSDGPU

MB1_WCK01#<18> MB1_WCK01<18>

MB1_WCK23#<18> MB1_WCK23<18>

MB1_EDC0<18> MB1_EDC1<18> MB1_EDC2<18> MB1_EDC3<18>

MB1_DBI#0<18> MB1_DBI#1<18> MB1_DBI#2<18> MB1_DBI#3<18>

MB1_CLK< 18> MB1_CLK#<18> MB1_CKE<18>

RV117 1K _0402_1%LEXA@ RV477 1K _0402_1%LEXA@ RV121 120 _0402_1%

MB1_ADBI<18> MB1_CAS#<18> MB1_WE#<18> MB1_RAS#<18> MB1_CS#< 18>

MB1_EDC0 MB1_EDC1 MB1_EDC2 MB1_EDC3

MB1_DBI#0 MB1_DBI#1 MB1_DBI#2 MB1_DBI#3

MB1_CLK MB1_CLK# MB1_CKE

MB1_A4 MB1_A3 MB1_A2 MB1_A5

MB1_A0 MB1_A6 MB1_A7 MB1_A1 MB1_A8

1 2

LEXA@

MB1_ADBI MB1_CAS# MB1_WE# MB1_RAS# MB1_CS#

MB1_WCK01# MB1_WCK01

MB1_WCK23# MB1_WCK23

VREFD2_B1 VREFC_B1

MB_VRAMRST#

+1.35VSDGPU

12 12

A4 A2 B4 B2 E4 E2 F4 F2 A11 A13 B11 B13 E11 E13 F11 F13 U11 U13 T11 T13 N11 N13 M11 M13 U4 U2 T4 T2 N4 N2 M4 M2

B1 D1 F1 M1 P1 T1 G2 L2 B3 D3 F3 H3 K3 M3 P3 T3 E5 N5 E10 N10 B12 D12 F12 H12 K12 M12 P12 T12 G13 L13 B14 D14 F14 M14 P14 T14

A1 C1 E1 N1 R1 U1 H2 K2 A3 C3 E3 N3 R3 U3 C4 R4 F5 M5 F10 M10 C11 R11 A12 C12 E12 N12 R12 U12 H13 K13 A14 C14 E14 N14 R14 U14

+1.35VSDGPU

MB1_D7 MB1_D5 MB1_D6 MB1_D4 MB1_D3 MB1_D2 MB1_D0 MB1_D1 MB1_D8 MB1_D10 MB1_D9 MB1_D11 MB1_D12 MB1_D13 MB1_D15 MB1_D14 MB1_D20 MB1_D22 MB1_D21 MB1_D23 MB1_D16 MB1_D19 MB1_D17 MB1_D18 MB1_D25 MB1_D24 MB1_D26 MB1_D27 MB1_D29 MB1_D31 MB1_D30 MB1_D28

Byte 0

Byte 1

Byte 2

Byte 3

Decoupling Caps for single-sided 1x 10uF /per DRAM 8x 1uF /per DRAM 8x 0.1uF /per DRAM

1

A A

2

LEXA@

1

CV4401U_0201_6.3V6M

CV44510U_0603_6.3V6M

1

CV4411U_0201_6.3V6M

2

LEXA@

1

CV4421U_0201_6.3V6M

CV4431U_0201_6.3V6M

CV4441U_0201_6.3V6M

2

LEXA@

5

1

CV4471U_0201_6.3V6M

CV4461U_0201_6.3V6M

2

LEXA@

Decoupling Caps for Clamshell 1x 10uF /per Clamshell DRAM 8x 1uF /per Clamshell DRAM

1

CV4330.1U_0201 _10V6K

CV4320.1U_0201 _10V6K

CV4481U_0201_6.3V6M

2

LEXA@

+1.35VSDGPU+1.35VSDGPU +1.35VSDGPU

1

CV4350.1U_0201 _10V6K

CV4340.1U_0201 _10V6K

CV4360.1U_0201 _10V6K

2

LEXA@

1

CV4370.1U_0201 _10V6K

CV4390.1U_0201 _10V6K

CV4380.1U_0201 _10V6K

2

LEXA@

1

CV4230.1U_0201 _10V6K

CV4220.1U_0201 _10V6K

CV4240.1U_0201 _10V6K

2

LEXA@

4

For Layout Antenna Effect For Layout Antenna Effect

1

CV4250.1U_0201 _10V6K

CV4260.1U_0201 _10V6K

2

LEXA@

1

CV4270.1U_0201 _10V6K

2

LEXA@

1

CV4290.1U_0201 _10V6K

CV4280.1U_0201 _10V6K

CV4300.1U_0201 _10V6K

CV4310.1U_0201 _10V6K

2

DIS@

LEXA@

1

CV48110U_0603_6.3V6M

2

LEXA@

1

CV4851U_0201_6.3V6M

CV4801U_0201_6.3V6M

CV4821U_0201_6.3V6M

2

LEXA@

3

1

CV4771U_0201_6.3V6M

CV4831U_0201_6.3V6M

2

LEXA@

1

CV4841U_0201_6.3V6M

CV4791U_0201_6.3V6M

CV4781U_0201_6.3V6M

2

LEXA@

1

CV4690.1U_0201 _10V6K

2

LEXA@

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

CV4700.1U_0201 _10V6K

2

LEXA@

Issued Date

1

CV4710.1U_0201 _10V6K

CV4720.1U_0201 _10V6K

CV4730.1U_0201 _10V6K

2

LEXA@

1

CV4750.1U_0201 _10V6K

CV4740.1U_0201 _10V6K

CV4760.1U_0201 _10V6K

2

DIS@

LEXA@

Compal Secret Data

2017/12/25 2019/12/25

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

R18M-M260/G190_(8/9)_CH B

Size

Document Number Re v

Custom

DH5AV_JV_0V_LA-G021P

Date : Sheet of

DH5AV_JV_0V_LA-G021P

1

22 48Monday, December 25, 2017

1.B

5

D D

R18M-M2-60 R18M-G1-90

Power Up Ready within 20m s

VGA_ON

+3VSDGPU

+1.8VSDGPU

+0.8VSDGPU

VGA_ON_B

+VGA_CORE

(VDDCI merge VDDC)

DGPU_PWROK

C C

+1.35VSDGPU (1.35V)

Delay 3ms

Delay 5ms

Delay +3VSDGPU 7ms

VGA_ON

+3VSDGPU

+1.8VSDGPU

VGA_ON_B

+VDDCI

(0.8VSDGPU merge VDDCI)

+VGA_CORE

DGPU_PWROK

+1.35VSDGPU (1.5V)

4

Power Up Ready within 20m s

Delay 3ms

Delay +3VSDGPU 7ms

3

APU_PCIE_RS T#

PCIE_RST_L

APU

EGPIO1 40

EGPIO1 41

EGPIO1 43

PE_GPIO0

PE_GPIO1

AND GATE

VGA_ON

+3VSDGPU

AND GATE

2

Delay 3ms

+19VB

Delay 5ms

+19VB

VGA_ON_B

Delay +3VSDGPU 7ms

+19VB

DGPU_ PWRO K

PLT_RST_VGA#

DL SW

SWR

PWM

Drive r

LDO

1

2

3

4

5

PERSTB

+3VSDGPU+3VALW

+1.8VSDGPU+1.8VALW

+0.8VSDGPU

+VGA_CORE

DGPU_ PWRO K

+VDDCI

+1.35VSDGPU

1

GPU

For AMD R17M-P1-50/R18M-M2-60/R18M-G1-90 VRAM

Memory ID/Vendor/Size

000 SAMSUNG 256M x32

001 HYNI X 256M x32

010 SAMSUNG 128M x32

B B

011 HYNI X 128M x32

100 MICRON 256M x32

For AMD R18M-G1-90 VRAM Table

Memory ID/Vendor/Size

000 SAMSUNG 256M x32

001

A A

HYNI X 256M x32

100 MICRON 256M x32

Memory PN R3(ABO!) A0

UV1001 V4G_S@

(5Gb) (6Gb)

S IC D5 256M32 K4G80325FB-HC03 FBGA ABO!

SA000094R30

UV1001 V4G_H@

(5Gb) (6Gb)

S IC D5 256M32 H5GC8H24MJR-T2C BGA ABO!

SA00009ZG20

UV1001 V2G_S@

(5Gb)

S IC D5 128M32 K4G41325FE-HC28 FBGA ABO!

SA00009TT30

UV1001 V2G_H@

(5Gb)

S IC D5 128M322.5G H5GC4H24AJR-T2C ABO!

SA000085V70

UV1001 V4G_M@

(5Gb) (6Gb)

S IC D5 256M32 MT51J256M32HF-60A ABO!

SA000096K30

UV1001 V4G_S7G@

(7Gb)

S IC D5 256M32 K4G80325FB-HC28 FBGA ABO!

SA000092D00

UV1001 V4G_H7G@

(7Gb)

S IC D5 256M32 H5GC8H24MJR-R0C BGA ABO!

SA00009U110

UV1001 V4G_M7G@

(7Gb)

S IC D5 256M32 MT51J256M32HF-70A ABO!

SA00009TV10

5

UV1001 PV4G_S@

UV1001 PV4G_H@

UV1001 PV2G_S@

UV1001 PV2G_H@

UV1001 PV4G_M@

Memory PN R3(ABO!) A1

UV1002 V4G_S@

S IC D5 256M32 K4G80325FB-HC03 FBGA ABO!

SA000094R30

UV1002 V4G_H@

S IC D5 256M32 H5GC8H24MJR-T2C BGA ABO!

SA00009ZG20

UV1002 V2G_S@

S IC D5 128M32 K4G41325FE-HC28 FBGA ABO!

SA00009TT30

UV1002 V2G_H@

S IC D5 128M322.5G H5GC4H24AJR-T2C ABO!

SA000085V70

UV1002 V4G_M@

S IC D5 256M32 MT51J256M32HF-60A ABO!

SA000096K30

UV1002 PV4G_S@

UV1002 PV4G_H@

UV1002 PV2G_S@

UV1002 PV2G_H@

UV1002 PV4G_M@

(7Gb)

UV1002 V4G_S7G@

S IC D5 256M32 K4G80325FB-HC28 FBGA ABO!

SA000092D00

UV1002 V4G_H7G@

S IC D5 256M32 H5GC8H24MJR-R0C BGA ABO!

SA00009U110

UV1002 V4G_M7G@

S IC D5 256M32 MT51J256M32HF-70A ABO!

SA00009TV10

Memory PN R3(ABO!) B0 Memory PN R3(ABO!) B1

UV1003 V4G_S@

S IC D5 256M32 K4G80325FB-HC03 FBGA ABO!

SA000094R30

UV1003 V4G_H@

S IC D5 256M32 H5GC8H24MJR-T2C BGA ABO!

SA00009ZG20

UV1003 V2G_S@

S IC D5 128M32 K4G41325FE-HC28 FBGA ABO!

SA00009TT30

UV1003 V2G_H@

S IC D5 128M322.5G H5GC4H24AJR-T2C ABO!

SA000085V70

UV1003 V4G_M@

S IC D5 256M32 MT51J256M32HF-60A ABO!

SA000096K30

UV1004 V4G_S@

S IC D5 256M32 K4G80325FB-HC03 FBGA ABO!

SA000094R30

UV1004 V4G_H@

S IC D5 256M32 H5GC8H24MJR-T2C BGA ABO!

SA00009ZG20

UV1004 V2G_S@

S IC D5 128M32 K4G41325FE-HC28 FBGA ABO!

SA00009TT30

UV1004 V2G_H@

S IC D5 128M322.5G H5GC4H24AJR-T2C ABO!

SA000085V70

UV1004 V4G_M@

S IC D5 256M32 MT51J256M32HF-60A ABO!

SA000096K30

Memory PN R3(ABO!) B0 Memory PN R3(ABO!) B1Memory PN R3(ABO!) A0 Memory PN R3(ABO!) A1

UV1003 V4G_S7G@

S IC D5 256M32 K4G80325FB-HC28 FBGA ABO!

SA000092D00

UV1003 V4G_H7G@

S IC D5 256M32 H5GC8H24MJR-R0C BGA ABO!

SA00009U110

UV1003 V4G_M7G@

S IC D5 256M32 MT51J256M32HF-70A ABO!

SA00009TV10

4

UV1004 V4G_S7G@

S IC D5 256M32 K4G80325FB-HC28 FBGA ABO!

SA000092D00

UV1004 V4G_H7G@

S IC D5 256M32 H5GC8H24MJR-R0C BGA ABO!

SA00009U110

UV1004 V4G_M7G@

S IC D5 256M32 MT51J256M32HF-70A ABO!

SA00009TV10

3

AMD GPU PN

R17M-P1-50 PN R3(ROH)

UV1 RX540@

S IC 216-0905018 A1 R17M-P1-50 ABO!

SA0000ALV20

R18M-M2-60 PN R1(ROH)

UV1 R535@

S IC 216-0915006 A0 R18M-M2-60 FCBGA 769P GPU 0FA

SA0000BFE00

R18M-G1-90 PN R1(ROH)

UV1 RX565@

S IC 215-0908004 A1 R18M-G1-90 FCBGA 769P GPU 0FA

SA0000BFF00

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2017/12/25 2019/12/25

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

R18M-M260/G190_(9/9)_NOTE

Size

Document Number Re v

DH5AV_JV_0V_LA-G021P

Date : Sheet of

1

23 48Monday, December 25, 2017

1.B

5

4

3

2

1

LCD POWER CIRCUIT

C2656

1U_0201_6.3V6M

1

2

D D

ENVDD<8 >

+19VB_C PU

C C

W=60mils

SM01000EJ00 3000ma 220 ohm@1 00mh z

DCR 0.04

EDP_TXP 0<8> EDP_TXN 0< 8> EDP_TXP 1<8> EDP_TXN 1< 8> EDP_TXP 2<8> EDP_TXN 2< 8> EDP_TXP 3<8> EDP_TXN 3< 8>

U8

5

OUT

IN

GND

4

OC

EN

SY6288C20 AAC_SOT23-5

SA000079400

Vih=1.5

L11

HCB2012 KF-221T30_080 5

1 2

C371 .1U _0402_16V7K

1 2

C372 .1U _0402_16V7K

1 2

C373 .1U _0402_16V7K

1 2

C374 .1U _0402_16V7K

1 2

C2695 .1U_0 402_16V7K

1 2

C2696 .1U_0 402_16V7K

1 2

C2698 .1U_0 402_16V7K

1 2

C2697 .1U_0 402_16V7K

1

2

3

W=60mils

+INVPW R_B+

C365

68P_0402_50V8J

@EMC@

+LCDVDD+3VS

1

2

C367

4.7U_040 2_6.3V6M

W=60mils

C364

1000P_0402_50V7K

1

@EMC@

2

EDP_TXP 0_C EDP_TXN 0_C EDP_TXP 1_C EDP_TXN 1_C EDP_TXP 2_C EDP_TXN 2_C EDP_TXP 3_C EDP_TXN 3_C

1

C368

0.1U_020 1_10V6K

2

@

Place closed to JEDP1

+LCDVDD

1

C419

0.1U_020 1_10V6K

2

@

+3VALW +3VS_CAM+3VS

C102

1U_0201_6.3V6M

1

@

2

CAM_EN<3 0>

1 2

R110 0_0603_ 5%RS@

U45

@

5

OUT

IN

GND

4

OC

EN

SY6288C20 AAC_SOT23-5

SA000079400

Vih=1.5

EDP_HPD

R364 100K_04 02_5%

INVTPW M

R393 100K_04 02_5%@

C549 220P_0 402_50V7K

BKOFF#

C528 220P_0 402_50V7K

R280 10K_040 2_5%@

W=20mils

1

2

3

Place closed to JEDP1

1 2

@EMC@

1 2

@EMC@

1 2

C375

0.1U_0201_10V6K

1

2

LED PANEL Conn.

+INVPW R_B+

INVTPW M< 8>

BKOFF#<30>

EDP_HPD< 8>

+LCDVDD

HUB_USB 20_P2<33>

Touch Screen

C2735

1U_0201_6.3V6M

1

@

2

For Camera

HUB_USB 20_N2<33>

+TS_PW R

TS_EN<30>

+3VS_CA M

DMIC_CLK_ R<29> DMIC_DATA<29>

W=60mils

INVTPW M BKOFF#

EDP_HPD

EDP_AUX N_C EDP_AUX P_C

EDP_TXP 0_C EDP_TXN 0_C

EDP_TXP 1_C EDP_TXN 1_C

EDP_TXP 2_C EDP_TXN 2_C

EDP_TXP 3_C EDP_TXN 3_C

HUB_USB 20_P2 HUB_USB 20_N2

TS_EN

USB20_N 4_R USB20_P 4_R

DMIC_CLK_ R DMIC_DATA

D2015

@EMC@

YSLC05CH_ SOT23-3

SCA00000U10

2

3

1

JEDP1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37 38 39 40

G1

37

G2

38

G3

39

G4

40

G5

ACES_50 398-04041-001

CONN@

SP010013I00

41 42 43 44 45

1 2

EDP_AUX P<8> EDP_AUX N< 8>

B B

USB20_P 4<10>

USB20_N 4< 10>

A A

C370 .1U _0402_16V7K

1 2

C369 .1U _0402_16V7K

L2511

1 2

DLM0NSN 900HY2D_4P

EMC@

SM070005U00

5

EDP_AUX P_C EDP_AUX N_C

34

USB20_P 4_R

USB20_N 4_R

4

Touch Screen

+5VS +TS_PW R+3VS

1 2

R3987 0_060 3_5%@

1 2

R3986 0_060 3_5%@

Security Classification

2017/12/ 25 2019/12/ 25

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2017/12/ 25 2019/12/ 25

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Re v

Custom

Date : Sheet o f

2

Date : Sheet o f

Compal Electronics, Inc.

EDP/CAMERA/DMIC

DH5AV_JV_0V_LA-G021P

24 48Monday, December 2 5, 2017

1

1.B

5

+3VS

+5VALW

1

2

D D

C2739

0.1U_0201_10V6K

C C

+3VS

1 2

1

2

12

B B

+3VS

12

+3VS

12

C2736

10U_0603_6.3V6M

1

2

R4004 10K_0402_5%

C2747 1U_0201_6.3V6M

@

R4005

4.7K_0402_5%

@

R4009

4.7K_0402_5%

@

R4010

4.7K_0402_5%

@

R4011

4.7K_0402_5%

1

2

C2740

C2748

0.1U_0201_10V6K

APU_DP0_P0<8> APU_DP0_N0< 8>

APU_DP0_P1<8> APU_DP0_N1< 8>

APU_DP0_P2<8> APU_DP0_N2< 8>

APU_DP0_P3<8> APU_DP0_N3< 8>

RESET# RESET#

HDMI_DCIN_EN

HDMI_EQ

HDMI_I2C_ADDR

DC c oupling enable; Internal pull up, 3.3V I/O. L: DC coupling input H: Default,AC coupling input

Receiver equalization setting(Internal 150K PD) (*) L: programmable EQ for channel loss up to 5.3dB ( ) H: program mable EQ for channel loss up to 10dB ( ) M: program mable EQ for channel loss up to 14dB

I2C Slave Address select i on; I nternal pull do wn; 3. 3 V I/ O L: Default, Slave address 0x10-0x2F. H: Alternat i ve sal ve a ddr ess 0x90- 0x9F, 0x D0- 0x DF.

8

VIN

7

NC

6

VDD

5

EN

U1302

1

RT9041E-15GQW _WDFN8_2X2

SA00006K300

2

C2737

1U_0201_6.3V6M

1

2

C2741

R4006 should be placed close to REXT pin.

C2743

C2742

0.01U_0402_16V7K

Enhance Vswing

0.01U_0402_16V7K

1 2

C505 .1U_0402_ 16V7K

1 2

C506 .1U_0402_ 16V7K

1 2

C507 .1U_0402_ 16V7K

1 2

C508 .1U_0402_ 16V7K

1 2

C509 .1U_0402_ 16V7K

1 2

C510 .1U_0402_ 16V7K

1 2

C511 .1U_0402_ 16V7K

1 2

C512 .1U_0402_ 16V7K

1 2

R4006 4.99K_0402 _1%

PGOOD

+1.2V_HDMI

1

2

VOUT

GND

PGND

ADJ

1

2

3

4 9

HDMI_TX_P2 HDMI_TX_N2

HDMI_TX_P1 HDMI_TX_N1

HDMI_TX_P0 HDMI_TX_N0

HDMI_CLKP HDMI_CLKN

HDMI_DCIN_EN HDMI_EQ HDMI_I2C_ADDR

HDMI_PRE

R4012

4.99K_0402_1 %

R4013

10K_0402_1%

U2615

6

VDD12

30

VDD12

11

VDDA12

43

VDDRX12

46

VDDRX12

15

VDDTX12

18

VDDTX12

37

POWERSWITCH

38

IN_D2p

39

IN_D2n

41

IN_D1p

42

IN_D1n

44

IN_D0p

45

IN_D0n

47

IN_CLKp

48

IN_CLKn

3

DCIN_ENB

5

EQ

31

I2C_ADDR

10

RSV1

25

NC

26

RSV2

36

REXT

4

PDB

35

RESETB

27

PRE

2

TESTMODEB

PS8409AQFN48GTR2 -A0_QFN48_6X6

SA0000AC320

S IC PS8409AQFN48GTR2-A2 QFN48P REPEATER

12

@

+3VS

12

@

R4008

4.7K_0402_5%

4

+1.2V_HDMI

1

2

C2738

10U_0603_6.3V6M

VDD33 VDD33

OUT_D2p OUT_D2n

OUT_D1p OUT_D1n

OUT_D0p OUT_D0n

OUT_CLKp OUT_CLKn

SDA_SRC/AUXN SCL_SRC/AUXP

SDA_SNK SCL_SNK

HPD_SRC HPD_SNK

HDMI_ID

HDMI_CEC

CEC_EN

CSCL CSDA

EPAD

HDMI_PRE

R4007

4.7K_0402_5%

HDMI_ID

+3VS

1

2

C2744

1 24

23 22

20 19

17 16

14 13

33 34 8 7

40 21

32 9 12

29 28

49

0.01U_0402_16V7K

HDMI_RT_TX_P2 HDMI_RT_TX_N2

HDMI_RT_TX_P1 HDMI_RT_TX_N1

HDMI_RT_TX_P0 HDMI_RT_TX_N0

HDMI_RT_CLKP HDMI_RT_CLKN

APU_DP0_CTRL _DATA APU_DP0_CTRL _CLK HDMI_CTRL_DAT HDMI_CTRL_CL K

HDMI_HPD HDMI_RT_HPD

HDMI_ID

Output pre-emphasis setting;Internal pull- up 3.3V I/O L: Pre-emphasis =2.5dB H: Default, No Pre-emphasis

HDMI_ID enable ; Internal pull down;3.3V I/O L: Default, HDMI ID enable H: HDMI ID disable

2

C2746

C2745

0.1U_0201_10V6K

0.01U_0402_16V7K

R4018 0_0402_5%

12

RS@

T4958 T4959

1

2

APU_DP0_CTRL _DATA <8> APU_DP0_CTRL _CLK <8>

APU_DP0_HPD <8>

3

+5VS

1

HDMI_RT_CLKN

HDMI_RT_CLKP

HDMI_RT_TX_N0

HDMI_RT_TX_P0

HDMI_RT_TX_N1

HDMI_RT_TX_P1

HDMI_RT_TX_N2

HDMI_RT_TX_P2

2K_0402_5%

HDMI_CTRL_DAT

U74

IN

AP2330W-7_SC 59-3

SA00004ZA00

R756 0_040 2_5%RS@

R765 0_040 2_5%RS@

R769 0_040 2_5%RS@

R779 0_040 2_5%RS@

R781 0_040 2_5%RS@

R782 0_040 2_5%RS@

R783 0_040 2_5%RS@

R794 0_040 2_5%RS@

12

R4014

+5VS_DISP

W=40mils

3

OUT

2

GND

1 2

L2512

SM070003V00

@

3 4

HCM1012GH90 0BP_4P

1 2

L2513

SM070003V00

@

3 4

HCM1012GH90 0BP_4P

1 2

L2514

SM070003V00

@

3 4

HCM1012GH90 0BP_4P

1 2

L2515

SM070003V00

@

3 4

HCM1012GH90 0BP_4P

1 2

12

R4015

2K_0402_5%

1

C543

0.1U_0201_10 V6K

2

12

ZZZ

HDMI_ROYALTY

ROYALTY HDMI W/LOGO+HDCP

RO0000003HM

45@

HDMI_L_CLKN

2

C2749

@

3.3P_0402_50 V8

1

HDMI_L_CLKP

HDMI_L_TX_N0

R4020

@

150_0402_1 %

1 2

HDMI_L_TX_P0

HDMI_L_TX_N1

R4021

@

150_0402_1 %

1 2

HDMI_L_TX_P1

HDMI_L_TX_N2

R4022

@

150_0402_1 %

1 2

HDMI_L_TX_P2

R4016

47K_0402_5% @

APU_DP0_CTRL _DATA

APU_DP0_CTRL _CLKHDMI_CTRL_CL K

2

Improve Intra-pair Skew on CLK+/-

+3VS+5VS_DISP

12

R4017

47K_0402_5% @

12

1

For HDMI DDC Capacitance Leakage issue

D2016

HDMI_RT_HPD

HDMI_CTRL_CL K HDMI_CT RL_DAT

HDMI_L_CLKN

HDMI_L_CLKP

HDMI_L_TX_N0

HDMI_L_TX_P0

HDMI_L_TX_N1

HDMI_L_TX_P1

HDMI_L_TX_N2

HDMI_L_TX_P2

+5VS_DISP

@EMC@

6

I/O4

5

VDD

4

I/O3

AZC099-04S.R7G_SOT 23-6

SC300001G00

D2017

@EMC@

1

2

4

5

3

8

L05ESDL5V0NA-4 SLP2 510P8

SC300003Z00

D2018

@EMC@

1

2

4

5

3

8

L05ESDL5V0NA-4 SLP2 510P8

SC300003Z00

HDMI_RT_HPD

HDMI_CTRL_DAT HDMI_CTRL_CL K

HDMI_L_CLKN

HDMI_L_CLKP HDMI_L_TX_N0

HDMI_L_TX_P0 HDMI_L_TX_N1

HDMI_L_TX_P1 HDMI_L_TX_N2

HDMI_L_TX_P2

3

I/O2

2

GND

1

I/O1

HDMI_L_CLKN

9

10

HDMI_L_CLKP

8

9

HDMI_L_TX_N0

7

HDMI_L_TX_P0

6

HDMI_L_TX_N1

9

10

HDMI_L_TX_P1

8

9

HDMI_L_TX_N2

7

HDMI_L_TX_P2

6

HDMI connector

JHDMI1

19

HP_DET

18

+5V

17

DDC/CEC_GND

16

SDA

15

SCL

14

Reserved

13

CEC

12

CK-

11

CK_shield

10

CK+

9

D0-

8

D0_shield

7

D0+

6

D1-

5

D1_shield

4

D1+

3

D2-

2

D2_shield

1

D2+

CCM_C10004 2GR019M298ZL

CONN@

DC232003500

GND GND GND GND

20 21 22 23

+5VS_DISP

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/12/25 2019/12/25

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number R ev

Custom

Date : Sheet of

2

Date : Sheet of

Compal Electronics, Inc.

HDMI REDRIVER (PS8409)

DH5AV_JV_0V_LA-G021P

1

1.B

25 4 8Thursday, January 11, 2018

1.B

5

3

LAN-RTL8411B

+3VALW +3V_LAN

D D

60mil

CL14

1U_0201_6.3V6M

2

1

From EC

High active. EN threshold voltage min:1.2V typ:1.6V max:2.0V Current limit threshold 1.5~2.8A

+3V_LAN Rising time must >0.5ms and <100ms

C C

+3V_LAN

12

XTLI

CL18

1

2

15P_0402_50 V8J

B B

LAN_TERMAL LAN_MIDI0+ LAN_MIDI0- RJ45_MIDI0-

LAN_MIDI1+ LAN_MIDI1-

LAN_MIDI2+ LAN_MIDI2-

LAN_MIDI3+ LAN_MIDI3- RJ45_MIDI3-

1

.1U_0402_16V7K

2

RL2 0_0805_5%

1 2

@

UL1

SA000079400

5

IN

4

EN

SY6288C20AAC_SOT23 -5

LAN_PWR_EN

RL12 10K_0402_5%

@

GPO

YL1

SJ10000UP00

25MHZ_10PF_XRCGB2 5M000F2P34R0

1

NC

2

TL1

1

TCT1

2

TD1+

3

TD1-

4

TCT2

5

TD2+

6

TD2-

7

TCT3

8

TD3+

9

TD3-

10

TCT4

11

TD4+

12

TD4-

GST5009-E

CL26

SP050006B10

Place close to TCT pi n

1

OUT

2

GND

3

OC

XTLO_R

3

NC

4

24

MCT1

23

MX1+

22

MX1-

21

MCT2

20

MX2+

19

MX2-

18

MCT3

17

MX3+

16

MX3-

15

MCT4

14

MX4+

13

MX4-

60mil

LAN_PWR_EN <30>

1

15P_0402_50 V8J

CL19

2

MCT1

MCT2

MCT3

MCT4

182736

45

RJ45_GND

PU at PCH side

CL15,CL17 close to UL2

+3V_LAN

RL11 0_040 2_5%SW R@

RL13 0_040 2_5%RS@

+3VS

RJ45_MIDI0+

RJ45_MIDI1+ RJ45_MIDI1-

RJ45_MIDI2+ RJ45_MIDI2-

RJ45_MIDI3+

RPL1 75_0804_8P4 R_1%

SWR mode

1 2

LDO mode

12

RL15 1K_0402_5%

RL18 15K_0402_5%

1 2

ISOLATEB

4

reserve EC_PME# pull high 100K to +3VALW_EC

RL3 0_0402_5%RS@

RL8 10K_0402_5%

+3V_LAN

CL17 .1U_0402_ 16V7K CL15 .1U_0402_ 16V7K

LAN_GPO<30>

for disable PHY reserve 0 ohm

LAN Connector

JRJ45

8

PR4-

7

PR4+

6

PR2-

5

PR3-

4

PR3+

3

PR2+

2

PR1-

1

PR1+

SINGA_2RJ1660-0001 11F

CONN@

DC234009H00

APU_PCIE_RST#<9,15,27,28>

CLKREQ_PCIE#4<10>

PCIE_ARX_DTX_P4<6>

PCIE_ARX_DTX_N4<6> PCIE_ATX_C_DRX_P4<6> PCIE_ATX_C_DRX_N4<6>

RJ45_MIDI3-

RJ45_MIDI3+

RJ45_MIDI1-

RJ45_MIDI2-

RJ45_MIDI2+

RJ45_MIDI1+

RJ45_MIDI0-

RJ45_MIDI0+

LAN_WAKE#<30>

CLK_PCIE_P4<10> CLK_PCIE_N4< 10>

ENSWREG

1 2

1 2 1 2

XTLO_R

W=60m il

+REGOUT

RL14 1K_0402_5%

1 2

RL16

2.49K_0402_1 %

GND

LDO mode

RL1 0_0603_5%RS@

LL1

SWR@

1 2

2.2UH_HPC252 012NF-2R2M_20%

0.1U_0201_10V6K

Using for Switch mode

CL2

1

The trace length from Lx to PIN48 (REGOUT)

LDO@

2

and from C to Lx must < 200mils.

11/27: P/N change to SH00000RT00 ( S COIL 2.2UH +-20%

HPC252012NF-2R2M 1.3A)

ISOLATEB

CLK_PCIE_P4 CLK_PCIE_N4

APU_PCIE_RST# CLKREQ_PCIE#4

PCIE_ARX_C_DTX_P4 PCIE_ARX_C_DTX_N4

LAN_MIDI0+ LAN_MIDI0LAN_MIDI1+ LAN_MIDI1LAN_MIDI2+ LAN_MIDI2LAN_MIDI3+ LAN_MIDI3-

XTLI XTLO

+REGOUT

ENSWREG

LAN_RST

TP@

T4950

1 2

@

0_0402_5%

TP@

T4951

TP@

T4952

LANGND

LAN_PME#

GPO

12

+3V_LAN

12

RL17

12

11

10

9

3

12

IDC=1200mA

4.7U_0402_6.3V6M CL1

SWR@

UL2

Power Manahement/Isolation

31

ISOLATEBPIN

39

LANWAKEB

PCI-Express

23

REFCLK_P

24

REFCLK_N

30

PERSTBPIN

29

CLKREQBPIN

25

HSOP

26

HSON

21

HSIP

22

HSIN

Transceiver Interface

1

MDIP0

2

MDIN0

4

MDIP1

5

MDIN1

6

MDIP2

7

MDIN2

9

MDIP3

10

MDIN3

44

CKXTAL1

45

CKXTAL2

Regulator and Reference

36

REG_OUT

35

VDDREG

34

ENSWREG_H

46

AVDD10

47

RSET

41

LED0

38

LED1/GPO

37

LED3

40

LED_CR

RTL8411B-CGT _QFN48_6X6

CL25 10P_0402_50 V8J

12

2

3

JUMP_43X118

EMC@

DL1

MESC5V02BD03_SOT23-3

1

0.1U_0201_10V6K

2

1

Clock

LEDs

40mil40mil

RJ45_GND

@

JPL1

2

W=60m il

300mA

0.1U_0201_10V6K

CL28

1

SWR@

2

CL3

1

2

Place near Pin 3,8,33,46

Card Reader

SD_D0/MS_D1

SD_D1

SD_CLK/MS_D0

SD_CMD/MS_D2

SD_D3/MS_D3

SD_D2/MS_CLK

SD_WP/MS_BS

SD_CD# MS_CD#

AVDD33 AVDD33 DVDD33 DVDD33

DVDD10 AVDD10 AVDD10

EVDD10

Card_3V3

DV33/18

E_Pad

0.1U_0201_10V6K

CL4

CL5

CL6

1

2

SD_D0 SD_D0_R

15 14 16 17 18 19 28

42 43

48 11 12 32

33 3 8

20

13

27

49

RL9 0_0402_5%@

SD_D1 SD_D1_R

RL4 0_0402_5%@

SD_CLK

RL10 10_0402_5%

SD_CMD

RL5 0_0402_5%@ RL6 0_0402_5%@

SD_D2

RL7 0_0402_5%@

SD_WP

SD_CD#

1400 mA

300m A

800m A

+VDD33_18

0.1U_0201_10V6K

CL20

1

2

0.1U_0201_10V6K

CL7

1

2

Place near Pin 20

1 2 1 2 1 2 1 2 1 2 1 2

+3V_LAN

+LAN_VDD

CL21

4.7U_0402_6.3V6M

1

2

+LAN_VDD

1U_0201_6.3V6M

1

2

Card Uninsert

1

2

CL8

Card insert

CL22

0.1U_0201_10 V6K

Using for Switch mode

The trace length from C to PIN3 4,35 (VDDR EG) must < 200mils.

SD_CLK_R SD_CMD_R SD_D3_RSD_D3 SD_D2_R

+CARD_3V3+LAN_VDD

+3V_LAN

W=60m il

1.4A

0.1U_0201_10V6K

CL9

1

2

Protect cotact

Write protect (Lock)

Open Close

CL10

4.7U_0402_6.3V6M

1

2

Place near Pin 11, 32,48

2

1

close to pin17

Write Enable (Unlock)

Open Open Open

0.1U_0201_10V6K

CL11

1

2

CL16 5P_0402_50V8C

@EMC@

1

0.1U_0201_10V6K

CL12

1

2

Card contact

Close

CL13

Place near Pin 27

100K_0402_5 %

SD_WP#

RL21

12

WP is Normal Open

@

RL22 0_0402_5%

+3VS+3 V_LAN

12

RL20

100K_0402_5 %@

Connector side

+CARD_3V3

SD_WPSD_WP#

12

IC side

SD_WP

13

D

QL1

2

2N7002K_SOT 23-3

G

SB00000PU00

S

CL23

4.7U_0402_6.3V6M

1

2

Close to Card Reader CONN

SD_CMD_R

CL24

0.1U_0201_10V6K

SD_CLK_R

1

SD_D0_R SD_D1_R

2

SD_D2_R SD_D3_R

SD_WP# SD_CD#

DVT: 02/1 7

Vgs=1.0-2.0V

SD_CLK_R

Card Reader Connector

JSD1

6

VDD

3

CMD

7

CLK

5

VSS1

8

VSS2

9

DAT0

10

DAT1

1

DAT2

2

CD/DAT3

11

W/P

4

CD

TAITW_PSDATQ09GL BS1NN4H1

CONN@

SP011611110

RL19

1 2

0_0402_5%@EMC@

1 2

CL27

@EMC@

10P_0402_50 V8J

GND GND

12 13

Close to JREAD1 for EMI

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

2017/12/25 2019/12/25

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number R ev

Custom

Date : Sheet of

Compal Electronics, Inc.

LAN RTL8411-CG

DH5AV_JV_0V_LA-G021P

26 48Monday, December 25, 2017

1

1.B

A

Wireless LAN

60mil

+3VS +3VS_W LAN

1 2

1U_0201_6.3V6M

+3VALW

C2664

1

@

2

WLA N_ON<30>

R212 0_0805_ 5%

1

C458

4.7U_040 2_6.3V6M

2

5

4

NGFF WL+BT (KEY E)

1

@

C459

0.1U_020 1_10V6K

2

@

U2606

IN

EN

SY6288C20 AAC_SOT23-5

SA000079400

Vih=1.5

OUT

GND

1

2

3

OC

W=60mils

1

C460

0.1U_020 1_10V6K

2

+3VS_W LAN

1 1

2 2

B

1 2

PCIE_ATX_ C_DRX_P5<6 > PCIE_ATX_ C_DRX_N5<6>

PCIE_ARX_ DTX_P5<6> PCIE_ARX_ DTX_N5<6>

CLKREQ_ PCIE#5<10> WLA N_WAKE#<30>

R4027 0_040 2_5%HUB@ R4028 0_040 2_5%HUB@

R4029 0_040 2_5%NHUB@ R4030 0_040 2_5%NHUB@

CLK_PCIE_ P5<10> CLK_PCIE_ N5< 10>

1 2

1 2 1 2

12

R3807 10K_040 2_5%

HUB_USB 20_P4<33>

HUB_USB 20_N4<33>

USB20_P 3<10>

USB20_N 3< 10>

+3VS_W LAN

C

USB20_P 3_R USB20_N 3_R

JNGFF1

1

GND_1

3

USB_D+

5

USB_D-

7

GND_7

9

SDIO_CLK

11

SDIO_CMD

13

SDIO_DAT0

15

SDIO_DAT1

17

SDIO_DAT2

19

SDIO_DAT3

21

SDIO_WAKE

23

SDIO_RST

25

GND_33

27

PET_RX_P0

29

PET_RX_N0

31

GND_39

33

PER_TX_P0

35

PER_TX_N0

37

GND_45

39

REFCLK_P0

41

REFCLK_N0

43

GND_51

45

CLKREQ0#

47

PEWAKE0#

49

GND_57

51

RSVD/PCIE_RX_P1

53

RSVD/PCIE_RX_N1

55

GND_63

57

RSVD/PCIE_TX_P1

59

RSVD/PCIE_TX_N1

61

GND_69

63

RSVD_71

65

RSVD_73

67

GND_75

69

GND2

BELLW _80152-3221

CONN@

KEY E

UART_WAKE

SUSCLK(32KHz)

W_DISABLE2# W_DISABLE1#

3.3VAUX_2

3.3VAUX_4 LED1#

PCM_CLK

PCM_SYNC

PCM_OUT

PCM_IN

LED2#

GND_18

UART_TX

UART_RX UART_RTS UART_CTS CLink_RST

CLink_DATA

CLink_CLK

COEX3 COEX2 COEX1

PERST0#

I2C_DAT I2C_CLK

I2C_IRQ RSVD_64 RSVD_66 RSVD_68 RSVD_70

3.3VAUX_72

3.3VAUX_74

GND1

2 4 6 8 10 12 14 16 18 20 22

24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66

68

+3VS_W LAN

D

UART_0_ ATXD_DRXD<10>

UART_0_ ARXD_DTXD<10>

UART_0_ ARXD_R_DTXD

UART_0_ ATXD_R_DRXD

E51TXD_ P80DATA_R E51RXD_ P80CLK_R

WL_ RST#_R BT_ON WL_ OFF#

+1.8VS

5

UART_0_ ATXD_DRXD

SB000016K00

PJT138K A_SOT363-6

UART_0_ ARXD_DTXD UART_0_ ARXD_R_DTXD

UART_0_ ATXD_DRXD UART_0_ ARXD_DTXD UART_0_ ATXD_R_DRXD UART_0_ ARXD_R_DTXD

12 12

R874 1 00K_0402_5%

1 2

T4947

R873 0_0402_ 5%RS@ R3955 0_040 2_5%RS@

TP@

R440 0_0402_ 5%RS @

34

SGD

Q101A

@

SB000016K00

PJT138K A_SOT363-6

12

@

1 2

R101 1K_0402 _5%@

1 2

R102 1K_0402 _5%@

1 2

R103 1K_0402 _5%@

1 2

R104 1K_0402 _5%@

APU_PCIE_ RST# <9,15,26,28> BT_ON <3 0> WL_ OFF# <30 >

2

G

S

D

Q101B

EC_TX <30> EC_RX <3 0>

E

UART_0_ ATXD_R_DRXD

61

+1.8VS

+3VS

SP070013E00

3 3

4 4

Security Classification

2017/12/ 25 2019/12/ 25

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

2017/12/ 25 2019/12/ 25

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Re v

Custom

Date : Sheet o f

D

Date : Sheet o f

Compal Electronics, Inc.

M.2 KEY-E (WLAN)

DH5AV_JV_0V_LA-G021P

27 48Monday, December 2 5, 2017

E

1.B

A

B

SATA Re-Driver and cable HDD Conn.

C

D

E

F

G

H

G-Sensor (reserved)

RZ10

2.2K_0402_5%

I2C_1_SCL

1 2

GS@

RZ11

2.2K_0402_5%

1 1

I2C_1_SCL< 9>

I2C_1_SDA<9>

+3VS

2 2

1 2

GS@

1 2

RO10 4.7K_0402_5%@

1 2

RO15 4.7K_0402_5%@

1 2

RO13 4.7K_0402_5%@

1 2

RO18 4.7K_0402_5%PAR@

1 2

RO14 4.7K_0402_5%@

1 2

RO19 4.7K_0402_5%@

1 2

RO11 4.7K_0402_5%@

1 2

RO16 4.7K_0402_5%@

1 2

RO12 4.7K_0402_5%@

1 2

RO17 4.7K_0402_5%PAR@

1 2

RO20 4.7K_0402_5%@

1 2

RO21 4.7K_0402_5%PAR@

1 2

RO22 4.7K_0402_5%TI@

I2C_1_SDA

+1.8VALW

5

SGD

QZ1A PJT138KA_SOT363-6

Vgs=0.8-1.1V

+3VALW+1.8VALW +3VS

RZ9

2.2K_0402_5%

1 2

GS@

RZ8

2.2K_0402_5%

1 2

GS@

2

G

I2C_1_SCL_L

61

S

D

QZ1B

GS@

SB000016K00

PJT138KA_SOT363-6

34

GS@

SB000016K00

I2C_1_SDA_L

A_DE

A_EQ1

A_EQ2

B_DE

B_EQ1

B_EQ2

DEW

I2C_1_SCL_L

I2C_1_SDA_L

5

3 4

SGD

QZ3A

GS@

PJT138KA_SOT363-6

Vgs=0.8-1.1V

SATA_ATX_DRX_P0<6> SATA_ATX_DRX_N0<6>

SATA_ARX_DTX_N0<6> SATA_ARX_DTX_P0<6>

+3VS

2

G

6 1

S

D

QZ3B PJT138KA_SOT363-6

SB000016K00

RZ4

2.2K_0402_5%

1 2

GS@

RZ5

2.2K_0402_5%

1 2

GS@

CO16 0.01U_0402_16V 7K CO17 0.01U_0402_16V 7K

CO18 0.01U_0402_16V 7K CO19 0.01U_0402_16V 7K

I2C_1_SCL_G

SB000016K00

I2C_1_SDA_G

I2C_1_SCL_G

I2C_1_SDA_G

12 12

1 2

RZ2 10 K_0402_5%@

+3VS

1 2

RZ6 10 K_0402_5%GS@

B_EQ1

+3VS

CO14

12

0.01U_0402_16V7K

SATA_ATX_C_RD_DRX_P0 SATA_ATX_C_RD_DRX_N0

SATA_ARX_C_RD_DTX_N0 SATA_ARX_C_RD_DTX_P0 SATA_ARX_RD_DTX_P0

RO6

+3VS

RO5

4.7K_0402_5%

UO2

SN75LVCP601RTJR_A.4_TQFN20_4X4

TI@

SA00003ZX00

20

VDD2

1

A_INP

2

A_INN

3

GND1

4

B_OUTN

5

B_OUTP

21

GND2

REXT6EN7B_DE8A_DE9VDD1

12

4.99K_0402_1%

1 2

@

USE 8527 re-driver SA00007J U10

I2C_1_SCL_G I2C_1_SDA_G

DEW

A_EQ2

A_EQ1

17

16

B_EQ119A_EQ218A_EQ1

10

1

B_DE

A_DE

2

DEW

A_OUTP

A_OUTN

B_EQ2

B_INN B_INP

CO15

0.1U_0201_10V6K

+3VS

12

RZ1

GS@

10K_0402_5%

UZ1

8

CS

4

SCLSPC

6

SDA/SDI/SDO

7

SDO/SA0

16

ADC1

15

ADC2

13

ADC3

2

NC

3

NC

LIS3DHTR_LGA16_3X3

GS@

SA00004VF00

LIS3 DH SA0 ->0, Address is 0011 000 (0x30h) SA0 ->1, Address is 0011 001 (0x32h)

UO2 PS8527CTQFN20GTR2A_TQFN20_4X4

SA00007JU10

PAR@

SATA_ATX_RD_DRX_P0

15

SATA_ATX_RD_DRX_N0

14

B_EQ2

13

SATA_ARX_RD_DTX_N0

12 11

+3VS

Vdd_IO

+3VS

1

14

Vdd

G_INT#

11

G_INT2

INT1

9

INT2

10

RES

5

GND

12

GND

GS@

1 2

CZ1 10U_0603_6.3V6M

GS@

1 2

CZ2 0.1U_0201_10V6K

INT1/2 all High Active

G_INT#

10K_0402_5%

+3VS

12

RZ3

GS@

RZ7 0_0402_5%

1 2

GS@

G_INT#_APU <9>

JHDD1,J HDD2Co -Lay

+5VS_HDD

12

CO12

10U_0603_6.3V6M

100mils

1

2

CO13

0.1U_0201_10V6K

@

Check INT pin

SATA_ARX_RD_DTX_P0 SATA_ARX_RD_DTX_N0

SATA_ATX_RD_DRX_N0 SATA_ATX_RD_DRX_P0

1 2

RO3 0_0805_5%RS@

+5VS

G_INT2 JHDD_P9

1 2

RO4 0_0402_5%@

12

CO4 0.0 1U_0402_16V7K

12

CO3 0.0 1U_0402_16V7K

12

CO2 0.0 1U_0402_16V7K

12

CO1 0.0 1U_0402_16V7K

SATA_ARX_C_DTX_P0 SATA_ARX_C_DTX_N0

SATA_ATX_C_DRX_N0 SATA_ATX_C_DRX_P0

close to CONN.

+3VS

+5VS_HDD

JHDD2

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

G1

22

G2

23

G3

24

G4

ACES_50406-02071-001

CONN@

SP010016L00

+5VS_HDD

JHDD_P9 JHDD_P8JHDD_P8

SATA_ARX_C_DTX_P0 SATA_ARX_C_DTX_N0

SATA_ATX_C_DRX_N0 SATA_ATX_C_DRX_P0

JHDD1

14

GND

13

GND

12

11

10

9

8

7

6

5

4

3

2

1

ACES_51625-01201-001

CONN@

SP010028W00

SATA NGFF SSD Conn.

JSSD1

3 3

PCIE SSD

SATA SSD

4 4

A

PCIE_ARX_DTX_N3<6> PCIE_ARX_DTX_P3<6>

PCIE_ATX_C_DRX_N3<6> PCIE_ATX_C_DRX_P3<6>

PCIE_ARX_DTX_N2<6> PCIE_ARX_DTX_P2<6>

PCIE_ATX_C_DRX_N2<6> PCIE_ATX_C_DRX_P2<6>

PCIE_ARX_DTX_N1<6> PCIE_ARX_DTX_P1<6>

PCIE_ATX_C_DRX_N1<6> PCIE_ATX_C_DRX_P1<6>

PCIE_ARX_DTX_N0<6> PCIE_ARX_DTX_P0<6>

PCIE_ATX_C_DRX_N0<6> PCIE_ATX_C_DRX_P0<6>

SATA_ARX_DTX_P1<6> SATA_ARX_DTX_N1<6>

SATA_ATX_DRX_N1<6> SATA_ATX_DRX_P1<6>

B

PCIE_ARX_DTX_N3 PCIE_ARX_DTX_P3

PCIE_ATX_C_DRX_N3 PCIE_ATX_C_DRX_P3

PCIE_ARX_DTX_N2 PCIE_ARX_DTX_P2

PCIE_ATX_C_DRX_N2 PCIE_ATX_C_DRX_P2

PCIE_ARX_DTX_N1 PCIE_ARX_DTX_P1

PCIE_ATX_C_DRX_N1 PCIE_ATX_C_DRX_P1

PCIE_ARX_DTX_N0 PCIE_ARX_DTX_P0

PCIE_ATX_C_DRX_N0 PCIE_ATX_C_DRX_P0

SATA_ARX_DTX_P1 SATA_ARX_DTX_N1

SATA_ATX_DRX_N1 SATA_ATX_DRX_P1

AGPIO8<9>

1 2

RM26 0_0402 _5%T1PCIE@

1 2

RM25 0_0402 _5%T1PCIE@

1 2

RM24 0_0402 _5%T1PCIE@

1 2

RM23 0_0402 _5%T1PCIE@

1 2

RM11 0_0402 _5%PCIE@

1 2

RM12 0_0402 _5%PCIE@

SATA@

1 2

CM7 0.01U_0402_16V7K

1 2

CM8 0.01U_0402_16V7K

SATA@

1 2

CM9 0.01U_0402_16V7K

1 2

CM10 0.01U_0402_16V7K

SATA@

CLK_PCIE_N0<10> CLK_PCIE_P0<10>

1 2

RM22 0_0402 _5%@

C

CLK_PCIE_N0 CLK_PCIE_P0

SSD_DET#

SSD_DET# Function

10PCIE SSD Device

SATA SSD Device

PCIE_ARX_R_DTX_N3 PCIE_ARX_R_DTX_P3

PCIE_ARX_R_DTX_N2 PCIE_ARX_R_DTX_P2

PCIE_ARX_R_DTX_N0 PCIE_ARX_R_DTX_P0

LON/SAM:Pin61=GND

1

GND

3

GND

5

PERn3

DTx3

7

PERp3

9

GND

11

PETn3

DRx3

13

PETp3

15

GND

17

PERn2

DTx2

19

PERp2

21

GND

23

PETn2

DRx2

25

PETp2

27

GND

29

PERn1

DTx1

31

PERp1

33

GND

35

PETn1

DRx1

37

PETp1

39

GND

41

PERn0/SATA-B+

43 45 47 49 51 53 55 57

59

63 65 67

D

DTx0

PERp0/SATA-BGND PETn0/SATA-A-

DRx0

PETp0/SATA-A+ GND REFCLKN REFCLKP GND

Pin67 Pin68

NC

Pin69 Pin70

PEDET(NC-PCIE/GND-SATA)613P3VAUX

Pin71 Pin72

GND

Pin73 Pin74

GND

Pin75

GND

BELLW_80159-3221

CONN@

SP070018L00

SUSCLK(32kHz)

3P3VAUX 3P3VAUX

DAS/DSS#

3P3VAUX 3P3VAUX 3P3VAUX 3P3VAUX

DEVSLP

PERST#

CLKREQ#

PEWake#

3P3VAUX 3P3VAUX

GND1 GND2

NC NC

NC NC NC NC NC NC NC NC NC

NC NC NC NC NC

NC NC

+3VS_SSD_NGFF

2 4 6

LON/SAM:Pin10=Device_Active_Signa l

8

SSD_LED#

10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58

60 62 64 66

68 69

TP@

T245

LON:If system didn't support DEVSLP, set Device Sleep Signal high and keep (from power on), device will ignore.

DEVSLP1_R

SSD_PCIE_RST# CLKREQ_PCIE#0_R

SUSCLK_SSD

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

E

TP@

RM21 0_0402 _5%@

RM20 0_0402 _5%RS@

CM15 100P_0402_50V8JEMC@

1 2

RM18 0_0402 _5%@

1 2

RM5 0_0402_5%@

T246

1 2

DEVSLP1 <9>

APU_PCIE_RST# <9,15,26,2 7>

CLKREQ_PCIE#0 <10>

Compal Secret Data

2017/12/25 2019/12/25

Compal Secret Data

F

Deciphered Date

RM9 0_1206_5%

1 2

+3VS_SSD_NGFF+3VS

RS@

1

2

G

1

+

CM16

PCIE@

150U_B2_6.3VM_R35M

CM13

CM14

2

SGA00009M00

2

0.1U_0201_10V6K

22U_0603_6.3V6M

Compal Electronics, Inc.

Title

Size

Custom

Date : Sheet of

HDD/SSD

Document Number Re v

DH5AV_JV_0V_LA-G021P

H

1.B

28 48Monday, December 25, 2017

1.B

A

B

C

D

E

HD Audio Codec

SM01000EJ00 3000mA 220ohm@100mhz DCR 0.04

LA1

+VDDA

HCB2012KF-221 T30_0805

1 1

Pin9 need to matching with SOC HDA interface.

CA32 10P_0402_50 V8J

1 2

2 2

GND

HP_PLUG#<33>

+1.8VS

+3VS

@EMC@

Idea is close to IC

+3VS

RA2 0_0402_5%@

RA5 0 _0402_5%@

DMIC_CLK

12

Combo MIC

DMIC_CLK_R<24>

EC_MUTE#<30>

HDA_RST#_R<9>

10mil

RA13 200K_0402_1 % RA14 100K_0402_1 %

40mil

Close codec

10U_0603_6.3V6M

RING2 SLEEVE

DMIC_DATA<24>

1 2

LA6 BLM15PX221SN1D_ 2PEMC@

EC_MUTE# HDA_RST#_R

CA1

12

Place near Pin41

+MICBIAS

RA42 0_0 402_5%

12 12

GND

Pin20 ALC255/256/233 : Power for combo jack depop circuit at system shutdown mode

3 3

Pin4 ALC255/256/233 : DC DET (For Japen customer only)

GNDA

GND

40mil

CA2

0.1U_0201_10V6K

2

1

GND GND

1 2

CA5 10U_0603_6.3V6M

12

CA6 0.1U_0201_1 0V6K

Place near Pin9

20mil

10U_0603_6.3V6M

CA10

1

2

Place near Pin1

LINE1-L LINE1-R

+MICBIAS

DMIC_DATA DMIC_CLK

1 2

RESETB

255@

MONO_IN

SENSE_AHP_PLUG#

1

CA19

2.2U_0402_6.3 V6M

2

3V_1.8V_PVDD

12

CA3510U_0603_6.3V6M

3V_5V_STB

RA44 0_0402_ 5%@

12

10U_0603_6.3V6M

CA34

1 2

Place near Pin46

+1.8VS_DVDDIO

+3VS_DVDD

0.1U_0201_10V6K CA11

1

2

GND

22 21

24 23

17 18

31 30

2 3

47 11

12

13 14

37 35

36

20

12

19

CA2210U_0603_6.3 V6M

4

49

0.1U_0201_10V6K CA3

2

@

1

UA1

LINE1-L(PORT-C-L) LINE1-R(PORT-C-R)

LINE2-L(PORT-E-L) LINE2-R(PORT-E-R)

MIC2-L(PORT-F-L) /RING2 MIC2-R(PORT-F-R) /SLEEVE

LINE1-VREFO-L LINE1-VREFO-R

GPIO0/DMIC-DATA GPIO1/DMIC-CLK

PDB RESETB

PCBEEP

SENSE A SENSE B

CBP CBN

CPVDD

CPVREF

MIC-CAP

DVSS Thermal PAD

ALC255-CG_MQFN48 _6X6

255@

SA000082700

GND

1

+PVDD_HDA

+AVDD1_HDA

GNDA

Place near Pin26

+1.8VS_VDDA

26

41

9

DVDD

DVDD-IO

PVDD1

46

AVDD1

PVDD2

40

AVDD2

SPK-OUT-L-

SPK-OUT-L+

SPK-OUT-R+

SPK-OUT-R-

HPOUT-L(PORT-I-L)

HPOUT-R(PORT-I-R)

SYNC BCLK

SDATA-OUT

SDATA-IN

SPDIF-OUT/GPIO2

MONO-OUT

MIC2-VREFO

LDO3-CAP LDO2-CAP LDO1-CAP

VREF

JDREF CPVEE

AVSS1 AVSS2

0.1U_0201_10V6K

1

@

2

1

2

GNDA

Place near Pin40

43 42

45 44

32 33

HDA_SYNC_R

10

HDA_BIT_CLK_R

6

HDA_SDOUT_R

5

HDA_SDIN0_R

8

48

16

29

7 39 27

CODEC_VREF

28

15 34

CPVEE

25 38

GND

CA8

CA12

0.1U_0201_10V6K

@

SPKLSPKL+

SPKR+ SPKR-

HP_LEFT HP_RIGHT

RA10 0_0402_ 5%

GNDA

RA21

DOS mode

EC_BEEP#< 30>

OS mode

APU_SPKR<9>

+3VS_DVDD

+1.8VS

4 4

+3VALW

+5VALW

RA36 0_0 402_5%

RA37 0_0 402_5%

for ALC256 co-lay

22K_0402_5%

RA22 22K_0402_5%

1 2

255@

1 2

256@

1 2

255@

RA43 0_0 402_5%

1 2

256@

RA35 0_0 402_5%

A

BEEP#_R

12

3V_1.8V_PVDD

3V_5V_STB

GND & GNDA moat

CA28

100P_0402_50V8J

@EMC@

CA27

255@

.1U_0402_16V7K

1 2

1

10/20 vendor review change to 0.1uF.

RA23

4.7K_0402_5%

2

1 2

GND

MONO_IN

GND & GNDA moat

JPA2 JUMP_43X39

112

@

JPA4 JUMP_43X39

112

@

CA31

@EMC@

.1U_0402_16V7K

1 2

RA25 0_040 2_5%@EMC@

B

JPA3 JUMP_43X39

2

112

@

JPA5 JUMP_43X39

2

112

@

JPA6 JUMP_43X39

2

112

@

JPA7 JUMP_43X39

2

112

@

GNDAGNDGND GNDA

(output = 300 mA)

+5VS

40mil

.1U_0402_16V7K

1

2

@EMC@

20mil

RA1

CA9

10U_0603_6.3V6M

12

CA13

12

1 2

@EMC@

RA33 33_0402 _5%

1 2

RA51 0_040 2_5%256@

1 2

CA33 .1U_0402_16V7K

CA18 10U_0603_6.3V6M CA20 10U_0603_6.3V6M CA21 10U_0603_6.3V6M

1 2

RA15 100K_0 402_5%

1

2.2U_0402_6.3 V6M

2

JPA1

112

CA4

JUMP_43X79

@

GND & GNDA moat

1 2

@

0_0603_5%

GND & GNDA moat

RA6

10U_0603_6.3V6M

0_0402_5%

1 2

CA15 22P _0402_50V8J

@EMC@

1 2

256@

+MIC2_VREFO

12 12 12

CA26

2

@

HDA_SYNC_R <9>

HDA_BIT_CLK_R <9>

DMIC_DATA34

BEEP#_R

GND

Pin15 ALC255/256/233 : Jack Detect for SPDIF-OUT and SPK-OUT port

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

40mil

4.75V

+VDDA

12

+VDDA

+1.8VS

GND

HDA_SDOUT_R <9>

HDA_SDIN0 < 9>

GND

GNDA

10mil

CA23

0.1U_0201_10V6K

2.2U_0402_6.3V6M

1

2

@

Place near pin28

2017/12/25 2019/12/25

CA24

GNDA

1

2

DMIC3/4 Conn. (support on 256)

+3VS

DA4

6

I/O4

5

VDD

4

I/O3

AZC099-04S.R7G_SOT 23-6

256EMC@

SC300001G00

Int. Speaker Conn.

SPKR+ SPKRSPKL+ SPKL-

EMI request for solve EMI noise, SM01000OW00.

Headphone Out

HP_RIGHT HPOUT_R_1

LINE1-L

D

LINE1-R

DA5

1

BAT54A_SOT23-3

SCSBAT54100

+MICBIAS

Compal Secret Data

Deciphered Date

I/O2

GND

I/O1

RA19

2.2K_0402_5%

1 2

RA24 0_060 3_5%@

1 2

RA27 0_060 3_5%@

CA29 4.7U_0402_6.3V6M

CA30 4.7U_0402_6.3V6M

2

3

+MIC2_VREFO

+3VS_DVDD

12

256@

RA41

3.3K_0402_5%

for ALC256 co-lay

DMIC_CLK34

3

2

GND

DMIC_DATA34

1

1 2

LA2EMC@ PBY160808T-121 Y-N_2P

1 2

LA3EMC@ PBY160808T-121 Y-N_2P

1 2

LA4EMC@ PBY160808T-121 Y-N_2P

1 2

LA5EMC@ PBY160808T-121 Y-N_2P

TVNST52302AB0_ SOT523-3

12

RA20

2.2K_0402_5%

SLEEVE RING2

HPOUT_L_1HP_LEFT

1 2

12

RA29

4.7K_0402_5%

12

RA32

4.7K_0402_5%

Title

Size Document Number R ev

Custom

Date : Sheet of

12

256@

RA50

3.3K_0402_5%

MONO_IN

RESETB

+3VS

DMIC_DATA34 DMIC_CLK34DMIC_CLK

1 2

256@

RA46 0_040 2_5%

GND

40mil

2

3

2

@EMC@

DA1

1

GND GND

SLEEVE <33> RING2 <33>

Compal Electronics, Inc.

HDA CODEC (ALC255/256)

DH5AV_JV_0V_LA-G021P

SPK_R+ SPK_RSPK_L+ SPK_L-

3

@EMC@

DA2 TVNST52302AB0_ SOT523-3

1

HPOUT_L_1 < 33>

HPOUT_R_1 <33>

E

GND

JDMIC1

1

2

3

4

5

G5

6

G6

ACES_50273-004 0N-001

SP02000TI00

JSPK1

1

2

3

4

5

G1

6

G2

ACES_50278-004 01-001

CONN@

SP02000RR00

29 4 8Monday, December 25, 2017

1.B

5

D D

1 2

KBRST#<10>

1 2

C1263 22P_0402_50 V8J

C819 1000P_0402_5 0V7K

C C

B B

1 2

@EMC@

R1560 10_0402_1%

1 2

EMC@

1 2

R207 100K_040 2_5%

1 2

C1279 1 00P_0402_50V8J

LPC_CLK0_EC

@EMC@

EC_RST#

LPC_RST#

@

@EMC@

Change for New Charger IC

RS@

R3973 0_0402_5%

SYS_PWRGD_EC is OD-Pin

+3VLP

SYS_PWRGD_EC< 9> PWR_SUSP_ LED#<33>

4

JP2

112

JUMP_43X39

SERIRQ<10,31>

LPC_FRAME#<10,3 1>

LPC_AD3_R<31> LPC_AD2_R<31> LPC_AD1_R<31> LPC_AD0_R<31>

LPC_CLK0_EC<10>

LPC_RST#<10,31>

EC_RST#< 32> EC_SCI#<10>

WLAN_ON<27>

KSI[0..7]< 31>

KSO[0..17]<31>

EC_SMB_CK1<37,38> EC_SMB_DA1<37,38> EC_SMB_CK2<8,16,34> EC_SMB_DA2<8,16,34>

SLP_S3#<9>

TP_I2C_INT#<31 >

CHG_CTL3<33> TP_3V_EN<31 > WL_OFF#<27>

WLAN_WAKE#<27>

CAM_EN<24>

SPOK<39> FAN_SPEED1<32> FAN_SPEED2<32>

EC_TX<27>

EC_RX<27>

NUM_LED#<31>

PBTN_OUT#<9>

SLP_S5#< 9,38>

+EC_VCC

@

2

C1255

0.1U_0201_10V6K

C1256

0.1U_0201_10V6K

2

1

KBRST#_R

SERIRQ LPC_FRAME#

LPC_AD3_R LPC_AD2_R LPC_AD1_R LPC_AD0_R

LPC_CLK0_EC LPC_RST# EC_RST# EC_SCI# WLAN_ON

KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17

EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2

SLP_S3# TP_I2C_INT# CHG_CTL3 TP_3V_EN WL_OFF# WLAN_WAKE# CAM_EN

SPOK FAN_SPEED1

FAN_SPEED2 EC_TX EC_RX SYS_PWRGD_EC PWR_SUSP_ LED# NUM_LED#

PBTN_OUT# SLP_S5#

C1257

0.1U_0201_10V6K

1000P_0402_50V7K

C1258

0.1U_0201_10V6K

2

@

1

GATEA20/GPIO00

2

KBRST#/GPIO01

3

SERIRQ

4

LPC_FRAME#

5

LPC_AD3

7

LPC_AD2

8

LPC_AD1

10

LPC_AD0

12

CLK_PCI_EC

13

PCIRST#/GPIO05

37

EC_RST#

20

EC_SCI#/GPIO0E

38

CLKRUN#/GPIO1D

55

KSI0/GPIO30

56

KSI1/GPIO31

57

KSI2/GPIO32

58

KSI3/GPIO33

59

KSI4/GPIO34

60

KSI5/GPIO35

61

KSI6/GPIO36

62

KSI7/GPIO37

39

KSO0/GPIO20

40

KSO1/GPIO21

41

KSO2/GPIO22

42

KSO3/GPIO23

43

KSO4/GPIO24

44

KSO5/GPIO25

45

KSO6/GPIO26

46

KSO7/GPIO27

47

KSO8/GPIO28

48

KSO9/GPIO29

49

KSO10/GPIO2A

50

KSO11/GPIO2B

51

KSO12/GPIO2C

52

KSO13/GPIO2D

53

KSO14/GPIO2E

54

KSO15/GPIO2F

81

KSO16/GPIO48

82

KSO17/GPIO49

77

EC_SMB_CLK1/GPIO44

78

EC_SMB_DAT1/GPIO45

79

EC_SMB_CLK2/GPIO46

80

EC_SMB_DAT2/GPIO47

6

PM_SLP_S3#/GPIO04

14

GPIO07

15

GPIO08

16

GPIO0A

17

GPIO0B

18

GPIO0C

19

AC_PRESENT/GPIO0D

25

PWM2/GPIO11

28

FAN_SPEED1/GPIO14

29

FANFB1/GPIO15

30

EC_TX/GPIO16

31

EC_RX/GPIO17

32

PCH_PWROK/GPIO18

34

SUSP_LED#/GPIO19

36

NUM_LED#/GPIO1A

122

PBTN_OUT#/GPIO5D

123

PM_SLP_S4#/GPIO5E

U44

KB9022QD_LQFP12 8_14X14

C1261

C1259

1000P_0402_50V7K

1

2

LPC & MISC

Int. K/B Matrix

FBM-11-160808- 601-T_0603

SM Bus

3

L44

1 2

9

22

33

67

96

111

125

VCC

VCC0

VCC_LPC

PWM Output

PS2 Interface

AVCC

EC_VCCST_PG/GPIO0F

EC_FAN_PWM/GPIO12

VCIN1_BATT_TEMP/AD0/GPIO38

VCIN1_BATT_DROP/AD1/GPIO39

AD Input

DA Output

ADP_I/AD2/GPIO3A

AD_BID/AD3/GPIO3B

EN_DFAN1/DA1/GPIO3D

EC_MUTE#/PSCLK1/GPIO4A

USB_EN#/PSDAT1/GPIO4B

WOL_EN/GPXIOA01

VCIN0_PH1/GPXIOD00

SPI Device Interface

SPI Flash ROM

EC_CIR_RX/AD6/GPIO40

SYS_PWROK/AD7/GPIO41

BATT_CHG_LED#/GPIO52

CAPS_LED#/GPIO53

GPIO

PWR_LED#/GPIO54

BATT_LOW_LED#/GPIO55

DPWROK_EC/GPIO59

EC_RSMRST#/GPXIOA03

VCIN1_ADP_PROCHOT/GPXIOA05

VCOUT1_PROCHOT#/GPXIOA06

VCOUT0_MAIN_PWR_ON/GPXIOA07

GPIO

GND

11

24

35

BKOFF#/GPXIOA08

GPO

PCH_PWR_EN/GPXIOA10

PWR_VCCST_PG/GPXIOA11

VCIN1_AC_IN/GPXIOD01

ON/OFF#/GPXIOD03

GPI

LID_SW#/GPXIOD04

GND

AGND

GND

69

94

113

ECAGND

+EC_VCCA

2

C1262

0.1U_0201_10 V6K

1

ECAGND

BEEP#/GPIO10

AC_OFF/GPIO13

AD4/GPIO42 AD5/GPIO43

DA0/GPIO3C

DA2/GPIO3E DA3/GPIO3F

PSCLK2/GPIO4C

PSDAT2/GPIO4D

TP_CLK/GPIO4E

TP_DATA/GPIO4F

ENKBL/GPXIOA00

ME_EN/GPXIOA02

MISO/GPIO5B

MOSI/GPIO5C SPICLK/GPIO58 SPICS#/GPIO5A

GPIO50

SYSON/GPIO56 VR_ON/GPIO57

GPXIOA04

GPXIOA09

EC_ON/GPXIOD02

SUSP#/GPXIOD05

GPXIOD06

PECI/GPXIOD07

V18R/VCC_IO2

L43

FBM-11-160808- 601-T_0603

12

20mil

LAN_PWR_EN

21

EC_BEEP#

23

FAN_PWM1

26

FAN_PWM2

27

BATT_TEMP

63

VCIN1_BATT_DROP

64

ADP_I

65

AD_BID

66 75

LAN_WAKE#

76

TS_EN

68

GPU_THERMAL#

70

TP_SENOFF#

71

KBL_EN

72

TYPEC_1P5A

83

TYPEC_3A

84

EC_MUTE#

85

USB_EN

86

TP_CLK

87

TP_DATA

88

CHG_CTL1

97

GPU_ACIN

98

0.9VS_PWR_EN #

99

9022_PH1

109

EC_RTCRST

119

BT_ON

120

USB_HUB_RESET #

126

FP_PWR_EN

128

CHG_EN

73 74

VGATE BATT_4S

89

BATT_BLUE_LED #

90

CAPS_LED#

91

PWR_LED#

92

BATT_AMB_LED#

93 95

SYSON VR_ON

121

0.9_1.8VALW_PW REN

127

EC_RSMRST#

100

CHG_ILMSEL

101

9022_VCIN

102

EC_THERM

103 104

MAINPWON

105

BKOFF# LAN_GPO

106

3V_EN_R_EC

107 108

THERMTRIP#

110

ACIN EC_ON

112 114

ON/OFFBTN# LID_SW#

115 116

SUSP#

117

ENBKL EC_TYPEC_EN#

118

124

LAN_PWR_EN <26> EC_BEEP# < 29> FAN_PWM1 <32> FAN_PWM2 <32>

BATT_TEMP <37,38> VCIN1_BATT_DROP <37>

ADP_I <3 7,38>

LAN_WAKE# <26>

TS_EN <24> GPU_THERMAL# <16>

TP_SENOFF# < 31>

KBL_EN <31>

TYPEC_1P5A <34> TYPEC_3A <34>

EC_MUTE# <29> USB_EN < 33> TP_CLK <31> TP_DATA <31>

CHG_CTL1 <33>

GPU_ACIN <1 6>

0.9VS_PWR_EN # <35> 9022_PH1 <37 >

BT_ON <27> USB_HUB_RESET # < 33> FP_PWR_EN <3 1>

CHG_EN <33> VGATE <42>

BATT_4S <38> BATT_BLUE_LED # <33> CAPS_LED# <31>

PWR_LED# <33>

BATT_AMB_LED# <33>

SYSON <40>

VR_ON < 41,42>

0.9_1.8VALW_PW REN < 41>

EC_RSMRST# <9> CHG_ILMSEL <33>

9022_VCIN <37>

MAINPWON <32,37,3 9> BKOFF# <24> LAN_GPO < 26>

THERMTRIP# <8>

ACIN <38 >

EC_ON < 39>

ON/OFFBTN# <31 > LID_SW# <31> SUSP# <35,38,40> ENBKL <8>

EC_TYPEC_EN# <34>

+EC_VCC

2

Board ID / Rb

DH5JV

DH5AV

DH50V

Reserve TS_EN

New Add for GPU Thermal

New Add for PW I Limit

PS2

Change for New Charger IC

Reserve for HUB RST#

Reserve for FP

Change for New Charger IC

Add for Type-C PW

1

2

3

R1564

EJ@

12K_0402_1%

SD034120280

R1564

EA@

15K_0402_1%

SD034150280

R1564

VX@

20K_0402_1%

SD034200280

EC_RTCRST

EC_MUTE# TP_I2C_INT#

EC_SMB_DA1 EC_SMB_CK1 LID_SW#

BATT_TEMP

ACIN

EC_RSMRST#

SYSON 3V_EN

EC_THERM

MAINPWON

3V_EN_R_EC

SPOK

Ra

Rb

+EC_VCC

12

R1562 100K_0402_5 %

AD_BID

12

R1564 20K_0402_1%@

12

R1563 10K_0402_5%

R1565 10K_0402_5 %@ R116 1K_0402_5%@

R1577 2.2K_0402_5% R1574 2.2K_0402_5% R344 47K_0402_5%

R3907 47K_0402_ 5%@ R1675 100K_0402 _5%@ R940 1M_04 02_5%

1 2

RS@

R1690

0_0402_5%

2

C1269

0.1U_0201_10 V6K

1

+RTC_APU_R

13

D

2

G

S

1 2 1 2

1 2 1 2 1 2

1 2

C1265 100P_0402_50V8J

1 2

C1266 100P_0402_50V8J

1 2 1 2 1 2

1 2

D2012

@

RB751V-40_SOD32 3-2

1 2

R3926 1K_0402_5 %

1 2

D2013 RB751V-40_SOD32 3-2

1 2

D2014 RB751V-40_SOD32 3-2

EC_RSMRST#

@

SYS_PWRGD_EC

@

1

@

Q91 2N7002K_SOT 23-3

SB00000PU00

Vgs=1.0-2.0V

+3VS

+EC_VCC

APU_PROCHOT# <8,38,42>

3V_EN

3V_EN <39>

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/12/25 2019/12/25

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number R ev

Custom

Date : Sheet of

2

Date : Sheet of

Compal Electronics, Inc.

EC ENE-KB9022

DH5AV_JV_0V_LA-G021P

1

1.B

30 4 8Monday, December 25, 2017

1.B

ON/OFF BTN

+3VLP

ON/OFFBTN#< 30>

Test Only

BOT

R534 100K_0402_5 %

12

34

SWK1 NTC013-AA1J-A160T _4P

12

SN10000CV00

ON/OFFBTN#

@

TP/B Conn.

ACES_51524-008 01-001

SP01001A910

Lid Switch

(Hall Effect Switch)

LID_SW#<30>

LID_SW#

+3VLP

JHS1

1

2

3

4

5

GND

6

GND

ACES_51524-004 0N-001

CONN@

SP010022M00

TPM

+3VALW +3VALW_TP M +3VS +3VS_TPM

RW1 0_0603_5%

1 2

RS@

BADD

1 AEh(write), AFh(read)

*

LPC_CLK1_T PM<10>

LPC_FRAME#<10,3 0>

SELECTION

1 2

LPC_RST#<10,30> SERIRQ<10,30>

CLKRUN#< 10>

10U_0603_6.3V6M

CW1

1

2

TPM@

RW310K_0402_ 5% @

CLKRUN PH 10K to +3VS at APU side

CW2

0.1U_0201_10V6K

1

2

TPM@

TPM_BADD

LPC_AD0_R LPC_AD1_R LPC_AD2_R LPC_AD3_R

LPC_CLK1_T PM

near pin5

LPC_AD0<10> LPC_AD1<10> LPC_AD2<10> LPC_AD3<10>

29 30

24 21 18 15

19 20 17 27 13 28

SA00008ELE0

RW4 3 3_0402_5%

RW2 0_0603_5%

1 2

RS@

10U_0603_6.3V6M

1

2

TPM@

1 2

RW5 0 _0402_5%

1 2

RW6 0 _0402_5%

1 2

RW7 0 _0402_5%

1 2

RW8 0 _0402_5%

UW1

TPM@

XOR_OUT/SDA/GPIO0 SCL/GPIO1

3

GPX/GPIO2

6

GPIO3/BADD

LAD0/MISO LAD1/MOSI LAD2/SPI_IRQ# LAD3

LCLK/SCLK LFRAME#/SCS# LRESET#/SPI_RST#/SRESET# SERIRQ CLKRUN#/GPIO4/SINT# LPCPD#

4

PP

5

TEST

NPCT650ABCYX _QFN32_ 5X5

VDD1 VDD2 VDD3

GND1 GND2 GND3 GND4

PGND

Reserved

VSB

NC1 NC2 NC3 NC4 NC5 NC6 NC7

S IC NPCT650ABCYX QFN 32P TPM2.0 FW 1.3.2 .8

1 2

@EMC@

1 2

CW7 22P_0402_50 V8J

CW3

@EMC@

1

2

1

8 14 22

2 7 10 11 25 26 31

9 16 23 32 33 12

CW4

0.1U_0201_10V6K

CW5

0.1U_0201_10V6K

1

2

TPM@

near pin10, 19, 24

LPC_AD0_R <30> LPC_AD1_R <30> LPC_AD2_R <30> LPC_AD3_R <30>

+3VALW_TPM

+3VS_TPM

CW6

0.1U_0201_10V6K

1

2

TPM@

+TP_VCC

20mil 0.1A

1 2

@

R463 0 _0402_5%

C663

0.1U_0201_10 V6K

1 2

@

TP_SENOFF# < 30>

GND GND

CONN@

JTP1

1

TP_CLK

2

TP_DATA

3

4

I2C_3_SDA_R

5

I2C_3_SCL_R

6

TP_I2C_INT#

7

TP_SENOFF#

8

9 10

KB BackLight

+5VS

U1

5

IN

KBL_EN<30>

4

EN

SY6288C20AAC_SOT23 -5

SA000079400

Vih=1.5

Finger Print

Power Souce Check EGIS ETU801 +FP_VCC=5V ELAN SA464K-2200 +FP_VCC=3.3V

1 2

RK16 0_0603_ 5%FP@

+3VALW +5VALW

1 2

RK17 0_0603_ 5%@

CK11

1U_0201_6.3V6M

4.7K_0402_5%

FP@

TP_CLK TP_DATA

OUT

GND

OC

2

1

I2C_3_SCL_R

I2C_3_SDA_R

ON/OFFBTN#

KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8

KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17

KSI0

KSI1

KSI2

KSI3

KSI4

KSI5

KSI6

KSI7

I2C_3_SDA_R I2C_3_SCL_R TP_I2C_INT#_APU

TP_I2C_INT#

KSI[0..7]

KSO[0..17]

30

GND2

29

GND1

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

ACES_85201-280 5

+3VS

R2507

1

2

3

+TP_VCC

12

+3VALW

1U_0201_6.3V6M

C2562

12

R2509

4.7K_0402_5%

+5VS_BL

2

1

2

C3

0.1U_0201_10 V6K

U13

SA000079400

SY6288C20AAC_SOT23 -5

5

OUT

IN

GND

4

OC

EN

Vih=1.5

TP_3V_EN <30>

TP_CLK <30> TP_DATA <30>

JBL1

1

2

3

4

5

GND

6

GND

ACES_51524-004 0N-001

CONN@

SP010022M00

JBL2

1

2

3

4

5

GND

6

GND

ACES_51524-004 0N-001

CONN@

SP010022M00

+TP_VCC

1

2

3

4.7U_0402_6.3V6M

C2563

1

2

KB Conn.

SP01000GO00

HUB_USB20_N 3<33>

HUB_USB20_P3<33>

UK6

5

OUT

IN

GND

4

OC

EN

SY6288C20AAC_SOT23 -5

FP@

SA000079400

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+FP_VCC

1

2

3

2

FP_PWR_EN <30>

FP@

CK12

4.7U_0402_6.3 V6M

2017/12/25 2019/12/25

HUB_USB20_P3

+FP_VCC

Compal Secret Data

Deciphered Date

RP20

1 8 2 7 3 6 4 5

2.2K_0804_8P4 R_5%

R633 10K_0402_5%

+TP_VCC

G

2

2N7002KDW _SOT363-6

S

61

D

1 2

R2622 0_0402_5%@

1 2

R2623 0_0402_5%@

JKB2

CONN@

1 2

RK18 0_040 2_5%RS@

1 2

RK19 0_040 2_5%RS@

DK2

@EMC@

6

I/O4

5

VDD

4

I/O3

AZC099-04S.R7G_SOT 23-6

SC300001G00

+TP_VCC

12

1 2

D22 RB751V-40_SOD32 3-2

G

5

2N7002KDW _SOT363-6

S

34

D

Q2509A

SB00000EO00

KSI[0..7] <30>

KSO[0..17] <30>

CAPS_LED#<30>

NUM_LED#<30 >

3

I/O2

2

GND

1

I/O1

+3VS

+TP_VCC

Vgs=1.0-2.5V

Q2509B

SB00000EO00

TP_I2C_INT# <30>

TP_I2C_INT#_APU <9>

I2C_3_SCL < 9>

To EC

To APU

I2C_3_SDA <9>

JKB1

ON/OFFBTN#

KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8

KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17

KSI0

KSI1

KSI2

KSI3

KSI4

KSI5

KSI6

KSI7

+FP_VCC

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

ACES_50596-032 01-P01

CONN@

SP010017J00

1 2

R3982 1K_0402_5%

1 2

R3983 0_0402_5%@

1 2

+5VS

HUB_USB20_N 3_LHUB_USB20_N3

HUB_USB20_P3 _L

HUB_USB20_N 3_L

HUB_USB20_P3 _L

R3984 0_0402_5%@

1 2

R3985 1K_0402_5%

HUB_USB20_P3 _L HUB_USB20_N 3_L

Compal Electronics, Inc.

Title

Size Document Number R ev

Custom

Date : Sheet of

Compal Electronics, Inc.

KB/TP/TPM/LID

DH5AV_JV_0V_LA-G021P

33

GND

34

GND

JFP1

8

7

10

7

G2

6

9

6

G1

5

4

3

2

1

ACES_51522-008 01-001

CONN@

SP01001AE00

31 4 8Monday, December 25, 2017

1.B

5

4

3

2

1

FAN Conn

80mil

+5VS

D D

@EMC@

1000P_0402_ 50V7K

C C

1

CF2

2

RF1 0_0603_5%RS@

RF7 0_0603_5%RS@

2

CF1

4.7U_0402_6.3 V6M

1

1 2

+VCC_FAN1

+VCC_FAN2

FAN_SPEED1<30>

FAN_SPEED2<30>

+3VS

12

RF2 10K_0402_5%

1

CF3 1000P_0402_ 50V7K

@EMC@

2

+3VS

12

RF5 10K_0402_5%

1

CF10 1000P_0402_ 50V7K

@EMC@

2

40mil

+VCC_FAN1 FAN_SPEED1

FAN_PWM1<30>

FAN_PWM2<30>

FAN_PWM1

40mil

+VCC_FAN2 FAN_SPEED2 FAN_PWM2

JFAN1

1

2

3

4

5

G1

6

G2

ACES_50278-004 01-001

CONN@

SP02000RR00

JFAN2

1

2

3

4

5

G1

6

G2

ACES_50278-004 01-001

CONN@

SP02000RR00

Screw Hole

H34

H4

H_3P0

1

@

CPU Hole

H14

H13

H15

H_3P8

1

@

H23

H35

H_2P7X2P0N

@

1

Reset Circuit

BI_GATE PH to +RTCVCC at PWR side

H36

H37

H_3P0

1

@

GPU Hole NGFF Stand-Off

H_3P8

H_2P0N

@

H10

H_6P0

1

H26

@

H25

BI_GATE<37>

1

@

H27

H38

H_3P8

1

@

1

BI_GATE

2N7002KDW _SOT363-6

H39

H_6P4

1

@

H29

H_3P2

1

@

5

SB00000EO00

Vgs=1.0-2.5V

H_3P2

G

H30

1

@

Q2519B

H_2P5

34

S

H33

@

D

1

H_4P0

H5

@

H6

H_4P0

1

@

+3VLP

R349 100K_0402_5 %

1 2

1

C347

0.1U_0201_10 V6K

2

H_4P0

1

BI_GATE#

PCB Fiducial Mark

FD1

@

1

FIDUCIAL_C40M80

FD3

H31

H32

H_4P0

1

@

2

G

1

FIDUCIAL_C40M80

R3925 0_0402_5%@

R3924 0_0402_5%RS@

61

D

Q2519A 2N7002KDW _SOT363-6

SB00000EO00

S

@

1 2

FD2

@

1

FIDUCIAL_C40M80

FD4

@

1

FIDUCIAL_C40M80

MAINPWON <30,37,39>

EC_RST# <30>

B B

Reset But t on

SWG2

1 2

3 4

NTC013-AA1J-A160T SPST_4P

SN10000CV00

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/12/25 2019/12/25

BI_GATEBI_GATE

Compal Secret Data

Deciphered Date

2

BI SW

@

SWG1

ATE-2-V-TR_4P

H : 3.8mm

1

2

3

4

Release : Bat t er y Off Push : Bat t ery ON

BI_S <37>

Compal Electronics, Inc.

Title

Size Document Number R ev

Custom

Date : Sheet of

Compal Electronics, Inc.

FAN/BATT RESET_DEGUB SW

DH5AV_JV_0V_LA-G021P

1

32 4 8Monday, December 25, 2017

1.B

5

4

3

2

1

1 2

12

39K_0402_1%

+USB3_VCCA

1

+

C487 .1U_0402_16V7K

2

EMC@

2

USB3.0 Conn.

JUSB1

1

VBUS

2

D-

3

D+

4

GND

5

SSRX-

6

SSRX+

GND

7

GND

8

SSTX-

GND

9

SSTX+

GND

ACON_TARB5-9V1391

CONN@

DC23300NH00

+USB3_VCCA

10 11 12 13

0831 Reserve ILIM_L R as vendor recomm end

RS13

@

+USB3_VCCA

@

12

For ESD request

D15

EMC@

1

2

4

5

3

8

L05ESDL5V0NA-4 SLP2510P8

SC300003Z00

D2010

EMC@

6

I/O4

5

VDD

4

I/O3

AZC099-04S.R7G_SOT23-6

SC300001G00

0904 vendor recommend

22U_0603_6.3V6M

0.1U_0201_10V6K

1

CS9

CHG@

2

USB20_N0<10> USB20_P0<10>

CHG_ILMSEL<30>

CHG_EN<30>

CHG_CTL1<30>

CHG_CTL3<30>

USB20_N0 USB20_P0

CHG_ILMSEL

CHG_EN

CHG_CTL1 CHG_CTL2 CHG_CTL3

10

9

7

6

I/O2

GND

I/O1

CS7

USB3_ATX_L_DRX_P0

9

USB3_ATX_L_DRX_N0

8

USB3_ARX_L_DTX_P0

7

USB3_ARX_L_DTX_N0

6

USB20_P0_R

3

2

USB20_N0_R

1

0904 reserve VI N & VOUT 1206 for QFN current measure

US10

CHG@

1

VIN

2

DM_OUT

3

DP_OUT

13

FAULT#

4

ILIM_SEL

5

EN

6

CTL1

7

CTL2

8

CTL3

SLGC55544CVTR_TQFN16_3X3

SA000097E10

VOUT

DP_IN

DM_IN

ILIM_L

ILIM_HI

Thermal Pad

12

10 11

15 16

9

NC

14

GND

17

CS25

150U_B2_6.3VM_R35M

SGA00009M00

USB20_N0_R USB20_P0_R

USB3_ARX_L_DTX_N0 USB3_ARX_L_DTX_P0

USB3_ATX_L_DRX_N0 USB3_ATX_L_DRX_P0

+USB3VCCA_CHG+5VALW_CHG

RS10 0_1206_5%RS@

SW_USB20_P0 SW_USB20_N0

12

22.1K_0402_1% RS12

CHG@

ILM R vaule Ios(mA) =50250 /R(Koh m) ILIM_H i=2273 mA ILIM_L =1288m A

USB3.0 (Port 0)

1 2

USB3_ATX_DRX_N0<10>

USB3_ATX_DRX_P0<10>

USB3_ARX_DTX_N0<10>

USB3_ARX_DTX_P0<10>

D D

C482 0.22U_0402_16V 7K

1 2

C484 0.22U_0402_16V 7K

1 2

C2754 0.33U_0402_10V6K

1 2

C2755 0.33U_0402_10V6K

USB3_ATX_C_DRX_N0

USB3_ATX_C_DRX_P0

USB3_ARX_C_DTX_N0

USB3_ARX_C_DTX_P0

1 2

R3968 0_0402_5%RS@

1 2

R3967 0_0402_5%RS@

1 2

R3966 0_0402_5%RS@

1 2

R3965 0_0402_5%RS@

USB3_ATX_L_DRX_N0

USB3_ATX_L_DRX_P0

USB3_ARX_L_DTX_N0

USB3_ARX_L_DTX_P0

SW_USB20_P0 USB20_P0_R

SW_USB20_N0 USB20_N0_R

3 4

DLM0NSN900HY2D_4P L2508 EMC@

SM070005U00

12

USB3_ATX_L_DRX_P0

USB3_ATX_L_DRX_N0

USB3_ARX_L_DTX_P0

USB3_ARX_L_DTX_N0

Non-Charger Co-lay

+USB3_VCCA+5VALW

C483

NCHG@

1U_0201_6.3V6M

1 2

USB_EN<30>

USB20_N0 USB20_P0

C C

USB Host Charger Truth Table

CHG_EN

CTL1

CTL2 CTL3 ILIM_SEL

0

0 1 10 ILIM_ H

1

0

1

0 1 1 1

1

1 111

USB_EN

101

U25

NCHG@

5

IN

4

EN

SY6288C20AAC_SOT23-5

SA000079400

Vih=1.5

1 2

RS96 0_0402_5%NCHG@

1 2

RS97 0_0402_5%NCHG@

MODE

SDP1-OFF

SDP1

DCP Aut o

CDP

1

OUT

2

GND

3

R454 0_0402_5%@

OC

Current Limit Settin g

ILIM_H

80mils 2A

1 2

1

C612

0.1U_0201_10V6K

2

@

SW_USB20_N0 SW_USB20_P0

Note

Port power off

Data Lines Connected

Data Lines Disconnected

Data Lines Connected

USB_OC0# <10>

+5VALW

1 2

RS14 10K_0402_5%CHG@

1 2

RS15 10K_0402_5%@

For Test Debug Only

+5VALW

RS150 10K_0402_5%

CHG_EN CHG_CTL1

RS151 10K_0402_5%

0911 Rerserve P U, vendor suggest to E C control if future need supp ort S DP2

1 2

@

CHG_CTL2

CHG_ILMSEL

CHG_CTL3

12

USB_OC0#

0.1U_0201_10V6K

+5VALW

CS8

@

RS147 0_1206_5%RS@

RS11 0_0402_5%@

1

2

1 2

USB HUB

B B

+3VALW

R269 0_0402_5%

1 2

HUB@

+3V_HUB

A A

+3V_HUB

C294

10U_0603_6.3V6M

1

HUB@

2

1 2

HUB@

R266 100K_0402_5%

1 2

HUB@

R273 10K_0402_5%

1 2

HUB@

R271 100K_0402_5%

HUB_XIN

C295

33P_0402_50V8J

HUB@

1

2

PSELF

OVCUR1#

PGANG

1

2

5

0.1U_0201_10V6K

+3V_HUB

C293

HUB@

L:Bus-Powered H:Slef-Powered

Float:Non-Removable High:Removable

L:Individual Mode H:Gand Mode

Y11

124

12MHZ_18PF_7V12000001

HUB@

1 2

C288 0.1 U_0201_10V6K

HUB@

1 2

C289 0.1 U_0201_10V6K

HUB@

1 2

C291 0.1 U_0201_10V6K

HUB@

1 2

C290 0.1 U_0201_10V6K

C296

33P_0402_50V8J

HUB@

3

SJ10000C210

1

HUB_XOUT

2

USB_HUB_RESET#< 30>

C279 close to U73 pin5 C280 close to U73 pin9 C283 close t o U73 pin14 C284 close t o U73 pin21

R976 0_0402_5%

1 2

@

+3V_HUB

12

2

1

HUB@

R272 10K_0402_5%

HUB@

C292 1U_0201_6.3V6M

4

HUB@

R1053

0_0402_5%

+3V_HUB

1 2

USB20_P5<10> USB20_N5<10>

USB20_N1<10>

USB20_P1<10>

12

HUB_RESET#

HUB_XIN HUB_XOUT

PSELF PGANG

R4023 0_0402_5%NHUB@

1 2

R4024 0_0402_5%NHUB@

3 4

DLM0NSN900HY2D_4P L2517 EMC@

SM070005U00

+3V_HUB

U73

5

AVDD

9

AVDD

14

AVDD

21

DVDD

27

V5

28

V33

18

TEST/SCL

26

SDA

17

RESET#

10

X1

11

X2

22

PSELF

23

PGANG

29

GND

GL850G-OHY50_QFN28_5X5

HUB@

SA000066320, S IC GL850G-OHY50 QFN 28P USB2.0 HUB

OVCUR1#/SMC OVCUR2#/SMD

OVCUR3# OVCUR4#

RREF

DM0 DP0

DM1 DP1

DM2 DP2

DM3 DP3

DM4 DP4

USB20_P5_R USB20_N5_R

12

USB20_N5

1

USB20_P5

2

HUB_USB20_N1

3

HUB_USB20_P1

4

HUB_USB20_N2

6

HUB_USB20_P2

7

HUB_USB20_N3

12

HUB_USB20_P3

13

HUB_USB20_N4

15

HUB_USB20_P4

16

25

OVCUR1#

24 20 19

8

RREF

RREF can just the driving.

1 2

R4025 0_0402_5%NHUB@

1 2

R4026 0_0402_5%NHUB@

USB20_N1_R

USB20_P1_R

HUB_USB20_N2 <24> HUB_USB20_P2 <24>

HUB_USB20_N3 <31> HUB_USB20_P3 <31>

HUB_USB20_N4 <27> HUB_USB20_P4 <27>

12

HUB@

R267 680_0402_1 %

3

HUB_USB20_P1

HUB_USB20_N1

SUB/B Type-A

Touch Screen

Finger P rint

WLAN/BT

1 2

DLM0NSN900HY2D_4P L2516 EMC@

SM070005U00

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

HUB_USB20_P1_L

HUB_USB20_N1_L

34

HPOUT_L_1 HPOUT_R_1

SLEEVE RING2

HP_PLUG#

GNDA

USB20_N1_R USB20_P1_R

HUB_USB20_N1_L HUB_USB20_P1_L

BATT_AMB_LED# BATT_BLUE_LED# PWR_SUSP_LED# PWR_LED#

USB_EN

GNDA

Compal Secret Data

2017/12/25 2019/12/25

Compal Secret Data

Deciphered Date

2

BATT_AMB_LED#<30>

BATT_BLUE_LED#<30>

PWR_SUSP_LED#<30>

100mils 2.5A

HPOUT_L_1<29> HPOUT_R_1<29>

SLEEVE<29> RING2<29> HP_PLUG#<29>

PWR_LED#<30>

+5VALW

JIO2

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

GND

28

GND

ACES_51522-02601-001

CONN@

SP01001AO00

Compal Electronics, Inc.

Title

USB30/USB HUB/LED

Size

Document Number Re v

Custom

DH5AV_JV_0V_LA-G021P

Date : Sheet of

DH5AV_JV_0V_LA-G021P

1

33 48Monday, December 25, 2017

1.B

5

USB3.0 Type-C

1 2

USB3_ATX_DRX_P2<10>

USB3_ATX_DRX_N2<10>

USB3_ARX_DTX_P2<10>

USB3_ARX_DTX_N2<10>

CS1 0.22U_0402_16V7K

TYPEC@

1 2

CS2 0.22U_0402_16V7K

TYPEC@

1 2

CS109 0.33U_0402_10V6K

TYPEC@

1 2

CS110 0.33U_0402_10V6K

TYPEC@

USB3_ATX_C_DRX_P2 USB3_ATX_R_DRX_P2

USB3_ATX_C_DRX_N2

USB3_ARX_C_DTX_P2

USB3_ARX_C_DTX_N2

D D

1 2

RS1 0_0402_5%RS@

1 2

RS2 0_0402_5%RS@

1 2

RS3 0_0402_5%RS@

1 2

RS4 0_0402_5%RS@

USB3.0 Type-C

1 2

USB3_ATX_DRX_P3<10>

USB3_ATX_DRX_N3<10>

USB3_ARX_DTX_P3<10>

USB3_ARX_DTX_N3<10>

CS3 0.22U_0402_16V7K

TYPEC@

1 2

CS4 0.22U_0402_16V7K

TYPEC@

1 2

CS111 0.33U_0402_10V6K

TYPEC@

1 2

CS112 0.33U_0402_10V6K

TYPEC@

USB3_ATX_C_DRX_P3

USB3_ATX_C_DRX_N3

USB3_ARX_C_DTX_P3

USB3_ARX_C_DTX_N3

C C

+5VALW +5VALW_VCONN

+3VALW

RS156 100K_0402_5%TYPEC@

1 2

RS155 1K_0402_5%TYPEC@

12

CS124

2.2U_0402_6.3V6M

@

1

2

US11

6

IN

5

SET

4

EN(/EN)

G527ATP1U_TSOT23-6

TYPEC@

SA00006Y700

FLAG

20 mils

1

OUT

2

GND

3

0.2A OCP for VCONN!

RS127 0_0603_5%

1 2

RS@

Close to Pin9 Close to Pin8

1

TYPEC@

CS116

2.2U_0402_6.3V6M

2

+1.8V_LDO+3VALW +3VALW_CC

1

TYPEC@

CS122 1U_0201_6.3V6M

2

B B

+3VALW_CC

12

TYPEC@

10K_0402_5%

10K_0402_5% @

CUR_MODE0 CUR_MODE1 MODE

A A

RS136

RS135

10K_0402_5%

12

RS134

RS133

10K_0402_5% @

Initial Current mode selection

L

H

L

H

Default Current

Medium current

High current

TYPEC_SMB_DA2

CUR_MODE0 CUR_MODE1

12

TYPEC_SMB_CK2

VBUS_MON CUR_MODE0 CUR_MODE1

EC_SMB_CK2<8,16,30>

EC_SMB_DA2<8,16,30>

5

RS5 0_0402_5%RS@

RS6 0_0402_5%RS@

RS8 0_0402_5%RS@

RS7 0_0402_5%RS@

TYPEC@

1

CS97

0.1U_0201_10V6K

2

EC_SMB_DA2

14 15

1 2

EC_TYPEC_EN#<30>

US1

TYPEC@

1

GPIO2(INT#)

2

CUR_DR

3

SI0(SDA)

4

SI1(SCL)

7

VBUS_DC CUR_MODE0 CUR_MODE1

TYPC_CONN_DET

6

GND

EJ179F_QFN16_4X4

SA0000BAT00

S IC EJ179F QFN 16P USB SW

+3VS

S

G

2

S

D

RS148 0_0 402_5%TYPEC@

RS149 0_0 402_5%TYPEC@

USB3_ATX_R_DRX_N2

USB3_ARX_R_DTX_P2

USB3_ARX_R_DTX_N2

USB3_ATX_R_DRX_P3

USB3_ATX_R_DRX_N3

USB3_ARX_R_DTX_P3

USB3_ARX_R_DTX_N3

5V@3A

@

RS112

100K_0402_5%

VCONN

VDD33

VDD18

CC1 CC2

CC_EN

CC_SEL

EPAD

Vgs=1.0-2.5V

G

5

@

QS4B 2N7002KDW_SOT363-6

34

D

@

QS4A

SB00000EO00

2N7002KDW_SOT363-6

61

12

4

+5VALW

12

10

9

8

11 12

16 5 13

17

SB00000EO00

4

CS108 150U_B2_6.3VM_R35M

CS104

0.1U_0201_10V6K

2

G

+5VALW_VCONN

+3VALW_CC

TYPEC_CC1 TYPEC_CC2

TYPEC_SMB_CK2

TYPEC_SMB_DA2

USB20_P2<10>

USB20_N2<10>

+5VALW +USB3_VCCC

TYPEC@

12

+

TYPEC@

12

RSET

VBUS_P_CTRL

13

@

D

QS6 2N7002K_SOT23-3

SB00000PU00

S

+1.8V_LDO

VBUS_P_CTRL

12

TYPEC@

RS154 10K_0402_5%

TYPEC_SMB_CK2EC_SMB_CK2

TYPEC_SMB_DA2

USB20_P2

USB20_N2

120mils 3A

US12

TYPEC@

6

OUT

IN

5

GND

SET

4

FLAG3EN

SY6861B1ABC_TSOT23-6

SA0000BDN00

VEN=1.0V

VBUS_MON

0.01U_0402_16V7K

1

2

RS120 0_0 402_5%@

TYPEC@

RS131

4.7K_0402_5%

TYPEC@

RS130

4.7K_0402_5%

TYPEC@

3 4

CS107

0.1U_0201_10V6K

1

CS121

2

+3VALW_CC

12

DLM0NSN900HY2D_4P LS7 TYPECEMC@

SM070005U00

12

1

@

2

+USB3_VCCC

12

TYPEC@

RS137 39K_0402_1%

12

TYPEC@

RS138 3K_0402_1%

3

12

USB20_P2_R

USB20_N2_R

USB_OC2# <10>

For ESD request

TYPEC_CC1 TYPEC_CC1

TBTA_SBU1 TBTA_SBU1

USB3_ATX_R_DRX_P2

USB20_P2_R USB20_P2_R

USB20_N2_R USB20_N2_R

USB3_ARX_R_DTX_N3

USB3_ARX_R_DTX_P3

USB3_ARX_R_DTX_P2

USB3_ARX_R_DTX_N2

USB3_ATX_R_DRX_N3

USB3_ATX_R_DRX_P3 USB3_ATX_R_DRX_P3

RSET

TYPEC@

RS146

6.2K_0402_5%

CS106

22U_0805_25V6M

CS123

10U_0603_25V6M

CS105

22U_0805_25V6M

CS13

0.1U_0402_25V6

1

@

2

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

12

1

TYPEC@

2

Issued Date

1

@

2

@

DS5 MESC5V02BD03_SOT23-3

TYPECEMC@

2017/12/25 2019/12/25

DS1

TYPECEMC@

1

2

4

5

3

8

L05ESDL5V0NA-4 SLP2510P8

SC300003Z00

1

2

4

5

3

8

L05ESDL5V0NA-4 SLP2510P8

SC300003Z00

1

2

4

5

3

8

L05ESDL5V0NA-4 SLP2510P8

SC300003Z00

1

2

4

5

3

8

L05ESDL5V0NA-4 SLP2510P8

SC300003Z00

12

TYPEC@

RS145

8.2K_0402_5%

TYPEC@

QS1B

2N7002KDW_SOT363-6

SB00000EO00

GPP_B1 RSET(kΩ ) MO DE

GPP_B4

L L

L

H

*H

10

9

7

6

DS2

TYPECEMC@

10

9

7

6

DS3

TYPECEMC@

10

9

7

6

DS4

TYPECEMC@

10

9

7

6

12

TYPEC@

4.3K_0402_5%

TYPEC@

2N7002KDW_SOT363-6

SB00000EO00

34

D

G

S

Vgs=1.0-2.5V

G518 MOS Current Limit

6.2

3.53

H

2.54

L

1.94 3.5A

H

9

8

7

6

9

8

7

6

9

8

7

6

9

8

7

6

RS144

QS1A

5

CC1_VCONN/CC2_V CONN 20mils

USB3_ATX_R_DRX_P2 USB3_ATX_R_DRX_N2

CS11 0.1U_0402_25V6

2

3

1

TYPEC@

TYPEC_CC1

USB20_P2_R USB20_N2_R

TBTA_SBU1

CS14 0.1U_0402_25V6

TYPEC@

USB3_ARX_R_DTX_N3 USB3_ARX_R_DTX_P3

Compal Secret Data

Deciphered Date

TYPEC_CC2TYPEC_CC2

TBTA_SBU2TBTA_SBU2

USB3_ATX_R_DRX_P2

USB3_ATX_R_DRX_N2USB3_ATX_R_DRX_N2

USB3_ARX_R_DTX_N3

USB3_ARX_R_DTX_P3

USB3_ARX_R_DTX_P2

USB3_ARX_R_DTX_N2

USB3_ATX_R_DRX_N3

12

61

D

2

G

S

limit point

0.9A

1.5A

2A

3A

+USB3_VCCC +USB3_VCCC

12

2

1.09A

1.92A

2.67A

TYPEC_3A <30>

TYPEC_1P5A <30>

JTYPEC1

A1

GND

A2

SSTXP1

A3

SSTXN1

A4

VBUS

A5

CC1

A6

DP1

A7

DN1

A8

SBU1

A9

VBUS

A10

SSRXN2

A11

SSRXP2

A12

GND

1

GND

2

GND

3

GND

4

GND

LOTES_AUSB0181-P001A

DC021702230

CONN@

1

From EC Current Limit

B12

GND

SSRXP1 SSRXN1

VBUS

SBU2

DN2 DP2

CC2

VBUS

SSTXN2

SSTXP2

GND

GND GND GND GND

Title

Size

Document Number Re v

Custom

Date : Sheet of

USB3_ARX_R_DTX_P2

B11

USB3_ARX_R_DTX_N2

B10

B9

B8

B7 B6

B5

B4

B3 B2

B1

5 6 7 8

1 2

CS12 0.1 U_0402_25V6

TYPEC@

TBTA_SBU2

USB20_N2_R USB20_P2_R

TYPEC_CC2

1 2

CS15 0.1 U_0402_25V6

TYPEC@

USB3_ATX_R_DRX_N3 USB3_ATX_R_DRX_P3

Compal Electronics, Inc.

TYPE-C CONN

DH5AV_JV_0V_LA-G021P

34 48Monday, December 25, 2017

1

1.B

A

B

C

D

E

VIN 5V and 3.3V (VBIAS=5V),IMAX(per channel) =6A,Rds=18mohm

+3VALW

1 2

SUSP#<30,38,40>

1 1

RS@

R1667 0_0402_ 5%

1 2

RS@

R1668 0_0402_ 5%

3VS_ON

5VS_ON

+5VALW

1 2

C12 1U_0201 _6.3V6M

1 2

C11 1U_0201 _6.3V6M

@

U2

1 2

3

4

5

6 7

VOUT1

VIN1

VOUT1

VIN1

ON1

VBIAS

ON2

VIN2

VOUT2

VIN2

VOUT2

EM5209V F_DFN14_3X2

SA00007PM00

CT1

GND

CT2

GPAD

+3VS_LS

14 13

12

11

10

9 8

15

1 2

C10

560P_04 02_50V7K

1 2

C9 330P_04 02_50V7K

+5VS_LS

J7

JUMP_43 X118

J8

JUMP_43 X118

VIN 1.8V and 1.5V (VBIAS=5V),IMA X(per channel)=6A,Rds=18m ohm

U3

R1669 0_0402_ 5%

1 2

SUSP#

RS@

2 2

4.7U_040 2_6.3V6M

3 3

+5VALW

0.9VS_PW R_EN#<30>

4 4

+1.8VALW

1.8VS_ON

+5VALW

1

C940

2

1 2

R1674

4.7K_040 2_5%

2

SB00000ZN00

S TR AO4354 1N SOIC-8

U4 AO4354 1 N SOIC8

8 7 6 5

0.9VS_GA TE

13

D

G

Q84

S

2N7002K _SOT23-3

SB00000PU00

Vgs=1.0-2.0V

1 2

C24 1U_0201 _6.3V6M

1 2

@

3

4

5

6 7

1 2 3

4

1

C16

0.1U_020 1_10V6K

2

VOUT1

VIN1

VOUT1

VIN1

ON1

VBIAS

ON2

VIN2 VIN2

EM5209V F_DFN14_3X2

SA00007PM00

CT1

GND

CT2

VOUT2 VOUT2

GPAD

+0.9VS+0.9VALW

C939

4.7U_0402_6.3V6M

C46

1U_0201_6.3V6M

1

2

@

+1.8VS_L S

14 13

1 2

12

C21

11

330P_04 02_50V7K

10

9 8

15

160mils(4.0A)

J9

JUMP_43 X79

VGA_ON

JP@

+3VS

1

C13

0.1U_020 1_10V6K

2

+5VS

1

C14

0.1U_020 1_10V6K

2

+1.8VS

1

C26

0.1U_020 1_10V6K

2

0.22U_04 02_16V7K

1 2

RV1648 0_0402_5%RS@

1 2

RV1629 33K_0402_5 %DIS@

0.22U_04 02_16V7K

CV2724

DIS@

CV625

RV807 0_0402_ 5%

1 2

@

1 2

RV833 33K_040 2_5%

DIS@

CV2701

DIS@

RS@

CV626

0.22U_04 02_16V7K

VGA_ON

1

Vih 2.1V

2

Delay 7ms

1

@

2

PE_GPIO1<10>

+3VSDGP U

RV913

100K_04 02_5%

1 2

0.22U_04 02_16V7K

+3VALW TO +3VSDGPU

+1.8VALW TO +1.8VSDGPU

2

@

1

+3VALW

+1.8VALW

1

2

1 2

@

CV260 1U_0201 _6.3V6M

1 2

@

CV2699 1U_020 1_6.3V6M

Vih 1.2V Delay 3ms

IMAX(per channel )=6A,Rds=18mohm

UV8

+5VALW

1 2

3

4

5

6 7

VOUT1

VIN1

VOUT1

VIN1

ON1

VBIAS

ON2

VIN2

VOUT2

VIN2

VOUT2

EM5209V F_DFN14_3X2

DIS@

SA00007PM00

CT1

GND

CT2

GPAD

14 13

12

11

10

9 8

15

0_0402_ 5%

1

2

1

2

+3VSDGP U_LS

1 2

DIS@

1 2

DIS@

+1.8VSDG PU_LS

RV406

12

@

+3VALW

UV5 MC74VHC 1G08DFT2G_SC 70-5

5

DIS@

P

IN1

4

O

IN2

G

3

+3VALW

UV6 MC74VHC 1G08DFT2G_SC 70-5

5

DIS@

P

IN1

4

O

IN2

G

3

20mil(10mA)

J2504

112

JUMP_43 X39

CV6211 000P_0402_50 V7K

CV6221 000P_0402_50 V7K

J2503

112

JUMP_43 X39

40mil(1.013A)

SA00000OH00

VGA_ON

1

DIS@

CV2698

0.1U_020 1_10V6K

2

SA00000OH00

VGA_ON_ B

2

@

CV2722 1U_0201 _6.3V6M

1

JP@

2

JP@

2

+3VSDGP U

2

1

+1.8VSDG PU

2

1

VGA_ON <45>

VGA_ON_ B <45>

CV2725

DIS@

0.1U_020 1_10V6K

CV31

DIS@

0.1U_020 1_10V6K

Security Classification

2017/12/ 25 2019/12/ 25

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

2017/12/ 25 2019/12/ 25

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Re v

Custom

Date : Sheet o f

D

Date : Sheet o f

Compal Electronics, Inc.

DC INTERFACE

DH5AV_JV_0V_LA-G021P

35 48Monday, December 2 5, 2017

E

1.B

A

B

C

D

1 1

@

ACES_50299-00601-001

1

2

3

4

4 G7 G8

PJP101

5

6

7 8

2 2

3 3

+19V_ADPIN

4.7_1206_5%

1 2

EMI@

0.1U_0603_25V7K

1 2

+19V_ADPIN

PR102

12

PC103

PC101

EMI@

100P_0402_50V8J

PL101

EMI@

NA_2P

1 2

PL102

EMI@

NA_2P

1 2

+19V_VIN

PC102

EMI@

1000P_0402_50V7K

PR103

12

4.7_1206_5%

1 2

EMI@

0.1U_0603_25V7K

1 2

PC104

PR101

@

0_0603_5%

+3VLP

4 4

A

1 2

+CHGRTC

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2017/12/25 2019/12/25

Compal Secret Data

Deciphered Date

C

Compal Electronics, Inc.

Title

Size Document Number Re v

Custom

Date: Sheet of

Compal Electronics, Inc.

DCIN

DH5AV_JV_0V_LA-G021P

D

36 48Monday, December 25, 2017

1.B

A

PR201 100_0402_1%

1 2

PR202 100_0402_1%

1 2

PR203

200K_0402_1%

@

PJP201

1

GND

2 3 4 5 6 7 8

2 3 4 5 6 7 8 9 10

EC_SMB_DA1-1 EC_SMB_CK1-1 BATT_TS BATT_B/I

1 1

CVILU_CI9908M2HR0-NH

+17.4V_BATT+

12

PC201

EMI@

2 2

1000P_0402_50V7K

1 2

PR204 1K_0402_1%

BI_GATE

PL201

EMI@

NA_2P

1 2

PL202

EMI@

NA_2P

1 2

PC203

EMI@

1000P_0402_50V7K

+3VLP

12

BATT_TEMP

+RTCVCC

PR208 100K_0402_5%

+17.4V_BATT

12

2

G

B

EC_SMB_DA1

EC_SMB_CK1

13

D

PQ201

LBSS139LT1G_SOT23-3

S

12

PR212

0_0402_5%

BI_S

<45,47>

MAINPWON

For KB9022 OTP

C

PR207

@

100K_0402_1%

MAINPWON

D

+3VLP

12

PC202

@

12

0.1U_0603_25V7K

PU201

@

1

VCC

TMSNS1

2

GND

RHYST1

3

OT1

TMSNS2

4

RHYST2

OT2

G718TM1U_SOT23-8

10K_0402_1%

RecoveryActive

12

PR205

@

8

7

6

5

@

47K_0402_1%

12

PR209

For KB9012 sense 20mΩ

PR206

@

10K_0402_1%

PH201

@

100K_0402_1%_NCP15WF104F0 3RC

RecoveryActive

92C, 1V 56C, 2.VVCIN0 _PH(V )

PH202 (ohm) 7.309 2K 26.1 1K

SR 45W

BR 65W

58.5W, 0.61V

84.5W, 0.61V

58.5W, 0.61V

84.5W, 0.61V

PH202 under CPU botten side : CPU thermal protection at 96 degree C ( shutdown ) Recovery at 56 degree C

2013/10/02

3 3

Add for ENE9022 Battery Voltage drop detection. Connect to ENE9022 pin64 AD1.

Reserve for 2-cell design

9022_PH1

+EC_VCCA

12

PR210

16.9K_0402_1%

PR211

65W@

4.53K_0402_1%

12

135W@

20K_0402_1%

PR211

ADP_I

45W@

10_0402_1%

PR211

+19VB_5V

12

PR213 750K_0402_1%

12

PC204

0.1U_0402_25V6

4 4

1 2

PR216 150K_0402_1%

A

0_0402_5%

1 2

PR214

VCIN1_BATT_DROP

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPET ENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPET ENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPET ENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2017/12/25 2019/12/25

100K_0402_1%_B25/50 4250K

B value:4250K± 1%

Compal Secret Data

Deciphered Date

C

PH202

12

ECAGND

@

T1

@

T2

PR217

@

0_0402_5%

12

PR215 10K_0402_1%

Compal Electronics, Inc.

Title

Size Document Number Re v

Custom

Date : Sheet o f

Compal Electronics, Inc.

DH5AV_JV_0V_LA-G021P

9022_VCIN

BATTERY CONN / OTP

37 48Monday, December 25, 2017

D

37 48Monday, December 25, 2017

1.B

5

4

3

2

1

Module model information

ISL95520_H ybrid _Boost _V2.m dd

Protection for reverse input

Vgs = 20V Vds = 60V Id = 250mA

D D

Need check the SOA for inru sh

+19V_VIN

Range:2V ~3.5V 20*49.9/ (392+49.9) =2.5 5V

0x3CH <BIT9> PSYS current gain Rs1 = 10mΩ and Rs2 = 5mΩ o r Rs1 = 10mΩ and R s2 = 10mΩ BIT0 = 1.14uA/W BIT1 = 0.285uA/W ======== ========== ========== =========== ======= ==== ===== == Rs1 = 20mΩ and Rs2 = 10mΩ o r Rs1 = 20mΩ and R s2 = 20mΩ BIT0 = 2.28uA/W BIT1 = 0.57uA/W

C C

Ipsys = KPSYS x ( VAD P x IAD P + VBA T x IBAT ) R_Psys = 1.2V / Ipsys KPSYS = 1.14uA/W adapter wattage = 45W Battery wattage = 40Wh Ipsys = 1.14 x (45+40) = 96.9uA R_Psys = 1.2V / 96.9uA = 12.3K-ohm. ======== ========== ========== ==== ===== adapter wattage = 65W Battery wattage = 40Wh Ipsys = 1.14 x (65+40) = 119.7uA R_Psys = 1.2V / 96.9uA = 10K-ohm.

B B

  

**Design Notes** For 45W/65W /90W s ystem, 2S/3S/4S battery Maximum Charging current 3.5A Maximum Battery discharge power 55W #Register Setting

1. 0X3D H bit10 set 0 (default 1) to enable turbo boost function

2. Disa ble turbo when AC only #Circuit Design

1. A CLIM and CCLIM are d evider v oltage c ontrol.

2. Use 7X7 ch oke and 3X3 H/L side MOSFET Charge current 3A Power loss : 1.79W (H/S=0.22 7W,L/S=1.2738W,Choke= 0.297W) Power density : 0.61 (23X16) #Protect function

1. ACOV P : VC C voltage > 24V

2. S MBus timeou t : 0X3DH bi t15 set 0 ( default 0) to enable 175s(default).

3. A COC : OX3CH bit4 set 1 releas e adapte r limit function (default:Enable ).

4. C HGOCP : based on charge current setting

5. B ATOVP : 4.6V/Cell

6. BATL OWV : No.

7. TSHU T : 150C

Battery current limimed by CCLIm ~ 3.89A. Adapter current limimed by ACLIm ~ 4.33A. (PR779 and PQ741 are for change ACLIm when AC in)

(Rs1 = 10mΩ and Rs2 = 5mΩ or Rs1 = 20mΩ a nd Rs2 = 10mΩ). CC_LIM = VccLIM / 64 x Rs2 ======== ========== ========== =========== ========= ==== ===== ==== (Rs1 = 10mΩ and Rs2 = 10mΩ or Rs 1 = 20m Ω and Rs2 = 20mΩ). CC_LIM = VccLIM / 32 x Rs2 ======== ========== ========== =========== ========= ==== ===== ==== AC_LIM = Vac_LIM / 32 x Rs1

ACIN

1 2

PR301

1M_0402_1%

VDD_CHG

12

PR311

100K_0402_1%

12

PR313

158K_0402_1%

EMB04N03H_EDFN5X6-8-5

5

12

PR306 499K_0402_1%

PR310

66.5K_0402_1%

EC_SMB_DA1

EC_SMB_CK1

APU_PROCHOT#

ADP_I

ACIN

1 2

PR302

3M_0402_5%

PQ310

12

PC316

0.1U_0402_25V6

Close to EC.

@

L2N7002WT1G_SC70-3

65W@

80.6K_0402_1%

45W@

57.6K_0402_1%

13

D

2

G

S

1 2 3

4

PC322

@

1 2

1000P_0402_25V

12

PR307 4.02K_0402_1%

12

PC301

2200P_0402_50V7K

support Turbo boost : 2200P no support Turbo boost : 0.1u

PR314 0_0402_5%@

PR316 0_0402_5%@

PR317 0_0402_5%@

PR318 1K_0402_1%

PR321 1K_0402_1%

12

PC317

0.1U_0402_25V6

VDD=5 V

@

PR331

76.8K_0402_1%

1 2

PQ316

13

D

2

G

S

PR336

Hybrid boost power mode

PR336

Cell = 4s

ICClimit : 7.73A Delta I : 1.44A 1C charge current :6.48A

PQ301 L2N7002WT1G_SC70-3

+19V_P1

PR308 4.02K_0402_1%

1 2

Close to EC.

VDD_CHG

12

PR329

PR328

200K_0402_1%

OCCP setting

12

PR337

PR336

232K_0402_1%

135W@

PQ311

45W@

135W@

AON7506_DFN33-8-5

AON7380_DFN3X3-8-5

PQ311

65W@

AON7506_DFN33-8-5

1 2 3

12

200K_0402_1%

12

100K_0402_1%

+19V_P2 +19VB_CHG

5

4

PR304

@

CMSRC_CHG

ASGATE_CHG

PU301

ACIN_CHG BST_CHG_R

1

ACIN

2

ACOK

3

SDA

4

SCL

5

PROCHOT#

AMON_ISL95520

6

AMON

7

BMON

8

NC

12

AGND

PR322

33

0_0402_5%

@

CCLIM_CHG

ACLIM_CHG

PROG_CHG

COMP_CHG

12

PR335

12

4 cell@

150K_0402_1%

@

For 4S per cell 4.35V battery

ACIN_CHG

12

PR339

2M_0402_1%

PR341

@

0_0402_5%

1 2

A A

BATT_4S

SUSP#

100K_0402_1%

1 2

PR340

2

G

5

2

13

D

PQ308 L2N7002WT1G_SC70-3

S

13

PQ307 LTC015EUBFS8TL_UMT3F

4

PQ311

PR303

0.005_1206_1%

134

2

CSIP_CHG_R

12

0_0402_5%

PC306

0.1U_0402_25V6

1 2

CSIN_CHG

CSIP_CHG

30

31

32

CSIP

CSIN

ASGATE

ISL88739AHRZ-T_QFN32_4X4

CCLIM11COMP

PROG

9

10

FSET_CHG

12

PR332

100_0402_1%

12

PC321

PC320

560P_0402_50V7K

0.015U_0402_25V7K

APU_PROCHOT#

max Power loss 0.22W for 90 W;0.12W fo r 65W system;0.05W for 45W CSR rating: 1W VCSIP-VCSIN spec < 81mV

PL303

EMI@

FBMA-L11-201209-800LMA50T

1 2

PL302

EMI@

FBMA-L11-201209-800LMA50T

1 2

Isat: 10A DCR: 14mohm

PJ301

@

CSIN_CHG_R

12

PR305

2_0402_5%

12

PC307 0.22U_0603_25V7K

OPCN_CHG

28

29

OPCN

CMSRC

FSET12BATGONE13CSON14CSOP

12

PR333

0_0402_5%

112

JUMP_43X118

Co-lay jump and ISN choke.

OPCP_CHG

VBAT_CHG

BGATE_CHG

25

26

27

VBAT

QPCP

BGATE

24

BOOT

23

UGATE

22

PHASE

21

LGATE

20

VDDP

19

VDD

18

DCIN

17

NTC

ACLIM

15

16

PR325 10K_0402_1%

CSOP_CHG

PR333=0 ohm, Fs=500KHZ ~ +/- 15%

CSON_CHG

BATGONE( BATT_TE MP) logic high: above 2.4V logic low: under 0.8V

BST_CHG

UG_CHG

LX_CHG

LG_CHG

VDDP_CHG

VDD_CHG

PR323

12

100K_0402_1%

PC318

BATT_TEMP

2

PR309

100_0402_1%

1 2

@

0_0603_5%

1 2

1U_0603_25V6

PR312

PR319 4.7_0402_5%

12

PC313 1U_0402_10V6K

PR324 10_1206_5%

1 2

VF = 0.38V

PC302

10U_0805_25V6K

0.47U_0603_16V7K

1 2

S SCH DIO BAS40CW SOT-323

12

0.1U_0402_25V6

@EMI@

12

PC305

PC303

10U_0805_25V6K

+17.4V_BATT

PC309

1 2

12

3

1

2

PD301

PR330 2_0402_5%

1 2

PC319

PR334

@

0_0402_5%

1 2

12

0.1U_0402_25V7K

PC314 1U_0402_10V6K

EMI@

PC304

12

2200P_0402_25V7K

4

+19V_VIN

+3VS

12

1

PQ314

@

RUM001L02_VMT3

2

3

34

D

5

ACIN

G

S

3

12

PR343

@

10K_0402_1%

PQ315B

@

2N7002KDW_SOT363-6

PR342

@

10K_0402_1%

PQ315A

@

61

D

2N7002KDW_SOT363-6

2

G

S

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRI ETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRI ETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+19VB

PQ312

45W@

AON7506_DFN33-8-5

65W@

AON7506_DFN33-8-5

5

PQ305

5

Choke 4.7uH SH0000 0YC00 (Common Part) (Size:6.6 x 7.3 x 3 mm) (DCR:28 m~33m)

AON7506_DFN33-8-5

123

4.7UH_PCMB063T-4R7MS_8A_20%

1 2

12

PQ306

5

PR320

4.7_1206_5%

EMI@

12

PC315

AON7506_DFN33-8-5

123

EMI@

680P_0402_50V7K

PR326 0_0603_5%

1 2

PR327

@

0_0603_5%

1 2

CSOP_CHG_R

CSON_CHG_R

APU_PROCHOT#_D

2017/12/25 2019/12/25

135W@

AON7380_DFN3X3-8-5

PQ312

1 2 3

4

1 2

PC308

@

0.1U_0402_25V7K

PL301

+17.4V_BATT_CHG

+17.4V_BATT

BA

Compal Secret Data

Deciphered Date

2

PQ312

PR315

0.01_1206_1%

134

2

Support max charge 3.5A Power loss: 0.245W CSR rating: 1W VCSPP-VCSON spec < 81mV

+17.4V_BATT

12

PC312

PC310

PC311

10U_0805_25V6K

PQ309

@

LMUN5113T1G_SOT323-3

2

SLP_S5#

@

LTC015EUBFS8TL_UMT3F

13

2

PQ313

Compal Electronics, Inc.

Title

PWR_CHARGER

Size

Document Number Rev

Date: Sheet o f

1 3

BA

1.B

38 48Monday, December 25, 2017

1

38 48Monday, December 25, 2017

A

1 1

PJ402

+19VB

2 2

3 3

@

JUMP_43X79

112

+3VALWP

2

PC407

EMI@

12

0.1U_0402_25V6

12

PC409

PC408

2200P_0402_50V7K

@EMI@

MAINPWON

12

10U_0805_25V6K

EC_ON

12

PC421

10U_0805_25V6K

+

PC413

PL402

3.3UH_6.3A_20%_7X7X3_M

1

2

220U_6.3V_ESR18M_6.3X4.5

12

PR413

2.2K_0402_5%

1 2

PR414

@

0_0402_5%

1 2

PR410

@EMI@

PC416

@EMI@

LX_3V

4.7_1206_5%

680P_0402_50V7K

12

PR415

1M_0402_1%

+19VB_3V

5V_EN

12

4

D1

D110D2/S1

S2

5

PC420

4.7U_0402_6.3V6M

B

C

+3VLP

PC402

@

100P_0402_50V8J

1 2

PR402

13.7K_0402_1%

1 2

VFB=2V

PR403

20K_0402_1%

1 2

PR405 105K_0402_1%

1 2

PR407

100K_0402_1%

PR408

2.2_0603_5%

1 2

LG_3V

+3VLP

1 2

+19VB

LX_3V

BST_3V

UG_3V

6

EN2

7

PGOOD

8

PHASE2

9

BOOT2

10

UGATE2

PR412

2.2_1206_1%

1 2

FB_3V

CS2_3V

4

5

FB2

CS2

VIN

LGATE2

12

11

VIN_3/5V

12

PC418

@

1U_0603_25V6K

5V Dual Mos AON7934 H/S (Q1) Rds(on) :typ:12.4mOhm, max:15.8mOhm Idsm(TA=25)=13A, Idsm(TA=70)=7.8A

L/S (Q2) Rds(on) :typ:9.1mOhm, max:11.6mOhm Idsm(TA=25)=15A(Typ), Idsm(TA=70)=9A(Typ)

Choke: 10x10x3 Rdc= 14.5mohm(Typ), 16mohm(Max)

Switching Frequency: 300kHz Ipeak= 12A Iocp~1 5A OVP: 113%

POK need pull high, it will pull high on VS transfer circuit

3V_EN

1

3

2

D1

G1

9

S2

G2

PQ402

6

7

8

EMB09A03VP_EDFN3X3-8-10

3V Dual Mos AON7934 H/S (Q1) Rds(on) :typ:12.4mOhm, max:15.8mOhm Idsm(TA=25)=13A, Idsm(TA=70)=7.8A

L/S (Q2) Rds(on) :typ:9.1mOhm, max:11.6mOhm Idsm(TA=25)=15A(Typ), Idsm(TA=70)=9A(Typ)

Choke: 7x7x3 Rdc= 18mohm(Typ), 22mohm(Max)

Switching Frequency: 355kHz Ipeak=9 .4A Iocp~11 .3A OVP: 113%

1. Vout1=2V*(1+30.9k/20k)=5.09V; Vout2=2V*(1+13.7k/20k)= 3.37V

2. 5V current limit = (140K*10uA/8/11.6mohm)= 15A

3. 3.3V current limit = (105K*10uA/8/11.6mohm) =11.3A

SPOK

PC410

0.1U_0402_25V6

1 2

BST_3V_R

PC401 1U_0402_10V6K

1 2

VFB=2 V

FB_5V

2

3

FB1

LDO3

BYP1

LDO5

14

13

+5VLP

12

PC419 1U_0402_10V6K

PC403

@

100P_0402_50V8J

1 2

PR401

30.9K_0402_1%

1 2

PR404

20K_0402_1%

1 2

PR406

140K_0402_1%

1 2

CS1_5V

PU401

1

21

RT6575DGQW(2)_ WQFN20_3X3

CS1

GND

20

EN1

19

VCLK

18

PHASE1

17

BOOT1

16

UGATE1

LGATE1

15

+5VALWP

5V_EN

LX_5V

BST_5V

UG_5V

D

Output capacitor ESR need follow below equation to make sure feed back loop stability ESR=20mV *L*fsw /2V

+19VB

PR409

2.2_0603_5%

1 2

0.1U_0402_25V6

BST_5V_R LX_5V

PC411

1 2

LG_5V

PJ401

@

JUMP_43X79

112

+19VB_5V

2

4

1

3

2

D1

G1

9

D2/S1

8

D1

S2

G2

6

7

5

+3VALWP +3VALW

12

PC405

PC404

0.1U_0402_25V6

EMI@

@EMI@

PQ401 EMB09A03VP_EDFN3X3-8-10

D1

10

S2

PC417

@EMI@

680P_0402_50V7K

PJ403

@

112

JUMP_43X118

PJ404

@

112

JUMP_43X118

E

12

2200P_0402_50V7K

3.3UH_VMPI1004AR-3R3M- Z01_11A_20%

1 2

12

PR411

4.7_1206_5%

@EMI@

12

2

PL401

12

PC406

PC422

10U_0805_25V6K

1

+

PC414

2

220U_6.3V_ESR18M_6.3X4.5

+5VALW+5VALWP

+5VALWP

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2017/12/25 2019/12/25

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Re v

Custom

Date : Sheet o f

D

Date : Sheet o f

Compal Electronics, Inc.

+3VALW/+5VALW

DH5AV_JV_0V_LA-G021P

E

1.B

39 48Monday, December 25, 2017

1.B

5

PJ504

D D

+19VB

@

112

JUMP_43X79

2

12

PC525

EMI@

0.1U_0402_25V6

1UH_6.6A_20%_5X5X3_M

+1.2VP

12

C C

Mode Level +0.6VSP VTTREF_1.2V S5 L off off S3 L off on S0 H on on

Note: S3 - sleep ; S5 - power off

B B

A A

+3VALW

PC511

12

22U_0603_6.3V6M

SYSON

12

PC512

22U_0603_6.3V6M

PJ505

@

112

JUMP_43X39

0_0402_5%

1 2

12

PC513

22U_0603_6.3V6M

2

PR515

@

12

PC515

PC514

22U_0603_6.3V6M

12

PC521

4.7U_0402_6.3V6M

12

PC520

@

0.1U_0402_16V7K

PC516

22U_0603_6.3V6M

VIN_2.5VVIN_2.5V

EN_2.5V

12

+19VB_1.5V

12

PC501

0.1U_0402_25V6

@EMI@

PL503

1 2

@EMI@

4.7_1206_5%

@EMI@

680P_0402_50V7K

H/S AON7408 Rds(on) :typ:27mOhm, max:34mOhm Idsm(TA=25)=7.5A, Idsm(TA=70)=5.5A

L/S AON7506 Rds(on) :typ:13mOhm, max:15.8mOhm Idsm(TA=25)=12A, Idsm(TA=70)=10.5A

Choke: 5x5x3 Rdc=13mohm(Typ), 14mohm(Max)

Switching Frequency: 530kHz Ipeak=9. 5A Iocp~11. 4A OVP: 110%~120%

+5VALW

PR511

1M_0402_5%

PC502

EMI@

PR503

PC517

2200P_0402_50V7K

12

PC503

12

PC524

1U_0402_6.3V6K

4

VDD

3

VIN

2

EN

1

PGOOD

4

12

PC504

10U_0805_25V6K

5

4

PQ501

AON7408L_DFN8-5

123

5

PQ502

G9661MF11U_SO8PU502

5

NC

6

VOUT

7

ADJ

8

GND

9

4

AON7506_DFN3X3-8-5

123

Due to buyer command. PC508,PC510 need change to SE00000QL10. Because 0603 change to 0402, PVT need change footprint.

21.5K_0402_1%

10K_0402_1%

+5VALW

PR512

FB_2.5V

PR513

0.1U_0603_25V7K

PC505

12

Rup

12

Rdown

12

5.1_0603_5%

1 2

1U_0402_10V6K

12

PR504

PC522

PC510

0.01U_0402_25V7K

12

PC523

3

BST_1.5V_R

24.9K_0402_1%

1 2

@

RB751V-40_SOD323-2

+2.5VP

22U_0603_6.3V6M

PR501

2.2_0603_5%

1 2

PR502

PC508

1U_0402_10V6K

1 2

PD501

+5VALW

SYSON

SUSP#

LG_1.5V

CS_1.5V

VDD_1.5V

12

+19VB_1.5V

15

14

13

12

11

PR505

2.2_0603_5%

1 2

PR507 470K_0402_1%

1 2

0_0402_5%

1 2

BST_1.5V

UG_1.5V

LX_1.5V

16

PU501

PHASE

LGATE

PGND

CS

RT8207PGQW_WQFN20_3X 3

VDDP

VDD

PGOOD

10

PR509

@

0_0402_5%

1 2

PC518

@

0.1U_0402_10V7K

PR510

@

2

1

0.6Volt +/- 5% TDC 0.7A Peak Current 1A

+1.2VP

+0.6VSP

12

18

17

UGATE

TON

9

TON_1.5V

EN_1.5V

8

12

BOOT

S5

20

19

21

VTT

PAD

VLDOIN

S3

7

EN_0.75VSP

12

1

VTTGND

2

VTTSNS

3

GND

VTTREF_1.5V

4

VTTREF

5

VDDQ

FB

6

FB_1.5V

12

PR506

6.19K_0402_1%

1 2

PR508 10K_0402_1%

+1.2VP

+1.2VP +1.2V

PC519

@

0.1U_0402_10V7K

JUMP_43X118

+0.6VSP +0.6VS

+2.5VP

12

PC506

PC507

10U_0603_6.3V6M

12

PC509

0.033U_0402_16V7K

+1.2VP

0.75*(1+ 6.19/10) =1.21

PJ501

@

2

112

PJ502

@

2

112

JUMP_43X39

PJ503

@

2

112

JUMP_43X39

10U_0603_6.3V6M

+2.5V

Vout=0.8V* (1+(21.5/10)) = 2.52V 0.8%

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2017/12/25 20 19/12/25

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Re v

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

+1.5VP/+0.75VSP

DH5AV_JV_0V_LA-G021P

1

1.B

40 48Monday, December 25, 2017

1.B

5

4

3

2

1

D D

EN pin don't floating If have pull down resistor at HW side, pls delete PR2

LDO_VDDP

12

PR604

@

0_0402_5%

ILMT_VDDP

12

PR605

@

0_0402_5%

C C

B B

+3VALW

+19VB

0.9_1.8VALW_PWREN

PJ602

@

IN_1.8VALW

2

112

JUMP_43X79

PC617

22U_0603_6.3V6M

Not e: When des ign Vin=5V, please stuff snubber to prevent Vin damage

PJ604

@

2

112

JUMP_43X79

@

0_0402_5%

1 2

FB=0 .6V Note: Iload (max )=3 .5A

12

FB=0.6V

Note:Iloa d(max)=3A

PR601

PR607 1M_0402_1%

PU602

PGND

1

FB

SGND

2

PG

3

IN

4

PGND

SY8003ADFC_DFN8_2X2

PC623

EMI@

0.1U_0402_25V6

12

EN

LX

NC

12

9 8

7

6

5

PC601

EMI@

2200P_0402_50V7K

12

PC604

PC605

0.1U_0402_25V6

@EMI@

PC614

@

0.22U_0402_10V6K

LX_1.8VALW

12

+19VB_VDDP

12

PC622

10U_0805_25V6K

+3VALW

PC616

@

0.1U_0402_16V7K

1UH_2.8A_30%_4X4X2_F

1 2

12

PR613

4.7_0603_5%

@EMI@

FB_1.8VALW

12

PC621

@EMI@

680P_0402_50V7K

PU601

2

IN

3

IN

4

IN

5

IN

7

GND

8

GND

18

GND

11

12

PR612

1M_0402_5%

12

Rup

12

Rdo wn

EN

13

ILMT

15

BYP

PC615

SY8288RAC_QFN20_3X3

1U_0402_6.3V6K

PR611

@

0_0402_5%

1 2

Note: Iload (max )=2 .5A

12

PC618

PC619

68P_0402_50V8J

12

PL603

PR614

20K_0402_1%

PR615

10K_0402_1%

ILMT_VDDP

12

Vout=0.6V* (1+Rup/Rdown)

PG

BS

LX

FB

VCC

NC

PAD

9

1

6

19

20

14

17

10

12

16

21

0.9_1.8VALW_PWREN

BST_VDDP

LX_VDDP

FB_VDDP

LDO_VDDP

PR603

@

0_0603_5%

1 2

12

PC612

2.2U_0402_6.3V6M

PC602

0.1U_0603_25V7K

1 2

FB = 0.6V

PR602

@EMI@

4.7_1206_5%

1 2

PL602

1UH_6.6A_20%_5X5X3_M

1 2

(R2 )

SNB_VDDP

@EMI@

680P_0402_50V7K

1 2

12

PC613

330P_0402_50V7K

13.7K_0402_1%

1 2

(R1 )

12

PR609

24.3K_0402_1%

PR606

PC603

PR610

10_0402_1%

+1.8VALWP

PJ603

12

PC620

22U_0603_6.3V6M

+1.8VALWP

@

112

JUMP_43X79

2

+1.8VALW

+0.9VALWP

12

PC606

22U_0603_6.3V6M

1 2

PR622

@

0_0402_5%

1 2

PR621

@

0_0402_5%

PC607

22U_0603_6.3V6M

1

PJ601

@

112

JUMP_43X118

12

PC608

22U_0603_6.3V6M

2

3

PQ601

@

LSK3541G1ET2L_VMT3

2

+0.9VALW

+0.9VALWP

12

PC610

PC609

22U_0603_6.3V6M

1 2

PR623

@

0_0402_5%

PC611

22U_0603_6.3V6M

VR_ON

APU_VDDP_SEN_H

APU_VDDP_SEN_L

VFB= 0.6V Vout= 0.6V*(1+R1 /R2) =0. 9V

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/12/25 2019/12/25

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size

C

Date: Shee t of

Compal Electronics, Inc.

+0.95VALW/+1.8VALW

Document Number Rev

Document Number R ev

+0.95VALW/+1.8VALW

DH5AV_JV_0V_LA-G021P

1

41 48M onday, December 25, 2017

1.B

5

1 2

12

VREF_C PU

@

330P_0 402_50 V7K

PC827

0.47U_0402_6.3V6K

APU_CORE_SEN_H

LL CORE(Rdroop)=2.079m

1 2

PC801

@

APU_PW ROK

APU_SVC

APU_SVD

APU_SVT_R

PR818

25.5K_0 402_1%

1 2

PR822

5.9K_04 02_1%

1 2

PR823

20.5K_0 402_1%

1 2

12

PC828

@

0.47U_0402_6.3V6K

PR802

10_040 2_5%

1 2

10K_04 02_1%

1 2

270P_0 402_50 V7K

1 2

1U_0402 _6.3V6K

12

PR805

PC807

PC813

12

0.01U_04 02_50V 7K

1 2

PH802

100K_0402_1%_B25/50 4250K

PC802

+APU_COR E

35W_C PU@

+1.8VS

PR815

@

0_0402 _5%

APU_PROCHOT#

Pull high at HW side

15W_C PU@

80.6K_0 402_1%

34.8K_0 402_1%

1 2

PC808

68P_04 02_50V 8J

1 2

IMON_CPU

VREF_C PU

IMONA_CP U

APU_SVC

APU_SVD

APU_SVT

SET1_C PU

SET2_C PU

+5VS +5VS

PR806

PR844

PR843

0_0402_5%

1 2

15W_CPU@

35W_CPU@

PR806

FB_CPU

COMP_CPU

12

11

13

FB

VSEN

COMP

14

RGND

15

IMON

16

V064/SET3

17

IMONA

18

VDDIO

19

PWROK

20

SVC

21

SVD

22

SVT

23

OFS

24

OFSA

25

SET1

26

SET2

OCP_L27VCC28IBIAS29COMPA30FBA31VSENA32ISENA2P33ISENA2N34ISENA1N35ISENA1P36EN37PGOODA

IBIAS_CPU

VCC_CPU

12

PR827

100K_0402_1%

PC829

68P_04 02_50V 8J

1 2

PR831

97.6K_0 402_1%

1 2

ISEN3N_CPU

ISEN3P_CPU

PR845

0_0402_5%

1 2

35W_CPU@

ISEN1P_CPU

ISEN1N_CPU

ISEN3P_CPU_IC

ISEN3N_CPU_IC

8

10

9

ISEN1P

ISEN3P

FBA_CPU

COMPA_CPU

+5VS

APU_VSS_SEN_L

PR801

10_040 2_5%

1 2

D D

Iocp_spikea = (3.19375 - 0.64)* PR755/ (2*DCR*Rimona)

Iocp_TDCA has relation between ocp_spikea and Δ VSET1

Δ VSET1 = +5VS*( PR788//PR784 )

SVD_CPU and SVC_CPURC filter put CPU side. SVT_CPU RC filter put controlle r side.

C C

VCC_CP U

B B

PR859

43K_04 02_1%

1 2

15W_C PU@

PR816

16.5K_0 402_1%

15W_C PU@

PR821

8.66K_0 402_1%

15W_C PU@

PR825

17.8K_0 402_1%

1

PC852

PR858

0.022U_0 402_25 V7K

2

1 2

48.7K_0402_1%

PC852󵚩IC Pin16

35W_C PU@

PR816

7.87K_0 402_1%

35W_C PU@

PR821

12.1K_0 402_1%

1 2

12

35W_C PU@

PR825

PH801

14.3K_0 402_1%

100K_0402_1%_B25/50 4250K

Iocp_spike = (3.19375 - 0.64)* PR709/ (DCR*Rimon )

Iocp_TDC has relation between o cp_spike and Δ VSET1

Δ VSET1 = +5VS*( PR788//PR784 )

LL_SOC(Rdroop)=3.9 92m

PR834

8.2K_04 02_1%

1 2

PR836 470_04 02_1%

1 2

A A

5

PR835

124K_0 402_1%

1 2

PR837

33K_04 02_1%

1 2

SET2_CPU SET1_CPU

VCC_CPU

+APU_COR E_SOC

0.01U_04 02_50V 7K

PC838

+19VB_CPU

PR846

0_0402_5%

1 2

15W_CPU@

ISEN2P_CPU

ISEN2N_CPU

5

6

ISEN2N

ISEN1N7ISEN3N

ISENA1N_CPU

PC830

270P_0 402_50 V7K

1 2

PR832

10K_04 02_1%

1 2

PR833

10_040 2_5%

1 2

12

4

CORE SW= 430KHz

PR807

1 2

88.7K_0402_1%

12

PR848

15W_C PU@

0_0402 _5%

12

PR847

35W_C PU@

0_0402 _5%

TONSET_CPU

PWM3_CPU_IC

BST2_CPU

UG2_CPU

PU801

3

4

1

2

RT3663 BCGQW _WQF N52_6X6

53

PWM3

GND

BOOT2

ISEN2P

UGATE2

TONSET

ISENA1P_CPU

LX2_CP U

52

PHASE2

LG2_CP U

51

LGATE2

PVCC_C PU

50

PVCC

LG1_CP U

49

LGATE1

LX1_CP U

48

PHASE1

UG1_CPU

47

UGATE1

BST1_C PU

46

BOOT1

LG1_NB

45

LGATEA1

LX1_NB

44

PHASEA1

UG1_NB

43

UGATEA1

BST1_NB

42

BOOTA1

41

PWMA2

40

TONSETA

PGOOD

38

39

Confirm HW side the pull high resistor

1 2

PR828

100K_0 402_5%

12

PC831

@

PC833

@

330P_0 402_50 V7K

1 2

APU_VSS_SEN_L

APU_CORESOC_SEN_H

4

Module model information

RT8880C_CZ35W_V2A.mdd for IC portion

RT8880C_CZ35W_V2B.mdd for SW portion

+5VS

PWM3_C PU

PVCC_C PU

VCC_CP U

12

PC814

2.2U_0603_10V6K

PR819

+5VS

100K_0 402_1%

+19VB_C PU

1 2

VGATE

+3VS

VR_ON

EN: high > 2V, Low < 0.8V Can't be floating.

12

PR829

@

10K_04 02_5%

0.1U_0402_25V6

PR811

2.2_040 2_5%

1 2

PR812

12

10_060 3_5%

PC815

2.2U_0603_10V6K

UG1_CPU

PR839

2.2_060 3_5%

BST1_C PU

1 2

LX1_CP U

LG1_CP U

UG1_NB

PR804

2.2_060 3_5%

BST1_NB BST1_NB1_ R

1 2

LX1_NB

LG1_NB

UG2_CPU

BST2_C PU

LX2_CP U

LG2_CP U

PR838

0_0603 _5%

1 2

0.22U_06 03_25V 7K

BST1_C PU_R

PR803 0_0603 _5%

1 2

0.22U_06 03_25V 7K

1 2

3

2

D1

PQ802 AON6962 _DFN5X6 D-8-7

S23G2

12

PC810

@EMI@

2200P_0402_50V7K

12

PC804

10U_0805_25V6K

ISENA1P _CPU_R

2.7K_04 02_1%

1 2

PC826

@EMI@

PC839

+19VB_C PU

PR809

1 2

PR810

845_04 02_1%

PC819

10U_0805_25V6K

12

SNB_APU

12

680P_0402_50V7K

12

10U_0805_25V6K

PC843

680P_0402_50V7K

@EMI@

+19VB_CPU

12

PC821

PC818

0.1U_0402_25V6

10U_0805_25V6K

@EMI@

ISEN2P_ CPU_R

PR824

PR826

2.7K_04 02_1%

1 2

4.7_1206_5%

@EMI@

ISEN2P_ CPU

PR830

1.1K_04 02_1%

ISEN2N_C PU

1 2

+19VB_CPU

12

PC840

10U_0805_25V6K

ISEN1P_ CPU_R

12

PR840

PR841

2.7K_04 02_1%

1 2

4.7_1206_5%

@EMI@

SNB_APU2

12

ISEN1P_ CPU

ISEN1N_C PU

PL803

0.22UH_24 A_20%_ 7X7X4 _M

134

2

1 2

PC806

0.1U_040 2_25V6

ISENA1N_CPU-1

12

PC812

@

0.1U_0402_25V6

1

12

+

PC822

2

@EMI@

2200P_0402_50V7K

PL804

0.22UH_24 A_20%_ 7X7X4 _M

134

2

1 2

PC825

0.1U_040 2_25V6

12

PC832

@

0.1U_0402_25V6

PL805

0.22UH_24 A_20%_ 7X7X4 _M

134

2

1 2

PC842

0.1U_040 2_25V6

PR842

1.1K_04 02_1%

1 2

12

PC844

@

+APU_COR E_SOC

PC820

33U_25V_NC_6.3X4.5

0.1U_0402_25V6

PR817

0_0603 _5%

UG2_CPU_ R

1 2

1

1 2

2

S24S2

2

S24S2

7

D1

PQ804 AON6962 _DFN5X6 D-8-7

S23G2

D1

PQ801 AON6962 _DFN5X6 D-8-7

S23G2

G1

D2/S1

S24S2

5

6

PC809

0.1U_0402_25V6

@EMI@

12

PC803

10U_0805_25V6K

12

PR808

4.7_1206_5%

SNB_APU_ NB

@EMI@

12

PC811

680P_0402_50V7K

@EMI@

ISENA1P _CPU

ISENA1N_ CPU

PC824

PR820

0.22U_06 03_25V 7K

2.2_060 3_5%

BST2_C PU_R

1 2

+5VALW

UG1_CPU_ R

1

PC841

UG1_NB_R

PC805

1 2

G1

7

D2/S1

5

6

1

G1

7

D2/S1

5

6

3

2

PL801

EMI@

NA_2P

1 2

PL802

EMI@

1

+

2

ISEN2N_CPU_R

NA_2P

1 2

PC834

33U_25V_NC_6.3X4.5

+APU_COR E

PWM3_C PU LX3_ CPU

+5VS

35W_C PU@

1U_0603 _10V6K

1 2

ISEN1N_CPU_R

+APU_CO RE_SO C TDC 10A (15W & 25W &35W) EDC 13A (15W & 25W &35W) OCP current 18.2A (15W & 25W &35W) Load line -4mV/A FSW=4 00kHz DCR 0.98mohm +/-5% TYP MAX H/S Rds(on) :11.7mohm , 14mohm L/S Rds(on) :2.7mohm , 3.3mohm

Security C lassification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I NC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I NC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

BST3_CPU

PC845

35W_C PU@

PR860

2.2_060 3_5%

1 2

+19VB

APU_c ore TDC 35A (15W & 25W), 53A (35W) EDC 45A (15W & 25W), 70A (35W) OCP current 63A (15W & 25W), 98A (35W) Load line -2.1mV/A FSW=4 30kHz DCR 0.98mohm +/-5% TYP MAX H/S Rds(on) :11.7mohm , 14mohm L/S Rds(on) :2.7mohm , 3.3mohm

35W_C PU@

PC846

0.22U_06 03_25V 7K

BST3_C PU_R

1 2

35W_C PU@

PU802

4

3

BOOT

UGATE

5

2

PWM

PHASE

1

6

EN

PGND

8

VCC

RT9610 CGQW_ WDFN8 _2X2

LG3_CP U

7

LGATE

9

GND

Compal Secret Data

2017/12/25 201 9/12/25

35W_C PU@

PR853 0_0603 _5%

1 2

Deciphered Date

UG3_CPU_ RUG3 _CPU

AON6962 _DFN5X6 D-8-7

1

+19VB_CPU

PC847

PC848

PQ80535W _CPU@

1

G1

7

D2/S1

5

6

12

2

10U_0805_25V6K

35W_CPU@

D1

S24S2

S23G2

Title

Size

Date: Sheet o f

12

PC817

PC816

0.1U_0402_25V6

@EMI@

10U_0805_25V6K

2200P_0402_50V7K

35W_CPU@

ISEN3P_ CPU_R

PR855

35W_C PU@

12

2.7K_04 02_1%

1 2

@EMI@

4.7_1206_5%

SNB_APU3

12

PC849

680P_0402_50V7K

@EMI@

ISEN3P_ CPU

35W_C PU@

ISEN3N_C PU

Compal Electronics, Inc.

RT8880CGQW

Document Number Rev

1

35W_C PU@

0.22UH_24 A_20%_ 7X7X4 _M

PR856

PR857

1.1K_04 02_1%

1 2

134

2

1 2

35W_C PU@

PC850

0.1U_040 2_25V6

12

PC851

@35W_CPU@

42 48Monday, De cembe r 25, 2017

PL806

+APU_COR E

ISEN3N_CPU_R

0.1U_0402_25V6

1.B

+APU_CORE

5

4

3

2

1

+APU_CORE +APU_CORE_SOC

+APU_CORE_SOC

D D

C C

B B

12

PC9002

PC9001

22U_0603_6.3V6M

12

PC9030

PC9029

22U_0603_6.3V6M

12

PC9052

PC9048

22U_0603_6.3V6M

12

PC9056

12

PC9081

12

PC9003

22U_0603_6.3V6M

12

PC9031

22U_0603_6.3V6M

12

PC9046

22U_0603_6.3V6M

12

PC9057

0.22U_0402_16V7K

180P_0402_50V8J

12

PC9005

PC9004

22U_0603_6.3V6M

12

PC9032

PC9033

22U_0603_6.3V6M

12

PC9050

PC9051

22U_0603_6.3V6M

12

PC9059

PC9058

0.22U_0402_16V7K

12

22U_0603_6.3V6M

12

22U_0603_6.3V6M

12

22U_0603_6.3V6M

12

0.22U_0402_16V7K

12

PC9006

22U_0603_6.3V6M

12

PC9034

22U_0603_6.3V6M

12

PC9047

22U_0603_6.3V6M

12

PC9060

0.22U_0402_16V7K

PC9008

PC9007

22U_0603_6.3V6M

12

PC9035

PC9036

22U_0603_6.3V6M

12

PC9049

22U_0603_6.3V6M

12

PC9061

PC9062

0.22U_0402_16V7K

12

PC9009

22U_0603_6.3V6M

12

PC9037

22U_0603_6.3V6M

12

PC9063

0.22U_0402_16V7K

12

PC9010

22U_0603_6.3V6M

12

PC9038

22U_0603_6.3V6M

0.22U_0402_16V7K

1

+

2

12

PC9012

PC9011

22U_0603_6.3V6M

12

PC9040

PC9039

22U_0603_6.3V6M

12

1

+

PC9100

PC9099

2

330U_D2_2V_Y

12

PC9013

22U_0603_6.3V6M

12

PC9041

22U_0603_6.3V6M

12

PC9065

PC9064

0.22U_0402_16V7K

PC9082

180P_0402_50V8J

APU_CORE_SOC 330uF*2 22uF*18

0.22uF*8

330U_D2_2V_Y

12

PC9015

PC9014

22U_0603_6.3V6M

12

PC9042

22U_0603_6.3V6M

PC9066

0.22U_0402_16V7K

PC9016

22U_0603_6.3V6M

12

PC9043

PC9044

22U_0603_6.3V6M

12

PC9067

0.22U_0402_16V7K

180pF*1

12

PC9017

PC9018

22U_0603_6.3V6M

12

22U_0603_6.3V6M

12

PC9068

0.22U_0402_16V7K

22U_0603_6.3V6M

12

PC9053

PC9045

22U_0603_6.3V6M

12

PC9069

PC9070

0.22U_0402_16V7K

12

PC9019

PC9020

22U_0603_6.3V6M

PC9071

0.22U_0402_16V7K

near CPU

+APU_CORE

330u is common part SGA00009S00

1

+

PC9095

2

1

+

PC9097

PC9096

2

330U_D2_2V_Y

1

+

PC9094

@

PC9098

2

330U_D2_2V_Y

APU_CORE 330uF*5 22uF*27

0.22uF*8 180pF*1

near CPU

A A

CPU back side

330u is common part SGA00009S00

Security Classification

2017/12/ 25 2019/12/ 25

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

2017/12/ 25 2019/12/ 25

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Re v

Custom

Date : Sheet o f

2

Date : Sheet o f

Compal Electronics, Inc.

+APU_CORE Cap

DH5AV_JV_0V_LA-G021P

1

1.B

43 48Monday, December 25, 201 7

5

4

3

2

1

EN pin don't floating If have pull down resistor at HW side, pls delete PR2

Module model information

SY82 08D_ V1.m dd

D D

12

VGA@

PU1001

2

IN

3

IN

4

IN

5

IN

7

GND

8

GND

18

GND

11

EN

13

ILMT

15

BYP

SY8288RAC_QFN20_3X3

9

PG

1

BS

6

LX

19

LX

20

LX

14

FB

17

VCC

10

NC

12

NC

16

NC

21

PAD

@VGA@

BST_1.35V

LX_1.35V

FB_1.35V

LDO_3V_1.35

PR1001

0_0603_5%

1 2

12

VGA@

2.2U_0402_6.3V6M

PC1003

VGA@

0.1U_0603_25V7K

1 2

PC1013

PR1002

VGA_EMI@

4.7_1206_5%

SNUB_1.35V

1 2

PL1002

VGA@

0.68UH_PCMB061H-R68MS_9A_20%

1 2

PR1006

60W_VGA@

15.4K_0402_1%

FB = 0.6V

PC1004

VGA_EMI@

680P_0402_50V7K

1 2

(R1 )

12

25W_40W_50W_VGA@

PR1006

12.7K_0402_1%

12

PR1009

VGA@

10K_0402_1%

(R2 )

chock 7*7*1.8

12

PC1007

PC1014

12

VGA@

330P_0402_50V7K

VGA@

+1.35VSDGPUP

12

PC1009

VGA@

22U_0603_6.3V6M

+1.35VSDGPUP

12

22U_0603_6.3V6M

12

PC1008

22U_0603_6.3V6M

VGA@

12

PC1011

22U_0603_6.3V6M

VGA@

@

JUMP_43X118

PJ1002

112

PC1012

22U_0603_6.3V6M

VGA@

2

+1.35VSDGPU

PC1010

22U_0603_6.3V6M

VGA@

VFB=0.6V Vout=0.6V*(1+R 1/R2 )=1. 362V

+19VB

LDO_3V_1.35

C C

B B

12

@VGA@

0_0402_5%

12

@VGA@

0_0402_5%

PR1003

ILMT_1.35V

PR1005

DGPU_PWROK

PJ1001

@

112

JUMP_43X79

2

@VGA@

0_0402_5%

1 2

PC1017

VGA_EMI@

PR1004

PR1007

VGA@

1M_0402_1%

+19VB_1.35V

12

PC1001

0.1U_0402_25V6

2200P_0402_50V7K

VGA_EMI@

12

PC1005

0.1U_0402_25V6

@VGA_EMI@

12

PC1006

PC1002

VGA@

10U_0805_25V6K

@VGA@

PC1015

0.22U_0402_16V7K

10U_0805_25V6K

12

1.35V_EN

+3VALW

PC1016

VGA@

1U_0402_6.3V6K

ILMT_1.35V

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/12/25 2019/12/25

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number R ev

Custom

Date: Sheet o f

Compal Electronics, Inc.

+GFX_CORE

DH5AV_JV_0V_LA-G021P

1

44 48Monday, December 25, 2017

1.B

5

PC1401

VGA@

PR1401

10_040 2_1%

PC1414

1 2

VGA@

@

100_04 02_1%

.047U_0402_16V7K

PR1416

@VGA@

12

VGA@

12

330P_0 402_50 V7K

PR1410 0_0402 _5%

1 2

PC1412

@

1000P_ 0402_5 0V7K

PR1414

1.4K_04 02_1%

PC1423

@

220P_0 402_50 V7K

12

GPU_VDD CI_SEN

VGA@

PH1401

10K +-5% 0402 B25/50 4250K

12

PR1412

12

2.61K_0402_1%

VGA@

12

VGA@

0.1U_060 3_25V7 K

+VDDCI

1 2

PC1422

PC1413

PR1413

1 2

VGA@

11K_0402_1%

0.022U_0402_25V7K

VSUMP_NB

D D

VSUMN_NB

After rev1.1 must change to 133 k

PR1418

VGA@

27.4K_0 402_1%

PH1402

VGA@

470K_0 402_5% _TSM0B 474J47 02RE

VGA@

133K_0 402_1%

1 2

After rev1.1 must change to 133 k

VGA@

1000P_ 0402_2 5V6K

1 2

C C

470K_0 402_5% _TSM0B 474J47 02RE

B B

12

GPU_PRO CHOT#

PR1433

PC1434

PR1435

VGA@

27.4K_0 402_1%

PH1403

VGA@

12

VGA@

12.7K_0 402_1%

VGA@

100K_0 402_1%

+3VS

PR1422

PR1427

12

VGA@

133K_0 402_1%

PR1421

PC1424

VGA@

1000P_ 0402_2 5V6K

1 2

+5VALW

GPU_SVC

GPU_SVD

+1.8VSDG PU +5VALW

GPU_SVT

1 2

VGA_ON_ B

PR1434

VGA@

12.7K_0 402_1%

+5VALW

40W_5 0W_60 W_VG A@

PC1444

0.22U_06 03_25V 7K

@VGA@

1 2

0_0402 _5%

12

VSUM+

PH1404

VSUM-

VGA@

1.13K_0 402_1%

12

VGA@

1K_040 2_1%

PC1410

VGA@

1000P_ 0402_5 0V7K

12

25W_4 0W_50 W_60 W_VG A@

12

+5VALW

PR1431

DGPU_PW ROK

25W_V GA@

0_0402 _5%

1 2

40W_5 0W_60 W_VG A@

PC1436

0.22U_04 02_6.3V 6K

PC1437

VGA@

0.22U_04 02_6.3V 6K

PC1438

VGA@

0.22U_04 02_6.3V 6K

12

PR1439

12

2.61K_0402_1%

VGA@

1 2

10K +-5% 0402 B25/50 4250K

12

VGA@

0.1U_060 3_25V7 K

40W_V GA@

PR1448

732_04 02_1%

50W_V GA@

PR1448

825_04 02_1%

60W_V GA@

PR1448

PR1405

VGA@

2K_040 2_1%

PR1407

12

PR1411

VGA@

301_04 02_1%

PR1417 10K _0402_ 1%

M260_VG A@

PR1466 0_ 0402_ 5%

1 2

PU1401

1

2

3

4

5

6

7

8

9

ENABLE

10

11

12

PR1465

12

PC1443

PR1443

1 2

VGA@

11K_0402_1%

0.047U_0402_25V7K

@

100_04 02_1%

PC1448

40W_V GA@

PR1446

1.24K_0 402_1%

50W_V GA@

PR1446

1.43K_0 402_1%

60W_V GA@

PR1446

1.87K_0 402_1%

12

VGA@

37.4K_0 402_1%

12

ISEN2_NB

NTC_NB

IMON_NB

SVC

VR_HOT_L

SVD

VDDIO

SVT

ENABLE

PWROK

IMON

NTC

25W_V GA@

PC1444

0.15U_06 03_25V 7K

1 2

PR1450

PR1408

VGA@

220P_0 402_50 V8J

47

48

ISEN1_NB

ISEN3

14

13

GPU_ISEN2

GPU_ISEN3

25W_V GA@

PR1448

665_04 02_1%

PC1449

@

820P_0 402_50 V7K

12

PC1409

VGA@

390P_0 402_50 V7K

12

PC1411

12

44

45

46

FB_NB

VSEN_NB

ISUMP_NB

ISUMN_NB

S IC ISL 6277AHR Z-T QFN 4 8P

ISUMP16ISEN2

15

GPU_ISEN1

12

43

COMP_NB

18

1 2

PC1450

VGA@

0.01UF_0402_25V7K

PR1409

@

32.4K_0 402_1%

41

42

FCCM_NB

PGOOD_NB

RTN19ISUMN17ISEN1

VGA@

1000P_ 0402_2 5V6K

PC1446

330P_0402_50V7K

VGA@

@VGA@

12

39

40

PWM2_NB

FB21PGOOD23FB220VSEN

22

PC1439

0_0402 _5%

1 2

0_0402 _5%

1 2

LGATEX

COMP

12

PR1452

PR1453

38

25W_V GA@

PR1446

1K_040 2_1%

UGATEX37PHASEX

BOOT1

24

GPU_BOO T1

VGA@

301_04 02_1%

FCCM_NB

GPU_LGA TE3

GPU_PHAS E3

GPU_UGAT E3

BOOTX

BOOT2

UGATE2

PHASE2

LGATE2

VDDP

VDD

PWM_Y

LGATE1

PHASE1

UGATE1

12

VIN

TP

49

PR1440

VGA@

10_040 2_1%

VGA@

10_040 2_1%

4

PR1425

VGA@

PC1425

VGA@

2.2_060 3_5%

1 2

40W_5 0W_60 W_VG A@

PR1404

2.2_060 3_5%

GPU_BOO T3

1 2

GPU_PHAS E3

GPU_LGA TE3

12

25W_4 0W_50 W_60 W_VG A@

PC1465

1U_0402 _10V6K

0.22U_06 03_25V 7K

1 2

40W_5 0W_60 W_VG A@

PC1407

0.22U_06 03_25V 7K

1 2

25W_4 0W_50 W_60 W_VG A@

PU1402

6

UGATE1VCC

7

FCCM

BOOT

3

PWM

PHASE

4

LGATE

GND

9

TP

ISL620 8BCRZ-T _QFN8_ 2X2

0.22U_06 03_16V 7K

2

8

5

GPU_BOO T2

PR1428

GPU_PHAS E2

GPU_LGA TE2

12

+5VS

FCCM_NB

12

PR1415

VGA@

41.2K_0 402_1%

Due to buyer command. PC1428,PC1429 need change to SE00000QL10. Because 0603 c hange to 0402, PVT need change footprint.

GPU_BOO T3

36

35

GPU_BOO T2

34

GPU_UGAT E2

33

GPU_PHAS E2

32

GPU_LGA TE2

31

30

29

GPU_PW M3

28

GPU_LGA TE1

27

GPU_PHAS E1

26

GPU_UGAT E1

25

VGA@

100K_0 402_1%

1 2

PC1440

VGA@

180P_0 402_50 V8J

12

PR1447

VGA@

137K_0 402_1%

12

PR1449

VGA@

2K_040 2_1%

12

PR1451

12

+VGA_CO RE

GPU_VDD C_SEN

GPU_VSS _SEN_L

PR1454

12

@VGA@

12

0.22U_06 03_25V 7K

12

PR1436

12

PC1445

VGA@

390P_0 402_50 V7K

12

PC1447

VGA@

680P_0 402_50 V7K

12

0_0603 _5%

VGA@

1_0603 _5%

PC1428

VGA@

1U_0402_10V6K

PR1424

PC1427

PR1430

+3VS

DGPU_PW ROK

PR1441

@

32.4K_0 402_1%

GPU_B+

12

@VGA@

0_0603 _5%

12

PC1429

VGA@

1U_0402_10V6K

12

7

D2/S1

PC1466

UGATE_NB 1

BOOT_NB 1

PHASE_NB 1GPU_PW M3

LGATE_ NB1

GPU_UGATE2

1

6

2

D1

G1

AON6962 _DFN5X6 D-8-7

S24S2

S23G2

5

GPU_UGATE3

1

G1

7

D2/S1

5

6

1 2 12

25W_4 0W_50 W_60 W_VG A@

PR1464

2.2_060 3_5%

3

PQ1402VGA@

2

D1

40W_5 0W_60 W_VG A@

PQ1401 AON6962 _DFN5X6 D-8-7

S24S2

S23G2

12

@EMI@

4.7_120 6_5%

12

@EMI@

680P_0 402_50 V7K

12

PC1418

PC1417

10U_0805_25V6K

VGA@

PR1419

PC1426

12

PC1403

10U_0805_25V6K

40W_50W_60W_VGA@

PR1402

@EMI@

4.7_120 6_5%

PC1408

@EMI@

680P_0 402_50 V7K

UGATE_NB 1

GPU_B+

2

GPU_B+

12

PC1420

12

PC1419

0.1U_0402_25V6K

@EMI@

2200P_0402_50V7K

10U_0805_25V6K

VGA_EMI@

PR1420

VGA@

10K_04 02_1%

GPU_ISE N2

1 2

PR1423

VGA@

3.65K_0 603_1%

1 2

VSUM+

PR1426

VGA@

1_0402 _1%

1 2

VSUM-

GPU_B1+

PC1405

12

PC1404

PC1406

@EMI@

2200P_0402_50V7K

0.1U_0402_25V6

10U_0805_25V6K

40W_50W_60W_VGA@

40W_50W_60W_VGA_EMI@

40W_5 0W_60 W_VG A@

10K_04 02_1%

GPU_ISE N3

1 2

40W_5 0W_60 W_VG A@

3.65K_0 603_1%

1 2

VSUM+

40W_5 0W_60 W_VG A@

1 2

VSUM-

5

25W_4 0W_50 W_60 W_VG A@

PQ1404 AON6380 _DFN5X6 -8-5

4

123

5

25W_4 0W_50 W_60 W_VG A@

PQ1405 AON6314 _N_DFN56 -8-5

4

123

PL1403

60W_V GA@

0.22UH_MMD-06 DZER2 2MEM2L__ 32A_2 0%

(DCR:0.98± 5 %)

25W_4 0W_50 W_VG A@

PL1403

0.22UH_24 A_20%_ 7X7X4 _M

134

2

PJ1402

@

2

112

JUMP_43X 79

12

60W_V GA@

0.22UH_MMD-06 DZER2 2MEM2L__ 32A_2 0%

(DCR:0.98± 5 %)

40W_5 0W_VG A@

PL1405

0.22UH_24 A_20%_ 7X7X4 _M

134

2

PR1460

PR1461

PR1462

1_0402 _1%

GPU_VDDCI

12

PC1463

PC1462

10U_0805_25V6K

25W_40W_50W_60W_VGA@

12

@EMI@

4.7_120 6_5%

12

@EMI@

680P_0 402_50 V7K

PL1405

PC1461

@EMI@

2200P_0402_50V7K

PR1463

PC1467

+VGA_CORE

12

PC1460

0.1U_0402_25V6

25W_40W_50W_60W_VGA_EMI@

25W_4 0W_50 W_60 W_VG A@

VSUMP_NB

25W_4 0W_50 W_60 W_VG A@

VSUMN_NB

+19VB

3.65K_0 603_1%

JUMP_43X 79

1 2

1_0402 _1%

1 2

VGA@

GPU_BOO T1

1 2

GPU_PHAS E1

GPU_LGA TE1

PJ1403

@

2

112

25W_4 0W_50 W_60 W_VG A@

0.47UH_PC MB061H-R4 7MS_11A _20%

PR1403

PR1406

PR1444

VGA@

2.2_060 3_5%

0.22U_06 03_25V 7K

+19VB

(DCR:7.3± 5 %)

PL1402

134

2

GPU_UGATE1

1

2

D1

PC1441

1 2

G1

7

AON6962 _DFN5X6 D-8-7

D2/S1

S24S2

S23G2

5

6

VGA_C ORE TDC 30A (25W), 47A (40W), 55A (50W), 60A (60W) EDC 45A (25W), 80A (40W), 105A (50W), 140A (60W) OCP current 63A (25W), 120A (40W), 147A (50W), 200A (60W) Load line -0.6mV/A FSW=4 00kHz DCR 0.98mohm +/-5% TYP MAX H/S Rds(on) :11.7mohm , 14mohm L/S Rds(on) :2.7mohm , 3.3mohm

+VDDC I TDC 8A (25W & 40W & 50W & 60W) EDC 12A (25W & 40W & 50W & 60W) OCP current 18A (25W &50W) FSW=4 00kHz DCR 0.98mohm +/-5% TYP MAX H/S Rds(on) :11.7mohm , 14mohm L/S Rds(on) :2.7mohm , 3.3mohm

chock 7*7*1.8

+VDDCI

12

PC1431

PC1435

10U_0805_25V6K

VGA@

PQ1403VGA@

12

PR1437

@EMI@

4.7_120 6_5%

12

PC1442

@EMI@

680P_0 402_50 V7K

PC1432

2200P_0402_50V7K

@EMI@

GPU_ISE N1

VSUM+

VSUM-

12

VGA@

12

PC1433

0.1U_0402_25V6

VGA_EMI@

PR1438

10K_04 02_1%

1 2

PR1442

3.65K_0 603_1%

1 2

PR1445

1_0402 _1%

1 2

1

PJ1401

@

112

JUMP_43X 79

(DCR:0.98± 5 %)

25W_4 0W_50 W_VG A@

PL1404

0.22UH_24 A_20%_ 7X7X4 _M

134

2

0.22UH_MMD-06 DZER2 2MEM2L__ 32A_2 0%

60W_V GA@

+19VB

PL1404

+VGA_CORE

PC1480

12

M260_VG A@

PU1406

2

IN

3

IN

4

IN

5

IN

7

GND

8

GND

18

GND

11

EN

13

ILMT

15

BYP

SY8284R AC_QFN2 0_3X3

PG

BS

LX

FB

VCC

NC

PAD

9

1

6

19

20

14

17

10

12

16

21

4

@M260_VG A@

0_0603 _5%

0.8VSDG PUP_BST _VDDP

1 2

0.8VSDG PUP_LX_ VDDP

0.8VSDG PUP_FB_ VDDP

0.8VSDG PUP_LDO _VDDP

PR1471

M260_VG A@

12

PC1478

2.2U_040 2_6.3V6 M

M260_VG A@

PC1477

0.1U_060 3_25V7 K

1 2

@M260_VG A_EMI@

PR1478

4.7_120 6_5%

1 2

M260_VG A@

PL1406

1UH_6.6A_ 20%_5X 5X3_M

1 2

FB = 0.6V

0.8VSDG PUP_SNB_ VDDP

(R1)

12

M260_VG A@

PR1476

5.9K_04 02_1%

12

M260_VG A@

PR1475

10K_04 02_1%

(R2)

@M260_VG A_EMI@

PC1481

680P_0 402_50 V7K

1 2

12

PC1484

330P_0402_50V7K

M260_VGA@

+0.8VS DGPUP TDC 2A (R535_25W) 4A (R560_60W)

Vout=0.6V* (1+Rup/Rdown) =0.954V R535 25W =0.906V R560 60W

12

PC1475

PC1474

PC1483

PC1473

22U_0603_6.3V6M

M260_VGA@

+0.8VSDG PUP

3

12

PC1482

22U_0603_6.3V6M

M260_VGA@

@

112

JUMP_43X 118

PJ1407

+0.8VSDGPUP

PC1470

22U_0603_6.3V6M

M260_VGA@

2

+0.8VSDG PU

Security C lassification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I NC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I NC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

Compal Secret Data

2017/12/25 201 9/12/25

Deciphered Date

Compal Electronics, Inc.

Title

RT8880CGQW

Size

Document Number Rev

Date: Sheet o f

1

45 48Monday, De cembe r 25, 2017

+19VB

PJ1406

@

2

112

0.8VSDGPUP_LDO_VDDP

12

@M260_VG A@

PR1474

0_0402 _5%

0.8VSDG PUP_ILMT _VDDP

12

@M260_VG A@

PR1477

0_0402 _5%

A A

JUMP_43X 79

M260_VG A@

VGA_ON

5

PC1471

M260_VGA_EMI@

PR1473

40.2K_0 402_1%

1 2

M260_VG A@

PR1472

1M_0402 _1%

12

PC1472

PC1479

0.1U_0402_25V6

@M260_VGA_EMI@

M260_VGA_EMI@

2200P_0402_50V7K

12

M260_VGA@

0.1U_0402_25V6

12

M260_VG A@

PC1476

0.47U_04 02_6.3V 6K

PC1486

10U_0805_25V6K

12

M260_VGA@

+19VB_0 .8VSDG PUP

12

PC1485

10U_0805_25V6K

0.8VSDG PUP_ILMT _VDDP

+3VALW

M260_VG A@

1U_0402 _6.3V6K

1.B

A A

B B

C C

D D

+VGA_CORE

PC1517

PC1523

@VGA@

22U_0603_6.3V6M

PC1540

VGA@

220U_D2 SX_2VY_R9M

5

4

60W_VGA@

330U_D1_2VY_R9M

VGA@

220U_D2 SX_2VY_R9M

2

VGA@

220U_D2 SX_2VY_R9M

2

VGA@

220U_D2 SX_2VY_R9M

2

Non 60W_VGA@

220U_D2 SX_2VY_R9M

2

PC1539

2

PC1501

PC1502

PC1504

PC1505

1

+

1

+

1

+

1

+

1

+

1

+

330U_D1_2VY_R9M

60W_VGA@

PC1505

@VGA@

22U_0603_6.3V6M

@VGA@

22U_0603_6.3V6M

@VGA@

22U_0603_6.3V6M

12

PC1525

12

PC1524

12

PC1522

12

VGA@

22U_0603_6.3V6M

PC1518

VGA@

22U_0603_6.3V6M

PC1519

VGA@

22U_0603_6.3V6M

PC1520

VGA@

22U_0603_6.3V6M

PC1521

VGA@

22U_0603_6.3V6M

PC1543

VGA@

2.2U_0402_6.3V6M

PC1544

VGA@

2.2U_0402_6.3V6M

PC1507

VGA@

12

22U_0603_6.3V6M

PC1508

VGA@

22U_0603_6.3V6M

PC1509

VGA@

22U_0603_6.3V6M

PC1510

VGA@

22U_0603_6.3V6M

PC1511

VGA@

22U_0603_6.3V6M

PC1512

VGA@

22U_0603_6.3V6M

PC1513

VGA@

22U_0603_6.3V6M

PC1514

VGA@

22U_0603_6.3V6M

PC1515

VGA@

22U_0603_6.3V6M

PC1516

VGA@

22U_0603_6.3V6M

12

+VDDCI +0.8VSDGPU

+VGA_CORE

5

4

+VGA_CORE +VDDCI

SOLDER_PREFORMS_0402

P150_P170_G190_VGA@

1

PR1503

3

1

2

SOLDER_PREFORMS_0402

1

2

M260_VGA@

1

2

PR1502

2

3

PR1501

+VDDCI

2

25W_40W_50W_60W _VGA@

Title

Size

Date : She et o f

Title

Size

Title

Size

B

Document Number Re v

DH5AV_JV_0V_LA-G021P 1.B

<Title>

Document Number Re v

DH5AV_JV_0V_LA-G021P 1.B

<Title>

Document Number Re v

DH5AV_JV_0V_LA-G021P 1.B

<Title>

@25W_40W_50W_60W_ VGA@

PC1545

330U_D1_2VY_R9M

2

+

PC1546

22U_0603_6.3V6M

PC1547

22U_0603_6.3V6M

1

12

2

1

46 48Monday, December 25, 2017

1

5

Version change list (P.I.R. List)

Design Update Down Size for EMI Cap

01

Design Update Down Size for VGA Cap Change PC1443 from 0.047U_0603_25V7M (SE042473M80) to 0.047U_0402_25V7K (SE00000MJ00)45

02

D D

Design Update Solution Change

03

Reason for change Rev. PG# Modify List Date Pha seFixed IssueItem

04

05

Design Update change to r-short 2017/11/1 B

Design Update

06

Design Update

07

C C

Design Update 37

08

Design Update

09

Design Update

10

Design Update

11

Design Update

12

Design Update

13

change HW sequence disable VDDCI

tune CPU transient and

load line

Down Size for Cap

Cap shortage

󳱎 󰶂 󲵵󴦯

change to common part

4

39, 41,

Change PC315, PC603, PC811, PC826, PC843, PC849, PC1408, PC1426, PC1467, PC1004, PC1442, PC1481 from

42, 44,

1.0

680P_50V_K_X7R_0603 (SE025681K80) to 680P_ 50V_K_X7R_0402 (SE074681K80).

45

3

Page 1 of 1 for PWR

2

1.0

Change PQ310 from AON6366E (SB00001D800) to EMB04N03H (SB00001C500)

1.0

1.0 40, 39

1.0

Change 135W Adapter PQ311, PQ312 from AON7506 (SB000010A00) to AON7380 SB00001GM00)

38

Delete the PC323 10U_0805_25V (SE00000QK00)

Change PC101 from 100P_50V_J_NPO_0603 (SE024101J80) to 100P_50V_J_NPO_0402 (SE071101J80). Change PC102 from 1000P_50V_K_X7R_0603 (SE025102K80) to 1000P_50V_K_X7R_0402 (SE074102K80).

38, 39,

Change PR304, PR314, PR316, PR317, P R322, PR334, PR509, PR510, PR515, PR414, PR611, PR815 (0402)

40, 41,

AND PR327, PR312 (0603) 0ohm to r-short

42

Change PC1476 from 0.22 U_0402_10V6K (SE095224K00) to 0.47U_0402_6.3V6K (SE124474K80)

45

Add PR1466 for disable VDDCI when ues R535 GPU

Change PR809 from 2.49K_0402_1% (SD034249180) to 2.7K_0402_1% (SD034270180) Change PR826, PR841, PR856 from 2.26K_0603_1% (SD014226180) to 2.7K_0402_1% (SD034270180) Change PR806 from 53.6K_0402_1% (SD034536280) to 80.6K_0402_1% (SD034806280) 15W CPU Change PC807, PC830 from 330P_0402_50V8J (SE000006I80) to 270P_0402_50V7K (SE074271K80)

42 B

Change PR859 from 18.2K_0402_1%(SD034182280) to 43K_0402_1% (SD034430280) Change PR858 from 30.9K_0 402_1% (SD034309280) to 48.7K_0402_1% (SD034487280) Change PC828 to un pop

Change PC201, PC203 from 1000P_50V_K_X7R_0603 (SE025102K80) to 1000P_50V_K_X7R_0402 (SE074102K80) 2017/11/14 BDown Size for EMI Cap

Change PC507, PC506 from 10U_0805_6.3V6K (SE093106K80) to 10U_0603_6.3V6M (SE000005T80) Change PC416, PC417 from 680P_0603_50V8J(SE024681J80) to 680P_0402_50V7K (SE074681K80)

38, 45

Change PC1015, PC1476, PC9056, PC90 57, PC9058, PC9059, PC9060, PC9061, PC9062, PC9063, PC9064, PC9065, PC9066, PC9067, PC9068, PC9069, PC9070, PC9071 from 0.22U_0402_10V6K (SE095 224K00) to

44, 46

0.22U_0402_16V7K (SE00000R700)

Delete PC1538 330U_D1_2VY_R9M (SGA00009S00) Reserved 22U_0603_6.3V6M*4 (SE00000M000)

46

Change PC1505 from 220U_D2 SX_2VY_R9M (SGA20221D40) to 330U_D1_2VY_R9M (SGA00009S00) for 60W VGA

42 Change PC820, PC834 from 33U_25V_NC_6.3X4.5 (SF000007700) to 33U_25V_NC_6.3X4.5 (SF000007200)

1

2017/10/20

2017/10/20 B36Design Update Down Size for EMI Cap

2017/11/6

2017/11/14 B

B

B2017/ 11/1

B2017/ 11/14Change PC313, PC314, PC1428, PC1429 from 1U_0402_16V 6K (SE00000OU00) to 1U_0402_10V6K (SE00000QL10)

B2017/ 11/14

Design Update 2017/11/23Change PC820, PC834 from 33U_25V_NC_6.3X4.5 (SF000007200) to 33U_25V_NC_6.3X4.5 (SF000007700)42

14

Design Update 2017/11/23

15

B B

Design Update 2017/11/23

16

Design Update

17

Design Update

18

19

20

Design Update B2017/ 12/22add PL302/PL303 FBMA-L11-201209-800LMA50T (SM01000U600)

21

A A

Design Update for ACIN point

22

standby mode

swi t c h des i g n

󲔀󵙄

reserve

two cell low b att protect

change PQ307 and PQ313 source for source request

adaject BATGONE Threshold

adaject bootst ability 1.0

for EMI request

5

1.0

41 Change PR609 from 26.7K_0402_1% (SD034267280) to 24.3K_0402_1% (SD00000AT80)

PQ601 unpop

PR326 0 _0603_5% pop

1.0 38, 43

1.0

PQ309 LMUN5113T1G_SOT323-3 un pop PQ313 LTC015EUBFS8TL_UMT3F un pop PC9094 330U_D2_2V_Y un pop

pop PC204 0.1U 25V K X 5R (SE00000G880) pop PR213 750K +-1% 0402 (SD00000AL80) pop PR214 0 +-5% 0402 (SD028000080)

37

pop PR216 150K +-1% 0402 (SD034150380) pop PR212 0 +-5% 0402 (SD028000080)

38

change PQ307 & P Q313 form LTC015EUBFS8TL (SB00000RM00) to LMUN5236T1G (SB000011K00)

37 change PR203 from 6.49K_0402_1% (SD034649180) to 200K_0402_1% (SD034200380) 2017/11/23 BDesign Update

38 change PC309 from 0.22U_0603_25V7K (SE000005Z80)to 0.47U_0603_16V7K (SE026474K80) 2017/11/23 BDesign Update

1.0

38

1.0

change PR306 392K_0402_1% (SD034392380) to 499K_0402_1% (SD034499380)

38

change PR310 49.9K_0402_1% (SD034499280) to 66.5K_0402_1% (SD034665280)

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/12/25 2019/12/25

Compal Secret Data

Deciphered Date

BFor sourcer request

Btune VDDP in AMD spec

Buse SW solution in

2017/11/23pop PR212 0_0402_5% (SD028000080)

B

B2017/ 11/23

2017/12/22

Compal Electronics, Inc.

Title

Size

Custom

Date: Sheet o f

2

Date: Sheet o f

PWR_PIR1

Document Number Re v

DH5AV_JV_0V_LA-G021P

B

1.B

47 4 8Monday, December 25, 2017

1

5

3

Version Change List ( P. I. R. List )

4

3

2

1

Page 1

Item Issue DescriptionDate Request Owner

Solution Description Rev.Page#

1 07/31 0.11. Initial

2 09/30 EVT Final 0.1

D D

3 11/02 1. UW1 change PN(SA00008ELE0)

C C

11/074

2. US11,U74 change PN(SA00004ZA00)

3. L43,L44 change PN(SM01000K500)

4. US10 Pin2,3 swap Pin 10,11 (USB Charger modify)

5. RC6155 change location to CLRP1

6. RM23,RM24,RM25,RM26 add 0-ohm with T1PCIE@

7. All 1uF_0402 capacitor change to 1uF_0201 (SE00000UC00)

8. CS123 change PN(SE00000X200)

9. CC16 change to 1uF (SE00000UC00)

10.RO18 change to pop with PAR@

11.JDMIC1 change to 4pin connector (SP02000TI00)

12.R1562 pop, R1564 change to 20k (SD034200280)

13.R3_APU change PN(SA0000BBJ20)

14.US12 update value and part description

15.Q101,R101,R102,R103,R104 add with @ for UART0 debug

16.L2508,L2511,LS7 change to small size (SM070005U00)

17.PCB change PN(DAZ28Z00100)

18.SKU_ID change to AGPIO23, AGPIO40 will left N.C.

19.RC30,RC700,RC690,RC1676,RC1677,RC1672,RL1,RL13,RM20,RS10,RS127, RS147,RV807,RV1648,RV1632,R110,R4018 change to R-short

20.UV4 change PN(SA0000A4K00)

2. C796,C797 change to 3.9pF

3. Combine power 11/06

4. R756,R765,R769,R779,R781,R782,R783,R794 change to R-short

5. L2516,L2517 add with EMC@ R4031,R4032 remove

6. RS150,RS151 add with @ for debug

2. Combine power

1.0

1.01. CV450,CV451 change to 10pF

1.05 11/15 1. CC120 change to 0402_50V7K (SE074681K80)

11/206 1.01. Board ID set by project

B B

2. VRAM table add MICRON VRAM

3. Memory strap pin add MICRON config PV4G_M@

4. EVT@ change to @

5. R3APU@ seperate to R3APUDC@ and R3APUQC@

6. CS11,CS12,CS14,CS15 change to 0.1uF_0402_25V (SE00000G880)

7. TPM@,FP@,GS@,HDT@ remove from BOM PVT Final

7 12/18 1. C796,C797 change PN to SE07139AC80 (S CER CAP 3.9P 50V C NPO 0402)

12/228

A A

12/229 1.B

2. RW5,RW6,RW7,RW8 change to pop

3. RC6175,RC6174 change to @, RC693 change to DIS@, RC692 change to UMA@

4. VRAM config V4G_S7G@,V4G_H7G@,V4G_M7G@ add into table and strap-pin

5. RC6175 change to @, RC6174 change to @

6. US11 change to Power Switch (SA00006Y700, S IC G527ATP1U TSOT-23 6P PW SW)

7. RS154,RS155,RS156 add with TYPEC@; CS124 add with @

8. SWG1 change to @

9. QS4 change to @; RS148,RS149 change to TYPEC@

10.QC1 change to TYPEC@; RC616,RC617 change to NTYPEC@

11.RS112,QS6 change to @

12.Q2509,RC6158,RC6159 change to pop; R2622,R2623 change to @

1. RO19 remove from BOM.

2. DAZ28Z00102 add into NOTE LIST

1. PCB Location change to ZZZ1/ZZZ2/ZZZ3

2. D2016,D2017,D2018 change to EMC@

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2017/12/25 2019/12/25

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number R ev

Custom

Date : Sheet of

Compal Electronics, Inc.

HW PIR

DH5AV_JV_0V_LA-G021P

1

1.B

48 48Monday, December 25, 2017

1.B

5

3

Version Change List ( P. I. R. List )

4

3

2

1

Page 2

Item Issue DescriptionDate Request Owner

10 12/25 1.B1. PCB change location to ZZZ, and config to PCB1A@,PCB1B@

D D

2. BOM Loader without HUB@

3. APU PN update to R3 PN

4. Update Schematic to 1B

Solution Description Rev.Page#

C C

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

2017/12/25 2019/12/25

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number R ev

Custom

Date : Sheet of

Compal Electronics, Inc.

HW PIR

DH5AV_JV_0V_LA-G021P

48 48Monday, December 25, 2017

1

1.B

Compal LA-G021P Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual