Compal LA-G021P Schematics
A
1 1
B
C
D
E
Compal Confidential
2 2
DH5AV_JV_0V Schematics Document
AMD Raven Ridge Platform
AMD R17M-P1-50/R18M-M2-60/R18M-G1-90
3 3
LA-G021P REV:1.B
2017-12-25
4 4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Shared with ACER
Shared with ACER
A
B
Shared with ACER
2017/12/ 25 2019/12/ 25
2017/12/ 25 2019/12/ 25
2017/12/ 25 2019/12/ 25
C
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Custom
Custom
Custom
Date : Sheet o f
Date : Sheet o f
D
Date : Sheet o f
Compal Electronics, Inc.
COVER PAGE
COVER PAGE
COVER PAGE
DH5AV_JV_0V_LA-G021P
DH5AV_JV_0V_LA-G021P
DH5AV_JV_0V_LA-G021P
E
1.B
1.B
1.B
1 4 8Thursday, January 11, 20 18
1 4 8Thursday, January 11, 20 18
1 4 8Thursday, January 11, 20 18
A
Compal Confidential
Model Name : DH5AV_JV_0V
B
C
D
E
(Channel A)
1 1
GPU
GDDR5 x4pcs
128- bits
S4 Package
R535 : R18M-M2-60
RX540 : R17M-P1-50
RX565 : R18M-G1-90
USB2 .0
Port 1
eDP Conn.
PEG x8
page 15~23
Display Port
Port 0
page 24 page 25
HDMI Conn.
AMD
RAVEN RIDGE
Memory BUS(DDR4)
1.2V DDRIV
2400Mhz
USB2 .0
Port 0
Type-A (CHG)
Conn.
Port 4
2 2
USB3 .1
Port 0
260pin DDRIV SO-DIMM
Port 1
page 33
S/B
2.0 Conn.
page 13
Port 2
Type-C
Conn.
Port 2,3
AMD FP5 APU
BGA 1140-balls
PCI E
Port 0, 1, 2, 3
page 28
SSD
NGFF Conn.
Port 4
LAN+CR
RTL8411
page 26
USB2 .0
Port 3
Transformer
RJ45
page 26 page 26
3 3
Fan Control
page 32
Card Reader
Conn.
Port 5
WLAN/BT
NGFF Conn.
page 27
page 10
BIOS (8M)
page 31
Discrete TPM
page 6~12
HD Audio(AZ)
I2C
Port 1
Port 3
SATA III
G-Sensor
(Reserve)
PTP
page 28
page 31
HDD
Conn .
Port 0
page 28
Port 1
page 28
SSD
NGFF Conn.
SPI
LPC
ENE
KBC9022
page 30
PS2
page 31
Int.KBD
(Channel B)
page 14
260pin DDRIV SO-DIMM
Port 5
USB2.0 Hub
Touch
Screen
page 24
page 29
UAJ
on Sub/B
page 29
page 33
Port 1Port 2Port 3
S/B
2.0 Conn.
page 33
page 33
page 27
Port 4
Camera
page 24
Port 3
page 34page 33
WLAN/BT
Combo
Port 4
Finger
Print
page 31
Audio
ALC2 55/2 56
page 24
Int. DMIC
on Camera
Int. Speaker
Conn.
RTC CKT.
Power On/Off CKT.
4 4
DC/DC Interface CKT.
Power Circuit DC/DC
VRAM Config Table
page 11
page 32
page 35
page 36-47
page 23
A
Sub Board
LS-G021 USB2.0/B
LS-E911 Hall Sensor/B
page 33
page 31
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2017/12/25 2019/12/25
2017/12/25 2019/12/25
2017/12/25 2019/12/25
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number R ev
Size Document Number R ev
Size Document Number R ev
Custom
Custom
Custom
Date : Sheet of
Date : Sheet of
D
Date : Sheet of
Compal Electronics, Inc.
BLOCK DIAGRAMS
BLOCK DIAGRAMS
BLOCK DIAGRAMS
DH5AV_JV_0V_LA-G021P
DH5AV_JV_0V_LA-G021P
DH5AV_JV_0V_LA-G021P
E
2 48Monday, December 25, 2017
2 48Monday, December 25, 2017
2 48Monday, December 25, 2017
1.B
1.B
1.B
A
B
C
D
E
Voltage Rails
Power Plane
+19V_VIN
+19VB
+APU_CORE
1 1
2 2
+0.8VALW
+0.8VS
+1.8VALW
+1.8VS
+2.5V
+1.2V
+0.6VS
+3VALW
+3VS
+5VALW
+5VS
+RTC_APU
+3V_LAN 3.3V LAN IC power
+TP_VCC 3.3V Touch Pad power
+3VSDGPU
+1.8VSDGPU
+0.8VSDGPU
+VDDCI
+VGA_CORE
+FP_VCC ON
APU SMBus/I2C Address Table
Master
I2C Port 0
(+1.8VS)
I2C Port 1
(+1.8VS)
I2C Port 2
(+3VS)
SBMus Port 0
3 3
(+3VS)
I2C Port 3
(+3VALW)
SMBus Port 1
(+3VALW)
Description
Adapter power supply (19V)
AC or battery power r ail for power circuit.
Core voltage for APU
Voltage for On-die VGA of APU
0.8V always on power rail
0.8V switched power rail
1.8V always on power rail
1.8V switched power rail
2.5V power rail for APU and DDR
1.2V power rail for APU and DDR
0.6V switched power r ail for DDR terminator
3.3V always on power rail
3.3V switched power rail
5V always on power rail
5V switched power rail
RTC power
VGA power
VGA power
VGA power
VGA power
VGA power
3.3V Finger Print power
Device
G-Sensor
(Reserver)
JDIMM1
JDIMM2
PTP
(Synaptics)
PTP
(ELAN)
Address[7: 1]
0001 1000b
18h
0101 0000b
50h
0101 0001b
51h
0010 1100b
2Ch
0001 1111b
15h
Address [7:0]
Write
0011 0000b
30h
1010 0000b
A0h
1010 0010b
A2h
0101 1000b
58h
0011 1110b
3Eh
ON
ON
ON+APU_CORE_NB
ON
ON
ON
ON ON
ON
ON
ON
ON
ON ON
ON ON
ON
ON
ON
ON
ON
ON
0011 0001b
31h
1010 0001b
A1h
1010 0011b
A3h
0101 1001b
59h
0011 1111b
3Fh
ON ON
OFF
OFF OFF
ONON
OFF OFF
ON
OFF OFF
ONON
OFF OFF
ONON
OFF OFF
AC:ON
ON
DC:OFF
OFF OFF
OFF OFF
Read
EC SMBus Address Table
SMBus Port 1
(+3VALW)
4 4
SMBus Port 2
(+3VS)
Smart Battery
Charger IC
(BQ24735)
APU Temp.
(TSI)
GPU Temp.
CC-Logi c
A
0000 1011b
0Bh
0000 1001b
09h
0100 1100b
4Ch
0100 0001b
41h
1100 0000b
C0h
0001 0110b
16h
0001 0010b
12h
1001 1000b
98h
1000 0010b
82h
1000 0000b
80h
0001 0111b
17h
0001 0011b
13h
1001 1001b
99h
1000 0011b
83h
1000 0001b
81h
B
BOARD ID Table
S5S3S0
ONONON
OFF
OFF
OFF
OFF
OFF
OFF
ONONON
OFF
OFF
OFFOFF
OFFOFF
OFFOFF
OFFOFF
OFF
Board ID
0
PCB Revision
EVT
1 DH5 JV
2
3
DH5 AV
DH5 0V
BOM Structure Table
BTO ItemBOM Structure
@
EMC@ /@EM C@
45@
CON N@
JP@
RS@
TP@
TPM @
PCIE @/T1P CIE @
SAT A@
GS@
LDO@ /SWR @
PAR@ /TI@
CHG@ /NCH G@
255 @
256@ /256E MC@
UMA @
R3/R 5/R7A PU@
15W@ /25W@/35W@
T1@/ T2@
EJ@/ EA@/ VX@
DIS@ /T1D IS@
R53 5@
RX540@
RX565@
LEX A@
VRAM 7G@/VRAM6G@
HUB@ /NHU B@
FP@/ FPEM C@
DMIC 2@/DM IC4 @
HDT @
TYPEC@
TYPE CEMC @
NTYP EC@
Unpop
EMI/ESD Pop/Unpop
HDMI Royalty
Mechanical Connector
Jump
R-Shor t
Test Point
TPM Circuits
PCIE SSD/Type-1 APU PCIE SSD
SATA SSD
G-Sensor Circuits
RTL8411 LDO-Mode/Switching-Mode
SATA Redriver PARADE/TI solution
USB Charger/Non-Charger
Audio Codec AL255 Design
Audio Codec AL256 Design
UMA Config
APU PN Refer p.6
APU Watt Config
APU Type Config
EJ/EA/VX Project Config
VGA Circuits/Type1-APU VGA Circuits
GPU and VRAM Config Refer p.23
R18M-M2-60 GPU
R17M-P1-50 GPU
R18M-G1-90 GPU
LEXA Series VGA
VRAM7G and VRAM6G
USB20 HUB/Non-HUB
Finger Print
2 or 4 DMIC Design
HDT Circuits
TYPEC Circuits
TYPEC EMC Circuits
No TYPEC Circuits
@
ZZZ
DA8001E9010
PCB 28Z LA-G021P REV1 MB 2
PCB@
ZZZ
DAZ28Z00100
PCB DH5JV LA-G021P LS-G021P /E911P
PCB1A@
ZZZ
DAZ28Z00101
PCB DH5JV LA-G021P LS-G021P /E911P 1A
PCB1B@
ZZZ
DAZ28Z00102
PCB DH5JV LA-G021P LS-G021P /E911P 1B
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
Board ID / SKU ID Table for AD channel
POWER SEQUENCE
G-A
G-B
G-C
G-D
+RTC BATT
EC_O N
+5VA LW
3V_E N
+3VA LW
0.9_ 1.8V ALW_P WREN
+1.8 VALW /+0.9 VALW
SYSO N
+1.2 V/+2 .5V
SUSP #
+5VS /+3V S/+1. 8VS/ +0.6V S
0.9V S_PW R_EN #
+0.9 VS
VR_O N
+APU _COR E
+APU _COR E_SO C
VGA POWER SEQUENCE
PE_G PIO1 /VGA_ ON
+3VS DGPU
+1.8 VSDG PU
+0.8 VSDG PU
VGA_ ON_B
+VDD CI
+VGA _COR E
DGPU _PWR OK
+1.3 5VSD GPU
PE_G PIO0
Compal Secret Data
Compal Secret Data
2017/12/25 2019/12/25
2017/12/25 2019/12/25
2017/12/25 2019/12/25
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number R ev
Size Document Number R ev
Size Document Number R ev
Custom
Custom
Custom
Date : Sheet of
Date : Sheet of
Date : Sheet of
Compal Electronics, Inc.
NOTES LIST
NOTES LIST
NOTES LIST
DH5AV_JV_0V_LA-G021P
DH5AV_JV_0V_LA-G021P
DH5AV_JV_0V_LA-G021P
E
3 48Monday, December 25, 2017
3 48Monday, December 25, 2017
3 48Monday, December 25, 2017
1.B
1.B
1.B
5
PJP101
AC-IN
PU301
1802 0mA
+19V B
5243 mA
638m A
237m A
2311 mA
+19V _VIN
+17. 4V_BAT T
D D
PJP201
DC-IN
C C
PU801
PU501
PU601
PU401
+APU _CORE
+APU _CORE_ SOC
+1.2 V
9500 mA
+0.6 VS
1200 mA
5000 mA
+0.9 VALW
+3VL P
KB9022
B B
+5VA LW
1470 0mA3869 mA 7100 mA
PU401
To VGA
+VGA _CORE
+VDD CI/VDD _08
+1.3 5VSDGP U
A A
1500 mA
5
L11
3579 mA
169m A
474m A
+INV PWR_B +
Panel BackLight
1334 7mA
4
+3VA LW
4
2026 mA
7335 mA
PU602
+1.8 VALW
3713 mA
U2
To VGA10mA
+3VS
+5VS
4000 mA
2200 mA
304m A
U4
To VGA 1 013mA
U3
JRTC1
PU502
RM9
UL1
RL2
R463
U13
R212
U2606
R269
U8
RW2
RW1
U45
R110
U1
RS127
US12
U25
US10
JIO2
RO3
RF1/RF 7
JPA1
U73
UK6
R3986
3
+0.9 VS
+1.8 VS
+2.5 V
3
U102
+RTC _APU_ R
2
+3VS
+1.8 VS
+0.9 VS
+1.2 V
+3VA LW
+1.8 VALW
+1.8 VS
+0.9 VALW
+RTC _APU_ R
+2.5 V
+1.2 V
+0.6 VS
+3V_ LAN
+TP_ VCC
+3VS _WLAN
+3V_ HUB
+LCD VDD
+3VS _TPM
+3VA LW_TP M
+3VS _CAM
+5VS _BL
+3VA LW_CC
+USB 3_VCC C
+USB 3_VCC A
+5VS _HDD
+VCC _FAN1
+VCC _FAN2
+VDD A
+5VS _DISP
+FP_ VCC
+TS_ PWR
APU Power Rail
VDDCR_VDD @0.65-TBD
VDDCR_SOC @0.72-TBD
Group C, S0 domain
VDD_33 @0.25A
VDD_18 @2.0A
Group B, S0 domain
VDDP @4.0A
VDDIO_MEM_S3 @6.0A
VDD_33_S5 @0.25A
VDD_18_S5 @0.5A
VDDIO_AUDIO @0.2A
Group B, S3 domain
VDDP_S5 @1.0A
VDDBT_RTC_G @0.045mA
Group A, S5 domain
DDR4 SO-DIMM/MEM-DOWN
+2.5V
+1.2V
+0.6VS
SATA Redriver
SSD
LAN RTL8411
Touch Pad
WLAN
USB HUB
R18M-M2-60
R17M-P1-50
R18M-G1-90
Panel Logic
TPM
Camera
+19V B
3579 mA
KB Light
Type C
EJ179F
USB3.0
(Charger )
USB/B
HDD
FAN1/FAN 2
Audio
HDMI Logic
+19V B
169m A
+3VA LW 10mA
10mA
+1.8 VALW
1013 mA
+19V B
474m A
Finger Print
Touch Screen
Compal Secret Data
Compal Secret Data
2017/12/25 2019/12/25
2017/12/25 2019/12/25
2017/12/25 2019/12/25
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
+APU _CORE
7000 0mA
+APU _CORE_ SOC
1300 0mA
250m A
2000 mA
4000 mA
6000 mA
250m A
500m A
200m A
1000 mA
0.04 5mA
400m A
3500 mA
1200 mA
125m A
3500 mA
+3VS _SSD_N GFF
1400 mA
200m A
1500 mA
53.7 mA
1500 mA
50mA
1mA
200m A
500m A
250m A
3000 mA
2000 mA
2500 mA
2000 mA
2000 mA
1500 mA
1000 mA
100m A
100m A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECT RONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECT RONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECT RONICS, INC.
PU1401
PU1405
UV8
PU1001
6000 0mA
8000 mA
4000 mA
1013 mA
6000 mA
1
GPU Power Rail (R18M-G1-90)
+VGA _CORE
VDDC
@60A
PR1501
PR1502
+VDD CI
VDDCI
@8A
PR1503
+0.8 VSDGP U
+3VS DGPU
+1.8 VSDGP U
2000 mA
+1.3 5VSDGP U
4000 mA
+1.3 5VSDGP U
Title
Title
Title
Size
Size
Size
Custom
Custom
Custom
Date : Sheet of
Date : Sheet of
Date : Sheet of
VDD_08
@4A
VDD_GPIO 33
VDD_18
TSVDD
VMEMIO
@0.01A
@1A
@0.013 A
@2A
VRAM x4pcs
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
POWER MAP
POWER MAP
POWER MAP
Document Number Re v
Document Number Re v
Document Number Re v
DH5AV_JV_0V_LA-G021P
DH5AV_JV_0V_LA-G021P
DH5AV_JV_0V_LA-G021P
1
1.B
1.B
4 48Monday, December 25, 2017
4 48Monday, December 25, 2017
4 48Monday, December 25, 2017
1.B
5
Raven Ridge Platform Power Sequence
4
3
2
1
AC-IN G3 --> S0
+3VL P
ACIN
EC_O N
D D
+5VAL W
ON/OFF BTN#
3V_E N
+3VAL W
0.9_1. 8VALW_P WREN
+1.8VA LW
+0.9VA LW
PBTN_O UT#
EC_RSM RST#
SLP_S 5#
SLP_S 3#
SYSO N
+1.2 V
+2.5 V
SUSP #
C C
+5VS
+3VS
+1.8V S
+0.6V S
KBRST #
0.9VS_ PWR_EN #
+0.9V S
VR_O N
+APU_C ORE
+APU_C ORE_SO C
VGAT E
SYS_PW RGD_E C
APU_PW ROK
LPC_RS T#
APU_PC IE_RST #
B B
APU_RS T#
VGA Sequence
PE_GPI O1
+3VSDG PU
+1.8VS DGPU
+0.8VS DGPU +0.8VS DGPU(R18M- M2-60 )
VGA_ON _B
(R18M- G1-90 )
+VDDC I
+VGA_C ORE
DGPU_P WROK
+1.35V SDGPU
PE_GPI O0
PLT_RS T_VGA # PLT_RS T_VGA #
41.37ms
41.37ms
3.3ms, Tr = 339us
1.905us
99ms
99ms
218.1ms
880us, Tr = 349us
2.32ms, Tr = 409us
820us, Tr = 153us
202ms
4.601ms
117ms
101ms
100us
98.84us
120.6ms
720us, Tr = 68us
1.44ms, Tr = 601us
20.16ms
620us, Tr = 289us
580us, Tr = 303us
280us, Tr = 86us
20.08ms
20.28ms
400us, Tr = 55us 400us, Tr = 50us2.3ms, Tf = 748us 1.946ms, Tf = 612us
20.22ms
2.393ms, Tr = 145us
2.333ms, Tr = 160us
2.432ms
39.45ms
17.83ms
13.21ms
15.4ms
24.39ms
1.103s
1.013ms, Tr = 472us
5.895ms, Tr = 146us 5.695ms, Tr = 151us
5.041ms
6.273ms, Tr = 31us
6.273ms, Tr = 33us
6.2ms
733us, Tr = 153us 733us, Tr = 145us
164.3ms 117.3ms
S0 --> S3 S3 --> S0
1.31ms
60.28ms
11ms. Tf = 7.276ms
7.2ms, Tf = 4.062ms
7.2ms, Tf = 3.825ms
60.24ms
60.32ms
86.74ms
303us, Tf = 143us
303us, Tf = 120us
29.63ms
3.629ms
94.99us
431.6ms
431.6ms
11.6ms
266us, Tf = 152us
12.99ms, Tf = 1.904ms
32.6ms, Tf = 1.524ms
2.253ms, Tf = 992us
2.253ms, Tf = 1.17ms
6.026, Tf = 2.176ms
14.72ms
620us, Tr = 270us
620us, Tr = 293us
320us, Tr = 90us
200us, Tr = 9us200us, Tr = 9us 4.8ms, Tf = 2.1ms 626us, Tf = 97us
20.2ms
18.9ms
20.2ms
2.293ms, Tr = 143us
2.293ms, Tr = 158us
2.44ms
39.49ms
17.88ms
13.24ms
15.35ms
24.53ms
295ms
953us, Tr = 437us
2.693ms, Tr = 196us2.693ms, Tr = 210us
4.985ms
6.273ms, Tr = 30us
6.723ms, Tr = 30us
6.254ms
S0 --> S5
1.3ms
60.05ms
360us, Tf = 152us
4.54ms, Tf = 1.996ms
57.42ms
11ms, Tf = 7.574ms
6.6ms, Tf = 3.982ms
5.8ms, Tf = 3.407ms
57.36ms
57.44ms
80.02ms
303us, Tf = 133us
303us, Tf = 141us
29.63ms
3.623ms
93.02us
4.56s
4.56s
12.98ms
306us, Tf = 159us
12.91ms, Tf = 1.86ms
32.6ms, Tf = 1.424ms
2.253ms, Tf = 1.097ms
2.253ms, Tf = 1.175ms
6.026ms, Tf = 2.563ms
8.856s
9.13s
9.12s
9.12s
21ms, Tf = 14.21ms
Tf = 2.175ms
Tf = 7.438ms
+3VL P
ACIN
EC_O N
+5VAL W
ON/OFF BTN#
3V_E N
+3VAL W
0.9_1. 8VALW_P WREN
+1.8VA LW
+0.9VA LW
PBTN_O UT#
EC_RSM RST#
SLP_S 5#
SLP_S 3#
SYSO N
+1.2 V
+2.5 V
SUSP #
+5VS
+3VS
+1.8V S
+0.6V S
KBRST #
0.9VS_ PWR_EN #
+0.9V S
VR_O N
+APU_C ORE
+APU_C ORE_N B
VGAT E
SYS_PW RGD_E C
APU_PW ROK
LPC_RS T#
APU_PC IE_RST #
APU_RS T#
VGA Sequence
PE_GPI O1
+3VSDG PU
+1.8VS DGPU
VGA_ON _B
+VDDC I
+VGA_C ORE
DGPU_P WROK
+1.35V SDGPU
PE_GPI O0
(R18M- M2-60 )
(R18M- G1-90 )
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2
Compal Secret Data
Compal Secret Data
Compal Secret Data
2017/12/25 2019/12/25
2017/12/25 2019/12/25
2017/12/25 2019/12/25
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size
Size
Size
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
POWER SEQUENCE
POWER SEQUENCE
POWER SEQUENCE
Document Number Re v
Document Number Rev
Document Number Rev
DH5AV_JV_0V_LA-G021P
DH5AV_JV_0V_LA-G021P
DH5AV_JV_0V_LA-G021P
1
5 48Monday, December 25, 2017
5 48Monday, December 25, 2017
5 48Monday, December 25, 2017
1.B
1.B
1.B
5
4
3
2
1
Main Func = CPU
UC1B
D D
PEG_ARX _GTX_P0<15>
PEG_ARX _GTX_N0<15>
PEG_ARX _GTX_P1<15>
PEG PEG
C C
LAN+CR
WLAN
SSD SSD
B B
PEG_ARX _GTX_N1<15>
PEG_ARX _GTX_P2<15>
PEG_ARX _GTX_N2<15>
PEG_ARX _GTX_P3<15>
PEG_ARX _GTX_N3<15>
PEG_ARX _GTX_P4<15>
PEG_ARX _GTX_N4<15>
PEG_ARX _GTX_P5<15>
PEG_ARX _GTX_N5<15>
PEG_ARX _GTX_P6<15>
PEG_ARX _GTX_N6<15>
PEG_ARX _GTX_P7<15>
PEG_ARX _GTX_N7<15>
PCIE_ARX_ DTX_P0<28>
PCIE_ARX_ DTX_N0<28>
PCIE_ARX_ DTX_P1<28>
PCIE_ARX_ DTX_N1<28>
PCIE_ARX_ DTX_P2<28>
PCIE_ARX_ DTX_N2<28>
PCIE_ARX_ DTX_P3<28>
PCIE_ARX_ DTX_N3<28>
PCIE_ARX_ DTX_P4<26> PCIE_ATX_ C_DRX_P4 <26>
PCIE_ARX_ DTX_N4<26>
PCIE_ARX_ DTX_N5<27>
SATA_AR X_DTX_P0<28>
SATA_AR X_DTX_N0<28>
SATA_AR X_DTX_P1<28>
SATA_AR X_DTX_N1<28>
PEG_ARX _GTX_P0
PEG_ARX _GTX_N0
PEG_ARX _GTX_P1
PEG_ARX _GTX_N1
PEG_ARX _GTX_P2
PEG_ARX _GTX_N2
PEG_ARX _GTX_P3
PEG_ARX _GTX_N3
PEG_ARX _GTX_P4
PEG_ARX _GTX_N4
PEG_ARX _GTX_P5
PEG_ARX _GTX_N5
PEG_ARX _GTX_P6
PEG_ARX _GTX_N6
PEG_ARX _GTX_P7
PEG_ARX _GTX_N7
PCIE_ARX_ DTX_P0
PCIE_ARX_ DTX_N0
PCIE_ARX_ DTX_P1
PCIE_ARX_ DTX_N1
PCIE_ARX_ DTX_P2
PCIE_ARX_ DTX_N2
PCIE_ARX_ DTX_P3
PCIE_ARX_ DTX_N3
PCIE_ARX_ DTX_P4
PCIE_ARX_ DTX_N4
PCIE_ARX_ DTX_P5
PCIE_ARX_ DTX_N5
SATA_AR X_DTX_P0 SATA_AT X_DRX_P0
SATA_AR X_DTX_N0
SATA_AR X_DTX_P1
SATA_AR X_DTX_N1 SATA_ATX_ DRX_N1
P8
P_GFX_RXP0
P9
P_GFX_RXN0
N6
P_GFX_RXP1
N7
P_GFX_RXN1
M8
P_GFX_RXP2
M9
P_GFX_RXN2
L6
P_GFX_RXP3
L7
P_GFX_RXN3
K11
P_GFX_RXP4
J11
P_GFX_RXN4
H6
P_GFX_RXP5
H7
P_GFX_RXN5
G6
P_GFX_RXP6
F7
P_GFX_RXN6
G8
P_GFX_RXP7
F8
P_GFX_RXN7
N10
P_GPP_RXP0
N9
P_GPP_RXN0
L10
P_GPP_RXP1
L9
P_GPP_RXN1
L12
P_GPP_RXP2
M11
P_GPP_RXN2
P12
P_GPP_RXP3
P11
P_GPP_RXN3
V6
P_GPP_RXP4
V7
P_GPP_RXN4
T8
P_GPP_RXP5
T9
P_GPP_RXN5
R6
P_GPP_RXP6/SATA_RXP0
R7
P_GPP_RXN6/SATA_RXN0
R9
P_GPP_RXP7/SATA_RXP1
R10
P_GPP_RXN7/SATA_RXN1
@
PCIE
FP5 REV 0.90
PART 2 OF 13
FP5_BGA _1140P
P_GFX_TXP0
P_GFX_TXN0
P_GFX_TXP1
P_GFX_TXN1
P_GFX_TXP2
P_GFX_TXN2
P_GFX_TXP3
P_GFX_TXN3
P_GFX_TXP4
P_GFX_TXN4
P_GFX_TXP5
P_GFX_TXN5
P_GFX_TXP6
P_GFX_TXN6
P_GFX_TXP7
P_GFX_TXN7
P_GPP_TXP0
P_GPP_TXN0
P_GPP_TXP1
P_GPP_TXN1
P_GPP_TXP2
P_GPP_TXN2
P_GPP_TXP3
P_GPP_TXN3
P_GPP_TXP4
P_GPP_TXN4
P_GPP_TXP5
P_GPP_TXN5
P_GPP_TXP6/SATA_TXP0
P_GPP_TXN6/SATA_TXN0
P_GPP_TXP7/SATA_TXP1
P_GPP_TXN7/SATA_TXN1
N1
N3
M2
M4
L2
L4
L1
L3
K2
K4
J2
J4
H1
H3
H2
H4
N2
P3
P4
P2
R3
R1
T4
T2
W2
W4
W3
V2
V1
V3
U2
U4
PEG_ATX _GRX_P0
PEG_ATX _GRX_N0
PEG_ATX _GRX_P1
PEG_ATX _GRX_N1
PEG_ATX _GRX_P2
PEG_ATX _GRX_N2
PEG_ATX _GRX_P3
PEG_ATX _GRX_N3
PEG_ATX _GRX_P4
PEG_ATX _GRX_N4
PEG_ATX _GRX_P5
PEG_ATX _GRX_N5
PEG_ATX _GRX_P6
PEG_ATX _GRX_N6
PEG_ATX _GRX_P7
PEG_ATX _GRX_N7
PCIE_ATX_ DRX_P0
PCIE_ATX_ DRX_N0
PCIE_ATX_ DRX_P1
PCIE_ATX_ DRX_N1
PCIE_ATX_ DRX_P2
PCIE_ATX_ DRX_N2
PCIE_ATX_ DRX_P3
PCIE_ATX_ DRX_N3
PCIE_ATX_ DRX_P4
PCIE_ATX_ DRX_N4
PCIE_ATX_ DRX_P5
PCIE_ATX_ DRX_N5
SATA_AT X_DRX_N0
SATA_AT X_DRX_P1
1 2
CC1204 0.22U_04 02_16V7KPCIE@
1 2
CC1203 0.22U_04 02_16V7KPCIE@
1 2
CC1206 0.22U_04 02_16V7KPCIE@
1 2
CC1205 0.22U_04 02_16V7KPCIE@
1 2
CC1212 0.22U_04 02_16V7KT1PCIE@
1 2
CC1211 0.22U_04 02_16V7KT1PCIE@
1 2
CC1214 0.22U_04 02_16V7KT1PCIE@
1 2
CC1213 0.22U_04 02_16V7KT1PCIE@
1 2
CC1 .1U_0402_16V7K
1 2
CC2 .1U_0402_16V7K
1 2
CC3 .1U_0402_16V7K
1 2
CC4 .1U_0402_16V7K
PEG_ATX _GRX_P0 <15>
PEG_ATX _GRX_N0 <15>
PEG_ATX _GRX_P1 <15>
PEG_ATX _GRX_N1 <15>
PEG_ATX _GRX_P2 <15>
PEG_ATX _GRX_N2 <15>
PEG_ATX _GRX_P3 <15>
PEG_ATX _GRX_N3 <15>
PEG_ATX _GRX_P4 <15>
PEG_ATX _GRX_N4 <15>
PEG_ATX _GRX_P5 <15>
PEG_ATX _GRX_N5 <15>
PEG_ATX _GRX_P6 <15>
PEG_ATX _GRX_N6 <15>
PEG_ATX _GRX_P7 <15>
PEG_ATX _GRX_N7 <15>
PCIE_ATX_ C_DRX_P0 <28>
PCIE_ATX_ C_DRX_N0 <28>
PCIE_ATX_ C_DRX_P1 <28>
PCIE_ATX_ C_DRX_N1 <28>
PCIE_ATX_ C_DRX_P2 <28>
PCIE_ATX_ C_DRX_N2 <28>
PCIE_ATX_ C_DRX_P3 <28>
PCIE_ATX_ C_DRX_N3 <28>
PCIE_ATX_ C_DRX_N4 <26>
PCIE_ATX_ C_DRX_P5 <27>PCIE_ARX_ DTX_P5<27>
PCIE_ATX_ C_DRX_N5 <27>
SATA_AT X_DRX_P0 <28>
SATA_AT X_DRX_N0 <28>
SATA_AT X_DRX_P1 <28>
SATA_AT X_DRX_N1 <28>
SSDSSD
LAN+CR
WLAN
HDDHDD
APU PN Table
APU Platform
Rave n
A A
R3 PN R3 PN R3 PN R3 PN
UC1 R3APUDC@
S IC RAVEN3 YM2200C4T2OFB 2G BGA AB O!
SA0000BBJ30
5
UC1 R3APUQC@
S IC RAVEN3 YM2300C4T4MFB 2G BGA AB O!
SA0000BIT20
4
UC1 R5APU@
S IC RAVEN5 YM2500C4T4MFB 2G BGA AB O!
SA0000A8R30
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
UC1 R7APU@
S IC RAVEN7 YM2700C4T4MFB 2.2G BGA ABO!
SA0000ASA20
2017/12/ 25 2019/12/ 25
2017/12/ 25 2019/12/ 25
2017/12/ 25 2019/12/ 25
3
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Custom
Custom
Custom
Date : Sheet o f
Date : Sheet o f
2
Date : Sheet o f
Compal Electronics, Inc.
FP5_(1/7)_PEG/PCIE/SATA
FP5_(1/7)_PEG/PCIE/SATA
FP5_(1/7)_PEG/PCIE/SATA
DH5AV_JV_0V_LA-G021P
DH5AV_JV_0V_LA-G021P
DH5AV_JV_0V_LA-G021P
6 4 8Tuesday, December 26, 2 017
6 4 8Tuesday, December 26, 2 017
6 4 8Tuesday, December 26, 2 017
1
1.B
1.B
1.B
5
Main Func = CPU
4
3
2
1
UC1A
DDR_A_MA[13..0]<13>
D D
DDR_A_MA14_W E#< 13>
DDR_A_MA15_CAS#<13>
DDR_A_MA16_RAS#<13>
DDR_A_BA0<13>
DDR_A_BA1<13>
DDR_A_BG0<13>
DDR_A_BG1<13>
DDR_A_ACT#< 13>
DDR_A_DM[7..0]<13>
DDR_A_DQS0<13>
DDR_A_DQS0#<13>
DDR_A_DQS1<13>
DDR_A_DQS1#<13>
DDR_A_DQS2<13>
C C
B B
DDR_A_DQS2#<13>
DDR_A_DQS3<13>
DDR_A_DQS3#<13>
DDR_A_DQS4<13>
DDR_A_DQS4#<13>
DDR_A_DQS5<13>
DDR_A_DQS5#<13>
DDR_A_DQS6<13>
DDR_A_DQS6#<13>
DDR_A_DQS7<13>
DDR_A_DQS7#<13>
DDR_A_CLK0<13>
DDR_A_CLK0#<13>
DDR_A_CLK1<13>
DDR_A_CLK1#<13>
DDR_A_CS0#<13>
DDR_A_CS1#<13>
DDR_A_CKE0<13>
DDR_A_CKE1<13>
DDR_A_ODT0<13>
DDR_A_ODT1<13>
DDR_A_ALERT#<13>
DDR_A_EVENT#<13>
DDR_A_RST#<13>
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14_W E#
DDR_A_MA15_CAS#
DDR_A_MA16_RAS#
DDR_A_BA0
DDR_A_BA1
DDR_A_BG0
DDR_A_BG1
DDR_A_ACT#
DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7
DDR_A_DQS0
DDR_A_DQS0#
DDR_A_DQS1
DDR_A_DQS1#
DDR_A_DQS2
DDR_A_DQS2#
DDR_A_DQS3
DDR_A_DQS3#
DDR_A_DQS4
DDR_A_DQS4#
DDR_A_DQS5
DDR_A_DQS5#
DDR_A_DQS6
DDR_A_DQS6#
DDR_A_DQS7
DDR_A_DQS7#
DDR_A_CLK0
DDR_A_CLK0#
DDR_A_CLK1
DDR_A_CLK1#
DDR_A_CS0#
DDR_A_CS1#
DDR_A_CKE0
DDR_A_CKE1
DDR_A_ODT0
DDR_A_ODT1
DDR_A_ALERT#
DDR_A_EVENT#
DDR_A_RST#
AF25
AE23
AD27
AE21
AC24
AC26
AD21
AC27
AD22
AC21
AF22
AA24
AC23
AJ25
AG27
AG23
AG26
AF21
AF27
AA21
AA27
AA22
AL24
AN27
AW25
AT21
AM26
AM27
AN24
AN25
AU23
AT23
AV20
AW20
AD25
AD24
AE26
AE27
AG21
AJ27
AG24
AJ22
AA25
AE24
F21
G27
N24
N23
T27
F22
G22
H27
H26
N27
N26
R21
P21
V24
V23
Y23
Y26
Y24
MA_ADD0
MA_ADD1
MA_ADD2
MA_ADD3
MA_ADD4
MA_ADD5
MA_ADD6
MA_ADD7
MA_ADD8
MA_ADD9
MA_ADD10
MA_ADD11
MA_ADD12
MA_ADD13_BANK2
MA_WE_L_ADD14
MA_CAS_L_ADD15
MA_RAS_L_ADD16
MA_BANK0
MA_BANK1
MA_BG0
MA_BG1
MA_ACT_L
MA_DM0
MA_DM1
MA_DM2
MA_DM3
MA_DM4
MA_DM5
MA_DM6
MA_DM7
RSVD_36
MA_DQS_H0
MA_DQS_L0
MA_DQS_H1
MA_DQS_L1
MA_DQS_H2
MA_DQS_L2
MA_DQS_H3
MA_DQS_L3
MA_DQS_H4
MA_DQS_L4
MA_DQS_H5
MA_DQS_L5
MA_DQS_H6
MA_DQS_L6
MA_DQS_H7
MA_DQS_L7
RSVD_41
RSVD_40
MA_CLK_H0
MA_CLK_L0
MA_CLK_H1
MA_CLK_L1
MA_CS_L0
MA_CS_L1
MA_CKE0
MA_CKE1
MA_ODT0
MA_ODT1
MA_ALERT_L
MA_EVENT_L
MA_RESET_L
@
MEMORY A
FP5 REV 0.90
PART 1 OF 13
FP5_BGA_1140P
MA_DATA0
MA_DATA1
MA_DATA2
MA_DATA3
MA_DATA4
MA_DATA5
MA_DATA6
MA_DATA7
MA_DATA8
MA_DATA9
MA_DATA10
MA_DATA11
MA_DATA12
MA_DATA13
MA_DATA14
MA_DATA15
MA_DATA16
MA_DATA17
MA_DATA18
MA_DATA19
MA_DATA20
MA_DATA21
MA_DATA22
MA_DATA23
MA_DATA24
MA_DATA25
MA_DATA26
MA_DATA27
MA_DATA28
MA_DATA29
MA_DATA30
MA_DATA31
MA_DATA32
MA_DATA33
MA_DATA34
MA_DATA35
MA_DATA36
MA_DATA37
MA_DATA38
MA_DATA39
MA_DATA40
MA_DATA41
MA_DATA42
MA_DATA43
MA_DATA44
MA_DATA45
MA_DATA46
MA_DATA47
MA_DATA48
MA_DATA49
MA_DATA50
MA_DATA51
MA_DATA52
MA_DATA53
MA_DATA54
MA_DATA55
MA_DATA56
MA_DATA57
MA_DATA58
MA_DATA59
MA_DATA60
MA_DATA61
MA_DATA62
MA_DATA63
RSVD_34
RSVD_35
RSVD_51
RSVD_52
RSVD_27
RSVD_28
RSVD_43
RSVD_42
MA_PAROUT
J21
H21
F23
H23
G20
F20
J22
J23
G25
F26
L24
L26
L23
F25
K25
K27
M25
M27
P27
R24
L27
M24
P24
P25
M22
N21
T22
V21
L21
M20
R23
T21
AL27
AL25
AP26
AR27
AK26
AK24
AM24
AP27
AM23
AM21
AR25
AU27
AL22
AL21
AP24
AP23
AW26
AV25
AV22
AW22
AU26
AV27
AW23
AT22
AW21
AU21
AP21
AN20
AR22
AN22
AT20
AR20
T24
T25
W25
W27
R26
R27
V27
V26
AF24
DDR_A_DQ0
DDR_A_DQ1
DDR_A_DQ2
DDR_A_DQ3
DDR_A_DQ4
DDR_A_DQ5
DDR_A_DQ6
DDR_A_DQ7
DDR_A_DQ8
DDR_A_DQ9
DDR_A_DQ10
DDR_A_DQ11
DDR_A_DQ12
DDR_A_DQ13
DDR_A_DQ14
DDR_A_DQ15
DDR_A_DQ16
DDR_A_DQ17
DDR_A_DQ18
DDR_A_DQ19
DDR_A_DQ20
DDR_A_DQ21
DDR_A_DQ22
DDR_A_DQ23
DDR_A_DQ24
DDR_A_DQ25
DDR_A_DQ26
DDR_A_DQ27
DDR_A_DQ28
DDR_A_DQ29
DDR_A_DQ30
DDR_A_DQ31
DDR_A_DQ32
DDR_A_DQ33
DDR_A_DQ34
DDR_A_DQ35
DDR_A_DQ36
DDR_A_DQ37
DDR_A_DQ38
DDR_A_DQ39
DDR_A_DQ40
DDR_A_DQ41
DDR_A_DQ42
DDR_A_DQ43
DDR_A_DQ44
DDR_A_DQ45
DDR_A_DQ46
DDR_A_DQ47
DDR_A_DQ48
DDR_A_DQ49
DDR_A_DQ50
DDR_A_DQ51
DDR_A_DQ52
DDR_A_DQ53
DDR_A_DQ54
DDR_A_DQ55
DDR_A_DQ56
DDR_A_DQ57
DDR_A_DQ58
DDR_A_DQ59
DDR_A_DQ60
DDR_A_DQ61
DDR_A_DQ62
DDR_A_DQ63
DDR_A_PAR
DDR_A_DQ[63..0] <13>
DDR_A_PAR <13>
DDR_B_MA[13..0]<14>
DDR_B_MA14_ WE#<14>
DDR_B_MA15_ CAS#<14>
DDR_B_MA16_ RAS#<14>
DDR_B_BA0<14>
DDR_B_BA1<14>
DDR_B_BG0<14>
DDR_B_BG1<14>
DDR_B_ACT#<14>
DDR_B_DM[7 ..0]<14>
DDR_B_DQS0<14>
DDR_B_DQS0 #<14>
DDR_B_DQS1<14>
DDR_B_DQS1 #<14>
DDR_B_DQS2<14>
DDR_B_DQS2 #<14>
DDR_B_DQS3<14>
DDR_B_DQS3 #<14>
DDR_B_DQS4<14>
DDR_B_DQS4 #<14>
DDR_B_DQS5<14>
DDR_B_DQS5 #<14>
DDR_B_DQS6<14>
DDR_B_DQS6 #<14>
DDR_B_DQS7<14>
DDR_B_DQS7 #<14>
DDR_B_CLK 0<14>
DDR_B_CLK 0#<14>
DDR_B_CLK 1<14>
DDR_B_CLK 1#<14>
DDR_B_CS0 #<14>
DDR_B_CS1 #<14>
DDR_B_CKE0<14>
DDR_B_CKE1<14>
DDR_B_ODT 0<14>
DDR_B_ODT 1<14>
DDR_B_ALERT #<14>
DDR_B_EVENT #<14>
DDR_B_RST #<14>
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14_ WE#
DDR_B_MA15_ CAS#
DDR_B_MA16_ RAS#
DDR_B_BA0
DDR_B_BA1
DDR_B_BG0
DDR_B_BG1
DDR_B_ACT#
DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7
DDR_B_DQS0
DDR_B_DQS0 #
DDR_B_DQS1
DDR_B_DQS1 #
DDR_B_DQS2
DDR_B_DQS2 #
DDR_B_DQS3
DDR_B_DQS3 #
DDR_B_DQS4
DDR_B_DQS4 #
DDR_B_DQS5
DDR_B_DQS5 #
DDR_B_DQS6
DDR_B_DQS6 #
DDR_B_DQS7
DDR_B_DQS7 #
DDR_B_CLK 0
DDR_B_CLK 0#
DDR_B_CLK 1
DDR_B_CLK 1#
DDR_B_CS0 #
DDR_B_CS1 #
DDR_B_CKE0
DDR_B_CKE1
DDR_B_ODT 0
DDR_B_ODT 1
DDR_B_ALERT #
DDR_B_EVENT #
DDR_B_RST #
AG30
AC32
AC30
AB29
AB31
AA30
AA29
AA31
W29
AH29
W31
AL30
AK30
AK32
AJ30
AH31
AG32
AP30
AW31
BB26
BD22
AR29
AR31
AW30
AW29
BC25
BA25
BC22
BA22
AC31
AD30
AD29
AD31
AE30
AE32
AF29
AF31
AJ31
AM31
AJ29
AM29
AL31
AM32
AL29
AM30
W30
AG29
Y30
Y32
V31
V29
V30
C21
C25
E32
K30
N32
D22
B22
D25
B25
F29
F30
K31
K29
N31
N29
U29
T30
V32
U31
T31
MB_ADD0
MB_ADD1
MB_ADD2
MB_ADD3
MB_ADD4
MB_ADD5
MB_ADD6
MB_ADD7
MB_ADD8
MB_ADD9
MB_ADD10
MB_ADD11
MB_ADD12
MB_ADD13_BANK2
MB_WE_L_ADD14
MB_CAS_L_ADD15
MB_RAS_L_ADD16
MB_BANK0
MB_BANK1
MB_BG0
MB_BG1
MB_ACT_L
MB_DM0
MB_DM1
MB_DM2
MB_DM3
MB_DM4
MB_DM5
MB_DM6
MB_DM7
RSVD_21
MB_DQS_H0
MB_DQS_L0
MB_DQS_H1
MB_DQS_L1
MB_DQS_H2
MB_DQS_L2
MB_DQS_H3
MB_DQS_L3
MB_DQS_H4
MB_DQS_L4
MB_DQS_H5
MB_DQS_L5
MB_DQS_H6
MB_DQS_L6
MB_DQS_H7
MB_DQS_L7
RSVD_20
RSVD_18
MB_CLK_H0
MB_CLK_L0
MB_CLK_H1
MB_CLK_L1
MB_CLK_H2
MB_CLK_L2
MB_CLK_H3
MB_CLK_L3
MB0_CS_L0
MB0_CS_L1
MB1_CS_L0
MB1_CS_L1
MB0_CKE0
MB0_CKE1
MB1_CKE0
MB1_CKE1
MB0_ODT0
MB0_ODT1
MB1_ODT0
MB1_ODT1
MB_ALERT_L
MB_EVENT_L
MB_RESET_L
@
UC1I
MEMORY B
FP5 REV 0.90
PART 9 OF 13
FP5_BGA_1140P
MB_DATA0
MB_DATA1
MB_DATA2
MB_DATA3
MB_DATA4
MB_DATA5
MB_DATA6
MB_DATA7
MB_DATA8
MB_DATA9
MB_DATA10
MB_DATA11
MB_DATA12
MB_DATA13
MB_DATA14
MB_DATA15
MB_DATA16
MB_DATA17
MB_DATA18
MB_DATA19
MB_DATA20
MB_DATA21
MB_DATA22
MB_DATA23
MB_DATA24
MB_DATA25
MB_DATA26
MB_DATA27
MB_DATA28
MB_DATA29
MB_DATA30
MB_DATA31
MB_DATA32
MB_DATA33
MB_DATA34
MB_DATA35
MB_DATA36
MB_DATA37
MB_DATA38
MB_DATA39
MB_DATA40
MB_DATA41
MB_DATA42
MB_DATA43
MB_DATA44
MB_DATA45
MB_DATA46
MB_DATA47
MB_DATA48
MB_DATA49
MB_DATA50
MB_DATA51
MB_DATA52
MB_DATA53
MB_DATA54
MB_DATA55
MB_DATA56
MB_DATA57
MB_DATA58
MB_DATA59
MB_DATA60
MB_DATA61
MB_DATA62
MB_DATA63
RSVD_17
RSVD_19
RSVD_26
RSVD_29
RSVD_16
RSVD_15
RSVD_25
RSVD_24
MB_PAROUT
B21
D21
B23
D23
A20
C20
A22
C22
D24
A25
D27
C27
C23
B24
C26
B27
C30
E29
H29
H31
A28
D28
F31
G30
J29
J31
L29
L31
H30
H32
L30
L32
AP29
AP32
AT29
AU32
AN30
AP31
AR30
AT31
AU29
AV30
BB30
BA28
AU30
AU31
AY32
AY29
BA27
BC27
BA24
BC24
BD28
BB27
BB25
BD25
BC23
BB22
BC21
BD20
BB23
BA23
BB21
BA21
M31
N30
P31
R32
M30
M29
P30
P29
AG31
DDR_B_DQ0
DDR_B_DQ1
DDR_B_DQ2
DDR_B_DQ3
DDR_B_DQ4
DDR_B_DQ5
DDR_B_DQ6
DDR_B_DQ7
DDR_B_DQ8
DDR_B_DQ9
DDR_B_DQ10
DDR_B_DQ11
DDR_B_DQ12
DDR_B_DQ13
DDR_B_DQ14
DDR_B_DQ15
DDR_B_DQ16
DDR_B_DQ17
DDR_B_DQ18
DDR_B_DQ19
DDR_B_DQ20
DDR_B_DQ21
DDR_B_DQ22
DDR_B_DQ23
DDR_B_DQ24
DDR_B_DQ25
DDR_B_DQ26
DDR_B_DQ27
DDR_B_DQ28
DDR_B_DQ29
DDR_B_DQ30
DDR_B_DQ31
DDR_B_DQ32
DDR_B_DQ33
DDR_B_DQ34
DDR_B_DQ35
DDR_B_DQ36
DDR_B_DQ37
DDR_B_DQ38
DDR_B_DQ39
DDR_B_DQ40
DDR_B_DQ41
DDR_B_DQ42
DDR_B_DQ43
DDR_B_DQ44
DDR_B_DQ45
DDR_B_DQ46
DDR_B_DQ47
DDR_B_DQ48
DDR_B_DQ49
DDR_B_DQ50
DDR_B_DQ51
DDR_B_DQ52
DDR_B_DQ53
DDR_B_DQ54
DDR_B_DQ55
DDR_B_DQ56
DDR_B_DQ57
DDR_B_DQ58
DDR_B_DQ59
DDR_B_DQ60
DDR_B_DQ61
DDR_B_DQ62
DDR_B_DQ63
DDR_B_PAR
DDR_B_DQ[63 ..0] <14>
DDR_B_PAR <14>
EVENT# pull high
+1.2V
1 2
RC1 1K_0402_5%
+1.2V
1 2
A A
5
RC2 1K_0402_5%
DDR_B_EVENT #
DDR_A_EVENT#
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2017/12/25 2019/12/25
2017/12/25 2019/12/25
2017/12/25 2019/12/25
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number R ev
Size Document Number R ev
Size Document Number R ev
Custom
Custom
Custom
Date : Sheet of
Date : Sheet of
2
Date : Sheet of
Compal Electronics, Inc.
FP5_(2/7)_DDR4
FP5_(2/7)_DDR4
FP5_(2/7)_DDR4
DH5AV_JV_0V_LA-G021P
DH5AV_JV_0V_LA-G021P
DH5AV_JV_0V_LA-G021P
1
1.B
1.B
7 48Monday, December 25, 2017
7 48Monday, December 25, 2017
7 48Monday, December 25, 2017
1.B
A
Main Func = CPU
EC/THERM
+3VS
RPC25
APU_SID
18
APU_ALERT#
27
APU_SIC
36
APU_PROCHOT#
1 1
+3VS
2 2
+3VS
Close to APU
SVID
3 3
45
1K_0804_8P 4R_5%
1 2
RC16 1K_0402_5%@
1 2
RC17 1K_0402_5%@
EC_SMB_CK2<16 ,30,34>
EC_SMB_DA2<16 ,30,34>
1 2
RC664 1K_0402_5%
1
@EMC@
CC1202
.1U_0402_1 6V7K
2
+1.8VS
1
EMC@
CC5
33P_0402_5 0V8J
2
Reserve for debug
EC_SMB_CK2
EC_SMB_DA2
EC_SMB_CK2
EC_SMB_DA2
THERMTRIP#
RPC65
@
18
27
36
45
1K_0804_8P 4R_5%
2
G
6 1
D
RC616 0_0402_ 5%NTYPEC@
RC617 0_0402_ 5%NTYPEC@
1
EMC@
CC6
33P_0402_5 0V8J
2
APU_SVT_R
APU_SVC
APU_SVD
+3VS
5
G
QC1B
2N7002KDW _SOT363-6
SB00000EO00
3 4
S
D
TYPEC@
QC1A
2N7002KDW _SOT363-6
SB00000EO00
S
TYPEC@
1 2
1 2
APU_PROCHOT#
APU_RST#
APU_PWROK
APU_SIC
APU_SID
APU_SVT_R<42>
HDMI
EDP
+1.8VS
+1.8VS
APU_PWROK<42>
APU_SVC<42>
APU_SVD<42>
B
APU_DP0_P0<25>
APU_DP0_N0<25>
APU_DP0_P1<25>
APU_DP0_N1<25>
APU_DP0_P2<25>
APU_DP0_N2<25>
APU_DP0_P3<25>
APU_DP0_N3<25>
EDP_TXP0<24>
EDP_TXN0<24>
EDP_TXP1<24>
EDP_TXN1<24>
EDP_TXP2<24>
EDP_TXN2<24>
EDP_TXP3<24>
EDP_TXN3<24>
1 2
RC80 300_0402_ 5%
1 2
RC81 300_0402_ 5%
THERMTRIP#<30>
APU_PROCHOT#<30,38,42>
1 2
RC669 0_0402_5%
1 2
RC670 0_0402_5%
APU_DP0_P0
APU_DP0_N0
APU_DP0_P1
APU_DP0_N1
APU_DP0_P2
APU_DP0_N2
APU_DP0_P3
APU_DP0_N3
EDP_TXP0
EDP_TXN0
EDP_TXP1
EDP_TXN1
EDP_TXP2
EDP_TXN2
EDP_TXP3
EDP_TXN3
APU_TDI
APU_TDO
APU_TCK
APU_TMS
APU_TRST#
APU_DBREQ#
APU_RST#
APU_PWROK
APU_SIC
APU_SID
APU_ALERT#
THERMTRIP#
APU_PROCHOT#
APU_SVC_R
APU_SVD_R
APU_SVT_R
AW3
AW4
AW2
AP16
AU2
AU4
AU1
AU3
AV3
H14
L19
F16
H16
C8
D8
C7
C6
D6
D5
C1
J14
J15
J16
A8
B8
B6
E6
E1
F3
E4
F4
F2
DP0_TXP0
DP0_TXN0
DP0_TXP1
DP0_TXN1
DP0_TXP2
DP0_TXN2
DP0_TXP3
DP0_TXN3
DP1_TXP0
DP1_TXN0
DP1_TXP1
DP1_TXN1
DP1_TXP2
DP1_TXN2
DP1_TXP3
DP1_TXN3
TDI
TDO
TCK
TMS
TRST_L
DBREQ_L
RESET_L
PWROK
SIC
SID
ALERT_L
THERMTRIP_L
PROCHOT_L
SVC0
SVD0
SVT0
@
DISPLAY/SVI2/ JTAG/TE ST
DP3:
DP2:
DP1: eDP
DP0: HDMI
IO18S5
IO18
IO33
IO18
FP5_BGA_1140P
UC1C
FP5 REV 0.90
PART 3 OF 13
C
IO18
DP_DIGON
DP_VARY_BL
DP0_AUXP
DP0_AUXN
DP1_AUXP
DP1_AUXN
DP2_AUXP
DP2_AUXN
DP3_AUXP
DP3_AUXN
DP_STEREOSYNC
SMU_ZVDD
CORETYPE
VDDP_SENSE
VDDCR_SOC_SENSE
VDDCR_SENSE
VSS_SENSE_A
VSS_SENSE_B
DP_BLON
DP0_HPD
DP1_HPD
DP2_HPD
DP3_HPD
RSVD_4
RSVD_3
RSVD_2
TEST4
TEST5
TEST6
TEST14
TEST15
TEST16
TEST17
TEST31
TEST41
TEST470
TEST471
ENBKL_R
G15
ENVDD_R
F15
INVTPWM_R
L14
APU_DP0_CTR L_CLK
D9
APU_DP0_CTR L_DATA
B9
APU_DP0_HPD
C10
EDP_AUXP
G11
EDP_AUXN
F11
EDP_HPD
G13
J12
H12
K13
J10
H10
K8
DP_STEREOSYNC
K15
F14
F12
F10
APU_TEST4
AP14
APU_TEST5
AN14
F13
APU_TEST14
G18
APU_TEST15
H19
APU_TEST16
F18
APU_TEST17
F19
APU_TEST31
W24
APU_TEST41
AR11
APU_TEST470
AJ21
APU_TEST471
AK21
SMU_ZVDDP
V4
AW11
CORETYPE
APU_VDDP_SEN_H
AN11
APU_CORESOC_SE N_H
J19
APU_CORE_SEN_ H
K18
APU_VSS_SEN_L
J18
APU_VDDP_SEN_L
AM11
APU_DP0_CTR L_CLK <25>
APU_DP0_CTR L_DATA <25>
APU_DP0_HPD <25>
EDP_AUXP <24>
EDP_AUXN <24>
EDP_HPD <24>
TP@
T4949
TP@
T4948
TP@
T4942
TP@
T4941
TP@
T4940
TP@
T4939
1 2
RC1682 196_040 2_1%
1 2
RC1681 1K_0402_ 5%@
APU_VDDP_SEN_H <41>
APU_CORESOC_SE N_H <42>
APU_CORE_SEN_ H <4 2>
APU_VSS_SEN_L <42>
APU_VDDP_SEN_L <41>
D
HDMI
EDP
+0.9VS
+3VALW
Leakage prevent from power side
DISP
ENBKL_R
ENVDD_R
ENVDD_R
INVTPWM_R
ENBKL
ENVDD
INVTPWM
ENBKL_R
ENVDD_R
INVTPWM_R
+1.8VALW
5
UC66
1
P
NC
4
ENBKL
Y
2
A
G
NL17SZ07DFT 2G_SC70-5
3
SA00004BV00
+1.8VALW
5
UC64
1
P
NC
4
Y
2
A
G
NL17SZ07DFT 2G_SC70-5
3
SA00004BV00
@
1 2
RC690 0_0402_5%RS@
+1.8VALW
5
UC65
1
P
NC
4
Y
2
A
G
NL17SZ07DFT 2G_SC70-5
3
SA00004BV00
1 2
RC3 4.7K_0402_5 %
1 2
RC4 4.7K_0402_5 %@
1 2
RC5 4.7K_0402_5 %
1 2
RC6130 100K_040 2_5%
1 2
RC6131 100K_040 2_5%
1 2
RC6132 100K_040 2_5%@
ENVDD
INVTPWM
E
ENBKL <30>
ENVDD <24>
ENVDD
INVTPWM <24>
+3VS
HDT+
+1.8VALW
RPH3
10K_0804_8 P4R_5%
APU_TRST#_R
HDT_P11
HDT_P13
HDT_P15
1 2
RH21 3 3_0402_5%
0.01U_0402 _16V7K
4 4
1
2
CH2
1 8
2 7
3 6
4 5
A
JHDT1
@
1
1
2
3
3
4
5
5
6
7
7
8
9
9
10
11
11
12
13
13
14
15
15
16
17
17
18
19
19
20
SAMTE_ASP-13644 6-07-B
2
4
6
8
10
12
14
16
18
20
APU_TCK_R
APU_TMS_R
APU_TDI_R
APU_TDO_R
APU_PWROK_R
APU_RST#_R
APU_DBREQ#_R
B
1 2
RH27 0 _0402_5%HDT@
1 2
RH28 0 _0402_5%HDT@
1 2
RH29 0 _0402_5%HDT@
1 2
RH30 0 _0402_5%HDT@
1 2
RH31 0 _0402_5%HDT@
1 2
RH32 0 _0402_5%HDT@
1 2
RH33 3 3_0402_5%
Follow C5V08
APU_TCK
APU_TMS
APU_TDI
APU_TDO
APU_PWROK
APU_RST#
APU_DBREQ#
APU_TCK
APU_TMS
APU_TDI
APU_DBREQ#
APU_TRST#APU_TRST#
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
RPH1
1 8
2 7
3 6
4 5
1K_0804_8P 4R_5%
1 2
RH26 1K_0402_5%
+1.8VALW
Compal Secret Data
Compal Secret Data
2017/12/25 2019/12/25
2017/12/25 2019/12/25
2017/12/25 2019/12/25
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
TESTPOINT
DP_STEREOSYNC
Title
Title
Title
Size Document Number R ev
Size Document Number R ev
Size Document Number R ev
Custom
Custom
Custom
Date : Sheet of
Date : Sheet of
Date : Sheet of
+1.8VS
1 2
RC155 1K_0402_5%
1 2
RC154 1K_0402_5%@
+1.8VS
RPC30
APU_TEST14
APU_TEST15
APU_TEST16
APU_TEST17
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
(3/7)_DISP/MISC/HDT
(3/7)_DISP/MISC/HDT
(3/7)_DISP/MISC/HDT
DH5AV_JV_0V_LA-G021P
DH5AV_JV_0V_LA-G021P
DH5AV_JV_0V_LA-G021P
@
10K_0804_8 P4R_5%
E
18
27
36
45
1.B
1.B
8 48Monday, December 25, 2017
8 48Monday, December 25, 2017
8 48Monday, December 25, 2017
1.B
Main Func = CPU
A
B
C
D
E
UC1D
SW PU/PD
SW PU/PD
ACPI/AUDIO/I2C/GPI O/MISC
SW PU/PD
SW PU/PD
SW PU/PD
SW PU/PD
SW PU/PD
SW PU/PD
SW PU/PD
FP5 REV 0.90
PART 4 OF 13
FP5_BGA_1140P
1.8V_S5
1.8V_S5
SW PU/PD
EGPIO41/SFI_S5_EGPIO41
AGPIO39/SFI_S5_AGPIO39
I2C0_SCL/SFI0_I2C_SCL/EGPIO151
I2C0_SDA/SFI0_I2C_SDA/EGPIO152
I2C1_SCL/SFI1_I2C_SCL/EGPIO149
I2C1_SDA/SFI1_I2C_SDA/EGPIO150
I2C2_SCL/EGPIO113/SCL0
3.3V
I2C2_SDA/EGPIO114/SDA0
I2C3_SCL/AGPIO19/SCL1
3.3V_S5
I2C3_SDA/AGPIO20/SDA1
AGPIO4/SATAE_IFDET
SATA_ACT_L/AGPIO130
3.3VALW input
3.3VS input
3.3VS input
3.3VS Output
3.3VS input
3.3VS input
3.3VS input
3.3VS input
PSA_I2C_SCL
PSA_I2C_SDA
AGPIO5/DEVSLP0
AGPIO6/DEVSLP1
INTRUDER_ALERT
SPKR/AGPIO91
BLINK/AGPIO11
GENINT1_L/AGPIO89
GENINT2_L/AGPIO90
FANIN0/AGPIO84
FANOUT0/AGPIO85
AGPIO40
AGPIO69
AGPIO86
AW12
AU12
I2C_0_SCL
AR13
I2C_0_SDA
AT13
I2C_1_SCL
AN8
I2C_1_SDA
AN9
SMB_0_SCL
BC20
SMB_0_SDA
BA20
I2C_3_SCL
AM9
I2C_3_SDA
AM10
L16
M16
AT15
AGPIO3
AGPIO3
AW10
AGPIO4
AP9
AGPIO5
AU10
DEVSLP1
AV15
AU7
AGPIO9
AGPIO9
AU6
AGPIO40
AW13
G_INT#_APU
AW15
AU14
APU_SPKR
AU16
AV8
AGPIO11
AW16
TP_I2C_INT#_APU
BD15
AR18
AT18
I2C_1_SCL <28>
I2C_1_SDA <28>
SMB_0_SCL <13,14>
SMB_0_SDA <13,14>
I2C_3_SCL <31>
I2C_3_SDA <31>
DEVSLP1 <28>
G_INT#_APU <28>
APU_SPKR <29>
TP_I2C_INT#_APU < 31>
G-SENSOR
DDR4
Touch Pad
I2C_0_SCL
I2C_0_SDA
SMB_0_SCL
SMB_0_SDA
I2C_3_SCL
I2C_3_SDA
AGPIO8
DEVSLP1
1 2
RC6139 2.2K_0402_5%@
1 2
RC6140 2.2K_0402_5%@
1 2
RC6157 2.2K_0402_5%
1 2
RC6156 2.2K_0402_5%
1 2
RC6159 2.2K_0402_5%
1 2
RC6158 2.2K_0402_5%
RC6167 10K_0402_5%@
RC663 10K_0402_5%@
AGPIO4 0
DIS
H
1 2
CC7 150P_0402_50V8J
1 2
CC100 150P_0 402_50V8J@
1 2
1 1
RC29 33_0402_5%
1 2
RC704 33_0402_5%@
EC_RSMRST#<30>
PBTN_OUT#<30>
SYS_PWRGD_EC<30>
SLP_S3#<30>
SLP_S5#<30,38>
ACPI
+3VALW
1 2
RC6133 10K_0402_5%@
CRB use S0-rail
+3VALW
2 2
+3VS
12
12
RC6165
10K_0402_1%@
RC28
10K_0402_1%
2
CC8
0.22U_0402_16V7K
1
APU_PCIE_WAKE#
Reserve for MBDG/CRB
+1.8VALW
CC1210
10U_0603_6.3V6M
1 2
@
12
RC54
22K_0402_1%
SYS_PWRGD_EC EC_RSMRST#
1
CC16
1U_0201_6.3V6M
2
HDA_SDIN0<29>
AGPIO8<28>
APU_PCIE_RST#_RAPU_PCIE_RST#_C
APU_PCIE1_RST#_RAPU_PCIE1_RST#_C
EC_RSMRST#
PBTN_OUT#
SYS_PWRGD_EC
SYS_RST#
APU_PCIE_WAKE#
SLP_S3#
SLP_S5#
AGPIO10
AGPIO23
AGPIO12
HDA_BIT_CLK
HDA_SDIN0
HDA_SDIN1
HDA_SDIN2
HDA_RST#
HDA_SYNC
HDA_SDOUT
AGPIO7
AGPIO8
BD5
PCIE_RST0_L/EGPIO26
BB6
PCIE_RST1_L/EGPIO27
AT16
RSMRST_L
AR15
PWR_BTN_L/AGPIO0
AV6
PWR_GOOD
AP10
SYS_RESET_L/AGPIO1
AV11
WAKE_L/AGPIO2
AV13
SLP_S3_L
AT14
SLP_S5_L
AR8
S0A3_GPIO/AGPIO10
AT10
AC_PRES/AGPIO23
AN6
LLB_L/AGPIO12
AW8
EGPIO42
AR2
AZ_BITCLK/TDM_BCLK_MIC
AP7
AZ_SDIN0/CODEC_GPI
AP1
AZ_SDIN1/SW_DATA1B/TDM_BCLK_PLAYBACK
AP4
AZ_SDIN2/SW_DATA2/TDM_DATA_PLAYBACK
AP3
AZ_RST_L/SW_DATA1A/SW_DATA3/TDM_DATA_MIC
AR4
AZ_SYNC/TDM_FRM_MIC
AR3
AZ_SDOUT/TDM_FRM_PLAYBACK
AT2
SW_MCLK/TDM_BCLK_BT
AT4
SW_DATA0/TDM_DOUT_BT
AR6
AGPIO7/FCH_ACP_I2S_SDIN_BT
AP6
AGPIO8/FCH_ACP_I2S_LRCLK_BT
@
L
APU_PCIE_RST#_C APU_PCIE_RST#_U
APU_PCIE1_RST#_C
APU_PCIE_RST#_U APU_PCIE_RST#
APU_PCIE_RST#_U
3 3
RC6160
10K_0402_5% @
1 2
1 2
RC700 0_0402_5%RS@
1 2
RC701 0_0402_5%@
1 2
RC30 0_0402_5%RS@
+3VALW
1
IN1
2
IN2
@
CC14
0.1U_0201_10V6K
1 2
@
5
P
4
O
G
UC4
SA00000OH00
3
MC74VHC1G08DFT2G_SC70-5
APU_PCIE_RST#
APU_PCIE_RST# <15,26,27, 28>
GPIO Table
AGPIO40
AGPIO9
AGPIO12
AGPIO23
DIS@
RC693
10K_0402_5%
UMA@
RC692
10K_0402_5%
12
12
12
10K_0402_5%
12
10K_0402_5%
AGPIO9
Type1
Type2
T1@
RC6147
T2@
RC6148
+1.8VALW
+3VS
+3VALW
+3VS
12
10K_0402_5%
12
10K_0402_5%
AGPIO1 2
DMIC x4
DMIC x2
DMIC4@
RC6135
DMIC2@
RC6136
12
10K_0402_5%
12
10K_0402_5%
AGPIO2 3
RSV
RSVUMA
+3VALW
@
RC6175
@
RC6174
12
12
AGPIO1 0 AGPIO1 1
AGPIO7AGPI O5
35W@
15W@
L
H
15W
25W
35W
12
12
25W@
RC6137
10K_0402_5%
12
12
15W@
RC6138
10K_0402_5%
2017/12/25 2019/12/25
2017/12/25 2019/12/25
2017/12/25 2019/12/25
HDA
EMC@
RPC4
33_0804_8P4R_5%
HDA_RST#_R<29>
HDA_BIT_CLK_R<29>
HDA_SYNC_R<29>
HDA_SDOUT_R<29>
4 4
1 8
2 7
3 6
4 5
RPC5
1K_0804_8P4R_5%
1 2
RC695 10K_0402_5 %
1 2
RC696 10K_0402_5 %
1 2
RC703 10K_0402_5 %@
A
HDA_RST#
HDA_BIT_CLK
HDA_SYNC
HDA_SDOUT
18
27
36
45
HDA_SDIN1
HDA_SDIN2
HDA_SDIN0
Strap Pin
APU_SPI_ CLK_R S YS_RST#
USE 48MHZ CRYSTAL
H
CLOCK
(Default)
USE 100MHZ PCIE
L
CLOCK AS
REFERENCE CLOCK
APU_SPI_CLK_R<10>
B
NORMAL RESET MODE
(Default)
SHORT RESET MODE
+1.8VS +1.8VALW +3VALW
12
RC622
10K_0402_5%
10K_0402_5% @
APU_SPI_CLK_R
SYS_RST#
RC1703
2K_0402_5% @
12
12
RC951
RC47
10K_0402_5%
12
12
RC929
2K_0402_5% @
C
L
L
H L
RC6145
10K_0402_5%
RC6146
10K_0402_5%
RC6138
10K_0402_5%
AGPIO5
25W@
RC6146
35W@
10K_0402_5%
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
AGPIO3 AGPIO4
L L
RC6171
EA@
10K_0402_5%
RC6169
VX@
10K_0402_5%
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
10K_0402_5%
AGPIO3
AGPIO4AGPIO7
10K_0402_5%
RC6170
RC6171
EJ
EA
HL
VX
LH
+3VALW+3VALW
12
10K_0402_5%
12
10K_0402_5%
RC6168
RC6169
12
EA@
12
EJ@
VX@
EJ@
L
H L
H H
RC6172
RX540@
10K_0402_5%
RC6134
RX540@
10K_0402_5%
RC619
10K_0402_5%
RC6173
10K_0402_5%
10K_0402_5%
AGPIO10
AGPIO11
RX550@
RX550@
10K_0402_5%
Title
Title
Title
FP5_(4/7)_GPIO/HDA/STRAP
FP5_(4/7)_GPIO/HDA/STRAP
FP5_(4/7)_GPIO/HDA/STRAP
Size
Size
Size
Document Number Re v
Document Number Re v
Document Number Re v
Custom
Custom
Custom
Date : Sheet of
Date : Sheet of
Date : Sheet of
L
R535
L
RX540
H
RX550
RX565
+3VALW
12
12
RX565@
RX565@
RC6172
RC619
10K_0402_5%
12
12
R535@
R535@
RC6173
RC6134
10K_0402_5%
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
DH5AV_JV_0V_LA-G021P
DH5AV_JV_0V_LA-G021P
DH5AV_JV_0V_LA-G021P
E
9 48Monday, December 25, 2017
9 48Monday, December 25, 2017
9 48Monday, December 25, 2017
1.B
1.B
1.B
A
B
C
D
E
Main Func = CPU
UC1E
SW PU/PD
M.2 WLAN/BT
GBE LAN
M.2 WWAN
M.2 WLAN
PCIE X4 DT SLOT
M.2 PCIE SSD
EVAL GFX SLOT
USB_0_DP0
USB_0_DM0
USB_0_DP1
USB_0_DM1
USB_0_DP2
USB_0_DM2
USB_0_DP3
USB_0_DM3
USB_1_DP0
USB_1_DM0
USB_1_DP1
USB_1_DM1
USBC_I2C_SCL
USBC_I2C_SDA
USB_OC0_L/AGPIO16
USB_OC1_L/AGPIO17
USB_OC2_L/AGPIO18
USB_OC3_L/AGPIO24
AGPIO14/USB_OC4_L
AGPIO13/USB_OC5_L
CLK/LPC/EMMC/SD/SPI/eSPI/ UART
FP5 REV 0.90
PART 5 OF 13
Controller 0
Controller 1
SW PU/PD
FP5 REV 0.90
PART 10 OF 13
SW PU/PD
SW PU/PD
SW PU/PD
SW PU/PD
SW PU/PD
SW PU/PD
FP5_BGA_1140P
UC1J
USB
Port 0
Port 3
FP5_BGA_1140P
EGPIO70/SD_CLK
LPC_PD_L/SD_CMD/AGPIO21
LAD0/SD_DATA0/EGPIO104
LAD1/SD_DATA1/EGPIO105
LAD2/SD_DATA2/EGPIO106
LAD3/SD_DATA3/EGPIO107
LPCCLK0/EGPIO74
LPC_CLKRUN_L/AGPIO88
LPCCLK1/EGPIO75
SERIRQ/AGPIO87
LFRAME_L/EGPIO109
LPC_RST_L/SD_WP_L/AGPIO32
AGPIO68/SD_CD
LPC_PME_L/SD_PWR_CTRL/AGPIO22
SPI_ROM_REQ/EGPIO67
SPI_ROM_GNT/AGPIO76
ESPI_RESET_L/KBRST_L/AGPIO129
ESPI_ALERT_L/LDRQ0_L/EGPIO108
SPI_CLK/ESPI_CLK
SPI_DI/ESPI_DATA
SPI_WP_L/ESPI_DAT2
SPI_HOLD_L/ESPI_DAT3
SPI_CS1_L/EGPIO118
SPI_CS2_L/ESPI_CS_L/AGPIO30
SPI_CS3_L/AGPIO31
SPI_TPM_CS_L/AGPIO29
UART0_RXD/EGPIO136
UART0_TXD/EGPIO138
UART0_RTS_L/UART2_RXD/EGPIO137
UART0_CTS_L/UART2_TXD/EGPIO135
UART0_INTR/AGPIO139
EGPIO141/UART1_RXD
EGPIO143/UART1_TXD
EGPIO142/UART1_RTS_L/UART3_RXD
EGPIO140/UART1_CTS_L/UART3_TXD
AGPIO144/UART1_INTR
USBC0_A2/USB_0_TXP0/DP3_TXP2
USBC0_A3/USB_0_TXN0/DP3_TXN2
USBC0_B11/USB_0_RXP0/DP3_TXP3
USBC0_B10/USB_0_RXN0/DP3_TXN3
USBC0_B2/DP3_TXP1
USBC0_B3/DP3_TXN1
USBC0_A11/DP3_TXP0
USBC0_A10/DP3_TXN0
USB_0_TXP1
Port 1
USB_0_TXN1
USB_0_RXP1
USB_0_RXN1
USB_0_TXP2
Port 2
USB_0_TXN2
USB_0_RXP2
USB_0_RXN2
USBC1_A2/USB_0_TXP3/DP2_TXP2
USBC1_A3/USB_0_TXN3/DP2_TXN2
USBC1_B11/USB_0_RXP3/DP2_TXP3
USBC1_B10/USB_0_RXN3/DP2_TXN3
USBC1_B2/DP2_TXP1
USBC1_B3/DP2_TXN1
USBC1_A11/DP2_TXP0
USBC1_A10/DP2_TXN0
USB_1_TXP0
Port 4
USB_1_TXN0
USB_1_RXP0
USB_1_RXN0
SPI_DO
BD13
BB14
BB12
BC11
BB15
BC15
BA15
BC13
BB13
BC12
BA12
BD11
BA11
BA13
BC8
BB8
BB11
BC6
BB7
BA9
BB10
BA10
BC10
BC9
BA8
BA6
BD8
BA16
BB18
BC17
BA18
BD18
BC18
BA17
BC16
BB19
BB16
AD2
AD4
AC2
AC4
AF4
AF2
AE3
AE1
AG3
AG1
AJ9
AJ8
AG4
AG2
AG7
AG6
AA2
AA4
Y1
Y3
AC1
AC3
AB2
AB4
AH4
AH2
AK7
AK6
LPCPD#
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_CLK0
CLKRUN#
LPC_CLK1
SERIRQ
LPC_FRAME#
LPC_RST_A#
EC_SCI#
KBRST#
APU_SPI_CLK
APU_SPI_MISO
APU_SPI_MOSI
APU_SPI_WP#
APU_SPI_HOLD#
APU_SPI_CS#1
APU_SPI_TPMCS#
UART_0_ARXD_DTXD
UART_0_ATXD_DRXD
PE_GPIO1
DGPU_PWROK
PE_GPIO0
USB3_ATX_DRX_P0
USB3_ATX_DRX_N0
USB3_ARX_DTX_P0
USB3_ARX_DTX_N0
USB3_ATX_DRX_P2
USB3_ATX_DRX_N2
USB3_ARX_DTX_P2
USB3_ARX_DTX_N2
USB3_ATX_DRX_P3
USB3_ATX_DRX_N3
USB3_ARX_DTX_P3
USB3_ARX_DTX_N3
T103TP@
1 2
RC449 22_0402_5%
1 2
RC6163 22_0402_5%TPM@
EC_SCI# <30>
KBRST# <30>
RC74 10_0402_5%
1 2
EMC@
UART_0_ARXD_DTXD <27>
UART_0_ATXD_DRXD <27>
PE_GPIO1 <35>
DGPU_PWROK <44,45>
PE_GPIO0 <15>
USB3_ATX_DRX_P0 <33>
USB3_ATX_DRX_N0 <33>
USB3_ARX_DTX_P0 <33>
USB3_ARX_DTX_N0 <33>
USB3_ATX_DRX_P2 <34>
USB3_ATX_DRX_N2 <34>
USB3_ARX_DTX_P2 <34>
USB3_ARX_DTX_N2 <34>
USB3_ATX_DRX_P3 <34>
USB3_ATX_DRX_N3 <34>
USB3_ARX_DTX_P3 <34>
USB3_ARX_DTX_N3 <34>
LPC_AD0 <31>
LPC_AD1 <31>
LPC_AD2 <31>
LPC_AD3 <31>
LPC_CLK0_EC <30>
CLKRUN# <31>
LPC_CLK1_TPM <31>
SERIRQ <30,31>
LPC_FRAME# <30,31>
APU_SPI_CLK_R < 9>
8MB SPI ROM
Type-A MB CHG
Type-C MB
Type-C MB
APU_SPI_CS#1
APU_SPI_MISO
APU_SPI_WP#
LPC_RST_A#
EC_SCI#
PE_GPIO1
APU_SPI_CLK_R
RC602
33_0402_5%
1 2
RC6154 10K_0402_5%
RC6166 10K_0402_5%@
APU_SPI_MISO
RC1706 10K _0402_5%@
APU_SPI_WP#
APU_SPI_HOLD#
APU_SPI_CS#1
APU_SPI_TPMCS#
+1.8VALW
+1.8VS
UC7
1
CS#
2
3
4
VCC
DO(IO1)
HOLD#(IO3)
WP#(IO2)
CLK
GND
DI(IO0)
W25Q64FWSS IQ_SOIC_8P
SA00006ZV10
1 2
@EMC@
RC680
10_0402_5%
LPC_RST# <30,31>
1
CC615
150P_0402_50V8J
2
+3VALW
12
+3VS
12
1 2
1 2
RC640 10K_0402_5 %
1 2
RC642 10K_0402_5 %
1 2
RC639 10K_0402_5 %
1 2
RC646 10K_0402_5 %@
RC1672
0_0603_5%
1 2
RS@
RC1700
0_0603_5%
1 2
@
+SPI_VCC
8
APU_SPI_HOLD#
7
APU_SPI_CLK_R
6
APU_SPI_MOSI
5
@EMC@
1 2
CC636
10P_0402_50V8J
+SPI_VCC
+SPI_VCC
@
2
CC635
0.1U_0201_10V6K
1
T115 TP@
CLKREQ_PCIE#0
CLKREQ_PCIE#4
CLKREQ_PCIE#5
CLKREQ_PEG#6
CLK_PCIE_P0
CLK_PCIE_N0
CLK_PCIE_P4
CLK_PCIE_N4
CLK_PCIE_P5
CLK_PCIE_N5
CLK_PEG_P6
CLK_PEG_N6
48M_X1
48M_X2
RTCCLK
32K_X1
32K_X2
AV18
CLK_REQ0_L/SATA_IS0_L/SATA_ZP0_L/AGPIO92
AN19
CLK_REQ1_L/AGPIO115
AP19
CLK_REQ2_L/AGPIO116
AT19
CLK_REQ3_L/SATA_IS1_L/SATA_ZP1_L/EGPIO131
AU19
CLK_REQ4_L/OSCIN/EGPIO132
AW18
CLK_REQ5_L/EGPIO120
AW19
CLK_REQ6_L/EGPIO121
AK1
GPP_CLK0P
AK3
GPP_CLK0N
AM2
GPP_CLK1P
AM4
GPP_CLK1N
AM1
GPP_CLK2P
AM3
GPP_CLK2N
AL2
GPP_CLK3P
AL4
GPP_CLK3N
AN2
GPP_CLK4P
AN4
GPP_CLK4N
AN3
GPP_CLK5P
AP2
GPP_CLK5N
AJ2
GPP_CLK6P
AJ4
GPP_CLK6N
AJ3
48M_OSC
BB3
X48M_X1
BA5
X48M_X2
AF8
RSVD_76
AF9
RSVD_77
AW14
RTCCLK
AY1
X32K_X1
AY4
X32K_X2
@
+3VS
1 2
RC1695 10K_0402_5%
1 2
RC6149 10K_0402_5%
1 2
1 1
RC1696 10K_0402_5%
1 2
RC1697 10K_0402_5%
CLKREQ_PCIE#0
CLKREQ_PCIE#5
CLKREQ_PCIE#4
CLKREQ_PEG#6
CLKREQ_PCIE#0<28>
CLKREQ_PCIE#4<26>
CLKREQ_PCIE#5<27>
CLKREQ_PEG#6<16>
SSD
CLK_PCIE_P0<28>
CLK_PCIE_N0<28>
48MHz CRYSTAL
48M_X2
1
1
YC2
48MHZ_8PF_X3S048000D81H-W
SJ10000AF00
4
4
1
C797
3.9P_0402_50V8C
2
YC3
CC682
18P_0402_50V8J
48M_X1
LAN
WLAN
DGP U
32K_X1
12
32K_X2
1 2
RC939
1M_0402_5%
2
2
3
3
1
C796
3.9P_0402_50V8C
2
2 2
32.768KHz CRYSTAL
SJ100001K00
32.768KHZ_12.5PF_CM31532768DZFT
12
RC914
20M_0402_5%
1
CC686
18P_0402_50V8J
2
1
2
CLK_PCIE_P4<26>
CLK_PCIE_N4<26>
CLK_PCIE_P5<27>
CLK_PCIE_N5<27>
CLK_PEG_P6<15>
CLK_PEG_N6<15>
USB Function
+1.8VALW
1 2
3 3
RC94 4.7K_0402_5%
1 2
RC95 4.7K_0402_5%
+3VALW
1 2
RC905 100K_0402_5%@
1 2
RC6162 100K_0402_5%@
4 4
APU_USBC_SCL
APU_USBC_SDA
USB_OC0#
USB_OC2#
Type-A MB CHG
Type-A SUB
Type-C MB
WLAN/B T
CAMERA
USB Hub
USB20_P0<33>
USB20_N0<33>
USB20_P1<33>
USB20_N1<33>
USB20_P2<34>
USB20_N2<34>
USB20_P3<27>
USB20_N3<27>
USB20_P4<24>
USB20_N4<24>
USB20_P5<33>
USB20_N5<33>
USB_OC0#<33>
USB_OC2#<34>
USB20_P0
USB20_N0
USB20_P1
USB20_N1
USB20_P2
USB20_N2
USB20_P3
USB20_N3
USB20_P4
USB20_N4
USB20_P5
USB20_N5
APU_USBC_SCL
APU_USBC_SDA
USB_OC0#
USB_OC2#
AG10
AF12
AF11
AE10
AK10
AT12
AE7
AE6
AG9
AE9
AJ12
AJ11
AD9
AD8
AM6
AM7
AK9
AL9
AL8
AW7
@
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2017/12/25 2019/12/25
2017/12/25 2019/12/25
2017/12/25 2019/12/25
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
FP5_(5/7)_CLK/USB/SPI/LPC
FP5_(5/7)_CLK/USB/SPI/LPC
FP5_(5/7)_CLK/USB/SPI/LPC
Size
Size
Size
Document Number Re v
Document Number Re v
Document Number Re v
Custom
Custom
Custom
DH5AV_JV_0V_LA-G021P
DH5AV_JV_0V_LA-G021P
Date : Sheet of
Date : Sheet of
Date : Sheet of
DH5AV_JV_0V_LA-G021P
E
10 48Monday, December 25, 2017
10 48Monday, December 25, 2017
10 48Monday, December 25, 2017
1.B
1.B
1.B
A
B
C
D
E
Main Func = CPU
UC1F
Vo=1.5 V
UC8
SA000066U00
Vout
GND
680P_0402_ 50V7K
Vin
TDC: 53A
EDC: 70A
+RTCVCC
1
CC120
+APU_CORE
SCL/MBDG:
16*22uF (BU)
1*180pF (BU)
1
2
+APU_CORE Cap place at Power Side
+RTCBATT
+RTCBATT
DC1
1
CHN202UPT _SC70-3
3
2
RC6161
1K_0402_5%
1 2
+CHGRTC
JRTC1
1
1
2
2
3
GND
4
GND
ACES_50271-00 20N-001
CONN@
SP02000RO00
TDC: 10A
+APU_CORE_SOC
SCL/MBDG:
7*22uF (BU)
1*1uF (BU)
1 1
+APU_CORE_SOC Cap
place at Power Side
+1.2V +1.2V
CC1057 22U_0603_6.3V6M
CC1058 22U_0603_6.3V6M
CC1008 22U_0603_6.3V6M
CC1059 22U_0603_6.3V6M
1
1
1
1
2
2
2
2
2 2
CC1063 22U_0603_6.3V6M
CC1163 22U_0603_6.3V6M
CC1062 22U_0603_6.3V6M
CC1061 22U_0603_6.3V6M
CC1060 22U_0603_6.3V6M
1
1
1
1
1
2
2
2
2
2
All BU(on bottom side under SOC)
SCL/MBDG:
1 *22uF (BO)
+1.8VS +3VS +3VS_APU
RC1677
0_0402_5%
1 2
RS@
+VDDIO_AUDIO
CC1207 22U_0603_6.3V6M
1
2
1*1uF (BU)
CC1192 1U_0201_6.3V6M
1
2
1*180pF (BU)
SCL/MBDG:
9*22uF (BU)
2*1uF (BU)
4*0.22uF
1*180pF (BU)
CC1093 180P_0402_50V8J
CC1164 1U_0201_6.3V6M
CC1165 1U_0201_6.3V6M
1
1
1
2
2
2
CC1078 0.22U_0402_16V7K
CC1079 0.22U_0402_16V7K
CC1081 0.22U_0402_16V7K
CC1082 0.22U_0402_16V7K
1
1
1
1
2
2
2
2
2*180pF
CC1167 180P_0402_50V8J
CC1166 180P_0402_50V8J
1
1
2
2
ACROSS VDDIO AND VSS SPLIT
SCL/MBDG:
1 *22uF (BO)
RC1676
0_0402_5%
1 2
RS@
CC1137 22U_0603_6.3V6M
1
2
2*1uF (BO+BU)
CC1209 1U_0201_6.3V6M
CC1208 1U_0201_6.3V6M
1
1
2
2
+3VS_APU
+1.8VALW
BO B U BUB O BO
3 3
+1.8VS +1.8VALW + 3VALW
CC1189 22U_0603_6.3V6M
1
2
BO
CC1191 1U_0201_6.3V6M
CC1190 1U_0201_6.3V6M
1
2
BO B U
1
2
SCL/MBDG:
1 *22uF (BO)
2*1uF (BO+BU)
CC1186 22U_0603_6.3V6M
1
2
BO BUBO
SCL/MBDG:
1 *22uF (BO)
2*1uF (BO+BU)
CC1187 1U_0201_6.3V6M
CC1188 1U_0201_6.3V6M
1
1
2
2
CC1183 22U_0603_6.3V6M
1
2
SCL/MBDG:
1 *22uF (BO)
2*1uF (BO+BU)
CC1184 1U_0201_6.3V6M
CC1185 1U_0201_6.3V6M
1
1
2
2
BO BUBO
+0.9VALW
EDC: 13A
TDC: 6A
+1.2V
TDC :0.2A
+VDDIO_AUDIO
TDC :0.25A
TDC :2A
+1.8VS
TDC :0.5A
TDC :0.25A
+3VALW
TDC :1A
TDC :4A
+0.9VS
TDC :4.5uA
+RTC_APU_R
RTC OF APU
W18
W20
W28
W32
AA20
AA23
AA26
AA28
AA32
AC20
AC22
AC25
AC28
AD23
AD26
AD28
AD32
AE20
AE22
AE25
AE28
AF23
AF26
AF28
AF32
AG20
AG22
AG25
AG28
AJ20
AJ23
AJ26
AJ28
AJ32
AK28
AL28
AL32
AP12
AL18
AM17
AL20
AM19
AL19
AM18
AL17
AM16
AL14
AL15
AM14
AL13
AM12
AM13
AN12
AN13
AT11
M15
M18
M19
N16
N18
N20
P17
P19
R18
R20
T19
U18
U20
V19
Y19
T32
V28
Y22
Y25
Y28
VDDCR_SOC_1
VDDCR_SOC_2
VDDCR_SOC_3
VDDCR_SOC_4
VDDCR_SOC_5
VDDCR_SOC_6
VDDCR_SOC_7
VDDCR_SOC_8
VDDCR_SOC_9
VDDCR_SOC_10
VDDCR_SOC_11
VDDCR_SOC_12
VDDCR_SOC_13
VDDCR_SOC_14
VDDCR_SOC_15
VDDCR_SOC_16
VDDCR_SOC_17
VDDIO_MEM_S3_1
VDDIO_MEM_S3_2
VDDIO_MEM_S3_3
VDDIO_MEM_S3_4
VDDIO_MEM_S3_5
VDDIO_MEM_S3_6
VDDIO_MEM_S3_7
VDDIO_MEM_S3_8
VDDIO_MEM_S3_9
VDDIO_MEM_S3_10
VDDIO_MEM_S3_11
VDDIO_MEM_S3_12
VDDIO_MEM_S3_13
VDDIO_MEM_S3_14
VDDIO_MEM_S3_15
VDDIO_MEM_S3_16
VDDIO_MEM_S3_17
VDDIO_MEM_S3_18
VDDIO_MEM_S3_19
VDDIO_MEM_S3_20
VDDIO_MEM_S3_21
VDDIO_MEM_S3_22
VDDIO_MEM_S3_23
VDDIO_MEM_S3_24
VDDIO_MEM_S3_25
VDDIO_MEM_S3_26
VDDIO_MEM_S3_27
VDDIO_MEM_S3_28
VDDIO_MEM_S3_29
VDDIO_MEM_S3_30
VDDIO_MEM_S3_31
VDDIO_MEM_S3_32
VDDIO_MEM_S3_33
VDDIO_MEM_S3_34
VDDIO_MEM_S3_35
VDDIO_MEM_S3_36
VDDIO_MEM_S3_37
VDDIO_MEM_S3_38
VDDIO_MEM_S3_39
VDDIO_MEM_S3_40
VDDIO_AUDIO
VDD_33_1
VDD_33_2
VDD_18_1
VDD_18_2
VDD_18_S5_1
VDD_18_S5_2
VDD_33_S5_1
VDD_33_S5_2
VDDP_S5_1
VDDP_S5_2
VDDP_S5_3
VDDP_1
VDDP_2
VDDP_3
VDDP_4
VDDP_5
VDDBT_RTC_G
@
+RTC_APU_R
SCL/MBDG:
CC1178 180P_0402_50V8J
1
2
2 *22uF (BO)
8*1uF (BOx4+BUx4)
1*180pF (BU)
CC1179 22U_0603_6.3V6M
CC1180 1U_0201_6.3V6M
1
1
2
2
+0.9VS +0.9VALW
CC1168 22U_0603_6.3V6M
CC1170 1U_0201_6.3V6M
CC1171 1U_0201_6.3V6M
CC1169 22U_0603_6.3V6M
1
1
1
1
4 4
2
2
2
2
CC1173 1U_0201_6.3V6M
CC1172 1U_0201_6.3V6M
CC1176 1U_0201_6.3V6M
CC1177 1U_0201_6.3V6M
CC1174 1U_0201_6.3V6M
CC1175 1U_0201_6.3V6M
1
1
1
1
1
1
2
2
2
2
2
2
CC1181 1U_0201_6.3V6M
CC1182 1U_0201_6.3V6M
1
2
1
2
SCL/MBDG:
1 *22uF (BO)
3*1uF (BOx1+BUx2)
close to UC1
CC166
0.22U_0402 _16V7K
W=20 mils
1
1U_0201_6 .3V6M
2
CC923
1
2
0_0603_5%
CLRP1
POWER
FP5 REV 0.90
PART 6 OF 13
RC6164
1K_0402_5%
1 2
12
@
0.1U_0201_ 10V6K
FP5_BGA_1140P
+RTC_APU
CC119
G7
VDDCR_1
G10
VDDCR_2
G12
VDDCR_3
G14
VDDCR_4
H8
VDDCR_5
H11
VDDCR_6
H15
VDDCR_7
K7
VDDCR_8
K12
VDDCR_9
K14
VDDCR_10
L8
VDDCR_11
M7
VDDCR_12
M10
VDDCR_13
N14
VDDCR_14
P7
VDDCR_15
P10
VDDCR_16
P13
VDDCR_17
P15
VDDCR_18
R8
VDDCR_19
R14
VDDCR_20
R16
VDDCR_21
T7
VDDCR_22
T10
VDDCR_23
T13
VDDCR_24
T15
VDDCR_25
T17
VDDCR_26
U14
VDDCR_27
U16
VDDCR_28
V13
VDDCR_29
V15
VDDCR_30
V17
VDDCR_31
W7
VDDCR_32
W10
VDDCR_33
W14
VDDCR_34
W16
VDDCR_35
Y8
VDDCR_36
Y13
VDDCR_37
Y15
VDDCR_38
Y17
VDDCR_39
AA7
VDDCR_40
AA10
VDDCR_41
AA14
VDDCR_42
AA16
VDDCR_43
AA18
VDDCR_44
AB13
VDDCR_45
AB15
VDDCR_46
AB17
VDDCR_47
AB19
VDDCR_48
AC14
VDDCR_49
AC16
VDDCR_50
AC18
VDDCR_51
AD7
VDDCR_52
AD10
VDDCR_53
AD13
VDDCR_54
AD15
VDDCR_55
AD17
VDDCR_56
AD19
VDDCR_57
AE8
VDDCR_58
AE14
VDDCR_59
AE16
VDDCR_60
AE18
VDDCR_61
AF7
VDDCR_62
AF10
VDDCR_63
AF13
VDDCR_64
AF15
VDDCR_65
AF17
VDDCR_66
AF19
VDDCR_67
AG14
VDDCR_68
AG16
VDDCR_69
AG18
VDDCR_70
AH13
VDDCR_71
AH15
VDDCR_72
AH17
VDDCR_73
AH19
VDDCR_74
AJ7
VDDCR_75
AJ10
VDDCR_76
AJ14
VDDCR_77
AJ16
VDDCR_78
AJ18
VDDCR_79
AK13
VDDCR_80
AK15
VDDCR_81
AK17
VDDCR_82
AK19
VDDCR_83
AP2138N-1.5TR G1_SOT23-3
3
2
1
2
BOx 4
Need OPEN
BUx 4 BO BU
A
BUBO
BO
B
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
for Clear CMOS
Compal Secret Data
Compal Secret Data
2017/12/25 2019/12/25
2017/12/25 2019/12/25
2017/12/25 2019/12/25
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number R ev
Size Document Number R ev
Size Document Number R ev
Custom
Custom
Custom
Date : Sheet of
Date : Sheet of
D
Date : Sheet of
Compal Electronics, Inc.
(6/7)_PWR
(6/7)_PWR
(6/7)_PWR
DH5AV_JV_0V_LA-G021P
DH5AV_JV_0V_LA-G021P
DH5AV_JV_0V_LA-G021P
E
11 48Monday, December 25, 2017
11 48Monday, December 25, 2017
11 48Monday, December 25, 2017
1.B
1.B
1.B
5
Main Func = CPU
N12
VSS_316
A3
VSS_1
A5
VSS_2
A7
VSS_3
A10
VSS_4
A12
VSS_5
A14
VSS_6
A16
VSS_7
A19
G16
G19
G21
G23
G26
G28
G32
A21
A23
A26
A30
C32
D16
D18
D20
E10
E11
E12
E13
E14
E15
E16
E18
E19
E20
E21
E22
E23
E25
E26
E27
F28
H13
H18
H20
H22
H25
H28
K16
K19
K21
K22
K26
K28
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
C3
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
E7
VSS_18
E8
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
F5
VSS_36
VSS_37
G1
VSS_38
G5
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
H5
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
K1
VSS_54
K5
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
@
D D
C C
B B
UC1G
GND
FP5 REV 0.90
PART 7 OF 13
FP5_BGA _1140P
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
K32
L5
L13
L15
L18
L20
L25
L28
M1
M5
M12
M21
M23
M26
M28
M32
N4
N5
N8
N11
N13
N15
N17
N19
N22
N25
N28
P1
P5
P14
P16
P18
P20
P23
P26
P28
P32
R5
R11
R12
R13
R15
R17
R19
R22
R25
R28
R30
T1
T5
T14
T16
T18
T20
T23
T26
T28
U13
U15
U17
U19
V5
UC1M
A18
CAM0_CSI2_CLOCKP
C18
CAM0_CSI2_CLOCKN
A15
CAM0_CSI2_DATAP0
C15
CAM0_CSI2_DATAN0
B16
CAM0_CSI2_DATAP1
C16
CAM0_CSI2_DATAN1
C19
CAM0_CSI2_DATAP2
B18
CAM0_CSI2_DATAN2
B17
CAM0_CSI2_DATAP3
D17
CAM0_CSI2_DATAN3
D12
CAM1_CSI2_CLOCKP
B12
CAM1_CSI2_CLOCKN
C13
CAM1_CSI2_DATAP0
A13
C12
B11
J13
CAM1_CSI2_DATAN0
CAM1_CSI2_DATAP1
CAM1_CSI2_DATAN1
RSVD_6
A A
@
5
CAMERAS
FP5 REV 0.90
PART 13 OF 13
FP5_BGA _1140P
CAM0_CLK
CAM0_I2C_SCL
CAM0_I2C_SDA
CAM0_SHUTDOWN
CAM1_CLK
CAM1_I2C_SCL
CAM1_I2C_SDA
CAM1_SHUTDOWN
CAM_PRIV_LED
CAM_IR_ILLU
B15
D15
C14
B13
B10
A11
C11
D11
D13
D10
4
V8
V11
V12
V14
V16
V18
V20
V22
V25
W1
W5
W13
W15
W17
W19
W23
W26
Y5
Y11
Y12
Y14
Y16
Y18
Y20
AA1
AA5
AA13
AA15
AA17
AA19
AB14
AB16
AB18
AB20
AC5
AC8
AC11
AC12
AC13
AC15
AC17
AC19
AD1
AD5
AD14
AD16
AD18
AD20
AE5
AE11
AE12
AE13
AE15
AE17
AE19
AF1
AF5
AF14
AF16
AF18
AF20
AG5
@
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
3
UC1H
GND
FP5 REV 0.90
PART 8 OF 13
FP5_BGA _1140P
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
AG8
AG11
AG12
AG13
AG15
AG17
AG19
AH14
AH16
AH18
AH20
AJ1
AJ5
AJ13
AJ15
AJ17
AJ19
AK5
AK8
AK11
AK12
AK14
AK16
AK18
AK20
AK22
AK25
AL1
AL5
AL7
AL10
AL12
AL16
AL23
AL26
AM5
AM8
AM15
AM20
AM22
AM25
AM28
AN1
AN5
AN7
AN10
AN15
AN18
AN21
AN23
AN26
AN28
AN32
AP5
AP8
AP13
AP15
AP18
AP20
AP25
AP28
AR1
AR5
AR7
AR12
AR14
AR16
AR19
AR21
AR26
AR28
AR32
AU5
AU8
AU11
AU13
AU15
AU18
AU20
AU22
AU25
AU28
AV1
AV5
AV7
AV10
AV12
AV14
AV16
AV19
AV21
AV23
AV26
AV28
AV32
AW5
AW28
AY6
AY7
AY8
AY10
AY11
AY12
AY13
AY14
AY15
AY16
AY18
AY19
AY20
AY21
AY22
AY23
AY25
AY26
AY27
BB1
BB20
BB32
BD3
BD7
BD10
BD12
BD14
2
1
UC1K
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273
VSS_274
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
@
GND/RSVD
FP5 REV 0.90
PART 11 OF 13
FP5_BGA _1140P
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
RSVD_1
RSVD_5
RSVD_7
RSVD_8
RSVD_9
RSVD_10
RSVD_11
RSVD_12
RSVD_13
RSVD_22
RSVD_23
RSVD_30
RSVD_31
RSVD_37
RSVD_44
RSVD_49
RSVD_50
RSVD_57
RSVD_58
RSVD_59
RSVD_60
RSVD_69
RSVD_70
RSVD_71
RSVD_74
RSVD_75
RSVD_78
RSVD_79
RSVD_80
RSVD_81
RSVD_82
RSVD_83
RSVD_87
RSVD_88
RSVD_14
RSVD_84
RSVD_85
RSVD_86
BD16
BD19
BD21
BD23
BD26
BD30
B20
G3
J20
K3
K6
K20
M3
M6
M13
P6
P22
T3
T6
T29
W6
W21
W22
Y21
Y27
AA3
AA6
AC29
AD3
AD6
AF3
AF6
AF30
AJ6
AJ24
AK23
AK27
AL3
AN29
AN31
M14
AL6
AL11
AN16
UC1L
T11
RSVD_32
AC7
RSVD_66
Y9
RSVD_55
Y10
RSVD_56
W11
RSVD_47
W12
RSVD_48
V9
RSVD_38
V10
RSVD_39
AA12
RSVD_64
AC10
RSVD_68
@
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
RSVD
FP5 REV 0.90
PART 12 OF 13
FP5_BGA _1140P
2017/12/ 25 2019/12/ 25
2017/12/ 25 2019/12/ 25
2017/12/ 25 2019/12/ 25
3
AA9
RSVD_62
AA8
RSVD_61
AC6
RSVD_65
AD11
RSVD_72
AC9
RSVD_67
AA11
RSVD_63
T12
RSVD_33
AD12
RSVD_73
Y6
RSVD_53
Y7
RSVD_54
W8
RSVD_45
W9
RSVD_46
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Custom
Custom
Custom
Date : Sheet o f
Date : Sheet o f
2
Date : Sheet o f
Compal Electronics, Inc.
FP5_(7/7)_GND/RSVD/CSI
FP5_(7/7)_GND/RSVD/CSI
FP5_(7/7)_GND/RSVD/CSI
DH5AV_JV_0V_LA-G021P
DH5AV_JV_0V_LA-G021P
DH5AV_JV_0V_LA-G021P
12 48Monday, December 2 5, 2017
12 48Monday, December 2 5, 2017
12 48Monday, December 2 5, 2017
1
1.B
1.B
1.B
A
B
C
D
E
Reverse Type-4H
2-3A to 1 DIMMs/channel
DDR_A_CLK0<7>
DDR_A_CLK0#<7>
DDR_A_CLK1<7>
Address : A0
1 1
+3VS
12
RD5
0_0402_5%
@
12
RD8
0_0402_5%
RS@
Layout Note:
Place near JDIMM1
2 2
+1.2V
1U_0201_6.3V6M
1
2
+1.2V
10U_0603_6.3V6M
1
2
3 3
+1.2V
0.1U_0201_10V6K
2
1
12
12
12
CD2
CD10
CD61
RD7
0_0402_5%
RD6
0_0402_5%
@
@
DDR_A_SA2
DDR_A_SA1
DDR_A_SA0
12
RD10
0_0402_5%
RS@
RD9
0_0402_5%
RS@
Note:
Check voltage tolerance of
VREF_DQ at the DIMM socket
CRB use 0.1uF x12 (6 pop,6 unpop),180pF x1,100uF x2
1U_0201_6.3V6M
1U_0201_6.3V6M
CD3
1
1
2
2
10U_0603_6.3V6M
10U_0603_6.3V6M
CD11
1
1
2
2
0.1U_0201_10V6K
0.1U_0201_10V6K
CD62
2
2
1
1
1U_0201_6.3V6M
1U_0201_6.3V6M
CD4
1
2
10U_0603_6.3V6M
CD12
1
2
0.1U_0201_10V6K
CD63
2
1
1U_0201_6.3V6M
CD6
CD5
CD13
CD64
CD7
1
1
2
2
10U_0603_6.3V6M
10U_0603_6.3V6M
CD14
CD15
1
1
2
2
180P_0402_50V8J
2
1
CD1
@EMC@
.1U_0402_1 6V7K
DDR4 support Even Parity check in DRAMs.
DDR_A_RST#
12
Follow MA51
1
@
+
CD18
330U_D2_2 V_Y
2
SGA00009S00
330U 2V H1.9
9mohm POLY
CD65
DDR_A_CLK1#<7>
DDR_A_CKE0<7>
DDR_A_CKE1<7>
DDR_A_CS0#<7>
DDR_A_CS1#<7>
DDR_A_ODT0<7>
DDR_A_ODT1<7>
DDR_A_BG0<7>
DDR_A_BG1<7>
DDR_A_BA0<7>
DDR_A_BA1<7>
DDR_A_MA[13..0]<7>
DDR_A_MA14_W E#<7>
DDR_A_MA15_CAS#<7>
DDR_A_MA16_RAS#<7>
DDR_A_ACT#<7>
DDR_A_PAR<7>
DDR_A_ALERT#<7>
DDR_A_EVENT#<7>
DDR_A_RST#<7 >
SMB_0_SDA< 9,14>
SMB_0_SCL<9,14>
DDR_A_DM[7..0]<7>
DDR_A_CLK0
DDR_A_CLK0#
DDR_A_CLK1
DDR_A_CLK1#
DDR_A_CKE0
DDR_A_CKE1
DDR_A_CS0#
DDR_A_CS1#
DDR_A_ODT0
DDR_A_ODT1
DDR_A_BG0
DDR_A_BG1
DDR_A_BA0
DDR_A_BA1
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14_W E#
DDR_A_MA15_CAS#
DDR_A_MA16_RAS#
DDR_A_ACT#
DDR_A_PAR
DDR_A_ALERT#
DDR_A_EVENT#
DDR_A_RST#
SMB_0_SDA
SMB_0_SCL
DDR_A_SA2
DDR_A_SA1
DDR_A_SA0
DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7
JDIMM1A
REVERSE
137
CK0(T)
139
CK0#(C)
138
CK1(T)
140
CK1#(C)
109
CKE0
110
CKE1
149
S0#
157
S1#
162
S2#/C0
165
S3#/C1
155
ODT0
161
ODT1
115
BG0
113
BG1
150
BA0
145
BA1
144
A0
133
A1
132
A2
131
A3
128
A4
126
A5
127
A6
122
A7
125
A8
121
A9
146
A10_AP
120
A11
119
A12
158
A13
151
A14_WE#
156
A15_CAS#
152
A16_RAS#
114
ACT#
143
PARITY
116
ALERT#
134
EVENT#
108
RESET#
254
SDA
253
SCL
166
SA2
260
SA1
256
SA0
92
CB0_NC
91
CB1_NC
101
CB2_NC
105
CB3_NC
88
CB4_NC
87
CB5_NC
100
CB6_NC
104
CB7_NC
97
DQS8(T)
95
DQS8#(C)
12
DM0#/DBI0#
33
DM1#/DBI1#
54
DM2#/DBI2#
75
DM3#/DBI3#
178
DM4#/DBI4#
199
DM5#/DBI5#
220
DM6#/DBI6#
241
DM7#/DBI7#
96
DM8#/DBI8#
LOTES_ADDR02 06-P001A
CONN@
DQS0(T)
DQS0#(C)
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS1(T)
DQS1#(C)
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS2(T)
DQS2#(C)
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQS3(T)
DQS3#(C)
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS4(T)
DQS4#(C)
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQS5(T)
DQS5#(C)
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQS6(T)
DQS6#(C)
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQS7(T)
DQS7#(C)
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DDR_A_DQ1
7
DDR_A_DQ2
20
DDR_A_DQ3
21
DDR_A_DQ4
4
DDR_A_DQ5
3
DDR_A_DQ6
16
DDR_A_DQ7
17
DDR_A_DQS0
13
DDR_A_DQS0#
11
DDR_A_DQ8
28
DDR_A_DQ9
29
DDR_A_DQ10
41
DDR_A_DQ11
42
DDR_A_DQ12
24
DDR_A_DQ13
25
DDR_A_DQ14
38
DDR_A_DQ15
37
DDR_A_DQS1
34
DDR_A_DQS1#
32
DDR_A_DQ16
50
DDR_A_DQ17
49
DDR_A_DQ18
62
DDR_A_DQ19
63
DDR_A_DQ20
46
DDR_A_DQ21
45
DDR_A_DQ22
58
DDR_A_DQ23
59
DDR_A_DQS2
55
DDR_A_DQS2#
53
DDR_A_DQ24
70
DDR_A_DQ25
71
DDR_A_DQ26
83
DDR_A_DQ27
84
DDR_A_DQ28
66
DDR_A_DQ29
67
DDR_A_DQ30
79
DDR_A_DQ31
80
DDR_A_DQS3
76
DDR_A_DQS3#
74
DDR_A_DQ32
174
DDR_A_DQ33
173
DDR_A_DQ34
187
DDR_A_DQ35
186
DDR_A_DQ36
170
DDR_A_DQ37
169
DDR_A_DQ38
183
DDR_A_DQ39
182
DDR_A_DQS4
179
DDR_A_DQS4#
177
DDR_A_DQ40
195
DDR_A_DQ41
194
DDR_A_DQ42
207
DDR_A_DQ43
208
DDR_A_DQ44
191
DDR_A_DQ45
190
DDR_A_DQ46
203
DDR_A_DQ47
204
DDR_A_DQS5
200
DDR_A_DQS5#
198
DDR_A_DQ48
216
DDR_A_DQ49
215
DDR_A_DQ50
228
DDR_A_DQ51
229
DDR_A_DQ52
211
DDR_A_DQ53
212
DDR_A_DQ54
224
DDR_A_DQ55
225
DDR_A_DQS6
221
DDR_A_DQS6#
219
DDR_A_DQ56
237
DDR_A_DQ57
236
DDR_A_DQ58
249
DDR_A_DQ59
250
DDR_A_DQ60
232
DDR_A_DQ61
233
DDR_A_DQ62
245
DDR_A_DQ63
246
DDR_A_DQS7
242
DDR_A_DQS7#
240
DDR_A_DQ0
8
DDR_A_DQ[7..0] < 7>
DDR_A_DQS0 <7>
DDR_A_DQS0# <7>
DDR_A_DQ[15..8] <7>
DDR_A_DQS1 <7>
DDR_A_DQS1# <7>
DDR_A_DQ[23..16 ] <7>
DDR_A_DQS2 <7>
DDR_A_DQS2# <7>
DDR_A_DQ[31..24 ] <7>
DDR_A_DQS3 <7>
DDR_A_DQS3# <7>
DDR_A_DQ[39..32 ] <7>
DDR_A_DQS4 <7>
DDR_A_DQS4# <7>
DDR_A_DQ[47..40 ] <7>
DDR_A_DQS5 <7>
DDR_A_DQS5# <7>
DDR_A_DQ[55..48 ] <7>
DDR_A_DQS6 <7>
DDR_A_DQS6# <7>
DDR_A_DQ[63..56 ] <7>
DDR_A_DQS7 <7>
DDR_A_DQS7# <7>
Follow CRB design
+1.2V
RD3
1K_0402_1%
RD4
1K_0402_1%
1 2
CD20 4.7U_0402_6.3V6M
1 2
15mil
CD22 0.1U_0201_10V6K
1
2
+VREFA_CA
CD21 0.1U_0201_10V6K
CD19 1000P_0402_50V7K
2
2
1
1
1
2
Place near to SO-DIMM connector.
+1.2V +1.2V
JDIMM1B
REVERSE
111
VDD1
112
117
118
123
124
129
130
+3VS
135
136
255
164
1
2
5
6
9
10
14
15
18
19
22
23
26
27
30
31
35
36
39
40
43
44
47
48
51
52
56
57
60
61
64
65
68
69
72
73
77
78
81
82
85
86
89
90
93
94
98
262
Layout Note:
Place near JDIMM1.258
VDD11
VDD2
VDD12
VDD3
VDD13
VDD4
VDD14
VDD5
VDD15
VDD6
VDD16
VDD7
VDD17
VDD8
VDD18
VDD9
VDD19
VDD10
VDDSPD
VTT
VREFCA
VPP1
VPP2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
GND
LOTES_ADDR02 06-P001A
CONN@
GND
141
142
147
148
153
154
159
160
+0.6VS
163
258
257
259
99
102
103
106
107
167
168
171
172
175
176
180
181
184
185
188
189
192
193
196
197
201
202
205
206
209
210
213
214
217
218
222
223
226
227
230
231
234
235
238
239
243
244
247
248
251
252
261
+2.5V
CD31 1U_0201_6.3V6M
1
2
CRB use 1uF x1
CRB use 4.7uF x1,0.1uF x1
Layout Note:
Place near JDIMM1.257,259
CRB use 0.1uF x2,180pF x1
4 4
10U_0603_6.3V6M
1
2
+2.5V
1U_0201_6.3V6M
10U_0603_6.3V6M
CD23
CD25
CD24
1
1
2
2
A
Layout Note:
Place near JDIMM1.255
CRB use 1uF x1
+3VS
1U_0201_6.3V6M
CD26
1
2
1
2
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2017/12/25 2019/12/25
2017/12/25 2019/12/25
2017/12/25 2019/12/25
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Title
Title
Title
Size Document Number R ev
Size Document Number R ev
Size Document Number R ev
Custom
Custom
Custom
DH5AV_JV_0V_LA-G021P
DH5AV_JV_0V_LA-G021P
DH5AV_JV_0V_LA-G021P
Date : Sheet of
Date : Sheet of
D
Date : Sheet of
+0.6VS
10U_0603_6.3V6M
10U_0603_6.3V6M
CD27
CD28
1
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
DDR4_SO-DIMM
DDR4_SO-DIMM
DDR4_SO-DIMM
1U_0201_6.3V6M
1U_0201_6.3V6M
CD30
CD29
1
1
2
2
13 48Monday, December 25, 2017
13 48Monday, December 25, 2017
E
13 48Monday, December 25, 2017
1.B
1.B
1.B
A
B
C
D
E
Reverse Type-8H
2-3A to 1 DIMMs/channel
DDR_B_CLK 0<7>
DDR_B_CLK 0#<7>
DDR_B_CLK 1<7>
Address : A2
1 1
+3VS
RD244
12
RD247
0_0402_5%
@
12
RD252
0_0402_5%
RS@
Layout Note:
Place near JDIMM2
2 2
+1.2V
1U_0201_6.3V6M
CD86
1
2
+1.2V
10U_0603_6.3V6M
CD82
1
2
3 3
+1.2V
0.1U_0201_10V6K
CD91
2
1
10K_0402_5%
12
12
RD248
0_0402_5%
@
DDR_B_SA2
DDR_B_SA1
DDR_B_SA0
12
12
RD249
0_0402_5%
RD246
0_0402_5%
RS@
@
Note:
Check voltage tolerance of
VREF_DQ at the DIMM socket
CRB use 0.1uF x12 (6 pop,6 unpop),180pF x1,100uF x2
1U_0201_6.3V6M
1U_0201_6.3V6M
1
2
10U_0603_6.3V6M
1
2
0.1U_0201_10V6K
2
1
1U_0201_6.3V6M
CD78
CD67
1
1
2
2
10U_0603_6.3V6M
10U_0603_6.3V6M
CD90
CD96
1
1
2
2
0.1U_0201_10V6K
0.1U_0201_10V6K
CD94
CD97
2
2
1
1
1U_0201_6.3V6M
1U_0201_6.3V6M
CD93
CD77
CD66
CD81
CD71
1
1
2
2
10U_0603_6.3V6M
10U_0603_6.3V6M
CD68
CD88
1
1
2
2
180P_0402_50V8J
CD85
2
1
CD73
@EMC@
.1U_0402_1 6V7K
12
DDR_B_RST #
DDR_B_CLK 1#<7>
DDR_B_CKE0<7>
DDR_B_CKE1<7>
DDR_B_CS0 #<7>
DDR_B_CS1 #<7>
DDR_B_ODT 0<7>
DDR_B_ODT 1<7>
DDR_B_BG0<7>
DDR_B_BG1<7>
DDR_B_BA0< 7>
DDR_B_BA1< 7>
DDR_B_MA[13..0]<7>
DDR_B_MA14_ WE#<7>
DDR_B_MA15_ CAS#<7>
DDR_B_MA16_ RAS#<7>
DDR_B_ACT#<7 >
DDR_B_PAR<7>
DDR_B_ALERT #<7>
DDR_B_EVENT #<7>
DDR_B_RST #<7>
SMB_0_SDA< 9,13>
SMB_0_SCL<9,13>
DDR_B_DM[7 ..0]<7>
DDR_B_CLK 0
DDR_B_CLK 0#
DDR_B_CLK 1
DDR_B_CLK 1#
DDR_B_CKE0
DDR_B_CKE1
DDR_B_CS0 #
DDR_B_CS1 #
DDR_B_ODT 0
DDR_B_ODT 1
DDR_B_BG0
DDR_B_BG1
DDR_B_BA0
DDR_B_BA1
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14_ WE#
DDR_B_MA15_ CAS#
DDR_B_MA16_ RAS#
DDR_B_ACT#
DDR_B_PAR
DDR_B_ALERT #
DDR_B_EVENT #
DDR_B_RST #
SMB_0_SDA
SMB_0_SCL
DDR_B_SA2
DDR_B_SA1
DDR_B_SA0
DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7
JDIMM2A
RESERVE
137
CK0(T)
139
CK0#(C)
138
CK1(T)
140
CK1#(C)
109
CKE0
110
CKE1
149
S0#
157
S1#
162
S2#/C0
165
S3#/C1
155
ODT0
161
ODT1
115
BG0
113
BG1
150
BA0
145
BA1
144
A0
133
A1
132
A2
131
A3
128
A4
126
A5
127
A6
122
A7
125
A8
121
A9
146
A10_AP
120
A11
119
A12
158
A13
151
A14_WE#
156
A15_CAS#
152
A16_RAS#
114
ACT#
143
PARITY
116
ALERT#
134
EVENT#
108
RESET#
254
SDA
253
SCL
166
SA2
260
SA1
256
SA0
92
CB0_NC
91
CB1_NC
101
CB2_NC
105
CB3_NC
88
CB4_NC
87
CB5_NC
100
CB6_NC
104
CB7_NC
97
DQS8(T)
95
DQS8#(C)
12
DM0#/DBI0#
33
DM1#/DBI1#
54
DM2#/DBI2#
75
DM3#/DBI3#
178
DM4#/DBI4#
199
DM5#/DBI5#
220
DM6#/DBI6#
241
DM7#/DBI7#
96
DM8#/DBI8#
LOTES_ADDR00 70-P009A
CONN@
DQS0(T)
DQS0#(C)
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS1(T)
DQS1#(C)
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS2(T)
DQS2#(C)
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQS3(T)
DQS3#(C)
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS4(T)
DQS4#(C)
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQS5(T)
DQS5#(C)
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQS6(T)
DQS6#(C)
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQS7(T)
DQS7#(C)
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DDR_B_DQ1
7
DDR_B_DQ2
20
DDR_B_DQ3
21
DDR_B_DQ4
4
DDR_B_DQ5
3
DDR_B_DQ6
16
DDR_B_DQ7
17
DDR_B_DQS0
13
DDR_B_DQS0 #
11
DDR_B_DQ8
28
DDR_B_DQ9
29
DDR_B_DQ10
41
DDR_B_DQ11
42
DDR_B_DQ12
24
DDR_B_DQ13
25
DDR_B_DQ14
38
DDR_B_DQ15
37
DDR_B_DQS1
34
DDR_B_DQS1 #
32
DDR_B_DQ16
50
DDR_B_DQ17
49
DDR_B_DQ18
62
DDR_B_DQ19
63
DDR_B_DQ20
46
DDR_B_DQ21
45
DDR_B_DQ22
58
DDR_B_DQ23
59
DDR_B_DQS2
55
DDR_B_DQS2 #
53
DDR_B_DQ24
70
DDR_B_DQ25
71
DDR_B_DQ26
83
DDR_B_DQ27
84
DDR_B_DQ28
66
DDR_B_DQ29
67
DDR_B_DQ30
79
DDR_B_DQ31
80
DDR_B_DQS3
76
DDR_B_DQS3 #
74
DDR_B_DQ32
174
DDR_B_DQ33
173
DDR_B_DQ34
187
DDR_B_DQ35
186
DDR_B_DQ36
170
DDR_B_DQ37
169
DDR_B_DQ38
183
DDR_B_DQ39
182
DDR_B_DQS4
179
DDR_B_DQS4 #
177
DDR_B_DQ40
195
DDR_B_DQ41
194
DDR_B_DQ42
207
DDR_B_DQ43
208
DDR_B_DQ44
191
DDR_B_DQ45
190
DDR_B_DQ46
203
DDR_B_DQ47
204
DDR_B_DQS5
200
DDR_B_DQS5 #
198
DDR_B_DQ48
216
DDR_B_DQ49
215
DDR_B_DQ50
228
DDR_B_DQ51
229
DDR_B_DQ52
211
DDR_B_DQ53
212
DDR_B_DQ54
224
DDR_B_DQ55
225
DDR_B_DQS6
221
DDR_B_DQS6 #
219
DDR_B_DQ56
237
DDR_B_DQ57
236
DDR_B_DQ58
249
DDR_B_DQ59
250
DDR_B_DQ60
232
DDR_B_DQ61
233
DDR_B_DQ62
245
DDR_B_DQ63
246
DDR_B_DQS7
242
DDR_B_DQS7 #
240
DDR_B_DQ0
8
DDR_B_DQ[7..0] < 7>
DDR_B_DQS0 <7>
DDR_B_DQS0 # <7>
DDR_B_DQ[15 ..8] <7>
DDR_B_DQS1 <7>
DDR_B_DQS1 # <7>
DDR_B_DQ[23 ..16] <7>
DDR_B_DQS2 <7>
DDR_B_DQS2 # <7>
DDR_B_DQ[31 ..24] <7>
DDR_B_DQS3 <7>
DDR_B_DQS3 # <7>
DDR_B_DQ[39 ..32] <7>
DDR_B_DQS4 <7>
DDR_B_DQS4 # <7>
DDR_B_DQ[47 ..40] <7>
DDR_B_DQS5 <7>
DDR_B_DQS5 # <7>
DDR_B_DQ[55 ..48] <7>
DDR_B_DQS6 <7>
DDR_B_DQS6 # <7>
DDR_B_DQ[63 ..56] <7>
DDR_B_DQS7 <7>
DDR_B_DQS7 # <7>
Follow CRB design
+1.2V
RD243
1K_0402_1%
RD251
1K_0402_1%
1 2
CD84 4.7U_0402_6.3V6M
1 2
15mil
CD76 0.1U_0201_10V6K
1
2
+VREFB_CA
CD80 0.1U_0201_10V6K
CD87 1000P_0402_50V7K
2
2
1
1
1
2
Place near to SO-DIMM connector.
+1.2V +1.2V
JDIMM2B
RESERVE
111
VDD1
112
117
118
123
124
129
130
+3VS
135
136
255
164
1
2
5
6
9
10
14
15
18
19
22
23
26
27
30
31
35
36
39
40
43
44
47
48
51
52
56
57
60
61
64
65
68
69
72
73
77
78
81
82
85
86
89
90
93
94
98
262
Layout Note:
Place near JDIMM2.258
VDD11
VDD2
VDD12
VDD3
VDD13
VDD4
VDD14
VDD5
VDD15
VDD6
VDD16
VDD7
VDD17
VDD8
VDD18
VDD9
VDD19
VDD10
VDDSPD
VTT
VREFCA
VPP1
VPP2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
GND
LOTES_ADDR00 70-P009A
CONN@
GND
141
142
147
148
153
154
159
160
+0.6VS
163
258
257
259
99
102
103
106
107
167
168
171
172
175
176
180
181
184
185
188
189
192
193
196
197
201
202
205
206
209
210
213
214
217
218
222
223
226
227
230
231
234
235
238
239
243
244
247
248
251
252
261
+2.5V
CD89 1U_0201_6.3V6M
1
2
CRB use 1uF x1
CRB use 4.7uF x1,0.1uF x1
Layout Note:
Place near JDIMM2.257,259
CRB use 0.1uF x2,180pF x1
4 4
10U_0603_6.3V6M
1
2
+2.5V
1U_0201_6.3V6M
10U_0603_6.3V6M
CD79
CD75
CD83
1
1
2
2
A
Layout Note:
Place near JDIMM2.255
CRB use 1uF x1
+3VS
1U_0201_6.3V6M
CD95
1
2
1
2
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2017/12/25 2019/12/25
2017/12/25 2019/12/25
2017/12/25 2019/12/25
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Title
Title
Title
Size Document Number R ev
Size Document Number R ev
Size Document Number R ev
Custom
Custom
Custom
Date : Sheet of
Date : Sheet of
D
Date : Sheet of
+0.6VS
1U_0201_6.3V6M
1U_0201_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
CD74
CD70
1
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
DDR4_SO-DIMM
DDR4_SO-DIMM
DDR4_SO-DIMM
DH5AV_JV_0V_LA-G021P
DH5AV_JV_0V_LA-G021P
DH5AV_JV_0V_LA-G021P
E
CD72
CD92
1
1
2
2
14 48Monday, December 25, 2017
14 48Monday, December 25, 2017
14 48Monday, December 25, 2017
1.B
1.B
1.B
5
4
3
2
1
D D
PEG_ATX _GRX_P0<6>
PEG_ATX _GRX_N0<6>
PEG_ATX _GRX_P1<6>
PEG_ATX _GRX_N1<6>
PEG_ATX _GRX_P2<6>
PEG_ATX _GRX_N2<6>
PEG_ATX _GRX_P3<6>
PEG_ATX _GRX_N3<6>
PEG_ATX _GRX_P4<6>
PEG_ATX _GRX_N4<6>
PEG_ATX _GRX_P5<6>
PEG_ATX _GRX_N5<6>
PEG_ATX _GRX_P6<6>
PEG_ATX _GRX_N6<6>
PEG_ATX _GRX_P7<6>
PEG_ATX _GRX_N7<6>
C C
B B
PEG_ATX _GRX_P0
PEG_ATX _GRX_N0
PEG_ATX _GRX_P1
PEG_ATX _GRX_N1
PEG_ATX _GRX_P2
PEG_ATX _GRX_N2
PEG_ATX _GRX_P3
PEG_ATX _GRX_N3
PEG_ATX _GRX_P4
PEG_ATX _GRX_N4
PEG_ATX _GRX_P5
PEG_ATX _GRX_N5
PEG_ATX _GRX_P6
PEG_ATX _GRX_N6
PEG_ATX _GRX_P7
PEG_ATX _GRX_N7
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
CV312 0.2 2U_0402_16V7 KDIS@
CV306 0.2 2U_0402_16V7 KDIS@
CV308 0.2 2U_0402_16V7 KDIS@
CV305 0.2 2U_0402_16V7 KDIS@
CV307 0.2 2U_0402_16V7 KDIS@
CV309 0.2 2U_0402_16V7 KDIS@
CV313 0.2 2U_0402_16V7 KDIS@
CV304 0.2 2U_0402_16V7 KDIS@
CV2710 0.22U_0 402_16V7KT1DIS@
CV2707 0.22U_0 402_16V7KT1DIS@
CV2711 0.22U_0 402_16V7KT1DIS@
CV2709 0.22U_0 402_16V7KT1DIS@
CV2717 0.22U_0 402_16V7KT1DIS@
CV2714 0.22U_0 402_16V7KT1DIS@
CV2704 0.22U_0 402_16V7KT1DIS@
CV2706 0.22U_0 402_16V7KT1DIS@
CLK_PEG _P6<10>
CLK_PEG _N6<10>
PEG_ATX _C_GRX_P0
PEG_ATX _C_GRX_N0
PEG_ATX _C_GRX_P1
PEG_ATX _C_GRX_N1
PEG_ATX _C_GRX_P2
PEG_ATX _C_GRX_N2
PEG_ATX _C_GRX_P3
PEG_ATX _C_GRX_N3
PEG_ATX _C_GRX_P4
PEG_ATX _C_GRX_N4
PEG_ATX _C_GRX_P5
PEG_ATX _C_GRX_N5
PEG_ATX _C_GRX_P6
PEG_ATX _C_GRX_N6
PEG_ATX _C_GRX_P7
PEG_ATX _C_GRX_N7
CLK_PEG _P6
CLK_PEG _N6
APU_PCIE_ RST#<9,26,27,2 8>
PE_GPIO0<10>
UV1B
@
AT41
AT40
AR41
AR40
AP41
AP40
AM41
AM40
AL41
AL40
AK41
AK40
AJ41
AJ40
AH41
AH40
AV33
AU33
symbol2
PCIE_RX0P
PCIE_RX0N
PCIE_RX1P
PCIE_RX1N
PCIE_RX2P
PCIE_RX2N
PCIE_RX3P
PCIE_RX3N
PCIE_RX4P
PCIE_RX4N
PCIE_RX5P
PCIE_RX5N
PCIE_RX6P
PCIE_RX6N
PCIE_RX7P
PCIE_RX7N
PCIE_REFCLKP
PCIE_REFCLKN
REV 0.91
2160896 088A1R16M_FC BGA769P-NH
1
2
12
RV370
2.2K_040 2_5%
DIS@
PCIE_TX0P
PCIE_TX0N
PCIE_TX1P
PCIE_TX1N
PCIE_TX2P
PCIE_TX2N
PCIE_TX3P
PCIE_TX3N
PCIE_TX4P
PCIE_TX4N
PCIE_TX5P
PCIE_TX5N
PCIE_TX6P
PCIE_TX6N
PCIE_TX7P
PCIE_TX7N
PCIE_ZVSS
AV35
AU35
AU38
AU39
AR37
AR38
AN37
AN38
AL37
AL38
AJ37
AJ38
AG37
AG38
AE37
AE38
AV41
PERSTB
AC41
PX_EN
AU41
+3VSDGP U
UV2
MC74VHC 1G08DFT2G_SC 70-5
5
DIS@
P
IN1
4
O
IN2
G
3
PEG_ARX _C_GTX_P0
PEG_ARX _C_GTX_N0
PEG_ARX _C_GTX_P1
PEG_ARX _C_GTX_N1
PEG_ARX _C_GTX_P2
PEG_ARX _C_GTX_N2
PEG_ARX _C_GTX_P3
PEG_ARX _C_GTX_N3
PEG_ARX _C_GTX_P4
PEG_ARX _C_GTX_N4
PEG_ARX _C_GTX_P5
PEG_ARX _C_GTX_N5
PEG_ARX _C_GTX_P6
PEG_ARX _C_GTX_N6
PEG_ARX _C_GTX_P7
PEG_ARX _C_GTX_N7
PLT_RST _VGA#
PX_EN
1
TP@
For BACO mode(AMD PowerXpress) use, NC if not use
1 2
SA00000OH00
12
RV4
100K_04 02_5%
DIS@
T218
RV371
DIS@
200_040 2_1%
PLT_RST _VGA#
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
CV1 0.22U_0402 _16V7KDIS@
CV2 0.22U_0402 _16V7KDIS@
CV3 0.22U_0402 _16V7KDIS@
CV4 0.22U_0402 _16V7KDIS@
CV5 0.22U_0402 _16V7KDIS@
CV6 0.22U_0402 _16V7KDIS@
CV7 0.22U_0402 _16V7KDIS@
CV8 0.22U_0402 _16V7KDIS@
CV2715 0.22U_0 402_16V7KT1DIS@
CV2708 0.22U_0 402_16V7KT1DIS@
CV2713 0.22U_0 402_16V7KT1DIS@
CV2703 0.22U_0 402_16V7KT1DIS@
CV2705 0.22U_0 402_16V7KT1DIS@
CV2712 0.22U_0 402_16V7KT1DIS@
CV2716 0.22U_0 402_16V7KT1DIS@
CV2702 0.22U_0 402_16V7KT1DIS@
PEG_ARX _GTX_P0
PEG_ARX _GTX_N0
PEG_ARX _GTX_P1
PEG_ARX _GTX_N1
PEG_ARX _GTX_P2
PEG_ARX _GTX_N2
PEG_ARX _GTX_P3
PEG_ARX _GTX_N3
PEG_ARX _GTX_P4
PEG_ARX _GTX_N4
PEG_ARX _GTX_P5
PEG_ARX _GTX_N5
PEG_ARX _GTX_P6
PEG_ARX _GTX_N6
PEG_ARX _GTX_P7
PEG_ARX _GTX_N7
PEG_ARX _GTX_P0 <6>
PEG_ARX _GTX_N0 <6 >
PEG_ARX _GTX_P1 <6>
PEG_ARX _GTX_N1 <6 >
PEG_ARX _GTX_P2 <6>
PEG_ARX _GTX_N2 <6 >
PEG_ARX _GTX_P3 <6>
PEG_ARX _GTX_N3 <6 >
PEG_ARX _GTX_P4 <6>
PEG_ARX _GTX_N4 <6 >
PEG_ARX _GTX_P5 <6>
PEG_ARX _GTX_N5 <6 >
PEG_ARX _GTX_P6 <6>
PEG_ARX _GTX_N6 <6 >
PEG_ARX _GTX_P7 <6>
PEG_ARX _GTX_N7 <6 >
A A
Security Classification
Security Classification
Security Classification
2017/12/ 25 2019/12/ 25
2017/12/ 25 2019/12/ 25
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
2017/12/ 25 2019/12/ 25
3
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
R18M-M260/G190_(1/9)_PCIE
R18M-M260/G190_(1/9)_PCIE
R18M-M260/G190_(1/9)_PCIE
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Custom
Custom
Custom
Date : Sheet o f
Date : Sheet o f
2
Date : Sheet o f
Compal Electronics, Inc.
DH5AV_JV_0V_LA-G021P
DH5AV_JV_0V_LA-G021P
DH5AV_JV_0V_LA-G021P
15 48Monday, December 2 5, 2017
15 48Monday, December 2 5, 2017
15 48Monday, December 2 5, 2017
1
1.B
1.B
1.B
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