Compal LA-F803P Schematics

1 1

Compal Confidential

2 2

KBL-Y MB Schematic Document

EPS30 LA-F803P

3 3

4 4

Security Class ification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev: 0.3

2018.06.08

2017/03/ 20 2020/03/ 20

Issued Date

2017/03/ 20 2020/03/ 20

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Cover Sheet

Size Document N umber Rev

Custom

LA-F803P

Date: Sheet of

1 55Friday, June 08, 201 8

0.1

Compal Confidential

Model Name: KBL-Y

Project Name: LA-F803P

Kaby Lake Y Block Diagram

(KBL-Y 2+2 w/ LPDDR3L x64, Modern Standby )

1 1

FPC

Combo Jack

Sub-Board LS-F803P

Sub-Board

LS-F801P

2 2

eDP conn

JSIM

WWAN M.2 Conn.

TouchScreen Controller

eKTH6315

JTS2

eDP Redriver SN75DP130

HD + IR Camera

G-Sensor

Speaker AMP

TAS2557 T

Speaker_L

40 pin

40pin Conn.

40 pin

HP9DS1TR

PCIe Redriver

P. 26

udio Codec

Realtek ALC3292

P. 28

JLCD1

PCIe Redriver

SN75LVPE801DRFR

3 3

Follow Premiun Power Segment, S0ix & C10 optimized

HDA

I2S

P. 27

Speaker AMP

AS2557

P. 28

Speaker_R

. 22

P. 28

Headphone

eDP 1.3 x4

Intel Kaby Lake Y

2 + 2

I2C

Dual Core

USB2.0

ISH I2C

P. 25

USB2.0

Port 9

PCIe

Port 9

Port 1,5

TPD 4.5W

Memory Bus

Dual Channel 1866HMz

PCIe x4

Port 5 ~ 8

SPI0_CS0#

PCIe

SB2.0

USB2.0

USB3.1

Port 3

LPDDR3L Memory Down 64bit x 2

SSD (PCIe)

NGFF Key M

System BIOS ROM

8MB (TBD)

Port 10

Port 3

Port 7

LAN + BT

Windstorm Peak

SD1216

USB3.1 / DP Mux & Redriver

TI TUSB546A-DCIRNQR

P. 24

I2C

P. 7

P. 23

P. 37

P. 19 ~ 21

TX/RX

SUB1/2

USB3.1 Type-C Conn.

P. 36

CC1 / CC2

Power Path

DC/DC Circuit

Power Circuit

Compal Electronics, Inc.

Title

CNL-Y_2+2 Block Diagrams

Size Document Number Rev

Custom

LA-F803P

Date: Sheet of

P. 39

P. 40 ~ 53

2 55Friday, June 08, 2018

0.1

Port 1

Port 5

4 4

USB3.1

Type-C Conn.

P. 38

USB3.1

Type-C Conn.

P. 38

SBU1/2

TX/RX

MUX/DEMUX

TS3DS10224RUKR

P. 38

TX/RX

MUX/DEMUX

TS3DS10224RUKR

P. 38

CC1/2

C1/2

AUX

LSTX/RX

Thunderbolt 3

lpine Ridge DP

AUX

LSTX/RX

I2C

SB3.1 Type-C PD Controller

SPI ROM

8M-bi

TI TPS65988

P. 33~34

P. 35

PCIe x4

Port 1~4

DDI_1

DI_2

I2C/SMBus

LPC

KBC

ENE KB9022

PS/2

P. 30 P

Int. KBDClickPad

P. 5 ~ 18

P. 29

SMBus

. 30

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NTDI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NTDI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NTDI VISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTPRIOR WRI TTEN CONSENT OFCOMPA L ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTPRIOR WRI TTEN CONSENT OFCOMPA L ELECTRONICS, INC.

USB3.1 Type-C PD Controller

TI TPS65987D

SPI ROM

2M-bi

Thermal Sensor

F75303M

2017/03/20 2020/03/20

P. 31

Compal Secret Data

Deciphered Date

+3VS

(TBC)

Device Address (7 bit)

Track PAD

TBC

N/A N/A N/A N/A

EC TBC TBC

TBC

(TBC)

BATT

Charger 0x09 0x12

TPS65988(1)

TPS65988(2)

TPS65987D

F75303M

Power CHIP

SN75DP130

Codec

SPK AMP

0x0B 0x16

0x25 TBC TBC

0x21

1001_101xb

TBC TBC TBC

(TBC)

+3V_PCH +1.8V_PRIM+5VALW +1.0V_PRIM +1.0VA_GATE +VCC_PRIM

X7676632L24

+1.2V_DDR +3.3V_CV2 +1.8V_MEM +

ON ON

OFF

R1Sam@

ZZZ

1.0V_VCCST

ONOFF

Compal Electronics, Inc.

Title

Notes List

Size Document Number Rev

Custom

LA-F803P

Date: Sheet of

0x2C

0x10b TBC

1101011xb 0011110xb

+5VS +3VS +1.8VS +1.0V_VCCSTG +0.85VS_VCCIO +0.6VS_VTT +VCC_SA +VCC_GT +VCC_CORE

OFF

Address (8bit)

Read

Write

TBC TBC

Address (8bit) Write

Read

0x17

0x13

TBC TBC

TBC0x23

TBC

TBCTBC TBC

Address (8bit)

Write Read

TBC TBC

TBC

3 55Friday, June 08, 2018

Board ID Table for AD channel

Vcc 3.3V

Board ID /

PCB Revision

0 / 0.2 0 1 / 0.3 2 / 0.4 4 / 1.0

100K +/- 1%

15K +/- 1% 27K +/- 1% 43K +/- 1%

BOM Structure Table

Function

S0IX Mode S0IX@ NDSX@ Non-S0IX Mode LPC 1.8V LPC 3.3V

RF Componets RF@ @RF@ EMI Components ESD Components ESD@ @ESD@ ME Cnnector CONN@

Stuff

NDSX@

LPC@

@CPUPWM@Panel PWM control

EMI@ @EMI@

Un-Stuff

S0IX@ LPC@

@ECPWM@

V min

BID

0.423 V

0.978 V

V TYP

BID

0 V 0.300 V

0.430 V 0.438 V

0.702 V

0.992 V 1.006 V

HSIO Port Table

HSIO Port Capable

USB3.1 #1

USB3.1 #2

2 USB3.1 #3

3 USB3.1 #4

BID

0.713 V

Max

EC AD3

0x00 - 0x0B 0x1D - 0x26 0x31 - 0x3B0.691 V

0x47 - 0x54

Device PCIe CLK

USB3.1 Type-C

NOTE

USB3.1 Type-C DP with Mux + PD

USB2.0 Port Table

USB2.0 Port Device

USB2.0 (MB)1

USB2.0 (MB)

Blue Tooth

IR Camera

NOTE

USB3.1 Type-C + PD

WLAN 8265

SOC SMBUS Address Table

SOC_SMBUS Net Name

SOC_SMBCLK SOC_SMBDATA

SOC_SML0CLK SOC_SML0DATA

SML1_SMBCLK SML1_SMBDAT

Power Rail

+3V_PRIM

+3VS

EC SMBUS Address Table

EC_SMBUS Port

SMBUS Port 1

SMBUS Port 2

Power Rail Device Address (7 bit)

+3V_SMBUS

+3VL_EC

4 USB3.1 #5 / PCIE #1

5 USB3.1 #6 / PCIE #2

Un-stuff Components

@ TP@ Rshort@

Remove in MP MP@

6 PCIE #3

7 PCIE #4

8 PCIE #5

/ GbE

9 PCIE #6

10 PCIE #7

11 PCIE #8

1 1

12 PCIE #9

13 PCIE #10 WLAN CLK3 &

Power State

STATE

/ SATA #0

/ SATA #1

/ GbE

SIGNAL

S0 (Full ON)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

Load BOM Option Table

S5 (Soft OFF)

BOM Number Load BOM Option

431ACZ32L01

431ACZ32L02

431ACZ32L03

431ACZ32L04

431ACZ32L05

431ACZ32L06

431ACZ32L07

@CPUPWM@/LPC@/MP@/S0IX@/X4E@/RF@/R1Mi@/R1I7@

@CPUPWM@/LPC@/MP@/S0IX@/X4E@/RF@/R1Hy@/R1I5@

@CPUPWM@/LPC@/MP@/S0IX@/X4E@/RF@/R1Mi16@/R1I7@

@CPUPWM@/LPC@/MP@/S0IX@/X4E@/RF@/R1Sam@/R1I5@

@CPUPWM@/LPC@/MP@/S0IX@/X4E@/RF@/R1Mi16@/R1I7R@

@CPUPWM@/LPC@/MP@/S0IX@/X4E@/RF@/R1Mi16@/R1I5R@

@CPUPWM@/LPC@/MP@/S0IX@/X4E@/RF@/R1Hy@/R1I7R@

431ACZ32L08 @CPUPWM@/LPC@/MP@/S0IX@/X4E@/RF@/R1Mi@/R1I5R@

431ACZ32L09

431ACZ32L10

431ACZ32L11

@CPUPWM@/LPC@/MP@/S0IX@/X4E@/RF@/R1Sam@/R1I7R@

@CPUPWM@/LPC@/MP@/S0IX@/X4E@/RF@/R1Hy@/R1I5R@

@CPUPWM@/LPC@/MP@/S0IX@/X4E@/RF@/R1Mi@/R1I7R@

431ACZ32L12 @CPUPWM@/LPC@/MP@/S0IX@/X4E@/RF@/R1Sam@/R1I5R@

Thunderbolt, Alpine Rodge

SSD (NGFF_Key M)

WWAN CLK1 &

SLP_S4#

SLP_S3#

LOW HIGH

SLP_S5#

HIGH

LOWLOW

HIGH

+VALW

ON ON ON ONHIGH HIGH HIGH

ONONON

OFF

OFFLOW LOW LOW

CLK4 & CLKREQ#4

CLK2 & CLKREQ#2

CLKREQ#1

CLKREQ#3

+VS Clock

OFF

PCIe/SATA interface

OFF

SA0000ADW00 S IC HE8067702739826 SR345 H0 1.2G BGA

SA0000ADW10 S IC HE8067702739826 SR345 H0 1.2G A32 !

SA0000C4Q00 S IC A32 HE8067702739846 QLKW H0 1.3G BGA 1515

DAX

PCB

Part Number = DAA000H5000 PCB 2DC LA-F803P REV0 M/B

X4E@

ZZZ

X4EACZ32L01

R1I5@

UC1

R3I5@

UC1

R1I5R@

UC1

SMBUS Port 3

+3VALW

I2C/ISH Address Table

I2C Port

I2C 0

I2C 1

ISH_I2C 0

State

R1I7@

UC1

SA0000ADS30 S IC HE8067702739526 SR33X H0 1.3G BGA

R3I7@

UC1

SA0000ADS40 S IC HE8067702739526 SR33X H0 1.3G A32 !

R1I7R@

UC1

SA0000C4P00 S IC A32 HE8067702739858 QQF4 H0 1.5G BGA 1515

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NTDI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NTDI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NTDI VISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTPRIOR WRI TTEN CONSENT OFCOMPA L ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTPRIOR WRI TTEN CONSENT OFCOMPA L ELECTRONICS, INC.

S3 /AC

DS3

S5 S4/AC doesn't exist OFFO

R1Mi@

ZZZ

X7676632L21

2017/03/20 2020/03/20

Power Rail Device Address (7 bit)

+3VS

+3V_PRIM

+3VALW

Power plane

R1Hy@

ZZZ

X7676632L22

Compal Secret Data

Deciphered Date

Track PAD(Reserved)

Touch Screen

HP9DS1TR

+3VALW_D SW

+3VALW +1.8VALW +3VLP

ON ON

ONS5 S4/AC OFF

FF OFF

R1Mi16@

ZZZ

X7676632L23

0.1

[EPDS30-Power Map_KBL-Y2+2_LPDDR3L_Premium_S0ix]

+8.4V PUZ1

PWM

+3V_LID(Battery Cell)

D D

DC1

DC2

+3VL_RTC

+3VL

+3V_SMBUS

C C

[EPS30-SMBus Map]

UC1

SOC_SMBCLK

AC12 W6

SOC_SMBDATA

CPU

B B

AA4 W10

W4 AC10

CY10 CW9

AB11 AB9

SOC_SML0CLK SOC_SML0DATA

I2C_0_SCL I2C_0_SDA

I2C_1_SCL_TS I2C_1_SDA_TS

SOC_SML1CLK SOC_SML1DATA

+3VL

+3V_PRIM

R=1K

+3V_PRIM

R=1K

+3V_PRIM

R=1K

+3V_PRIM

R=1K

+3VALW_TP

QC3 @

+3VS

R=1K

SMB_CK2 SMB_DA2

+3VALW_TP

R=2.2K

+3VALW_TP

+3VS

R=2.2K

Thermal Sensor :F75303M

TP_SMBCLK TP_SMBDAT

Address : 1001_101x b

Touch Pad

Touch Screen

MP2940-0020

PU1001

SY8286RAC

PUH1 PWM NB681GD-Z

PUM1 PWM SY8210DQVC

PU301 Regulator SY8286BRAC

PU302 Regulator SY8286BRAC

Page. 50

Page. 48

Page. 44

Page. 39

Page. 33

+VCCIN

(33A)

+1.05V_PRIM

(4.91A)PWM

+1.05V_PRIM_COR E

(2.31A)

Premium

+0.6VS_VTT

+1.1V_VDDQ

+3VALW

PU1801 PWM G5719CTB1U

UC18 Loadswitch TPS22907YZTR

+5VALW

UV2 MOSFET G527ATP1U

Page. 40

Page. 29

+1.8PRIM

+3V_PRIM

(3.2A)

+5VS_SUB

(2A)

(0.15A)

+1.0V_PRIM

C10

+1.8V_PRIM

SYSON (PM_SLP_S4#)

UC5 +1.0VS_VCCST G Loadswitch TPS22922YZPR

Loadswitch TPS22907YZTR

UD5 Loadswitch TPS22913CYZVR

UA4

+3VALW

LDO G9090-180TO1U

Page. 12

+1.2V_VCCPLL_OCUC7+1.2V_VDDQ

Page. 12

+1.8V_MEM

Page. 21

+1.8VALW_AUDIO

Page. 28

For SPK AMP register value kee p.

Page. 39

Page. 24

Page. 23

+3VS_AUDIO

+1.8VS_AUDIO

+3VS_SSD

+3VS_WLAN

+3VALW

SUSP# (AUDIO_PWREN)

+3VALW

NGFF_SSD_PWREN

+3VALW

WLAN_PWR_EN

U7 Loadswitch TPS22907YZTR

US1 Loadswitch TPS22922YZPR

UN2 Loadswitch TPS22922YZPR

Premium

+3VS+3VALW

+5VS

+5VALW

SUSP#

(PM_SLP_S3#)

U6 Load Switch

EM5209VF

+3VS

UK1:+3VALW_EC

A A

Address : 0x1A/0X19

(+3VL)

EC_SMB_CK2

B8 A6

EC_SMB_DA2

EC_SMB_CK1

A8 A7

EC_SMB_DA1

D6 E7

EC_SMB_CK3 EC_SMB_DA3

+3VL_EC

R=2.2K

+3V_SMBUS

R=2.2K

+3VALW

R=4.7K

EC_SMB_CK1_R EC_SMB_DA1_R

R=100

R=0

SPK AMP*2

R=0@

SCL_CHG SDA_CHG

QK3

BAT

Charger

Codec:ALC3292

0x09

TPS65988/TPS65987

+3VALW

QK5

JTYPEC1

JTYPEC2

JTYPEC3

SMB_BS_CLK SMB_BS_DAT

Address : 0x25

Address : 0x21

Address : 0x23

SCL_P_MP2940 SDA_P_MP2940

R=0

RE_CL RE_DA

R=0

R: Address : 0x4B W: Address : 0x4A

R: Address : 0x43 W: Address : 0x42

R: Address : 0x47 W: Address : 0x46

+3VALW

R=10K

+3VS_EDP_RE

R=10K

MP2940

SN75DP130

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NTDI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NTDI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NTDI VISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTPRIOR WRI TTEN CONSENT OFCOMPA L ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTPRIOR WRI TTEN CONSENT OFCOMPA L ELECTRONICS, INC.

2017/03/20 2020/03/20

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Power MAP

LA-F801P

4 55Friday, June 08, 2018

0.1

+3VS

1 2

RC6 2.2K_0201_5%@

1 2

RC16 2.2K_0201_5%

1 2

RC32 2.2K_0201_5%@

1 2

RC33 2.2K_0201_5%

SOC_DP1_CT RL_CLK SOC_DP1_CT RL_DATA SOC_DP2_CT RL_CLK SOC_DP2_CT RL_DATA

PV: HPD double pull down

Functional Strap Definitions

D D

GPP_E19 (Internal Pull Down): DDPB_CTRLDATA

0 = Port B is not detected.

1 = Port B is detected.

GPP_E21 (Internal Pull Down): DDPC_CTRLDATA

0 = Port C is not detected.

1 = Port C is detected.

+3VS

1 2

RC1 100K_0201_5%@

1 2

RC71 10K_0201_5%@

1 2

RC485 10K_ 0201_5%

+1.0V_VCCST

C C

+1.0VS_VCCSTG

1 2

RC95 1K_0201_5%

1 2

RC80 49.9_0402_1%@

1 2

RC13 1K_0201_5%

+3V_PRIM

1 2

RC490 10K_ 0201_5%

TP_INT#

TS_INT#

EC_SCI#

H_THERMT RIP#

H_CATERR#

H_PROCHOT#

NMI_DBG#_CPU

Alpine Ridge

+0.85VS_VCCIO

PDG_Processor strap CFG[4] should be pulled

UC1A

NMI_DBG#_CPU(29)

A46

DDI1_TXN[0]

C46

DDI1_TXP[0]

C48

DDI1_TXN[1]

A48

DDI1_TXP[1]

B45

DDI1_TXN[2]

D45

DDI1_TXP[2]

B47

DDI1_TXN[3]

D47

DDI1_TXP[3]

A42

DDI2_TXN[0]

C42

DDI2_TXP[0]

A44

DDI2_TXN[1]

C44

DDI2_TXP[1]

B41

DDI2_TXN[2]

D41

DDI2_TXP[2]

B43

DDI2_TXN[3]

D43

DDI2_TXP[3]

GPP_E18/DDPB_CTRLCLK

GPP_E19/DDPB_CTRLDATA

GPP_E20/DDPC_CTRLCLK

GPP_E21/DDPC_CTRLDATA

GPP_E22

GPP_E23

A50

EDP_RCOMP

KBL-Y_BGA1515

TC69 @ TC68 @ TC6 @ TC7 @

TS_INT#(22) TP_INT#(30)

12 12

H_CATERR#

H_PROCHOT# _R H_THERMT RIP#

XDP_BPM#0_R XDP_BPM#1_R XDP_BPM#2_R XDP_BPM#3_R

TS_INT# TP_INT# NMI_DBG#_CPU

CPU_POPIRCOMP PCH_OPIRCOMP

SOC_DP1_N0(33) SOC_DP1_P0(33) SOC_DP1_N1(33) SOC_DP1_P1(33) SOC_DP1_N2(33) SOC_DP1_P2(33) SOC_DP1_N3(33) SOC_DP1_P3(33)

SOC_DP2_N0(33) SOC_DP2_P0(33) SOC_DP2_N1(33) SOC_DP2_P1(33) SOC_DP2_N2(33) SOC_DP2_P2(33) SOC_DP2_N3(33) SOC_DP2_P3(33)

RC4

RC4 Width 20 mils, Spacing 25 mils, Length < 100 mil

H_PECI(29)

H_PROCHOT#(29,49)

SOC_DP1_N0 SOC_DP1_P0 SOC_DP1_N1 SOC_DP1_P1 SOC_DP1_N2 SOC_DP1_P2 SOC_DP1_N3 SOC_DP1_P3

SOC_DP2_N0 SOC_DP2_P0 SOC_DP2_N1 SOC_DP2_P1 SOC_DP2_N2 SOC_DP2_P2 SOC_DP2_N3 SOC_DP2_P3

SOC_DP1_CT RL_CLK SOC_DP1_CT RL_DATA

SOC_DP2_CT RL_CLK SOC_DP2_CT RL_DATA

V: delete TS_RS T#_PCH

H_PECI H_PROCHOT#

24.9_0402_1 %

+EDP_COM

1 2

RC8 499_0402_1%

RC67 0_0402_5%

RC14 4 9.9_0402_1% RC15 4 9.9_0402_1%

SKYLAKE_ULX

DDI

<DDI1>

<DDI2>

DISPLAY SIDEBANDS

SKTOCC#

low to enable embedded DisplayPort*

DISPLAY

eDP

<DDI1>

<DDI2>

<DDI1>

GPP_E13/DDPB_HPD0

<DDI2>

GPP_E14/DDPC_HPD1 GPP_E15/DDPD_HPD2 GPP_E16/DDPE_HPD3

GPP_E17/EDP_HPD

1 OF 20

SKYLAKE_ULX

UC1D

H49

CATERR#

F49

PECI

J48

PROCHOT#

H47

THERMTRIP#

B62

SKTOCC#

H51

BPM#[0]

J50

BPM#[1]

F51

BPM#[2]

G50

BPM#[3]

E11

GPP_E3/CPU_GP0

GPP_E7/CPU_GP1

BD8

GPP_B3/CPU_GP2

BC11

GPP_B4/CPU_GP3

BN17

PROC_POPIRCOMP

BP16

PCH_OPIRCOMP

CPU MISC

KBL-Y_BGA1515

EDP_DISP_UTIL

Rev0.87

EDP_TXN[0] EDP_TXP[0] EDP_TXN[1] EDP_TXP[1] EDP_TXN[2] EDP_TXP[2] EDP_TXN[3] EDP_TXP[3]

EDP_AUXN EDP_AUXP

DDI1_AUXN DDI1_AUXP DDI2_AUXN DDI2_AUXP

EDP_BKLEN

EDP_BKLCTL

EDP_VDDEN

JTAG

4 OF 20

EDP_TXN0

H45

EDP_TXP0

F45

EDP_TXN1

J44

EDP_TXP1

G44

EDP_TXN2

J46

EDP_TXP2

G46

EDP_TXN3

H43

EDP_TXP3

F43

EDP_AUXN

J42

EDP_AUXP

G42

EDP_DISP

A40

SOC_DP1_AUXN

H41

SOC_DP1_AUXP

F41

SOC_DP2_AUXN

J40

SOC_DP2_AUXP

G40

SOC_DP1_HPD

C11

SOC_DP2_HPD

L10

EC_SCI#

M7 F6

EDP_HPD

SOC_ENBKL

SOC_BKL_PW M

SOC_ENVDD

Rev0.87

PROC_TCK

PROC_TDI PROC_TDO PROC_TMS

PROC_TRST#

PCH_JTAG_TCK

PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS

PCH_TRST#

JTAGX

EDP_TXN0 (22) EDP_TXP0 (22) EDP_TXN1 (22) EDP_TXP1 (22) EDP_TXN2 (22) EDP_TXP2 (22) EDP_TXN3 (22) EDP_TXP3 (22)

EDP_AUXN (22) EDP_AUXP (22)

0_0201_5%

CPU_XDP_TCK 0 SOC_XDP_TDI SOC_XDP_TDO SOC_XDP_TMS SOC_XDP_TRST #

PCH_JTAG_TC K1 SOC_XDP_TDI

SOC_XDP_TDO SOC_XDP_TMS SOC_XDP_TRST # CPU_XDP_TCK 0

SOC_DP1_AUXN (33) SOC_DP1_AUXP (33) SOC_DP2_AUXN (33) SOC_DP2_AUXP (33)

SOC_DP1_HPD (33) SOC_DP2_HPD (33) EC_SCI# (29 )

EDP_HPD (22)

SOC_ENBKL ( 22,29) SOC_BKL_PW M (22) SOC_ENVDD (22)

RC2

D53 C54 G48 C59 F47

B53 C50 B51 A52 C52 B49

<eDP>

TBT

+1.0VS_VCCSTG

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2041/09/08 2013/10/28

Compal Secret Data

Deciphered Date

Place to CPU si de

SOC_XDP_TMS

SOC_XDP_TDI

SOC_XDP_TDO

PCH_JTAG_TC K1

CPU_XDP_TCK 0

5 55Friday, June 08, 2018

RC390 51_0402_5 %@

RC389 51_0402_5 %@

RC391 51_0402_1 %

RC399 51_0402_5 %@

RC398 51_0402_1 %

Title

Size Document Number Rev

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

SKL Y(1/13) DDI,MSIC,XDP

LA-F803P

0.1

Non-Interleave Memory

D D

UC1B

DDR_A_D[0..15](19)

DDR_A_D[16..31 ](19)

C C

DDR_A_D[32..47 ](19)

DDR_A_D[48..63 ](19)

B B

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15

DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

AG61

DDR0_DQ[0]

AH60

DDR0_DQ[1]

AK62

DDR0_DQ[2]

AK60

DDR0_DQ[3]

AH62

DDR0_DQ[4]

AG63

DDR0_DQ[5]

AL61

DDR0_DQ[6]

AL63

DDR0_DQ[7]

AM60

DDR0_DQ[8]

AM62

DDR0_DQ[9]

AT60

DDR0_DQ[10]

AR61

DDR0_DQ[11]

AN61

DDR0_DQ[12]

AN63

DDR0_DQ[13]

AR63

DDR0_DQ[14]

AT62

DDR0_DQ[15]

Interleave/Non-lnterleaved

AT56

DDR1_DQ[0]/DDR0_DQ[16]

AR55

DDR1_DQ[1]/DDR0_DQ[17]

AN57

DDR1_DQ[2]/DDR0_DQ[18]

AN55

DDR1_DQ[3]/DDR0_DQ[19]

AR57

DDR1_DQ[4]/DDR0_DQ[20]

AT58

DDR1_DQ[5]/DDR0_DQ[21]

AM58

DDR1_DQ[6]/DDR0_DQ[22]

AM56

DDR1_DQ[7]/DDR0_DQ[23]

AL55

DDR1_DQ[8]/DDR0_DQ[24]

AL57

DDR1_DQ[9]/DDR0_DQ[25]

AH58

DDR1_DQ[10]/DDR0_DQ[26]

AH56

DDR1_DQ[11]/DDR0_DQ[27]

AK58

DDR1_DQ[12]/DDR0_DQ[28]

AK56

DDR1_DQ[13]/DDR0_DQ[29]

AG55

DDR1_DQ[14]/DDR0_DQ[30]

AG57

DDR1_DQ[15]/DDR0_DQ[31]

BE55

DDR0_DQ[16]/DDR0_DQ[32]

BC55

DDR0_DQ[17]/DDR0_DQ[33]

BG53

DDR0_DQ[18]/DDR0_DQ[34]

BE53

DDR0_DQ[19]/DDR0_DQ[35]

BC53

DDR0_DQ[20]/DDR0_DQ[36]

BG55

DDR0_DQ[21]/DDR0_DQ[37]

BD52

DDR0_DQ[22]/DDR0_DQ[38]

BF52

DDR0_DQ[23]/DDR0_DQ[39]

BC51

DDR0_DQ[24]/DDR0_DQ[40]

BE51

DDR0_DQ[25]/DDR0_DQ[41]

BC49

DDR0_DQ[26]/DDR0_DQ[42]

BE49

DDR0_DQ[27]/DDR0_DQ[43]

BG51

DDR0_DQ[28]/DDR0_DQ[44]

BG49

DDR0_DQ[29]/DDR0_DQ[45]

BF48

DDR0_DQ[30]/DDR0_DQ[46]

BD48

DDR0_DQ[31]/DDR0_DQ[47]

BJ55

DDR1_DQ[16]/DDR0_DQ[48]

BL55

DDR1_DQ[17]/DDR0_DQ[49]

BJ53

DDR1_DQ[18]/DDR0_DQ[50]

BL53

DDR1_DQ[19]/DDR0_DQ[51]

BN55

DDR1_DQ[20]/DDR0_DQ[52]

BN53

DDR1_DQ[21]/DDR0_DQ[53]

BM52

DDR1_DQ[22]/DDR0_DQ[54]

BK52

DDR1_DQ[23]/DDR0_DQ[55]

BL51

DDR1_DQ[24]/DDR0_DQ[56]

BJ51

DDR1_DQ[25]/DDR0_DQ[57]

BL49

DDR1_DQ[26]/DDR0_DQ[58]

BJ49

DDR1_DQ[27]/DDR0_DQ[59]

BN49

DDR1_DQ[28]/DDR0_DQ[60]

BN51

DDR1_DQ[29]/DDR0_DQ[61]

BK48

DDR1_DQ[30]/DDR0_DQ[62]

BM48

DDR1_DQ[31]/DDR0_DQ[63]

KBL-Y_BGA1515

Reserve

DDR0_ALERT #

SKYLAKE_ULX

DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]

DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]

DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]

DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]

DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]

DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]

DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]

DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]

DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]

DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]

DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]

DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1]

DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]

DDR CH-A

2 OF 20

1 2

RC540 0_0201_5 %short@

DDR0_CKN[0] DDR0_CKP[0] DDR0_CKN[1] DDR0_CKP[1]

DDR0_CKE[0] DDR0_CKE[1] DDR0_CKE[2] DDR0_CKE[3]

DDR0_CS#[0] DDR0_CS#[1]

DDR3L / LPDDR3 / DDR4

DDR1_DQSN[0]/DDR0_DQSN[2] DDR1_DQSP[0]/DDR0_DQSP[2] DDR1_DQSN[1]/DDR0_DQSN[3] DDR1_DQSP[1]/DDR0_DQSP[3] DDR0_DQSN[2]/DDR0_DQSN[4] DDR0_DQSP[2]/DDR0_DQSP[4] DDR0_DQSN[3]/DDR0_DQSN[5] DDR0_DQSP[3]/DDR0_DQSP[5] DDR1_DQSN[2]/DDR0_DQSN[6] DDR1_DQSP[2]/DDR0_DQSP[6] DDR1_DQSN[3]/DDR0_DQSN[7] DDR1_DQSP[3]/DDR0_DQSP[7]

DDR0_ODT[0]

DDR0_MA[3]

DDR0_MA[4] DDR0_DQSN[0] DDR0_DQSP[0] DDR0_DQSN[1] DDR0_DQSP[1]

Interleave/Non-lnterleaved

DDR0_ALERT#

DDR_VREF_CA

DDR0_VREF_DQ DDR1_VREF_DQ

DDR_VTT_CNTL

Rev0.87

DDR0_PAR

M_CLK_A_DDR #0

BC62

M_CLK_A_DDR 0

BC60

M_CLK_A_DDR #1

BA60

M_CLK_A_DDR 1

BA62

DDR_A_CKE0

BB57

DDR_A_CKE1

BC58

DDR_A_CKE2

BE57

DDR_A_CKE3

AW61

DDR_A_CS0#

AW63

DDR_A_CS1#

BJ57

DDR_A_ODT0

BN61

DDR_A_CAA_0

AW59

DDR_A_CAA_1

AW55

DDR_A_CAA_2

BF62

DDR_A_CAA_3

AV56

DDR_A_CAA_4

AW57

DDR_A_CAA_5

AV58

DDR_A_CAA_6

BA56

DDR_A_CAA_7

BD59

DDR_A_CAA_8

BD61

DDR_A_CAA_9

BG61

DDR_A_CAB_0

BK59

DDR_A_CAB_1

BL62

DDR_A_CAB_2

BJ61

DDR_A_CAB_3

AV60

DDR_A_CAB_4

BN62

DDR_A_CAB_5

BB61

DDR_A_CAB_6

BL61

DDR_A_CAB_7

BM59

DDR_A_CAB_8

BN58

DDR_A_CAB_9

AV62

BB63 BL57

DDR_A_DQS#0

AJ61

DDR_A_DQS0

AJ63

DDR_A_DQS#1

AP62

DDR_A_DQS1

AP60

DDR_A_DQS#2

AP56

DDR_A_DQS2

AP58

DDR_A_DQS#3

AJ57

DDR_A_DQS3

AJ55

DDR_A_DQS#4

BD54

DDR_A_DQS4

BF54

DDR_A_DQS#5

BF50

DDR_A_DQS5

BD50

DDR_A_DQS#6

BM54

DDR_A_DQS6

BK54

DDR_A_DQS#7

BK50

DDR_A_DQS7

BM50

DDR0_ALERT #

BG57 BM56

AR53 AN53 AW53

DDR_VTT_C NTL SM_RCOMP2

BN47

DDR_VTT_C NTL

M_CLK_A_DDR #0 (19) M_CLK_A_DDR 0 (19) M_CLK_A_DDR #1 (19) M_CLK_A_DDR 1 (19)

DDR_A_CKE0 (19) DDR_A_CKE1 (19) DDR_A_CKE2 (19) DDR_A_CKE3 (19)

DDR_A_CS0# (19) DDR_A_CS1# (19) DDR_A_ODT0 (19)

DDR_A_CAA_0 (19) DDR_A_CAA_1 (19) DDR_A_CAA_2 (19) DDR_A_CAA_3 (19) DDR_A_CAA_4 (19) DDR_A_CAA_5 (19) DDR_A_CAA_6 (19) DDR_A_CAA_7 (19) DDR_A_CAA_8 (19) DDR_A_CAA_9 (19) DDR_A_CAB_0 (19) DDR_A_CAB_1 (19) DDR_A_CAB_2 (19) DDR_A_CAB_3 (19) DDR_A_CAB_4 (19) DDR_A_CAB_5 (19) DDR_A_CAB_6 (19) DDR_A_CAB_7 (19) DDR_A_CAB_8 (19) DDR_A_CAB_9 (19)

DDR_A_DQS#0 (19) DDR_A_DQS0 (19) DDR_A_DQS#1 (19) DDR_A_DQS1 (19)

DDR_A_DQS#2 (19) DDR_A_DQS2 (19) DDR_A_DQS#3 (19) DDR_A_DQS3 (19) DDR_A_DQS#4 (19) DDR_A_DQS4 (19) DDR_A_DQS#5 (19) DDR_A_DQS5 (19) DDR_A_DQS#6 (19) DDR_A_DQS6 (19) DDR_A_DQS#7 (19) DDR_A_DQS7 (19) DDR_B_DQS# 6 (20)

T273TP@ T86TP@

+0.6V_VREFCA +0.6V_A_VREFDQ +0.6V_B_VREFDQ

Trace width/Spacing >= 20mils

1 2

RC48 0_0201_5%short@

DDR_B_D[0..15 ](20)

DDR_B_D[16 ..31](20)

DDR_B_D[32 ..47](20)

DDR_B_D[48 ..63](20)

SM_PG_CTRL (44)

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47

DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

UC1C

interleave / Non-lnterleaved

BC41

DDR0_DQ[32]/DDR1_DQ[0]

BC39

DDR0_DQ[33]/DDR1_DQ[1]

BG41

DDR0_DQ[34]/DDR1_DQ[2]

BE39

DDR0_DQ[35]/DDR1_DQ[3]

BF42

DDR0_DQ[36]/DDR1_DQ[4]

BD42

DDR0_DQ[37]/DDR1_DQ[5]

BG39

DDR0_DQ[38]/DDR1_DQ[6]

BE41

DDR0_DQ[39]/DDR1_DQ[7]

BC43

DDR0_DQ[40]/DDR1_DQ[8]

BD46

DDR0_DQ[41]/DDR1_DQ[9]

BG43

DDR0_DQ[42]/DDR1_DQ[10]

BG45

DDR0_DQ[43]/DDR1_DQ[11]

BC45

DDR0_DQ[44]/DDR1_DQ[12]

BE43

DDR0_DQ[45]/DDR1_DQ[13]

BE45

DDR0_DQ[46]/DDR1_DQ[14]

BF46

DDR0_DQ[47]/DDR1_DQ[15]

BM28

DDR1_DQ[32]/DDR1_DQ[16]

BN27

DDR1_DQ[33]/DDR1_DQ[17]

BK28

DDR1_DQ[34]/DDR1_DQ[18]

BL25

DDR1_DQ[35]/DDR1_DQ[19]

BN25

DDR1_DQ[36]/DDR1_DQ[20]

BL27

DDR1_DQ[37]/DDR1_DQ[21]

BJ25

DDR1_DQ[38]/DDR1_DQ[22]

BJ27

DDR1_DQ[39]/DDR1_DQ[23]

BM24

DDR1_DQ[40]/DDR1_DQ[24]

BK24

DDR1_DQ[41]/DDR1_DQ[25]

BN21

DDR1_DQ[42]/DDR1_DQ[26]

BJ23

DDR1_DQ[43]/DDR1_DQ[27]

BL23

DDR1_DQ[44]/DDR1_DQ[28]

BN23

DDR1_DQ[45]/DDR1_DQ[29]

BJ21

DDR1_DQ[46]/DDR1_DQ[30]

BL21

DDR1_DQ[47]/DDR1_DQ[31]

BN45

DDR0_DQ[48]/DDR1_DQ[32]

BM46

DDR0_DQ[49]/DDR1_DQ[33]

BL43

DDR0_DQ[50]/DDR1_DQ[34]

BK46

DDR0_DQ[51]/DDR1_DQ[35]

BN43

DDR0_DQ[52]/DDR1_DQ[36]

BL45

DDR0_DQ[53]/DDR1_DQ[37]

BJ45

DDR0_DQ[54]/DDR1_DQ[38]

BJ43

DDR0_DQ[55]/DDR1_DQ[39]

BM42

DDR0_DQ[56]/DDR1_DQ[40]

BN41

DDR0_DQ[57]/DDR1_DQ[41]

BJ41

DDR0_DQ[58]/DDR1_DQ[42]

BN39

DDR0_DQ[59]/DDR1_DQ[43]

BK42

DDR0_DQ[60]/DDR1_DQ[44]

BL41

DDR0_DQ[61]/DDR1_DQ[45]

BL39

DDR0_DQ[62]/DDR1_DQ[46]

BJ39

DDR0_DQ[63]/DDR1_DQ[47]

BF28

DDR1_DQ[48]

BD28

DDR1_DQ[49]

BG25

DDR1_DQ[50]

BC27

DDR1_DQ[51]

BG27

DDR1_DQ[52]

BE27

DDR1_DQ[53]

BE25

DDR1_DQ[54]

BC25

DDR1_DQ[55]

BF24

DDR1_DQ[56]

BD24

DDR1_DQ[57]

BG21

DDR1_DQ[58]

BC23

DDR1_DQ[59]

BE23

DDR1_DQ[60]

BG23

DDR1_DQ[61]

BC21

DDR1_DQ[62]

BE21

DDR1_DQ[63]

KBL-Y_BGA1515

SKYLAKE_ULX

DDR3L / LPDDR3 / DDR4

DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]

DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]

DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]

DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]

DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]

DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]

DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]

DDR1_BA[0] /DDR1_CAB[4]/DDR1_BA[0]

DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]

DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]

DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1]

DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]

interleave / Non-lnterleaved

DDR0_DQSN[4]/DDR1_DQSN[0] DDR0_DQSP[4]/DDR1_DQSP[0] DDR0_DQSN[5]/DDR1_DQSN[1] DDR0_DQSP[5]/DDR1_DQSP[1] DDR1_DQSN[4]/DDR1_DQSN[2] DDR1_DQSP[4]/DDR1_DQSP[2] DDR1_DQSN[5]/DDR1_DQSN[3] DDR1_DQSP[5]/DDR1_DQSP[3] DDR0_DQSN[6]/DDR1_DQSN[4] DDR0_DQSP[6]/DDR1_DQSP[4] DDR0_DQSN[7]/DDR1_DQSN[5] DDR0_DQSP[7]/DDR1_DQSP[5]

DDR CH-B

3 OF 20

Rev0.87

DDR1_CKN[0] DDR1_CKP[0] DDR1_CKN[1] DDR1_CKP[1]

DDR1_CKE[0] DDR1_CKE[1] DDR1_CKE[2] DDR1_CKE[3]

DDR1_CS#[0] DDR1_CS#[1] DDR1_ODT[0]

DDR1_MA[3] DDR1_MA[4]

DDR1_DQSN[6] DDR1_DQSP[6] DDR1_DQSN[7] DDR1_DQSP[7]

DDR1_ALERT#

DDR1_PAR DRAM_RESET# DDR_RCOMP[0] DDR_RCOMP[1] DDR_RCOMP[2]

BK36 BM36 BD32 BF32

BN33 BK32 BG33 BH30

BM30 BJ33 BC35

BK30 BN31 BM32 BL37 BG31 BN37 BJ37 BJ35 BM34 BN35 BG37 BE37 BC37 BF34 BC33 BF30 BD36 BG35 BC31 BF36

BJ31 BK34

BD40 BF40 BD44 BF44 BK26 BM26 BM22 BK22 BK44 BM44 BM40 BK40

BD26 BF26 BF22 BD22 BD34 BD30 BP20 BF64 BJ64 BC64

M_CLK_B_DD R#0 M_CLK_B_DD R0 M_CLK_B_DD R#1 M_CLK_B_DD R1

DDR_B_CKE0 DDR_B_CKE1 DDR_B_CKE2 DDR_B_CKE3

DDR_B_CS0 # DDR_B_CS1 # DDR_B_ODT 0

DDR_B_CAA_0 DDR_B_CAA_1 DDR_B_CAA_2 DDR_B_CAA_3 DDR_B_CAA_4 DDR_B_CAA_5 DDR_B_CAA_6 DDR_B_CAA_7 DDR_B_CAA_8 DDR_B_CAA_9 DDR_B_CAB_0 DDR_B_CAB_1 DDR_B_CAB_2 DDR_B_CAB_3 DDR_B_CAB_4 DDR_B_CAB_5 DDR_B_CAB_6 DDR_B_CAB_7 DDR_B_CAB_8 DDR_B_CAB_9

DDR_B_DQS# 0 DDR_B_DQS0 DDR_B_DQS# 1 DDR_B_DQS1 DDR_B_DQS# 2 DDR_B_DQS2 DDR_B_DQS# 3 DDR_B_DQS3 DDR_B_DQS# 4 DDR_B_DQS4 DDR_B_DQS# 5 DDR_B_DQS5

DDR_B_DQS# 6 DDR_B_DQS6 DDR_B_DQS# 7 DDR_B_DQS7 DDR1_ALERT #

DDR3_DRAMR ST# SM_RCOMP0 SM_RCOMP1

SC03

0.1U_0201_ 16V6K

@ESD@

M_CLK_B_DD R#0 (20) M_CLK_B_DD R0 (20) M_CLK_B_DD R#1 (20) M_CLK_B_DD R1 (20)

DDR_B_CKE0 (20) DDR_B_CKE1 (20) DDR_B_CKE2 (20) DDR_B_CKE3 (20)

DDR_B_CS0 # (20) DDR_B_CS1 # (20) DDR_B_ODT 0 (20)

DDR_B_CAA_0 (20) DDR_B_CAA_1 (20) DDR_B_CAA_2 (20) DDR_B_CAA_3 (20) DDR_B_CAA_4 (20) DDR_B_CAA_5 (20) DDR_B_CAA_6 (20) DDR_B_CAA_7 (20) DDR_B_CAA_8 (20) DDR_B_CAA_9 (20) DDR_B_CAB_0 (20) DDR_B_CAB_1 (20) DDR_B_CAB_2 (20) DDR_B_CAB_3 (20) DDR_B_CAB_4 (20) DDR_B_CAB_5 (20) DDR_B_CAB_6 (20) DDR_B_CAB_7 (20) DDR_B_CAB_8 (20) DDR_B_CAB_9 (20)

DDR_B_DQS# 0 (20) DDR_B_DQS0 (20) DDR_B_DQS# 1 (20) DDR_B_DQS1 (20) DDR_B_DQS# 2 (20) DDR_B_DQS2 (20) DDR_B_DQS# 3 (20) DDR_B_DQS3 (20) DDR_B_DQS# 4 (20) DDR_B_DQS4 (20) DDR_B_DQS# 5 (20) DDR_B_DQS5 (20)

DDR_B_DQS6 (20) DDR_B_DQS# 7 (20) DDR_B_DQS7 (20)

T91 T87TP@ T274TP@

1 2

RC45 200_0402_1%

1 2

RC46 80.6_0402_1%

1 2

RC47 162_0402_1%

DDR3_DRAMR ST#

DDR1_ALERT #

A A

1 2

RC524 0_0201_5 %short@

2016-08-24 Modify-Follow TD team

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2041/09/08 2013/10/28

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

SKL Y(2/13) DDRIII

LA-F803P

6 55Friday, June 08, 2018

0.1

Functional Strap Definitions

GPP_C2 (Internal Pull Down): SMBALERT#

0 = Disable Intel ME Crypto Transport Layer Security

(TLS) cipher suite (no confidentiality).

1 = Enable Intel ME Crypto Transport Layer Security

(TLS) cipher suite (with confidentiality). Must be pulled up to support Intel AMT with TLS and Intel SBA (Small Business Advantage) with TLS.

+3V_PRIM

CLK_LPC _EC_R (29)

LPC_CLK RUN# (29)

RH101

2.2K_020 1_5%

SOC_SMB ALERT#

C LINK

SKYLAKE_ULX

LPC

5 OF 20

Rev0.87

GPP_C0/SMBCLK

GPP_C1/SMBDATA

GPP_C2/SMBALERT#

GPP_C3/SML0CLK

GPP_C4/SML0DATA

GPP_C5/SML0ALERT#

GPP_C6/SML1CLK

GPP_B23/SML1ALERT#/PCHHOT#

GPP_A14/SUS_STAT#/ESPI_RESET#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

GPP_C7/SML1DATA

GPP_A1/LAD0/ESPI_IO0 GPP_A2/LAD1/ESPI_IO1 GPP_A3/LAD2/ESPI_IO2 GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS#

GPP_A10/CLKOUT_LPC1

GPP_A8/CLKRUN#

AC12 W6 W8

W4 AC10 AA6

AA4 W10 BB6

BK11 BJ8 BG10 BP5 BP7 BJ6

BJ10 BF5 BH11

SOC_SMB ALERT#

SOC_SML 0CLK SOC_SML 0DATA GPP_C5

PCH_TBT _RST# TBT_W AKE# SOC_SML 1ALERT#

LPC_AD0

RC446 0_0201_ 5%LPC@

LPC_AD1

RC447 0_0201_ 5%LPC@

LPC_AD2

RC448 0_0201_ 5%LPC@

LPC_AD3

RC449 0_0201_ 5%LPC@

CLK_LPC _EC CLKOUT_ LPC1 LPC_CLK RUN#

SOC_SMB CLK (30) SOC_SMB DATA (30)

PCH_TBT _RST# (33) TBT_W AKE# (33)

1 2 1 2 1 2 1 2

1 2

RH20 22_0201 _5%EMI@

T23TP@

PIR29 SI: pop CH47

LPC_AD0 _R LPC_AD1 _R LPC_AD2 _R LPC_AD3 _R

CH47

RF@

68P_0201_50V8J

Connect TP

V: modify for RTD3

LPC_AD0 _R (29) LPC_AD1 _R (29) LPC_AD2 _R (29) LPC_AD3 _R (29)

LPC_FRA ME# (29)

CLK_LPC _EC_R

UC1E

50MHz

D D

T13 TP@ T369 TP@

WW AN_DISABLE#(26)

WW AN_PWRE N(26) CAMERA_ PWREN(26) WW AN_PREN(25 )

PV: control WWAN

To EC

T21 TP@ T22 TP@ T24 TP@

EC_KBRS T#(29) LPC_SER IRQ(29)

PCH_SPI_C LK PCH_SPI_S O PCH_SPI_S I PCH_SPI_IO2 PCH_SPI_IO3 PCH_SPI_C S0# PCH_SPI_C S1# PCH_SPI_C S2#

T15 TP@

WW AN_DISABLE# WW AN_PWRE N

T370 TP@

CL_CK CL_DATA CL_RST_ N

EC_KBRS T# LPC_SER IRQ

LPC Mode

AU10

SPI0_CLK

AU12

SPI0_MISO

AT3

SPI0_MOSI

AV11

SPI0_IO2

AV13

SPI0_IO3

AU4

SPI0_CS0#

AU6

SPI0_CS1#

AU8

SPI0_CS2#

GPP_D1

GPP_D2/SPI1_MISO

GPP_D3

W12

GPP_D21

GPP_D22

GPP_D0

F12

CL_CLK

D12

CL_DATA

B12

CL_RST#

BL10

GPP_A0/RCIN#

BN8

GPP_A6/SERIRQ

KBL-Y_BGA1515

SPI - FLASH SMBUS, SMLINK

SPI - TOUCH

Functional Strap Definitions

C C

+3V_PRIM +3.3 V_SPI

Closed to ROM

PCH_SPI_S I PCH_SPI_C LK

From CPU

EC_SPI_SO(29)

From EC

(For share ROM)

B B

EC_SPI_SI(29) EC_SPI_CL K_R(29) EC_SPI_CS #0(29)

PCH_SPI_S O PCH_SPI_IO2 PCH_SPI_IO3

EC_SPI_SO EC_SPI_SI EC_SPI_CL K_R EC_SPI_CS #0

RC454 33_02 01_5% RC455 33_02 01_5% RC456 33_02 01_5% RC457 33_02 01_5% RC539 33_02 01_5%

RC458 33_02 01_5% RC459 33_02 01_5% RC460 33_02 01_5% RC461 33_02 01_5%

EMI@

LPC@ LPC@ LPC@ LPC@

12 12 12 12 12

12 12 12 12

SPI_SI_VROM0 SPI_CLK_V ROM0 SPI_SO_VR OM0 SPI_IO2_VROM 0 SPI_IO3_VROM 0

SPI_SO_VR OM0 SPI_SI_VROM0 SPI_CLK_V ROM0 PCH_SPI_C S0#

To SPI ROM

16M SPI ROM(Support ISH)

PCH_SPI_C S0# SPI_SO_VR OM0 SPI_IO3_VROM 0 SPI_IO2_VROM 0 SPI_CLK_V ROM0

UC2

CS#

HOLD#_RESET#

WP#

GND

W25 Q128FVPIQ_W SON8_6X5

SA00007 XA10

ThemalPad

VCC

CLK

8 7 6

SPI_SI_VROM0

RH470

1 2

+3.3V_SP I

0_0402_ 5%@

CH35

0.1U_020 1_10V6K

GPP_B23 :SML1ALERT#

If USB 3.0 Port 1 is used for 4-wire DCI.OOB (BSSB), and

‧‧‧‧

alternate functionality is also used on the pin, pull up to V3.3S with >100K resistor to avoid noise.

If USB 3.0 Port 1 is used for DCI.OOB (BSSB) 4-wire

‧‧‧‧

BSSB, and NO alternate functionality is used, leave float.

If DCI.OOB (BSS B) 2+2 functio nality is used, pull up to

‧‧‧‧

V3.3S with a 4.7K resistor.

PIR24 SI: Change to 16M

GPP_C5 (Internal Pull Down): SML0ALERT#

0 = LPC Is selected for EC.

1 = eSPI Is selected for EC.

SOC_SML 1ALERT#

PCH_TBT _RST# TBT_W AKE#

SOC_SML 0CLK SOC_SML 0DATA

SOC_SMB CLK SOC_SMB DATA

+3V_PRIM

RH102 4.7K_040 2_5%

RH96 10K_020 1_5%@ RH97 10K_020 1_5%

RH99 1K_0201 _5% RH100 1K_0201 _5%

RH94 1K_0201 _5% RH95 1K_0201 _5%

RH98

10K_020 1_5%

1 2

1 2 1 2

GPP_C5

+3V_PRIM

+3VS

LPC_CLK RUN#

LPC_SER IRQ

A A

Security Class ification

2041/09/ 08 2013/10/ 28

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2041/09/ 08 2013/10/ 28

Compal Secret Data

Deciphered Date

EC_KBRS T#

Compal Electronics, Inc.

Title

Size Document N umber Rev

Date: Sheet of

Compal Electronics, Inc.

SKL Y(3/13) SPI,SMB

LA-F803P

1 2

RH13 8.2K_020 1_5%

1 2

RH472 10K_020 1_5%

1 2

RH473 10K_020 1_5%

7 55Friday, June 08, 201 8

0.1

AUDIO

<+3V_1.8V_PGPPD>

EMI@

12 12 12

SKYLAKE_ULX

7 OF 20

SDIO/SDXC

GPP_A17/SD_PWR_EN#/ISH_GP7

MP@

CC171

2.2P_0201_25V

GPP_G0/SD_CMD GPP_G1/SD_DATA0 GPP_G2/SD_DATA1 GPP_G3/SD_DATA2 GPP_G4/SD_DATA3

GPP_G5/SD_CD# GPP_G6/SD_CLK

GPP_G7/SD_WP

GPP_A16/SD_1P8_SEL

SD_RCOMP

HDA_BIT_C LK HDA_SYNC HDA_SDO UT HDA_RST #

RF@

CC140

10P_0201_25V8

CC170

HDA_SDIN0

Rev0.87

GPP_F23

AH9 AH11 AG12 AF9 AF11 AG8 AG10 AE12

BL4 BN4

BF1

AJ8

SDIO_RCOM P

RC60 200_020 1_1%

561280_KBL UY PDG Rev2_0 if SDXC interface is not used, the SD_RCOMP pin does not need to be connected to a RCOMP resistor.

To Enable ME Override

ME_EN(29)

+3V_HDA

1 2

RC500 1K _0201_1%

VGS(Max) : <1.5 V

HDA_SDO / I2S0_TXD (Internal Pull Down)(Primary well): Flash Descriptor Security Override 0 = Enable (Default) 1 = Disable (Override) The internal pull-down is disabled after PCH_PWROK is High.

QC1 PJE138K 1N SOT-523-3

1 2

RC501 100K_0201_5 %

1 2

RC507 0_0201_ 5%@

HDA_SDO UT

UC1G

A00_0906: EMI Request RH109 33chnage 56ohm

HDA_SYNC HDA_BIT_C LK HDA_SDO UT HDA_SDIN0

HDA_RST #

D D

Camera

RTD3_US B_PWR_EN(33)

WLA N_TRANSMIT_OFF#(23)

T30 TP@

BT_ON(23 )

T127 TP@

SOC_DMIC_ CLK0(22) SOC_DMIC_ DATA0(22)

AUDIO_PW REN(39)

WW AN_ASPM_CT RL(26)

SPKR(27)

RTD3_US B_PWR_EN

WLA N_TRANSMIT_OFF#

SOC_GPIOF 0

BT_ON

SOC_GPIOF 3

SOC_DMIC_ CLK0 SOC_DMIC_ DATA0

AUDIO_PW REN WW AN_ASPM_CT RL

SPKR

BJ19

HDA_SYNC/I2S0_SFRM

BK18

HDA_BLK/I2S0_SCLK

BK16

HDA_SDO/I2S0_TXD

BL15

HDA_SDI0/I2S0_RXD

BL17

HDA_SDI1/I2S1_RXD

BL19

HDA_RST#/I2S1_SCLK

GPP_D23/I2S_MCLK

BL12

I2S1_SFRM

BK14

I2S1_TXD

AT13

GPP_F1/I2S2_SFRM

AT11

GPP_F0/I2S2_SCLK

AP11

GPP_F2/I2S2_TXD

AT5

GPP_F3/I2S2_RXD

GPP_D19/DMIC_CLK0

V11

GPP_D20/DMIC_DATA0

U12

GPP_D17/DMIC_CLK1

GPP_D18/DMIC_DATA1

AV3

GPP_B14/SPKR

KBL-Y_BGA1515

Functional Strap Definitions

GPP_B14 (Internal Pull Down): SPKR TOP Swap Override 0 = Disable TOP Swap mode.---> AAU30 Use 1 = Enable TOP Swap Mode.

C C

+3V_PRIM

RC83

1 2

100K_02 01_5%

RTD3_US B_PWR_EN

SPKR

+3V_PRIM

1 2

RC577 49 .9K_0201_1%

HDA for AUDIO

HDA_BIT_C LK_R(27) HDA_SYNC_ R(27) HDA_SDO UT_R(27) HDA_RST #_R(27)

HDA_SDIN0(27)

RC462 33_0201 _5% RC463 33_0201 _5% RC464 33_0201 _5% RC499 33_0201 _5%

UC1I

G30

G32

H29 F29 F33 H33

D29 B29 C32 A32 C30 A30 D33 B33

D35 B35 C36 A36 D37 B37 C38 A38

J30

J32

CSI2_DN0 CSI2_DP0 CSI2_DN1 CSI2_DP1 CSI2_DN2 CSI2_DP2 CSI2_DN3 CSI2_DP3

CSI2_DN4 CSI2_DP4 CSI2_DN5 CSI2_DP5 CSI2_DN6 CSI2_DP6 CSI2_DN7 CSI2_DP7

CSI2_DN8 CSI2_DP8 CSI2_DN9 CSI2_DP9 CSI2_DN10 CSI2_DP10 CSI2_DN11 CSI2_DP11

KBL-Y_BGA1515

B B

A A

SKYLAKE_ULX

CSI-2

eMMC

GPP_F13/EMMC_DATA0 GPP_F14/EMMC_DATA1 GPP_F15/EMMC_DATA2 GPP_F16/EMMC_DATA3 GPP_F17/EMMC_DATA4 GPP_F18/EMMC_DATA5 GPP_F19/EMMC_DATA6 GPP_F20/EMMC_DATA7

GPP_F21/EMMC_RCLK

GPP_F12/EMMC_CMD

9 OF 20

Rev0.87

CSI2_CLKN0

CSI2_CLKP0

CSI2_CLKN1

CSI2_CLKP1

CSI2_CLKN2

CSI2_CLKP2

CSI2_CLKN3

CSI2_CLKP3 CSI2_COMP

GPP_D4/FLASHTRIG

GPP_F22/EMMC_CLK

EMMC_RCOMP

H31 F31 D31 B31 C34 A34 D39 B39 A11 N4

AN12 AP9 AN10 AJ10 AM9 AL12 AJ12 AN8

AL10 AL8 AM11

BC1

CSI2_COMP

RAM_ID0 RAM_ID1 RAM_ID2

EMMC_RC OMP

RC64 100_020 1_1%

RC61 200_020 1_1%

Security Class ification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

RAM ID

DDR Memory Configuratino Type Strap pin

+1.8V_PR IM

1K_0201_1%

RC138

RAM_ID0 RAM_ID1 RAM_ID2

2041/09/ 08 2013/10/ 28

1 2

1K_0201_1%

RC509

1 2

Compal Secret Data

1K_0201_1%

RC510

1 2

1K_0201_1%

RC508

1 2

Deciphered Date

RC511

1 2

RC512

1 2

L01

L02

L04

RAM_ID2/1/0

000

001

010

011L03 Micron 16G

P/N DescribtionConfig

S IC D3 512M64 Micron 8G LPDDR3L

Hynix 8G LPDDR3L

SAMSUNG 8GB LPDDR3L

LPDDR3L

Micron 8GB LPDDR3L

Hynix 4GB LPDDR3L

SAMSUNG 4GB LPDDR3L

R1 SA00009Z800

R1 SA000092J20

R1 SA00009DC00

SA0000C1800

R3 SA00009Z810

R3 SA000092J30

R3 SA00009DC10

Title

SKL Y(4/13) HDA,EMMC,SDIO

Size Document N umber Rev

LA-F803P

Date: Sheet of

Date: Sheet

MT52L512M64D4PQ-107WT:B

S IC D3 32G/1866

H9CCNNNCPTALBR-NUD

FBGA

S IC D3 32G/1866

K3QF4F40BM-AGCF

FBGA

S IC D3 64G/1866

MT52L1G64D8QC-107 WT:B

S IC D3

MT52L512M64D4PQ-107WT:B

A32!

S IC D3 32G/1866

H9CCNNNCPTALBR-NUD

FBGA A32 !

S IC D3 32G/1866

K3QF4F40BM-AGCF

A32 !

Compal Electronics, Inc.

Matched ResisterSKU

RC509 RC508 RC512

RC138

RC509 RC510 RC512

8 55Friday, June 08, 201 8

RC508 RC512

RC512RC510RC138R1

0.1

+3VL_RT C

1 2

RC514 20K_0 201_5%

1 2

CC6 1U_0201_6 .3V6M

1 2

CLRP1 S HORT PADS

1 2

D D

+3VS

+3V_PRIM

C C

+3VALW _DSW

B B

RC513 20K_0 201_5%

1 2

CC277 1U_02 01_6.3V6M

1 2

CLRP2 S HORT PADS

1 2

RC54 1M_020 1_5%

1 2

RC474 10K_020 1_5%@

1 2

RC475 10K_020 1_5%

1 2

RC476 10K_020 1_5%

1 2

RC477 10K_020 1_5%@

1 2

RC478 10K_020 1_5%

1 2

RH114 10K_020 1_5%@

1 2

RH208 10K_020 1_5%

1 2

RH132 10K_020 1_5%

1 2

RH44 100K_02 01_5%

1 2

RH115 10K_020 1_5%

1 2

RH210 10K_020 1_5%

1 2

RH117 10K_020 1_5%

1 2

RH82 10K_020 1_5%

1 2

RH471 1K_0201 _5%

1 2

RH68 2.2K_020 1_5%

1 2

RH50 100K_02 01_5%

1 2

RH49 10K_020 1_5%

1 2

CC278 100P_02 01_50V8J

ESD@

PCH_SUS WARN#(29)

SOC_SRT CRST#

SOC_RTC RST#

SM_INTRUD ER#

CLKREQ_ PCIE#1

CLKREQ_ PCIE#2

CLKREQ_ PCIE#3

CLKREQ_ PCIE#4

PCH_SUS WARN# VRALERT #

SYS_RESET #

PCH_PW ROK

AC_PRES ENT_R PCH_GPD 11 BATLOW # LAN_W AKE# SOC_PCIE_ WAKE# PBTN_OU T#_R

PCH_DPW ROK_R EC_RSMR ST#

SUSACK#(29 )

CLR ME

CLR CMOS

Wireless LAN

CLKREQ_PCIE#3 use PU RN19.

CLRP4 SHORT PA DS

1 2

RH60 0_0201_ 5%short@

PV: remove TBT_WAKE#

PBTN_OU T#(29 )

ACIN(29)

DPWR OK_EC(29 )

A A

RC516 0_020 1_5%

RC515 0_020 1_5%

RC69 0_0 201_5%

PBTN_OU T#_R

AC_PRES ENT_R

PCH_DPW ROK_R

RH66

1K_0201 _5%

R03_0629 For Thermal diode placement del UH2 RH4

EC_VCCS T_PG_R(29)

WWAN

VMe SSD

PLT_RST#(22,23,24,29,31,33)

EC_RSMR ST#(29)

SYS_PW ROK(29) PCH_PW ROK(29 )

+1.0V_VC CST

SYS_RESET #

TC67 @

RC79

1 2

60.4_040 2_1%

CLK_PCIE_ N1(26) CLK_PCIE_ P1(26 ) CLKREQ_ PCIE#1(26)

CLK_PCIE_ N2(24) CLK_PCIE_ P2(24 ) CLKREQ_ PCIE#2(24)

CLK_PCIE_N3(23) CLK_PCIE_P3(23)

CLKREQ_ PCIE#3(23)

CLK_PCIE_N4(33) CLK_PCIE_P4(33)

CLKREQ_ PCIE#4(33)

+3VS

T33 TP@ T34 TP@

1 2

RC75 10K_020 1_5%@

CLK_PCIE_ N1 CLK_PCIE_ P1 CLKREQ_ PCIE#1

CLK_PCIE_ N2 CLK_PCIE_ P2 CLKREQ_ PCIE#2

CLK_PCIE_ N3 CLK_PCIE_ P3 CLKREQ_ PCIE#3

CLK_PCIE_ N4 CLK_PCIE_ P4 CLKREQ_ PCIE#4

CLK_PCIE_ N5CLKREQ_ PCIE#5 CLK_PCIE_ P5 CLKREQ_ PCIE#5

D15

2 1

H35

F35

AV9

J36

G36

BD10

J38 G38 AV5

H37

F37 AV7

H39

F39 BC5

BB10

KBL-Y_BGA1515

D16

RB751S4 0T1G_SOD523-2

PCH_PW ROKEC_RSMR ST#

RB751S4 0T1G_SOD523-2

PV: D15,D16 pop

+3V_PRIM

TC7SH08 FU_SSOP5

UH1

BB8

BJ12

A62 B61

BP14 BN15

BL6 BF9

BP9 BE15 BC15 BB16

RH46

100K_02 01_5%

PCH_PLT RST# SYS_RESET # EC_RSMR ST#

H_CPUPW RGD_R EC_VCCS T_PG

PCH_PW ROK PCH_DPW ROK_R

PCH_SUS WARN# SUSACK# _R

SOC_PCIE_ WAKE# LAN_W AKE# PCH_GPD 11

PDG_DPWROK connect to VccDSW3_3 power rail monitoring circuit to support Deep Sx state.This signal can be tied to RSMRST# for platforms that do not support the Deep Sx state.The DSW rails must be stable for at least 10 ms before DPWROK is asserted to PCH.

PDG_SUSACK#, this signal is driven from the platform EC to PCH to acknowledge that EC has received the SUSWARN# signals and it is preparing to go into DeepSx mode.for at least 10 ms before DPWROK is asserted to PCH.

PDG_SLP_SUS#, a low on this signal indicates that PCH is in Deep Sx state and that EC/platform logic does not need to keep the Primary Rails ON.

EC_VCCS T_PG

PCH_PLT RST#

UC1K

GPP_B13/PLTRST# SYS_RESET# RSMRST#

PROCPWRGD VCCST_PWRGD

SYS_PWROK PCH_PWROK DSW_PWROK

GPP_A13/SUSWARN#/SUSPWRDNACK GPP_A15/SUSACK#

WAKE# GPD2/LAN_WAKE# GPD11/LANPHYPC GPD7/RSVD

KBL-Y_BGA1515

Security Class ification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SKYLAKE_ULX

SYSTEM POWER MANAGEMENT

11 OF 20

2041/09/ 08 2013/10/ 28

UC1J

CLKOUT_PCIE_N1 CLKOUT_PCIE_P1 GPP_B6/SRCCLKREQ1#

CLKOUT_PCIE_N2 CLKOUT_PCIE_P2 GPP_B7/SRCCLKREQ2#

CLKOUT_PCIE_N3 CLKOUT_PCIE_P3 GPP_B8/SRCCLKREQ3#

CLKOUT_PCIE_N4 CLKOUT_PCIE_P4 GPP_B9/SRCCLKREQ4#

CLKOUT_PCIE_N5 CLKOUT_PCIE_P5 GPP_B10/SRCCLKREQ5#

GPP_B5/SRCCLKREQ0#

XTAL24_ OUT

XTAL24_ IN

GPP_B11/EXT_PWR_GATE#

Compal Secret Data

SKYLAKE_ULX

CLOCK SIGNALS

10 OF 20

PWR_ 3V5V_PG (43)

1 2

RC50

EMI@

33_0201 _1%

1 2

RC195

EMI@

33_0201 _1%

Rev0.87

GPP_B12/SLP_S0#

GPD4/SLP_S3# GPD5/SLP_S4#

GPD10/SLP_S5#

SLP_SUS# SLP_LAN#

GPD9/SLP_WLAN#

GPD6/SLP_A#

GPD3/PWRBTN#

GPD1/ACPRESENT

GPD0/BATLOW#

GPP_A11/PME#

INTRUDER#

GPP_B2/VRALERT#

SLP_W LAN#

Deciphered Date

CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P

XTAL24_ OUT_R

XTAL24_ IN_R

CC8

BC9 AY14 BF16 BH14

BN10 BP11 BH16 BE17

BF14 BD14 BD16

BF7 BG19

BC7 BD6

Rev0.87

GPD8/SUSCLK

XTAL24_IN

XTAL24_OUT

XCLK_BIASREF

RTCX1 RTCX2

SRTCRST#

RTCRST#

22P_0402_50V8J

PM_SLP_ S0# PM_SLP_ S3# PM_SLP_ S4# PM_SLP_ S5#

SLP_SUS # SLP_LAN # SLP_W LAN# PM_SLP_ A#

PBTN_OU T#_R AC_PRES ENT_R BATLOW #

SM_INTRUD ER#

VRALERT #

J34 G34

BA15

M1 L2

BN19 BP18

BH18 BN12

1 2

RC563 1M_0402 _1%

YC1

X'tal

24MHZ_8 PF_8Y24080002

SJ10000 PS00

TC11@

SUSCLK_ S

XTAL24_ IN XTAL24_ OUT

XCLK_BIAS REF

PCH_RTC X1 PCH_RTC X2

SOC_SRT CRST# SOC_RTC RST#

RH76

1 2

0_0402_ 5%

RH78

1 2

2.7K_020 1_1%

SUSCLK

+1.0V_PR IM

SOC_SRT CRST# (29 ) SOC_RTC RST# (29)

CH46

0.1U_0201_10V6K

RTC_RST# by PWR BTN

PCH_RTC X2

PCH_RTC X1

1 2

RC58 10M_0402_5 %

1 2

YC2

PM_SLP_ S0# (11,12,29,47,49) PM_SLP_ S3# (12,29,33,39) PM_SLP_ S4# (21,29)

TP@

SLP_SUS # (29) TP@ SLP_W LAN# (23)

TC63@

22P_0402_50V8J

CC7

T392

T35

T395TP@

Title

SKL Y(5/13) CLK,GPIO

Size Document N umber Rev

LA-F803P

Date: Sheet of

Date: Sheet

PDG_ internal pull-up resistor, nterna 16 ms de-bounce on the input.

Compal Electronics, Inc.

6.8P_0402_50V8C

CC14

SJ10000 SK00

32.768KH Z_9PF

SUSCLK (23)

@EMI@

6.8P_0402_50V8C

CC12

0.1

9 55Friday, June 08, 201 8

UC1F

Strap Pin

BC3

GPP_B15/GSPI0_CS#

AW10

GPP_B16/GSPI0_CLK

AW6

GPP_B17/GSPI0_MISO

BB4

GPP_B18/GSPI0_MOSI

BB2

GPP_B19/GSPI1_CS#

AW12

GPP_B20/GSPI1_CLK

AW4

GPP_B21/GSPI1_MISO

AW8

GPP_B22/GSPI1_MOSI

AC8

GPP_C8/UART0_RXD

AA8

GPP_C9/UART0_TXD

AA10

GPP_C10/UART0_RTS#

AA12

GPP_C11/UART0_CTS#

AD5

GPP_C20/UART2_RXD

AD7

GPP_C21/UART2_TXD

AD3

GPP_C22/UART2_RTS#

AD9

GPP_C23/UART2_CTS#

AD11

GPP_C16/I2C0_SDA

AB3

GPP_C17/I2C0_SCL

AB9

GPP_C18/I2C1_SDA

AB11

GPP_C19/I2C1_SCL

AP3

GPP_F4/I2C2_SDA

AP7

GPP_F5/I2C2_SCL

AP5

GPP_F6/I2C3_SDA

AT7

GPP_F7/I2C3_SCL

AN4

GPP_F8/I2C4_SDA

AN6

GPP_F9/I2C4_SCL

KBL-Y_BGA1515

Functional Strap Definitions

GPP_B22 (Internal Pull Down): GSSPI1_MOSI Boot BIOS Strap Bit 0 = SPI Mode --> AAU30 Use 1 = LPC Mode

PV: delete TS_STOP#_PCH

GPP_B18

D D

WW AN_WAKE #(26)

PV: delete TS_PWREN_PCH

TBT_CIO_P LUG_EVENT#(33)

To TBT.

Track Pad (Reserved)

Touch Screen

C C

+3V_PRIM

B B

TBT_FOR CE_PWR(33)

PM_BATL OW#(33)

RTD3_CIO_ PWR_EN(33)

I2C_0_SDA(30) I2C_0_SCL(30)

I2C_1_SDA _TS(22) I2C_1_SCL _TS(22)

COEX1(23,26)

COEX2(23,26) COEX3(23,26)

PIR1 SI: PU 10Kohm

PV: change PU +3V_PRIM

1 2

RC580 10K_020 1_5%

1 2

RC200 49.9K_02 01_1%

1 2

RC201 49.9K_02 01_1%

PV: delete TS_STOP#_PCH PV: delete TS_PWREN_PCH

WW AN_WAKE #

GPP_B22

UART_2_ CRXD_DTXD UART_2_ CTXD_DRXD

I2C_0_SDA I2C_0_SCL

I2C_1_SDA _TS I2C_1_SCL _TS

PM_BATL OW# UART_2_ CRXD_DTXD UART_2_ CTXD_DRXD

Functional Strap Definitions

GPP_B18 (Internal Pull Down): GSSPIO_MOSI No Reboot 0 = Disable No Reboot mode. --> AAU30 Use 1 = Enable No Reboot Mode. (PCH will disable the TCO

Timer system reboot feature). This function is useful when running ITP/XDP.

+3V_PRIM +3V_PRIM

RC84

1 2

150K_02 01_5%

GPP_B18 GPP_B22

SKYLAKE_ULX

1.8V

6 OF 20

+3V_PRIM

DMN63D8 LV-7_SOT563-6

RC85

1 2

150K_02 01_5%

ISHLPSS

GPP_D5/ISH_I2C0_SDA

GPP_D6/ISH_I2C0_SCL

GPP_D7/ISH_I2C1_SDA

GPP_D8/ISH_I2C1_SCL

GPP_F10/I2C5_SDA/ISH_I2C2_SDA

1.8V

GPP_F11/I2C5_SCL/ISH_I2C2_SCL

GPP_D13/ISH_UART0_RXD/SML0BDATA

GPP_D14/ISH_UART0_TXD/SML0BCLK

GPP_D16/ISH_UART0_CTS#/SML0BALERT#

Sx_EXIT_HOLDOFF# / GPP_A12 / BM_BUSY#/ISH_GP6

QC4

GPP_D15/ISH_UART0_RTS#

GPP_C12/UART1_RXD/ISH_UART1_RXD

GPP_C13/UART1_TXD/ISH_UART1_TXD GPP_C14/UART1_RTS#/ISH_UART1_RTS# GPP_C15/UART1_CTS#/ISH_UART1_CTS#

GPP_A18/ISH_GP0 GPP_A19/ISH_GP1 GPP_A20/ISH_GP2 GPP_A21/ISH_GP3 GPP_A22/ISH_GP4 GPP_A23/ISH_GP5

ISH_I2C_0_SC L_R

ISH_I2C_0_SD A_R

Rev0.87

GPP_D9 GPP_D10 GPP_D11 GPP_D12

P11 T7 T5 T11

ISH_I2C_0_SD A_R

ISH_I2C_0_SC L_R

T9 T3

AM7 AT9

U10 U4 U6 V9

AC6 AC4 AB7 AB5

BF11 BD2 BJ1 BL3 BJ3 BD4 BJ4

ISH_I2C_0_SC L (26)

TC41@ TC42@

DDR_CHB _EN DDR_CHA _EN BID_BC

NGFF_SS D_WAKE# NGFF_SS D_PWREN

INT1_A_G WW AN_RESET# INT2_A_G

To Sub/B (In +3VALW plan)

ISH_I2C_0_SD A (26)

MUX_DCI_C LK (37) MUX_DCI_D AT (37)

9x-Sensor,

NGFF_SS D_WAKE# (24 )

NGFF_SS D_PWREN (24)

INT1_A_G (26) WW AN_RESET# (26) INT2_A_G (26)

V: change pin define from GPP_F4 to GPP_A19

WW AN_WAKE # NGFF_SS D_WAKE# DDR_CHA _EN DDR_CHB _EN INT1_A_G INT2_A_G

DDR_CHA _EN DDR_CHB _EN

ISH_I2C_0_SD A_R

ISH_I2C_0_SC L_R

RTD3_CIO_ PWR_EN

TBT_CIO_P LUG_EVENT#

WW AN_WAKE #

ACCEL2

PIR5 PV: Add PU 10Kohm

IR6 PV: PU +3V_PRIM 10K

+3V_PRIM

RH142 100K_02 01_5%

BID_BC

1 2

RC572 10K_020 1_5%@

1 2

RC570 10K_020 1_5%@

1 2

RH140 100K_0 201_5%

1 2

RH141 100K_0 201_5%

1 2

RC441 10K_020 1_5%

1 2

RC440 10K_020 1_5%

1 2

RH61 SH ORT PADS@

1 2

RH65 SH ORT PADS@

1 2

RC78 1K_ 0201_5%

1 2

RC503 1K_0 201_5%

1 2

RC145 10K_ 0201_5%

1 2

RC582 10K_ 0201_5%

1 2

RC583 10 K_0201_5%

1 2

RH143 100K_02 01_5%

1 2

+3V_PRIM

+3VS

A A

Security Class ification

2041/09/ 08 2013/10/ 28

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2041/09/ 08 2013/10/ 28

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document N umber Rev

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

SKL Y(6/13) GPIO,LPIO,I2C

LA-F803P

10 55Friday, June 08, 20 18

0.1

UC1H

PCIE_CRX_ TTX_N1(33)

D D

Alpine Ridge PCIe Gen3 x 4

NVMe SSD (PICe Interface)

M.2 SSD PCIe Gen3 x 4

C C

WWAN

WLAN PCIe Gen2 x 1

B B

PCIE_CRX_ TTX_P1(33) PCIE_CTX_ TRX_N1(33) PCIE_CTX_ TRX_P1(33)

PCIE_CRX_ TTX_N2(33) PCIE_CRX_ TTX_P2(33) PCIE_CTX_ TRX_N2(33) PCIE_CTX_ TRX_P2(33)

PCIE_CRX_ TTX_N3(33) PCIE_CRX_ TTX_P3(33) PCIE_CTX_ TRX_N3(33) PCIE_CTX_ TRX_P3(33)

PCIE_CRX_ TTX_N4(33) PCIE_CRX_ TTX_P4(33) PCIE_CTX_ TRX_N4(33) PCIE_CTX_ TRX_P4(33)

PCIE_CRX_ DTX_N5(24) PCIE_CRX_ DTX_P5(24) PCIE_CTX_ DRX_N5(24) PCIE_CTX_ DRX_P5(24)

PCIE_CRX_ DTX_N6(24) PCIE_CRX_ DTX_P6(24) PCIE_CTX_ DRX_N6(24) PCIE_CTX_ DRX_P6(24)

PCIE_CRX_ DTX_N7(24) PCIE_CRX_ DTX_P7(24) PCIE_CTX_ DRX_N7(24) PCIE_CTX_ DRX_P7(24)

PCIE_CRX_ DTX_N8(24) PCIE_CRX_ DTX_P8(24) PCIE_CTX_ DRX_N8(24) PCIE_CTX_ DRX_P8(24)

PCIE_CRX_ DTX_N9(25) PCIE_CRX_ DTX_P9(25) PCIE_CTX_ DRX_N9(26) PCIE_CTX_ DRX_P9(26)

PCIE_CRX_ DTX_N10(23) PCIE_CRX_ DTX_P10(2 3) PCIE_CTX_ DRX_N10(23 ) PCIE_CTX_ DRX_P10(23)

1 2

RC88 100_ 0201_1%

PCIE_RCOM PN PCIE_RCOM PP

PCH_GPIOA 7

C20

PCIE1_RXN/USB3_5_RXN

A20

PCIE1_RXP/USB3_5_RXP

G20

PCIE1_TXN/USB3_5_TXN

J20

PCIE1_TXP/USB3_5_TXP

B19

PCIE2_RXN/USB3_6_RXN

D19

PCIE2_RXP/USB3_6_RXP

F19

PCIE2_TXN/USB3_6_TXN

H19

PCIE2_TXP/USB3_6_TXP

C22

PCIE3_RXN

A22

PCIE3_RXP

G22

PCIE3_TXN

J22

PCIE3_TXP

B21

PCIE4_RXN

D21

PCIE4_RXP

F21

PCIE4_TXN

H21

PCIE4_TXP

C24

PCIE5_RXN

A24

PCIE5_RXP

G24

PCIE5_TXN

J24

PCIE5_TXP

B23

PCIE6_RXN

D23

PCIE6_RXP

F23

PCIE6_TXN

H23

PCIE6_TXP

C26

PCIE7_RXN/SATA0_RXN

A26

PCIE7_RXP/SATA0_RXP

G26

PCIE7_TXN/SATA0_TXN

J26

PCIE7_TXP/SATA0_TXP

B25

PCIE8_RXN/SATA1A_RXN

D25

PCIE8_RXP/SATA1A_RXP

F25

PCIE8_TXN/SATA1A_TXN

H25

PCIE8_TXP/SATA1A_TXP

C28

PCIE9_RXN

A28

PCIE9_RXP

G28

PCIE9_TXN

J28

PCIE9_TXP

B27

PCIE10_RXN

D27

PCIE10_RXP

F27

PCIE10_TXN

H27

PCIE10_TXP

PCIE_RCOMPN

B10

PCIE_RCOMPP

D51

PROC_PRDY#

B55

PROC_PREQ#

BF3

GPP_A7/PIRQA#

KBL-Y_BGA1515

PCIE/USB3/SATA

SKYLAKE_ULX

8 OF 20

SSIC / USB3

USB3_2_RXN/SSIC_1_RXN

USB3_2_RXP/SSIC_RXP USB3_2_TXN/SSIC_TXN

USB3_2_TXP/SSIC_TXP

USB3_3_RXP/SSIC_2_RXP

USB2

GPP_E10/USB2_OC1# GPP_E11/USB2_OC2# GPP_E12/USB2_OC3#

GPP_E0/SATAXPCIE0/SATAGP0 GPP_E1/SATAXPCIE1/SATAGP1 GPP_E2/SATAXPCIE2/SATAGP2

Rev0.87

USB3_1_RXN USB3_1_RXP USB3_1_TXN USB3_1_TXP

USB3_3_RXN

USB3_3_TXN USB3_3_TXP

USB3_4_RXN USB3_4_RXP USB3_4_TXN USB3_4_TXP

USB2N_1 USB2P_1

USB2N_5 USB2P_5

USB2N_7 USB2P_7

USB2N_3 USB2P_3

USB2N_9 USB2P_9

USB2N_2 USB2P_2

USB2_COMP

USB2_ID

USB2_VBUSSENSE

GPP_E9/USB2_OC0#

GPP_E4/DEVSLP0 GPP_E5/DEVSLP1 GPP_E6/DEVSLP2

GPP_E8/SATALED#

C16 A16 G16 J16

B15 D15 F15 H15

C18 A18 G18 J18

B17 D17 F17 H17

AJ6 AJ4

AH5 AH3

AF5 AF3

AL6 AL4

AG6 AG4

AM3 AM5

N2 AF7 AE6

N12 M11 F8 B8

F10 H10 L8

G11 J11 N10

USB3_CR X_DTX_N1 USB3_CR X_DTX_P1 USB3_CT X_DRX_N1 USB3_CT X_DRX_P1

USB3.1 Type-C Full function (SUB/B)

USB2_CO MP USB_ID USB2_VB USSENSE

USB_OC0 # USB_OC1 # USB_OC2 # PRIM_CORE _OPT

USB_OC0 # USB_OC1 # USB_OC2 # PRIM_CORE _OPT DEVSLP1 SATA_GP 0

PCH_GPIOA 7 SATA_GP 2

USB_ID USB2_VB USSENSE

RC87 113 _0402_1%

DEVSLP0 DEVSLP1

SATA_GP 0 SATA_GP 1 SATA_GP 2

+3V_PRIM

1 2

RC203 0_0201_ 5%@

1 2

RC204 0_0201_ 5%@

USB3_CR X_DTX_N3 (37)

USB3_CR X_DTX_P3 (37)

USB3_CT X_DRX_N3 (37)

USB3_CT X_DRX_P3 (37)

USB20_N 1 (35,38) USB20_P 1 (35,38)

USB20_N 5 (35,38) USB20_P 5 (35,38)

USB20_N 7 (36) USB20_P 7 (36)

USB20_N 3 (23) USB20_P 3 (23)

USB20_N 9 (26) USB20_P 9 (26)

1 2

T60 T P@

DEVSLP1 (24)

SATA_GP 1 (24)

T371 TP@

1 2

RH122 10K_020 1_5%

1 2

RH123 10K_020 1_5%

1 2

RH124 10K_020 1_5%

1 2

RH125 10K_020 1_5%

1 2

RH155 10K_020 1_5%

1 2

RH469 10K_020 1_5%

PIR11 SI: pop RH125

1 2

RC90 10K_020 1_5%

1 2

RC569 10K_020 1_5%@

1 2

RH153 1K_0201 _5%

1 2

RH154 1K_0201 _5%

USB3.1 Type-C

Bluetooth

IR Camera

for SATA SSD

+3V_PRIM

+3VS

PIR26 SI: pop UH3 , un-pop RC579

PRIM_CORE _OPT

PM_SLP_ S0#(9,12,29,47 ,49)

A A

Security Class ification

2041/09/ 08 2013/10/ 28

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2041/09/ 08 2013/10/ 28

Compal Secret Data

Deciphered Date

PM_SLP_ S0#

Title

Size Document N umber Rev

Date: Sheet of

UH3

INA

INB

MC74VHC 1G32DFT2G_SC 70-5

RC579 0_0201_ 5%@

SKL Y(7/13) PCIE,USB

LA-F803P

Compal Electronics, Inc.

PRIM_CORE _LPM (4 8)

11 55Friday, June 08, 20 18

0.1

CC314

1.8P_0201_50V8J

1U_0201_6.3V6M

RF@

C285

+0.85VS_ VCCIO +1.2V_VD DQ +3VALW +3V_PRIM +1.0V_VC CST

+1.0V_PR IM +1.0VS_V CCSTG

68P_0201_50V8J

CC387

RF@

0.1U_0201_10V6K CC357

@RF@

0.1U_0201_6.3V6K

CC388

RF@

0.1U_0201_10V6K CC358

@RF@

VOUT VOUT

GND GND

+0.85VS_ VCCIO(5,18,47) +1.2V_VD DQ(18,19,20,21,44) +3VALW(13,23,24,2 5,28,29,30,33,34,38 ,39,43,44,45,47,48 ,49,50) +3V_PRIM(5,7,8,9,10,1 1,13,24,25,26,29,30 ,33) +1.0V_VC CST(5,9,1 4,49)

+1.0V_PR IM(9 ,13,17,46) +1.0VS_V CCSTG(5 ,14)

7 8

1000P_0 402_50V7K

5 9

CC315

1 2

+3V_PRIM

0.1U_0402_25V6

CC316

PIR30 SI: pop CC387,CC388

+1.0V_VC CST

0.1U_0201_10V6K C279

+1.2V_VD DQ

D D

VDDQC trace filter width = 6mm Total etch length = 186.94mils PDG P597

+1.2V_VD DQ

VCCST : Sustain voltage for processor standby modes

VCCSTG : Gated sustain voltage for processor standby modes

C C

BSC Side

0.1U_020 1_10V6K

+1.0V_VC CST

RC106 0_0201_ 5%short@

CC280

+1.0V_VC CPLL

1 2

CC17

0.1U_020 1_10V6K

LC1

1 2

1NH +-0.3N H HCI1005F-1N0S

+VDDQ_C PU_CLK

CC9

0.1U_020 1_10V6K

Backside cap

+1.0VS_V CCSTG

+1.2V_VC CPLL_OC

+1.0V_VC CPLL

+1.0V_VC CST

AH64 BA27 BA37 BA49 BP32 BP50 AK64 BA29 BA41 BA51 BP34 BP56

AT64 BA31 BA43 BN64 BP40 BP58 AV64 BA33 BA45 BP24 BP42 BP64 BA25 BA35 BA47 BP26 BP48 BA39

AE27

AF27

V26 Y26

R26 T26

R27 T27

KBL-Y_BGA15 15

SKYLAKE_ULX

UC1N

VDDQ VDDQ

1.2V@ 2A

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQC

VCCST

1.0V@100mA (60mA)

VCCST

VCCSTG

1.0V@20mA

VCCSTG

VCCPLL_OC VCCPLL_OC

VCCPLL

1.0V@100mA

VCCPLL

CPU POWER 3 OF 4

1.2V@100mA

14 OF 20

0.85V@3A

VCCIO_DDR VCCIO_DDR VCCIO_DDR VCCIO_DDR VCCIO_DDR VCCIO_DDR VCCIO_DDR VCCIO_DDR VCCIO_DDR VCCIO_DDR VCCIO_DDR VCCIO_DDR VCCIO_DDR VCCIO_DDR VCCIO_DDR VCCIO_DDR VCCIO_DDR VCCIO_DDR VCCIO_DDR VCCIO_DDR VCCIO_DDR VCCIO_DDR VCCIO_DDR VCCIO_DDR VCCIO_DDR VCCIO_DDR

VCCIO_SENSE

VSSIO_SENSE

+0.85VS_ VCCIO

Rev0.87

AC23

VCCIO

AF24

VCCIO

AN26

VCCIO

AC24

VCCIO

AF26

VCCIO

AR26

VCCIO

AE23

VCCIO

AH26

VCCIO

AT26

VCCIO

AE24

VCCIO

AK26

VCCIO

AE26

VCCIO

AL26

VCCIO

AV26 AV36 AV46 AW31 AW41 AW51 AV28 AV38 AV48 AW33 AW43 AV30 AV40 AV50 AW35 AW45 AV32 AV42 AW27 AW37 AW47 AV34 AV44 AW29 AW39 AW49

AT24 AR24

PCH_PW R_EN(29,39,45,4 6,48)

+0.85VS_ VCCIO

RC538 100_020 1_1%@

RC98

0_0201_ 5%

+5VALW

Intel recommand RON(Max) : 70m ohm

+3VALW TO +3V_PRIM

+3VALW

CC50

1U_0201_6.3V6M

UC9

VIN

CC317

VIN

VBIAS

SA00006 U600

AOZ1336 _DFN8_2X2

1 2

RC562 0_ 0201_5%

EN_3V_P RIM

short@

VCCIO_SEN SE (47) VSSIO_SEN SE (47)

1U_0201_6.3V6M

PIR8 SI: From SE000000K80 to SE00000QL10

1 2

+1.2V_VD DQ

+1.0V_VC CST

S0IX@

1 2

RC136 0_0402_ 5%

NDSX@

1 2

RC137 0_0402_ 5%

BSC Side

Title

SKL Y(8/13) Power

Size Document N umber Rev

LA-F803P

Date: Sheet of

CC321

1U_0201_6.3V6M

Compal Electronics, Inc.

0.1U_0201_10V6K CC337

RF@

0.1U_0201_10V6K

CC338

CC339

@RF@

0.1

12 55Friday, June 08, 20 18

+1.0V_PR IM

+1.0V_PRIM TO +1.0VS_VCCSTG

tCPU26:CPU_C10_GATE# de-assertion

+1.0V_PR IM

B B

EN_VCCS TG_VCCPLL_OC

A A

to VCCSTG stable = 10us<Tr<65us(S0i3)

VOUT

VIN

VOUT

VIN

CTC2PG

SUSP#

PM_SLP_ S3#

PM_SLP_ S0#

UC5

GND

1U_0201_6.3V6M

CC319

PM_SLP_ S3#(9,29,33,39 )

PM_SLP_ S0#(9,11,29,47 ,49)

A2 B2

TPS2297 1YZPT_DSBGA8

SUSP#(29,39,44 ,47)

+1.0VS_V CCSTG

A1 B1

1 2

RC108 0_020 1_5%

1 2

RC109 0_020 1_5%

1 2

RC110 0_020 1_5%S0 IX@

1U_0201_6.3V6M

CC30

0.1U_0201_10V6K

0.1U_0201_10V6K CC360

CC359

@RF@

AND GATE

UC6

GND

74LVC1G 08FZ4-7_X2-DFN 1410-6

SA00007 YD00 S0IX@

+1.0VS_V CCSTG

BSC Side

0.1U_020 1_10V6K

RC578 0_020 1_5%

VCC

CC18

NDSX@

1 2

+3V_PRIM

SYSON(21,29,44)

CC318

1 2

0.1U_020 1_10V6KS0IX@

Security Class ification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

EN_VCCS TG_VCCPLL_OC

2041/09/ 08 2013/10/ 28

C5245

1U_0402 _10V6K

1 2

+3VALW

+1.2V_VD DQ +1.2V_VC CPLL_OC

CC320 1U_0201 _6.3V6M

EN_VCCS TG_VCCPLL_OC

Compal Secret Data

U27

VIN

VBIAS

AOZ1336 DI_DFN8_2X2

SA00006 U600

For Modern Stan dby

S0IX@

VIN

CTC2PG

TPS2297 1YZPT_DSBGA8

Deciphered Date

VOUT VOUT

GND GND

VOUT VOUT

GND

UC7

7 8

C284 1000P_0402_50 V7K

5 9

+1.1V_VC CPLL_OC

A1 B1

+1.0V_PRIM

CC32

0.1U_0201_10V6K

CC48

0.1U_0201_10V6K

CC34

0.1U_0201_10V6K

Close to Pin AH18 Close to Pin V1Close to Pin AH13 Close to Pin AR21 Close to Pin AA15

D D

+VCCPRIM_CORE

+1.0V_PRIM

CC129

0.1U_0201_10V6K

Close to Pin AE18 and AR16

CC332 22U_0402_6.3V6M

CC130

0.1U_0201_10V6K

CC1

0.1U_0201_6.3V6K

R213 0_0402_5% R212 0_0402_5%

CC19

0.1U_0201_10V6K

1 2 1 2

Close to Pin T1 and T15

+1.0V_PRIM

C C

Close to Pin V15

+1.0V_APLL

PIR20 SI: pop C ap.

CC393

CC394

RF@

68P_0201_50V8J

CC281

0.1U_0201_10V6K

CC322

0.1U_0201_10V6K

CC395

RF@

68P_0201_50V8J

FF:38.2

W=40mils

CC396

RF@

0.1U_0201_6.3V6K

CC391

RF@

0.1U_0201_6.3V6K

CC392

RF@

CC284

22U_0603_6.3V6M

CC328 22U_0402_6.3V6M

CC323

0.1U_0201_10V6K

0.1U_0201_6.3V6K

CC285

0.1U_0201_10V6K

+1.0V_PRIM

+3V_PRIM +1.0V_PRIM

B B

+1.8V_PRIM +VCCPRIM_CORE

PIR7 SI: From S M01000HC00 to SM01000NY00

LC3

1 2

BLM15PX221SN1D

CC399

RF@

68P_0201_50V8J

CC329 22U_0402_6.3V6M

CC324

0.1U_0201_10V6K

Close to Pin AH21 Close to Pin AK19Close to Pin AC2

CC390

RF@

68P_0201_50V8J

CC389

RF@

RTC Battery

Battery Module

+3V_LID

A A

+3VL

W=20mils

1 2

RC116 1K_0402_5%

W=20mils

MAX. 8000mil

DC1

BAT54LPS-7_X2-DFN100 6-2-2

SCS0000AO00

DC2

BAT54LPS-7_X2-DFN100 6-2-2

SCS0000AO00

CC35

0.1U_0201_10V6K

CC286

0.1U_0201_10V6K

CC333

1U_0201_6.3V6M

Close to Pin AK19

CC397

RF@

0.1U_0201_6.3V6K

+3VL_RTC

2mA

CC325

0.1U_0201_10V6K

DCPDSW _1P0

CC334

0.1U_0201_6.3V6K

Close to Pin AL2

CC289

0.1U_0201_10V6K

Close to Pin AT15

+1.0V_PRIM

+3VALW_D SW+3VALW+3V_PRIM

+3VALW_D SW

CC131

Close to Pin AL15

+3V_PRIM

PIR7 SI: From S M01000HC00 to SM01000NY00

CC398

RF@

0.1U_0201_6.3V6K

CC53

0.1U_0201_10V6K

+1.0V_PRIM

BLM15PX221SN1D

CC169

2.2P_0201_25V

CC39

0.1U_0201_10V6K

Close to Pin R21

CC24

0.1U_0201_10V6K

Close to Pin V19 Close to Pin V23

+3V_PRIM(5,7 ,8,9,10,11,12,24,25,26,29,30,33) +1.0V_PRIM(9, 12,17,46) +VCCPRIM_CORE(48)

UC1P

+1.0V_PRIM

1.0V/0.599A

+VCCPRIM_CORE

1.1A

DCPDSW _1P0

+1.0V_PRIM

1.0V/0.022A

1.0V/1.6A

+1.0V_PRIM

1.0V/0.088A

+1.0V_APLL

1.0V/0.026A

+1.0V_PRIM

1.0V/0.599A

3.3V/0.071A

+3V_HDA

3.3V/0.068A

3.3V/0.011A

1.0V/0.565A

CC29

0.1U_0201_10V6K

Close to Pin AA21

+3V_PRIM

3.3V/0.075A

+1.0V_PRIM

1.0V/0.033A

L24

1 2

+3V_HDA+3V_PRIM

CC282

0.1U_0201_10V6K

Close to Pin V21

CC38

0.1U_0201_10V6K

Close to Pin V18

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

AH18 AH19

AK18 AL18

AE18 AE19 AF18 AF19 AR16 AT16

AL2

AM1

T1 T15 T16

V15 V16

AA18 AA19

AH13 AH15

AL15

AM13

AT23 AV22

AT15 AV15

AA21 AA23 AK23

AL23 AN23 AR23

AH21

AK21

AR21

AT21

R15 R16

Close to Pin AT23

CC23

0.1U_0201_10V6K

VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0

VCCPRIM_CORE VCCPRIM_CORE VCCPRIM_CORE VCCPRIM_CORE VCCPRIM_CORE VCCPRIM_CORE

DCPDSW_1P0 DCPDSW_1P0

VCCMPHYAON_1P0 VCCMPHYAON_1P0

VCCMPHYGT_1P0 VCCMPHYGT_1P0 VCCMPHYGT_1P0 VCCMPHYGT_1P0

VCCAMPHYPLL_1P0 VCCAMPHYPLL_1P0

VCCAPLL_1P0 VCCAPLL_1P0

VCCPRIM_1P0 VCCPRIM_1P0

VCCDSW_3P3 VCCDSW_3P3

VCCHDA VCCHDA

VCCSPI VCCSPI

VCCSRAM_1P0 VCCSRAM_1P0 VCCSRAM_1P0 VCCSRAM_1P0 VCCSRAM_1P0 VCCSRAM_1P0

VCCPRIM_3P3 VCCPRIM_3P3

VCCPRIM_1P0 VCCPRIM_1P0

VCCAPLLEBB_1P0 VCCAPLLEBB_1P0

KBL-Y_BGA1515

+3V_PRIM

Primary Well 1.0 V : For I/O blocks, ungated ISH SRAM power, USB AFE Digital Logic, JTAG, Thermal Sensor and MIPI DPHY.

1.0V@

1.0V/0.85V@

Analog supply for OPI, USB2 and Audio PLL Primary 1.0V: Filtering required.

HD Audio Power 3.3 V, 1.8 V, 1.5 V. For Intel High Definition Audio

SPI Primary Well 3.3 V or 1.8 V

SRAM Primary Well 1.0 V. Dedicated SRAM rail and can have on board power down gate control.

PDG_place as close as ball

PDG_VCCHDA design for HD Audio VCCHDA should be connected to 3.3V or 1.5V, or designed for I2S VCCHDA should be connected to 1.8V or 3.3V.

CC330 22U_0402_6.3V6M

Close to Pin R19

CC331 22U_0402_6.3V6M

2041/09/08 2013/10/28

SKYLAKE_ULX

DCPDSW_1P0 Deep Sx Well 1.0 V: This rail is generated by on die DSW low dropout (LDO) linear voltage regulator to supply DSW GPIOs, DSW core logic and DSW USB2 logic. Board needs to connect 1 uF capacitor to this rail and power should NOT be driven from the board. When primary well power is up, this rail is ypassed from VCCPRIM_1p0.

Mod PHY Always On Primary 1.0 V: Always on primary supply for PCIe/DMI/USB3/SATA/MIPI MPHY logic

Mod PHY Externally Gated Primary 1.0 V: Externally gated primary supply for PCIe/DMI/USB3/SATA/MIPI MPHY logic.

Analog supply for USB3, PCIe Gen 2/Gen 3, SATA3 and MIPI PLL 1.0V: This rail is from externally gated domain. Filtering required.

Deep Sx Well for GPD GPIOs and USB2

Primary Well 3.3 V

1.0V/0.599A

PCH POWER

16 OF 20

CC291

0.1U_0201_10V6K

Close to Pin AV1 Close to Pin AH1 Close to Pin AF1 Close to Pin AA2

+1.8V_PRIM

Compal Secret Data

Deciphered Date

+3V_PRIM +1.0V_PRIM +VCCPRIM_CORE

RTC Logic Primary Well 3.3 V. This power supplies the RTC internal VRM. It will be off during Deep Sx mode.

VCCRTCPRIM_3P3 VCCRTCPRIM_3P3

RTC de-coupling capacitor only. This rail should NOT be driven.

1.0V/0.035A

Clock Buffers Primary 1.0 V

1.0V/0.029A

Clock Buffers Primary 1.0 V

1.0V/0.024A

Clock Buffers Primary 1.0 V

1.0V/0.033A

Clock Buffers Primary 1.0 V

1.0V/0.004A

Clock Buffers Primary 1.0 V

1.0V/0.010A

GPP_B0/CORE_VID0 GPP_B1/CORE_VID1

+3VL_RTC

CC292

0.1U_0201_10V6K

CC297

0.1U_0201_10V6K

Close to Pin AN2

Rev0.87

VCCPGPPA VCCPGPPA VCCPGPPB VCCPGPPB VCCPGPPC VCCPGPPC VCCPGPPD VCCPGPPD VCCPGPPE VCCPGPPE

VCCPGPPF

VCCPGPPF VCCPGPPG VCCPGPPG

VCCPRIM_3P3 VCCPRIM_3P3

VCCPRIM_1P0 VCCPRIM_1P0

VCCATS_1P8 VCCATS_1P8

VCCRTC VCCRTC

DCPRTC DCPRTC

VCCCLK1 VCCCLK1

VCCCLK2 VCCCLK2

VCCCLK3 VCCCLK3

VCCCLK4 VCCCLK4

VCCCLK5 VCCCLK5

VCCCLK6 VCCCLK6

CC336

0.1U_0201_6.3V6K

Close to Pin AR19

CC293

0.1U_0201_10V6K

CC335

0.1U_0201_6.3V6K

Close to Pin AE15

+1.0V_PRIM

CC290

0.1U_0201_10V6K

1 2

2.2P_0201_25V

1 2

2.2P_0201_25V

+3VL_RTC +3VALW_D SW +1.8V_PRIM

Close to Pin R15

CC296

0.1U_0201_10V6K

Close to Pin AN15Close to Pin AT1

EMI@

13 55Friday, June 08, 2018

+3VL_RTC(9) +3VALW_D SW(9) +1.8V_PRIM(8,21,26,39,45)

+3V_PRIM

AT1 AU2 AV1 AW2 AH1 AJ2 AF1 AG2 AA2 AB1

+1.8V_PRIM

AN2 AP1 AN15 AP13

+3V_PRIM

AC2 AD1

3.3V/0.075A

+1.0V_PRIM

AA15 AA16

1.0V/0.599A

Thermal Sensor Primary Well 1.8 V

+1.8V_PRIM

AE15 AE16

1.8V/0.006A

+3V_PRIM

AK19 AL19

3.3V/0.001A

AR19 AT19

3.3V/0.001A

AT18 AV18

CC326 0.1U_0201_10V6K

V18 Y18

1.0V/0.035A

V19 Y19

1.0V/0.029A

V23 Y23

1.0V/0.024A

V21 Y21

1.0V/0.033A

R21 R23

1.0V/0.004A

R19 T19

1.0V/0.01A

BA13 BB12

CC327

0.1U_0201_10V6K

CC294

0.1U_0201_10V6K

Title

Size Document Number Rev

Date: Sheet of

1.8V/0.009A

3.3V/0.004A

3.3V/0.006A

3.3V/0.008A

3.3V/0.006A

1.8V/0.033A

3.3V/0.041A

RTC Well Supply. This rail can drop to 2.0 V if all other planes are off. This power is not expected to be shut off unless the RTC battery is removed or drained.

+3VL_RTC

1 2

Close to Pin AT18

CORE_VID0 (48) CORE_VID1 (48)

CC295

0.1U_0201_10V6K

+3V_HDA

+1.0V_APLL

Compal Electronics, Inc.

SKL Y(9/13) Power

LA-F803P

CC283

CC168

0.1

RC139

100_020 1_1%

RC141

100_020 1_1%

1 2

+VCC_CO RE +VCC_GT +1.0V_VC CST

VCCGT_S ENSE (49 ) VSSGT_S ENSE (49)

+VCC_CO RE(49,5 0,51) +VCC_GT(4 9,50,51) +1.0V_VC CST(5,9,1 2,49)

+VCC_CO RE +VCC_CO RE

D D

C C

B B

A64 AE32 AE40 AH41 AN32

AT33 AT41

M33 M43 M53 M64

N40

N59

P60

R57

AA32 AE33 AE41 AK32 AN41

AT35

B64

M35 M45 M56

N32

N42

N61

P62

R59

V32 AA41 AE35

AF32 AK41 AR32

AT36

D64

M37 M47

R63 P56 R32 Y32

J64 L48

T41

L40 L50

L42 L52

UC1L

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

KBL-Y_BGA1515

SKYLAKE_ULX

.5V@24A

CPU POWER 1 OF 4

12 OF 20

Rev0.87

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

VCC_SENSE VSS_SENSE

VIDALERT#

VIDSCK

VIDSOUT

VCCSTG VCCSTG

M58 N34 N54 N63 P64 R61 V41 AC41 AE38 AH32 AL41 AT32 AT40 H63 L46 L63 M41 M51 M62 N38 N57 P58 R41 T32 Y41 AC32 AE36 AF41 AL32 AR41 AT38 F64 L44 L54 M39 M49 M60 N36 N55

L34 L32

B58 A56 A58

AA26 AC26

Trace Length < 25 mils

SOC_SVID_ ALERT# SOC_SVID_ CLK_R SOC_SVID_ DAT_R

RC526

1 2

short@

0_0201_ 5%

+VCC_CO RE

RC147

100_020 1_1%

RC148

100_020 1_1%

1 2

+1.0VS_V CCSTG

PIR21 SI: un-pop RC147,RC148

VCCSENS E (49) VSSSENS E (4 9)

+VCC_GT

AA53 AB62 AC47 AC55 AD54 AD64 AE61

AF47

AJ53 AK49 AN46

AT43

AT50

N50

U61 V60

W57

Y44 Y51

Y62 AB54 AB64 AC49 AC57 AD56 AE53 AE63

AF49 AK43 AK50 AN47

AT44

AT51

R51

U53 U63 V62

W59

Y46 Y54

Y64 AB58 AC44 AC51 AC61 AD60 AE57

AF44

AF51 AK46 AB60 AC46

T46 T54

T47

UC1M

VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT

KBL-Y_BGA1515

SKYLAKE_ULX

1.5V@24A

CPU POWER 2 OF 4

13 OF 20

Rev0.87

VCCGT_SENSE

VSSGT_SENSE

+VCC_GT

AC53 AC63 AD62 AE59 AF46 AG53 AK47 AN44 AN51 AT49 N48 T44 T51 U59 V58 W55 Y43 Y50 Y60 AB56 AC43 AC50 AC59 AD58 AE55 AF43 AF50 AK44 AK51 AN49 AT46 N44 R53 T49 U55 V54 V64 W61 Y47 Y56 AN50 AT47 N46 T43 T50 U57 V56 W53 W63 Y49 Y58 AN43

Close CPU

N52 P52

Trace Length < 25 mils

+VCC_GT

SVID ALERT

+1.0V_VC CST

SOC_SVID_ ALERT# SOC_SVID_ALE RT#_R

RC143

1 2

220_020 1_5%

SVID DATA

+1.0V_VC CST

A A

SOC_SVID_ DAT_R

RC146

1 2

short@

0_0201_ 5%

Place the PU resistors close to CPU

RC142

56_0201 _5%

Place the PU resistors close to CPU

RC144

100_020 1_1%

1 2

SOC_SVID_ DAT

(To VR)

SOC_SVID_ DAT (49)

Security Class ification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

SVID CLK

SOC_SVID_ CLK_R SVID_CLK

RC525

1 2

short@

0_0201_ 5%

2041/09/ 08 2013/10/ 28

Compal Secret Data

Deciphered Date

SOC_SVID_ CLK (49)SOC_SVID_ ALERT#_R (4 9)

Compal Electronics, Inc.

Title

Size Document N umber Rev

Date: Sheet

Date: Sheet of

Compal Electronics, Inc.

SKL Y(10/13) Power

LA-F803P

0.1

14 55Friday, June 08, 20 18

D D

1.0V@4.1A

+VCC_SA

CC61

CC60

22U_0603_6.3V6M

0.1U_0201_10V6K

RC149

RC150

CC59

0.1U_0201_10V6K

+VCC_SA

1 2

C C

100_020 1_1%

VCCSA_S ENSE(49) VSSSA_S ENSE(49)

100_020 1_1%

B B

AA29

AF30

AN29

T30 AC29 AH29 AN30

M31

V29 AC30 AK29 AR29

N30

Y29 AE29 AK30

R29

Y30

AF29 AL29

T29

AT29 AT30

M29

N28

L30

KBL-Y_BGA1515

UC1O

VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA

VCCSA_DDR VCCSA_DDR

VCCSA_SENSE VSSSA_SENSE

SKYLAKE_ULX

CPU POWER 4 OF 4

15 OF 20

Rev0.87

VCCG0 VCCG0 VCCG0 VCCG0 VCCG0 VCCG0 VCCG0 VCCG0 VCCG0 VCCG0 VCCG0 VCCG0

VCCG1 VCCG1 VCCG1 VCCG1 VCCG1 VCCG1 VCCG1 VCCG1 VCCG1 VCCG1 VCCG1 VCCG1

AA35 R38 Y35 AA38 T35 Y38 AC35 T38 AC38 V35 R35 V38

AF35 AK38 AR35 AF38 AL35 AR38 AH35 AL38 AH38 AN35 AK35 AN38

+VCC_SA(49,50,51 ) +VCCCOR EG0(18) +VCCCOR EG1(18)

+VCCCOR EG0

+VCCCOR EG1

+VCC_SA +VCCCOR EG0 +VCCCOR EG1

A A

Security Class ification

2041/09/ 08 2013/10/ 28

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2041/09/ 08 2013/10/ 28

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document N umber Rev

Date: Sheet

Date: Sheet of

Compal Electronics, Inc.

SKL Y(11/13) Power

LA-F803P

0.1

15 55Friday, June 08, 20 18

SKYLAKE_ULX

UC1Q

D D

C C

B B

AA36 AA47 AA57 AC15 AC27 AE10 AE43 AE50 AF16 AF40 AF62 AH24 AH40 AH49

AK24 AK40 AL16 AL33 AL46 AL53 AN18 AN33 AP64

AR47

AU55 AV16

AW17

AY16 AY32 AY42 AY52

BB28 BB38 BB48 BC17 BD56 BE33 BF56

BG2

BG8 BH28 BH40 BH50 BJ29 BK56 BL35

BM16

BP36 BP54

AH47 AJ59 AK16 AK36

A14

AK1

AR2 AR4

AR6

BA5 BA9

D10 E14 E24 E34 E44 E54

AK9

J14

V24

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

KBL-Y_BGA1515

GND 1 OF 3

17 OF 20

Rev0.87

K23 K33 K43 K53 L61 N20 R10 R24 R40 R49 T13 T33 T60 V27 V43 V50 Y15 Y33 Y9 AA24 AA40 AA49 AA59 AC16 AC33 AE2 AE44 AE51 AF21 AF54 AF64 AH27 AH43 AH50 AK11 AK27 AK5 AL21 AL36 AL47 AL59 AN19 AN36 AR10 AR27 AR40 AR49 AR8 AU57 AV20 AW19 AY24 AY34 AY44 BA53 BB20 BB30 BB40 BB50 BC29 BD63 BE35 BF59 BG29 AL30 AL44 AL51 AN16 AN27 BA7

BH20 BH32 BH42 BH52

BJ47

BL1

BL47

BM18

BN6 BP38 BP60

E16

E26

E36

E46

E56

K15

K25

K35

K45

K55

N22

R30

R43

R50

V30

V44

V51

Y16

Y36

AA27 AA43 AA50 AA61 AC18 AC36 AE21 AE46

AE8

AF23

AF56 AG59 AH30 AH44 AH51 AK13

AK3

AK54

AL24

AL40

AL49

AM54

AN21 AN40 AR12 AR30 AR43 AP54 AR18 AR36 AR46 AR59

BA3

T18 T36 T62

UC1R

KBL-Y_BGA1515

SKYLAKE_ULX

GND 2 OF 3

18 OF 20

Rev0.87

AR50 AT27 AU59 AV24 AW21 AY26 AY36 AY46 BA1 BA58 BB22 BB32 BB42 BB52 BC47 BE12 BE47 BG12 BG4 BH22 BH34 BH44 BH54 BJ62 BL29 BL8 BM20 BP22 BP44 D6 E18 E28 E38 E48 E59 J5 K17 K27 K37 K47 L14 N14 N24 R33 R44 R55 T21 T40 T64 V33 V46 Y1 Y24 Y40 AA30 AA44 AA51 AA63 AC19 AC40 AE30 AE47 AF13 AU53 AU63 AV54 AW25 AY30 AY50

AF33

AF58 AH16 AH33 AH46 AH54 AK15 AK33

AK7 AL27 AL43 AL50

AM64 AN24 AN59 AR15 AR33 AR44 AR51

AT54

AU61 AV52

AW23

AY28 AY38 AY48 BA11 BA64 BB24 BB34 BB44 BB54 BD20 BE29

BF20

BG15

BG6

BH24 BH36 BH46 BH56 BK20

BL31

BM11 BM38 BP28 BP46

AY40

AH36

C14 D62 E20 E30 E40 E50 F62

K19 K29 K39 K49 L57 N16 N26 R18 R36

V49 Y13

V40

J62

UC1S

KBL-Y_BGA1515

SKYLAKE_ULX

GND 3 OF 3

19 OF 20

Rev0.87

VSS

R46 R6 T23 T56 V13 V36 V47 Y11 Y27 Y5 BB26 BB36 BB46 BB59 BD38 BE31 BF38 BG17 BG63 BH26 BH38 BH48 BH59 BK38 BL33 BM14 BN29 BP30 BP52 C40 D8 E22 E32 E42 E52 G14 J7 K21 K31 K41 K51 L59 N18 P54 R2 R4 R47 R8 T24 T58 Y3 AA33 AA46 AA55 AB13 AC21 AD13 AE4 AE49 AF15 AF36 AF60 AH23 BP1 A5 D1

BP62

A A

Security Class ification

2041/09/ 08 2013/10/ 28

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2041/09/ 08 2013/10/ 28

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document N umber Rev

Date: Sheet of

Compal Electronics, Inc.

SKL Y(12/13) GND

LA-F803P

0.1

16 55Friday, June 08, 20 18

D D

UC1T

G52

CFG[0]

F53

CFG[1]

J52

G58

G54

G56

BA19 BB18

BC19 BD18

M21

M19

H53 H55 D55 C56 F55 D61

D57 F61 J60 J58 H61 H59

J54

J56

A54

A60

L36 L38

D49

L20

L26

B4 B3

F3 F1

KBL-Y_BGA1515

CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15]

CFG[16] CFG[17]

CFG[18] CFG[19]

CFG_RCOMP

ITP_PMODE

RSVD RSVD

RSVD RSVD RSVD RSVD

RSVD

+1.0V_PR IM

XDP_ITP_P MODE

C C

1 2

RC567 1K_0 201_5%

RC151 49.9_040 2_1%

RC152 1K_0201 _1%

1 2

CFG4

CFG_RCO MP

XDP_ITP_P MODE

CFG4

Functional Strap Definitions

CFG[4] : Display Port Presence strap 0 = Enabled - A Display Port device is connected to the Embedded Display Port. No connect for disable. 1 = Disabled - No Physical Display Port attached to Embedded DisplayPort*. Pull-down to GND through a 1 K? +-5% resistor to enable port.

B B

SKYLAKE_ULX

RESERVED SIGNALS

20 OF 20

Rev0.87

RSVD_TP RSVD_TP

RSVD RSVD

RSVD RSVD RSVD RSVD

RSVD RSVD

RSVD

RSVD RSVD

RSVD

RSVD RSVD

TP5 TP6

TP4

TP1 TP2

BL64 BG47

BA17 AY18

BF18 BE19

BA23 AY22

R12 P13 M15 L16

L18 M17

AH7

K12 H12

BN3 BP3

L22 M23

BN1

AY20 BA21

BB14

M25 L24

L28 M27

BJ15 BJ17

1 2

RC153 0_0201_ 5%short@

A A

Security Class ification

2041/09/ 08 2013/10/ 28

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2041/09/ 08 2013/10/ 28

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document N umber Rev

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

SKL Y(13/13) RSVD

LA-F803P

0.1

17 55Friday, June 08, 20 18

+ 38 hidden pages

Compal LA-F803P Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual