Compal LA-F322P Schematics rev.2.0

INFI@ : Inf i nit y SKU Co mponent

COMPAL CONFIDENTIAL

1 1

MODEL NAME : DAZ40 PCB NO : LA-F322P

Steamboat MLK 14" NonAR

BOM P/N : 431A8U31L0X

Kabylake-U U22 & Kabylake-R U42

2017-12-29

REV : 2.0 (A01)

@ : Nopop Component

2 2

3 3

EMI@ : EMI Component

@EMI@ : EMI Nopop Component

ESD@ : ESDComponent

@ESD@ : ESD Nopop Component

RF@ : RF Component

@RF@ : RF Nopop Component

CXDP@ : XDP Component

CONN@ : Connector Component

ESPI@ : ESPI interface Component

LPC@ : External ESPI Component (SHD)

MB PCB

Part Number

DA8001CH010

Layout Dell logo

Description

PCB 265 LA-F322P REV0 MB NAR 1

U42@ : KBL-R U42 Component U22@ : KBL-R U22 Component

DS3@ : Deep sleep Component

NDS3@ : Non Deep sleep Component

4 4

Power CKT : 0920

PIO map : 0821

546@ : TI TUSB546 Component

8743@ : PARADE PS8743 Component

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOU T THE EXPRESS WRITTEN AUTHORIZATION O F DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

PARTY WITHOUT DELL'S EXPRESS WRIT TEN CONSENT.

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

Size Document Number Re v

Date : Sheet o f

Compal Electronics, Inc.

Cover Sheet

LA-F322P

1 59Friday, December 29, 2017

2.0

Lef t Fr ont

Lef t Rear

Steamboat MLK 14 w/o AR Block Diagram

Memory BUS (DDR4)

2133 MHz on KBL-U

1 1

EDP CONN

P27

eDP 14": Lane x 4; 12" :Lane x 2

2400 MHz on KBL-R up to 16GB

Steamboat MLK 12&13 only support one DIMM

Reverse Type

DDR4-SO-DIMM X2

BANK 0, 1, 2, 3

P20~21

I2C

P31

P27

P35

LCD Touch

Camera

USB3.0 Conn PS(Ext Port 1) Right

USB3.0 Conn (Ext Port 2)

USB3.0 Conn (Ext Port 3)

P27

Trough eDP Cable

P36

P37

only 14"

LID SWITCH

USH CONN

P39

P34

USB2.0[8]-Reser ve

PCIE[3]

P30

USB2.0[7]

P23

DDI[1]

DDI[2]

INTEL

KABYLAKE_U MCP

U22

KABYLAKE_R MCP

U42

SPI

ESPI

SMSC KBC MEC5105

P32-3 3

PAGE 6~19

HD Audio I/F

SATA[2]/PCIE [9][10][11] [12]

W25Q128JVSIQ

128M 4K sector

W25Q128JVSIQ

128M 4K sector

TPM1.2/2.0 Nuvoton NPCT750JAAYX

KB/TP CONN

FAN CONN

reserve

P38

P33

USB2.0[5]

USB2.0[9]

USB

USB3.0[6]

SLGC55544CVTR

USB POWER SHARE

P36

USB2.0[9]_PS

USB3.0[6]

USB2.0[2]

USB3.0[3]

USB2.0[3]

USB3.0[4]

INT.Speaker

HDA Codec ALC3246

P34

P31

Universal Jack

ig. MIC

Trough eDP Cable

M.2 2280

SSD Conn

HDMI 1.4 CONN

HDMI

P22

To NonAR type C

2 2

PCIE[1]

Card reader RTS5242

P29

SD4.0

P29

3 3

PCIE[4]

Intel Jacksonville

WGI219LM

Transformer

RJ45

P28

SATA[1]

M.2,3042 Key B

WWAN/LTE/Cache

P30

USB2.0[4]

USB3.0[2]

M.2,3030 Key A

WLAN+BT

CPU&PCH XDP Port

Non-AR Type C

DP1.2 4 lanes

TX/RX

USB 3.0 + AM Type C CONN.

4 4

USB2.0

Vbus

HS Redriver Switch TUSB546

P23

GPIO

PD Solut i on TPS65982DC

P24-2 5P26

DDI[2]

USB3.0[1]

SMBUS

USB2.0[1]

Smart Card

5V VR

Charger

TDA8034HN

RFID/NFC

Fingerprint CONN

USH board

USB2.0[10]

P34

USH TPM1.2

BCM58102

SPI

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER P ROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

DELL CONFIDENTIAL/PROPRIETARY

Title

Size

Document Number Re v

Size

Document Number Re v

Size

Document Number Re v

Date: Sheet of

AUTOMATIC POWER SWITCH(APS)

DC/DC Interface

POWER ON/OFF

SW & LED

Compal Electronics, Inc.

Block diagram

LA-F322P

P14

P11

P40

P39

2 59Wednesday, December 20, 2017

2.0

JUSB2-->Lef t Fr ont

JUSB3-->Lef t Rear ( SB14 onl y)

POWER STATES

Signal

State

S0 (Full ON) / M0

S3 (Suspend to RAM) / M3 LOW

D D

S4 (Suspend to DISK) / M3

S5 (SOFT OFF) / M3

S3 (Suspend to RAM) / M-OFF

S4 (Suspend to DISK) / M-OFF

S5 (SOFT OFF) / M- OFF

SLP S3#

HIGH

LOW

LOW LOW LOW

LOW LOW LOW LOW

SLP

S5#

S4#

HIGH HIGH

LOW

HIGH HIGH

HIGH

ALW AYS

SLP

PLANE

HIGH

ON ON ON

ON ON

HIGH

ON ON

LOW

PM TABLE

+5V_ALW

+3.3V_ALW

+3.3V_ALW_D SW

power

C C

State

S5 S4/AC

S5 S4/AC doesn't exist

plane

+3.3V_ALW_PCH +1.2V_MEM

+RTC_CELL

+1.8V_PRIM

+1.0V_PRIM

+1.0V_PRIM_CORE

+5V_ALW 2

+3.3V_ALW 2

+3.3V_RTC_LDO

+1.0V_MPHYGT

+3.3V_CV2

+2.5V_MEM

+1.0V_VCCST

+5V_RUN

+3.3V_RUN

+0.6V_DDR_VTT

+1.8V_RUN

+VCC_CORE

+VCC_GT

+VCC_SA

+1.0VS_VCCIO

ON ON

OFF

OFFOFF

M PLANE

OFF OFF OFF

OFF OFF OFF OFF

OFF

RUN

SUS

PLA NE

PLANE

ON ON ON

OFF

OFFLOW

CLOCKS

OFF

USB3.0

USB3.0-1

USB3.0-2

USB3.0-3

USB3.0-4

USB3.0-5

USB3.0-6

SSIC

PCIE

PCIE-1

PCIE-2

PCIE-3

PCIE-4

PCIE-5

PCIE-6

PCIE-7

PCIE-8

PCIE-9

PCIE-10

PCIE-11

PCIE-12

SATA

JUSB3-->Lef t Rear ( SB14 onl y)

SATA-0

ATA-1

SATA-1*

M.2 3042(SATA Cache)

M.2 2280 SSD (PCIex4 or SATA)

SATA-2

12" not support JUSB3

Typce-C(Non AR)

M.2 3042(LTE)

Card Reader (PCIE)

JUSB1-->Right

M.2 3030(WLAN)

LOM

NonAR config

USB PORT#DESTINATION

DESTINATION

Typce-C(Non AR)

M2 3042(WWAN)

Camera

M.2 3030(BT)

Touch Screen

JUSB1-->Right

USH

B B

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Port assignment

LA-F322P

3 59Wednesday, December 20, 2017

2.0

AR use 1086PP (10L) Non AR use 1080PP (8L)

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EX PRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT DELL'S EX PRESS WRITTEN CONSENT.

Title

Size Document Nu mber Re v

Date : Sheet of

Barrel ADAPT ER

D D

CHARGER ISL9538

(PU901)

Type-C A

DAPTER

+PWR_SRC

BATTERY

C C

SY8210A (PU200)

SY8286R (PU301)

SYV828C

(PU102)

SY8288B

(PU100)

SIO_SLP_S4#

0.6V_DDR_ VTT_ON

PCH_P RIM_EN (SIO_SLP_SU S#)

ALWO N

+1.2V_MEM

+0.6V_DDR_VTT

+1.0V_PRIM

+5V_ALW

+5V_ALW2

+3.3V_RTC_LDO

+3.3V_ALW2

+3.3V_ALW

TPS22961

(UZ26)

VCCSTG_ EN

+VCC_SFR_OC

TPS62134C

(PU401)

TPS62134D

(PU402)

EM5209

(UZ4)

SLGC55544C

(UI3)

SY6288

(UI1)

SY6288

(UI2)

RUN_ ON

PCH_P RIM_EN (SIO_SLP_SU S#)

RUN_ ON

USB_PW R_SHR_ VBUS_EN

USB_PW R_EN1#

USB_PW R_EN2#

TPS22961

(UZ19)

TPS22961

(UZ21)

+1.0VS_VCCIO

+1.0V_PRIM_CORE

+5V_RUN

+5V_USB_CHG_PWR

+USB_EX2_PWR

+USB_EX3_PWR

SB14 only

RUN_ ON SIO_SLP_S0#

SIO_SLP_S4#

LP2301

(QV8)

EM5209

(@UZ5)

+1.0V_VCCSTG

+1.0V_VCCST

3.3V_TS_EN

AUD_PW R_EN

CPU PWR

PCH PWR

GT3 PWR

Peripheral Device PWR

TYPE-C Power

GPU PWR

+5V_TSP

+5V_RUN_AUDIO

RT8097A

CSD97396Q

ISL95808

(PU614)

IMVP_V R_ON

B B

CSD97396Q

(PU612)

IMVP_V R_ON

+VCC_GT+VCC_SA

(PU610) CSD9 7396Q (PU613)

U42@

IMVP_V R_ON

+VCC_CORE

AO6405

(QV1)

EN_IN VPWR

+BL_PWR_SRC

TYPE-C

(PU501)

EM5209

(UZ2)

EM5209

(UZ3)

EM5209

(UZ4)

G524B1T11U (UV24)

PCH_P RIM_EN (SIO_SLP_SU S#)

SIO_SLP_L AN#

AUX_EN_WOW L

@SIO_SLP_ WLAN#

PCH_P RIM_EN (SIO_SLP_SU S#)

@PCH_ALW _ON

RUN_ ON

3.3V_W WAN_EN

ENVCC _PCH

+1.8V_PRIM

+3.3V_LAN

+3.3V_W LAN

+3.3V_ALW_PCH

+3.3V_RUN

+3.3V_W WAN

+LCDV DD

AOZ1336

(UZ8)

EM5209

(@UZ5)

LP2301 A

(QZ1)

RUN_ ON

3.3V_CAM_ EN#

+1.8V_RUN

+3.3V_RUN_AUDIO

+3.3V_CAM

+5V_ALW

TPS65982D

+5V_ALW

(UT5)

AP2112 K

(UT7)

+PP_HV(5V~20V)

A A

AP2204

(UT8)

+5V_TBT_VBUS

+TBTA_Vbus_1(5V~20V)

+3.3V_VDD_PIC

AP7361C

(PU503)

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

SIO_SLP_S4#

+2.5V_MEM

for D DR4

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

Size Document Nu mber Re v

Date : Sheet of

Compal Electronics, Inc.

Power rails

LA-F322P

4 59Wednesday, December 20, 2017

2.0

AW44

BB43

KBL-R

D D

KBL-U

AW45 AW42

AY44

BB39

SML1_SMBD ATA

SML1_SMBCLK

D8E11

UPD2_SMBCLK

UPD2_SMBDAT

MEM_SMBC LK

MEM_SMBDATA

SML0_SMBCLK

SML0_SMBD ATA

+3.3 V_ALW_ PCH

2.2K

+3.3 V_ALW

499

+3.3 V_ALW_ PCH

DMN65D8LDW-7

LOM

2.2K

+3.3 V_RUN

202

200

202

200

DIMMA

DIMMB

XDP

@2.2K

USH_SMBCLK

C C

KBC

C12

E10

USH_SMBDAT

2.2K

UPD_SMB CLK

UPD_SMBDAT

+3.3 V_ALW

DMN66D0LDW-7

2.2K

+3.3 V_CV2

USH

USH/B

+3.3 V_TBT_ FLAS H

MEC 5105

A12

N10

B B

A A

08 C5

1010M3

PBAT_CHARGER_SMBCLK

PBAT__CHARGER_SMBDAT

2.2K

+3.3 V_ALW

100 ohm

Charger

BATTERY

CONN

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

Title

Size Document Nu mber Re v

Date : Sheet of

Compal Electronics, Inc.

Port assignment

LA-F322P

5 59Wednesday, December 20, 2017

2.0

+3.3V_RUN

CPU_DP1_CTRL_CLK

RC175 2.2K_0402_5%

RC178 2.2K_0402_5%

D D

RC176 2.2K_0402_5%

RC177 2.2K_0402_5%

CPU_DP1_CTRL_DATA

CPU_DP2_CTRL_CLK

CPU_DP2_CTRL_DATA

AR (AR)/ HDMI(Non AR)

Dockport (Non AR)

+1.0VS_VCCIO

C C

B B

CPU_DP1_N0<22> CPU_DP1_P0<22> CPU_DP1_N1<22> CPU_DP1_P1<22> CPU_DP1_N2<22> CPU_DP1_P2<22> CPU_DP1_N3<22> CPU_DP1_P3<22>

CPU_DP2_N0<23> CPU_DP2_P0<23> CPU_DP2_N1<23> CPU_DP2_P1<23> CPU_DP2_N2<23> CPU_DP2_P2<23> CPU_DP2_N3<23> CPU_DP2_P3<23>

CPU_DP1_CTRL_CLK CPU_DP1_CTRL_DATA

CPU_DP2_CTRL_CLK CPU_DP2_CTRL_DATA

TS_INT#

EDP_COMP

CPU_DP1_CTRL_CLK<22>

CPU_DP1_CTRL_DATA<22>

TS_INT#<27>

RC2 24.9_0402_1%

COMPENSATION PU FOR eDP

CAD Note:Trace width=20 mils , Spacing=25mil, Max length=100 mils.

CPU@

UC1A

E55

DDI1_TXN[0]

F55

DDI1_TXP[0]

E58

DDI1_TXN[1]

F58

DDI1_TXP[1]

F53

DDI1_TXN[2]

G53

DDI1_TXP[2]

F56

DDI1_TXN[3]

G56

DDI1_TXP[3]

C50

DDI2_TXN[0]

D50

DDI2_TXP[0]

C52

DDI2_TXN[1]

D52

DDI2_TXP[1]

A50

DDI2_TXN[2]

B50

DDI2_TXP[2]

D51

DDI2_TXN[3]

C51

DDI2_TXP[3]

L13

GPP_E18/DDPB_CTRLCLK

L12

GPP_E19/DDPB_CTRLDATA

GPP_E20/DDPC_CTRLCLK

GPP_E21/DDPC_CTRLDATA

N11

GPP_E22

N12

GPP_E23

E52

EDP_RCOMP

KBL-RU42_BGA1356

CPU@

UC1I

CSI-2

A36

CSI2_DN0

B36

CSI2_DP0

C38

CSI2_DN1

D38

CSI2_DP1

C36

CSI2_DN2

D36

CSI2_DP2

A38

CSI2_DN3

B38

CSI2_DP3

C31

CSI2_DN4

D31

CSI2_DP4

C33

CSI2_DN5

D33

CSI2_DP5

A31

CSI2_DN6

B31

CSI2_DP6

A33

CSI2_DN7

B33

CSI2_DP7

A29

CSI2_DN8

B29

CSI2_DP8

C28

CSI2_DN9

D28

CSI2_DP9

A27

CSI2_DN10

B27

CSI2_DP10

C27

CSI2_DN11

D27

CSI2_DP11

KBL-RU42_BGA1356

KBL-R U4+2

DDI

DISPLAY SIDEBANDS

KBL-R U4+2

EDP

Rev_0.1

CSI2_CLKN0 CSI2_CLKP0 CSI2_CLKN1 CSI2_CLKP1 CSI2_CLKN2 CSI2_CLKP2 CSI2_CLKN3 CSI2_CLKP3

CSI2_COMP

GPP_D4/FLASHTRIG

EMMC

GPP_F13/EMMC_DATA0 GPP_F14/EMMC_DATA1 GPP_F15/EMMC_DATA2 GPP_F16/EMMC_DATA3 GPP_F17/EMMC_DATA4 GPP_F18/EMMC_DATA5 GPP_F19/EMMC_DATA6 GPP_F20/EMMC_DATA7

GPP_F21/EMMC_RCLK

GPP_F22/EMMC_CLK

GPP_F12/EMMC_CMD

EMMC_RCOMP

9 OF 20

Rev_0.1

EDP_TXN[0] EDP_TXP[0] EDP_TXN[1] EDP_TXP[1] EDP_TXN[2] EDP_TXP[2] EDP_TXN[3] EDP_TXP[3]

EDP_AUXN EDP_AUXP

EDP_DISP_UTIL

DDI1_AUXN DDI1_AUXP DDI2_AUXN DDI2_AUXP

RSVD

GPP_E13/DDPB_HPD0 GPP_E14/DDPC_HPD1 GPP_E15/DDPD_HPD2 GPP_E16/DDPE_HPD3

RSVD

GPP_E17/EDP_HPD

EDP_BKLTEN

EDP_BKLTCTL

EDP_VDDEN

1 OF 20

C37 D37 C32 D32 C29 D29 B26 A26

CSI2_COMP

E13 B7

AP2 AP1 AP3 AN3 AN1 AN2 AM4 AM1

AM2 AM3 AP4

EMMC_RCOMP

AT1

C47 C46 D46 C45 A45 B45 A47 B47

E45 F45

B52

G50 F50 E48 F48 G46 F46

L9 L7 L6 N9 L10

R12 R11 U13

RC3

TBT_FORCE_PWR

1 2

RC4 200_0402_1%

CPU_DP1_AUXN CPU_DP1_AUXP

CPU_DP3_AUXN CPU_DP3_AUXP

1 2

EDP_TXN0 <27> EDP_TXP0 <27> EDP_TXN1 <27> EDP_TXP1 <27> EDP_TXN2 <27> EDP_TXP2 <27> EDP_TXN3 <27> EDP_TXP3 <27>

EDP_AUXN <27> EDP_AUXP <27>

PAD~D PAD~D

CPU_DP2_AUXN <23,24>

CPU_DP2_AUXP <23,24>

PAD~D PAD~D

CPU_DP1_HPD <22> CPU_DP2_HPD <23,24>

EDP_HPD <27>

PANEL_BKLEN <27> EDP_BIA_PWM <27> ENVDD_PCH <27>

100_0402_1%

T19 @PAD~D

+3.3V_RUN

T281

T282

CPU_DP2_AUXN

CPU_DP2_AUXP

CPU_DP2_HPD

EDP_HPD

1 2

RC448 100K_0402_5%

1 2

RC447 100K_0402_5%

1 2

RC446 100K_0402_5%

1 2

RC1 100K_0402_5%

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.

Title

ize Document N umber Re v

Size Document Number Re v

Date: Sheet of

Compal Electronics, Inc.

CPU (1/14)

LA-F322P

6 59Wednesday, December 20, 2017

2.0

For DDR4

DDR_A_DQS#[0..7]<20>

DDR4, Ballout for side by side(Non-Interleave)

D D

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15

DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41

C C

B B

DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47

AL71

AL68 AN68 AN69

AL70

AL69 AN70 AN71 AR70 AR68 AU71 AU68 AR71 AR69 AU70 AU69

BB65

AW65 AW63

AY63 BA65 AY65 BA63 BB63 BA61

AW61

BB59

AW59

BB61 AY61 BA59 AY59 AY39

AW39

AY37

AW37

BB39 BA39 BA37 BB37 AY35

AW35

AY33

AW33

BB35 BA35 BA33 BB33 AY31

AW31

AY29

AW29

BB31 BA31 BA29 BB29 AY27

AW27

AY25

AW25

BB27 BA27 BA25 BB25

CPU@

UC1B

DDR0_DQ[0] DDR0_DQ[1] DDR0_DQ[2] DDR0_DQ[3] DDR0_DQ[4] DDR0_DQ[5] DDR0_DQ[6] DDR0_DQ[7] DDR0_DQ[8] DDR0_DQ[9] DDR0_DQ[10] DDR0_DQ[11] DDR0_DQ[12] DDR0_DQ[13] DDR0_DQ[14] DDR0_DQ[15]

Interleave / Non-Interleaved

DDR0_DQ[16]/DDR0_DQ[32] DDR0_DQ[17]/DDR0_DQ[33] DDR0_DQ[18]/DDR0_DQ[34] DDR0_DQ[19]/DDR0_DQ[35] DDR0_DQ[20]/DDR0_DQ[36] DDR0_DQ[21]/DDR0_DQ[37] DDR0_DQ[22]/DDR0_DQ[38] DDR0_DQ[23]/DDR0_DQ[39] DDR0_DQ[24]/DDR0_DQ[40] DDR0_DQ[25]/DDR0_DQ[41] DDR0_DQ[26]/DDR0_DQ[42] DDR0_DQ[27]/DDR0_DQ[43] DDR0_DQ[28]/DDR0_DQ[44] DDR0_DQ[29]/DDR0_DQ[45] DDR0_DQ[30]/DDR0_DQ[46] DDR0_DQ[31]/DDR0_DQ[47] DDR0_DQ[32]/DDR1_DQ[0] DDR0_DQ[33]/DDR1_DQ[1] DDR0_DQ[34]/DDR1_DQ[2] DDR0_DQ[35]/DDR1_DQ[3] DDR0_DQ[36]/DDR1_DQ[4] DDR0_DQ[37]/DDR1_DQ[5] DDR0_DQ[38]/DDR1_DQ[6] DDR0_DQ[39]/DDR1_DQ[7] DDR0_DQ[40]/DDR1_DQ[8] DDR0_DQ[41]/DDR1_DQ[9] DDR0_DQ[42]/DDR1_DQ[10] DDR0_DQ[43]/DDR1_DQ[11] DDR0_DQ[44]/DDR1_DQ[12] DDR0_DQ[45]/DDR1_DQ[13] DDR0_DQ[46]/DDR1_DQ[14] DDR0_DQ[47]/DDR1_DQ[15] DDR0_DQ[48]/DDR1_DQ[32] DDR0_DQ[49]/DDR1_DQ[33] DDR0_DQ[50]/DDR1_DQ[34] DDR0_DQ[51]/DDR1_DQ[35] DDR0_DQ[52]/DDR1_DQ[36] DDR0_DQ[53]/DDR1_DQ[37] DDR0_DQ[54]/DDR1_DQ[38] DDR0_DQ[55]/DDR1_DQ[39] DDR0_DQ[56]/DDR1_DQ[40] DDR0_DQ[57]/DDR1_DQ[41] DDR0_DQ[58]/DDR1_DQ[42] DDR0_DQ[59]/DDR1_DQ[43] DDR0_DQ[60]/DDR1_DQ[44] DDR0_DQ[61]/DDR1_DQ[45] DDR0_DQ[62]/DDR1_DQ[46] DDR0_DQ[63]/DDR1_DQ[47]

KBL-RU42_BGA1356

KBL-R U4+2

DDR0_CKN[0] DDR0_CKP[0] DDR0_CKN[1] DDR0_CKP[1]

DDR0_CKE[0] DDR0_CKE[1] DDR0_CKE[2] DDR0_CKE[3]

DDR0_CS#[0] DDR0_CS#[1] DDR0_ODT[0] DDR0_ODT[1]

DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]

DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]

DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]

DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]

DDR0_CAS#/DDR0_CAB[1]/DDR0_M A[15]

DDR0_WE#/DDR0_CA B[2]/DDR0_MA[14]

DDR0_RAS#/DDR0_CAB[3]/DDR0_M A[16]

DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]

DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]

DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]

DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]

DDR CH - A

2 OF 20

DDR3L / LPDDR3 / DDR4

DDR0_MA[3]

DDR0_MA[4] DDR0_DQSN[0] DDR0_DQSP[0] DDR0_DQSN[1] DDR0_DQSP[1]

Interleave / Non-Interleaved

DDR0_DQSN[2]/DDR0_DQSN[4] DDR0_DQSP[2]/DDR0_DQSP[4] DDR0_DQSN[3]/DDR0_DQSN[5] DDR0_DQSP[3]/DDR0_DQSP[5] DDR0_DQSN[4]/DDR1_DQSN[0] DDR0_DQSP[4]/DDR1_DQSP[0] DDR0_DQSN[5]/DDR1_DQSN[1] DDR0_DQSP[5]/DDR1_DQSP[1] DDR0_DQSN[6]/DDR1_DQSN[4] DDR0_DQSP[6]/DDR1_DQSP[4] DDR0_DQSN[7]/DDR1_DQSN[5] DDR0_DQSP[7]/DDR1_DQSP[5]

DDR0_ALERT#

DDR_VREF_CA

DDR0_VREF_DQ DDR1_VREF_DQ

DDR_VTT_CNTL

Rev_0.1

DDR0_PAR

DDR_A_D[0..63]<20>

DDR_A_DQS[0..7]<20>

DDR_A_MA[0..16]<20>

DDR_A_CLK#0

AU53

DDR_A_CLK0

AT53

DDR_A_CLK#1

AU55

DDR_A_CLK1

AT55

DDR_A_CKE0

BA56

DDR_A_CKE1

BB56

DDR_A_CKE2

AW56

DDR_A_CKE3

AY56

DDR_A_CS#0

AU45

DDR_A_CS#1

AU43

DDR_A_ODT0

AT45

DDR_A_ODT1 DDR_B_ODT0

AT43

DDR_A_MA5

BA51

DDR_A_MA9

BB54

DDR_A_MA6

BA52

DDR_A_MA8

AY52

DDR_A_MA7

AW52

DDR_A_BG0

AY55

DDR_A_MA12

AW54

DDR_A_MA11

BA54

DDR_A_ACT#

BA55

DDR_A_BG1

AY54

DDR_A_MA13

AU46

DDR_A_MA15

AU48

DDR_A_MA14 DDR_B_MA15

AT46

DDR_A_MA16

AU50

DDR_A_BA0

AU52

DDR_A_MA2

AY51

DDR_A_BA1

AT48

DDR_A_MA10

AT50

DDR_A_MA1

BB50

DDR_A_MA0

AY50

DDR_A_MA3

BA50

DDR_A_MA4

BB52

DDR_A_DQS#0

AM70

DDR_A_DQS0

AM69

DDR_A_DQS#1

AT69

DDR_A_DQS1

AT70

DDR_A_DQS#4

BA64

DDR_A_DQS4

AY64

DDR_A_DQS#5

AY60

DDR_A_DQS5

BA60

DDR_B_DQS#0

BA38

DDR_B_DQS0

AY38

DDR_B_DQS#1

AY34

DDR_B_DQS1

BA34

DDR_B_DQS#4

BA30

DDR_B_DQS4

AY30

DDR_B_DQS#5

AY26

DDR_B_DQS5

BA26

DDR_A_ALERT#

AW50

DDR_A_PARITY

AT52

AY67

+DDR_VREF_A_DQ

AY68 BA67

AW67

DDR_A_CLK#0 <20> DDR_A_CLK0 <20> DDR_A_CLK#1 <20> DDR_A_CLK1 <20>

DDR_A_CKE0 <20> DDR_A_CKE1 <20>

PAD~D

DDR_A_CS#0 <20> DDR_A_CS#1 <20> DDR_A_ODT0 <20> DDR_A_ODT1 <20>

DDR_A_BG0 <20>

DDR_A_ACT# <20> DDR_A_BG1 <20>

DDR_A_BA0 <20>

DDR_A_BA1 <20>

DDR0_PAR,DDR0_ALERT# for DDR4

DDR_A_ALERT# <20>

+DDR_VREF_CA

T132

PAD~D

+DDR_VREF_B_DQ

DDR_VTT_CTRL <20>

DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31

DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

AF65

AF64 AK65 AK64

AF66

AF67 AK67 AK66

AF70

AF68 AH71 AH68

AF71

AF69 AH70 AH69

AT66 AU66 AP65 AN65 AN66 AP66

AT65 AU65

AT61 AU61 AP60 AN60 AN61 AP61

AT60 AU60 AU40

AT40

AT37 AU37 AR40 AP40 AP37 AR37

AT33 AU33 AU30

AT30 AR33 AP33 AR30 AP30

AU27

AT27

AT25 AU25 AP27 AN27 AN25 AP25

AT22 AU22 AU21

AT21 AN22 AP22 AP21 AN21

CPU@

UC1C

Interleave / Non-Interleaved

DDR1_DQ[0]/DDR0_DQ[16] DDR1_DQ[1]/DDR0_DQ[17] DDR1_DQ[2]/DDR0_DQ[18] DDR1_DQ[3]/DDR0_DQ[19] DDR1_DQ[4]/DDR0_DQ[20] DDR1_DQ[5]/DDR0_DQ[21] DDR1_DQ[6]/DDR0_DQ[22] DDR1_DQ[7]/DDR0_DQ[23] DDR1_DQ[8]/DDR0_DQ[24] DDR1_DQ[9]/DDR0_DQ[25] DDR1_DQ[10]/DDR0_DQ[26] DDR1_DQ[11]/DDR0_DQ[27] DDR1_DQ[12]/DDR0_DQ[28] DDR1_DQ[13]/DDR0_DQ[29] DDR1_DQ[14]/DDR0_DQ[30] DDR1_DQ[15]/DDR0_DQ[31] DDR1_DQ[16]/DDR0_DQ[48] DDR1_DQ[17]/DDR0_DQ[49] DDR1_DQ[18]/DDR0_DQ[50] DDR1_DQ[19]/DDR0_DQ[51] DDR1_DQ[20]/DDR0_DQ[52] DDR1_DQ[21]/DDR0_DQ[53] DDR1_DQ[22]/DDR0_DQ[54] DDR1_DQ[23]/DDR0_DQ[55] DDR1_DQ[24]/DDR0_DQ[56] DDR1_DQ[25]/DDR0_DQ[57] DDR1_DQ[26]/DDR0_DQ[58] DDR1_DQ[27]/DDR0_DQ[59] DDR1_DQ[28]/DDR0_DQ[60] DDR1_DQ[29]/DDR0_DQ[61] DDR1_DQ[30]/DDR0_DQ[62] DDR1_DQ[31]/DDR0_DQ[63] DDR1_DQ[32]/DDR1_DQ[16] DDR1_DQ[33]/DDR1_DQ[17] DDR1_DQ[34]/DDR1_DQ[18] DDR1_DQ[35]/DDR1_DQ[19] DDR1_DQ[36]/DDR1_DQ[20] DDR1_DQ[37]/DDR1_DQ[21] DDR1_DQ[38]/DDR1_DQ[22] DDR1_DQ[39]/DDR1_DQ[23] DDR1_DQ[40]/DDR1_DQ[24] DDR1_DQ[41]/DDR1_DQ[25] DDR1_DQ[42]/DDR1_DQ[26] DDR1_DQ[43]/DDR1_DQ[27] DDR1_DQ[44]/DDR1_DQ[28] DDR1_DQ[45]/DDR1_DQ[29] DDR1_DQ[46]/DDR1_DQ[30] DDR1_DQ[47]/DDR1_DQ[31]

DDR1_DQ[48] DDR1_DQ[49] DDR1_DQ[50] DDR1_DQ[51] DDR1_DQ[52] DDR1_DQ[53] DDR1_DQ[54] DDR1_DQ[55] DDR1_DQ[56] DDR1_DQ[57] DDR1_DQ[58] DDR1_DQ[59] DDR1_DQ[60] DDR1_DQ[61] DDR1_DQ[62] DDR1_DQ[63]

KBL-RU42_BGA1356

KBL-R U4+2

DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]

DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]

DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]

DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]

DDR1_CAS#/DDR1_CAB[1]/DDR1_M A[15]

DDR1_WE#/DDR1_CA B[2]/DDR1_MA[14]

DDR1_RAS#/DDR1_CAB[3]/DDR1_M A[16]

DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]

DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]

DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]

DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]

DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]

DDR CH - B

3 OF 20

DDR3L / LPDDR3 / DDR4

Interleave / Non-Interleaved

DDR1_DQSN[0]/DDR0_DQSN[2] DDR1_DQSP[0]/DDR0_DQSP[2] DDR1_DQSN[1]/DDR0_DQSN[3] DDR1_DQSP[1]/DDR0_DQSP[3] DDR1_DQSN[2]/DDR0_DQSN[6] DDR1_DQSP[2]/DDR0_DQSP[6] DDR1_DQSN[3]/DDR0_DQSN[7] DDR1_DQSP[3]/DDR0_DQSP[7] DDR1_DQSN[4]/DDR1_DQSN[2] DDR1_DQSP[4]/DDR1_DQSP[2] DDR1_DQSN[5]/DDR1_DQSN[3] DDR1_DQSP[5]/DDR1_DQSP[3]

DDR1_DQSN[6] DDR1_DQSP[6] DDR1_DQSN[7] DDR1_DQSP[7]

DRAM_RESET# DDR_RCOMP[0] DDR_RCOMP[1] DDR_RCOMP[2]

DDR1_CKN[0] DDR1_CKN[1] DDR1_CKP[0] DDR1_CKP[1]

DDR1_CKE[0] DDR1_CKE[1] DDR1_CKE[2] DDR1_CKE[3]

DDR1_CS#[0]

DDR1_CS#[1] DDR1_ODT[0] DDR1_ODT[1]

DDR1_MA[3] DDR1_MA[4]

DDR1_ALERT#

DDR1_PAR

Rev_0.1

AN45 AN46 AP45 AP46

AN56 AP55 AN55 AP53

BB42 AY42 BA42 AW42

AY48 AP50 BA48 BB48 AP48 AP52 AN50 AN48 AN53 AN52 BA43 AY43 AY44 AW44 BB44 AY47 BA44 AW46 AY46 BA46

BB46 BA47

AH66 AH65 AG69 AG70 AR66 AR65 AR61 AR60 AT38 AR38 AT32 AR32

AR25 AR27 AR22 AR21 AN43 AP43 AT13 AR18 AT18 AU18

DDR_B_DQS#[0..7]<21>

DDR_B_D[0..63]<21>

DDR_B_DQS[0..7]<21>

DDR_B_MA[0..16]<21>

DDR_B_CLK#0 DDR_B_CLK#1 DDR_B_CLK0 DDR_B_CLK1

DDR_B_CKE0 DDR_B_CKE1 DDR_B_CKE2 DDR_B_CKE3

DDR_B_CS#0 DDR_B_CS#1

DDR_B_ODT1

DDR_B_MA5 DDR_B_MA9 DDR_B_MA6 DDR_B_MA8 DDR_B_MA7 DDR_B_BG0 DDR_B_MA12 DDR_B_MA11 DDR_B_ACT# DDR_B_BG1 DDR_B_MA13

DDR_B_MA14 DDR_B_MA16 DDR_B_BA0 DDR_B_MA2 DDR_B_BA1 DDR_B_MA10 DDR_B_MA1 DDR_B_MA0

DDR_B_MA3 DDR_B_MA4

DDR_A_DQS#2 DDR_A_DQS2 DDR_A_DQS#3 DDR_A_DQS3 DDR_A_DQS#6 DDR_A_DQS6 DDR_A_DQS#7 DDR_A_DQS7 DDR_B_DQS#2 DDR_B_DQS2 DDR_B_DQS#3 DDR_B_DQS3

DDR_B_DQS#6 DDR_B_DQS6 DDR_B_DQS#7 DDR_B_DQS7 DDR_B_ALERT# DDR_B_PARITY DDR_DRAMRST# SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

DDR_B_CLK#0 <21> DDR_B_CLK#1 <21> DDR_B_CLK0 <21> DDR_B_CLK1 <21>

DDR_B_CKE0 <21> DDR_B_CKE1 <21>

PAD~D

DDR_B_CS#0 <21> DDR_B_CS#1 <21> DDR_B_ODT0 <21> DDR_B_ODT1 <21>

DDR_B_BG0 <21>

DDR_B_ACT# <21> DDR_B_BG1 <21>

DDR_B_BA0 <21>

DDR_B_BA1 <21>

DDR1_PAR,DDR1_ALERT# for DDR4

DDR_B_ALERT# <21>DDR_A_PARITY <20> DDR_B_PARITY <21> DDR_DRAMRST# <20>

DDR4 COMPENSATION SIGNALS

SM_RCOMP0

SM_RCOMP1

SM_RCOMP2

CAD Note: Trace width=12~15 mil, Spacing=20 mils Max trace length= 500 mil

A A

1 2

RC5 121_0402_1%

1 2

RC6 80.6_0402_1%

1 2

RC7 100_0402_1%

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.

Title

ize Document N umber Re v

Size Document Number Re v

Date: Sheet of

Compal Electronics, Inc.

CPU (2/14)

LA-F322P

7 59Wednesday, December 20, 2017

2.0

SPI_MOSI= SPI_IO0 SPI_MISO= SPI_IO1 PCH EDS R0.7 p.235~236

PCH_SPI_CLK PCH_SPI_D1

CXDP@

1 2

PCH_SPI_DO_XDP<14>

PCH_SPI_DO2_XDP<14>

D D

C C

PCH_SPI_CLK_1_R PCH_SPI_CLK_0_R

33_0402_5%

@EMI@

RC28

33P_0402_50V8J

@EMI@

CC7

RC10 1K_0402_1%

CXDP@

1 2

RC11 1K_0402_1%

+3.3V_1.8V_ESPI

33_0402_5%

@EMI@

RC29

33P_0402_50V8J

@EMI@

CC8

PCH_SPI_CS#2<34>

PCH_CL_CLK1<30> PCH_CL_DATA1<30> PCH_CL_RST1#<30>

ESPI_ALERT#<32>

RC21 8.2K_0402_1%

PCH_SPI_D0 PCH_SPI_D2 PCH_SPI_D3 PCH_SPI_CS#0 PCH_SPI_CS#1 PCH_SPI_CS#2

+3.3V_SPI

RC30 1K_0402_5%

RC31 1K_0402_5%

RC316 1K_0402_5%

03/02:follow Intel MOW_2015W W06

PCH_SPI_D2_R1

PCH_SPI_D3_R1

AV2

AW3

AV3

AW2

AU4 AU3 AU2 AU1

M2 M3

J4 V1 V2

G3 G2 G1

AW13

AY11

KBL-RU42_BGA1356

CPU@

UC1E

SPI - FLASH

SPI0_CLK SPI0_MISO SPI0_MOSI SPI0_IO2 SPI0_IO3 SPI0_CS0# SPI0_CS1# SPI0_CS2#

SPI - TOUCH

GPP_D1/SPI1_CLK GPP_D2/SPI1_MISO GPP_D3/SPI1_MOSI GPP_D21/SPI1_IO2 GPP_D22/SPI1_IO3 GPP_D0/SPI1_CS#

C LINK

CL_CLK CL_DATA CL_RST#

GPP_A0/RCIN#

GPP_A6/SERIRQ

PCH_SPI_D1_R1<34>

PCH_SPI_D0_R1<34>

PCH_SPI_CLK_R1<34>

PCH_SPI_D1_R1 PCH_SPI_D0_R1 PCH_SPI_CLK_R1 PCH_SPI_D3_R1

PCH_SPI_CLK_R1 PCH_SPI_D0_R1 PCH_SPI_D1_R1

KBL-R U4+2

LPC

SMBUS, SMLINK

GPP_B23/SML1ALERT#/PCHHOT#

GPP_A5/LFRAME#/ESPI_CS#

GPP_A14/SUS_STAT#/ESPI_RESET#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

SOFTWARE TAA

RPC1

1 8 2 7 3 6 4 5

33_0804_8P4R_5%

1 2

RC407 33_0402_5%

1 2

RC408 33_0402_5%

1 2

RC409 33_0402_5%

1 2

RC410 33_0402_5%

Rev_0.1

GPP_C0/SMBCLK

GPP_C1/SMBDATA

GPP_C2/SMBALERT#

GPP_C3/SML0CLK

GPP_C4/SML0DATA

GPP_C5/SML0ALERT#

GPP_C6/SML1CLK

GPP_C7/SML1DATA

GPP_A1/LAD0/ESPI_IO0 GPP_A2/LAD1/ESPI_IO1 GPP_A3/LAD2/ESPI_IO2 GPP_A4/LAD3/ESPI_IO3

GPP_A10/CLKOUT_LPC1

GPP_A8/CLKRUN#

5 OF 20

PCH_SPI_D1_0_R PCH_SPI_D0_0_R PCH_SPI_CLK_0_R PCH_SPI_D3_0_R

PCH_SPI_D3_1_RPCH_SPI_D3_R1 PCH_SPI_CLK_1_R PCH_SPI_D0_1_R PCH_SPI_D1_1_R

R7 R8 R10

R9 W2 W1

W3 V3 AM7

AY13 BA13 BB13 AY12 BA12 BA11

AW9 AY9 AW11

MEM_SMBCLK MEM_SMBDATA PCH_SMB_ALERT#

SML0_SMBCLK SML0_SMBDATA GPP_C5

SML1_SMBCLK SML1_SMBDATA GPP_B23

ESPI_IO0_R ESPI_IO1_R ESPI_IO2_R ESPI_IO3_R

ESPI_CLK PCI_CLK_LPC1

CLKRUN#

SML0_SMBCLK <28> SML0_SMBDATA <2 8>

SML1_SMBCLK <32> SML1_SMBDATA <3 2>

1 2

RC366

1 2

RC367

1 2

RC368

1 2

RC369

ESPI_CS# <32,33>

ESPI_RESET# <32,33>

1 2

RC16

EMI@

1 2

RC22@ 22_0402_5%

ESPI_CLK_5105

SML0_SMBCLK

SML1_SMBCLK

MEM_SMBCLK

15_0402_5% 15_0402_5% 15_0402_5% 15_0402_5%

15_0402_5%

HECK,LPC_CLK FOR DEBUG CARD?

ESPI_IO0 <32,33> ESPI_IO1 <32,33> ESPI_IO2 <32,33> ESPI_IO3 <32,33>

ESPI_CLK_5105 <32,33>

RF Request

1 2

CC316@RF@ 33P_0402_50V8J

1 2

CC318@RF@ 33P_0402_50V8J

1 2

CC319@RF@ 33P_0402_50V8J

1 2

CC320@RF@ 33P_0402_50V8J

Place close CPU side

MEM_SMBCLK

MEM_SMBDATA

+3.3V_RUN

DMN65D8LDW-7_SOT363-6

3 4

QC2B

DMN65D8LDW-7_SOT363-6

For BR/SB

DDR_XDP_WAN_S MBCLK <14,20,21>

QC2A

DDR_XDP_WAN_S MBDAT <14,20,21>

DDR_XDP_WAN_S MBDAT

DDR_XDP_WAN_S MBCLK

MEM_SMBCLK

MEM_SMBDATA

SML1_SMBCLK

SML1_SMBDATA

SML0_SMBCLK

SML0_SMBDATA

Rese rve

SML0_SMBCLK

SML0_SMBDATA

CLKRUN#

PCH_SMB_ALERT#

TLS C ONFIDENTIALITY

HIGH LOW(DEFAULT)

WEAK INT ERNAL 20K PD

+3.3V_RUN

1 2

RC318 2.2K_0402_5%

1 2

RC319 2.2K_0402_5%

1 2

RC12 1K_0402_5%

1 2

RC14 1K_0402_5%

1 2

RC15 1K_0402_5%

1 2

RC17 1K_0402_5%

1 2

RC347 499_0402_1%

1 2

RC348 499_0402_1%

1 2

RC19 499_0402_1%@

1 2

RC20 499_0402_1%@

1 2

RC27 8.2K_0402_5%LPC@

1 2

RC23 2.2K_0402_5%

ENABLE DISAB LE

+3.3V_ALW_PCH

+3.3V_LAN

+3.3V_ALW_PCH

B B

+3.3V_SPI

128Mb Flash ROM

PCH_SPI_CS#0_R1

PCH_SPI_D2_R1 PCH_SPI_CLK_0_R

1 2

RC37 0_0402_5%

1 2

RC39 33_0402_5%

PCH_SPI_CS#0_R2 PCH_SPI_D1_0_R PCH_SPI_D2_0_R

UC5

/CS

IO1

IO2

GND

W25Q128JVSIQ_SO8

VCC

CLK

IO3

IO0

PCH_SPI_D3_0_R

7 6

PCH_SPI_D0_0_R

+3.3V_SPI

128Mb Flash ROM

UC6

PCH_SPI_CS#1_R1

PCH_SPI_D2_R1

A A

1 2

RC42 0_0402_5%@

1 2

RC43 33_0402_5%

PCH_SPI_CS#1_R2 PCH_SPI_D1_1_R PCH_SPI_D2_1_R

/CS

IO1

IO2

GND

W25Q128JVSIQ_SO8

VCC

CLK

IO3

IO0

PCH_SPI_D3_1_R

PCH_SPI_CLK_1_R

PCH_SPI_D0_1_R

CC9

1 2

0.1U_0201_10V6K

CC10

@ 1 2

0.1U_0201_10V6K

+3.3V_SPI

RC32 0_0402_5%

1 2

RC33 0_0402_5%

1 2

RC34 0_0402_5%

1 2

RC35 0_0402_5%

1 2

RC36 0_0402_5%

1 2

RC38 0_0402_5%

1 2

RC40 0_0402_5%

+3.3V_ALW_PCH

1 2

RC41 0_0402_5%

PCH_SPI_CS#1_R1

PCH_SPI_CS#1

PCH_SPI_D0_R1

PCH_SPI_D0

PCH_SPI_D1_R1

PCH_SPI_D1

PCH_SPI_CLK_R1

PCH_SPI_CLK

PCH_SPI_CS#0_R1

PCH_SPI_CS#0

PCH_SPI_D2_R1

PCH_SPI_D2

PCH_SPI_D3_R1

PCH_SPI_D3

JSPI1

CONN@

GND1

GND2

CVILU_CF5020FD0R0-05-NH

GPP_C5

EC interface

HIGH LOW(DEFAULT)

WEAK INTERNAL 20k PD

GPP_B23

RC317 150K_0402_5%

EXI BOOT STALL BYPASS

HIGH LOW(DEFAULT)

WEAK INTERNAL PD

1 2

RC25 4.7K_0402_5%ESPI@

1 2

ESPI

LPC

ENABLED DIABL ED

+3.3V_ALW_PCH

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.

Title

ize Document N umber Re v

Size Document Number Re v

Date: Sheet of

Compal Electronics, Inc.

CPU (3/14)

LA-F322P

8 59Wednesday, December 20, 2017

2.0

BOOT BIOS Dest i nat i on(Bi t 6)

9/24: Reserve for embedded locat i on ,r ef er I nt el PD G 0. 9

For BR/SB

CPU@

+3.3V_RUN

D D

RC282 100K_0402_5%

RC237 10K_0402_5 %

RC402 49.9K_0402_1%@

RC403 49.9K_0402_1%@

+3.3V_ALW_PCH

RC283 10K_0402_5%

RC330 49.9K_0402_1%

RC331 49.9K_0402_1%

C C

+3.3V_RUN

RC186 4.7K_0402_5%@

PCH_3.3V_TS_EN

SIO_EXT_SCI#

NRB_BIT

LPSS_UART2_RXD

LPSS_UART2_TXD

SIO_EXT_WAKE#

LPSS_UART2_RXD

LPSS_UART2_TXD

TPM_PIRQ#<34>

NO REBOOT STRAP

HIGH LOW(DEFAULT)

Weak IPD

B B

+3.3V_ALW_PCH

RC184 8.2K_0402_5%

No REBOOT

REBOOT ENABLE

BBS_BIT6

DIMM Detect

HIGH LOW

MEDIACARD_IRQ#<29>

RC560 0_0402_ 5%

RC561 0_0402_ 5%

PCH_3.3V_TS_EN<27>

RC405 100K _0402_5%@

TS_I2C_SDA<27> TS_I2C_SCL<27>

I2C1_SDA_TP<38> I2C1_SCK_TP<38>

+3.3V_RUN

10K_0402_5%

RC267

1 2

ONE_DIMM#

10K_0402_5%

RC268

1 2

SBIOS_TX<33>

1 DIMM 2 DIMM

ONE_DIMM#

TPM_PIRQ#_R

NRB_BIT

SIO_EXT_SCI#

BBS_BIT6

GPP_C8

TYPEC_CON_SEL1 TYPEC_CON_SEL2

LPSS_UART2_RXD LPSS_UART2_TXD

I2C3_ANT_SDA I2C3_ANT_SCL

I2C3_ANT_SCL_Q I2C3_ANT_SDA_Q LPSS_UART2_RXD LPSS_UART2_TXD

+3.3V_RUN

+5V_ALW

UC1F

LPSS ISH

AN8

GPP_B15/GSPI0_CS#

AP7

GPP_B16/GSPI0_CLK

AP8

GPP_B17/GSPI0_MISO

AR7

GPP_B18/GSPI0_MOSI

AM5

GPP_B19/GSPI1_CS#

AN7

GPP_B20/GSPI1_CLK

AP5

GPP_B21/GSPI1_MISO

AN5

GPP_B22/GSPI1_MOSI

AB1

GPP_C8/UART0_RXD

AB2

GPP_C9/UART0_TXD

GPP_C10/UART0_RTS#

AB3

GPP_C11/UART0_CTS#

AD1

GPP_C20/UART2_RXD

AD2

GPP_C21/UART2_TXD

AD3

GPP_C22/UART2_RTS#

AD4

GPP_C23/UART2_CTS#

GPP_C16/I2C0_SDA

GPP_C17/I2C0_SCL

GPP_C18/I2C1_SDA

GPP_C19/I2C1_SCL

AH9

GPP_F4/I2C2_SDA

AH10

GPP_F5/I2C2_SCL

AH11

GPP_F6/I2C3_SDA

AH12

GPP_F7/I2C3_SCL

AF11

GPP_F8/I2C4_SDA

AF12

GPP_F9/I2C4_SCL

KBL-RU42_BGA1356

1 2

RC549 0_0402_5%

1 2

RC548 0_0402_5%

1 2

RC547 0_0402_5%

1 2

RC546 0_0402_5%

@ 1 2

RC435 0_0402_5%

1 2

RC434 0_0402_5%

KBL-R U4+2

UART2_RX_I2C3_SDA UART2_TX_I2C3_SCL

+3.3V_+5V_UART

Rev_0.1

GPP_D9 GPP_D10 GPP_D11 GPP_D12

GPP_D5/ISH_I2C0_SDA GPP_D6/ISH_I2C0_SCL

GPP_D7/ISH_I2C1_SDA GPP_D8/ISH_I2C1_SCL

GPP_F10/I2C5_SDA/ISH_I2C2_SDA

GPP_F11/I2C5_SCL/ISH_I2C2_SCL

GPP_D13/ISH_UART0_RXD/SML0BDATA /I2C4B_SDA

GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_S CL

Sx_EXIT_HOLDOFF# / GPP_A12 / BM_BUSY# / ISH_GP6

1 2 3 4

CVILU_CI1804M1HRG-NH

GPP_D15/ISH_UART0_RTS#

GPP_D16/ISH_UART0_CTS#/SML0BALER T#

GPP_C12/UART1_RXD/ISH_UART1_RXD

GPP_C13/UART1_TXD/ISH_UART1_TXD GPP_C14/UART1_RTS#/ISH_UART1_RTS# GPP_C15/UART1_CTS#/ISH_UART1_CTS#

CONN@

JUART1

1 2 3

G1 G2

5 6

GPP_A18/ISH_GP0 GPP_A19/ISH_GP1 GPP_A20/ISH_GP2 GPP_A21/ISH_GP3 GPP_A22/ISH_GP4 GPP_A23/ISH_GP5

6 OF 20

MEM_INTERLEAVED

P2 P3

AR_DET#

P4 P1

M4 N3

N1 N2

ISH_I2C2_SDA

AD11

ISH_I2C2_SCL

AD12

U1 U2 U3 U4

AC1

RTD3_CIO_PWR_EN

AC2 AC3 AB4

AY8 BA8 BB7 BA7 AY7 AW7 AP13

MEM_INTERLEAVED

CLKDET#

TPM_TYPE LID_CL#_PCH

ISH_I2C2_SDA <30> ISH_I2C2_SCL <30>

ISH_UART0_RXD <30>

ISH_UART0_TXD <30> ISH_UART0_RTS# <30>

ISH_UART0_CTS# <30>

SIO_EXT_WAKE# <32>

LCD_CBL_DET# <27>

PAD~D

T258

WWAN

ISH_I2C2_SDA

ISH_I2C2_SCL

WLAN

T18 @PAD~D

LCD_CBL_DET#

TPM_TYPE

T268

Reser ved

RC363 1K_0402_5%

RC362 1K_0402_5%

RC287 100K_0402_5%

RC349 100_0402_1%@

GPP_A GROUP is +1.8V

+3.3V_ALW_PCH +3.3V_ALW_PCH

RC371

10K_0402_5%

1 2

10K_0402_5% RC372

AR_DET#

DIMM TYPE

HIGH Interle ave

RC400 10K_0402_5%

1 2

10K_0402_5% RC401

+1.8V_RUN

1 2

+3.3V_RUN

1 2

AR_DET #

NON ARHIGH

LOW ARLOW Non-Interl eave

LOW

+3.3V_ALW_PCH+3.3V_ALW_PCH

1 2

FOXCONJAE

LOW

HIGH LOW

RC553

10K_0402_5%

RC554

10K_0402_5%

TBDTBD

HIGHHIGH

HIGH

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

ize Document N umber Re v

Size Document Number Re v

Date: Sheet of

Compal Electronics, Inc.

CPU (4/14)

LA-F322P

9 59Wednesday, December 20, 2017

2.0

HIGH LOW(DEFAULT)

Internal 20k PD

A A

LPC SPI

I2C3_ANT_SDA_Q

I2C3_ANT_SCL_Q

+3.3V_RUN

RC513

2.2K_0402_5%

RC512

2.2K_0402_5%

3 4

DMN63D8LDW-7_SOT363-6

QC4B

+1.8V_RUN +1.8V_RUN

QC4A

DMN63D8LDW-7_SOT363-6

+1.8V_RUN

RC511

2.2K_0402_5%

RC510

2.2K_0402_5%

I2C3_ANT_SDA

I2C3_ANT_SCL

RC555

10K_0402_5%

1 2

TYPEC_CON_SEL2TYPEC_CON_SEL1

RC556

10K_0402_5%

Vendor

TYPEC_CON_SE L1 LOW

TYPEC_CON_SE L2

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.

Steamboat MLK 14 nonAR

CPU@

UC1H

PCIE / USB3 / SATA

D D

Card Reader RTS5242----->

Ext USB3 Port 1 Charge (Right) ----->

M.2 3030(WLAN) --->

10/100/1G LAN --->

C C

M.2 3042(SATA Cache )--->

M2 2280 SSD (4 Lane) --->

B B

PCIE_PRX_DTX_N1<29> PCIE_PRX_DTX_P1<29> PCIE_PTX_DRX_N1<29> PCIE_PTX_DRX_P1<29>

USB3_PRX_DTX_N6<36> USB3_PRX_DTX_P6<36> USB3_PTX_DRX_N6<36> USB3_PTX_DRX_P6<36>

PCIE_PRX_DTX_N3<30> PCIE_PRX_DTX_P3<30> PCIE_PTX_DRX_N3<30> PCIE_PTX_DRX_P3<30>

PCIE_PRX_DTX_N4<28> PCIE_PRX_DTX_P4<28> PCIE_PTX_DRX_N4<28> PCIE_PTX_DRX_P4<28>

SATA_PRX_DTX_N1<30> SATA_PRX_DTX_P1<30> SATA_PTX_DRX_N1<30> SATA_PTX_DRX_P1<30>

PCIE_PRX_DTX_N9<35> PCIE_PRX_DTX_P9<35> PCIE_PTX_DRX_N9<35> PCIE_PTX_DRX_P9<35>

PCIE_PRX_DTX_N10<35>

PCIE_PRX_DTX_P10<35> PCIE_PTX_DRX_N10<35> PCIE_PTX_DRX_P10<35>

1 2

RC45 100_0402_1%

CPU_XDP_PRDY#<14> CPU_XDP_PREQ#<14>

PCIE_PRX_DTX_N11<35> PCIE_PRX_DTX_P11<35> PCIE_PTX_DRX_N11<35> PCIE_PTX_DRX_P11<35> PCIE_PRX_DTX_N12<35> PCIE_PRX_DTX_P12<35> PCIE_PTX_DRX_N12<35> PCIE_PTX_DRX_P12<35>

PCIE_RCOMPN PCIE_RCOMPP

H13

PCIE1_RXN/USB3_5_RXN

G13

PCIE1_RXP/USB3_5_RXP

B17

PCIE1_TXN/USB3_5_TXN

A17

PCIE1_TXP/USB3_5_TXP

G11

PCIE2_RXN/USB3_6_RXN

F11

PCIE2_RXP/USB3_6_RXP

D16

PCIE2_TXN/USB3_6_TXN

C16

PCIE2_TXP/USB3_6_TXP

H16

PCIE3_RXN

G16

PCIE3_RXP

D17

PCIE3_TXN

C17

PCIE3_TXP

G15

PCIE4_RXN

F15

PCIE4_RXP

B19

PCIE4_TXN

A19

PCIE4_TXP

F16

PCIE5_RXN

E16

PCIE5_RXP

C19

PCIE5_TXN

D19

PCIE5_TXP

G18

PCIE6_RXN

F18

PCIE6_RXP

D20

PCIE6_TXN

C20

PCIE6_TXP

F20

PCIE7_RXN/SATA0_RXN

E20

PCIE7_RXP/SATA0_RXP

B21

PCIE7_TXN/SATA0_TXN

A21

PCIE7_TXP/SATA0_TXP

G21

PCIE8_RXN/SATA1A_RXN

F21

PCIE8_RXP/SATA1A_RXP

D21

PCIE8_TXN/SATA1A_TXN

C21

PCIE8_TXP/SATA1A_TXP

E22

PCIE9_RXN

E23

PCIE9_RXP

B23

PCIE9_TXN

A23

PCIE9_TXP

F25

PCIE10_RXN

E25

PCIE10_RXP

D23

PCIE10_TXN

C23

PCIE10_TXP

PCIE_RCOMPN

PCIE_RCOMPP

D56

PROC_PRDY#

D61

PROC_PREQ#

BB11

GPP_A7/PIRQA#

E28

PCIE11_RXN/SATA1B_RXN

E27

PCIE11_RXP/SATA1B_RXP

D24

PCIE11_TXN/SATA1B_TXN

C24

PCIE11_TXP/SATA1B_TXP

E30

PCIE12_RXN/SATA2_RXN

F30

PCIE12_RXP/SATA2_RXP

A25

PCIE12_TXN/SATA2_TXN

B25

PCIE12_TXP/SATA2_TXP

KBL-RU42_BGA1356

KBL-R U4+2

SSIC / USB3

USB3_2_RXN/SSIC_RXN USB3_2_RXP/SSIC_RXP

USB3_2_TXN/SSIC_TXN USB3_2_TXP/SSIC_TXP

USB2

USB2_VBUSSENSE

GPP_E9/USB2_OC0# GPP_E10/USB2_OC1# GPP_E11/USB2_OC2# GPP_E12/USB2_OC3#

GPP_E4/DEVSLP0 GPP_E5/DEVSLP1 GPP_E6/DEVSLP2

GPP_E0/SATAXPCIE0/SATAGP0 GPP_E1/SATAXPCIE1/SATAGP1 GPP_E2/SATAXPCIE2/SATAGP2

GPP_E8/SATALED#

Rev_0.1

USB3_1_RXN USB3_1_RXP USB3_1_TXN USB3_1_TXP

USB3_3_RXN USB3_3_RXP USB3_3_TXN USB3_3_TXP

USB3_4_RXN USB3_4_RXP USB3_4_TXN USB3_4_TXP

USB2N_1 USB2P_1

USB2N_2 USB2P_2

USB2N_3 USB2P_3

USB2N_4 USB2P_4

USB2N_5 USB2P_5

USB2N_6 USB2P_6

USB2N_7 USB2P_7

USB2N_8 USB2P_8

USB2N_9 USB2P_9

USB2N_10 USB2P_10

USB2_COMP

USB2_ID

8 OF 20

H8 G8 C13 D13

J6 H6 B13 A13

J10 H10 B15 A15

E10 F10 C15 D15

AB9 AB10

AD6 AD7

AH3 AJ3

AD9 AD10

AJ1 AJ2

AF6 AF7

AH1 AH2

AF8 AF9

AG1 AG2

AH7 AH8

AB6 AG3 AG4

A9 C9 D9 B9

J1 J2 J3

H2 H3 G4

USBCOMP USB2_ID

USB2_VBUSSENSE

USB_OC3#

Rese rve

SATAGP0 M3042_PCIE#_SATA

M2280_PCIE_SATA#

SATALED#

USB3_PRX_DTX_N1 <23>

USB3_PRX_DTX_P1 <23> USB3_PTX_DRX_N1 <23> USB3_PTX_DRX_P1 <2 3>

USB3_PRX_DTX_N2 <30>

USB3_PRX_DTX_P2 <30> USB3_PTX_DRX_N2 <30> USB3_PTX_DRX_P2 <3 0>

USB3_PRX_DTX_N3 <37>

USB3_PRX_DTX_P3 <37> USB3_PTX_DRX_N3 <37> USB3_PTX_DRX_P3 <3 7>

USB3_PRX_DTX_N4 <37>

USB3_PRX_DTX_P4 <37> USB3_PTX_DRX_N4 <37> USB3_PTX_DRX_P4 <3 7>

USB20_N1 <24> USB20_P1 <24>

USB20_N2 <37> USB20_P2 <37>

USB20_N3 <37> USB20_P3 <37>

USB20_N4 <30> USB20_P4 <30>

USB20_N5 <27> USB20_P5 <27>

USB20_N7 <30> USB20_P7 <30>

USB20_N8 <27> USB20_P8 <27>

USB20_N9 <36> USB20_P9 <36>

USB20_N10 <34> USB20_P10 <34>

1 2

RC44 113_0402_1%

USB2_ID <24>

1 2

RC338 1K_0402_5%

USB_OC0# <36> USB_OC1# <37> USB_OC2# <37>

M3042_DEVSLP <30> M2280_DEVSLP <35>

M3042_PCIE#_SATA <32>

M2280_PCIE_SATA# <35>

SATALED# <30,35,39>

-----> Typce-C(Non AR)

-----> M.2 3042(LTE)

-----> Ext USB3 Port 2 (Lert Front)

-----> Ext USB3 Port 3 (Lef t Rear)

-----> Typce-C(Non AR)

-----> Ext USB Port 2(Lef t Front)

-----> Ext USB Port 3 (Lef t Rear)

-----> M2 3042(WWAN)

-----> Camera

-----> M.2 3030(BT)

-----> LCD Touch

-----> Ext USB Port 1 Charge (Right)

-----> USH

NEED DOUBLE C HECK

USB_OC3# USB_OC0# USB_OC1# USB_OC2#

USB2_ID

RPC3

4 5 3 2 1

10K_8P4R_5%

1 2

RC337 10K_0402_5%

6 7 8

+3.3V_ALW_PCH

+3.3V_RUN

M2280_PCIE_SATA# SATAGP0

SATALED#

A A

M3042_PCIE#_SATA

RPC4

4 5 3 2 1

10K_8P4R_5%

6 7 8

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.

Title

ize Document N umber Re v

Size Document Number Re v

Date: Sheet of

Compal Electronics, Inc.

CPU (5/14)

LA-F322P

10 59Wednesday, December 20, 2017

2.0

CLK_PCIE_N0<29>

Cardreader-- ->

D D

WLAN--->

M.2 SDD--->

LAN--->

+3.3V_LAN

C C

+3.3V_ALW_DSW

+1.0V_VCCST

+3.3V_ALW_PCH

B B

+3.3V_1.8V_PGPPA

CLK_PCIE_P0<29>

CLKREQ_PCIE#0<29>

CLK_PCIE_N1<30> CLK_PCIE_P1<30>

CLKREQ_PCIE#1<30>

CLK_PCIE_N3<35>

CLK_PCIE_P3<35>

CLKREQ_PCIE#3<35>

CLK_PCIE_N4<28> CLK_PCIE_P4<28>

CLKREQ_PCIE#4<28>

RL70 10K_0402_5%@

RC323 10K_0402_5%

RC67 1K_0402 _5%

RC71 1K_0402 _5%

RC74 10K_0402_5%@

10/6 depop, prevent singal step.

RC411 10K_0402_5%@

PAD~D

VCCST_PWRGD<14,32,33>

ME_SUS_PWR_ACK<32>

RC550 1K_0402_ 5%

+3.3V_RUN

SUSACK#<32>

SUSACK#_R

@RF@

RC373 0_0402_5% RC189 10K_0402_5%

@RF@

RC374 0_0402_5% RC47 10K_0402_5%

RC50 10K_0402_5%

@RF@

RC376 0_0402_5% RC59 10K_0402_5%

@RF@

RC377 0_0402_5% RC51 10K_0402_5%

RC190 10K_0402_5%

LAN_WAKE#

PCH_PCIE_WAKE#

VCCST_PWRGD

ME_SUS_PWR_ACK

RC77 1K_0402 _5%@ RC78 60.4_0402_1%

RC444 0_0402_5% RC443 0_0402_5%@

1 2

PCH_PLTRST#

H_CPUPWRGD VCCST_PWRGD

PCH_RSMRST#_AND<14,38>

1 2 1 2

PCH_PCIE_WAKE#<32,33>

PM_LANPHY_ENABLE<28>

CLKREQ_PCIE#0_R

CLKREQ_PCIE#1_R

CLKREQ_PCIE#2_R

CLKREQ_PCIE#3_R

CLKREQ_PCIE#4_R

CLKREQ_PCIE#5_R

TC7SH08FU_SSOP5~D

100P_0402_50V8J

CC300ESD@

SYS_PWROK<14,32> PCH_PWROK<47>

PCH_DPWROK<32>

3.3V_CAM_EN#<27>

100P_0402_50V8J

ESD Request:place near CPU side

PCH_PLTRST# SYS_RESET#

PCH_RSMRST#_AND

H_CPUPWRGDH_CPUPWRGD_R VCCST_PWRGD_CPU

ME_SUS_PWR_ACK_R SUSACK#_R

LAN_WAKE#<28,32>

RC311 10K_0 402_5%

RC62 0_0402_5%

1 2

RC244 0_0402_5%

1 2

+3.3V_ALW_PCH

UC7

CC301ESD@

RC215

POP

NO Support Deep sleep

DE-POP

PCH_DPWROK PCH_RSMRST#_AND

A A

1 2

RC215 0_0402_5%NDS3@

100K_0402_1%

0.01UF_0402_25V7K

RC220

CC266

RC75 10K_0402_5%

Support Deep sleep

XDP_DBRESET#<14>

+3.3V_RUN

XDP_DBRESET#

RC225@ 8.2K_0402_5%

RC227@ 8.2K_0402_5%

CPU@

UC1J

D42

CLKOUT_PCIE_N0

C42

CLKOUT_PCIE_P0

AR10

GPP_B5/SRCCLKREQ0#

B42

CLKOUT_PCIE_N1

A42

CLKOUT_PCIE_P1

AT7

GPP_B6/SRCCLKREQ1#

D41

CLKOUT_PCIE_N2

C41

CLKOUT_PCIE_P2

AT8

GPP_B7/SRCCLKREQ2#

D40

CLKOUT_PCIE_N3

C40

CLKOUT_PCIE_P3

AT10

GPP_B8/SRCCLKREQ3#

B40

CLKOUT_PCIE_N4

A40

CLKOUT_PCIE_P4

AU8

GPP_B9/SRCCLKREQ4#

E40

CLKOUT_PCIE_N5

E38

CLKOUT_PCIE_P5

AU7

GPP_B10/SRCCLKREQ5#

KBL-RU42_BGA1356

PCH_PLTRST#_AND

100K_0402_5%

UC1K

AN10

GPP_B13/PLTRST#

SYS_RESET#

AY17

RSMRST#

A68

PROCPWRGD

B65

VCCST_PWRGD

SYS_PWROK

BA20

PCH_PWROK

BB20

DSW_PWR OK

AR13

GPP_A13/SUSWARN#/SUSPWRDNACK

AP11

GPP_A15/SUSACK#

BB15

WAKE#

AM15

GPD2/LAN_WAKE#

AW17

GPD11/LANPHYPC

AT15

GPD7/RSVD

KBL-RU42_BGA1356

RC290 0_0402_5%

ME_RESET#

PLTRST_LAN# <28>

PCH_PLTRST#_EC <33>

RC65

CPU@

SYSTEM POWER MANAGEMENT

1 2

+3.3V_RUN

KBL-R U4+2

CLOCK SIGNALS

PCH_PLTRST#_AND <27,29,30,34,35>

VCCDSW_EN_GPIO<18>

VCCDSW_EN<32>

KBL-R U4+2

74AHC1G09GW_TSSOP5

SYS_RESET#_R

UC12@

KBL-U / KBL-R U4+2

RSVD_E3/XTAL24_IN

RSVD_C7/XTAL24_OUT

XTAL24_IN/NC_2

XTAL24_OUT/NC_1

CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P

GPD8/SUSCLK

XCLK_BIASREF

ALW_PWRGD_3V_5V<38,42>

GPP_B11/EXT_PWR_GATE#

1 2

RC224 1K_0402_5%

if pop UC12, RC291 also need pop(74AHC1G09GW is OD output)

Rev_0.1

XTAL24_IN_U42_CPU XTAL24_IN_U42

XTAL24_OUT_U42_CPU

XTAL24_IN_U22_CPU

E37

XTAL24_OUT_U22_CPU

E35

CLK_ITPXDP_N

F43

CLK_ITPXDP_P

E43

BA17

SUSCLK

XCLK_BIASREF

E42

PCH_RTCX1

AM18

RTCX1 RTCX2

SRTCRST#

RTCRST#

10 OF 20

AM20

AN18 AM16

PCH_RTCX2

SRTCRST#

PCH_RTCRST# <32>

PCH_RTCRST#

CMOS1 m ust take care short & touch risk on layout plac ement

PCH_PLTRST#

PCH_PLTRST#_AND

RC445

1 2

0_0402_5%

Rev_0.1

GPP_B12/SLP_S0#

GPD4/SLP_S3# GPD5/SLP_S4#

GPD10/SLP_S5#

SLP_SUS#

SLP_LAN#

GPD9/SLP_WLAN#

GPD6/SLP_A#

GPD3/PWRBTN#

GPD1/ACPRESENT

GPD0/BATLOW#

GPP_A11/PME#

INTRUDER#

GPP_B2/VRALERT#

11 OF 20

+3.3V_RUN

1 2

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

1 2

RC60 0_0402_5%

1 2

RC325 0_0402_5%

NDS3@

RB751S40T1G_SOD523-2

SIO_SLP_S0#

AT11 AP15 BA16 AY16

AN15 AW15 BB17 AN16

BA15 AY15

PCH_BATLOW#

AU13

AU11

PME#

AP16

INTRUDER#

MPHYP_PWR_EN

AM10 AM11

VRALERT#

RC291

10K_0402_5%

SYS_RESET#

RC417 0_0402_5%

U42@

1 2 1 2

RC418 0_0402_5%

U42@

RC419 0_0402_5%

U22@

1 2 1 2

RC420 0_0402_5%

U22@

1 2

RC297 0_0402_5%

RC298 0_0402_5%

1 2

SUSCLK <30,35>

1 2

RC52 2.7K_0402_1%

1 2

RC324 59_0402_1%

546765_54 6765_201 4WW48 _Skylake_MO W_Rev_1_ 0

RC56 20K_0402_5%

1 2

CC24 1U_0 402_6.3V6K

RC57 20K_0402_5%

1 2

CC25 1U_0 402_6.3V6K

SHORT PADS~D

CMOS1

PLTRST_TPM# <34>

SIO_SLP_SUS#

DC1

2 1

NDS3@

RB751S40T1G_SOD523-2

VCCDSW_EN_Q

DC2

SIO_SLP_S0# <17,34,45> SIO_SLP_S3# <32,33> SIO_SLP_S4# <17,32,43,46> SIO_SLP_S5# <32>

SIO_SLP_SUS# < 32> SIO_SLP_LAN# <32 ,40>

SIO_SLP_WLAN# <32,40> SIO_SLP_A# <32>

SIO_PWRBTN# <14,32>

AC_PRESENT <32>

T115

PAD~D

connect to VCCMPHYGTAON_1P0 enable pin

ESD Request:place near CPU side

XTAL24_OUT_U42 XTAL24_IN_U22 XTAL24_OUT_U22

CLK_ITPXDP_N_R <14> CLK_ITPXDP_P_R <14>

+1.0V_CLK5

For Skylake, pop RC52,depop RC324 For Cannonlake, pop RC324,depop RC52

+RTC_CELL_PCH

@DS3@

RC441

1 2

0_0402_5%

RC442

NDS3@

1 2

0_0402_5%

Support DS3

No Support DS3

'V' mean POP, 'X' mean DE-POP

SYS_RESET#

@ESD@

0.1U_0402_25V6

CC302

For KBL-R U22

U22@

1M_0402_1%

RC46

XTAL24_IN_U22 XTAL24_OUT_U22

1 2

For Skylake,YC1 24 MHz (50 Ohm ESR) For Cannonlake,YC1 38.4 MHz (30 Ohm ESR)

546765_54 6765_201 4WW48 _Skylake_MO W_Rev_1_ 0

For KBL-R U42

U42@

1M_0402_1%

RC415

XTAL24_IN_U42 XTAL24_OUT_U42

PCH_RTCX1 PCH_RTCX2

PCH_PRIM_EN <17,40,44,45,46>

RC439

RC440 RE536RC21 5RC441RC44 2

V V V

X X

+3.3V_ALW_PCH

+3.3V_ALW

POWER_SW#_MB<33,39>

DELL CONFIDENTIAL/PROPRIETARY

Title

ize Document Number R ev

Size Document Number R ev

Date : Sheet of

1 2

For Skylake,YC3 24 MHz (50 Ohm ESR)

RC54 10M_0402_5%

1 2

RC296 0_0402_5%

8/21 can change to 10K for merge to RP

PCH_BATLOW#

AC_PRESENT

INTRUDER#

MPHYP_PWR_ENPCH_PWROK

VRALERT#

Compal Electronics, Inc.

SIO_SLP_S3#

SIO_SLP_S5# SIO_SLP_S4# SIO_SLP_A#

PCH_RTCRST#

SYS_RESET#

SIO_SLP_S0#

CPU (6/14)

LA-F322P

SIO_SLP_LAN#

SUSCLK

PCH_RTCX2_R

RC72 8.2K_0402_5%

RC243 10K_0402_5%

JAPS1

GND

CONN@

ACES_50506-01841-P01

11 59Wednesday, December 20, 2017

U22@

CC21

1 2

RC69 1M_0402_5%

RC387 10K_0402_5%@

RC73 10K_0402_5%

RC344 10K_0402_5%@

RC68 10K_0402_5%@

RC48 1K_0402_5%@

12P_0402_50V8J

U22@

YC1

24MHZ_12PF_X3G024 000DC1H

U22@

CC22

1 2

12P_0402_50V8J

U42@

CC334

1 2

12P_0402_50V8J

U42@

YC3

24MHZ_12PF_X3G024 000DC1H

U42@

CC335

1 2

12P_0402_50V8J

CC23

1 2

15P_0402_50V8J

YC2

32.768KHZ_12.5PF_9H03200042

ESR MAX=50k ohm

CC26

1 2

12P_0402_50V8J

+RTC_CELL_PCH

1 2

2.0

+3.3V_ALW_DSW

+3.3V_ALW_PCH

+3.3V_ALW

+1.0V_VCCSTG

PCH_JTAG_TDI

PCH_JTAG_TDO

PCH_JTAG_TMS

1 2

RC86 51_0402_5%

Service Mode Switch: Add a switch to ME_FWP signal to unlock the ME region and allow the ent ir e r egi on of t he S PI f la sh to be updat ed us i ng FPT.

+3.3V_ALW_PCH

ME_FWP PCH has internal 20K PD. (suspend power rail)

FLASH DESCRIPTOR SECURITY OVERRIDE

LOW = ENABLE (DEFAULT) -->Pin1 & Pin3 short HIGH = DISABLE (ME can update) -->Pin2 & Pin3 short

CAM_MIC_CBL_DET# <27>

CONTACTLESS_DET# <34>

HOST_SD_WP# <29>

AUD_PWR_EN <31>

0.1U_0402_25V6

@ESD@

CC304

CPU MISC

KBL-R U4+2

CC332

RF@

2.2P_0402_50V8C

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.

Rev_0.1

JTAG

PROC_TCK

PROC_TDI PROC_TDO PROC_TMS

PROC_TRST#

PCH_JTAG_TCK

PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS

PCH_TRST#

JTAGX

4 OF 20

GPP_A17/SD_PWR_EN#/ISH_GP7

CC333

RF@

2.2P_0402_50V8C

CPU_XDP_TCLK XDP_JTAGX

RC328 0_0402_5%

CPU_XDP_TCLK

B61

CPU_XDP_TDI

D60

CPU_XDP_TDO

A61

CPU_XDP_TMS

C60

CPU_XDP_TRST#

B59

PCH_JTAG_TCK

B56

PCH_JTAG_TDI

D59

PCH_JTAG_TDO

A56

PCH_JTAG_TMS

C59

CPU_XDP_TRST#

C61

XDP_JTAGX

A59

SDIO / SDXC

GPP_G0/SD_CMD GPP_G1/SD_DATA0 GPP_G2/SD_DATA1 GPP_G3/SD_DATA2 GPP_G4/SD_DATA3

GPP_A16/SD_1P8_SEL

RC87 1K_0402_5%@

Rev_0.1

GPP_G5/SD_CD# GPP_G6/SD_CLK

GPP_G7/SD_WP

SD_RCOMP

GPP_F23

7 OF 20

1 2

AB11 AB13 AB12 W12 W11 W10 W8 W7

BA9 BB9

AB7

AF13

1 2

CPU_XDP_TCLK <14> CPU_XDP_TDI <14> CPU_XDP_TDO <14> CPU_XDP_TMS <14> CPU_XDP_TRST# <14>

PCH_JTAG_TCK <14> PCH_JTAG_TDI <14> PCH_JTAG_TDO <14> PCH_JTAG_TMS <14>

+1.0V_VCCSTG

CONTACTLESS_DET#

AUD_PWR_EN

SD_RCOMP

RC96 200_0402_1%

PCH_JTAG_TDO PCH_JTAG_TDI XDP_JTAGX

0.1U_0402_25V6

@ESD@

CC303

1 2

ESD request,Place near CPU side.

CPU@

D D

+1.0V_VCCST

RC79 49 .9_0402_1%@

RC80 1K_0402_5%

+1.0V_VCCSTG

RC83 1K_0402_5%

+3.3V_RUN

RC414 10K_ 0402_5%

RC413 10K_ 0402_5%

C C

B B

RC278 10K_ 0402_5%

RC272 10K_ 0402_5%

RC279 10 K_0402_5%

RC345 100K_0402_5%

RC292 10 K_0402_5%

+3.3V_ALW_PCH

RC346 10K_ 0402_5%

RC288 10K_0402_5%

H_CATERR#

H_THERMTRIP#

PROCHOT#

TOUCHPAD_INTR#

CAM_MIC_CBL_DET#

CONTACTLESS_DET#

TOUCH_SCREEN_PD#

AUD_PWR_EN

IR_CAM_DET#

HOST_SD_WP#

SIO_EXT_SMI#

KB_DET#

HDA_SYNC_R<31>

HDA_BIT_CLK_R<31>

HDA_SDOUT_R<31>

HDA_RST#_R<31>

Close to RC93

TOUCH_SCREEN_PD# don't move to RPC,

ME_FWP_PCH

HDA_BIT_CLK_R

PECI_EC<32>

PROCHOT#<32,47,50>

H_THERMTRIP#<20,21,33>

TOUCH_SCREEN_DET#<27>

1 2

RC92 33_0402_5%

1 2

RC93 33_0402_5%EMI@

1 2

RC94 33_0402_5%

1 2

RC223 1K_0402_5%

1 2

RC95 33_0402_5%

47P_0402_50V8J

RF@

CC27

1 2

RC84 499_0402_1%

XDP_OBS0_R<14> XDP_OBS1_R<14>

T10

PAD~D

TOUCH_SCREEN_PD#<27> TOUCHPAD_INTR#<32,38>

RC88

49.9_0402_1%

IR_CAM_DET#<27>

3MM_CAM_DET#<27>

KB_DET#<38>

SPKR<31>

RC89

HDA_SYNC HDA_BIT_CLK HDA_SDOUT

HDA_SDIN0<31>

HDA_RST#

PROCHOT#_R H_THERMTRIP#

XDP_OBS2_R

SIO_EXT_SMI#

TOUCHPAD_INTR#

CPU_POPIRCOMP PCH_POPIRCOMP

EDRAM_OPIO_RCOMP

EOPIO_RCOMP

RC90

49.9_0402_1%

IR_CAM_DET#

3MM_CAM_DET#

KB_DET#

H_CATERR#

RC91

49.9_0402_1%

D63 A54 C65 C63 A65

C55 D55 B54 C56

BA5 AY5

AT16 AU16

H66 H65

UC1G

BA22

HDA_SYNC/I2S0_SFRM

AY22

HDA_BLK/I2S0_SCLK

BB22

HDA_SDO/I2S0_TXD

BA21

HDA_SDI0/I2S0_RXD

AY21

HDA_SDI1/I2S1_RXD

AW22

HDA_RST#/I2S1_SCLK

GPP_D23/I2S_MCLK

AY20

I2S1_SFRM

AW20

I2S1_TXD

AK7

GPP_F1/I2S2_SFRM

AK6

GPP_F0/I2S2_SCLK

AK9

GPP_F2/I2S2_TXD

AK10

GPP_F3/I2S2_RXD

GPP_D19/DMIC_CLK0

GPP_D20/DMIC_DATA0

GPP_D17/DMIC_CLK1

GPP_D18/DMIC_DATA1

AW5

GPP_B14/SPKR

KBL-RU42_BGA1356

UC1D

CATERR# PECI PROCHOT# THERMTRIP# SKTOCC#

BPM#[0] BPM#[1] BPM#[2] BPM#[3]

GPP_E3/CPU_GP0

GPP_E7/CPU_GP1 GPP_B3/CPU_GP2 GPP_B4/CPU_GP3

PROC_POPIRCOMP PCH_OPIRCOMP OPCE_RCOMP OPC_RCOMP

KBL-RU42_BGA1356

CPU@

AUDIO

RF Request. Place near CPU side (Intel MOW)

+3.3V_ALW_PCH +3.3V_ALW_PCH

ENABLE DISAB LE

SPKR

RC187 4.7K_0402_5%

Flash Descriptor Security override

HIGH LOW(DEFAULT)

RC183 8.2K_0402_5%

TOP SWAP STRAP

A A

HIGH LOW(DEFAULT)

nternal 20k PD

HDA_SDOUT

DISABLE

ENABLE

HDA_RST# HD A_SDIN0 HDA_SDOUT

CC331

RF@

2.2P_0402_50V8C

1 2

RC81 51_0402_5%

1 2

RC82 100_0402_5%

1 2

RC130 51_0402_5%

ME_FWP_PCHME_FWP

1 2

RC221 0_0402_5%

PT,ST pop RC222 and SW1; MP pop RC221

RC222

1K_0402_5%

1 2

ME_FWP<32>

0.1U_0402_25V6

@ESD@

CC305

ME_FWP_PCH

H_THERMTRIP#

0.1U_0402_25V6

@ESD@

CC312

SW1

SS3-CMFTQR9_3P

PROCHOT#

0.1U_0402_25V6

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

ize Document N umber Re v

Size Document Number Re v

Date: Sheet o f

Compal Electronics, Inc.

CPU (7/14)

LA-F322P

@ESD@

CC310

2.0

12 59Wednesday, December 20, 2017

2.0

D D

CFG[0..19]<14>

CFG[2][5][6][7] for SKYLAKE-H CPU CFG strap pin

RC113 10K_0402_1%

CFG0

RC112 10K_0402_1%

RC110 10K_0402_1%

Stall reset sequence

HIGH(DEFAULT ) LOW

C C

RC109 1K_0402_5%

eDP enable

HIGH(DEFAULT ) LOW

B B

No stall(Normal Operat i on)

ta ll

CFG4

Disa bled Enabled

+1.0V_PRIM_XDP

RC114 49.9_0402_1%

RC115 1.5K_0402_5%

ITP_PMODE<14>

T16

PAD~D

T17

PAD~D

1 2

U42@

RC436 0_0402_5%

CFG_RCOMP

ITP_PMODE

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15

CFG16 CFG17

CFG18 CFG19

UC1S

E68

CFG[0]

B67

CFG[1]

D65

CFG[2]

D67

CFG[3]

E70

CFG[4]

C68

CFG[5]

D68

CFG[6]

C67

CFG[7]

F71

CFG[8]

G69

CFG[9]

F70

CFG[10]

G68

CFG[11]

H70

CFG[12]

G71

CFG[13]

H69

CFG[14]

G70

CFG[15]

E63

CFG[16]

F63

CFG[17]

E66

CFG[18]

F66

CFG[19]

E60

CFG_RCOMP

ITP_PMODE

AY2

RSVD_AY2

AY1

RSVD_AY1

RSVD_D1

RSVD_D3

K46

RSVD_K46

K45

RSVD_K45

AL25

RSVD_AL25

AL27

RSVD_AL27

C71

RSVD_C71

B70

RSVD_B70

F60

RSVD_F60

A52

RSVD_A52

BA70

RSVD_TP_BA70

BA68

RSVD_TP_BA68

J71

RSVD_J71

J68

RSVD_J68

F65

VSS_F65

G65

VSS_G65

F61

RSVD_F61

E61

RSVD_E61

KBL-RU42_BGA1356

CPU@

KBL-R U4+2

RESERVED SIGNALS-1

Rev_0.1

RSVD_TP_BB68 RSVD_TP_BB69

RSVD_TP_AK13 RSVD_TP_AK12

RSVD_BB2 RSVD_BA3

RSVD_D5 RSVD_D4 RSVD_B2 RSVD_C2

RSVD_B3 RSVD_A3

RSVD_AW1

RSVD_E1 RSVD_E2

RSVD_BA4 RSVD_BB4

RSVD_A4 RSVD_C4

RSVD_A69 RSVD_B69

RSVD_AY3

RSVD_D71 RSVD_C70

RSVD_C54 RSVD_D54

VSS_AY71

ZVM#

RSVD_TP RSVD_TP

MSM#

PROC_SELECT#

19 OF 20

UC1T

BB68 BB69

AK13 AK12

BB2 BA3

AU5

TP5

AT5

TP6

D5 D4 B2 C2

B3 A3

AW1

E1 E2

BA4 BB4

A4 C4

BB5

TP4

A69 B69

AY3

D71 C70

C54 D54

AY4

TP1

BB3

TP2

AY71 AR56

AW71 AW70

AP56 C64

T12

PAD~D

T13

PAD~D

T15

PAD~D

T128

PAD~D

T129

PAD~D

T130

PAD~D

T126

PAD~D

T127

PAD~D

T113

PAD~D

T114

PAD~D

1 2

RC120 100K_0402_5%@

For Skylake , RC120 depop For Cannonlake, RC120 pop

546765_546765_2014WW48_ Skylake_MOW_R ev_1_0

1/5 2014 WW52 MOW reserve to support Cannonlake-U PCH compatibility

close UC1.U11/U12 and <400mil

1 2

RC313 0_0402_5%

+1.0V_VCCST

+VCC_1P8+ 1.8V_PRIM

AW69 AW68

AU56

AW48

U12 U11

H11

CC222

1U_0402_6.3V6K

KBL-RU42_BGA1356

RSVD_AW69 RSVD_AW68 RSVD_AU56 RSVD_AW48

RSVD_U12 RSVD_U11 RSVD_H11

SPARE

Rev_0.1

RSVD_F6

RSVD_C11 RSVD_B11 RSVD_A11 RSVD_D12 RSVD_C12 RSVD_F52

20 OF 20

C11 B11 A11 D12 C12 F52

KBL-R U4+2

CPU@

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.

Title

ize Document N umber Re v

Size Document Number Re v

Date: Sheet o f

Compal Electronics, Inc.

CPU (8/14)

LA-F322P

13 59Wednesday, December 20, 2017

2.0

+1.0V_PRIM

1 2

RC216 0_0603_5%

+1.0V_PRIM_XDP

0.1U_0201_10V6K

CC28

D D

Place near JXDP1

VCCST_PWRGD<11,32,33>

PCH_RSMRST#_AND<11,38>

+1.0VS_VCCIO

C C

+1.0V_VCCST

+1.0V_PRIM_XDP

CC29

XDP_OBS0_R<12> XDP_OBS1_R<12>

RC123 1K_0402_5%@

RC124CXDP@

PCH_SPI_DO_XDP<8>

SYS_PWROK<11,32>

RC132 150_0402_5%

RC218 150_0402_5%@

RC219 10K_0402_5%@

RC239 0_0402_5%

CXDP@

RC240 0_0402_5%

CXDP@

RC5 need to close to JCPU1

1 2

1K_0402_5%

FIVR_EN CFG0

RC217 0_0402_5%

RC126 1K_0402_5%@ RC128 0_0402_5%

CXDP@

RC129 0_0402_5%

DDR_XDP_WAN_S MBDAT<8,20,21>

DDR_XDP_WAN_S MBCLK<8,20,21>

FIVR_EN_R

FIVR_EN

CPU_XDP_PREQ#<10>

CPU_XDP_PRDY#<10>

1 2 1 2

1 2 1 2 1 2 1 2

PCH_JTAG_TCK<12>

CPU_XDP_TCLK<12>

CPU XDP

H_VCCST_PWRGD_XD P

SIO_PWRBTN#<11,32>

CPU_XDP_PREQ# CPU_XDP_PRDY#

RESET_OUT#_R

CPU_XDP_TCLK

+1.0V_PRIM_XDP

CFG0 CFG1

CFG2 CFG3

XDP_OBS0 XDP_OBS1

CFG4 CFG5

CFG6 CFG7

FIVR_EN_R

XDP_PRSNT_PIN1

13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57

JXT_FP270H-061G1AM

CXDP@

1 2

RC121 0_0402_5%

1 2

RC122 0_0402_5%@

CONN@

JXDP1

112

334

556

778

9910

111112

595960 61

GND62GND

CFG3

+1.0V_PRIM_XDP

CFG17 CFG16

CFG8 CFG9

CFG10 CFG11

CFG19 CFG18

CFG12 CFG13

CFG14 CFG15

ITP_PMODE XDP_DBRESET#

TDO_XDP TRST#_XDP TDI_XDP XDP_TMS

CFG[0..19]<13>

CLK_ITPXDP_P_R <11> CLK_ITPXDP_N_R <11>

ITP_PMODE <13> XDP_DBRESET# <11>

PCH_SPI_DO2_XDP <8>

+3.3V_RUN

CC30

0.1U_0201_10V6K

TDO_XDP

TDI_XDP

XDP_TMS

TRST#_XDP

RUNPWROK<32>

UC8

VCC

1OE

2OE

3OE

4OE

74CBTLV3126BQ_DHVQFN14_2P5X3

CPU_XDP_TMS

RC131 51_0402_5%

CPU_XDP_TDI

RC134 51_0402_5%

CPU_XDP_TDO

RC135 100_0402_5%

CPU_XDP_TRST#

RC136

CPU_XDP_TCLK

RC139 51_0402_5%

GND PAD

1 2

GND

51_0402_5%

CPU_XDP_TDO <12>

CPU_XDP_TDI <12>

CPU_XDP_TMS <12>

CPU_XDP_TRST# <12>

+1.0V_VCCSTG

+3.3V_RUN

XDP_DBRESET#

+1.0V_PRIM_XDP

B B

A A

RC137 3K_0402_5%

RC138 51_0402_5%

CPU_XDP_PREQ#

+3.3V_ALW_PCH

RC133

1.5K_0402_5%

1 2

CXDP@

PCH_SPI_DO_XDP

RESET_OUT#_R

0.1U_0402_25V6

CC33@

Place near JXDP1.47

Place near JXDP1.48

XDP_DBRESET#

0.1U_0402_25V6

CXDP@

CC32

SIO_PWRBTN#

Place near JXDP1.41

+3.3V_ALW_DSW

1.5K_0402_5%

1 2

0.1U_0402_25V6

XDP_TMS

RC241

CC269

TDO_XDP H_VCCST_PWRGD_XD P CPU_XDP_TRST#

0.1U_0402_25V6

@ESD@

CC306

ESD request,Place near JXDP1 side. ES D request,Place near UC8 side.

TDI_XDP

TDO_XDP

0.1U_0402_25V6

@ESD@

CC307

1 2

RC228 0_0402_5%

1 2

RC229 0_0402_5%

1 2

RC230 0_0402_5%

0.1U_0402_25V6

@ESD@

CC308

PCH_JTAG_TMS <12>

PCH_JTAG_TDI <12>

PCH_JTAG_TDO <12>

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.

Title

ize Document N umber Re v

Size Document Number Re v

Date: Sheet o f

Compal Electronics, Inc.

CPU (9/14)

LA-F322P

14 59Wednesday, December 20, 2017

2.0

+VCC_CORE: 0.3~1.35V

D D

T122

PAD~D

T123

PAD~D

C C

+VCC_CORE +VCC_CORE

+VCC_CORE_G0

+VCC_CORE_G1

UC1L

A30

VCC_A30

A34

VCC_A34

A39

VCC_A39

A44

VCC_A44

AK33

VCC_AK33

AK35

VCC_AK35

AK37

VCC_AK37

AK38

VCC_AK38

AK40

VCC_AK40

AL33

VCC_AL33

AL37

VCC_AL37

AL40

VCC_AL40

AM32

VCC_AM32

AM33

VCC_AM33

AM35

VCC_AM35

AM37

VCC_AM37

AM38

VCC_AM38

G30

VCC_G30

K32

RSVD

AK32

RSVD

AB62

VCCOPC_AB62

P62

VCCOPC_P62

V62

VCCOPC_V62

H63

VCC_OPC_1P8_H63

G61

VCC_OPC_1P8_G61

AC63

VCCOPC_SENSE

AE63

VSSOPC_SENSE

AE62

VCCEOPIO

AG62

VCCEOPIO

AL63

VCCEOPIO_SENSE

AJ62

VSSEOPIO_SENSE

KBL-RU42_BGA1356

CPU@

KBL-R U4+2

CPU POWER 1 OF 4

Rev_0.1

VCC_G32 VCC_G33 VCC_G35 VCC_G37 VCC_G38 VCC_G40 VCC_G42

VCC_J30 VCC_J33 VCC_J37

VCC_J40 VCC_K33 VCC_K35 VCC_K37 VCC_K38 VCC_K40 VCC_K42 VCC_K43

VCC_SENSE VSS_SENSE

VIDALERT#

VIDSCK

VIDSOUT

VCCSTG_G20

12 OF 20

G32 G33 G35 G37 G38 G40 G42 J30 J33 J37 J40 K33 K35 K37 K38 K40 K42 K43

E32 E33

B63 A63 D64

G20

VCCSENSE VSSSENSE

H_CPU_SVIDALRT# VIDSCLK

VIDSOUT

+1.0V_VCCSTG_R

VIDSCLK <47>

+VCC_CORE

RC140

100_0402_1%

1 2

RC141

100_0402_1%

1 2

RC143 0_0603_5%

VCCSENSE <47> VSSSENSE <47>

+1.0V_VCCSTG

VIDSCLK

RF Request

1 2

CC321@RF@ 33P_0402_50V8J

Place close CPU side

PSC(Primary side cap) : Place as close to the packag BSC(Backside cap) : Place on secondary side, underneath the package

Component placement order: Package edge > 0402 caps > 0805 caps > Bulk caps >Power source

e as possible

B B

SVID ALERT

VIDALERT_N<47>

SVID DATA

A A

VIDSOUT<47>

+1.0V_VCCST

1 2

+1.0V_VCCST

1 2

56_0402_1%

RC152

100_0402_1%

RC157

CAD Note: Place the PU resistors close to CPU

RC204 close to CPU 300 - 1500mils

H_CPU_SVIDALRT#

RC153220_0402_5%

CAD Note: Place the PU resistors close to CPU

RC208close to CPU 300 - 1500mils

VIDSOUT

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.

Title

ize Document N umber Re v

Size Document Number Re v

Date: Sheet o f

Compal Electronics, Inc.

CPU (10/14)

LA-F322P

15 59Wednesday, December 20, 2017

2.0

+VCCGT: 0.3~1.35V +VCCGTX : 0.3~1.35V

KBL-R 4+2 and KBL-U 2+2&2+3e opt i on ( pl ace on po wer page)

+VCC_GT_+VCC_CORE

KBL-R U4+2

CPU@

D D

+VCC_GT

C C

VCC_GT_SENSE<47> VSS_GT_SENSE<47>

B B

1 2

RC437 0_0402_5%

+VCC_GT

RC161

100_0402_1%

1 2

VCC_GT_SENSE VSS_GT_SENSE

RC163

100_0402_1%

UC1M

KBL-U / KBL-R U4+2

A48

VCCGT/VCCCORE_5

A53

VCCGT/VCCCORE_6

J43

VCCGT/VCCCORE_44

J45

VCCGT/VCCCORE_45

J46

VCCGT/VCCCORE_46

J48

VCCGT/VCCCORE_47

J50

VCCGT/VCCCORE_48

J52

VCCGT/VCCCORE_49

K48

VCCGT/VCCCORE_57

K50

VCCGT/VCCCORE_58

K52

VCCGT/RSVD_6

A58

VCCGT

A62

VCCGT

A66

VCCGT

AA63

VCCGT

AA64

VCCGT

AA66

VCCGT

AA67

VCCGT

AA69

VCCGT

AA70

VCCGT

AA71

VCCGT

AC64

VCCGT

AC65

VCCGT

AC66

VCCGT

AC67

VCCGT

AC68

VCCGT

AC69

VCCGT

AC70

VCCGT

AC71

VCCGT

J53

VCCGT

J55

VCCGT

J56

VCCGT

J58

VCCGT

J60

VCCGT

K53

VCCGT

K55

VCCGT

K56

VCCGT

K58

VCCGT

K60

VCCGT

L62

VCCGT

L63

VCCGT

L64

VCCGT

L65

VCCGT

L66

VCCGT

L67

VCCGT

L68

VCCGT

L69

VCCGT

L70

VCCGT

L71

VCCGT

M62

VCCGT

N63

VCCGT

N64

VCCGT

N66

VCCGT

N67

VCCGT

N69

VCCGT

J70

VCCGT_SENSE

J69

VSSGT_SENSE

KBL-RU42_BGA1356

CPU POWER 2 OF 4

KBL-U / KBL-R U4+2

VCCGTX_AK42/VCCCORE_12 VCCGTX_AK43/VCCCORE_13 VCCGTX_AK45/VCCCORE_14 VCCGTX_AK46/VCCCORE_15 VCCGTX_AK48/VCCCORE_16 VCCGTX_AK50/VCCCORE_17

VCCGTX_AL43/VCCCORE_21 VCCGTX_AL46/VCCCORE_22

VCCGTX_AL50/VCCCORE_23 VCCGTX_AM48/VCCCORE_29 VCCGTX_AM50/VCCCORE_30 VCCGTX_AM52/VCCCORE_31

VCCGTX_AK52/RSVD_5

Rev_0.1

VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT

VCCGTX_AK53 VCCGTX_AK55 VCCGTX_AK56 VCCGTX_AK58 VCCGTX_AK60 VCCGTX_AK70

VCCGTX_AL53 VCCGTX_AL56

VCCGTX_AL60 VCCGTX_AM53 VCCGTX_AM56 VCCGTX_AM58 VCCGTX_AU58 VCCGTX_AU63 VCCGTX_BB57 VCCGTX_BB66

VCCGTX_SENSE

VSSGTX_SENSE

13 OF 20

N70 N71 R63 R64 R65 R66 R67 R68 R69 R70 R71 T62 U65 U68 U71 W63 W64 W65 W66 W67 W68 W69 W70 W71 Y62

AK42 AK43 AK45 AK46 AK48 AK50 AL43 AL46 AL50 AM48 AM50 AM52 AK52

AK53 AK55 AK56 AK58 AK60 AK70 AL53 AL56 AL60 AM53 AM56 AM58 AU58 AU63 BB57 BB66

AK62 AL61

+VCC_GT

Follow KBL-R_U42_Processor_Line_BGA1356_Ballout_Rev1p0

KBL-R 4+2 and KBL-U 2+2&2+3e opt i on ( pl ace on po wer pa

+VCC_GT_+VCC_CORE

1 2

RC438 0_0402_5%

+VCC_GT

+VCC_GTUS

Reserve for soldering

ge)

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.

Title

ize Document N umber Re v

Size Document Number Re v

Date: Sheet o f

Compal Electronics, Inc.

CPU (11/14)

LA-F322P

16 59Wednesday, December 20, 2017

2.0

+5V_ALW

CZ104

CC253

UZ34

1U_0402_6.3V6K

+1.2V_MEM

CC250

1U_0402_6.3V6K

1 2

RZ119 0_0 402_5%

UZ26

VIN1

VIN2

VIN thermal

VBIAS

TPS22961DNYR_WSON8

CC251

1U_0402_6.3V6K

SIO_SLP_S0#

SIO_SLP_S3#

AND

+VCCPLL_OC source

+1.2V_MEM+1.2V_MEM_CPUCLK

1 2

RC231 0_0402_5%

D D

PSC

CC177

CC176

10U_0402_6.3V6M

PSC

22U_0603_6.3V6M

CC294

+1.0V_VCCST

C C

B B

PSC

CC195

1U_0402_6.3V6K

VDDQ: 8.45A

CC179

CC178

10U_0402_6.3V6M

22U_0603_6.3V6M

CC296

CC295

+1.0V_VCCSTG

BSC

CC297

CC199

1U_0402_6.3V6K

+1.2V_MEM_CPUCLK

10U_0402_6.3V6M

+VCC_SFR_OC

CC288

+1.0V_VCCST source

+1.2V_MEM

CC322

RF@

1U_0402_6.3V6K

2.2P_0402_50V8C

RF Request

UC1N

AU23

VDDQ_AU23

AU28

VDDQ_AU28

AU35

VDDQ_AU35

AU42

VDDQ_AU42

BB23

VDDQ_BB23

BB32

VDDQ_BB32

BB41

VDDQ_BB41

BB47

VDDQ_BB47

BB51

VDDQ_BB51

AM40

VDDQC

A18

VCCST

A22

VCCSTG_A22

AL23

VCCPLL_OC

K20

VCCPLL_K20

K21

VCCPLL_K21

KBL-RU42_BGA1356

+1.0V_VCCST

CZ102 1U_0402_6.3V6K

VCCSTG_EN

AK28 AK30 AL30 AL42 AM28 AM30 AM42

AK23 AK25 G23 G25 G27 G28 J22 J23 J27 K23 K25 K27 K28 K30

AM23 AM22

H21 H20

1 2

+1.0VS_VCCIO

VCCIO_SENSE VSSIO_SENSE

+VCC_SA

+1.0VS_VCCIO

RC166

100_0402_1%

VSA_SEN- <47> VSA_SEN+ <47>

1 2

RC165

100_0402_1%

VCCIO_SENSE <45> VSSIO_SENSE <45>

RC167

100_0402_1%

PCH_PRIM_EN<11,40,44,45,46>

SIO_SLP_S4#<11,17,32,43,46>

KBL-R U4+2

CPU@

CPU POWER 3 OF 4

Rev_0.1

VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO

VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA

VCCIO_SENSE VSSIO_SENSE

VSSSA_SENSE

VCCSA_SENSE

14 OF 20

+VCC_SA

RC168 100_0402_1%

PSC

U22@

CC202

CC341

CC202

22U_0603_6.3V6M

1U_0402_6.3V6K

22U_0402_6.3V6M

U42@

1 2

RZ120 0_0402_5%

+3.3V_ALW

1 2

0.1U_0402_10V7K

TC7SH08FU_SSOP5~D

+1.0VS_VCCIO

PSC

CC252

1U_0402_6.3V6K

+1.0V_VCCSTG source

+VCC_SFR_OC

VOUT

GND

HIGH

HIGH LOW LOW

S0Ix

LOW

HIGH

LOW

1 2

CZ103 0.1U_0201_10V6K

+1.0V_VCCST+1.0V_VCC STG

1 2

RZ151 0_0603_5%

+1.0V_PRIM

CZ100 1U_0402_6.3V6K

SIO_SLP_S4#<11,17,32,43,46>

A A

+1.0V_PRIM

+5V_ALW

UZ21

VIN1

VIN2

VIN thermal

VBIAS

TPS22961DNYR_WSON8

4.4mohm /6A TR=12.5us@Vin=1.05V

VOUT

GND

+1.0V_VCCST_C

PJP1

PAD-OPEN1x1m

1 2

CZ101 0.1U_0201_10V6K

+1.0V_VCCST

SIO_SLP_S0#<11,34,45>

RUN_ON<32,33,40,45>

TC7SH08FU_SSOP5~D

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.

CZ105 1U_0402_6.3V6K

+5V_ALW

+3.3V_ALW

UZ35

1 2

RZ320 0_0402_5%

VCCSTG_EN

1 2

UZ19

VIN1 VIN2

VIN thermal

VBIAS

TPS22961DNYR_WSON8

4.4mohm /6A TR=12.5us@Vin=1.05V

VOUT

GND

PJP2 PAD-OPEN1x1m

+1.0V_VCCSTG_C

DELL CONFIDENTIAL/PROPRIETARY

pop option with UZ19

1 2

CZ106 0.1U_0201_10V6K

Compal Electronics, Inc.

Title

ize Document N umber Re v

Size Document Number Re v

Date: Sheet o f

Compal Electronics, Inc.

CPU (12/14)

LA-F322P

17 59Wednesday, December 20, 2017

2.0

+1.0V_PRIM

Imax : 2.57A

1 2

D D

C C

B B

RC299 0_0603_5%

1 2

RC300 0_0402_5%

1 2

RC301 0_0402_5%

1 2

RC302 0_0402_5%

1 2

RC303 0_0402_5%

+1.8V_PRIM

1 2

RC304 0_0402_5%

1 2

RC234 0_0402_5%

+3.3V_ALW_PCH

1 2

RC235 0_0402_5%

1 2

RC211 0_0402_5%

LPC@

+1.8V_PRIM

@ESPI@

1 2

RC212 0_0402_5%

1 2

RC305 0_0402_5%

1 2

RC306 0_0402_5%

1 2

RC307 0_0402_5%

1 2

RC308 0_0402_5%

+3.3V_ALW_PCH

1 2

LC1 BLM15GA750SN1D_2P

CC215

1U_0402_6.3V6K

+1.0V_MPHYAON

+1.0V_CLK6

+1.0V_DTS

+1.0V_CLK1

+1.0V_CLK3

+1.8V_PGPPF

+3.3V_1.8V_PGPPG

+3.3V_1.8V_PGPPA

+3.3V_PGPPB+3.3V_ALW_PCH

+3.3V_PGPPC

+3.3V_PGPPD

+3.3V_PGPPE

8/28 schematic review

close UC1.AF20 and <400mil

+3.3V_1.8V_ESPI

PJP4

1 2

PAD-OPEN1x1m

Must be +1.8V for eSPI I/F

+3.3V_VCCHDA

CC313

0.1U_0201_10V6K

close UC1.AJ19 and <400mil

A A

1 2

RC173 0_0402_5%

close UC1.N20 and <100mil

+1.0V_CLK4+1.0V_PRIM

CC226

47U_0805_6.3V6M

close UC1.AL1 and <120mil

+1.0V_MPHYAON

CC203

1U_0402_6.3V6K

+1.0V_MPHYGT

close UC1.N15 and CC210 <400mil, CC211 <120mil

CC210

47U_0805_6.3V6M

+1.0V_SRAM

CC217

1U_0402_6.3V6K

close UC1.K15, UC1.L15 and <100mil

@ 1 2

RC169 0_0603_5%

CC281

0.1U_0201_10V6K

+1.0V_PRIM

1 2

LC2 BLM 15GA750SN1D_2P

CC225

47U_0805_6.3V6M

close UC1.V15 and <100mil

1 2

RC170 0_0402_5%

close UC1.K19 and <100mil

CC204

1U_0402_6.3V6K

CC211

1U_0402_6.3V6K

+1.0V_APLLEBB

+1.0V_PRIM_CORE+1.0VO_DSW

close UC1.AB19 and <400milclose UC1.K17 and <120mil

CC205

1U_0402_6.3V6K

close UC1.AF18 and <400mil

+1.0V_AMPHYPLL

+1.0V_APLL

+1.0V_PRIM

+3.3V_ALW_DSW

+3.3V_VCCHDA

+3.3V_SPI

+3.3V_ALW_PCH

+1.0V_PRIM

close UC1.N18 and <120mil

CC218

1U_0402_6.3V6K

+1.0V_AMPHYPLL+1.0V_MPHYGT

close UC1.K15 and <120mil

CC264

1U_0402_6.3V6K

+1.0V_APLL

CC314

+1.0V_CLK2+1.0V_PRIM

CC220

47U_0805_6.3V6M

+1.0V_PRIM

CC206

0.1U_0201_10V6K

1U_0402_6.3V6K

No Support DS3

PCH PWR

UC1O

AB19

VCCPRIM_1P0

AB20

VCCPRIM_1P0

P18

VCCPRIM_1P0

AF18

VCCPRIM_CORE

AF19

VCCPRIM_CORE

V20

VCCPRIM_CORE

V21

VCCPRIM_CORE

AL1

DCPDSW_1P0

K17

VCCMPHYAON_1P0

N15

VCCMPHYGT_1P0_N15

N16

VCCMPHYGT_1P0_N16

N17

VCCMPHYGT_1P0_N17

P15

VCCMPHYGT_1P0_P15

P16

VCCMPHYGT_1P0_P16

K15

VCCAMPHYPLL_1P0

L15

VCCAMPHYPLL_1P0

V15

VCCAPLL_1P0

AB17

VCCPRIM_1P0_AB17

Y18

VCCPRIM_1P0_Y18

AD17

VCCDSW_3P3_AD17

AD18

VCCDSW_3P3_AD18

AJ17

VCCDSW_3P3_AJ17

AJ19

VCCHDA

AJ16

VCCSPI

AF20

VCCSRAM_1P0

AF21

VCCSRAM_1P0

T19

VCCSRAM_1P0

T20

VCCSRAM_1P0

AJ21

VCCPRIM_3P3_AJ21

AK20

VCCPRIM_1P0_AK20

N18

VCCAPLLEBB_1P0

KBL-RU42_BGA1356

+3.3V_ALW_DSW

22U_0603_6.3V6M

CC279

Support DS3

'V' mean POP, 'X' mean DE-POP

KBL-R U4+2

CPU POWER 4 OF 4

VCCPRIM_3P3_V19

VCCPRIM_1P0_T1

VCCATS_1P8

VCCRTCPRIM_3P3

VCCRTC_AK19 VCCRTC_BB14

GPP_B0/CORE_VID0 GPP_B1/CORE_VID1

1 2

RC440 0_0402_5%

NDS3@

1 2

RC214 0_0402_5%

1 2

@DS3@

RC439 0_0402_5%

22U_0603_6.3V6M

CC280

RC439

RC440RE5 36RC215RC44 1RC442

V V V

X X

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.

Rev_0.1

VCCPGPPA VCCPGPPB VCCPGPPC VCCPGPPD VCCPGPPE

VCCPGPPF

VCCPGPPG

DCPRTC

VCCCLK1

VCCCLK2

VCCCLK3

VCCCLK4

VCCCLK5

VCCCLK6

15 OF 20

+3.3V_ALW_DSW_R

close UC1.AG15 and <120mil

Must be + 1.8V

AK15 AG15 Y16 Y15 T16 AF16 AD15

V19

AA1

AK17

AK19 BB14

BB10

A14

K19

L21

N20

L19

A10

AN11 AN13

+3.3V_1.8V_PGPPA

+3.3V_PGPPD

+1.8V_PGPPF +3.3V_1.8V_PGPPG

+1.0V_DTS

+3.3V_ALW_PCH

close UC1.AK19 and <120mil

+DCPRTC

close UC1.BB10 and <120mil

+1.0V_CLK1

+1.0V_CLK2

+1.0V_CLK3

+1.0V_CLK4

+1.0V_CLK5

CORE_VID0 <45> CORE_VID1 <45>

Take care!!! Note1 on Page 19

+3.3V_ALW

QC7

DS3@

LP2301ALT1G_SOT23-3

123

499K_0402_1%

RC432

0.1U_0402_25V6K

49.9K_0402_1% RC433

L2N7002WT1G_SC-70-3

QC6

DS3@

CC340

DS3@

close UC1.Y16 a nd <400mil

+3.3V_PGPPB

+3.3V_PGPPC

CC265

1U_0402_6.3V6K

close UC1.AA1 and <400mil

+RTC_CELL_PCH

CC214

0.1U_0201_10V6K

+1.0V_CLK6

CC216

close UC1.L19 and <100mil

DS3@

100K_0402_5%

RC431

DS3@

1 2

VCCDSW_EN_GPIO <11>

+3.3V_PGPPE

close UC1.T16 a nd <400mil

CC207

1U_0402_6.3V6K

CC270

CC208

1U_0402_6.3V6K

CC213

1U_0201_6.3V6K

0.1U_0201_10V6K

close UC1.A10 and <120mil

1U_0402_6.3V6K

1 2

RC171 0_0402_5%

+1.0V_MPHYGT source

561280_561280_KBL_UY_PDG_Rev0p9 : MPHY has defeature

DELL CONFIDENTIAL/PROPRIETARY

+1.0V_MPHYGT

+1.0V_SRAM

+1.0V_APLLEBB

close UC1.AD15 and <400mil

CC326

1U_0402_6.3V6K

+1.8V_PRIM

RC309 0_0603_5%

RC310 0_0603_5%

+3.3V_ALW_PCH

CC209

1U_0402_6.3V6K

close UC1.V19 and <120mil

CC212

1U_0402_6.3V6K

1 2

+3.3V_1.8V_PGPPG

RF Request

+1.0V_APLL +3.3V_V CCHDA +1.0V_APLLEBB

+1.0V_CLK5+1.0V_PRIM+3.3V_ALW_PCH

CC221

47U_0805_6.3V6M

PJP3

1 2

PAD-OPEN1x3m

Compal Electronics, Inc.

Title

Size Document Number Re v

Date: Sheet o f

Compal Electronics, Inc.

CPU (13/14)

LA-F322P

CC323

RF@

2.2P_0402_50V8C

+3.3V_ALW_PCH

CC223

0.1U_0201_10V6K

+1.0V_MPHYGT+1.0V_PRIM

CC324

RF@

close UC1.AK17 and <120mil

CC325

2.2P_0402_50V8C

CC224

RF@

2.2P_0402_50V8C

1U_0402_6.3V6K

18 59Wednesday, December 20, 2017

2.0

+ 41 hidden pages

Compal LA-F322P Schematics rev.2.0

Specifications and Main Features

Frequently Asked Questions

User Manual