Compal LA-F312P Schematic
A
COMPAL CONFIDENTIAL
B
C
D
E
1 1
MODEL NAME : DAZ20 (SBMLK 12) / DAZ30 (SBMLK 13)
PCB NO : LA-F312P
Steamboat MLK 12"/13" NonAR
BOM P/N : 431A8W31L0X (12_NonAR)
Kabylake-U U22 & Kabylake-R U42
2017-12-29
REV : 2.0 (A01)
@ : Nopop Component
EMI@ : EMI Component
2 2
3 3
@EMI@ : EMI Nopop Component
ESD@ : ESDComponent
@ESD@ : ESD Nopop Component
RF@ : RF Component
@RF@ : RF Nopop Component
CXDP@ : XDP Component
CONN@ : Connector Component
ESPI@ : ESPI interface Component
LPC@ : External ESPI Component (SHD)
U42@ : KBL-R U42 Component
U22@ : KBL-R U22 Component
MB PCB
Part Number
DA8001CG010
Description
PCB 263 LA-F312P REV0 MB NAR 1
SB12@ : For SB12 System ID
SB13@ : For SB13 System ID
Layout Dell logo
DS3@ : Deep sleep Component
NDS3@ : Non Deep sleep Component
4 4
COPYRIGHT 2017
ALL RIGHT RESERVED
REV:A01
PWB: 3DRR6
A
Power CKT : 0919
GPIO map : 0821
B
546@ : TI TUSB546 Component
8743@ : PARADE PS8743 Component
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOU T THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRIT TEN CONSENT.
C
D
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Date : Sheet o f
Date : Sheet o f
Date : Sheet o f
Compal Electronics, Inc.
Cover Sheet
Cover Sheet
Cover Sheet
LA-F312P
LA-F312P
LA-F312P
1 58Friday, December 29, 2017
1 58Friday, December 29, 2017
1 58Friday, December 29, 2017
E
2.0
2.0
2.0
A
B
C
D
E
Steamboat MLK 12&13 w/o AR Block Diagram
Memory BUS (DDR4)
2133 MHz on KBL-U
USB
2400 MHz on KBL-R
up to 16GB
USB2.0[9]
USB3.0[6]
HDA Codec
ALC3246
1 1
EDP CONN
HDMI 1.4
CONN
P26
eDP 14": Lane x 4; 12" :Lane x 2
HDMI
P21
To NonAR type C
P22
DDI[1]
DDI[2]
INTEL
KABYLAKE_U MCP
U22
KABYLAKE_R MCP
U42
2 2
PCIE[1]
Card reader
RTS5242
P28
SD4.0
P28
3 3
PCIE[4]
Intel Jacksonville
WGI219LM
Transformer
RJ45
P27
P27
P27
WWAN/LTE/Cache
SATA[1]
M.2,3042 Key B
USB3.0[2]
P29
USB2.0[4]
M.2,3030 Key A
WLAN+BT
PCIE[3]
P29
USB2.0[7]
ESPI
SMSC KBC
MEC5105
SPI
P31-3 2
PAGE 6~19
HD Audio I/F
SATA[2]/PCIE [9][10][11] [12]
W25Q128JVSIQ
128M 4K sector
P8
W25Q128JVSIQ
128M 4K sector
TPM1.2/2.0 Nuvoton
NPCT750JAAYX
KB/TP CONN
FAN CONN
P8
reserve
P37
P32
P33
Steamboat MLK 12&13 only support one DIMM
Reverse Type
DDR4-SO-DIMM X1
BANK 0, 1, 2, 3
P20
SLGC55544CVTR
USB POWER SHARE
P35
INT.Speaker
Universal Jack
P30
Dig. MIC
USB2.0[8]
USB2.0[5]
USB2.0[9]_PS
USB3.0[6]
USB2.0[2]
USB3.0[3]
P30
P30
P26
LCD Touch
Camera
USB3.0 Conn
PS(Ext Port 1)
Right
USB3.0 Conn
(Ext Port 2)
Lef t Fr ont
Trough eDP Cable
M.2 2280
SSD Conn
P34
P26
P26
Trough eDP Cable
P35
P36
only 14"
LID SWITCH
LED board
USH CONN
P33
CPU&PCH XDP Port
Non-AR Type C
DP1.2 4 lanes
TX/RX
USB 3.0 + AM
Type C CONN.
4 4
USB2.0
CC
Vbus
HS Redriver Switch
TUSB546
P22
GPIO
PD Solut i on
TPS65982DC
P23-2 4P25
DDI[2]
USB3.0[1]
SMBUS
USB2.0[1]
Smart Card
5V VR
Charger
A
B
TDA8034HN
RFID/NFC
Fingerprint
CONN
C
USH board
USB2.0[10]
P33
D
USH TPM1.2
BCM58102
SPI
SPI
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER P ROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DELL CONFIDENTIAL/PROPRIETARY
Title
Title
Title
Size
Document Number Re v
Size
Document Number Re v
Size
Document Number Re v
Date: Sheet of
Date: Sheet of
Date: Sheet of
AUTOMATIC POWER
SWITCH(APS)
DC/DC Interface
POWER ON/OFF
SW & LED
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Block diagram
Block diagram
Block diagram
LA-F312P
LA-F312P
LA-F312P
E
P14
P11
P39
P38
2.0
2.0
2 58Wednesday, December 20, 2017
2 58Wednesday, December 20, 2017
2 58Wednesday, December 20, 2017
2.0
5
POWER STATES
Signal
State
S0 (Full ON) / M0
S3 (Suspend to RAM) / M3 LOW
D D
S4 (Suspend to DISK) / M3
S5 (SOFT OFF) / M3
S3 (Suspend to RAM) / M-OFF
S4 (Suspend to DISK) / M-OFF
S5 (SOFT OFF) / M- OFF
SLP
S3#
HIGH
LOW
LOW
LOW LOW LOW
LOW LOW LOW LOW
SLP
SLP
S5#
S4#
HIGH HIGH
HIGH HIGH
HIGH HIGH
LOW
LOW
LOW
HIGH HIGH
HIGH
ALW AYS
SLP
PLANE
A#
HIGH
ON
HIGH
ON ON ON
ON ON
HIGH
ON ON
ON ON
LOW
ON
ON
PM TABLE
+5V_ALW
+3.3V_ALW
+3.3V_ALW_D SW
power
C C
State
S0
S3
S5 S4/AC
S5 S4/AC doesn't exist
plane
+3.3V_ALW_PCH +1.2V_MEM
+RTC_CELL
+1.8V_PRIM
+1.0V_PRIM
+1.0V_PRIM_CORE
+5V_ALW 2
+3.3V_ALW 2
+3.3V_RTC_LDO
+1.0V_MPHYGT
ON
ON
ON
+3.3V_CV2
+2.5V_MEM
+1.0V_VCCST
+5V_RUN
+3.3V_RUN
+0.6V_DDR_VTT
+1.8V_RUN
+VCC_CORE
+VCC_GT
+VCC_SA
+1.0VS_VCCIO
ON ON
ON
OFF
OFFOFF
4
M
PLANE
ON
OFF OFF OFF
OFF OFF OFF OFF
OFF OFF OFF OFF
OFF
OFF
OFF
RUN
SUS
PLA NE
PLANE
ON ON ON
OFF
OFF
OFF
OFF
OFFLOW
CLOCKS
OFF
OFF
OFF
USB3.0
USB3.0-1
USB3.0-2
USB3.0-3
USB3.0-4
USB3.0-5
USB3.0-6
SSIC
SSIC
3
PCIE
PCIE-1
PCIE-2
PCIE-3
PCIE-4
PCIE-5
PCIE-6
PCIE-7
PCIE-8
PCIE-9
PCIE-10
PCIE-11
PCIE-12
SATA
JUSB3-->Lef t Rear ( SB14 onl y)
SATA-0
SATA-1
SATA-1*
M.2 3042(SATA Cache)
M.2 2280 SSD
(PCIex4 or SATA)
SATA-2
12" not support JUSB3
Typce-C(Non AR)
M.2 3042(LTE)
JUSB2-->Lef t Fr ont
Card Reader (PCIE)
JUSB1-->Right
M.2 3030(WLAN)
LOM
NA
NA
NA
2
1
NonAR config
USB PORT#DESTINATION
1
2
3
4
5
6
7
8
9
10
DESTINATION
Typce-C(Non AR)
JUSB2-->Lef t Fr ont
JUSB3-->Lef t Rear ( SB14 onl y)
M2 3042(WWAN)
Camera
NA
M.2 3030(BT)
Touch Screen
JUSB1-->Right
USH
B B
A A
AR use 1086PP (10L)
Non AR use 1080PP (8L)
5
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EX PRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY TH IRD
PARTY WITHOUT DELL'S EX PRESS WRITTEN CONSENT.
4
3
2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Date : Sheet of
Date : Sheet of
Date : Sheet of
Compal Electronics, Inc.
Port assignment
Port assignment
Port assignment
LA-F312P
LA-F312P
LA-F312P
1
3 58Wednesday, December 20, 2017
3 58Wednesday, December 20, 2017
3 58Wednesday, December 20, 2017
2.0
2.0
2.0
5
Barrel
ADAPT ER
D D
CHARGER
ISL9538
(PU901)
Type-C
ADAPTER
+PWR_SRC
SY8210A
(PU200)
SY8286R
(PU301)
SYV828C
(PU102)
4
SIO_SLP_S4#
0.6V_DDR_ VTT_ON
PCH_P RIM_EN
(SIO_SLP_SU S#)
ALWO N
+1.2V_MEM
+0.6V_DDR_VTT
+1.0V_PRIM
+5V_ALW
+5V_ALW2
TPS22961
(UZ26)
3
VCCSTG_ EN
TPS62134C
(PU401)
TPS62134D
(PU402)
EM5209
(UZ4)
+VCC_SFR_OC
RUN_ ON
PCH_P RIM_EN
(SIO_SLP_SU S#)
RUN_ ON
TPS22961
(UZ19)
TPS22961
(UZ21)
+1.0VS_VCCIO
+1.0V_PRIM_CORE
+5V_RUN
2
1
CPU PWR
PCH PWR
GT3 PWR
AUD_PW R_EN
Peripheral Device PWR
TYPE-C Power
+5V_RUN_AUDIO
RUN_ ON
SIO_SLP_S0#
SIO_SLP_S4#
EM5209
(@UZ5)
+1.0V_VCCSTG
+1.0V_VCCST
BATTERY
SY8288B
C C
(PU100)
ALWO N
+3.3V_RTC_LDO
+3.3V_ALW2
SLGC55544C
(UI3)
SY6288
(UI1)
USB_PW R_SHR_ VBUS_EN
USB_PW R_EN1#
+5V_USB_CHG_PWR
+USB_EX2_PWR
+3.3V_ALW
RT8097A
CSD97396Q
ISL95808
(PU614)
IMVP_V R_ON
B B
CSD97396Q
(PU612)
IMVP_V R_ON
+VCC_GT+VCC_SA
(PU610)
CSD9 7396Q
(PU613)
U42@
IMVP_V R_ON
+VCC_CORE
AO6405
(QV1)
EN_IN VPWR
+BL_PWR_SRC
TYPE-C
+5V_ALW
+PP_HV(5V~20V)
TPS65982D
(UT5)
+TBTA_Vbus_1(5V~20V)
(PU501)
EM5209
(UZ2)
EM5209
(UZ3)
EM5209
(UZ4)
G524B1T11U
(UV24)
PCH_P RIM_EN
(SIO_SLP_SU S#)
SIO_SLP_L AN#
AUX_EN_WOW L
@SIO_SLP_ WLAN#
PCH_P RIM_EN
(SIO_SLP_SU S#)
@PCH_ALW _ON
RUN_ ON
3.3V_W WAN_EN
ENVCC _PCH
+1.8V_PRIM
+3.3V_LAN
+3.3V_W LAN
+3.3V_ALW_PCH
+3.3V_RUN
+3.3V_W WAN
+LCDV DD
AOZ1336
(UZ8)
LP2301
(QV8)
LP2301 A
(QZ1)
EM5209
(@UZ5)
RUN_ ON
3.3V_TS_EN
3.3V_CAM_ EN#
AUD_PW R_EN
+1.8V_RUN
+3.3V_TSP
+3.3V_CAM
+3.3V_RUN_AUDIO
A A
AP2204
(UT8)
5
+5V_ALW
+5V_TBT_VBUS
AP2112 K
(UT7)
4
+3.3V_VDD_PIC
AP7361C
(PU503)
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EX PRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY TH IRD
PARTY WITHOUT DELL'S EX PRESS WRITTEN CONSENT.
3
SIO_SLP_S4#
+2.5V_MEM
for D DR4
2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Date : Sheet of
Date : Sheet of
Date : Sheet of
Compal Electronics, Inc.
Power rails
Power rails
Power rails
LA-F312P
LA-F312P
LA-F312P
1
4 58Wednesday, December 20, 2017
4 58Wednesday, December 20, 2017
4 58Wednesday, December 20, 2017
2.0
2.0
2.0
5
AW44
BB43
KBL-R
D D
KBL-U
AW45 AW42
03
03
AY44
BB39
SML1_SMBD ATA
SML1_SMBCLK
D8E11
00
00
UPD2_SMBCLK
D7
UPD2_SMBDAT
E7
MEM_SMBC LK
MEM_SMBDATA
SML0_SMBCLK
SML0_SMBD ATA
1K
1K
4
+3.3 V_ALW_ PCH
2.2K
2.2K
+3.3 V_ALW
499
499
1K
1K
+3.3 V_ALW_ PCH
+3.3 V_ALW_ PCH
3
DMN65D8LDW-7
DMN65D8LDW-7
28
31
LOM
2
1
2.2K
2.2K
+3.3 V_RUN
202
200
DIMMA
53
51
XDP
@2.2K
@2.2K
B3
E5
C12
E10
C3
B4
USH_SMBCLK
USH_SMBDAT
UPD1_SMBCLK
UPD1_SMBDAT
2.2K
2.2K
C C
01
01
02
02
KBC
04
04
+3.3 V_ALW
+3.3 V_ALW
DMN66D0LDW-7
DMN66D0LDW-7
2.2K
2.2K
2.2K
2.2K
+3.3 V_CV2
M9
USH
L9
USH/B
+3.3 V_TBTA_FLA SH
B5
PD
A5
MEC 5105
F7
05
B6
05
A12
06
N10
B B
A A
06
07
07
08 C5
08
09
09
1010M3
M4
M7
C8
F6
E9
N2
PBAT_CHARGER_SMBCLK
PBAT__CHARGER_SMBDAT
2.2K
2.2K
+3.3 V_ALW
100 ohm
100 ohm
7
6
Charger
BATTERY
CONN
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EX PRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY TH IRD
PARTY WITHOUT DELL'S EX PRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Date : Sheet of
Date : Sheet of
Date : Sheet of
Compal Electronics, Inc.
Port assignment
Port assignment
Port assignment
LA-F312P
LA-F312P
LA-F312P
1
5 58Wednesday, December 20, 2017
5 58Wednesday, December 20, 2017
5 58Wednesday, December 20, 2017
2.0
2.0
2.0
5
4
3
2
1
+3.3V_RUN
CPU_DP1_CTRL_CLK
RC175 2.2K_0402_5%
RC178 2.2K_0402_5%
D D
RC176 2.2K_0402_5%
RC177 2.2K_0402_5%
12
CPU_DP1_CTRL_DATA
12
CPU_DP2_CTRL_CLK
12
CPU_DP2_CTRL_DATA
12
AR (AR)/
HDMI(Non AR)
Dockport (Non AR)
+1.0VS_VCCIO
C C
B B
CPU_DP1_N0<21>
CPU_DP1_P0<21>
CPU_DP1_N1<21>
CPU_DP1_P1<21>
CPU_DP1_N2<21>
CPU_DP1_P2<21>
CPU_DP1_N3<21>
CPU_DP1_P3<21>
CPU_DP2_N0<22>
CPU_DP2_P0<22>
CPU_DP2_N1<22>
CPU_DP2_P1<22>
CPU_DP2_N2<22>
CPU_DP2_P2<22>
CPU_DP2_N3<22>
CPU_DP2_P3<22>
12
CPU_DP1_CTRL_CLK
CPU_DP1_CTRL_DATA
CPU_DP2_CTRL_CLK
CPU_DP2_CTRL_DATA
GPP_E23
EDP_COMP
CPU_DP1_CTRL_CLK<21>
CPU_DP1_CTRL_DATA<21>
@
T120
PAD~D
RC2 24.9_0402_1%
COMPENSATION PU FOR eDP
CAD Note:Trace width=20 mils , Spacing=25mil,
Max length=100 mils.
CPU@
UC1A
E55
DDI1_TXN[0]
F55
DDI1_TXP[0]
E58
DDI1_TXN[1]
F58
DDI1_TXP[1]
F53
DDI1_TXN[2]
G53
DDI1_TXP[2]
F56
DDI1_TXN[3]
G56
DDI1_TXP[3]
C50
DDI2_TXN[0]
D50
DDI2_TXP[0]
C52
DDI2_TXN[1]
D52
DDI2_TXP[1]
A50
DDI2_TXN[2]
B50
DDI2_TXP[2]
D51
DDI2_TXN[3]
C51
DDI2_TXP[3]
L13
GPP_E18/DDPB_CTRLCLK
L12
GPP_E19/DDPB_CTRLDATA
N7
GPP_E20/DDPC_CTRLCLK
N8
GPP_E21/DDPC_CTRLDATA
N11
GPP_E22
N12
GPP_E23
E52
EDP_RCOMP
KBL-RU42_BGA1356
CPU@
UC1I
CSI-2
A36
CSI2_DN0
B36
CSI2_DP0
C38
CSI2_DN1
D38
CSI2_DP1
C36
CSI2_DN2
D36
CSI2_DP2
A38
CSI2_DN3
B38
CSI2_DP3
C31
CSI2_DN4
D31
CSI2_DP4
C33
CSI2_DN5
D33
CSI2_DP5
A31
CSI2_DN6
B31
CSI2_DP6
A33
CSI2_DN7
B33
CSI2_DP7
A29
CSI2_DN8
B29
CSI2_DP8
C28
CSI2_DN9
D28
CSI2_DP9
A27
CSI2_DN10
B27
CSI2_DP10
C27
CSI2_DN11
D27
CSI2_DP11
KBL-RU42_BGA1356
KBL-R U4+2
DDI
DISPLAY SIDEBANDS
KBL-R U4+2
EDP
Rev_0.1
CSI2_CLKN0
CSI2_CLKP0
CSI2_CLKN1
CSI2_CLKP1
CSI2_CLKN2
CSI2_CLKP2
CSI2_CLKN3
CSI2_CLKP3
CSI2_COMP
GPP_D4/FLASHTRIG
EMMC
GPP_F13/EMMC_DATA0
GPP_F14/EMMC_DATA1
GPP_F15/EMMC_DATA2
GPP_F16/EMMC_DATA3
GPP_F17/EMMC_DATA4
GPP_F18/EMMC_DATA5
GPP_F19/EMMC_DATA6
GPP_F20/EMMC_DATA7
GPP_F21/EMMC_RCLK
GPP_F22/EMMC_CLK
GPP_F12/EMMC_CMD
EMMC_RCOMP
9 OF 20
Rev_0.1
EDP_TXN[0]
EDP_TXP[0]
EDP_TXN[1]
EDP_TXP[1]
EDP_TXN[2]
EDP_TXP[2]
EDP_TXN[3]
EDP_TXP[3]
EDP_AUXN
EDP_AUXP
EDP_DISP_UTIL
DDI1_AUXN
DDI1_AUXP
DDI2_AUXN
DDI2_AUXP
RSVD
GPP_E13/DDPB_HPD0
GPP_E14/DDPC_HPD1
GPP_E15/DDPD_HPD2
GPP_E16/DDPE_HPD3
RSVD
GPP_E17/EDP_HPD
EDP_BKLTEN
EDP_BKLTCTL
EDP_VDDEN
1 OF 20
C37
D37
C32
D32
C29
D29
B26
A26
CSI2_COMP
E13
B7
AP2
AP1
AP3
AN3
AN1
AN2
AM4
AM1
AM2
AM3
AP4
EMMC_RCOMP
AT1
C47
C46
D46
C45
A45
B45
A47
B47
E45
F45
B52
G50
F50
E48
F48
G46
F46
L9
L7
L6
N9
L10
R12
R11
U13
RC3
TBT_FORCE_PWR
1 2
RC4 200_0402_1%
CPU_DP1_AUXN
CPU_DP1_AUXP
CPU_DP3_AUXN
CPU_DP3_AUXP
1 2
EDP_TXN0 <26>
EDP_TXP0 <26>
EDP_TXN1 <26>
EDP_TXP1 <26>
EDP_AUXN <26>
EDP_AUXP <26>
PAD~D
PAD~D
CPU_DP2_AUXN <22,23>
CPU_DP2_AUXP <22,23>
PAD~D
PAD~D
CPU_DP1_HPD <21>
CPU_DP2_HPD <22,23>
EDP_HPD <26>
PANEL_BKLEN <26>
EDP_BIA_PWM <26>
ENVDD_PCH <26>
100_0402_1%
T19 @PAD~D
+3.3V_RUN
@
T281
@
T282
@
T1
@
T2
CPU_DP2_AUXN
CPU_DP2_AUXP
CPU_DP2_HPD
EDP_HPD
1 2
@
RC448 100K_0402_5%
1 2
@
RC447 100K_0402_5%
1 2
RC446 100K_0402_5%
1 2
RC1 100K_0402_5%
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.
5
4
3
2
Title
Size Document N umber Re v
Size Document N umber Re v
Size Document N umber Re v
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (1/14)
CPU (1/14)
CPU (1/14)
LA-F312P
LA-F312P
LA-F312P
6 58Wednesday, December 20, 2017
6 58Wednesday, December 20, 2017
6 58Wednesday, December 20, 2017
1
2.0
2.0
2.0
5
4
3
2
1
For DDR4
DDR_A_DQS#[0..7]<20>
AU53
AT53
AU55
AT55
BA56
BB56
AW56
AY56
AU45
AU43
AT45
AT43
BA51
BB54
BA52
AY52
AW52
AY55
AW54
BA54
BA55
AY54
AU46
AU48
AT46
AU50
AU52
AY51
AT48
AT50
BB50
AY50
BA50
BB52
AM70
AM69
AT69
AT70
BA64
AY64
AY60
BA60
BA38
AY38
AY34
BA34
BA30
AY30
AY26
BA26
AW50
AT52
AY67
AY68
BA67
AW67
DDR_A_D[0..63]<20>
DDR_A_DQS[0..7]<20>
DDR_A_MA[0..16]<20>
DDR_A_CLK#0
DDR_A_CLK0
DDR_A_CLK#1
DDR_A_CLK1
DDR_A_CKE0
DDR_A_CKE1
DDR_A_CKE2
DDR_A_CKE3
DDR_A_CS#0
DDR_A_CS#1
DDR_A_ODT0
DDR_A_ODT1
DDR_A_MA5
DDR_A_MA9
DDR_A_MA6
DDR_A_MA8
DDR_A_MA7
DDR_A_BG0
DDR_A_MA12
DDR_A_MA11
DDR_A_ACT#
DDR_A_BG1
DDR_A_MA13
DDR_A_MA15
DDR_A_MA14
DDR_A_MA16
DDR_A_BA0
DDR_A_MA2
DDR_A_BA1
DDR_A_MA10
DDR_A_MA1
DDR_A_MA0
DDR_A_MA3
DDR_A_MA4
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_ALERT#
DDR_A_PARITY
+DDR_VREF_A_DQ
+DDR_VREF_B_DQ
DDR_A_CLK#0 <20>
DDR_A_CLK0 <20>
DDR_A_CLK#1 <20>
DDR_A_CLK1 <20>
DDR_A_CKE0 <20>
DDR_A_CKE1 <20>
@
T3
PAD~D
@
T4
PAD~D
DDR_A_CS#0 <20>
DDR_A_CS#1 <20>
DDR_A_ODT0 <20>
DDR_A_ODT1 <20>
DDR_A_BG0 <20>
DDR_A_ACT# <20>
DDR_A_BG1 <20>
DDR_A_BA0 <20>
DDR_A_BA1 <20>
DDR0_PAR,DDR0_ALERT# for DDR4
DDR_A_ALERT# <20 >
DDR_A_PARITY <20>
+DDR_VREF_CA
@
T132
PAD~D
@
T226
PAD~D
DDR_VTT_CTRL <20>
UC1C
Interleave / Non-Interleaved
AF65
DDR1_DQ[0]/DDR0_DQ[16]
AF64
DDR1_DQ[1]/DDR0_DQ[17]
AK65
DDR1_DQ[2]/DDR0_DQ[18]
AK64
DDR1_DQ[3]/DDR0_DQ[19]
AF66
DDR1_DQ[4]/DDR0_DQ[20]
AF67
DDR1_DQ[5]/DDR0_DQ[21]
AK67
DDR1_DQ[6]/DDR0_DQ[22]
AK66
DDR1_DQ[7]/DDR0_DQ[23]
AF70
DDR1_DQ[8]/DDR0_DQ[24]
AF68
DDR1_DQ[9]/DDR0_DQ[25]
AH71
DDR1_DQ[10]/DDR0_DQ[26]
AH68
DDR1_DQ[11]/DDR0_DQ[27]
AF71
DDR1_DQ[12]/DDR0_DQ[28]
AF69
DDR1_DQ[13]/DDR0_DQ[29]
AH70
DDR1_DQ[14]/DDR0_DQ[30]
AH69
DDR1_DQ[15]/DDR0_DQ[31]
AT66
DDR1_DQ[16]/DDR0_DQ[48]
AU66
DDR1_DQ[17]/DDR0_DQ[49]
AP65
DDR1_DQ[18]/DDR0_DQ[50]
AN65
DDR1_DQ[19]/DDR0_DQ[51]
AN66
DDR1_DQ[20]/DDR0_DQ[52]
AP66
DDR1_DQ[21]/DDR0_DQ[53]
AT65
DDR1_DQ[22]/DDR0_DQ[54]
AU65
DDR1_DQ[23]/DDR0_DQ[55]
AT61
DDR1_DQ[24]/DDR0_DQ[56]
AU61
DDR1_DQ[25]/DDR0_DQ[57]
AP60
DDR1_DQ[26]/DDR0_DQ[58]
AN60
DDR1_DQ[27]/DDR0_DQ[59]
AN61
DDR1_DQ[28]/DDR0_DQ[60]
AP61
DDR1_DQ[29]/DDR0_DQ[61]
AT60
DDR1_DQ[30]/DDR0_DQ[62]
AU60
DDR1_DQ[31]/DDR0_DQ[63]
AU40
DDR1_DQ[32]/DDR1_DQ[16]
AT40
DDR1_DQ[33]/DDR1_DQ[17]
AT37
DDR1_DQ[34]/DDR1_DQ[18]
AU37
DDR1_DQ[35]/DDR1_DQ[19]
AR40
DDR1_DQ[36]/DDR1_DQ[20]
AP40
DDR1_DQ[37]/DDR1_DQ[21]
AP37
DDR1_DQ[38]/DDR1_DQ[22]
AR37
DDR1_DQ[39]/DDR1_DQ[23]
AT33
DDR1_DQ[40]/DDR1_DQ[24]
AU33
DDR1_DQ[41]/DDR1_DQ[25]
AU30
DDR1_DQ[42]/DDR1_DQ[26]
AT30
DDR1_DQ[43]/DDR1_DQ[27]
AR33
DDR1_DQ[44]/DDR1_DQ[28]
AP33
DDR1_DQ[45]/DDR1_DQ[29]
AR30
DDR1_DQ[46]/DDR1_DQ[30]
AP30
DDR1_DQ[47]/DDR1_DQ[31]
AU27
DDR1_DQ[48]
AT27
DDR1_DQ[49]
AT25
DDR1_DQ[50]
AU25
DDR1_DQ[51]
AP27
DDR1_DQ[52]
AN27
DDR1_DQ[53]
AN25
DDR1_DQ[54]
AP25
DDR1_DQ[55]
AT22
DDR1_DQ[56]
AU22
DDR1_DQ[57]
AU21
DDR1_DQ[58]
AT21
DDR1_DQ[59]
AN22
DDR1_DQ[60]
AP22
DDR1_DQ[61]
AP21
DDR1_DQ[62]
AN21
DDR1_DQ[63]
KBL-RU42_BGA1356
CPU@
KBL-R U4+2
DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5]
DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9]
DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6]
DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8]
DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]
DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]
DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12]
DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]
DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT#
DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]
DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]
DDR1_CAS#/DDR1_CAB[1]/DDR1_M A[15]
DDR1_WE#/DDR1_CA B[2]/DDR1_MA[14]
DDR1_RAS#/DDR1_CAB[3]/DDR1_M A[16]
DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]
DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]
DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]
DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]
DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1]
DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]
DDR CH - B
3 OF 20
DDR3L / LPDDR3 / DDR4
Interleave / Non-Interleaved
DDR1_DQSN[0]/DDR0_DQSN[2]
DDR1_DQSP[0]/DDR0_DQSP[2]
DDR1_DQSN[1]/DDR0_DQSN[3]
DDR1_DQSP[1]/DDR0_DQSP[3]
DDR1_DQSN[2]/DDR0_DQSN[6]
DDR1_DQSP[2]/DDR0_DQSP[6]
DDR1_DQSN[3]/DDR0_DQSN[7]
DDR1_DQSP[3]/DDR0_DQSP[7]
DDR1_DQSN[4]/DDR1_DQSN[2]
DDR1_DQSP[4]/DDR1_DQSP[2]
DDR1_DQSN[5]/DDR1_DQSN[3]
DDR1_DQSP[5]/DDR1_DQSP[3]
DRAM_RESET#
DDR_RCOMP[0]
DDR_RCOMP[1]
DDR_RCOMP[2]
Rev_0.1
DDR1_CKN[0]
DDR1_CKN[1]
DDR1_CKP[0]
DDR1_CKP[1]
DDR1_CKE[0]
DDR1_CKE[1]
DDR1_CKE[2]
DDR1_CKE[3]
DDR1_CS#[0]
DDR1_CS#[1]
DDR1_ODT[0]
DDR1_ODT[1]
DDR1_MA[3]
DDR1_MA[4]
DDR1_DQSN[6]
DDR1_DQSP[6]
DDR1_DQSN[7]
DDR1_DQSP[7]
DDR1_ALERT#
DDR1_PAR
AN45
AN46
AP45
AP46
AN56
AP55
AN55
AP53
BB42
AY42
BA42
AW42
AY48
AP50
BA48
BB48
AP48
AP52
AN50
AN48
AN53
AN52
BA43
AY43
AY44
AW44
BB44
AY47
BA44
AW46
AY46
BA46
BB46
BA47
AH66
AH65
AG69
AG70
AR66
AR65
AR61
AR60
AT38
AR38
AT32
AR32
AR25
AR27
AR22
AR21
AN43
AP43
AT13
AR18
AT18
AU18
DDR1_PAR,DDR1_ALERT# for DDR4
DDR_DRAMRST#
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
DDR_DRAMRST# <20>
DDR4, Ballout for side by side(Interleave)
D D
CPU@
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
C C
B B
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
UC1B
AL71
DDR0_DQ[0]
AL68
DDR0_DQ[1]
AN68
DDR0_DQ[2]
AN69
DDR0_DQ[3]
AL70
DDR0_DQ[4]
AL69
DDR0_DQ[5]
AN70
DDR0_DQ[6]
AN71
DDR0_DQ[7]
AR70
DDR0_DQ[8]
AR68
DDR0_DQ[9]
AU71
DDR0_DQ[10]
AU68
DDR0_DQ[11]
AR71
DDR0_DQ[12]
AR69
DDR0_DQ[13]
AU70
DDR0_DQ[14]
AU69
DDR0_DQ[15]
Interleave / Non-Interleaved
BB65
DDR0_DQ[16]/DDR0_DQ[32]
AW65
DDR0_DQ[17]/DDR0_DQ[33]
AW63
DDR0_DQ[18]/DDR0_DQ[34]
AY63
DDR0_DQ[19]/DDR0_DQ[35]
BA65
DDR0_DQ[20]/DDR0_DQ[36]
AY65
DDR0_DQ[21]/DDR0_DQ[37]
BA63
DDR0_DQ[22]/DDR0_DQ[38]
BB63
DDR0_DQ[23]/DDR0_DQ[39]
BA61
DDR0_DQ[24]/DDR0_DQ[40]
AW61
DDR0_DQ[25]/DDR0_DQ[41]
BB59
DDR0_DQ[26]/DDR0_DQ[42]
AW59
DDR0_DQ[27]/DDR0_DQ[43]
BB61
DDR0_DQ[28]/DDR0_DQ[44]
AY61
DDR0_DQ[29]/DDR0_DQ[45]
BA59
DDR0_DQ[30]/DDR0_DQ[46]
AY59
DDR0_DQ[31]/DDR0_DQ[47]
AY39
DDR0_DQ[32]/DDR1_DQ[0]
AW39
DDR0_DQ[33]/DDR1_DQ[1]
AY37
DDR0_DQ[34]/DDR1_DQ[2]
AW37
DDR0_DQ[35]/DDR1_DQ[3]
BB39
DDR0_DQ[36]/DDR1_DQ[4]
BA39
DDR0_DQ[37]/DDR1_DQ[5]
BA37
DDR0_DQ[38]/DDR1_DQ[6]
BB37
DDR0_DQ[39]/DDR1_DQ[7]
AY35
DDR0_DQ[40]/DDR1_DQ[8]
AW35
DDR0_DQ[41]/DDR1_DQ[9]
AY33
DDR0_DQ[42]/DDR1_DQ[10]
AW33
DDR0_DQ[43]/DDR1_DQ[11]
BB35
DDR0_DQ[44]/DDR1_DQ[12]
BA35
DDR0_DQ[45]/DDR1_DQ[13]
BA33
DDR0_DQ[46]/DDR1_DQ[14]
BB33
DDR0_DQ[47]/DDR1_DQ[15]
AY31
DDR0_DQ[48]/DDR1_DQ[32]
AW31
DDR0_DQ[49]/DDR1_DQ[33]
AY29
DDR0_DQ[50]/DDR1_DQ[34]
AW29
DDR0_DQ[51]/DDR1_DQ[35]
BB31
DDR0_DQ[52]/DDR1_DQ[36]
BA31
DDR0_DQ[53]/DDR1_DQ[37]
BA29
DDR0_DQ[54]/DDR1_DQ[38]
BB29
DDR0_DQ[55]/DDR1_DQ[39]
AY27
DDR0_DQ[56]/DDR1_DQ[40]
AW27
DDR0_DQ[57]/DDR1_DQ[41]
AY25
DDR0_DQ[58]/DDR1_DQ[42]
AW25
DDR0_DQ[59]/DDR1_DQ[43]
BB27
DDR0_DQ[60]/DDR1_DQ[44]
BA27
DDR0_DQ[61]/DDR1_DQ[45]
BA25
DDR0_DQ[62]/DDR1_DQ[46]
BB25
DDR0_DQ[63]/DDR1_DQ[47]
KBL-RU42_BGA1356
KBL-R U4+2
DDR0_CKN[0]
DDR0_CKP[0]
DDR0_CKN[1]
DDR0_CKP[1]
DDR0_CKE[0]
DDR0_CKE[1]
DDR0_CKE[2]
DDR0_CKE[3]
DDR0_CS#[0]
DDR0_CS#[1]
DDR0_ODT[0]
DDR0_ODT[1]
DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5]
DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9]
DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6]
DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8]
DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]
DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]
DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12]
DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]
DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT#
DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]
DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]
DDR0_CAS#/DDR0_CAB[1]/DDR0_M A[15]
DDR0_WE#/DDR0_CA B[2]/DDR0_MA[14]
DDR0_RAS#/DDR0_CAB[3]/DDR0_M A[16]
DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]
DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]
DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]
DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]
DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1]
DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]
DDR CH - A
2 OF 20
DDR3L / LPDDR3 / DDR4
DDR0_MA[3]
DDR0_MA[4]
DDR0_DQSN[0]
DDR0_DQSP[0]
DDR0_DQSN[1]
DDR0_DQSP[1]
Interleave / Non-Interleaved
DDR0_DQSN[2]/DDR0_DQSN[4]
DDR0_DQSP[2]/DDR0_DQSP[4]
DDR0_DQSN[3]/DDR0_DQSN[5]
DDR0_DQSP[3]/DDR0_DQSP[5]
DDR0_DQSN[4]/DDR1_DQSN[0]
DDR0_DQSP[4]/DDR1_DQSP[0]
DDR0_DQSN[5]/DDR1_DQSN[1]
DDR0_DQSP[5]/DDR1_DQSP[1]
DDR0_DQSN[6]/DDR1_DQSN[4]
DDR0_DQSP[6]/DDR1_DQSP[4]
DDR0_DQSN[7]/DDR1_DQSN[5]
DDR0_DQSP[7]/DDR1_DQSP[5]
DDR0_ALERT#
DDR_VREF_CA
DDR0_VREF_DQ
DDR1_VREF_DQ
DDR_VTT_CNTL
Rev_0.1
DDR0_PAR
DDR4 COMPENSATION SIGNALS
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
CAD Note:
Trace width=12~15 mil, Spacing=20 mils
Max trace length= 500 mil
A A
1 2
RC5 121_0402_1%
1 2
RC6 80.6_0402_1%
1 2
RC7 100_0402_1%
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.
5
4
3
2
Title
Size Document N umber Re v
Size Document N umber Re v
Size Document N umber Re v
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (2/14)
CPU (2/14)
CPU (2/14)
LA-F312P
LA-F312P
LA-F312P
7 58Wednesday, December 20, 2017
7 58Wednesday, December 20, 2017
7 58Wednesday, December 20, 2017
1
2.0
2.0
2.0
5
SPI_MOSI= SPI_IO0
SPI_MISO= SPI_IO1
PCH EDS R0.7 p.235~236
PCH_SPI_CLK
PCH_SPI_D1
CXDP@
1 2
PCH_SPI_DO_XDP<14>
PCH_SPI_DO2_XDP<14>
D D
C C
PCH_SPI_CLK_1_R PCH_SPI_CLK_0_R
33_0402_5%
@EMI@
12
RC28
33P_0402_50V8J
@EMI@
12
CC7
B B
A A
RC10 1K_0402_1%
CXDP@
1 2
RC11 1K_0402_1%
PCH_SPI_CS#2<33>
PCH_CL_CLK1<29>
PCH_CL_DATA1<29>
PCH_CL_RST1#<29>
ESPI_ALERT#<31>
+3.3V_1.8V_ESPI
33_0402_5%
@EMI@
12
RC29
33P_0402_50V8J
12
CC8
RC21 8.2K_0402_1%
@EMI@
PCH_SPI_CS#0_R1
PCH_SPI_D2_R1 PCH_SPI_CLK_0_R
PCH_SPI_CS#1_R1
PCH_SPI_D2_R1
PCH_SPI_D0
PCH_SPI_D2
PCH_SPI_D3
PCH_SPI_CS#0
PCH_SPI_CS#1
PCH_SPI_CS#2
12
+3.3V_SPI
RC30 1K_0402_5%
@
RC31 1K_0402_5%
@
RC316 1K_0402_5%
@
@
1 2
RC37 0_0402_5%
1 2
RC39 33_0402_5%
1 2
RC42 0_0402_5%@
1 2
RC43 33_0402_5%
@
12
12
12
03/02:follow Intel MOW_2015W W06
PCH_SPI_D2_R1
PCH_SPI_D3_R1
PCH_SPI_D3_R1
AV2
SPI0_CLK
AW3
SPI0_MISO
AV3
SPI0_MOSI
AW2
SPI0_IO2
AU4
SPI0_IO3
AU3
SPI0_CS0#
AU2
SPI0_CS1#
AU1
SPI0_CS2#
M2
GPP_D1/SPI1_CLK
M3
GPP_D2/SPI1_MISO
J4
GPP_D3/SPI1_MOSI
V1
GPP_D21/SPI1_IO2
V2
GPP_D22/SPI1_IO3
M1
GPP_D0/SPI1_CS#
G3
CL_CLK
G2
CL_DATA
G1
CL_RST#
AW13
GPP_A0/RCIN#
AY11
GPP_A6/SERIRQ
KBL-RU42_BGA1356
PCH_SPI_CS#0_R2
PCH_SPI_D1_0_R
PCH_SPI_D2_0_R
PCH_SPI_CS#1_R2
PCH_SPI_D1_1_R
PCH_SPI_D2_1_R
UC1E
4
CPU@
SPI - TOUCH
C LINK
SPI - FLASH
PCH_SPI_D1_R1<33>
PCH_SPI_D0_R1<33>
PCH_SPI_CLK_R1<33>
1
2
3
4
1
2
3
4
KBL-R U4+2
LPC
PCH_SPI_D1_R1
PCH_SPI_D0_R1
PCH_SPI_CLK_R1
PCH_SPI_D3_R1
PCH_SPI_CLK_R1
PCH_SPI_D0_R1
PCH_SPI_D1_R1
128Mb Flash ROM
UC5
/CS
IO1
IO2
GND
W25Q128JVSIQ_SO8
VCC
CLK
IO3
IO0
128Mb Flash ROM
UC6
@
/CS
IO1
IO2
GND
W25Q128JVSIQ_SO8
VCC
CLK
IO3
IO0
SMBUS, SMLINK
GPP_C2/SMBALERT#
GPP_C5/SML0ALERT#
GPP_B23/SML1ALERT#/PCHHOT#
GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1
GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3
GPP_A5/LFRAME#/ESPI_CS#
GPP_A14/SUS_STAT#/ESPI_RESET#
GPP_A9/CLKOUT_LPC0/ESPI_CLK
GPP_A10/CLKOUT_LPC1
SOFTWARE TAA
RPC1
PCH_SPI_D1_0_R
1 8
PCH_SPI_D0_0_R
2 7
PCH_SPI_CLK_0_R
3 6
PCH_SPI_D3_0_R
4 5
33_0804_8P4R_5%
1 2
RC407 33_0402_5%
@
1 2
RC408 33_0402_5%
@
1 2
RC409 33_0402_5%
@
1 2
RC410 33_0402_5%
@
+3.3V_SPI
8
PCH_SPI_D3_0_R
7
6
PCH_SPI_D0_0_R
5
+3.3V_SPI
8
PCH_SPI_D3_1_R
7
PCH_SPI_CLK_1_R
6
PCH_SPI_D0_1_R
5
CC9
1 2
0.1U_0201_10V6K
CC10
@
1 2
0.1U_0201_10V6K
3
Rev_0.1
GPP_C0/SMBCLK
GPP_C1/SMBDATA
GPP_C3/SML0CLK
GPP_C4/SML0DATA
GPP_C6/SML1CLK
GPP_C7/SML1DATA
GPP_A8/CLKRUN#
5 OF 20
PCH_SPI_D3_1_RPCH_SPI_D3_R1
PCH_SPI_CLK_1_R
PCH_SPI_D0_1_R
PCH_SPI_D1_1_R
R7
R8
R10
R9
W2
W1
W3
V3
AM7
AY13
BA13
BB13
AY12
BA12
BA11
AW9
AY9
AW11
+3.3V_SPI
MEM_SMBCLK
MEM_SMBDATA
PCH_SMB_ALERT#
SML0_SMBCLK
SML0_SMBDATA
GPP_C5
SML1_SMBCLK
SML1_SMBDATA
GPP_B23
ESPI_IO0_R
ESPI_IO1_R
ESPI_IO2_R
ESPI_IO3_R
ESPI_CLK
PCI_CLK_LPC1
CLKRUN#
RC32 0_0402_5%
@
1 2
@
RC33 0_0402_5%
1 2
@
RC34 0_0402_5%
1 2
@
RC35 0_0402_5%
1 2
@
RC36 0_0402_5%
1 2
@
RC38 0_0402_5%
1 2
@
RC40 0_0402_5%
+3.3V_ALW_PCH
@
RC41 0_0402_5%
SML0_SMBCLK <27>
SML0_SMBDATA <2 7>
SML1_SMBCLK <31>
SML1_SMBDATA <3 1>
1 2
RC366
1 2
RC367
1 2
RC368
1 2
RC369
ESPI_CS# <31,32>
ESPI_RESET# <31,32>
1 2
RC16
EMI@
1 2
1 2
RC22@ 22_0402_5%
ESPI_CLK_5105
SML0_SMBCLK
SML1_SMBCLK
MEM_SMBCLK
PCH_SPI_CS#1_R1
12
PCH_SPI_D0_R1
PCH_SPI_D1_R1
PCH_SPI_CLK_R1
PCH_SPI_CS#0_R1
PCH_SPI_D2_R1
PCH_SPI_D3_R1
2
15_0402_5%
15_0402_5%
15_0402_5%
15_0402_5%
15_0402_5%
CHECK,LPC_CLK FOR DEBUG CARD?
ESPI_IO0 <31,32>
ESPI_IO1 <31,32>
ESPI_IO2 <31,32>
ESPI_IO3 <31,32>
RF Request
1 2
CC316@RF@ 33P_0402_50V8J
1 2
CC318@RF@ 33P_0402_50V8J
1 2
CC319@RF@ 33P_0402_50V8J
1 2
CC320@RF@ 33P_0402_50V8J
Place close CPU side
JSPI1
1
PCH_SPI_CS#1
PCH_SPI_D0
PCH_SPI_D1
PCH_SPI_CLK
PCH_SPI_CS#0
PCH_SPI_D2
PCH_SPI_D3
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
GND1
22
GND2
CVILU_CF5020FD0R0-05-NH
MEM_SMBCLK
MEM_SMBDATA
ESPI_CLK_5105 <31,32>
CONN@
3 4
DMN65D8LDW-7_SOT363-6
+3.3V_RUN
2
6
5
DMN65D8LDW-7_SOT363-6
QC2B
For BR/SB
1
DDR_XDP_WAN_S MBCLK <14,20>
QC2A
DDR_XDP_WAN_S MBDAT <14,20>
DDR_XDP_WAN_S MBDAT
DDR_XDP_WAN_S MBCLK
MEM_SMBCLK
MEM_SMBDATA
SML1_SMBCLK
SML1_SMBDATA
SML0_SMBCLK
SML0_SMBDATA
Rese rve
SML0_SMBCLK
SML0_SMBDATA
CLKRUN#
PCH_SMB_ALERT#
TLS C ONFIDENTIALITY
HIGH
LOW(DEFAULT)
WEAK INT ERNAL 20K PD
GPP_C5
EC interface
HIGH
LOW(DEFAULT)
WEAK INTERNAL 20k PD
GPP_B23
EXI BOOT STALL BYPASS
HIGH
LOW(DEFAULT)
WEAK INTERNAL PD
1
+3.3V_RUN
1 2
RC318 2.2K_0402_5%
1 2
RC319 2.2K_0402_5%
1 2
RC12 1K_0402_5%
1 2
RC14 1K_0402_5%
1 2
RC15 1K_0402_5%
1 2
RC17 1K_0402_5%
1 2
RC347 499_0402_1%
1 2
RC348 499_0402_1%
1 2
RC19 499_0402_1%@
1 2
RC20 499_0402_1%@
1 2
RC27 8.2K_0402_5%LPC@
1 2
RC23 2.2K_0402_5%
1 2
RC25 4.7K_0402_5%ESPI@
1 2
RC317 150K_0402_5%
ENABLE
DISAB LE
ESPI
LPC
ENABLED
DIABL ED
+3.3V_ALW_PCH
+3.3V_LAN
+3.3V_ALW_PCH
+3.3V_ALW_PCH
+3.3V_ALW_PCH
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.
5
4
3
2
Title
Size Document N umber Re v
Size Document N umber Re v
Size Document N umber Re v
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (3/14)
CPU (3/14)
CPU (3/14)
LA-F312P
LA-F312P
LA-F312P
8 58Wednesday, December 20, 2017
8 58Wednesday, December 20, 2017
8 58Wednesday, December 20, 2017
1
2.0
2.0
2.0
5
4
3
2
1
For BR/SB
CPU@
AN8
AP7
AP8
AR7
AM5
AN7
AP5
AN5
AB1
AB2
W4
AB3
AD1
AD2
AD3
AD4
U7
U6
U8
U9
AH9
AH10
AH11
AH12
AF11
AF12
+5V_ALW
UC1F
LPSS ISH
GPP_B15/GSPI0_CS#
GPP_B16/GSPI0_CLK
GPP_B17/GSPI0_MISO
GPP_B18/GSPI0_MOSI
GPP_B19/GSPI1_CS#
GPP_B20/GSPI1_CLK
GPP_B21/GSPI1_MISO
GPP_B22/GSPI1_MOSI
GPP_C8/UART0_RXD
GPP_C9/UART0_TXD
GPP_C10/UART0_RTS#
GPP_C11/UART0_CTS#
GPP_C20/UART2_RXD
GPP_C21/UART2_TXD
GPP_C22/UART2_RTS#
GPP_C23/UART2_CTS#
GPP_C16/I2C0_SDA
GPP_C17/I2C0_SCL
GPP_C18/I2C1_SDA
GPP_C19/I2C1_SCL
GPP_F4/I2C2_SDA
GPP_F5/I2C2_SCL
GPP_F6/I2C3_SDA
GPP_F7/I2C3_SCL
GPP_F8/I2C4_SDA
GPP_F9/I2C4_SCL
KBL-RU42_BGA1356
LPSS_UART2_RXD
LPSS_UART2_TXD
+3.3V_RUN
D D
@
RC282 100K_0402_5%
RC237 10K_0402_5 %
RC402 49.9K_0402_1%@
RC403 49.9K_0402_1%@
+3.3V_ALW_PCH
RC283 10K_0402_5%
@
RC330 49.9K_0402_1%
@
RC331 49.9K_0402_1%
C C
+3.3V_RUN
RC186 4.7K_0402_5%@
PCH_3.3V_TS_EN
12
SIO_EXT_SCI#
12
12
12
12
12
12
NRB_BIT
12
LPSS_UART2_RXD
LPSS_UART2_TXD
SIO_EXT_WAKE#
LPSS_UART2_RXD
LPSS_UART2_TXD
TPM_PIRQ#<33>
MEDIACARD_IRQ#<28>
RC560 0_0402_ 5%
@
RC561 0_0402_ 5%
PCH_3.3V_TS_EN<26>
RC405 100K _0402_5%@
SBIOS_TX<32>
I2C1_SDA_TP<37>
I2C1_SCK_TP<37>
1 2
1 2
12
+3.3V_RUN
10K_0402_5%
RC267
ONE_DIMM#
TPM_PIRQ#_R
NRB_BIT
SIO_EXT_SCI#
BBS_BIT6
GPP_C8
TYPEC_CON_SEL1
TYPEC_CON_SEL2
LPSS_UART2_RXD
LPSS_UART2_TXD
NO REBOOT STRAP
HIGH
LOW(DEFAULT)
Weak IPD
B B
+3.3V_ALW_PCH
RC184 8.2K_0402_5%
@
No REBOOT
REBOOT ENABLE
BBS_BIT6
12
1 2
10K_0402_5%
12
DIMM Detect
HIGH
LOW
@
RC268
ONE_DIMM#
1 DIMM
2 DIMM
BOOT BIOS Dest i nat i on(Bi t 6)
HIGH
LOW(DEFAULT)
Internal 20k PD
LPC
SPI
KBL-R U4+2
Sx_EXIT_HOLDOFF# / GPP_A12 / BM_BUSY# / ISH_GP6
CONN@
JUART1
1
1
2
2
3
3
4
4
5
GND
6
GND
CVILU_CI1804M1VRA-NH
Rev_0.1
GPP_D9
GPP_D10
GPP_D11
GPP_D12
GPP_D5/ISH_I2C0_SDA
GPP_D6/ISH_I2C0_SCL
GPP_D7/ISH_I2C1_SDA
GPP_D8/ISH_I2C1_SCL
GPP_F10/I2C5_SDA/ISH_I2C2_SDA
GPP_F11/I2C5_SCL/ISH_I2C2_SCL
GPP_D13/ISH_UART0_RXD/SML0BDATA /I2C4B_SDA
GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_S CL
GPP_D15/ISH_UART0_RTS#
GPP_D16/ISH_UART0_CTS#/SML0BALER T#
GPP_C12/UART1_RXD/ISH_UART1_RXD
GPP_C13/UART1_TXD/ISH_UART1_TXD
GPP_C14/UART1_RTS#/ISH_UART1_RTS#
GPP_C15/UART1_CTS#/ISH_UART1_CTS#
GPP_A18/ISH_GP0
GPP_A19/ISH_GP1
GPP_A20/ISH_GP2
GPP_A21/ISH_GP3
GPP_A22/ISH_GP4
GPP_A23/ISH_GP5
6 OF 20
P2
P3
P4
P1
M4
N3
N1
N2
AD11
AD12
U1
U2
U3
U4
AC1
AC2
AC3
AB4
AY8
BA8
BB7
BA7
AY7
AW7
AP13
MEM_INTERLEAVED
RC555
@
10K_0402_5%
1 2
12
RC556
@
10K_0402_5%
MEM_INTERLEAVED
AR_DET#
ISH_I2C2_SDA
ISH_I2C2_SCL
RTD3_CIO_PWR_EN
CLKDET#
TPM_TYPE
LID_CL#_PCH
ISH_I2C2_SDA <29>
ISH_I2C2_SCL <29>
9/24: Reserve for embedded locat i on ,r ef er I nt el PDG 0. 9
ISH_UART0_RXD <29>
ISH_UART0_TXD <29>
ISH_UART0_RTS# <29>
ISH_UART0_CTS# <29>
SIO_EXT_WAKE# <31>
LCD_CBL_DET# <26>
@
T258
PAD~D
PAD~D
WWAN
WLAN
T18 @PAD~D
@
T268
Reser ved
ISH_I2C2_SDA
ISH_I2C2_SCL
LCD_CBL_DET#
TPM_TYPE
RC363 1K_0402_5%
RC362 1K_0402_5%
RC287 100K_0402_5%
GPP_A GROUP is +1.8V
+3.3V_ALW_PCH +3.3V_ALW_PCH
RC371
10K_0402_5%
1 2
AR_DET#
12
@
10K_0402_5%
RC372
DIMM TYPE
HIGH Interle ave
+3.3V_ALW_PCH+3.3V_ALW_PCH
RC553
@
10K_0402_5%
1 2
TYPEC_CON_SEL2TYPEC_CON_SEL1
12
RC554
@
10K_0402_5%
1 2
12
1 2
1 2
1 2
1 2
RC349 100_0402_1%@
RC400
10K_0402_5%
@
10K_0402_5%
RC401
+1.8V_RUN
+3.3V_RUN
AR_DET #
NON ARHIGH
LOW ARLOW Non-Interl eave
A A
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.
5
4
3
Vendor
TYPEC_CON_SE L1 LOW
TYPEC_CON_SE L2
LOW
FOXCONJAE
LOW
HIGH LOW
TBDTBD
HIGHHIGH
HIGH
2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document N umber Re v
Size Document N umber Re v
Size Document N umber Re v
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (4/14)
CPU (4/14)
CPU (4/14)
LA-F312P
LA-F312P
LA-F312P
9 58Wednesday, December 20, 2017
9 58Wednesday, December 20, 2017
9 58Wednesday, December 20, 2017
1
2.0
2.0
2.0
5
4
3
2
1
Steamboat MLK 12&13 nonAR
CPU@
UC1H
PCIE / USB3 / SATA
D D
Card Reader RTS5242----->
Ext USB3 Port 1 Charge (Right) ----->
M.2 3030(WLAN) --->
10/100/1G LAN --->
C C
M.2 3042(SATA Cache )--->
M2 2280 SSD (4 Lane) --->
B B
PCIE_PRX_DTX_N1<28>
PCIE_PRX_DTX_P1<28>
PCIE_PTX_DRX_N1<28>
PCIE_PTX_DRX_P1<28>
USB3_PRX_DTX_N6<35>
USB3_PRX_DTX_P6<35>
USB3_PTX_DRX_N6<35>
USB3_PTX_DRX_P6<35>
PCIE_PRX_DTX_N3<29>
PCIE_PRX_DTX_P3<29>
PCIE_PTX_DRX_N3<29>
PCIE_PTX_DRX_P3<29>
PCIE_PRX_DTX_N4<27>
PCIE_PRX_DTX_P4<27>
PCIE_PTX_DRX_N4<27>
PCIE_PTX_DRX_P4<27>
SATA_PRX_DTX_N1<29>
SATA_PRX_DTX_P1<29>
SATA_PTX_DRX_N1<29>
SATA_PTX_DRX_P1<29>
PCIE_PRX_DTX_N9<34>
PCIE_PRX_DTX_P9<34>
PCIE_PTX_DRX_N9<34>
PCIE_PTX_DRX_P9<34>
PCIE_PRX_DTX_N10<34>
PCIE_PRX_DTX_P10<34>
PCIE_PTX_DRX_N10<34>
PCIE_PTX_DRX_P10<34>
1 2
RC45 100_0402_1%
CPU_XDP_PRDY#<14>
CPU_XDP_PREQ#<14>
PCIE_PRX_DTX_N11<34>
PCIE_PRX_DTX_P11<34>
PCIE_PTX_DRX_N11<34>
PCIE_PTX_DRX_P11<34>
PCIE_PRX_DTX_N12<34>
PCIE_PRX_DTX_P12<34>
PCIE_PTX_DRX_N12<34>
PCIE_PTX_DRX_P12<34>
PCIE_RCOMPN
PCIE_RCOMPP
H13
PCIE1_RXN/USB3_5_RXN
G13
PCIE1_RXP/USB3_5_RXP
B17
PCIE1_TXN/USB3_5_TXN
A17
PCIE1_TXP/USB3_5_TXP
G11
PCIE2_RXN/USB3_6_RXN
F11
PCIE2_RXP/USB3_6_RXP
D16
PCIE2_TXN/USB3_6_TXN
C16
PCIE2_TXP/USB3_6_TXP
H16
PCIE3_RXN
G16
PCIE3_RXP
D17
PCIE3_TXN
C17
PCIE3_TXP
G15
PCIE4_RXN
F15
PCIE4_RXP
B19
PCIE4_TXN
A19
PCIE4_TXP
F16
PCIE5_RXN
E16
PCIE5_RXP
C19
PCIE5_TXN
D19
PCIE5_TXP
G18
PCIE6_RXN
F18
PCIE6_RXP
D20
PCIE6_TXN
C20
PCIE6_TXP
F20
PCIE7_RXN/SATA0_RXN
E20
PCIE7_RXP/SATA0_RXP
B21
PCIE7_TXN/SATA0_TXN
A21
PCIE7_TXP/SATA0_TXP
G21
PCIE8_RXN/SATA1A_RXN
F21
PCIE8_RXP/SATA1A_RXP
D21
PCIE8_TXN/SATA1A_TXN
C21
PCIE8_TXP/SATA1A_TXP
E22
PCIE9_RXN
E23
PCIE9_RXP
B23
PCIE9_TXN
A23
PCIE9_TXP
F25
PCIE10_RXN
E25
PCIE10_RXP
D23
PCIE10_TXN
C23
PCIE10_TXP
F5
PCIE_RCOMPN
E5
PCIE_RCOMPP
D56
PROC_PRDY#
D61
PROC_PREQ#
BB11
GPP_A7/PIRQA#
E28
PCIE11_RXN/SATA1B_RXN
E27
PCIE11_RXP/SATA1B_RXP
D24
PCIE11_TXN/SATA1B_TXN
C24
PCIE11_TXP/SATA1B_TXP
E30
PCIE12_RXN/SATA2_RXN
F30
PCIE12_RXP/SATA2_RXP
A25
PCIE12_TXN/SATA2_TXN
B25
PCIE12_TXP/SATA2_TXP
KBL-RU42_BGA1356
KBL-R U4+2
SSIC / USB3
USB3_2_RXN/SSIC_RXN
USB3_2_RXP/SSIC_RXP
USB3_2_TXN/SSIC_TXN
USB3_2_TXP/SSIC_TXP
USB2
USB2_VBUSSENSE
GPP_E9/USB2_OC0#
GPP_E10/USB2_OC1#
GPP_E11/USB2_OC2#
GPP_E12/USB2_OC3#
GPP_E4/DEVSLP0
GPP_E5/DEVSLP1
GPP_E6/DEVSLP2
GPP_E0/SATAXPCIE0/SATAGP0
GPP_E1/SATAXPCIE1/SATAGP1
GPP_E2/SATAXPCIE2/SATAGP2
GPP_E8/SATALED#
Rev_0.1
USB3_1_RXN
USB3_1_RXP
USB3_1_TXN
USB3_1_TXP
USB3_3_RXN
USB3_3_RXP
USB3_3_TXN
USB3_3_TXP
USB3_4_RXN
USB3_4_RXP
USB3_4_TXN
USB3_4_TXP
USB2N_1
USB2P_1
USB2N_2
USB2P_2
USB2N_3
USB2P_3
USB2N_4
USB2P_4
USB2N_5
USB2P_5
USB2N_6
USB2P_6
USB2N_7
USB2P_7
USB2N_8
USB2P_8
USB2N_9
USB2P_9
USB2N_10
USB2P_10
USB2_COMP
USB2_ID
8 OF 20
H8
G8
C13
D13
J6
H6
B13
A13
J10
H10
B15
A15
E10
F10
C15
D15
AB9
AB10
AD6
AD7
AH3
AJ3
AD9
AD10
AJ1
AJ2
AF6
AF7
AH1
AH2
AF8
AF9
AG1
AG2
AH7
AH8
AB6
AG3
AG4
A9
C9
D9
B9
J1
J2
J3
H2
H3
G4
H1
USBCOMP
USB2_ID
USB2_VBUSSENSE
USB_OC2#
USB_OC3#
Rese rve
SATAGP0
M3042_PCIE#_SATA
M2280_PCIE_SATA#
SATALED#
USB3_PRX_DTX_N1 <22>
USB3_PRX_DTX_P1 <22>
USB3_PTX_DRX_N1 <22>
USB3_PTX_DRX_P1 <2 2>
USB3_PRX_DTX_N2 <29>
USB3_PRX_DTX_P2 <29>
USB3_PTX_DRX_N2 <29>
USB3_PTX_DRX_P2 <2 9>
USB3_PRX_DTX_N3 <36>
USB3_PRX_DTX_P3 <36>
USB3_PTX_DRX_N3 <36>
USB3_PTX_DRX_P3 <3 6>
USB20_N1 <23>
USB20_P1 <23>
USB20_N2 <36>
USB20_P2 <36>
USB20_N4 <29>
USB20_P4 <29>
USB20_N5 <26>
USB20_P5 <26>
USB20_N7 <29>
USB20_P7 <29>
USB20_N8 <26>
USB20_P8 <26>
USB20_N9 <35>
USB20_P9 <35>
USB20_N10 <33>
USB20_P10 <33>
1 2
RC44 113_0402_1%
USB2_ID <23>
1 2
RC338 1K_0402_5%
USB_OC0# <35>
USB_OC1# <36>
M3042_DEVSLP <29>
M2280_DEVSLP <34>
M3042_PCIE#_SATA <31>
M2280_PCIE_SATA# <34>
SATALED# <29,34,38>
-----> Typce-C(Non AR)
-----> M.2 3042(LTE)
-----> Ext USB3 Port 2 (Lert Front)
-----> Typce-C(Non AR)
-----> Ext USB Port 2(Lef t Front)
-----> M2 3042(WWAN)
-----> Camera
-----> M.2 3030(BT)
-----> LCD Touch
-----> Ext USB Port 1 Charge (Right)
-----> USH
NEED DOUBLE C HECK
USB_OC3#
USB_OC0#
USB_OC1#
USB_OC2#
USB2_ID
RPC3
4 5
3
6
2
7
1
8
10K_8P4R_5%
1 2
RC337 10K_0402_5%
+3.3V_ALW_PCH
+3.3V_RUN
M2280_PCIE_SATA#
SATALED#
M3042_PCIE#_SATA
A A
SATAGP0
RPC4
4 5
3
2
1
10K_8P4R_5%
6
7
8
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.
5
4
3
2
Title
Size Document N umber Re v
Size Document N umber Re v
Size Document N umber Re v
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (5/14)
CPU (5/14)
CPU (5/14)
LA-F312P
LA-F312P
LA-F312P
10 58Wednesday, December 20, 2017
10 58Wednesday, December 20, 2017
10 58Wednesday, December 20, 2017
1
2.0
2.0
2.0
5
CLK_PCIE_N0<28>
Cardreader-- ->
D D
WLAN--->
M.2 SDD--->
LAN--->
+3.3V_LAN
C C
+3.3V_ALW_DSW
+1.0V_VCCST
+3.3V_ALW_PCH
B B
+3.3V_1.8V_PGPPA
@
CLK_PCIE_P0<28>
CLKREQ_PCIE#0<28>
CLK_PCIE_N1<29>
CLK_PCIE_P1<29>
CLKREQ_PCIE#1<29>
CLK_PCIE_N3<34>
CLK_PCIE_P3<34>
CLKREQ_PCIE#3<34>
CLK_PCIE_N4<27>
CLK_PCIE_P4<27>
CLKREQ_PCIE#4<27>
RL70 10K_0402_5%@
RC323 10K_0402_5%
RC67 1K_0402 _5%
RC71 1K_0402 _5%
RC74 10K_0402_5%@
10/6 depop, prevent singal step.
RC411 10K_0402_5%@
@
T9
PAD~D
VCCST_PWRGD<14,31,32>
ME_SUS_PWR_ACK<31>
RC550 1K_0402_ 5%
12
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
12
12
12
12
12
12
SUSACK#<31>
SUSACK#_R
@RF@
RC373 0_0402_5%
RC189 10K_0402_5%
@RF@
RC374 0_0402_5%
RC47 10K_0402_5%
RC50 10K_0402_5%
@RF@
RC376 0_0402_5%
RC59 10K_0402_5%
@RF@
RC377 0_0402_5%
RC51 10K_0402_5%
RC190 10K_0402_5%
LAN_WAKE#
PCH_PCIE_WAKE#
VCCST_PWRGD
ME_SUS_PWR_ACK
PCH_PWROK
RC77 1K_0402 _5%@
RC78 60.4_0402_1%
@
RC444 0_0402_5%
RC443 0_0402_5%@
1 2
12
1 2
12
12
1 2
12
1 2
12
12
PCH_PLTRST#
H_CPUPWRGD VCCST_PWRGD
100P_0402_50V8J
12
PCH_RSMRST#_AND<14,37>
1 2
1 2
1 2
1 2
PCH_PCIE_WAKE#<31,32>
PM_LANPHY_ENABLE<27>
CLKREQ_PCIE#0_R
CLKREQ_PCIE#1_R
CLKREQ_PCIE#2_R
CLKREQ_PCIE#3_R
CLKREQ_PCIE#4_R
CLKREQ_PCIE#5_R
@
RC62 0_0402_5%
@
RC244 0_0402_5%
UC7
TC7SH08FU_SSOP5~D
100P_0402_50V8J
12
CC300ESD@
SYS_PWROK< 14,31>
PCH_PWROK<46>
PCH_DPWROK<31>
LAN_WAKE#<27,31>
3.3V_CAM_EN#<26>
CC301ESD@
ESD Request:place near CPU side
PCH_PLTRST#
SYS_RESET#
PCH_RSMRST#_AND
H_CPUPWRGDH_CPUPWRGD_R
VCCST_PWRGD_CPU
ME_SUS_PWR_ACK_R
SUSACK#_R
RC311 10K_0 402_5%
1 2
1 2
+3.3V_ALW_PCH
1
B
2
A
12
RC215
POP
NO Support Deep sleep
DE-POP
PCH_DPWROK PCH_RSMRST#_AND
A A
1
2
1 2
RC215 0_0402_5%NDS3@
100K_0402_1%
0.01UF_0402_25V7K
12
@
RC220
CC266
12
RC75
10K_0402_5%
5
Support Deep sleep
XDP_DBRESET#<14>
+3.3V_RUN
XDP_DBRESET#
RC225@ 8.2K_0402_5%
RC227@ 8.2K_0402_5%
12
12
4
CPU@
UC1J
D42
CLKOUT_PCIE_N0
C42
CLKOUT_PCIE_P0
AR10
GPP_B5/SRCCLKREQ0#
B42
CLKOUT_PCIE_N1
A42
CLKOUT_PCIE_P1
AT7
GPP_B6/SRCCLKREQ1#
D41
CLKOUT_PCIE_N2
C41
CLKOUT_PCIE_P2
AT8
GPP_B7/SRCCLKREQ2#
D40
CLKOUT_PCIE_N3
C40
CLKOUT_PCIE_P3
AT10
GPP_B8/SRCCLKREQ3#
B40
CLKOUT_PCIE_N4
A40
CLKOUT_PCIE_P4
AU8
GPP_B9/SRCCLKREQ4#
E40
CLKOUT_PCIE_N5
E38
CLKOUT_PCIE_P5
AU7
GPP_B10/SRCCLKREQ5#
KBL-RU42_BGA1356
5
P
PCH_PLTRST#_AND
4
O
12
G
3
@
100K_0402_5%
UC1K
AN10
GPP_B13/PLTRST#
B5
SYS_RESET#
AY17
RSMRST#
A68
PROCPWRGD
B65
VCCST_PWRGD
B6
SYS_PWROK
BA20
PCH_PWROK
BB20
DSW_PWR OK
AR13
GPP_A13/SUSWARN#/SUSPWRDNACK
AP11
GPP_A15/SUSACK#
BB15
WAKE#
AM15
GPD2/LAN_WAKE#
AW17
GPD11/LANPHYPC
AT15
GPD7/RSVD
KBL-RU42_BGA1356
@
RC290 0_0402_5%
ME_RESET#
PLTRST_LAN# <27>
PCH_PLTRST#_EC <32>
RC65
CPU@
SYSTEM POWER MANAGEMENT
1 2
+3.3V_RUN
1
B
2
A
KBL-R U4+2
CLOCK SIGNALS
PCH_PLTRST#_AND <28,29, 33,34>
KBL-R U4+2
5
P
O
G
74AHC1G09GW_TSSOP5
3
SYS_RESET#_R
4
UC12@
RSVD_E3/XTAL24_IN
RSVD_C7/XTAL24_OUT
XTAL24_OUT/NC_1
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P
VCCDSW_EN_GPIO<18>
VCCDSW_EN<31>
ALW_PWRGD_3V_5V<37,41>
GPP_B11/EXT_PWR_GATE#
RC224 1K_0402_5%
KBL-U / KBL-R U4+2
XTAL24_IN/NC_2
GPD8/SUSCLK
XCLK_BIASREF
1 2
if pop UC12, RC291 also need pop(74AHC1G09GW is OD output)
4
3
Rev_0.1
XTAL24_IN_U42_CPU XTAL24_IN_U42
E3
XTAL24_OUT_U42_CPU
C7
XTAL24_IN_U22_CPU
E37
XTAL24_OUT_U22_CPU
E35
CLK_ITPXDP_N
F43
CLK_ITPXDP_P
E43
BA17
SUSCLK
XCLK_BIASREF
E42
PCH_RTCX1
AM18
RTCX1
RTCX2
SRTCRST#
RTCRST#
10 OF 20
AM20
AN18
AM16
PCH_RTCX2
SRTCRST#
PCH_RTCRST# <31>
CMOS1 m ust take care short & touch risk on layout plac ement
PCH_PLTRST#
PCH_PLTRST#_AND
RC445
1 2
0_0402_5%
Rev_0.1
GPP_B12/SLP_S0#
GPD4/SLP_S3#
GPD5/SLP_S4#
GPD10/SLP_S5#
SLP_SUS#
SLP_LAN#
GPD9/SLP_WLAN#
GPD6/SLP_A#
GPD3/PWRBTN#
GPD1/ACPRESENT
GPD0/BATLOW#
GPP_A11/PME#
INTRUDER#
GPP_B2/VRALERT#
11 OF 20
+3.3V_RUN
1 2
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
1 2
RC60 0_0402_5%
@
RC325 0_0402_5%
@
1 2
NDS3@
RB751S40T1G_SOD523-2
SIO_SLP_S0#
AT11
AP15
BA16
AY16
AN15
AW15
BB17
AN16
BA15
AY15
PCH_BATLOW#
AU13
AU11
PME#
AP16
INTRUDER#
MPHYP_PWR_EN
AM10
AM11
VRALERT#
@
RC291
10K_0402_5%
SYS_RESET#
3
RC417 0_0402_5%
U42@
U42@
U22@
U22@
@
DC1
2 1
NDS3@
RB751S40T1G_SOD523-2
1 2
1 2
RC418 0_0402_5%
RC419 0_0402_5%
1 2
1 2
RC420 0_0402_5%
1 2
RC297 0_0402_5%
@
RC298 0_0402_5%
@
1 2
SUSCLK <29 ,34>
1 2
RC52 2.7K_0402_1%
1 2
RC324 59_0402_1%
546765_54 6765_201 4WW48 _Skylake_MO W_Rev_1_ 0
RC56 20K_0402_5%
1 2
1 2
CC24 1U_0 402_6.3V6K
RC57 20K_0402_5%
1 2
1 2
CC25 1U_0 402_6.3V6K
1
1
2
SHORT PADS~D
@
CMOS1
PLTRST_TPM# <33>
SIO_SLP_SUS#
VCCDSW_EN_Q
DC2
21
SIO_SLP_S0# <17,33,44>
SIO_SLP_S3# <31,32>
SIO_SLP_S4# <17,31,42,45>
SIO_SLP_S5# <31>
SIO_SLP_SUS# <31>
SIO_SLP_LAN# <31,39>
SIO_SLP_WLAN# <31,39>
SIO_SLP_A# <31>
SIO_PWRBTN# <14,31>
AC_PRESENT <31>
@
T115
PAD~D
connect to VCCMPHYGTAON_1P0 enable pin
XTAL24_OUT_U42
XTAL24_IN_U22
XTAL24_OUT_U22
CLK_ITPXDP_N_R <14>
CLK_ITPXDP_P_R <14>
+1.0V_CLK5
For Skylake, pop RC52,depop RC324
For Cannonlake, pop RC324,depop RC52
+RTC_CELL_PCH
2
@DS3@
RC441
1 2
0_0402_5%
RC442
NDS3@
1 2
0_0402_5%
Support DS3
No Support DS3
'V' mean POP, 'X' mean DE-POP
SYS_RESET#
0.1U_0402_25V6
@ESD@
12
CC302
ESD Request:place near CPU side
2
For KBL-R U22
U22@
1M_0402_1%
RC46
XTAL24_IN_U22
XTAL24_OUT_U22
1 2
For Skylake,YC1 24 MHz (50 Ohm ESR)
For Cannonlake,YC1 38.4 MHz (30 Ohm ESR)
546765_54 6765_201 4WW48 _Skylake_MO W_Rev_1_ 0
For KBL-R U42
U42@
1M_0402_1%
RC415
XTAL24_IN_U42
XTAL24_OUT_U42PCH_RTCRST#
PCH_RTCX1
PCH_RTCX2
PCH_PRIM_EN <17,39,43 ,44,45>
RC439
RC440 RE536RC21 5RC441RC44 2
V V V
X
V V V
X X
+3.3V_ALW_PCH
+3.3V_ALW
+3.3V_ALW
POWER_SW#_MB<32,38>
DELL CONFIDENTIAL/PROPRIETARY
Title
Title
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Date : Sheet of
Date : Sheet of
2
Date : Sheet of
1 2
For Skylake,YC3 24 MHz (50 Ohm ESR)
RC54
10M_0402_5%
1 2
1 2
@
RC296 0_0402_5%
8/21 can change to 10K for merge to RP
PCH_BATLOW#
AC_PRESENT
INTRUDER#
MPHYP_PWR_EN
VRALERT#
X
X
X
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
SIO_SLP_LAN#
SUSCLK
SIO_SLP_S3#
SIO_SLP_S5#
SIO_SLP_S4#
SIO_SLP_A#
PCH_RTCRST#
SYS_RESET#
SIO_SLP_S0#
CPU (6/14)
CPU (6/14)
CPU (6/14)
LA-F312P
LA-F312P
LA-F312P
PCH_RTCX2_R
JAPS1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
CVILU_CF4218FH0R0-05-NH
1
U22@
CC21
1 2
3
4
1
2
3
4
1
2
12
RC72 8.2K_0402_5%
RC243 10K_0402_5%
RC387 10K_0402_5%@
RC73 10K_0402_5%
@
RC344 10K_0402_5%@
RC68 10K_0402_5%@
RC48 1K_0402_5%@
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
GND
GND
11 58Wednesday, December 20, 2017
11 58Wednesday, December 20, 2017
11 58Wednesday, December 20, 2017
12P_0402_50V8J
U22@
YC1
24MHZ_12PF_X3G024 000DC1H
U22@
CC22
1 2
12P_0402_50V8J
U42@
CC334
1 2
12P_0402_50V8J
U42@
YC3
24MHZ_12PF_X3G024 000DC1H
U42@
CC335
1 2
12P_0402_50V8J
CC23
1 2
15P_0402_50V8J
YC2
32.768KHZ_12.5PF_9H03200042
ESR MAX=50k ohm
CC26
1 2
12P_0402_50V8J
1 2
1 2
+RTC_CELL_PCH
1 2
RC69 1M_0402_5%
1 2
1 2
1 2
1 2
1 2
CONN@
2.0
2.0
2.0
1
+3.3V_ALW_DSW
+3.3V_ALW_PCH
+3.3V_ALW
5
4
3
2
+1.0V_VCCSTG
1
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS
1 2
RC86 51_0402_5%
Service Mode Switch:
Add a switch to ME_FWP signal to unlock the ME region and
allow the ent ir e r egi on of t he SPI fl ash to be updat ed usi ng FPT.
+3.3V_ALW_PCH
ME_FWP PCH has internal 20K PD.
(suspend power rail)
FLASH DESCRIPTOR SECURITY OVERRIDE
LOW = ENABLE (DEFAULT) -->Pin1 & Pin3 short
HIGH = DISABLE (ME can update) -->Pin2 & Pin3 short
CAM_MIC_CBL_DET# <26>
CONTACTLESS_DET# <33>
HOST_SD_WP# <28>
AUD_PWR_EN <30>
0.1U_0402_25V6
@ESD@
12
CC304
2
CPU MISC
KBL-R U4+2
KBL-R U4+2
1
2
CC332
RF@
2.2P_0402_50V8C
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.
Rev_0.1
JTAG
PROC_TCK
PROC_TDI
PROC_TDO
PROC_TMS
PROC_TRST#
PCH_JTAG_TCK
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS
PCH_TRST#
JTAGX
4 OF 20
GPP_A17/SD_PWR_EN#/ISH_GP7
1
2
CC333
RF@
2.2P_0402_50V8C
3
CPU_XDP_TCLK XDP_JTAGX
@
RC328 0_0402_5%
CPU_XDP_TCLK
B61
CPU_XDP_TDI
D60
CPU_XDP_TDO
A61
CPU_XDP_TMS
C60
CPU_XDP_TRST#
B59
PCH_JTAG_TCK
B56
PCH_JTAG_TDI
D59
PCH_JTAG_TDO
A56
PCH_JTAG_TMS
C59
CPU_XDP_TRST#
C61
XDP_JTAGX
A59
SDIO / SDXC
GPP_G0/SD_CMD
GPP_G1/SD_DATA0
GPP_G2/SD_DATA1
GPP_G3/SD_DATA2
GPP_G4/SD_DATA3
GPP_A16/SD_1P8_SEL
RC87 1K_0402_5%@
Rev_0.1
GPP_G5/SD_CD#
GPP_G6/SD_CLK
GPP_G7/SD_WP
SD_RCOMP
GPP_F23
7 OF 20
1 2
AB11
AB13
AB12
W12
W11
W10
W8
W7
BA9
BB9
AB7
AF13
1 2
CPU_XDP_TCLK <14>
CPU_XDP_TDI <14>
CPU_XDP_TDO <14>
CPU_XDP_TMS <14>
CPU_XDP_TRST# <14>
PCH_JTAG_TCK <14>
PCH_JTAG_TDI <14>
PCH_JTAG_TDO <14>
PCH_JTAG_TMS <14>
+1.0V_VCCSTG
CONTACTLESS_DET#
AUD_PWR_EN
SD_RCOMP
RC96 200_0402_1%
PCH_JTAG_TDO PCH_JTAG_TDI XDP_JTAGX
0.1U_0402_25V6
@ESD@
12
CC303
@
1 2
ESD request,Place near CPU side.
CPU@
D D
+1.0V_VCCST
RC79 49 .9_0402_1%@
RC80 1K_0402_5%
+1.0V_VCCSTG
RC83 1K_0402_5%
+3.3V_RUN
RC414 10K_ 0402_5%
RC413 10K_ 0402_5%
C C
B B
RC278 10K_ 0402_5%
RC272 10K_ 0402_5%
@
RC279 10 K_0402_5%
RC345 100K_0402_5%
RC292 10 K_0402_5%
+3.3V_ALW_PCH
RC346 10K_ 0402_5%
RC288 10K_0402_5%
H_CATERR#
12
H_THERMTRIP#
12
12
PROCHOT#
TOUCHPAD_INTR#
12
CAM_MIC_CBL_DET#
12
CONTACTLESS_DET#
12
TOUCH_SCREEN_PD#
12
AUD_PWR_EN
12
IR_CAM_DET#
12
HOST_SD_WP#
12
SIO_EXT_SMI#
12
KB_DET#
12
HDA_SYNC_R<30>
HDA_BIT_CLK_R<30>
HDA_SDOUT_R<30>
HDA_RST#_R<30>
Close to RC93
TOUCH_SCREEN_PD# don't move to RPC,
ME_FWP_PCH
HDA_BIT_CLK_R
12
PECI_EC<31>
PROCHOT#<31,46,49>
H_THERMTRIP#<20,32>
TOUCH_SCREEN_DET#<26>
1 2
RC92 33_0402_5%
1 2
RC93 33_0402_5%EMI@
1 2
RC94 33_0402_5%
1 2
RC223 1K_0402_5%
1 2
RC95 33_0402_5%
RF@
47P_0402_50V8J
CC27
1 2
RC84 499_0402_1%
XDP_OBS0_R<14>
XDP_OBS1_R<14>
@
T10
PAD~D
@
T11
PAD~D
TOUCH_SCREEN_PD#<26>
TOUCHPAD_INTR#<31,37>
12
12
RC88
49.9_0402_1%
IR_CAM_DET#<26>
KB_DET#<37>
SPKR<30>
RC89
HDA_SYNC
HDA_BIT_CLK
HDA_SDOUT
HDA_SDIN0<30>
HDA_RST#
PROCHOT#_R
H_THERMTRIP#
XDP_OBS2_R
XDP_OBS3_R
SIO_EXT_SMI#
TOUCHPAD_INTR#
CPU_POPIRCOMP
PCH_POPIRCOMP
EDRAM_OPIO_RCOMP
EOPIO_RCOMP
12
12
RC90
49.9_0402_1%
49.9_0402_1%
IR_CAM_DET#
KB_DET#
H_CATERR#
RC91
49.9_0402_1%
D63
A54
C65
C63
A65
C55
D55
B54
C56
A6
A7
BA5
AY5
AT16
AU16
H66
H65
UC1G
BA22
HDA_SYNC/I2S0_SFRM
AY22
HDA_BLK/I2S0_SCLK
BB22
HDA_SDO/I2S0_TXD
BA21
HDA_SDI0/I2S0_RXD
AY21
HDA_SDI1/I2S1_RXD
AW22
HDA_RST#/I2S1_SCLK
J5
GPP_D23/I2S_MCLK
AY20
I2S1_SFRM
AW20
I2S1_TXD
AK7
GPP_F1/I2S2_SFRM
AK6
GPP_F0/I2S2_SCLK
AK9
GPP_F2/I2S2_TXD
AK10
GPP_F3/I2S2_RXD
H5
GPP_D19/DMIC_CLK0
D7
GPP_D20/DMIC_DATA0
D8
GPP_D17/DMIC_CLK1
C8
GPP_D18/DMIC_DATA1
AW5
GPP_B14/SPKR
KBL-RU42_BGA1356
UC1D
CATERR#
PECI
PROCHOT#
THERMTRIP#
SKTOCC#
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
GPP_E3/CPU_GP0
GPP_E7/CPU_GP1
GPP_B3/CPU_GP2
GPP_B4/CPU_GP3
PROC_POPIRCOMP
PCH_OPIRCOMP
OPCE_RCOMP
OPC_RCOMP
KBL-RU42_BGA1356
CPU@
AUDIO
RF Request. Place near CPU side (Intel MOW)
+3.3V_ALW_PCH +3.3V_ALW_PCH
HDA_SDOUT
12
ENABLE
DISAB LE
SPKR
5
RC183 8.2K_0402_5%
@
TOP SWAP STRAP
A A
HIGH
LOW(DEFAULT)
Internal 20k PD
@
Flash Descriptor Security override
HIGH
LOW(DEFAULT)
12
RC187 4.7K_0402_5%
DISABLE
ENABLE
4
HDA_RST# HD A_SDIN0 HDA_SDOUT
1
2
CC331
RF@
2.2P_0402_50V8C
1 2
RC81 51_0402_5%
1 2
RC82 100_0402_5%
1 2
RC130 51_0402_5%
ME_FWP_PCHME_FWP
1 2
@
RC221 0_0402_5%
PT,ST pop RC222 and SW1; MP pop RC221
@
RC222
1K_0402_5%
1 2
ME_FWP<31>
0.1U_0402_25V6
@ESD@
12
CC305
ME_FWP_PCH
H_THERMTRIP#
0.1U_0402_25V6
@ESD@
12
CC312
@
SW1
1
A
2
B
3
C
4
G1
5
G2
SS3-CMFTQR9_3P
PROCHOT#
0.1U_0402_25V6
12
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document N umber Re v
Size Document N umber Re v
Size Document N umber Re v
Date: Sheet o f
Date: Sheet o f
Date: Sheet o f
Compal Electronics, Inc.
CPU (7/14)
CPU (7/14)
CPU (7/14)
LA-F312P
LA-F312P
LA-F312P
1
@ESD@
CC310
2.0
2.0
12 58Wednesday, December 20, 2017
12 58Wednesday, December 20, 2017
12 58Wednesday, December 20, 2017
2.0
5
D D
4
CFG[0..19]<14>
3
2
1
CFG[2][5][6][7] for SKYLAKE-H CPU CFG strap pin
12
RC113 10K_0402_1%
@
CFG0
RC112 10K_0402_1%
@
RC110 10K_0402_1%
@
12
12
Stall reset sequence
HIGH(DEFAULT )
LOW
C C
RC109 1K_0402_5%
eDP enable
HIGH(DEFAULT )
LOW
B B
No stall(Normal Operat i on)
sta ll
12
CFG4
Disa bled
Enabled
+1.0V_PRIM_XDP
RC114 49.9_0402_1%
RC115 1.5K_0402_5%
ITP_PMODE<14>
@
T16
PAD~D
@
T17
PAD~D
1 2
U42@
RC436 0_0402_5%
CFG_RCOMP
12
ITP_PMODE
12
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
UC1S
E68
CFG[0]
B67
CFG[1]
D65
CFG[2]
D67
CFG[3]
E70
CFG[4]
C68
CFG[5]
D68
CFG[6]
C67
CFG[7]
F71
CFG[8]
G69
CFG[9]
F70
CFG[10]
G68
CFG[11]
H70
CFG[12]
G71
CFG[13]
H69
CFG[14]
G70
CFG[15]
E63
CFG[16]
F63
CFG[17]
E66
CFG[18]
F66
CFG[19]
E60
CFG_RCOMP
E8
ITP_PMODE
AY2
RSVD_AY2
AY1
RSVD_AY1
D1
RSVD_D1
D3
RSVD_D3
K46
RSVD_K46
K45
RSVD_K45
AL25
RSVD_AL25
AL27
RSVD_AL27
C71
RSVD_C71
B70
RSVD_B70
F60
RSVD_F60
A52
RSVD_A52
BA70
RSVD_TP_BA70
BA68
RSVD_TP_BA68
J71
RSVD_J71
J68
RSVD_J68
F65
VSS_F65
G65
VSS_G65
F61
RSVD_F61
E61
RSVD_E61
KBL-RU42_BGA1356
CPU@
KBL-R U4+2
RESERVED SIGNALS-1
Rev_0.1
RSVD_TP_BB68
RSVD_TP_BB69
RSVD_TP_AK13
RSVD_TP_AK12
RSVD_BB2
RSVD_BA3
RSVD_D5
RSVD_D4
RSVD_B2
RSVD_C2
RSVD_B3
RSVD_A3
RSVD_AW1
RSVD_E1
RSVD_E2
RSVD_BA4
RSVD_BB4
RSVD_A4
RSVD_C4
RSVD_A69
RSVD_B69
RSVD_AY3
RSVD_D71
RSVD_C70
RSVD_C54
RSVD_D54
VSS_AY71
ZVM#
RSVD_TP
RSVD_TP
MSM#
PROC_SELECT#
19 OF 20
UC1T
BB68
BB69
AK13
AK12
BB2
BA3
AU5
TP5
AT5
TP6
D5
D4
B2
C2
B3
A3
AW1
E1
E2
BA4
BB4
A4
C4
BB5
TP4
A69
B69
AY3
D71
C70
C54
D54
AY4
TP1
BB3
TP2
AY71
AR56
AW71
AW70
AP56
C64
@
T12
PAD~D
@
T13
PAD~D
@
T14
PAD~D
@
T15
PAD~D
@
T130
PAD~D
@
T126
PAD~D
@
T127
PAD~D
@
T113
PAD~D
@
T114
PAD~D
1 2
RC120 100K_0402_5%@
For Skylake , RC120 depop
For Cannonlake, RC120 pop
546765_546765_2014WW48_ Skylake_MOW_R ev_1_0
1/5 2014 WW52 MOW reserve to support
Cannonlake-U PCH compatibility
close UC1.U11/U12 and <400mil
1 2
RC313 0_0402_5%
@
+1.0V_VCCST
+VCC_1P8+1 .8V_PRIM
AW69
AW68
AU56
AW48
U12
U11
1
2
H11
CC222
@
1U_0402_6.3V6K
KBL-RU42_BGA1356
RSVD_AW69
RSVD_AW68
RSVD_AU56
RSVD_AW48
RSVD_U12
RSVD_U11
RSVD_H11
SPARE
Rev_0.1
RSVD_F6
RSVD_C11
RSVD_B11
RSVD_A11
RSVD_D12
RSVD_C12
RSVD_F52
20 OF 20
F6
C11
B11
A11
D12
C12
F52
KBL-R U4+2
CPU@
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.
5
4
3
2
Title
Size Document N umber Re v
Size Document N umber Re v
Size Document N umber Re v
Date: Sheet o f
Date: Sheet o f
Date: Sheet o f
Compal Electronics, Inc.
CPU (8/14)
CPU (8/14)
CPU (8/14)
LA-F312P
LA-F312P
LA-F312P
13 58Wednesday, December 20, 2017
13 58Wednesday, December 20, 2017
13 58Wednesday, December 20, 2017
1
2.0
2.0
2.0
+1.0V_PRIM
@
1 2
RC216 0_0603_5%
+1.0V_PRIM_XDP
0.1U_0201_10V6K
0.1U_0201_10V6K
@
CC28
1
1
2
2
D D
Place near
JXDP1
VCCST_PWRGD<11,31,32>
PCH_RSMRST#_AND<11,37>
+1.0VS_VCCIO
C C
+1.0V_VCCST
+3.3V_RUN
+1.0V_PRIM_XDP
5
+1.0V_PRIM_XDP
@
CC29
XDP_OBS0_R<12>
XDP_OBS1_R<12>
RC123 1K_0402_5%@
RC124CXDP@
PCH_SPI_DO_XDP<8>
SYS_PWROK<11,31>
RC132 150_0402_5%
RC218 150_0402_5%@
RC219 10K_0402_5%@
RC137 3K_0402_5%
RC138 51_0402_5%
@
RC239 0_0402_5%
CXDP@
RC240 0_0402_5%
CXDP@
RC5 need to close to JCPU1
1 2
1 2
1K_0402_5%
12
12
12
12
12
FIVR_EN
CFG0
RC217 0_0402_5%
@
RC126 1K_0402_5%@
RC128 0_0402_5%
CXDP@
RC129 0_0402_5%
@
DDR_XDP_WAN_S MBDAT<8,20>
DDR_XDP_WAN_S MBCLK<8,20>
FIVR_EN_R
FIVR_EN
FIVR_EN
XDP_DBRESET#
CPU_XDP_PREQ#
CPU_XDP_PREQ#<10>
CPU_XDP_PRDY#<10>
1 2
1 2
1 2
1 2
1 2
1 2
PCH_JTAG_TCK<12>
CPU_XDP_TCLK<12>
CPU XDP
H_VCCST_PWRGD_XD P
SIO_PWRBTN#<11,31>
CPU_XDP_PREQ#
CPU_XDP_PRDY#
RESET_OUT#_R
CPU_XDP_TCLK
+1.0V_PRIM_XDP
CFG0
CFG1
CFG2
CFG3
XDP_OBS0
XDP_OBS1
CFG4
CFG5
CFG6
CFG7
FIVR_EN_R
+3.3V_ALW_PCH
0.1U_0402_25V6
CC33@
4
XDP_PRSNT_PIN1
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
61
RC133
1.5K_0402_5%
1 2
CXDP@
PCH_SPI_DO_XDP
RESET_OUT#_R
12
CXDP@
1 2
RC121 0_0402_5%
1 2
RC122 0_0402_5%@
CONN@
JXDP1
JXT_FP270H-061G1AM
112
334
556
778
9910
111112
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
595960
61
GND62GND
2
4
6
8
10
12
14
14
16
16
18
18
20
20
22
22
24
24
26
26
28
28
30
30
32
32
34
34
36
36
38
38
40
40
42
42
44
44
46
46
48
48
50
50
52
52
54
54
56
56
58
58
60
63
CFG3
Place near JXDP1.48
XDP_DBRESET#
+1.0V_PRIM_XDP
CFG17
CFG16
CFG8
CFG9
CFG10
CFG11
CFG19
CFG18
CFG12
CFG13
CFG14
CFG15
ITP_PMODE
XDP_DBRESET#
TDO_XDP
TRST#_XDP
TDI_XDP
XDP_TMS
12
3
0.1U_0402_25V6
CXDP@
CC32
Place near JXDP1.41
CFG[0..19]<13>
CLK_ITPXDP_P_R <11>
CLK_ITPXDP_N_R <11>
ITP_PMODE <13>
XDP_DBRESET# <11>
PCH_SPI_DO2_XDP <8>
+3.3V_ALW_DSW
SIO_PWRBTN#
2
+3.3V_RUN
CC30
12
0.1U_0201_10V6K
TDO_XDP
TDI_XDP
XDP_TMS
TRST#_XDP
RUNPWROK<31>
1.5K_0402_5%
@
RC241
1 2
0.1U_0402_25V6
CC269
@
12
UC8
14
VCC
2
1A
1
1OE
5
2A
4
2OE
9
3A
10
3OE
12
4A
13
4OE
74CBTLV3126BQ_DHVQFN14_2P5X3
CPU_XDP_TMS
RC131 51_0402_5%
CPU_XDP_TDI
RC134 51_0402_5%
CPU_XDP_TDO
RC135 100_0402_5%
CPU_XDP_TRST#
RC136
@
CPU_XDP_TCLK
RC139 51_0402_5%
XDP_TMS
TDI_XDP
TDO_XDP
1 2
@
RC228 0_0402_5%
1 2
@
RC229 0_0402_5%
1 2
@
RC230 0_0402_5%
GND PAD
1 2
1 2
1 2
1 2
1 2
1B
2B
3B
4B
GND
1
3
6
8
11
7
15
51_0402_5%
PCH_JTAG_TMS <12>
PCH_JTAG_TDI <12>
PCH_JTAG_TDO <12>
CPU_XDP_TDO <12>
CPU_XDP_TDI <12>
CPU_XDP_TMS <12>
CPU_XDP_TRST# <12>
+1.0V_VCCSTG
B B
A A
Place near JXDP1.47
TDO_XDP H_VCCST_PWRGD_XD P CPU_XDP_TRST#
0.1U_0402_25V6
@ESD@
12
CC306
ESD request,Place near JXDP1 side. ES D request,Place near UC8 side.
0.1U_0402_25V6
@ESD@
12
CC307
0.1U_0402_25V6
@ESD@
12
CC308
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.
5
4
3
2
Title
Size Document N umber Re v
Size Document N umber Re v
Size Document N umber Re v
Date: Sheet o f
Date: Sheet o f
Date: Sheet o f
Compal Electronics, Inc.
CPU (9/14)
CPU (9/14)
CPU (9/14)
LA-F312P
LA-F312P
LA-F312P
14 58Wednesday, December 20, 2017
14 58Wednesday, December 20, 2017
14 58Wednesday, December 20, 2017
1
2.0
2.0
2.0
5
4
3
2
1
+VCC_CORE: 0.3~1.35V
D D
@
T122
PAD~D
@
T123
PAD~D
C C
+VCC_CORE +VCC_CORE
+VCC_CORE_G0
+VCC_CORE_G1
UC1L
A30
VCC_A30
A34
VCC_A34
A39
VCC_A39
A44
VCC_A44
AK33
VCC_AK33
AK35
VCC_AK35
AK37
VCC_AK37
AK38
VCC_AK38
AK40
VCC_AK40
AL33
VCC_AL33
AL37
VCC_AL37
AL40
VCC_AL40
AM32
VCC_AM32
AM33
VCC_AM33
AM35
VCC_AM35
AM37
VCC_AM37
AM38
VCC_AM38
G30
VCC_G30
K32
RSVD
AK32
RSVD
AB62
VCCOPC_AB62
P62
VCCOPC_P62
V62
VCCOPC_V62
H63
VCC_OPC_1P8_H63
G61
VCC_OPC_1P8_G61
AC63
VCCOPC_SENSE
AE63
VSSOPC_SENSE
AE62
VCCEOPIO
AG62
VCCEOPIO
AL63
VCCEOPIO_SENSE
AJ62
VSSEOPIO_SENSE
KBL-RU42_BGA1356
CPU@
KBL-R U4+2
CPU POWER 1 OF 4
Rev_0.1
VCC_G32
VCC_G33
VCC_G35
VCC_G37
VCC_G38
VCC_G40
VCC_G42
VCC_J30
VCC_J33
VCC_J37
VCC_J40
VCC_K33
VCC_K35
VCC_K37
VCC_K38
VCC_K40
VCC_K42
VCC_K43
VCC_SENSE
VSS_SENSE
VIDALERT#
VIDSCK
VIDSOUT
VCCSTG_G20
12 OF 20
G32
G33
G35
G37
G38
G40
G42
J30
J33
J37
J40
K33
K35
K37
K38
K40
K42
K43
E32
E33
B63
A63
D64
G20
VCCSENSE
VSSSENSE
H_CPU_SVIDALRT#
VIDSCLK
VIDSCLK < 46>
VIDSOUT
+1.0V_VCCSTG_R
+VCC_CORE
RC140
100_0402_1%
1 2
12
RC141
100_0402_1%
@
1 2
RC143 0_0603_5%
VCCSENSE <46>
VSSSENSE <46>
+1.0V_VCCSTG
VIDSCLK
RF Request
1 2
CC321@RF@ 33P_0402_50V8J
Place close CPU side
PSC(Primary side cap) : Place as close to the package as possible
BSC(Backside cap) : Place on secondary side, underneath the package
Component placement order:
Package edge > 0402 caps > 0805 caps > Bulk caps >Power source
B B
SVID ALERT
VIDALERT_N<46>
SVID DATA
A A
VIDSOUT<46>
+1.0V_VCCST
1 2
+1.0V_VCCST
1 2
56_0402_1%
RC152
100_0402_1%
RC157
CAD Note: Place the PU resistors close to CPU
RC204 close to CPU 300 - 1500mils
H_CPU_SVIDALRT#
12
RC153220_0402_5%
CAD Note: Place the PU resistors close to CPU
RC208close to CPU 300 - 1500mils
VIDSOUT
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.
5
4
3
2
Title
Size Document N umber Re v
Size Document N umber Re v
Size Document N umber Re v
Date: Sheet o f
Date: Sheet o f
Date: Sheet o f
Compal Electronics, Inc.
CPU (10/14)
CPU (10/14)
CPU (10/14)
LA-F312P
LA-F312P
LA-F312P
15 58Wednesday, December 20, 2017
15 58Wednesday, December 20, 2017
15 58Wednesday, December 20, 2017
1
2.0
2.0
2.0
5
4
3
2
1
+VCCGT: 0.3~1.35V
+VCCGTX : 0.3~1.35V
KBL-R 4+2 and KBL-U 2+2&2+3e opt i on ( pl ace on po wer page)
+VCC_GT_+VCC_CORE
KBL-R U4+2
CPU@
D D
+VCC_GT
+VCC_GT
C C
VCC_GT_SENSE<46>
VSS_GT_SENSE<46>
B B
1 2
@
RC437 0_0402_5%
+VCC_GT
RC161
100_0402_1%
1 2
VCC_GT_SENSE
VSS_GT_SENSE
12
RC163
100_0402_1%
UC1M
KBL-U / KBL-R U4+2
A48
VCCGT/VCCCORE_5
A53
VCCGT/VCCCORE_6
J43
VCCGT/VCCCORE_44
J45
VCCGT/VCCCORE_45
J46
VCCGT/VCCCORE_46
J48
VCCGT/VCCCORE_47
J50
VCCGT/VCCCORE_48
J52
VCCGT/VCCCORE_49
K48
VCCGT/VCCCORE_57
K50
VCCGT/VCCCORE_58
K52
VCCGT/RSVD_6
A58
VCCGT
A62
VCCGT
A66
VCCGT
AA63
VCCGT
AA64
VCCGT
AA66
VCCGT
AA67
VCCGT
AA69
VCCGT
AA70
VCCGT
AA71
VCCGT
AC64
VCCGT
AC65
VCCGT
AC66
VCCGT
AC67
VCCGT
AC68
VCCGT
AC69
VCCGT
AC70
VCCGT
AC71
VCCGT
J53
VCCGT
J55
VCCGT
J56
VCCGT
J58
VCCGT
J60
VCCGT
K53
VCCGT
K55
VCCGT
K56
VCCGT
K58
VCCGT
K60
VCCGT
L62
VCCGT
L63
VCCGT
L64
VCCGT
L65
VCCGT
L66
VCCGT
L67
VCCGT
L68
VCCGT
L69
VCCGT
L70
VCCGT
L71
VCCGT
M62
VCCGT
N63
VCCGT
N64
VCCGT
N66
VCCGT
N67
VCCGT
N69
VCCGT
J70
VCCGT_SENSE
J69
VSSGT_SENSE
KBL-RU42_BGA1356
CPU POWER 2 OF 4
KBL-U / KBL-R U4+2
VCCGTX_AK42/VCCCORE_12
VCCGTX_AK43/VCCCORE_13
VCCGTX_AK45/VCCCORE_14
VCCGTX_AK46/VCCCORE_15
VCCGTX_AK48/VCCCORE_16
VCCGTX_AK50/VCCCORE_17
VCCGTX_AL43/VCCCORE_21
VCCGTX_AL46/VCCCORE_22
VCCGTX_AL50/VCCCORE_23
VCCGTX_AM48/VCCCORE_29
VCCGTX_AM50/VCCCORE_30
VCCGTX_AM52/VCCCORE_31
VCCGTX_AK52/RSVD_5
Rev_0.1
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGTX_AK53
VCCGTX_AK55
VCCGTX_AK56
VCCGTX_AK58
VCCGTX_AK60
VCCGTX_AK70
VCCGTX_AL53
VCCGTX_AL56
VCCGTX_AL60
VCCGTX_AM53
VCCGTX_AM56
VCCGTX_AM58
VCCGTX_AU58
VCCGTX_AU63
VCCGTX_BB57
VCCGTX_BB66
VCCGTX_SENSE
VSSGTX_SENSE
13 OF 20
N70
N71
R63
R64
R65
R66
R67
R68
R69
R70
R71
T62
U65
U68
U71
W63
W64
W65
W66
W67
W68
W69
W70
W71
Y62
AK42
AK43
AK45
AK46
AK48
AK50
AL43
AL46
AL50
AM48
AM50
AM52
AK52
AK53
AK55
AK56
AK58
AK60
AK70
AL53
AL56
AL60
AM53
AM56
AM58
AU58
AU63
BB57
BB66
AK62
AL61
+VCC_GT
Follow KBL-R_U42_Processor_Line_BGA1356_Ballout_Rev1p0
KBL-R 4+2 and KBL-U 2+2&2+3e opt i on ( pl ace on po wer page)
+VCC_GT_+VCC_CORE
1 2
@
RC438 0_0402_5%
+VCC_GT
+VCC_GTUS
Reserve for soldering
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.
5
4
3
2
Title
Size Document N umber Re v
Size Document N umber Re v
Size Document N umber Re v
Date: Sheet o f
Date: Sheet o f
Date: Sheet o f
Compal Electronics, Inc.
CPU (11/14)
CPU (11/14)
CPU (11/14)
LA-F312P
LA-F312P
LA-F312P
16 58Wednesday, December 20, 2017
16 58Wednesday, December 20, 2017
16 58Wednesday, December 20, 2017
1
2.0
2.0
2.0
5
4
3
2
1
+5V_ALW
CZ104
@
1 2
4
O
@
1
2
CC253
1U_0402_6.3V6K
UZ34
1
2
+1.2V_MEM
1
2
CC250
1U_0402_6.3V6K
@
RZ119 0_0 402_5%
UZ26
1
VIN1
2
VIN2
7
VIN thermal
3
VBIAS
4
ON
TPS22961DNYR_WSON8
CC251
1U_0402_6.3V6K
SIO_SLP_S0#
SIO_SLP_S3#
AND
1 2
+VCCPLL_OC source
+1.2V_MEM+1.2V_MEM_CPUCLK
1 2
@
RC231 0_0402_5%
D D
PSC
1
1
2
1
CC177
CC176
2
2
10U_0402_6.3V6M
10U_0402_6.3V6M
PSC
22U_0603_6.3V6M
CC294
1
1
2
2
+1.0V_VCCST
C C
B B
PSC
1
2
CC195
1U_0402_6.3V6K
VDDQ: 8.45A
1
CC179
CC178
2
10U_0402_6.3V6M
10U_0402_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
CC296
CC295
1
2
+1.0V_VCCSTG
BSC
1
2
@
CC199
PSC
1
CC297
2
1U_0402_6.3V6K
+1.2V_MEM_CPUCLK
10U_0402_6.3V6M
+VCC_SFR_OC
1
2
CC288
+1.0V_VCCST source
+1.2V_MEM
1
2
CC322
1U_0402_6.3V6K
RF@
2.2P_0402_50V8C
RF Request
UC1N
AU23
VDDQ_AU23
AU28
VDDQ_AU28
AU35
VDDQ_AU35
AU42
VDDQ_AU42
BB23
VDDQ_BB23
BB32
VDDQ_BB32
BB41
VDDQ_BB41
BB47
VDDQ_BB47
BB51
VDDQ_BB51
AM40
VDDQC
A18
VCCST
A22
VCCSTG_A22
AL23
VCCPLL_OC
K20
VCCPLL_K20
K21
VCCPLL_K21
KBL-RU42_BGA1356
+1.0V_VCCST
1
2
12
CZ102 1U_0402_6.3V6K
VCCSTG_EN
AK28
AK30
AL30
AL42
AM28
AM30
AM42
AK23
AK25
G23
G25
G27
G28
J22
J23
J27
K23
K25
K27
K28
K30
AM23
AM22
H21
H20
1 2
+1.0VS_VCCIO
VCCIO_SENSE
VSSIO_SENSE
+VCC_SA
+1.0VS_VCCIO
12
RC166
100_0402_1%
VSA_SEN- <46>
VSA_SEN+ <46>
1 2
12
RC165
100_0402_1%
VCCIO_SENSE <44>
VSSIO_SENSE <44>
RC167
100_0402_1%
PCH_PRIM_EN<11,39,43,44,45>
SIO_SLP_S4#<11,17,31,42,45>
KBL-R U4+2
CPU@
CPU POWER 3 OF 4
Rev_0.1
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCIO_SENSE
VSSIO_SENSE
VSSSA_SENSE
VCCSA_SENSE
14 OF 20
+VCC_SA
RC168 100_0402_1%
PSC
U22@
CC202
@
1U_0402_6.3V6K
22U_0402_6.3V6M
CC202
1
CC341
2
U42@
22U_0603_6.3V6M
1 2
@
RZ120 0_0402_5%
+3.3V_ALW
5
0.1U_0402_10V7K
1
P
B
2
A
G
3
TC7SH08FU_SSOP5~D
+1.0VS_VCCIO
PSC
1
2
CC252
1U_0402_6.3V6K
+1.0V_VCCSTG source
+VCC_SFR_OC
6
VOUT
5
GND
S0
HIGH
HIGH
HIGH LOW LOW
S0Ix
LOW
HIGH
S3
LOW
LOW
1 2
CZ103 0.1U_0201_10V6K
+1.0V_VCCST+1.0V_VCC STG
1 2
RZ151 0_0603_5%
@
+1.0V_PRIM
12
CZ100 1U_0402_6.3V6K
SIO_SLP_S4#<11,17,31,42,45>
A A
5
+1.0V_PRIM
+5V_ALW
UZ21
1
VIN1
2
VIN2
7
VIN thermal
3
VBIAS
4
ON
TPS22961DNYR_WSON8
4.4mohm /6A
TR=12.5us@Vin=1.05V
VOUT
GND
+1.0V_VCCST_C
6
5
4
PJP1
12
PAD-OPEN1x1m
1 2
CZ101 0.1U_0201_10V6K
+1.0V_VCCST
SIO_SLP_S0#<11,33,44>
RUN_ON<31,32,39,44>
TC7SH08FU_SSOP5~D
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.
3
12
CZ105 1U_0402_6.3V6K
@
+5V_ALW
+3.3V_ALW
5
1
P
B
O
2
A
G
UZ35
3
1 2
RZ320 0_0402_5%
4
VCCSTG_EN
1
2
7
3
4
UZ19
VIN1
VIN2
VIN thermal
VBIAS
ON
TPS22961DNYR_WSON8
4.4mohm /6A
TR=12.5us@Vin=1.05V
VOUT
GND
2
12
PJP2
PAD-OPEN1x1m
+1.0V_VCCSTG_C
6
5
DELL CONFIDENTIAL/PROPRIETARY
pop option with UZ19
1 2
CZ106 0.1U_0201_10V6K
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document N umber Re v
Size Document N umber Re v
Size Document N umber Re v
Date: Sheet o f
Date: Sheet o f
Date: Sheet o f
Compal Electronics, Inc.
CPU (12/14)
CPU (12/14)
CPU (12/14)
LA-F312P
LA-F312P
LA-F312P
17 58Wednesday, December 20, 2017
17 58Wednesday, December 20, 2017
17 58Wednesday, December 20, 2017
1
2.0
2.0
2.0
5
+1.0V_PRIM
Imax : 2.57A
@
1 2
D D
C C
B B
RC299 0_0603_5%
@
1 2
RC300 0_0402_5%
@
1 2
RC301 0_0402_5%
@
1 2
RC302 0_0402_5%
@
1 2
RC303 0_0402_5%
+1.8V_PRIM
@
1 2
RC304 0_0402_5%
@
1 2
RC234 0_0402_5%
+3.3V_ALW_PCH
@
1 2
RC235 0_0402_5%
1 2
RC211 0_0402_5%
LPC@
+1.8V_PRIM
@ESPI@
1 2
RC212 0_0402_5%
@
1 2
RC305 0_0402_5%
@
1 2
RC306 0_0402_5%
@
1 2
RC307 0_0402_5%
@
1 2
RC308 0_0402_5%
+3.3V_ALW_PCH
1 2
LC1 BLM15GA750SN1D_2P
1
CC215
2
@
1U_0402_6.3V6K
+1.0V_MPHYAON
+1.0V_CLK6
+1.0V_DTS
+1.0V_CLK1
+1.0V_CLK3
+1.8V_PGPPF
+3.3V_1.8V_PGPPG
+3.3V_1.8V_PGPPA
+3.3V_PGPPB+3.3V_ALW_PCH
+3.3V_PGPPC
+3.3V_PGPPD
+3.3V_PGPPE
8/28 schematic review
close UC1.AF20 and <400mil
+3.3V_1.8V_ESPI
PJP4
1 2
PAD-OPEN1x1m
Must be +1.8V for eSPI I/F
+3.3V_VCCHDA
1
CC313
2
0.1U_0201_10V6K
close UC1.AJ19 and <400mil
A A
@
1 2
RC173 0_0402_5%
close UC1.N20 and <100mil
+1.0V_CLK4+1.0V_PRIM
1
CC226
2
@
47U_0805_6.3V6M
5
close UC1.AL1 and <120mil
+1.0V_MPHYAON
1
2
CC203
1U_0402_6.3V6K
+1.0V_MPHYGT
close UC1.N15 and CC210 <400mil, CC211 <120mil
1
1
CC210
2
2
@
47U_0805_6.3V6M
+1.0V_SRAM
1
CC217
2
@
1U_0402_6.3V6K
close UC1.K15, UC1.L15 and <100mil
@
1 2
RC169 0_0603_5%
1
2
CC281
@
0.1U_0201_10V6K
+1.0V_PRIM
1 2
LC2 BLM 15GA750SN1D_2P
1
CC225
2
@
47U_0805_6.3V6M
close UC1.V15 and <100mil
@
RC170 0_0402_5%
close UC1.K19 and <100mil
1
2
CC204
1U_0402_6.3V6K
CC211
1U_0402_6.3V6K
+1.0V_APLLEBB
1
2
1 2
4
+1.0V_PRIM_CORE+1.0VO_DSW
1
2
close UC1.AB19 and <400milclose UC1.K17 and <120mil
CC205
@
1U_0402_6.3V6K
close UC1.AF18 and <400mil
+1.0V_AMPHYPLL
+1.0V_APLL
+1.0V_PRIM
+3.3V_ALW_DSW
+3.3V_VCCHDA
+3.3V_SPI
+3.3V_ALW_PCH
+1.0V_PRIM
close UC1.N18 and <120mil
CC218
1U_0402_6.3V6K
+1.0V_AMPHYPLL+1.0V_MPHYGT
close UC1.K15 and <120mil
1
1
CC219
2
2
CC264
@
@
1U_0402_6.3V6K
47U_0805_6.3V6M
+1.0V_APLL
1
CC314
2
+1.0V_CLK2+1.0V_PRIM
1
CC220
2
@
47U_0805_6.3V6M
4
+1.0V_PRIM
1
CC206
2
@
0.1U_0201_10V6K
1U_0402_6.3V6K
No Support DS3
3
PCH PWR
UC1O
AB19
VCCPRIM_1P0
AB20
VCCPRIM_1P0
P18
VCCPRIM_1P0
AF18
VCCPRIM_CORE
AF19
VCCPRIM_CORE
V20
VCCPRIM_CORE
V21
VCCPRIM_CORE
AL1
DCPDSW_1P0
K17
VCCMPHYAON_1P0
L1
VCCMPHYAON_1P0
N15
VCCMPHYGT_1P0_N15
N16
VCCMPHYGT_1P0_N16
N17
VCCMPHYGT_1P0_N17
P15
VCCMPHYGT_1P0_P15
P16
VCCMPHYGT_1P0_P16
K15
VCCAMPHYPLL_1P0
L15
VCCAMPHYPLL_1P0
V15
VCCAPLL_1P0
AB17
VCCPRIM_1P0_AB17
Y18
VCCPRIM_1P0_Y18
AD17
VCCDSW_3P3_AD17
AD18
VCCDSW_3P3_AD18
AJ17
VCCDSW_3P3_AJ17
AJ19
VCCHDA
AJ16
VCCSPI
AF20
VCCSRAM_1P0
AF21
VCCSRAM_1P0
T19
VCCSRAM_1P0
T20
VCCSRAM_1P0
AJ21
VCCPRIM_3P3_AJ21
AK20
VCCPRIM_1P0_AK20
N18
VCCAPLLEBB_1P0
KBL-RU42_BGA1356
+3.3V_ALW_DSW
22U_0603_6.3V6M
@
CC279
1
2
Support DS3
'V' mean POP, 'X' mean DE-POP
KBL-R U4+2
CPU POWER 4 OF 4
VCCPRIM_3P3_V19
VCCPRIM_1P0_T1
VCCATS_1P8
VCCRTCPRIM_3P3
VCCRTC_AK19
VCCRTC_BB14
GPP_B0/CORE_VID0
GPP_B1/CORE_VID1
1 2
RC440 0_0402_5%
NDS3@
1 2
RC214 0_0402_5%
@
1 2
@DS3@
RC439 0_0402_5%
22U_0603_6.3V6M
@
CC280
1
2
RC439
RC440RE5 36RC215RC44 1RC442
V V V
X
V V V
X X
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.
3
X
Rev_0.1
VCCPGPPA
VCCPGPPB
VCCPGPPC
VCCPGPPD
VCCPGPPE
VCCPGPPF
VCCPGPPG
DCPRTC
VCCCLK1
VCCCLK2
VCCCLK3
VCCCLK4
VCCCLK5
VCCCLK6
15 OF 20
+3.3V_ALW_PCH
+3.3V_ALW_DSW_R
X
X
close UC1.AG15 and <120mil
Must be + 1.8V
AK15
AG15
Y16
Y15
T16
AF16
AD15
V19
T1
AA1
AK17
AK19
BB14
BB10
A14
K19
L21
N20
L19
A10
AN11
AN13
+3.3V_1.8V_PGPPA
+3.3V_PGPPD
+1.8V_PGPPF
+3.3V_1.8V_PGPPG
+1.0V_DTS
+3.3V_ALW_PCH
close UC1.AK19 and <120mil
+DCPRTC
close UC1.BB10 and <120mil
+1.0V_CLK1
+1.0V_CLK2
+1.0V_CLK3
+1.0V_CLK4
+1.0V_CLK5
CORE_VID0 <44>
CORE_VID1 <44>
Take care!!! Note1 on Page 19
+3.3V_ALW
QC7
DS3@
LP2301ALT1G_SOT23-3
123
D
S
499K_0402_1%
12
RC432
G
0.1U_0402_25V6K
49.9K_0402_1%
DS3@
12
L2N7002WT1G_SC-70-3
RC433
12
@
CC340
13
D
QC6
DS3@
2
G
S
2
close UC1.Y16 a nd <400mil
+3.3V_PGPPB
+3.3V_PGPPC
1
1
CC265
2
@
2
1U_0402_6.3V6K
close UC1.AA1 and <400mil
+RTC_CELL_PCH
1
2
CC214
0.1U_0201_10V6K
+1.0V_CLK6
1
CC216
2
@
close UC1.L19 and <100mil
DS3@
100K_0402_5%
RC431
DS3@
1 2
VCCDSW_EN_GPIO <11>
2
+3.3V_PGPPE
close UC1.T16 a nd <400mil
1
CC207
@
1U_0402_6.3V6K
1
2
CC270
CC208
2
@
1U_0402_6.3V6K
1
2
CC213
1U_0402_6.3V6K
0.1U_0201_10V6K
close UC1.A10 and <120mil
1U_0402_6.3V6K
@
1 2
RC171 0_0402_5%
+1.0V_MPHYGT source
561280_561280_KBL_UY_PDG_Rev0p9 :
MPHY has defeature
DELL CONFIDENTIAL/PROPRIETARY
1
+1.0V_MPHYGT
+1.0V_SRAM
+1.0V_APLLEBB
close UC1.AD15 and <400mil
1
CC326
2
1U_0402_6.3V6K
+1.8V_PRIM
1
2
@
RC309 0_0603_5%
@
RC310 0_0603_5%
+3.3V_ALW_PCH
1
CC209
2
@
1U_0402_6.3V6K
close UC1.V19 and <120mil
CC212
1U_0402_6.3V6K
1 2
1 2
+3.3V_1.8V_PGPPG
RF Request
+1.0V_APLL +3.3V_VCCHDA +1.0V_APLLEBB
1
1
2
2
+1.0V_CLK5+1.0V_PRIM
1
CC221
2
@
47U_0805_6.3V6M
PJP3
@
1 2
PAD-OPEN1x3m
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document N umber Re v
Size Document N umber Re v
Size Document N umber Re v
Date: Sheet o f
Date: Sheet o f
Date: Sheet o f
Compal Electronics, Inc.
CPU (13/14)
CPU (13/14)
CPU (13/14)
LA-F312P
LA-F312P
LA-F312P
CC323
RF@
2.2P_0402_50V8C
+3.3V_ALW_PCH
1
CC223
2
0.1U_0201_10V6K
+1.0V_MPHYGT+1.0V_PRIM
1
CC324
RF@
close UC1.AK17 and <120mil
1
2
1
2
CC325
2.2P_0402_50V8C
CC224
RF@
2.2P_0402_50V8C
1U_0402_6.3V6K
18 58Wednesday, December 20, 2017
18 58Wednesday, December 20, 2017
18 58Wednesday, December 20, 2017
2.0
2.0
2.0
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