Compal LA-F312P Schematic

A

COMPAL CONFIDENTIAL

B

C

D

E

1 1

MODEL NAME : DAZ20 (SBMLK 12) / DAZ30 (SBMLK 13)
PCB NO : LA-F312P

Steamboat MLK 12"/13" NonAR

BOM P/N : 431A8W31L0X (12_NonAR)

Kabylake-U U22 & Kabylake-R U42

2017-12-29

REV : 2.0 (A01)

@ : Nopop Component

EMI@ : EMI Component

2 2

3 3

@EMI@ : EMI Nopop Component

ESD@ : ESDComponent

@ESD@ : ESD Nopop Component

RF@ : RF Component

@RF@ : RF Nopop Component

CXDP@ : XDP Component

CONN@ : Connector Component

ESPI@ : ESPI interface Component

LPC@ : External ESPI Component (SHD)

U42@ : KBL-R U42 Component
U22@ : KBL-R U22 Component

MB PCB

Part Number

DA8001CG010

Description

PCB 263 LA-F312P REV0 MB NAR 1

SB12@ : For SB12 System ID
SB13@ : For SB13 System ID

Layout Dell logo

DS3@ : Deep sleep Component

NDS3@ : Non Deep sleep Component

4 4

COPYRIGHT 2017

ALL RIGHT RESERVED
REV:A01
PWB: 3DRR6

A

Power CKT : 0919
GPIO map : 0821

B

546@ : TI TUSB546 Component

8743@ : PARADE PS8743 Component

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOU T THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRIT TEN CONSENT.

C

D

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date : Sheet o f

Date : Sheet o f

Date : Sheet o f

Compal Electronics, Inc.

Cover Sheet

Cover Sheet

Cover Sheet

LA-F312P

LA-F312P

LA-F312P

1 58Friday, December 29, 2017

1 58Friday, December 29, 2017

1 58Friday, December 29, 2017

E

2.0

2.0

2.0

A

B

C

D

E

Steamboat MLK 12&13 w/o AR Block Diagram

Memory BUS (DDR4)

2133 MHz on KBL-U

USB

2400 MHz on KBL-R
up to 16GB

USB2.0[9]

USB3.0[6]

HDA Codec
ALC3246

1 1

EDP CONN

HDMI 1.4
CONN

P26

eDP 14": Lane x 4; 12" :Lane x 2

HDMI

P21

To NonAR type C

P22

DDI[1]

DDI[2]

INTEL

KABYLAKE_U MCP
U22

KABYLAKE_R MCP
U42

2 2

PCIE[1]

Card reader
RTS5242

P28

SD4.0

P28

3 3

PCIE[4]

Intel Jacksonville
WGI219LM

Transformer

RJ45

P27

P27

P27

WWAN/LTE/Cache

SATA[1]

M.2,3042 Key B

USB3.0[2]

P29

USB2.0[4]

M.2,3030 Key A

WLAN+BT

PCIE[3]

P29

USB2.0[7]

ESPI

SMSC KBC
MEC5105

SPI

P31-3 2

PAGE 6~19

HD Audio I/F

SATA[2]/PCIE [9][10][11] [12]

W25Q128JVSIQ

128M 4K sector

P8

W25Q128JVSIQ

128M 4K sector

TPM1.2/2.0 Nuvoton
NPCT750JAAYX

KB/TP CONN

FAN CONN

P8

reserve

P37

P32

P33

Steamboat MLK 12&13 only support one DIMM

Reverse Type

DDR4-SO-DIMM X1

BANK 0, 1, 2, 3

P20

SLGC55544CVTR
USB POWER SHARE

P35

INT.Speaker

Universal Jack

P30

Dig. MIC

USB2.0[8]

USB2.0[5]

USB2.0[9]_PS

USB3.0[6]

USB2.0[2]

USB3.0[3]

P30

P30

P26

LCD Touch

Camera

USB3.0 Conn
PS(Ext Port 1)
Right

USB3.0 Conn
(Ext Port 2)
Lef t Fr ont

Trough eDP Cable

M.2 2280

SSD Conn

P34

P26

P26

Trough eDP Cable

P35

P36

only 14"

LID SWITCH

LED board

USH CONN

P33

CPU&PCH XDP Port

Non-AR Type C

DP1.2 4 lanes

TX/RX

USB 3.0 + AM
Type C CONN.

4 4

USB2.0

CC

Vbus

HS Redriver Switch
TUSB546

P22

GPIO

PD Solut i on
TPS65982DC

P23-2 4P25

DDI[2]

USB3.0[1]

SMBUS

USB2.0[1]

Smart Card

5V VR

Charger

A

B

TDA8034HN

RFID/NFC

Fingerprint
CONN

C

USH board

USB2.0[10]

P33

D

USH TPM1.2
BCM58102

SPI

SPI

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER P ROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

DELL CONFIDENTIAL/PROPRIETARY

Title

Title

Title

Size

Document Number Re v

Size

Document Number Re v

Size

Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

AUTOMATIC POWER
SWITCH(APS)

DC/DC Interface

POWER ON/OFF

SW & LED

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Block diagram

Block diagram

Block diagram

LA-F312P

LA-F312P

LA-F312P

E

P14

P11

P39

P38

2.0

2.0

2 58Wednesday, December 20, 2017

2 58Wednesday, December 20, 2017

2 58Wednesday, December 20, 2017

2.0

5

POWER STATES

Signal

State

S0 (Full ON) / M0

S3 (Suspend to RAM) / M3 LOW

D D

S4 (Suspend to DISK) / M3

S5 (SOFT OFF) / M3

S3 (Suspend to RAM) / M-OFF

S4 (Suspend to DISK) / M-OFF

S5 (SOFT OFF) / M- OFF

SLP
S3#

HIGH

LOW

LOW

LOW LOW LOW

LOW LOW LOW LOW

SLP

SLP

S5#

S4#

HIGH HIGH

HIGH HIGH

HIGH HIGH

LOW

LOW

LOW

HIGH HIGH

HIGH

ALW AYS

SLP

PLANE

A#

HIGH

ON

HIGH

ON ON ON

ON ON

HIGH

ON ON

ON ON

LOW

ON

ON

PM TABLE

+5V_ALW

+3.3V_ALW

+3.3V_ALW_D SW

power

C C

State

S0

S3

S5 S4/AC

S5 S4/AC doesn't exist

plane

+3.3V_ALW_PCH +1.2V_MEM

+RTC_CELL

+1.8V_PRIM

+1.0V_PRIM

+1.0V_PRIM_CORE

+5V_ALW 2

+3.3V_ALW 2

+3.3V_RTC_LDO

+1.0V_MPHYGT

ON

ON

ON

+3.3V_CV2

+2.5V_MEM

+1.0V_VCCST

+5V_RUN

+3.3V_RUN

+0.6V_DDR_VTT

+1.8V_RUN

+VCC_CORE

+VCC_GT

+VCC_SA

+1.0VS_VCCIO

ON ON

ON

OFF

OFFOFF

4

M
PLANE

ON

OFF OFF OFF

OFF OFF OFF OFF

OFF OFF OFF OFF

OFF

OFF

OFF

RUN

SUS

PLA NE

PLANE

ON ON ON

OFF

OFF

OFF

OFF

OFFLOW

CLOCKS

OFF

OFF

OFF

USB3.0

USB3.0-1

USB3.0-2

USB3.0-3

USB3.0-4

USB3.0-5

USB3.0-6

SSIC

SSIC

3

PCIE

PCIE-1

PCIE-2

PCIE-3

PCIE-4

PCIE-5

PCIE-6

PCIE-7

PCIE-8

PCIE-9

PCIE-10

PCIE-11

PCIE-12

SATA

JUSB3-->Lef t Rear ( SB14 onl y)

SATA-0

SATA-1

SATA-1*

M.2 3042(SATA Cache)

M.2 2280 SSD
(PCIex4 or SATA)

SATA-2

12" not support JUSB3

Typce-C(Non AR)

M.2 3042(LTE)

JUSB2-->Lef t Fr ont

Card Reader (PCIE)

JUSB1-->Right

M.2 3030(WLAN)

LOM

NA

NA

NA

2

1

NonAR config

USB PORT#DESTINATION

1

2

3

4

5

6

7

8

9

10

DESTINATION

Typce-C(Non AR)

JUSB2-->Lef t Fr ont

JUSB3-->Lef t Rear ( SB14 onl y)

M2 3042(WWAN)

Camera

NA

M.2 3030(BT)

Touch Screen

JUSB1-->Right

USH

B B

A A

AR use 1086PP (10L)
Non AR use 1080PP (8L)

5

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EX PRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY TH IRD
PARTY WITHOUT DELL'S EX PRESS WRITTEN CONSENT.

4

3

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date : Sheet of

Date : Sheet of

Date : Sheet of

Compal Electronics, Inc.

Port assignment

Port assignment

Port assignment

LA-F312P

LA-F312P

LA-F312P

1

3 58Wednesday, December 20, 2017

3 58Wednesday, December 20, 2017

3 58Wednesday, December 20, 2017

2.0

2.0

2.0

5

Barrel
ADAPT ER

D D

CHARGER
ISL9538

(PU901)

Type-C
ADAPTER

+PWR_SRC

SY8210A
(PU200)

SY8286R
(PU301)

SYV828C

(PU102)

4

SIO_SLP_S4#

0.6V_DDR_ VTT_ON

PCH_P RIM_EN
(SIO_SLP_SU S#)

ALWO N

+1.2V_MEM

+0.6V_DDR_VTT

+1.0V_PRIM

+5V_ALW

+5V_ALW2

TPS22961

(UZ26)

3

VCCSTG_ EN

TPS62134C

(PU401)

TPS62134D

(PU402)

EM5209

(UZ4)

+VCC_SFR_OC

RUN_ ON

PCH_P RIM_EN
(SIO_SLP_SU S#)

RUN_ ON

TPS22961

(UZ19)

TPS22961

(UZ21)

+1.0VS_VCCIO

+1.0V_PRIM_CORE

+5V_RUN

2

1

CPU PWR

PCH PWR

GT3 PWR

AUD_PW R_EN

Peripheral Device PWR

TYPE-C Power

+5V_RUN_AUDIO

RUN_ ON
SIO_SLP_S0#

SIO_SLP_S4#

EM5209

(@UZ5)

+1.0V_VCCSTG

+1.0V_VCCST

BATTERY

SY8288B

C C

(PU100)

ALWO N

+3.3V_RTC_LDO

+3.3V_ALW2

SLGC55544C

(UI3)

SY6288

(UI1)

USB_PW R_SHR_ VBUS_EN

USB_PW R_EN1#

+5V_USB_CHG_PWR

+USB_EX2_PWR

+3.3V_ALW

RT8097A

CSD97396Q

ISL95808

(PU614)

IMVP_V R_ON

B B

CSD97396Q

(PU612)

IMVP_V R_ON

+VCC_GT+VCC_SA

(PU610)
CSD9 7396Q
(PU613)

U42@

IMVP_V R_ON

+VCC_CORE

AO6405

(QV1)

EN_IN VPWR

+BL_PWR_SRC

TYPE-C

+5V_ALW

+PP_HV(5V~20V)

TPS65982D

(UT5)

+TBTA_Vbus_1(5V~20V)

(PU501)

EM5209

(UZ2)

EM5209

(UZ3)

EM5209

(UZ4)

G524B1T11U
(UV24)

PCH_P RIM_EN
(SIO_SLP_SU S#)

SIO_SLP_L AN#

AUX_EN_WOW L

@SIO_SLP_ WLAN#

PCH_P RIM_EN
(SIO_SLP_SU S#)

@PCH_ALW _ON

RUN_ ON

3.3V_W WAN_EN

ENVCC _PCH

+1.8V_PRIM

+3.3V_LAN

+3.3V_W LAN

+3.3V_ALW_PCH

+3.3V_RUN

+3.3V_W WAN

+LCDV DD

AOZ1336

(UZ8)

LP2301

(QV8)

LP2301 A

(QZ1)

EM5209

(@UZ5)

RUN_ ON

3.3V_TS_EN

3.3V_CAM_ EN#

AUD_PW R_EN

+1.8V_RUN

+3.3V_TSP

+3.3V_CAM

+3.3V_RUN_AUDIO

A A

AP2204

(UT8)

5

+5V_ALW

+5V_TBT_VBUS

AP2112 K

(UT7)

4

+3.3V_VDD_PIC

AP7361C

(PU503)

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EX PRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY TH IRD
PARTY WITHOUT DELL'S EX PRESS WRITTEN CONSENT.

3

SIO_SLP_S4#

+2.5V_MEM

for D DR4

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date : Sheet of

Date : Sheet of

Date : Sheet of

Compal Electronics, Inc.

Power rails

Power rails

Power rails

LA-F312P

LA-F312P

LA-F312P

1

4 58Wednesday, December 20, 2017

4 58Wednesday, December 20, 2017

4 58Wednesday, December 20, 2017

2.0

2.0

2.0

5

AW44

BB43

KBL-R

D D

KBL-U

AW45 AW42

03

03

AY44

BB39

SML1_SMBD ATA

SML1_SMBCLK

D8E11

00

00

UPD2_SMBCLK

D7

UPD2_SMBDAT

E7

MEM_SMBC LK

MEM_SMBDATA

SML0_SMBCLK

SML0_SMBD ATA

1K

1K

4

+3.3 V_ALW_ PCH

2.2K

2.2K

+3.3 V_ALW

499

499

1K

1K

+3.3 V_ALW_ PCH

+3.3 V_ALW_ PCH

3

DMN65D8LDW-7

DMN65D8LDW-7

28

31

LOM

2

1

2.2K

2.2K

+3.3 V_RUN

202

200

DIMMA

53

51

XDP

@2.2K

@2.2K

B3

E5

C12

E10

C3

B4

USH_SMBCLK

USH_SMBDAT

UPD1_SMBCLK

UPD1_SMBDAT

2.2K

2.2K

C C

01

01

02

02

KBC

04

04

+3.3 V_ALW

+3.3 V_ALW

DMN66D0LDW-7

DMN66D0LDW-7

2.2K

2.2K

2.2K

2.2K

+3.3 V_CV2

M9

USH

L9

USH/B

+3.3 V_TBTA_FLA SH

B5

PD

A5

MEC 5105

F7

05

B6

05

A12

06

N10

B B

A A

06

07

07

08 C5

08

09

09

1010M3

M4

M7

C8

F6

E9

N2

PBAT_CHARGER_SMBCLK

PBAT__CHARGER_SMBDAT

2.2K

2.2K

+3.3 V_ALW

100 ohm

100 ohm

7

6

Charger

BATTERY

CONN

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EX PRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY TH IRD
PARTY WITHOUT DELL'S EX PRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date : Sheet of

Date : Sheet of

Date : Sheet of

Compal Electronics, Inc.

Port assignment

Port assignment

Port assignment

LA-F312P

LA-F312P

LA-F312P

1

5 58Wednesday, December 20, 2017

5 58Wednesday, December 20, 2017

5 58Wednesday, December 20, 2017

2.0

2.0

2.0

5

4

3

2

1

+3.3V_RUN

CPU_DP1_CTRL_CLK

RC175 2.2K_0402_5%

RC178 2.2K_0402_5%

D D

RC176 2.2K_0402_5%

RC177 2.2K_0402_5%

12

CPU_DP1_CTRL_DATA

12

CPU_DP2_CTRL_CLK

12

CPU_DP2_CTRL_DATA

12

AR (AR)/
HDMI(Non AR)

Dockport (Non AR)

+1.0VS_VCCIO

C C

B B

CPU_DP1_N0<21>
CPU_DP1_P0<21>
CPU_DP1_N1<21>
CPU_DP1_P1<21>
CPU_DP1_N2<21>
CPU_DP1_P2<21>
CPU_DP1_N3<21>
CPU_DP1_P3<21>

CPU_DP2_N0<22>
CPU_DP2_P0<22>
CPU_DP2_N1<22>
CPU_DP2_P1<22>
CPU_DP2_N2<22>
CPU_DP2_P2<22>
CPU_DP2_N3<22>
CPU_DP2_P3<22>

12

CPU_DP1_CTRL_CLK
CPU_DP1_CTRL_DATA

CPU_DP2_CTRL_CLK
CPU_DP2_CTRL_DATA

GPP_E23

EDP_COMP

CPU_DP1_CTRL_CLK<21>

CPU_DP1_CTRL_DATA<21>

@

T120

PAD~D

RC2 24.9_0402_1%

COMPENSATION PU FOR eDP

CAD Note:Trace width=20 mils , Spacing=25mil,
Max length=100 mils.

CPU@

UC1A

E55

DDI1_TXN[0]

F55

DDI1_TXP[0]

E58

DDI1_TXN[1]

F58

DDI1_TXP[1]

F53

DDI1_TXN[2]

G53

DDI1_TXP[2]

F56

DDI1_TXN[3]

G56

DDI1_TXP[3]

C50

DDI2_TXN[0]

D50

DDI2_TXP[0]

C52

DDI2_TXN[1]

D52

DDI2_TXP[1]

A50

DDI2_TXN[2]

B50

DDI2_TXP[2]

D51

DDI2_TXN[3]

C51

DDI2_TXP[3]

L13

GPP_E18/DDPB_CTRLCLK

L12

GPP_E19/DDPB_CTRLDATA

N7

GPP_E20/DDPC_CTRLCLK

N8

GPP_E21/DDPC_CTRLDATA

N11

GPP_E22

N12

GPP_E23

E52

EDP_RCOMP

KBL-RU42_BGA1356

CPU@

UC1I

CSI-2

A36

CSI2_DN0

B36

CSI2_DP0

C38

CSI2_DN1

D38

CSI2_DP1

C36

CSI2_DN2

D36

CSI2_DP2

A38

CSI2_DN3

B38

CSI2_DP3

C31

CSI2_DN4

D31

CSI2_DP4

C33

CSI2_DN5

D33

CSI2_DP5

A31

CSI2_DN6

B31

CSI2_DP6

A33

CSI2_DN7

B33

CSI2_DP7

A29

CSI2_DN8

B29

CSI2_DP8

C28

CSI2_DN9

D28

CSI2_DP9

A27

CSI2_DN10

B27

CSI2_DP10

C27

CSI2_DN11

D27

CSI2_DP11

KBL-RU42_BGA1356

KBL-R U4+2

DDI

DISPLAY SIDEBANDS

KBL-R U4+2

EDP

Rev_0.1

CSI2_CLKN0
CSI2_CLKP0
CSI2_CLKN1
CSI2_CLKP1
CSI2_CLKN2
CSI2_CLKP2
CSI2_CLKN3
CSI2_CLKP3

CSI2_COMP

GPP_D4/FLASHTRIG

EMMC

GPP_F13/EMMC_DATA0
GPP_F14/EMMC_DATA1
GPP_F15/EMMC_DATA2
GPP_F16/EMMC_DATA3
GPP_F17/EMMC_DATA4
GPP_F18/EMMC_DATA5
GPP_F19/EMMC_DATA6
GPP_F20/EMMC_DATA7

GPP_F21/EMMC_RCLK

GPP_F22/EMMC_CLK

GPP_F12/EMMC_CMD

EMMC_RCOMP

9 OF 20

Rev_0.1

EDP_TXN[0]
EDP_TXP[0]
EDP_TXN[1]
EDP_TXP[1]
EDP_TXN[2]
EDP_TXP[2]
EDP_TXN[3]
EDP_TXP[3]

EDP_AUXN
EDP_AUXP

EDP_DISP_UTIL

DDI1_AUXN
DDI1_AUXP
DDI2_AUXN
DDI2_AUXP

RSVD

GPP_E13/DDPB_HPD0
GPP_E14/DDPC_HPD1
GPP_E15/DDPD_HPD2
GPP_E16/DDPE_HPD3

RSVD

GPP_E17/EDP_HPD

EDP_BKLTEN

EDP_BKLTCTL

EDP_VDDEN

1 OF 20

C37
D37
C32
D32
C29
D29
B26
A26

CSI2_COMP

E13
B7

AP2
AP1
AP3
AN3
AN1
AN2
AM4
AM1

AM2
AM3
AP4

EMMC_RCOMP

AT1

C47
C46
D46
C45
A45
B45
A47
B47

E45
F45

B52

G50
F50
E48
F48
G46
F46

L9
L7
L6
N9
L10

R12
R11
U13

RC3

TBT_FORCE_PWR

1 2

RC4 200_0402_1%

CPU_DP1_AUXN
CPU_DP1_AUXP

CPU_DP3_AUXN
CPU_DP3_AUXP

1 2

EDP_TXN0 <26>
EDP_TXP0 <26>
EDP_TXN1 <26>
EDP_TXP1 <26>

EDP_AUXN <26>
EDP_AUXP <26>

PAD~D
PAD~D

CPU_DP2_AUXN <22,23>

CPU_DP2_AUXP <22,23>

PAD~D
PAD~D

CPU_DP1_HPD <21>
CPU_DP2_HPD <22,23>

EDP_HPD <26>

PANEL_BKLEN <26>
EDP_BIA_PWM <26>
ENVDD_PCH <26>

100_0402_1%

T19 @PAD~D

+3.3V_RUN

@

T281

@

T282

@

T1

@

T2

CPU_DP2_AUXN

CPU_DP2_AUXP

CPU_DP2_HPD

EDP_HPD

1 2

@

RC448 100K_0402_5%

1 2

@

RC447 100K_0402_5%

1 2

RC446 100K_0402_5%

1 2

RC1 100K_0402_5%

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.

5

4

3

2

Title

Size Document N umber Re v

Size Document N umber Re v

Size Document N umber Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CPU (1/14)

CPU (1/14)

CPU (1/14)

LA-F312P

LA-F312P

LA-F312P

6 58Wednesday, December 20, 2017

6 58Wednesday, December 20, 2017

6 58Wednesday, December 20, 2017

1

2.0

2.0

2.0

5

4

3

2

1

For DDR4

DDR_A_DQS#[0..7]<20>

AU53
AT53
AU55
AT55

BA56
BB56
AW56
AY56

AU45
AU43
AT45
AT43

BA51
BB54
BA52
AY52
AW52
AY55
AW54
BA54
BA55
AY54
AU46
AU48
AT46
AU50
AU52
AY51
AT48
AT50
BB50
AY50

BA50
BB52
AM70
AM69
AT69
AT70

BA64
AY64
AY60
BA60
BA38
AY38
AY34
BA34
BA30
AY30
AY26
BA26

AW50
AT52

AY67
AY68
BA67

AW67

DDR_A_D[0..63]<20>

DDR_A_DQS[0..7]<20>

DDR_A_MA[0..16]<20>

DDR_A_CLK#0
DDR_A_CLK0
DDR_A_CLK#1
DDR_A_CLK1

DDR_A_CKE0
DDR_A_CKE1
DDR_A_CKE2
DDR_A_CKE3

DDR_A_CS#0
DDR_A_CS#1
DDR_A_ODT0
DDR_A_ODT1

DDR_A_MA5
DDR_A_MA9
DDR_A_MA6
DDR_A_MA8
DDR_A_MA7
DDR_A_BG0
DDR_A_MA12
DDR_A_MA11
DDR_A_ACT#
DDR_A_BG1
DDR_A_MA13
DDR_A_MA15
DDR_A_MA14
DDR_A_MA16
DDR_A_BA0
DDR_A_MA2
DDR_A_BA1
DDR_A_MA10
DDR_A_MA1
DDR_A_MA0

DDR_A_MA3
DDR_A_MA4
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_DQS#1
DDR_A_DQS1

DDR_A_DQS#2
DDR_A_DQS2
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_DQS#7
DDR_A_DQS7

DDR_A_ALERT#
DDR_A_PARITY

+DDR_VREF_A_DQ
+DDR_VREF_B_DQ

DDR_A_CLK#0 <20>
DDR_A_CLK0 <20>
DDR_A_CLK#1 <20>
DDR_A_CLK1 <20>

DDR_A_CKE0 <20>
DDR_A_CKE1 <20>

@

T3

PAD~D

@

T4

PAD~D

DDR_A_CS#0 <20>
DDR_A_CS#1 <20>
DDR_A_ODT0 <20>
DDR_A_ODT1 <20>

DDR_A_BG0 <20>

DDR_A_ACT# <20>
DDR_A_BG1 <20>

DDR_A_BA0 <20>

DDR_A_BA1 <20>

DDR0_PAR,DDR0_ALERT# for DDR4

DDR_A_ALERT# <20 >
DDR_A_PARITY <20>

+DDR_VREF_CA

@

T132

PAD~D

@

T226

PAD~D

DDR_VTT_CTRL <20>

UC1C

Interleave / Non-Interleaved

AF65

DDR1_DQ[0]/DDR0_DQ[16]

AF64

DDR1_DQ[1]/DDR0_DQ[17]

AK65

DDR1_DQ[2]/DDR0_DQ[18]

AK64

DDR1_DQ[3]/DDR0_DQ[19]

AF66

DDR1_DQ[4]/DDR0_DQ[20]

AF67

DDR1_DQ[5]/DDR0_DQ[21]

AK67

DDR1_DQ[6]/DDR0_DQ[22]

AK66

DDR1_DQ[7]/DDR0_DQ[23]

AF70

DDR1_DQ[8]/DDR0_DQ[24]

AF68

DDR1_DQ[9]/DDR0_DQ[25]

AH71

DDR1_DQ[10]/DDR0_DQ[26]

AH68

DDR1_DQ[11]/DDR0_DQ[27]

AF71

DDR1_DQ[12]/DDR0_DQ[28]

AF69

DDR1_DQ[13]/DDR0_DQ[29]

AH70

DDR1_DQ[14]/DDR0_DQ[30]

AH69

DDR1_DQ[15]/DDR0_DQ[31]

AT66

DDR1_DQ[16]/DDR0_DQ[48]

AU66

DDR1_DQ[17]/DDR0_DQ[49]

AP65

DDR1_DQ[18]/DDR0_DQ[50]

AN65

DDR1_DQ[19]/DDR0_DQ[51]

AN66

DDR1_DQ[20]/DDR0_DQ[52]

AP66

DDR1_DQ[21]/DDR0_DQ[53]

AT65

DDR1_DQ[22]/DDR0_DQ[54]

AU65

DDR1_DQ[23]/DDR0_DQ[55]

AT61

DDR1_DQ[24]/DDR0_DQ[56]

AU61

DDR1_DQ[25]/DDR0_DQ[57]

AP60

DDR1_DQ[26]/DDR0_DQ[58]

AN60

DDR1_DQ[27]/DDR0_DQ[59]

AN61

DDR1_DQ[28]/DDR0_DQ[60]

AP61

DDR1_DQ[29]/DDR0_DQ[61]

AT60

DDR1_DQ[30]/DDR0_DQ[62]

AU60

DDR1_DQ[31]/DDR0_DQ[63]

AU40

DDR1_DQ[32]/DDR1_DQ[16]

AT40

DDR1_DQ[33]/DDR1_DQ[17]

AT37

DDR1_DQ[34]/DDR1_DQ[18]

AU37

DDR1_DQ[35]/DDR1_DQ[19]

AR40

DDR1_DQ[36]/DDR1_DQ[20]

AP40

DDR1_DQ[37]/DDR1_DQ[21]

AP37

DDR1_DQ[38]/DDR1_DQ[22]

AR37

DDR1_DQ[39]/DDR1_DQ[23]

AT33

DDR1_DQ[40]/DDR1_DQ[24]

AU33

DDR1_DQ[41]/DDR1_DQ[25]

AU30

DDR1_DQ[42]/DDR1_DQ[26]

AT30

DDR1_DQ[43]/DDR1_DQ[27]

AR33

DDR1_DQ[44]/DDR1_DQ[28]

AP33

DDR1_DQ[45]/DDR1_DQ[29]

AR30

DDR1_DQ[46]/DDR1_DQ[30]

AP30

DDR1_DQ[47]/DDR1_DQ[31]

AU27

DDR1_DQ[48]

AT27

DDR1_DQ[49]

AT25

DDR1_DQ[50]

AU25

DDR1_DQ[51]

AP27

DDR1_DQ[52]

AN27

DDR1_DQ[53]

AN25

DDR1_DQ[54]

AP25

DDR1_DQ[55]

AT22

DDR1_DQ[56]

AU22

DDR1_DQ[57]

AU21

DDR1_DQ[58]

AT21

DDR1_DQ[59]

AN22

DDR1_DQ[60]

AP22

DDR1_DQ[61]

AP21

DDR1_DQ[62]

AN21

DDR1_DQ[63]

KBL-RU42_BGA1356

CPU@

KBL-R U4+2

DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5]
DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9]
DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6]
DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8]
DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]

DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]
DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12]
DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]

DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT#

DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]

DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]

DDR1_CAS#/DDR1_CAB[1]/DDR1_M A[15]

DDR1_WE#/DDR1_CA B[2]/DDR1_MA[14]

DDR1_RAS#/DDR1_CAB[3]/DDR1_M A[16]

DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]

DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]

DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]
DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]

DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1]
DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]

DDR CH - B

3 OF 20

DDR3L / LPDDR3 / DDR4

Interleave / Non-Interleaved

DDR1_DQSN[0]/DDR0_DQSN[2]
DDR1_DQSP[0]/DDR0_DQSP[2]
DDR1_DQSN[1]/DDR0_DQSN[3]
DDR1_DQSP[1]/DDR0_DQSP[3]
DDR1_DQSN[2]/DDR0_DQSN[6]
DDR1_DQSP[2]/DDR0_DQSP[6]
DDR1_DQSN[3]/DDR0_DQSN[7]
DDR1_DQSP[3]/DDR0_DQSP[7]
DDR1_DQSN[4]/DDR1_DQSN[2]
DDR1_DQSP[4]/DDR1_DQSP[2]
DDR1_DQSN[5]/DDR1_DQSN[3]
DDR1_DQSP[5]/DDR1_DQSP[3]

DRAM_RESET#
DDR_RCOMP[0]
DDR_RCOMP[1]
DDR_RCOMP[2]

Rev_0.1

DDR1_CKN[0]
DDR1_CKN[1]
DDR1_CKP[0]
DDR1_CKP[1]

DDR1_CKE[0]
DDR1_CKE[1]
DDR1_CKE[2]
DDR1_CKE[3]

DDR1_CS#[0]

DDR1_CS#[1]
DDR1_ODT[0]
DDR1_ODT[1]

DDR1_MA[3]
DDR1_MA[4]

DDR1_DQSN[6]
DDR1_DQSP[6]
DDR1_DQSN[7]
DDR1_DQSP[7]
DDR1_ALERT#

DDR1_PAR

AN45
AN46
AP45
AP46

AN56
AP55
AN55
AP53

BB42
AY42
BA42
AW42

AY48
AP50
BA48
BB48
AP48
AP52
AN50
AN48
AN53
AN52
BA43
AY43
AY44
AW44
BB44
AY47
BA44
AW46
AY46
BA46

BB46
BA47

AH66
AH65
AG69
AG70
AR66
AR65
AR61
AR60
AT38
AR38
AT32
AR32

AR25
AR27
AR22
AR21
AN43
AP43
AT13
AR18
AT18
AU18

DDR1_PAR,DDR1_ALERT# for DDR4

DDR_DRAMRST#
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2

DDR_DRAMRST# <20>

DDR4, Ballout for side by side(Interleave)

D D

CPU@

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15

DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24

C C

B B

DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

UC1B

AL71

DDR0_DQ[0]

AL68

DDR0_DQ[1]

AN68

DDR0_DQ[2]

AN69

DDR0_DQ[3]

AL70

DDR0_DQ[4]

AL69

DDR0_DQ[5]

AN70

DDR0_DQ[6]

AN71

DDR0_DQ[7]

AR70

DDR0_DQ[8]

AR68

DDR0_DQ[9]

AU71

DDR0_DQ[10]

AU68

DDR0_DQ[11]

AR71

DDR0_DQ[12]

AR69

DDR0_DQ[13]

AU70

DDR0_DQ[14]

AU69

DDR0_DQ[15]

Interleave / Non-Interleaved

BB65

DDR0_DQ[16]/DDR0_DQ[32]

AW65

DDR0_DQ[17]/DDR0_DQ[33]

AW63

DDR0_DQ[18]/DDR0_DQ[34]

AY63

DDR0_DQ[19]/DDR0_DQ[35]

BA65

DDR0_DQ[20]/DDR0_DQ[36]

AY65

DDR0_DQ[21]/DDR0_DQ[37]

BA63

DDR0_DQ[22]/DDR0_DQ[38]

BB63

DDR0_DQ[23]/DDR0_DQ[39]

BA61

DDR0_DQ[24]/DDR0_DQ[40]

AW61

DDR0_DQ[25]/DDR0_DQ[41]

BB59

DDR0_DQ[26]/DDR0_DQ[42]

AW59

DDR0_DQ[27]/DDR0_DQ[43]

BB61

DDR0_DQ[28]/DDR0_DQ[44]

AY61

DDR0_DQ[29]/DDR0_DQ[45]

BA59

DDR0_DQ[30]/DDR0_DQ[46]

AY59

DDR0_DQ[31]/DDR0_DQ[47]

AY39

DDR0_DQ[32]/DDR1_DQ[0]

AW39

DDR0_DQ[33]/DDR1_DQ[1]

AY37

DDR0_DQ[34]/DDR1_DQ[2]

AW37

DDR0_DQ[35]/DDR1_DQ[3]

BB39

DDR0_DQ[36]/DDR1_DQ[4]

BA39

DDR0_DQ[37]/DDR1_DQ[5]

BA37

DDR0_DQ[38]/DDR1_DQ[6]

BB37

DDR0_DQ[39]/DDR1_DQ[7]

AY35

DDR0_DQ[40]/DDR1_DQ[8]

AW35

DDR0_DQ[41]/DDR1_DQ[9]

AY33

DDR0_DQ[42]/DDR1_DQ[10]

AW33

DDR0_DQ[43]/DDR1_DQ[11]

BB35

DDR0_DQ[44]/DDR1_DQ[12]

BA35

DDR0_DQ[45]/DDR1_DQ[13]

BA33

DDR0_DQ[46]/DDR1_DQ[14]

BB33

DDR0_DQ[47]/DDR1_DQ[15]

AY31

DDR0_DQ[48]/DDR1_DQ[32]

AW31

DDR0_DQ[49]/DDR1_DQ[33]

AY29

DDR0_DQ[50]/DDR1_DQ[34]

AW29

DDR0_DQ[51]/DDR1_DQ[35]

BB31

DDR0_DQ[52]/DDR1_DQ[36]

BA31

DDR0_DQ[53]/DDR1_DQ[37]

BA29

DDR0_DQ[54]/DDR1_DQ[38]

BB29

DDR0_DQ[55]/DDR1_DQ[39]

AY27

DDR0_DQ[56]/DDR1_DQ[40]

AW27

DDR0_DQ[57]/DDR1_DQ[41]

AY25

DDR0_DQ[58]/DDR1_DQ[42]

AW25

DDR0_DQ[59]/DDR1_DQ[43]

BB27

DDR0_DQ[60]/DDR1_DQ[44]

BA27

DDR0_DQ[61]/DDR1_DQ[45]

BA25

DDR0_DQ[62]/DDR1_DQ[46]

BB25

DDR0_DQ[63]/DDR1_DQ[47]

KBL-RU42_BGA1356

KBL-R U4+2

DDR0_CKN[0]
DDR0_CKP[0]
DDR0_CKN[1]
DDR0_CKP[1]

DDR0_CKE[0]
DDR0_CKE[1]
DDR0_CKE[2]
DDR0_CKE[3]

DDR0_CS#[0]

DDR0_CS#[1]
DDR0_ODT[0]
DDR0_ODT[1]

DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5]
DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9]
DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6]
DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8]
DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]

DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]
DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12]
DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]

DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT#
DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]

DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]

DDR0_CAS#/DDR0_CAB[1]/DDR0_M A[15]

DDR0_WE#/DDR0_CA B[2]/DDR0_MA[14]

DDR0_RAS#/DDR0_CAB[3]/DDR0_M A[16]

DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]

DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]

DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]

DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]

DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1]
DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]

DDR CH - A

2 OF 20

DDR3L / LPDDR3 / DDR4

DDR0_MA[3]

DDR0_MA[4]
DDR0_DQSN[0]
DDR0_DQSP[0]
DDR0_DQSN[1]
DDR0_DQSP[1]

Interleave / Non-Interleaved

DDR0_DQSN[2]/DDR0_DQSN[4]

DDR0_DQSP[2]/DDR0_DQSP[4]

DDR0_DQSN[3]/DDR0_DQSN[5]

DDR0_DQSP[3]/DDR0_DQSP[5]

DDR0_DQSN[4]/DDR1_DQSN[0]

DDR0_DQSP[4]/DDR1_DQSP[0]

DDR0_DQSN[5]/DDR1_DQSN[1]

DDR0_DQSP[5]/DDR1_DQSP[1]

DDR0_DQSN[6]/DDR1_DQSN[4]

DDR0_DQSP[6]/DDR1_DQSP[4]

DDR0_DQSN[7]/DDR1_DQSN[5]

DDR0_DQSP[7]/DDR1_DQSP[5]

DDR0_ALERT#

DDR_VREF_CA
DDR0_VREF_DQ
DDR1_VREF_DQ

DDR_VTT_CNTL

Rev_0.1

DDR0_PAR

DDR4 COMPENSATION SIGNALS

SM_RCOMP0

SM_RCOMP1

SM_RCOMP2

CAD Note:
Trace width=12~15 mil, Spacing=20 mils
Max trace length= 500 mil

A A

1 2

RC5 121_0402_1%

1 2

RC6 80.6_0402_1%

1 2

RC7 100_0402_1%

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.

5

4

3

2

Title

Size Document N umber Re v

Size Document N umber Re v

Size Document N umber Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CPU (2/14)

CPU (2/14)

CPU (2/14)

LA-F312P

LA-F312P

LA-F312P

7 58Wednesday, December 20, 2017

7 58Wednesday, December 20, 2017

7 58Wednesday, December 20, 2017

1

2.0

2.0

2.0

5

SPI_MOSI= SPI_IO0
SPI_MISO= SPI_IO1
PCH EDS R0.7 p.235~236

PCH_SPI_CLK
PCH_SPI_D1

CXDP@

1 2

PCH_SPI_DO_XDP<14>

PCH_SPI_DO2_XDP<14>

D D

C C

PCH_SPI_CLK_1_R PCH_SPI_CLK_0_R

33_0402_5%

@EMI@

12

RC28

33P_0402_50V8J

@EMI@

12

CC7

B B

A A

RC10 1K_0402_1%

CXDP@

1 2

RC11 1K_0402_1%

PCH_SPI_CS#2<33>

PCH_CL_CLK1<29>
PCH_CL_DATA1<29>
PCH_CL_RST1#<29>

ESPI_ALERT#<31>

+3.3V_1.8V_ESPI

33_0402_5%

@EMI@

12

RC29

33P_0402_50V8J

12

CC8

RC21 8.2K_0402_1%

@EMI@

PCH_SPI_CS#0_R1

PCH_SPI_D2_R1 PCH_SPI_CLK_0_R

PCH_SPI_CS#1_R1

PCH_SPI_D2_R1

PCH_SPI_D0
PCH_SPI_D2
PCH_SPI_D3
PCH_SPI_CS#0
PCH_SPI_CS#1
PCH_SPI_CS#2

12

+3.3V_SPI

RC30 1K_0402_5%

@

RC31 1K_0402_5%

@

RC316 1K_0402_5%

@

@

1 2

RC37 0_0402_5%

1 2

RC39 33_0402_5%

1 2

RC42 0_0402_5%@

1 2

RC43 33_0402_5%

@

12

12

12

03/02:follow Intel MOW_2015W W06

PCH_SPI_D2_R1

PCH_SPI_D3_R1

PCH_SPI_D3_R1

AV2

SPI0_CLK

AW3

SPI0_MISO

AV3

SPI0_MOSI

AW2

SPI0_IO2

AU4

SPI0_IO3

AU3

SPI0_CS0#

AU2

SPI0_CS1#

AU1

SPI0_CS2#

M2

GPP_D1/SPI1_CLK

M3

GPP_D2/SPI1_MISO

J4

GPP_D3/SPI1_MOSI

V1

GPP_D21/SPI1_IO2

V2

GPP_D22/SPI1_IO3

M1

GPP_D0/SPI1_CS#

G3

CL_CLK

G2

CL_DATA

G1

CL_RST#

AW13

GPP_A0/RCIN#

AY11

GPP_A6/SERIRQ

KBL-RU42_BGA1356

PCH_SPI_CS#0_R2
PCH_SPI_D1_0_R
PCH_SPI_D2_0_R

PCH_SPI_CS#1_R2
PCH_SPI_D1_1_R
PCH_SPI_D2_1_R

UC1E

4

CPU@

SPI - TOUCH

C LINK

SPI - FLASH

PCH_SPI_D1_R1<33>

PCH_SPI_D0_R1<33>

PCH_SPI_CLK_R1<33>

1
2
3
4

1
2
3
4

KBL-R U4+2

LPC

PCH_SPI_D1_R1
PCH_SPI_D0_R1
PCH_SPI_CLK_R1
PCH_SPI_D3_R1

PCH_SPI_CLK_R1
PCH_SPI_D0_R1
PCH_SPI_D1_R1

128Mb Flash ROM

UC5

/CS
IO1
IO2
GND

W25Q128JVSIQ_SO8

VCC

CLK

IO3

IO0

128Mb Flash ROM

UC6

@

/CS
IO1
IO2
GND

W25Q128JVSIQ_SO8

VCC

CLK

IO3

IO0

SMBUS, SMLINK

GPP_C2/SMBALERT#

GPP_C5/SML0ALERT#

GPP_B23/SML1ALERT#/PCHHOT#

GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1
GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS#

GPP_A14/SUS_STAT#/ESPI_RESET#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

GPP_A10/CLKOUT_LPC1

SOFTWARE TAA

RPC1

PCH_SPI_D1_0_R

1 8

PCH_SPI_D0_0_R

2 7

PCH_SPI_CLK_0_R

3 6

PCH_SPI_D3_0_R

4 5

33_0804_8P4R_5%

1 2

RC407 33_0402_5%

@

1 2

RC408 33_0402_5%

@

1 2

RC409 33_0402_5%

@

1 2

RC410 33_0402_5%

@

+3.3V_SPI

8

PCH_SPI_D3_0_R

7
6

PCH_SPI_D0_0_R

5

+3.3V_SPI

8

PCH_SPI_D3_1_R

7

PCH_SPI_CLK_1_R

6

PCH_SPI_D0_1_R

5

CC9

1 2

0.1U_0201_10V6K

CC10

@
1 2

0.1U_0201_10V6K

3

Rev_0.1

GPP_C0/SMBCLK

GPP_C1/SMBDATA

GPP_C3/SML0CLK

GPP_C4/SML0DATA

GPP_C6/SML1CLK

GPP_C7/SML1DATA

GPP_A8/CLKRUN#

5 OF 20

PCH_SPI_D3_1_RPCH_SPI_D3_R1
PCH_SPI_CLK_1_R
PCH_SPI_D0_1_R
PCH_SPI_D1_1_R

R7
R8
R10

R9
W2
W1

W3
V3
AM7

AY13
BA13
BB13
AY12
BA12
BA11

AW9
AY9
AW11

+3.3V_SPI

MEM_SMBCLK
MEM_SMBDATA
PCH_SMB_ALERT#

SML0_SMBCLK
SML0_SMBDATA
GPP_C5

SML1_SMBCLK
SML1_SMBDATA
GPP_B23

ESPI_IO0_R
ESPI_IO1_R
ESPI_IO2_R
ESPI_IO3_R

ESPI_CLK
PCI_CLK_LPC1

CLKRUN#

RC32 0_0402_5%

@

1 2

@

RC33 0_0402_5%

1 2

@

RC34 0_0402_5%

1 2

@

RC35 0_0402_5%

1 2

@

RC36 0_0402_5%

1 2

@

RC38 0_0402_5%

1 2

@

RC40 0_0402_5%

+3.3V_ALW_PCH

@

RC41 0_0402_5%

SML0_SMBCLK <27>
SML0_SMBDATA <2 7>

SML1_SMBCLK <31>
SML1_SMBDATA <3 1>

1 2

RC366

1 2

RC367

1 2

RC368

1 2

RC369

ESPI_CS# <31,32>

ESPI_RESET# <31,32>

1 2

RC16

EMI@

1 2

1 2

RC22@ 22_0402_5%

ESPI_CLK_5105

SML0_SMBCLK

SML1_SMBCLK

MEM_SMBCLK

PCH_SPI_CS#1_R1

12

PCH_SPI_D0_R1

PCH_SPI_D1_R1

PCH_SPI_CLK_R1

PCH_SPI_CS#0_R1

PCH_SPI_D2_R1

PCH_SPI_D3_R1

2

15_0402_5%
15_0402_5%
15_0402_5%
15_0402_5%

15_0402_5%

CHECK,LPC_CLK FOR DEBUG CARD?

ESPI_IO0 <31,32>
ESPI_IO1 <31,32>
ESPI_IO2 <31,32>
ESPI_IO3 <31,32>

RF Request

1 2

CC316@RF@ 33P_0402_50V8J

1 2

CC318@RF@ 33P_0402_50V8J

1 2

CC319@RF@ 33P_0402_50V8J

1 2

CC320@RF@ 33P_0402_50V8J

Place close CPU side

JSPI1

1

PCH_SPI_CS#1

PCH_SPI_D0

PCH_SPI_D1

PCH_SPI_CLK

PCH_SPI_CS#0

PCH_SPI_D2

PCH_SPI_D3

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

GND1

22

GND2

CVILU_CF5020FD0R0-05-NH

MEM_SMBCLK

MEM_SMBDATA

ESPI_CLK_5105 <31,32>

CONN@

3 4

DMN65D8LDW-7_SOT363-6

+3.3V_RUN

2

6

5

DMN65D8LDW-7_SOT363-6

QC2B

For BR/SB

1

DDR_XDP_WAN_S MBCLK <14,20>

QC2A

DDR_XDP_WAN_S MBDAT <14,20>

DDR_XDP_WAN_S MBDAT

DDR_XDP_WAN_S MBCLK

MEM_SMBCLK

MEM_SMBDATA

SML1_SMBCLK

SML1_SMBDATA

SML0_SMBCLK

SML0_SMBDATA

Rese rve

SML0_SMBCLK

SML0_SMBDATA

CLKRUN#

PCH_SMB_ALERT#

TLS C ONFIDENTIALITY

HIGH
LOW(DEFAULT)

WEAK INT ERNAL 20K PD

GPP_C5

EC interface

HIGH
LOW(DEFAULT)

WEAK INTERNAL 20k PD

GPP_B23

EXI BOOT STALL BYPASS

HIGH
LOW(DEFAULT)

WEAK INTERNAL PD

1

+3.3V_RUN

1 2

RC318 2.2K_0402_5%

1 2

RC319 2.2K_0402_5%

1 2

RC12 1K_0402_5%

1 2

RC14 1K_0402_5%

1 2

RC15 1K_0402_5%

1 2

RC17 1K_0402_5%

1 2

RC347 499_0402_1%

1 2

RC348 499_0402_1%

1 2

RC19 499_0402_1%@

1 2

RC20 499_0402_1%@

1 2

RC27 8.2K_0402_5%LPC@

1 2

RC23 2.2K_0402_5%

1 2

RC25 4.7K_0402_5%ESPI@

1 2

RC317 150K_0402_5%

ENABLE
DISAB LE

ESPI

LPC

ENABLED
DIABL ED

+3.3V_ALW_PCH

+3.3V_LAN

+3.3V_ALW_PCH

+3.3V_ALW_PCH

+3.3V_ALW_PCH

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.

5

4

3

2

Title

Size Document N umber Re v

Size Document N umber Re v

Size Document N umber Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CPU (3/14)

CPU (3/14)

CPU (3/14)

LA-F312P

LA-F312P

LA-F312P

8 58Wednesday, December 20, 2017

8 58Wednesday, December 20, 2017

8 58Wednesday, December 20, 2017

1

2.0

2.0

2.0

5

4

3

2

1

For BR/SB

CPU@

AN8
AP7
AP8
AR7

AM5
AN7
AP5
AN5

AB1
AB2

W4

AB3

AD1
AD2
AD3
AD4

U7
U6

U8
U9

AH9

AH10

AH11
AH12

AF11
AF12

+5V_ALW

UC1F

LPSS ISH

GPP_B15/GSPI0_CS#
GPP_B16/GSPI0_CLK
GPP_B17/GSPI0_MISO
GPP_B18/GSPI0_MOSI

GPP_B19/GSPI1_CS#
GPP_B20/GSPI1_CLK
GPP_B21/GSPI1_MISO
GPP_B22/GSPI1_MOSI

GPP_C8/UART0_RXD
GPP_C9/UART0_TXD
GPP_C10/UART0_RTS#
GPP_C11/UART0_CTS#

GPP_C20/UART2_RXD
GPP_C21/UART2_TXD
GPP_C22/UART2_RTS#
GPP_C23/UART2_CTS#

GPP_C16/I2C0_SDA
GPP_C17/I2C0_SCL

GPP_C18/I2C1_SDA
GPP_C19/I2C1_SCL

GPP_F4/I2C2_SDA
GPP_F5/I2C2_SCL

GPP_F6/I2C3_SDA
GPP_F7/I2C3_SCL

GPP_F8/I2C4_SDA
GPP_F9/I2C4_SCL

KBL-RU42_BGA1356

LPSS_UART2_RXD
LPSS_UART2_TXD

+3.3V_RUN

D D

@

RC282 100K_0402_5%

RC237 10K_0402_5 %

RC402 49.9K_0402_1%@

RC403 49.9K_0402_1%@

+3.3V_ALW_PCH

RC283 10K_0402_5%

@

RC330 49.9K_0402_1%

@

RC331 49.9K_0402_1%

C C

+3.3V_RUN

RC186 4.7K_0402_5%@

PCH_3.3V_TS_EN

12

SIO_EXT_SCI#

12

12

12

12

12

12

NRB_BIT

12

LPSS_UART2_RXD

LPSS_UART2_TXD

SIO_EXT_WAKE#

LPSS_UART2_RXD

LPSS_UART2_TXD

TPM_PIRQ#<33>

MEDIACARD_IRQ#<28>

RC560 0_0402_ 5%

@

RC561 0_0402_ 5%

PCH_3.3V_TS_EN<26>

RC405 100K _0402_5%@

SBIOS_TX<32>

I2C1_SDA_TP<37>

I2C1_SCK_TP<37>

1 2

1 2

12

+3.3V_RUN

10K_0402_5%

RC267

ONE_DIMM#

TPM_PIRQ#_R

NRB_BIT

SIO_EXT_SCI#

BBS_BIT6

GPP_C8

TYPEC_CON_SEL1
TYPEC_CON_SEL2

LPSS_UART2_RXD
LPSS_UART2_TXD

NO REBOOT STRAP

HIGH
LOW(DEFAULT)

Weak IPD

B B

+3.3V_ALW_PCH

RC184 8.2K_0402_5%

@

No REBOOT

REBOOT ENABLE

BBS_BIT6

12

1 2

10K_0402_5%

12

DIMM Detect

HIGH
LOW

@

RC268

ONE_DIMM#

1 DIMM
2 DIMM

BOOT BIOS Dest i nat i on(Bi t 6)

HIGH
LOW(DEFAULT)

Internal 20k PD

LPC
SPI

KBL-R U4+2

Sx_EXIT_HOLDOFF# / GPP_A12 / BM_BUSY# / ISH_GP6

CONN@

JUART1

1

1

2

2

3

3

4

4

5

GND

6

GND

CVILU_CI1804M1VRA-NH

Rev_0.1

GPP_D9
GPP_D10
GPP_D11
GPP_D12

GPP_D5/ISH_I2C0_SDA
GPP_D6/ISH_I2C0_SCL

GPP_D7/ISH_I2C1_SDA
GPP_D8/ISH_I2C1_SCL

GPP_F10/I2C5_SDA/ISH_I2C2_SDA

GPP_F11/I2C5_SCL/ISH_I2C2_SCL

GPP_D13/ISH_UART0_RXD/SML0BDATA /I2C4B_SDA

GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_S CL

GPP_D15/ISH_UART0_RTS#

GPP_D16/ISH_UART0_CTS#/SML0BALER T#

GPP_C12/UART1_RXD/ISH_UART1_RXD

GPP_C13/UART1_TXD/ISH_UART1_TXD
GPP_C14/UART1_RTS#/ISH_UART1_RTS#
GPP_C15/UART1_CTS#/ISH_UART1_CTS#

GPP_A18/ISH_GP0
GPP_A19/ISH_GP1
GPP_A20/ISH_GP2
GPP_A21/ISH_GP3
GPP_A22/ISH_GP4
GPP_A23/ISH_GP5

6 OF 20

P2
P3
P4
P1

M4
N3

N1
N2

AD11
AD12

U1
U2
U3
U4

AC1
AC2
AC3
AB4

AY8
BA8
BB7
BA7
AY7
AW7
AP13

MEM_INTERLEAVED

RC555

@

10K_0402_5%

1 2

12

RC556

@

10K_0402_5%

MEM_INTERLEAVED

AR_DET#

ISH_I2C2_SDA
ISH_I2C2_SCL

RTD3_CIO_PWR_EN

CLKDET#

TPM_TYPE
LID_CL#_PCH

ISH_I2C2_SDA <29>
ISH_I2C2_SCL <29>

9/24: Reserve for embedded locat i on ,r ef er I nt el PDG 0. 9

ISH_UART0_RXD <29>

ISH_UART0_TXD <29>
ISH_UART0_RTS# <29>

ISH_UART0_CTS# <29>

SIO_EXT_WAKE# <31>

LCD_CBL_DET# <26>

@

T258

PAD~D

PAD~D

WWAN

WLAN

T18 @PAD~D

@

T268

Reser ved

ISH_I2C2_SDA

ISH_I2C2_SCL

LCD_CBL_DET#

TPM_TYPE

RC363 1K_0402_5%

RC362 1K_0402_5%

RC287 100K_0402_5%

GPP_A GROUP is +1.8V

+3.3V_ALW_PCH +3.3V_ALW_PCH

RC371
10K_0402_5%

1 2

AR_DET#

12

@

10K_0402_5%
RC372

DIMM TYPE

HIGH Interle ave

+3.3V_ALW_PCH+3.3V_ALW_PCH

RC553

@

10K_0402_5%

1 2

TYPEC_CON_SEL2TYPEC_CON_SEL1

12

RC554

@

10K_0402_5%

1 2

12

1 2

1 2

1 2

1 2

RC349 100_0402_1%@

RC400
10K_0402_5%

@

10K_0402_5%
RC401

+1.8V_RUN

+3.3V_RUN

AR_DET #

NON ARHIGH

LOW ARLOW Non-Interl eave

A A

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.

5

4

3

Vendor

TYPEC_CON_SE L1 LOW

TYPEC_CON_SE L2

LOW

FOXCONJAE

LOW

HIGH LOW

TBDTBD

HIGHHIGH

HIGH

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document N umber Re v

Size Document N umber Re v

Size Document N umber Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CPU (4/14)

CPU (4/14)

CPU (4/14)

LA-F312P

LA-F312P

LA-F312P

9 58Wednesday, December 20, 2017

9 58Wednesday, December 20, 2017

9 58Wednesday, December 20, 2017

1

2.0

2.0

2.0

5

4

3

2

1

Steamboat MLK 12&13 nonAR

CPU@

UC1H

PCIE / USB3 / SATA

D D

Card Reader RTS5242----->

Ext USB3 Port 1 Charge (Right) ----->

M.2 3030(WLAN) --->

10/100/1G LAN --->

C C

M.2 3042(SATA Cache )--->

M2 2280 SSD (4 Lane) --->

B B

PCIE_PRX_DTX_N1<28>

PCIE_PRX_DTX_P1<28>
PCIE_PTX_DRX_N1<28>
PCIE_PTX_DRX_P1<28>

USB3_PRX_DTX_N6<35>

USB3_PRX_DTX_P6<35>
USB3_PTX_DRX_N6<35>
USB3_PTX_DRX_P6<35>

PCIE_PRX_DTX_N3<29>

PCIE_PRX_DTX_P3<29>
PCIE_PTX_DRX_N3<29>
PCIE_PTX_DRX_P3<29>

PCIE_PRX_DTX_N4<27>

PCIE_PRX_DTX_P4<27>
PCIE_PTX_DRX_N4<27>
PCIE_PTX_DRX_P4<27>

SATA_PRX_DTX_N1<29>
SATA_PRX_DTX_P1<29>
SATA_PTX_DRX_N1<29>
SATA_PTX_DRX_P1<29>

PCIE_PRX_DTX_N9<34>
PCIE_PRX_DTX_P9<34>
PCIE_PTX_DRX_N9<34>
PCIE_PTX_DRX_P9<34>

PCIE_PRX_DTX_N10<34>
PCIE_PRX_DTX_P10<34>
PCIE_PTX_DRX_N10<34>
PCIE_PTX_DRX_P10<34>

1 2

RC45 100_0402_1%

CPU_XDP_PRDY#<14>

CPU_XDP_PREQ#<14>

PCIE_PRX_DTX_N11<34>
PCIE_PRX_DTX_P11<34>
PCIE_PTX_DRX_N11<34>
PCIE_PTX_DRX_P11<34>
PCIE_PRX_DTX_N12<34>
PCIE_PRX_DTX_P12<34>
PCIE_PTX_DRX_N12<34>
PCIE_PTX_DRX_P12<34>

PCIE_RCOMPN
PCIE_RCOMPP

H13

PCIE1_RXN/USB3_5_RXN

G13

PCIE1_RXP/USB3_5_RXP

B17

PCIE1_TXN/USB3_5_TXN

A17

PCIE1_TXP/USB3_5_TXP

G11

PCIE2_RXN/USB3_6_RXN

F11

PCIE2_RXP/USB3_6_RXP

D16

PCIE2_TXN/USB3_6_TXN

C16

PCIE2_TXP/USB3_6_TXP

H16

PCIE3_RXN

G16

PCIE3_RXP

D17

PCIE3_TXN

C17

PCIE3_TXP

G15

PCIE4_RXN

F15

PCIE4_RXP

B19

PCIE4_TXN

A19

PCIE4_TXP

F16

PCIE5_RXN

E16

PCIE5_RXP

C19

PCIE5_TXN

D19

PCIE5_TXP

G18

PCIE6_RXN

F18

PCIE6_RXP

D20

PCIE6_TXN

C20

PCIE6_TXP

F20

PCIE7_RXN/SATA0_RXN

E20

PCIE7_RXP/SATA0_RXP

B21

PCIE7_TXN/SATA0_TXN

A21

PCIE7_TXP/SATA0_TXP

G21

PCIE8_RXN/SATA1A_RXN

F21

PCIE8_RXP/SATA1A_RXP

D21

PCIE8_TXN/SATA1A_TXN

C21

PCIE8_TXP/SATA1A_TXP

E22

PCIE9_RXN

E23

PCIE9_RXP

B23

PCIE9_TXN

A23

PCIE9_TXP

F25

PCIE10_RXN

E25

PCIE10_RXP

D23

PCIE10_TXN

C23

PCIE10_TXP

F5

PCIE_RCOMPN

E5

PCIE_RCOMPP

D56

PROC_PRDY#

D61

PROC_PREQ#

BB11

GPP_A7/PIRQA#

E28

PCIE11_RXN/SATA1B_RXN

E27

PCIE11_RXP/SATA1B_RXP

D24

PCIE11_TXN/SATA1B_TXN

C24

PCIE11_TXP/SATA1B_TXP

E30

PCIE12_RXN/SATA2_RXN

F30

PCIE12_RXP/SATA2_RXP

A25

PCIE12_TXN/SATA2_TXN

B25

PCIE12_TXP/SATA2_TXP

KBL-RU42_BGA1356

KBL-R U4+2

SSIC / USB3

USB3_2_RXN/SSIC_RXN

USB3_2_RXP/SSIC_RXP
USB3_2_TXN/SSIC_TXN

USB3_2_TXP/SSIC_TXP

USB2

USB2_VBUSSENSE

GPP_E9/USB2_OC0#
GPP_E10/USB2_OC1#
GPP_E11/USB2_OC2#
GPP_E12/USB2_OC3#

GPP_E4/DEVSLP0
GPP_E5/DEVSLP1
GPP_E6/DEVSLP2

GPP_E0/SATAXPCIE0/SATAGP0
GPP_E1/SATAXPCIE1/SATAGP1
GPP_E2/SATAXPCIE2/SATAGP2

GPP_E8/SATALED#

Rev_0.1

USB3_1_RXN
USB3_1_RXP
USB3_1_TXN

USB3_1_TXP

USB3_3_RXN
USB3_3_RXP
USB3_3_TXN

USB3_3_TXP

USB3_4_RXN
USB3_4_RXP
USB3_4_TXN

USB3_4_TXP

USB2N_1
USB2P_1

USB2N_2
USB2P_2

USB2N_3
USB2P_3

USB2N_4
USB2P_4

USB2N_5
USB2P_5

USB2N_6
USB2P_6

USB2N_7
USB2P_7

USB2N_8
USB2P_8

USB2N_9
USB2P_9

USB2N_10
USB2P_10

USB2_COMP

USB2_ID

8 OF 20

H8
G8
C13
D13

J6
H6
B13
A13

J10
H10
B15
A15

E10
F10
C15
D15

AB9
AB10

AD6
AD7

AH3
AJ3

AD9
AD10

AJ1
AJ2

AF6
AF7

AH1
AH2

AF8
AF9

AG1
AG2

AH7
AH8

AB6
AG3
AG4

A9
C9
D9
B9

J1
J2
J3

H2
H3
G4

H1

USBCOMP
USB2_ID

USB2_VBUSSENSE

USB_OC2#
USB_OC3#

Rese rve

SATAGP0
M3042_PCIE#_SATA

M2280_PCIE_SATA#

SATALED#

USB3_PRX_DTX_N1 <22>
USB3_PRX_DTX_P1 <22>
USB3_PTX_DRX_N1 <22>

USB3_PTX_DRX_P1 <2 2>

USB3_PRX_DTX_N2 <29>
USB3_PRX_DTX_P2 <29>
USB3_PTX_DRX_N2 <29>

USB3_PTX_DRX_P2 <2 9>

USB3_PRX_DTX_N3 <36>
USB3_PRX_DTX_P3 <36>
USB3_PTX_DRX_N3 <36>

USB3_PTX_DRX_P3 <3 6>

USB20_N1 <23>
USB20_P1 <23>

USB20_N2 <36>
USB20_P2 <36>

USB20_N4 <29>
USB20_P4 <29>

USB20_N5 <26>
USB20_P5 <26>

USB20_N7 <29>
USB20_P7 <29>

USB20_N8 <26>
USB20_P8 <26>

USB20_N9 <35>
USB20_P9 <35>

USB20_N10 <33>
USB20_P10 <33>

1 2

RC44 113_0402_1%

USB2_ID <23>

1 2

RC338 1K_0402_5%

USB_OC0# <35>
USB_OC1# <36>

M3042_DEVSLP <29>
M2280_DEVSLP <34>

M3042_PCIE#_SATA <31>
M2280_PCIE_SATA# <34>

SATALED# <29,34,38>

-----> Typce-C(Non AR)

-----> M.2 3042(LTE)

-----> Ext USB3 Port 2 (Lert Front)

-----> Typce-C(Non AR)

-----> Ext USB Port 2(Lef t Front)

-----> M2 3042(WWAN)

-----> Camera

-----> M.2 3030(BT)

-----> LCD Touch

-----> Ext USB Port 1 Charge (Right)

-----> USH

NEED DOUBLE C HECK

USB_OC3#
USB_OC0#
USB_OC1#
USB_OC2#

USB2_ID

RPC3

4 5
3

6

2

7

1

8

10K_8P4R_5%

1 2

RC337 10K_0402_5%

+3.3V_ALW_PCH

+3.3V_RUN

M2280_PCIE_SATA#
SATALED#

M3042_PCIE#_SATA

A A

SATAGP0

RPC4

4 5
3
2
1

10K_8P4R_5%

6
7
8

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.

5

4

3

2

Title

Size Document N umber Re v

Size Document N umber Re v

Size Document N umber Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CPU (5/14)

CPU (5/14)

CPU (5/14)

LA-F312P

LA-F312P

LA-F312P

10 58Wednesday, December 20, 2017

10 58Wednesday, December 20, 2017

10 58Wednesday, December 20, 2017

1

2.0

2.0

2.0

5

CLK_PCIE_N0<28>

Cardreader-- ->

D D

WLAN--->

M.2 SDD--->

LAN--->

+3.3V_LAN

C C

+3.3V_ALW_DSW

+1.0V_VCCST

+3.3V_ALW_PCH

B B

+3.3V_1.8V_PGPPA

@

CLK_PCIE_P0<28>

CLKREQ_PCIE#0<28>

CLK_PCIE_N1<29>
CLK_PCIE_P1<29>

CLKREQ_PCIE#1<29>

CLK_PCIE_N3<34>
CLK_PCIE_P3<34>

CLKREQ_PCIE#3<34>

CLK_PCIE_N4<27>
CLK_PCIE_P4<27>

CLKREQ_PCIE#4<27>

RL70 10K_0402_5%@

RC323 10K_0402_5%

RC67 1K_0402 _5%

RC71 1K_0402 _5%

RC74 10K_0402_5%@

10/6 depop, prevent singal step.

RC411 10K_0402_5%@

@

T9

PAD~D

VCCST_PWRGD<14,31,32>

ME_SUS_PWR_ACK<31>

RC550 1K_0402_ 5%

12

+3.3V_RUN

+3.3V_RUN

+3.3V_RUN

+3.3V_RUN

+3.3V_RUN

+3.3V_RUN

12

12

12

12

12

12

SUSACK#<31>

SUSACK#_R

@RF@

RC373 0_0402_5%
RC189 10K_0402_5%

@RF@

RC374 0_0402_5%
RC47 10K_0402_5%

RC50 10K_0402_5%

@RF@

RC376 0_0402_5%
RC59 10K_0402_5%

@RF@

RC377 0_0402_5%
RC51 10K_0402_5%

RC190 10K_0402_5%

LAN_WAKE#

PCH_PCIE_WAKE#

VCCST_PWRGD

ME_SUS_PWR_ACK

PCH_PWROK

RC77 1K_0402 _5%@
RC78 60.4_0402_1%

@

RC444 0_0402_5%
RC443 0_0402_5%@

1 2

12

1 2

12

12

1 2

12

1 2

12

12

PCH_PLTRST#

H_CPUPWRGD VCCST_PWRGD

100P_0402_50V8J

12

PCH_RSMRST#_AND<14,37>

1 2
1 2

1 2
1 2

PCH_PCIE_WAKE#<31,32>

PM_LANPHY_ENABLE<27>

CLKREQ_PCIE#0_R

CLKREQ_PCIE#1_R

CLKREQ_PCIE#2_R

CLKREQ_PCIE#3_R

CLKREQ_PCIE#4_R

CLKREQ_PCIE#5_R

@

RC62 0_0402_5%

@

RC244 0_0402_5%

UC7

TC7SH08FU_SSOP5~D

100P_0402_50V8J

12

CC300ESD@

SYS_PWROK< 14,31>
PCH_PWROK<46>

PCH_DPWROK<31>

LAN_WAKE#<27,31>

3.3V_CAM_EN#<26>

CC301ESD@

ESD Request:place near CPU side

PCH_PLTRST#
SYS_RESET#

PCH_RSMRST#_AND

H_CPUPWRGDH_CPUPWRGD_R
VCCST_PWRGD_CPU

ME_SUS_PWR_ACK_R
SUSACK#_R

RC311 10K_0 402_5%

1 2

1 2

+3.3V_ALW_PCH

1

B

2

A

12

RC215

POP

NO Support Deep sleep

DE-POP

PCH_DPWROK PCH_RSMRST#_AND

A A

1

2

1 2

RC215 0_0402_5%NDS3@

100K_0402_1%

0.01UF_0402_25V7K

12

@

RC220

CC266

12

RC75
10K_0402_5%

5

Support Deep sleep

XDP_DBRESET#<14>

+3.3V_RUN

XDP_DBRESET#

RC225@ 8.2K_0402_5%

RC227@ 8.2K_0402_5%

12

12

4

CPU@

UC1J

D42

CLKOUT_PCIE_N0

C42

CLKOUT_PCIE_P0

AR10

GPP_B5/SRCCLKREQ0#

B42

CLKOUT_PCIE_N1

A42

CLKOUT_PCIE_P1

AT7

GPP_B6/SRCCLKREQ1#

D41

CLKOUT_PCIE_N2

C41

CLKOUT_PCIE_P2

AT8

GPP_B7/SRCCLKREQ2#

D40

CLKOUT_PCIE_N3

C40

CLKOUT_PCIE_P3

AT10

GPP_B8/SRCCLKREQ3#

B40

CLKOUT_PCIE_N4

A40

CLKOUT_PCIE_P4

AU8

GPP_B9/SRCCLKREQ4#

E40

CLKOUT_PCIE_N5

E38

CLKOUT_PCIE_P5

AU7

GPP_B10/SRCCLKREQ5#

KBL-RU42_BGA1356

5

P

PCH_PLTRST#_AND

4

O

12

G

3

@

100K_0402_5%

UC1K

AN10

GPP_B13/PLTRST#

B5

SYS_RESET#

AY17

RSMRST#

A68

PROCPWRGD

B65

VCCST_PWRGD

B6

SYS_PWROK

BA20

PCH_PWROK

BB20

DSW_PWR OK

AR13

GPP_A13/SUSWARN#/SUSPWRDNACK

AP11

GPP_A15/SUSACK#

BB15

WAKE#

AM15

GPD2/LAN_WAKE#

AW17

GPD11/LANPHYPC

AT15

GPD7/RSVD

KBL-RU42_BGA1356

@

RC290 0_0402_5%

ME_RESET#

PLTRST_LAN# <27>

PCH_PLTRST#_EC <32>

RC65

CPU@

SYSTEM POWER MANAGEMENT

1 2

+3.3V_RUN

1

B

2

A

KBL-R U4+2

CLOCK SIGNALS

PCH_PLTRST#_AND <28,29, 33,34>

KBL-R U4+2

5

P

O

G

74AHC1G09GW_TSSOP5

3

SYS_RESET#_R

4

UC12@

RSVD_E3/XTAL24_IN

RSVD_C7/XTAL24_OUT

XTAL24_OUT/NC_1

CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P

VCCDSW_EN_GPIO<18>

VCCDSW_EN<31>

ALW_PWRGD_3V_5V<37,41>

GPP_B11/EXT_PWR_GATE#

RC224 1K_0402_5%

KBL-U / KBL-R U4+2

XTAL24_IN/NC_2

GPD8/SUSCLK

XCLK_BIASREF

1 2

if pop UC12, RC291 also need pop(74AHC1G09GW is OD output)

4

3

Rev_0.1

XTAL24_IN_U42_CPU XTAL24_IN_U42

E3

XTAL24_OUT_U42_CPU

C7

XTAL24_IN_U22_CPU

E37

XTAL24_OUT_U22_CPU

E35

CLK_ITPXDP_N

F43

CLK_ITPXDP_P

E43

BA17

SUSCLK

XCLK_BIASREF

E42

PCH_RTCX1

AM18

RTCX1
RTCX2

SRTCRST#

RTCRST#

10 OF 20

AM20

AN18
AM16

PCH_RTCX2

SRTCRST#

PCH_RTCRST# <31>

CMOS1 m ust take care short & touch risk on layout plac ement

PCH_PLTRST#

PCH_PLTRST#_AND

RC445

1 2

0_0402_5%

Rev_0.1

GPP_B12/SLP_S0#

GPD4/SLP_S3#
GPD5/SLP_S4#

GPD10/SLP_S5#

SLP_SUS#

SLP_LAN#

GPD9/SLP_WLAN#

GPD6/SLP_A#

GPD3/PWRBTN#

GPD1/ACPRESENT

GPD0/BATLOW#

GPP_A11/PME#

INTRUDER#

GPP_B2/VRALERT#

11 OF 20

+3.3V_RUN

1 2

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

1 2

RC60 0_0402_5%

@

RC325 0_0402_5%

@

1 2

NDS3@

RB751S40T1G_SOD523-2

SIO_SLP_S0#

AT11
AP15
BA16
AY16

AN15
AW15
BB17
AN16

BA15
AY15

PCH_BATLOW#

AU13

AU11

PME#

AP16

INTRUDER#

MPHYP_PWR_EN

AM10
AM11

VRALERT#

@

RC291

10K_0402_5%

SYS_RESET#

3

RC417 0_0402_5%

U42@
U42@
U22@
U22@

@

DC1

2 1

NDS3@

RB751S40T1G_SOD523-2

1 2
1 2

RC418 0_0402_5%
RC419 0_0402_5%

1 2
1 2

RC420 0_0402_5%

1 2

RC297 0_0402_5%

@

RC298 0_0402_5%

@

1 2

SUSCLK <29 ,34>

1 2

RC52 2.7K_0402_1%

1 2

RC324 59_0402_1%

546765_54 6765_201 4WW48 _Skylake_MO W_Rev_1_ 0

RC56 20K_0402_5%

1 2

1 2

CC24 1U_0 402_6.3V6K

RC57 20K_0402_5%

1 2

1 2

CC25 1U_0 402_6.3V6K

1

1

2

SHORT PADS~D

@

CMOS1

PLTRST_TPM# <33>

SIO_SLP_SUS#

VCCDSW_EN_Q

DC2

21

SIO_SLP_S0# <17,33,44>
SIO_SLP_S3# <31,32>
SIO_SLP_S4# <17,31,42,45>
SIO_SLP_S5# <31>

SIO_SLP_SUS# <31>
SIO_SLP_LAN# <31,39>
SIO_SLP_WLAN# <31,39>
SIO_SLP_A# <31>

SIO_PWRBTN# <14,31>

AC_PRESENT <31>

@

T115

PAD~D

connect to VCCMPHYGTAON_1P0 enable pin

XTAL24_OUT_U42
XTAL24_IN_U22
XTAL24_OUT_U22

CLK_ITPXDP_N_R <14>
CLK_ITPXDP_P_R <14>

+1.0V_CLK5

For Skylake, pop RC52,depop RC324
For Cannonlake, pop RC324,depop RC52

+RTC_CELL_PCH

2

@DS3@

RC441

1 2

0_0402_5%

RC442

NDS3@

1 2

0_0402_5%

Support DS3

No Support DS3

'V' mean POP, 'X' mean DE-POP

SYS_RESET#

0.1U_0402_25V6

@ESD@

12

CC302

ESD Request:place near CPU side

2

For KBL-R U22

U22@

1M_0402_1%

RC46

XTAL24_IN_U22
XTAL24_OUT_U22

1 2

For Skylake,YC1 24 MHz (50 Ohm ESR)
For Cannonlake,YC1 38.4 MHz (30 Ohm ESR)

546765_54 6765_201 4WW48 _Skylake_MO W_Rev_1_ 0

For KBL-R U42

U42@

1M_0402_1%

RC415

XTAL24_IN_U42
XTAL24_OUT_U42PCH_RTCRST#

PCH_RTCX1
PCH_RTCX2

PCH_PRIM_EN <17,39,43 ,44,45>

RC439

RC440 RE536RC21 5RC441RC44 2

V V V

X

V V V

X X

+3.3V_ALW_PCH

+3.3V_ALW

+3.3V_ALW

POWER_SW#_MB<32,38>

DELL CONFIDENTIAL/PROPRIETARY

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date : Sheet of

Date : Sheet of

2

Date : Sheet of

1 2

For Skylake,YC3 24 MHz (50 Ohm ESR)

RC54
10M_0402_5%

1 2

1 2

@

RC296 0_0402_5%

8/21 can change to 10K for merge to RP

PCH_BATLOW#

AC_PRESENT

INTRUDER#

MPHYP_PWR_EN

VRALERT#

X

X

X

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

SIO_SLP_LAN#

SUSCLK

SIO_SLP_S3#

SIO_SLP_S5#
SIO_SLP_S4#
SIO_SLP_A#

PCH_RTCRST#

SYS_RESET#

SIO_SLP_S0#

CPU (6/14)

CPU (6/14)

CPU (6/14)

LA-F312P

LA-F312P

LA-F312P

PCH_RTCX2_R

JAPS1

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18

19

20

CVILU_CF4218FH0R0-05-NH

1

U22@

CC21

1 2

3

4

1

2

3

4

1

2

12

RC72 8.2K_0402_5%

RC243 10K_0402_5%

RC387 10K_0402_5%@

RC73 10K_0402_5%

@

RC344 10K_0402_5%@

RC68 10K_0402_5%@

RC48 1K_0402_5%@

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

GND
GND

11 58Wednesday, December 20, 2017

11 58Wednesday, December 20, 2017

11 58Wednesday, December 20, 2017

12P_0402_50V8J

U22@

YC1

24MHZ_12PF_X3G024 000DC1H

U22@

CC22

1 2

12P_0402_50V8J

U42@

CC334

1 2

12P_0402_50V8J

U42@

YC3

24MHZ_12PF_X3G024 000DC1H

U42@

CC335

1 2

12P_0402_50V8J

CC23

1 2

15P_0402_50V8J

YC2

32.768KHZ_12.5PF_9H03200042

ESR MAX=50k ohm

CC26

1 2

12P_0402_50V8J

1 2

1 2

+RTC_CELL_PCH

1 2

RC69 1M_0402_5%

1 2

1 2

1 2

1 2

1 2

CONN@

2.0

2.0

2.0

1

+3.3V_ALW_DSW

+3.3V_ALW_PCH

+3.3V_ALW

5

4

3

2

+1.0V_VCCSTG

1

PCH_JTAG_TDI

PCH_JTAG_TDO

PCH_JTAG_TMS

1 2

RC86 51_0402_5%

Service Mode Switch:
Add a switch to ME_FWP signal to unlock the ME region and
allow the ent ir e r egi on of t he SPI fl ash to be updat ed usi ng FPT.

+3.3V_ALW_PCH

ME_FWP PCH has internal 20K PD.
(suspend power rail)

FLASH DESCRIPTOR SECURITY OVERRIDE

LOW = ENABLE (DEFAULT) -->Pin1 & Pin3 short
HIGH = DISABLE (ME can update) -->Pin2 & Pin3 short

CAM_MIC_CBL_DET# <26>

CONTACTLESS_DET# <33>

HOST_SD_WP# <28>

AUD_PWR_EN <30>

0.1U_0402_25V6

@ESD@

12

CC304

2

CPU MISC

KBL-R U4+2

KBL-R U4+2

1

2

CC332

RF@

2.2P_0402_50V8C

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.

Rev_0.1

JTAG

PROC_TCK

PROC_TDI
PROC_TDO
PROC_TMS

PROC_TRST#

PCH_JTAG_TCK

PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS

PCH_TRST#

JTAGX

4 OF 20

GPP_A17/SD_PWR_EN#/ISH_GP7

1

2

CC333

RF@

2.2P_0402_50V8C

3

CPU_XDP_TCLK XDP_JTAGX

@

RC328 0_0402_5%

CPU_XDP_TCLK

B61

CPU_XDP_TDI

D60

CPU_XDP_TDO

A61

CPU_XDP_TMS

C60

CPU_XDP_TRST#

B59

PCH_JTAG_TCK

B56

PCH_JTAG_TDI

D59

PCH_JTAG_TDO

A56

PCH_JTAG_TMS

C59

CPU_XDP_TRST#

C61

XDP_JTAGX

A59

SDIO / SDXC

GPP_G0/SD_CMD
GPP_G1/SD_DATA0
GPP_G2/SD_DATA1
GPP_G3/SD_DATA2
GPP_G4/SD_DATA3

GPP_A16/SD_1P8_SEL

RC87 1K_0402_5%@

Rev_0.1

GPP_G5/SD_CD#
GPP_G6/SD_CLK

GPP_G7/SD_WP

SD_RCOMP

GPP_F23

7 OF 20

1 2

AB11
AB13
AB12
W12
W11
W10
W8
W7

BA9
BB9

AB7

AF13

1 2

CPU_XDP_TCLK <14>
CPU_XDP_TDI <14>
CPU_XDP_TDO <14>
CPU_XDP_TMS <14>
CPU_XDP_TRST# <14>

PCH_JTAG_TCK <14>
PCH_JTAG_TDI <14>
PCH_JTAG_TDO <14>
PCH_JTAG_TMS <14>

+1.0V_VCCSTG

CONTACTLESS_DET#

AUD_PWR_EN

SD_RCOMP

RC96 200_0402_1%

PCH_JTAG_TDO PCH_JTAG_TDI XDP_JTAGX

0.1U_0402_25V6

@ESD@

12

CC303

@

1 2

ESD request,Place near CPU side.

CPU@

D D

+1.0V_VCCST

RC79 49 .9_0402_1%@

RC80 1K_0402_5%

+1.0V_VCCSTG

RC83 1K_0402_5%

+3.3V_RUN

RC414 10K_ 0402_5%

RC413 10K_ 0402_5%

C C

B B

RC278 10K_ 0402_5%

RC272 10K_ 0402_5%

@

RC279 10 K_0402_5%

RC345 100K_0402_5%

RC292 10 K_0402_5%

+3.3V_ALW_PCH

RC346 10K_ 0402_5%

RC288 10K_0402_5%

H_CATERR#

12

H_THERMTRIP#

12

12

PROCHOT#

TOUCHPAD_INTR#

12

CAM_MIC_CBL_DET#

12

CONTACTLESS_DET#

12

TOUCH_SCREEN_PD#

12

AUD_PWR_EN

12

IR_CAM_DET#

12

HOST_SD_WP#

12

SIO_EXT_SMI#

12

KB_DET#

12

HDA_SYNC_R<30>

HDA_BIT_CLK_R<30>

HDA_SDOUT_R<30>

HDA_RST#_R<30>

Close to RC93

TOUCH_SCREEN_PD# don't move to RPC,

ME_FWP_PCH

HDA_BIT_CLK_R

12

PECI_EC<31>

PROCHOT#<31,46,49>

H_THERMTRIP#<20,32>

TOUCH_SCREEN_DET#<26>

1 2

RC92 33_0402_5%

1 2

RC93 33_0402_5%EMI@

1 2

RC94 33_0402_5%

1 2

RC223 1K_0402_5%

1 2

RC95 33_0402_5%

RF@

47P_0402_50V8J

CC27

1 2

RC84 499_0402_1%

XDP_OBS0_R<14>
XDP_OBS1_R<14>

@

T10

PAD~D

@

T11

PAD~D

TOUCH_SCREEN_PD#<26>
TOUCHPAD_INTR#<31,37>

12

12

RC88

49.9_0402_1%

IR_CAM_DET#<26>

KB_DET#<37>

SPKR<30>

RC89

HDA_SYNC
HDA_BIT_CLK
HDA_SDOUT

HDA_SDIN0<30>

HDA_RST#

PROCHOT#_R
H_THERMTRIP#

XDP_OBS2_R
XDP_OBS3_R

SIO_EXT_SMI#

TOUCHPAD_INTR#

CPU_POPIRCOMP
PCH_POPIRCOMP

EDRAM_OPIO_RCOMP

EOPIO_RCOMP

12

12

RC90

49.9_0402_1%

49.9_0402_1%

IR_CAM_DET#

KB_DET#

H_CATERR#

RC91

49.9_0402_1%

D63

A54
C65
C63

A65

C55
D55

B54
C56

A6

A7
BA5
AY5

AT16
AU16

H66
H65

UC1G

BA22

HDA_SYNC/I2S0_SFRM

AY22

HDA_BLK/I2S0_SCLK

BB22

HDA_SDO/I2S0_TXD

BA21

HDA_SDI0/I2S0_RXD

AY21

HDA_SDI1/I2S1_RXD

AW22

HDA_RST#/I2S1_SCLK

J5

GPP_D23/I2S_MCLK

AY20

I2S1_SFRM

AW20

I2S1_TXD

AK7

GPP_F1/I2S2_SFRM

AK6

GPP_F0/I2S2_SCLK

AK9

GPP_F2/I2S2_TXD

AK10

GPP_F3/I2S2_RXD

H5

GPP_D19/DMIC_CLK0

D7

GPP_D20/DMIC_DATA0

D8

GPP_D17/DMIC_CLK1

C8

GPP_D18/DMIC_DATA1

AW5

GPP_B14/SPKR

KBL-RU42_BGA1356

UC1D

CATERR#
PECI
PROCHOT#
THERMTRIP#
SKTOCC#

BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]

GPP_E3/CPU_GP0
GPP_E7/CPU_GP1
GPP_B3/CPU_GP2
GPP_B4/CPU_GP3

PROC_POPIRCOMP
PCH_OPIRCOMP
OPCE_RCOMP
OPC_RCOMP

KBL-RU42_BGA1356

CPU@

AUDIO

RF Request. Place near CPU side (Intel MOW)

+3.3V_ALW_PCH +3.3V_ALW_PCH

HDA_SDOUT

12

ENABLE
DISAB LE

SPKR

5

RC183 8.2K_0402_5%

@

TOP SWAP STRAP

A A

HIGH
LOW(DEFAULT)

Internal 20k PD

@

Flash Descriptor Security override

HIGH
LOW(DEFAULT)

12

RC187 4.7K_0402_5%

DISABLE

ENABLE

4

HDA_RST# HD A_SDIN0 HDA_SDOUT

1

2

CC331

RF@

2.2P_0402_50V8C

1 2

RC81 51_0402_5%

1 2

RC82 100_0402_5%

1 2

RC130 51_0402_5%

ME_FWP_PCHME_FWP

1 2

@

RC221 0_0402_5%

PT,ST pop RC222 and SW1; MP pop RC221

@

RC222

1K_0402_5%

1 2

ME_FWP<31>

0.1U_0402_25V6

@ESD@

12

CC305

ME_FWP_PCH

H_THERMTRIP#

0.1U_0402_25V6

@ESD@

12

CC312

@

SW1

1

A

2

B

3

C

4

G1

5

G2

SS3-CMFTQR9_3P

PROCHOT#

0.1U_0402_25V6

12

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document N umber Re v

Size Document N umber Re v

Size Document N umber Re v

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

Compal Electronics, Inc.

CPU (7/14)

CPU (7/14)

CPU (7/14)

LA-F312P

LA-F312P

LA-F312P

1

@ESD@

CC310

2.0

2.0

12 58Wednesday, December 20, 2017

12 58Wednesday, December 20, 2017

12 58Wednesday, December 20, 2017

2.0

5

D D

4

CFG[0..19]<14>

3

2

1

CFG[2][5][6][7] for SKYLAKE-H CPU CFG strap pin

12

RC113 10K_0402_1%

@

CFG0

RC112 10K_0402_1%

@

RC110 10K_0402_1%

@

12

12

Stall reset sequence

HIGH(DEFAULT )
LOW

C C

RC109 1K_0402_5%

eDP enable

HIGH(DEFAULT )
LOW

B B

No stall(Normal Operat i on)
sta ll

12

CFG4

Disa bled
Enabled

+1.0V_PRIM_XDP

RC114 49.9_0402_1%

RC115 1.5K_0402_5%

ITP_PMODE<14>

@

T16

PAD~D

@

T17

PAD~D

1 2

U42@

RC436 0_0402_5%

CFG_RCOMP

12

ITP_PMODE

12

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15

CFG16
CFG17

CFG18
CFG19

UC1S

E68

CFG[0]

B67

CFG[1]

D65

CFG[2]

D67

CFG[3]

E70

CFG[4]

C68

CFG[5]

D68

CFG[6]

C67

CFG[7]

F71

CFG[8]

G69

CFG[9]

F70

CFG[10]

G68

CFG[11]

H70

CFG[12]

G71

CFG[13]

H69

CFG[14]

G70

CFG[15]

E63

CFG[16]

F63

CFG[17]

E66

CFG[18]

F66

CFG[19]

E60

CFG_RCOMP

E8

ITP_PMODE

AY2

RSVD_AY2

AY1

RSVD_AY1

D1

RSVD_D1

D3

RSVD_D3

K46

RSVD_K46

K45

RSVD_K45

AL25

RSVD_AL25

AL27

RSVD_AL27

C71

RSVD_C71

B70

RSVD_B70

F60

RSVD_F60

A52

RSVD_A52

BA70

RSVD_TP_BA70

BA68

RSVD_TP_BA68

J71

RSVD_J71

J68

RSVD_J68

F65

VSS_F65

G65

VSS_G65

F61

RSVD_F61

E61

RSVD_E61

KBL-RU42_BGA1356

CPU@

KBL-R U4+2

RESERVED SIGNALS-1

Rev_0.1

RSVD_TP_BB68
RSVD_TP_BB69

RSVD_TP_AK13
RSVD_TP_AK12

RSVD_BB2
RSVD_BA3

RSVD_D5
RSVD_D4
RSVD_B2
RSVD_C2

RSVD_B3
RSVD_A3

RSVD_AW1

RSVD_E1
RSVD_E2

RSVD_BA4
RSVD_BB4

RSVD_A4
RSVD_C4

RSVD_A69
RSVD_B69

RSVD_AY3

RSVD_D71
RSVD_C70

RSVD_C54
RSVD_D54

VSS_AY71

ZVM#

RSVD_TP
RSVD_TP

MSM#

PROC_SELECT#

19 OF 20

UC1T

BB68
BB69

AK13
AK12

BB2
BA3

AU5

TP5

AT5

TP6

D5
D4
B2
C2

B3
A3

AW1

E1
E2

BA4
BB4

A4
C4

BB5

TP4

A69
B69

AY3

D71
C70

C54
D54

AY4

TP1

BB3

TP2

AY71
AR56

AW71
AW70

AP56
C64

@

T12

PAD~D

@

T13

PAD~D

@

T14

PAD~D

@

T15

PAD~D

@

T130

PAD~D

@

T126

PAD~D

@

T127

PAD~D

@

T113

PAD~D

@

T114

PAD~D

1 2

RC120 100K_0402_5%@

For Skylake , RC120 depop
For Cannonlake, RC120 pop

546765_546765_2014WW48_ Skylake_MOW_R ev_1_0

1/5 2014 WW52 MOW reserve to support
Cannonlake-U PCH compatibility

close UC1.U11/U12 and <400mil

1 2

RC313 0_0402_5%

@

+1.0V_VCCST

+VCC_1P8+1 .8V_PRIM

AW69
AW68

AU56

AW48

U12
U11

1

2

H11

CC222

@

1U_0402_6.3V6K

KBL-RU42_BGA1356

RSVD_AW69
RSVD_AW68
RSVD_AU56
RSVD_AW48

RSVD_U12
RSVD_U11
RSVD_H11

SPARE

Rev_0.1

RSVD_F6

RSVD_C11
RSVD_B11
RSVD_A11
RSVD_D12
RSVD_C12
RSVD_F52

20 OF 20

F6

C11
B11
A11
D12
C12
F52

KBL-R U4+2

CPU@

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.

5

4

3

2

Title

Size Document N umber Re v

Size Document N umber Re v

Size Document N umber Re v

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

Compal Electronics, Inc.

CPU (8/14)

CPU (8/14)

CPU (8/14)

LA-F312P

LA-F312P

LA-F312P

13 58Wednesday, December 20, 2017

13 58Wednesday, December 20, 2017

13 58Wednesday, December 20, 2017

1

2.0

2.0

2.0

+1.0V_PRIM

@

1 2

RC216 0_0603_5%

+1.0V_PRIM_XDP

0.1U_0201_10V6K

0.1U_0201_10V6K

@

CC28

1

1

2

2

D D

Place near
JXDP1

VCCST_PWRGD<11,31,32>

PCH_RSMRST#_AND<11,37>

+1.0VS_VCCIO

C C

+1.0V_VCCST

+3.3V_RUN

+1.0V_PRIM_XDP

5

+1.0V_PRIM_XDP

@

CC29

XDP_OBS0_R<12>
XDP_OBS1_R<12>

RC123 1K_0402_5%@

RC124CXDP@

PCH_SPI_DO_XDP<8>

SYS_PWROK<11,31>

RC132 150_0402_5%

RC218 150_0402_5%@

RC219 10K_0402_5%@

RC137 3K_0402_5%

RC138 51_0402_5%

@

RC239 0_0402_5%

CXDP@

RC240 0_0402_5%

CXDP@

RC5 need to close to JCPU1

1 2

1 2

1K_0402_5%

12

12

12

12

12

FIVR_EN
CFG0

RC217 0_0402_5%

@

RC126 1K_0402_5%@
RC128 0_0402_5%

CXDP@

RC129 0_0402_5%

@

DDR_XDP_WAN_S MBDAT<8,20>

DDR_XDP_WAN_S MBCLK<8,20>

FIVR_EN_R

FIVR_EN

FIVR_EN

XDP_DBRESET#

CPU_XDP_PREQ#

CPU_XDP_PREQ#<10>

CPU_XDP_PRDY#<10>

1 2
1 2

1 2
1 2
1 2
1 2

PCH_JTAG_TCK<12>

CPU_XDP_TCLK<12>

CPU XDP

H_VCCST_PWRGD_XD P

SIO_PWRBTN#<11,31>

CPU_XDP_PREQ#
CPU_XDP_PRDY#

RESET_OUT#_R

CPU_XDP_TCLK

+1.0V_PRIM_XDP

CFG0
CFG1

CFG2
CFG3

XDP_OBS0
XDP_OBS1

CFG4
CFG5

CFG6
CFG7

FIVR_EN_R

+3.3V_ALW_PCH

0.1U_0402_25V6

CC33@

4

XDP_PRSNT_PIN1

13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57

61

RC133

1.5K_0402_5%

1 2

CXDP@

PCH_SPI_DO_XDP

RESET_OUT#_R

12

CXDP@

1 2

RC121 0_0402_5%

1 2

RC122 0_0402_5%@

CONN@

JXDP1

JXT_FP270H-061G1AM

112
334
556
778
9910
111112
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
595960
61

GND62GND

2
4
6
8
10
12
14

14

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

40

42

42

44

44

46

46

48

48

50

50

52

52

54

54

56

56

58

58

60

63

CFG3

Place near JXDP1.48

XDP_DBRESET#

+1.0V_PRIM_XDP

CFG17
CFG16

CFG8
CFG9

CFG10
CFG11

CFG19
CFG18

CFG12
CFG13

CFG14
CFG15

ITP_PMODE
XDP_DBRESET#

TDO_XDP
TRST#_XDP
TDI_XDP
XDP_TMS

12

3

0.1U_0402_25V6

CXDP@

CC32

Place near JXDP1.41

CFG[0..19]<13>

CLK_ITPXDP_P_R <11>
CLK_ITPXDP_N_R <11>

ITP_PMODE <13>
XDP_DBRESET# <11>

PCH_SPI_DO2_XDP <8>

+3.3V_ALW_DSW

SIO_PWRBTN#

2

+3.3V_RUN

CC30

12

0.1U_0201_10V6K

TDO_XDP

TDI_XDP

XDP_TMS

TRST#_XDP

RUNPWROK<31>

1.5K_0402_5%

@

RC241

1 2

0.1U_0402_25V6

CC269

@

12

UC8

14

VCC

2

1A

1

1OE

5

2A

4

2OE

9

3A

10

3OE

12

4A

13

4OE

74CBTLV3126BQ_DHVQFN14_2P5X3

CPU_XDP_TMS

RC131 51_0402_5%

CPU_XDP_TDI

RC134 51_0402_5%

CPU_XDP_TDO

RC135 100_0402_5%

CPU_XDP_TRST#

RC136

@

CPU_XDP_TCLK

RC139 51_0402_5%

XDP_TMS

TDI_XDP

TDO_XDP

1 2

@

RC228 0_0402_5%

1 2

@

RC229 0_0402_5%

1 2

@

RC230 0_0402_5%

GND PAD

1 2

1 2

1 2

1 2

1 2

1B

2B

3B

4B

GND

1

3

6

8

11

7

15

51_0402_5%

PCH_JTAG_TMS <12>

PCH_JTAG_TDI <12>

PCH_JTAG_TDO <12>

CPU_XDP_TDO <12>

CPU_XDP_TDI <12>

CPU_XDP_TMS <12>

CPU_XDP_TRST# <12>

+1.0V_VCCSTG

B B

A A

Place near JXDP1.47

TDO_XDP H_VCCST_PWRGD_XD P CPU_XDP_TRST#

0.1U_0402_25V6

@ESD@

12

CC306

ESD request,Place near JXDP1 side. ES D request,Place near UC8 side.

0.1U_0402_25V6

@ESD@

12

CC307

0.1U_0402_25V6

@ESD@

12

CC308

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.

5

4

3

2

Title

Size Document N umber Re v

Size Document N umber Re v

Size Document N umber Re v

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

Compal Electronics, Inc.

CPU (9/14)

CPU (9/14)

CPU (9/14)

LA-F312P

LA-F312P

LA-F312P

14 58Wednesday, December 20, 2017

14 58Wednesday, December 20, 2017

14 58Wednesday, December 20, 2017

1

2.0

2.0

2.0

5

4

3

2

1

+VCC_CORE: 0.3~1.35V

D D

@

T122

PAD~D

@

T123

PAD~D

C C

+VCC_CORE +VCC_CORE

+VCC_CORE_G0

+VCC_CORE_G1

UC1L

A30

VCC_A30

A34

VCC_A34

A39

VCC_A39

A44

VCC_A44

AK33

VCC_AK33

AK35

VCC_AK35

AK37

VCC_AK37

AK38

VCC_AK38

AK40

VCC_AK40

AL33

VCC_AL33

AL37

VCC_AL37

AL40

VCC_AL40

AM32

VCC_AM32

AM33

VCC_AM33

AM35

VCC_AM35

AM37

VCC_AM37

AM38

VCC_AM38

G30

VCC_G30

K32

RSVD

AK32

RSVD

AB62

VCCOPC_AB62

P62

VCCOPC_P62

V62

VCCOPC_V62

H63

VCC_OPC_1P8_H63

G61

VCC_OPC_1P8_G61

AC63

VCCOPC_SENSE

AE63

VSSOPC_SENSE

AE62

VCCEOPIO

AG62

VCCEOPIO

AL63

VCCEOPIO_SENSE

AJ62

VSSEOPIO_SENSE

KBL-RU42_BGA1356

CPU@

KBL-R U4+2

CPU POWER 1 OF 4

Rev_0.1

VCC_G32
VCC_G33
VCC_G35
VCC_G37
VCC_G38
VCC_G40
VCC_G42
VCC_J30
VCC_J33
VCC_J37
VCC_J40
VCC_K33
VCC_K35
VCC_K37
VCC_K38
VCC_K40
VCC_K42
VCC_K43

VCC_SENSE
VSS_SENSE

VIDALERT#

VIDSCK

VIDSOUT

VCCSTG_G20

12 OF 20

G32
G33
G35
G37
G38
G40
G42
J30
J33
J37
J40
K33
K35
K37
K38
K40
K42
K43

E32
E33

B63
A63
D64

G20

VCCSENSE
VSSSENSE

H_CPU_SVIDALRT#
VIDSCLK

VIDSCLK < 46>

VIDSOUT

+1.0V_VCCSTG_R

+VCC_CORE

RC140

100_0402_1%

1 2

12

RC141

100_0402_1%

@

1 2

RC143 0_0603_5%

VCCSENSE <46>
VSSSENSE <46>

+1.0V_VCCSTG

VIDSCLK

RF Request

1 2

CC321@RF@ 33P_0402_50V8J

Place close CPU side

PSC(Primary side cap) : Place as close to the package as possible
BSC(Backside cap) : Place on secondary side, underneath the package

Component placement order:
Package edge > 0402 caps > 0805 caps > Bulk caps >Power source

B B

SVID ALERT

VIDALERT_N<46>

SVID DATA

A A

VIDSOUT<46>

+1.0V_VCCST

1 2

+1.0V_VCCST

1 2

56_0402_1%

RC152

100_0402_1%

RC157

CAD Note: Place the PU resistors close to CPU
RC204 close to CPU 300 - 1500mils

H_CPU_SVIDALRT#

12

RC153220_0402_5%

CAD Note: Place the PU resistors close to CPU
RC208close to CPU 300 - 1500mils

VIDSOUT

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.

5

4

3

2

Title

Size Document N umber Re v

Size Document N umber Re v

Size Document N umber Re v

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

Compal Electronics, Inc.

CPU (10/14)

CPU (10/14)

CPU (10/14)

LA-F312P

LA-F312P

LA-F312P

15 58Wednesday, December 20, 2017

15 58Wednesday, December 20, 2017

15 58Wednesday, December 20, 2017

1

2.0

2.0

2.0

5

4

3

2

1

+VCCGT: 0.3~1.35V
+VCCGTX : 0.3~1.35V

KBL-R 4+2 and KBL-U 2+2&2+3e opt i on ( pl ace on po wer page)

+VCC_GT_+VCC_CORE

KBL-R U4+2

CPU@

D D

+VCC_GT

+VCC_GT

C C

VCC_GT_SENSE<46>
VSS_GT_SENSE<46>

B B

1 2

@

RC437 0_0402_5%

+VCC_GT

RC161

100_0402_1%

1 2

VCC_GT_SENSE
VSS_GT_SENSE

12

RC163

100_0402_1%

UC1M

KBL-U / KBL-R U4+2

A48

VCCGT/VCCCORE_5

A53

VCCGT/VCCCORE_6

J43

VCCGT/VCCCORE_44

J45

VCCGT/VCCCORE_45

J46

VCCGT/VCCCORE_46

J48

VCCGT/VCCCORE_47

J50

VCCGT/VCCCORE_48

J52

VCCGT/VCCCORE_49

K48

VCCGT/VCCCORE_57

K50

VCCGT/VCCCORE_58

K52

VCCGT/RSVD_6

A58

VCCGT

A62

VCCGT

A66

VCCGT

AA63

VCCGT

AA64

VCCGT

AA66

VCCGT

AA67

VCCGT

AA69

VCCGT

AA70

VCCGT

AA71

VCCGT

AC64

VCCGT

AC65

VCCGT

AC66

VCCGT

AC67

VCCGT

AC68

VCCGT

AC69

VCCGT

AC70

VCCGT

AC71

VCCGT

J53

VCCGT

J55

VCCGT

J56

VCCGT

J58

VCCGT

J60

VCCGT

K53

VCCGT

K55

VCCGT

K56

VCCGT

K58

VCCGT

K60

VCCGT

L62

VCCGT

L63

VCCGT

L64

VCCGT

L65

VCCGT

L66

VCCGT

L67

VCCGT

L68

VCCGT

L69

VCCGT

L70

VCCGT

L71

VCCGT

M62

VCCGT

N63

VCCGT

N64

VCCGT

N66

VCCGT

N67

VCCGT

N69

VCCGT

J70

VCCGT_SENSE

J69

VSSGT_SENSE

KBL-RU42_BGA1356

CPU POWER 2 OF 4

KBL-U / KBL-R U4+2

VCCGTX_AK42/VCCCORE_12
VCCGTX_AK43/VCCCORE_13
VCCGTX_AK45/VCCCORE_14
VCCGTX_AK46/VCCCORE_15
VCCGTX_AK48/VCCCORE_16
VCCGTX_AK50/VCCCORE_17

VCCGTX_AL43/VCCCORE_21
VCCGTX_AL46/VCCCORE_22

VCCGTX_AL50/VCCCORE_23
VCCGTX_AM48/VCCCORE_29
VCCGTX_AM50/VCCCORE_30
VCCGTX_AM52/VCCCORE_31

VCCGTX_AK52/RSVD_5

Rev_0.1

VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT

VCCGTX_AK53
VCCGTX_AK55
VCCGTX_AK56
VCCGTX_AK58
VCCGTX_AK60
VCCGTX_AK70

VCCGTX_AL53
VCCGTX_AL56

VCCGTX_AL60
VCCGTX_AM53
VCCGTX_AM56
VCCGTX_AM58
VCCGTX_AU58
VCCGTX_AU63
VCCGTX_BB57
VCCGTX_BB66

VCCGTX_SENSE

VSSGTX_SENSE

13 OF 20

N70
N71
R63
R64
R65
R66
R67
R68
R69
R70
R71
T62
U65
U68
U71
W63
W64
W65
W66
W67
W68
W69
W70
W71
Y62

AK42
AK43
AK45
AK46
AK48
AK50
AL43
AL46
AL50
AM48
AM50
AM52
AK52

AK53
AK55
AK56
AK58
AK60
AK70
AL53
AL56
AL60
AM53
AM56
AM58
AU58
AU63
BB57
BB66

AK62
AL61

+VCC_GT

Follow KBL-R_U42_Processor_Line_BGA1356_Ballout_Rev1p0

KBL-R 4+2 and KBL-U 2+2&2+3e opt i on ( pl ace on po wer page)

+VCC_GT_+VCC_CORE

1 2

@

RC438 0_0402_5%

+VCC_GT

+VCC_GTUS

Reserve for soldering

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.

5

4

3

2

Title

Size Document N umber Re v

Size Document N umber Re v

Size Document N umber Re v

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

Compal Electronics, Inc.

CPU (11/14)

CPU (11/14)

CPU (11/14)

LA-F312P

LA-F312P

LA-F312P

16 58Wednesday, December 20, 2017

16 58Wednesday, December 20, 2017

16 58Wednesday, December 20, 2017

1

2.0

2.0

2.0

5

4

3

2

1

+5V_ALW

CZ104

@
1 2

4

O

@

1

2

CC253

1U_0402_6.3V6K

UZ34

1

2

+1.2V_MEM

1

2

CC250

1U_0402_6.3V6K

@

RZ119 0_0 402_5%

UZ26

1

VIN1

2

VIN2

7

VIN thermal

3

VBIAS

4

ON

TPS22961DNYR_WSON8

CC251

1U_0402_6.3V6K

SIO_SLP_S0#

SIO_SLP_S3#

AND

1 2

+VCCPLL_OC source

+1.2V_MEM+1.2V_MEM_CPUCLK

1 2

@

RC231 0_0402_5%

D D

PSC

1

1

2

1

CC177

CC176

2

2

10U_0402_6.3V6M

10U_0402_6.3V6M

PSC

22U_0603_6.3V6M

CC294

1

1

2

2

+1.0V_VCCST

C C

B B

PSC

1

2

CC195

1U_0402_6.3V6K

VDDQ: 8.45A

1

CC179

CC178

2

10U_0402_6.3V6M

10U_0402_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

CC296

CC295

1

2

+1.0V_VCCSTG

BSC

1

2

@

CC199

PSC

1

CC297

2

1U_0402_6.3V6K

+1.2V_MEM_CPUCLK

10U_0402_6.3V6M

+VCC_SFR_OC

1

2

CC288

+1.0V_VCCST source

+1.2V_MEM

1

2

CC322

1U_0402_6.3V6K

RF@

2.2P_0402_50V8C

RF Request

UC1N

AU23

VDDQ_AU23

AU28

VDDQ_AU28

AU35

VDDQ_AU35

AU42

VDDQ_AU42

BB23

VDDQ_BB23

BB32

VDDQ_BB32

BB41

VDDQ_BB41

BB47

VDDQ_BB47

BB51

VDDQ_BB51

AM40

VDDQC

A18

VCCST

A22

VCCSTG_A22

AL23

VCCPLL_OC

K20

VCCPLL_K20

K21

VCCPLL_K21

KBL-RU42_BGA1356

+1.0V_VCCST

1

2

12

CZ102 1U_0402_6.3V6K

VCCSTG_EN

AK28
AK30
AL30
AL42
AM28
AM30
AM42

AK23
AK25
G23
G25
G27
G28
J22
J23
J27
K23
K25
K27
K28
K30

AM23
AM22

H21
H20

1 2

+1.0VS_VCCIO

VCCIO_SENSE
VSSIO_SENSE

+VCC_SA

+1.0VS_VCCIO

12

RC166

100_0402_1%

VSA_SEN- <46>
VSA_SEN+ <46>

1 2

12

RC165

100_0402_1%

VCCIO_SENSE <44>
VSSIO_SENSE <44>

RC167

100_0402_1%

PCH_PRIM_EN<11,39,43,44,45>

SIO_SLP_S4#<11,17,31,42,45>

KBL-R U4+2

CPU@

CPU POWER 3 OF 4

Rev_0.1

VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO

VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA

VCCIO_SENSE
VSSIO_SENSE

VSSSA_SENSE

VCCSA_SENSE

14 OF 20

+VCC_SA

RC168 100_0402_1%

PSC

U22@

CC202

@

1U_0402_6.3V6K

22U_0402_6.3V6M

CC202

1

CC341

2

U42@

22U_0603_6.3V6M

1 2

@

RZ120 0_0402_5%

+3.3V_ALW

5

0.1U_0402_10V7K

1

P

B

2

A

G

3

TC7SH08FU_SSOP5~D

+1.0VS_VCCIO

PSC

1

2

CC252

1U_0402_6.3V6K

+1.0V_VCCSTG source

+VCC_SFR_OC

6

VOUT

5

GND

S0

HIGH

HIGH

HIGH LOW LOW

S0Ix

LOW

HIGH

S3

LOW

LOW

1 2

CZ103 0.1U_0201_10V6K

+1.0V_VCCST+1.0V_VCC STG

1 2

RZ151 0_0603_5%

@

+1.0V_PRIM

12

CZ100 1U_0402_6.3V6K

SIO_SLP_S4#<11,17,31,42,45>

A A

5

+1.0V_PRIM

+5V_ALW

UZ21

1

VIN1

2

VIN2

7

VIN thermal

3

VBIAS

4

ON

TPS22961DNYR_WSON8

4.4mohm /6A
TR=12.5us@Vin=1.05V

VOUT

GND

+1.0V_VCCST_C

6

5

4

PJP1

12

PAD-OPEN1x1m

1 2

CZ101 0.1U_0201_10V6K

+1.0V_VCCST

SIO_SLP_S0#<11,33,44>

RUN_ON<31,32,39,44>

TC7SH08FU_SSOP5~D

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.

3

12

CZ105 1U_0402_6.3V6K

@

+5V_ALW

+3.3V_ALW

5

1

P

B

O

2

A

G

UZ35

3

1 2

RZ320 0_0402_5%

4

VCCSTG_EN

1
2

7

3

4

UZ19

VIN1
VIN2

VIN thermal

VBIAS

ON

TPS22961DNYR_WSON8

4.4mohm /6A
TR=12.5us@Vin=1.05V

VOUT

GND

2

12

PJP2
PAD-OPEN1x1m

+1.0V_VCCSTG_C

6

5

DELL CONFIDENTIAL/PROPRIETARY

pop option with UZ19

1 2

CZ106 0.1U_0201_10V6K

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document N umber Re v

Size Document N umber Re v

Size Document N umber Re v

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

Compal Electronics, Inc.

CPU (12/14)

CPU (12/14)

CPU (12/14)

LA-F312P

LA-F312P

LA-F312P

17 58Wednesday, December 20, 2017

17 58Wednesday, December 20, 2017

17 58Wednesday, December 20, 2017

1

2.0

2.0

2.0

5

+1.0V_PRIM

Imax : 2.57A

@

1 2

D D

C C

B B

RC299 0_0603_5%

@

1 2

RC300 0_0402_5%

@

1 2

RC301 0_0402_5%

@

1 2

RC302 0_0402_5%

@

1 2

RC303 0_0402_5%

+1.8V_PRIM

@

1 2

RC304 0_0402_5%

@

1 2

RC234 0_0402_5%

+3.3V_ALW_PCH

@

1 2

RC235 0_0402_5%

1 2

RC211 0_0402_5%

LPC@

+1.8V_PRIM

@ESPI@

1 2

RC212 0_0402_5%

@

1 2

RC305 0_0402_5%

@

1 2

RC306 0_0402_5%

@

1 2

RC307 0_0402_5%

@

1 2

RC308 0_0402_5%

+3.3V_ALW_PCH

1 2

LC1 BLM15GA750SN1D_2P

1

CC215

2

@

1U_0402_6.3V6K

+1.0V_MPHYAON

+1.0V_CLK6

+1.0V_DTS

+1.0V_CLK1

+1.0V_CLK3

+1.8V_PGPPF

+3.3V_1.8V_PGPPG

+3.3V_1.8V_PGPPA

+3.3V_PGPPB+3.3V_ALW_PCH

+3.3V_PGPPC

+3.3V_PGPPD

+3.3V_PGPPE

8/28 schematic review

close UC1.AF20 and <400mil

+3.3V_1.8V_ESPI

PJP4

1 2

PAD-OPEN1x1m

Must be +1.8V for eSPI I/F

+3.3V_VCCHDA

1

CC313

2

0.1U_0201_10V6K

close UC1.AJ19 and <400mil

A A

@

1 2

RC173 0_0402_5%

close UC1.N20 and <100mil

+1.0V_CLK4+1.0V_PRIM

1

CC226

2

@

47U_0805_6.3V6M

5

close UC1.AL1 and <120mil

+1.0V_MPHYAON

1

2

CC203

1U_0402_6.3V6K

+1.0V_MPHYGT

close UC1.N15 and CC210 <400mil, CC211 <120mil

1

1

CC210

2

2

@

47U_0805_6.3V6M

+1.0V_SRAM

1

CC217

2

@

1U_0402_6.3V6K

close UC1.K15, UC1.L15 and <100mil

@

1 2

RC169 0_0603_5%

1

2

CC281

@

0.1U_0201_10V6K

+1.0V_PRIM

1 2

LC2 BLM 15GA750SN1D_2P

1

CC225

2

@

47U_0805_6.3V6M

close UC1.V15 and <100mil

@

RC170 0_0402_5%

close UC1.K19 and <100mil

1

2

CC204

1U_0402_6.3V6K

CC211

1U_0402_6.3V6K

+1.0V_APLLEBB

1

2

1 2

4

+1.0V_PRIM_CORE+1.0VO_DSW

1

2

close UC1.AB19 and <400milclose UC1.K17 and <120mil

CC205

@

1U_0402_6.3V6K

close UC1.AF18 and <400mil

+1.0V_AMPHYPLL

+1.0V_APLL

+1.0V_PRIM

+3.3V_ALW_DSW

+3.3V_VCCHDA

+3.3V_SPI

+3.3V_ALW_PCH

+1.0V_PRIM

close UC1.N18 and <120mil

CC218

1U_0402_6.3V6K

+1.0V_AMPHYPLL+1.0V_MPHYGT

close UC1.K15 and <120mil

1

1

CC219

2

2

CC264

@

@

1U_0402_6.3V6K

47U_0805_6.3V6M

+1.0V_APLL

1

CC314

2

+1.0V_CLK2+1.0V_PRIM

1

CC220

2

@

47U_0805_6.3V6M

4

+1.0V_PRIM

1

CC206

2

@

0.1U_0201_10V6K

1U_0402_6.3V6K

No Support DS3

3

PCH PWR

UC1O

AB19

VCCPRIM_1P0

AB20

VCCPRIM_1P0

P18

VCCPRIM_1P0

AF18

VCCPRIM_CORE

AF19

VCCPRIM_CORE

V20

VCCPRIM_CORE

V21

VCCPRIM_CORE

AL1

DCPDSW_1P0

K17

VCCMPHYAON_1P0

L1

VCCMPHYAON_1P0

N15

VCCMPHYGT_1P0_N15

N16

VCCMPHYGT_1P0_N16

N17

VCCMPHYGT_1P0_N17

P15

VCCMPHYGT_1P0_P15

P16

VCCMPHYGT_1P0_P16

K15

VCCAMPHYPLL_1P0

L15

VCCAMPHYPLL_1P0

V15

VCCAPLL_1P0

AB17

VCCPRIM_1P0_AB17

Y18

VCCPRIM_1P0_Y18

AD17

VCCDSW_3P3_AD17

AD18

VCCDSW_3P3_AD18

AJ17

VCCDSW_3P3_AJ17

AJ19

VCCHDA

AJ16

VCCSPI

AF20

VCCSRAM_1P0

AF21

VCCSRAM_1P0

T19

VCCSRAM_1P0

T20

VCCSRAM_1P0

AJ21

VCCPRIM_3P3_AJ21

AK20

VCCPRIM_1P0_AK20

N18

VCCAPLLEBB_1P0

KBL-RU42_BGA1356

+3.3V_ALW_DSW

22U_0603_6.3V6M

@

CC279

1

2

Support DS3

'V' mean POP, 'X' mean DE-POP

KBL-R U4+2

CPU POWER 4 OF 4

VCCPRIM_3P3_V19

VCCPRIM_1P0_T1

VCCATS_1P8

VCCRTCPRIM_3P3

VCCRTC_AK19
VCCRTC_BB14

GPP_B0/CORE_VID0
GPP_B1/CORE_VID1

1 2

RC440 0_0402_5%

NDS3@

1 2

RC214 0_0402_5%

@

1 2

@DS3@

RC439 0_0402_5%

22U_0603_6.3V6M

@

CC280

1

2

RC439

RC440RE5 36RC215RC44 1RC442

V V V

X

V V V

X X

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.

3

X

Rev_0.1

VCCPGPPA
VCCPGPPB
VCCPGPPC
VCCPGPPD
VCCPGPPE

VCCPGPPF

VCCPGPPG

DCPRTC

VCCCLK1

VCCCLK2

VCCCLK3

VCCCLK4

VCCCLK5

VCCCLK6

15 OF 20

+3.3V_ALW_PCH

+3.3V_ALW_DSW_R

X

X

close UC1.AG15 and <120mil

Must be + 1.8V

AK15
AG15
Y16
Y15
T16
AF16
AD15

V19

T1

AA1

AK17

AK19
BB14

BB10

A14

K19

L21

N20

L19

A10

AN11
AN13

+3.3V_1.8V_PGPPA

+3.3V_PGPPD

+1.8V_PGPPF
+3.3V_1.8V_PGPPG

+1.0V_DTS

+3.3V_ALW_PCH

close UC1.AK19 and <120mil

+DCPRTC

close UC1.BB10 and <120mil

+1.0V_CLK1

+1.0V_CLK2

+1.0V_CLK3

+1.0V_CLK4

+1.0V_CLK5

CORE_VID0 <44>
CORE_VID1 <44>

Take care!!! Note1 on Page 19

+3.3V_ALW

QC7

DS3@

LP2301ALT1G_SOT23-3

123

D

S

499K_0402_1%

12

RC432

G

0.1U_0402_25V6K

49.9K_0402_1%

DS3@

12

L2N7002WT1G_SC-70-3

RC433

12

@

CC340

13

D

QC6

DS3@

2

G

S

2

close UC1.Y16 a nd <400mil

+3.3V_PGPPB

+3.3V_PGPPC

1

1

CC265

2

@

2

1U_0402_6.3V6K

close UC1.AA1 and <400mil

+RTC_CELL_PCH

1

2

CC214

0.1U_0201_10V6K

+1.0V_CLK6

1

CC216

2

@

close UC1.L19 and <100mil

DS3@

100K_0402_5%

RC431

DS3@

1 2

VCCDSW_EN_GPIO <11>

2

+3.3V_PGPPE

close UC1.T16 a nd <400mil

1

CC207

@

1U_0402_6.3V6K

1

2

CC270

CC208

2

@

1U_0402_6.3V6K

1

2

CC213

1U_0402_6.3V6K

0.1U_0201_10V6K

close UC1.A10 and <120mil

1U_0402_6.3V6K

@

1 2

RC171 0_0402_5%

+1.0V_MPHYGT source

561280_561280_KBL_UY_PDG_Rev0p9 :
MPHY has defeature

DELL CONFIDENTIAL/PROPRIETARY

1

+1.0V_MPHYGT

+1.0V_SRAM

+1.0V_APLLEBB

close UC1.AD15 and <400mil

1

CC326

2

1U_0402_6.3V6K

+1.8V_PRIM

1

2

@

RC309 0_0603_5%

@

RC310 0_0603_5%

+3.3V_ALW_PCH

1

CC209

2

@

1U_0402_6.3V6K

close UC1.V19 and <120mil

CC212

1U_0402_6.3V6K

1 2

1 2

+3.3V_1.8V_PGPPG

RF Request

+1.0V_APLL +3.3V_VCCHDA +1.0V_APLLEBB

1

1

2

2

+1.0V_CLK5+1.0V_PRIM

1

CC221

2

@

47U_0805_6.3V6M

PJP3

@

1 2

PAD-OPEN1x3m

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document N umber Re v

Size Document N umber Re v

Size Document N umber Re v

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

Compal Electronics, Inc.

CPU (13/14)

CPU (13/14)

CPU (13/14)

LA-F312P

LA-F312P

LA-F312P

CC323

RF@

2.2P_0402_50V8C

+3.3V_ALW_PCH

1

CC223

2

0.1U_0201_10V6K

+1.0V_MPHYGT+1.0V_PRIM

1

CC324

RF@

close UC1.AK17 and <120mil

1

2

1

2

CC325

2.2P_0402_50V8C

CC224

RF@

2.2P_0402_50V8C

1U_0402_6.3V6K

18 58Wednesday, December 20, 2017

18 58Wednesday, December 20, 2017

18 58Wednesday, December 20, 2017

2.0

2.0

2.0

5

4

3

2

1

Note1: VCCPRIM_CORE Implementat i on wit h PC H C ORE_VI D Reco mmenda t i on

CPU@

KBL-R U4+2

UC1P

A5

VSS

A67

VSS

A70

VSS

AA2

D D

C C

B B

VSS

AA4

VSS

AA65

VSS

AA68

VSS

AB15

VSS

AB16

VSS

AB18

VSS

AB21

VSS

AB8

VSS

AD13

VSS

AD16

VSS

AD19

VSS

AD20

VSS

AD21

VSS

AD62

VSS

AD8

VSS

AE64

VSS

AE65

VSS

AE66

VSS

AE67

VSS

AE68

VSS

AE69

VSS

AF1

VSS

AF10

VSS

AF15

VSS

AF17

VSS

AF2

VSS

AF4

VSS

AF63

VSS

AG16

VSS

AG17

VSS

AG18

VSS

AG19

VSS

AG20

VSS

AG21

VSS

AG71

VSS

AH13

VSS

AH6

VSS

AH63

VSS

AH64

VSS

AH67

VSS

AJ15

VSS

AJ18

VSS

AJ20

VSS

AJ4

VSS

AK11

VSS

AK16

VSS

AK18

VSS

AK21

VSS

AK22

VSS

AK27

VSS

AK63

VSS

AK68

VSS

AK69

VSS

AK8

VSS

AL2

VSS

AL28

VSS

AL32

VSS

AL35

VSS

AL38

VSS

AL4

VSS

AL45

VSS

AL48

VSS

AL52

VSS

AL55

VSS

AL58

VSS

AL64

VSS

KBL-RU42_BGA1356

GND 1 OF 3

16 OF 20

Rev_0.1

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AL65
AL66
AM13
AM21
AM25
AM27
AM43
AM45
AM46
AM55
AM60
AM61
AM68
AM71
AM8
AN20
AN23
AN28
AN30
AN32
AN33
AN35
AN37
AN38
AN40
AN42
AN58
AN63
AP10
AP18
AP20
AP23
AP28
AP32
AP35
AP38
AP42
AP58
AP63
AP68
AP70
AR11
AR15
AR16
AR20
AR23
AR28
AR35
AR42
AR43
AR45
AR46
AR48
AR5
AR50
AR52
AR53
AR55
AR58
AR63
AR8
AT2
AT20
AT23
AT28
AT35
AT4
AT42
AT56
AT58

CPU@

UC1Q

AT63
AT68

AT71
AU10
AU15
AU20
AU32
AU38

AV1
AV68
AV69
AV70
AV71

AW10
AW12
AW14
AW16
AW18
AW21
AW23
AW26
AW28
AW30
AW32
AW34
AW36
AW38
AW41
AW43
AW45
AW47
AW49
AW51
AW53
AW55
AW57

AW6
AW60
AW62
AW64
AW66

AW8

AY66

B10
B14
B18
B22
B30
B34
B39
B44
B48
B53
B58
B62
B66
B71

BA1
BA10
BA14
BA18

BA2
BA23
BA28
BA32
BA36

F68

BA45

KBL-RU42_BGA1356

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

KBL-R U4+2

GND 2 OF 3

17 OF 20

Rev_0.1

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

BA49
BA53
BA57
BA6
BA62
BA66
BA71
BB18
BB26
BB30
BB34
BB38
BB43
BB55
BB6
BB60
BB64
BB67
BB70
C1
C25
C5
D10
D11
D14
D18
D22
D25
D26
D30
D34
D39
D44
D45
D47
D48
D53
D58
D6
D62
D66
D69
E11
E15
E18
E21
E46
E50
E53
E56
E6
E65
E71
F1
F13
F2
F22
F23
F27
F28
F32
F33
F35
F37
F38
F4
F40
F42
BA41

CPU@

UC1R

F8

VSS

G10

VSS

G22

VSS

G43

VSS

G45

VSS

G48

VSS

G5

VSS

G52

VSS

G55

VSS

G58

VSS

G6

VSS

G60

VSS

G63

VSS

G66

VSS

H15

VSS

H18

VSS

H71

VSS

J11

VSS

J13

VSS

J25

VSS

J28

VSS

J32

VSS

J35

VSS

J38

VSS

J42

VSS

J8

VSS

K16

VSS

K18

VSS

K22

VSS

K61

VSS

K63

VSS

K64

VSS

K65

VSS

K66

VSS

K67

VSS

K68

VSS

K70

VSS

K71

VSS

L11

VSS

L16

VSS

L17

VSS

KBL-RU42_BGA1356

KBL-R U4+2

GND 3 OF 3

18 OF 20

Rev_0.1

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

L18
L2
L20
L4
L8
N10
N13
N19
N21
N6
N65
N68
P17
P19
P20
P21
R13
R6
T15
T17
T18
T2
T21
T4
U10
U63
U64
U66
U67
U69
U70
V16
V17
V18
W13
W6
W9
Y17
Y19
Y20
Y21

R1: PR408,PR411 ; R2: PR417,PR418 ; R3,PR419,PR420 ; R4: PR423 ; R5: PR424

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.

5

4

3

2

Title

Size Document N umber Re v

Size Document N umber Re v

Size Document N umber Re v

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

Compal Electronics, Inc.

CPU (14/14)

CPU (14/14)

CPU (14/14)

LA-F312P

LA-F312P

LA-F312P

19 58Wednesday, December 20, 2017

19 58Wednesday, December 20, 2017

19 58Wednesday, December 20, 2017

1

2.0

2.0

2.0

5

4

3

2

1

For DDR4

DDR_A_DQS#[0..7]<7>

DDR_A_D[0..63]<7>

DDR_A_DQS[0..7]<7>

DDR_A_MA[0..16]<7>

Layout Note:

D D

C C

B B

A A

Place near JDIMM1

+1.2V_MEM

10U_0603_10V6M

10U_0603_10V6M

CD1

12

12

+1.2V_MEM

1U_0402_6.3V6K

1U_0402_6.3V6K

12

12

CD9

+0.6V_DDR_VTT

12

DIMM Select

SA01SA1

DIMM1

*

DIMM2

DIMM3

DIMM4

10U_0603_10V6M

CD2

12

1U_0402_6.3V6K

12

CD10

Layout Note:
Place near
JDIMM1.258

10U_0603_10V6M

CD22

0

1

0

1

10U_0603_10V6M

10U_0603_10V6M

10U_0603_10V6M

10U_0603_10V6M

10U_0603_10V6M

330U_D3_2.5VY_R6M

@

12

CD4

CD5

CD3

12

1U_0402_6.3V6K

12

CD11

1U_0402_6.3V6K

CD23

1

2

0

0

1

CD6

12

12

12

1U_0402_6.3V6K

1U_0402_6.3V6K

12

CD12

1

2

SA2

0

0

0

0

1U_0402_6.3V6K

12

12

CD13

CD14

1U_0402_6.3V6K

CD24

12

RD4

@

0_0402_5%

12

@

RD5

0_0402_5%

CD17

CD7

CD8

12

+

+2.5V_MEM

1U_0402_6.3V6K

1U_0402_6.3V6K

10U_0603_10V6M

CD19

12

@

1

2

1

2

RD10
0_0603_5%

2.2U_0402_6.3V6M

CD27

10U_0603_10V6M

1

CD20

CD21

2

+3.3V_RUN_DIMM1

0.1U_0201_10V6K

CD28

1

2

DDR_A_CKE0<7>

DDR_A_BG1<7>
DDR_A_BG0<7>

DDR_A_CLK0<7>
DDR_A_CLK#0<7>

DDR_A_PARITY<7>

DDR_A_BA1<7>

DDR_A_CS#0<7>

DDR_A_MA14<7>

DDR_A_ODT0<7>

DDR_A_CS#1<7>

DDR_A_ODT1<7>

T51PAD~D

@

DDR_XDP_WAN_SMBCLK<8,14>

1U_0402_6.3V6K

12

CD16

CD15

12

RD6

@

0_0402_5%

12

@

RD7

0_0402_5%

+DDR_VREF_A_CA

1

2

+3.3V_RUN+3.3V_RUN+3.3V_RUN

12

RD8

@

0_0402_5%

DIMM1_SA0
DIMM1_SA1
DIMM1_SA2

12

@

RD9

0_0402_5%

1

1

CD18

2

2

0.1U_0402_10V6K

2.2U_0402_6.3V6M

@

1

CD26

CD25

2

+3.3V_RUN

JDIMM1 REV Type H=9.2

JDIMM1

DDR_A_D4

DDR_A_D0

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D2

DDR_A_D6

DDR_A_D9

DDR_A_D8

DDR_A_D10

DDR_A_D14

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D19

DDR_A_D23

DDR_A_D28

DDR_A_D24

DDR_A_D26 DDR_A_D27

DDR_A_D30 DDR_A_D31

DDR_A_CKE0

DDR_A_BG1
DDR_A_BG0

DDR_A_MA12
DDR_A_MA9

DDR_A_MA8
DDR_A_MA6

DDR_A_MA3
DDR_A_MA1

DDR_A_CLK0
DDR_A_CLK#0

DDR_A_PARITY

DDR_A_BA1

DDR_A_CS#0
DDR_A_MA14

DDR_A_ODT0
DDR_A_CS#1

DDR_A_ODT1

DDR_A_D32

DDR_A_D36

DDR_A_DQS#4
DDR_A_DQS4

DDR_A_D35

DDR_A_D34

DDR_A_D40

DDR_A_D44

DDR_A_D42 DDR_A_D46

DDR_A_D47 DDR_A_D43

DDR_A_D52

DDR_A_D48

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D55

DDR_A_D51

DDR_A_D59

DDR_A_D58

DDR_A_D62

DDR_A_D63

+3.3V_RUN_DIMM1

1

VSS1

3

DQ5

5

VSS3

7

DQ1

9

VSS5
DQS0_c11DM0_n/DBI0_n

13

DQS0_t

15

VSS8

17

DQ7

19

VSS10

21

DQ3

23

VSS12

25

DQ13

27

VSS14

29

DQ9

31

VSS16

33

DM1_n/DBI_n

35

VSS17

37

DQ15

39

VSS19

41

DQ10

43

VSS21

45

DQ21

47

VSS23

49

DQ17

51

VSS25
DQS2_c53DM2_n/DBI2_n

55

DQS2_t

57

VSS28

59

DQ23

61

VSS30

63

DQ19

65

VSS32

67

DQ29

69

VSS34

71

DQ25

73

VSS36
DM3_n/DBI3_n75DQS3_t

77

VSS37

79

DQ30

81

VSS39

83

DQ26

85

VSS41

87

CB5/NC

89

VSS43

91

CB1/NC

93

VSS45
DQS8_c95DM8_n/DBI_n/NC

97

DQS8_t

99

VSS48

101

CB2/NC

103

VSS50

105

CB3/NC

107

VSS52

109

CKE0

111

VDD1

113

BG1

115

BG0

117

VDD3

119

A12

121

A9

123

VDD5

125

A8

127

A6

129

VDD7

131

A3

133

A1

135

VDD9

137

CK0_t

139

CK0_c

141

VDD11

143

PARITY

145

BA1

147

VDD13

149

CS0_n

151

WE_n/A14

153

VDD15

155

ODT0

157

CS1_n

159

VDD17

161

ODT1

163

VDD19

165

C1, CS3_n,NC

167

VSS53

169

DQ37

171

VSS55

173

DQ33

175

VSS57

177

DQS4_c

179

DQS4_t

181

VSS60

183

DQ38

185

VSS62

187

DQ34

189

VSS64

191

DQ44

193

VSS66

195

DQ40

197

VSS68

199

DM5_n/DBI5_n

201

VSS69

203

DQ46

205

VSS71

207

DQ42

209

VSS73

211

DQ52

213

VSS75

215

DQ49

217

VSS77

219

DQS6_c

221

DQS6_t

223

VSS80

225

DQ55

227

VSS82

229

DQ51

231

VSS84

233

DQ61

235

VSS86

237

DQ56

239

VSS88

241

DM7_n/DBI7_n

243

VSS89

245

DQ62

247

VSS91

249

DQ58

251

VSS93

253

SCL

255

VDDSPD

257

VPP1

259

VPP2

261

GND1

LCN_DAN05-Q0406-0103

CONN@

LINK SP07001D200 DONE

EVENT_n/NF

RAS_n/A16

CAS_n/A15

C0/CS2_n/NC

DM4_n/DBI4_n

DM6_n/DBI6_n

VSS11

VSS13

VSS15

DQS1_c

DQS1_t

VSS18

VSS20

VSS22

VSS24

VSS26

VSS27

VSS29

VSS31

VSS33

VSS35

DQS3_c

VSS38

VSS40

VSS42

CB4/NC

VSS44

CB0/NC

VSS46

VSS47

CB6/NC

VSS49

CB7/NC

VSS51

RESET_n

VDD2

ACT_n

ALERT_n

VDD4

VDD6

VDD8

VDD10

CK1_t/NF

CK1_c/NF

VDD12

A10/AP
VDD14

VDD16

VDD18

VREFCA

VSS54

VSS56

VSS58

VSS59

VSS61

VSS63

VSS65

VSS67

DQS5_c

DQS5_t

VSS70

VSS72

VSS74

VSS76

VSS78

VSS79

VSS81

VSS83

VSS85

VSS87

DQS7_c

DQS7_t

VSS90

VSS92

VSS94

GND2

DQ12

DQ14

DQ11

DQ20

DQ16

DQ22

DQ18

DQ28

DQ24

DQ31

DQ27

CKE1

DQ36

DQ32

DQ39

DQ35

DQ45

DQ41

DQ47

DQ43

DQ53

DQ48

DQ54

DQ50

DQ60

DQ57

DQ63

DQ59

+1.2V_MEM+1.2V_MEM

2

VSS2

DQ4

VSS4

DQ0

VSS6

VSS7

DQ6

VSS9

DQ2

DQ8

A11

A7

A5
A4

A2

A0

BA0

A13

SA2

SDA

SA0

VTT

SA1

DDR_A_D1

4
6

DDR_A_D5

8
10
12
14

DDR_A_D3

16
18

DDR_A_D7

20
22

DDR_A_D11

24
26

DDR_A_D12

28
30

DDR_A_DQS#1

32

DDR_A_DQS1

34
36

DDR_A_D13

38
40

DDR_A_D15

42
44

DDR_A_D17DDR_A_D21

46
48

DDR_A_D16DDR_A_D20

50
52
54
56

DDR_A_D18

58
60

DDR_A_D22

62
64

DDR_A_D29

66
68

DDR_A_D25

70
72

DDR_A_DQS#3

74

DDR_A_DQS3

76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106

DDR_DRAMRST#_R

108

DDR_A_CKE1

110
112

DDR_A_ACT#

114

DDR_A_ALERT#

116
118

DDR_A_MA11

120

DDR_A_MA7

122
124

DDR_A_MA5

126

DDR_A_MA4

128
130

DDR_A_MA2

132

JDIMM1_EVENT#

134
136

DDR_A_CLK1

138

DDR_A_CLK#1

140
142

DDR_A_MA0

144

DDR_A_MA10

146
148

DDR_A_BA0

150

DDR_A_MA16

152
154

DDR_A_MA15

156

DDR_A_MA13

158
160
162
164

DIMM1_SA2

166
168

DDR_A_D37

170
172

DDR_A_D33

174
176
178
180

DDR_A_D38

182
184

DDR_A_D39

186
188

DDR_A_D41

190
192

DDR_A_D45

194
196

DDR_A_DQS#5

198

DDR_A_DQS5

200
202
204
206
208
210

DDR_A_D49

212
214

DDR_A_D53

216
218
220
222

DDR_A_D54

224
226

DDR_A_D50

228
230

DDR_A_D56

232
234

DDR_A_D57

236
238

DDR_A_DQS#7

240

DDR_A_DQS7

242
244

DDR_A_D60

246
248

DDR_A_D61

250
252
254

DIMM1_SA0

256
258

DIMM1_SA1

260
262

DDR_A_CKE1 <7>

DDR_A_ACT# <7>
DDR_A_ALERT# <7>

DDR_A_CLK1 <7>
DDR_A_CLK#1 <7>

DDR_A_BA0 <7>

+DDR_VREF_A_CA

T50 PAD~D

@

+DDR_VREF_A_CA

DDR_XDP_WAN_SMBDAT <8,14>

+0.6V_DDR_VTT+2.5V_MEM

+1.2V_MEM

470_0402_1%

12

RD11

1 2

@

RD12 0_0402_5%

+1.2V_MEM

12

12

1

CD29

@

0.1U_0402_25V6

2

JDIMM1_EVENT#

DDR_VTT_CTRL< 7>

1 2

RD14 1K_0402_5%

@

UD1

1

NC

VCC

2

A

Y

3

GND

74AUP1G07SE-7_SOT353_5P

+1.2V_MEM

5

4

DDR_DRAMRST#DDR_DRAMRST#_R

1K_0402_1%

RD15

1 2

RD17 2_0402_1%

1K_0402_1%

RD16

1 2

CD32@0.1U_0201_10V6K

1 2

RD19 100K_04 02_5%

CHEC K

0.022U_0402_16V7K

CD31

12

24.9_0402_1%

12

RD18

H_THERMTRIP# <12,32>

0.6V_DDR_VTT_ON <42>

+3.3V_RUN

DDR_DRAMRST# <7>

+DDR_VREF_CA+DDR_VREF_A_CA

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS D OCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL . IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

3

PARTY WITHOUT DE LL'S EXPRESS WRITTEN CONSENT.

2

Title

Size

Size

Size

Date : Sheet

Date : Sheet

Date : Sheet

Compal Electronics, Inc.

DDR4

DDR4

Document Number Re v

Document Number Re v

Document Number Re v

DDR4

LA-F312P

LA-F312P

LA-F312P

1

20 58Wednesday, December 20, 2017

20 58Wednesday, December 20, 2017

20 58Wednesday, December 20, 2017

of

of

of

2.0

2.0

2.0

5

3

0.1U_0201_10V6K

1

@

CV39

2

+3.3V_RUN

+3.3V_RUN

+5V_RUN

1

AP2330W-7_SC59-3

IN

UV2

GND2OUT

3

12

RV19@10K_ 0402_5%

1 2

RV10 470_0402_1 %

1 2

RV11 470_0402_1 %

1 2

RV12 470_0402_1 %

1 2

RV13 470_0402_1 %

1 2

RV14 470_0402_1 %

1 2

RV15 470_0402_1 %

1 2

RV16 470_0402_1 %

1 2

RV17 470_0402_1 %

1 2

RV18 10K_040 2_5%

2

+VHDMI_VCC

0.1U_0201_10V6K

1

@

2

HDMI_HPD

HDMI_CTRL_DATA
HDMI_CTRL_CLK

HDMI_CEC
HDMI_L_CLKN

HDMI_L_CLKP
HDMI_L_TX_N0

HDMI_L_TX_P0
HDMI_L_TX_N1

HDMI_L_TX_P1
HDMI_L_TX_N2

HDMI_L_TX_P2

HDMI_OB

2

G

For 1.65G HDMI from CPU

10U_0603_10V6M

CV41

12

CV40

1

HDMI connector

ACON_HMRBL-A41L0F

19

HPD

18

+5V

17

DDC/CEC GND

16

SDA

15

SCL

14

Reserved

13

CEC

12

CK-

11

CK_Shield

10

CK+

9

D0-

8

D0_Shield

7

D0+

6

D1-

5

D1_Shield

4

D1+

3

D2-

2

D2_Shield

1

D2+

JHDMI1

LINK DC231604012 (temp) DONE

1

D

QV4
L2N7002W T1G_SC-70-3

S

3

GND
GND
GND
GND

CONN@

23
22
21
20

5

D D

C C

CPU_DP1_P0<6>

CPU_DP1_N0<6 >

CPU_DP1_P1<6>

CPU_DP1_N1<6 >

CPU_DP1_P2<6>

CPU_DP1_N2<6 >

CPU_DP1_P3<6>

CPU_DP1_N3<6 >

1 2

CV31 0.1U_0402_25V6

1 2

CV32 0.1U_0402_25V6

1 2

CV33 0.1U_0402_25V6

1 2

CV34 0.1U_0402_25V6

1 2

CV35 0.1U_0402_25V6

1 2

CV36 0.1U_0402_25V6

12

0.1U_0402_25V6

CV37

12

0.1U_0402_25V6

CV38

HDMI_TX_P2

HDMI_TX_N2

HDMI_TX_P1

HDMI_TX_N1

HDMI_TX_P0

HDMI_TX_N0

HDMI_CLKP

HDMI_CLKN

4

EMI@

LV31 10NH_L QG15HS10NJ02D

1 2

HCM1012GH900BP_4P

2

2

1

1

@EMI@

1 2

EMI@

LV32 10NH_LQG15HS10NJ02D

EMI@

LV33 10NH_L QG15HS10NJ02D

1 2

HCM1012GH900BP_4P

2

2

1

1

@EMI@

1 2

EMI@

LV34 10NH_LQG15HS10NJ02D

EMI@

LV35 10NH_L QG15HS10NJ02D

1 2

HCM1012GH900BP_4P

2

2

1

1

@EMI@

1 2

EMI@

LV36 10NH_LQG15HS10NJ02D

EMI@

LV37 18NH_L QG15HS18NJ02D_5%

1 2

HCM1012GH900BP_4P

2

2

1

1

@EMI@

1 2

EMI@

LV38 18NH_LQG15HS18NJ02D_5%

LV3

LV6

LV9

LV12

3

3

4

4

3

3

4

4

3

3

4

4

3

3

4

4

HDMI_L_TX_P2

EMI@

RV26
300_0402_5%

1 2

HDMI_L_TX_N2

HDMI_L_TX_P1

EMI@

RV29
300_0402_5%

1 2

HDMI_L_TX_N1

HDMI_L_TX_P0

EMI@

RV32
300_0402_5%

1 2

HDMI_L_TX_N0

HDMI_L_CLKP

EMI@

RV35
100_0402_5%

1 2

HDMI_L_CLKN

3

HDMI_TX_P2
HDMI_TX_N2
HDMI_TX_P1
HDMI_TX_N1
HDMI_TX_P0
HDMI_TX_N0
HDMI_CLKP
HDMI_CLKN

+3.3V_RUN

1M_0402_5%

RV20

CPU_DP1_HPD<6>

1 2

G

123

D

S

QV5

L2N7002W T1G_SC-70-3

HDMI_HPD

1 2

RV21 20K_0402 _5%

B B

+3.3V_RUN

QV3A

2

DMN65D8LDW-7_SOT36 3-6

HDMI_CTRL_CLK

1

CPU_DP1_CTRL_CLK< 6>

CPU_DP1_CTRL_DATA<6>

5

QV3B

DMN65D8LDW-7_SOT36 3-6

6

HDMI_CTRL_DATA

34

1 2

RV22 2.2K_0 402_5%

1 2

RV23 2.2K_0 402_5%

+VHDMI_VCC

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EX PRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY TH IRD
PARTY WITHOUT DELL'S EX PRESS WRITTEN CONSENT.

4

2

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date : Sheet of

Date : Sheet of

Date : Sheet of

Compal Electronics, Inc.

HDMI CONN

HDMI CONN

HDMI CONN

LA-F312P

LA-F312P

LA-F312P

21 58Wednesday, December 20, 2017

21 58Wednesday, December 20, 2017

21 58Wednesday, December 20, 2017

1

2.0

2.0

2.0

5

4

3

2

1

+3.3V_RUN

+3.3V_VDD_PIC

D D

+3.3V_CPS

546@

RT308

4.7K_0402_5%

(I2C_EN )

1 2

AUX1_SNOOP_EN#

12

8743@

RT416

C C

PS8743B Pin Control Mode
USB HOST facing TX channel
De-emphasis setting. Internally pull down at 150k.
Tolerant to VDD_DCI only.
SSDE =

B B

L: -3.5dB Output De-emphasis(default)
H: -6dB Output De-emphasis

4.7K_0402_5%

RT137

@

4.7K_0402_5%

SD028470180

(SSDE/ DCI_DATA)

MUX1_SSEQ0

1 2

@

LT11 BLM15PX600SN1D_2P

1 2

LT13 BLM15PX600SN1D_2P

TUSB546:(AUX1_SNOOP_EN#)
Pop RT308, Depop RT416
PS8743:(I2C_E N)
Pin C ontrol mode Depop RT308,Pop RT416
I2C mode Pop RT308,Depop RT416

+3.3V_CPS

1K_0402_5%

@

RT137

1 2

546@

20K_0402_5%

@

1K_0402_5%

12

12

RT138

RT302

+3.3V_CPS

12

RT248

8743@

4.99K_0402_1%

SD034499180

10U_0402_6.3V6M

1

CT117

2

(REXT)

MUX1_DPEQ1

UT9

546@

UT9

1

VCC

6

VCC

20

VCC

28

VCC

9

DP0p

10

DP0n

12

DP1p

13

DP1n

15

DP2p

16

DP2n

18

DP3p

19

DP3n

31

RX1n

30

RX1p

39

RX2n

40

RX2p

8

SSTXp

7

SSTXn

29

SNK_CAD/DCI_DAT

32

HPDIN/DCI_CLK

41

PAD

TUSB546_QFN40_4X6

20K_0402_5%

@

12

RT304

8743@

PS8743BQFN40GTR-B1_QFN40_4X6

SA00009E910

(CE_USB)

(FLIP)

(VDD_ DCI)

(REXT)

(CDE/D CI_CLK)

(SSDE/ DCI_DATA)

(I2C_EN ).

PS8743B Pin Control Mode
USB Type-C connector facing RX channel receiver
equalization setting;Internally tied to VDD33/2, 3.3V I/O.
CEQ =
L: Compensation for channel loss up to 7dB
H: Compensation for channel loss up to 18.5dB
M: Compensation for channel loss up to 11.5dB(default)

(ADDR /DCICFG )

(DPEQ)

(CEQ)

(CE_DP)

DPEQ0/A1

SSEQ0/A0

FLIP/SCL

CTL0/SDA

12

12

I2C_EN

DPEQ1

SSEQ1

CTL1

TX1n
TX1p

TX2p
TX2n

SSRXp
SSRXn

SBU1
SBU2

AUXp
AUXn

4.7K_0402_5%

@

RT412

4.7K_0402_5%

@

RT413

EQ1
EQ0

TUSB546: Pop RT69,RT90,Depop RT417,RT418
PS8743: Depop RT69,RT90,Pop RT417,RT418
(EQ1=CE_USB,EQ0=FL IP)

MUX1_USB_EQ1

35

MUX1_USB_EQ0

38

MUX1_I2C_EN

17

MUX1_DPEQ1

2

MUX1_DPEQ0

14

MUX1_SSEQ1

3

MUX1_SSEQ0

11

MUX1_FLIP_SEL

21

MUX1_USB_SEL

22

MUX1_DP_SEL

23

34
33

37
36

USB3_PRX_C_DTX_P1

5

USB3_PRX_C_DTX_N1

4

TUSB546A_SBU1_R

27

TUSB546A_SBU2_R

26

CPU_DP2_AUXP_C

24

CPU_DP2_AUXN_C

25

8743@
8743@

(DPEQ)(CEQ)

MUX1_FLIP_SELMUX1_USB_SEL

PS8743B Pin Control Mode
DP Receiver equalization setting;
Internal tied to VDD33/2, 3.3V I/O.
DPEQ =
L: Compensation for channel loss up to 7dB
H: Compensation for channel loss up to 14.5dB
M: Compensation for channel loss up to 10.5dB(default)

MUX1_USB_EQ1 <23>
MUX1_USB_EQ0 <23>

MUX1_FLIP_SEL <23>

MUX1_USB_SEL <23>

MUX1_DP_SEL <23>

TBTA_TX1N <25>
TBTA_TX1P <25>

TBTA_TX2P <25>
TBTA_TX2N <25>

12

4.7K_0402_5%

12

4.7K_0402_5%

12

1 2
1 2

@

RT411

@

RT410

12

12
12

CT111 0.1U_0402_25V6
CT112 0.1U_0402_25V6

RT132 0_0402_5%8743@
RT133 0_0402_5%8743@

CT115 0.1U_0402_25V6
CT116 0.1U_0402_25V6

+3.3V_CPS+3.3V_CPS

0.1U_0201_10V6K

0.1U_0201_10V6K

CT118

CT119

1

2

CPU_DP2_P0<6>
CPU_DP2_N0<6>

CPU_DP2_P1<6>
CPU_DP2_N1<6>

CPU_DP2_P2<6>
CPU_DP2_N2<6>

CPU_DP2_P3<6>
CPU_DP2_N3<6>

USB3_PTX_DRX_P1<10>
USB3_PTX_DRX_N1<10>

0.1U_0201_10V6K

0.1U_0201_10V6K

CT120

1

1

2

2

TBTA_RX1N<25>
TBTA_RX1P<25>

TBTA_RX2N<25>
TBTA_RX2P<25>

for pin control , connect to PD GPIO

+3.3V_CPS

1K_0402_5%

@

RT247

1 2

546@

20K_0402_5%

1K_0402_5%

12

12

RT248

TUSB546: Pop RT246,Depop CT122

CT121

Check I2C or Pin control

@

RT303

PS8740: Depop RT246,Pop CT122
PS8743: Depop RT246,Pop CT1 22(CEXT)

1 2

546@

RT246 0_0402_5%

1 2
1 2

CT103 0.1U_0402_25V6
CT104 0.1U_0402_25V6

1 2
1 2

CT105 0.1U_0402_25V6
CT106 0.1U_0402_25V6

1 2
1 2

CT107 0.1U_0402_25V6
CT108 0.1U_0402_25V6

1 2
1 2

CT109 0.1U_0402_25V6
CT110 0.1U_0402_25V6

1 2
1 2

CT113 0.1U_0402_25V6
CT114 0.1U_0402_25V6

CPU_DP2_HPD<6,23>

@

RT380 0_0402_5%

+3.3V_CPS_R1

CPU_DP2_P0_C
CPU_DP2_N0_C

CPU_DP2_P1_C
CPU_DP2_N1_C

CPU_DP2_P2_C
CPU_DP2_N2_C

CPU_DP2_P3_C
CPU_DP2_N3_C

USB3_PTX_C_DRX_P1
USB3_PTX_C_DRX_N1

AUX1_SNOOP_EN#

1 2

MUX1_USB_EQ0

12

CT1222.2U_0402_6.3V6M

8743@

+3.3V_CPS

1K_0402_5%

@

RT143

1 2

546@

1K_0402_5%

12

RT144

For NON-AR port1

TUSB546: Pop RT300,Depop RT145,RT301
PS8743:Depop RT301,Pop RT145,RT300(change to 0.1uf)(VDD_DCI)

RT145

8743@

0_0402_5%

SD028000080

(VDD_ DCI)

MUX1_I2C_EN

I2C Programming or Pin Strap Programming Select,Internally
30k pull-up and 60k pull-down
I2C_EN =
0: Tie 1k to GND,Pin Strap(I2C disable)
R:Tie 20k to GND,TI Test M ode(I2C enabled)
F: Float,TI Test Mode(I2C enabled)

USB3_PRX_DTX_P1 <1 0>

USB3_PRX_DTX_N1 <10>

TBTA_SBU1 <23,25>
TBTA_SBU2 <23,25>

CPU_DP2_AUXP <6,23>
CPU_DP2_AUXN <6,23>

1:Tie 1k to VCC,I2C enabled

CPU_DP2_AUXN_C

CPU_DP2_AUXP_C

+3.3V_CPS

1 2

12

TUSB546A_SBU1_R

8743@

TUSB546A_SBU2_R

8743@

1 2

1 2

1K_0402_5%

@

RT145

546@

20K_0402_5%

1K_0402_5%

@

12

RT300

RT301

12

1 2

RT414 2M_0402_5%

1 2

RT415 2M_0402_5%

RT131100K_0402_5%

RT130100K_0402_5%

0.1U_0402_25V6

8743@

CT213

+3.3V_CPS

Ser the USB receiver equalizer gain for upstream facing
SSTXP/N,Internally 30k pull-up and 60k pull-down
SSEQ =
0: Tie 1k to GND
R:Tie 20k to GND
F: Float
1:Tie 1k to VCC

RT135

@

4.7K_0402_5%

SD028470180

(ADDR /DCICFG ) (CDE/D CI_CLK)

MUX1_SSEQ1

RT136

A A

PS8743B Pin Control Mode
DCI mode configuration pin; Internally tied to
VDD33/2, 3.3V I/O.
DCICFG =
L: DCI mode disabled
H: DCI mode enabled
M: Automatic DCI mode entering enabled (default)

@

4.7K_0402_5%

SD028470180

+3.3V_CPS

1K_0402_5%

@

RT135

1 2

546@

20K_0402_5%

1K_0402_5%

12

12

RT136

PS8743:
I2C Control mode
ADDR: I2C control bus address LSB.
Internally pull down at 150k, 3.3VI/O.
[ADDR] =
L: 0x20/0x21
H: 0x22/0x23

5

@

RT305

Select the DisplayPort receiver equalizer gain ,Internally
30k pull-up and 60k pull-down
DPEQ =
0: Tie 1k to GND
R:Tie 20k to GND
F: Float
1:Tie 1k to VCC

RT139

@

1K_0402_5%

@

4.7K_0402_5%

SD028470180

PS8743B Pin Control Mode
USB Type-C connector facing TX channel
De-emphasis setting. Internally pull down at 150k.
Tolerant to VDD_DCI only.
CDE =
L: -3.5dB Output De-emphasis(default)
H: -6dB Output De-emphasis

RT139

1 2

20K_0402_5%

@

1K_0402_5%

546@

12

12

RT306

RT140

4

Ser the USB receiver equalizer gain for downstream facing
RX1 and RX2 when USB utilized,Internally 30k pull-up and
60k pull-down
USB_EQ =
0: Tie 1k to GND
R:Tie 20k to GND
F: Float
1:Tie 1k to VCC

+3.3V_CPS+3.3V_CPS

1K_0402_5%

@

RT141

MUX1_USB_EQ1MUX1_DPEQ0

1 2

546@

20K_0402_5%

@

1K_0402_5%

12

12

RT142

RT307

PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.

3

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Nu mber Re v

Size Document Nu mber Re v

Size Document Nu mber Re v

Date: Sheet o f

Date: Sheet o f

2

Date: Sheet o f

Compal Electronics, Inc.

DP/USB3 Repeater SW TUSB546

DP/USB3 Repeater SW TUSB546

DP/USB3 Repeater SW TUSB546

LA-F312P

LA-F312P

LA-F312P

22 58Wednesday, December 20, 2017

22 58Wednesday, December 20, 2017

22 58Wednesday, December 20, 2017

1

2.0

2.0

2.0

5

+3.3V_TBTA_FLASH+3.3V_TBTA_FLASH

12

12

CT70

RT50

3.3K_0402_5%
.1U_0402_16V7K

@

RT54 0_0402_5%

@

RT55 0_0402_5%

@

RT56 0_0402_5%

@

RT57 0_0402_5%

JDB1

1

1

2

2

3

3

4

4

5

5

GND

6

6

GND

ACES_50506-00641-P01

CONN@

DIV_ma xDIV_min

0.080.00

0.180.10

0.280.20

0.380.30

0.480.40

0.580.50

0.680.60

1.00 7

8
7
6
5

TBTA_ROM_CLK_PD_R
TBTA_ROM_DI_PD_R
TBTA_ROM_DO_PD_R
TBTA_ROM_CS#_PD_R

TBTA_ROM_HOLD#_PD
TBTA_ROM_CLK_PD_R
TBTA_ROM_DI_PD_R

D D

TBTA_ROM_CLK_PD_R
TBTA_ROM_DI_PD_R
TBTA_ROM_DO_PD_R
TBTA_ROM_CS#_PD_R

7
8

DIV = R2/(R1+R2)

C C

B B

0.70

A A

UT6

TBTA_ROM_CS#_PD_R

1

TBTA_ROM_DO_PD_R

CS#

VCC
HOLD#(IO3)
CLK
DI(IO0)

GD25Q80CSIGR_SO8

1 2
1 2
1 2
1 2

+3.3V_TBTA_FLASH

Config uration

2

TBTA_ROM_WP#_PD

DO(IO1)

3

WP#(IO2)

4

GND

TBTA_ROM_CLK_PD
TBTA_ROM_DI_PD
TBTA_ROM_DO_PD
TBTA_ROM_CS#_PD

Descrip tionFactory Device

UFP onl y
5V @0.9A Sink capabil ity w ith "Ask for Max/" for
anything from 0.9 -3.0A

0

TBT Alternate Modes not supported
DisplayPort Alternate Modes not supported
TI VID supported

UFP onl y
5V @0.9A Sink capabil ity w ith "Ask for Max/" for
anything from 0.9 -3.0A

1

TBT Alternate Modes not supported
DisplayPort Alternate Modes -Sink, C and D pin configuration
TI VID supported

UFP onl y
5V @3.0A Source capability

2

TBT Alternate Modes not supported
DisplayPort Alternate Modes not supported
TI VID supported

UFP onl y
5V @3.0A Source capability

3

TBT Alternate Modes not supported
DisplayPort Alternate Modes -Sink, C and D pin configuration
TI VID supported

DRP
5V @0.9-3.0A Sink capabil ity
5V @3.0A Source capability
TBT Alternate Modes not supported

4

DisplayPort Alternate Modes not supported
TI VID supported
Accepts data and power role sw aps, but does not
initiat e.

DRP
5V @0.9-3.0A Sink capabil ity
5V @3.0A Source capability
TBT Alternate Modes not supported

5

DisplayPort Alternate Modes - Sourc e, C, D, and E
pin configurations.
TI VID supported
Accepts power role swaps but w ill not initiate.
Accepts data rol e swap to UFP and c an initia te.

DRP
5V @0.9-3.0A Sink capabil ity
5V @3.0A Source capability
TBT Alternate Modes not supported

6

DisplayPort Alternate Modes - Sourc e, C, D, and E
pin configurations.
TI VID supported
Accepts power role swaps but w ill not initiate.
Accepts data rol e swap to DFP and c an initia te.

Infinite boot retry from Flash to Host I/F cycles.

12

12

12

RT52

RT51

RT53

3.3K_0402_5%

3.3K_0402_5%

3.3K_0402_5%

UPD1_SMBCLK<31>

+3.3V_TBTA_FLASH +3.3V_TBTA_FLASH +3.3V_TBTA_FLASH

12

@

RT405

10K_0402_1%

MUX1_FLIP_SEL_R TBTA_DEBUG3 TBTA_DEBUG4

+3.3V_TBTA_FLASH

+3.3V_TBTA_FLASH

546@

546@

4

DMN66D0LDW-7_SOT363-6

UPD1_SMBDAT<31>

UPD1_SMBINT#< 31>

12

@

RT406

10K_0402_1%

10K_0402_1%

RT76

1 2

PD1_GPIO8

12

RT377

43K_0402_1%

RT81

RT82 1M_0402_5%@

TI ref ckt: 100k
Intel ref ckt: 1M

MUX1_DP_SEL/MUX1_USB_SEL control by:
GPIO: Pop RT89,RT90;Depop RT375,RT376
I2C:Depop RT89,RT90;pop RT375,RT376

MUX1_FLIP_SEL<22,23>
MUX1_USB_SEL< 22,23>

Check AUX connect to PD or PS8743B

TBTA_AUXN_C

12

RT95

RT96

12

100K_0402_5%

TBTA_AUXP_C

100K_0402_5%

+3.3V_VDD_PIC

126

QT1A

@

@

1 2

RT58 0_0402_5%

@

DMN66D0LDW-7_SOT363-6

@

RT59 0_0402_5%

@

1 2

RT60 0_0402_5%

12

8743@

RT407

10K_0402_1%

TI is 3x1uf

UART_MOSI

12

100K_0402_5%

UART_MISO

12

RT375 0_0402_5%

@

RT376 0_0402_5%

@

UPD1_SMBCLK_Q

5

QT1B

1 2

MUX1_USB_EQ0<22>
MUX1_FLIP_SEL<22 ,23>

1 2
1 2

+VCC1V8D_TBTA_LDO

34

1

CT71

2

EN_PD_HV_1<50>

AC1_DISC#<49,50>
CPU_DP2_HPD<6,22>
USB2_ID<10>

3

UPD1_SMBDAT_Q

UPD1_SMBINT#_R

+TBTA_LDO_BMC
+VCC1V8D_TBTA_LDO
+VCC1V8A_TBTA_LDO

1

1

CT72

2

2

2.2U_0402_16V6K

2.2U_0402_16V6K

MUX1_DP_SEL<22>
MUX1_USB_SEL< 22,23>
MUX1_USB_EQ1<22>

CPU_DP2_AUXP<6,22>
CPU_DP2_AUXN<6,22>

RT97 0_0402_5%@

+3.3V_VDD_PIC

CT73

2.2U_0402_16V6K

+3.3V_TBTA_FLASH

+3.3V_ALW

EN_PD_HV_1

UART_MOSI

UART_MISO

T219@ PAD~D
T220@ PAD~D

546@
8743@

UPD1_SMBCLK_Q TBTA_DEBUG1
UPD1_SMBDAT_Q

1 2

PJP7

1 2

PAD-OPEN1x1m

+3.3V_TBTA_FLASH

RT66 3.3K_0402_5%

@

RT67 3.3K_0402_5%

@

RT68 10K_0402_5%

@

@

1 2

RT70 0_0402_5%
RT71 1M_0402_5%

@

1 2

RT72 0_0402_5%

@

1 2

RT73 0_0402_5%

@

1 2

RT74 0_0402_5%

RT75 0_0402_5%

@

RT339 0_0402_5%

@

USB20_P1<10>
USB20_N1<10>

@
@

RT86 1M_0402_5%

1 2

RT87 0_0402_5%@

1 2

RT88 0_0402_5%@

1 2

@

1 2

RT89 0_0402_5%
RT90 0_0402_5%
RT418 0_0402_5%

1 2

@

1 2

RT92 0_0402_5%

@

RT93 0_0402_5%

546@

1 2

CT80 0.1U_0201_10V6K

546@

1 2

CT81 0.1U_0201_10V6K

+3.3V_TBTA_FLASH

@

RT98

1 2

@

RT99
0_0402_5%

1 2

+5V_ALW

PJP8

1 2

PAD-OPEN 1x3m

1

@

RT63 0_0402_5%

CT74

2

1U_0402_10V6K

RT378 10K_0402_5%
RT379 10K_0402_5%

12
12
12

12

8743@

12

546@

12

12
12

@

RT84 0_0402_5%
RT85 0_0402_5%

12

12

0_0402_5%

12
12

UPD1_SMBDAT_Q
UPD1_SMBCLK_Q
UPD1_SMBINT#_R

RT4170_040 2_5%

MUX1_FLIP_SEL_R

RT690_0402_5%

EN_PD_HV_1_R
PD1_GPIO2
AC1_DISC#_R
CPU_DP2_HPD_R
OTG_ID
PD1_GPIO6
PD1_GPIO7

TBTA_ROM_CLK_PD
TBTA_ROM_DI_PD
TBTA_ROM_DO_PD
TBTA_ROM_CS#_PD

1 2

RT83 0_0402_5%

12
12

TBTA_MRESET

TBTA_LSTX_R
TBTA_LSRX_R

TBTA_DEBUG3
TBTA_DEBUG4

TBTA_DEBUG2

TBTA_AUXP_C
TBTA_AUXN_C

TBTA_ROSC

12

RT100

15K_0402_1%

TI is 1x47uf+1x0.1uf

1 2

PD1_GPIO8

1

CT75

2

22U_0805_25V6M

UT5

F1

I2C_ADDR

D1

I2C_SDA1

D2

I2C_SCL1

C1

I2C_IRQ1_N

A5

I2C_SDA2

B5

I2C_SCL2

B6

I2C_IRQ2_N

B2

GPIO0

C2

GPIO1

D10

GPIO2

G11

GPIO3

C10

GPIO4

E10

GPIO5

G10

GPIO6

D7

GPIO7

H6

GPIO8

A3

SPI_CLK

B4

SPI_MOSI

A4

SPI_MISO

B3

SPI_SS_N

L5

USB_RP_P

K5

USB_RP_N

E2

UART_TX

F2

UART_RX

F4

SWD_DATA

G4

SWD_CLK

E11

MRESET

L4

TBT_LSTX/R2P

K4

TBT_LSRX/P2R

L3

DIG_AUD_P/DEBUG3

K3

DIG_AUD_N/DEBUG4

L2

DEBUG1

K2

DEBUG2

J1

AUX_P

J2

AUX_N

F10

BUSPOWER_N

G2

R_OSC

1

1

CT77

CT76

2

2

22U_0805_25V6M

+3.3V_VDD_PIC_PDA

H1

VIN_3V3

2

1

For NON-AR port1

+TBTA_Vbus_1

1

CT78

2

22U_0805_25V6M

22U_0805_25V6M

1 2

RT64 0_0402_5%

@

1 2

RT65 0_0402_5%

@

+5V_ALW_PDA

A11

B11

B1

VDDIO

H10

K1

A2

LDO_1V8A

LDO_1V8D

GND

HRESET

GNDE5GND

E7

A1

E6

D6

12

RT101

100K_0402_5%

E1

GND

F5

LDO_BMC

GND

G5

PP_CABLE

GND

GNDH4GND

H5

C11

PP_5V0

PP_5V0

PP_5V0

GND

GNDF6GNDF7GND

GND

GND

E8

B8

D8

0.22U_0402_16V7K

D11

GNDA6GNDA7GNDA8GND

PP_5V0

GND

GNDG7GND

SSH7GNDL1GND

F8

H8

G6

G8

1

CT87

2

B7

GND

L11

HV_GATE1_A

B10

A10

SENSEP

SENSEN

VOUT_3V3

LDO_3V3

C_USB_TP
C_USB_TN

C_USB_BP

C_USB_BN

RPD_G1
RPD_G2

DEBUG_CTL1
DEBUG_CTL2

C_SBU1

C_SBU2

RESET_N

TPS65982DC_BGA96

12

RT103

@

0_0402_5%

HV_GATE2_A

A9

+TBTA_Vbus_1

HV_GATE1B9HV_GATE2

VBUS
VBUS
VBUS
VBUS

TI has 1x1uf

+3.3V_PDA_VOUT

H11

12

J10
J11

CT82

K11

H2

1U_0603_50V6K

G1

K6
L6

K7
L7

TI has 2x220pf

L9

C_CC1

L10

C_CC2

WHEN CONNECT BUSPOWERZ TO GND,
CONNECT ALSO RPD_Gn to C_CCn

K9

@

K10

RT104 0_0402_5%

@

RT105 0_0402_5%

TBTA_DBG_CTL1

E4

TBTA_DBG_CTL2

D5

TBTA_SBU1_R

K8

TBTA_SBU2_R

L8

TBTA_RESET_N_EC_R

F11

1 2
1 2

546@

RT108 0_0402_5%

546@

RT109 0_0402_5%

+3.3V_TBTA_FLASH

1

1

CT83

2

2

1U_0402_10V6K

TBTA_TOP_P <25>
TBTA_TOP_N <25>

TBTA_BOT_P <25>
TBTA_BOT_N <25>

1 2

RT106 10K_0402_5%

1 2

RT107 10K_0402_5%

1 2

1 2

CT84

10U_0603_6.3V6M

TBTA_CC1 <25>

12

+3.3V_TBTA_FLASH

RT1100_0402_5%

@

TBTA_CC2 <25>

TBTA_SBU1 <22,25>

TBTA_SBU2 <22,25>

1

1

CT86

CT85

2

2

820PF_0402_50V7K

820PF_0402_50V7K

Need Link TPS65982D

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size

Size

Size

Date : Sheet

Date : Sheet

Date : Sheet

Compal Electronics, Inc.

[Type C]PD Controller TI

[Type C]PD Controller TI

[Type C]PD Controller TI

Document Number Re v

Document Number Re v

Document Number Re v

LA-F312P

LA-F312P

LA-F312P

1

23 58Wednesday, December 20, 2017

23 58Wednesday, December 20, 2017

23 58Wednesday, December 20, 2017

of

of

of

2.0

2.0

2.0

+5V_ALW

5

4

3

2

1

DT1

+5V_TBT_VBUS

D D

C C

1N4148WS-L_SOD323-2

1N4148WS-L_SOD323-2

DT3

1 2

1N4148WS-L_SOD323-2

1U_0402_10V6K

1

CT93

2

12

DT2

12

+5V_TBTA_VBUS_D

+5V_PD_VDD

100K_0402_5%

12

3

VOUT

AP2204R-5.0TRG1_SOT89-3

@

0.1U_0201_10V6K

RT393

1

2

UT8

1

VCC

2

GND

CT88

1U_0402_10V6K

1

CT89

2

+TBTA_VBUS_1

1 2

RT111 100K_0402_5%

1U_0603_50V6K

1

CT94

2

UT7

VCC1VOUT

2

GND

EN3ADJ/NC

AP2112K-3.3TRG1_SOT23-5

1

CT90
1U_0402_10V6K

2

5

4

2.2U_0603_25V6K

0.1U_0402_25V6K

12

12

@

CT91

+3.3V_VDD_PIC

CT92

place near UT7

B B

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Title

Title

Size Document N umber Re v

Size Document N umber Re v

Size Document N umber Re v

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

Compal Electronics, Inc.

[Type C]PD Power

[Type C]PD Power

[Type C]PD Power

LA-F312P

LA-F312P

LA-F312P

24 58Wednesday, December 20, 2017

24 58Wednesday, December 20, 2017

24 58Wednesday, December 20, 2017

1

2.0

2.0

2.0

5

4

3

2

1

For NON AR Config

D D

+TBTA_VBUS+TBTA_VBUS +TBTA_VBUS +TBTA_VBUS

JUSBC1

A1

TBTA_TX1P<22 >
TBTA_TX1N<22>

TBTA_TOP_P<23>

C C

B B

TBTA_TOP_N<23> TBTA_BOT_P <23>

TBTA_TX1P_C

TBTA_TX1N_C

TBTA_RX2N

TBTA_RX2P

@EMI@
@EMI@

ESD@

1 2

AZ5B75-01B

ESD@

1 2

AZ5B75-01B

ESD@

1 2

AZ5B75-01B

ESD@

1 2

AZ5B75-01B

1 2
1 2

CT95 0.22U_0201_6.3 V6K
CT96 0.22U_0201_6.3 V6K

TBTA_CC1<23>

1 2

RT120 0_0402_5%

1 2

RT121 0_0402_5%

TBTA_RX2N<22>
TBTA_RX2P<22>

DT5

DT6

DT9

DT10

TBTA_TX1P_C
TBTA_TX1N_C

12

CT990.01U_0201_25V6 K

TBTA_CC1

TBTA_TOP_P_R
TBTA_TOP_N_R

12

CT1010.01U_0201_25V 6K

Premium 12/14/15 UMA:Check SBU1/SBU2 connect to PD or PS8740B
Link DC23300MEBL Done

TBTA_RX1P

TBTA_RX1N

TBTA_TX2P_C

TBTA_TX2N_C

GND_A1

A2

SSTXp1

A3

SSTXn1

A4

VBUS_A4

A5

CC1

A6

Dp1

A7

Dn1

A8

SBU1

A9

VBUS_A9

A10

SSRXn2

A11

SSRXp2

A12

GND_A12

1

GND1

3

GND3

JAE_DX07B024XJ1R1300 ~D

CONN@

DT13

ESD@

1 2

AZ5B75-01B

DT14

ESD@

1 2

AZ5B75-01B

DT17

ESD@

1 2

AZ5B75-01B

DT18

ESD@

1 2

AZ5B75-01B

TOP

B12

GND_B12

B11

SSRXp1

B10

SSRXn1

B9

VBUS_B9

B8

SBU2

B7

Dn2

B6

Dp2

B5

CC2

B4

Bottom

VBUS_B4

B3

SSTXn2

B2

SSTXp2

B1

GND_B1

2

GND2

4

GND4

Check ,FROM PWR PAGE

TBTA_RX1P
TBTA_RX1N

CT100 0.01U_0201_25V6K

TBTA_SBU2

TBTA_BOT_N_R
TBTA_BOT_P_R

TBTA_CC2TBTA_SBU1

CT102 0.01U_0201_25V6K

TBTA_TX2N_C
TBTA_TX2P_C

TBTA_RX1P <22>
TBTA_RX1N <22 >

1 2

TBTA_SBU2 <22,2 3>

@EMI@

1 2

RT122 0_0402_5%

@EMI@

1 2

RT123 0_0402_5%

TBTA_CC2 <23>TBTA_SBU1<22,23>

1 2

TBTA_BOT_N <23>

12

CT980.22U_0 201_6.3V6K

TBTA_TX2N <22>

12

CT970.22U_0 201_6.3V6K

TBTA_TX2P <22>

RF Request

12P_0402_50V8J

RF@

1

CT189

2

2

3

1

DT4

ESD@

AZ4024-02S_SOT23-3

DT39

TBTA_CC1 TBTA_CC1

TBTA_TOP_P_R TBTA_TOP_P_R

A A

TBTA_TOP_N_R

TBTA_SBU1

5

ESD@

1

1

2

2

4

4

5

5

3

3

8

AZ1045-04F_DFN2510P10E-10 -9

9

10

8

9

7

7

6

6

TBTA_TOP_N_R

TBTA_SBU1

TBTA_SBU2 TBTA_SBU2

TBTA_BOT_N_R TBTA_BOT_N_R

TBTA_BOT_P_R TBTA_BOT_P _R

TBTA_CC2 TBTA_CC2

4

DT40

ESD@

1

1

2

2

4

4

5

5

3

3

8

AZ1045-04F_DFN2510P10E-10 -9

9

10

8

9

7

7

6

6

Compal Electronics, Inc.

Compal Electronics, Inc.

PROPRIETARY NOTE:
THIS SHEET OF EN GINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER P ROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

3

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

2

Title

Title

Title

Size

Size

Size

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

USB 3.0 CONN TYPE C

USB 3.0 CONN TYPE C

USB 3.0 CONN TYPE C

Document Number Re v

Document Number Re v

Document Number Re v

LA-F312P

LA-F312P

LA-F312P

1

25 58Wednesday, December 20, 2017

25 58Wednesday, December 20, 2017

25 58Wednesday, December 20, 2017

2.0

2.0

2.0

5

LINK 50398-04041-001 DONE

JEDP1

10
11
12
13
14

D D

+BL_PWR_SRC

12

C C

Close to JEDP1.17~19

BIA_PWM

4.7K_0402_5%

12

RV1

15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35

41

36

G1

42

37

G2

43

38

G3

44

39

G4

45

40

G5

ACES_50398-04041-001

CONN@

0.1U_0603_50V7K

@

CV11

Close to JEDP1.30~31 Close to JEDP1.11 Close to JEDP1.1 Close to JEDP1.10

1

BAT54CW_SOT323-3

+3.3V_TSP

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

+LCDVDD +3.3V_CAM +3.3V_TSP

1

2

DV1

EDP_BIA_PWM

3

BIA_PWM_EC

2

USB20_N5_R
USB20_P5_R

CAM_MIC_CBL_DET# <12>

Pin15: LOOP_BACK

+BL_PWR_SRC

1 2

LV1

EMI@

DISP_ON

EDP_HPD <6>

LCD_TST <31 >

+LCDVDD

TOUCH_SCREEN_DET#
EDP_AUXN_C
EDP_AUXP_C
EDP_TXP0_C
EDP_TXN0_C
EDP_TXP1_C
EDP_TXN1_C

LCD_CBL_DET# <9>

0.1U_0201_10V6K

@

CV12

+3.3V_RUN
+3.3V_CAM

BIA_PWM

BLM15PX221SN1D_2P

12

CV1 0. 1U_0402_25V6

12

CV2 0. 1U_0402_25V6

12

CV3 0. 1U_0402_25V6

12

CV4 0. 1U_0402_25V6

12

CV5 0. 1U_0402_25V6

12

CV6 0. 1U_0402_25V6

0.1U_0201_10V6K

1

@

CZ1

2

EDP_BIA_PWM <6>

BIA_PWM_EC <31>

TOUCH_SCREEN_DET# <12>

TOUCH_SCREEN_PD# <12>

0.1U_0201_10V6K

1

@

2

RF Request

+LCDVDD +3.3V_CAM +BL_PWR_SRC

12P_0402_50V8J

82P_0402_50V8J

12P_0402_50V8J

82P_0402_50V8J

RF@

RF@

B B

RF@

1

1

1

CV22

CV20

CV21

2

2

2

12P_0402_50V8J

82P_0402_50V8J

RF@

RF@

1

CV23

2

RF@

1

1

CV24

CV25

2

2

100P_0402_50V8 J

12

EMI Request

EDP_HPD

1 2

RV7 100K_0 402_5%@

EDP_AUXN <6>

EDP_AUXP <6>
EDP_TXP0 <6>
EDP_TXN0 <6>
EDP_TXP1 <6>
EDP_TXN1 <6>

CZ2

DISP_ON

4.7K_0402_5%

12

@EMI@

CA5

RV2

4

100P_0402_50V8 J

12

+3.3V_RUN

@EMI@

CA6

0.1U_0201_10V6K

1

@

CA7

2

+LCDVDD

Reserve for EA

DV2

3

1

2

BAT54CW_SOT323-3

DMIC0 <30>

DMIC_CLK0 <30>

223

1

3

1

USB20_N8_R
USB20_P8_R

AZC199-02SPR7G_SOT23-3

@ESD@

DV4

TOUCH_PANEL_INTR#:

Close lid >> TP_EN = 0 >> Disable touch events
Open lid >> TP_EN = 1 >> Enable touch events

ESD depop locat i on

TOUCH_SCREEN_DET#

Due to SB12/14 Mic. receive path is dif f er ent
between Touch and Non-Touch Panel, so add
TOUCH_SCREEN_DET# pin for dif f er ent verb
table

USB20_N5_R
USB20_P5_R

PANEL_BKLEN <6>

PANEL_BKEN_EC <31>

3

EXC24CQ900U_4P

1 2

LV27

+3.3V_RUN

10K_0402_5%

RV8

1 2

@ESD@

ESD8011MUT5G_X3DFN2-2

12

DV7

ESD depop locat i on

12

EMI@

2

34

@ESD@

ESD8011MUT5G_X3DFN2-2

DV8

RF Request

+3.3V_TSP

12P_0402_50V8J

RF@

1

CV18

2

USB20_N8 <10>

USB20_P8 <10>

82P_0402_50V8J

RF@

1

CV19

2

JIR1

CONN@

1
2
3
4

7

5

GND

8

6

GND

E-T_4251K-F06N-40L

1
2
3
4
5
6

For 2LANE EDP &3.3V_TSP
For Breckenridge&Steamboat 12

+PWR_SRC

IR_CAM_DET# <12>

RF Request

+PWR_SRC

RF@

100P_0402_50V8 J

1

CZ3

2

1

For Touchscreen

+3.3V_RUN+3.3V_RUN +3.3V_TSP

10K_0402_5%

+3.3V_RUN

@

1 2

3.3V_TS_EN<3 1>

PCH_3.3V_TS_EN<9>

RV323 0_0402_5%

@

1 2

RV324 0_0402_5%

3.3V_TS_EN_R

RV6

100K_0402_5%

1 2

12

RV326

2

G

1 2

RV400 0_0402_5%

L2N7002WT1G_SC-70-3

13

D

QV7

S

QV8

LP2301A LT1G_SOT23-3

123

D

S

G

0.1U_0402_25V6K

12

@

CV635

LCDVDD POWER

WebCAM

3.3V_CAM_EN#<11>

A A

USB20_P5<10>

1 2

RZ380 0_0402_5%

5

LP2301A LT1G_SOT23-3

EXC24CQ900U_4P

1 2

LZ1

EMI@

QZ1

123

D

34

S

G

0.1U_0402_25V6K

12

@

CZ200

USB20_P5_R

USB20_N5_R

+3.3V_RUN+3.3V_CAM

Backlight POWER

+PWR_SRC

1000P_0402_50V7K

270K_0402_5%

CV13

RV4

1 2

1 2

BL_PWR_SRC_ON

0.01U_0402_50V7K

1

2

CV14

4

1 2

RV5 4 7K_0402_5 %

EN_INVPWR<31>USB20_N5<10>

QV1

S

4 5

G

AO6405_TSOP6

3

L2N7002 WT1G_SC-70 -3

D

6

2
1

123

D

QV2

S

G

+BL_PWR_SRC

12

0.1U_0603_50V7K

CV15

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER P ROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

3

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

+LCDVDD +EDP_VDD

CV16

@

12

10U_0603_10V6M

LCD_VCC_TEST_EN<31>

ENVDD_PCH<6>

PJP13

1 2

PAD-OPEN1 x1m

BAT54CW_SOT323-3

2

+3.3V_ALW

UV24

1

VOUT

2

GND

3

/OC

DV3

2

3

G524B1T11U_SOT23-5

1

EN_LCDPWR

5

VIN

4

EN

0.01UF_0402_25V7K

@

CV17

12

100K_0402_5%

RV3

1 2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size

Size

Size

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

eDP CONN & Touch screen

eDP CONN & Touch screen

eDP CONN & Touch screen

Document Number Re v

Document Number Re v

Document Number Re v

LA-F312P

LA-F312P

LA-F312P

1

26 58Wednesday, December 20, 2017

26 58Wednesday, December 20, 2017

26 58Wednesday, December 20, 2017

2.0

2.0

2.0

5

+3.3V_LAN

RL1@ 10K_0402_5%

RL2@ 10K_0402_5%

RL4 4.7K_ 0402_5%@

D D

PM_LANPHY_ENABLE<11>

+0.9V_LAN

22U_0603_6.3V6M

1

12

CL12

2

Note:
+1.0V_LAN will work at 0.95V to 1.15V

C C

B B

+3.3V_LAN

12

+3.3V_LAN

12

For W LAN c an't recognize during enable
Unobtrusive m ode(BITS152312)

A A

TP_LAN_JTAG_TMS

12

TP_LAN_JTAG_TCK

12

CLKREQ_PCIE#4

12

1 2

@

RL7 0_0402_5%

0.1U_0201_10V6K

0.1U_0201_10V6K

0.1U_0201_10V6K

CL9

1

2

LOM_SPD100LED_ORG#

LOM_SPD10LED_GRN#

LOM_ACTLED_YEL#

RL29
1M_0402_5%

LOM_SPD100LED_ORG#

RL30
1M_0402_5%

LOM_SPD10LED_GRN#

0.1U_0201_10V6K

CL11

CL10

CL8

1

1

2

2

When LAN & WLAN are exist at the same time, WLAN will disable

+3.3V_LAN

0.1U_0201_10V6K

5

1

P

B

O

2

A

G

TC7SH08FU_SSOP5~D

3

QL1A

DMN65D8LDW-7_SOT363-6

126

LED_MASK#

QL1B

DMN65D8LDW-7_SOT363-6

LED_100_ORG#

34

5

LED_MASK#

QL2A

DMN65D8LDW-7_SOT363-6

126

LED_MASK#

QL2B

DMN65D8LDW-7_SOT363-6

34

5

LED_10_GRN#

+3.3V_LAN

10K_0402_5%

1 2

10K_0402_5%

12

XTALO_R

27P_0402_50V8J

12

CL13

25MHZ_18PF_7V25000034

@

CL15

1 2

4

UL2

LAN_ACTLED_YEL#

LED_MASK# <31,38>

CLKREQ_PCIE#4< 11>

CLK_PCIE_P4<11>
CLK_PCIE_N4<11>

PCIE_PRX_DTX_P4<10>

PCIE_PRX_DTX_N4<10>

PCIE_PTX_DRX_P4<10>

PCIE_PTX_DRX_N4<10>

RL5 @

RL9@

SML0_SMBDATA<8>

LAN_WAKE#<11,31>

SMBus Device Address 0xC8

1 2

@

RL34 0_0402_5%

YL1

1

3

IN

OUT

2

4

GND

GND

LOM_CABLE_DETECT# <31>

PLTRST_LAN#<11>

SML0_SMBCLK<8>

T88@ PAD~D
T89@ PAD~D

12

12

CLKREQ_PCIE#4

PCIE_PRX_C_DTX_P4

1 2

CL1 0.1U_0402_25V6

PCIE_PRX_C_DTX_N4

1 2

CL2 0.1U_0402_25V6

PCIE_PTX_C_DRX_P4

1 2

CL5 0.1U_0402_25V6

PCIE_PTX_C_DRX_N4

1 2

CL6 0.1U_0402_25V6

RL11
1M_0402_5%

27P_0402_50V8J

CL14

0.1U_0201_10V6K

0.1U_0201_10V6K

12

12

CL16

CL17

0.1U_0201_10V6K

0.1U_0201_10V6K

12

CL20

LAN_DISABLE#_R

LOM_ACTLED_YEL#
LOM_SPD100LED_ORG#
LOM_SPD10LED_GRN#

TP_LAN_JTAG_TDI
TP_LAN_JTAG_TDO
TP_LAN_JTAG_TMS
TP_LAN_JTAG_TCK

LAN_TEST_EN

3.01K_0402_1%

1K_0402_5%

12

12

RL13

RL12

LAN_MDIN3_L

LAN_MDIP3_L

LAN_MDIN1_L

LAN_MDIP1_L

LAN_MDIN2_L

LAN_MDIP2_L

LAN_MDIN0_L

12

CL21

LAN_MDIP0_L

4

UL1

48

CLK_REQ_N

36

PE_RST_N

44

PE_CLKP

45

PE_CLKN

38

PETp

39

PETn

41

PERp

42

PERn

28

SMB_CLK

31

SMB_DATA

2

LANWAKE_N

3

LAN_DISABLE_N

26

LED0

27

LED1

25

LED2

32

JTAG_TDI

34

JTAG_TDO

33

JTAG_TMS

35

JTAG_TCK

9

XTALO

XTAL_OUT

10

XTALI

XTAL_IN

30

TEST_EN

12

RBIAS

WGI219LM-QREF- A0_QFN48_6X6~D

change to SA000081G1L ,(S IC W GI219LM SLKJ2 A0 QFN 48P PHY A31 !)

JTAG LED

MDI

PCIE

RSVD_VCC3P3_1

SMBUS

MDI_PLUS0

MDI_MINUS0

MDI_PLUS1

MDI_MINUS1

MDI_PLUS2

MDI_MINUS2

MDI_PLUS3

MDI_MINUS3

SVR_EN_N

VDD3P3_IN

VDD3P3_4

VDD3P3_15
VDD3P3_19
VDD3P3_29

VDD0P9_47
VDD0P9_46
VDD0P9_37

VDD0P9_43

VDD0P9_11

VDD0P9_40
VDD0P9_22
VDD0P9_16

VDD0P9_8

CTRL0P9

VSS_EPAD

Place CL3, CL4 and LL1 close to UL1

1

TD1+

2

TD1-

3

TDCT1

4

TDCT2

5

TD2+

6

TD2-

7

TD3+

8

TD3-

9

TDCT3

10

TDCT4

11

TD4+

12

TD4-

TL1

MHPC_NS692417

GND

GND
CHASSIS

CHASSIS

1:1

1:1

1:1

1:1

1 2

EMI@

CL22 10P_1808_3KV8J

0601:EMI ask to change 150pF

LAN_MDIP0

13

LAN_MDIN0

14

LAN_MDIP1

17

LAN_MDIN1

18

LAN_MDIP2

20

LAN_MDIN2

21

LAN_MDIP3

23

LAN_MDIN3

24

VCT_LAN_R1

6

+RSVD_VCC3P3_1

1

5

4

15
19
29

47
46
37

43

11

40
22
16
8

+REGCTL_PNP10RES_BIAS

7

49

Layout Not i ce : Pl ace bead as
close UL4 as possible

RL71
RL72

RL73
RL74

RL75
RL76

RL77
RL78

1 2

+3.3V_LAN_OUT

+0.9V_LAN

1 2

Idc_min=5 00mA
DCR=100 mohm

RJ45_MDIN3

24

TX1+

RJ45_MDIP3

23

TX1-

22

TXCT1

21

RJ45_MDIN1

TXCT2

20

TX2+

RJ45_MDIP1

19

TX2-

RJ45_MDIN2

18

TX3+

RJ45_MDIP2

17

TX3-

16

TXCT3

15

RJ45_MDIN0

TXCT4

14

TX4+

RJ45_MDIP0

13

TX4-

+GND_CHASSIS

use 40mil trace if necessary

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

0.1U_0201_10V6K

12

LL14.7UH +-20% MPB201210T-4R7M-NA2

Z2806

Z2808

CL7

Z2807

3

@

RL30_0402_5%

22U_0805_6.3V6M

1

2

+0.9V_LAN

0.1U_0201_10V6K

1

2

Z2805

2.2_0603_5%

2.2_0603_5%

2.2_0603_5%

2.2_0603_5%

2.2_0603_5%

2.2_0603_5%

2.2_0603_5%

2.2_0603_5%

1 2

1 2

CL28

Place C L28 close to UL1.5

10U_0603_10V6M

@

CL3

CL4

12

12

12

12

12

RL17 75_0402_1%

RL16 75_0402_1%

RL15 75_0402_1%

RL18 75_0402_1%

RL64.7K_0402_5%

LAN_MDIP0_L
LAN_MDIN0_L

LAN_MDIP1_L
LAN_MDIN1_L

LAN_MDIP2_L
LAN_MDIN2_L

LAN_MDIP3_L
LAN_MDIN3_L

@

RL80_0603_5%

+3.3V_LAN

+3.3V_LAN

2

RF Request

+3.3V_LAN_OUT

@RF@

@RF@

12P_0402_50V8J

82P_0402_50V8J

1

1

CL29

CL30

2

2

470P_0402_50V7K

1

12

CL18

2

LAN_ACTLED_YEL# LAN_ACTLED_YEL_R#

LED_10_GRN# LED_10_GRN_R#

LED_100_ORG# LED_100_ORG_R#

1 2

RL14 150_040 2_5%

RJ45_MDIN3

RJ45_MDIP3

RJ45_MDIN1

RJ45_MDIN2

RJ45_MDIP2

RJ45_MDIP1

RJ45_MDIN0

RJ45_MDIP0

1 2

RL19 150_0402_5%

1 2

RL20 150_0402_5%

0.1U_0201_10V6K

+3.3V_LAN

CL19

RJ45 LOM circuit

10

9

8

7

6

5

4

3

2

1

11

13

12

Link DC231603220 (temp) DONE

+3.3V_LAN:20mils

JLOM1

CONN@

Yellow LED-

Yellow LED+

PR4-

PR4+

PR2-

PR3-

PR3+

PR2+

PR1-

PR1+

Green LED-

Orange LED-

Green-Orange LED+

SANTA_130470-19

GND

GND

GND

GND

1

17

16

15

14

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS D OCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL . IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

3

PARTY WITHOUT DE LL'S EXPRESS WRITTEN CONSENT.

2

Title

Size

Size

Size

Date : Sheet

Date : Sheet

Date : Sheet

Compal Electronics, Inc.

LAN Clarkvillie & RJ45

LAN Clarkvillie & RJ45

LAN Clarkvillie & RJ45

Document Number Re v

Document Number Re v

Document Number Re v

LA-F312P

LA-F312P

LA-F312P

1

27 58Wednesday, December 20, 2017

27 58Wednesday, December 20, 2017

27 58Wednesday, December 20, 2017

of

of

of

2.0

2.0

2.0

A

B

C

D

E

For PCIE Interface

1 1

+3.3V_MMI_IN+3.3V_RUN

PJP14

RF Request

+3.3V_MMI_IN+3.3V_MMI_AUX

@RF@

@RF@

12P_0402_50V8J

82P_0402_50V8J

1

1

CR27

CR28

2

2

2 2

@RF@

@RF@

82P_0402_50V8J

12P_0402_50V8J

1

1

CR26

CR25

2

2

1 2

@

RR274 0_0603_5%

+3.3V_MMI_AUX

RR19 10K_0402_5%

PAD-OPEN1x2m

1 2

12

+3.3V_MMI_AUX+3.3V_MMI_IN

MEDIACARD_IRQ#

support D3 Hot(if D3 cold PIN11,PIN27 need Add MOS on/of f 3V3A UX)

7/18 Vender suggest.

PCH_PLTRST#_AND<11,29,33,34>

CLKREQ_PCIE#0< 11>

CLK_PCIE_P0<11>
CLK_PCIE_N0<11>

1 2

PCIE_PTX_DRX_P1<10>
PCIE_PTX_DRX_N1<10>
PCIE_PRX_DTX_P1<10>
PCIE_PRX_DTX_N1<10>

CR11 0.1U_0402_25V6
CR12 0.1U_0402_25V6
CR13 0.1U_0402_25V6
CR14 0.1U_0402_25V6

+1.2V_LDO

CR13 close to UR2.10
CR9 CR10 close to UR2.14

4.7U_0603_6.3V6K

0.1U_0201_10V6K

1

CR5

12

2

1 2
1 2
1 2

CR6

MEDIACARD_IRQ#<9>

0.1U_0201_10V6K

+1.8V_RUN_CARD

1

CR7

2

PCIE_PTX_C_DRX_P1
PCIE_PTX_C_DRX_N1
PCIE_PRX_C_DTX_P1
PCIE_PRX_C_DTX_N1

SD/MMCCD#

12

+RREF

RR4

6.2K_0402_1%

+3.3V_MMI_AUX

4.7U_0402_6.3V6M

1

CR1

2

UR1

1

PERST#

2

CLK_REQ#

5

REFCLKP

6

REFCLKN

3

HSIP

4

HSIN

7

HSOP

8

HSON

32

WAKE#

31

MS_INS#

30

SD_CD#

10

AV12

14

DV12S

13

SD_VDD2

9

RREF

1

2

0.1U_0201_10V6K

CR2

11

27

3V3_IN

CARD_3V3

3V3aux

RTS5242

SD_LN1_P

SD_LN1_M

SD_LN0_P

SD_LN0_M

E-PAD

RTS5242-GR_QFN32_4X4

33

+3.3V_MMI_IN

0.1U_0201_10V6K

1

CR3

2

DV33_18

SDREG2

GPIO

1

2

SP1
SP2
SP3
SP4
SP5
SP6
SP7

10U_0402_6.3V6M

CR4

12

+DV33_18

18

15

SD/MMCDAT1/RCLK-

16

SD/MMCDAT0/RCLK+

17

SD/MMCCLK

19

SD/MMCCMD

20

SD/MMCDAT3

21

SD/MMCDAT2

29

SDWP

SD_UHS2_D1P

22

SD_UHS2_D1N

23

SD_UHS2_D0P

26

SD_UHS2_D0N

25

24

+SDREG2

28

SD_GPIO

+3.3V_RUN_CARD

@
@

@EMI@

@
@
@

7/18 Vender suggest

1 2

CR15

1U_0402_6.3V6K

12

RR310K_0402_5%

1 2

CR22 1U_0402_6.3V 6K

1 2

RR9 0_0402_5%

1 2

RR10 0_0402_5%

1 2

RR5 0_0402_5%

1 2

RR6 0_0402_5%

1 2

RR7 0_0402_5%

1 2

RR8 0_0402_5%

+3.3V_MMI_AUX

SD/MMCDAT1/RCLK-_R
SD/MMCDAT0/RCLK+_R

SD/MMCCLK_R
SD/MMCCMD_R
SD/MMCDAT3_R
SD/MMCDAT2_R

@EMI@

5P_0402_50V8C

12

CR21

EMI depop locat i on

3 3

HOST_SD_W P#

High

Low

SDWP _Q SDWP

Low

Low

Low

High Write Protect(FW LOCK)

STATUS

Write Enable

QR1

L2N7002WT1G_SC-70-3

SDWP_Q

1 3

SDWP

D

S

G

HOST_SD_WP#<12>

2

+3.3V_RUN_CARD +1.8V_RUN_CARD

2

CR17

1 2

CR18

1

0.1U_0201_10V6K

4.7U_0603_6.3V6K

+3.3V_RUN_CARD
+1.8V_RUN_CARD

2

CR19

1

0.1U_0201_10V6K

SD/MMCCMD_R
SD/MMCCLK_R

SD/MMCCD#

SD/MMCDAT0/RCLK+_R
SD/MMCDAT1/RCLK-_R
SD/MMCDAT2_R
SD/MMCDAT3_R

SD_UHS2_D0P
SD_UHS2_D0N
SD_UHS2_D1P
SD_UHS2_D1N

CR20

1 2

4.7U_0603_6.3V6K

JSD1

CONN@

4

VDD1

15

VDD2

3

CMD

5

CLK

9

CD

16

SWIO

7

DAT0/RCLK+

8

DAT1/RCLK-

1

DAT2

2

CD/DAT3

18

D0+

19

D0-

22

D1+

21

D1-

6

VSS1

17

VSS2

20

VSS3

23

VSS4

T-SOL_158-1240902600

GND1
GND2
GND3
GND4
GND5

10
11
12
13
14

CR38,CR39 n ear JSD1.4 CR40,CR41 near JSD1 .14

4 4

LINK SP071603151 (temp) DONE

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS D OCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL . IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

A

B

C

PARTY WITHOUT DE LL'S EXPRESS WRITTEN CONSENT.

D

Title

Size

Size

Size

Date : Sheet

Date : Sheet

Date : Sheet

Compal Electronics, Inc.

Card Reader RTS5242

Card Reader RTS5242

Card Reader RTS5242

Document Number Re v

Document Number Re v

Document Number Re v

LA-F312P

LA-F312P

LA-F312P

E

28 58Wednesday, December 20, 2017

28 58Wednesday, December 20, 2017

28 58Wednesday, December 20, 2017

of

of

of

2.0

2.0

2.0

5

+3.3V_WW AN

NGFF slot B Key B

WWAN_PW R_EN

12

RZ43 47K_0402_5%

D D

Drop HCA function in DVT1.0
NonAR config support SA TA only,

C C

+3.3V_WW AN

.047U_0402_16V7K

.047U_0402_16V7K

33P_0402_50V8J

22U_0603_6.3V6M

12

12

12

12

CZ19

CZ17

B B

CZ20

CZ18

USB3_PTX_DRX_P2<10>

USB3_PTX_DRX_N2<10>

100P_0402_50V8J

RF@

12

SATA_PTX_DRX_N1<10>
SATA_PTX_DRX_P1<10>

33P_0402_50V8J

12

CZ21

USB3_PRX_DTX_P2<10>

USB3_PRX_DTX_N2<10>

NGFF_CONFIG_3<31>

CZ198

NGFF_CONFIG_0<31>
WWAN_W AKE#<31>

SATA_PRX_DTX_P1<10>
SATA_PRX_DTX_N1<10>

1 2

CZ10 0.1U_0402_25V6

1 2

CZ11 0.1U_0402_25V6

NGFF_CONFIG_1<31>

NGFF_CONFIG_2<31>

+3.3V_WW AN

47P_0402_50V8J

RF@

12

12

CZ23

USB3_PTX_C_DRX_P2

12

CI30 0.1U_0402_25V6

USB3_PTX_C_DRX_N2

12

CI29 0.1U_0402_25V6

@RF@

RF Request

100P_0402_50V8J

2200P_0402_50V7K

RF@

RF@

12

CZ24

USB20_P4_L
USB20_N4_L

RZ326 0_0402_5%

USB3_PRX_L_DTX_N2
USB3_PRX_L_DTX_P2

USB3_PTX_L_DRX_N2
USB3_PTX_L_DRX_P2

SATA_PTX_C_DRX_N1

SATA_PTX_C_DRX_P1

@

100U_B2_6.3VM_R35M

RF@

1

+

CZ26

CZ25

2

1 2

RI27 0_0402_5%

@RF@

LI16

1 2

HCM1012GH900BP_4P

1 2

RI28 0_0402_5%

@RF@

1 2

RI29 0_0402_5%

@RF@

HCM1012GH900BP_4P

1 2

LI17

RI30 0_0402_5%

@RF@

12

T225PAD~D

RF@

RF@

1 2

SIM Card Push-Push

CONN@

UIM_DATA

UIM_CLK

+SIM_PWR

UIM_CLK

A A

47P_0402_50V8J

@RF@

12

CZ38

@RF@

51_0402_5%

12

RZ334

UIM_RESET

4.7U_0402_6.3V6M

12

CZ37

SIM_DET

5

RFU1

C7

IO

C6

VPP

C5

GND

C4

RFU2

C3

CLK

C2

RST

C1

VCC

1

DLSW

2

DTSW

JAE_SF51S006V4DR1000Q

SP070017I00 LINK DONE

+SIM_PWR

@RF@

15K_0402_5%

12

RZ335

UIM_DATA UIM_RESET

33P_0402_50V8J

@RF@

12

CZ39

JSIM1

C8

GND1
GND2
GND3
GND4
GND5
GND6
GND7

12

3
4
5
6
7
8
9

+SIM_PWR

33P_0402_50V8J

@RF@

CZ40

RF Request

0.1U_0402_25V6

1

2

4

CONN@

JNGFF2

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

53

53

55

55

57

57

59

59

61

61

63

63

65

65

67

67

69

GND

BELLW_80149-3221

2

2

4

4

6

6

8

8

10

10

12

12

14

14

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

40

42

42

44

44

46

46

48

48

50

50

52

52

54

54

56

56

58

58

60

60

62

62

64

64

66

66

68

GND

80149-3221 LINK DON

WWAN_RADIO_DIS#<31>

GPS_DISABLE#<31>

USB3_PRX_L_DTX_P2

USB3_PRX_L_DTX_N2

34

USB3_PTX_L_DRX_P2

34

USB3_PTX_L_DRX_N2

STATE #

0

1

8

RF@

CZ41

14

15

4

+3.3V_WW AN

WWAN_PW R_EN

WWAN_RADIO_DIS#_R

SLOT2_SATA_LED#

GPS_DISABLE#_R

UIM_RESET
UIM_CLK
UIM_DATA

ISH_I2C2_SCL_R
ISH_I2C2_SDA_R

9/24: Reserve for embedded locat i on ,r ef er I nt el PDG 0.9

PCH_PLTRST#_AND

@

RZ132 0_0402_5%

WWAN_COEX3
WWAN_COEX2
WWAN_COEX1

RN101 0_ 0402_5%@

RZ76 0_0402_5%

@

RZ77 0_0402_5%

@

PCIE_WAKE#

SIM_DET

1 2

12

RZ128 0_0201_5%@RF@
RZ129 0_0201_5%@RF@
RZ130 0_0201_5%@RF@

+SIM_PWR

12
12

HOST_DEBUG_TX <31,32>

1 2
1 2
1 2

E

1 2

DZ5

RB751S40T1G_SOD523-2

1 2

DZ6

RB751S40T1G_SOD523-2

RF Request

1 2

RI47 0_0402_5%

@RF@

CONFIG_1

GND

HIGH

GND

GND

HIGH

MCM1012B900F06BP_4P

1 2

LI8

RF@

1 2

RI48 0_0402_5%

@RF@

CONFIG_2

GND

GND

GND

HIGH

HIGH

USB20_P4<10>

USB20_N4<10>

CONFIG_0

GND

GND

HIGH GND

HIGH

HIGH

SATALED# <10,34,38>

M3042_DEVSLP <10>
ISH_I2C2_SCL <9>
ISH_I2C2_SDA <9>

WLAN_COEX3
WLAN_COEX2
WLAN_COEX1

WWAN_RADIO_DIS#_R

GPS_DISABLE#_R

USB20_P4_L

34

USB20_N4_L

CONFIG_3

GND

GND

HIGH

HIGH

3

WLAN

Module Type

SSD-SATA

SSD-PCIE(2 lane)

WW AN

HCA-PCIE(1 lane)

NA

3

2

1

for no AR,Brekenridge 12/14/15 UMA/Steamboat

NGFF slot A Key A

JNGFF1

CONN@

USB20_P7_L
USB20_N7_L

1 2

PCIE_PTX_DRX_P3<10>
PCIE_PTX_DRX_N3<10>

CZ12 0.1U_0402_25V6

1 2

CZ13 0.1U_0402_25V6

PCIE_PRX_DTX_P3<10>
PCIE_PRX_DTX_N3<10>

CLK_PCIE_P1<11>
CLK_PCIE_N1<11>

CLKREQ_PCIE#1< 11>

PCIE_WAKE#<32,34>

PCIE_PTX_C_DRX_P3
PCIE_PTX_C_DRX_N3

PCIE_WAKE#

1
3
5
7

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75

76

1
3
5
7

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75

GND

LCN_DAN05-67306-0100

SP070019F00 LINK DONE

DZ1

DZ2

RF Request

1 2

RI49 0_0402_5%

@RF@

MCM1012B900F06BP_4P

1 2

LI9

RF@

RI50 0_0402_5%

@RF@

2

WLAN_WIGIG60GHZ_DIS#_R

BT_RADIO_DIS#_R

34

1 2

USB20_P7_L

USB20_N7_L

WLAN_WIGIG60GHZ_DIS#<31>

BT_RADIO_DIS#<31>

USB20_P7<10>

USB20_N7<10>

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS D OCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL . IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DE LL'S EXPRESS WRITTEN CONSENT.

1 2

RB751S40T1G_SOD523-2

1 2

RB751S40T1G_SOD523-2

+3.3V_WLAN

2

2

4

4

6

6

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

40

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74

77

+3.3V_WLAN

12

WLAN_COEX3
WLAN_COEX2
WLAN_COEX1

WIGIG_32KHZ
PCH_PLTRST#_AND
BT_RADIO_DIS#_R
WLAN_WIGIG60GHZ_DIS#_R
ISH_UART0_RXD_R
ISH_UART0_TXD_R
ISH_UART0_CTS#_R
ISH_UART0_RTS#_R
PCH_PLTRST#_AND

PCIE_WAKE#

9/24: Reserve for embedded locat i on ,r ef er I nt el PDG 0.9

0.1U_0201_10V6K

0.01UF_0402_25V7K

1

CZ30

CZ28

2

+3.3V_WLAN

12

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74

GND

Power Rating TBD

Voltag e

PWR

Toleranc e

Rail

+3.3V

DELL CONFIDENTIAL/PROPRIETARY

Title

Title

Title

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

Date : Sheet

Date : Sheet

Date : Sheet

PCH_CL_RST1# <8>

PCH_CL_DATA1 <8>

PCH_CL_CLK1 <8>

@

1 2

RZ56 0_0402_5%

PCH_PLTRST#_AND <11,28,33,34>

RZ78 0_0402_5%

@

RZ79 0_0402_5%

@

RZ80 0_0402_5%

@

RZ81 0_0402_5%

@

0.01UF_0402_25V7K

10U_0603_10V6M

1

12

CZ27

2

Place near JNGFF1.2/JNGFF1.4Place near JNGFF1.72/JNGFF1.74

CZ29

SUSCLK <11,34>

12

ISH_UART0_RXD <9>

12

ISH_UART0_TXD <9>

12

ISH_UART0_CTS# <9>

12

ISH_UART0_RTS# <9>

0.1U_0201_10V6K

4.7U_0603_6.3V6K

1

12

CZ31

CZ32

2

RF Request

15P_0402_50V8J

15P_0402_50V8J

15P_0402_50V8J

RF@

12

CZ33

15P_0402_50V8J

RF@

RF@

RF@

CZ35

12

12

CZ34

CZ36

Primary Power Aux Power

Peak Normal Normal

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

NGFF Card

NGFF Card

NGFF Card

LA-F312P

LA-F312P

LA-F312P

1

29 58Wednesday, December 20, 2017

29 58Wednesday, December 20, 2017

29 58Wednesday, December 20, 2017

2.0

2.0

2.0

of

of

of

5

1W x 1ch, 4ohm (Transducer spec is 8Ohm/0.5Watt per unit, there are two transducer units i n one speaker box.)

Internal Speakers Header

40 mils trace keep 20 mil spacing

1 2

LA6 BL M15PX330SN1D_2P

EMI@

1 2

LA7 BL M15PX330SN1D_2P

INT_SPK_R+
INT_SPK_R-

D D

EMI@

1 2

LA8 BL M15PX330SN1D_2P

EMI@

1 2

LA9 BL M15PX330SN1D_2P

EMI@

@ESD@

1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K

12

1000P_0402_50V7K

12

12

12

CA23@EMI@

CA19@EMI@

CA22@EMI@

CA24@EMI@

DA6

INT_SPKR_L+INT_SPK_L+
INT_SPKR_L-INT_SPK_L­INT_SPKR_R+
INT_SPKR_R-

L03ESDL5V0CC3-2_SOT23-3

2

2

3

1

1

JSPK1

1

1

2

2

3

3

4

4

L03ESDL5V0CC3-2_SOT23-3

5

3

GND

6

@ESD@

GND

ACES_50278-0040N-001

Link SP02001CE00 DONE

DA7

CONN@

Close to UA1

Close to UA1 pin6

HDA_BIT_CLK_R

33_0402_5%

12

RA17@EMI@

10P_0402_50V8J

12

C C

CA33@EMI@

Place closely to Pin 13.

AUD_HP_NB_SENSE

12

place close to UA1 pin3

+3.3V_RUN_AUDIO

100K_0402_1%

12

200K_0402_1%

12

DMIC_CLK0

82P_0402_50V8J

RF@

CA54

RA59

RA60

AUD_SENSE_A

12

+3.3V_RUN_AUDIO

0.1U_0402_25V6

@

CA41

Add for solve
pop noise and
detect issue

4

+3.3V_RUN_AUDIO

1U_0603_10V6K

+3.3V_RUN_AUDIO

100K_0402_5%

RA61

1 2

12

LA12 BLM15PX600SN1D_2P

12

LA14 BLM15PX600SN1D_2P

0.1U_0201_10V6K

1

2

place close to pin1

HDA_SYNC_R<12>

HDA_BIT_CLK_R<12>

HDA_SDOUT_R<12>

RA52100K_0402_5%

12

RA1810K_0402_5%

12

CA31

12

HDA_BIT_CLK_R

Place R A9 close to codec

HDA_SDIN0<12>

DMIC0<26>

DMIC_CLK0 DMIC_CLK_CODEC

DMIC_CLK0<26>

PD#

AUD_SENSE_B

EMI@

10U_0603_10V6M

CA10

12

1 2

RA9 33_0402_5%

1 2

RA14

CA61

HDA_SDOUT_R
HDA_SDIN0_R

22_0402_5%

INT_SPK_L+
INT_SPK_L­INT_SPK_R­INT_SPK_R+

AUD_SENSE_A
AUD_SENSE_B

1

2

12

12

RA44100K_0402_5%

12

CA5110U_0603_10V6M

12

CA5210U_0603_10V6M
CA5310U_0603_10V6M

3

+3.3V_RUN_AUDIO_IO

10U_0603_10V6M

0.1U_0201_10V6K

CA56

CA55

12

place close to pin9

+3.3V_RUN_AUDIO_DVDD

1

9

UA1

DVDD

11

I2C_SDA

12

I2C_SCL

10

SYNC

6

BIT-CLK

5

SDATA-OUT

8

SDATA-IN

4

EAPD/DC DET

2

GPIO0/DMIC-DATA12

3

GPIO1/DMIC-CLK

47

PDB

48

SPDIFO/GPIO2/DMIC-DATA-34/DMIC-CLK-In/MIC-GPI

27

LDO1-CAP

39

LDO2-CAP

7

LDO3-CAP

42

SPK-L+

43

SPK-L-

44

SPK-R-

45

SPK-R+

13

HP/LINE1 JD1

14

MIC2/LINE2 JD2

15

SPDIFO/FRONT JD3/GPIO3

ALC3246-CG_MQFN48_6X6

+5V_RUN_PVDD_L

41

46

PVDD1

DVDD-IO

2

SPKR_R

RING2

SLEEVE

12

SPKR <12>
BEEP <31>

place close to pin46place close to pin41

0.1U_0201_10V6K

10U_0603_10V6M

0.1U_0201_10V6K
CA45

1

2

+VDDA_AVDD1

+1.8V_RUN_AUDIO

26

36

40

AVDD1

AVDD2

PVDD2

CPVDD

LINE1-VREFO-L
LINE1-VREFO-R

MIC2-VREFO

VREF

CBN

5VSTB

CPVEE

MIC2-L/RING2

MIC2-R/SLEEVE

MIC-CAP

LINE2-L

LINE2-R

LINE1-L

LINE1-R

PCBEEP

HP-OUT-L

HP-OUT-R

AVSS1
AVSS2

THERMAL PAD

CA47

1

1

CA46

2

2

31

+LINE1-VREFO-L

30

+LINE1-VREFO-R

29

+MIC2-VREFO

28
35

CA35 2.2U_0402_6.3V6M

37

CBP

CA29 1U_0603_10V6K

20

RA53 0_0402_5%

@

@

RA54 0_0402_5%

34

CA49 1U_0603_10V6K

SLEEVE/RING2 please keep 40 mils trace width

17

RING2

18

SLEEVE

19
24
23

LINE1_L HP_OUT_L

22

LINE1_R

21

AUD_PC_BEEP

16

HP_OUT_L AUD_HP_OUT_L

32

HP_OUT_R

33

25
38
49

LA13

1 2

HCB2012VF-601T20_2P

10U_0603_10V6M

1

CA48

2

place close to pin26

10U_0603_10V6M

12

CA9

place close to pin40

10U_0603_10V6M

CA58

12

1 2

RA57 4.7K_0402_5%

1 2

RA58 4.7K_0402_5%

1 2

12

1 2
1 2

1 2

1 2

1 2
1 2

1 2
1 2

600 Ohm/2A

0.1U_0201_10V6K

CA8

1

2

@

0.1U_0201_10V6K

CA57

1

2

AUD_PC_BEEP SPKR_R

CA2510U_0603_10V6M

CA4310U_0603_10V6M
CA4410U_0603_10V6M

+5V_RUN_AUDIO

0.1U_0201_10V6K

10U_0603_10V6M

CA60

1

1

CA59

2

2

+5V_RUN_AUDIO

LA5

1 2

BLM15PX600SN1D_2P

1 2

RA3 0_0603_5%

AUD_HP_OUT_L
AUD_HP_OUT_R

Place CA29 close to Codec

+5V_ALW
+RTC_CELL

CA27 0.1U_0402_25V6
CA28 0.1U_0402_25V6

HP_OUT_R

AUD_HP_OUT_R

RA716.2_04 02_1%
RA816.2_04 02_1%

+1.8V_RUN

AUD_HP_OUT_L/ AUD_HP_OUT_Rplease keep 15 mils trace width

RA5 2.2K_0402_5%

+MIC2-VREFO

12
12

AUD_HP_OUT_L/ AUD_HP_OUT_Rplease keep 15 mils trace width

RA6 2.2K_0402_5%

BEEP_R

RA12 1K_0402_5%
RA13 1K_0402_5%

1 2

1 2

1 2
1 2

100P_0402_50V8J

12

CA72@

1

10K_0402_5%

@

RA51

+1.8V_RUN_AUDIO

33P_0402_50V8J

1

2

BEEP_R

100P_0402_50V8J

10K_0402_5%

@

12

12

CA62@

RA45

RF Request

+5V_RUN_AUDIO

100P_0402_50V8J

RF@

RF@

12P_0402_50V8J

68P_0402_50V8J

1

1

12

CA78@RF@

CA63

CA64

2

2

RF Request

+1.8V_RUN

RF@

CA69

12P_0402_50V8J

RF@

1

CA65

2

RF Request

+3.3V_RUN_AUDIO

12P_0402_50V8J

RF@

1

CA67

2

68P_0402_50V8J

RF@

1

CA66

2

68P_0402_50V8J

RF@

1

CA68

2

place at AGND and DGND plane

1 2

@

@

@

@

@

UZ5

@

1

VIN1

2

VIN1

3

ON1

4

VBIAS

5

ON2

6

VIN2
VIN27VOUT2

EM5209VF_SON14_2X3

RA35 0_0402_5%

1 2

RA36 0_0402_5%

1 2

RA37 0_0402_5%

1 2

RA38 0_0402_5%

1 2

RA39 0_0402_5%

+3.3V_RUN_AUDIO_UZ5

14

VOUT1

13

VOUT1

12

CT1

11

GND

10

CT2

9

+5V_RUN_AUDIO_UZ5

VOUT2

8

15

GPAD

+3.3V_RUN_AUDIO

12

PAD-OPEN1x1m

@

CZ125 0.1U_0201_10V6K

CZ126

@

CZ127

@

1 2

CZ128 0.1U_0201_10V6K

@

PJP19

1 2

PAD-OPEN1x1m

+5V_RUN

PJP15@

+3.3V_RUN +3.3V_RUN_AUDIO

1 2

1 2

1000P_0402_50V7K

1 2

220P_0402_50V7K

PJP16@

PAD-OPEN1x1m

1 2

B B

Power sequence +5V_RUN_AUDIO(501us) > +3.3V_RUN_AUDIO(1204 us) > +1.5V_RUN

Reserve for support D3 cold

+3.3V_RUN

A A

AUD_PWR_EN<12>

+5V_ALW

+5V_RUN

5

CLASS-D POWER DOWN CONTROL CIRCUIT

NB_MUTE#<31>

HDA_RST#_R<12>

HDA_Link is 3.3V,no need level shi ft circuit

PJP17

1 2

+5V_RUN_AUDIO

PAD-OPEN1x2m

1 2

PAD-OPEN1x1m

+5V_RUN_AUDIO

PJP18

2.5A

500mA

4

1 2

@

RA48 0_0 402_5%

DA8

@

RB751S40T1G_SOD523-2

1 2

RA50 0_0402_5%@

21

RE313 @one control line if DVDD is 3.3V
DE2@two control lines1

Add t his Filter to avoid other
components/chips be influenced

@ESD@

680P_0402_50V7K

ESD@

DA1

AZ5123-02S.R7G_SOT23-3

3

1

2017/01/01

2017/01/01

2017/01/01

ESD@

2

DA2

1

CA13

2

AUD_HP_NB_SENSE

2

AZ5125-02S.R7G_SOT23-3

PD#

2016/01/01

2016/01/01

2016/01/01

RING2_R
AUD_HP_OUT_L1

AUD_HP_OUT_R1
SLEEVE_R

680P_0402_50V7K

ESD@

1

2

CA1

2

1

Compal Secret Data

Compal Secret Data

Compal Secret Data

2

EMI@

330P_0402_50V8J

CA2

EMI@

330P_0402_50V8J

680P_0402_50V7K

1

1

CA3

2

2

Deciphered Date

Deciphered Date

Deciphered Date

ESD@

2

3

CA4

1

RING2
AUD_HP_OUT_L

AUD_HP_OUT_R

SLEEVE

3

1 2

LA10 BLM15PX330SN1D_2P

ESD@

@EMI@

1 2

RA55 0_0402_5%

Only BR15U UMA use LA2,LA3,because 6L

@EMI@

1 2

RA56 0_0402_5%

1 2

LA11 BLM15PX330SN1D_2P

ESD@

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECT RONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECT RONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECT RONICS, INC.

HP-Out-Right

HP-Out-L ef t

Universal Jack

ESD@

3

DA3

@ESD@

680P_0402_50V7K

AZ5123-02S.R7G_SOT23-3

1

CA12

2

1

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Codec ALC3246

Codec ALC3246

Codec ALC3246

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

C

C

C

LA-F312P

LA-F312P

LA-F312P

Wednesday, December 20, 2017

Wednesday, December 20, 2017

Wednesday, December 20, 2017

Date : Sheet of

Date : Sheet of

Date : Sheet of

Nokia-MIC

iPhone-MIC

Global Headset

JHP1

CONN@

7

GND

4

#4 G/M

1

#1 L/R

5

#5

6

#6 AGND

2

#2 R/L

3

#3 M/G

SINGA_2SJ3095-085111F

Link DC23000DG10 DONE

1

Norma l
Open

30 58

30 58

30 58

2.0

2.0

2.0

5

+RTC_CELL

+3.3V_ALW_UE1

+3.3V_ALW

+3.3V_ALW_UE1

D D

0.1U_0201_10V6K

CE19

1

1

2

2

close to pin G8/M9

RF Request

+3.3V_ALW

0.1U_0201_10V6K

+3.3V_ALW_UE1

CE20

+3.3V_ALW_UE1

12

1 2

10U_0603_6.3V6M

CE16

0.1U_0201_10V6K

1

CE15

PJP22

PAD-OPEN1x1m

2

68P_0402_50V8J

12P_0402_50V8J

RF@

RF@

1

1

CE60

CE59

2

2

PJP20

+1.8V_PRIM

C C

+3.3V_ALW

+3.3V_ALW

@

RE526 10K_0402_5%

RE532 4.7K_0402_5%

B B

A A

1 2

1

PAD-OPEN1x1m

CE22

0.1U_0201_10V6K

2

PJP21

@

1 2

PAD-OPEN1x1m

RPE10

1

8

2

7

3456

100K_0804_8P4R_5%

1 2

RE95 100K_0402_5%

@

USH_DET#

1 2

BCM5882_ALERT#

1 2

+1.8V_3.3V_ALW_VTR3

12

@

RE549
100K_0402_5%

ENABLE_DS#

12

RE550
100K_0402_5%

MEC_XTAL1 MEC_XTAL2

10P_0402_50V8J

32.768KHZ_9PF_X1A000141000200

12

CE28

Close to pin H1

SLP_WLAN#_GATE<39>

+1.8V_3.3V_ALW_VTR3

CV2_ON_R
IMVP_VR_ON_EC

RUN_ON_EC

TBT_RESET_N_EC_R

Deep Sle ep support

non Deep Sleep

Deep Sleep

MEC_XTAL2_R

32 KHz Clock

YE1

1 2

5

VCCST_PWRGD<11,14,32>

CE21

1

0.1U_0201_10V6K

Close to pin N5

2

+3.3V_ALW2

+3.3V_ALW

@

1

0

12

@

RE290
0_0402_5%

8/28 schematic review

10P_0402_50V8J

12

1 2

@

RE32 0_0402_5%

0.1U_0201_10V6K

CE13

1

2

12

RE314100_0402_1%

22U_0603_6.3V6M

@

1

CE17

2

+VSS_PLL

PCH_DPWROK<11>

SIO_SLP_SUS#<11>

1 2

@

RE308 0_0402_5%

1 2

@

RE552 0_0402_5%

@

T141

PAD~D

@

T142

PAD~D

1 2

RE362 100K_0402_5%

SB12 only for w ireless charger

12

RE57 1K_0402_5%

@

T144

PAD~D

SYS_PWROK<11,14>

@SHORT PADS~D

CE29

1U_0402_6.3V6K

CE14

1

12

2

0.1U_0201_10V6K

1

CE18

2

@DS3@

RE536 0_0402_5%

DS3@

RE349 43K_0402_1%

change to PS2

3.3V_ALW2

T143

12

100K_0402_5%

RE58

1

1

JTAG1 CONN@

2

2

0.1U_0201_10V6K

CE23

1 2

1 2

WLAN_WIGIG60GHZ_DIS#<29>

CLK_TP_SIO_I2C_DAT<37>
DAT_TP_SIO_I2C_CLK<37>

@

PAD~D

@

1 2

RE548 0_0402_5%

+3.3V_ALW

1 2

1U_0402_6.3V6K

12

12

CE30

+3.3V_ALW_UE1

+1.8V_3.3V_ALW_VTR3

RUN_ON_EC<32>

SIO_EXT_WAKE#<9>

BT_RADIO_DIS#<29>

PBAT_PRES#<40,49>

PCH_ALW_ON<39>
AC_PRESENT<11>

SML1_SMBDATA<8>

SML1_SMBCLK<8>

WWAN_W AKE#<29>

SUSACK#<11>

SIO_PWRBTN#<11,14>

LID_CL_SIO#< 32>

JTAG_TDI<32>

JTAG_TDO<32>

JTAG_CLK< 32>

JTAG_TMS<32>

TACH_FAN1<32>

LCD_TST<26>

PWM_FAN1<32>

PCH_RSMRST#<37>

BIA_PWM_EC<26>

HW_ACAVIN_NB<40,49,50>

PANEL_BKEN_EC<26>

SIO_SLP_WLAN#<11,39>

AC_DIS<49>

BCM5882_ALERT#<33>

MSCLK<32>

MSDATA<32>

NB_MUTE#<30>

EN_INVPWR< 26>

IMVP_VR_ON_EC<32>

SIO_SLP_S3#<11,32>
SIO_SLP_S5#<11>

@

T264

PAD~D

AC_DISC#<40,50>
USH_DET#<33>

WWAN_RADIO_DIS#<29>

BC_DAT_ECE1117<37>

BC_CLK_ECE1117<37>

NGFF_CONFIG_3<29>

VBUS2_ECOK<40,50>
ESPI_RESET#<8,32>

ESPI_ALERT#<8>

PCH_PLTRST#_5105<32>

ESPI_CLK_5105<8,32>

ESPI_CS#<8,32>

ESPI_IO0<8,32>
ESPI_IO1<8,32>
ESPI_IO2<8,32>
ESPI_IO3<8,32>

DCIN2_EN<40>

100K_0402_5%

RE63

JTAG_RST#

100_0402_1%

RE65@

4

PS_ID<40>

BEEP<30>

4

+RTC_CELL_VBAT

0.1U_0201_10V6K
CE11

1

2

+3.3V_EC_PLL

PCH_DPWROK_EC

RUN_ON_EC

BT_RADIO_DIS#

SIO_SLP_SUS#_R
PCH_ALW_ON

WWAN_W AKE#

JTAG_TDI
JTAG_TDO
JTAG_CLK
JTAG_TMS
JTAG_RST#

GPIO051

LCD_TST

GPIO054

PCH_RSMRST#

TBT_RESET_N_EC_R

AC_DIS

MSCLK
MSDATA

EN_INVPWR

RESET_IN#

IMVP_VR_ON_ECPCH_ALW_ON

VBUS3_ECOK

GPU_PWR_LEVEL

RTCRST_ON
WWAN_RADIO_DIS#

GPIO011
VBUS2_ECOK

ENABLE_DS#

GPIO100
RESET_OUTSYS_PWROK

MEC_XTAL1
MEC_XTAL2_R

A2

B7

K2

F1

H1

G8
M9
N5

F8
E8

M12

C2

F9
N4
M8

K8

E11

D8

M13

K12
L13
K11
K10
N11
E10
C12

E9

F6
C8
C5

G13

E3
D1
M2

L10
L11

M5

J8
N1

L8
N6

J9

H11

D9

H12

G10

H10

G9

A4

B2
C1
N7

K9
N8

F13
E13
C13
E12

F11
F12
D12
D13

F4

B1

K7
N3

K6
H7

K1
G7
H6

K5

L4
G6

L5

L2
M1
G4

L12

A1

A3

For EMI request

ESPI_CLK_5105

33_0402_5%

@EMI@

12

RE350

33P_0402_50V8J

@EMI@

12

CE57

3

GPIO223

GPIO224

eSPI

NA NANA

LPC

SHD_I O0

GPIO204

NA

eSPI

RSMRST#

LPC

For EVT/DVT1.0 Only,SA00009GL10, S IC MEC5105K-TMP2-TN WFBGA 169P EC
After DVT1.1,SA00009GL00, S IC MEC5105K-D1-TN WFBGA 169P EC

UE1

VBAT

VTR_ANALOG

VREF_ADC

VTR_PLL

VTR_REG

VTR1
VTR2
VTR3

GPIO020
GPIO045
GPIO120
GPIO166
GPIO175
GPIO230
GPIO231
GPIO233

GPIO007/SMB03_DATA/PS2_CLK0B
GPIO010/SMB03_CLK/PS2_DAT0B
GPIO110/PS2_CLK2
GPIO111/PS2_DAT2
GPIO112/PS2_CLK1A
GPIO113/PS2_DAT1A
GPIO114/PS2_CLK0A/nEC_SCI
GPIO115/PS2_DAT0A
GPIO154/SMB02_DATA/PS2_CLK1B
GPIO155/SMB02_CLK/PS2_DAT1B

GPIO145/SMB09_DATA/JTAG_TDI
GPIO146/SMB09_CLK/JTAG_TDO
GPIO147/SMB08_DATA/JTAG_CLK
GPIO150/SMB08_CLK/JTAG_TMS
JTAG_RST#

GPIO050/FAN_TACH0/GTACH0
GPIO051/FAN_TACH1/GTACH1
GPIO052/FAN_TACH2/LRESET#
GPIO053/PWM0/GPWM0
GPIO054/PWM1/GPWM1
GPIO055/PWM2/SHD_CS#/(RSMRST#)
GPIO056/PWM3/SHD_CLK
GPIO001/PWM4
GPIO002/PWM5
GPIO014/PWM6/GPTP-IN6
GPIO015/PWM7
GPIO035/PWM8/CTOUT1
GPIO133/PWM9
GPIO134/PWM10/UART1_RTS#
GPIO135/UART1_CTS#
GPIO170/TFDP_CLK/UART1_TX
GPIO171/TFDP_DATA/UART1_RX

GPIO022/GPTP-IN0
GPIO023/GPTP-IN1
GPIO024/nRESETI
GPIO031/GPTP-OUT1
GPIO032/GPTP-OUT0
GPI0040/GPTP-OUT2

GPIO121/PVT_IO0
GPIO124/GPTP-OUT6/PVT_CS#
GPIO125/GPTP-OUT5/PVT_CLK
GPIO126/PVT_IO3

GPIO122/BCM0_DAT/PVT_IO1
GPIO123/BCM0_CLK/PVT_IO2
GPIO046/BCM1_DAT
GPIO047/BCM1_CLK

GPIO041/SYS_SHDN#
SYSPWR_PRES
GPIO011/nSMI
GPIO021/LPCPD#
GPIO061/LPCPD#/ESPI_RESET#
GPIO063/SER_IRQ/ESPI_ALERT#
GPIO064/LRESET#
GPIO065/PCI_CLK/ESPI_CLK
GPIO066/LFRAME#/ESPI_CS#
GPIO070/LAD0/ESPI_IO0
GPIO071/LAD1/ESPI_IO1
GPIO072/LAD2/ESPI_IO2
GPIO073/LAD3/ESPI_IO3
GPIO067/CLKRUN#
GPIO100/nEC_SCI
GPIO106/PWROK
GPIO107/nSMI

XTAL1
XTAL2

SHD_I O1

GPIO011

NA NA

SIO_EXT_SMI#

VSS1

A6

RUN_ON<17,32,39,44>

GPIO227

*PRIM_ PWRG D N A

SHD_I O2

* For Version B IC

GPIO100

VSS2

A13

RUN_ON#<39>

GPIO056

GPIO016

SHD_CL K

SHD_I O3

GPIO021
SIO_R CIN#

SIO_EXT_SC I#

LPCPD #

GPIO034/RC_ID1/SPI0_CLK

GPIO036/RC_ID2/SPI0_MISO

GPIO003/SMB00_DATA/SPI0_CS#

GPIO004/SMB00_CLK/SPI0_MOSI

GPIO060/KBRST/48MHZ_OUT

GPIO127/A20M/UART0_CTS#

GPIO025/TIN0/nEM_INT/UART_CLK

GPIO005/SMB01_DATA/GPTP-OUT4

GPIO006/SMB01_CLK/GPTP-OUT7

GPIO012/SMB07_DATA/TOUT3

GPIO013/SMB07_CLK/TOUT2

GPIO130/SMB10_DATA/TOUT1

GPIO131/SMB10_CLK/TOUT0

GPIO141/SMB05_DATA/SPI1_CLK/UART0_DCD#

GPIO143/SMB04_DATA/SPI1_MISO/UART0_DTR#

GPIO140/SMB06_CLK/ICT5

GPIO142/SMB05_CLK/SPI1_MOSI/UART0_DSR#

GPIO144/SMB04_CLK/SPI1_CS#/UART0_RI#

GPIO224/GPTP-IN4/SHD_IO1

GPIO016/GPTP-IN7/SHD_IO3/ICT3

GPIO165/32KHZ_IN/CTOUT0

GPIO221/GPTP-IN3/32KHZ_OUT

GPIO042/PECI_DAT/SB-TSI_DAT

GPIO160/PWM11/PROCHOT#

VSS_ADCH4VR_CAPJ1VSS_PLL

+3.3V_ALW

RE68

1 2

61

+VR_CAP

12

100K_0402_5%

DMN65D8LDW-7_SOT363-6

CE31 1U_0402_6.3V6K

RUN_ON#

QE2A

VSS_ANALOG

C4

RUNPWROK

5

G1

+VSS_PLL

+3.3V_RUN

RE67

VSS3

E6

2

3

GPIO055
PCH_RSM RST#
SHD_CS #

GPIO067

NA

CLKRU N#

GPIO033/RC_ID0

GPIO057/VCC_PWRGD

GPIO104/UART0_TX

GPIO105/UART0_RX

GPIO225/UART0_RTS#

GPIO026/TIN1
GPIO027/TIN2
GPIO030/TIN3

GPIO017/GPTP-IN5

GPIO151/ICT4

GPIO152/GPTP-OUT3

GPIO156/LED0
GPIO157/LED1
GPIO153/LED2
GPIO226/LED3

GPIO132/SMB06_DATA

GPIO200/ADC00
GPIO201/ADC01
GPIO202/ADC02
GPIO203/ADC03
GPIO204/ADC04
GPIO205/ADC05
GPIO206/ADC06
GPIO207/ADC07
GPIO210/ADC08
GPIO211/ADC09
GPIO212/ADC10
GPIO213/ADC11
GPIO214/ADC12
GPIO215/ADC13
GPIO216/ADC14
GPIO217/ADC15

GPIO222/SER_IRQ
GPIO223/SHD_IO0

GPIO227/SHD_IO2

GPIO164/VCI_OVRD_IN

VCI_OUT
GPIO163/VCI_IN0#
GPIO162/VCI_IN1#
GPIO161/VCI_IN2#
GPIO000/VCI_IN3#

GPIO044/VREF_VTT

GPIO043/SB-TSI_CLK

DN1_DP1A
DP1_DN1A
DN2_DP2A
DP2_DN2A
DN3_DP3A
DP3_DN3A
DN4_DP4A
DP4_DN4A

GPIO103/THERMTRIP2#

THERMTRIP1#

MEC5105_WFBGA169_11X11

10K_0402_5%

1 2

DMN65D8LDW-7_SOT363-6

34

QE2B

F2
J10
J13
E7
D7

G3
H5
G11
G12
B13
F10

N13
N12
M11
H9

L9
M10
N9

C11
D10
D11
E1

E5
B3
M7
M4
M3
N2
N10
A12
B6
F7
B4
C3

J4
J5
J6
G2
H2
J2
J3
K3
D3
D2
E2
G5
F5
K4
L1
L3

H8
J7
L6
L7
M6

D6

BGPO0

C7
A5
D5
B5
D4
E4

C6

F3

J11
K13
J12
A8
A7
A10
A9
B9
B8
A11
B10
C10

VIN

C9

VSET

B11

VCP

H3
B12
H13

12

L2N7002WT1G_SC-70-3

TYPEC_ID
SYSTEM_ID
BOARD_ID
UPD2_SMBDAT
UPD2_SMBCLK

GPS_DISABLE#

UPD1_SMBINT#

PCIE_WAKE#_R

VGA_IDENTIFY

DGPU_PWROKVCCST_PWRGD_EC
PBAT_CHARGER_SMBDAT
PBAT_CHARGER_SMBCLK

GPU_SMDAT
GPU_SMCLK
UPD1_SMBDAT
UPD1_SMBCLK

I_BATT_R
I_SYS_R
DCIN3_EN

USH_PWR_STATE#
USB_POWERSHARE_VBUS_EN
USB_POWERSHARE_EN#
USB_PWR_EN1#

USB_PWR_EN2#
UPD2_SMBINT#

CV2_ON_R

3.3V_TS_EN
MASK_SATA_LED#

1.8V_PRIM_PWRGD
VBUS1_ECOK

VCI_IN1#
VCI_IN2#
POA_WAKE#

32KHZ_OUT

+PECI_VREF
PECI_EC_R
M3042_PCIE#_SATA
REM_DIODE1_N
REM_DIODE1_P
REM_DIODE2_N
REM_DIODE2_P

REM_DIODE4_N
REM_DIODE4_P
+VR_CAP
VSET_5105

THERMTRIP2#
THERMTRIP1#

PROCHOT#_R1

1U_0402_6.3V6K

CE63

QE17

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS D OCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL . IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DE LL'S EXPRESS WRITTEN CONSENT.

TYPEC_ID <32>
SYSTEM_ID <32>
BOARD_ID <32>

RUNPWROK <14>
GPS_DISABLE# <29>
HOST_DEBUG_TX <29,32>
ME_FWP <12>
ME_SUS_PWR_ACK <11>
UPD1_SMBINT# <23>

PCIE_WAKE#_R <32>
SIO_SLP_S4# <11,17,42,45>
SIO_SLP_A# <11>
SIO_SLP_LAN# <11,39>

NGFF_CONFIG_1 <29>
NGFF_CONFIG_0 <29>

BREATH_LED# <38>
BAT1_LED# <38>
BAT2_LED# <38>
LCD_VCC_TEST_EN <26>

USH_EXPANDER_SMBDAT <33>
USH_EXPANDER_SMBCLK <33>
VCCDSW_EN <11>

PBAT_CHARGER_SMBDAT <40,49>
PBAT_CHARGER_SMBCLK <40,49>
NGFF_CONFIG_2 <29>
LED_MASK# <27,38>

UPD1_SMBDAT <23>
UPD1_SMBCLK <23>

1 2

RE64 300_0402_5%

1 2

RE312 300_0402_5%

@

1 2

RE318 0_0402_5%

USH_PWR_STATE# < 33>

USB_POWERSHARE_EN# <35>
USB_PWR_EN1# <36>
AUX_EN_WOWL <39>

LOM_CABLE_DETECT# <27>

BC_INT#_ECE1117 <37>

DCIN1_EN < 50>

PCH_PCIE_WAKE# <11,32>

LAN_WAKE# <11,27>

1 2

RE539 100_0402_5%

3.3V_TS_EN <26>
MASK_SATA_LED# <38>

1.8V_PRIM_PWRGD <45>
VBUS1_ECOK <50>

EC_FPM_EN <33>

ACAV_IN <49>
ALWON <41>
POWER_SW_IN# <32>

POA_WAKE# <33>

3.3V_WWA N_EN <39>

1 2

CE54 10P_0402_50V8J

@

1 2

RE60 43_0402_5%

1 2

CE24 2200P_0402_50V7K

1 2

CE26 2200P_0402_50V7K

1 2

CE27 2200P_0402_50V7K

VSET_5105 <32>

I_ADP <49>

THERMTRIP2# <32>

1 2

RE288 100_0402_5%

10K_0402_5%

12

RE546

2 1

RB751S40T1G_SOD523-2

13

D

S

RTCRST_ON_R

2

G

RE543

1 2

1M_0402_5%

22P_0402_50V8J

12

CE65

2

PAD~D

I_BATT <49>
I_SYS <46,49>

PAD~D

USB_POWERSHARE_VBUS_EN <35>

DE2

TOUCHPAD_INTR# <12,37>

M3042_PCIE#_SATA <10>

QE15

LP2301ALT1G_SOT23-3

123

D

S

G

100K_0402_5%

RE541

CV2_ON <33>

PECI_EC <12>

PROCHOT# <12,46,49>

1 2

2

VCCDSW_EN

0.1U_0402_25V6

@

T147

12

SB12 only for w ireless charger

@

T262

RE59 close to UE2 at least 250mils

+PECI_VREF

@

RE59 0_0402_5%

0.1U_0201_10V6K

CE25

12

REM_DIODE1_N
REM_DIODE1_P
REM_DIODE2_N
REM_DIODE2_P

REM_DIODE4_N
REM_DIODE4_P

+RTC_CELL+RTC_CELL_PCH

+RTC_CELL_PCH + RTC_CELL

RE551 0_0402_5%

@

1 2

RE565 0_0402 _5%

0.1U_0402_25V6

@

CE64

12

@

CE66

1 2

1 2

REM_DIODE1_N <32>
REM_DIODE1_P <32>
REM_DIODE2_N <32>
REM_DIODE2_P <32>

REM_DIODE4_N <32>
REM_DIODE4_P <32>

RTCRST_ON

+1.0V_VCCST

100K_0201_5%

For SB

UPD1_SMBDAT

UPD1_SMBCLK

UPD1_SMBINT#

UPD2_SMBINT#

SIO_SLP_SUS#_R

PBAT_CHARGER_SMBDAT

PBAT_CHARGER_SMBCLK

GPU_SMCLK
GPU_SMDAT

UPD2_SMBCLK
UPD2_SMBDAT

NGFF_CONFIG_0
NGFF_CONFIG_1
NGFF_CONFIG_2
NGFF_CONFIG_3

USB_POWERSHARE_VBUS_EN
USB_POWERSHARE_EN#
USB_PWR_EN1#
USB_PWR_EN2#

AC_DIS

GPS_DISABLE#

WLAN_WIGIG60GHZ_DIS#

WWAN_W AKE#

LED_MASK#

THERMTRIP1#

LOM_CABLE_DETECT#

PCIE_WAKE#_R

GPU_PWR_LEVEL

BC_DAT_ECE1117

WWAN_RADIO_DIS#

BT_RADIO_DIS#

3.3V_TS_EN

RTCRST_ON

I_BATT_R

I_SYS_R

PCH_RSMRST#

SYS_PWROK

I_SYS_R

LCD_TST

EN_INVPWR

VGA_IDENTIFY

VGA_IDENTIFY

RE93

@

VCI_IN1#

VCI_IN2#

POA_WAKE#

Discrete

UMA

2

G

12

NDS3@

13

1

1 2

RE302 2.2K_0402_5%

1 2

RE303 2.2K_0402_5%

1 2

RE91 100K_0402_5%

1 2

RE92 100K_0402_5%

1 2

RE561 100K_0402_5%

1 2

RE37 2.2K_0402_5%

1 2

RE43 2.2K_0402_5%

1
2
3
4 5

2.2K_0804_8P4R_5%

100K_0804_8P4R_5%

4 5
3
2
1

RPE11

1
2
3
4 5

100K_0804_8P4R_5%

1 2

RE83 100K_0402_5%@

1 2

RE12 100K_0402_5%

1 2

RE8 100K_0402_5%

1 2

RE38 10K_0402_5%

1 2

RE21 10K_0402_5%

1 2

RE301 10K_0402_5%

1 2

@

RE505 100K_0402_5%

1 2

RE35 10K_0402_5%

1 2

RE5 10K_0402_5%

1 2

RE365 100K_0402_5%

1 2

RE10 100K_0402_5%

1 2

RE11 100K_0402_5%

1 2

@

RE547 100K_0402_5%

1 2

CE3 2200P_0402_50V7K

1 2

CE4 2200P_0402_50V7K

1 2

RE342 10K_0402_5%

1 2

RE56 10K_0402_5%

1 2

@

RE313

1 2

RE20 100K_0402_5%

1 2

RE55 100K_0402_5%

1 2

RE507 100K_0402_5%

1 2

RE508 100K_0402_5%

1 2

RE324 100K_0402_5%

1 2

RE84 100K_0402_5%

1 2

RE85 100K_0402_5%@

RE94

@

1 2

75_0402_5%

D

QE12

@

L2N7002WT1G_SC-70-3

S

RPE12

8
7
6

6
7
8

RPE9

8
7
6

10K_0402_5%

VGA_IDENTIF Y

PCH_RTCRST# <11>

0

1

+3.3V_ALW

+3.3V_RUN

+RTC_CELL

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size

Size

Size

Date : Sheet

Date : Sheet

Date : Sheet

Compal Electronics, Inc.

EC MEC5105

EC MEC5105

Document Number Re v

Document Number Re v

Document Number Re v

EC MEC5105

LA-F312P

LA-F312P

LA-F312P

1

31 58Wednesday, December 20, 2017

31 58Wednesday, December 20, 2017

31 58Wednesday, December 20, 2017

+3.3V_ALW

of

of

of

2.0

2.0

2.0

5

+1.8V_3.3V_ALW_VTR3

+3.3V_ALW

UE6

1

5

NC

VCC

CONN@

2

A

4

Y

3

GND

74AUP1G07GW_TSS OP5

+3.3V_RUN

JESPI

1

1

2

2

3

3

4

4

5

5

6

6

7

7
8
9

10

GND1
GND2

8

9

10

11

12

1 2

RE375 0_0 402_5%

LPC@

1 2

RE560 0_0 402_5%

@

PCH_PLTRST#_EC<11>

D D

ACES_50506-01041-P01

LPC 80Port Debug L PC ESPI

1

+3.3V_RU N

2

+3.3V_RU N

3

LPC_LAD0

4

C C

B B

A A

LPC_LAD1

5

LPC_LAD2

6

LPC_LAD3

7

LPC_FRAM E#

8

PCH_PLTRS T#

9

GND

10

LPC_CLOC K

PCH_PLTRST#_EC
ESPI_RESET#

+3.3V_RU N

+3.3V_RU N

ESPI_IO0

ESPI_IO1

ESPI_IO2

ESPI_IO3

ESPI_CS#

NA

GND

ESPI_CLK

1 2

RE340
10K_0402_ 5%

PCH_PLTRST#_5105 <31>

ESPI_IO0 <8,31>
ESPI_IO1 <8,31>
ESPI_IO2 <8,31>
ESPI_IO3 <8,31>

ESPI_CS# <8,31>

ESPI_RESET# <8,31>

ESPI_CLK_5105 <8,31>

PAGE

8

18 RC212_0ohm RC211_0ohm

31

32

4

ESPI LPC

RC25_10K RC8_15ohm

RC13/RC27_8.2K

0603 0603

RE337,RE338
RE339,RE340,
RE341

0_ohm

RE2 / RE3
0_ohm

CONN@

JDEG1

1

1

2

2

3

3

4

4

5

5

6

11

6

G1

7

12

7

G2

8

8

9

9

10

10

ACES 50506-01 041-P01

+EC_DEBUG_VCC

3

2

1

For SB

+RTC_CELL

100K_0402_5%

12

RE31

POWER_SW_IN#<31>

LID_CL_SIO#

10K_8P4R_5%

678

12

RPE7

RE71

123

4 5

10_0402_1%

JTAG_TDI

JTAG_TDI <31>

JTAG_TMS

JTAG_TMS <31>

JTAG_CLK

JTAG_CLK <31>

JTAG_TDO

JTAG_TDO <31>

MSCLK
MSDATA

HOST_DEBUG_TX

DEBUG_TX

1 2

@

RE30

0_0402_5%

+1.0V_VCCST

SBIOS_TX<9>

HOST_DEBUG_TX <29,3 1>
MSDATA <31>
MSCLK <31>

+1.0VS_VCCIO

@

L2N7002WT1G_SC-70-3

@

RE90 0_0402_5%

QE11

1 3

1 2

D

CHEC K

2

G

12

+3.3V_ALW

100K_0402_5%

RE25

12

.047U_0402_16V7K

12

RF Request

+3.3V_ALW

1

2

+3.3V_ALW

10K_0402_5%

12

1 2

RE306

0_0402_5%

@

SIO_SLP_S3# <11,31,32>

1 2

RE70 2.2 K_0402_5%

S

1 2

RE33 1K_0402_5%

2.2U_0402_6.3V6M

CE12

RE26

10_0402_5%

CE8

CE61

68P_0402_50V8J

RF@

10K_0402_5%

12

RE72

RE73

+3.3V_ALW

CE10@

1 2

1U_0402_6.3 V6K

POWER_SW#_MB <11,38>

12

LID_CL# <38>LID_CL_SIO#<31>

+3.3V_ALW +3.3V_ALW

RE343

240K_0402_5%

TYPEC_ID<31>

CE62RE3 43

4700p240 K

*

4700p130 K
4700p

62K
33K

4700p
4700p

8.2K
4700p

4.3K

2K

4700p
4700p

1K

1 2

12

CE62
4700P_040 2_25V7K

REV

Single Port ACE w/o AR

Single Port ACE w/AR

Dual Port ACE w/o AR

Dual Port ACE w/AR

Dual Port ACE (w/AR +w/o AR)

PD_ACE_DET# rise t i me is measured fr o m 5 %~ 68%.

10K_0402_5%

100K_0402_5%

12

12

RE74

RE75@

RE86

10K_0402_ 5%

1 2

RE69

1 2

8.2K_0402_ 5%

H_THERMTRIP#<12,20>

0.1U_0402_25V6

THERMTRIP2# <31>

CE36

LMBT3904WT1G SC70-3

12

C

QE4

2

B

E

3 1

12

RE3040_0402_5%

@

CE53

1 2

4

RE2800_0402_5%

12

RE2920_0402_5%

@

CE52

1 2

0.1U_0402_25V6K

4

O

VSET_5105 <31>

1 2

RE79
2K_0402_5%

1 2

12

CE40
4700P_040 2_25V7K

PCIE_WAKE#_R<31>

IMVP_VR_ON_EC

IMVP_VR_ON_EC<31>

SIO_SLP_S3#<11,31,32>

RUN_ON_EC<31>

SIO_SLP_S3#

RUN_ON_EC

*

BOARD_ID rise t i me is measured fr o m 5 %~ 68%.

Rest=1.58K , Tp=96 degree
Rest=1.33K , Tp=93 degree

1 2

@

RE275 0_0 402_5%

Stuff RE275 and no stuff RE274 keep E5 design
Stuff RE274 and no stuff RE2 75 to save two GPIOs on EC(PCH_PCIE_WAKE# should be output with OD)

@

+3.3V_ALW

0.1U_0402_25V6K

5

1

P

B

O

2

A

G

UE3

TC7SH08FU_SSOP5~D

RE79

240K 4700 p
130K
62K
33K 4700p

8.2K

4.3K
2K

3

1 2

@

@

+3.3V_ALW

5

1

P

B

2

A

G

UE5

TC7SH08FU_SSOP5~D

3

BOARD_ID<31> SYSTEM_ID<31>

CE40

REV

X00
X01

4700p
4700p

X02
X03
X04

4700p

A00

4700p

A01

4700p
4700p1K

VSET_5105

0.1U_0402_25V6

1.58K_0402_1%

12

12

CE38

RE77

Link 50271-0040N-001 DONE

+3.3V_RUN

PWM_FAN1

1 2

RE48 10K _0402_5%

1 2

RE51 10K _0402_5%

Thermal diode mapping

5105 Channel

DP1/DN1

DP2/DN2

DN2a/DP2a

DP3/DN3

DP4/DN4

DP4/DN4 for Sk in on
QE6, place QE6 close to
Vcore VR choke.

100P_0402_50V8J

C

@

2

CE39

B

E

QE6

1 2

3 1

LMBT3904WT1G SC70-3

TACH_FAN1

Locat i on

CPU (QE3)

WiGig (QE5)

DDR (QE7)

NA

CPU VR (QE6 )

REM_DIODE4_P <31>

REM_DIODE4_N <31>

ACES_50271-00 40N-001

100P_0402_50V8J

CE46@

PCIE_WAKE# <29,34 >

PCH_PCIE_WAKE# <11,31>

RE2740_0402_5%

@

+3.3V_ALW

UE4

1

5

NC

2

A

3

GND

74AUP1G07GW_TSS OP5

240K 4700p
130K 4700p

*

62K

4.3K 47 00p
2K
1K

VCC

+3.3V_ALW

1 2

SYSTEM_IDBOARD_ID

12

CE47RE300

4700 p
4700 p3 3K
4700 p8 .2K

4700 p 1 5P
4700 p

4

Y

SB12@

RE300

130K_0402_5%

CE47
4700P_040 2_25V7K

VCCST_PWRGD <11,14,31>

62K_0402_5%

PANEL SIZE

11"
12"
13"
14"
15"
17"

IMVP_VR_ON

IMVP_VR_ON <46>

RUN_ON <17,31,39,44>

SYSTEM_ID rise t i me is measur ed fr o m 5 %~68 %.

JFAN1

1

PWM_FAN1

1

2

2

3

3

4

4

5

GND1

6

GND2

CONN@

Place under CPU
Place CE35 close to the QE3 as possible

100P_0402_50V8J

C

2

CE35@

B

1 2

E

QE3

3 1

LMBT3904WT1G SC70-3

DP2/DN2 for WiGig on QE5, place QE5 c lose
to WiGig and CE37 clos e to QE5

DN2a/DP2a for DDR on QE7, place QE7 close
to DDR and CE46 close to QE7

100P_0402_50V8J

31

E

12

B

2

QE7

C

LMBT3904WT1G SC70-3

12

CE37@

TACH_FAN1

10U_0603_6.3V6M

12

C

CE32

E

3 1

PWM_FAN1 <31>
TACH_FAN1 <31 >

+5V_RUN

@

DE1

BZV55-B5V6_SOD80C2

2 1

REM_DIODE1_P <31>

REM_DIODE1_N <31>

REM_DIODE2_P <31>

2

B

QE5

LMBT3904WT1G SC70-3

REM_DIODE2_N <31>

SB13@

RE300

DELL CONFIDENTIAL/PROPRIETARY

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL ") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

3

PARTY WITHOUT DELL'S EXPRESS W RITTEN CONSENT.

2

Title

MEC5105 support

MEC5105 support

MEC5105 support

Size

Document Number Rev

Size

Document Number Rev

Size

Document Number Rev

LA-F312P

LA-F312P

Date: Sheet

Date: Sheet

Date: Sheet

LA-F312P

1

2.0

2.0

2.0

32 58Friday, December 29, 2017

32 58Friday, December 29, 2017

32 58Friday, December 29, 2017

of

of

of

5

4

3

2

1

For NUVOTON TPM

@

1 2

VSB

VDD
VHIO
VHIO

GND

GND

GND

GND

PGND

Reserved

NC
NC
NC
NC
NC
NC
NC

Depop

@

1

8
14
22

2
7
10
11
25
26
31

9
16
23
32
33
12

RZ367 0_0402_5%

1 2

RZ89 0_0402_5%

+3.3V_ALW

PJP391
PAD-OPEN1x1m

1 2

+3.3V_ALW_UZ12

0.1U_0201_10V6K

1

CZ51

2

+UZ12_TPM
+UZ12_VHIO

0.1U_0201_10V6K

1

CZ54

2

CZ53,CZ55 as close as UZ12.14
CZ54 as close as UZ12.22

Comment

VDD - V_RUN Power
VHIO - V_SPI Power

Option1 (recommended)
VDD and VHIO - V_RUN power

Option2 (for Z1 sample [early sample])

VDD and VHIO - V_SPI power

+UZ12_TPM

10U_0402_6.3V6M

CZ75

1

2

10U_0603_10V6M

place CZ51,CZ52 as close as UZ12.1

1

CZ52

2

@

RZ366 0_0402_5%

@

RZ365 0_0402_5%

10U_0603_10V6M

0.1U_0201_10V6K

1

1

2

CZ55

CZ53

2

place CZ50, CZ75 as close as UZ 12.8

0.1U_0201_10V6K

1

CZ50

2

1 2

1 2

+3.3V_M_TPM

+3.3V_RUN

PCH_PLTRST#_AND< 11,28,29,34>

CONTACTLESS_DET#<12>

+PWR_SRC

POA_WAKE#<31>

D D

+3.3V_ALW

@

1 2

+3.3V_RUN

@EMI@

@EMI@

CZ56

RZ369 0_0402_5%

@

1 2

RZ368 0_0402_5%

1 2

RZ69 10K_0402_5%

12

RZ362

@

10K_0402_5%

1 2

@

RZ112 0_0402_5%

1 2

@

RZ363 0_0402_5%

1 2

RZ58
RZ59

RZ60

@

RZ61 0_0402_5%

1 2

1 2
1 2

PLTRST_TPM#<11>

T283

33_0402_5%
33_0402_5%

33_0402_5%EMI@

@

NPCT65x RZ89, RZ366, RZ62, RZ363

NPCT75x RZ89, RZ365, RZ112

NPCT75x

TPM_PIRQ#

TPM_PIRQ#<9>

PAD~D

+3.3V_M_TPM

UZ12

29

GPIO0/SDA/XOR_OUT

30

GPIO1/SCL

3

GPIO2/GPX

6

GPIO3/BADD

24

LAD0/MISO

21

LAD1/MOSI

18

LAD2/SPI_IRQ#

15

LAD3

19

LCKL/SCLK

20

LFRAME#/SCS#

17

LRESET#/SPI_RST#/SRESET#

27

SERIRQ

13

CLKRUN#/GPIO4/SINT#

28

LPCPD#

4

PP

5

TEST

NPCT750JAAYX_QFN32_5X5

PCH_SPI_D1_2_R
PCH_SPI_D0_2_R

PCH_SPI_CLK_2_R
PCH_SPI_CS#2_R

@

10K_0402_5%

12

RZ62

TPM_GPIO0

TPM_LPM#

TPM_GPIO4

Pop

RZ367, RZ366 RZ89, RZ365, RZ62

+3.3V_ALW_PCH

C C

B B

PCH_SPI_CLK_R1<8>

SIO_SLP_S0#<11,17,44>

PCH_SPI_D1_R1<8>

PCH_SPI_D0_R1<8>

PCH_SPI_CS#2<8>

PCH_SPI_CLK_2_R

33_0402_5%

1 2

12

RZ63

0.1U_0402_25V6

+3.3V_M_TPM

+3.3V_RUN

RZ365, RZ367, RZ112

RZ367, RZ366, RZ62, RZ363

RF Request RF Request

+3.3V_ALW +3.3V_M_ TPM

RF@

RF@

12P_0402_50V8J

68P_0402_50V8J

1

1

CZ57

CZ58

2

2

+3.3V_ALW

1 2

RZ8 4.7K_0402_5%

1 2

RZ9 4.7K_0402_5%

1 2

RZ10 100K_0402_5%

1 2

CZ78 100P_0402_50V8J

RF@

@

1 2

RZ85 0_0402_5%

1 2

RZ364 100_0402_5%

USH_EXPANDER_SMBC LK<31>
USH_EXPANDER_SMBD AT<31>

1 2

RZ114 0_0402_5%

@

DZ8

RB751S40T1G_SOD523-2

USH_DET#<31>

PCH_PLTRST#_AND

.047U_0402_16V7K

ESD@

12

CZ61

For E SD solution

12

@

1 2

RZ87 0_0402_5%

@

RB751S40T1G_SOD523-2

USH_EXPANDER_SMBC LK

USH_EXPANDER_SMBD AT

USH_PWR_STATE#

CV2_ON<31>

EC_FPM_EN<31>

USB20_N10<10>
USB20_P10<10>

BCM5882_ALERT#<31>

+3.3V_ALW

+5V_ALW
+3.3V_RUN

+5V_RUN

USH_PWR_STATE#<31>

DZ7

12

+5V_ALW

0.1U_0201_10V6K

1

CZ64

2

RF@

RF@

68P_0402_50V8J

12P_0402_50V8J

1

1

CZ60

CZ59

2

2

+PWR_SRC_R

POA_WAKE#_R

USH_RST#_R

CONTACTLESS_DET#_R

USH_DET#_R

Close to JUSH1

@

CVILU_CF5026FD0RK-05-NH

1

2

Close to UZ12

RF Request

+3.3V_RUN

RF@

RF@

12P_0402_50V8J

68P_0402_50V8J

1

1

CZ76

CZ77

2

2

USH CONN

JUSH1

CONN@

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25

25

26

26

27

GND1

28

GND2

Update to LTCX007Q600 (DVT1.0)

+3.3V_ALW+3.3V_RUN+5V_RU N

0.1U_0201_10V6K

1

@

CZ66

2

0.1U_0201_10V6K

0.1U_0201_10V6K

1

@

@

CZ68

CZ67

2

68P_0402_50V8J

1

2

RF Request

RF@

CZ73

RF Request

USH_EXPANDER_SMBC LK

A A

USH_EXPANDER_SMBD AT

1 2

CZ62 68P_ 0402_50V8J

@RF@

1 2

CZ63 68P_ 0402_50V8J

@RF@

RF@

68P_0402_50V8J

1

CZ69

2

RF@

68P_0402_50V8J

1

CZ71

2

+3.3V_ALW+3.3V_RUN+5V_RU N+5V_ALW

RF@

68P_0402_50V8J

1

CZ72

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.

5

4

3

2

Title

Size Document N umber Re v

Size Document N umber Re v

Size Document N umber Re v

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

Compal Electronics, Inc.

USH & TPM

USH & TPM

USH & TPM

LA-F312P

LA-F312P

LA-F312P

33 58Wednesday, December 20, 2017

33 58Wednesday, December 20, 2017

33 58Wednesday, December 20, 2017

1

2.0

2.0

2.0

5

4

3

2

1

For Brekenridge 12/14/15 UMA/Steamboat

RF Request

D D

+3.3V_HDD_M2

68P_0402_50V8J

@RF@

1

CN60

2

+3.3V_HDD_M2

0.1U_0201_10V6K

@

CN61

1

2

0.1U_0201_10V6K
22U_0603_6.3V6M

CN62

1

2

22U_0603_6.3V6M

12

12

CN63

CN64

2280 SSD

NGFF slot C Key M

Place near HDD CONN

JNGFF3

CONN@

1

GND

3

GND

5

PCIE_PRX_DTX_N9<10>
PCIE_PRX_DTX_P9<10>

PCIE_PTX_DRX_N9<10>
PCIE_PTX_DRX_P9<10>

PCIE_PRX_DTX_N10<10>

C C

+3.3V_HDD_M2

M2280_DEVSLP

1 2

RN37@ 10K_0402_5%

B B

if signal is PCIE GEN3/SATA GEN3 maybe change C value
or no need for DG0.9 SATA EXPRESS HDD

PCIE_PRX_DTX_P10<1 0>

PCIE_PTX_DRX_N10<10>
PCIE_PTX_DRX_P10<1 0>

PCIE_PRX_DTX_N11<10>
PCIE_PRX_DTX_P11<1 0>

PCIE_PTX_DRX_N11<10>
PCIE_PTX_DRX_P11<1 0>

PCIE_PRX_DTX_P12<1 0>
PCIE_PRX_DTX_N12<10>

PCIE_PTX_DRX_N12<10>
PCIE_PTX_DRX_P12<1 0>

12

CN65 0.22U_0402_10V6K

12

CN66 0.22U_0402_10V6K

12

CN67 0.22U_0402_10V6K

12

CN68 0.22U_0402_10V6K

12

CN69 0.22U_0402_10V6K

12

CN70 0.22U_0402_10V6K

12

CN71 0.22U_0402_10V6K

12

CN72 0.22U_0402_10V6K

CLK_PCIE_N3<11>
CLK_PCIE_P3<11>

M2280_PCIE_SATA#<10>

PCIE_PTX_C_DRX_N9
PCIE_PTX_C_DRX_P9

PCIE_PTX_C_DRX_N10
PCIE_PTX_C_DRX_P10

PCIE_PTX_C_DRX_N11
PCIE_PTX_C_DRX_P11

PCIE_PTX_C_DRX_N12
PCIE_PTX_C_DRX_P12

PERn3

7

PERp3

9

GND

11

PETp3

13

PETn3

15

GND

17

PERn2

19

PERp2

21

GND

23

PETp2

25

PETn2

27

GND

29

PERn1

31

PERp1

33

GND

35

PETn1

37

PETp1

39

GND

41

PERn0/SATA-B+

43

PERp0/SATA-B-

45

GND

47

PETn0/SATA-A-

49

PETp0/SATA-A+

51

GND

53

REFCLKN

55

REFCLKP

57

GND

67

N/C

69

PEDET (OC-PCIe/GND-SATA)

71

GND

73

GND

75

GND

77

GND

LOTES_APCI0170-P001A

SUSCLK(32kHz) (O)(0/3.3V)

3.3VAUX

3.3VAUX

DAS/DSS#

3.3VAUX

3.3VAUX

3.3VAUX

3.3VAUX

DEVSLP

PERST#

CLKREQ#

PEWake#

3.3VAUX

3.3VAUX

3.3VAUX

GND

2
4
6

N/C

8

N/C

10
12
14
16
18
20

N/C

22

N/C

24

N/C

26

N/C

28

N/C

30

N/C

32

N/C

34

N/C

36

N/C

38
40

N/C

42

N/C

44

N/C

46

N/C

48

N/C

50
52
54
56

N/C

58

N/C

68
70
72
74

76

+3.3V_HDD_M2

NVME_LED#

PCIE_WAKE#

SUSCLK_R

1 2

RN100 0_0402_ 5%@

@

RN99 0_0402_5%

Link DC04000LI00 DONE

2.8A

PJP31

1 2

PAD-OPEN1x3m

M2280_DEVSLP <10>

PCH_PLTRST#_AND <11,28,29,33>

CLKREQ_PCIE#3 <11>

PCIE_WAKE# <29,32>

1 2

+3.3V_RUN

SATALED# <10,29,38>

SUSCLK <11,29>

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.

5

4

3

2

Title

Size Document N umber Re v

Size Document N umber Re v

Size Document N umber Re v

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

Compal Electronics, Inc.

M2 2280 Socket

M2 2280 Socket

M2 2280 Socket

LA-F312P

LA-F312P

LA-F312P

34 58Wednesday, December 20, 2017

34 58Wednesday, December 20, 2017

34 58Wednesday, December 20, 2017

1

2.0

2.0

2.0

5

4

3

2

1

+5V_USB_CHG_PWR

DI4

D D

C C

+5V_ALW

RI13

USB3_PRX_DTX_N6<10>

USB3_PRX_DTX_P6<10>

USB3_PTX_DRX_N6<10>

USB3_PTX_DRX_P6<10>

ILIM_SEL

12

10K_0402_5%

12

CI13 0.1U_0402_25V6

12

CI16 0.1U_0402_25V6

USB20_N9<10>
USB20_P9<10>

USB_OC0#<10>

USB_POWERSHARE_V BUS_EN<31>

USB_POWERSHARE_E N#<31>

ILIM_SEL

+5V_ALW

1

2
3

13

4

5

6
7
8

SA000097E10 Link Done

USB3_PRX_DTX_N6 USB3_PRX_DTX_N6

USB3_PRX_DTX_P6

USB3_PTX_C_DRX_N6

USB3_PTX_C_DRX_P6

VOUT

DP_IN

DM_IN

ILIM_L

ILIM_HI

GND

12

10
11

15
16

9

NC

14
17

+5V_USB_CHG_PWR

UI3

VIN

DM_OUT
DP_OUT

FAULT#

ILIM_SEL

EN

CTL1
CTL2
CTL3

Thermal Pad

SLGC55544CVTR_TQFN16_3X3

ESD@

1

1

2

2

4

4

5

5

3

3

8

AZ1045-04F_DFN2510P10E-10-9

SW_USB20_P9
SW_USB20_N9

RI14

22.1K_0402_1%

9

10

USB3_PRX_DTX_P6

8

9

USB3_PTX_C_DRX_N6

7

7

USB3_PTX_C_DRX_P6

6

6

LI7

SW_USB20_N9

SW_USB20_P9

12

EMI@

1 2

EXC24CQ900U_4P

150U_B2_6.3VM_R35M

@

1

CI32

+

2

34

1

2

100U_1206_6.3V6M

CI14

USB20_N9_R

USB20_P9_R

0.1U_0201_10V6K

CI17

1

2

3

1

1

PESD5V0U2BT_SOT23-3

ESD@

223

DI5

USB20_N9_R
USB20_P9_R

USB3_PRX_DTX_N6
USB3_PRX_DTX_P6

USB3_PTX_C_DRX_N6
USB3_PTX_C_DRX_P6

JUSB1

CONN@

1

VBUS

2

D-

3

D+

4

GND

5

SSRX-

6

SSRX+

7

GND

8

SSTX-

9

SSTX+

ACON_TCRA2-9U1U93

GND
GND
GND
GND

10
11
12
13

LINK DC231604011 DONE

RF Request

+5V_USB_CHG_PWR

RF@

RF@

68P_0402_50V8J

12P_0402_50V8J

1

1

CI44

CI43

2

2

B B

A A

+5V_ALW

47U_0603_6.3V6M

47U_0603_6.3V6M

@

1

1

CI34

2

2

@

1

CI33

2

Place near UI3.1

10U_0402_6.3V6M

0.1U_0201_10V6K

@

CI19

1

CI31

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.

5

4

3

2

Title

Size Document N umber Re v

Size Document N umber Re v

Size Document N umber Re v

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

Compal Electronics, Inc.

JUSB1+PS

JUSB1+PS

JUSB1+PS

LA-F312P

LA-F312P

LA-F312P

35 58Wednesday, December 20, 2017

35 58Wednesday, December 20, 2017

35 58Wednesday, December 20, 2017

1

2.0

2.0

2.0

5

USB3_PRX_DTX_N3<10>

USB3_PRX_DTX_P3<10>

USB3_PTX_DRX_N3<10>

USB3_PTX_DRX_P3<10>

D D

C C

4

12

CI5 0.1U_0402_25V6

12

CI4 0.1U_0402_25V6

3

DI1

USB3_PRX_DTX_N3 USB3_ PRX_DTX_N3

USB3_PRX_DTX_P3 USB3_PRX_DTX_P3

USB3_PTX_C_DRX_N3 USB3_PTX_C_DRX_N3

USB3_PTX_C_DRX_P3 USB3_PTX_C_DRX_P3

USB20_P2<10>

USB20_N2<10>

USB20_P2

USB20_N2

DFB request:
main SM07000 3Z00 (INPAQ_MCM1012B900F06BP_4P)
Footprint use 2nd source SM070004400 (PANAS_EXC24CQ900U_4P)
Pitch change from 0.5mm to 0.55mm

ESD@

1

1

2

2

4

4

5

5

3

3

8

AZ1045-04F_DFN2510P10E-10-9

1 2

10

9

7

6

EXC24CQ900U_4P

LI3

EMI@

9

8

7

6

34

USB20_P2_R

USB20_N2_R

2

1

For Breckenridge/Steamboat 12&Kirkwood

RF Request

+USB_EX2_PW R

+5V_ALW

12

68P_0402_50V8J

12P_0402_50V8J

RF@

RF@

1

1

Part Reference

CI45

2

2

0.1U_0201_10V6K

10U_0603_10V6M

CI7

@

1

CI6

2

+USB_EX2_PWR

100U_1206_6.3V6M

12

CI1

USB_PWR_EN1#<31>

JUSB2

CONN@

1

USB20_N2_R

223

1

1

USB20_P2_R

USB3_PRX_DTX_N3
USB3_PRX_DTX_P3

PESD5V0U2BT_SOT23-3

USB3_PTX_C_DRX_N3

ESD@

USB3_PTX_C_DRX_P3

DI2

0.1U_0201_10V6K

CI3

1

3

2

VBUS

2

D-

3

D+

4

GND

5

SSRX-

6

SSRX+

7

GND

8

SSTX-

9

SSTX+

ACON_TCRA2-9U1U93

GND
GND
GND
GND

10
11
12
13

LINK DC231604011 DONE

+USB_EX2_PWR

UI1

1

OUT

5

IN

2

GND

4

EN

3

OCB

SY6288D20AAC_SOT23-5

USB_OC1# <10>

B B

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EX PRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY TH IRD
PARTY WITHOUT DELL'S EX PRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date : Sheet of

Date : Sheet of

Date : Sheet of

Compal Electronics, Inc.

JUSB2

JUSB2

JUSB2

LA-F312P

LA-F312P

LA-F312P

1

36 58W ednesday, December 20, 2017

36 58W ednesday, December 20, 2017

36 58W ednesday, December 20, 2017

2.0

2.0

2.0

5

4

3

2

1

RF Request

Touch Pad

+3.3V_TP

4.7K_0402_5%

4.7K_0402_5%

12

12

RZ18

D D

DAT_TP_SIO_I2C_CLK<31>

CLK_TP_SIO_I2C_DAT<31>

10P_0402_50V8J

10P_0402_50V8J

12

12

CZ80

CZ81

RZ22 0_0402_5%

@

RZ23 0_0402_5%

@

@

RZ346 0_0402_5%

@

RZ347 0_0402_5%

PS2

12

12

1 2

1 2

I2C From EC

+3.3V_TP +3.3V_TP

2.2K_0402_5%

12

C C

I2C1_SDA_TP< 9>

I2C1_SCK_TP< 9>

2.2K_0402_5%

12

RZ20

RZ21

1 2

@

RZ26 0_0402_5%

1 2

@

RZ29 0_0402_5%

RZ19

DAT_TP_SIO_R

CLK_TP_SIO_R

I2C1_SDA_TP_R

I2C1_SCK_TP_R

I2C1_SDA_TP_R

I2C1_SCK_TP_R

10K_0402_5%

12

12

@

RZ116

+3.3V_RUN +3.3V_TP

10K_0402_5%

@

RZ117

PJP35

1 2

PAD-OPEN1x1m

Keyboard

BC_INT#_ECE1117<31>

BC_DAT_ECE1117<31>

BC_CLK_ECE1117<31>

Reserve for future use

KB_DET#<12>

+5V_RUN
+3.3V_ALW

TOUCHPAD_INTR#<12,31>

+3.3V_TP

KB_DET#

BC_INT#_ECE1117
BC_DAT_ECE1117

BC_CLK_ECE1117

DAT_TP_SIO_R

CLK_TP_SIO_R

I2C1_SDA_TP_R
I2C1_SCK_TP_R

I2C From CPU

+3.3V_TP

1

CZ83

RF@

68P_0402_50V8J

2

CVILU_CF5020FD0RK-05-NH

22

GND

21

GND

20

20

19

19

18

18

17

17

16

16

15

15

14

14

13

13

12

12

11

11

10

10

9

9

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

CONN@

JKBTP1

CHECK PIN DEFINE

Update to LTCX007Q500 (DVT1.0)

+5V_RUN+3.3V_ALW+3.3V_TP

0.1U_0201_10V6K

0.1U_0201_10V6K

1

@

CZ90

2

0.1U_0201_10V6K

1

1

@

CZ91

CZ92

2

2

Place close to JKBTP1

@

P lan is f or I2C to be driven by the EC for Win7 and Pre-OS (will utilize Intel I2C drivers for Win7)
For Win8.1 and 10 the EC will control TP over I2C Pre-OS and then the PCH will drive I2C when in Windows
Route PS2 from EC to the touch pad also for contingency plan if I2C has issues

B B

RSMRST circuit

+3.3V_ALW

@

CZ82

1 2

0.1U_0201_10V6K

5

1

PCH_RSMRST#<31>

ALW_PWRGD_3V_ 5V<11,41>

A A

5

4

P

B

2

A

G

3

4

O

UZ6

TC7SH08FU_SSOP5~D

PCH_RSMRST#_AND <11,14>

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.

3

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document N umber Re v

Size Document N umber Re v

Size Document N umber Re v

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

Compal Electronics, Inc.

Keyboard

Keyboard

Keyboard

LA-F312P

LA-F312P

LA-F312P

37 58Wednesday, December 20, 2017

37 58Wednesday, December 20, 2017

37 58Wednesday, December 20, 2017

1

2.0

2.0

2.0

5

4

3

2

1

means EC c an swi tch battery whi te le d and HDD LED by hot key “ Fn+ H”

MASK_SATA_LED#<31>

D D

SATALED#< 10,29,34>

BAT2_LED#<31,38>

HDD LED MUX

5

BAT2_LED#_R

34

QZ2B

@

DMN65D8LDW-7_SOT363-6

+3.3V_ALW

2

61

QZ2A

@

DMN65D8LDW-7_SOT363-6

BAT2_LED#_R

2

R1=10K/R2= 10K
Change ba ck to SB 000002T00 4/25

DDTA144VCA-7-F_SOT23-3
QZ3

@

1 3

1 2

RZ25 150_0402_5%@

BATT_WHITE#

Bat t er y LE D

BAT2_LED#<31,38>

BAT1_LED#<31>

1 2

RZ361 100_0402_5%

1 2

RZ28 330_0402_5%

LED P/N change to SC50000FL00 from SC50000BA00

BATT_WHITE#

BATT_YELLOW#

Breath LED

QZ7B

C C

+3.3V_ALW

@

CZ93

1 2

0.1U_0201_10V6K

5

1

LED_MASK#<27,31>

LID_CL#<32,38>

B

2

A

P

MASK_BASE_LEDS#

4

O

G

UZ10

TC7SH08FU_SSOP5~D

3

BREATH_LED#<31>

DMN65D8LDW-7_SOT363-6

BREATH_LED#_Q BREATH_WHITE_LED_SNIFF#

34

5

MASK_BASE_LEDS#

1 2

RZ32 330_0402_5%

POWER & INSTANT ON SWITCH

SW3

1

POWER_SW#_M B<11,32>

B B

2

4

SKRBACE010_4P

3

LTW-C193DC-C_WHITE

Place LED3 close to SW3

LED board CONN

BATT_YELLOW#
BATT_WHITE#

LID_CL#<32,38>

+3.3V_ALW

+5V_ALW

LED3

21

+5V_ALW

JLED1

CONN@

1

1

2

2

3

3

4

4

5

5

6

6

7

GND

8

GND

ACES_50209-0060N-P01

Fiducial Mark

FD1@

1

FIDUCIAL MARK~D

FD2@

1

FIDUCIAL MARK~D

FD3@

1

FIDUCIAL MARK~D

FD4@

1

FIDUCIAL MARK~D

A A

Mask All LEDs (Unobtrusive mode )

Mask Base MB LEDs (Lid Closed)
Do not Mask LEDs (Lid Opened) 11

H_3P4

CPU

H2@

H3@

H_3P4

H_3P4

1

1

H_3P4

H1@

1

LED Circuit Control Table

H5@

H6@

H4@

H_1P0N

H_1P0N

1

1

1

LED_MASK#

0
1 0

NGFF

H8@

H7@

H_3P2

H_3P2

1

1

H_3P2

H_2P6

LID_CL#

X

FAN

H26@

H10@

H25@

H_3P2

H_2P6

1

1

H23@

H24@

H_2P6

H_2P6

1

1

H12@

H9@

1

H14@

1

H_3P8

H_2P6

H_2P6

H_3P5

1

1

H27@

H15@

H_3P5

H_3P5

1

1

H20@

H29@

H16@

H_3P1

H_3P1

H_2P6

1

1

1

H18@

H28@

H_2P6

H_2P6

1

1

H39@

H37@

H38@

H_2P6

1

1

H33@

1

H_2P3N

H21@

H22@

H_3P5

H_3P5

1

1

1

H30@

H_2P3X2P7N

1

CLIP1

1

P1

CLIP_14P0X2P6

CLIP2

1

P1

CLIP_7P7X4P2

CONN@

CONN@

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS D OCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL . IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

3

PARTY WITHOUT DE LL'S EXPRESS WRITTEN CONSENT.

2

Title

Size

Size

Size

Date : Sheet

Date : Sheet

Date : Sheet

Compal Electronics, Inc.

PAD, LED

PAD, LED

PAD, LED

Document Number Re v

Document Number Re v

Document Number Re v

LA-F312P

LA-F312P

LA-F312P

1

38 58Wednesday, December 20, 2017

38 58Wednesday, December 20, 2017

38 58Wednesday, December 20, 2017

of

of

of

2.0

2.0

2.0

5

4

3

2

1

+3.3V_WLAN/+3.3V_LAN source

+3.3V_ALW

D D

WLAN_PWR_EN

+5V_ALW

SIO_SLP_LAN#<11,31>

UZ2

1

VIN1

VOUT1

2

VIN1

VOUT1

3

ON1

4

VBIAS

5

6

EM5209VF_SON14 _2X3

GND

ON2

VIN2

VOUT2

VIN27VOUT2

GPAD

CT1

CT2

+3.3V_WLAN_UZ2

14
13

12

11

10

9
8

15

+3.3V_LAN_UZ2

1 2

PAD-OPEN1x2m

1 2

CZ122 0.1U_0201_10V6K

1 2

CZ109 470P_0402_50 V7K

1 2

CZ110 470P_0402_50 V7K

1 2

CZ111 0 .1U_0201_10V6K

1 2

PAD-OPEN1x1m

PJP36

PJP37

2A

+3.3V_WLAN

+3.3V_LAN

1A

+3.3V_ALW_PCH/+3.3V_RUN source

0.63A

PJP38

1 2

+3.3V_ALW

C C

1 2

RZ65 0_04 02_5%

PCH_ALW_ON<31>

PCH_PRIM_EN<11,17,43,44,45>

@

@

1 2

RZ64 0_04 02_5%

+5V_ALW

RUN_ON

UZ3

1

VIN1

VOUT1

2

VIN1

VOUT1

3

ON1

4

VBIAS

5

ON2

6

VIN2

VOUT2

VIN27VOUT2

EM5209VF_SON14 _2X3

CT1

GND

CT2

GPAD

+3.3V_ALW_PCH_UZ3

14
13

12

11

10

9

+3.3V_RUN_UZ3

8

15

PAD-OPEN1x1m

1 2

CZ112 0 .1U_0201_10V6K

1 2

CZ113 470P_0402_50 V7K

1 2

CZ114 1000P_0402_5 0V7K

1 2

CZ115 0 .1U_0201_10V6K

1 2

PAD-OPEN1x3m

PJP39

+3.3V_ALW_PCH

+3.3V_RUN

3.435A

+1.8V_RUN source

RUN_ON<17,31,32,39,44>

Reserve R/C for Audio power sequence, + 5V->+3.3V-> +1.8V

1 2

@

RZ345 0_0402_5%

CZ197

470P_0402_ 50V7K

SLP_WLAN#_GATE<31>

SIO_SLP_WLAN#<11,31>

S TR BSS138W 1N SOT-323-3

EC request to reserve OR g ate for WLAN power enable

+5V_ALW

12

@

+3.3V_ALW

QZ15

1 3

12

2

D

AUX_EN_WOWL<31>

+1.8V_PRIM

RZ518
10K_0402_5%

G

SLP_WLAN#_M

S

UZ8

1

VOUT

VIN

2

VOUT

VIN

3

ON

4

VBIAS

AOZ1336_DFN8_2X2

RZ71 0_ 0402_5%

@

BAT54CW_SOT323-3

RZ70 0_ 0402_5%

@

GND
GND

CT

7
8

6

5
9

1 2

DZ9

3

2

1 2

+1.8V_RUN_UZ8

1

PJP42

1 2

PAD-OPEN1x1m

1 2

CZ120 0 .1U_0201_10V6K

1 2

CZ121 470P_0402_50 V7K

WLAN_PWR_EN

12

RZ38
100K_0402_5%

0.013A

+1.8V_RUN

+5V_RUN

12

13

2

G

@

RZ370
100_0603_5%

+5V_RUN_CHG

D

@

QZ4
L2N7002WT1G_SC-70 -3

S

+5V_RUN/+3.3V_WWAN source

B B

PJP40

CZ118 470P_0402_50 V7K

1 2

+3.3V_WWAN_UZ4

1

RF@

2200P_0402_50V7K

2

1 2

PAD-OPEN1x2m

1 2

CZ116 0.1U_0201_10V6K

1 2

CZ117 470P_0402_50 V7K

1 2

1 2

CZ119 0.1U_0201_10V6K

PJP41

PAD-OPEN1x3m

CZ124

+5V_ALW

RUN_ON<17,31,32,39,44>

3.3V_WWAN_EN

3.3V_WWAN_EN

+3.3V_ALW

3.3V_WWAN_EN<31>

1 2

RZ40 100K_04 02_5%

A A

UZ4

1

VIN1

2

VIN1

3

ON1

4

VBIAS

5

ON2

6

VIN2
VIN27VOUT2

EM5209VF_SON14 _2X3

VOUT1
VOUT1

VOUT2

GPAD

CT1

GND

CT2

+5V_RUN_UZ4

14
13

12

11

10

+3.3V_WWAN_UZ4

9
8

15

2A

+5V_RUN

+3.3V_WWAN

2.5A

RUN_ON#<31>

Reserve for S3 no power issue (+5V_RUN discharge circuit)

DELL CONFIDENTIAL/PROPRIETARY

RF Request

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EX PRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY TH IRD
PARTY WITHOUT DELL'S EX PRESS WRITTEN CONSENT.

5

4

3

2

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date : Sheet of

Date : Sheet of

Date : Sheet of

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Power control

Power control

Power control

LA-F312P

LA-F312P

LA-F312P

1

39 58W ednesday, December 20, 2017

39 58W ednesday, December 20, 2017

39 58W ednesday, December 20, 2017

2.0

2.0

2.0

5

4

3

2

1

+COINCELL

COIN RTC Battery

12

PR2

PD3

PQ1B

3

PBAT_PRES# <31,49>PBAT_CHARGER_SMBCLK <31,49>

12

PR17
100K_0402_5%

34

+Z4012

2

1

PS_ID <31>

5

1K_0402_5%

1

2

+COINCELL

+RTC_CELL

PC3
1U_0603_25V6K

82P 50V +-5% NPO 0402

12

RF reserved

PR25

1 2

0_0402_5%

+3.3V_VDD_DCIN

PC12

@RF@

+3.3V_RTC_LDO

D D

1

PD1

EMC@

TVNST52302AB0_SOT523-3

2

Primary Battery Connector

PBATT1

@

1

1

2

2

3

3

4

4

5

5

12

PC1

EMC@

2200P_0402_50V7K

C C

6

6

7

7

8

8

9

9

10

10

11

GND

12

GND

DEREN_40-42251-01001RHF

PBAT_SMBCLK_C
PBAT_SMBDAT_C
PBAT_PRES#_C

GND

NB_PSID PS_ID

2

3

1

PRP1

100_0804_8P4R_5%

PL3

EMC@

BLM15AG102SN1D_2P

PD4

EMC@

PESD5V0U2BT_SOT23-3

+DC_IN

PL4

EMC@

FBMJ4516HS720NT_2P

1 2

B B

PJPDC1

@

7

GND

6

GND

-DCIN_JACK-D CIN_JACK

5

5

4

4

+DCIN_JACK

3

3

2

2

1

1

CVILU_CI0805M1HRC-NH

DCIN2_EN<31>

A A

5

PC7 can't over 1000P

12

PC5

EMC@

1000P_0603_50V7K

HW_ACAVIN_NB<31,49,50>

PQ8

12

PR28

100K_0402_5%

+3.3V_ALW

DMN65D8LW-7_SOT323-3

S

G

PR26

@

1 2

0_0402_5%

2
12

12

PC7

0.1U_0603_25V7K

@EMC@

D

13

@

PR29
0_0402_5%

12

PR13

4.7K_0805_5%

@

0.1U_0402_10V7K

PR21

1 2

1 2

12

PR27

100K_0402_5%

+3.3V_VDD_DCIN

PC9

0_0402_5%

PR22

0_0402_5%

@

12

PD6

PC6

1 2

0.022U_0603_50V7K

DFLS160-7_POWERDI123-2

+3.3V_VDD_DCIN

12

PU1

5

MC74VHC1G08DFT2G SC70 5P AND

1

P

B

4

O

2

A

G

3

PR23

1 2

0_0402_5%

4

3

18
27
36
45

12

DC_IN+ Source

S1 S2

PQ9

EMZB08P03VL 1P EDFN3X3-8

1
2
3 5

4

12

PR12

1M +-5% 0402

12

PR18

1M +-5% 0402

13

D

2

G

PQ6

S

12

DMN65D8LW-7_SOT323-3

PR30

100K_0402_1%

2

100K_0402_1%

15K_0402_1%

12

PR14

100K_0402_5%

1

PD2

EMC@

TVNST52302AB0_SOT523-3

3

PBAT_CHARGER_SMBDAT <31,49>

PR6

1 2

PR8

1 2

+DC_IN_SS

12

PC8

10U_0805_25V6K

PBATT+_C

PR3

@

1 2

0_0402_5%

1 3

D

S

PQ2
FDV301N-G_SOT23-3

G

2

C

2

PQ3

B

MMST3904-7-F_SOT323~D

E

3 1

S SCH DIO 5A 100V 15UA 0.88V TO227-3

PL1

EMC@

FBMJ4516HS720NT_2P

1 2

PL2

EMC@

FBMJ4516HS720NT_2P

1 2

+PBATT

+3.3V_ALW

12

PR1

100K_0402_5%

BAS40CW SOT-323

+3.3V_ALW

PR4

PR5

33_0402_5%

1 2

2.2K_0402_5%

1 2

+5V_ALW

12

PR7

10K_0402_1%

PD5

2

1

3

PQ4
EMZB08P03VL 1P EDFN3X3-8

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

1
2
35

4

12

PR16

49.9K +-1% 0402

13

PR20

D

2

1 2

G

PQ7

S

0_0402_5%

DMN65D8LW-7_SOT323-3

+SDC_IN

+SDC_IN

12

12

PC4

12

PR11

0.022U_0603_50V7K

499K +-1% 0402

AO3409 P-CHANNEL SOT-23

12

PR24

100K_0402_5%

S

D

1 3

DMN65D8LDW-7_SOT363-6

PQ5

G

2

12

61

PQ1A

PR10
300K +-5% 0402

PR15
100K_0402_5%

PR19

1 2

2

0_0402_5%

VBUS2_ECOK <31,50>

+3.3V_VDD_DCIN

DMN65D8LDW-7_SOT363-6

2

12

PC2

JRTC1

@

EMC@

2200P_0402_50V7K

1

3

1

G

4

22G

ACES_50271-0020N-001

+DC_IN

1

2

1000P 50V K X7R 0603

1

PC11

2

12

PC10

2.2U 10V M X5R 0402

AC_DISC# <31,50>

PU2

VCC

3

VOUT

GND

AP2204R-3.3TRG1 SOT-89 3P LDO

footprint use SA00008HO00
PN use SA0000AVC00

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size

Size

Size

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

Compal Electronics, Inc.

+DCIN

+DCIN

+DCIN

Document Number Re v

Document Number Re v

Document Number Re v

LA-F311P

LA-F311P

LA-F311P

1

40 58Wednesday, December 20, 2017

40 58Wednesday, December 20, 2017

40 58Wednesday, December 20, 2017

2.0

2.0

2.0

A

B

C

D

E

PGOOD_3V

1 1

+PWR_SRC +PWR_SRC

12

12

12

PC133

1000P_0402_50V7K

@EMC@

2 2

PC135

PC134

1U_0402_25V6K

@EMC@

@EMC@

1000P_0402_50V7K

@EMC@

+PWR_SRC

PAD-OPEN 1x2m~D

12

12

PC137

3 3

4 4

PC138

1000P_0402_50V7K

1000P_0402_50V7K

@EMC@

@EMC@

ALWON<31>

12

12

PC140

PC139

1U_0402_25V6K

1U_0402_25V6K

@EMC@

@EMC@

E9 delete PD100

1 2

12

PC136

1U_0402_25V6K

PJP101

PR114

0_0402_5%

PJP100

PAD-OPEN 1x2m~D

+3.3V_ALW

21

PC115

@EMC@

12

PR116

12

PC103

100P 50V J NPO 0402

@EMC@

PR107
100K_0402_5%

1 2

PGOOD_3V

5V_VIN

12

PC117

2200P_0402_50V7K

10U_0805_25V6K

4.7U_0603_6.3V6K

3V_VIN

12

PC105

10U_0603_25V6M

12

PC118

10U_0805_25V6K

PR113
100K_0402_5%

1 2

12

PC104

12

PGOOD_5V

21

PC100

@EMC@

12

0.1U_0402_25V6

+3.3V_ALW

3V5V_EN

12

1M_0402_1%

100P 50V J NPO 0402

PC116

@EMC@

PC128

EN1 and EN2 dont't floating

BST_3V

1

2

5

12

10U_0603_25V6M

PC143

1 2

100P_0402_50V8J

RF@

LX_3V

3V5V_EN

LX_5V

PU100

6

7

8

9

10

PU102

6

7

8

9

10

IN

LX

GND

GND

SY8288BRAC_QFN20_3X3

PG

NC

LX

GND

GND

SYV828CRAC QFN 20P PWM

PG

NC

IN3IN4IN

EN112EN2

FF13OUT14NC

11

ENLDO_3V5V

PC113
1000P_0402_50V7K

3V_FB

2

5

11

ENLDO_3V5V

3V5V_EN

EN112EN2

IN

IN3IN4IN

FF13OUT14LDO

BS

20

LX

19

LX

18

GND

17

LDO

16

NC

21

GND

15

1 2

BST_5V

1

BS

20

LX

19

LX

18

GND

17

VCC

16

NC

21

GND

15

+5V_ALW2

5V LDO 150mA~300mA

12

PC126

4.7U_0603_6.3V6K

PC127
1000P_0402_50V7K

5V_FB

1 2

PR100

1 2

0_0603_5%

PR104

1 2

PR105

0_0402_5%

1 2

0_0402_5%

3.3V LDO 150mA~300mA

12

PC111

4.7U_0603_6.3V6K

PR108

1K_0402_5%

1 2

PR111

1 2

0_0603_5%

LX_5V

PC119

1 2

4.7U_0603_6.3V6K

PR117

1K_0402_5%

1 2

LX_3V

+3.3V_RTC_LDO

PC114

1 2

0.1U_0603_25V7K

PC102

1 2

0.1U_0603_25V7K

+3.3V_ALW2

@EMC@

@EMC@

PR106

12

@EMC@

4.7 +-5% 1206

3V_SN

12

PC112

680P_0603_50V7K

@EMC@

12

PR112

4.7_1206_5%

5V_SN

12

PC125

680P_0603_50V7K

PGOOD_5V

PL100

1.5UH +-20% 9A 7X7X3 MOLDING

1 2

PL101

1.5UH +-20% 9A 7X7X3 MOLDING

1 2

PR119

1 2

0_0402_5%
PR120

1 2

0_0402_5%

PR102

ENLDO_3V5V

PR103

499K_0402_1%

1 2

12

499K_0402_1%

12

12

PC106

PC107

22UF_0805_6.3V6M

Vout is 3.234V~3.366V

12

ALW_PWRGD_3V_ 5V <11,37>

12

12

PC108

PC109

22UF_0805_6.3V6M

22UF_0805_6.3V6M

+3.3V_ALWP +3.3V_ALW

12

12

PC121

PC120

22UF_0805_6.3V6M

22UF_0805_6.3V6M

5VALWP
TDC 7.6 A
Peak Current 8.06A
OCP Current 9.67 A

12

12

PC141

1 2

PC110

PC129

22UF_0805_6.3V6M

22UF_0805_6.3V6M

22UF_0805_6.3V6M

RF reserved

12

PC122

22UF_0805_6.3V6M

12

12

PC123

PC130

22UF_0805_6.3V6M

22UF_0805_6.3V6M

100P_0402_50V8J

RF@

PJP102

112

JUMP_43X118

PJP103

112

JUMP_43X118

PC124

22UF_0805_6.3V6M

RF reserved

2

2

1 2

3VALWP
TDC 6.5 A
Peak Current 9.29 A
OCP Current 11.04A

PC142

100P_0402_50V8J

RF@

+3.3V_ALWP

+5V_ALW+5V_ALWP

+5V_ALWP

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

D

Title

Size Document Nu mber Re v

Size Document Nu mber Re v

Size Document Nu mber Re v

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

Compal Electronics, Inc.

+5V_ALW/3.3V_ALW

+5V_ALW/3.3V_ALW

+5V_ALW/3.3V_ALW

LA-F311P

LA-F311P

LA-F311P

41 58Wednesday, December 20, 2017

41 58Wednesday, December 20, 2017

41 58Wednesday, December 20, 2017

E

2.0

2.0

2.0

5

D D

4

3

2

1

+PWR_SRC

C C

The current limit is
set to 8A, 12A or 16A
when this pin is pull
low, floating or pull
high
+1.2V_DDR OCP set 8A

B B

PJP202

PAD-OPEN 1x2m~D

21

12

PC200

10U_0805_25V6K

+3.3V_ALW

1 2

1 2

0.6V_DDR_VTT_ON<20>

12

PC201

@

PR205
0_0402_5%

ILMT_DDR

PR207

@

0_0402_5%

PC224

100P_0402_50V8J

RF@

+3.3V_ALW

1U_0402_6.3V6K

12

+1.2V_DD R_B+

PC206

2.2U_0402_6.3V6M

12

PC207

100P 50V J NPO 0402

100P 50V J NPO 0402

12

12

10U_0805_25V6K

@EMC@

@EMC@

PC203

PC202

1 2

RF reserved

ILMT_DDR

EN_1.2V

EN_0.6V

PR208

SIO_SLP_S4#<11,17,31,45>

1 2

0_0402_5%

PR210

1 2

0_0402_5%

12

PR209

1M_0402_5%

12

PC221

@

0.1U_0402_10V7K

1M_0402_5%

12

12

PR212

PU200

10

IN

13

BYP

14

VCC

4

VTTGND

9

PGND

15

SGND

17

ILMT

1

S5

2

S3

SY8210AQVC_QFN19_4X3

0.1U_0402_10V7K

@

PC222

19

OT

PG

BS

LX

FB

VDDQSNS

VLDOIN

VTT

VTTSNS

VTTREF

Mode S3 S5 VOUT VTT
Normal H H on on
Stadby L H on off
Shutdown L L off off

@

18

PR203

12

1 2

11

16

8

7

6

5

3

LX_DDR

0_0603_5%

+1.2V_DD RP

PC205

BST_DDR

1 2

0.1U_0603_16V7K

1U_0402_10V6K

12

PC218

Note: S3 - sleep ; S5 - power off

@EMC@

PR202

4.7_1206_5%

1 2

1 2

1UH +-20% 11A 7X7X3 MOLDING, A.2

PC209

22U_0603_6.3V6M

1 2

+0.6VSP

22U_0603_6.3V6M

12

PC219

@EMC@

PC204

680P_0603_50V7 K

SNU_DDR

1 2

PL201

330P_0402_50V7 K

12

PC208

12

R1

12

R2

PJP200

JUMP_43X118

112

+1.2V_DDR
TDC 6.5A
Peak Current 9.4A
OCP Current 11.2A

+1.2V_DDRP

102K_0402_1%

PR204

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

PC210

PC211

12

12

100K_0402_1%

PR206

2

PC212

12

10U_0603_6.3V6M

10U_0603_6.3V6M

12

PJP201

100P 50V J NPO 0402

PC214

100P_0402_50V8J

@EMC@

@EMC@

PC217

PC216

12

12

+0.6V_DDR_VTT+0.6VSP+1.2V_MEM+1.2V_DDRP

2

22U_0603_6.3V6M

PC223

PC213

12

12

JUMP_43 X39

112

0.6Volt +/- 5%
TDC 1.05 A
Peak Current 1.5 A
OCP Current 2A (fix)

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date : Sheet o f

Date : Sheet o f

Date : Sheet o f

Compal Electronics, Inc.

+1.2V_MEN/+0.6V_DDR_VTT

+1.2V_MEN/+0.6V_DDR_VTT

+1.2V_MEN/+0.6V_DDR_VTT

LA-F311P

LA-F311P

LA-F311P

42 58Wednesday, December 20, 2017

42 58Wednesday, December 20, 2017

42 58Wednesday, December 20, 2017

1

2.0

2.0

2.0

5

D D

+PWR_SRC

C C

PJP301

PAD-OPEN 1x2m~D

PCH_PRIM_EN< 11,17,39,44,45>

21

12

@

PR312

1 2

0_0402_5%

1M_0402_1%

PR302

12

PC303

PC301

0.1U_0402_25V6

10U_0603_25V6M

RF@

RF@

100P 50V J NPO 0402

EN_+1VALW P

12

+3.3V_ALW

12

PR307

@

0_0402_5%

ILMT_+1VALWP

12

PR310

@

B B

0_0402_5%

The current limit is set to 6A, 9A or 12A
when this pin is pull low, floating or pull high

+1VALW P_B+

12

PC306

PC305

10U_0603_25V6M

+3.3V_ALW

4

PU301

2

IN

12

4.7U_0603_6.3V6K

3

IN

4

IN

5

IN

7

GND

8

GND

18

GND

11

EN

13

ILMT

15

BYP

12

12

100P_0402_50V8J

SY8286RAC_QFN20_3X3

PC312

PC316

@RF@

VCC

PAD

9

PG

1

BS

6

LX

19

LX

20

LX

14

FB

17

10

NC

12

NC

16

NC

21

3

BST_+1VALW P

SW_ +1VALWP

12

PC304

0.1U_0603_25V7K

BST_+1VALW P_C

1 2

PC313

4.7U_0603_6.3V6K

@

PR304

1 2

0_0603_5%

RF@

FB_+1VALW P

2

PR303

4.7_1206_5%

1 2

0.68UH_7.9A_20%_5X5 X3_M

PL301

1 2

SNB_+1VALW P

12

PR306

21.5K_0402_1%

12

PR311

31.6K_0402_1%

RF@

PC302

680P_0603_50V7 K

1 2

12

PC307

12

330P_0402_50V7 K

PR308

1K_0402_5%

+1VALWP

12

12

PC308

22U_0603_6.3V6M

1

PJP302

2

112

JUMP_43X118

+1.0V_PRIM

+1VALWP

100P_0402_50V8J

100P_0402_50V8J

PC315

12

12

PC311

PC310

PC309

22U_0603_6.3V6M

22U_0603_6.3V6M

PC314

12

12

22U_0603_6.3V6M

RF@

RF@

RF reserved

+1.0V_PRIM
TDC 4.9A
Peak Current 7.1 A
OCP Current 8.6A
TYP MAX
Choke DCR 11.0mohm , 12.0mohm

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

3

2

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date : Sheet o f

Date : Sheet o f

Date : Sheet o f

Compal Electronics, Inc.

+1VALWP

+1VALWP

+1VALWP

LA-F311P

LA-F311P

LA-F311P

43 58Wednesday, December 20, 2017

43 58Wednesday, December 20, 2017

43 58Wednesday, December 20, 2017

1

2.0

2.0

2.0

5

4

3

2

1

+3.3V_ALW

LPM LOGIC

EN_1VS_VCCIO

13

PU401

EN

PVIN

PVIN

TPS62134CRGT_QFN16_3X3

AVIN

VID0

VID1

8

12

PR427

0_0402_5%

@

12

14

LPM

SS_1VS_VCCIO

PR404
0_0402_5%

7

12

@

PJP401

JUMP_43X79

2

+1VS_VCCIOP

12

PR421

0 +-5% 0402

112

PR422

@

0_0402_5%

1 2

12

12

PC406

22U_0603_6.3V6M

VCCIO_SENSE <17>

VSSIO_SENSE <17>

10U_0603_6.3V6M

PC425

12

12

PC407

22U_0603_6.3V6M

+1VS_VCCIOP +1.0VS_VCCIO

17

15

TP

PGND16PGND

1

VOS

LX_1VS_VCCIO

2

SW

3

SW

4

PG

FBS5AGND6SS

PC410

470P_0402_50V7K

+1VS_VCCIOP

PL402

1UH_1277AS-H-1R0N-P2_3.3A_30%

1 2

12

PR405

@EMC@

4.7_0603_5%

SNUB_1VS_VCCIO

12

PC401

@EMC@

470P_0402_50V7K

@

PR412

1 2

0_0402_5%

TPS62134 C 1 0

+1VS_VCCIOP

10U_0603_6.3V6M

PC426

PR425

@

PR403

1M_0402_1%

VIN_1VS_VCCIO

VID0_VCCIO

VID1_VCCIO

1 2

12

0_0402_5%

PC402

@

12

0.1U_0402_25V6

12

11

10

9

SIO_SLP_S0#<11,17,33,44>

PR402

RUN_ON<17,31,32,39>

D D

Vin=3 ~17V

+5V_ALW

+3.3V_ALW

PR413

PR415

12

PR414

10K_0402_1%

12

PR416

@

10K_0402_1%

VID0_VCCIO

VID1_VCCIO

12

@

10K_0402_1%

12

C C

10K_0402_1%

PL405

@

3A_Z120_40M_0603_2P

1 2

PJP403

1 2

PAD-OPEN1x1m

12

PC408

PC409

0.1U_0402_25V6

@EMC@

@EMC@

12

2200P_0402_50V7K

1 2

0_0402_5%

@

12

12

PC404

PC403

10U_0603_10V6M

10U_0603_10V6M

"R" for SILERGY

VID1 LOGIC

0

1

1

1

+1.0VS_VCCIO
TDC 1.9 A
Peak Current 2.7 A
OCP Current 3.3 A
TYP M AX
Choke DCR 48.0mohm

VID0 LOGIC

X

0

1

1

OUTPUT VOLTAGE

X

0

1

0

1 1.05

0(LPM)

0.80

0.95

1.00

+3.3V_ALW

12

PR410

EN_1.0V_PRIM_COREP

14

13

EN

PVIN

PVIN

TPS62134DRGT_QFN16_3X3

AVIN

VID0

VID1

8

VID1_PRIM_CORE

@

0_0402_5%

LPM

7

SS_1V_PRIM

12

PJP402

JUMP_43X79

2

Rup

112

+1.0V_PRIM_COREP

10U_0603_6.3V6M

10U_0603_6.3V6M

PC427

12

12

PC415

PC424

22U_0603_6.3V6M

PC428

12

12

22U_0603_6.3V6M

+1.0V_PRIM_CORE
TDC 1.8 A
Peak Current 2.6 A
OCP Current 3.1 A

TYP MAX
Choke DCR 48.0mohm

TPS62134 D 1 0

LPM LOGIC

VID1 LOGIC

0

1

1

1

X

0

1

1

VID0 LOGIC

X

0

1

0

1 1.00

OUTPUT VOLTAGE

0.7(LPM)

0.85

0.90

0.95

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size

Size

Size

Date: Sheet o f

Date: Sheet o f

2

Date: Sheet o f

Compal Electronics, Inc.

+1VS_VCCIOP/+1.0V_PRIM_COREP

+1VS_VCCIOP/+1.0V_PRIM_COREP

+1VS_VCCIOP/+1.0V_PRIM_COREP

Document Number Re v

Document Number Re v

Document Number Re v

LA-F311P

LA-F311P

LA-F311P

1

44 58Wednesday, December 20, 2017

44 58Wednesday, December 20, 2017

44 58Wednesday, December 20, 2017

2.0

2.0

2.0

+1.0V_PRIM_COREP +1.0V_PRIM_CORE

17

15

TP

PGND16PGND

1

VOS

SW

SW

PG

FBS5AGND6SS

12

PR428

PC420

@

1M_0402_1%

470P_0402_50V7K

+1.0V_PRIM_COREP

PL404

1UH_1277AS-H-1R0N-P2_3.3A_30%

2

3

4

LX_1V_PRIM

3

1 2

12

PR409

@EMC@

4.7_0603_5%

SNUB_1V_PRIM

@EMC@

12

PC419

470P_0402_50V7K

@

PR423

1 2

12

0_0402_5%

PR424

@

100K_0402_1%

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

PR426

@

PR407

1M_0402_1%

VIN_1V_PRIM

PR408

@

0_0402_5%

1 2

@

PR411
0_0402_5%

1 2

1 2

0_0402_5%

12

VID0_PRIM_CORE

12

PC411

@

0.1U_0402_25V6

PU402

12

11

10

9

SIO_SLP_S0#<11,17,33,44>

@

PR406

PCH_PRIM_EN<11,17,39,43,45>

PL406

@

3A_Z120_40M_0603_2P

1 2

VID0_PRIM_CORE

VID1_PRIM_CORE

Vin=3 ~17V

+5V_ALW

PJP404

1 2

PAD-OPEN1x1m

12

PC417

0.1U_0402_25V6

@EMC@

CORE_VID0<18>

CORE_VID1<18>

PC418

@EMC@

B B

+3.3V_ALW

PR417

PR419

12

PR418

10K_0402_1%

12

PR420

@

10K_0402_1%

12

10K_0402_1%

12

@

10K_0402_1%

A A

1 2

0_0402_5%

12

12

PC413

PC412

10U_0603_10V6M

10U_0603_10V6M

12

2200P_0402_50V7K

"R" for SILERGY

5

4

5

+3.3V_ALW

D D

PCH_PRIM_EN<11,17,39,43,44>

C C

4

PC531

PR517

100K_0402_5%

12

12

10U_0603_6.3V6M

PC530

12

10U_0603_6.3V6M

VIN_1.8VALW

12

EN_1.8VALW

12

PC505

@

0.1U_0402_16V7K

PL502

@

3A_Z120_40M_0603_2P

1 2

PJP501

1 2

PAD-OPEN1x1m

+3.3V_ALW

1.8V_PRIM_PWRGD<31>

@

PR504

1 2

0_0402_5%

PR505

1M_0402_1%

Not e:
When design Vin=5V, please stuff snubber
to prevent Vin dama ge

PU501

4

IN

LX

5

PG

GND

FB6EN

RT8097ALGE_SOT23-6

3

2

1

3

LX_1.8VALW

PJP502

PL501

1 2

20K_0402_1%

FB_1.8VALW

10K_0402_1%

1 2

PAD-OPEN1x1m

PR501

PR506

+1.8VALWP

Imax= 2A, Ipeak= 3A
FB=0 .6V

1UH_1277AS-H-1R0N-P2_3.3A_30%

12

PR502

@EMC@

4.7_0603_5%

SNUB_1.8VALW

12

PC506

@EMC@

680P_0402_50V7K

Vout=0.6V* (1+Rup/Rdown)

12

Rup

12

Rdo wn

PC503

12

68P_0402_50V8J

+1.8V_PRIM

12

12

PC501

22U_0603_6.3V6M

+1.8V_PRIM
TDC 0.7 A
Peak Current 1.0 A
OCP Current 1.2 A

2

PC504

22U_0603_6.3V6M

1

+1.8VALWP

B B

+2.5V_MEN
TDC 0.3A by power budget
AP7361 U-DFN3030-8 Pd limit=1.7W
Peak loading=1.1A.
Pd=(3.3-2.5)*1.1=0.88W < 1.7W

12

12

PR516

10.2K_0402_1%

OCP is 1.1~1.5A

2.5VSP

12

PC515

0.01UF_0402_25V7K

PAD-OPEN1x1m

12

PC516

22U_0603_6.3V6M

PJP506

1 2

+2.5V_MEM

PJP505

+3.3V_ALW

SIO_SLP_S4#<11,17,31,42>

A A

1 2

PAD-OPEN1x1m

@

1 2

PR513

0_0402_5%

1M_0402_1%

PR514

+2.5V_VIN

12

PC514

4.7U_0603_6.3V6K

12

EN_2.5V

12

@

.1U_0402_16V7K

PU503

AP7361C-FGE-7-01 U-DFN3030 8P LDO

9

GND

8

IN

7

NC

6

NC

5

EN

PC513

ADJ/NC

1

OUT

2

NC

3

4

GND

PR515

21.5K_0402_1%

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

3

2

Title

Size

Size

Size

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

Compal Electronics, Inc.

+1.8VALWP/+1.5VSP

+1.8VALWP/+1.5VSP

+1.8VALWP/+1.5VSP

Document Number Re v

Document Number Re v

Document Number Re v

LA-F311P

LA-F311P

LA-F311P

1

45 58Wednesday, December 20, 2017

45 58Wednesday, December 20, 2017

45 58Wednesday, December 20, 2017

2.0

2.0

2.0

5

4

3

2

1

+1.0V_VCCST

@

12

12

Local sense put on HW site

D D

PROCHOT#<12,31,49>

470K_0402_5%_B25/50 4700K

PH601

1 2

1 2

PR631

27.4K_0402_1%

2200P_0402_50V7K

VCCSENSE<15>

C C

VSSSENSE<15>

ISUMP_IA<47>

PR658

@

20M_0402_5%

ISUMN_IA<47>

B B

A A

@

1 2

330P_0402_50V7K

PC619

1 2

0.01UF_0402_25V7K

12

1 2

12

PH602

10K_0402_5%_B25/50 4250K

PC614

1 2

PC618

PR628

4.99K_0402_1%

PC641

.1U_0402_16V7K

@

33P_0402_50V8J

12

PR633

@U42

0.022U_0402_16V7K

@U42

0.022U_0402_16V7K

1 2

12

1 2

PC605 47P_0402_50V8J~D

PR610
10K_0402_1%

1 2

PR617

4.3K_0402_1%

1 2

PC616

1 2

12

@

11K_0402_1%

PC635

1 2

PC638

ISEN2_IA

12

PC620

@

PC624

.022U 16V K X7R 0402

ISEN1_IA<47>

ISEN2_IA<47>

VIDSCLK<15>

VIDALERT_N<15>

VIDSOUT<15>

PR678

100_0402_1%

1 2

PC617

@

1200P_0402_50V7K

1 2

1.91K_0402_1%

PC621
680P_0402_50V7K

1 2

0.082U_0402_16V7K

12

PC626

@

1K_0402_1%

0.047U_0402_25V7K

@

PR613

90.9K +-1% 0402

1 2

PC613
330P_0402_50V7K

@

1 2

PR622

@

1 2

1 2

PR632

1 2

@

374_0402_1%

1 2

ISEN1_IA

1 2

PR621

316_0402_1%

PR623
2K_0402_1%

PC627

2200P_0402_50V7K

PR638

@U22

PR634

0_0402_5%

1 2

1 2

@U22

PR615

0_0402_5%

1 2

PR601

@

45.3_0402_1%

+3.3V_RUN

I_SYS<31,49>

+5V_ALW

VCC_GT_SENSE<16>

VSS_GT_SENSE<16>

PCH_PWROK<11>

12

12

PC602

PR605

PR604

75_0402_1%

100_0402_1%

@

PR625 0_0402_5%

@

PR614

IMVP_VR_ON<32>

@

PR616

PR620

@

1 2

0_0402_5%

FCCM_IA<47>
PWM1_IA<47>
PWM2_IA<47>

PH603
470K_0402_5%_B25/50 4700K

1 2

PR647

27.4K_0402_1%

1 2

PC629

2200P_0402_50V7K

1 2

PC636

33P_0402_50V8J

PC639

1500P_0402_50V7K

1 2

1 2

PR648

1.91K_0402_1%

PC651

@

1 2

330P_0402_50V7K

PC654

1 2

0.01UF_0402_25V7K

0.1U_0402_25V6

1 2

1 2

1 2

1 2

1 2

0_0402_5%

1 2

0_0402_5%

PU602

1
2
3
4
5
6
7
8
9

10

41

PC625

330P_0402_50V7K

1 2

PR629

86.6K +-1% 0402

1 2

1 2

10K_0402_1%

PR639

3.09K_0402_1%

1 2

1 2

PR645

1 2

PR62610_0402_1%

PR6121.91K_0402_1%

PSYS
IMON_B
NTC_B
COMP_B
FB_B
RTN_B
ISUMP_B
ISUMN_B
ISEN1_B
ISEN2_B

AGND

PR635

316_0402_1%

PR61849.9_0402_1%

39

40

VR_ENABLE

FCCM_B11PWM1_B12PWM2_B13IMON_A14NTC_A15COMP_A

12

1 2

12

PC653

@

12

1 2

VIDSOUT_B

VIDSCLK_B

VIDALERT_N_B

36

37

38

35

SCLK

ALERT#

VR_HOT#

VR_READY

16

IMON_GT

NTC_GT

COMP_GT

2K_0402_1%

PR650

PC647

680P_0402_50V7K

0.082U_0402_16V7K

PR608

88.7K_0402_1%

1 2

PR611

1.87K +-1% 0402

32

33

34

VIN

SDA

VCC

PROG231PROG1

PWM_C

FCCM_C

ISUMN_C

ISUMP_C

RTN_C

FB_C

COMP_C

IMON_C
PWM_A

FCCM_A

FB_A

RTN_A18ISUMP_A19ISUMN_A

17

20

ISL95857AHRTZ-T TQFN 40P PWM

FB_GT

PR657

4.42K_0402_1%

1 2

PR653

@

20M_0402_5%

ISUMP_GT <47>

PR602

1 2

1 2

12

PC604

PC603

0.22U_0603_25V7K

1U_0603_10V6K

PWM_VSA

30

FCCM_VSA

29
28
27
26

FB_VSA

25

COMP_VSA

24

IMON_VSA

23
22

PWM_GT <47>

21

FCCM_GT <47>

12

PC630

2200P_0402_50V7K

12

PR644

1K_0402_1%

PC642

.022U 16V K X7R 0402

1 2

PC646

0.047U_0402_25V7K

1 2

PR656

11K_0402_1%

1 2

PH605

1 2

10K_0402_5%_B25/50 4250K

12

0_0402_5%

0_0402_5%

12

CPU_B+

@

PR603

PR640

PC645

+5V_ALW

374_0402_1%

12

.1U_0402_16V7K

ISUMN_GT <47>

PR619 2.2_0603_5%

1 2

BST_SA

PC611

0.22U_0603_16V7K

1 2

PWM_SA

@

PR606
0_0402_5%

1 2

PWM_VSA

12

PC628

33P 50V J NPO 0402

PC631

12

330P_0402_50V7K

PR651

PC643

Local sense put on HW site

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

VCC_SA U22
TDC 4.0A
Peak Current 4.5A
OCP current 10A
Choke DCR 6.2 m ohm

SA_UGATE

PU614

S IC ISL95808HRZ-TS2778 DFN MOSFET DRIVE

1

2

3

+5V_ALW

12

PR630

12

4700P 25V 0402

12

113K_0402_1%

2.49K_0402_1%

UGATE

BOOT

PWM

GND4LGATE

12

@

12

PHASE

FCCM

VCC

TP

9

12P 50V J N PO 0402

12

RF reserved

1 2

PC632
1000P_0402_50V7K

PR646

1 2

316_0402_1%

1.62K_0402_1%

PR652

2K_0402_1%

PC601

@

680P_0402_50V7K

2

8

7

6

5

68P 50V J N PO 0402

PC701

PC700

12

RF@

1 2

PR636 665 +-1% 0402

2200P_0402_50V7K

PR649

1 2

RF@

12

PC685

PC640

1 2

VCC_SA U42
TDC 4.0A
Peak Current 5A
OCP current 10A
Choke DCR 6.2 m ohm

VCCSA_B+ CPU_B+

1 2

PAD-OPEN1x1m

VCCSA_B+

12

12

PC612

PC608

10U 25V 0603 ZRB

10U 25V 0603 ZRB

4

1

3

2

PQ614
PE642DT 2N PDFN3X3S

D1

D1

D1

G1

SA_SW

9

RF@

PR627

4.7_1206_5%

PC622

RF@

680P_0603_50V7K

12

PC637

0.033U 25V K X7R 0402

PC644

.1U_0402_16V7K

1 2

PC650

@

12

SA_SNUBSA_SNUB

12

12

1 2

0.082U_0402_16V7K

S2

S2

G2

6

7

8

SA_LGATE

12

@

PR679
0_0402_5%

FCCM_VSA

1U_0402_10V6K

1 2

PR641

1K_0402_1%

D110D2/S1

S2

5

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

Compal Electronics, Inc.

PWR_VCORE_ISL95857

PWR_VCORE_ISL95857

PWR_VCORE_ISL95857

LA-F311P

LA-F311P

LA-F311P

PJP603

PL614

0.47UH_MMD05CZR47M_12A_20%

4

3

12

PR624

3.65K_0603_1%

ISUMP_VSA

PC633

1 2

4700P 50V K X7R 0402

PC649

0.01UF_0402_25V7K

1 2

@

PC652

330P_0402_50V7K

1 2

1

1

2

PR643

11K_0402_1%

1 2

ISUMN_VSA

RF reserved

ISUMP_VSA

12

PR642

2.61K_0402_1%

12

10KB_0402_5%

VSA_SEN- <17>

VSA_SEN+ <17>

46 58W ednesday, Dec ember 20, 2017

46 58W ednesday, Dec ember 20, 2017

46 58W ednesday, Dec ember 20, 2017

+VCC_SA

PC695

100P_0402_50V8J

RF@

PH604

ISUMN_VSA

2.0

2.0

2.0

5

4

3

2

1

VCC_core (U22)
TDC 21A
Peak Current 32A
OCP current 38.4A
Choke DCR 0.9 +-5%m ohm

D D

CPU_B+

RF@

12

12

12

12

PC656

PC682

10U 25V 0603 ZRB

10U 25V 0603 ZRB

12

C C

+5V_ALW

B B

+5V_ALW

A A

PC680

FCCM_IA<46,47>

PWM1_IA<46>

PC657

0.1U 25V K X5R 0402

PC683

@U42

1_0603_5%

1 2

FCCM_IA<46,47>

PWM2_IA<46>

PC658

10U 25V 0603 ZRB

PR688

1_0603_5%

1 2

@

PR687

12

PC684

10U 25V 0603 ZRB

@U42

PR691

10U 25V 0603 ZRB

@

1 2

PR659

0_0402_5%

1 2

0_0402_5%

12

10U 25V 0603 ZRB

@U42

12

VCC_IA1

12

PC672

PC679

@U42

VCC_IA2

12

@U42

0_0402_5%

1 2

@U42

0_0402_5%

1 2

5

0.22U_0603_16V7K

1 2

3.9 +-1% 0603

PC676

1U_0402_10V6K

12

PC673

10U 25V 0603 ZRB

@U42

@U42

0.22U_0603_16V7K

@U42

3.9 +-1% 0603

0.1U 25V K X5R 0402

PC677

@U42

1U_0402_10V6K

PR671

PR692

PC659

RF demand

PC655

1 2

PR660

12

10U 25V 0603 ZRB

@U42

PC671

1 2

1 2

PR672

VCC_core (U42)
TDC 42A
Peak Current 64A
OCP current 76.8A
Choke DCR 0.9 +-5%m ohm

+PWR_SRC

PJP601

1 2

PAD-OPEN 4x4m

PL602

@EMC@

1 2

9A Z80 10M 1812_2P

1

+

12

PC606

2

100U_D_20VM_R55M

PU610

PGND10SW

9

VIN

8

VIN

7

PHASE

6

N/C

5

BOOT

4

AGND

3

VCC

2

FCCM

1

PWM

FDMF3035_PQFN31_5X5

@U42

PGND10SW

9

VIN

8

VIN

7

PHASE

6

N/C

5

BOOT

4

AGND

3

VCC

2

FCCM

1

PWM

FDMF3035_PQFN31_5X5

1

+

PC607

2

100U_D_20VM_R55M

PGND
PVCC

AGND

PU613

SW

GL

PGND
PVCC

N/C
N/C

GL

AGND

RF@

12

PC660

0.1U_0402_25V6K~D

2200P_0402_50V7K

PR682

@U42

112

SOLDER_PREFORMS_0603

+VCC_GT

12

12

PC690

PC689

1000P_0402_50V7K

1000P_0402_50V7K

@EMC@

@EMC@

11
12

SW

13

GL

N/C
N/C

GL

+5V_ALW

14
15

16

12

17

19
18

PR686

@

10K_0402_1%

12

12

PC692

PC691

1U_0402_25V6K

1U_0402_25V6K

@EMC@

@EMC@

For KBL U42 : Pop PR682 and PR684
For KBL U22 : Pop PR683 and PR685

RF@

12

PR667

4.7_1206_5%

3.65K_0603_1%

PR663

12

PC661

1U_0402_10V6K

1 2

ISEN1_IA<46>

IA_SNUB1

12

PC662

ISUMP_IA

RF@

680P_0603_50V7K

PR683

@U22

112

SOLDER_PREFORMS_0603

PR684

@U42

112

SOLDER_PREFORMS_0603

PL610

0.15UH 20% MMD-06CZER15MEX5L 35A

4

3

IA1P

@U42

PR668

100K_0402_1%

1 2

PR670

@

IA2N

100K_0402_1%

<46,47>

+VCC_GT_+VCC_CORE+VCC_CORE

2

2

+VCC_GT_+VCC_CORE+VCC_CORE

2

IA1N

PR666
10_0402_1%

+VCC_CORE

PC696

1 2

RF@

RF reserved

<46,47>

1

2

12

12

ISUMN_IA

RF reserved

100P_040 2_50V8J

PC702

12

11
12

13

14
15

16
17

19
18

+5V_ALW

12

PR689

@

4

RF@

PR676

12

PC697

10K_0402_1%

1U_0402_10V6K

@U42

PC678

RF@

@RF@

12

@U42

3.65K_0603_1%

4.7_1206_5%

1 2

ISEN2_IA<46>

IA_SNUB2

12

ISUMP_IA

680P_0603_50V7K

@U42

PL613

0.15UH 20% MMD-06CZER15MEX5L 35A

IA_SW2

PR674

IA1N

<46,47>

IA2P

@U42

@

100K_0402_1%

1

4

3

2

PR675

100K_0402_1%

1 2

PR677

1 2

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+VCC_CORE

IA2N

12

@U42

PR673

10_0402_1%

<46,47>

ISUMN_IA

3

U42

PC626 @U42

0.1U 25V 0402

PR638 @U42

475 +-1% 0402

PR613 @U42

93.1K +-1% 0402

PR622 @U42

3.09K_0402_1%

PR621 @U42

1K +-1% 0402

PC616 @U42

68P 50V J 0402

U22

PC626 @U22

0.047U_0402_25V7K

PR638 @U22

383 +-1% 0402

100P_0402_50V8J

PR613 @U22

90.9K +-1% 0402

PR622 @U22

1.5K +-1% 0402

GPU_B+

12

PC675

10U 25V 0603 ZRB

+5V_ALW

FCCM_GT<46>

PWM_GT<46>

PC674

10U 25V 0603 ZRB

12

PC664

10U 25V 0603 ZRB

PR680

1 2

1_0603_5%

@

12

PR664

12

PC665

10U 25V 0603 ZRB

12

PC681

VCC_GT

12

PC669

PR662

@

1 2

1 2

0_0402_5%

0.22U_0603_16V7K

1 2

3.9 +-1% 0603

0.1U 25V K X5R 0402

1U_0402_10V6K

0_0402_5%

DELL CONFIDENTIAL/PROPRIETARY

PR621 @U22

316 +-1% 0402

PC616 @U22

33P 50V J 0402

VCC_GT (U22)
TDC 18A
Peak Current 31A
OCP current 37.2A
Choke DCR 0.9 +-5%m ohm

9

PC663

1 2

PR665

8

7
6

5
4

3
2
1

2

PC624 @U42

0.015U 25V K X7R 0402

PC617 @U42

220P 50V 0402

PC617 @U22

1200P 50V 0402

PC624 @U22

.022U 16V K X7R 0402

PU612

PGND10SW
VIN

SW

VIN

GL

PHASE

PGND

N/C

PVCC

BOOT

N/C

AGND

N/C

VCC
FCCM

GL

PWM

AGND

FDMF3035_PQFN31_5X5

PJP602

PAD-OPEN 1x2m~D

GT_SW

11
12

13

14
15

16
17

19
18

VCC_GT (U42)
TDC 12A
Peak Current 28A
OCP current 33.6A
Choke DCR 0.9 +-5%m ohm

21

CPU_B+GPU_B+

PR669

RF@

4.7_1206_5%

1 2

+5V_ALW

12

12

PR681

@

10K_0402_1%

Title

Title

Title

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

GT_SNUB

0.15UH 20% MMD-06CZER15MEX5L 35A

12

PC668

1U_0402_10V6K

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

PWR_VCORE_ISL95857

PWR_VCORE_ISL95857

PWR_VCORE_ISL95857

LA-F311P

LA-F311P

LA-F311P

RF@

680P_0603_50V7K

1 2

PL612

4

3

PR661

3.65K_0603_1%

ISUMP_GT

1

<46>

PC670

1

2

47 58W ednesday, Dec ember 20, 2017

47 58W ednesday, Dec ember 20, 2017

47 58W ednesday, Dec ember 20, 2017

+VCC_GT

PC703

1 2

100P_0402_50V8J

RF@

RF reserved

ISUMN_GT

<46>

2.0

2.0

2.0

4 4

3 3

2 2

1 1

VCC_GT_+VCC_CORE Place on CPU

22U_0603 * 6 pcs +1U_0201*5 pcs

A

PC1326

22U_0603_6.3V6M

PC1325

22U_0603_6.3V6M

PC1324

22U_0603_6.3V6M

PC1323

22U_0603_6.3V6M

PC1322

22U_0603_6.3V6M

VCC_SA Place on CPU (U22/U42)

PC1327

22U_0603_6.3V6M

PC1330

1U_0201_6.3V6M

PC1331

1U_0201_6.3V6M

PC1332

1U_0201_6.3V6M

PC1333

1U_0201_6.3V6M

PC1334

1U_0201_6.3V6M

B

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

C

follow intel spec

22U_0603*12 pcs + 1U_0201*7 pcs

+VCC_GT_+VCC_CORE

1

2

+

330U_D2_2.5VM_R9M

PC1127

1

2

+

330U_D3_2VM_R6M

PC1062

1

2

12

12

12

12

12

12

12

12

12

12

12

for U42

for U42

+

220U_D7_2VM_R4.5M

PC1321

@U42

12

PC1099

1U_0201_6.3V6M

12

PC1095

1U_0201_6.3V6M

12

PC1094

1U_0201_6.3V6M

12

PC1096

1U_0201_6.3V6M

12

PC1090

1U_0201_6.3V6M

12

PC1093

1U_0201_6.3V6M

12

PC1091

1U_0201_6.3V6M

12

PC1097

1U_0201_6.3V6M

12

PC1092

1U_0201_6.3V6M

12

PC1098

1U_0201_6.3V6M

12

PC1050

1U_0201_6.3V6M

12

PC1051

1U_0201_6.3V6M

12

PC1052

1U_0201_6.3V6M

12

PC1053

1U_0201_6.3V6M

12

PC1083

1U_0201_6.3V6M

12

PC1030

1U_0201_6.3V6M

12

PC1031

1U_0201_6.3V6M

12

PC1032

1U_0201_6.3V6M

12

PC1033

1U_0201_6.3V6M

12

PC1034

1U_0201_6.3V6M

12

PC1035

1U_0201_6.3V6M

12

PC1036

1U_0201_6.3V6M

12

PC1037

1U_0201_6.3V6M

12

PC1038

1U_0201_6.3V6M

12

PC1039

1U_0201_6.3V6M

12

PC1084

1U_0201_6.3V6M

12

PC1086

1U_0201_6.3V6M

12

PC1085

1U_0201_6.3V6M

12

PC1088

1U_0201_6.3V6M

12

PC1087

1U_0201_6.3V6M

12

PC1089

1U_0201_6.3V6M

PC1081

22U_0603_6.3V6M

PC1080

22U_0603_6.3V6M

PC1082

22U_0603_6.3V6M

PC1067

22U_0603_6.3V6M

PC1072

22U_0603_6.3V6M

PC1069

22U_0603_6.3V6M

PC1074

22U_0603_6.3V6M

PC1070

22U_0603_6.3V6M

PC1061

22U_0603_6.3V6M

PC1071

22U_0603_6.3V6M

PC1066

22U_0603_6.3V6M

PC1073

22U_0603_6.3V6M

PC1068

22U_0603_6.3V6M

PC1075

22U_0603_6.3V6M

PC1064

22U_0603_6.3V6M

PC1065

22U_0603_6.3V6M

PC1076

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

22U_0603_6.3V6M

PC1078

22U_0603_6.3V6M

PC1077

22U_0603_6.3V6M

PC1079

22U_0603_6.3V6M

PC1001

22U_0603_6.3V6M

PC1002

22U_0603_6.3V6M

PC1003

22U_0603_6.3V6M

PC1004

22U_0603_6.3V6M

PC1005

22U_0603_6.3V6M

PC1006

22U_0603_6.3V6M

PC1007

22U_0603_6.3V6M

PC1008

22U_0603_6.3V6M

PC1009

22U_0603_6.3V6M

PC1010

22U_0603_6.3V6M

PC1011

22U_0603_6.3V6M

PC1012

22U_0603_6.3V6M

PC1013

22U_0603_6.3V6M

+VCC_CORE +VCC_GT

VCC_CORE Place on CPU (U22)

22U_0603 * 33 pcs +1U_0201*31 pcs

+330u_D2*2 pcs

A

12

12

12

12

12

12

12

12

VCC_CORE Place on CPU (U42)

22U_0603 * 33 pcs +1U_0201*31 pcs

12

12

12

12

12

12

12

12

12

+330u_D2*2 pcs+220u_D7*1 pcs

B

C

VCC_GT Place on CPU (U22)

22U_0603 * 19 pcs +1U_0201*14 pcs

+330u_D2*2 pcs

1

2

+VCC_SA

D

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Nu mber Re v

Date: Sheet o f

Title

Size Document Nu mber Re v

Date: Sheet o f

Title

Size Document Nu mber Re v

Date: Sheet o f

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

PROCESSOR DECOUPLING

PROCESSOR DECOUPLING

PROCESSOR DECOUPLING

LA-F311P

LA-F311P

LA-F311P

E

48 58Wednesday, December 20, 2017

48 58Wednesday, December 20, 2017

48 58Wednesday, December 20, 2017

12

PC1153

1U_0201_6.3V6M

12

PC1147

1U_0201_6.3V6M

12

PC1148

1U_0201_6.3V6M

12

PC1149

1U_0201_6.3V6M

12

PC1150

1U_0201_6.3V6M

12

PC1151

1U_0201_6.3V6M

12

PC1152

1U_0201_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

12

PC1057

12

PC1058

12

PC1059

12

PC1060

12

PC1139

12

PC1140

12

PC1141

12

PC1142

12

PC1143

12

PC1144

12

PC1145

12

PC1146

+

PC1128

330U_D2_2.5VM_R9M

1

2

+

PC1063

330U_D3_2VM_R6M

12

PC1040

1U_0201_6.3V6M

12

PC1041

1U_0201_6.3V6M

12

PC1042

1U_0201_6.3V6M

12

PC1043

1U_0201_6.3V6M

12

PC1044

1U_0201_6.3V6M

12

PC1045

1U_0201_6.3V6M

12

PC1046

1U_0201_6.3V6M

12

PC1047

1U_0201_6.3V6M

12

PC1048

1U_0201_6.3V6M

12

PC1049

1U_0201_6.3V6M

12

PC1055

1U_0201_6.3V6M

12

PC1056

1U_0201_6.3V6M

12

PC1328

1U_0201_6.3V6M

12

PC1329

1U_0201_6.3V6M

for U42

PC1133

22U_0603_6.3V6M

PC1137

22U_0603_6.3V6M

PC1129

22U_0603_6.3V6M

PC1132

22U_0603_6.3V6M

PC1136

22U_0603_6.3V6M

PC1134

22U_0603_6.3V6M

PC1135

22U_0603_6.3V6M

PC1138

22U_0603_6.3V6M

PC1027

22U_0603_6.3V6M

PC1028

22U_0603_6.3V6M

PC1130

22U_0603_6.3V6M

PC1029

22U_0603_6.3V6M

PC1131

22U_0603_6.3V6M

12

12

12

12

12

12

12

12

12

12

12

12

12

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

@

@

@

@

@

@

@

PC1014

PC1015

PC1016

PC1017

PC1018

PC1019

PC1020

PC1021

PC1022

PC1023

PC1024

PC1025

PC1026

12

12

12

12

12

12

12

12

12

12

12

12

12

D

E

2.0

2.0

2.0

A

+SDC_IN

1 1

12

PR909

2 +-1% 0603

12

PC926

DCIN_ISL9538

VDD_ISL9538

ACIN_ISL9538

0_0402_5%

PC938

10P_0402_50V8J

1 2

0_0402_5%

1U 25V K X5R 0402

17

DCIN

18

VDD

19

ACIN

20

OTGEN/CMIN

21

SDA

22

SCL

23

PROCHOT#

24

ACOK

PR933

100K_0402_1%

1 2

PR951

@

1 2

COMP_ISL9538

12

PR934

12

499 +-1% 0402

PC943

@

12

560P_0402_50V7K

PC944

0.01UF 25V K X7R 0402

Close to EC ADP_I pin

16

25

PC955

PROCHOT#<12,31,46>

+SDC_IN

12

@

0_0402_5%

1 2

@

1 2

PR928

0_0402_5%

PR931

100K_0402_1%

1 2

12

PR944
442K_0402_1%

ACIN_ISL9538

12

PR945
100K_0402_5%

PR960

@

1 2

0_0402_5%

PR919

@

PR920

@

1 2

PR926

@

0_0402_5%

1 2

OTGEN/CMIN

1 2

1 2

PR922

0_0402_5%

ACOK_ISL9538

@

PR930

100K_0402_1%

1 2

PR943

0_0603_5%

PROCHOT#_ISL9538

+PWR_SRC

PD901

SDMK0340L-7-F_SOD323-2~D

+VBUS_DC_SS

2 2

+DC_IN_SS

SDMK0340L-7-F_SOD323-2~D

PC931 1U_0603_25V6

PD903

2 1

RB520SM-30T2R_EMD2-2

PD904

1 2

12

12

0.1U 25V K X5R 0402

PR916
1_0805_5%~D

1 2

12

PC933

1U_0402_6.3V6K

ACAV_IN1

PQ909

13

D

PR927

154K_0402_1%

S

PR925

DMN65D8LW-7_SOT323-3

3 3

2

AC_DIS<31>

G

12

1M_0402_1%

PR918
100K_0402_1%

1 2

PBAT_CHARGER_SMBDAT<31,40>

12

PBAT_CHARGER_SMBCLK<31,40>

PROCHOT#_ISL9538<50>

PBAT_PRES#<31,40>

+3.3V_ALW

CMOUT<50>

PR948

@U42

SD034118280

11.8K +-1% 0402

PR948

@U22

4 4

A

SD034127280

12.7K +-1% 0402

PR901

0.01_1206_1%

1

2

PR910

2 +-1% 0603

CSIP_ISL9538

PC925

4.7U 6.3V M X5R 0402

1 2

ADP_ISL9538

CSIP_ISL9538

CSIN_ISL9538

13

14

15

ADP

CSIP

CSIN

ASGATE

CMOP

BATGONE

OTGPG/CMOUT26PROG27AMON/BMON29PSYS30VBAT

28

12

PR932

105K +-1% 0402

@

PR947

0_0402_5%

12

12

I_BATT

I_ADP

I_BATT <31>

I_ADP <31>

B

+PWR_SRC_AC

4

3

12

12

CSIN_ISL9538

PC930

0.22U_0603_25V7K

1 2

12

PR914
0_0603_5%

UG1_ISL9538

LX1_ISL9538

BOOT1_ISL9538

11

10

12

BOOT1

PHASE1

UGATE1

31

VBAT1_ISL9538

12

PC947

0.1U_0402_25V6

@

PR935
0_0402_5%

I_SYS <31,46>

0.1U_0402_25V6

B

EMC@

PL901

1UH +-20% 6.6A 5X5X3 MOLDING, A.3

PD906

SMF4L22A SOD123FL-2

PJP901

@

1 2

PAD-OPEN 4x4m

12

12

PC927

1U 25V K X5R 0402

LG1_ISL9538

PR915

4.7 +-5% 0603

1 2

PU901

9

33

S IC ISL9538HRTZ-REV.C-T TQFN32P CHARGER

PAD

VDDP_ISL9538

8

LGATE1

VDDP

LG2_ISL9538

7

LGATE2

LX2_ISL9538

6

PHASE2

UG2_ISL9538

5

UGATE2

BOOT2_ISL9538

4

BOOT2

3

VSYS

CSOP_ISL9538

2

CSOP

CSON_ISL9538

1

CSON

BGATE

32

BGATE_ISL9538

12

@

12

PR936
0_0402_5%

PR948

@

1U 25V K X5R 0402

12.7K +-1% 0402

PC950

@

100_0402_1%

1 2

12

PC902

PC903

0.1U_0402_25V6

@EMC@

@EMC@

VDD_ISL9538

PC932

1U_0402_6.3V6K

12

PC934

12

0.22U_0603_25V7K

PR929

@

1 2

0_0402_5%

PC945

+PBATT

12

PR940

C

+CHARGER_SRC

12

12

PC911

2200P_0402_50V7K

10U 25V K X6S 0805

12

12

PC905

PC904

PC906

10U 25V K X6S 0805

10U 25V K X6S 0805

12

PC952

PC951

10U_0805_25VAK

PQ905
AON6962 2N DFN5X6D-8

PR921

12

2.2_0603_5%

+PWR_SRC

1 2

PC939 0.1U_0402_25V6@

1 2

PC942 1U 25V K X5R 0402@

1 2

PR937 1 +-1% 0603

PR938 1 +-1% 0603

1 2

1 2

1 2

PC946 0.22U 25V K X5R 0402

AC1_DISC#<23,50>

HW_ACAVIN_NB<31,40,50>

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

12

+

PC909

2

10U 25V K X6S 0805

15U_B2_25VM_R100M

@

E9 delete 15uF*2

12

10U_0805_25VAK

UG1_ISL9538

1

2

D1

D2/S1

S24S2

S2

5

3

6

LG1_ISL9538

PR939

@

1 2

1 2

0_0402_5%

@

PR941

G1

2.2UH_PCMB103T-2R2MS_13A_20%

7

G2

12

LX1_ISL9538

SNUB_CHG1

12

@EMC@

BAT54CW_SOT323-3

3

0_0402_5%

2

C

PL902

1 2

PR923

4.7_1206_5%

@EMC@

PC940

680P_0603_50V7K

PD905

1

12

PR961

@

100K_0402_1%

PR924

4.7_1206_5%

@EMC@

PC941

680P_0603_50V7K

@EMC@

12

SNUB_CHG2

12

1 2

ACAV_IN1

@

LX2_ISL9538

PR950

@

0_0402_5%

0.1U_0402_10V7K

PR942

1 2

0_0402_5%

UG2_ISL9538

1

7

D2/S1

6

LG2_ISL9538

PC949

1 2

+PWR_SRC

PC913

PC928

@EMC@

PQ904
AON6962 2N DFN5X6D-8

2

D1

G1

S24S2

S2

G2

5

3

LM393_P

5

1

P

B

2

A

G

3

12

12

PC915

PC914

10U_0805_25V6K

10U_0805_25V6K

12

12

PC929

0.1U_0402_25V6
2200P_0402_50V7K

@EMC@

PR917

0.005_1206_1%

1

2

MC74VHC1G08DFT2G SC70 5P AND

PU903

PR946

@

4

1 2

Y

0_0402_5%

D

1

12

12

PC916

10U_0805_25V6K

12

PC956

1000P_0402_50V7K

@EMC@

+

PC921

2

10U_0805_25V6K

15U_B2_25VM_R100M

100P_0402_50V8J

100P_0402_50V8J

PC961

12

12

PC957

PC958

PC959

1U_0402_25V6K

@EMC@

@EMC@

1000P_0402_50V7K

@EMC@

PC960

12

12

12

1U_0402_25V6K

12

RF@

RF@

RF reserve d

12

PC936

10U_0805_25V6K

PQ906
EMZB08P03V 1P EDFN3X3-8

1
2
3 5

4

PC937

1 2

@

4700P_0402_25V7K

+VCHGR

4

3

12

PC935

10U_0805_25V6K

ACAV_IN<31>

12

PR953
100K_0402_1%

Add PR953 for IT8010 voltage leakage issue

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

P59 PWR-Charger

P59 PWR-Charger

P59 PWR-Charger

LA-F311P

LA-F311P

LA-F311P

D

100P_0402_50V8J

PC962

RF@

+PBATT

BGATE_ISL9538

2.0

2.0

49 58Wednesday, December 20, 2017

49 58Wednesday, December 20, 2017

49 58Wednesday, December 20, 2017

2.0

5

DCIN_ AC_Dete ctor

PC1201

@

0.01U_0402_25V7K~D

1 2

12

3

2

BAT54CW-7-F SOT-323

PC1206

220P_0402_50V8J~D

PD1801

1

LM393_P

8

3

P

+

2

-

G

4

EMI Part

5A_Z120_25M_0805_2P

1 2

1 2

5A_Z120_25M_0805_2P

EMC@

12

PC1208

EMC@

1000P_0402_50V7K

LM393_P

PR1203

1.8M_0402_1%

1 2

PU1201A
LM393DGKR_VSSOP8

1

O

PL1201

EMC@

PL1202

+3.3V_VDD_DCIN

12

PR1206
1K_0402_1%

12

PC1207

1200P_0402_50V7K

12

PR1227

100K_0402_5%

HW_ACAVIN_NB

HW_ACAVIN_NB <31,40,49,50>

+TBTA_Vbus_1

12

PC1216

100P_0402_50V8J

EMC@

+3.3V_VDD_DCIN

+DC_IN

D D

PR1201

PR1219

C C

240K_0402_1%

23.2K +-1% 0402

12

(>17.6V)

12

PR1208

PR1217

12

102K_0402_1%

12

84.5K_0402_1%

+3.3V_VDD_DCIN

+3.3V_VDD_PIC

12

PC1205

100P_0402_50V8J~D

+TBTA_VBUS

PC1209 can't over 1000P

B B

+TBTA_Vbus_1 +3.3V_VDD_PIC

12

PR1237

100K_0402_1%

@

12

PR1239

150K_0402_1%

@

12

12

12

PC1211

PR1246

PR1247

100P_0402_50V8J

@

100K_0402_1%

@

100K +-1% 0402

S3 OVP

PD1205

@

SDMK0340L-7-F_SOD323-2

1 2

PR1238

@

1 2

0_0402_5%

5

6

12

PC1212

@

100P_0402_50V8J

LM393_P

8

+

-

4

PU1201B
LM393DGKR_VSSOP8

P

7

O

G

12

PR1240
100K_0402_1%

@

PR1243

1 2

12

PC1213

@

1200P_0402_50V7K

0_0402_5%

+TBTA_Vbus_1

4

5

12

PC1214

@

+AC_IN

+3.3V_VDD_PIC

PR1236
100K_0402_5%

1 2

34

PQ1209B

DMN65D8LDW-7_SOT363-6

0.01UF_0402_25V7K

PJP1202

@

2

112

JUMP_43X118

PQ1206

S3

EMZB08P03V 1P EDFN3X3-8

1
2
35

4

PC1210

1500P_0402_50V7K

12

PR1229

49.9K +-1% 0402

61

PQ1209A

2

DMN65D8LDW-7_SOT363-6

+3.3V_VDD_PIC

EN_PD_HV_1<23,50>

1M_0402_5%

EN_PD_HV_1<23,50>

(From TI GPIO1)

DCIN1_EN<31>

12

1 2

PR1228

499K +-1% 0402

12

12

PR1210

PR1255

@

150K_0402_1%

PR1253
100K_0402_5%

EN_PD_HV_1#

34

5

12

@

PR1221

1 2

0_0402_5%

2

PQ1214B

@

DMN65D8LDW-7_SOT363-6
0_0402_5%

+3.3V_ALW

12

300K +-5% 0402

12

61

PC1204

0.1U_0402_10V7K

PR1254

1 2

PR1211

@

1 2

1 2

0_0402_5%

@

PR1215

12

PR1224

100K_0402_5%

3

PR1251

G

2

PR1252
100K_0402_5%

PQ1214A

DMN65D8LDW-7_SOT363-6

12

5

0_0402_5%

1

P

B

2

A

G

3

PQ1205

DMN65D8LW-7_SOT323-3

D

S

13

G

2

12

@

PR1225
0_0402_5%

S

12

PC1202

PR1205

PQ1215

D

1 3

499K +-1% 0402

0.47U 25V K X7R 0603

AO3409 P-CHANNEL SOT-23

+3.3V_VDD_PIC

4

PR1226

+3.3V_VDD_PIC

12

1 2

100K_0402_5%

PU1200
MC74VHC1G08DFT2G SC70 5P AND

O

S4 S5

PQ1213

EMZB08P03V 1P EDFN3X3-8

1
2
3 5

12

12

PR1212

49.9K +-1% 0402

61

2

@

PR1216
0_0402_5%

12

EN_PD_HV_1<23,50>

AC1_DISC#<23,49>

4

PQ1201A

DMN65D8LDW-7_SOT363-6

PR1262
100K_0402_1%

PR1260

@

0_0402_5%

1 2

@

1 2

PR1244

0_0402_5%

+VBUS_DC_SS

VBUS1_ECOK<31,50>

+3.3V_ALW

PR1259

100K_0402_5%

1 2

34

D

5

G

S

HW_ACAVIN_NB<31,40,49,50>

VBUS1_ECOK

100K_0402_5%

PQ1208B

DMN65D8LDW-7 2N SOT363-6

VBUS2_ECOK<31,40>

VBUS1_ECOK<31,50>

PR1234

2

G

PR1261

@

0_0402_5%

1 2

2

S SCH DIO 5A 100V 15UA 0.88V TO227-3

@

PR1220

1 2

12

0_0402_5%

PR1222

100K_0402_5%

@

0_0402_5%

1 2

1 2

@

PR1257

+3.3V_ALW

1 2

61

D

PQ1208A

S

DMN65D8LDW-7 2N SOT363-6

PR1241

@

1 2

0_0402_5%

PD1202

2

1

3

PQ1202
EMZB08P03V 1P EDFN3X3-8

1
2
35

4

12

PR1213

34

49.9K +-1% 0402

5

PQ1201B

DMN65D8LDW-7_SOT363-6

@

100K_0402_5%

1 2

PR1242

0_0402_5%

2

G

+3.3V_ALW

PR1232

100K_0402_5%

1 2

34

D

5

G

S

12

12

PC1203

PR1207

1500P_0402_50V7K

499K +-1% 0402

AO3409 P-CHANNEL SOT-23

+3.3V_ALW+3.3V_ALW

PR1235

@

100K_0402_5%

1 2

61

D

5

G

PQ1211A

S

+3.3V_ALW

DMN65D8LDW-7 2N SOT363-6

1 2

61

D

2

G

S

PQ1207B
DMN65D8LDW-7 2N SOT363-6

1 2

PR1258

@

0_0402_5%

12

PR1202
300K +-5% 0402

S

G

PQ1203

2

D

1 3

12

PR1209
100K_0402_5%

34

5

PQ1204B

DMN65D8LDW-7_SOT363-6

PR1233

+3.3V_ALW

AC_DISC# <31,40,50>

34

D

12

S

PC1217

@

PQ1211B

DMN65D8LDW-7 2N SOT363-6

PR1230
100K_0402_5%

PQ1207A
DMN65D8LDW-7 2N SOT363-6

1 2

61

D

S

1500P_0402_50V7K

@

PR1218

1 2

0_0402_5%

PR1231
100K_0402_5%

PR1245

@

1 2

0_0402_5%

G

PQ1210A

DMN65D8LDW-7 2N SOT363-6

+3.3V_VDD_PIC

2

1

+SDC_IN

12

PR1214
100K_0402_5%

61

@

PR1223

2

1 2

PQ1204A

DMN65D8LDW-7_SOT363-6

34

D

5

G

S

13

D

2

G

S

PQ1216

AC_DISC# <31,40,50>

0_0402_5%

CMOUT <49>

PQ1210B

DMN65D8LDW-7 2N SOT363-6

PROCHOT#_ISL9538 <49>

DMN65D8LW-7_SOT323-3

OVP set t i ng: 5. 5V

PR1248

12

PR1249
10K_0402_5%

@

0_0402_5%

1 2

PR1250

@

1 2

0_0402_5%

13

D

2

G

S

A A

PQ1212

DMN65D8LW-7_SOT323-3

LPS_PROTECT#

PT1

@

PAD~D

(From EC)

EN_PD_HV_1 <23,50>

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

Title

Size

Size

Size

Date: Sheet

Date: Sheet

Date: Sheet

TypeC_PD

TypeC_PD

TypeC_PD

Document Number Re v

Document Number Re v

Document Number Re v

LA-F311P

LA-F311P

LA-F311P

1

50 58Wednesday, December 20, 2017

50 58Wednesday, December 20, 2017

50 58Wednesday, December 20, 2017

of

of

of

2.0

2.0

2.0

5

4

3

2

1

Version Change List ( P. I. R.

List )

Item

1

57 Change DrMOS from TI to Fairlchild PU610/ PU612/ PU613 change to FDMF3035 (SA0000AHX00) X01Compal

50
51
52

2

53

D D

56
57
59

Title

VCC_CORE
VCORE_VGT, VSA

+3.3V_ALW, +5V_ALW
VCC_CORE
VCORE_VGT, VSA
Charger

Request Owner

Date

2017
06/07

2017
06/12

Larry

Issue

Description

RF team request some item

Add PC315, PC314, PC960, PC961, PC962, PC700, PC701,
PC142, PC143,

Reserved PC316, PC12, PC702, PC141,PC695, PC696,PC224, PC703

Solution
Description

Rev.Page#

X01

+3.3V_ALW, +5V_ALW

51

VCC_CORE

3

57

VCORE_VGT, VSA

59

Charger

57

Charger

59

4

5

C C

VCC_CORE

57

VCORE_VGT

2017
06/12

2017
06/12

2017
06/19

EMI need to modify

Albert X01

Compal Change component for acoustic solution

Add one more bulk for acoustic solution

Compal

1. Depop PC133, PC134, PC135, PC136, PC137, PC138, PC139, PC140,
PC689, PC690, PC691, PC692, PC956, PC957, PC958, PC959.

2. Pop PL901.

1. CPU input MLCC change to 0603 size and change to low noise
MLCC (SE00000X210): PC608, PC612, PC656, PC657, PC658, PC664, PC665,
PC672, PC673, PC674, PC675, PC682, PC683, PC684

2. Remove PC917~PC920(10U*4pcs) , add PC921(15U pos cap)

Pop 2pcs 100uf (PC606,PC607)

X01

X01

7

8

12

13

14

15

16

B B

Compal

Compal

Compal

Compal

Compal

17 Compal

18 Compal

19

20

21

22

23

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

PWR P.I.R

PWR P.I.R

PWR P.I.R

Size Document Number R e v

Size Document Number R e v

Size Document Number R e v

LA-F311P

LA-F311P

LA-F311P

Date: Sheet

Date: Sheet

Date: Sheet

51 58Wednesday, December 20, 2017

51 58Wednesday, December 20, 2017

51 58Wednesday, December 20, 2017

of

of

of

1

2.0

2.0

2.0

5

Timing Diagram for S5 to S0 mode

D D

6

C C

VCCST_PWRGD

12

H_CPUPWR GD

15

PCH_PLTRS T#

17

0.6V_DDR_VTT_ON

12

+1.0V_PRIM_C ORE

+1.8V_PRIM

6

6

+1.0V_PRIM SY8286

CPU

VCCST_PWRGD

PROCPWRGD

PLTRST#

DDR_VTT_CNT L

+PWR_SR C

TPS62134

+3.3V_ALW

RT8097

+PWR_SR C

VCCIO

VCCGT

VDDQ
VDDQC
VCCPLL_OC

VCCST
VCCSTG
VCCPL L

VCCSA

SIO_SLP_SU S#

+VCC_CO RE

VCC

+1.0VS_VCCIO

+VCC_GT

+1.2V_MEM

+1.0V_VCC ST

+VCC_S A

4

+1.0V_PRIM

11

TPS22961

SIO_SLP_S4 #

+LCDVD D

11

+5V_TSP

3

+3.3V_ALW

+3.3V_SPI

3

+1.0V_MPHYGT

5

6

+1.0V_PRIM_C ORE

6

17

4

+3.3V_ALW

G524B1T11

+3.3V_ALW

EM5209VF+3.3V_LAN

+5V_RU N

LP2301ALT1G

+3.3V_RUN

LP2301ALT1G+3.3V_CAM

+1.0V_PRIM

+3.3V_ALW_DSW

+3.3V_ALW_PCH

+1.8V_PRIM

+RTC_CEL L

PCH_PLTRS T#

PCH_DPWR OK

ENVDD_PCH

SIO_SLP_LAN#

@PCH_3.3V_TS _EN

3.3V_TS_EN (EC)

3.3V_CAM_EN#

VCCPRIM_1P0
VCCPRIM_CORE
DCPDSW _1P0
VCCMPHYAON_1P0
VCCAPLL_1P0
VCCCLK1~ 6
VCCMPHYGT_1P0
VCCSRAM_1P0
VCCAMPHYPLL_1P0
VCCAPLLEBB

VCCDSW_3P 3

VCCHDA
VCCSPI
VCCPRIM_3P3
VCCPGPPA~E
VCCRTCPRIM

VCCPGPPG
VCCATS

VCCRTC

VCCPRIM_CORE

PLTRST#

DSW_PWROK

EDP_VDDEN

SLP_LAN#

GPP_B21

GPD7

PCH

PWRBTN#

RSMRST#

SLP_SUS #

SLP_S5 #

SLP_S4 #

SLP_S3 #

SLP_LAN#

SLP_WLAN#/GPD 9

SYS_PWROK

PCH_PWRO K

VCCST_PWRGD

PROCPWRGD

SLP_A#

2

SIO_PWRBTN#

PCH_RSMRST #

SIO_SLP_SU S#

SIO_SLP_S5 #

SIO_SLP_S4 #

SIO_SLP_S3 #

SIO_SLP_A#

SIO_SLP_LAN#

SIO_SLP_WLAN#

RESET_OUT#

PCH_PWRO K

VCCST_PWRGD

H_CPUPWR GD

16

15

10

11

14

12

1

8

7

5

9

Power Button

SIO_SLP_WLAN#

EC 5105

11

11

RUN_ON

+5V_ALW

EM5209VF

+5V_RU N

+3.3V_ALW

EM5209VF

+1.8V_PRIM

EM5209VF +1.8V_ RUN

+PWR_SR C

TLV62130

SLP_WLAN#_GATE

OR
Gate

SIO_SLP_WLAN#

NMOS

AUX_EN_WOWL

B B

+3.3V_WLAN EM5 209VF

11

A A

+3.3V_RUN

+1.0VS_VCCIO

13

+3.3V_HDD_M2

+VCC_S A

+VCC_CO RE

+VCC_GT

10

+PWR_SR C

ISL95857

PCH_PWRO K

14

ADAPTER

BATTERY

7

4

16

5

9

11

PCH_RSMRST #

PCH_DPWR OK

RESET_OUT#

SIO_SLP_SU S#

SIO_SLP_S4 #

SIO_SLP_S5 #

SIO_SLP_LAN#

SIO_SLP_S3 #

SIO_SLP_A#

12

IMVP_VR_ON

2AC1BAT

@PCH_ALW_ON

+PWR_SR C

ALWON

+PWR_SR C

5

SIO_SLP_SU S#

EN_INVPWR

10

SIO_SLP_S4 #

0.6V_DDR_VTT_ON

SYV828EC 5105

SY8288

+3.3V_ALW

EM5209VF+3.3V_ALW

+PWR_SR C

AO6405

+PWR_SR C

SY8210

+5V_ALW2
+5V_ALW

+3.3V_RTC _LDO
+3.3V_ALW2
+3.3V_ALW

+3.3V_ALW_PCH

+BL_PWR_S RC

+1.2V_MEM

+0.6V_DDR _VTT

12

1BAT

2AC

5

Pop option

+3.3V_SPI

18

VDDQ

VTT

DDR

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date : Sheet

Date : Sheet

Date : Sheet

Power Sequence

Power Sequence

Power Sequence

LA-F312P

LA-F312P

LA-F312P

1

52 58Wednesday, December 20, 2017

52 58Wednesday, December 20, 2017

52 58Wednesday, December 20, 2017

of

of

of

2.0

2.0

2.0

5

4

3

Version Change List ( P. I. R. List ) LA-F312P

2

1

Page#

D D

2 8 JSPI1 connector change vendor

3

5 14

6 16

C C

10 28 ESD requestESD Remove DV7, DV8

11

Title

CPU (3/14)

CPU (3/14)

CPU (6/14)

CPU (8/14)

CPU (9/14)

CPU (11/14)

CPU (13/14)

EC MEC5105

EC MEC5105
Support

eDP CONN &
Touch screen

USH & TPM

NGFF Card

EC MEC5105

All

Date Issue DescriptionItem

2017/03/21

2017/03/21

2017/03/21

2017/03/21

2017/03/21

2017/03/21

2017/03/21

2017/03/21

2017/03/21

2017/03/21

2017/03/21

2017/03/21

2017/03/21

Owner

Winbond 16MB SPI ROM EOL (change to J-die)1 8 2017/03/21 EE

ME

KBL-R U42 X'tal11 EE

KBL-R CRB schematic4 13 EE

JXDP1 connector change vendorME Change JXDP1 to SP01001VB00

EE Reserve RC437, RC438

Follow KBL-R_U42_Processor_Line_BGA1356_
Ballout_Rev1p0

RTC Power Gate Circuit for +3.3V_DSW7 18 EE Add RC431~RC433, RC439, RC440, QC6, QC7

RTC Power Gate Circuit for RTCRST8 33 EE Add QE14~QE17, RE540~RE546, RE551, CE63, RC441, RC442, DC1, DC2, RC445

Remove IO expander9 34 EE Remove UE2 relating circuit

TPM NPCT65X and NPCT75X schematic colay35 EE UZ12 relating circuit and change UZ12 to SA0000AQ200

RF request to align w/ BR MLK12 31 RF LI8, LI9 change to SM070003Z00, LI16, LI17 change to SM070003V00

RTCRST_ON glitch 13 33 EE Reserve CE64

Port map change14 All EE JUSB1 change to USB30_port6 and USB20_port9

Change JSPI1 to SP010022Q00

Add RC415~RC420,CC334,CC335,YC3

Add RC436 0ohm to GND

USB20_port1 BOM option to Type-C(PD UT5)
Delete PS8338 and WIGIG circuit and connect DDI2 to UT1
(Add RC446~RC448 for CPU_DP2_HPD/CPU_DP2_AUXP/CPU_DP2_AUXN)

Solution Description

Rev.

0.1(X00)Change UC5, UC6 to SA00005VV20

0.1(X00)

0.1(X00)

0.1(X00)

0.1(X00)

0.1(X00)

0.1(X00)

0.1(X00)

0.1(X00)

0.1(X00)

0.1(X00)

0.1(X00)

0.1(X00)

0.1(X00)

Request

[Type C]PD

2315 Change UT5 to SA0000AP500Change PD to PD3.0 EE 0.1(X00)2017/03/28

B B

16 9

18 33 Add RZ364 100 ohm to POA_WAKE#EE

20 25 ESD request

A A

Controller TI

CPU (4/14)

EC MEC5105
Support

USH & TPM

USH & TPM

3319 Add DZ8EE 0.1(X00)2017/03/28

[Type C]USB3.0
CONN

CPU (6/14)

2017/03/28

EE JUART1 reverse JUART1 pin SWAP2017/03/28 0.1(X00)

Panel ID define changeEE3217

Prevent POA_WAKE# ESD

RE300 change to 130K ohm for 12"
RE300 change to 62K ohm for 13"

0.1(X00)

0.1(X00)2017/03/28

Prevent Contactless_det# backdrive

ESD 0.1(X00)2017/03/28

RTC Power Gate Circuit optionEE1121 Add RC441, RC442, DC1, DC2, RC4452017/03/28

Change DT7, DT8, DT11, DT12 to DT39
Change DT15, DT16, DT19, DT20 to DT40

0.1(X00)

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document N umber Re v

Size Document N umber Re v

Size Document N umber Re v

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

Compal Electronics, Inc.

EE P.I.R (1/6)

EE P.I.R (1/6)

EE P.I.R (1/6)

LA-F312P

LA-F312P

LA-F312P

53 58Wednesday, December 20, 2017

53 58Wednesday, December 20, 2017

53 58Wednesday, December 20, 2017

1

2.0

2.0

2.0

5

4

3

Version Change List ( P. I. R. List ) LA-E122P

2

1

Request

All

All

Title

All

Date Issue DescriptionItem

2017/03/28

2017/03/30 PANEL_ID -> SYSTEM_ID

2017/03/30

Owner

GPIO map changeEEAll22 0.1(X00)PCH_RSMRST#_GPIO204 -> USH_PWR_STATE# (delete RE363)

GPIO map changeEEAll24 0.1(X00)UE1.B1 -> add net name 3.3V_ALW2 and depop RE57 (Microchip suggest)

PORT80_DET# -> DCIN1_EN (delete RE512,RE513,RZ131)
SHD_IO3 -> VBUS1_ECOK
SHD_IO1 -> SATA_LED_EN
ENVDD_PCH -> DCIN2_EN
SIO_RCIN#_EC -> VBUS2_ECOK and delete RE339/RC13
USH_SMBCLK -> USH_EXPANDER_SMBCLK
USH_SMBDAT -> USH_EXPANDER_SMBCLK
Delete RTCRST_ON_GPIO141
PRIM_PWRGD_GPIO024 -> RESET_IN#

3.3V_TS_EN rename to PCH_3.3_TS_EN
SHD_IO0 change to 3.3V_TS_EN and delete RE366 and PU 100K RE547
Add RV323/RV324 for 3.3V_TS_EN/PCH_3.3V_TS_EN option

SHD_IO1 -> SATA_LED_EN -> MASK_SATA_LED#
EXPANDER_GPU_SMDAT -> VCCDSW_EN_GPIO and delete RE524
EXPANDER_GPU_SMCLK -> free and delete RE525
THERMATRIP1# -> THERMTRIP1#
THERMATRIP2# -> THERMTRIP2#
SIO_EXT_SCI#_EC -> free and delete RE341
FAN1_TACH -> TACH_FAN1
LCD_TST -> free
WWAN_RADIO_DIS# -> LCD_TST
EC GPIO123 (UE1.F12) -> WWAN_RADIO_DIS#
DCIN3_EN -> EC GPIO202 (UE1.J6) (SBMLK 12/13 only)
FAN1_PWM -> PWM_FAN1
PS_ID -> free
SHD_CLK -> PS_ID and delete RE374
AUD_NB_MUTE# -> NB_MUTE#

RESET_IN# -> Remove RE361 (Microchip suggest)
SLOT2_CONFIG_3 -> NGFF_CONFIG_3
ME_FWP -> ME_FWP_PCH
ME_FW_EC -> ME_FWP
HW_GPS_DISABLE# -> GPS_DISABLE#
VGA_ID -> BEEP
H_PROCHOT# -> PROCHOT#
USB_PWR_SHR_VBUS_EN -> USB_POWERSHARE_VBUS_EN
USB_PWR_SHR_LFT_EN# -> USB_POWERSHARE_EN#
SIO_EXT_SMI#_EC -> free and delete RE338
CLKRUN#_EC -> ENABLE_DS# and delete RE337 and add RE549, RE550
SHD_IO2 -> 1.8V_PRIM_PWRGD and delete RE360
BEEP -> VGA_IDENTIFY (rename from VGA_ID)
SHD_CS# -> PCH_RSMRST# and delete RE364
SLOT2_CONFIG_0 -> NGFF_CONFIG_0
SLOT2_CONFIG_1 -> NGFF_CONFIG_1
SLOT2_CONFIG_2 -> NGFF_CONFIG_2
ACAV_IN_NB -> HW_ACAVIN_NB
LID_CL#_NB -> LID_CL_SIO#
SYS_PWROK->reserved 0ohm RE548 and add netname to RESET_OUT

Page#

D D

23 All EE GPIO map change

C C

B B

Solution Description

Rev.

0.1(X00)

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document N umber Re v

Size Document N umber Re v

Size Document N umber Re v

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

Compal Electronics, Inc.

EE P.I.R (2/6)

EE P.I.R (2/6)

EE P.I.R (2/6)

LA-F312P

LA-F312P

LA-F312P

54 58Wednesday, December 20, 2017

54 58Wednesday, December 20, 2017

54 58Wednesday, December 20, 2017

1

2.0

2.0

2.0

5

4

3

Version Change List ( P. I. R. List ) LA-F312P

2

1

Page#

D D

11
31

17
39

32

29 39 EE

31 +5V_RUN for FANEE

32 39

C C

33 32

34 31

35 11

36 30

37 31

38 11

39

B B

32 0.1(X00)Change DE1 to SC400002J002017/04/11

11

10
23

All41 GPIO map change 0.1(X00)RC443 BOM structure change to @

Title

All

CPU (6/14)
EC MEC5105

CPU (12/14)
Power control

EC MEC5105
Support

Power control

PAD, LED

EC MEC5105
Support

Power control

EC MEC5105
Support

EC MEC5105

CPU (6/14)

CodeC ALC3246

EC MEC5105
CPU (6/14)

CPU (6/14)

CPU (5/14)
[Type C]PD
Controller TI

CPU (8/14)

All

Date Issue DescriptionItem

2017/03/30

2017/04/05

2017/04/05 EE Change net name from SIO_SLP_SUS# to PCH_PRIM_EN

2017/04/05 Change RE71 to 10 ohm 0.1(X00)

2017/04/05 Add QZ4 and RZ370 0.1(X00)

2017/04/05

2017/04/14 Reserve DZ9 0.1(X00)

Owner

EE

EE

EE

Port map change25 All EE

Intel PDG for DSx and NonDSx26

PCH_PRIM_EN net name change27

Microchip suggest28

+5V_RUN discharge circuit for
S3 no power issue

Add bracket30 38 EE

EC request to reseve OR gate for
WLAN power EN

NGFF3 (SSD 4 Lane) add PCIE port 9 and port 10
LOM change to PCIE port 4

Add RC443, RC444 for SUSACK#, ME_SUS_PWR_ACK
Add BOM structure DS3@ for RE349 and RE536

Add bracket CLIP1 CLIP_14P0X2P6
Add bracket CLIP2 CLIP_7P7X4P2

EE EC request to reseve ESPI_RESET# for JESPI2017/04/14 Reserve RE560 0.1(X00)

EE Schmatic align2017/04/14 Add GPU_SMCLK/GPU_SMDAT PU to RPE12 0.1(X00)

EE WIGIG feature remove2017/04/14 Add back RC50 and depop 0.1(X00)

EE Realtek request2017/04/14 CA54 change back to 10pf and depop 0.1(X00)

EE RTC power Gate circuit rev.2 (0411)2017/04/14 Delete RE540, RE542, RE544, RE545, QE14, QE16

Change RE543 to 1M ohm and RE546 to 10K ohm
Add DE2, CE65,
Reserve CE66 for VCCDSW_EN

EE RTC Power Gate Circuit option (0411)2017/04/14 RC445 change to connect to VCCDSW_EN and pop 0.1(X00)

EE OTG support2017/04/14 Pop RT74, Depop RC337 0.1(X00)

2017/04/19

EE40 13

EE

KBL-R CRB schematic 0.1(X00)Add BOM structure for RC436 U42@2017/04/19

GPIO126->GPU_PWR_LEVEL
Add RTCRST_ON_R net neme for QE17.2
Add SIO_SLP_SUS#_R net name and PU RE561
SYS_LED_MASK#->LED_MASK#
RC27.2->NC for CLKRUN#
HDD_DET#->SATAGP0
Add RV326 and depop RC282/RE547 for 3.3V_TS_EN/PCH_3.3V_TS_EN

Solution Description

Rev.

0.1(X00)

0.1(X00)

0.1(X00)

0.1(X00)

0.1(X00)

Request

USH & TPM

CPU (4/14)

943

A A

EE42 33

RF

TPM change to NPCT650x 0.1(X00)Change UZ12 to SA00008EL80 and related resistors2017/04/19

I2C interface for Active Steering Antenna
(SB14 only)

0.1(X00)Swap I2C3_SDA and I2C3_SCL2017/04/19

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document N umber Re v

Size Document N umber Re v

Size Document N umber Re v

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

Compal Electronics, Inc.

EE P.I.R (3/6)

EE P.I.R (3/6)

EE P.I.R (3/6)

LA-F312P

LA-F312P

LA-F312P

55 58Wednesday, December 20, 2017

55 58Wednesday, December 20, 2017

55 58Wednesday, December 20, 2017

1

2.0

2.0

2.0

5

4

Version Change List ( P. I. R. List )

3

2

1

LA-F312P

Item

D D

43 31

Page#

All44 GPIO map changeEE2017/04/20 GPIO013 net name change to DGPU_PWROK

1145 Schematic alignEE2017/04/20 INTRUDER# PU change to +RTC_CELL_PCH 0.1(X00)

46 31

47 11

C C

48 10

49 39

50 23

51 11

52 33

53 All

54 All

B B

55 All

56 30

57 33

58 32

959 GPIO map change

3960

A A

Title

EC MEC5105

All

CPU (6/14)

EC MEC5105

CPU (6/14)

CPU (5/14)

Power control

[Type C]PD
Controller TI

CPU (6/14)

USH & TPM

All

All

All

CodeC ALC3246

USH & TPM

EC MEC5105
Support

CPU (4/14)

Power control

TUSB546

[Type C]PD
Controller TI

Date Issue

2017/04/26 EE GPIO map change UPD2_ALERT#->UPD2_SMBINT# 0.1(X00)

2017/05/03 EE CLKREQ align Pop RC50 and RC190 0.1(X00)

2017/05/03 EE OTG support RC337 pop and change to 10K ohm 0.1(X00)

2017/06/02 EE

2017/06/02 EE

2017/06/02 EE Dell request to change cap to L-end P/N L-end P/N for all cap 0.2(X01)

2017/06/12 EE DFX request LA13 footprint change to TAI-T_HCB2012KF-121T50_2P 0.2(X01)

2017/06/12 RF RF request

2017/06/12 EE Board ID Change RE79 to 130Kohm (rev. X01) 0.2(X01)

2017/06/14 EE

2017/06/14 EE

2017/06/14 EE61 22

2017/06/14 EE62 23

Request
Owner

Description

EE2017/04/19 Dell request to add test point for

EC free pins

EC request to reseve OR gate for
WLAN power EN

PD ROM main source change 2017/06/02 EE UT6 change to SA000095R10 (GD) 0.2(X01)

Schematic align2017/06/02 EE Reserve RC551 for SUSACK#_R 0.2(X01)

Nuvoton request to change TPM_PIRQ# power rail
TPM change to NPCT750

Main source change2017/06/02 ESD

DFX request2017/06/02 EE

EC request to reseve OR gate for
WLAN power EN

Solution
Description

Add test point T141 for UE1.D1->GPIO051
Add test point T142 for UE1.L11->GPIO054
Add test point T264 for UE1.F13->VBUS3_ECOK
Add test point T143 for UE1.K7->GPIO011
Add test point T144 for UE1.M1->GPIO100
Add test point T262 for UE1.J6->DCIN3_EN
Add test point T147 for UE1.M4->GPIO013

UPD1_ALERT#->UPD1_SMBINT#
UPD1_SMBUS_ALERT#->UPD1_SMBINT#_R

Add QZ15 and RZ518
Add SLP_WLAN#_GATE net and RE552 to UE1.K10

TPM_PIRQ# power rail change to +3.3V_ALW_PCH
Change UZ12 to SA0000AQ200 and related resistors and CZ75 change to 10U

DI1,DI4,DT39,DT40,DI6 change to SC300001Y00
DI2,DI3,DI5 change to SCA00000T00
DA2 change to SCA00001A00
DT4 change to SCA00002Q00

DA8, DC1, DC2, DE2, DZ1, DZ2, DZ5-DZ8 footprint
change to AZ5125-01HPR7G_SOD523-2

Add CZ76/CZ77 (12pf/68pf) for +3.3V_RUN of UZ12
Add CZ78 (100pf) for +PWR_SRC of JUSH1

Add TypeC_CON_SEL1/TypeC_CON_SEL2 for UC1.W4/UC1.AB3
Reserve RC553-RC556 for connector selection

Rev.

0.1(X00)

0.1(X00)

0.2(X01)

0.2(X01)

0.2(X01)

0.2(X01)

0.2(X01)

0.2(X01)

Change QZ15 to SB00000T000 0.2(X01)

0.2(X01)Add RT410, RT411, RT412,RT413, RT414, RT415, RT416,CT213PS8743-B1 colay (SA00009E910)

0.2(X01)Add RT405, RT406, RT407, RT417, RT418PS8743-B1 colay (SA00009E910)

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document N umber Re v

Size Document N umber Re v

Size Document N umber Re v

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

Compal Electronics, Inc.

EE P.I.R (4/6)

EE P.I.R (4/6)

EE P.I.R (4/6)

LA-F312P

LA-F312P

LA-F312P

56 58Wednesday, December 20, 2017

56 58Wednesday, December 20, 2017

56 58Wednesday, December 20, 2017

1

2.0

2.0

2.0

5

4

Version Change List ( P. I. R. List )

3

2

1

LA-F312P

Item

D D

63 RF requestRF2017/06/15

Page#

30 Reserve CA78 for +5V_RUN_AUDIO 0.2(X01)

2364 PD change to rer.C UT5 change to SA0000AX700EE2017/06/21

665 0.2(X01)EE

2366 0.2(X01)EE

23 PS8743-B1 colay (SA00009E910)67 EE2017/08/02 Change RT405-RT407 to 10K 0.3(X02)

25 Schematic align68 EE2017/08/02 CT99-CT102 change to 0.01uf (SE00000YH00) 0.3(X02)

2269 TUSB546 new version IC

70

C C

26
31
13

3071

2172

73

32

74 9

75 32

1276 ME SW depopEE 1.0(A00)Depop RC222, SW1, RC221 change to 0 ohm short pad

B B

77 33

978

879

80 All

All81

82 22

83

20
29

84 24

A A

85 27

Title

CodeC ALC3246

[Type C]PD
Controller TI

CPU (1/14)

TUSB546

[Type C]PD
Controller TI

[Type C]USB3.0
CONN

TUSB546

eDP CONN
EC MEC5105
CPU (13/14)

CodeC ALC3246

HDMI Conn

EC MEC5105
Support

CPU (4/14)

EC MEC5105
Support

CPU (7/14)

USH & TPM

CPU (4/14)

CPU (3/14)

All

All

TUSB546

HDMI CONN
NGFF card

[Type C]PD Power

LAN Clarkvillie
& RJ45

Date Issue

2017/08/02

2017/08/04

2017/08/09 EE TPM_PIRQ# GPIO map change Add RC560 and reserve RC561 to TPM_PIRQ# 0.3(X02)

2017/09/15 EE Board ID 1.0(A00)Change RE79 to 4.2Kohm (rev. A00)

2017/09/15

2017/09/15 EE TPM change to MP version 1.0(A00)UZ12 change to SA0000AQ220

2017/09/15 EE GPIO map change 1.0(A00)Depop RC330, RC331

2017/09/15 EE Add solder mask 1.0(A00)Add UC6 -NPM

2017/09/15 EE 0 ohm change to short pad 1.0(A00)0 ohm change to short pad

2017/09/15 EE Only support DS3 (0 ohm change to short pad) 1.0(A00)Only support DS3 (0 ohm change to short pad)

2017/09/15 EE TUSB546 DPEQ set to default 1.0(A00)Depop RT303, RT306, Pop RT140, RT248

2017/09/18 EE DFX request 1.0(A00)Add LV3,LV6,LV9,LV12 RI27,RI28,RI29,RI30,RI47,RI48,RI49,RI50 -NPM

2017/10/03 EE X1 Code DT1,DT2,DT3 Change from SC1N4148180 to SC100005500 1.0(A00)

2017/10/03 EE LL1 Change from SHI0000IY00 to SHI0000K000 1.0(A00)Not completely replaced with DAZ40

Request
Owner

EE

EE

Description

Solution
Description

Rev.

0.2(X01)

Depop RC448, RC447AUX voltage level shift2017/06/21

Depop RT248, RT140 and pop RT303 and RT306TUSB546 DPEQ set to level 52017/06/21

UT9 change to SA00009R720 0.3(X02)

Reserve soft start solution

RF request to pop CA54 for 2MHz/4MHz noiseRF2017/08/04

HDMI EA for NonAR onlyEMI/EE2017/08/04

Reserve RV400, CV635 for QV8
Reserve CZ200, RZ380 for QZ1
Reserve CC340 for QC7
Reserve RE565 for QE15

Change CA54 to 82pf and pop

Change RV35 to 100ohn
Change LV37, LV38 to SHI0000M500
Change LV31-LV36 to SHI00003F0L

0.3(X02)

0.3(X02)

0.3(X02)

Board IDEE2017/08/07 Change RE79 to 62Kohm (rev. X02) 0.3(X02)

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document N umber Re v

Size Document N umber Re v

Size Document N umber Re v

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

Compal Electronics, Inc.

EE P.I.R (5/6)

EE P.I.R (5/6)

EE P.I.R (5/6)

LA-F312P

LA-F312P

LA-F312P

57 58Wednesday, December 20, 2017

57 58Wednesday, December 20, 2017

57 58Wednesday, December 20, 2017

1

2.0

2.0

2.0

5

4

Version Change List ( P. I. R. List )

3

2

1

LA-F312P

Item

D D

86 Main vendor EOLEE2017/11/10

Page#

23 CT74,CT83 Change from SE00000OU00 to SE00000QL10 1.0(A00)

2387 PD just change part number UT5 Change from SA0000AX700 to SA0000BIJ00EE2017/11/10

88 SW3 main source changeEE2017/12/08

38 SW3 main source change from SN111005800 to SN100005800 1.0(A00)

1789 WHEA BSOD Intel request CC202 change to 22uf for 4+2 CPU, but keep 1uf for 2+2 CPUEE2017/12/08

1790 WHEA BSOD Add CC341 22uf 0603,Depop CC202 22uf 0402EE2017/12/20

C C

Title

[Type C]PD
Controller TI

[Type C]PD
Controller TI

PAD, LED

CPU (12/14)

CPU (12/14)

MEC5105 support

Date Issue

2017/12/29 2.0(A01)

Request
Owner

EE Change RE79 to 2Kohm (rev. A01)Board ID91 32

Description

Solution
Description

Rev.

1.0(A00)

1.0(A00)

2.0(A01)

B B

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document N umber Re v

Size Document N umber Re v

Size Document N umber Re v

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

Compal Electronics, Inc.

EE P.I.R (6/6)

EE P.I.R (6/6)

EE P.I.R (6/6)

LA-F312P

LA-F312P

LA-F312P

58 58Friday, December 29, 2017

58 58Friday, December 29, 2017

58 58Friday, December 29, 2017

1

2.0

2.0

2.0