Compal LA-F292P Schematics Rev1.0

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smd.db-x7.ru

COMPAL CONFIDENTIAL

B

C

D

E

1 1

MODEL NAME :DDA30
PCB NO : LA-F292P

Port Map:
Kirkwood MLK Port Map as of 2017-04-13

BOM P/N :

X9 KBL UMA U42

Kabylake R

2017-11-14

2 2

@ : Nopop Component

EMI@ : EMI Component

@EMI@ : EMI Nopop Component

ESD@ : ESDComponent

@ESD@ : ESD Nopop Component

RF@ : RF Component

@RF@ : RF Nopop Component

3 3

CXDP@ : XDP Component

REV : 1.0(A00)

RTD3@ : Support RTD3 Component

NRTD3@ : No Support RTD3 Component
@RTD3@ : Reserve RTD3 Component

CONN@ : Connector Component

ESPI@ : ESPI interface Component

MB PCB

Part Number

DAB00025010

Description

PCB 26B LA-F292P REV1 MB UMA AR 2

Layout Dell logo

4 4

COPYRIGHT 2016

ALL RIGHT RESERVED
REV:X00
PWB:

A

PWR CKT:0810

LPC@ : External ESPI Component (SHD)

U42@ : KBL-R U42 Component
U22@ : KBL-R U22 Component

DS3@ : Support DS3 Component

NDS3@ : No Support DS3 Component

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOU T THE EXPRESS WRITTEN AUTHORIZATION O F DELL. IN ADDITION,
NEITHER THIS SHEET NOR TH E INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

B

PARTY WITHOUT DELL'S EXPRESS WRIT TEN CONSENT.

C

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Cover Sheet

Cover Sheet

Cover Sheet

LA-F292P

LA-F292P

LA-F292P

1 60Tuesday, November 14, 2017

1 60Tuesday, November 14, 2017

1 60Tuesday, November 14, 2017

E

1.0

1.0

1.0

A

smd.db-x7.ru

B

C

D

E

Kirkwood MLK AR Block Diagram

1 1

HDMI 1.4
CONN

Lef t r ear TypeC

Lef t fr ont TypeC

HDMI

P22

USB3.0/USB2.0

P28

USB3.0/USB2.0

P29

PD Solution
TPS65982D

2 2

Micro SIM

P33

EDP CONN

AR-DP

USB2.0/SMBusUSB2.0/SMBus

P25-2 6

SATA[1]/PC IE[8]

M.2,3042 Key B

WWAN/LTE/HCA

PCIex2 for 2nd SSD and
Optane

P30

P23-2 4

P33

USB2.0[4]

eDP Lane x 4

PCIE[1][2][3][ 4]

PCIE[6]

M.2,3030 Key A

WLAN+BT/WIGIG

SW2_DP1

PCIE[5]

P33

USB2.0[7]

DDI[1]

DDI[2]

INTEL

KABYLAKE_U/R MCP

Memory BUS (LPDDR3)

4xSDP/DDP/QDP

4x32b,1866MH z

USB

USB2.0[8]

I2C[0,2]

USB2.0[9]

SLGC55544BVTR
USB POWER SHARE

USB/PCIE MUX

HD3SS3212

3 3

Smart Card

TDA8034HN

RFID/NFC

NB-2023-S

4 4

A

Fingerprint
CONN

P32

USB3.0[2]PCIE[7]

SPI

SPI

USH TPM1.2
BCM58102

USB2.0[10]

USH board

GPIO expander
MCP23008

B

PAGE 6~19

HD Audio I/F

SPI

SATA[2]/PCIE [12][11][10 ][9]

W25Q128JVSIQ

ESPI

P38

SMSC KBC

I2C

P37

MEC5105

P36

128M 4K sector

W25Q128JVSIQ

128M 4K sector

TPM1.2
NPCT650JB2YX &
NPCT750JAAYX

KB/TP CONN

FAN CONN

C

P8

P8

reserve

P38

P42

P37

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER P ROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

HDA Codec
ALC3253

Memory Down

LPDDR3 x 2

P20,P2 1

USB2.0[5]

USB2.0[9]_PS

P40

USB3.0[1]

USB2.0[2]

USB3.0[3]

USB2.0[6]

USB3.0[4]

Wacom G12T Touchscreen/Pen

10 pin conn(default).

I2C

MEC5105

INT.Speaker

Universal Jack

P35

Dig. MIC

P30

0 ohm

0 ohm

P35

P35

P30

Trough eDP Cable

M.2 2280

SSD Conn

P39

D

Trough eDP Cable

UF Camera

P30

USB3.0 Conn
PS(Ext Port 1)

USB3.0 Conn
(Ext Port 2)

Card reader
RTS5330

2nd Accelerometer
(MB)

Magnetometer/

E-Compass

P40

P41

P31

P45

SD4.0

P31

Place on Sensor/B

Accelerometer &
Gyroscope

Place on RF module

SAR Sensor
Semtech SX9310

P45

LID SWITCH for

Laptop mode

LID SWITCH for
Tablet mode

USH CONN

CPU&PCH XDP Port

AUTOMATIC POWER
SWITCH(APS)

DC/DC Interface

Place on PWR/B

POWER ON/OFF

SW & LED

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size

Size

Size

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Block diagram

Block diagram

Block diagram

Document Number Re v

Document Number Re v

Document Number Re v

LA-F292P

LA-F292P

LA-F292P

E

P45

P45

P38

P14

P11

P44

P43

1.0

1.0

2 60Tuesday, November 14, 2017

2 60Tuesday, November 14, 2017

2 60Tuesday, November 14, 2017

1.0

5

smd.db-x7.ru

4

3

2

1

POWER STATES

Signal

State

S0 (Full ON) / M0

S3 (Suspend to RAM) / M3 LOW

D D

S4 (Suspend to DISK) / M3

S5 (SOFT OFF) / M3

S3 (Suspend to RAM) / M-OFF

S4 (Suspend to DISK) / M-OFF

S5 (SOFT OFF) / M-OFF

SLP
S3#

HIGH

LOW

LOW

LOW LOW LOW

LOW LOW LOW LOW

SLP

SLP

S5#

S4#

HIGH HIGH

HIGH HIGH

HIGH HIGH

LOW

LOW

LOW

HIGH HIGH

HIGH

ALWAYS

SLP

PLANE

A#

HIGH

ON

HIGH

ON ON ON

ON ON

HIGH

ON ON

ON ON

LOW

ON

ON

M
PLANE

ON

OFF OFF OFF

OFF OFF OFF OFF

OFF OFF OFF OFF

RUN

SUS

PLANE

PLANE

ON ON ON

OFF

OFF

OFF

OFF

OFFLOW

CLOCKS

OFF

OFF

OFF

USB3.0

USB3.0-1

USB3.0-2

USB3.0-3

USB3.0-4

USB3.0-5

USB3.0-6

PM TABLE

+5V_ALW
+3.3V_ALW
+3.3V_ALW_DSW

power

C C

State

S0

S3

S5 S4/AC

S5 S4/AC doesn't exist

plane

+3.3V_ALW_PCH +1.2V_MEM

+RTC_CELL

+1.8V_PRIM
+1.0V_PRIM
+1.0V_PRIM_CORE
+5V_ALW2
+3.3V_ALW2
+3.3V_RTC_LDO
+1.0V_MPHYGT

ON

ON

ON

+3.3V_CV2

+2.5V_MEM
+1.0V_VCCST

+5V_RUN

+3.3V_RUN

+0.6V_DDR_VTT

+1.8V_RUN

ON ON

ON

OFF

OFFOFF

+3.3V_M +3.3V_M

OFF

OFF

OFF

ON

ON

ON

(M-OFF)

+VCC_CORE

+VCC_GT

+1.0VS_VCCIO
+VCC_SA

ON

OFF

OFF

OFFOFF

SSIC

SSIC

PCIE

PCIE-1

PCIE-2

PCIE-3

PCIE-4

PCIE-5

PCIE-6

PCIE-7

PCIE-8

PCIE-9

PCIE-10

PCIE-11

PCIE-12

SATA

SATA-0

M.2 3042(SATA Cache or HCA)

SATA-1

SATA-1*

SATA-2

JUSB1-->Right

M.2 3042(LTE)

JUSB2-->Lef t

SD Card Reader

Alpine Ridge-DP

M.2 3030(WLAN)

M.2 3030(WIGIG)

M.2 2280 SSD
(PCIe4 or SATA)

USB PORT#DESTINATION

1

2

3

4

5

6

7

8

9

10

DESTINATION

TYPEC Front Side

JUSB2-->Lef t

TYPEC Rear Side

M2 3042(WWAN)

UF Camera

SD Card Reader

M.2 3030(BT)

Touch Screen

JUSB1-->Right

USH

B B

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EX PRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET N OR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY TH IRD
PARTY WITHOUT DELL'S EX PRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date : Sheet of

Date : Sheet of

Date : Sheet of

Compal Electronics, Inc.

Port assignment

Port assignment

Port assignment

LA-F292P

LA-F292P

LA-F292P

1

3 60Tuesday, November 14, 2017

3 60Tuesday, November 14, 2017

3 60Tuesday, November 14, 2017

1.0

1.0

1.0

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smd.db-x7.ru

Barrel
ADAPTER

D D

C C

B B

+3.3V_TBT_SX

CHARGER

ISL9538
(PU901)

BATTERY

ISL95808

(PU614)

IMVP_VR_ON

Type-C
ADAPTER

+5V_ALW

ISL95857

(PU602)

CSD97396

(PU612)

IMVP_VR_ON

+VCC_GT+VCC_SA

AP2112K

(UT14)

+PWR_SRC

CSD97396

(PU610)

IMVP_VR_ON

+VCC_CORE

AO6405

(QV1)

+BL_PWR_SRC

TPS65982D

(UT5,UT11)

+5V_ALW

+5V_TBT_VBUS

EN_IN VPWR

A A

4

SY8210A
(PU200)

SY8286R
(PU301)

SYV828C

(PU102)

SY8288B

(PU100)

+TBT_VBUS(5V~20V)

AP2204

(UT8,UT12)

SIO_SLP_S4#

0.6V_DDR_VTT_ON

SIO_SLP_SUS#

ALWON

ALWON

TYPE-C

+1.2V_MEM

+0.6V_DDR_VTT

+1.0V_PRIM

+5V_ALW

+5V_ALW2

+3.3V_RTC_LDO

+3.3V_ALW2

+3.3V_ALW

TPS22961

(UZ26)

3

SIO_SLP_SUS#
SIO_SLP_S4#

SLGC55544C

(UI3)

RT8097ALGE
(PU501)

G524B1T11U
(UV24)

+VCC_SFR_OC

TPS62134C

(PU401)

TPS62134D

(PU402)

EM5209

(UZ4)

EM5209

(@UZ5)

SY6288

(UI1)

AP7361C

(PU503)

EM5209

(UZ2)

EM5209

(UZ3)

EM5209

(UZ4)

EM5209

(@UZ5)

AOZ1336

(UT4)

TPS22967

(UZ18)

RUN_ ON

SIO_SLP_SUS#

RUN_ ON

AUD_PW R_EN

USB_POWERSHAR E_VBUS_E N

USB_PWR_EN1#

SIO_SLP_S4#

SIO_SLP_SUS#

AUX_EN_WOW L

@SIO_SLP_WLAN#

SIO_SLP_SUS#

@PCH_ALW _ON

RUN_ ON

3.3V_W WAN_EN

AUD_PW R_EN

ENVCC_PCH

TBT_PWR_EN

CV2_ON

+1.0VS_VCCIO

+1.0V_PRIM_CORE

+USB_EX2_PWR

+1.8V_MEM

+1.8V_PRIM

+3.3V_WLAN

+3.3V_ALW_PCH

+3.3V_RUN

+3.3V_WWAN

+3.3V_RUN_AUDIO

+LCDVDD

+3.3V_TBT

+3.3V_CV2

TPS22961

(UZ19)

TPS22961

(UZ21)

+5V_RUN

+5V_RUN_AUDIO

+5V_USB_CHG_PWR

for LPDDR3

2

CPU PWR

PCH PWR

Peripheral Device PWR

RUN_ ON

TYPE-C Power

+3.3V_TSP

+1.8V_RUN

+3.3V_CAM

USH/B

RUN_ ON
SIO_SLP_S0#

SIO_SLP_S4#

LP2301

(QV8)

AOZ1336

(UZ8)

LP2301A

(QZ1)

+1.0V_VCCSTG

+1.0V_VCCST

3.3V_TS_EN

3.3V_CAM_EN#

1

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EX PRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET N OR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY TH IRD
PARTY WITHOUT DELL'S EX PRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date : Sheet of

Date : Sheet of

Date : Sheet of

Compal Electronics, Inc.

Power rails

Power rails

Power rails

LA-F292P

LA-F292P

LA-F292P

1

4 60Tuesday, November 14, 2017

4 60Tuesday, November 14, 2017

4 60Tuesday, November 14, 2017

1.0

1.0

1.0

5

smd.db-x7.ru

SMBUS Address [0x9a]

AW44
BB43

PCH

D D

AW45 AW42

03

C C

KBC

MEC 5105

B B

SML1_SMBDATA

SML1_SMBCLK

D8E11

03

00
00

01
01

02
02

04
04

05
05

06

06

07
07

AY44
BB39

D7
E7

B3
E5

E10
C12

C3
B4

F7
B6

A12

N10

M4
M7

4

MEM_SMBCLK

MEM_SMBDATA

SML0_SMBCLK

SML0_SMBDATA

1K

1K

+3.3V_ALW_PCH

UPD2_SMBCLK
UPD2_SMBDAT

USH_SMBCLK
USH_SMBDAT

DAT_TP_SIO_I2C_CLK

DAT_TP_SIO_I2C_DATA

UPD1_SMBCLK
UPD1_SMBDAT

EXPANDER_GPU_SMCLK

EXPANDER_GPU_SMDATA

499

499

1K

1K

2.2K

2.2K

@2.2K

@2.2K

2.2K

2.2K

2.2K

+3.3V_ALW_PCH

+3.3V_ALW_PCH

+3.3V_ALW

DMN66D0LDW-7
DMN66D0LDW-7

+3.3V_ALW

+3.3V_ALW

DMN66D0LDW-7
DMN66D0LDW-7

2.2K

2.2K

+3.3V_ALW

3

DMN66D0LDW-7
DMN66D0LDW-7

M9
L9

2.2K

2.2K

USH

DDR_XDP_WAN_SMBCLK

DDR_XDP_WAN_SMBDATA

2.2K

2.2K

+3.3V_CV2

4.7K

2.2K

2.2K

2

+3.3V_TBT_FLASH

B5

PD
FW reflash

A5

DMN66D0LDW-7
DMN66D0LDW-7

USH/B

+3.3V_RUN

I2C_1_SCL
I2C_1_SDA

+3.3V_TBT_FLASH

B5
A5

Expander IO

1

2.2K

0
0
0
0

53
51

+3.3V_RUN

2.2K

2.2K

XDP

KEYSCAN_SMBDAT

+3.3V_RUN

SAR

ALS

TP

2.2K

PD

08 C5

C8

08

F6

09

E9

09

N2

A A

1010M3

PBAT_CHARGER_SMBCLK
PBAT__CHARGER_SMBDAT

2.2K

2.2K

+3.3V_ALW

100 ohm

100 ohm

7
6

Charger

BATTERY

CONN

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EX PRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET N OR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY TH IRD
PARTY WITHOUT DELL'S EX PRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date : Sheet of

Date : Sheet of

Date : Sheet of

Compal Electronics, Inc.

Port assignment

Port assignment

Port assignment

LA-F292P

LA-F292P

LA-F292P

1

5 60Tuesday, November 14, 2017

5 60Tuesday, November 14, 2017

5 60Tuesday, November 14, 2017

1.0

1.0

1.0

5

smd.db-x7.ru

4

3

2

1

+3.3V_RUN

CPU_DP1_CTRL_CLK

RC175 2.2K_0402_5%
RC178 2.2K_0402_5%

D D

RC176 2.2K_0402_5%
RC177 2.2K_0402_5%

C C

B B

12
12
12
12

UC1I

CSI-2

A36

CSI2_DN0

B36

CSI2_DP0

C38

CSI2_DN1

D38

CSI2_DP1

C36

CSI2_DN2

D36

CSI2_DP2

A38

CSI2_DN3

B38

CSI2_DP3

C31

CSI2_DN4

D31

CSI2_DP4

C33

CSI2_DN5

D33

CSI2_DP5

A31

CSI2_DN6

B31

CSI2_DP6

A33

CSI2_DN7

B33

CSI2_DP7

A29

CSI2_DN8

B29

CSI2_DP8

C28

CSI2_DN9

D28

CSI2_DP9

A27

CSI2_DN10

B27

CSI2_DP10

C27

CSI2_DN11

D27

CSI2_DP11

KBL-RU42_BGA1356

CPU_DP1_CTRL_DATA
CPU_DP2_CTRL_CLK
CPU_DP2_CTRL_DATA

CPU@

KBL-R U4+2

AR

+1.0VS_VCCIO

Rev_0.1

CSI2_CLKN0
CSI2_CLKP0
CSI2_CLKN1
CSI2_CLKP1
CSI2_CLKN2
CSI2_CLKP2
CSI2_CLKN3
CSI2_CLKP3

CSI2_COMP

GPP_D4/FLASHTRIG

EMMC

GPP_F13/EMMC_DATA0
GPP_F14/EMMC_DATA1
GPP_F15/EMMC_DATA2
GPP_F16/EMMC_DATA3
GPP_F17/EMMC_DATA4
GPP_F18/EMMC_DATA5
GPP_F19/EMMC_DATA6
GPP_F20/EMMC_DATA7

GPP_F21/EMMC_RCLK

GPP_F22/EMMC_CLK

GPP_F12/EMMC_CMD

EMMC_RCOMP

9 OF 20

CPU_DP1_N0<23>
CPU_DP1_P0<23>
CPU_DP1_N1<23>
CPU_DP1_P1<23>
CPU_DP1_N2<23>
CPU_DP1_P2<23>
CPU_DP1_N3<23>
CPU_DP1_P3<23>

CPU_DP2_N0<23>
CPU_DP2_P0<23>
CPU_DP2_N1<23>
CPU_DP2_P1<23>
CPU_DP2_N2<23>
CPU_DP2_P2<23>
CPU_DP2_N3<23>
CPU_DP2_P3<23>

CPU_DP1_CTRL_CLK<23>

CPU_DP1_CTRL_DATA<23>

TS_INT#<30>

RC2 24.9_0402_1%

COMPENSATION PU FOR eDP

CAD Note:Trace width=20 mils , Spacing=25mil,
Max length=100 mils.

C37
D37
C32
D32
C29
D29
B26
A26

CSI2_COMP

E13

TBT_FORCE_PWR

B7

MEM_CONFIG0

AP2

MEM_CONFIG1

AP1

MEM_CONFIG2

AP3

MEM_CONFIG3

AN3

MEM_CONFIG4

AN1
AN2
AM4
AM1

AM2
AM3
AP4

EMMC_RCOMP

AT1

CPU_DP1_CTRL_CLK
CPU_DP1_CTRL_DATA

CPU_DP2_CTRL_CLK
CPU_DP2_CTRL_DATA

1 2

TBT_FORCE_PWR <23>

EDP_COMP

12

RC3 100_0402_1%

1 2

RC4 200_0402_1%

UC1A

CPU@

E55

DDI1_TXN[0]

F55

DDI1_TXP[0]

E58

DDI1_TXN[1]

F58

DDI1_TXP[1]

F53

DDI1_TXN[2]

G53

DDI1_TXP[2]

F56

DDI1_TXN[3]

G56

DDI1_TXP[3]

C50

DDI2_TXN[0]

D50

DDI2_TXP[0]

C52

DDI2_TXN[1]

D52

DDI2_TXP[1]

A50

DDI2_TXN[2]

B50

DDI2_TXP[2]

D51

DDI2_TXN[3]

C51

DDI2_TXP[3]

L13

GPP_E18/DDPB_CTRLCLK

L12

GPP_E19/DDPB_CTRLDATA

N7

GPP_E20/DDPC_CTRLCLK

N8

GPP_E21/DDPC_CTRLDATA

N11

GPP_E22

N12

GPP_E23

E52

EDP_RCOMP

KBL-RU42_BGA1356

KBL-RU42_BGA1356.olb

KBL-R U4+2

DDI

DISPLAY SIDEBANDS

EDP

Rev_0.1

EDP_TXN[0]
EDP_TXP[0]
EDP_TXN[1]
EDP_TXP[1]
EDP_TXN[2]
EDP_TXP[2]
EDP_TXN[3]
EDP_TXP[3]

EDP_AUXN
EDP_AUXP

EDP_DISP_UTIL

DDI1_AUXN
DDI1_AUXP
DDI2_AUXN
DDI2_AUXP

RSVD

GPP_E13/DDPB_HPD0
GPP_E14/DDPC_HPD1
GPP_E15/DDPD_HPD2
GPP_E16/DDPE_HPD3

RSVD

GPP_E17/EDP_HPD

EDP_BKLTEN

EDP_BKLTCTL

EDP_VDDEN

1 OF 20

C47
C46
D46
C45
A45
B45
A47
B47

E45
F45

B52

CPU_DP1_AUXN

G50

CPU_DP1_AUXP

F50
E48
F48

CPU_DP3_AUXN

G46

CPU_DP3_AUXP

F46
L9

L7
L6
N9
L10

R12
R11
U13

EDP_TXN0 <30>
EDP_TXP0 <30>
EDP_TXN1 <30>
EDP_TXP1 <30>
EDP_TXN2 <30>
EDP_TXP2 <30>
EDP_TXN3 <30>
EDP_TXP3 <30>

EDP_AUXN <30>
EDP_AUXP <30>

CPU_DP1_AUXN <23>
CPU_DP1_AUXP <23>
CPU_DP2_AUXN <23>
CPU_DP2_AUXP <23>

@

T1

PAD~D

@

T2

PAD~D

CPU_DP1_HPD <23>
CPU_DP2_HPD <23>

EDP_HPD <30>

PANEL_BKLEN <30>
EDP_BIA_PWM <30>
ENVDD_PCH <30>

support QHD

EDP_HPD

1 2

RC1 100K_0402_5%

A A

+1.8V_PRIM

5

1 2

RC388 10K_0402_5%X76@

1 2

RC389 10K_0402_5%X76@

1 2

RC390 10K_0402_5%X76@

1 2

RC391 10K_0402_5%X76@

1 2

RC392 10K_0402_5%X76@

MEM_CONFIG0
MEM_CONFIG1
MEM_CONFIG2
MEM_CONFIG3
MEM_CONFIG4

1 2

RC393 10K_0402_5%X76@

1 2

RC394 10K_0402_5%X76@

1 2

RC395 10K_0402_5%X76@

1 2

RC396 10K_0402_5%X76@

1 2

RC397 10K_0402_5%X76@

4

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.

3

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CPU (1/14)

CPU (1/14)

CPU (1/14)

LA-F292P

LA-F292P

LA-F292P

6 60Tuesday, November 14, 2017

6 60Tuesday, November 14, 2017

6 60Tuesday, November 14, 2017

1

1.0

1.0

1.0

5

smd.db-x7.ru

4

3

2

1

For LPDDR3

DDR_A_DQS#[0..7]<20>

D D

LPDDR3, Ballout for side by side(Non-Interleave)

UC1B

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15

DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40

C C

B B

DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47

AN68
AN69

AN70
AN71
AR70
AR68
AU71
AU68
AR71
AR69
AU70
AU69

BB65
AW65
AW63

AY63

BA65

AY65

BA63

BB63

BA61
AW61

BB59
AW59

BB61

AY61

BA59

AY59

AY39
AW39

AY37
AW37

BB39

BA39

BA37

BB37

AY35
AW35

AY33
AW33

BB35

BA35

BA33

BB33

AY31
AW31

AY29
AW29

BB31

BA31

BA29

BB29

AY27
AW27

AY25
AW25

BB27

BA27

BA25

BB25

CPU@

AL71

DDR0_DQ[0]

AL68

DDR0_DQ[1]
DDR0_DQ[2]
DDR0_DQ[3]

AL70

DDR0_DQ[4]

AL69

DDR0_DQ[5]
DDR0_DQ[6]
DDR0_DQ[7]
DDR0_DQ[8]
DDR0_DQ[9]
DDR0_DQ[10]
DDR0_DQ[11]
DDR0_DQ[12]
DDR0_DQ[13]
DDR0_DQ[14]
DDR0_DQ[15]

Interleave / Non-Interleaved

DDR0_DQ[16]/DDR0_DQ[32]
DDR0_DQ[17]/DDR0_DQ[33]
DDR0_DQ[18]/DDR0_DQ[34]
DDR0_DQ[19]/DDR0_DQ[35]
DDR0_DQ[20]/DDR0_DQ[36]
DDR0_DQ[21]/DDR0_DQ[37]
DDR0_DQ[22]/DDR0_DQ[38]
DDR0_DQ[23]/DDR0_DQ[39]
DDR0_DQ[24]/DDR0_DQ[40]
DDR0_DQ[25]/DDR0_DQ[41]
DDR0_DQ[26]/DDR0_DQ[42]
DDR0_DQ[27]/DDR0_DQ[43]
DDR0_DQ[28]/DDR0_DQ[44]
DDR0_DQ[29]/DDR0_DQ[45]
DDR0_DQ[30]/DDR0_DQ[46]
DDR0_DQ[31]/DDR0_DQ[47]
DDR0_DQ[32]/DDR1_DQ[0]
DDR0_DQ[33]/DDR1_DQ[1]
DDR0_DQ[34]/DDR1_DQ[2]
DDR0_DQ[35]/DDR1_DQ[3]
DDR0_DQ[36]/DDR1_DQ[4]
DDR0_DQ[37]/DDR1_DQ[5]
DDR0_DQ[38]/DDR1_DQ[6]
DDR0_DQ[39]/DDR1_DQ[7]
DDR0_DQ[40]/DDR1_DQ[8]
DDR0_DQ[41]/DDR1_DQ[9]
DDR0_DQ[42]/DDR1_DQ[10]
DDR0_DQ[43]/DDR1_DQ[11]
DDR0_DQ[44]/DDR1_DQ[12]
DDR0_DQ[45]/DDR1_DQ[13]
DDR0_DQ[46]/DDR1_DQ[14]
DDR0_DQ[47]/DDR1_DQ[15]
DDR0_DQ[48]/DDR1_DQ[32]
DDR0_DQ[49]/DDR1_DQ[33]
DDR0_DQ[50]/DDR1_DQ[34]
DDR0_DQ[51]/DDR1_DQ[35]
DDR0_DQ[52]/DDR1_DQ[36]
DDR0_DQ[53]/DDR1_DQ[37]
DDR0_DQ[54]/DDR1_DQ[38]
DDR0_DQ[55]/DDR1_DQ[39]
DDR0_DQ[56]/DDR1_DQ[40]
DDR0_DQ[57]/DDR1_DQ[41]
DDR0_DQ[58]/DDR1_DQ[42]
DDR0_DQ[59]/DDR1_DQ[43]
DDR0_DQ[60]/DDR1_DQ[44]
DDR0_DQ[61]/DDR1_DQ[45]
DDR0_DQ[62]/DDR1_DQ[46]
DDR0_DQ[63]/DDR1_DQ[47]

KBL-RU42_BGA1356

KBL-R U4+2

DDR0_CKN[0]
DDR0_CKP[0]
DDR0_CKN[1]
DDR0_CKP[1]

DDR0_CKE[0]
DDR0_CKE[1]
DDR0_CKE[2]
DDR0_CKE[3]

DDR0_CS#[0]
DDR0_CS#[1]
DDR0_ODT[0]
DDR0_ODT[1]

DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5]
DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9]
DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6]
DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8]
DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]

DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]
DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12]
DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]

DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT#

DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]

DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]

DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]

DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]

DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]

DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]

DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]

DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]
DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]

DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1]
DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]

DDR CH - A

2 OF 20

DDR3L / LPDDR3 / DDR4

DDR0_DQSN[0]

DDR0_DQSP[0]

DDR0_DQSN[1]

DDR0_DQSP[1]

Interleave / Non-Interleaved

DDR0_DQSN[2]/DDR0_DQSN[4]
DDR0_DQSP[2]/DDR0_DQSP[4]
DDR0_DQSN[3]/DDR0_DQSN[5]
DDR0_DQSP[3]/DDR0_DQSP[5]
DDR0_DQSN[4]/DDR1_DQSN[0]
DDR0_DQSP[4]/DDR1_DQSP[0]
DDR0_DQSN[5]/DDR1_DQSN[1]
DDR0_DQSP[5]/DDR1_DQSP[1]
DDR0_DQSN[6]/DDR1_DQSN[4]
DDR0_DQSP[6]/DDR1_DQSP[4]
DDR0_DQSN[7]/DDR1_DQSN[5]
DDR0_DQSP[7]/DDR1_DQSP[5]

DDR0_ALERT#

DDR_VREF_CA
DDR0_VREF_DQ
DDR1_VREF_DQ

DDR_VTT_CNTL

Rev_0.1

DDR0_MA[3]
DDR0_MA[4]

DDR0_PAR

DDR_A_CLK#0

AU53

DDR_A_CLK0

AT53

DDR_A_CLK#1

AU55

DDR_A_CLK1

AT55

DDR_A_CKE0

BA56

DDR_A_CKE1

BB56

DDR_A_CKE2

AW56

DDR_A_CKE3

AY56

DDR_A_CS#0

AU45

DDR_A_CS#1

AU43

DDR_A_ODT0

AT45
AT43

DDR_A_CAA0

BA51

DDR_A_CAA1

BB54

DDR_A_CAA2

BA52

DDR_A_CAA3

AY52

DDR_A_CAA4

AW52

DDR_A_CAA5

AY55

DDR_A_CAA6

AW54

DDR_A_CAA7

BA54

DDR_A_CAA8

BA55

DDR_A_CAA9

AY54

DDR_A_CAB0

AU46

DDR_A_CAB1

AU48

DDR_A_CAB2 DDR_B_CAB1

AT46

DDR_A_CAB3

AU50

DDR_A_CAB4

AU52

DDR_A_CAB5

AY51

DDR_A_CAB6

AT48

DDR_A_CAB7

AT50

DDR_A_CAB8

BB50

DDR_A_CAB9

AY50
BA50

BB52

DDR_A_DQS#0

AM70

DDR_A_DQS0

AM69

DDR_A_DQS#1

AT69

DDR_A_DQS1

AT70

DDR_A_DQS#4

BA64

DDR_A_DQS4

AY64

DDR_A_DQS#5

AY60

DDR_A_DQS5

BA60

DDR_B_DQS#0

BA38

DDR_B_DQS0

AY38

DDR_B_DQS#1

AY34

DDR_B_DQS1

BA34

DDR_B_DQS#4

BA30

DDR_B_DQS4

AY30

DDR_B_DQS#5

AY26

DDR_B_DQS5

BA26
AW50

AT52
AY67

AY68
BA67

DDR_VTT_CTRL

AW67

DDR_A_D[0..63]<20>
DDR_A_DQS[0..7]<20>

DDR_A_CAA[0..9]<20>
DDR_A_CAB[0..9]<20> DDR_B_CAB[0..9]<21>

DDR_A_CLK#0 <20>
DDR_A_CLK0 <20>
DDR_A_CLK#1 <20>
DDR_A_CLK1 <20>

DDR_A_CKE0 <20>
DDR_A_CKE1 <20>
DDR_A_CKE2 <20>
DDR_A_CKE3 <20> DDR_B_CKE2 <21>

DDR_A_CS#0 <20>
DDR_A_CS#1 <20>
DDR_A_ODT0 <20>

DDR0_PAR,DDR0_ALERT# for DDR4

@

T260

PAD~D

@

T261

PAD~D

+DDR_VREF_CA
+DDR_VREF_A_DQ
+DDR_VREF_B_DQ

DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31

DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

UC1C

Interleave / Non-Interleaved

AF65

DDR1_DQ[0]/DDR0_DQ[16]

AF64

DDR1_DQ[1]/DDR0_DQ[17]

AK65

DDR1_DQ[2]/DDR0_DQ[18]

AK64

DDR1_DQ[3]/DDR0_DQ[19]

AF66

DDR1_DQ[4]/DDR0_DQ[20]

AF67

DDR1_DQ[5]/DDR0_DQ[21]

AK67

DDR1_DQ[6]/DDR0_DQ[22]

AK66

DDR1_DQ[7]/DDR0_DQ[23]

AF70

DDR1_DQ[8]/DDR0_DQ[24]

AF68

DDR1_DQ[9]/DDR0_DQ[25]

AH71

DDR1_DQ[10]/DDR0_DQ[26]

AH68

DDR1_DQ[11]/DDR0_DQ[27]

AF71

DDR1_DQ[12]/DDR0_DQ[28]

AF69

DDR1_DQ[13]/DDR0_DQ[29]

AH70

DDR1_DQ[14]/DDR0_DQ[30]

AH69

DDR1_DQ[15]/DDR0_DQ[31]

AT66

DDR1_DQ[16]/DDR0_DQ[48]

AU66

DDR1_DQ[17]/DDR0_DQ[49]

AP65

DDR1_DQ[18]/DDR0_DQ[50]

AN65

DDR1_DQ[19]/DDR0_DQ[51]

AN66

DDR1_DQ[20]/DDR0_DQ[52]

AP66

DDR1_DQ[21]/DDR0_DQ[53]

AT65

DDR1_DQ[22]/DDR0_DQ[54]

AU65

DDR1_DQ[23]/DDR0_DQ[55]

AT61

DDR1_DQ[24]/DDR0_DQ[56]

AU61

DDR1_DQ[25]/DDR0_DQ[57]

AP60

DDR1_DQ[26]/DDR0_DQ[58]

AN60

DDR1_DQ[27]/DDR0_DQ[59]

AN61

DDR1_DQ[28]/DDR0_DQ[60]

AP61

DDR1_DQ[29]/DDR0_DQ[61]

AT60

DDR1_DQ[30]/DDR0_DQ[62]

AU60

DDR1_DQ[31]/DDR0_DQ[63]

AU40

DDR1_DQ[32]/DDR1_DQ[16]

AT40

DDR1_DQ[33]/DDR1_DQ[17]

AT37

DDR1_DQ[34]/DDR1_DQ[18]

AU37

DDR1_DQ[35]/DDR1_DQ[19]

AR40

DDR1_DQ[36]/DDR1_DQ[20]

AP40

DDR1_DQ[37]/DDR1_DQ[21]

AP37

DDR1_DQ[38]/DDR1_DQ[22]

AR37

DDR1_DQ[39]/DDR1_DQ[23]

AT33

DDR1_DQ[40]/DDR1_DQ[24]

AU33

DDR1_DQ[41]/DDR1_DQ[25]

AU30

DDR1_DQ[42]/DDR1_DQ[26]

AT30

DDR1_DQ[43]/DDR1_DQ[27]

AR33

DDR1_DQ[44]/DDR1_DQ[28]

AP33

DDR1_DQ[45]/DDR1_DQ[29]

AR30

DDR1_DQ[46]/DDR1_DQ[30]

AP30

DDR1_DQ[47]/DDR1_DQ[31]

AU27

DDR1_DQ[48]

AT27

DDR1_DQ[49]

AT25

DDR1_DQ[50]

AU25

DDR1_DQ[51]

AP27

DDR1_DQ[52]

AN27

DDR1_DQ[53]

AN25

DDR1_DQ[54]

AP25

DDR1_DQ[55]

AT22

DDR1_DQ[56]

AU22

DDR1_DQ[57]

AU21

DDR1_DQ[58]

AT21

DDR1_DQ[59]

AN22

DDR1_DQ[60]

AP22

DDR1_DQ[61]

AP21

DDR1_DQ[62]

AN21

DDR1_DQ[63]

KBL-RU42_BGA1356

CPU@

KBL-R U4+2

DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5]
DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9]
DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6]
DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8]
DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]

DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]
DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12]
DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]

DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT#
DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]

DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]

DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]

DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]

DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]

DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]

DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]

DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]
DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]

DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1]
DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]

DDR CH - B

3 OF 20

DDR3L / LPDDR3 / DDR4

Interleave / Non-Interleaved

DDR1_DQSN[0]/DDR0_DQSN[2]

DDR1_DQSP[0]/DDR0_DQSP[2]

DDR1_DQSN[1]/DDR0_DQSN[3]

DDR1_DQSP[1]/DDR0_DQSP[3]

DDR1_DQSN[2]/DDR0_DQSN[6]

DDR1_DQSP[2]/DDR0_DQSP[6]

DDR1_DQSN[3]/DDR0_DQSN[7]

DDR1_DQSP[3]/DDR0_DQSP[7]

DDR1_DQSN[4]/DDR1_DQSN[2]

DDR1_DQSP[4]/DDR1_DQSP[2]

DDR1_DQSN[5]/DDR1_DQSN[3]

DDR1_DQSP[5]/DDR1_DQSP[3]

DRAM_RESET#
DDR_RCOMP[0]
DDR_RCOMP[1]
DDR_RCOMP[2]

Rev_0.1

DDR1_CKN[0]
DDR1_CKN[1]
DDR1_CKP[0]
DDR1_CKP[1]

DDR1_CKE[0]
DDR1_CKE[1]
DDR1_CKE[2]
DDR1_CKE[3]

DDR1_CS#[0]
DDR1_CS#[1]
DDR1_ODT[0]
DDR1_ODT[1]

DDR1_MA[3]
DDR1_MA[4]

DDR1_DQSN[6]
DDR1_DQSP[6]
DDR1_DQSN[7]
DDR1_DQSP[7]

DDR1_ALERT#

DDR1_PAR

AN45
AN46
AP45
AP46

AN56
AP55
AN55
AP53

BB42
AY42
BA42
AW42

AY48
AP50
BA48
BB48
AP48
AP52
AN50
AN48
AN53
AN52
BA43
AY43
AY44
AW44
BB44
AY47
BA44
AW46
AY46
BA46

BB46
BA47

AH66
AH65
AG69
AG70
AR66
AR65
AR61
AR60
AT38
AR38
AT32
AR32

AR25
AR27
AR22
AR21
AN43
AP43
AT13
AR18
AT18
AU18

DDR_B_DQS#[0..7]<21>

DDR_B_D[0..63]<21>
DDR_B_DQS[0..7]<21>

DDR_B_CAA[0..9]<21>

DDR_B_CLK#0
DDR_B_CLK#1
DDR_B_CLK0
DDR_B_CLK1

DDR_B_CKE0
DDR_B_CKE1
DDR_B_CKE2
DDR_B_CKE3

DDR_B_CS#0
DDR_B_CS#1
DDR_B_ODT0

DDR_B_CAA0
DDR_B_CAA1
DDR_B_CAA2
DDR_B_CAA3
DDR_B_CAA4
DDR_B_CAA5
DDR_B_CAA6
DDR_B_CAA7
DDR_B_CAA8
DDR_B_CAA9
DDR_B_CAB0

DDR_B_CAB2
DDR_B_CAB3
DDR_B_CAB4
DDR_B_CAB5
DDR_B_CAB6
DDR_B_CAB7
DDR_B_CAB8
DDR_B_CAB9

DDR_A_DQS#2
DDR_A_DQS2
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_DQS#7
DDR_A_DQS7
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_DQS#3
DDR_B_DQS3

DDR_B_DQS#6
DDR_B_DQS6
DDR_B_DQS#7
DDR_B_DQS7

SM_RCOMP0
SM_RCOMP1
SM_RCOMP2

DDR_B_CLK#0 <21>
DDR_B_CLK#1 <21>
DDR_B_CLK0 <21>
DDR_B_CLK1 <21>

DDR_B_CKE0 <21>
DDR_B_CKE1 <21>

DDR_B_CKE3 <21>
DDR_B_CS#0 <21>

DDR_B_CS#1 <21>
DDR_B_ODT0 <21>

@

T257

PAD~D

@

T258

PAD~D

@

T259

PAD~D

DDR1_PAR,DDR1_ALERT# for DDR4

VCC

+1.2V_MEM

5

4

Y

1 2

CD115@ 0.1U_0201_10V6K

1 2

RD83 100K_0402_5%

CHECK

0.6V_DDR_VTT_ON (control 0.6V power EN)

0.6V_DDR_VTT_ON <49>

+3.3V_RUN

UD5

1

DDR_VTT_CTRL

NC

2

A

3

GND

74AUP1G07SE-7 SOT353

A A

LPDDR3 COMPENSATION SIGNALS

SM_RCOMP0
SM_RCOMP1
SM_RCOMP2

CAD Note:
Trace width=12~15 mil, Spacing=20 mils
Max trace length= 500 mil

1 2

RC5 200_0402_1%

1 2

RC6 80.6_0402_1%

1 2

RC7 162_0402_1%

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.

5

4

3

2

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CPU (2/14)

CPU (2/14)

CPU (2/14)

LA-F292P

LA-F292P

LA-F292P

7 60Tuesday, November 14, 2017

7 60Tuesday, November 14, 2017

7 60Tuesday, November 14, 2017

1

1.0

1.0

1.0

5

smd.db-x7.ru

SPI_MOSI= SPI_IO0
SPI_MISO= SPI_IO1
PCH EDS R0.7 p.235~236

PCH_SPI_CLK
PCH_SPI_D1

12

PCH_SPI_D0
PCH_SPI_D2
PCH_SPI_D3
PCH_SPI_CS#0
PCH_SPI_CS#1
PCH_SPI_CS#2

1 2

+3.3V_1.8V_ESPI

RC10 1K_0402_1%CXDP@

1 2

RC11 1K_0402_1%CXDP@

PCH_SPI_CS#2<38>

PCH_CL_CLK1<33>
PCH_CL_DATA1<33>
PCH_CL_RST1#<33>

ESPI_ALERT#<36>

RC21 8.2K_0402_1%

PCH_SPI_DO_XDP<14>

D D

PCH_SPI_DO2_XDP<14>

AV2

AW3

AV3

AW2

AU4
AU3
AU2
AU1

M2
M3

J4
V1
V2

M1

G3
G2
G1

AW13

AY11

KBL-RU42_BGA1356

4

UC1E

CPU@

SPI - FLASH

SPI0_CLK
SPI0_MISO
SPI0_MOSI
SPI0_IO2
SPI0_IO3
SPI0_CS0#
SPI0_CS1#
SPI0_CS2#

SPI - TOUCH

GPP_D1/SPI1_CLK
GPP_D2/SPI1_MISO
GPP_D3/SPI1_MOSI
GPP_D21/SPI1_IO2
GPP_D22/SPI1_IO3
GPP_D0/SPI1_CS#

C LINK

CL_CLK
CL_DATA
CL_RST#

GPP_A0/RCIN#
GPP_A6/SERIRQ

KBL-R U4+2

LPC

3

SMBUS, SMLINK

GPP_C2/SMBALERT#

GPP_C5/SML0ALERT#

GPP_B23/SML1ALERT#/PCHHOT#

GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1
GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS#

GPP_A14/SUS_STAT#/ESPI_RESET#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

GPP_A10/CLKOUT_LPC1

Rev_0.1

GPP_C0/SMBCLK

GPP_C1/SMBDATA

GPP_C3/SML0CLK

GPP_C4/SML0DATA

GPP_C6/SML1CLK

GPP_C7/SML1DATA

GPP_A8/CLKRUN#

5 OF 20

R7
R8
R10

R9
W2
W1

W3
V3
AM7

AY13
BA13
BB13
AY12
BA12
BA11

AW9
AY9
AW11

MEM_SMBCLK
MEM_SMBDATA
PCH_SMB_ALERT#

SML0_SMBCLK
SML0_SMBDATA
GPP_C5

SML1_SMBCLK
SML1_SMBDATA
GPP_B23

ESPI_IO0_R
ESPI_IO1_R
ESPI_IO2_R
ESPI_IO3_R

ESPI_CLK
PCI_CLK_LPC1

CLKRUN#

SML1_SMBCLK <36>
SML1_SMBDATA <36>

1 2

RC366 15_0402_5%

1 2

RC367 15_0402_5%

1 2

RC368 15_0402_5%

1 2

RC369 15_0402_5%

ESPI_CS# <36,37>
ESPI_RESET# <36,37>

1 2

RC16EMI@ 15_0402_5%

1 2

RC22@ 22_0402_5%

2

MEM_SMBCLK

MEM_SMBDATA

ESPI_IO0 <36,37>
ESPI_IO1 <36,37>
ESPI_IO2 <36,37>
ESPI_IO3 <36,37>

ESPI_CLK_5105 <36,37>

+3.3V_RUN

6

CXDP@

5

DMN65D8LDW-7_SOT363-6

3 4

QC2B

CXDP@

DMN65D8LDW-7_SOT363-6

1

For Kirkwood

2

1

DDR_XDP_WAN_SMBCLK <14>

QC2A

DDR_XDP_WAN_SMBDAT <14>

DDR_XDP_WAN_SMBDAT
DDR_XDP_WAN_SMBCLK

MEM_SMBCLK
MEM_SMBDATA
SML1_SMBCLK
SML1_SMBDATA
SML0_SMBCLK
SML0_SMBDATA

1 2

RC318 2.2K_0402_5%

1 2

RC319 2.2K_0402_5%

1 2

RC12 1K_0402_5%

1 2

RC14 1K_0402_5%

1 2

RC15 1K_0402_5%

1 2

RC17 1K_0402_5%

1 2

RC347 499_0402_1%

1 2

RC348 499_0402_1%

+3.3V_RUN

+3.3V_ALW_PCH

C C

ESPI_CLK_5105

SOFTWARE TAA

PCH_SPI_D0_R1<38>

PCH_SPI_CLK_R1<38>

PCH_SPI_CLK_1_R PCH_SPI_CLK_0_R

33_0402_5%

@EMI@

12

RC28

33P_0402_50V8J

@EMI@

B B

12

CC7

33_0402_5%

@EMI@

12

RC29

33P_0402_50V8J

@EMI@

12

CC8

PCH_SPI_CS#0_R1
PCH_SPI_D2_R1 PCH_SPI_CLK_0_R

+3.3V_SPI

RC30 1K_0402_5%@
RC31 1K_0402_5%@

RC316 1K_0402_5%@

03/02:follow Intel MOW_2015WW06

@

1 2

RC37 0_0402_5%

1 2

RC39 33_0402_5%

PCH_SPI_D2_R1

12

PCH_SPI_D3_R1

12

PCH_SPI_D3_R1

12

PCH_SPI_CS#0_R2
PCH_SPI_D1_0_R
PCH_SPI_D2_0_R

PCH_SPI_D1_R1<38>

128Mb Flash ROM

UC5

1

/CS

2

IO1

3

IO2

4

GND

W25Q128FVSIQ_SO8

PCH_SPI_D0_R1
PCH_SPI_CLK_R1
PCH_SPI_D1_R1
PCH_SPI_D3_R1 PCH_SPI_D3_0_R

PCH_SPI_D3_R1
PCH_SPI_CLK_R1
PCH_SPI_D0_R1
PCH_SPI_D1_R1

VCC

CLK

@
@
@
@

IO3
IO0

128Mb Flash ROM

UC6

PCH_SPI_CS#1_R1

A A

PCH_SPI_D2_R1

1 2

RC42 0_0402_5%

@

1 2

RC43 33_0402_5%

@

PCH_SPI_CS#1_R2
PCH_SPI_D1_1_R
PCH_SPI_D2_1_R

@

1

/CS

2

IO1

3

IO2

4

GND

W25Q128FVSIQ_SO8

VCC

CLK

IO3
IO0

RPC1

PCH_SPI_D0_0_R

1 8

PCH_SPI_CLK_0_R

2 7

PCH_SPI_D1_0_R

3 6
4 5

33_0804_8P4R_5%

1 2

RC407 33_0402_5%

1 2

RC408 33_0402_5%

1 2

RC409 33_0402_5%

1 2

RC410 33_0402_5%

+3.3V_SPI

8

PCH_SPI_D3_0_R

7
6

PCH_SPI_D0_0_R

5

+3.3V_SPI

8

PCH_SPI_D3_1_R

7

PCH_SPI_CLK_1_R

6

PCH_SPI_D0_1_R

5

CC9

1 2

0.1U_0201_10V6K

CC10

@
1 2

0.1U_0201_10V6K

PCH_SPI_D3_1_R
PCH_SPI_CLK_1_R
PCH_SPI_D0_1_R
PCH_SPI_D1_1_R

+3.3V_SPI

@

@

@

@

@

@

SML0_SMBCLK

SML1_SMBCLK

MEM_SMBCLK

RC32 0_0402_5%

@

RC33 0_0402_5%
RC34 0_0402_5%
RC35 0_0402_5%
RC36 0_0402_5%
RC38 0_0402_5%
RC40 0_0402_5%

+3.3V_ALW_PCH

@

RC41 0_0402_5%

12
12
12
12
12
12
12

RF Request

CC316RF@ 82P_0402_50V8J

CC318@RF@ 33P_0402_50V8J

CC319@RF@ 33P_0402_50V8J

CC320@RF@ 33P_0402_50V8J

PCH_SPI_CS#1_R1

PCH_SPI_CS#1

PCH_SPI_D0_R1

PCH_SPI_D0

PCH_SPI_D1_R1

PCH_SPI_D1

PCH_SPI_CLK_R1

PCH_SPI_CLK

PCH_SPI_CS#0_R1

PCH_SPI_CS#0

PCH_SPI_D2_R1

PCH_SPI_D2

PCH_SPI_D3_R1

PCH_SPI_D3

12

1 2

1 2

1 2

1 2

Place close CPU side

ACES_50696-0200M-P01

22

GND_2

21

GND_1

20

20

19

19

18

18

17

17

16

16

15

15

14

14

13

13

12

12

11

11

10

10

9

9

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

JSPI1

CONN@

CLKRUN#

PCH_SMB_ALERT#

TLS C ONFIDENTIALITY

HIGH
LOW(DEFAULT)

WEAK INTERNAL 20K PD

GPP_C5

ESPI@

EC interface

HIGH
LOW(DEFAULT)

WEAK INTERNAL 20K PD

GPP_B23

RC317 150K_0402_5%

EXI BOOT STALL BYPASS

HIGH
LOW(DEFAULT)

WEAK INTERNAL PD

1 2

RC27 8.2K_0402_5%LPC@

+3.3V_ALW_PCH

1 2

RC23 2.2K_0402_5%

ENABLE
DISAB LE

+3.3V_ALW_PCH

1 2

RC25 4.7K_0402_5%

ESPI

LPC

+3.3V_ALW_PCH

1 2

ENABLED
DIABL ED

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.

5

4

3

2

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CPU (3/14)

CPU (3/14)

CPU (3/14)

LA-F292P

LA-F292P

LA-F292P

8 60Tuesday, November 14, 2017

8 60Tuesday, November 14, 2017

8 60Tuesday, November 14, 2017

1

1.0

1.0

1.0

5

smd.db-x7.ru

4

3

2

1

+3.3V_RUN

RC560

@

D D

RC282 100K_0402_5%@

RC237 10K_0402_5%

RC402 49.9K_0402_1%@
RC403 49.9K_0402_1%@

+3.3V_ALW_PCH

RC283 10K_0402_5%

RC330 49.9K_0402_1%@

RC331 49.9K_0402_1%@

C C

RC557 100K_0402_5%

@

RC558 100K_0402_5%

RTD3@

+3.3V_RUN

RC186 4.7K_0402_5%@

NO REBOOT STRAP

HIGH
LOW(DEFAULT)

Weak IPD

B B

+3.3V_ALW_PCH

RC184 8.2K_0402_5%@

PCH_3.3V_TS_EN

12

SIO_EXT_SCI#

12

LPSS_UART2_RXD

12

LPSS_UART2_TXD

12

SIO_EXT_WAKE#

12

LPSS_UART2_RXD

12

LPSS_UART2_TXD

12

PCH_TBT_PERST#

12

PCH_TBT_PERST#

12

NRB_BIT

12

No REBOOT

REBOOT ENABLE

GPP_B22

12

TPM_PIRQ#<38>

PCH_3.3V_TS_EN<30>

PCH_TBT_PERST#<23>

SBIOS_TX<37>

TS_I2C_SDA<30>
TS_I2C_SCL<30>

I2C1_SDA_TP<42>
I2C1_SCK_TP<42>

I2C2_SDA_ALS<45>

I2C2_SCL_ALS<45>

0_0201_5%

1 2

RC561

@

0_0201_5%

1 2

ONE_DIMM#
NRB_BIT

SIO_EXT_SCI#
GPP_B22
PCH_TBT_PERST#
TYPEC_CON_SEL1

TYPEC_CON_SEL2
LPSS_UART2_RXD

LPSS_UART2_TXD

I2C2_ALS_SDA
I2C2_ALS_CLK

+3.3V_RUN

12

RC513

2.2K_0402_5%

AN8
AP7
AP8
AR7

AM5
AN7
AP5
AN5

AB1
AB2

AB3
AD1

AD2
AD3
AD4

AH9

AH10
AH11

AH12

AF11
AF12

+3.3V_RUN

12

@

W4

U7
U6

U8
U9

RC512

2.2K_0402_5%

UC1F

CPU@

LPSS ISH

GPP_B15/GSPI0_CS#
GPP_B16/GSPI0_CLK
GPP_B17/GSPI0_MISO
GPP_B18/GSPI0_MOSI

GPP_B19/GSPI1_CS#
GPP_B20/GSPI1_CLK
GPP_B21/GSPI1_MISO
GPP_B22/GSPI1_MOSI

GPP_C8/UART0_RXD
GPP_C9/UART0_TXD
GPP_C10/UART0_RTS#
GPP_C11/UART0_CTS#

GPP_C20/UART2_RXD
GPP_C21/UART2_TXD
GPP_C22/UART2_RTS#
GPP_C23/UART2_CTS#

GPP_C16/I2C0_SDA
GPP_C17/I2C0_SCL

GPP_C18/I2C1_SDA
GPP_C19/I2C1_SCL

GPP_F4/I2C2_SDA
GPP_F5/I2C2_SCL

GPP_F6/I2C3_SDA
GPP_F7/I2C3_SCL

GPP_F8/I2C4_SDA
GPP_F9/I2C4_SCL

KBL-RU42_BGA1356

@

6

DMN63D8LDW-7_SOT363-6

5

3 4

QC4B

@

DMN63D8LDW-7_SOT363-6

BOOT BIOS Dest i nat i on(Bi t 10)

RC267@

RC268

ONE_DIMM#

LPC
SPI

1 2

12

TYPEC_CON_SEL1

TYPEC_CON_SEL2

HIGH
LOW(DEFAULT)

Internal 20k PD

+3.3V_RUN

10K_0402_5%

1 2

10K_0402_5%

12

A A

KBL-R U4+2

GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA

GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL

Sx_EXIT_HOLDOFF# / GPP_A12 / BM_BUSY# / ISH_GP6

+1.8V_RUN +1.8V_RUN

2

1

QC4A

@

RC555

@

10K_0402_5%

RC556

@

10K_0402_5%

Vendor

TYPEC_CON_SEL2TYPEC_CON_SEL1

JAE FOXCON
LOW

LOW

+1.8V_RUN

12

+3.3V_ALW_PCH+3.3V_ALW_PCH

1 2

12

LOW

HIGH

GPP_D5/ISH_I2C0_SDA
GPP_D6/ISH_I2C0_SCL

GPP_D7/ISH_I2C1_SDA
GPP_D8/ISH_I2C1_SCL

GPP_F10/I2C5_SDA/ISH_I2C2_SDA

GPP_F11/I2C5_SCL/ISH_I2C2_SCL

GPP_D16/ISH_UART0_CTS#/SML0BALERT#

12

RC510

2.2K_0402_5%

RC511

2.2K_0402_5%

@

10K_0402_5%

@

10K_0402_5%

HIGH HIGH

LOW

GPP_D15/ISH_UART0_RTS#

GPP_C12/UART1_RXD/ISH_UART1_RXD

GPP_C13/UART1_TXD/ISH_UART1_TXD
GPP_C14/UART1_RTS#/ISH_UART1_RTS#
GPP_C15/UART1_CTS#/ISH_UART1_CTS#

@

I2C2_ALS_SDA

@

I2C2_ALS_CLK

RC553

RC554

TBD TBD

HIGH

GPP_A18/ISH_GP0
GPP_A19/ISH_GP1
GPP_A20/ISH_GP2
GPP_A21/ISH_GP3
GPP_A22/ISH_GP4
GPP_A23/ISH_GP5

Rev_0.1

P2

GPP_D9

P3

GPP_D10

P4

GPP_D11

P1

GPP_D12

M4
N3

N1
N2

AD11
AD12

U1
U2
U3
U4

AC1
AC2
AC3
AB4

AY8
BA8
BB7
BA7
AY7
AW7
AP13

6 OF 20

MEM_INTERLEAVED

MEM_INTERLEAVED
AR_DET#

ISH_I2C0_SDA
ISH_I2C0_SCL

ISH_I2C1_SDA
ISH_I2C1_SCL

ISH_I2C2_SDA
ISH_I2C2_SCL

RTD3_CIO_PWR_EN

ISH_GP0_D
ISH_GP1_D
ISH_GP2_D
ISH_GP3_D

NB_MODE#_D
LID_CL#_NB_C
LID_CL#_TAB_C

ISH_GP0 for Main Accelerometer (LCD Sesnor Board)
ISH_GP1 for 2nd Accelerometer (MB)
ISH_GP2 for E-Compass (MB)
ISH_GP3 for ALS (LCD Sesnor Board)
ISH_GP4 for EC5105 (Tablet/NB mode)

NB_MODE#<36>

+3.3V_ALW_PCH +3.3V_ALW_PCH

RC371

@

10K_0402_5%

1 2

12

10K_0402_5%
RC372

ISH_I2C0_SDA <45>
ISH_I2C0_SCL <45>

ISH_I2C1_SDA <36,45>
ISH_I2C1_SCL <36,45>

ISH_I2C2_SDA <33>
ISH_I2C2_SCL <33>

9/24: Reserve for embedded locat i on ,r ef er I nt el P DG 0. 9

ISH_UART0_RXD <33>

ISH_UART0_TXD <33>
ISH_UART0_RTS# <33>

ISH_UART0_CTS# <33>

SIO_EXT_WAKE# <36>

RTD3_CIO_PWR_EN <23>
LCD_CBL_DET# <30>

ISH_GP0_D <45>
ISH_GP1_D <45>
ISH_GP2_D <45>
ISH_GP3_D <45>

@

RC504 0_0402_5%

@

RC505 0_0402_5%

Only for Kirkwood

WWAN

WLAN

12
12

LID_CL#_NB_D <45>
LID_CL#_TAB_D <45>

GPP_A GROUP is +1.8V

+1.8V_PRIM+3.3V_ALW

2

G

S

QC3

DIMM TYPE

Non-InterleaveLOW

12

RC506
10K_0402_5%

@

NB_MODE#_D

12

RC509
10K_0402_5%

12

RC507
100K_0402_5%

1 3

D

S TR BSS138W 1N SOT-323-3

1 2

RC508 0_0402_5%@

HIGH Interleave

RTD3_CIO_PWR_ENTPM_PIRQ#_R

ISH_I2C0_SDA
ISH_I2C0_SCL
ISH_I2C1_SDA
ISH_I2C1_SCL
LCD_CBL_DET#

ISH_I2C2_SDA
ISH_I2C2_SCL

ISH_GP0_D
ISH_GP1_D
ISH_GP2_D
ISH_GP3_D
NB_MODE#_D

AR_DET#

1 2

RC559 10K_0402_5%RTD3@

1 2

RC358 2.2K_0402_5%

1 2

RC359 2.2K_0402_5%

1 2

RC360 1K_0402_5%@

1 2

RC361 1K_0402_5%@

1 2

RC287 100K_0402_5%

1 2

RC363 1K_0402_5%@

1 2

RC362 1K_0402_5%@

1 2

RC365 10K_0402_5%@

1 2

RC364 10K_0402_5%@

1 2

RC501 10K_0402_5%@

1 2

RC502 10K_0402_5%@

1 2

RC349 10K_0402_5%@

RC400

@

10K_0402_5%

1 2

12

10K_0402_5%
RC401

+3.3V_ALW_PCH

+3.3V_RUN

+1.8V_RUN

AR_DET#

HIGH NON AR

LOW AR

DIMM Detect

HIGH
LOW

1 DIMM
2 DIMM

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.

5

4

3

2

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CPU (4/14)

CPU (4/14)

CPU (4/14)

LA-F292P

LA-F292P

LA-F292P

9 60Tuesday, November 14, 2017

9 60Tuesday, November 14, 2017

9 60Tuesday, November 14, 2017

1

1.0

1.0

1.0

5

smd.db-x7.ru

4

3

2

1

For AR, Kirkwood

UC1H

CPU@

PCIE / USB3 / SATA

D D

AR ----->

M.2 3030(WLAN) --->

C C

M.2 3042(SATA Cache
or/HCA)--->

M2 2280 SSD --->

B B

PCIE_PRX_DTX_N1<23>

PCIE_PRX_DTX_P1<23>
PCIE_PTX_DRX_N1<23>
PCIE_PTX_DRX_P1<23>

PCIE_PRX_DTX_N2<23>

PCIE_PRX_DTX_P2<23>
PCIE_PTX_DRX_N2<23>
PCIE_PTX_DRX_P2<23>

PCIE_PRX_DTX_N3<23>

PCIE_PRX_DTX_P3<23>
PCIE_PTX_DRX_N3<23>
PCIE_PTX_DRX_P3<23>

PCIE_PRX_DTX_N4<23>

PCIE_PRX_DTX_P4<23>
PCIE_PTX_DRX_N4<23>
PCIE_PTX_DRX_P4<23>

PCIE_PRX_DTX_N5<33>

PCIE_PRX_DTX_P5<33>
PCIE_PTX_DRX_N5<33>
PCIE_PTX_DRX_P5<33>

PCIE_PRX_DTX_N7<32>
PCIE_PRX_DTX_P7<32>
PCIE_PTX_DRX_N7<32>
PCIE_PTX_DRX_P7<32>

PCIE_PRX_DTX_N8<33>
PCIE_PRX_DTX_P8<33>
PCIE_PTX_DRX_N8<33>
PCIE_PTX_DRX_P8<33>

PCIE_PRX_DTX_N9<39>
PCIE_PRX_DTX_P9<39>
PCIE_PTX_DRX_N9<39>
PCIE_PTX_DRX_P9<39>

PCIE_PRX_DTX_N10<39>
PCIE_PRX_DTX_P10<39>
PCIE_PTX_DRX_N10<39>
PCIE_PTX_DRX_P10<39>

1 2

RC45 100_0402_1%

CPU_XDP_PRDY#<14>

CPU_XDP_PREQ#<14>

PCIE_PRX_DTX_N11<39>
PCIE_PRX_DTX_P11<39>
PCIE_PTX_DRX_N11<39>
PCIE_PTX_DRX_P11<39>
PCIE_PRX_DTX_N12<39>
PCIE_PRX_DTX_P12<39>
PCIE_PTX_DRX_N12<39>
PCIE_PTX_DRX_P12<39>

HDD_FALL_INT

PCIE_RCOMPN
PCIE_RCOMPP

H13

PCIE1_RXN/USB3_5_RXN

G13

PCIE1_RXP/USB3_5_RXP

B17

PCIE1_TXN/USB3_5_TXN

A17

PCIE1_TXP/USB3_5_TXP

G11

PCIE2_RXN/USB3_6_RXN

F11

PCIE2_RXP/USB3_6_RXP

D16

PCIE2_TXN/USB3_6_TXN

C16

PCIE2_TXP/USB3_6_TXP

H16

PCIE3_RXN

G16

PCIE3_RXP

D17

PCIE3_TXN

C17

PCIE3_TXP

G15

PCIE4_RXN

F15

PCIE4_RXP

B19

PCIE4_TXN

A19

PCIE4_TXP

F16

PCIE5_RXN

E16

PCIE5_RXP

C19

PCIE5_TXN

D19

PCIE5_TXP

G18

PCIE6_RXN

F18

PCIE6_RXP

D20

PCIE6_TXN

C20

PCIE6_TXP

F20

PCIE7_RXN/SATA0_RXN

E20

PCIE7_RXP/SATA0_RXP

B21

PCIE7_TXN/SATA0_TXN

A21

PCIE7_TXP/SATA0_TXP

G21

PCIE8_RXN/SATA1A_RXN

F21

PCIE8_RXP/SATA1A_RXP

D21

PCIE8_TXN/SATA1A_TXN

C21

PCIE8_TXP/SATA1A_TXP

E22

PCIE9_RXN

E23

PCIE9_RXP

B23

PCIE9_TXN

A23

PCIE9_TXP

F25

PCIE10_RXN

E25

PCIE10_RXP

D23

PCIE10_TXN

C23

PCIE10_TXP

F5

PCIE_RCOMPN

E5

PCIE_RCOMPP

D56

PROC_PRDY#

D61

PROC_PREQ#

BB11

GPP_A7/PIRQA#

E28

PCIE11_RXN/SATA1B_RXN

E27

PCIE11_RXP/SATA1B_RXP

D24

PCIE11_TXN/SATA1B_TXN

C24

PCIE11_TXP/SATA1B_TXP

E30

PCIE12_RXN/SATA2_RXN

F30

PCIE12_RXP/SATA2_RXP

A25

PCIE12_TXN/SATA2_TXN

B25

PCIE12_TXP/SATA2_TXP

KBL-RU42_BGA1356

KBL-R U4+2

SSIC / USB3

USB3_2_RXN/SSIC_RXN

USB3_2_RXP/SSIC_RXP
USB3_2_TXN/SSIC_TXN

USB3_2_TXP/SSIC_TXP

USB2

USB2_VBUSSENSE

GPP_E9/USB2_OC0#
GPP_E10/USB2_OC1#
GPP_E11/USB2_OC2#
GPP_E12/USB2_OC3#

GPP_E4/DEVSLP0
GPP_E5/DEVSLP1
GPP_E6/DEVSLP2

GPP_E0/SATAXPCIE0/SATAGP0
GPP_E1/SATAXPCIE1/SATAGP1
GPP_E2/SATAXPCIE2/SATAGP2

GPP_E8/SATALED#

Rev_0.1

USB3_1_RXN
USB3_1_RXP
USB3_1_TXN
USB3_1_TXP

USB3_3_RXN
USB3_3_RXP
USB3_3_TXN
USB3_3_TXP

USB3_4_RXN
USB3_4_RXP
USB3_4_TXN
USB3_4_TXP

USB2N_1
USB2P_1

USB2N_2
USB2P_2

USB2N_3
USB2P_3

USB2N_4
USB2P_4

USB2N_5
USB2P_5

USB2N_6
USB2P_6

USB2N_7
USB2P_7

USB2N_8
USB2P_8

USB2N_9
USB2P_9

USB2N_10
USB2P_10

USB2_COMP

USB2_ID

8 OF 20

H8
G8
C13
D13

J6
H6
B13
A13

J10
H10
B15
A15

E10
F10
C15
D15

AB9
AB10

AD6
AD7

AH3
AJ3

AD9
AD10

AJ1
AJ2

AF6
AF7

AH1
AH2

AF8
AF9

AG1
AG2

AH7
AH8

AB6
AG3
AG4

A9
C9
D9
B9

J1
J2
J3

H2
H3
G4

H1

USBCOMP
USB2_ID

USB2_VBUSSENSE

USB_OC2#
USB_OC3#

SATAGP0
M3042_PCIE#_SATA

m2280_PCIE_SATA#

SATALED#

Reserve

USB3_PRX_DTX_N1 <40>

USB3_PRX_DTX_P1 <40>
USB3_PTX_DRX_N1 <40>
USB3_PTX_DRX_P1 <40>

USB3_PRX_DTX_N2 <32>

USB3_PRX_DTX_P2 <32>
USB3_PTX_DRX_N2 <32>
USB3_PTX_DRX_P2 <32>

USB3_PRX_DTX_N3 <41>

USB3_PRX_DTX_P3 <41>
USB3_PTX_DRX_N3 <41>
USB3_PTX_DRX_P3 <41>

USB3_PRX_DTX_N4 <31>

USB3_PRX_DTX_P4 <31>
USB3_PTX_DRX_N4 <31>
USB3_PTX_DRX_P4 <31>

USB20_N1 <26>
USB20_P1 <26>

USB20_N2 <41>
USB20_P2 <41>

USB20_N3 <25>
USB20_P3 <25>

USB20_N4 <33>
USB20_P4 <33>

USB20_N5 <30>
USB20_P5 <30>

USB20_N6 <31>
USB20_P6 <31>

USB20_N7 <33>
USB20_P7 <33>

USB20_N8 <30>
USB20_P8 <30>

USB20_N9 <40>
USB20_P9 <40>

USB20_N10 <38>
USB20_P10 <38>

1 2

RC44 113_0402_1%

@

1 2

RC337 0_0402_5%

1 2

RC338 1K_0402_5%

USB_OC0# <40>
USB_OC1# <41>

M3042_DEVSLP <33>
M2_DEVSLP <39>

M3042_PCIE#_SATA <36>

m2280_PCIE_SATA# <39>

SATALED# <33,39,43>

-----> Ext USB3 Port 1 Charge

-----> M.2 3042(LTE)

-----> Ext USB3 Port 2

-----> Card Reader RTS5330

-----> Typce-C port1(AR,Front Side)

-----> Ext USB Port 2(LEFT)

-----> Typce-C port2(AR,Rear Side)

-----> M2 3042(WWAN)

-----> Camera

-----> Card Reader RTS5330

-----> M.2 3030(BT)

-----> LCD Touch

-----> Ext USB Port 1 Charge(RIGHT)

-----> USH

USB_OC1#
USB_OC3#
USB_OC0#
USB_OC2#

NEED DOUBLE CHECK

M2280_PCIE_SATA#

SATAGP0
SATALED#

M3042_PCIE#_SATA

M3042_PCIE#_SATA

+3.3V_ALW_PCH

10K_8P4R_5%

1

8

2

7

3

6

4 5

RPC3

RPC4

8
7
6

+3.3V_RUN

10K_8P4R_5%

1
2
3
4 5

1 2

RC551 10K_0402_5%

1 2

RC552@ 10K_0402_5%

1.8V?

HDD_FALL_INT

1 2

RC370@ 10K_0402_5%

12/17:INT1 is PP mode, depop RC370,double check.

+1.8V_RUN

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.

5

4

3

2

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CPU (5/14)

CPU (5/14)

CPU (5/14)

LA-F292P

LA-F292P

LA-F292P

10 60Tuesday, November 14, 2017

10 60Tuesday, November 14, 2017

10 60Tuesday, November 14, 2017

1

1.0

1.0

1.0

5

smd.db-x7.ru

4

3

2

1

UC1J

CPU@

CLK_PCIE_N0<33>

WWAN--->

WLAN--->

D D

WIGIG--->

M.2 SDD--->

LAN--->

AR --->

+3.3V_ALW_DSW

+1.0V_VCCST

C C

+3.3V_ALW_PCH

10/6 depop, prevent singal step.

H_CPUPWRGD VCCST_PWRGD

100P_0402_50V8J

12

B B

+3.3V_1.8V_PGPPA

CLK_PCIE_P0<33>

CLKREQ_PCIE#0<33>

CLK_PCIE_N1<33>
CLK_PCIE_P1<33>

CLKREQ_PCIE#1<33>

+3.3V_RUN

CLKREQ_PCIE#2_R<23>

CLK_PCIE_N3<39>
CLK_PCIE_P3<39>

CLKREQ_PCIE#3<39>

+3.3V_RUN

CLK_PCIE_N5<23>
CLK_PCIE_P5<23>

CLKREQ_PCIE#5<23>

LAN_WAKE#

RC323 10K_0402_5%

RC67 1K_0402_5%

RC71 1K_0402_5%

RC411 10K_0402_5%@

CC300ESD@

T9

12

PCH_PCIE_WAKE#

12

VCCST_PWRGD

12

ME_SUS_PWR_ACK

12

RC74 10K_0402_5%@

PCH_PWROK

12

100P_0402_50V8J

12

ESD Request:place near CPU side

@

PAD~D

VCCST_PWRGD<14,36,37>

ME_SUS_PWR_ACK<36>

1 2

RC550 1K_0402_5%@

CC301ESD@

SUSACK#<36>

+3.3V_RUN

+3.3V_RUN

+3.3V_RUN

+3.3V_RUN

SUSACK#_R

@RF@

RC373 0_0402_5%

RC189 10K_0402_5%

@RF@

RC374 0_0402_5%

RC47 10K_0402_5%

RC50 10K_0201_1%@

@RF@

RC59 10K_0402_5%

RC51 10K_0402_5%@

@RF@

RC190 10K_0402_5%

PCH_PLTRST#

RC77 1K_0402_5%@
RC78 60.4_0402_1%

RC444 0_0402_5%@

12

RC376 0_0402_5%

12

RC378 0_0402_5%

@

RC244 0_0402_5%

UC7

TC7SH08FU_SSOP5~D

PCH_RSMRST#_AND<14,42>

1 2
1 2

1 2
1 2

RC443 0_0402_5%@

PCH_PCIE_WAKE#<23,36,37>

12
12

12
12

CLKREQ_PCIE#2_R

12
12

12
12

1 2

+3.3V_ALW_PCH

5

1

P

B

2

A

G

3

SYS_PWROK<14,36>
PCH_PWROK<53>

PCH_DPWROK<36>

LAN_WAKE#<36>

3.3V_CAM_EN#<30>

RC311 10K_0402_5%

CLKREQ_PCIE#0_R

CLKREQ_PCIE#1_R

CLKREQ_PCIE#3_R

CLKREQ_PCIE#4_R

CLKREQ_PCIE#5_R

4

O

PCH_PLTRST#
SYS_RESET#

PCH_RSMRST#_AND

H_CPUPWRGDH_CPUPWRGD_R
VCCST_PWRGD_CPU

ME_SUS_PWR_ACK_R

RC215

POP

NO Support Deep sleep

DE-POP

PCH_DPWROK PCH_RSMRST#_AND

A A

1

2

RC215 0_0402_5%

NDS3@

100K_0402_1%

0.01UF_0402_25V7K

12

@

RC220

CC266

Support Deep sleep

1 2

12

RC75
10K_0402_5%

XDP_DBRESET#<14>

+3.3V_RUN

RC225@ 8.2K_0402_5%
RC227@ 8.2K_0402_5%

D42
C42

AR10

B42
A42
AT7

D41
C41
AT8

D40
C40

AT10

B40
A40

AU8

E40
E38

AU7

PCH_PLTRST#_EC <37>

PCH_PLTRST#_AND

12

RC65

@

100K_0402_5%

PCH_PWROK

SUSACK#_R

12

XDP_DBRESET#

12
12

CLKOUT_PCIE_N0
CLKOUT_PCIE_P0
GPP_B5/SRCCLKREQ0#

CLKOUT_PCIE_N1
CLKOUT_PCIE_P1
GPP_B6/SRCCLKREQ1#

CLKOUT_PCIE_N2
CLKOUT_PCIE_P2
GPP_B7/SRCCLKREQ2#

CLKOUT_PCIE_N3
CLKOUT_PCIE_P3
GPP_B8/SRCCLKREQ3#

CLKOUT_PCIE_N4
CLKOUT_PCIE_P4
GPP_B9/SRCCLKREQ4#

CLKOUT_PCIE_N5
CLKOUT_PCIE_P5
GPP_B10/SRCCLKREQ5#

KBL-RU42_BGA1356

PCH_PLTRST#

PCH_PLTRST#_AND

PCH_PLTRST#_AND <23,30,33,38,39>

UC1K

CPU@

AN10

GPP_B13/PLTRST#

B5

SYS_RESET#

AY17

RSMRST#

A68

PROCPWRGD

B65

VCCST_PWRGD

B6

SYS_PWROK

BA20

PCH_PWROK

BB20

DSW_PWROK

AR13

GPP_A13/SUSWARN#/SUSPWRDNACK

AP11

GPP_A15/SUSACK#

BB15

WAKE#

AM15

GPD2/LAN_WAKE#

AW17

GPD11/LANPHYPC

AT15

GPD7/RSVD

KBL-RU42_BGA1356

1 2

@

RC290 0_0402_5%

+3.3V_RUN

1

ME_RESET#

2

if pop UC12, RC291 also need pop(74AHC1G09GW is OD output)

5

4

KBL-R U4+2

CLOCK SIGNALS

1 2

RC60 0_0402_5%@

1 2

@

RC325 0_0402_5%

VCCDSW_EN_GPIO<18>

VCCDSW_EN<36>

ALW_PWRGD_3V_5V<42,48>

SYSTEM POWER MANAGEMENT

5

P

B

4

O

A

G

UC12@

74AHC1G09GW_TSSOP5

3

@

1 2

0_0402_5%

KBL-R U4+2

SYS_RESET#_R

Rev_0.1

KBL-U / KBL-R U4+2

RSVD_E3/XTAL24_IN

RSVD_C7/XTAL24_OUT

XTAL24_IN/NC_2

XTAL24_OUT/NC_1

CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P

GPD8/SUSCLK

XCLK_BIASREF

RTCX1
RTCX2

SRTCRST#

RTCRST#

10 OF 20

RC445

GPP_B12/SLP_S0#

GPD10/SLP_S5#

GPD9/SLP_WLAN#

GPD3/PWRBTN#

GPD1/ACPRESENT

GPD0/BATLOW#

GPP_B11/EXT_PWR_GATE#

GPP_B2/VRALERT#

1 2

RC224 1K_0402_5%

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.

XTAL24_IN_U42_CPU XTAL24_IN_U42

E3

XTAL24_OUT_U42_CPU

C7

XTAL24_IN_U22_CPU

E37

XTAL24_OUT_U22_CPU

E35

CLK_ITPXDP_N

F43

CLK_ITPXDP_P

E43
BA17

SUSCLK

XCLK_BIASREF

E42

PCH_RTCX1

AM18

PCH_RTCX2

AM20
AN18

SRTCRST#

AM16

PCH_RTCRST#

PLTRST_TPM# <38>

RC297 0_0402_5%@
RC298 0_0402_5%@

PCH_RTCRST# <36>

CMOS1 must take care short & touch risk on layout placement

SIO_SLP_SUS#

DC1

NDS3@

2 1

RB751S-40 SOD-523

NDS3@

RB751S-40 SOD-523

DC2

VCCDSW_EN_Q

21

Close to CPU

1 2

RC417 33_0402_5%U42@

1 2

RC418 33_0402_5%U42@

1 2

RC419 0_0402_5%U22@

1 2

RC420 0_0402_5%U22@

1 2
1 2

SUSCLK <33,39>

1 2

RC52 2.7K_0402_1%

1 2

RC324 59_0402_1%@

546765_546765_2014WW48_Skylake_MOW_Rev_1_0

1 2

RC56 20K_0402_5%

1 2

CC24 1U_0402_6.3V6K

1 2

RC57 20K_0402_5%

1 2

CC25 1U_0402_6.3V6K

1

1

2

SHORT PADS~D

@

CMOS1

@DS3@

RC441

1 2

0_0402_5%

RC442

NDS3@

1 2

0_0402_5%

RC439RC440

Support DS3

No Support DS3

Rev_0.1

GPD4/SLP_S3#
GPD5/SLP_S4#

SLP_SUS#
SLP_LAN#

GPD6/SLP_A#

GPP_A11/PME#

INTRUDER#

11 OF 20

+3.3V_RUN

1 2

3

AT11
AP15
BA16
AY16

AN15
AW15
BB17
AN16

BA15
AY15
AU13

AU11
AP16

AM10
AM11

RC291

10K_0402_5%

@

SYS_RESET#

SIO_SLP_S0#

PCH_BATLOW#

PME#
INTRUDER#

MPHYP_PWR_EN
VRALERT#

'V' mean POP, 'X' mean DE-POP

SIO_SLP_S0# <17,38,51>
SIO_SLP_S3# <23,36,37>
SIO_SLP_S4# <17,36,49,52>
SIO_SLP_S5# <36>

SIO_SLP_SUS# <36>
SIO_SLP_LAN# <36>
SIO_SLP_WLAN# <36,44>
SIO_SLP_A# <36>

SIO_PWRBTN# <14,36>

AC_PRESENT <36>

@

T115

PAD~D

connect to VCCMPHYGTAON_1P0 enable pin

XTAL24_OUT_U42
XTAL24_IN_U22
XTAL24_OUT_U22

CLK_ITPXDP_N_R <14>
CLK_ITPXDP_P_R <14>

+1.0V_CLK5

For Skylake, pop RC52,depop RC324
For Cannonlake, pop RC324,depop RC52

+RTC_CELL_PCH

2

PCH_PRIM_EN <17,44,50,51,52>

X

V

SUSCLK

SYS_RESET#

0.1U_0402_25V6

@ESD@

12

CC302

ESD Request:place near CPU side

2

XTAL24_IN_U22
XTAL24_OUT_U22

XTAL24_IN_U42
XTAL24_OUT_U42

VVVXXX

RC48 1K_0402_5%@

For UMA CONFIG

For KBL-R U22

1M_0402_1%

U22@

RC46

1 2

For Skylake,YC1 24 MHz (50 Ohm ESR)
For Cannonlake,YC1 38.4 MHz (30 Ohm ESR)

546765_546765_2014WW48_Skylake_MOW_Rev_1_0

3

4

1

2

For KBL-R U42

U42@

1M_0402_1%

RC415

1 2

For Skylake,YC3 24 MHz (50 Ohm ESR)

PCH_RTCX1
PCH_RTCX2

RC54
10M_0402_5%

1 2

1 2

@

RC296 0_0402_5%

8/21 can change to 10K for merge to RP

RC442RC441RC215RE536

VVXX

1 2

+3.3V_ALW_PCH

+3.3V_ALW

+3.3V_ALW

PCH_BATLOW#
AC_PRESENT

INTRUDER#

MPHYP_PWR_EN

VRALERT#

SIO_SLP_LAN#

POWER_SW#_MB<37,43>

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

3

4

1

2

12

ESR MAX=50k ohm

PCH_RTCX2_R

1 2

RC72 8.2K_0402_5%

1 2

RC243 10K_0402_5%

1 2

RC69 1M_0402_5%

1 2

RC387 100K_0201_5%@

1 2

RC73 10K_0402_5%

@

1 2

RC344 10K_0402_5%@

1 2

RC68 10K_0402_5%@

SIO_SLP_S3#
SIO_SLP_S5#

SIO_SLP_S4#
SIO_SLP_A#

PCH_RTCRST#

SYS_RESET#
SIO_SLP_S0#

CPU (6/14)

CPU (6/14)

CPU (6/14)

LA-F292P

LA-F292P

LA-F292P

1

CC21

U22@

1 2

15P_0402_50V8J

YC1

U22@

24MHZ_12PF_X3G024000DC1H

CC22

U22@

1 2

15P_0402_50V8J

U42@

CC338

1 2

12P_0402_50V8J

U42@

YC3

24MHZ_12PF_X3G024000DC1H

U42@

CC339

1 2

12P_0402_50V8J

CC23

1 2

15P_0402_50V8J

YC2

32.768KHZ_12.5PF_9H03200042

CC26

1 2

12P_0402_50V8J

+3.3V_ALW_DSW

+RTC_CELL_PCH

+3.3V_ALW_PCH

+3.3V_ALW

JAPS1

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

GND

20

GND

CVILU_CF4218FH0R0-05-NH

CONN@

11 60Tuesday, November 14, 2017

11 60Tuesday, November 14, 2017

11 60Tuesday, November 14, 2017

1.0

1.0

1.0

5

smd.db-x7.ru

4

3

2

+1.0V_VCCSTG

1

PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS

CPU_XDP_TCLK XDP_JTAGX

1 2

RC86 51_0402_5%@

Service Mode Switch:
Add a switch to ME_FWP signal to unlock the ME region and
allow the ent ir e r egi on of t he S PI f l ash to be updat ed us i ng FPT.

+3.3V_ALW_PCH

ME_FWP PCH has internal 20K PD.
(suspend power rail)

FLASH DESCRIPTOR SECURITY OVERRIDE

LOW = ENABLE (DEFAULT) -->Pin3 & Pin2 short
HIGH = DISABLE (ME can update) -->Pin1 & Pin2 short

CAM_MIC_CBL_DET# <30>

TBT_CIO_PLUG_EVENT# <23>

CONTACTLESS_DET# <38>

HOST_SD_WP# <31>

AUD_PWR_EN <35>
SPK_DET# <35>

0.1U_0402_25V6

@ESD@

12

CC304

2

CPU MISC

HDA_SDIN0

CC332

RF@

2.2P_0402_50V8C

KBL-R U4+2

KBL-R U4+2

1

2

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.

Rev_0.1

JTAG

PROC_TCK

PROC_TDI
PROC_TDO
PROC_TMS

PROC_TRST#

PCH_JTAG_TCK

PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS

PCH_TRST#

JTAGX

4 OF 20

GPP_A17/SD_PWR_EN#/ISH_GP7

HDA_SDOUT

CC333

RF@

2.2P_0402_50V8C

3

CPU_XDP_TCLK

B61

CPU_XDP_TDI

D60

CPU_XDP_TDO

A61

CPU_XDP_TMS

C60

CPU_XDP_TRST#

B59

PCH_JTAG_TCK

B56

PCH_JTAG_TDI

D59

PCH_JTAG_TDO

A56

PCH_JTAG_TMS

C59

CPU_XDP_TRST#

C61

XDP_JTAGX

A59

SDIO / SDXC

GPP_G0/SD_CMD
GPP_G1/SD_DATA0
GPP_G2/SD_DATA1
GPP_G3/SD_DATA2
GPP_G4/SD_DATA3

GPP_G5/SD_CD#
GPP_G6/SD_CLK

GPP_G7/SD_WP

GPP_A16/SD_1P8_SEL

SD_RCOMP

GPP_F23

1 2

RC87 1K_0402_5%@

Rev_0.1

7 OF 20

CPU_XDP_TCLK <14>
CPU_XDP_TDI <14>
CPU_XDP_TDO <14>
CPU_XDP_TMS <14>
CPU_XDP_TRST# <14>

PCH_JTAG_TCK <14>
PCH_JTAG_TDI <14>
PCH_JTAG_TDO <14>
PCH_JTAG_TMS <14>

+1.0V_VCCSTG

AB11
AB13

TBT_CIO_PLUG_EVENT#

AB12
W12

CONTACTLESS_DET#

W11

HOST_SD_WP#

W10

AUD_PWR_EN

W8

SPK_DET#

W7
BA9

BB9

SD_RCOMP

AB7

AF13

PCH_JTAG_TDO PCH_JTAG_TDI XDP_JTAGX

0.1U_0402_25V6

@ESD@

12

CC303

1 2

RC96 200_0402_1%

ESD request,Place near CPU side.

UC1D

CPU@

D63

CATERR#

A54

PECI

C65

PROCHOT#

C63

THERMTRIP#

A65

SKTOCC#

C55

BPM#[0]

D55

BPM#[1]

B54

BPM#[2]

C56

BPM#[3]

A6

GPP_E3/CPU_GP0

A7

GPP_E7/CPU_GP1

BA5

GPP_B3/CPU_GP2

AY5

GPP_B4/CPU_GP3

AT16

PROC_POPIRCOMP

AU16

PCH_OPIRCOMP

H66

OPCE_RCOMP

H65

OPC_RCOMP

KBL-RU42_BGA1356

UC1G

CPU@

AUDIO

HDA_SYNC/I2S0_SFRM
HDA_BLK/I2S0_SCLK
HDA_SDO/I2S0_TXD
HDA_SDI0/I2S0_RXD
HDA_SDI1/I2S1_RXD
HDA_RST#/I2S1_SCLK
GPP_D23/I2S_MCLK
I2S1_SFRM
I2S1_TXD

GPP_F1/I2S2_SFRM
GPP_F0/I2S2_SCLK
GPP_F2/I2S2_TXD
GPP_F3/I2S2_RXD

GPP_D19/DMIC_CLK0
GPP_D20/DMIC_DATA0

GPP_D17/DMIC_CLK1
GPP_D18/DMIC_DATA1

GPP_B14/SPKR

KBL-RU42_BGA1356

1

2

D D

+1.0V_VCCST

RC79 49.9_0402_1%@

RC80 1K_0402_5%

+1.0V_VCCSTG

RC83 1K_0402_5%

+3.3V_RUN

C C

B B

RC278 10K_0402_5%
RC272 10K_0402_5%@
RC279 10K_0402_5%
RC345 100K_0402_5%
RC292 10K_0402_5%

+3.3V_ALW_PCH

RC346 10K_0402_5%

RC288 10K_0402_5%

+3.3V_ALW_PCH +3.3V_ALW_PCH

RC183 8.2K_0402_5%@

12
12

12

RPC5

1

8

2

7

3

6

45

10K_8P4R_5%

12
12
12
12
12

12

12

CC334

RF@

82P_0402_50V8J

Close to RC94

12

H_CATERR#
H_THERMTRIP#

PROCHOT#

TOUCHPAD_INTR#
CAM_MIC_CBL_DET#

CONTACTLESS_DET#
TOUCH_SCREEN_PD#

AUD_PWR_EN
IR_CAM_DET#
HOST_SD_WP#

SIO_EXT_SMI#

KB_DET#

HDA_SYNC_R<35>

HDA_BIT_CLK_R<35>

HDA_SDOUT_R<35>

HDA_RST#_R<35>

CC27

RF@

47P_0402_50V8J

Close to RC93

HDA_SDOUT_R

1

2

SPKR

TOUCH_SCREEN_PD# PU changes to Module Side
(Not confirm yet?) 20160311

ME_FWP_SW

HDA_BIT_CLK_R

1

2

PECI_EC<36>

PROCHOT#<36,53,56>

H_THERMTRIP#<37>

1 2

RC92 33_0402_5%

1 2

RC93 33_0402_5%EMI@

1 2

RC94 33_0402_5%

1 2

RC223 1K_0402_5%

1 2

RC95 33_0402_5%

RC187 4.7K_0402_5%@

RC84 499_0402_1%

T10
T11

TOUCH_SCREEN_PD#<30>
TOUCHPAD_INTR#<36,42>

TOUCH_SCREEN_DET#<30>

12

IR_CAM_DET#<30>

PANEL_SIZE_DET<30>

HDA_SDOUT

12

1 2

XDP_OBS0_R<14>
XDP_OBS1_R<14>

@

PAD~D

@

PAD~D

12

RC88

49.9_0402_1%

KB_DET#<42>

SPKR<35>

RC89

HDA_SYNC
HDA_BIT_CLK
HDA_SDOUT

HDA_SDIN0<35>

HDA_RST#

TOP SWAP STRAP

A A

HIGH
LOW(DEFAULT)

Internal 20k PD

ENABLE
DISAB LE

5

Flash Descriptor Security override

HIGH
LOW(DEFAULT)

DISABLE

ENABLE

PROCHOT#_R
H_THERMTRIP#

XDP_OBS2_R
XDP_OBS3_R

SIO_EXT_SMI#
TOUCHPAD_INTR#

CPU_POPIRCOMP
PCH_POPIRCOMP

EDRAM_OPIO_RCOMP

EOPIO_RCOMP

12

12

RC90

49.9_0402_1%

49.9_0402_1%

IR_CAM_DET#
PANEL_SIZE_DET

KB_DET#

4

H_CATERR#

RC91

49.9_0402_1%

BA22

AY22
BB22
BA21

AY21

AW22

J5

AY20

AW20

AK7
AK6
AK9

AK10

H5
D7

D8
C8

AW5

RF Request. Place near CPU side (Intel MOW)

HDA_RST#

1

2

CC331

RF@

2.2P_0402_50V8C

1 2

RC81 51_0402_5%

1 2

RC82 100_0402_5%

1 2

RC130 51_0402_5%

@

RC328 0_0402_5%

RC222

@

1K_0402_5%

1 2

12

12

ME_FWP

PT,ST pop RC222 and SW1; MP pop RC221

ME_FWP<36>

0.1U_0402_25V6

@ESD@

CC305

ME_FWP_SW

12

@

RC2210_0402_5%

ME_FWP_SW

PANEL_SIZE_DET

H_THERMTRIP#

0.1U_0402_25V6

@ESD@

12

CC312

SW1

@

1
2
3

4

G

5

G

SSAL120100_3P

1 2

PROCHOT#

0.1U_0402_25V6

12

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CPU (7/14)

CPU (7/14)

CPU (7/14)

LA-F292P

LA-F292P

LA-F292P

1

@ESD@

CC310

+3.3V_ALW_PCH

RC50310K_0402_5%

12 60Tuesday, November 14, 2017

12 60Tuesday, November 14, 2017

12 60Tuesday, November 14, 2017

1.0

1.0

1.0

5

smd.db-x7.ru

D D

4

CFG[0..19]<14>

3

2

1

CFG[2][5][6][7] for SKYLAKE-H CPU CFG strap pin

12

RC113 10K_0402_1%@

CFG0

RC112 10K_0402_1%@
RC110 10K_0402_1%@

12
12

Stall reset sequence

HIGH(DEFAULT )
LOW

C C

RC109 1K_0402_5%

eDP enable

HIGH(DEFAULT )
LOW

B B

No stall(Normal Operat i on)
sta ll

12

CFG4

Disa bled
Enabled

+1.0V_PRIM_XDP

RC114 49.9_0402_1%
RC115 1.5K_0402_5%

ITP_PMODE<14>

@

T16

PAD~D

@

T17

PAD~D

1 2

U42@

RC436 0_0402_5%

CFG_RCOMP

12

ITP_PMODE

12

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15

CFG16
CFG17

CFG18
CFG19

UC1S

E68

CFG[0]

B67

CFG[1]

D65

CFG[2]

D67

CFG[3]

E70

CFG[4]

C68

CFG[5]

D68

CFG[6]

C67

CFG[7]

F71

CFG[8]

G69

CFG[9]

F70

CFG[10]

G68

CFG[11]

H70

CFG[12]

G71

CFG[13]

H69

CFG[14]

G70

CFG[15]

E63

CFG[16]

F63

CFG[17]

E66

CFG[18]

F66

CFG[19]

E60

CFG_RCOMP

E8

ITP_PMODE

AY2

RSVD_AY2

AY1

RSVD_AY1

D1

RSVD_D1

D3

RSVD_D3

K46

RSVD_K46

K45

RSVD_K45

AL25

RSVD_AL25

AL27

RSVD_AL27

C71

RSVD_C71

B70

RSVD_B70

F60

RSVD_F60

A52

RSVD_A52

BA70

RSVD_TP_BA70

BA68

RSVD_TP_BA68

J71

RSVD_J71

J68

RSVD_J68

F65

VSS_F65

G65

VSS_G65

F61

RSVD_F61

E61

RSVD_E61

KBL-RU42_BGA1356

CPU@

KBL-R U4+2

RESERVED SIGNALS-1

Rev_0.1

RSVD_TP_BB68
RSVD_TP_BB69

RSVD_TP_AK13
RSVD_TP_AK12

RSVD_BB2
RSVD_BA3

RSVD_D5
RSVD_D4
RSVD_B2
RSVD_C2

RSVD_B3
RSVD_A3

RSVD_AW1

RSVD_E1
RSVD_E2

RSVD_BA4
RSVD_BB4

RSVD_A4
RSVD_C4

RSVD_A69

RSVD_B69
RSVD_AY3
RSVD_D71

RSVD_C70
RSVD_C54

RSVD_D54

VSS_AY71

ZVM#

RSVD_TP
RSVD_TP

MSM#

PROC_SELECT#

19 OF 20

UC1T

BB68
BB69

AK13
AK12

BB2
BA3

AU5

TP5

AT5

TP6

D5
D4
B2
C2

B3
A3

AW1
E1

E2
BA4

BB4
A4

C4
BB5

TP4

A69
B69

AY3
D71

C70
C54

D54
AY4

TP1

BB3

TP2

AY71
AR56

AW71
AW70

AP56
C64

@

T12

PAD~D

@

T13

PAD~D

@

T14

PAD~D

@

T15

PAD~D

@

T128

PAD~D

@

T129

PAD~D

@

T130

PAD~D

@

T126

PAD~D

@

T127

PAD~D

@

T113

PAD~D

@

T114

PAD~D

1 2

RC120 100K_0402_5%@

For Skylake , RC120 depop
For Cannonlake, RC120 pop

546765_546765_2014WW48_Skylake_MOW_Rev_1_0

1/5 2014WW52 MOW reserve to support
Cannonlake-U PCH compatibility

close UC1.U11/U12 and <400mil

1 2

RC313 0_0402_5%@

+VCC_1P8+1.8V_PRIM

ZVM# for SKYLAKE-U 2+3e

MSM# for SKYLAKE-U 2+3e

+1.0V_VCCST

AW69
AW68

AU56

AW48

U12
U11

1

2

@

H11

CC222

1U_0402_6.3V6K

KBL-RU42_BGA1356

RSVD_AW69
RSVD_AW68
RSVD_AU56
RSVD_AW48

RSVD_U12
RSVD_U11
RSVD_H11

SPARE

Rev_0.1

RSVD_F6

RSVD_C11
RSVD_B11
RSVD_A11
RSVD_D12
RSVD_C12
RSVD_F52

20 OF 20

F6
C11

B11
A11
D12
C12
F52

KBL-R U4+2

CPU@

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.

5

4

3

2

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CPU (8/14)

CPU (8/14)

CPU (8/14)

LA-F292P

LA-F292P

LA-F292P

13 60Tuesday, November 14, 2017

13 60Tuesday, November 14, 2017

13 60Tuesday, November 14, 2017

1

1.0

1.0

1.0

+1.0V_PRIM

smd.db-x7.ru

@

1 2

RC216 0_0603_5%

+1.0V_PRIM_XDP +1.0V_PRIM_XDP

0.1U_0201_10V6K

0.1U_0201_10V6K

@

CC28

1

1

2

2

D D

Place near
JXDP1

VCCST_PWRGD<11,36,37>

PCH_RSMRST#_AND<11,42>

+1.0VS_VCCIO

C C

+1.0V_VCCST

+3.3V_RUN

+1.0V_PRIM_XDP

5

+1.0V_PRIM_XDP

@

CC29

XDP_OBS0_R<12>
XDP_OBS1_R<12>

RC123 1K_0402_5%@

RC124CXDP@

PCH_SPI_DO_XDP<8>

SYS_PWROK<11,36>

RC132 150_0402_5%

RC218 150_0402_5%@

RC219 10K_0402_5%@

RC137 3K_0402_5%

RC138 51_0402_5%@

RC239 0_0402_5%CXDP@
RC240 0_0402_5%CXDP@

RC5 need to close to JCPU1

1 2
1 2

1K_0402_5%

12

12

12

12

12

FIVR_EN
CFG0

RC217 0_0402_5%@
RC126 1K_0402_5%@
RC128 0_0402_5%CXDP@
RC129 0_0402_5%@

DDR_XDP_WAN_SMBDAT<8>

DDR_XDP_WAN_SMBCLK<8>

FIVR_EN_R

FIVR_EN

FIVR_EN

XDP_DBRESET#

CPU_XDP_PREQ#

CPU_XDP_PREQ#<10>

CPU_XDP_PRDY#<10>

1 2
1 2

1 2
1 2
1 2
1 2

PCH_JTAG_TCK<12>

CPU_XDP_TCLK<12>

CPU XDP

H_VCCST_PWRGD_XDP

SIO_PWRBTN#<11,36>

CPU_XDP_PREQ#
CPU_XDP_PRDY#

RESET_OUT#_R

CPU_XDP_TCLK

4

+1.0V_PRIM_XDP

CFG0
CFG1

CFG2
CFG3

XDP_OBS0
XDP_OBS1

CFG4
CFG5

CFG6
CFG7

FIVR_EN_R

+3.3V_ALW_PCH

1 2

PCH_SPI_DO_XDP
RESET_OUT#_R

0.1U_0402_25V6

12

CC33@

Place near JXDP1.47

XDP_PRSNT_PIN1

RC133

1.5K_0402_5%

CXDP@

CXDP@

1 2

RC121 0_0402_5%

1 2

RC122 0_0402_5%@
JXDP1

1

1
3
5
7
9
111112
131314
151516
171718
191920
212122
232324
252526
272728
292930
313132
333334
353536
373738
393940
414142
434344
454546
474748
494950
515152
535354
555556
575758
595960
61

GND

CONN@

GND

2
4
6
8

10

3
5
7
9

61
62

E-T_6601K-Y61N-04L

Place near JXDP1.48

CFG3

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60

63

XDP_DBRESET#

CFG17
CFG16

CFG8
CFG9

CFG10
CFG11

CFG19
CFG18

CFG12
CFG13

CFG14
CFG15

ITP_PMODE
XDP_DBRESET#

TDO_XDP
TRST#_XDP
TDI_XDP
XDP_TMS

0.1U_0402_25V6

12

3

CXDP@

CC32

Place near JXDP1.41

CFG[0..19]<13>

CLK_ITPXDP_P_R <11>
CLK_ITPXDP_N_R <11>

ITP_PMODE <13>
XDP_DBRESET# <11>

PCH_SPI_DO2_XDP <8>

+3.3V_ALW_DSW

SIO_PWRBTN#

1 2

12

2

+3.3V_RUN

CC30

12

0.1U_0201_10V6K

TDO_XDP

TDI_XDP

XDP_TMS

TRST#_XDP

RUNPWROK<36>

1.5K_0402_5%

@

RC241

0.1U_0402_25V6
CC269

@

UC8

14

VCC

2

1A

1

1OE

5

2A

4

2OE

9

3A

10

3OE

12

4A

13

4OE

74CBTLV3126BQ_DHVQFN14_2P5X3

CPU_XDP_TMS

RC131 51_0402_5%

CPU_XDP_TDI

RC134 51_0402_5%

CPU_XDP_TDO

RC135 100_0402_5%

CPU_XDP_TRST#

RC136@ 51_0402_5%

CPU_XDP_TCLK

RC139 51_0402_5%

XDP_TMS

1 2

@

RC228 0_0402_5%

TDI_XDP

1 2

@

RC229 0_0402_5%

TDO_XDP

1 2

@

RC230 0_0402_5%

GND PAD

1 2
1 2
1 2

1 2
1 2

1B

2B

3B

4B

GND

1

3

6

8

11

7
15

+1.0V_VCCSTG

PCH_JTAG_TMS <12>
PCH_JTAG_TDI <12>
PCH_JTAG_TDO <12>

CPU_XDP_TDO <12>

CPU_XDP_TDI <12>

CPU_XDP_TMS <12>

CPU_XDP_TRST# <12>

B B

TDO_XDP H_VCCST_PWRGD_XDP CPU_XDP_TRST#

0.1U_0402_25V6

@ESD@

12

CC306

ESD request,Place near JXDP1 side. ESD request,Place near UC8 side.

0.1U_0402_25V6

@ESD@

12

CC307

0.1U_0402_25V6

@ESD@

12

CC308

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.

5

4

3

2

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CPU (9/14)

CPU (9/14)

CPU (9/14)

LA-F292P

LA-F292P

LA-F292P

14 60Tuesday, November 14, 2017

14 60Tuesday, November 14, 2017

14 60Tuesday, November 14, 2017

1

1.0

1.0

1.0

5

smd.db-x7.ru

4

3

2

1

+VCC_CORE: 0.3~1.35V

D D

@

T122

PAD~D

@

T123

PAD~D

Remove (not support 2+3e)
2016 0303

C C

VCCOPC,VCCOPC_1P8,VCCEOPIO for SKYLAKE-U 2+3e

(w/ on package cache)

+VCC_CORE +VCC_CORE

+VCC_CORE_G0
+VCC_CORE_G1

UC1L

A30

VCC_A30

A34

VCC_A34

A39

VCC_A39

A44

VCC_A44

AK33

VCC_AK33

AK35

VCC_AK35

AK37

VCC_AK37

AK38

VCC_AK38

AK40

VCC_AK40

AL33

VCC_AL33

AL37

VCC_AL37

AL40

VCC_AL40

AM32

VCC_AM32

AM33

VCC_AM33

AM35

VCC_AM35

AM37

VCC_AM37

AM38

VCC_AM38

G30

VCC_G30

K32

RSVD

AK32

RSVD

AB62

VCCOPC_AB62

P62

VCCOPC_P62

V62

VCCOPC_V62

H63

VCC_OPC_1P8_H63

G61

VCC_OPC_1P8_G61

AC63

VCCOPC_SENSE

AE63

VSSOPC_SENSE

AE62

VCCEOPIO

AG62

VCCEOPIO

AL63

VCCEOPIO_SENSE

AJ62

VSSEOPIO_SENSE

KBL-RU42_BGA1356

CPU@

KBL-R U4+2

CPU POWER 1 OF 4

Rev_0.1

VCC_G32
VCC_G33
VCC_G35
VCC_G37
VCC_G38
VCC_G40
VCC_G42

VCC_J30
VCC_J33
VCC_J37
VCC_J40
VCC_K33
VCC_K35
VCC_K37
VCC_K38
VCC_K40
VCC_K42
VCC_K43

VCC_SENSE
VSS_SENSE

VIDALERT#

VIDSCK

VIDSOUT

VCCSTG_G20

12 OF 20

G32
G33
G35
G37
G38
G40
G42
J30
J33
J37
J40
K33
K35
K37
K38
K40
K42
K43

E32
E33

B63
A63
D64

G20

VCCSENSE
VSSSENSE

H_CPU_SVIDALRT#
VIDSCLK

VIDSOUT

+1.0V_VCCSTG_R

VIDSCLK <53>

+VCC_CORE

RC140

100_0402_1%

1 2

12

RC141

100_0402_1%

@

1 2

RC143 0_0603_5%

VCCSENSE <53>
VSSSENSE <53>

+1.0V_VCCSTG

VIDSCLK

RF Request

1 2

CC321@RF@ 33P_0402_50V8J

Place close CPU side

PSC(Primary side cap) : Place as close to the package as possible
BSC(Backside cap) : Place on secondary side, underneath the package

Component placement order:
Package edge > 0402 caps > 0805 caps > Bulk caps >Power source

B B

SVID ALERT

VIDALERT_N<53>

SVID DATA

A A

VIDSOUT<53>

+1.0V_VCCST

1 2

+1.0V_VCCST

1 2

56_0402_1%

RC152

100_0402_1%

RC157

CAD Note: Place the PU resistors close to CPU
RC204 close to CPU 300 - 1500mils

H_CPU_SVIDALRT#

12

RC153220_0402_5%

CAD Note: Place the PU resistors close to CPU
RC208close to CPU 300 - 1500mils

VIDSOUT

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.

5

4

3

2

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CPU (10/14)

CPU (10/14)

CPU (10/14)

LA-F292P

LA-F292P

LA-F292P

15 60Tuesday, November 14, 2017

15 60Tuesday, November 14, 2017

15 60Tuesday, November 14, 2017

1

1.0

1.0

1.0

5

smd.db-x7.ru

4

3

2

1

+VCCGT: 0.3~1.35V
+VCCGTX : 0.3~1.35V

KBL-R 4+2 and KBL-U 2+2&2+3e opt i on ( pl ac e on po wer page)

D D

+VCC_GT
+VCC_GT

C C

B B

VCC_GT_SENSE<53>
VSS_GT_SENSE<53>

RC437 0_0402_5%

@

1 2

+VCC_GT

+VCC_GT_+VCC_CORE

RC161

100_0402_1%

1 2

VCC_GT_SENSE
VSS_GT_SENSE

12

RC163

100_0402_1%

UC1M

KBL-U / KBL-R U4+2

A48

VCCGT/VCCCORE_5

A53

VCCGT/VCCCORE_6

J43

VCCGT/VCCCORE_44

J45

VCCGT/VCCCORE_45

J46

VCCGT/VCCCORE_46

J48

VCCGT/VCCCORE_47

J50

VCCGT/VCCCORE_48

J52

VCCGT/VCCCORE_49

K48

VCCGT/VCCCORE_57

K50

VCCGT/VCCCORE_58

K52

VCCGT/RSVD_6

A58

VCCGT

A62

VCCGT

A66

VCCGT

AA63

VCCGT

AA64

VCCGT

AA66

VCCGT

AA67

VCCGT

AA69

VCCGT

AA70

VCCGT

AA71

VCCGT

AC64

VCCGT

AC65

VCCGT

AC66

VCCGT

AC67

VCCGT

AC68

VCCGT

AC69

VCCGT

AC70

VCCGT

AC71

VCCGT

J53

VCCGT

J55

VCCGT

J56

VCCGT

J58

VCCGT

J60

VCCGT

K53

VCCGT

K55

VCCGT

K56

VCCGT

K58

VCCGT

K60

VCCGT

L62

VCCGT

L63

VCCGT

L64

VCCGT

L65

VCCGT

L66

VCCGT

L67

VCCGT

L68

VCCGT

L69

VCCGT

L70

VCCGT

L71

VCCGT

M62

VCCGT

N63

VCCGT

N64

VCCGT

N66

VCCGT

N67

VCCGT

N69

VCCGT

J70

VCCGT_SENSE

J69

VSSGT_SENSE

KBL-RU42_BGA1356

KBL-R U4+2

CPU@

CPU POWER 2 OF 4

KBL-U / KBL-R U4+2

VCCGTX_AK42/VCCCORE_12
VCCGTX_AK43/VCCCORE_13
VCCGTX_AK45/VCCCORE_14
VCCGTX_AK46/VCCCORE_15
VCCGTX_AK48/VCCCORE_16
VCCGTX_AK50/VCCCORE_17
VCCGTX_AL43/VCCCORE_21
VCCGTX_AL46/VCCCORE_22
VCCGTX_AL50/VCCCORE_23
VCCGTX_AM48/VCCCORE_29
VCCGTX_AM50/VCCCORE_30
VCCGTX_AM52/VCCCORE_31

VCCGTX_AK52/RSVD_5

Rev_0.1

VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT

VCCGTX_AK53
VCCGTX_AK55
VCCGTX_AK56
VCCGTX_AK58
VCCGTX_AK60
VCCGTX_AK70

VCCGTX_AL53
VCCGTX_AL56

VCCGTX_AL60
VCCGTX_AM53
VCCGTX_AM56
VCCGTX_AM58
VCCGTX_AU58
VCCGTX_AU63
VCCGTX_BB57
VCCGTX_BB66

VCCGTX_SENSE
VSSGTX_SENSE

13 OF 20

N70
N71
R63
R64
R65
R66
R67
R68
R69
R70
R71
T62
U65
U68
U71
W63
W64
W65
W66
W67
W68
W69
W70
W71
Y62

AK42
AK43
AK45
AK46
AK48
AK50
AL43
AL46
AL50
AM48
AM50
AM52
AK52

AK53
AK55
AK56
AK58
AK60
AK70
AL53
AL56
AL60
AM53
AM56
AM58
AU58
AU63
BB57
BB66

AK62
AL61

+VCC_GT

KBL-R 4+2 and KBL-U 2+2&2+3e opt i on ( pl ac e on po wer page)

+VCC_GT_+VCC_CORE

1 2

@

RC438 0_0402_5%

+VCC_GT
+VCC_GTUS

Reserve for soldering

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.

5

4

3

2

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CPU (11/14)

CPU (11/14)

CPU (11/14)

LA-F292P

LA-F292P

LA-F292P

16 60Tuesday, November 14, 2017

16 60Tuesday, November 14, 2017

16 60Tuesday, November 14, 2017

1

1.0

1.0

1.0

5

smd.db-x7.ru

4

3

2

1

+VCCPLL_OC source

+1.2V_MEM+1.2V_MEM_CPUCLK

@

1 2

RC231 0_0402_5%

D D

PSC

1

1

2

1

CC177

CC176

2

2

10U_0402_6.3V6M

10U_0402_6.3V6M

PSC

22U_0603_6.3V6M

CC294

1

1

2

2

+1.0V_VCCST

C C

B B

PSC

1

2

CC195

1U_0402_6.3V6K

1

CC178

2

10U_0402_6.3V6M

22U_0603_6.3V6M

CC295

1

2

+1.0V_VCCSTG

CC179

10U_0402_6.3V6M

22U_0603_6.3V6M

CC296

VDDQ: 8.45A

+1.2V_MEM_CPUCLK

+1.2V_MEM

PSC

1

CC297

2

10U_0402_6.3V6M

BSC

+VCC_SFR_OC

1

CC199

2

@

1U_0402_6.3V6K

1

1

2

CC322

2

CC288

RF@

2.2P_0402_50V8C

1U_0402_6.3V6K

RF Request

+1.0V_VCCST source

UC1N

AU23

VDDQ_AU23

AU28

VDDQ_AU28

AU35

VDDQ_AU35

AU42

VDDQ_AU42

BB23

VDDQ_BB23

BB32

VDDQ_BB32

BB41

VDDQ_BB41

BB47

VDDQ_BB47

BB51

VDDQ_BB51

AM40

VDDQC

A18

VCCST

A22

VCCSTG_A22

AL23

VCCPLL_OC

K20

VCCPLL_K20

K21

VCCPLL_K21

KBL-RU42_BGA1356

+1.0V_VCCST

1

2

CPU@

CC202

CPU POWER 3 OF 4

1U_0402_6.3V6K

KBL-R U4+2

PSC

VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO

VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA

VCCIO_SENSE

VSSIO_SENSE

VSSSA_SENSE
VCCSA_SENSE

14 OF 20

+VCC_SA

Rev_0.1

AK28
AK30
AL30
AL42
AM28
AM30
AM42

AK23
AK25
G23
G25
G27
G28
J22
J23
J27
K23
K25
K27
K28
K30

AM23
AM22

H21
H20

1 2

RC168 100_0402_1%

+1.0VS_VCCIO

VCCIO_SENSE
VSSIO_SENSE

+VCC_SA

+1.0VS_VCCIO

12

RC166

100_0402_1%

VSA_SEN- <53>
VSA_SEN+ <53>

1 2

12

RC165

100_0402_1%

VCCIO_SENSE <51>
VSSIO_SENSE <51>

RC167

100_0402_1%

12

CZ102 1U_0402_6.3V6K

VCCSTG_EN

PCH_PRIM_EN<11,44,50,51,52>
SIO_SLP_S4#<11,17,36,49,52>

@

RZ120 0_0402_5%

+1.0VS_VCCIO

1 2

+3.3V_ALW

1

B

2

A

+5V_ALW

1 2

5

0.1U_0402_10V7K

P

O

G

3

TC7SH08FU_SSOP5~D

PSC

1

2

CC252

1U_0402_6.3V6K

+1.0V_VCCSTG source

+1.2V_MEM

1 2

@

RZ119 0_0402_5%

UZ26

1

VIN1

2

VIN2

7

VIN thermal

3

VBIAS

4

ON

1

2

CC251

1U_0402_6.3V6K

TPS22961DNYR_WSON8

SIO_SLP_S0#

SIO_SLP_S3#

AND

CZ104

@

4

UZ34

@

1

1

2

2

CC250

CC253

1U_0402_6.3V6K

1U_0402_6.3V6K

+VCC_SFR_OC

6

VOUT

5

GND

S0

HIGH

HIGH

HIGH LOW LOW

S0Ix

LOW

HIGH

S3

LOW

LOW

1 2

CZ103 0.1U_0201_10V6K

+1.0V_VCCST+1.0V_VCCSTG

1 2

RZ151 0_0603_5%@

+1.0V_PRIM

12

CZ100 1U_0402_6.3V6K

SIO_SLP_S4#<11,17,36,49,52>

+1.0V_PRIM

+5V_ALW

A A

5

UZ21

1

VIN1

2

VIN2

7

VIN thermal

3

VBIAS

4

ON

TPS22961DNYR_WSON8

4.4mohm /6A
TR=12.5us@Vin=1.05V

VOUT

GND

6

5

4

+1.0V_VCCST_C

PJP1

12

PAD-OPEN1x1m

1 2

CZ101 0.1U_0201_10V6K

+1.0V_VCCST

SIO_SLP_S0#<11,38,51>

RUN_ON<36,37,44,51>

TC7SH08FU_SSOP5~D

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.

3

12

CZ105 1U_0402_6.3V6K

UZ35

RZ320 0_0402_5%@

+5V_ALW

+3.3V_ALW

5

1

B

2

A

3

1 2

P

O

G

4

UZ19

1

VIN1

2

VIN2

7

VIN thermal

3

VBIAS

4

ON

TPS22961DNYR_WSON8

4.4mohm /6A

VCCSTG_EN

TR=12.5us@Vin=1.05V

VOUT

GND

2

12

PJP2
PAD-OPEN1x1m

+1.0V_VCCSTG_C

6

5

DELL CONFIDENTIAL/PROPRIETARY

pop option with UZ19

1 2

CZ106 0.1U_0201_10V6K

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CPU (12/14)

CPU (12/14)

CPU (12/14)

LA-F292P

LA-F292P

LA-F292P

17 60Tuesday, November 14, 2017

17 60Tuesday, November 14, 2017

17 60Tuesday, November 14, 2017

1

1.0

1.0

1.0

5

smd.db-x7.ru

close UC1.AL1 and <120mil

+1.0V_PRIM

@

1 2

D D

C C

B B

RC299 0_0603_5%

@

1 2

RC300 0_0402_5%

@

1 2

RC301 0_0402_5%

@

1 2

RC302 0_0402_5%

@

1 2

RC303 0_0402_5%

+1.8V_PRIM

@

1 2

RC304 0_0402_5%

1 2

RC234 0_0402_5%@

+3.3V_ALW_PCH

@

1 2

RC235 0_0402_5%

1 2

RC211 0_0402_5%LPC@

+1.8V_PRIM

1 2

RC212 0_0402_5%ESPI@

@

1 2

RC305 0_0402_5%

@

1 2

RC306 0_0402_5%

@

1 2

RC307 0_0402_5%

@

1 2

RC308 0_0402_5%

+3.3V_ALW_PCH

1 2

LC1 FBMA-11-100505-750A10T 0402

1

CC215

2

RF@

1U_0402_6.3V6K

+1.0V_MPHYAON

+1.0V_CLK6

+1.0V_DTS

+1.0V_CLK1

+1.0V_CLK3

+1.8V_PGPPF

+3.3V_1.8V_PGPPG

+3.3V_1.8V_PGPPA

+3.3V_PGPPB+3.3V_ALW_PCH

+3.3V_PGPPC

+3.3V_PGPPD

+3.3V_PGPPE

8/28 schematic review

+3.3V_1.8V_ESPI

PJP4

1 2

PAD-OPEN1x1m

Must be +1.8V for eSPI I/F

+3.3V_VCCHDA

1

CC313

2

0.1U_0201_10V6K

close UC1.AJ19 and <400mil

A A

@

1 2

RC173 0_0402_5%

close UC1.N20 and <100mil

5

+1.0V_CLK4+1.0V_PRIM

1

CC226

2

@

47U_0805_6.3V6M

+1.0V_MPHYAON

1

2

CC203

1U_0402_6.3V6K

+1.0V_MPHYGT

close UC1.N15 and CC210 <400mil, CC211 <120mil

1

1

CC210

2

2

@

47U_0805_6.3V6M

+1.0V_SRAM

close UC1.AF20 and <400mil

1

CC217

2

@

1U_0402_6.3V6K

close UC1.K15, UC1.L15 and <100mil

@

1 2

RC169 0_0603_5%

1

2

CC281

@

0.1U_0201_10V6K

+1.0V_PRIM

1 2

LC2 FBMA-11-100505-750A10T 0402

1

1

CC225

CC335

2

2

@

RF@

1U_0402_6.3V6K

47U_0805_6.3V6M

close UC1.V15 and <100mil

@

1 2

RC170 0_0402_5%

close UC1.K19 and <100mil

1

2

CC204

1U_0402_6.3V6K

CC211

1U_0402_6.3V6K

+1.0V_APLLEBB

+1.0V_AMPHYPLL+1.0V_MPHYGT

1

CC219

2

@

47U_0805_6.3V6M

1

2

1

2

4

+1.0V_PRIM_CORE+1.0VO_DSW

1

CC205

2

@

1U_0402_6.3V6K

close UC1.AF18 and <400mil

+1.0V_AMPHYPLL

+1.0V_APLL

+1.0V_PRIM

+3.3V_ALW_DSW

+3.3V_VCCHDA

+3.3V_SPI

+3.3V_ALW_PCH

+1.0V_PRIM

close UC1.N18 and <120mil

CC218

1U_0402_6.3V6K

close UC1.K15 and <120mil

close UC1.K15 and <120mil

CC264

@

1U_0402_6.3V6K

+1.0V_APLL

1

CC314

2

+1.0V_CLK2+1.0V_PRIM

1

CC220

2

@

47U_0805_6.3V6M

4

close UC1.AB19 and <400milclose UC1.K17 and <120mil

1

2

0.1U_0201_10V6K

+1.0V_PRIM

CC206

@

1U_0402_6.3V6K

3

PCH PWR

UC1O

CPU@

AB19

VCCPRIM_1P0

AB20

VCCPRIM_1P0

P18

VCCPRIM_1P0

AF18

VCCPRIM_CORE

AF19

VCCPRIM_CORE

V20

VCCPRIM_CORE

V21

VCCPRIM_CORE

AL1

DCPDSW_1P0

K17

VCCMPHYAON_1P0

L1

VCCMPHYAON_1P0

N15

VCCMPHYGT_1P0_N15

N16

VCCMPHYGT_1P0_N16

N17

VCCMPHYGT_1P0_N17

P15

VCCMPHYGT_1P0_P15

P16

VCCMPHYGT_1P0_P16

K15

VCCAMPHYPLL_1P0

L15

VCCAMPHYPLL_1P0

V15

VCCAPLL_1P0

AB17

VCCPRIM_1P0_AB17

Y18

VCCPRIM_1P0_Y18

AD17

VCCDSW_3P3_AD17

AD18

VCCDSW_3P3_AD18

AJ17

VCCDSW_3P3_AJ17

AJ19

VCCHDA

AJ16

VCCSPI

AF20

VCCSRAM_1P0

AF21

VCCSRAM_1P0

T19

VCCSRAM_1P0

T20

VCCSRAM_1P0

AJ21

VCCPRIM_3P3_AJ21

AK20

VCCPRIM_1P0_AK20

N18

VCCAPLLEBB_1P0

KBL-RU42_BGA1356

+3.3V_ALW_DSW

22U_0603_6.3V6M

@

CC279

1

2

Support DS3

No Support DS3

'V' mean POP, 'X' mean DE-POP

KBL-R U4+2

CPU POWER 4 OF 4

1 2

RC440 0_0402_5%NDS3@

1 2

RC214 0_0402_5%@

1 2

@DS3@

RC439 0_0402_5%

22U_0603_6.3V6M

@

CC280

1

2

RC439

RC440RE536RC215RC441RC442

V V V

X

V V V

X X

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.

3

Rev_0.1

VCCPGPPA
VCCPGPPB
VCCPGPPC
VCCPGPPD
VCCPGPPE
VCCPGPPF
VCCPGPPG

VCCPRIM_3P3_V19

VCCPRIM_1P0_T1

VCCATS_1P8

VCCRTCPRIM_3P3

VCCRTC_AK19
VCCRTC_BB14

DCPRTC
VCCCLK1
VCCCLK2
VCCCLK3
VCCCLK4
VCCCLK5
VCCCLK6

GPP_B0/CORE_VID0
GPP_B1/CORE_VID1

15 OF 20

+3.3V_ALW_PCH

+3.3V_ALW_DSW_R

X

X

close UC1.AG15 and <120mil

Must be +1.8V

AK15
AG15
Y16
Y15
T16
AF16
AD15

V19
T1
AA1
AK17
AK19

BB14
BB10
A14
K19
L21
N20
L19
A10
AN11

AN13

+3.3V_1.8V_PGPPA

+3.3V_PGPPD
+1.8V_PGPPF

+3.3V_1.8V_PGPPG

+1.0V_DTS

+3.3V_ALW_PCH

close UC1.AK19 and <120mil

+DCPRTC

close UC1.BB10 and <120mil

+1.0V_CLK1
+1.0V_CLK2
+1.0V_CLK3
+1.0V_CLK4
+1.0V_CLK5

CORE_VID0 <51>
CORE_VID1 <51>

Take care!!! Note1 on Page 19

QC7

DS3@

LP2301ALT1G_SOT23-3

123

D

S

499K_0402_1%

12

G

49.9K_0402_1%

0.1U_0402_25V6K
RC433

DS3@

12

12

@

CC340

L2N7002WT1G_SC-70-3

X

13

D

QC6

DS3@

2

G

S

2

close UC1.Y16 a nd <400mil

+3.3V_PGPPB

+3.3V_PGPPC

1

CC265

2

@

1U_0402_6.3V6K

close UC1.AA1 and <400mil

1

2

CC214

0.1U_0201_10V6K

+1.0V_CLK6

1

2

+3.3V_ALW

RC432

DS3@

100K_0402_5%

RC431

DS3@

1 2

VCCDSW_EN_GPIO <11>

2

+3.3V_PGPPE

1

2

+RTC_CELL_PCH

1

2

1

CC207

2

@

1U_0402_6.3V6K

1

2

CC270

CC213

1U_0402_6.3V6K

0.1U_0201_10V6K

close UC1.A10 and <120mil

CC216

@

1U_0402_6.3V6K

@

RC171 0_0402_5%

close UC1.L19 and <100mil

DELL CONFIDENTIAL/PROPRIETARY

1

+1.0V_MPHYGT

+1.0V_SRAM

+1.0V_APLLEBB

close UC1.AD15 and <400mil

1

CC326

2

1U_0402_6.3V6K

close UC1.T16 a nd <400mil

CC208

@

1U_0402_6.3V6K

+3.3V_ALW_PCH

+1.8V_PRIM

1

CC209

1

2

@

2

1U_0402_6.3V6K

CC212

1U_0402_6.3V6K

@

1 2

RC309 0_0603_5%

@

1 2

RC310 0_0603_5%

+3.3V_1.8V_PGPPG

close UC1.V19 and <120mil

RF Request

+1.0V_APLL +3.3V_VCCHDA +1.0V_APLLEBB

1

2

CC325

1.2P_0402_50V8C

RF@

close UC1.AK17 and <120mil

1

2

CC224

1U_0402_6.3V6K

0.1U_0201_10V6K

1 2

1

1

2

2

CC323

CC324

RF@

RF@

1.2P_0402_50V8C

+3.3V_ALW_PCH+1.0V_CLK5+1.0V_PRIM

1

CC221

2

@

47U_0805_6.3V6M

1

CC223

2

+1.0V_MPHYGT source

+1.0V_MPHYGT+1.0V_PRIM

PJP3

1 2

PAD-OPEN1x3m

Pop PJP35 & Depop UZ20/RZ83/CZ84

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CPU (13/14)

CPU (13/14)

CPU (13/14)

LA-F292P

LA-F292P

LA-F292P

18 60Tuesday, November 14, 2017

18 60Tuesday, November 14, 2017

18 60Tuesday, November 14, 2017

1

1.2P_0402_50V8C

1.0

1.0

1.0

5

smd.db-x7.ru

4

3

2

1

CPU@

KBL-R U4+2

CPU@

KBL-R U4+2

UC1P

A5

VSS

A67

VSS

A70

VSS

AA2

VSS

AA4

D D

C C

B B

VSS

AA65

VSS

AA68

VSS

AB15

VSS

AB16

VSS

AB18

VSS

AB21

VSS

AB8

VSS

AD13

VSS

AD16

VSS

AD19

VSS

AD20

VSS

AD21

VSS

AD62

VSS

AD8

VSS

AE64

VSS

AE65

VSS

AE66

VSS

AE67

VSS

AE68

VSS

AE69

VSS

AF1

VSS

AF10

VSS

AF15

VSS

AF17

VSS

AF2

VSS

AF4

VSS

AF63

VSS

AG16

VSS

AG17

VSS

AG18

VSS

AG19

VSS

AG20

VSS

AG21

VSS

AG71

VSS

AH13

VSS

AH6

VSS

AH63

VSS

AH64

VSS

AH67

VSS

AJ15

VSS

AJ18

VSS

AJ20

VSS

AJ4

VSS

AK11

VSS

AK16

VSS

AK18

VSS

AK21

VSS

AK22

VSS

AK27

VSS

AK63

VSS

AK68

VSS

AK69

VSS

AK8

VSS

AL2

VSS

AL28

VSS

AL32

VSS

AL35

VSS

AL38

VSS

AL4

VSS

AL45

VSS

AL48

VSS

AL52

VSS

AL55

VSS

AL58

VSS

AL64

VSS

KBL-RU42_BGA1356

GND 1 OF 3

Rev_0.1

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

16 OF 20

AL65
AL66
AM13
AM21
AM25
AM27
AM43
AM45
AM46
AM55
AM60
AM61
AM68
AM71
AM8
AN20
AN23
AN28
AN30
AN32
AN33
AN35
AN37
AN38
AN40
AN42
AN58
AN63
AP10
AP18
AP20
AP23
AP28
AP32
AP35
AP38
AP42
AP58
AP63
AP68
AP70
AR11
AR15
AR16
AR20
AR23
AR28
AR35
AR42
AR43
AR45
AR46
AR48
AR5
AR50
AR52
AR53
AR55
AR58
AR63
AR8
AT2
AT20
AT23
AT28
AT35
AT4
AT42
AT56
AT58

UC1Q

AT63
AT68
AT71
AU10
AU15
AU20
AU32
AU38

AV1
AV68
AV69
AV70
AV71

AW10
AW12
AW14
AW16
AW18
AW21
AW23
AW26
AW28
AW30
AW32
AW34
AW36
AW38
AW41
AW43
AW45
AW47
AW49
AW51
AW53
AW55
AW57

AW6
AW60
AW62
AW64
AW66

AW8

AY66

B10
B14
B18
B22
B30
B34
B39
B44
B48
B53
B58
B62
B66
B71

BA1
BA10
BA14
BA18

BA2
BA23
BA28
BA32
BA36

F68

BA45

KBL-RU42_BGA1356

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

GND 2 OF 3

Rev_0.1

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

17 OF 20

BA49
BA53
BA57
BA6
BA62
BA66
BA71
BB18
BB26
BB30
BB34
BB38
BB43
BB55
BB6
BB60
BB64
BB67
BB70
C1
C25
C5
D10
D11
D14
D18
D22
D25
D26
D30
D34
D39
D44
D45
D47
D48
D53
D58
D6
D62
D66
D69
E11
E15
E18
E21
E46
E50
E53
E56
E6
E65
E71
F1
F13
F2
F22
F23
F27
F28
F32
F33
F35
F37
F38
F4
F40
F42
BA41

CPU@

UC1R

F8

VSS

G10

VSS

G22

VSS

G43

VSS

G45

VSS

G48

VSS

G5

VSS

G52

VSS

G55

VSS

G58

VSS

G6

VSS

G60

VSS

G63

VSS

G66

VSS

H15

VSS

H18

VSS

H71

VSS

J11

VSS

J13

VSS

J25

VSS

J28

VSS

J32

VSS

J35

VSS

J38

VSS

J42

VSS

J8

VSS

K16

VSS

K18

VSS

K22

VSS

K61

VSS

K63

VSS

K64

VSS

K65

VSS

K66

VSS

K67

VSS

K68

VSS

K70

VSS

K71

VSS

L11

VSS

L16

VSS

L17

VSS

KBL-RU42_BGA1356

KBL-R U4+2

GND 3 OF 3

Rev_0.1

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

18 OF 20

L18
L2
L20
L4
L8
N10
N13
N19
N21
N6
N65
N68
P17
P19
P20
P21
R13
R6
T15
T17
T18
T2
T21
T4
U10
U63
U64
U66
U67
U69
U70
V16
V17
V18
W13
W6
W9
Y17
Y19
Y20
Y21

Note1: VCCPRIM_CORE Implementat i on wit h PC H C ORE_VI D Reco mmendat i on

R1: PR408,PR411 ; R2: PR417,PR418 ; R3,PR419,PR420 ; R4: PR423 ; R5: PR424

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.

5

4

3

2

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CPU (14/14)

CPU (14/14)

CPU (14/14)

LA-F292P

LA-F292P

LA-F292P

19 60Tuesday, November 14, 2017

19 60Tuesday, November 14, 2017

19 60Tuesday, November 14, 2017

1

1.0

1.0

1.0