Compal LA-F292P Schematics Rev1.0

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smd.db-x7.ru

COMPAL CONFIDENTIAL

B

C

D

E

1 1

MODEL NAME :DDA30
PCB NO : LA-F292P

Port Map:
Kirkwood MLK Port Map as of 2017-04-13

BOM P/N :

X9 KBL UMA U42

Kabylake R

2017-11-14

2 2

@ : Nopop Component

EMI@ : EMI Component

@EMI@ : EMI Nopop Component

ESD@ : ESDComponent

@ESD@ : ESD Nopop Component

RF@ : RF Component

@RF@ : RF Nopop Component

3 3

CXDP@ : XDP Component

REV : 1.0(A00)

RTD3@ : Support RTD3 Component

NRTD3@ : No Support RTD3 Component
@RTD3@ : Reserve RTD3 Component

CONN@ : Connector Component

ESPI@ : ESPI interface Component

MB PCB

Part Number

DAB00025010

Description

PCB 26B LA-F292P REV1 MB UMA AR 2

Layout Dell logo

4 4

COPYRIGHT 2016

ALL RIGHT RESERVED
REV:X00
PWB:

A

PWR CKT:0810

LPC@ : External ESPI Component (SHD)

U42@ : KBL-R U42 Component
U22@ : KBL-R U22 Component

DS3@ : Support DS3 Component

NDS3@ : No Support DS3 Component

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOU T THE EXPRESS WRITTEN AUTHORIZATION O F DELL. IN ADDITION,
NEITHER THIS SHEET NOR TH E INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

B

PARTY WITHOUT DELL'S EXPRESS WRIT TEN CONSENT.

C

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Cover Sheet

Cover Sheet

Cover Sheet

LA-F292P

LA-F292P

LA-F292P

1 60Tuesday, November 14, 2017

1 60Tuesday, November 14, 2017

1 60Tuesday, November 14, 2017

E

1.0

1.0

1.0

A

smd.db-x7.ru

B

C

D

E

Kirkwood MLK AR Block Diagram

1 1

HDMI 1.4
CONN

Lef t r ear TypeC

Lef t fr ont TypeC

HDMI

P22

USB3.0/USB2.0

P28

USB3.0/USB2.0

P29

PD Solution
TPS65982D

2 2

Micro SIM

P33

EDP CONN

AR-DP

USB2.0/SMBusUSB2.0/SMBus

P25-2 6

SATA[1]/PC IE[8]

M.2,3042 Key B

WWAN/LTE/HCA

PCIex2 for 2nd SSD and
Optane

P30

P23-2 4

P33

USB2.0[4]

eDP Lane x 4

PCIE[1][2][3][ 4]

PCIE[6]

M.2,3030 Key A

WLAN+BT/WIGIG

SW2_DP1

PCIE[5]

P33

USB2.0[7]

DDI[1]

DDI[2]

INTEL

KABYLAKE_U/R MCP

Memory BUS (LPDDR3)

4xSDP/DDP/QDP

4x32b,1866MH z

USB

USB2.0[8]

I2C[0,2]

USB2.0[9]

SLGC55544BVTR
USB POWER SHARE

USB/PCIE MUX

HD3SS3212

3 3

Smart Card

TDA8034HN

RFID/NFC

NB-2023-S

4 4

A

Fingerprint
CONN

P32

USB3.0[2]PCIE[7]

SPI

SPI

USH TPM1.2
BCM58102

USB2.0[10]

USH board

GPIO expander
MCP23008

B

PAGE 6~19

HD Audio I/F

SPI

SATA[2]/PCIE [12][11][10 ][9]

W25Q128JVSIQ

ESPI

P38

SMSC KBC

I2C

P37

MEC5105

P36

128M 4K sector

W25Q128JVSIQ

128M 4K sector

TPM1.2
NPCT650JB2YX &
NPCT750JAAYX

KB/TP CONN

FAN CONN

C

P8

P8

reserve

P38

P42

P37

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER P ROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

HDA Codec
ALC3253

Memory Down

LPDDR3 x 2

P20,P2 1

USB2.0[5]

USB2.0[9]_PS

P40

USB3.0[1]

USB2.0[2]

USB3.0[3]

USB2.0[6]

USB3.0[4]

Wacom G12T Touchscreen/Pen

10 pin conn(default).

I2C

MEC5105

INT.Speaker

Universal Jack

P35

Dig. MIC

P30

0 ohm

0 ohm

P35

P35

P30

Trough eDP Cable

M.2 2280

SSD Conn

P39

D

Trough eDP Cable

UF Camera

P30

USB3.0 Conn
PS(Ext Port 1)

USB3.0 Conn
(Ext Port 2)

Card reader
RTS5330

2nd Accelerometer
(MB)

Magnetometer/

E-Compass

P40

P41

P31

P45

SD4.0

P31

Place on Sensor/B

Accelerometer &
Gyroscope

Place on RF module

SAR Sensor
Semtech SX9310

P45

LID SWITCH for

Laptop mode

LID SWITCH for
Tablet mode

USH CONN

CPU&PCH XDP Port

AUTOMATIC POWER
SWITCH(APS)

DC/DC Interface

Place on PWR/B

POWER ON/OFF

SW & LED

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size

Size

Size

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Block diagram

Block diagram

Block diagram

Document Number Re v

Document Number Re v

Document Number Re v

LA-F292P

LA-F292P

LA-F292P

E

P45

P45

P38

P14

P11

P44

P43

1.0

1.0

2 60Tuesday, November 14, 2017

2 60Tuesday, November 14, 2017

2 60Tuesday, November 14, 2017

1.0

5

smd.db-x7.ru

4

3

2

1

POWER STATES

Signal

State

S0 (Full ON) / M0

S3 (Suspend to RAM) / M3 LOW

D D

S4 (Suspend to DISK) / M3

S5 (SOFT OFF) / M3

S3 (Suspend to RAM) / M-OFF

S4 (Suspend to DISK) / M-OFF

S5 (SOFT OFF) / M-OFF

SLP
S3#

HIGH

LOW

LOW

LOW LOW LOW

LOW LOW LOW LOW

SLP

SLP

S5#

S4#

HIGH HIGH

HIGH HIGH

HIGH HIGH

LOW

LOW

LOW

HIGH HIGH

HIGH

ALWAYS

SLP

PLANE

A#

HIGH

ON

HIGH

ON ON ON

ON ON

HIGH

ON ON

ON ON

LOW

ON

ON

M
PLANE

ON

OFF OFF OFF

OFF OFF OFF OFF

OFF OFF OFF OFF

RUN

SUS

PLANE

PLANE

ON ON ON

OFF

OFF

OFF

OFF

OFFLOW

CLOCKS

OFF

OFF

OFF

USB3.0

USB3.0-1

USB3.0-2

USB3.0-3

USB3.0-4

USB3.0-5

USB3.0-6

PM TABLE

+5V_ALW
+3.3V_ALW
+3.3V_ALW_DSW

power

C C

State

S0

S3

S5 S4/AC

S5 S4/AC doesn't exist

plane

+3.3V_ALW_PCH +1.2V_MEM

+RTC_CELL

+1.8V_PRIM
+1.0V_PRIM
+1.0V_PRIM_CORE
+5V_ALW2
+3.3V_ALW2
+3.3V_RTC_LDO
+1.0V_MPHYGT

ON

ON

ON

+3.3V_CV2

+2.5V_MEM
+1.0V_VCCST

+5V_RUN

+3.3V_RUN

+0.6V_DDR_VTT

+1.8V_RUN

ON ON

ON

OFF

OFFOFF

+3.3V_M +3.3V_M

OFF

OFF

OFF

ON

ON

ON

(M-OFF)

+VCC_CORE

+VCC_GT

+1.0VS_VCCIO
+VCC_SA

ON

OFF

OFF

OFFOFF

SSIC

SSIC

PCIE

PCIE-1

PCIE-2

PCIE-3

PCIE-4

PCIE-5

PCIE-6

PCIE-7

PCIE-8

PCIE-9

PCIE-10

PCIE-11

PCIE-12

SATA

SATA-0

M.2 3042(SATA Cache or HCA)

SATA-1

SATA-1*

SATA-2

JUSB1-->Right

M.2 3042(LTE)

JUSB2-->Lef t

SD Card Reader

Alpine Ridge-DP

M.2 3030(WLAN)

M.2 3030(WIGIG)

M.2 2280 SSD
(PCIe4 or SATA)

USB PORT#DESTINATION

1

2

3

4

5

6

7

8

9

10

DESTINATION

TYPEC Front Side

JUSB2-->Lef t

TYPEC Rear Side

M2 3042(WWAN)

UF Camera

SD Card Reader

M.2 3030(BT)

Touch Screen

JUSB1-->Right

USH

B B

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EX PRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET N OR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY TH IRD
PARTY WITHOUT DELL'S EX PRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date : Sheet of

Date : Sheet of

Date : Sheet of

Compal Electronics, Inc.

Port assignment

Port assignment

Port assignment

LA-F292P

LA-F292P

LA-F292P

1

3 60Tuesday, November 14, 2017

3 60Tuesday, November 14, 2017

3 60Tuesday, November 14, 2017

1.0

1.0

1.0

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smd.db-x7.ru

Barrel
ADAPTER

D D

C C

B B

+3.3V_TBT_SX

CHARGER

ISL9538
(PU901)

BATTERY

ISL95808

(PU614)

IMVP_VR_ON

Type-C
ADAPTER

+5V_ALW

ISL95857

(PU602)

CSD97396

(PU612)

IMVP_VR_ON

+VCC_GT+VCC_SA

AP2112K

(UT14)

+PWR_SRC

CSD97396

(PU610)

IMVP_VR_ON

+VCC_CORE

AO6405

(QV1)

+BL_PWR_SRC

TPS65982D

(UT5,UT11)

+5V_ALW

+5V_TBT_VBUS

EN_IN VPWR

A A

4

SY8210A
(PU200)

SY8286R
(PU301)

SYV828C

(PU102)

SY8288B

(PU100)

+TBT_VBUS(5V~20V)

AP2204

(UT8,UT12)

SIO_SLP_S4#

0.6V_DDR_VTT_ON

SIO_SLP_SUS#

ALWON

ALWON

TYPE-C

+1.2V_MEM

+0.6V_DDR_VTT

+1.0V_PRIM

+5V_ALW

+5V_ALW2

+3.3V_RTC_LDO

+3.3V_ALW2

+3.3V_ALW

TPS22961

(UZ26)

3

SIO_SLP_SUS#
SIO_SLP_S4#

SLGC55544C

(UI3)

RT8097ALGE
(PU501)

G524B1T11U
(UV24)

+VCC_SFR_OC

TPS62134C

(PU401)

TPS62134D

(PU402)

EM5209

(UZ4)

EM5209

(@UZ5)

SY6288

(UI1)

AP7361C

(PU503)

EM5209

(UZ2)

EM5209

(UZ3)

EM5209

(UZ4)

EM5209

(@UZ5)

AOZ1336

(UT4)

TPS22967

(UZ18)

RUN_ ON

SIO_SLP_SUS#

RUN_ ON

AUD_PW R_EN

USB_POWERSHAR E_VBUS_E N

USB_PWR_EN1#

SIO_SLP_S4#

SIO_SLP_SUS#

AUX_EN_WOW L

@SIO_SLP_WLAN#

SIO_SLP_SUS#

@PCH_ALW _ON

RUN_ ON

3.3V_W WAN_EN

AUD_PW R_EN

ENVCC_PCH

TBT_PWR_EN

CV2_ON

+1.0VS_VCCIO

+1.0V_PRIM_CORE

+USB_EX2_PWR

+1.8V_MEM

+1.8V_PRIM

+3.3V_WLAN

+3.3V_ALW_PCH

+3.3V_RUN

+3.3V_WWAN

+3.3V_RUN_AUDIO

+LCDVDD

+3.3V_TBT

+3.3V_CV2

TPS22961

(UZ19)

TPS22961

(UZ21)

+5V_RUN

+5V_RUN_AUDIO

+5V_USB_CHG_PWR

for LPDDR3

2

CPU PWR

PCH PWR

Peripheral Device PWR

RUN_ ON

TYPE-C Power

+3.3V_TSP

+1.8V_RUN

+3.3V_CAM

USH/B

RUN_ ON
SIO_SLP_S0#

SIO_SLP_S4#

LP2301

(QV8)

AOZ1336

(UZ8)

LP2301A

(QZ1)

+1.0V_VCCSTG

+1.0V_VCCST

3.3V_TS_EN

3.3V_CAM_EN#

1

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EX PRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET N OR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY TH IRD
PARTY WITHOUT DELL'S EX PRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date : Sheet of

Date : Sheet of

Date : Sheet of

Compal Electronics, Inc.

Power rails

Power rails

Power rails

LA-F292P

LA-F292P

LA-F292P

1

4 60Tuesday, November 14, 2017

4 60Tuesday, November 14, 2017

4 60Tuesday, November 14, 2017

1.0

1.0

1.0

5

smd.db-x7.ru

SMBUS Address [0x9a]

AW44
BB43

PCH

D D

AW45 AW42

03

C C

KBC

MEC 5105

B B

SML1_SMBDATA

SML1_SMBCLK

D8E11

03

00
00

01
01

02
02

04
04

05
05

06

06

07
07

AY44
BB39

D7
E7

B3
E5

E10
C12

C3
B4

F7
B6

A12

N10

M4
M7

4

MEM_SMBCLK

MEM_SMBDATA

SML0_SMBCLK

SML0_SMBDATA

1K

1K

+3.3V_ALW_PCH

UPD2_SMBCLK
UPD2_SMBDAT

USH_SMBCLK
USH_SMBDAT

DAT_TP_SIO_I2C_CLK

DAT_TP_SIO_I2C_DATA

UPD1_SMBCLK
UPD1_SMBDAT

EXPANDER_GPU_SMCLK

EXPANDER_GPU_SMDATA

499

499

1K

1K

2.2K

2.2K

@2.2K

@2.2K

2.2K

2.2K

2.2K

+3.3V_ALW_PCH

+3.3V_ALW_PCH

+3.3V_ALW

DMN66D0LDW-7
DMN66D0LDW-7

+3.3V_ALW

+3.3V_ALW

DMN66D0LDW-7
DMN66D0LDW-7

2.2K

2.2K

+3.3V_ALW

3

DMN66D0LDW-7
DMN66D0LDW-7

M9
L9

2.2K

2.2K

USH

DDR_XDP_WAN_SMBCLK

DDR_XDP_WAN_SMBDATA

2.2K

2.2K

+3.3V_CV2

4.7K

2.2K

2.2K

2

+3.3V_TBT_FLASH

B5

PD
FW reflash

A5

DMN66D0LDW-7
DMN66D0LDW-7

USH/B

+3.3V_RUN

I2C_1_SCL
I2C_1_SDA

+3.3V_TBT_FLASH

B5
A5

Expander IO

1

2.2K

0
0
0
0

53
51

+3.3V_RUN

2.2K

2.2K

XDP

KEYSCAN_SMBDAT

+3.3V_RUN

SAR

ALS

TP

2.2K

PD

08 C5

C8

08

F6

09

E9

09

N2

A A

1010M3

PBAT_CHARGER_SMBCLK
PBAT__CHARGER_SMBDAT

2.2K

2.2K

+3.3V_ALW

100 ohm

100 ohm

7
6

Charger

BATTERY

CONN

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EX PRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET N OR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY TH IRD
PARTY WITHOUT DELL'S EX PRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date : Sheet of

Date : Sheet of

Date : Sheet of

Compal Electronics, Inc.

Port assignment

Port assignment

Port assignment

LA-F292P

LA-F292P

LA-F292P

1

5 60Tuesday, November 14, 2017

5 60Tuesday, November 14, 2017

5 60Tuesday, November 14, 2017

1.0

1.0

1.0

5

smd.db-x7.ru

4

3

2

1

+3.3V_RUN

CPU_DP1_CTRL_CLK

RC175 2.2K_0402_5%
RC178 2.2K_0402_5%

D D

RC176 2.2K_0402_5%
RC177 2.2K_0402_5%

C C

B B

12
12
12
12

UC1I

CSI-2

A36

CSI2_DN0

B36

CSI2_DP0

C38

CSI2_DN1

D38

CSI2_DP1

C36

CSI2_DN2

D36

CSI2_DP2

A38

CSI2_DN3

B38

CSI2_DP3

C31

CSI2_DN4

D31

CSI2_DP4

C33

CSI2_DN5

D33

CSI2_DP5

A31

CSI2_DN6

B31

CSI2_DP6

A33

CSI2_DN7

B33

CSI2_DP7

A29

CSI2_DN8

B29

CSI2_DP8

C28

CSI2_DN9

D28

CSI2_DP9

A27

CSI2_DN10

B27

CSI2_DP10

C27

CSI2_DN11

D27

CSI2_DP11

KBL-RU42_BGA1356

CPU_DP1_CTRL_DATA
CPU_DP2_CTRL_CLK
CPU_DP2_CTRL_DATA

CPU@

KBL-R U4+2

AR

+1.0VS_VCCIO

Rev_0.1

CSI2_CLKN0
CSI2_CLKP0
CSI2_CLKN1
CSI2_CLKP1
CSI2_CLKN2
CSI2_CLKP2
CSI2_CLKN3
CSI2_CLKP3

CSI2_COMP

GPP_D4/FLASHTRIG

EMMC

GPP_F13/EMMC_DATA0
GPP_F14/EMMC_DATA1
GPP_F15/EMMC_DATA2
GPP_F16/EMMC_DATA3
GPP_F17/EMMC_DATA4
GPP_F18/EMMC_DATA5
GPP_F19/EMMC_DATA6
GPP_F20/EMMC_DATA7

GPP_F21/EMMC_RCLK

GPP_F22/EMMC_CLK

GPP_F12/EMMC_CMD

EMMC_RCOMP

9 OF 20

CPU_DP1_N0<23>
CPU_DP1_P0<23>
CPU_DP1_N1<23>
CPU_DP1_P1<23>
CPU_DP1_N2<23>
CPU_DP1_P2<23>
CPU_DP1_N3<23>
CPU_DP1_P3<23>

CPU_DP2_N0<23>
CPU_DP2_P0<23>
CPU_DP2_N1<23>
CPU_DP2_P1<23>
CPU_DP2_N2<23>
CPU_DP2_P2<23>
CPU_DP2_N3<23>
CPU_DP2_P3<23>

CPU_DP1_CTRL_CLK<23>

CPU_DP1_CTRL_DATA<23>

TS_INT#<30>

RC2 24.9_0402_1%

COMPENSATION PU FOR eDP

CAD Note:Trace width=20 mils , Spacing=25mil,
Max length=100 mils.

C37
D37
C32
D32
C29
D29
B26
A26

CSI2_COMP

E13

TBT_FORCE_PWR

B7

MEM_CONFIG0

AP2

MEM_CONFIG1

AP1

MEM_CONFIG2

AP3

MEM_CONFIG3

AN3

MEM_CONFIG4

AN1
AN2
AM4
AM1

AM2
AM3
AP4

EMMC_RCOMP

AT1

CPU_DP1_CTRL_CLK
CPU_DP1_CTRL_DATA

CPU_DP2_CTRL_CLK
CPU_DP2_CTRL_DATA

1 2

TBT_FORCE_PWR <23>

EDP_COMP

12

RC3 100_0402_1%

1 2

RC4 200_0402_1%

UC1A

CPU@

E55

DDI1_TXN[0]

F55

DDI1_TXP[0]

E58

DDI1_TXN[1]

F58

DDI1_TXP[1]

F53

DDI1_TXN[2]

G53

DDI1_TXP[2]

F56

DDI1_TXN[3]

G56

DDI1_TXP[3]

C50

DDI2_TXN[0]

D50

DDI2_TXP[0]

C52

DDI2_TXN[1]

D52

DDI2_TXP[1]

A50

DDI2_TXN[2]

B50

DDI2_TXP[2]

D51

DDI2_TXN[3]

C51

DDI2_TXP[3]

L13

GPP_E18/DDPB_CTRLCLK

L12

GPP_E19/DDPB_CTRLDATA

N7

GPP_E20/DDPC_CTRLCLK

N8

GPP_E21/DDPC_CTRLDATA

N11

GPP_E22

N12

GPP_E23

E52

EDP_RCOMP

KBL-RU42_BGA1356

KBL-RU42_BGA1356.olb

KBL-R U4+2

DDI

DISPLAY SIDEBANDS

EDP

Rev_0.1

EDP_TXN[0]
EDP_TXP[0]
EDP_TXN[1]
EDP_TXP[1]
EDP_TXN[2]
EDP_TXP[2]
EDP_TXN[3]
EDP_TXP[3]

EDP_AUXN
EDP_AUXP

EDP_DISP_UTIL

DDI1_AUXN
DDI1_AUXP
DDI2_AUXN
DDI2_AUXP

RSVD

GPP_E13/DDPB_HPD0
GPP_E14/DDPC_HPD1
GPP_E15/DDPD_HPD2
GPP_E16/DDPE_HPD3

RSVD

GPP_E17/EDP_HPD

EDP_BKLTEN

EDP_BKLTCTL

EDP_VDDEN

1 OF 20

C47
C46
D46
C45
A45
B45
A47
B47

E45
F45

B52

CPU_DP1_AUXN

G50

CPU_DP1_AUXP

F50
E48
F48

CPU_DP3_AUXN

G46

CPU_DP3_AUXP

F46
L9

L7
L6
N9
L10

R12
R11
U13

EDP_TXN0 <30>
EDP_TXP0 <30>
EDP_TXN1 <30>
EDP_TXP1 <30>
EDP_TXN2 <30>
EDP_TXP2 <30>
EDP_TXN3 <30>
EDP_TXP3 <30>

EDP_AUXN <30>
EDP_AUXP <30>

CPU_DP1_AUXN <23>
CPU_DP1_AUXP <23>
CPU_DP2_AUXN <23>
CPU_DP2_AUXP <23>

@

T1

PAD~D

@

T2

PAD~D

CPU_DP1_HPD <23>
CPU_DP2_HPD <23>

EDP_HPD <30>

PANEL_BKLEN <30>
EDP_BIA_PWM <30>
ENVDD_PCH <30>

support QHD

EDP_HPD

1 2

RC1 100K_0402_5%

A A

+1.8V_PRIM

5

1 2

RC388 10K_0402_5%X76@

1 2

RC389 10K_0402_5%X76@

1 2

RC390 10K_0402_5%X76@

1 2

RC391 10K_0402_5%X76@

1 2

RC392 10K_0402_5%X76@

MEM_CONFIG0
MEM_CONFIG1
MEM_CONFIG2
MEM_CONFIG3
MEM_CONFIG4

1 2

RC393 10K_0402_5%X76@

1 2

RC394 10K_0402_5%X76@

1 2

RC395 10K_0402_5%X76@

1 2

RC396 10K_0402_5%X76@

1 2

RC397 10K_0402_5%X76@

4

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.

3

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CPU (1/14)

CPU (1/14)

CPU (1/14)

LA-F292P

LA-F292P

LA-F292P

6 60Tuesday, November 14, 2017

6 60Tuesday, November 14, 2017

6 60Tuesday, November 14, 2017

1

1.0

1.0

1.0

5

smd.db-x7.ru

4

3

2

1

For LPDDR3

DDR_A_DQS#[0..7]<20>

D D

LPDDR3, Ballout for side by side(Non-Interleave)

UC1B

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15

DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40

C C

B B

DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47

AN68
AN69

AN70
AN71
AR70
AR68
AU71
AU68
AR71
AR69
AU70
AU69

BB65
AW65
AW63

AY63

BA65

AY65

BA63

BB63

BA61
AW61

BB59
AW59

BB61

AY61

BA59

AY59

AY39
AW39

AY37
AW37

BB39

BA39

BA37

BB37

AY35
AW35

AY33
AW33

BB35

BA35

BA33

BB33

AY31
AW31

AY29
AW29

BB31

BA31

BA29

BB29

AY27
AW27

AY25
AW25

BB27

BA27

BA25

BB25

CPU@

AL71

DDR0_DQ[0]

AL68

DDR0_DQ[1]
DDR0_DQ[2]
DDR0_DQ[3]

AL70

DDR0_DQ[4]

AL69

DDR0_DQ[5]
DDR0_DQ[6]
DDR0_DQ[7]
DDR0_DQ[8]
DDR0_DQ[9]
DDR0_DQ[10]
DDR0_DQ[11]
DDR0_DQ[12]
DDR0_DQ[13]
DDR0_DQ[14]
DDR0_DQ[15]

Interleave / Non-Interleaved

DDR0_DQ[16]/DDR0_DQ[32]
DDR0_DQ[17]/DDR0_DQ[33]
DDR0_DQ[18]/DDR0_DQ[34]
DDR0_DQ[19]/DDR0_DQ[35]
DDR0_DQ[20]/DDR0_DQ[36]
DDR0_DQ[21]/DDR0_DQ[37]
DDR0_DQ[22]/DDR0_DQ[38]
DDR0_DQ[23]/DDR0_DQ[39]
DDR0_DQ[24]/DDR0_DQ[40]
DDR0_DQ[25]/DDR0_DQ[41]
DDR0_DQ[26]/DDR0_DQ[42]
DDR0_DQ[27]/DDR0_DQ[43]
DDR0_DQ[28]/DDR0_DQ[44]
DDR0_DQ[29]/DDR0_DQ[45]
DDR0_DQ[30]/DDR0_DQ[46]
DDR0_DQ[31]/DDR0_DQ[47]
DDR0_DQ[32]/DDR1_DQ[0]
DDR0_DQ[33]/DDR1_DQ[1]
DDR0_DQ[34]/DDR1_DQ[2]
DDR0_DQ[35]/DDR1_DQ[3]
DDR0_DQ[36]/DDR1_DQ[4]
DDR0_DQ[37]/DDR1_DQ[5]
DDR0_DQ[38]/DDR1_DQ[6]
DDR0_DQ[39]/DDR1_DQ[7]
DDR0_DQ[40]/DDR1_DQ[8]
DDR0_DQ[41]/DDR1_DQ[9]
DDR0_DQ[42]/DDR1_DQ[10]
DDR0_DQ[43]/DDR1_DQ[11]
DDR0_DQ[44]/DDR1_DQ[12]
DDR0_DQ[45]/DDR1_DQ[13]
DDR0_DQ[46]/DDR1_DQ[14]
DDR0_DQ[47]/DDR1_DQ[15]
DDR0_DQ[48]/DDR1_DQ[32]
DDR0_DQ[49]/DDR1_DQ[33]
DDR0_DQ[50]/DDR1_DQ[34]
DDR0_DQ[51]/DDR1_DQ[35]
DDR0_DQ[52]/DDR1_DQ[36]
DDR0_DQ[53]/DDR1_DQ[37]
DDR0_DQ[54]/DDR1_DQ[38]
DDR0_DQ[55]/DDR1_DQ[39]
DDR0_DQ[56]/DDR1_DQ[40]
DDR0_DQ[57]/DDR1_DQ[41]
DDR0_DQ[58]/DDR1_DQ[42]
DDR0_DQ[59]/DDR1_DQ[43]
DDR0_DQ[60]/DDR1_DQ[44]
DDR0_DQ[61]/DDR1_DQ[45]
DDR0_DQ[62]/DDR1_DQ[46]
DDR0_DQ[63]/DDR1_DQ[47]

KBL-RU42_BGA1356

KBL-R U4+2

DDR0_CKN[0]
DDR0_CKP[0]
DDR0_CKN[1]
DDR0_CKP[1]

DDR0_CKE[0]
DDR0_CKE[1]
DDR0_CKE[2]
DDR0_CKE[3]

DDR0_CS#[0]
DDR0_CS#[1]
DDR0_ODT[0]
DDR0_ODT[1]

DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5]
DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9]
DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6]
DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8]
DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]

DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]
DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12]
DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]

DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT#

DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]

DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]

DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]

DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]

DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]

DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]

DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]

DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]
DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]

DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1]
DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]

DDR CH - A

2 OF 20

DDR3L / LPDDR3 / DDR4

DDR0_DQSN[0]

DDR0_DQSP[0]

DDR0_DQSN[1]

DDR0_DQSP[1]

Interleave / Non-Interleaved

DDR0_DQSN[2]/DDR0_DQSN[4]
DDR0_DQSP[2]/DDR0_DQSP[4]
DDR0_DQSN[3]/DDR0_DQSN[5]
DDR0_DQSP[3]/DDR0_DQSP[5]
DDR0_DQSN[4]/DDR1_DQSN[0]
DDR0_DQSP[4]/DDR1_DQSP[0]
DDR0_DQSN[5]/DDR1_DQSN[1]
DDR0_DQSP[5]/DDR1_DQSP[1]
DDR0_DQSN[6]/DDR1_DQSN[4]
DDR0_DQSP[6]/DDR1_DQSP[4]
DDR0_DQSN[7]/DDR1_DQSN[5]
DDR0_DQSP[7]/DDR1_DQSP[5]

DDR0_ALERT#

DDR_VREF_CA
DDR0_VREF_DQ
DDR1_VREF_DQ

DDR_VTT_CNTL

Rev_0.1

DDR0_MA[3]
DDR0_MA[4]

DDR0_PAR

DDR_A_CLK#0

AU53

DDR_A_CLK0

AT53

DDR_A_CLK#1

AU55

DDR_A_CLK1

AT55

DDR_A_CKE0

BA56

DDR_A_CKE1

BB56

DDR_A_CKE2

AW56

DDR_A_CKE3

AY56

DDR_A_CS#0

AU45

DDR_A_CS#1

AU43

DDR_A_ODT0

AT45
AT43

DDR_A_CAA0

BA51

DDR_A_CAA1

BB54

DDR_A_CAA2

BA52

DDR_A_CAA3

AY52

DDR_A_CAA4

AW52

DDR_A_CAA5

AY55

DDR_A_CAA6

AW54

DDR_A_CAA7

BA54

DDR_A_CAA8

BA55

DDR_A_CAA9

AY54

DDR_A_CAB0

AU46

DDR_A_CAB1

AU48

DDR_A_CAB2 DDR_B_CAB1

AT46

DDR_A_CAB3

AU50

DDR_A_CAB4

AU52

DDR_A_CAB5

AY51

DDR_A_CAB6

AT48

DDR_A_CAB7

AT50

DDR_A_CAB8

BB50

DDR_A_CAB9

AY50
BA50

BB52

DDR_A_DQS#0

AM70

DDR_A_DQS0

AM69

DDR_A_DQS#1

AT69

DDR_A_DQS1

AT70

DDR_A_DQS#4

BA64

DDR_A_DQS4

AY64

DDR_A_DQS#5

AY60

DDR_A_DQS5

BA60

DDR_B_DQS#0

BA38

DDR_B_DQS0

AY38

DDR_B_DQS#1

AY34

DDR_B_DQS1

BA34

DDR_B_DQS#4

BA30

DDR_B_DQS4

AY30

DDR_B_DQS#5

AY26

DDR_B_DQS5

BA26
AW50

AT52
AY67

AY68
BA67

DDR_VTT_CTRL

AW67

DDR_A_D[0..63]<20>
DDR_A_DQS[0..7]<20>

DDR_A_CAA[0..9]<20>
DDR_A_CAB[0..9]<20> DDR_B_CAB[0..9]<21>

DDR_A_CLK#0 <20>
DDR_A_CLK0 <20>
DDR_A_CLK#1 <20>
DDR_A_CLK1 <20>

DDR_A_CKE0 <20>
DDR_A_CKE1 <20>
DDR_A_CKE2 <20>
DDR_A_CKE3 <20> DDR_B_CKE2 <21>

DDR_A_CS#0 <20>
DDR_A_CS#1 <20>
DDR_A_ODT0 <20>

DDR0_PAR,DDR0_ALERT# for DDR4

@

T260

PAD~D

@

T261

PAD~D

+DDR_VREF_CA
+DDR_VREF_A_DQ
+DDR_VREF_B_DQ

DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31

DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

UC1C

Interleave / Non-Interleaved

AF65

DDR1_DQ[0]/DDR0_DQ[16]

AF64

DDR1_DQ[1]/DDR0_DQ[17]

AK65

DDR1_DQ[2]/DDR0_DQ[18]

AK64

DDR1_DQ[3]/DDR0_DQ[19]

AF66

DDR1_DQ[4]/DDR0_DQ[20]

AF67

DDR1_DQ[5]/DDR0_DQ[21]

AK67

DDR1_DQ[6]/DDR0_DQ[22]

AK66

DDR1_DQ[7]/DDR0_DQ[23]

AF70

DDR1_DQ[8]/DDR0_DQ[24]

AF68

DDR1_DQ[9]/DDR0_DQ[25]

AH71

DDR1_DQ[10]/DDR0_DQ[26]

AH68

DDR1_DQ[11]/DDR0_DQ[27]

AF71

DDR1_DQ[12]/DDR0_DQ[28]

AF69

DDR1_DQ[13]/DDR0_DQ[29]

AH70

DDR1_DQ[14]/DDR0_DQ[30]

AH69

DDR1_DQ[15]/DDR0_DQ[31]

AT66

DDR1_DQ[16]/DDR0_DQ[48]

AU66

DDR1_DQ[17]/DDR0_DQ[49]

AP65

DDR1_DQ[18]/DDR0_DQ[50]

AN65

DDR1_DQ[19]/DDR0_DQ[51]

AN66

DDR1_DQ[20]/DDR0_DQ[52]

AP66

DDR1_DQ[21]/DDR0_DQ[53]

AT65

DDR1_DQ[22]/DDR0_DQ[54]

AU65

DDR1_DQ[23]/DDR0_DQ[55]

AT61

DDR1_DQ[24]/DDR0_DQ[56]

AU61

DDR1_DQ[25]/DDR0_DQ[57]

AP60

DDR1_DQ[26]/DDR0_DQ[58]

AN60

DDR1_DQ[27]/DDR0_DQ[59]

AN61

DDR1_DQ[28]/DDR0_DQ[60]

AP61

DDR1_DQ[29]/DDR0_DQ[61]

AT60

DDR1_DQ[30]/DDR0_DQ[62]

AU60

DDR1_DQ[31]/DDR0_DQ[63]

AU40

DDR1_DQ[32]/DDR1_DQ[16]

AT40

DDR1_DQ[33]/DDR1_DQ[17]

AT37

DDR1_DQ[34]/DDR1_DQ[18]

AU37

DDR1_DQ[35]/DDR1_DQ[19]

AR40

DDR1_DQ[36]/DDR1_DQ[20]

AP40

DDR1_DQ[37]/DDR1_DQ[21]

AP37

DDR1_DQ[38]/DDR1_DQ[22]

AR37

DDR1_DQ[39]/DDR1_DQ[23]

AT33

DDR1_DQ[40]/DDR1_DQ[24]

AU33

DDR1_DQ[41]/DDR1_DQ[25]

AU30

DDR1_DQ[42]/DDR1_DQ[26]

AT30

DDR1_DQ[43]/DDR1_DQ[27]

AR33

DDR1_DQ[44]/DDR1_DQ[28]

AP33

DDR1_DQ[45]/DDR1_DQ[29]

AR30

DDR1_DQ[46]/DDR1_DQ[30]

AP30

DDR1_DQ[47]/DDR1_DQ[31]

AU27

DDR1_DQ[48]

AT27

DDR1_DQ[49]

AT25

DDR1_DQ[50]

AU25

DDR1_DQ[51]

AP27

DDR1_DQ[52]

AN27

DDR1_DQ[53]

AN25

DDR1_DQ[54]

AP25

DDR1_DQ[55]

AT22

DDR1_DQ[56]

AU22

DDR1_DQ[57]

AU21

DDR1_DQ[58]

AT21

DDR1_DQ[59]

AN22

DDR1_DQ[60]

AP22

DDR1_DQ[61]

AP21

DDR1_DQ[62]

AN21

DDR1_DQ[63]

KBL-RU42_BGA1356

CPU@

KBL-R U4+2

DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5]
DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9]
DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6]
DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8]
DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]

DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]
DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12]
DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]

DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT#
DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]

DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]

DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]

DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]

DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]

DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]

DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]

DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]
DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]

DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1]
DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]

DDR CH - B

3 OF 20

DDR3L / LPDDR3 / DDR4

Interleave / Non-Interleaved

DDR1_DQSN[0]/DDR0_DQSN[2]

DDR1_DQSP[0]/DDR0_DQSP[2]

DDR1_DQSN[1]/DDR0_DQSN[3]

DDR1_DQSP[1]/DDR0_DQSP[3]

DDR1_DQSN[2]/DDR0_DQSN[6]

DDR1_DQSP[2]/DDR0_DQSP[6]

DDR1_DQSN[3]/DDR0_DQSN[7]

DDR1_DQSP[3]/DDR0_DQSP[7]

DDR1_DQSN[4]/DDR1_DQSN[2]

DDR1_DQSP[4]/DDR1_DQSP[2]

DDR1_DQSN[5]/DDR1_DQSN[3]

DDR1_DQSP[5]/DDR1_DQSP[3]

DRAM_RESET#
DDR_RCOMP[0]
DDR_RCOMP[1]
DDR_RCOMP[2]

Rev_0.1

DDR1_CKN[0]
DDR1_CKN[1]
DDR1_CKP[0]
DDR1_CKP[1]

DDR1_CKE[0]
DDR1_CKE[1]
DDR1_CKE[2]
DDR1_CKE[3]

DDR1_CS#[0]
DDR1_CS#[1]
DDR1_ODT[0]
DDR1_ODT[1]

DDR1_MA[3]
DDR1_MA[4]

DDR1_DQSN[6]
DDR1_DQSP[6]
DDR1_DQSN[7]
DDR1_DQSP[7]

DDR1_ALERT#

DDR1_PAR

AN45
AN46
AP45
AP46

AN56
AP55
AN55
AP53

BB42
AY42
BA42
AW42

AY48
AP50
BA48
BB48
AP48
AP52
AN50
AN48
AN53
AN52
BA43
AY43
AY44
AW44
BB44
AY47
BA44
AW46
AY46
BA46

BB46
BA47

AH66
AH65
AG69
AG70
AR66
AR65
AR61
AR60
AT38
AR38
AT32
AR32

AR25
AR27
AR22
AR21
AN43
AP43
AT13
AR18
AT18
AU18

DDR_B_DQS#[0..7]<21>

DDR_B_D[0..63]<21>
DDR_B_DQS[0..7]<21>

DDR_B_CAA[0..9]<21>

DDR_B_CLK#0
DDR_B_CLK#1
DDR_B_CLK0
DDR_B_CLK1

DDR_B_CKE0
DDR_B_CKE1
DDR_B_CKE2
DDR_B_CKE3

DDR_B_CS#0
DDR_B_CS#1
DDR_B_ODT0

DDR_B_CAA0
DDR_B_CAA1
DDR_B_CAA2
DDR_B_CAA3
DDR_B_CAA4
DDR_B_CAA5
DDR_B_CAA6
DDR_B_CAA7
DDR_B_CAA8
DDR_B_CAA9
DDR_B_CAB0

DDR_B_CAB2
DDR_B_CAB3
DDR_B_CAB4
DDR_B_CAB5
DDR_B_CAB6
DDR_B_CAB7
DDR_B_CAB8
DDR_B_CAB9

DDR_A_DQS#2
DDR_A_DQS2
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_DQS#7
DDR_A_DQS7
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_DQS#3
DDR_B_DQS3

DDR_B_DQS#6
DDR_B_DQS6
DDR_B_DQS#7
DDR_B_DQS7

SM_RCOMP0
SM_RCOMP1
SM_RCOMP2

DDR_B_CLK#0 <21>
DDR_B_CLK#1 <21>
DDR_B_CLK0 <21>
DDR_B_CLK1 <21>

DDR_B_CKE0 <21>
DDR_B_CKE1 <21>

DDR_B_CKE3 <21>
DDR_B_CS#0 <21>

DDR_B_CS#1 <21>
DDR_B_ODT0 <21>

@

T257

PAD~D

@

T258

PAD~D

@

T259

PAD~D

DDR1_PAR,DDR1_ALERT# for DDR4

VCC

+1.2V_MEM

5

4

Y

1 2

CD115@ 0.1U_0201_10V6K

1 2

RD83 100K_0402_5%

CHECK

0.6V_DDR_VTT_ON (control 0.6V power EN)

0.6V_DDR_VTT_ON <49>

+3.3V_RUN

UD5

1

DDR_VTT_CTRL

NC

2

A

3

GND

74AUP1G07SE-7 SOT353

A A

LPDDR3 COMPENSATION SIGNALS

SM_RCOMP0
SM_RCOMP1
SM_RCOMP2

CAD Note:
Trace width=12~15 mil, Spacing=20 mils
Max trace length= 500 mil

1 2

RC5 200_0402_1%

1 2

RC6 80.6_0402_1%

1 2

RC7 162_0402_1%

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.

5

4

3

2

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CPU (2/14)

CPU (2/14)

CPU (2/14)

LA-F292P

LA-F292P

LA-F292P

7 60Tuesday, November 14, 2017

7 60Tuesday, November 14, 2017

7 60Tuesday, November 14, 2017

1

1.0

1.0

1.0

5

smd.db-x7.ru

SPI_MOSI= SPI_IO0
SPI_MISO= SPI_IO1
PCH EDS R0.7 p.235~236

PCH_SPI_CLK
PCH_SPI_D1

12

PCH_SPI_D0
PCH_SPI_D2
PCH_SPI_D3
PCH_SPI_CS#0
PCH_SPI_CS#1
PCH_SPI_CS#2

1 2

+3.3V_1.8V_ESPI

RC10 1K_0402_1%CXDP@

1 2

RC11 1K_0402_1%CXDP@

PCH_SPI_CS#2<38>

PCH_CL_CLK1<33>
PCH_CL_DATA1<33>
PCH_CL_RST1#<33>

ESPI_ALERT#<36>

RC21 8.2K_0402_1%

PCH_SPI_DO_XDP<14>

D D

PCH_SPI_DO2_XDP<14>

AV2

AW3

AV3

AW2

AU4
AU3
AU2
AU1

M2
M3

J4
V1
V2

M1

G3
G2
G1

AW13

AY11

KBL-RU42_BGA1356

4

UC1E

CPU@

SPI - FLASH

SPI0_CLK
SPI0_MISO
SPI0_MOSI
SPI0_IO2
SPI0_IO3
SPI0_CS0#
SPI0_CS1#
SPI0_CS2#

SPI - TOUCH

GPP_D1/SPI1_CLK
GPP_D2/SPI1_MISO
GPP_D3/SPI1_MOSI
GPP_D21/SPI1_IO2
GPP_D22/SPI1_IO3
GPP_D0/SPI1_CS#

C LINK

CL_CLK
CL_DATA
CL_RST#

GPP_A0/RCIN#
GPP_A6/SERIRQ

KBL-R U4+2

LPC

3

SMBUS, SMLINK

GPP_C2/SMBALERT#

GPP_C5/SML0ALERT#

GPP_B23/SML1ALERT#/PCHHOT#

GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1
GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS#

GPP_A14/SUS_STAT#/ESPI_RESET#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

GPP_A10/CLKOUT_LPC1

Rev_0.1

GPP_C0/SMBCLK

GPP_C1/SMBDATA

GPP_C3/SML0CLK

GPP_C4/SML0DATA

GPP_C6/SML1CLK

GPP_C7/SML1DATA

GPP_A8/CLKRUN#

5 OF 20

R7
R8
R10

R9
W2
W1

W3
V3
AM7

AY13
BA13
BB13
AY12
BA12
BA11

AW9
AY9
AW11

MEM_SMBCLK
MEM_SMBDATA
PCH_SMB_ALERT#

SML0_SMBCLK
SML0_SMBDATA
GPP_C5

SML1_SMBCLK
SML1_SMBDATA
GPP_B23

ESPI_IO0_R
ESPI_IO1_R
ESPI_IO2_R
ESPI_IO3_R

ESPI_CLK
PCI_CLK_LPC1

CLKRUN#

SML1_SMBCLK <36>
SML1_SMBDATA <36>

1 2

RC366 15_0402_5%

1 2

RC367 15_0402_5%

1 2

RC368 15_0402_5%

1 2

RC369 15_0402_5%

ESPI_CS# <36,37>
ESPI_RESET# <36,37>

1 2

RC16EMI@ 15_0402_5%

1 2

RC22@ 22_0402_5%

2

MEM_SMBCLK

MEM_SMBDATA

ESPI_IO0 <36,37>
ESPI_IO1 <36,37>
ESPI_IO2 <36,37>
ESPI_IO3 <36,37>

ESPI_CLK_5105 <36,37>

+3.3V_RUN

6

CXDP@

5

DMN65D8LDW-7_SOT363-6

3 4

QC2B

CXDP@

DMN65D8LDW-7_SOT363-6

1

For Kirkwood

2

1

DDR_XDP_WAN_SMBCLK <14>

QC2A

DDR_XDP_WAN_SMBDAT <14>

DDR_XDP_WAN_SMBDAT
DDR_XDP_WAN_SMBCLK

MEM_SMBCLK
MEM_SMBDATA
SML1_SMBCLK
SML1_SMBDATA
SML0_SMBCLK
SML0_SMBDATA

1 2

RC318 2.2K_0402_5%

1 2

RC319 2.2K_0402_5%

1 2

RC12 1K_0402_5%

1 2

RC14 1K_0402_5%

1 2

RC15 1K_0402_5%

1 2

RC17 1K_0402_5%

1 2

RC347 499_0402_1%

1 2

RC348 499_0402_1%

+3.3V_RUN

+3.3V_ALW_PCH

C C

ESPI_CLK_5105

SOFTWARE TAA

PCH_SPI_D0_R1<38>

PCH_SPI_CLK_R1<38>

PCH_SPI_CLK_1_R PCH_SPI_CLK_0_R

33_0402_5%

@EMI@

12

RC28

33P_0402_50V8J

@EMI@

B B

12

CC7

33_0402_5%

@EMI@

12

RC29

33P_0402_50V8J

@EMI@

12

CC8

PCH_SPI_CS#0_R1
PCH_SPI_D2_R1 PCH_SPI_CLK_0_R

+3.3V_SPI

RC30 1K_0402_5%@
RC31 1K_0402_5%@

RC316 1K_0402_5%@

03/02:follow Intel MOW_2015WW06

@

1 2

RC37 0_0402_5%

1 2

RC39 33_0402_5%

PCH_SPI_D2_R1

12

PCH_SPI_D3_R1

12

PCH_SPI_D3_R1

12

PCH_SPI_CS#0_R2
PCH_SPI_D1_0_R
PCH_SPI_D2_0_R

PCH_SPI_D1_R1<38>

128Mb Flash ROM

UC5

1

/CS

2

IO1

3

IO2

4

GND

W25Q128FVSIQ_SO8

PCH_SPI_D0_R1
PCH_SPI_CLK_R1
PCH_SPI_D1_R1
PCH_SPI_D3_R1 PCH_SPI_D3_0_R

PCH_SPI_D3_R1
PCH_SPI_CLK_R1
PCH_SPI_D0_R1
PCH_SPI_D1_R1

VCC

CLK

@
@
@
@

IO3
IO0

128Mb Flash ROM

UC6

PCH_SPI_CS#1_R1

A A

PCH_SPI_D2_R1

1 2

RC42 0_0402_5%

@

1 2

RC43 33_0402_5%

@

PCH_SPI_CS#1_R2
PCH_SPI_D1_1_R
PCH_SPI_D2_1_R

@

1

/CS

2

IO1

3

IO2

4

GND

W25Q128FVSIQ_SO8

VCC

CLK

IO3
IO0

RPC1

PCH_SPI_D0_0_R

1 8

PCH_SPI_CLK_0_R

2 7

PCH_SPI_D1_0_R

3 6
4 5

33_0804_8P4R_5%

1 2

RC407 33_0402_5%

1 2

RC408 33_0402_5%

1 2

RC409 33_0402_5%

1 2

RC410 33_0402_5%

+3.3V_SPI

8

PCH_SPI_D3_0_R

7
6

PCH_SPI_D0_0_R

5

+3.3V_SPI

8

PCH_SPI_D3_1_R

7

PCH_SPI_CLK_1_R

6

PCH_SPI_D0_1_R

5

CC9

1 2

0.1U_0201_10V6K

CC10

@
1 2

0.1U_0201_10V6K

PCH_SPI_D3_1_R
PCH_SPI_CLK_1_R
PCH_SPI_D0_1_R
PCH_SPI_D1_1_R

+3.3V_SPI

@

@

@

@

@

@

SML0_SMBCLK

SML1_SMBCLK

MEM_SMBCLK

RC32 0_0402_5%

@

RC33 0_0402_5%
RC34 0_0402_5%
RC35 0_0402_5%
RC36 0_0402_5%
RC38 0_0402_5%
RC40 0_0402_5%

+3.3V_ALW_PCH

@

RC41 0_0402_5%

12
12
12
12
12
12
12

RF Request

CC316RF@ 82P_0402_50V8J

CC318@RF@ 33P_0402_50V8J

CC319@RF@ 33P_0402_50V8J

CC320@RF@ 33P_0402_50V8J

PCH_SPI_CS#1_R1

PCH_SPI_CS#1

PCH_SPI_D0_R1

PCH_SPI_D0

PCH_SPI_D1_R1

PCH_SPI_D1

PCH_SPI_CLK_R1

PCH_SPI_CLK

PCH_SPI_CS#0_R1

PCH_SPI_CS#0

PCH_SPI_D2_R1

PCH_SPI_D2

PCH_SPI_D3_R1

PCH_SPI_D3

12

1 2

1 2

1 2

1 2

Place close CPU side

ACES_50696-0200M-P01

22

GND_2

21

GND_1

20

20

19

19

18

18

17

17

16

16

15

15

14

14

13

13

12

12

11

11

10

10

9

9

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

JSPI1

CONN@

CLKRUN#

PCH_SMB_ALERT#

TLS C ONFIDENTIALITY

HIGH
LOW(DEFAULT)

WEAK INTERNAL 20K PD

GPP_C5

ESPI@

EC interface

HIGH
LOW(DEFAULT)

WEAK INTERNAL 20K PD

GPP_B23

RC317 150K_0402_5%

EXI BOOT STALL BYPASS

HIGH
LOW(DEFAULT)

WEAK INTERNAL PD

1 2

RC27 8.2K_0402_5%LPC@

+3.3V_ALW_PCH

1 2

RC23 2.2K_0402_5%

ENABLE
DISAB LE

+3.3V_ALW_PCH

1 2

RC25 4.7K_0402_5%

ESPI

LPC

+3.3V_ALW_PCH

1 2

ENABLED
DIABL ED

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.

5

4

3

2

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CPU (3/14)

CPU (3/14)

CPU (3/14)

LA-F292P

LA-F292P

LA-F292P

8 60Tuesday, November 14, 2017

8 60Tuesday, November 14, 2017

8 60Tuesday, November 14, 2017

1

1.0

1.0

1.0

5

smd.db-x7.ru

4

3

2

1

+3.3V_RUN

RC560

@

D D

RC282 100K_0402_5%@

RC237 10K_0402_5%

RC402 49.9K_0402_1%@
RC403 49.9K_0402_1%@

+3.3V_ALW_PCH

RC283 10K_0402_5%

RC330 49.9K_0402_1%@

RC331 49.9K_0402_1%@

C C

RC557 100K_0402_5%

@

RC558 100K_0402_5%

RTD3@

+3.3V_RUN

RC186 4.7K_0402_5%@

NO REBOOT STRAP

HIGH
LOW(DEFAULT)

Weak IPD

B B

+3.3V_ALW_PCH

RC184 8.2K_0402_5%@

PCH_3.3V_TS_EN

12

SIO_EXT_SCI#

12

LPSS_UART2_RXD

12

LPSS_UART2_TXD

12

SIO_EXT_WAKE#

12

LPSS_UART2_RXD

12

LPSS_UART2_TXD

12

PCH_TBT_PERST#

12

PCH_TBT_PERST#

12

NRB_BIT

12

No REBOOT

REBOOT ENABLE

GPP_B22

12

TPM_PIRQ#<38>

PCH_3.3V_TS_EN<30>

PCH_TBT_PERST#<23>

SBIOS_TX<37>

TS_I2C_SDA<30>
TS_I2C_SCL<30>

I2C1_SDA_TP<42>
I2C1_SCK_TP<42>

I2C2_SDA_ALS<45>

I2C2_SCL_ALS<45>

0_0201_5%

1 2

RC561

@

0_0201_5%

1 2

ONE_DIMM#
NRB_BIT

SIO_EXT_SCI#
GPP_B22
PCH_TBT_PERST#
TYPEC_CON_SEL1

TYPEC_CON_SEL2
LPSS_UART2_RXD

LPSS_UART2_TXD

I2C2_ALS_SDA
I2C2_ALS_CLK

+3.3V_RUN

12

RC513

2.2K_0402_5%

AN8
AP7
AP8
AR7

AM5
AN7
AP5
AN5

AB1
AB2

AB3
AD1

AD2
AD3
AD4

AH9

AH10
AH11

AH12

AF11
AF12

+3.3V_RUN

12

@

W4

U7
U6

U8
U9

RC512

2.2K_0402_5%

UC1F

CPU@

LPSS ISH

GPP_B15/GSPI0_CS#
GPP_B16/GSPI0_CLK
GPP_B17/GSPI0_MISO
GPP_B18/GSPI0_MOSI

GPP_B19/GSPI1_CS#
GPP_B20/GSPI1_CLK
GPP_B21/GSPI1_MISO
GPP_B22/GSPI1_MOSI

GPP_C8/UART0_RXD
GPP_C9/UART0_TXD
GPP_C10/UART0_RTS#
GPP_C11/UART0_CTS#

GPP_C20/UART2_RXD
GPP_C21/UART2_TXD
GPP_C22/UART2_RTS#
GPP_C23/UART2_CTS#

GPP_C16/I2C0_SDA
GPP_C17/I2C0_SCL

GPP_C18/I2C1_SDA
GPP_C19/I2C1_SCL

GPP_F4/I2C2_SDA
GPP_F5/I2C2_SCL

GPP_F6/I2C3_SDA
GPP_F7/I2C3_SCL

GPP_F8/I2C4_SDA
GPP_F9/I2C4_SCL

KBL-RU42_BGA1356

@

6

DMN63D8LDW-7_SOT363-6

5

3 4

QC4B

@

DMN63D8LDW-7_SOT363-6

BOOT BIOS Dest i nat i on(Bi t 10)

RC267@

RC268

ONE_DIMM#

LPC
SPI

1 2

12

TYPEC_CON_SEL1

TYPEC_CON_SEL2

HIGH
LOW(DEFAULT)

Internal 20k PD

+3.3V_RUN

10K_0402_5%

1 2

10K_0402_5%

12

A A

KBL-R U4+2

GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA

GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL

Sx_EXIT_HOLDOFF# / GPP_A12 / BM_BUSY# / ISH_GP6

+1.8V_RUN +1.8V_RUN

2

1

QC4A

@

RC555

@

10K_0402_5%

RC556

@

10K_0402_5%

Vendor

TYPEC_CON_SEL2TYPEC_CON_SEL1

JAE FOXCON
LOW

LOW

+1.8V_RUN

12

+3.3V_ALW_PCH+3.3V_ALW_PCH

1 2

12

LOW

HIGH

GPP_D5/ISH_I2C0_SDA
GPP_D6/ISH_I2C0_SCL

GPP_D7/ISH_I2C1_SDA
GPP_D8/ISH_I2C1_SCL

GPP_F10/I2C5_SDA/ISH_I2C2_SDA

GPP_F11/I2C5_SCL/ISH_I2C2_SCL

GPP_D16/ISH_UART0_CTS#/SML0BALERT#

12

RC510

2.2K_0402_5%

RC511

2.2K_0402_5%

@

10K_0402_5%

@

10K_0402_5%

HIGH HIGH

LOW

GPP_D15/ISH_UART0_RTS#

GPP_C12/UART1_RXD/ISH_UART1_RXD

GPP_C13/UART1_TXD/ISH_UART1_TXD
GPP_C14/UART1_RTS#/ISH_UART1_RTS#
GPP_C15/UART1_CTS#/ISH_UART1_CTS#

@

I2C2_ALS_SDA

@

I2C2_ALS_CLK

RC553

RC554

TBD TBD

HIGH

GPP_A18/ISH_GP0
GPP_A19/ISH_GP1
GPP_A20/ISH_GP2
GPP_A21/ISH_GP3
GPP_A22/ISH_GP4
GPP_A23/ISH_GP5

Rev_0.1

P2

GPP_D9

P3

GPP_D10

P4

GPP_D11

P1

GPP_D12

M4
N3

N1
N2

AD11
AD12

U1
U2
U3
U4

AC1
AC2
AC3
AB4

AY8
BA8
BB7
BA7
AY7
AW7
AP13

6 OF 20

MEM_INTERLEAVED

MEM_INTERLEAVED
AR_DET#

ISH_I2C0_SDA
ISH_I2C0_SCL

ISH_I2C1_SDA
ISH_I2C1_SCL

ISH_I2C2_SDA
ISH_I2C2_SCL

RTD3_CIO_PWR_EN

ISH_GP0_D
ISH_GP1_D
ISH_GP2_D
ISH_GP3_D

NB_MODE#_D
LID_CL#_NB_C
LID_CL#_TAB_C

ISH_GP0 for Main Accelerometer (LCD Sesnor Board)
ISH_GP1 for 2nd Accelerometer (MB)
ISH_GP2 for E-Compass (MB)
ISH_GP3 for ALS (LCD Sesnor Board)
ISH_GP4 for EC5105 (Tablet/NB mode)

NB_MODE#<36>

+3.3V_ALW_PCH +3.3V_ALW_PCH

RC371

@

10K_0402_5%

1 2

12

10K_0402_5%
RC372

ISH_I2C0_SDA <45>
ISH_I2C0_SCL <45>

ISH_I2C1_SDA <36,45>
ISH_I2C1_SCL <36,45>

ISH_I2C2_SDA <33>
ISH_I2C2_SCL <33>

9/24: Reserve for embedded locat i on ,r ef er I nt el P DG 0. 9

ISH_UART0_RXD <33>

ISH_UART0_TXD <33>
ISH_UART0_RTS# <33>

ISH_UART0_CTS# <33>

SIO_EXT_WAKE# <36>

RTD3_CIO_PWR_EN <23>
LCD_CBL_DET# <30>

ISH_GP0_D <45>
ISH_GP1_D <45>
ISH_GP2_D <45>
ISH_GP3_D <45>

@

RC504 0_0402_5%

@

RC505 0_0402_5%

Only for Kirkwood

WWAN

WLAN

12
12

LID_CL#_NB_D <45>
LID_CL#_TAB_D <45>

GPP_A GROUP is +1.8V

+1.8V_PRIM+3.3V_ALW

2

G

S

QC3

DIMM TYPE

Non-InterleaveLOW

12

RC506
10K_0402_5%

@

NB_MODE#_D

12

RC509
10K_0402_5%

12

RC507
100K_0402_5%

1 3

D

S TR BSS138W 1N SOT-323-3

1 2

RC508 0_0402_5%@

HIGH Interleave

RTD3_CIO_PWR_ENTPM_PIRQ#_R

ISH_I2C0_SDA
ISH_I2C0_SCL
ISH_I2C1_SDA
ISH_I2C1_SCL
LCD_CBL_DET#

ISH_I2C2_SDA
ISH_I2C2_SCL

ISH_GP0_D
ISH_GP1_D
ISH_GP2_D
ISH_GP3_D
NB_MODE#_D

AR_DET#

1 2

RC559 10K_0402_5%RTD3@

1 2

RC358 2.2K_0402_5%

1 2

RC359 2.2K_0402_5%

1 2

RC360 1K_0402_5%@

1 2

RC361 1K_0402_5%@

1 2

RC287 100K_0402_5%

1 2

RC363 1K_0402_5%@

1 2

RC362 1K_0402_5%@

1 2

RC365 10K_0402_5%@

1 2

RC364 10K_0402_5%@

1 2

RC501 10K_0402_5%@

1 2

RC502 10K_0402_5%@

1 2

RC349 10K_0402_5%@

RC400

@

10K_0402_5%

1 2

12

10K_0402_5%
RC401

+3.3V_ALW_PCH

+3.3V_RUN

+1.8V_RUN

AR_DET#

HIGH NON AR

LOW AR

DIMM Detect

HIGH
LOW

1 DIMM
2 DIMM

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.

5

4

3

2

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CPU (4/14)

CPU (4/14)

CPU (4/14)

LA-F292P

LA-F292P

LA-F292P

9 60Tuesday, November 14, 2017

9 60Tuesday, November 14, 2017

9 60Tuesday, November 14, 2017

1

1.0

1.0

1.0

5

smd.db-x7.ru

4

3

2

1

For AR, Kirkwood

UC1H

CPU@

PCIE / USB3 / SATA

D D

AR ----->

M.2 3030(WLAN) --->

C C

M.2 3042(SATA Cache
or/HCA)--->

M2 2280 SSD --->

B B

PCIE_PRX_DTX_N1<23>

PCIE_PRX_DTX_P1<23>
PCIE_PTX_DRX_N1<23>
PCIE_PTX_DRX_P1<23>

PCIE_PRX_DTX_N2<23>

PCIE_PRX_DTX_P2<23>
PCIE_PTX_DRX_N2<23>
PCIE_PTX_DRX_P2<23>

PCIE_PRX_DTX_N3<23>

PCIE_PRX_DTX_P3<23>
PCIE_PTX_DRX_N3<23>
PCIE_PTX_DRX_P3<23>

PCIE_PRX_DTX_N4<23>

PCIE_PRX_DTX_P4<23>
PCIE_PTX_DRX_N4<23>
PCIE_PTX_DRX_P4<23>

PCIE_PRX_DTX_N5<33>

PCIE_PRX_DTX_P5<33>
PCIE_PTX_DRX_N5<33>
PCIE_PTX_DRX_P5<33>

PCIE_PRX_DTX_N7<32>
PCIE_PRX_DTX_P7<32>
PCIE_PTX_DRX_N7<32>
PCIE_PTX_DRX_P7<32>

PCIE_PRX_DTX_N8<33>
PCIE_PRX_DTX_P8<33>
PCIE_PTX_DRX_N8<33>
PCIE_PTX_DRX_P8<33>

PCIE_PRX_DTX_N9<39>
PCIE_PRX_DTX_P9<39>
PCIE_PTX_DRX_N9<39>
PCIE_PTX_DRX_P9<39>

PCIE_PRX_DTX_N10<39>
PCIE_PRX_DTX_P10<39>
PCIE_PTX_DRX_N10<39>
PCIE_PTX_DRX_P10<39>

1 2

RC45 100_0402_1%

CPU_XDP_PRDY#<14>

CPU_XDP_PREQ#<14>

PCIE_PRX_DTX_N11<39>
PCIE_PRX_DTX_P11<39>
PCIE_PTX_DRX_N11<39>
PCIE_PTX_DRX_P11<39>
PCIE_PRX_DTX_N12<39>
PCIE_PRX_DTX_P12<39>
PCIE_PTX_DRX_N12<39>
PCIE_PTX_DRX_P12<39>

HDD_FALL_INT

PCIE_RCOMPN
PCIE_RCOMPP

H13

PCIE1_RXN/USB3_5_RXN

G13

PCIE1_RXP/USB3_5_RXP

B17

PCIE1_TXN/USB3_5_TXN

A17

PCIE1_TXP/USB3_5_TXP

G11

PCIE2_RXN/USB3_6_RXN

F11

PCIE2_RXP/USB3_6_RXP

D16

PCIE2_TXN/USB3_6_TXN

C16

PCIE2_TXP/USB3_6_TXP

H16

PCIE3_RXN

G16

PCIE3_RXP

D17

PCIE3_TXN

C17

PCIE3_TXP

G15

PCIE4_RXN

F15

PCIE4_RXP

B19

PCIE4_TXN

A19

PCIE4_TXP

F16

PCIE5_RXN

E16

PCIE5_RXP

C19

PCIE5_TXN

D19

PCIE5_TXP

G18

PCIE6_RXN

F18

PCIE6_RXP

D20

PCIE6_TXN

C20

PCIE6_TXP

F20

PCIE7_RXN/SATA0_RXN

E20

PCIE7_RXP/SATA0_RXP

B21

PCIE7_TXN/SATA0_TXN

A21

PCIE7_TXP/SATA0_TXP

G21

PCIE8_RXN/SATA1A_RXN

F21

PCIE8_RXP/SATA1A_RXP

D21

PCIE8_TXN/SATA1A_TXN

C21

PCIE8_TXP/SATA1A_TXP

E22

PCIE9_RXN

E23

PCIE9_RXP

B23

PCIE9_TXN

A23

PCIE9_TXP

F25

PCIE10_RXN

E25

PCIE10_RXP

D23

PCIE10_TXN

C23

PCIE10_TXP

F5

PCIE_RCOMPN

E5

PCIE_RCOMPP

D56

PROC_PRDY#

D61

PROC_PREQ#

BB11

GPP_A7/PIRQA#

E28

PCIE11_RXN/SATA1B_RXN

E27

PCIE11_RXP/SATA1B_RXP

D24

PCIE11_TXN/SATA1B_TXN

C24

PCIE11_TXP/SATA1B_TXP

E30

PCIE12_RXN/SATA2_RXN

F30

PCIE12_RXP/SATA2_RXP

A25

PCIE12_TXN/SATA2_TXN

B25

PCIE12_TXP/SATA2_TXP

KBL-RU42_BGA1356

KBL-R U4+2

SSIC / USB3

USB3_2_RXN/SSIC_RXN

USB3_2_RXP/SSIC_RXP
USB3_2_TXN/SSIC_TXN

USB3_2_TXP/SSIC_TXP

USB2

USB2_VBUSSENSE

GPP_E9/USB2_OC0#
GPP_E10/USB2_OC1#
GPP_E11/USB2_OC2#
GPP_E12/USB2_OC3#

GPP_E4/DEVSLP0
GPP_E5/DEVSLP1
GPP_E6/DEVSLP2

GPP_E0/SATAXPCIE0/SATAGP0
GPP_E1/SATAXPCIE1/SATAGP1
GPP_E2/SATAXPCIE2/SATAGP2

GPP_E8/SATALED#

Rev_0.1

USB3_1_RXN
USB3_1_RXP
USB3_1_TXN
USB3_1_TXP

USB3_3_RXN
USB3_3_RXP
USB3_3_TXN
USB3_3_TXP

USB3_4_RXN
USB3_4_RXP
USB3_4_TXN
USB3_4_TXP

USB2N_1
USB2P_1

USB2N_2
USB2P_2

USB2N_3
USB2P_3

USB2N_4
USB2P_4

USB2N_5
USB2P_5

USB2N_6
USB2P_6

USB2N_7
USB2P_7

USB2N_8
USB2P_8

USB2N_9
USB2P_9

USB2N_10
USB2P_10

USB2_COMP

USB2_ID

8 OF 20

H8
G8
C13
D13

J6
H6
B13
A13

J10
H10
B15
A15

E10
F10
C15
D15

AB9
AB10

AD6
AD7

AH3
AJ3

AD9
AD10

AJ1
AJ2

AF6
AF7

AH1
AH2

AF8
AF9

AG1
AG2

AH7
AH8

AB6
AG3
AG4

A9
C9
D9
B9

J1
J2
J3

H2
H3
G4

H1

USBCOMP
USB2_ID

USB2_VBUSSENSE

USB_OC2#
USB_OC3#

SATAGP0
M3042_PCIE#_SATA

m2280_PCIE_SATA#

SATALED#

Reserve

USB3_PRX_DTX_N1 <40>

USB3_PRX_DTX_P1 <40>
USB3_PTX_DRX_N1 <40>
USB3_PTX_DRX_P1 <40>

USB3_PRX_DTX_N2 <32>

USB3_PRX_DTX_P2 <32>
USB3_PTX_DRX_N2 <32>
USB3_PTX_DRX_P2 <32>

USB3_PRX_DTX_N3 <41>

USB3_PRX_DTX_P3 <41>
USB3_PTX_DRX_N3 <41>
USB3_PTX_DRX_P3 <41>

USB3_PRX_DTX_N4 <31>

USB3_PRX_DTX_P4 <31>
USB3_PTX_DRX_N4 <31>
USB3_PTX_DRX_P4 <31>

USB20_N1 <26>
USB20_P1 <26>

USB20_N2 <41>
USB20_P2 <41>

USB20_N3 <25>
USB20_P3 <25>

USB20_N4 <33>
USB20_P4 <33>

USB20_N5 <30>
USB20_P5 <30>

USB20_N6 <31>
USB20_P6 <31>

USB20_N7 <33>
USB20_P7 <33>

USB20_N8 <30>
USB20_P8 <30>

USB20_N9 <40>
USB20_P9 <40>

USB20_N10 <38>
USB20_P10 <38>

1 2

RC44 113_0402_1%

@

1 2

RC337 0_0402_5%

1 2

RC338 1K_0402_5%

USB_OC0# <40>
USB_OC1# <41>

M3042_DEVSLP <33>
M2_DEVSLP <39>

M3042_PCIE#_SATA <36>

m2280_PCIE_SATA# <39>

SATALED# <33,39,43>

-----> Ext USB3 Port 1 Charge

-----> M.2 3042(LTE)

-----> Ext USB3 Port 2

-----> Card Reader RTS5330

-----> Typce-C port1(AR,Front Side)

-----> Ext USB Port 2(LEFT)

-----> Typce-C port2(AR,Rear Side)

-----> M2 3042(WWAN)

-----> Camera

-----> Card Reader RTS5330

-----> M.2 3030(BT)

-----> LCD Touch

-----> Ext USB Port 1 Charge(RIGHT)

-----> USH

USB_OC1#
USB_OC3#
USB_OC0#
USB_OC2#

NEED DOUBLE CHECK

M2280_PCIE_SATA#

SATAGP0
SATALED#

M3042_PCIE#_SATA

M3042_PCIE#_SATA

+3.3V_ALW_PCH

10K_8P4R_5%

1

8

2

7

3

6

4 5

RPC3

RPC4

8
7
6

+3.3V_RUN

10K_8P4R_5%

1
2
3
4 5

1 2

RC551 10K_0402_5%

1 2

RC552@ 10K_0402_5%

1.8V?

HDD_FALL_INT

1 2

RC370@ 10K_0402_5%

12/17:INT1 is PP mode, depop RC370,double check.

+1.8V_RUN

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.

5

4

3

2

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CPU (5/14)

CPU (5/14)

CPU (5/14)

LA-F292P

LA-F292P

LA-F292P

10 60Tuesday, November 14, 2017

10 60Tuesday, November 14, 2017

10 60Tuesday, November 14, 2017

1

1.0

1.0

1.0

5

smd.db-x7.ru

4

3

2

1

UC1J

CPU@

CLK_PCIE_N0<33>

WWAN--->

WLAN--->

D D

WIGIG--->

M.2 SDD--->

LAN--->

AR --->

+3.3V_ALW_DSW

+1.0V_VCCST

C C

+3.3V_ALW_PCH

10/6 depop, prevent singal step.

H_CPUPWRGD VCCST_PWRGD

100P_0402_50V8J

12

B B

+3.3V_1.8V_PGPPA

CLK_PCIE_P0<33>

CLKREQ_PCIE#0<33>

CLK_PCIE_N1<33>
CLK_PCIE_P1<33>

CLKREQ_PCIE#1<33>

+3.3V_RUN

CLKREQ_PCIE#2_R<23>

CLK_PCIE_N3<39>
CLK_PCIE_P3<39>

CLKREQ_PCIE#3<39>

+3.3V_RUN

CLK_PCIE_N5<23>
CLK_PCIE_P5<23>

CLKREQ_PCIE#5<23>

LAN_WAKE#

RC323 10K_0402_5%

RC67 1K_0402_5%

RC71 1K_0402_5%

RC411 10K_0402_5%@

CC300ESD@

T9

12

PCH_PCIE_WAKE#

12

VCCST_PWRGD

12

ME_SUS_PWR_ACK

12

RC74 10K_0402_5%@

PCH_PWROK

12

100P_0402_50V8J

12

ESD Request:place near CPU side

@

PAD~D

VCCST_PWRGD<14,36,37>

ME_SUS_PWR_ACK<36>

1 2

RC550 1K_0402_5%@

CC301ESD@

SUSACK#<36>

+3.3V_RUN

+3.3V_RUN

+3.3V_RUN

+3.3V_RUN

SUSACK#_R

@RF@

RC373 0_0402_5%

RC189 10K_0402_5%

@RF@

RC374 0_0402_5%

RC47 10K_0402_5%

RC50 10K_0201_1%@

@RF@

RC59 10K_0402_5%

RC51 10K_0402_5%@

@RF@

RC190 10K_0402_5%

PCH_PLTRST#

RC77 1K_0402_5%@
RC78 60.4_0402_1%

RC444 0_0402_5%@

12

RC376 0_0402_5%

12

RC378 0_0402_5%

@

RC244 0_0402_5%

UC7

TC7SH08FU_SSOP5~D

PCH_RSMRST#_AND<14,42>

1 2
1 2

1 2
1 2

RC443 0_0402_5%@

PCH_PCIE_WAKE#<23,36,37>

12
12

12
12

CLKREQ_PCIE#2_R

12
12

12
12

1 2

+3.3V_ALW_PCH

5

1

P

B

2

A

G

3

SYS_PWROK<14,36>
PCH_PWROK<53>

PCH_DPWROK<36>

LAN_WAKE#<36>

3.3V_CAM_EN#<30>

RC311 10K_0402_5%

CLKREQ_PCIE#0_R

CLKREQ_PCIE#1_R

CLKREQ_PCIE#3_R

CLKREQ_PCIE#4_R

CLKREQ_PCIE#5_R

4

O

PCH_PLTRST#
SYS_RESET#

PCH_RSMRST#_AND

H_CPUPWRGDH_CPUPWRGD_R
VCCST_PWRGD_CPU

ME_SUS_PWR_ACK_R

RC215

POP

NO Support Deep sleep

DE-POP

PCH_DPWROK PCH_RSMRST#_AND

A A

1

2

RC215 0_0402_5%

NDS3@

100K_0402_1%

0.01UF_0402_25V7K

12

@

RC220

CC266

Support Deep sleep

1 2

12

RC75
10K_0402_5%

XDP_DBRESET#<14>

+3.3V_RUN

RC225@ 8.2K_0402_5%
RC227@ 8.2K_0402_5%

D42
C42

AR10

B42
A42
AT7

D41
C41
AT8

D40
C40

AT10

B40
A40

AU8

E40
E38

AU7

PCH_PLTRST#_EC <37>

PCH_PLTRST#_AND

12

RC65

@

100K_0402_5%

PCH_PWROK

SUSACK#_R

12

XDP_DBRESET#

12
12

CLKOUT_PCIE_N0
CLKOUT_PCIE_P0
GPP_B5/SRCCLKREQ0#

CLKOUT_PCIE_N1
CLKOUT_PCIE_P1
GPP_B6/SRCCLKREQ1#

CLKOUT_PCIE_N2
CLKOUT_PCIE_P2
GPP_B7/SRCCLKREQ2#

CLKOUT_PCIE_N3
CLKOUT_PCIE_P3
GPP_B8/SRCCLKREQ3#

CLKOUT_PCIE_N4
CLKOUT_PCIE_P4
GPP_B9/SRCCLKREQ4#

CLKOUT_PCIE_N5
CLKOUT_PCIE_P5
GPP_B10/SRCCLKREQ5#

KBL-RU42_BGA1356

PCH_PLTRST#

PCH_PLTRST#_AND

PCH_PLTRST#_AND <23,30,33,38,39>

UC1K

CPU@

AN10

GPP_B13/PLTRST#

B5

SYS_RESET#

AY17

RSMRST#

A68

PROCPWRGD

B65

VCCST_PWRGD

B6

SYS_PWROK

BA20

PCH_PWROK

BB20

DSW_PWROK

AR13

GPP_A13/SUSWARN#/SUSPWRDNACK

AP11

GPP_A15/SUSACK#

BB15

WAKE#

AM15

GPD2/LAN_WAKE#

AW17

GPD11/LANPHYPC

AT15

GPD7/RSVD

KBL-RU42_BGA1356

1 2

@

RC290 0_0402_5%

+3.3V_RUN

1

ME_RESET#

2

if pop UC12, RC291 also need pop(74AHC1G09GW is OD output)

5

4

KBL-R U4+2

CLOCK SIGNALS

1 2

RC60 0_0402_5%@

1 2

@

RC325 0_0402_5%

VCCDSW_EN_GPIO<18>

VCCDSW_EN<36>

ALW_PWRGD_3V_5V<42,48>

SYSTEM POWER MANAGEMENT

5

P

B

4

O

A

G

UC12@

74AHC1G09GW_TSSOP5

3

@

1 2

0_0402_5%

KBL-R U4+2

SYS_RESET#_R

Rev_0.1

KBL-U / KBL-R U4+2

RSVD_E3/XTAL24_IN

RSVD_C7/XTAL24_OUT

XTAL24_IN/NC_2

XTAL24_OUT/NC_1

CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P

GPD8/SUSCLK

XCLK_BIASREF

RTCX1
RTCX2

SRTCRST#

RTCRST#

10 OF 20

RC445

GPP_B12/SLP_S0#

GPD10/SLP_S5#

GPD9/SLP_WLAN#

GPD3/PWRBTN#

GPD1/ACPRESENT

GPD0/BATLOW#

GPP_B11/EXT_PWR_GATE#

GPP_B2/VRALERT#

1 2

RC224 1K_0402_5%

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.

XTAL24_IN_U42_CPU XTAL24_IN_U42

E3

XTAL24_OUT_U42_CPU

C7

XTAL24_IN_U22_CPU

E37

XTAL24_OUT_U22_CPU

E35

CLK_ITPXDP_N

F43

CLK_ITPXDP_P

E43
BA17

SUSCLK

XCLK_BIASREF

E42

PCH_RTCX1

AM18

PCH_RTCX2

AM20
AN18

SRTCRST#

AM16

PCH_RTCRST#

PLTRST_TPM# <38>

RC297 0_0402_5%@
RC298 0_0402_5%@

PCH_RTCRST# <36>

CMOS1 must take care short & touch risk on layout placement

SIO_SLP_SUS#

DC1

NDS3@

2 1

RB751S-40 SOD-523

NDS3@

RB751S-40 SOD-523

DC2

VCCDSW_EN_Q

21

Close to CPU

1 2

RC417 33_0402_5%U42@

1 2

RC418 33_0402_5%U42@

1 2

RC419 0_0402_5%U22@

1 2

RC420 0_0402_5%U22@

1 2
1 2

SUSCLK <33,39>

1 2

RC52 2.7K_0402_1%

1 2

RC324 59_0402_1%@

546765_546765_2014WW48_Skylake_MOW_Rev_1_0

1 2

RC56 20K_0402_5%

1 2

CC24 1U_0402_6.3V6K

1 2

RC57 20K_0402_5%

1 2

CC25 1U_0402_6.3V6K

1

1

2

SHORT PADS~D

@

CMOS1

@DS3@

RC441

1 2

0_0402_5%

RC442

NDS3@

1 2

0_0402_5%

RC439RC440

Support DS3

No Support DS3

Rev_0.1

GPD4/SLP_S3#
GPD5/SLP_S4#

SLP_SUS#
SLP_LAN#

GPD6/SLP_A#

GPP_A11/PME#

INTRUDER#

11 OF 20

+3.3V_RUN

1 2

3

AT11
AP15
BA16
AY16

AN15
AW15
BB17
AN16

BA15
AY15
AU13

AU11
AP16

AM10
AM11

RC291

10K_0402_5%

@

SYS_RESET#

SIO_SLP_S0#

PCH_BATLOW#

PME#
INTRUDER#

MPHYP_PWR_EN
VRALERT#

'V' mean POP, 'X' mean DE-POP

SIO_SLP_S0# <17,38,51>
SIO_SLP_S3# <23,36,37>
SIO_SLP_S4# <17,36,49,52>
SIO_SLP_S5# <36>

SIO_SLP_SUS# <36>
SIO_SLP_LAN# <36>
SIO_SLP_WLAN# <36,44>
SIO_SLP_A# <36>

SIO_PWRBTN# <14,36>

AC_PRESENT <36>

@

T115

PAD~D

connect to VCCMPHYGTAON_1P0 enable pin

XTAL24_OUT_U42
XTAL24_IN_U22
XTAL24_OUT_U22

CLK_ITPXDP_N_R <14>
CLK_ITPXDP_P_R <14>

+1.0V_CLK5

For Skylake, pop RC52,depop RC324
For Cannonlake, pop RC324,depop RC52

+RTC_CELL_PCH

2

PCH_PRIM_EN <17,44,50,51,52>

X

V

SUSCLK

SYS_RESET#

0.1U_0402_25V6

@ESD@

12

CC302

ESD Request:place near CPU side

2

XTAL24_IN_U22
XTAL24_OUT_U22

XTAL24_IN_U42
XTAL24_OUT_U42

VVVXXX

RC48 1K_0402_5%@

For UMA CONFIG

For KBL-R U22

1M_0402_1%

U22@

RC46

1 2

For Skylake,YC1 24 MHz (50 Ohm ESR)
For Cannonlake,YC1 38.4 MHz (30 Ohm ESR)

546765_546765_2014WW48_Skylake_MOW_Rev_1_0

3

4

1

2

For KBL-R U42

U42@

1M_0402_1%

RC415

1 2

For Skylake,YC3 24 MHz (50 Ohm ESR)

PCH_RTCX1
PCH_RTCX2

RC54
10M_0402_5%

1 2

1 2

@

RC296 0_0402_5%

8/21 can change to 10K for merge to RP

RC442RC441RC215RE536

VVXX

1 2

+3.3V_ALW_PCH

+3.3V_ALW

+3.3V_ALW

PCH_BATLOW#
AC_PRESENT

INTRUDER#

MPHYP_PWR_EN

VRALERT#

SIO_SLP_LAN#

POWER_SW#_MB<37,43>

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

3

4

1

2

12

ESR MAX=50k ohm

PCH_RTCX2_R

1 2

RC72 8.2K_0402_5%

1 2

RC243 10K_0402_5%

1 2

RC69 1M_0402_5%

1 2

RC387 100K_0201_5%@

1 2

RC73 10K_0402_5%

@

1 2

RC344 10K_0402_5%@

1 2

RC68 10K_0402_5%@

SIO_SLP_S3#
SIO_SLP_S5#

SIO_SLP_S4#
SIO_SLP_A#

PCH_RTCRST#

SYS_RESET#
SIO_SLP_S0#

CPU (6/14)

CPU (6/14)

CPU (6/14)

LA-F292P

LA-F292P

LA-F292P

1

CC21

U22@

1 2

15P_0402_50V8J

YC1

U22@

24MHZ_12PF_X3G024000DC1H

CC22

U22@

1 2

15P_0402_50V8J

U42@

CC338

1 2

12P_0402_50V8J

U42@

YC3

24MHZ_12PF_X3G024000DC1H

U42@

CC339

1 2

12P_0402_50V8J

CC23

1 2

15P_0402_50V8J

YC2

32.768KHZ_12.5PF_9H03200042

CC26

1 2

12P_0402_50V8J

+3.3V_ALW_DSW

+RTC_CELL_PCH

+3.3V_ALW_PCH

+3.3V_ALW

JAPS1

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

GND

20

GND

CVILU_CF4218FH0R0-05-NH

CONN@

11 60Tuesday, November 14, 2017

11 60Tuesday, November 14, 2017

11 60Tuesday, November 14, 2017

1.0

1.0

1.0

5

smd.db-x7.ru

4

3

2

+1.0V_VCCSTG

1

PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS

CPU_XDP_TCLK XDP_JTAGX

1 2

RC86 51_0402_5%@

Service Mode Switch:
Add a switch to ME_FWP signal to unlock the ME region and
allow the ent ir e r egi on of t he S PI f l ash to be updat ed us i ng FPT.

+3.3V_ALW_PCH

ME_FWP PCH has internal 20K PD.
(suspend power rail)

FLASH DESCRIPTOR SECURITY OVERRIDE

LOW = ENABLE (DEFAULT) -->Pin3 & Pin2 short
HIGH = DISABLE (ME can update) -->Pin1 & Pin2 short

CAM_MIC_CBL_DET# <30>

TBT_CIO_PLUG_EVENT# <23>

CONTACTLESS_DET# <38>

HOST_SD_WP# <31>

AUD_PWR_EN <35>
SPK_DET# <35>

0.1U_0402_25V6

@ESD@

12

CC304

2

CPU MISC

HDA_SDIN0

CC332

RF@

2.2P_0402_50V8C

KBL-R U4+2

KBL-R U4+2

1

2

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.

Rev_0.1

JTAG

PROC_TCK

PROC_TDI
PROC_TDO
PROC_TMS

PROC_TRST#

PCH_JTAG_TCK

PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS

PCH_TRST#

JTAGX

4 OF 20

GPP_A17/SD_PWR_EN#/ISH_GP7

HDA_SDOUT

CC333

RF@

2.2P_0402_50V8C

3

CPU_XDP_TCLK

B61

CPU_XDP_TDI

D60

CPU_XDP_TDO

A61

CPU_XDP_TMS

C60

CPU_XDP_TRST#

B59

PCH_JTAG_TCK

B56

PCH_JTAG_TDI

D59

PCH_JTAG_TDO

A56

PCH_JTAG_TMS

C59

CPU_XDP_TRST#

C61

XDP_JTAGX

A59

SDIO / SDXC

GPP_G0/SD_CMD
GPP_G1/SD_DATA0
GPP_G2/SD_DATA1
GPP_G3/SD_DATA2
GPP_G4/SD_DATA3

GPP_G5/SD_CD#
GPP_G6/SD_CLK

GPP_G7/SD_WP

GPP_A16/SD_1P8_SEL

SD_RCOMP

GPP_F23

1 2

RC87 1K_0402_5%@

Rev_0.1

7 OF 20

CPU_XDP_TCLK <14>
CPU_XDP_TDI <14>
CPU_XDP_TDO <14>
CPU_XDP_TMS <14>
CPU_XDP_TRST# <14>

PCH_JTAG_TCK <14>
PCH_JTAG_TDI <14>
PCH_JTAG_TDO <14>
PCH_JTAG_TMS <14>

+1.0V_VCCSTG

AB11
AB13

TBT_CIO_PLUG_EVENT#

AB12
W12

CONTACTLESS_DET#

W11

HOST_SD_WP#

W10

AUD_PWR_EN

W8

SPK_DET#

W7
BA9

BB9

SD_RCOMP

AB7

AF13

PCH_JTAG_TDO PCH_JTAG_TDI XDP_JTAGX

0.1U_0402_25V6

@ESD@

12

CC303

1 2

RC96 200_0402_1%

ESD request,Place near CPU side.

UC1D

CPU@

D63

CATERR#

A54

PECI

C65

PROCHOT#

C63

THERMTRIP#

A65

SKTOCC#

C55

BPM#[0]

D55

BPM#[1]

B54

BPM#[2]

C56

BPM#[3]

A6

GPP_E3/CPU_GP0

A7

GPP_E7/CPU_GP1

BA5

GPP_B3/CPU_GP2

AY5

GPP_B4/CPU_GP3

AT16

PROC_POPIRCOMP

AU16

PCH_OPIRCOMP

H66

OPCE_RCOMP

H65

OPC_RCOMP

KBL-RU42_BGA1356

UC1G

CPU@

AUDIO

HDA_SYNC/I2S0_SFRM
HDA_BLK/I2S0_SCLK
HDA_SDO/I2S0_TXD
HDA_SDI0/I2S0_RXD
HDA_SDI1/I2S1_RXD
HDA_RST#/I2S1_SCLK
GPP_D23/I2S_MCLK
I2S1_SFRM
I2S1_TXD

GPP_F1/I2S2_SFRM
GPP_F0/I2S2_SCLK
GPP_F2/I2S2_TXD
GPP_F3/I2S2_RXD

GPP_D19/DMIC_CLK0
GPP_D20/DMIC_DATA0

GPP_D17/DMIC_CLK1
GPP_D18/DMIC_DATA1

GPP_B14/SPKR

KBL-RU42_BGA1356

1

2

D D

+1.0V_VCCST

RC79 49.9_0402_1%@

RC80 1K_0402_5%

+1.0V_VCCSTG

RC83 1K_0402_5%

+3.3V_RUN

C C

B B

RC278 10K_0402_5%
RC272 10K_0402_5%@
RC279 10K_0402_5%
RC345 100K_0402_5%
RC292 10K_0402_5%

+3.3V_ALW_PCH

RC346 10K_0402_5%

RC288 10K_0402_5%

+3.3V_ALW_PCH +3.3V_ALW_PCH

RC183 8.2K_0402_5%@

12
12

12

RPC5

1

8

2

7

3

6

45

10K_8P4R_5%

12
12
12
12
12

12

12

CC334

RF@

82P_0402_50V8J

Close to RC94

12

H_CATERR#
H_THERMTRIP#

PROCHOT#

TOUCHPAD_INTR#
CAM_MIC_CBL_DET#

CONTACTLESS_DET#
TOUCH_SCREEN_PD#

AUD_PWR_EN
IR_CAM_DET#
HOST_SD_WP#

SIO_EXT_SMI#

KB_DET#

HDA_SYNC_R<35>

HDA_BIT_CLK_R<35>

HDA_SDOUT_R<35>

HDA_RST#_R<35>

CC27

RF@

47P_0402_50V8J

Close to RC93

HDA_SDOUT_R

1

2

SPKR

TOUCH_SCREEN_PD# PU changes to Module Side
(Not confirm yet?) 20160311

ME_FWP_SW

HDA_BIT_CLK_R

1

2

PECI_EC<36>

PROCHOT#<36,53,56>

H_THERMTRIP#<37>

1 2

RC92 33_0402_5%

1 2

RC93 33_0402_5%EMI@

1 2

RC94 33_0402_5%

1 2

RC223 1K_0402_5%

1 2

RC95 33_0402_5%

RC187 4.7K_0402_5%@

RC84 499_0402_1%

T10
T11

TOUCH_SCREEN_PD#<30>
TOUCHPAD_INTR#<36,42>

TOUCH_SCREEN_DET#<30>

12

IR_CAM_DET#<30>

PANEL_SIZE_DET<30>

HDA_SDOUT

12

1 2

XDP_OBS0_R<14>
XDP_OBS1_R<14>

@

PAD~D

@

PAD~D

12

RC88

49.9_0402_1%

KB_DET#<42>

SPKR<35>

RC89

HDA_SYNC
HDA_BIT_CLK
HDA_SDOUT

HDA_SDIN0<35>

HDA_RST#

TOP SWAP STRAP

A A

HIGH
LOW(DEFAULT)

Internal 20k PD

ENABLE
DISAB LE

5

Flash Descriptor Security override

HIGH
LOW(DEFAULT)

DISABLE

ENABLE

PROCHOT#_R
H_THERMTRIP#

XDP_OBS2_R
XDP_OBS3_R

SIO_EXT_SMI#
TOUCHPAD_INTR#

CPU_POPIRCOMP
PCH_POPIRCOMP

EDRAM_OPIO_RCOMP

EOPIO_RCOMP

12

12

RC90

49.9_0402_1%

49.9_0402_1%

IR_CAM_DET#
PANEL_SIZE_DET

KB_DET#

4

H_CATERR#

RC91

49.9_0402_1%

BA22

AY22
BB22
BA21

AY21

AW22

J5

AY20

AW20

AK7
AK6
AK9

AK10

H5
D7

D8
C8

AW5

RF Request. Place near CPU side (Intel MOW)

HDA_RST#

1

2

CC331

RF@

2.2P_0402_50V8C

1 2

RC81 51_0402_5%

1 2

RC82 100_0402_5%

1 2

RC130 51_0402_5%

@

RC328 0_0402_5%

RC222

@

1K_0402_5%

1 2

12

12

ME_FWP

PT,ST pop RC222 and SW1; MP pop RC221

ME_FWP<36>

0.1U_0402_25V6

@ESD@

CC305

ME_FWP_SW

12

@

RC2210_0402_5%

ME_FWP_SW

PANEL_SIZE_DET

H_THERMTRIP#

0.1U_0402_25V6

@ESD@

12

CC312

SW1

@

1
2
3

4

G

5

G

SSAL120100_3P

1 2

PROCHOT#

0.1U_0402_25V6

12

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CPU (7/14)

CPU (7/14)

CPU (7/14)

LA-F292P

LA-F292P

LA-F292P

1

@ESD@

CC310

+3.3V_ALW_PCH

RC50310K_0402_5%

12 60Tuesday, November 14, 2017

12 60Tuesday, November 14, 2017

12 60Tuesday, November 14, 2017

1.0

1.0

1.0

5

smd.db-x7.ru

D D

4

CFG[0..19]<14>

3

2

1

CFG[2][5][6][7] for SKYLAKE-H CPU CFG strap pin

12

RC113 10K_0402_1%@

CFG0

RC112 10K_0402_1%@
RC110 10K_0402_1%@

12
12

Stall reset sequence

HIGH(DEFAULT )
LOW

C C

RC109 1K_0402_5%

eDP enable

HIGH(DEFAULT )
LOW

B B

No stall(Normal Operat i on)
sta ll

12

CFG4

Disa bled
Enabled

+1.0V_PRIM_XDP

RC114 49.9_0402_1%
RC115 1.5K_0402_5%

ITP_PMODE<14>

@

T16

PAD~D

@

T17

PAD~D

1 2

U42@

RC436 0_0402_5%

CFG_RCOMP

12

ITP_PMODE

12

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15

CFG16
CFG17

CFG18
CFG19

UC1S

E68

CFG[0]

B67

CFG[1]

D65

CFG[2]

D67

CFG[3]

E70

CFG[4]

C68

CFG[5]

D68

CFG[6]

C67

CFG[7]

F71

CFG[8]

G69

CFG[9]

F70

CFG[10]

G68

CFG[11]

H70

CFG[12]

G71

CFG[13]

H69

CFG[14]

G70

CFG[15]

E63

CFG[16]

F63

CFG[17]

E66

CFG[18]

F66

CFG[19]

E60

CFG_RCOMP

E8

ITP_PMODE

AY2

RSVD_AY2

AY1

RSVD_AY1

D1

RSVD_D1

D3

RSVD_D3

K46

RSVD_K46

K45

RSVD_K45

AL25

RSVD_AL25

AL27

RSVD_AL27

C71

RSVD_C71

B70

RSVD_B70

F60

RSVD_F60

A52

RSVD_A52

BA70

RSVD_TP_BA70

BA68

RSVD_TP_BA68

J71

RSVD_J71

J68

RSVD_J68

F65

VSS_F65

G65

VSS_G65

F61

RSVD_F61

E61

RSVD_E61

KBL-RU42_BGA1356

CPU@

KBL-R U4+2

RESERVED SIGNALS-1

Rev_0.1

RSVD_TP_BB68
RSVD_TP_BB69

RSVD_TP_AK13
RSVD_TP_AK12

RSVD_BB2
RSVD_BA3

RSVD_D5
RSVD_D4
RSVD_B2
RSVD_C2

RSVD_B3
RSVD_A3

RSVD_AW1

RSVD_E1
RSVD_E2

RSVD_BA4
RSVD_BB4

RSVD_A4
RSVD_C4

RSVD_A69

RSVD_B69
RSVD_AY3
RSVD_D71

RSVD_C70
RSVD_C54

RSVD_D54

VSS_AY71

ZVM#

RSVD_TP
RSVD_TP

MSM#

PROC_SELECT#

19 OF 20

UC1T

BB68
BB69

AK13
AK12

BB2
BA3

AU5

TP5

AT5

TP6

D5
D4
B2
C2

B3
A3

AW1
E1

E2
BA4

BB4
A4

C4
BB5

TP4

A69
B69

AY3
D71

C70
C54

D54
AY4

TP1

BB3

TP2

AY71
AR56

AW71
AW70

AP56
C64

@

T12

PAD~D

@

T13

PAD~D

@

T14

PAD~D

@

T15

PAD~D

@

T128

PAD~D

@

T129

PAD~D

@

T130

PAD~D

@

T126

PAD~D

@

T127

PAD~D

@

T113

PAD~D

@

T114

PAD~D

1 2

RC120 100K_0402_5%@

For Skylake , RC120 depop
For Cannonlake, RC120 pop

546765_546765_2014WW48_Skylake_MOW_Rev_1_0

1/5 2014WW52 MOW reserve to support
Cannonlake-U PCH compatibility

close UC1.U11/U12 and <400mil

1 2

RC313 0_0402_5%@

+VCC_1P8+1.8V_PRIM

ZVM# for SKYLAKE-U 2+3e

MSM# for SKYLAKE-U 2+3e

+1.0V_VCCST

AW69
AW68

AU56

AW48

U12
U11

1

2

@

H11

CC222

1U_0402_6.3V6K

KBL-RU42_BGA1356

RSVD_AW69
RSVD_AW68
RSVD_AU56
RSVD_AW48

RSVD_U12
RSVD_U11
RSVD_H11

SPARE

Rev_0.1

RSVD_F6

RSVD_C11
RSVD_B11
RSVD_A11
RSVD_D12
RSVD_C12
RSVD_F52

20 OF 20

F6
C11

B11
A11
D12
C12
F52

KBL-R U4+2

CPU@

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.

5

4

3

2

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CPU (8/14)

CPU (8/14)

CPU (8/14)

LA-F292P

LA-F292P

LA-F292P

13 60Tuesday, November 14, 2017

13 60Tuesday, November 14, 2017

13 60Tuesday, November 14, 2017

1

1.0

1.0

1.0

+1.0V_PRIM

smd.db-x7.ru

@

1 2

RC216 0_0603_5%

+1.0V_PRIM_XDP +1.0V_PRIM_XDP

0.1U_0201_10V6K

0.1U_0201_10V6K

@

CC28

1

1

2

2

D D

Place near
JXDP1

VCCST_PWRGD<11,36,37>

PCH_RSMRST#_AND<11,42>

+1.0VS_VCCIO

C C

+1.0V_VCCST

+3.3V_RUN

+1.0V_PRIM_XDP

5

+1.0V_PRIM_XDP

@

CC29

XDP_OBS0_R<12>
XDP_OBS1_R<12>

RC123 1K_0402_5%@

RC124CXDP@

PCH_SPI_DO_XDP<8>

SYS_PWROK<11,36>

RC132 150_0402_5%

RC218 150_0402_5%@

RC219 10K_0402_5%@

RC137 3K_0402_5%

RC138 51_0402_5%@

RC239 0_0402_5%CXDP@
RC240 0_0402_5%CXDP@

RC5 need to close to JCPU1

1 2
1 2

1K_0402_5%

12

12

12

12

12

FIVR_EN
CFG0

RC217 0_0402_5%@
RC126 1K_0402_5%@
RC128 0_0402_5%CXDP@
RC129 0_0402_5%@

DDR_XDP_WAN_SMBDAT<8>

DDR_XDP_WAN_SMBCLK<8>

FIVR_EN_R

FIVR_EN

FIVR_EN

XDP_DBRESET#

CPU_XDP_PREQ#

CPU_XDP_PREQ#<10>

CPU_XDP_PRDY#<10>

1 2
1 2

1 2
1 2
1 2
1 2

PCH_JTAG_TCK<12>

CPU_XDP_TCLK<12>

CPU XDP

H_VCCST_PWRGD_XDP

SIO_PWRBTN#<11,36>

CPU_XDP_PREQ#
CPU_XDP_PRDY#

RESET_OUT#_R

CPU_XDP_TCLK

4

+1.0V_PRIM_XDP

CFG0
CFG1

CFG2
CFG3

XDP_OBS0
XDP_OBS1

CFG4
CFG5

CFG6
CFG7

FIVR_EN_R

+3.3V_ALW_PCH

1 2

PCH_SPI_DO_XDP
RESET_OUT#_R

0.1U_0402_25V6

12

CC33@

Place near JXDP1.47

XDP_PRSNT_PIN1

RC133

1.5K_0402_5%

CXDP@

CXDP@

1 2

RC121 0_0402_5%

1 2

RC122 0_0402_5%@
JXDP1

1

1
3
5
7
9
111112
131314
151516
171718
191920
212122
232324
252526
272728
292930
313132
333334
353536
373738
393940
414142
434344
454546
474748
494950
515152
535354
555556
575758
595960
61

GND

CONN@

GND

2
4
6
8

10

3
5
7
9

61
62

E-T_6601K-Y61N-04L

Place near JXDP1.48

CFG3

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60

63

XDP_DBRESET#

CFG17
CFG16

CFG8
CFG9

CFG10
CFG11

CFG19
CFG18

CFG12
CFG13

CFG14
CFG15

ITP_PMODE
XDP_DBRESET#

TDO_XDP
TRST#_XDP
TDI_XDP
XDP_TMS

0.1U_0402_25V6

12

3

CXDP@

CC32

Place near JXDP1.41

CFG[0..19]<13>

CLK_ITPXDP_P_R <11>
CLK_ITPXDP_N_R <11>

ITP_PMODE <13>
XDP_DBRESET# <11>

PCH_SPI_DO2_XDP <8>

+3.3V_ALW_DSW

SIO_PWRBTN#

1 2

12

2

+3.3V_RUN

CC30

12

0.1U_0201_10V6K

TDO_XDP

TDI_XDP

XDP_TMS

TRST#_XDP

RUNPWROK<36>

1.5K_0402_5%

@

RC241

0.1U_0402_25V6
CC269

@

UC8

14

VCC

2

1A

1

1OE

5

2A

4

2OE

9

3A

10

3OE

12

4A

13

4OE

74CBTLV3126BQ_DHVQFN14_2P5X3

CPU_XDP_TMS

RC131 51_0402_5%

CPU_XDP_TDI

RC134 51_0402_5%

CPU_XDP_TDO

RC135 100_0402_5%

CPU_XDP_TRST#

RC136@ 51_0402_5%

CPU_XDP_TCLK

RC139 51_0402_5%

XDP_TMS

1 2

@

RC228 0_0402_5%

TDI_XDP

1 2

@

RC229 0_0402_5%

TDO_XDP

1 2

@

RC230 0_0402_5%

GND PAD

1 2
1 2
1 2

1 2
1 2

1B

2B

3B

4B

GND

1

3

6

8

11

7
15

+1.0V_VCCSTG

PCH_JTAG_TMS <12>
PCH_JTAG_TDI <12>
PCH_JTAG_TDO <12>

CPU_XDP_TDO <12>

CPU_XDP_TDI <12>

CPU_XDP_TMS <12>

CPU_XDP_TRST# <12>

B B

TDO_XDP H_VCCST_PWRGD_XDP CPU_XDP_TRST#

0.1U_0402_25V6

@ESD@

12

CC306

ESD request,Place near JXDP1 side. ESD request,Place near UC8 side.

0.1U_0402_25V6

@ESD@

12

CC307

0.1U_0402_25V6

@ESD@

12

CC308

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.

5

4

3

2

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CPU (9/14)

CPU (9/14)

CPU (9/14)

LA-F292P

LA-F292P

LA-F292P

14 60Tuesday, November 14, 2017

14 60Tuesday, November 14, 2017

14 60Tuesday, November 14, 2017

1

1.0

1.0

1.0

5

smd.db-x7.ru

4

3

2

1

+VCC_CORE: 0.3~1.35V

D D

@

T122

PAD~D

@

T123

PAD~D

Remove (not support 2+3e)
2016 0303

C C

VCCOPC,VCCOPC_1P8,VCCEOPIO for SKYLAKE-U 2+3e

(w/ on package cache)

+VCC_CORE +VCC_CORE

+VCC_CORE_G0
+VCC_CORE_G1

UC1L

A30

VCC_A30

A34

VCC_A34

A39

VCC_A39

A44

VCC_A44

AK33

VCC_AK33

AK35

VCC_AK35

AK37

VCC_AK37

AK38

VCC_AK38

AK40

VCC_AK40

AL33

VCC_AL33

AL37

VCC_AL37

AL40

VCC_AL40

AM32

VCC_AM32

AM33

VCC_AM33

AM35

VCC_AM35

AM37

VCC_AM37

AM38

VCC_AM38

G30

VCC_G30

K32

RSVD

AK32

RSVD

AB62

VCCOPC_AB62

P62

VCCOPC_P62

V62

VCCOPC_V62

H63

VCC_OPC_1P8_H63

G61

VCC_OPC_1P8_G61

AC63

VCCOPC_SENSE

AE63

VSSOPC_SENSE

AE62

VCCEOPIO

AG62

VCCEOPIO

AL63

VCCEOPIO_SENSE

AJ62

VSSEOPIO_SENSE

KBL-RU42_BGA1356

CPU@

KBL-R U4+2

CPU POWER 1 OF 4

Rev_0.1

VCC_G32
VCC_G33
VCC_G35
VCC_G37
VCC_G38
VCC_G40
VCC_G42

VCC_J30
VCC_J33
VCC_J37
VCC_J40
VCC_K33
VCC_K35
VCC_K37
VCC_K38
VCC_K40
VCC_K42
VCC_K43

VCC_SENSE
VSS_SENSE

VIDALERT#

VIDSCK

VIDSOUT

VCCSTG_G20

12 OF 20

G32
G33
G35
G37
G38
G40
G42
J30
J33
J37
J40
K33
K35
K37
K38
K40
K42
K43

E32
E33

B63
A63
D64

G20

VCCSENSE
VSSSENSE

H_CPU_SVIDALRT#
VIDSCLK

VIDSOUT

+1.0V_VCCSTG_R

VIDSCLK <53>

+VCC_CORE

RC140

100_0402_1%

1 2

12

RC141

100_0402_1%

@

1 2

RC143 0_0603_5%

VCCSENSE <53>
VSSSENSE <53>

+1.0V_VCCSTG

VIDSCLK

RF Request

1 2

CC321@RF@ 33P_0402_50V8J

Place close CPU side

PSC(Primary side cap) : Place as close to the package as possible
BSC(Backside cap) : Place on secondary side, underneath the package

Component placement order:
Package edge > 0402 caps > 0805 caps > Bulk caps >Power source

B B

SVID ALERT

VIDALERT_N<53>

SVID DATA

A A

VIDSOUT<53>

+1.0V_VCCST

1 2

+1.0V_VCCST

1 2

56_0402_1%

RC152

100_0402_1%

RC157

CAD Note: Place the PU resistors close to CPU
RC204 close to CPU 300 - 1500mils

H_CPU_SVIDALRT#

12

RC153220_0402_5%

CAD Note: Place the PU resistors close to CPU
RC208close to CPU 300 - 1500mils

VIDSOUT

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.

5

4

3

2

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CPU (10/14)

CPU (10/14)

CPU (10/14)

LA-F292P

LA-F292P

LA-F292P

15 60Tuesday, November 14, 2017

15 60Tuesday, November 14, 2017

15 60Tuesday, November 14, 2017

1

1.0

1.0

1.0

5

smd.db-x7.ru

4

3

2

1

+VCCGT: 0.3~1.35V
+VCCGTX : 0.3~1.35V

KBL-R 4+2 and KBL-U 2+2&2+3e opt i on ( pl ac e on po wer page)

D D

+VCC_GT
+VCC_GT

C C

B B

VCC_GT_SENSE<53>
VSS_GT_SENSE<53>

RC437 0_0402_5%

@

1 2

+VCC_GT

+VCC_GT_+VCC_CORE

RC161

100_0402_1%

1 2

VCC_GT_SENSE
VSS_GT_SENSE

12

RC163

100_0402_1%

UC1M

KBL-U / KBL-R U4+2

A48

VCCGT/VCCCORE_5

A53

VCCGT/VCCCORE_6

J43

VCCGT/VCCCORE_44

J45

VCCGT/VCCCORE_45

J46

VCCGT/VCCCORE_46

J48

VCCGT/VCCCORE_47

J50

VCCGT/VCCCORE_48

J52

VCCGT/VCCCORE_49

K48

VCCGT/VCCCORE_57

K50

VCCGT/VCCCORE_58

K52

VCCGT/RSVD_6

A58

VCCGT

A62

VCCGT

A66

VCCGT

AA63

VCCGT

AA64

VCCGT

AA66

VCCGT

AA67

VCCGT

AA69

VCCGT

AA70

VCCGT

AA71

VCCGT

AC64

VCCGT

AC65

VCCGT

AC66

VCCGT

AC67

VCCGT

AC68

VCCGT

AC69

VCCGT

AC70

VCCGT

AC71

VCCGT

J53

VCCGT

J55

VCCGT

J56

VCCGT

J58

VCCGT

J60

VCCGT

K53

VCCGT

K55

VCCGT

K56

VCCGT

K58

VCCGT

K60

VCCGT

L62

VCCGT

L63

VCCGT

L64

VCCGT

L65

VCCGT

L66

VCCGT

L67

VCCGT

L68

VCCGT

L69

VCCGT

L70

VCCGT

L71

VCCGT

M62

VCCGT

N63

VCCGT

N64

VCCGT

N66

VCCGT

N67

VCCGT

N69

VCCGT

J70

VCCGT_SENSE

J69

VSSGT_SENSE

KBL-RU42_BGA1356

KBL-R U4+2

CPU@

CPU POWER 2 OF 4

KBL-U / KBL-R U4+2

VCCGTX_AK42/VCCCORE_12
VCCGTX_AK43/VCCCORE_13
VCCGTX_AK45/VCCCORE_14
VCCGTX_AK46/VCCCORE_15
VCCGTX_AK48/VCCCORE_16
VCCGTX_AK50/VCCCORE_17
VCCGTX_AL43/VCCCORE_21
VCCGTX_AL46/VCCCORE_22
VCCGTX_AL50/VCCCORE_23
VCCGTX_AM48/VCCCORE_29
VCCGTX_AM50/VCCCORE_30
VCCGTX_AM52/VCCCORE_31

VCCGTX_AK52/RSVD_5

Rev_0.1

VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT

VCCGTX_AK53
VCCGTX_AK55
VCCGTX_AK56
VCCGTX_AK58
VCCGTX_AK60
VCCGTX_AK70

VCCGTX_AL53
VCCGTX_AL56

VCCGTX_AL60
VCCGTX_AM53
VCCGTX_AM56
VCCGTX_AM58
VCCGTX_AU58
VCCGTX_AU63
VCCGTX_BB57
VCCGTX_BB66

VCCGTX_SENSE
VSSGTX_SENSE

13 OF 20

N70
N71
R63
R64
R65
R66
R67
R68
R69
R70
R71
T62
U65
U68
U71
W63
W64
W65
W66
W67
W68
W69
W70
W71
Y62

AK42
AK43
AK45
AK46
AK48
AK50
AL43
AL46
AL50
AM48
AM50
AM52
AK52

AK53
AK55
AK56
AK58
AK60
AK70
AL53
AL56
AL60
AM53
AM56
AM58
AU58
AU63
BB57
BB66

AK62
AL61

+VCC_GT

KBL-R 4+2 and KBL-U 2+2&2+3e opt i on ( pl ac e on po wer page)

+VCC_GT_+VCC_CORE

1 2

@

RC438 0_0402_5%

+VCC_GT
+VCC_GTUS

Reserve for soldering

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.

5

4

3

2

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CPU (11/14)

CPU (11/14)

CPU (11/14)

LA-F292P

LA-F292P

LA-F292P

16 60Tuesday, November 14, 2017

16 60Tuesday, November 14, 2017

16 60Tuesday, November 14, 2017

1

1.0

1.0

1.0

5

smd.db-x7.ru

4

3

2

1

+VCCPLL_OC source

+1.2V_MEM+1.2V_MEM_CPUCLK

@

1 2

RC231 0_0402_5%

D D

PSC

1

1

2

1

CC177

CC176

2

2

10U_0402_6.3V6M

10U_0402_6.3V6M

PSC

22U_0603_6.3V6M

CC294

1

1

2

2

+1.0V_VCCST

C C

B B

PSC

1

2

CC195

1U_0402_6.3V6K

1

CC178

2

10U_0402_6.3V6M

22U_0603_6.3V6M

CC295

1

2

+1.0V_VCCSTG

CC179

10U_0402_6.3V6M

22U_0603_6.3V6M

CC296

VDDQ: 8.45A

+1.2V_MEM_CPUCLK

+1.2V_MEM

PSC

1

CC297

2

10U_0402_6.3V6M

BSC

+VCC_SFR_OC

1

CC199

2

@

1U_0402_6.3V6K

1

1

2

CC322

2

CC288

RF@

2.2P_0402_50V8C

1U_0402_6.3V6K

RF Request

+1.0V_VCCST source

UC1N

AU23

VDDQ_AU23

AU28

VDDQ_AU28

AU35

VDDQ_AU35

AU42

VDDQ_AU42

BB23

VDDQ_BB23

BB32

VDDQ_BB32

BB41

VDDQ_BB41

BB47

VDDQ_BB47

BB51

VDDQ_BB51

AM40

VDDQC

A18

VCCST

A22

VCCSTG_A22

AL23

VCCPLL_OC

K20

VCCPLL_K20

K21

VCCPLL_K21

KBL-RU42_BGA1356

+1.0V_VCCST

1

2

CPU@

CC202

CPU POWER 3 OF 4

1U_0402_6.3V6K

KBL-R U4+2

PSC

VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO

VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA

VCCIO_SENSE

VSSIO_SENSE

VSSSA_SENSE
VCCSA_SENSE

14 OF 20

+VCC_SA

Rev_0.1

AK28
AK30
AL30
AL42
AM28
AM30
AM42

AK23
AK25
G23
G25
G27
G28
J22
J23
J27
K23
K25
K27
K28
K30

AM23
AM22

H21
H20

1 2

RC168 100_0402_1%

+1.0VS_VCCIO

VCCIO_SENSE
VSSIO_SENSE

+VCC_SA

+1.0VS_VCCIO

12

RC166

100_0402_1%

VSA_SEN- <53>
VSA_SEN+ <53>

1 2

12

RC165

100_0402_1%

VCCIO_SENSE <51>
VSSIO_SENSE <51>

RC167

100_0402_1%

12

CZ102 1U_0402_6.3V6K

VCCSTG_EN

PCH_PRIM_EN<11,44,50,51,52>
SIO_SLP_S4#<11,17,36,49,52>

@

RZ120 0_0402_5%

+1.0VS_VCCIO

1 2

+3.3V_ALW

1

B

2

A

+5V_ALW

1 2

5

0.1U_0402_10V7K

P

O

G

3

TC7SH08FU_SSOP5~D

PSC

1

2

CC252

1U_0402_6.3V6K

+1.0V_VCCSTG source

+1.2V_MEM

1 2

@

RZ119 0_0402_5%

UZ26

1

VIN1

2

VIN2

7

VIN thermal

3

VBIAS

4

ON

1

2

CC251

1U_0402_6.3V6K

TPS22961DNYR_WSON8

SIO_SLP_S0#

SIO_SLP_S3#

AND

CZ104

@

4

UZ34

@

1

1

2

2

CC250

CC253

1U_0402_6.3V6K

1U_0402_6.3V6K

+VCC_SFR_OC

6

VOUT

5

GND

S0

HIGH

HIGH

HIGH LOW LOW

S0Ix

LOW

HIGH

S3

LOW

LOW

1 2

CZ103 0.1U_0201_10V6K

+1.0V_VCCST+1.0V_VCCSTG

1 2

RZ151 0_0603_5%@

+1.0V_PRIM

12

CZ100 1U_0402_6.3V6K

SIO_SLP_S4#<11,17,36,49,52>

+1.0V_PRIM

+5V_ALW

A A

5

UZ21

1

VIN1

2

VIN2

7

VIN thermal

3

VBIAS

4

ON

TPS22961DNYR_WSON8

4.4mohm /6A
TR=12.5us@Vin=1.05V

VOUT

GND

6

5

4

+1.0V_VCCST_C

PJP1

12

PAD-OPEN1x1m

1 2

CZ101 0.1U_0201_10V6K

+1.0V_VCCST

SIO_SLP_S0#<11,38,51>

RUN_ON<36,37,44,51>

TC7SH08FU_SSOP5~D

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.

3

12

CZ105 1U_0402_6.3V6K

UZ35

RZ320 0_0402_5%@

+5V_ALW

+3.3V_ALW

5

1

B

2

A

3

1 2

P

O

G

4

UZ19

1

VIN1

2

VIN2

7

VIN thermal

3

VBIAS

4

ON

TPS22961DNYR_WSON8

4.4mohm /6A

VCCSTG_EN

TR=12.5us@Vin=1.05V

VOUT

GND

2

12

PJP2
PAD-OPEN1x1m

+1.0V_VCCSTG_C

6

5

DELL CONFIDENTIAL/PROPRIETARY

pop option with UZ19

1 2

CZ106 0.1U_0201_10V6K

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CPU (12/14)

CPU (12/14)

CPU (12/14)

LA-F292P

LA-F292P

LA-F292P

17 60Tuesday, November 14, 2017

17 60Tuesday, November 14, 2017

17 60Tuesday, November 14, 2017

1

1.0

1.0

1.0

5

smd.db-x7.ru

close UC1.AL1 and <120mil

+1.0V_PRIM

@

1 2

D D

C C

B B

RC299 0_0603_5%

@

1 2

RC300 0_0402_5%

@

1 2

RC301 0_0402_5%

@

1 2

RC302 0_0402_5%

@

1 2

RC303 0_0402_5%

+1.8V_PRIM

@

1 2

RC304 0_0402_5%

1 2

RC234 0_0402_5%@

+3.3V_ALW_PCH

@

1 2

RC235 0_0402_5%

1 2

RC211 0_0402_5%LPC@

+1.8V_PRIM

1 2

RC212 0_0402_5%ESPI@

@

1 2

RC305 0_0402_5%

@

1 2

RC306 0_0402_5%

@

1 2

RC307 0_0402_5%

@

1 2

RC308 0_0402_5%

+3.3V_ALW_PCH

1 2

LC1 FBMA-11-100505-750A10T 0402

1

CC215

2

RF@

1U_0402_6.3V6K

+1.0V_MPHYAON

+1.0V_CLK6

+1.0V_DTS

+1.0V_CLK1

+1.0V_CLK3

+1.8V_PGPPF

+3.3V_1.8V_PGPPG

+3.3V_1.8V_PGPPA

+3.3V_PGPPB+3.3V_ALW_PCH

+3.3V_PGPPC

+3.3V_PGPPD

+3.3V_PGPPE

8/28 schematic review

+3.3V_1.8V_ESPI

PJP4

1 2

PAD-OPEN1x1m

Must be +1.8V for eSPI I/F

+3.3V_VCCHDA

1

CC313

2

0.1U_0201_10V6K

close UC1.AJ19 and <400mil

A A

@

1 2

RC173 0_0402_5%

close UC1.N20 and <100mil

5

+1.0V_CLK4+1.0V_PRIM

1

CC226

2

@

47U_0805_6.3V6M

+1.0V_MPHYAON

1

2

CC203

1U_0402_6.3V6K

+1.0V_MPHYGT

close UC1.N15 and CC210 <400mil, CC211 <120mil

1

1

CC210

2

2

@

47U_0805_6.3V6M

+1.0V_SRAM

close UC1.AF20 and <400mil

1

CC217

2

@

1U_0402_6.3V6K

close UC1.K15, UC1.L15 and <100mil

@

1 2

RC169 0_0603_5%

1

2

CC281

@

0.1U_0201_10V6K

+1.0V_PRIM

1 2

LC2 FBMA-11-100505-750A10T 0402

1

1

CC225

CC335

2

2

@

RF@

1U_0402_6.3V6K

47U_0805_6.3V6M

close UC1.V15 and <100mil

@

1 2

RC170 0_0402_5%

close UC1.K19 and <100mil

1

2

CC204

1U_0402_6.3V6K

CC211

1U_0402_6.3V6K

+1.0V_APLLEBB

+1.0V_AMPHYPLL+1.0V_MPHYGT

1

CC219

2

@

47U_0805_6.3V6M

1

2

1

2

4

+1.0V_PRIM_CORE+1.0VO_DSW

1

CC205

2

@

1U_0402_6.3V6K

close UC1.AF18 and <400mil

+1.0V_AMPHYPLL

+1.0V_APLL

+1.0V_PRIM

+3.3V_ALW_DSW

+3.3V_VCCHDA

+3.3V_SPI

+3.3V_ALW_PCH

+1.0V_PRIM

close UC1.N18 and <120mil

CC218

1U_0402_6.3V6K

close UC1.K15 and <120mil

close UC1.K15 and <120mil

CC264

@

1U_0402_6.3V6K

+1.0V_APLL

1

CC314

2

+1.0V_CLK2+1.0V_PRIM

1

CC220

2

@

47U_0805_6.3V6M

4

close UC1.AB19 and <400milclose UC1.K17 and <120mil

1

2

0.1U_0201_10V6K

+1.0V_PRIM

CC206

@

1U_0402_6.3V6K

3

PCH PWR

UC1O

CPU@

AB19

VCCPRIM_1P0

AB20

VCCPRIM_1P0

P18

VCCPRIM_1P0

AF18

VCCPRIM_CORE

AF19

VCCPRIM_CORE

V20

VCCPRIM_CORE

V21

VCCPRIM_CORE

AL1

DCPDSW_1P0

K17

VCCMPHYAON_1P0

L1

VCCMPHYAON_1P0

N15

VCCMPHYGT_1P0_N15

N16

VCCMPHYGT_1P0_N16

N17

VCCMPHYGT_1P0_N17

P15

VCCMPHYGT_1P0_P15

P16

VCCMPHYGT_1P0_P16

K15

VCCAMPHYPLL_1P0

L15

VCCAMPHYPLL_1P0

V15

VCCAPLL_1P0

AB17

VCCPRIM_1P0_AB17

Y18

VCCPRIM_1P0_Y18

AD17

VCCDSW_3P3_AD17

AD18

VCCDSW_3P3_AD18

AJ17

VCCDSW_3P3_AJ17

AJ19

VCCHDA

AJ16

VCCSPI

AF20

VCCSRAM_1P0

AF21

VCCSRAM_1P0

T19

VCCSRAM_1P0

T20

VCCSRAM_1P0

AJ21

VCCPRIM_3P3_AJ21

AK20

VCCPRIM_1P0_AK20

N18

VCCAPLLEBB_1P0

KBL-RU42_BGA1356

+3.3V_ALW_DSW

22U_0603_6.3V6M

@

CC279

1

2

Support DS3

No Support DS3

'V' mean POP, 'X' mean DE-POP

KBL-R U4+2

CPU POWER 4 OF 4

1 2

RC440 0_0402_5%NDS3@

1 2

RC214 0_0402_5%@

1 2

@DS3@

RC439 0_0402_5%

22U_0603_6.3V6M

@

CC280

1

2

RC439

RC440RE536RC215RC441RC442

V V V

X

V V V

X X

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.

3

Rev_0.1

VCCPGPPA
VCCPGPPB
VCCPGPPC
VCCPGPPD
VCCPGPPE
VCCPGPPF
VCCPGPPG

VCCPRIM_3P3_V19

VCCPRIM_1P0_T1

VCCATS_1P8

VCCRTCPRIM_3P3

VCCRTC_AK19
VCCRTC_BB14

DCPRTC
VCCCLK1
VCCCLK2
VCCCLK3
VCCCLK4
VCCCLK5
VCCCLK6

GPP_B0/CORE_VID0
GPP_B1/CORE_VID1

15 OF 20

+3.3V_ALW_PCH

+3.3V_ALW_DSW_R

X

X

close UC1.AG15 and <120mil

Must be +1.8V

AK15
AG15
Y16
Y15
T16
AF16
AD15

V19
T1
AA1
AK17
AK19

BB14
BB10
A14
K19
L21
N20
L19
A10
AN11

AN13

+3.3V_1.8V_PGPPA

+3.3V_PGPPD
+1.8V_PGPPF

+3.3V_1.8V_PGPPG

+1.0V_DTS

+3.3V_ALW_PCH

close UC1.AK19 and <120mil

+DCPRTC

close UC1.BB10 and <120mil

+1.0V_CLK1
+1.0V_CLK2
+1.0V_CLK3
+1.0V_CLK4
+1.0V_CLK5

CORE_VID0 <51>
CORE_VID1 <51>

Take care!!! Note1 on Page 19

QC7

DS3@

LP2301ALT1G_SOT23-3

123

D

S

499K_0402_1%

12

G

49.9K_0402_1%

0.1U_0402_25V6K
RC433

DS3@

12

12

@

CC340

L2N7002WT1G_SC-70-3

X

13

D

QC6

DS3@

2

G

S

2

close UC1.Y16 a nd <400mil

+3.3V_PGPPB

+3.3V_PGPPC

1

CC265

2

@

1U_0402_6.3V6K

close UC1.AA1 and <400mil

1

2

CC214

0.1U_0201_10V6K

+1.0V_CLK6

1

2

+3.3V_ALW

RC432

DS3@

100K_0402_5%

RC431

DS3@

1 2

VCCDSW_EN_GPIO <11>

2

+3.3V_PGPPE

1

2

+RTC_CELL_PCH

1

2

1

CC207

2

@

1U_0402_6.3V6K

1

2

CC270

CC213

1U_0402_6.3V6K

0.1U_0201_10V6K

close UC1.A10 and <120mil

CC216

@

1U_0402_6.3V6K

@

RC171 0_0402_5%

close UC1.L19 and <100mil

DELL CONFIDENTIAL/PROPRIETARY

1

+1.0V_MPHYGT

+1.0V_SRAM

+1.0V_APLLEBB

close UC1.AD15 and <400mil

1

CC326

2

1U_0402_6.3V6K

close UC1.T16 a nd <400mil

CC208

@

1U_0402_6.3V6K

+3.3V_ALW_PCH

+1.8V_PRIM

1

CC209

1

2

@

2

1U_0402_6.3V6K

CC212

1U_0402_6.3V6K

@

1 2

RC309 0_0603_5%

@

1 2

RC310 0_0603_5%

+3.3V_1.8V_PGPPG

close UC1.V19 and <120mil

RF Request

+1.0V_APLL +3.3V_VCCHDA +1.0V_APLLEBB

1

2

CC325

1.2P_0402_50V8C

RF@

close UC1.AK17 and <120mil

1

2

CC224

1U_0402_6.3V6K

0.1U_0201_10V6K

1 2

1

1

2

2

CC323

CC324

RF@

RF@

1.2P_0402_50V8C

+3.3V_ALW_PCH+1.0V_CLK5+1.0V_PRIM

1

CC221

2

@

47U_0805_6.3V6M

1

CC223

2

+1.0V_MPHYGT source

+1.0V_MPHYGT+1.0V_PRIM

PJP3

1 2

PAD-OPEN1x3m

Pop PJP35 & Depop UZ20/RZ83/CZ84

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CPU (13/14)

CPU (13/14)

CPU (13/14)

LA-F292P

LA-F292P

LA-F292P

18 60Tuesday, November 14, 2017

18 60Tuesday, November 14, 2017

18 60Tuesday, November 14, 2017

1

1.2P_0402_50V8C

1.0

1.0

1.0

5

smd.db-x7.ru

4

3

2

1

CPU@

KBL-R U4+2

CPU@

KBL-R U4+2

UC1P

A5

VSS

A67

VSS

A70

VSS

AA2

VSS

AA4

D D

C C

B B

VSS

AA65

VSS

AA68

VSS

AB15

VSS

AB16

VSS

AB18

VSS

AB21

VSS

AB8

VSS

AD13

VSS

AD16

VSS

AD19

VSS

AD20

VSS

AD21

VSS

AD62

VSS

AD8

VSS

AE64

VSS

AE65

VSS

AE66

VSS

AE67

VSS

AE68

VSS

AE69

VSS

AF1

VSS

AF10

VSS

AF15

VSS

AF17

VSS

AF2

VSS

AF4

VSS

AF63

VSS

AG16

VSS

AG17

VSS

AG18

VSS

AG19

VSS

AG20

VSS

AG21

VSS

AG71

VSS

AH13

VSS

AH6

VSS

AH63

VSS

AH64

VSS

AH67

VSS

AJ15

VSS

AJ18

VSS

AJ20

VSS

AJ4

VSS

AK11

VSS

AK16

VSS

AK18

VSS

AK21

VSS

AK22

VSS

AK27

VSS

AK63

VSS

AK68

VSS

AK69

VSS

AK8

VSS

AL2

VSS

AL28

VSS

AL32

VSS

AL35

VSS

AL38

VSS

AL4

VSS

AL45

VSS

AL48

VSS

AL52

VSS

AL55

VSS

AL58

VSS

AL64

VSS

KBL-RU42_BGA1356

GND 1 OF 3

Rev_0.1

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

16 OF 20

AL65
AL66
AM13
AM21
AM25
AM27
AM43
AM45
AM46
AM55
AM60
AM61
AM68
AM71
AM8
AN20
AN23
AN28
AN30
AN32
AN33
AN35
AN37
AN38
AN40
AN42
AN58
AN63
AP10
AP18
AP20
AP23
AP28
AP32
AP35
AP38
AP42
AP58
AP63
AP68
AP70
AR11
AR15
AR16
AR20
AR23
AR28
AR35
AR42
AR43
AR45
AR46
AR48
AR5
AR50
AR52
AR53
AR55
AR58
AR63
AR8
AT2
AT20
AT23
AT28
AT35
AT4
AT42
AT56
AT58

UC1Q

AT63
AT68
AT71
AU10
AU15
AU20
AU32
AU38

AV1
AV68
AV69
AV70
AV71

AW10
AW12
AW14
AW16
AW18
AW21
AW23
AW26
AW28
AW30
AW32
AW34
AW36
AW38
AW41
AW43
AW45
AW47
AW49
AW51
AW53
AW55
AW57

AW6
AW60
AW62
AW64
AW66

AW8

AY66

B10
B14
B18
B22
B30
B34
B39
B44
B48
B53
B58
B62
B66
B71

BA1
BA10
BA14
BA18

BA2
BA23
BA28
BA32
BA36

F68

BA45

KBL-RU42_BGA1356

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

GND 2 OF 3

Rev_0.1

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

17 OF 20

BA49
BA53
BA57
BA6
BA62
BA66
BA71
BB18
BB26
BB30
BB34
BB38
BB43
BB55
BB6
BB60
BB64
BB67
BB70
C1
C25
C5
D10
D11
D14
D18
D22
D25
D26
D30
D34
D39
D44
D45
D47
D48
D53
D58
D6
D62
D66
D69
E11
E15
E18
E21
E46
E50
E53
E56
E6
E65
E71
F1
F13
F2
F22
F23
F27
F28
F32
F33
F35
F37
F38
F4
F40
F42
BA41

CPU@

UC1R

F8

VSS

G10

VSS

G22

VSS

G43

VSS

G45

VSS

G48

VSS

G5

VSS

G52

VSS

G55

VSS

G58

VSS

G6

VSS

G60

VSS

G63

VSS

G66

VSS

H15

VSS

H18

VSS

H71

VSS

J11

VSS

J13

VSS

J25

VSS

J28

VSS

J32

VSS

J35

VSS

J38

VSS

J42

VSS

J8

VSS

K16

VSS

K18

VSS

K22

VSS

K61

VSS

K63

VSS

K64

VSS

K65

VSS

K66

VSS

K67

VSS

K68

VSS

K70

VSS

K71

VSS

L11

VSS

L16

VSS

L17

VSS

KBL-RU42_BGA1356

KBL-R U4+2

GND 3 OF 3

Rev_0.1

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

18 OF 20

L18
L2
L20
L4
L8
N10
N13
N19
N21
N6
N65
N68
P17
P19
P20
P21
R13
R6
T15
T17
T18
T2
T21
T4
U10
U63
U64
U66
U67
U69
U70
V16
V17
V18
W13
W6
W9
Y17
Y19
Y20
Y21

Note1: VCCPRIM_CORE Implementat i on wit h PC H C ORE_VI D Reco mmendat i on

R1: PR408,PR411 ; R2: PR417,PR418 ; R3,PR419,PR420 ; R4: PR423 ; R5: PR424

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.

5

4

3

2

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CPU (14/14)

CPU (14/14)

CPU (14/14)

LA-F292P

LA-F292P

LA-F292P

19 60Tuesday, November 14, 2017

19 60Tuesday, November 14, 2017

19 60Tuesday, November 14, 2017

1

1.0

1.0

1.0

5

smd.db-x7.ru

UD1

X76@

+1.8V_MEM

+1.2V_MEM

D D

+1.2V_MEM

C C

+1.2V_MEM

B B

A3

VDD1

A4

VDD1

A5

VDD1

A6

VDD1

A10

VDD1

U3

VDD1

U4

VDD1

U5

VDD1

U6

VDD1

U10

VDD1

A8

VDD2

A9

VDD2

D4

VDD2

D5

VDD2

D6

VDD2

G5

VDD2

H5

VDD2

H6

VDD2

H12

VDD2

J5

VDD2

J6

VDD2

K5

VDD2

K6

VDD2

K12

VDD2

L5

VDD2

P4

VDD2

P5

VDD2

P6

VDD2

U8

VDD2

U9

VDD2

A11

VDDQ

C12

VDDQ

E8

VDDQ

E12

VDDQ

G12

VDDQ

H8

VDDQ

H9

VDDQ

H11

VDDQ

J9

VDDQ

J10

VDDQ

K8

VDDQ

K11

VDDQ

L12

VDDQ

N8

VDDQ

N12

VDDQ

R12

VDDQ

U11

VDDQ

F2

VDDCA

G2

VDDCA

H3

VDDCA

L2

VDDCA

M2

VDDCA

A1

NC

A2

NC

A12

NC

A13

NC

B1

NC

B13

NC

C4

NC

K9

NC

R3

NC

T1

NC

T13

NC

U1

NC

U2

NC

U12

NC

U13

NC

P3

VSSCA

M4

VSSCA

J4

VSSCA

G4

VSSCA

G3

VSSCA

F4

VSSCA

D3

VSSCA

C3

VSSCA

T12

VSSQ

T6

VSSQ

R6

VSSQ

P12

VSSQ

N6

VSSQ

M12

VSSQ

M6

VSSQ

L9

VSSQ

K10

VSSQ

H10

VSSQ

G9

VSSQ

G6

VSSQ

F12

VSSQ

F6

VSSQ

E6

VSSQ

D12

VSSQ

C6

VSSQ

B12

VSSQ

B6

VSSQ

LPDDR3_FBGA178

Vref_DQ

Vref_CA

DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

DQS0
DQS1
DQS2
DQS3

DQS0#
DQS1#
DQS2#
DQS3#

CKE0
CKE1

CS0#
CS1#

P9

DQ0

N9

DQ1

N10

DQ2

N11

DQ3

M8

DQ4

M9

DQ5

M10

DQ6

M11

DQ7

F11

DQ8

F10

DQ9

F9
F8
E11
E10
E9
D9
T8
T9
T10
T11
R8
R9
R10
R11
C11
C10
C9
C8
B11
B10
B9
B8

R2

CA0

P2

CA1

N2

CA2

N3

CA3

M3

CA4

F3

CA5

E3

CA6

E2

CA7

D2

CA8

C2

CA9

L10
G10
P10
D10

L11
G11
P11
D11

L8

DM0

G8

DM1

P8

DM2

D8

DM3

B3

ZQ0

B4

ZQ1

K3
K4

L3
L4

J3

CK

J2

CK#

J8

ODT

J11
H4

B2

VSS

B5

VSS

C5

VSS

E4

VSS

E5

VSS

F5

VSS

H2

VSS

J12

VSS

K2

VSS

L6

VSS

M5

VSS

N4

VSS

N5

VSS

R4

VSS

R5

VSS

T2

VSS

T3

VSS

T4

VSS

T5

VSS

DDR_A_D3
DDR_A_D7
DDR_A_D5
DDR_A_D2
DDR_A_D0
DDR_A_D1
DDR_A_D4
DDR_A_D6
DDR_A_D26
DDR_A_D28
DDR_A_D30
DDR_A_D31
DDR_A_D27
DDR_A_D29
DDR_A_D25
DDR_A_D24
DDR_A_D9
DDR_A_D12
DDR_A_D14
DDR_A_D15
DDR_A_D8
DDR_A_D13
DDR_A_D11
DDR_A_D10
DDR_A_D16
DDR_A_D20
DDR_A_D22
DDR_A_D18
DDR_A_D17
DDR_A_D21
DDR_A_D23
DDR_A_D19

DDR_A_CAA0
DDR_A_CAA1
DDR_A_CAA2
DDR_A_CAA3
DDR_A_CAA4
DDR_A_CAA5
DDR_A_CAA6
DDR_A_CAA7
DDR_A_CAA8
DDR_A_CAA9

DDR_A_DQS0
DDR_A_DQS3
DDR_A_DQS1
DDR_A_DQS2

DDR_A_DQS#0
DDR_A_DQS#3
DDR_A_DQS#1
DDR_A_DQS#2

1 2

RD28 243_0402_1%

1 2

RD29 243_0402_1%

DDR_A_CKE0
DDR_A_CKE1

DDR_A_CS#0
DDR_A_CS#1

DDR_A_CLK0
DDR_A_CLK#0

DDR_A_ODT0

+VREFDQ_A
+VREFCA

+VREFCA
+VREFDQ_A

DDR_A_CKE0 <7>
DDR_A_CKE1 <7>

DDR_A_CS#0 <7>
DDR_A_CS#1 <7>

DDR_A_CLK0 <7>
DDR_A_CLK#0 <7>

DDR_A_ODT0 <7>

1

CD10

0.047U_0402_16V7K

2

1

CD20

0.047U_0402_16V7K

2

4

UD2

+1.8V_MEM

+1.2V_MEM

+1.2V_MEM

+1.2V_MEM

A3

VDD1

A4

VDD1

A5

VDD1

A6

VDD1

A10

VDD1

U3

VDD1

U4

VDD1

U5

VDD1

U6

VDD1

U10

VDD1

A8

VDD2

A9

VDD2

D4

VDD2

D5

VDD2

D6

VDD2

G5

VDD2

H5

VDD2

H6

VDD2

H12

VDD2

J5

VDD2

J6

VDD2

K5

VDD2

K6

VDD2

K12

VDD2

L5

VDD2

P4

VDD2

P5

VDD2

P6

VDD2

U8

VDD2

U9

VDD2

A11

VDDQ

C12

VDDQ

E8

VDDQ

E12

VDDQ

G12

VDDQ

H8

VDDQ

H9

VDDQ

H11

VDDQ

J9

VDDQ

J10

VDDQ

K8

VDDQ

K11

VDDQ

L12

VDDQ

N8

VDDQ

N12

VDDQ

R12

VDDQ

U11

VDDQ

F2

VDDCA

G2

VDDCA

H3

VDDCA

L2

VDDCA

M2

VDDCA

A1

NC

A2

NC

A12

NC

A13

NC

B1

NC

B13

NC

C4

NC

K9

NC

R3

NC

T1

NC

T13

NC

U1

NC

U2

NC

U12

NC

U13

NC

P3

VSSCA

M4

VSSCA

J4

VSSCA

G4

VSSCA

G3

VSSCA

F4

VSSCA

D3

VSSCA

C3

VSSCA

T12

VSSQ

T6

VSSQ

R6

VSSQ

P12

VSSQ

N6

VSSQ

M12

VSSQ

M6

VSSQ

L9

VSSQ

K10

VSSQ

H10

VSSQ

G9

VSSQ

G6

VSSQ

F12

VSSQ

F6

VSSQ

E6

VSSQ

D12

VSSQ

C6

VSSQ

B12

VSSQ

B6

VSSQ

LPDDR3_FBGA178

X76@

3

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

DQS0
DQS1
DQS2
DQS3

DQS0#
DQS1#
DQS2#
DQS3#

DM0

DM1

DM2

DM3

CKE0
CKE1

CS0#
CS1#

ODT

Vref_DQ
Vref_CA

P9
N9
N10
N11
M8
M9
M10
M11
F11
F10
F9
F8
E11
E10
E9
D9
T8
T9
T10
T11
R8
R9
R10
R11
C11
C10
C9
C8
B11
B10
B9
B8

R2

CA0

P2

CA1

N2

CA2

N3

CA3

M3

CA4

F3

CA5

E3

CA6

E2

CA7

D2

CA8

C2

CA9

L10
G10
P10
D10

L11
G11
P11
D11

L8
G8
P8
D8

B3

ZQ0

B4

ZQ1

K3
K4

L3
L4

J3

CK

J2

CK#

J8

J11
H4

B2

VSS

B5

VSS

C5

VSS

E4

VSS

E5

VSS

F5

VSS

H2

VSS

J12

VSS

K2

VSS

L6

VSS

M5

VSS

N4

VSS

N5

VSS

R4

VSS

R5

VSS

T2

VSS

T3

VSS

T4

VSS

T5

VSS

2

DDR_A_D37
DDR_A_D36
DDR_A_D38
DDR_A_D34
DDR_A_D32
DDR_A_D39
DDR_A_D33
DDR_A_D35
DDR_A_D42
DDR_A_D43
DDR_A_D40
DDR_A_D44
DDR_A_D46
DDR_A_D47
DDR_A_D41
DDR_A_D45
DDR_A_D52
DDR_A_D48
DDR_A_D55
DDR_A_D54
DDR_A_D53
DDR_A_D49
DDR_A_D51
DDR_A_D50
DDR_A_D63
DDR_A_D62
DDR_A_D56
DDR_A_D60
DDR_A_D58
DDR_A_D59
DDR_A_D61
DDR_A_D57 DDR_A_CKE2

DDR_A_CAB0
DDR_A_CAB1
DDR_A_CAB2
DDR_A_CAB3
DDR_A_CAB4
DDR_A_CAB5
DDR_A_CAB6
DDR_A_CAB7
DDR_A_CAB8
DDR_A_CAB9

DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

1 2

RD31 243_0402_1%

1 2

RD32 243_0402_1%

DDR_A_CKE2
DDR_A_CKE3

DDR_A_CS#0
DDR_A_CS#1

DDR_A_CLK1
DDR_A_CLK#1

DDR_A_ODT0

+VREFDQ_A
+VREFCA

+VREFCA
+VREFDQ_A

DDR_A_CKE2 <7>
DDR_A_CKE3 <7>

DDR_A_CLK1 <7>
DDR_A_CLK#1 <7>

1

CD11

0.047U_0402_16V7K

2

1

CD21

0.047U_0402_16V7K

2

DDR_A_CAA0
DDR_A_CAA1
DDR_A_CAA2
DDR_A_CAA3
DDR_A_CAA4
DDR_A_CAA5
DDR_A_CAA6
DDR_A_CAA7
DDR_A_CAA8
DDR_A_CAA9
DDR_A_CAB0
DDR_A_CAB1
DDR_A_CAB2
DDR_A_CAB3
DDR_A_CAB4
DDR_A_CAB5
DDR_A_CAB6
DDR_A_CAB7
DDR_A_CAB8
DDR_A_CAB9

DDR_A_CS#0
DDR_A_CS#1
DDR_A_ODT0
DDR_A_CKE0
DDR_A_CKE1

DDR_A_CKE3

DDR_A_CLK#0
DDR_A_CLK0

DDR_A_CLK#1
DDR_A_CLK1

+0.6V_DDR_VTT

12

RD1 68_0402_1%

12

RD2 68_0402_1%

12

RD3 68_0402_1%

12

RD4 68_0402_1%

12

RD5 68_0402_1%

12

RD6 68_0402_1%

12

RD7 68_0402_1%

12

RD8 68_0402_1%

12

RD9 68_0402_1%

12

RD10 68_0402_1%

12

RD11 68_0402_1%

12

RD12 68_0402_1%

12

RD13 68_0402_1%

12

RD14 68_0402_1%

12

RD15 68_0402_1%

12

RD16 68_0402_1%

12

RD17 68_0402_1%

12

RD18 68_0402_1%

12

RD19 68_0402_1%

12

RD20 68_0402_1%

+0.6V_DDR_VTT

1 2

RD21 80.6_0402_1%

1 2

RD22 80.6_0402_1%

1 2

RD23 80.6_0402_1%

1 2

RD24 80.6_0402_1%

1 2

RD25 80.6_0402_1%

1 2

RD79 80.6_0402_1%

1 2

RD80 80.6_0402_1%

+0.6V_DDR_VTT

1 2

RD26 37.4_0402_1%

1 2

RD27 37.4_0402_1%

+0.6V_DDR_VTT

1 2

RD30 37.4_0402_1%

1 2

RD33 37.4_0402_1%

Follow CRB 544250

Follow CRB 544250

Follow CRB 544250Fo llow CRB 544 250
CA - 68 ohm

CA - 68 ohm

CA - 68 ohm CA - 68 ohm
CS/CKE/ODT - 80.6 ohm

CS/CKE/ODT - 80.6 ohm

CS/CKE/ODT - 80.6 ohm CS/CKE/O DT - 80.6 ohm
C LK - 37.4 ohm

C LK - 37.4 ohm

C LK - 37.4 ohm CLK - 37.4 ohm

10U_0402_6.3V6M

CD5

10U_0402_6.3V6M

1

2

CD31

1

2

10U_0402_6.3V6M

1

CD41

2

10U_0402_6.3V6M

1

CD32

2

For VDDCA

10U_0402_6.3V6M

CD6

For VDD1

1

CD42

2

For VDD2

10U_0402_6.3V6M

1

CD33

2

1U_0201_6.3V6K

CD1

1

2

+1.2V_MEM

+1.2V_MEM

+1.8V_MEM

1

2

10U_0402_6.3V6M

1

2

1

For LPDDR3

DDR_A_DQS#[0..7]<7>

DDR_A_D[0..63]<7>
DDR_A_DQS[0..7]<7>

DDR_A_CAA[0..9]<7>
DDR_A_CAB[0..9]<7>

Total
VDD :8x0.1uF,16x1uF,5x10uF
VDDCA: 8x1uF,3x10uF
VDD2:12x1uF,5x10uF
VDD1:8x1uF,5x10uF
VTT:8x1uF,2x22uF

1U_0201_6.3V6K

10U_0402_6.3V6M

1

CD43

2

1U_0201_6.3V6K

1

CD30

2

1U_0201_6.3V6K

CD2

1

1

2

2

1U_0201_6.3V6K

1U_0201_6.3V6K

1

CD52

2

1U_0201_6.3V6K

1

CD68

2

1U_0201_6.3V6K

CD3

1

2

1U_0201_6.3V6K

1

1

CD75

CD74

1

2

1U_0201_6.3V6K

CD76

2

2

1U_0201_6.3V6K

1U_0201_6.3V6K

1

CD69

2

CD4

1U_0201_6.3V6K

1U_0201_6.3V6K

1

1

CD70

CD72

CD71

2

2

+0.6V_DDR_VTT

+DDR_VREF_CA +VREFCA

A A

CD39

0.022U_0402_25V7K

RD40

24.9_0402_1%

5

+1.2V_MEM +DDR_VREF_A_DQ

12

RD34

8.2K_0402_1%

RD36

1 2

5.11_0402_1%

1

2

12

12

RD38

8.2K_0402_1%

CD40

0.022U_0402_25V7K

RD41

24.9_0402_1%

4

+1.2V_MEM +VREFDQ_A

RD37

1 2

10_0402_1%

1

2

12

12

RD35

8.2K_0402_1%

12

RD39

8.2K_0402_1%

1

2

3

For VTT

22U_0603_6.3V6M

CD55

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT M AY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

CD60

1

1

2

2

1U_0201_6.3V6K

CD61

CD62

CD66

1

1

2

2

+1.2V_MEM

For VDDQ

10U_0402_6.3V6M

10U_0402_6.3V6M

CD37

CD36

1

1

2

2

1U_0201_6.3V6K

10U_0402_6.3V6M

CD38

1

1

2

2

1U_0201_6.3V6K

1U_0201_6.3V6K

CD22

1

2

1U_0201_6.3V6K

CD24

CD23

1

1

2

2

1U_0201_6.3V6K

1U_0201_6.3V6K

CD26

CD25

1

1

2

2

1U_0201_6.3V6K

1U_0201_6.3V6K

CD27

CD29

CD28

1

1

2

2

0.1U_0201_10V6K

0.1U_0201_10V6K
CD16

1

1

2

2

0.1U_0201_10V6K

0.1U_0201_10V6K

CD17

CD19

CD18

1

1

2

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size

Size

Size

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

LPDDR3

LPDDR3

Document Number Re v

Document Number Re v

Document Number Re v

LPDDR3

LA-F292P

LA-F292P

LA-F292P

1

20 60Tuesday, November 14, 2017

20 60Tuesday, November 14, 2017

20 60Tuesday, November 14, 2017

1.0

1.0

1.0

5

smd.db-x7.ru

UD3

X76@

+1.8V_MEM

+1.2V_MEM

D D

+1.2V_MEM

C C

+1.2V_MEM

B B

A3

VDD1

A4

VDD1

A5

VDD1

A6

VDD1

A10

VDD1

U3

VDD1

U4

VDD1

U5

VDD1

U6

VDD1

U10

VDD1

A8

VDD2

A9

VDD2

D4

VDD2

D5

VDD2

D6

VDD2

G5

VDD2

H5

VDD2

H6

VDD2

H12

VDD2

J5

VDD2

J6

VDD2

K5

VDD2

K6

VDD2

K12

VDD2

L5

VDD2

P4

VDD2

P5

VDD2

P6

VDD2

U8

VDD2

U9

VDD2

A11

VDDQ

C12

VDDQ

E8

VDDQ

E12

VDDQ

G12

VDDQ

H8

VDDQ

H9

VDDQ

H11

VDDQ

J9

VDDQ

J10

VDDQ

K8

VDDQ

K11

VDDQ

L12

VDDQ

N8

VDDQ

N12

VDDQ

R12

VDDQ

U11

VDDQ

F2

VDDCA

G2

VDDCA

H3

VDDCA

L2

VDDCA

M2

VDDCA

A1

NC

A2

NC

A12

NC

A13

NC

B1

NC

B13

NC

C4

NC

K9

NC

R3

NC

T1

NC

T13

NC

U1

NC

U2

NC

U12

NC

U13

NC

P3

VSSCA

M4

VSSCA

J4

VSSCA

G4

VSSCA

G3

VSSCA

F4

VSSCA

D3

VSSCA

C3

VSSCA

T12

VSSQ

T6

VSSQ

R6

VSSQ

P12

VSSQ

N6

VSSQ

M12

VSSQ

M6

VSSQ

L9

VSSQ

K10

VSSQ

H10

VSSQ

G9

VSSQ

G6

VSSQ

F12

VSSQ

F6

VSSQ

E6

VSSQ

D12

VSSQ

C6

VSSQ

B12

VSSQ

B6

VSSQ

LPDDR3_FBGA178

Vref_DQ

Vref_CA

DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

DQS0
DQS1
DQS2
DQS3

DQS0#
DQS1#
DQS2#
DQS3#

CKE0
CKE1

CS0#
CS1#

P9

DQ0

N9

DQ1

N10

DQ2

N11

DQ3

M8

DQ4

M9

DQ5

M10

DQ6

M11

DQ7

F11

DQ8

F10

DQ9

F9
F8
E11
E10
E9
D9
T8
T9
T10
T11
R8
R9
R10
R11
C11
C10
C9
C8
B11
B10
B9
B8

R2

CA0

P2

CA1

N2

CA2

N3

CA3

M3

CA4

F3

CA5

E3

CA6

E2

CA7

D2

CA8

C2

CA9

L10
G10
P10
D10

L11
G11
P11
D11

L8

DM0

G8

DM1

P8

DM2

D8

DM3

B3

ZQ0

B4

ZQ1

K3
K4

L3
L4

J3

CK

J2

CK#

J8

ODT

J11
H4

B2

VSS

B5

VSS

C5

VSS

E4

VSS

E5

VSS

F5

VSS

H2

VSS

J12

VSS

K2

VSS

L6

VSS

M5

VSS

N4

VSS

N5

VSS

R4

VSS

R5

VSS

T2

VSS

T3

VSS

T4

VSS

T5

VSS

DDR_B_D15
DDR_B_D11
DDR_B_D8
DDR_B_D9
DDR_B_D14
DDR_B_D10
DDR_B_D12
DDR_B_D13
DDR_B_D18
DDR_B_D19
DDR_B_D21
DDR_B_D17
DDR_B_D23
DDR_B_D16
DDR_B_D20
DDR_B_D22
DDR_B_D3
DDR_B_D0
DDR_B_D2
DDR_B_D4
DDR_B_D1
DDR_B_D6
DDR_B_D5
DDR_B_D7
DDR_B_D33
DDR_B_D38
DDR_B_D34
DDR_B_D37
DDR_B_D39
DDR_B_D35
DDR_B_D32
DDR_B_D36

DDR_B_CAA0
DDR_B_CAA1
DDR_B_CAA2
DDR_B_CAA3
DDR_B_CAA4
DDR_B_CAA5
DDR_B_CAA6
DDR_B_CAA7
DDR_B_CAA8
DDR_B_CAA9

DDR_B_DQS1
DDR_B_DQS2 DDR_B_DQS6
DDR_B_DQS0
DDR_B_DQS4

DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#0
DDR_B_DQS#4

1 2

RD70 243_0402_1%

1 2

RD71 243_0402_1%

DDR_B_CKE0
DDR_B_CKE1

DDR_B_CS#1

DDR_B_CLK0
DDR_B_CLK#0

DDR_B_ODT0

+VREFDQ_B
+VREFCA

DDR_B_CKE0 <7>
DDR_B_CKE1 <7>

DDR_B_CS#0 <7>
DDR_B_CS#1 <7>

DDR_B_CLK0 <7>
DDR_B_CLK#0 <7>

DDR_B_ODT0 <7>

1

CD46

0.047U_0402_16V7K

2

+VREFCA
+VREFDQ_B +VREFDQ_B

1

CD53

0.047U_0402_16V7K

2

4

UD4

+1.8V_MEM

+1.2V_MEM

+1.2V_MEM

+1.2V_MEM

A3

VDD1

A4

VDD1

A5

VDD1

A6

VDD1

A10

VDD1

U3

VDD1

U4

VDD1

U5

VDD1

U6

VDD1

U10

VDD1

A8

VDD2

A9

VDD2

D4

VDD2

D5

VDD2

D6

VDD2

G5

VDD2

H5

VDD2

H6

VDD2

H12

VDD2

J5

VDD2

J6

VDD2

K5

VDD2

K6

VDD2

K12

VDD2

L5

VDD2

P4

VDD2

P5

VDD2

P6

VDD2

U8

VDD2

U9

VDD2

A11

VDDQ

C12

VDDQ

E8

VDDQ

E12

VDDQ

G12

VDDQ

H8

VDDQ

H9

VDDQ

H11

VDDQ

J9

VDDQ

J10

VDDQ

K8

VDDQ

K11

VDDQ

L12

VDDQ

N8

VDDQ

N12

VDDQ

R12

VDDQ

U11

VDDQ

F2

VDDCA

G2

VDDCA

H3

VDDCA

L2

VDDCA

M2

VDDCA

A1

NC

A2

NC

A12

NC

A13

NC

B1

NC

B13

NC

C4

NC

K9

NC

R3

NC

T1

NC

T13

NC

U1

NC

U2

NC

U12

NC

U13

NC

P3

VSSCA

M4

VSSCA

J4

VSSCA

G4

VSSCA

G3

VSSCA

F4

VSSCA

D3

VSSCA

C3

VSSCA

T12

VSSQ

T6

VSSQ

R6

VSSQ

P12

VSSQ

N6

VSSQ

M12

VSSQ

M6

VSSQ

L9

VSSQ

K10

VSSQ

H10

VSSQ

G9

VSSQ

G6

VSSQ

F12

VSSQ

F6

VSSQ

E6

VSSQ

D12

VSSQ

C6

VSSQ

B12

VSSQ

B6

VSSQ

LPDDR3_FBGA178

X76@

3

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

DQS0
DQS1
DQS2
DQS3

DQS0#
DQS1#
DQS2#
DQS3#

DM0

DM1

DM2

DM3

CKE0
CKE1

CS0#
CS1#

ODT

Vref_DQ
Vref_CA

P9
N9
N10
N11
M8
M9
M10
M11
F11
F10
F9
F8
E11
E10
E9
D9
T8
T9
T10
T11
R8
R9
R10
R11
C11
C10
C9
C8
B11
B10
B9
B8

R2

CA0

P2

CA1

N2

CA2

N3

CA3

M3

CA4

F3

CA5

E3

CA6

E2

CA7

D2

CA8

C2

CA9

L10
G10
P10
D10

L11
G11
P11
D11

L8
G8
P8
D8

B3

ZQ0

B4

ZQ1

K3
K4

L3
L4

J3

CK

J2

CK#

J8

J11
H4

B2

VSS

B5

VSS

C5

VSS

E4

VSS

E5

VSS

F5

VSS

H2

VSS

J12

VSS

K2

VSS

L6

VSS

M5

VSS

N4

VSS

N5

VSS

R4

VSS

R5

VSS

T2

VSS

T3

VSS

T4

VSS

T5

VSS

DDR_B_D44
DDR_B_D45
DDR_B_D43
DDR_B_D46
DDR_B_D41
DDR_B_D42
DDR_B_D40
DDR_B_D47
DDR_B_D51
DDR_B_D50
DDR_B_D49
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D52
DDR_B_D48
DDR_B_D29
DDR_B_D24
DDR_B_D26
DDR_B_D27
DDR_B_D25
DDR_B_D28
DDR_B_D31
DDR_B_D30
DDR_B_D57
DDR_B_D63
DDR_B_D56
DDR_B_D60
DDR_B_D58
DDR_B_D59
DDR_B_D61
DDR_B_D62

DDR_B_CAB0
DDR_B_CAB1
DDR_B_CAB2
DDR_B_CAB3
DDR_B_CAB4
DDR_B_CAB5
DDR_B_CAB6
DDR_B_CAB7
DDR_B_CAB8
DDR_B_CAB9

DDR_B_DQS5
DDR_B_DQS3

DDR_B_DQS7

DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#3
DDR_B_DQS#7

1 2

RD72 243_0402_1%

1 2

RD73 243_0402_1%

DDR_B_CKE2
DDR_B_CKE3

DDR_B_CS#0DDR_B_CS#0
DDR_B_CS#1

DDR_B_CLK1
DDR_B_CLK#1

DDR_B_ODT0

+VREFDQ_B
+VREFCA

+VREFCA

DDR_B_CKE2 <7>
DDR_B_CKE3 <7>

DDR_B_CLK1 <7>
DDR_B_CLK#1 <7>

1

CD47

0.047U_0402_16V7K

2

1

CD54

0.047U_0402_16V7K

2

2

1

For LPDDR3

10U_0402_6.3V6M

CD83

10U_0402_6.3V6M

1

2

CD100

1

2

12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12

CD111

1

2

10U_0402_6.3V6M

1

2

For VDDCA

10U_0402_6.3V6M

@

CD78

+0.6V_DDR_VTT

+0.6V_DDR_VTT

+0.6V_DDR_VTT

+0.6V_DDR_VTT

For VDD1

10U_0402_6.3V6M

CD110

For VDD2

10U_0402_6.3V6M

CD101

1

2

1U_0201_6.3V6K

CD81

1

2

DDR_B_DQS#[0..7]<7>

DDR_B_D[0..63]<7>
DDR_B_DQS[0..7]<7>

DDR_B_CAA[0..9]<7>
DDR_B_CAB[0..9]<7>

1U_0201_6.3V6K

1U_0201_6.3V6K

10U_0402_6.3V6M

@

CD112

1

1

2

2

1U_0201_6.3V6K

@

CD98

CD102

1

2

1U_0201_6.3V6K

1U_0201_6.3V6K

CD82

1

1

2

2

1U_0201_6.3V6K

1U_0201_6.3V6K

CD104

CD103

1

2

CD79

CD106

1

2

1U_0201_6.3V6K

CD105

1

2

1U_0201_6.3V6K

CD80

1

2

CD107

1

1

2

2

1U_0201_6.3V6K

1U_0201_6.3V6K

CD109

1

2

1U_0201_6.3V6K

1U_0201_6.3V6K

CD108

CD114

CD113

1

1

2

2

DDR_B_CAA0
DDR_B_CAA1
DDR_B_CAA2
DDR_B_CAA3
DDR_B_CAA4
DDR_B_CAA5
DDR_B_CAA6
DDR_B_CAA7
DDR_B_CAA8
DDR_B_CAA9
DDR_B_CAB0
DDR_B_CAB1
DDR_B_CAB2
DDR_B_CAB3
DDR_B_CAB4
DDR_B_CAB5
DDR_B_CAB6
DDR_B_CAB7
DDR_B_CAB8
DDR_B_CAB9

DDR_B_CS#0
DDR_B_CS#1
DDR_B_ODT0
DDR_B_CKE0
DDR_B_CKE1
DDR_B_CKE2
DDR_B_CKE3

DDR_B_CLK#0
DDR_B_CLK0

DDR_B_CLK#1
DDR_B_CLK1

RD42 68_0402_1%
RD43 68_0402_1%
RD44 68_0402_1%
RD45 68_0402_1%
RD46 68_0402_1%
RD47 68_0402_1%
RD48 68_0402_1%
RD49 68_0402_1%
RD50 68_0402_1%
RD51 68_0402_1%
RD52 68_0402_1%
RD53 68_0402_1%
RD54 68_0402_1%
RD55 68_0402_1%
RD56 68_0402_1%
RD57 68_0402_1%
RD58 68_0402_1%
RD59 68_0402_1%
RD60 68_0402_1%
RD61 68_0402_1%

1 2

RD62 80.6_0402_1%

1 2

RD63 80.6_0402_1%

1 2

RD64 80.6_0402_1%

1 2

RD65 80.6_0402_1%

1 2

RD66 80.6_0402_1%

1 2

RD81 80.6_0402_1%

1 2

RD82 80.6_0402_1%

1 2

RD67 37.4_0402_1%

1 2

RD68 37.4_0402_1%

1 2

RD69 37.4_0402_1%

1 2

RD74 37.4_0402_1%

Follow CRB 544250

Follow CRB 544250

Follow CRB 544250Fo llow CRB 544 250
CA - 68 ohm

CA - 68 ohm

CA - 68 ohm CA - 68 ohm
CS/CKE/ODT - 80.6 ohm

CS/CKE/ODT - 80.6 ohm

CS/CKE/ODT - 80.6 ohm CS/CKE/O DT - 80.6 ohm
C LK - 37.4 ohm

C LK - 37.4 ohm

C LK - 37.4 ohm CLK - 37.4 ohm

+1.8V_MEM

+1.2V_MEM

1

2

+1.2V_MEM

10U_0402_6.3V6M

1

2

+1.2V_MEM +VREFDQ_B+DDR_VREF_B_DQ

12

RD76

RD75

8.2K_0402_1%

12

RD77

8.2K_0402_1%

3

A A

0.022U_0402_25V7K

24.9_0402_1%

5

4

CD67

RD78

1

2

12

1 2

10_0402_1%

+0.6V_DDR_VTT

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT M AY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

For VTT

1U_0201_6.3V6K

1U_0201_6.3V6K

22U_0603_6.3V6M

CD63

1

1

2

2

1U_0201_6.3V6K

CD57

CD56

CD58

1

1

2

2

+1.2V_MEM

1U_0201_6.3V6K

CD64

1

2

10U_0402_6.3V6M

10U_0402_6.3V6M

CD90

CD93

1

1

2

2

2

1U_0201_6.3V6K

10U_0402_6.3V6M

@

CD96

1

1

2

2

For VDDQ

1U_0201_6.3V6K

1U_0201_6.3V6K

CD92

CD99

1

1

2

2

1U_0201_6.3V6K

1U_0201_6.3V6K

CD97

CD89

1

1

2

2

1U_0201_6.3V6K

1U_0201_6.3V6K

CD95

1

2

1U_0201_6.3V6K

CD91

CD86

1

1

2

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size

Size

Size

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

LPDDR3

LPDDR3

Document Number Re v

Document Number Re v

Document Number Re v

LPDDR3

LA-F292P

LA-F292P

LA-F292P

1

0.1U_0201_10V6K

CD85

CD87

CD84

1

1

2

2

21 60Tuesday, November 14, 2017

21 60Tuesday, November 14, 2017

21 60Tuesday, November 14, 2017

CD94

CD88

1

1

2

2

1.0

1.0

1.0

0.1U_0201_10V6K

0.1U_0201_10V6K

0.1U_0201_10V6K

5

smd.db-x7.ru

4

3

2

1

For passive level shifter from PS8339

1 2

+5V_RUN

+5V_ALW

D D

1 2

LV31 4.3NH_LQG15HS4N3S02D_0.3NHEMI@

LV3

@EMI@

1

1

2

2

HCM1012GH900BP_4P

1 2

LV32 4.3NH_LQG15HS4N3S02D_0.3NHEMI@

1 2

LV33 4.3NH_LQG15HS4N3S02D_0.3NHEMI@

@EMI@

1

1

2

2

HCM1012GH900BP_4P

1 2

LV34 4.3NH_LQG15HS4N3S02D_0.3NHEMI@

1 2

LV35 4.3NH_LQG15HS4N3S02D_0.3NHEMI@

@EMI@

1

1

2

2

HCM1012GH900BP_4P

1 2

LV36 4.3NH_LQG15HS4N3S02D_0.3NHEMI@

1 2

LV37 15NH_LQG15HS15NJ02D_450MA_5%EMI@

@EMI@

1

1

2

2

HCM1012GH900BP_4P

1 2

LV38 15NH_LQG15HS15NJ02D_450MA_5%EMI@

1 2

1 2

RV316 2.2K_0402_5%

1 2

RV315 2.2K_0402_5%

LV6

LV9

LV12

4

3

4

3

4

3

4

3

+VHDMI_VCC

HDMI_RD_HPD

HDMI_TX_P2

HDMI_TX_N2

HDMI_TX_P1

HDMI_TX_N1

HDMI_TX_P0

HDMI_TX_N0

HDMI_CLKP

HDMI_CLKN

RV21 20K_0402_5%

4

AR_DP1_P0<23>

AR_DP1_N0<23>

AR_DP1_P1<23>

C C

AR_DP1_N1<23>

AR_DP1_P2<23>

AR_DP1_N2<23>

AR_DP1_P3<23>

AR_DP1_N3<23>

B B

AR_DP1_HPD<23>

+3.3V_RUN

A A

AR_DP1_CTRL_CLK<23>

AR_DP1_CTRL_DATA<23>

DMN65D8LDW-7_SOT363-6

1 2

CV31 0.1U_0201_25V6K

1 2

CV32 0.1U_0201_25V6K

1 2

CV33 0.1U_0201_25V6K

1 2

CV34 0.1U_0201_25V6K

1 2

CV35 0.1U_0201_25V6K

1 2

CV36 0.1U_0201_25V6K

1 2

CV37 0.1U_0201_25V6K

1 2

CV38 0.1U_0201_25V6K

+3.3V_RUN

1M_0402_5%

RV20

1 2

5

QV3B

S

L2N7002W T1G_SC-70-3

2

DMN65D8LDW-7_SOT363-6

1

6

34

G

QV5

123

D

QV3A

HDMI_CTRL_CLK

HDMI_CTRL_DATA

5

HDMI_L_TX_P2

4

3

4

3

4

3

4

3

EMI@

RV26
360_0402_5%

1 2

HDMI_L_TX_N2

HDMI_L_TX_P1

EMI@

RV29
360_0402_5%

1 2

HDMI_L_TX_N1

HDMI_L_TX_P0

EMI@

RV32
360_0402_5%

1 2

HDMI_L_TX_N0

HDMI_L_CLKP

EMI@

RV35
360_0402_5%

1 2

HDMI_L_CLKN

HDMI_TX_P2
HDMI_TX_N2
HDMI_TX_P1
HDMI_TX_N1
HDMI_TX_P0
HDMI_TX_N0
HDMI_CLKP
HDMI_CLKN

RV10 470_0402_1%
RV11 470_0402_1%
RV12 470_0402_1%
RV13 470_0402_1%
RV14 470_0402_1%
RV15 470_0402_1%
RV16 470_0402_1%
RV17 470_0402_1%

+3.3V_RUN

3

RV314 0_0201_5%@

1 2

RV313 0_0201_5%@

0.1U_0201_10V6K

@

CV39

1

2

+3.3V_RUN

+VHDMI_IN

1

IN

GND2OUT

AP2330W-7_SC59-3

UV2

3

12

RV19@10K_0402_5%

+VHDMI_VCC

0.1U_0201_10V6K

1

@

CV40

2

HDMI_RD_HPD

HDMI_CTRL_DATA
HDMI_CTRL_CLK

HDMI_CEC
HDMI_L_CLKN

HDMI_L_CLKP
HDMI_L_TX_N0

HDMI_L_TX_P0
HDMI_L_TX_N1

HDMI_L_TX_P1
HDMI_L_TX_N2

HDMI_L_TX_P2

10U_0402_10V6M

12

LINK 099BKAC19YBLCNF DONE

+3.3V_ALW

12

RV312
10K_0201_5%

DISPLAY_HPD_EC# <36>

1

HDMI_OB

2

G

2

G

D

QV6
L2N7002W T1G_SC-70-3

S

3

1

D

QV4
L2N7002W T1G_SC-70-3

S

3

HDMI_RD_HPD

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2

RV18 10K_0402_5%

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EX PRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET N OR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY TH IRD
PARTY WITHOUT DELL'S EX PRESS WRITTEN CONSENT.

2

CV41

HDMI connector

JHDMI1

19

HP_DET

18

+5V

17

DDC/CEC_GND

16

SDA

15

SCL

14

Reserved

13

CEC

12

CK-

11

CK_shield

10

CK+

9

D0-

8

D0_shield

7

D0+

6

D1-

5

D1_shield

4

D1+

3

D2-

2

D2_shield

1

D2+

CONCR_099A3AC19JBLCNF

CONN@

20

GND1

21

GND2

22

GND3

23

GND4

DELL CONFIDENTIAL/PROPRIETARY

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date : Sheet of

Date : Sheet of

Date : Sheet of

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

HDMI CONN

HDMI CONN

HDMI CONN

LA-F292P

LA-F292P

LA-F292P

22 60Tuesday, November 14, 2017

22 60Tuesday, November 14, 2017

22 60Tuesday, November 14, 2017

1

1.0

1.0

1.0

5

smd.db-x7.ru

RT4

1 2

3.3K_0402_5%

+3.3V_TBT_LC

UT1A

Y23

PCIE_RX0_P

Y22

PCIE_RX0_N

T23

PCIE_RX1_P

T22

PCIE_RX1_N

M23

PCIE_RX2_P

M22

PCIE_RX2_N

H23

PCIE_RX3_P

H22

PCIE_RX3_N

V19

PCIE_REFCLK_100_IN_P

T19

PCIE_REFCLK_100_IN_N

AC5

PCIE_CLKREQ_N

AB7

DPSNK0_ML0_P

AC7

DPSNK0_ML0_N

AB9

DPSNK0_ML1_P

AC9

DPSNK0_ML1_N

AB11

DPSNK0_ML2_P

AC11

DPSNK0_ML2_N

AB13

DPSNK0_ML3_P

AC13

DPSNK0_ML3_N

Y11

DPSNK0_A UX_P

W11

DPSNK0_A UX_N

AA2

DPSNK0_HPD

Y5

DPSNK0_DDC_CLK

R4

DPSNK0_DDC_DATA

AB15

DPSNK1_ML0_P

AC15

DPSNK1_ML0_N

AB17

DPSNK1_ML1_P

AC17

DPSNK1_ML1_N

AB19

DPSNK1_ML2_P

AC19

DPSNK1_ML2_N

AB21

DPSNK1_ML3_P

AC21

DPSNK1_ML3_N

Y12

DPSNK1_A UX_P

W12

DPSNK1_A UX_N

Y6

DPSNK1_HPD

Y8

DPSNK1_DDC_CLK

N4

DPSNK1_DDC_DATA

Y18

DPSNK_RBIAS

Y4

TDI

V4

TMS

T4

TCK

W4

TDO

H6

RBIAS

J6

RSENSE

A15

PA_RX1_P

B15

PA_RX1_N

A17

PA_TX1_P

B17

PA_TX1_N

A19

PA_TX0_P

B19

PA_TX0_N

B21

PA_RX0_P

A21

PA_RX0_N

Y15

PA_DPSRC_AUX_P

W15

PA_DPSRC_AUX_N

E20

PA_USB2_D_P

D20

PA_USB2_D_N

A5

PA_LSTX

A4

PA_LSRX

M4

PA_DPSRC_HPD

H19

PA_USB2_RBIAS

AC23

THERMDA

AB23

THERMDA

V18

PCIE_ATEST

AC1

TEST_EDM

L15

FUSE_VQP S_64

N15

FUSE_VQP S_128

C23

MONDC_CIO_ 0

C22

MONDC_CIO_ 1

ALPINE-RIDGE_BGA337

+3.3V_TBT_FL ASH_R+3.3V_TBT_FL ASH_R

12

1 2

3.3K_0402_5%

TBT_ROM_HOLD#

TBT_ROM_CLK
TBT_ROM_DI

PCIE_PTX_DRX_P1<10>
PCIE_PTX_DRX_N1<10>

PCIE_PTX_DRX_P2<10>
PCIE_PTX_DRX_N2<10>

PCIE_PTX_DRX_P3<10>
PCIE_PTX_DRX_N3<10>

PCIE_PTX_DRX_P4<10>
PCIE_PTX_DRX_N4<10>

CPU_DP1_P0<6 >
CPU_DP1_N0<6>

CPU_DP1_P1<6 >
CPU_DP1_N1<6>

CPU_DP1_P2<6 >
CPU_DP1_N2<6>

CPU_DP1_P3<6 >
CPU_DP1_N3<6>

CPU_DP1_AUXP<6>

CPU_DP1_AUXN<6>

CPU_DP1_CTRL_CLK<6>

CPU_DP1_CTRL_DATA<6>

CPU_DP2_AUXP<6>

CPU_DP2_AUXN<6>

CT1

0.1U_0201_10V6K

8
7
6
5

CPU_DP2_P0<6>
CPU_DP2_N0<6>

CPU_DP2_P1<6>
CPU_DP2_N1<6>

CPU_DP2_P2<6>
CPU_DP2_N2<6>

CPU_DP2_P3<6>
CPU_DP2_N3<6>

SWAP 0524

UT2

1

CS#

VCC
HOLD#(IO3)
CLK
DI(IO0)

W25Q8 0DVSSIG_SO8

CT123 0.22U_0201_6.3V6K
CT124 0.22U_0201_6.3V6K

CT125 0.22U_0201_6.3V6K
CT126 0.22U_0201_6.3V6K

@
@

5

2

DO(IO1)

3

WP#(IO2 )

4

GND

1 2

CT2 0 .22U_0201_ 6.3V6K

1 2

CT3 0 .22U_0201_ 6.3V6K

1 2

CT4 0 .22U_0201_ 6.3V6K

1 2

CT5 0 .22U_0201_ 6.3V6K

1 2
1 2

1 2
1 2

CLK_PCIE_P5<11>
CLK_PCIE_N5<11>

CLKREQ_P CIE#5<11>

1 2

CT10 0.1U_0201_10V6K

1 2

CT11 0.1U_0201_10V6K

1 2

CT12 0.1U_0201_10V6K

1 2

CT13 0.1U_0201_10V6K

1 2

CT14 0.1U_0201_10V6K

1 2

CT15 0.1U_0201_10V6K

1 2

CT16 0.1U_0201_10V6K

1 2

CT17 0.1U_0201_10V6K

1 2

CT18 0.1U_0201_10V6K

1 2

CT19 0.1U_0201_10V6K

CPU_DP1_HPD<6>

1 2
1 2

RT341 0_0402_5%
RT342 0_0402_5%

1 2

CT186 0.1U_020 1_10V6K

1 2

CT187 0.1U_020 1_10V6K

1 2

CT183 0.1U_020 1_10V6K

1 2

CT180 0.1U_020 1_10V6K

1 2

CT185 0.1U_020 1_10V6K

1 2

CT179 0.1U_020 1_10V6K

1 2

CT182 0.1U_020 1_10V6K

1 2

CT181 0.1U_020 1_10V6K

1 2

CT178 0.1U_020 1_10V6K

1 2

CT184 0.1U_020 1_10V6K

CPU_DP2_HPD<6>

12

RT38 14K_ 0402_1%

1 2

RT39 4.75K_0402 _0.5%

TBTB_RX2P<29>
TBTB_RX2N<29>

TBTB_TX2P<29>
TBTB_TX2N<29>

TBTB_TX1P<29>
TBTB_TX1N<29>

TBTB_RX1P<29>
TBTB_RX1N<29>

TBTB_AUXP<26>
TBTB_AUXN<26>

TBTB_USB20_P<26>
TBTB_USB20_N<26>

TBTB_LSTX<26>
TBTB_LSRX<26>
TBTB_HPD<26,36>

12

RT41 499_0201_1%

RT2

RT3

1 2

1 2

2.2K_0402_5%

TBT_ROM_CS#
TBT_ROM_DO
TBT_ROM_WP #

2.2K_0402_5%

PCIE_PTX_C_DRX_P1
PCIE_PTX_C_DRX_N1

PCIE_PTX_C_DRX_P2 PCIE_PRX_C_DTX_P2
PCIE_PTX_C_DRX_N2

PCIE_PTX_C_DRX_P3
PCIE_PTX_C_DRX_N3

PCIE_PTX_C_DRX_P4
PCIE_PTX_C_DRX_N4

CPU_DP1_P0_C
CPU_DP1_N0_C

CPU_DP1_P1_C
CPU_DP1_N1_C

CPU_DP1_P2_C
CPU_DP1_N2_C

CPU_DP1_P3_C
CPU_DP1_N3_C

CPU_DP1_AUXP_C
CPU_DP1_AUXN_C

CPU_DP1_HPD
DPSNK0_DDC_CLK

DPSNK0_DDC_DATA
CPU_DP2_P0_C

CPU_DP2_N0_C
CPU_DP2_P1_C

CPU_DP2_N1_C
CPU_DP2_P2_C

CPU_DP2_N2_C
CPU_DP2_P3_C

CPU_DP2_N3_C
CPU_DP2_AUXP_C

CPU_DP2_AUXN_C
CPU_DP2_HPD
DPSNK1_DDC_CLK

SNK0_CONFIG1
DPSNK_RBIAS

TBT_JTAG_TDI
TBT_JTAG_TMS
TBT_JTAG_TCK
TBT_JTAG_TDO

TBT_RBIAS
TBT_RSENSE

TBTB_LSTX
TBTB_LSRX
TBTB_HPD

TBTB_USB2_RBIAS TBTA_USB2_RBIAS

RT1

D D

C C

B B

Type C

A A

4

RT6

RT5

RT7

10K_0402_5%

10K_0402_5%

1 2

10K_0402_5%

1 2

1 2

Rework Debug Pin1 +3.3V_TBT_LC, Pin6 GND

SINK PORT 0

SINK PORT 1

MISC

Port A

TBT PORTS

POC

DEBUG

4

RT8

10K_0402_5%

PCIe GEN3

1 2

TBT_JTAG_TDI

TBT_JTAG_TMS
TBT_JTAG_TCK
TBT_JTAG_TDO

DPSRC_ML0 _P
DPSRC_ML0 _N

DPSRC_ML1 _P
DPSRC_ML1 _N

DPSRC_ML2 _P
DPSRC_ML2 _N

DPSRC_ML3 _P
DPSRC_ML3 _N

DPSRC_AUX _P
DPSRC_AUX _N

SOURCE PORT 0

LC GPIOPOC GPIO

TEST_PWR_ GOOD

Misc

PB_DPSRC_AUX_P
PB_DPSRC_AUX_N

PORT B

POC

PB_DPSRC_HPD
PB_USB2_RBIAS

MONDC_DPSNK_0
MONDC_DPSNK_1

MONDC_DPSRC

PCIE_TX0_P

PCIE_TX0_N

PCIE_TX1_P

PCIE_TX1_N

PCIE_TX2_P

PCIE_TX2_N

PCIE_TX3_P

PCIE_TX3_N

PERST_N

PCIE_RBIA S

DPSRC_HPD

DPSRC_RBIAS

GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
GPIO_6
GPIO_7

GPIO_8
POC_GPIO _0
POC_GPIO _1
POC_GPIO _2
POC_GPIO _3
POC_GPIO _4
POC_GPIO _5
POC_GPIO _6

TEST_EN

RESET_N

XTAL_25_IN

XTAL_25_OUT

EE_DI

EE_DO

EE_CS_N

EE_CLK

PB_RX1_P
PB_RX1_N

PB_TX1_P
PB_TX1_N

PB_TX0_P
PB_TX0_N

PB_RX0_P
PB_RX0_N

PB_USB2_D_P
PB_USB2_D_N

PB_LSTX

PB_LSRX

MONDC_SVR

ATEST_P
ATEST_N

USB2_ATES T

3

@

TBT_PERST#

PCIE_PRX_C_DTX_P1

V23

PCIE_PRX_C_DTX_N1

V22
P23

PCIE_PRX_C_DTX_N2

P22

PCIE_PRX_C_DTX_P3

K23

PCIE_PRX_C_DTX_N3

K22

PCIE_PRX_C_DTX_P4

F23

PCIE_PRX_C_DTX_N4

F22

TBT_PERST#

L4

TBT_PCIE_RBIAS

N16

AR_DP1_P 0

R2

AR_DP1_N0

R1

AR_DP1_P 1

N2

AR_DP1_N1

N1

AR_DP1_P 2

L2

AR_DP1_N2

L1

AR_DP1_P 3

J2

AR_DP1_N3

J1
W19

Y19

AR_DP1_HPD

G1

TBT_DP_RBIAS

N6

TBT_I2C_SDA

U1

TBT_I2C_SCL

U2

TBT_ROM_WP #

V1

TBT_TMU_CLK_OUT

V2

PCIE_W AKE#_AR

W1

TBT_CIO_PLUG _EVENT#

W2

AR_DP1_CTRL_DATA

Y1

AR_DP1_CTRL_CLK

Y2

TBT_SRC_CFG1

AA1

TBTB_I2C_INT_R

J4

TBTA_I2C_INT_R

E2

RTD3_USB_P WR_EN

D4

TBT_FORCE_PW R

H4

TDOCK_BATLOW#

F2

SIO_SLP_S3#

D2

RTD3_CIO_PW R_EN_R

F1
E1
AB5
F4
D22

D23
AB3

AC4
AC3
AB4

B7
A7

A9
B9

A11
B11

A13
B13

Y16
W16

E19
D19

B4
B5
G2

F19
D6
A23

B23
E18
W13
W18
AB2

@

TEST_EN
TEST_PWRG D
TBT_RESET_N_E C
XTAL_25_IN

XTAL_25_OUT XTAL_25_OUT_R
TBT_ROM_DI

TBT_ROM_DO
TBT_ROM_CS#
TBT_ROM_CLK

TBTA_LSTX
TBTA_LSRX
TBTA_HPD

1 2

CT6 0 .22U_0201_ 6.3V6K

1 2

CT7 0 .22U_0201_ 6.3V6K

1 2

CT8 0 .22U_0201_ 6.3V6K

1 2

CT9 0 .22U_0201_ 6.3V6K

1 2

CT127 0.22U_0201_6.3V6K

1 2

CT128 0.22U_0201_6.3V6K

1 2

CT129 0.22U_0201_6.3V6K

1 2

CT130 0.22U_0201_6.3V6K

1 2

RT34 3.01K_0402 _1%

AR_DP1_HPD <22>

1 2

RT35 14K_0402_1 %~D

TBT_I2C_SDA <25,26>
TBT_I2C_SCL <25,26>

TBT_CIO_PLUG _EVENT# <12>
AR_DP1_CTRL_DATA <22>
AR_DP1_CTRL_CLK <22>

@

1 2

RT409 0_0402_5%

@

1 2

RT410 0_0402_5%

TBT_FORCE_PW R <6>
SIO_SLP_S3# <11,36,37>

1 2

RT392 0_0402_5%

1 2

RT36 100_ 0402_5%

1 2

RT37 100_ 0402_5%

TBT_RESET_N_E C <25,26,36>

1 2

@

1 2

RT394 0_0402_5%

@

RT40 0_0402_5%

TBTA_RX2P <28>
TBTA_RX2N <28>

TBTA_TX2P <28>
TBTA_TX2N <28>

TBTA_TX1P <28>
TBTA_TX1N <28>

TBTA_RX1P <28>
TBTA_RX1N <28>

TBTA_AUXP <25>

TBTA_AUXN <25>
TBTA_USB20_P <25>

TBTA_USB20_N <25>

TBTA_LSTX <25>

TBTA_LSRX <25>

TBTA_HPD <25,36>

1 2

RT42 499_0201_1%

PCH_TBT_PERS T#

RTD3 SELECT<23,36>

12

RT9 0_0402_5%

12

1 2

RT419 0_0402_5%NRTD3@

1 2

RT420 0_0402_5%@RTD3@

AR_DP1_P 0 <22>

AR_DP1_N0 <22>

AR_DP1_P 1 <22>

AR_DP1_N1 <22>

AR_DP1_P 2 <22>

AR_DP1_N2 <22>

AR_DP1_P 3 <22>

AR_DP1_N3 <22>

PCIE_W AKE#_AR

TBTB_I2C_INT
TBTA_I2C_INT

XTAL_25_IN_R

27P_040 2_50V8J

SWAP 0524

Reserve for TBT RTD3 Support 20170807

support TBT RTD3 & non TBT RTD3

1 2

RT444 0_ 0402_5%RTD3@

1 2

RT446 0_ 0402_5%RTD3@

12

RTD3@

RT447
10K_040 2_5%

3

2

+3.3V_TBT_LC+3.3V_TBT_FLASH_R +3.3V_TBTA_FLASH

RT100_0402_5% @

PCH_PLTRST#_ AND

PCH_TBT_PERS T#

PCH_PLTRST#_ AND <11,30,33,38,39>

PCH_TBT_PERS T# <9>

Reserve for TBT RTD3 Support 20170726

PCIE_PRX_DTX_P1 <10>
PCIE_PRX_DTX_N1 <10>

PCIE_PRX_DTX_P2 <10>
PCIE_PRX_DTX_N2 <10>

PCIE_PRX_DTX_P3 <10>
PCIE_PRX_DTX_N3 <10>

PCIE_PRX_DTX_P4 <10>
PCIE_PRX_DTX_N4 <10>

AR_DP1_P 0 A R_DP1_N0

1 2

CT201 1P_0201_50V8C@

AR_DP1_P 1
AR_DP1_P 2
AR_DP1_P 3

NRTD3@

1 2

RT421 0_0402_5%

@

1 2

RT422 0_0402_5%

@RTD3@

1 2

RT454 0_0402_5%

TBTB_I2C_INT <26>
TBTA_I2C_INT <25>

RTD3_CIO_PW R_EN <9>

1

CT20

2

UT33

1

NO
NC3COM

6

GND

IN

TS5A3159ADCKR_SC70-6

RTD3@

PROPRIETARY NOTE:
THIS SHEET OF EN GINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER P ROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

PCIE_W AKE# <33,37,39>
PCH_PCIE_ WAKE# <11, 36,37>
CLKREQ_P CIE#2_R <11>

5/24 Change

YT1

3

IN

OUT

4

GND

GND

20PF 30P PM FL2500123Z

+3.3V_AL W

0.1U_040 2_25V6

1 2

5

V+

TBT_PERST#_RPCH_PLTRST#_AND

4
2

1
2

RTD3@

CT238

AR_DP1_N1

1 2

CT202 1P_0201_50V8C@

AR_DP1_N2

1 2

CT203 1P_0201_50V8C@

AR_DP1_N3

1 2

CT204 1P_0201_50V8C

Closr UT1
Intel Review
request

20160324

1

CT21
27P_040 2_50V8J

2

RTD3@

RT443

1 2

0_0402_ 5%

RTD3@

RT442
1M_0402_5%

IN

1 2

L
H

PI3WVR31313A has internal PD 120Kohm

PI3WVR31310 has internal PD 120Kohm

TBT_PERST#

NONC
X

COM

COM

X

2

TBT_CIO_PLUG _EVENT#

Intel review for back-driver

20160627

TBT_RESET_N_E C

AR_DP1_CTRL_DATA
AR_DP1_CTRL_CLK
DPSNK0_DDC_CLK
DPSNK0_DDC_DATA
DPSNK1_DDC_CLK
SNK0_CONFIG1

SNK0_DDC_data/clk – connect to 2k PU only if
SRC0 is connected and support HDMI (a.i HDMI
or DP++ connector). Otherwise can be 100k PD.
SNK1_DDC_data – connect to 100k PD. If SRC0
support HDMI, connect as SNK0_CFG1 to GPU
and/or appropriate AUX/DDC demux control
SNK1_DDC_clk – connect to 100k PD.

PCIE_W AKE#_AR
TBTA_I2C_INT

TBTB_I2C_INT
TBT_I2C_SDA

TBT_I2C_SCL

TDOCK_BATLOW#
TBT_SRC_CFG1
TBT_CIO_PLUG _EVENT#

RTD3_CIO_PW R_EN_R

TBTA_LSRX
TBTA_LSTX
TBTA_HPD
CPU_DP1_HPD

RTD3_CIO_PW R_EN_R

RTD3_USB_P WR_EN
TBT_FORCE_PW R
TBT_TMU_CLK_OUT
CPU_DP2_HPD

TBT_SRC_CFG1
TBTB_LSTX
TBTB_LSRX
TBTB_HPD

AR_DP1_CTRL_DATA
AR_DP1_CTRL_CLK
DPSNK0_DDC_CLK
DPSNK0_DDC_DATA
DPSNK1_DDC_CLK
SNK0_CONFIG1

support TBT RTD3 & non TBT RTD3

CLKREQ_P CIE#2_R
PCH_PCIE_ WAKE#

RT456 0_04 02_5%RTD3@

1 2
1 2

RT445 0_0402_5%@RTD3@

1 2

RT448 0_0402_5%RTD3@

RTD3 SELECT<23,36>

12

RT391 10K_0402_5%

RT11 10K_0402_5%@

RT12 2.2K_0402_5%
RT13 2.2K_0402_5%
RT14 2.2K_0402_5%@
RT15 2.2K_0402_5%@
RT336 2.2K_ 0402_5%

@

RT337 2.2K_ 0402_5%@

RT455 10K_0402_5%RTD3@
RT16 10K_0402_5%

RT17 10K_0402_5%
RT18 2.2K_0402_5%

RT19 2.2K_0402_5%

RT20 10K_0402_5%
RT338 10K_0402_5%
RT371 10K_0402_5%@

RT372 10K_0402_5%

@RTD3@

RT21 1M_0402_5%
RT22 1M_0201_5%
RT23 100K_0402_5%
RT24 100K_0402_5%
RT25 100K_0402_5%NRTD3@
RT26 100K_0402_5%
RT27 10K_0402_5%
RT28 100K_0402_5%
RT29 100K_0402_5%

RT30 1M_0402_5%@
RT31 1M_0402_5%
RT32 1M_0402_5%
RT33 100K_0402_5%

RT124 100K_0402_5%@
RT125 100K_0402_5%@
RT126 100K_0402_5%@
RT127 100K_0402_5%@
RT128 100K_0402_5%
RT129 100K_0402_5%

Reserve for TBT RTD3 Support 20170808

1

6

RTD3@

RT449
10K_040 2_5%

DELL CONFIDENTIAL/PROPRIETARY

Title

Title

Title

Size

Size

Size

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

For kirkwood

+3.3V_AL W_PCH

1 2

+3.3V_TBT

1 2

1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2

1 2
1 2

1 2

1 2
1 2
1 2

1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2
1 2
1 2

+3.3V_AL W

UT32

5

NO

V+

4

NC3COM

2

GND

IN

TS5A3159ADCKR_SC70-6

RTD3@

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

TBT-AR-DP(1/2) DP, PCIE

TBT-AR-DP(1/2) DP, PCIE

TBT-AR-DP(1/2) DP, PCIE

Document Number Re v

Document Number Re v

Document Number Re v

+3.3V_TBT_SX

RTD3@

CT237

0.1U_040 2_25V6

1 2

PCIE_W AKE#_AR_RPCIE_W AKE#

LA-F292P

LA-F292P

LA-F292P

1

Need to check 20160310

Intel review request
for TBT RTD3

20170810

Need to check 20160310

RTD3@

RT441

1 2

0_0402_ 5%

RTD3@

RT440
1M_0402_5%

IN

1 2

HLCOM

23 60Tuesday, November 14, 2017

23 60Tuesday, November 14, 2017

23 60Tuesday, November 14, 2017

PCIE_W AKE#_AR

NC NO

COMXX

1.0

1.0

1.0

A

smd.db-x7.ru

B

C

D

E

For Steamboat 12/14 &kirkwood,For AR

+0.9V_TBT_DP

1

1

1 1

2 2

3 3

+3.3V_TBT_S0 +3.3V_TBT

12

CT67

1U_0402_6.3V6K

4 4

1

CT26

CT25

2

2

1U_0201_6.3V6M

1U_0201_6.3V6M

+0.9V_TBT_PCIE +0.9V_TBT_DP

1

1

CT35

CT34

2

2

1U_0201_6.3V6M

1U_0201_6.3V6M

change pn to SHI0000N600

1 2

LT2 1UH_LQM1 8NN1R0K00D_ 10%

1

1

CT69

CT68

2

2

47U_0603_6.3V6M

47U_0603_6.3V6M

1

1

CT28

CT27

2

2

1U_0201_6.3V6M

1U_0201_6.3V6M

1

1

CT36

CT37

2

2

1U_0201_6.3V6M

1U_0201_6.3V6M

1

CT29

CT30

CT31

2

2

1U_0201_6.3V6M

1U_0201_6.3V6M

1

2

1U_0201_6.3V6M

@

1 2

PAD-OPEN1 x1m

PJP5

+0.9V_TBT_US B

1

CT32

2

1U_0201_6.3V6M

+0.9V_TBT_CIO

1

CT38

2

1U_0201_6.3V6M

+3.3V_TBT+3.3V_RUN

1

CT43

2

1U_0201_6.3V6M

<BOM Structure>

+TBT_SVR_IND

+3.3V_AL W

1

1

1

CT46

CT45

CT44

2

10U_0402_6.3V6M

1

CT49

CT48

2

1U_0201_6.3V6M

1U_0201_6.3V6M

1 2

LT1 0.6UH_MND-04ABIR60M-XG L_20%

CT59

10U_0402_6.3V6M

2

2

10U_0402_6.3V6M

10U_0402_6.3V6M

1

1

CT51

CT50

2

2

1U_0201_6.3V6M

1U_0201_6.3V6M

1

1

CT60

CT61

2

2

1U_0201_6.3V6M

10U_0402_6.3V6M

+3.3V_TBT

VCC3P3_SVR:3.3V @ 0.6A max

1

CT47

2

10U_0402_6.3V6M

1

2

+0.9V_TBT_LVR_OUT

1

2

VCC0P9_SVR:0.9V @ 1.8A max
Minimum of 4vias must be used

1

1

CT53

CT52

2

2

1U_0201_6.3V6M

1U_0201_6.3V6M

1

1

CT56

CT55

2

2

47U_0603_6.3V6M

47U_0603_6.3V6M

1

CT62

2

1U_0201_6.3V6M

+0.9V_TBT_SVR

1

CT54

2

1U_0201_6.3V6M

1

Share Same GND plane

CT57

with SVR_VSS of AR

2

Intel review request

47U_0603_6.3V6M

Change 10U*4 to
47U*3

20160324

+0.9V_TBT_PCIE

+0.9V_TBT_US B

+0.9V_TBT_CIO

+VCC3V3_A NA_PCIE
+VCC3V3_A NA_USB2

1

CT64

2

1U_0201_6.3V6M

PJP6

@

1 2

PAD-OPEN1 x1m

+3.3V_TBT_LC

UT1B

L8

VCC0P9_DP

L11

VCC0P9_DP

L12

VCC0P9_DP

M8

VCC0P9_DP

T11

VCC0P9_DP

T12

VCC0P9_DP

L6

VCC0P9_A NA_DPSRC

M6

VCC0P9_A NA_DPSRC

V11

VCC0P9_A NA_DPSNK

V12

VCC0P9_A NA_DPSNK

V13

VCC0P9_A NA_DPSNK

M13

VCC0P9_P CIE

M15

VCC0P9_P CIE

M16

VCC0P9_P CIE

L19

VCC0P9_A NA_PCIE_1

N19

VCC0P9_A NA_PCIE_1

L18

VCC0P9_A NA_PCIE_2

M18

VCC0P9_A NA_PCIE_2

N18

VCC0P9_A NA_PCIE_2

R15

VCC0P9_USB

R16

VCC0P9_USB

R8

VCC0P9_CIO

R9

VCC0P9_CIO

R11

VCC0P9_CIO

R12

VCC0P9_CIO

L16

VCC3P3_A NA_PCIE

J16

VCC3P3_A NA_USB2

A6

VSS_ANA

A8

VSS_ANA

A10

VSS_ANA

A12

VSS_ANA

A14

VSS_ANA

A16

VSS_ANA

A18

VSS_ANA

A20

VSS_ANA

A22

VSS_ANA

B6

VSS_ANA

B8

VSS_ANA

B10

VSS_ANA

B12

VSS_ANA

B14

VSS_ANA

B16

VSS_ANA

B18

VSS_ANA

B20

VSS_ANA

B22

VSS_ANA

D8

VSS_ANA

D9

VSS_ANA

D11

VSS_ANA

D12

VSS_ANA

D13

VSS_ANA

D15

VSS_ANA

D16

VSS_ANA

D18

VSS_ANA

E8

VSS_ANA

E9

VSS_ANA

E11

VSS_ANA

E15

VSS_ANA

E16

VSS_ANA

E22

VSS_ANA

E23

VSS_ANA

F9

VSS_ANA

F16

VSS_ANA

F20

VSS_ANA

G22

VSS_ANA

G23

VSS_ANA

H1

VSS_ANA

H2

VSS_ANA

H12

VSS_ANA

H13

VSS_ANA

H15

VSS_ANA

H16

VSS_ANA

H20

VSS_ANA

J5

VSS_ANA

J18

VSS_ANA

J19

VSS_ANA

J20

VSS_ANA

J22

VSS_ANA

J23

VSS_ANA

K1

VSS_ANA

K2

VSS_ANA

L5

VSS_ANA

L20

VSS_ANA

L22

VSS_ANA

L23

VSS_ANA

M1

VSS_ANA

M2

VSS_ANA

M5

VSS_ANA

M19

VSS_ANA

M20

VSS_ANA

N5

VSS_ANA

N20

VSS_ANA

N22

VSS_ANA

N23

VSS_ANA

1 2

RT48 0_06 03_5%@

1 2

RT49 0_06 03_5%@

+3.3V_TBT_S0

1

1

CT41

CT42

2

2

1U_0201_6.3V6M

1U_0201_6.3V6M

F8

R6

VCC3P3_LC

VSS_ANAP1VSS_ANAP2VSS_ANAR5VSS_ANA

R18

R19

VCC3P3_SX

GND VCC

VSS_ANA

VSS_ANA

VSS_ANA

R20

R22

R13

H9

VCC3P3A

VCC3P3_S0

VCC0P9_S VR_ANA
VCC0P9_S VR_ANA
VCC0P9_S VR_ANA
VCC0P9_S VR_ANA
VCC0P9_S VR_ANA
VCC0P9_S VR_ANA

VCC0P9_S VR_SENSE

VCC0P9_L VR_SENSE

VSS_ANA

VSS_ANAT1VSS_ANAT2VSS_ANAT5VSS_ANA

T20

R23

U22

A2

VCC3P3_S VR

A3

VCC3P3_S VR

B3

VCC3P3_S VR

L9

VCC0P9_S VR

M9

VCC0P9_S VR

E12
E13
F11
F12
F13
F15
J9

C1

SVR_IND

C2

SVR_IND

D1

SVR_IND

A1

SVR_VSS

B1

SVR_VSS

B2

SVR_VSS

SVR_VSS:Minimum of 4 vias must be used.

F18

VCC0P9_L VR

H18

VCC0P9_L VR

J11

VCC0P9_L VR

H11
V5

VSS_ANA

V6

VSS_ANA

V8

VSS_ANA

V9

VSS_ANA

V15

VSS_ANA

V16

VSS_ANA

V20

VSS_ANA

W5

VSS_ANA

W6

VSS_ANA

W8

VSS_ANA

W9

VSS_ANA

W20

VSS_ANA

W22

VSS_ANA

W23

VSS_ANA

Y9

VSS_ANA

Y13

VSS_ANA

Y20

VSS_ANA

AA22

VSS_ANA

AA23

VSS_ANA

AB6

VSS_ANA

AB8

VSS_ANA

AB10

VSS_ANA

AB12

VSS_ANA

AB14

VSS_ANA

AB16

VSS_ANA

AB18

VSS_ANA

AB20

VSS_ANA

AB22

VSS_ANA

AC6

VSS_ANA

AC8

VSS_ANA

AC10

VSS_ANA

AC12

VSS_ANA

AC14

VSS_ANA

AC16

VSS_ANA

AC18

VSS_ANA

AC20

VSS_ANA

AC22

VSS_ANA

D5

VSS

E4

VSS

E5

VSS

E6

VSS

F5

VSS

F6

VSS

H5

VSS

H8

VSS

J8

VSS

J12

VSS

J13

VSS

J15

VSS

L13

VSS

M11

VSS

M12

VSS

N8

VSS

N9

VSS

N11

VSS

N12

VSS

N13

VSS

T6

VSS

T8

VSS

T9

VSS

T13

VSS

T15

VSS

T16

VSS

T18

VSS

AB1

VSS

AC2

VSS

VSS_ANA

VSS_ANA

U23

1

CT33

2

1U_0201_6.3V6M

1

1

CT39

CT40

2

2

1U_0201_6.3V6M

1U_0201_6.3V6M

+3.3V_VDD_PIC +3.3V_TBT_SX

1

CT63

2

1U_0201_6.3V6M

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

PROPRIETARY NOTE:
THIS SHEET OF EN GINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER P ROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

A

B

C

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

D

Title

Title

Title

Size

Size

Size

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

Compal Electronics, Inc.

TBT-AR-SP(2/2) PWR,VSS

TBT-AR-SP(2/2) PWR,VSS

TBT-AR-SP(2/2) PWR,VSS

Document Number Re v

Document Number Re v

Document Number Re v

LA-F292P

LA-F292P

LA-F292P

E

24 60Tuesday, November 14, 201 7

24 60Tuesday, November 14, 201 7

24 60Tuesday, November 14, 201 7

1.0

1.0

1.0

5

smd.db-x7.ru

D D

5/24 Change ROM From TBTA to TBTB
5/24 Del FLASH Conn.

+3.3V_TBTA_FLASH

C C

USB20_P3<10>
USB20_N3<10>

TBTA_USB20_P<23>
TBTA_USB20_N<23>

B B

DIV = R2/(R1+R2)

A A

0.70

DIV_maxDIV_min

0.080.00

0.180.10

0.280.20

0.380.30

0.480.40

0.580.50

0.680.60

1.00 7

Config uration

0

1

2

3

4

5

6

Descrip tionFactory Device

UFP only
5V @0.9A Sink capability with "Ask for Max/" for
anything from 0.9 -3.0A
TBT Alternate Modes not supported
DisplayPort Alternate Modes not sup ported
TI VID supported

UFP only
5V @0.9A Sink capability with "Ask for Max/" for
anything from 0.9 -3.0A
TBT Alternate Modes not supported
DisplayPort Alternate Modes -Sink , C and D pin configuration
TI VID supported

UFP only
5V @3.0A Source capability
TBT Alternate Modes not supported
DisplayPort Alternate Modes not sup ported
TI VID supported

UFP only
5V @3.0A Source capability
TBT Alternate Modes not supported
DisplayPort Alternate Modes -Sink , C and D pin configuration
TI VID supported

DRP
5V @0.9-3.0A Sink capability
5V @3.0A Source capability
TBT Alternate Modes not supported
DisplayPort Alternate Modes not sup ported
TI VID supported
Accepts data and power role swaps, but does not
initiat e.

DRP
5V @0.9-3.0A Sink capability
5V @3.0A Source capability
TBT Alternate Modes not supported
DisplayPort Alternate Modes - Source, C, D, and E
pin configurations.
TI VID supported
Accepts power role swaps but will not ini tiate.
Accepts data role swap to UFP and can i nitiate.

DRP
5V @0.9-3.0A Sink capability
5V @3.0A Source capability
TBT Alternate Modes not supported
DisplayPort Alternate Modes - Source, C, D, and E
pin configurations.
TI VID supported
Accepts power role swaps but will not ini tiate.
Accepts data role swap to DFP and can i nitiate.

Infinite boot retry from Flash to Hos t I/F cycles.

5

12
12

12
12

Route in pass through manner so AUX can be snooped by 546

10K_0402_1%

1 2
12

43K_0402_1%

RT4010_0402_5% @
RT4020_0402_5% @

@

RT4030_0402_5%

@

RT4040_0402_5%

RT81 100K_0402_5 %@

MUX1_FLIP_SEL/MUX1_USB_SEL control by:
GPIO: Pop RT69,RT90;Depop RT375,RT376
I2C:Depop RT69,RT90;pop RT375,RT376

+3.3V_TBTA_FLASH

RT76

PD1_GPIO8

RT377

PD1_USB20_P
PD1_USB20_N

PD1_USB20_P
PD1_USB20_N

UART_MOSI

12

UART_MISO

12

RT821M_0402_5%@

4

12

12

4

UPD2_SMBCLK<36>

UPD2_SMBDAT<36>

TI is 3x1uf

5/24 Change

CHEC K

RT375 0_0402_5%@
RT376 0_0402_5%@

TBTA_AUXN_C

RT95100K_0201_5%

TBTA_AUXP_C

RT96100K_0201_5%

UPD2_SMBINT#<36>

1

1

CT71

2

2

2.2U 16V K X5R 0402

EN_PD_HV_1<57>
AC1_DISC#<56,57>

TBTA_HPD<23,36>

+3.3V_TBTA_FLASH

UART_MOSI_R<26>
UART_MISO_R<26>

Reserve Share ROM solution
Because TPS65982D ha s internal ROM

TBTA_LSTX<23>
TBTA_LSRX<23>

1 2
1 2

+VCC1V8D_TBTA_LDO

+3.3V_VDD_PIC

126

QT1A

@

DMN66D0LDW-7_SOT363-6

@

1 2

RT58 0_0402_5%

DMN66D0LDW-7_SOT363-6

@

RT59 0_0402_5%

@

1 2

RT60 0_0402_5%

+TBTA_LDO_BMC
+VCC1V8D_TBTA_LDO
+VCC1V8A_TBTA_LDO

1

CT72

2

2.2U 16V K X5R 0402

@

RT345 0_0402_5%

@

RT346 0_0402_5%

RT97 0_0402_5%@

+3.3V_VDD_PIC

+3.3V_ALW

CT73

2.2U 16V K X5R 0402

+3.3V_TBTA_FLASH

+3.3V_ALW

RT218 100K_0402_5%
RT219 100K_0402_5%
RT220 100K_0402_5%
RT221 3.3K_0402_0.5%

UART_MOSI

1 2

UART_MISO

1 2

RT86 1M_0402_5%

TBTA_LSTX
TBTA_LSRX

TBTA_LSTX
TBTA_LSRX

UPD1_SMBUS_CLK_Q TBTA_DEBUG1
UPD1_SMBUS_DAT_Q

TBTA_AUXP<23>
TBTA_AUXN<23>

1 2

UPD1_SMBUS_CLK_Q

5

UPD1_SMBUS_DAT_Q

34

QT1B

@

1 2

UPD1_SMBINT#_R

+5V_ALW

PJP8

PAD-OPEN 1x3m

5/24 Change RT63 to @

1 2

RT450 0_ 0402_5%@

1 2

@

RT451 0_ 0402_5%

12

RT663.3K_0402_5% @

12

RT673.3K_0402_5% @

12

RT6810K_0402_5% @

12
12
12
12
12
12
12
12

12
12
12
12

RT83 0_0402_5%@

12

1 2

@

1 2

RT87 0_0402_5%

@

RT88 0_0402_5%

1 2
1 2

RT89 0_0402_5%@
RT90 0_0402_5%@

1 2

@

1 2

RT92 0_0402_5%

@

RT93 0_0402_5%

1 2

CT80 0.1U_0201_10V6K

1 2

CT81 0.1U_0201_10V6K

+3.3V_TBTA_FLASH

@

RT98

0_0402_5%

1 2

12

@

RT99

0_0402_5%

12

TBT_I2C_SDA< 23,26>
TBT_I2C_SCL<23,26>
TBTA_I2C_INT<23>

@

RT690_0402_5%

@

RT700_0402_5%
RT711M_0402_5%

@

RT720_0402_5%

@

RT730_0402_5%
RT740_0402_5% @
RT750_0402_5%

@

RT3390_0402_5% @

3

TI is 1x47uf+1x0.1uf

1

2

1

CT74

2

1U_0402_10V6K

UPD1_SMBUS_DAT_Q
UPD1_SMBUS_CLK_Q
UPD1_SMBINT#_R

MUX1_FLIP_SEL_R
EN_PD_HV_1_R
PD1_GPIO2
AC1_DISC#_R
TBTA_HPD_R
OTG_ID1
PD1_GPIO6
PD1_GPIO7
PD1_GPIO8

TBTA_ROM_CLK_PD
TBTA_ROM_DI_PD
TBTA_ROM_DO_PD
TBTA_ROM_CS#_PD

PD1_USB20_P
PD1_USB20_N

12

12
12

TBTA_MRESET

TBTA_LSTX_R
TBTA_LSRX_R

TBTA_DEBUG3
TBTA_DEBUG4

TBTA_DEBUG2

TBTA_AUXP_C
TBTA_AUXN_C

TBTA_ROSC

12

RT100

15K_0402_1%

3

1

CT75

2

22U_0805_25V6M

RT63 0_0402_5%@

RT840_0402_5% @
RT850_0402_5% @

CT76

22U_0805_25V6M

1 2

D10
G11
C10
E10
G10

E11

F10

1

1

CT77

2

2

22U_0805_25V6M

UT5

F1

I2C_ADDR

D1

I2C_SDA1

D2

I2C_SCL1

C1

I2C_IRQ1_N

A5

I2C_SDA2

B5

I2C_SCL2

B6

I2C_IRQ2_N

B2

GPIO0

C2

GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6

D7

GPIO7

H6

GPIO8

A3

SPI_CLK

B4

SPI_MOSI

A4

SPI_MISO

B3

SPI_SS_N

L5

USB_RP_P

K5

USB_RP_N

E2

UART_TX

F2

UART_RX

F4

SWD_DATA

G4

SWD_CLK

MRESET

L4

TBT_LSTX/R2P

K4

TBT_LSRX/P2R

L3

DIG_AUD_P/DEBUG3

K3

DIG_AUD_N/DEBUG4

L2

DEBUG1

K2

DEBUG2

J1

AUX_P

J2

AUX_N

BUSPOWER_N

G2

R_OSC

2

+TBTA_Vbus_1

12

@

RT397

0_0402_5%

CT78

22U_0805_25V6M

+3.3V_VDD_PIC_PDA

H1

B1

VIN_3V3

VDDIO

A1

+5V_ALW_PDA

A11

B11

H10

K1

A2

LDO_1V8A

LDO_1V8D

GND

HRESET

GNDE5GND

E7

E6

D6

12

RT101

100K_0402_5%

C11

LDO_BMC

GND

G5

PP_CABLE

GND

GNDH4GND

H5

PP_5V0

PP_5V0

GND

GNDF6GNDF7GND

GND

GND

E8

B8

D8

0.22U_0402_16V7K

D11

PP_5V0

PP_5V0

GND

F8

G6

CT87

E1

GND

F5

GNDA6GNDA7GNDA8GND

GNDG7GND

G8

GND

SSH7GNDL1GND

H8

1

2

B7

L11

+TBTA_SENSE

HV_GATE1_A

B10

A10

SENSEP

SENSEN

HV_GATE1B9HV_GATE2

VBUS
VBUS
VBUS
VBUS

VOUT_3V3

LDO_3V3

C_USB_TP

C_USB_TN

C_USB_BP
C_USB_BN

C_CC1
C_CC2

RPD_G1
RPD_G2

DEBUG_CTL1
DEBUG_CTL2

C_SBU1
C_SBU2

RESET_N

TPS65982DCZQZR_BGA96

12

RT103

0_0402_5%

@

Need Link TPS65982D

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

2

1 2

RT64 0_0402_5%@

1 2

RT65 0_0402_5%@

HV_GATE2_A

A9

+TBTA_Vbus_1

TI has 1x1uf

+3.3V_PDA_VOUT

H11

12

J10
J11
K11

H2

G1

K6
L6

K7
L7

L9
L10

WHEN CONNECT BUSPOWERZ TO GND,
CONNECT ALSO RP D_Gn to C_CCn

K9
K10

E4
D5

K8
L8

F11

CT82

1U_0603_25V6K

@

RT395 0_0402_5%

@

RT396 0_0402_5%

TBTA_DBG_CTL1
TBTA_DBG_CTL2

TBTA_SBU1_R

@

TBTA_SBU2_R

@

TBTA_RESET_N_EC_R

1

CT83

2

1 2
1 2

RT108 0_0402_5%
RT109 0_0402_5%

6/20 PN:SA0000AX700

1

For Non-AR port1

+3.3V_TBTA_FLASH

1

CT84

2

1U_0402_10V6K

10U_0603_6.3V6M

TBTA_TOP_P <28>
TBTA_TOP_N <28>

TBTA_BOT_P <28>
TBTA_BOT_N <28>

@

1 2

RT104 0_0402_5%

@

1 2

RT105 0_0402_5%

1 2

CT86 1000P_0402_50V7K

1 2

CT85 1000P_0402_50V7K

TI has 2x220pf

1 2

RT106 10K_0402_5%

1 2

RT107 10K_0402_5%

1 2
1 2

@

1 2

RT110 0_0402_5%

DELL CONFIDENTIAL/PROPRIETARY

Title

Title

Title

Size

Size

Size

Date : Sheet o f

Date : Sheet o f

Date : Sheet o f

+3.3V_TBTA_FLASH

TBTA_SBU1 <28>
TBTA_SBU2 <28>

TBT_RESET_N_EC <23,26,36>

1

CT205

2

0.1U_0402_25V6

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

[Type C]PD Controller TI

[Type C]PD Controller TI

[Type C]PD Controller TI

Document Number Re v

Document Number Re v

Document Number Re v

LA-F292P

LA-F292P

LA-F292P

1

TBTA_CC1 <28>

TBTA_CC2 <28>

25 60Tuesday, November 14, 2017

25 60Tuesday, November 14, 2017

25 60Tuesday, November 14, 2017

1.0

1.0

1.0

5

smd.db-x7.ru

DIV = R2/(R1+R2)

D D

0.70

C C

B B

A A

DIV_maxDIV_min

0.080.00

0.180.10

0.280.20

0.380.30

0.480.40

0.580.50

0.680.60

1.00 7

Config uration

0

1

2

3

4

5

6

Descrip tionFactory Device

UFP only
5V @0.9A Sink capability with "Ask for Max/" for
anything from 0.9 -3.0A
TBT Alternate Modes not supported
DisplayPort Alternate Modes not sup ported
TI VID supported

UFP only
5V @0.9A Sink capability with "Ask for Max/" for
anything from 0.9 -3.0A
TBT Alternate Modes not supported
DisplayPort Alternate Modes -Sink , C and D pin configuration
TI VID supported

UFP only
5V @3.0A Source capability
TBT Alternate Modes not supported
DisplayPort Alternate Modes not sup ported
TI VID supported

UFP only
5V @3.0A Source capability
TBT Alternate Modes not supported
DisplayPort Alternate Modes -Sink , C and D pin configuration
TI VID supported

DRP
5V @0.9-3.0A Sink capability
5V @3.0A Source capability
TBT Alternate Modes not supported
DisplayPort Alternate Modes not sup ported
TI VID supported
Accepts data and power role swaps, but does not
initiat e.

DRP
5V @0.9-3.0A Sink capability
5V @3.0A Source capability
TBT Alternate Modes not supported
DisplayPort Alternate Modes - Source, C, D, and E
pin configurations.
TI VID supported
Accepts power role swaps but will not ini tiate.
Accepts data role swap to UFP and can i nitiate.

DRP
5V @0.9-3.0A Sink capability
5V @3.0A Source capability
TBT Alternate Modes not supported
DisplayPort Alternate Modes - Source, C, D, and E
pin configurations.
TI VID supported
Accepts power role swaps but will not ini tiate.
Accepts data role swap to DFP and can i nitiate.

Infinite boot retry from Flash to Hos t I/F cycles.

USB20_P1<10>
USB20_N1<10>

TBTB_USB20_P<23>
TBTB_USB20_N<23>

+3.3V_TBTB_FLASH

+3.3V_TBTB_FLASH

1 2
12

12
12

12
12

RT50

3.3K_0402_5%

10K_0201_1%

RT172

RT378

43K_0201_1%

RT4050_0201_5% @
RT4060_0201_5% @

RT4070_0201_5% @
RT4080_0201_5% @

12

12

4

+3.3V_TBTB_FLASH +3.3V_TBTB_FLASH

12

CT70

1 2

TBTB_ROM_HOLD#_PD
TBTB_ROM_CLK_PD_R
TBTB_ROM_DI_PD_R

TBTB_ROM_CLK_PD_R
TBTB_ROM_DI_PD_R
TBTB_ROM_DO_PD_R
TBTB_ROM_CS#_PD_R

6/1 PN:SA000095R10

.1U_0402_16V7K

8

VCC

7

HOLD#(IO3)

6

CLK

5

DI(IO0)

W25Q80DVSSIG_SO8

@

RT54 0_0402_5%

@

RT55 0_0402_5%

@

RT56 0_0402_5%

@

RT57 0_0402_5%

DO(IO1)

WP#(IO2)

GND

12
12
12
12

UT6

CS#

TBTB_ROM_CS#_PD_R

1

TBTB_ROM_DO_PD_R

2

TBTB_ROM_WP#_PD

3
4

TBTB_ROM_CLK_PD
TBTB_ROM_DI_PD
TBTB_ROM_DO_PD
TBTB_ROM_CS#_PD

5/24 Change ROM From TBTA to TBTB

TI is 3x1uf

1

2

CT147

2.2U 16V K X5R 0402

PD2_GPIO8

for TI strap pin
need do uble check

UART_MOSI_R

12

RT343100K_0402_5%@

UART_MISO_R

12

RT3441M_0402_5%@

TBTB_AUXN_C

RT204100K_0402_5%

TBTB_AUXP_C

RT205100K_0402_5%

PD2_USB20_P
PD2_USB20_N

PD2_USB20_P
PD2_USB20_N

RT384 0_0402_5%@
RT383 0_0402_5%@

1 2
1 2

+VCC1V8D_TBTB_LDO

EN_PD_HV_2<57>

AC2_DISC#<56,57>

TBTB_HPD< 23,36>

5/24 Change

UART_MISO_R<25>
UART_MOSI_R<25>

TBTB_LSTX<23>
TBTB_LSRX<23>

RT191 0_0201_5%@

3

RT53

RT51

RT52

1 2

1 2

1 2

3.3K_0402_5%

3.3K_0402_5%

3.3K_0402_5%

+5V_ALW

5/24 Change RT159 to non@

+TBTB_LDO_BMC
+VCC1V8D_TBTB_LDO
+VCC1V8A_TBTB_LDO

+3.3V_ALW

1

1

2

2

CT148

CT149

2.2U 16V K X5R 0402

2.2U 16V K X5R 0402

+3.3V_TBTB_FLASH

+3.3V_ALW

@
@

@
@

@

GPIO8: USB_TYPEC_FAULT#

UART_MISO_R
UART_MOSI_R

RT182 1M_0402_5%

TBTB_LSTX
TBTB_LSRX

TBTB_LSTX
TBTB_LSRX

UPD2_SMBUS_CLK_Q TBTB_DEBUG1
UPD2_SMBUS_DAT_Q

TBTB_AUXP<23>
TBTB_AUXN<23>

1 2

PJP10

12

PAD-OPEN 1x3m

+3.3V_VDD_PIC

1 2

@

RT452 0_ 0402_5%

1 2

RT453 0_ 0402_5%@

TBT_I2C_SDA<23,25>
TBT_I2C_SCL<23,25>
TBTB_I2C_INT<23>

12

RT162 3.3K_0402_5%@

12

RT163 3.3K_0402_5%@

12

RT164 10K_0402_5%@

12

RT165 0_0402_5%

12

RT166 0_0402_5%

12

RT167 1M_0402_5%

12

RT168 0_0402_5%

12

RT169 0_0402_5%

12

RT170 0_0402_5%@

12

RT171 0_0402_5%

12

RT340 0_0402_5%@

RT178 0_0402_5%@

RT180 0_0402_5%@
RT181 0_0402_5%@

12

1 2

RT183 0_0201_5%@

1 2

RT184 0_0201_5%@

1 2

RT185 0_0201_5%@

1 2

RT186 0_0201_5%@

1 2

@

1 2

RT188 0_0402_5%

@

RT189 0_0402_5%

1 2

CT156 0.1U_0201_10V6K

1 2

CT157 0.1U_0201_10V6K

+3.3V_TBTB_FLASH

@

RT192

0_0201_5%

1 2

12

RT193

@

0_0201_5%

TI is 1x47uf+1x0.1uf

1

CT142

2

22U_0805_25V6M

1

@

CT150

2

1U_0402_10V6K

UPD2_SMBUS_DAT_Q
UPD2_SMBUS_CLK_Q
UPD2_SMBINT#_R

MUX2_FLIP_SEL_R
EN_PD_HV_2_R
PD2_GPIO2
AC2_DISC#_R
TBTB_HPD_R
OTG_ID2
PD2_GPIO6
PD2_GPIO7
PD2_GPIO8

TBTB_ROM_CLK_PD
TBTB_ROM_DI_PD
TBTB_ROM_DO_PD
TBTB_ROM_CS#_PD

PD2_USB20_P
PD2_USB20_N

12

12
12

TBTB_MRESET

TBTB_LSTX_R
TBTB_LSRX_R

TBTB_DEBUG3
TBTB_DEBUG4

TBTB_DEBUG2

TBTB_AUXP_C
TBTB_AUXN_C

TBTB_ROSC

12

RT194

15K_0402_1%

RT159 0_0402_5%

1

2

UPD1_SMBCLK<36>

UPD1_SMBDAT<36>

1

CT143

2

22U_0805_25V6M

F1
D1

D2
C1

A5
B5
B6

B2

C2
D10
G11
C10

E10

G10

D7

H6

A3

B4

A4

B3

L5

K5

E2

F2

F4

G4

E11

L4

K4

L3

K3

L2

K2

J1

J2

F10

G2

UPD1_SMBINT#<36>

1

CT145

CT144

2

22U_0805_25V6M

22U_0805_25V6M

+3.3V_VDD_PIC_PDB

12

UT11

I2C_ADDR
I2C_SDA1

I2C_SCL1
I2C_IRQ1_N

I2C_SDA2
I2C_SCL2
I2C_IRQ2_N

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8

SPI_CLK
SPI_MOSI
SPI_MISO
SPI_SS_N

USB_RP_P
USB_RP_N

UART_TX
UART_RX

SWD_DATA
SWD_CLK

MRESET

TBT_LSTX/R2P
TBT_LSRX/P2R

DIG_AUD_P/DEBUG3
DIG_AUD_N/DEBUG4

DEBUG1
DEBUG2

AUX_P
AUX_N

BUSPOWER_N

R_OSC

H1

B1

VIN_3V3

DMN66D0LDW-7_SOT363-6

K1

A2

VDDIO

LDO_1V8A

GND

HRESET

GNDE5GND

A1

E6

D6

12

RT195

+3.3V_VDD_PIC

126

QT2A

@

@

1 2

RT150 0_0402_5%

DMN66D0LDW-7_SOT363-6

@

RT151 0_0402_5%

@

1 2

RT156 0_0402_5%

+5V_ALW_PDB

A11

B11

H10

E1

PP_5V0

LDO_BMC

LDO_1V8D

PP_CABLE

GND

GND

GND

GND

GND

GND

GNDH4GND

F5

E7

E8

B8

D8

H5

G5

0.22U_0402_16V7K

100K_0402_5%

C11

PP_5V0

GNDF6GNDF7GND

QT2B

@

1 2

D11

PP_5V0

PP_5V0

GND

F8

G6

CT158

5

GNDA6GNDA7GNDA8GND

GNDG7GND

G8

2

34

B7

GND

SSH7GNDL1GND

H8

1

2

L11

UPD2_SMBUS_CLK_Q

UPD2_SMBUS_DAT_Q

UPD2_SMBINT#_R

+TBTB_Vbus_1

12

@

RT398

0_0402_5%

HV_GATE1_B

+TBTB_SENSE

B10

A10

SENSEP

SENSEN

HV_GATE1B9HV_GATE2

VBUS
VBUS
VBUS
VBUS

VOUT_3V3

LDO_3V3

C_USB_TP

C_USB_TN

C_USB_BP
C_USB_BN

C_CC1
C_CC2

RPD_G1
RPD_G2

DEBUG_CTL1
DEBUG_CTL2

C_SBU1
C_SBU2

RESET_N

TPS65982DCZQZR_BGA96

12

RT196

0_0402_5%

@

1

For Non-AR port2 kirkwood

1 2

RT160 0_0402_5%@

1 2

RT161 0_0402_5%@

HV_GATE2_B

A9

+TBTB_Vbus_1

TI has 1x1uf

+3.3V_PDB_VOUT

CT151

1U_0603_25V6K

1 2
1 2

1

CT152

2

1U_0201_6.3V6M

TBTB_TOP_P <29>
TBTB_TOP_N <29>

TBTB_BOT_P <29>
TBTB_BOT_N <29>

@

+3.3V_TBTB_FLASH

1

2

CT153

10U_0402_6.3V6M

1 2

RT199 10K_0402_5%

1 2

RT200 10K_0402_5%

1 2

RT201 0_0201_5%@

@

1 2

RT202 0_0402_5%

1 2

RT203 0_0402_5%

TBTB_CC1 <29>

TBTB_CC2 <29>

+3.3V_TBTB_FLASH

TBTB_SBU1 <29>
TBTB_SBU2 <29>

TBT_RESET_N_EC <23,25,36>

H11

12

J10
J11
K11

H2

G1

K6
L6

K7
L7

TI has 2x220pf

L9
L10

WHEN CONNECT BUSPOWERZ TO GND,
CONNECT ALSO RP D_Gn to C_CCn

@

K9

RT197 0_0402_5%

@

K10

RT198 0_0402_5%

TBTB_DBG_CTL1

E4

TBTB_DBG_CTL2

D5

TBTB_SBU1_R

K8

TBTB_SBU2_R

L8

TBTB_RESET_N_EC_R

F11

6/20 PN:SA0000AX700

1

1

2

2

CT154

CT155

820P_0402_50V7K

820P_0402_50V7K

Need Link TPS65982D

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Compal Electronics, Inc.

Title

Title

Title

[Type C]PD Controller TI-2

[Type C]PD Controller TI-2

[Type C]PD Controller TI-2

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

Date : Sheet o f

Date : Sheet o f

Date : Sheet o f

LA-F292P

LA-F292P

LA-F292P

1

26 60Tuesday, November 14, 2017

26 60Tuesday, November 14, 2017

26 60Tuesday, November 14, 2017

1.0

1.0

1.0

5

smd.db-x7.ru

4

3

2

1

For kirkwood

+5V_ALW

D D

DT1

+5V_TBT_VBUS

1U_0402_10V6K

1

C C

CT93

2

DA2J10100L SOD323

DA2J10100L SOD323

DT3

1 2

DA2J10100L SOD323

DT38

1 2

DA2J10100L SOD323

12

DT2

12

100K_0402_5%

+5V_TBTA_VBUS_D

+5V_TBTB_VBUS_D

AP2204R-5.0TRG1_SOT89-3

+5V_PD_VDD

0.1U_0201_10V6K

12

VOUT

UT12

1

2

UT8

VCC

GND

1

VCC

2

GND

RT393

3

AP2204R-5.0TRG1_SOT89-3

3

VOUT

@

CT88

1

2

1U_0402_10V6K

1

CT89

2

+TBTA_VBUS_1

+TBTB_VBUS_1

RT111 100K_0402_5%

1U_0603_25V6-K~D

1

CT94

2

1U_0603_25V6-K~D

1

CT167

2

1 2

1

CT90
1U_0402_6.3V6K

2

UT7

9

GND

1

OUT

8

IN

2

NC

7

NC

3

ADJ/NC

6

NC

4

GND

5

EN

AP7361C-FGE-7_U-DFN3030-8_3X3

12

32.4K_0402_1%
RT389

12

RT390

10.2K_0402_1%

place near UT7

+3.3V_VDD_PIC

2.2U_0402_10V6M

0.1U_0402_25V6K

1

12

@

CT91

CT92

2

B B

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

[Type C]PD Power-2

[Type C]PD Power-2

[Type C]PD Power-2

LA-F292P

LA-F292P

LA-F292P

27 60Tuesday, November 14, 2017

27 60Tuesday, November 14, 2017

27 60Tuesday, November 14, 2017

1

1.0

1.0

1.0

5

smd.db-x7.ru

4

3

2

1

For NON AR Config
Rear Side

D D

TBTA_RX1P
TBTA_RX1N

TBTA_SBU2
TBTA_BOT_N_R

TBTA_BOT_P_R
TBTA_CC2TBTA_SBU1

TBTA_TX2N_C
TBTA_TX2P_C

Check ,FROM PWR PAGE

TBTA_RX1P <23>
TBTA_RX1N <23>

1 2

CT100 0.47U_02 01_25V

TBTA_SBU2 <25>

@EMI@

1 2

RT122 0_0402_5%

@EMI@

1 2

RT123 0_0402_5%

TBTA_CC2 <25>TBTA_SBU1<25>

1 2

CT102 0.47U_0201_2 5V

RF Request

+TBTA_VBUS

12P_0402_50V8J

RF@

82P_0402_50V8J

RF@

1

TBTA_BOT_N <25 >

12

CT980.22U_0201_6.3V 6K

12

CT970.22U_0201_6.3V 6K

TBTA_TX2N <23>
TBTA_TX2P <23>

1

CT189

CT190

2

2

+TBTA_VBUS

2

3

1

DT4

ESD@

AZ4024-02S_SOT23-3

+TBTA_VBUS+TBTA_VBUS

JUSBC1

A1

GND

A2

SSTXP1

A3

SSTXN1

A4

VBUS

A5

CC1

A6

DP1

A7

DN1

A8

SUB1

A9

VBUS

A10
A11

A12

1
2

5

JAE_DX07SD24JJ2R1300~D

20160628

AZ5B75-01B.R7G CSP0603P2Y

AZ5B75-01B.R7G CSP0603P2Y

AZ5B75-01B.R7G CSP0603P2Y

AZ5B75-01B.R7G CSP0603P2Y

TOP

SSRXN2
SSRXP2

GND

GND
GND

GND

JAE_DX07 SD24JJ2R130 0~D

CONN@

DT13

ESD@

1 2

DT14

ESD@

1 2

DT17

ESD@

1 2

DT18

ESD@

1 2

12

CT1010.47U_0201_25V

TBTA_TX1P_C
TBTA_TX1N_C

TBTA_CC1
TBTA_TOP_P_R

TBTA_TOP_N_R

TBTA_RX2N
TBTA_RX2P

TBTA_RX1P

TBTA_RX1N

TBTA_TX2P_C

TBTA_TX2N_C

1 2

TBTA_TX1P<23>
TBTA_TX1N<23>

TBTA_TOP_P<25>

C C

B B

TBTA_TOP_N<25> TBTA_BOT_P <25>

TBTA_TX1P_C

AZ5B75-01B.R7G CSP0603P2Y

TBTA_TX1N_C

AZ5B75-01B.R7G CSP0603P2Y

TBTA_RX2N

AZ5B75-01B.R7G CSP0603P2Y

TBTA_RX2P

AZ5B75-01B.R7G CSP0603P2Y

CT95 0.22U_0201_6. 3V6K
CT96 0.22U_0201_6. 3V6K

CT99 0.47U_0201_25V

@EMI@

RT120 0_0402_5%

@EMI@

RT121 0_0402_5%

DT5

ESD@

1 2

DT6

ESD@

1 2

DT9

ESD@

1 2

DT10

ESD@

1 2

1 2

1 2
1 2

12

TBTA_CC1<25>

TBTA_RX2N<23 >
TBTA_RX2P<23>

B12

GND

B11

SSRXP1

B10

SSRXN1

B9

VBUS

B8

SUB2

B7

DN2

B6

DP2

B5

CC2

B4

VBUS

B3

SSTXN2

B2

Bottom

SSTXP2

B1

GND

4

GND

3

GND

6

GND

DT41

TBTA_SBU1
TBTA_TOP_N_R
TBTA_TOP_P_R
TBTA_CC1 TBTA_CC2

A A

5

ESD@

1

1

2

2

4

4

5

5

3

3

8

AZ1045-04F_DFN2510P10E-10-9

9

10

8

9

7

7

6

6

TBTA_SBU1
TBTA_TOP_N_R
TBTA_TOP_P_R
TBTA_CC1

TBTA_SBU2
TBTA_BOT_N_R
TBTA_BOT_P_R

4

DT42

ESD@

1

1

2

2

4

4

5

5

3

3

8

AZ1045-04F_DFN2510P10E-10-9

9

10

8

9

7

7

6

6

TBTA_SBU2
TBTA_BOT_N_R
TBTA_BOT_P_R
TBTA_CC2

Compal Electronics, Inc.

Compal Electronics, Inc.

PROPRIETARY NOTE:
THIS SHEET OF EN GINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER P ROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

3

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

2

Title

Title

Title

Size

Size

Size

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

USB 3.0 CONN TYPE C

USB 3.0 CONN TYPE C

USB 3.0 CONN TYPE C

Document Number Re v

Document Number Re v

Document Number Re v

LA-F292P

LA-F292P

LA-F292P

1

28 60Tuesday, November 14, 2017

28 60Tuesday, November 14, 2017

28 60Tuesday, November 14, 2017

1.0

1.0

1.0

5

smd.db-x7.ru

4

3

2

1

For kirkwood
For NON AR Config
Front Side

D D

TBTB_RX1P
TBTB_RX1N

TBTB_SBU2
TBTB_BOT_N_R

TBTB_BOT_P_R
TBTB_CC2TBTB_SBU1

TBTB_TX2N_C
TBTB_TX2P_C

Check ,FROM PWR PAGE

TBTB_RX1P <23>
TBTB_RX1N <23>

1 2

CT164 0.47U_02 01_25V

TBTB_SBU2 <26>

@EMI@

1 2

RT216 0_0402_5%

@EMI@

1 2

RT217 0_0402_5%

TBTB_CC2 <26>TBTB_SBU1<26>

1 2

CT166 0.47U_02 01_25V

RF Request

+TBTB_VBUS

TBTB_BOT_N <26 >

12P_0402_50V8J

RF@

82P_0402_50V8J

RF@

1

12

CT1620.22U_0201_6 .3V6K

12

TBTB_TX2N <23>

CT1610.22U_0201_6 .3V6K

TBTB_TX2P <23>

1

CT191

CT192

2

2

+TBTB_VBUS

2

3

1

DT21

ESD@

AZ4024-02S_SOT23-3

+TBTB_VBUS+TBTB_VBUS

JUSBC2

A1

GND

A2

SSTXP1

A3

SSTXN1

A4

VBUS

A5

CC1

A6

DP1

A7

DN1

A8

SUB1

A9

VBUS

A10
A11

A12

1
2

5

JAE_DX07SD24JJ2R1300~D

20160628

AZ5B75-01B.R7G CSP0603P2Y

AZ5B75-01B.R7G CSP0603P2Y

AZ5B75-01B.R7G CSP0603P2Y

AZ5B75-01B.R7G CSP0603P2Y

1
2
4
5
3

TOP

SSRXN2
SSRXP2

GND

GND
GND

GND

JAE_DX07 SD24JJ2R130 0~D

CONN@

DT30

ESD@

1 2

DT31

ESD@

1 2

DT34

ESD@

1 2

DT35

ESD@

1 2

DT44

ESD@

10

1

9

2

7

4

6

5

3

8

AZ1045-04F_DFN2510P10E-10-9

12

CT1630.47 U_0201_25V

12

CT1650.47U_0201_25V

TBTB_TX1P_C
TBTB_TX1N_C

TBTB_CC1
TBTB_TOP_P_R

TBTB_TOP_N_R

TBTB_RX2N
TBTB_RX2P

TBTB_RX1P

TBTB_RX1N

TBTB_TX2P_C

TBTB_TX2N_C

TBTB_SBU2
TBTB_BOT_N_R
TBTB_BOT_P_R
TBTB_CC2

1 2

TBTB_TX1P<23>
TBTB_TX1N<23>

TBTB_TOP_P<26>

C C

B B

A A

TBTB_TOP_N<26> TBTB_BOT_P <26>

TBTB_TX1P_C

TBTB_TX1N_C

TBTB_RX2N

TBTB_RX2P

TBTB_SBU1
TBTB_TOP_N_R
TBTB_TOP_P_R
TBTB_CC1

CT159 0.22U_0201_6.3V 6K

1 2

CT160 0.22U_0201_6.3V 6K

@EMI@

RT214 0_0402_5%

@EMI@

RT215 0_0402_5%

DT22

ESD@

1 2

AZ5B75-01B.R7G CSP0603P2Y

DT23

ESD@

1 2

AZ5B75-01B.R7G CSP0603P2Y

DT26

ESD@

1 2

AZ5B75-01B.R7G CSP0603P2Y

DT27

ESD@

1 2

AZ5B75-01B.R7G CSP0603P2Y

DT43

ESD@

1

1

2

2

4

4

5

5

3

3

8

AZ1045-04F_DFN2510P10E-10-9

9

10

8

9

7

7

6

6

1 2
1 2

TBTB_SBU1
TBTB_TOP_N_R
TBTB_TOP_P_R
TBTB_CC1

TBTB_CC1<26>

TBTB_RX2N<23 >
TBTB_RX2P<23>

SSRXP1
SSRXN1

SSTXN2

Bottom

SSTXP2

TBTB_SBU2

9

TBTB_BOT_N_R

8

TBTB_BOT_P_R

7

TBTB_CC2

6

GND

VBUS
SUB2

VBUS

GND

GND
GND

GND

B12
B11

B10
B9
B8
B7

DN2

B6

DP2

B5

CC2

B4
B3

B2
B1

4
3

6

Compal Electronics, Inc.

Compal Electronics, Inc.

PROPRIETARY NOTE:
THIS SHEET OF EN GINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER P ROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

3

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

2

Title

Title

Title

Size

Size

Size

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

USB 3.0 CONN TYPE C-2

USB 3.0 CONN TYPE C-2

USB 3.0 CONN TYPE C-2

Document Number Re v

Document Number Re v

Document Number Re v

LA-F292P

LA-F292P

LA-F292P

1

29 60Tuesday, November 14, 2017

29 60Tuesday, November 14, 2017

29 60Tuesday, November 14, 2017

1.0

1.0

1.0

5

smd.db-x7.ru

JEDP1

D D

41
42
43
44
45

ACES_50398-04041-001

CONN@

+BL_PWR_SRC

0.1U_0603_50V7K

12

@

CV11

C C

Close to JEDP1.17~19

BIA_PWM

4.7K_0402_5%

12

RV1

LINK 50398-04041-001 DONE

20160308

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25

25

26

26

27

27

28

28

29

29

30

30

31

31

32

32

33

33

34

34

35

35

36

36

G1

37

37

G2

38

38

G3

39

39

G4

40

40

G5

+LCDVDD

Close to JEDP1.30~31 Close to JEDP1.11 C lose to JEDP1.1 Close to JEDP1.10

DV1

3

1

2

BAT54CW SOT323

USB20_N5_R
USB20_P5_R

EMI@

DISP_ON

0.1U_0201_10V6K

1

@

CV12

2

EDP_BIA_PWM

BIA_PWM_EC

+3.3V_RUN
+3.3V_CAM

CAM_MIC_CBL_DET# <12>

Pin15: LOOP_BACK

+BL_PWR_SRC

1 2

LV1

BLM15BB221SN1D_2P

EDP_HPD <6>

LCD_TST <36>

+LCDVDD

PANEL_SIZE_DET <12>

EDP_AUXN_C

CV1 0.1 U_0402_25V6

EDP_AUXP _C

CV2 0.1 U_0402_25V6

EDP_TXP0_ C

CV3 0.1 U_0402_25V6

EDP_TXN0_C

CV4 0.1 U_0402_25V6

EDP_TXP1_ C

CV5 0.1 U_0402_25V6

EDP_TXN1_C

CV6 0.1 U_0402_25V6

EDP_TXP2_ C

CV7 0.1 U_0402_25V6

EDP_TXN2_C

CV8 0.1 U_0402_25V6

EDP_TXP3_ C

CV9 0.1 U_0402_25V6

EDP_TXN3_C

CV10 0.1U_0402_25V6

LCD_CBL_DET# <9>

+3.3V_CAM +3.3V_TSP

0.1U_0201_10V6K

1

@

CZ1

2

EDP_BIA_PWM <6>

BIA_PWM_EC <36>

BIA_PWM

12

EMI Request

EDP_HPD

12
12
12
12
12
12
12
12
12
12

0.1U_0201_10V6K

1

@

2

RF Request

+LCDVDD +3.3V_CAM +BL_PW R_SRC

82P_0402_50V8J

RF@

12P_0402_50V8J

RF@

82P_0402_50V8J

RF@

12P_0402_50V8J

RF@

82P_0402_50V8J

12P_0402_50V8J

RF@

1

1

B B

1

CV20

2

2

1

CV21

CV22

CV23

2

2

RF@

1

1

CV24

CV25

2

2

100P_0201_50V8J

CA5RF@

RV7 10 0K_0402_5 %@

CZ2

100P_0201_50V8J

12

CA6RF@

1 2

EDP_AUXN <6>
EDP_AUXP <6>

EDP_TXP0 <6>
EDP_TXN0 <6>
EDP_TXP1 <6>
EDP_TXN1 <6>
EDP_TXP2 <6>
EDP_TXN2 <6>
EDP_TXP3 <6>
EDP_TXN3 <6>

DISP_ON

4.7K_0402_5%

12

RV2

4

+3.3V_RUN

0.1U_0201_10V6K

1

@

CA7

2

BAT54CW SOT323

1

DMIC0 <35>
DMIC_CLK0 <35>

+LCDVDD

Reserve for EA

DV2

3

2

JTS1

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

GND

12

GND

ACES_50208-01001-P03

CONN@

LINK ACES_50208-01201-P01 Done

SP01001UP00 20160711

PANEL_BKLEN <6>

PANEL_BKEN_EC <36>

TOUCH_SCREEN_DET#

3

+3.3V_TSP

TS_I2C_SDA
TS_I2C_SCL

10K_0402_5%

12

RV305

RF Request

+3.3V_TSP

12P_0402_50V8J

RF@

1

CV18

2

For Touchscreen

PCH_PLTRST#_AND <11,23,33,38,39>
TOUCH_SCREEN_PD# <12>

TS_I2C_SDA <9>
TS_I2C_SCL <9>
TS_INT# <6>

TOUCH_SCREEN_DET# <12>

KKW

82P_0402_50V8J

RF@

1

CV19

2

PCH_3.3V_TS_EN<9>

3.3V_TS_EN<36>

Close lid >> TP_EN = 0 >> Disable touch events
Open lid >> TP_EN = 1 >> Enable touch events

2

3

1

ESD depop locat i on

JIR1

1
2
3
4
5

6
GND
GND

ACES_50208-0060N-P0 1

CONN@

Link ACES_50208-0060N-P01 do ne

20160315

+3.3V_RUN

1 2

RV306 0_0402 _5%@

1 2

@

RV323 0_0402 _5%

TOUCH_PANEL_PD#:

USB20_N8 _R
USB20_P8_R

PESD5V0U2BT_SOT23-3

@ESD@

DV4

1
2
3
4
5
6
7
8

12

+5V_ALW

TS_I2C_SDA
TS_I2C_SCL
TS_INT#

IR_CAM_DET# <12>

+3.3V_RUN

100K_0402_5%

RV326

TS_EN

2

1 2

RV98 2.2K_0 402_5%

1 2

RV99 2.2K_0 402_5%

1 2

RV311 100K_ 0402_5%

EXC24CQ9 00U_4P

1 2

LV27

EMI@

TS_I2C_SDA
TS_I2C_SCL

+PWR_SRC

UZ41

1

VOUT

VIN

2

VOUT

VIN

3

ON

4

VBIAS

GND
GND

AOZ1336_DFN8_2X2

RF Request

7
8

6

CT

5
9

+3.3V_TSP

34

+PWR_SRC

1

2

+3.3V_TSP_ UZ41

CV54 33P_0402_50V8JRF@
CV55 33P_0402_50V8JRF@

100P_0402_50V8J

RF@

CZ3

CHECK Power Rail

USB20_N8 <10>

USB20_P8 <10>

1 2
1 2

RF Request

1 2

@

RZ516 0_0402_5%

1 2

CZ305 0.1U_0201_10V6K

1 2

CZ306 470P_0402_50V7K

1

For Kirkwood

+3.3V_RUN

10K_0402_5%

@

RV8

TOUCH_SCREEN_DET#

+3.3V_TSP

1 2

WebCAM

+3.3V_CAM +3.3V_RUN

3.3V_CAM_EN#<11>

A A

USB20_P5<10>

@

RZ380 0_0402_5%

5

1 2

EXC24CQ9 00U_4P

1 2

LZ1

LP2301A LT1G_SOT23-3

EMI@

QZ1

123

D

12

34

S

G

0.1U_0402_25V6K

@

CZ200

USB20_P5_R

USB20_N5_R

Backlight POWER

+PWR_SRC

1000P_0402_50V7K

270K_0402_5%

CV13

RV4

1 2

0.01U_0402_50V7K

1

CV14

2

4

1 2

BL_PWR_SRC_ON

1 2

RV5 47K_0402_5%

EN_INVPWR<36>USB20_N5<10 >

S

4 5

QV1

D

6
2

1

G

AO6405_ TSOP6

3

QV2

L2N7002WT1G_SC-70-3

123

D

S

G

+BL_PWR_SRC

12

0.1U_0603_50V7K

CV15

3

LCDVDD POWER

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER P ROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

+LCDVDD +EDP_VDD

CV16

@

12

10U_0603_10V6M

LCD_VCC_TEST_EN<36>

ENVDD_PCH<6>

PJP12

1 2

PAD-OPEN1 x1m

BAT54CW SOT323

2

+3.3V_ALW

UV24

1

VOUT

2

GND

3

/OC

DV3

2

3

G524B1T11U_SOT23-5

1

EN_LCDPWR

5

VIN

4

EN

0.01UF_0402_25V7K

@

CV17

12

100K_0402_5%

RV3

1 2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size

Size

Size

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

eDP CONN & Touch screen

eDP CONN & Touch screen

eDP CONN & Touch screen

Document Number Re v

Document Number Re v

Document Number Re v

LA-F292P

LA-F292P

LA-F292P

1

30 60Tuesday, November 14, 2017

30 60Tuesday, November 14, 2017

30 60Tuesday, November 14, 2017

1.0

1.0

1.0

A

smd.db-x7.ru

B

C

D

E

RF Request

+3.3V_MMI_IN

12P_0402_50V8J

@RF@

82P_0402_50V8J

@RF@

1

1

CR25

CR26

2

2

1 1

+3.3V_MMI_IN

close to UR1.8 close to UR1.27

0.1U_0201_10V6K

4.7U_0603_6.3V6K

1

CR1

12

2

+1.2V_LDO

4.7U_0603_6.3V6K
CR5

1

12

2 2

2

4.7U_0402_6.3V6M
CR3

12

CR2

+SD40_AV12

1U_0402_6.3V6K

0.1U_0201_10V6K

12

CR6

CR8

close to UR1.11

0.1U_0201_10V6K

10U_0402_6.3V6M

0.1U_0201_10V6K

1

2

CR29

1

CR4

1

CR30

2

2

close to UR1.21close to UR1.6 close to UR1.24

+DV_12S

4.7U_0402_6.3V6M
CR9

12

0.1U_0201_10V6K

1

CR10

2

Swap TX/RX (Based on Vendor Review)
20160323

PJP14

1 2

PAD-OPEN1x2m

+3.3V_MMI_IN+3.3V_RUN

USB20_P6<10>
USB20_N6<10>

USB3_PTX_DRX_P4<10>
USB3_PTX_DRX_N4<10>

USB3_PRX_DTX_P4<10>
USB3_PRX_DTX_N4<10>

@

RR20 0_0402_5%

@

RR21 0_0402_5%
CR31 0.1U_0402_2 5V6
CR32 0.1U_0402_2 5V6

CR13 0.1U_0402_2 5V6
CR14 0.1U_0402_2 5V6

+3.3V_MMI_IN

1 2
1 2

1 2
1 2

1 2
1 2

+3.3V_MMI_IN

+1.2V_LDO

+SD40_AV12
+DV_12S

USB20_P6_R
USB20_N6_R

USB3_PTX_C_DRX_P4
USB3_PTX_C_DRX_N4

USB3_PRX_C_DTX_P4
USB3_PRX_C_DTX_N4

1 2

RR3 10K_0 402_5%

1 2

RR22 10K_0 402_5%

1 2

RR4 6.2K_ 0402_1%

SD_GPIO0
SD_GPIO1

+RREF

11
27

8
6

24
21

9

10

2
3

4
5

29
28

32

1
7

UR1

3V3_IN
D3V3
A3V3
AV12

VDD_LANE
DV12S
DP

DM
SS_RX+

SS_RX­SS_TX+

SS_TX­XTLI

XTLO
GPIO0
GPIO1
RREF

SD_3V3

SD40_VDD2

SDREG

SD_WP

SD_CD#

SD_CLK

SD_CMD

SD_D3
SD_D2
SD_D1
SD_D0

SD40_D1+

SD40_D1-

SD40_D0+

SD40_D0-

EPAD

RTS5330-GR_QFN32_4X4

12
13
14

30
31

17
18

19
20
15
16

22
23
26
25

33

SD/MMCCD#

+SDREG2

CR15 1U_0 402_6.3V6K

SDWP

SD/MMCCLK
SD/MMCCMD

SD/MMCDAT3
SD/MMCDAT2
SD/MMCDAT1/RCLK­SD/MMCDAT0/RCLK+

SD_UHS2_D1P
SD_UHS2_D1N
SD_UHS2_D0P
SD_UHS2_D0N

+3.3V_RUN_CARD
+1.8V_RUN_CARD

1 2

@EMI@

@

@
@
@
@

RR5 0_0402_5%
RR6 0_0402_5%

RR7 0_0402_5%
RR8 0_0402_5%
RR9 0_0402_5%
RR10 0_0402_5%

For USB Interface

1 2
1 2

1 2
1 2
1 2
1 2

SD/MMCCLK_R
SD/MMCCMD_R

SD/MMCDAT3_R
SD/MMCDAT2_R
SD/MMCDAT1/RCLK-_R
SD/MMCDAT0/RCLK+_R

SD/MMCCLK_R

@EMI@

5P_0402_50V8C

12

CR21

EMI depop locat i on

close to UR1.17

20160304 CIS Link

3 3

QR1

HOST_SD_W P#

4 4

High

Low

SDWP _Q SDWP

High

High

Low

Low

High

High

Low

High

STATUS

Write Protect(SD LOCK)

Write Enable

Write Protect(SD& FW LOCK)

Write Protect(FW LOCK)

HOST_SD_WP#<12>

L2N7002WT1G_SC-70-3

1 3

SDWP

D

S

G

2

+3.3V_RUN_CARD +1.8V_RUN_CARD

2

CR17

1 2

CR18

1

0.1U_0201_10V6K

4.7U_0603_6.3V6K

CR38,CR39 n ear JSD1.4 CR40,CR41 near JSD1 .14

JSD1

+3.3V_RUN_CARD
+1.8V_RUN_CARD

2

CR20

CR19

1 2

1

0.1U_0201_10V6K

4.7U_0603_6.3V6K

SD/MMCCMD_R
SD/MMCCLK_R

SD/MMCCD#

SD/MMCDAT0/RCLK+_R
SD/MMCDAT1/RCLK-_R
SD/MMCDAT2_R
SD/MMCDAT3_R

SD_UHS2_D0P
SD_UHS2_D0N
SD_UHS2_D1P
SD_UHS2_D1N

4

VDD1

15

VDD2

3

CMD

5

CLK

9

CD

16

SWIO

7

DAT0/RCLK+

8

DAT0/RCLK-

1

DAT2

2

CD/DAT3

18

D0+

19

D0-

22

D1+

21

D1-

6

VSS1

17

VSS2

20

VSS3

23

VSS4

T-SOL_158-1240902600

CONN@

LINK T-SOL_158-1240902600 DONE
20160329

GND1
GND2
GND3
GND4
GND5

10
11
12
13
14

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS D OCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL . IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

A

B

C

PARTY WITHOUT DE LL'S EXPRESS WRITTEN CONSENT.

D

Title

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

Date : Sheet o f

Date : Sheet o f

Date : Sheet o f

Card Reader RTS5330

Card Reader RTS5330

Card Reader RTS5330

LA-F292P

LA-F292P

LA-F292P

E

31 60Tuesday, November 14, 2017

31 60Tuesday, November 14, 2017

31 60Tuesday, November 14, 2017

1.0

1.0

1.0

5

smd.db-x7.ru

4

3

2

1

Only for Kirkwood

PCIE/USB MUX

D D

USB3_PRX_DTX_P2<10>
USB3_PRX_DTX_N2<10>
USB3_PTX_DRX_P2<10>
USB3_PTX_DRX_N2<10>

PCIE_PRX_DTX_P7<10>
PCIE_PRX_DTX_N7<10>
PCIE_PTX_DRX_P7<10>
PCIE_PTX_DRX_N7<10>

C C

B B

Function
B to A
C to A
All ports Hi-Z,

IC power down

STATE #

CONFIG_0 CONFIG_21CONFIG_3

0

8
14
15

NEED LINK TI HD3SS3212 as main

1 2

CZ150 0.1U_0402_10V7K

1 2

CZ151 0.1U_0402_10V7K

1 2

CZ152 0.22U_0402_10V6K

1 2

CZ153 0.22U_0402_10V6K

NGFF_CONFIG_1<33,36>

SEL PD
L L

LH

HX

CONFIG_1
GND
GND

HIGH
HIGH
HIGH HIGH

GND

HIGH

GND
GND

USB3_PRX_DTX_P2
USB3_PRX_DTX_N2
USB3_PTX_C_DRX_P2
USB3_PTX_C_DRX_N2

PCIE_PRX_DTX_P7
PCIE_PRX_DTX_N7
PCIE_PTX_C_SW_DRX_P7
PCIE_PTX_C_SW_DRX_N7

NGFF_CONFIG_1

GND
GND
GND

HIGH
HIGH

UZ29

19

B0p

18

B0n

17

B1p

16

B1n

15

C0p

14

C0n

13

C1p

12

C1n

9

SEL

2

OEn

HD3SS3212RKSR_VQFN20_2P5X4P5

GND
GND
GND

HIGH
HIGH

1

NC

6

VCC

10

NC

3

A0p

4

A0n

7

A1p

8

A1n

5

GND

11

GND

20

GND

21

PGND

Module Type
SSD-SATA

SSD-PCIE(2 lane)

WWAN

HCA-PCIE(1 lane)

NA

PCIE_PRX_SW_DTX_P7
PCIE_PRX_SW_DTX_N7
PCIE_PTX_SW_DRX_P7
PCIE_PTX_SW_DRX_N7

M3042_PCIE#_SATA

HIGH

LOW
LOW
LOW
LOW

+3.3V_WWAN

.1U_0402_16V7K

.1U_0402_16V7K

1

1

CZ154

CZ155

2

2

PCIE_PRX_SW_DTX_P7 <33>
PCIE_PRX_SW_DTX_N7 <33>
PCIE_PTX_SW_DRX_P7 <33>
PCIE_PTX_SW_DRX_N7 <33>

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date : Sheet of

Date : Sheet of

Date : Sheet of

Compal Electronics, Inc.

USB/PCIE MUX

USB/PCIE MUX

USB/PCIE MUX

LA-F292P

LA-F292P

LA-F292P

1

32 60Tuesday, November 14, 2017

32 60Tuesday, November 14, 2017

32 60Tuesday, November 14, 2017

1.0

1.0

1.0

5

smd.db-x7.ru

+3.3V_WW AN

NGFF slot B Key B

WWAN_P WR_EN

12

RZ43 47K_0402_5%

D D

support PCIE & SATA

WWAN_ANTCTL0_R<34>
WWAN_ANTCTL1_R<34>
WWAN_ANTCTL2_R<34>
WWAN_ANTCTL3_R<34>

C C

+3.3V_WW AN

.047U_0402_16V7K

.047U_0402_16V7K

12

12

CZ18

CZ17

B B

SIM Card Push-Push

100P_0402_50V8J

RF@

12

CZ198

NGFF_CONFIG_0<36>
WWAN_W AKE#<36>

Double check P/N PIN for SATA/PCIE

PCIE_PTX_DRX_N8<10>
PCIE_PTX_DRX_P8<10>

@RF@
@RF@
@RF@
@RF@

68P_0402_50V8J

68P_0402_50V8J

68P_0402_50V8J

@RF@

@RF@

12

12

12

CZ302

CZ303

33P_0402_50V8J

33P_0402_50V8J

22U_0603_6.3V6M

12

12

12

CZ19

CZ20

CZ21

PCIE_PRX_SW_DTX_N7<32>

PCIE_PRX_SW_DTX_P7<32>

PCIE_PTX_SW_DRX_N7<32>

PCIE_PTX_SW_DRX_P7<32>

+SIM_PWR

4.7U_0402_6.3V6M

12

CZ37

NGFF_CONFIG_3<36>

PCIE_PRX_DTX_P8<10>
PCIE_PRX_DTX_N8<10>

1 2

CZ10 0.1U_0402_25V6

1 2

CZ11 0.1U_0402_25V6

CLK_PCIE_N0<11>
CLK_PCIE_P0<11>

12
12

RZ327 0_0402_5%

12

RZ328 0_0402_5%

12

RZ329 0_0402_5%
RZ330 0_0402_5%

@RF@

12

CZ301

UIM_RESET
UIM_CLK

68P_0402_50V8J

@RF@

CZ300

+3.3V_WW AN

12

JSIM1

1
2
3
4

11
12
13

NGFF_CONFIG_1<32,36>

NGFF_CONFIG_2<36>

47P_0402_50V8J

RF@

CZ23

VCC
RST
CLK
NC

GND
GND
GND

JAE_SF51S006V4B
CONN@

P_SENSOR_ACK#_R

@RF@

RF Request

100P_0402_50V8J

RF@

12

12

CZ24

5

GND

6

VPP

7

I/O

8

NC

9

DLSW

10

DTSW

14

GND

15

GND

16

GND

17

GND

USB20_P4_L
USB20_N4_L

PCIE_PRX_L_DTX_N7
PCIE_PRX_L_DTX_P7

PCIE_PTX_L_DRX_N7
PCIE_PTX_L_DRX_P7

PCIE_PTX_C_DRX_N8
PCIE_PTX_C_DRX_P8

WWAN_ANTCTL0
WWAN_A NTCTL1
WWAN_A NTCTL2
WWAN_A NTCTL3

T225PAD~D @

100U_B2_6.3VM_R35M

RF@

RF@

1

CZ26

+

CZ25

2

RI27 0_0402_5%@RF@

1 2

RI28 0_0402_5%@RF@
RI29 0_0402_5%@RF@

1 2

RI30 0_0402_5%@RF@

UIM_DATA

SIM_DET

12

1 2

HCM1012GH900BP_4P

RF@

1 2
1 2

HCM1012GH900BP_4P

RF@

1 2

RZ326 0_0402_5%

2200P_0402_50V7K

LI16

LI17

4

JNGFF2

1

1

3

3

5

5

7

7

9

9

11

11

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

53

53

55

55

57

57

59

59

61

61

63

63

65

65

67

67

69

69

71

71

73

73

75

75

77

GND

LOTES_APCI0242-P001A

LINK OK

PCIE_PRX_L_DTX_N7

PCIE_PRX_L_DTX_P7

34

PCIE_PTX_L_DRX_N7

PCIE_PTX_L_DRX_P7

34

CONN@

3

+3.3V_WW AN

2

2

4

4

6

6

8

8

10

10

20

20

22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

40

42

42

44

44

46

46

48

48

50

50

52

52

54

54

56

56

58

58

60

60

62

62

64

64

66

66

68

68

70

70

72

72

74

74

76

GND

WWAN_RADIO_DIS#<36>

GPS_DISABLE#<36>

USB20_P4<10>

USB20_N4<10>

WWAN_P WR_EN

WWAN_RADIO_DIS#_R

SLOT2_SATA_LED#

HW_GPS_DISABLE#_R

ISH_I2C2_SCL_R
ISH_I2C2_SDA_R

PCH_PLTRST#_AND

PCIE_WAKE#

RZ132 0_0402_5%@

WWAN_COEX3
WWAN_COEX2
WWAN_COEX1

SIM_DET

1 2

RN101 0_0402_5%@

UIM_RESET
UIM_CLK
UIM_DATA

RZ76 0_0402_5%@
RZ77 0_0402_5%@

12

1 2

RZ128 0_0201_5%

@RF@

1 2

RZ129 0_0201_5%

@RF@

1 2

RZ130 0_0201_5%

@RF@

1 2

RB751S-40 SOD-523

1 2

RB751S-40 SOD-523

SAR_DPR#<36>

Q1 L2N700 2WT1G_SC-70-3

RF Request

1 2

RI47 0_0402_5%@RF@

LI8

RF@

1 2

EXC24CQ900U_4P

1 2

RI48 0_0402_5%@RF@

SATALED# <10,3 9,43>

CZ304
close

1 2

JNGFF2

CZ304 68P_0402_50V8JRF@

+SIM_PWR

M3042_DEVSLP <10>

12
12

9/24: Reserve for embedded locat i on ,r ef er I nt el P DG 0. 9

CLKREQ_PCIE#0 <11>

HOST_DEBUG_TX <36,37>

DZ5

DZ6

+1.8V_RUN

2

G

1 3

D

S

USB20_P4_L

USB20_N4_L

34

ISH_I2C2_SCL <9>
ISH_I2C2_SDA <9>

WLAN_COEX3
WLAN_COEX2
WLAN_COEX1

WWAN_RADIO_DIS#_R

HW_GPS_DISABLE#_R

+1.8V_RUN

12

RZ344
10K_0201_1%

P_SENSOR_ACK#_R

WLAN

WIGI

1 2

PCIE_PTX_DRX_P5<10>
PCIE_PTX_DRX_N5<10>

WLAN_WIGIG60GHZ_DIS#<36>

BT_RADIO_DIS#<36>

CZ12 0.1U_0402_25V6

1 2

CZ13 0.1U_0402_25V6

PCIE_PRX_DTX_P5<10>
PCIE_PRX_DTX_N5<10>

CLK_PCIE_P1<11>
CLK_PCIE_N1<11>

CLKREQ_PCIE#1<1 1>

PCIE_WAKE#< 23,37,39>

USB20_N7<10>

USB20_P7<10>

2

80148-3221&80148-4221 Footprint the sam

80148-3221&80148-4221 Footprint the sam

80148-3221&80148-4221 Footprint the sam

80148-3221&80148-4221 Footprint the sam

NGFF slot A Key A

JNGFF1

USB20_P7_L
USB20_N7_L

PCIE_PTX_C_DRX_P5
PCIE_PTX_C_DRX_N5

PCIE_WAKE#

1

1

3

3

5

5

7

7

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

53

53

55

55

57

57

59

59

61

61

63

63

65

65

67

67

69

69

71

71

73

73

75

75

77

GND

LOTES_APCI0241-P001A

CONN@

+3.3V_WLAN

2

2

4

4

6

6

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

40

42

42

44

44

46

46

48

48

50

50

52

52

54

WLAN_WIGIG60GHZ_DIS#_R

54

56

56

58

58

60

60

62

62

64

64

66

66

68

68

70

70

72

72

74

74

76

GND

LINK OK

+3.3V_WLAN

0.01UF_0402_25V7K

12

DZ1

DZ2

1 2

WLAN_WIGIG60GHZ_DIS#_R

RF Request

1 2

RI49 0_0402_5%@RF@

LI9

RF@

EXC24CQ900U_4P

1 2

RI50 0_0402_5%@RF@

BT_RADIO_DIS#_R

34

USB20_N7_L

USB20_P7_L

Place near JNGFF1.72/JNGFF1.74 Place near JNGFF1.2/JNGFF1.4

RF Request

+3.3V_WLAN

15P_0402_50V8J

12

Power Rating TBD

Voltage

PWR

Toleranc e

Rail

+3.3V

1 2

RB751S-40 SOD-523

1 2

RB751S-40 SOD-523

1

Only for Kirkwood

e

e

e

e

PCH_CL_RST1# <8>

PCH_CL_DATA1 <8>
WLAN_COEX3
WLAN_COEX2
WLAN_COEX1

WIGIG_32KHZ
PCH_PLTRST#_AND
BT_RADIO_DIS#_R

ISH_UART0_RXD_R
ISH_UART0_TXD_R
ISH_UART0_CTS#_R
ISH_UART0_RTS#_R
PCH_PLTRST#_AND

PCIE_WAKE#

PCH_CL_CLK1 <8>

@

PCH_PLTRST#_AND <11,23,30,38,39>

RZ78 0_0402_5%@
RZ79 0_0402_5%@
RZ80 0_0402_5%@
RZ81 0_0402_5%@

12

RZ56 0_0402_5%

12
12
12
12

9/24: Reserve for embedded locat i on ,r ef er I nt el P DG 0. 9

0.01UF_0402_25V7K

10U_0402_6.3V6M

0.1U_0201_10V6K

1

1

CZ28

RF@

CZ33

CZ27

CZ30

2

2

12P_0402_50V8J

2.2P_0402_50V8C

RF@

RF@

12

12

12

CZ35

CZ34

0.1U_0201_10V6K

4.7U_0603_6.3V6K

1

12

15P_0402_50V8J

RF@

CZ36

12

CZ29

CZ31

2

Primary Power Aux Power

Peak Normal Normal

SUSCLK <11,39>

ISH_UART0_RXD <9>
ISH_UART0_TXD <9>

ISH_UART0_CTS# <9>

ISH_UART0_RTS# <9>

CZ32

JAE_SF51S006V4DR1000Q LINK DONE
20160321 (Temp symbol is correct, SP number is wrong on DTSW)

+SIM_PWR

A A

UIM_CLK

5

47P_0402_50V8J

@RF@

12

CZ38

@RF@

51_0402_5%

12

RZ334

UIM_DATA UIM_RESET

@RF@

15K_0402_5%

12

RZ335

33P_0402_50V8J

RF@

1

CZ39

2

4

+SIM_PWR

33P_0402_50V8J

RF@

1

CZ40

2

RF Request

0.1U_0402_25V6

RF@

1

CZ41

2

3

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS D OCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL . IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DE LL'S EXPRESS WRITTEN CONSENT.

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

Date : Sheet o f

Date : Sheet o f

Date : Sheet o f

NGFF Card

NGFF Card

NGFF Card
LA-F292P

LA-F292P

LA-F292P

1

33 60Tuesday, November 14, 2017

33 60Tuesday, November 14, 2017

33 60Tuesday, November 14, 2017

1.0

1.0

1.0

5

smd.db-x7.ru

D D

4

3

2

1

Only for Kirkwood

Annt. Control

+3.3V_WW AN

WWAN_ANTCTL0_R<33>
WWAN_ANTCTL1_R<33>
WWAN_ANTCTL2_R<33>

C C

B B

WWAN_ANTCTL3_R<33>

+3.3V_WW AN_MAIN
+3.3V_WW AN_AUX
WWAN_ANTCTL0_R
WWAN_ANTCTL1_R
WWAN_ANTCTL2_R
WWAN_ANTCTL3_R

+3.3V_WW AN

@RF@
@RF@

CZ180 68P_0402_50V8JRF@

1 2

CZ181 68P_0402_50V8JRF@

1 2

CZ182 68P_0402_50V8JRF@

1 2

CZ183 68P_0402_50V8JRF@

1 2

CZ184 68P_0402_50V8JRF@

1 2

CZ185 68P_0402_50V8JRF@

1 2

12

RZ331 0_0402_5%

12

RZ332 0_0402_5%

+3.3V_WW AN_MAIN
+3.3V_WW AN_AUX
WWAN_ANTCTL0_R
WWAN_ANTCTL1_R
WWAN_ANTCTL2_R
WWAN_ANTCTL3_R

JTUN1

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

GND

10

GND

ACES_50208-00801-003

CONN@

Link ACES_50208-00801-003 done
20160315

+3.3V_WW AN_MAIN

0.1U_0201_10V6K

1

CZ186

2

+3.3V_WW AN_AUX

0.1U_0201_10V6K

1

CZ187

2

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS D OCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL . IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

3

PARTY WITHOUT DE LL'S EXPRESS WRITTEN CONSENT.

2

Title

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

Date : Sheet o f

Date : Sheet o f

Date : Sheet o f

RF Tunable Conn

RF Tunable Conn

RF Tunable Conn
LA-F292P

LA-F292P

LA-F292P

1

34 60Tuesday, November 14, 2017

34 60Tuesday, November 14, 2017

34 60Tuesday, November 14, 2017

1.0

1.0

1.0

2

smd.db-x7.ru

+3.3V_RUN_AUDIO_DVDD

+1.8V_RUN

RA3

@

1 2

BLM15PX600SN1D_2P

AUD_HP_OUT_R
AUD_HP_OUT_L

HDA_SYNC_R< 12>

HDA_SDIN0<12>

HDA_SDOUT_R<12>

DMIC_CLK0<30>

0_0603_5%

place close to pin16

LA5

12

place close to pin40

12

CA73 330P_0402_50V8J

12

CA74 330P_0402_50V8J

HDA_BIT_CLK_R

1 2

RA9 33_0402_5 %

Place R A9 close to codec

1 2

RA62 100K_0402_5%

1 2

RA14EMI@ 22_0402_5%

1 2

RA61 100K_0402_5%

1W x 1ch, 4ohm (Transducer spec is 8Ohm/0.5Watt per unit, there are two transducer units in one speaker box.)

Internal Speakers Header

INT_SPK_L+
INT_SPK_L­INT_SPK_R+
INT_SPK_R-

40 mils trace keep 20 mil spacing

1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K

12

1000P_0402_50V7K

12

12

12

CA23EMI@

CA19EMI@

CA22EMI@

1 2

LA6 BLM15PX330SN1D_2PEMI@

1 2

LA7 BLM15PX330SN1D_2PEMI@

1 2

LA8 BLM15PX330SN1D_2PEMI@

1 2

LA9 BLM15PX330SN1D_2PEMI@

CA24EMI@

INT_SPKR_L+
INT_SPKR_L­INT_SPKR_R+
INT_SPKR_R-

AZ5125-02S.R7G_SOT23-3

AZ5125-02S.R7G_SOT23-3

2

3

1

SPK_DET#<12>

@ESD@

@ESD@

2

3

DA7

DA6

Change to 6pin to support 2 SPK vendor
Link ACES _50278-00601-001 DONE
20160325

1

+3.3V_RUN

Close to UA1

B B

Close to UA1 pin6

HDA_BIT_CLK_R

33_0402_5%

12

RA17@EMI@

10P_0402_50V8J

12

CA33@EMI@

Place closely to Pin 14.

AUD_HP_NB_SENSE

12

place close to UA1 pin6

+3.3V_RUN_AUDIO

100K_0402_1%

12

200K_0402_1%

12

DMIC_CLK0

10P_0402_50V8J

CA54@EMI@

RA59

RA60

AUD_SENSE_A

12

0.1U_0402_25V6

@

CA41

Add for solve
pop noise and
detect issue

12

RA58
10K_0402_5%

SPK_DET#

JSPK1

1

1

2

2

3

3

4

4

5

5

6

6

ACES_50278-00601-001

CONN@

SPK_DET#

7

G1

+5V_RUN_AUDIO

8

G2

HDA_BIT_CLK_R<12>

+3.3V_RUN_AUDIO

+1.8V_RUN_AUDIO

0.1U_0201_10V6K

10U_0603_10V6M

CA57

CA58

1

12

2

+VDDA_AVDD1 +5V_RUN_PVDD_L

10U_0603_10V6M

0.1U_0201_10V6K
CA8

1

12

CA9

2

HP_OUT_R

12

RA816.2_040 2_1%

HP_OUT_L

12

RA716.2_040 2_1%

HDA_SDIN0_R
HDA_SDOUT_R

DMIC0<30>

DMIC_CLK_CODECDMIC_CLK0

INT_SPK_L+
INT_SPK_L­INT_SPK_R­INT_SPK_R+

AUD_SENSE_A
AUD_SENSE_B

16

40

AVDD1

25

HP-OUT-R

26

HP-OUT-L

19

HP-OUT2-L

20

HP-OUT2-R

15

LINE1-VREFO-R-E/MONO

14

LINE1-VREFO-L-E

8

BCLK

9

SYNC

10

SDATA-IN

11

SDATA-OUT

2

SPDIFO/GPIO2

5

GPIO0/DMIC-DATA

6

GPIO1/DMIC-CLK

42

SPK-L+

43

SPK-L-

44

SPK-R-

45

SPK-R+

1

HP1/LINE1 JD

48

HP2/LINE2 JD

21

AVDD2

CPVDD

AVSS2

37

18

AVSS1

4

12

41

DVDD

DVDD-IO

49

1

2

PVDD1

PGND

ALC3253-CG_MQFN48_6X6

0.1U_0201_10V6K
CA10

12

1 2

RA54 0_0402_5%@

@

1 2

RA55 0_0402_5%

UA1

47

46

PVDD2

LINE2-L

5VSTB/AUX MODE

LINE2-R

LINE1-L
LINE1-R
PCBEEP
SLEEVE

RING2
MIC2-VREFO-L
MIC2-VREFO-R

CBN
CBP

DC DET/EAPD

LDO1-CAP
LDO2-CAP
LDO3-CAP

PD

CPVEE

MIC2-CAP

VREF

10U_0603_10V6M

+3.3V_RUN_AUDIO_IO

CA61

36
35

LINE1_L HP_OUT_L

34

LINE1_R HP_OUT_R

33

AUD_PC_BEEP

32
30

SLEEVE

29

RING2

27

+MIC2-VREFO-L

RA5 2.2K_ 0402_5%

28

+MIC2-VREFO-R

RA6 2.2K_ 0402_5%

23

Place CA29 close to Codec

22

CA29 1U_0603_10V6K

7

1 2

RA44 100K_ 0402_5%

39

1 2

CA51 10U_0603_10V6M

1 2

17

CA52 10U_0603 _10V6M

1 2

13

CA53 10U_0603_10V6M

1 2

RA18 10K_0402_5%

1 2

3

PD#

CA31 1U_0603_ 10V6K

24

1 2

CA49 1U_0603_10V6K

1 2

31

CA25 10U_0603_10V6M

1 2

38

CA35 2.2U_0402_6.3V6M

LA14 BLM15PX600SN1D_2P

LA12 BLM15PX600SN1D_2P

0.1U_0201_10V6K

10U_0603_10V6M

CA55

CA56

1

12

2

place close to pin41 place close to pin46

1

2

1 2

CA43 10U_0603_10V6M

1 2

CA44 10U_0603_10V6M

12
12

CA27 0.1U_0402_25V6
CA28 0.1U_0402_25V6

SLEEVE/RING2 please keep 40 mils trace width

12

RING2

12

SLEEVE

12

+5V_ALW
+RTC_CELL

need link SM01000NS00
Realtek suggest rated current : 2A

Change Footprint to TAI-T_HCB2012KF-121T50_2P

0.1U_0201_10V6K
CA45

+3.3V_RUN_AUDIO

1

+3.3V_RUN_AUDIO

12

12

1 2

HCB2012VF-601T20_2P

0.1U_0201_10V6K

10U_0603_10V6M

1

2

10U_0603_10V6M

CA47

1

1

CA46

CA48

2

SPKR_R
BEEP_R

600 Ohm/2A

2

AUD_HP_OUT_L/ AUD_HP_OUT_Rplease keep 15 mils trace width

1 2
1 2

RA12 1K_0402_5%
RA13 1K_0402_5%

SPKR_R

100P_0402_50V8J

10K_0402_5%

@

12

12

RA51

+1.8V_RUN_AUDIO

RF@

33P_0402_50V8J

CA69

1

2

BEEP_R

100P_0402_50V8J

12

12

CA62@

RF Request

+5V_RUN_AUDIO

12P_0402_50V8J

1

2

RF Request

+1.8V_RUN

1

2

RF Request

+3.3V_RUN_AUDIO

1

2

10K_0402_5%

@

RA45

68P_0402_50V8J

RF@

RF@

1

CA63

CA64

2

12P_0402_50V8J

RF@

68P_0402_50V8J

RF@

1

CA65

CA66

2

12P_0402_50V8J

RF@

68P_0402_50V8J

RF@

1

CA67

CA68

2

CA72@

LA13

0.1U_0201_10V6K
CA60

1

2

SPKR <12>

BEEP <36>

10U_0603_10V6M

1

2

+5V_RUN_AUDIO

CA59

CLASS-D POWE R DOWN CONTR OL CIRCUIT

1 2

@

place at AGND and DGND plane

1 2

@

RA35 0_0402_5%

1 2

@

RA36 0_0402_5%

1 2

@

RA37 0_0402_5%

A A

Power sequence +5V_RUN_AUDIO(501us) > +3.3V_RUN_AUDIO(1204 us) > +1.5V_RUN

Reserve for support D3 cold

+5V_RUN

AUD_PWR_EN<12>

+5V_ALW

+3.3V_RUN

UZ5

@

1

VIN1

2

VIN1

3

ON1

4

VBIAS

5

ON2

6

VIN2
VIN27VOUT2

EM5209VF_SON14_2X3

VOUT1
VOUT1

VOUT2

GPAD

CT1

GND

CT2

+5V_RUN_AUDIO_UZ5

14
13

12
11
10
9

+3.3V_RUN_AUDIO_UZ5

8
15

+5V_RUN_AUDIO

12

CZ125 0.1 U_0201_10V6K@

CZ126

@

CZ127

@

CZ128 0.1 U_0201_10V6K@

PJP19

1 2

PAD-OPEN1x1m

+5V_RUN

PJP15@

+3.3V_RUN +3.3V_RUN_AUDIO

PAD-OPEN1x1m

1 2

1 2

220P_0402_50V7K

1 2

1000P_0402_50V7K

PJP16@

1 2

PAD-OPEN1x1m

+3.3V_RUN_AUDIO

1 2

2

NB_MUTE#<36>

HDA_RST#_R<12>

HDA_Link is 3.3V,no need level shift circuit

PJP17

1 2

+5V_RUN_AUDIO

PAD-OPEN1x2m

PJP18

1 2

PAD-OPEN1x1m

500mA

2.5A

RA48 0_0402_5%

21

DA8

@

RB751S-40 SOD-523

1 2

RA50 0_0402_5%

@

PD#

RE313 @one control line if DVDD is 3.3V
DE2@two control lines1

RING2
AUD_HP_OUT_L

AUD_HP_OUT_R
SLEEVE

1 2

LA10 BL M15PX330SN1D_2PESD@

@EMI@

1 2

RA52 0_0402_5%

@EMI@

1 2

RA53 0_0402_5%

1 2

LA11 BL M15PX330SN1D_2PESD@

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS D OCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL . IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DE LL'S EXPRESS WRITTEN CONSENT.

RING2_R
AUD_HP_OUT_L1

AUD_HP_OUT_R1
SLEEVE_R

@ESD@

680P_0402_50V7K

1

2

CA1

2

1

@EMI@

@EMI@

330P_0402_50V7K

330P_0402_50V7K

1

1

CA3

CA2

2

2

680P_0402_50V7K

@ESD@

CA4

1

Add t his Filter to avoid other
components/chips be influenced

AZ5125-02S.R7G_SOT23-3

2

3

ESD@

DA1

1

HP-Out-Right

HP-Out-L ef t

680P_0402_50V7K

@ESD@

1

CA13

2

AUD_HP_NB_SENSE

AZ5125-02S.R7G_SOT23-3

2

3

2

3

ESD@

DA2

1

1

Universal Jack

ESD@

DA3

680P_0402_50V7K

@ESD@

AZ5123-02S.R7G_SOT23-3

1

CA12

2

Nokia-MIC

iPhone-MIC

Global Headset

JHP1

7

GND

4

#4 G/M

1

#1 L/R

5

#5

6

#6 AGND

2

#2 R/L

3

#3 M/G

SINGA_2SJ3095-085111F

CONN@

Link SINGA_2SJ3095-085111F DONE
20160308

Norma l
Open

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size

Size

Size

Date : Sheet o f

Date : Sheet o f

Date : Sheet o f

Codec ALC3253

Codec ALC3253

Codec ALC3253

Document Number Re v

Document Number Re v

Document Number Re v

LA-F292P

LA-F292P

LA-F292P

35 60Tuesday, November 14, 2017

35 60Tuesday, November 14, 2017

35 60Tuesday, November 14, 2017

1.0

1.0

1.0

5

smd.db-x7.ru

+RTC_CELL

+3.3V_ALW_UE1

+3.3V_ALW

+3.3V_ALW_UE1

D D

C C

+1.8V_PRIM

B B

8/28 schematic review

A A

0.1U_0201_10V6K

0.1U_0201_10V6K

1

2

close to pin G8/M9

RF Request

+3.3V_ALW

1

2

+3.3V_ALW

RPE10

8
7

100K_0804_8P4R_5%

JTAG1 CONN@

@SHORT PADS~D

CE19

1

2

12P_0402_50V8J

RF@

CE59

1

2

1
2
3456

1

1

2

2

+3.3V_ALW_UE1

CE20

+3.3V_ALW_UE1

68P_0402_50V8J

RF@

1

CE60

2

+3.3V_ALW

PJP20

1 2

PAD-OPEN1x1m

CE22

0.1U_0201_10V6K

@

PJP21

1 2

PAD-OPEN1x1m

CV2_ON_R
IMVP_VR_ON_EC
PCH_ALW_ON
RUN_ON_EC

+3.3V_ALW2

+3.3V_ALW

100K_0402_5%

RE63

1 2

JTAG_RST#

1U_0402_6.3V6K

100_0402_1%

12

12

RE65@

CE30

This change for AR only because E C code need to align on AR & NAR

MEC_XTAL2_R

32 KHz Clock

YE1

MEC_XTAL1 MEC_XTAL2

1 2

10P_0402_50V8J

32.768KHZ_9PF_X1A000141000200

12

CE28

0601 c hange PN to SJ10000Q400

12

Close to pin H1

RE526 10K_0402_5%@
RE532 4.7K_0402_5%

+1.8V_3.3V_ALW_VTR3

CE21

1

0.1U_0201_10V6K

2

Close to pin N5

RE57 1K_0402_5%@

12

@

RE290
0_0402_5%

10P_0402_50V8J

12

CE29

5

10U_0603_6.3V6M

1

2

PJP22

1 2

PAD-OPEN1x1m

CE16

12

0.1U_0201_10V6K
CE15

VCCST_PWRGD<11,14,37>

SLP_WLAN#_GATE<44>

12
12

Modify 0523

TBT_RESET_N_EC<23,25,26>

12

For EMI request

ESPI_CLK_5105

33_0402_5%

12

12

@

RE314100_0402_1%

+VSS_PLL

+3.3V_ALW

SYS_PWROK< 11,14>

@EMI@

RE350

33P_0402_50V8J

CE57

@EMI@

12

RE32 0_0402_5%

0.1U_0201_10V6K

1U_0402_6.3V6K

CE13

1

12

2

0.1U_0201_10V6K

22U_0603_6.3V6M

@

1

1

CE17

2

2

PCH_DPWROK<11>

@DS3@

SIO_SLP_SUS#<11>

@

1 2
1 2

RE308 0_0402_5%

@

RE552 0_0402_5%

USH_DET#
BCM5882_ALERT#

1 2

@

RE506 0_0402_5%

RE362 100K_0402_5%

RTD3 SELECT<23>

DCIN1_EN_R<57>

TP_DISABLE#_EC

RTD3@

3.3V_ALW2

12

100K_0402_5%

VBUS1_ECOK_R<57>

RE58

+1.8V_3.3V_ALW_V TR3

@

RE548 0_0402_5%

@

RE600 0_0402_5%

1 2

0.1U_0201_10V6K
CE23

CE14

1

2

CE18

1 2

RE536

1 2

RE349 43K_0402_1%DS3@

WLAN_WIGIG60GHZ_DIS#<33>

CLK_TP_SIO_I2C_DAT<42>
DAT_TP_SIO_I2C_CLK<42>

change to PS2

12

1 2

RE509 0_0402_5%

@

RE602 0_0402_5%

1 2
1 2

RE529
10K_0402_5%

TBTB_HPD<23,26>

TBTA_HPD<23,25>

+1.8V_3.3V_ALW_VTR3

4

+3.3V_ALW_UE1

+1.8V_3.3V_ALW_VTR3

PCH_DPWROK_EC

0_0402_5%

RUN_ON_EC<37>

SIO_EXT_WAKE#<9>

BT_RADIO_DIS#<33>

PBAT_PRES#<47,56>

PCH_ALW_ON<44>
AC_PRESENT<11>

SML1_SMBDATA<8>

SML1_SMBCLK< 8>

WWAN_W AKE#<33>

SUSACK#<11>

SIO_PWRBTN#<11,14>

LID_CL_SIO#<37>

JTAG_TDI<37>

JTAG_TDO<37>

JTAG_CLK<37>

JTAG_TMS<37>

TACH_FAN1<37>

VOL_UP#<43>

LCD_TST<30>

PWM_FAN1<37>
DISPLAY_HPD_EC#<22>
PCH_RSMRST#<42>

NB_MODE#<9>

BIA_PWM_EC<30>

@

T266

PAD~D

PANEL_BKEN_EC<30>

BEEP< 35>

SIO_SLP_WLAN#<11,44>

AC_DIS<56>

BCM5882_ALERT#<38>

MSCLK<37>

MSDATA<37>

NB_MUTE#<35>

EN_INVPWR<30>

IMVP_VR_ON_EC<37>

SIO_SLP_S3#<11,23,37>
SIO_SLP_S5#<11>

AC_DISC#<57>

USH_DET#<38>

LID_CL_SIO_TAB#<45>

WWAN_RADIO_DIS#<33>

BC_DAT_ECE1117<42>
BC_CLK_ECE1117<42>

NGFF_CONFIG_3<33>

1 2

ESPI_RESET#<8,37>

ESPI_ALERT#<8>

PCH_PLTRST#_5105<37>

ESPI_CLK_5105<8,37>

ESPI_CS#<8,37>

ESPI_IO0<8,37>
ESPI_IO1<8,37>
ESPI_IO2<8,37>
ESPI_IO3<8,37>

UE10

1

NC

VCC

2

A

Y

3

GND

74AUP1G07SE-7 SOT353

1 2

RE554 1M_0402_5%

1 2

RE553 1M_0402_5%

4

+RTC_CELL_VBAT

0.1U_0201_10V6K
CE11

1

2

+3.3V_EC_PLL

RUN_ON_EC
BT_RADIO_DIS#
SIO_SLP_SUS#_R

PCH_ALW_ON

WWAN_W AKE#

WLAN_W IGIG60GHZ_DIS#

VCCST_PWRGD_EC

JTAG_TDI
JTAG_TDO
JTAG_CLK
JTAG_TMS
JTAG_RST#

LCD_TST

PCH_RSMRST#

TBT_RESET_N_EC_R
HW_ACAVIN_NB

AC_DIS

MSCLK
MSDATA

EN_INVPWR
RESET_IN#
IMVP_VR_ON_EC

P_SENSOR_ACT#_EC

LID_CL_SIO_TAB#

RTCRST_ON

UPD1_HPD
VBUS2_ECOK

ESPI_CLK_5105

TP_DISABLE#_EC
UPD2_HPD
RESET_OUT

DCIN2_EN

MEC_XTAL1
MEC_XTAL2_R

+1.8V_3.3V_ALW_VTR3

5

4

1 2

DZ106

RB751S-40 SOD-523

1 2

DZ107

RB751S-40 SOD-523

UPD2_HPD
UPD1_HPD

UE1

A2

VBAT

B7

VTR_ANALOG

K2

VREF_ADC

F1

VTR_PLL

H1

VTR_REG

G8

VTR1

M9

VTR2

N5

VTR3

F8

GPIO020

E8

GPIO045

M12

GPIO120

C2

GPIO166

F9

GPIO175

N4

GPIO230

M8

GPIO231

K8

GPIO233

E11

GPIO007/SMB03_DATA/PS2_CLK0B

D8

GPIO010/SMB03_CLK/PS2_DAT0B

M13

GPIO110/PS2_CLK2

K12

GPIO111/PS2_DAT2

L13

GPIO112/PS2_CLK1A

K11

GPIO113/PS2_DAT1A

K10

GPIO114/PS2_CLK0A/nEC_SCI

N11

GPIO115/PS2_DAT0A

E10

GPIO154/SMB02_DATA/PS2_CLK1B

C12

GPIO155/SMB02_CLK/PS2_DAT1B

E9

GPIO145/SMB09_DATA/JTAG_TDI

F6

GPIO146/SMB09_CLK/JTAG_TDO

C8

GPIO147/SMB08_DATA/JTAG_CLK

C5

GPIO150/SMB08_CLK/JTAG_TMS

G13

JTAG_RST#

E3

GPIO050/FAN_TACH0/GTACH0

D1

GPIO051/FAN_TACH1/GTACH1

M2

GPIO052/FAN_TACH2/LRESET#

L10

GPIO053/PWM0/GPWM0

L11

GPIO054/PWM1/GPWM1

M5

GPIO055/PWM2/SHD_CS#/(RSMRST#)

J8

GPIO056/PWM3/SHD_CLK

N1

GPIO001/PWM4

L8

GPIO002/PWM5

N6

GPIO014/PWM6/GPTP-IN6

J9

GPIO015/PWM7

H11

GPIO035/PWM8/CTOUT1

D9

GPIO133/PWM9

H12

GPIO134/PWM10/UART1_RTS#

G10

GPIO135/UART1_CTS#

H10

GPIO170/TFDP_CLK/UART1_TX

G9

GPIO171/TFDP_DATA/UART1_RX

A4

GPIO022/GPTP-IN0

B2

GPIO023/GPTP-IN1

C1

GPIO024/GPTP-IN2

N7

GPIO031/GPTP-OUT1

K9

GPIO032/GPTP-OUT0

N8

GPI0040/GPTP-OUT2

F13

GPIO121/PVT_IO0

E13

GPIO124/nRESETI

C13

GPIO125/GPTP-OUT5/PVT_CLK

E12

GPIO126/PVT_IO3

F11

GPIO122/BCM0_DAT/PVT_IO1

F12

GPIO123/BCM0_CLK/PVT_IO2

D12

GPIO046/BCM1_DAT

D13

GPIO047/BCM1_CLK

F4

GPIO041/SYS_SHDN#

B1

SYSPWR_PRES

K7

GPIO011/nSMI

N3

GPIO021/LPCPD#

K6

GPIO061/LPCPD#/ESPI_RESET#

H7

GPIO063/SER_IRQ/ESPI_ALERT#

K1

GPIO064/LRESET#

G7

GPIO065/PCI_CLK/ESPI_CLK

H6

GPIO066/LFRAME#/ESPI_CS#

K5

GPIO070/LAD0/ESPI_IO0

L4

GPIO071/LAD1/ESPI_IO1

G6

GPIO072/LAD2/ESPI_IO2

L5

GPIO073/LAD3/ESPI_IO3

L2

GPIO067/CLKRUN#

M1

GPIO100/nEC_SCI

G4

GPIO106/PWROK

L12

GPIO107/nSMI

A1

XTAL1

A3

XTAL2

+3.3V_RUN

RE555
10K_0402_5%

1 2

UPD2_HPD

UPD1_HPD

MP uses SA00009GL30
20161213

VSS1

VSS2

A6

E6

A13

TP_DISABLE# <42>

RUN_ON<17,37,44,51>

3

GPIO033/RC_ID0

GPIO034/RC_ID1/SPI0_CLK

GPIO036/RC_ID2/SPI0_MISO
GPIO003/SMB00_DATA/SPI0_CS#
GPIO004/SMB00_CLK/SPI0_MOSI

GPIO057/VCC_PWRGD

GPIO060/KBRST/48MHZ_OUT

GPIO104/UART0_TX

GPIO105/UART0_RX

GPIO127/A20M/UART0_CTS#

GPIO225/UART0_RTS#

GPIO025/TIN0/nEM_INT/UART_CLK

GPIO017/GPTP-IN5

GPIO152/GPTP-OUT3

GPIO156/LED0
GPIO157/LED1
GPIO153/LED2

GPIO005/SMB01_DATA/GPTP-OUT4

GPIO141/SMB05_DATA/SPI1_CLK/UART0_DCD#

GPIO142/SMB05_CLK/SPI1_MOSI/UART0_DSR#

GPIO143/SMB04_DATA/SPI1_MISO/UART0_DTR#

GPIO144/SMB04_CLK/SPI1_CS#/UART0_RI#

VSS_ADCH4VR_CAPJ1VSS_PLL

VSS3

C4

+VR_CAP

12

CE31 1U_0402_6.3V6K

+3.3V_ALW

RUN_ON#<44>

2

3

GPIO226/LED3

GPIO006/SMB01_CLK/GPTP-OUT7

GPIO012/SMB07_DATA/TOUT3

GPIO013/SMB07_CLK/TOUT2

GPIO130/SMB10_DATA/TOUT1

GPIO131/SMB10_CLK/TOUT0

GPIO132/SMB06_DATA

GPIO140/SMB06_CLK/ICT5

GPIO200/ADC00
GPIO201/ADC01
GPIO202/ADC02
GPIO203/ADC03
GPIO204/ADC04
GPIO205/ADC05
GPIO206/ADC06
GPIO207/ADC07
GPIO210/ADC08
GPIO211/ADC09
GPIO212/ADC10
GPIO213/ADC11
GPIO214/ADC12
GPIO215/ADC13
GPIO216/ADC14
GPIO217/ADC15

GPIO222/SER_IRQ

GPIO223/SHD_IO0

GPIO224/GPTP-IN4/SHD_IO1

GPIO227/SHD_IO2

GPIO016/GPTP-IN7/SHD_IO3/ICT3

GPIO164/VCI_OVRD_IN

GPIO163/VCI_IN0#
GPIO162/VCI_IN1#
GPIO161/VCI_IN2#
GPIO000/VCI_IN3#

GPIO165/32KHZ_IN/CTOUT0

GPIO221/GPTP-IN3/32KHZ_OUT

GPIO044/VREF_VTT

GPIO042/PECI_DAT/SB-TSI_DAT

GPIO043/SB-TSI_CLK

GPIO103/THERMTRIP2#

THERMTRIP1#

GPIO160/PWM11/PROCHOT#

VSS_ANALOG

MEC5105_WFBGA169_11X11

G1

+VSS_PLL

100K_0402_5%

RUNPWROK

RE68

1 2

RUN_ON#

5

DMN65D8LDW-7_SOT363-6

61

QE2A

GPIO026/TIN1
GPIO027/TIN2
GPIO030/TIN3

GPIO151/ICT4

BGPO0

VCI_OUT

DN1_DP1A
DP1_DN1A
DN2_DP2A
DP2_DN2A
DN3_DP3A
DP3_DN3A
DN4_DP4A
DP4_DN4A

VSET

+3.3V_RUN

RE67

1 2

34

2

TYPEC_ID

F2

SYSTEM_ID

J10

BOARD_ID

J13

UPD2_SMBDAT

E7

UPD2_SMBCLK

D7
G3

GPS_DISABLE#

H5
G11
G12
B13

UPD1_SMBINT#

F10

PCIE_WAKE#_R

N13
N12
M11
H9

VGA_IDENTIFY

L9
M10
N9

C11
D10
D11
E1

E5
B3
M7

SAR_DPR#

M4

PBAT_CHARGER_SMBDAT

M3

PBAT_CHARGER_SMBCLK

N2
N10

LED_MASK#

A12

ISH_I2C1_SDA_EC

B6

ISH_I2C1_SCL_EC

F7

UPD1_SMBDAT

B4

UPD1_SMBCLK

C3

I_BATT_R

J4

I_SYS_R

J5
J6
G2

USH_PWR_STATE#

H2

USB_POWERSHARE_VB US_EN

J2

USB_POWERSHARE_EN#

J3

USB_PWR_EN1#

K3
D3

LOM_CABLE_DETECT#

D2
E2

USB_PWR_EN2#

G5

UPD2_SMBINT#

F5

DCIN1_EN

K4

PCH_PCIE_WAKE#

L1
L3

CV2_ON_R

H8

3.3V_TS_EN

J7

MASK_SATA_LED#

L6

1.8V_PRIM_PWRGD

L7

VBUS1_ECOK

M6
D6

C7
A5
D5

VCI_IN1#

B5

VCI_IN2#

D4

POA_WAKE#

E4

C6

32KHZ_OUT

F3

+PECI_VREF

J11

PECI_EC_R

K13
J12

REM_DIODE1_N

A8

REM_DIODE1_P

A7

REM_DIODE2_N

A10

REM_DIODE2_P

A9
B9
B8

REM_DIODE4_N

A11

REM_DIODE4_P

B10

+VR_CAP

C10

VSET_5105

VIN

C9
B11

VCP

H3

THERMTRIP2#

B12

THERMTRIP1#
PROCHOT#_R1

H13

1U_0402_6.3V6K

12

CE63

10K_0402_5%

DMN65D8LDW-7_SOT363-6

QE2B

QE17

L2N7002WT1G_SC-70-3

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS D OCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL . IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DE LL'S EXPRESS WRITTEN CONSENT.

TYPEC_ID <37>
SYSTEM_ID <37>
BOARD_ID <37>
UPD2_SMBDAT <25>
UPD2_SMBCLK <25>

RUNPWROK <14>
GPS_DISABLE# <33>
HOST_DEBUG_TX <33,37>
ME_FWP <12>
ME_SUS_PWR_ACK <11>
UPD1_SMBINT# <26>

PCIE_WAKE#_R <37>
SIO_SLP_S4# <11,17,49,52>
SIO_SLP_A# <11>
SIO_SLP_LAN# <11>

NGFF_CONFIG_1 <32,33>
NGFF_CONFIG_0 <33>

BREATH_LED# <43>
BAT1_LED# <43>
BAT2_LED# <43>
LCD_VCC_TEST_EN <30>

USH_EXPANDER_SMBDAT <37,38,45>
USH_EXPANDER_SMBCLK <37,38,45>
VCCDSW_EN <11>
SAR_DPR# <33>
PBAT_CHARGER_SMBDAT <47,56>
PBAT_CHARGER_SMBCLK <47,56>
NGFF_CONFIG_2 <33>

1 2

RE516 0_0402_5%@

1 2

RE517 0_0402_5%@

UPD1_SMBDAT <26>
UPD1_SMBCLK <26>

1 2

RE64 300_0402_5%

1 2

RE312 300_0402_5%

@

1 2

RE318 0_0402_5%

USH_PWR_STATE# < 38>

USB_POWERSHARE_VBUS_EN <40>
USB_POWERSHARE_EN# <40>
USB_PWR_EN1# <41>
AUX_EN_WOWL <44>

BC_INT#_ECE1117 <42>

@

@

RE603 0_0402_5%

CE54 10P_0402_50V8J@

12

RE601 0_0402_5%

PCH_PCIE_WAKE# <11,23,37>

LAN_WAKE# <11>

1 2

RE539 100_0402_5%

3.3V_TS_EN <30>
MASK_SATA_LED# <43>

1.8V_PRIM_PWRGD <52>

12

EC_FPM_EN <38>

ACAV_IN <56>
ALWON <48>
POWER_SW_IN# <37>

POA_WAKE# <38>

3.3V_WWA N_EN <44>

1 2

1 2

RE60 43_0402_5%

1 2

CE24 2200P_0402_50V7K

1 2

CE26 2200P_0402_50V7K

1 2

CE27 2200P_0402_50V7K

VSET_5105 <37>

I_ADP <56>

THERMTRIP2# <37>

1 2

RE288 100_0402_5%

10K_0402_5%

12

RE546

2 1

RB751S-40 SOD-523

13

D

S

RTCRST_ON_R

2

G

RE543

1 2

1M_0402_5%

22P_0402_50V8J

12

CE65

LP2301ALT1G_SOT23-3

DE2

I_BATT <56>
I_SYS <53,56>

VOL_DOWN# <43>

TOUCHPAD_INTR# <12,42>

UPD2_SMBINT# <25>
DCIN2_EN_R <57>

CV2_ON <38>

VBUS2_ECOK_R <57>

PECI_EC <12>

M3042_PCIE#_SATA <10>

PROCHOT# <12,53,56>

QE15

123

D

S

G

100K_0402_5%

1 2

2

VCCDSW_EN

ISH_I2C1_SDA <9,45>

ISH_I2C1_SCL <9,45>

3.3V_TS_EN

RE557 100K_0402_5%@

RE59 close to UE2 at least 250mils

+PECI_VREF

@

RE59 0_0402_5%

0.1U_0201_10V6K
CE25

12

REM_DIODE1_N
REM_DIODE1_P
REM_DIODE2_N
REM_DIODE2_P

REM_DIODE4_N
REM_DIODE4_P

+RTC_CELL+RTC_CELL_PCH

+RTC_CELL_PCH +RTC_CELL

@

1 2

@

RE565 0_0402_5%

0.1U_0402_25V6

@

CE64

RE541

12

For KW

0.1U_0402_25V6

@

CE66

12

+3.3V_RUN

1 2

12

+1.0V_VCCST

REM_DIODE1_N <37>
REM_DIODE1_P <37>
REM_DIODE2_N <37>
REM_DIODE2_P <37>

REM_DIODE4_N <37>
REM_DIODE4_P <37>

1 2

RE551 0_0402_5%

RTCRST_ON

UPD2_SMBDAT
UPD2_SMBCLK
UPD2_SMBINT#
UPD1_SMBINT#
VOL_UP#
VOL_DOWN#
PBAT_CHARGER_SMBDAT
PBAT_CHARGER_SMBCLK
NGFF_CONFIG_1
SIO_SLP_SUS#_R

ISH_I2C1_SCL_EC
ISH_I2C1_SDA_EC
UPD1_SMBCLK
UPD1_SMBDAT

NGFF_CONFIG_2
NGFF_CONFIG_0
NGFF_CONFIG_3

USB_PWR_EN2#
USB_POWERSHARE_EN#
USB_PWR_EN1#
USB_POWERSHARE_VB US_EN

AC_DIS
GPS_DISABLE#
WLAN_W IGIG60GHZ_DIS#
WWAN_W AKE#
LED_MASK#

THERMTRIP1#

PCIE_WAKE#_R
LID_CL_SIO_TAB#
BC_DAT_ECE1117
WWAN_RADIO_DIS#
BT_RADIO_DIS#
LOM_CABLE_DETECT#

VCI_IN1#
VCI_IN2#

100K_0201_5%

I_BATT_R
I_SYS_R

PCH_RSMRST#
SYS_PWROK
I_SYS_R
LCD_TST
EN_INVPWR
TBT_RESET_N_EC_R

POA_WAKE#

VGA_IDENTIFY
VGA_IDENTIFY

RTCRST_ON

RE93

@

NDS3@

Discrete
UMA

2

G

12

1

1 2

RE302 2.2K_0402_5%

1 2

RE303 2.2K_0402_5%

1 2

RE91 100K_0402_5%

1 2

RE92 100K_0402_5%

1 2

RE519 10K_0402_5%@

1 2

RE520 10K_0402_5%@

1 2

RE37 2.2K_0402_5%

1 2

RE43 2.2K_0402_5%

1 2

RE562 2.2K_0402_5%

1 2

RE561 100K_0 402_5%

1
2
3
4 5

2.2K_0804_8P4R_5%

1
2
3
4 5

100K_0804_8P4R_5%

RPE11

1
2
3
4 5

100K_0804_8P4R_5%

1 2

RE83 100K_0402_5%@

1 2

RE12 100K_0402_5%

1 2

RE8 100K_0402_5%

1 2

RE38 10K_0402_5%

1 2

RE21 10K_0402_5%

1 2

RE301 10K_0402_5%

1 2

RE35 10K_0402_5%

1 2

RE5 10K_0402_5%

1 2

RE365 100K_0402_5%

1 2

RE10 100K_0402_5%

1 2

RE11 100K_0402_5%

1 2

RE505 100K_0402_5%

1 2

RE507 100K_0402_5%

1 2

RE508 100K_0402_5%

1 2

CE3 2200P_04 02_50V7K

1 2

CE4 2200P_04 02_50V7K

1 2

RE342 10K_0402_5%

1 2

RE56 10K_0402_5%

1 2

@

RE313

1 2

RE20 100K_0402_5%

1 2

RE55 100K_0402_5%

1 2

RE95 100K_0402_5%

1 2

RE324 100K_0402_5%

1 2

RE84 100K_0402_5%

1 2

RE85 100K_0402_5%@

RE94

@

1 2

75_0402_5%

13

D

QE12

@

L2N7002WT1G_SC-70-3

S

RPE12

RPE9

8
7
6

8
7
6

8
7
6

10K_0402_5%

VGA_ID0

+3.3V_ALW

+RTC_CELL

+RTC_CELL

+3.3V_ALW

0
1

PCH_RTCRST# <11>

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

Date : Sheet o f

Date : Sheet o f

Date : Sheet o f

EC MEC5105

EC MEC5105

EC MEC5105

LA-F292P

LA-F292P

LA-F292P

1

36 60Tuesday, November 14, 2017

36 60Tuesday, November 14, 2017

36 60Tuesday, November 14, 2017

1.0

1.0

1.0

5

smd.db-x7.ru

+1.8V_3.3V_ALW_ VTR3

+3.3V_ALW

UE6

1

5

NC

VCC

CONN@

JESPI

11

GND

12

GND

JXT_FP241AH-010GAAM

2

A

3

GND

74AUP1G07SE-7 SOT35 3

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

Y

+3.3V_RUN

RE375 0_0402_5 %LPC@
RE560 0_0402_5 %@

4

1 2
1 2

PCH_PLTRST#_EC<11>

D D

RE340
10K_0402_ 5%

1 2

PCH_PLTRST#_EC
ESPI_RESET#

PCH_PLTRST#_5105 <36 >

ESPI_IO0 <8,36>
ESPI_IO1 <8,36>
ESPI_IO2 <8,36>
ESPI_IO3 <8, 36>

ESPI_CS# <8,36>

ESPI_RESET# <8,36>

ESPI_CLK_5105 <8,36>

4

3

+RTC_CELL

100K_0402_5%

12

RE31

POWER_SW_IN#<36>

LID_CL_SIO#

RE33 10K_0402_ 5%

1U_0402_6.3V6K

12

+3.3V_ALW

100K_0402_5%

RE25

12

.047U_0402_16V7K

12

CE8

1 2

CE12

RE26

10_0402_5 %

CE10@

1 2

1U_0402_6.3 V6K

POWER_SW#_MB <11,43>

12

LID_CL# <45>LID_CL_SIO#<36>

RF Request

+3.3V_ALW

1

2

2

PCIE_WAKE#_R<36>

Stuff RE275 and no stuff RE274 keep E5 design
Stuff RE274 and no stuff RE275 to save two GPIOs on EC(PCH_PCIE_WAKE# should be output with OD)

IMVP_VR_ON_EC

IMVP_VR_ON_EC<36>
SIO_SLP_S3#<11,23,36,37>

CE61

RF@

RUN_ON_EC<36>

68P_0402_50V8J

SIO_SLP_S3#

RUN_ON_EC

TC7SH08FU_SSOP5~D

TC7SH08FU_SSOP5~D

12

@

RE275 0_04 02_5%

+3.3V_ALW

5

1

P

B

O

2

A

G

UE3

3

1 2

+3.3V_ALW

5

1

P

B

2

A

G

UE5

3

12

@

RE3040_0402_ 5%

@

CE53

1 2

0.1U_0402_2 5V6K

4

@

RE2800_0402_5%

12

@

RE2920_0402_ 5%

@

CE52

1 2

0.1U_0402_2 5V6K

4

O

1 2

IMVP_VR_ON

1

PCIE_WAKE# <23,33,39>

PCH_PCIE_WAKE# <11,23 ,36>

RE2740_0402_5% @

1

NC

2

A

3

GND

74AUP1G07SE-7 SOT35 3

IMVP_VR_ON <53>

RUN_ON <17,36,44,51>

+3.3V_ALW

UE4

5

VCC

4

VCCST_PWRGD <11,14,36>

Y

C C

TYPEC_ID<36>

CE40RE343

4700p240K
4700p130K
4700p

62K
33K

4700p

*

8.2K

4700p
4700p

4.3K
2K

4700p
4700p

1K

QE11

1 3

1 2

D

CHECK

SIO_SLP_S3# <11 ,23,36,37>

2

G

S

+3.3V_ALW

10K_0402_5%

10K_0402_5%

10K_0402_5%

12

12

12

RE72

RE73

RE74

1 2

RE306

@

0_0402_5%

+3.3V_ALW

1 2

RE70 2.2K_0402_5%

100K_0402_5%

12

RE75@

RE86
10K_0402_ 5%

1 2

RE69

1 2

8.2K_0402_ 5%

H_THERMTRIP#<12>

2

B

E

3 1

10K_8P4R_5%

12

678

RPE7

+EC_DEBUG_VCC

1
2
3
4
5
6
7
8
9
10

RE71

123

4 5

10_0402_1%

JTAG_TDI

JTAG_TDI <36>

JTAG_TMS

JTAG_TMS <36>

JTAG_CLK

JTAG_CLK <36>

JTAG_TDO

JTAG_TDO <36>

MSCLK
MSDATA

HOST_DEBUG_TX

DEBUG_TX

SBIOS_TX<9>

HOST_DEBUG_TX <33,36>
MSDATA <36>
MSCLK <36>

1 2

@

RE30

0_0402_5%

+1.0VS_VCCIO

@

+1.0V_VCCST

L2N7002WT1G_ SC-70-3

@

RE90 0 _0402_5%

B B

Control Byte

0 001 R/ WA0A1A2

R/W = 0 = Write

+3.3V_ALW

12

12

10K_0402_5%

@

RE504

1U_0402_6.3V6K

@

CE500

R/W = 1 = Read

WRST#

SMBus address 0x40

+3.3V_ALW

10K_0402_5%

10K_0402_5%

10K_0402_5%

12

12

12

@

@

@

RE502

RE527

RE500

10K_0402_5%

10K_0402_5%

10K_0402_5%

12

12

12

@

@

@

RE503

RE501

RE528

0.1U_0402_25V6K

1

@

CE501

2

USH_EXPANDER_SMBCLK<37,39,46>
USH_EXPANDER_SMBDAT<37,39,46>

@

T267

PAD~D

A A

+3.3V_ALW

1U_0402_6.3V6K

12

@

CE502

UE2

@

18

VSTBY33

19

SCL

20

SDL

1

A2

2

A1

3

A0

4

WRST#

EXPANDER_ALERT#

WRST#

7

INT

5

NC

6

NC

8

NC

MCP23008T_QFN20 P

Link MCP23008 OK

16

GP7

15

GP6

14

GP5

13

GP4

12

MW_2

GP3

11

@

1 2

RE518 0_0402_5 %

MW_1

GP2
GP1
GP0

VSS

EPAD

@

10
9

17
21

1 2

RE550 0_0402_5 %

CONN@

11

GND

12

GND

JXT_FP241AH-010GAAM

JDEG1

1
2
3
4
5
6
7
8
9

10

+3.3V_ALW

TYPEC_ID

TYPEC_ID

REV
Single Port ACE w/o AR
Single Port ACE w/AR
Dual Port ACE w/o AR
Dual Port ACE w/AR
Dual Port ACE (w/AR +w/o AR)

0.1U_0402_25V6

THERMTRIP2# <36>

CE36

LMBT3904WT1G SC70-3

12

C

QE4

RE343
33K_0402_ 5%

1 2

12

CE62
4700P_040 2_25V7K

CHECK

BOARD_ID<36> SYSTEM_ID<36>

RE79

240K 4700p
130K
62K

*

33K 4700p

8.2K

4.3K
2K

BOARD_ID rise t i me is measured fr o m 5 %~ 68%.

Rest=1.58K , Tp=96 degree
Rest=1.33K , Tp=93 degree

+3.3V_RUN

RE48 10K_0402_5 %
RE51 10K_0402_5 %

5085 Channel

DP1/DN1

DP2/DN2

DN2a/DP2a

DP3/DN3

DP4/DN4

100P_0402_50V8J

C

@

CE39

E

3 1

1 2

12

12

CE40

REV

X00

4700p

X01

4700p

X02
X03

Reserve

4700p
4700p

A00
4700p
4700p1K

VSET_5105

0.1U_0402_25V6

1.58K_0402_1%

12

12

CE38

RE77

PWM_FAN1

1 2

TACH_FAN1

1 2

Thermal diode mapping

Locat i on

CPU (QE3)

AR (QE5)

DDR (QE7)

NA

CPU VR (QE6 )

DP4/DN4 for Sk in on
QE6, place QE6 close to
Vcore VR choke.

REM_DIODE4_P <36>

2

B

QE6

LMBT3904WT1G SC70-3

REM_DIODE4_N <36>

4.3K_0402_ 5%
RE79

CE40
4700P_040 2_25V7K

PANEL_ID rise t i me is measured fro m 5%~68%.

VSET_5105 <36>

Link ACES_50278-0040N-001 DONE

20160331

JFAN1

GND
GND

ACES_50278-00 40N-001

CONN@

100P_0402_50V8J

CE35@

1 2

DP2/DN2 for WiGig on QE5, place QE5 c lose
to WiGig and CE37 close to QE5

DN2a/DP2a for DDR on QE7, place QE7 close
to DDR and CE46 close to QE7

100P_0402_50V8J

31

12

CE46@

C

+3.3V_ALW+3.3V_ALW

12

RE300
130K_0402 _5%

SYSTEM_IDBOARD_ID

12

CE47
4700P_040 2_25V7K

CE47RE300

PANEL SIZE

4700p
4700p33K
4700p8.2K

4700p 15P
4700p

PWM_FAN1
TACH_FAN1

10U_0603_6.3V6M

12

CE32

REM_DIODE1_P <36>

REM_DIODE1_N <36>

12

C

CE37@

E

3 1

LMBT3904WT1G SC70-3

11"
12"
13"
14"
15"
17"

+5V_RUN

DE1 @
BZV55-B5V6_SOD80 C2

2 1

2

B

QE5

240K 4700p
130K 4700p

*

62K

4.3K 4700p
2K
1K

1

1

2

2

3

3

4

4

5
6

Place under CPU
Place CE35 close to the QE3 as possible

C

2

B

E

QE3

3 1

LMBT3904WT1G SC70-3

100P_0402_50V8J

E

B

2

QE7

LMBT3904WT1G SC70-3

PWM_FAN1 <36>
TACH_FAN1 <36>

REM_DIODE2_P <36>

REM_DIODE2_N <36>

DELL CONFIDENTIAL/PROPRIETARY

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL ") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

3

PARTY WITHOUT DELL'S EXPRESS W RITTEN CONSENT.

2

Title

Size

Size

Size

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

MEC5105 support

MEC5105 support

MEC5105 support

Document Number Rev

Document Number Rev

Document Number Rev

LA-F292P

LA-F292P

LA-F292P

37 60Tuesday, November 14, 2017

37 60Tuesday, November 14, 2017

1

37 60Tuesday, November 14, 2017

1.0

1.0

1.0

5

smd.db-x7.ru

4

For NUVOTON TPM

3

2

RF Request RF Request

+3.3V_ALW +3.3V_M_TPM

1

68P_0402_50V8J

12P_0402_50V8J

RF@

RF@

1

POA_WAKE#<36>

RZ114 0_0402_5%@

RB751S-40 SOD-523

USH_DET#<36>

PCH_PLTRST#_AND

.047U_0402_16V7K

12

CZ61ESD@

For ESD solution

1

CZ58

CZ57

2

2

KW pop RZ8/RZ9 because

+3.3V_ALW

@

share I2C on USH/SAR/ALS

1 2

RZ8 2.2K_0402_5%

1 2

RZ9 2.2K_0402_5%

1 2

RZ10 100K_0402_5%

1 2

CZ78RF@ 100P_0402_50V8J

1 2

RZ85 0_0402_5%

1 2

RZ364 100_0402_5%

USH_EXPANDER_SMBCLK<36,37,45>
USH_EXPANDER_SMBDAT<36,37,45>

BCM5882_ALERT#<36>

1 2

DZ8

USH_PWR_STATE#<36>

12

1 2

RZ87 0_0402_5%@

DZ7

RB751S-40 SOD-523

USH_EXPANDER_SMBCLK
USH_EXPANDER_SMBDAT

USH_PWR_STATE#

CV2_ON<36>
EC_FPM_EN<36>

USB20_N10<10>
USB20_P10<10>

+3.3V_ALW
+5V_ALW

+3.3V_RUN

12

+5V_ALW

1

2

@

1 2

VDD
VHIO
VHIO

GND

GND

GND

GND

PGND

Reserved

VSB

@

1
8

14
22

2

NC

7

NC

10

NC

11

NC

25

NC

26

NC

31

NC

9
16
23
32
33
12

RZ367 0_0402_5%

1 2

RZ89 0_0402_5%

+3.3V_ALW

PJP391
PAD-OPEN1x1m

1 2

+3.3V_ALW_UZ12

0.1U_0201_10V6K

1

CZ51

2

+UZ12_TPM
+UZ12_VHIO +PWR_SRC_R

0.1U_0201_10V6K

1

CZ54

2

CZ53,CZ55 as close as UZ12.14
CZ54 as close as UZ12.22

+UZ12_TPM

4.7U_0402_6.3V6M

1

CZ75

2

10U_0603_10V6M

place CZ51,CZ52 as close as UZ12.1

1

CZ52

2

RZ366 0_0402_5%@

@

RZ365 0_0402_5%

0.1U_0201_10V6K

10U_0603_10V6M

1

1

CZ53

CZ55

2

2

place CZ50, CZ75 as close as UZ 12.8

0.1U_0201_10V6K

1

CZ50

2

1 2
1 2

PCH_SPI_CLK_2_R

33_0402_5%

@EMI@

RZ63

0.1U_0402_25V6

1 2

@EMI@

12

CZ56

+3.3V_M_TPM
+3.3V_RUN

PCH_PLTRST#_AND<11,23,30,33,39>

CONTACTLESS_DET#<12>

+PWR_SRC

D D

+3.3V_ALW

@

1 2

+3.3V_ALW_PCH

C C

B B

SIO_SLP_S0#<11,17,51>

PCH_SPI_D1_R1<8>

PCH_SPI_D0_R1<8>

PCH_SPI_CLK_R1<8>

PCH_SPI_CS#2<8>

NPCT65x
NPCT75x
NPCT75x

RZ369 0_0402_5%

@

1 2

RZ368 0_0402_5%

1 2
1 2

1 2
1 2

1 2
1 2

T283

TPM_PIRQ#

TPM_PIRQ#<9>

PLTRST_TPM#<11>

@

PAD~D

1 2

RZ69 10K_0402_5%

+3.3V_RUN

12

RZ362

@

10K_0402_5%

@

RZ112 0_0402_5%
RZ363 0_0402_5%@

RZ58 33_0402_5%
RZ59 33_0402_5%

RZ60 33_0402_5%EMI@

@

RZ61 0_0402_5%

Pop

RZ89, RZ366, RZ62, RZ363
RZ89, RZ365, RZ112

+3.3V_M_TPM

TPM_GPIO0
TPM_LPM#

PCH_SPI_D1_2_R
PCH_SPI_D0_2_R

TPM_PIRQ#

PCH_SPI_CLK_2_R
PCH_SPI_CS#2_R

TPM_GPIO4

10K_0402_5%

@

12

RZ62

Depop
RZ365, RZ367, RZ112
RZ367, RZ366, RZ62, RZ363
RZ89, RZ365, RZ62RZ367, RZ366

UZ12

29

GPIO0/SDA/XOR_OUT

30

GPIO1/SCL

3

GPIO2/GPX

6

GPIO3/BADD

24

LAD0/MISO

21

LAD1/MOSI

18

LAD2/SPI_IRQ#

15

LAD3

19

LCKL/SCLK

20

LFRAME#/SCS#

17

LRESET#/SPI_RST#/SRESET#

27

SERIRQ

13

CLKRUN#/GPIO4/SINT#

28

LPCPD#

4

PP

5

TEST

NPCT750JAAYX_QFN32_5X5

+3.3V_M_TPM

+3.3V_RUN

Comment

VDD - V_RUN Power
VHIO - V_SPI Power

Option1 (recommended)
VDD and VHIO - V_RUN power

Option2 (for Z1 sample [early sample])

VDD and VHIO - V_SPI power

12P_0201_50V8J

RF@

1

1

CZ59

2

2

+5V_RUN

CONTACTLESS_DET#_R

0.1U_0201_10V6K

@

CZ64

68P_0201_50V8J

RF@

CZ60

POA_WAKE#_R

USH_RST#_R

USH_DET#_R

Close to JUSH1

USH CONN

JUSH1

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25

25

26

26

27

GND1

28

GND2

CVILU_CF5026FD0RK-05-NH

CONN@

Link CVILU_CF5026FD0RK-05-NH DONE
2016020

+3.3V_ALW+3.3V_RUN+5V_RUN

0.1U_0201_10V6K

0.1U_0201_10V6K

1

1

@

CZ66

2

2

0.1U_0201_10V6K

1

@

@

CZ67

CZ68

2

68P_0402_50V8J

1

2

RF Request

RF@

CZ73

RF Request

A A

USH_EXPANDER_SMBCLK

USH_EXPANDER_SMBDAT

1 2

CZ62 68P_0402_50V8J@RF@

1 2

CZ63 68P_0402_50V8J@RF@

68P_0402_50V8J

RF@

1

CZ69

2

68P_0402_50V8J

RF@

1

CZ71

2

+3.3V_ALW+3.3V_RUN+5V_RUN+5V_ALW

68P_0402_50V8J

RF@

1

CZ72

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.

5

4

3

2

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

USH & TPM

USH & TPM

USH & TPM

LA-F292P

LA-F292P

LA-F292P

38 60Tuesday, November 14, 2017

38 60Tuesday, November 14, 2017

38 60Tuesday, November 14, 2017

1

1.0

1.0

1.0

5

smd.db-x7.ru

4

3

2

1

For PCIEX4,Kirkwood

RF Request

D D

+3.3V_HDD_M2

68P_0402_50V8J

@RF@

1

CN60

2

+3.3V_HDD_M2

0.1U_0201_10V6K

@

CN61

1

2

0.1U_0201_10V6K
22U_0603_6.3V6M

CN62

1

2

22U_0603_6.3V6M

12

12

CN63

CN64

2280 SSD

NGFF slot C Key M

Place near HDD CONN

JNGFF3

CONN@

Need update! CHECK Kirkwood Port Mapping

PCIE_PRX_DTX_N9<10>
PCIE_PRX_DTX_P9<10>

PCIE_PTX_DRX_N9<10>
PCIE_PTX_DRX_P9<10>

PCIE_PRX_DTX_N10<10>

C C

+3.3V_HDD_M2

M2_DEVSLP

1 2

RN37@ 10K_0402_5%

B B

if signal is PCIE GEN3/SATA GEN3 maybe change C value
or no need for DG0.9 SATA EXPRESS HDD

PCIE_PRX_DTX_P10<10>
PCIE_PTX_DRX_N10<10>

PCIE_PTX_DRX_P10<10>

PCIE_PRX_DTX_N11<10>
PCIE_PRX_DTX_P11<10>

PCIE_PTX_DRX_N11<10>
PCIE_PTX_DRX_P11<10>

PCIE_PRX_DTX_P12<10>
PCIE_PRX_DTX_N12<10>

PCIE_PTX_DRX_N12<10>
PCIE_PTX_DRX_P12<10>

12

CN65 0.22U_0402_10V6K

12

CN66 0.22U_0402_10V6K

12

CN67 0.22U_0402_10V6K

12

CN68 0.22U_0402_10V6K

12

CN69 0.22U_0402_10V6K

12

CN70 0.22U_0402_10V6K

12

CN71 0.22U_0402_10V6K

12

CN72 0.22U_0402_10V6K

PCIE_PRX_DTX_N9
PCIE_PRX_DTX_P9

PCIE_PTX_C_DRX_N9
PCIE_PTX_C_DRX_P9

PCIE_PRX_DTX_N10
PCIE_PRX_DTX_P10

PCIE_PTX_C_DRX_N10
PCIE_PTX_C_DRX_P10

PCIE_PRX_DTX_N11
PCIE_PRX_DTX_P11

PCIE_PTX_C_DRX_N11
PCIE_PTX_C_DRX_P11

PCIE_PRX_DTX_P12
PCIE_PRX_DTX_N12

PCIE_PTX_C_DRX_N12
PCIE_PTX_C_DRX_P12

CLK_PCIE_N3<11>
CLK_PCIE_P3<11>

m2280_PCIE_SATA#<10>

67
69

75

2

112

4

334

6

556

8

778

10

9910

12

111112

14

131314

16

151516

18

171718

20

191920

22

212122

24

232324

26

252526

28

272728

30

292930

32

313132

34

333334

36

353536

38

373738

40

393940

42

414142

44

434344

46

454546

48

474748

50

494950

52

515152

54

535354

56

555556

58

575758

68

67

68

70

70

69

72

717172

74

737374
75

76

GND

77

GND

LOTES_YPCI0016-P003A

Link LOTES_YPCI0016-P003A Done (Key M)
20160315

+3.3V_HDD_M2

NVME_LED#

RN100 0_0402_5%@

PCIE_WAKE#

SUSCLK_R

@

RN99 0_0402_5%

1 2

2.5A

PJP31

1 2

PAD-OPEN1x2m

M2_DEVSLP <10>

PCH_PLTRST#_AND <11,23,30,33,38>

CLKREQ_PCIE#3 <11>

PCIE_WAKE# <23,33,37>

1 2

+3.3V_RUN

SATALED# <10,33,43>

SUSCLK <11,33>

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.

5

4

3

2

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

M2 2280 Socket

M2 2280 Socket

M2 2280 Socket

LA-F292P

LA-F292P

LA-F292P

39 60Tuesday, November 14, 2017

39 60Tuesday, November 14, 2017

39 60Tuesday, November 14, 2017

1

1.0

1.0

1.0

5

smd.db-x7.ru

4

3

2

1

For PWR SW + Charger combine IC

EMI@

+5V_USB_CHG_PWR

150U_B2_6.3VM_R35M

100U_1206_6.3V6M

@

1

1

CI32

+

2

2

34

JUSB1

1

VBUS

2

D-

3

D+

4

GND

5

SSRX-

6

SSRX+

7

GND

8

SSTX-

9

SSTX+

SANTA_375230-1

CONN@

LINK 375230-1 DONE
20160315

RF Request

+5V_USB_CHG_PWR

68P_0402_50V8J

RF@

12P_0402_50V8J

RF@

1

1

CI44

CI43

2

2

GND
GND
GND
GND

10
11
12
13

PESD5V0U2BT_SOT23-3

2

USB20_N9_R
USB20_P9_R

USB3_PRX_DTX_N1

ESD@

USB3_PRX_DTX_P1
USB3_PTX_C_DRX_N1

DI5

USB3_PTX_C_DRX_P1

0.1U_0201_10V6K
CI17

1

CI14

2

3

1

USB20_N9_R

USB20_P9_R

DI4

D D

C C

+5V_ALW

RI13

USB3_PRX_DTX_P1<10>

USB3_PRX_DTX_N1<10>

USB3_PTX_C_DRX_P1

USB3_PTX_DRX_P1<10>

USB3_PTX_DRX_N1<10>

ILIM_SEL

12

10K_0402_5%

12

CI16 0.1U_0402_25V6

CI13 0.1U_0402_25V6

USB3_PTX_C_DRX_N1

12

USB_POWERSHARE_VBUS_EN<36>

USB_POWERSHARE_EN#<36>

+5V_ALW

UI3

1

VIN

USB20_N9<10>
USB20_P9<10>

USB_OC0#<10>

ILIM_SEL

2

DM_OUT

3

DP_OUT

13

FAULT#

4

ILIM_SEL

5

EN

6

CTL1

7

CTL2

8

CTL3

SLGC55544CVTR_TQFN16_3X3

CIS Link Seligro SA000097E10 20160304

Thermal Pad

MAIN:SLGC55544CVTR

VOUT

DP_IN

DM_IN

ILIM_L

ILIM_HI

GND

12

10
11

15
16

9

NC

14
17

+5V_USB_CHG_PWR

USB3_PRX_DTX_N1 USB3_PRX_DTX_N1
USB3_PRX_DTX_P1
USB3_PTX_C_DRX_N1
USB3_PTX_C_DRX_P1

SW_USB20_P9
SW_USB20_N9

RI14

12

22.1K_0402_1%

ESD@

1

1

2

2

4

4

5

5

3

3

8

AZ1045-04F_DFN2510P10E-10-9

9

10

8

9

7

7

6

6

SW_USB20_N9

SW_USB20_P9

USB3_PRX_DTX_P1
USB3_PTX_C_DRX_N1
USB3_PTX_C_DRX_P1

LI7

1 2

MCM1012B900F06BP_4P

B B

+5V_ALW

1

2

47U_0603_6.3V6M

47U_0603_6.3V6M

@

1

CI34

2

@

1

CI33

2

Place near UI3.1

10U_0402_6.3V6M

0.1U_0201_10V6K

@

CI19

1

CI31

2

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.

5

4

3

2

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

JUSB1+PS

JUSB1+PS

JUSB1+PS
LA-F292P

LA-F292P

LA-F292P

40 60Tuesday, November 14, 2017

40 60Tuesday, November 14, 2017

40 60Tuesday, November 14, 2017

1

1.0

1.0

1.0

5

smd.db-x7.ru

4

3

2

1

For Breckenridge/Steamboat 12&Kirkwood

DI1

USB3_PRX_DTX_N3
USB3_PRX_DTX_P3
USB3_PTX_C_DRX_N3
USB3_PTX_C_DRX_P3

D D

C C

USB3_PRX_DTX_P3<10>

USB3_PRX_DTX_N3<10>

USB3_PTX_C_DRX_P3

USB3_PTX_DRX_P3<10>

USB3_PTX_DRX_N3<10>

12

CI4 0.1U_0402_25V6

USB3_PTX_C_DRX_N3

12

CI5 0.1U_0402_25V6

USB20_N2<10>

USB20_P2<10>

USB20_N2

USB20_P2

DFB request:
main SM070003Z00 (INPAQ_MCM1012B900F06BP_4P)
Footprint use 2nd source SM070004400 (PANAS_EXC24CQ900U_4P)
Pitch change from 0.5mm to 0.55mm

ESD@

1

1

2

2

4

4

5

5

3

3

8

AZ1045-04F_DFN2510P10E-10-9

9

10

8

9

7

7

6

6

LI3

EMI@

1 2

MCM1012B900F06BP_4P

USB3_PRX_DTX_N3
USB3_PRX_DTX_P3
USB3_PTX_C_DRX_N3
USB3_PTX_C_DRX_P3

USB20_N2_R

USB20_P2_R

34

RF Request

+USB_EX2_PW R

+5V_ALW

12

+USB_EX2_PWR

USB20_N2_R

ESD@

PESD5V0U2BT_SOT23-3

2

DI2

1

USB20_P2_R

USB3_PRX_DTX_N3
USB3_PRX_DTX_P3

USB3_PTX_C_DRX_N3
USB3_PTX_C_DRX_P3

UI1

OUT

5

IN

GND

4

EN

OCB

SY6288D20AAC_SOT23-5

0.1U_0201_10V6K

100U_1206_6.3V6M

CI3

1

12

68P_0402_50V8J

RF@

12P_0402_50V8J

RF@

1

1

Part Reference

CI45

2

2

0.1U_0201_10V6K

10U_0603_10V6M

CI7

@

1

CI6

2

CI1

USB_PWR_EN1#<36>

3

2

1
2
3
4
5
6
7
8
9

LINK 375230-1 DONE
20160315

+USB_EX2_PWR

1
2
3

JUSB2

VBUS
D­D+
GND
SSRX­SSRX+
GND
SSTX­SSTX+

SANTA_375230-1

CONN@

USB_OC1# <10>

GND
GND
GND
GND

10
11
12
13

B B

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EX PRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET N OR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY TH IRD
PARTY WITHOUT DELL'S EX PRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date : Sheet of

Date : Sheet of

Date : Sheet of

Compal Electronics, Inc.

JUSB2

JUSB2

JUSB2

LA-F292P

LA-F292P

LA-F292P

1

41 60Tuesday, November 14, 2017

41 60Tuesday, November 14, 2017

41 60Tuesday, November 14, 2017

1.0

1.0

1.0

5

smd.db-x7.ru

Touch Pad

D D

DAT_TP_SIO_I2C_CLK<36>
CLK_TP_SIO_I2C_DAT<36>

I2C From EC

C C

I2C1_SDA_TP<9>
I2C1_SCK_TP<9>

I2C From CPU

4

+3.3V_TP

4.7K_0402_5%

12

RZ18

PS2

DAT_TP_SIO_R

RZ22 0_0402_5%@

10P_0402_50V8J

10P_0402_50V8J

12

12

CZ80

CZ81

RZ23 0_0402_5%@

@

RZ348 0_0402_5%

@

RZ349 0_0402_5%

12

CLK_TP_SIO_R

12

I2C1_SDA_TP_R

12

I2C1_SCK_TP_R

12

I2C From EC

+3.3V_TP +3.3V_TP

2.2K_0402_5%

2.2K_0402_5%

12

12

RZ21

RZ20

1 2

@

RZ26 0_0402_5%

1 2

@

RZ29 0_0402_5%

I2C1_SDA_TP_R
I2C1_SCK_TP_R

10K_0402_5%

12

@

RZ116

3

+3.3V_RUN +3.3V_TP

PJP35

1 2

4.7K_0402_5%

12

RZ19

PAD-OPEN1x1m

Keyboard

KB_DET#<12>

+5V_RUN

+3.3V_ALW

BC_INT#_ECE1117<36>

BC_DAT_ECE1117<36>

BC_CLK_ECE1117<36>

TP_DISABLE#<36>

10K_0402_5%

12

@

RZ117

+3.3V_TP

TOUCHPAD_INTR#<12,36>

Reserve for future use

2

KB_DET#

BC_INT#_ECE1117
BC_DAT_ECE1117

BC_CLK_ECE1117

DAT_TP_SIO_R

CLK_TP_SIO_R

I2C1_SDA_TP_R
I2C1_SCK_TP_R

+3.3V_TP

1

CZ83

RF@

68P_0402_50V8J

2

JKBTP1

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

GND

22

GND

CHECK PIN DEFINE

KB_DET#

BC_INT#_ECE1117

BC_DAT_ECE1117

BC_CLK_ECE1117

DAT_TP_SIO_R

CLK_TP_SIO_R

CONN@

Link CVILU_CF5020FD0R0-05-NH DONE

CVILU_CF5020FD0RK-05-NH

20160321

1

RF Request

1 2

CZ84 68P_0402_50V8JRF@

1 2

CZ85 68P_0402_50V8J@RF@

1 2

CZ86 68P_0402_50V8J@RF@

1 2

CZ87 68P_0402_50V8J@RF@

1 2

CZ88 68P_0402_50V8J@RF@

1 2

CZ89 68P_0402_50V8J@RF@

0.1U_0201_10V6K

1

@

CZ90

2

Place close to JKBTP1

+5V_RUN+3.3V_ALW+3.3V_TP

0.1U_0201_10V6K

0.1U_0201_10V6K

1

1

@

@

CZ91

CZ92

2

2

Plan is for I2C to be driven by the EC for Win7 and Pre-OS (will utilize Intel I2C drivers for Win7)
For Win8.1 and 10 the EC will control TP over I2C Pre-OS and then the PCH will drive I2C when in Windows
Route PS2 from EC to the touch pad also for contingency plan if I2C has issues

B B

RSMRST circuit

+3.3V_ALW

PCH_RSMRST#<36>

ALW_PWRGD_3V_5V<11,48>

1
2

@

1 2

0.1U_0201_10V6K

5

P

B

4

O

A

G

3

TC7SH08FU_SSOP5~D

CZ82

PCH_RSMRST#_AND <11,14>

UZ6

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.

5

4

3

2

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Keyboard

Keyboard

Keyboard
LA-F292P

LA-F292P

LA-F292P

42 60Tuesday, November 14, 2017

42 60Tuesday, November 14, 2017

42 60Tuesday, November 14, 2017

1

1.0

1.0

1.0

5

smd.db-x7.ru

4

3

2

1

Bat t er y LE D

means EC can switch battery white led and HDD LED by hot key “ Fn+ H”

MASK_SATA_LED#<36>

D D

SATALED#< 10,33,39>

BAT2_LED#<36,43>

HDD LED MUX

5

BAT2_LED#_R

34

QZ2B

@

DMN65D8LDW-7_SOT363-6

+3.3V_ALW

2

61

QZ2A

@

DMN65D8LDW-7_SOT363-6

BAT2_LED#_R

2

R1/R2=1 0K

DDTA114EUA-7-F_SOT323-3
QZ3

1 3

RZ511 150_0402_5%@

@

1 2

BATT_WHITE#

BAT2_LED#<36,43>

BAT1_LED#<36>

1 2

RZ25 330_0402_5%

1 2

RZ28 150_0402_5%

BATT_WHITE#

BATT_YELLOW#

LED P/N change to SC50000FL00 from SC50 000BA00

Breath LED

POWER & INSTANT ON SWITCH

C C

For NPI USE

POWER_SW#_M B<11,37,4 3>

@

SW3

2

4

SKRBAAE010_4P

1

BREATH_LED#<36>

3

RZ32 150_0402_5%

1 2

BREATH_WHITE_LED_SNIFF#

+5V_ALW

POWER_SW#_M B<11,37,4 3>
VOL_UP#<36>
VOL_DOWN#<36>

BREATH_WHITE_LED_SNIFF#

B B

Fiducial Mark

FD1@

1

FIDUCIAL MARK~D

FD2@

1

FIDUCIAL MARK~D

FD3@

1

FIDUCIAL MARK~D

FD4@

1

FIDUCIAL MARK~D

A A

Mask All LEDs (Unobtrusive mode)

Mask Base MB LEDs (Lid Closed)
Do not Mask LEDs (Lid Opened) 11

CPU

H3@

H_3P8

H1@

H_3P8

1

H4@

H2@

H_3P8

H_3P8

1

1

LED Circuit Control Table

H5@

H6@

H_1P1N

H_1P1N

1

1

1

SYS_LED_MASK#

NGFF

H8@

H7@

H_7P0N

H_7P0N

1

1

LID_CL#

0
1 0

H11@

H_2P3

H9@

1

H_2P5

H_5P6

H12@

H_2P3

1

H24@

1

H18@

1

For JAE JSIM1 boss hole

H19@

H20@

H_2P3

H_2P3

1

H30@

H_0P8N

1

1

H_0P8N

H31@

EDP screw hole

ST1@

CLIP_C5P5

1

H_0P9N

1

H32@

1

ST2@

CLIP_C5P5

1

H_1P1N

H33@

1

X

H13@

H_2P5

1

1

H26@

H_2P3

1

H_2P3

H_5P6

H16@

H14@

1

H27@

H_1P3N

1

H28@

1

H_2P3

1

H29@

H_1P3X1P8N

1

H17@

H_2P5N

1

H_3P2

H_2P3

H34@

1

JPWR1

1

1

2

2

3

3

4

4

5

5

6

6

7

GND

8

GND

ACES_50208-0060N-P01

CONN@

Link ACES_50208-0060N-P01 done
20160321

CLP1

CONN@

1

P1

EMIST_SUL-12A2M_1P

CLP16

CONN@

1

P1

EMIST_SUL-12A2M_1P

CLP24

CONN@

1

P1

EMIST_SUL-12A2M_1P

CLP32

CONN@

1

P1

EMIST_SUL-12A2M_1P

CLP33

CONN@

1

P1

EMIST_SUL-12A2M_1P

CLP2

1

P1

EMIST_SUL-12A2M_1P

CLP9

1

P1

EMIST_SUL-12A2M_1P

CLP17

1

P1

EMIST_SUL-12A2M_1P

CLP25

1

P1

EMIST_SUL-12A2M_1P

CLP34

1

P1

EMIST_SUL-12A2M_1P

CONN@

CONN@

CONN@

CONN@

CONN@

CLP4

CONN@

1

P1

EMIST_SUL-12A2M_1P

CLP11

CONN@

1

P1

EMIST_SUL-12A2M_1P

CLP19

CONN@

1

P1

EMIST_SUL-12A2M_1P

CLP27

CONN@

1

P1

EMIST_SUL-12A2M_1P

CLP35

CONN@

1

P1

EMIST_SUL-12A2M_1P

LED board CONNPWR board CONN

+5V_ALW

BATT_YELLOW#
BATT_WHITE#

Link CVILU_CF61062D0R0-05-NH done
20160829

CLP3

CONN@

1

P1

EMIST_SUL-12A2M_1P

CLP10

CONN@

1

P1

EMIST_SUL-12A2M_1P

CLP18

CONN@

1

P1

EMIST_SUL-12A2M_1P

CLP26

CONN@

1

P1

EMIST_SUL-12A2M_1P

CLP36

CONN@

1

P1

EMIST_SUL-12A2M_1P

CLP6

1

P1

EMIST_SUL-12A2M_1P

CLP13

1

P1

EMIST_SUL-12A2M_1P

CLP21

1

P1

EMIST_SUL-12A2M_1P

CLP29

1

P1

EMIST_SUL-12A2M_1P

CLP37

1

P1

EMIST_SUL-12A2M_1P

CONN@

CONN@

CONN@

CONN@

CONN@

JLED1

1

1

2

2

3

3

4

4

5

5

6

6

7

GND

8

GND

CVILU_CF61062D0R0-05-NH

CONN@

CLP5

CONN@

1

P1

EMIST_SUL-12A2M_1P

CLP12

CONN@

1

P1

EMIST_SUL-12A2M_1P

CLP20

CONN@

1

P1

EMIST_SUL-12A2M_1P

CLP28

CONN@

1

P1

EMIST_SUL-12A2M_1P

CLP38

CONN@

1

P1

EMIST_SUL-12A2M_1P

CLP8

CONN@

1

P1

EMIST_SUL-12A2M_1P

CLP15

CONN@

1

P1

EMIST_SUL-12A2M_1P

CLP23

CONN@

1

P1

EMIST_SUL-12A2M_1P

CLP31

CONN@

1

P1

EMIST_SUL-12A2M_1P

CLP7

CONN@

1

P1

EMIST_SUL-12A2M_1P

CLP14

CONN@

1

P1

EMIST_SUL-12A2M_1P

CLP22

CONN@

1

P1

EMIST_SUL-12A2M_1P

CLP30

CONN@

1

P1

EMIST_SUL-12A2M_1P

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS D OCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL . IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

3

PARTY WITHOUT DE LL'S EXPRESS WRITTEN CONSENT.

2

Title

Size

Size

Size

Date : Sheet o f

Date : Sheet o f

Date : Sheet o f

PAD, LED

PAD, LED

PAD, LED

Document Number Re v

Document Number Re v

Document Number Re v

LA-F292P

LA-F292P

LA-F292P

1

43 60Tuesday, November 14, 2017

43 60Tuesday, November 14, 2017

43 60Tuesday, November 14, 2017

1.0

1.0

1.0

5

smd.db-x7.ru

4

3

2

1

+3.3V_WLAN/+3.3V_ALW_PCH source

1

1 2

PAD-OPEN1x2m

CZ122 0.1U_0201_10V6K

CZ109 470P_0402_50V7K

CZ113 470P_0402_50V7K
CZ112 0.1U_0201_10V6K

1 2

PAD-OPEN1x1m

WLAN_PWR_EN

1 2

CZ114 1000P_0402_50V7K

1 2

CZ115 0.1U_0201_10V6K

1 2

PAD-OPEN1x3m

+3.3V_ALW

UZ2

1

VIN1

2

12

2

G

D

AUX_EN_WOW L<36>

VIN1

3

ON1

4

VBIAS

5

ON2

6

VIN2
VIN27VOUT2

EM5209VF_SON14_2X3

RZ518
10K_0402_5%

SLP_WLAN#_M

S

UZ3

1

VIN1

2

VIN1

3

ON1

4

VBIAS

5

ON2

6

VIN2
VIN27VOUT2

EM5209VF_SON14_2X3

VOUT1
VOUT1

VOUT2

D D

PCH_ALW_ON<36>

PCH_PRIM_EN<11,17,50,51,52>

SLP_WLAN#_GATE<36>

SIO_SLP_WLAN#<11,36>

C C

EC request to reserve OR gate for WLAN power enable

+3.3V_RUN source

B B

WLAN_PWR_EN

+5V_ALW

1 2

RZ65 0_0402_5%@

@

1 2

RZ64 0_0402_5%

QZ15

S TR BSS138W 1N SOT-323-3

+5V_ALW

RUN_ON

+3.3V_ALW

1 3

+3.3V_ALW

+3.3V_WLAN_UZ2

14

VOUT1

13

VOUT1

12

CT1

11

GND

10

CT2

9

VOUT2

8
15

GPAD

1 2

RZ71 0_0402_5%@

@

3

2

BAT54CW_SOT323-3

1 2

@

RZ70 0_0402_5%

14
13

12

CT1

11

GND

10

CT2

9
8

15

GPAD

+3.3V_ALW_PCH_UZ3

DZ9

+3.3V_RUN_UZ3

PJP36

1 2

1 2

1 2
1 2

PJP38

PJP39

12

RZ38
100K_0402_5%

2A

+3.3V_WLAN

0.63A

+3.3V_ALW_PCH

+3.3V_RUN

3.435A

+1.8V_RUN source

RUN_ON<17,36,37,44,51>

1 2

@

RZ345 0_0402_5%

12

+5V_RUN

12

@

RZ370
100_0603_5%

+5V_RUN_CHG

+5V_ALW

@

470P_0402_50V7K

RUN_ON_1.8V

CZ197

+1.8V_PRIM

UZ8

1

VOUT

VIN

2

VOUT

VIN

3

ON

4

VBIAS

AOZ1336_DFN8_2X2

GND
GND

CT

7

+1.8V_RUN_UZ8

8
6

5
9

0.013A

PJP42

1 2

PAD-OPEN1x1m

1 2

CZ120 0.1U_0201_10V6K

1 2

CZ121 470P_0402_50V7K

+1.8V_RUN

13

D

@

+5V_RUN/+3.3V_WWAN source

PJP40

CZ118 470P_0402_50V7K

4

1 2

PAD-OPEN1x2m

1 2

CZ116 0.1U_0201_10V6K

1 2

CZ117 470P_0402_50V7K

1 2

1 2

CZ119 0.1U_0201_10V6K

PJP41

1 2

PAD-OPEN1x3m

+5V_ALW

RUN_ON<17,36,37,44,51>

3.3V_WWAN_EN

3.3V_WWAN_EN

+3.3V_ALW

A A

3.3V_WWAN_EN<36>

1 2

RZ40 100K_0402_5%

5

UZ4

1

VIN1

VOUT1

2

VIN1

VOUT1

3

ON1

4

VBIAS

5

ON2

6

VIN2

VOUT2

VIN27VOUT2

EM5209VF_SON14_2X3

GPAD

CT1

GND

CT2

14
13

12
11
10

+3.3V_WW AN_UZ4

9
8

15

+5V_RUN_UZ4

2A

+5V_RUN

+3.3V_WWAN

2.5A

RUN_ON#<36>

Reserve for S3 no power issue (+5V_RUN discharge circuit)

+3.3V_WWAN_UZ4

1

RF@

2200P_0402_50V7K

2

RF Request

2

G

QZ4
L2N7002W T1G_SC-70-3

S

CZ124

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

BE TRANSFERRED OR COPIED WITHOUT THE EX PRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET N OR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY TH IRD
PARTY WITHOUT DELL'S EX PRESS WRITTEN CONSENT.

3

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date : Sheet of

Date : Sheet of

2

Date : Sheet of

Compal Electronics, Inc.

Power control

Power control

Power control

LA-F292P

LA-F292P

LA-F292P

1

44 60Tuesday, November 14, 2017

44 60Tuesday, November 14, 2017

44 60Tuesday, November 14, 2017

1.0

1.0

1.0

5

smd.db-x7.ru

4

3

2

1

Only for Kirkwood

Accelerometer use on 360o hinge designs

+VDD_IO

double check with BIOS for SMB address

D D

+3.3V_WWAN

SAR Sensor

C C

USH_EXPANDER_SMBDAT<36,37,38>

USH_EXPANDER_SMBCLK<36,37,38>

I2C from EC
Reserve CPU path

ISH_I2C0_SDA<9>

DMN65D8LDW-7_SOT363-6

ISH_I2C0_SCL<9>

B B

+3.3V_WWAN

CZ164

@RF@

100P_0402_50V8J

1

2

2

1

6

QZ13A

DMN65D8LDW-7_SOT363-6

+3.3V_RUN

2

1

QZ10A

@

RF Request

SAR_I2C0_SDA SAR_I2C0_SCL

CZ165

1

@RF@

100P_0402_50V8J

2

5

3 4

QZ13B

DMN65D8LDW-7_SOT363-6

6

5

QZ10B

@

DMN65D8LDW-7_SOT363-6

CZ166

@RF@

1 2

SAR_I2C0_SDA
SAR_I2C0_SCL

34

ACES_50208-0040N-001 LINK DONE
20160315

1

100P_0402_50V8J

2

Located on motherboard

+3.3V_WWAN

2.2K_0402_5%
RZ350

2.2K_0402_5%
RZ351

+3.3V_WWAN

1 2

JSAR1

1

1

2

2

3

3

4

4

ACES_50208-0040N-001

CONN@

5

G1

6

G2

Located near the WWAN antenna

ISH_I2C0_SCL
ISH_I2C1_SCL<9,36>
ISH_I2C1_SDA<9,36>

A A

5

ALS I2C reserve EC solution

USH_EXPANDER_SMBCLK

USH_EXPANDER_SMBDAT

ISH_I2C1_SCL

ISH_I2C0_SDA

ISH_I2C1_SDA

ISH_GP3

3 4

DMN65D8LDW-7_SOT363-6

4

@

QZ14B

@

RZ137 0_0402_5%

RZ138 0_0402_5%@

@

RZ140 0_0402_5%
RZ141 0_0402_5%@

@

RZ143 0_0402_5%

RZ145 0_0402_5%@

I2C2_SDA_ALS<9>

I2C2_SCL_ALS<9>

+3.3V_RUN

2

6

QZ14A

@

5

DMN65D8LDW-7_SOT363-6

1

1 2
1 2
1 2
1 2
1 2

3.3V_ALS_EN#

1 2

ALS_I2C0_SCL

ALS_I2C0_SDA

ACC1_I2C0_SCL
ALS_I2C0_SCL
ACC1_I2C0_SDA
ALS_I2C0_SDA
ACC1_INT1ISH_GP0

ALS_INT#

+5V_ALW

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WR ITTEN CONSENT.

3

12

RZ121

@

0_0402_5%

ACC1_SA0

12

@

RZ122

0_0402_5%

+1.8V_RUN

@

@

Detect closed in tablet position

+3.3V_ALW +3.3V_ALW

0.1U_0201_10V6K

1
@

CZ188

LID_CL_SIO_TAB#<36> LID_CL#<37>

2

Hall sensor: SA00009CB00

3.3V_ALS_EN#

+3.3V_RUN

12

JSEN2

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

GND

14

GND

ACES_50208-01201-P01

CONN@

LINK ACES_50208-01001-P03 Done
20160321

+3.3V_RUN

10U_0603_10V6M

12

12

CZ168

1 2

RZ509 0_0402_5%

1 2

RZ510 0_0402_5%

+3.3V_ALW

ISH_GP0

RE52110K_0402_5%

ISH_GP1

ISH_GP2

+VDD_IO

0.1U_0201_10V6K

CZ169

ACC1_SA0
ISH_I2C0_SDA
ISH_I2C0_SCL

UZ28

2

VCC

3

VOUT

TCS40DLR_SOT23F3

RB751S-40 SOD-523

RB751S-40 SOD-523

RB751S-40 SOD-523

RB751S-40 SOD-523

RB751S-40 SOD-523

RB751S-40 SOD-523

0.1U_0201_10V6K

12

CZ170

+VDD_IO+3.3V_RUN

GND

1 2

DZ100

1 2

DZ101

1 2

DZ102

1 2

DZ103

@

1 2

DZ104

1 2

DZ105

2

LGA1

LNG2DM

10

VDD_IO

9

VDD

3

SDO/SA0

4

SDA/SDI/SDO
SCL/SPC1GND

2

CS

LNG2DMTR_LGA12_2X2

1

Level Shift

ISH_GP0_D

ISH_GP1_D

ISH_GP2_D

ISH_GP3_DISH_GP3

LID_CL#_NB_DLID_CL#

LID_CL#_TAB_DLID_CL_SIO_TAB#

INT 1
INT 2

GND
GND

RES

5

ISH_GP1

12
11

6
7
8

HIGH ACTIVE

LNG2DMTR Interrupt active value.Default value:0
(0:active high; 1:active low)

GPP_A GROUP is +1.8V power rail

Located on MB

Detect clamshell closed

UZ1

0.1U_0201_10V6K

1
@

CZ167

2

Place CZ1 near UZ1.

2

VCC

GND

3

VOUT

TCS40DLR_SOT23F3

Hall sensor: SA00009CB00

CPU sideDevice Side

ISH_GP0_D <9>

ISH_GP1_D <9>

ISH_GP2_D <9>

ISH_GP3_D <9>

LID_CL#_NB_D <9>

LID_CL#_TAB_D <9>

ISH_GP0_D
ISH_GP1_D
ISH_GP2_D
ISH_GP3_D
LID_CL#_NB_D
LID_CL#_TAB_D

ISH_GP0
ISH_GP1
ISH_GP2
ISH_GP3
LID_CL#
LID_CL_SIO_TAB#

1 2

RZ501 10K_0402_5%

1 2

RZ502 10K_0402_5%

1 2

RZ503 10K_0402_5%

1 2

RZ504 10K_0402_5%@

1 2

RZ512 10K_0402_5%

1 2

RZ513 10K_0402_5%

1 2

RZ505 10K_0402_5%@

1 2

RZ506 10K_0402_5%@

1 2

RZ507 10K_0402_5%@

1 2

RZ508 10K_0402_5%@

1 2

RZ514 10K_0402_5%@

1 2

RZ515 10K_0402_5%@

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

SENSOR

SENSOR

SENSOR
LA-F292P

LA-F292P

LA-F292P

1

1

+1.8V_RUN

+3.3V_RUN

1.0

1.0

45 60Tuesday, November 14, 2017

45 60Tuesday, November 14, 2017

45 60Tuesday, November 14, 2017

1.0

5

smd.db-x7.ru

Timing Diagram for S5 to S0 mode

11

CPU

VCCST_PWRGD

PROCPWRGD

PLTRST#

DDR_VTT_CNT L

+PWR_SRC

TLV62130

+3.3V_ALW

TLV62130

+PWR_SRC

SIO_SLP_WLAN#

D D

6

C C

VCCST_PWRGD

12

H_CPUPWR GD

15

PCH_PLTRS T#

17

0.6V_DDR_VTT_ON

12

+1.0V_PRIM_CORE

+1.8V_PRIM

6

6

+1.0V_PRIM SYX198

VCCIO

VCCGT

VDDQ
VDDQC
VCCPLL_OC

VCCST
VCCSTG
VCCPL L

VCCSA

SIO_SLP_SU S#

+VCC_CORE

VCC

+1.0VS_VCCIO

+VCC_GT

+1.2V_MEM

+1.0V_VCCST

+VCC_SA

EC 5105

4

+1.0V_PRIM

11

TPS22961

SIO_SLP_S4 #

+LCDVDD

11

+5V_TSP

3

+3.3V_ALW

+3.3V_SPI

3

+1.0V_MPHYGT

5

6

+1.0V_PRIM_CORE

6

17

4

+3.3V_ALW

AP2821K

+3.3V_ALW

EM5209VF+3.3V_LAN

+5V_RUN

LP2301ALT1G

+3.3V_RUN

LP2301ALT1G+3.3V_CAM

+1.0V_PRIM

+3.3V_ALW_DSW

+3.3V_ALW_PCH

+1.8V_PRIM

+RTC_CEL L

PCH_PLTRS T#

PCH_DPWR OK

ENVDD_PCH

SIO_SLP_LAN#

3.3V_TS_EN

3.3V_CAM_EN#

VCCPRIM_1P0
VCCPRIM_CORE
DCPDSW _1P0
VCCMPHYAON_1P0
VCCAPLL_1P0
VCCCLK1~ 6
VCCMPHYGT_1P0
VCCSRAM_1P0
VCCAMPHYPLL_1P0
VCCAPLLEBB

VCCDSW_3P 3

VCCHDA
VCCSPI
VCCPRIM_3P3
VCCPGPPA~E
VCCRTCPRIM

VCCPGPPG
VCCATS

VCCRTC

VCCPRIM_CORE

PLTRST#

DSW_PWROK

EDP_VDDEN

SLP_LAN#

GPP_B21

GPD7

PCH

PWRBTN#

RSMRST#

SLP_SUS #

SLP_S5 #

SLP_S4 #

SLP_S3 #

SLP_LAN#

SLP_WLAN#/GPD 9

SYS_PWROK

PCH_PWRO K

VCCST_PWRGD

PROCPWRGD

2

SLP_A#

Power Button

SIO_PWRBTN#

PCH_RSMRST #

SIO_SLP_SU S#

SIO_SLP_S5 #

SIO_SLP_S4 #

SIO_SLP_S3 #

SIO_SLP_A#

SIO_SLP_LAN#

SIO_SLP_WLAN#

RESET_OUT#

PCH_PWRO K

VCCST_PWRGD

H_CPUPWR GD

16

15

10

11

14
12

1

8

7

5

9

2AC1BAT

11

RUN_ON

+5V_ALW

EM5209VF

+3.3V_ALW

EM5209VF

+5V_RUN

+3.3V_RUN

+5V_HDD

+3.3V_HDD

ADAPTER

BATTERY

ALWON

+PWR_SRC

SYX198EC 5105

+PWR_SRC

SYX198

+5V_ALW2
+5V_ALW

+3.3V_RTC_LDO
+3.3V_ALW2
+3.3V_ALW

1BAT

2AC

B B

@SIO_SLP_WLAN#

+3.3V_ALW

+3.3V_WLAN EM5209VF

11

AUX_EN_WOWL

MCP 23008

A A

+PWR_SRC

TLV62130

+1.0VS_VCCIO

13

SM BUS

+VCC_SA

+VCC_CORE

+VCC_GT

PCH_PWRO K

7
4

16

5

10

9

11

+PWR_SRC

ISL95857

14

PCH_RSMRST #

PCH_DPWR OK

RESET_OUT#

SIO_SLP_SU S#

SIO_SLP_S4 #

SIO_SLP_S5 #

SIO_SLP_LAN#

SIO_SLP_S3 #

SIO_SLP_A#

12

IMVP_VR_ON

5

SIO_SLP_SU S#

@PCH_ALW_ON

EN_INVPWR

10

SIO_SLP_S4 #

0.6V_DDR_VTT_ON

+3.3V_ALW

EM5209VF

+PWR_SRC

AO6405

+PWR_SRC

RT8207MZ

+3.3V_ALW_PCH

+BL_PWR_SRC

+1.2V_MEM
+0.6V_DDR_VTT

12

5

Pop option

+3.3V_SPI

18

VDDQ

VTT

DDR

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Compal Electronics, Inc.

Title

Title

Title

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Date : Sheet of

Date : Sheet of

Date : Sheet of

LA-F292P

LA-F292P

LA-F292P

Power Sequence

Power Sequence

Power Sequence

1

46 60Tuesday, Novem ber 14, 2017

46 60Tuesday, Novem ber 14, 2017

46 60Tuesday, Novem ber 14, 2017

1.0

1.0

1.0

5

smd.db-x7.ru

4

3

2

1

+COINCELL

COIN RTC Battery

12

PR2

+Z4012

2

3

PD3

1

PBAT_PRES# (36,56)

1K_0402_5%

+RTC_CELL

1

PC3
1U_0603_25V6K

2

+COINCELL

+3.3V_RTC_LDO

D D

1

PD1

@ESD@

TVNST52302AB0_SOT523-3

2

Primary Battery Connector

PBATT1

1

1

2

2

3

3

4

4

5

5

12

PC1

EMC@

2200P_0402_50V7K

C C

6

6

7

7

8

8

9

9

10

10

11

GND

12

GND

13

GND

14

GND

DEREN_40-42507-01001RHF

GND

PBAT_SMBCLK_C
PBAT_SMBDAT_C
PBAT_PRES#_C

GND

PRP1

100_0804_8P4R_5%

3

18
27
36
45

1

PD2

@ESD@

TVNST52302AB0_SOT523-3

2

3

PBATT+_C

PBAT_CHARGER_SMBDAT (36,56)

PBAT_CHARGER_SMBCLK (36,56)

PL1

EMC@

FBMJ4516HS720NT_2P

1 2

PL2

EMC@

FBMJ4516HS720NT_2P

1 2

+PBATT

+3.3V_ALW

12

PR1
100K_0402_5%

BAS40CW SOT-323

PC2

EMC@

2200P_0402_50V7K

12

1
2

3
4

JRTC1

@

1
2

GND
GND

ACES_50271-0020N-001

B B

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2

Title

Size

Size

Size

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

BATT/RTC

BATT/RTC

BATT/RTC

Document Number Re v

Document Number Re v

Document Number Re v

LA-F292P

LA-F292P

LA-F292P

1

48 59Tuesday, November 14, 2017

48 59Tuesday, November 14, 2017

48 59Tuesday, November 14, 2017

1.0

1.0

1.0

A

smd.db-x7.ru

1 1

+PWR_SRC

PJP100

21

PAD-OPEN 1x2m~D

12

12

PC134

PC133

1000P_0402_50V7K

1000P_0402_50V7K

@EMC@

@EMC@

2 2

12

12

PC136

PC135

1U_0402_25V6K

1U_0402_25V6K

@EMC@

@EMC@

12

PC100

0.1U_0402_25V6

RF@

RF demand

PC103

RF@

+3.3V_ALW

12

PC131

RF@

2200P_0402_50V7K

PR107
100K_0402_5%

1 2

PGOOD_3V

3V_VIN

12

82P_0402_50V8J

12

PC105

10U_0603_25V6M

B

BST_3V

2

EN112EN2

IN3IN4IN

FF13OUT14NC

3V_FB

1

IN

BS

20

LX

19

LX

18

GND

17

LDO

16

NC

21

GND

15

PC113
1000P_0402_50V7K

1 2

12

PC111

4.7U_0603_6.3V6K

PR108

1K_0402_5%

1 2

1 2

1 2

5

LX_3V

3V5V_EN

PU100

6

LX

7

GND

8

SY8288BRAC_QFN20_3X3

GND

9

PG

10

NC

11

ENLDO_3V5V

12

PC104

10U_0603_25V6M

C

PR100

@

0_0603_5%

1 2

PR104

@

0_0402_5%

PR105

@

0_0402_5%

LX_3V

PC102

1 2

0.1U_0603_25V7K

+3.3V_ALW2

+3.3V_RTC_LDO

3.3V LDO 150mA~300mA

PGOOD_3V
PGOOD_5V

PL100

2.2UH_PCMB062D-2R2MS_7A_20%

1 2

PR106

12

4.7_1206_5%

@EMC@

3V_SN

12

PC112

680P_0603_50V7K

@EMC@

D

PR119

@

0_0402_5%

1 2
1 2

PR120

@

0_0402_5%

PR102

ENLDO_3V5V

PR103

499K_0402_1%

1 2

12

499K_0402_1%

12

12

PC107

PC106

22U_0603_6.3V6M

Vout is 3.234V~3.366V

ALW_PWRGD_3V_5V (11,42)

+PWR_SRC

12

12

PC108

22U_0603_6.3V6M

22U_0603_6.3V6M

+3.3V_ALWP +3.3V_ALW

12

12

PC109

22U_0603_6.3V6M

PC129

PC110

22U_0603_6.3V6M

12

22U_0603_6.3V6M

3VALWP
TDC 5.6 A
Peak Current 6.7 A
OCP Current 11.5 A

12

PC162

PC161

@

@

22U_0603_6.3V6M

22U_0603_6.3V6M

PJP102

2

112

JUMP_43X118

E

+3.3V_ALWP

+PWR_SRC

PJP101

21

PAD-OPEN 1x2m~D

12

12

PC137

PC138

3 3

1000P_0402_50V7K

1000P_0402_50V7K

@EMC@

@EMC@

ALWON(36)

12

12

PC140

PC139

1U_0402_25V6K

1U_0402_25V6K

@EMC@

@EMC@

PR114

@

0_0402_5%

1 2

PC115

RF@

RF demand

4 4

5V_VIN

12

12

12

PC132

PC116

0.1U_0402_25V6

82P_0402_50V8J

RF@

RF@

2200P_0402_50V7K

+3.3V_ALW

3V5V_EN

12

12

PC128

PR116

1M_0402_1%

4.7U_0603_6.3V6K

EN1 and EN2 dont't floating

12

PC117

10U_0603_16VAK

PR113
100K_0402_5%

1 2

PGOOD_5V

5

LX_5V

PU102

6
7
8
9

10

LX
GND
GND
PG
NC

IN3IN4IN

SYV828CRAC QFN 20P PWM

EN112EN2

FF13OUT14LDO

11

3V5V_EN

ENLDO_3V5V

12

PC118

10U_0603_16VAK

2

1

IN

15

12

BST_5V

BS

20

LX

19

LX

18

GND

17

VCC

16

NC

21

GND

+5V_ALW2

5V LDO 150mA~300mA

PC126

4.7U_0603_6.3V6K

PC127
1000P_0402_50V7K

5V_FB

1 2

@

0_0603_5%

1 2

PC119

1 2

4.7U_0603_6.3V6K

1K_0402_5%

PR111

LX_5V

PR117

1 2

PC114

1 2

0.1U_0603_25V7K

PL101

1UH +-20% PCMB062D-1R0MS 9A

1 2

12

PR112

@EMC@

4.7_1206_5%

5V_SN

12

PC125

@EMC@

680P_0603_50V7K

12

12

PC120

22U_0603_6.3VAM

12

12

PC121

PC122

22U_0603_6.3VAM

22U_0603_6.3VAM

5VALWP
TDC 7.8 A
Peak Current 9 A
OCP Current 11.5 A

12

12

PC123

PC124

22U_0603_6.3VAM

22U_0603_6.3VAM

PC130

12

22U_0603_6.3VAM

PJP103

112

JUMP_43X118

12

PC151

PC150

22U_0603_6.3VAM

2

+5V_ALW+5V_ALWP

+5V_ALWP

12

12

PC164

PC163

@

@

22U_0603_6.3VAM

22U_0603_6.3VAM

22U_0603_6.3VAM

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

D

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

+5V_ALW/3.3V_ALW

+5V_ALW/3.3V_ALW

+5V_ALW/3.3V_ALW

LA-F292P

LA-F292P

LA-F292P

49 59Tuesday, November 14, 2017

49 59Tuesday, November 14, 2017

49 59Tuesday, November 14, 2017

E

1.0

1.0

1.0

5

smd.db-x7.ru

D D

4

3

2

1

+PWR_SRC

C C

The current limit is
set to 8A, 12A or 16A
when this pin is pull
low, floating or pull
high
+1.2V_DDR OCP set 8A

B B

PJP202

PAD-OPEN 1x2m~D

PR208

PR210

+1.2V_DDR_B+

+3.3V_ALW

1U_0402_6.3V6K

12

PR209

1M_0402_5%

PU200

10

IN

13

BYP

PC206

2.2U_0402_6.3V6M

12

PC207

ILMT_DDR

S5_1.2V

14

VCC

4

VTTGND

9

PGND

15

SGND

17

ILMT

1

S5

2

S3

SY8210AQVC_QFN19_4X3

Layout for Pin4,9,15

VDDQSNS

VLDOIN

VTT

VTTSNS

VTTREF

19

OT

18

PR203

PG

BS
LX
FB

@

0_0603_5%

1 2

12
11
16

+1.2V_DDRP

8
7
6
5
3

LX_DDR

PC205

0.1U_0603_16V7K

1 2

1U_0402_10V6K

PC218

12

12

RF@

PR202

4.7_1206_5%

1 2

PL201

1 2

1UH_PCMB062D-1R0MS_9A_20%

PC209

22U_0603_6.3V6M

1 2

+0.6VSP

22U_0603_6.3V6M

PC219

RF@

PC204

680P_0603_50V7K

1 2

12

+1.2V_DDRP

330P_0402_50V7K

102K_0402_1%

12

PR204

PC208

R1

100K_0402_1%

12

PR206

R2

22U_0603_6.3V6M

22U_0603_6.3V6M

PC211

PC210

12

12

22U_0603_6.3V6M

22U_0603_6.3V6M

PC212

12

10U_0603_6.3V6M

10U_0603_6.3V6M

PC213

12

12

PC214

PC223

12

100P_0402_50V8J

2200P_0402_50V7K

EMC@

EMC@

12

12

PC217

PC216

VTTGND , PGND seperate GND via
PGNE Cin_cap shape GND via
SGND alone GND

12

12

PC221

@

0.1U_0402_10V7K

12

PR212

1M_0402_5%

12

PC222

@

0.1U_0402_10V7K

Mode S3 S5 VOUT VTT
Normal H H on on
Stadby L H on off
Shutdown L L off off

+1.2V_DDR
TDC 6.4A
Peak Current 9.7A
OCP Current 11.6A

PJP200@

JUMP_43X118

112

@

2

JUMP_43X39

0.6Volt +/- 5%
TDC 0.007A
Peak Current 0.01A
OCP Current 2A (fix)

PJP201

112

+0.6V_DDR_VTT+0.6VSP+1.2V_MEM+1.2V_DDRP

2

21

12

PC200

PC201

10U_0603_25V6M

10U_0603_25V6M

+3.3V_ALW

1 2

1 2

0.6V_DDR_VTT_ON(7)

12

@

PR205
0_0402_5%

ILMT_DDR

@

PR207
0_0402_5%

SIO_SLP_S4#(11,17,36,52)

82P 50V J NPO 0402

12

12

PC202

RF@

RF@

RF demand

0.1U 25V K X5R 0402
PC203

@

0_0402_5%

1 2

@

0_0402_5%

1 2

Note: S3 - sleep ; S5 - power off

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

+1.2V_MEN/+0.6V_DDR_VTT

+1.2V_MEN/+0.6V_DDR_VTT

+1.2V_MEN/+0.6V_DDR_VTT

LA-F292P

LA-F292P

LA-F292P

50 59Tuesday, November 14, 2017

50 59Tuesday, November 14, 2017

50 59Tuesday, November 14, 2017

1

1.0

1.0

1.0

5

smd.db-x7.ru

D D

+PWR_SRC

C C

PJP301

PAD-OPEN 1x2m~D

PCH_PRIM_EN(11,17,44,51,52)

21

12

12

PC301

@RF@

100P_0402_50V8J

PR312

@

0_0402_5%

1 2

1M_0402_1%

PC303

@RF@

PR302

100P_0402_50V8J

PC305

10U_0603_25V6M

EN_+1VALWP

12

+3.3V_ALW

+3.3V_ALW

12

PR307

@

B B

0_0402_5%

12

@

0_0402_5%

ILMT_+1VALWP

PR310

4

+1VALW P_B+

12

12

PC306

10U_0603_25V6M

PC312

1U_0402_6.3V6K

+1.0V_PRIM
TDC 3.5A
Peak Current 6.5 A
OCP Current 9 A Fix by IC
TYP MAX
Choke DCR 11.0mohm , 12.0mohm

PU301

2

IN

3

IN

4

IN

5

IN

7

GND

8

GND

18

GND

11

EN

13

ILMT

15

BYP

12

SY8286RAC_QFN20_3X3

VCC

PAD

PG
BS
LX
LX
LX
FB

NC
NC
NC

9
1
6
19
20
14
17
10
12
16
21

BST_+1VALWP

3

PR304

@

0_0402_5%

1 2

SW_+1VALWP

12

2.2U_0402_6.3V6M

PC313

0.1U_0201_10V6K

BST_+1VALWP_C

PC304

1 2

FB_+1VALWP

PR303

@EMC@

4.7_1206_5%

1 2

1UH_PCMB051H-1R0MS_8A_20%

SNB_+1VALWP

PL301

1 2

12

PR306

21.5K_0402_1%

12

2

PC302

@EMC@

680P_0603_50V7K

1 2

12

12

PR308

1K_0402_5%

PR311

31.6K_0402_1%

+1VALWP

12

PC307

330P_0402_50V7K

1

PJP302

2

112

JUMP_43X118

+1.0V_PRIM

+1VALWP

12

12

PC308

PC309

22U_0603_6.3V6M

22U_0603_6.3V6M

12

PC310

PC311

22U_0603_6.3V6M

22U_0603_6.3V6M

The current limit is set to 6A, 9A or 12A when this pin
is pull low, floating or pull high

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

3

2

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

+1VALWP

+1VALWP

+1VALWP

51 59Tuesday, November 14, 2017

51 59Tuesday, November 14, 2017

51 59Tuesday, November 14, 2017

1

1.0

1.0

1.0

5

smd.db-x7.ru

4

3

2

1

+3.3V_ALW

LPM LOGIC

EN_1VS_VCCIO

13

PU401

EN

PVIN

PVIN

TPS62134CRGT_QFN16_3X3

AVIN

VID0

VID1

8

12

PR427

0_0402_5%

@

12

14

LPM

SS_1VS_VCCIO

PR404
0_0402_5%

7

12

@

PJP401

JUMP_43X79

2

+1VS_VCCIOP

12

PR421
0_0402_5%

112

PR422

@

0_0402_5%

1 2

12

PC406

22U_0603_6.3V6M

12

PC407

22U_0603_6.3V6M

VCCIO_SENSE (17)

VSSIO_SENSE (17)

12

PC422

22U_0603_6.3V6M

+1VS_VCCIOP +1.0VS_VCCIO

15

17

TP

PGND16PGND

1

VOS

LX_1VS_VCCIO

2

SW

3

SW

4

PG

FBS5AGND6SS

PC410

470P_0402_50V7K

+1VS_VCCIOP

PL402

1UH_1277AS-H-1R0N-P2_3.3A_30%

1 2

12

PR405

@EMC@

4.7_0603_5%

SNUB_1VS_VCCIO

12

PC401

@EMC@

470P_0402_50V7K

PR412

@

0_0402_5%

1 2

TPS62134 C 1 0

+1VS_VCCIOP

PR425

@

0_0402_5%

PR403

1M_0402_1%

VIN_1VS_VCCIO

VID0_VCCIO

VID1_VCCIO

1 2

12

12

PC402

@

0.1U_0402_25V6

12

11

10

9

SIO_SLP_S0#(11,17,38,51)

PR402

@

0_0402_5%

RUN_ON(17,36,37,44)

D D

+5V_ALW

+3.3V_ALW

PL407

@

3A_Z120_40M_0603_2P

1 2

PL405

3A_Z120_40M_0603_2P

1 2

+3.3V_ALW

12

12

@

10K_0402_1%

12

C C

10K_0402_1%

PR413

PR415

12

PR414

10K_0402_1%

12

@

PR416

10K_0402_1%

VID0_VCCIO
VID1_VCCIO

12

PC408

PC409

0.1U_0402_25V6

2200P_0402_50V7K

@EMC@

@EMC@

1 2

12

12

PC403

PC404

10U_0603_10V6M

10U_0603_10V6M

VID1 LOGIC

0

1

1

1

+1.0VS_VCCIO
TDC 1.9 A
Peak Current 2.7 A
OCP Current 3.3 A
TYP MAX
Choke DCR 48.0mohm

VID0 LOGIC

X

0

1

1

"R" for SILERGY

OUTPUT VOLTAGE

X

0

1

0

1 1 .05

0(LPM)

0.80

0.95

1.00

+3.3V_ALW

12

PR410

PR426

@

0_0402_5%

SIO_SLP_S0#(11,17,38,51)

1 2

0_0402_5%

@

PJP402

Rup

JUMP_43X79

112

2

+1.0V_PRIM_COREP

12

PC415

12

12

PC427

PC424

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

+1.0V_PRIM_CORE
TDC 1.8 A
Peak Current 2.6 A
OCP Current 3.1 A
TYP MAX
Choke DCR 48.0mohm

LPM LOGIC

TPS62134 D 1 0

VID1 LOGIC

0

1

1

1

VID0 LOGIC

X

0

1

1

OUTPUT VOLTAGE

X

0

1

0

1 1.00

0.7(LPM)

0.85

0.90

0.95

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size

Size

Size

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

+1VS_VCCIOP/+1.0V_PRIM_COREP

+1VS_VCCIOP/+1.0V_PRIM_COREP

+1VS_VCCIOP/+1.0V_PRIM_COREP

Document Number Re v

Document Number Re v

Document Number Re v

LA-F292P

LA-F292P

LA-F292P

1

52 59Tuesday, November 14, 2017

52 59Tuesday, November 14, 2017

52 59Tuesday, November 14, 2017

1.0

1.0

1.0

PR406

@

0_0402_5%

PCH_PRIM_EN(11,17,44,50,52)

PL408

@

3A_Z120_40M_0603_2P

B B

+5V_ALW

+3.3V_ALW

1 2

PL406

3A_Z120_40M_0603_2P

1 2

+3.3V_ALW

12

12

PC417

PC421

RF demand

PR417

10K_0402_1%

PR419

@

10K_0402_1%

12

10K_0402_1%

12

@

10K_0402_1%

PR418

VID0_PRIM_CORE
VID1_PRIM_CORE

PR420

12

12

A A

PC418

0.1U_0402_25V6

82P_0402_50V8J

2200P_0402_50V7K

RF@

RF@

CORE_VID0(18)

CORE_VID1(18)

1 2

12

12

PC412

PC413

10U_0603_10V6M

10U_0603_10V6M

12

RF@

PR407

1M_0402_1%

VIN_1V_PRIM

PR408

@

0_0402_5%

1 2

PR411

@

0_0402_5%

1 2

12

12

PC411

EN_1.0V_PRIM_COREP

@

0.1U_0402_25V6

13

15

14

PU402

EN

PVIN

PVIN

TPS62134DRGT_QFN16_3X3

AVIN

VID0

VID1

8

VID1_PRIM_CORE

LPM

7

SS_1V_PRIM

12

12

11

10

9

VID0_PRIM_CORE

17

PGND16PGND

12

PR428

PC420

@

1M_0402_1%

470P_0402_50V7K

+1.0V_PRIM_COREP +1.0V_PRIM_CORE

TP

1

VOS

SW

SW

PG

FBS5AGND6SS

+1.0V_PRIM_COREP

1UH_1277AS-H-1R0N-P2_3.3A_30%

LX_1V_PRIM

2

3

12

@

100K_0402_1%

PR424

12

SNUB_1V_PRIM

12

4

PL404

1 2

PR409

@EMC@

4.7_0603_5%

PC419

@EMC@

470P_0402_50V7K

PR423

@

0_0402_5%

1 2

"R" for SILERGY

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

3

5

smd.db-x7.ru

+3.3V_ALW

D D

PCH_PRIM_EN(11,17,44,50,51)

C C

4

PL502

@

3A_Z120_40M_0603_2P

1 2

PJP501

1 2

PAD-OPEN1x1m

+3.3V_ALW

1.8V_PRIM_PWRGD(36)

PR504

@

0_0402_5%

1 2

PR505

1M_0402_1%

Note:
When design Vin=5V, please stuff snubber
to prevent Vin damage

12

PC502

PR517
100K_0402_5%

12

VIN_1.8VALW

22U_0603_6.3V6M

12

12

@

0.1U_0402_16V7K

EN_1.8VALW

PC505

PU501

4

IN

5

PG

GND

FB6EN

RT8097ALGE_SOT23-6

3

PJP502

PL501

1 2

20K_0402_1%

FB_1.8VALW

10K_0402_1%

1 2

PAD-OPEN1x1m

PR501

PR506

12

Rup

12

Rdown

+1.8VALWP

Imax= 2A, Ipeak= 3A
FB=0.6V

LX_1.8VALW

3

LX

2
1

1UH_1277AS-H-1R0N-P2_3.3A_30%

12

PR502

@EMC@

4.7_0603_5%

SNUB_1.8VALW

12

PC506

@EMC@

680P_0402_50V7K

+1.8V_PRIM

12

PC503

68P_0402_50V8J

12

12

PC501

22U_0603_6.3V6M

+1.8V_PRIM
TDC 2 A
Peak Current 3 A
OCP Current 3.5A

2

PC504

22U_0603_6.3V6M

1

+1.8VALWP

Vout=0.6V* (1+Rup/Rdown)

B B

+1.8V_MEM
TDC 0.5 A
Peak Current 0.7 A
OCP Current 0.8 A

PJP505

+3.3V_ALW

SIO_SLP_S4#(11,17,36,49)

1 2

PAD-OPEN1x1m

@

0_0402_5%

1 2

A A

PR513

1M_0402_1%

PR514

+1.8V_VIN

12

PC514

4.7U_0603_6.3V6K

12

EN_1.8V

12

@

.1U_0402_16V7K

PU503

AP7361C-FGE-7-01_U-DFN3030-8_3X3

9

GND

8

IN

7

NC

6

NC

5

EN

PC513

ADJ/NC

PJP506

1 2

PAD-OPEN1x1m

22U_0603_6.3V6M

+1.8V_MEM

1

OUT

2

NC

3
4

GND

PR515

12.7K_0402_1%

12

12

PR516

10.2K_0402_1%

1.8V_out

12

0.01UF_0402_25V7K

PC515

12

PC516

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

3

2

Title

Size

Size

Size

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

+1.8VALWP/1.8V_MEN

+1.8VALWP/1.8V_MEN

+1.8VALWP/1.8V_MEN

Document Number Re v

Document Number Re v

Document Number Re v

LA-F292P

LA-F292P

LA-F292P

1

53 59Tuesday, November 14, 2017

53 59Tuesday, November 14, 2017

53 59Tuesday, November 14, 2017

1.0

1.0

1.0

5

smd.db-x7.ru

4

3

2

1

+1.0V_VCCST

PR602

@

12

12

Local sense put on HW site

D D

PROCHOT#(12,36,56)

470K_0402_5%_B25/50 4700K

PH601

1 2
1 2

PR631

27.4K_0402_1%

2200P_0402_50V7K

VCCSENSE(15)

C C

VSSSENSE(15)

ISUMP_IA(54)

@

20M_0402_5%

ISUMN_IA(54)

B B

IA OCP : 77A by PR638 setting 453 (for U42)
IA OCP : 38A by PR638 setting 365 (for U22)
GT OCP : 37A by PR640 setting 357
SA OCP : 10A by PR636 setting 665

PR608 setting 88.7K for
IA IccMax : 64A
GT IccMax : 31A

A A

SA IccMax : 6A

PR658

@

1 2

330P_0402_50V7K

PC619

1 2

0.01UF_0402_25V7K

12

1 2

12

PH602

10K_0402_5%_B25/50 4250K

PC614

1 2

PC618

PR628

4.99K_0402_1%

12

12

PC641

.1U_0402_16V7K

1 2

PC605 47P_0402_50V8J

PR610
10K_0402_1%

1 2

PR617

@

4.3K_0402_1%

1 2

PC616

@

33P_0402_50V8J

1 2

12

@

PR633

11K_0402_1%

PC635

@U42

0.022U_0402_16V7K

1 2

PC638

@U42

0.022U_0402_16V7K

ISEN2_IA

1 2

12

PC620

@

PC624

0.033U_0402_16V7K

ISEN1_IA(54)
ISEN2_IA(54)

VIDSCLK(15)

VIDALERT_N(15)
VIDSOUT(15)

PR678

100_0402_1%

1 2

PC617

@

1200P_0402_50V7K

1 2

PC621
680P_0402_50V7K

1 2

0.082U_0402_16V7K

12

PC626

@

0.01U_0402_25V7K

PR613

@

86.6K_0402_1%

1 2

PC613
330P_0402_50V7K

@

316_0402_1%

1 2

PR622

@

1.5K_0402_1%

1 2

1 2

PR632

1K_0402_1%

1 2

@

360_0402_1%

1 2

ISEN1_IA

1 2

PR621

PR623
2K_0402_1%

PR638

@U22

0_0402_5%

1 2
1 2

@U22

0_0402_5%

PR634

PC627

2200P_0402_50V7K

1 2

PR615

PR611 setting 1.87K for frequency 450KHz

PR601

@

45.3_0402_1%

+3.3V_RUN

PCH_PWROK(11)

IMVP_VR_ON(37)

I_SYS(36,56)

+5V_ALW

VCC_GT_SENSE(16)

VSS_GT_SENSE(16)

12

12

PC602

PR605

PR604

75_0402_1%

100_0402_1%

PR612

1.91K_0402_1%

1 2
1 2

PR614 0_0402_5%@

1 2

PR616 0_0402_5%@

PR620

@

0_0402_5%

1 2

FCCM_IA(54)
PWM1_IA(54)
PWM2_IA(54)

PH603
470K_0402_5%_B25/50 4700K

1 2

PR647

27.4K_0402_1%

1 2

PC629

2200P_0402_50V7K

1 2

PC636

33P_0402_50V8J

PC639

1500P_0402_50V7K

1 2

1 2

PR648

1.91K_0402_1%

PC651

@

1 2

330P_0402_50V7K

PC654

1 2

0.01UF_0402_25V7K

0.1U_0402_25V6

1 2
1 2
1 2

PU602

1
2
3
4
5
6
7
8
9

10
41

PC625

330P_0402_50V7K

1 2

PR629

86.6K_0402_1%@

1 2

1 2

10K_0402_1%
PR639

3.09K_0402_1%

1 2

1 2

PR645

1 2

PSYS
IMON_B
NTC_B
COMP_B
FB_B
RTN_B
ISUMP_B
ISUMN_B
ISEN1_B
ISEN2_B

AGND

PR635

316_0402_1%

PR61849.9_0402_1%

PR6250_0402_5% @

PR62610_0402_1%

39

40

VR_ENABLE

FCCM_B11PWM1_B12PWM2_B13IMON_A14NTC_A15COMP_A

12

1 2

12

PC653

@

12

1 2

VIDSOUT_B

VIDSCLK_B

VIDALERT_N_B

36

37

38

35

SCLK

ALERT#

VR_HOT#

VR_READY

16

IMON_GT

NTC_GT

COMP_GT

2K_0402_1%

PR650

PC647

680P_0402_50V7K

0.082U_0402_16V7K

PR608

88.7K_0402_1%

1 2

PR611

1.87K_0402_1%

32

33

34

VIN

SDA

VCC

PROG231PROG1

PWM_C

FCCM_C

ISUMN_C

ISUMP_C

RTN_C

FB_C

COMP_C

IMON_C
PWM_A

FCCM_A

FB_A

RTN_A18ISUMP_A19ISUMN_A

17

20

ISL95857AHRTZ-T TQFN 40P PWM

FB_GT

PR657

4.42K_0402_1%

1 2

PR653

@

20M_0402_5%

ISUMP_GT (54)

Local sense put on HW site

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS C ONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

0_0402_5%

1 2

1 2

@

12

0_0402_5%

PC603

PC604

1U_0603_10V6K

0.22U_0603_25V7K

PWM_VSA

30

FCCM_VSA

29
28
27
26

FB_VSA

25

COMP_VSA

24

IMON_VSA

23
22

PWM_GT (54)

21

FCCM_GT (54)

12

PC630

2200P_0402_50V7K

12

PR644

1K_0402_1%

PC642

@

0.033U_0402_16V7K

1 2

PC646

@

0.01U_0402_25V7K

1 2

PR656

11K_0402_1%

1 2

PH605

1 2

10K_0402_5%_B25/50 4250K

12

3

PR603

12

CPU_B+

PR640

PC645

357_0402_1%

12

.1U_0402_16V7K

+5V_ALW

ISUMN_GT (54)

PR619 2.2_0603_5%

1 2

PC611

0.22U_0603_16V7K

1 2

PWM_SA

PR606

@

0_0402_5%

1 2

PWM_VSA

12

PC628

33P 50V J NPO 0402

PC631

12

330P_0402_50V7K

PR651

PC643

@

SA_UGATE

PU614
ISL95808HRZ-TS2378_DFN8_2X2

1

UGATE

2

BOOT

3

PWM
GND4LGATE

TP

9

+5V_ALW

12

PR630

2.49K_0402_1%

12

4700P_0402_25V7K

PR646

1 2

316_0402_1%

12

12

113K_0402_1%

PR652

2K_0402_1%

@

12

PC601

@

2

8

PHASE

7

FCCM

6

VCC

5

@

665_0402_1%

1 2

1 2

PC632
1000P_0402_50V7K

2200P_0402_50V7K

PR649

1 2

1.62K_0402_1%

680P_0402_50V7K

PC685

PR636

12

1U_0402_10V6K

PC640

1 2

PJP603

VCCSA_B+ CPU_B+

1 2

PAD-OPEN1x1m

VCCSA_B+

12

12

PC608

PC612

10U_0603_25V6M

10U_0603_25V6M

4

1

3

2

PQ614
PE642DT_DFN3X3

D1

D1

D1

SA_LGATE

12

PR679

@

0_0402_5%

FCCM_VSA

1 2

PR641

1K_0402_1%

D110D2/S1

S2

S2

S2

6

7

5

G1

9

G2

8

.1U_0402_16V7K

SA_SW

12

0.47UH MMD-05AHNR47MEX2L 10.5A

12

@EMC@

PR627

4.7_1206_5%

SA_SNUBSA_SNUB

12

PC622

680P_0603_50V7K

@EMC@

12

PC637

0.033U 25V K X7R 0402

PC644

1 2

PC650

1 2

@

0.082U_0402_16V7K

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

PWR_VCORE_ISL95857

PWR_VCORE_ISL95857

PWR_VCORE_ISL95857

PL614

4
3

12

PR624

3.65K_0603_1%

ISUMP_VSA

PC633

4700P 50V K X7R 0402

PC649

0.01UF_0402_25V7K

330P_0402_50V7K

1

1 2

@

PC652

1 2

1

+VCC_SA

2

ISUMN_VSA

ISUMP_VSA

12

PR642

2.61K_0402_1%

PR643

12

10KB_0402_5%

1 2

11K_0402_1%

PH604

ISUMN_VSA

VSA_SEN- (17)

VSA_SEN+ (17)

1.0

1.0

54 59Tuesday, November 14, 2017

54 59Tuesday, November 14, 2017

54 59Tuesday, November 14, 2017

1.0

5

smd.db-x7.ru

4

3

2

1

AR U42

+PWR_SRC

PJP601

PC697

@

100U_D2_20VM_R55M

1

+

2

1 2

PAD-OPEN 4x4m

PL602

@EMC@

1 2

9A Z80 10M 1812_2P

12

12

12

12

PC691

PC689

PC690

1000P_0402_50V7K

@EMC@

@EMC@

PC692

1U_0402_25V6K

1000P_0402_50V7K

1U_0402_25V6K

@EMC@

@EMC@

CPU_B+

RF@

RF@

D D

12

PC682

10U_0603_16VAK

12

12

PC657

PC656

10U_0603_16VAK

10U_0603_16VAK

RF@

12

12

PC658

10U_0603_16VAK

PC693

PC659

0.1U_0402_25V6K~D

RF@

RF@

12

12

PC660

PC694

2200P_0402_50V7K

0.1U_0402_25V6K~D

@RF@

12

12

PC695

PC696

82P_0402_50V8J

2200P_0402_50V7K

1

+

12

PC606

2

82P_0402_50V8J

100U_D2_20VM_R55M

RF demand

PU610

PGND10SW
VIN9SW

PC671

1 2

1 2

PR672

8

VIN

7

PHASE

6

N/C

5

BOOT

4

AGND

3

VCC

2

FCCM

1

PWM

FDMF3035_ PQFN31_5X5

8
7

6
5

4
3

2
1

PC655

0.1U_0402_25V6

VCC_IA1

PC673

@U42

PC1335

1U_0402_10V6K

PR659

@

0_0402_ 5%

1 2

PR687

@

0_0402_ 5%

1 2

12

10U_0603_16VAK

PC688

0.1U_0402_25V6

@U42

PR691

0.22U_06 03_16V7K

1 2

3.9_0603_1%

VCC_IA2

12

PC677

@U42

1U_0402_10V6K

@U42

0_0402_ 5%

1 2

@U42

0_0402_ 5%

1 2

1 2

PR660

@U42

0.22U_06 03_16V7K

@U42

3.9_0603_1%

PR671

PR692

12

PC686

PR688

1_0603_ 5%

1 2

C C

B B

+5V_ALW

12

PC683

10U_0603_16VAK

@U42

+5V_ALW

A A

12

FCCM_IA(53 ,54)

PWM1_I A(53)

12

12

PC684

PC672

10U_0603_16VAK

10U_0603_16VAK

@U42

@U42

12

@U42

1_0603_ 5%

1 2

FCCM_IA(53 ,54)

PWM2_I A(53)

11
12

13

GL

14

PGND

15

PVCC

16

N/C

17

N/C

19

GL

18

AGND

PU613

@U42

PGND10SW
VIN9SW

VIN

GL

PHASE

PGND

N/C

PVCC

BOOT

N/C

AGND

N/C

VCC
FCCM

GL

PWM

AGND

FDMF3035_ PQFN31_5X5

+5V_ALW

12

12

PR686

PC661

@

10K_0402_1%

1U_0402_10V6K

11
12

13
14

15
16

17

19
18

12

+5V_ALW

PR689

@

10K_0402_1%

12

PC1336

@U42

IA_SW1

12

PR663

RF@

4.7_1206_5%

IA_SNUB1

12

PC662

RF@

PR676

4.7_1206_5%

@EMC@

1U_0402_10V6K

PC678

680P_0603_50V7K

@EMC@

0.15UH_MMD-06BDER15MEM1L_27A_20%

PR667

3.65K_0603_1%

1 2

ISEN1_IA(53)

IA2N

(53,54)

ISUMP_IA

680P_0603_50V7K

IA_SW2

12

@U42

3.65K_0603_1%

1 2

ISEN2_IA(53)

IA_SNUB2

12

ISUMP_IA

4
3

IA1P

@U42

100K_06 03_1%

1 2

@

100K_04 02_1%

0.15UH_MMD-06BDER15MEM1L_27A_20%

PR674

IA1N

(53,54)

+VCC_CORE

@U42

PR682 SOLDER_PREFORMS _0603

112

@U22

+VCC_GT

+VCC_CORE +VCC_GT_+VCC_CORE

For KBL U42 : Pop PR682 and P R684
For KBL U22 : Pop PR683

PL610

1
2

IA1N

12

PR668

PR670

12

ISUMN_IA

PL613

@U42

1

4
3

2

IA2P

PR675

@U42

100K_06 03_1%

1 2

PR677

@

1 2

100K_04 02_1%

PR683

PR684

+VCC_CORE

PR666
10_0402 _1%

(53,54)

IA2N

12

@U42

10_0402 _1%

ISUMN_IA

SOLDER_P REFORMS_0603

112

@U42

SOLDER_P REFORMS_0603

112

+VCC_CORE

PR673

(53,54)

2

2

2

+VCC_GT_+VCC_CORE

+5V_ALW

12

PC675

10U_0603_16VAK

PR1300

1_0603_ 5%

1 2

PC626 @U42AR

0.1U_0402_25V6

PR638 @U42AR

453_0402_1%

nAR U42

PC626 @U42NAR

0.1U_0402_25V6

PR638 @U42NAR

453_0402_1%

nAR U22

PC626 @U22

0.047U_0402_25V7K

PR638 @U22

360_0402_1%

12

PC674

PC664

10U_0603_16VAK

10U_0603_16VAK

12

VCC_GT

12

FCCM_GT(53)

PWM_GT(53)

12

PC687

0.1U_0402_25V6

PC669

1U_0402_10V6K

12

PC665

10U_0603_16VAK

PR1299

@

0_0402_ 5%

1 2

PR664

@

0_0402_ 5%

1 2

PR613 @U42AR

93.1K_0402_1%

PR622 @U42AR

3.09K_0402_1%

PR613 @U42NAR

93.1K_0402_1%

PR622 @U42NAR

3.09K_0402_1%

PR613 @U22

88.7K_0402_1%

PR622 @U22

1.5K_0402_1%

GPU_B+

0.22U_06 03_16V7K

1 2

3.9_0603_1%

PC663

1 2

PR665

PR621 @U42AR

1K_0402_1%

PC616 @U42AR

68P_0402_50V8J

PR621 @U42NAR

1K_0402_1%

PC616 @U42NAR

68P_0402_50V8J

PR621 @U22

316_0402_1%

PC616 @U22

33P_0402_50V8J

PU612

PGND10SW
VIN9SW

8

VIN

7

PHASE

6

N/C

5

BOOT

4

AGND

3

VCC

2

FCCM

1

PWM

FDMF3035_ PQFN31_5X5

PC617 @U42AR

220P_0402_50V7K

PR636 @U42AR

732_0402_1%

PC617 @U42NAR

220P_0402_50V7K

PR636 @U42NAR

732_0402_1%

PC617 @U22

1200P_0402_50V7K

PR636 @U22

732_0402_1%

11
12

13

GL

14

PGND

15

PVCC

16

N/C

17

N/C

19

GL

18

AGND

PC624 @U42AR

0.01UF_0402_25V7K

PC646 @U42AR

0.047U_0402_25V7K

PC624 @U42NAR

0.022U_0402_16V7K

PC646 @U42NAR

0.047U_0402_25V7K

PC624 @U22

0.022U_0402_16V7K

PC646 @U22

0.047U_0402_25V7K

PJP602

PAD-OPEN 1x2m~D

GT_SW

12

PR1298

@

21

@EMC@

4.7_1206_5%

1 2

+5V_ALW

12

10K_0402_1%

PC642 @U42AR

0.022U_0402_16V7K

PR629 @U42AR

86.6K_0402_1%

PC642 @U42NAR

0.022U_0402_16V7K

PR629 @U42NAR

88.7K_0402_1%

PC642 @U22

0.022U_0402_16V7K

PR629 @U22

88.7K_0402_1%

CPU_B+GPU_B+

PR669

GT_SNUB

0.15UH_MMD-06BDER15MEM1L_27A_20%

4
3

12

PR661

3.65K_0603_1%

PC1337

1U_0402_10V6K

ISUMP_GT

PC670

@EMC@

680P_06 03_50V7K

1 2

PL612

1
2

(53)

PR651 @U42AR

113K_0402_1%

PR617 @U42AR

4.3K_0402_1%

PR651 @U42NAR

105K_0402_1%

PR617 @U42NAR

4.3K_0402_1%

PR651 @U22

105K_0402_1%

PR617 @U22

3.4K_0402_1%

+VCC_GT

(53)

ISUMN_GT

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DELL CONFIDENTIAL/PROPRIETARY

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

Compal Electronics, Inc.

PWR_VCORE_ISL95857A

PWR_VCORE_ISL95857A

PWR_VCORE_ISL95857A

1

55 59Tuesday, November 14, 2017

55 59Tuesday, November 14, 2017

55 59Tuesday, November 14, 2017

1.0

1.0

1.0

4 4

smd.db-x7.ru

3 3

2 2

1 1

VCC_GT_+VCC_CORE Place on CPU

22U_0603 * 6 pcs + 1U_0201 * 5 pcs

A

PC1322

22U_0603_6.3V6M

PC1323

22U_0603_6.3V6M

PC1324

22U_0603_6.3V6M

PC1325

22U_0603_6.3V6M

PC1326

22U_0603_6.3V6M

B

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

C

PC1327

22U_0603_6.3V6M

PC1330

1U_0201_6.3V6M

PC1331

1U_0201_6.3V6M

PC1332

1U_0201_6.3V6M

PC1333

1U_0201_6.3V6M

PC1334

1U_0201_6.3V6M

VCC_SA Place on CPU

22U_0603 * 12 pcs + 1U_0201*7 pcs

+VCC_GT_+VCC_CORE

PC1127

220U_D7_2VM_R4.5M

220U_D7_2VM_R4.5M

12

12

220U_D7_2VM_R4.5M

12

12

12

12

12

12

12

12

12

@U42

2

2

2

PC1062

PC1321

1

+

1

+

1

+

12

PC1099

1U_0201_6.3V6M

12

PC1095

1U_0201_6.3V6M

12

PC1094

1U_0201_6.3V6M

12

PC1096

1U_0201_6.3V6M

12

PC1090

1U_0201_6.3V6M

12

PC1093

1U_0201_6.3V6M

12

PC1091

1U_0201_6.3V6M

12

PC1097

1U_0201_6.3V6M

12

PC1092

1U_0201_6.3V6M

12

PC1098

1U_0201_6.3V6M

12

PC1050

1U_0201_6.3V6M

12

PC1051

1U_0201_6.3V6M

12

PC1052

1U_0201_6.3V6M

12

PC1053

1U_0201_6.3V6M

12

PC1054

1U_0201_6.3V6M

12

PC1126

1U_0201_6.3V6M

12

PC1083

1U_0201_6.3V6M

12

PC1030

1U_0201_6.3V6M

12

PC1031

1U_0201_6.3V6M

12

PC1032

1U_0201_6.3V6M

12

PC1033

1U_0201_6.3V6M

12

PC1034

1U_0201_6.3V6M

12

PC1035

1U_0201_6.3V6M

12

PC1036

1U_0201_6.3V6M

12

PC1037

1U_0201_6.3V6M

12

PC1038

1U_0201_6.3V6M

12

PC1039

1U_0201_6.3V6M

12

PC1084

1U_0201_6.3V6M

12

PC1086

1U_0201_6.3V6M

12

PC1085

1U_0201_6.3V6M

12

PC1088

1U_0201_6.3V6M

12

PC1087

1U_0201_6.3V6M

12

PC1089

1U_0201_6.3V6M

PC1081

22U_0603_6.3V6M

PC1080

22U_0603_6.3V6M

PC1082

22U_0603_6.3V6M

PC1067

22U_0603_6.3V6M

PC1072

22U_0603_6.3V6M

PC1069

22U_0603_6.3V6M

PC1074

22U_0603_6.3V6M

PC1070

22U_0603_6.3V6M

PC1061

22U_0603_6.3V6M

PC1071

22U_0603_6.3V6M

PC1066

22U_0603_6.3V6M

PC1073

22U_0603_6.3V6M

PC1068

22U_0603_6.3V6M

PC1075

22U_0603_6.3V6M

PC1064

22U_0603_6.3V6M

PC1065

22U_0603_6.3V6M

PC1076

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

22U_0603_6.3V6M

PC1078

22U_0603_6.3V6M

PC1077

22U_0603_6.3V6M

PC1079

22U_0603_6.3V6M

PC1001

22U_0603_6.3V6M

PC1002

22U_0603_6.3V6M

PC1003

22U_0603_6.3V6M

PC1004

22U_0603_6.3V6M

PC1005

22U_0603_6.3V6M

PC1006

22U_0603_6.3V6M

PC1007

22U_0603_6.3V6M

PC1008

22U_0603_6.3V6M

PC1009

22U_0603_6.3V6M

PC1010

22U_0603_6.3V6M

PC1011

22U_0603_6.3V6M

PC1012

22U_0603_6.3V6M

PC1013

22U_0603_6.3V6M

+VCC_CORE +VCC_GT

A

VCC_CORE Place on CPU

22U_0603 * 33 pcs +1U_0201*33 pcs

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

12

+220u_D7*3 pcs

B

C

PC1128

220U_D7_2VM_R4.5M

+VCC_SA

12

D

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet of

Title

Size Document Number Rev

Date: Sheet of

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

PROCESSOR DECOUPLING

PROCESSOR DECOUPLING

PROCESSOR DECOUPLING

E

56 59Tuesday, November 14, 2017

56 59Tuesday, November 14, 2017

56 59Tuesday, November 14, 2017

PC1153

1U_0201_6.3V6M

12

PC1147

1U_0201_6.3V6M

12

PC1148

1U_0201_6.3V6M

12

PC1149

1U_0201_6.3V6M

12

PC1150

1U_0201_6.3V6M

12

PC1151

1U_0201_6.3V6M

12

PC1152

1U_0201_6.3V6M

12

PC1057

22U_0603_6.3V6M

12

PC1058

22U_0603_6.3V6M

12

PC1059

22U_0603_6.3V6M

12

PC1060

22U_0603_6.3V6M

12

PC1139

22U_0603_6.3V6M

12

PC1140

22U_0603_6.3V6M

12

PC1141

22U_0603_6.3V6M

12

PC1142

22U_0603_6.3V6M

12

PC1143

22U_0603_6.3V6M

12

PC1144

22U_0603_6.3V6M

12

PC1145

22U_0603_6.3V6M

12

PC1146

22U_0603_6.3V6M

220U_D7_2VM_R4.5M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

@

@

@

@

@

@

@

2

PC1063

2

PC1181

PC1180

PC1177

PC1179

PC1176

PC1178

PC1175

1

+

1

+

12

12

12

12

12

12

12

12

PC1040

1U_0201_6.3V6M

12

PC1041

1U_0201_6.3V6M

12

PC1042

1U_0201_6.3V6M

12

PC1043

1U_0201_6.3V6M

12

PC1044

1U_0201_6.3V6M

12

PC1045

1U_0201_6.3V6M

12

PC1046

1U_0201_6.3V6M

12

PC1047

1U_0201_6.3V6M

12

PC1048

1U_0201_6.3V6M

12

PC1049

1U_0201_6.3V6M

12

PC1055

1U_0201_6.3V6M

12

PC1056

1U_0201_6.3V6M

12

PC1328

1U_0201_6.3V6M

12

PC1329

1U_0201_6.3V6M

PC1133

22U_0603_6.3V6M

PC1137

22U_0603_6.3V6M

PC1129

22U_0603_6.3V6M

PC1132

22U_0603_6.3V6M

PC1136

22U_0603_6.3V6M

PC1134

22U_0603_6.3V6M

12

12

12

12

12

12

PC1014

22U_0603_6.3V6M

PC1015

22U_0603_6.3V6M

PC1016

22U_0603_6.3V6M

PC1017

22U_0603_6.3V6M

PC1018

22U_0603_6.3V6M

PC1019

22U_0603_6.3V6M

PC1020

22U_0603_6.3V6M

PC1021

22U_0603_6.3V6M

PC1022

22U_0603_6.3V6M

PC1023

22U_0603_6.3V6M

PC1024

22U_0603_6.3V6M

PC1025

22U_0603_6.3V6M

PC1026

22U_0603_6.3V6M

12

12

12

12

12

12

12

12

12

12

12

12

12

VCC_GT Place on CPU (U22)

22U_0603 * 19 pcs + 1U_0201 * 14 pcs

+220u_D7*2 pcs

D

E

1.0

1.0

1.0

A

smd.db-x7.ru

+SDC_IN

1 1

PC926

DCIN_ISL9538

VDD_ISL9538
ACIN_ISL9 538

OTGEN/CMIN

ACOK_ISL 9538

PC938

10P_040 2_50V8J

1 2

PR934

@

0_0402_5%

PC944

.012U 16V K X7R 0402

@

0_0402_ 5%

1 2

12

12

1U 25V K X5R 0402

ADP_ISL9 538

17
18
19
20
21
22
23
24

PR933

100K_04 02_1%

1 2

PR951

COMP_ISL9538

PC943

@

Close to EC ADP_I pin

PC955

PROCHOT#_IS L9538(57)

+SDC_IN

12

PROCHOT#(12,36 ,53)

PR931

100K_0402_1%

1 2

12

12

PD901

PD903

2 1

RB520SM-3 0T2R_EMD2-2
PD904

2 1

RB520SM-3 0T2R_EMD2-2

PC931
1U_0603_25V6

1 2

1U_0402_6.3V6K

PQ909

13

D

2

154K_04 02_1%

G

12

S

L2N7002WT1G 1N SC-70-3

PR927

1M_0402_1%

12

PC933

PR925

1 2

PR916
1_0805_ 5%

12

12

0.1U 25V K X5R 0402

PR918
100K_04 02_1%

1 2

PBAT_CHARGER_SMBDAT(36,47)
PBAT_CHARGER_SMBCLK(36,47)

PBAT_PRES #(36,47)

+PWR_SRC

SDMK0340 L-7-F_SOD323 -2~D

TBTA_DC_SS

TBTA_DC_SS

TBTA_DC_SSTBTA_DC_SS

2 2

TBTB_DC_SS

TBTB_DC_SS

TBTB_DC_SSTBTB_DC_SS

ACAV_IN1

AC_DIS(36)

3 3

PR944
442K_04 02_1%

ACIN_ISL9 538

PR945
100K_04 02_5%

PR960

@

0_0402_ 5%

1 2

100K_04 02_1%

PR943
0_0603_ 5%

1 2

@

PR919

0_0402_ 5%

1 2

PR920

@

1 2

PR922

@

1 2

PR926 0_04 02_5%@

1 2

PR928

@

0_0402_ 5%

1 2

PR930

@

1 2

0_0402_ 5%
0_0402_ 5%

PROCHOT#_IS L9538

+3.3V_ALW

CMOUT(57)

4 4

PR948 @U22

16.5K_0402_1%

PR948 @U42

11.8K_0402_1%

A

PR901

0.01_1206_1%

1
2

12

PR909
2_0603_ 1%

PC925

4.7U 6.3V M X5R 0402

CSIP_ISL9538 CSIN_ISL 9538

1 2

12

CSIP_ISL9538

15

16

ADP

CSIP
DCIN
VDD
ACIN
OTGEN/CMIN
SDA
SCL
PROCHOT#
ACOK

BATGONE

OTGPG/CMOUT26PROG27AMON/BMON29PSYS30VBAT

25

12

12

PR947

@

0_0402_5%

560P_0402_50V7K

I_BATT

I_BATT

(36)

+PWR_SRC_AC

4
3

12

PR910
2_0603_ 1%

PC930

0.22U_06 03_25V7K

1 2

PR914

4.7_0603_5%

1 2

BOOT1_ISL9538

CSIN_ISL9538

11

12

13

14

CSIN

BOOT1

ASGATE

CMOP

28

12

PR932

105K_0402_1%

12

12

PC947
PR935

@

0_0402_5%

I_ADP

I_ADP

(36)

B

EMC@

1UH_PCMB0 51H-1R0MS_8A _20%

1 2

@

1 2

PAD-OPEN 4x4m

12

PD906

SMF4L22A SOD123FL-2

12

PC927

LG1_ISL9538

UG1_ISL9538

LX1_ISL9538

10

9

33

PAD

LGATE1

PHASE1

UGATE1

VDDP
LGATE2
PHASE2
UGATE2

BOOT2

VSYS

CSOP

CSON

BGATE

31

32

VBAT1_ISL9538

BGATE_ISL9538

12

12

PR936

0_0402_5%

@

0.1U_0402_25V6

I_SYS

(36,53)

PC950

@

0.1U_040 2_25V6

B

PL901

PJP901

12

PC902

0.1U_0402_25V6

@EMC@

1U 25V K X5R 0402

PR915

4.7_0603_5%

VDD_ISL9538

1 2

PU901
ISL9538HRTZ-T TQFN 32P PW M

VDDP_ISL9538

8

LG2_ISL9538

7

LX2_ISL9538

6

UG2_ISL9 538

5

BOOT2_ISL 9538

4
3
2
1

PR948

@

16.5K_0402_1%

1 2

CSOP_ISL 9538
CSON_ISL9538

PC934

0.22U_06 03_25V7K

PR940

100_040 2_5%

12

PC903

PC911

2200P_0402_50V7K

@EMC@

12

PC932
1U_0402_6.3V6K

PR921

4.7_0603_5%

12

PR929

@

0_0402_ 5%

1 2

1 2

PC939 0.1U_0402_25V6@

PC945

1U 25V K X5R 0402

+PBATT

12

C

+CHARGER_SRC

+PWR_SRC

1

12

12

12

PC904

10U_0603_25V6M

10U_0603_25V6M

12

12

PC905

PC906

10U_0603_25V6M

10U_0603_25V6M

UG1_ISL9 538 LG1_ISL 9538

1

LX1_ISL9538

G1

2

S1/D2

3

D1

4

D1

PQ905
AOE6936 _DFN5X6E8-10

+PWR_SRC

PC942

@

1U 25V K X5R 0402

1 2

PR937
1_0603_ 1%

1 2

PR938
1_0603_ 1%

1 2

1 2

PC946

0.22U_04 02_25V6K

1 2

AC1_DISC#(25,57)

AC2_DISC#(26,57)

+

PC909

2

@

15U_B2_25VM_R100M

PC951

9

8

G2

D1

7

D2/S1

6

D2/S1

5

D2/S1

S2

10

PR939

@

0_0402_ 5%

1 2

PR941

@

0_0402_ 5%

1 2

BAT54CW-7-F SOT-323 DII

12

12

PC952

10U_0603_25V6M

10U_0603_25V6M

LG2_ISL9538 UG 2_ISL9538

PL902

1UH_PCMB1 02T-1R0MS_10.8A_20%

1 2

LX1_ISL9538

12

SNUB_CHG1

12

3

2

PD905

PR923

EMC@

PC940

EMC@

LX2_ISL9538

12

PR924

4.7_1206_5%

4.7_1206_5%

EMC@

SNUB_CHG2

12

PC941

680P_0603_50V7K

680P_0603_50V7K

EMC@

1

12

PR961

@

100K_0402_1%

8
7
6
5

G2
D2/S1
D2/S1
D2/S1

ACAV_IN1

9

D1

S2

10

1 2

DELL CONFIDENTIAL/PROPRIETARY

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

PC913

10U_0603_16VAK

PC928

0.1U_0402_25V6

@EMC@

1

G1

LX2_ISL9538

2

S1/D2

3

D1

4

D1

PQ904
AOE6936 _DFN5X6E8-10

PR950

@

0_0402_ 5%

PC949

0.1U_040 2_10V7K

1 2

1

PR942

@

0_0402_ 5%

2

1 2

12

12

12

PC915

PC914

12

PC929

@EMC@

PC916

10U_0603_16VAK

10U_0603_16VAK

2200P_0402_50V7K

10U_0603_16VAK

12

PC986

1000P_0402_50V7K

@EMC@

+PWR_SRC

PR917

0.005_1206_1%

1
2

+3.3V_VDD_PIC

5

PR946

@

0_0402_ 5%

P

IN1

1 2

4

O

IN2

G

PU903

3

MC74VHC1G 08DFT2G SC70 5P AND

D

1

12

12

12

PC917

10U_0603_16VAK

12

PC987

1000P_0402_50V7K

@EMC@

12

PC918

10U_0603_16VAK

EMI demand

12

PC988

1U_0402_25V6K

@EMC@

12

12

PC920

PC919

10U_0603_16VAK

10U_0603_16VAK

12

PC989

1U_0402_25V6K

@EMC@

+

PC990

2

@

15U_B2_25VM_R100M

RF demand

12

12

12

PC957

PC956

0.1U_0402_25V6

0.1U_0402_25V6

RF@

RF@

12

12

PC959

PC958

0.1U_0402_25V6

82P_0402_50V8J

RF@

RF@

+VCHGR

4
3

12

12

PC936

PC935

10U_0603_16VAK

10U_0603_16VAK

ACAV_IN (36)

100K_0402_1%

12

PR953

12

PC960

PC961

82P_0402_50V8J

82P_0402_50V8J

RF@

RF@

PQ906
EMZB08P0 3V_DFN8-5

1
2
3 5

4

PC937

BGATE_ISL9538

1 2

@

4700P_0402_25V7K

For IT8010 voltage leakage issue

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

Compal Electronics, Inc.

PWR_charger_ISL9538

PWR_charger_ISL9538

PWR_charger_ISL9538

D

12

12

PC962

PC963

RF@

RF@

2200P_0402_50V7K

2200P_0402_50V7K

+PBATT

1.0

1.0

57 59Tuesday, November 14, 2 017

57 59Tuesday, November 14, 2 017

57 59Tuesday, November 14, 2 017

1.0

5

smd.db-x7.ru

PJP120 1

21

PAD-OPE N 1x2m~D

12

47K_04 02_1%

12

(From EC)

LPSA_PROTECT#

12

PR1254
47K_04 02_1%

12

(From EC)

LPSB_P ROTECT#

PR1217

PR1223

@

0_0402 _5%

1 2

PR1259

@

0_0402 _5%

1 2

S5

PQ1200

@

EMZB08P 03V_DFN8-5

12

PC1212

0.1U 25V M X5R 0402

PT1

@

PAD~D

@

12

PC1224

0.1U 25V K X5R 0402

PT2

@

PAD~D

EN_PD_HV _2 (26,57 )

4

PC1204

@

+3.3V_VD D_PIC

PR1213

@

1 2

100K_0402_5%

34

5

PQ1201 B

DMN65D8L DW-7_SOT3 63-6

EN_PD_HV _1 (25,57)

PAD-OPE N 1x2m~D

S6

PQ1210

@

EMZB08P 03V_DFN8-5

+3.3V_VD D_PIC

PR1249

1 2

100K_0402_5%

34

5

DMN65D8L DW-7_SOT3 63-6

1
2
35

1 2

1500P_0402_50V7K

2

2

PQ1217 B

PJP120 2

PL1203

EMC@

FBMA-L11 -201209_08 05

EMC@

PC1283

EMC@

12

PC1284

100P_0402_50V8J

FBMA-L11 -201209_08 05

12

PC1201

100P_0402_50V8J

@EMC@

1 2

EMC@

1 2

12

0.1U_0402_25V6

+TBTA_V BUS_1

PR1215

499K_0402_1%

PR1225

200K_0402_1%

FBMA-L11 -201209_08 05

FBMA-L11 -201209_08 05

PC1213

0.1U_0402_25V6

@EMC@

+TBTB_V BUS_1

PR1252

499K_0402_1%

PR1261

200K_0402_1%

+TBTA_VBUS_1

PL1201

12

12

12

PR1201

PC1203

PC1202

@

1M_0402_1%

100P_0402_50V8J

1000P_0402_50V7K

EMC@

@EMC@

PC1202 can't over 1000P

+3.3V_VD D_PIC

S5 OVP

PD1201

SDMK034 0L-7-F_SOD3 23-2

12

12

12

EMC@

EMC@

12

12

12

1 2

1 2

PC1221

1 2

PR1218

1.8M_040 2_1%

1 2

PR1216

221K_0402_1%

3
2

12

12

PR1227

PL1204

PL1202

+3.3V_VD D_PIC

PR1253

PR1262

200K_0402_1%

D

S

PQ1208

L2N7002WT1G 1N SC-70-3)

12

PC1214

1000P_0402_50V7K

EMC@

SDMK034 0L-7-F_SOD3 23-2

12

221K_0402_1%

12

200K_0402_1%

D

S

PQ1219

L2N7002WT1G 1N SC-70-3)

13

PC1215

@EMC@

13

PC1210

G

12

100P_0402_50V8J

1 2

PC1222

G

12

100P_0402_50V8J

2

12

PR1234

@

S6 OVP

PD1206

PR1256

1.8M_040 2_1%

1 2

12

100P_0402_50V8J

2

12

10K_04 02_5%

1M_0402_1%

5
6

10K_04 02_5%

PC1209

10U 10V M X5R 0402

PC1214 can't over 1000P

12

10U 10V M X5R 0402

12

PR1231

PR1270

+

-

+

-

8

P

G

4

8

P

G

4

PU1201A
LM393DG KR_VSSOP8

1

O

PR1230

@

0_0402 _5%

1 2

PR1232

@

0_0402 _5%

1 2

PU1201B
LM393DG KR_VSSOP8

7

O

@

0_0402 _5%

1 2

@

0_0402 _5%

1 2

PR1266

PR1269

EN_PD_HV _2(26,57)

PC1211

2.2U 25V M X5R 0402

EN_PD_HV _1(25,57)

PC1223

2.2U 25V M X5R 0402

+TBTA_VBUS

D D

C C

+TBTB_VBUS +TBTB_VBUS_1

B B

A A

5

12

PR1206

1M_0402_5%

@

PR1211

@

100K_0 402_5%

1 2

61

PQ1201 A

DMN65D8L DW-7_SOT3 63-6

PR1295

@

0_0402 _5%

1 2

21

1
2
35

4

PC1216

1 2

@

1500P_0402_50V7K

PR1242

@

100K_0 402_5%

1 2

61

PQ1217 A

DMN65D8L DW-7_SOT3 63-6

PR1296

@

0_0402 _5%

1 2

12

12

4

+AC1_IN

PR1287

@

10K_04 02_5%

S3_OVP

PR1236

1M_0402_5%

@

S1_OVP

4

12

10K_04 02_5%

@

PR1288

3

S2

PD1202

@

34

PQ1221 B
DMN65D8L DW-7_SOT3 63-6

5

PR1268

100K_0 402_5%

PQ1223 B
DMN65D8L DW-7_SOT3 63-6

1 2

@

PR1290

0_0402 _5%

2 1

PQ1203
EMZB08P 03V_DFN8-5

+3.3V_AL W

+3.3V_AL W+3 .3V_ALW

1 2

61

2

B2100A F-13 SMAF-2

1
2
35

4

PR1212

49.9K_0 402_1%

1 2

PQ1207 B

34

DMN65D8L DW-7_SOT3 63-6

5

S4

PD1205

2 1

B2100A F-13 SMAF-2
PQ1212
EMZB08P 03V_DFN8-5

4

PR1246

49.9K_0 402_1%

1 2

34

@

PR1264
100K_0 402_5%

1 2

AC_DIS C# (36,57)

61

2

PQ1221 A
DMN65D8L DW-7_SOT3 63-6

PQ1223 A
DMN65D8L DW-7_SOT3 63-6

1
2
35

PQ1216 B
DMN65D8L DW-7_SOT3 63-6

5

1 2

S1

PQ1202

EMZB08P 03V_DFN8-5

1
2

PC1208

0.1U_0402_25V6

12

12

PR1220

3 5

PC1205

0.47U_06 03_25V6K

1 2

100K_0402_5%

2

12

PR1277

61

2

PQ1224A

PQ1224B

DMN65D8LDW-7_SOT363-6

1 2
1 2

PQ1209

L2N7002 WT1G 1N SC-7 0-3

D

S

13

G

2
12

PR1233

@

0_0402 _5%

DMN65D8LDW-7_SOT363-6

PR1219

@

0_0402 _5%

PR1222

@

0_0402 _5%

300K_0 402_5%

PR1279

100K_0 402_5%

+3.3V_VD D_PIC

PR1228

1 2

100K_0402_5%

+3.3V_VD D_PIC

2

12

@

PR1284

12

0_0402 _5%

+3.3V_VDD_PIC

PC1207

0.01U_04 02_25V7K

1 2

1
2

S

G

PQ1225

D

1 3

AO3409 P-CHANNEL SOT-23

5

P

IN1

4

O

IN2

G

3

PU1202
MC74VHC1 G08DFT2G S C70 5P AND

12

PR1203

499K_0402_1%

PR1214

@

0_0402 _5%

1 2

S1_OVP

+3.3V_VD D_PIC

12

PR1278
100K_0 402_5%

EN_PD_HV _1#

34

5

EN_PD_HV _1(25,57)

EN_PD_HV _1(25,57) VBUS1_E COK_R (36,57)

PR1285

1M_0402 _5%

1 2

PR1226

@

0_0402 _5%

1 2

DCIN1_E N_R(36)

12

PR1229

100K_0402_5%

+3.3V_AL W

S3

1

12

PC1217

0.47U_06 03_25V6K

12

PC1220

0.1U_0402_25V6

100K_0 402_5%

1 2

@

PR1289

0_0402 _5%

PR1267

EN_PD_HV _2(26,57)

AC2_DI SC#(26,56)

PR1250

1 2

100K_0402_5%

+3.3V_AL W+3.3V_AL W

2

2
3 5

1 2

61

PQ1220 A
DMN65D8L DW-7_SOT3 63-6

+AC2_IN

12

PR1280

300K_0 402_5%

PR1251

@

0_0402 _5%

1 2

12

EN_PD_HV _2#

PR1281
100K_0 402_5%

5

PR1286
1M_0402 _5%

12

PR1260

100K_0402_5%

+3.3V_AL W

S3_OVP

61

2

34

PQ1226B

DMN65D8LDW-7_SOT363-6

1 2

PQ1218

L2N7002 WT1G 1N SC-7 0-3

D

S

13

G

2

12

PR1265

@

0_0402 _5%

PQ1226A

DMN65D8LDW-7_SOT363-6

@

0_0402 _5%

1 2
1 2

@

0_0402 _5%

EN_PD_HV _1(25,57)

AC1_DI SC#(25,56)

PR1282

100K_0 402_5%

PR1245

PR1247

PR1258

+3.3V_VD D_PIC

12

+3.3V_VD D_PIC

12

@

PR1283

0_0402 _5%

0.01U_04 02_25V7K

PU1203
MC74VHC1 G08DFT2G S C70 5P AND

1 2

100K_0402_5%

@

0_0402 _5%

1 2

@

0_0402 _5%

1 2

+3.3V_VD D_PIC

EN_PD_HV _2(26,57)

EN_PD_HV _2(26,57)

DCIN2_E N_R(36)

G

2

PC1219

1 2

PR1293

PR1273

S

PQ1227

D

1 3

AO3409 P-CHANNEL SOT-23

+3.3V_VDD_PIC

5

1

P

IN1

2

IN2

G

3

PR1271

100K_0 402_5%

PR1237

499K_0402_1%

4

O

5

12

PR1248

@

0_0402 _5%

1 2

VBUS2_E COK_R(36 ,57)

VBUS1_E COK_R(36 ,57)

1 2

34

PQ1220 B
DMN65D8L DW-7_SOT3 63-6

3

4

PR1209

49.9K_0 402_1%

1 2

61

PQ1207 A
DMN65D8L DW-7_SOT3 63-6

PQ1211
EMZB08P 03V_DFN8-5

4

PR1244

49.9K_0 402_1%

1 2

61

PQ1216 A
DMN65D8L DW-7_SOT3 63-6

2

PR1275

@

0_0402 _5%

1 2

PR1276

@

0_0402 _5%

1 2

@

PR1294

0_0402 _5%

1 2

PR1274

@

0_0402 _5%

1 2

TBTA_DC_SS

TBTB_DC_SS

+3.3V_AL W

PR1263
100K_0 402_5%

1 2

PR1272

100K_0 402_5%

5

1 2

34

2

+SDC_IN

12

PR1208

@

0_0402 _5%

+3.3V_VD D_PIC

PR1205

100K_0 402_5%

PQ1205

L2N7002WT1G 1N SC-70-3

PR1224
100K_0 402_5%

1 2

12

@

0_0402 _5%

1 2

PC1206

PR1221

PR1202

12

PR1204

499K_0402_1%

0.022U_0402_25V7K

300K_0 402_5%

S

1 2

G

2

PQ1204

D

1 3

PR1207

AO3409 P-CHANNEL SOT-23

100K_0 402_5%

1 2
13

D

2

G

S

PQ1206

L2N7002WT1G 1N SC-70-3

+SDC_IN

12

@

0_0402 _5%

CMOUT (56)

PR1241

+3.3V_VD D_PIC

PR1239

100K_0 402_5%

PR1257
100K_0 402_5%

1 2

+3.3V_AL W

PC1285

@

1500P_0402_50V7K

12

@

0_0402 _5%

1 2

1 2

34

PC1218

PR1255

12

PR1238

499K_0402_1%

0.022U_0402_25V7K

PR1291
100K_0 402_5%

PR1292

@

0_0402 _5%

1 2

PQ1222 B
DMN65D8L DW-7_SOT3 63-6

5

S

G

2

PQ1213

D

1 3

AO3409 P-CHANNEL SOT-23

PQ1215

VBUS2_E COK_R (36,57)

2

G

1 2

1 2
13

D

S

L2N7002WT1G 1N SC-70-3

2

13

D

S

PR1235
300K_0 402_5%

PR1240
100K_0 402_5%

2

G

61

PQ1222 A
DMN65D8L DW-7_SOT3 63-6

PQ1228

L2N7002WT1G 1N SC-70-3

PROCHOT #_ISL9538 (56)

DELL CONFIDENTIAL/PROPRIETARY

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

1

1 2

PR1210

@

13

D

0_0402 _5%

1 2

2

G

S

1 2

13

D

2

G

S

PQ1214

L2N7002WT1G 1N SC-70-3

AC_DIS C# (36,57)

PR1243

@

0_0402 _5%

1 2

AC_DIS C# (36,57)

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

PWR_2TypeC PD_Selector

PWR_2TypeC PD_Selector

PWR_2TypeC PD_Selector

Size

Size

Size

Document Number Rev

Document Number Rev

Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

LA-F292P

LA-F292P

LA-F292P

58 59Tuesday, Nove mber 14, 2017

58 59Tuesday, Nove mber 14, 2017

58 59Tuesday, Nove mber 14, 2017

1.0

1.0

1.0

5

smd.db-x7.ru

Version Change List ( P. I. R. List ) LA-F292P

Version Change List ( P. I. R. List ) LA-F292P

Version Change List ( P. I. R. List ) LA-F292PVersion Change List ( P. I. R. List ) LA-F292P

Request

Request

Title

Item

ItemItem

D D

C C

11

12

B B

13
14

15
16

17
18

19

20

A A

Page#

Page#Page#

1 37

2

3

5 36

6 25 BOM errorEE

9

10

22 DISPLAY_HPD_EC change to DISPLAY_HPD_EC#2017/05/16 0.2(X01)

52 EE

36 EE

36

36
36

22
28

35

36

36

TitlePage#

TitleTitle

MEC5105

HDMI
MEC5105

Power control
MEC5105

Power control
MEC5105

AR

PD

screw hole

Type C

Type C

Type C

PD

EC MEC5105

EC MEC5105
EC MEC5105

HDMI

BOARD_ID
codec

Card Reader

EC MEC5105

EC MEC5106

Date

Date Issue Description

DateDate

2017/05/16 EE

2017/05/16

2017/05/23

2017/05/23

2017/05/16

2017/05/24

2017/05/24

2017/05/24

2017/05/25

2017/05/25

2017/06/01 0.2(X01)
2017/06/01

2017/06/01
2017/06/01

2017/06/01
2017/06/02

2017/06/02

2017/06/02

Request Request
Owner

Owner

Owner Owner

EE
EE

EE

4

Issue DescriptionItem

Issue DescriptionIssue Description

for smbclk/data missed on EVT CKT

GPIO namingEE

CKT naming error37 EE

modify WLAN PWR enable control CKT4 37 EE

for AREE

part reference naming error7 43 EE "ST1 " change to "ST1", delete unnecessary space

AR layout8 57 EE Change RT159 pop

AR layout

AR layout56 EE

EC to PD SMB swap

EC control power phase EC SWAPEE

DFB requestEE
BOM error

HDMI EA test
BOARD_ID

DFB request
GPIOEE32

modify WLAN PWR enable control CKTEE

align schematic

3

Solution Description

Solution Description

Solution DescriptionSolution Description

UE2.P20 USH_EXPANDER_SMBDAT

UE1.H5 HW_GPS_DISABLE# naming to GPS_DISABLE#2017/05/16
Add QZ15 ,RZ517,RZ518

EC GPIO133 change to "SLP_WLAN#_GATE"
Add RE506

Contact "TBT_RESET_N_EC" From UE2 to UT1
change RT87,RT88 to stuff

change RT89,RT90 to non-stuff

add RT409,RT410
UT1.J4 from TBTA_I2C_INT Change to TBTB_I2C_INT_R &
Add0 ohm to TBTB_I2C_INT
UT1.E2 from TBTB_I2C_INT Change to TBTA_I2C_INT_R &
Add0 ohm to TBTA_I2C_INT
swap PA to TBTB, PB to TBTA

Change ROM From TBTA to TBTB
Del FLASH Conn.
Change RT63 to @
RT218 change to TBTA_ROM_CLK_PD Pull-Down
RT219 change to TBTA_ROM_DI_PD Pull-Down
RT220 change to TBTA_ROM_DO_PD Pull-Down
RT221 change to TBTA_ROM_CS#_PD Pull-Up to +3.3V_TBTA_FLASH

see 0525 swap list
follow EC request SMB ADDR need same with NAR SKU, SWAP UPD1/UPD2 SMB

see 0525 swap list
follow EC request need to swap

1.DCIN1_EN and DCIN2_EN

2.VBUS1_ECOK and VBUS2_ECOK
YE1 change PN from SJ10000PW00 to SJ10000Q400
Change RE95 to stuffEE
change CT203 to @

change RV32 to 200_0402_1% SD034200080
RE79 Change to 130k ohm 0.3(X02)

LA13 footprint change to TAI-T_HCB2012KF-121T50_2P DFX requirementEE
RTK Vic suggest add GPIO1 PU

UR1.32 from SD_GPIO change to SD_GPIO0
UR1.1 PU 10K to +3.3V_MMI_IN

1.UE1.D9 from SLP_WLAN#_GATE Change to SIO_SLP_WLAN#

2.NGFF_CONFIG_1 PU RE552 Cheange Location to RE562

3.SLP_WLAN#_GATE contact to EC GPIO114(Add RE552)

1. RE563 change Location to RE600

2. RE564 change Location to RE601

3. RE565 change Location to RE602

4. RE566 change Location to RE603

2

1

Rev.

Rev.

Rev.Rev.

0.2(X01)UE2.P19 USH_EXPANDER_SMBCLK

0.2(X01)

0.2(X01)

0.2(X01)

0.2(X01)

0.2(X01)

0.2(X01)

0.2(X01)

0.2(X01)

0.2(X01)

0.2(X01)

0.2(X01)

0.2(X01)

0.2(X01)

0.3(X02)

0.3(X02)

0.3(X02)

0.3(X02)

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

EE P.I.R (1/3)

EE P.I.R (1/3)

EE P.I.R (1/3)

LA-F292P

LA-F292P

LA-F292P

59 60Tuesday, November 14, 2017

59 60Tuesday, November 14, 2017

59 60Tuesday, November 14, 2017

1

1.0

1.0

1.0

5

smd.db-x7.ru

Version Change List ( P. I. R. List )

Version Change List ( P. I. R. List )

Version Change List ( P. I. R. List )Version Change List ( P. I. R. List )

Item

Item Issue Description

Page#

ItemItem

Page#Page#

1

57

D D

2

55

3

57 X01

4

52 2017/06/14 NA JUMP PJP403 / PJP404 change to PL407 / PL408 EMI bead

5

55 2017/06/14 NA Add un-stuff footprint PC693 ~ PC696 for RF request

6

57 2017/06/14 NA Add un-stuff footprint PC990 B2 size footprint for acoustic concern X01

7

57 2017/06/14 NA Add PL901 EMI choke for EMI request X01

8

49 2017/06/14 For thermal derating concern Change +5V_ALW output MLCC type from X5R to X6S

C C

9

58 2017/06/14 Vendor sample EOL

10

54 2017/06/14 Vendor sample EOL

11

Date Solution Description

DateDate

2017/06/6 TI symbol shortage issue PQ904 / PQ905 change to AOE6936 (SB00001JP00)

2017/06/6 X01

2017/06/14 NA Change PR915,PR909,PR910,PR937,PR938 size from 0402 to 0603

TI symbol shortage issue PU610 / PU612 / PU613 change to FDMF3035 (SA0000AHX00)

4

Issue DescriptionDate

Issue DescriptionIssue Description

3

because TI shortage issue

because TI shortage issue

because Charger IC version update fine-tune

for more thermal derating
Change MOS solution to 2nd source

from AON7409 to EMZB08P03V because vendor EOL
Location : PQ1202,PQ1203,PQ1211,PQ1212,PQ906

Change MOS solution to 2nd source
from AON7934 to PE642DT because vendor EOL
Location : PQ614

For nAR U22

1. PR636 from 665 change to 732

2. PR651 from 113K change to 105K

3. PR613,PR629 from 86.6K change to 88.7K

4. PC626,PC646 from 0.01uF change to 0.047uF

5. PC624,PC642 from 0.033uF change to 0.022uF

2

Solution Description Rev.

Solution DescriptionSolution Description

1

Rev.Page#

Rev.Rev.

X01

X01

X01

X01

X01

X01

X0255 2017/08/4 For new CPU driver MOS fine-tune R/C value

For nAR U42

1. PR636 from 665 change to 732

2. PR651 from 113K change to 105K

12

B B

55 2017/08/4 For new CPU driver MOS fine-tune R/C value

13

55 2017/08/4 For new CPU driver MOS fine-tune R/C value

14

55 2017/08/10 Stuff component for RF request

15 57 2017/08/10 X02Reserve footprint for chagrer input Add PD906 for footprint reserve

3. PR629 from 86.6K change to 88.7K

4. PC626 from 0.033uF change to 0.1uF

5. PC646 from 0.01uF change to 0.047uF

6. PC624,PC642 from 0.033uF change to 0.022uF

For AR U42

1. PR636 from 665 change to 732

2. PC626 from 0.033uF change to 0.1uF

3. PC624 from 0.033uF change to 0.01uF

4. PC646 from 0.01uF change to 0.047uF

5. PC642 from 0.033uF change to 0.022uF

1. PR202 and PC204 change to stuff

2. PR663 and PC662 change to stuff

3. PC693, PC694, PC695 change to stuff

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

PWR P.I.R

PWR P.I.R

PWR P.I.R

1

X02

X02

X02

A0016 57 Reserve footprint change to stuff PD906 reserve footprint change to stuff

1.0

1.0

59 59Tuesday, November 14, 2017

59 59Tuesday, November 14, 2017

59 59Tuesday, November 14, 2017

1.0

5

smd.db-x7.ru

Version Change List ( P. I. R. List ) LA-F292P

Version Change List ( P. I. R. List ) LA-F292P

Version Change List ( P. I. R. List ) LA-F292PVersion Change List ( P. I. R. List ) LA-F292P

Request

Request

Title

Item

ItemItem

D D

21 0.3(X02)

22
23
24 SUSACK#EE

26
27

31

C C

Page#

Page#Page#

11
39
11 SUSACK#_R Reserved RC550 PU 1K to +3.3V_1.8V_PGPPA
11
38 EE
12

22

TitlePage#

TitleTitle

MEC5105

CPU(6/14)

USH

CPU(6/14)

CPU(6/14)

TPM

CPU(7/14)

CPU

AR

CPU

HDMI

Date

Date Issue Description

DateDate

2017/06/15
2017/06/15
2017/06/15
2017/06/15
2017/06/15
2017/06/15
2017/07/2728 9
2017/07/272329 0.5(X04)
2017/07/27930 align schematicEE
2017/08/07

Request Request
Owner

Owner

Owner Owner

EE Microchip request RC444 Change to @
EE NPCT75x

EE ME Lock RC223.1 from ME_FWP change to ME_FWP_SW

EE

4

Issue DescriptionItem

Issue DescriptionIssue Description

UPD1_HPD/UPD2_HPD EE36

XTALEE25 RC417,RC418 change to 33 ohm
NPCT750 RZ69.1 From +UZ12_VHIO Change to +3.3V_ALW_PCH

align schematicEE

EMI request

3

Solution Description

Solution Description

Solution DescriptionSolution Description

RE553/RE554 resistor to 1M ohm(change to SD028100480)2017/06/07

Pop RZ89, RZ365, RZ112,Depop RZ367, RZ366, RZ62, RZ363

Add RT419

Remove RC405 0.5(X04)
LV31~LV36 Change to 8.2 ohm & LV37~LV38 Change to 15nH,

CT201

、、、、

RT420 & Add RT421 to EC& Reserved RT422 to PCH

、、、、

CT202

、、、、

CT20 4 chang e t o @

2

1

Rev.

Rev.

Rev.Rev.

0.3(X02)

0.3(X02)

0.3(X02)

0.3(X02)

0.3(X02)

0.3(X02)

0.5(X04)align schematicEE Reserved RC557 PU,RC558 PD

0.5(X04)

、、、、

2 6

、、、、

3 4

[Type C]
PD Power-2

[Type C]
PD Controller TI

、、、、

2 6

EC

CPU (4/14)

CPU (4/14)

PD

AR

CPU (4/14)

CPU (7/14)

PAD,LED
MEC5105

support
MEC5105

support
CPU (3/14)

HDMI CONN
& NGFF Card

USH & TPM

All

2017/08/08

2017/08/09

2017/08/09

2017/08/09 EE PD

2017/08/1036 23
2017/10/309
2017/10/30
2017/10/30
2017/10/30

2017/10/30 1.0(A00)

2017/10/30 1.0(A00)

EE

EE

EE

EE 0.5(X04)Add RT456 For RDT3RTD3
EE
EE
EE
EE
EE41 BOARD ID RE79 From 62K change to 4.3KBOARD ID38 2017/10/30 1.0(A00)
EE42 Add footprint -NPM on UC6Add solder mask

EE43
EE44 UZ12 SA0000AQ200->SA0000AQ220 TPM A-rev.
EE45 0 ohm change to short pad0 ohm change to short pad
EE46 UT7 SA00009TZ00 change to SA00009TZ10Change Part Number
EE47 UT5 UT11 SA0000AX700 change to SA0000BIJ00PD change main source

BOARD ID BOARD ID RE79 From 130K change to 62K

RTD3 Reserved RC559

RTD4

ME SW depop
PWR SW depop
UE2 depop

DFX request

Add RC560

PJP7 Change to RT450 Reserved
PJP9 Change to RT452

Depop RC330, RC331GPIO map change 1.0(A00)
Depop RC222, SW1, RC221 change to 0 ohm short pad
Depop SW3
Depop UE2,CE501,CE502,RE501,RE503,RE528,RE504,CE500

Add footprint -NPM on LV3, LV6, LV9, LV12, RI27, RI28,
RI29, RI30, RI47, RI48, RI49, RI50

、、、、

Reserved RC561

、、、、

、、、、

Reserved RT453 to +3.3V_ALW

Add RT451 to +3.3V_ALW

0.5(X04)

0.5(X04)

0.5(X04)

0.5(X04)

1.0(A00)

1.0(A00)

1.0(A00)

32

33

34

35

37
38

B B

39
40

A A

37

9

9

2 5

12
44
38

8 2017/10/30 1.0(A00)

2 3

39 2017/10/30 1.0(A00)
All 2017/10/30 1.0(A00)
27 2017/10/30 1.0(A00)

2 5

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

EE P.I.R (2/3)

EE P.I.R (2/3)

EE P.I.R (2/3)

LA-F292P

LA-F292P

LA-F292P

60 60Tuesday, November 14, 2017

60 60Tuesday, November 14, 2017

60 60Tuesday, November 14, 2017

1

1.0

1.0

1.0

5

smd.db-x7.ru

Version Change List ( P. I. R. List ) LA-F292P

Version Change List ( P. I. R. List ) LA-F292P

Version Change List ( P. I. R. List ) LA-F292PVersion Change List ( P. I. R. List ) LA-F292P

Request

Request

Title

Item

ItemItem

D D

48

49
50

Page#

Page#Page#

23
22

TitlePage#

TitleTitle

TBT-AR-DP
(1/2) DP, PCIE

TBT-AR-DP
(1/2) DP, PCIE

HDMI CONN

Date

Date Issue Description

DateDate

2017/10/30

2017/10/30

2017/10/30

Request Request
Owner

Owner

Owner Owner

EE EMI HDMI request CT201,CT202 depop
EE EMI HDMI request

4

Issue DescriptionItem

Issue DescriptionIssue Description

RTD3_CIO_PWR_EN PU changeEE9,23

3

Solution Description

Solution Description

Solution DescriptionSolution Description

Depop RT372, pop RC559

RV32 SD034200080->SD028360080
LV31,LV32,LV33,LV34,LV35,LV36 SHI0000JI00->SHI0000I300

2

1

Rev.

Rev.

Rev.Rev.

1.0(A00)

1.0(A00)

1.0(A00)

51

2 5

C C

B B

[Type C]
PD Controller TI

、、、、

2 6

2017/11/02 1.0(A00)

EE Material change CT74,CT83,CT150 SE000010V00->SE00000QL10

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

EE P.I.R (3/3)

EE P.I.R (3/3)

EE P.I.R (3/3)

LA-F292P

LA-F292P

LA-F292P

60 60Tuesday, November 14, 2017

60 60Tuesday, November 14, 2017

60 60Tuesday, November 14, 2017

1

1.0

1.0

1.0