A
B
C
D
E
Compal Confidential
Model Name : D4PB1/D5PB1
1 1
File Name : TBD
BOM P/N:43
ZZZ
LA-F241P MB REV1
DAA000EV010
DA2@
ZZZ1
LS-D303P FUN/B
DA400299000
DAS@
ZZZ2
2 2
LS-D302P USB/B
DA6001HX000
DAS@
ZZZ3
Compal Confidential
D4PB1/D5PB1
M/B Schematics Document
LS-A133P
DA600101010
DAS@
ZZZ4
LS-D301P LID/B
DA400272000
DAS@
ZZZ5
LS-B734P
3 3
DA6001B8010
DAS@
ZZZ5
HDMI LOGO
RO0000003HM
HDMI@
ZZZ
LS-B732P
DA4001YF010
DAS@
ZZZ
SKL U22/KBL U22 U42 Processor + DDR4
2017-02-22
Rev:1.0
UC1
FJ8067702739739 SR342 H0 2.5G
CPU_SR342@
SA0000A37N0
UC1
S IC FJ8067702739740 SR341 H0 2.7G ABO
CPU_SR341@
SA0000A34L0
UC1
S IC FJ8067703281813 QN5C Y0 1.8G
CPU_QN5C@
SA0000AQZ10
UC1
S IC FJ8067702739738 SR343 H0 2.4G ABO!
CPU_SR343@
SA0000A38M0
KBL-R U42
DAZ PCB
DAZ1IB00100
4 4
DAZ@
X4EA99BOL01 includes EMC@, EMI@ and ESD@
ZZZ
Security Cl assification
Security Cl assification
SMT EMC EE AF241 D4PB1
X4E@EMC
X4EA99BOL01
A
Security Cl assification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAYNOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAYNOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAYNOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENTEXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS
DEPARTMENTEXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS
DEPARTMENTEXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS
MAYBE USED BY OR DISCLOSED TOANY THIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAYBE USED BY OR DISCLOSED TOANY THIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
MAYBE USED BY OR DISCLOSED TOANY THIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2017/02/22 2018/02/22
2017/02/22 2018/02/22
2017/02/22 2018/02/22
UC1
S IC FJ8067703281813 QN5C Y0 1.8G
CPU_QN5C@
SA0000AQZ10
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Title
Title
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
UC1
S IC FJ8067702739738 SR2ZW H0 2.4G ABO!
CPU_3860@
SA0000A3860
UC1
S IC FJ8067702739738 QLDP H0 2.4G BGA
CPU_3820@
SA0000A3820
UC1
S IC FJ8067702739739 SR2ZU H0 2.5G ABO!
CPU_3760@
SA0000A3760
UC1
S IC FJ8067702739739 QLDM H0 2.5G BGA
CPU_3720@
SA0000A3720
UC1
S IC FJ8066201924931 SR2F0 D1 2.4G ABO!
CPU_2T80@
SA000092T80
UC1
S IC FJ8067702739741 QLDU H0 2.6G BGA
CPU_3L20@
SA0000A3L20
UC1
S IC FJ8067702739740 SR2ZV H0 2.7G ABO!
CPU_3450@
SA0000A3450
UC1
S IC FJ8067702739633 QLYG H0 2.6G BGA
CPU_DO10@
SA0000ADO10
UC1
S IC FJ8067702739628 QLYF H0 2.8G BGA
CPU_DP10@
SA0000ADP10
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Cover Page
Cover Page
Cover Page
LA-F241P
LA-F241P
LA-F241P
E
0.1
0.1
1 54Wednesday, June 14, 2017
1 54Wednesday, June 14, 2017
1 54Wednesday, June 14, 2017
0.1
A
www.schematic-x.blogspot.com
B
C
D
E
Compal Confidential
Touch Screen Conn.
page 21
USB2.0
Intel Skylake U/Kabylake U
1 1
eDP Conn.
page 21
eDP
Skylake U/Kabylake U
DOCK CONN.
page 37
CRT Conn.
page 23
CRT SW.
PI3V713
page 23
HDMI CONN
page 25
MIDI
CHC
2 2
MIDI
CHB
LAN SW.
page 28
MIDI
RJ45 Conn.
PCI-Express x 8 (PCIE2.0 5GT/s)
port 5
LAN(GbE)
Intel I219
page 28
page 29
NGFF Card
WLAN+BT+Wigig
(Combo)
TYPE-C CONN
page 35
port 6,8
page 31
DP to VGA
RTD2168
HDMI/DP
Power delivery
port 4
Card reader
RTS5229
Conn.
page 38
page 22
DDI1
DP SW
PS 8338
page 24
Thunderbolt
AR4C
page 33~34
page 35
SATA x 6 (GEN2 3.0GT/S ,GEN3 6GT/S)
GEN3 GEN3
port 11,12
PCIE/SATA
SSD
NGFF Card
page 27 page 26
DDI2
PCIE
port 9,10
CLK=100MHz
CLK=100MHz
SATA
HDD
Conn.
PCH-LP(MCP)
SKL-U_2+2, KBL-U2+2,
KBL-U4+2
Processor
Dual Core + GT2
15W
1356pin BGA
page 6~17
LPC BUS
CLK=33MHz
port 0
TPM
NPCT650
page 38
Memory BUS(DDR4)
Dual Channel
1.2V DDR4 1866/2133
DOCK CONN.
USB port 3
USBx8
3.3V 48MHz
HD Audio
SPI
SPI ROM
(16M)
page 8
SM BUS
NFC
Module
page 27
page 37
3.3V 24MHz
HDA Codec
ALC3225
260pin DDR4-SO-DIMM X1
DDR4-ON BOARD 4G 8Gbx16
8G 16Gbx16
USB 3.0
conn x3
USB port 1,2,4 USB port 5
page 32 page 21
WLAN Module
for BT
page 31
LTE
Card
USB port 9
page 31
HP
page 30
MIC
LINE IN
Int.
Speaker
page 30
page 18
page 19 ,20
CMOS
Camera
USB port 7
Finger
Print
USB port 8
Combo Jack
(CTIA)
page 38
page 30
3 3
DOCK CONN.
G-Sensor
LS-A131P
FUN/B
page 38
Fan
page 39
ENE KB9022
page 36
LIS3DHTR
page 26
page 37
LS-D302
USB/B
page 32
LS-A133P
CardReader/B
page 38
LS-D301P
LID/B
4 4
page 38
LS-B734P
FP/B
page 38
LS-B732P
TP/B
LS-A136P
Docking1/B
LS-A137P
Docking2/B
A
page 38
page 37
RTC CKT.
page 14
DC/DC Interface CKT.
page 40
Power Circuit DC/DC
page 41~50
B
Touch Pad
page 38
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
Int.KBD
page 38
Compal Secret Data
Compal Secret Data
2017/02/22 2018/02/22
2017/02/22 2018/02/22
2017/02/22 2018/02/22
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Custom
Custom
Custom
Date : Sheet of
Date : Sheet of
Date : Sheet of
Compal Electronics, Inc.
Block Diagrams
Block Diagrams
Block Diagrams
LA-F241P
LA-F241P
LA-F241P
2 54Friday, June 09, 2017
2 54Friday, June 09, 2017
E
2 54Friday, June 09, 2017
0.1
0.1
0.1
A
B
C
D
E
Board ID Table for AD channel
Vcc 3.3V +/- 5%
Board ID
1 1
100K +/- 5%Ra
0
1
2
3
4
5
6
7
0 0 V
12K +/- 1% 0.347 V 0.345 V 0.360 V
15K +/- 1%
20K +/- 1%
27K +/- 1%
33K +/- 1%
43K +/- 1%
56K +/- 1%
Rb V min
BID
0.423 V 0.430 V 0.438 V
V typ
BID
0 V 0.300 V
V
BID
max
EC AD3
0x00 - 0x0B
0x0C - 0x1C
0x1D - 0x26
0x27 - 0x300.541 V 0.550 V 0.559 V
0x31 - 0x3B0.691 V 0.702 V 0.713 V
0x3C - 0x460.807 V 0.819 V 0.831 V
0x47 - 0x540.978 V 0.992 V 1.006 V
0x55 - 0x641.169 V 1.185 V 1.200 V
Power State
STATE
S0 (Full ON) ON ON ON ONHIGH HIGH HIGH
S3 (Suspen d to R AM)
S4 (Suspen d to D isk)
S5 (Soft OFF)
SIGNAL
SLP_S3# SLP_S4# SLP_S 5# +VAL W +V +VS Cl ock
LOW HIG H
LOWLOW
HIGH
HIGH
ONONON
ON
OFF
OFFLOW LOW LOW
OFF
OFF
OFF
OFF
OFF
OFF
BOARD ID Table
Board ID Res Vb rd
EVT 0K 0v 0.1
PV T 12k 0.34 5 V 0.2
PreM P 15k 0.430V 1
versio n
PCB
Project Note
New P 6
BOM Structure Table
BOM Option Table
Item BOM Structure
Unpop
Connector
EMC requirement
EMC requirement unpop
Thunderbolt Funct i on
2 2
UMA only
VGA EMI Requirement
VGA UNPOP
VGA RF Requirement
VGA Power
GC6 Funct i on
INTEL CMC
ESPI
@
EMC@
@EMC@
@EMI@/EMI@EMI requirement
TBT@
@RF@/RF@RF requirement
3G@LTE Funct i on
UMA@
VPRO@/NOVPRO@VPRO Funct i on
@VGA_EMI@/VGA_EMI @
@VGA@
@RF@_VGA@
22@/23E@
GC6@/NOGC6@/NGC6
CMC@
ESPI @
BOM Option Table
Item BOM Structure
dGPU
ON Board DDR4
Without WiGi Funct i on
HDD Redriver
N16V-GM
VRAM BOM Select
Single/Dual Rank
PD Funct i on
ESD requirement
Touch screen reserve
KBL-R U42
KBL U22
VGA@
X76OBRAM@CONN@
SGT@N16S-GT
NOWG@
X76TI@/X76PAR@
VGM@
SR@/DR@
(DR@ is not been used
in this project)
PD@
QH7Y@CPU Code
ESD@
TS@
U42@
U22@
X76@
I2C Address Table
SO C_SMB C LK _ 1 +3 VS JD IMM1 A4 /A5
SO C_SMB C LK _ 1 +3 VS Gs ensor U26 30/31
SO C_SML 0CL K +3V S
SO C_SML 0CL K +3V _LA N
3 3
SO C_SML 1CL K _1 +3V S DGP U_ MA IN
SO C_SML 1CL K _1 +3V S
SO C_SML 1CL K _1 +3V S
EC _SMB_ C K1 +3VL P_E C
EC _SMB_ C K1 +3VL P_E C
EC _SMB_ C K1 +3VL P_E C
BUS D e vic e 8B it Read /W rite
JNF C 1 52 /53
LA N UL 1 C8 /C 9
UGPU1 9E /9F
Therm al S enso r UU24 98/99
PC H_ LP 90 /91
PD U5 007 70 /71
Battery PJ P20 1 16 /17
Charge r P U3 01 12 /13
Voltage Rails
Power Plane
+19V_VIN
+17.4V_BATT
+19VB
+VCC_CORE
+VCC_GT
+VCC_SA
+0.6VS_VTT
+1.0VALW_PRIM +1.0V Always power rail
+1.0V_VCCSTU Sustain voltage for processor in Standby modes
+VCCIO
+1.0VS_VCCSTG +1.0VALW_PRIM Gated version of VCCST
+1.2V_VDDQ
+1.8VALW_PRIM +1.8V Always power rail
+1.8VS System +1.8V power rail
+3VLP +19VB to +3VLP power rail for suspend power
+3VALW System + 3VALW always on power rail
+3VS
+5VALW
+5VS System +5V power rail
+RTCVCC
+1.05VSDGPU +1.05VS power rail for GPU
+1.5VSDGPU +1.5VS power rail for GPU
+3VSDGPU_AON +3VS power rail for GPU(AON rails)
+3VSDGPU_MAIN +3VS power rail for GPU GC62.0
+VGA_CORE
+2.5V
Note : ON*1 means power plane is ON only w hen WOL enable and RTC wake at BIOS setting, otherwise it is OFF.
Description
Adapter power supply
Battery power supply
AC or battery power rail for power circuit.
Processor IA Cores Power Rail
Processor Graphics Power Rails
System Agent power rail
DDR +0.6VS power rail f or DDR terminator .
CPU IO power rail
DDR4 +1.2V Power Rail
System +3V power rail
+5V Always power rail
RTC Battery Power
Core power for descrete GPU
DDR4 +2.5V Power Rail
S0
N/A
N/A
N/A
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON ON
S3
S4/S5
N/A N /A
OFF OFF
OFF
OFF OFF
ON
ON
OFF OFF
ON
ON
OFF
ON
ON
OFF
ON
ON ON
OFF OFF
OFF OFF
OFF
N/AN/A
N/AN/A
OFF
OFFOFF
ON*1
OFF
OFFOFF
OFF
ON*1
OFF
ON
ON*1
OFF
ON
OFFOFF
OFFOFF
OFF
OFFOFF
OFF
43 level BOM table
431A0NBOL0 1
431A0NBOL0 2
431A0NBOL0 3
431A0NBOL0 4
4 4
SMT MB AD3 01 B4DBG QJFC 2.3G UMA HD MI
SMT MB AD3 01 B4DBG QJ8M 2.4G UMA HD MI
SMT MB AD3 01 B4DBG QJKP 2.3G DIS HD MI
SMT MB AD3 01 B4DBG QJKK 2.5G DIS HD MI
A
BOM Structure43 Level Descr ipt ion
3G@/CMC@/DA2@/S R@/EMC@/EMI@/ESD @/HDMI@/NOVPRO@/ PD@/TBT@/U MA@/X 76PA R@/X7 6SAM @/RF@
3G@/CMC@/DA2@/S R@/EMC@/EMI@/ESD @/HDMI@/NOVPRO@/ PD@/TBT@/U MA@/X 76PA R@/X7 6SAM @/RF@
3G@/CMC@/DA2@/S R@/EMC@/EMI@/ESD @/GC6@/HDMI@/PD@ /SGT@/TBT@/VGA@/V GA_EMI @/VP RO@/X 76PA R@/X7 6SAM @/RF@
3G@/CMC@/DA2@/S R@/EMC@/EMI@/ESD @/GC6@/HDMI@/PD@ /SGT@/TBT@/VGA@/V GA_EMI @/VP RO@/X 76PA R@/X7 6SAM @/RF@
Security Classifi cation
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF C OMPALELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF C OMPALELECTRONICS, INC.
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF C OMPALELECTRONICS, INC.
C
2017/02/22 2018/02/22
2017/02/22 2018/02/22
2017/02/22 2018/02/22
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Notes List
Notes List
Notes List
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Custom
Custom
Custom
LA-F241P
LA-F241P
LA-F241P
Date : Sheet o f
Date: Sh eet o f
D
Date: Sh eet o f
E
3 54Wednesday, June 14, 2017
3 54Wednesday, June 14, 2017
3 54Wednesday, June 14, 2017
0.1
0.1
0.1
5
D D
C C
4
3
2
1
B B
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Compal Secret Data
Compal Secret Data
Compal Secret Data
2017/02/22 2018/02/22
2017/02/22 2018/02/22
2017/02/22 2018/02/22
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Power Map
Power Map
Power Map
Size
Size
Size
Document Number Rev
Document Number Rev
Document Number Rev
E
E
E
LA-F241P
LA-F241P
LA-F241P
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
4 54Friday, June 09, 2017
4 54Friday, June 09, 2017
4 54Friday, June 09, 2017
0.1
0.1
0.1
A
B
C
D
E
C4PB1/C5PB1 Power OFF sequence
SPOK
PBTN_OUT#
1 1
C4PB1/C5PB1 Power on sequence
+RTCVCC
SOC_RTCRST#
+19VB
+3VLP
EC_ON
+5VAL W
SPOK
ON/OFF
PBTN_OUT#
+3VAL W
+1.8VALW_P RIM
+1.8 VALW_ PG
EC_RSMRST#
+VCCPRIM_CORE
2 2
PM_SLP_S 5#
PM_SLP_S 4#
PM_SLP_S 3#
SYSON
+1.2V_VDDQ
ESPI_RST#
+1.0V_VCCS TU
+1.0VS_VC CSTG
SUSP#
+5VS/+3VS /+1.8V S
+1.5VS
EC_VCCST_PG
VR_ON
+0.6VS_V TT
3 3
SM_PG_CTRL
+VCC_SA
VR_PWRGD
PCH_PWROK
H_CPUPWRGD
PLT_RST#
+VCC_CORE
4 4
190.0u s
2.56m s
880.0u s
910us
298ms 19ms
131ms
98ms
98ms
70.8u s
802.8u s
635.7m s
218.7m s
38us
41.06
10.12m s
720us
281.7u s
360us
9.080m s
9.72m s
1.62m s
6.160m s
6.040u s
12.4m s
12.8u s
20.8u s
2.224m s
5.26u s
8028m s
9.052m s
2.167m s
653.0u s
+3VAL W
+1.8VALW_P RIM
+1.8 VALW_ PG
EC_RSMRST#
+VCCPRIM_CORE
PM_SLP_S 5#
PM_SLP_S 4#
PM_SLP_S 3#
SYSON
+1.2V_VDDQ
+1.0V_VCCS TU
+1.0VS_VC CSTG
SUSP#
+5VS/+3VS /+1.8V S
EC_VCCST_PG
+1.5VS
VR_ON
+0.6VS_V TT
SM_PG_CTRL
+VCC_SA
VR_PWRGD
PCH_PWROK
H_CPUPWRGD
PLT_RST#
+VCC_CORE
PM_SLP_S 3#
+1.0V_VCCS TU
+1.0VS_VC CSTG
SUSP#
+5VS/+3VS /+1.8V S
+1.5VS
EC_VCCST_PG
VR_ON
+0.6VS_V TT
SM_PG_CTRL
+VCC_SA
VR_PWRGD
PCH_PWROK
H_CPUPWRGD
PLT_RST#
+VCC_CORE
71.68u s
39.12u s
68.48u s
130us
23.84u s
465.6u s
23.84u s
0
31.98u s
5s
29us
78us
29us
26.8u s
26.8u s
29.2u s
89.6u s
465.6u s
C4PB1/C5PB1 S3 sequence
13.46u s
39.86u s
13.46u s
68.8u s
428.3m s 36.6m s
35.68u s
33.04u s
32.4u s
32.4u s
32.4u s
20.8u s
28.2u s
376.8u s
475.2u s
0
0
6.94u s
4.294m s
0
0
4.108m s
4.108m s
8.904 s
ResumOFF
245.3u s
23.61m s
245.3u s
1.632m s
20.424 ms
20.424 ms
20.09m s
20.09m s
2.205m s
22.04m s
30.44m s
133.6m s
143.5m s
653.6u s
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.
MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.
A
B
C
MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.
2017/02/22 2018/02/22
2017/02/22 2018/02/22
2017/02/22 2018/02/22
D
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Power Sequence
Power Sequence
Power Sequence
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
LA-F241P
LA-F241P
LA-F241P
Date: Sheet of
Date: Sheet of
Date: Sheet of
E
5 54Friday, June 09, 2017
5 54Friday, June 09, 2017
5 54Friday, June 09, 2017
0.1
0.1
0.1
A
Functional Strap Definitions
#543016 PDG0.9 P .775
DDPB_CTRLDATA/ GPP_E19 (Internal Pull Down):
DDPC_CTRLDATA/ GPP_E21 (Internal Pull Down):
DDPD_CTRLDATA/ GPP_E23 (Internal Pull Down):
(Sampled:Rising edge of P CH_PWROK)
Display Port B/C/D Detected
0 =Port is not detected.
1 1
1 =Port is detected.
!&%62!% 78!9
+VCCIO
RC1
/
2) #'$3. 4"+3.4"&5 +$34
+1.0V_VCCST
RC2 1K_0402_5%
2 2
EDP_COMP
1 2
24.9_0402_1%
/ /
:;2
7) /'+) #**# <)=>
H_THERMTRIP#
1 2
<BOM Structure>
CC52
@EMC@
.1U_0402_16V7K
H_PECI
12
CC53
ESD@
.1U_0402_16V7K
H_PROCHOT#_R
12
Reserved for ESD 2014/9/17
AR HDMI DDC
H_PROCHOT#<36,43>
PDG0.9 P.771
PROC_ POP IRC OM P/P CH_ OPI RCO MP
PD 50ohm
#544669 CRB RVP7 1.0
EDRAM _OP IO_ RCO MP/ EOP IO_ RC OMP
PD5 0oh m
Docking HDMI+TBT
PS8338 HDMI DDC
TBT_DP1_CTRL_CLK<33>
TBT_DP1_CTRL_DATA<33>
+1.0VS_VCCSTG
B
<DP to VGA>
< PS8338 >
+3VS
R4955 2.2K_0402_5%<BOM Structure>
DDI2_CTRL_CK<24>
DDI2_CTRL_DATA<24>
TBT_DP1_CTRL_CLK
TBT_DP1_CTRL_DATA
12
RC3
1K_0402_5%
1 2
RC4 499_0402_1%
DET_SIG#_R<28,37>
RC5 49.9_0402_1%
RC6 49.9_0402_1%
RC7 49.9_0402_1%
RC8 49.9_0402_1%
SOC_DP1_N0<22>
SOC_DP1_P0<22>
SOC_DP1_N1<22>
SOC_DP1_P1<22>
CPU_DP2_N0<24>
CPU_DP2_P0<24>
CPU_DP2_N1<24>
CPU_DP2_P1<24>
CPU_DP2_N2<24>
CPU_DP2_P2<24>
CPU_DP2_N3<24>
CPU_DP2_P3<24>
12
follow INTEL check list to reserve D63 test point
12
12
12
12
SOC_DP1_CTRL_DATA
DDI2_CTRL_CK
DDI2_CTRL_DATA
@
@
EDP_COMP
T167@
H_PECI<36>
T160@
T161@
T170@
CPU_POPIRCOMP
PCH_OPIRCOMP
EDRAM_OPIO_RCOMP
EOPIO_RCOMP
12
12
RC2380_0402_5%
RC2450_0402_5%
CATERR#
H_PECI
H_PROCHOT#_R
H_THERMTRIP#
XDP_BPM#0
XDP_BPM#1
I2C_TS_INT#
AT16
AU16
UC1A
E55
DDI1_TXN[0]
F55
DDI1_TXP[0]
E58
DDI1_TXN[1]
F58
DDI1_TXP[1]
F53
DDI1_TXN[2]
G53
DDI1_TXP[2]
F56
DDI1_TXN[3]
G56
DDI1_TXP[3]
C50
DDI2_TXN[0]
D50
DDI2_TXP[0]
C52
DDI2_TXN[1]
D52
DDI2_TXP[1]
A50
DDI2_TXN[2]
B50
DDI2_TXP[2]
D51
DDI2_TXN[3]
C51
DDI2_TXP[3]
L13
GPP_E18/DDPB_CTRLCLK
L12
GPP_E19/DDPB_CTRLDATA
N7
GPP_E20/DDPC_CTRLCLK
N8
GPP_E21/DDPC_CTRLDATA
N11
GPP_E22/DDPD_CTRLCLK
N12
GPP_E23/DDPD_CTRLDATA
E52
EDP_RCOMP
SKL-U_BGA1356
@
UC1D
D63
CATERR#
A54
PECI
C65
PROCHOT#
C63
THERMTRIP#
A65
SKTOCC#
C55
BPM#[0]
D55
BPM#[1]
B54
BPM#[2]
C56
BPM#[3]
A6
GPP_E3/CPU_GP0
A7
GPP_E7/CPU_GP1
BA5
GPP_B3/CPU_GP2
AY5
GPP_B4/CPU_GP3
PROC_POPIRCOMP
PCH_OPIRCOMP
H66
OPCE_RCOMP
H65
OPC_RCOMP
SKL-U_BGA1356
@
CPU MISC
C
DDI
DISPLAY SIDEBANDS
SKL-U
4 OF 20
SKL-U
1 OF 20
JTAG
PROC_TCK
PROC_TDO
PROC_TMS
PROC_TRST#
PCH_JTAG_TCK
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS
PCH_TRST#
EDP
Rev_0.5 3
PROC_TDI
JTAGX
Rev_0.5 3
EDP_TXN[0]
EDP_TXP[0]
EDP_TXN[1]
EDP_TXP[1]
EDP_TXN[2]
EDP_TXP[2]
EDP_TXN[3]
EDP_TXP[3]
EDP_AUXN
EDP_AUXP
EDP_DISP_UTIL
DDI1_AUXN
DDI1_AUXP
DDI2_AUXN
DDI2_AUXP
DDI3_AUXN
DDI3_AUXP
GPP_E13/DDPB_HPD0
GPP_E14/DDPC_HPD1
GPP_E15/DDPD_HPD2
GPP_E16/DDPE_HPD3
GPP_E17/EDP_HPD
EDP_BKLTEN
EDP_BKLTCTL
EDP_VDDEN
CPU_XDP_TCK0
B61
SOC_XDP_TDI
D60
SOC_XDP_TDO
A61
SOC_XDP_TMS
C60
SOC_XDP_TRST#
B59
PCH_JTAG_TCK1
B56
SOC_XDP_TDI
D59
SOC_XDP_TDO
A56
SOC_XDP_TMS
C59
SOC_XDP_TRST#
C61
CPU_XDP_TCK0
A59
C47
C46
D46
C45
A45
B45
A47
B47
E45
F45
B52
G50
F50
E48
F48
G46
F46
L9
L7
L6
N9
L10
R12
R11
U13
D
EDP_TXN0 <21>
EDP_TXP0 <21>
EDP_TXN1 <21>
EDP_TXP1 <21>
EDP_TXN2 <21>
EDP_TXP2 <21>
EDP_TXN3 <21>
EDP_TXP3 <21>
EDP_AUXN <21>
EDP_AUXP <21>
SOC_DP1_AUXN
SOC_DP1_AUXP
SOC_DP2_AUXN
SOC_DP2_AUXP
SOC_DP1_HPD
CPU_HDMI_HPD
EC_SCI#
CPU_EDP_HPD
ENBKL
SOC_BKL_PWM
SOC_ENVDD
T3848@
SOC_DP1_AUXN <22>
SOC_DP1_AUXP <22>
DDI2_AUX_DN <24>
DDI2_AUX_DP <24>
SOC_DP1_HPD <22>
CPU_HDMI_HPD <24>
EC_SCI# <36>
CPU_EDP_HPD <21>
ENBKL <36>
SOC_BKL_PWM <21>
SOC_ENVDD <21>
!"
#$ %& ' & ' !
(# ) $ ! $ )*' +) & ) %&,
(" ( " (./
‧‧‧‧
-0. /,
‧‧‧‧
-0, 1
‧‧‧‧
-0,1" -0, /1
‧‧‧‧
<eDP>
DP Aux (Po rt B for VGA)
PS8338
From VGA Trans.
From DP MUX
From eDP
E
RC212
10K_0402_5%
EC_SCI#
1 2
EC_SCI# SOC internal PU
+3VS
@
+1.0VS_VCCSTG
RC11 51_0402_5%CMC@
Place to CPU side
3 3
RC13 51_0402_5%CMC@
RC15 51_0402_5%CMC@
12
12
12
SOC_XDP_TMS
SOC_XDP_TDI
SOC_XDP_TDO
APS CONN
+3VALW_PRIM+3VALW
JAPS1
1
1
A
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
GND
20
GND
ACES_50506-01841-P01
CONN@
12
12
use for iAMT Test
Place to CPU side
PBTN_OUT#_R2
RC35 51_0402_1%CMC@
RC37 51_0402_5%@
12
12
CPU_XDP_TCK0
PCH_JTAG_TCK1
Follow 544924_Skylake_EDS_Vol_1_Rev_0.93
B
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF C OMPALELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF C OMPALELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF C OMPALELECTRONICS, INC.
C
2017/02/22 2018/02/22
2017/02/22 2018/02/22
2017/02/22 2018/02/22
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Date: Sh eet o f
Date: Sh eet o f
Date: Sh eet o f
Compal Electronics, Inc.
SKL-U(1/12)DDI,MSIC,XDP,EDP
SKL-U(1/12)DDI,MSIC,XDP,EDP
SKL-U(1/12)DDI,MSIC,XDP,EDP
Custom
Custom
Custom
LA-F241P
LA-F241P
LA-F241P
E
6 54Friday, June 09, 2017
6 54Friday, June 09, 2017
6 54Friday, June 09, 2017
0.1
0.1
0.1
PM_SLP_S3#<10,36,40>
PM_SLP_S5#<10>
PM_SLP_S4#<10,36,40>
PM_SLP_A#<10,36>
SOC_RTCRST#<10>
SYS_RESET#<10>
PM_SLP_S0#<10>
4 4
PBTN_OUT#<10,36>
ON/OFF#<36,38>
PBTN_OUT#_R2
RC53 0_0402_5%@
RC54 0_0402_5%@
A
B
C
D
E
)' &4)
1 1
UC1B
DDR_A_D[0..15]<19>
DDR_A_D[16..31]<19>
2 2
DDR_A_D[32..47]<19>
DDR_A_D[48..63]<19>
3 3
ES Sample
UC1
4 4
CPU_QHMF_C0_2.3G
QHMF@
SA00008M420
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
UC1
CPU_QHMG_C0_1.6G
QHMG@
SA00008M320
AL71
DDR0_DQ[0]
AL68
DDR0_DQ[1]
AN68
DDR0_DQ[2]
AN69
DDR0_DQ[3]
AL70
DDR0_DQ[4]
AL69
DDR0_DQ[5]
AN70
DDR0_DQ[6]
AN71
DDR0_DQ[7]
AR70
DDR0_DQ[8]
AR68
DDR0_DQ[9]
AU71
DDR0_DQ[10]
AU68
DDR0_DQ[11]
AR71
DDR0_DQ[12]
AR69
DDR0_DQ[13]
AU70
DDR0_DQ[14]
AU69
DDR0_DQ[15]
BB65
DDR0_DQ[16]/DDR0_DQ[32]
AW65
DDR0_DQ[17]/DDR0_DQ[33]
AW63
DDR0_DQ[18]/DDR0_DQ[34]
AY63
DDR0_DQ[19]/DDR0_DQ[35]
BA65
DDR0_DQ[20]/DDR0_DQ[36]
AY65
DDR0_DQ[21]/DDR0_DQ[37]
BA63
DDR0_DQ[22]/DDR0_DQ[38]
BB63
DDR0_DQ[23]/DDR0_DQ[39]
BA61
DDR0_DQ[24]/DDR0_DQ[40]
AW61
DDR0_DQ[25]/DDR0_DQ[41]
BB59
DDR0_DQ[26]/DDR0_DQ[42]
AW59
DDR0_DQ[27]/DDR0_DQ[43]
BB61
DDR0_DQ[28]/DDR0_DQ[44]
AY61
DDR0_DQ[29]/DDR0_DQ[45]
BA59
DDR0_DQ[30]/DDR0_DQ[46]
AY59
DDR0_DQ[31]/DDR0_DQ[47]
AY39
DDR0_DQ[32]/DDR1_DQ[0]
AW39
DDR0_DQ[33]/DDR1_DQ[1]
AY37
DDR0_DQ[34]/DDR1_DQ[2]
AW37
DDR0_DQ[35]/DDR1_DQ[3]
BB39
DDR0_DQ[36]/DDR1_DQ[4]
BA39
DDR0_DQ[37]/DDR1_DQ[5]
BA37
DDR0_DQ[38]/DDR1_DQ[6]
BB37
DDR0_DQ[39]/DDR1_DQ[7]
AY35
DDR0_DQ[40]/DDR1_DQ[8]
AW35
DDR0_DQ[41]/DDR1_DQ[9]
AY33
DDR0_DQ[42]/DDR1_DQ[10]
AW33
DDR0_DQ[43]/DDR1_DQ[11]
BB35
DDR0_DQ[44]/DDR1_DQ[12]
BA35
DDR0_DQ[45]/DDR1_DQ[13]
BA33
DDR0_DQ[46]/DDR1_DQ[14]
BB33
DDR0_DQ[47]/DDR1_DQ[15]
AY31
DDR0_DQ[48]/DDR1_DQ[32]
AW31
DDR0_DQ[49]/DDR1_DQ[33]
AY29
DDR0_DQ[50]/DDR1_DQ[34]
AW29
DDR0_DQ[51]/DDR1_DQ[35]
BB31
DDR0_DQ[52]/DDR1_DQ[36]
BA31
DDR0_DQ[53]/DDR1_DQ[37]
BA29
DDR0_DQ[54]/DDR1_DQ[38]
BB29
DDR0_DQ[55]/DDR1_DQ[39]
AY27
DDR0_DQ[56]/DDR1_DQ[40]
AW27
DDR0_DQ[57]/DDR1_DQ[41]
AY25
DDR0_DQ[58]/DDR1_DQ[42]
AW25
DDR0_DQ[59]/DDR1_DQ[43]
BB27
DDR0_DQ[60]/DDR1_DQ[44]
BA27
DDR0_DQ[61]/DDR1_DQ[45]
BA25
DDR0_DQ[62]/DDR1_DQ[46]
BB25
DDR0_DQ[63]/DDR1_DQ[47]
SKL-U_BGA1356
@
SKL-U
DDR0_CKN[0]
DDR0_CKP[0]
DDR0_CKN[1]
DDR0_CKP[1]
DDR0_CKE[0]
DDR0_CKE[1]
DDR0_CKE[2]
DDR0_CKE[3]
DDR0_CS#[0]
DDR0_CS#[1]
DDR0_ODT[0]
DDR0_MA[5]/DDR0_CAA[0]/DDR0_M A[5]
DDR0_MA[9]/DDR0_CAA[1]/DDR0_M A[9]
DDR0_MA[6]/DDR0_CAA[2]/DDR0_M A[6]
DDR0_MA[8]/DDR0_CAA[3]/DDR0_M A[8]
DDR0_MA[7]/DDR0_CAA[4]/DDR0_M A[7]
DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]
DDR0_MA[12]/DDR0_CAA[6]/DDR0_ MA[12]
DDR0_MA[11]/DDR0_CAA[7]/DDR0_ MA[11]
DDR0_MA[15]/DDR0_CAA[8]/DDR0_ ACT#
DDR0_MA[14]/DDR0_CAA[9]/DDR0_ BG[1]
DDR0_MA[13]/DDR0_CAB[0]/DDR0_ MA[13]
DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15 ]
DDR0_WE#/DDR0_CAB[2]/DDR 0_MA[14]
DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16 ]
DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]
DDR0_MA[2]/DDR0_CAB[5]/DDR0_M A[2]
DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]
DDR0_MA[10]/DDR0_CAB[7]/DDR0_ MA[10]
DDR0_MA[1]/DDR0_CAB[8]/DDR0_M A[1]
DDR0_MA[0]/DDR0_CAB[9]/DDR0_M A[0]
DDR0_DQSN[2]/DDR0_DQSN[4]
DDR0_DQSP[2]/DDR0_DQSP[4]
DDR0_DQSN[3]/DDR0_DQSN[5]
DDR0_DQSP[3]/DDR0_DQSP[5]
DDR0_DQSN[4]/DDR1_DQSN[0]
DDR0_DQSP[4]/DDR1_DQSP[0]
DDR0_DQSN[5]/DDR1_DQSN[1]
DDR0_DQSP[5]/DDR1_DQSP[1]
DDR0_DQSN[6]/DDR1_DQSN[4]
DDR0_DQSP[6]/DDR1_DQSP[4]
DDR0_DQSN[7]/DDR1_DQSN[5]
DDR0_DQSP[7]/DDR1_DQSP[5]
DDR0_ODT[1]
DDR0_DQSN[0]
DDR0_DQSP[0]
DDR0_DQSN[1]
DDR0_DQSP[1]
DDR0_ALERT#
DDR_VREF_CA
DDR CH - A
2 OF 20
DDR0_VREF_DQ
DDR1_VREF_DQ
DDR_VTT_CNTL
DDR0_MA[3]
DDR0_MA[4]
DDR0_PAR
DDR_A_CLK#0
AU53
DDR_A_CLK0
AT53
DDR_A_CLK#1
AU55
DDR_A_CLK1
AT55
DDR_A_CKE0
BA56
DDR_A_CKE1
BB56
AW56
AY56
DDR_A_CS#0
AU45
DDR_A_CS#1
AU43
DDR_A_ODT0
AT45
DDR_A_ODT1
AT43
DDR_A_MA5
BA51
DDR_A_MA9
BB54
DDR_A_MA6
BA52
DDR_A_MA8
AY52
DDR_A_MA7
AW52
DDR_A_BG0
AY55
DDR_A_MA12
AW54
DDR_A_MA11
BA54
M_A_ACT#
BA55
DDR_A_BG1
AY54
DDR_A_MA13
AU46
DDR_A_MA15
AU48
DDR_A_MA14
AT46
DDR_A_MA16
AU50
DDR_A_BA0
AU52
DDR_A_MA2
AY51
DDR_A_BA1
AT48
DDR_A_MA10
AT50
DDR_A_MA1
BB50
DDR_A_MA0
AY50
DDR_A_MA3
BA50
DDR_A_MA4
BB52
DDR_A_DQS#0
AM70
DDR_A_DQS0
AM69
DDR_A_DQS#1
AT69
DDR_A_DQS1
AT70
DDR_A_DQS#2
BA64
DDR_A_DQS2
AY64
DDR_A_DQS#3
AY60
DDR_A_DQS3
BA60
DDR_A_DQS#4
BA38
DDR_A_DQS4
AY38
DDR_A_DQS#5
AY34
DDR_A_DQS5
BA34
DDR_A_DQS#6
BA30
DDR_A_DQS6
AY30
DDR_A_DQS#7
AY26
DDR_A_DQS7
BA26
AW50
AT52
+0.6V_VREFCA
AY67
AY68
+0.6V_B_VREFDQ
BA67
DDR_PG_CTRL
AW67
DDR_ VTT_CNTL to DDR
VTT supplied ramped
<35 uS
(tC PU1 8)
DDR_PG_CTRL
Reserve for cost test.
T25@
DDR_A_CLK#0 <19>
DDR_A_CLK0 <19>
T20@
T19@
DDR_A_CKE0 <19,20>
T21@
DDR_A_CS#0 <19,20>
T23@
T22@
DDR_A_MA5 <19,20>
DDR_A_MA9 <19,20>
DDR_A_MA6 <19,20>
DDR_A_MA8 <19,20>
DDR_A_MA7 <19,20>
DDR_A_BG0 <19,20>
DDR_A_MA12 <19,20>
DDR_A_MA11 <19,20>
M_A_ACT# <19,20>
DDR_A_BG1 <19>
DDR_A_MA13 <19,20>
DDR_A_MA15 <19,20>
DDR_A_MA14 <19,20>
DDR_A_MA16 <19,20>
DDR_A_BA0 <19,20>
DDR_A_MA2 <19,20>
DDR_A_BA1 <19,20>
DDR_A_MA10 <19,20>
DDR_A_MA1 <19,20>
DDR_A_MA0 <19,20>
DDR_A_MA3 <19,20>
DDR_A_MA4 <19,20>
DDR_A_DQS#0 <19>
DDR_A_DQS0 <19>
DDR_A_DQS#1 <19>
DDR_A_DQS1 <19>
DDR_A_DQS#2 <19>
DDR_A_DQS2 <19>
DDR_A_DQS#3 <19>
DDR_A_DQS3 <19>
DDR_A_DQS#4 <19>
DDR_A_DQS4 <19>
DDR_A_DQS#5 <19>
DDR_A_DQS5 <19>
DDR_A_DQS#6 <19>
DDR_A_DQS6 <19>
DDR_A_DQS#7 <19>
DDR_A_DQS7 <19>
DDR_A_ALERT# <19>
DDR_A_PARITY <19,20>
+0.6V_VREFCA <19>
+0.6V_B_VREFDQ <18>
12
<BOM Structure>
UC7
NC1VCC
2
A
GND
Y
G
123
D
S
Q2009
@
3
74AUP1G07GW_TSSOP5
<BOM Structure>
+1.2V_VDDQ
MESS138W-G_SOT323-3
DDR_B_D[0..15]<18>
DDR_B_D[16..31]<18>
DDR_B_D[32..47]<18>
DDR_B_D[48..63]<18>
Trace width/Spacing >= 20mils
Place componment near SODIMM
#543016 PDG0.9 P.163 RC place near SODIMM
+1.2V_VDDQ
+3VS
CC57.1U_0402_16V7K
12
5
4
RC10
220K_0402_5%
<BOM Structure>
RC16
2M_0402_5%@
1 2
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
SM_PG_CTRL <45>
UC1C
AF65
DDR1_DQ[0]/DDR0_DQ[16]
AF64
DDR1_DQ[1]/DDR0_DQ[17]
AK65
DDR1_DQ[2]/DDR0_DQ[18]
AK64
DDR1_DQ[3]/DDR0_DQ[19]
AF66
DDR1_DQ[4]/DDR0_DQ[20]
AF67
DDR1_DQ[5]/DDR0_DQ[21]
AK67
DDR1_DQ[6]/DDR0_DQ[22]
AK66
DDR1_DQ[7]/DDR0_DQ[23]
AF70
DDR1_DQ[8]/DDR0_DQ[24]
AF68
DDR1_DQ[9]/DDR0_DQ[25]
AH71
DDR1_DQ[10]/DDR0_DQ[26]
AH68
DDR1_DQ[11]/DDR0_DQ[27]
AF71
DDR1_DQ[12]/DDR0_DQ[28]
AF69
DDR1_DQ[13]/DDR0_DQ[29]
AH70
DDR1_DQ[14]/DDR0_DQ[30]
AH69
DDR1_DQ[15]/DDR0_DQ[31]
AT66
DDR1_DQ[16]/DDR0_DQ[48]
AU66
DDR1_DQ[17]/DDR0_DQ[49]
AP65
DDR1_DQ[18]/DDR0_DQ[50]
AN65
DDR1_DQ[19]/DDR0_DQ[51]
AN66
DDR1_DQ[20]/DDR0_DQ[52]
AP66
DDR1_DQ[21]/DDR0_DQ[53]
AT65
DDR1_DQ[22]/DDR0_DQ[54]
AU65
DDR1_DQ[23]/DDR0_DQ[55]
AT61
DDR1_DQ[24]/DDR0_DQ[56]
AU61
DDR1_DQ[25]/DDR0_DQ[57]
AP60
DDR1_DQ[26]/DDR0_DQ[58]
AN60
DDR1_DQ[27]/DDR0_DQ[59]
AN61
DDR1_DQ[28]/DDR0_DQ[60]
AP61
DDR1_DQ[29]/DDR0_DQ[61]
AT60
DDR1_DQ[30]/DDR0_DQ[62]
AU60
DDR1_DQ[31]/DDR0_DQ[63]
AU40
DDR1_DQ[32]/DDR1_DQ[16]
AT40
DDR1_DQ[33]/DDR1_DQ[17]
AT37
DDR1_DQ[34]/DDR1_DQ[18]
AU37
DDR1_DQ[35]/DDR1_DQ[19]
AR40
DDR1_DQ[36]/DDR1_DQ[20]
AP40
DDR1_DQ[37]/DDR1_DQ[21]
AP37
DDR1_DQ[38]/DDR1_DQ[22]
AR37
DDR1_DQ[39]/DDR1_DQ[23]
AT33
DDR1_DQ[40]/DDR1_DQ[24]
AU33
DDR1_DQ[41]/DDR1_DQ[25]
AU30
DDR1_DQ[42]/DDR1_DQ[26]
AT30
DDR1_DQ[43]/DDR1_DQ[27]
AR33
DDR1_DQ[44]/DDR1_DQ[28]
AP33
DDR1_DQ[45]/DDR1_DQ[29]
AR30
DDR1_DQ[46]/DDR1_DQ[30]
AP30
DDR1_DQ[47]/DDR1_DQ[31]
AU27
DDR1_DQ[48]
AT27
DDR1_DQ[49]
AT25
DDR1_DQ[50]
AU25
DDR1_DQ[51]
AP27
DDR1_DQ[52]
AN27
DDR1_DQ[53]
AN25
DDR1_DQ[54]
AP25
DDR1_DQ[55]
AT22
DDR1_DQ[56]
AU22
DDR1_DQ[57]
AU21
DDR1_DQ[58]
AT21
DDR1_DQ[59]
AN22
DDR1_DQ[60]
AP22
DDR1_DQ[61]
AP21
DDR1_DQ[62]
AN21
DDR1_DQ[63]
SKL-U_BGA1356
@
SKL-U
DDR1_MA[5]/DDR1_CAA[0]/DDR1_M A[5]
DDR1_MA[9]/DDR1_CAA[1]/DDR1_M A[9]
DDR1_MA[6]/DDR1_CAA[2]/DDR1_M A[6]
DDR1_MA[8]/DDR1_CAA[3]/DDR1_M A[8]
DDR1_MA[7]/DDR1_CAA[4]/DDR1_M A[7]
DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]
DDR1_MA[12]/DDR1_CAA[6]/DDR1_ MA[12]
DDR1_MA[11]/DDR1_CAA[7]/DDR1_ MA[11]
DDR1_MA[15]/DDR1_CAA[8]/DDR1_ ACT#
DDR1_MA[14]/DDR1_CAA[9]/DDR1_ BG[1]
DDR1_MA[13]/DDR1_CAB[0]/DDR1_ MA[13]
DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15 ]
DDR1_WE#/DDR1_CAB[2]/DDR 1_MA[14]
DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16 ]
DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]
DDR1_MA[2]/DDR1_CAB[5]/DDR1_M A[2]
DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]
DDR1_MA[10]/DDR1_CAB[7]/DDR1_ MA[10]
DDR1_MA[1]/DDR1_CAB[8]/DDR1_M A[1]
DDR1_MA[0]/DDR1_CAB[9]/DDR1_M A[0]
DDR1_DQSN[0]/DDR0_DQSN[2]
DDR1_DQSP[0]/DDR0_DQSP[2]
DDR1_DQSN[1]/DDR0_DQSN[3]
DDR1_DQSP[1]/DDR0_DQSP[3]
DDR1_DQSN[2]/DDR0_DQSN[6]
DDR1_DQSP[2]/DDR0_DQSP[6]
DDR1_DQSN[3]/DDR0_DQSN[7]
DDR1_DQSP[3]/DDR0_DQSP[7]
DDR1_DQSN[4]/DDR1_DQSN[2]
DDR1_DQSP[4]/DDR1_DQSP[2]
DDR1_DQSN[5]/DDR1_DQSN[3]
DDR1_DQSP[5]/DDR1_DQSP[3]
DDR_RCOMP[0]
DDR CH - B
3 OF 20
DDR_RCOMP[1]
DDR_RCOMP[2]
Rev_0.5 3Rev_0.5 3
DDR1_CKN[0]
DDR1_CKN[1]
DDR1_CKP[0]
DDR1_CKP[1]
DDR1_CKE[0]
DDR1_CKE[1]
DDR1_CKE[2]
DDR1_CKE[3]
DDR1_CS#[0]
DDR1_CS#[1]
DDR1_ODT[0]
DDR1_ODT[1]
DDR1_MA[3]
DDR1_MA[4]
DDR1_DQSN[6]
DDR1_DQSP[6]
DDR1_DQSN[7]
DDR1_DQSP[7]
DDR1_ALERT#
DDR1_PAR
DRAM_RESET#
DDR_B_CLK#0
AN45
DDR_B_CLK#1
AN46
DDR_B_CLK0
AP45
DDR_B_CLK1
AP46
DDR_B_CKE0
AN56
DDR_B_CKE1
AP55
AN55
AP53
DDR_B_CS#0
BB42
DDR_B_CS#1
AY42
DDR_B_ODT0
BA42
DDR_B_ODT1
AW42
DDR_B_MA5
AY48
DDR_B_MA9
AP50
DDR_B_MA6
BA48
DDR_B_MA8
BB48
DDR_B_MA7
AP48
DDR_B_BG0
AP52
DDR_B_MA12
AN50
DDR_B_MA11
AN48
M_B_ACT#
AN53
DDR_B_BG1
AN52
DDR_B_MA13
BA43
DDR_B_MA15
AY43
DDR_B_MA14
AY44
DDR_B_MA16
AW44
DDR_B_BA0
BB44
DDR_B_MA2
AY47
DDR_B_BA1
BA44
DDR_B_MA10
AW46
DDR_B_MA1
AY46
DDR_B_MA0
BA46
DDR_B_MA3
BB46
DDR_B_MA4
BA47
DDR_B_DQS#0
AH66
DDR_B_DQS0
AH65
DDR_B_DQS#1
AG69
DDR_B_DQS1
AG70
DDR_B_DQS#2
AR66
DDR_B_DQS2
AR65
DDR_B_DQS#3
AR61
DDR_B_DQS3
AR60
DDR_B_DQS#4
AT38
DDR_B_DQS4
AR38
DDR_B_DQS#5
AT32
DDR_B_DQS5
AR32
DDR_B_DQS#6
AR25
DDR_B_DQS6
AR27
DDR_B_DQS#7
AR22
DDR_B_DQS7
AR21
DDR_B_ALERT#
AN43
DDR_B_PARITY
AP43
DDR_DRAMRST#
AT13
AR18
AT18
SM_RCOMP0
AU18
SM_RCOMP1
SM_RCOMP2
#543016 PDG0.9 P.117
W=12-15 Space= 20/25 L=500mil
DDR_B_CLK#0 <18>
DDR_B_CLK#1 <18>
DDR_B_CLK0 <18>
DDR_B_CLK1 <18>
DDR_B_CKE0 <18>
DDR_B_CKE1 <18>
DDR_B_CS#0 <18>
DDR_B_CS#1 <18>DDR_A_ODT0 <19,20>
DDR_B_ODT0 <18>
DDR_B_ODT1 <18>
DDR_B_MA5 <18>
DDR_B_MA9 <18>
DDR_B_MA6 <18>
DDR_B_MA8 <18>
DDR_B_MA7 <18>
DDR_B_BG0 <18>
DDR_B_MA12 <18>
DDR_B_MA11 <18>
M_B_ACT# <18>
DDR_B_BG1 <18>
DDR_B_MA13 <18>
DDR_B_MA15 <18>
DDR_B_MA14 <18>
DDR_B_MA16 <18>
DDR_B_BA0 <18>
DDR_B_MA2 <18>
DDR_B_BA1 <18>
DDR_B_MA10 <18>
DDR_B_MA1 <18>
DDR_B_MA0 <18>
DDR_B_MA3 <18>
DDR_B_MA4 <18>
DDR_B_DQS#0 <18>
DDR_B_DQS0 <18>
DDR_B_DQS#1 <18>
DDR_B_DQS1 <18>
DDR_B_DQS#2 <18>
DDR_B_DQS2 <18>
DDR_B_DQS#3 <18>
DDR_B_DQS3 <18>
DDR_B_DQS#4 <18>
DDR_B_DQS4 <18>
DDR_B_DQS#5 <18>
DDR_B_DQS5 <18>
DDR_B_DQS#6 <18>
DDR_B_DQS6 <18>
DDR_B_DQS#7 <18>
DDR_B_DQS7 <18>
DDR_B_ALERT# <18>
DDR_B_PARITY <18>
follow INTEL review feedback change to 200ohm
DDR_DRAMRST# <18,19>
RC38 121_0402_1%
1 2
1 2
RC39 80.6_0402_1%
1 2
RC40 100_0402_1%
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF C OMPALELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF C OMPALELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF C OMPALELECTRONICS, INC.
C
2017/02/22 2018/02/22
2017/02/22 2018/02/22
2017/02/22 2018/02/22
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Custom
Custom
Custom
Date: Sh eet o f
Date: Sh eet o f
D
Date: Sh eet o f
SKL-U(2/12)DDR
SKL-U(2/12)DDR
SKL-U(2/12)DDR
LA-F241P
LA-F241P
LA-F241P
Friday, June 09, 2017
Friday, June 09, 2017
Friday, June 09, 2017
E
7
0.1
0.1
0.1
54
54
54
7
7
A
B
C
D
E
UC1E
SOC_SPI_C LK
SOC_SPI_S O
SOC_SPI_S I
SPI ROM
1 1
RTD3_US B_PWR_EN<33>
To TPM
RTD3_CIO_ PWR_EN<33>
TBT_BAT LOW#<33>
TBT_FOR CE_PWR<33>
TBT_CIO_P LUG_EVENT#<33>
CL_CLK<31>
CL_DATA<31>
CL_RST#< 31>
EC_KBRS T#_R<36>
TPM_SER IRQ<36,38>
AR GPIO
WLAN
SOC_SPI_IO2
SOC_SPI_IO3
SOC_SPI_C S#0
TBT_FOR CE_PWR
TBT_CIO_P LUG_EVENT#
EC_KBRS T#_R
TPM_SER IRQ
AV2
AW3
AV3
AW2
AU4
AU3
AU2
AU1
AW13
AY11
M2
M3
J4
V1
V2
M1
G3
G2
G1
LPC Mode
2 2
Single SPI ROM_CS0#
To SPI ROM
3 3
UC2
W25 Q128JVSIQ_SO8
ROM16M@
SA00005 VV20
SPI ROM ( 8MByte )
SOC_SPI_C S#0
SOC_SPI_IO2_ 0_R
4 4
ROM Socket
SOC_SPI_C S#0
SOC_SPI_IO2_ 0_R
SOC_SPI_IO3_ 0_R
UC2
W25 Q64FVSSIQ_SO8
ROM8M@
UC2
1
2
3
4
W25 Q64FVSSIQ_SO8
@
1
3
7
4
A
RPC5 and RC 52 are clo se UC2
RPC5
1 8
2 7
3 6
4 5
33_0804 _8P4R_5%
RC52
<BOM Struc ture>
UC9
W25 Q64FVSSIQ_SO8
ROM8M@
+3VALW _SPI
8
/CS
DO(IO1)
/WP(IO2)
GND
JC1
CS#
WP#
HOLD#
GND
ACES_91 960-0084N_MX2 5L3206EM2I
CONN@
VCC
/HOLD(IO3)
CLK
DI(IO0)
VCC
SCLK
SI/SIO0
SO/SIO1
SOC_SPI_IO3_ 0_RSOC_SPI_S O_0_R
7
SOC_SPI_C LK_0_R
6
SOC_SPI_S I_0_R
5
+3VALW _SPI
8
SOC_SPI_C LK_0_R
6
SOC_SPI_S I_0_R
5
SOC_SPI_S O_0_R
2
SOC_SPI_C LK_0_R
<BOM Struc ture>
SOC_SPI_IO3SO C_SPI_IO3_0_R
SOC_SPI_S ISOC_SPI_S I_0_R
SOC_SPI_C LKSOC_SPI_C LK_0_R
SOC_SPI_S OSOC_SPI_S O_0_R
SOC_SPI_IO2SOC_SPI_IO2_ 0_R
12
33_0402 _5%
CC8
.1U_0402 _16V7K
1 2
1 2
<BOM Struc ture>
RC24
0_0402_ 5%@EMC@
SPI - FLASH
SPI0_CLK
SPI0_MISO
SPI0_MOSI
SPI0_IO2
SPI0_IO3
SPI0_CS0#
SPI0_CS1#
SPI0_CS2#
SPI - TOUCH
GPP_D1/SPI1_CLK
GPP_D2/SPI1_MISO
GPP_D3/SPI1_MOSI
GPP_D21/SPI1_IO2
GPP_D22/SPI1_IO3
GPP_D0/SPI1_CS#
C LINK
CL_CLK
CL_DATA
CL_RST#
GPP_A0/RCIN#
GPP_A6/SERIRQ
SKL-U_BG A1356
@
1 2
CC9
10P_040 2_50V8J
@EMC@
B
SKL-U
PM_CLKR UN#
TPM_SER IRQ
LPC
SMBUS, SMLINK
GPP_B23/SML1ALERT#/PCHHOT#
GPP_A14/SUS_STAT#/ESPI_RESET#
GPP_A9/CLKOUT_LPC0/ESPI_CLK
5 OF 20
1 2
RC107 10K_040 2_5%
1 2
RC112 10K_040 2_5%
GPP_C5/SML0ALERT#
GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1
GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3
GPP_A5/LFRAME#/ESPI_CS#
GPP_A10/CLKOUT_LPC1
<BOM Struc ture>
<BOM Struc ture>
Rev_0 .53
GPP_C0/SMBCLK
GPP_C1/SMBDATA
GPP_C2/SMBALERT#
GPP_C3/SML0CLK
GPP_C4/SML0DATA
GPP_C6/SML1CLK
GPP_C7/SML1DATA
GPP_A8/CLKRUN#
+1.8VS_3 VS_PGPPA
2015MOW06 no need PU 1K on SPI_IO 2/IO3
SOC_SPI_IO2
SOC_SPI_IO3
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1 2
RC47 1 K_0402_1%@
1 2
RC48 1 K_0402_1%@
2017/02/ 22 2018/02/ 22
2017/02/ 22 2018/02/ 22
2017/02/ 22 2018/02/ 22
C
R7
R8
R10
R9
W2
W1
W3
V3
AM7
AY13
BA13
BB13
AY12
BA12
BA11
AW9
AY9
AW11
+3VALW _SPI
SOC_SMB CLK_1
SOC_SMB DATA_1
SOC_SMB ALERT#
SOC_SML 0CLK
SOC_SML 0DATA
SOC_SML 0ALERT#
SOC_SML 1CLK_1
SOC_SML 1DATA_1
SOC_SML 1ALERT#
LPC_AD0
RC144 0_040 2_5%@
LPC_AD1
RC145 0_040 2_5%@
LPC_AD2
RC146 0_040 2_5%@
LPC_AD3
RC147 0_040 2_5%@
LPC_FRA ME#
ESPI_RST#
ESPI_CLK
CK_LPC_ TPM_R
PM_CLKR UN#
Compal Secret Data
Compal Secret Data
Compal Secret Data
RC45 22_0402_5%
R395 22_04 02_5%
SOC_SML 0CLK
SOC_SML 0DATA
SOC_SMB CLK_1
SOC_SMB DATA_1
SOC_SML 1CLK_1
SOC_SML 1DATA_1
ME2N7002D1KW use SB00000DH00 symbol
Deciphered Date
Deciphered Date
Deciphered Date
RC250 2.2K _0402_5%
SOC_SML 0CLK <27,28>
SOC_SML 0DATA <27,28>
1 2
1 2
1 2
1 2
<BOM Struc ture>
T234@
LPC_FRA ME# <36,38>
T235@
12
12
PM_CLKR UN# <38 >
1 2
RC49 4 99_0402_1%<BOM Struc ture>
1 2
RC50 4 99_0402_1%<BOM Struc ture>
1 8
2 7
3 6
4 5
SOC_SMB CLK_1
SOC_SMB DATA_1
SOC_SML 1CLK_1
SOC_SML 1DATA_1
+3VALW _PRIM
12
+3VALW _PRIM
12
RC2024.7K_040 2_5% ESPI@
LPC_AD0 _R <36,38 >
LPC_AD1 _R <36,38 >
LPC_AD2 _R <36,38 >
LPC_AD3 _R <36,38 >
CK_LPC_ TPM <38>
For TPM
+3VALW _PRIM
RPC7
2.2K_080 4_8P4R_5%
<BOM Struc ture>
RC220 0_0402_ 5%@
RC221 0_0402_ 5%@
+3VS
3 4
RC225 0_0402_ 5%@
RC224 0_0402_ 5%@
6 1
+3VS
D
Strap Pin
+3VS
5
Q2017B
3 4
6 1
+3VS
ME2N700 2D1KW-G 2N S OT363-6
12
12
Q2017A
ME2N700 2D1KW-G 2N S OT363-6
2
SB00000 SA00
5
Q2018B
ME2N700 2D1KW-G 2N S OT363-6
12
12
Q2018A
ME2N700 2D1KW-G 2N S OT363-6
2
Title
Title
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Custom
Custom
Custom
Date : Sheet of
Date : Sheet of
Date : Sheet of
SMB
(Link to DDR, G-sensor)
SML0
(Link to NFC, LAN)
SML1
(Link to EC, DGPU, DDR thermal, RTD2168)
ESPI / LPC Bus
ESPI : +1.8V
LPC : +3.3V
RC45
To EC
ESPI_CLK_ R <36>
1
@RF@
C5241
22P_040 2_50V8J
2
SOC_SMB CLK
SOC_SMB DATA
SOC_SML 1CLK
SOC_SML 1DATA
SB00000 SA00
SOC_SMB CLK
SOC_SMB DATA
SB00000 SA00
SOC_SML 1CLK
SOC_SML 1DATA
SB00000 SA00
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
SKL-U(3/12)SPI,ESPI,SMB,LPC
SKL-U(3/12)SPI,ESPI,SMB,LPC
SKL-U(3/12)SPI,ESPI,SMB,LPC
LA-F241P
LA-F241P
LA-F241P
15_0402 _5%
ESPI@
1 2
RC222 2.2K_0 402_5%<BOM Struc ture>
1 2
RC223 2.2K_0 402_5%<BOM Struc ture>
1 2
RC246 2.2K_0 402_5%<BOM Struc ture>
1 2
RC247 2.2K_0 402_5%<BOM Struc ture>
SOC_SMB CLK <18,26>
SOC_SMB DATA <18,26>
SOC_SML 1CLK <19,22,36 >
SOC_SML 1DATA <19,22,36>
E
+3VS
0.1
0.1
0.1
8 54Friday, June 09, 201 7
8 54Friday, June 09, 201 7
8 54Friday, June 09, 201 7
A
#545659 SKL_PCH_EDS_R0.7 P.84
B
C
D
E
UC1G
HDA_SYNC
HDA_BIT_C LK
HDA_SDO UT
HDA_SDIN0
1 1
HDA_RST #
Functional Strap Definitions
SPKR / GPP_B14 (Internal Pull Down):
(Sampled:Rising edge of PCH_PWROK)
TOP Swap Override
0 = Disable TOP Swap mode.---> AAX05 Use
1 = Enable TOP Swap Mode.
2 2
3 3
PCH_DMIC_ CLK<30>
PCH_DMIC_ DATA<30>
BEEP#<30>
PCH_DMIC_ CLK
PCH_DMIC_ DATA
BEEP#
BA22
AY22
BB22
BA21
AY21
AW22
AY20
AW20
AK7
AK6
AK9
AK10
AW5
J5
H5
D7
D8
C8
12
AUDIO
HDA_SYNC/I2S0_SFRM
HDA_BLK/I2S0_SCLK
HDA_SDO/I2S0_TXD
HDA_SDI0/I2S0_RXD
HDA_SDI1/I2S1_RXD
HDA_RST#/I2S1_SCLK
GPP_D23/I2S_MCLK
I2S1_SFRM
I2S1_TXD
GPP_F1/I2S2_SFRM
GPP_F0/I2S2_SCLK
GPP_F2/I2S2_TXD
GPP_F3/I2S2_RXD
GPP_D19/DMIC_CLK0
GPP_D20/DMIC_DATA0
GPP_D17/DMIC_CLK1
GPP_D18/DMIC_DATA1
GPP_B14/SPKR
SKL-U_BG A1356
@
HDA_BIT_C LK_R HDA_SYNC
RF@
0_0402_ 5%
R5253
2
RF@
C5228
22P_040 2_50V8J
1
UC1I
CSI-2
A36
CSI2_DN0
B36
CSI2_DP0
C38
CSI2_DN1
D38
CSI2_DP1
C36
CSI2_DN2
D36
CSI2_DP2
A38
CSI2_DN3
B38
CSI2_DP3
C31
CSI2_DN4
D31
CSI2_DP4
C33
CSI2_DN5
D33
CSI2_DP5
A31
CSI2_DN6
B31
CSI2_DP6
A33
CSI2_DN7
B33
CSI2_DP7
A29
CSI2_DN8
B29
CSI2_DP8
C28
CSI2_DN9
D28
CSI2_DP9
A27
CSI2_DN10
B27
CSI2_DP10
C27
CSI2_DN11
D27
CSI2_DP11
SKL-U_BG A1356
@
SKL-U
HDA for AUDIO
HDA_SYNC_ R<30>
HDA_SDO UT_R<30>
HDA_BIT_C LK_R<30>
HDA_RST #_R<30>
SKL_ULT
9 OF 20
7 OF 20
ME_EN< 36>
HDA_SDIN0<30>
GPP_F13/EMMC_DATA0
GPP_F14/EMMC_DATA1
GPP_F15/EMMC_DATA2
GPP_F16/EMMC_DATA3
GPP_F17/EMMC_DATA4
GPP_F18/EMMC_DATA5
GPP_F19/EMMC_DATA6
GPP_F20/EMMC_DATA7
SDIO/SDXC
GPP_G1/SD_DATA0
GPP_G2/SD_DATA1
GPP_G3/SD_DATA2
GPP_G4/SD_DATA3
GPP_A17/SD_PWR_EN#/ISH_GP7
GPP_A16/SD_1P8_SEL
RPC9
1 8
2 7
3 6
4 5
33_0804 _8P4R_5%
1 2
RC77 0_0402_5%
Rev_0 .53
CSI2_CLKN0
CSI2_CLKP0
CSI2_CLKN1
CSI2_CLKP1
CSI2_CLKN2
CSI2_CLKP2
CSI2_CLKN3
CSI2_CLKP3
CSI2_COMP
GPP_D4/FLASHTRIG
EMMC
GPP_F21/EMMC_RCLK
GPP_F22/EMMC_CLK
GPP_F12/EMMC_CMD
EMMC_RCOMP
Rev_0 .53
GPP_G0/SD_CMD
GPP_G5/SD_CD#
GPP_G6/SD_CLK
GPP_G7/SD_WP
SD_RCOMP
GPP_F23
<BOM Struc ture>
HDA_SDO UT
HDA_BIT_C LK
HDA_RST #
HDA_SDO UT
@
HDA_SDIN0
C37
D37
C32
D32
C29
D29
B26
A26
CSI2_COMP
E13
DGPU_PR SNT#
B7
AP2
AP1
AP3
AN3
AN1
AN2
AM4
AM1
AM2
AM3
AP4
EMMC_RC OMP
AT1
/ /.
2)4 + 7* ' !? @ +
!+)4* 5' # $ ! '
'<* !<* A *B<
!)<*'" $+
AB11
*' !'<$ !
AB13
<* * '" $ + < =
AB12
W12
W11
W10
W8
W7
BA9
BB9
SD_RCOM P
AB7
AF13
RC80 100_040 2_1%<BOM Structu re>
RC89 200_040 2_1%
12
12
<BOM Struc ture>
RC76 2 00_0402_1%<BOM Struc ture>
12
+3VALW _1.8VALW _PGPPD
UMA@
DGPU_PR SNT#
VGA@
GPIO 67
DGPU_PRSNT#
DIS,Optimus10
UMA
12
RC133
10K_040 2_5%
12
RC134
10K_040 2_5%
4 4
Security Classification
Security Classification
Security Classification
2017/02/ 22 2018/02/ 22
2017/02/ 22 2018/02/ 22
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
2017/02/ 22 2018/02/ 22
C
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
SKL-U(4/12)HDA,EMMC,SDIO,CSI2
SKL-U(4/12)HDA,EMMC,SDIO,CSI2
SKL-U(4/12)HDA,EMMC,SDIO,CSI2
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Custom
Custom
Custom
LA-F241P
LA-F241P
LA-F241P
Date : Sheet o f
Friday, June 09, 201 7
Date : Sheet o f
Friday, June 09, 201 7
Date : Sheet o f
D
Friday, June 09, 201 7
9
9
9
E
0.1
0.1
0.1
54
54
54
A
+RTCVCC
1 2
RC91 2 0K_0402_5%
1 2
CC10 1 U_0402_6.3V6K
SOC_SRT CRST#
Remove CLR ME
1 2
1 1
RC93 2 0K_0402_5%
1 2
CC11 1 U_0402_6.3V6K
1 2
JCMOS1 0_ 0603_5%@
SOC_RTC RST#
CLR CMOS
N
GFF WL+BT(KEY E)
Place at RAM DOOR
1 2
RC94 1M_040 2_5%
+3VS
1 2
RC165 10K_040 2_5%
1 2
RC105 10K_040 2_5%
1 2
RC259 10K_040 2_5%
1 2
RC121 10K_040 2_5%
1 2
RC123 10K_040 2_5%
1 2
RC124 10K_040 2_5%
2 2
+3VALW _PRIM
+3VALW _DSW
CLKREQ_ PCIE#4
CLKREQ_ PCIE#5
CLKREQ_ PCIE#0
CLKREQ_ PCIE#1
CLKREQ_ PCIE#2
CLKREQ_ PCIE#3
RPC11
18
27
36
45
10K_080 4_8P4R_5%
Follow 54 3016_SKL_U_Y_PDG _0_9
+3VALW _DSW
1 2
RC103 10K_0 402_5%
1 2
RC104 1K_04 02_5%
1 2
@
RC106 10K_0 402_5%
+3VALW _PRIM
3 3
+3VALW _DSW
1 2
RC115 10K_0 402_5%@
RC111 100K_ 0402_5%@
12
+1.0V_VC CST
From EC(open-drain)
EC_VCCS T_PG_R<36,40>
4 4
A
SM_INTRUD ER#
PCH_PW ROK
EC_RSMR ST#
SYS_RESET #
LAN_PME #
Note for PCH_PWRO K
PDG1.0 Figure43-4 note2 0: PC H_PWROK
does not glitch when RSMRS T# is
de-as ser te d
PM_BATL OW#
PCH_PCIE_ WAKE#
AC_PRES ENT
SOC_VRA LERT#
#543016 PD G0.9 P.526
PROCPWRGD is used only for power sequence
debug and is not r equired to be connected to
anything on the platform.
C6:A@#DB
: E * = * ; C/-/
2$*=* )F*)'< G )<
*' $ < ) 4
H6%C6:,H6%CD')<)4$ I
PBTN_OU T#_R
Note for VCCST_PWRGD
1. 1.0V toleran ce
2. PDG1.0 Figure4 3-4 note17: when failure events ,
VCCST_PWRGD and PCH_PWROK de-assert at the same time
12
RC113
1K_0402 _5%
1 2
RC116 60.4_0 402_1%
CC51
.1U_0402 _16V7K
CC50
.1U_0402 _16V7K
EC_VCCS T_PG
@EMC@
SYS_RESET # SYS_PW ROK
12
@EMC@
H_CPUPW RGD
12
Reserved for ESD 2014/ 9/17
B
SSD
GLAN
AR
CR
WIGI G
EC_RSMR ST#<36>
PCH_PW ROK<36>
SUSPW RDNACK<36 >
PCH_PCIE_ WAKE#<28,33>
LAN_PME #<28 >
LAN_DISAB LE_N<28>
Close to UC1
CC436 .1U_0 402_16V7K
ESD@
20 17/4/18 for MB Field
lesson learnt ESD request
B
SYS_RESET #<6>
SYS_PW ROK<36>
12
CLK_PCIE_ N0<2 7>
CLK_PCIE_ P0<27>
CLKREQ_ PCIE#0<27>
CLK_PCIE_ N1<2 8>
CLK_PCIE_ P1<28>
CLKREQ_ PCIE#1<28>
CLK_PCIE_ N2<3 1>
CLK_PCIE_ P2<31>
CLKREQ_ PCIE#2<31>
CLK_PCIE_ N3<3 3>
CLK_PCIE_ P3<33>
CLKREQ_ PCIE#3<33>
CLK_PCIE_ CARD<38>
CLK_PCIE_ CARD#<38>
CLKREQ_ PCIE#4<38>
CLK_PCIE_ N5<3 1>
CLK_PCIE_ P5<31>
CLKREQ_ PCIE#5<31>
PLT_RST #<27,33,36 ,38>
T95 @
T89 @
T92
EC_VCCS T_PG
C
UC1J
CLK_PCIE_ N0
CLK_PCIE_ P0
CLKREQ_ PCIE#0
CLK_PCIE_ N1
CLK_PCIE_ P1
CLKREQ_ PCIE#1
CLK_PCIE_ N2
CLK_PCIE_ P2
CLKREQ_ PCIE#2
CLK_PCIE_ N3
CLKREQ_ PCIE#3
CLK_PCIE_ CARD
CLK_PCIE_ CARD#
CLKREQ_ PCIE#4
CLK_PCIE_ N5
CLK_PCIE_ P5
CLKREQ_ PCIE#5
D42
CLKOUT_PCIE_N0
C42
CLKOUT_PCIE_P0
AR10
GPP_B5/SRCCLKREQ0#
B42
CLKOUT_PCIE_N1
A42
CLKOUT_PCIE_P1
AT7
GPP_B6/SRCCLKREQ1#
D41
CLKOUT_PCIE_N2
C41
CLKOUT_PCIE_P2
AT8
GPP_B7/SRCCLKREQ2#
D40
CLKOUT_PCIE_N3
C40
CLKOUT_PCIE_P3
AT10
GPP_B8/SRCCLKREQ3#
B40
CLKOUT_PCIE_N4
A40
CLKOUT_PCIE_P4
AU8
GPP_B9/SRCCLKREQ4#
E40
CLKOUT_PCIE_N5
E38
CLKOUT_PCIE_P5
AU7
GPP_B10/SRCCLKREQ5#
S
KL-U_BGA 1356
@
PCH PLTRST Buffer
PLT_RST #
UC1K
SYSTEM POWER MANAGEMENT
PLT_RST #
SYS_RESET #
EC_RSMR ST#
H_CPUPW RGD
EC_VCCS T_PG
SYS_PW ROK
PCH_PW ROK
PCH_DPW ROK
SUSPW RDNACK
@
SUSACK#
PCH_PCIE_ WAKE#
LAN_PME #
LAN_DISAB LE_N
AN10
GPP_B13/PLTRST#
B5
SYS_RESET#
AY17
RSMRST#
A68
PROCPWRGD
B65
VCCST_PWRGD
B6
SYS_PWROK
BA20
PCH_PWROK
BB20
DSW_PWROK
AR13
GPP_A13/SUSWARN#/SUSPWRDNACK
AP11
GPP_A15/SUSACK#
BB15
WAKE#
AM15
GPD2/LAN_WAKE#
AW17
GPD11/LANPHYPC
AT15
GPD7/RSVD
S
KL-U_BGA 1356
@
PBTN_OU T#<6,36>
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2017/02/ 22 2018/02/ 22
2017/02/ 22 2018/02/ 22
2017/02/ 22 2018/02/ 22
C
2
<BOM Struc ture>
1
UC3
MC74VHC 1G08DFT2G_SC 70-5
RC125 0_040 2_5%
RC109 0_040 2_5%
EC_RSMR ST# PCH_DPW ROK
RC122 0_040 2_5%
RC110 10K_0 402_5%<BOM Structu re>
SKL_ULT
CLOCK SIGNALS
10 OF 20
RC248 0_0 402_5%
12
@
12
RC249 0_0 402_5%
5
P
B
A
@
SKL-U
11 OF 20
PLT_RST _BUF#
4
Y
G
3
12
GPP_B11/EXT_PWR_GATE#
PBTN_OU T#_R
12
@
12
@
RC1140_ 0402_5%
PCH_PW ROKSYS_PWROK
12
@
1 2
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
+3VM
+3VS
12
R157
100K_04 02_5%
GPP_B12/SLP_S0#
GPD4/SLP_S3#
GPD5/SLP_S4#
GPD10/SLP_S5#
SLP_SUS#
SLP_LAN#
GPD9/SLP_WLAN#
GPD6/SLP_A#
GPD3/PWRBTN#
GPD1/ACPRESENT
GPD0/BATLOW#
GPP_A11/PME#
INTRUDER#
GPP_B2/VRALERT#
D
Rev_0 .53
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P
GPD8/SUSCLK
XTAL24_IN
XTAL24_OUT
XCLK_BIASREF
RTCX1
RTCX2
SRTCRST#
RTCRST#
PLT_RST _BUF# <27,28,31>
Rev_0 .53
AT11
AP15
BA16
AY16
AN15
AW15
BB17
AN16
BA15
AY15
AU13
AU11
AP16
AM10
AM11
D
PM_SLP_ S0#
PM_SLP_ S3#
PM_SLP_ S4#
PM_SLP_ S5#
SLP_SUS #
SLP_LAN #
SLP_W LAN#
PM_SLP_ A#
PBTN_OU T#_R
AC_PRES ENT
PM_BATL OW#
SM_INTRUD ER#
EXT_PW R_GATE#
SOC_VRA LERT#
F43
E43
BA17
E37
E35
E42
AM18
AM20
AN18
AM16
CLK_CPU _ITP#
CLK_CPU _ITP
SUSCLK
SOC_XTA L24_IN
SOC_XTA L24_OUT
XCLK_BIAS REFCLK_PCIE_ P3
SOC_RTC X1
SOC_RTC X2
SOC_SRT CRST#
SOC_RTC RST#
SLP_W LAN# <36>
PM_SLP_ A# <6,36>
Title
Title
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Custom
Custom
Custom
Date : Sheet o f
Date : Sheet o f
Date : Sheet o f
T164 @
T165 @
SUSCLK <27,31>
1 2
RC96 2 .7K_0402_1%<BOM Struc ture>
1 2
RC136 60.4_040 2_1%
SOC_RTC RST# <6>
T84@
T85@
PM_SLP_ S0# <6>
PM_SLP_ S3# <6,36 ,40>
PM_SLP_ S4# <6,36 ,40>
PM_SLP_ S5# <6>
T86@
T90@
SLP_LAN # < 36>
AC_PRES ENT <36>
T91@
T93@
CC15
8.2P_040 2_50V8D
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
SKL-U(5/12)CLK,GPIO
SKL-U(5/12)CLK,GPIO
SKL-U(5/12)CLK,GPIO
LA-F241P
LA-F241P
LA-F241P
Follow 2014MOW48
S
kylake U PU 2.7k o hm to 1V
Cannonlake U PD 60. 4 ohm
X
CLK_B IAS RE F
T:50ohm S:12/15 L:1000 Via:2
@
SOC_XTA L24_IN
SOC_XTA L24_OUT
12
0_0201_ 5%
U22@
RC252
RC92 1M_0402 _5%
SOC_XTA L24_OUT_R
3
3
CC12
15P_0402_50V8J
12
U22@
2014M OW 48:
Skylake U use 24M 50 ohm
ESR
Cannonlake U use 38.4M 3 0
ohm ESR
SOC_RTC X2
SOC_RTC X1
1 2
RC98 10 M_0402_5%
1 2
32.768KH Z_9PF_X1A000 141000200
Change PN to SJ10000PW0 0
1
CC16
8.2P_040 2_50V8D
2
E
+1.0VALW _CLK5_F24 NS
U22@
0_0201_ 5%
RC251
U22@
GND
4
U22@
SOC_XTA L24_IN_R
1
GND
U22@
2
1
2
10 54Friday, June 09, 2017
10 54Friday, June 09, 2017
10 54Friday, June 09, 2017
1 2
YC1
24MHZ_1 2PF_7V240000 20
<BOM Struc ture>
YC2
E
12
1
CC13
15P_0402_50V8J
12
0.1
0.1
0.1
A
B
C
D
E
# 543016 SKY PDG 0.9 P.401
UC1F
LPSS ISH
GPP_B15/GSPI0_CS#
GPP_B16/GSPI0_CLK
GPP_B17/GSPI0_MISO
GPP_B18/GSPI0_MOSI
GPP_B19/GSPI1_CS#
GPP_B20/GSPI1_CLK
GPP_B21/GSPI1_MISO
GPP_B22/GSPI1_MOSI
GPP_C8/UART0_RXD
GPP_C9/UART0_TXD
GPP_C10/UART0_RTS#
GPP_C11/UART0_CTS#
GPP_C20/UART2_RXD
GPP_C21/UART2_TXD
GPP_C22/UART2_RTS#
GPP_C23/UART2_CTS#
GPP_C16/I2C0_SDA
GPP_C17/I2C0_SCL
GPP_C18/I2C1_SDA
GPP_C19/I2C1_SCL
GPP_F4/I2C2_SDA
GPP_F5/I2C2_SCL
GPP_F6/I2C3_SDA
GPP_F7/I2C3_SCL
GPP_F8/I2C4_SDA
GPP_F9/I2C4_SCL
KL-U_BGA1356
X76OBRAM@
1 2
RC215 10K_0402_5%
1 2
RC216 10K_0402_5%
X76OBRAM@
1 2
RC217 10K_0402_5%SR@
1 2
RC218 10K_0402_5%DR@
GPP_D9
GL
GM
0
1
GPP_D10
DR
SR
0
1
T3815@
T111@
T114@
T112@
T3823@
NFC_DFU
GC6_FB_EN_R
GSPI0_MOSI
EC_LID_OUT#
GSPI1_MOSI
SOC_AC_DET
GPU_EVENT_R#
UART_2_CRXD_DTXD
UART_2_CTXD_DRXD
UART_2_CRTS_DCTS
UART_2_CCTS_DRTS
I2C_0_SDA
I2C_0_SCL
I2C_1_SDA
I2C_1_SCL
I2C_2_SDA
I2C_2_SCL
I2C_3_SDA
I2C_3_SCL
I2C_4_SDA
I2C_4_SCL
NFC_DFU follow PDG 1.3
1 1
NFC_DFU<27>
DGPU_A C_DETECT
T3814@
UART_2_CRXD_DTXD<31>
UART_2_CTXD_DRXD<31>
T141 @
T142 @
T140 @
no use
no use
no use
2 2
T143 @
T135 @
T134 @
T131 @
T130 @
T128 @
T129 @
Functional Strap Definitions
SPKR / GPP_B14 (Internal Pull Down):
(Sampled:Rising edge of PCH_PWROK)
TOP Swap Override
0 = Disable TOP Swap mode.---> AAX05 Use
*
1 = Enable TOP Swap Mode.
GSPI0_MOSI /GPP_B18 (Internal Pull Down):
(Rising edge of PCH_PWROK)
No Reboot
0 = Disable No Reboot mode. --> AAX05 Use
*
1 = Enable No Reboot Mode. (PCH will disable the TCO
Timer system reboot feature). This function is useful
when running ITP/XDP.
3 3
GSPI1_MOSI / GPP_B22 (Internal Pull Down):
(Rising edge of PCH_PWROK)
Boot BIOS Strap Bit
0 = SPI Mode --> AAX05 Use
*
1 = LPC Mode
SML0ALERT# / GPP_C5 (Internal Pull Down):
(Sampled: Rising edge of RSMRST# )
eSPI or LPC
0 = LPC is selected for EC --> For KB9022/9032 Use
*
1 = eSPI is selected for EC --> For KB9032 Only.
D4PB1/D5PB1
Change to
On Borad Ram ID
Page. 19
AN8
AP7
AP8
AR7
AM5
AN7
AP5
AN5
AB1
AB2
W4
AB3
AD1
AD2
AD3
AD4
U7
U6
U8
U9
AH9
AH10
AH11
AH12
AF11
AF12
S
@
VGA_ID
RANK_ID
VGA_ID
RANK_ID
SKL-U
GPP_D5/ISH_I2C0_SDA
GPP_D7/ISH_I2C1_SDA
GPP_F10/I2C5_SDA/ISH_I2C2_S DA
GPP_F11/I2C5_SCL/ISH_I2C2_SC L
GPP_D13/ISH_UART0_RX D/SML0BDATA/I2C4B_SDA
GPP_D14/ISH_UART0_TXD /SML0BCLK/I2C4B_SCL
GPP_D16/ISH_UART0_CT S#/SML0BALERT#
6 OF 20
+3VALW_1.8VALW_ PGPPD +3VALW_1.8VALW_ PGPPD
GPP_D15/ISH_UART0_RT S#
GPP_C12/UART1_RXD /ISH_UART1_RXD
GPP_C13/UART1_TXD/ ISH_UART1_TXD
GPP_C14/UART1_RTS# /ISH_UART1_RTS#
GPP_C15/UART1_CTS# /ISH_UART1_CTS#
GPP_A12/BM_BUSY#/ ISH_GP6
PROJECT_ID0
PROJECT_ID1
Project ID
*
B4DBU+VPRO
B4DBU+NVPRO
Reserved
Reserved
Rev_0. 53
P2
GPP_D9
P3
GPP_D10
P4
GPP_D11
P1
GPP_D12
M4
NOVPRO@
1 2
VPRO@
1 2
N3
N1
N2
AD11
AD12
U1
U2
U3
U4
AC1
AC2
AC3
AB4
AY8
BA8
BB7
BA7
AY7
AW7
AP13
12
12
GPP_D6/ISH_I2C0_SCL
GPP_D8/ISH_I2C1_SCL
GPP_A18/ISH_GP0
GPP_A19/ISH_GP1
GPP_A20/ISH_GP2
GPP_A21/ISH_GP3
GPP_A22/ISH_GP4
GPP_A23/ISH_GP5
RC207 10K_0402_5%
RC210 10K_0402_5%
RC211 10K_0402_5%@
RC213 10K_0402_5%
0 0
0
1
1 1
VGA_ID
RANK_ID
PROJECT_ID0
PROJECT_ID1
ISH_I2C0_SDA
ISH_I2C0_SCL
ISH_I2C1_SDA
ISH_I2C1_SCL
I2C_5_SDA
I2C_5_SCL
SOC_GPIOD13
SOC_GPIOD14
SOC_GPIOD15
SOC_GPIOD16
DGPU_PWR_EN
DGPU_HOLD_RST#
GPU_OVERT
GPU_ALERT
RAM_FLAG0
RAM_FLAG1
G_INT
ALS_INT#
NFC_DET#
MINI_DET#
Project_ID0Project_ID1
GPP_D11GPP_D12
1
0
I
(Reserve for Verify)
T105 @
T106 @
T107 @
T108 @
T113 @
T110 @
SH sensor HUB
no use
no use
T3819@
T3820@
T3812@
T3813@
RAM_FLAG0 <19>
RAM_FLAG1 <19>
G_INT <26>
T3849@
T115 @
NFC_DET# <27>
MINI_DET# <31>
I2C/ISH Port(From PDG 0.9)
MINI_DET#
NFC_DET#
ISH_I2C1_SCL
ISH_I2C1_SDA
ISH_I2C0_SCL
ISH_I2C0_SDA
UART_2_CRXD_DTXD
UART_2_CTXD_DRXD
UART_2_CRTS_DCTS
UART_2_CCTS_DRTS
+1.8VS_3VS_PGPPA
RPC12
1 8
2 7
3 6
4 5
10K_0804_8P4R_5%
RPC19
1 8
2 7
3 6
4 5
@
1K_0804_8P4R_5%
1 2
RC62 49.9K_0402_1%
1 2
RC63 49.9K_0402_1%
1 2
RC64 49.9K_0402_1%
1 2
RC65 49.9K_0402_1%
+3VALW_1.8VALW_ PGPPD
<BOM Structure>
<BOM Structure>
@
@
RC177
0_0402_5% ESPI@
RC178
0_0402_5% @
+3VS
+3VS
+1.8VS
12
12
SMBALERT# / GPP_C2 (Internal Pull Down):
Sampled: Rising edge of RSMRST# )
(
TLS Confidentiality
0 = Disable Intel ME Crypto Transport Layer Security
4 4
*
(TLS) cipher suite (no confidentiality).
1 = Enable Intel ME Crypto (TLS) (with confidentiality).
Must be pulled up to support Intel AMT with TLS and Intel
SBA (Small Business Advantage) with TLS.
A
HDA_SDO/I2S_TXD0 (Internal Pull Down):
(Sampled: Rising edge of PCH_PWROK )
Flash Descriptor Security Override
0 = Enable security measures defined in the Flash
Descriptor.
1 = Disable Flash Descriptor Security (override). This
strap should only be asserted high using external
pull-up in manufacturing/debug environments ONLY.
B
DDPB_CTRLDATA/ GPP_E19 (Internal Pull Down):
DDPC_CTRLDATA/ GPP_E21 (Internal Pull Down):
DDPD_CTRLDATA/ GPP_E23 (Internal Pull Down):
(Sampled:Rising edge of PCH_PWROK)
Display Port B/C/D Detected
0 =Port D is not detected.
1 =Port D is detected.
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTYW ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTYW ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTYW ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2017/02/22 2018/02/22
2017/02/22 2018/02/22
2017/02/22 2018/02/22
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
SKL-U(6/12)GPIO
SKL-U(6/12)GPIO
SKL-U(6/12)GPIO
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Custom
Custom
Custom
LA-F241P
LA-F241P
LA-F241P
Date : Shee t of
Date : Shee t of
D
Date : Shee t of
E
11 54Wednesday, June 14, 2017
11 54Wednesday, June 14, 2017
11 54Wednesday, June 14, 2017
0.1
0.1
0.1
A
1 1
PCIE_CRX_DTX_N4<38>
CR
GLAN
NGFF WLAN+BT(Key E)
HDD
2 2
Wigi g
Thunde rbol t
#543016 P.239 PCIE_RCOMPN/PCIE_RCOMPP
BO=4 W=12 S=12 R=100ohm
SSD
+3VALW _PRIM
3 3
RC135
@
10K_040 2_5%
12
PIRQA#
PCIE_CRX_DTX_P4<38>
PCIE_CTX_ C_DRX_N4<38>
PCIE_CTX_ C_DRX_P4<38>
PCIE_CRX_DTX_N5<28>
PCIE_CRX_DTX_P5<28>
PCIE_CTX_ C_DRX_N5<28>
PCIE_CTX_ C_DRX_P5<28>
PCIE_CRX_DTX_N6<31>
PCIE_CRX_DTX_P6<31>
PCIE_CTX_ C_DRX_N6<31>
PCIE_CTX_ C_DRX_P6<31>
SATA_CR X_DTX_N0<2 6>
SATA_CR X_DTX_P0<26>
SATA_CT X_DRX_N0<2 6>
SATA_CT X_DRX_P0<26>
PCIE_CRX_ GTX_N8<31>
PCIE_CRX_ GTX_P8<31>
PCIE_CTX_ C_GRX_N8<31>
PCIE_CTX_ C_GRX_P8<31>
PCIE_CRX_ GTX_N9<33>
PCIE_CRX_ GTX_P9<33>
PCIE_CTX_ C_GRX_N9<33>
PCIE_CTX_ C_GRX_P9<33>
PCIE_CRX_ GTX_N10<33>
PCIE_CRX_ GTX_P10<3 3>
PCIE_CTX_ C_GRX_N10<33>
PCIE_CTX_ C_GRX_P10<33>
PCIE_CRX_DTX_N11<27>
PCIE_CRX_DTX_P11<27>
PCIE_CTX_ DRX_N11<2 7>
PCIE_CTX_ DRX_P11<27>
PCIE_CRX_DTX_N12<27>
PCIE_CRX_DTX_P12<27>
PCIE_CTX_ DRX_N12<2 7>
PCIE_CTX_ DRX_P12<27>
CC90 0.22U_04 02_16V7KTBT@
CC89 0.22U_04 02_16V7KTBT@
CC93 0.22U_04 02_16V7KTBT@
CC92 0.22U_04 02_16V7KTBT@
6)!'<
4 4
A
B
12
CC433 .1U_04 02_16V7K
12
CC434 .1U_04 02_16V7K
12
CC25 .1U_0402_ 16V7K
12
CC26 .1U_0402_ 16V7K
1 2
C3803 .1U_0402_1 6V7K
1 2
C3804 .1U_0402_1 6V7K
12
CC108 .1U_04 02_16V7K
12
CC109 .1U_04 02_16V7K
1 2
1 2
1 2
1 2
1 2
RC120 100_0 402_1%
T3824@
T3846@
B
PCIE_CRX_ DTX_N4
PCIE_CRX_ DTX_P4
PCIE_CTX_ DRX_N4
PCIE_CTX_ DRX_P4
PCIE_CRX_ DTX_N5
PCIE_CRX_ DTX_P5
PCIE_CTX_ DRX_N5
PCIE_CTX_ DRX_P5
PCIE_CRX_ DTX_N6
PCIE_CRX_ DTX_P6
PCIE_CTX_ DRX_N6
PCIE_CTX_ DRX_P6
PCIE_CRX_ GTX_N8
PCIE_CRX_ GTX_P8
PCIE_CTX_ GRX_N8
PCIE_CTX_ GRX_P8
PCIE_CRX_ GTX_N9
PCIE_CRX_ GTX_P9
PCIE_CTX_ GRX_N9
PCIE_CTX_ GRX_P9
PCIE_CRX_ GTX_N10
PCIE_CRX_ GTX_P10
PCIE_CTX_ GRX_N10
PCIE_CTX_ GRX_P10
PCIE_RCOM PN
PCIE_RCOM PP
XDP_PRD Y#
XDP_PRE Q#
PIRQA#
PCIE_CRX_ DTX_N11
PCIE_CRX_ DTX_P11
PCIE_CTX_ DRX_N11
PCIE_CTX_ DRX_P11
PCIE_CRX_ DTX_N12
PCIE_CRX_ DTX_P12
PCIE_CTX_ DRX_N12
PCIE_CTX_ DRX_P12
C
UC1H
PCIE/US B3/SATA
H13
PCIE1_RXN/USB3_5_RXN
G13
PCIE1_RXP/USB3_5_RXP
B17
PCIE1_TXN/USB3_5_TXN
A17
PCIE1_TXP/USB3_5_TXP
G11
PCIE2_RXN/USB3_6_RXN
F11
PCIE2_RXP/USB3_6_RXP
D16
PCIE2_TXN/USB3_6_TXN
C16
PCIE2_TXP/USB3_6_TXP
H16
PCIE3_RXN
G16
PCIE3_RXP
D17
PCIE3_TXN
C17
PCIE3_TXP
G15
PCIE4_RXN
F15
PCIE4_RXP
B19
PCIE4_TXN
A19
PCIE4_TXP
F16
PCIE5_RXN
E16
PCIE5_RXP
C19
PCIE5_TXN
D19
PCIE5_TXP
G18
PCIE6_RXN
F18
PCIE6_RXP
D20
PCIE6_TXN
C20
PCIE6_TXP
F20
PCIE7_RXN/SATA0_RXN
E20
PCIE7_RXP/SATA0_RXP
B21
PCIE7_TXN/SATA0_TXN
A21
PCIE7_TXP/SATA0_TXP
G21
PCIE8_RXN/SATA1A_RXN
F21
PCIE8_RXP/SATA1A_RXP
D21
PCIE8_TXN/SATA1A_TXN
C21
PCIE8_TXP/SATA1A_TXP
E22
PCIE9_RXN
E23
PCIE9_RXP
B23
PCIE9_TXN
A23
PCIE9_TXP
F25
PCIE10_RXN
E25
PCIE10_RXP
D23
PCIE10_TXN
C23
PCIE10_TXP
F5
PCIE_RCOMPN
E5
PCIE_RCOMPP
D56
PROC_PRDY#
D61
PROC_PREQ#
BB11
GPP_A7/PIRQA#
E28
PCIE11_RXN/SATA1B_RXN
E27
PCIE11_RXP/SATA1B_RXP
D24
PCIE11_TXN/SATA1B_TXN
C24
PCIE11_TXP/SATA1B_TXP
E30
PCIE12_RXN/SATA2_RXN
F30
PCIE12_RXP/SATA2_RXP
A25
PCIE12_TXN/SATA2_TXN
B25
PCIE12_TXP/SATA2_TXP
S
KL-U_BGA 1356
@
GPI O
USB_ OC0 #
USB_ OC1 #
USB_ OC2 #
USB_ OC3 #
DEVS LP0
DEVS LP1
DEVS LP2
SATA _GP 0
SATA _GP 1
SATA _GP 2
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2017/02/ 22 2018/02/ 22
2017/02/ 22 2018/02/ 22
2017/02/ 22 2018/02/ 22
C
SKL-U
SSIC / USB3
USB2
GPP_E0/SATAXPCIE0/SATAGP0
GPP_E1/SATAXPCIE1/SATAGP1
GPP_E2/SATAXPCIE2/SATAGP2
8 OF 20
DEVICE CONTROL
USB Port 1,2,4
NA
NA
NFC
NA
NA
SSD
NA
NA
NA
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
USB3_2_RXN/SSIC_1_RXN
USB3_2_RXP/SSIC_1_RXP
USB3_2_TXN/SSIC_1_TXN
USB3_2_TXP/SSIC_1_TXP
USB3_3_RXN/SSIC_2_RXN
USB3_3_RXP/SSIC_2_RXP
USB3_3_TXN/SSIC_2_TXN
USB3_3_TXP/SSIC_2_TXP
USB2_VBUSSENSE
GPP_E9/USB2_OC0#
GPP_E10/USB2_OC1#
GPP_E11/USB2_OC2#
GPP_E12/USB2_OC3#
GPP_E4/DEVSLP0
GPP_E5/DEVSLP1
GPP_E6/DEVSLP2
GPP_E8/SATALED#
Rev_0 .53
USB3_1_RXN
USB3_1_RXP
USB3_1_TXN
USB3_1_TXP
USB3_4_RXN
USB3_4_RXP
USB3_4_TXN
USB3_4_TXP
USB2N_1
USB2P_1
USB2N_2
USB2P_2
USB2N_3
USB2P_3
USB2N_4
USB2P_4
USB2N_5
USB2P_5
USB2N_6
USB2P_6
USB2N_7
USB2P_7
USB2N_8
USB2P_8
USB2N_9
USB2P_9
USB2N_10
USB2P_10
USB2_COMP
USB2_ID
D
H8
G8
C13
D13
J6
H6
B13
A13
J10
H10
B15
A15
E10
F10
C15
D15
USB20_N 1
AB9
USB20_P 1
AB10
USB20_N 2
AD6
USB20_P 2
AD7
USB20_N 3
AH3
USB20_P 3
AJ3
USB20_N 4
AD9
USB20_P 4
AD10
USB20_N 5
AJ1
USB20_P 5
AJ2
USB20_N 6
AF6
USB20_P 6
AF7
USB20_N 7
AH1
USB20_P 7
AH2
USB20_N 8
AF8
USB20_P 8
AF9
USB20_N 9
AG1
USB20_P 9
AG2
USB20_N 10
AH7
USB20_P 10
AH8
USB2_CO MP
AB6
USB2_ID
AG3
USB2_VB USSENSE
AG4
USB_OC0 #
A9
USB_OC1 #
C9
D9
NFC_IRQ
B9
NFC_RST #
J1
J2
J3
DEVSLP2
H2
H3
G4
PCH_SAT ALED#
H1
Close to UC1
20 17/4/18 for MB Field
lesson learnt ESD request
DEVSLP[2:0] Implementation
DEVSLP is a host-controlled hardware signal which enables a SATA host and device to
enter an ultra-low interface power state, including the possibility to completely power
down host and device PHYs.
The processor provides three SATA DEVSLP signals, DEVSLP[2:0] for SKL U.
When high, DEVSLP requests the SATA device to enter into the DEVSLP power state.
‧
When low, DEVSLP requests the SATA device to exit from the DEVSLP power state
‧
and transition to active state.
SATA General Purpose (SATAGP[2:0]) Signals
The processor provides three SATA general purpose input signals,SATAGP[2:0] for SKL U.
‧
These signals can be configured as interlock switch inputs corresponding to a given SATA port.
When used as an interlock switch status indication, this signal should be driven to 0
‧
to indicate that the switch is closed and to a 1 to indicate that the switch is open.
If mechanical presence switches will not be used on the platform, SATAGP[2:0]
‧
signals can be configured as GPP_E[2:0] GPIOs signals.
D
T3821 @
T3822 @
RC119 113_0 402_1%
RC130 0_040 2_5%
RC131 0_040 2_5%
1 2
RC258 10K_0 402_5%
SATAXPC IE1
Title
Title
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Custom
Custom
Custom
Date : Sheet o f
Date : Sheet o f
Date : Sheet o f
E
PCH_USB 3_RX1_N <32>
PCH_USB 3_RX1_P <32 >
PCH_USB 3_TX1_N <32>
PCH_USB 3_TX1_P <32>
PCH_USB 3_RX2_N <32>
PCH_USB 3_RX2_P <32 >
PCH_USB 3_TX2_N <32>
PCH_USB 3_TX2_P <32>
PCH_USB 3_RX3_N <37>
PCH_USB 3_RX3_P <37 >
PCH_USB 3_TX3_N <37>
PCH_USB 3_TX3_P <37>
PCH_USB 3_RX4_N <32>
PCH_USB 3_RX4_P <32 >
PCH_USB 3_TX4_N <32>
PCH_USB 3_TX4_P <32>
USB20_N 1 <32>
USB20_P 1 < 32>
USB20_N 2 <32>
USB20_P 2 < 32>
USB20_N 3 <37>
USB20_P 3 < 37>
USB20_N 4 <32>
USB20_P 4 < 32>
USB20_N 5 <31>
USB20_P 5 < 31>
IO/B
USB3 MB
DOCKING
IO/B
IO/B
USB3 MB
DOCKING
IO/B
BT
NFC
USB20_N 7 <21>
USB20_P 7 < 21>
USB20_N 8 <38>
USB20_P 8 < 38>
USB20_N 9 <31>
USB20_P 9 < 31>
USB20_N 10 <21>
USB20_P 10 <21>
1 2
1 2
1 2
USB_OC0 # <32>
T166 @
NFC_IRQ <27>
NFC_RST # <27>
DEVSLP2 < 27>
PCH_SAT ALED# <38>
USB_OC0 #
CC435 .1U_04 02_16V7K
ESD@
PCH_SAT ALED#
NFC_RST #
DEVSLP2
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
SKL-U(7/12)PCIE,USB,SATA
SKL-U(7/12)PCIE,USB,SATA
SKL-U(7/12)PCIE,USB,SATA
LA-F241P
LA-F241P
LA-F241P
Camera
FP
LTE
TS
AG3,AG4 PD1K for DCI
w
arm boot fail issue
(follow PCH ED S1.2)
2015MOW10, USB2_ID
NFC_IRQ,RST# foll ow PDG 1.3
12
connected to GND
+3VS
SATAXPC IE1 <27>
1 2
RC132 10K_0 402_5%
1 2
RC139 10K_0 402_5%
1 2
RC138 10K_0 402_5%
1 2
RC201 10K_0 402_5%
E
12 54Friday, June 09, 2017
12 54Friday, June 09, 2017
12 54Friday, June 09, 2017
+3VALW _PRIM
+3VS
0.1
0.1
0.1
A
B
C
D
E
+1.0VALW_PRIM TO +1.0V_VCCSTU / +1.0VCCST
+5VALW
1
@
2
EN_1.0V_ VCCSTU
EN_1.8VS
+1.8VALW _VS
1
@
2
VOUT
VOUT
VIN
VOUT
VIN
ON
VBIAS
1U_0402_6.3V6K
CC97
UC5
1
VIN1
2
VIN1
3
ON1
4
VBIAS
5
ON2
6
VIN2
7
VIN2
1U_0402_6.3V6K
CC99
EM5209V F_DFN14_2X3
VOUT1
VOUT1
CT1
GND
CT2
VOUT2
VOUT2
GPAD
14
13
12
11
10
9
8
15
+1.8VALW_PRIM TO +1.8VS
VCCSTG and VCCIO SLEW RATE <=65us
1 2
RC188 0_04 02_5%
@
112
JUMP_43 X79
GND
GND
GND
CT
+1.0VS_V CCSTG_IO
6
5
7
8
1 2
6
5
9
PSC SideBSC Side
+1.0VS_V CCSTG_IO
C977
1000P_0 402_50V7K
@
1U_0402_6.3V6K
CC98
1
2
1 1
SYSON<32,36,40,45>
SUSP#<33,36,37,40 ,45>
2 2
+1.0VALW _PRIM
Imax : 2.77 A
For Power consu mption
Measu rement
CC107
.1U_0402 _16V7K
12
@
SUSP#
3 3
+VCCIO
CC105 .1U_0402 _16V7K
RC142 20K_0 402_5%
JPC4
2
112
JUMP_43 X79
@
+5VALW
1 2
@
RC186 0_04 02_5%
12
1 2
1 2
@
RC168 0_04 02_5%
12
CC104
1U_0402 _6.3V6K@
+1.8VALW _PRIM
112
JPC8
JUMP_43 X39
@
2
+1.0VALW_PRIM TO +1.0VS_VCCSTG
+1.0VALW _PRIM_JP
1U_0402_6.3V6K
CC117
1
<BOM Struc ture>
2
SUSP#_R 1
@
UC6
1
VIN1
2
VIN2
7
VIN thermal
3
VBIAS
4
ON
1U_0402_6.3V6K
CC106
1
TPS2296 1DNYR_WSON8
2
+1.0VALW _PRIM_JP
SUSP#_R 1
+5VALW
U4902
1
2
3
4
AOZ1336 _DFN8_2X2
@
+1.0V_VC CSTU+1.0VALW _PRIM
1 2
CC95
1000P_0 402_50V7K
1 2
CC94
1000P_0 402_50V7K
+1.0VS_V CCSTG
@
J16
2
Imax : 2.73 A
1
2
+1.8VS
1
2
+VCCIO
CC96
.1U_0402 _16V7K
CC100
.1U_0402 _16V7K
+1.2V_VD DQ
For Power consu mption
Measu rement
JPC1
1 2
@
JUMP_43 X118
JPC2
1 2
@
JUMP_43 X118
+1.2V_VD DQC
+1.0V_VC CST
+1.0VS_V CCSTG
+1.2V_VC CSFR_OC
+1.0V_VC CSFR
CC37
1
2
+1.2V_VD DQC
+1.0V_VC CSFR
+1.2V_VC CSFR_OC
22U_0603_6.3V6M
CC41
+1.2V_VD DQ_CPU
1 2
@
RC208 0_04 02_5%
+1.0V_VC CSTU +1.0V_VC CST
1 2
@
RC140 0_0 402_5%
1 2
@
RC143 0_0 402_5%
+1.2V_VD DQ_CPU
1 2
@
RC141 0_0 402_5%
+1.0VS_V CCSTG
+1.2V_VD DQ_CPU
22U_0603_6.3V6M
1
2
+1.2V_VD DQ_CPU
AU23
AU28
AU35
AU42
BB23
BB32
BB41
BB47
BB51
AM40
A18
A22
AL23
K20
K21
UC1N
VDDQ_AU23
VDDQ_AU28
VDDQ_AU35
VDDQ_AU42
VDDQ_BB23
VDDQ_BB32
VDDQ_BB41
VDDQ_BB47
VDDQ_BB51
VDDQC
VCCST
VCCSTG_A22
VCCPLL_OC
VCCPLL_K20
VCCPLL_K21
S
KL-U_BGA 1356
@
PSC Side
1 2
CC47 10U_060 3_6.3V6M
CC48
<BOM Struc ture>
PSC Side
1 2
1U_0402 _6.3V6K
<BOM Struc ture>
PSC Side
1 2
CC55 1U_0402 _6.3V6K
CC49 1U_0402 _6.3V6K
B
SC Side
1 2
<BOM Struc ture>
<BOM Struc ture>
BSC Side
1 2
CC56 1U_0402 _6.3V6K
22U_0603_6.3V6M
1
2
@
10U_0603_6.3V6M
CC54
1
2
10U_0603_6.3V6M
1
CC38
2
CPU POWER 3 OF 4
0.0 9A
0.0 4A
1
CC39
2
SKL-U
6.3 5A
0.0 4A
0.2 6A
0.1 2A
14 OF 20
543016_S KL_P DG_1 _0
+1.35V_VDDQC : 1x 1uF 0201 (Placeholder)
543016_S KL_P DG_1 _0
+1.0V_VCCST : 1x 1uF 0402
543016_S KL_P DG_1 _0
+1.0V_VCCSFR : 1x 1uF 0402
543016_S KL_P DG_1 _0
+1.35V_VCCSFR_OC : 1x 1uF 0201
543016_S KL_P DG_1 _0
+1.0VS_VCCSTG : 1x 1uF 0402 (Placeholder)
Rev_0 .53
VCCIO
VCCIO
2.7 3A
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
6A
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCIO_SENSE
VSSIO_SENSE
VSSSA_SENSE
VCCSA_SENSE
+VCCIO
AK28
AK30
AL30
AL42
AM28
AM30
AM42
AK23
AK25
G23
G25
G27
G28
J22
J23
J27
K23
K25
K27
K28
K30
VCCIO_SEN SE
AM23
VSSIO_SEN SE
AM22
VSSSA_S ENSE
H21
VCCSA_S ENSE
H20
1x 10uF 0402
+VCC_SA
BSC SidePSC Side
10U_0603_6.3V6M
10U_0603_6.3V6M
1
1
CC42
CC40
@
2
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
CC44
CC43
@
@
2
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1
CC46
CC45
@
2
T124 @
T125 @
VSSSA_S ENSE <48>
VCCSA_S ENSE <4 8>
22U_0603_6.3V6M
22U_0603_6.3V6M
CC59
CC58
1
1
4 4
@
@
2
2
543016_S KL_P DG_1 _0
VCCIO : 2x10uF 0402 (Placeholder)
+
1
@
2
4x 1uF 0201 (Placeholder)
4x 1uF 0402
10U_0603_6.3V6M
10U_0603_6.3V6M
1
1
CC28
CC27
@
@
2
2
A
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
CC30
CC29
@
@
2
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1
CC31
@
2
1U_0402_6.3V6K
1
1
CC32
CC33
2
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1
CC34
2
B
1U_0402_6.3V6K
1
CC35
CC36
2
Security Classification
Security Classification
Security Classification
2017/02/ 22 2018/02/ 22
2017/02/ 22 2018/02/ 22
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2017/02/ 22 2018/02/ 22
C
Compal Secret Data
Compal Secret Data
Compal Secret Data
543016_S KL_P DG_1 _0
+1.35V_VDDQ_CPU : 2x 10uF 0402 (Placeholder)
Deciphered Date
Deciphered Date
Deciphered Date
4x 1uF 0201 (Placeholder)
4x 10uF 0402
3x 22uF 0603
Title
Title
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Custom
Custom
Custom
Date : Sheet o f
Date : Sheet o f
D
Date : Sheet o f
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
SKL-U(8/12)Power
SKL-U(8/12)Power
SKL-U(8/12)Power
LA-F241P
LA-F241P
LA-F241P
13 54Friday, June 09, 2017
13 54Friday, June 09, 2017
13 54Friday, June 09, 2017
E
0.1
0.1
0.1
1 2
@
1 2
@
RF@
1 2
@
@
RF@
2
+1.0VALW _PRIM
A
+1.0V_PR IM_CORE
+1.0VALW _MPHYAON
CC87 near K 17 (<3 mm)
+1.0VALW _APLL
RC148MURATA B LM18EG221SN1 D
+3VALW _DSW
+3VALW _SPI
+3VALW _PRIM+ 3VALW
HSIO
Imax : 3.5 A
JPC9
112
JUMP_43 X79
@
C2012
Follow LA-C641P
1 2
47U_080 5_6.3V6M
VPRO@
1 2
CC87
1U_0402 _6.3V6K
1 2
CC123
22U_060 3_6.3V6M@
1 2
CC118
.1U_0402 _16V7KRF@
INTEL Sightings report recommends
reserve 0.1uF for RF 5.76GHz noise
CC63 near AJ19 (<10 mm)
1 2
CC63
1U_0402 _6.3V6K@
1 2
CC110
.1U_0402 _16V7KRF@
INTEL Sightings report recommends
reserve 0.1uF for RF 5.76GHz noise
+1.0VALW _MPHYPLL
2
RC209 0_0 603_5%
CC80 nea r N15 (<3mm)
CC81,CC82 near N15 (<1 0mm)
RC149 0_0 603_5%
RC176 0_0 603_5%
RC156 0_04 02_5%
+1.0V _MPHY PLL
1 2
@
1 2
@
1 2
@
1 2
@
+1.0VALW _PRIM
RC192 0_0 603_5%
1 1
+1.0VALW _PRIM
RC175 0_04 02_5%
+1.0VALW _PRIM
+3VALW
1 2
RC173 0_04 02_5%
+3VM
1 2
RC154 0_04 02_5%
+3VALW _PRIM +3VALW _HDA
2 2
3 3
1 2
RC198 BLM1 5GA750SN1D_2 P
JPC7
112
JUMP_43 X39
@
B
12
VCCMP HYGT
1 2
1 2
1 2
1 2
1 2
1 2
+1.0VALW _PRIM
DCPDSW _1P0
@
@
<BOM Struc ture>
@
@
CC91
12
1U_0402 _6.3V6K
@
Near AB19 (<10 m m)
+1.0V_PR IM_CORE
12
CC76
1U_0402 _6.3V6K@
near AF18 (<10 m m)
CC85
1U_0402 _6.3V6K <BOM Structure>
+1.0VALW _MPHYAON
+1.0VALW _MPHYGT
+1.0VALW _AMPHYPLL
+1.0VALW _APLL
+1.0VALW _PRIM
+3VALW _DSW
+3VALW _HDA
+3VALW _SPI
+1.0VALW _SRAM
+3VALW _PRIM
+1.0VALW _PRIM
+1.0VALW _APLLEBB
+1.0VALW _MPHYGT
CC82 22U_060 3_6.3V6M
CC81 22U_060 3_6.3V6M
CC80 1U_0402 _6.3V6K
+1.0VALW _AMPHYPLL
CC61 near K 15 (<3 mm)
CC61 1U_0402 _6.3V6K
+1.0VALW _SRAM
CC122 near AF20 (<10mm)
CC122 1U_04 02_6.3V6K
+1.0VALW _APLLEBB
CC68 nea r N18 (<3mm)
CC68 1U_0402 _6.3V6K
UC1O
AB19
VCCPRIM_1P0
AB20
VCCPRIM_1P0
P18
VCCPRIM_1P0
AF18
VCCPRIM_CORE
AF19
VCCPRIM_CORE
V20
VCCPRIM_CORE
V21
VCCPRIM_CORE
AL1
DCPDSW_1P0
K17
VCCMPHYAON_1P0
L1
VCCMPHYAON_1P0
N15
VCCMPHYGT_1P0_N15
N16
VCCMPHYGT_1P0_N16
N17
VCCMPHYGT_1P0_N17
P15
VCCMPHYGT_1P0_P15
P16
VCCMPHYGT_1P0_P16
K15
VCCAMPHYPLL_1P0
L15
VCCAMPHYPLL_1P0
V15
VCCAPLL_1P0
AB17
VCCPRIM_1P0_AB17
Y18
VCCPRIM_1P0_Y18
AD17
VCCDSW_3P3_AD17
AD18
VCCDSW_3P3_AD18
AJ17
VCCDSW_3P3_AJ17
AJ19
VCCHDA
AJ16
VCCSPI
AF20
VCCSRAM_1P0
AF21
VCCSRAM_1P0
T19
VCCSRAM_1P0
T20
VCCSRAM_1P0
AJ21
VCCPRIM_3P3_AJ21
AK20
VCCPRIM_1P0_AK20
N18
VCCAPLLEBB
SKL-U_BG A1356
@
C
HSIO
HSIO
HSIO
2.1 A
SKL-U
15 OF 20
VCCPGPPA
VCCPGPPB
VCCPGPPC
VCCPGPPD
VCCPGPPE
VCCPGPPF
VCCPGPPG
VCCPRIM_3P3_V19
VCCPRIM_1P0_T1
VCCATS_1P8
VCCRTCPRIM_3P3
VCCRTC_AK19
VCCRTC_BB14
GPP_B0/CORE_VID0
GPP_B1/CORE_VID1
CPU POWER 4 OF 4
0.8 9A
2.5 7A
HSIO
Per 543016_SKL_U_Y_PDG_0_9
VCCRTC does not exceed 3.2 V From PDG
Power Rail Volt age
+CHG RTC
BAT54 C( VF)
+3VL _RT C
3.383 V(M AX )
240 mV
3.14 3V
Result : Pass
Rev_0 .53
DCPRTC
VCCCLK1
VCCCLK2
VCCCLK3
VCCCLK4
VCCCLK5
VCCCLK6
AK15
AG15
Y16
Y15
T16
AF16
AD15
V19
T1
AA1
AK17
AK19
BB14
BB10
A14
K19
L21
N20
L19
A10
AN11
AN13
1 2
CC71 .1U_0402_ 16V7K
PRIMCORE_ VID0
PRIMCORE_ VID1
RTC Battery
+RTCBATT
DC1
1
W=20mils
BAS40-04 _SOT23-3
<BOM Struc ture>
cap Plac e clos e AK19.
+3VALW _1.8VALW _PGPPA
+3VALW _PGPPB
+3VALW _PGPPC
+3VALW _1.8VALW _PGPPD
+3VALW _PGPPE
+1.8VALW _PRIM
+3VALW _PGPPG
+3VALW _PRIM
+1.0VALW _DTS
+1.8VALW _PRIM
+3VALW _RTC
+RTCVCC
<BOM Struc ture>
+1.0VALW _CLK6_24T BT
+1.0VALW _VCCCLK2
+1.0VALW _APLL
+1.0VALW _CLK4_F10 0OC
+1.0VALW _CLK5_F24 NS
+1.0VALW _CLK6_24T BT
+CHGRTC
2
W=10m il
3
T136 @
T138 @
W=20mils
+RTCVCC
No use
1
C151
.1U_0402 _16V7K
2
<BOM Struc ture>
D
SPI Touch
+1.8VALW _PRIM+3VALW _1.8VALW _PGPPA
EC LP C/ESPI
12
RC1960_0402_5% ESPI@
12
@
RC1970_0402_5%
CC102
1U_0402 _6.3V6K @
CC102 near AG15 (< 3 mm)
CC73
1U_0402 _6.3V6K @
CC73 near Y 16 (<10 mm)
+3VALW _1.8VALW _PGPPD
CC103
1U_0402 _6.3V6K
CC74
1U_0402 _6.3V6K @
CC74 near T 16 (<10 mm)
CC83
1U_0402 _6.3V6K @
CC67
1U_0402 _6.3V6K @
CC67 near V 19 (<3 mm)
+1.0VALW _DTS
CC72
1U_0402 _6.3V6K
CC72 near A A1 (<10 mm)
CC78
.1U_0402 _16V7K
CC77
1U_0402 _6.3V6K
CC77,CC78 near AK1 7 (<3 mm)
+1.0VALW _CLK6_24T BT
CC86
1U_0402 _6.3V6K @
CC86 near A 10 (<3 mm)
CC75
1U_0402 _6.3V6K @
CC124
22U_060 3_6.3V6M @
CC125
22U_060 3_6.3V6M @
1 2
+3VALW _PRIM
+1.0VALW _PRIM
E
12
@
RC1610_0402_5%
12
@
RC1630_0402_5%
+1.8VALW _PRIM
12
@
RC1720_0402_5%
12
@
RC1670_0402_5%
12
@
RC1870_0402_5%
+1.8VALW _PRIM
12
@
RC1710_0402_5%
+1.0VALW _PRIM
12
@
RC1690_0402_5%
12
@
RC1640_060 3_5%
+1.0VALW _PRIM
12
@
RC1900_060 3_5%
+1.0VALW _PRIM
12
@
RC1520_060 3_5%
+3VALW _PRIM
+3VALW _PRIM
+3VALW _PRIM
RC2060_0402_5% @
+3VALW _PRIM
+3VALW _PRIM
+3VALW _PRIM
+3VALW _PRIM
+3VALW _PGPPB
12
+3VALW _PGPPC
12
12
+3VALW _PGPPE
12
+3VALW _PGPPG
12
12
12
@
RC1620_0402_5%
12
+3VALW _RTC
12
12
12
+1.0VALW _VCCCLK2 +1.0V ALW_PRIM
12
12
+1.0VALW _CLK4_F10 0OC
12
+1.0VALW _CLK5_F24 NS
Follow 543016_SKL_U_Y_PDG_0_9
+1.0VALW _PRIM +3 VALW_PRIM +1.8VALW _PRIM
22U_0603_6.3V6M
CC111
1
4 4
1
@
@
2
2
22U_0603_6.3V6M
22U_0603_6.3V6M
CC112
@
22U_0603_6.3V6M
CC113
1
2
CC114
1
@
@
2
22U_0603_6.3V6M
22U_0603_6.3V6M
CC115
CC116
1
1
@
2
2
Security Classification
Security Classification
Security Classification
2017/02/ 22 2018/02/ 22
2017/02/ 22 2018/02/ 22
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
2017/02/ 22 2018/02/ 22
C
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Custom
Custom
Custom
Date : Sheet o f
Date : Sheet o f
D
Date : Sheet o f
SKL-U(9/12)Power
SKL-U(9/12)Power
SKL-U(9/12)Power
LA-F241P
LA-F241P
LA-F241P
0.1
0.1
0.1
14 54Friday, June 09, 2017
14 54Friday, June 09, 2017
14 54Friday, June 09, 2017
E
A
B
C
D
E
VCC 27A (U 15W Dual Core GT2) VCCGT / VCCGTX(2+3e only) 40A(need confirm)
#544924 Skylake EDS P.12 5
1 1
.DD .
;!; .6
;-!-; 46
;!! ;";"; .6
2 2
For C PU2+3e SKU
T132 @
T133 @
T137 @
T139 @
SVID ALERT
3 3
VCCOPC_ SENSE
VSSOPC_ SENSE
VCCEOPIO_ SENSE
VSSEOPIO_ SENSE
+1.0V_VC CST
UC1L
A30
VCC_A30
A34
VCC_A34
A39
VCC_A39
A44
VCC_A44
AK33
VCC_AK33
AK35
VCC_AK35
AK37
VCC_AK37
AK38
VCC_AK38
AK40
VCC_AK40
AL33
VCC_AL33
AL37
VCC_AL37
AL40
VCC_AL40
AM32
VCC_AM32
AM33
VCC_AM33
AM35
VCC_AM35
AM37
VCC_AM37
AM38
VCC_AM38
G30
VCC_G30
K32
RSVD_K32
AK32
RSVD_AK32
AB62
VCCOPC_AB62
P62
VCCOPC_P62
V62
VCCOPC_V62
H63
VCC_OPC_1P8_H63
G61
VCC_OPC_1P8_G61
AC63
VCCOPC_SENSE
AE63
VSSOPC_SENSE
AE62
VCCEOPIO
AG62
VCCEOPIO
AL63
VCCEOPIO_SENSE
AJ62
VSSEOPIO_SENSE
S
KL-U_BGA 1356
@
Place the PU
resistors close to CPU
12
RC179
56_0402 _5%
SKL-U
CPU POWER 1 OF 4
12 OF 20
Rev_0 .53
VCC_G32
VCC_G33
VCC_G35
VCC_G37
VCC_G38
VCC_G40
VCC_G42
VCC_J30
VCC_J33
VCC_J37
VCC_J40
VCC_K33
VCC_K35
VCC_K37
VCC_K38
VCC_K40
VCC_K42
VCC_K43
VCC_SENSE
VSS_SENSE
VIDALERT#
VIDSCK
VIDSOUT
VCCSTG_G20
.DD .
;7ACB='*) 2. .6A2B=//6A&6@B
= ;
G32
G33
G35
G37
G38
G40
G42
J30
J33
J37
J40
K33
K35
K37
K38
K40
K42
K43
E32
E33
B63
A63
D64
G20
SOC_SVID_ ALERT#
SOC_SVID_ CLK
SOC_SVID_ DAT
+1.0V S(S USP #)
Trace Length < 25 m ils
VCCSENS E <48>
VSSSENS E <48>
SOC_SVID_ CLK <48>
+1.0VS_V CCSTG
.DD .
; 27ACB='*) 2.6A&6@B
= ;
J;- 2-;!9A%B
7..33>J;- 2
7.33>J;-!9
VCCGT_S ENSE<48>
VSSGT_S ENSE<4 8>
+VCC_GT _VCORE
+VCC_GT
1 2
0_0402_ 5%
56910 U42/U2 2 common
board K52/AK52 NC
@
RC256
VCC_GT_ K52
VCCGT_S ENSE
VSSGT_S ENSE
Trace Length < 25 m ils
+VCC_GT +VCC_GT+VCC_CO RE +VCC_CO RE
A48
A53
A58
A62
A66
AA63
AA64
AA66
AA67
AA69
AA70
AA71
AC64
AC65
AC66
AC67
AC68
AC69
AC70
AC71
K48
K50
K52
K53
K55
K56
K58
K60
M62
N63
N64
N66
N67
N69
J43
J45
J46
J48
J50
J52
J53
J55
J56
J58
J60
L62
L63
L64
L65
L66
L67
L68
L69
L70
L71
J70
J69
UC1M
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT_SENSE
VSSGT_SENSE
S
KL-U_BGA 1356
@
CPU POWER 2 OF 4
SKL-U
13 OF 20
Rev_0 .53
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGTX_AK42
VCCGTX_AK43
VCCGTX_AK45
VCCGTX_AK46
VCCGTX_AK48
VCCGTX_AK50
VCCGTX_AK52
VCCGTX_AK53
VCCGTX_AK55
VCCGTX_AK56
VCCGTX_AK58
VCCGTX_AK60
VCCGTX_AK70
VCCGTX_AL43
VCCGTX_AL46
VCCGTX_AL50
VCCGTX_AL53
VCCGTX_AL56
VCCGTX_AL60
VCCGTX_AM48
VCCGTX_AM50
VCCGTX_AM52
VCCGTX_AM53
VCCGTX_AM56
VCCGTX_AM58
VCCGTX_AU58
VCCGTX_AU63
VCCGTX_BB57
VCCGTX_BB66
VCCGTX_SENSE
VSSGTX_SENSE
N70
N71
R63
R64
R65
R66
R67
R68
R69
R70
R71
T62
U65
U68
U71
W63
W64
W65
W66
W67
W68
W69
W70
W71
Y62
AK42
AK43
AK45
AK46
AK48
AK50
AK52
AK53
AK55
AK56
AK58
AK60
AK70
AL43
AL46
AL50
AL53
AL56
AL60
AM48
AM50
AM52
AM53
AM56
AM58
AU58
AU63
BB57
BB66
VCCGTX_ SENSE
AK62
VSSGTX_ SENSE
AL61
+VCC_GT X_VCORE
VCCGTX_ AK52
+VCC_ GTX_ VCOR E( 12P IN)
U22 ==> NC
U42 ==> +VCC_CORE
T3811@
or CP U2+3e SKU
F
T155 @
T219 @
SOC_SVID_ ALERT#
1 2
<BOM Struc ture>
RC180 220_040 2_5%
SVID DATA
SOC_SVID_ DAT
4 4
A
<BOM Struc ture>
+1.0V_VC CST
12
RC181
100_040 2_1%
<BOM Struc ture>
SOC_SVID_ ALERT#_R <48>
Place the PU
resistors close to CPU
SOC_SVID_ DAT <4 8>
B
(To VR)
(To VR)
543016 PDG0.9 P.189
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Need check
Compal Secret Data
Compal Secret Data
2017/02/ 22 2018/02/ 22
2017/02/ 22 2018/02/ 22
2017/02/ 22 2018/02/ 22
C
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Custom
Custom
Custom
Date : Sheet o f
Date : Sheet o f
D
Date : Sheet o f
SKL-U(10/12)Power,SVID
SKL-U(10/12)Power,SVID
SKL-U(10/12)Power,SVID
LA-F241P
LA-F241P
LA-F241P
E
0.1
0.1
0.1
15 54Friday, June 09, 2017
15 54Friday, June 09, 2017
15 54Friday, June 09, 2017
A
B
C
D
E
1 1
A5
A67
A70
AA2
AA4
AA65
AA68
AB15
AB16
AB18
AB21
AB8
AD13
AD16
AD19
AD20
AD21
AD62
AD8
AE64
AE65
AE66
AE67
AE68
2 2
3 3
AE69
AF1
AF10
AF15
AF17
AF2
AF4
AF63
AG16
AG17
AG18
AG19
AG20
AG21
AG71
AH13
AH6
AH63
AH64
AH67
AJ15
AJ18
AJ20
AJ4
AK11
AK16
AK18
AK21
AK22
AK27
AK63
AK68
AK69
AK8
AL2
AL28
AL32
AL35
AL38
AL4
AL45
AL48
AL52
AL55
AL58
AL64
SKL-U_BG A1356
@
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
UC1P
GND 1 OF 3
SKL-U
Rev_0 .53 Rev_0 .53
AL65
VSS
AL66
VSS
AM13
VSS
AM21
VSS
AM25
VSS
AM27
VSS
AM43
VSS
AM45
VSS
AM46
VSS
AM55
VSS
AM60
VSS
AM61
VSS
AM68
VSS
AM71
VSS
AM8
VSS
AN20
VSS
AN23
VSS
AN28
VSS
AN30
VSS
AN32
VSS
AN33
VSS
AN35
VSS
AN37
VSS
AN38
VSS
AN40
VSS
AN42
VSS
AN58
VSS
AN63
VSS
AP10
VSS
AP18
VSS
AP20
VSS
AP23
VSS
AP28
VSS
AP32
VSS
AP35
VSS
AP38
VSS
AP42
VSS
AP58
VSS
AP63
VSS
AP68
VSS
AP70
VSS
AR11
VSS
AR15
VSS
AR16
VSS
AR20
VSS
AR23
VSS
AR28
VSS
AR35
VSS
AR42
VSS
AR43
VSS
AR45
VSS
AR46
VSS
AR48
VSS
AR5
VSS
AR50
VSS
AR52
VSS
AR53
VSS
AR55
VSS
AR58
VSS
AR63
VSS
AR8
VSS
AT2
VSS
AT20
VSS
AT23
VSS
AT28
VSS
AT35
VSS
AT4
VSS
AT42
VSS
AT56
VSS
AT58
VSS
16 OF 20
AT63
AT68
AT71
AU10
AU15
AU20
AU32
AU38
AV1
AV68
AV69
AV70
AV71
AW10
AW12
AW14
AW16
AW18
AW21
AW23
AW26
AW28
AW30
AW32
AW34
AW36
AW38
AW41
AW43
AW45
AW47
AW49
AW51
AW53
AW55
AW57
AW6
AW60
AW62
AW64
AW66
AW8
AY66
BA1
BA10
BA14
BA18
BA2
BA23
BA28
BA32
BA36
BA45
B10
B14
B18
B22
B30
B34
B39
B44
B48
B53
B58
B62
B66
B71
F68
UC1Q
GND 2 OF 3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SKL-U_BG A1356
@
SKL-U
17 OF 20
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
BA49
BA53
BA57
BA6
BA62
BA66
BA71
BB18
BB26
BB30
BB34
BB38
BB43
BB55
BB6
BB60
BB64
BB67
BB70
C1
C25
C5
D10
D11
D14
D18
D22
D25
D26
D30
D34
D39
D44
D45
D47
D48
D53
D58
D6
D62
D66
D69
E11
E15
E18
E21
E46
E50
E53
E56
E6
E65
E71
F1
F13
F2
F22
F23
F27
F28
F32
F33
F35
F37
F38
F4
F40
F42
BA41
UC1R
F8
VSS
G10
VSS
G22
VSS
G43
VSS
G45
VSS
G48
VSS
G5
VSS
G52
VSS
G55
VSS
G58
VSS
G6
VSS
G60
VSS
G63
VSS
G66
VSS
H15
VSS
H18
VSS
H71
VSS
J11
VSS
J13
VSS
J25
VSS
J28
VSS
J32
VSS
J35
VSS
J38
VSS
J42
VSS
J8
VSS
K16
VSS
K18
VSS
K22
VSS
K61
VSS
K63
VSS
K64
VSS
K65
VSS
K66
VSS
K67
VSS
K68
VSS
K70
VSS
K71
VSS
L11
VSS
L16
VSS
L17
VSS
SKL-U_BG A1356
@
GND 3 OF 3
SKL-U
18 OF 20
Rev_0 .53
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
L18
L2
L20
L4
L8
N10
N13
N19
N21
N6
N65
N68
P17
P19
P20
P21
R13
R6
T15
T17
T18
T2
T21
T4
U10
U63
U64
U66
U67
U69
U70
V16
V17
V18
W13
W6
W9
Y17
Y19
Y20
Y21
4 4
Security Classification
Security Classification
Security Classification
2017/02/ 22 2018/02/ 22
2017/02/ 22 2018/02/ 22
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
2017/02/ 22 2018/02/ 22
C
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Custom
Custom
Custom
Date : Sheet o f
Date : Sheet o f
D
Date : Sheet o f
SKL-U(11/12)GND
SKL-U(11/12)GND
SKL-U(11/12)GND
LA-F241P
LA-F241P
LA-F241P
0.1
0.1
0.1
16 54Friday, June 09, 2017
16 54Friday, June 09, 2017
16 54Friday, June 09, 2017
E
A
1 1
T213 @
T215 @
RC257
1 2
0_0402_ 5%@
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG_RCO MP
XDP_ITP_P MODE
T3825@
T3826@
T3827@
T3828@
T3829@
T3830@
T3831@
T3832@
T3833@
CFG Signals
(For Strap & XDP)
2 2
#544924 SK ylake EDS 0.75 P.117
RSVD - these signals should not be connected
‧
RSVD_TP - these signal s should be routed t o a test point
‧
RSVD_NCTF - these sign als are non-critical to function
‧
and m ay be left un-connecte d
3 3
T3834@
T3835@
T3836@
T3837@
T3838@
T3839@
T3840@
T3841@
T3842@
T3843@
T3844@
T3845@
E68
B67
D65
D67
E70
C68
D68
C67
G69
G68
H70
G71
H69
G70
E63
E66
E60
AY2
AY1
K46
K45
AL25
AL27
C71
B70
A52
BA70
BA68
G65
E61
F71
F70
F63
F66
E8
D1
D3
F60
J71
J68
F65
F61
B
UC1S
CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]
CFG[18]
CFG[19]
CFG_RCOMP
ITP_PMODE
RSVD_AY2
RSVD_AY1
RSVD_D1
RSVD_D3
RSVD_K46
RSVD_K45
RSVD_AL25
RSVD_AL27
RSVD_C71
RSVD_B70
RSVD_F60
RSVD_A52
RSVD_TP_BA70
RSVD_TP_BA68
RSVD_J71
RSVD_J68
VSS_F65
VSS_G65
RSVD_F61
RSVD_E61
SKL-U_BG A1356
@
RESERVED SIGNALS-1
SKL-U
19 OF 20
Rev_0 .53
RSVD_TP_BB68
RSVD_TP_BB69
RSVD_TP_AK13
RSVD_TP_AK12
RSVD_BB2
RSVD_BA3
TP5
TP6
RSVD_D5
RSVD_D4
RSVD_B2
RSVD_C2
RSVD_B3
RSVD_A3
RSVD_AW1
RSVD_E1
RSVD_E2
RSVD_BA4
RSVD_BB4
RSVD_A4
RSVD_C4
TP4
RSVD_A69
RSVD_B69
RSVD_AY3
RSVD_D71
RSVD_C70
RSVD_C54
RSVD_D54
TP1
TP2
VSS_AY71
ZVM#
RSVD_TP_AW71
RSVD_TP_AW70
MSM#
PROC_SELECT#
C
BB68
BB69
AK13
AK12
BB2
BA3
AU5
AT5
D5
D4
B2
C2
B3
A3
AW1
E1
E2
BA4
BB4
A4
C4
BB5
A69
B69
AY3
D71
C70
C54
D54
AY4
BB3
AY71
AR56
AW71
AW70
AP56
C64
PM_ZVM#
PM_MSM#
SKL_CNL #
T156 @
T157 @
T158 @
T159 @
T162 @
T163 @
T199 @
1 2
RC182 0_040 2_5%@
T214 @
T216 @
1 2
RC183 0_040 2_5%@
T225 @
T221 @
T223 @
T230 @
1 2
RC184 100K_04 02_5%
+1.8VALW _PRIM
@
RC57
0_0402_ 5%
+1.0V_VC CST
@
Follow 544669_SKL_U _DDR3L_RVP7_sche matic_rev1.0
D
AW69
RSVD_AW69
AW68
RSVD_AW68
AU56
RSVD_AU56
AW48
SOC_XTA L24_OUT_U42
+1.8VALW _PRIM_U11
12
1
CC79
1U_0402 _6.3V6K
2
@
CC79 nea r U11,U12 (<10 mm)
14MOW52, Connect U11, U 12 to
1.8V for Cannonlake-U PC H
compa tib ili ty
RSVD_AW48
C7
RSVD_C7
U12
RSVD_U12
U11
RSVD_U11
H11
RSVD_H11
SKL-U_BG A1356
@
For 2+3e Solution
PM_Z VM#
Zero Vol tage Mode : Control Signal to OPC
VR, when low OPC VR output is 0V.
PM_M SM#
Minimum Speed Mode: Control signal to
VccEOPIO V R (connected only in 2 VR
solution for OPC) .
PROC_ SEL ECT #
Processor Select: This pin is for
compatibility w ith future plat forms. It should
NC with Skylake
SOC_XTA L24_IN_U42
SOC_XTA L24_OUT_U42
12
U42@
SOC_XTA L24_OUT_U42_ R
12
U42@
UC1T
SPARE
0_0201_ 5%
RC254
U42@
1 2
RC253 1M_04 02_5%
YC3
24MHZ_1 2PF_7V240000 20
3
3
CC432
15P_0402_50V8J
GND
U42@
4
SKL-U
Rev_0 .53
RSVD_F6
RSVD_E3
RSVD_C11
RSVD_B11
RSVD_A11
RSVD_D12
RSVD_C12
RSVD_F52
20 OF 20
U42@
0_0201_ 5%
RC255
SOC_XTA L24_IN_U42_R
1
1
GND
U42@
2
F6
SOC_XTA L24_IN_U42
E3
C11
B11
A11
D12
C12
F52
E
12
CC431
15P_0402_50V8J
12
CFG_RCO MP
CFG4
4 4
Display Port Presence Strap
1 : Disabled; No Physical Display Port
CFG4
attached to Embedded Display Port
0 : Enabled; An external Display Port device is
connected to the Embedded Display Port
1 2
RC185 49.9_040 2_1%
1 2
RC193 1K_0402 _1%
A
Security Classification
Security Classification
Security Classification
2017/02/ 22 2018/02/ 22
2017/02/ 22 2018/02/ 22
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
2017/02/ 22 2018/02/ 22
C
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Custom
Custom
Custom
Date : Sheet o f
Date : Sheet o f
D
Date : Sheet o f
SKL-U(12/12)RSVD
SKL-U(12/12)RSVD
SKL-U(12/12)RSVD
LA-F241P
LA-F241P
LA-F241P
0.1
0.1
0.1
17 54Friday, June 09, 2017
17 54Friday, June 09, 2017
17 54Friday, June 09, 2017
E
A
DDR_B_DQS#[0..7]<7>
DDR_B_D[0..63]<7>
DDR_B_DQS[0..7]<7>
DDR_B_MA[0..16]<7>
DDR_B_BA0<7>
DDR_B_BA1<7>
DDR_B_BG0<7>
DDR_B_BG1<7>
DDR_B_CLK0<7>
1 1
Layout Note:
Place near JDIMM1
+1.2V_VDDQ
2 2
+1.2V_VDDQ
DDR_B_CLK#0<7>
DDR_B_CLK1<7 >
DDR_B_CLK#1<7>
DDR_B_CKE0<7>
DDR_B_CKE1<7>
DDR_B_CS#0<7 >
DDR_B_CS#1<7>
SOC_SMBDATA<8,18,26>
SOC_SMBCLK<8,18,26>
DDR_B_ODT0<7>
DDR_B_ODT1<7>
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
CD5
CD4
2
2
4 as near side of the DIMM close to VDD pins
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
CD11
CD10
1
1
1
2
2
2
Place these caps on the VTT plane close to DIMM
+0.6VS_VTT
1
1
CD31
CD30
1U_0402_6.3V6K
1U_0402_6.3V6K
2
2
3 3
DDR_B_BA0
DDR_B_BA1
DDR_B_BG0
DDR_B_BG1
DDR_B_CLK0
DDR_B_CLK#0
DDR_B_CLK1
DDR_B_CLK#1
DDR_B_CKE0
DDR_B_CKE1
DDR_B_CS#0
DDR_B_CS#1
SOC_SMBDATA
SOC_SMBCLK
DDR_B_ODT0
DDR_B_ODT1
Note:
Check voltage tolerance of
VREF_DQ at the DIMM socket
1U_0402_6.3V6K
1
2
10U_0603_6.3V6M
CD12
1
CD32
1U_0402_6.3V6K
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
CD6
2
10U_0603_6.3V6M
CD13
1
2
1
CD33
1U_0402_6.3V6K
2
1
CD8
CD7
2
2
10U_0603_6.3V6M
10U_0603_6.3V6M
CD19
CD14
CD15
1
1
1
2
2
2
10U_0603_6.3V6M
10U_0603_6.3V6M
CD22
1
1
2
2
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
CD23
1U_0402_6.3V6K
1
1
CD17
CD9
CD18
2
2
CD20
1
2
+3VS
1
C2142
<BOM Structure>
2.2U_0402_6.3V6M
2
close to DIMM
+2.5V
10U_0603_6.3V6M
1
2
4 4
C2140
1
CD29
1U_0402_6.3V6K
2
+3VS_DIMM
1
CD28
.1U_0402_16V7K
2
B
C
D
E
Reverse Type
2-3A to 1 DIMMs/channel
CD21
0.022U_0402_16V7K
12
@
1
2
RD12
24.9_0402_1%
+1.2V_VDDQ
12
RD10
2_0402_1%
RD43
470_0402_1%
<BOM Structure>
12
.4
1 2
RD45 0_0402_ 5%
+1.2V_VDDQ
RD194
1K_0402_1%
1 2
RD199
1K_0402_1%
1 2
DDR_DRAMRST# <7,19>
+DIMM_VREF_DQ
+2.5V
+1.2V_VDDQ +1.2V_VDDQ
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D13
DDR_B_D12
DDR_B_D1
DDR_B_D5
DDR_B_D2 DDR_B_D7
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D23
DDR_B_D22
DDR_B_D29
DDR_B_D25
DDR_B_D30 DDR_B_D31
DDR_B_D26 DDR_B_D27
6/16 INTEL suggest
DDR_B_PARITY<7>
1 2
1 2
RD165 240_0402_ 1%
RD166 240_0402_ 1%
DDR_B_CKE0 DDR_B_CKE1
DDR_B_BG1
DDR_B_BG0
DDR_B_MA9
DDR_B_MA8
DDR_B_MA6
DDR_B_MA1
DDR_B_CLK0
DDR_B_CLK#0
DDR_B_BA1
DDR_B_CS#0
DDR_B_MA14
DDR_B_ODT0
DDR_B_CS#1
DDR_B_ODT1
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D38
DDR_B_D34
DDR_B_D44
DDR_B_D40
DDR_B_D43 DDR_B_D47
DDR_B_D42 DDR_B_D46
DDR_B_D52 DDR_B_D53
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D55
DDR_B_D50
DDR_B_D61
DDR_B_D56
DDR_B_D59
DDR_B_D58 DDR_B_D62
+3VS_DIMM
JDIMM1
1
VSS
3
DQ5
5
VSS
7
DQ1
9
VSS
DQS0_C11DM0*/DBI0*
DQS0_T13VSS
15
VSS
17
DQ7
19
VSS
21
DQ3
VSS23DQ12
DQ1325VSS
27
VSS
29
DQ9
VSS31DQS1_C
DM1*/DBI1*33DQS1_T
35
VSS
DQ1537DQ14
39
VSS
DQ1041DQ11
43
VSS
DQ2145DQ20
47
VSS
DQ1749DQ16
51
VSS
DQS2_C53DM2*/DBI2*
DQS2_T55VSS
VSS57DQ22
DQ2359VSS
VSS61DQ18
DQ1963VSS
VSS65DQ28
DQ2967VSS
VSS69DQ24
DQ2571VSS
VSS73DQS3_C
DM3*/DBI3*75DQS3_T
77
VSS
DQ3079DQ31
81
VSS
DQ2683DQ27
85
VSS
CB5_NC87CB4_NC
89
VSS
CB1_NC91CB0_NC
93
VSS
DQS8_C95DM8*/DBI8*
DQS8_T97VSS
VSS99CB6_NC
101
CB2_NC
103
VSS
105
CB3_NC
107
VSS
109
CKE0
111
VDD1
113
BG1
115
BG0
117
VDD3
119
A12
121
A9
123
VDD5
125
A8
127
A6
129
VDD7
131
A3
133
A1
135
VDD9
137
CK0_T
139
CK0_C
141
VDD11
143
PARITY
145
BA1
147
VDD13
149
S0*
151
A14_WE*
153
VDD15
155
ODT0
157
S1*
159
VDD17
161
ODT1
163
VDD19
165
S3*/C1
167
VSS
169
DQ37
171
VSS
173
DQ33
175
VSS
177
DQS4_C
179
DQS4_T
181
VSS
183
DQ38
185
VSS
187
DQ34
189
VSS
191
DQ44
193
VSS
195
DQ40
197
VSS
199
DM5*/DBI5*
201
VSS
203
DQ46
205
VSS
207
DQ42
209
VSS
211
DQ52
213
VSS
215
DQ49
217
VSS
219
DQS6_C
221
DQS6_T
223
VSS
225
DQ55
227
VSS
229
DQ51
231
VSS
233
DQ61
235
VSS
237
DQ56
239
VSS
241
DM7*/DBI7*
243
VSS
245
DQ62
247
VSS
249
DQ58
251
VSS
253
SCL
255
VDDSPD
257
VPP1
259
VPP2
FOX_AS0A827-H2SB-7HCONN@
CB7_NC
RESET*
ALERT*
EVENT*
VDD10
CK1_T
CK1_C
VDD12
A10_AP
VDD14
A16_RAS*
VDD16
A15_CAS*
VDD18
S2*/C0
VREFCA
DM4*/DBI4*
DQS5_C
DQS5_T
DM6*/DBI6*
DQS7_C
DQS7_T
VSS
DQ4
VSS
DQ0
VSS
DQ6
VSS
DQ2
VSS
DQ8
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
CKE1
VDD2
ACT*
VDD4
A11
A7
VDD6
A5
A4
VDD8
A2
A0
BA0
A13
SA2
VSS
DQ36
VSS
DQ32
VSS
VSS
DQ39
VSS
DQ35
VSS
DQ45
VSS
DQ41
VSS
VSS
DQ47
VSS
DQ43
VSS
DQ53
VSS
DQ48
VSS
VSS
DQ54
VSS
DQ50
VSS
DQ60
VSS
DQ57
VSS
VSS
DQ63
VSS
DQ59
VSS
SDA
SA0
VTT
SA1
GND
GND
2
DDR_B_D11DDR_B_D14
4
6
DDR_B_D10DDR_B_D15
8
10
12
14
DDR_B_D8
16
18
DDR_B_D9
20
22
DDR_B_D4
24
26
DDR_B_D0
28
30
DDR_B_DQS#0
32
DDR_B_DQS0
34
36
DDR_B_D6DDR_B_D3
38
40
42
44
DDR_B_D20DDR_B_D21
46
48
DDR_B_D16DDR_B_D17
50
52
54
56
DDR_B_D19
58
60
DDR_B_D18
62
64
DDR_B_D28
66
68
DDR_B_D24
70
72
DDR_B_DQS#3
74
DDR_B_DQS3
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
DDR_B_MA11DDR_B_MA12
120
DDR_B_MA7
122
124
DDR_B_MA5
126
DDR_B_MA4
128
130
DDR_B_MA2DDR_B_MA3
132
134
136
DDR_B_CLK1
138
DDR_B_CLK#1
140
142
DDR_B_MA0
144
DDR_B_MA10
146
148
DDR_B_BA0
150
DDR_B_MA16
152
154
DDR_B_MA15
156
DDR_B_MA13
158
160
162
164
166
168
DDR_B_D36DDR_B_D37
170
172
DDR_B_D32DDR_B_D33
174
176
178
180
DDR_B_D39
182
184
DDR_B_D35
186
188
DDR_B_D45
190
192
DDR_B_D41
194
196
DDR_B_DQS#5
198
DDR_B_DQS5
200
202
204
206
208
210
212
214
DDR_B_D48DDR_B_D49
216
218
220
222
DDR_B_D54
224
226
DDR_B_D51
228
230
DDR_B_D60
232
234
DDR_B_D57
236
238
DDR_B_DQS#7
240
DDR_B_DQS7
242
244
DDR_B_D63
246
248
250
252
254
256
258
260
261
262
DDR_DRAMRST#_R
M_B_ACT# <7>
DDR_B_ALERT# <7>
+DIMM_VREF_DQ
+0.6VS_VTT
SOC_SMBDATA <8,18,26 >SOC_SMBCLK<8,18,26>
1
@
CD34
.1U_0402_16V7K
2
10K_0402_5%
0_0402_5%
RD108
<BOM Structure>
RD138
@
+3VS
1 2
12
+0.6V_B_VREFDQ<7>
DDR_DRAMRST#_R
)'&4)
A
B
C
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENTDIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENTDIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENTDIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.
MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.
MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.
2017/02/22 2018/02/22
2017/02/22 2018/02/22
2017/02/22 2018/02/22
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size
Size
Size
Date: Sheet of
Date: Sheet of
Date: Sheet of
DDR4_DIMM
DDR4_DIMM
DDR4_DIMM
Document Number Re v
Document Number Re v
Document Number Re v
Custom
Custom
Custom
LA-F241P
LA-F241P
LA-F241P
E
18 5 4Friday, June 09, 2017
18 5 4Friday, June 09, 2017
18 5 4Friday, June 09, 2017
0.1
0.1
0.1
5
4
3
2
1
+DDR_VREF_CA
U2
M1
RU160
VREFCA
P3
A0
P7
A1
R3
A2
N7
A3
N3
A4
P8
A5
P2
A6
R8
A7
R2
A8
R7
A9
M3
A10/AP
T2
A11
M7
A12/BC
T8
A13
L2
A14/WE
N2
BA0
N8
BA1
E2
DMU/DBIU
E7
DML/DBIL
K7
CK_t
K8
CK_c
K2
CKE
K3
ODT
L7
CS
L8
RAS
M8
CAS
A7
DQSU_c
B7
DQSU_t
F3
DQSL_c
G3
DQSL_t
P1
RESET
F9
ZQ
L3
ACT
M2
BG0
N9
TEN
P9
ALERT
T3
PAR
T7
NC
B1
VPP
R9
VPP
96-BALL
SDRAM DDR4
K4A8G165WB-BCPB_FBGA96
X76OBRAM@
DDR_A_MA0
12
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
CD124
DDR_A_MA4
0.047U_0402_25V7K
D D
DDR_A_BA0<7,19,20>
DDR_A_BA1<7,19,20>
+1.2V_VDDQ
DDR_A_CLK0<7,19>
DDR_A_CLK#0<7 ,19>
DDR_A_CKE0<7,19,20>
DDR_A_ODT0<7,19 ,20>
DDR_A_CS#0<7,19,20>
C C
DDR_A_MA[0..16]<7,20>
DDR_A_DQS#[0..7]<7>
DDR_A_DQS[0..7]<7>
DDR_A_D[0..63]<7>
M_A_ACT#<7 ,19,20>
DDR_A_BG0<7,19,20>
DDR_A_ALERT#<7,19>
DDR_A_PARITY<7,19,20>
+2.5V
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_BA0
DDR_A_BA1 DDR_A_BA1
DDR_A_CLK0
DDR_A_CLK#0
DDR_A_CKE0
DDR_A_ODT0
DDR_A_CS#0
DDR_A_MA16
DDR_A_MA15
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_DQS#0
DDR_A_DQS0
MEMRST#
1 2
240_0402_1%
M_A_ACT#
DDR_A_BG0
DDR_A_ALERT#
DDR_A_PARITY
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
DDR_A_D3
G2
DDR_A_D1
F7
DDR_A_D2
H3
DDR_A_D0
H7
DDR_A_D7
H2
DDR_A_D5
H8
DDR_A_D6
J3
DDR_A_D4
J7
DDR_A_D10
A3
DDR_A_D8
B8
DDR_A_D11
C3
DDR_A_D9
C7
DDR_A_D14
C2
DDR_A_D13
C8
DDR_A_D15
D3
DDR_A_D12
D7
B3
VDD
B9
VDD
D1
VDD
G7
VDD
J1
VDD
J9
VDD
L1
VDD
L9
VDD
R1
VDD
T9
VDD
A1
A9
C1
D9
F2
F8
G1
G9
J2
J8
B2
VSS
E1
VSS
E9
VSS
G8
VSS
K1
VSS
K9
VSS
M9
VSS
N1
VSS
T1
VSS
A2
A8
C9
D2
D8
E3
E8
F1
H1
H9
+1.2V_VDDQ
RU174
DDP@
1 2
240_0402_1%
DDR_A_BG1_R DDR_A_BG1_R
CLOCK TERMINATION
DDR_A_CLK0
RU166 3 6_0402_1%
DDR_A_CLK#0
DDR_DRAMRST#<7,18>
CU181
0.1U_0402_16V4Z
1 2
@
UU24
1
VDD
2
D+
3
D-
THERM#4GND
W83L771AWG-2 TSSOP8P
SA00003PU00
DDR_A_ALERT#
B B
External DDR Thermal Sensor
+3VS
A A
SA00003PU0 0
S IC W83L771AWG-2 TSSOP 8P SENSOR
5
1 2
RU167 3 6_0402_1%
1 2
RD41 49.9_0402_1%
DDR_DRAMRST#
8
SCLK
7
SDATA
6
ALERT#
RU165 10K_0402_5 %
5
@
12
INTEL suggest 50ohm 1%
@
1 2
RD46 0_0402_ 5%
2017/6/8
confirm Thermal/EC change to reserve
SOC_SML1CLK <8,22,36 >
SOC_SML1DATA <8,2 2,36>
1 2
+3VS
@
@
1
CD36
.1U_0402_16V7K
2
@
1 2
RD47 0_0402_ 5%
+1.2V_VDDQ
MEMRST#
4
+DDR_VREF_CA
U3
M1
RU161
VREFCA
P3
A0
P7
A1
R3
A2
N7
A3
N3
A4
P8
A5
P2
A6
R8
A7
R2
A8
R7
A9
M3
A10/AP
T2
A11
M7
A12/BC
T8
A13
L2
A14/WE
N2
BA0
N8
BA1
E2
DMU/DBIU
E7
DML/DBIL
K7
CK_t
K8
CK_c
K2
CKE
K3
ODT
L7
CS
L8
RAS
M8
CAS
A7
DQSU_c
B7
DQSU_t
F3
DQSL_c
G3
DQSL_t
P1
RESET
F9
ZQ
L3
ACT
M2
BG0
N9
TEN
P9
ALERT
T3
PAR
T7
NC
B1
VPP
R9
VPP
96-BALL
SDRAM DDR4
K4A8G165WB-BCPB_FBGA96
X76OBRAM@
DDR_A_MA0
12
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
CD125
DDR_A_MA4
0.047U_0402_25V7K
DDR_A_BA0<7,19,20>
DDR_A_BA1<7,19,20> DDR_A_BA0<7,19,20>
+1.2V_VDDQ
DDR_A_CLK0<7,19>
DDR_A_CLK#0<7 ,19> DDR_A_CLK0<7,19>
DDR_A_CKE0<7,19,20>
DDR_A_ODT0<7,19 ,20>
0_0402_5%
SD028000080
RU174
SDP@
DDR_A_BG1_R <20>
M_A_ACT#<7 ,19,20>
DDR_A_BG0<7,19,20>
DDR_A_ALERT#<7,19>
DDR_A_PARITY<7,19,20>
+2.5V
+0.6VS_VTT
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_BA0
DDR_A_CLK0
DDR_A_CLK#0
DDR_A_CKE0
DDR_A_ODT0
DDR_A_CS#0
DDR_A_MA16
DDR_A_MA15
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_DQS#2
DDR_A_DQS2
MEMRST#
1 2
240_0402_1%
M_A_ACT#
DDR_A_BG0
DDR_A_ALERT#
DDR_A_PARITY
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
G2
DQL0
F7
DQL1
H3
DQL2
H7
DQL3
H2
DQL4
H8
DQL5
J3
DQL6
J7
DQL7
A3
B8
C3
C7
C2
C8
D3
D7
B3
VDD
B9
VDD
D1
VDD
G7
VDD
J1
VDD
J9
VDD
L1
VDD
L9
VDD
R1
VDD
T9
VDD
A1
A9
C1
D9
F2
F8
G1
G9
J2
J8
B2
VSS
E1
VSS
E9
VSS
G8
VSS
K1
VSS
K9
VSS
M9
VSS
N1
VSS
T1
VSS
A2
A8
C9
D2
D8
E3
E8
F1
H1
H9
Co-lay for SDP/DDP
1
2
12
DDP@
SDP@
RD11
2.7_0402_1%
RD13
24.9_0402_1%
0_0402_5%
RU178
1 2
1 2
RU179
0_0402_5%
+1.2V_VDDQ
12
1 2
1 2
RD195
1.8K_0402_1%
RD200
1.8K_0402_1%
DDR_A_BG1_R DDR_A_BG1
+0.6V_VREFCA<7>
CD24
0.022U_0402_16V7K
DDR_A_D19
DDR_A_D17
DDR_A_D18
DDR_A_D16
DDR_A_D23
DDR_A_D21
DDR_A_D22
DDR_A_D20
DDR_A_D26
DDR_A_D24
DDR_A_D27
DDR_A_D25
DDR_A_D30
DDR_A_D29
DDR_A_D31
DDR_A_D28
+DDR_VREF_CA
3
+1.2V_VDDQ
RU175
DDP@
1 2
240_0402_1%
DDR_A_BG1 <7>
+DDR_VREF_CA
U4
M1
RU162
VREFCA
P3
A0
P7
A1
R3
A2
N7
A3
N3
A4
P8
A5
P2
A6
R8
A7
R2
A8
R7
A9
M3
A10/AP
T2
A11
M7
A12/BC
T8
A13
L2
A14/WE
N2
BA0
N8
BA1
E2
DMU/DBIU
E7
DML/DBIL
K7
CK_t
K8
CK_c
K2
CKE
K3
ODT
L7
CS
L8
RAS
M8
CAS
A7
DQSU_c
B7
DQSU_t
F3
DQSL_c
G3
DQSL_t
P1
RESET
F9
ZQ
L3
ACT
M2
BG0
N9
TEN
P9
ALERT
T3
PAR
T7
NC
B1
VPP
R9
VPP
96-BALL
SDRAM DDR4
K4A8G165WB-BCPB_FBGA96
X76OBRAM@
RAM_FLAG0<11> RAM_FLAG1 <11>
2017/02/22 2018/02/22
2017/02/22 2018/02/22
2017/02/22 2018/02/22
DDR_A_MA0
12
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
CD126
DDR_A_MA4
DDR_A_MA5
0.047U_0402_25V7K
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_BA0
DDR_A_BA1<7,19,20>
DDR_A_CLK#0<7 ,19>
DDR_A_CKE0<7,19,20>
DDR_A_ODT0<7,19 ,20> DDR_A_ODT0<7,19 ,20>
DDR_A_CS#0<7,19,20> DDR_A_CS#0<7,19,20>
0_0402_5%
SD028000080
RU175
SDP@
M_A_ACT#<7 ,19,20>
DDR_A_BG0<7,19,20>
DDR_A_ALERT#<7,19>
DDR_A_PARITY<7,19,20>
DDR_A_BA1
+1.2V_VDDQ +1.2V_VDDQ
DDR_A_CLK0
DDR_A_CLK#0
DDR_A_CKE0
DDR_A_ODT0
DDR_A_CS#0
DDR_A_MA16
DDR_A_MA15
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_DQS#4
DDR_A_DQS4
MEMRST#
1 2
240_0402_1%
M_A_ACT#
DDR_A_BG0
DDR_A_ALERT#
DDR_A_PARITY
+2.5V
ZZZ
ALT. GROUP PARTS HYNIX 8G C4PB1
X76@OBHYNIX8
X76713BOL06
ZZZ
ALT. GROUP PARTS HYNIX 4G AE591 C4PB1
X76@OBHYNIX4
X76713BOL03
LA-F241P
LA-F241P
LA-F241P
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENTDIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENTDIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENTDIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.
MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.
MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.
DDR_A_D35
G2
DQL0
DDR_A_D33
F7
DQL1
DDR_A_D34
H3
DQL2
DDR_A_D32
H7
DQL3
DDR_A_D39
H2
DQL4
DDR_A_D37
H8
DQL5
DDR_A_D38
J3
DQL6
DDR_A_D36
J7
DQL7
DDR_A_D42
A3
DQU0
DDR_A_D40
B8
DQU1
DDR_A_D43
C3
DQU2
DDR_A_D41
C7
DQU3
DDR_A_D46
C2
DQU4
DDR_A_D45
C8
DQU5
DDR_A_D47
D3
DQU6
DDR_A_D44
D7
DQU7
B3
VDD
B9
VDD
D1
VDD
G7
VDD
J1
VDD
J9
VDD
L1
VDD
L9
VDD
R1
VDD
T9
VDD
A1
VDDQ
A9
VDDQ
C1
VDDQ
D9
VDDQ
F2
VDDQ
F8
VDDQ
G1
VDDQ
G9
VDDQ
J2
VDDQ
J8
VDDQ
B2
VSS
E1
VSS
E9
VSS
G8
VSS
K1
VSS
K9
VSS
M9
VSS
N1
VSS
T1
VSS
A2
VSSQ
A8
VSSQ
C9
VSSQ
D2
VSSQ
D8
VSSQ
E3
VSSQ
E8
VSSQ
F1
VSSQ
H1
VSSQ
H9
VSSQ
Data mapping
U2
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
on board ram flag
hynix 8G(DDP) SA0000ARA10
Micron 4G(SDP) SA00009V220
hynix 4G(SDP) SA0000A1H20
MICRON 8G (DDP) SA0000A3120
No on baord RAM
X76OBRAM@
X76OBRAM@
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
+1.2V_VDDQ
RU176
DDP@
1 2
240_0402_1%
DDR_A_BG1_R DDR_A_BG1_R
DQ
U3
D3
DQL0
D1
DQL1
D2
DQL2
DQL3
D0
DQL4
D7
DQL5
D5
DQL6
D6
DQL7
D4
DQU0
D10
DQU1
D8
DQU2
D11
DQU3
D9
DQU4
D14
DQU5
D13
DQU6
D15
DQU7
D12
+3VS +3VS
12
RU170
10K_0402_5%
12
RU173
10K_0402_5%
+DDR_VREF_CA
12
CD127
0.047U_0402_25V7K
DDR_A_BA0<7,19,20>
DDR_A_BA1<7,19,20>
DDR_A_CLK0<7,19>
DDR_A_CLK#0<7 ,19>
DDR_A_CKE0<7,19,20>
0_0402_5%
SD028000080
RU176
SDP@
M_A_ACT#<7 ,19,20>
DDR_A_BG0<7,19,20>
DDR_A_ALERT#<7,19>
DDR_A_PARITY<7,19,20>
+2.5V
DQ
D19
D17
D18
D16
D23
D21
D22
D20
D26
D24
D27
D25
D30
D29
D31
D28
VGA_ID
FLAG10FLAG0
(D4PB1/D5PB1)
0
0
0
1
0
1
0
1
0 0
1
0
1
1
1 1 1
12
X76OBRAM@
RU169
10K_0402_5%
RAM_FLAG1RAM_FLAG 0
12
RU172
10K_0402_5%
X76OBRAM@
M1
DDR_A_MA0
P3
DDR_A_MA1
P7
DDR_A_MA2
R3
DDR_A_MA3
N7
DDR_A_MA4
N3
DDR_A_MA5
P8
DDR_A_MA6
P2
DDR_A_MA7
R8
DDR_A_MA8
R2
DDR_A_MA9
R7
DDR_A_MA10
M3
DDR_A_MA11
T2
DDR_A_MA12
M7
DDR_A_MA13
T8
DDR_A_MA14
DDR_A_BA0
DDR_A_BA1
DDR_A_CLK0
DDR_A_CLK#0
DDR_A_CKE0
DDR_A_CS#0
DDR_A_MA16
DDR_A_MA15
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_DQS#6
DDR_A_DQS6
MEMRST#
1 2
240_0402_1%
M_A_ACT#
DDR_A_BG0
DDR_A_ALERT#
DDR_A_PARITY
U4 U5
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
DDR_A_ODT0
RU163
0
10
L2
N2
N8
E2
E7
K7
K8
K2
K3
L7
L8
M8
A7
B7
F3
G3
P1
F9
L3
M2
N9
P9
T3
T7
B1
R9
DQ
D35
D33
D34
D32
D39
D37
D38
D36
D42
D40
D43
D41
D46
D45
D47
D44
1
1
0
U5
VREFCA
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14/WE
BA0
BA1
DMU/DBIU
DML/DBIL
CK_t
CK_c
CKE
ODT
CS
RAS
CAS
DQSU_c
DQSU_t
DQSL_c
DQSL_t
RESET
ZQ
ACT
BG0
TEN
ALERT
PAR
NC
VPP
VPP
96-BALL
SDRAM DDR4
K4A8G165WB-BCPB_FBGA96
X76OBRAM@
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
ZZZ
ALT. GROUP PARTS MICRON 4G AE591 C4PB1
X76@OBMICRON4
X76713BOL01
ZZZ
ALT. GROUP PARTS MICRON 8G AE591 C4PB1
X76@OBMICRON8
X76713BOL02
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
DDR_A_D51
G2
DQL0
DDR_A_D49
F7
DQL1
DDR_A_D50
H3
DQL2
DDR_A_D48
H7
DQL3
DDR_A_D55
H2
DQL4
DDR_A_D53
H8
DQL5
DDR_A_D54
J3
DQL6
DDR_A_D52
J7
DQL7
DDR_A_D58
A3
DDR_A_D56
B8
DDR_A_D59
C3
DDR_A_D57
C7
DDR_A_D62
C2
DDR_A_D61
C8
DDR_A_D63
D3
DDR_A_D60
D7
+1.2V_VDDQ
B3
VDD
B9
VDD
D1
VDD
G7
VDD
J1
VDD
J9
VDD
L1
VDD
L9
VDD
R1
VDD
T9
VDD
A1
A9
C1
D9
F2
RU177
F8
G1
G9
SD028000080
J2
0_0402_5%
J8
SDP@
DDP@
B2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
240_0402_1%
E1
1 2
E9
RU177
G8
K1
K9
M9
N1
T1
A2
A8
C9
D2
D8
E3
E8
F1
H1
H9
DQ
D51
D49
D50
D48
D55
D53
D54
D52
D58
D56
D59
D57
D62
D61
D63
D60
X76OBRAM@ Level includes U2~U5, RU169, RU 170, RU172, RU173, RC215 and RC216
Title
Title
Title
DDR4 ON BOARD CHIPS
DDR4 ON BOARD CHIPS
DDR4 ON BOARD CHIPS
Size
Document Number Re v
Size
Document Number Re v
Size
Document Number Re v
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
19 5 4Wednesday, June 14, 2017
19 5 4Wednesday, June 14, 2017
19 5 4Wednesday, June 14, 2017
0.1
0.1
0.1
5
DDR_A_MA[0..16]<7,19>
D D
+1.2V_VDDQ
CU195
CU197
CU198
1U_0402_6.3V6K
1
2
CU200
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
1
2
2
2
CU196
CU199
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
2
2
8#&6
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
CD26
CD25
1
1
2
2
C C
+2.5V +0.6VS_VTT
CU203
CU205
CU206
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
1
2
2
2
2 as near each on board RAM device as possible
10U_0402_6.3V6M
10U_0402_6.3V6M
1
1
CD42
<BOM Structure>
2
1
CD43
<BOM Structure>
2
CD41
B B
<BOM Structure>
2
10U_0603_6.3V6M
CD27
1
2
CU208
1U_0402_6.3V6K
1
2
10U_0402_6.3V6M
1
CD39
CD40
1
1
+
CU89
330U_D2_2V_Y
@
2
CU207
SGA00009S00
2
2
330U 2V H1.9
9mohm POLY
CU204
CU209
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
2
2
4
CD211
CU201
1U_0402_6.3V6K
1
2
CD212
CD210
1U_0402_6.3V6K
1
2
CD213
CD214
1U_0402_6.3V6K
1U_0402_6.3V6K
1
2
1U_0402_6.3V6K
1
2
1U_0402_6.3V6K
1
1
2
2
4 as near each on board RAM device as possible
CU210
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
2
2
3
CD215
CD216
CD217
1U_0402_6.3V6K
1
2
CD218
1U_0402_6.3V6K
1U_0402_6.3V6K
1
2
1U_0402_6.3V6K
1
1
2
2
CU212
CU213
CU216
1U_0402_6.3V6K
1
2
CU218
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
1
2
2
2
CU214
CU215
1U_0402_6.3V6K
1
2
CU217
CU211
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1
2
1U_0402_6.3V6K
1
1
2
2
2 as near each on board RAM device as possible
10U_0603_6.3V6M
10U_0603_6.3V6M
CD46
CD47
1
1
2
2
2
+0.6VS_VTT
RP17
DDR_A_MA9
1 8
DDR_A_MA5
2 7
DDR_A_MA0
3 6
DDR_A_MA1
4 5
36_0804_8P4R_5%
RP18
DDR_A_MA6
1 8
DDR_A_MA11
2 7
DDR_A_MA7
3 6
DDR_A_MA4
4 5
36_0804_8P4R_5%
RP19
DDR_A_MA14
1 8
DDR_A_MA15
2 7
DDR_A_BA0
DDR_A_BA0<7,19>
DDR_A_BA1<7,19>
DDR_A_ODT0<7,19>
DDR_A_CS#0<7,19>
DDR_A_BG0<7,19>
M_A_ACT#<7,19>
DDR_A_CKE0<7,19>
DDR_A_PARITY<7,19>
DDR_A_BG1_R<19>
DDR_A_BA1
DDR_A_ODT0
DDR_A_CS#0
DDR_A_MA16
DDR_A_MA10
DDR_A_BG0
DDR_A_MA12
M_A_ACT#
DDR_A_CKE0
DDR_A_MA13
DDR_A_MA8
DDR_A_MA3
DDR_A_MA2
DDR_A_PARITY
DDR_A_BG1_R
3 6
4 5
36_0804_8P4R_5%
RP20
1 8
2 7
3 6
4 5
36_0804_8P4R_5%
RP21
1 8
2 7
3 6
4 5
36_0804_8P4R_5%
RP22
1 8
2 7
3 6
4 5
36_0804_8P4R_5%
RP24
1 8
2 7
3 6
4 5
36_0804_8P4R_5%
1 2
RU180
DDP@
36_0402_1%
1
A A
LA-F241P
LA-F241P
LA-F241P
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENTDIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENTDIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENTDIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.
MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.
5
4
3
MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.
2017/02/22 2018/02/22
2017/02/22 2018/02/22
2017/02/22 2018/02/22
Compal Secret Data
Compal Secret Data
Compal Secret Data
2
Deciphered Date
Deciphered Date
Deciphered Date
Title
Title
Title
DDRIII ON BOARD CHIPS
DDRIII ON BOARD CHIPS
DDRIII ON BOARD CHIPS
Size
Document Number Re v
Size
Document Number Re v
Size
Document Number Re v
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
20 5 4Friday, June 09, 2017
20 5 4Friday, June 09, 2017
20 5 4Friday, June 09, 2017
0.1
0.1
0.1
A
B
C
D
E
SM01000EJ00 3000ma
+19VB +INVPWR_ B+
+3VS
C140
1U_0402_6.3V6K
1
<BOM Struc ture>
1 1
2 2
2
SOC_ENV DD<6>
EDP_TXP0<6>
EDP_TXN0<6>
EDP_TXP1<6>
EDP_TXN1<6>
EDP_TXP2<6>
EDP_TXN2<6>
EDP_TXP3<6>
EDP_TXN3<6>
EDP_AUXP<6>
EDP_AUXN<6>
CPU_EDP_HPD<6>
H!C9972
U8
5
OUT
IN
GND
4
1 2
C371 .1U_0402 _16V7K
1 2
C372 .1U_0402 _16V7K
1 2
C373 .1U_0402 _16V7K
1 2
C374 .1U_0402 _16V7K
1 2
C388 .1U_0402 _16V7K
1 2
C376 .1U_0402 _16V7K
1 2
C387 .1U_0402 _16V7K
1 2
C378 .1U_0402 _16V7K
1 2
C379 .1U_0402 _16V7K
1 2
C377 .1U_0402 _16V7K
EDP_AUX N_C
EDP_AUX P_C
OC
EN
SY6288C20 AAC_SOT23-5
<BOM Struc ture>
R613 100K _0402_5%@
R614 100K _0402_5%@
1 2
@
R407 0_ 0402_5%
R364
100K_04 02_5%
<BOM Struc ture>
EDP_TXP 0_C
EDP_TXN 0_C
EDP_TXP 1_C
EDP_TXN 1_C
EDP_TXP 2_C
EDP_TXN 2_C
EDP_TXP 3_C
EDP_TXN 3_C
EDP_AUX P_C
EDP_AUX N_C
12
12
EDP_HPD
W=60mils
1
2
3
12
+LCDVDD
1
2
C367
4.7U_060 3_6.3V6K
<BOM Struc ture>
+3VS
1
C368
.1U_0402 _16V7K
2
@
SOC_BKL _PWM<6>
BKOFF#<36>
220 ohm@ 100 mhz
DCR 0.04
SOC_BKL _PWM
BKOFF#
L14
HCB2012 KF-221T30_080 5
1 2
EMC@
C365
68P_040 2_50V8J
@EMC@
1 2
R393 100K _0402_5%@
@EMC@
1 2
C549 220P_0402 _50V7K
C528 220P_0402 _50V7K
R280 10K_ 0402_5%@
1 2
1 2
@EMC@
W=60milsW=60mils
1
1
2
2
+19VB +19VB +19VB
+3VS
1
2
1
2
C375
.1U_0402 _16V7K
<BOM Struc ture>
12
C5229
0.1U_040 2_25V6
RF@
C364
1000P_0402_50V7K
@EMC@
C5230
2200P_0 402_25V7K
RF@
+LCDVDD
1
2
1
C5231
68P_040 2_50V8J
2
RF@
C419
.1U_0402 _16V7K
@
H6%H
+3VS
8)4)
+LCDVDD
+INVPW R_B+
W=60mils
USB20_P 7_CAMERA
USB20_N 7_CAMERA
EDP_AUX P_C
EDP_AUX N_C
EDP_TXN 3_C
EDP_TXP 3_C
EDP_TXN 2_C
EDP_TXP 2_C
EDP_HPD
BKOFF#
SOC_BKL _PWM
EDP_TXN 1_C
EDP_TXP 1_C
EDP_TXN 0_C
EDP_TXP 0_C
CONN@
ACES_50 406-03071-001
30
30
29
29
28
28
27
27
26
26
25
25
24
24
23
23
22
22
21
21
20
20
19
19
18
18
17
17
16
16
15
15
14
14
13
13
12
12
11
11
10
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
JEDP2
35
G5
34
G4
33
G3
32
G2
31
G1
SP010011Z00
3 3
+5VS
1 2
1 2
R5270
TS@
R5271
TS@
TS_5VS@
TS_3VS@
+5VS
1 2
12
A
+3VS
100K_04 02_5%
4 4
220K_04 02_5%
+TS_PW R
R52680_0603 _5%
R52720_0603 _5%
U5010
5
4
SY6288C20 AAC_SOT23-5
TS@
C5261
0.1U_0402_16V4Z
1
TS@
2
TS_EN
+TS_PW R
1
OUT
IN
EN
GND
2
3
OC
D2020
6
5
4
ESD@
I/O4
VDD
I/O3
AZC099-0 4S.R7G_SOT23-6
I/O2
GND
I/O1
+TS_PW R
C5262
TS@
B
USB20_N 10
3
2
USB20_P 10
1
10U_0402_6.3V6M
1
2
+TS_PW R
TS_EN<36>
USB20_N 10<12>
USB20_N 10
USB20_P 10
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2*$)
JTS1
1
1
2
2
3
3
4
4
5
6
2017/02/ 22 2018/02/ 22
2017/02/ 22 2018/02/ 22
2017/02/ 22 2018/02/ 22
C
7
5
GND
8
6
GND
ACES_50 376-00601-P01
CONN@
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
4)
USB20_N 7< 12>USB20_P 10<12 >
USB20_P 7<12>
D
USB20_N 7 U SB20_N7_CAMER AUSB20_N7 _CAMERA
USB20_P 7
Title
Title
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Custom
Custom
Custom
Date : Sheet o f
Date : Sheet o f
Date : Sheet o f
1
1
L4904
2
2
MCF1210 2G900-T_4P
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
eDP/TS Connector
eDP/TS Connector
eDP/TS Connector
LA-F241P
LA-F241P
LA-F241P
4
4
EMI@
USB20_P 7_CAMERA
3
3
21 54Friday, June 09, 2017
21 54Friday, June 09, 2017
21 54Friday, June 09, 2017
E
0.1
0.1
0.1
A
B
C
D
E
+3VS
1 1
2 2
SOC_DP1 _HPD<6>
12
R2530
100K_04 02_5%
1 2
SOC_DP1 _AUXN<6>
SOC_DP1 _AUXP<6>
SOC_DP1 _P0<6>
SOC_DP1 _N0<6>
SOC_DP1 _P1<6>
SOC_DP1 _N1<6>
C6 .1U _0402_16V7K
1 2
C5 .1U _0402_16V7K
1 2
C18 .1U _0402_16V7K
1 2
C37 .1U _0402_16V7K
1 2
C38 .1U _0402_16V7K
1 2
C39 .1U _0402_16V7K
C14 2.2 U_0402_6.3V6M<BOM S tructure>
C13 .1U _0402_16V7K
C16 .1U _0402_16V7K
<BOM Struc ture>
C17 .1U _0402_16V7K
1 2
R9 12 K_0402_1%
<BOM Struc ture>
L3
FBMA-L11 -160808-800LMT _0603
1 2
<BOM Struc ture>
12
12
12
12
<BOM Struc ture>
+3VS_CR T
SOC_DP1 _HPD
DP_CRT_ AUXN
DP_CRT_ AUXP
SOC_DP1 _P0_C
SOC_DP1 _N0_C
SOC_DP1 _P1_C
SOC_DP1 _N1_C
+3VS
2
1
<BOM Struc ture>
C1
VCCK_12
VCCK_12
C15
1
2
.1U_0402_16V7K
1
27
26
29
30
31
32
19
24
25
28
11
13
14
16
33
10U_0603_6.3V6M
1
C2
2
<BOM Struc ture>
<BOM Struc ture>
.1U_0402_16V7K
U6
HPD
AUX_N
AUX_P
LANE0P
LANE0N
LANE1P
LANE1N
VCCK_12
AVCC_33
AVCC_12
RRX
BLUE_N
GREEN_N
GND_DAC
RED_N
EPAD_GND
RTD2168 -CG_QFN32_5X5<BOM Structure>
1
1
C4
C3
2
.1U_0402_16V7K
5
9
20
DVCC_33
DVCC_33
VDD_DAC_33
POL1_SDA
POL2_SCL
2
<BOM Struc ture>
VGA_SDA
VGA_SCL
HSYNC
VSYNC
RED_P
GREEN_P
BLUE_P
SMB_SCL
SMB_SDA
LDO_EN
XO
XI/CKIN
10U_060 3_6.3V6M
<BOM Struc ture>
CRT_DAT A_1
6
CRT_CLK _1
4
PCH_CRT _HSYNC_R
8
PCH_CRT _VSYNC_R
7
PCH_CRT _R
15
PCH_CRT _G
12
PCH_CRT _B
10
POL1_SD A
22
POL2_SC L
23
CRT_SMB _CLK
2
CRT_SMB _SDA
3
LDO_EN
21
18
17
1 2
R24 0_0402_5%@
1 2
R19 0_0402_5%@
CRT_DAT A_1 <23>
CRT_CLK _1 <23>
PCH_CRT _HSYNC_R <23 >
PCH_CRT _VSYNC_R <23>
PCH_CRT _R <23 >
PCH_CRT _G <23>
PCH_CRT _B <23>
182736
45
75_0804 _8P4R_1%
RP23
SOC_SML 1CLK
SOC_SML 1DATA
Address:(layout guide P.11)
Please reserve slave address of
0x64/0x65 and 0x68/0x69 for RTD2168’ s use
SOC_SML 1CLK <8,19,36>
SOC_SML 1DATA <8,19,36>
+3VS+3VS +3VS
3 3
POL_SDA
0
1
POL_SCL
ROM: Internal ROM
EP: Programmed external EC
EEPROM: External ROM
4 4
0
1
*ROM
A
EP
X
EEPROM
<BOM Struc ture>
12
R10
4.7K_0402_5%
12
@
R5241
4.7K_0402_5%
12
@
R5239
POL1_SD APOL2_SC L LDO_EN
12
<BOM Struc ture>
R5242
<BOM Struc ture>
4.7K_0402_5%
4.7K_0402_5%
12
R5240
4.7K_0402_5%
LDO_EN:
*1: Internal 1.2V
12
@
0: External 1.2V
R5243
4.7K_0402_5%
B
Security Classification
Security Classification
Security Classification
2017/02/ 22 2018/02/ 22
2017/02/ 22 2018/02/ 22
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2017/02/ 22 2018/02/ 22
C
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Custom
Custom
Custom
Date : Sheet o f
Date : Sheet o f
Date : Sheet o f
Compal Electronics, Inc.
Realtek RTD2168
Realtek RTD2168
Realtek RTD2168
LA-F241P
LA-F241P
LA-F241P
22 54Friday, June 0 9, 2017
22 54Friday, June 0 9, 2017
22 54Friday, June 0 9, 2017
E
0.1
0.1
0.1
A
92
1 1
CRT_R
CRT_G
CRT_B
2 2
SM01000LU00 ( S SUPPRE_ MURATA BLM15BA220SN1D 0402)
L2503
EMC@
BLM15BA 220SN1D_2P
1 2
L2505
EMC@
BLM15BA 220SN1D_2P
1 2
L2504
EMC@
BLM15BA 220SN1D_2P
1 2
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
1
1
1
C2529
2
2
C2531
C2530
2
10P_0402_50V8J
1
2
CRT_HSYNC CRT_HSYNC _1
CRT_VSYNC CRT_V SYNC_1
B
D2019
CRT_R_2
CRT_G_2
10P_0402_50V8J
1
C2532
2
1 2
33_0402 _5%
1 2
33_0402 _5%
C2533
R2524
R2525
CRT_R_2
CRT_G_2
CRT_B_2
10P_0402_50V8J
1
2
6
5
4
C2534
ESD@
I/O4
VDD
I/O3
AZC099-0 4S.R7G_SOT23-6
L12 EMI@
BLM15BB 470SN1D_2P
1 2
L13 EMI@
BLM15BB 470SN1D_2P
1 2
I/O2
GND
I/O1
10P_040 2_50V8J
3
2
1
+HDMI_5V_ OUT
CRT_B_2
1
C2536
2
C
CRT_HSYNC _2
CRT_VSYNC _2
1
C2537
10P_040 2_50V8J
2
CRT_HSYNC _2
CRT_VSYNC _2
D2018
6
5
4
ESD@
I/O4
VDD
I/O3
AZC099-0 4S.R7G_SOT23-6
I/O2
GND
I/O1
3
2
1
D
CRT_CLK _2
CRT_DAT A_2
W=40mils
+HDMI_5V_ OUT
T99 @
T109 @
CRT_CLK _2
CRT_DAT A_2
E
92)
JCRT2
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
16
G
17
G
SUYIN_070546 FR015S251ZR
CONN@
+5VS_CR T_SW
R5277
1 2
0_0402_ 5%
3 3
0.1U_0402_16V4Z
1
C782
2
From RTD2168
+3VS
12
R647
4.7K_040 2_5%
4 4
DOCK_CR T_DET#<37>
12
R648
4.7K_040 2_5%
CRT_DAT A_1
CRT_CLK _1
A
+3VS+5 VS
PCH_CRT _HSYNC_R<22>
PCH_CRT _VSYNC_R<22>
+3VS
L4905
1 2
FBMA-L11 -160808-800LMT _0603
PCH_CRT _R<22>
PCH_CRT _G<22>
PCH_CRT _B<2 2>
CRT_DAT A_1<2 2>
CRT_CLK _1<22>
DOCK_CR T_DET#
+3VS_CR T_SW
0.1U_0402_16V4Z
1
C779
2
PCH_CRT _R
PCH_CRT _G
PCH_CRT _B
PCH_CRT _HSYNC_R
PCH_CRT _VSYNC_R
CRT_DAT A_1
@
12
R5490_0402 _5% @
1 2
0.1U_0402_16V4Z
CRT_CLK _1
12
R5500_0402_5%
R76210K_0402_ 5%
0.1U_0402_16V4Z
1
2
B
1
C780
C781
2
U11
1
R
2
G
5
B
6
H_SOURCE
7
V_HOURCE
9
SDA_SOURCE
10
SCL_SOURCE
30
SEL
29
TEST
8
Reserved
3
GND
11
GND
28
GND
31
GND
33
GPAD
PI3V713-AZ LEX_TQFN32_6 X3~D
SA00004 R600
+3VS
DOCK_CR T_DET#
+5VS_CR T_SW
16
5V VDD
4
VDD
23
VDD
32
VDD
27
R1
25
G1
22
B1
20
H1_OUT
18
V1_OUT
12
SDA1
14
SCL1
26
R2
24
G2
21
B2
19
H2_OUT
17
V2_OUT
13
SDA2
15
SCL2
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
+3VS_CR T_SW
RED_DOC K
GREEN_D OCK
BLUE_DO CK
HSYNC_DOC K
VSYNC_DOCK
CRT_DAT A_DOCK
CRT_CLK _DOCK
CRT_R
CRT_G
CRT_B
CRT_HSYNC
CRT_VSYNC
CRT_DAT A_2
CRT_CLK _2
RED_DOC K <37>
GREEN_D OCK < 37>
BLUE_DO CK <37>
HSYNC_DOC K <37>
VSYNC_DOCK <37>
CRT_DAT A_DOCK <37>
CRT_CLK _DOCK <37>
To CRT CONN.
SEL:High
2017/02/ 22 2018/02/ 22
2017/02/ 22 2018/02/ 22
2017/02/ 22 2018/02/ 22
C
1 2
R635 10K_ 0402_5%
To Docking
SEL:Low
+HDMI_5V_ OUT
12
R302
2.2K_040 2_5%
Compal Secret Data
Compal Secret Data
Compal Secret Data
12
R303
2.2K_040 2_5%
Deciphered Date
Deciphered Date
Deciphered Date
SELx Function
L port 1 is chose
H port 2 is chose
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Custom
Custom
Custom
Date : Sheet o f
Date : Sheet o f
D
Date : Sheet o f
Compal Electronics, Inc.
CRT CONN.
CRT CONN.
CRT CONN.
LA-F241P
LA-F241P
LA-F241P
0.1
0.1
0.1
23 54Friday, June 0 9, 2017
23 54Friday, June 0 9, 2017
23 54Friday, June 0 9, 2017
E
5
4
3
2
1
D D
C C
+3VS
Chip operational mode configuration;
Internal pull down at ~150K?, 3.3V I/O.
L: Control switching mode (default)
H: Automatic switching mode
1 2
R185 4.7K_0201_5%@
+3VS
+3VS
AUX interception disable for Port y (y=1,2)
Internal pull down at ~150K?, 3.3V I/O.
L: AUX interception enable, driver configuration
is set by link training (default)
H: AUX interception disable, driver output with
fixed 800mv and 0dB
M: AUX interception disable, driver output with
fixed 400mv and 0dB
1 2
R186 4.7K_0201_5%@
1 2
R187 4.7K_0201_5%@
1 2
R188 4.7K_0201_5%@
1 2
R183 4.7K_0201_5%
DP_CFG0
PC10
PC20
+3VS +3VS
Automatic EQ disable;
Internal pull down at ~150K?, 3.3V IO
+3VS
+3VS
Output swing adjusment for Port y (y=1,2).
Internal pull down at ~150K?, 3.3V I/O.
1 2
R198 4.7K_0201_5%@
L: Automatic EQ enable (default)
H: Automatic EQ disable
1 2
R189 4.7K_0201_5%@
1 2
R190 4.7K_0201_5%@
1 2
R191 4.7K_0201_5%@
1 2
R194 4.7K_0201_5%@
L:default
H: +20%
M: -16.7%
PI0 PI1
PC11
PC21
1 2
R199 4.7K_0201_5%@
1 2
Auto test enable;
Internal pull down at ~150K?, 3.3V I/O.
+3VS
C160
C159
1
2
0.1U_0201_10V6K
C35
1
2
0.1U_0201_10V6K
C36
1
1
2
2
0.01U_0402_16V7K
Programmable input equalization levels; Internal
pull down at ~150K?, 3.3V I/O.
0.01U_0402_16V7K
R203 4.7K_0201_5%@
L: Auto test disable & input offset cancellation
enable (default)
H: Auto test enable & input offset cancellation enable
M: Auto test disable & input offset cancellation disable
+3VS
L: default, LEQ, compensate channel loss up
to 11.5dB @ HBR2
H: HEQ, compensate channel loss up to 14.5dB
@ HBR2
M: LLEQ, compensate channel loss up to 8.5dB
@ HBR2
1 2
R197 4.7K_0201_5%@
1 2
R196 4.7K_0201_5%@
PEQ
DP_MUX_SEL pin
Port switching control or priority configuration;
Internal pull down at ~150K?, 3.3V I/O.
L: Port1 is selected or with higher priority
(default)
H: Port2 is selected or with higher priority
+3VS
1 2
R5236 2.2K_0402_5%<BOM Structure>
1 2
R5237 2.2K_0402_5%<BOM Structure>
B B
DDI2_CTRL_CK
DDI2_CTRL_DATA
CPU_HDMI_HPD<6>
R5238
<BOM Structure>
100K_0402_5%
1 2
+3VS
DPB_P0
DPB_N0
DPB_P1
DPB_N1
DPB_P2
DPB_N2
DPB_P3
DPB_N3
PI1
PI0
DDI2_CTRL_CK<6>
DDI2_CTRL_DATA<6>
DDI2_CTRL_CK
DDI2_CTRL_DATA
DPB_AUXP
DPB_AUXN
DP_CFG0
PC10
PC11
PC20
PC21
U23
5
VDD33
21
VDD33
30
VDD33
51
VDD33
57
VDD33
6
IN_D0p
7
IN_D0n
9
IN_D1p
10
IN_D1n
12
IN_D2p
13
IN_D2n
15
IN_D3p
16
IN_D3n
4
IN_CA_DET
3
IN_HPD
2
I2C_CTL_EN
1
Pl1/SCL_CTL
60
Pl0/SDA_CTL
22
IN_DDC_SCL
23
IN_DDC_SDA
24
IN_AUXp
25
IN_AUXn
59
CFG0
58
CFG1
56
PC10
55
PC11
54
PC20
53
PC21
11
GND
19
GND
52
GND
61
PAD(GND)
PS8338BQFN60GTR-A0_QFN60_5X9
OUT1_D0p
OUT1_D0n
OUT1_D1p
OUT1_D1n
OUT1_D2p
OUT1_D2n
OUT1_D3p
OUT1_D3n
OUT2_D0p
OUT2_D0n
OUT2_D1p
OUT2_D1n
OUT2_D2p
OUT2_D2n
OUT2_D3p
OUT2_D3n
OUT1_AUXp_SCL
OUT1_AUXn_SDA
OUT2_AUXp_SCL
OUT2_AUXn_SDA
OUT1_CA_DET
OUT1_HPD
OUT2_CA_DET
OUT2_HPD
PEQ
CEXT
REXT
50
49
47
46
45
44
42
41
40
39
37
36
35
34
32
31
26
27
28
29
43
48
OUT2_CA_DET
33
38
18
SW
8
14
PD
17
20
DP_DOCK_P0 <37>
DP_DOCK_N0 <37>
DP_DOCK_P1 <37>
DP_DOCK_N1 <37>
DP_DOCK_P2 <37>
DP_DOCK_N2 <37>
DP_DOCK_P3 <37>
DP_DOCK_N3 <37>
TBT_DP1_P0 <33>
TBT_DP1_N0 <33>
TBT_DP1_P1 <33>
TBT_DP1_N1 <33>
TBT_DP1_P2 <33>
TBT_DP1_N2 <33>
TBT_DP1_P3 <33>
TBT_DP1_N3 <33>
DP_DOCK_AUXP <37>
DP_DOCK_AUXN <37>
TBT_DP1_AUXP <33>
TBT_DP1_AUXN <33>
DP_DOCK_CAD <37>
DP_HPD_DOCK <37>
PEQ
CEXT
REXT
TBT_DP1_HPD <33>
1 2
C57 2.2U_0402_6.3V6M
1 2
R1101 4.99K_0402_0.5%
to Dock ing
to Alpine Ridge
R5234
4.7K_0402_5%
1 2
@
R5235 0_0402_5%
+3VS
1 2
DP_DOCK_SEL <37>
TBT_DP1_AUXN
DP_DOCK_AUXN
TBT_DP1_AUXP
DP_DOCK_AUXP
OUT2_CA_DET
1 2
R126 100K_0201_5%
1 2
R5244 100K_0201_5%
1 2
R129 100K_0201_5%
1 2
R137 100K_0201_5%
1 2
R106 1M_0402_5%
+3VS
CPU_DP2_N0<6>
CPU_DP2_P0<6>
CPU_DP2_N1<6>
A A
CPU_DP2_P1<6>
CPU_DP2_N2<6>
CPU_DP2_P2<6>
CPU_DP2_N3<6>
CPU_DP2_P3<6>
DDI2_AUX_DN<6>
DDI2_AUX_DP<6>
5
CPU_DP2_N0 DPB_N0
CPU_DP2_P0
CPU_DP2_N1
CPU_DP2_P1
CPU_DP2_N2
CPU_DP2_P2
CPU_DP2_N3
CPU_DP2_P3
DDI2_AUX_DN
DDI2_AUX_DP
12
C300 0.1U_0402_16V7K
12
C299 0.1U_0402_16V7K
12
C277 0.1U_0402_16V7K
12
C278 0.1U_0402_16V7K
12
C276 0.1U_0402_16V7K
12
C301 0.1U_0402_16V7K
12
C298 0.1U_0402_16V7K
12
C302 0.1U_0402_16V7K
12
C285 0.1U_0402_16V7K
12
C289 0.1U_0402_16V7K
DPB_P0
DPB_N1
DPB_P1
DPB_N2
DPB_P2
DPB_N3
DPB_P3
DPB_AUXN
DPB_AUXP
4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE S ECRET INFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R& D
AND TRADE S ECRET INFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R& D
AND TRADE S ECRET INFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R& D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTP RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTP RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTP RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2017/02/22 2018/02/22
2017/02/22 2018/02/22
2017/02/22 2018/02/22
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size
Size
Size
Date: Sheet o f
Date: Sheet o f
Date: Sheet o f
Compal Electronics, Inc.
P32-DP MUX
P32-DP MUX
P32-DP MUX
Document Number Re v
Document Number Re v
Document Number Re v
LA-F241P
LA-F241P
LA-F241P
1
24 54Friday, June 09, 2017
24 54Friday, June 09, 2017
24 54Friday, June 09, 2017
0.1
0.1
0.1
A
B
C
D
E
2017/4/17 add diode for ESD request
D2021
HDMI_TX1+
HDMI_TX1-
HDMI_CLK+
HDMI_CLK-
1 1
L05ESDL5V0NA-4 SLP2510P8
HDMI_TX0+
1 2
HDMI_TX0+<33>
HDMI_TX0-<33>
HDMI_TX1+<33>
HDMI_TX1-<33>
HDMI_TX2+<33>
HDMI_TX2-<33>
HDMI_CLK+<33>
HDMI_CLK-<33>
2 2
HDMI_TX0HDMI_TX1+
HDMI_TX1-
HDMI_TX2+
HDMI_TX2HDMI_CLK+
HDMI_CLK-
+3VS
1 2
1 2
1 2
1 2
1 2
1 2
1 2
R861 475_0402_1%
R862 475_0402_1%
R863 475_0402_1%
R864 475_0402_1%
R865 475_0402_1%
R866 475_0402_1%
R867 475_0402_1%
R868 475_0402_1%
5
34
Q2020B
ME2N7002D1KW-G 2N SOT363-6
SB00000SA00
HDMI_TX0+
HDMI_TX0-
HDMI_TX2+ HDMI_TX2+
HDMI_TX2- HDMI_TX2-
L05ESDL5V0NA-4 SLP2510P8
HDMI_R_HPD
+HDMI_5V_OUT
ESD@
1
1
2
2
4
4
5
5
3
3
8
D2022
1
1
2
2
4
4
5
5
3
3
8
D2023 ESD@
3
I/O2
2
GND
1
I/O1
AZC099-04SP.R7G_SOT23-6
SC300003S00
ESD@
10
9
7
6
10
9
7
6
I/O4
VDD
I/O3
9
8
7
6
9
8
7
6
6
5
4
HDMI_TX1+
HDMI_TX1-
HDMI_CLK+
HDMI_CLK-
HDMI_TX0+
HDMI_TX0-
HDMI_R_SDATA
HDMI_R_SCLK
Q2020A
HDMI_HPD<33>
3 3
ME2N7002D1KW use SB00000DH00 symbol
HDMI_SCLK<33>
HDMI_SDATA<33>
4 4
ME2N7002D1KW-G 2N SOT363-6
HDMI_SDATA
ME2N7002D1KW-G 2N SOT363-6
A
ME2N7002D1KW-G 2N SOT363-6
R5172
1M_0402_5%
SB00000SA00
Q2019B
Q2019A
SB00000SA00
12
5
2
+3VS
+3VS
2
HDMI_R_SCLKHDMI_SCLK
34
61
61
SB00000SA00
+3VS
+HDMI_5V_OUT
HDMI_R_HPDHDMI_HPD
R4
20K_0402_5%
1 2
1
D2013
BAW56W-7-F 3P
SC600000L00
2
3
HDMI_R_SDATA_D
HDMI_R_SCLK_D
R338
2.2K_0402_5%
1 2
HDMI_R_SDATA
B
use SC600000B00's footprint
R337
2.2K_0402_5%
1 2
+5VS
U53
1
AP2330W-7_SC59-3
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
OUT
IN
GND
2017/02/22 2018/02/22
2017/02/22 2018/02/22
2017/02/22 2018/02/22
+HDMI_5V_OUT
W=40mils
3
2
Compal Secret Data
Compal Secret Data
Compal Secret Data
1
C802
0.1U_0402_16V4Z
2
Deciphered Date
Deciphered Date
Deciphered Date
D
HDMI connector
+HDMI_5V_OUT
Custom
Custom
Custom
HDMI_R_HPD
HDMI_R_SDATA
HDMI_R_SCLK
HDMI_CLK-
HDMI_CLK+
HDMI_TX2-
HDMI_TX2+
HDMI_TX1-
HDMI_TX1+
HDMI_TX0-
HDMI_TX0+
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Date : Sheet o f
Date : Sheet o f
Date : Sheet o f
Compal Electronics, Inc.
LA-F241P
LA-F241P
LA-F241P
JHDMI1
19
HP_DET
18
+5V
17
DDC/CEC_GND
16
SDA
15
SCL
14
Reserved
13
CEC
12
CK-
11
CK_shield
10
CK+
9
D0-
8
D0_shield
7
D0+
6
D1-
5
D1_shield
4
D1+
3
D2-
2
D2_shield
1
D2+
SUYIN_100042GR019M27SZL
CONN@
DC23 2000 S0 0
HDMI CONN.
HDMI CONN.
HDMI CONN.
E
GND
GND
GND
GND
20
21
22
23
25 54Friday, June 09, 2017
25 54Friday, June 09, 2017
25 54Friday, June 09, 2017
0.1
0.1
0.1
A
HDD Board Conn
1 1
2 2
SATA_CTX_DRX_P0<12>
SATA_CTX_DRX_N0<12>
SATA_CRX_DTX_P0<12>
SATA_CRX_DTX_N0<12>
+3VS
1 2
R15 4.7K_0402_5%@
1 2
R17 4.7K_0402_5%@
1 2
R14 4.7K_0402_5%@
1 2
R20 4.7K_0402_5%@
1 2
R22 4.7K_0402_5%@
1 2
R13 4.7K_0402_5%@
1 2
R21 4.7K_0402_5%@
1 2
R16 4.7K_0402_5%@
1 2
R18 4.7K_0402_5%X76SATA@
1 2
R5247 4.7K_0402_5%
1 2
R23 0_0402_5%
1 2
R5248 0_0402_5%
SATA_CTX_DRX_P0
SATA_CTX_DRX_N0 SATA_PTX_C_DRX_N0
SATA_CRX_DTX_P0
SATA_CRX_DTX_N0
A_DE
B_DE
B_EQ1
A_EQ1
A_EQ2
B_EQ2
A_DE
B_DE
B_EQ1
A_EQ1
A_EQ2
B_EQ2
12
C9 0.01U _0402_16V7K
12
C10 0.01U _0402_16V7K
12
C11 0.01U _0402_16V7K
12
C12 0.01U _0402_16V7K
B
+3VS
12
R12
4.7K_0402_5%
@
SATA_PTX_C_DRX_P0
SATA_PRX_C_DTX_P0
SATA_PRX_C_DTX_N0
B_EQ1
A_EQ1
A_EQ2
B_EQ2
U1
PS8527CTQFN20GTR 2-A1
X76SATA@
SA00007JU10
ZZZ
ALT. GROUP PARTS SATA REDRIVER TI A4DBH
X76@SATATI
X76525BOL51
U1
7
EN
1
A_INp
2
A_INn
5
B_OUTp
4
B_OUTn
19
A_PRE1
17
B_PRE1
18
TEST
3
GND
13
GND
21
EPAD
SN75LVCP601RTJR_ A.4_TQFN20_4X4
SA00003ZX00
X76SATA@
VDD
VDD
A_PRE0
B_PRE0
A_OUTp
A_OUTn
B_INp
B_INn
10
20
6
NC
16
NC
9
8
15
14
11
12
C
+3VS
0.1U_0402_16V7K
0.01U_0402_16V7K
1
1
C8
C7
2
2
1 2
R11 4.99K_0402_1%X76SATA@
1 2
R755 1K_0402_5%
A_DE
B_DE
RDSATA_PTX_DRX_P0
RDSATA_PTX_DRX_N0
RDSATA_PRX_DTX_P0
RDSATA_PRX_DTX_N0
R11
7.5K +-5% 0402
X76SATA@
SD028750180
ZZZ
ALT. GROUP PARTS SATA REDRI PARADE A4DBH
X76@SATAPAR
X76713BOL05
D
RDSATA_PTX_DRX_P0
RDSATA_PTX_DRX_N0
RDSATA_PRX_DTX_N0
RDSATA_PRX_DTX_P0
+5VS_HDD
1
C284
10U_0805_10V4Z
2
1 2
C279 0 .01U_0402_16V7K
1 2
C280 0 .01U_0402_16V7K
1 2
C281 0 .01U_0402_16V7K
1 2
C282 0 .01U_0402_16V7K
+5VS +5VS_HDD
100mils
C286
0.1U_0402_16V4Z
1
1
2
2
RDSATA_PTX_C_DRX_P0
RDSATA_PTX_C_DRX_N 0
RDSATA_PRX_C_DTX_N 0
RDSATA_PRX_C_DTX_P0
+3VS
J2
1 2
JUMP_43X118
@
C287
1000P_0402_50V7K
@
G_INT2
E
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
JHDD1
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
11
12
13
14
15
16
17
18
19
20
G1
G2
G3
G4
ACES_50406-02071-001
CONN@
SP0 10016L0 0
APS G-Sensor
3 3
SOC_SMBCLK<8,18>
SOC_SMBDATA<8,18>
1 2
R521 10K_0402_ 5%@
+3VS
4 4
A
1 2
R522 10K_0402_ 5%
B
+3VS
12
0_0402_5%
@
R523
LIS 3DH
SA0 ->0, Address is 0011 000 (0x30h)
SA0 ->1, Address is 0011 001 (0x32h)
U26
8
CS
4
SCLSPC
6
SDA/SDI/SDO
7
SDO/SA0
16
ADC1
15
ADC2
13
ADC3
2
NC
3
NC
LIS3DHTR_LGA16_3X3
SA00004VF00
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Vdd_IO
+3VS
@
1
14
Vdd
11
INT1
9
INT2
10
RES
5
GND
12
GND
2017/02/22 2018/02/22
2017/02/22 2018/02/22
2017/02/22 2018/02/22
C
1 2
C633 1 0U_0603_6.3V6M
1 2
C628 0 .1U_0402_16V4Z
R5240_0402 _5% @
1 2
G_INT
G_INT2
12
R52510_0402_5% @
0810 add for customer's request
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
G_INT <11>
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size
Size
Size
Custom
Custom
Custom
Date : Sheet o f
Date : Sheet o f
D
Date : Sheet o f
Compal Electronics, Inc.
HDD & G-Sensor
HDD & G-Sensor
Document Number Re v
Document Number Re v
Document Number Re v
HDD & G-Sensor
LA-F241P
LA-F241P
LA-F241P
26 54Friday, June 09, 2017
26 54Friday, June 09, 2017
26 54Friday, June 09, 2017
E
0.1
0.1
0.1
5
4
3
2
1
R413
+3VS_SSD_NGFF+3VS
NFC_DET#
NFC_DFU
NFC_RESET#
SML0CLK_NFC
SML0DATA_NFC
+5V_BST_NFC
TU12@
12
1
C834
4.7U_0603_6.3V6K
2
@
1 2
1 2
+3V_NFC
R6370_0603_5%
R6400_0603_5%
1
C835
0.1U_0402_16V4Z
2
+3V_NFC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
+
C5265
150U_B2_6.3VM_R35M
SGA00009M00
2
for PCIE SSD
CONN@
HB_A511510-SCHR22
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
GND
17
GND
JNFC1
JSSD1
1
GND
3
GND
5
PERn3
7
PERp3
9
GND
11
PETp3
13
PETn3
15
D D
PCIE_CRX_DTX_N12<12>
PCIE_CRX_DTX_P12<12>
PCIE_CTX_DRX_N12<12>
PCIE_CTX_DRX_P12<12>
PCIE_CRX_DTX_P11<12>
PCIE_CRX_DTX_N11<12>
PCIE_CTX_DRX_N11<12>
PCIE_CTX_DRX_P11<12>
C C
SATAXPCIE1< 12>
SOC_SML0CLK<8,28>
B B
SOC_SML0DATA<8,28>
A A
PCIE_CRX_DTX_N12
PCIE_CRX_DTX_P12
PCIE_CTX_DRX_N12
PCIE_CTX_DRX_P12
PCIE_CRX_DTX_P11
PCIE_CRX_DTX_N11
PCIE_CTX_DRX_N11
PCIE_CTX_DRX_P11
13
D
Q2023
G
@
S
2N7002E_SOT23-3
ME2N7002D1KW-G 2N SOT363-6
SOC_SML0CLK
SOC_SML0DATA
ME2N7002D1KW use SB00000DH00 symbol
C838 0.22U_0402_16V7K
C839 0.22U_0402_16V7K
C836 0.22U_0402_16V7K
C837 0.22U_0402_16V7K
CLK_PCIE_N0<10>
CLK_PCIE_P0<10>
+3VS_SSD_NGFF
12
R5275
10K_0402_5%
R5276
1 2
@
0_0402_5%
2
SB00000SA00
6 1
1 2
@
R643 0_0402_5%
SB00000SA00
ME2N7002D1KW-G 2N SOT363-6
1 2
R642 0_0402_5%
NFC_RST#<12>
PLT_RST_BUF#<10,28,31>
1 2
1 2
1 2
1 2
@
SSD_DET#
SSD_ DET #
SATA dev ice 0
PCIE dev ice 1
+3VS
Q53A
2
5
3 4
Q53B
@
PLT_RST_BUF#
MC74VHC1G08DFT2G_SC70-5
CLK_PCIE_N0
CLK_PCIE_P0
R638
499_0402_1%
PCIE_CTX_C_DRX_N12
PCIE_CTX_C_DRX_P12
PCIE_CTX_C_DRX_N11
PCIE_CTX_C_DRX_P11
SSD_DET#
+3VS
R639
499_0402_1%
1 2
1 2
SML0CLK_NFC
SML0DATA_NFC
+3V_NFC
5
1
IN1
VCC
OUT
2
IN2
GND
U57
3
4
R641
0_0402_5%
1 2
@
GND
17
PERn2
19
PERp2
21
GND
23
PETp2
25
PETn2
27
GND
29
PERn1
31
PERp1
33
GND
35
PETn1
37
PETp1
39
GND
41
PERn0/SATA B+
43
PERp0/SATA B-
45
GND
47
PETn0/SATA A-
49
PETp0/SATA A+
51
GND
53
REFCLKn
55
REFCLKp
57
GND
59
N/C
61
PEDET
63
GND
65
GND
67
GND
69
MTG77
LTCX005V800
BELLW_80159-3221_67P-T
1 2
@
R664 0_0402_5%
12
R414
100K_0402_5%
@
BELLW_80159-3221
NFC_RESET#
2
3
2
3.3VAUX
4
3.3VAUX
6
N/C
8
N/C
10
DAS/DSS#
12
3.3VAUX
14
3.3VAUX
16
3.3VAUX
18
3.3VAUX
20
N/C
22
N/C
24
N/C
26
N/C
28
N/C
30
N/C
32
N/C
34
N/C
36
N/C
38
DEVSLP
40
N/C
42
N/C
44
N/C
46
N/C
48
N/C
50
PERST#
52
CLKREQ#
54
PEWake#
56
N/C
58
N/C
60
SUSCLK
62
3.3VAUX
64
3.3VAUX
66
3.3VAUX
68
MTG76
U58
NC1VCC
IN A
GND
SA00004BV00
NL17SZ07DFT2G_SC70-5
@
5
4
Y
+3VS_SSD_NGFF
NGFF_SSD_RST#_R
CLKREQ_PCIE#0
SUSCLK_SSD
+3VS_SSD_NGFF
+3V_NFC+3V_N FC
R644
10K_0402_5%
1 2
R657 0_0402_5%@
1 2
R670 0_0402_5%
ESD@
1 2
C5263 100P_0402_50V8J
1 2
R659 0_0402_5%
R660
1 2
0_0402_5%@
+5VALW
+5VS
12
@
NFC_RESET#
@
1 2
1 2
remove J13 jump for C5265 placement,
the +3VS_SSD_NGFF still need to divide from +3VS on layout
DEVSLP2 <12>
+5V_BST_NFC
R6630_0603_5%
R6620_0603_5%
PLT_RST# <10,33,36,38>
+3VALW
+3VS
NFC_DET#<11>
NFC_DFU<11>
NFC_IRQ<12>
100K_0402_5%
CLKREQ_PCIE#0 <10>
SUSCLK <10,31>
Security Cl assification
Security Cl assification
Security Cl assification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAYNOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAYNOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAYNOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENTEXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS
DEPARTMENTEXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS
DEPARTMENTEXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS
MAYBE USED BY OR DISCLOSED TOANY THIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAYBE USED BY OR DISCLOSED TOANY THIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAYBE USED BY OR DISCLOSED TOANY THIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2017/02/22 2018/02/22
2017/02/22 2018/02/22
2017/02/22 2018/02/22
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
SSD & NFC
SSD & NFC
SSD & NFC
LA-F241P
LA-F241P
LA-F241P
0.1
0.1
27 54Friday, June 09, 2017
27 54Friday, June 09, 2017
1
27 54Friday, June 09, 2017
0.1
5
+3V_LAN
12
D D
LAN_DISABLE_N_R
NOTE: LANWAKE_N must be connected
to PCH's LAN_WAKE# pin.
NOTE: LAN_DISABLE_N must be connected
to PCH's GPIO12/LAN_PHY_PWR_CTRL pin
C C
RL138
@
10K_0402_5 %
CL5
10P_0402_5 0V8J
CLKREQ_PCIE#1<10>
PLT_RST_B UF#<10,27,31>
CLK_PCIE_P1<10>
CLK_PCIE_N1<10>
PCIE_CRX_DTX_P5<12>
PCIE_CRX_DTX_N5<12>
PCIE_CTX_C_DR X_P5<12>
PCIE_CTX_C_DR X_N5<12>
LAN_DISABLE_N<10>
25MHZ_10PF_7 V25000014
3
3
GND
1
4
YL1
2
LAN_LINK#
1 2
@
1
2
1
1
10P_0402_5 0V8J
2
LAN_PME#
CL6
LAN_PME#<10>
RL8 0_0402_5%
GND
CLKREQ_PCIE#1
RL1 0_0402_5%
LAN_SCLK
LAN_SDATA
1 2
RL6 0_0402_5%
TL1 @
TL2 @
TL3 @
TL4 @
LAN_XTALO_RLAN_XTALO
LAN_XTALI
4
1 2
1 2
1 2
1 2
RL5 0_0402_5%
@
RL9 1K_04 02_5%
RL10 3.01K_0402_ 1%
Connect RBIAS through a 3.01 kΩ 1%
pull-down resistor to ground and then
place it no more than one half inch
(0.5” ) away from the PHY.
UL1
S IC WGI219LM SLKJ3 A0 QFN 48P PHY ABO !
<BOM Structure>
SA000081G50
@
PCIE_CRX_C_DT X_P5
CL10.1U _0402_10V7K
PCIE_CRX_C_DT X_N5
CL20.1U _0402_10V7K
LAN_DISABLE_N_RLAN_DISABLE_N
@
LAN_R_ACTIVITY#LAN_ACTIVITY#
JTAG_TDI_LAN
JTAG_TDO_LAN
JTAG_TMS_LAN
JTAG_TCK_LAN
1 2
1 2
UL1
48
CLK_REQ_N
36
PE_RST_N
44
PE_CLKP
45
PE_CLKN
38
PETp
39
PETn
41
PERp
42
PERn
28
SMB_CLK
31
SMB_DATA
2
LANWAKE_N
3
LAN_DISABLE_N
26
LED0
27
LED1
25
LED2
32
JTAG_TDI
34
JTAG_TDO
33
JTAG_TMS
35
JTAG_TCK
9
XTAL_OUT
10
XTAL_IN
30
TEST_EN
12
RBIAS
@
WGI219LM-QRE F-A0_QFN48_6X6
PCIE
SMBUS
JTAG LED
MDI_PLUS0
MDI_MINUS0
MDI_PLUS1
MDI_MINUS1
MDI_PLUS2
MDI
MDI_MINUS2
MDI_PLUS3
MDI_MINUS3
SVR_EN_N
RSVD1_VCC3P3
VDD3P3_IN
VDD3P3_4
VDD3P3_15
VDD3P3_19
VDD3P3_29
VDD0P9_47
VDD0P9_46
VDD0P9_37
VDD0P9_43
VDD0P9_11
VDD0P9_40
VDD0P9_22
VDD0P9_16
VDD0P9_8
CTRL0P9
VSS_EPAD
3
UL1
S IC WGI219LM QREF A0 QFN 4 8P PHY ABO !
@
SA000081G30
LAN_MIDI0+
13
LAN_MIDI0-
14
LAN_MIDI1+
17
LAN_MIDI1-
18
LAN_MIDI2+
20
LAN_MIDI2-
21
LAN_MIDI3+
23
LAN_MIDI3-
24
6
1
1 2
RL4 4.7K_040 2_5%
5
4
15
19
29
47
46
37
43
11
40
22
16
8
+0.9V_LAN_OUT
7
4.7UH_PG031 B-4R7MS_1.1A_20%
49
1U_0402_1 0V6K
UL1
S IC WGI219V SLKJ5 A1 QFN 48P PHY ABO !
@
SA000093420
+3V_LAN
22U_0603_6.3V6M
2
1
CL4
1
2
+0.9V_PHY_CORE
12
LL1
CL8
0.1U_0402_16V4Z
CL7
22U_0603_6.3V6M
1
2
2
1
2
60mil
1
CL15
LAN_PWR_ON
2
1U_0402_6 .3V6K
CL13
0.1U_0402_16V4Z
1
CL14
2
10U_0603_6.3V6M
1
CL9
NOTE: Total requirement Cout>=20uF. ESR<50mohm.
2
@
LAYOUT NOTE: Place LL1, CL7, CL8, CL9, and close to PHY
PD SEL Function
L L Ax to Bx; LEDAx to LEDBx
L H Ax to Cx; LEDAx to LEDCx
H X Hi-Z
1 2
UL3
5
OUT
IN
GND
4
OC
EN
SY6288C20AAC_SOT 23-5
8)4
+$
%$)$'+ 4,.;,; 45,.;
*)) 4 $)$' L.6
J/;-H6%9+ 4 4* > 4 ' K 4
LAN_PWR_ON
1 2
RL14 1K_0402_5%
RL20_ 0603_5% @
1
2
3
1
+3V_LAN+3VALW
60mil
LAN_PWR_E N < 36>
CL10
LAN_MIDI3-
LAN_MIDI3+
LAN_MIDI2-
LAN_MIDI2+
LAN_MIDI1-
LAN_MIDI1+
LAN_MIDI0-
LAN_MIDI0+
@
LAN_LINK#
LAN_ACTIVITY#
RL18
10K_0402_5 %
Compal Secret Data
Compal Secret Data
Compal Secret Data
0.1U_0402_ 16V4Z
1
2
1 2
Deciphered Date
Deciphered Date
Deciphered Date
1
1
CL11
CL12
2
2
0.1U_0402_ 16V4Z
UL2
2
A0+
3
A0-
6
A1+
7
A1-
9
A2+
10
A2-
11
A3+
12
A3-
13
SEL
15
LEDA0
16
LEDA1
42
LEDA2
5
PD
43
PAD_GND
PI3L720ZHEX_TQFN4 2_9X3P5~D
SA00003B200
2
LAN Switch
39
38
B0+
VDD1VDD4VDD8VDD14VDD21VDD30VDD
37
B0-
34
B1+
33
B1-
29
B2+
28
B2-
25
B3+
24
B3-
17
LEDB0
18
LEDB1
41
LEDB2
36
C0+
35
C0-
32
C1+
31
C1-
27
C2+
26
C2-
23
C3+
22
C3-
19
LEDC0
20
LEDC1
40
LEDC2
LAN_MIDI3-_DOCK <37>
LAN_MIDI3+_DOCK <37>
LAN_MIDI2-_DOCK <37>
LAN_MIDI2+_DOCK <37>
LAN_MIDI1-_DOCK <37>
LAN_MIDI1+_DOCK <37>
LAN_MIDI0-_DOCK <37>
LAN_MIDI0+_DOCK <37>
LAN_ACTIVITY#_DOCK < 37>
LAN_LINK#_DOCK <37>
LAN_MIDI3-_RJ45 <29>
LAN_MIDI3+_RJ45 <29>
LAN_MIDI2-_RJ45 <29>
LAN_MIDI2+_RJ45 <29>
LAN_MIDI1-_RJ45 <29>
LAN_MIDI1+_RJ45 <29>
LAN_MIDI0-_RJ45 <29>
LAN_MIDI0+_RJ45 <29>
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number R ev
Size Document Number R ev
Size Document Number R ev
Custom
Custom
Custom
Date : Sheet o f
Date : Sheet o f
Date : Sheet o f
Compal Electronics, Inc.
LA-F241P
LA-F241P
LA-F241P
To Docking.
To Docking.
SEL:Low
SEL:Low
To RJ45 conn
To RJ45 conn
SEL:High
SEL:High
LAN Intel I219
LAN Intel I219
LAN Intel I219
1
28 54Frid ay, June 09, 2017
28 54Frid ay, June 09, 2017
28 54Frid ay, June 09, 2017
0.1
0.1
0.1
+3V_LAN
+3V_LAN
B B
PCH_PCIE_W AKE#<10,33>
+3V_LAN
1 2
RL19 0_0402_5%@
1 2
RL7 10K_0402_5%
1 2
RL12 10K_040 2_5%@
1 2
RL11 10K_040 2_5%@
LAN_PME#
DET_SIG#_R
JTAG_TMS_LAN
JTAG_TCK_LAN
ME2N7002D1KW use SB00000DH00 symbol
SOC_SML0CLK<8,27>
SOC_SML0DATA<8,27>
NOTE: Default SMBus
Address is 0xC8
SOC_SML0CLK
SB00000SA00
ME2N7002D1 KW-G 2N SOT363-6
SOC_SML0DATA LAN_SDATA
2
6 1
QL2A
3 4
QL2B
SB00000SA00
ME2N7002D1 KW-G 2N SOT363-6
SMBUS PULL-UP OPTIONS
SMBUS SPEED
1MHz(Defaul setting)
A A
5
4
RL15 & RL16
499oh m
5
RL16
499_0402_ 1%
RL15
499_0402_ 1%
1 2
1 2
LAN_SCLK
DET_SIG#_R< 6,37>
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TR ANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TR ANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TR ANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
DET_SIG#_R
0.1U_0402_ 16V4Z
1 2
RL13 0_0402_5%
2017/02/22 2018/02/22
2017/02/22 2018/02/22
2017/02/22 2018/02/22
5
4
TR1
3
2
1
LAN Connector
BOTH_GS T5009-E-LF
SP05000 6B10
TR1
1
D D
LAN_MIDI0+_R J45<28>
LAN_MIDI0-_RJ 45<28>
LAN_MIDI1+_R J45<28>
LAN_MIDI1-_RJ 45<28>
LAN_MIDI2+_R J45<28>
LAN_MIDI2-_RJ 45<28>
LAN_MIDI3+_R J45<28>
LAN_MIDI3-_RJ 45<28>
C C
LAN_MIDI0+_R J45
LAN_MIDI0-_RJ 45
LAN_MIDI1+_R J45
LAN_MIDI1-_RJ 45
LAN_MIDI2+_R J45
LAN_MIDI2-_RJ 45
LAN_MIDI3+_R J45
LAN_MIDI3-_RJ 45
0.1U_040 2_16V4Z
1
C335
0.1U_040 2_16V4Z
2
1
C336
2
0.1U_040 2_16V4Z
1
C337
0.1U_040 2_16V4Z
2
1
C338
2
TCT1
2
TD1+
3
TD1-
4
TCT2
5
TD2
6
TD2-
7
TCT3
8
TD3+
9
TD3-
10
TCT4
11
TD4+
TD4-12MX4-
350UH_IH-1 60
SP05000 6F00
@
Place close to TCT pin
MCT1
MX1+
MX1-
MCT2
MX2+
MX2-
MCT3
MX3+
MX3-
MCT4
MX4+
24
23
22
21
20
19
18
17
16
15
14
13
RP3
75_0804 _8P4R_1%
1 8
2 7
3 6
4 5
RJ45_GN D
RJ45_MIDI0+
RJ45_MIDI0-
RJ45_MIDI1+
RJ45_MIDI1-
RJ45_MIDI2+
RJ45_MIDI2-
RJ45_MIDI3+
RJ45_MIDI3-
RJ45_GN D
RJ45_MIDI3-
RJ45_MIDI3+
RJ45_MIDI1-
RJ45_MIDI2-
RJ45_MIDI2+
RJ45_MIDI1+
RJ45_MIDI0-
RJ45_MIDI0+
C339
1 2
1000P_1 206_2KV7K
RJ45_GN D
40mil
JRJ1
8
7
6
5
4
3
2
1
SINGA_2RJ 1660-000111F
CONN@
DC234 007 U0 0
LANGND
EMI@
2
3
D31
SCA0000 2M00
MESC5V0 2BD03_SOT23-3
ESD@
1
PR4-
PR4+
PR2-
PR3-
PR3+
PR2+
PR1-
PR1+
12
GND
11
GND
10
GND
9
GND
12
JP2500
@EMC@
B88069X 9231T203_4P5 X3P2-2
7/2 Add JP2500,J15 for EMI request
40mil
B B
A A
Security Classification
Security Classification
Security Classification
2017/02/ 22 2018/02/ 22
2017/02/ 22 2018/02/ 22
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
2017/02/ 22 2018/02/ 22
3
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Custom
Custom
Custom
Date : Sheet o f
Date : Sheet o f
2
Date : Sheet o f
Compal Electronics, Inc.
LAN Magnetic & RJ45
LAN Magnetic & RJ45
LAN Magnetic & RJ45
LA-F241P
LA-F241P
LA-F241P
0.1
0.1
0.1
29 54Friday, June 0 9, 2017
29 54Friday, June 0 9, 2017
29 54Friday, June 0 9, 2017
1
A
+5VS
60mil 60mil
1 2
@
RC229 0_0603_5%
1
CC2
0.1U_0402_16V4Z
2
7/1 Vendor suggest to DGND
+VDDA
1 1
(output = 300 mA)
SM010014520 3000ma 220ohm@100mhz DCR 0.04
LC1
12
FBMA-L11-201209-221LMA30T_0805
10U_0805_10V4Z
SM010014520 3000ma 220ohm@100mhz DCR 0.04
12
HCB1608KF-121T30 _0603
HP_DOCK_L<37>
HP_DOCK_R<37>
MIC2_DOCK_L<37>
MIC2_DOCK_R<37>
LINE1_LEFT<37>
LINE1_RIGHT<37>
MIC2_DOCK_DET<37>
DOCK_CODEC_DET<37>
HP_DOCK_DET<37>
LC2
FBMA-L11-201209-221LMA30T_0805
LC6
1 2
10U_0805_10V4Z
RC231 1K_0402_5%
RC14 1K_0402_5%
RC236 1K_0402_5%
RC237 1K_0402_5%
RC234 1K_0402_5%
RC235 1K_0402_5%
HP_PLUG#
MIC1_JD
LINEIN_JD<37>
+1.8VS
+VDDA
2 2
3 3
4 4
+VDDA
4.75V
40mil
0.1U_0402_16V4Z
1
1
CC5
CC4
2
2
Place near Pin41
10U_0603_6.3V6M
1
1
CC7
CC126
2
0.1U_0402_16V4Z
CC130
HP_DR_L
12
HP_DR_R
12
MIC2_DR_L
12
MIC2_DR_R
12
LINE1_R_L
12
LINE1_R_R
12
Combo Mic
RC241 39.2K_0402_1%
RC242 20K_0402_1%
RC243 10K_0402_1%
RC27 39.2K_0402_1%
RC28 20K_0402_1%
RC29 10K_0402_1%
2
Place near Pin40
0.1U_0402_16V4Z
1
1
CC131
2
2
0.1U_0402_16V4Z
Place near Pin26
CC137
1 2
CC138
1 2
CC139
1 2
1 2
CC140
1 2
CC135
CC136
1 2
1
CC141
2.2U_0402_6.3V6M
2
+MIC2_VREFO
+MIC1_VREFOL
CC142
CC144
CC145
RC22 20K_0402_1%
CC146 2.2U_0402_6.3V6M
1 2
AUDIO_MUTE#<36>
Place near
codec
12
12
12
12
12
12
T168@
1 2
1 2
1 2
1
2
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
12
SENSE_A
SENSE_B
BEEP#<9>
EC_BEEP#<36>
0.1U_0402_16V4Z
CC6
Place near Pin46
CC132
HP_DC_L
HP_DC_R
MIC2_DC_L
MIC2_DC_R
LINE1_C_L
LINE1_C_R
MIC1_C_L
MIC1_C_R
10mil
10mil
10mil
AUDIO_MUTE#
DGND
1
2
CPVEE
SENSE_A
SENSE_B
+1.8VS_VDDA
20mil
24
23
17
18
22
21
19
20
35
37
29
30
31
27
39
7
15
34
13
14
48
4
49
RC226
22K_0402_5%
<BOM Structure>
RC33
22K_0402_5%
<BOM Structure>
+PVDD_HDA
12
12
BEEP#
EC_BEEP#
20mil
HD Audio Codec
+AVDD_HDA
40
46
UC4
41
LINE2_L
AVDD126AVDD2
PVDD2
PVDD1
LINE2_R
68mA 600mA
MIC2_L
MIC2_R
LINE1_L
LINE1_R
MIC1_L
MIC1_R
CBN
CBP
MIC2_VREFO
MIC1_VREFO_R
MIC1_VREFO_L
LDO1_CAP
LDO2_CAP
LDO3_CAP
JDREF
CPVEE
SENSE A
SENSE B
SPDIFO
DVSS
GND
ALC3225-CG_MQFN48_6X6
SA0000 64R0 0
J5
JUMP_43X39
112
@
J6
JUMP_43X39
112
@
J8
JUMP_43X39
112
@
GND GNDA GND GNDA
BEEP#_R
100P_0402_50V8J
20mil
1
36
DVDD
CPVDD
35mA
SPK_OUT_L+
SPK_OUT_L-
SPK_OUT_R+
SPK_OUT_R-
HPOUT_L
HPOUT_R
SDATA_IN
SDATA_OUT
GPIO0/DMIC_DATA
GPIO1/DMIC_CLK
MONO_OUT
2
2
2
CC3
9
SYNC
RESETB
BCLK
PCBEEP
AVSS2
VREF
AVSS1
B
1
2
0.1U_0402_16V4Z
DVDD_IO
42
43
45
44
32
33
8
5
10
11
6
2
3
47
PD#
12
16
38
28
25
RC230
4.7K_0402_5%
1 2
+3VS_DVDD
1
CC127
2
0.1U_0402_16V4Z
Place near Pin1, 9
HDA_SDIN0_AUDIO
HDA_RST#_R
DMIC_DATA
DMIC_CLK
EC_MUTE#
MONO_IN
CODEC_VREF
10mil
1 2
CC1 1U_0402_6.3V6K
10U_0603_6.3V6M
1
1
CC129
CC128
2
2
SPKL+
SPKL-
SPKR+
SPKR-
HP_LEFT
HP_RIGHT
RC25
1 2
33_0402_5%
HDA_BIT_CLK_R <9>
@EMI@
1 2
1 2
RC239 0_0402_5%
For EMI
CC147 0.1U_0402_16V4Z
1 2
1 2
CC148 2.2U_0402_6.3V6M
1 2
CC149 10U_0603_6.3V6M
@
Place next pin28
J7
JUMP_43X39
2
112
@
J10
JUMP_43X39
2
112
@
J9
JUMP_43X39
2
112
@
MONO_IN
Connect to docking, for the soultion of POP sound issue
DC2
2 1
POP
POP<37>
HCB1608KF-121T30 _0603
SPKR+ <32>
SPKR- <32>
HDA_RST#_R <9>
@EMI@
CC143
22P_0402_50V8J
EC_MUTE# <36>
1 2
HDA_SDOUT_R <9>
HDA_SYNC_R <9>
@
RB751V-40-YS_SOD323-2
DC3
2 1
RB751V-40-YS_SOD323-2
SM010015410 300ma 80ohm@100mhz DCR 0.3
LC4
+3VS
HDA_SDIN0 <9>
HDA_RST#_R
EC_MUTE#
C
SPKL+
SPKL-
Int. Speaker Conn.
RC69 60.4_0603_5%
RC68 60.4_0603_5%
COMBO_MIC
MIC1_JD
2N7002E_SOT23-3
HP_PLUG#
22P_0402_50V8J
+3VS
HCB1608KF-121T30 _0603
COMBO_MIC
1 2
1 2
HP_PLUG#
1 2
@
RC19 0_0402_5%
D
Q25
S
@
12
RC200_0402_5%
2
CC150
@RF@
1
EMI@
LC10
1 2
PCH_DMIC_DATA<9>
RC227
40mil
HPOUT_L_1HP_LEFT HPOUT_L_2
HPOUT_R_1HP_RIGHT
3
13
2
G
FCM1005KF-301T01 _2P
1 2
+3VS_DMIC
PCH_DMIC_CLK<9>
DMIC_CLK
DMIC_DATA
PBY160808T-121Y-N_2P
EMC@
1 2
1 2
EMC@
RC228
PBY160808T-121Y-N_2P
2
3
DC4
AZ5125-02S.R7G_SOT23-3
@ESD@
1
7/2 change to 0ohm for EMI request
LC11 0_0603_5%
1 2
EMI@
LC12 0_0603_5%
1 2
EMI@
2
DC5
AZ5125-02S.R7G_SOT23-3
ESD@
1
LC7
1 2
NBQ100505T-800Y-N
RC32
22K_0402_5%
<BOM Structure>
1 2
12
CC430
4.7U_0402_6.3V6M
SM01000II00
LC9
EMI@
DMIC_CLK_R
1
C5232
.1U_0402_16V7K
2
RF@
R488 33_0402_5%@
1 2
1 2
R485 33_0402_5%@
R486 BLM15BD121SN1D_2P
1 2
1 2
R487 BLM15BD121SN1D_2P
SPKL+_1
SPKL-_1
+MIC1_VREFOL
1 2
1 2
D
JSPK1
1
1
2
2
3
G1
4
G2
3800-F02N-00R
CONN@
HPOUT_R_2
RC18
2.2K_0402_5%
12
RC244 1K_0402_5%
RC30
22K_0402_5%
<BOM Structure>
7/2 change to PBY160808T for EMI request
EMI@
SM010028800 2000 ma 120ohm@100mhz DCR 0.1
+3VS_DMIC
DMIC_CLK_R
DMIC_DATA_R
1
1
C5253
C5252
@ESD@
2
.1U_0402_16V7K
2
@ESD@
DMIC_CLK_R
DMIC_DATA_R
.1U_0402_16V7K
EMI@
EMI@
Combo Jack
JHP1
3
6
1
2
4
5
SINGA_2SJ-E960-001F
1 2
CC151
2.2U_0402_6.3V6M
1 2
CC152
2.2U_0402_6.3V6M
Digital MIC CONN
JDMIC1
1
1
2
2
3
5
3
G1
6
4
G2
4
ACES_50208-0040N-001
CONN@
SP0200 0K2 00
R486
@
0_0402_5%
R487
@
0_0402_5%
MIC1_C_L
MIC1_C_R
E
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.
MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.
A
B
C
MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.
2017/02/22 2018/02/22
2017/02/22 2018/02/22
2017/02/22 2018/02/22
D
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
HD Audio Codec_ALC3225X
HD Audio Codec_ALC3225X
HD Audio Codec_ALC3225X
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Custom
Custom
Custom
LA-F241P
LA-F241P
LA-F241P
Date: Sheet of
Date: Sheet of
Date: Sheet of
E
30 54Friday, June 09, 2017
30 54Friday, June 09, 2017
30 54Friday, June 09, 2017
0.1
0.1
0.1
A
B
C
D
E
C)H6%
USB20_P5
USB20_P5<12>
60mil
R212
1 2
1 1
+3VALW
C165
1U_0402_6.3V6K
1
<BOM Structure>
2
WLAN_ON<36>
+3VS_WLAN
2 2
+3VS_3G +3VALW +3VS_3G
R406 10K _0402_5%3G@
3 3
TU149 @
TU150 @
TU151 @
TU152 @
USB20_N9
USB20_P9
USB20_N9<12>
USB20_P9<12>
4 4
0_0805_5%@
<BOM Structure>
10K_0402_5%
TU157 @
FOR ME906
ANT_TUNE_0_AP
ANT_TUNE_1_AP
ANT_TUNE_2_AP
ANT_TUNE_3_AP
+3VS_3G
1 2
R420 0_0 402_5%@
1 2
R421 0_0 402_5%@
+3VS_WLAN+3VS
1
C458
4.7U_0603_6.3V6K
2
<BOM Structure>
U9
5
IN
4
EN
SY6288C20AAC_SOT23-5
<BOM Structure>
R3809
WLAN_PME#
12
12
+3VS_3G
MINI_DET#<11>
1 2
R621 0_04 02_5%
1 2
R622 0_04 02_5%
1 2
R623 0_04 02_5%
1 2
R624 0_04 02_5%
1 2
R416 10K_0402_5%3G@
USB20_N9
USB20_P9
1
@
C459
2
.1U_0402_16V7K
W=60mils
1
OUT
2
GND
3
OC
WAKE_OUT_WW AN
TU156 @
1 2
R402 10K _0402_5%
3G@
MINI_DET#
12
R527415K_0402_1% 3G@
C52033P_0402_50V8K @
12
C445330P_0402_50V7K @
12
C446330P_0402_50V7K @
12
C447330P_0402_50V7K @
12
C448330P_0402_50V7K @
@
@
@
@
TU153 @
TU154 @
USB20_N9_D
USB20_P9_D
U59
1
Y+
2
Y-
3
GND
4
M-
5
M+
PI3USB102ZLEX_TQFN10_1P6X1P3@
SEL
Vdd
OE
D+
1
C460
.1U_0402_16V7K
2
<BOM Structure>
+3VS_WLAN
TU155 @
USB20_P9_L
USB20_N9_L
WAKE_OUT_WW AN
BODYSAR_DET#
10
9
8
7
6
D-
3G_CONFIG3
3G_CONFIG0
ANT_TUNE_0
ANT_TUNE_1
ANT_TUNE_2
ANT_TUNE_3
3G_RESET#
3G_CONFIG1
3G_CONFIG2
R419 10K _0402_5%@
R418 10K _0402_5%@
R417 10K _0402_5%@
1 2
(link to PICE Port 4)
PCIE X1
(From PCH CLKOUT5)
PCIE CLK
USB20_N9_D
USB20_P9_D
R318
0_0402_5%
@
USB2 P5
(For BT)
JMINI2
1
CONFIG_3
3
Ground
5
Ground
7
USB_D+
9
USB_D-
11
Ground
13
CONFIG_0
15
Wake_On_WWAN#
17
BODYSAR_N
19
Ground
21
NC
23
NC
25
Ground
27
NC
29
NC
31
Ground
33
NC
35
NC
37
Ground
39
NC
41
NC
43
Ground
45
NC
47
NC
49
Ground
51
ANTCTL0
53
ANTCTL1
55
ANTCTL2
57
ANTCTL3
59
Reset#
61
CONFIG_1
63
Ground
65
Ground
67
CONFIG_2
69
GND
BELLW_80149-3223_67P CONN@
12
12
12
+3VALW
PCIE_CTX_C_DRX_P6<12>
PCIE_CTX_C_DRX_N6<12>
PCIE_CRX_DTX_P6<12>
PCIE_CRX_DTX_N6<12>
CLK_PCIE_P2<10>
CLK_PCIE_N2<10>
CLKREQ_PCIE#2<10>
WLAN_PME#<31,3 6>
PCIE_CTX_C_GRX_N8< 12>
PCIE_CTX_C_GRX_P8<12>
PCIE_CRX_GTX_N8< 12>
PCIE_CRX_GTX_P8<12>
CLK_PCIE_N5<10>
CLK_PCIE_P5<10>
3.3V
3.3V
Power_On_Off
W_DISABLE#
LED#
Reserved
Reserved
Reserved
GPS_DISABLE#
Reserved
UIM-RESET
UIM-CLK
UIM-DATA
UIM-PWR
NC
Reserved
Reserved
Reserved
Reserved
Reserved
NC
NC
NC
NC
NC
Reserved
Reserved
Reserved
SIM_DET
NC
3.3V
3.3V
3.3V
GND
+3VALW
3G_OFF# <31,36>
+3VS
Truth Table
SEL OE# Y+ Y-
X
H
Hi-Z
L
L
M+ M -
D+
H
L
USB20_N5
USB20_N5<12>
PCIE_CTX_C_DRX_P6
PCIE_CTX_C_DRX_N6
PCIE_CRX_DTX_P6
PCIE_CRX_DTX_N6
CLK_PCIE_P2
CLK_PCIE_N2
CLKREQ_PCIE#2 E51RXD_P80CLK_R
WLAN_PME#
PCIE_CRX_GTX_N8
PCIE_CRX_GTX_P8
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
GPS_DISABLE#
UIM_RST
UIM_CLK
UIM_DATA
UIM_PWR
1 2
3G@
R401 47K_040 2_5%
3G_OFF#
+3VS_3G
Hi-Z
D-
JNGFF1
1
GND_1
3
USB_D+
5
USB_D-
7
GND_7
9
SDIO_CLK
11
SDIO_CMD
13
SDIO_DAT0
15
SDIO_DAT1
17
SDIO_DAT2
19
SDIO_DAT3
21
SDIO_WAKE
23
SDIO_RST
25
GND_33
27
PET_RX_P0
29
PET_RX_N0
31
GND_39
33
PER_TX_P0
35
PER_TX_N0
37
GND_45
39
REFCLK_P0
41
REFCLK_N0
43
GND_51
45
CLKREQ0#
47
PEWAKE0#
49
GND_57
51
RSVD/PCIE_RX_P1
53
RSVD/PCIE_RX_N1
55
GND_63
57
RSVD/PCIE_TX_P1
59
RSVD/PCIE_TX_N1
61
GND_69
63
RSVD_71
65
RSVD_73
67
GND_75
69
GND2
BELLW_80152-3221
CONN@
SP070013E00
+3VS_3G
change to 47K for ME906
3G_OFF# <31,36>
USB20_P9_D
USB20_N9_D
KEY E
SUSCLK(32KHz)
W_DISABLE2#
W_DISABLE1#
UIM_CLK
UIM_RST
UIM_PWR
UIM_CLK
UIM_RST
UIM_DATA
UIM_PWR
UART_WAKE
+3VS_WLAN
2
3.3VAUX_2
4
3.3VAUX_4
6
LED1#
8
PCM_CLK
10
PCM_SYNC
12
PCM_OUT
14
PCM_IN
16
LED2#
18
GND_18
20
22
UART_TX
24
UART_RX
26
UART_RTS
28
UART_CTS
30
CLink_RST
32
CLink_DATA
34
CLink_CLK
36
COEX3
38
COEX2
40
COEX1
42
44
PERST0#
46
48
50
I2C_DAT
52
I2C_CLK
54
I2C_IRQ
56
RSVD_64
58
RSVD_66
60
RSVD_68
62
RSVD_70
64
3.3VAUX_72
66
3.3VAUX_74
68
GND1
JSIM1
RFU4RFU
3
CLK
2
RST
1
VCC
TAI_CPMPAT5-08GLBS1ZZ4H0
LTCX0060A00
3G@
C523 33P_040 2_50V8K
3G@
C524 33P_040 2_50V8K
3G@
C525 33P_040 2_50V8K
3G@
C526 33P_040 2_50V8K
3G@
1 2
C809 1U_0402_10V6K
MCF12102G900-T_4P
2
2
L37
3
1
1
4
CL_RST#_R
CL_DATA_R
CL_CLK_R
@
SUSCLK_R
WL_RST#_R
WL_OFF#
WG_RST#_R
WG_PME#
CONN@
GND
USB20_P9_L
3
EMI@
USB20_N9_L
4
T3801@
T3802@
PH +3VS at SOC side, for win7 USB3 debug
UART_2_CRXD_DTXD
0_0402_5%
R625
0_0402_5%
R626
T3803@
T3804@
T3805
T3809@
T3810@
1 2
R873 0_0402_5%@
8
7
I/O
6
VPP
5
12
UART_2_CTXD_DRXD
12
1 2
1 2
R445 0_0402_5%
VPRO@
1 2
R444 0_0402_5%
VPRO@
R443 0_0402_5%
VPRO@
12
R5252 0_0402_5%@
1 2
@
12
R440 0_0402_5%
@
1 2
@
R441 0_0402_5%
1 2
@
R442 0_0402_5%
UIM_DATA
20mil
+19VB
3G_PWR_ON#<36>
ME2N7002D1KW-G 2N SOT363-6
R8720_0402_5%
470K_0402_5%
R620
3G@
3G_PWR_ON#
SB00000SA00
33P_0402_50V8K
R158
100K_0402_5%
2
3G@
1
12
Q51B
C522
@EMI@
UART_2_CRXD_DTXD <11>
UART_2_CTXD_DRXD <11>
CL_RST# <8>
CL_DATA <8>
CL_CLK <8>
E51RXD_P80CLK mulitplexed with
BT_ON function
SUSCLK <10,27>
PLT_RST_BUF# <10,27,28,31>
E51RXD_P80CLK <36>
WL_OFF# <36>
12
E51TXD_P80DATA <36>
PLT_RST_BUF# <10,27,28,31>
CLKREQ_PCIE#5 <10>
WLAN_PME# <31,36>
+3VALW TO +3VS_3G
U52
DMN3030LSS-13_SOP8L-8
8
4.7U_0603_6.3V6K
7
C812
5
34
3G@
5
3G@
2
C444
1
330P_0402_50V7K
0.1U_0402_16V4Z
3G@
10mil
3G@
C807
1
2
4
1
C813
0.1U_0603_25V7K
3G@
2
3G@
1
C806
2
1U_0402_10V6K
1
2
36
3G@
1
C808
2
22U_0805_6.3V6M
NGFF WL+BT+W IGIG (KEY E)
240mil
R616
470_0603_5%
3G@
1 2
61
3G_PWR_ON#3G_PW R_ON#_R
2
Q51A
ME2N7002D1KW-G 2N SOT363-6
3G@ SB00000SA00
ME2N7002D1KW use SB00000DH00 symbol
+3VS_3G
1
1
3G@
+
C803
2
220U 4V Y D2 ESR15M
1
3G@
3G@
+
+
C804
2
C805
2
220U 4V Y D2 ESR15M
220U 4V Y D2 ESR15M
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R& D
AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R& D
AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R& D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PALELECT RONICS, INC. NEITHER THIS SH EET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PALELECT RONICS, INC. NEITHER THIS SH EET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PALELECT RONICS, INC. NEITHER THIS SH EET NOR THE INFORMATION IT CONTAINS
MAYB E USED BY OR DISCLOSED TO ANY T HIRD PARTY WITHOUT P RIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.
MAYB E USED BY OR DISCLOSED TO ANY T HIRD PARTY WITHOUT P RIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.
A
B
MAYB E USED BY OR DISCLOSED TO ANY T HIRD PARTY WITHOUT P RIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.
C
2017/02/22 2018/02/22
2017/02/22 2018/02/22
2017/02/22 2018/02/22
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
mini Card & LTE CONN.
mini Card & LTE CONN.
mini Card & LTE CONN.
Size
Size
Size
Document Number R e v
Document Number R e v
Document Number R e v
Custom
Custom
Custom
LA-F241P
LA-F241P
LA-F241P
Date : Sheet o f
Date : Sheet o f
Date : Sheet o f
E
31 54Friday, June 09, 2 017
31 54Friday, June 09, 2 017
31 54Friday, June 09, 2 017
0.1
0.1
0.1
A
B
C
D
E
USB20_N 2< 12>
1
1
L36
2
2
2
1
2
1
MCF1210 2G900-T_4P
3
4
3
4
1 1
PCH_USB 3_RX2_P<12>
PCH_USB 3_RX2_N<12>
PCH_USB 3_TX2_P<1 2>
2 2
PCH_USB 3_TX2_N<12>
PCH_USB 3_TX2_P
PCH_USB 3_TX2_N
C798 0.1U_0402_16 V7K
C799 0.1U_0402_16 V7K
USB20_P 2<12>
PCH_USB 3_RX2_P
PCH_USB 3_RX2_N
PCH_USB 3_TX2_P_C
12
PCH_USB 3_TX2_N_C
12
USB20_P 2
L48
L49
2
1
2
1
MCF1210 2G900-T_4P
MCF1210 2G900-T_4P
4
3
3
EMI@
4
3
EMI@
4
U2DN2_LUSB20_N 2
4
EMI@
3
U2DP2_L
U3RXDP2
U3RXDN2
U3TXDP2
U3TXDN2
USB_PW R_EN#< 32,36,37> USB_OC0 # <12,32>
For ESD request
D37
U3RXDN2
U3RXDP2
U3TXDN2
U3TXDP2 U3TXDP2
U2DP2_L
1
1
2
2
4
4
5
5
3
3
8
L05ESDL 5V0NA-4 SLP251 0P8
D44 ESD@
3
I/O2
2
GND
1
I/O1
AZC099-0 4SP.R7G_SOT23 -6
SC30000 3S00
+5VALW +USB3_V CCA
U33
1
GND
VOUT
2
VOUT
VIN
VIN3VOUT
4
FLG
EN
SY6288D10 CAC _MSOP8
C395
0.1U_0402_16V4Z
SA00004 KB10
1
2
ESD@
9
10
9
7
6
I/O4
VDD
I/O3
U3RXDN2
8
U3RXDP2
7
U3TXDN2
6
+USB3_V CCA
6
5
U2DN2_L
4
0810 for ESD request, change to SC300003S00
use SC300001G00's footprint
100U_B2 _6.3VM_R35M
W=40mils
8
7
6
5
+USB3_V CCA
C398
W=80mils
1
+
2
USB_OC0 #
470P_0402_50V7K
2
1
JUSB1
U3TXDP2
U3TXDN2
C399
U2DP2_L
U2DN2_L
U3RXDP2
U3RXDN2
9
1
8
3
7
2
6
4
5
SSTX+
VBUS
SSTXD+
GND
DSSRX+
GND
SSRX-
CONN@
GND
GND
GND
GND
10
11
12
13
USB3.0 Conn.(MB)
IO Board Conn(For FFC,FPC)
1 2
+3VALW
+3VS
+3VALW
1
C833
3 3
4 4
1U_0402 _10V6K @
2
SYSON<13,36,40,45>
20mil(250mA)
U60
5
OUT
IN
GND
4
OC
EN
SY6288C20 AAC_SOT23-5
@
+3V_USB
1
2
3
2
C832
1
4.7U_060 3_6.3V6K@
USB_OC0 #<12,32 >
PCH_USB 3_RX1_N<12>
PCH_USB 3_RX1_P<12>
PCH_USB 3_TX1_N<12>
PCH_USB 3_TX1_P<1 2>
USB20_P 1<12>
USB20_N 1< 12>
PCH_USB 3_RX4_N<12>
PCH_USB 3_RX4_P<12>
PCH_USB 3_TX4_N<12>
PCH_USB 3_TX4_P<1 2>
USB20_P 4<12>
USB20_N 4< 12>
USB_CHA RGE_2A#<36>
USB_PW R_EN#< 32,36,37>
USB_CHA RGE_CB0<36,37 >
USB_CEN<3 6>
SPKR-<30>
SPKR+<3 0>
SELCDP<3 6,37>
+3V_USB
20mil
+5VALW
0.1U_040 2_25V6
USB_OC0 #
USB20_P 1
USB20_N 1
USB20_P 4
USB20_N 4
USB_PW R_EN#
USB_CEN
SPKR-
SPKR+
68P_040 2_50V8J
@
R666 0_ 0402_5%
1 2
R661 0_04 02_5%@
12
C5233
EMI@
1
C5240
RF@
2
JIO1
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
32
GND2
31
GND1
32
ACES_51 547-03201-W 01
CONN@
34
33
Security Classification
Security Classification
Security Classification
2017/02/ 22 2018/02/ 22
2017/02/ 22 2018/02/ 22
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
2017/02/ 22 2018/02/ 22
C
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Custom
Custom
Custom
Date : Sheet o f
Date : Sheet o f
D
Date : Sheet o f
Compal Electronics, Inc.
USB3.0 & IO/B
USB3.0 & IO/B
USB3.0 & IO/B
LA-F241P
LA-F241P
LA-F241P
0.1
0.1
0.1
32 54Friday, June 0 9, 2017
32 54Friday, June 0 9, 2017
32 54Friday, June 0 9, 2017
E
5
4
3
2
1
PCIE_CTX_C_GRX_P9<12>
PCIE_CTX_C_GRX_N9<12>
PCIE_CTX_C_GRX_P10<12>
PCIE X2 Bus
D D
(Link to CPU Port 1~4)
PCIE CLK
(From PCH CLKOUT0)
from PS8338
+3.3V_LC
R5127
R5126
12
12
TBT@
TBT@
10K_0402_5%
C C
HDMI_SCLK
HDMI_SDATA
TBT_I2C_SDA
TBT_I2C_SCL
TBT_PCIE_W AKE_N
TBT_CIO_PLUG_ EVENT#
SLP_S3#
BATLOW#
TBTA_I2C_INT
TBT_POC_GPIO_1
CFG1 PU is HDMI MODE
B B
A A
TBT_SRC_ CFG1
RTD3_CIO_PW R_EN_R
RTD3_USB_ PWR_EN_R
TBT_TMU_ CLK_OUT
TBT_FORCE_ PWR_R
PS8338 Internal PD
TBT_DP1_H PD
TBTA_LSTX
TBTA_HPD
TBTA_LSRX
TBT_SNK1_ DDC_CLK
SNK0_CONFIG1
PB_LSTX
PB_LSRX
PB_DPSRC_H PD
For BAD40_SL For P6 EVT For P6 PVT
U5004
12
TBT@
10K_0402_5%
R5129
R5128
12
TBT@
+3.3V_LC
10K_0402_5%
10K_0402_5%
TBT_TDI
TBT_TMS
TBT_TCK
TBT_TDO
R5201 2.2K_0402_5%TBT@
R5202 2.2K_0402_5%TBT@
R5137 2.2K_0402_5%TBT@
R5138 2.2K_0402_5%TBT@
R5249 10K_0402_ 5%@
R5133 10K_0402_ 5%TBT@
R5135 10K_0402_ 5%@
R5134 10K_0402_ 5%TBT@
R5131 10K_0402_ 5%TBT@
R5136 10K_0402_ 5%TBT@
R5144 10K_0402_ 5%TBT@
R5141 10K_0201_ 5%@
R5142 10K_0201_ 5%@
1 2
R5264 100K_0201_5%TBT@
1 2
R5265 100K_0201_5%TBT@
1 2
R5139 100K_0402_5%TBT@
1 2
R5140 10K_0402_5%T BT@
1 2
R5143 100K_0402_5%@
1 2
R5147 1M_0402_1%T BT@
1 2
R5145 100K_0402_5%TBT@
1 2
R5148 1M_0402_1%T BT@
1 2
R5146 100K_0402_5%TBT@
1 2
R5149 100K_0402_5%TBT@
1 2
R5150 1M_0402_1%T BT@
1 2
R5151 1M_0402_1%T BT@
1 2
R5152 100K_0402_5%TBT@
INTEL SP ref sch v1.2
JTAG1
1
1
2
2
3
3
4
4
5
5
6
6
7
GND
8
GND
ACES_50228-00 67N-001
CONN@
12
12
12
12
12
12
12
12
12
12
12
12
12
U5004
+3VS_TBT
+3.3V_TBT_SX
PCIE_CTX_C_GRX_N10<12>
CLK_PCIE_P3<10>
CLK_PCIE_N3<10>
CLKREQ_PCIE#3<10>
TBT_DP1_P 0<24>
TBT_DP1_N 0<24 >
TBT_DP1_P 1<24>
TBT_DP1_N 1<24 >
TBT_DP1_P 2<24>
TBT_DP1_N 2<24 >
TBT_DP1_P 3<24>
TBT_DP1_N 3<24 >
TBT_DP1_AUXP<24>
TBT_DP1_AUXN<24>
TBT_DP1_H PD<24>
TBT_DP1_C TRL_CLK<6>
TBT_DP1_C TRL_DATA<6>
USB3_A_TRX_DT X_P1<35>
USB3_A_TRX_DT X_N1<35>
USB3_A_TTX_C_ DRX_P1<35>
USB3_A_TTX_C_ DRX_N1< 35>
USB3_A_TTX_C_ DRX_P0<35>
USB3_A_TTX_C_ DRX_N0< 35>
USB3_A_TRX_DT X_P0<35>
USB3_A_TRX_DT X_N0<35>
TBT_A_AUX_P_C<35>
TBT_A_AUX_N_C<35>
TBT_A_USB20 _P<35>
TBT_A_USB20 _N<35>
TBTA_LSTX<3 5>
TBTA_LSRX<35>
TBTA_HPD<35>
U5004
R5112 0_0 402_5%TBT@
C4016 0.1U _0402_16V7KTBT@
C4015 0.1U _0402_16V7KTBT@
C4023 0.1U _0402_16V7KTBT@
C4022 0.1U _0402_16V7KTBT@
C4020 0.1U _0402_16V7KTBT@
C4018 0.1U _0402_16V7KTBT@
C4021 0.1U _0402_16V7KTBT@
C4019 0.1U _0402_16V7KTBT@
C4025 0.1U _0402_16V7KTBT@
C4024 0.1U _0402_16V7KTBT@
C5179 0.22U_0201_ 6.3V6MTBT @
C5180 0.22U_0201_ 6.3V6MTBT @
C5181 0.22U_0201_ 6.3V6MTBT @
C5182 0.22U_0201_ 6.3V6MTBT @
C5183 0.1U _0402_16V7KTBT@
C5184 0.1U _0402_16V7KTBT@
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
DDC: 3.3 V
PU @ SOC side
R5153 14K_040 2_1%
12
TBT@
R5098 4 .75K_0402_0.5%
1 2
1 2
1 2
1 2
1 2
1 2
R5099 499_0402 _1%
PCIE_CTX_C_GRX_P9
PCIE_CTX_C_GRX_N 9
PCIE_CTX_C_GRX_P1 0
PCIE_CTX_C_GRX_N 10
CLKREQ_PCIE#3_ R
TBT_DP1_P 0_C
TBT_DP1_N 0_C
TBT_DP1_P 1_C
TBT_DP1_N 1_C
TBT_DP1_P 2_C
TBT_DP1_N 2_C
TBT_DP1_P 3_C
TBT_DP1_N 3_C
TBT_DP1_AUXP_ C
TBT_DP1_AUXN _C
TBT_DP1_C TRL_CLK
TBT_DP1_C TRL_DATA
TBT_SNK1_ DDC_CLK
SNK0_CONFIG1
DPSNK_RBIAS
12
TBT@
TBT_TDI
TBT_TMS
TBT_TCK
TBT_TDO
TBT_RBIAS
TBT_RSENS E
USB3_A_TTX_DR X_P1
USB3_A_TTX_DR X_N1
USB3_A_TTX_DR X_P0
USB3_A_TTX_DR X_N0
TBT_A_AUX_P
TBT_A_AUX_N
PA_USB2_RBIAS PB_USB2_RBIAS
12
TBT@
U5004A
Y23
PCIE_RX0_P
Y22
PCIE_RX0_N
T23
PCIE_RX1_P
T22
PCIE_RX1_N
M23
PCIE_RX2_P
M22
PCIE_RX2_N
H23
PCIE_RX3_P
H22
PCIE_RX3_N
V19
PCIE_REFCLK_100_IN_P
T19
PCIE_REFCLK_100_IN_N
AC5
PCIE_CLKREQ_N
AB7
DPSNK0_ML0_P
AC7
DPSNK0_ML0_N
AB9
DPSNK0_ML1_P
AC9
DPSNK0_ML1_N
AB11
DPSNK0_ML2_P
AC11
DPSNK0_ML2_N
AB13
DPSNK0_ML3_P
AC13
DPSNK0_ML3_N
Y11
DPSNK0_AUX_P
W11
DPSNK0_AUX_N
AA2
DPSNK0_HPD
Y5
DPSNK0_DDC_CLK
R4
DPSNK0_DDC_DATA
AB15
DPSNK1_ML0_P
AC15
DPSNK1_ML0_N
AB17
DPSNK1_ML1_P
AC17
DPSNK1_ML1_N
AB19
DPSNK1_ML2_P
AC19
DPSNK1_ML2_N
AB21
DPSNK1_ML3_P
AC21
DPSNK1_ML3_N
Y12
DPSNK1_AUX_P
W12
DPSNK1_AUX_N
Y6
DPSNK1_HPD
Y8
DPSNK1_DDC_CLK
N4
DPSNK1_DDC_DATA
Y18
DPSNK_RBIAS
Y4
TDI
V4
TMS
T4
TCK
W4
TDO
H6
RBIAS
J6
RSENSE
A15
PA_RX1_P
B15
PA_RX1_N
A17
PA_TX1_P
B17
PA_TX1_N
A19
PA_TX0_P
B19
PA_TX0_N
B21
PA_RX0_P
A21
PA_RX0_N
Y15
PA_DPSRC_AUX_P
W15
PA_DPSRC_AUX_N
E20
PA_USB2_D_P
D20
PA_USB2_D_N
A5
PA_LSTX
A4
PA_LSRX
M4
PA_DPSRC_HPD
H19
PA_USB2_RBIAS
AC23
THERMDA
AB23
THERMDA
V18
PCIE_ATEST
AC1
TEST_EDM
L15
FUSE_VQPS_64
N15
FUSE_VQPS_128
C23
MONDC_CIO_0
C22
MONDC_CIO_1
AR4C_FC-CSP337
@
PCIE_TX0_P
PCIE_TX0_N
PCIE_TX1_P
PCIE_TX1_N
PCIE_TX2_P
PCIE_TX2_N
PCIE_TX3_P
DPSRC_ML0_P
DPSRC_ML0_N
DPSRC_ML1_P
DPSRC_ML1_N
DPSRC_ML2_P
DPSRC_ML2_N
DPSRC_ML3_P
DPSRC_ML3_N
DPSRC_AUX_P
DPSRC_AUX_N
SOURCE PORT 0
DPSRC_RBIAS
LC GPIOPOC GPIO
TEST_PWR_GOOD
Misc
XTAL_25_OUT
PB_DPSRC_AUX_P
PB_DPSRC_AUX_N
PORT B
PB_USB2_D_P
PB_USB2_D_N
PB_DPSRC_HPD
POC
PB_USB2_RBIAS
MONDC_DPSNK_0
MONDC_DPSNK_1
MONDC_DPSRC
PCIE_TX3_N
PERST_N
PCIE_RBIAS
DPSRC_HPD
GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
GPIO_6
GPIO_7
GPIO_8
POC_GPIO_0
POC_GPIO_1
POC_GPIO_2
POC_GPIO_3
POC_GPIO_4
POC_GPIO_5
POC_GPIO_6
TEST_EN
RESET_N
XTAL_25_IN
EE_DI
EE_DO
EE_CS_N
EE_CLK
PB_RX1_P
PB_RX1_N
PB_TX1_P
PB_TX1_N
PB_TX0_P
PB_TX0_N
PB_RX0_P
PB_RX0_N
PB_LSTX
PB_LSRX
MONDC_SVR
ATEST_P
ATEST_N
USB2_ATEST
PCIe GEN3
SINK PORT 0
SINK PORT 1
MISC
Port A
TBT PORTS
POC
DEBUG
PCIE_CRX_C_GTX_P9
V23
PCIE_CRX_C_GTX_N 9
V22
PCIE_CRX_C_GTX_P1 0 PCIE_C RX_GTX_P10
P23
PCIE_CRX_C_GTX_N 10
P22
K23
K22
F23
F22
TBT_RST# _R
L4
PCIE_RBIAS
N16
DPSRC_ML0+
R2
DPSRC_ML0-
R1
DPSRC_ML1+
N2
DPSRC_ML1-
N1
DPSRC_ML2+
L2
DPSRC_ML2-
L1
DPSRC_ML3+
J2
DPSRC_ML3-
J1
W19
Y19
HDMI_HPD
G1
DPSRC_RBIAS
N6
U1
U2
TBT_EE_W P_N
V1
TBT_TMU_ CLK_OUT
V2
TBT_PCIE_W AKE_N
W1
TBT_CIO_PLUG_ EVENT#
W2
HDMI_SDATA
Y1
HDMI_SCLK
Y2
TBT_SRC_ CFG1
AA1
J4
TBT_POC_GPIO_1
E2
RTD3_USB_ PWR_EN_R
D4
TBT_FORCE_ PWR_R
H4
F2
BATLOW#
SLP_S3#
D2
RTD3_CIO_PW R_EN_R
F1
TBT_TEST _EN
E1
TBT_TEST _PWG
AB5
F4
TBT_XTAL_25_ IN
D22
TBT_XTAL_25_ OUT
D23
AB3
AC4
AC3
AB4
B7
A7
A9
B9
A11
B11
A13
B13
Y16
W16
E19
D19
PB_LSTX
B4
PB_LSRX
B5
PB_DPSRC_H PD
G2
F19
D6
A23
B23
E18
W13
W18
AB2
C4027 0.1U _0402_16V7KTBT@
C4026 0.1U _0402_16V7KTBT@
C4029 0.1U _0402_16V7KTBT@
C4028 0.1U _0402_16V7KTBT@
C4031 0.1U _0402_16V7KTBT@
C4030 0.1U _0402_16V7KTBT@
C4033 0.1U _0402_16V7KTBT@
C4032 0.1U _0402_16V7KTBT@
TBT_EE_DI <35 >
TBT_EE_DO <35>
TBT_EE_CS_ N <3 5>
TBT_EE_CL K <35>
1 2
R5125 3.01K_0402_1%TBT@
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
HDMI_HPD <25>
1 2
R5154 14K_0402_1%T BT@
R5185 0_0 402_5%TBT@
R5189 0_0 402_5%TBT@
R5190 0_0 402_5%TBT@
R5186 0_0 402_5%TBT@
R5187 0_0 402_5%TBT@
R5191 0_0 402_5%TBT@
1 2
R5123 100 _0402_5%TBT@
1 2
R5124 100 _0402_5%TBT@
1 2
TBT@
R5100 499_0402 _1%
R5104
3.3K_0402_5 %
TBT@
12
R51880 _0402_5% TBT@
HDMI_CLK+
TBT_I2C_SDA <35>
TBT_I2C_SCL <35>
1 2
TBT_CIO_PLUG_ EVENT# <8>
HDMI_SDATA <25>
HDMI_SCLK <25>
TBTA_I2C_INT <35>
1 2
1 2
1 2
1 2
1 2
TBT_RESET _N <35>
3.3K_0402_5%
12
12
R5103
TBT@
12
C52230.22U_04 02_16V7K TBT@
12
C52240.22U_04 02_16V7K TBT@
12
C52250.22U_04 02_16V7K TBT@
12
C52260.22U_04 02_16V7K TBT@
HDMI_TX0+
HDMI_TX0-
HDMI_TX1+
HDMI_TX1-
HDMI_TX2+
HDMI_TX2-
HDMI_CLK-
T32@
C5108
12P_0402_5 0V8J
TBT@
12
R5102
3.3K_0402_5 %
TBT@
TBT_EE_CS_ N
TBT_EE_DO
TBT_EE_W P_N TBT_EE_CLK
PCIE_CRX_GTX_P9
PCIE_CRX_GTX_N9
PCIE_CRX_GTX_N10
HDMI_TX0+ <25>
HDMI_TX0- <25>
HDMI_TX1+ <25>
HDMI_TX1- <25>
HDMI_TX2+ <25>
HDMI_TX2- <25>
HDMI_CLK+ <25>
HDMI_CLK- <25>
PCH_PCIE_W AKE# <10,28>
RTD3_USB_ PWR_EN <8>
TBT_FORCE_ PWR <8>
TBT_BATLOW # <8>
SUSP# <13,3 6,37,40,45>
RTD3_CIO_PW R_EN < 8>
Y2802
25MHZ_12PF_7 V25000012
1
1
1
GND
GND
TBT@
2
2
U5005
1
CS#
2
DO(IO1)
3
WP#(IO2)
4
GND
W25Q80D VSSIG_SO8
TBT@
PCIE_CRX_GTX_P9 <12>
PCIE_CRX_GTX_N9 <12>
PCIE_CRX_GTX_P10 <12>
PCIE_CRX_GTX_N10 <12>
PLT_RST# <10,27,3 6,38>
to CPU BB15 pin
to CPU GPP_D0 (SCI function pin)
From CPU GPP_D2
From_CPU_GPP_22 (GPO pin)
From CPU GPP_D21
From CPU GPP_D3
3
3
1
C5109
4
12P_0402_5 0V8J
2
TBT@
6/16 INTEL suggest add 1pF
+3.3V_FLASH
1
C4036
0.1U_0402_ 10V7K
2
TBT@
8
VCC
7
HOLD#(IO3)
6
CLK
5
DI(IO0)
TBT_EE_DI
From CPU pin BB8
DPSRC_ML0+
DPSRC_ML0-
DPSRC_ML1+
DPSRC_ML1-
DPSRC_ML2+
DPSRC_ML2-
DPSRC_ML3+
DPSRC_ML3-
12
R5101
3.3K_0402_5 %
TBT@
C5126
C5121
C5118
C5117
1P 50V C NPO 0201
1
@
2
1P 50V C NPO 0201
1
@
2
1P 50V C NPO 0201
1
@
2
1P 50V C NPO 0201
1
@
2
S IC DSL6340 SLL3 Z B1 THUNDERBOLT ABO !
@
SA000090N80
5
S IC JHL6340 QT5T C1 FCCSP THUNDER BOLT
@
SA00009YL60
S IC JHL6340 SLLS Q C1 THUNDERBOLT ABO!
TBT@
SA00009YL70
4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TR ANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TR ANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TR ANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2017/02/22 2018/02/22
2017/02/22 2018/02/22
2017/02/22 2018/02/22
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number R ev
Size Document Number R ev
Size Document Number R ev
Custom
Custom
Custom
Date : Sheet o f
Date : Sheet o f
Date : Sheet o f
Compal Electronics, Inc.
Alpine Ridge
Alpine Ridge
Alpine Ridge
LA-F241P
LA-F241P
LA-F241P
1
33 54Frid ay, June 09, 2017
33 54Frid ay, June 09, 2017
33 54Frid ay, June 09, 2017
0.1
0.1
0.1
5
+3VALW +3.3V_T BT_SX
Option 1 for wake support over TBT:
1.Connect R1581 and R1582,
2.Simple BIOS implementation
D D
Option 2 for wake support over TBT:
1.Connect R1581 and R1579
2.Bios need to implement Sx emtry pre-notice flow by PCIe2TBT
Option 3 No wake support at all from AR
1. Connect R1579 and R41582
C C
B B
A A
1 2
R1581 0_0603_5%
TBT@
1 2
R1579 0_0603_5%
@
R1582
+3VS_TBT+3VS
+3.3V_TBT_S0 +3VS_TBT
C5145
TBT@
0_0603_5%
TBT@
1 2
1U_0201_6.3V6K
1
C5111
C5110
TBT@
TBT@
2
+0.9V_USB
1U_0201_6.3V6K
1U_0201_6.3V6K
1
1
C5130
C5129
TBT@
TBT@
2
2
C5138
L64
1UH +-20% LQ M18PN1R0MFHD
1U_0201_6.3V6K
47U_0603_6.3V
TBT@
C1401
1
TBT@
2
1
2
1 2
TBT@
47U_0603_6.3V
C1402
1
2
1U_0201_6.3V6K
1
2
TBT@
C5112
TBT@
1
2
1
2
1U_0201_6.3V6K
C5137
+0.9V_DP
1U_0201_6.3V6K
C5113
TBT@
C5122
TBT@
+0.9V_CIO
TBT@
4
0.1U_0201_6.3V6K
1
C5144
C5143
TBT@
2
U5004B
1U_0201_6.3V6K
1
C5114
TBT@
2
1U_0201_6.3V6K
1
C5123
TBT@
2
1U_0201_6.3V6K
1
1
C5139
TBT@
2
2
C5141
1U_0201_6.3V6K
1U_0201_6.3V6K
1
1
C5115
C5116
TBT@
TBT@
2
2
+0.9V_PCIE
1U_0201_6.3V6K
1U_0201_6.3V6K
1
1
C5124
C5125
TBT@
TBT@
2
2
1U_0201_6.3V6K
+3.3V_ANA_PCIE
+3.3V_ANA_USB2
1U_0201_6.3V6K
1U_0201_6.3V6K
1
1
C5142
TBT@
TBT@
2
2
L8
1U_0201_6.3V6K
L11
L12
1
M8
T11
T12
2
L6
M6
V11
V12
V13
M13
1U_0201_6.3V6K
M15
M16
1
L19
N19
L18
2
M18
N18
R15
R16
R8
R9
R11
R12
L16
J16
A6
A8
A10
A12
A14
A16
A18
A20
A22
B6
B8
B10
B12
B14
B16
B18
B20
B22
D8
D9
D11
D12
D13
D15
D16
D18
E8
E9
E11
E15
E16
E22
E23
F9
F16
F20
G22
G23
H1
H2
H12
H13
H15
H16
H20
J5
J18
J19
J20
J22
J23
K1
K2
L5
L20
L22
L23
M1
M2
M5
M19
M20
N5
N20
N22
N23
AR4C_FC-CSP33 7
@
R6
VCC0P9_DP
VCC0P9_DP
VCC0P9_DP
VCC0P9_DP
VCC0P9_DP
VCC0P9_DP
VCC0P9_ANA_DPSRC
VCC0P9_ANA_DPSRC
VCC0P9_ANA_DPSNK
VCC0P9_ANA_DPSNK
VCC0P9_ANA_DPSNK
VCC0P9_PCIE
VCC0P9_PCIE
VCC0P9_PCIE
VCC0P9_ANA_PCIE_1
VCC0P9_ANA_PCIE_1
VCC0P9_ANA_PCIE_2
VCC0P9_ANA_PCIE_2
VCC0P9_ANA_PCIE_2
VCC0P9_USB
VCC0P9_USB
VCC0P9_CIO
VCC0P9_CIO
VCC0P9_CIO
VCC0P9_CIO
VCC3P3_ANA_PCIE
VCC3P3_ANA_USB2
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
TBT@
VCC3P3_LC
VSS_ANAP1VSS_ANAP2VSS_ANAR5VSS_ANA
1
2
R18
1U_0201_6.3V6K
F8
VSS_ANA
R19
R20
3
+3.3V_TBT_S0
R13
VCC3P3_S0
VCC3P3_SX
VCC0P9_SVR_SENSE
VCC0P9_LVR_SENSE
GND VCC
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANAT1VSS_ANAT2VSS_ANAT5VSS_ANA
R22
R23
C5146
H9
VCC3P3_SVR
VCC3P3_SVR
VCC3P3_SVR
VCC3P3A
VCC0P9_SVR
VCC0P9_SVR
VCC0P9_SVR_ANA
VCC0P9_SVR_ANA
VCC0P9_SVR_ANA
VCC0P9_SVR_ANA
VCC0P9_SVR_ANA
VCC0P9_SVR_ANA
SVR_IND
SVR_IND
SVR_IND
SVR_VSS
SVR_VSS
SVR_VSS
VCC0P9_LVR
VCC0P9_LVR
VCC0P9_LVR
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
T20
U23
U22
TBT@
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
2
+3VS_TBT+3.3V_TBT_SX+3.3 V_LC
10U_0402_6.3V6M
1U_0201_6.3V6K
1
C5147
TBT@
2
A2
A3
B3
L9
M9
E12
E13
C5151
F11
F12
TBT@
F13
F15
J9
TBT_SVR_IND
C1
C2
D1
A1
B1
B2
+0.9V_LVR_OUT
F18
H18
J11
H11
V5
V6
V8
V9
V15
V16
V20
W5
W6
W8
W9
W20
W22
W23
Y9
Y13
Y20
AA22
AA23
AB6
AB8
AB10
AB12
AB14
AB16
AB18
AB20
AB22
AC6
AC8
AC10
AC12
AC14
AC16
AC18
AC20
AC22
D5
E4
E5
E6
F5
F6
H5
H8
J8
J12
J13
J15
L13
M11
M12
N8
N9
N11
N12
N13
T6
T8
T9
T13
T15
T16
T18
AB1
AC2
10U_0402_6.3V6M
1
C5148
TBT@
2
1U_0201_6.3V6K
1
C5152
TBT@
2
1 2
6/3, Change PN
to SHI000MD00
C5161
TBT@
10U_0402_6.3V6M
1
1
C5149
TBT@
2
2
1U_0201_6.3V6K
1
1
C5153
TBT@
2
2
L4903 0.6UH_MN D-04ABIR60M-XGL_20%
TBT@
10U_0402_6.3V6M
1
1
C5160
TBT@
2
2
C5150
TBT@
+0.9V_SVR
1U_0201_6.3V6K
C5154
TBT@
TBT@
10U_0402_6.3V6M
C5119
TBT@
10U_0402_6.3V6M
1
2
1U_0201_6.3V6K
1U_0201_6.3V6K
1
1
C5155
C5136
TBT@
TBT@
2
2
47U_0603_6.3V
47U_0603_6.3V
C1403
C1404
1
1
TBT@
TBT@
2
2
1U_0201_6.3V6K
1U_0201_6.3V6K
1
1
C5120
TBT@
2
2
1U_0201_6.3V6K
1U_0201_6.3V6K
1
1
C5135
TBT@
2
2
47U_0603_6.3V
C1405
1
2
Share same GND plane
1
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TR ANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TR ANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TR ANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2017/02/22 2018/02/22
2017/02/22 2018/02/22
2017/02/22 2018/02/22
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number R ev
Size Document Number R ev
Size Document Number R ev
Custom
Custom
Custom
Date : Sheet o f
Date : Sheet o f
2
Date : Sheet o f
Compal Electronics, Inc.
Alpine Ridge-POWER
Alpine Ridge-POWER
Alpine Ridge-POWER
LA-F241P
LA-F241P
LA-F241P
1
34 54Frid ay, June 09, 2017
34 54Frid ay, June 09, 2017
34 54Frid ay, June 09, 2017
0.1
0.1
0.1
5
4
+3VALW _PD+3VALW
R5193
1 2
0_0402_ 5%
3
2
1
1
C93
0.1U_040 2_10V6K
2
D D
22U_0603_6.3V6M
22U_0603_6.3V6M
1
C5192
TBT@
2
TBTA_LDO_BM C
+1.8VD_TBTA_ LDO
+1.8VA_TBTA _LDO
1
C5200
2.2U_0603_10V6K
TBT@
2
1 2
1
2
B1
H1
VDDIO
VIN_3V3
0_0402_ 5%
TBT@
R5262
C5193
TBT@
A1
K1
GND
D6
C5191
1
C5198
2.2U_040 2_16V6K
2
TBT@
C C
12
R5171
TBT@
PD_IRQ#<36>
TBTA_I2C_SDA 1
TBTA_I2C_SCL 1
TBTA_LSTX<33>
TBTA_LSRX<33>
R5163 100K_0 402_5%TBT@
R5164 100K_0 402_5%TBT@
R5167 100K_0 402_5%TBT@
R5168 100K_0 402_5%TBT@
12
+3.3V_FLA SH
+1.8VS
12
@TBT@
TBT@
R5162 100K_04 02_5%
1 2
R5196 0_0402 _5%
1 2
R5204 0_0402 _5%
100K_04 02_5%
1 2
EC_SMB_D A1<36 ,42,43>
EC_SMB_C K1<36 ,42,43>
B B
A A
R5210 0_040 2_5%@
1 2
R5209 0_040 2_5%@
PD_IRQ# PU at EC side
100K_04 02_5%
TBT_A_AUX_P _C<33>
TBT_A_AUX_N _C<33>
+3.3V_FLA SH
R5170
TBT@
100K_04 02_5%
TI suggest reserve 0ohm to 1.8V,3.3V,GND
TBT_I2C_SDA<33>
TBT_I2C_SCL<3 3>
TBTA_I2C_INT<33>
R5250
10K_040 2_5%
TBTA_HPD<33>
TBT_EE_CLK<33 >
TBT_EE_DI<33 >
TBT_EE_DO<33 >
TBT_EE_CS_N<33>
TBT_A_USB20 _P<33>
TBT_A_USB20 _N<33>
12
R51651M_0 402_5%
TBT@
1 2
R5192 0_0402 _5%@
1 2
R5194 0_0402 _5%@
12
12
12
12
@
@
TBT@
R5205
12
BUSPOW ER#
1 2
1
C5199
2.2U_0603_10V6K
TBT@
2
C5203
TBT@
PD_UART
TBT_MRESET
TBTA_DIG_AUD _P
TBTA_DIG_AUD _N
TBTA_DEBUG1
TBTA_DEBUG2
TBTA_ROSC
12
R5169
15K_040 2_1%
TBT@
EC_PD_HRE SET<3 6>
+3VALW _PD
1
2
F1
D1
D2
C1
A5
B5
B6
B2
C2
D10
G11
C10
E10
G10
D7
H6
A3
B4
A4
B3
L5
K5
E2
F2
F4
G4
E11
L4
K4
L3
K3
L2
K2
J1
J2
F10
G2
10U_0402_6.3V6M
U5007
I2C_ADDR
I2C_SDA1
I2C_SCL1
I2C_IRQ1_N
I2C_SDA2
I2C_SCL2
I2C_IRQ2_N
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
SPI_CLK
SPI_MOSI
SPI_MISO
SPI_SS_N
USB_RP_P
USB_RP_N
UART_TX
UART_RX
SWD_DATA
SWD_CLK
MRESET
TBT_LSTX/R2P
TBT_LSRX/P2R
DIG_AUD_P/DEBUG3
DIG_AUD_N/DEBUG4
DEBUG1
DEBUG2
AUX_P
AUX_N
BUSPOWER_N
R_OSC
TBT@
1 2
5
4
TBT@
+5VALW _PD +20V_HV_SYS
22U_0603_6.3V6M
22U_0603_6.3V6M
1
1
C5194
TBT@
TBT@
2
2
H10
E1
A2
LDO_1V8A
GND
GNDE5GND
E6
EC_PD_HRE SET_R
R5263
0_0402_ 5%
@
A11
B11
C11
PP_5V0
PP_5V0
LDO_BMC
LDO_1V8D
PP_CABLE
GND
GND
GND
GNDF6GNDF7GND
GND
GND
GND
GNDH4GND
F5
E7
E8
B8
D8
H5
G5
R5273
TBT@
0_0603_5%
1 2
D11
B7
PP_HVA6PP_HVA7PP_HVA8PP_HV
PP_5V0
PP_5V0
GND
GND
GNDG7GND
GNDH7GNDL1GND
F8
H8
G6
G8
L11
SS
1
C5212
0.22U_04 02_10V4Z
2
TBT@
+5VALW +5VALW_PD
J38
@
JUMP_43X 79
2
112
12
C34
1U_0603 _25V6K
TBT@
A9
B10
A10
SENSEP
SENSEN
HV_GATE1B9HV_GATE2
H11
VBUS
J10
VBUS
J11
VBUS
K11
VBUS
H2
VOUT_3V3
G1
LDO_3V3
K6
C_USB_TP
L6
C_USB_TN
K7
C_USB_BP
L7
C_USB_BN
L9
C_CC1
L10
C_CC2
RPD_G1
K9
RPD_G1
RPD_G2
K10
RPD_G2
E4
DEBUG_CTL1
D5
DEBUG_CTL2
K8
R5197 0_0402 _5%@
C_SBU1
L8
R5198 0_0402 _5%@
C_SBU2
F11
R5203 0_0402 _5%@
RESET_N
TPS65982 _BGA96
3
2
1
+3.3V_TBT_S X_R
TBT_A_USB20 _PT
TBT_A_USB20 _NT
TBT_A_USB20 _PB
TBT_A_USB20 _NB
TBTA_CC1
TBTA_CC2
R5207 0_040 2_5%TBT@
R5208 0_040 2_5%TBT@
R5266 10K_0402_5%@
R5267 10K_0402_5%@
DEBUG_CTL1
DEBUG_CTL2
1 2
1 2
1 2
3
1
2
1 2
1 2
+TBTA_VBUS +TBTA_VB US
JUSB2
A1
GND
C52010.47U_0 201_25V
C51960.47U_0 201_25V
USB3_A_ TTX_C_DRX_P0
USB3_A_ TTX_C_DRX_N0
USB3_A_ TRX_DTX_P0
USB3_A_ TRX_DTX_N0
USB3_A_ TTX_C_DRX_P1
USB3_A_ TTX_C_DRX_N1
USB3_A_ TRX_DTX_P1
USB3_A_ TRX_DTX_N1
+3.3V_FLA SH
Compal Secret Data
Compal Secret Data
Compal Secret Data
A2
SSTXP1
A3
SSTXN1
A4
VBUS
A5
CC1
A6
DP1
A7
DN1
A8
RFU1
A9
VBUS
A10
SSRXN2
A11
SSRXP2
A12
GND
1
GND
2
GND
5
GND
JAE_DX07 S024JJ2
CONN@
Deciphered Date
Deciphered Date
Deciphered Date
2
TOP
1 2
D17
PESD5V0 H1BSF SOD96 2
1 2
D18
PESD5V0 H1BSF SOD96 2
1 2
D19
PESD5V0 H1BSF SOD96 2
1 2
D20
PESD5V0 H1BSF SOD96 2
1 2
D21
PESD5V0 H1BSF SOD96 2
1 2
D34
PESD5V0 H1BSF SOD96 2
1 2
D23
PESD5V0 H1BSF SOD96 2
1 2
D24
PESD5V0 H1BSF SOD96 2
USB3_A_ TTX_C_DRX_P0<33>
USB3_A_ TTX_C_DRX_N0<33>
ESD@
D36
L30ESD24VC3-2_SOT23-3
TBTA_PD_SEN SEP <4 1>
TBTA_PD_SEN SEN <41>
TBTA_HV_GATE 1 <41>
TBTA_HV_GATE 2 <41>
C5204
1U_0402 _6.3V6K
TBT@
TBT@
C550 220P_04 02_50V7K
TBT@
C551 220P_04 02_50V7K
12
12
R5161 10K_04 02_5%TBT@
R5166 10K_04 02_5%
1 2
TBT@
0_0402_ 5%
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS
MAYBE US ED BY OR DISCLOSED TOANY THIRDPARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAYBE US ED BY OR DISCLOSED TOANY THIRDPARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAYBE US ED BY OR DISCLOSED TOANY THIRDPARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
USB3_A_ TRX_DTX_N1<33>
USB3_A_ TRX_DTX_P1<33>
+3.3V_FLA SH
1
C5205
10U_060 3_10V6M
2
TBT@
12
12
2017/4/27 for support dead battery
12
12
TBT@
TBTA_SBU1
TBTA_SBU2
TBT_RESET_N <33>
R5173
EC_TBTA_RES ET <36>
12
TBTA_CC1
TBT@
TBT_A_USB20 _PT
TBT_A_USB20 _NT
TBTA_SBU1
12
TBT@
2017/02/22 2018/02/22
2017/02/22 2018/02/22
2017/02/22 2018/02/22
B12
GND
B11
SSRXP1
B10
SSRXN1
B9
VBUS
B8
RFU2
B7
DN2
B6
DP2
B5
CC2
B4
VBUS
B3
SSTXN2
B2
Bottom
SSTXP2
B1
GND
4
GND
3
GND
6
GND
ESD@
ESD@
ESD@
ESD@
ESD@
ESD@
ESD@
ESD@
USB3_A_ TRX_DTX_P0 <33>
USB3_A_ TRX_DTX_N0 <33 >
12
C52020.47U_ 0201_25V
TBT@
TBTA_SBU2
TBT_A_USB20 _NB
TBT_A_USB20 _PB
TBTA_CC2
12
C51970.47U_0 201_25V
TBT@
USB3_A_ TTX_C_DRX_N1 <33>
USB3_A_ TTX_C_DRX_P1 <33>
TBTA_SBU1
+5VALW
TBTA_SBU2
TBT_A_USB20 _PB
Title
Title
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Custom
Custom
Custom
Date : Sheet of
Date : Sheet of
Date : Sheet of
6
I/O4
5
VDD
TBT_A_USB20 _NT
4
I/O3
AZC099-04 SP.R7G_SOT2 3-6
SC30000 3S00
SC30000 3S00
AZC099-04 SP.R7G_SOT2 3-6
1
I/O1
2
GND
3
I/O2
D30 ESD@
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
PD+Type C
PD+Type C
PD+Type C
LA-F241P
LA-F241P
LA-F241P
1
GND
VDD
D29ES D@
TBT_A_USB20 _PT
3
I/O2
2
TBTA_CC1
1
I/O1
TBT_A_USB20 _NB
4
I/O3
5
6
I/O4
TBTA_CC2
35
35
35
+5VALW
0.1
0.1
0.1
54Friday, June 09 , 2017
54Friday, June 09 , 2017
54Friday, June 09 , 2017
A
<40,44,47>
+3VLP
JP4901
112
JUMP_43X39
@
For Power consumption
Measurement
1 1
ESPI Bus Pin : 1~5.7.8.10.12.14
LPC Bus Pin : 3~5.7.8.10.12.13
For turn off internal LPC module of KB9032
ESPI@
1 2
R4950 47K_0402_5%
1 2
C4916 100P_0402_50V8J@EMC@
Reserved for ESD 2014/9/17
1 2
C4915 100P_0402_50V8 J
2 2
3 3
@EMC@
12
C4910
R4904 33_0402_5%
22P_0402_50V8J
EC_KBRST#_R<8>
+3VLP_EC
1 2
R490 2.2K_0402_5%
1 2
R491 2.2K_0402_5%
1 2
R636 10K_0402_5%<BOM Structure>
EC_RSMRST#
<BOM Structure>
1
10P_0402_50V8J
C5251
2
EC_RST#
1
2
08/10 add for abnormal shutdown
@
C5227
.1U_0402_16V7K
AC_IN
@EMC@
ESPI_CLK_R
12
1 2
R4951 0_0402_5%
PLT_RST#
@
EC_KBRST#
EC_SMB_CK1
EC_SMB_DA1
USB_CEN
Combine w/ SMI
PU at CPU side For Thermal Portect Shutdown
SUSPWRDNAC K<10>
TPM_SERIRQ<8,38>
LPC_FRAME#<8,38>
LPC_AD3_R<8,38>
LPC_AD2_R<8,38>
LPC_AD1_R<8,38>
LPC_AD0_R<8,38>
ESPI_CLK_R<8>
PLT_RST#<10,27,33,38>
EC_RST#<39>
EC_SCI#<6>
WLAN_ON<31>
KSO[0..17]<38>
EC_SMB_CK1<35,42,43>
EC_SMB_DA1<35,42,43>
SOC_SML1CLK<8,19,22>
SOC_SML1DATA<8,19,22>
PM_SLP_S3#<6,10,40>
PM_SLP_A#<6,10>
AUDIO_MUTE#<30>
NUM_LED#<38>
WL_OFF#<31>
AC_PRESENT<10>
USB1_CHARGE_2A#<37>
FAN_SPEED1<39>
VR_ON<40,48>
E51TXD_P80DATA<31>
E51RXD_P80CLK<31>
PCH_PWROK<10>
PWR_SUSP_LED#<38>
VR_PWRGD<48>
PBTN_OUT#<6,10>
PM_SLP_S4#<6,10,40>
For abnormal shutdown
D25
RB751V-40_SOD323-2
SPOK
4 4
1 2
D26
RB751V-40_SOD323-2
1 2
D27
RB751V-40_SOD323-2
1 2
EC_RSMRST#
PCH_PWROK
EC_VCCST_PG_R
A
B
2
.1U_0402_16V7K
.1U_0402_16V7K
+3VALW_1.8VALW_ PGPPA
C4901
C4902
1
1
2
2
SUSPWRDNAC K
EC_KBRST#
TPM_SERIRQ
LPC_FRAME#
LPC_AD3_R
LPC_AD2_R
LPC_AD1_R
LPC_AD0_R
ESPI_CLK_R
PLT_RST#
EC_RST#
EC_SCI#
WLAN_ON
KSI[0..7]<38>
SPOK<44,47>
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
EC_SMB_CK1
EC_SMB_DA1
SOC_SML1CLK
SOC_SML1DATA
PM_SLP_S3#
PM_SLP_A#
SPOK
AUDIO_MUTE#
NUM_LED#
WL_OFF#
AC_PRESENT
USB1_CHARGE_2A#
FAN_SPEED1
VR_ON
E51TXD_P80DATA
E51RXD_P80CLK
PWR_SUSP_LED#
VR_PWRGD
PBTN_OUT#
PM_SLP_S4#
122
123
CO-LAY with KB9032QA (SA000080J00)
B
12
0_0402_5%@
R4953
+3VCC_LPC
U4901
1
GATEA20/GPIO00
2
KBRST#/GPIO01
3
SERIRQ
4
LPC_FRAME#
5
LPC_AD3
7
LPC_AD2
8
LPC_AD1
10
LPC & MISC
LPC_AD0
12
CLK_PCI_EC
13
PCIRST#/GPIO05
37
EC_RST#
20
EC_SCI#/GPIO0E
38
CLKRUN#/GPIO1D
55
KSI0/GPIO30
56
KSI1/GPIO31
57
KSI2/GPIO32
58
KSI3/GPIO33
59
KSI4/GPIO34
60
KSI5/GPIO35
61
KSI6/GPIO36
62
KSI7/GPIO37
39
KSO0/GPIO20
40
KSO1/GPIO21
41
KSO2/GPIO22
42
KSO3/GPIO23
43
KSO4/GPIO24
44
KSO5/GPIO25
45
KSO6/GPIO26
46
KSO7/GPIO27
47
KSO8/GPIO28
48
KSO9/GPIO29
49
KSO10/GPIO2A
50
KSO11/GPIO2B
51
KSO12/GPIO2C
52
KSO13/GPIO2D
53
KSO14/GPIO2E
54
KSO15/GPIO2F
81
KSO16/GPIO48
82
KSO17/GPIO49
77
EC_SMB_CLK1/GPIO44
78
EC_SMB_DAT1/GPIO45
79
EC_SMB_CLK2/GPIO46
80
EC_SMB_DAT2/GPIO47
6
PM_SLP_S3#/GPIO04
14
GPIO07
15
GPIO08
16
GPIO0A
17
GPIO0B
18
GPIO0C
19
AC_PRESENT/GPIO0D
25
PWM2/ GPIO11
28
FAN_SPEED1/GPIO14
29
FANFB1/GPIO15
30
EC_TX/GPIO16
31
EC_RX/GPIO17
32
PCH_PW ROK/GPIO18
34
SUSP_LED#/GPIO19
36
NUM_LED#/GPIO1A
PBTN_OUT#/GPIO5D
PM_SLP_S4#/GPIO5E
+3VLP_EC
12
@
Int. K/B
Matrix
L4901
<BOM Structure>
FBMA-L11-160808-800LMT_0603
1 2
R4952
0_0402_5%
22
33
96
125
9
111
VCC
VCC
VCC
VCC
VCC0
VCC_LPC
PWM Output
VCIN1_BATT_TEMP/AD0/ GPIO38
VCIN1_BATT_DROP/AD 1/GPIO39
AD Input
DA Output
EC_MUTE#/PSCLK1/ GPIO4A
PS2 Interface
SPI Device Interface
SPI Flash ROM
GPIO
SM Bus
VCIN1_ADP_PROCHOT/ GPXIOA05
VCOUT1_PROCHOT# /GPXIOA06
VCOUT0_MAIN_PW R_ON/GPXIOA07
GPIO
GPO
PWR_VC CST_PG/GPXIOA11
GPI
GND
GND
GND
GND
GND
11
24
35
94
113
Security Classification
Security Classification
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTYW ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTYW ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTYW ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
+3VLP_ECA
+3VLP_ECA
1
C4907
.1U_0402_16V7K
2
<BOM Structure>
ECAGND
67
AVCC
EC_VCCST_PG/GPIO0 F
BEEP#/GPIO10
EC_FAN_PW M/GPIO12
AC_OFF/GPIO13
ADP_I/AD2/GPIO3A
AD_BID/AD3/GPIO3B
AD4/GPIO42
AD5/GPIO43
DA0/GPIO3C
EN_DFAN1/DA1/GP IO3D
DA2/GPIO3E
DA3/GPIO3F
USB_EN#/PSDAT1/G PIO4B
PSCLK2/GPIO4C
PSDAT2/GPIO4D
TP_CLK/GPIO4E
TP_DATA/GPIO4F
ENKBL/GPXIOA00
WOL_EN /GPXIOA01
ME_EN/GPXIOA02
VCIN0_PH1/GPXIOD00
MISO/GPIO5B
MOSI/GPIO5C
SPICLK/GPIO58
SPICS#/GPIO5A
EC_CIR_RX/AD6/GPIO4 0
SYS_PWR OK/AD7/GPIO41
BATT_CHG_LED#/GPIO 52
BATT_LOW _LED#/GPIO55
EC_RSMRST#/GPXIO A03
PCH_PW R_EN/GPXIOA10
VCIN1_AC_IN/GPXIOD01
AGND
69
ECAGND
Issued Date
Issued Date
Issued Date
GPIO50
CAPS_LED#/GPIO53
PWR_LED #/GPIO54
SYSON/GPIO56
VR_ON/GPIO57
DPWRO K_EC/GPIO59
GPXIOA04
BKOFF#/GPXIOA08
GPXIOA09
EC_ON/GPXIOD02
ON/OFF#/GPXIOD03
LID_SW#/G PXIOD04
SUSP#/GPXIOD05
GPXIOD06
PECI/GPXIOD07
V18R/VCC_IO2
KB9022QD_LQFP128_14X14
20mil
FBMA-L11-160808-800LMT_0603
1 2
C4909
<BOM Structure>
100P_0402_50V8J
L4902
<BOM Structure>
C
BATT_TEMP
D
ECAGND <42>
EC_VCCST_PG_R
21
EC_BEEP#
23
FAN_PWM
26
TS_EN
27
BATT_TEMP
63
3G_OFF#
64
ADP_I
65
AD_BID
66
WLAN_PME#
75
SLP_LAN#
76
LAN_PWR_EN
68
USB_CHARGE_CB0
70
FAN_VSET
71
KB_BL_EN
72
EC_MUTE#
83
USB_PWR_EN#
84
USB_CEN
85
EC_PD_HRESET
86
TP_CLK
87
TP_DATA
88
97
ENBKL
3G_PWR_ON#
98
ME_EN
99
VCIN0_PH
109
119
SELCDP
MUTE_LED#
120
SLP_WLAN#
126
PKEY_LED#
128
PD_IRQ#
73
SYS_PWROK_R
74
USB1_CEN
89
BATT_BLUE_LED#
90
CAP_LED#
91
PWR_LED#
92
BATT_AMB_LED#
93
95
SYSON
USB2_CHARGE_2A#
121
USB_CHARGE_2A#
127
EC_RSMRST#
100
EC_TBTA_RESET
101
VCIN1_ADP_PROCHOT
102
VCOUT1_PROCHOT
103
104
MAINPWON
105
BKOFF#
COMM_LED#
106
3V_EN_R
107
USB2_CEN
108
AC_IN
110
EC_ONPCH_PWROK
112
114
ON/OFF#
LID_SW#
115
116
SUSP#
ADP_DET
117
H_PECI_R
118
124
12
2017/02/22 2018/02/22
2017/02/22 2018/02/22
2017/02/22 2018/02/22
R4944 43_0402_1%
EC_VCCST_PG_R <10,40>
EC_BEEP# <30>
FAN_PWM <39>
TS_EN <21>
BATT_TEMP <4 2,43>
3G_OFF# <31>
ADP_I <42,43>
WLAN_PME# <31>
SLP_LAN# <10>
LAN_PWR_EN <28>
USB_CHARGE_CB0 <32,37>
FAN_VSET <39>
KB_BL_EN <38>
EC_MUTE# <30>
USB_PWR_EN# <32,37>
USB_CEN <32 >
EC_PD_HRESET <35>
ENBKL <6>
3G_PWR_ON# <31>
ME_EN <9>
VCIN0_PH <42>
SELCDP <32,37>
MUTE_LED# <38>
SLP_WLAN# <10>
PKEY_LED# <38>
PD_IRQ# <35>
USB1_CEN <37>
BATT_BLUE_LED# <38>
CAP_LED# <38>
PWR_LED# <37,38>
BATT_AMB_LED# < 38>
SYSON <13,32,40,45>
USB2_CHARGE_2A# <37>
USB_CHARGE_2A# <32>
EC_RSMRST# <10>
EC_TBTA_RESET <35>
VCIN1_ADP_PROCHOT <42>
MAINPWON <42,44>
BKOFF# <21>
COMM_LED# <38>
USB2_CEN <3 7>
1 2
<BOM Structure>
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
TP_CLK <36,38>
TP_DATA <36,38>
AC_IN <43>
EC_ON <44>
ON/OFF# <6,38>
LID_SW# <3 8>
SUSP# <13,33,37,40,45>
ADP_DET <42>
H_PECI <6>
+3VLP_EC
H_PROCHOT#<6,43>
D
New P6
PIN27 from DGPU_AC_DETECT to TS_EN on UMA only
USB_CHARGE_CB0
R4943 for 9032 only
OPMODE(PIN70 Internal Pull High) :
Pull Up : Intel eSPI Master Attached Flash Sharing Topology
--> For KB9032 Only.
Pull Down : Intel Legacy Wire-OR share ROM.
--> For KB9022/9032 Use
08/03
EC PIN86 is changed for PM_SLP_S0# to
EC_PD_HRESET from customer's request
SYS_PWROK_R
TP_CLK<36,38>
TP_DATA<36,38>
MAINPWON
3V_EN_R
NC for D4PB1 UMA only
ME2N7002D1KW use SB00000DH00 symbol
VCOUT1_PROCHOT VCOUT1_PROCHOT
ME2N7002D1KW-G 2N SOT363-6
2015/1/9 acer require:
eserved protect circuit when
r
adaptor 107% happen
1 2
R4936 0_0402_5%
1 2
R4938 0_0402_5%
Title
Title
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Custom
Custom
Custom
Date : Shee t of
Date : Shee t of
Date : Shee t of
Board ID
+3VLP_EC
R4902
100K_0402_1%
Ra
<BOM Structure>
1 2
12
R4903
Rb
12K_0402_1%
Analog Board ID definition,
P
lease see page 3.
12
@
R49434.7K_0402_5%
1 2
@
R4956 0_0402_5%
TP_CLK
TP_DATA
PD_IRQ#
LID_SW#
D2012
RB751V-40_SOD323-2
1 2
<BOM Structure>
1 2
<BOM Structure>
R492
1K_0402_5%
61
2
Q2010A
@SB00000SA 00
@
@
EC ENE KB9022
EC ENE KB9022
EC ENE KB9022
LA-F241P
LA-F241P
LA-F241P
VR_HOT#
SW_PROCHOT#H_PROCHOT#
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
E
AD_BID
1
C4908
.1U_0402_16V7K
2
@
SYS_PWROK <10>
1 2
R5245 4.7K_0402_5%
1 2
R5246 4.7K_0402_5%
1 2
R634 10K_0402_5%PD@
1 2
R618 100K_0402_1%<BOM Structure>
3V_EN
R4901
1M_0402_5%
R4960 0_0402_5%
1 2
SW_PROCHOT#DGPU_AC_DETECT
34
5
Q2010B
ME2N7002D1KW-G 2N SOT363-6
@ SB 00000SA00
E
1 2
<BOM Structure>
VCOUT1_PROCHOT
VR_HOT# <48>
36 54Friday, June 09, 2017
36 54Friday, June 09, 2017
36 54Friday, June 09, 2017
3V_EN
+3VS
+3VALW
+3VLP_EC
0.1
0.1
0.1
2
JDOCK3
1
LAN_MIDI0+_DOCK<28>
LAN_MIDI0-_DOCK<28>
LAN_MIDI1+_DOCK<28>
LAN_MIDI1-_DOCK<28>
LAN_MIDI2+_DOCK<28>
LAN_MIDI2-_DOCK<28>
LAN_MIDI3+_DOCK<28>
LAN_MIDI3-_DOCK<28>
B B
DOCK_CODEC_DET<30>
LINEIN_JD<30>
MIC2_DOCK_DET<30>
HP_DOCK_DET<30>
POP<30>
LINE1_RIGHT<30>
LINE1_LEFT<30>
MIC2_DOCK_R<3 0>
MIC2_DOCK_L<30>
HP_DOCK_R<30>
HP_DOCK_L<30>
+MIC2_VREFO
PCH_USB3_TX3_P<12>
PCH_USB3_TX3_N<12>
PCH_USB3_RX3_N<12>
PCH_USB3_RX3_P<12>
USB20_N3<12>
A A
USB20_P3<12>
USB20_N3
USB20_P3
2
L38
1
MCF12102G900-T_4P
2
3
1
4
USB20_N3_L
3
EMI@
USB20_P3_L
4
LAN_MIDI0+_DOCK
LAN_MIDI0-_DOCK
LAN_MIDI1+_DOCK
LAN_MIDI1-_DOCK
LAN_MIDI2+_DOCK
LAN_MIDI2-_DOCK
LAN_MIDI3+_DOCK
LAN_MIDI3-_DOCK
LINEIN_JD
MIC2_DOCK_DET
HP_DOCK_DET
LINE1_RIGHT
LINE1_LEFT
MIC2_DOCK_R
MIC2_DOCK_L
HP_DOCK_R
HP_DOCK_L
USB20_P3_L
USB20_N3_L
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
41
41
43
43
45
45
47
47
49
49
51
51
53
53
55
55
57
57
59
59
61
61
63
63
65
65
67
67
69
69
71
71
73
73
75
75
77
77
79
79
81
81
83
83
85
85
87
87
89
89
91
91
93
93
95
95
97
97
99
99
101
101
103
103
105
105
107
107
109
109
111
111
113
113
115
115
117
117
119
119
121
121
123
123
125
125
127
127
129
129
131
131
133
133
135
135
137
137
139
139
141
141
143
143
145
GND1
146
PWR1
147
PWR1
148
PWR1
153
Shield_G
154
Shield_G
155
Shield_G
156
Shield_G
157
Shield_G
158
Shield_G
JAE_WD2F144W B5R400
CONN@
SP030 00 13A 0
PWR2
PWR2
PWR2
GND2
Shield_G
Shield_G
Shield_G
Shield_G
Shield_G
Shield_G
2
2
4
4
6
6
8
8
10
10
12
12
14
14
16
16
18
18
20
20
22
22
24
24
26
26
28
28
30
30
32
32
34
34
36
36
38
38
40
40
42
42
44
44
46
46
48
48
50
50
52
52
54
54
56
56
58
58
60
60
62
62
64
64
66
66
68
68
70
70
72
72
74
74
76
76
78
78
80
80
82
82
84
84
86
86
88
88
90
90
92
92
94
94
96
96
98
98
100
100
102
102
104
104
106
106
108
108
110
110
112
112
114
114
116
116
118
118
120
120
122
122
124
124
126
126
128
128
130
130
132
132
134
134
136
136
138
138
140
140
142
142
144
144
149
150
151
152
159
160
161
162
163
164
SYS_IN#
LAN_ACTIVITY#_DOCK
LAN_LINK#_DOCK
DP_DOCK_SEL
CRT_DATA_DOCK
CRT_CLK_DOCK
RED_DOCK
BLUE_DOCK
GREEN_DOCK
HSYNC_DOCK
VSYNC_DOCK
DP_HPD_DOCK
DP_DOCK_P0_R
DP_DOCK_N0_R
DP_DOCK_P1_R
DP_DOCK_N1_R
DP_DOCK_P2_R
DP_DOCK_N2_R
DP_DOCK_P3_R
DP_DOCK_N3_R
DP_DOCK_AUXN
DP_DOCK_AUXP
ON/OFFBTN#
DET_SIG#
DOCK_SPOK#
USB_PWR_EN#
SUSP#
PWR_LED#
1K_0402_5%
1
C5245
EMI@
.1U_0402_16V7K
2
12
R547
1 2
R649 0_0402_5%EM I@
1 2
R650 0_0402_5%EM I@
1 2
R651 0_0402_5%EM I@
1 2
R652 0_0402_5%EM I@
1 2
R653 0_0402_5%EM I@
1 2
R654 0_0402_5%EM I@
1 2
R655 0_0402_5%EM I@
1 2
R656 0_0402_5%EM I@
@
width=10 mil
+3V_LAN
LAN_ACTIVITY#_DOCK <28>
LAN_LINK#_DOCK <28 >
DP_DOCK_CAD <24>
DP_DOCK_SEL <24>
USB1_CEN <36>
USB2_CEN <36>
USB1_CHARGE_2A# <36>
USB2_CHARGE_2A# <36>
DOCK_CRT_DET# <23>
CRT_DATA_DOCK <23>
CRT_CLK_DOCK <23>
RED_DOCK <23>
BLUE_DOCK <23>
GREEN_DOCK <23>
HSYNC_DOCK <23>
VSYNC_DOCK <23>
DP_HPD_DOCK <24>
DP_DOCK_AUXN <24>
DP_DOCK_AUXP <24>
12
R5460_0402_5%
USB_PWR_EN# <32,36>
SUSP# <13 ,33,36,40,45>
PWR_LED# <36,38>
USB_CHARGE_CB0 <32,36>
SELCDP <32,36>
DET_SIG#_R
DP_DOCK_P0_C
DP_DOCK_N0_C
DP_DOCK_P1_C
DP_DOCK_N1_C
DP_DOCK_P2_C
DP_DOCK_N2_C
DP_DOCK_P3_C
DP_DOCK_N3_C
MB_VIN
12
C290 0.1U_0402_16V7K
12
C291 0.1U_0402_16V7K
12
C292 0.1U_0402_16V7K
12
C293 0.1U_0402_16V7K
12
C295 0.1U_0402_16V7K
12
C294 0.1U_0402_16V7K
12
C296 0.1U_0402_16V7K
12
C297 0.1U_0402_16V7K
ON/OFFBTN# <38>
DET_SIG#_R <6,28>
SUSP#
C814
1U_0402_6.3V6K
1
2
USB_PWR_EN# U SB_CHARGE_CB0
1
C5244
EMI@
.1U_0402_16V7K
2
1
DP_DOCK_P0
DP_DOCK_N0
DP_DOCK_P1
DP_DOCK_N1
DP_DOCK_P2
DP_DOCK_N2
DP_DOCK_P3
DP_DOCK_N3
1
C5243
EMI@
.1U_0402_16V7K
2
SELCDP
1
2
1M_0402_5%
DP_DOCK_CAD
1M_0402_5%
DP_DOCK_P0 <24>
DP_DOCK_N0 <24>
DP_DOCK_P1 <24>
DP_DOCK_N1 <24>
DP_DOCK_P2 <24>
DP_DOCK_N2 <24>
DP_DOCK_P3 <24>
DP_DOCK_N3 <24>
C5242
EMI@
.1U_0402_16V7K
R127
R124
+3VS
12
@
1 2
Security Cl assification
Security Cl assification
Security Cl assification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2017/02/22 2018/02/22
2017/02/22 2018/02/22
2017/02/22 2018/02/22
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
Compal Electronics, Inc.
E Series Dcok CONN.
E Series Dcok CONN.
E Series Dcok CONN.
LA-F241P
LA-F241P
LA-F241P
0.1
0.1
37 54Friday, June 09, 2017
37 54Friday, June 09, 2017
37 54Friday, June 09, 2017
0.1
A
B
C
D
E
TPM
R742
0_0603_5%
1 2
1 1
GPIO3/BADD with Internal PH (default)
2 2
1 2
PM_CLKRUN#<8>
LPC_AD0_R<8,36>
LPC_AD1_R<8,36>
LPC_AD2_R<8,36>
LPC_AD3_R<8,36>
LPCPD# had internal PH
CK_LPC_TPM<8>
LPC_FRAME#<8,36>
PLT_RST#<10,27,33,36,38>
TPM_SERIRQ<8,36>
CK_LPC_TPM
0.1U_0402_16V4Z
10U_0603_6.3V6M
1
1
C889
2
2
near pin5
TPM_BADD
R7390_0402_5% @
PM_CLKRUN#
LPC_AD0_R
LPC_AD1_R
LPC_AD2_R
LPC_AD3_R
CK_LPC_TPM
LPC_FRAME#
PLT_RST#
TPM_SERIRQ
@EMC@
1 2
R740 33_0402_5%
ON/OFF BTN
Test Only
SMT1-05-A_4P
1
2
6
@
SW1
5
+3VS+3VALW +3VALW_TPM +3VS_TPM
R741
0_0603_5%
1 2
C890
U67
1
GPIO0/XOR_OUT
2
GPIO1
6
GPIO2/GPX
9
GPIO3/BADD
15
GPIO4/CLKRUN#
26
LAD0/MISO
23
LAD1/MOSI
20
LAD2/SPI_IRQ#
17
LAD3
28
LPCPD#
21
LCLK/SCLK
22
LRFAME#/SCS#
16
LRSET#/SPI_RST#
27
SERIRQ
7
PP
NPCT650ABAWX
SA00007IO60
@
@EMC@
1 2
C886 22P_0402_50V8J
D28
@
2
ON/OFFBTN#
1
BAV70W_SOT323-3
3
12
R5480_0402_5% @
3
4
1
2
TEST
VSB
VDD
VDD
VDD
GND
GND
GND
GND
10U_0603_6.3V6M
C891
NC
NC
NC
NC
+3VLP
1 2
0.1U_0402_16V4Z
1
C892
2
near pin10, 19, 24
5
10
19
24
8
3
12
13
14
4
11
18
25
R513
100K_0402_5%
0.1U_0402_16V4Z
1
1
C893
2
2
+3VALW_TPM
+3VS_TPM
*
ON/OFF# <6, 36>
0.1U_0402_16V4Z
C894
U67
NPCT650ABCWX
SA00007IOA0
BADD SELECTION
EEh - EFh
0
7Eh - 7Fh
1
KB
Conn.
KSI[0..7]
KSO[0..17]
C5235
68P_0402_50V8J
RF@
+3VS closed JKB1 need to place 2 68p CAPs
Lid Switch/B
(Hall Effect Switch)
+3VS +3VS
1
2
KSO[0..17] <36>
1
C5236
68P_0402_50V8J
RF@
2
KSI[0..7] <36>
LID_SW#<36>
+3VLP
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
ACES_50565-0260N-001_26P
JKB1
GND2
GND1
26
26
25
25
24
24
23
23
22
22
21
21
20
20
19
19
18
18
17
17
16
16
15
15
14
14
13
13
12
12
11
11
10
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
CONN@
SP01 001 IE00
JLID1
1
1
2
2
3
G1
3
4
G2
4
ACES_50504-0040N-001
CONN@
SP01 000 Z300
07/26 Add
28
27
5
6
KB Backlight Conn
R511
100K_0402_5%
KB_BL_EN<36>
TP Conn.
+5VALW
12
68P_0402_50V8J
TP_DATA<36>
TP_CLK<36>
+5VS
S
Q23 DMG2301U-7_SOT23-3
G
2
KB_BL_EN#
13
D
2
G
S
+3VS
1
1
C5237
RF@
RF@
2
2
D
+5VS_BL
13
Q24
2N7002E_SOT23-3
C480
0.1U_0402_16V4Z
+3VS
CONN@
ACES_50504-0040N-001
6
4
G2
4
5
3
G1
3
2
2
1
1
JBL1
JTP1
6
4
G2
4
5
3
G1
3
2
2
1
1
ACES_50504-0040N-001
CONN@
SP01 000 Z300
470K_0402_5%
MUTE_LED#
COMM_LED#
PWR_LED#<36,37,38>
MUTE_LED#<36>
PKEY_LED#<36>
COMM_LED#<36>
NUM_LED#<36>
CAP_LED#<36>
KSO0<36>
KSI3<36>
KSI4<36>
KSI5<36>
ON/OFFBTN#<37>
PWR_LED#
MUTE_LED#
PKEY_LED#
COMM_LED#
NUM_LED#
KSO0
KSI3
KSI4
KSI5
ON/OFFBTN#
+3VALW +3VALW
12
R5254
C
C
C
3 3
CardReader Board
JREAD1
1
PCIE_CTX_C_DRX_P4<12>
PCIE_CTX_C_DRX_N4<12>
CLK_PCIE_CARD<10>
CLK_PCIE_CARD#<10>
PCIE_CRX_DTX_P4<12>
PCIE_CRX_DTX_N4<12>
CLKREQ_PCIE#4<10>
PLT_RST#<10,27,33,36,38>
PWR_LED#<36,37,38>
PWR_SUSP_LED#<36>
BATT_BLUE_LED#<36>
BATT_AMB_LED#<36>
PCH_SATALED#<12>
4 4
PCIE_CTX_C_DRX_P4
PCIE_CTX_C_DRX_N4
CLK_PCIE_CARD
CLK_PCIE_CARD#
PCIE_CRX_DTX_P4
PCIE_CRX_DTX_N4
CLKREQ_PCIE#4
PLT_RST#
BATT_AMB_LED#
BATT_AMB_LED# CAP_LED#
1
C831
0.1U_0402_16V4Z
ESD@
2
A
+5VALW
+3VS +3VS
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
G1
18
18
G2
ACES_50505-0184N-001
CONN@
19
20
B
FP Board
USB20_N8<12>
USB20_P8<12>
USB20_P8
C5239
0.1U_0402_16V7K
EMI@
USB20_N8
USB20_P8
D22
@ESD@
3
I/O2
2
GND
1
I/O1
AZC099-04S.R7G_SOT23-6
C
+3VS
1
C5238
68P_0402_50V8J
RF@
USB20_N8
6
5
4
Issued Date
Issued Date
Issued Date
2
JFP1
1
1
2
2
5
3
G1
3
6
4
G2
4
ACES_50504-0040N-001
CONN@
2017/02/22 2018/02/22
2017/02/22 2018/02/22
2017/02/22 2018/02/22
+3VS
12
I/O4
VDD
I/O3
Security Classification
Security Classification
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE S ECRET INFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R& D
AND TRADE S ECRET INFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R& D
AND TRADE S ECRET INFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R& D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTP RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTP RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTP RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Function Board
C8200.1U_0402_16V4Z ESD@
C8210.1U_0402_16V4Z ESD@
C8220.1U_0402_16V4Z ESD@
C8230.1U_0402_16V4Z ESD@
C8240.1U_0402_16V4Z ESD@
C8250.1U_0402_16V4Z ESD@
C8260.1U_0402_16V4Z @
C8270.1U_0402_16V4Z @
C8280.1U_0402_16V4Z @
C8290.1U_0402_16V4Z @
C8300.1U_0402_16V4Z ESD@
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
added for Draco_SL
12
R5255
470K_0402_5%
+3VALW
JFUN1
1
PWR_LED#
MUTE_LED#
PKEY_LED#
COMM_LED#
NUM_LED#
CAP_LED#
KSO0
KSI3
KSI4
KSI5
ON/OFFBTN#
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
KB/TP/LID/TPM/FUN/FP/CARD
KB/TP/LID/TPM/FUN/FP/CARD
KB/TP/LID/TPM/FUN/FP/CARD
Size
Size
Size
Document Number Re v
Document Number Re v
Document Number Re v
LA-F241P
LA-F241P
LA-F241P
Date: Sheet o f
Date: Sheet o f
Date: Sheet o f
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
GND
18
GND
ACES_51524-0160N-001
CONN@
SP01 001 C600
07/26 Add
E
38 54Friday, June 09, 2017
38 54Friday, June 09, 2017
38 54Friday, June 09, 2017
0.1
0.1
0.1
FAN Conn
+5VS
FAN_SPEED1<36>
20mil
1 2
R514 0_0603_5%
R761
0_0603_5%
@
1 2
FAN_VSET<36>
+3VS
12
+VCC_FAN1
+5VS_FAN
@
+VCC_FAN1
FAN_VSET
R515
10K_0402_5%
FAN_PWM<36>
C895
1 2
4.7U_0603_6.3V6K
U68
1
EN
2
VIN
3
VOUT
4
VSET
NCT3942S SOP 8P
SA00005CA00
+VCC_FAN1
FAN_SPEED1
FAN_PWM
1 2
1 2
C48110U_0805_10V4Z
C8960.1U_0402_16V4Z
GND
GND
GND
GND
8
7
6
5
CONN@
ACES_88266-04001_4P
4
3
2
1
JFAN1
6
4
G2
5
3
G1
2
1
SP02000K2 00
+RTCVCC
WIFI Stand off
H1
H_3P3
1
@
+3VLP +3VLP
2
3
DU2
BAV70W_SOT323-3
3G Stand off
H18
H_3P0N
1
@
H_3P0N
H19
@
H_3P3
1
H2
1
@
H8
H_2P5
1
@
H20
H_4P0
1
@
12
R415
10K_0402_5%
H21
H_4P0
@
FAN Stand offSSD Stand off
1
H_2P5
H5
H_3P8
1
@
H16
H_2P5
1
@
H26
H_3P5X3P0N
1
@
H17
1
@
H3
H_3P3
1
@
H11
H_2P5
1
@
H22
H_4P0
1
1
@
H4
H_3P8
@
H15
H_3P0
1
@
H25
H_5P0X3P0N
1
@
locate MB
EC_RST# <36>
61
1
<BOM Structure>
100K_0402_5%
BI<42>
Q22
13
D
2N7002E_SOT23-3
2
G
S
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
R527
1M_0402_5%
1 2
2017/02/22 2018/02/22
2017/02/22 2018/02/22
2017/02/22 2018/02/22
R525
1 2
1
C369
0.1U_0402_16V4Z
2
Compal Secret Data
Compal Secret Data
Compal Secret Data
SB00000SA00
ME2N7002D1KW-G 2N SOT363-6
SW2
3
4
SN100009500
DTSJ-62N-Q-T-R_4P
Deciphered Date
Deciphered Date
Deciphered Date
34
5
Q52B
1
2
1
2
2
C370
0.1U_0402_16V4Z
ME2N7002D1KW-G 2N SOT363-6
Q52A
SB00000SA00
ME2N7002D1KW use SB00000DH00 s ymbol
FD1
@
1
FIDUCIAL_C40M80
FD3
@
1
FIDUCIAL_C40M80
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size
Size
Size
Document Number Re v
Document Number Re v
Document Number Re v
Custom
Custom
Custom
Date: Sheet o f
Date: Sheet o f
Date: Sheet o f
Compal Electronics, Inc.
FAN & Screw
FAN & Screw
FAN & Screw
LA-F241P
LA-F241P
LA-F241P
39 54Friday, June 09, 2017
39 54Friday, June 09, 2017
39 54Friday, June 09, 2017
FD2
@
1
FIDUCIAL_C40M80
FD4
@
1
FIDUCIAL_C40M80
0.1
0.1
0.1
A
B
C
D
E
M; 6)<
J36
U5008
+3VALW
EC_nDS@
C5246
+5VALW
12
1 2
3VS_ON
+5VALW
5VS_ON
.1U_0402_16V7KEC_n DS@
SUSP#
1 1
1 2
@
R927 0_0402_5%
C980
@
C979
3V_EN<36,44,47>
1 2
12
R9260_0402_5%
1 2
.1U_0402_16V7K@
.1U_0402_16V7K@
R5257
0_0402_5%
1
VIN1
2
VIN1
3
ON1
4
VBIAS
5
ON2
6
VIN2
7
VIN2
EM5209VF_DFN14_2X3
+3VALWP
3V_EN_R1
+3VALWP
Only use in the power of AR is +3VS
+5VALW+3VS
2 2
ME2N7002D1KW-G 2N SOT363-6
3 3
R5259
60.4_0603_5%
@
3VS_R 3VS_ON#
3VS_ON#
5
Q2021B
@SB00000SA00
1 2
1 2
61
34
R5258
100K_0402_5%
@
2
SUSP#
Q2021A
ME2N7002D1KW-G 2N SOT363-6
@ SB00000SA00
SUSP# <13,33,36,37,40,45>
14
VOUT1
13
VOUT1
12
1 2
CT1
C976 100 0P_0402_50V7K
11
GND
1 2
10
CT2
C967 100 0P_0402_50V7K
9
VOUT2
8
VOUT2
15
GPAD
U5009
1
VIN1
2
VIN1
3
ON1
4
VBIAS
5
ON2
6
VIN2
7
VIN2
EM5209VF_DFN14_2X3
EC_nDS@
ME2N7002D1KW-G 2N SOT363-6
ME2N7002D1KW-G 2N SOT363-6
VOUT1
VOUT1
CT1
GND
CT2
VOUT2
VOUT2
GPAD
EN_1.8VALW# EN_1.8VALW
@
+3VS_OUT
+5VS_OUT
14
13
12
C5248 1000P_0402_50V7K
11
10
9
8
15
240_0402_1%
EC_nDS@
3VALW_ON# 3V_EN
EC_nDS@
SB00000SA00
240_0402_1%
1.8VALW_PRIM_R
SB00000SA00
2
112
JUMP_43X118
J37
@
2
112
JUMP_43X118
EC_nDS@
1 2
+3VALW +3VALWP
12
R5260
3VALW_R
2
Q2022A
+1.8VALW_PRIM +3VALWP
R5278
5
Q2024B
1 2
3VALW_ON#
34
61
12
1 2
61
34
+3VS
+5VS
ME2N7002D1KW-G 2N SOT363-6
+3VALW
R5261
100K_0402_5%
EC_nDS@
5
Q2022B
ME2N7002D1KW-G 2N SOT363-6
EC_nDS@
SB00000SA00
R5279
100K_0402_5%
EN_1.8VALW#
2
Q2024A
ME2N7002D1KW-G 2N SOT363-6
SB00000SA00
+1.2V_VDDQ +5VALW
R573
470_0603_5%
@
+1.2V_VDDQ_R
2
SYSON# SYSON
Q40A
@SB00000SA00
ME2N7002D1KW use SB00000DH00 symbol
1
C5250
4.7U_0603_6.3V6K
EC_nDS@
2
SUSP#<13,33,36,37 ,40,45>
SUSP
R555
10K_0402_5%
100K_0402_5% @
@
EN_1.8VALW <47>
R554
100K_0402_5%
@
1 2
1 2
SYSON#
61
34
Q40B
ME2N7002D1KW-G 2N SOT363-6
@ SB00000SA00
R552
1 2
61
2
12
Q2006A
@ SB00000SA00
ME2N7002D1KW-G 2N SOT363-6
5
+0.6VS_VTT+5VALW
SYSON <13,32 ,36,45>
12
R566
470_0603_5%@
+0.675VS_VTT_R
34
5
SUSP
Q2006B
@ SB0000 0SA00
ME2N7002D1KW-G 2N SOT363-6
8)#)!< < F*
+3VALW
R1000
100K_0402_5%
SB00000SA00
SB00000SA00
Q2014A
2
R1002
100K_0402_5%
<BOM Structure>
Q2016A
2
+3VALW
ME2N7002D1KW-G 2N SOT363-6
PM_SLP_S3#<6,10,36>
ME2N7002D1KW use SB00000DH00 symbol
ME2N7002D1KW-G 2N SOT363-6
PM_SLP_S4#<6,10,36>
12
61
12
61
Q2014B
ME2N7002D1KW-G 2N SOT363-6
PM_SLP_S3
Q2013B
ME2N7002D1KW-G 2N SOT363-6
Q2013A
ME2N7002D1KW-G 2N SOT363-6
Q2016B
ME2N7002D1KW-G 2N SOT363-6
PM_SLP_S4
5
5
SB00000SA00
2
SB00000SA00
5
SB00000SA00
34
EC_VCCST_PG_R <10,36>
For
tCPU28 1us(max)
34
VR_ON <36,48>
For tCPU17 1us(max)
61
SUSP#
For tCPU18 1us(max)
SB00000SA00
34
SYSON
tPLT15 1us(max)
For
+3VALW to +3VM for Intel AMT
20mil(68mA)
+3VM
2
C811
VPRO@
1
4 4
A
B
4.7U_0603_6.3V6K
+3VALW
@
1 2
R645 0_0603_5%
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2017/02/22 2018/02/22
2017/02/22 2018/02/22
2017/02/22 2018/02/22
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Custom
Custom
Custom
Date : Sheet of
Date : Sheet of
Date : Sheet of
Compal Electronics, Inc.
DC Interface
DC Interface
DC Interface
LA-F241P
LA-F241P
LA-F241P
40 54F riday, June 09, 2017
40 54F riday, June 09, 2017
E
40 54F riday, June 09, 2017
0.1
0.1
0.1
A
B
C
D
E
PD101
1 1
PJP101
@
ACES_87302-0401-003
GND
GND
6
5
4
4
3
3
2
2
1
1
12
PC101
EMI@
1000P_0603_50V7K
PL101
EMI@
FBMA-L11-322513-151LMA50T_1210
1 2
MB_VIN
DC_IN_S2
DC_IN_S2DC_IN_S1
12
PC102
EMI@
1000P_0603_50V7K
3
2
5A_100V 15UA_0.88V_TO227-3
PD102
3
2
5A_100V 15UA_0.88V_TO227-3
+19V_VIN
1
1
2015/7/8
PD101 and PD102 SCS00002F00 change to SCS00002M00
EMI
2 2
+TBTA_VBUS
PD103
SI7716ADN-T1-GE3_POWERPAK8-5
12
PC103
1U_0402_25V6
3 3
1M_0201_5%
1 2
@
PR105
PQ101
1
2
3
4
1 2
@
PR106
0_0201_5%
5
PQ102
SI7716ADN-T1-GE3_POWERPAK8-5
5
4
1 2
1
2
3
@
PR107
0_0201_5%
1M_0201_5%
1 2
@
PR108
PR104
1
2
0.01_1206_1%
@
PR109
0_0402_5%
1 2
4
3
12
12
1 2
1 2
10U_0603_25V6M
PC107
PC106
0.1U_0402_25V6
1000P_0402_50V7K
1 2
@
PR110
0_0402_5%
PC104
@
10U_0603_25V6M
PC105
@
TBTA_PD_SENSEN <35>
TBTA_PD_SENSEP <35>
3
2
5A_100V 15UA_0.88V_TO227-3
+19V_VIN
1
Keep these two signals
TBTA_HV_GATE2<35>
TBTA_HV_GATE1<35>
@
PR101
+3VLP
4 4
- +
1 2
PBJ101@
ML1220T13RE
0_0402_5%
A
PR102
560_0603_5%
12
1 2
+RTC
+CHGRTC
+RTC_R
TBTA_HV_GATE2
TBTA_HV_GATE1
PR103
560_0603_5%
1 2
+RTCBATT
Security Cl assification
Security Cl assification
Security Cl assification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAYNOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAYNOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAYNOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENTEXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS
DEPARTMENTEXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS
DEPARTMENTEXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS
MAYBE USED BY OR DISCLOSED TOANY THIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAYBE USED BY OR DISCLOSED TOANY THIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
MAYBE USED BY OR DISCLOSED TOANY THIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
as pair routing
Compal Secret Data
Compal Secret Data
2017/02/22 2018/02/22
2017/02/22 2018/02/22
2017/02/22 2018/02/22
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
PWR DCIN / Pre-charge
PWR DCIN / Pre-charge
PWR DCIN / Pre-charge
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Custom
Custom
Custom
LA-F241P
LA-F241P
LA-F241P
Date: Sheet of
Date: Sheet of
Date: Sheet of
E
41 54Friday, June 09, 2017
41 54Friday, June 09, 2017
41 54Friday, June 09, 2017
0.1
0.1
0.1
A
PJP201
@
ACES_50290-0100N
10
9
8
7
6
1 1
5
4
3
2
1
EC_SMDA
EC_SMCA
TH
BI+
+VMB
PL201
EMI@
FBMA-L11-322513-151LMA50T_1210
1 2
12
PC201
EMI@
1000P_0402_50V7K
12
EMI@
0.01U_0402_25V7K
BATT+
PC206
EMI
12
B
1 2
PR212
@
PR201
0_0402_5%
PR202
100_0402_1%
12
1K_0402_1%
PR203
PR217
100_0402_1%
1 2
12
EC_SMB_DA1 <35,36,43>
200K_0402_1%
EC_SMB_CK1 <35,36,43>
+3VLP
BATT_TEMP <36,43>
C
D
E
+3VLP
12
12
PR214
@
30.1K_0402_1%
12
12
PH202
@
G718_OT1#
12
PC205
0.1U_0603_25V7K
1
VCC
2
GND
3
OT1
4
OT2
G718TM1U_SOT23-8
PU201
TMSNS1
RHYST1
TMSNS2
RHYST2
8
7
6
5
G718_TMSNS1
G718_RHYST1
G718_TMSNS2
G718_RHYST2
1 2
PR220
105K_0402_1%
PR216
@
16.2K_0402_1%
12
12
PR213
PR219
@
100K_0402_1%
100K_0402_1%
@
PR221
MAINPWON<36,44>
Adp_det<36>
MAINPWON
0_0402_5%
PD201
S SCH DIO BAS40CW SOT-323
MB_VIN
2 2
BI < 39>
DC_IN_S2
3
2
Adp_Vin
1
PR215
100K_0402_1%
1 2
PR218
5.11K_0402_1%
1 2
(Common Part)
SL200002 H00
100K_0402_1%_NCP15WF104F03RC
PH1 under CPU botten side :
CPU thermal protection at 93 +-3 degree C
Recovery at 56 +-3 degree C
T202@
T201@
PH201
+3VLP_ECA
12
PR204
16.5K_0402_1%
12
VCIN0_PH <36>
PC203 must close to EC pin
PC203
0.022U_0402_16V7K
1 2
ECAGND <36>
2015/07/09 update
3 3
For KB9022
sense 20mΩ
65W
For AC IN
45W
For PD IN
RecoveryActive
84.5 W,0 .61V 84 .5W,0.61V
58.5 W,0 .40V 58 .5W,0.40V
12
PR208
10K_0402_1%
PR206
19.1K_0402_1%
1 2
ADP_I <36,43>
VCIN1_ADP_PROCHOT <36>
(Common Part)
SL200002 H00
100K_0402_1%_NCP15WF104F0 3RC
T202 T201 must close to PH201
4 4
Security Cl assification
Security Cl assification
Security Cl assification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAYNOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAYNOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAYNOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENTEXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS
DEPARTMENTEXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS
DEPARTMENTEXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS
MAYBE USED BY OR DISCLOSED TOANY THIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAYBE USED BY OR DISCLOSED TOANY THIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAYBE USED BY OR DISCLOSED TOANY THIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2017/02/22 2018/02/22
2017/02/22 2018/02/22
2017/02/22 2018/02/22
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
PWR-BATTERY CONN/OTP
PWR-BATTERY CONN/OTP
PWR-BATTERY CONN/OTP
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Custom
Custom
Custom
LA-F241P
LA-F241P
LA-F241P
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
E
42 54Friday, June 09, 2017
42 54Friday, June 09, 2017
42 54Friday, June 09, 2017
0.1
0.1
0.1
A
PR302
1M_0402_1%
Inverse_GATE
12
PQ303
MDU1512RH_POW ERDFN56-8-5
+19V_VIN
1 1
2014/9/30
PC301 change to SE025102K80
2014/9/30
PC301 change to SE025102K81
+19V_VIN
12
2 2
3 3
PR311
ACDET
422K_0402_1%
12
PR313
66.5K_0402_1%
5
12
PC301
1000P_0603_50V7
12
PC315
2200P_0402_25V7K
1
2
3
4
ACFET_GATE
PR301
1 2
4.7_0603_1%
+19V_VIN
+19VB
EC_SMB_DA1<35,36, 42>
EC_SMB_CK1<35,36, 42>
PSYS_MON<48>
2
G
PR303
3M_0402_5%
ADP_I<36,42>
13
D
PQ301
2N7002KW_S OT323-3
S
+19V_P1
12
AON7506_DFN33-8-5
1
2
3 5
12
PC303
0.047U_0603_25V7M
PR305
4.02K_0402_1%
PD301
S SCH DIO BAS40C W SOT-323
3
2
PC318 2.2U_06 03_6.3V7K
1 2
@
PC319 100P_0603_50V8
PC327
1 2
0.1U_0402_25V6
H_PROCHOT#<6,36>
12
PQ304
4
RBFET_GATE
PR308
4.02K_0402_1%
1 2
1
1 2
B
ACDRV_CHGR
CMSRC_CHGR
PR312 10_1206_5%
VCC_CHGR_R
PC314 1U_0603_25V6K
PR317 0_0402_5%@
1 2
1 2
PR315 0_0402_5%@
@
1 2
0_0402_5%
BATT_TEMP<36,42>
12
1 2
IDCHG_CHGR
PR331
PR321
@
0_0402_5%
1 2
+19V_P2
PC310
0.1U_0603_25V7K
12
VCC_CHGR
EC_SMB_DA1_CHGR
EC_SMB_CK1_CHGR
PR333
499_0402_1%
PMON_CHGR
PROCHOT#_CHGR
C
2014/9/25
PR304 10m ohm chang -->20m ohm
12
ACDRV_CHGR
CMSRC_CHGR
ACPRN_CHGR
ADPI_CHGR
SD00000S120
PR304
0.02_1206_1%
1
2
ACP
PC311
0.1U_0402_25V6
1 2
4
2
PU301
28
3
6
11
12
5
7
8
9
10
13
14
15
16
29
ACP
VCC
ACDRV
CMSRC
ACDET
SDA
SCL
ACOK
IADP
IDCHG
PMON
/PROCHOT
CMPIN
CMPOUT
/BATPRES
/TB_STAT
PWPD
BQ24780RUYR_W QFN28_4X4
4
3
ACN
0.01U_0402_25V7K
@
1000P_0402_50V7K
1
ACN
REGN
BTST
HIDRV
PHASE
LODRV
GND
ILIM
SRP
SRN
BATDRV
BATSRC
1 2
PC313
1 2
PJ301
@
JUMP_43X79
112
PC312
+6V_CHG_REGN
24
BST_CHGR BST_CHGR _R
25
UG_CHGR
26
LX_CHGR
27
LG_CHGR
23
22
ILIM_CHGR
21
SRP_CHGR
20
SRN_CHGR
19
BATDRV_CHGR
18
BATSRC_CHGR
17
PC304
1 2
@
10U_0805_25V6K
2015/7/27
PC316 change to SE000006S80
PC316
2.2U_0603_16V6K
1 2
@
PR316
1 2
0_0603_5%
PR323
10_0402_1%
1 2
1 2
PR324
10_0402_1%
+19VB
2
12
PC305
@
10U_0805_25V6K
PC317
0.047U_0603_25V7M
1 2
PR320 316K_0402_1%@
1 2
PR332 316K_0402_1%
1 2
PR322 100K_0402_1%
PC324
0.1U_0402_25V6
1 2
12
PC325
0.1U_0402_25V6
12
PC306
@EMI@
1 2
12
1 2
68P_0402_50V8J
1 2
PC326
@
PR314
0_0603_5%
0.1U_0402_25V6
PC307
2200P_0402_50V7K
EMI@
+5VALW
+3VLP
D
+19V_CHG
PC308
1 2
1 2
10U_0805_25V6K
DH_CHGR_R
PC309
10U_0805_25V6K
BATDRV_CHGR
BATSRC_CHGR
PQ305
MDV1528URH_PDFN33- 8-5
5
4
(Common Part)
123
Choke 2.2uH SH00000YV00
2.2UH_PCMB063T-2R 2MS_8A_20%
5
4
123
MDV1527URH_POWERDFN33-8-5
PQ306
PQ302
AON7506_DFN33-8-5
PR306
4.02K_0402_1%
PL301
1 2
12
PR319
4.7_1206_5%
@EMI@
SNUB_CHGR
12
PC323
680P_0603_50V7K
@EMI@
1
2
35
4
PC302
0.022U_0603_25V7K
1 2
BATFET_GATE
12
PR307
PR318
0.01_1206_1%
1
2
SRP
E
12
10_0402_1%
SRN
BATT+_CHG
4
3
12
PC320
10U_0805_25V6K
BATT+
12
PC321
10U_0805_25V6K
+6V_CHG_REGN
12
PR325
PR326
10K_0402_1%
AC_IN<36>
4 4
A
B
1 2
10K_0402_1%
ACPRN_CHGR
12
PR327
12K_0402_1%
Security Cl assification
Security Cl assification
Security Cl assification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF C OMPAL ELEC TRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF C OMPAL ELEC TRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF C OMPAL ELEC TRONICS, INC.
2017/02/22 2018/02/22
2017/02/22 2018/02/22
2017/02/22 2018/02/22
C
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
BQ24780
BQ24780
BQ24780
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Custom
Custom
Custom
LA-F241P
LA-F241P
LA-F241P
Date: Sheet o f
Date: Sheet o f
Date: Sheet o f
43 54Friday, June 09, 20 17
43 54Friday, June 09, 20 17
43 54Friday, June 09, 20 17
E
0.1
0.1
0.1
A
1 1
+19VB
PJ403
@
JUMP_43X79
112
2
12
PC403
0.1U_0402_25V6
@EMI@
12
PC404
2200P_0402_50V7K
EMI@
+3VALWP
Check pull up resistor of SPOK at HW side
PR406
100K_0402_5%
SPOK<36,47>
PR414 0_0402_5%@
3V_EN<36,40,47>
1 2
B
EN1 and EN2 dont't floating
PU401
SY8286BRAC_QFN20_3X3
2
12
LX_3V
PC405
10U_0805_25V6K
12
ENLDO_3V5V
+3VALWP_EN
5
11
EN112EN2
IN3IN4IN
FF13OUT14NC
PC402
1000P_0402_25V8J
6
LX
7
GND
8
GND
9
PG
10
NC
@
PR401
BST_3V
1 2
1
IN
0_0603_5%
BS
20
LX
19
LX
18
GND
17
LDO
16
NC
21
GND
15
3.3V LDO 150mA~300mA
3V_FB_C3V_FB
1 2
BST_3V_R+19VB_3V
LX_3V
12
PC411
4.7U_0603_6.3V6M
PR403
1K_0402_5%
1 2
+3VLP
C
PC401
0.1U_0603_25V7K
1 2
PR402
PR404
12
150K_0402_1%
499K_0402_1%
1 2
ENLDO_3V5V
5*5*3 Common part SH000016800
PL402
1.5UH_PCMB053T-1R5MS_6A_20%
1 2
12
PR405
4.7_1206_5%
@EMI@
3V_SN
12
PC412
@EMI@
680P_0603_50V7K
D
+19VB
+3VALWP
12
12
12
12
PC408
PC407
22U_0603_6.3V6M
PC409
PC410
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
Vout is 3.234V~3.366V
Ipeak=7A
Imax=4.9A
Iocp=10A
E
2 2
+19VB
3 3
EC_ON<36>
4 4
MAINPWON<36,42>
A
PJ404
@
JUMP_43X79
112
PR410
2.2K_0402_5%
1 2
PR411
@
0_0402_5%
1 2
5V_EN
@
PR415
1 2
0_0402_5%
+19VB_5V
2
12
PC414
10U_0805_25V6K
5V_EN
12
12
PR412
1M_0402_1%
+19VB_5V BST_5V
5
PU402
12
12
PC416
PC415
10U_0805_25V6K
@
PC428
4.7U_0402_6.3V6M
2200P_0402_50V7K
EMI@
12
LX_5V
6
LX
0.1U_0402_25V6
PG_5V
12
@
ENLDO_3V5V
5V_EN
7
GND
8
GND
9
PG
10
NC
PR413
0_0402_5%
11
PC417
@EMI@
SPOK
B
EN112EN2
2
1
IN
IN3IN4IN
BS
LX
LX
GND
VCC
NC
GND
FF13OUT14LDO
15
12
OUT_5V
PC427
PC413
1000P_0402_25V8J
1 2
Security Cl assification
Security Cl assification
Security Cl assification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAYNOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAYNOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAYNOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENTEXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS
DEPARTMENTEXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS
DEPARTMENTEXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS
MAYBE USED BY OR DISCLOSED TOANY THIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAYBE USED BY OR DISCLOSED TOANY THIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAYBE USED BY OR DISCLOSED TOANY THIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
@
PR408
1 2
0_0603_5%
SY8288CRAC_QFN20_3X3
20
LX_5V
19
18
PC419 4.7U_0603_6.3V6M
VCC_5V
17
1 2
16
21
5V LDO 150mA~300mA
VL
PR416 0_0402_5%
1 2
4.7U_0603_6.3V6M
Issued Date
Issued Date
Issued Date
5V_FB_C5V_FB
PR407
1K_0402_5%
1 2
C
PC418
0.1U_0603_25V7K
BST_5V_R
1 2
5*5*3 Common part SH000016800
PL404
1.5UH_9A_20%_7X7X3_M
1 2
12
PR409
4.7_1206_5%
@EMI@
5V_SN
12
PC426
@EMI@
680P_0603_50V7K
Compal Secret Data
Compal Secret Data
2017/02/22 2018/02/22
2017/02/22 2018/02/22
2017/02/22 2018/02/22
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
12
12
12
PC420
22U_0603_6.3V6M
12
PC422
PC421
22U_0603_6.3V6M
PC423
@
22U_0603_6.3V6M
Vout is 4.998V~5.202V
Ipeak=7A
Imax=4.9A
Iocp=10A
+3VALWP +3 VALW
Title
Title
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
+5VALWP
12
12
PC424
PC425
@
22U_0603_6.3V6M
22U_0603_6.3V6M
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
PWR-3.3VALWP/5VALWP
PWR-3.3VALWP/5VALWP
PWR-3.3VALWP/5VALWP
LA-F241P
LA-F241P
LA-F241P
22U_0603_6.3V6M
PJ401
@
112
JUMP_43X118
PJ402
@
112
JUMP_43X118
2
2
E
+5VALW+5VALWP
0.1
0.1
44 54Friday, June 09, 2017
44 54Friday, June 09, 2017
44 54Friday, June 09, 2017
0.1
A
B
C
D
E
Module model information
RT8207M_V1.mdd For Single la yer
RT8207M_V2.mdd For Dual layer
1 1
PJ506
@
JUMP_43X79
2
+19VB
Update Pc510 change
to Common Part
SF000006S00 20141227
+1.2VP
2 2
112
Choke 1.5uH SH000016700
Common Part 7*7*3
1
+
PC510
2
330U_2.5V_M
+19VB_1.2VP
12
12
PC502
PC503
0.1U_0402_25V6
@EMI@
EMI@
PL502
1.5UH_PCMC063T-1R5MN_9A_20%
1 2
@EMI@
@EMI@
680P_0402_50V7K
2200P_0402_50V7K
4.7_1206_5%
+19VB_1.2VP
12
PR504
PC518
PC504
LX_1.2VP
12
PC505
10U_0805_25V6K
12
SNB_1.2VP
12
10U_0805_25V6K
5
MDV1528URH_PDFN33-8-5
123
5
SI7716ADN-T1-GE3_POWERPAK8-5
123
change PQ502 form 7506
to 7716, 20150108
PC506
4
PQ503
+5VALW
4
PQ502
12
0.1U_0603_25V7K
Change PR503 to 17.8K ohm
OCP setting 9.6A
PR505
5.1_0603_5%
1 2
BST_1.2VP_R
12
PC517
1U_0402_10V6K
PR502
2.2_0603_5%
1 2
PR503
17.8K_0402_1%
1 2
PC509
1U_0402_10V6K
1 2
VDD_1.2VP
LG_1.2VP
CS_1.2VP
VDDP_1.2VP
PR511
+5VALW
+19VB_1.2VP
SYSON<13,32,36,40,45>
SUSP#<13,33,36,37,40>
SM_PG_CTRL<7>
MOSFET: 3x3 DFN
H/S Rds(on): 23.2mohm(Typ), 27.8mohm(Max)
Mode Level +0.675VSP VTTREF_1.35V
S5 L off off
S3 L off on
S0 H on on
Note: S3 - sleep ; S5 - power off
3 3
Idsm: 10.1A@Ta=25C, 8.1A@Ta=70C
L/S Rds(on): 13.5mohm(Typ), 16.5mohm(Max)
Idsm: 12A@Ta=25C, 9.5A@Ta=70C
Choke: 7x7x3
Rdc=14mohm(Typ), 15mohm(Max)
Switching Frequency: 285kHz
Ipeak=8A
Iocp~9.6A
OVP: 110%~120%
VFB=0.75V, Vout=1.2V
MOSFET footprint: SIS412DN
PJ503
@
JUMP_43X79
VIN_2.5VP
VIN_2.5VP
+3VALW
112
2
12
PC521
PC526
22U_0805_6.3VAM
EN_2.5VP
PU502
9
PGND
1
8
FB
SGND
2
7
PG
EN
3
IN
4
12
22U_0805_6.3VAM
PGND
SY8003ADFC DFN 8P
SA00007QP00
LX_2.5VP
6
LX
5
NC
PC520
0.1U_0402_16V7K
1UH_PH041H-1R0MS_3.8A_20%
1 2
SH00000YG00
12
PR514
4.7_0603_5%
@EMI@
Pin19 need pull separate from +1.2VP.
If you have +1.2V and +0.6V sequence question,
you can change from +1.2VP to +1.2VS.
BST_1.2VP
UG_1.2VP
LX_1.2VP
18
16
17
19
20
VTT
PAD
BOOT
UGATE
VLDOIN
VTTGND
VTTSNS
GND
VTTREF
VDDQ
FB
S5
S3
TON
6
8
7
9
FB_1.2VP
EN_1.2VP
EN_0.6VSP
12
+1.2VP
+1.2VP
12
PC519
@
+0.6VSP
22U_0603_6.3V6M
22U_0603_6.3V6M
12
68P_0402_50V8J
PC524
PC523
12
12
12
2.2_0402_1%
887K_0402_1%
12
PL503
36.5K_0402_1%
FB_2.5VP
PU501
15
LGATE
14
PGND
13
CS
12
VDDP
11
VDD
PR507
1 2
@
1 2
1 2
1 2
12
1M_0402_5%
PR515
PR501
0_0402_5%
0.1U_0402_10V7K
PR509
@
0_0402_5%
@
PR510
0_0402_5%
PR513
12
Rup
PHASE
RT8207MZQW_WQFN20_3X3
PGOOD
10
TON_1.2VP
PC501
@
0.1U_0402_10V7K
PR512
@
1 2
0_0402_5%
3.8x3.8xH1 .8
DCR: 20~25mohm
Idc / Isat: 3.8A
PC522
21
1
2
3
VTTREF_1.2VP
4
5
+1.2VP
PR506
6.19K_0402_1%
1 2
12
PR508
10K_0402_1%
SYSON <13,32,36,40,45>
+2.5VP
Iocp : 3.7A
FSW : 1MHz
0.6Volt +/- 5%
TDC 0.7A
Peak Current 1A
+1.2VP
+0.6VSP
12
12
PC507
PC508
10U_0603_6.3V6M
10U_0603_6.3V6M
12
PC516
0.033U_0402_16V7K
+1.2VP
Vout=0.75V* (1+Rup/Rdown)
=0.75*(1+(6.19/10))
=1.2V
PJ501
@
JUMP_43X118
112
PJ505
@
JUMP_43X118
112
PJ502
@
JUMP_43X39
112
2
2
+1.2V_VDDQ
+1.2V_VDDQ
2
+0.6VS_VTT
5/29 add PC526
In order to avoid capacito r decay
4 4
A
B
SNUB_2.5VP
12
PC525
@EMI@
680P_0402_50V7K
Rdow n
12
PR516
11.5K_0402_1%
Vout=0.6V* (1+Rup/Rdown)
2.504V= 0.6V*(1+36. 5K/11.5K)
Security Classification
Security Classification
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENTDIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENTDIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENTDIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.
MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.
MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPALELECTRONICS, INC.
C
Issued Date
Issued Date
Issued Date
@
PJ504
+2.5VP
2017/02/22 2018/02/22
2017/02/22 2018/02/22
2017/02/22 2018/02/22
2
112
JUMP_43X79
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
+2.5V
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
+1.2VP/+0.6VSP/+2.5VP
+1.2VP/+0.6VSP/+2.5VP
+1.2VP/+0.6VSP/+2.5VP
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Custom
Custom
Custom
LA-F241P
LA-F241P
LA-F241P
Date: Sheet of
Date: Sheet of
Date: Sheet of
45 54Friday, June 09, 2017
45 54Friday, June 09, 2017
45 54Friday, June 09, 2017
E
0.1
0.1
0.1
A
B
C
D
E
EN pin don't floating
PJ602
2
PC604
EMI@
J;(-;6HC
12
PC605
0.1U_0402_25V6
@EMI@
2200P_0402_50V7K
PR601
1M_0402_1%
PR605
@EMI@
4.7_1206_5%
SNB_1VALW
1 2
(Common Part)
SH00000Y E00
PL602
1UH_11A_20%_7X7X3_M
1 2
FB = 0.6V
Rdo wn
12
@
1 2
PR603
@
10K_0402_1%
1 2
18
11
13
15
PC614
1U_0402_6.3V6K
PR602
0_0402_5%
PU601
2
IN
3
IN
4
IN
5
IN
7
GND
8
GND
GND
EN
ILMT
BYP
SY8288RAC_QFN20_3X3
9
PG
1
BS
6
LX
19
LX
20
LX
14
FB
17
VCC
10
NC
12
NC
16
NC
21
PAD
+1.8VALW_PG <47>
+3VALW
LX_1VALW
FB_1VALW
LDO_3V_1VALW
@
PR606
1 2
0_0603_5%
12
PC613
2.2U_0402_6.3V6M
Pin 7 BYP is for CS.
Common NB can delete +3VALW and PC15
BST_1VALW_RBST_1VALW
PC603
0.1U_0603_25V7K
1 2
+19VB_1VALW
12
12
PC606
10U_0805_25V6K
EN_1VALW
ILMT_1VALW
+3VALW
EN_1VALW
12
12
PC601
@
0.22U_0402_10V6K
PC602
@EMI@
680P_0603_50V7K
1 2
12
Rup
Vout=0.6V* ( 1+Rup/Rdown)
Vout=1.02V 2%
12
PC608
PR608
14K_0402_1%
PR610
20K_0402_1%
330P_0402_50V7K
12
=0.6*(1+(14/20))
Ipeak =9 .8A
Imax= 6. 86A
Iocp =12 A
+1.0VALWP
12
12
PC609
PC610
22U_0603_6.3V6M
PJ601
@
JUMP_43X118
2
112
+1.0VALW_PRIM
J;6HC
1
12
12
PC611
22U_0603_6.3V6M
22U_0603_6.3V6M
+
PC612
PC615
2
330U_2.5V_M
@
22U_0603_6.3V6M
1 1
@
J;(
LDO_3V_1VALW
12
PR607
@
0_0402_5%
ILMT_1VALW
12
PR609
@
0_0402_5%
The current limit is set to 8A ,12A ,16A, when this pin
is pull low, floating or pull high
2 2
112
JUMP_43X79
3 3
4 4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE S ECRET INFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R& D
AND TRADE S ECRET INFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R& D
AND TRADE S ECRET INFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R& D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTP RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTP RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTP RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2017/02/22 2018/02/22
2017/02/22 2018/02/22
2017/02/22 2018/02/22
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
+1.0VALWP
+1.0VALWP
+1.0VALWP
Size
Size
Size
Document Number R ev
Document Number R ev
Document Number R ev
C
C
C
LA-F241P
LA-F241P
LA-F241P
Date: Sheet o f
Date: Sheet o f
Date: Sheet o f
E
46 54Friday, June 09, 2017
46 54Friday, June 09, 2017
46 54Friday, June 09, 2017
0.1
0.1
0.1
A
1 1
B
C
D
E
Module model information
SY803 2_V 2.m dd
PJ702
@
JUMP_43X79
2
+1.8VALWP
112
VIN_1.8VALW
PC702
EN_1.8VALW<40>
1M_0402_1%
PR701
22U_0603_6.3V6M
PJ701
@
JUMP_43X79
112
PR702
100K_0402_1%
1 2
12
1 2
2
12
@
0.1U_0402_16V7K
VIN_1.8VALW
EN_1.8VALW
PC701
PU701
SY8032ABC_SOT23-6
4
IN
5
PG
GND
FB6EN
LX_1.8VALW
3
LX
2
1
2 2
+3VALW
+1.8VALW_PG<46>
+3VALW
1 2
SPOK<36,44>
3V_EN<36,40,44>
+3VALW<6,14,27,28,31,32,34,35,36,38,40,44,45,46>
1 2
1 2
PR705
0_0402_5%
PR708
@
0_0402_5%
PR709
@
0_0402_5%
Not e:
When design Vin=5V, please stuff snubber
to preve nt Vin damage
FB=0 .6V
PL701
1UH_2.8A_30%_4X4X2_F
1 2
12
PR703
4.7_0603_5%
@EMI@
SNB_1.8VALW
12
PC706
@EMI@
680P_0402_50V7K
FB_1.8VALW
12
12
PC703
PR704
20K_0402_1%
68P_0402_50V8J
Rup
12
Rdo wn
PR707
Vout=0.6V* ( 1+Rup/Rdown)
10K_0402_1%
Vout=0.6V* (1+(20 /10))=1.8V
12
12
PC705
PC704
22U_0603_6.3V6M
+1.8VALWP
22U_0603_6.3V6M
+1.8VALW_PRIM
+1.8VALWP:
Imax=0.19A Ipeak=0.27A
IOCP=3.9A
3 3
4 4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE S ECRET INFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R& D
AND TRADE S ECRET INFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R& D
AND TRADE S ECRET INFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R& D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTP RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTP RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTP RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2017/02/22 2018/02/22
2017/02/22 2018/02/22
2017/02/22 2018/02/22
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
SY8032
SY8032
SY8032
Size
Size
Size
Document Number Re v
Document Number Re v
Document Number Re v
C
C
C
LA-F241P
LA-F241P
LA-F241P
Date: Sheet o f
Date: Sheet o f
Date: Sheet o f
E
47 54Friday, June 09, 2017
47 54Friday, June 09, 2017
47 54Friday, June 09, 2017
0.1
0.1
0.1
A
B
C
D
E
PR811
20K_0402_1%
1 2
1 2
KB_U42@
PR822
23.2K_0402_1%
SK_U22@
PR822
28.7K_0402_1%
PR822
1 2
KB_U22@
IOUT_2ph
12
PR850
@
1 2
2_0402_1%
PR870
1 2
2_0402_1%
PC831
PC803
1000P_0402_50V7K
1 2
PR805
1.69K_0402_1%
1 2
PR807
1K_0402_1%
1 2
1 2
PC807
2200P_0402_50V7K
VSP_2ph
PR814
806_0402_1%
1 2
PC810
3300P_0402_50V7-K
12
PC813
26.1K_0402_1%
470P_0402_50V7K
1
IOUT_2ph
2
DIFFOUT_2ph
3
FB_2ph
4
COMP_2ph
5
ILIM_2ph
6
CSCOMP_2ph
7
CSSUM_2ph
8
CSREF_2ph
9
CSP2_2ph
10
CSP1_2ph
11
TSENSE_2ph
12
VRMP
PC801
0.01U_0402_50V7K
12
PR853
SK_U22@
45.3K_0402_1%
VSP_1b
VSN_2ph
33.2K_0402_1%
FSW FOR GT AND IA
PC802
8200P_0402_25V7K
COMP_1b
12
PR808
19.6K_0402_1%
ILIM_1b
Iout_1b
42
47
49
48
TAB
VSN_2ph
13
12
PR854
24K_0402_1%
PR856
46
PSYS
VSP_2ph
12
FSW FOR SA
43
44
45
VSP_1b
VSN_1b
COMP_1b
PWM2_2ph17PWM1_2ph
16
12
KB_U42@
100K_0402_1%
39
40
41
ILIM_1b
CSP_1b
CSN_1b
ADDR_VBOOT21ICCMAX_1b20ICCMAX_1a19ICCMAX_2ph18RSOC_SAUS15ROSC_COREGT14VCC
12
PR856
51.1K_0402_1%
KB_U22@
PR856
PR802
1.5K_0402_1%
1 2
1 2
1 2
PC804
15P_0402_50V8J
1 2
PC806
1000P_0402_50V7K
PR819
57.6K_0402_1%
12
PC811
470P_0402_50V7K
1 2
PR863
@
1 2
0_0402_5%
PU801
NCP81218MNTXG_QFN48_6X6
37
38
EN
36
IOUT_1b
VR_RDY
PWM_1b
35
DRVON
34
SCLK
33
ALERT#
32
SDIO
31
VR_HOT#
30
IOUT_1a
29
CSP_1a
28
CSN_1a
27
ILIM_1a
26
COMP_1a
25
VSN_1a
PWM_1a22TSENSE_1ph
VSP_1a
23
24
PR846 3.09K_0402_1%
VSP_1a
PC830
1000P_0402_50V7K
12
PR857
PR858
97.6K_0402_1%
19.1K_0402_1%
PC836
12
2200P_0402_50V7K
PR875
10_0402_1%
1 2
12
PC833
PC809
1 2
0.01U_0402_25V7K
1200P_0402_50V7K
VR_ON <36,40>
PWM_1b_SA <49>
DRVON <49>
PR834
49.9_0402_1%
1 2
PR860
1 2
SCLK
0_0402_5%@
ALERT#
1 2
SDIO
10_0402_1%
IOUT_1a
CSP_1a
VSN_1a
1 2
ILIM_1a
COMP_1a
3300P_0402_50V7-K
1 2
1 2
499_0402_1%
1 2
PR869 100_0402_1%
PC824
PR843
1 2
PR867
3.09K_0402_1%
12
PWM_1a_GT <49>
12
PR859
35.7K_0402_1%
PR857=97.6K in all platform
VBOOT
PR858=19.1K in all platform
PR808 change 19.6K in all platform
P
R819=57.6K iin all platform
12
PH802
100K_0402_1%_NCP15WF104F03RC
place close to SA chock
12
PR816
12K_0402_1%
PR818
7.5K_0603_1%
+1.0V_VCCST
12
12
PR826 110_0402_1%
PR824 45.3_0402_1%
@
PR862
1 2
PR865
@
1 2
12
0_0402_5%
PC828 1000P_0402_50V7K
PR847
@
1 2
0_0402_5%
PR852
@
1 2
0_0402_5%
PC832
1000P_0402_50V7K
12
12
SW_1b <49>
close to the longer distance phase(81208 or 81210)
Alert,Data,C lk.
12
PC815
0.1U_0402_16V7K
PR866 100_0402_1%
SOC_SVID_CLK <15>
SOC_SVID_ALERT#_R <15>
SOC_SVID_DAT <15>
PR840
100_0402_1%
12
12
PR851
100_0402_1%
12
61.9K_0402_1%
PR855
CSN_1b <49>
+3VS
PR821
10K_0402_1%
12
PR836=69.8K in all platform
PR828
@
110_0402_1%
PC819
470P_0402_50V7K
1 2
PR836
69.8K_0402_1%
12
PC829
15P_0402_50V8J
VSSGT_SENSE <15>
VCCGT_SENSE <15>
+VCC_GT
12
PH805
100K_0402_1%_NCP15WF104F03RC
place
close
to GT high side
VR_PWRGD <36>
VR_HOT# < 36>
12
12
PC825
12
1500P_0402_50V7K
PR848
2.49K_0402_1%
PR829
7.5K_0603_1%
1 2
12
PC820
PR842
1 2
36.5K_0402_1%
OCP for GT
12
PC834
8200P_0402_25V7K
12
12
PC826
1000P_0402_50V7K
PR835
12K_0402_1%
1 2
12
PH804
100K_0402_1%_NCP15WF104F03RC
0.022U_0402_25V7K
1 2
PR876
10_0402_1%
PC837
2200P_0402_50V7K
place close to GTchock
SWN_GT1 <49>
CSN_GT1 <49>
PR803 100_0402_1%
1 1
VCCSA_SENSE<13>
VSSSA_SENSE<13>
+VCC_SA
+VCC_CORE
VCCSENSE<15>
VSSSENSE<15>
2 2
THERM_ 220K 5% 0402
12
PR830
165K_0402_1%
1 2
PC822
0.1U_0402_16V7K
12
PR874
+5VS
97.6K_0603_1%
1 2
U42@
97.6K_0603_1%
1 2
PR873
10_0402_1%
1 2
1 2
PR872
U42@
10_0402_1%
PR825
1 2
2.15K_0402_1%
1 2
U42@
2.15K_0402_1%
1 2
U22@
0_0402_5%
12
PC821
0.22U_0402_16V7K
PR845
PR871
PR868
SW_1a
SW_2a
CSN_1a<49>
CSN_2a<49>
SW_1a<49>
3 3
SW_2a<49>
1 2
1 2
PR809 100_0402_1%
1 2
PR810 100_0402_1%
100_0402_1%
PH803
place close to IA chock
1 2
1 2
PR831
75K_0402_1%
PC817
1000P_0402_50V7K
PC835
U42@
0.1U_0402_16V7K
PH801
100
度度度度
place close to IA MOS
100K_0402_1%_NCP15WF104F03RC
1 2
PR815
470P_0402_50V7K
12
12
@
12
49.9_0402_1%
15P_0402_50V8J
U42@
16.9K_0402_1%
PC818
U22@
1000P_0402_50V7K
PR864
@
1 2
12
0_0402_5%
61.9K_0402_1%
PR844
PR804
@
0_0402_5%
1 2
1000P_0402_50V7K
PR806
@
1 2
0_0402_5%
PR812
0_0402_5%@
1 2
@
PR813
0_0402_5%
1 2
PR817
PC812
PC814
PR833
PR833
9.76K_0402_1%
12
VSPP_1b
PC805
PSYS_MON< 43>
12
12
12
12
PR820
PR823
12
4.75K_0402_1%
1 2
12
PC816
2200P_0402_50V7K
1 2
+19VB_CPU
PC827
1000P_0402_50V7K
+5VS
+5VALW
RDRPSP
12
VSNN_1b
PC808
1000P_0402_50V7K
VSNN_2ph
604_0402_1%
1 2
PR801
1K_0402_1%
1U_0603_10V6K
PWM2_2ph_IA <49>
4 4
PWM1_2ph_IA <49>
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE S ECRET INFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R& D
AND TRADE S ECRET INFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R& D
AND TRADE S ECRET INFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R& D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTP RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTP RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTP RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2017/02/22 2018/02/22
2017/02/22 2018/02/22
2017/02/22 2018/02/22
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
IMVP8, NCP81206
IMVP8, NCP81206
IMVP8, NCP81206
Size
Size
Size
Document Number Re v
Document Number Re v
Document Number Re v
C
C
C
LA-F241P
LA-F241P
LA-F241P
Date: Sheet o f
Date: Sheet o f
Date: Sheet o f
E
48 54Friday, June 09, 2017
48 54Friday, June 09, 2017
48 54Friday, June 09, 2017
0.1
0.1
0.1
A
change PL9 002, PL9003
SM01000C000 to comm
part SM01000P200
1 1
PR901
1 2
0_0603_5%
@
FLAG
DRVH
GND
DRVL
SW
PC905
0.22U_0603_16V7K
1 2
9
HG_VCORE
8
SW_VCORE
7
6
LG_VCORE
5
PR903
2.2_0603_5%
1 2
PU901
NCP81151MNTBG_DFN8_2X2
1
BST
PWM1_2ph_IA<48>
DRVON<48>
+5VS
2 2
2
PWM
3
EN
4
12
VCC
PC918
4.7U_0402_6.3V6M
1
7
D2/S1
6
AON6992_DFN5X6D-8-7
2
G1
G2
5
InputCapa citor:
10uF_0805 _X5R_25V
PQ901
D1
S24S2
S2
3
B
+19VB_CPU
12
12
PC910
10U_0603_25V6M
12
PR905
@EMI@
12
PC920
@EMI@
12
PC914
PC913
EMI@
2200P_0402_50V7K
(Common Part)
SH000011H00 7*7*4
1
2
DCR=0.98m ohm +-5%
Common part SH000011H00
4.7_1206_5%
2017/06/02 PL904 change common part
SH000011H00 7*7*5
680P_0603_50V7K
PC908
@EMI@
0.1U_0402_25V6
10U_0603_25V6M
4
PL904
0.22UH_24A_20%_ 7X7X4_M
3
PJ901
@
JUMP_43X79
112
12
+19VB
2
1
+
PC901
2
33U_25V_NC_6.3X4.5
+VCC_CORE
CSN_1a <48>
SW_1a <48>
PWM2_2ph_IA<48>
DRVON
+5VS
C
PC906
U42@
PR902
U42@
1
BST
2
PWM
3
EN
4
PC919
U42@
4.7U_0402_6.3V6M
VCC
NCP81151MNTBG_DFN8_2X2
12
2.2_0603_5%
1 2
PU902U42@
FLAG
DRVH
SW
GND
DRVL
0.22U_0603_16V7K
1 2
9
HG_VCORE_IA
8
SW_VCORE_IA
7
6
5
LG_VCORE_IA
PR904
1 2
0_0603_5%
PQ903
1
7
D2/S1
AON6992_DFN5X6D-8-7
6
D
+19VB_CPU
2
D1
G1
S24S2
G2
5
InputCapa citor:
10uF_0805 _X5R_25V
12
PC909
U42@
10U_0603_25V6M
S2
3
PR906
12
4.7_1206_5%
@U42_EMI@
12
PC921
680P_0603_50V7K
@U42_EMI@
PC904
12
12
PC907
0.1U_0402_25V6
2200P_0402_50V7K
@U42_EMI@
U42_EMI@
(Common Part)
SH000011H00 7*7*4
1
2
DCR=0.98m ohm +-5%
Common part SH000011H00
U42@
4
PL903
3
0.22UH_24A_20%_ 7X7X4_M
12
PC902
U42@
10U_0603_25V6M
+VCC_CORE
CSN_2a <48>
SW_2a <48>
E
2.2_0603_5%
U22
VCC:
Imax=21A Ipeak=32A Iocp=40A
U42
VCC:
Imax=42A Ipeak=64A Iocp=70A
VCCGT:
Imax=18A Ipeak=31A Iocp=39A
VCCSA:
3 3
Imax=4A Ipeak=5A Iocp=9.5A
PWM_1a_GT<48>
DRVON
+5VS
InputCapa citor:
10uF_0805 _X5R_25V
12
PR910
9
DRVH
DRVL
PAD
SW
GND
PC938
0.22U_0603_16V7K
1 2
8
7
6
5
HG_SA
4
D110D2/S1
5
SW_SA
LG_SA
2.2_0603_5%
1 2
PU904
NCP81253MNTBG_DFN8_2X2
1
BST
PWM_1b_SA<48>
4 4
+5VS
DRVON
2
PWM
3
EN
4
VCC
12
PC939
4.7U_0402_6.3V6M
A
PC934
10U_0603_25V6M
AON7934
Rds(on)=12.4~15.8m ohm
PQ907
1
3
2
AON7934_DFN3X3A8-10
D1
D1
D1
G1
9
S2
S2
S2
G2
6
7
8
12
12
PC936
PC935
10U_0603_25V6M
0.1U_0402_25V6
@EMI@
SW_SA
12
PR911
4.7_1206_5%
@EMI@
12
PC940
680P_0603_50V7K
@EMI@
+19VB_CPU
12
PC937
EMI@
2200P_0402_50V7K
DCR=6.2m ohm +-5%
Common part SH00001ED00
PL907
1
4
3
2
0.47UH_NA__12.2A_20%
B
+VCC_SA
CSN_1b <48>
SW_1b <48>
1 2
PU903
NCP81253MNTBG_DFN8_2X2
1
2
3
4
12
PC932
4.7U_0402_6.3V6M
1 2
5
HG1_GT
BST
PWM
EN
VCC
C
8
DRVH
SW1_GT
7
SW
6
GND
5
DRVL
PAD
9
LG1_GT
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE S ECRET INFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R& D
AND TRADE S ECRET INFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R& D
AND TRADE S ECRET INFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R& D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTP RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTP RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTP RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PR915
1 2
0_0603_5%
@
2017/02/22 2018/02/22
2017/02/22 2018/02/22
2017/02/22 2018/02/22
4
123
5
4
123
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
1
+
PC903
2
33U_25V_NC_6.3X4.5
PQ902
AON6380_DFN5X6-8-5
12
PQ904
AON6314_N_DFN56-8-5
PR909
@EMI@
12
PC933
@EMI@
D
12
12
PC924
0.1U_0402_25V6
@EMI@
1
2
2017/06/02 PL906 change common part
SH000011H00 7*7*6
4.7_1206_5%
680P_0603_50V7K
12
12
PC925
EMI@
PC927
PC926
10U_0603_25V6M
10U_0603_25V6M
2200P_0402_50V7K
DCR=0.98m ohm +-5%
Common part SH000011H00
4
PL906
0.22UH_24A_20%_ 7X7X4_M
3
Size
Size
Size
C
C
C
Date: Sheet o f
Date: Sheet o f
Date: Sheet o f
PC922
PR907
0.22U_0603_16V7K
+19VB_CPU
InputCapa citor:
10uF_0805 _X5R_25V
+VCC_GT
+VCC_GT
CSN_GT1 <48>
SWN_GT1 <48>
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Power Train
Power Train
Power Train
Document Number Re v
Document Number Re v
Document Number Re v
LA-F241P
LA-F241P
LA-F241P
E
49 54Friday, June 09, 2017
49 54Friday, June 09, 2017
49 54Friday, June 09, 2017
0.1
0.1
0.1
A
B
C
D
E
+VCC_CORE
22U_0603_6.3V6M
22U_0603_6.3V6M
12
1U_0201_4V6M
12
22U_0603_6.3V6M
U42@
PC9096
12
PC9027
22U_0603_6.3V6M
12
12
PC9053
22U_0603_6.3V6M
12
12
22U_0603_6.3V6M
U42@
PC9156
12
PC9081
+VCC_GTX_VCORE
1U_0201_4V6M
PC9110
12
12
1U_0201_4V6M
PC9130
12
12
22U_0603_6.3V6M
22U_0603_6.3V6M
12
1U_0201_4V6M
1U_0201_4V6M
1 1
1U_0201_4V6M
1U_0201_4V6M
PC9155
PC9154
12
12
2 2
22U_0603_6.3V6M
U42@
12
12
PC9085
3 3
22U_0603_6.3V6M
PC9003
12
12
@
22U_0603_6.3V6M
PC9029
22U_0603_6.3V6M
PC9028
12
12
22U_0603_6.3V6M
PC9055
22U_0603_6.3V6M
12
12
PC9054
+VCC_GT_VCORE
22U_0603_6.3V6M
U42@
22U_0603_6.3V6M
U42@
12
12
PC9082
PC9083
1U_0201_4V6M
1U_0201_4V6M
PC9111
PC9112
12
12
1U_0201_4V6M
1U_0201_4V6M
PC9132
PC9131
12
12
PC9004
22U_0603_6.3V6M
PC9002
@
22U_0603_6.3V6M
PC9007
22U_0603_6.3V6M
PC9006
22U_0603_6.3V6M
PC9005
PC9030
PC9056
22U_0603_6.3V6M
U42@
PC9084
PC9113
PC9133
12
12
12
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
PC9032
12
12
12
@
PC9031
PC9064
22U_0603_6.3V6M
22U_0603_6.3V6M
12
1U_0201_4V6M
12
1U_0201_4V6M
12
22U_0603_6.3V6M
12
12
PC9057
22U_0603_6.3V6M
12
1
1
+
+
PC9100
U42@
PC9102
PC9101
2
2
U42@
U42@
220U_D2 SX_2VY_R9M
220U_D2 SX_2VY_R9M
1U_0201_4V6M
1U_0201_4V6M
PC9115
PC9114
12
12
1U_0201_4V6M
1U_0201_4V6M
PC9134
PC9135
12
12
@
PC9010
22U_0603_6.3V6M
PC9008
PC9009
22U_0603_6.3V6M
12
PC9033
22U_0603_6.3V6M
12
PC9034
22U_0603_6.3V6M
PC9065
12
PC9066
22U_0603_6.3V6M
PC9097
12
PC9080
1
+
2
220U_D2 SX_2VY_R9M
1U_0201_4V6M
PC9116
PC9117
12
1U_0201_4V6M
PC9137
PC9136
12
12
22U_0603_6.3V6M
12
22U_0603_6.3V6M
12
22U_0603_6.3V6M
12
22U_0603_6.3V6M
12
+VCC_CORE
1U_0201_4V6M
12
1U_0201_4V6M
12
PC9001
22U_0603_6.3V6M
12
22U_0603_6.3V6M
PC9036
12
PC9035
@
PC9067
22U_0603_6.3V6M
12
PC9068
PC9098
PC9099
22U_0603_6.3V6M
12
22U_0603_6.3V6M
12
PC9104
PC9103
PC9105
1U_0201_4V6M
PC9119
PC9118
12
1U_0201_4V6M
PC9139
PC9138
12
SGA20221 D40
PC9012
22U_0603_6.3V6M
PC9013
22U_0603_6.3V6M
PC9014
PC9011
22U_0603_6.3V6M
12
12
PC9037
22U_0603_6.3V6M
22U_0603_6.3V6M
12
12
@
PC9058
22U_0603_6.3V6M
22U_0603_6.3V6M
12
12
22U_0603_6.3V6M
22U_0603_6.3V6M
12
12
PC9086
1
+
2
220U_D2 SX_2VY_R9M
0.47U_0201_4V6M
1U_0201_4V6M
@
PC9120
12
12
22U_0603_6.3V6M
PC9015
12
PC9038
22U_0603_6.3V6M
12
PC9059
22U_0603_6.3V6M
12
22U_0603_6.3V6M
@
12
PC9087
1U_0201_4V6M
PC9121
12
22U_0603_6.3V6M
12
12
PC9040
22U_0603_6.3V6M
PC9041
22U_0603_6.3V6M
PC9039
12
12
PC9062
22U_0603_6.3V6M
PC9060
PC9061
22U_0603_6.3V6M
12
12
22U_0603_6.3V6M
22U_0603_6.3V6M
@
@
@
12
12
@
PC9088
PC9122
PC9090
PC9089
1U_0201_4V6M
1U_0201_4V6M
PC9124
PC9123
12
12
@
@
@
22U_0603_6.3V6M
PC9016
22U_0603_6.3V6M
12
12
22U_0603_6.3V6M
PC9042
22U_0603_6.3V6M
12
12
@
22U_0603_6.3V6M
PC9063
22U_0603_6.3V6M
12
12
22U_0603_6.3V6M
22U_0603_6.3V6M
@
12
12
PC9091
22U_0603_6.3V6M
12
@
0.47U_0201_4V6M
1U_0201_4V6M
PC9125
12
12
+VCC_GT
+VCC_GT
@
@
PC9017
PC9018
22U_0603_6.3V6M
12
PC9043
PC9044
22U_0603_6.3V6M
12
@
PC9069
PC9070
22U_0603_6.3V6M
12
22U_0603_6.3V6M
12
PC9092
PC9093
PC9020
22U_0603_6.3V6M
PC9019
22U_0603_6.3V6M
12
12
PC9045
22U_0603_6.3V6M
PC9046
22U_0603_6.3V6M
12
12
PC9072
22U_0603_6.3V6M
PC9071
22U_0603_6.3V6M
12
12
@
PC9094
22U_0603_6.3V6M
PC9095
22U_0603_6.3V6M
12
12
22U_0603_6.3V6M
22U_0603_6.3V6M
12
12
PC9021
PC9022
PC9049
22U_0603_6.3V6M
PC9047
22U_0603_6.3V6M
PC9048
22U_0603_6.3V6M
12
12
1U_0201_4V6M
1U_0201_4V6M
PC9073
12
12
PC9050
22U_0603_6.3V6M
12
12
1U_0201_4V6M
1U_0201_4V6M
PC9074
PC9075
12
12
SA
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
12
12
12
PC9106
PC9107
PC9109
PC9108
pop:
22uF_0603*9
1uF_0201*7
unpop:
22uF_0603*3
@
0.47U_0201_4V6M
PC9126
12
0.47U_0201_4V6M
1U_0201_4V6M
@
PC9127
PC9129
PC9128
12
12
220uF*1
22uF*36
1uF*9
+VCC_SA
+VCC_SA
PC9159
22U_0603_6.3V6M
12
PC9051
22U_0603_6.3V6M
PC9052
22U_0603_6.3V6M
12
12
1U_0201_4V6M
1U_0201_4V6M
1U_0201_4V6M
PC9077
PC9076
12
PC9079
PC9078
12
12
0.47uF*4
1U_0201_4V6M
1U_0201_4V6M
1U_0201_4V6M
12
1U_0201_4V6M
1U_0201_4V6M
1U_0201_4V6M
1U_0201_4V6M
PC9141
PC9140
PC9142
12
PC9143
12
12
12
1U_0201_4V6M
PC9144
PC9145
12
12
1U_0201_4V6M
1U_0201_4V6M
PC9146
12
1U_0201_4V6M
PC9148
PC9147
PC9149
12
12
1U_0201_4V6M
12
1U_0201_4V6M
PC9151
PC9150
PC9152
12
12
12
+VCC_GTX_VCORE
U42@
PR9001
2
1U_0201_4V6M
1U_0201_4V6M
PC9157
PC9158
12
12
+VCC_CORE
112
SOLDER_PREFORMS_0402
U42@
PR9002
2
112
SOLDER_PREFORMS_0402
+VCC_GT_VCORE
1U_0201_4V6M
PC9153
unpop:
22uF *8
1uF*1
U22@
+VCC_GT
2016/10/26
4 4
VCORE Output Capacitor:
U42
22uF_0603*39
1uF_0201*35
220uF *3
UNPOP
22_0603*3
A
2016/10/26
VCORE Output Capacitor:
U22
22uF_0603*33
1uF_0201*35
UNPOP
22_0603*9
220uF *3
B
PR9003
2
112
SOLDER_PREFORMS_0402
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE S ECRET INFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R& D
AND TRADE S ECRET INFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R& D
AND TRADE S ECRET INFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R& D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTP RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTP RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTP RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2017/02/22 2018/02/22
2017/02/22 2018/02/22
2017/02/22 2018/02/22
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Power Train
Power Train
Power Train
Size
Size
Size
Document Number Re v
Document Number Re v
Document Number Re v
C
C
C
LA-F241P
LA-F241P
LA-F241P
Date: Sheet o f
Date: Sheet o f
Date: Sheet o f
E
50 54Friday, June 09, 2017
50 54Friday, June 09, 2017
50 54Friday, June 09, 2017
0.1
0.1
0.1
5
4
3
2
1
Version change list (P.I.R. List) Page 1 of 1
for PWR
Item
Reason for change
Rev. PG#
01
D D
02
03
Design Change.
CPU setting
0.2 55
PC818 change to 33 pF.
PC834 Change to 8200pF
PC820 Change to 0.033 uF
PR857 Change to 73.2K ohm
PR836 Change to 61.9K ohm
04
Modify List Date PhaseFixed Issue
9/21
PVTON FAE suggest to modify Parts for Kaby lake
05
06
Design Change.
For material issue, Changer main source part
0.2
07
08
Design Change.
For material issue, Changer main source part
1.0 PQ502 change to SB000010A00.
09
C C
10
11
12
Design Change.
For PD power function, add 0 ohm
1.0
56
PC9004,PC9079 change to SF000007700 (33 uF).
PL9006 change to SH00000PK00 (0.47uH).
48
PD101, PD102 change to SCS00005X00.
52
PQ305, PQ503 change to SB00000H800.50, 52
56, 60 PQ1201,PQ1203,PQ9002,PQ9005 change to SB00000JZ00.
56, 60 PQ1202,PQ1204,PQ9003,PQ9007 change to SB000017Q00.
50
50
51
PQ303 change to SB000017B00.
PQ306 change to SB00000H700.
Add PR416 (0 ohm)
9/30
1/4
1/4
PVT
Pre-MP
Pre-MP
13
14
B B
14
A A
Security Cl assification
Security Cl assification
Security Cl assification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAYNOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAYNOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAYNOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENTEXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS
DEPARTMENTEXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS
DEPARTMENTEXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS
MAYBE USED BY OR DISCLOSED TOANY THIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAYBE USED BY OR DISCLOSED TOANY THIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAYBE USED BY OR DISCLOSED TOANY THIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2017/02/22 2018/02/22
2017/02/22 2018/02/22
2017/02/22 2018/02/22
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
PIR
PIR
PIR
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Custom
Custom
Custom
LA-F241P
LA-F241P
LA-F241P
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
1
51 54Friday, June 09, 2017
51 54Friday, June 09, 2017
51 54Friday, June 09, 2017
0.1
0.1
0.1
A
B
C
D
E
1K
1K
BH10
1 1
Skylake
BG12
SOC_SMBCLK
SOC_SMBDATA
+3VS
SO-DIMM 1
SO-DIMM 2
SOC
SOC_SML0CLK
SOC_SML0DATA
499
499
+3VS
1K
1K
SOC_SML1CLK
SOC_SML0DATA
2 2
+3VS
2.2K
+3VLP_E C
100 ohm
100 ohm
SCL 1
SDA 1
77
78
2.2K
EC_SMB_CK1
EC_SMB_DA1
0 ohm
0 ohm
KBC
3 3
KB9022
SCL 2
SDA 2
79
80
SOC_SML1CLK
SOC_SML0DATA
XDP
EC_SMB_CK1_CHGR
EC_SMB_DA1_CHGR
7
6
12
11
BATTERY
CONN
Charge r
1.8K
1.8K
2N7002DW
4 4
A
B
I2CS_SCL
I2CS_SDA
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
+3VSDGPU_AON
VGA
2014/11/ 10 2016/11/ 10
2014/11/ 10 2016/11/ 10
2014/11/ 10 2016/11/ 10
C
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
SMBUS_Routing_Table
SMBUS_Routing_Table
SMBUS_Routing_Table
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Custom
Custom
Custom
C4PB1/C5PB1 LA-591
C4PB1/C5PB1 LA-591
C4PB1/C5PB1 LA-591
Date : Sheet o f
Date : Sheet o f
D
Date : Sheet o f
61 64Friday, June 0 9, 2017
61 64Friday, June 0 9, 2017
61 64Friday, June 0 9, 2017
E
0.1
0.1
0.1
5
P6->P6 U42
EVT_R0.1
4/24
1. ADD TS conn. JTS1
2. Add USB PORT 10 for TS function
3. Reserve USB PORT 6 test point(T3821,T3822) for NFC
4. Remove GPU circuit
5. Support PD charger in
D D
6. ADD U5010 circuit for TS function
7. Add 24M XTAL(YC3) for KBL U42
8. +VCC_GTX_CORE contact to CPU (UC1.M)
9. +VCC_GT_CORE contact to CPU (UC1.M)
10. Add RC256
11. Del UC9 circuit
12. DEL RC58 (direct contact U11, U12)
13. Add TBTA_HV_GATE1/2 for PD in
14. Add TBTA_PD_SENSEP/N for PD in
15. DEL H23,H24
16. DEL RC204, RC195
17. Reserve test point T3812~3815 for GPU
18. update PARADE X76, X76525BOL05
19. Change RC38 to 121ohm
20. DEL XDP circuit
21. change RC182 to 0ohm@
22. Add R5274 for ME906
23. ADD HYNIX 8G SA0000ARA10 on board ram
24. ADD T3849
25. ADD SATAXPCIE2
C C
26. ADD R5276,R5275@, Q2023@ for PCIE SSD
27. Change Card reader to PCIE port4
28. ADD PCIE port 10 for PCIE_SSD
29. ADD CLK port 0 for PCIE_SSD
30. ADD D2018,D2019,D2020,D2021,D2022,D2023 for ESD
31. ADD CC435,CC436
32. ADD RC258
4/25
1. Q40,Q51,Q52,Q53,Q2006,Q2010,Q2013,Q2014,Q2016,
Q2017,Q2018,Q2019,Q2020,Q2021,QL2, change PN to SB00000SA00
2. Change U67 PN to SA00007IOA0 NPCT650ABCWX
4
3
2
1
PVT_R1.0
5/10
Swap JSSD1 PIN41,43 net
6/3
R401 chager to 47K for RF request(ME906)
Add RC 259 for CLKREQ_PCIE#0 pull up +3VS
change R5196,R4960 to @
change R5205 to 100Kohm TBT@
change R659 to mount
change UC2 PN to SA00005VV20
swap JSSD PCIE port 11,12
SSD_DET# connect to SATAXPCIE1
change R4903 to 12K
Add C5265 for PCIE SSD power
Add Adp_det
change R4938 to 0ohm
VCOUT1_PROCHOT connect to HPROCHOT#
remove J13 for C5265
6/8
Add R5277 for +5VS_CRT_SW
Add L4905 for +3VS_CRT_SW
SW_PROCHOT# connect to H_PROCHOT#
Change R4960 to mount
Change R523,R4938,R5276 to short pad
Change R5260 to 0ohm
Add Q2024,R5279,R5278 for +1.8VALW_PRIM discharge circuit
Change UU24, CU181, RU165 to @
6/8A
remove RC151
6/9
change R5193 to 0ohm_0402
4/26
Change U67 to SA00007IOA0
4/27
change R5207,R5208 to TBT@ and R5266,R5267 to @ for support dead battery
B B
5/4
modify yellow BOM structure to meet white item
CC53,D17,D18,D19,D20,D21,D23,D24,R5196,R5204,R5207,R5208
A A
Security Cl assification
Security Cl assification
Security Cl assification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAYNOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAYNOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAYNOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENTEXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS
DEPARTMENTEXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS
DEPARTMENTEXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS
MAYBE USED BY OR DISCLOSED TOANY THIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAYBE USED BY OR DISCLOSED TOANY THIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAYBE USED BY OR DISCLOSED TOANY THIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2016/07/29 2016/07/29
2016/07/29 2016/07/29
2016/07/29 2016/07/29
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
HW PIR
HW PIR
HW PIR
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Custom
Custom
Custom
C4PB1/C5PB1 LA-E591P
C4PB1/C5PB1 LA-E591P
C4PB1/C5PB1 LA-E591P
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
1
63 64Friday, June 09, 2017
63 64Friday, June 09, 2017
63 64Friday, June 09, 2017
1.0
1.0
1.0
5
4
3
2
1
DDR4 On Board RAM
X76713BOL03 Hynix X76713BOL01 micron 4G X76713BOL02 micron 8G
D4 512M16 H5AN8G6NAFR
SA0000A1H20
D D
U2
X76OBHY@
D4 512M16 H5AN8G6NAFR
SA0000A1H20
U3
X76OBHY@
D4 512M16 H5AN8G6NAFR
SA0000A1H20
U4
X76OBHY@
D4 512M16 H5AN8G6NAFR
SA0000A1H20
U5
X76OBHY@
10K +-5% 0402
SD028100280
RU173
X76OBHY@
10K +-5% 0402
SD028100280
RU169
X76OBHY@
D4 512M16 MT40A512M16JY
SA00009V220
U2
X76OBMACRON4@
D4 512M16 MT40A512M16JY
SA00009V220
U3
X76OBMACRON4@
D4 512M16 MT40A512M16JY
SA00009V220
U4
X76OBMACRON4@
D4 512M16 MT40A512M16JY
SA00009V220
U5
X76OBMACRON4@
10K +-5% 0402
SD028100280
RU170
X76OBMACRON4@
10K +-5% 0402
SD028100280
RU172
X76OBMACRON4@
D4 16G MT40A1G16WBU
SA0000A3120
U2
X76OBMACRON8@
D4 16G MT40A1G16WBU
SA0000A3120
U3
X76OBMACRON8@
D4 16G MT40A1G16WBU
SA0000A3120
U4
X76OBMACRON8@
D4 16G MT40A1G16WBU
SA0000A3120
U5
X76OBMACRON8@
10K +-5% 0402
SD028100280
RU169
X76OBMACRON8@
10K +-5% 0402
SD028100280
RU170
X76OBMACRON8@
X76713BOL06 HYNIX 8G
D4 16G/2400 H5ANAG6NAMR
SA0000ARA10
U2
X76OBHYNIX8@
D4 16G/2400 H5ANAG6NAMR
SA0000ARA10
U3
X76OBHYNIX8@
D4 16G/2400 H5ANAG6NAMR
SA0000ARA10
U4
X76OBHYNIX8@
D4 16G/2400 H5ANAG6NAMR
SA0000ARA10
U5
X76OBHYNIX8@
10K +-5% 0402
SD028100280
RU173
X76OBHYNIX8@
10K +-5% 0402
SD028100280
RU172
X76OBHYNIX8@
VRAM
C C
X76614BOL54 Hynix X76614BOL58 SANSUNG
D3 256M16 H5TC4G63CFR
SA00008DN10
U2004
X76VHY@
D3 256M16 H5TC4G63CFR
SA00008DN10
U2005
X76VHY@
D3 256M16 H5TC4G63CFR
SA00008DN10
U2006
X76VHY@
D3 256M16 H5TC4G63CFR
SA00008DN10
U2007
X76VHY@
30K +-1% 0402
SD034300280
R2044
X76VHY@
D3 256M16 K4W4G1646E
SA000076PB0
U2004
X76VSAM@
D3 256M16 K4W4G1646E
SA000076PB0
U2005
X76VSAM@
D3 256M16 K4W4G1646E
SA000076PB0
U2006
X76VSAM@
D3 256M16 K4W4G1646E
SA000076PB0
U2007
X76VSAM@
24.9K +-1% 0402
SD034249280
R2044
X76VSAM@
X76713BOL04 Hynix E-die
S IC D3 256M16 H5TC4G63EFR-N0C
SA00008DN80
U2004
X76VHY_E@
S IC D3 256M16 H5TC4G63EFR-N0C
SA00008DN80
U2005
X76VHY_E@
S IC D3 256M16 H5TC4G63EFR-N0C
SA00008DN80
U2006
X76VHY_E@
S IC D3 256M16 H5TC4G63EFR-N0C
SA00008DN80
U2007
X76VHY_E@
10K_0402_1%
SD034100280
R2035
X76VHY_E@
SATA Redriver
X76525BOL51 TI
B B
A A
SN75LVCP601RTJR
SA00003ZX00
U1
X76SATATI@
4.99K +-1% 0402
SD034499180
R11
X76SATATI@
5
X76713BOL05 Parade X76525BOL52 Parade
PS8527CTQFN20GTR2-A2
SA00007JU10
U1
X76SATAPAR@
4.7K +-5% 0402
SD028470180
R18
X76SATAPAR@
7.5K +-5% 0402
SD028100280
R11
X76SATAPAR@
4
PS8527CTQFN20GTR2-A1
SA00007JU00
U1
X76SATAPARa@
4.7K +-5% 0402
SD028470180
R18
X76SATAPARa@
7.5K +-5% 0402
SD028100280
R11
X76SATAPARa@
Security Cl assification
Security Cl assification
Security Cl assification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAYNOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAYNOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAYNOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENTEXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS
DEPARTMENTEXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS
DEPARTMENTEXCEPT AS AUTHORIZED BY COMPALELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS
MAYBE USED BY OR DISCLOSED TOANY THIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAYBE USED BY OR DISCLOSED TOANY THIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAYBE USED BY OR DISCLOSED TOANY THIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2014/11/10 2016/11/10
2014/11/10 2016/11/10
2014/11/10 2016/11/10
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
X76 Level Note
X76 Level Note
X76 Level Note
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Custom
Custom
Custom
C4PB1/C5PB1 LA-E591P
C4PB1/C5PB1 LA-E591P
C4PB1/C5PB1 LA-E591P
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
64 64Friday, June 09, 2017
64 64Friday, June 09, 2017
64 64Friday, June 09, 2017
1.0
1.0
1.0
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