Compal LA-E992P Schematic

A

B

C

D

E

MODEL NAME :

PCB NO :

LA-E992P

CKF50/CKA50

BOM P/N :

1 1

451A7631L51 451A7631L52 451A7631L01 451A7631L02

Dell/Compal Confidential

Schematic Document

KABYLAKE-H

2 2

N17E

Firestar/Armani

2017-07-25

Rev: 1.0 (A00)

3 3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2011/08/25 2011/08/25

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Cover Page

LA-E992P

E

1.0(A00)

1 77Tuesday, July 25, 2017

1.0(A00)

A

256M*32 x6 =6G

VRAM * 6 GDDR5

B

C

D

E

P28

P33P33

P29

P23

P17

P27

GB4-256

P46-55

P39~40

PEG 3.0 x16

DDI3 x2

P35

DDI1 x4 DDI2 x4

PCI-E x4

Port 1-Port 4

PCI-E x1

Port 6

PCI-E x1

Port 5

PCI-E x4

Port 9-Port 12

SATA0A

SATA1B

HD Audio

SPI

SMBus

I2C

Intel

KBL-Lake-H

Processor

45W

BGA

DMI x4

100MHz 5GB/s

Intel

KBL-H-PCH

BGA 837 Balls

HM175

P7-13

P16-22

DDR4 ChannelA DDR4 ChannelB

eDP1.4 x4

USB2.0

Port 1

USB3.0

Port 1

USB Powershare TPS2544

USB 3.0 Re-driver PS8713

USB2.0 USB3.0

USB2.0

USB2.0 SD3.0

Port 7

Card Reader 2 in 1 RTS5176E SD / MS

USB2.0

Port 8

HDMI 2.0 Conn.

1 1

P45

Retimer PS8409A

CRT Conn.

P44

IFPHDMI2.0

P35

GPU N17E-G1

DP to VGA RTD2166-CG

CIO/USB3.1

USB3.1 TypeC

2 2

3 3

P41

USB2.0/CC

Main SPKR *2

Universal Audio Jack

TPS65982D

RJ45

P24

P41

I2C/USB2.0

TPM NPCT650VBCYX

Thunderbolt Alpine Ridge-SP

M.2 Slot A Key-E

(WLAN+BT4.0)

LOM RTL8111H

M.2 Slot C Key-M

(SATA/PCIe SSD)

HDD Conn.

HDA Codec ALC3246

SPI Flash (BIOS 16MB)

DDRIV-DIMM X2

1.2V DDR4 2400 MHz

P14-15

32GB Max

15.6'' HD/FHD / UHD

P31

P31 P31

Port 2 Port 2

Port 3 Port 3

Port 12

Port 4

Port 9

P34 P34

P38

USB 3.0

Type-A

USB 3.0

Type-A

USB 3.0

Type-A

Digital Camera Conn.

M.2 Slot A Key-EUSB2.0

(WLAN+BT4.0)

Touch Panel Conn.

Touch Finger Print w/ power button Conn.

Left

Right

P32

Right

P32

P38

P28

P38

P37

Power Button Board

MEC1416

KBC

SMBus

C

eSPI

P36

Charger & Battery

PWM

I2C

FAN

P26

Thermal Sensor F75303M

KB Conn.

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

P27

P25

AC Adaptor

P59P59/P60

Compal Secret Data

2011/08/25 2011/08/25

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Block diagram

Size Document Number Rev

Date: Sheet of

E

LA-E992P

2 77Tuesday, July 25, 2017

1.0(A00)

FFS LNG2DMTR

4 4

P29

Touch Pad

LED

PS2

P26

P37

LED Board

Power Button

P37

Power Button Board

A

B

5

4

3

2

1

Page 61

+5VALW

+3VALW

Page 62

Page 64

Page 74

Page 69

Page 65

Page 72

DC IN

Page 59

D D

C C

VIN

CHARGER BQ24780

Battery 56Whr 4S1P for 15'

Page 60

B+

+3VALW TDC:5.823A +5VALW TDC:10.34A TPS51285B (Module)

+1.2V TDC:7.95A +0.6VS TDC:1.05A RT8207P(Module)

+1VALW TDC:4.2805A SY8286 (Module)

+VCCIO TDC: 3.85A SY8286 (Module)

+1.35VS_VGAP TDC: 19.8A TPS51212 (Module)

+1.8VSP TDC: 1.289A SY8286 (Module)

+VCC_CORE TDC: 49A ISL95829 (Module)

+1.0VS_VGA TDC: 0.9835A RT8061

+2.5V_MEM TDC:0.428A RT9059GSP_SO8 (LDO)

+1.2V_DDR

+0.6VS

+1VALW

+VCCIO

+1.35VS_VGA

+1.8V_PRIM

+VCC_CORE

+PEX_VDD

Page 66

+2.5V_MEM

Page 63

2

+VCCGT

+VCCSA

+NVVDD1

Compal Electronics, Inc.

Title

Power Block Diagram

Size Document Number Rev

Date: Sheet of

LA-E992P

1

0.3(X02)

58 77Tuesday, July 25, 2017

0.3(X02)

+VCC_GT TDC: 38.5A ISL95829 (Module)

B B

+VCC_SA TDC: 7.77A ISL95829 (Module)

N17E G1 MAX-Q GPU_CORE TDC: 70A UP9511P

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/08/25 2012/07/25

3

Compal Secret Data

Deciphered Date

Page 73

Page 68

A

B

C

D

E

Compal Confidential

Project Code : File Name :

1 1

ME Hole Location

M/B

2 2

3 3

Base on ME 0505

LED Board PWB Board

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/08/25 2012/07/25

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

DB block diagram

LA-E992P

1.0(A00)

3 77Tuesday, July 25, 2017

E

A

Refer Page 36

PCI EXPRESS

Lane 1

Lane 2

Lane 3

Lane 4

Lane 5

Lane 6

Lane 7

Lane 8 None

Lane 9

Lane 10

Lane 11

DESTINATION

Alpine Ridge - SP

LOM

NGFF - WLAN + BT

None

NGFF - SSD

7

8

9

10

SATA

0A

1A

DESTINATIONUSB3

None

DESTINATION

NGFF - SSD

None

Lane 12

Lane 13

Lane 14

Lane 15

Lane 16

1 1

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

None

DESTINATIONCLK_PCIE

None

LOM

NGFF - WLAN + BT

None

Alpine Ridge - SP

NGFF - SSD

GPU

None

0B

2

3

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

None

HDD1B

None

DESTINATIONCLK_REQ

None

LOM

NGFF - WLAN + BT

None

Alpine Ridge - SP

NGFF - SSD

GPU

None

USB2 DESTINATION

1

USB JUSB3 (Left Side)

2

USB JUSB1 (Right Side)

3

USB JUSB2 (Right Side)

4

NGFF - WLAN + BT

None

5

6

None

7

CARD READER

8

Finger Print

9

Touch screen

10

11

12

None

CAMERA

Symbol Note :

: means Digital Ground

: means Analog Ground

USB31DESTINATION

USB JUSB3 (Left Side)

2

USB JUSB1 (Right Side)

3

USB JUSB2 (Right Side)

4

None

5

None

6

None

DDI

1

2

3

DESTINATION

Alpine Ridge

DP to VGA

Board ID

X00

X01

X02

X03

A00

Resistor

10K

17.8K

27K

37.4K

49.9K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/08/25 2012/07/25

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Notes List

Size Document Number Rev

LA-E992P

Date: Sheet of

1.0(A00)

4 77Tuesday, July 25, 2017

5

4

3

2

1

1K

Address: 0x88/0x89

Host

AW44

BB43

D D

AY44

BB39

Host

AR41

AR44

SMBCLK SMBDATA

SML0_SMBCLK SML0_SMBDATA

I2C1_SCK_TP I2C1_SDA_TP

1K

499

2.2K

+3VALW

+3VS

DMN65D8L

+3VALW

+3VS

DMN65D8L

1K

PCH_SMBCLK PCH_SMBDATA

2.4K

I2C1_SCK_TP_C I2C1_SDA_TP_C

+3VS

+3VS_TP

Slave

DIMMA

Slave

DIMMB

Slave

FFS

Slave

RTD2166

Slave

Touch Pad

Address: 0xA0/0xA1

Address: 0xA4/0xA5

Address: 0x52/0x53

Address: 0x64/0x65, 0x68/0x69

Address: 0x2C/0x2D

PCH

C C

2.2K

Slave

AW42

AW45

GPU_THM_SMBCLK GPU_THM_SMBDAT

B B

Host

+3VALW_EC

+3VS

DMN65D8L

ALL_GPWRGD

DMN65D8L

4.7K

PBAT_CHG_SMBCLK

MEC1416

Host

PBAT_CHG_SMBDAT

Host

TYPEC_SMBCLK

2.2K

0 Ohm

TYPEC_SMBDA

A A

0 Ohm

10K

1.8K

+3VALW_EC

+3VS

THM_SML1_CLK THM_SML1_DATA

+1V8_AON

VGA_SMB_CK2 VGA_SMB_DA2

Slave

BATT

Slave

CHAGER

Address: 0x16/0x17

Address: 0x12/0x13

PD_I2C_SCL_R PD_I2C_SDA_R

Slave

Thermal Sensor

Slave

GPU

10K(@)

Address: 0x9A/0x9B

Address: 0x9E/0x9F

+3VS

Slave

TPS65982D

Address: 0x70/0x71

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/08/25 2012/07/15

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

SMBus Block Diagram

Size Document Number Rev

Custom

Date: Sheet of

LA-E992P

1

5 77Tuesday, July 25, 2017

1.0(A00)

5

+VCCST

D D

+VCCSTG

+1V_PCH

C C

+3VALW

+VCCIO

+3V_ROM

+3V_PCH_DSW

B B

1 2

RH97 51_0402_5%@

1 2

RH98 51_0402_5%@

1 2

RH100 51_0402_5%@

1 2

RH497 51_0402_5%

1 2

RH496 51_0402_5%

1 2

RH56 51_0402_5%

1 2

RH95 51_0402_5%

1 2

RH61 51_0402_5%

1 2

RH60 51_0402_5%

1 2

RH520 2.2K_0402_5%

1 2

RH521 2.2K_0402_5%

1 2

RH526 150_0402_5%

1 2

RH540 1K_0402_5%XDP@

1 2

RH529 1K_0402_5%XDP@

+3VS

1 2

RH531 1K_0402_5%

0.1U_0402_10V7K

PCH_JTAG_TDO

PCH_JTAG_TMS

PCH_JTAG_TDI

CPU_XDP_TDO

CPU_XDP_TMS

CPU_XDP_TDI

PCH_JTAG_TCK

CPU_XDP_TCK

CPU_XDP_TRST#

XDP_PLTRST#

PCH_SYS_PWROK_XDP

PWR_DEBUG#_XDP

XDP_PRESENT#

XDP_DBRESET# SYS_RESET#

XDP@

1

CH206

2

1 2

RH528 1K_0402_5%

1 2

RH519 1K_0402_5%XDP@

1 2

RH530 0_0402_5%@

Pilot Change RH530 to 0ohm 0402 short-pad footprint.

1 2

RH532 0_0402_5%@

XDP@

1

CH207

0.1U_0402_10V7K

2

4

CFG0

PCH_SPI_WP#

SIO_PWRBTN#PWRBTN#_XDP

DVT2.0 Change RH532 to 0ohm 0402 short-pad footprint.

PCH_SPI_WP# <17>

SIO_PWRBTN# <18,36>

SYS_RESET# <18>

3

PCH_ITP_PMODE<18>

PLTRST_CPU#<9,16>

SYS_PWROK<18,36>

PCH_SPI_SI<17,27>

PCH_RSMRST#<18,36>

H_VCCST_PWRGD<9,18>

CFG[0..19]<9>

CFG3

RH517 1K_0402_5%XDP@

XDP_PREQ#<9,22>

XDP_PRDY#<9,22>

XDP_BPM#0<9> XDP_BPM#1<9>

PCH_SMBDATA<14,15,18,29,35>

PCH_SMBCLK<14,15,18,29,35>

PCH_JTAG_TCK<18> CPU_XDP_TCK<9,18>

PCH_ITP_PMODE

PLTRST_CPU# XDP_PLTRST#

SYS_PWROK

PCH_SPI_SI PCH_SYS_PWROK_XDP

PCH_RSMRST#

H_VCCST_PWRGD XDP_PWRGOOD

12

XDP_PREQ# XDP_PRDY#

CFG0 CFG1

CFG2 CFG3

XDP_BPM#0 XDP_BPM#1

CFG4 CFG5

CFG6 CFG7

XDP_PWRGOOD PWRBTN#_XDP

PWR_DEBUG#_XDP PCH_SYS_PWROK_XDP

PCH_SMBDATA PCH_SMBCLK PCH_JTAG_TCK CPU_XDP_TCK

RH518

0_0402_5%

2

1 2

RH522 0_0402_5%XDP@

1 2

RH523 1K_0402_5%@

1 2

RH524 0_0402_5%@

1 2

RH525 1K_0402_5%XDP@

1 2

RH541 1K_0402_5%XDP@

1 2

RH542 1K_0402_5%@

+1V_PCH +1V_PCH

JXDP1

2

112

4

334

6

556

8

778

10

9910

12

111112

14

131314

16

151516

18

171718

20

191920

22

212122

24

232324

26

252526

28

272728

30

292930

32

313132

34

333334

36

353536

38

373738

40

393940

42

414142

44

434344

46

454546

48

474748

50

494950

52

515152

54

535354

56

555556

58

575758

60

12

@

595960

SAMTE_BSH-030-01-L-D-A-TR

CONN@

CFG17 CFG16

CFG8 CFG9

CFG10 CFG11

CFG19 CFG18

CFG12 CFG13

CFG14 CFG15

PCH_XDP_CLK_P PCH_XDP_CLK_N

XDP_PLTRST# XDP_DBRESET#

XDP_TDO XDP_TRST# XDP_TDI XDP_TMS XDP_PRESENT#

1

PCH_XDP_CLK_P <17> PCH_XDP_CLK_N <17>

XDP@

1

CH205

0.1U_0402_10V7K

2

XDP_TDO

XDP_TDI

XDP_TMS

XDP_TRST#

A A

5

Pilot Change RH533, RH534, RH535, RH536 to 0ohm 0402 short-pad footprint.

1 2

RH533 0_0402_5%@

1 2

RH534 0_0402_5%@

1 2

RH535 0_0402_5%@

1 2

RH536 0_0402_5%@

CPU_XDP_TDO

CPU_XDP_TDI

CPU_XDP_TMS

CPU_XDP_TRST#

4

CPU PCH

CPU_XDP_TDO <9>

CPU_XDP_TDI <9>

CPU_XDP_TMS <9>

CPU_XDP_TRST# <9,22>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

XDP_TMS

XDP_TDI

XDP_TDO PCH_JTAG_TDO

Pilot Change RH538, RH537, RH539 to 0ohm 0402 short-pad footprint.

2011/08/25 2012/07/25

1 2

RH538 0_0402_5%@

1 2

RH537 0_0402_5%@

1 2

RH539 0_0402_5%@

Compal Secret Data

Deciphered Date

PCH_JTAG_TMS

PCH_JTAG_TDI

2

PCH_JTAG_TMS <18>

PCH_JTAG_TDI <18>

PCH_JTAG_TDO <18>

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

XDP CONN

LA-E992P

1

1.0(A00)

of

6 77Tuesday, July 25, 2017

5

4

3

2

1

PEG_HTX_C_GRX_P[0..15]<46>

PEG_HTX_C_GRX_N[0..15]<46>

PEG_GTX_C_HRX_P[0..15]<46>

PEG_GTX_C_HRX_N[0..15]<46>

D D

C C

B B

A A

PEG_HTX_C_GRX_P[0..15]

PEG_HTX_C_GRX_N[0..15]

PEG_GTX_C_HRX_P[0..15]

PEG_GTX_C_HRX_N[0..15]

TBT-AR

DP to VGA

PEG_GTX_C_HRX_P15 PEG_GTX_C_HRX_N15

PEG_GTX_C_HRX_P14 PEG_GTX_C_HRX_N14

PEG_GTX_C_HRX_P13 PEG_GTX_C_HRX_N13

PEG_GTX_C_HRX_P12 PEG_GTX_C_HRX_N12

PEG_GTX_C_HRX_P11 PEG_GTX_C_HRX_N11

PEG_GTX_C_HRX_P10 PEG_GTX_C_HRX_N10

PEG_GTX_C_HRX_P9 PEG_GTX_C_HRX_N9

PEG_GTX_C_HRX_P8 PEG_GTX_C_HRX_N8

PEG_GTX_C_HRX_P7 PEG_GTX_C_HRX_N7

PEG_GTX_C_HRX_P6 PEG_GTX_C_HRX_N6

PEG_GTX_C_HRX_P5 PEG_GTX_C_HRX_N5

PEG_GTX_C_HRX_P4 PEG_GTX_C_HRX_N4

PEG_GTX_C_HRX_P3 PEG_GTX_C_HRX_N3

PEG_GTX_C_HRX_P2 PEG_GTX_C_HRX_N2

PEG_GTX_C_HRX_P1 PEG_GTX_C_HRX_N1

PEG_GTX_C_HRX_P0

RH24

24.9_0402_1%

PEG_GTX_C_HRX_N0

PEG_RCOMP

DMI_CRX_PTX_P0 DMI_CRX_PTX_N0

DMI_CRX_PTX_P1 DMI_CRX_PTX_N1

DMI_CRX_PTX_P2 DMI_CRX_PTX_N2

DMI_CRX_PTX_P3 DMI_CRX_PTX_N3

CPU_DDI1_P0 CPU_DDI1_N0 CPU_DDI1_P1 CPU_DDI1_N1 CPU_DDI1_P2 CPU_DDI1_N2 CPU_DDI1_P3 CPU_DDI1_N3

DDI1_AUXP DDI1_AUXN

CPU_DDI2_P0 CPU_DDI2_N0 CPU_DDI2_P1 CPU_DDI2_N1 CPU_DDI2_P2 CPU_DDI2_N2 CPU_DDI2_P3 CPU_DDI2_N3

DDI2_AUXP DDI2_AUXN

CPU_DDI3_P0 CPU_DDI3_N0 CPU_DDI3_P1 CPU_DDI3_N1

DDI3_AUXP DDI3_AUXN

+VCCIO

1 2

DMI_CRX_PTX_P0<19> DMI_CRX_PTX_N0<19>

DMI_CRX_PTX_P1<19> DMI_CRX_PTX_N1<19>

DMI_CRX_PTX_P2<19> DMI_CRX_PTX_N2<19>

DMI_CRX_PTX_P3<19> DMI_CRX_PTX_N3<19>

CPU_DDI1_P0<39> CPU_DDI1_N0<39> CPU_DDI1_P1<39> CPU_DDI1_N1<39> CPU_DDI1_P2<39> CPU_DDI1_N2<39> CPU_DDI1_P3<39> CPU_DDI1_N3<39>

DDI1_AUXP<39> DDI1_AUXN<39>

CPU_DDI2_P0<39> CPU_DDI2_N0<39> CPU_DDI2_P1<39> CPU_DDI2_N1<39> CPU_DDI2_P2<39> CPU_DDI2_N2<39> CPU_DDI2_P3<39> CPU_DDI2_N3<39>

DDI2_AUXP<39> DDI2_AUXN<39>

CPU_DDI3_P0<35> CPU_DDI3_N0<35> CPU_DDI3_P1<35> CPU_DDI3_N1<35>

DDI3_AUXP<35> DDI3_AUXN<35>

E25 D25

E24 F24

E23 D23

E22 F22

E21 D21

E20 F20

E19 D19

E18 F18

D17 E17

F16 E16

D15 E15

F14 E14

D13 E13

F12 E12

D11 E11

F10 E10

G2

D8

E8

E6 F6

D5

E5

J8 J9

K36 K37 J35

J34 H37 H36

J37 J38

D27

E27

H34 H33

F37 G38

F34

F35

E37

E36

F26

E26

C34 D34

B36

B34

F33

E33 C33

B33

A27

B27

UH1C

PEG_RXP[0] PEG_RXN[0]

PEG_RXP[1] PEG_RXN[1]

PEG_RXP[2] PEG_RXN[2]

PEG_RXP[3] PEG_RXN[3]

PEG_RXP[4] PEG_RXN[4]

PEG_RXP[5] PEG_RXN[5]

PEG_RXP[6] PEG_RXN[6]

PEG_RXP[7] PEG_RXN[7]

PEG_RXP[8] PEG_RXN[8]

PEG_RXP[9] PEG_RXN[9]

PEG_RXP[10] PEG_RXN[10]

PEG_RXP[11] PEG_RXN[11]

PEG_RXP[12] PEG_RXN[12]

PEG_RXP[13] PEG_RXN[13]

PEG_RXP[14] PEG_RXN[14]

PEG_RXP[15] PEG_RXN[15]

PEG_RCOMP

DMI_RXP[0] DMI_RXN[0]

DMI_RXP[1] DMI_RXN[1]

DMI_RXP[2] DMI_RXN[2]

DMI_RXP[3] DMI_RXN[3]

SKL-H_BGA1440

@

UH1D

DDI1_TXP[0] DDI1_TXN[0] DDI1_TXP[1] DDI1_TXN[1] DDI1_TXP[2] DDI1_TXN[2] DDI1_TXP[3] DDI1_TXN[3]

DDI1_AUXP DDI1_AUXN

DDI2_TXP[0] DDI2_TXN[0] DDI2_TXP[1] DDI2_TXN[1] DDI2_TXP[2] DDI2_TXN[2] DDI2_TXP[3] DDI2_TXN[3]

DDI2_AUXP DDI2_AUXN

DDI3_TXP[0] DDI3_TXN[0] DDI3_TXP[1] DDI3_TXN[1] DDI3_TXP[2] DDI3_TXN[2] DDI3_TXP[3] DDI3_TXN[3]

DDI3_AUXP DDI3_AUXN

SKL-H_BGA1440

@

SKYLAKE_HALO

3 OF 14

SKYLAKE_HALO

4 OF 14

Rev_1.0

PEG_TXP[0] PEG_TXN[0]

PEG_TXP[1] PEG_TXN[1]

PEG_TXP[2] PEG_TXN[2]

PEG_TXP[3] PEG_TXN[3]

PEG_TXP[4] PEG_TXN[4]

PEG_TXP[5] PEG_TXN[5]

PEG_TXP[6] PEG_TXN[6]

PEG_TXP[7] PEG_TXN[7]

PEG_TXP[8] PEG_TXN[8]

PEG_TXP[9] PEG_TXN[9]

PEG_TXP[10] PEG_TXN[10]

PEG_TXP[11] PEG_TXN[11]

PEG_TXP[12] PEG_TXN[12]

PEG_TXP[13] PEG_TXN[13]

PEG_TXP[14] PEG_TXN[14]

PEG_TXP[15] PEG_TXN[15]

DMI_TXP[0] DMI_TXN[0]

DMI_TXP[1] DMI_TXN[1]

DMI_TXP[2] DMI_TXN[2]

DMI_TXP[3] DMI_TXN[3]

Rev_1.0

EDP_TXP[0] EDP_TXN[0] EDP_TXP[1] EDP_TXN[1] EDP_TXN[2] EDP_TXP[2] EDP_TXN[3] EDP_TXP[3]

EDP_AUXP

EDP_AUXN

EDP_DISP_UTIL

EDP_RCOMP

PROC_AUDIO_CLK

PROC_AUDIO_SDI

PROC_AUDIO_SDO

PEG_HTX_GRX_P15

B25

PEG_HTX_GRX_N15

A25

PEG_HTX_GRX_P14

B24

PEG_HTX_GRX_N14

C24

PEG_HTX_GRX_P13

B23

PEG_HTX_GRX_N13

A23

PEG_HTX_GRX_P12

B22

PEG_HTX_GRX_N12

C22

PEG_HTX_GRX_P11

B21

PEG_HTX_GRX_N11

A21

PEG_HTX_GRX_P10

B20

PEG_HTX_GRX_N10

C20

PEG_HTX_GRX_P9

B19

PEG_HTX_GRX_N9

A19

PEG_HTX_GRX_P8

B18

PEG_HTX_GRX_N8

C18

PEG_HTX_GRX_P7

A17

PEG_HTX_GRX_N7

B17

PEG_HTX_GRX_P6

C16

PEG_HTX_GRX_N6

B16

PEG_HTX_GRX_P5

A15

PEG_HTX_GRX_N5

B15

PEG_HTX_GRX_P4

C14

PEG_HTX_GRX_N4

B14

PEG_HTX_GRX_P3

A13

PEG_HTX_GRX_N3

B13

PEG_HTX_GRX_P2

C12

PEG_HTX_GRX_N2

B12

PEG_HTX_GRX_P1

A11

PEG_HTX_GRX_N1

B11

PEG_HTX_GRX_P0

C10

PEG_HTX_GRX_N0

B10

DMI_CTX_PRX_P0

B8

DMI_CTX_PRX_N0

A8

DMI_CTX_PRX_P1

C6

DMI_CTX_PRX_N1

B6

DMI_CTX_PRX_P2

B5

DMI_CTX_PRX_N2

A5

DMI_CTX_PRX_P3

D4

DMI_CTX_PRX_N3

B4

EDP_TXP0

D29

EDP_TXN0

E29

EDP_TXP1

F28

EDP_TXN1

E28

EDP_TXN2

B29

EDP_TXP2

A29

EDP_TXN3

B28

EDP_TXP3

C28

EDP_AUXP

C26

EDP_AUXN

B26

EDP_DISP_UTIL BIA_PWM_PCH

A33

EDP_COMP

D37

EDP_COMP CAD Note:Trace width=20 mils ,Spacing=25mil, Max length=100 mils.

AUD_AZA_CPU_SCLK

G27

AUD_AZA_CPU_SDO

G25

AUD_AZA_CPU_SDI AUD_AZA_CPU_SDI_R

G29

1 2

CH5 0.22U_0201_6.3V6M

1 2

CH6 0.22U_0201_6.3V6M

1 2

CH7 0.22U_0201_6.3V6M

1 2

CH8 0.22U_0201_6.3V6M

1 2

CH9 0.22U_0201_6.3V6M

1 2

CH10 0.22U_0201_6.3V6M

1 2

CH11 0.22U_0201_6.3V6M

1 2

CH12 0.22U_0201_6.3V6M

1 2

CH13 0.22U_0201_6.3V6M

1 2

CH14 0.22U_0201_6.3V6M

1 2

CH15 0.22U_0201_6.3V6M

1 2

CH16 0.22U_0201_6.3V6M

1 2

CH17 0.22U_0201_6.3V6M

1 2

CH18 0.22U_0201_6.3V6M

1 2

CH19 0.22U_0201_6.3V6M

1 2

CH20 0.22U_0201_6.3V6M

1 2

CH21 0.22U_0201_6.3V6M

1 2

CH22 0.22U_0201_6.3V6M

1 2

CH23 0.22U_0201_6.3V6M

1 2

CH24 0.22U_0201_6.3V6M

1 2

CH25 0.22U_0201_6.3V6M

1 2

CH26 0.22U_0201_6.3V6M

1 2

CH27 0.22U_0201_6.3V6M

1 2

CH28 0.22U_0201_6.3V6M

1 2

CH29 0.22U_0201_6.3V6M

1 2

CH30 0.22U_0201_6.3V6M

1 2

CH31 0.22U_0201_6.3V6M

1 2

CH32 0.22U_0201_6.3V6M

1 2

CH33 0.22U_0201_6.3V6M

1 2

CH34 0.22U_0201_6.3V6M

1 2

CH35 0.22U_0201_6.3V6M

1 2

CH36 0.22U_0201_6.3V6M

DMI_CTX_PRX_P0 <19> DMI_CTX_PRX_N0 <19>

DMI_CTX_PRX_P1 <19> DMI_CTX_PRX_N1 <19>

DMI_CTX_PRX_P2 <19> DMI_CTX_PRX_N2 <19>

DMI_CTX_PRX_P3 <19> DMI_CTX_PRX_N3 <19>

EDP_TXP0 <38> EDP_TXN0 <38> EDP_TXP1 <38> EDP_TXN1 <38> EDP_TXN2 <38> EDP_TXP2 <38> EDP_TXN3 <38> EDP_TXP3 <38>

EDP_AUXP <38> EDP_AUXN <38>

1 2

RH20

@

0_0402_5%

1 2

RH30

24.9_0402_1%

1 2

RH145

20_0402_5%

Close to CPU

PEG_HTX_C_GRX_P15 PEG_HTX_C_GRX_N15

PEG_HTX_C_GRX_P14 PEG_HTX_C_GRX_N14

PEG_HTX_C_GRX_P13 PEG_HTX_C_GRX_N13

PEG_HTX_C_GRX_P12 PEG_HTX_C_GRX_N12

PEG_HTX_C_GRX_P11 PEG_HTX_C_GRX_N11

PEG_HTX_C_GRX_P10 PEG_HTX_C_GRX_N10

PEG_HTX_C_GRX_P9 PEG_HTX_C_GRX_N9

PEG_HTX_C_GRX_P8 PEG_HTX_C_GRX_N8

PEG_HTX_C_GRX_P7 PEG_HTX_C_GRX_N7

PEG_HTX_C_GRX_P6 PEG_HTX_C_GRX_N6

PEG_HTX_C_GRX_P5 PEG_HTX_C_GRX_N5

PEG_HTX_C_GRX_P4 PEG_HTX_C_GRX_N4

PEG_HTX_C_GRX_P3 PEG_HTX_C_GRX_N3

PEG_HTX_C_GRX_P2 PEG_HTX_C_GRX_N2

PEG_HTX_C_GRX_P1 PEG_HTX_C_GRX_N1

PEG_HTX_C_GRX_P0 PEG_HTX_C_GRX_N0

BIA_PWM_PCH <16,38>

+VCCIO

AUD_AZA_CPU_SCLK <18> AUD_AZA_CPU_SDO <18> AUD_AZA_CPU_SDI_R <18>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/08/25 2012/07/25

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

PROCESSOR(1/7) DMI,FDI,PEG

Size Document Number Rev

Custom

Date: Sheet of

LA-E992P

1

1.0(A00)

7 77Tuesday, July 25, 2017

5

4

3

2

1

Non-Interleave

DDR_A_D[0..63]<14> DDR_A_MA[0..13]<14> DDR_A_DQS#[0..7]<14> DDR_A_DQS[0..7]<14>

DDR_B_D[0..63]<15> DDR_B_MA[0..13]<15> DDR_B_DQS#[0..7]<15>

D D

DDR_B_DQS[0..7]<15>

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15

DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36

C C

B B

DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47

UH1A

BR6

DDR0_DQ[0]

BT6

DDR0_DQ[1]

BP3

DDR0_DQ[2]

BR3

DDR0_DQ[3]

BN5

DDR0_DQ[4]

BP6

DDR0_DQ[5]

BP2

DDR0_DQ[6]

BN3

DDR0_DQ[7]

BL4

DDR0_DQ[8]

BL5

DDR0_DQ[9]

BL2

DDR0_DQ[10]

BM1

DDR0_DQ[11]

BK4

DDR0_DQ[12]

BK5

DDR0_DQ[13]

BK1

DDR0_DQ[14]

BK2

DDR0_DQ[15]

Interleave / Non-Interleaved

BG4

DDR0_DQ[16]/DDR0_DQ[32]

BG5

DDR0_DQ[17]/DDR0_DQ[33]

BF4

DDR0_DQ[18]/DDR0_DQ[34]

BF5

DDR0_DQ[19]/DDR0_DQ[35]

BG2

DDR0_DQ[20]/DDR0_DQ[36]

BG1

DDR0_DQ[21]/DDR0_DQ[37]

BF1

DDR0_DQ[22]/DDR0_DQ[38]

BF2

DDR0_DQ[23]/DDR0_DQ[39]

BD2

DDR0_DQ[24]/DDR0_DQ[40]

BD1

DDR0_DQ[25]/DDR0_DQ[41]

BC4

DDR0_DQ[26]/DDR0_DQ[42]

BC5

DDR0_DQ[27]/DDR0_DQ[43]

BD5

DDR0_DQ[28]/DDR0_DQ[44]

BD4

DDR0_DQ[29]/DDR0_DQ[45]

BC1

DDR0_DQ[30]/DDR0_DQ[46]

BC2

DDR0_DQ[31]/DDR0_DQ[47]

AB1

DDR0_DQ[32]/DDR1_DQ[0]

AB2

DDR0_DQ[33]/DDR1_DQ[1]

AA4

DDR0_DQ[34]/DDR1_DQ[2]

AA5

DDR0_DQ[35]/DDR1_DQ[3]

AB5

DDR0_DQ[36]/DDR1_DQ[4]

AB4

DDR0_DQ[37]/DDR1_DQ[5]

AA2

DDR0_DQ[38]/DDR1_DQ[6]

AA1

DDR0_DQ[39]/DDR1_DQ[7]

V5

DDR0_DQ[40]/DDR1_DQ[8]

V2

DDR0_DQ[41]/DDR1_DQ[9]

U1

DDR0_DQ[42]/DDR1_DQ[10]

U2

DDR0_DQ[43]/DDR1_DQ[11]

V1

DDR0_DQ[44]/DDR1_DQ[12]

V4

DDR0_DQ[45]/DDR1_DQ[13]

U5

DDR0_DQ[46]/DDR1_DQ[14]

U4

DDR0_DQ[47]/DDR1_DQ[15]

R2

DDR0_DQ[48]/DDR1_DQ[32]

P5

DDR0_DQ[49]/DDR1_DQ[33]

R4

DDR0_DQ[50]/DDR1_DQ[34]

P4

DDR0_DQ[51]/DDR1_DQ[35]

R5

DDR0_DQ[52]/DDR1_DQ[36]

P2

DDR0_DQ[53]/DDR1_DQ[37]

R1

DDR0_DQ[54]/DDR1_DQ[38]

P1

DDR0_DQ[55]/DDR1_DQ[39]

M4

DDR0_DQ[56]/DDR1_DQ[40]

M1

DDR0_DQ[57]/DDR1_DQ[41]

L4

DDR0_DQ[58]/DDR1_DQ[42]

L2

DDR0_DQ[59]/DDR1_DQ[43]

M5

DDR0_DQ[60]/DDR1_DQ[44]

M2

DDR0_DQ[61]/DDR1_DQ[45]

L5

DDR0_DQ[62]/DDR1_DQ[46]

L1

DDR0_DQ[63]/DDR1_DQ[47]

BA2

DDR0_ECC[0]

BA1

DDR0_ECC[1]

AY4

DDR0_ECC[2]

AY5

DDR0_ECC[3]

BA5

DDR0_ECC[4]

BA4

DDR0_ECC[5]

AY1

DDR0_ECC[6]

AY2

DDR0_ECC[7]

SKL-H_BGA1440

@

SKYLAKE_HALO

DDR3L / LPDDR3 / DDR4

DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]

DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]

DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]

DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]

DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]

DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]

DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8]

DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]

DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT#

Interleave / Non-Interleaved

DDR0_DQSN[2]/DDR0_DQSN[4] DDR0_DQSN[3]/DDR0_DQSN[5]

DDR0_DQSP[4]/DDR1_DQSP[0] DDR0_DQSP[5]/DDR1_DQSP[1] DDR0_DQSP[6]/DDR1_DQSP[4] DDR0_DQSP[7]/DDR1_DQSP[5]

DDR0_DQSP[2]/DDR0_DQSP[4]

DDR0_DQSP[3]/DDR0_DQSP[5] DDR0_DQSN[4]/DDR1_DQSN[0] DDR0_DQSN[5]/DDR1_DQSN[1] DDR0_DQSN[6]/DDR1_DQSN[4] DDR0_DQSN[7]/DDR1_DQSN[5]

DDR CH - A

1 OF 14

Rev_1.0

DDR0_CKP[0] DDR0_CKN[0] DDR0_CKN[1] DDR0_CKP[1]

DDR0_CLKP[2] DDR0_CLKN[2] DDR0_CLKP[3] DDR0_CLKN[3]

DDR0_CKE[0] DDR0_CKE[1] DDR0_CKE[2] DDR0_CKE[3]

DDR0_CS#[0]

DDR0_CS#[1]

DDR0_CS#[2]

DDR0_CS#[3]

DDR0_ODT[0] DDR0_ODT[1] DDR0_ODT[2] DDR0_ODT[3]

DDR0_MA[3] DDR0_MA[4]

DDR0_PAR

DDR0_ALERT#

DDR0_DQSN[0] DDR0_DQSN[1]

DDR0_DQSP[0] DDR0_DQSP[1]

DDR0_DQSP[8] DDR0_DQSN[8]

AG1 AG2 AK1 AK2 AL3 AK3 AL2 AL1

AT1 AT2 AT3 AT5

AD5 AE2 AD2 AE5

AD3 AE4 AE1 AD4

AH5 AH1 AU1

AH4 AG4 AD1

AH3 AP4 AN4 AP5 AP2 AP1 AP3 AN1 AN3 AT4 AH2 AN2 AU4 AE3 AU2 AU3

AG3 AU5

BR5 BL3

BG3 BD3 AB3 V3 R3 M3 BP5 BK3 BF3 BC3 AA3 U3 P3 L3

AY3 BA3

DDR_A_CLK0 DDR_A_CLK#0 DDR_A_CLK#1 DDR_A_CLK1

DDR_A_CKE0 DDR_A_CKE1

DDR_A_CS#0 DDR_A_CS#1

DDR_A_ODT0 DDR_A_ODT1

DDR_A_BS0 DDR_A_BS1 DDR_A_BG0

DDR_A_RAS# DDR_A_WE# DDR_A_CAS#

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_BG1 DDR_A_ACT#

DDR_A_PAR DDR_A_ALERT#

DDR_A_DQS#0 DDR_A_DQS#1

DDR_A_DQS#4 DDR_A_DQS#5 DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS4 DDR_B_DQS5 DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS4 DDR_A_DQS5 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#4 DDR_B_DQS#5

DDR_A_CLK0 <14 > DDR_A_CLK#0 <1 4> DDR_A_CLK#1 <1 4> DDR_A_CLK1 <14 >

DDR_A_CKE0 <14> DDR_A_CKE1 <14>

DDR_A_CS#0 <14 > DDR_A_CS#1 <14 >

DDR_A_ODT0 <14> DDR_A_ODT1 <14>

DDR_A_BS0 <14> DDR_A_BS1 <14> DDR_A_BG0 <14>

DDR_A_RAS# <14> DDR_A_WE# <14> DDR_A_CAS# <14>

DDR_A_BG1 <14> DDR_A_ACT# <14>

DDR_A_PAR <14> DDR_A_ALERT# <14>

1 2

RH148 121_0402_1%

1 2

RH149 75_0402_1%

1 2

RH150 100_0402_1%

DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31

DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

DDR_RCOMP0 DDR_RCOMP1 DDR_RCOMP2

UH1B

Interleave / Non-Interleaved

BT11

DDR1_DQ[0]/DDR0_DQ[16]

BR11

DDR1_DQ[1]/DDR0_DQ[17]

BT8

DDR1_DQ[2]/DDR0_DQ[18]

BR8

DDR1_DQ[3]/DDR0_DQ[19]

BP11

DDR1_DQ[4]/DDR0_DQ[20]

BN11

DDR1_DQ[5]/DDR0_DQ[21]

BP8

DDR1_DQ[6]/DDR0_DQ[22]

BN8

DDR1_DQ[7]/DDR0_DQ[23]

BL12

DDR1_DQ[8]/DDR0_DQ[24]

BL11

DDR1_DQ[9]/DDR0_DQ[25]

BL8

DDR1_DQ[10]/DDR0_DQ[26]

BJ8

DDR1_DQ[11]/DDR0_DQ[27]

BJ11

DDR1_DQ[12]/DDR0_DQ[28]

BJ10

DDR1_DQ[13]/DDR0_DQ[29]

BL7

DDR1_DQ[14]/DDR0_DQ[30]

BJ7

DDR1_DQ[15]/DDR0_DQ[31]

BG11

DDR1_DQ[16]/DDR0_DQ[48]

BG10

DDR1_DQ[17]/DDR0_DQ[49]

BG8

DDR1_DQ[18]/DDR0_DQ[50]

BF8

DDR1_DQ[19]/DDR0_DQ[51]

BF11

DDR1_DQ[20]/DDR0_DQ[52]

BF10

DDR1_DQ[21]/DDR0_DQ[53]

BG7

DDR1_DQ[22]/DDR0_DQ[54]

BF7

DDR1_DQ[23]/DDR0_DQ[55]

BB11

DDR1_DQ[24]/DDR0_DQ[56]

BC11

DDR1_DQ[25]/DDR0_DQ[57]

BB8

DDR1_DQ[26]/DDR0_DQ[58]

BC8

DDR1_DQ[27]/DDR0_DQ[59]

BC10

DDR1_DQ[28]/DDR0_DQ[60]

BB10

DDR1_DQ[29]/DDR0_DQ[61]

BC7

DDR1_DQ[30]/DDR0_DQ[62]

BB7

DDR1_DQ[31]/DDR0_DQ[63]

AA11

DDR1_DQ[32]/DDR1_DQ[16]

AA10

DDR1_DQ[33]/DDR1_DQ[17]

AC11

DDR1_DQ[34]/DDR1_DQ[18]

AC10

DDR1_DQ[35]/DDR1_DQ[19]

AA7

DDR1_DQ[36]/DDR1_DQ[20]

AA8

DDR1_DQ[37]/DDR1_DQ[21]

AC8

DDR1_DQ[38]/DDR1_DQ[22]

AC7

DDR1_DQ[39]/DDR1_DQ[23]

W8

DDR1_DQ[40]/DDR1_DQ[24]

W7

DDR1_DQ[41]/DDR1_DQ[25]

V10

DDR1_DQ[42]/DDR1_DQ[26]

V11

DDR1_DQ[43]/DDR1_DQ[27]

W11

DDR1_DQ[44]/DDR1_DQ[28]

W10

DDR1_DQ[45]/DDR1_DQ[29]

V7

DDR1_DQ[46]/DDR1_DQ[30]

V8

DDR1_DQ[47]/DDR1_DQ[31]

R11

DDR1_DQ[48]

P11

DDR1_DQ[49]

P7

DDR1_DQ[50]

R8

DDR1_DQ[51]

R10

DDR1_DQ[52]

P10

DDR1_DQ[53]

R7

DDR1_DQ[54]

P8

DDR1_DQ[55]

L11

DDR1_DQ[56]

M11

DDR1_DQ[57]

L7

DDR1_DQ[58]

M8

DDR1_DQ[59]

L10

DDR1_DQ[60]

M10

DDR1_DQ[61]

M7

DDR1_DQ[62]

L8

DDR1_DQ[63]

AW11

DDR1_ECC[0]

AY11

DDR1_ECC[1]

AY8

DDR1_ECC[2]

AW8

DDR1_ECC[3]

AY10

DDR1_ECC[4]

AW10

DDR1_ECC[5]

AY7

DDR1_ECC[6]

AW7

DDR1_ECC[7]

G1

DDR_RCOMP[0]

H1

DDR_RCOMP[1]

J2

DDR_RCOMP[2]

SKL-H_BGA1440

@

SKYLAKE_HALO

DDR3L / LPDDR3 / DDR4

DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]

DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]

DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]

DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]

DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0] DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]

DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8]

DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]

DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT#

Interleave / Non-Interleaved

DDR1_DQSN[0]/DDR0_DQSN[2] DDR1_DQSN[1]/DDR0_DQSN[3] DDR1_DQSN[2]/DDR0_DQSN[6] DDR1_DQSN[3]/DDR0_DQSN[7] DDR1_DQSN[4]/DDR1_DQSN[2] DDR1_DQSN[5]/DDR1_DQSN[3]

DDR1_DQSP[0]/DDR0_DQSP[2] DDR1_DQSP[1]/DDR0_DQSP[3] DDR1_DQSP[2]/DDR0_DQSP[6] DDR1_DQSP[3]/DDR0_DQSP[7] DDR1_DQSP[4]/DDR1_DQSP[2] DDR1_DQSP[5]/DDR1_DQSP[3]

DDR CH - B

2 OF 14

DDR0_VREF_DQ DDR1_VREF_DQ

Rev_1.0

DDR1_CKP[0] DDR1_CKN[0] DDR1_CKN[1]

DDR1_CKP[1] DDR1_CLKP[2] DDR1_CLKN[2] DDR1_CLKP[3] DDR1_CLKN[3]

DDR1_CKE[0]

DDR1_CKE[1]

DDR1_CKE[2]

DDR1_CKE[3]

DDR1_CS#[0] DDR1_CS#[1] DDR1_CS#[2] DDR1_CS#[3]

DDR1_ODT[0]

DDR1_ODT[1]

DDR1_ODT[2]

DDR1_ODT[3]

DDR1_MA[3] DDR1_MA[4]

DDR1_PAR

DDR1_ALERT#

DDR1_DQSN[6] DDR1_DQSN[7]

DDR1_DQSP[6] DDR1_DQSP[7]

DDR1_DQSP[8] DDR1_DQSN[8]

DDR_VREF_CA

AM9 AN9 AM8 AM7 AM11 AM10 AJ10 AJ11

AT8 AT10 AT7 AT11

AF11 AE7 AF10 AE10

AF7 AE8 AE9 AE11

AH10 AH11 AF8

AH8 AH9 AR9

AJ9 AK6 AK5 AL5 AL6 AM6 AN7 AN10 AN8 AR11 AH7 AN11 AR10 AF9 AR7 AT9

AJ7 AR8

BP9 BL9 BG9 BC9 AC9 W9 R9 M9

BR9 BJ9 BF9 BB9 AA9 V9 P9 L9

AW9 AY9

BN13 BP13 BR13

DDR_B_CLK0 DDR_B_CLK#0 DDR_B_CLK#1 DDR_B_CLK1

DDR_B_CKE0 DDR_B_CKE1

DDR_B_CS#0 DDR_B_CS#1

DDR_B_ODT0 DDR_B_ODT1

DDR_B_RAS# DDR_B_WE# DDR_B_CAS#

DDR_B_BS0 DDR_B_BS1 DDR_B_BG0

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_BG1 DDR_B_ACT#

DDR_B_PAR DDR_B_ALERT#

DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#6 DDR_A_DQS#7 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#6 DDR_B_DQS#7

DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS6 DDR_A_DQS7 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS6 DDR_B_DQS7

DDR_B_CLK0 <15 > DDR_B_CLK#0 <1 5> DDR_B_CLK#1 <1 5> DDR_B_CLK1 <15 >

DDR_B_CKE0 < 15> DDR_B_CKE1 < 15>

DDR_B_CS#0 <15 > DDR_B_CS#1 <15 >

DDR_B_ODT0 <15> DDR_B_ODT1 <15>

DDR_B_RAS# < 15> DDR_B_WE# <15> DDR_B_CAS# < 15>

DDR_B_BS0 <15> DDR_B_BS1 <15> DDR_B_BG0 <15>

DDR_B_BG1 <15> DDR_B_ACT# <15>

DDR_B_PAR <1 5> DDR_B_ALERT# <15>

+V_DDR_REFA_R

+V_DDR_REFB_R

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/08/25 2012/07/25

Compal Secret Data

Deciphered Date

Title

PROCESSOR(3/7) DDRIII

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet

LA-E992P

8 77Tuesday, July 25, 2017

1

8 77Tuesday, July 25, 2017

1.0(A00)

of

5

4

3

2

1

+VCCSTG

CFG Straps for Processor

+VCCST

Stall reset sequence after CPU PLL lock until de-asserted

D D

CFG0

1 = (Default) Normal Operation; No stall.

*

0 = Stall.

RH183

1 2

@

1K_0402_5%

CFG0

RH165

RH163

RH156

RH164

RH151

RH152

RH144

1 2

1K_0402_5%

1 2

1K_0402_5%

1 2

51_0402_5%

1 2

1K_0402_5%

1 2

100_0402_5%

1 2

56.2_0402_1%

1 2

49.9_0402_1%

PCI EXPRESS STATIC LANE REVERSAL FOR ALL PEG PORTS

CFG2

C C

1: Normal Operation; Lane # definition matches socket pin map definition

0:Lane Reversed

*

RH184

1 2

1K_0402_5%

CFG2

Display Port Presence Strap

CFG4

PCIE Port Bifurcation Straps

B B

CFG[6:5]

1 : Disabled; No Physical Display Port attached to Embedded Display Port

0 : Enabled; An external Display Port device is connected to the Embedded Display Port

*

RH185

RH186

RH187

1 2

1K_0402_5%

1 2

@

1K_0402_5%

1 2

@

1K_0402_5%

CFG4

11: (Default) x16 - Device 1 functions 1 and 2 disabled

*

10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled

01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)

00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

CFG5

CFG6

SM_PG_CTRL<62>

If change to x8, need cheange setting.

PEG DEFER TRAINING

CFG7

A A

1: (Default) PEG Train immediately following xxRESETB de assertion

*

0: PEG Wait for BIOS for training

RH188

1 2

1K_0402_5%

5

@

CFG7

4

@

VR_SVID_ALERT#<71> VR_SVID_CLK<71> VR_SVID_DATA<71> H_PROCHOT#<36,59,60,71>

H_VCCST_PWRGD<6,18>

H_CPUPWRGD<18> PLTRST_CPU#< 6,16> H_PM_SYNC_R<16>

H_PM_DOWN<16>

PECI_EC<16,36>

H_THERMTRIP#_R<16>

PROC_DETECT#<16>

0.1U_0402_10V7K

PCH_TRIGGER<22>

CPU_TRIGGER<22>

H_PROCHOT#

H_THERMTRIP#_R

XDP_PREQ#

H_VCCST_PWRGD

VR_SVID_DATA

VR_SVID_ALERT#

H_CATERR#

VR_SVID_ALERT# VR_SVID_CLK VR_SVID_DATA

H_VCCST_PWRGD

H_PM_DOWN PECI_EC

PROC_DETECT#

DVT2.0 Change RH190 to 0ohm 0402 short-pad footprint.

PCH_CPU_BCLK_P<17> PCH_CPU_BCLK_N<17>

PCH_CPU_PCIBCLK_P<17> PCH_CPU_PCIBCLK_N<17>

CPU_24MHZ_P<17> CPU_24MHZ_N<17>

RH153 220_0402_5%

RH158 499_0402_1%

RH154 60.4_0402_1%

RH155 20_0402_5% RH190 0_0402_5%@

RH89 0_0402_5%@

+1.2V_DDR

@

CH197

1

2

SM_PG_CTRL

RH93

220K_0402_5%

+3VS

12

UC1

5

VCC

4

Y

74AUP1G07SE-7_SOT353

SA00007WE00

Reserve for ESD

H_VCCST_PWRGD

H_PROCHOT#_R

1 2

CH210

100P_0402_50V8J@ESD@

1 2

CH211

100P_0402_50V8J

PCH_TRIGGER PCH_TRIGGER_R CPU_TRIGGER CPU_TRIGGER_R

RH167 30_0402_5% RH192 30_0402_5%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

1 2

1 2 1 2

1 2

NC

GND

1 2 1 2

D35 C36

D31

BH31 BH32 BH29 BR30

BT13

H13

BT31 BP35 BM34 BP31

BT34

BR33

BN1

BM30

BR1 BT2

BN35

H24

BN33

BL34

N29

R14 AE29 AA14

H23

C30

BR35 BR31 BH30

B31 A32

E31

J31

D1 E1 E3 E2

J24

A36 A37

J23

F30 E30

B30

G3 J3

UH1E

BCLKP BCLKN

PCI_BCLKP PCI_BCLKN

CLK24P CLK24N

VIDALERT# VIDSCK VIDSOUT PROCHOT#

DDR_VTT_CNTL

VCCST_PWRGD

PROCPWRGD RESET# PM_SYNC PM_DOWN PECI THERMTRIP#

SKTOCC# PROC_SELECT#

CATERR#

SKL-H_BGA1440

@

UH1K

RSVD_TP RSVD_TP RSVD_TP RSVD_TP

RSVD_TP RSVD_TP

RSVD

RSVD RSVD RSVD RSVD

RSVD RSVD

PROC_TRIGIN PROC_TRIGOUT

RSVD RSVD

RSVD RSVD RSVD

SKL-H_BGA1440

@

PCH_CPU_BCLK_P PCH_CPU_BCLK_N

PCH_CPU_PCIBCLK_P PCH_CPU_PCIBCLK_N

CPU_24MHZ_P CPU_24MHZ_N

VR_SVID_ALERT#_R

H_PROCHOT#_RH_PROCHOT#

DDR_VTT_PG_CTRL

VCCST_PWRGD_CPU

H_CPUPWRGD PLTRST_CPU# H_PM_SYNC_R H_PM_DOWN_R PECI_EC_R H_THERMTRIP#_R

H_CATERR#

1

DDR_VTT_PG_CTRL

2

A

3

Compal Secret Data

2011/08/25 2012/07/25

Compal Secret Data

Deciphered Date

SKYLAKE_HALO

2

5 OF 14

SKYLAKE_HALO

11 OF 14

Rev_1.0

CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8]

CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15]

CFG[17] CFG[16] CFG[19] CFG[18]

BPM#[0] BPM#[1] BPM#[2] BPM#[3]

PROC_TDO

PROC_TDI PROC_TMS PROC_TCK

PROC_TRST#

PROC_PREQ#

PROC_PRDY#

CFG_RCOMP

CFG[0..19] <6>

BN25

CFG0

BN27

CFG1

BN26

CFG2

BN28

CFG3

BR20

CFG4

BM20

CFG5

BT20

CFG6

BP20

CFG7

BR23

CFG8

BR22

CFG9

BT23

CFG10

BT22

CFG11

BM19

CFG12

BR19

CFG13

BP19

CFG14

BT19

CFG15

BN23

CFG17

BP23

CFG16

BP22

CFG19

BN22

CFG18

XDP_BPM#0

BR27

XDP_BPM#1

BT27 BM31 BT30

CPU_XDP_TDO

BT28

CPU_XDP_TDI

BL32

CPU_XDP_TMS

BP28

CPU_XDP_TCK

BR28

CPU_XDP_TRST#

BP30

XDP_PREQ#

BL30

XDP_PRDY#

BP27

CFG_RCOMP

BT25

Rev_1.0

RSVD_TP RSVD_TP

RSVD RSVD

VSS

RSVD_TP RSVD_TP

RSVD RSVD

VSS

RSVD_TP RSVD_TP

RSVD RSVD RSVD

NCTF NCTF NCTF NCTF NCTF NCTF

Compal Electronics, Inc.

Title

PROCESSOR(4/7) RSVD,CFG

Size Document Number Rev

Custom

Date: Sheet of

Date: Sheet

BM33 BL33

BJ14 BJ13

BK28 BJ28

BJ18

BJ16 BK16

BK24 BJ24

BK21 BJ21

BT17 BR17

BK18

BJ34 BJ33

G13 AJ8 BL31

B2 B38 BP1 BR2 C1 C38

XDP_BPM#0 <6> XDP_BPM#1 <6>

CPU_XDP_TDO <6 > CPU_XDP_TDI <6> CPU_XDP_TMS <6> CPU_XDP_TCK <6,18 >

CPU_XDP_TRST# <6,22> XDP_PREQ# <6,22> XDP_PRDY# <6,22>

12

RH59

49.9_0402_1%

LA-E992P

of

9 77Tuesday, July 25, 2017

1

9 77Tuesday, July 25, 2017

1.0(A00)

5

4

3

2

1

+VCC_CORE +VCC_CORE

D D

C C

B B

AA13 AA31 AA32 AA33 AA34 AA35 AA36 AA37 AA38 AB29 AB30 AB31 AB32 AB35 AB36 AB37 AB38 AC13 AC14 AC29 AC30 AC31 AC32 AC33 AC34 AC35 AC36 AD13 AD14 AD31 AD32 AD33 AD34 AD35 AD36 AD37 AD38 AE13 AE14 AE30 AE31 AE32 AE35 AE36 AE37 AE38

AF35 AF36 AF37 AF38

K13 K14

N13 N14 N30 N31 N32 N35 N36 N37 N38 P13

L13

SKYLAKE_HALO

UH1G

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

SKL-H_BGA1440

@

7 OF 14

Rev_1.0

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

VCC_SENSE

VSS_SENSE

V32 V33 V34 V35 V36 V37 V38 W13 W14 W29 W30 W31 W32 W35 W36 W37 W38 Y29 Y30 Y31 Y32 Y33 Y34 Y35 Y36 L14 P29 P30 P31 P32 P33 P34 P35 P36 R13 R31 R32 R33 R34 R35 R36 R37 R38 T29 T30 T31 T32 T35 T36 T37 T38 U29 U30 U31 U32 U33 U34 U35 U36 V13 V14 V31 P14

AG37 AG38

+VCC_CORE

12

RH197 100_0402_1%

1 2

RH198 0_0402_5%@

1 2

RH28 0_0402_5%@

DVT2.0 Change RH198, RH28 to 0ohm 0402 short-pad footprint.

RH29 100_0402_1%

VCCSENSE VSSSENSE

VCCSENSE <71> VSSSENSE <71>

1 2

RH166 49.9_0402_1%@

1 2

RH57 49.9_0402_1%@

1 2

RH58 49.9_0402_1%@

BJ17 BJ19

BJ20 BK17 BK19 BK20 BL16 BL17 BL18 BL19 BL20 BL21

BM17 BN17

BJ23

BJ26

BJ27 BK23 BK26 BK27 BL23 BL24 BL25 BL26 BL27 BL28

BM24

BL15

BM16

BL22

BM22

BP15

BR15

BT15

BP16

BR16

BT16

BN15 BM15

BP17

BN16

BM14

BL14

BJ35

BJ36

AT13

AW13

AU13

AY13

BT29

BR25

BP25

UH1J

VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC

RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD

VCCOPC_SENSE VSSOPC_SENSE

RSVD RSVD

VCCEOPIO VCCEOPIO VCCEOPIO

RSVD RSVD RSVD

VCCEOPIO_SENSE VSSEOPIO_SENSE

RSVD RSVD

VCC_OPC_1P8 VCC_OPC_1P8

RSVD RSVD

ZVM# MSM#

ZVM2# MSM2#

OPC_RCOMP OPCE_RCOMP OPCE_RCOMP2

SKL-H_BGA1440

@

SKYLAKE_HALO

10 OF 14

Rev_1.0

A A

Security Classification

2011/08/25 2012/07/25

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/08/25 2012/07/25

3

Compal Secret Data

Deciphered Date

Title

PROCESSOR(5/7) PWR,BYPASS

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet

LA-E992P

1

10 77Tuesday, July 25, 2017

1.0(A00)

of

5

D D

4

3

2

1

Rev_1.0

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VCCST

+1.2V_DDR

AA6 AE12 AF5 AF6 AG5 AG9 AJ12 AL11 AP6 AP7 AR12 AR6 AT12 AW6 AY6 J5 J6 K12 K6 L12 L6 R6 T6 W6

Y12

BH13 G11

H30

H29

G30

H28 J28

M38 M37

H14 J14

+1.2V_DDR

10U_0402_6.3V6M

1

CH124

Close to Ball Y12

2

+1.2V_DDR+1.2V_VCCPLL_OC

1 2

RH107 0_0402_5%@

+VCCST

+VCCSTG

+VCCST

+VCCSA

1 2

RH201 100_0402_1%

1 2

RH202 0_0402_5%@

1 2

RH31 0_0402_5%@

1 2

RH41 100_0402_1%

DVT2.0 Change RH202, RH31 to 0ohm 0402 short-pad footprint.

1 2

RH515 100_0402_1%

1 2

RH514 0_0402_5%@

1 2

RH513 0_0402_5%@

1 2

RH516 100_0402_1%

DVT2.0 Change RH514, RH513 to 0ohm 0402 short-pad footprint.

VCCSA_SENSE VSSSA_SENSE

+VCCIO

VCCIO_SENSE VSSIO_SENSE

VCCSA_SENSE <71> VSSSA_SENSE <71>

VCCIO_SENSE <74> VSSIO_SENSE <74>

CH102

10U_0603_6.3V6M

+1.2V_DDR

CH129

22U_0603_6.3V6M

+1.2V_DDR

CH118

10U_0603_6.3V6M

1

2

1

2

1

2

CH103

CH130

CH121

+VCCSTG +VCCSA

CH104

1

10U_0603_6.3V6M

2

CH131

1

22U_0603_6.3V6M

2

1

10U_0603_6.3V6M

2

CH106

1

2

1

2

CH132

CH120

1U_0402_6.3V6K

1

22U_0603_6.3V6M

2

CH119

1

10U_0603_6.3V6M

2

10U_0603_6.3V6M

22U_0603_6.3V6M

+VCCST+VCCIO

CH204

CH110

1

2

1

1U_0402_6.3V6K

2

+VCCSA +VCCSA

CH133

1

1U_0402_6.3V6K

2

CH122

1

10U_0603_6.3V6M

2

CH134

CH123

1

2

CH111

1

1U_0402_6.3V6K

10U_0603_6.3V6M

2

CH135

1

1U_0402_6.3V6K

2

CH125

1

10U_0603_6.3V6M

2

1

2

1

2

CH112

CH126

CH113

1

10U_0603_6.3V6M

2

CH136

47U_0603_6.3V6M

CH127

1

10U_0603_6.3V6M

2

1

2

1

2

1

2

CH114

CH128

CH115

CH116

CH117

1

10U_0603_6.3V6M

2

1

10U_0603_6.3V6M

2

1

10U_0603_6.3V6M

2

1

10U_0603_6.3V6M

2

+VCCSA

C C

+VCCIO

B B

K29 K30 K31 K32 K33 K34 K35

M29 M30 M31 M32 M33 M34 M35 M36

AG12

G15 G17 G19 G21 H15 H16 H17 H19 H20 H21 H26 H27

J30

L31 L32 L35 L36 L37 L38

J15 J16 J17 J19 J20 J21 J26 J27

UH1I

VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA

VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO

SKL-H_BGA1440

@

SKYLAKE_HALO

9 OF 14

VDDQC

VCCPLL_OC VCCPLL_OC

VCCSTG

VCCPLL VCCPLL

VCCSA_SENSE

VSSSA_SENSE

VCCIO_SENSE

VSSIO_SENSE

A A

Security Classification

2011/08/25 2012/07/25

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/08/25 2012/07/25

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

PROCESSOR(6/7) PWR

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet

LA-E992P

1

11 77Tuesday, July 25, 2017

1.0(A00)

of

5

4

3

2

1

+VCCGT

SKYLAKE_HALO

D D

C C

B B

A A

BG34 BG35 BG36 BH33 BH34 BH35 BH36 BH37 BH38

BJ37 BJ38 BL36

BL37 BM36 BM37

BN36 BN37 BN38 BP37 BP38 BR37 BT37 BE38 BF13 BF14 BF29 BF30 BF31 BF32 BF35 BF36 BF37 BF38 BG29 BG30 BG31 BG32 BG33 BC36 BC37 BC38 BD13 BD14 BD29 BD30 BD31 BD32 BD33 BD34 BD35 BD36 BE31 BE32 BE37

UH1H

VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT

SKL-H_BGA1440

@

8 OF 14

Rev_1.0

VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT

+VCCGT +VCCGT

AV29 AV30 AV31 AV32 AV33 AV34 AV35 AV36 AW14 AW31 AW32 AW33 AW34 AW35 AW36 AW37 AW38 AY29 AY30 AY31 AY32 AY35 AY36 AY37 AY38 BA13 BA14 BA29 BA30 BA31 BA32 BA33 BA34 BA35 BA36 BB13 BB14 BB31 BB32 BB33 BB34 BB35 BB36 BB37 BB38 BC29 BC30 BC31 BC32 BC35 BE33 BE34 BE35 BE36

AJ29 AJ30 AJ31 AJ32 AJ33 AJ34 AJ35

AJ36 AK31 AK32 AK33 AK34 AK35 AK36 AK37 AK38

AL13

AL29

AL30

AL31

AL32

AL35

AL36

AL37

AL38 AM13 AM14 AM29 AM30 AM31 AM32 AM33 AM34 AM35 AM36 AN13 AN14 AN31 AN32 AN33 AN34 AN35 AN36 AN37 AN38 AP13 AP14 AP29 AP30 AP31 AP32 AP35 AP36 AP37 AP38 AR29 AR30 AR31 AR32 AR33 AR34 AR35 AR36 AT14 AT31 AT32 AT33 AT34 AT35 AT36 AT37 AT38 AU14 AU29 AU30 AU31 AU32 AU35 AU36 AU37 AU38

UH1N

VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT

SKL-H_BGA1440

@

SKYLAKE_HALO

14 OF 14

Rev_1.0

VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX

VCCGT_SENSE

VSSGTX_SENSE

VSSGT_SENSE

VCCGTX_SENSE

AF29 AF30 AF31 AF32 AF33 AF34 AG13 AG14 AG31 AG32 AG33 AG34 AG35 AG36 AH13 AH14 AH29 AH30 AH31 AH32 AJ13 AJ14

AH38 AH35 AH37 AH36

+VCCGT

12

RH203 100_0402_1%

1 2

RH204 0_0402_5%@

RH32

1 2

RH33 100_0402_1%

0_0402_5%@

DVT2.0 Change RH204, RH32 to 0ohm 0402 short-pad footprint.

VCCGT_SENSE <71>

VSSGT_SENSE <71>

Security Classification

2011/08/25 2012/07/25

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/08/25 2012/07/25

3

Compal Secret Data

Deciphered Date

Title

PROCESSOR(2/7) PM,XDP,CLK

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet

LA-E992P

1

12 77Tuesday, July 25, 2017

1.0(A00)

of

5

4

3

2

1

SKYLAKE_HALO

UH1F

Y38

VSS

Y37

VSS

Y14

VSS

Y13

VSS

Y11

VSS

D D

C C

B B

A A

Y10

Y9 Y8

Y7 W34 W33 W12

W5 W4 W3 W2 W1 V30 V29 V12

V6

U38 U37

U6 T34 T33 T14 T13 T12 T11 T10

T9 T8 T7 T5 T4 T3 T2

T1 R30 R29 R12

P38 P37 P12

P6 N34 N33 N12 N11 N10

N9 N8 N7 N6 N5 N4 N3 N2

N1 M14 M13 M12

M6

L34 L33 L30 L29 K38 K11 K10

K9 K8 K7 K5 K4 K3 K2

SKL-H_BGA1440

@

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

6 OF 14

Rev_1.0

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

NCTFVSS

K1 J36 J33 J32 J25 J22 J18 J10 J7 J4 H35 H32 H25 H22 H18 H12 H11 G28 G26 G24 G23 G22 G20 G18 G16 G14 G12 G10 G9 G8 G6 G5 G4 F36 F31 F29 F27 F25 F23 F21 F19 F17 F15 F13 F11 F9 F8 F5 F4 F3 F2 E38 E35 E34 E9 E4 D33 D30 D28 D26 D24 D22 D20 D18 D16 D14 D12 D10 D9 D6 D3 C37 C31 C29 C27

D38

C17 C13

BT32 BT26 BT24 BT21 BT18 BT14 BT12

BT9

BT5 BR36 BR34 BR29 BR26 BR24 BR21 BR18 BR14 BR12

BR7 BP34 BP33 BP29 BP26 BP24 BP21 BP18 BP14 BP12

BP7 BN34 BN31 BN30 BN29 BN24 BN21 BN20 BN19 BN18 BN14 BN12

BN9

BN7

BN4

BN2

BM38 BM35 BM28 BM27 BM26 BM23 BM21 BM13 BM12

BM9 BM6

BM2 BL29 BK29 BK15 BK14 BJ32 BJ31 BJ25 BJ22

BH14 BH12

BH9

BH8

BH5

BH4

BH1

BG38 BG13 BG12

BF33 BF12 BE29

BE6

BD9

BC34 BC12

BB12

C9

SKL-H_BGA1440

@

UH1L

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

SKYLAKE_HALO

12 OF 14

Rev_1.0

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

NCTFVSS NCTFVSS NCTFVSS NCTFVSS NCTFVSS NCTFVSS

C25 C23 C21 C19 C15 C11 C8 C5 BM29 BM25 BM18 BM11 BM8 BM7 BM5 BM3 BL38 BL35 BL13 BL6 BK25 BK22 BK13 BK6 BJ30 BJ29 BJ15 BJ12 BH11 BH10 BH7 BH6 BH3 BH2 BG37 BG14 BG6 BF34 BF6 BE30 BE5 BE4 BE3 BE2 BE1 BD38 BD37 BD12 BD11 BD10 BD8 BD7 BD6 BC33 BC14 BC13 BC6 BB30 BB29 BB6 BB5

C2 BT36 BT35 BT4 BT3 BR38

BB4 BB3 BB2

BB1 BA38 BA37 BA12 BA11 BA10

BA9

BA8

BA7

BA6

AY34 AY33 AY14 AY12

AW30 AW29 AW12

AW5 AW4 AW3 AW2

AW1 AV38 AV37 AU34 AU33 AU12 AU11 AU10

AU9 AU8 AU7

AU6 AT30 AT29

AT6 AR38 AR37 AR14 AR13

AR5 AR4 AR3 AR2

AR1 AP34 AP33 AP12 AP11 AP10

AP9

AP8 AN30 AN29 AN12

AN6

AN5 AM38 AM37 AM12

AM5

AM4

AM3

AM2

AM1

AL34 AL33 AL14 AL12 AL10

AL9 AL8 AL7 AL4

B9

SKL-H_BGA1440

@

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

UH1M

SKYLAKE_HALO

13 OF 14

Rev_1.0

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

NCTFVSS NCTFVSS NCTFVSS NCTFVSS NCTFVSS

AK30 AK29 AK4 AJ38 AJ37 AJ6 AJ5 AJ4 AJ3 AJ2 AJ1 AH34 AH33 AH12 AH6 AG30 AG29 AG11 AG10 AG8 AG7 AG6 AF14 AF13 AF12 AF4 AF3 AF2 AF1 AE34 AE33 AE6 AD30 AD29 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AC38 AC37 AC12 AC6 AC5 AC4 AC3 AC2 AC1 AB34 AB33 AB6 AA30 AA29 AA12 A30 A28 A26 A24 A22 A20 A18 A16 A14 A12 A10 A9 A6

B37 B3 A34 A4 A3

Security Classification

2011/08/25 2012/07/25

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/08/25 2012/07/25

3

Compal Secret Data

Deciphered Date

Title

PROCESSOR(7/7) VSS

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

LA-E992P

13 77Tuesday, July 25, 2017

1

1.0(A00)

5

DDR_A_D[0..63]<8> DDR_A_MA[0..13]<8> DDR_A_DQS#[0..7]<8> DDR_A_DQS[0..7]<8>

Layout Note: Place near JDIMM1.257,259

D D

+2.5V_MEM +3VS+0.6VS

CD10

CD9

1

10U_0603_6.3V6M

2

Layout Note: Place near JDIMM1

CD4

CD3

1

10U_0603_6.3V6M

2

1

1U_0402_6.3V6K

2

Layout Note: Place near JDIMM1.258

CD14

CD13

CD12

1

1U_0402_6.3V6K

2

1

10U_0603_6.3V6M

2

+1.2V_DDR

CD75

CD1

CD2

1

1U_0402_6.3V6K

C C

2

CD74

CD77

1

2

1

1U_0402_6.3V6K

2

CD79

CD76

1

1U_0402_6.3V6K

2

CD78

1

2

1

1U_0402_6.3V6K

2

+1.2V_DDR

CD6

CD5

CD7

1

10U_0603_6.3V6M

2

CD70

CD8

1

10U_0603_6.3V6M

2

CD71

1

10U_0603_6.3V6M

2

CD73

CD72

1

10U_0603_6.3V6M

2

DVT1.0 Remove CD11

2

+1.2V_DDR

B B

A A

DVT2.0 Change RD31 to 0ohm 0402 short-pad footprint.

DDR4_DRAMRST#<15> H_DRAMRST# <18>

RH45

1 2

2_0402_1%

+1.2V_DDR

12

+V_DDR_REFA_R

20mil

1

CH101

0.022U_0402_16V7K

2

12

RH211

24.9_0402_1%

RH206 1K_0402_1%

+V_DDR_REFA

RH209 1K_0402_1%

1

@ESD@

CD97

.1U_0402_16V7K

2

RD31

1 2

@

0_0402_5%

12

RD35 470_0402_1%

H_DRAMRST#DDR4_DRAMRST#

1

@ESD@

CD69

.1U_0402_16V7K

2

DIMM_CHA_SA2

DIMM_CHA_SA1

DIMM_CHA_SA0

4

Layout Note: Place near JDIMM1.255

CD15

1

10U_0603_6.3V6M

2

CD17

CD16

1

2.2U_0402_6.3V6M

0.1U_0402_10V6K

2

+3VS

+2.5V_MEM

3

+1.2V_DDR

JDIMM1

1

VSS1

3

DQ5

5

DDR_A_D0

DDR_A_DQS#0 DDR_A_DQS0

DDR_A_D7

DDR_A_D3

DDR_A_D13

DDR_A_D12

DDR_A_D15 DDR_A_D10

DDR_A_D14 DDR_A_D11

DDR_A_D37

DDR_A_DQS#4 DDR_A_DQS4

DDR_A_D38

DDR_A_D34

DDR_A_D45

DDR_A_D44

DDR_A_D46

DDR_A_CKE0<8>

DDR_A_BG1<8> DDR_A_BG0<8>

DDR_A_CLK0<8> DDR_A_CLK#0<8>

DDR_A_PAR<8> DDR_A_BS1<8>

DDR_A_CS#0<8> DDR_A_WE#<8>

DDR_A_ODT0<8> DDR_A_CS#1<8>

DDR_A_ODT1<8>

DDR_A_CKE0

DDR_A_BG1 DDR_A_BG0

DDR_A_MA12 DDR_A_MA9

DDR_A_MA8 DDR_A_MA6

DDR_A_MA3 DDR_A_MA1

DDR_A_CLK0 DDR_A_CLK#0

DDR_A_PAR DDR_A_BS1

DDR_A_CS#0 DDR_A_WE#

DDR_A_ODT0 DDR_A_CS#1

DDR_A_ODT1

DDR_A_D20

DDR_A_D21

DDR_A_DQS#2 DDR_A_DQS2

DDR_A_D18

DDR_A_D19

DDR_A_D25

DDR_A_D24

+1.2V_DDR

DDR_A_D29

DDR_A_D49

DDR_A_D48

DDR_A_DQS#6 DDR_A_DQS6

DDR_A_D53

DDR_A_D51

DDR_A_D60

DDR_A_D57

+1.2V_DDR

DDR_A_D56

DDR_A_D61 DDR_A_D58

PCH_SMBCLK<6,15,18,29,35>

PCH_SMBCLK

VSS3

7

DQ1

9

VSS5

11

DQS0_c

13

DQS0_t

15

VSS8

17

DQ7

19

VSS10

21

DQ3

23

VSS12

25

DQ13

27

VSS14

29

DQ9

31

VSS16

33

DM1_n/DBI_n

35

VSS17

37

DQ15

39

VSS19

41

DQ10

43

VSS21

45

DQ21

47

VSS23

49

DQ17

51

VSS25

53

DQS2_c

55

DQS2_t

57

VSS28

59

DQ23

61

VSS30

63

DQ19

65

VSS32

67

DQ29

69

VSS34

71

DQ25

73

VSS36

75

DM3_n/DBI3_n

77

VSS37

79

DQ30

81

VSS39

83

DQ26

85

VSS41

87

CB5/NC

89

VSS43

91

CB1/NC

93

VSS45

95

DQS8_c

97

DQS8_t

99

VSS48

101

CB2/NC

103

VSS50

105

CB3/NC

107

VSS52

109

CKE0

111

VDD1

113

BG1

115

BG0

117

VDD3

119

A12

121

A9

123

VDD5

125

A8

127

A6

129

VDD7

131

A3

133

A1

135

VDD9

137

CK0_t

139

CK0_c

141

VDD11

143

PARITY

145

BA1

147

VDD13

149

CS0_n

151

WE_n/A14

153

VDD15

155

ODT0

157

CS1_n

159

VDD17

161

ODT1

163

VDD19

165

C1, CS3_n,NC

167

VSS53

169

DQ37

171

VSS55

173

DQ33

175

VSS57

177

DQS4_c

179

DQS4_t

181

VSS60

183

DQ38

185

VSS62

187

DQ34

189

VSS64

191

DQ44

193

VSS66

195

DQ40

197

VSS68

199

DM5_n/DBI5_n

201

VSS69

203

DQ46

205

VSS71

207

DQ42

209

VSS73

211

DQ52

213

VSS75

215

DQ49

217

VSS77

219

DQS6_c

221

DQS6_t

223

VSS80

225

DQ55

227

VSS82

229

DQ51

231

VSS84

233

DQ61

235

VSS86

237

DQ56

239

VSS88

241

DM7_n/DBI7_n

243

VSS89

245

DQ62

247

VSS91

249

DQ58

251

VSS93

253

SCL

255

VDDSPD

257

VPP1

259

VPP2

261

GND1

DEREN_40-42271-26001RHF CONN@

SP07001CW00

VSS2

VSS4

VSS6

DM0_n/DBI0_n

VSS7

VSS9

VSS11

DQ12

VSS13

VSS15

DQS1_c

DQS1_t

VSS18

DQ14

VSS20

DQ11

VSS22

DQ20

VSS24

DQ16

VSS26

DM2_n/DBI2_n

VSS27

DQ22

VSS29

DQ18

VSS31

DQ28

VSS33

DQ24

VSS35

DQS3_c

DQS3_t

VSS38

DQ31

VSS40

DQ27

VSS42

CB4/NC

VSS44

CB0/NC

VSS46

DM8_n/DBI_n/NC

VSS47

CB6/NC

VSS49

CB7/NC

VSS51

RESET_n

CKE1 VDD2

ACT_n

ALERT_n

VDD4

VDD6

VDD8

EVENT_n/NF

VDD10

CK1_t/NF

CK1_c/NF

VDD12

A10/AP

VDD14

RAS_n/A16

VDD16

CAS_n/A15

VDD18

C0/CS2_n/NC

VREFCA

VSS54

DQ36

VSS56

DQ32

VSS58

DM4_n/DBI4_n

VSS59

DQ39

VSS61

DQ35

VSS63

DQ45

VSS65

DQ41

VSS67

DQS5_c

DQS5_t

VSS70

DQ47

VSS72

DQ43

VSS74

DQ53

VSS76

DQ48

VSS78

DM6_n/DBI6_n

VSS79

DQ54

VSS81

DQ50

VSS83

DQ60

VSS85

DQ57

VSS87

DQS7_c

DQS7_t

VSS90

DQ63

VSS92

DQ59

VSS94

GND2

2

1

+1.2V_DDR

2

DDR_A_D1DDR_A_D4

4

DQ4

6

DDR_A_D5

8

DQ0

10 12 14

DDR_A_D6

16

DQ6

18

DDR_A_D2

20

DQ2

22

DDR_A_D9

24 26

DDR_A_D8

28

DQ8

30

DDR_A_DQS#1

32

DDR_A_DQS1

34 36 38 40 42 44

DDR_A_D32

46 48

DDR_A_D33DDR_A_D36

50 52 54 56

DDR_A_D35

58 60

DDR_A_D39

62 64

DDR_A_D40

66 68

DDR_A_D41

70 72

DDR_A_DQS#5

74

DDR_A_DQS5

76 78

DDR_A_D42DDR_A_D43

80 82

DDR_A_D47

84 86 88 90 92 94 96 98 100 102 104 106

DDR4_DRAMRST#

108

DDR_A_CKE1

110 112

DDR_A_ACT#

114

DDR_A_ALERT#

116 118

DDR_A_MA11

120

A11

DDR_A_MA7

122

A7

124

DDR_A_MA5

126

A5

DDR_A_MA4

128

A4

130

DDR_A_MA2

132

A2

134 136

DDR_A_CLK1

138

DDR_A_CLK#1

140 142

DDR_A_MA0

144

A0

DDR_A_MA10

146 148

DDR_A_BS0

150

BA0

DDR_A_RAS#

152 154

DDR_A_CAS#

156

DDR_A_MA13

158

A13

160 162 164

DIMM_CHA_SA2

166

SA2

168

DDR_A_D17

170 172

DDR_A_D16

174 176 178 180

DDR_A_D22

182 184

DDR_A_D23

186 188

DDR_A_D26

190 192

DDR_A_D30

194 196

DDR_A_DQS#3

198

DDR_A_DQS3

200 202

DDR_A_D31DDR_A_D27

204 206

DDR_A_D28

208 210

DDR_A_D50

212 214

DDR_A_D54

216 218 220 222

DDR_A_D52

224 226

DDR_A_D55

228 230

DDR_A_D59

232 234

DDR_A_D62

236 238

DDR_A_DQS#7

240

DDR_A_DQS7

242 244

DDR_A_D63

246 248 250 252

PCH_SMBDATA

254

SDA

DIMM_CHA_SA0

256

SA0

258

VTT

DIMM_CHA_SA1

260

SA1

262

DDR_A_CKE1 <8>

DDR_A_ACT# <8> DDR_A_ALERT# <8>

DDR_A_CLK1 <8> DDR_A_CLK#1 <8>

DDR_A_BS0 <8> DDR_A_RAS# <8>

DDR_A_CAS# <8>

+1.2V_DDR

PCH_SMBDATA <6,15,18,29,35>

+V_DDR_REFA

CD96

1

0.1U_0402_10V6K

All VREF traces should have 10 mil trace width

2

+0.6VS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/08/25 2012/07/25

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

DDRIII DIMMA

Size Document Number Rev

Date: Sheet of

Date: Sheet

LA-E992P

1

of

14 77Tuesday, July 25, 2017

1.0(A00)

5

DDR_B_D[0..63]<8> DDR_B_MA[0..13]<8> DDR_B_DQS#[0..7]<8> DDR_B_DQS[0..7]<8>

Layout Note: Place near JDIMM2.257,259

D D

+2.5V_MEM +0.6VS +3VS

CD31

CD30

1

1U_0402_6.3V6K

2

Layout Note: Place near JDIMMB

CD28

CD27

1

1U_0402_6.3V6K

2

1

10U_0603_6.3V6M

2

Layout Note: Place near JDIMM2.258

CD32

CD89

CD90

1

1U_0402_6.3V6K

2

1

10U_0603_6.3V6M

2

+1.2V_DDR

CD20

CD19

1

1U_0402_6.3V6K

C C

2

CD22

CD21

1

1U_0402_6.3V6K

2

+1.2V_DDR

CD25

1

2

RH46

1 2

2_0402_1%

10U_0603_6.3V6M

CD26

1

2

+1.2V_DDR

CD23

CD24

1

10U_0603_6.3V6M

2

B B

+V_DDR_REFB_R

20mil

1

CH100

0.022U_0402_16V7K

2

12

RH212

A A

24.9_0402_1%

1U_0402_6.3V6K

10U_0603_6.3V6M

12

CD83

1

2

CD87

1

2

RH207 1K_0402_1%

+V_DDR_REFB

RH210 1K_0402_1%

CD81

1

1U_0402_6.3V6K

2

CD85

1

10U_0603_6.3V6M

2

CD82

CD80

1

2

1

2

1

1U_0402_6.3V6K

2

CD84

10U_0603_6.3V6M

SF000003100

CD86

1

2

CD33

1

10U_0603_6.3V6M

330U_2.5V_M

2

+3VS

DIMM_CHB_SA1

DIMM_CHB_SA2

DIMM_CHB_SA0

4

CD88

1

10U_0603_6.3V6M

2

DVT1.0 Change to SF000003100 OS-CON Cap.

1

+

2

Layout Note: Place near JDIMM2.255

CD34

CD35

1

0.1U_0402_10V6K

1

2.2U_0402_6.3V6M

2

+2.5V_MEM

3

+1.2V_DDR

DDR_B_D1

DDR_B_DQS#0 DDR_B_DQS0

DDR_B_D3

DDR_B_D2

DDR_B_D8

DDR_B_D12

DDR_B_D14 DDR_B_D11

DDR_B_D15 DDR_B_D10

DDR_B_D22

DDR_B_D23

DDR_B_DQS#2 DDR_B_DQS2

DDR_B_D21

DDR_B_D16

DDR_B_D25

DDR_B_D24

DDR_B_D31

DDR_B_D27 DDR_B_D30

DDR_B_CKE0<8>

DDR_B_BG1<8> DDR_B_BG0<8>

DDR_B_CLK0<8> DDR_B_CLK#0<8>

DDR_B_PAR<8> DDR_B_BS1<8>

DDR_B_CS#0<8> DDR_B_WE#<8>

DDR_B_ODT0<8> DDR_B_CS#1<8>

DDR_B_ODT1<8>

+3VS

PCH_SMBCLK<6,14,18,29,35>

DDR_B_CKE0

DDR_B_BG1 DDR_B_BG0

DDR_B_MA12 DDR_B_MA9

DDR_B_MA8 DDR_B_MA6

DDR_B_MA3 DDR_B_MA1

DDR_B_CLK0 DDR_B_CLK#0

DDR_B_PAR DDR_B_BS1

DDR_B_CS#0 DDR_B_WE#

DDR_B_ODT0 DDR_B_CS#1

DDR_B_ODT1

DDR_B_D32

DDR_B_D38

DDR_B_DQS#4 DDR_B_DQS4

DDR_B_D37

DDR_B_D39

DDR_B_D40

DDR_B_D45

+1.2V_DDR

DDR_B_D47 DDR_B_D46

DDR_B_D42

DDR_B_D52

DDR_B_D51

DDR_B_DQS#6 DDR_B_DQS6

DDR_B_D55

DDR_B_D50

DDR_B_D61

DDR_B_D57

+1.2V_DDR

DDR_B_D63

DDR_B_D58

PCH_SMBCLK

JDIMM2

1

VSS1

3

DQ5

5

VSS3

7

DQ1

9

VSS5

11

DQS0_c

13

DQS0_t

15

VSS8

17

DQ7

19

VSS10

21

DQ3

23

VSS12

25

DQ13

27

VSS14

29

DQ9

31

VSS16

33

DM1_n/DBI_n

35

VSS17

37

DQ15

39

VSS19

41

DQ10

43

VSS21

45

DQ21

47

VSS23

49

DQ17

51

VSS25

53

DQS2_c

55

DQS2_t

57

VSS28

59

DQ23

61

VSS30

63

DQ19

65

VSS32

67

DQ29

69

VSS34

71

DQ25

73

VSS36

75

DM3_n/DBI3_n

77

VSS37

79

DQ30

81

VSS39

83

DQ26

85

VSS41

87

CB5/NC

89

VSS43

91

CB1/NC

93

VSS45

95

DQS8_c

97

DQS8_t

99

VSS48

101

CB2/NC

103

VSS50

105

CB3/NC

107

VSS52

109

CKE0

111

VDD1

113

BG1

115

BG0

117

VDD3

119

A12

121

A9

123

VDD5

125

A8

127

A6

129

VDD7

131

A3

133

A1

135

VDD9

137

CK0_t

139

CK0_c

141

VDD11

143

PARITY

145

BA1

147

VDD13

149

CS0_n

151

WE_n/A14

153

VDD15

155

ODT0

157

CS1_n

159

VDD17

161

ODT1

163

VDD19

165

C1, CS3_n,NC

167

VSS53

169

DQ37

171

VSS55

173

DQ33

175

VSS57

177

DQS4_c

179

DQS4_t

181

VSS60

183

DQ38

185

VSS62

187

DQ34

189

VSS64

191

DQ44

193

VSS66

195

DQ40

197

VSS68

199

DM5_n/DBI5_n

201

VSS69

203

DQ46

205

VSS71

207

DQ42

209

VSS73

211

DQ52

213

VSS75

215

DQ49

217

VSS77

219

DQS6_c

221

DQS6_t

223

VSS80

225

DQ55

227

VSS82

229

DQ51

231

VSS84

233

DQ61

235

VSS86

237

DQ56

239

VSS88

241

DM7_n/DBI7_n

243

VSS89

245

DQ62

247

VSS91

249

DQ58

251

VSS93

253

SCL

255

VDDSPD

257

VPP1

259

VPP2

261

GND1

DEREN_40-42271-26001RHF CONN@

SP07001CW00

VSS2

VSS4

VSS6

DM0_n/DBI0_n

VSS7

VSS9

VSS11

DQ12

VSS13

VSS15

DQS1_c

DQS1_t

VSS18

DQ14

VSS20

DQ11

VSS22

DQ20

VSS24

DQ16

VSS26

DM2_n/DBI2_n

VSS27

DQ22

VSS29

DQ18

VSS31

DQ28

VSS33

DQ24

VSS35

DQS3_c

DQS3_t

VSS38

DQ31

VSS40

DQ27

VSS42

CB4/NC

VSS44

CB0/NC

VSS46

DM8_n/DBI_n/NC

VSS47

CB6/NC

VSS49

CB7/NC

VSS51

RESET_n

CKE1 VDD2

ACT_n

ALERT_n

VDD4

VDD6

VDD8

EVENT_n/NF

VDD10 CK1_t/NF CK1_c/NF

VDD12

A10/AP

VDD14

RAS_n/A16

VDD16

CAS_n/A15

VDD18

C0/CS2_n/NC

VREFCA

VSS54

DQ36

VSS56

DQ32

VSS58

DM4_n/DBI4_n

VSS59

DQ39

VSS61

DQ35

VSS63

DQ45

VSS65

DQ41

VSS67

DQS5_c

DQS5_t

VSS70

DQ47

VSS72

DQ43

VSS74

DQ53

VSS76

DQ48

VSS78

DM6_n/DBI6_n

VSS79

DQ54

VSS81

DQ50

VSS83

DQ60

VSS85

DQ57

VSS87

DQS7_c

DQS7_t

VSS90

DQ63

VSS92

DQ59

VSS94

GND2

2

1

+1.2V_DDR

2

DDR_B_D5DDR_B_D0

4

DQ4

6

DDR_B_D4

8

DQ0

10 12 14

DDR_B_D7

16

DQ6

18

DDR_B_D6

20

DQ2

22

DDR_B_D9

24 26

DDR_B_D13

28

DQ8

30

DDR_B_DQS#1

32

DDR_B_DQS1

34 36 38 40 42 44

DDR_B_D18

46 48

DDR_B_D19

50 52 54 56

DDR_B_D20

58 60

DDR_B_D17

62 64

DDR_B_D28

66 68

DDR_B_D29

70 72

DDR_B_DQS#3

74

DDR_B_DQS3

76 78

DDR_B_D26

80 82 84 86 88 90 92 94 96 98 100 102 104 106

DDR4_DRAMRST#

108

DDR_B_CKE1

110 112

DDR_B_ACT#

114

DDR_B_ALERT#

116 118

DDR_B_MA11

120

A11

A7

A5 A4

A2

A0

BA0

A13

SA2

SDA SA0 VTT SA1

DDR_B_MA7

122 124

DDR_B_MA5

126

DDR_B_MA4

128 130

DDR_B_MA2

132 134 136

DDR_B_CLK1

138

DDR_B_CLK#1

140 142

DDR_B_MA0

144

DDR_B_MA10

146 148

DDR_B_BS0

150

DDR_B_RAS#

152 154

DDR_B_CAS#

156

DDR_B_MA13

158 160 162 164

DIMM_CHB_SA2

166 168

DDR_B_D34

170 172

DDR_B_D36

174 176 178 180

DDR_B_D35

182 184

DDR_B_D33

186 188

DDR_B_D44

190 192

DDR_B_D41

194 196

DDR_B_DQS#5

198

DDR_B_DQS5

200 202 204 206

DDR_B_D43

208 210

DDR_B_D54

212 214

DDR_B_D48

216 218 220 222

DDR_B_D53

224 226

DDR_B_D49

228 230

DDR_B_D59

232 234

DDR_B_D62

236 238

DDR_B_DQS#7

240

DDR_B_DQS7

242 244

DDR_B_D60

246 248

DDR_B_D56

250 252

PCH_SMBDATA

254

DIMM_CHB_SA0

256 258

DIMM_CHB_SA1

260 262

DDR4_DRAMRST# <14> DDR_B_CKE1 <8>

DDR_B_ACT# <8> DDR_B_ALERT# <8>

DDR_B_CLK1 <8> DDR_B_CLK#1 <8>

DDR_B_BS0 <8> DDR_B_RAS# <8>

DDR_B_CAS# <8>

CD29

+1.2V_DDR

PCH_SMBDATA <6,14,18,29,35>

+V_DDR_REFB

1

0.1U_0402_10V6K

All VREF traces should have 10 mil trace width

2

+0.6VS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/08/25 2012/07/25

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

DDRIII DIMMB

Size Document Number Rev

Date: Sheet of

LA-E992P

1

15 77Tuesday, July 25, 2017

1.0(A00)

5

4

3

2

1

UH2C

AV2

CL_CLK

AV3

CL_DATA

AW2

CL_RST#

R44

D D

CAM_CBL_DET#

TBT_CIO_PLUG_EVENT#<39>

KB_BL_DET<25 >

PCIE_PTX_SSDRX_P11<29>

+3VS

PCIE_PTX_SSDRX_N11<29> PCIE_PRX_SSDTX_P11<29> PCIE_PRX_SSDTX_N11<29>

SATA_PTX_DRX_N1B<29>

SATA_PTX_DRX_P1B<29> SATA_PRX_DTX_N1B<29> SATA_PRX_DTX_P1B<29>

PCIE_PTX_SSDRX_P12<29>

PCIE_PTX_SSDRX_N12<29> PCIE_PRX_SSDTX_P12<29> PCIE_PRX_SSDTX_N12<29>

12

TPM@

RH561 10K_0402_5%

12

NON_TPM@

RH562 10K_0402_5%

EDP_HPD

PROJECT_ID1 PROJECT_ID2

12

SSD

HDD

C C

SSD

RV551 100K_0402_5%

B B

AMN@

RH557

10K_0402_5%

FSTR@

RH558

10K_0402_5%

TBT_CIO_PLUG_EVENT#

KB_BL_DET

PCIE_PTX_SSDRX_P11 PCIE_PTX_SSDRX_N11 PCIE_PRX_SSDTX_P11 PCIE_PRX_SSDTX_N11

SATA_PTX_DRX_N1B SATA_PTX_DRX_P1B SATA_PRX_DTX_N1B SATA_PRX_DTX_P1B

PCIE_PTX_SSDRX_P12 PCIE_PTX_SSDRX_N12 PCIE_PRX_SSDTX_P12 PCIE_PRX_SSDTX_N12

CPU_DDI1HPD<39> CPU_DDI2HPD<39> CPU_DDI3HPD<35>

EDP_HPD<38>

T91PAD@

T94PAD@

AB33 AB35 AA44 AA45

CPU_DDI1HPD CPU_DDI2HPD CPU_DDI3HPD

EDP_HPD

GPP_G8/FAN_PWM_0

R43

GPP_G9/FAN_PWM_1

U39

GPP_G10/FAN_PWM_2

N42

GPP_G11/FAN_PWM_3

U43

GPP_G0/FAN_TACH_0

U42

GPP_G1/FAN_TACH_1

U41

GPP_G2/FAN_TACH_2

M44

GPP_G3/FAN_TACH_3

U36

GPP_G4/FAN_TACH_4

P44

GPP_G5/FAN_TACH_5

T45

GPP_G6/FAN_TACH_6

T44

GPP_G7/FAN_TACH_7

B33

PCIE11_TXP

C33

PCIE11_TXN

K31

PCIE11_RXP

L31

PCIE11_RXN

GPP_F10/SCLOCK GPP_F11/SLOAD GPP_F13/SDATAOUT0 GPP_F12/SDATAOUT1

B38

PCIE14_TXN/SATA1B_TXN

C38

PCIE14_TXP/SATA1B_TXP

D39

PCIE14_RXN/SATA1B_RXN

E37

PCIE14_RXP/SATA1B_RXP

C36

PCIE13_TXN/SATA0B_TXN

B36

PCIE13_TXP/SATA0B_TXP

G35

PCIE13_RXN/SATA0B_RXN

E35

PCIE13_RXP/SATA0B_RXP

A35

PCIE12_TXP

B35

PCIE12_TXN

H33

PCIE12_RXP

G33

PCIE12_RXN

J45

PCIE20_TXP

K44

PCIE20_TXN

N38

PCIE20_RXP

N39

PCIE20_RXN

H44

PCIE19_TXP

H43

PCIE19_TXN

L39

PCIE19_RXP

L37

PCIE19_RXN

SKY-H-PCH_BGA837

@

AW4

AY2 AV4 BA4

BD7

UH2E

GPP_I0/DDPB_HPD0 GPP_I1/DDPC_HPD1 GPP_I2/DDPD_HPD2 GPP_I3/DDPE_HPD3

GPP_I4/EDP_HPD

SKY-H-PCH_BGA837

@

SKY-S-PCH_BGA837

CLINK

PCIE10_RXN/SATA1A_RXN PCIE10_RXP/SATA1A_RXP

FAN

3 OF 12 REV = 1.3

SKY-S-PCH_BGA837

PCIE10_TXN/SATA1A_TXN PCIE10_TXP/SATA1A_TXP

PCIe/SATA

GPP_E0/SATAXPCIE0/SATAGP0 GPP_E1/SATAXPCIE1/SATAGP1 GPP_E2/SATAXPCIE2/SATAGP2 GPP_F0/SATAXPCIE3/SATAGP3 GPP_F1/SATAXPCIE4/SATAGP4 GPP_F2/SATAXPCIE5/SATAGP5 GPP_F3/SATAXPCIE6/SATAGP6 GPP_F4/SATAXPCIE7/SATAGP7

HOST

GPP_I8/DDPC_CTRLDATA

GPP_I6/DDPB_CTRLDATA

GPP_I10/DDPD_CTRLDATA

5 OF 12 REV = 1.3

PCIE9_RXN/SATA0A_RXN PCIE9_RXP/SATA0A_RXP PCIE9_TXN/SATA0A_TXN

PCIE9_TXP/SATA0A_TXP

PCIE15_RXN/SATA2_RXN PCIE15_RXP/SATA2_RXP

PCIE15_TXN/SATA2_TXN PCIE15_TXP/SATA2_TXP

PCIE16_RXN/SATA3_RXN PCIE16_RXP/SATA3_RXP

PCIE16_TXN/SATA3_TXN PCIE16_TXP/SATA3_TXP

PCIE17_RXN/SATA4_RXN PCIE17_RXP/SATA4_RXP

PCIE17_TXN/SATA4_TXN PCIE17_TXP/SATA4_TXP

PCIE18_RXN/SATA5_RXN PCIE18_RXP/SATA5_RXP

PCIE18_TXN/SATA5_TXN PCIE18_TXP/SATA5_TXP

GPP_E8/SATALED#

GPP_F21/EDP_BKLTCTL

GPP_F20/EDP_BKLTEN

GPP_F19/EDP_VDDEN

THERMTRIP#

PECI

PM_SYNC

PLTRST_CPU#

PM_DOWN

GPP_I7/DDPC_CTRLCLK

GPP_I5/DDPB_CTRLCLK

GPP_I9/DDPD_CTRLCLK

GPP_F14 GPP_F23 GPP_F22

GPP_G23 GPP_G22 GPP_G21 GPP_G20 GPP_H23

SATA_PRX_SSDTX_N0A

G31

SATA_PRX_SSDTX_P0A

H31

SATA_PTX_SSDRX_N0A

C31

SATA_PTX_SSDRX_P0A

B31

PCIE_PRX_SSDTX_N10

G29

PCIE_PRX_SSDTX_P10

E29

PCIE_PTX_SSDRX_N10

C32

PCIE_PTX_SSDRX_P10

B32

F41 E41 B39 A39

D43 E42 A41 A40

H42 H40 E45 F45

K37 G37 G45 G44

PCH_SATA_LED#

AD44

mCARD_PCIE_SATA#

AG36 AG35

T182 PAD @

AG39 AD35 AD31 AD38 AC43 AB44

BIA_PWM_PCH

W36

L_BKLT_EN_EC

W35

ENVDD_PCH

W42

H_THERMTRIP#

AJ3 AL3

PECI H_PM_SYNC

AJ4

PLTRST_CPU#

AK2

H_PM_DOWN

AH2

BB3

DDI2_DDPC_CTRLDAT

BD6 BA5

DDI1_DDPB_CTRLDAT

BC4 BE5

DDI3_DDPD_CTRLDAT

BE6

PROC_DETECT#

Y44 V44 W39

PROJECT_ID2

L43

PROJECT_ID1

L44

LCD_DBC

U35 R35 BD36

SATA_PRX_SSDTX_N0A <29> SATA_PRX_SSDTX_P0A <29> SATA_PTX_SSDRX_N0A <29> SATA_PTX_SSDRX_P0A <29>

PCIE_PRX_SSDTX_N10 <29> PCIE_PRX_SSDTX_P10 <29> PCIE_PTX_SSDRX_N10 <29> PCIE_PTX_SSDRX_P10 <29>

PCH_SATA_LED# <37>

mCARD_PCIE_SATA# <29>

BIA_PWM_PCH <7,38> L_BKLT_EN_EC <36> ENVDD_PCH <42>

1 2

RH191 620_0402_5%

1 2

RH138 13_0402_5% RH189

1 2

T2 PAD@

T8 PAD

30_0402_5%

PLTRST_CPU# <6,9> H_PM_DOWN <9>

PROC_DETECT# <9>

@

SSD

H_THERMTRIP#_R PECI_EC H_PM_SYNC_R

+3VS

12

RH559

LCD_DBC

H_THERMTRIP#_R <9> PECI_EC <9,36> H_PM_SYNC_R <9>

10K_0402_5%

12

@

RH560 10K_0402_5%

mCARD_PCIE_SATA#

CAM_CBL_DET#

PCH_SATA_LED#

PCH Strap PIN

DDI3_DDPD_CTRLDAT

DDI2_DDPC_CTRLDAT

DDI1_DDPB_CTRLDAT

RH68

RH79

RH80

RH141

RH579

RH580

1 2

10K_0402_5%

1 2

10K_0402_5%

1 2

10K_0402_5%

1 2

2.2K_0402_5%

1 2

2.2K_0402_5%

1 2

2.2K_0402_5%

+3VALW

+3VS

A A

DVT1.0 Change RH557 BS to AMN@. Change RH558 BS to FSTR@

PROJECT ID

Firestar Armani

PROJECT ID1 (GPP_G22)

0 1

5

TPM ID

SW TPM HW TPM

PROJECT ID2 (GPP_G23)

0 1

Security Classification

2011/08/25 2012/07/25

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/08/25 2012/07/25

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet

Compal Electronics, Inc.

PCH (1/8) SATA,HDA

LA-E992P

1

1.0(A00)

of

16 77Tuesday, July 25, 2017

5

+3VS

RP3

RH74

RH568

991@EMI@

LAN_CLKREQ# VGA_CLK_REQ# WLAN_CLK_REQ# SSD_CLK_REQ#

PCH_SPI_CS#

TPM_PIRQ#

RH582

0_0402_5%

SD028000080

PCH_SPI_CLK_R1<27>

992@EMI@

10P_0402_25V8J

PCH_SPI_CLK_R1

@RF@

CH215

CPU_24MHZ_P<9> CPU_24MHZ_N<9>

PCH_CPU_BCLK_P<9> PCH_CPU_BCLK_N<9>

LAN_CLKREQ#<33> WLAN_CLK_REQ#<28>

TBT_CLK_REQ#<39> SSD_CLK_REQ#<29> VGA_CLK_REQ#<46>

RH582 15_0402_5%@EMI@

1

2

+1VALW

PCH_SPI_SI<6,27>

1 2

PCH_SPI_WP#<6>

PCH_SPI_CS2#<27>

4 5 3 6 2 7 1 8

10K_0804_8P4R_5%

D D

+3V_ROM

1 2

4.7K_0402_5%

C C

+3VALW

RH582

1 2

10K_0402_5%

15_0402_5%

SD028150A80

DVT1.0 Add RH582 BOM option for LA-E991P and LA-E992P EA difference.

B B

Reserve for RF

SPI ROM FOR ME ( 16MByte )

DVT2.0 Change RH101 to 0ohm 0402 short-pad footprint.

PCH_SPI_CS#

A A

PCH_SPI_CLK_R1 PCH_SPI_SO PCH_SPI_SO_R

PCH

PCH_SPI_SI PCH_SPI_WP#

1 2

RH101 0_0402_5%@

1 2

RE126 33_0402_5%

1 2

RE127 33_0402_5%

1 2

RE128 33_0402_5%

1 2

RE129 33_0402_5%

1 2

RE71 33_0402_5%

Close to UH8

5

PCH_SPI_CS#_R PCH_SPI_SO_R PCH_SPI_WP#_R

PCH_SPI_CLK_R

PCH_SPI_SI_R PCH_SPI_WP#_R PCH_SPI_HOLD#_RPCH_SPI_HOLD#

4

UH2G

2.7K_0402_1%

+3V_ROM+3VALW

12

8

PCH_SPI_HOLD#_R

7

PCH_SPI_CLK_R

6

PCH_SPI_SI_R

5

AR17

GPP_A16/CLKOUT_48

G1

CLKOUT_CPUNSSC_P

F1

CLKOUT_CPUNSSC

G2

CLKOUT_CPUBCLK_P

H2

CLKOUT_CPUBCLK

A5

XTAL24_OUT

A6

XTAL24_IN

E1

XCLK_BIASREF

BC9

RTCX1

BD10

RTCX2

BC24

GPP_B5/SRCCLKREQ0#

AW24

GPP_B6/SRCCLKREQ1#

AT24

GPP_B7/SRCCLKREQ2#

BD25

GPP_B8/SRCCLKREQ3#

BB24

GPP_B9/SRCCLKREQ4#

BE25

GPP_B10/SRCCLKREQ5#

AT33

GPP_H0/SRCCLKREQ6#

AR31

GPP_H1/SRCCLKREQ7#

BD32

GPP_H2/SRCCLKREQ8#

BC32

GPP_H3/SRCCLKREQ9#

BB31

GPP_H4/SRCCLKREQ10#

BC33

GPP_H5/SRCCLKREQ11#

BA33

GPP_H6/SRCCLKREQ12#

AW33

GPP_H7/SRCCLKREQ13#

BB33

GPP_H8/SRCCLKREQ14#

BD33

GPP_H9/SRCCLKREQ15#

R13

CLKOUT_PCIE_N15

R11

CLKOUT_PCIE_P15

P1

CLKOUT_PCIE_N14

R2

CLKOUT_PCIE_P14

W7

CLKOUT_PCIE_N13

Y5

CLKOUT_PCIE_P13

U2

CLKOUT_PCIE_N12

U3

CLKOUT_PCIE_P12

SKY-H-PCH_BGA837

@

UH2A

BD17

GPP_A11/PME#

AG15

RSVD_AG15

AG14

RSVD_AG14

AF17

RSVD_AF17

AE17

RSVD_AE17

AR19

TP5

AN17

TP4

BB29

SPI0_MOSI

BE30

SPI0_MISO

BD31

SPI0_CS0#

BC31

SPI0_CLK

AW31

SPI0_CS1#

BC29

SPI0_IO2

BD30

SPI0_IO3

AT31

SPI0_CS2#

AN36

GPP_D1/SPI1_CLK

AL39

GPP_D0/SPI1_CS#

AN41

GPP_D3/SPI1_MOSI

AN38

GPP_D2/SPI1_MISO

AH43

GPP_D22/SPI1_IO3

AG44

GPP_D21/SPI1_IO2

SKY-H-PCH_BGA837

@

DVT2.0 Change RH121 to 0ohm 0603 short-pad footprint.

T92PAD@

CPU_24MHZ_P CPU_24MHZ_N

PCH_CPU_BCLK_P PCH_CPU_BCLK_N

XTAL24_OUT XTAL24_IN

1 2

RH71

PCH_RTCX1 PCH_RTCX2

LAN_CLKREQ# WLAN_CLK_REQ#

TBT_CLK_REQ# SSD_CLK_REQ# VGA_CLK_REQ#

T17PAD@

PCH_SPI_SI

PCH_SPI_SO<27>

FFS_INT2<29> TPM_PIRQ#<27>

UH8

1

/CS

2

DO(IO1)

3

/WP(IO2)

4

GND

MX25L12873FM2I-10G_SOP_8P

W25Q128FVSIQ_SO8

SA00006O300

DVT1.0 Change UH8 to SA00006O300 due to SA00005VV10 and SA00008KK00 EOL

PCH_SPI_SO PCH_SPI_CS# PCH_SPI_CLK

PCH_SPI_WP# PCH_SPI_HOLD# PCH_SPI_CS2#

FFS_INT2 TPM_PIRQ#

RH121

0_0603_5%

VCC

/HOLD(IO3)

CLK

DI(IO0)

@

SPI ROM

4

SKY-S-PCH_BGA837

7 OF 12 REV = 1.3

SKY-S-PCH_BGA837

1 OF 12 REV = 1.3

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

CLKOUT_ITPXDP

CLKOUT_ITPXDP_P

CLKOUT_CPUPCIBCLK

CLKOUT_CPUPCIBCLK_P

CLKOUT_PCIE_N0 CLKOUT_PCIE_P0

CLKOUT_PCIE_N1 CLKOUT_PCIE_P1

CLKOUT_PCIE_N2 CLKOUT_PCIE_P2

CLKOUT_PCIE_N3 CLKOUT_PCIE_P3

CLKOUT_PCIE_N4 CLKOUT_PCIE_P4

CLKOUT_PCIE_N5 CLKOUT_PCIE_P5

CLKOUT_PCIE_N6 CLKOUT_PCIE_P6

CLKOUT_PCIE_N7 CLKOUT_PCIE_P7

CLKOUT_PCIE_N8 CLKOUT_PCIE_P8

CLKOUT_PCIE_N9 CLKOUT_PCIE_P9

CLKOUT_PCIE_N10 CLKOUT_PCIE_P10

CLKOUT_PCIE_N11 CLKOUT_PCIE_P11

GPP_B13/PLTRST#

GPP_G16/GSXCLK

GPP_G12/GSXDOUT

GPP_G13/GSXSLOAD

GPP_G14/GSXDIN

GPP_G15/GSXSRESET#

GPP_E3/CPU_GP0 GPP_E7/CPU_GP1 GPP_B3/CPU_GP2 GPP_B4/CPU_GP3

GPP_H18/SML4ALERT#

GPP_H17/SML4DATA

GPP_H16/SML4CLK

GPP_H15/SML3ALERT#

GPP_H14/SML3DATA

GPP_H13/SML3CLK

GPP_H12/SML2ALERT#

GPP_H11/SML2DATA

GPP_H10/SML2CLK

INTRUDER#

3

2

PCH_XDP_CLK_N

L1

PCH_XDP_CLK_P

L2

PCH_CPU_PCIBCLK_N

J1

PCH_CPU_PCIBCLK_P

J2

N7 N8

L7 L5

CLK_PCIE_LAN#

D3

CLK_PCIE_LAN

F2

CLK_PCIE_WLAN#

E5

CLK_PCIE_WLAN

G4

D5 E6

CLK_PCIE_N5

D8

CLK_PCIE_P5

D7

CLK_PCIE_SSD#

R8

CLK_PCIE_SSD

R7

CLK_PEG_GPU#

U5

CLK_PEG_GPU

U7

W10 W11

N3 N2

P3 P2

R3 R4

PCH_PLTRST#

BB27

TBT_FORCE_PWR

P43

RTD3_CIO_PWR_EN

R39 R36 R42 R41

AF41

TOUCH_SCREEN_PD#

AE44

TOUCHPAD_INTR#

BC23

GC6_THM_DIS#

BD24

BC36 BE34 BD39 BB36 BA35 BC35 BD35 AW35 BD34

BE11

INTRUDER#

PCH_PLTRST#

SA00000OH00

MC74VHC1G08DFT2G_SC70-5

2011/08/25 2012/07/25

1

IN1

2

IN2

Compal Secret Data

TBT_FORCE_PWR <39> RTD3_CIO_PWR_EN <39>

TOUCH_SCREEN_PD# <38>

GC6_THM_DIS# <36>

RH1

1 2

@

0_0402_5%

+3VS

5

UH7

VCC

OUT

GND

3

Deciphered Date

PCH_XDP_CLK_N <6> PCH_XDP_CLK_P <6>

PCH_CPU_PCIBCLK_N <9> PCH_CPU_PCIBCLK_P <9>

CLK_PCIE_LAN# <33> CLK_PCIE_LAN < 33>

CLK_PCIE_WLAN# <28> CLK_PCIE_WLAN <28>

CLK_PCIE_N5 <39> CLK_PCIE_P5 <39>

CLK_PCIE_SSD# <2 9> CLK_PCIE_SSD <29 >

CLK_PEG_GPU# <46> CLK_PEG_GPU <46>

XTAL24_OUT

XTAL24_IN

4

PCH_PLTRST#_EC

12

RH77 100K_0402_5%

2

RH570 33_0201_5%EMI@

RH569 33_0201_5%EMI@

PCH_RTCX2

PCH_RTCX1

LAN

NGFF - WLAN

TBT-AR

NGFF - SSD

GPU

1 2

TOUCH_SCREEN_PD#

TOUCHPAD_INTR#

GC6_THM_DIS#

Need SW confirm!!!

INTRUDER#

Pilot Change DH1 footprint to AZ5125-01HPR7G_SOD523-2

TOUCHPAD_INTR# PTP_INT#

PCH_PLTRST#

PCH_PLTRST#_EC <27,28,29,33,36,39,46>

1

RTC CRYSTAL

1 2

RH70 10M_0402_5%

YH1

32.768KHZ 9PF 20PPM 9H03280012

1 2

SJ10000Q400

Max Crystal ESR

1

= 50k Ohm.

CH45

8.2P_0402_50V8D

2

XTAL24_OUT_R

XTAL24_IN_R

PCH CRYSTAL

1 2

1M_0402_5%

24MHZ_12PF_X3G024000DC1H

SJ10000CS00

123

1

CH47 15P_0402_50V8J

2

1 2

RH69 10K_0402_5%

1 2

RH179 10K_0402_5%

1 2

RH573 10K_0402_5%

1 2

RH143 1M_0402_5%

DH1

12

RB751S40T1G_SOD523-2

AZ5125-01HPR7G_SOD523-2

Reserve for ESD

1 2

CH208 100P_0402_50V8J

@ESD@

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

PCH (2/8) SMBUS, CLK, SPI, LPC

RH72

4

YH2

LA-E992P

1

CH46

8.2P_0402_50V8D

2

1

2

+3VS

+RTCVCC

17 77Tuesday, July 25, 2017

CH48 15P_0402_50V8J

PTP_INT# <26,36>

1.0(A00)

of

5

+3VALW

1 2

RH21 1K_0402_5%

1 2

RH22 1K_0402_5%

1 2

RH62 499_0402_1%

1 2

RH63 499_0402_1%

+3VS

1 2

RH27 1K_0402_5%

1 2

RH26 1K_0402_5%

1 2

RH86 10K_0402_5%

D D

1 2

RH13 100K_0402_5%

1 2

RH581 100K_0402_5%

RTCRST_ON<36>

RH571

100K_0402_5%

C C

QH4A

2

DMN65D8LDW-7_SOT363-6

SMBCLK

SMBDATA

Buffer with Open Drain Output For VTT power control

B B

A A

6 1

3 4

QH4B DMN65D8LDW-7_SOT363-6

UC16

1

ME_FWP<36>

NC

2

A

3

GND

74AUP1G07SE-7_SOT353

SA00007WE00

VR_ON

Service Mode Switch: Add a switch to ME_FWP signal to unlock the ME region and allow the entire region of the SPI flash to be updated using FPT.

SMBCLK SMBDATA

SML0_SMBCLK SML0_SMBDATA

PCH_SMBCLK PCH_SMBDATA

DGPU_PWROK

PCH_RSMRST# SYS_PWROK

13

D

2

G

12

ME_FWP

S

+3VS

5

+3VALW

12

CC2980.1U_0402_16V7K

5

VCC

4

Y

RH18 1K_0402_5%

HDA_SDOUT_AUDIO<23>

HDA_SYNC_AUDIO<23>

HDA_BITCLK_AUDIO<23>

HDA_SDIN0_AUDIO<23>

AUD_AZA_CPU_SDO<7>

AUD_AZA_CPU_SDI_R<7>

AUD_AZA_CPU_SCLK<7>

PCH_RTCRST#

DVT1.0 Change QH6 to SB00000PU00

QH6 L2N7002LT1G_SOT23-3

PCH_RSMRST#<6,36>

PCH to DDR

PCH_SMBCLK

PCH_SMBDATA

H_VCCST_PWRGD

1 2

PCH_SMBCLK <6,14,15,29, 35>

PCH_SMBDATA <6,14,15,29,35>

H_VCCST_PWRGD <6,9> VR_ON <71>

HDA_SDOUT

1 2

HDA_SDOUT_AUDIO HDA_SDOUT

HDA_SYNC_AUDIO HDA_SYNC

CH5010P_0402_25V8J @EMI@

AUD_AZA_CPU_SCLK

DVT2.0 Change RH9, RH503 to 0ohm 0402 short-pad footprint.

PCH_RSMRST#

ME_FWP PCH has internal 20K PD.

FLASH DESCRIPTOR SECURITY OVERRIDE

Disable ME Protect (ME can be updated) Enable ME Protect (ME cannot be updated)(Default position)

5

GPU_THM_SMBCLK<27,36,46>

GPU_THM_SMBDAT<27,36,46>

4

1 2

Close to PCH

RH146

RH147

DGPU_PWROK<46,55,69>

RH503 0_0402_5%

RH9

+VCCIO_PG<74>

IMVP_VR_PG<71>

ALL_SYS_PWRGD<18,36,61>

IMVP_VR_ON<36>

RH552

10K_0402_5%

SD028100280

RH554

10K_0402_5%

SD028100280

4

RP15

1 8 2 7 3 6 4 5

33_0804_8P4R_5%

RH57233_0402_5% EMI@

1 2

30_0402_5%

1 2

30_0402_5%

1 2

@

1 2

@

0_0402_5%

MC74VHC1G08DFT2G_SC70-5

GPU ID

N/A N17P-G0 N17E-G1 N17P-G1

UMA@

3

UH2D

HDA_BITCLK

HDA_SDIN0_AUDIO

HDA_SDOUT HDA_SYNC

AUD_AZA_CPU_SDO_RAUD_AZA_CPU_SDO AUD_AZA_CPU_SDI_R AUD_AZA_CPU_SCLK_R

GPU_ID2 GPU_ID1

DGPU_PWROK

PCH_RTCRST# PCH_SRTCRST#

PCH_PWROK PCH_RSMRST#_R AC_PRESENT

PCH_DPWROK SMBALERT# SMBCLK SMBDATA SML0ALERT# SML0_SMBCLK SML0_SMBDATA SML1ALERT# GPU_THM_SMBCLK GPU_THM_SMBDAT

IMVP_VR_PG

ALL_SYS_PWRGD

IMVP_VR_ON

SIO_SLP_S3#

SA00000OH00

GPU ID2 (GPP_D6)

0 0 1 1

RH551

N17P_G0@

10K_0402_5%

SD028100280

RH554

N17P_G0@

10K_0402_5%

SD028100280

BA9

HDA_BCLK

BD8

HDA_RST#

BE7

HDA_SDI0

BC8

HDA_SDI1

BB7

HDA_SDO

BD9

HDA_SYNC

BD1

RSVD_BD1

BE2

RSVD_BE2

AM1

DISPA_SDO

AN2

DISPA_SDI

AM2

DISPA_BCLK

AL42

GPP_D8/SSP0_SCLK

AN42

GPP_D7/SSP0_RXD

AM43

GPP_D6/SSP0_TXD

AJ33

GPP_D5/SSP0_SFRM

AH44

GPP_D20/DMIC_DATA0

AJ35

GPP_D19/DMIC_CLK0

AJ38

GPP_D18/DMIC_DATA1

AJ42

GPP_D17/DMIC_CLK1

BC10

RTCRST#

BB10

SRTCRST#

AW11

PCH_PWROK

BA11

RSMRST#

AV11

DSW_PWRO K

BB41

GPP_C2/SMBALERT#

AW44

GPP_C0/SMBCLK

BB43

GPP_C1/SMBDATA

BA40

GPP_C5/SML0ALERT#

AY44

GPP_C3/SML0CLK

BB39

GPP_C4/SML0DATA

AT27

GPP_B23/SML1ALERT#/PCHHOT#

AW42

GPP_C6/SML1CLK

AW45

GPP_C7/SML1DATA

SKY-H-PCH_BGA837

@

+3VS

12

RH180 100K_0402_5%

RH103

1 2

MC74VHC1G08DFT2G_SC70-5

RH105

1 2

@

0_0402_5%

DVT2.0 Change RH103, RH105 to 0ohm 0402 short-pad footprint.

SA00000OH00

+3VALW

5

UZ21

1

VCC

IN1

OUT

2

IN2

GND

3

AUDIO

ALL_SYS_PWRGD+VCCIO_PG

@

+3VS

5

1

VCC

IN1

2

IN2

GND

3

4

12

RZ71 100K_0402_5%

GPU ID1 (GPP_D5)

0 1 0 1

RH551

RH552

N17E_G1@

10K_0402_5%

SD028100280

RH553

N17E_G1@

10K_0402_5%

SD028100280

N17P_G1@

10K_0402_5%

SD028100280

RH553

N17P_G1@

10K_0402_5%

SD028100280

SKY-S-PCH_BGA837

GPP_B1 GPP_B0

GPP_B11

SYS_PWROK

WAKE#

SLP_LAN#

SLP_SUS#

SYS_RESET#

ITP_PMODE

JTAGX

JTAG_TMS

JTAG_TDO

JTAG_TDI

JTAG_TCK

BB17 AW22

AR15

AV13

H_DRAMRST#

BC14 BD23

LAN_DISABLE#_R

AL27 AR27 N44 AN24

SYS_PWROK

AY1

PCH_PCIE_WAKE#

BC13 BC15 AV15

SIO_SLP_S0#

BC26

SIO_SLP_S3#

AW15

SIO_SLP_S4#

BD15

SIO_SLP_S5#

BA13

AN15

SUSCLK PCH_BATLOW#

BD13 BB19

ME_SUS_PWR_ACK

BD19

LAN_WAKE#

BD11 BB15 BB13

SIO_PWRBTN#

AT13

SYS_RESET#

AW1 BD26

SPKR H_CPUPWRGD

AM3

PCH_ITP_PMODE

AT2

PCH_JTAGX CPU_XDP_TCK

AR3

PCH_JTAG_TMS

AR2

PCH_JTAG_TDO

AP1

PCH_JTAG_TDI

AP2

PCH_JTAG_TCK

AN3

+RTCVCC

1 2

RH83 20K_0402_5%

+RTCVCC

1 2

RH84 20K_0402_5%

UH14

OUT

VR_ON

GPP_A12/BMBUSY#/ISH_GP6/SX_EXIT_HOLDOFF#

GPP_A13/SUSWARN#/SUSPW RDNACK

SMBUS

JTAG

4 OF 12REV = 1.3

ALL_SYS_PWRGD <18,36,61>

PCH_PWROK

4

12

RH94 10K_0402_5%

GPP_A8/CLKRUN#

GPD11/LANPHYPC

GPD9/SLP_WLAN#

DRAM_RESET#

GPP_B2/VRALERT#

GPP_G17/ADR_COMPLETE

GPD6/SLP_A#

GPP_B12/SLP_S0#

GPD4/SLP_S3# GPD5/SLP_S4#

GPD10/SLP_S5#

GPD8/SUSCLK

GPD0/BATLOW#

GPP_A15/SUSACK#

GPD2/LAN_WAKE#

GPD1/ACPRESENT

GPD3/PWRBTN#

GPP_B14/SPKR

PROCPWRGD

Reserve for ESD

CH212 100P_0402_50V8J

+3VS

12

10K_0402_5%

12

10K_0402_5%

@

RH553

@

RH554

12

GPU_ID1 GPU_ID2

12

2011/08/25 2012/07/25

@

RH551

10K_0402_5%

@

RH552

10K_0402_5%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

CH209 100P_0402_50V8J

Reserve for RF please close to UH1

Compal Secret Data

Deciphered Date

2

H_DRAMRST# <14>

LAN_DISABLE#_R <33>

SYS_PWROK <6,36>

1 2

RH114

@

0_0402_5%

SIO_SLP_S0# <27> SIO_SLP_S3# <38,39,42,43,44,62> SIO_SLP_S4# <42,43,63>

SUSCLK <28,29,36>

DVT2.0 Change RH11 to 0ohm 0402 short-pad footprint.

1 2

RH11 0_0402_5%@ DV1

12

RB751S40T1G_SOD523-2 AZ5125-01HPR7G_SOD523-2

SIO_PWRBTN# <6,36> SYS_RESET# <6> SPKR <23> H_CPUPWRGD <9>

PCH_ITP_PMODE <6>

PCH_JTAG_TMS <6> PCH_JTAG_TDO <6> PCH_JTAG_TDI <6> PCH_JTAG_TCK <6>

RTC Reset

CH52

1U_0402_6.3V6K

CH53

1U_0402_6.3V6K

12

ESD@

12

@ESD@

1 2

CH51 10P_0402_25V8J

@RF@

2

PCH_SRTCRST#

12

PCH_RTCRST#

12

PCH_PCIE_WAKE# PCH_BATLOW# LAN_WAKE# AC_PRESENT

SYS_RESET#

ME_SUS_PWR_ACK

DVT2.0 Change RH114 to 0ohm 0402 short-pad footprint.

PCIE_WAKE#

LANWAKE# ACAV_IN

PCIE_WAKE# <28,33,36,39>

LANWAKE# <36>

Pilot

DVT2.0 Change RH38 to 0ohm 0402 short-pad footprint.

RH38

1 2

@

0_0402_5%

Change DV1 footprint to AZ5125-01HPR7G_SOD523-2

+3VALW

RH66 2.2K_0402_5%@

TLS CONFIDENTIALITY

HIGH LOW(DEFAULT)

+3VALW

CLRP1 SHORT PADS

@

PCH_RSMRST#

SYS_RESET#

HDA_SDOUT

Title

Size Document Number Rev

Date: Sheet of

RH64 2.2K_0402_5%

EC interface

HIGH LOW(DEFAULT)

+3VALW

RH65 150K_0402_5%

PCHHOT#

HIGH LOW(DEFAULT)

+3VALW

RH82 2.2K_0402_5%@

Top Swap Override (internal PD)

HIGH LOW(DEFAULT)

Compal Electronics, Inc.

PCH (3/8) DMI,FDI,PM,GFX,DP

1

1 2

RH17 1K_0402_5%

1 2

RH81 10K_0402_5%

1 2

RH181 10K_0402_5%

1 2

RH125 100K_0402_5%

1 2

RH193 8.2K_0402_5%@

1 2

RH67 1M_0402_5%@

T4938 PAD @

ACAV_IN <36,59,60>

CPU_XDP_TCK <6,9>

1 2

Enable Disable

1 2

ESPI LPC

1 2

Enable Disable

1 2

ENABLE DISABLE

LA-E992P

1

SMBALERT#

SML0ALERT#

SML1ALERT#

SPKR

18 77Tuesday, July 25, 2017

+3V_PCH_DSW

+3VALW

+1.8V_PRIM

1.0(A00)

5

4

3

2

1

DMI_CTX_PRX_N0<7>

D D

TBT-AR

C C

LAN

NGFF

DMI_CTX_PRX_P0<7>

DMI_CRX_PTX_N0<7>

DMI_CRX_PTX_P0<7> DMI_CTX_PRX_N1<7> DMI_CTX_PRX_P1<7>

DMI_CRX_PTX_N1<7>

DMI_CRX_PTX_P1<7> DMI_CTX_PRX_N2<7> DMI_CTX_PRX_P2<7>

DMI_CRX_PTX_N2<7>

DMI_CRX_PTX_P2<7> DMI_CTX_PRX_N3<7> DMI_CTX_PRX_P3<7>

DMI_CRX_PTX_N3<7>

DMI_CRX_PTX_P3<7>

1 2

RH108

PCIE_PRX_TBTTX_N1<39> PCIE_PRX_TBTTX_P1<39>

PCIE_PRX_TBTTX_N2<39> PCIE_PRX_TBTTX_P2<39> PCIE_PRX_TBTTX_N3<39> PCIE_PRX_TBTTX_P3<39>

PCIE_PRX_TBTTX_N4<39> PCIE_PRX_TBTTX_P4<39>

PCIE_PRX_LANTX_N5<33> PCIE_PRX_LANTX_P5<33>

PCIE_PRX_WLANTX_N6<28 > PCIE_PRX_WLANTX_P6<28>

100_0402_1%

PCIE_PTX_TBTRX_N1<39>

PCIE_PTX_TBTRX_P1<39>

PCIE_PTX_TBTRX_N2<39>

PCIE_PTX_TBTRX_P2<39>

PCIE_PTX_TBTRX_N3<39>

PCIE_PTX_TBTRX_P3<39>

PCIE_PTX_TBTRX_N4<39>

PCIE_PTX_TBTRX_P4<39>

PCIE_PTX_LANRX_N5<33>

PCIE_PTX_LANRX_P5<33>

PCIE_PTX_WLANRX_N6<28 >

PCIE_PTX_WLANRX_P6<28>

DMI_CTX_PRX_N0 DMI_CTX_PRX_P0 DMI_CRX_PTX_N0 DMI_CRX_PTX_P0 DMI_CTX_PRX_N1 DMI_CTX_PRX_P1 DMI_CRX_PTX_N1 DMI_CRX_PTX_P1 DMI_CTX_PRX_N2 DMI_CTX_PRX_P2 DMI_CRX_PTX_N2 DMI_CRX_PTX_P2 DMI_CTX_PRX_N3 DMI_CTX_PRX_P3 DMI_CRX_PTX_N3 DMI_CRX_PTX_P3

PCIE_RCOMPN PCIE_RCOMPP

PCIE_PRX_TBTTX_N1 PCIE_PRX_TBTTX_P1 PCIE_PTX_TBTRX_N1 PCIE_PTX_TBTRX_P1 PCIE_PTX_TBTRX_N2 PCIE_PTX_TBTRX_P2 PCIE_PRX_TBTTX_N2 PCIE_PRX_TBTTX_P2 PCIE_PRX_TBTTX_N3 PCIE_PRX_TBTTX_P3 PCIE_PTX_TBTRX_N3 PCIE_PTX_TBTRX_P3 PCIE_PRX_TBTTX_N4 PCIE_PRX_TBTTX_P4 PCIE_PTX_TBTRX_N4 PCIE_PTX_TBTRX_P4 PCIE_PRX_LANTX_N5 PCIE_PRX_LANTX_P5 PCIE_PTX_LANRX_N5 PCIE_PTX_LANRX_P5 PCIE_PRX_WLANTX_N6 PCIE_PRX_WLANTX_P6 PCIE_PTX_WLANRX_N6 PCIE_PTX_WLANRX_P6

UH2B

L27

DMI_RXN0

N27

DMI_RXP0

C27

DMI_TXN0

B27

DMI_TXP0

E24

DMI_RXN1

G24

DMI_RXP1

B28

DMI_TXN1

A28

DMI_TXP1

G27

DMI_RXN2

E26

DMI_RXP2

B29

DMI_TXN2

C29

DMI_TXP2

L29

DMI_RXN3

K29

DMI_RXP3

B30

DMI_TXN3

A30

DMI_TXP3

B18

PCIE_RCOMPN

C17

PCIE_RCOMPP

H15

PCIE1_RXN/USB3_7_RXN

G15

PCIE1_RXP/USB3_7_RXP

A16

PCIE1_TXN/USB3_7_TXN

B16

PCIE1_TXP/USB3_7_TXP

B19

PCIE2_TXN/USB3_8_TXN

C19

PCIE2_TXP/USB3_8_TXP

E17

PCIE2_RXN/USB3_8_RXN

G17

PCIE2_RXP/USB3_8_RXP

L17

PCIE3_RXN/USB3_9_RXN

K17

PCIE3_RXP/USB3_9_RXP

B20

PCIE3_TXN/USB3_9_TXN

C20

PCIE3_TXP/USB3_9_TXP

E20

PCIE4_RXN/USB3_10_RXN

G19

PCIE4_RXP/USB3_10_RXP

B21

PCIE4_TXN/USB3_10_TXN

A21

PCIE4_TXP/USB3_10_TXP

K19

PCIE5_RXN

L19

PCIE5_RXP

D22

PCIE5_TXN

C22

PCIE5_TXP

G22

PCIE6_RXN

E22

PCIE6_RXP

B22

PCIE6_TXN

A23

PCIE6_TXP

L22

PCIE7_RXN

K22

PCIE7_RXP

C23

PCIE7_TXN

B23

PCIE7_TXP

K24

PCIE8_RXN

L24

PCIE8_RXP

C24

PCIE8_TXN

B24

PCIE8_TXP

SKY-H-PCH_BGA837

@

SKY-S-PCH_BGA837

DMI

USB 2.0

PCIe/USB 3

2 OF 12REV = 1.3

USB2N_1 USB2P_1 USB2N_2 USB2P_2 USB2N_3 USB2P_3 USB2N_4 USB2P_4 USB2N_5 USB2P_5 USB2N_6 USB2P_6 USB2N_7 USB2P_7 USB2N_8 USB2P_8 USB2N_9

USB2P_9 USB2N_10 USB2P_10 USB2N_11 USB2P_11 USB2N_12 USB2P_12 USB2N_13 USB2P_13 USB2N_14 USB2P_14

GPP_E9/USB2_OC0# GPP_E10/USB2_OC1# GPP_E11/USB2_OC2# GPP_E12/USB2_OC3#

GPP_F15/USB2_OCB_4 GPP_F16/USB2_OCB_5 GPP_F17/USB2_OCB_6 GPP_F18/USB2_OCB_7

USB2_COMP

USB2_VBUSSENSE

RSVD_AB13

USB2_ID

GPD7/RSVD

USB20_N1

AF5

USB20_P1

AG7

USB20_N2

AD5

USB20_P2

AD7

USB20_N3

AG8

USB20_P3

AG10

USB20_N4

AE1

USB20_P4

AE2 AC2 AC3

DVT1.0

AF2

Remove net USB20_N6/P6

AF3

USB20_N7

AB3

USB20_P7

AB2

USB20_N8

AL8

USB20_P8

AL7

USB20_N9

AA1

USB20_P9

AA2 AJ8 AJ7 W2 W3

USB20_N12

AD3

USB20_P12

AD2 V2 V1 AJ11 AJ13

USB_OC0#

AD43

USB_OC1#

AD42

USB_OC2#

AD39

USB_OC3#

AC44

USB_OC4#

Y43

USB_OC5#

Y41

USB_OC6#

W44

USB_OC7#

W43

USB2_COMP

AG3

USB2_VBUSSENSE

AD10 AB13

USB2_ID

AG2

BD14

USB20_N1 <31> USB20_P1 <3 1> USB20_N2 <32> USB20_P2 <3 2> USB20_N3 <32> USB20_P3 <3 2> USB20_N4 <28> USB20_P4 <2 8>

USB20_N7 <34> USB20_P7 <3 4> USB20_N8 <37> USB20_P8 <3 7> USB20_N9 <38> USB20_P9 <3 8>

USB20_N12 <38> USB20_P12 < 38>

USB_OC0# <31> USB_OC1# <32>

1 2

RH109 113_0402_1 %

1 2

RH112 1K_0402_5%

1 2

RH113 1K_0402_ 5%

Left USB Type-A

Right USB Type-A

Mini Card(WLAN)

Card Reader

Finger Print

Touch Screen

Camera

USB_OC3# USB_OC2# USB_OC1# USB_OC0#

USB_OC5# USB_OC4# USB_OC6# USB_OC7#

RP16

4 5 3 6 2 7 1 8

10K_0804_8P4R_5%

RP8

4 5 3 6 2 7 1 8

10K_0804_8P4R_5%

+3VALW

UH2F

C11

USB3_1_TXN

B11

USB3_1_TXP

B7

USB3_1_RXN

A7

USB3_1_RXP

B12

USB3_2_TXN/SSIC_1_TXN

A12

USB3_2_TXP/SSIC_1_TXP

C8

USB3_2_RXN/SSIC_1_RXN

B8

USB3_2_RXP/SSIC_1_RXP

B15

USB3_6_TXN

C15

USB3_6_TXP

K15

USB3_6_RXN

K13

USB3_6_RXP

B14

USB3_5_TXN

C14

USB3_5_TXP

G13

USB3_5_RXN

H13

USB3_5_RXP

D13

USB3_3_TXP/SSIC_2_TXP

C13

USB3_3_TXN/SSIC_2_TXN

A9

USB3_3_RXP/SSIC_2_RXP

B10

USB3_3_RXN/SSIC_2_RXN

B13

USB3_4_TXP

A14

USB3_4_TXN

G11

USB3_4_RXP

E11

USB3_4_RXN

SKY-H-PCH_BGA837

@

4

USB3TN1 USB3TP1 USB3RN1 USB3RP1

USB3TN2 USB3TP2 USB3RN2 USB3RP2

USB3TP3 USB3TN3 USB3RP3 USB3RN3

B B

Left USB Type-A

Right USB Type-A

A A

5

USB3TN1<31>

USB3TP1<31> USB3RN1<31> USB3RP1<31>

USB3TN2<32>

USB3TP2<32> USB3RN2<32> USB3RP2<32>

USB3TP3<32>

USB3TN3<32> USB3RP3<32> USB3RN3<32>

SKY-S-PCH_BGA837

LPC/eSPI

USB

SATA

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

GPP_A1/LAD0/ESPI_IO0 GPP_A2/LAD1/ESPI_IO1 GPP_A3/LAD2/ESPI_IO2 GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS#

GPP_A6/SERIRQ

GPP_A7/PIRQA#/ESPI_ALERT0#

GPP_A0/RCIN#/ESPI_ALERT1#

GPP_A14/SUS_STAT#/ESPI_RESET#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

GPP_A10/CLKOUT_LPC1

GPP_G19/SMI# GPP_G18/NMI#

GPP_E6/DEVSLP2 GPP_E5/DEVSLP1 GPP_E4/DEVSLP0 GPP_F9/DEVSLP7 GPP_F8/DEVSLP6 GPP_F7/DEVSLP5 GPP_F6/DEVSLP4 GPP_F5/DEVSLP3

6 OF 12REV = 1.3

2011/08/25 2012/07/25

3

AT22 AV22 AT19 BD16

BE16 BA17 AW17 AT17 BC18

BC17 AV19

M45 N43

AE45 AG43 AG42 AB39 AB36 AB43 AB42 AB41

PCH_ESPI_IO0 PCH_ESPI_IO1 PCH_ESPI_IO2 PCH_ESPI_IO3

ESPI_CS# ESPI_ALERT# PIRQA#

ESPI_RESET#

PCH_ESPI_CLK

HDD_DEVSLP mSATA_DEVSLP

RH574 15_0402_5% RH575 15_0402_5% RH576 15_0402_5% RH577 15_0402_5%

RH168

Compal Secret Data

Deciphered Date

1 2 1 2 1 2 1 2

ESPI_CS# <36> ESPI_ALERT# <36 >

ESPI_RESET# < 36>

1 2

22_0402_5%EMI@

HDD_DEVSLP <29> mSATA_DEVSLP < 29>

ESPI_CLK

2

ESPI_IO0 <36> ESPI_IO1 <36> ESPI_IO2 <36> ESPI_IO3 <36>

PIRQA#

ESPI_ALERT#

ESPI_CLK <36>

1 2

RH546 10K_0402_5%

1 2

RH578 8.2K_0402_5%

Reserve for EMI

ESPI_CLK

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

PCH (4/8) PCI, USB

12

CC4

@EMI@ 12P_0402_50V8J

LA-E992P

1

+1.8V_PRIM

19 77Tuesday, July 25, 2017

1.0(A00)

of

5

4

3

2

1

D D

C C

B B

+3VS

1 2

RH10 10K_0402_5%

1 2

RH159 49.9K_0402_1%

1 2

RH160 49.9K_0402_1%

1 2

RH119 2.2K_0402_5%

1 2

RH120 2.2K_0402_5%

1 2

RH545 100K_0402_5%

+3VALW

1 2

RH91 10K_0402_5%

1 2

RZ96 100K_0402_5%

1 2

RH567 100K_0402_5%

Reserve for N17E HDMI HPD.

+3VS

12

@

RH547

10K_0402_5%

12

@

RH548

10K_0402_5%

@

RH549 10K_0402_5%

@

RH550 10K_0402_5%

SIO_EXT_SCI# UART_2_CTXD_DRXD UART_2_CRXD_DTXD I2C1_SCK_TP I2C1_SDA_TP GPU_GC6_FB_EN_H

SIO_EXT_WAKE# IR_CAM_DET#

HDMI_HPD_PCH

PHASE_ID1 PHASE_ID2

GPU_GC6_FB_EN_H<46>

GPU_EVENT#<46>

BT_RADIO_DIS#< 28>

HDMI_HPD_PCH<44>

SIO_EXT_WAKE#<36>

UART_2_CTXD_DRXD<28>

UART_2_CRXD_DTXD<28>

I2C1_SCK_TP<26> I2C1_SDA_TP<26>

RH548

EVT@

10K_0402_5%

SD028100280

RH547

DVT1@

10K_0402_5%

SD028100280

RH548

DVT2@

FFS_INT1<29>

RH550

EVT@

10K_0402_5%

SD028100280

RH550

DVT1@

10K_0402_5%

SD028100280

RH549

DVT2@

BBS_BIT0

SIO_EXT_SCI# FFS_INT1

NRB_BIT

GPU_GC6_FB_EN_H

HDMI_HPD_PCH PHASE_ID2 PHASE_ID1

IR_CAM_DET# SIO_EXT_WAKE#

I2C1_SCK_TP I2C1_SDA_TP

UH2K

AT29

GPP_B22/GSPI1_MOSI

AR29

GPP_B21/GSPI1_MISO

AV29

GPP_B20/GSPI1_CLK

BC27

GPP_B19/GSPI1_CS#

BD28

GPP_B18/GSPI0_MOSI

BD27

GPP_B17/GSPI0_MISO

AW27

GPP_B16/GSPI0_CLK

AR24

GPP_B15/GSPI0_CS#

AV44

GPP_C9/UART0_TXD

BA41

GPP_C8/UART0_RXD

AU44

GPP_C11/UART0_CTS#

AV43

GPP_C10/UART0_RTS#

AU41

GPP_C15/UART1_CTS#/ISH_UART1_CTS#

AT44

GPP_C14/UART1_RTS#/ISH_UART1_RTS#

AT43

GPP_C13/UART1_TXD/ISH_UART1_TXD

AU43

GPP_C12/UART1_RXD/ISH_UART1_RXD

AN43

GPP_C23/UART2_CTS#

AN44

GPP_C22/UART2_RTS#

AR39

GPP_C21/UART2_TXD

AR45

GPP_C20/UART2_RXD

AR41

GPP_C19/I2C1_SCL

AR44

GPP_C18/I2C1_SDA

AR38

GPP_C17/I2C0_SCL

AT42

GPP_C16/I2C0_SDA

AM44

GPP_D4/ISH_I2C2_SDA

AJ44

GPP_D23/ISH_I2C2_SCL

SKY-H-PCH_BGA837

@

SKY-S-PCH_BGA837

11 OF 12REV = 1.3

GPP_D9 GPP_D10 GPP_D11

GPP_D16/ISH_UART0_CTS# GPP_D15/ISH_UART0_RTS#

GPP_D14/ISH_UART0_TXD GPP_D13/ISH_UART0_RXD

GPP_D12

GPP_H20/ISH_I2C0_SCL GPP_H19/ISH_I2C0_SDA

GPP_H22/ISH_I2C1_SCL GPP_H21/ISH_I2C1_SDA

GPP_A23/ISH_GP5 GPP_A22/ISH_GP4 GPP_A21/ISH_GP3 GPP_A20/ISH_GP2 GPP_A19/ISH_GP1 GPP_A18/ISH_GP0 GPP_A17/ISH_GP7

AL44 AL36 AL35 AJ39

AJ43 AL43 AK44 AK45

BC38 BB38

BD38 BE39

BC22 BD18 BE21 BD22 BD21 BB22 BC19

KB_DET#

DGPU_HOLD_RST# < 46> WLAN_WIGIG60GHZ_DIS# <28> DGPU_PWR_EN <55>

KB_DET# <25>

DGPU_PWR_EN

KB_DET#

1 2

RH129 10K_0402_5%

1 2

RH127 10K_0402_5%@

1 2

RH128 10K_0402_5%

+3VS

+1.8V_PRIM

+3VALW +3VALW

1 2

RH130 2.2K_0402_5%@

BBS_BIT0

Boot BIOS Strap Bit (internal PD) HIGH

LOW(DEFAULT)

Compal Secret Data

Deciphered Date

2

LPC SPI

1 2

RH92 2.2K_0402_5%@

NRB_BIT

NO REBOOT mode (internal PD)

HIGH LOW(DEFAULT)

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

PCH (5/8) GPIO, CPU, MISC

LA-E992P

ENABLE DISABLE

1.0(A00)

of

20 77Tuesday, July 25, 2017

1

20 77Tuesday, July 25, 2017

PILOT@

10K_0402_5%

SD028100280

RH549

PILOT@

10K_0402_5%

SD028100280

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/08/25 2012/07/25

10K_0402_5%

PHASE ID

A A

EVT DVT1 DVT2 Pilot

PHASE ID2 PHASE ID1 (GPP_C13) (GPP_C12)

0 0 1 1

5

0 1 0 1

SD028100280

RH547

10K_0402_5%

SD028100280

5

4

3

2

1

@

PJP1302

1 2

PAD-OPEN 43x39

1 2

D D

C C

B B

RZ70 0_0805_5%@

DVT2.0 Change RZ70 to 0ohm 0805 short-pad footprint.

1 2

@

RH137 0_0603_5%

1 2

@

RH196 0_0402_5%

+1VALW

1 2

@

RH124 0_0603_5%

+1VALW

1 2

@

RH123 0_0603_5%

+1VALW

1 2

LH2 BLM15PX221SN1D_2P

1 2

LH1 BLM15PX221SN1D_2P

1 2

@

RH122 0_0603_5%

DVT2.0 Change RH137, RH124, RH123, RH122 to 0ohm 0603 short-pad footprint.

+1V_PCH_CLK5

Close to K2,K3 Close to A43,B43 Close to U21,U23

22U_0603_6.3V6M

1

CH177

2

+1V_MPHY_MPHYPLL +1V_PCH_USBPLL

1U_0402_6.3V6K

22U_0603_6.3V6M

CH179

1

CH178

@

2

+1V_PCH+1VALW

+1V_MPHY

+3V_PCH_DSW+3VALW

+1V_VCCDSW+1V_PCH_PRIM

+1V_MPHY_MPHYPLL

+1V_PCH_USBPLL

+1V_PCH_AZPLL

+3V_PCH_AZIO+3VALW

+1V_PCH_CLK5+1VALW

22U_0603_6.3V6M

1

CH181

@

2

Close to AN19

1

2

SKY-S-PCH_BGA837

CORE

MPHY

USB

8 OF 12 REV = 1.3

VCCGPIO

+1V_VCCDSW

Close to BA29

1U_0402_6.3V6K

1

2

VCCPRIM_1P0_AL22

VCCDSW_3P3_BA24

VCCPGPPBH_BC42 VCCPGPPBH_BD40

VCCPGPPEF_AJ41

VCCPGPPEF_AL41

VCCPRIM_3P3_AN5

VCCPRIM_1P0_AD15

VCCRTCPRIM_3P3

VCCPRIM_1P0_AJ20 VCCPRIM_1P0_AJ21 VCCPRIM_1P0_AJ23 VCCPRIM_1P0_AJ25

VCCPGPPCD_BC44 VCCPGPPCD_BA45 VCCPGPPCD_BC45 VCCPGPPCD_BB45

VCCPRIM_3P3_BD3 VCCPRIM_3P3_BE3 VCCPRIM_3P3_BE4

CH176

VCCPGPPA

VCCPGPPG

VCCATS

VCCRTC DCPRTC

VCCSPI_BE41 VCCSPI_BE43 VCCSPI_BE42

AL22

BA24

BA31

BC42 BD40 AJ41 AL41 AD41 AN5

AD15 AD13 BA20 BA22 BA26

AJ20 AJ21 AJ23 AJ25

BE41 BE43 BE42

BC44 BA45 BC45 BB45

BD3 BE3 BE4

+3V_PCH_AZIO

0.1U_0402_10V6K

CH200

1

2

+1V_PCH_PRIM

+3V_PCH_SPI

Close to BA15

+DCPRTC

0.0908A

0.92089A

0.0061A

0.0066A

0.0002A

0.0395A

0.0811A

0.403A

+1V_PCH_PRIM

DVT2.0 Change RH493 to 0ohm 0603 short-pad footprint.

+1V_PCH

+3V_PCH_DSW

+1.8V_PRIM

eSPI need use +1.8V_PRIM

+3VALW

+1V_PCH +3VS +3VALW

+RTCVCC +DCPRTC

+3VALW

Close to BA26

0.1U_0402_10V6K

CH70

1

2

@

12

Close to AD13

1

2

2.75835A

RH4930_060 3_5%

1U_0402_6.3V6K

CH188

+3VALW

0.0121A

@

PJP1303

+1V_VCCDSW

+1V_PCH

+1V_PCH_CLK5

+1V_MPHY

+1V_APLLEBB

+1V_PCH

+1V_PCH_AZPLL

+3V_HDA

+3V_PCH_DSW

+1V_PCH_PRIM

0.0454A

0.0046A

0.0248A

0.075A

1 2

PAD-OPEN 43x39

0.0348A

3.53A

+1V_MPHY_MPHYPLL

0.095A

0.533A

+1V_PCH_USBPLL

2.75835A

+1VALW

+1V_MPHY +3VS

Close to AJ5,AL5

1U_0402_6.3V6K

22U_0603_6.3V6M

CH180

1

CH182

2

10U_0402_6.3V6M

CH185

1

2

1U_0402_6.3V6K

CH184

1

2

CH183

1

2

22U_0603_6.3V6M

1

CH201

@

2

CH202

@

2

UH2H

AA23

VCCPRIM_1P0_AA23

AA26

VCCPRIM_1P0_AA26

AA28

VCCPRIM_1P0_AA28

AC23

VCCPRIM_1P0_AC23

AC26

VCCPRIM_1P0_AC26

AC28

VCCPRIM_1P0_AC28

AE23

VCCPRIM_1P0_AE23

AE26

VCCPRIM_1P0_AE26

Y23

VCCPRIM_1P0_Y23

Y25

VCCPRIM_1P0_Y25

BA29

DCPDSW_1P0

N17

VCCCLK1

R19

VCCCLK3

U20

VCCCLK4

V17

VCCCLK2

R17

VCCCLK6

K2

VCCCLK5_K2

K3

VCCCLK5_K3

U21

VCCMPHY_1P0_U21

U23

VCCMPHY_1P0_U23

U25

VCCMPHY_1P0_U25

U26

VCCMPHY_1P0_U26

V26

VCCMPHY_1P0_V26

A43

VCCMPHYPLL_1P0_A43

B43

VCCMPHYPLL_1P0_B43

C44

VCCPCIE3PLL_1P0_C44

C45

VCCPCIE3PLL_1P0_C45

V28

VCCAPLLEBB_1P0

AC17

VCCPRIM_1P0_AC17

AJ5

VCCUSB2PLL_1P0_AJ5

AL5

VCCUSB2PLL_1P0_AL5

AN19

VCCHDAPLL_1P0

BA15

VCCHDA

W15

VCCDSW_3P3_W15

SKY-H-PCH_BGA837

@

+1V_PCH_AZPLL

0.1U_0402_10V6K

CH203

RF@

+1V_MPHY

RH544 0_0402_5%

CH213

0.5P_0402_50V8C

1

DVT2.0 Change RH544 to 0ohm 0402 short-pad footprint.

2

1 2

@

+1V_APLLEBB

CH214

1

RF@

2

+3V_PCH_DSW

Close to W15

0.5P_0402_50V8C

0.1U_0402_10V7K

1

CH190

@

2

1U_0402_6.3V6K

CH82

1

@

2

+3VALW+3VALW +3VALW+3VALW

Close to AN5Close to AD41 Close to AJ41,AL41Close to BC42,BD40

0.1U_0402_10V7K

1

CH189

@

2

0.1U_0402_10V7K

1

CH192

@

2

0.1U_0402_10V7K

1

CH191

@

2

+RTCVCC

Close to BA22 Close to BA20

0.1U_0402_10V6K

1U_0402_6.3V6K

CH173

CH80

1

2

+3VALW

+3V_PCH_AZIO +3V_HDA

1 2

@

0.1U_0402_10V6K

1U_0402_6.3V6K

CH186

CH187

1

2

DVT2.0 Change RH543 to 0ohm 0402 short-pad footprint.

2

RH543 0_0402_5%

Close to BA15 Close to V28

A A

Security Classification

2011/08/25 2012/07/25

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/08/25 2012/07/25

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet

Compal Electronics, Inc.

PCH (6/8) PWR

LA-E992P

1.0(A00)

of

21 77Tuesday, July 25, 2017

1

5

4

3

2

1

C42 D10 D12 D15 D16 D17 D19 D21 D24 D25 D27 D29 D30 D31 D33 D35 D36 E13 E15 E31 E33

G42

H17 H19 H22 H24 H27 H29

H35

U10 U11 U14 U17 U18 U28 U29 U31 U32 U33 U38

V18 V20 V21 V23 V25 V29

V45 W14 W31 W32 W33 W38

Y17

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

F44

VSS

F8

VSS VSS

G9

VSS VSS VSS VSS VSS VSS VSS

H3

VSS VSS

J10

VSS

J11

VSS

J3

VSS

J39

VSS

J5

VSS

T42

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

U4

VSS

U8

VSS VSS VSS VSS VSS VSS VSS

V3

VSS VSS VSS VSS VSS VSS VSS

W4

VSS

W8

VSS VSS

@

SKY-S-PCH_BGA837

UH2L

SKY-H-PCH_BGA837

12 OF 12 REV = 1.3

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AB11 AB7 AB14 AB31 AB32 AB38 AB4 AB5 AC1 AC20 AC21 AC25 AC29 AC45 AB8 AD11 AD14 AB15 AD32 AD33 AD36 AD4 AD8 AE18 AE20 AE21 AE25 AE28 AL10 AL11 AL13 AL17 AL19 AL24 AL29 AL32 AL33 AL38 AM15 AM17 AM19 AM22 AM24 AM27 AM29 AM45 AN11 AN22 AN27 AN31 AN39 AN7 AN8 AP11 AP4 AR33 AR34 AR42 AR9 AT10 AT15 AT36 AT9 AU1 AU35 AU36 AU39 AU45 C4

BD2 BD45 BD44

BE44

D45

BB1

BC1

A42 B45 B44

A44

A4 A3 B2 A2 B1

C1 D1

@

UH2J

VSS_BD2 VSS_BD45 VSS_BD44 VSS_BE44 VSS_D45 VSS_A42 VSS_B45 VSS_B44 VSS_A4 VSS_A3 VSS_B2 VSS_A2 VSS_B1 VSS_BB1 VSS_BC1 VSS_A44

RSVD_C1 RSVD_D1

SKY-H-PCH_BGA837

SKY-S-PCH_BGA837

PCH_TRIGOUT

RSVD_AR22

RSVD_W13

RSVD_U13

RSVD_P31 RSVD_N31

RSVD_P27 RSVD_R27 RSVD_N29 RSVD_P29

RSVD_AN29

RSVD_R24 RSVD_P24

PREQ#

PRDY#

CPU_TRST#

PCH_TRIGIN

10 OF 12REV = 1.3

AR22 W13 U13

P31 N31

P27 R27 N29 P29 AN29 R24 P24

AT3 AT4 AY5 AL2 AK1

XDP_PREQ# <6,9> XDP_PRDY# <6,9> CPU_XDP_TRST# <6 ,9> PCH_TRIGGER <9> CPU_TRIGGER <9>

UH2I

SKY-S-PCH_BGA837

AC18

VSS

AN4

VSS

AN10

VSS

D D

C C

B B

BE14 BE18 BE23 BE28 BE32 BE37 BE40

BE9 C10

C28 C37

K10 K27 K33 K36

K42 K43

M35 M42

N10 N15 N19 N22 N24 N35 N36

N41

P17 P19 P22 P45 R10 R14 R22 R29 R33 R38

Y18 Y20 Y21 Y26 Y28 Y29 A18 A25 A32

A37 AA17 AA18 AA20 AA21 AA25 AA29

AA4 AA42 AB10

C2

J7

K4

L12 L13 L15

L4

L41

L8

N4

N5

R5 T1 T2 T4

@

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

SKY-H-PCH_BGA837

AR5

VSS

AR7

VSS

U15

VSS

AL4

VSS

AE29

VSS

AE4

VSS

AE42

VSS

AF18

VSS

AF20

VSS

AF21

VSS

AF23

VSS

AF25

VSS

AF26

VSS

AF28

VSS

AF29

VSS

AG11

VSS

AG13

VSS

AG31

VSS

AG32

VSS

AG33

VSS

AG38

VSS

AG4

VSS

AH1

VSS

AH17

VSS

AH18

VSS

AH20

VSS

AH21

VSS

AH23

VSS

AH25

VSS

AH26

VSS

AH28

VSS

AH29

VSS

AH45

VSS

AJ10

VSS

AJ14

VSS

AJ15

VSS

AJ17

VSS

AJ18

VSS

AJ26

VSS

AJ28

VSS

AJ29

VSS

AJ31

VSS

AJ32

VSS

AJ36

VSS

AK4

VSS

AK42

VSS

AU7

VSS

AV17

VSS

AV24

VSS

AV27

VSS

AV31

VSS

AV33

VSS

AV6

VSS

AW13

VSS

AW19

VSS

AW29

VSS

AW37

VSS

AW9

VSS

AY38

VSS

AY45

VSS

B25

VSS

B3

VSS

B37

VSS

B40

VSS

B6

VSS

BA1

VSS

BB11

VSS

BB16

VSS

BB21

VSS

BB25

VSS

BB30

VSS

BB34

VSS

BC2

VSS

BD43

VSS

9 OF 12REV = 1.3

A A

Security Classification

2011/08/25 2012/07/25

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/08/25 2012/07/25

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet

Compal Electronics, Inc.

PCH (8/8) VSS

LA-E992P

22 77Tuesday, July 25, 2017

1

1.0(A00)

of

5

4

3

2

1

Main Func = Audio

Pilot Change RA1 to 0ohm 0402 short-pad footprint.

+1.8V_PRIM

LN2306LT1G_SOT23-3

DVT2.0

D D

Reserve RA58

DVT2.0 Pop CA7, UA1, RA2, CA10, CA4,RA57

+1.8V_DVDD

Pilot Change RA57 to 0ohm 0603 short-pad footprint.

+3VS +3V_DVDD

C C

+3VS

RA5

1 2

@

0_0402_5%

25mA

QA1

1 3

D

2

0_0603_5%

G

RA57

RA58

S

@

12

4.7U_0603_6.3V6K

1

2

12

@

0_0603_5%

5

+1.8VS

1U_0402_6.3V6K

4

CA7

1

2

CA8

G9090-180T11U_SOT23-5

Pilot

Change RA5 to 0ohm 0402

short-pad footprint.

1

CA9

0.1U_0402_10V6K

Close pin9

2

UA1

VOUT

NC

SA00004Z400

Speaker trace width >40mil @ 2W4ohm speaker power

B B

DMIC_CLK<38>

47P_0402_50V8J

Reserve for RF

Close pin3

@RF@

CA30

1

2

DVT 2.0 EMI request change LA1 to 470 ohm bead to depress EMI rediation.

RA1 0_0402_5%@

1

CA3

0.1U_0402_10V6K

Close pin36

2

VIN

GND

EN

Layout Note:

EC_MUTE#<36>

1 2

BLM15PX471SN1D_2P

moat

1 2

1

2

3

AUD_AGND

+3V_DVDD

LA1

EMI@

CA1

4.7U_0603_6.3V6K

+1.8V_AVDD+1.8V_DVDD

1

CA2

0.1U_0402_10V6K

2

AUD_AGND

+3VS

1 2

AUD_SPK_L+<24>

AUD_SPK_L-<24>

AUD_SPK_R-<24>

AUD_SPK_R+<24>

@

DMIC_DATA_R

@

HDA_SDOUT_AUDIO<18>

HDA_BITCLK_AUDIO<18>

HDA_SDIN0_AUDIO<18>

HDA_SYNC_AUDIO<18>

1U_0402_6.3V6K

CA4

1

2

1

2

12

RA2

10K_0402_5%

CA10

0.22U_0603_25V7K

1 2

CA22 10U_0603_6.3V6M

CA63 10U_0603_6.3V6M

1 2

RA23 100K_0402_5%

DMIC_DAT<38>

LINE1_VREFO_R<24>

LINE1_VREFO_L<24>

AUD_HP1_JACK_L<24>

AUD_HP1_JACK_R<24>

2

CA20 1U_0603_10V6K

1

LDO2_CAP

+1.8V_AVDD

+5V_PVDD

CA62 10P_0402_25V8J

DVT 1.0 Change RA27 to 33 ohm.

1 2

RA27 33_0402_5%

RA32

CBN

CBP

+1.8V_DVDD

HDA1

37

CBP

38

AVSS2

39

LDO2-CAP

40

AVDD2

41

PVDD1

42

SPK-OUT-L+

43

SPK-OUT-L-

44

SPK-OUT-R-

45

SPK-OUT-R+

46

PVDD2

47

PDB

48

SPDIF-OUT/GPIO2

49

GND

+3V_DVDD

1

CA25

2

1 2

33_0402_5%

1

@RF@

CA66 10P_0402_25V8J

2

CA15 1U_0603_10V6K

1 2

CPVEE

34

35

36

CBN

CPVEE

CPVDD

DVDD1GPIO0/DMIC-DATA2GPIO1/DMIC-CLK3EAPD/DC DET4SDATA-OUT5BCLK6LDO3-CAP7SDATA-IN8DVDD-IO9SYNC

4.7U_0603_6.3V6K

CA26

1

2

0.1U_0402_10V6K

DMIC_DATA_R

DMIC_CLK_R

HDA_SDOUT_AUDIO

HDA_BITCLK_AUDIO

HDA_CODEC_SDIN0

HDA_SYNC_AUDIO

31

32

33

LINE1-VREFO-L

HPOUT-L/PORT-I-L

HPOUT-R/PORT-I-R

ALC3246-CG-GP

SA00008GJ00

4.7U_0603_6.3V6K

2.2U_0402_6.3V6M

CA16

CA19

1

2

LDO1_CAP

26

27

28

29

30

VREF

AVDD1

LDO1-CAP

MIC2-VREFO

LINE1-VREFO-R

MIC2_R/SLEEVE

MIC2_L/RING2

SPDIFO/FRONT_JD/JD3/GPIO3

MIC2/LINE2_JD/JD2

HP/LINE1_JD/JD1

I2C_SDA

10

11

CA280.1U_0402_10V6K

CA274.7U_0603_6.3V6K

LDO3_CAP

1

2

12

RA11 100K_0402_5%

25

AVSS1

LINE2_L

LINE2_R

LINE1_L

LINE1_R

5/3D3VSTB

MIC-CAP

MONO-OUT

I2C_SCL

12

+3V_DVDD

AUD_AGND

+5V_AVDD

AUD_AGND

24

23

22

21

20

19

18

17

16

15

14

13

MIC2_VREFO <24>

LINE1_L <24>

LINE1_R <24>

SLEEVE <24>

RING2 <24>

AUD_SENSE_A

SPKR<18>

BEEP<36>

1 2

CA23 10U_0402_6.3V6M

1 2

RA19 0_0402_5%@

DVT2.0 Change RA19 to 0ohm 0402 short-pad footprint.

1 2

RA22

200K_0402_5%

Place close to Pin 13

3

2

Reserve for RF

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2015/07/15 2016/07/31

Compal Secret Data

Deciphered Date

Pilot Change RA7, RA10 to 0ohm 0805 short-pad footprint.

+5VS +5V_PVDD

1.5A

1 2

@

RA7 0_0805_5%

1 2

@

RA10 0_0805_5%

moat

RA8

Pilot Change RA8 to 0ohm 0603 short-pad footprint.

0_0603_5%

@

12

4.7U_0603_6.3V6K

CA18

moat

1 2

RA17 0_0402_5%@

1 2

RA18 0_0402_5%

AUD_AGND

Width>40mil, to improve Headpohone Crosstalk noise

Layout Note:

AUD_SENSE

Change it to sharp will be better. Add 2 vias (>0.5A) when trace layer change.

AUD_PC_BEEP

AUD_SENSE <24>

moat

D1

AUD_PC_BEEP_C

1

BAT54C-7-F_SOT23-3

1 2

RA30 1K_0402_5%

+3VS To +1.8V_DVDD

Pilot Change RA9, RA12, RA13, RA14, RA15 to 0ohm 0402 short-pad footprint.

Pilot Change RA16 to 0ohm 0805 short-pad footprint.

2

5V_PVDD trace width > 40mil.

CA11

1

2

10U_0603_6.3V6M~D

+5V_AVDD

1

2

AUD_AGND

+3VALW

1

2

1

2

CA12

0.1U_0402_10V6K

CA17

0.1U_0402_10V6K

Place close to Pin 26

+RTCVCC

12

CA14

CA13

1

2

0.1U_0402_10V6K

10U_0603_6.3V6M~D

Close pin46Close pin41

Pop RA18 to prevent "zizi" noise on G3 or DC S5/S4.

AUD_SENSE_A

1

CA24

0.1U_0402_10V6K

CA29

1 2

0.1U_0402_10V6K

RA33 10K_0402_5%

2

AUD_AGND

AUD_PC_BEEP

RA24

moat

+3V_DVDD

12

100K_0402_5%

moat

1 2

RA9 0_0402_5%@

1 2

RA12 0_0402_5%@

1 2

RA13 0_0402_5%@

1 2

RA14 0_0402_5%@

1 2

RA15 0_0402_5%@

AUD_AGND

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

1 2

RA16 0_0805_5%@

CODEC ALC3246

LA-E992P

1

23 77Tuesday, July 25, 2017

1.0(A00)

5

Main Func = Audio

4

3

2

1

Layout Note:

Speaker trace width >40mil @ 2W4ohm speaker power

2

1

3

LA19 BLM15PX330SN1D 0402ESD@ LA20 BLM15AX700SN1D_2PEMI@

LA21 BLM15AX700SN1D_2PEMI@ LA22 BLM15PX330SN1D 0402ESD@

AUD_SPK_R+_C AUD_SPK_R-_C AUD_SPK_L+_C AUD_SPK_L-_C

DA2

AZ5125-02S.R7G_SOT23-3

1 2 1 2

ESD@

2

3

DA3

1

AZ5125-02S.R7G_SOT23-3

1 2

D D

C C

AUD_SPK_R+<23> AUD_SPK_R-<23> AUD_SPK_L+<23> AUD_SPK_L-<23>

MIC2_VREFO<23>

RING2<23> AUD_HP1_JACK_L<23> LINE1_L<23> LINE1_VREFO_L<23>

AUD_HP1_JACK_R<23> LINE1_R<23> LINE1_VREFO_R<23>

SLEEVE<23>

LA23 BLM15PX181SN1D_2PEMI@

1 2

LA24 BLM15PX181SN1D_2PEMI@

1 2

LA25 BLM15PX181SN1D_2PEMI@

1 2

LA26 BLM15PX181SN1D_2PEMI@

RA42 2.2K_0402_5% RA43 2.2K_0402_5%

LINE1-L_C

1 2

CA64 10U_0603_6.3V6M~D

LINE1-L_R

1 2

CA65 10U_0603_6.3V6M~D

EMI@

CA36

CA37

1

2

1000P_0402_50V7K

1 2 1 2

1 2

RA44 10_0402_1%

1 2

RA48 1K_0402_5%

1 2

RA46 4.7K_0402_5%

1 2

RA49 10_0402_1%

1 2

RA51 1K_0402_5%

1 2

RA53 4.7K_0402_5%

EMI@

CA38

1

2

1000P_0402_50V7K

AUD_HP1_JACK_L1

AUD_HP1_JACK_R1

EMI@

CA39

1

2

ESD@

1000P_0402_50V7K

Close to HDA1

Universal Jack

3

1

RING2_R AUD_PORTA_L_R_B

JACK_PLUG AUD_PORTA_R_R_B SLEEVE_R

ESD@

2

DA4

moat

SLEEVE_R AUD_PORTA_R_R_B

JACK_PLUG

AUD_PORTA_L_R_B RING2_R

RING2_R

AUD_PORTA_L_R_B

B B

AUD_SENSE<23>

DVT2.0 Change RA56 to 0ohm 0402 short-pad footprint.

RA56

0_0402_5%

JACK_PLUG

12

@

AUD_PORTA_R_R_B SLEEVE_R

680P_0402_50V7K

1

ESD@

CA42

2

AUD_AGND AUD_AGND AUD_AGND AUD_ AGND

Pilot Change connect CA42.2, CA43.2, CA60.2, CA61.2 from GND to AGND. Change CA60, CA61 BS from EMI@ to @EMI@ reserve for EMI.

ESD@

CA43

1

2

CA60

@EMI@

1

2

33P_0402_50V8J

CA61

@EMI@

1

33P_0402_50V8J

2

ESD@

DA6

2

3

1

TVNST52302AB0_SOT523-3

ESD@

2

3

DA5

1

L03ESDL5V0CC3-2_SOT23-3

AZ5123-02S.R7G_SOT23-3

Need to check Speaker pin define

Speaker

EMI@

CA40

AUD_AGND

JSPK1

1

2

3

4

5

GND

6

GND

ACES_50278-0040N-001

CONN@

SP02001CE00

680P_0402_50V7K

1

2

AUD_AGND

JHP1

3

#3 M/G

2

#2 R

6

#6 AGND

5

#5

1

#1 L

4

#4 G/M

7

GND

SINGA_2SJ3095-106111F

CONN@

DC23000FV00

1

2

CONN Pin

Pin1

Pin2

Pin3

Pin4

RING2_R AUD_PORTA_L_R_B

AUD_PORTA_R_R_B SLEEVE_R

680P_0402_50V7K

Pilot

EMI@

Change CA40, CA41 from 100p

CA41

0402 to 680p 0402 and pop for EMI(EMI@).

Net name

SPK_R+

SPK_R-

SPK_L+

SPK_L-

SINGA_2SJ3095-106111F

A A

10 mils10 mils

Security Classification

2015/07/15 2016/07/31

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2015/07/15 2016/07/31

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet

Compal Electronics, Inc.

SPKR/JACK

LA-E992P

1

1.0(A00)

of

24 77Tuesday, July 25, 2017

5

4

3

2

1

Fuse for Backlight

D D

C C

+5VS

20mil

2 1

F1

0.5A_13.2V_NANOSMDC050F-13.2-2

1

CE5 1U_0402_6.3V6K

2

+5VS_KBL

1

CE6 10U_0603_6.3V6M~D

2

Connector for Keyboard

KSI[0..7] <36>

JKB1

32 31

B B

30

GND

29

KSI7

29

GND

28

KSI6

28

27

KSI4

27

26

KSI2

26

25

KSI5

25

24

KSI1

24

23

KSI3

23

22

KSI0

22

21

KSO5

21

20

KSO4

20

19

KSO7

19

18

KSO6

18

17

KSO8

17

16

KSO3

16

15

KSO1

15

14

KSO2

14

13

KSO0

13

12

KSO12

12

11

KSO16

11

10

KSO15

10

9

KSO13

9

8

KSO14

8

7

KSO9

7

6

KSO11

6

5

KSO10

5

CAP_LED

4

3

2

1

ACES_50699-03001-P01_30P

ACES_50699-03001-P01

CONN@

SP01001LM00

KSO[0..16] <36>

KB_DET# <20>

DMG2301U-7_SOT23-3

CAP_LED_R

12

RE2 240_0402_1%

QE4

1 3

D

G

2

1

CE1

0.1U_0402_10V7K~D

@

2

+3VS+5VS+5VS

S

RE1

100K_0402_5%

1 2

L2N7002WT1G_SC-70-3 QE3

2

1 3

D

G

S

Connector for Keyboard Backlight Lid Switch

+3VALW

1

CE18

2

Pilot Change UE3 from SA00009CB00 TCS40DLR to SA0000AO500 YB8251PST23

KB_BL_DET<16>

KB_LED_PWM<36>

Current limited 20mA

1 2

RE3 47K_0402_5%

RE4

100K_0402_1%

KB_LED_PWM

1 2

2

G

KB_LED_PWM#

13

D

QE5

L2N7002WT1G_SC-70-3

S

+5VS_KBL

JBL1

1

2

3

G1

4

ACES_51575-00401-001

CONN@

SP01002BY00

G2

LED Maximum Current is 273mA

1U_0402_6.3V6K

1

CE4

5 6

2

.1U_0402_16V7K

Connector for Touch Finger Print module. (Cancel)

+3VS

RE120

100K_0402_5%

1 2

CAP_LED# <36>

DVT1.0 Change net CAPS_LED# to CAP_LED#

DVT1.0 Remove Finger print connector and component.

CE17

10P_0402_25V8J

LID_CLOSE# <36>

1

3

2

UE3

VCC

2

VOUT

GND

YB8251PST23_PSOT23_3P

1

TCS40DLR_SOT23F3

SA0000AO500

DVT1.0 Change to symbol ACES_50699-03001-P01

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/06/02 2013/10/28

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet

Compal Electronics, Inc.

KB/Lid/Finger Print

LA-E992P

1

1.0(A00)

of

25 77Tuesday, July 25, 2017

5

4

3

2

1

Touch pad

+3VALW

RZ32

D D

TP_EN#<36>

C C

B B

A A

I2C1_SDA_TP<20>

I2C1_SCK_TP<20>

PTP_INT#<17,36>

PTP_DIS#_R<36>

DAT_TP_SIO<36>

CLK_TP_SIO<36>

100K_0402_5%

1 2

DMN65D8LDW-7_SOT363-6

5

QE19B

DMN65D8LDW-7_SOT363-6

+3VS_TP

2

G

1 3

D

S

QE13 L2N7002WT1G_SC-70-3

+3VS_TP

12

RE123

100K_0402_5%

PTP_INT#_R PTP_DIS#_R DAT_TP_SIO CLK_TP_SIO

22P_0402_50V8J

UE4

5

IN

4

EN

SY6288D20AAC_SOT23-5

SA00007AO00

+3VS

2

34

12

RE87 100K_0402_5%

PTP_INT#_R

I2C1_SDA_TP_C I2C1_SCK_TP_C

@

CE9

@

CE10

22P_0402_50V8J

1

2

QE19A

+3VS_TP_OUT

1

OUT

2

GND

3

OCB

DVT2.0 Change RE9, RE7 to 1.5K 0402.

1.5K_0402_5%

SD028150180

61

I2C1_SDA_TP_C

I2C1_SCK_TP_C

SE074271K80

CE80

270P_0402_50V7K

1

2

Pilot Change RE93 to 0603 0ohm short-pad footprint.

1 2

RE93 0_0603_5%@

12

@

100K_0402_5% RZ33

+3VS_TP

RE7

1.5K_0402_5%

SD028150180

1 2

I2C1_SDA_TP_C

I2C1_SCK_TP_C

3

I/O2

2

GND

1

I/O1

AZC099-04S.R7G_SOT23-6

270P_0402_50V7K

RE9

+3VS_TP

CE105

+3VS_TP

1

CE2

0.1U_0402_10V6K

2

DE4

6

I/O4

5

VDD

4

I/O3

ESD@

JTP

8

7 6 5 4 3 2 1

10

7

G2

9

6

G1 5 4 3 2 1

ACES_51524-0080N-001

CONN@

SP01001A900

DAT_TP_SIO

+3VS_TP

CLK_TP_SIO FAN1_PWM_OUT

RTC Battery non- Charge Function

W=20mils

+3VLP +CHGRTC

@

PJP1304

2

112

JUMP_43X39

DVT1.0 Change DC2 to SCS00003800.

DC2

12

2

1

3

BAT54CW_SOT323-3

BAT54CW-7-F_SOT323-3

SCS00003800

+RTCVCC

W=20mils

1

2

+RTCBATT

W=20mils

RC11

1K_0402_5%

+CHGRTC

W=20mils

PWM FAN

+5VS+3VS

12

@

RE121

10K_0402_5%

FAN1_PWM<36>

RE122

10K_0402_5%

FAN2_PWM<36>

S

12

@

S

12

RE100

@

G

2

L2N7002LT1G_SOT23-3

G

2

L2N7002LT1G_SOT23-3

Q12

Q13

10K_0402_5%

FAN1_PWM_OUT

13

D

+5VS+3VS

12

RE101 10K_0402_5%@

FAN2_PWM_OUT

13

D

100K_0402_5%

FAN1_TACH<36>

0.01U_0402_16V7K

100K_0402_5%

FAN2_TACH<36>

0.01U_0402_16V7K

+3VS +5VS

12

RE81

1

CE99

2

+3VS +5VS

12

RE83

1

CE100

2

RTC Battery

+RTCBATT

CC27 1U_0402_6.3V6K

12

RE82

10K_0402_5%

DE7

12

RB751S40T1G_SOD523-2

AZ5125-01HPR7G_SOD523-2

Pilot Change DE7 footprint to AZ5125-01HPR7G_SOD523-2

12

RE84

10K_0402_5%

DE9

12

RB751S40T1G_SOD523-2

AZ5125-01HPR7G_SOD523-2

Pilot Change DE9 footprint to AZ5125-01HPR7G_SOD523-2

JRTC

1

2

3

GND

4

GND

ACES_50273-0020N-001

CONN@

SP02000SJ00

Pilot Change RE104 to 0603 0ohm short-pad footprint.

12

RE104

@

0_0603_5%

5VS_FAN1 FAN1_TACH_D

Pilot Change RE105 to 0603 0ohm short-pad footprint.

12

RE105

@

0_0603_5%

5VS_FAN2 FAN2_TACH_D FAN2_PWM_OUT

JFAN1

1

2

3

4

5

GND

6

GND

ACES_50278-0040N-001

CONN@

SP02001CE00

JFAN2

1

2

3

4

5

GND

6

GND

ACES_50278-0040N-001

CONN@

SP02001CE00

Security Classification

2011/08/25 2012/07/25

Issued Date

DVT2.0 Pop CE80, CE105 and change to 270P 0402.

5

4

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/08/25 2012/07/25

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

FAN/TP/KB/PWR SW

LA-E992P

26 77Tuesday, July 25, 2017

1

1.0(A00)

5

4

3

2

1

Thermal Sensor

+3VS

Fintek thermal sensor

OTP Thermistor

Placed BOT near between DIMM

1

D D

TOP VCORE Close UTH1

1

C

MMBT3904WH_SOT323-3

QTH1

E

3

REMOTE1+

12

CTH3

2

2200P_0402_25V7K

B

@

REMOTE1- REMOTE1-

CTH4

2200P_0402_25V7K

BOTTOM GPU

1

12

MMBT3904WH_SOT323-3

QTH2

C

E

3

2

B

CTH5 2200P_0402_25V7K

@

REMOTE2-

CT114

2200P_0402_25V7K

CTH1

0.1U_0201_10V6K

1

2

1

2

REMOTE1+

REMOTE2+

REMOTE2-

UTH1

1

VCC

2

DP1

3

DN1

4

DP2

5

DN2

F75303M_MSOP10

SA000046C00

SCL

SDA

ALERT#

THERM#

GND

10

9

8

7

6

Address 1001_101xb

REMOTE1,2 (+/-) :

C C

TPM

DVT1.0 Add RTPM5 BOM option for LA-E991P and LA-E992P EA difference.

RTPM5

991@TPM@

B B

27_0402_5%

SD028270A80

RTPM5

992@TPM@

33_0402_5%

SD028330A80

A A

Trace width/space:10/10 mil Trace length:<8"

SIO_SLP_S0#<18>

PCH_SPI_SO<17>

PCH_SPI_SI<6,17>

TPM_PIRQ#<17 >

PCH_SPI_CLK_R1<17>

PCH_SPI_CS2#<17> PCH_PLTRST#_EC<17,28,29,33,36,39,46>

+3V_TPM

@

RTPM13

4.7K_0402_5%

PCH_SPI_CS2#_R

5

1 2

RTPM8 100_0402_5%

DVT2.0 Change RTPM11 to 0ohm 0402 short-pad footprint.

1 2

SIO_SLP_S0# SIO_SLP_S0#_R

PCH_SPI_SO PCH_SPI_SI

PCH_SPI_CLK_R1 PCH_SPI_CS2#

@

DVT1.0 Change TPM to NPCT650VBCYX with new FW version.

RTPM3 0_0402_5%

RTPM11 0_0402_5%@

RTPM2 33_0402_5% RTPM4 33_0402_5% RTPM12 0_0402_5%

RTPM5 33_0402_5% RTPM6 0_0402_5%@

DVT2.0 Change RTPM6 to 0ohm 0402 short-pad footprint.

G

2

2nd source SA000029210-->EMC1403-2-AIZL-TR

UTPM1

TPM@

NPCT650VBCYX QFN_TPM2.0 FW 1.3.2.8

SA00008ELD0

1 2

TPM@

1 2

TPM@

1 2

@

1 2 1 2

+3V_TPM

S

3

QTPM1

@

ME2301DC-G_SOT23-3

D

1

TPM_LPM#

12

RTPM9

@

10K_0402_5%

4

@

TPM_LPM#

PCH_SPI_MISO PCH_SPI_MOSI TPM_PIRQ#_RTPM_PIRQ#

PCH_SPI1_CLK_R PCH_SPI_CS2#_R PCH_PLTRST#_EC

RTPM7

TPM@

10K_0402_5%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

29 30

3 6

24 21 18 15

19 20 17 27 13 28

12

4 5

+3VS

12

RTH2 10K_0402_5%

@

THM_SML1_CLK

THM_SML1_DATA

MAINPWONREMOTE2+

12

RTH3

10K_0402_5%

THM_SML1_DATA

THM_SML1_CLK

Place CZ95,CZ96 as close as UTPM.1

CTPM1

TPM@

1

8 14 22

2 7 10 11 25 26 31

9 16 23 32 33 12

0.1U_0402_16V7K

TPM@

CTPM5

10U_0402_6.3V6M

@

UTPM1

GPIO0/SDA/XOR_OUT GPIO1/SCL GPIO2/GPX GPIO3/BADD

LAD0/MISO LAD1/MOSI LAD2/SPI_IRQ# LAD3

LCKL/SCLK LFRAME#/SCS# LRESET#/SPI_RST#/SRESET# SERIRQ CLKRUN#/GPIO4/SINT# LPCPD#

PP TEST

NPCT650VBBYX_QFN32_5X5

VSB

VDD VDD VDD

GND GND GND GND

PGND

Reserved

NC NC NC NC NC NC NC

SA00008EL90

Compal Secret Data

2014/04/01 2015/04/30

3

Compal Secret Data

Deciphered Date

RTH4 10K_0402_5%

RTH5 0_0402_5%@

RTH6 0_0402_5%@

1

2

TPM@

CTPM6

0.1U_0402_16V7K

1

2

VCIN0_PH<36>

CPU TOP side

HT1 100K +-1% 0402 B25/50 4250K

SL200002H00

Main SL200000U00 S THERM_ 100K +-1% TSM0B104F4251RZ 0402 Thinking 2nd SL200001J00 S THERM_ 100K +-1% ERTJ0ER104F 0402 Panasonic 3rd SL200000V00 S THERM_ 100K +-1% NCP15WF104F03RC 0402 MURATA

+3VS

QTH3A

2

DMN65D8LDW-7_SOT363-6

61

QTH3B

5

DMN65D8LDW-7_SOT363-6

34

1 2

RTPM14 0_0402_5%

RTPM1 0_0402_5%

1

CTPM2

TPM@

10U_0402_6.3V6M

2

+3V_TPM

RTPM10 0_0402_5%

RTPM15 0_0402_5%

TPM@

CTPM7

0.1U_0402_16V7K

1

2

@

1 2

TPM@

1 2

@

+3VALW

Title

Thermal Sensor

Size Document Number Rev

Date: Sheet of

Date: Sheet

+3VALW

12

RTH1

7.87K_0402_1%

12

1

CTh2

0.01U_0402_16V7K

2

GPU_THM_SMBDAT <18,36,4 6>

GPU_THM_SMBCLK <18,36,46>

+3VALW+3VS

+3VS

1

TPM@

CTPM4

0.1U_0201_10V6K

CTPM3

10U_0402_6.3V6M

2

Compal Electronics, Inc.

LA-E992P

1

of

27 77Tuesday, July 25, 2017

1.0(A00)

5

4

3

2

1

M.2 Key-E (WLAN + BT)

+3VS_WLAN+3VS

1 2

RM22 0_0603_5%@

D D

+3VALW

1 2

RN2 0_0402_5%@

Reserve for NGFF Debug Card

Pilot Change RM22 to 0603 0ohm short-pad footprint.

+3VS_WLAN

JNGFF1

1

GND

USB20_P4<19> USB20_N4<19>

A-Key

3

USB_D+

5

USB_D-

7

GND

9

SIDO_CLK

11

SDIO_CMD

13

SDO_DAT0

15

SDO_DAT1

17

SDO_DAT2

19

SDO_DAT3

21

SDIO_WAKE#

23

SDIO_RESET#

PCM_SYNC

UART_WAKE#

E-Key

25

1 2

PCIE_PTX_WLANRX_P6<19>

C C

B B

HOST_DEBUG_TX<36>

PCIE_PTX_WLANRX_N6<19>

PCIE_PRX_WLANTX_P6<19> PCIE_PRX_WLANTX_N6<19>

CLK_PCIE_WLAN<17> CLK_PCIE_WLAN#<17>

WLAN_CLK_REQ#<17> PCIE_WAKE#<18,33,36,39>

DVT2.0 Change RN8 to 0ohm 0402 short-pad footprint.

Reserve for NGFF Debug Card

CN21 0.1U_040 2_10V7K

1 2

CN20 0.1U_040 2_10V7K

WLAN_CLK_REQ# PCIE_WAKE#

1 2

RN8 0_0402_5%@

1 2

RN5 0_0402_5%@

12

@

PCIE_PTX_WLANRX_RE_P6 PCIE_PTX_WLANRX_RE_N6

UART_2_CTXD_DRXD_R

E51_TX2

RN4 100K_0402_5%

GND

27

PETP0

29

PETN0

31

GND

33

PERP0

35

PERN0

37

GND

39

REFCLKP0

41

REFCLKN0

43

GND

45

CLKEQ0#

47

PEWAKE0#

49

GND

51

RSRVD/PETP1

53

RSRVD/PETN1

55

GND

57

RSRVD/PERP1

59

RSRVD/PERN1

61

GND

63

RESERVED

65

RESERVED

67

GND

69

MTG77

CONCR_213EAAA32FA

CONN@

SP070011I00

UART_CTS

UART_RTS RESERVED RESERVED RESERVED

W_DISABLE2# W_DISABLE1#

RESERVED RESERVED RESERVED RESERVED

3.3VAUX

3.3VAUX LED1#

PCM_CLK

PCM_IN

PCM_OUT

LED2#

GND

UART_RX

UART_TX

COEX3 COEX2 COEX1

SUSCLK

PERST0#

I2C_DATA

I2C_CLK

ALERT

3.3VAUX

MTG76

2 4 6 8 10 12 14 16 18 20

UART_2_CRXD_DTXD_R

22

UART_2_CTXD_DRXD_R

24 26 28

E51_TX2

30 32 34 36 38 40

SUSCLK_R

42 44

BT_RADIO_DIS#_R

46

WLAN_WIGIG60GHZ_ DIS#_R

48 50 52 54 56 58 60 62 64 66

68

22U_0603_6.3V6M

1

2

+3VS_WLAN

CN6

22U_0603_6.3V6M

Close to JNGFF

RN6 0_0402_5%@

RN7 0_0402_5%@

1 2

RN1 0_0402_5%@

.1U_0402_16V7K

CN7

1

2

Close to JNGFF

1

2

1 2

.1U_0402_16V7K

1

CN1

CN2

2

WLAN_WIGIG60GHZ_DIS#_R

BT_RADIO_DIS#_R

1

@RF@

CN9 10P_0402_25V8J

2

UART_2_CRXD_DTXD <20>

UART_2_CTXD_DRXD <20>

SUSCLK <18,29,36> PCH_PLTRST#_EC <17,27,29,33,36, 39,46>

DN1

12

RB751S40T1G_SOD523-2

AZ5125-01HPR7G_SOD523-2

DN2

12

RB751S40T1G_SOD523-2

AZ5125-01HPR7G_SOD523-2

Pilot Change DN1, DN2 footprint to AZ5125-01HPR7G_SOD523-2

WLAN_WIGIG60GHZ_ DIS# <20>

BT_RADIO_DIS# <20>

Key-E Debug Card Socket

A A

Security Classification

2011/08/25 2012/07/25

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/08/25 2012/07/25

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet

Compal Electronics, Inc.

NGFF-WLAN

LA-E992P

28 77Tuesday, July 25, 2017

1

1.0(A00)

of

5

M.2 Key-M (SSD)

PCIE_PRX_SSDTX_N12<16>

D D

PCIe SSD

SATA SSD

PCIE_PRX_SSDTX_P12<16>

PCIE_PTX_SSDRX_N12<16> PCIE_PTX_SSDRX_P12<16>

PCIE_PRX_SSDTX_N11<16> PCIE_PRX_SSDTX_P11<16>

PCIE_PTX_SSDRX_N11<16> PCIE_PTX_SSDRX_P11<16>

PCIE_PRX_SSDTX_N10<16> PCIE_PRX_SSDTX_P10<16>

PCIE_PTX_SSDRX_N10<16> PCIE_PTX_SSDRX_P10<16>

SATA_PRX_SSDTX_P0A<16> SATA_PRX_SSDTX_N0A<16>

SATA_PTX_SSDRX_N0A<16> SATA_PTX_SSDRX_P0A<16>

CD37 0.22U_0402_10V6K CD42 0.22U_0402_10V6K

CD43 0.22U_0402_10V6K CD44 0.22U_0402_10V6K

CD45 0.22U_0402_10V6K CD46 0.22U_0402_10V6K

CD53 0.22U_0402_10V6K CD51 0.22U_0402_10V6K

CLK_PCIE_SSD#<17> CLK_PCIE_SSD<17>

4

Pilot Change RZ36 to 0805 0ohm short-pad footprint.

RZ36 0_0805_5%

1 2 1 2

1 2

@

+3.3VDX_SSD+3VS

PCIE_PTX_SSDRX_N12_C PCIE_PTX_SSDRX_P12_C

PCIE_PTX_SSDRX_N11_C PCIE_PTX_SSDRX_P11_C

PCIE_PTX_SSDRX_N10_C PCIE_PTX_SSDRX_P10_C

SATA_PTX_SSDRX_N0A_C SATA_PTX_SSDRX_P0A_C

JNGFF2

1

GND

3

GND

5

PERn3

7

PERp3

9

GND

11

PETn3

13

PETp3

15

GND

17

PERn2

19

PERp2

21

GND

23

PETn2

25

PETp2

27

GND

29

PERn1

31

PERp1

33

GND

35

PETn1

37

PETp1

39

GND

41

PERn0/SATA-B+

43

PERp0/SATA-B-

45

GND

47

PETn0/SATA-A-

49

PETp0/SATA-A+

51

GND

53

REFCLKN

55

REFCLKP

57

GND

3

+3.3VDX_SSD

2

3P3VAUX

4

3P3VAUX

6

NC

8

DAS/DSS#

3P3VAUX 3P3VAUX 3P3VAUX 3P3VAUX

DEVSLP

PERST#

CLKREQ#

PEWake#

NC

10 12 14 16 18 20

NC

22

NC

24

NC

26

NC

28

NC

30

NC

32

NC

34

NC

36

NC

38 40

NC

42

NC

44

NC

46

NC

48

NC

50 52 54 56

NC

58

NC

SSD_LED#

SSD_PCIE_WAKE#

DVT1.0 Un-pop RD7

RD7 10K_0402_5%@

RD59 0_0402_5%@

DVT2.0 Change RD59 to 0ohm 0402 short-pad footprint.

RD8 10K_0402_5%

SSD_LED# <37>

1 2

2

1

RF Reserved.

RF@

CD41

CD38

0.1U_0402_10V6K

CD36

4.7U_0603_6.3V6K

1

2

12

+3.3VDX_SSD

CD39

0.01U_0402_16V7K

1

2

mSATA_DEVSLP < 19>

PCH_PLTRST#_EC <17,27,28,33,36,39,46> SSD_CLK_REQ# <17>

15P_0402_50V8J

CD40

47P_0402_50V8J

1

2

59

+3VS

12

RS40

NC

61

PEDET(NC-PCIE/GND-SATA)

63

GND

65

GND

67

GND

BELLW_SD-80159-4221

CONN@

SP07001D300

12

RS41 100K_0402_5%

FFS_INT1 FFS_INT2

1 2

RD58 0_0402_5%@

DVT2.0 Change RD58 to 0ohm 0402 short-pad footprint.

Free Fall Sensor

U5603

FFS@

LNG2DM

10

VDD_IO

9

VDD

3

SDO/SA0

4

SDA/SDI/SDO SCL/SPC1GND

2

CS

LNG2DMTR_LGA12_2X2

SA000089W00

RES

INT 1 INT 2

GND GND

5

12 11

6 7 8

100K_0402_5%

+3VS

0.1U_0402_16V7K

1

2

mCARD_PCIE_SATA#<16>

10U_0603_6.3V6M

CN22

1

@

2

PCH_SMBDATA PCH_SMBCLK

C C

CN19

FFS@

B B

PCH_SMBDATA<6,14,15,18,35>

PCH_SMBCLK<6,14,15,18,35>

SUSCLK(32kHz)

FFS_INT1 <20> FFS_INT2 <17>

3P3VAUX 3P3VAUX 3P3VAUX

GND1 GND2

60 62 64 66

68 69

DMN65D8LDW-7_SOT363-6

FFS_INT2

RD9 0_0402_5%@

FFS@

RS39

100K_0402_5%

FFS@

QC5B

5

1 2

+3VS

12

34

+5VS_HDD

12

FFS@

RS1 100K_0402_5%

61

FFS@

QC5A

2

DMN65D8LDW-7_SOT363-6

+3.3VDX_SSD

FFS_INT2_Q

SUSCLK <18,28,36>

HDD CONN

Pilot Change RZ34 to 0805 0ohm short-pad footprint.

SATA_PTX_DRX_P1B<16> SATA_PTX_DRX_N1B<16>

SATA_PRX_DTX_N1B<16> SATA_PRX_DTX_P1B<16>

HDD_DEVSLP<19>

A A

5

SATA_PTX_DRX_P1B SATA_PTX_DRX_N1B

SATA_PRX_DTX_N1B SATA_PRX_DTX_P1B

1 2

CS28 0.01U_0402_16V7K

1 2

CS27 0.01U_0402_16V7K

1 2

CS25 0.01U_0402_16V7K

1 2

CS26 0.01U_0402_16V7K

1 2

RD62 0_0402_5%@

4

1 2

RZ34 0_0805_5%

+5VS_HDD

+5VS_HDD+5VS

@

SATA_PTX_DRX_P1B_RC SATA_PTX_DRX_N1B_RC

SATA_PRX_DTX_N1B_RC SATA_PRX_DTX_P1B_RC

HDD_DEVSLP_R FFS_INT2_Q

DVT2.0 Change JHDD1 to ACES_51625-01201-001

JHDD1

1

2

3

4

5

6

7

8

9

10

11

12

13

GND

14

GND

CONN@

ACES_51625-01201-001

SP010028W00

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/08/25 2012/07/25

Place near HDD CONN (JHDD1)

+5VS_HDD

1

CS12 1000P_0402_50V7K

2

Compal Secret Data

Deciphered Date

1

2

CS13

0.1U_0402_10V6K

1

CS14 1U_0402_6.3V6K

2

1

CS15 10U_0603_6.3V6M

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

SSD/HDD

LA-E992P

1

of

29 77Tuesday, July 25, 2017

1.0(A00)

5

USB Powershare

4

3

2

1

Device Control Pins

CTL1 CTL2 CTL3 ILIM_SEL

0 1 1 X

D D

1 1 1 0

1 1 1 1

+3VALW

1 2

RI30 100K_0402_5%

1 2

RI9 100K_0 402_5%

1 2

RI10 100K_0402_5%

1 2

RI51 1M_0402_5%

C C

Flow Line Condition

DCP AUTO

SDP

CDP

ILIM_SEL_R

USB_R_CTL

USB_PWR_SHR_EN_L#

USB_POWERSHARE_VBUS_EN

Suspend mode

USB_POWERSHARE_VBUS_EN<36>

USB_PWR_SHR_EN_L#<36>

S0 mode

USB20_N1<1 9> USB20_P1<19>

USB_OC0#<19>

CTL1 = 0 : Enable Power Share DCP mode in Suspend mode

CTL1 = 1 : Disable Power Share in Suspend mode (For Support USB wake)

ILIM_SEL = 0 : SDP mode (0.9A by ILIM_LO setting)

ILIM_SEL = 1 : CDP mode (STATUS# trigger by ILIM_HI =2.2A)

USB3.0 / USB2.0 Port1

+5VALW

12

CI230.1U_0402_10V6K

ILIM_SEL_R

USB_POWERSHARE_VBUS_EN

USB_PWR_SHR_EN_L#

USB_R_CTL

US1

1

IN

2

DM_OUT

3

DP_OUT

13

FAULT#

4

ILIM_SEL

5

EN

6

CTL1

7

CTL2

8

CTL3

TPS2544RTER_WQFN16_3X3

SA000070N00

OUT

DP_IN

DM_IN

ILIM_LO

ILIM_HI

GND

GNDP

NC

+5V_CHGUSB_3

12

USBP1_D+

10

USBP1_D-

11

ILIM_LO1

15 16

9 14 17

1 2

ILIM_HI1

1 2

RI49 22.1K_0402_1% RI45 22.1K_0402_1%

USB3TP1_RE

USB3TN1_RE

USBP1_D-

USBP1_D+

1 2

CI28 0.1U_0402_10V7K

1 2

CI29 0.1U_0402_10V7K

Pilot Change RI65, RI66 footprint to R_0402-NPM

1 2

RI65 0_0402_5%

@EMI@

R_0402-NPM

LI8

EMI@

1 2

MCM1012B900F06BP_4P

SM070003Z00

1 2

RI66 0_0402_5%

@EMI@

R_0402-NPM

USB3TP1_RE_C USB3TP1_RE_C

USB3TN1_RE_C

USB3RP1_RE USB3RP1_RE

USB3RN1_RE

DI12

1

2

4

5

3

TVWDF1004AD0_DFN9

ESD@

USBP1_D-_R

USBP1_D+_R

34

9

USB3TN1_RE_C

8

7

USB3RN1_RE

6

Place close to JUSB3

USB3.0 Re-driver

Setting Status

A_EQB_EQ

6.0dB

PI3EQX7502AI

6.0dBNC

3.0dB0

9dB1

A B EQ1EQ0

9.5dB

PS8713

00

4.5dB

0 1 1 0 1 0

13 dB

7.5dB1 1

B B

+3VS

+3VALW

1 2

RI67 0_0603_5%@

1 2

RI59 0_0603_5%@

Pilot Change RI59 to 0603 0ohm short-pad footprint.

1

2

CI4

CI3

0.1U_0402_10V7K

NC 0 1

EQ0EQ1

0 1

* red color is current setting

+3V_USBRD

1

2

0.01U_0402_16V7K

3.0dB 9dB

B_EQA_EQ

9.5dB

00

4.5dB 13 dB

7.5dB1 1

USB3TP1<19> USB3TN1<19>

USB3RP1<19> USB3RN1<19>

B_DE A_DE

NC NC

-3.5dB -3.5dB

0

0.0dB 0.0dB

1

-6.0dB -6.0dB

A

DE0DE1

00 00

-3.5dB

-2.7dB

0 1

0.0dB1 0

-5.0dB1 1

1 2

CI5 0.1U_0402_10V7K

1 2

CI6 0.1U_0402_10V7K

1 2

CI7 0.1U_0402_10V7K

1 2

CI8 0.1U_0402_10V7K

PS8713 CH_B

+3V_USBRD

PS8713 CH_A

1 2

RI12 10K_0402_5%

1 2

RI11 10K_0402_5%@

A_DE

0 1 B

DE0DE1

0 1

+3V_USBRD

USB3TP1_C USB3TN1_C

USB3RN1_C

A_EQ0 A_DE0 A_OS0

B_EQ0 B_DE0 B_OS0

B_DE

-3.5dB

-2.7dB

0.0dB1 0

-5.0dB1 1

PARADE@

UI3

13

VCC<1>

1

VCC<0>

9

RX1P

8

RX1N

12

TX2P

11

TX2N

2

EQ1

3

DE1

4

OS1

17

EQ2

16

DE2

15

OS2

5

EN_RXD

PS8713BTQFN24GTR2-A1 TQFN

SA00005OR30

From PCH

PERICOM: RXA, PS8713: B_In

PERICOM: TXB, PS8713: A_Out

To USB3 CONN

PERICOM: TXA, PS8713:B_Out

PERICOM: RXB, PS8713:A_In

PS8713

USB3TP1_RE

22

TX1P

USB3TN1_RE

23

TX1N

USB3RP1_REUSB3RP1_C

19

RX2P

USB3RN1_RE

20

RX2N

REXT_8713

7

NC<0> NC<1>

RSVD GND<0> GND<2>

GND<3> GND<1>

THPAD

24

14 6 18

21 10 25

I2C_EN8713

USB8713_test

A_DE1 B_DE1

A_DE0 A_DE1

B_DE0 B_DE1

I2C_EN8713 REXT_8713

@

CI21

SE00000O000

Pilot Change CI21 BOM structure from RBOM@ to @.

1 2 1 2

RI564.7K_0402_5%

RI5410K_0402_5%

RI584.7K_0402_5%

RI574.7K_0402_5%

1 2

@

RI25 0_0402_5%~D@ RI23 4.99K_0402_1 %~D

12 12

+5V_CHGUSB_3

100U_1206_6.3V6K

1

2

RI19 4.7K_0402_5%@ RI20 4.7K_0402_5%@

RI21 4.7K_0402_5%@ RI22 4.7K_0402_5%@

47U_0805_6.3V6M

1

2

+3V_USBRD

0.1U_0402_10V6K

10U_0603_6.3V6M

CI27

CI25

CI26

1

2

USB3.0 / USB2.0 Left Side

USBP1_D-_R USBP1_D+_R

AZC199-02SPR7G_SOT23-3

USB3RN1_RE USB3RP1_RE

USB3TN1_RE_C USB3TP1_RE_C

1 2 1 2

RI4610K_0402_5%

RI4810K_0402_5%

RI4710K_0402_5%

RI5510K_0402_5%

1 2

@

1 2

RI24 4.7K_0402_5%@

ESD@

3

223

DI11

1

A_EQ0 A_OS0

B_EQ0 B_OS0

1 2

USB8713_test

JUSB3

1

VBUS

2

D-

3

D+

4

GND

5

SSRX-

6

SSRX+

7 8 9

Pilot Change JUSB3 footprint from SINGA_2UB2309-000111F_9P-T to ACON_TCRA2-9R1394_9P

RI15 10K_0402_5%@ RI16 4.7K_0402_5%@

RI17 10K_0402_5%@ RI18 4.7K_0402_5%@

+3V_USBRD

GND

SSTX-

GND

SSTX+

GND

ACON_TCRA2-9R1394

CONN@

DC23300ES00

ACON_TCRA2-9R1394_9P

+3V_USBRD

10 11 12 13

PS8713:

A A

5

DVT2.0 Remove UI3 TI@ BOM option

UI3

PERICOM@

PI3EQX7502AIZDEX TQFN24 USB3.0 REDR

SA00006WV00

4

Pin8,9=B_In, P22,23=B_Out Pin11,12=A_Out, Pin19,20=A_In Pin 17=A_EQ0, Pin 15=A_EQ1 Pin 16=A_DE0, Pin 18=A_DE1 Pin 2=B_EQ0, Pin 4=B_EQ1 Pin 3=B_DE0, Pin 6=B_DE1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/08/25 2012/07/25

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

USB Powershare

LA-E992P

1

1.0(A00)

of

31 77Tuesday, July 25, 2017

5

4

3

2

1

+5VALW

1

CI24 1U_0402_6.3V6K

D D

2

USB_EN#<36>

Active Low

USB Power Switch

+5V_CHGUSB_1_OUT

US2

OUT

5

IN

GND

4

EN

SY6288D20AAC_SOT23-5

SA00007AO00

OCB

1

2

3

1 2

RE115 0_0805_5%

USB_OC1# <19>

+5V_CHGUSB_1

@

Pilot Change RE115 to 0805 0ohm short-pad footprint.

+5VALW +5V_CHGUSB_1 +5V_CHGUSB_1_OUT Trace width : 100mil

LI2

C C

USB3RN2<19>

USB3RP2<19>

USB3TN2<19>

USB3TP2<19>

CI16 0.1U_0402_10V6K

CI20 0.1U_0402_10V6K

USB20_N2<19>

USB20_P2<19>

1 2

USB20_N2 USB20_N2_L

USB20_P2

USB3RN2

USB3RP2

USB3TN2_C

USB3TP2_C

EMI@

1 2

MCM1012B900F06BP_4P

SM070003Z00

DI9

1

2

4

5

3

TVWDF1004AD0_DFN9

ESD@

34

9

8

7

6

USB20_P2_L

USB3RN2

USB3RP2

USB3TN2_C

USB3TP2_C

+5V_CHGUSB_1

100U_1206_6.3V6K

1

CI30

SE00000O000

2

Pilot Change CI30 BOM structure from RBOM@ to pop.

USB3.0 / USB2.0 Right Side

JUSB1

1

USB20_N2_L

47U_0805_6.3V6M

1

CI17

2

0.1U_0402_10V6K

10U_0603_6.3V6M

CI19

CI18

1

2

AZC199-02SPR7G_SOT23-3

223

USB20_P2_L

USB3RN2 USB3RP2

USB3TN2_C

3

USB3TP2_C

ESD@

DI10

1

VBUS

2

D-

3

D+

4

GND

5

SSRX-

6

SSRX+

7

GND

8

SSTX-

9

SSTX+

ACON_TCRA2-9R1394

CONN@

DC23300ES00

ACON_TCRA2-9R1394_9P

Pilot Change JUSB1 footprint from SINGA_2UB2309-000111F_9P-T to ACON_TCRA2-9R1394_9P

GND GND GND GND

10 11 12 13

Place close to JUSB1

B B

LI5

USB20_N3<19>

USB20_P3<19>

USB3RN3<19>

USB3RP3<19>

USB3TN3<19>

USB3TP3<19>

A A

1 2

CI9 0. 1U_0402_10V6K

1 2

CI10 0.1U_0402_10V6K

USB20_N3 USB20_N3_L

USB20_P3

USB3RN3

USB3RP3

USB3TN3_C

USB3TP3_C

Place close to JUSB2

5

4

EMI@

1 2

MCM1012B900F06BP_4P

SM070003Z00

DI7

1

2

4

5

3

TVWDF1004AD0_DFN9

ESD@

34

9

8

7

6

USB20_P3_L

USB3RN3

USB3RP3

USB3TN3_C

USB3TP3_C

+5V_CHGUSB_1

10U_0603_6.3V6M

47U_0805_6.3V6M

CI12

1

@

CI31

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/08/25 2012/07/25

Compal Secret Data

1

CI11

2

Deciphered Date

USB3.0 / USB2.0 Right Side

USB20_N3_L

0.1U_0402_10V6K

CI13

1

2

AZC199-02SPR7G_SOT23-3

223

USB20_P3_L

USB3RN3

USB3RP3

USB3TN3_C

3

USB3TP3_C

ESD@

DI8

1

JUSB2

1

VBUS

2

D-

3

D+

4

GND

5

SSRX-

6

SSRX+

7

GND

8

SSTX-

9

SSTX+

ACON_TCRA2-9R1394

CONN@

DC23300ES00

ACON_TCRA2-9R1394_9P

Pilot Change JUSB2 footprint from SINGA_2UB2309-000111F_9P-T to ACON_TCRA2-9R1394_9P

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

USB conn.

LA-E992P

10

GND

11

GND

12

GND

13

GND

1.0(A00)

32 77Tuesday, July 25, 2017

1

32 77Tuesday, July 25, 2017

1.0(A00)

1

2

3

4

5

LOM + RJ45

A A

LAN_EN<36>

PCIE_PRX_LANTX_P5<19> PCIE_PRX_LANTX_N5<19>

PCIE_PTX_LANRX_P5<19> PCIE_PTX_LANRX_N5<19>

B B

LAN_DISABLE#_R<18,33>

PCIE_WAKE#<18,28,36,39>

+LAN_IO

LAN_DISABLE#_R<18,33>

+3VS

12

RL33 1K_0402_5%

ISOLATEB

12

RL30 15K_0402_1%

+LAN_IO rising time : >1ms and <100ms

+3VALW

RL41

IN

EN

100K_0402_5%

UL2

1

OUT

2

GND

3

OC

PCIE_PRX_LANTX_P5_C PCIE_PRX_LANTX_N5_C

PCIE_PTX_LANRX_P5_C PCIE_PTX_LANRX_N5_C

+LAN_VDD

+LAN_IO +LAN_VDD +LAN_VDD

0.1U_0402_10V6K

1 2

ISOLATEB

LAN_WAKE#_R

CL24

CL39

1U_0402_6.3V6K

12

W=40mils

RL27

100K_0402_5%

DVT2.0 Change RL2, RL43 to 0ohm 0402 short-pad footprint.

5

4

SY6288C20AAC_SOT23-5

SA000079400

1 2

CL30 0.1U_0402_10V6K

1 2

CL31 0.1U_0402_10V6K

1 2

CL47 0.1U_0402_10V6K

1 2

CL48 0.1U_0402_10V6K

PCH_PLTRST#_EC<17,27,28,29,36,39,46>

1 2

RL1 0_0402_5%@

1 2

RL2 0_0402_5%@

1 2

RL42 1K_0402_ 5%@

1 2

RL43 0_0402_ 5%@

+LAN_IO+3VALW

1.5A

W=40mils

1

CL15

CL19

2

0.1U_0402_10V6K

These caps close to Pin 11,32

UL1

17

HSOP

18

HSON

13

HSIP

14

HSIN

19

PERSTB

20

ISOLATEB

21

LANWAKEB

26

GPO

3

AVDD10

MDI2+ MDI2MDI3+ MDI3-

1

2

6 7

9 10 11 22 24

RTL8111H-CG_QFN32_4X4

1

@

SA000080P00

CL42

0.1U_0402_10V7K

2

MDIP2 MDIN2 MDIP3 MDIN3 AVDD33 DVDD10 REGOUT

DVT2.0 Remove DL1, DL2

CL44

4.7U_0402_6.3V6M

MDIP0 MDIP1 MDIN0 MDIN1

AVDD10 AVDD10 AVDD33 DVDD33

REFCLK_P

REFCLK_N

CLKREQB

CKXTAL1 CKXTAL2

LED0 LED1

RSET

GND

1

@

2

4.7U_0402_6.3V6M

1

MDI0+

4

MDI1+

2

MDI0-

5

MDI1-

8 30 32 23

15 16

LAN_CLKREQ#

12 28

XTLO

29

XTLI

27 25

31

RL31 2.49K_04 02_1%

33

Main SP050006800 S X'FORM_ NS892407 1G MHPC 2nd SP050006B10 S X'FORM_ GST5009-E LF LAN BOTHHAND 3rd SP050006F00 S X'FORM_ IH-160 LAN TAIMAG

DVT2.0 Change SP050006800 as main source.

+V_DAC

MDI3-

MDI3+

+LAN_VDD

+LAN_IO

CLK_PCIE_LAN <17> CLK_PCIE_LAN# <17>

LAN_CLKREQ# <17>

T944PAD~D@

12

+V_DAC

MDI2-

MDI2+

+V_DAC

MDI1-

MDI1+

+V_DAC

MDI0-

MDI0+

TL2

1

TCT1

2

TD1+

3

TD1-

4

TCT2

5

TD2

6

TD2-

7

TCT3

8

TD3+

9

TD3-

10

TCT4

11

TD4+

TD4-12MX4-

MHPC_NS892407

MCT1

MX1+

MX1-

MCT2

MX2+

MX2-

MCT3

MX3+

MX3-

MCT4

MX4+

24

MCT0

23

MDO3-

22

MDO3+

21

MCT1

20

MDO2-

19

MDO2+

18

MCT2

17

MDO1-

16

MDO1+

15

MCT3

14

MDO0-

13

MDO0+

Place close to MCT pin

1 2

RL19 75_0402 _5%

1 2

RL20 75_0402 _5%

1 2

RL39 75_0402 _5%

1 2

RL40 75_0402 _5%

1

EMI@

CL33

10P_1206_2KV8J

2

1

@

CL43

2

0.1U_0402_10V6K

SP050006800

EMI@

CL49

EMI@

1

CL41

2

EMI@

1

CL53

CL52

2

1

2

EMI@

CL55

1

2

EMI@

CL54

1

2

EMI@

CL57

1

2

EMI@

CL56

1

2

C C

CL36

XTLI

+LAN_IO

1

CL21

2

0.1U_0402_10V6K

D D

1

+LAN_VDD +LAN_VDD

W=20mils

CL34

1

2

1

CL35

2

0.1U_0402_10V6K

1U_0402_6.3V6K

These caps close to Pin 22

2

CL20

YL2

XTAL0

XTAL1

1

3

2

GND0

4

1

CL22

2

0.1U_0402_10V6K

1

CL32

2

0.1U_0402_10V6K

GND1

25MHZ_10PF_7V25000014

SJ10000E800

XTLO

These caps close to Pin 3,8,30These caps close to Pin 23

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/08/01 2014/07/31

3

1 2

10P_0402_25V8J

CL37

1 2

10P_0402_25V8J

Compal Secret Data

Deciphered Date

0.1U_0402_25V6

MDO3-

MDO3+

MDO1-

MDO2-

MDO2+

MDO1+

MDO0-

MDO0+

1000P_0402_50V7K

0.1U_0402_25V6 1000P_0402_50V7K

JLAN

8

PR4-

7

PR4+

6

PR2-

5

PR3-

4

PR3+

3

PR2+

2

PR1-

1

PR1+

SANTA_130460-N

CONN@

0.1U_0402_25V6

GND GND GND GND

0.1U_0402_25V6

1000P_0402_50V7K

9 10 11 12

1000P_0402_50V7K

DVT2.0 Remove SP050009200 BOM option.

DC23400DT00

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

4

Date: Sheet

Compal Electronics, Inc.

LAN RTL8111GUS-CG

LA-E992P

5

1.0(A00)

of

33 77Tuesday, July 25, 2017

5

Card Reader

4

3

2

1

D D

Pilot Change RI52 to 0603 0ohm short-pad footprint.

USB20_N7<19> USB20_P7<19>

Pin 2 Trace width : 15mil

C C

Close to UR1

RI3 6.19K_0402_1%

USB20_N7 USB20_P7

SD_CD#

12

Pin 5,6,8 Trace width : 40mil

+VCC_3IN1

B B

4.7U_0603_6.3V6K

CR5

1

0.1U_0402_10V7K

2

CR6

SD_CMD SD_CLK

1

2

SD_D0 SD_D1 SD_D2 SD_D3

Close to JREAD1

SD_WP SD_CD#

+3VS& +3VS_CR Trace width:40mil

1 2

RI52 0_0603_5%@

0.1U_0402_10V7K

Close to UR1

+3VS_CR

UR1

3

DM

4

DP

10

SD_CD#

15

MS_INS#

9

SD_D1

RREF

GPIO

12

SD_DAT1

2

RREF

5

3V3_IN1

6

3V3_IN2

8

3V3_IN3

24

48MHz_In

25

GND

RTS5176E-GR_QFN24_4X4

SA000071R00

Pin 11,12,13,18,20,22,23 Trace length mismatchinh within 100 mils.

JREAD1

4

VDD

2

CMD

5

CLK

3

VSS1

6

VSS2

7

DAT0

8

DAT1

9

DAT2

1

CD/DAT3

11

W/P

10

CD

T-SOL_156-1001902607

CONN@

CR9

AV18

CARD_3V3

SDREG

SP1 SP2 SP3 SP4 SP5 SP6 SP7 SP8 SP9

SP10

GND GND GND GND

1

2

+3VS_CR+3VS

+VCC_3IN1

1 7

16

11 13 14 17 18 19 20 21 22 23

12 13 14 15

1

2

CR10

4.7U_0603_6.3V6K

Pin 7 +VCC_3IN1 Trace width : 40mil

V18

SDREG

SD_WP SD_D0

SD_CLK_R

SD_CMD

SD_D3 SD_D2

Pin1,16 Trace width : 15mil Close to UR1

1U_0402_6.3V6K

CR7

1U_0402_6.3V6K

2

1

CR8

2

1

SD_CLK_R

EMI@

1 2

RI53 22_0402_5%

SD_CLK

1

@EMI@

CR4

6.8P_0402_50V8C

2

Close to UR1 chip side

SP07001AC00

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2015/09/01

3

Compal Secret Data

Deciphered Date

2016/09/01

2

Compal Electronics, Inc.

Title

Crad Reader RTS5176E

Size Document Number Rev

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

LA-E992P

Tuesday, July 25, 2017

LA-E992P

1

of

34 77

1.0(A00)

5

4

Main Func = DP to VGA Converter

3

2

1

+3VS

1 2

RVGA1 0_0603_5%@

D D

Pilot Change RVGA1 to 0603 0ohm short-pad footprint.

+3VS

@

+CRT_5V_OUT

C C

RVGA7

2.2K_0402_5%

VGA@

1 2

2.2K_0402_5%

VGA@

1 2

RVGA8

CRT_DDCDATA_CON CRT_DDCCLK_CON

DDI3_AUXN_C

12

RVGA3100K_0402_5%

DDI3_AUXP_C

12

RVGA4100K_0402_5%

DDI3_AUXP<7> DDI3_AUXN<7>

CPU_DDI3_P0< 7> CPU_DDI3_N0<7> CPU_DDI3_P1< 7> CPU_DDI3_N1<7>

2

CVGA1 10U_0603_6.3V6M

1

VGA@

+3VS VDD_DAC_33AVCC33

1 2

RVGA2 0_0603_5%@

Pilot Change RVGA2 to 0603 0ohm short-pad footprint.

DDI3_AUXP DDI3_AUXN

CPU_DDI3_P0 CPU_DDI3_N0 CPU_DDI3_P1 CPU_DDI3_N1

AVCC33

CPU_DDI3HPD<16>

2

CVGA2 10U_0603_6.3V6M

1

VGA@

CVGA6 0.1U_0402_16V4ZVGA@

CVGA4 0.1U_0402_16V4ZVGA@ CVGA9 0.1U_0402_16V4ZVGA@

CVGA10 0.1U_0402_16V4ZVGA@ CVGA11 0.1U_0402_16V4ZVGA@ CVGA12 0.1U_0402_16V4ZVGA@ CVGA13 0.1U_0402_16V4ZVGA@

RVGA5 4.7K_0402_5%VGA@ RVGA6 4.7K_0402_5%VGA@

CPU_DDI3HPD

1 2

1 2 1 2

1 2 1 2 1 2 1 2

+3VS

PCH_SMBCLK<6,14,15,18,29>

PCH_SMBDATA<6,14,15,18,29>

RVGA9 0_0402_5%@

DVT2.0 Change RVGA9 to 0ohm 0402 short-pad footprint.

12 12

RVGA16 4.7K_0402_5%@

1 2

+CRT_5V_OUT +5VS

FVGA1

1.1A_6V_SPR-P110

VGA@

DVGA1

21

LRB551V-30T1G_SOD323-2

VGA@

21

Note: CG3, CG4. CG6, CG8, CG15 need to place to Chip

UVGA1

1

AVC33

4

AVCC_12

14

VCC_33

2

AUX_P

3

AUX_N

5

LANE0_P

6

LANE0_N

7

LANE1_P

8

LANE1_N

10

POL1/SPI_CEB

9

POL2

11

GPI1/SPI_CLK

12

GPI2/SPI_SI

13

GPI3/SPI_SO

15

VGA_SCL

16

VGA_SDA

30

SMB_SCL

29

SMB_SDA

32

HPD

RTD2166

+1.2V_VCCK

+3VS

DDI3_AUXP_C DDI3_AUXN_C

DP_P0 DP_N0 DP_P1 DP_N1

POL1_SDA POL1_SCL

12

CRT_DDCCLK_CON CRT_DDCDATA_CON

CRT_PCH_HPD

RVGA10 100K_0402_5%

1 2

AVCC33

RTD2166-CG_QFN32_4X4VGA@

VDD_DAC_33

VCCK_12

PVCC_33

HVSYNC_PWR

VSYNC

HSYNC

BLUE_P

GREEN_P

RED_P

LDO_RSTB

EXT_CLK_IN

EXT1.2V_CTRL

GND

EPAD_GND

20

25

26

17 18 19

21

22

23

27 28 31

24 33

+1.2V_VCCK

+3VS

VDD_DAC_33

CVGA3 0.1U_0402_16V4ZVGA@

CVGA5 2.2U_0402_6.3V6MVGA@

CVGA7 0.1U_0402_16V4ZVGA@

CVGA8 0.1U_0402_16V4ZVGA@

DP_CRT_VSYNC_CON DP_CRT_HSYNC_CON

DP_CRT_B

DP_CRT_G

DP_CRT_R

1 2

+5VS

CVGA14

VGA@

0.1U_0402_16V4Z

1

CVGA15

VGA@

2

4.7U_0603_6.3V6K

1

2

CRT RGB

B B

A A

CRT H/VSYNC CRT SMBUS

DP_CRT_B

RVGA11

DP_CRT_HSYNC_CON

DP_CRT_VSYNC_CON

5

VGA@

12

VGA@

75_0402_1%

RVGA12

RVGA13

CVGA16

12

VGA@

75_0402_1%

VGA@

10P_0402_50V

VGA@EMI@

DVT 1.0 Change LVGA1, LVGA2, LVGA3 BS to VGA@EMI@.

VGA@EMI@

1 2

LVGA1 BLM15BB220SN1D

VGA@EMI@

1 2

LVGA2 BLM15BB220SN1D

VGA@EMI@

1 2

LVGA3 BLM15BB220SN1D

1

2

VGA@

2.2P_0402_50V8C

12

CVGA17

RVGA1447_0402_5%

RVGA1547_0402_5%

CVGA23

1

2

VGA@

2.2P_0402_50V8C

CVGA18

2.2P_0402_50V8C

1

2

CRT_HSYNC_CON

CRT_VSYNC_CON

12

4

12

CVGA24 10P_0402_50V

VGA@EMI@

VGA@

CVGA19

+CRT_5V_OUT

CRT_RDP_CRT_R

CRT_GDP_CRT_G

CRT_B

VGA@

CVGA21

2.2P_0402_50V8C

CVGA20

1

2

DVT 1.0 Change CVGA23, CVGA24 BS to VGA@EMI@.

2.2P_0402_50V8C

1

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2015/09/01

3

CRT_R

CRT_DDCDATA_CON CRT_G

CRT_HSYNC_CON CRT_B

CRT_VSYNC_CON

CRT_DDCCLK_CON

@

CVGA22

0.01U_0402_16V7K

Compal Secret Data

Deciphered Date

1

2

JCRT1

6

11

1 7

12

2 8

13

3 9

14

4 10 15

5

C-K_80454-5K1-152

CONN@

DC060004S10

2016/09/01

2

16

G

17

G

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

DP to VGA Converter

LA-E992P

Tuesday, July 25, 2017

LA-E992P

1

of

35 77

1.0(A00)

5

H_PROCHOT#<9,59,60,71>

+3VALW

RE12

1 2

@

0_0603_5%

100K_0402_5%

12

LID_CL_SIO#

0.047U_0402_16V4Z

12

CE76

+3VALW_EC

0.1U_0402_10V6K

10U_0603_6.3V6M

CE62

1

CE89

2

1

CE86

47P_0402_50V8J

2

SATA_LED_EN<37>

ESPI_CLK<19>

DVT2.0 Change net UPD_SMBINT# to UPD1_ALERT

12

RE149 0_0402_5%@

1

2

USB_POWERSHARE_VBUS_EN<31>

ALL_SYS_PWRGD<18,61>

1000P_0402_50V7K

@

1000P_0402_50V7K

@

2

1

CE64

CE63

+3VS

1

CE85

2

5

UE6

P

2

Y4A

G3NC

1

SN74LVC1G06DCKR_SC70-5

DVT2.0 Change RE132 to 0ohm 0402 short-pad footprint.

ESPI_CS#<19>

PRIM_PWRGD

PRIM_PWRGD_R<61,64,65>

L_BKLT_EN_EC<16>

AC_DIS<60>

FPR_SCAN#<37>

PTP_INT#<17,26> LAN_EN<33>

USB_EN#<32>

IMVP_VR_ON<18>

SUSCLK<18,28,29>

DVT2.0 Change RE131, RE66, RE135, RE133, RE134, RE62, RE61 to 0ohm 0402 short-pad footprint.

+3VALW

RPE2 10K_0804_8P4R_5%

KSI0

3456

KSI1

2

7 8

7

+3VS_TP

8

1 8 2 7 3 6 4 5

1 2

D D

C C

1

RPE3 10K_0804_8P4R_5%

3456 2 1

RPE4 100K_0804_8P4R_5%

RPE5 100K_0804_8P4R_5%

KSO10 KSO11 KSO12 KSO13

RPE6 100K_0804_8P4R_5%

KSO15 KSO14 KSO16

RPE7 100K_0804_8P4R_5%

12

RE30 100K_0402_5%

USB_EN#

12

RE29 100K_0402_5%

BAT1_LED#

12

RE39 100K_0402_5%

BAT2_LED#

12

RE113 100K_0402_5%

PRIM_PWRGD

12

@

RE150 100K_0402_5%

RE24 4.7K_0402_5%

RE55 4.7K_0402_5%

LID_CLOSE#<25>

DVT2.0 Change RE68 to 0ohm 0402 short-pad footprint.

KSI2 KSI3

KSI4 KSI5 KSI6 KSI7

KSO0 KSO1 KSO2 KSO3

KSO4 KSO5 KSO6 KSO7

KSO8

KSO9

CLK_TP_SIO

DAT_TP_SIO

+3VALW

Pilot Change RE12 to 0603 0ohm short-pad footprint.

RE25

RE68

1 2

@

0_0402_5%

CE8

1V_PG<64>

PBAT_PRES#<59,60>

100P_0402_50V8J

Note:

The LPC Interface signals require the VTR_33_18 power

B B

pin to be connected to the 3.3V VTR rail. The eSPI Interface signals require the VTR_33_18 power pin to be connected to the 1.8V rail. The GPIO signals on these pins may operate at either 1.8V or 3.3V.

GPIO061/LPCPD#/ESPI_RESET#

‧

VTR_33_18

‧

GPIO063/SER_IRQ/ESPI_ALERT#

‧

GPIO064/LRESET#

‧

GPIO034/PCI_CLK/ESPI_CLK

‧

GPIO044/LFRAME#/ESPI_CS#

‧

GPIO040/LAD0/ESPI_IO0

‧

GPIO041/LAD1/ESPI_IO1

‧

GPIO042/LAD2/ESPI_IO2

‧

GPIO043/LAD3/ESPI_IO3

‧

GPIO067/CLKRUN#

‧

Debug Connector

+3VALW_EC

A A

JDEG1

11

GND

12

GND

JXT_FP241AH-010GAAM

CONN@

RE60

49.9_0402_1%

1 2

1

JTAG_TDI

2

JTAG_TMS

3

JTAG_CLK

4

JTAG_TDO

5

6

MSCLK

6

7

MSDATA

7

HOST_DEBUG_TX

8

9

10

DVT2.0 Change RE109, RE110, RE111, RE112 to 0ohm 0402 short-pad footprint.

12

RE109 0_0402_5%@

12

RE110 0_0402_5%@

12

RE111 0_0402_5%@

12

RE112 0_0402_5%@

12

RE63 10K_0402_5%

12

RE65 @ 100K_0402_5%

12

RE64 10K_0402_5%

12

RE118 10K_0402_5%@

5

ICSP_CLK ICSP_CLR

ICSP_DAT

+3VALW_EC

T3 PAD~D@

4

0.1U_0402_10V6K

CAP_LED#<25>

CLK_TP_SIO<26> DAT_TP_SIO<26>

ESPI_IO0<19> ESPI_IO1<19> ESPI_IO2<19> ESPI_IO3<19>

ESPI_ALERT#<19>

ESPI_RESET#<19>

UPD1_ALERT<41>

1 2

GND GND

CONN@

CE67

1

2

TP_EN#<26>

Y1

1 2

JESPI1

10

0.1U_0402_10V6K CE68

1

2

Pilot Change RE16 to 0603 0ohm short-pad footprint.

KSI[0..7]<25>

KSO[0..16]<25>

12

T4942 @

12

12 12

MEC_XTAL2MEC_XTAL1

+DEBUG_PWR+3VALW_EC

RE1300_0402_5% @

1

2

3

4

5

6

7

8

9

10

T4941 @

12

0.1U_0402_10V6K CE66

CE65

1

2

0.1U_0402_10V6K

PROCHOT

RE27 100K_0402_5%

1 2

DVT1.0 Change net CAPS_LED# to CAP_LED#

SIO_PWRBTN#<6,18>

ESPI_CS#

RE132 0_0402_5%

GPU_PWR_LEVEL<46>

SYS_PWROK<6,18>

RE133 0_0402_5%@

RTCRST_ON<18> PCH_RSMRST#<6,18>

RE134 0_0402_5%@

RE61 0_0402_5%@ RE131 0_0402_5%@

RE62 0_0402_5%@ RE135 0_0402_5%@

RE106 0_0402_5%@

MEC_XTAL1

RE66 0_0402_5%@

32 KHz Clock

32.768KHZ 9PF 20PPM 9H03280012

Y_X1A000141000200_2P

SJ10000Q400

12

CE102 12P_0402_50V8J

DVT1.0 Change CE102, CE101 to 12pF.

DVT2.0 Change RE130 to 0ohm 0402 short-pad footprint.

11 12

JXT_FP241AH-010GAAM

4

0.1U_0402_10V6K CE69

1

2

DVT1.0 Change net +RTCVCC_VBAT to +RTC_CELL_VBAT

+RTCVCC

RE16

1 2

@

0_0603_5%

0.1U_0402_10V6K

UE1

KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16

KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7

ESPI_IO0 ESPI_IO1 ESPI_IO2 ESPI_IO3

MASK_SATA_LED# ESPI_CLK

ESPI_ALERT#

ESPI_RESET# LID_CL_SIO#

UPD1_ALERT

PRIM_PWRGD RTCRST_ON PCH_RSMRST#

BKLT_IN_EC AC_DIS

FPR_SCAN# TP_WAKE_KBC# AUX_ON

RUNPWROK RESET_OUT#

MEC_XTAL2 MEC_XTAL1_R

DVT2.0 Change Y1 to SJ10000Q400 (Metal lid)

DVT2.0 Change RE67 to 0ohm 0603 short-pad footprint.

CE101 12P_0402_50V8J

ESPI_IO0 ESPI_IO1 ESPI_IO2 ESPI_IO3

ESPI_CLK

2

GPIO027/KSO00/PVT_IO1

14

GPIO015/KSO01/PVT_nCS

15

GPIO016/KSO02/PVT_SCLK

16

GPIO017/KSO03/PVT_IO0

37

GPIO045/BCM_nINT1/KSO04

38

GPIO046/BCM_DAT1/KSO05

39

GPIO047/BCM_CLK1/KSO06

50

GPIO025/KSO07/PVT_IO2

46

GPIO055/PWM2/KSO08/PVT_IO3

68

GPIO102/KSO09/CR_STRAP

72

GPIO106/KSO10

74

GPIO110/KSO11

75

GPIO111/KSO12

76

GPIO112/PS2_CLK1A/KSO13

77

GPIO113/PS2_DAT1A/KSO14

86

GPIO125/KSO15

92

GPIO132/KSO16

93

GPIO140/KSO17

98

GPIO143/KSI0/nDTR

99

GPIO144/KSI1/nDCD

6

GPIO005/SMB00_DATA/SMB00_DATA18/KSI2

7

GPIO006/SMB00_CLK/SMB00_CLK18/KSI3

104

GPIO147/KSI4/nDSR

105

GPIO150/KSI5/nRI

107

GPIO151/KSI6/nRTS

108

GPIO152/KSI7/nCTS

78

GPIO114/PS2_CLK0

79

GPIO115/PS2_DAT0

52

GPIO026/PS2_CLK1B

88

GPIO127/PS2_DAT1B

59

GPIO040/LAD0/ESPI_IO0

60

GPIO041/LAD1/ESPI_IO1

61

GPIO042/LAD2/ESPI_IO2

62

GPIO043/LAD3/ESPI_IO3

58

GPIO044/LFRAME#/ESPI_CS#

56

GPIO064/nLRESET

57

GPIO034/PCI_CLK/ESPI_CLK

63

GPIO067/nCLKRUN

55

GPIO063/SER_IRQ/ESPI_ALERT#

10

GPIO011/nSMI/nEMI_INT

49

GPIO060/KBRST

53

GPIO061/LPCPD#/ESPI_RESET#

66

GPIO100/nEC_SCI

32

GPIO126/SHD_SCLK

28

GPIO133/SHD_IO0

29

GPIO134/SHD_IO1

30

GPIO135/SHD_IO2

31

GPIO136/SHD_IO3

27

GPIO123/SHD_CS# [BSS_STRAP]

67

GPIO101/SPI_CLK

69

GPIO103/SPI_IO0

71

GPIO105/SPI_IO1

42

GPIO052/SPI_IO2

33

GPIO062/SPI_IO3

3

GPIO001/SPI_nCS/32KHZ_OUT

13

nRESET_IN/GPIO014

48

GPIO057/VCC_PWRGD

73

GPIO107/nRESET_OUT

125

XTAL2

123

XTAL1

SA0000A8L00

1 2

3

RE125 For SKU ID Select

10K

UMA

17.8K

N17P_G0

27K

N17P_G1

37.4KN17E_G1

DVT1.0 Dell update Model ID Res. value

RE125

37.4K_0402_1%

SD034374280

+RTC_CELL_VBAT

CE73

N17E_G1@

1

2

RE125

27K_0402_1%

SD034270280

122

VBAT

N17P_G1@

+3VALW_EC

43

103

VTR5VTR19VTR

GPIO007/SMB01_DATA/SMB01_DATA18

GPIO010/SMB01_CLK/SMB01_CLK18

GPIO012/SMB02_DATA/SMB02_DATA18

GPIO013/SMB02_CLK/SMB02_CLK18

GPIO130/SMB03_DATA/SMB03_DATA18

GPIO131/SMB03_CLK/SMB03_CLK18

GPIO141/SMB04_DATA/SMB04_DATA18

GPIO142/SMB04_CLK/SMB04_CLK18

MEC1416

GPIO033/PECI_DAT/SB_TSI_DAT

GPIO166/CMP_VREF1/UART_CLK

VSS17VSS51AVSS

VSS_VBAT

VSS

VSS64VSS

84

112

124

100

EC_AGND

RE67

1 2

@

0_0603_5%

Close UE1

EC_AGND

DVT1.0 Change CE103 to SE000006900

ESPI_RESET#ESPI_CS#

RE1440_0402_5% @

RE1450_0402_5% @

PCH_PLTRST#_EC <17,27,28,29,33,39,46>

3

RE125

UMA@

10K_0402_1%

SD034100280

RE125

N17P_G0@

17.8K_0402_1%

SD034178280

For eSPI Power +1.8V_PRIM

+1.8V_PRIM +1.8VALW_EC

RE15 0_0603_5%

1 2

@

VTR_33_18

VTR65VTR82VTR

GPIO050/TACH0 GPIO051/TACH1

GPIO053/PWM0 GPIO054/PWM1

GPIO056/PWM3 GPIO030/BCM_nINT0/PWM4 GPIO031/BCM_DAT0/PWM5 GPIO032/BCM_CLK0/PWM6

GPIO002/PWM7

GPIO157/LED0/TST_CLK_OUT

GPIO156/LED1 GPIO104/LED2

GPIO116/TFDP_DATA/UART_RX

GPIO117/TFDP_CLK/UART_TX

GPIO035/SB-TSI_CLK

VREF_CPU

GPIO145/ICSP_CLOCK

GPIO146/ICSP_DATA

ICSP_MCLR

BGPO/GPIO004

SYSPWR_PRES/GPIO003

VCI_OUT/GPIO036 nVCI_IN1/GPIO162 nVCI_IN0/GPIO163

VCI_OVRD_IN/GPIO164

GPIO160/DAC_0

GPIO161/DAC_1

DAC_VREF

GPIO124/CMP_VOUT0

GPIO020/CMP_VIN0

GPIO165/CMP_VREF0

GPIO120/CMP_VOUT1

GPIO021/CMP_VIN1

GPIO024/ADC7

GPIO023/ADC6/A20M

GPIO022/ADC5 GPIO153/ADC4 GPIO154/ADC3 GPIO155/ADC2 GPIO122/ADC1 GPIO121/ADC0

ADC_VREF

VR_CAP

MEC1416-NU-D0 VTQFP 128P_14X14

18

MEC1404-NU-TR_VTQFP128_14X14

T4931@

CE103

VR_CAP

1 2

1U_0603_25V6K

SE000006900

ESR <100m ohms Close UE1

2

Ra

MODEL_ID

0.1U_0402_10V6K

CE104

1

Rb

2

Pilot Change RE15 to 0603 0ohm short-pad footprint.

CE71

1 2

0.1U_0402_10V6K

PBAT_CHG_SMBDAT PBAT_CHG_SMBCLK GPU_THM_SMBDAT GPU_THM_SMBCLK TYPEC_SMBDA TYPEC_SMBCLK TBTA_HRESET_EC TBT_RESET_N_EC#

FAN1_TACH FAN2_TACH

FAN1_PWM FAN2_PWM

BAT2_LED# BAT1_LED# BREATH_LED#

ME_FWP HOST_DEBUG_TX

PTP_DIS# H_PECI

VREF_CPU

ICSP_CLK ICSP_DAT ICSP_CLR

NB_MUTE# SYSPWR_PRES

POWER_SW_IN# HW_ACAV_IN

GC6_THM_DIS#

T4940@

CMP_VOUT0 CMP_VIN0 VCREF0

PROCHOT

T4939@

MODEL_ID I_ADP BOARD_ID

I_BATT

Issued Date

+3VALW_EC

12

RE125 10K_0402_1%@

RE124 100K_0402_1%

1 2

EC_AGND

PBAT_CHG_SMBDAT <59,60>

PBAT_CHG_SMBCLK <59,60>

GPU_THM_SMBDAT <18,27,46>

GPU_THM_SMBCLK <18,27,46>

TYPEC_SMBDA <41>

TYPEC_SMBCLK <41>

TBT_RESET_N_EC# <39,41>

FAN1_TACH <26> FAN2_TACH <26>

KB_LED_PWM <25> BEEP <23>

FAN1_PWM <26> FAN2_PWM <26> LANWAKE# <18> PS_ID <59> PCIE_WAKE# <18,28,33,39>

BAT2_LED# <37> BAT1_LED# <37> BREATH_LED# <37>

ME_FWP <18> HOST_DEBUG_TX <28>

ALWON <61,65>

GC6_THM_DIS# <17>

CMP_VOUT0 <55,61>

DVT1.0 Change Test Point T4939 connect to EC pin21.

LCD_TST <38>

USB_PWR_SHR_EN_L# <31> PANEL_BKEN_EC <38> SIO_EXT_WAKE# <20>

DVT1.0 Change net I_ADP_R to I_ADP

LCD_VCC_TEST_EN <42>

EC_AGND

RE147 300_0402_5%

1 2

1

CE107 2200P_0402_25V7K

2

EC_AGND

MODEL_ID

54

8 9 11 12 89 91 96 97

40 41

44 45

47 34 35 36 4

1 106 70

80 81

90 94

95

101 102 87

119 120 121 126 127 128

23 24 22

85 20 25

83 21 26

118 117 116 109 110 111 113 114 115

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SD034100280 10K_0402_1%

13.7K_0402_1%SD034137280

17.8K_0402_1%SD034178280

22.1K_0402_1%SD034221280

SD034270280 27K_0402_1%

32.4K_0402_1%SD034324280

37.4K_0402_1%SD034374280

SD034499280 49.9K_0402_1%

57.6K_0402_1%

SD034576280 SD034649280 64.9K_0402_1%

73.2K_0402_1%SD00000B180 SD000002780 82.5K_0402_1% SD034931280 93.1K_0402_1% SD034107380

107K_0402_1% 120K_0402_1%

SD034120380

137K_0402_1%

SD034137380

154K_0402_1%

SD034154380

200K_0402_1%

SD034200380

232K_0402_1%

SD034232380

SD034100380 100K_0402_1%

RE148 0_0402_5%@

DVT1.0 Change net TBT_RESET_N_EC# connect to EC pin97.

12

RE57 0_0402_5%@

1 2

RE17 33_0402_5%

DVT2.0 Change RE58, RE57 to 0ohm 0402 short-pad footprint.

12

RE58 0_0402_5%@

1 2

RE52 100K_0402_5%

12

RE138 0_0402_5%@

12

RE73

+3VALW_EC

0.1U_0402_10V6K

CE81

1

2

DVT1.0 Change net I_ADP_R to I_ADP

I_BATT_R <60>

DVT2.0 Change RE116 to 0ohm 0402 short-pad footprint.

VREF_CPU

0.1U_0402_10V6K

Compal Secret Data

2015/07/15 2016/07/31

Compal Secret Data

Deciphered Date

2

12

PTP_DIS#_R <26> PECI_EC <9,16>

EC_MUTE# <23>

ACAV_IN <18,59,60>

+3VALW_EC

CE79

0_0402_5%@

I_ADP

1

2

EC_AGND

+1VALW

12

@

1

CE77

2

1 2

RE36 300_0402_5%

1 2

CE87 2200P_0402_25V7K

RE116 0_0402_5%

RE13 For Board ID Select

X00

EVT DVT1

X01 17.8K

X02

DV1

X03 37.4K

A00

Pilot

DVT1.0 Dell update Board ID Res. value

RE13

PILOT@

49.9K_0402_1%

SD034499280

TBTA_HRESET <41>

+3VLP

+RTCVCC

0.1U_0402_10V6K

VCIN0_PH <27>

VCREF0

1

2

10K

27K

49.9K

RE13

27K_0402_1%

SD034270280

RE20 1K_0402_5%

1 2

RE22 100K_0402_5%

DVT2.0 Change RE138 to 0ohm 0402 short-pad footprint.

DVT2.0 Change RE73 to 0ohm 0402 short-pad footprint.

POWER_SW_IN#

I_ADP_R <59,60>

DVT1.0 Change net I_ADP to I_ADP_R

+3VALW

12

RE34 10K_0402_1%

0.1U_0402_10V6K

12

CE91

RE35 10K_0402_1%

1

RE13

EVT@

10K_0402_1%

SD034100280

RE13

DVT2@

DVT1@

17.8K_0402_1%

SD034178280

PBAT_CHG_SMBDAT

PBAT_CHG_SMBCLK

GPU_THM_SMBDAT

GPU_THM_SMBCLK

TP_WAKE_KBC#

BREATH_LED#

TYPEC_SMBDA

TYPEC_SMBCLK

UPD1_ALERT

DVT2.0 Change RE141.1 Cconnect to UPD1_ALERT

FPR_SCAN#

DVT2.0 Change RE143 to 100K.

IMVP_VR_ON

ME_FWP

BKLT_IN_EC

DVT1.0 Change RE114.2 connect to BKLT_IN_EC

TBT_RESET_N_EC#

DVT1.0 Add RE151 PD res on TBT_RESET_N_EC#

+RTCVCC

12

RE31 100K_0402_5%

RE47

1 2

1K_0402_5%

1

CE12

2.2U_0402_6.3V6M

2

CMP_VIN0 CMP_VOUT0

RE33 100K_0402_5%

IMVP_VR_ON

ACAV_IN

Board ID

1 2

RE43 4.7K_0402_5%

1 2

RE44 4.7K_0402_5%

1 2

RE45 2.2K_0402_5%

1 2

RE46 2.2K_0402_5%

1 2

RE53 100K_0402_5%

1 2

RE119 100K_0402_5%

1 2

RE139 2.2K_0402_5%

1 2

RE140 2.2K_0402_5%

1 2

RE141 10K_0402_5%

1 2

RE143 100K_0402_5%

1 2

RE23 10K_0402_5%

1 2

RE21 1K_0402_5%

RE114 100K_0402_5%

RE151 100K_0402_5%

1 2

@

CE82

CE84

+3VALW_EC

Ra

BOARD_ID

0.1U_0402_10V6K

CE98

1

Rb

2

EC_AGND

+3VALW_EC

@

12

POWER_SW#_MB <37>

+3VALW

RE38

100K_0402_5%

1 2

1000P_0402_50V7K@

12

100P_0402_50V8J

Close to UE1 each pin

Compal Electronics, Inc.

Title

EC MEC1404

Size Document Number Rev

Date: Sheet of

Date: Sheet

LA-E992P

1

12

RE13

@

10K_0402_1%

RE14 100K_0402_1%

1 2

+3VS

12

36 77Tuesday, July 25, 2017

1.0(A00)

of

5

4

3

2

1

LED Board Connector

+5VALW

BAT1_LED#<36>

5

D D

BAT2_LED#<36>

C C

PCH_SATA_LED#<16>

SSD_LED#<29>

DVT2.0 Change RH502 to 0ohm 0402 short-pad footprint.

QE20B

34

DMN65D8LDW-7_SOT363-6

2

61

QE23A DMN65D8LDW-7_SOT363-6

12

RH504 100K_0402_5%

DMN65D8LDW-7_SOT363-6

+5VALW

12

RH505 100K_0402_5%

10K_0402_5%

SATA_LED_EN<36>

DMN63D8LDW-7_SOT363-6

@

0_0402_5% RH502

QE21A

12

61

2

QE20A

34

QE23B

5

DMN65D8LDW-7_SOT363-6

+1.8V_DVDD

12

RE146

61

2

VGS(th) = 0.8V -1.5V

+5VALW - Trace width : 20mil

+5VALW

JLED

LED1 LED2

4 3 2 1

6

4

G2

5

3

G1 2 1

ACES_51575-00401-001

CONN@

SP01002BY00

DVT1.0 Change net LED1 to LED2

LED2

34

5

QE21B

12

@

RE152 1M_0402_5%

DVT2.0 Add RE152(@) for EC reserved

DMN63D8LDW-7_SOT363-6

VGS(th) = 0.8V -1.5V

Screw Hole

CPU x 4 GPU x 2

HCPU1

@

H_4P0-G

HCPU3

@

H_3P7-G

@

H_2P8-G

@

H_2P8-G

@

H_3P3

@

H_3P0-G

1

H1

1

H7

1

H13

1

H19

1

HCPU2

@

1

H_4P0-G

HCPU4

@

1

DVT2.0

H_3P7-G

Change HCPU3, HCPU4 to H_3P7-G footprint.

GND Pad Hole x 16 Non-GND Pad Hole x 5

H2

@

1

H_2P8-G

H8

@

1

H_2P8-G

H14

@

1

H_2P8X3P4-G

DVT1.0 Change H14 to footprint H_2P8X3P4-G

H3

@

1

H_2P8-G

H15

@

1

H_2P8-G

HGPU1

@

H_4P0-G

1

HGPU2

@

1

H_4P0-G

DVT1.0 Change H5 to footprint H_3P3

H4

@

1

H_2P8-G

H10

@

1

H_2P8-G

H16

@

1

H_2P8-G

H5

@

1

H_3P3

H11

@

1

H_2P8-G

H17

@

1

H_2P8-G

Remove H6 12/21

Remove H12 12/21

H18

@

1

H_3P0-G

H20

@

1

H_2P8X3P4N

H9

@

1

H_2P8N

DVT1.0 Change H20 to footprint H_2P8X3P4N Change H21 to footprint H_2P8N Add H22 footprint H_2P8x3P4N Change H9 to footprint H_2P8N

FD1 FIDUCAL@

1

H21

@

1

H_2P8N

H23

@

1

H_4P5N

DVT2.0 Change H23 to H_4P5N footprint.

FD2 FIDUCIAL@

1

FD3 FIDUCAL@

1

H22

@

1

H_2P8X3P4N

FD4 FIDUCIAL@

1

PWR BOARD Connector

Pilot

B B

BREATH_LED#<36>

2

QE24A DMN65D8LDW-7_SOT363-6

R126 0_0402_5%

USB20_P8<19>

USB20_N8<19>

A A

Pilot Change R126, R127 footprint to R_0402-NPM

3 4

R127 0_0402_5%

5

+5VALW

12

61

DMN65D8LDW-7_SOT363-6

1 2

@

R_0402-NPM

TR5807

FP1@EMI@

12

MCM1012B900F06BP_4P

SM070003Z00

1 2

@

R_0402-NPM

RH506 100K_0402_5%

USB20_P8_R

USB20_N8_R

5

BREATH_LED_MB

34

QE24B

DVT1.0 Remove JPW1

4

Change RW4 to 0ohm 0402 short-pad footprint.

FPR_SCAN#<36>

Touch Finger Print module.

+3VS

1 2

RW4 0_040 2_5%@

POWER_SW#_MB BREATH_LED_MB

USB20_P8_R USB20_N8_R

FPR_SCAN#

2

3

D5225

@ESD@

1

TVNST52302AB0_SOT523-3

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

3

D5226

FP1@ESD@

1

TVNST52302AB0_SOT523-3

DVT2.0 Rename EU3405 to D5226.

2011/08/25 2012/07/25

3

+3V_FPSW

L03ESDL5V0CC3-2_SOT23-3

Compal Secret Data

+5VALW

JPW

1

2

3

4

5

6

7

8

9

G11

10

G12

ACES_51530-01001-P01

CONN@

SP010025K00

DVT2.0

2

3

Change JPW to ACE 51530-01001-P01

1

D5223

FP1@ESD@

C5235

+3V_FPSW

12

1U_0402_10V6K

Close to JPW

Deciphered Date

11 12

2

Power Button & LED (Reserve)

+5VALW

@

LED3

BREATH_LED_R2BREATH_LED_MB

21

HT-F196BP5_WHITE

DVT2.0 Change LED3 BOM option to @.

POWER_SW#_MB<36>

1

3

DEBUG@

RW3

1 2

300_0402_5%

DEBUG@

SW5

SKRBAAE010_4P

2

4

SN111005800

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

TPM/BTB conn.

LA-E992P

1.0(A00)

of

37 77Tuesday, July 25, 2017

1

5

4

3

2

1

LCD backlight PWR CTRL

F2

@

JCAM1

8

GND

7

GND

6

5

4

3

2

1

ACES_50228-0067N-001

CONN@

SP02000WS00

+INV_PWR_SRC

RV538 0_0402_5%@

1 2

AZ5125-01HPR7G_SOD523-2TS@

1

CV576

8.2P_0402_50V8D

2

USB20_N9<1 9>

USB20_P9<19>

PESD5V0U2BT_SOT23-3

10P_0402_25V8J

TS@ESD@

DVT2.0 Change RV538 to 0ohm 0402 short-pad footprint.

Pilot Change DI1 footprint to AZ5125-01HPR7G_SOD523-2

TOUCH_SCREEN_PD#<17>

+5VS

DVT1.0 Change DV2 to SCS00003800.

DV2

LCD_TST<36>

BIA_PWM_PCH<7,1 6>

PANEL_BKEN_EC<36>

EDP_TXN0<7>

EDP_TXP0<7>

EDP_TXN1<7>

EDP_TXP1<7>

EDP_TXN2<7>

EDP_TXP2<7>

EDP_TXN3<7>

EDP_TXP3<7>

EDP_AUXP<7>

EDP_AUXN<7>

3

1

2

BAT54CW_SOT323-3~D

BAT54CW-7-F_SOT323-3

SCS00003800

DVT2.0 Change RV566 to 0ohm 0402 short-pad footprint.

1 2

RV566 0_0402_5%@

12

1 2

CV581 0.1U_0402_10V 6K

1 2

CV580 0.1U_0402_10V 6K

1 2

CV586 0.1U_0402_10V 6K

1 2

CV585 0.1U_0402_10V 6K

1 2

CV588 0.1U_0402_10V 6K

1 2

CV587 0.1U_0402_10V 6K

1 2

CV590 0.1U_0402_10V 6K

1 2

CV589 0.1U_0402_10V 6K

1 2

CV592 0.1U_0402_10V 6K

1 2

CV591 0.1U_0402_10V 6K

12

RV537 100K_0402_5%

DISPOFF#

RV536 100K_0402_5%

EDP_TXN0_C

EDP_TXP0_C

EDP_TXN1_C

EDP_TXP1_C

EDP_TXN2_C

EDP_TXP2_C

EDP_TXN3_C

EDP_TXP3_C

EDP_AUXP_C

EDP_AUXN_C

INV_PWM

+5VS_TS

RZ26

1 2

@

0_0603_5%

Pilot Change RZ26 to 0603 0ohm short-pad footprint.

LCD_TST LCD_TST_R

DI1 RB751S40T1G_SOD523-2

EDP_HPD<16>

+EDPVDD

10U_0603_6.3V6M

CV577

1

@

2

B+

1 2

SMD1812P150TF/24 1.5A UL/CSA/TUV

QV11 SI3457BDV-T1-E3_TSOP6~D

D D

B+

12

CV578 1U_0603_25V6K

SE000006900

DVT1.0 Change CV578 to SE000006900

SIO_SLP_S3#<18,39,42,43,44,62>

2

G

SB934570010

12

RV535 1M_0402_5%

12

RV570 120K_0402_5%

13

D

QV2 L2N7002WT1G_SC-70-3

S

D

6

S

4 5

2 1

G

3

DVT1.0 Change RV570 to 120Kohm

60mil60mil

+INV_PWR_SRC

1

0.1U_0402_25V6

2

CV579

CCD +DMIC Circuit

C C

1 2

Pilot Change RZ37 to 0603 0ohm short-pad footprint.

USB20_P12<19>

USB20_N12<19>

B B

DMIC_DAT<23> DMIC_CLK<23>

1

@

2

A A

RZ37 0_0603_5%

Pilot Change RV545, RV547 footprint to R_0402-NPM

1 2

RV545 0_0402_5%

@EMI@

R_0402-NPM

LV22

EMI@

1 2

MCM1012B900F06BP_4P

SM070003Z00

1 2

RV547 0_0402_5%@EMI@

R_0402-NPM

USB20_P12_R USB20_N12_R DMIC_DAT DMIC_CLK

EC5205

6.8P_0402_50V8C

EC5206

6.8P_0402_50V8C

1

@

2

+3VS_CAM+3VS

@

34

CV582

USB20_P12_R

USB20_N12_R

0.1U_0402_10V6K

1

CV583

2

10U_0603_6.3V6M

8.2P_0402_50V8D

1

@

CV584

2

Need to check pin define

CCD +DMIC Connector

+3VS_CAM

1

CZ44

1U_0402_6.3V6K

PESD5V0U2BT_SOT23-3

2

3

ESD@

DV12

1

2

AZC199-02SPR7G_SOT23-3

3

ESD@

223

DA1

1

+INV_PWR_SRC

@RF@

CV922

1 2

1

2

USB20_P9_R USB20_N9_R

TS_EN

INV_PWM DISPOFF# EDP_HPD

eDP & TS Conn.

W=60mils

EDP_AUXP_C EDP_AUXN_C

EDP_TXP0_C EDP_TXN0_C

EDP_TXP1_C EDP_TXN1_C

EDP_TXP2_C EDP_TXN2_C

EDP_TXP3_C EDP_TXN3_C

Pilot Change RI1, RI2 footprint to R_0402-NPM

1 2

RI1 0_0402_5%

@TS@EMI@

R_0402-NPM

SM070003Z00

MCM1012B900F06BP_4P

1 2

LI1

1 2

RI2 0_0402_5%

USB20_P9_R

USB20_N9_R

2

3

DI3

1

TS@EMI@

@TS@EMI@

R_0402-NPM

34

JEDP1

1

GND

2

BATT_WHITE_LED

3

BATT_YELLOW_LED

4

BREATH_WHITE_LED

5

VR_SRC

6

VR_SRC

7

VR_SRC

8

NC

9

DISP_ON/OFF#

10

PWM

11

CONNTST_GND

12

VR_GND

13

VR_GND

14

VR_GND

15

LCD_B_CLK+

16

LCD_B_CLK-

17

GND

18

LVDS_B2+

19

LVDS_B2-

20

LVDS_B1+

21

LVDS_B1-

22

LVDS_B0+

23

LVDS_B0-

24

GND

25

LVDS_A_CLK+

26

LVDS_A_CLK-

27

GND

28

LVDS_A2+

29

LVDS_A2-

30

LVDS_A1+

31

LVDS_A1-

32

LVDS_A0+

33

LVDS_A0-

34

EDID_DATA

35

EDID_CLK

36

BIST

37

V_EDID

38

LCD_VDD

39

LCD_VDD CONNTST40MGND1

ACES_59003-04006-001

CONN@

SP01001BT00

USB20_N9_R

USB20_P9_R

MGND6 MGND5 MGND4 MGND3 MGND2

46 45 44 43 42 41

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/08/25 2012/07/25

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

eDP /TS conn.

LA-E992P

1

1.0(A00)

of

38 77Tuesday, July 25, 2017

5

UT1

TBT@

4

3

2

1

1 2

S IC JHL6340 SLLSP C1 THUNDERBOLT A31!

SA00009YL3L

PCIE X4 Bus

D D

DVT2.0 Change RT2 to 0 ohm 0201 short-pad footprint.

10K_0201_5%

TBT_TDI TBT_TMS TBT_TCK TBT_TDO

RPT1

1 8 2 7 3 6 4 5

100K_0804_8P4R_5%T BT@

1 2 1 2 1 2 1 2 1 2

+3VS_TBT

DVT1.0 Remove JTAG

Reserve for common DP design

DDI1_AUXN DDI2_AUXN DDI1_AUXP DDI2_AUXP TBT_CLK_REQ#

+3.3V_LC

C C

10K_0201_5%

12

RT7

RT6

TBT@

TBTA_LSTX TBT_CLK_REQ#_R

DPSNK1_DDC_CLK DPSNK1_DDC_DATA DPSNK2_DDC_CLK DPSNK2_DDC_DATA

B B

CPU_DDI1HPD CPU_DDI2HPD TBTA_LSTX TBTA_HPD TBTA_LSRX

A A

10K_0201_5%

12

RT8

TBT@

1 2

RT76 100K_0201_5%@

1 2

RT77 100K_0201_5%@

1 2

RT78 100K_0201_5%@

1 2

RT79 100K_0201_5%@

1 2

RT24 10K_0201_5%@

10K_0201_5%

12

RT9

TBT@

12

RT21 10K_0201_5%@ RT20 10K_0201_5%T BT@

RT38 100K_0201_5%TBT@ RT39 100K_0201_5%TBT@ RT40 1M_0201_1%TBT@ RT41 100K_0201_5%TBT@ RT42 1M_0201_1%TBT@

PCIE CLK

CPU DDI1

CPU DDI2

+3VS_TBT

12 12

+3VS

SIO_SLP_S3#_AR

PCIE_PTX_TBTRX_P1<19> PCIE_PTX_TBTRX_N1<19>

PCIE_PTX_TBTRX_P2<19> PCIE_PTX_TBTRX_N2<19>

PCIE_PTX_TBTRX_P3<19> PCIE_PTX_TBTRX_N3<19>

PCIE_PTX_TBTRX_P4<19> PCIE_PTX_TBTRX_N4<19>

CLK_PCIE_P5<17> CLK_PCIE_N5<17>

TBT_CLK_REQ#<17>

CPU_DDI1_P0<7> CPU_DDI1_N0<7>

CPU_DDI1_P1<7> CPU_DDI1_N1<7>

CPU_DDI1_P2<7> CPU_DDI1_N2<7>

CPU_DDI1_P3<7> CPU_DDI1_N3<7>

DDI1_AUXP< 7> DDI1_AUXN<7>

CPU_DDI1HPD<16>

CPU_DDI2_P0<7> CPU_DDI2_N0<7>

CPU_DDI2_P1<7> CPU_DDI2_N1<7>

CPU_DDI2_P2<7> CPU_DDI2_N2<7>

CPU_DDI2_P3<7> CPU_DDI2_N3<7>

DDI2_AUXP< 7> DDI2_AUXN<7>

CPU_DDI2HPD<16>

USB3_A_TRX_DTX_P1<41> USB3_A_TRX_DTX_N1<41>

USB3_A_TTX_C_DRX_P1<41> USB3_A_TTX_C_DRX_N1<41>

USB3_A_TTX_C_DRX_P0<41> USB3_A_TTX_C_DRX_N0<41>

USB3_A_TRX_DTX_P0<41> USB3_A_TRX_DTX_N0<41>

TBT_A_AUX_P_C<41> TBT_A_AUX_N_C<41>

TBT_A_USB20_P<41> TBT_A_USB20_N<41>

TBTA_LSTX<41> TBTA_LSRX<41> TBTA_HPD<41>

DVT2.0 Change RT110 to 0 ohm 0201 short-pad footprint.

1 2

RT110 0_0201_5%@

CT3 0.22U_0201_6.3VTBT@

1 2

CT15 0.22U_0201_6.3VTBT@

1 2

CT1 0.22U_0201_6.3VTBT@

1 2

CT13 0.22U_0201_6.3VTBT@

1 2

CT4 0.22U_0201_6.3VTBT@

1 2

CT18 0.22U_0201_6.3VTBT@

1 2

CT5 0.22U_0201_6.3VTBT@

1 2

CT21 0.22U_0201_6.3VTBT@

12

@

RT2 0_0201_5%

1 2

CT6 0.1U_0201_6.3V6KTBT@

1 2

CT7 0.1U_0201_6.3V6KTBT@

1 2

CT8 0.1U_0201_6.3V6KTBT@

1 2

CT9 0.1U_0201_6.3V6KTBT@

1 2

CT10 0.1U_0201_6.3V6KTBT@

1 2

CT23 0.1U_0201_6.3V6KTBT@

1 2

CT11 0.1U_0201_6.3V6KTBT@

1 2

CT24 0.1U_0201_6.3V6KTBT@

1 2

CT25 0.1U_0201_6.3V6KTBT@

1 2

CT26 0.1U_0201_6.3V6KTBT@

1 2

CT27 0.1U_0201_6.3V6KTBT@

1 2

CT28 0.1U_0201_6.3V6KTBT@

1 2

CT29 0.1U_0201_6.3V6KTBT@

1 2

CT30 0.1U_0201_6.3V6KTBT@

1 2

CT31 0.1U_0201_6.3V6KTBT@

1 2

CT32 0.1U_0201_6.3V6KTBT@

1 2

CT33 0.1U_0201_6.3V6KTBT@

1 2

CT34 0.1U_0201_6.3V6KTBT@

1 2

CT35 0.1U_0201_6.3V6KTBT@

1 2

CT36 0.1U_0201_6.3V6KTBT@

12

TBT@

RT19 14K_0402_1%

12

TBT@

RT25 4.75K_04 02_0.5%

1 2

CT39 0.22U_0201_6.3VTBT@

1 2

CT40 0.22U_0201_6.3VTBT@

1 2

CT41 0.22U_0201_6.3VTBT@

1 2

CT42 0.22U_0201_6.3VTBT@

1 2

CT43 0.1U_0201_6.3V6KTBT@

1 2

CT44 0.1U_0201_6.3V6KTBT@

12

TBT@

RT43 499_0201_1%

SIO_SLP_S3# <18,38,42,43,44,62>

PCIE_PTX_TBTRX_P1_C PCIE_PTX_TBTRX_N1_C

PCIE_PTX_TBTRX_P2_C PCIE_PTX_TBTRX_N2_C

PCIE_PTX_TBTRX_P3_C PCIE_PTX_TBTRX_N3_C

PCIE_PTX_TBTRX_P4_C PCIE_PTX_TBTRX_N4_C

TBT_CLK_REQ#_R

CPU_DP1_P0_C CPU_DP1_N0_C

CPU_DP1_P1_C CPU_DP1_N1_C

CPU_DP1_P2_C CPU_DP1_N2_C

CPU_DP1_P3_C CPU_DP1_N3_C

CPU_DP1_AUXP_C CPU_DP1_AUXN_C

CPU_DDI1HPD

DPSNK1_DDC_CLK DPSNK1_DDC_DATA

CPU_DP2_P0_C CPU_DP2_N0_C

CPU_DP2_P1_C CPU_DP2_N1_C

CPU_DP2_P2_C CPU_DP2_N2_C

CPU_DP2_P3_C CPU_DP2_N3_C

CPU_DP2_AUXP_C CPU_DP2_AUXN_C

CPU_DDI2HPD

DPSNK2_DDC_CLK DPSNK2_DDC_DATA

DPSNK_RBIAS

TBT_TDI TBT_TMS TBT_TCK TBT_TDO

TBT_RBIAS TBT_RSENSE

USB3_A_TTX_DRX_P1 USB3_A_TTX_DRX_N1

USB3_A_TTX_DRX_P0 USB3_A_TTX_DRX_N0

TBT_A_AUX_P TBT_A_AUX_N

TBT_A_USB20_P TBT_A_USB20_N

TBTA_LSTX TBTA_LSRX TBTA_HPD

PA_USB2_RBIAS PB_USB2_RBIAS

UT1A

Y23

PCIE_RX0_P

Y22

PCIE_RX0_N

T23

PCIE_RX1_P

T22

PCIE_RX1_N

M23

PCIE_RX2_P

M22

PCIE_RX2_N

H23

PCIE_RX3_P

H22

PCIE_RX3_N

V19

PCIE_REFCLK_100_IN_P

T19

PCIE_REFCLK_100_IN_N

AC5

PCIE_CLKREQ_N

AB7

DPSNK0_ML0_P

AC7

DPSNK0_ML0_N

AB9

DPSNK0_ML1_P

AC9

DPSNK0_ML1_N

AB11

DPSNK0_ML2_P

AC11

DPSNK0_ML2_N

AB13

DPSNK0_ML3_P

AC13

DPSNK0_ML3_N

Y11

DPSNK0_AUX_P

W11

DPSNK0_AUX_N

AA2

DPSNK0_HPD

Y5

DPSNK0_DDC_CLK

R4

DPSNK0_DDC_DATA

AB15

DPSNK1_ML0_P

AC15

DPSNK1_ML0_N

AB17

DPSNK1_ML1_P

AC17

DPSNK1_ML1_N

AB19

DPSNK1_ML2_P

AC19

DPSNK1_ML2_N

AB21

DPSNK1_ML3_P

AC21

DPSNK1_ML3_N

Y12

DPSNK1_AUX_P

W12

DPSNK1_AUX_N

Y6

DPSNK1_HPD

Y8

DPSNK1_DDC_CLK

N4

DPSNK1_DDC_DATA

Y18

DPSNK_RBIAS

Y4

TDI

V4

TMS

T4

TCK

W4

TDO

H6

RBIAS

J6

RSENSE

A15

PA_RX1_P

B15

PA_RX1_N

A17

PA_TX1_P

B17

PA_TX1_N

A19

PA_TX0_P

B19

PA_TX0_N

B21

PA_RX0_P

A21

PA_RX0_N

Y15

PA_DPSRC_AUX_P

W15

PA_DPSRC_AUX_N

E20

PA_USB2_D_P

D20

PA_USB2_D_N

A5

PA_LS_G1

A4

PA_LS_G2

M4

PA_LS_G3

H19

PA_USB2_RBIAS

AC23

THERMDA

AB23

THERMDA

V18

PCIE_ATEST

AC1

TEST_EDM

L15

FUSE_VQPS_64

N15

FUSE_VQPS_128

C23

MONDC_CIO_0

C22

MONDC_CIO_1

PCIE_PRX_TBTTX_P1_C

V23

PCIE_TX0_P PCIE_TX0_N

PCIE_TX1_P PCIE_TX1_N

PCIE_TX2_P PCIE_TX2_N

PCIE_TX3_P

SOURCE PORT 0

PCIE_TX3_N

PERST_N

PCIE_RBIAS

DPSRC_ML0_P DPSRC_ML0_N

DPSRC_ML1_P DPSRC_ML1_N

DPSRC_ML2_P DPSRC_ML2_N

DPSRC_ML3_P DPSRC_ML3_N

DPSRC_AUX_P DPSRC_AUX_N

DPSRC_HPD

DPSRC_RBIAS

PCIe GEN3

SINK PORT 0

LC GPIOPOC GPIO

POC_GPIO_0 POC_GPIO_1 POC_GPIO_2 POC_GPIO_3 POC_GPIO_4

TEST_PWR_GOOD

Misc

XTAL_25_OUT

PB_DPSRC_AUX_P

PB_DPSRC_AUX_N

PORT B

PB_USB2_D_P PB_USB2_D_N

POC

PB_USB2_RBIAS

MONDC_DPSNK_0

MONDC_DPSNK_1

MONDC_DPSRC

ALPINE-RIDGE_BGA337@

POC_GPIO_5 POC_GPIO_6

TEST_EN

RESET_N

XTAL_25_IN

EE_CS_N

PB_RX1_P PB_RX1_N

PB_TX1_P PB_TX1_N

PB_TX0_P PB_TX0_N

PB_RX0_P PB_RX0_N

PB_LS_G1 PB_LS_G2 PB_LS_G3

MONDC_SVR

ATEST_P ATEST_N

USB2_ATEST

SINK PORT 1

MISC

Port A

TBT PORTS

POC

DEBUG

GPIO_0 GPIO_1 GPIO_2 GPIO_3 GPIO_4 GPIO_5 GPIO_6 GPIO_7 GPIO_8

EE_DI

EE_DO

EE_CLK

PCIE_PRX_TBTTX_N1_C

V22

PCIE_PRX_TBTTX_P2_C

P23

PCIE_PRX_TBTTX_N2_C

P22

PCIE_PRX_TBTTX_P3_C

K23

PCIE_PRX_TBTTX_N3_C

K22

PCIE_PRX_TBTTX_P4_C

F23

PCIE_PRX_TBTTX_N4_C

F22

TBT_RST#_R

L4

PCIE_RBIAS

N16

R2 R1

N2 N1

L2 L1

J2 J1

TBT_SRC_AUX_P

W19

TBT_SRC_AUX_N

Y19

TBT_SRC_HPD

G1

DPSRC_RBIAS

N6

U1 U2

TBT_EE_WP_N

V1

TBT_TMU_CLK_OUT

V2

TBT_PCIE_WAKE_N

W1

TBT_CIO_PLUG_EVENT#

W2

TBT_HDMI_DDC_DATA

Y1

TBT_HDMI_DDC_CLK

Y2

TBT_SRC_CFG1

AA1

TBTA_I2C_INT

J4

TBTB_I2C_INT

E2

RTD3_USB_PWR_EN_R

D4

TBT_FORCE_PWR_R

H4 F2

BATLOW# SIO_SLP_S3#_AR

D2

RTD3_CIO_PWR_EN_R

F1

TBT_TEST_EN

E1

TBT_TEST_PWG

AB5

TBT_RESET_N

F4

TBT_XTAL_25_IN

D22

TBT_XTAL_25_OUT

D23

TBT_EE_DI

AB3

TBT_EE_DO

AC4

TBT_EE_CS_N

AC3

TBT_EE_CLK

AB4

B7 A7

A9 B9

A11 B11

A13 B13

Y16 W16

E19 D19

NC_B4

B4

NC_B5

B5

NC_G2

G2

F19

D6

A23 B23

E18

W13

W18

AB2

RT1 0_0201_5%@

1 2

RT3 3.01K_0201_1%TBT@

1 2

RT5 14K_0402_1%TBT@

1 2

RT10 0_0201_5%@

1 2

RT11 1M_0201_1%TBT@

1 2

RT13 0_0201_5%@

1 2

RT16 0_0201_5%@

1 2

RT17 100_0201_5%TBT@

1 2

RT18 100_0201_5%TBT@

1 2

RT121 0_0201_5%@

1 2

TBT@

RT44 499_0201_1%

RT49 2.2K_0402_5%TBT@ RT50 2.2K_0402_5%TBT@

1 2

RT48 3.3K_0402_5%TBT@

12

CT140.22U_0201_6.3V TBT @

12

CT160.22U_0201_6.3V TBT @

12

CT120.22U_0201_6.3V TBT @

12

CT20.22U_0201_6.3V TBT@

12

CT1090.22U_0201_6.3V TBT@

12

CT1080.22U_0201_6.3V TBT@

12

CT1110.22U_0201_6.3V TBT@

12

CT1100.22U_0201_6.3V TBT@

12

PCIE_PRX_TBTTX_P1 <19> PCIE_PRX_TBTTX_N1 <19>

PCIE_PRX_TBTTX_P2 <19> PCIE_PRX_TBTTX_N2 <19>

PCIE_PRX_TBTTX_P3 <19> PCIE_PRX_TBTTX_N3 <19>

PCIE_PRX_TBTTX_P4 <19> PCIE_PRX_TBTTX_N4 <19>

PCH_PLTRST#_EC <17,27,28,29,33,36,46>

Closed to UT1

TBT_I2C_SDA TBT_I2C_SCL

DVT1.0 Un-pop RT30

T25@ T26@

TBT_I2C_SDA <41> TBT_I2C_SCL <41>

T7@ T9@

DVT2.0 Change RT121 to 0 ohm 0201 short-pad footprint.

1 2

RT116 33_0201_5%

TBT@EMI@

1 2

RT117 33_0201_5%

TBT@EMI@

Close to UT1

TBT_EE_CLK TBT_EE_CLK_R

12 12

1 2

RT101 15_0201_1%

TBT@EMI@

TBT_EE_CS_N TBT_EE_DO TBT_EE_WP_N TBT_EE_CLK_R

TBT_PCIE_WAKE_N TBT_CIO_PLUG_EVENT# SIO_SLP_S3#_AR BATLOW# TBTA_I2C_INT TBTB_I2C_INT NC_B4 TBT_FORCE_PWR_R TBT_RESET_N

TBT_SRC_HPD

PCIE_WAKE# <18,28,33,36> TBT_CIO_PLUG_EVENT# <16>

TBTA_I2C_INT <41>

TBT_FORCE_PWR <17>

RTD3_CIO_PWR_EN <17>

TBT_RESET_N <41>

TBT_RESET_N_EC# <36,41>

TBT_XTAL_25_IN_R

TBT_XTAL_25_OUT_R

TBT_TMU_CLK_OUT TBT_FORCE_PWR_R RTD3_CIO_PWR_EN_R RTD3_USB_PWR_EN_R

NC_B4 NC_B5 NC_G2

TBT@

UT2

1

CS# DO(IO1) WP#(IO2) GND

HOLD#(IO3)

DI(IO0)

VCC

CLK

2 3 4

W25Q80DVSSIG_SO8

SA00003EW10

1 2

12 12 12 12 12 12 12 12 12 12 12

RT26 3.3K_0201_5%TBT@ RT27 3.3K_0201_5%TBT@ RT28 10K_0201_5%@ RT29 10K_0201_5%TBT@ RT30 10K_0201_5%@ RT31 10K_0201_5%TBT@ RT32 10K_0201_5%TBT@ RT33 10K_0201_5%TBT@ RT86 10K_0201_5%@ RT94 10K_0201_5%@ RT80 10K_0201_5%@

RT4 1M_0201_1%TBT@

DVT1.0 Un-pop RT80

DVT2.0 Change RT13, RT16 to 0 ohm 0201 short-pad footprint.

27P_0402_50V8J

TBT@

CT38

1 2

3

4

GND

TBT@

YT1

2

GND

SJ10000TZ00

RT34 100K_0201_5%TBT @ RT35 100K_0201_5%TBT @ RT36 100K_0201_5%TBT @ RT37 100K_0201_5%TBT @

RT45 100K_0201_5%TBT @ RT46 100K_0201_5%TBT @ RT47 100K_0201_5%TBT @

DVT1.0 Remove RT98, RT99, RT100

8

TBT_HOLD_N

7 6

TBT_EE_DI

5

1

TBT@

1 2

27P_0402_50V8J CT37

1 2 1 2 1 2 1 2

1 2 1 2 1 2

DVT1.0 Remove Off- page connector

+3.3V_FLASH

1

CT45

0.1U_0201_6.3V6K

TBT@

2

+3.3V_TBT_SX

12

25MHZ 20PF +-10PPM 7M25000153

RT513.3K_0402_5% TBT@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2016/01/06 2016/09/18

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

Thunderbolt (1/2)

LA-E992P

1

39 77Tuesday, July 25, 2017

1.0(A00)

of

5

4

3

2

1

+3VS_TBT+3.3V_TBT_SX+3VALW +3VALW

+3VS

1 2

RT95 0_0603_5%@

1 2

RT124 0_0603_5%TBT@

Follow Berlineta

CT77

TBT@

CT54

TBT@

1

2

1

2

+0.9V_USB

1U_0201_6.3V6M

CT56

1U_0201_6.3V6M

TBT@

CT57

TBT@

CT116

47U_0603_6.3V6M

1

@

2

+0.9V_DP

1U_0201_6.3V6M

1

CT58

TBT@

2

1U_0201_6.3V6M

1

2

CT78

TBT@

1

CT59

CT60

TBT@

2

1U_0201_6.3V6M

1

CT70

CT55

TBT@

2

+0.9V_CIO

1U_0201_6.3V6M

1

CT79

TBT@

2

1

CT80

TBT@

2

1U_0201_6.3V6M

CT85

1

2

1

2

TBT@

1U_0201_6.3V6M

CT61

TBT@

+0.9V_PCIE

1U_0201_6.3V6M

CT71

1

2

TBT@

1U_0201_6.3V6M

CT86

1

2

1

2

TBT@

1U_0201_6.3V6M

CT62

TBT@

1U_0201_6.3V6M

CT72

47U_0603_6.3V6M

1

TBT@

2

1U_0201_6.3V6M

1

2

1U_0201_6.3V6M

1

TBT@

2

+3.3V_ANA_PCIE +3.3V_ANA_USB2

1U_0201_6.3V6M

1

2

1U_0201_6.3V6M

1

TBT@

2

L8 L11 L12

M8 T11 T12

L6

M6

V11 V12 V13

M13 M15 M16

L19

N19

L18

M18 N18

R15 R16

R8

R9

R11 R12

L16 J16

A6

A8 A10 A12 A14 A16 A18 A20 A22

B6

B8 B10 B12 B14 B16 B18 B20 B22

D8

D9 D11 D12 D13 D15 D16 D18

E8

E9 E11 E15 E16 E22 E23

F9

F16

F20 G22 G23

H1

H2 H12 H13 H15 H16 H20

J5 J18 J19 J20 J22 J23

K1

K2

L5 L20 L22 L23

M1 M2

M5 M19 M20

N5 N20 N22 N23

0.1U_0201_6.3V6K

1

CT46

TBT@

2

UT1B

VCC0P9_DP VCC0P9_DP VCC0P9_DP VCC0P9_DP VCC0P9_DP VCC0P9_DP VCC0P9_ANA_DPSRC VCC0P9_ANA_DPSRC VCC0P9_ANA_DPSNK VCC0P9_ANA_DPSNK VCC0P9_ANA_DPSNK

VCC0P9_PCIE VCC0P9_PCIE VCC0P9_PCIE VCC0P9_ANA_PCIE_1 VCC0P9_ANA_PCIE_1 VCC0P9_ANA_PCIE_2 VCC0P9_ANA_PCIE_2 VCC0P9_ANA_PCIE_2

VCC0P9_USB VCC0P9_USB

VCC0P9_CIO VCC0P9_CIO VCC0P9_CIO VCC0P9_CIO

VCC3P3_ANA_PCIE VCC3P3_ANA_USB2

VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA

@

CT48

CT115

1 2

@

RT97 0_0402_5%

Pilot Change RT97 to 0ohm

D D

C C

B B

A A

0402 short-pad footprint.

CT47

+3.3V_TBT_SX+3.3V_LC

TBT@

R6

VCC3P3_LC

VSS_ANAP1VSS_ANAP2VSS_ANAR5VSS_ANA

1U_0201_6.3V6M

1

2

R18

R19

+3.3V_TBT_S0

R13

F8

VCC3P3_SX

GND VCC

VSS_ANA

R20

R22

R23

LT4

1 2

LQM18PN1R0MFHD_2P

H9

VCC3P3_SVR VCC3P3_SVR VCC3P3_SVR

VCC3P3A

VCC3P3_S0

VCC0P9_SVR

VCC0P9_SVR VCC0P9_SVR_ANA VCC0P9_SVR_ANA VCC0P9_SVR_ANA VCC0P9_SVR_ANA VCC0P9_SVR_ANA VCC0P9_SVR_ANA

VCC0P9_SVR_SENSE

VCC0P9_LVR VCC0P9_LVR VCC0P9_LVR

VCC0P9_LVR_SENSE

VSS_ANAT1VSS_ANAT2VSS_ANAT5VSS_ANA

VSS_ANA

ALPINE-RIDGE_BGA337

T20

U23

U22

TBT@

CT49

SVR_IND SVR_IND SVR_IND

SVR_VSS SVR_VSS SVR_VSS

VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

TBT@

1

2

A2 A3 B3

L9 M9 E12 E13 F11 F12 F13 F15 J9

C1 C2 D1

A1 B1 B2

F18 H18 J11 H11

V5 V6 V8 V9 V15 V16 V20 W5 W6 W8 W9 W20 W22 W23 Y9 Y13 Y20 AA22 AA23 AB6 AB8 AB10 AB12 AB14 AB16 AB18 AB20 AB22 AC6 AC8 AC10 AC12 AC14 AC16 AC18 AC20 AC22 D5 E4 E5 E6 F5 F6 H5 H8 J8 J12 J13 J15 L13 M11 M12 N8 N9 N11 N12 N13 T6 T8 T9 T13 T15 T16 T18 AB1 AC2

1U_0201_6.3V6M

+3VS_TBT

1

CT50

TBT@

2

CT63

TBT@

TBT_SVR_IND

0.6UH_MND-04ABIR60M-XGL_20%

+0.9V_LVR_OUT

10U_0402_6.3V6M

CT51

TBT@

1U_0201_6.3V6M

1

2

CT81

TBT@

10U_0402_6.3V6M

1

CT52

TBT@

2

1

CT64

TBT@

2

LT1

TBT@

1 2

10U_0402_6.3V6M

1

2

1U_0201_6.3V6M

CT82

TBT@

1

2

CT65

TBT@

10U_0402_6.3V6M

1

CT53

TBT@

2

CT73

TBT@

1

2

+0.9V_SVR

1U_0201_6.3V6M

1

2

10U_0402_6.3V6M

1

2

CT83

TBT@

CT66

TBT@

47U_0603_6.3V6M

CT74

TBT@

1

2

1U_0201_6.3V6M

1

CT67

CT68

TBT@

2

47U_0603_6.3V6M

1

CT75

TBT@

2

1U_0201_6.3V6M

1

CT84

TBT@

2

1U_0201_6.3V6M

1

CT69

TBT@

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2016/01/06 2016/09/18

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

Thunderbolt (2/2)

LA-E992P

1

1.0(A00)

of

40 77Tuesday, July 25, 2017

5

D D

TYPEC_SMBDA<36>

TYPEC_SMBCLK<36>

C C

B B

A A

+3.3V_FLASH

RT68 100K_0201_5%PD@ RT69 100K_0201_5%PD@ RT71 100K_0201_5%PD@ RT72 100K_0201_5%PD@

PD_I2C_SCL_R PD_I2C_SDA_R

12

PD@

RT112 10K_0201_5%

12

PD@

RT113 100K_0201_5%

TBT_CONFIG

12 12 12 12

RT118 0_0402_5%@ RT119 0_0402_5%@

1 2

RT53 0_0402_5%

Pilot Change RT53 to 0ohm 0402 short-pad footprint.

DVT2.0 Change RT120 to 0ohm 0402 short-pad footprint.

UPD1_ALERT<36>

DVT2.0 Change net UPD_SMBINT# to UPD1_ALERT

TBTA_DIG_AUD_P TBTA_DIG_AUD_N TBTA_DEBUG1 TBTA_DEBUG2

TBT_A_AUX_P_C<39> TBT_A_AUX_N_C<39>

12 12

BUSPOWERZ Sampled by ADC at boot. Tie pin to LDO_3V3 through a 100-kohm resistor to disable PP_EXT power path during dead-battery or no-battery boot conditions.

5

+3VALW_PD+3VALW

@

DVT1.0 Change RT123.2 connect to net PD_EE_CLK_R

TBTA_DEBUG1 TBTA_DEBUG2

1 2

RT59 0_0201_5%@

1 2

RT60 0_0201_5%@

RT120 0_0402_5%@

PD_EE_CLK_R

TBT_RESET_N_EC#<36,39>

100K_0201_5%

1

2

10K_0201_5%

12

TBTA_LSTX<39> TBTA_LSRX<39>

+3.3V_TBT_SX

PD@

RT70

PD@

RT73

CT88

0.1U_0402_10V6K

PD@

+3VS

12

RT57

@

12

RT58 10K_0201_5%

@

RT123 15_0201_1%TBT@EMI@

RT62 100K_0201_5%PD@

RT122 0_0201_5%@

RT63 100K_0201_5%PD@

TBTA_HRESET<36>

12

DVT2.0 Change RT83 to 0 ohm 0201 short-pad footprint.

TBTA_HPD<39>

12

TBT_A_USB20_P<39> TBT_A_USB20_N<39>

12

1 2

RT114 0_0201_5%@

1 2

RT115 0_0201_5%@

+3.3V_FLASH

PD@

RT75

15K_0402_0.1%

4

CT90

PD@

CT98

Master0:0 ohm Slave1:93.1K ohm

1 2

1

2.2U_0603_16V6K

PD@

RT83 0_0201_5%@

PD_I2C_SDA_R PD_I2C_SCL_R PD_I2C_INT#

TBT_CONFIG

TI's Request

12

CT99

4.7U_0603_10V6K

2

PD@

1 2

TBT_I2C_SDA<39> TBT_I2C_SCL<39>

TBTA_I2C_INT<39>

DVT1.0 Remove T64

T65 @

12

RT1111M_0201_1% PD@

T4936 @

T121 @

DVT1.0 Remove T70

PD_EE_CLK PD_EE_DI PD_EE_DO PD_EE_CS_N

TBT_A_USB20_P TBT_A_USB20_N

PD_UART

T62 @ T63 @

TBTA_MRESET

TBTA_LSTX TBTA_LSRX

TBTA_DIG_AUD_P TBTA_DIG_AUD_N

TBTA_DEBUG1 TBTA_DEBUG2

TBT_A_AUX_P_C TBT_A_AUX_N_C

BUSPOWER#

@

0_0201_5%

RT74

TBTA_ROSC

TBTA_HRESET

DVT2.0

12

Change RT108 to 0 ohm 0201 short-pad footprint.

@

RT108 0_0201_5%

TBTA_HRESET might be connected to EC or PCH to allow TPS65982 FW load

Active high hardware reset input. Will re-load settings from optional external flash memory. Ground pin when HRESET functionality will not be used.

DVT1.0 Add RT125(3.3K), RT126(3.3K), RT127(3.3K), RT128(3.3K), UT5, CT117(0.1u)

4

+3VALW_PD

1

2

F1

D1 D2 C1

A5 B5 B6

B2

C2 D10 G11 C10 E10 G10

D7

H6

A3

B4

A4

B3

L5

K5

E2

F2

F4

G4

E11

L4

K4

L3

K3

L2

K2

J1

J2

F10

G2

D6

+3.3V_FLASH

1

2

PD@

CT101 1U_0402_6.3V6K

UT4

I2C_ADDR

I2C_SDA1 I2C_SCL1 I2C_IRQ1_N

I2C_SDA2 I2C_SCL2 I2C_IRQ2_N

GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8

SPI_CLK SPI_MOSI SPI_MISO SPI_SS_N

USB_RP_P USB_RP_N

UART_TX UART_RX

SWD_DATA SWD_CLK

MRESET

TBT_LSTX/R2P TBT_LSRX/P2R

DIG_AUD_P/DEBUG3 DIG_AUD_N/DEBUG4

DEBUG1 DEBUG2

AUX_P AUX_N

BUSPOWER_N

R_OSC

HRESET

SA0000AK400

RT125 3.3K_0201_5%PD@ RT126 3.3K_0201_5%PD@ RT127 3.3K_0201_5%PD@ RT128 3.3K_0201_5%PD@

PD_EE_CS_N PD_EE_DO PD_EE_WP#

22U_0603_6.3V6M

1

CT91

PD@

2

TBTA_LDO_BMC +1.8VD_TBTA_LDO +1.8VA_TBTA_LDO

CT100

4.7U_0603_10V6K

PD@

H1

B1

VIN_3V3

12 12 12 12

UT5

1

CS#

2

DO

3

WP#

4

GND

W25X20CLSNIG_SO8

SA00003GM30

PD@

EMI Clip

CONN@

CLP1 EMIST_SUL-12A2M_1P

EC0M5000700

3

+TBTA_VBUS+5VALW

60mil 3A

22U_0603_6.3V6M

1

CT92

PD@

2

K1

VDDIO

A1

LDO_1V8A

GND

HOLD#

1

2

A2

LDO_1V8D

GNDE5GND

E6

VCC

CLK

DI

CT93

PD@

E1

LDO_BMC

GND

F5

E7

8 7 6 5

GND

G5

PD_EE_DO PD_EE_CS_N PD_EE_WP# PD_EE_HOLD#

22U_0603_6.3V6M

1

2

A11

B11

H10

C11

PP_5V0

PP_CABLE

GND

GNDF6GNDF7GND

GND

GNDH4GND

E8

B8

D8

H5

PD_EE_HOLD# PD_EE_CLK_R PD_EE_DI

CONN@

CLP2 EMIST_SUL-12A2M_1P

EC0M5000700

D11

F8

PP_5V0

G6

PP_FCMA6PP_FCMA7PP_FCMA8PP_FCM

GND

GNDG7GND

G8

GNDH7GND

H8

1

PD@

CT104

0.22U_0402_10V4Z

2

+3.3V_FLASH

60mil 3A Change DT1 and add DT15 follow E-team's design for DELL dat.04/07

12

Close to UT4

B10

A10

SENSEP

1

CT117

0.1U_0201_6.3V6K

PD@

2

3

SENSEN

HV_GATE1B9HV_GATE2

VBUS VBUS VBUS VBUS

VOUT_3V3

LDO_3V3

C_USB_TP

C_USB_TN

C_USB_BP C_USB_BN

C_CC1 C_CC2

RPD_G1 RPD_G2

DEBUG_CTL1 DEBUG_CTL2

C_SBU1

C_SBU2

RESET_N

A9

B7

GND

SN1610042ZQZR BGA 96P_BGA96

L1

PD@

CONN@

CLP3 EMIST_SUL-12A2M_1P

EC0M5000700

PD@

CT106 1U_0603_25V6K

H11 J10 J11 K11

H2

G1

K6 L6

K7 L7

L9 L10

K9 K10

E4 D5

K8

L8

F11

L11

NC

CONN@

CLP4 EMIST_SUL-12A2M_1P

EC0M5000700

12

DT1 RB751S40T1G_SOD523-2

AZ5125-01HPR7G_SOD523-2

PD@ESD@

DVT1.0 Change DT1 to SC100000S00

Pilot Change DT1 footprint to AZ5125-01HPR7G_SOD523-2

1 2

@

RT61 0_0201_5%

1

CT102 1U_0201_6.3V6M

PD@

2

TBT_A_USB20_PT TBT_A_USB20_NT

TBT_A_USB20_PB TBT_A_USB20_NB

TBTA_CC1 TBTA_CC2

DEBUG_CTL1 DEBUG_CTL2

TBTA_SBU1

TBTA_SBU2

PD@

1 2

CT112 220P_0201_25V7K

1 2

CT113 220P_0201_25V7K

PD@

Differential Signal

TBT_RESET_NRESET_N

1 2

@

RT102 0_0201_5%

DVT1.0 Un-pop RT102

USB3_A_TTX_C_DRX_P0<39> USB3_A_TTX_C_DRX_N0<39>

CT94 0.01U_0402_50V7KTBT@

CT95 0.01U_0402_50V7KTBT@

USB3_A_TRX_DTX_N1<39> USB3_A_TRX_DTX_P1<39>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

+3.3V_TBT_SX+3.3V_TBT_SX_R

+3.3V_FLASH

1

CT103 10U_0402_6.3V6M

PD@

2

TI's Requirement

1 2

TBTA_CC1

TBT_A_USB20_L_PT

TBTA_SBU1

1 2

2016/01/06 2016/09/18

2

3

DT15 PESD24VS2UT_SOT23-3

PD@ESD@

1

+3.3V_FLASH

12

PD@

RT66

10K_0201_5%

TBT_RESET_N <39>

+TBTA_VBUS +TBTA_VBUS

RT67 10K_0201_5%

JUSBC1

6

GND10

3

GND7

4

GND8

B1

GND4

B2

SSTXP2

B3

SSTXN2

B4

VBUS4

B5

CC2

B6

DP2

B7

DN2

B8

SBU2

B9

VBUS3

B10

SSRXN1

B11

SSRXP1

B12

GND3

JAE_DX07S024JJ7R1200

JAE_DX07S024JJ7R1200_24P-T

CONN@

LTCX0074A1L

Compal Secret Data

Deciphered Date

2

Bottom

DVT2.0 Change DT2, DT3, DT4, DT5, DT6, DT7, DT8, DT9, DT13, DT14 from ESD8011MUT5G(SC40000AR00) to PESD5V0H1BSF(SC40000AT00).

USB3_A_TTX_C_DRX_P0

USB3_A_TTX_C_DRX_N0

USB3_A_TRX_DTX_P0

USB3_A_TRX_DTX_N0

USB3_A_TTX_C_DRX_P1

USB3_A_TTX_C_DRX_N1

USB3_A_TRX_DTX_P1

USB3_A_TRX_DTX_N1

TBTA_SBU1

TBTA_SBU2

TBT_A_USB20_PT TBT_A_USB20_L_PT

TBT_A_USB20_NT

TBT_A_USB20_NB

TBT_A_USB20_PB

TBT_A_USB20_L_PT

TBT_A_USB20_L_NT

TBT_A_USB20_L_NB

TBT_A_USB20_L_PB

5

GND9

2

GND6

1

GND5

A12

GND2

A11

SSRXP2

A10

TOP

SSRXN2

A9

VBUS2

A8

SBU1

A7

DN1

A6

DP1

A5

CC1

A4

VBUS1

A3

SSTXN1

A2

SSTXP1

A1

GND1

1

1 2

DT2

SC40000AT00

1 2

DT3

SC40000AT00

1 2

DT4

SC40000AT00

1 2

DT5

SC40000AT00

1 2

DT6

SC40000AT00

1 2

DT7

SC40000AT00

1 2

DT8

SC40000AT00

1 2

DT9

SC40000AT00

1 2

DT13

SC40000AT00

1 2

DT14

SC40000AT00

LT2

TBT@EMI@

1 2

MCM1012B900F06BP_4P

SM070003Z00

LT3

TBT@EMI@

1 2

MCM1012B900F06BP_4P

SM070003Z00

DT10

1

2

4

5

3

TVWDF1004AD0_DFN9

TBT@ESD@

TBTA_CC2

TBTA_CC1

3

TVNST52302AB0_SOT523-3

CT96 0.01U_0402_50V7KTBT@

TBTA_SBU2

TBT_A_USB20_L_NB TBT_A_USB20_L_PBTBT_A_USB20_L_NT

TBTA_CC2

CT97 0.01U_0402_50V7KTBT@

Title

Size Document Number Rev

Date: Sheet of

Date: Sheet

TBT@ESD@

ESD8011MUT5G_X3DFN2-2

PESD5V0H1BSF_SOD962-2-2

TBT@ESD@

ESD8011MUT5G_X3DFN2-2

PESD5V0H1BSF_SOD962-2-2

TBT@ESD@

ESD8011MUT5G_X3DFN2-2

PESD5V0H1BSF_SOD962-2-2

TBT@ESD@

ESD8011MUT5G_X3DFN2-2

PESD5V0H1BSF_SOD962-2-2

TBT@ESD@

ESD8011MUT5G_X3DFN2-2

PESD5V0H1BSF_SOD962-2-2

TBT@ESD@

ESD8011MUT5G_X3DFN2-2

PESD5V0H1BSF_SOD962-2-2

TBT@ESD@

ESD8011MUT5G_X3DFN2-2

PESD5V0H1BSF_SOD962-2-2

TBT@ESD@

ESD8011MUT5G_X3DFN2-2

PESD5V0H1BSF_SOD962-2-2

TBT@ESD@

ESD8011MUT5G_X3DFN2-2

PESD5V0H1BSF_SOD962-2-2

TBT@ESD@

ESD8011MUT5G_X3DFN2-2

PESD5V0H1BSF_SOD962-2-2

34

TBT_A_USB20_L_NT

TBT_A_USB20_L_NB

34

TBT_A_USB20_L_PB

TBT_A_USB20_L_PT

9

TBT_A_USB20_L_NT

8

TBT_A_USB20_L_NB

7

TBT_A_USB20_L_PB

6

2

DT11

TBT@ESD@

1

USB3_A_TRX_DTX_P0 <39> USB3_A_TRX_DTX_N0 <39>

1 2

USB3_A_TTX_C_DRX_N1 <39> USB3_A_TTX_C_DRX_P1 <39>

Compal Electronics, Inc.

PD+USB3.1 type C

LA-E992P

1

1.0(A00)

of

41 77Tuesday, July 25, 2017

A

B

C

D

E

+5VALW to +5VS

+3VALW to +3VS

1 1

UZ1

+5VALW

SIO_SLP_S3#<18,38,39,43,44,62>

SIO_SLP_S3#

+3VALW

1

VIN1

2

VIN1

3

ON1

4

VBIAS

5

ON2

6

VIN2

7

VIN2

EM5209VF_DFN14_3X2

VOUT1 VOUT1

CT1

GND

CT2

VOUT2 VOUT2

GPAD

14 13

12

11

10

9 8

15

Close UZ1

+3VALW+5VALW

2 2

1

CZ11

@

1U_0603_10V6K

2

1

CZ12

@

1U_0603_10V6K

2

+5VS_OUT

1 2

CZ4 470P_0402_5 0V7K

1 2

CZ6 0.01U_0402_1 6V7K

JPZ1

1 2

PAD-OPEN1x3m

1 2

CZ8 10U_0603_6.3 V6M

DVT1.0 Change CZ4 to 470pF

+3VS_OUT

1 2

CZ9 10U_0603_6.3 V6M

JPZ2

1 2

PAD-OPEN1x3m

+5VS

@

+3VS

+VCCST Load Switch

1 2

SIO_SLP_S4#<18,43,63>

SIO_SLP_S3#

DVT1.0 Add RZ111 connect to SIO_SLP_S4# Add RZ112(@) connect to SIO_SLP_S3# Add net VCCST_EN

RZ111 0_0402_ 5%

1 2

RZ112 0_0402_ 5%@

1

2

+5VALW

CZ96

1U_0402_6.3V6K

VCCST_EN

+1VALW

12

Pilot Change RZ66 to 0603 0ohm

UZ15

1

VIN1

2

VIN2

7

VIN thermal

3

VBIAS

4

CZ97@

0.1U_0402_25V6

ON

TPS22961DNYR_WSON8

SA00007XR00

4.4mohm/6A TR=12.5us@Vin=1.05V

VOUT

GND

6

5

short-pad footprint.

+VCCST_OUT

RZ66 0_0603_5%

1 2

1

CZ28

0.1U_0402_10V6K

2

+VCCST

@

eDP Load Switch

B+

3 3

+3VALW

5

12

RZ40 100K_0402_5%

IN

4

EN

SY6288C20AAC_SOT23-5

DV3

LCD_VCC_TEST_EN<36>

ENVDD_PCH<1 6>

4 4

A

2

1

ENVDD

3

BAT54CW_SOT323-3~D

BAT54CW-7-F_SOT323-3

SCS00003800

DVT1.0 Change DV3 to SCS00003800.

UZ8

OUT

GND

OC

+EDPVDD_OUT

1

2

3

B

Pilot Change RZ35 to 0603 0ohm short-pad footprint.

RZ35 0_0603_5%

1 2

+EDPVDD

@

1

CZ41

0.1U_0402_10V6K

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B+ Discharge

R3 1M_0402_5%

VCC_CHG<60>

Compal Secret Data

2011/08/25 2012/07/25

C

Compal Secret Data

1 2

Deciphered Date

1M_0402_5%

12

R4

B+

12

R1

1M_0402_5%

34

QZ13B

5

DMN65D8LDW-7_SOT363-6

D

1 2

1M_0402_5%

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

SYS DC/DC Interface

R2

4.7K_0805_5%

1 2

61

QZ13A

2

DMN65D8LDW-7_SOT363-6

DVT1.0 Change QZ13 to SB00000ZU00

R5

LA-E992P

E

1.0(A00)

of

42 77Tuesday, July 25, 2017

5

4

3

2

1

D D

C C

+VCCSTG Load Switch

+1VALW

UZ9

1

VIN1

2

+5VALW

0.1U_0402_10V7K

@

1U_0402_6.3V6K

1

12

CZ86

CZ88

2

VIN2

7

VIN thermal

3

VBIAS

4

ON

TPS22961DNYR_WSON8

4.4mohm/6A TR=12.5us@Vin=1.05V

SIO_SLP_S3# <18,38,39,42,43,44,62>

VOUT

GND

Pilot Change RZ48 to 0603 0ohm short-pad footprint.

+VCCSTG_OUT

6

5

RZ48 0_0603_5%

@

12

+VCCSTG

1

CZ47

0.1U_0402_10V6K

2

+1.2V_DDR Enable

Pilot Change DZ1 footprint to AZ5125-01HPR7G_SOD523-2

SIO_SLP_S4#<18,42,63> 1.2V_VDDQ_EN <62>

DZ1

1 2

RB751S40T1G_SOD523-2

AZ5125-01HPR7G_SOD523-2

1 2

RZ102 100K_040 2_5%

1

CZ102

0.1U_0402_10V6K

2

DVT1.0 Change CZ102 to 0.1uF

+VCCPLL_OC Load Switch

+VCCIO Enable

B B

+1.2V_DDR

UZ16

1

VIN

2

SIO_SLP_S3#

+5VALW

A A

5

VIN

3

EN

4

VBIAS

AOZ1336DI_DFN8_2X2

SA00006U600

APE8937GN2_DFN8_2X2

Pilot Change UZ16 form APE8937GN2(SA000070L00) to AOZ1336DI(SA00006U600), keep using APE8937GN2_DFN8_2X2 footprint.

+1.2V_VCCPLL_OC_OUT

8

VOUT

7

VOUT

6

CZ57

5 9

GND GND

CT

Pilot Change RZ67 to 0603 0ohm short-pad footprint.

RZ67 0_0603_5%

1 2

@

1 2

@

2200P_0402_25V7K

4

+1.2V_VCCPLL_OC

1

CZ49

0.1U_0402_10V6K

2

SIO_SLP_S3#<18,38,39,42,43,44,62> VCCIO_EN <74 >

Security Classification

2011/08/25 2012/07/25

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/08/25 2012/07/25

3

Compal Secret Data

Deciphered Date

Pilot Change DZ2 footprint to AZ5125-01HPR7G_SOD523-2

DZ2

1 2

RB751S40T1G_SOD523-2

AZ5125-01HPR7G_SOD523-2

1 2

RZ108 150K_040 2_5%

1

CZ108

0.22U_0402_10V4Z

2

DVT1.0 Change CZ108 to 0.22uF

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet

Compal Electronics, Inc.

DC/DC/S0iX/CS

LA-E992P

1

1.0(A00)

of

43 77Tuesday, July 25, 2017

5

4

3

2

1

1 24

23 22

20 19

17 16

14 13

33 34 8 7

40 21

32 9 12

29 28

49

+1.2V_RTM

CP28

22U_0603_6.3V6M

@PS8409@

1

2

+3V_RTM

IFPC_I2C_8409_DAT IFPC_I2C_8409_CLK

1 2

RP11 0_0402_5%

RTM_CSCL RTM_CSDA

1

2

RP45 1K_0402_5%PS8409@

DVT 2.0 Add CP28/CP29 for +1.2V_RTM

CP29

stable

@PS8409@

22U_0603_6.3V6M

TMDS_T_TX2P <45> TMDS_T_TX2N <45>

TMDS_T_TX1P <45> TMDS_T_TX1N <45>

TMDS_T_TX0P <45> TMDS_T_TX0N <45>

TMDS_T_TXCP <45> TMDS_T_TXCN <45>

IFPC_I2C_8409_DAT <47> IFPC_I2C_8409_CLK <47> DDC_SDA_HDMI <45,47> DDC_SCL_HDMI <45,47>

1 2

HDMI_HPD <45>

@PS8409@

HDMI_CEC <45>

GPU_HPD_RT <46>

11/14 Add

HDMI_HPD_PCH<20>

Pilot Change RP28 to 0603 0ohm short-pad footprint.

1 2

RP28

@

0_0603_5%

TMDS_T_TXCP

TMDS_T_TXCN

1

@PS8409@

CP23

0.1U_0402_10V6K

2

+3VS+3V_RTM

IFPC_I2C_8409_DATRTM_HDMI_ID IFPC_I2C_8409_CLK

12/12 Add

RTM_CSCL RTM_CSDA

+3VS

QP1 S TR METR3904W-G NPN SOT323-3

1

C

2

1 2

B

E

RP46

3

150K_0402_5%

0.1U_0402_10V6K

RP24

1 2 1 2

RP25

RP48

1 2 1 2

RP49

HDMI_HPD

1

CP47

0.1U_0402_16V7K

2

CP24

PS8409@

Close Pin 24

47K_0402_5%@PS8409@ 47K_0402_5%@PS8409@

10K_0402_5%@PS8409@ 10K_0402_5%@PS8409@

+3V_RTM

1

2

+3V_RTM

1

PS8409@

CP26

2

1

CP25

0.01U_0402_16V7K

2

PS8409@

0.1U_0402_10V6K

Close Pin 1

+3V_RTM

DVT1.0 Add QZ2

2

1 3

D

QZ2

@

1 2

SIO_SLP_S3#

G

S

1 2

CP17 0.1U_0402_10V6KPS8409@

1 2

CP18 0.1U_0402_10V6KPS8409@

1 2

CP19 0.1U_0402_10V6KPS8409@

1 2

CP20 0.1U_0402_10V6KPS8409@

1 2

CP22 0.1U_0402_10V6KPS8409@

1 2

CP21 0.1U_0402_10V6KPS8409@

1 2

CP16 0.1U_0402_10V6KPS8409@

1 2

CP15 0.1U_0402_10V6KPS8409@

4.99K_0402_1%

PS8409@

SIO_SLP_S3# <18,38,39,42,43,62>

12

RP32

1

2

1U_0402_6.3V6K

CP27

PS8409@

+1.2V_RTM

IFPC_TX2_CP IFPC_TX2_CN

IFPC_TX1_CP IFPC_TX1_CN

IFPC_TX0_CP IFPC_TX0_CN

IFPC_CLK_CP IFPC_CLK_CN

RTM_DCIN_ENB RTM_EQ RTM_I2C_ADDR

RTM_PDB RTM_RST# RTM_PRE

DVT 2.0 Del UP1/RP29/RP30/CP1/CP2

UP2

30

VDD12

6

VDD12

11

VDDA12

43

VDDRX12

46

VDDRX12

15

VDDTX12

18

VDDTX12

37

POWERSWITCH

38

IN_D2p

39

IN_D2n

41

IN_D1p

42

IN_D1n

44

IN_D0p

45

IN_D0n

47

IN_CKp

48

IN_CKn

3

DCIN_EN

5

EQ

31

I2C_ADDR

10

RSV1

25

NC

26

RSV2

36

REXT

4

PDB

35

RESETB

27

PRE

2

TESTMODEB

PS8409AQFN48GTR2-A0 QFN48P

PS8409@

VDD33 VDD33

OUT_D2p OUT_D2n

OUT_D1p OUT_D1n

OUT_D0p OUT_D0n

OUT_CKp OUT_CKn

SDA_SRC/AUXN

SCL_SRC/AUXP

SDA_SNK

SCL_SNK

HPD_SRC HPD_SNK

HDMI_ID

HDMI_CEC

CEC_EN

CSCL CSDA

EPAD

+1.2V_RTM

DVT2.0 Del LP1

D D

0.01U_0402_16V7K

PS8409@

Close Pin 30

1

2

CP4

0.1U_0402_10V6K

2

PS8409@

+1.2V_VCCPLL_OC +1.2V_RTM

LN2306LT1G_SOT23-3

RP31 0_0603_5%

PS8409@

CP3

+1.2V_RTM

DVT2.0 Del LP2

0.1U_0402_10V6K

PS8409@

Close Pin 6,11

C C

DVT2.0 Del LP3

CP8

4.7U_0603_6.3V6K

PS8409@

1

CP5

2

+1.2V_RTM

1

2

+1.2V_RTM

1

2

0.1U_0402_10V6K

1

2

PS8409@

CP9

CP6

PS8409@

0.1U_0402_10V6K

CP11

PS8409@

1

2

1

2

CP7

0.01U_0402_16V7K

PS8409@

1

CP10

0.01U_0402_16V7K

2

PS8409@

0.1U_0402_10V6K

IFPC_TX2_P<47> IFPC_TX2_N<47>

IFPC_TX1_P<47> IFPC_TX1_N<47>

IFPC_TX0_P<47> IFPC_TX0_N<47>

IFPC_CLK_P<47> IFPC_CLK_N<47>

Close Pin 43,46

+1.2V_RTM

DVT2.0 Del LP4

0.1U_0402_10V6K

B B

+3V_RTM

1

CP13

PS8409@

2

Close Pin 15,18

RP33 10K_0402_5%@PS8409@ RP34 10K_0402_5%@PS8409@ RP38 10K_0402_5%@PS8409@ RP37 10K_0402_5%@PS8409@ RP36 10K_0402_5%@PS8409@

RP35 10K_0402_5%PS8409@

1

PS8409@

2

CP12

1 2 1 2 1 2 1 2 1 2

1 2

1

2

0.1U_0402_10V6K

CP14

0.01U_0402_16V7K

PS8409@

RTM_DCIN_ENB RTM_EQ RTM_I2C_ADDR RTM_PRE RTM_HDMI_ID

RTM_RST#

1 2

RP39 10K_0402_5%PS8409@

1 2

RP40 10K_0402_5%@PS8409@

1 2

A A

RP41 10K_0402_5%@PS8409@

1 2

RP42 10K_0402_5%@PS8409@

1 2

RP43 10K_0402_5%@PS8409@

1 2

RP44 10K_0402_5%@PS8409@

5

RTM_DCIN_ENB RTM_EQ RTM_I2C_ADDR RTM_PRE RTM_HDMI_ID RTM_PDB

Title

Size Document Number Rev

C

Date: Sheet

4

3

2

Date: Sheet

HDMI Retimer-PS8409

LA-E992P

1

44 77Tuesday, July 25, 2017

1.0(A00)

of

5

4

3

2

1

Place close to JHDMI1

D D

C C

B B

TMDS_T_TXCP<44>

TMDS_T_TXCN<44>

TMDS_T_TX0P<44>

TMDS_T_TX0N<44>

TMDS_T_TX1P<44>

TMDS_T_TX1N<44>

TMDS_T_TX2P<44>

TMDS_T_TX2N<44>

TMDS_T_TXCP

TMDS_T_TXCN

TMDS_T_TX0P

TMDS_T_TX0N

TMDS_T_TX1P

TMDS_T_TX1N

TMDS_T_TX2P

TMDS_T_TX2N

+5VS

RV554

@EMI@

300_0402_5%

RV557

@EMI@

300_0402_5%

RV562

@EMI@

300_0402_5%

RV565

@EMI@

300_0402_5%

UV17

1

IN

AP2330W-7_SC59-3

SA00004ZA00

12

OUT

GND

3

2

1 2

RV609 2.2_0402_1%EMI@

1 2

RV610 2.2_0402_1%EMI@

1 2

RV611 2.2_0402_1%EMI@

1 2

RV612 2.2_0402_1%EMI@

1 2

RV613 2.2_0402_1%EMI@

1 2

RV614 2.2_0402_1%EMI@

1 2

RV615 2.2_0402_1%EMI@

1 2

RV616 2.2_0402_1%EMI@

W=40mils

+VDISPLAY_VCC

CV598

0.1U_0402_10V6K

1

2

+VDISPLAY_VCC

1 2

RM3 2.2K_0402_5%

1 2

For EMI Reserve

1 2

A A

CV599 0.1U_0402_25V6@

1 2

CV600 0.1U_0402_25V6@

1 2

CV601 0.1U_0402_25V6@

Close to JHDMI

5

HDMI_HPD

HDMI_Reserved

HDMI_CEC

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

RM4 2.2K_0402_5%

3

TMDS_T_TXCP_R

TMDS_T_TXCN_R

TMDS_T_TX0P_R

TMDS_T_TX0N_R

TMDS_T_TX1P_R

TMDS_T_TX1N_R

TMDS_T_TX2P_R

TMDS_T_TX2N_R

CV597

10U_0603_6.3V6M

1

2

2011/08/25 2012/07/25

HDMI_HPD<44>

DDC_SDA_HDMI<44 ,47>

DDC_SCL_HDMI<44,47>

HDMI_CEC<44>

DDC_SCL_HDMI

DDC_SDA_HDMI

Compal Secret Data

Deciphered Date

HDMI_HPD

DDC_SDA_HDMI DDC_SCL_HDMI HDMI_Reserved HDMI_CEC TMDS_T_TXCN_R

TMDS_T_TXCP_R TMDS_T_TX0N_R

TMDS_T_TX0P_R TMDS_T_TX1N_R

TMDS_T_TX1P_R TMDS_T_TX2N_R

TMDS_T_TX2P_R

2

HDMI conn

JHDMI1

19

HP_DET

18

+5V

17

DDC/CEC_GND

16

SDA

15

SCL

14

Reserved

13

CEC

12

CK-

11

CK_shield

10

CK+

9

D0-

8

D0_shield

7

D0+

6

D1-

5

D1_shield

4

D1+

3

D2-

2

D2_shield

1

D2+

CONCR_099A3AC19JBLCNF

CONN@

DC232003400

Title

Size Document Number Rev

Date: Sheet of

Date: Sheet

20

GND1

21

GND2

22

GND3

23

GND4

Compal Electronics, Inc.

HDMI

LA-E992P

1

of

45 77Tuesday, July 25, 2017

1.0(A00)

5

+1V8_AON

1

CG483

0.1U_0201_6.3V6K

N17E@

5

2

+1V8_AON

5

VCC

IN B

OUT Y

IN A

GND

UG10

3

NL17SZ08DFT2G_SC70-5

N17E@

SA00003R000

P.P

N17E-G1_BGA2152~D

1

CG526

0.1U_0201_6.3V6K

N17E@

2

4

I2CS_SCL I2CS_SDA

I2CC_SCL

I2CC_SDA

I2CB_SCL I2CB_SDA

GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8

GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21 GPIO22 GPIO23 GPIO24 GPIO25 GPIO26 GPIO27 GPIO28 GPIO29 GPIO30 GPIO31 GPIO32

1

VCC

IN B

4

OUT Y

2

IN A

GND

UG29 NL17SZ08DFT2G_SC70-5

3

N17E@

SA00003R000

P.P

VGA_CLK_REQ#<17>

VGA_SMB_CK2

BJ8

VGA_SMB_DA2

BH8

I2CC_SCL_R

BG9

I2CC_SDA_R

BH9

1 2

BG8

RG19 1.8K_0402_5%N17E@

1 2

BF8

RG20 1.8K_0402_5%N17E@

BD6

GPU_GC6_FB_EN

BB5

GC6_EVENT#_D

BD1

MAX-Q_DET

BE4 BE1

FRAME_LOCK#

BG2 BD2 BD7

MEM_VDD_CTL

BH4 BJ3

ALERT# MEM_VREF

BD3 BH3

EC_AC_BAT#

BE6 BB1 BG4 BG1

SYS_PEX_RST_MON#

BE2 BH1 BE3 BD4 BE5 BA5 BB6

GPU_PEX_RST_HOLD#

BG3 BD5 BB2 BE7

HPD_IFPC

BA4

GPIO3_OC_WARN#

BB4 BA3 BB3 BA2 BA1

RG157 0_0201_5%

N17E@

1 2

G

Vgs(th):0.5V~1.5V

123

D

S

N17E@

QG510 MESS138W-G_SOT323-3

SB00000S700

RG537 0_0201_5%

1 2

@N17E@

1 2

RG160 0_0201_5%

N17E@

+1V8_AON

NVVDD_VID <67>

1V8_MAIN_EN <55>

1 2

RG566 0_0201_5%

N17E@

MEM_VDD_CTL <69>

MEM_VREF <52,53,54>

EC_AC_BAT# <59>

GPIO3_OC_WARN# <49>

DGPU_PWROK<18,55,69>

12

RG26 10K_0201_5%

N17E@

RG165 10K_0201_5%

OVERT#

NVVDD1_PGOOD<55,67>

1 2

DGPU_HOLD_RST#

PCH_PLTRST#_EC

UG9W

BG5

OVERT

BF12

TS_VREF

BJ1

THERMDN

BJ2

THERMDP

BK24

JTAG_TCK

BL23

JTAG_TMS

BM23

JTAG_TDI

BM24

JTAG_TDO

BL24

JTAG_TRST*

BK23

NVJTAG_SEL

@

5

N17E@

13/23 MISC 1

1

2

D D

C C

B B

A A

T10 PAD~D@ T11 PAD~D@ T12 PAD~D@ T13 PAD~D@

10K_0201_5%

DGPU_HOLD_RST#<20>

PCH_PLTRST#_EC<17,27,28,29,33,36,39>

OVERT#<55>

GPU_JTAG_TCK GPU_JTAG_TMS GPU_JTAG_TDI GPU_JTAG_TDO GPU_JTAG_TRST#

12

RG518

N17E@

4

+1V8_AON

RG163

N17E@

10K_0201_5%

1 2

PEX_CLKREQ#

+1V8_AON

GPU_PEX_RST_HOLD#

SYS_PEX_RST_MON#

@N17E@

3

1

2

DG9 BAT54A-7-F_SOT23-3

DGPU_PEX_RST#

VGA_SMB_CK2

VGA_SMB_DA2

+1V8_AON

RG159

N17E@

1.8K_0402_1%

I2CC_SCL_R

I2CC_SDA_R

Pilot Change DG2 footprint to AZ5125-01HPR7G_SOD523-2

DVT1.0 Change DG2 to SC100000S00

AZ5125-01HPR7G_SOD523-2

N17E@

12

DG2 RB751S40T1G_SOD523-2

BSS138W 1N SOT-323-3

4

2

Vgs(th):0.8V~1.5V

61

N17E@

QG6A DMN53D0LDW-7 2N SOT363-6

SB000018X00

12

RG167

N17E@

1.8K_0402_1%

N17E@

QG7A DMN53D0LDW-7 2N SOT363-6

SB000018X00

GPU_EVENT# <20>

NVVDD_PSI <67>

HPD_IFPC

13

D

QG9

N17E@

S

354

2

G

PEG_HTX_C_GRX_P[0..15]<7>

PEG_HTX_C_GRX_N[0..15]<7>

PEG_GTX_C_HRX_P[0..15]<7>

PEG_GTX_C_HRX_N[0..15]<7>

12

@N17E@

RG161 10K_0201_5%

DGPU_PEX_RST#

SB000018X00

QG6B DMN53D0LDW-7 2N SOT363-6

N17E@

DGPU_PEX_RST#

SB000018X00

N17E@

QG7B DMN53D0LDW-7 2N SOT363-6

354

Vgs(th):0.8V~1.5V

61

EC_AC_BAT#

Pilot Change DG8 footprint to AZ5125-01HPR7G_SOD523-2

@N17E@

1 2

RG575 0_0402_5%

4

12

RG573 100K_0402_5%

N17E@

DGPU_PEX_RST# <55>

GPU_THM_SMBCLK <18,27,36>

GPU_THM_SMBDAT <18,27,36>

MAX-Q_DET GC6_EVENT#_D OVERT# GPU_PEX_RST_HOLD# EC_AC_BAT# VGA_SMB_CK2 VGA_SMB_DA2 SYS_PEX_RST_MON# ALERT# GPIO3_OC_WARN# FRAME_LOCK# NVVDD_PSI HPD_IFPC

DG8

RB751S40T1G_SOD523-2

AZ5125-01HPR7G_SOD523-2

GPU_PWR_LEVEL(GPIO12)

Low High

GPU_GC6_FB_EN MEM_VREF DGPU_PEX_RST#

+1V8_AON

5

1

P

B

O

2

A

G

3

UG30 TC7SZ08FU_SSOP5

N17E@

P.P

PEG_HTX_C_GRX_P[0..15]

PEG_HTX_C_GRX_N[0..15]

PEG_GTX_C_HRX_P[0..15]

PEG_GTX_C_HRX_N[0..15]

I2CC_SCL <49>

I2CC_SDA <49>

RG579 10K_0201_5%N17E@ RG164 10K_0201_5%N17E@ RG168 10K_0201_5%N17E@ RG166 10K_0201_5%N17E@ RG16 100K_0201_5%N17E@ RG17 1.8K_0402_5%N17E@ RG18 1.8K_0402_5%N17E@ RG21 10K_0201_5%N17E@ RG504 10K_0201_5%N17E@ RG522 10K_0201_5%N17E@ RG502 10K_0201_5%N17E@ RG162 10K_0201_5%N17E@ RG572 10K_0201_5%N17E@

12

N17E@

Low Performace High Performace

RG22 10K_0201_5%N17E@ RG24 100K_0201_5%N17E@ RG562 100K_0402_5%N17E@

GPU_HPD_RT <44>

DGPU_PEX_RST#

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

1 2 1 2 1 2

+1V8_AON

GPU_PWR_LEVEL <36>

3

CLK_PEG_GPU<17>

CG519 0.22U_0201_6.3VN17E@ CG516 0.22U_0201_6.3VN17E@

CG506 0.22U_0201_6.3VN17E@ CG513 0.22U_0201_6.3VN17E@

CG518 0.22U_0201_6.3VN17E@ CG25 0.22U_0201_6.3VN17E@

CG26 0.22U_0201_6.3VN17E@ CG27 0.22U_0201_6.3VN17E@

CG28 0.22U_0201_6.3VN17E@ CG29 0.22U_0201_6.3VN17E@

CG30 0.22U_0201_6.3VN17E@ CG31 0.22U_0201_6.3VN17E@

CG32 0.22U_0201_6.3VN17E@ CG33 0.22U_0201_6.3VN17E@

CG35 0.22U_0201_6.3VN17E@ CG36 0.22U_0201_6.3VN17E@

CG488 0.22U_0201_6.3VN17E@ CG489 0.22U_0201_6.3VN17E@

CG491 0.22U_0201_6.3VN17E@ CG490 0.22U_0201_6.3VN17E@

CG493 0.22U_0201_6.3VN17E@ CG492 0.22U_0201_6.3VN17E@

CG495 0.22U_0201_6.3VN17E@ CG494 0.22U_0201_6.3VN17E@

CG497 0.22U_0201_6.3VN17E@ CG496 0.22U_0201_6.3VN17E@

CG499 0.22U_0201_6.3VN17E@ CG498 0.22U_0201_6.3VN17E@

CG501 0.22U_0201_6.3VN17E@ CG500 0.22U_0201_6.3VN17E@

CG503 0.22U_0201_6.3VN17E@ CG502 0.22U_0201_6.3VN17E@

CLK_PEG_GPU#<17>

1 2 1 2

Vgs(th):0.5V~1.5V

GPU_GC6_FB_EN

PEG_GTX_C_HRX_P0 PEG_GTX_C_HRX_N0 PEG_GTX_HRX_N0

PEG_GTX_C_HRX_P1 PEG_GTX_C_HRX_N1

PEG_GTX_C_HRX_P2 PEG_GTX_C_HRX_N2

PEG_GTX_C_HRX_P3 PEG_GTX_C_HRX_N3

PEG_GTX_C_HRX_P4 PEG_GTX_C_HRX_N4

PEG_GTX_C_HRX_P5 PEG_GTX_C_HRX_N5

PEG_GTX_C_HRX_P6 PEG_GTX_C_HRX_N6

PEG_GTX_C_HRX_P7 PEG_GTX_C_HRX_N7

PEG_GTX_C_HRX_P8 PEG_GTX_C_HRX_N8

PEG_GTX_C_HRX_P9 PEG_GTX_C_HRX_N9

PEG_GTX_C_HRX_P10 PEG_GTX_C_HRX_N10

PEG_GTX_C_HRX_P11 PEG_GTX_C_HRX_N11

PEG_GTX_C_HRX_P12 PEG_GTX_C_HRX_N12

PEG_GTX_C_HRX_P13 PEG_GTX_C_HRX_N13

PEG_GTX_C_HRX_P14 PEG_GTX_C_HRX_N14

PEG_GTX_C_HRX_P15 PEG_GTX_C_HRX_N15

3

DGPU_PEX_RST#

PEX_CLKREQ#

PEG_GTX_HRX_P0

PEG_HTX_C_GRX_P0 PEG_HTX_C_GRX_N0

PEG_GTX_HRX_P1 PEG_GTX_HRX_N1

PEG_HTX_C_GRX_P1 PEG_HTX_C_GRX_N1

PEG_GTX_HRX_P2 PEG_GTX_HRX_N2

PEG_HTX_C_GRX_P2 PEG_HTX_C_GRX_N2

PEG_GTX_HRX_P3 PEG_GTX_HRX_N3

PEG_HTX_C_GRX_P3 PEG_HTX_C_GRX_N3

PEG_GTX_HRX_P4 PEG_GTX_HRX_N4

PEG_HTX_C_GRX_P4 PEG_HTX_C_GRX_N4

PEG_GTX_HRX_P5 PEG_GTX_HRX_N5

PEG_HTX_C_GRX_P5 PEG_HTX_C_GRX_N5

PEG_GTX_HRX_P6 PEG_GTX_HRX_N6

PEG_HTX_C_GRX_P6 PEG_HTX_C_GRX_N6

PEG_GTX_HRX_P7 PEG_GTX_HRX_N7

PEG_HTX_C_GRX_P7 PEG_HTX_C_GRX_N7

PEG_GTX_HRX_P8 PEG_GTX_HRX_N8

PEG_HTX_C_GRX_P8 PEG_HTX_C_GRX_N8

PEG_GTX_HRX_P9 PEG_GTX_HRX_N9

PEG_HTX_C_GRX_P9 PEG_HTX_C_GRX_N9

PEG_GTX_HRX_P10 PEG_GTX_HRX_N10

PEG_HTX_C_GRX_P10 PEG_HTX_C_GRX_N10

PEG_GTX_HRX_P11 PEG_GTX_HRX_N11

PEG_HTX_C_GRX_P11 PEG_HTX_C_GRX_N11

PEG_GTX_HRX_P12 PEG_GTX_HRX_N12

PEG_HTX_C_GRX_P12 PEG_HTX_C_GRX_N12

PEG_GTX_HRX_P13 PEG_GTX_HRX_N13

PEG_HTX_C_GRX_P13 PEG_HTX_C_GRX_N13

PEG_GTX_HRX_P14 PEG_GTX_HRX_N14

PEG_HTX_C_GRX_P14 PEG_HTX_C_GRX_N14

PEG_GTX_HRX_P15 PEG_GTX_HRX_N15

PEG_HTX_C_GRX_P15 PEG_HTX_C_GRX_N15

+1V8_AON

G

123

D

S

QG511 MESS138W-G_SOT323-3

N17E@

SB00000S700

2

UG9A

1/23 PCI_EXPRESS

BK26

PEX_RST*

BL26

PEX_CLKREQ*

BM26

PEX_REFCLK

BM27

PEX_REFCLK*

BG26

PEX_TX0

BH26

PEX_TX0*

BL27

PEX_RX0

BK27

PEX_RX0*

BF26

PEX_TX1

BE26

PEX_TX1*

BK29

PEX_RX1

BL29

PEX_RX1*

BF27

PEX_TX2

BG27

PEX_TX2*

BM29

PEX_RX2

BM30

PEX_RX2*

BG29

PEX_TX3

BH29

PEX_TX3*

BL30

PEX_RX3

BK30

PEX_RX3*

BF29

PEX_TX4

BE29

PEX_TX4*

BK32

PEX_RX4

BL32

PEX_RX4*

BF30

PEX_TX5

BG30

PEX_TX5*

BM32

PEX_RX5

BM33

PEX_RX5*

BG32

PEX_TX6

BH32

PEX_TX6*

BL33

PEX_RX6

BK33

PEX_RX6*

BF32

PEX_TX7

BE32

PEX_TX7*

BK35

PEX_RX7

BL35

PEX_RX7*

BF33

PEX_TX8

BG33

PEX_TX8*

BM35

PEX_RX8

BM36

PEX_RX8*

BG35

PEX_TX9

BH35

PEX_TX9*

BL36

PEX_RX9

BK36

PEX_RX9*

BF35

PEX_TX10

BE35

PEX_TX10*

BK38

PEX_RX10

BL38

PEX_RX10*

BF36

PEX_TX11

BG36

PEX_TX11*

BM38

PEX_RX11

BM39

PEX_RX11*

BG38

PEX_TX12

BH38

PEX_TX12*

BL39

PEX_RX12

BK39

PEX_RX12*

BF38

PEX_TX13

BE38

PEX_TX13*

BK41

PEX_RX13

BL41

PEX_RX13*

BF39

PEX_TX14

BG39

PEX_TX14*

BM41

PEX_RX14

BM42

PEX_RX14*

BH41

PEX_TX15

BG41

PEX_TX15*

BL42

PEX_RX15

BK42

PEX_RX15*

GPU_GC6_FB_EN_H <20>GPU_GC6_FB_EN<55>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETA RY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTA INS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETA RY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTA INS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS , INC. NEITHER THIS SHEET NOR THE INFO RMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS , INC. NEITHER THIS SHEET NOR THE INFO RMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS , INC. NEITHER THIS SHEET NOR THE INFO RMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC .

2

BB33

PEX_DVDD_1

BB35

PEX_DVDD_2

BB36

PEX_DVDD_3

BC33

PEX_DVDD_4

BC35

PEX_DVDD_5

BC36

PEX_DVDD_6

BD33

PEX_DVDD_7

BD36

PEX_DVDD_8

Under GPU

BB26

PEX_HVDD_1

BB27

PEX_HVDD_2

BB29

PEX_HVDD_3

BB32

PEX_HVDD_4

BC26

PEX_HVDD_5

BC27

PEX_HVDD_6

BC29

PEX_HVDD_7

BC30

PEX_HVDD_8

BC32

PEX_HVDD_9

BD27

PEX_HVDD_10

BD30

N17E-G1_BGA2152~D@

PEX_HVDD_11

PEX_PLL_HVDD

PEX_TERMP

GPIO Number

GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21 GPIO22 GPIO23 GPIO24 GPIO25 GPIO26 GPIO27 GPIO28 GPIO29 GPIO30

Under GPU

+PEX_PLL_HVDD

BB30

1

2

PEX_TERMP

BL44

Close to UG9

I/O

GPIO Name

O

NVVDD_PWM

O

GC6M:GC6_FB_EN

I

GC6M:GPU_EVENT*/WAKE*

O

NVVDDS_PWM

O

GC6M:1V8_MAIN_EN

I

FRM_CLK* NVVDD_PSI*/NVVDDS_PSI*

O

LCD_BL_PWM

O

MEM_VDD_CTL

I/O

THERM_ALERT*

O

MEM_VREF_CTL

O

LCD_VDD

I

PWM_LEVEL

O

LCD_BLEN

I

HPD_IFPA*

I

HPD_IFPB*

O

GC6M:SYS_PEX_RST_MON*

I

HPD_IFPD*

I

HPD_IFPE*

O

3D Vision/STEREO

I/O

GC5_MODE

I/O

RASTER_SYNC0

I/O

SWAP_RDY0 or SWAPRDY_IN

I/O

GC6M:GPU_PEX_RST_HOLD*

I

HPD_IFPF*

I/O

UNUSED

I/O

UNUSED

I

HPD_IFPC*

I

OC_WARN*/HT

I

EDPc_OUTPUT_CAP

I/O

UNUSED

Compal Secret Data

2016/01/06 2016/09/18

1

CG504

2

1U_0402_6.3V6K

N17E@

1

CG512

2

1U_0402_6.3V6K

N17E@

CG34

0.1U_0201_6.3V6K

N17E@

RG23

2.49K_0402_1%

Deciphered Date

1

2

1

2

CG523

1U_0402_6.3V6K

N17E@

CG517

1U_0402_6.3V6K

N17E@

12

1 2

1

CG509

CG525

2

CG510

2

1U_0402_6.3V6K

N17E@

4.7U_0603_6.3V6M

N17E@

Near GPU

1

CG522

CG505

CG520

2

1U_0402_6.3V6K

4.7U_0603_6.3V6M

N17E@

Near GPU

+1V8_MAIN

N17E@

LG9 PBY160808T-301Y-N

Function Description

PWM Output to control NVVDD(0 to1V8 PWM output) FB Enable for GC6 2.1 GPU wake signal for GC6 2.1

For MAX-Q detection.

GPU power sequencing for GC6 2.1

Active low Frame Lock

Phase Shedding(Optional, check with VR Spec)

Panel Backlight enable Control signal to turn on a logo LED Memory voltage control

Active Low Thermal Alert

Memory VREF Control

Panel Power enable(100 kΩ PD)

AC power detect for PWR supply overdraw input LCD Panel Backlight Hot Plug Detect for IFPA(Inverted input) Hot Plug Detect for IFPB(Inverted input) System side PCIe reset monitor Hot Plug Detect for IFPD(Inverted input) Hot Plug Detect for IFPE(Inverted input) 3D Vision L/R Signal

Phase Shedding,Optional, check with VR Spec.

Input when master GPU or Output when Slave GPU(100K PD) SLI SWAP READY OUT GPU PCIe self-reset control Hot Plug Detect for IFPF(Inverted input)

Hot Plug Detect for IFPC(Inverted input) Over current throttling trigger Input from power supply(0 to 1V8)

1

+PEX_VDD

2

1

CG511

CG524

CG521

1

2

N17E@

10U_0603_6.3V6M

22U_0805_6.3V6M

4.7U_0603_6.3V6M

N17E@

+1V8_MAIN

1

2

CG507

2

4.7U_0603_6.3V6M

N17E@

1

CG514

CG515

CG508

1

2

10U_0603_6.3V6M

22U_0805_6.3V6M

N17E@

22uF 10uF 4.7uF 1uF 0.1uF

PEX_DVDD

PEX_HVDD

1 1 2

1 2

Compal Electronics, Inc.

Title

N17E-G1(1/6) PCIE,GPIO

Size Document Number Rev

Date: Sheet of

LA-E992P

1

4

42

1.0(A00)

46 77Tuesday, July 25, 2017

5

4

3

2

1

0.1U_0402_10V7K

UG9U

AV7

AV8

AW9

UG9O

6/23 IFPF

BC21

IFP_IOVDD_11

BC23

IFP_IOVDD_12

IFPF

N17E-G1_BGA2152~D

@

UG9P

10/23 IFPE

BD17

IFPEF_RSET

BD15

IFPEF_PLLVDD

IFPE

BC18

IFP_IOVDD_9

BC20

IFP_IOVDD_10

N17E-G1_BGA2152~D

@

12/23 MIOB

MIOB_CAL_PD_VDDQ

MIOB_CAL_PU_GND

MIOB_VREF

IFPx_IOVDD

IFPx_PLLVDD

AT3

MIOB_D0

AV6

MIOB_D1

AT2

MIOB_D2

AT1

MIOB_D3

AW6

MIOB_D4

AV2

MIOB_D5

AV1

MIOB_D6

AV3

MIOB_D7

AW3

MIOB_D8

BA8

MIOB_D9

AW7

MIOB_D10

BB8

MIOB_D11

BB7

MIOB_CTL3

AV5

MIOB_HSYNC

BA7

MIOB_VSYNC

AW2

N17E-G1_BGA2152~D@

SDA SCL

TXC TXC

TXD0 TXD0

TXD1 TXD1

TXD2 TXD2

MIOB_DE

MIOB_CLKOUT

MIOB_CLKIN

IFPF_AUX_SDA*

IFPF_AUX_SCL

DP

AW1

AT6

IFPF_L3*

IFPF_L3

IFPF_L2*

IFPF_L2

IFPF_L1*

IFPF_L1

IFPF_L0*

IFPF_L0

BM9 BM8

BK11 BL11

BM11 BM12

BL12 BK12

BK14 BL14

GP106GP104

UNUSEDMIOB

DVI/HDMI

22uF 10uF 4.7uF 1uF 0.1uF

3

6

1

DVI/HDMI

SDA SCL

TXC TXC

TXD0 TXD0

TXD1 TXD1

TXD2 TXD2

DP

IFPE_AUX_SDA*

IFPE_AUX_SCL

IFPE_L3*

IFPE_L3

IFPE_L2*

IFPE_L2

IFPE_L1*

IFPE_L1

IFPE_L0*

IFPE_L0

BL8 BK8

BG14 BH14

BF14 BE14

BF15 BG15

BG17 BH17

UG9V

AM5

AM6

AM7

IFPC_I2C_DAT_R

IFPC_I2C_CLK_R

34

11/23 MIOA

MIOA_CAL_PD_VDDQ

MIOA_CAL_PU_GND

MIOA_VREF

@PS8409@

RP10 0_0402_5%

1 2

N17E@

RG577 0_0402_5%

1 2

N17E@

RG578 0_0402_5%

1 2

@PS8409@

RP9 0_0402_5%

1 2

N17E-G1_BGA2152~D@

+PEX_VDD

IFPC_I2C_8409_DAT <44>

DDC_SDA_HDMI <44,45>

DDC_SCL_HDMI <44,45>

IFPC_I2C_8409_CLK <44>

+PEX_VDD

UG9N

7/23 IFPAB

D D

+PEX_VDD

1

CG311

N17E@

2

4.7U_0603_6.3V6M

C C

Under GPU

1

CG309

2

0.1U_0402_10V7K

N17E@

Under GPU

N17E@

RG37 1K_0402_1%

+1V8_MAIN +IFPX_PLLVDD

1 2

LG8 PBY160808T-300Y-N_2P

N17E@

12

IFPCD_RSET

1

N17E@

2

UG9R

8/23 IFPC

BD20

IFPCD_RSET

BD18

IFPCD_PLLVDD

CG47

0.1U_0402_10V7K

IFPC

Under GPU

+PEX_VDD

B B

1

CG310

2

1U_0402_6.3V6K

N17E@

BB21

IFP_IOVDD_5

BB23

0.1U_0402_10V7K

IFP_IOVDD_6

N17E-G1_BGA2152~D

@

UG9Q

9/23 IFPD

1

CG48

N17E@

2

Under GPU

IFPD

BC15

IFP_IOVDD_7

+PEX_VDD

A A

1

CG42

N17E@

2

4.7U_0603_6.3V6M

BC17

0.1U_0402_10V7K

N17E@

IFP_IOVDD_8

N17E-G1_BGA2152~D

@

1

CG53

2

BD23

IFPAB_RSET

BD21

IFPAB_PLLVDD

BB17

IFP_IOVDD_2

BB15

IFP_IOVDD_1

BB18

IFP_IOVDD_3

BB20

CG308

N17E@

0.1U_0402_10V7K

IFP_IOVDD_4

IFPAB

N17E-G1_BGA2152~D

@

DVI/HDMI

SDA SCL

TXC TXC

TXD0 TXD0

TXD1 TXD1

TXD2 TXD2

DP

IFPC_AUX_SDA*

IFPC_AUX_SCL

SDA

IFPD_AUX_SDA*

SCL

IFPD_AUX_SCL

TXC TXC

TXD0 TXD0

TXD1 TXD1

TXD2 TXD2

DP

IFPC_L3*

IFPC_L3

IFPC_L2*

IFPC_L2

IFPC_L1*

IFPC_L1

IFPC_L0*

IFPC_L0

IFPD_L3*

IFPD_L3

IFPD_L2*

IFPD_L2

IFPD_L1*

IFPD_L1

IFPD_L0*

IFPD_L0

BL9 BK9

BF17 BE17

BF18 BG18

BG20 BH20

BF20 BE20

BF11 BE11

BM14 BM15

BL15 BK15

BK17 BL17

BM17 BM18

DL-DVI

SDA SCL

TXC TXC

TXD0 TXD0

TXD1 TXD1

TXD2 TXD2

TXD3 TXD3

TXD4 TXD4

TXD5 TXD5

IFPC_I2C_DAT IFPC_I2C_CLK

SDA SCL

TXC TXC

TXD0 TXD0

TXD1 TXD1

TXD2 TXD2

SDA SCL

TXC TXC

TXD0 TXD0

TXD1 TXD1

TXD2 TXD2

IFPA_AUX_SDA*

IFPA_AUX_SCL

IFPB_AUX_SDA*

IFPB_AUX_SCL

RG156

10K_0402_5%

N17E@

DPDVI/HDMI

BH11 BG11

BF21

IFPA_L3*

BG21

IFPA_L3

BG23

IFPA_L2*

BH23

IFPA_L2

BF23

IFPA_L1*

BE23

IFPA_L1

BF24

IFPA_L0*

BG24

IFPA_L0

BG12 BH12

BL18

IFPB_L3*

BK18

IFPB_L3

BK20

IFPB_L2*

BL20

IFPB_L2

BM20

IFPB_L1*

BM21

IFPB_L1

BL21

IFPB_L0*

BK21

IFPB_L0

+1V8_AON +1V8_AON

12

RG571 10K_0402_5%

2

N17E@

DMN61D9UDW-7 2N SOT363-6

SB00001GW00

Vgs:0.5V~1V

IFPC_CLK_N <44> IFPC_CLK_P <44>

IFPC_TX0_N <44> IFPC_TX0_P <44>

IFPC_TX1_N <44> IFPC_TX1_P <44>

IFPC_TX2_N <44> IFPC_TX2_P <44>

DMN61D9UDW-7 2N SOT363-6

N17E@

QG8A

61

5

SB00001GW00

N17E@

QG8B

MIOA_D0 MIOA_D1 MIOA_D2 MIOA_D3 MIOA_D4 MIOA_D5 MIOA_D6 MIOA_D7 MIOA_D8

MIOA_D9 MIOA_D10 MIOA_D11

MIOA_CTL3 MIOA_HSYNC MIOA_VSYNC

MIOA_DE

MIOA_CLKOUT

MIOA_CLKIN

Under GPU

AN9 AM2 AN7 AN6 AR1 AR6 AR5 AM8 AN3 AR8 AR3 AR2

AT7 AM1 AR7 AN1

AN2

AM3

N17E@

1

CG43

N17E@

2

4.7U_0603_6.3V6M

Under GPU

1

CG40

2

HDMI 2.0

1

CG51

2

N17E@

Under GPU

5

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2015/09/18 2016/09/18

Compal Secret Data

Deciphered Date

2

Title

N17E-G1(2/6) eDP,HDMI,mDP

Size Document Number Rev

C

Date: Sheet

LA-E992P

1

47 77Tuesday, July 25, 2017

of

1.0(A00)

5

D D

4

3

2

1

UG9B

2/23 FBA

FBA_D0<52> FBA_D1<52> FBA_D2<52> FBA_D3<52> FBA_D4<52> FBA_D5<52> FBA_D6<52> FBA_D7<52> FBA_D8<52> FBA_D9<52> FBA_D10<52> FBA_D11<52> FBA_D12<52> FBA_D13<52> FBA_D14<52> FBA_D15<52> FBA_D16<52> FBA_D17<52> FBA_D18<52> FBA_D19<52> FBA_D20<52> FBA_D21<52> FBA_D22<52> FBA_D23<52> FBA_D24<52> FBA_D25<52> FBA_D26<52> FBA_D27<52> FBA_D28<52> FBA_D29<52> FBA_D30<52> FBA_D31<52> FBA_D32<52> FBA_D33<52> FBA_D34<52> FBA_D35<52> FBA_D36<52> FBA_D37<52> FBA_D38<52> FBA_D39<52> FBA_D40<52> FBA_D41<52> FBA_D42<52>

C C

FBA_D43<52> FBA_D44<52> FBA_D45<52> FBA_D46<52> FBA_D47<52> FBA_D48<52> FBA_D49<52> FBA_D50<52> FBA_D51<52> FBA_D52<52> FBA_D53<52> FBA_D54<52> FBA_D55<52> FBA_D56<52> FBA_D57<52> FBA_D58<52> FBA_D59<52> FBA_D60<52> FBA_D61<52> FBA_D62<52> FBA_D63<52>

FBA_DBI0<52> FBA_DBI1<52> FBA_DBI2<52> FBA_DBI3<52> FBA_DBI4<52> FBA_DBI5<52> FBA_DBI6<52> FBA_DBI7<52>

FBA_EDC0<52> FBA_EDC1<52> FBA_EDC2<52> FBA_EDC3<52> FBA_EDC4<52> FBA_EDC5<52> FBA_EDC6<52> FBA_EDC7<52>

+FBX_PLLAVDD

1

CG59

N17E@

2

B B

0.1U_0402_10V7K

U51

FBA_D0

U48

FBA_D1

U50

FBA_D2

U49

FBA_D3

R51

FBA_D4

R50

FBA_D5

R47

FBA_D6

U46

FBA_D7

V46

FBA_D8

Y45

FBA_D9

Y47

FBA_D10

Y46

FBA_D11

V50

FBA_D12

V47

FBA_D13

U52

FBA_D14

V51

FBA_D15

AJ44

FBA_D16

AG48

FBA_D17

AJ45

FBA_D18

AG49

FBA_D19

AF46

FBA_D20

AF47

FBA_D21

AF48

FBA_D22

AD47

FBA_D23

AD49

FBA_D24

AD48

FBA_D25

AC46

FBA_D26

AC47

FBA_D27

AA47

FBA_D28

AA46

FBA_D29

AA45

FBA_D30

Y44

FBA_D31

AW51

FBA_D32

BA52

FBA_D33

AW50

FBA_D34

BA51

FBA_D35

BA50

FBA_D36

BB50

FBA_D37

BA49

FBA_D38

AW49

FBA_D39

AV48

FBA_D40

AT49

FBA_D41

AT47

FBA_D42

AT48

FBA_D43

AT46

FBA_D44

AV51

FBA_D45

AV52

FBA_D46

AV49

FBA_D47

AJ48

FBA_D48

AJ46

FBA_D49

AJ47

FBA_D50

AK49

FBA_D51

AM47

FBA_D52

AM46

FBA_D53

AN48

FBA_D54

AN49

FBA_D55

AM44

FBA_D56

AM45

FBA_D57

AN45

FBA_D58

AN46

FBA_D59

AR48

FBA_D60

AN47

FBA_D61

AR47

FBA_D62

AR46

FBA_D63

U47

FBA_DQM0

Y48

FBA_DQM1

AG47

FBA_DQM2

AC48

FBA_DQM3

BB51

FBA_DQM4

AV50

FBA_DQM5

AM48

FBA_DQM6

AR49

FBA_DQM7

R48

FBA_DQS_WP0

V48

FBA_DQS_WP1

AF44

FBA_DQS_WP2

AA48

FBA_DQS_WP3

BB52

FBA_DQS_WP4

AT50

FBA_DQS_WP5

AK48

FBA_DQS_WP6

AR51

FBA_DQS_WP7

W47

GND_694

W49

GND_695

W51

GND_696

W6

GND_697

W8

GND_698

Y14

GND_699

Y15

GND_700

Y16

GND_701

AF42

FB_REFPLL_AVDD0

L29

1

2

0.1U_0402_10V7K

FB_REFPLL_AVDD1

CG60

N17E@

12

RG47 10K_0402_5%

N17E@

FBA_CMD1

FBA_CMD17

FBA_CMD2

FBA_CMD18

12

RG53 10K_0402_5%

N17E@

N17E-G1_BGA2152~D@

+1.35VS_VGA

12

FBA_CMD0

FBA_CMD1 FBA_CMD2 FBA_CMD3 FBA_CMD4 FBA_CMD5 FBA_CMD6 FBA_CMD7 FBA_CMD8

FBA_CMD9 FBA_CMD10 FBA_CMD11 FBA_CMD12 FBA_CMD13 FBA_CMD14 FBA_CMD15 FBA_CMD16 FBA_CMD17 FBA_CMD18 FBA_CMD19 FBA_CMD20 FBA_CMD21 FBA_CMD22 FBA_CMD23 FBA_CMD24 FBA_CMD25 FBA_CMD26 FBA_CMD27 FBA_CMD28 FBA_CMD29 FBA_CMD30 FBA_CMD31 FBA_CMD32 FBA_CMD33 FBA_CMD34 FBA_CMD35

FBA_DBG_RFU1 FBA_DBG_RFU2

FBA_CLK0

FBA_CLK0*

FBA_CLK1

FBA_CLK1*

FBA_WCK01 FBA_WCK01* FBA_WCKB01

FBA_WCKB01*

FBA_WCK23 FBA_WCK23* FBA_WCKB23

FBA_WCKB23*

FBA_WCK45 FBA_WCK45* FBA_WCKB45

FBA_WCKB45*

FBA_WCK67 FBA_WCK67* FBA_WCKB67

FBA_WCKB67*

FBA_PLL_AVDD

RG48 10K_0402_5%

N17E@

RG54 10K_0402_5%

N17E@

Y51 Y52 Y49 AA52 AA51 AA50 AC50 AC51 AC52 AC49 AD52 AD51 AD50 AF50 AF51 AF52 AN50 AN51 AN52 AM49 AM52 AM51 AM50 AK50 AK51 AK52 AJ49 AJ52 AJ51 AJ50 AG50 AG51 AG52 AF49 Y50 AR50

AA44 AN44

AG45 AG46 AK46 AK45

U45 U44 V45 V44 AC45 AC44 AD46 AD45 AV47 AV46 AW48 AW47 AR45 AR44 AT45 AT44

+FBX_PLLAVDD

AN42

N17E@

Under GPU

FBA_CMD0 <52> FBA_CMD1 <52> FBA_CMD2 <52> FBA_CMD3 <52> FBA_CMD4 <52> FBA_CMD5 <52> FBA_CMD6 <52> FBA_CMD7 <52> FBA_CMD8 <52> FBA_CMD9 <52> FBA_CMD10 <52> FBA_CMD11 <52> FBA_CMD12 <52> FBA_CMD13 <52> FBA_CMD14 <52> FBA_CMD15 <52> FBA_CMD16 <52> FBA_CMD17 <52> FBA_CMD18 <52> FBA_CMD19 <52> FBA_CMD20 <52> FBA_CMD21 <52> FBA_CMD22 <52> FBA_CMD23 <52> FBA_CMD24 <52> FBA_CMD25 <52> FBA_CMD26 <52> FBA_CMD27 <52> FBA_CMD28 <52> FBA_CMD29 <52> FBA_CMD30 <52> FBA_CMD31 <52>

FBA_CLK0 <52> FBA_CLK0# <52> FBA_CLK1 <52> FBA_CLK1# <52>

FBA_WCK01 <52> FBA_WCK01# <52>

FBA_WCK23 <52> FBA_WCK23# <52>

FBA_WCK45 <52> FBA_WCK45# <52>

FBA_WCK67 <52> FBA_WCK67# <52>

1 2

LG6

@N17E@

PBY160808T-300Y-N_2P

1 2

LG7

N17E@

PBY160808T-300Y-N_2P

1

CG54

CG55

N17E@

2

0.1U_0402_16V7K

22U_0805_6.3V6M

+1V8_MAIN

FBB_D0<53> FBB_D1<53> FBB_D2<53> FBB_D3<53> FBB_D4<53> FBB_D5<53> FBB_D6<53> FBB_D7<53> FBB_D8<53> FBB_D9<53> FBB_D10<5 3> FBB_D11<5 3> FBB_D12<5 3> FBB_D13<5 3> FBB_D14<5 3> FBB_D15<5 3> FBB_D16<5 3> FBB_D17<5 3> FBB_D18<5 3> FBB_D19<5 3> FBB_D20<5 3> FBB_D21<5 3> FBB_D22<5 3> FBB_D23<5 3> FBB_D24<5 3> FBB_D25<5 3> FBB_D26<5 3> FBB_D27<5 3> FBB_D28<5 3> FBB_D29<5 3> FBB_D30<5 3> FBB_D31<5 3> FBB_D32<5 3> FBB_D33<5 3> FBB_D34<5 3> FBB_D35<5 3> FBB_D36<5 3> FBB_D37<5 3> FBB_D38<5 3> FBB_D39<5 3> FBB_D40<5 3> FBB_D41<5 3> FBB_D42<5 3> FBB_D43<5 3> FBB_D44<5 3> FBB_D45<5 3> FBB_D46<5 3> FBB_D47<5 3> FBB_D48<5 3> FBB_D49<5 3> FBB_D50<5 3> FBB_D51<5 3> FBB_D52<5 3> FBB_D53<5 3> FBB_D54<5 3> FBB_D55<5 3> FBB_D56<5 3> FBB_D57<5 3> FBB_D58<5 3> FBB_D59<5 3> FBB_D60<5 3> FBB_D61<5 3> FBB_D62<5 3> FBB_D63<5 3>

FBB_DBI0<53> FBB_DBI1<53> FBB_DBI2<53> FBB_DBI3<53> FBB_DBI4<53> FBB_DBI5<53> FBB_DBI6<53> FBB_DBI7<53>

FBB_EDC0<53> FBB_EDC1<53> FBB_EDC2<53> FBB_EDC3<53> FBB_EDC4<53> FBB_EDC5<53> FBB_EDC6<53> FBB_EDC7<53>

UG9C

H32 D32

A33 B32 E32

G32

J30

F32 H36 G36

J36

F36

F33 D33

J32 G33

E45 D45

F45 G45 D42

E42

F42 H41

E41

F39

E39 D39

F38

E38 D36

E36 M50

P48 M51 M49

P47

P52 R46

P46

L50

L51

L52

L49 M46

L47 M48 M47 D48 C50 C48 C49

E49

E50

F49

F48

F50 D52

J50 H48 H51

J51 H49 H52

C32

E33

E44 G39

P49

L48 D50 H50

B33

E35 G44 H38

P50

J48 D51

F51

Y17

Y18

Y19

Y20

Y21

Y22

Y23

Y24

N17E-G1_BGA2152~D

@

FBB_CMD1

FBB_CMD17

FBB_CMD2

FBB_CMD18

3/23 FBB

FBB_D0 FBB_D1 FBB_D2 FBB_D3 FBB_D4 FBB_D5 FBB_D6 FBB_D7 FBB_D8 FBB_D9 FBB_D10 FBB_D11 FBB_D12 FBB_D13 FBB_D14 FBB_D15 FBB_D16 FBB_D17 FBB_D18 FBB_D19 FBB_D20 FBB_D21 FBB_D22 FBB_D23 FBB_D24 FBB_D25 FBB_D26 FBB_D27 FBB_D28 FBB_D29 FBB_D30 FBB_D31 FBB_D32 FBB_D33 FBB_D34 FBB_D35 FBB_D36 FBB_D37 FBB_D38 FBB_D39 FBB_D40 FBB_D41 FBB_D42 FBB_D43 FBB_D44 FBB_D45 FBB_D46 FBB_D47 FBB_D48 FBB_D49 FBB_D50 FBB_D51 FBB_D52 FBB_D53 FBB_D54 FBB_D55 FBB_D56 FBB_D57 FBB_D58 FBB_D59 FBB_D60 FBB_D61 FBB_D62 FBB_D63

FBB_DQM0 FBB_DQM1 FBB_DQM2 FBB_DQM3 FBB_DQM4 FBB_DQM5 FBB_DQM6 FBB_DQM7

FBB_DQS_WP0 FBB_DQS_WP1 FBB_DQS_WP2 FBB_DQS_WP3 FBB_DQS_WP4 FBB_DQS_WP5 FBB_DQS_WP6 FBB_DQS_WP7

GND_702 GND_703 GND_704 GND_705 GND_706 GND_707 GND_708 GND_709

UG9D

FBB_CMD0 FBB_CMD1 FBB_CMD2 FBB_CMD3 FBB_CMD4 FBB_CMD5 FBB_CMD6 FBB_CMD7 FBB_CMD8

FBB_CMD9 FBB_CMD10 FBB_CMD11 FBB_CMD12 FBB_CMD13 FBB_CMD14 FBB_CMD15 FBB_CMD16 FBB_CMD17 FBB_CMD18 FBB_CMD19 FBB_CMD20 FBB_CMD21 FBB_CMD22 FBB_CMD23 FBB_CMD24 FBB_CMD25 FBB_CMD26 FBB_CMD27 FBB_CMD28 FBB_CMD29 FBB_CMD30 FBB_CMD31 FBB_CMD32 FBB_CMD33 FBB_CMD34 FBB_CMD35

FBB_DBG_RFU1 FBB_DBG_RFU2

FBB_CLK0

FBB_CLK0*

FBB_CLK1

FBB_CLK1*

FBB_WCK01

FBB_WCK01*

FBB_WCKB01

FBB_WCKB01*

FBB_WCK23

FBB_WCK23*

FBB_WCKB23

FBB_WCKB23*

FBB_WCK45

FBB_WCK45*

FBB_WCKB45

FBB_WCKB45*

FBB_WCK67

FBB_WCK67*

FBB_WCKB67

FBB_WCKB67*

FBB_PLL_AVDD

B35 A35 D35 A36 B36 C36 C38 B38 A38 D38 A39 B39 C39 C41 B41 A41 B49 A49 A48 D47 A47 B47 C47 C45 B45 A45 D44 A44 B44 C44 C42 B42 A42 D41 C35 B50

J35 J41

H42 G42 F47 E47

J33 H33 G35 H35 J39 H39 F41 G41 L46 L45 M44 M45 H47 H46 J47 J46

L38

N17E@

FBB_CMD0 <53> FBB_CMD1 <53> FBB_CMD2 <53> FBB_CMD3 <53> FBB_CMD4 <53> FBB_CMD5 <53> FBB_CMD6 <53> FBB_CMD7 <53> FBB_CMD8 <53> FBB_CMD9 <53> FBB_CMD10 <53> FBB_CMD11 <53> FBB_CMD12 <53> FBB_CMD13 <53> FBB_CMD14 <53> FBB_CMD15 <53> FBB_CMD16 <53> FBB_CMD17 <53> FBB_CMD18 <53> FBB_CMD19 <53> FBB_CMD20 <53> FBB_CMD21 <53> FBB_CMD22 <53> FBB_CMD23 <53> FBB_CMD24 <53> FBB_CMD25 <53> FBB_CMD26 <53> FBB_CMD27 <53> FBB_CMD28 <53> FBB_CMD29 <53> FBB_CMD30 <53> FBB_CMD31 <53>

FBB_CLK0 <53> FBB_CLK0# <53> FBB_CLK1 <53> FBB_CLK1# <53>

FBB_WCK01 <53> FBB_WCK01# <53>

FBB_WCK23 <53> FBB_WCK23# <53>

FBB_WCK45 <53> FBB_WCK45# <53>

FBB_WCK67 <53> FBB_WCK67# <53>

0.1U_0402_16V4Z~D

CG56

1

2

FBC_D0<54> FBC_D1<54> FBC_D2<54> FBC_D3<54> FBC_D4<54> FBC_D5<54> FBC_D6<54> FBC_D7<54> FBC_D8<54> FBC_D9<54> FBC_D10<54> FBC_D11<54> FBC_D12<54> FBC_D13<54> FBC_D14<54> FBC_D15<54> FBC_D16<54> FBC_D17<54> FBC_D18<54> FBC_D19<54> FBC_D20<54> FBC_D21<54> FBC_D22<54> FBC_D23<54> FBC_D24<54> FBC_D25<54> FBC_D26<54> FBC_D27<54> FBC_D28<54> FBC_D29<54> FBC_D30<54> FBC_D31<54> FBC_D32<54> FBC_D33<54> FBC_D34<54> FBC_D35<54> FBC_D36<54> FBC_D37<54> FBC_D38<54> FBC_D39<54> FBC_D40<54> FBC_D41<54> FBC_D42<54> FBC_D43<54> FBC_D44<54> FBC_D45<54> FBC_D46<54> FBC_D47<54> FBC_D48<54> FBC_D49<54> FBC_D50<54> FBC_D51<54> FBC_D52<54> FBC_D53<54> FBC_D54<54> FBC_D55<54> FBC_D56<54> FBC_D57<54> FBC_D58<54> FBC_D59<54> FBC_D60<54> FBC_D61<54> FBC_D62<54> FBC_D63<54>

FBC_DBI0<54> FBC_DBI1<54> FBC_DBI2<54> FBC_DBI3<54> FBC_DBI4<54> FBC_DBI5<54> FBC_DBI6<54> FBC_DBI7<54>

FBC_EDC0<54> FBC_EDC1<54> FBC_EDC2<54> FBC_EDC3<54> FBC_EDC4<54> FBC_EDC5<54> FBC_EDC6<54> FBC_EDC7<54>

Under GPU Under GPU

+1.35VS_VGA +1.35VS_VGA

12

RG49

RG50

10K_0402_5%

N17E@

12

RG55

RG56

10K_0402_5%

N17E@

4/23 FBC

C6

FBC_D0

D6

FBC_D1

A6

FBC_D2

B6

FBC_D3

B4

FBC_D4

A4

FBC_D5

B3

FBC_D6

C4

FBC_D7

D9

FBC_D8

C9

FBC_D9

E9

FBC_D10

B9

FBC_D11

B8

FBC_D12

A8

FBC_D13

F6

FBC_D14

E6

FBC_D15

F18

FBC_D16

G18

FBC_D17

E18

FBC_D18

H18

FBC_D19

D15

FBC_D20

E15

FBC_D21

G17

FBC_D22

H17

FBC_D23

J15

FBC_D24

H15

FBC_D25

E14

FBC_D26

F14

FBC_D27

H11

FBC_D28

G11

FBC_D29

F11

FBC_D30

E11

FBC_D31

J29

FBC_D32

F30

FBC_D33

H29

FBC_D34

G30

FBC_D35

B30

FBC_D36

A30

FBC_D37

H30

FBC_D38

C30

FBC_D39

D27

FBC_D40

J26

FBC_D41

F27

FBC_D42

G27

FBC_D43

C27

FBC_D44

B27

FBC_D45

A27

FBC_D46

G29

FBC_D47

H20

FBC_D48

D18

FBC_D49

G20

FBC_D50

E20

FBC_D51

F23

FBC_D52

E21

FBC_D53

D21

FBC_D54

E23

FBC_D55

G24

FBC_D56

H26

FBC_D57

F24

FBC_D58

G26

FBC_D59

F26

FBC_D60

D26

FBC_D61

B26

FBC_D62

C26

FBC_D63

A5

FBC_DQM0

C8

FBC_DQM1

J18

FBC_DQM2

F12

FBC_DQM3

D29

FBC_DQM4

E27

FBC_DQM5

F20

FBC_DQM6

E26

FBC_DQM7

D5

FBC_DQS_WP0

D8

FBC_DQS_WP1

E17

FBC_DQS_WP2

E12

FBC_DQS_WP3

E30

FBC_DQS_WP4

B29

FBC_DQS_WP5

G21

FBC_DQS_WP6

E24

FBC_DQS_WP7

Y25

GND_710

Y26

GND_711

Y27

GND_712

Y28

GND_713

Y29

GND_714

Y30

GND_715

Y31

GND_716

Y32

GND_717

N17E-G1_BGA2152~D

@

FBC_CMD1

FBC_CMD17

FBC_CMD2

FBC_CMD18

12

RG51 10K_0402_5%

N17E@

RG57 10K_0402_5%

N17E@

FBC_CMD0 FBC_CMD1 FBC_CMD2 FBC_CMD3 FBC_CMD4 FBC_CMD5 FBC_CMD6 FBC_CMD7 FBC_CMD8

FBC_CMD9 FBC_CMD10 FBC_CMD11 FBC_CMD12 FBC_CMD13 FBC_CMD14 FBC_CMD15 FBC_CMD16 FBC_CMD17 FBC_CMD18 FBC_CMD19 FBC_CMD20 FBC_CMD21 FBC_CMD22 FBC_CMD23 FBC_CMD24 FBC_CMD25 FBC_CMD26 FBC_CMD27 FBC_CMD28 FBC_CMD29 FBC_CMD30 FBC_CMD31 FBC_CMD32 FBC_CMD33 FBC_CMD34 FBC_CMD35

FBC_DBG_RFU1 FBC_DBG_RFU2

FBC_CLK0*

FBC_CLK1*

FBC_WCK01

FBC_WCK01* FBC_WCKB01 FBC_WCKB01*

FBC_WCK23

FBC_WCK23* FBC_WCKB23 FBC_WCKB23*

FBC_WCK45

FBC_WCK45* FBC_WCKB45 FBC_WCKB45*

FBC_WCK67

FBC_WCK67* FBC_WCKB67 FBC_WCKB67*

FBC_PLL_AVDD

12

RG52 10K_0402_5%

N17E@

12

RG58 10K_0402_5%

N17E@

FBC_CLK0

FBC_CLK1

UG9E

C11 B11 A11 D11 A12 B12 C12 C14 B14 A14 D14 A15 B15 C15 C17 B17 B24 A24 D23 A23 B23 C23 C21 B21 A21 D20 A20 B20 C20 C18 B18 A18 D17 A17 A9 C24

J14 J23

G15 F15 H21 J21

F8 G8 G9 F9 H12 G12 G14 H14 J27 H27 E29 F29 G23 H23 H24 J24

+FBX_PLLAVDD+FBX_PLLAVDD

L17

N17E@

FBC_CMD0 <54> FBC_CMD1 <54> FBC_CMD2 <54> FBC_CMD3 <54> FBC_CMD4 <54> FBC_CMD5 <54> FBC_CMD6 <54> FBC_CMD7 <54> FBC_CMD8 <54> FBC_CMD9 <54> FBC_CMD10 <54> FBC_CMD11 <54> FBC_CMD12 <54> FBC_CMD13 <54> FBC_CMD14 <54> FBC_CMD15 <54> FBC_CMD16 <54> FBC_CMD17 <54> FBC_CMD18 <54> FBC_CMD19 <54> FBC_CMD20 <54> FBC_CMD21 <54> FBC_CMD22 <54> FBC_CMD23 <54> FBC_CMD24 <54> FBC_CMD25 <54> FBC_CMD26 <54> FBC_CMD27 <54> FBC_CMD28 <54> FBC_CMD29 <54> FBC_CMD30 <54> FBC_CMD31 <54>

FBC_CLK0 <54> FBC_CLK0# <54> FBC_CLK1 <54> FBC_CLK1# <54>

FBC_WCK01 <54> FBC_WCK01# <54>

FBC_WCK23 <54> FBC_WCK23# <54>

FBC_WCK45 <54> FBC_WCK45# <54>

FBC_WCK67 <54> FBC_WCK67# <54>

0.1U_0402_16V4Z~D

CG57

1

2

AK8 AK4 AK2 AK3 AK5 AK6 AK9 AK7 AG4

AF9 AG6 AG7

AJ4

AJ5

AJ6 AG5

Y6 Y5 V5

Y4 AA6 AA5 AC5 AC4 AD7 AC6

AF6

AD6

AF7 AF8 AF2 AF3

F4

E1

F3

F5

D2

D1

C3

C2

J5 J4

L8

J2 F1 F2 H4 H5 V7 V8 V6 V9 U4 R5 R6 U8 P6 R9 P4 P5 L7 L6 L4 L5

AJ1 AG1 AA7 AD5

D3 H3 U5 M9

AJ3 AG2 AA9

AF4

E3 H2 U6 M5

Y33

Y34

Y35

Y36

Y37

Y38

Y39

Y9

N17E-G1_BGA2152~D

@

5/23 FBD

FBD_D0 FBD_D1 FBD_D2 FBD_D3 FBD_D4 FBD_D5 FBD_D6 FBD_D7 FBD_D8 FBD_D9 FBD_D10 FBD_D11 FBD_D12 FBD_D13 FBD_D14 FBD_D15 FBD_D16 FBD_D17 FBD_D18 FBD_D19 FBD_D20 FBD_D21 FBD_D22 FBD_D23 FBD_D24 FBD_D25 FBD_D26 FBD_D27 FBD_D28 FBD_D29 FBD_D30 FBD_D31 FBD_D32 FBD_D33 FBD_D34 FBD_D35 FBD_D36 FBD_D37 FBD_D38 FBD_D39 FBD_D40 FBD_D41 FBD_D42 FBD_D43 FBD_D44 FBD_D45 FBD_D46 FBD_D47 FBD_D48 FBD_D49 FBD_D50 FBD_D51 FBD_D52 FBD_D53 FBD_D54 FBD_D55 FBD_D56 FBD_D57 FBD_D58 FBD_D59 FBD_D60 FBD_D61 FBD_D62 FBD_D63

FBD_DQM0 FBD_DQM1 FBD_DQM2 FBD_DQM3 FBD_DQM4 FBD_DQM5 FBD_DQM6 FBD_DQM7

FBD_DQS_WP0 FBD_DQS_WP1 FBD_DQS_WP2 FBD_DQS_WP3 FBD_DQS_WP4 FBD_DQS_WP5 FBD_DQS_WP6 FBD_DQS_WP7

GND_0718 GND_0719 GND_0720 GND_0721 GND_0722 GND_0723 GND_0724 GND_0725

AD2

FBD_CMD0

AD1

FBD_CMD1

AD4

FBD_CMD2

AC1

FBD_CMD3

AC2

FBD_CMD4

AC3

FBD_CMD5

AA3

FBD_CMD6

AA2

FBD_CMD7

AA1

FBD_CMD8

AA4

FBD_CMD9

Y1

FBD_CMD10

Y2

FBD_CMD11

Y3

FBD_CMD12

V3

FBD_CMD13

V2

FBD_CMD14

V1

FBD_CMD15

L3

FBD_CMD16

L2

FBD_CMD17

L1

FBD_CMD18

M4

FBD_CMD19

M1

FBD_CMD20

M2

FBD_CMD21

M3

FBD_CMD22

P3

FBD_CMD23

P2

FBD_CMD24

P1

FBD_CMD25

R4

FBD_CMD26

R1

FBD_CMD27

R2

FBD_CMD28

R3

FBD_CMD29

U3

FBD_CMD30

U2

FBD_CMD31

U1

FBD_CMD32

V4

FBD_CMD33

AD3

FBD_CMD34

J3

FBD_CMD35

AC9

FBD_DBG_RFU1

P9

FBD_DBG_RFU2

Y8

FBD_CLK0

Y7

FBD_CLK0*

R8

FBD_CLK1

R7

FBD_CLK1*

AJ8

FBD_WCK01

AJ7

FBD_WCK01*

AG8

FBD_WCKB01

AG9

FBD_WCKB01*

AD8

FBD_WCK23

AD9

FBD_WCK23*

AC7

FBD_WCKB23

AC8

FBD_WCKB23*

J6

FBD_WCK45

J7

FBD_WCK45*

H7

FBD_WCKB45

H6

FBD_WCKB45*

P8

FBD_WCK67

P7

FBD_WCK67*

M7

FBD_WCKB67

M8

FBD_WCKB67*

+FBX_PLLAVDD

V11

FBD_PLL_AVDD

GP106

GP104

UNUSED

FBD

0.1U_0402_16V4Z~D

CG58

1

N17E@

2

Under GPU

22uF 10uF 4.7uF 1uF 0.1uF

FBx_PLL_AVDD

A A

5

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

Compal Secret Data

2015/09/18 2016/09/18

Deciphered Date

Title

N17E-G1(3/6) MEM interface

Size Document Number Rev

Custom

Date: Sheet of

Date: Sheet

1

LA-E992P

of

48 77Tuesday, July 25, 2017

1.0(A00)

5

4

3

2

1

+NVVDD1

D D

C C

B B

UG9G

19/23 VDD_2/2

AP21

VDD_145 VDD_146 VDD_147 VDD_148 VDD_149 VDD_150 VDD_151 VDD_152 VDD_153 VDD_154 VDD_155 VDD_156 VDD_157 VDD_158 VDD_159 VDD_160 VDD_161 VDD_162 VDD_163 VDD_164 VDD_165 VDD_166 VDD_167 VDD_168 VDD_169 VDD_170 VDD_171 VDD_172 VDD_173 VDD_174 VDD_175 VDD_176 VDD_177 VDD_178 VDD_179 VDD_180 VDD_181 VDD_182 VDD_183 VDD_184 VDD_185 VDD_186 VDD_187 VDD_188 VDD_189 VDD_190 VDD_191 VDD_192 VDD_193 VDD_194 VDD_195 VDD_196 VDD_197 VDD_198 VDD_199 VDD_200 VDD_201 VDD_202 VDD_203 VDD_204 VDD_205 VDD_206 VDD_207 VDD_208 VDD_209 VDD_210 VDD_211 VDD_212 VDD_213 VDD_214 VDD_215 VDD_216 VDD_217 VDD_218

VDD_219 VDD_220 VDD_221 VDD_222 VDD_223 VDD_224 VDD_225 VDD_226 VDD_227 VDD_228 VDD_229 VDD_230 VDD_231 VDD_232 VDD_233 VDD_234 VDD_235 VDD_236 VDD_237 VDD_238 VDD_239 VDD_240 VDD_241 VDD_242 VDD_243 VDD_244 VDD_245 VDD_246 VDD_247 VDD_248 VDD_249 VDD_250 VDD_251 VDD_252 VDD_253 VDD_254 VDD_255 VDD_321 VDD_322 VDD_323 VDD_324 VDD_325 VDD_326 VDD_327 VDD_328 VDD_329 VDD_330 VDD_331 VDD_332 VDD_333 VDD_334 VDD_335 VDD_336 VDD_337 VDD_338 VDD_339 VDD_340 VDD_341 VDD_342 VDD_343 VDD_344 VDD_345 VDD_346 VDD_347 VDD_348 VDD_349 VDD_350 VDD_351 VDD_352 VDD_353 VDD_354 VDD_355 VDD_356

AP22 AP23 AP30 AP31 AP32 AP33 AP34 AR13 AR40 AT14 AT15 AT16 AT17 AT18 AT19 AT20 AT21 AT22 AT23 AT24 AT25 AT26 AT27 AT28 AT29 AT30 AT31 AT32 AT33 AT34 AT35 AT36 AT37 AT38 AT39 AT42 AU43

AV19 AV20 AV21 AV22 AV23 AV30 AV31 AV32 AV33 AV34 AV42 AV43

AV44 AW13 AW40 AW42 AW43 AW44 AW45

AY14

AY18

AY22

AY26

AY27

AY31

AY35

AY39

AY43

AY45

BA43

BA44

BA45

BA46

BA47

BB38

BB39

10U_0603_6.3V6M

470U_D2_2VM_R4.5M~D

1

CG245

CG244

1

+

2

N17E@

+NVVDD1

BB45 BB46 BB47 BB48 BC38 BC39 BC40 BC41 BC45 BC47 BC49 BD39 BD41 BD46 BD47 BD48 BD49 BD50 BD51 BE41 BE42 BE43 BE46 BE47 BE48 BE49 BE50 BE51 BE52 BF42 BF44 BF45 BF47 BF49 BF51 BG43 BG44 U16 U17 U18 U19 U20 U21 U22 U23 U24 U25 U26 U27 U28 U29 U30 U31 U32 U33 U34 U35 U36 U37 U38 U39 V13 V40 W19 W20 W21 W22 W23 W30 W31 W32 W33 W34

+NVVDD1

UG9J

23/23 VDDS

AP27

VDDS_057

AP28

VDDS_058

AP29

VDDS_059

AP35

VDDS_060

AP36

VDDS_061

AP37

VDDS_062

AP38

VDDS_063

AP39

VDDS_064

AV14

VDDS_065

AV15

VDDS_066

AV16

VDDS_067

AV17

VDDS_068

AV18

VDDS_069

AV24

VDDS_070

AV25

VDDS_071

AV26

VDDS_072

AV27

VDDS_073

AV28

VDDS_074

AV29

VDDS_075

AV35

VDDS_076

AV36

VDDS_077

AV37

VDDS_078

AV38

VDDS_079

AV39

VDDS_080

R14

VDDS_081

R15

VDDS_082

R16

VDDS_083

R17

VDDS_084

R18

VDDS_085

R24

VDDS_086

R25

VDDS_087

R26

VDDS_088

R27

VDDS_089

R28

VDDS_090

R29

VDDS_091

R35

VDDS_092

R36

VDDS_093

R37

VDDS_094

R38

VDDS_095

R39

VDDS_096

W14

VDDS_097

W15

VDDS_098

W16

VDDS_099

W17

VDDS_100

W18

VDDS_101

W24

VDDS_102

W25

VDDS_103

W26

VDDS_104

W27

VDDS_105

W28

VDDS_106

W29

VDDS_107

W35

VDDS_108

W36

VDDS_109

W37

VDDS_110

W38

VDDS_111

W39

VDDS_112

N17E-G1_BGA2152~ D

@

VDDS_001 VDDS_002 VDDS_003 VDDS_004 VDDS_005 VDDS_006 VDDS_007 VDDS_008 VDDS_009 VDDS_010 VDDS_011 VDDS_012 VDDS_013 VDDS_014 VDDS_015 VDDS_016 VDDS_017 VDDS_018 VDDS_019 VDDS_020 VDDS_021 VDDS_022 VDDS_023 VDDS_024 VDDS_025 VDDS_026 VDDS_027 VDDS_028 VDDS_029 VDDS_030 VDDS_031 VDDS_032 VDDS_033 VDDS_034 VDDS_035 VDDS_036 VDDS_037 VDDS_038 VDDS_039 VDDS_040 VDDS_041 VDDS_042 VDDS_043 VDDS_044 VDDS_045 VDDS_046 VDDS_047 VDDS_048 VDDS_049 VDDS_050 VDDS_051 VDDS_052 VDDS_053 VDDS_054 VDDS_055 VDDS_056

VDDS_SENSE GNDS_SENSE

AC14 AC15 AC16 AC17 AC18 AC24 AC25 AC26 AC27 AC28 AC29 AC35 AC36 AC37 AC38 AC39 AF14 AF15 AF16 AF17 AF18 AF24 AF25 AF26 AG27 AG28 AG29 AG35 AG36 AG37 AG38 AG39 AK14 AK15 AK16 AK17 AK18 AK24 AK25 AK26 AK27 AK28 AK29 AK35 AK36 AK37 AK38 AK39 AP14 AP15 AP16 AP17 AP18 AP24 AP25 AP26

BM45 BM44

+NVVDD1

NVVDD_VCC_SENSE NVVDD_VSS_SENSE

+1.35VS_VGA

1

+

N17E@

2

UG9H

20/23 FBVDDQ

AA10

FBVDDQ_01 FBVDDQ_02 FBVDDQ_03 FBVDDQ_04 FBVDDQ_05 FBVDDQ_06 FBVDDQ_07 FBVDDQ_08 FBVDDQ_09 FBVDDQ_10 FBVDDQ_11 FBVDDQ_12 FBVDDQ_13 FBVDDQ_14 FBVDDQ_15 FBVDDQ_16 FBVDDQ_17 FBVDDQ_18 FBVDDQ_19 FBVDDQ_20 FBVDDQ_21 FBVDDQ_22 FBVDDQ_23 FBVDDQ_24 FBVDDQ_25 FBVDDQ_26 FBVDDQ_27 FBVDDQ_28 FBVDDQ_29 FBVDDQ_30 FBVDDQ_31 FBVDDQ_76 FBVDDQ_77 FBVDDQ_78 FBVDDQ_79 FBVDDQ_80 FBVDDQ_81 FBVDDQ_82 FBVDDQ_83 FBVDDQ_84 FBVDDQ_85 FBVDDQ_86 FBVDDQ_87

N17E@

FB_CAL_TERM_GND

N17E-G1_BGA2152~ D

@

FBVDDQ_32 FBVDDQ_33 FBVDDQ_34 FBVDDQ_35 FBVDDQ_36 FBVDDQ_37 FBVDDQ_38 FBVDDQ_39 FBVDDQ_40 FBVDDQ_41 FBVDDQ_42 FBVDDQ_43 FBVDDQ_44 FBVDDQ_45 FBVDDQ_46 FBVDDQ_47 FBVDDQ_48 FBVDDQ_49 FBVDDQ_50 FBVDDQ_51 FBVDDQ_52 FBVDDQ_53 FBVDDQ_54 FBVDDQ_55 FBVDDQ_56 FBVDDQ_57 FBVDDQ_58 FBVDDQ_59 FBVDDQ_60 FBVDDQ_61 FBVDDQ_62 FBVDDQ_63 FBVDDQ_64 FBVDDQ_65 FBVDDQ_66 FBVDDQ_67 FBVDDQ_68 FBVDDQ_69 FBVDDQ_70 FBVDDQ_71 FBVDDQ_72 FBVDDQ_73 FBVDDQ_74 FBVDDQ_75

FBVDDQ_SENSE

FB_VREF

FB_CAL_PD_VDDQ

FB_CAL_PU_GND

AA11 AA42 AA43 AC10 AC11 AC42 AC43 AD10 AD11 AD42 AD43 AF10 AF43 AG10 AG11 AG42 AG43 AJ10 AJ11 AJ42 AJ43 AK10 AK11 AK42 AK43 AM42 AM43 AN43 AR42 AR43

R42 R43 U10 U11 U43 V10 V42 V43 Y10 Y11 Y42 Y43

10U_0603_6.3V6M

220U_D2 SX_2VY_R9M

CG243

CG242

1

2

+1.35VS_VGA

AT43 K12 K14 K15 K17 K18 K20 K21 K23 K24 K26 K27 K29 K30 K32 K33 K35 K36 K38 K39 K41 L14 L15 L18 L20 L21 L23 L24 L26 L27 L30 L32 L33 L35 L36 L39 M10 M43 P10 P11 P42 P43 R10 R11

E52

P45

Place close to UG9

FBCAL_VDDQ

R44

FBCAL_GND

P44

FBCAL_TERM

R45

CSSN_B+<68>

CSSP_B+<68>

CSSN_NVVDD<68>

CSSP_NVVDD<68>

1 2

RG67 40.2_0402_1%N17E@

1 2

RG68 40.2_0402_1%N17E@

1 2

RG69 60.4_0402_1%N17E@

FB_VDDQ_SENSE <69>

1 2

10_0402_1% RG59

N17E@

RG62 10_0402_1%

1 2

N17E@

1 2

RG64 10_0402_1%

N17E@

RG66 10_0402_1%

1 2

N17E@

+1.35VS_VGA

2

CG62

N17E@

1

VIN1N

10U_0603_25V6M

VIN1P

VIN2N VIN2P

2

CG63

N17E@

1

10U_0603_25V6M

+3V3_SYS

100P_0402_50V8J~D

1

N17E@

UG11

4

VS

11

IN-1

12

IN+1

14

IN-2

15

IN+2

1

IN-3

2

IN+3

6

SCL

7

SDA

INA3221AIRGVR_VQFN16_ 4X4

N17E@

SA00007UF00

CG61

2

Warning

ThermalPad

Critical

N17E@

16

VPU

13

TC

N17E@

10

RG529

PV

0_0201_5%

9

1 2

O.D

8

5

A0

3

GND

17

RG65 10K_0402_1%

N17E@

12

GPIO3_OC_WARN# <46>

12

RG60

RG61

N17E@

1.8K_0402_1%

I2CC_SCL<46> I2CC_SDA<46>

22uF 10uF 4.7uF 1uF 0.1uF470uF

N17E-G1_BGA2152~ D

@

VDD_SENSE GND_SENSE

BK45 BL45

NVVDD_VCC_SENSE <6 7> NVVDD_VSS_SENSE <67>

FBVDDQ

129 24

Place under GPU

+1.35VS_VGA +1.35VS_VGA

1

CG18510U_0603_6.3V6M

CG18410U_0603_6.3V6M

CG18610U_0603_6.3V6M

N17E@

2

A A

2

1

CG18810U_0603_6.3V6M

CG18710U_0603_6.3V6M

N17E@

2

5

1

CG1921U_0402_6.3V4Z

CG1941U_0402_6.3V4Z

CG1931U_0402_6.3V4Z

CG1951U_0402_6.3V4Z

N17E@

2

N17E@

2

1

CG1971U_0402_6.3V4Z

CG1981U_0402_6.3V4Z

CG1961U_0402_6.3V4Z

N17E@

2

1

CG1991U_0402_6.3V4Z

N17E@

2

1

CG2001U_0402_6.3V4Z

CG2021U_0402_6.3V4Z

CG2011U_0402_6.3V4Z

CG2031U_0402_6.3V4Z

N17E@

2

1

CG2051U_0402_6.3V4Z

CG2041U_0402_6.3V4Z

N17E@

2

1

CG2071U_0402_6.3V4Z

CG2081U_0402_6.3V4Z

CG2061U_0402_6.3V4Z

CG2091U_0402_6.3V4Z

N17E@

2

4

1

CG2111U_0402_6.3V4Z

CG2101U_0402_6.3V4Z

CG2121U_0402_6.3V4Z

CG2131U_0402_6.3V4Z

N17E@

2

1

CG528330U_D3_2VM_R6M

CG2151U_0402_6.3V4Z

CG2141U_0402_6.3V4Z

+

N17E@

2

N17E@

2

Place Near GPU

1

CG21810U_0603_6.3V6M

CG21610U_0603_6.3V6M

CG21710U_0603_6.3V6M

CG21910U_0603_6.3V6M

N17E@

2

N17E@

2

1

CG22022U_0603_6.3V6M

N17E@

2

3

1

CG22122U_0603_6.3V6M

CG22422U_0603_6.3V6M

CG22322U_0603_6.3V6M

CG22222U_0603_6.3V6M

N17E@

2

1

CG22622U_0603_6.3V6M

CG22522U_0603_6.3V6M

N17E@

2

1

CG22722U_0603_6.3V6M

N17E@

2

1

CG22822U_0603_6.3V6M

CG19010U_0603_6.3V6M

CG19110U_0603_6.3V6M

CG18910U_0603_6.3V6M

N17E@

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFOR MATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFOR MATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFOR MATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2015/09/18 2016/09/18

2

Compal Secret Data

Deciphered Date

Title

N17E-G1(4/6) Power

Size Doc ument Number Rev

Custom

Date: She et of

Date: She et

1

LA-E992P

of

49 7 7Tuesday, July 25, 201 7

1.0(A00)

5

4

3

2

1

+NVVDD1

UG9I

21/23 NC/1V8

AT9

NC_1

BA6

NC_2

D D

C C

BA9 BD14 BE12

BG6

BH6

BJ11

BJ9

BK44

+1V8_AON

N17E@

1

2

NC_3 NC_4 NC_5 NC_6 NC_7 NC_8 NC_9 NC_10

N17E-G1_BGA2152~D

@

4.7U_0402_6.3V6M

Near

1U_0402_6.3V4Z

CG291

CG292

1

2

N17E@

Under GPU

1V8_AON_1 1V8_AON_2 1V8_AON_3

0.1U_0201_6.3V6K

1

2

VDD18_01 VDD18_02 VDD18_03 VDD18_04 VDD18_05 VDD18_06 VDD18_07 VDD18_08 VDD18_09 VDD18_10 VDD18_11 VDD18_12

CG293

1

N17E@

2

+1V8_AON

BA10 BB14 BC14

+1V8_MAIN

AM10 AM11 AN10 AN11 AR10 AR11 AT10 AT11 AV10 AV11 AW10 AW11

0.1U_0201_6.3V6K

CG294

N17E@

GPU

+1V8_MAIN

4.7U_0402_6.3V6M

CG296

CG295

N17E@

1

B B

+1V8_MAIN

N17E@

2

1

2

1

N17E@

2

0.1U_0201_6.3V6K

CG302

CG301

1

N17E@

2

4.7U_0402_6.3V6M

CG297

N17E@

0.1U_0201_6.3V6K

CG303

N17E@

Near GPU

1U_0402_6.3V4Z

CG298

1

N17E@

2

0.1U_0201_6.3V6K

CG304

1

N17E@

2

1U_0402_6.3V4Z

CG300

CG299

1

N17E@

2

0.1U_0201_6.3V6K

CG306

CG305

N17E@

CG307

1

N17E@

2

UG9F

18/21 VDD_1/2

AA14

VDD_001

AA15

VDD_002

AA16

VDD_003

AA17

VDD_004

AA18

VDD_005

AA19

VDD_006

AA20

VDD_007

AA21

VDD_008

AA22

VDD_009

AA23

VDD_010

AA24

VDD_011

AA25

VDD_012

AA26

VDD_013

AA27

VDD_014

AA28

VDD_015

AA29

VDD_016

AA30

VDD_017

AA31

VDD_018

AA32

VDD_019

AA33

VDD_020

AA34

VDD_021

AA35

VDD_022

AA36

VDD_023

AA37

VDD_024

AA38

VDD_025

AA39

VDD_026

AB13

VDD_027

AB40

VDD_028

AC19

VDD_029

AC20

VDD_030

AC21

VDD_031

AC22

VDD_032

AC23

VDD_033

AC30

VDD_034

AC31

VDD_035

AC32

VDD_036

AC33

VDD_037

AC34

VDD_038

AE14

VDD_039

AE15

VDD_040

AE16

VDD_041

AE17

VDD_042

AE18

VDD_043

AE19

VDD_044

AE20

VDD_045

AE21

VDD_046

AE22

VDD_047

AE23

VDD_048

AE24

VDD_049

AE25

VDD_050

AE26

VDD_051

AE27

VDD_052

AE28

VDD_053

AE29

VDD_054

AE30

VDD_055

AE31

VDD_056

AE32

VDD_057

AE33

VDD_058

AE34

VDD_059

AE35

VDD_060

AE36

VDD_061

AE37

VDD_062

AE38

VDD_063

AE39

VDD_064

AF13

VDD_065

AF30

VDD_066

AF31

VDD_067

AF32

VDD_068

AF33

VDD_069

AF34

VDD_070

AF40

VDD_071

AG13

VDD_072

AG19

VDD_073

AG20

VDD_074

AG21

VDD_075

BG45

VDD_256

BG46

VDD_257

BG47

VDD_258

BG48

VDD_259

BG49

VDD_260

BG50

VDD_261

BG51

VDD_262

BG52

VDD_263

BH44

VDD_264

BH45

VDD_265

BH47

VDD_266

BH48

VDD_267

BH49

VDD_268

BH50

VDD_269

BH51

VDD_270

BH52

VDD_271

BJ44

VDD_272

BJ45

VDD_273

BJ46

VDD_274

BJ47

VDD_275

BJ48

VDD_276

BJ49

VDD_277

BJ50

VDD_278

BJ51

VDD_279

BJ52

VDD_280

BK47

VDD_281

BK48

VDD_282

BK49

VDD_283

BK50

VDD_284

BK51

VDD_285

N17E-G1_BGA2152~D

@

VDD_076 VDD_077 VDD_078 VDD_079 VDD_080 VDD_081 VDD_082 VDD_083 VDD_084 VDD_085 VDD_086 VDD_087 VDD_088 VDD_089 VDD_090 VDD_091 VDD_092 VDD_093 VDD_094 VDD_095 VDD_096 VDD_097 VDD_098 VDD_099 VDD_100 VDD_101 VDD_102 VDD_103 VDD_104 VDD_105 VDD_106 VDD_107 VDD_108 VDD_109 VDD_110 VDD_111 VDD_112 VDD_113 VDD_114 VDD_115 VDD_116 VDD_117 VDD_118 VDD_119 VDD_120 VDD_121 VDD_122 VDD_123 VDD_124 VDD_125 VDD_126 VDD_127 VDD_128 VDD_129 VDD_130 VDD_131 VDD_132 VDD_133 VDD_134 VDD_135 VDD_136 VDD_137 VDD_138 VDD_139 VDD_140 VDD_141 VDD_142 VDD_143 VDD_144 VDD_286 VDD_287 VDD_288 VDD_289 VDD_290 VDD_291 VDD_292 VDD_293 VDD_294 VDD_295 VDD_296 VDD_297 VDD_298 VDD_299 VDD_300 VDD_301 VDD_302 VDD_303 VDD_304 VDD_305 VDD_306 VDD_307 VDD_308 VDD_309 VDD_310 VDD_311 VDD_312 VDD_313 VDD_314 VDD_315 VDD_316 VDD_317 VDD_318 VDD_319 VDD_320

AG22 AG23 AG40 AH14 AH15 AH16 AH17 AH18 AH19 AH20 AH21 AH22 AH23 AH24 AH25 AH26 AH27 AH28 AH29 AH30 AH31 AH32 AH33 AH34 AH35 AH36 AH37 AH38 AH39 AK19 AK20 AK21 AK22 AK23 AK30 AK31 AK32 AK33 AK34 AL13 AL40 AM14 AM15 AM16 AM17 AM18 AM19 AM20 AM21 AM22 AM23 AM24 AM25 AM26 AM27 AM28 AM29 AM30 AM31 AM32 AM33 AM34 AM35 AM36 AM37 AM38 AM39 AP19 AP20 BK52 BL46 BL47 BL48 BL49 BL50 BL51 BL52 BM47 BM48 BM49 BM50 BM51 N14 N18 N22 N26 N27 N31 N35 N39 P13 P40 R19 R20 R21 R22 R23 R30 R31 R32 R33 R34 U14 U15

+NVVDD1

Under GPU

A A

UG9K

16/23 GND_1/3

A2

GND_001

A26

GND_002

A29

GND_003

A3

GND_004

A32

GND_005

A50

GND_006

A51

GND_007

AA49

GND_008

AA8

GND_009

AB10

GND_010

AB14

GND_011

AB15

GND_012

AB16

GND_013

AB17

GND_014

AB18

GND_015

AB19

GND_016

AB2

GND_017

AB20

GND_018

AB21

GND_019

AB22

GND_020

AB23

GND_021

AB24

GND_022

AB25

GND_023

AB26

GND_024

AB27

GND_025

AB28

GND_026

AB29

GND_027

AB30

GND_028

AB31

GND_029

AB32

GND_030

AB33

GND_031

AB34

GND_032

AB35

GND_033

AB36

GND_034

AB37

GND_035

AB38

GND_036

AB39

GND_037

AB4

GND_038

AB43

GND_039

AB45

GND_040

AB47

GND_041

AB49

GND_042

AB51

GND_043

AB6

GND_044

AB8

GND_045

AD14

GND_046

AD15

GND_047

AD16

GND_048

AD17

GND_049

AD18

GND_050

AD19

GND_051

AD20

GND_052

AD21

GND_053

AD22

GND_054

AD23

GND_055

AD24

GND_056

AD25

GND_057

AD26

GND_058

AD27

GND_059

AD28

GND_060

AD29

GND_061

AD30

GND_062

AD31

GND_063

AD32

GND_064

AD33

GND_065

AD34

GND_066

AD35

GND_067

AD36

GND_068

AD37

GND_069

AD38

GND_070

AD39

GND_071

AD44

GND_072

AE10

GND_073

AE2

GND_074

AE4

GND_075

AE43

GND_076

AE45

GND_077

AE47

GND_078

AE49

GND_079

AE51

GND_080

AE6

GND_081

AE8

GND_082

AF1

GND_083

AF19

GND_084

AF20

GND_085

AF21

GND_086

AF22

GND_087

AF23

GND_088

AF27

GND_089

AF28

GND_090

AF29

GND_091

AF35

GND_092

AF36

GND_093

AF37

GND_094

AF38

GND_095

AF39

GND_096

AF45

GND_097

AF5

GND_098

AG14

GND_099

AG15

GND_100

AG16

GND_101

AG17

GND_102

AG18

GND_103

AG24

GND_104

AG25

GND_105

AG26

GND_106

AG3

GND_107

AG30

GND_108

AG31

GND_109

AG32

GND_110

AG33

GND_111

AG34

GND_112

AG44

GND_113

AH10

GND_114

AH2

GND_115

AH4

GND_116

AH43

GND_117

AH45

GND_118

AH47

GND_119

AH49

GND_120

AH51

GND_121

N17E-G1_BGA2152~D

@

GND_122 GND_123 GND_124 GND_125 GND_126 GND_127 GND_128 GND_129 GND_130 GND_131 GND_132 GND_133 GND_134 GND_135 GND_136 GND_137 GND_138 GND_139 GND_140 GND_141 GND_142 GND_143 GND_144 GND_145 GND_146 GND_147 GND_148 GND_149 GND_150 GND_151 GND_152 GND_153 GND_154 GND_155 GND_156 GND_157 GND_158 GND_159 GND_160 GND_161 GND_162 GND_163 GND_164 GND_165 GND_166 GND_167 GND_168 GND_169 GND_170 GND_171 GND_172 GND_173 GND_174 GND_175 GND_176 GND_177 GND_178 GND_179 GND_180 GND_181 GND_182 GND_183 GND_184 GND_185 GND_186 GND_187 GND_188 GND_189 GND_190 GND_191 GND_192 GND_193 GND_194 GND_195 GND_196 GND_197 GND_198 GND_199 GND_200 GND_201 GND_202 GND_203 GND_204 GND_205 GND_206 GND_207 GND_208 GND_209 GND_210 GND_211 GND_212 GND_213 GND_214 GND_215 GND_216 GND_217 GND_218 GND_219 GND_220 GND_221 GND_222 GND_223 GND_224 GND_225 GND_226 GND_227 GND_228 GND_229 GND_230 GND_231 GND_232 GND_233 GND_234 GND_235 GND_236 GND_237 GND_480

GND_H

GND_F

AH6 AH8 AJ14 AJ15 AJ16 AJ17 AJ18 AJ19 AJ2 AJ20 AJ21 AJ22 AJ23 AJ24 AJ25 AJ26 AJ27 AJ28 AJ29 AJ30 AJ31 AJ32 AJ33 AJ34 AJ35 AJ36 AJ37 AJ38 AJ39 AJ9 AK1 AK44 AK47 AL10 AL14 AL15 AL16 AL17 AL18 AL19 AL2 AL20 AL21 AL22 AL23 AL24 AL25 AL26 AL27 AL28 AL29 AL30 AL31 AL32 AL33 AL34 AL35 AL36 AL37 AL38 AL39 AL4 AL43 AL45 AL47 AL49 AL51 AL6 AL8 AM4 AM9 AN14 AN15 AN16 AN17 AN18 AN19 AN20 AN21 AN22 AN23 AN24 AN25 AN26 AN27 AN28 AN29 AN30 AN31 AN32 AN33 AN34 AN35 AN36 AN37 AN38 AN39 AN4 AN5 AN8 AP10 AP2 AP4 AP43 AP45 AP47 AP49 AP51 AP6 AP8 AR14 AR15 AR16 AR17 AR18 AR19 BL37 BD24 BC24

UG9L

17/23 GND_2/3

AR20

GND_238

AR21

GND_239

AR22

GND_240

AR23

GND_241

AR24

GND_242

AR25

GND_243

AR26

GND_244

AR27

GND_245

AR28

GND_246

AR29

GND_247

AR30

GND_248

AR31

GND_249

AR32

GND_250

AR33

GND_251

AR34

GND_252

AR35

GND_253

AR36

GND_254

AR37

GND_255

AR38

GND_256

AR39

GND_257

AR4

GND_258

AR52

GND_259

AR9

GND_260

AT4

GND_261

AT5

GND_262

AT51

GND_263

AT52

GND_264

AT8

GND_265

AU10

GND_266

AU14

GND_267

AU15

GND_268

AU16

GND_269

AU17

GND_270

AU18

GND_271

AU19

GND_272

AU2

GND_273

AU20

GND_274

AU21

GND_275

AU22

GND_276

AU23

GND_277

AU24

GND_278

AU25

GND_279

AU26

GND_280

AU27

GND_281

AU28

GND_282

AU29

GND_283

AU30

GND_284

AU31

GND_285

AU32

GND_286

AU33

GND_287

AU34

GND_288

AU35

GND_289

AU36

GND_290

AU37

GND_291

AU38

GND_292

AU39

GND_293

AU4

GND_294

AU45

GND_295

AU47

GND_296

AU49

GND_297

AU51

GND_298

AU6

GND_299

AU8

GND_300

AV4

GND_301

AV45

GND_302

AV9

GND_303

AW14

GND_304

AW15

GND_305

AW16

GND_306

AW17

GND_307

AW18

GND_308

AW19

GND_309

AW20

GND_310

AW21

GND_311

AW22

GND_312

AW23

GND_313

AW24

GND_314

AW25

GND_315

AW26

GND_316

AW27

GND_317

AW28

GND_318

AW29

GND_319

AW30

GND_320

AW31

GND_321

AW32

GND_322

AW33

GND_323

AW34

GND_324

AW35

GND_325

AW36

GND_326

AW37

GND_327

AW38

GND_328

AW39

GND_329

AW4

GND_330

AW46

GND_331

AW5

GND_332

AW52

GND_333

AW8

GND_334

AY10

GND_335

AY2

GND_336

AY4

GND_337

AY47

GND_338

AY49

GND_339

AY51

GND_340

AY6

GND_341

AY8

GND_342

B1

GND_343

B10

GND_344

B13

GND_345

B16

GND_346

B19

GND_347

B2

GND_348

B22

GND_349

B25

GND_350

B28

GND_351

B31

GND_352

B34

GND_353

B37

GND_354

B40

GND_355

B43

GND_356

B46

GND_357

B48

GND_358

N17E-G1_BGA2152~D

@

GND_361 GND_362 GND_363 GND_364 GND_365 GND_366 GND_367 GND_368 GND_369 GND_370 GND_371 GND_372 GND_373 GND_374 GND_375 GND_376 GND_377 GND_378 GND_379 GND_380 GND_381 GND_382 GND_383 GND_384 GND_385 GND_386 GND_387 GND_388 GND_389 GND_390 GND_391 GND_392 GND_393 GND_394 GND_395 GND_396 GND_397 GND_398 GND_399 GND_400 GND_401 GND_402 GND_403 GND_404 GND_405 GND_406 GND_407 GND_408 GND_409 GND_410 GND_411 GND_412 GND_413 GND_414 GND_415 GND_416 GND_417 GND_418 GND_419 GND_420 GND_421 GND_422 GND_423 GND_424 GND_425 GND_426 GND_427 GND_428 GND_429 GND_430 GND_431 GND_432 GND_433 GND_434 GND_435 GND_436 GND_437 GND_438 GND_439 GND_440 GND_441 GND_442 GND_443 GND_444 GND_445 GND_446 GND_447 GND_448 GND_449 GND_450 GND_451 GND_452 GND_453 GND_454 GND_455 GND_456 GND_457 GND_458 GND_459 GND_460 GND_461 GND_462 GND_463 GND_464 GND_465 GND_466 GND_467 GND_468 GND_469 GND_470 GND_471 GND_472 GND_473 GND_474 GND_475 GND_476 GND_477 GND_478 GND_479 GND_359 GND_360

B52 B7 BA48 BB49 BC13 BC16 BC19 BC2 BC22 BC25 BC28 BC31 BC34 BC37 BC4 BC51 BC6 BC8 BD26 BD29 BD32 BD35 BD38 BD52 BE10 BE13 BE15 BE16 BE18 BE19 BE21 BE22 BE24 BE25 BE27 BE28 BE30 BE31 BE33 BE34 BE36 BE37 BE39 BE40 BF2 BF4 BF41 BF6 BG10 BG13 BG16 BG19 BG22 BG25 BG28 BG31 BG34 BG37 BG40 BG42 BG7 BH15 BH18 BH2 BH21 BH24 BH27 BH30 BH33 BH36 BH39 BH42 BH5 BJ10 BJ12 BJ13 BJ14 BJ15 BJ16 BJ17 BJ18 BJ19 BJ20 BJ21 BJ22 BJ23 BJ24 BJ25 BJ26 BJ27 BJ28 BJ29 BJ30 BJ31 BJ32 BJ33 BJ34 BJ35 BJ36 BJ37 BJ38 BJ39 BJ40 BJ41 BJ42 BJ43 BJ7 BK1 BL1 BL10 BL13 BL16 BL19 BL2 BL22 BL25 BL28 BL31 BL34 B5 B51

UG9M

22/23 GND_3/3

BL43

GND_482

BL5

GND_483

BL7

GND_484

BM2

GND_485

BM3

GND_486

C1

GND_487

C29

GND_488

C33

GND_489

C5

GND_490

C51

GND_491

C52

GND_492

D10

GND_493

D12

GND_494

D13

GND_495

D16

GND_496

D19

GND_497

D22

GND_498

D24

GND_499

D25

GND_500

D28

GND_501

D30

GND_502

D31

GND_503

D34

GND_504

D37

GND_505

D4

GND_506

D40

GND_507

D43

GND_508

D46

GND_509

D49

GND_510

D7

GND_511

E2

GND_512

E4

GND_513

E48

GND_514

E5

GND_515

E51

GND_516

E8

GND_517

F10

GND_518

F13

GND_519

F16

GND_520

F17

GND_521

F19

GND_522

F21

GND_523

F22

GND_524

F25

GND_525

F28

GND_526

F31

GND_527

F34

GND_528

F35

GND_529

F37

GND_530

F40

GND_531

F43

GND_532

F44

GND_533

F46

GND_534

F52

GND_535

F7

GND_536

G2

GND_537

G38

GND_538

G4

GND_539

G47

GND_540

G49

GND_541

G51

GND_542

G6

GND_543

H1

GND_544

H10

GND_545

H13

GND_546

H16

GND_547

H19

GND_548

H22

GND_549

H25

GND_550

H28

GND_551

H31

GND_552

H34

GND_553

H37

GND_554

H40

GND_555

H43

GND_556

J1

GND_557

J12

GND_558

J17

GND_559

J20

GND_560

J38

GND_561

J49

GND_562

J52

GND_563

K13

GND_564

K16

GND_565

K19

GND_566

K2

GND_567

K22

GND_568

K25

GND_569

K28

GND_570

K31

GND_571

K34

GND_572

K37

GND_573

K4

GND_574

K40

GND_575

K45

GND_576

K47

GND_577

K49

GND_578

K51

GND_579

K6

GND_580

K8

GND_581

M52

GND_582

M6

GND_583

N10

GND_584

N2

GND_585

N4

GND_586

N43

GND_587

N45

GND_588

N47

GND_589

N49

GND_590

N51

GND_591

BL40

GND_481

N17E-G1_BGA2152~D

@

GND_592 GND_593 GND_594 GND_595 GND_596 GND_597 GND_598 GND_599 GND_600 GND_601 GND_602 GND_603 GND_604 GND_605 GND_606 GND_607 GND_608 GND_609 GND_610 GND_611 GND_612 GND_613 GND_614 GND_615 GND_616 GND_617 GND_618 GND_619 GND_620 GND_621 GND_622 GND_623 GND_624 GND_625 GND_626 GND_627 GND_628 GND_629 GND_630 GND_631 GND_632 GND_633 GND_634 GND_635 GND_636 GND_637 GND_638 GND_639 GND_640 GND_641 GND_642 GND_643 GND_644 GND_645 GND_646 GND_647 GND_648 GND_649 GND_650 GND_651 GND_652 GND_653 GND_654 GND_655 GND_656 GND_657 GND_658 GND_659 GND_660 GND_661 GND_662 GND_663 GND_664 GND_665 GND_666 GND_667 GND_668 GND_669 GND_670 GND_671 GND_672 GND_673 GND_674 GND_675 GND_676 GND_677 GND_678 GND_679 GND_680 GND_681 GND_682 GND_683 GND_684 GND_685 GND_686 GND_687 GND_688 GND_689 GND_690 GND_691 GND_692 GND_693

N6 N8 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P51 R49 R52 T10 T14 T15 T16 T17 T18 T19 T2 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 T31 T32 T33 T34 T35 T36 T37 T38 T39 T4 T43 T45 T47 T49 T51 T6 T8 U7 U9 V14 V15 V16 V17 V18 V19 V20 V21 V22 V23 V24 V25 V26 V27 V28 V29 V30 V31 V32 V33 V34 V35 V36 V37 V38 V39 V49 V52 W10 W2 W4 W43 W45

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2015/09/18 2016/09/18

Compal Secret Data

Deciphered Date

2

Title

N17E-G1(5/6) Power,GND

Size Document Number Rev

C

Date: Sheet

LA-E992P

1

50 77Tuesday, July 25, 2017

of

1.0(A00)

5

4

3

2

1

+1V8_AON

@N17E@

RG78 100K_0402_1%

1 2

+1V8_MAIN

STRAP0

@N17E@

RG90 100K_0402_1%

1 2

N17E@

LG5 PBY160808T-300Y-N_2P

D D

C C

B B

@N17E@

RG79 100K_0402_1%

1 2

STRAP1

@N17E@

RG91 100K_0402_1%

1 2

+1V8_MAIN

1

2

22U_0805_6.3VAM

CG239

N17E@

1 2

1

2

@N17E@

RG80 100K_0402_1%

1 2

STRAP2

@N17E@

RG92 100K_0402_1%

1 2

N17E@

LG4 PBY160808T-301Y-N

0.1U_0402_10V7K

CG237

CG238

1

2

N17E@

RG81 100K_0402_1%

1 2

@N17E@

RG93 100K_0402_1%

1 2

Under GPU

12

0.1U_0402_10V7K

CG236

1

2

N17E@

STRAP3

47U_0805_6.3V6M~D

0.1U_0402_10V7K

1

2

Under GPU

A A

22uF 10uF 4.7uF 1uF 0.1uF

47uF

VID_PLLVDD

SP_PLLVDD GPCPLL_AVDD

1 1

5

1

@N17E@

RG82 100K_0402_1%

1 2

STRAP4

N17E@

RG94 100K_0402_1%

1 2

0.1U_0402_10V7K

10U_0603_6.3V6M

CG232

CG235

CG230

CG231

1

2

N17E@

0.1U_0402_10V7K

CG233

CG234

1

2

N17E@

12

RG101 10K_0402_5%

N17E@

@N17E@

RG83 100K_0402_1%

1 2

STRAP5

N17E@

RG95 100K_0402_1%

1 2

BD12

BC12

U42

AF11

BB24

BJ6

XTALSSIN

BL6

XTALIN XTALOUT

CG75 22P_0402_50V8J

N17E@

6

4

UG9T

15/23 MISC 2

BL3

STRAP0

BL4

STRAP1

BM4

STRAP2

BM5

STRAP3

BK5

STRAP4

BJ5

STRAP5

N17E-G1_BGA2152~D

@

UG9S

14/23 XTAL/PLL

SP_PLLVDD

VID_PLLVDD

GPCPLL_AVDD0

GPCPLL_AVDD1

XS_PLLVDD

XTAL_SSIN

XTAL_IN

N17E-G1_BGA2152~D

@

N17E@

RG99 10M_0402_5%

1 2

YG1

1

GND

2

27MHZ 16PF +-30PPM 7M27070004F50Q5

SJ10000AY00

N17E@

GND

4

XTAL_OUTBUFF

3

SMB_ALT_ADDR

Low High

DEVID_SEL

Low High

VGA_DEVICE

Low High

PCIE_CFG

Low High

BK6

BM6

XTAL_OUT

3

BJ4

ROM_CS*

BK2

ROM_SI

BK4

ROM_SO

BK3

ROM_SCLK

BF9

BUFRST*

Single GPU Dual GPU

Original Device ID Re-brand Device ID

3D Device VGA Device

Normal signal swing Reduce the signal amplitude

XTALOUTBUFF_R

CG76 22P_0402_50V8J

N17E@

GPU_BUFRST#

12

RG98 100K_0402_5%~D

N17E@

3

N17E@

ROM_CS#

ROM_SI ROM_SO ROM_SCLK

T6

@

PAD~D

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

RG84 100K_0402_1%

1 2

@N17E@

RG87 100K_0402_1%

1 2

ROM_CS#

SAMSUNG , K4G80325FB-HC25

MICRON , MT51J256M32HF-80:A

HYNIX , H5GQ8H24MJR-R4C

2015/09/18 2016/09/18

+1V8_AON

N17E@

RG85 100K_0402_1%

1 2

@N17E@

RG88 100K_0402_1%

1 2

RG74 10K_0402_5%

N17E@

1 2

RG76 33_0402_5%~D

N17E@

N17E-G1 VRAM

Compal Secret Data

Deciphered Date

N17E@

RG86 100K_0402_1%

1 2

@N17E@

RG89 100K_0402_1%

1 2

+1V8_AON

12

UG13

1

DGPU_ROM_SO_RROM_SO

CS#

2

DO(IO1)

3

WP#(IO2)

4

GND

W25Q80EWSSIG_SO8

@N17E@

HOLD#(IO3)

VCC

DI(IO0)

CLK

+1V8_AON

8 7

DGPU_ROM_SCLK

6

DGPU_ROM_SI

5

1

CG66

0.1U_0402_16V4Z~D

N17E@

2

N17E@

RG75

33_0402_5%~D

1 2 1 2

RG77

33_0402_5%~D

N17E@

10/25 Need check high(SOIC or WSON)

Strap1

Strap2

Strap3

Strap4

Strap0

L

H

L

2

H

L

H

L

H

Title

N17E-G1(6/6) strap pin,ROM

Size Document Number Rev

C

Date: Sheet

Strap5

L

LL

L

ROM_SCLK ROM_SI

RAMCFG

LA-E992P

1

0

1

2

1.0(A00)

51 77Tuesday, July 25, 2017

of

5

4

3

2

1

UG1

FBA_EDC3<48> FBA_EDC2<48> FBA_EDC1<48>

40.2_0402_1% RG102

N17E@

+1.35VS_VGA

RG104 1K_0402_1%N17E@ RG106 1K_0402_1%N17E@ RG108 121_0402_1%N17E@

1

CG4031U_0402_6.3V4Z

N17E@

2

+FBA_VREFC

1

CG78

2

N17E@

1.33K_0402_1% 820P_0402_25V7

1

CG881U_0402_6.3V4Z

CG891U_0402_6.3V4Z

N17E@

2

FBA_EDC0<48>

FBA_DBI3<48> FBA_DBI2<48> FBA_DBI1<48> FBA_DBI0<48>

FBA_CMD1<48>

FBA_CMD12<48> FBA_CMD14<48> FBA_CMD13<48> FBA_CMD11<48>

FBA_CMD5<48> FBA_CMD8<48> FBA_CMD9<48> FBA_CMD4<48> FBA_CMD6<48>

FBA_CMD7<48> FBA_CMD0<48> FBA_CMD10<48> FBA_CMD3<48> FBA_CMD15<48>

FBA_WCK23#<48> FBA_WCK23<48>

FBA_WCK01#<48> FBA_WCK01<48>

FBA_CMD2<48>

W=16mils

1

CG79

2

N17E@

820P_0402_25V7

1

CG901U_0402_6.3V4Z

CG911U_0402_6.3V4Z

N17E@

2

12 12 12

+FBA_VREFC

+1.35VS_VGA

1

N17E@

2

D D

FBA_CLK0<48> FBA_CLK0#<48>

+1.35VS_VGA

C C

1

CG39110U_0402_6.3V4Z

CG39022U_0603_6.3V6M

CG38822U_0603_6.3V6M

CG38922U_0603_6.3V6M

N17E@

2

B B

MEM_VREF<46,53,54>

MEM_VREF levels

70% of rail 50% of rail

A A

1

CG39310U_0402_6.3V4Z

CG39210U_0402_6.3V4Z

N17E@

2

Termination Enable

Termination Disable

GDDR5_A

1

CG3951U_0402_6.3V4Z

CG3961U_0402_6.3V4Z

CG3941U_0402_6.3V4Z

N17E@

2

G

+1.35VS_VGA

1

CG8022U_0603_6.3V6M

CG8122U_0603_6.3V6M

N17E@

2

5

1

CG3971U_0402_6.3V4Z

CG3981U_0402_6.3V4Z

N17E@

2

1 2

N17E@

RG111 931_0402_1%

1

D

QG2 MESS138W-G_SOT323-3

N17E@

S

3

Under VRAM

1

CG8222U_0603_6.3V6M

CG8310U_0402_6.3V4Z

N17E@

2

40.2_0402_1%

12

RG523

N17E@

0.01U_0402_16V7K CG313

N17E@

1

2

1

CG3991U_0402_6.3V4Z

N17E@

2

1

CG8410U_0402_6.3V4Z

N17E@

2

1

CG4001U_0402_6.3V4Z

N17E@

2

1

CG8510U_0402_6.3V4Z

N17E@

2

1

CG4011U_0402_6.3V4Z

N17E@

2

+1.35VS_VGA

12

1

CG861U_0402_6.3V4Z

N17E@

2

1

CG4021U_0402_6.3V4Z

N17E@

2

RG110 549_0402_1%

N17E@

RG112

N17E@

1

CG871U_0402_6.3V4Z

N17E@

2

C2

EDC0 EDC3

C13

EDC1 EDC2

R13

EDC2 EDC1

R2

EDC3 EDC0

D2

DBI0# DBI3#

D13

DBI1# DBI2#

P13

DBI2# DBI1#

P2

DBI3# DBI0#

J12

CK

J11

CK#

J3

CKE#

H11

BA0/A2 BA2/A4

K10

BA1/A5 BA3/A3

K11

BA2/A4 BA0/A2

H10

BA3/A3 BA1/A5

K4

A8/A7 A10/A0

H5

A9/A1 A11/A6

H4

A10/A0 A8/A7

K5

A11/A6 A9/A1

J5

A12/RFU/NC

A5

VPP/NC

U5

VPP/NC

J1

MF

J10

SEN

J13

ZQ

J4

ABI#

G3

RAS# CAS#

G12

CS# WE#

L3

CAS# RAS#

L12

WE# CS#

D5

WCK01# WCK23#

D4

WCK01 WCK23

P5

WCK23# WCK01#

P4

WCK23 WCK01

A10

VREFD

U10

VREFD

J14

VREFC

J2

RESET#

H1

VSS

K1

VSS

B5

VSS

G5

VSS

L5

VSS

T5

VSS

B10

VSS

D10

VSS

G10

VSS

L10

VSS

P10

VSS

T10

VSS

H14

VSS

K14

VSS

G1

VDD

L1

VDD

G4

VDD

L4

VDD

C5

VDD

R5

VDD

C10

VDD

R10

VDD

D11

VDD

G11

VDD

L11

VDD

P11

VDD

G14

VDD

L14

VDD

170-BALL

SGRAM GDDR5

H5GQ1H24AFR-T2L_BGA170

@

+1.35VS_VGA

1

CG9722U_0603_6.3V6M

N17E@

2

4

MF=1 MF=0

MF=0 MF=1 MF=0MF=1

1

CG9822U_0603_6.3V6M

2

1

CG9922U_0603_6.3V6M

CG10110U_0402_6.3V4Z

CG1031U_0402_6.3V4Z

CG10210U_0402_6.3V4Z

CG10010U_0402_6.3V4Z

N17E@

2

DQ24 DQ0 DQ25 DQ1 DQ26 DQ2 DQ27 DQ3 DQ28 DQ4 DQ29 DQ5 DQ30 DQ6 DQ31 DQ7 DQ16 DQ8 DQ17 DQ9 DQ18 DQ10 DQ19 DQ11 DQ20 DQ12 DQ21 DQ13 DQ22 DQ14 DQ23 DQ15 DQ8 DQ16 DQ9 DQ17 DQ10 DQ18 DQ11 DQ19 DQ12 DQ20 DQ13 DQ21 DQ14 DQ22 DQ15 DQ23 DQ0 DQ24 DQ1 DQ25 DQ2 DQ26 DQ3 DQ27 DQ4 DQ28 DQ5 DQ29 DQ6 DQ30 DQ7 DQ31

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

1

CG1051U_0402_6.3V4Z

CG1041U_0402_6.3V4Z

N17E@

2

A4 A2 B4 B2 E4 E2 F4 F2 A11 A13 B11 B13 E11 E13 F11 F13 U11 U13 T11 T13 N11 N13 M11 M13 U4 U2 T4 T2 N4 N2 M4 M2

B1 D1 F1 M1 P1 T1 G2 L2 B3 D3 F3 H3 K3 M3 P3 T3 E5 N5 E10 N10 B12 D12 F12 H12 K12 M12 P12 T12 G13 L13 B14 D14 F14 M14 P14 T14

A1 C1 E1 N1 R1 U1 H2 K2 A3 C3 E3 N3 R3 U3 C4 R4 F5 M5 F10 M10 C11 R11 A12 C12 E12 N12 R12 U12 H13 K13 A14 C14 E14 N14 R14 U14

1

CG1061U_0402_6.3V4Z

N17E@

2

VDD/VDDQ

FBA_D24 <48> FBA_D25 <48> FBA_D26 <48> FBA_D27 <48> FBA_D28 <48> FBA_D29 <48> FBA_D30 <48> FBA_D31 <48> FBA_D16 <48> FBA_D17 <48> FBA_D18 <48> FBA_D19 <48> FBA_D20 <48> FBA_D21 <48> FBA_D22 <48> FBA_D23 <48> FBA_D8 <48> FBA_D9 <48> FBA_D10 <48> FBA_D11 <48> FBA_D12 <48> FBA_D13 <48> FBA_D14 <48> FBA_D15 <48> FBA_D0 <48> FBA_D1 <48> FBA_D2 <48> FBA_D3 <48> FBA_D4 <48> FBA_D5 <48> FBA_D6 <48> FBA_D7 <48>

+1.35VS_VGA

1

CG32422U_0603_6.3V6M

CG32510U_0402_6.3V4Z

N17E@

2

+1.35VS_VGA

1

CG3351U_0402_6.3V4Z

CG3341U_0402_6.3V4Z

N17E@

2

22uF 10uF 1uF

3

FBA_EDC4<48> FBA_EDC5<48> FBA_EDC6<48> FBA_EDC7<48>

FBA_DBI4<48> FBA_DBI5<48> FBA_DBI6<48>

40.2_0402_1%

12

RG103

N17E@

RG105 1K_0402_1%N17E@ RG107 1K_0402_1%N17E@ RG109 121_0402_1%N17E@

1

CG3321U_0402_6.3V4Z

CG3331U_0402_6.3V4Z

N17E@

2

1

CG3421U_0402_6.3V4Z

CG3431U_0402_6.3V4Z

N17E@

2

Issued Date

FBA_DBI7<48>

FBA_CMD17<48>

FBA_CMD29<48> FBA_CMD27<48> FBA_CMD28<48> FBA_CMD30<48>

FBA_CMD25<48> FBA_CMD20<48> FBA_CMD21<48> FBA_CMD24<48> FBA_CMD22<48>

12 12 12

FBA_CMD23<48> FBA_CMD19<48> FBA_CMD31<48> FBA_CMD16<48> FBA_CMD26<48>

FBA_WCK45#<48> FBA_WCK45<48>

FBA_WCK67#<48> FBA_WCK67<48>

+FBA_VREFC

FBA_CMD18<48>

+1.35VS_VGA

2015/09/18 2016/09/18

FBA_CLK1<48> FBA_CLK1#<48>

1

2

1

2

1

CG32610U_0402_6.3V4Z

CG3281U_0402_6.3V4Z

CG32710U_0402_6.3V4Z

N17E@

2

1

CG3371U_0402_6.3V4Z

CG3381U_0402_6.3V4Z

CG3361U_0402_6.3V4Z

N17E@

2

3610

12

40.2_0402_1%

12

RG524

N17E@

0.01U_0402_16V7K CG314

1

N17E@

2

1

CG3301U_0402_6.3V4Z

CG3291U_0402_6.3V4Z

CG3311U_0402_6.3V4Z

N17E@

2

1

CG3401U_0402_6.3V4Z

CG3411U_0402_6.3V4Z

CG3391U_0402_6.3V4Z

N17E@

2

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C13 R13

D13 P13

H11 K10 K11 H10

G12

A10 U10

B10 D10 G10

P10

H14 K14

C10 R10 D11 G11

P11 G14

Compal Secret Data

2

UG2

MF=0 MF=1 MF=0MF=1

C2

EDC0 EDC3 EDC1 EDC2 EDC2 EDC1

R2

EDC3 EDC0

D2

DBI0# DBI3# DBI1# DBI2# DBI2# DBI1#

P2

DBI3# DBI0#

J12

CK

J11

CK#

J3

CKE#

BA0/A2 BA2/A4 BA1/A5 BA3/A3 BA2/A4 BA0/A2 BA3/A3 BA1/A5

K4

A8/A7 A10/A0

H5

A9/A1 A11/A6

H4

A10/A0 A8/A7

K5

A11/A6 A9/A1

J5

A12/RFU/NC

A5

VPP/NC

U5

VPP/NC

J1

MF

J10

SEN

J13

ZQ

J4

ABI#

G3

RAS# CAS# CS# WE#

L3

CAS# RAS#

L12

WE# CS#

D5

WCK01# WCK23#

D4

WCK01 WCK23

P5

WCK23# WCK01#

P4

WCK23 WCK01

VREFD VREFD

J14

VREFC

J2

RESET#

H1

VSS

K1

VSS

B5

VSS

G5

VSS

L5

VSS

T5

VSS VSS VSS VSS

L10

VSS VSS

T10

VSS VSS VSS

G1

VDD

L1

VDD

G4

VDD

L4

VDD

C5

VDD

R5

VDD VDD VDD VDD VDD

L11

VDD VDD VDD

L14

VDD

170-BALL

SGRAM GDDR5

H5GQ1H24AFR-T2L_BGA170

@

Deciphered Date

DQ24 DQ0 DQ25 DQ1 DQ26 DQ2 DQ27 DQ3 DQ28 DQ4 DQ29 DQ5 DQ30 DQ6 DQ31 DQ7 DQ16 DQ8 DQ17 DQ9

DQ18 DQ10 DQ19 DQ11 DQ20 DQ12 DQ21 DQ13 DQ22 DQ14 DQ23 DQ15 DQ8 DQ16 DQ9 DQ17 DQ10 DQ18 DQ11 DQ19 DQ12 DQ20 DQ13 DQ21 DQ14 DQ22 DQ15 DQ23 DQ0 DQ24 DQ1 DQ25 DQ2 DQ26 DQ3 DQ27 DQ4 DQ28 DQ5 DQ29 DQ6 DQ30 DQ7 DQ31

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

A4 A2 B4 B2 E4 E2 F4 F2 A11 A13 B11 B13 E11 E13 F11 F13 U11 U13 T11 T13 N11 N13 M11 M13 U4 U2 T4 T2 N4 N2 M4 M2

B1 D1 F1 M1 P1 T1 G2 L2 B3 D3 F3 H3 K3 M3 P3 T3 E5 N5 E10 N10 B12 D12 F12 H12 K12 M12 P12 T12 G13 L13 B14 D14 F14 M14 P14 T14

A1 C1 E1 N1 R1 U1 H2 K2 A3 C3 E3 N3 R3 U3 C4 R4 F5 M5 F10 M10 C11 R11 A12 C12 E12 N12 R12 U12 H13 K13 A14 C14 E14 N14 R14 U14

Title

Size Document Number Rev

Date: Sheet of

Date: Sheet

FBA_D32 <48> FBA_D33 <48> FBA_D34 <48> FBA_D35 <48> FBA_D36 <48> FBA_D37 <48> FBA_D38 <48> FBA_D39 <48> FBA_D40 <48> FBA_D41 <48> FBA_D42 <48> FBA_D43 <48> FBA_D44 <48> FBA_D45 <48> FBA_D46 <48> FBA_D47 <48> FBA_D48 <48> FBA_D49 <48> FBA_D50 <48> FBA_D51 <48> FBA_D52 <48> FBA_D53 <48> FBA_D54 <48> FBA_D55 <48> FBA_D56 <48> FBA_D57 <48> FBA_D58 <48> FBA_D59 <48> FBA_D60 <48> FBA_D61 <48> FBA_D62 <48> FBA_D63 <48>

+1.35VS_VGA+1.35VS_VGA

Compal Electronics, Inc.

GDDR5_A

LA-E992P

1

52 77Tuesday, July 25, 2017

1.0(A00)

of

5

4

3

2

1

UG3

FBB_EDC3<48> FBB_EDC2<48> FBB_EDC1<48>

40.2_0402_1% RG113

N17E@

+1.35VS_VGA

RG115 1K_0402_1%N17E@ RG117 1K_0402_1%N17E@ RG119 121_0402_1%N17E@

1

CG4191U_0402_6.3V4Z

N17E@

2

+FBB_VREFC

1

CG113

N17E@

2

1.33K_0402_1% 820P_0402_25V7

1

CG1241U_0402_6.3V4Z

CG1231U_0402_6.3V4Z

N17E@

2

FBB_EDC0<48>

FBB_DBI3<48> FBB_DBI2<48> FBB_DBI1<48> FBB_DBI0<48>

FBB_CMD1<48>

FBB_CMD12<48> FBB_CMD14<48> FBB_CMD13<48> FBB_CMD11<48>

FBB_CMD5<48> FBB_CMD8<48> FBB_CMD9<48> FBB_CMD4<48> FBB_CMD6<48>

FBB_CMD7<48> FBB_CMD0<48> FBB_CMD10<48> FBB_CMD3<48> FBB_CMD15<48>

FBB_WCK23#<48> FBB_WCK23<48>

FBB_WCK01#<48> FBB_WCK01<48>

FBB_CMD2<48>

W=16mils

1

CG114

N17E@

2

820P_0402_25V7

1

CG1261U_0402_6.3V4Z

CG1251U_0402_6.3V4Z

N17E@

2

12 12 12

+FBB_VREFC

+1.35VS_VGA

1

N17E@

2

D D

FBB_CLK0<48> FBB_CLK0#<48>

+1.35VS_VGA

C C

1

CG40710U_0402_6.3V4Z

CG40522U_0603_6.3V6M

CG40622U_0603_6.3V6M

CG40422U_0603_6.3V6M

N17E@

2

B B

MEM_VREF<46,52,54>

MEM_VREF levels

70% of rail 50% of rail

A A

GDDR5_B

1

CG40810U_0402_6.3V4Z

N17E@

2

Termination Enable

Termination Disable

1

CG40910U_0402_6.3V4Z

CG4101U_0402_6.3V4Z

N17E@

2

+1.35VS_VGA +1.35VS_VGA

1

CG4111U_0402_6.3V4Z

CG4121U_0402_6.3V4Z

N17E@

2

G

1

CG11622U_0603_6.3V6M

CG11522U_0603_6.3V6M

N17E@

2

5

1

CG4131U_0402_6.3V4Z

CG4141U_0402_6.3V4Z

N17E@

2

1 2

RG122 931_0402_1%

N17E@

1

D

QG3 MESS138W-G_SOT323-3

N17E@

S

3

Under VRAM

1

CG11810U_0402_6.3V4Z

CG11722U_0603_6.3V6M

N17E@

2

40.2_0402_1%

12

RG525

N17E@

0.01U_0402_16V7K CG315

N17E@

1

2

1

CG4151U_0402_6.3V4Z

N17E@

2

1

CG11910U_0402_6.3V4Z

N17E@

2

CG4161U_0402_6.3V4Z

N17E@

2

1

CG12010U_0402_6.3V4Z

N17E@

2

1

CG4171U_0402_6.3V4Z

N17E@

2

+1.35VS_VGA

12

1

CG1211U_0402_6.3V4Z

N17E@

2

1

CG4181U_0402_6.3V4Z

N17E@

2

RG121 549_0402_1%

N17E@

RG123

N17E@

1

CG1221U_0402_6.3V4Z

N17E@

2

C2

EDC0 EDC3

C13

EDC1 EDC2

R13

EDC2 EDC1

R2

EDC3 EDC0

D2

DBI0# DBI3#

D13

DBI1# DBI2#

P13

DBI2# DBI1#

P2

DBI3# DBI0#

J12

CK

J11

CK#

J3

CKE#

H11

BA0/A2 BA2/A4

K10

BA1/A5 BA3/A3

K11

BA2/A4 BA0/A2

H10

BA3/A3 BA1/A5

K4

A8/A7 A10/A0

H5

A9/A1 A11/A6

H4

A10/A0 A8/A7

K5

A11/A6 A9/A1

J5

A12/RFU/NC

A5

VPP/NC

U5

VPP/NC

J1

MF

J10

SEN

J13

ZQ

J4

ABI#

G3

RAS# CAS#

G12

CS# WE#

L3

CAS# RAS#

L12

WE# CS#

D5

WCK01# WCK23#

D4

WCK01 WCK23

P5

WCK23# WCK01#

P4

WCK23 WCK01

A10

VREFD

U10

VREFD

J14

VREFC

J2

RESET#

H1

VSS

K1

VSS

B5

VSS

G5

VSS

L5

VSS

T5

VSS

B10

VSS

D10

VSS

G10

VSS

L10

VSS

P10

VSS

T10

VSS

H14

VSS

K14

VSS

G1

VDD

L1

VDD

G4

VDD

L4

VDD

C5

VDD

R5

VDD

C10

VDD

R10

VDD

D11

VDD

G11

VDD

L11

VDD

P11

VDD

G14

VDD

L14

VDD

170-BALL

SGRAM GDDR5

H5GQ1H24AFR-T2L_BGA170

@

1

CG13222U_0603_6.3V6M

N17E@

2

4

MF=1 MF=0

MF=0 MF=1 MF=0MF=1

1

CG13510U_0402_6.3V4Z

CG13322U_0603_6.3V6M

CG13422U_0603_6.3V6M

N17E@

2

1

CG1381U_0402_6.3V4Z

CG13610U_0402_6.3V4Z

CG13710U_0402_6.3V4Z

N17E@

2

DQ24 DQ0 DQ25 DQ1 DQ26 DQ2 DQ27 DQ3 DQ28 DQ4 DQ29 DQ5 DQ30 DQ6 DQ31 DQ7 DQ16 DQ8 DQ17 DQ9 DQ18 DQ10 DQ19 DQ11 DQ20 DQ12 DQ21 DQ13 DQ22 DQ14 DQ23 DQ15 DQ8 DQ16 DQ9 DQ17 DQ10 DQ18 DQ11 DQ19 DQ12 DQ20 DQ13 DQ21 DQ14 DQ22 DQ15 DQ23 DQ0 DQ24 DQ1 DQ25 DQ2 DQ26 DQ3 DQ27 DQ4 DQ28 DQ5 DQ29 DQ6 DQ30 DQ7 DQ31

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

1

CG1391U_0402_6.3V4Z

CG1401U_0402_6.3V4Z

N17E@

2

A4 A2 B4 B2 E4 E2 F4 F2 A11 A13 B11 B13 E11 E13 F11 F13 U11 U13 T11 T13 N11 N13 M11 M13 U4 U2 T4 T2 N4 N2 M4 M2

B1 D1 F1 M1 P1 T1 G2 L2 B3 D3 F3 H3 K3 M3 P3 T3 E5 N5 E10 N10 B12 D12 F12 H12 K12 M12 P12 T12 G13 L13 B14 D14 F14 M14 P14 T14

A1 C1 E1 N1 R1 U1 H2 K2 A3 C3 E3 N3 R3 U3 C4 R4 F5 M5 F10 M10 C11 R11 A12 C12 E12 N12 R12 U12 H13 K13 A14 C14 E14 N14 R14 U14

1

CG1411U_0402_6.3V4Z

N17E@

2

VDD/VDDQ

FBB_D24 <48> FBB_D25 <48> FBB_D26 <48> FBB_D27 <48> FBB_D28 <48> FBB_D29 <48> FBB_D30 <48> FBB_D31 <48> FBB_D16 <48> FBB_D17 <48> FBB_D18 <48> FBB_D19 <48> FBB_D20 <48> FBB_D21 <48> FBB_D22 <48> FBB_D23 <48> FBB_D8 <48> FBB_D9 <48> FBB_D10 <48> FBB_D11 <48> FBB_D12 <48> FBB_D13 <48> FBB_D14 <48> FBB_D15 <48> FBB_D0 <48> FBB_D1 <48> FBB_D2 <48> FBB_D3 <48> FBB_D4 <48> FBB_D5 <48> FBB_D6 <48> FBB_D7 <48>

+1.35VS_VGA

1

CG34510U_0402_6.3V4Z

CG34422U_0603_6.3V6M

N17E@

2

+1.35VS_VGA

1

CG3551U_0402_6.3V4Z

CG3541U_0402_6.3V4Z

N17E@

2

22uF 10uF 1uF

3

FBB_EDC4<48> FBB_EDC5<48> FBB_EDC6<48> FBB_EDC7<48>

FBB_DBI4<48> FBB_DBI5<48> FBB_DBI6<48>

40.2_0402_1%

12

RG114

N17E@

RG116 1K_0402_1%N17E@ RG118 1K_0402_1%N17E@ RG120 121_0402_1%N17E@

1

CG3521U_0402_6.3V4Z

CG3531U_0402_6.3V4Z

N17E@

2

1

CG3621U_0402_6.3V4Z

CG3631U_0402_6.3V4Z

N17E@

2

Issued Date

FBB_DBI7<48>

FBB_CMD17<48>

FBB_CMD29<48> FBB_CMD27<48> FBB_CMD28<48> FBB_CMD30<48>

FBB_CMD25<48> FBB_CMD20<48> FBB_CMD21<48> FBB_CMD24<48> FBB_CMD22<48>

12 12 12

FBB_CMD23<48> FBB_CMD19<48> FBB_CMD31<48> FBB_CMD16<48> FBB_CMD26<48>

FBB_WCK45#<48> FBB_WCK45<48>

FBB_WCK67#<48> FBB_WCK67<48>

+FBB_VREFC

FBB_CMD18<48>

+1.35VS_VGA

2015/09/18 2016/09/18

FBB_CLK1<48> FBB_CLK1#<48>

1

CG34710U_0402_6.3V4Z

CG3481U_0402_6.3V4Z

CG34610U_0402_6.3V4Z

N17E@

2

1

2

1

CG3581U_0402_6.3V4Z

CG3571U_0402_6.3V4Z

CG3561U_0402_6.3V4Z

N17E@

2

3610

12

40.2_0402_1%

12

RG526

N17E@

0.01U_0402_16V7K CG316

1

2

1

CG3511U_0402_6.3V4Z

CG3491U_0402_6.3V4Z

CG3501U_0402_6.3V4Z

N17E@

2

1

CG3611U_0402_6.3V4Z

CG3601U_0402_6.3V4Z

CG3591U_0402_6.3V4Z

N17E@

2

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C13 R13

D13 P13

H11 K10 K11 H10

G12

A10 U10

B10 D10 G10

P10

H14 K14

C10 R10 D11 G11

P11 G14

Compal Secret Data

2

UG4

MF=0 MF=1 MF=0MF=1

C2

EDC0 EDC3 EDC1 EDC2 EDC2 EDC1

R2

EDC3 EDC0

D2

DBI0# DBI3# DBI1# DBI2# DBI2# DBI1#

P2

DBI3# DBI0#

J12

CK

J11

CK#

J3

CKE#

BA0/A2 BA2/A4 BA1/A5 BA3/A3 BA2/A4 BA0/A2 BA3/A3 BA1/A5

K4

A8/A7 A10/A0

H5

A9/A1 A11/A6

H4

A10/A0 A8/A7

K5

A11/A6 A9/A1

J5

A12/RFU/NC

A5

VPP/NC

U5

VPP/NC

J1

MF

J10

SEN

J13

ZQ

J4

ABI#

G3

RAS# CAS# CS# WE#

L3

CAS# RAS#

L12

WE# CS#

D5

WCK01# WCK23#

D4

WCK01 WCK23

P5

WCK23# WCK01#

P4

WCK23 WCK01

VREFD VREFD

J14

VREFC

J2

RESET#

H1

VSS

K1

VSS

B5

VSS

G5

VSS

L5

VSS

T5

VSS VSS VSS VSS

L10

VSS VSS

T10

VSS VSS VSS

G1

VDD

L1

VDD

G4

VDD

L4

VDD

C5

VDD

R5

VDD VDD VDD VDD VDD

L11

VDD VDD VDD

L14

VDD

170-BALL

SGRAM GDDR5

H5GQ1H24AFR-T2L_BGA170

@

Deciphered Date

DQ24 DQ0 DQ25 DQ1 DQ26 DQ2 DQ27 DQ3 DQ28 DQ4 DQ29 DQ5 DQ30 DQ6 DQ31 DQ7 DQ16 DQ8 DQ17 DQ9

DQ18 DQ10 DQ19 DQ11 DQ20 DQ12 DQ21 DQ13 DQ22 DQ14 DQ23 DQ15 DQ8 DQ16 DQ9 DQ17 DQ10 DQ18 DQ11 DQ19 DQ12 DQ20 DQ13 DQ21 DQ14 DQ22 DQ15 DQ23 DQ0 DQ24 DQ1 DQ25 DQ2 DQ26 DQ3 DQ27 DQ4 DQ28 DQ5 DQ29 DQ6 DQ30 DQ7 DQ31

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

A4 A2 B4 B2 E4 E2 F4 F2 A11 A13 B11 B13 E11 E13 F11 F13 U11 U13 T11 T13 N11 N13 M11 M13 U4 U2 T4 T2 N4 N2 M4 M2

B1 D1 F1 M1 P1 T1 G2 L2 B3 D3 F3 H3 K3 M3 P3 T3 E5 N5 E10 N10 B12 D12 F12 H12 K12 M12 P12 T12 G13 L13 B14 D14 F14 M14 P14 T14

A1 C1 E1 N1 R1 U1 H2 K2 A3 C3 E3 N3 R3 U3 C4 R4 F5 M5 F10 M10 C11 R11 A12 C12 E12 N12 R12 U12 H13 K13 A14 C14 E14 N14 R14 U14

Title

Size Document Number Rev

Date: Sheet of

Date: Sheet

FBB_D32 <48> FBB_D33 <48> FBB_D34 <48> FBB_D35 <48> FBB_D36 <48> FBB_D37 <48> FBB_D38 <48> FBB_D39 <48> FBB_D40 <48> FBB_D41 <48> FBB_D42 <48> FBB_D43 <48> FBB_D44 <48> FBB_D45 <48> FBB_D46 <48> FBB_D47 <48> FBB_D48 <48> FBB_D49 <48> FBB_D50 <48> FBB_D51 <48> FBB_D52 <48> FBB_D53 <48> FBB_D54 <48> FBB_D55 <48> FBB_D56 <48> FBB_D57 <48> FBB_D58 <48> FBB_D59 <48> FBB_D60 <48> FBB_D61 <48> FBB_D62 <48> FBB_D63 <48>

+1.35VS_VGA+1.35VS_VGA

Compal Electronics, Inc.

GDDR5_B

LA-E992P

1

53 77Tuesday, July 25, 2017

1.0(A00)

of

5

4

3

2

1

UG5

FBC_EDC3<48> FBC_EDC2<48> FBC_EDC1<48>

40.2_0402_1% RG124

N17E@

+1.35VS_VGA

RG126 1K_0402_1%N17E@ RG128 1K_0402_1%N17E@ RG130 121_0402_1%N17E@

1

CG4351U_0402_6.3V4Z

N17E@

2

+FBC_VREFC

1

CG148

2

1.33K_0402_1% 820P_0402_25V7

N17E@

1

CG1591U_0402_6.3V4Z

CG1581U_0402_6.3V4Z

N17E@

2

FBC_EDC0<48>

FBC_DBI3<48> FBC_DBI2<48> FBC_DBI1<48> FBC_DBI0<48>

FBC_CMD1<48>

FBC_CMD12<48> FBC_CMD14<48> FBC_CMD13<48> FBC_CMD11<48>

FBC_CMD5<48> FBC_CMD8<48> FBC_CMD9<48> FBC_CMD4<48> FBC_CMD6<48>

FBC_CMD7<48> FBC_CMD0<48> FBC_CMD10<48> FBC_CMD3<48> FBC_CMD15<48>

FBC_WCK23#<48> FBC_WCK23<48>

FBC_WCK01#<48> FBC_WCK01<48>

FBC_CMD2<48>

W=16mils

1

CG149

2

820P_0402_25V7

N17E@

1

CG1611U_0402_6.3V4Z

CG1601U_0402_6.3V4Z

N17E@

2

12 12 12

+FBC_VREFC

+1.35VS_VGA

1

N17E@

2

D D

FBC_CLK0<48> FBC_CLK0#<48>

+1.35VS_VGA

C C

1

CG42222U_0603_6.3V6M

CG42022U_0603_6.3V6M

CG42310U_0402_6.3V4Z

CG42122U_0603_6.3V6M

N17E@

2

B B

MEM_VREF<46,52,53>

MEM_VREF levels

70% of rail 50% of rail

A A

GDDR5_C

1

CG42510U_0402_6.3V4Z

CG42410U_0402_6.3V4Z

N17E@

2

Termination Enable

Termination Disable

1

CG4281U_0402_6.3V4Z

CG4291U_0402_6.3V4Z

N17E@

2

1

D

2

QG4 MESS138W-G_SOT323-3

G

N17E@

S

3

Under VRAM

1

CG15122U_0603_6.3V6M

CG15222U_0603_6.3V6M

N17E@

2

1

CG4301U_0402_6.3V4Z

N17E@

2

1 2

N17E@

RG133 931_0402_1%

1

CG15310U_0402_6.3V4Z

N17E@

2

CG4261U_0402_6.3V4Z

CG4271U_0402_6.3V4Z

N17E@

2

+1.35VS_VGA +1.35VS_VGA

1

CG15022U_0603_6.3V6M

2

5

40.2_0402_1%

12

RG527

N17E@

0.01U_0402_16V7K CG317

N17E@

1

2

1

CG4341U_0402_6.3V4Z

CG4321U_0402_6.3V4Z

CG4331U_0402_6.3V4Z

CG4311U_0402_6.3V4Z

N17E@

2

1

CG15410U_0402_6.3V4Z

N17E@

2

1

CG15510U_0402_6.3V4Z

N17E@

2

+1.35VS_VGA

12

1

CG1561U_0402_6.3V4Z

N17E@

2

RG132 549_0402_1%

N17E@

RG134

N17E@

1

CG1571U_0402_6.3V4Z

N17E@

2

C2

EDC0 EDC3

C13

EDC1 EDC2

R13

EDC2 EDC1

R2

EDC3 EDC0

D2

DBI0# DBI3#

D13

DBI1# DBI2#

P13

DBI2# DBI1#

P2

DBI3# DBI0#

J12

CK

J11

CK#

J3

CKE#

H11

BA0/A2 BA2/A4

K10

BA1/A5 BA3/A3

K11

BA2/A4 BA0/A2

H10

BA3/A3 BA1/A5

K4

A8/A7 A10/A0

H5

A9/A1 A11/A6

H4

A10/A0 A8/A7

K5

A11/A6 A9/A1

J5

A12/RFU/NC

A5

VPP/NC

U5

VPP/NC

J1

MF

J10

SEN

J13

ZQ

J4

ABI#

G3

RAS# CAS#

G12

CS# WE#

L3

CAS# RAS#

L12

WE# CS#

D5

WCK01# WCK23#

D4

WCK01 WCK23

P5

WCK23# WCK01#

P4

WCK23 WCK01

A10

VREFD

U10

VREFD

J14

VREFC

J2

RESET#

H1

VSS

K1

VSS

B5

VSS

G5

VSS

L5

VSS

T5

VSS

B10

VSS

D10

VSS

G10

VSS

L10

VSS

P10

VSS

T10

VSS

H14

VSS

K14

VSS

G1

VDD

L1

VDD

G4

VDD

L4

VDD

C5

VDD

R5

VDD

C10

VDD

R10

VDD

D11

VDD

G11

VDD

L11

VDD

P11

VDD

G14

VDD

L14

VDD

170-BALL

SGRAM GDDR5

H5GQ1H24AFR-T2L_BGA170

@

1

CG16722U_0603_6.3V6M

N17E@

2

4

MF=1 MF=0

MF=0 MF=1 MF=0MF=1

1

CG16822U_0603_6.3V6M

2

1

CG16922U_0603_6.3V6M

N17E@

2

1

CG17110U_0402_6.3V4Z

CG17010U_0402_6.3V4Z

CG17210U_0402_6.3V4Z

CG1731U_0402_6.3V4Z

N17E@

2

DQ24 DQ0 DQ25 DQ1 DQ26 DQ2 DQ27 DQ3 DQ28 DQ4 DQ29 DQ5 DQ30 DQ6 DQ31 DQ7 DQ16 DQ8 DQ17 DQ9 DQ18 DQ10 DQ19 DQ11 DQ20 DQ12 DQ21 DQ13 DQ22 DQ14 DQ23 DQ15 DQ8 DQ16 DQ9 DQ17 DQ10 DQ18 DQ11 DQ19 DQ12 DQ20 DQ13 DQ21 DQ14 DQ22 DQ15 DQ23 DQ0 DQ24 DQ1 DQ25 DQ2 DQ26 DQ3 DQ27 DQ4 DQ28 DQ5 DQ29 DQ6 DQ30 DQ7 DQ31

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

1

CG1741U_0402_6.3V4Z

CG1751U_0402_6.3V4Z

N17E@

2

A4 A2 B4 B2 E4 E2 F4 F2 A11 A13 B11 B13 E11 E13 F11 F13 U11 U13 T11 T13 N11 N13 M11 M13 U4 U2 T4 T2 N4 N2 M4 M2

B1 D1 F1 M1 P1 T1 G2 L2 B3 D3 F3 H3 K3 M3 P3 T3 E5 N5 E10 N10 B12 D12 F12 H12 K12 M12 P12 T12 G13 L13 B14 D14 F14 M14 P14 T14

A1 C1 E1 N1 R1 U1 H2 K2 A3 C3 E3 N3 R3 U3 C4 R4 F5 M5 F10 M10 C11 R11 A12 C12 E12 N12 R12 U12 H13 K13 A14 C14 E14 N14 R14 U14

1

CG1761U_0402_6.3V4Z

N17E@

2

VDD/VDDQ

FBC_D24 <48> FBC_D25 <48> FBC_D26 <48> FBC_D27 <48> FBC_D28 <48> FBC_D29 <48> FBC_D30 <48> FBC_D31 <48> FBC_D16 <48> FBC_D17 <48> FBC_D18 <48> FBC_D19 <48> FBC_D20 <48> FBC_D21 <48> FBC_D22 <48> FBC_D23 <48> FBC_D8 <48> FBC_D9 <48> FBC_D10 <48> FBC_D11 <48> FBC_D12 <48> FBC_D13 <48> FBC_D14 <48> FBC_D15 <48> FBC_D0 <48> FBC_D1 <48> FBC_D2 <48> FBC_D3 <48> FBC_D4 <48> FBC_D5 <48> FBC_D6 <48> FBC_D7 <48>

+1.35VS_VGA

1

CG36422U_0603_6.3V6M

CG36510U_0402_6.3V4Z

N17E@

2

+1.35VS_VGA

1

CG3751U_0402_6.3V4Z

CG3741U_0402_6.3V4Z

N17E@

2

22uF 10uF 1uF

3

FBC_EDC4<48> FBC_EDC5<48> FBC_EDC6<48> FBC_EDC7<48>

FBC_DBI4<48> FBC_DBI5<48> FBC_DBI6<48>

40.2_0402_1%

12

RG125

N17E@

RG127 1K_0402_1%N17E@ RG129 1K_0402_1%N17E@ RG131 121_0402_1%N17E@

1

CG3721U_0402_6.3V4Z

CG3731U_0402_6.3V4Z

N17E@

2

1

CG3821U_0402_6.3V4Z

CG3831U_0402_6.3V4Z

N17E@

2

Issued Date

FBC_DBI7<48>

FBC_CMD17<48>

FBC_CMD29<48> FBC_CMD27<48> FBC_CMD28<48> FBC_CMD30<48>

FBC_CMD25<48> FBC_CMD20<48> FBC_CMD21<48> FBC_CMD24<48> FBC_CMD22<48>

12 12 12

FBC_CMD23<48> FBC_CMD19<48> FBC_CMD31<48> FBC_CMD16<48> FBC_CMD26<48>

FBC_WCK45#<48> FBC_WCK45<48>

FBC_WCK67#<48> FBC_WCK67<48>

+FBC_VREFC

FBC_CMD18<48>

+1.35VS_VGA

2015/09/18 2016/09/18

FBC_CLK1<48> FBC_CLK1#<48>

1

2

1

2

1

CG36710U_0402_6.3V4Z

CG3681U_0402_6.3V4Z

CG36610U_0402_6.3V4Z

N17E@

2

1

CG3761U_0402_6.3V4Z

CG3781U_0402_6.3V4Z

CG3771U_0402_6.3V4Z

N17E@

2

3610

12

40.2_0402_1%

12

RG528

N17E@

0.01U_0402_16V7K CG318

1

2

1

CG3701U_0402_6.3V4Z

CG3711U_0402_6.3V4Z

CG3691U_0402_6.3V4Z

N17E@

2

1

CG3791U_0402_6.3V4Z

CG3801U_0402_6.3V4Z

CG3811U_0402_6.3V4Z

N17E@

2

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

UG6

C2

EDC0 EDC3

C13

EDC1 EDC2

R13

EDC2 EDC1

R2

EDC3 EDC0

D2

DBI0# DBI3#

D13

DBI1# DBI2#

P13

DBI2# DBI1#

P2

DBI3# DBI0#

J12

CK

J11

CK#

J3

CKE#

H11

BA0/A2 BA2/A4

K10

BA1/A5 BA3/A3

K11

BA2/A4 BA0/A2

H10

BA3/A3 BA1/A5

K4

A8/A7 A10/A0

H5

A9/A1 A11/A6

H4

A10/A0 A8/A7

K5

A11/A6 A9/A1

J5

A12/RFU/NC

A5

VPP/NC

U5

VPP/NC

J1

MF

J10

SEN

J13

ZQ

J4

ABI#

G3

RAS# CAS#

G12

CS# WE#

L3

CAS# RAS#

L12

WE# CS#

D5

WCK01# WCK23#

D4

WCK01 WCK23

P5

WCK23# WCK01#

P4

WCK23 WCK01

A10

VREFD

U10

VREFD

J14

VREFC

J2

RESET#

H1

VSS

K1

VSS

B5

VSS

G5

VSS

L5

VSS

T5

VSS

B10

VSS

D10

VSS

G10

VSS

L10

VSS

P10

VSS

T10

VSS

H14

VSS

K14

VSS

G1

VDD

L1

VDD

G4

VDD

L4

VDD

C5

VDD

R5

VDD

C10

VDD

R10

VDD

D11

VDD

G11

VDD

L11

VDD

P11

VDD

G14

VDD

L14

VDD

SGRAM GDDR5

H5GQ1H24AFR-T2L_BGA170

@

Compal Secret Data

Deciphered Date

2

MF=0 MF=1 MF=0MF=1

170-BALL

DQ24 DQ0 DQ25 DQ1 DQ26 DQ2 DQ27 DQ3 DQ28 DQ4 DQ29 DQ5 DQ30 DQ6 DQ31 DQ7 DQ16 DQ8 DQ17 DQ9

DQ18 DQ10 DQ19 DQ11 DQ20 DQ12 DQ21 DQ13 DQ22 DQ14 DQ23 DQ15 DQ8 DQ16 DQ9 DQ17 DQ10 DQ18 DQ11 DQ19 DQ12 DQ20 DQ13 DQ21 DQ14 DQ22 DQ15 DQ23 DQ0 DQ24 DQ1 DQ25 DQ2 DQ26 DQ3 DQ27 DQ4 DQ28 DQ5 DQ29 DQ6 DQ30 DQ7 DQ31

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

A4 A2 B4 B2 E4 E2 F4 F2 A11 A13 B11 B13 E11 E13 F11 F13 U11 U13 T11 T13 N11 N13 M11 M13 U4 U2 T4 T2 N4 N2 M4 M2

B1 D1 F1 M1 P1 T1 G2 L2 B3 D3 F3 H3 K3 M3 P3 T3 E5 N5 E10 N10 B12 D12 F12 H12 K12 M12 P12 T12 G13 L13 B14 D14 F14 M14 P14 T14

A1 C1 E1 N1 R1 U1 H2 K2 A3 C3 E3 N3 R3 U3 C4 R4 F5 M5 F10 M10 C11 R11 A12 C12 E12 N12 R12 U12 H13 K13 A14 C14 E14 N14 R14 U14

Title

Size Document Number Rev

Date: Sheet of

Date: Sheet

FBC_D32 <48> FBC_D33 <48> FBC_D34 <48> FBC_D35 <48> FBC_D36 <48> FBC_D37 <48> FBC_D38 <48> FBC_D39 <48> FBC_D40 <48> FBC_D41 <48> FBC_D42 <48> FBC_D43 <48> FBC_D44 <48> FBC_D45 <48> FBC_D46 <48> FBC_D47 <48> FBC_D48 <48> FBC_D49 <48> FBC_D50 <48> FBC_D51 <48> FBC_D52 <48> FBC_D53 <48> FBC_D54 <48> FBC_D55 <48> FBC_D56 <48> FBC_D57 <48> FBC_D58 <48> FBC_D59 <48> FBC_D60 <48> FBC_D61 <48> FBC_D62 <48> FBC_D63 <48>

+1.35VS_VGA+1.35VS_VGA

Compal Electronics, Inc.

GDDR5_C

LA-E992P

1

54 77Tuesday, July 25, 2017

1.0(A00)

of

A

B

C

D

E

F

G

H

1V8_MAIN_EN

3V3_SYS_EN1V8_MAIN_EN

+1V8_AON

+1V8_MAIN

12

RG71 10K_0402_5%

N17E@

1

2

12

@N17E@

RG515 10K_0402_5%

12

CG240

0.01U_0402_16V

N17E@

+1V8_AON / +1V8_MAIN

+1.8V_PRIM

+5VS

22U_0603_6.3V6M

0.1U_0402_10V7K

CG487

0.1U_0402_10V7K

CG288

CG386

1

12

N17E@

2

@N17E@

1

CG322 1U_0402_6.3V6K

N17E@

2

+5VALW

0.1U_0402_10V7K

Enable 1.2V Disable 0.5V

UG12

14

1

VOUT1

VIN1

13

2

VOUT1

VIN1

3

ON1

4

VBIAS

5

ON2

+1V8_AON

6

VIN2

7

VIN2

10U_0603_6.3V6M

CG289

1

AOZ1331_SON14_2X3

N17E@

2

SA00006U300

+3V3_SYS

+3VS

Enable 1.2V Disable 0.5V

UG14

1

VIN1

2

VIN2

7

VIN thermal

3

VBIAS

4

ON

1

TPS22961DNYR_WSON8

CG384

N17E@

2

N17E@

SA00007XR00

1 2

12

CT1

CG64

11

220P_0402_50V8J

GND

10

1 2

CT2

CG65

9

220P_0402_50V8J

VOUT2

8

VOUT2

15

GPAD

6

VOUT

5

GND

+1V8_AON

1

N17E@

CG320 10U_0603_6.3V6M

2

+1V8_MAIN

1

N17E@

CG290 10U_0603_6.3V6M

2

+3V3_SYS

10U_0402_6.3V6M

1U_0402_6.3V6K~D

CG385

CG323

1

2

N17E@

GPU Power Down Sequence

Optimus Sequence

1V8_AON_ON

CG439

0.1U_0201_6.3V6K

N17E@

CG527

0.1U_0201_6.3V6K

N17E@

+1.8V_PRIM

N17E@

RG545 68K_0402_1%

1 2

PEX_VDD_EN <66>

DVT1.0 Add UG31/CG527=0.1uF

12

@N17E@

RG70 10K_0402_5%

+3VS

1

CG438

0.1U_0201_6.3V6K

N17E@

2

N17E@

RG551 0_0201_5%

1 2

NVVDD1_EN

N17E@

AZ5125-01HPR7G_SOD523-2

RB751S40T1G_SOD523-2

DG7

12

N17E@

RG549

100K_0402_5%

1 2

N17E@

DG10

1 2

RB751S40T1G_SOD523-2

AZ5125-01HPR7G_SOD523-2

N17E@

1 2

RG550 39K_0402_1%

DGPU_PWR_EN<20>

12

CG442 2200P_0402_25V7K

N17E@

1

CG482

0.047U_0402_16V4Z

N17E@

2

NVVDD1_PGOOD <46,67>

1 1

0_0402_5%

RG553 0_0201_5%

1 2

N17E@

61

12

RG584

@N17E@

Vgs(th):0.8V~1.5V

DMN63D8LDW-7 2N SOT363-6

DGPU_PEX_RST#<46>

2

+1V8_AON

53

1

VCC

B

2

A

G

+1V8_MAIN

12

RG546 10K_0402_5%

N17E@

5

34

QG23B

N17E@

SB000013K00

+1V8_AON

12

RG516 10K_0201_5%

N17E@

61

QG502A DMN53D0LDW-7 2N SOT363-6

N17E@

1

CG440

0.1U_0201_6.3V6K

N17E@

2

4

Y

UG27 74LVC1G32GW_TSSOP5

N17E@

DGPU_PEX_RST#

12

N17E@

RG557 10K_0402_5%

RG580 0_0402_5%

@N17E@

CMP_VOUT0 <36,61>

+1V8_AON

5

1

VCC

IN B

OUT Y

2

IN A

GND

3

1 2

1

CG246

0.1U_0201_6.3V6K

N17E@

2

RG554 0_0201_5%

4

1 2

N17E@

UG22 NL17SZ08DFT2G_SC70-5

N17E@

Need check

FBVDD/Q_EN <69>

1V8_MAIN_EN<46>

+3VS

12

RG505 10K_0201_5%

N17E@

1 2

DVT1.0 Change DG3 to SC100000S00

Pilot Change DG3 footprint to AZ5125-01HPR7G_SOD523-2

3

5

N17E@

QG502B

4

DMN53D0LDW-7 2N SOT363-6

DG3 RB751S40T1G_SOD523-2

AZ5125-01HPR7G_SOD523-2

N17E@

+3VS

12

RG506 10K_0201_5%

N17E@

Pilot Change DG7 footprint to AZ5125-01HPR7G_SOD523-2

DVT1.0 Change DG7 to SC100000S00

DVT1.0 Change RG549 to 100K ohm Change CG442 to 2200pF

DVT1.0 Add DG10/CG482=0.047uF/RG550=39K ohm

Pilot Change DG10 footprint to AZ5125-01HPR7G_SOD523-2

N17E@

AZ5125-01HPR7G_SOD523-2

RB751S40T1G_SOD523-2

DG4

12

DVT1.0 Change DG4 to SC100000S00

Pilot Change DG4 footprint to AZ5125-01HPR7G_SOD523-2

DGPU_PEX_RST#

DVT2.0 Reserve RG584(@) connect to DGPU_PEX_RST#.

0_0402_5% RG576

OVERT#<46>

1 2

N17E@

DMN63D8LDW-7 2N SOT363-6

2

QG23A

N17E@

SB000013K00

DVT1.0 Rename UG23 to QG23

2 2

GPU_GC6_FB_EN<46>

3 3

GPU_GC6_FB_EN

+1.0VS_VGA_PGOOD<66>

NVVDD1_EN <67>

DGPU_PWROK<18,46,69>

GPU_PWR_EN

53

1

VCC

B

4

Y

2

A

G

UG25 74LVC1G32GW_TSSOP5

N17E@

+1V8_AON

1

2

5

1

VCC

IN B

4

1V8_MAIN_EN

PEX_VDD_EN_U

OUT Y

2

IN A

GND

UG26 NL17SZ08DFT2G_SC70-5

3

N17E@

SA00003R000

+1V8_AON

1

2

5

1

VCC

IN B

4

OUT Y

2

IN A

GND

UG31 NL17SZ08DFT2G_SC70-5

3

N17E@

SA00003R000

GPU Power Up Sequence

GPU GC6 Entry/Exit Sequence

Discharge

+PEX_VDD

DVT1.0 Change

+5VALW

12

RG543 10K_0402_5%

SB000018X00

QG509A

N17E@

61

2

4 4

DMN53D0LDW-7 2N SOT363-6

12

RG544 10_0402_1%

N17E@

3

QG509B

5

DMN53D0LDW-7 2N SOT363-6

N17E@

SB000018X00

4

RG544 to 10 ohm

DVT1.0 Remove RG581/QG512

DVT1.0 Change QG509.pin2 connect to PEX_VDD_EN

A

+5VALW

1V8_AON_ON 1V8_MAIN_EN 3V3_SYS_ENPEX_VDD_EN

2

B

+1V8_AON

12

RG509

N17E@

3

10K_0402_5%

5

4

61

N17E@

QG503A

SB000018X00

DMN53D0LDW-7_SOT363-6

DVT1.0 Change RG510/RG512 to 10 ohm

RG510

N17E@

10_0402_1%

N17E@

QG503B

SB000018X00

DMN53D0LDW-7_SOT363-6

+5VALW

12

RG511

N17E@

10K_0402_5%

61

2

QG504A

N17E@

DMN53D0LDW-7_SOT363-6

C

+1V8_MAIN

12

RG512

N17E@

10_0402_1%

3

5

QG504B

N17E@

SB000018X00

4

DMN53D0LDW-7_SOT363-6

SB000018X00

+3V3_SYS

12

+5VALW

2

RG514

N17E@

12

61

51_0402_5%

RG513

N17E@

3

10K_0402_5%

5

N17E@

QG505B

SB000018X00

4

DMN53D0LDW-7_SOT363-6

N17E@

QG505A

DMN53D0LDW-7_SOT363-6

FBVDD/Q_EN

SB000018X00

D

+1.35VS_VGA

12

+5VALW

2

RG582

51_0402_5%

12

61

@N17E@

RG583

3

10K_0402_5%

@N17E@

5

QG513B

@N17E@

SB000018X00

4

DMN53D0LDW-7_SOT363-6

QG513A

@N17E@

SB000018X00

DMN53D0LDW-7_SOT363-6

E

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETA RY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTA INS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETA RY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTA INS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS , INC. NEITHER THIS SHEET NOR THE INFO RMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS , INC. NEITHER THIS SHEET NOR THE INFO RMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS , INC. NEITHER THIS SHEET NOR THE INFO RMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC .

F

Compal Secret Data

2015/09/18 2016/09/18

Deciphered Date

G

Compal Electronics, Inc.

Title

GPU power control

Size Document Number Rev

Date: Sheet of

Date: Sheet

LA-E992P

H

of

55 77Tuesday, July 25, 2017

1.0(A00)

5

MODEL NAME :

PCB NO :

ZZZ PCB@

PCB CKA50 LA-E992P LS-E992P/E993P 02

DAZ21J00310

D D

LA-E992P

CKF50/CKA50

Bom Structure

GPUCPU PCH

UH1

I7_QLM5@

R1

KBL-H_QLM5

SA0000AD70L

UH1

I5_QLM7@

R1

KBL-H_QLM7

SA0000AD80L

UH1

I7_MP@

UH2

QLF9@

PCH_QLF9

SA0000ADB0L

UH2

SR30W@

PCH_SR30W

SA0000ADB2L

UG9

N17E_G1@

N17E-G1-A1

SA00009PM1L

4

UG1

K4G80325FB-HC25

S6G@

SA00009TA1L

UG3

K4G80325FB-HC25

S6G@

SA00009TA1L

UG5

K4G80325FB-HC25

S6G@

SA00009TA1L

3

X7673331L07 : S6G@ X7673331L09 : M6G@

UG2

K4G80325FB-HC25

S6G@

SA00009TA1L

UG4

K4G80325FB-HC25

S6G@

SA00009TA1L

UG6

K4G80325FB-HC25

S6G@

SA00009TA1L

RG90

100K_0402_1%

S6G@

SD034100380

RG91

100K_0402_1%

S6G@

SD034100380

RG92

100K_0402_1%

S6G@

SD034100380

Micron 6GSamsung 6G

UG1

MT51J256M32HF-80:A

M6G@

SA00009TI1L

UG3

MT51J256M32HF-80:A

M6G@

SA00009TI1L

UG5

MT51J256M32HF-80:A

M6G@

SA00009TI1L

UG2

MT51J256M32HF-80:A

M6G@

SA00009TI1L

UG4

MT51J256M32HF-80:A

M6G@

SA00009TI1L

UG6

MT51J256M32HF-80:A

M6G@

SA00009TI1L

2

RG78

100K_0402_1%

M6G@

SD034100380

RG91

100K_0402_1%

M6G@

SD034100380

RG92

100K_0402_1%

M6G@

SD034100380

Hynix 6G

UG1

H5GQ8H24MJR-R4C

H6G@

SA00009TM1L

UG3

H5GQ8H24MJR-R4C

H6G@

SA00009TM1L

UG5

H5GQ8H24MJR-R4C

H6G@

SA00009TM1L

1

X7673331L08 : H6G@

UG2

H5GQ8H24MJR-R4C

H6G@

SA00009TM1L

UG4

H5GQ8H24MJR-R4C

H6G@

SA00009TM1L

UG6

H5GQ8H24MJR-R4C

H6G@

SA00009TM1L

RG90

100K_0402_1%

H6G@

SD034100380

RG79

100K_0402_1%

H6G@

SD034100380

RG92

100K_0402_1%

H6G@

SD034100380

R3

KBL-H_SR32Q

SA0000AD72L

UH1

C C

I5_MP@

R3

KBL-H_SR32S

SA0000AD82L

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/04/10 2014/05/01

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

NOTE

LA-E992P

1

56 77Tuesday, July 25, 2017

1.0(A00)

of

PJPDC1

@

11

10

9

8

7

6

5

4

3

2

1

1 1

1

ACES_51202-00901-001

BATT+

PL4

EMI@

HCB2012KF-121T50_0805

1 2

BATT+

PL5

EMI@

HCB2012KF-121T50_0805

1 2

12

PC6

PC5

2 2

EMI@

0.022U_0402_25V7K

0.01UF_0402_25V7K

A

ADPIN

PSID

L30ESD24VC3-2_SOT23-3

BATT++

12

PC7

EMI@

1000P_0402_50V7K

PL1

@EMI@

HCB2012KF-121T50_2P

1 2

PL2

@EMI@

HCB2012KF-121T50_2P

1 2

PL6

@EMI@

12

PC1

PC2

PC17

EMI@

100P_0402_50V8J

1000P_0402_50V7K

PC8

EMI@

100P_0402_50V8J

2

PD1

@

1

PD3 TVNST52302AB0_SOT523-3

ESD@

2

3

@EMI@

3

12

1000P_0402_50V7K

HCB2012KF-121T50_2P

1 2

EMI@

PC18

HCB2012KF-121T50_2P

1 2

EMI@

100P_0402_50V8J

HCB2012KF-121T50_2P

@EMI@

1 2 EMI@

HCB2012KF-121T50_2P

1 2

EMI@

BLM15HG601SN1D_2P

PL7

PL8

PL9

PL3

12

1

PD4 TVNST52302AB0_SOT523-3

ESD@

2

3

12

Adapter connector:

1.PSID

2.GND

3.GND

4.GND

5.GND

6.ADPIN

7.ADPIN

8.ADPIN

9.ADPIN

10.X

11.X

B

VIN

12

PC3

EMI@

1000P_0402_50V7K

12

PC19

PC4

EMI@

100P_0402_50V8J

PC20

100P_0402_50V8J

1000P_0402_50V7K

@EMI@

PSID-0

PR3

1 2

100K_0402_1%

PR5

15K_0402_1%

1 2

PSID-1

1 3

D

S

PSID-3

PQ1 FDV301N_G 1N SOT23-3

G

2

C

2

PQ2

B

S TR METR3904W-G NPN SOT323-3

E

3 1

PR1

33_0402_5%

1 2

PR4

10K_0402_1%

+3VALW

C

battery unplug prochot

D

H_PROCHOT#<9,36,60,71>

PR2

2.2K_0402_5%

1 2

12

+5VALW

PS_ID <36>

PC12

0.1U_0402_25V6

PQ5_GPBAT_PRES#

1 2

PR21

13

D

2

PQ5 L2N7002WT1G 1N SC-70-3

G

S

1 2

100K_0402_1%

PBATT1@

1

2

3

3 4 5 6 7 8

GND GND

ACES_50458-01001-P01

Battery connector:

1.BATT++

2.BATT++

3 3

3.BATT++

4.CLK_SMB

5.DAT_SMB

6.BATT_PRS

7.SYS_PRES

8.GND

9.GND

10.GND

ACIN=ACOK

VIN

4 4

4 5 6 7 8

9 10

CLK_SMB DAT_SMB BATT_PRS SYS_PRES

PR31

1M_0402_1%

1 2

1M_0402_1%

1 2 1 2

PR8 100_0402_1%

1 2

PR10 100_0402_1% PR12 100_0402_1%

adapter unplug prochot adapter OC prochot

PR34

@

PR33

PC16

1 2

100K_0402_1%

1 2

PR35

1 2

0_0402_5%

PR25

@ 1 2

0_0402_5%

1 2

61

2

PQ7A

DMN65D8LDW-7_SOT363-6

2

G

PR23

EC_AC_BAT#<46>

+3VALW

12

34

12

A

5

PR32

10K_0402_5%

0.1U_0402_25V6

1 2

PQ7B

DMN65D8LDW-7_SOT363-6

H_PROCHOT#

PC15

100K_0402_1%

0.1U_0402_25V6

PBAT_PRES#

PR13

10K_0402_1%

1 2

PBAT_CHG_SMBCLK <36,60>

PBAT_CHG_SMBDAT <36,60>

13

D

PQ9

S

L2N7002WT1G 1N SC-70-3

B

PBAT_PRES# <36,60>

+3VALW

Erp lot 6 circuit

ACAV_IN<36,60>

12

PR20

200K_0402_1%

PQ6B_G

PC13

Issued Date

12

0.1U_0402_25V6

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PRO PRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PRO PRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, I NC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, I NC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, I NC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WIT HOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WIT HOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

VIN

PR15

12

3.3K_0402_1%

PR16

1M_0402_1%

1 2

PQ6A_G

34

5

PQ6B

1 2

DMN65D8LDW-7_SOT363-6

2015/09/18 2016/09/18

PQ6A_D

61

2

1M_0402_1% PR22

Compal Secret Data

PQ6A

DMN65D8LDW-7_SOT363-6

Deciphered Date

C

I_ADP_R<36,60>

12

PR27

10K_0402_1%

CMPIN<60>

12

PR26

14.3K_0402_1%

12

H_PROCHOT#

@

1 2

13

D

2

G

S

LA-E992P

D

PR24

0_0402_5%

PQ8

L2N7002WT1G 1N SC-70-3

59 77Tuesday, July 25, 2017

0.3(X02)

of

REGN_CHG

REGN=6V

12

PR28

10K_0402_1%

CMPOUT<60>

PR29

12.4K_0402_1%

PR30

160K_0402_1%

1 2

12

PC14

0.022U_0402_25V7K

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

PWR-DCIN / BATT CONN / OTP

A

PQ700

13

D

PQ701

AON6366E_DFN5X6-8-5

12

1 1

2 2

3 3

PC700

PC701

1000P_0402_50V7K

12

1000P_0402_50V7K

PQ702 AON6366E_DFN5X6-8-5

AC_DIS<36>

4

1 2

PQ701_G

4

1 2

PQ702_G

4.7_0402_5%

1 2 35

PR702

4.7_0402_5%

1 2 35

PR704

ACAV_IN<18,36,59>

L2N7002WT1G 1N SC-70-3

P1VIN

PQ700_G

2

G

PR700

S

3M_0402_5%

12

PC702

0.1U_0402_25V6

B2B_G

12

PR709

4.12K_0603_1%

REGN_CHG

PQ708

L2N7002WT1G 1N SC-70-3

12

PR734 100K_0402_1%

1M_0402_1%

12

AON6366E_DFN5X6-8-5

1 2 3 5

12

PR710

4.12K_0603_1%

1 2

100K_0402_1%

2

G

PR701

PQ703

PR718

13

D

S

12

4

12

P2

PC710

0.1U_0603_25V7K

1 2

PR719

120K_0402_5%

12

PR725

49.9K_0402_1%

0.005_1206_1%

1

2

CSSP_1

PR705

@

1 2

0.1U_0402_25V6

VIN

12

PR720

324K_0402_1%

12

PR703

4

3

CSSN_1

0_0402_5%

PC711

1 2

CSSP_2

CSSN_2

I_ADP_R<36,59>

AC Det Max:18.16V Typ :17.98V Min :17.8V

PC724

0.01UF_0402_25V7K

1 2

PR706

0_0402_5%

@

1 2

PC712

0.01UF_0402_25V7K

@

0_0402_5%

B

ADP_I = 40*Iadapter*Rsense

VCC_CHG<42>

PD700

VIN

IADP_CHG

PC723

1 2

PC725 100P_0402_50V8J

3

2

BAT54CW_SOT323-3

1 2

PC715

1U_0603_25V6K

PU700

29

PWPD

1

ACN

2

ACP

3

CMSRC

4

ACDRV

5

ACOK

6

ACDET

7

IADP

100P_0402_50V8J

I_BATT_CHG

PR727

@

1 2

I_BATT_R

1

12

PR711

10_1206_1%

VCC_CHG_1

28

8

PR728

0_0402_5%

@

1 2

BATT++

CMSRC_CHG

ACDRV_CHG

ACDET_CHG

PR721

BST_CHG

PC713

1 2

0.047U_0402_25V7K

UG_CHG

LX_CHG

26

27

VCC

HIDRV

PHASE

BQ24780SRUYR_QFN28_4X4

IDCHG

PROCHOT#

PMON

9

10

PMON_CHG

PROCHOT_CHG

PR7290_0402_5%

0_0402_5%

1 2

@

<36>

P_SYS

H_PROCHOT#

C

D

CC =

CV =

12

SNUB_CHG

12

AON7380_DFN3X3-8-5

0.1U_0402_25V6

PQ704 AON7506_DFN33-8-5

PL701

1 2

PR717

4.7_1206_5%

@EMI@

PC719 680P_0402_50V7K

@EMI@

PC720

1 2

1 2 35

4

PQ704_G

PC703

1 2

0.01U_0603_25V7K

12

PR707

4.02K_0402_1%

BATDRV_CHG

PR716

0.01_1206_1%

1

2

CSOP_1

PC721

0.1U_0402_25V6

1 2

TYP MAX Rdc : 15mohm 16.5mohm TYP MAX H/S Rds(on) : 8.2mohm 10.5mohm L/S Rds(on) : 8.2mohm 10.5mohm

4

3

CSON_1

0.1U_0402_25V6

PC722

1 2

12

BATSRC_CHG

PC716

22U_0805_25V6M

PR708 10_0402_1%

12

PC717

12

22U_0805_25V6M

PQ703_S

BATT+

12

PC718

22U_0805_25V6M

B+

PL700

HCB3225KF-151T50_2P

1 2

12

PC708

PC709

PC714

2.2U_0603_16V6K

LG_CHG

23

REGN

LODRV

SCL

CMPIN

13

PR7310_0402_5%@

1 2

CMPIN

<9,36,59,71>

PR7320_0402_5%@

EMI@

22

GND

TB_STAT#

BATPRES#

CMPOUT

14

1 2

<36,59>

CMPOUT

1U_0402_25V6K

BATDRV

BATSRC

PR7330_0402_5%@

<59>

EMI@

1000P_0402_50V7K

21

ILIM

20

SRP

19

SRN

18

17

16

15

<59>

<36,59>

12

PR712

1 2

2.2_0603_5%

REGN_CHG

BTST_CHG

24

25

BTST

SDA

12

11

SDA_CHG

SCL_CHG

PR7300_0402_5%@

1 2

<71>

PBAT_CHG_SMBCLK

PBAT_CHG_SMBDAT

PC704

EMI@

0.1U_0402_25V6

+3VALW

@

1 2

PR714

20K_0402_1%

1 2

ILIM_CHG

1 2

SRP_CHG

SRN_CHG

BATDRV_CHG

BATSRC_CHG

TB_STAT#_CHG

BATPRES#_CHG

PR723

@

1 2

PBAT_PRES#<36,59>

12

PC705

2200P_0402_50V7K

EMI@

PR713

7.5K_0402_1%

PR715

5.76K_0402_1%

12

PR722 10K_0402_1%

0_0402_5%

+3VALW

12

PC707

PC706

10U_0805_25V6K~D

PQ707_D

PQ706

@ 13

D

L2N7002WT1G 1N SC-70-3

TB_STAT#_CHG

2

G

S

12

UG_CHG

LX_CHG

LG_CHG

4

PR724 10_0402_1%

1 2

PR726 10_0402_1%

1 2

CHG_B+

5

123

5

123

PQ705 AON6380_DFN5X6-8-5

4.7UH_MMD-10DZ-4R7M-X2_9.5A_20%

PQ707

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2015/09/18 2016/09/18

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

PWR_CHARGER

LA-E992P

D

60 77Tuesday, July 25, 2017

0.3(X02)

of

A

1 1

3.3V*5.823A=19.22W

19.22/0.85/12=1.88A

5V*10.34A=51.7W

51.7/0.85/12=5.07A

1.88A+3.71A=5.59A

PL300

EMI@

HCB2012KF-121T50_0805

1 2

PL301

EMI@

12

PC306

EMI@

1000P_0402_50V7K

+3VALWP

HCB2012KF-121T50_0805

1 2

3/5V_B+

12

PC303

PC304

0.1U_0402_25V6

EMI@

2200P_0402_50V7K

S COIL 1.5UH +-20% 9A 7X7X3

B+

12

PC305

2 2

1U_0402_25V6K

EMI@

ESR = 18mohm

1

+

PC311 220U_6.3V_M

2

3.3VALWP TDC=5.823A Peak Current 8.318A

3 3

OCP current 9.8A FSW=475kHz TYP MAX H/S Rds(on) : 8.2mohm 10.5mohm L/S Rds(on) : 4mohm 5mohm

TYP MAX Rdc : 14mohm 15mohm

3V_EN

5V_EN

2.2K_0402_5%

ALWON<36,65>

4 4

CMP_VOUT0<36,55>

PR315

@

0_0402_5%

1 2

ALL_SYS_PWRGD<18,36>

A

1 2

L2N7002WT1G_SC70-3

S

G

POK need pull high, it will pull high on VS transfer circuit

12

PC307

PC308

10U_0805_25V6K~D

PL302

1 2

PR309

@EMI@

PC313

@EMI@

EN Rising=1.6~0.3V

PR311 0_0402_5%@

1 2

PR312 0_0402_5%@

1 2

PR313

PQ305

D

13

2

12

LX_3V

12

4.7_1206_5%

SNUB_3V

12

680P_0402_50V7K

PC316

PRIM_PWRGD_R<36,64,65>

B

5

123

5

123

PQ301 AON7380_DFN3X3-8-5

4

0.1U_0402_25V6

PQ302 AON6796_DFN5X6-8-5

4

PC309

1 2

+3VALWP

1 2

BST_3V

PR314 100K_0402_1%

LX_3V

PR307

0_0603_5%

1 2

UG_3V

3V_EN

VBST2

LG_3V

3/5V_B+

6.49K_0402_1%

1 2

PU300

PR300

VFB=2V

PR302

10K_0402_1%

6

EN2

7

PGOOD

8

SW2

9

VBST2

10

DRVH2

C

+3VLP

PC300

4.7U_0603_6.3V6K

1 2

VFB=2V

12

PR304

6.19K_0402_1%

CS2

5

CS2

TPS51285BRUKR_QFN20_3X3

DRVL2

11

FB_5V

FB_3V

3

4

2

VFB2

VFB1

VREG3

VREG5

VIN

VO114DRVL1

13

12

VL

12

PC315

4.7U_0603_6.3V6K

15.4K_0402_1%

1 2

10K_0402_1%

1 2

12

PR305

10.5K_0402_1%

CS1

1

TP

CS1

EN1

VCLK

SW1

VBST1

DRVH1

15

+5VALWP

PR301

PR303

D

Output capacitor ESR need follow below equation to make sure feed back loop stability ESR=20mV*L*fsw/2V

3/5V_B+

12

PC301

21

5V_EN

20

19

18

17

16

VCLK

LX_5V

VBST1

0_0603_5%

1 2

UG_5V

PR306

200_0402_1%

1 2

PR308

LG_5V

BST_5V

PC310

0.1U_0402_25V6

1 2

PC302

10U_0805_25V6K~D

5

10U_0805_25V6K~D

4

PQ303 AON7380_DFN3X3-8-5

123

5

AON6796_DFN5X6-8-5 PQ304

123

PL303

S COIL 1.5UH +-20% 9A 7X7X3

LX_5V

1 2

12

PR310

4.7_1206_5%

@EMI@

SNUB_5V

12

PC314

680P_0402_50V7K

@EMI@

E

1

ESR = 18mohm

+

PC312 220U_6.3V_M

2

+5VALWP

OVP=Vout*(112.5%~117.5%)

OCP=Vtrip/Rdson+Iripple/2 Vtrip=Ics(min)*Rcs/8+1mV Vcs=Ics*Rcs should be in the range of 0.2~2V

Vout=VFB*(1+Rtop/Rbot) VFB=2V

PJP31

2

112

@JUMP_43X118

PJP32

2

3V_5V_EN

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

0.1U_0402_25V6

B

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2014/2/11 2014/2/11

Compal Secret Data

Deciphered Date

112

@JUMP_43X118

D

5VALWP TDC=10.34A Peak Current=14.77A OCP current 17.8A FSW=400kHz TYP MAX H/S Rds(on) : 8.2mohm 10.5mohm L/S Rds(on) : 4mohm 5mohm

TYP MAX Rdc : 14mohm 15mohm

PJP33

+5VALW+5VALW P +3VALW+3VALW P

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PWR-3.3VALWP/5VALWP

LA-E992P

112

PJP34

112

2

@JUMP_43X118

2

@JUMP_43X118

E

0.3(X02)

61 77Tuesday, July 25, 2017

0.3(X02)

5

4

3

2

1

Input Current: 0.935A

1.2V*7.95A/0.85/12V=0.935

D D

Pin19 need pull separate from +1.2VP. If you have +1.2V and +0.6V sequence question,

PJP200

@

B+

12

PC204

1U_0402_25V6K

EMI@

C C

+1.2VP

B B

1.2VP TDC=7.95A Ipeak=11.356A OCP=15A Switching Frequency: 550kHz TYP MAX DCR : 6.7mohm 7.4mohm

OVP: 110%~120% VFB=0.75V, Vout=1.2V TYP MAX H/S Rds(on) : 22.7mohm 32mohm L/S Rds(on) : 13mohm 15.8mohm

22U_0603_6.3V6M

PC217

12

PC218

12

22U_0603_6.3V6M

PC221

PC222

12

2

112

JUMP_43X39

PC205

EMI@

1000P_0402_50V7K

1UH_11A_20%_7X7X3_M

22U_0603_6.3V6M

PC219

12

22U_0603_6.3V6M

PC223

12

PL200

1 2

22U_0603_6.3V6M

PC220

@EMI@

22U_0603_6.3V6M

680P_0402_50V7K

PC224

+1.2VP +1.2V_DDR

+0.6VSP +0.6VS

12

PC200

EMI@

4.7_1206_5%

0.1U_0402_25V6

PR202

PC213

1.2V_B+

12

+3VALW

PC201

EMI@

2200P_0402_50V7K

12

SNUB_1.2V

12

PC202

10U_0805_25V6K~D

JUMP_43X118

12

PC203

10U_0805_25V6K~D

1 2

PR206 100K_0402_1%@

PJP201

@

112

PJP202

@

112

PJP203

@

112

JUMP_43X39

3 5

241

3 5

241

2

PR200

BST_1.2V

12

PC206

0.1U_0603_25V7K

PQ201 AON7408L_DFN8-5

PR201=20.5K for OCP=15A, Ron=15.8mohm, delta_I=3.94A

PQ202 AON7506_DFN33-8-5

+5VALW +1.2VP

5.1_0603_5%

1 2

1U_0603_10V6K

1.2V_PGOOD

PR203

PC214

1 2

PR201

20.5K_0402_1%

1 2

1U_0603_10V6K

12

1.2V_VDDQ_EN<43>

2.2_0603_5%

PC209

1 2

VDD_1.2V

1.2V_B+

SIO_SLP_S3#<18,38,39,42,43,44>

SM_PG_CTRL<9>

LG_1.2V

CS_1.2V

VDDP_1.2V

PR204

2.2_0603_5%

1 2

453K_0402_1%

1 2

you can change from +1.2VP to +1.2VS.

BOOT_1.2V

UG_1.2V

LX_1.2V

16

17

15

14

13

12

11

PR207

1 2

PU200

LGATE

PGND

CS

VDDP

VDD

@

0_0402_5%

PHASE

UGATE

RT8207PGQW_WQFN20 _3X3

PGOOD

TON

9

10

TON_1.2V

PR209

PC215

@

0.1U_0402_10V7K

PR210

@

0_0402_5%

1 2

PR211

@

1 2

0_0402_5%

18

8

EN_1.2V

12

20

19

VTT

BOOT

S5

PAD

VLDOIN

VTTGND

VTTSNS

GND

VTTREF

VDDQ

FB

S3

6

7

EN_0.6VSP

12

FB_1.2V

12

PR208

20K_0402_1%

21

1

2

3

4

5

+1.2VP

12

PC207

10U_0805_6.3V6K

VTTREF_1.2V

0.6VSP TDC 1.05A Peak Current 1.5A

12

PC208

10U_0805_6.3V6K

12

PC212

0.033U_0402_16V7K

PR205

12K_0402_1%

1 2

+0.6VSP

+1.2VP

Mode Level +0.6VSP VTTREF_1.2V S5 L off off S3 L off on

A A

S0 H on on

Note: S3 - sleep ; S5 - power off

5

RILMT=ILIMIT*Ron/10uA where RILMT=PR201=20.5K,Ron=15.8m =>ILIMIT=15A

4

Security Classification

2015/09/18 2016/09/18

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2015/09/18 2016/09/18

3

Compal Secret Data

Deciphered Date

PC216

@

0.1U_0402_10V7K

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PWR-1.2VP/0.6VSP

LA-E992P

62 77Tuesday, July 25, 2017

1

0.3(X02)

A

1 1

B

C

D

Input Current:0.42A

2.5*0.428=1.07W

1.07/0.85/3=0.42A

+3VALW

PR25V00

@

2 2

SIO_SLP_S4#<18,42,43>

+3VALW

1 2

PJP25V1

@

112

JUMP_43X79

0_0402_5%

2

PR25V01

VIN_2.5V

+5VALW

EN_2.5V

12

@

PC25V00

1M_0402_1%

0.1U_0402_16V7K

12

PC25V01

22U_0603_6.3V6M

12

PR25V02

@

100K_0402_1%

9

2.5V_PGOOD

12

PC25V02

22U_0603_6.3V6M

12

PU25V00

1

PGOOD

2

EN

3

VIN

4

VDD

RT9059GSP_SO8

GND

ADJ

VOUT

8 7 6 5

NC

Vout=0.8*(1+Rup/Rdown)

FB_2.5V

Rup

PR25V03

21.5K_0402_1%

PR25V04

10K_0402_1%

12

Rdown

+2.5V_MEMP

12

PC25V03

22P_0603_50V8

12

PC25V05

PC25V04

22U_0603_6.3V6M

PJP25V2

3 3

PC25V06

1U_0603_6.3V6M

+2.5V_MEMP +2.5V_MEM

@

112

JUMP_43X79

2

+2.5V_MEM TDC 0.428A Peak Current 0.612A OCP Current 3.5A

4 4

Security Classification

2015/09/18 2016/09/18

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

2015/09/18 2016/09/18

Compal Secret Data

Deciphered Date

C

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

PWR_+2.5V_MEM

LA-E992P

D

63 77Tuesday, July 25, 2017

0.3(X02)

of

5

D D

Input Current: 0.42A 1V*4.2805A/0.85/12V=0.42

+1V_B+

2

B+

C C

PRIM_PWRGD_R<36,61,65>

B B

12

PC100

EMI@

1000P_0402_50V7K

PR103

@

0_0402_5%

1 2

1M_0402_1%

@

JUMP_43X79

PC105

1U_0402_25V6K

EMI@

PR102

112

PJP11

12

PC102

EMI@

2200P_0402_50V7K

12

@

0.1U_0402_25V6

PC107

PC101

0.1U_0402_25V6

EMI@

12

+3VALW

12

PC104

10U_0805_25V6K~D

PR108

@

0_0402_5%

PR109

@

0_0402_5%

PC103

@

12

10U_0805_25V6K~D

4

EN_1V

ILMT_1V

+3VALW

PC108

1U_0402_6.3V6K

18

11

13

15

12

PU100

2

IN

3

IN

4

IN

5

IN

7

GND

8

GND

EN

ILMT

BYP

SY8286RAC_QFN20_3X3

1V_PG

9

PG

VBST_1V BST_1V

1

BS

LX_1V

6

LX

19

LX

20

LX

FB_1V

14

FB

LDO_1V

17

VCC

10

NC

12

NC

16

NC

21

PAD

PR101

@

0_0402_5%

1 2

3V

12

PC115

2.2U_0402_6.3V6M

3

1V_PG <36>

@EMI@

4.7_1206_5%

1 2

PC106

0.1U_0603_25V7K

1 2

Vout=0.6V* (1+R1/R2) =0.6*(1+(14/20))

Vout=1.02V

PR104

SNUB_1VALWP

PL100

1UH_11A_20%_7X7X3_M

1 2

FB=0.6V

@EMI@

680P_0603_50V7K

1 2

12

R1

12

PR107

R2

20K_0402_1%

PC111

PR106

2

+1VALW TDC 4.2805A Peak Current 6.115A OCP current 9A FSW=500KHz TYP MAX DCR: 6.7mohm 7.4mohm

IL=1.9A@19.5V ripple=7.3mV@19.5V

+1VALWP

PJP12

@

JUMP_43X118

112

1

2

+1VALW

+1VALWP

12

PC114

PC113

14K_0402_1%

330P_0402_50V7K

PC112

22U_0603_6.3V6M

12

PC109

PC110

22U_0603_6.3V6M

The current limit is set to 6A, 9A or 12A when this pin is pull low, floating or pull high.

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

PWR.Plane.Regulator(35.25), Support component(35.26)

5

4

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2015/09/18 2016/09/18

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PWR-+1VALWP

LA-E991P

1

64 77Tuesday, July 25, 2017

0.3(X02)

5

4

3

2

1

Input Current:0.227A

D D

1.8*1.289/0.85/12V=0.227A

+1.8VSP TDC 1.289A Peak Current 1.842A OCP current 6A FSW=500KHz TYP MAX DCR: 24mohm 27mohm

Input 0.7A

PJP18V1

B+

C C

ALWON<36,61>

+3VALW

B B

The current limit is set to 6A, 9A or 12A when this pin is pull low, floating or pull high.

@

112

JUMP_43X39

PR18V00

@

0_0402_5%

1 2

@

1 2

2

PR18V06

0_0402_5%

PR18V07

@

0_0402_5%

PR18V04

1M_0402_1%

1.8V_B+

12

ILMT_1.8V

+3VALW

1 2

PC18V00

PC18V02

10U_0805_25V6K~D

1.8V_EN

12

PC18V09

0.1U_0402_16V7K

PU18V00

2

IN

3

IN

4

IN

5

IN

7

GND

8

GND

18

GND

11

EN

13

ILMT

15

BYP

SY8286RAC_QFN20_3X3

VCC

PAD

9

PG

1

BS

6

LX

19

LX

20

LX

14

FB

17

10

NC

12

NC

16

NC

21

1 2

FB_1.8V

VCC_1.8V

2.2U_0402_16V6K

PR18V01 0_0603_5%

12

PC18V08

BST_1.8VBS_1.8V

LX_1.8V

Vout=0.6V* (1+Rup/Rdown)

12

PC18V11

1U_0603_6.3V6M

PRIM_PWRGD_R <36,61,64>

PC18V01

0.1U_0603_25V7K

1 2

12

4.7_0603_5%

SUNB_1.8V

12

PL18V00

1 2

1UH_PCMB042T-1R0MS_4.5A_20%

PR18V03

@EMI@

PC18V10

@EMI@

680P_0402_50V7K

Rdown

12

22U_0603_6.3V6M

PJP18V2

@

112

JUMP_43X79

+1.8VSP

PC18V07

22U_0603_6.3V6M

2

+1.8V_PRIM

12

PC18V05

PC18V06

22U_0603_6.3V6M

330P_0402_50V7K

Rup

12

PR18V02

20.5K_0402_1%

PC18V04

22U_0603_6.3V6M

PC18V03

12

PR18V05

10K_0402_1%

+1.8VSP

A A

Security Classification

2016/01/06 2017/01/06

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2016/01/06 2017/01/06

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PWR_+1.8VSP

LA-E992P

65 77Tuesday, July 25, 2017

1

0.3(X02)

5

4

3

2

1

Input Current:0.231A

+1.0VS_VGAP TDC 0.9835A

1*0.9835/0.85/5=0.231A

Peak Current 1.405A OCP current 4A

D D

FSW=1MHz TYP MAX DCR 45mohm 59mohm

PL10V01

+5VALW

PJP10V0

112

JUMP_43X39

+1.0VS_VGAP

C C

PEX_VDD_EN<55>

+1V8_AON

3A_Z120_40M_0603_2P

@

1 2

2

@

PR10V4

@

1 2

0_0402_5%

PR10V6

1 2

0_0402_5%

1.0VS_VGAP_VIN

PC10V0

Rup

PR10V2

12

6.81K_0402_1%

1 2

PC10V6

22P_0603_50V8

1 2

10U_0603_6.3V6M

FB_1.0VS_VGAP

PR10V5

1 2

PC10V1

1U_0603_6.3V6M

12

PR10V3

10K_0402_1%

12

PC10V7

@

1M_0402_1%

0.1U_0402_16V7K

PU10V0

11

TP

10

PVIN

9

PVIN

8

SVIN

7

NC

6

FB

RT8061AZQW_WDFN1 0_3X3

Rdown

EN_1.0VS_VGAP

PGOOD

1

NC

2

LX

3

LX

4

5

EN

+3V3_SYS

PR10V1 10K_0402_5%

1 2

LX_1.0VS_VGAP

+1.0VS_VGA_PGOOD <55>

PL10V0

1 2

12

1UH_1239AS-H-1R0M-P2_3A_20%

PR10V0

@EMI@

4.7_0603_5%

SNB_1.0VS_VGAP

12

PC10V5

@EMI@

680P_0402_50V7K

+1.0VS_VGAP

12

PC10V2

12

PC10V4

PC10V3

22U_0603_6.3V6M

Vout=0.6V* (1+Rup/Rdown)

PJP10V1

@

112

JUMP_43X79

2

+PEX_VDD+1.0VS_VGAP

B B

A A

Security Classification

2016/01/06 2017/01/06

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2016/01/06 2017/01/06

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PWR_+1.0VS_VGA

LA-E992P

1

0.3(X02)

66 77Tuesday, July 25, 2017

5

4

PC6000

0.1U_0402_25V6

1 2

NVVDD_B+

3

NVVDD_ISUMP1<68>

12

NVVDD_ISUMP2<68> NVVDD_ISUMP3<68>

12

2

1

12

COMP_GPU_1

PC6008 0.1U_04 02_25V6@

PR6022

0_0402_5%

@

1 2

FBRTN

PR6043

12

4.32K_0402_1%

R4

R5

PR6064

12

20.5K_0402_1%

PR6000

100K_0402_5%

PR6017 2.4K_040 2_1%

1 2

PU6000

31

FB

32

FBRTN

33

APL3

34

APL4

35

LPC

36

EN

37

PSI

38

PGOOD

39

VID

40

REFADJ

41

GND

R3

12

PR6052

REFIN_2

12

PR6062

FBRTN

D D

PC6002

0.01U_0402_16V7K

1 2

PC6006 0.015U_0 402_16V7K

1 2

PR6070

@

1 2

PR6024 0_0402_5%@

FB_RC_2

20K_0402_1%

PR6069

@

0_0402_5%

FB_RC_1

GPU_PROG3

GPU_PROG4

GPU_LPC

NVVDD1_ENP

PC6011

@

1 2

0.1U_0402_25V6

PR6025 1K_0402_1%

GPU_PSI

12

PR6039

REFIN_1

12

PC6015

FB_GPU

12

GPU_VID

REFADJ

R1

6.19K_0402_1%

R2

C

4700P_0402_50V7K

PR6021

NVVDD_VCC_SENSE<49>

+NVVDD1

C C

NVVDD_VSS_SENSE<49>

+3VALW

NVVDD1_EN<55>

+3VS

B B

+1.8V_PRIM

NVVDD_PSI <46>

A A

@

0_0402_5%

PR6023 100_0 402_5%

PR6026

@

0_0402_5%

PR6030

100_0402_5%

PR6034

1 2

10K_0402_5%

@

PR6040

1 2

0_0402_5%

PR6051 0_0402_ 5%@

1 2

@

PR6054 0_040 2_5%

12

1 2

12

FBRTN

PQ8203B_G

61

2

PR6042 0_040 2_5%@

12

+3VS

NVVDD1_PGOOD<46,55>

5

PQ6000A

DMN53D0LDW-7 2N SOT363-6

PR6061

100K_0402_5%

1 2

NVVDD_VID<46>

12

PR6036

3

PQ6000B

4

DMN53D0LDW-7 2N SOT363-6

1 2

PR6006

12

16.5K_0402_1%

309_0402_1%

910K_0402_5%

12

PR6018

0_0402_5%

@

EAP

COMP

30

29

EAP

COMP

REFIN1VREF2FSW3PWM84PWM75PWM66PWM57PWM48PWM39PWM2

REFIN

VREF

1 2

PC6016

0.01U_0402_16V

GPU_IMON

SS

VINMON

GPU_PROG5

25

26

27SS28

LLTH

IMON

VINMON

GPU_PROG6

PR6002

20K_0402_1%

@

PR6007

1 2

0_0402_5%

PR6011 0 _0402_5%@

PR6013

13.7K_0402_1%

PC6007 0.12U_0 402_10V6K

CSPSUM

CSNSUM

GPU_PROG1

GPU_PROG2

22

24

21

APL223APL1

CSPSUM

CSNSUM

10

PWM2

PWM3

PR6003

20K_0402_1%

NTC_La NTC_Lb

@

PR6008

1 2

0_0402_5%

1 2

ISEN1

ISEN2

ISEN3

ISEN4

ISEN5

ISEN6

ISEN7

ISEN8

5VCC

PWM1

PR6045 0_0402_5%@

1 2

PR6053 0_0402_ 5%@

12

20

19

18

17

16

15

14

13

12

11

PWM1

12

PR6020 1K_0402 _1%

UP9511PQGJ_VQFN40 _5X5

PWMVID 的RC BOM 請根據GPU's config 設定

5

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2016/01/06 2017/01/06

3

Compal Secret Data

PR6004

20K_0402_1%

PR6009 1_040 2_1%

PR6010 1_040 2_1%

PR6012 1_040 2_1%

NTC_La NTC_Lb

470K_0402_5%_B25/5 0 4700K

12

PC6009

0.1U_0402_10V6K

ISEN1

ISEN2

ISEN3

ISEN4

5VCC

PR6041

@

0_0402_5%

1 2

Deciphered Date

12

@

PH6000

1 2

PR6027 2.2K_040 2_1%

12

PR6028 2.2K_040 2_1%

12

PR6029 2K_0402 _1%

12

100K_0402_5%

5VCC

1U_0402_6.3V6K

PC6014

12

GPU_PWM1 <68>

GPU_PWM2 <68>

GPU_PWM3 <68>

2

layout 上 : 請將 Total DCR sensing 的componen t 放靠近Controlle r.

NVVDD_ISUMN1 <68 >

NVVDD_ISUMN2 <68 >

NVVDD_ISUMN3 <68 >

OCP=(Vocp-0.6V)*N*Rsum/Rimon/Rdc Where Vocp=1.6V(3phase),Rsum=Pr6020,Rimon=Pr6013, N=Phase number,Rdc=Ouput Inductor's DCR=0.98m Ohm

layout 上 : 請將 RSEN1 ~ 4 放靠近 C o n t r o l l e r.

LX_GPU_PH1

LX_GPU_PH2

LX_GPU_PH3

PR6033

12

5VCC

PR6037 2.2_0603 _1%

+5VS

12

請教AUTO PHASE的設定

+5VS

PR6046

1 2

PR6056

1 2

GPU_PROG1

PR6047

1 2

43K_0402_5%

PR6057

1 2

8.2K_0402_5%

GPU_PROG2

Title

Size Do cument Number Rev

Date: Sheet of

Date: Sheet

PR6048

1 2

36K_0402_5%

8.2K_0402_5%

10K_0402_5%

PR6058

0_0402_5%

1 2

@

GPU_PROG3

NVVDD1 TDC 70A Peak Current 160A OCP= 210A

GPU_PROG6

Fsw=300kHz

PR6044

1 2

10K_0402_5%

PR6059

0_0402_5%

@

1 2

GPU_PROG4

Compal Electronics, Inc.

PWR_VGA_UP9511P

GPU_PROG5

Cold Boot = 4-phase Warm Boot = 4-phase

LA-E992P

12

PR6035

@

0_0402_5%

FSW_GPU_R

PR6038

1 2

33K_0402_5%

1 2

PR6060

@

PR6063

1 2

0_0402_5%

@

1 2

GPU_LPC

67 77Tuesday, July 25, 2017

1

PR6050

10K_0402_5%

0_0402_5%

0.3(X02)

of

1

B+

PR6102

@

+5VS

A A

GPU_PWM1<67>

B B

C C

D D

+5VS

GPU_PWM2<67>

PC6122

EMI@

+5VS

GPU_PWM3<67>

PC6131

EMI@

0_0402_5%

NVVDD_B+

PR6109

@

0_0402_5%

NVVDD_B+

12

1U_0402_25V6K

PR6116

@

0_0402_5%

NVVDD_B+

12

1U_0402_25V6K

12

PR6104 1K_0402_1%

12

PC6105

PR6110 1K_0402_1%

12

PC6125

PR6118 1K_0402_1%

12

PC6137

12

PR6107

1 2

2.2_0402_1%

BST_GPU_PH1

12

PC6112

10U_0805_25V6K~D

12

PR6114

1 2

2.2_0402_1%

BST_GPU_PH2

12

PC6126

10U_0805_25V6K~D

12

PR6121

1 2

2.2_0402_1%

BST_GPU_PH3

12

PC6138

10U_0805_25V6K~D

0.1U_0603_50V7K

12

0.1U_0603_50V7K

12

+5VS

PC6100

1U_0603_16V7

12

PR6105

0_0402_5%

1 2

@

12

PC6111

PC6110

0.1U_0402_25V6

EMI@

12

PR6111

@

12

PC6117

PC6123

0.1U_0402_25V6

EMI@

1000P_0402_50V7K

12

PR6119

@

12

PC6133

PC6132

0.1U_0402_25V6

EMI@

1000P_0402_50V7K

PC6103

PC6104

EMI@

2200P_0402_50V7K

10U_0805_25V6K~D

+5VS

PC6114

1U_0603_16V7

12

0_0402_5%

1 2

12

PC6118

EMI@

2200P_0402_50V7K

+5VS

0_0402_5%

1 2

12

PC6134

EMI@

2200P_0402_50V7K

PC6119

PC6124

10U_0805_25V6K~D

PC6128

1U_0603_16V7

12

PC6135

PC6136

10U_0805_25V6K~D

1

2

0.005_2512_1%

PC6102

1 2

1

+

PC6106

2

100U_25V_M

PC6115

1 2

0.1U_0603_50V7K

PC6129

1 2

2

PR6100

BOOT_GPU1

GPU_B+

4

3

CSSN_B+<49>CSSP_B+<49>

ZCD_EN#_GPU_PH1

LX_GPU1

ZCD_EN#_GPU_PH2

BOOT_GPU2

LX_GPU2

ZCD_EN#_GPU_PH3

BOOT_GPU3

LX_GPU3

PR6101

1

2

0.005_2512_1%

CSSP_NVVDD <49>

PU6100

1

PWM

2

ZCD_EN#

3

VCIN

4

CGND

5

BOOT

6

NC

7

PHASE

8

VIN

9

VIN

10

PGND

11

SW

12

SW

13

SW

14

SW

SIC632CDT1GE3_POW ERPAK31_5X5

PU6101

1

PWM

2

ZCD_EN#

3

VCIN

4

CGND

5

BOOT

6

NC

7

PHASE

8

VIN

9

VIN

10

PGND

11

SW

12

SW

13

SW

14

SW

SIC632CDT1GE3_POW ERPAK31_5X5

PU6102

1

PWM

2

ZCD_EN#

3

VCIN

4

CGND

5

BOOT

6

NC

7

PHASE

8

VIN

9

VIN

10

PGND

11

SW

12

SW

13

SW

14

SW

SIC632CDT1GE3_POW ERPAK31_5X5

4

3

CGND

DSBL#

THWn VDRV PGND

CGND

DSBL#

THWn VDRV PGND

CGND

DSBL#

THWn VDRV PGND

3

PL6100

1 2

PC6101

DSBL_GPU_PH2

VDRV_GPU_PH2

PC6116

DSBL_GPU_PH3

VDRV_GPU_PH3

PC6130

EMI@

NVVDD_B+NVVDDB_B+

PR6103

1 2

10K_0402_1%

PR6106

2.2_0603_1%

12

PR6108

2.2_0603_1%

SNB_GPU1

12

PC6113

3300P_0805_50V7K

PR6112

1 2

10K_0402_1%

PR6113

2.2_0603_1%

12

PR6115

2.2_0603_1%

SNB_GPU2

PC6127

3300P_0805_50V7K

12

PR6122

2.2_0603_1%

SNB_GPU3

12

PC6141

3300P_0805_50V7K

12

PR6117

1 2

10K_0402_1%

PR6120

2.2_0603_1%

12

LX_GPU_PH1

12

FBMA-L11-453215800L MA90T_2P

12

PC6108

PC6109

1U_0402_25V6K

EMI@

CSSN_NVVDD<49>

28 27

GL

26 25 24 23 22

GL

21

SW

20

SW

19

SW

18

SW

17

SW

16

SW

15

SW

28 27

GL

26 25 24 23 22

GL

21

SW

20

SW

19

SW

18

SW

17

SW

16

SW

15

SW

28 27

GL

26 25 24 23 22

GL

21

SW

20

SW

19

SW

18

SW

17

SW

16

SW

15

SW

1000P_0402_50V7K

DSBL_GPU_PH1

VDRV_GPU_PH1

12

1U_0603_16V7

+5VS

NVVDD_ISUMP1<67>

NVVDD_ISUMN1<67>

+5VS

LX_GPU_PH2

NVVDD_ISUMP2<67>

NVVDD_ISUMN2<67>

+5VS

LX_GPU_PH3

NVVDD_ISUMP3<67>

NVVDD_ISUMN3<67>

4

LX_GPU_PH1

LX_GPU_PH2

LX_GPU_PH3

+NVVDD1 TDC 70A Peak Current 160A OCP=210A DCR:0.98mohm +-5% MAX H/S Rds(on):4.8mohm L/S Rds(on):1.3mohm

PL6101

1

2

1

2

PL6103

1

2

0.22UH_MMD-06DZER22 MEM2L__32A_20%

4

3

0.22UH_MMD-06DZER22 MEM2L__32A_20%

PL6102

4

3

0.22UH_MMD-06DZER22 MEM2L__32A_20%

4

3

5

+NVVDD1

1

+

PC6107

2

470U_D2_2VM_R4.5M~D

+NVVDD1

1

+

PC6121

2

470U_D2_2VM_R4.5M~D

+NVVDD1

1

+

PC6140

2

470U_D2_2VM_R4.5M~D

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2016/01/06 2017/01/06

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Do cument Number Rev

Date: Sheet of

4

Date: Sheet of

Compal Electronics, Inc.

PWR_+NVVDD1

LA-E992P

68 77Tuesday, July 25, 2017

5

0.3(X02)

5

4

3

2

1

Input Current: 2.074A

1.35V*15.67A/0.85/12V=2.074A

PL800

D D

+3VS

DGPU_PWROK<18,46,55>

OCP=Vtrip/Rdson+Iripple/2 Vtrip=Rtrip*Itrip/8

PR803

20K_0402_1%

FBVDD/Q_EN<55>

C C

1 2

12

PC800

0.1U_0402_16V7K

+1V8_AON

PR802

30.9K_0402_1%

1 2

12

TRIP_+1.35V

EN_+1.35V

FB_+1.35V

RF_+1.35V

PR804

470K_0402_1%

PC814

820P_0402_50V7K

1 2

PR807

9.76K_0402_1%

1 2

PR800

@

100K_0402_1%

PU800

1

2

3

4

5

VBST

PGOOD

TRIP

DRVH

EN

V5IN

VFB

DRVL

TST

TPS51212DSCR_SON10_3X3

PR815

49.9_0402_1%

1 2

PR801

VBST_+1.35V

10

UG_+1.35V

9

LX_+1.35V

8

SW

7

LG_+1.35V

6

11

TP

2.2_0603_5%

1 2

12

PC809 1U_0603_6.3V6M

0.1U_0603_25V7K

BST_+1.35V

+5VALW

PC808

1 2

1

2

S2

3

D1

S24S2

D2/S1

5

PQ800

AON6992_DFN5X6D-8-7

G1

7

G2

6

S2

3

2

D1

S24S2

+1.35VS_VGAP_B+

1

G1

D2/S1

G2

5

6

12

PC801

PC802

0.1U_0402_25V6

EMI@

2200P_0402_50V7K

AON6992_DFN5X6D-8-7

PQ801

7

0.88UH_PCMC104T-R88MN_20A_20%

12

SNUB_+1.35V

12

PL801

1 2

PR805

@EMI@

4.7_1206_5%

PC812

@EMI@

680P_0402_50V7K

12

PC803

PC804

22U_0805_25V6M

12

PR813

FBMA-L11-453215800LMA90T_2P

12

PC805

@

22U_0805_25V6M

1.35VS_VGAP TDC=19.8A Ipeak=32.2A OCP=38.3A Switching Frequency: 290kHz TYP MAX DCR : 2.7mohm 3.0mohm

PC810

100_0402_1%

1 2

1

+

2

220U_D2 SX_2VY_R9M

EMI@

GPU_B+

12

PC807

PC806

1U_0402_25V6K

EMI@

1000P_0402_50V7K

+1.35VS_VGAP

1

+

PC811

2

@

220U_D2 SX_2VY_R9M

12

PR812

@

Ra

2

G

47.5K_0402_1%

13

D

PQ802 BSS138W_SOT323-3

S

PR809

10.5K_0402_1%

Rb

PR812

47.5K_0402_1%

M6G@

PR812

35.7K_0402_1%

H6G@

PR812

35.7K_0402_1%

S6G@

PJP801

@

+1.35VS_VGAP +1.35VS_VGA

JUMP_43X118

112

@

112

PJP802

2

PR811

1 2

100K_0402_1%

PR810

1K_0402_1%

MEM_VDD_CTL<4 6>

B B

1 2

12

PC813

.047U_0402_16V7K

PR814

@

0_0402_5%

1 2

Switching Frequency: 290kHz OVP: 120%-130% VFB=0.7V TYP MAX H/S Rds(on) : 6.8mohm 8.6mohm L/S Rds(on) : 2mohm 2.5mohm

FB_VDDQ_SENSE <49>

N17E-G2/-G1 MAX-Q: P0:4004MHz,FBVDD=1.55V/1.50V P2:3802MHz,FBVDD=1.55V/1.50V P3:3003MHz,FBVDD=1.35V P5:810MHz,FBVDD=1.35V Idle(P8):405MHz,FBVDD=1.35V

If MEM_VDD_CTL high: Ra=47.5Kohm,Rb=10.5Kohm Ra//Rb = 8.599kohm Vout=0.704*(1+(9.76/8.599))=1.503V

A A

If MEM_VDD_CTL low: Vout=0.704*(1+(9.76/10.5))=1.358V

If MEM_VDD_CTL high: Ra=35.7Kohm,Rb=10.5Kohm Ra//Rb = 8.114kohm Vout=0.704*(1+(9.76/8.114))=1.5508V

If MEM_VDD_CTL low: Vout=0.704*(1+(9.76/10.5))=1.358V

5

BOM config GPU type VRAM memory VRAM vender RVL PR809 PR812 PR807

X7673331L07

X7673331L08

X7673331L09

N17E-G1 MAXQ

4

256Mx32

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Samsung

Hynix

Micron

2014/2/11 2014/2/11

3

1.35V & 1.55V

1.35V & 1.5V 10.5K

Compal Secret Data

Deciphered Date

10.5K

2

35.7K

9.76K

35.7K 9.76K

47.5K

Title

Size Document Number Rev

Date: Sheet of

Date: Sheet

9.76K

Compal Electronics, Inc.

PWR-1.35VRAM

LA-E992P

0.3(X02)

of

69 77Tuesday, July 25, 20 17

1

5

4

3

2

1

H_PROCHOT#<9,36,59,60>

+VCCST

12

D D

VR_SVID_CLK<9>

PR5014

12.4K_0402_1%

1 2

PC5006

1000P_0402_50V7K

1 2

12

PR5025 1K_0402_1%

1 2

12

PC5019

1 2

2200P_0402_50V7K

PR5040

PC5026

1 2

PC5029

0.022U_0402_25V7K

1 2

PC5036

1 2

330P_0402_50V7K

PR5048

27.4K_0402_1%

VR_SVID_ALERT#<9>

VR_SVID_DATA<9>

PR5045

12.4K_0402_1%

1 2

PH5004

1 2

PR5010

1 2

97.6K_0402_1%

PC5004

1 2

330P_0402_50V7K

PC5005

1 2

68P_0402_50V8J

PR5021

PC5007

1 2

12

PR5034

12

2.61K_0402_1%

10K +-5% 0402 B25/50 4250K PH5002

3.6K_0402_1%

12

VCCGT_SENSE<12>

VSSGT_SENSE<12>

PR5035

11K_0402_1%

6800P_0402_25V7K

C C

ISUMP_GT<73>

ISUMN_GT<73>

B B

FCCM_GT<73>

PWM1_GT<73>

PWM2_GT<73>

A A

12

PC5017

12

PH5000

1 2

470K_0402_5%_B25/50 4700K

27.4K_0402_1%

12

0.15U_0402_16V7K

PC5024

.1U_0402_16V7K

PR5013

1 2

PC5018

0.068U_0402_16V7K

93.1K_0402_1%

PC5008

1000P_0402_50V7K

PC5009

470P_0402_50V7K

1 2

2.87K_0402_1%

12

PC5014

0.01UF_0402_25V7K

1K_0402_1%

PR5047

12

PR5031

1 2

12

PR5022

2K_0402_1%

PR5038

1 2

294_0402_1%

0.022U_0402_25V7K

1 2

PR5006 0_0402_5%@

PR5008 0_0402_5%@

PR5011 0_0402_5%@

+3VS

IMVP_VR_PG<18>

VR_ON<18>

P_SYS<60>

ISEN2_GT <73>

ISEN1_GT <73>

1 2

PC5037

12

1000P_0402_50V7K

470K_0402_5%_B25/50 4700K

PC5038

68P_0402_50V8J

PR5001

45.3_0402_1%

12

PR5015

1 2

1.91K_0402_1%

PR5020

@ 1 2

0_0402_5%

12

PR5028

0_0402_5%

@

12

1 2

12

PR5002

@

75_0402_1%

PR5023

@

1 2

0_0402_5%

1

PSYS

2

IMON_B

3

NTC_B

4

COMP_B

5

FB_B

6

RTN_B

7

ISUMP_B

8

ISUMN_B

9

ISEN1_B

10

ISEN2_B

11

FCCM_B

12

PWM1_B

49

EP

PR5051

3.65K_0402_1%

PC5040

6800P_0402_25V7K

PR5003

100_0402_1%

PR5009 0_0402_5%@

12

PC5001

0.1U_0402_25V6

1 2

46

47

48

VR_READY

VR_ENABLE

PWM2_B13NTC_A15COMP_A16FB_A17RTN_A18ISUMP_A19ISUMN_A

IMON_A

14

PR500749.9_0402_1%

PR501210_ 0402_1%

44

45

SCLK

VR_HOT#

12

47P_0402_50V8J~D

41

42

43

VIN

SDA

VCC

ALERT#

20

2200P_0402_50V7K

PR5049

2K_0402_1%

PC5039

+5VS

PC5000

12

PR5000

0_0402_5%

@

PR5004

1_0402_5%

ISL95829AHRTZ-T_TQFN48_6X6

39

38

40

PROG2

PROG3

PROG437PROG1

ISUMN_C

ISUMP_C

COMP_C

ISEN1_A21ISEN2_A22ISEN3_A23FCCM_A

24

ISEN3_VCORE<72>

PR5041

1 2

287_0402_1%

PC5033

1 2

12

PU5000

PROG5 PWM_C

FCCM_C

RTN_C

IMON_C PWM3_A PWM2_A PWM1_A

CPU_B+

1 2

FB_C

ISEN2_VCORE<72>

PR5005

@

0_0402_5%

36 35 34 33 32 31 30 29 28 27 26 25

ISEN1_VCORE<72>

1 2

1K_0402_1%

PR5043

1U_0402_16V6K

0.22U_0603_25V7K

1 2

PR5046

1K_0402_1%

PC5002

1 2

PC5003

12

PR5050

2.43K_0402_1%

12

PR5017

PR5018

PR5016

16.9K_0402_1%

169K_0402_1%

PR5026

48.7K_0402_1%

1 2

PC5025 0.022U_0402_2 5V7K

1 2

PC5027 0.022U _0402_25V7K

12

PC5034

100P_0402_50V8J

12

PR5019

5.62K_0402_1% 110K_0402_1%

PWM_SA <73>

FCCM_SA <73>

PWM3_VCORE <72>

PWM2_VCORE <72>

PWM1_VCORE <72>

FCCM_VCORE <72>

1 2

PC5028 0.022U_0402_2 5V7K

2200P_0402_50V7K

12

PR5039

VCCSENSE <10>

PC5010

110K_0402_1%

PR5024

1.1K_0402_1%

1 2

PR5027

12

PC5020

330P_0402_50V7K

12

PC5030

.1U_0402_16V7K

12

PC5035

0.01UF_0402_25V7K

12

1K_0402_1%

1 2

12

PC5021

68P_0402_50V8J

PC5031

VSSSENSE <10>

2200P_0402_25V7K

12

PC5013

.1U_0402_16V7K

12

PR5037

4.53K_0402_1%

12

PC5022

2200P_0402_50V7K

12

PC5032

12

10K +-5% 0402 B25/50 4250K

PR5032

PR5029

4.42K_0402_1%

11K_0402_1%

1 2

PR5033

2.74K_0402_1%

PH5001

12

PR5030

3.6K_0402_1%

1 2

PC5015

1500P_0402_50V7K

ISUMN_VCORE <72>

ISUMP_VCORE <72>

12

PR5042

12

2K_0402_1%

PR5036

PC5023

680P_0402_50V7K

11K_0402_1%

12

PC5012

0.022U_0402_25V7K

1 2

316_0402_1%

12

10K +-5% 0402 B25/50 4250K

PH5003

12

PR5044

12

PC5011

0.01UF_0402_25V7K

12

0.22U_0402_16V7K

ISUMN_SA <73>

ISUMP_SA <73>

VCCSA_SENSE <11>

12

PC5016

0.01UF_0402_25V7K

VSSSA_SENSE <11>

680P_0402_50V7K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

Compal Secret Data

2016/01/06 2017/01/06

Deciphered Date

Compal Electronics, Inc.

Title

PWR_VCORE_ISL95855

Size Docum ent Number Rev

Date: Sheet

LA-E992P

1

of

71 77Tuesday, July 25, 2017

of

71 77Tuesday, July 25, 2017

of

71 77Tuesday, July 25, 2017

0.3(X02)

5

Input Current: 7A

1.5V*47.6A/0.85/12V=7

D D

B+

PL5100

EMI@

1 2

FBMA-L11-453215800LMA90T_2P

12

PC5110

PC5111

1U_0402_25V6K

EMI@

1000P_0402_50V7K

C C

B B

CPU_B+

12

PC5127

10U_0805_25V6K

+5VS

PWM1_VCORE<71>

PC5100

1 2

1U_0402_6.3V6K

1

+

PC5103

100U_25V_M

2

12

PC5105

PC5106

10U_0805_25V6K

FCCM_VCORE<71>

1_0402_5%

PR5100

1 2

12

PC5107

PC5108

10U_0805_25V6K

EMI@

0.1U_0402_25V6

PR5111,PR5136 pin1 要接到 PR5122 pin2 PR5112,PR5124 pin1 要接到 PR5134 pin2 PR5123,PR5135 pin1 要接到 PR5109 pin2

+5VS

PWM2_VCORE<71>

1_0402_5%

PR5115

PC5114

1 2

1U_0402_6.3V6K

12

PC5116

PC5117

10U_0805_25V6K

12

PC5119

PC5118

EMI@

10U_0805_25V6K

0.1U_0402_25V6

+5VS

PC5125

PR5127

1U_0402_6.3V6K

12

PC5128

PC5129

10U_0805_25V6K

1 2

12

PC5130

PC5131

EMI@

0.1U_0402_25V6

2200P_0402_50V7K

FCCM_VCORE

12

PC5122

PC5121

PC5120

1U_0402_25V6K

EMI@

1000P_0402_50V7K

2200P_0402_50V7K

PWM3_VCORE<71>

1_0402_5%

12

PC5133

PC5132

1U_0402_25V6K

EMI@

1000P_0402_50V7K

0.22U_0603_16V7K

PC5109

EMI@

2200P_0402_50V7K

FCCM_VCORE

4

PR5102 0_0402_5%@

1 2

PR5104 0_0402_5%@

1 2

PC5102

1 2

PR5105

2.2_0603_1%

PR5114 0_0402_5%@

1 2

PR5117 0_0402_5%@

1 2

PC5115

1 2

0.22U_0603_16V7K

1 2

PR5118

2.2_0603_1%

PR5126 0_0402_5%@

1 2

PR5129 0_0402_5%@

1 2

PC5126

1 2

0.22U_0603_16V7K

1 2

PR5130

2.2_0603_1%

PU5101

1

PWM

CGND

2

ZCD_EN#

GL

3

VCIN

DSBL#

4

CGND

THWn

5

BOOT

VDRV

6

NC

PGND

7

PHASE

GL

8

VIN

SW

9

VIN

SW

10

PGND

SW

11

SW

12

SW

13

SW

SW14SW

SIC632CDT1GE3_POWERPAK31_5X5

PU5102

1

PWM

CGND

2

ZCD_EN#

GL

3

VCIN

DSBL#

4

CGND

THWn

5

BOOT

VDRV

6

NC

PGND

7

PHASE

GL

8

VIN

SW

9

VIN

SW

10

PGND

SW

11

SW

12

SW

13

SW

SW14SW

SIC632CDT1GE3_POWERPAK31_5X5

PU5103

1

PWM

CGND

2

ZCD_EN#

GL

3

VCIN

DSBL#

4

CGND

THWn

5

BOOT

VDRV

6

NC

PGND

7

PHASE

GL

8

VIN

SW

9

VIN

SW

10

PGND

SW

11

SW

12

SW

13

SW

SW14SW

SIC632CDT1GE3_POWERPAK31_5X5

3

PC5101

PR5101

1 2

1_0402_5%

28

PR5103

1 2

27 26 25 24 23 22 21 20 19 18 17 16 15

28 27 26 25 24 23 22 21 20 19 18 17 16 15

10K_0402_1%

PR5116

1 2

28

PR5128

27 26 25 24 23 22 21 20 19 18 17 16 15

1 2

10K_0402_1%

12

PR5106

@EMI@

10_1206_5%

12

PC5112

@EMI@

33P_0603_50V8J

PR5113

1 2

1_0402_5%

10K_0402_1%

PR5125

1 2

1_0402_5%

12

PR5131

@EMI@

10_1206_5%

12

PC5134

@EMI@

33P_0603_50V8J

1U_0402_6.3V6K

ISUMP_VCORE

12

PR5121

10_1206_5%

@EMI@

12

PC5123

@EMI@

33P_0603_50V8J

1 2

PR5107

3.65K_0603_1%

1 2

PR5110

@

1 2

20M_0402_5%

1U_0402_6.3V6K

PR5119

3.65K_0603_1%

1 2

ISUMP_VCORE

PC5124

1 2

1U_0402_6.3V6K

PR5132

3.65K_0603_1%

1 2

ISUMP_VCORE

ISEN1_VCORE<71>

PC5113

1 2

ISEN2_VCORE<71>

ISEN3_VCORE<71>

CORE_V2N

CORE_V3N

<71>

VCC_CORE_PH1

100K_0402_1%

1 2

100K_0402_1%

VCC_CORE_PH2

100K_0402_1%

CORE_V1N

CORE_V3N

VCC_CORE_PH3

100K_0402_1%

CORE_V1N

CORE_V2N

PL5101

0.15UH_PCME064T-R15MS0R667_36A_ 20%

PR5108

@

PR5111

1 2

@

PR5112

1 2

PR5120

1 2

@

PR5123

100K_0402_1%

1 2

@

PR5124

100K_0402_1%

1 2

PR5133

1 2

@

PR5135

100K_0402_1%

1 2

@

PR5136

100K_0402_1%

1 2

12

CORE_V1N

PR5109

1 2

10_0402_1%

ISUMN_VCORE

PL5102

0.15UH_PCME064T-R15MS0R667_36A_ 20%

12

PR5122

PL5103

0.15UH_PCME064T-R15MS0R667_36A_ 20%

12

PR5134

2

+VCC_CORE TDC PL2 :50A Peak Current 70A OCP Current 82A DCR 0.66mohm +/-7% Load Line 1.8mV/A

1

TDC PL2 refer to EDS REV1.5

+VCC_CORE

<71>

CORE_V2N

1 2

10_0402_1%

ISUMN_VCORE

CORE_V3N

1 2

10_0402_1%

ISUMN_VCORE

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2016/01/06 2017/01/06

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

PWR_VCORE_+VCC_CORE

Size Document Number Rev

Date: Sheet of

LA-E992P

1

0.3(X02)

72 77Tuesday, July 25, 2017

5

4

3

2

1

Input Current: 5.66A

1.5V*38.5A/0.85/12V=5.66

PR5201

+5VS

PC5200

D D

1U_0402_6.3V6K

1 2

PWM1_GT<71>

FCCM_GT<71>

1_0402_5%

PR5200

1 2

CPU_B+

12

PC5205

PC5204

PC5203

10U_0805_25V6K~D

12

PC5206

EMI@

0.1U_0402_25V6

12

PC5207

PC5210

1U_0402_25V6K

EMI@

2200P_0402_50V7K

+5VS

C C

PC5212

1U_0402_6.3V6K

1 2

12

PC5217

PC5216

PC5218

10U_0805_25V6K

10U_0805_25V6K~D

12

PC5219

EMI@

0.1U_0402_25V6

PWM2_GT<71>

1_0402_5%

PR5214

1 2

12

PC5215

PC5214

PC5220

1U_0402_25V6K

EMI@

2200P_0402_50V7K

1000P_0402_50V7K

PC5208

EMI@

1000P_0402_50V7K

FCCM_GT

PR5202 0_0402_5%@

1 2

PR5204 0_0402_5%@

1 2

PC5202

1 2

0.22U_0603_16V7K

1 2

PR5205

2.2_0603_1%

PR5211 pin1 要接到 PR5221 pin2 PR5222 pin1 要接到 PR5209 pin2

PR5213 0_0402_5%@

1 2

PR5215 0_0402_5%@

1 2

PC5213

1 2

0.22U_0603_16V7K

1 2

PR5217

2.2_0603_1%

PU5201

1

PWM

2

ZCD_EN#

3

VCIN

4

CGND

5

BOOT

6

NC

7

PHASE

8

VIN

9

VIN

10

PGND

11

SW

12

SW

13

SW SW14SW

SIC632CDT1GE3_POWERPAK31_5X5

PU5202

1

PWM

2

ZCD_EN#

3

VCIN

4

CGND

5

BOOT

6

NC

7

PHASE

8

VIN

9

VIN

10

PGND

11

SW

12

SW

13

SW SW14SW

SIC632CDT1GE3_POWERPAK31_5X5

CGND

DSBL#

THWn VDRV PGND

CGND

DSBL#

THWn VDRV PGND

28 27

GL

26 25 24 23 22

GL

21

SW

20

SW

19

SW

18

SW

17

SW

16

SW

15

28 27

GL

26 25 24 23 22

GL

21

SW

20

SW

19

SW

18

SW

17

SW

16

SW

15

1 2

1_0402_5%

PR5203

1 2

10K_0402_1%

PR5212

1 2

1_0402_5%

PR5216

1 2

10K_0402_1%

PC5201

1 2

1U_0402_6.3V6K

12

PR5206

4.7_1206_5%

@EMI@

12

PC5209

@EMI@

680P_0603_50V7K

ISUMP_GT<71>

PC5211

1 2

1U_0402_6.3V6K

12

PR5218

4.7_1206_5%

@EMI@

12

PC5221

@EMI@

680P_0603_50V7K

+VCCGT

PL5201

VCC_GT_PH1

PR5207

3.65K_0603_1%

1 2

PR5210

@

1 2

20M_0402_5%

PR5219

3.65K_0603_1%

1 2

ISUMP_GT

ISEN1_GT<71>

GT_V2N

ISEN2_GT<71>

GT_V1N

PR5208

100K_0402_1%

1 2

@

100K_0402_1%

1 2

VCC_GT_PH2

PR5220

100K_0402_1%

1 2

@

100K_0402_1%

1 2

0.15UH_PCME064T-R15MS0R667_36A_20%

PR5211

PL5202

0.15UH_PCME064T-R15MS0R667_36A_20%

PR5222

12

GT_V1NGT_V2N

PR5209

1 2

10_0402_1%

ISUMN_GT<71>

12

PR5221

1 2

10_0402_1%

ISUMN_GT

+VCC_GT TDC PL2 :25A Peak Current 55A OCP Current 66A DCR 0.66mohm +/-7% Load Line 2.65mV/A

+VCC_SA TDC PL2 :10A Peak Current 11.1A OCP Current 13.32A DCR 6.2mohm +/-5% Load Line 9.1mV/A

Input Current: 0.8A

B B

1.05V*7.77A/0.85/12V=0.8

CPU_B+

FCCM_SA<71>

12

PC5224

PC5226

PC5225

PC5223

EMI@

0.1U_0402_25V6

A A

5

10U_0805_25V6K

2200P_0402_50V7K

PR5223 0_0402_5%@

1 2

PC5222

1 2

0.22U_0603_16V7K

1 2

PR5225

2.2_0603_1%

12

PC5228

PC5229

1U_0402_25V6K

EMI@

1000P_0402_50V7K

PC5230

4

SIC531CDT1GE3_POWERPAK22_4X3

1

ZCD_EN#

2

VCIN

3

CGND

4

BOOT

5

PHASE

6

VIN PGND7VSWH

PU5203

PR5229

1 2

1_0402_5%

1 2

1U_0402_6.3V6K

+5VS

CGND

PWM VDRV PGND

GL

PR5230

1 2

1_0402_5%

13

PR5224 0_0402_5%@

12

1 2 11 10 9 8

1 2

PC5231

1U_0402_6.3V6K

PWM_SA <71>

12

PR5226

4.7_1206_5%

@EMI@

12

ISUMP_SA<71>

ISUMN_SA<71>

PC5232

@EMI@

680P_0603_50V7K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

PL5203

0.47UH_MMD05CZR47M_12A_20%

1

4

3

2

12

PR5227

3.65K_0603_1%

PR5231

@

1 2

20M_0402_5%

2016/01/06 2017/01/06

PR5228

1 2

10_0402_1%

Compal Secret Data

Deciphered Date

+VCCSA

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

PWR_VCORE_+VCCGT,+VCCSA

LA-E992P

1

73 77Tuesday, July 25, 2017

of

0.3(X02)

5

4

3

2

1

Input Current:0.358A

0.95*3.85=3.6575W

3.6575/0.85/12V=0.358A

PJP4000

PC4004

EMI@

1000P_0402_50V7K

PR4003 0_0402_5%@

112

JUMP_43X39

1 2

@

2

@

PR4008 0_0402_5%

PR4011 0_0402_5%

B+_VCCIO

12

PC4001

0.22U_0402_10V6K

EMI@

0.1U_0402_25V6

12

PR4005

1M_0402_1%

ILMT_VCCIO

PC4002

10U_0805_25V6K

EN_VCCIO

+3VALW

12

PC4000

EMI@

2200P_0402_50V7K

12

PC4011

@

B+

12

D D

C C

PC4003

1U_0402_25V6K

EMI@

VCCIO_EN<43>

+3VALW

The current limit is set to 6A, 9A or 12A when this pin is pull low, floating or pull high.

PU4000

2

IN

3

IN

4

IN

5

IN

7

GND

8

GND

18

GND

11

EN

13

ILMT

15

BYP

SY8286RAC_QFN20_3X3

PC4014

1U_0603_6.3V6M

+VCCIO_PG<18>

9

PG

1

BS

6

LX

19

LX

20

LX

14

FB

VCC_VCCIO

17

VCC

10

NC

12

NC

16

NC

21

PAD

12

2.2U_0402_16V6K

FB_VCCIO

PC4012

PR4000 0_0603_5%

1 2

BST_VCCIOBS_VCCIO

10K_0402_5%

@

PR4001

12

PC4005

0.1U_0603_25V7K

1 2

+3VS

LX_VCCIO

12

PR4002

4.7_1206_5%

@EMI@

SNB_VCCIO

12

PC4013 680P_0603_50V7K

@EMI@

PL4000

1UH_PCMB042T-1R0MS_4.5A_20%

1 2

12

PC4010

Rup

12

Rdown

PR4009

35.7K_0402_1%

330P_0402_50V7K

PR4006

21K_0402_1%

+VCCIOP

12

PR4004

10_0402_1%

12

PC4006

22U_0603_6.3V6M

FB_VCCIO_SENSE

PJP4001

2

112

JUMP_43X118 @

+VCCIO

+VCCIOP

12

PC4007

22U_0603_6.3V6M

PC4009

PC4008

22U_0603_6.3V6M

PR4007 0_0402_5%@

1 2

PR4010 0_0402_5%@

1 2

+VCCIOP (0.95V) TDC 3.85 A Peak Current 5.5 A OCP Current 9 A Fix by IC FSW:500KHz TYP MAX DCR 24.0mohm 27.0mohm

VCCIO_SENSE <11>

VSSIO_SENSE <11>

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2016/01/06 2017/01/06

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

PWR_+VCCIO

LA-E992P

1

74 77Tuesday, July 25, 2017

0.3(X02)

of

A

+VCC_CORE

B

C

D

E

+VCC_CORE 330uF*1 220uF*2 22uF*15 1uF*6

1 1

2 2

.1uF*15

+VCCGT 470uF*1 330uF*1 47uF*9 22uF*26 1uF*6 .1uF*15

+VCCGT +VCCSA

1

+

PC5500

2

12

PC5503

12

1

+

PC5539

2

12

PC5553

1

+

PC5502

PC5501

2

330U_D3_2VM_R6M

12

22U_0603_6.3V6M

12

PC5518

1U_0402_6.3V6K

470U_D2_2VM_R4.5M

12

22U_0603_6.3V6M

220U_D7_2VM_R6M

12

PC5505

PC5504

22U_0603_6.3V6M

PC5519

1U_0402_6.3V6K

1

+

PC5540

2

330U_D3_2VM_R6M

PC5554

22U_0603_6.3V6M

PC5506

22U_0603_6.3V6M

12

PC5520

PC5521

1U_0402_6.3V6K

12

PC5541

PC5542

47U_0805_6.3V6M

12

PC5556

PC5555

22U_0603_6.3V6M

12

PC5507

22U_0603_6.3V6M

12

PC5522

1U_0402_6.3V6K

12

PC5543

47U_0805_6.3V6M

12

PC5557

22U_0603_6.3V6M

12

PC5509

PC5508

22U_0603_6.3V6M

PC5523

1U_0402_6.3V6K

PC5544

47U_0805_6.3V6M

PC5558

22U_0603_6.3V6M

PC5510

22U_0603_6.3V6M

12

PC5524

PC5525

.1U_0402_16V7K

12

PC5545

PC5546

47U_0805_6.3V6M

12

PC5559

PC5560

22U_0603_6.3V6M

12

PC5511

PC5512

22U_0603_6.3V6M

12

PC5527

PC5526

.1U_0402_16V7K

12

PC5547

PC5548

47U_0805_6.3V6M

12

PC5561

PC5562

22U_0603_6.3V6M

12

PC5513

PC5514

22U_0603_6.3V6M

12

PC5528

PC5529

.1U_0402_16V7K

PC5549

47U_0805_6.3V6M

12

PC5563

PC5564

22U_0603_6.3V6M

12

PC5515

22U_0603_6.3V6M

PC5530

.1U_0402_16V7K

PC5565

22U_0603_6.3V6M

PC5517

PC5516

22U_0603_6.3V6M

12

PC5531

.1U_0402_16V7K

PC5532

12

.1U_0402_16V7K

12

PC5534

PC5533

.1U_0402_16V7K

+VCCSA 47uF*3 22uF*9 .1uF*2

12

PC5535

.1U_0402_16V7K

12

PC5538

PC5537

PC5536

.1U_0402_16V7K

12

PC5552

PC5551

PC5550

47U_0603_6.3V6M

12

PC5566

22U_0603_6.3V6M

47U_0603_6.3V6M

12

PC5567

22U_0603_6.3V6M

PC5569

PC5568

22U_0603_6.3V6M

3 3

12

4 4

A

12

PC5570

PC5571

22U_0603_6.3V6M

12

PC5591

PC5590

1U_0402_6.3V6K

12

PC5596

PC5597

.1U_0402_16V7K

12

PC5572

PC5573

22U_0603_6.3V6M

12

PC5592

PC5593

1U_0402_6.3V6K

12

PC5598

PC5599

.1U_0402_16V7K

12

PC5574

PC5575

22U_0603_6.3V6M

12

PC5594

PC5595

1U_0402_6.3V6K

12

PC5601

PC5600

.1U_0402_16V7K

12

PC5576

PC5577

22U_0603_6.3V6M

12

PC5603

PC5602

.1U_0402_16V7K

B

12

PC5578

PC5579

22U_0603_6.3V6M

12

PC5604

PC5605

.1U_0402_16V7K

12

PC5580

PC5584

PC5587

22U_0603_6.3V6M

12

PC5606

PC5607

.1U_0402_16V7K

12

PC5610

PC5609

PC5608

.1U_0402_16V7K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2016/01/06 2017/01/06

12

PC5582

PC5581

22U_0603_6.3V6M

12

PC5588

PC5589

.1U_0402_16V7K

Compal Secret Data

Deciphered Date

12

PC5583

22U_0603_6.3V6M

PC5586

PC5585

22U_0603_6.3V6M

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

PWR_CPU DECOUPLING

LA-E992P

75 77Tuesday, July 25, 2017

E

0.3(X02)

+NVVDD1

5

4

3

2

1

1U_0402_6.3V6K

PC6500

D D

12

1U_0402_6.3V6K

PC6501

12

1U_0402_6.3V6K

PC6502

12

PC6503

12

1U_0402_6.3V6K

PC6505

PC6504

12

1U_0402_6.3V6K

PC6506

12

1U_0402_6.3V6K

PC6507

12

PC6508

12

1U_0402_6.3V6K

PC6510

PC6509

12

1U_0402_6.3V6K

PC6512

PC6511

12

+NVVDD 470uF X 1 330uF X 2 47uF_0805 X 3

1U_0402_6.3V6K

PC6514

PC6513

12

1U_0402_6.3V6K

PC6526

12

C C

12

B B

PC6527

12

1U_0402_6.3V6K

PC6539

PC6540

12

1U_0402_6.3V6K

PC6553

PC6552

12

10U_0603_6.3V6M

PC6566

PC6565

12

10U_0603_6.3V6M

PC6578

PC6579

12

1U_0402_6.3V6K

PC6515

12

1U_0402_6.3V6K

PC6528

12

1U_0402_6.3V6K

PC6541

12

1U_0402_6.3V6K

PC6554

12

10U_0603_6.3V6M

PC6567

12

22U_0805_6.3VAM

1

PC6580

2

1U_0402_6.3V6K

PC6516

12

1

2

PC6517

12

1U_0402_6.3V6K

PC6529

PC6530

12

1U_0402_6.3V6K

PC6542

PC6543

12

1U_0402_6.3V6K

PC6556

PC6555

12

10U_0603_6.3V6M

PC6568

PC6569

12

22U_0805_6.3VAM

1

PC6581

PC6582

2

1U_0402_6.3V6K

PC6519

PC6518

12

1U_0402_6.3V6K

PC6532

PC6531

12

1U_0402_6.3V6K

PC6544

12

1

2

PC6545

12

1U_0402_6.3V6K

PC6558

PC6557

12

10U_0603_6.3V6M

PC6571

PC6570

12

22U_0805_6.3VAM

47U_0805_6.3V6M

PC6584

12

PC6583

1U_0402_6.3V6K

PC6520

12

1U_0402_6.3V6K

PC6533

12

1U_0402_6.3V6K

PC6546

12

1U_0402_6.3V6K

PC6559

12

10U_0603_6.3V6M

PC6572

12

47U_0805_6.3V6M

PC6585

12

1U_0402_6.3V6K

PC6521

12

PC6522

12

1U_0402_6.3V6K

PC6534

PC6535

12

1U_0402_6.3V6K

PC6548

PC6547

12

1U_0402_6.3V6K

PC6561

PC6560

12

10U_0603_6.3V6M

PC6574

PC6573

12

330U_D3_2VM_R6M

47U_0805_6.3V6M

1

PC6587

PC6586

+

2

1U_0402_6.3V6K

PC6523

12

1U_0402_6.3V6K

PC6536

12

1U_0402_6.3V6K

PC6549

12

1U_0402_6.3V6K

PC6562

12

10U_0603_6.3V6M

PC6575

12

470U_D2_2VM_R4.5M~D

1

PC6588

+

2

1U_0402_6.3V6K

PC6524

12

1

+

2

PC6525

12

1U_0402_6.3V6K

PC6538

PC6537

12

1U_0402_6.3V6K

PC6550

PC6551

12

1U_0402_6.3V6K

PC6564

PC6563

12

10U_0603_6.3V6M

PC6577

PC6576

12

330U_D3_2VM_R6M

PC6589

22uF_0805 X 4 10uF_0603X 15 1uF_0402 X 65

A A

Security Classification

2015/09/18 2016/09/18

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2015/09/18 2016/09/18

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

VGA DECOUPLING

LA-E992P

70 77Tuesday, July 25, 2017

1

0.3(X02)

5

4

3

2

1

Version Change List ( P. I. R. List )

Item Issue

D D

60 CHARGER 2017/01/09 Compal_PWR

1

69 +1.35VRAM 2017/01/09 Compal_PWR

2

65 +1.8VGSP 2017/01/09 Compal_PWR 1. Change PC18V09 form 0.1u(@)F to 0.1uF.

3

61,64 +3/+5VALWP & +1VALWP 2017/02/13 Compal_PWR

4

67 VGA_UP9511 2017/02/17 Compal_PWR

5

59 DCIN / BATT CONN /OTP 2017/02/22 Compal_PWR

6

C C

59,60 DCIN / BATT CONN /OTP

7

60 Charger 2017/03/03 Compal_PWR 0.11. add PR734 100K Ohm on siganal AC_DIS

8

66 +1.0VS_VGA 2017/03/03 Compal_PWR 0.1Follow EE's request,change enable siganl. 1. Change net name from NVVDD1_EN to PEX_VDD_EN.

9

60

10

& Charger

Charger

Date Request Owner

Description

Modify ILMT.

For BOM control 0.1

For EE request to add capacitor for avoiding noise

Avoid to use Samsung Capcitor in common part, change to independent P/N.

Avoid 5VCC leakage issue, so we amplify the divider resistance

Follow EE's request,use the same part with EE.

2017/03/02 Compal_PWR Follow Dell &EC request,change I_ADP 's net name. 1. Change net name from I_ADP to I_ADP_R 0.1

Before EC program,AC_DIS is floating. Avoid the siganal forcing PQ708 open quickly, add pull down resistor on AC_DIS siganal.

2017/03/06 Compal_PWR Follow sourcer request,change PD part. 1. Change PD700 from SCS00005400 to SCS00003800. 0.1

1. Change PR714 from 20K(@) Ohm to 20K Ohm.

2. Change PR715 from 1.17K(@) Ohm to 5.76K Ohm

1. Add PR812 of 35.7k Ohm for S6G@

2. Add PR812 of 35.7k Ohm for H6G@

3. Add PR812 of 47.5k Ohm for M6G@

1. Change PC103,PC104,PC301,PC302,PC307,PC308 from SE00000QK00 to SE00000QK0L

1. Change PR6000 form 10K Ohm to 100K Ohm

2. Change PR6006 from 91K Ohm to 910K Ohm

1. Change PQ6 from SB00000DH00 to SB00000ZU00

2. Change PQ7 from SB00000I700 to SB00000ZU00

Page 1

Solution Description

Rev.Page# Title

0.1

69 +1.35VRAM 2017/03/07 Compal_PWR The VRAM voltage will switch between 1.5V and 1.35V,

11

B B

A A

65 +1.8VGSP 2017/03/14 Compal_PWR Follow EE's request,modify output voltage to solve 1.8VS

12

61 +3/+5VALWP 2017/03/14 Compal_PWR Follow EE's request,modify output voltage to solve

13

69 +1.35VRAM 2017/03/14 Compal_PWR The VRAM voltage will switch between 1.5V and 1.35V,

14

69 1.Change PQ802 from SB00000ST00 to SB00000T000.Avoid the mos PQ802 won't open,so we change the lower

15

59 DCIN / BATT CONN /OTP 2017/03/16 Compal_PWR 1.Change PD1's Pin2 from PSID-0 to PSID.Dell request us to change PD1 's position. 0.1

16

71 VCORE-ISL95829 Compal_PWR2017/03/20 1. Change PR5041 from 267 ohm to 287 ohm.

17

69 +1.35VRAM 2017/03/23 Compal_PWR Because FBVDDQ transient noise issue,so we follow

18

5

+1.35VRAM 2017/03/14 Compal_PWR 0.1

4

there will be a overshoot voltage.To solve this issue, we add 1K ohm and 47nF.

drop test.

TypeC VBUS drop test.

there will be a overshoot voltage.To solve this issue, we add 49.9 ohm and 1.5nF.

Vth 's Mos (Vth=1.5V)

After CPU VRTT Test,we tune some resistor&capcitor.

EE's request,remove 220uF*1 output cap.

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2. add 47nF PC813 from PQ802 gate to source.

1. Change PR18V02 from 20K ohm to 20.5K ohm 0.1

1. Change PR301 from 15K ohm to 15.4K ohm 0.1

1. add PC814 and PR815 parallel with PR807. 0.1

2. Change PC5031 from 4700 pF to 2200 pF.

3. Change PR5051 from 4.87K ohm to 3.65K ohm.

4. Change PC5034 from 470 pF to 100 pF.

5. Change PC5018 from 33 nF to 68 pF.

1. Change PC811 220uF to 220uF(@) 0.1

Compal Secret Data

2011/06/02 2013/10/28

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Date: Sheet

0.11. Change PR810 from 0 ohm to 1K ohm

0.1

Compal Electronics, Inc.

NOTE

LA-E992P

1

76 77Tuesday, July 25, 2017

0.3(X02)

of

5

4

3

2

1

Version Change List ( P. I. R. List )

Item Issue

73 VCORE_+VCCGT_+VCCSA 2017/05/05 Because VCCSA's Choke DCR value would impact VRTT test result,

D D

C C

1

61

2

69

3

4

5

+3VALWP 2017/05/08

VCORE_ISL9582971 2017/05/08 Modify VCCSA IMON resistor.

DCIN 2017/05/0859 Because DC-IN Cable is hard to plug and pull,we change

6

59 DCIN / BATT CONN / OTP 2017/05/11

7

59~74 2017/06/22 For schematic cost downAll page

8

69 +1.35VRAM 2017/06/22 Compal_PWR The VRAM voltage will switch between 1.5V and 1.35V,

9

Date Request Owner

Compal_PWR

2017/05/08+1.35VRAM

Compal_PWR

Description

so we choose SH000015M00 and SH000015P00 with same DCR value as main and 2nd source.

Modify +3VALWP OCP resistor.

Modify +1.35VRAM OCP resistor.

dc-in beed from 2 pcs to 3 pcs.

Add another circuit to pull down the GPU power level.

there will be a overshoot voltage.To solve this issue, we add 49.9 ohm and 820pF.

Page 2

Solution Description

1. Change PL5203 from SH00000T500 to SH000015M00.

1. Change PR304 from 8.87K ohm to 6.19K ohm.

1. Change PR802 from 30.9K ohm to 42.2K ohm.

1. Change PR5024 from 1.27K ohm to 1.1K ohm.

1. Change PL1/PL2 from SM010008E10 to SM01000C000.

2. Add PL6=SM01000C000.

1. Change PC12 from 1uF to 0.1uF. 0.2DCIN59 2017/05/10 Adjust the battery unplug prochot delay time.

1. Add PC16 0.1uF

2. Add PQ9=SB00000ST00.

3. Add PR34 0 ohm.

4. Add PR35 100Kohm.

PR6070,PR6035,PR5028,PR814,PR5011,PR6021,PR6018,PR101,PR103, PR5129,PR5213,PR705,PR732,PR5117,PR6026,PR5006,PR5102,PR731, PR5023,PR6060,PR727,PR6041,PR6045,PR5202,PR5215,PR4007,PR5020, PR5114,PR4003,PR5000,PR5005,PR5008,PR5224,PR5204,PR312,PR4010, PR5223,PR5009,PR5104,PR10V4,PR24,PR18V00,PR209,PR311,PR25,PR5126, PR211,PR25V00,PR18V07,PR6053,PR34 from 0 ohm to shortpad.

1. add PC814 and PR815 parallel with PR807. 1.0

Rev.Page# Title

0.2

1.01.Change PR721,PR706,PR723,PR730,PR733,PR6069,PR315,PR6051,

69 +1.35VRAM 2017/07/11 Modify OCP resistor. 1.Change from 42.2Kohm to 30.9Kohm. 1.0

10

61 +5VALWP 2017/07/11 Modify OCP resistor. 1.Change from 16.5Kohm to 10.5Kohm. 1.0

B B

11

12

13

14

15

16

A A

17

5

Compal_PWR

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/06/02 2013/10/28

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

NOTE

LA-E992P

1

0.3(X02)

77 77Tuesday, July 25, 2017

of

Compal LA-E992P Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual