Compal LA-E992P Schematics Rev1.0

A

B

C

D

E

MODEL NAME :

PCB NO :

LA-E992P

CKF50/CKA50

BOM P/N :

1 1

451A7631L51 451A7631L52 451A7631L01 451A7631L02

Dell/Compal Confidential

Schematic Document

KABYLAKE-H

2 2

N17E

Firestar/Armani

2017-07-25

Rev: 1.0 (A00)

3 3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2011/08/25 2011/08/25

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Cover Page

LA-E992P

E

1.0(A00)

1 77Tuesday, July 25, 2017

1.0(A00)

A

256M*32 x6 =6G

VRAM * 6 GDDR5

B

C

D

E

P28

P33P33

P29

P23

P17

P27

GB4-256

P46-55

P39~40

PEG 3.0 x16

DDI3 x2

P35

DDI1 x4 DDI2 x4

PCI-E x4

Port 1-Port 4

PCI-E x1

Port 6

PCI-E x1

Port 5

PCI-E x4

Port 9-Port 12

SATA0A

SATA1B

HD Audio

SPI

SMBus

I2C

Intel

KBL-Lake-H

Processor

45W

BGA

DMI x4

100MHz 5GB/s

Intel

KBL-H-PCH

BGA 837 Balls

HM175

P7-13

P16-22

DDR4 ChannelA DDR4 ChannelB

eDP1.4 x4

USB2.0

Port 1

USB3.0

Port 1

USB Powershare TPS2544

USB 3.0 Re-driver PS8713

USB2.0 USB3.0

USB2.0

USB2.0 SD3.0

Port 7

Card Reader 2 in 1 RTS5176E SD / MS

USB2.0

Port 8

HDMI 2.0 Conn.

1 1

P45

Retimer PS8409A

CRT Conn.

P44

IFPHDMI2.0

P35

GPU N17E-G1

DP to VGA RTD2166-CG

CIO/USB3.1

USB3.1 TypeC

2 2

3 3

P41

USB2.0/CC

Main SPKR *2

Universal Audio Jack

TPS65982D

RJ45

P24

P41

I2C/USB2.0

TPM NPCT650VBCYX

Thunderbolt Alpine Ridge-SP

M.2 Slot A Key-E

(WLAN+BT4.0)

LOM RTL8111H

M.2 Slot C Key-M

(SATA/PCIe SSD)

HDD Conn.

HDA Codec ALC3246

SPI Flash (BIOS 16MB)

DDRIV-DIMM X2

1.2V DDR4 2400 MHz

P14-15

32GB Max

15.6'' HD/FHD / UHD

P31

P31 P31

Port 2 Port 2

Port 3 Port 3

Port 12

Port 4

Port 9

P34 P34

P38

USB 3.0

Type-A

USB 3.0

Type-A

USB 3.0

Type-A

Digital Camera Conn.

M.2 Slot A Key-EUSB2.0

(WLAN+BT4.0)

Touch Panel Conn.

Touch Finger Print w/ power button Conn.

Left

Right

P32

Right

P32

P38

P28

P38

P37

Power Button Board

MEC1416

KBC

SMBus

C

eSPI

P36

Charger & Battery

PWM

I2C

FAN

P26

Thermal Sensor F75303M

KB Conn.

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

P27

P25

AC Adaptor

P59P59/P60

Compal Secret Data

2011/08/25 2011/08/25

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Block diagram

Size Document Number Rev

Date: Sheet of

E

LA-E992P

2 77Tuesday, July 25, 2017

1.0(A00)

FFS LNG2DMTR

4 4

P29

Touch Pad

LED

PS2

P26

P37

LED Board

Power Button

P37

Power Button Board

A

B

A

B

C

D

E

Compal Confidential

Project Code : File Name :

1 1

ME Hole Location

M/B

2 2

3 3

Base on ME 0505

LED Board PWB Board

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/08/25 2012/07/25

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

DB block diagram

LA-E992P

1.0(A00)

3 77Tuesday, July 25, 2017

E

Vinaﬁx.com

A

Refer Page 36

PCI EXPRESS

Lane 1

Lane 2

Lane 3

Lane 4

Lane 5

Lane 6

Lane 7

Lane 8 None

Lane 9

Lane 10

Lane 11

DESTINATION

Alpine Ridge - SP

LOM

NGFF - WLAN + BT

None

NGFF - SSD

7

8

9

10

SATA

0A

1A

DESTINATIONUSB3

None

DESTINATION

NGFF - SSD

None

Lane 12

Lane 13

Lane 14

Lane 15

Lane 16

1 1

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

None

DESTINATIONCLK_PCIE

None

LOM

NGFF - WLAN + BT

None

Alpine Ridge - SP

NGFF - SSD

GPU

None

0B

2

3

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

None

HDD1B

None

DESTINATIONCLK_REQ

None

LOM

NGFF - WLAN + BT

None

Alpine Ridge - SP

NGFF - SSD

GPU

None

USB2 DESTINATION

1

USB JUSB3 (Left Side)

2

USB JUSB1 (Right Side)

3

USB JUSB2 (Right Side)

4

NGFF - WLAN + BT

None

5

6

None

7

CARD READER

8

Finger Print

9

Touch screen

10

11

12

None

CAMERA

Symbol Note :

: means Digital Ground

: means Analog Ground

USB31DESTINATION

USB JUSB3 (Left Side)

2

USB JUSB1 (Right Side)

3

USB JUSB2 (Right Side)

4

None

5

None

6

None

DDI

1

2

3

DESTINATION

Alpine Ridge

DP to VGA

Board ID

X00

X01

X02

X03

A00

Resistor

10K

17.8K

27K

37.4K

49.9K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/08/25 2012/07/25

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Notes List

Size Document Number Rev

LA-E992P

Date: Sheet of

1.0(A00)

4 77Tuesday, July 25, 2017

5

4

3

2

1

1K

Address: 0x88/0x89

Host

AW44

BB43

D D

AY44

BB39

Host

AR41

AR44

SMBCLK SMBDATA

SML0_SMBCLK SML0_SMBDATA

I2C1_SCK_TP I2C1_SDA_TP

1K

499

2.2K

+3VALW

+3VS

DMN65D8L

+3VALW

+3VS

DMN65D8L

1K

PCH_SMBCLK PCH_SMBDATA

2.4K

I2C1_SCK_TP_C I2C1_SDA_TP_C

+3VS

+3VS_TP

Slave

DIMMA

Slave

DIMMB

Slave

FFS

Slave

RTD2166

Slave

Touch Pad

Address: 0xA0/0xA1

Address: 0xA4/0xA5

Address: 0x52/0x53

Address: 0x64/0x65, 0x68/0x69

Address: 0x2C/0x2D

PCH

C C

2.2K

Slave

AW42

AW45

GPU_THM_SMBCLK GPU_THM_SMBDAT

B B

Host

+3VALW_EC

+3VS

DMN65D8L

ALL_GPWRGD

DMN65D8L

4.7K

PBAT_CHG_SMBCLK

MEC1416

Host

PBAT_CHG_SMBDAT

Host

TYPEC_SMBCLK

2.2K

0 Ohm

TYPEC_SMBDA

A A

0 Ohm

10K

1.8K

+3VALW_EC

+3VS

THM_SML1_CLK THM_SML1_DATA

+1V8_AON

VGA_SMB_CK2 VGA_SMB_DA2

Slave

BATT

Slave

CHAGER

PD_I2C_SCL_R PD_I2C_SDA_R

Slave

Thermal Sensor

Slave

GPU

Address: 0x16/0x17

Address: 0x12/0x13

10K(@)

Address: 0x9A/0x9B

Address: 0x9E/0x9F

+3VS

Slave

TPS65982D

Address: 0x70/0x71

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/08/25 2012/07/15

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

SMBus Block Diagram

Size Document Number Rev

Custom

Date: Sheet of

LA-E992P

1

5 77Tuesday, July 25, 2017

1.0(A00)

5

+VCCST

D D

+VCCSTG

+1V_PCH

C C

+3VALW

+VCCIO

+3V_ROM

+3V_PCH_DSW

B B

1 2

RH97 51_0402_5%@

1 2

RH98 51_0402_5%@

1 2

RH100 51_0402_5%@

1 2

RH497 51_0402_5%

1 2

RH496 51_0402_5%

1 2

RH56 51_0402_5%

1 2

RH95 51_0402_5%

1 2

RH61 51_0402_5%

1 2

RH60 51_0402_5%

1 2

RH520 2.2K_0402_5%

1 2

RH521 2.2K_0402_5%

1 2

RH526 150_0402_5%

1 2

RH540 1K_0402_5%XDP@

1 2

RH529 1K_0402_5%XDP@

+3VS

1 2

RH531 1K_0402_5%

0.1U_0402_10V7K

PCH_JTAG_TDO

PCH_JTAG_TMS

PCH_JTAG_TDI

CPU_XDP_TDO

CPU_XDP_TMS

CPU_XDP_TDI

PCH_JTAG_TCK

CPU_XDP_TCK

CPU_XDP_TRST#

XDP_PLTRST#

PCH_SYS_PWROK_XDP

PWR_DEBUG#_XDP

XDP_PRESENT#

XDP_DBRESET# SYS_RESET#

XDP@

1

CH206

2

1 2

RH528 1K_0402_5%

1 2

RH519 1K_0402_5%XDP@

1 2

RH530 0_0402_5%@

Pilot Change RH530 to 0ohm 0402 short-pad footprint.

1 2

RH532 0_0402_5%@

XDP@

1

CH207

0.1U_0402_10V7K

2

4

CFG0

PCH_SPI_WP#

SIO_PWRBTN#PWRBTN#_XDP

DVT2.0 Change RH532 to 0ohm 0402 short-pad footprint.

PCH_SPI_WP# <17>

SIO_PWRBTN# <18,36>

SYS_RESET# <18>

3

PCH_ITP_PMODE<18>

PLTRST_CPU#<9,16>

SYS_PWROK<18,36>

PCH_SPI_SI<17,27>

PCH_RSMRST#<18,36>

H_VCCST_PWRGD<9,18>

CFG[0..19]<9>

CFG3

RH517 1K_0402_5%XDP@

XDP_PREQ#<9,22>

XDP_PRDY#<9,22>

XDP_BPM#0<9> XDP_BPM#1<9>

PCH_SMBDATA<14,15,18,29,35>

PCH_SMBCLK<14,15,18,29,35>

PCH_JTAG_TCK<18> CPU_XDP_TCK<9,18>

PCH_ITP_PMODE

PLTRST_CPU# XDP_PLTRST#

SYS_PWROK

PCH_SPI_SI PCH_SYS_PWROK_XDP

PCH_RSMRST#

H_VCCST_PWRGD XDP_PWRGOOD

12

XDP_PREQ# XDP_PRDY#

CFG0 CFG1

CFG2 CFG3

XDP_BPM#0 XDP_BPM#1

CFG4 CFG5

CFG6 CFG7

XDP_PWRGOOD PWRBTN#_XDP

PWR_DEBUG#_XDP PCH_SYS_PWROK_XDP

PCH_SMBDATA PCH_SMBCLK PCH_JTAG_TCK CPU_XDP_TCK

RH518

0_0402_5%

2

1 2

RH522 0_0402_5%XDP@

1 2

RH523 1K_0402_5%@

1 2

RH524 0_0402_5%@

1 2

RH525 1K_0402_5%XDP@

1 2

RH541 1K_0402_5%XDP@

1 2

RH542 1K_0402_5%@

+1V_PCH +1V_PCH

JXDP1

2

112

4

334

6

556

8

778

10

9910

12

111112

14

131314

16

151516

18

171718

20

191920

22

212122

24

232324

26

252526

28

272728

30

292930

32

313132

34

333334

36

353536

38

373738

40

393940

42

414142

44

434344

46

454546

48

474748

50

494950

52

515152

54

535354

56

555556

58

575758

60

12

@

595960

SAMTE_BSH-030-01-L-D-A-TR

CONN@

CFG17 CFG16

CFG8 CFG9

CFG10 CFG11

CFG19 CFG18

CFG12 CFG13

CFG14 CFG15

PCH_XDP_CLK_P PCH_XDP_CLK_N

XDP_PLTRST# XDP_DBRESET#

XDP_TDO XDP_TRST# XDP_TDI XDP_TMS XDP_PRESENT#

1

PCH_XDP_CLK_P <17> PCH_XDP_CLK_N <17>

XDP@

1

CH205

0.1U_0402_10V7K

2

XDP_TDO

XDP_TDI

XDP_TMS

XDP_TRST#

A A

5

Pilot Change RH533, RH534, RH535, RH536 to 0ohm 0402 short-pad footprint.

1 2

RH533 0_0402_5%@

1 2

RH534 0_0402_5%@

1 2

RH535 0_0402_5%@

1 2

RH536 0_0402_5%@

CPU_XDP_TDO

CPU_XDP_TDI

CPU_XDP_TMS

CPU_XDP_TRST#

4

CPU PCH

CPU_XDP_TDO <9>

CPU_XDP_TDI <9>

CPU_XDP_TMS <9>

CPU_XDP_TRST# <9,22>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

XDP_TMS

XDP_TDI

XDP_TDO PCH_JTAG_TDO

Pilot Change RH538, RH537, RH539 to 0ohm 0402 short-pad footprint.

2011/08/25 2012/07/25

1 2

RH538 0_0402_5%@

1 2

RH537 0_0402_5%@

1 2

RH539 0_0402_5%@

Compal Secret Data

Deciphered Date

PCH_JTAG_TMS

PCH_JTAG_TDI

2

PCH_JTAG_TMS <18>

PCH_JTAG_TDI <18>

PCH_JTAG_TDO <18>

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

XDP CONN

LA-E992P

1

1.0(A00)

6 77Tuesday, July 25, 2017

5

4

3

2

1

PEG_HTX_C_GRX_P[0..15]<46>

PEG_HTX_C_GRX_N[0..15]<46>

PEG_GTX_C_HRX_P[0..15]<46>

PEG_GTX_C_HRX_N[0..15]<46>

D D

C C

B B

A A

PEG_HTX_C_GRX_P[0..15]

PEG_HTX_C_GRX_N[0..15]

PEG_GTX_C_HRX_P[0..15]

PEG_GTX_C_HRX_N[0..15]

TBT-AR

DP to VGA

PEG_GTX_C_HRX_P15 PEG_GTX_C_HRX_N15

PEG_GTX_C_HRX_P14 PEG_GTX_C_HRX_N14

PEG_GTX_C_HRX_P13 PEG_GTX_C_HRX_N13

PEG_GTX_C_HRX_P12 PEG_GTX_C_HRX_N12

PEG_GTX_C_HRX_P11 PEG_GTX_C_HRX_N11

PEG_GTX_C_HRX_P10 PEG_GTX_C_HRX_N10

PEG_GTX_C_HRX_P9 PEG_GTX_C_HRX_N9

PEG_GTX_C_HRX_P8 PEG_GTX_C_HRX_N8

PEG_GTX_C_HRX_P7 PEG_GTX_C_HRX_N7

PEG_GTX_C_HRX_P6 PEG_GTX_C_HRX_N6

PEG_GTX_C_HRX_P5 PEG_GTX_C_HRX_N5

PEG_GTX_C_HRX_P4 PEG_GTX_C_HRX_N4

PEG_GTX_C_HRX_P3 PEG_GTX_C_HRX_N3

PEG_GTX_C_HRX_P2 PEG_GTX_C_HRX_N2

PEG_GTX_C_HRX_P1 PEG_GTX_C_HRX_N1

PEG_GTX_C_HRX_P0

RH24

24.9_0402_1%

PEG_GTX_C_HRX_N0

PEG_RCOMP

DMI_CRX_PTX_P0 DMI_CRX_PTX_N0

DMI_CRX_PTX_P1 DMI_CRX_PTX_N1

DMI_CRX_PTX_P2 DMI_CRX_PTX_N2

DMI_CRX_PTX_P3 DMI_CRX_PTX_N3

CPU_DDI1_P0 CPU_DDI1_N0 CPU_DDI1_P1 CPU_DDI1_N1 CPU_DDI1_P2 CPU_DDI1_N2 CPU_DDI1_P3 CPU_DDI1_N3

DDI1_AUXP DDI1_AUXN

CPU_DDI2_P0 CPU_DDI2_N0 CPU_DDI2_P1 CPU_DDI2_N1 CPU_DDI2_P2 CPU_DDI2_N2 CPU_DDI2_P3 CPU_DDI2_N3

DDI2_AUXP DDI2_AUXN

CPU_DDI3_P0 CPU_DDI3_N0 CPU_DDI3_P1 CPU_DDI3_N1

DDI3_AUXP DDI3_AUXN

+VCCIO

1 2

DMI_CRX_PTX_P0<19> DMI_CRX_PTX_N0<19>

DMI_CRX_PTX_P1<19> DMI_CRX_PTX_N1<19>

DMI_CRX_PTX_P2<19> DMI_CRX_PTX_N2<19>

DMI_CRX_PTX_P3<19> DMI_CRX_PTX_N3<19>

CPU_DDI1_P0<39> CPU_DDI1_N0<39> CPU_DDI1_P1<39> CPU_DDI1_N1<39> CPU_DDI1_P2<39> CPU_DDI1_N2<39> CPU_DDI1_P3<39> CPU_DDI1_N3<39>

DDI1_AUXP<39> DDI1_AUXN<39>

CPU_DDI2_P0<39> CPU_DDI2_N0<39> CPU_DDI2_P1<39> CPU_DDI2_N1<39> CPU_DDI2_P2<39> CPU_DDI2_N2<39> CPU_DDI2_P3<39> CPU_DDI2_N3<39>

DDI2_AUXP<39> DDI2_AUXN<39>

CPU_DDI3_P0<35> CPU_DDI3_N0<35> CPU_DDI3_P1<35> CPU_DDI3_N1<35>

DDI3_AUXP<35> DDI3_AUXN<35>

E25 D25

E24 F24

E23 D23

E22 F22

E21 D21

E20 F20

E19 D19

E18 F18

D17 E17

F16 E16

D15 E15

F14 E14

D13 E13

F12 E12

D11 E11

F10 E10

G2

D8

E8

E6 F6

D5

E5

J8 J9

K36 K37 J35

J34 H37 H36

J37 J38

D27

E27

H34 H33

F37 G38

F34

F35

E37

E36

F26

E26

C34 D34

B36

B34

F33

E33 C33

B33

A27

B27

UH1C

PEG_RXP[0] PEG_RXN[0]

PEG_RXP[1] PEG_RXN[1]

PEG_RXP[2] PEG_RXN[2]

PEG_RXP[3] PEG_RXN[3]

PEG_RXP[4] PEG_RXN[4]

PEG_RXP[5] PEG_RXN[5]

PEG_RXP[6] PEG_RXN[6]

PEG_RXP[7] PEG_RXN[7]

PEG_RXP[8] PEG_RXN[8]

PEG_RXP[9] PEG_RXN[9]

PEG_RXP[10] PEG_RXN[10]

PEG_RXP[11] PEG_RXN[11]

PEG_RXP[12] PEG_RXN[12]

PEG_RXP[13] PEG_RXN[13]

PEG_RXP[14] PEG_RXN[14]

PEG_RXP[15] PEG_RXN[15]

PEG_RCOMP

DMI_RXP[0] DMI_RXN[0]

DMI_RXP[1] DMI_RXN[1]

DMI_RXP[2] DMI_RXN[2]

DMI_RXP[3] DMI_RXN[3]

SKL-H_BGA1440

@

UH1D

DDI1_TXP[0] DDI1_TXN[0] DDI1_TXP[1] DDI1_TXN[1] DDI1_TXP[2] DDI1_TXN[2] DDI1_TXP[3] DDI1_TXN[3]

DDI1_AUXP DDI1_AUXN

DDI2_TXP[0] DDI2_TXN[0] DDI2_TXP[1] DDI2_TXN[1] DDI2_TXP[2] DDI2_TXN[2] DDI2_TXP[3] DDI2_TXN[3]

DDI2_AUXP DDI2_AUXN

DDI3_TXP[0] DDI3_TXN[0] DDI3_TXP[1] DDI3_TXN[1] DDI3_TXP[2] DDI3_TXN[2] DDI3_TXP[3] DDI3_TXN[3]

DDI3_AUXP DDI3_AUXN

SKL-H_BGA1440

@

SKYLAKE_HALO

3 OF 14

SKYLAKE_HALO

4 OF 14

Rev_1.0

PEG_TXP[0] PEG_TXN[0]

PEG_TXP[1] PEG_TXN[1]

PEG_TXP[2] PEG_TXN[2]

PEG_TXP[3] PEG_TXN[3]

PEG_TXP[4] PEG_TXN[4]

PEG_TXP[5] PEG_TXN[5]

PEG_TXP[6] PEG_TXN[6]

PEG_TXP[7] PEG_TXN[7]

PEG_TXP[8] PEG_TXN[8]

PEG_TXP[9] PEG_TXN[9]

PEG_TXP[10] PEG_TXN[10]

PEG_TXP[11] PEG_TXN[11]

PEG_TXP[12] PEG_TXN[12]

PEG_TXP[13] PEG_TXN[13]

PEG_TXP[14] PEG_TXN[14]

PEG_TXP[15] PEG_TXN[15]

DMI_TXP[0] DMI_TXN[0]

DMI_TXP[1] DMI_TXN[1]

DMI_TXP[2] DMI_TXN[2]

DMI_TXP[3] DMI_TXN[3]

Rev_1.0

EDP_TXP[0] EDP_TXN[0] EDP_TXP[1] EDP_TXN[1] EDP_TXN[2] EDP_TXP[2] EDP_TXN[3] EDP_TXP[3]

EDP_AUXP

EDP_AUXN

EDP_DISP_UTIL

EDP_RCOMP

PROC_AUDIO_CLK

PROC_AUDIO_SDI

PROC_AUDIO_SDO

PEG_HTX_GRX_P15

B25

PEG_HTX_GRX_N15

A25

PEG_HTX_GRX_P14

B24

PEG_HTX_GRX_N14

C24

PEG_HTX_GRX_P13

B23

PEG_HTX_GRX_N13

A23

PEG_HTX_GRX_P12

B22

PEG_HTX_GRX_N12

C22

PEG_HTX_GRX_P11

B21

PEG_HTX_GRX_N11

A21

PEG_HTX_GRX_P10

B20

PEG_HTX_GRX_N10

C20

PEG_HTX_GRX_P9

B19

PEG_HTX_GRX_N9

A19

PEG_HTX_GRX_P8

B18

PEG_HTX_GRX_N8

C18

PEG_HTX_GRX_P7

A17

PEG_HTX_GRX_N7

B17

PEG_HTX_GRX_P6

C16

PEG_HTX_GRX_N6

B16

PEG_HTX_GRX_P5

A15

PEG_HTX_GRX_N5

B15

PEG_HTX_GRX_P4

C14

PEG_HTX_GRX_N4

B14

PEG_HTX_GRX_P3

A13

PEG_HTX_GRX_N3

B13

PEG_HTX_GRX_P2

C12

PEG_HTX_GRX_N2

B12

PEG_HTX_GRX_P1

A11

PEG_HTX_GRX_N1

B11

PEG_HTX_GRX_P0

C10

PEG_HTX_GRX_N0

B10

DMI_CTX_PRX_P0

B8

DMI_CTX_PRX_N0

A8

DMI_CTX_PRX_P1

C6

DMI_CTX_PRX_N1

B6

DMI_CTX_PRX_P2

B5

DMI_CTX_PRX_N2

A5

DMI_CTX_PRX_P3

D4

DMI_CTX_PRX_N3

B4

EDP_TXP0

D29

EDP_TXN0

E29

EDP_TXP1

F28

EDP_TXN1

E28

EDP_TXN2

B29

EDP_TXP2

A29

EDP_TXN3

B28

EDP_TXP3

C28

EDP_AUXP

C26

EDP_AUXN

B26

EDP_DISP_UTIL BIA_PWM_PCH

A33

EDP_COMP

D37

EDP_COMP CAD Note:Trace width=20 mils ,Spacing=25mil, Max length=100 mils.

AUD_AZA_CPU_SCLK

G27

AUD_AZA_CPU_SDO

G25

AUD_AZA_CPU_SDI AUD_AZA_CPU_SDI_R

G29

1 2

CH5 0.22U_0201_6.3V6M

1 2

CH6 0.22U_0201_6.3V6M

1 2

CH7 0.22U_0201_6.3V6M

1 2

CH8 0.22U_0201_6.3V6M

1 2

CH9 0.22U_0201_6.3V6M

1 2

CH10 0.22U_0201_6.3V6M

1 2

CH11 0.22U_0201_6.3V6M

1 2

CH12 0.22U_0201_6.3V6M

1 2

CH13 0.22U_0201_6.3V6M

1 2

CH14 0.22U_0201_6.3V6M

1 2

CH15 0.22U_0201_6.3V6M

1 2

CH16 0.22U_0201_6.3V6M

1 2

CH17 0.22U_0201_6.3V6M

1 2

CH18 0.22U_0201_6.3V6M

1 2

CH19 0.22U_0201_6.3V6M

1 2

CH20 0.22U_0201_6.3V6M

1 2

CH21 0.22U_0201_6.3V6M

1 2

CH22 0.22U_0201_6.3V6M

1 2

CH23 0.22U_0201_6.3V6M

1 2

CH24 0.22U_0201_6.3V6M

1 2

CH25 0.22U_0201_6.3V6M

1 2

CH26 0.22U_0201_6.3V6M

1 2

CH27 0.22U_0201_6.3V6M

1 2

CH28 0.22U_0201_6.3V6M

1 2

CH29 0.22U_0201_6.3V6M

1 2

CH30 0.22U_0201_6.3V6M

1 2

CH31 0.22U_0201_6.3V6M

1 2

CH32 0.22U_0201_6.3V6M

1 2

CH33 0.22U_0201_6.3V6M

1 2

CH34 0.22U_0201_6.3V6M

1 2

CH35 0.22U_0201_6.3V6M

1 2

CH36 0.22U_0201_6.3V6M

DMI_CTX_PRX_P0 <19> DMI_CTX_PRX_N0 <19>

DMI_CTX_PRX_P1 <19> DMI_CTX_PRX_N1 <19>

DMI_CTX_PRX_P2 <19> DMI_CTX_PRX_N2 <19>

DMI_CTX_PRX_P3 <19> DMI_CTX_PRX_N3 <19>

EDP_TXP0 <38> EDP_TXN0 <38> EDP_TXP1 <38> EDP_TXN1 <38> EDP_TXN2 <38> EDP_TXP2 <38> EDP_TXN3 <38> EDP_TXP3 <38>

EDP_AUXP <38> EDP_AUXN <38>

1 2

RH20

@

0_0402_5%

1 2

RH30

24.9_0402_1%

1 2

RH145

20_0402_5%

Close to CPU

PEG_HTX_C_GRX_P15 PEG_HTX_C_GRX_N15

PEG_HTX_C_GRX_P14 PEG_HTX_C_GRX_N14

PEG_HTX_C_GRX_P13 PEG_HTX_C_GRX_N13

PEG_HTX_C_GRX_P12 PEG_HTX_C_GRX_N12

PEG_HTX_C_GRX_P11 PEG_HTX_C_GRX_N11

PEG_HTX_C_GRX_P10 PEG_HTX_C_GRX_N10

PEG_HTX_C_GRX_P9 PEG_HTX_C_GRX_N9

PEG_HTX_C_GRX_P8 PEG_HTX_C_GRX_N8

PEG_HTX_C_GRX_P7 PEG_HTX_C_GRX_N7

PEG_HTX_C_GRX_P6 PEG_HTX_C_GRX_N6

PEG_HTX_C_GRX_P5 PEG_HTX_C_GRX_N5

PEG_HTX_C_GRX_P4 PEG_HTX_C_GRX_N4

PEG_HTX_C_GRX_P3 PEG_HTX_C_GRX_N3

PEG_HTX_C_GRX_P2 PEG_HTX_C_GRX_N2

PEG_HTX_C_GRX_P1 PEG_HTX_C_GRX_N1

PEG_HTX_C_GRX_P0 PEG_HTX_C_GRX_N0

BIA_PWM_PCH <16,38>

+VCCIO

AUD_AZA_CPU_SCLK <18> AUD_AZA_CPU_SDO <18> AUD_AZA_CPU_SDI_R <18>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/08/25 2012/07/25

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

PROCESSOR(1/7) DMI,FDI,PEG

Size Document Number Rev

Custom

Date: Sheet of

LA-E992P

1

7 77Tuesday, July 25, 2017

1.0(A00)

5

4

3

2

1

Non-Interleave

DDR_A_D[0..63]<14> DDR_A_MA[0..13]<14> DDR_A_DQS#[0..7]<14> DDR_A_DQS[0..7]<14>

DDR_B_D[0..63]<15> DDR_B_MA[0..13]<15> DDR_B_DQS#[0..7]<15>

D D

DDR_B_DQS[0..7]<15>

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15

DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36

C C

B B

DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47

UH1A

BR6

DDR0_DQ[0]

BT6

DDR0_DQ[1]

BP3

DDR0_DQ[2]

BR3

DDR0_DQ[3]

BN5

DDR0_DQ[4]

BP6

DDR0_DQ[5]

BP2

DDR0_DQ[6]

BN3

DDR0_DQ[7]

BL4

DDR0_DQ[8]

BL5

DDR0_DQ[9]

BL2

DDR0_DQ[10]

BM1

DDR0_DQ[11]

BK4

DDR0_DQ[12]

BK5

DDR0_DQ[13]

BK1

DDR0_DQ[14]

BK2

DDR0_DQ[15]

Interleave / Non-Interleaved

BG4

DDR0_DQ[16]/DDR0_DQ[32]

BG5

DDR0_DQ[17]/DDR0_DQ[33]

BF4

DDR0_DQ[18]/DDR0_DQ[34]

BF5

DDR0_DQ[19]/DDR0_DQ[35]

BG2

DDR0_DQ[20]/DDR0_DQ[36]

BG1

DDR0_DQ[21]/DDR0_DQ[37]

BF1

DDR0_DQ[22]/DDR0_DQ[38]

BF2

DDR0_DQ[23]/DDR0_DQ[39]

BD2

DDR0_DQ[24]/DDR0_DQ[40]

BD1

DDR0_DQ[25]/DDR0_DQ[41]

BC4

DDR0_DQ[26]/DDR0_DQ[42]

BC5

DDR0_DQ[27]/DDR0_DQ[43]

BD5

DDR0_DQ[28]/DDR0_DQ[44]

BD4

DDR0_DQ[29]/DDR0_DQ[45]

BC1

DDR0_DQ[30]/DDR0_DQ[46]

BC2

DDR0_DQ[31]/DDR0_DQ[47]

AB1

DDR0_DQ[32]/DDR1_DQ[0]

AB2

DDR0_DQ[33]/DDR1_DQ[1]

AA4

DDR0_DQ[34]/DDR1_DQ[2]

AA5

DDR0_DQ[35]/DDR1_DQ[3]

AB5

DDR0_DQ[36]/DDR1_DQ[4]

AB4

DDR0_DQ[37]/DDR1_DQ[5]

AA2

DDR0_DQ[38]/DDR1_DQ[6]

AA1

DDR0_DQ[39]/DDR1_DQ[7]

V5

DDR0_DQ[40]/DDR1_DQ[8]

V2

DDR0_DQ[41]/DDR1_DQ[9]

U1

DDR0_DQ[42]/DDR1_DQ[10]

U2

DDR0_DQ[43]/DDR1_DQ[11]

V1

DDR0_DQ[44]/DDR1_DQ[12]

V4

DDR0_DQ[45]/DDR1_DQ[13]

U5

DDR0_DQ[46]/DDR1_DQ[14]

U4

DDR0_DQ[47]/DDR1_DQ[15]

R2

DDR0_DQ[48]/DDR1_DQ[32]

P5

DDR0_DQ[49]/DDR1_DQ[33]

R4

DDR0_DQ[50]/DDR1_DQ[34]

P4

DDR0_DQ[51]/DDR1_DQ[35]

R5

DDR0_DQ[52]/DDR1_DQ[36]

P2

DDR0_DQ[53]/DDR1_DQ[37]

R1

DDR0_DQ[54]/DDR1_DQ[38]

P1

DDR0_DQ[55]/DDR1_DQ[39]

M4

DDR0_DQ[56]/DDR1_DQ[40]

M1

DDR0_DQ[57]/DDR1_DQ[41]

L4

DDR0_DQ[58]/DDR1_DQ[42]

L2

DDR0_DQ[59]/DDR1_DQ[43]

M5

DDR0_DQ[60]/DDR1_DQ[44]

M2

DDR0_DQ[61]/DDR1_DQ[45]

L5

DDR0_DQ[62]/DDR1_DQ[46]

L1

DDR0_DQ[63]/DDR1_DQ[47]

BA2

DDR0_ECC[0]

BA1

DDR0_ECC[1]

AY4

DDR0_ECC[2]

AY5

DDR0_ECC[3]

BA5

DDR0_ECC[4]

BA4

DDR0_ECC[5]

AY1

DDR0_ECC[6]

AY2

DDR0_ECC[7]

SKL-H_BGA1440

@

SKYLAKE_HALO

DDR3L / LPDDR3 / DDR4

DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]

DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]

DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]

DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]

DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]

DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]

DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8]

DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]

DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT#

Interleave / Non-Interleaved

DDR0_DQSN[2]/DDR0_DQSN[4] DDR0_DQSN[3]/DDR0_DQSN[5]

DDR0_DQSP[4]/DDR1_DQSP[0] DDR0_DQSP[5]/DDR1_DQSP[1] DDR0_DQSP[6]/DDR1_DQSP[4] DDR0_DQSP[7]/DDR1_DQSP[5]

DDR0_DQSP[2]/DDR0_DQSP[4]

DDR0_DQSP[3]/DDR0_DQSP[5] DDR0_DQSN[4]/DDR1_DQSN[0] DDR0_DQSN[5]/DDR1_DQSN[1] DDR0_DQSN[6]/DDR1_DQSN[4] DDR0_DQSN[7]/DDR1_DQSN[5]

DDR CH - A

1 OF 14

Rev_1.0

DDR0_CKP[0] DDR0_CKN[0] DDR0_CKN[1] DDR0_CKP[1]

DDR0_CLKP[2] DDR0_CLKN[2] DDR0_CLKP[3] DDR0_CLKN[3]

DDR0_CKE[0] DDR0_CKE[1] DDR0_CKE[2] DDR0_CKE[3]

DDR0_CS#[0]

DDR0_CS#[1]

DDR0_CS#[2]

DDR0_CS#[3]

DDR0_ODT[0] DDR0_ODT[1] DDR0_ODT[2] DDR0_ODT[3]

DDR0_MA[3] DDR0_MA[4]

DDR0_PAR

DDR0_ALERT#

DDR0_DQSN[0] DDR0_DQSN[1]

DDR0_DQSP[0] DDR0_DQSP[1]

DDR0_DQSP[8] DDR0_DQSN[8]

AG1 AG2 AK1 AK2 AL3 AK3 AL2 AL1

AT1 AT2 AT3 AT5

AD5 AE2 AD2 AE5

AD3 AE4 AE1 AD4

AH5 AH1 AU1

AH4 AG4 AD1

AH3 AP4 AN4 AP5 AP2 AP1 AP3 AN1 AN3 AT4 AH2 AN2 AU4 AE3 AU2 AU3

AG3 AU5

BR5 BL3

BG3 BD3 AB3 V3 R3 M3 BP5 BK3 BF3 BC3 AA3 U3 P3 L3

AY3 BA3

DDR_A_CLK0 DDR_A_CLK#0 DDR_A_CLK#1 DDR_A_CLK1

DDR_A_CKE0 DDR_A_CKE1

DDR_A_CS#0 DDR_A_CS#1

DDR_A_ODT0 DDR_A_ODT1

DDR_A_BS0 DDR_A_BS1 DDR_A_BG0

DDR_A_RAS# DDR_A_WE# DDR_A_CAS#

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_BG1 DDR_A_ACT#

DDR_A_PAR DDR_A_ALERT#

DDR_A_DQS#0 DDR_A_DQS#1

DDR_A_DQS#4 DDR_A_DQS#5 DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS4 DDR_B_DQS5 DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS4 DDR_A_DQS5 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#4 DDR_B_DQS#5

DDR_A_CLK0 <14 > DDR_A_CLK#0 <1 4> DDR_A_CLK#1 <1 4> DDR_A_CLK1 <14 >

DDR_A_CKE0 <14> DDR_A_CKE1 <14>

DDR_A_CS#0 <14 > DDR_A_CS#1 <14 >

DDR_A_ODT0 <14> DDR_A_ODT1 <14>

DDR_A_BS0 <14> DDR_A_BS1 <14> DDR_A_BG0 <14>

DDR_A_RAS# <14> DDR_A_WE# <14> DDR_A_CAS# <14>

DDR_A_BG1 <14> DDR_A_ACT# <14>

DDR_A_PAR <14> DDR_A_ALERT# <14>

1 2

RH148 121_0402_1%

1 2

RH149 75_0402_1%

1 2

RH150 100_0402_1%

DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31

DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

DDR_RCOMP0 DDR_RCOMP1 DDR_RCOMP2

UH1B

Interleave / Non-Interleaved

BT11

DDR1_DQ[0]/DDR0_DQ[16]

BR11

DDR1_DQ[1]/DDR0_DQ[17]

BT8

DDR1_DQ[2]/DDR0_DQ[18]

BR8

DDR1_DQ[3]/DDR0_DQ[19]

BP11

DDR1_DQ[4]/DDR0_DQ[20]

BN11

DDR1_DQ[5]/DDR0_DQ[21]

BP8

DDR1_DQ[6]/DDR0_DQ[22]

BN8

DDR1_DQ[7]/DDR0_DQ[23]

BL12

DDR1_DQ[8]/DDR0_DQ[24]

BL11

DDR1_DQ[9]/DDR0_DQ[25]

BL8

DDR1_DQ[10]/DDR0_DQ[26]

BJ8

DDR1_DQ[11]/DDR0_DQ[27]

BJ11

DDR1_DQ[12]/DDR0_DQ[28]

BJ10

DDR1_DQ[13]/DDR0_DQ[29]

BL7

DDR1_DQ[14]/DDR0_DQ[30]

BJ7

DDR1_DQ[15]/DDR0_DQ[31]

BG11

DDR1_DQ[16]/DDR0_DQ[48]

BG10

DDR1_DQ[17]/DDR0_DQ[49]

BG8

DDR1_DQ[18]/DDR0_DQ[50]

BF8

DDR1_DQ[19]/DDR0_DQ[51]

BF11

DDR1_DQ[20]/DDR0_DQ[52]

BF10

DDR1_DQ[21]/DDR0_DQ[53]

BG7

DDR1_DQ[22]/DDR0_DQ[54]

BF7

DDR1_DQ[23]/DDR0_DQ[55]

BB11

DDR1_DQ[24]/DDR0_DQ[56]

BC11

DDR1_DQ[25]/DDR0_DQ[57]

BB8

DDR1_DQ[26]/DDR0_DQ[58]

BC8

DDR1_DQ[27]/DDR0_DQ[59]

BC10

DDR1_DQ[28]/DDR0_DQ[60]

BB10

DDR1_DQ[29]/DDR0_DQ[61]

BC7

DDR1_DQ[30]/DDR0_DQ[62]

BB7

DDR1_DQ[31]/DDR0_DQ[63]

AA11

DDR1_DQ[32]/DDR1_DQ[16]

AA10

DDR1_DQ[33]/DDR1_DQ[17]

AC11

DDR1_DQ[34]/DDR1_DQ[18]

AC10

DDR1_DQ[35]/DDR1_DQ[19]

AA7

DDR1_DQ[36]/DDR1_DQ[20]

AA8

DDR1_DQ[37]/DDR1_DQ[21]

AC8

DDR1_DQ[38]/DDR1_DQ[22]

AC7

DDR1_DQ[39]/DDR1_DQ[23]

W8

DDR1_DQ[40]/DDR1_DQ[24]

W7

DDR1_DQ[41]/DDR1_DQ[25]

V10

DDR1_DQ[42]/DDR1_DQ[26]

V11

DDR1_DQ[43]/DDR1_DQ[27]

W11

DDR1_DQ[44]/DDR1_DQ[28]

W10

DDR1_DQ[45]/DDR1_DQ[29]

V7

DDR1_DQ[46]/DDR1_DQ[30]

V8

DDR1_DQ[47]/DDR1_DQ[31]

R11

DDR1_DQ[48]

P11

DDR1_DQ[49]

P7

DDR1_DQ[50]

R8

DDR1_DQ[51]

R10

DDR1_DQ[52]

P10

DDR1_DQ[53]

R7

DDR1_DQ[54]

P8

DDR1_DQ[55]

L11

DDR1_DQ[56]

M11

DDR1_DQ[57]

L7

DDR1_DQ[58]

M8

DDR1_DQ[59]

L10

DDR1_DQ[60]

M10

DDR1_DQ[61]

M7

DDR1_DQ[62]

L8

DDR1_DQ[63]

AW11

DDR1_ECC[0]

AY11

DDR1_ECC[1]

AY8

DDR1_ECC[2]

AW8

DDR1_ECC[3]

AY10

DDR1_ECC[4]

AW10

DDR1_ECC[5]

AY7

DDR1_ECC[6]

AW7

DDR1_ECC[7]

G1

DDR_RCOMP[0]

H1

DDR_RCOMP[1]

J2

DDR_RCOMP[2]

SKL-H_BGA1440

@

SKYLAKE_HALO

DDR3L / LPDDR3 / DDR4

DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]

DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]

DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]

DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]

DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0] DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]

DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8]

DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]

DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT#

Interleave / Non-Interleaved

DDR1_DQSN[0]/DDR0_DQSN[2] DDR1_DQSN[1]/DDR0_DQSN[3] DDR1_DQSN[2]/DDR0_DQSN[6] DDR1_DQSN[3]/DDR0_DQSN[7] DDR1_DQSN[4]/DDR1_DQSN[2] DDR1_DQSN[5]/DDR1_DQSN[3]

DDR1_DQSP[0]/DDR0_DQSP[2] DDR1_DQSP[1]/DDR0_DQSP[3] DDR1_DQSP[2]/DDR0_DQSP[6] DDR1_DQSP[3]/DDR0_DQSP[7] DDR1_DQSP[4]/DDR1_DQSP[2] DDR1_DQSP[5]/DDR1_DQSP[3]

DDR CH - B

2 OF 14

DDR0_VREF_DQ DDR1_VREF_DQ

Rev_1.0

DDR1_CKP[0] DDR1_CKN[0] DDR1_CKN[1]

DDR1_CKP[1] DDR1_CLKP[2] DDR1_CLKN[2] DDR1_CLKP[3] DDR1_CLKN[3]

DDR1_CKE[0]

DDR1_CKE[1]

DDR1_CKE[2]

DDR1_CKE[3]

DDR1_CS#[0] DDR1_CS#[1] DDR1_CS#[2] DDR1_CS#[3]

DDR1_ODT[0]

DDR1_ODT[1]

DDR1_ODT[2]

DDR1_ODT[3]

DDR1_MA[3] DDR1_MA[4]

DDR1_PAR

DDR1_ALERT#

DDR1_DQSN[6] DDR1_DQSN[7]

DDR1_DQSP[6] DDR1_DQSP[7]

DDR1_DQSP[8] DDR1_DQSN[8]

DDR_VREF_CA

AM9 AN9 AM8 AM7 AM11 AM10 AJ10 AJ11

AT8 AT10 AT7 AT11

AF11 AE7 AF10 AE10

AF7 AE8 AE9 AE11

AH10 AH11 AF8

AH8 AH9 AR9

AJ9 AK6 AK5 AL5 AL6 AM6 AN7 AN10 AN8 AR11 AH7 AN11 AR10 AF9 AR7 AT9

AJ7 AR8

BP9 BL9 BG9 BC9 AC9 W9 R9 M9

BR9 BJ9 BF9 BB9 AA9 V9 P9 L9

AW9 AY9

BN13 BP13 BR13

DDR_B_CLK0 DDR_B_CLK#0 DDR_B_CLK#1 DDR_B_CLK1

DDR_B_CKE0 DDR_B_CKE1

DDR_B_CS#0 DDR_B_CS#1

DDR_B_ODT0 DDR_B_ODT1

DDR_B_RAS# DDR_B_WE# DDR_B_CAS#

DDR_B_BS0 DDR_B_BS1 DDR_B_BG0

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_BG1 DDR_B_ACT#

DDR_B_PAR DDR_B_ALERT#

DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#6 DDR_A_DQS#7 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#6 DDR_B_DQS#7

DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS6 DDR_A_DQS7 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS6 DDR_B_DQS7

DDR_B_CLK0 <15 > DDR_B_CLK#0 <1 5> DDR_B_CLK#1 <1 5> DDR_B_CLK1 <15 >

DDR_B_CKE0 < 15> DDR_B_CKE1 < 15>

DDR_B_CS#0 <15 > DDR_B_CS#1 <15 >

DDR_B_ODT0 <15> DDR_B_ODT1 <15>

DDR_B_RAS# < 15> DDR_B_WE# <15> DDR_B_CAS# < 15>

DDR_B_BS0 <15> DDR_B_BS1 <15> DDR_B_BG0 <15>

DDR_B_BG1 <15> DDR_B_ACT# <15>

DDR_B_PAR <1 5> DDR_B_ALERT# <15>

+V_DDR_REFA_R

+V_DDR_REFB_R

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/08/25 2012/07/25

Compal Secret Data

Deciphered Date

Title

PROCESSOR(3/7) DDRIII

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

LA-E992P

8 77Tuesday, July 25, 2017

1

8 77Tuesday, July 25, 2017

1.0(A00)

5

4

3

2

1

+VCCSTG

CFG Straps for Processor

+VCCST

Stall reset sequence after CPU PLL lock until de-asserted

D D

CFG0

1 = (Default) Normal Operation; No stall.

*

0 = Stall.

RH183

1 2

@

1K_0402_5%

CFG0

RH165

RH163

RH156

RH164

RH151

RH152

RH144

1 2

1K_0402_5%

1 2

1K_0402_5%

1 2

51_0402_5%

1 2

1K_0402_5%

1 2

100_0402_5%

1 2

56.2_0402_1%

1 2

49.9_0402_1%

PCI EXPRESS STATIC LANE REVERSAL FOR ALL PEG PORTS

CFG2

C C

1: Normal Operation; Lane # definition matches socket pin map definition

0:Lane Reversed

*

RH184

1 2

1K_0402_5%

CFG2

Display Port Presence Strap

CFG4

PCIE Port Bifurcation Straps

B B

CFG[6:5]

1 : Disabled; No Physical Display Port attached to Embedded Display Port

0 : Enabled; An external Display Port device is connected to the Embedded Display Port

*

RH185

RH186

RH187

1 2

1K_0402_5%

1 2

@

1K_0402_5%

1 2

@

1K_0402_5%

CFG4

11: (Default) x16 - Device 1 functions 1 and 2 disabled

*

10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled

01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)

00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

CFG5

CFG6

SM_PG_CTRL<62>

If change to x8, need cheange setting.

PEG DEFER TRAINING

CFG7

A A

1: (Default) PEG Train immediately following xxRESETB de assertion

*

0: PEG Wait for BIOS for training

RH188

1 2

1K_0402_5%

5

@

CFG7

4

@

VR_SVID_ALERT#<71> VR_SVID_CLK<71> VR_SVID_DATA<71> H_PROCHOT#<36,59,60,71>

H_VCCST_PWRGD<6,18>

H_CPUPWRGD<18> PLTRST_CPU#< 6,16> H_PM_SYNC_R<16>

H_PM_DOWN<16>

PECI_EC<16,36>

H_THERMTRIP#_R<16>

PROC_DETECT#<16>

0.1U_0402_10V7K

PCH_TRIGGER<22>

CPU_TRIGGER<22>

H_PROCHOT#

H_THERMTRIP#_R

XDP_PREQ#

H_VCCST_PWRGD

VR_SVID_DATA

VR_SVID_ALERT#

H_CATERR#

VR_SVID_ALERT# VR_SVID_CLK VR_SVID_DATA

H_VCCST_PWRGD

H_PM_DOWN PECI_EC

PROC_DETECT#

DVT2.0 Change RH190 to 0ohm 0402 short-pad footprint.

PCH_CPU_BCLK_P<17> PCH_CPU_BCLK_N<17>

PCH_CPU_PCIBCLK_P<17> PCH_CPU_PCIBCLK_N<17>

CPU_24MHZ_P<17> CPU_24MHZ_N<17>

RH153 220_0402_5%

RH158 499_0402_1%

RH154 60.4_0402_1%

RH155 20_0402_5% RH190 0_0402_5%@

RH89 0_0402_5%@

+1.2V_DDR

@

CH197

1

2

SM_PG_CTRL

RH93

220K_0402_5%

+3VS

12

UC1

5

VCC

4

Y

74AUP1G07SE-7_SOT353

SA00007WE00

Reserve for ESD

H_VCCST_PWRGD

H_PROCHOT#_R

1 2

CH210

100P_0402_50V8J@ESD@

1 2

CH211

100P_0402_50V8J

PCH_TRIGGER PCH_TRIGGER_R CPU_TRIGGER CPU_TRIGGER_R

RH167 30_0402_5% RH192 30_0402_5%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

1 2

1 2 1 2

1 2

NC

GND

1 2 1 2

BH31 BH32 BH29 BR30

BT13

BT31 BP35 BM34 BP31

BT34

BR33

BM30

BN35

BN33

BL34

AE29 AA14

BR35 BR31 BH30

B31 A32

D35 C36

E31 D31

H13

J31

BN1

D1 E1 E3 E2

BR1 BT2

J24

H24

N29 R14

A36 A37

H23

J23

F30 E30

B30 C30

G3 J3

UH1E

BCLKP BCLKN

PCI_BCLKP PCI_BCLKN

CLK24P CLK24N

VIDALERT# VIDSCK VIDSOUT PROCHOT#

DDR_VTT_CNTL

VCCST_PWRGD

PROCPWRGD RESET# PM_SYNC PM_DOWN PECI THERMTRIP#

SKTOCC# PROC_SELECT#

CATERR#

SKL-H_BGA1440

@

UH1K

RSVD_TP RSVD_TP RSVD_TP RSVD_TP

RSVD_TP RSVD_TP

RSVD

RSVD RSVD RSVD RSVD

RSVD RSVD

PROC_TRIGIN PROC_TRIGOUT

RSVD RSVD

RSVD RSVD RSVD

SKL-H_BGA1440

@

PCH_CPU_BCLK_P PCH_CPU_BCLK_N

PCH_CPU_PCIBCLK_P PCH_CPU_PCIBCLK_N

CPU_24MHZ_P CPU_24MHZ_N

VR_SVID_ALERT#_R

H_PROCHOT#_RH_PROCHOT#

DDR_VTT_PG_CTRL

VCCST_PWRGD_CPU

H_CPUPWRGD PLTRST_CPU# H_PM_SYNC_R H_PM_DOWN_R PECI_EC_R H_THERMTRIP#_R

H_CATERR#

1

DDR_VTT_PG_CTRL

2

A

3

Compal Secret Data

2011/08/25 2012/07/25

Compal Secret Data

Deciphered Date

SKYLAKE_HALO

2

5 OF 14

SKYLAKE_HALO

11 OF 14

Rev_1.0

CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8]

CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15]

CFG[17] CFG[16] CFG[19] CFG[18]

BPM#[0] BPM#[1] BPM#[2] BPM#[3]

PROC_TDO

PROC_TDI PROC_TMS PROC_TCK

PROC_TRST#

PROC_PREQ#

PROC_PRDY#

CFG_RCOMP

CFG[0..19] <6>

BN25

CFG0

BN27

CFG1

BN26

CFG2

BN28

CFG3

BR20

CFG4

BM20

CFG5

BT20

CFG6

BP20

CFG7

BR23

CFG8

BR22

CFG9

BT23

CFG10

BT22

CFG11

BM19

CFG12

BR19

CFG13

BP19

CFG14

BT19

CFG15

BN23

CFG17

BP23

CFG16

BP22

CFG19

BN22

CFG18

XDP_BPM#0

BR27

XDP_BPM#1

BT27 BM31 BT30

CPU_XDP_TDO

BT28

CPU_XDP_TDI

BL32

CPU_XDP_TMS

BP28

CPU_XDP_TCK

BR28

CPU_XDP_TRST#

BP30

XDP_PREQ#

BL30

XDP_PRDY#

BP27

CFG_RCOMP

BT25

Rev_1.0

RSVD_TP RSVD_TP

RSVD RSVD

VSS

RSVD_TP RSVD_TP

RSVD RSVD

VSS

RSVD_TP RSVD_TP

RSVD RSVD RSVD

NCTF NCTF NCTF NCTF NCTF NCTF

Compal Electronics, Inc.

Title

PROCESSOR(4/7) RSVD,CFG

Size Document Number Rev

Custom

Date: Sheet of

BM33 BL33

BJ14 BJ13

BK28 BJ28

BJ18

BJ16 BK16

BK24 BJ24

BK21 BJ21

BT17 BR17

BK18

BJ34 BJ33

G13 AJ8 BL31

B2 B38 BP1 BR2 C1 C38

XDP_BPM#0 <6> XDP_BPM#1 <6>

CPU_XDP_TDO <6 > CPU_XDP_TDI <6> CPU_XDP_TMS <6> CPU_XDP_TCK <6,18 >

CPU_XDP_TRST# <6,22> XDP_PREQ# <6,22> XDP_PRDY# <6,22>

12

RH59

49.9_0402_1%

LA-E992P

9 77Tuesday, July 25, 2017

1

9 77Tuesday, July 25, 2017

1.0(A00)

5

4

3

2

1

+VCC_CORE +VCC_CORE

D D

C C

B B

AA13 AA31 AA32 AA33 AA34 AA35 AA36 AA37 AA38 AB29 AB30 AB31 AB32 AB35 AB36 AB37 AB38 AC13 AC14 AC29 AC30 AC31 AC32 AC33 AC34 AC35 AC36 AD13 AD14 AD31 AD32 AD33 AD34 AD35 AD36 AD37 AD38 AE13 AE14 AE30 AE31 AE32 AE35 AE36 AE37 AE38

AF35 AF36 AF37 AF38

K13 K14

N13 N14 N30 N31 N32 N35 N36 N37 N38 P13

L13

SKYLAKE_HALO

UH1G

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

SKL-H_BGA1440

@

7 OF 14

Rev_1.0

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

VCC_SENSE

VSS_SENSE

V32 V33 V34 V35 V36 V37 V38 W13 W14 W29 W30 W31 W32 W35 W36 W37 W38 Y29 Y30 Y31 Y32 Y33 Y34 Y35 Y36 L14 P29 P30 P31 P32 P33 P34 P35 P36 R13 R31 R32 R33 R34 R35 R36 R37 R38 T29 T30 T31 T32 T35 T36 T37 T38 U29 U30 U31 U32 U33 U34 U35 U36 V13 V14 V31 P14

AG37 AG38

+VCC_CORE

12

RH197 100_0402_1%

1 2

RH198 0_0402_5%@

1 2

RH28 0_0402_5%@

DVT2.0 Change RH198, RH28 to 0ohm 0402 short-pad footprint.

RH29 100_0402_1%

VCCSENSE VSSSENSE

VCCSENSE <71> VSSSENSE <71>

1 2

RH166 49.9_0402_1%@

1 2

RH57 49.9_0402_1%@

1 2

RH58 49.9_0402_1%@

BJ17 BJ19

BJ20 BK17 BK19 BK20 BL16 BL17 BL18 BL19 BL20 BL21

BM17 BN17

BJ23

BJ26

BJ27 BK23 BK26 BK27 BL23 BL24 BL25 BL26 BL27 BL28

BM24

BL15

BM16

BL22

BM22

BP15

BR15

BT15

BP16

BR16

BT16

BN15 BM15

BP17

BN16

BM14

BL14

BJ35

BJ36

AT13

AW13

AU13

AY13

BT29

BR25

BP25

UH1J

VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC

RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD

VCCOPC_SENSE VSSOPC_SENSE

RSVD RSVD

VCCEOPIO VCCEOPIO VCCEOPIO

RSVD RSVD RSVD

VCCEOPIO_SENSE VSSEOPIO_SENSE

RSVD RSVD

VCC_OPC_1P8 VCC_OPC_1P8

RSVD RSVD

ZVM# MSM#

ZVM2# MSM2#

OPC_RCOMP OPCE_RCOMP OPCE_RCOMP2

SKL-H_BGA1440

@

SKYLAKE_HALO

10 OF 14

Rev_1.0

A A

Security Classification

2011/08/25 2012/07/25

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/08/25 2012/07/25

3

Compal Secret Data

Deciphered Date

Title

PROCESSOR(5/7) PWR,BYPASS

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

LA-E992P

1

10 77Tuesday, July 25, 2017

1.0(A00)

5

D D

4

3

2

1

Rev_1.0

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VDDQC

VCCST

+1.2V_DDR

AA6 AE12 AF5 AF6 AG5 AG9 AJ12 AL11 AP6 AP7 AR12 AR6 AT12 AW6 AY6 J5 J6 K12 K6 L12 L6 R6 T6 W6

Y12

BH13 G11

H30

H29

G30

H28 J28

M38 M37

H14 J14

+1.2V_DDR

10U_0402_6.3V6M

1

CH124

Close to Ball Y12

2

+1.2V_DDR+1.2V_VCCPLL_OC

1 2

RH107 0_0402_5%@

+VCCST

+VCCSTG

+VCCST

+VCCSA

1 2

RH201 100_0402_1%

1 2

RH202 0_0402_5%@

1 2

RH31 0_0402_5%@

1 2

RH41 100_0402_1%

DVT2.0 Change RH202, RH31 to 0ohm 0402 short-pad footprint.

1 2

RH515 100_0402_1%

1 2

RH514 0_0402_5%@

1 2

RH513 0_0402_5%@

1 2

RH516 100_0402_1%

DVT2.0 Change RH514, RH513 to 0ohm 0402 short-pad footprint.

VCCSA_SENSE VSSSA_SENSE

+VCCIO

VCCIO_SENSE VSSIO_SENSE

VCCSA_SENSE <71> VSSSA_SENSE <71>

VCCIO_SENSE <74> VSSIO_SENSE <74>

CH102

10U_0603_6.3V6M

+1.2V_DDR

CH129

22U_0603_6.3V6M

+1.2V_DDR

CH118

10U_0603_6.3V6M

1

2

1

2

1

2

CH103

CH130

CH121

+VCCSTG +VCCSA

CH104

1

10U_0603_6.3V6M

2

CH131

1

22U_0603_6.3V6M

2

1

10U_0603_6.3V6M

2

CH106

1

2

1

2

CH132

CH120

1U_0402_6.3V6K

1

22U_0603_6.3V6M

2

CH119

1

10U_0603_6.3V6M

2

10U_0603_6.3V6M

22U_0603_6.3V6M

+VCCST+VCCIO

CH204

CH110

1

2

1

1U_0402_6.3V6K

2

+VCCSA +VCCSA

CH133

1

1U_0402_6.3V6K

2

CH122

1

10U_0603_6.3V6M

2

CH134

CH123

1

2

CH111

1

2

1

2

CH135

CH125

1

2

1

10U_0603_6.3V6M

2

1

1U_0402_6.3V6K

2

1

10U_0603_6.3V6M

2

1U_0402_6.3V6K

10U_0603_6.3V6M

CH112

CH126

CH113

1

10U_0603_6.3V6M

2

CH136

47U_0603_6.3V6M

CH127

1

10U_0603_6.3V6M

2

1

2

1

2

1

2

CH114

CH128

CH115

CH116

CH117

1

10U_0603_6.3V6M

2

1

10U_0603_6.3V6M

2

1

10U_0603_6.3V6M

2

1

10U_0603_6.3V6M

2

+VCCSA

C C

+VCCIO

B B

K29 K30 K31 K32 K33 K34 K35

M29 M30 M31 M32 M33 M34 M35 M36

AG12

G15 G17 G19 G21 H15 H16 H17 H19 H20 H21 H26 H27

J30

L31 L32 L35 L36 L37 L38

J15 J16 J17 J19 J20 J21 J26 J27

UH1I

VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA

VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO

SKL-H_BGA1440

@

SKYLAKE_HALO

9 OF 14

VCCPLL_OC VCCPLL_OC

VCCSTG

VCCPLL VCCPLL

VCCSA_SENSE

VSSSA_SENSE

VCCIO_SENSE

VSSIO_SENSE

A A

Security Classification

2011/08/25 2012/07/25

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/08/25 2012/07/25

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

PROCESSOR(6/7) PWR

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

LA-E992P

1

11 77Tuesday, July 25, 2017

1.0(A00)

5

4

3

2

1

+VCCGT

SKYLAKE_HALO

D D

C C

B B

A A

BG34 BG35 BG36 BH33 BH34 BH35 BH36 BH37 BH38

BJ37 BJ38 BL36

BL37 BM36 BM37

BN36 BN37 BN38 BP37 BP38 BR37 BT37 BE38 BF13 BF14 BF29 BF30 BF31 BF32 BF35 BF36 BF37 BF38 BG29 BG30 BG31 BG32 BG33 BC36 BC37 BC38 BD13 BD14 BD29 BD30 BD31 BD32 BD33 BD34 BD35 BD36 BE31 BE32 BE37

UH1H

VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT

SKL-H_BGA1440

@

8 OF 14

Rev_1.0

VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT

+VCCGT +VCCGT

AV29 AV30 AV31 AV32 AV33 AV34 AV35 AV36 AW14 AW31 AW32 AW33 AW34 AW35 AW36 AW37 AW38 AY29 AY30 AY31 AY32 AY35 AY36 AY37 AY38 BA13 BA14 BA29 BA30 BA31 BA32 BA33 BA34 BA35 BA36 BB13 BB14 BB31 BB32 BB33 BB34 BB35 BB36 BB37 BB38 BC29 BC30 BC31 BC32 BC35 BE33 BE34 BE35 BE36

AJ29 AJ30 AJ31 AJ32 AJ33 AJ34 AJ35

AJ36 AK31 AK32 AK33 AK34 AK35 AK36 AK37 AK38

AL13

AL29

AL30

AL31

AL32

AL35

AL36

AL37

AL38 AM13 AM14 AM29 AM30 AM31 AM32 AM33 AM34 AM35 AM36 AN13 AN14 AN31 AN32 AN33 AN34 AN35 AN36 AN37 AN38 AP13 AP14 AP29 AP30 AP31 AP32 AP35 AP36 AP37 AP38 AR29 AR30 AR31 AR32 AR33 AR34 AR35 AR36 AT14 AT31 AT32 AT33 AT34 AT35 AT36 AT37 AT38 AU14 AU29 AU30 AU31 AU32 AU35 AU36 AU37 AU38

UH1N

VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT

SKL-H_BGA1440

@

SKYLAKE_HALO

14 OF 14

Rev_1.0

VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX

VCCGT_SENSE

VSSGTX_SENSE

VSSGT_SENSE

VCCGTX_SENSE

AF29 AF30 AF31 AF32 AF33 AF34 AG13 AG14 AG31 AG32 AG33 AG34 AG35 AG36 AH13 AH14 AH29 AH30 AH31 AH32 AJ13 AJ14

AH38 AH35 AH37 AH36

+VCCGT

12

RH203 100_0402_1%

1 2

RH204 0_0402_5%@

RH32

1 2

RH33 100_0402_1%

0_0402_5%@

DVT2.0 Change RH204, RH32 to 0ohm 0402 short-pad footprint.

VCCGT_SENSE <71>

VSSGT_SENSE <71>

Security Classification

2011/08/25 2012/07/25

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/08/25 2012/07/25

3

Compal Secret Data

Deciphered Date

Title

PROCESSOR(2/7) PM,XDP,CLK

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

LA-E992P

1

12 77Tuesday, July 25, 2017

1.0(A00)

5

4

3

2

1

SKYLAKE_HALO

UH1F

Y38

VSS

Y37

VSS

Y14

VSS

Y13

VSS

Y11

VSS

D D

C C

B B

A A

Y10

Y9 Y8

Y7 W34 W33 W12

W5 W4 W3 W2 W1 V30 V29 V12

V6

U38 U37

U6 T34 T33 T14 T13 T12 T11 T10

T9 T8 T7 T5 T4 T3 T2

T1 R30 R29 R12

P38 P37 P12

P6 N34 N33 N12 N11 N10

N9 N8 N7 N6 N5 N4 N3 N2

N1 M14 M13 M12

M6

L34 L33 L30 L29 K38 K11 K10

K9 K8 K7 K5 K4 K3 K2

SKL-H_BGA1440

@

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

6 OF 14

Rev_1.0

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

NCTFVSS

K1 J36 J33 J32 J25 J22 J18 J10 J7 J4 H35 H32 H25 H22 H18 H12 H11 G28 G26 G24 G23 G22 G20 G18 G16 G14 G12 G10 G9 G8 G6 G5 G4 F36 F31 F29 F27 F25 F23 F21 F19 F17 F15 F13 F11 F9 F8 F5 F4 F3 F2 E38 E35 E34 E9 E4 D33 D30 D28 D26 D24 D22 D20 D18 D16 D14 D12 D10 D9 D6 D3 C37 C31 C29 C27

D38

C17 C13

BT32 BT26 BT24 BT21 BT18 BT14 BT12

BT9

BT5 BR36 BR34 BR29 BR26 BR24 BR21 BR18 BR14 BR12

BR7 BP34 BP33 BP29 BP26 BP24 BP21 BP18 BP14 BP12

BP7 BN34 BN31 BN30 BN29 BN24 BN21 BN20 BN19 BN18 BN14 BN12

BN9

BN7

BN4

BN2

BM38 BM35 BM28 BM27 BM26 BM23 BM21 BM13 BM12

BM9 BM6

BM2 BL29 BK29 BK15 BK14 BJ32 BJ31 BJ25 BJ22

BH14 BH12

BH9

BH8

BH5

BH4

BH1

BG38 BG13 BG12

BF33 BF12 BE29

BE6

BD9

BC34 BC12

BB12

C9

SKL-H_BGA1440

@

UH1L

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

SKYLAKE_HALO

12 OF 14

Rev_1.0

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

NCTFVSS NCTFVSS NCTFVSS NCTFVSS NCTFVSS NCTFVSS

C25 C23 C21 C19 C15 C11 C8 C5 BM29 BM25 BM18 BM11 BM8 BM7 BM5 BM3 BL38 BL35 BL13 BL6 BK25 BK22 BK13 BK6 BJ30 BJ29 BJ15 BJ12 BH11 BH10 BH7 BH6 BH3 BH2 BG37 BG14 BG6 BF34 BF6 BE30 BE5 BE4 BE3 BE2 BE1 BD38 BD37 BD12 BD11 BD10 BD8 BD7 BD6 BC33 BC14 BC13 BC6 BB30 BB29 BB6 BB5

C2 BT36 BT35 BT4 BT3 BR38

BB4 BB3 BB2

BB1 BA38 BA37 BA12 BA11 BA10

BA9

BA8

BA7

BA6

AY34 AY33 AY14 AY12

AW30 AW29 AW12

AW5 AW4 AW3 AW2

AW1 AV38 AV37 AU34 AU33 AU12 AU11 AU10

AU9 AU8 AU7

AU6 AT30 AT29

AT6 AR38 AR37 AR14 AR13

AR5 AR4 AR3 AR2

AR1 AP34 AP33 AP12 AP11 AP10

AP9

AP8 AN30 AN29 AN12

AN6

AN5 AM38 AM37 AM12

AM5

AM4

AM3

AM2

AM1

AL34 AL33 AL14 AL12 AL10

AL9 AL8 AL7 AL4

B9

SKL-H_BGA1440

@

UH1M

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

SKYLAKE_HALO

13 OF 14

Rev_1.0

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

NCTFVSS NCTFVSS NCTFVSS NCTFVSS NCTFVSS

AK30 AK29 AK4 AJ38 AJ37 AJ6 AJ5 AJ4 AJ3 AJ2 AJ1 AH34 AH33 AH12 AH6 AG30 AG29 AG11 AG10 AG8 AG7 AG6 AF14 AF13 AF12 AF4 AF3 AF2 AF1 AE34 AE33 AE6 AD30 AD29 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AC38 AC37 AC12 AC6 AC5 AC4 AC3 AC2 AC1 AB34 AB33 AB6 AA30 AA29 AA12 A30 A28 A26 A24 A22 A20 A18 A16 A14 A12 A10 A9 A6

B37 B3 A34 A4 A3

Security Classification

2011/08/25 2012/07/25

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/08/25 2012/07/25

3

Compal Secret Data

Deciphered Date

Title

PROCESSOR(7/7) VSS

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

LA-E992P

13 77Tuesday, July 25, 2017

1

1.0(A00)

5

DDR_A_D[0..63]<8> DDR_A_MA[0..13]<8> DDR_A_DQS#[0..7]<8> DDR_A_DQS[0..7]<8>

Layout Note: Place near JDIMM1.257,259

D D

+2.5V_MEM +3VS+0.6VS

CD10

CD9

1

10U_0603_6.3V6M

2

Layout Note: Place near JDIMM1

CD4

CD3

1

10U_0603_6.3V6M

2

1

1U_0402_6.3V6K

2

Layout Note: Place near JDIMM1.258

CD14

CD13

CD12

1

1U_0402_6.3V6K

2

1

10U_0603_6.3V6M

2

+1.2V_DDR

CD75

CD1

CD2

1

1U_0402_6.3V6K

C C

2

CD74

CD77

1

2

1

1U_0402_6.3V6K

2

CD79

CD76

1

1U_0402_6.3V6K

2

CD78

1

2

1

1U_0402_6.3V6K

2

+1.2V_DDR

CD6

CD5

CD7

1

10U_0603_6.3V6M

2

CD70

CD8

1

10U_0603_6.3V6M

2

CD71

1

10U_0603_6.3V6M

2

CD73

CD72

1

10U_0603_6.3V6M

DVT1.0 Remove CD11

2

+1.2V_DDR

B B

A A

DVT2.0 Change RD31 to 0ohm 0402 short-pad footprint.

DDR4_DRAMRST#<15> H_DRAMRST# <18>

RH45

1 2

2_0402_1%

+1.2V_DDR

12

+V_DDR_REFA_R

20mil

1

CH101

0.022U_0402_16V7K

2

12

RH211

24.9_0402_1%

RH206 1K_0402_1%

+V_DDR_REFA

RH209 1K_0402_1%

1

@ESD@

CD97

.1U_0402_16V7K

2

RD31

1 2

@

0_0402_5%

12

RD35 470_0402_1%

H_DRAMRST#DDR4_DRAMRST#

1

@ESD@

CD69

.1U_0402_16V7K

2

DIMM_CHA_SA2

DIMM_CHA_SA1

DIMM_CHA_SA0

4

Layout Note: Place near JDIMM1.255

CD15

1

10U_0603_6.3V6M

2

CD17

CD16

1

2.2U_0402_6.3V6M

0.1U_0402_10V6K

2

+3VS

+2.5V_MEM

3

+1.2V_DDR

JDIMM1

1

VSS1

3

DQ5

5

DDR_A_D0

DDR_A_DQS#0 DDR_A_DQS0

DDR_A_D7

DDR_A_D3

DDR_A_D13

DDR_A_D12

DDR_A_D15 DDR_A_D10

DDR_A_D14 DDR_A_D11

DDR_A_D37

DDR_A_DQS#4 DDR_A_DQS4

DDR_A_D38

DDR_A_D34

DDR_A_D45

DDR_A_D44

DDR_A_D46

DDR_A_CKE0<8>

DDR_A_BG1<8> DDR_A_BG0<8>

DDR_A_CLK0<8> DDR_A_CLK#0<8>

DDR_A_PAR<8> DDR_A_BS1<8>

DDR_A_CS#0<8> DDR_A_WE#<8>

DDR_A_ODT0<8> DDR_A_CS#1<8>

DDR_A_ODT1<8>

DDR_A_CKE0

DDR_A_BG1 DDR_A_BG0

DDR_A_MA12 DDR_A_MA9

DDR_A_MA8 DDR_A_MA6

DDR_A_MA3 DDR_A_MA1

DDR_A_CLK0 DDR_A_CLK#0

DDR_A_PAR DDR_A_BS1

DDR_A_CS#0 DDR_A_WE#

DDR_A_ODT0 DDR_A_CS#1

DDR_A_ODT1

DDR_A_D20

DDR_A_D21

DDR_A_DQS#2 DDR_A_DQS2

DDR_A_D18

DDR_A_D19

DDR_A_D25

DDR_A_D24

+1.2V_DDR

DDR_A_D29

DDR_A_D49

DDR_A_D48

DDR_A_DQS#6 DDR_A_DQS6

DDR_A_D53

DDR_A_D51

DDR_A_D60

DDR_A_D57

+1.2V_DDR

DDR_A_D56

DDR_A_D61 DDR_A_D58

PCH_SMBCLK<6,15,18,29,35>

PCH_SMBCLK

VSS3

7

DQ1

9

VSS5

11

DQS0_c

13

DQS0_t

15

VSS8

17

DQ7

19

VSS10

21

DQ3

23

VSS12

25

DQ13

27

VSS14

29

DQ9

31

VSS16

33

DM1_n/DBI_n

35

VSS17

37

DQ15

39

VSS19

41

DQ10

43

VSS21

45

DQ21

47

VSS23

49

DQ17

51

VSS25

53

DQS2_c

55

DQS2_t

57

VSS28

59

DQ23

61

VSS30

63

DQ19

65

VSS32

67

DQ29

69

VSS34

71

DQ25

73

VSS36

75

DM3_n/DBI3_n

77

VSS37

79

DQ30

81

VSS39

83

DQ26

85

VSS41

87

CB5/NC

89

VSS43

91

CB1/NC

93

VSS45

95

DQS8_c

97

DQS8_t

99

VSS48

101

CB2/NC

103

VSS50

105

CB3/NC

107

VSS52

109

CKE0

111

VDD1

113

BG1

115

BG0

117

VDD3

119

A12

121

A9

123

VDD5

125

A8

127

A6

129

VDD7

131

A3

133

A1

135

VDD9

137

CK0_t

139

CK0_c

141

VDD11

143

PARITY

145

BA1

147

VDD13

149

CS0_n

151

WE_n/A14

153

VDD15

155

ODT0

157

CS1_n

159

VDD17

161

ODT1

163

VDD19

165

C1, CS3_n,NC

167

VSS53

169

DQ37

171

VSS55

173

DQ33

175

VSS57

177

DQS4_c

179

DQS4_t

181

VSS60

183

DQ38

185

VSS62

187

DQ34

189

VSS64

191

DQ44

193

VSS66

195

DQ40

197

VSS68

199

DM5_n/DBI5_n

201

VSS69

203

DQ46

205

VSS71

207

DQ42

209

VSS73

211

DQ52

213

VSS75

215

DQ49

217

VSS77

219

DQS6_c

221

DQS6_t

223

VSS80

225

DQ55

227

VSS82

229

DQ51

231

VSS84

233

DQ61

235

VSS86

237

DQ56

239

VSS88

241

DM7_n/DBI7_n

243

VSS89

245

DQ62

247

VSS91

249

DQ58

251

VSS93

253

SCL

255

VDDSPD

257

VPP1

259

VPP2

261

GND1

DEREN_40-42271-26001RHF CONN@

SP07001CW00

VSS2

VSS4

VSS6

DM0_n/DBI0_n

VSS7

VSS9

VSS11

DQ12

VSS13

VSS15

DQS1_c

DQS1_t

VSS18

DQ14

VSS20

DQ11

VSS22

DQ20

VSS24

DQ16

VSS26

DM2_n/DBI2_n

VSS27

DQ22

VSS29

DQ18

VSS31

DQ28

VSS33

DQ24

VSS35

DQS3_c

DQS3_t

VSS38

DQ31

VSS40

DQ27

VSS42

CB4/NC

VSS44

CB0/NC

VSS46

DM8_n/DBI_n/NC

VSS47

CB6/NC

VSS49

CB7/NC

VSS51

RESET_n

CKE1 VDD2

ACT_n

ALERT_n

VDD4

VDD6

VDD8

EVENT_n/NF

VDD10

CK1_t/NF

CK1_c/NF

VDD12

A10/AP

VDD14

RAS_n/A16

VDD16

CAS_n/A15

VDD18

C0/CS2_n/NC

VREFCA

VSS54

DQ36

VSS56

DQ32

VSS58

DM4_n/DBI4_n

VSS59

DQ39

VSS61

DQ35

VSS63

DQ45

VSS65

DQ41

VSS67

DQS5_c

DQS5_t

VSS70

DQ47

VSS72

DQ43

VSS74

DQ53

VSS76

DQ48

VSS78

DM6_n/DBI6_n

VSS79

DQ54

VSS81

DQ50

VSS83

DQ60

VSS85

DQ57

VSS87

DQS7_c

DQS7_t

VSS90

DQ63

VSS92

DQ59

VSS94

GND2

2

1

+1.2V_DDR

2

DDR_A_D1DDR_A_D4

4

DQ4

6

DDR_A_D5

8

DQ0

10 12 14

DDR_A_D6

16

DQ6

18

DDR_A_D2

20

DQ2

22

DDR_A_D9

24 26

DDR_A_D8

28

DQ8

30

DDR_A_DQS#1

32

DDR_A_DQS1

34 36 38 40 42 44

DDR_A_D32

46 48

DDR_A_D33DDR_A_D36

50 52 54 56

DDR_A_D35

58 60

DDR_A_D39

62 64

DDR_A_D40

66 68

DDR_A_D41

70 72

DDR_A_DQS#5

74

DDR_A_DQS5

76 78

DDR_A_D42DDR_A_D43

80 82

DDR_A_D47

84 86 88 90 92 94 96 98 100 102 104 106

DDR4_DRAMRST#

108

DDR_A_CKE1

110 112

DDR_A_ACT#

114

DDR_A_ALERT#

116 118

DDR_A_MA11

120

A11

DDR_A_MA7

122

A7

124

DDR_A_MA5

126

A5

DDR_A_MA4

128

A4

130

DDR_A_MA2

132

A2

134 136

DDR_A_CLK1

138

DDR_A_CLK#1

140 142

DDR_A_MA0

144

A0

DDR_A_MA10

146 148

DDR_A_BS0

150

BA0

DDR_A_RAS#

152 154

DDR_A_CAS#

156

DDR_A_MA13

158

A13

160 162 164

DIMM_CHA_SA2

166

SA2

168

DDR_A_D17

170 172

DDR_A_D16

174 176 178 180

DDR_A_D22

182 184

DDR_A_D23

186 188

DDR_A_D26

190 192

DDR_A_D30

194 196

DDR_A_DQS#3

198

DDR_A_DQS3

200 202

DDR_A_D31DDR_A_D27

204 206

DDR_A_D28

208 210

DDR_A_D50

212 214

DDR_A_D54

216 218 220 222

DDR_A_D52

224 226

DDR_A_D55

228 230

DDR_A_D59

232 234

DDR_A_D62

236 238

DDR_A_DQS#7

240

DDR_A_DQS7

242 244

DDR_A_D63

246 248 250 252

PCH_SMBDATA

254

SDA

DIMM_CHA_SA0

256

SA0

258

VTT

DIMM_CHA_SA1

260

SA1

262

DDR_A_CKE1 <8>

DDR_A_ACT# <8> DDR_A_ALERT# <8>

DDR_A_CLK1 <8> DDR_A_CLK#1 <8>

DDR_A_BS0 <8> DDR_A_RAS# <8>

DDR_A_CAS# <8>

+1.2V_DDR

PCH_SMBDATA <6,15,18,29,35>

+V_DDR_REFA

CD96

1

0.1U_0402_10V6K

All VREF traces should have 10 mil trace width

2

+0.6VS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/08/25 2012/07/25

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

DDRIII DIMMA

Size Document Number Rev

Date: Sheet of

LA-E992P

1

14 77Tuesday, July 25, 2017

1.0(A00)

5

DDR_B_D[0..63]<8> DDR_B_MA[0..13]<8> DDR_B_DQS#[0..7]<8> DDR_B_DQS[0..7]<8>

Layout Note: Place near JDIMM2.257,259

D D

+2.5V_MEM +0.6VS +3VS

CD31

CD30

1

1U_0402_6.3V6K

2

Layout Note: Place near JDIMMB

CD28

CD27

1

1U_0402_6.3V6K

2

1

10U_0603_6.3V6M

2

Layout Note: Place near JDIMM2.258

CD32

CD89

CD90

1

1U_0402_6.3V6K

2

1

10U_0603_6.3V6M

2

+1.2V_DDR

CD20

CD19

1

1U_0402_6.3V6K

C C

2

CD22

CD21

1

1U_0402_6.3V6K

2

+1.2V_DDR

CD25

1

2

RH46

1 2

2_0402_1%

10U_0603_6.3V6M

CD26

1

2

+1.2V_DDR

CD23

CD24

1

10U_0603_6.3V6M

2

B B

+V_DDR_REFB_R

20mil

1

CH100

0.022U_0402_16V7K

2

12

RH212

A A

24.9_0402_1%

1U_0402_6.3V6K

10U_0603_6.3V6M

12

CD83

1

2

CD87

1

2

RH207 1K_0402_1%

+V_DDR_REFB

RH210 1K_0402_1%

CD81

1

1U_0402_6.3V6K

2

CD85

1

10U_0603_6.3V6M

2

CD82

CD80

1

2

1

2

1

1U_0402_6.3V6K

2

CD84

10U_0603_6.3V6M

SF000003100

CD86

CD33

1

10U_0603_6.3V6M

2

330U_2.5V_M

2

+3VS

DIMM_CHB_SA1

DIMM_CHB_SA2

DIMM_CHB_SA0

4

CD88

1

10U_0603_6.3V6M

2

DVT1.0 Change to SF000003100 OS-CON Cap.

1

+

2

Layout Note: Place near JDIMM2.255

CD34

CD35

1

0.1U_0402_10V6K

1

2.2U_0402_6.3V6M

2

+2.5V_MEM

3

+1.2V_DDR

DDR_B_D1

DDR_B_DQS#0 DDR_B_DQS0

DDR_B_D3

DDR_B_D2

DDR_B_D8

DDR_B_D12

DDR_B_D14 DDR_B_D11

DDR_B_D15 DDR_B_D10

DDR_B_D22

DDR_B_D23

DDR_B_DQS#2 DDR_B_DQS2

DDR_B_D21

DDR_B_D16

DDR_B_D25

DDR_B_D24

DDR_B_D31

DDR_B_D27 DDR_B_D30

DDR_B_CKE0<8>

DDR_B_BG1<8> DDR_B_BG0<8>

DDR_B_CLK0<8> DDR_B_CLK#0<8>

DDR_B_PAR<8> DDR_B_BS1<8>

DDR_B_CS#0<8> DDR_B_WE#<8>

DDR_B_ODT0<8> DDR_B_CS#1<8>

DDR_B_ODT1<8>

+3VS

PCH_SMBCLK<6,14,18,29,35>

DDR_B_CKE0

DDR_B_BG1 DDR_B_BG0

DDR_B_MA12 DDR_B_MA9

DDR_B_MA8 DDR_B_MA6

DDR_B_MA3 DDR_B_MA1

DDR_B_CLK0 DDR_B_CLK#0

DDR_B_PAR DDR_B_BS1

DDR_B_CS#0 DDR_B_WE#

DDR_B_ODT0 DDR_B_CS#1

DDR_B_ODT1

DDR_B_D32

DDR_B_D38

DDR_B_DQS#4 DDR_B_DQS4

DDR_B_D37

DDR_B_D39

DDR_B_D40

DDR_B_D45

+1.2V_DDR

DDR_B_D47 DDR_B_D46

DDR_B_D42

DDR_B_D52

DDR_B_D51

DDR_B_DQS#6 DDR_B_DQS6

DDR_B_D55

DDR_B_D50

DDR_B_D61

DDR_B_D57

+1.2V_DDR

DDR_B_D63

DDR_B_D58

PCH_SMBCLK

JDIMM2

1

VSS1

3

DQ5

5

VSS3

7

DQ1

9

VSS5

11

DQS0_c

13

DQS0_t

15

VSS8

17

DQ7

19

VSS10

21

DQ3

23

VSS12

25

DQ13

27

VSS14

29

DQ9

31

VSS16

33

DM1_n/DBI_n

35

VSS17

37

DQ15

39

VSS19

41

DQ10

43

VSS21

45

DQ21

47

VSS23

49

DQ17

51

VSS25

53

DQS2_c

55

DQS2_t

57

VSS28

59

DQ23

61

VSS30

63

DQ19

65

VSS32

67

DQ29

69

VSS34

71

DQ25

73

VSS36

75

DM3_n/DBI3_n

77

VSS37

79

DQ30

81

VSS39

83

DQ26

85

VSS41

87

CB5/NC

89

VSS43

91

CB1/NC

93

VSS45

95

DQS8_c

97

DQS8_t

99

VSS48

101

CB2/NC

103

VSS50

105

CB3/NC

107

VSS52

109

CKE0

111

VDD1

113

BG1

115

BG0

117

VDD3

119

A12

121

A9

123

VDD5

125

A8

127

A6

129

VDD7

131

A3

133

A1

135

VDD9

137

CK0_t

139

CK0_c

141

VDD11

143

PARITY

145

BA1

147

VDD13

149

CS0_n

151

WE_n/A14

153

VDD15

155

ODT0

157

CS1_n

159

VDD17

161

ODT1

163

VDD19

165

C1, CS3_n,NC

167

VSS53

169

DQ37

171

VSS55

173

DQ33

175

VSS57

177

DQS4_c

179

DQS4_t

181

VSS60

183

DQ38

185

VSS62

187

DQ34

189

VSS64

191

DQ44

193

VSS66

195

DQ40

197

VSS68

199

DM5_n/DBI5_n

201

VSS69

203

DQ46

205

VSS71

207

DQ42

209

VSS73

211

DQ52

213

VSS75

215

DQ49

217

VSS77

219

DQS6_c

221

DQS6_t

223

VSS80

225

DQ55

227

VSS82

229

DQ51

231

VSS84

233

DQ61

235

VSS86

237

DQ56

239

VSS88

241

DM7_n/DBI7_n

243

VSS89

245

DQ62

247

VSS91

249

DQ58

251

VSS93

253

SCL

255

VDDSPD

257

VPP1

259

VPP2

261

GND1

DEREN_40-42271-26001RHF CONN@

SP07001CW00

VSS2

VSS4

VSS6

DM0_n/DBI0_n

VSS7

VSS9

VSS11

DQ12

VSS13

VSS15

DQS1_c

DQS1_t

VSS18

DQ14

VSS20

DQ11

VSS22

DQ20

VSS24

DQ16

VSS26

DM2_n/DBI2_n

VSS27

DQ22

VSS29

DQ18

VSS31

DQ28

VSS33

DQ24

VSS35

DQS3_c

DQS3_t

VSS38

DQ31

VSS40

DQ27

VSS42

CB4/NC

VSS44

CB0/NC

VSS46

DM8_n/DBI_n/NC

VSS47

CB6/NC

VSS49

CB7/NC

VSS51

RESET_n

CKE1 VDD2

ACT_n

ALERT_n

VDD4

VDD6

VDD8

EVENT_n/NF

VDD10 CK1_t/NF CK1_c/NF

VDD12

A10/AP

VDD14

RAS_n/A16

VDD16

CAS_n/A15

VDD18

C0/CS2_n/NC

VREFCA

VSS54

DQ36

VSS56

DQ32

VSS58

DM4_n/DBI4_n

VSS59

DQ39

VSS61

DQ35

VSS63

DQ45

VSS65

DQ41

VSS67

DQS5_c

DQS5_t

VSS70

DQ47

VSS72

DQ43

VSS74

DQ53

VSS76

DQ48

VSS78

DM6_n/DBI6_n

VSS79

DQ54

VSS81

DQ50

VSS83

DQ60

VSS85

DQ57

VSS87

DQS7_c

DQS7_t

VSS90

DQ63

VSS92

DQ59

VSS94

GND2

2

1

+1.2V_DDR

2

DDR_B_D5DDR_B_D0

4

DQ4

6

DDR_B_D4

8

DQ0

10 12 14

DDR_B_D7

16

DQ6

18

DDR_B_D6

20

DQ2

22

DDR_B_D9

24 26

DDR_B_D13

28

DQ8

30

DDR_B_DQS#1

32

DDR_B_DQS1

34 36 38 40 42 44

DDR_B_D18

46 48

DDR_B_D19

50 52 54 56

DDR_B_D20

58 60

DDR_B_D17

62 64

DDR_B_D28

66 68

DDR_B_D29

70 72

DDR_B_DQS#3

74

DDR_B_DQS3

76 78

DDR_B_D26

80 82 84 86 88 90 92 94 96 98 100 102 104 106

DDR4_DRAMRST#

108

DDR_B_CKE1

110 112

DDR_B_ACT#

114

DDR_B_ALERT#

116 118

DDR_B_MA11

120

A11

A7

A5 A4

A2

A0

BA0

A13

SA2

SDA SA0 VTT SA1

DDR_B_MA7

122 124

DDR_B_MA5

126

DDR_B_MA4

128 130

DDR_B_MA2

132 134 136

DDR_B_CLK1

138

DDR_B_CLK#1

140 142

DDR_B_MA0

144

DDR_B_MA10

146 148

DDR_B_BS0

150

DDR_B_RAS#

152 154

DDR_B_CAS#

156

DDR_B_MA13

158 160 162 164

DIMM_CHB_SA2

166 168

DDR_B_D34

170 172

DDR_B_D36

174 176 178 180

DDR_B_D35

182 184

DDR_B_D33

186 188

DDR_B_D44

190 192

DDR_B_D41

194 196

DDR_B_DQS#5

198

DDR_B_DQS5

200 202 204 206

DDR_B_D43

208 210

DDR_B_D54

212 214

DDR_B_D48

216 218 220 222

DDR_B_D53

224 226

DDR_B_D49

228 230

DDR_B_D59

232 234

DDR_B_D62

236 238

DDR_B_DQS#7

240

DDR_B_DQS7

242 244

DDR_B_D60

246 248

DDR_B_D56

250 252

PCH_SMBDATA

254

DIMM_CHB_SA0

256 258

DIMM_CHB_SA1

260 262

DDR4_DRAMRST# <14> DDR_B_CKE1 <8>

DDR_B_ACT# <8> DDR_B_ALERT# <8>

DDR_B_CLK1 <8> DDR_B_CLK#1 <8>

DDR_B_BS0 <8> DDR_B_RAS# <8>

DDR_B_CAS# <8>

CD29

+1.2V_DDR

PCH_SMBDATA <6,14,18,29,35>

+V_DDR_REFB

1

0.1U_0402_10V6K

All VREF traces should have 10 mil trace width

2

+0.6VS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/08/25 2012/07/25

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

DDRIII DIMMB

Size Document Number Rev

Date: Sheet of

LA-E992P

1

15 77Tuesday, July 25, 2017

1.0(A00)

5

4

3

2

1

UH2C

AV2

CL_CLK

AV3

CL_DATA

AW2

CL_RST#

R44

D D

CAM_CBL_DET#

TBT_CIO_PLUG_EVENT#<39>

KB_BL_DET<25 >

PCIE_PTX_SSDRX_P11<29>

+3VS

PCIE_PTX_SSDRX_N11<29> PCIE_PRX_SSDTX_P11<29> PCIE_PRX_SSDTX_N11<29>

SATA_PTX_DRX_N1B<29>

SATA_PTX_DRX_P1B<29> SATA_PRX_DTX_N1B<29> SATA_PRX_DTX_P1B<29>

PCIE_PTX_SSDRX_P12<29>

PCIE_PTX_SSDRX_N12<29> PCIE_PRX_SSDTX_P12<29> PCIE_PRX_SSDTX_N12<29>

12

TPM@

RH561 10K_0402_5%

12

NON_TPM@

RH562 10K_0402_5%

EDP_HPD

PROJECT_ID1 PROJECT_ID2

12

SSD

HDD

C C

SSD

RV551 100K_0402_5%

B B

AMN@

RH557

10K_0402_5%

FSTR@

RH558

10K_0402_5%

TBT_CIO_PLUG_EVENT#

KB_BL_DET

PCIE_PTX_SSDRX_P11 PCIE_PTX_SSDRX_N11 PCIE_PRX_SSDTX_P11 PCIE_PRX_SSDTX_N11

SATA_PTX_DRX_N1B SATA_PTX_DRX_P1B SATA_PRX_DTX_N1B SATA_PRX_DTX_P1B

PCIE_PTX_SSDRX_P12 PCIE_PTX_SSDRX_N12 PCIE_PRX_SSDTX_P12 PCIE_PRX_SSDTX_N12

CPU_DDI1HPD<39> CPU_DDI2HPD<39> CPU_DDI3HPD<35>

EDP_HPD<38>

T91PAD@

R43 U39 N42

U43 U42

T94PAD@

U41 M44 U36 P44 T45 T44

B33 C33 K31 L31

AB33 AB35 AA44 AA45

B38 C38 D39 E37

C36 B36 G35 E35

A35 B35 H33 G33

K44 N38 N39 H44 H43 L39 L37

CPU_DDI1HPD CPU_DDI2HPD CPU_DDI3HPD

EDP_HPD

GPP_G8/FAN_PWM_0 GPP_G9/FAN_PWM_1 GPP_G10/FAN_PWM_2 GPP_G11/FAN_PWM_3

GPP_G0/FAN_TACH_0 GPP_G1/FAN_TACH_1 GPP_G2/FAN_TACH_2 GPP_G3/FAN_TACH_3 GPP_G4/FAN_TACH_4 GPP_G5/FAN_TACH_5 GPP_G6/FAN_TACH_6 GPP_G7/FAN_TACH_7

PCIE11_TXP PCIE11_TXN PCIE11_RXP PCIE11_RXN

GPP_F10/SCLOCK GPP_F11/SLOAD GPP_F13/SDATAOUT0 GPP_F12/SDATAOUT1

PCIE14_TXN/SATA1B_TXN PCIE14_TXP/SATA1B_TXP PCIE14_RXN/SATA1B_RXN PCIE14_RXP/SATA1B_RXP

PCIE13_TXN/SATA0B_TXN PCIE13_TXP/SATA0B_TXP PCIE13_RXN/SATA0B_RXN PCIE13_RXP/SATA0B_RXP

PCIE12_TXP PCIE12_TXN PCIE12_RXP PCIE12_RXN

J45

PCIE20_TXP PCIE20_TXN PCIE20_RXP PCIE20_RXN PCIE19_TXP PCIE19_TXN PCIE19_RXP PCIE19_RXN

SKY-H-PCH_BGA837

@

AW4

AY2 AV4 BA4

BD7

UH2E

GPP_I0/DDPB_HPD0 GPP_I1/DDPC_HPD1 GPP_I2/DDPD_HPD2 GPP_I3/DDPE_HPD3

GPP_I4/EDP_HPD

SKY-H-PCH_BGA837

@

SKY-S-PCH_BGA837

CLINK

PCIE10_RXN/SATA1A_RXN PCIE10_RXP/SATA1A_RXP

FAN

3 OF 12 REV = 1.3

SKY-S-PCH_BGA837

PCIE10_TXN/SATA1A_TXN PCIE10_TXP/SATA1A_TXP

PCIe/SATA

GPP_E0/SATAXPCIE0/SATAGP0 GPP_E1/SATAXPCIE1/SATAGP1 GPP_E2/SATAXPCIE2/SATAGP2 GPP_F0/SATAXPCIE3/SATAGP3 GPP_F1/SATAXPCIE4/SATAGP4 GPP_F2/SATAXPCIE5/SATAGP5 GPP_F3/SATAXPCIE6/SATAGP6 GPP_F4/SATAXPCIE7/SATAGP7

HOST

GPP_I8/DDPC_CTRLDATA

GPP_I6/DDPB_CTRLDATA

GPP_I10/DDPD_CTRLDATA

5 OF 12 REV = 1.3

PCIE9_RXN/SATA0A_RXN PCIE9_RXP/SATA0A_RXP PCIE9_TXN/SATA0A_TXN

PCIE9_TXP/SATA0A_TXP

PCIE15_RXN/SATA2_RXN PCIE15_RXP/SATA2_RXP

PCIE15_TXN/SATA2_TXN PCIE15_TXP/SATA2_TXP

PCIE16_RXN/SATA3_RXN PCIE16_RXP/SATA3_RXP

PCIE16_TXN/SATA3_TXN PCIE16_TXP/SATA3_TXP

PCIE17_RXN/SATA4_RXN PCIE17_RXP/SATA4_RXP

PCIE17_TXN/SATA4_TXN PCIE17_TXP/SATA4_TXP

PCIE18_RXN/SATA5_RXN PCIE18_RXP/SATA5_RXP

PCIE18_TXN/SATA5_TXN PCIE18_TXP/SATA5_TXP

GPP_E8/SATALED#

GPP_F21/EDP_BKLTCTL

GPP_F20/EDP_BKLTEN

GPP_F19/EDP_VDDEN

THERMTRIP#

PECI

PM_SYNC

PLTRST_CPU#

PM_DOWN

GPP_I7/DDPC_CTRLCLK

GPP_I5/DDPB_CTRLCLK

GPP_I9/DDPD_CTRLCLK

GPP_F14 GPP_F23 GPP_F22

GPP_G23 GPP_G22 GPP_G21 GPP_G20 GPP_H23

SATA_PRX_SSDTX_N0A

G31

SATA_PRX_SSDTX_P0A

H31

SATA_PTX_SSDRX_N0A

C31

SATA_PTX_SSDRX_P0A

B31

PCIE_PRX_SSDTX_N10

G29

PCIE_PRX_SSDTX_P10

E29

PCIE_PTX_SSDRX_N10

C32

PCIE_PTX_SSDRX_P10

B32

F41 E41 B39 A39

D43 E42 A41 A40

H42 H40 E45 F45

K37 G37 G45 G44

PCH_SATA_LED#

AD44

mCARD_PCIE_SATA#

AG36 AG35

T182 PAD @

AG39 AD35 AD31 AD38 AC43 AB44

BIA_PWM_PCH

W36

L_BKLT_EN_EC

W35

ENVDD_PCH

W42

H_THERMTRIP#

AJ3 AL3

PECI H_PM_SYNC

AJ4

PLTRST_CPU#

AK2

H_PM_DOWN

AH2

BB3

DDI2_DDPC_CTRLDAT

BD6 BA5

DDI1_DDPB_CTRLDAT

BC4 BE5

DDI3_DDPD_CTRLDAT

BE6

PROC_DETECT#

Y44 V44 W39

PROJECT_ID2

L43

PROJECT_ID1

L44

LCD_DBC

U35 R35 BD36

SATA_PRX_SSDTX_N0A <29> SATA_PRX_SSDTX_P0A <29> SATA_PTX_SSDRX_N0A <29> SATA_PTX_SSDRX_P0A <29>

PCIE_PRX_SSDTX_N10 <29> PCIE_PRX_SSDTX_P10 <29> PCIE_PTX_SSDRX_N10 <29> PCIE_PTX_SSDRX_P10 <29>

PCH_SATA_LED# <37>

mCARD_PCIE_SATA# <29>

BIA_PWM_PCH <7,38> L_BKLT_EN_EC <36> ENVDD_PCH <42>

1 2

RH191 620_0402_5%

1 2

RH138 13_0402_5% RH189

1 2

T2 PAD@

T8 PAD

30_0402_5%

PLTRST_CPU# <6,9> H_PM_DOWN <9>

PROC_DETECT# <9>

@

SSD

H_THERMTRIP#_R PECI_EC H_PM_SYNC_R

+3VS

12

RH559

LCD_DBC

H_THERMTRIP#_R <9> PECI_EC <9,36> H_PM_SYNC_R <9>

10K_0402_5%

12

@

RH560 10K_0402_5%

mCARD_PCIE_SATA#

CAM_CBL_DET#

PCH_SATA_LED#

PCH Strap PIN

DDI3_DDPD_CTRLDAT

DDI2_DDPC_CTRLDAT

DDI1_DDPB_CTRLDAT

RH68

RH79

RH80

RH141

RH579

RH580

1 2

10K_0402_5%

1 2

10K_0402_5%

1 2

10K_0402_5%

1 2

2.2K_0402_5%

1 2

2.2K_0402_5%

1 2

2.2K_0402_5%

+3VALW

+3VS

A A

DVT1.0 Change RH557 BS to AMN@. Change RH558 BS to FSTR@

PROJECT ID

Firestar Armani

PROJECT ID1 (GPP_G22)

0 1

5

TPM ID

SW TPM HW TPM

PROJECT ID2 (GPP_G23)

0 1

Security Classification

2011/08/25 2012/07/25

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/08/25 2012/07/25

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PCH (1/8) SATA,HDA

LA-E992P

1

1.0(A00)

16 77Tuesday, July 25, 2017

5

+3VS

RP3

RH74

RH568

991@EMI@

LAN_CLKREQ# VGA_CLK_REQ# WLAN_CLK_REQ# SSD_CLK_REQ#

PCH_SPI_CS#

TPM_PIRQ#

RH582

0_0402_5%

SD028000080

PCH_SPI_CLK_R1<27>

992@EMI@

10P_0402_25V8J

PCH_SPI_CLK_R1

@RF@

CH215

CPU_24MHZ_P<9> CPU_24MHZ_N<9>

PCH_CPU_BCLK_P<9> PCH_CPU_BCLK_N<9>

LAN_CLKREQ#<33> WLAN_CLK_REQ#<28>

TBT_CLK_REQ#<39> SSD_CLK_REQ#<29> VGA_CLK_REQ#<46>

RH582 15_0402_5%@EMI@

1

2

+1VALW

PCH_SPI_SI<6,27>

1 2

PCH_SPI_WP#<6>

PCH_SPI_CS2#<27>

4 5 3 6 2 7 1 8

10K_0804_8P4R_5%

D D

+3V_ROM

1 2

4.7K_0402_5%

C C

+3VALW

RH582

1 2

10K_0402_5%

15_0402_5%

SD028150A80

DVT1.0 Add RH582 BOM option for LA-E991P and LA-E992P EA difference.

B B

Reserve for RF

SPI ROM FOR ME ( 16MByte )

DVT2.0 Change RH101 to 0ohm 0402 short-pad footprint.

PCH_SPI_CS#

A A

PCH_SPI_CLK_R1 PCH_SPI_SO PCH_SPI_SO_R

PCH

PCH_SPI_SI PCH_SPI_WP#

1 2

RH101 0_0402_5%@

1 2

RE126 33_0402_5%

1 2

RE127 33_0402_5%

1 2

RE128 33_0402_5%

1 2

RE129 33_0402_5%

1 2

RE71 33_0402_5%

Close to UH8

5

PCH_SPI_CS#_R PCH_SPI_SO_R PCH_SPI_WP#_R

PCH_SPI_CLK_R

PCH_SPI_SI_R PCH_SPI_WP#_R PCH_SPI_HOLD#_RPCH_SPI_HOLD#

4

UH2G

2.7K_0402_1%

+3V_ROM+3VALW

12

8

PCH_SPI_HOLD#_R

7

PCH_SPI_CLK_R

6

PCH_SPI_SI_R

5

AR17

GPP_A16/CLKOUT_48

G1

CLKOUT_CPUNSSC_P

F1

CLKOUT_CPUNSSC

G2

CLKOUT_CPUBCLK_P

H2

CLKOUT_CPUBCLK

A5

XTAL24_OUT

A6

XTAL24_IN

E1

XCLK_BIASREF

BC9

RTCX1

BD10

RTCX2

BC24

GPP_B5/SRCCLKREQ0#

AW24

GPP_B6/SRCCLKREQ1#

AT24

GPP_B7/SRCCLKREQ2#

BD25

GPP_B8/SRCCLKREQ3#

BB24

GPP_B9/SRCCLKREQ4#

BE25

GPP_B10/SRCCLKREQ5#

AT33

GPP_H0/SRCCLKREQ6#

AR31

GPP_H1/SRCCLKREQ7#

BD32

GPP_H2/SRCCLKREQ8#

BC32

GPP_H3/SRCCLKREQ9#

BB31

GPP_H4/SRCCLKREQ10#

BC33

GPP_H5/SRCCLKREQ11#

BA33

GPP_H6/SRCCLKREQ12#

AW33

GPP_H7/SRCCLKREQ13#

BB33

GPP_H8/SRCCLKREQ14#

BD33

GPP_H9/SRCCLKREQ15#

R13

CLKOUT_PCIE_N15

R11

CLKOUT_PCIE_P15

P1

CLKOUT_PCIE_N14

R2

CLKOUT_PCIE_P14

W7

CLKOUT_PCIE_N13

Y5

CLKOUT_PCIE_P13

U2

CLKOUT_PCIE_N12

U3

CLKOUT_PCIE_P12

SKY-H-PCH_BGA837

@

UH2A

BD17

GPP_A11/PME#

AG15

RSVD_AG15

AG14

RSVD_AG14

AF17

RSVD_AF17

AE17

RSVD_AE17

AR19

TP5

AN17

TP4

BB29

SPI0_MOSI

BE30

SPI0_MISO

BD31

SPI0_CS0#

BC31

SPI0_CLK

AW31

SPI0_CS1#

BC29

SPI0_IO2

BD30

SPI0_IO3

AT31

SPI0_CS2#

AN36

GPP_D1/SPI1_CLK

AL39

GPP_D0/SPI1_CS#

AN41

GPP_D3/SPI1_MOSI

AN38

GPP_D2/SPI1_MISO

AH43

GPP_D22/SPI1_IO3

AG44

GPP_D21/SPI1_IO2

SKY-H-PCH_BGA837

@

DVT2.0 Change RH121 to 0ohm 0603 short-pad footprint.

T92PAD@

CPU_24MHZ_P CPU_24MHZ_N

PCH_CPU_BCLK_P PCH_CPU_BCLK_N

XTAL24_OUT XTAL24_IN

1 2

RH71

PCH_RTCX1 PCH_RTCX2

LAN_CLKREQ# WLAN_CLK_REQ#

TBT_CLK_REQ# SSD_CLK_REQ# VGA_CLK_REQ#

T17PAD@

PCH_SPI_SI

PCH_SPI_SO<27>

FFS_INT2<29> TPM_PIRQ#<27>

UH8

1

/CS

2

DO(IO1)

3

/WP(IO2)

4

GND

MX25L12873FM2I-10G_SOP_8P

W25Q128FVSIQ_SO8

SA00006O300

DVT1.0 Change UH8 to SA00006O300 due to SA00005VV10 and SA00008KK00 EOL

PCH_SPI_SO PCH_SPI_CS# PCH_SPI_CLK

PCH_SPI_WP# PCH_SPI_HOLD# PCH_SPI_CS2#

FFS_INT2 TPM_PIRQ#

RH121

0_0603_5%

VCC

/HOLD(IO3)

CLK

DI(IO0)

@

SPI ROM

4

SKY-S-PCH_BGA837

7 OF 12 REV = 1.3

SKY-S-PCH_BGA837

1 OF 12 REV = 1.3

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

CLKOUT_ITPXDP

CLKOUT_ITPXDP_P

CLKOUT_CPUPCIBCLK

CLKOUT_CPUPCIBCLK_P

CLKOUT_PCIE_N0 CLKOUT_PCIE_P0

CLKOUT_PCIE_N1 CLKOUT_PCIE_P1

CLKOUT_PCIE_N2 CLKOUT_PCIE_P2

CLKOUT_PCIE_N3 CLKOUT_PCIE_P3

CLKOUT_PCIE_N4 CLKOUT_PCIE_P4

CLKOUT_PCIE_N5 CLKOUT_PCIE_P5

CLKOUT_PCIE_N6 CLKOUT_PCIE_P6

CLKOUT_PCIE_N7 CLKOUT_PCIE_P7

CLKOUT_PCIE_N8 CLKOUT_PCIE_P8

CLKOUT_PCIE_N9 CLKOUT_PCIE_P9

CLKOUT_PCIE_N10 CLKOUT_PCIE_P10

CLKOUT_PCIE_N11 CLKOUT_PCIE_P11

GPP_B13/PLTRST#

GPP_G16/GSXCLK

GPP_G12/GSXDOUT

GPP_G13/GSXSLOAD

GPP_G14/GSXDIN

GPP_G15/GSXSRESET#

GPP_E3/CPU_GP0 GPP_E7/CPU_GP1 GPP_B3/CPU_GP2 GPP_B4/CPU_GP3

GPP_H18/SML4ALERT#

GPP_H17/SML4DATA

GPP_H16/SML4CLK

GPP_H15/SML3ALERT#

GPP_H14/SML3DATA

GPP_H13/SML3CLK

GPP_H12/SML2ALERT#

GPP_H11/SML2DATA

GPP_H10/SML2CLK

INTRUDER#

3

2

PCH_XDP_CLK_N

L1

PCH_XDP_CLK_P

L2

PCH_CPU_PCIBCLK_N

J1

PCH_CPU_PCIBCLK_P

J2

N7 N8

L7 L5

CLK_PCIE_LAN#

D3

CLK_PCIE_LAN

F2

CLK_PCIE_WLAN#

E5

CLK_PCIE_WLAN

G4

D5 E6

CLK_PCIE_N5

D8

CLK_PCIE_P5

D7

CLK_PCIE_SSD#

R8

CLK_PCIE_SSD

R7

CLK_PEG_GPU#

U5

CLK_PEG_GPU

U7

W10 W11

N3 N2

P3 P2

R3 R4

PCH_PLTRST#

BB27

TBT_FORCE_PWR

P43

RTD3_CIO_PWR_EN

R39 R36 R42 R41

AF41

TOUCH_SCREEN_PD#

AE44

TOUCHPAD_INTR#

BC23

GC6_THM_DIS#

BD24

BC36 BE34 BD39 BB36 BA35 BC35 BD35 AW35 BD34

BE11

INTRUDER#

PCH_PLTRST#

SA00000OH00

MC74VHC1G08DFT2G_SC70-5

2011/08/25 2012/07/25

1

IN1

2

IN2

Compal Secret Data

TBT_FORCE_PWR <39> RTD3_CIO_PWR_EN <39>

TOUCH_SCREEN_PD# <38>

GC6_THM_DIS# <36>

RH1

1 2

@

0_0402_5%

+3VS

5

UH7

VCC

OUT

GND

3

Deciphered Date

PCH_XDP_CLK_N <6> PCH_XDP_CLK_P <6>

PCH_CPU_PCIBCLK_N <9> PCH_CPU_PCIBCLK_P <9>

CLK_PCIE_LAN# <33> CLK_PCIE_LAN < 33>

CLK_PCIE_WLAN# <28> CLK_PCIE_WLAN <28>

CLK_PCIE_N5 <39> CLK_PCIE_P5 <39>

CLK_PCIE_SSD# <2 9> CLK_PCIE_SSD <29 >

CLK_PEG_GPU# <46> CLK_PEG_GPU <46>

XTAL24_OUT

XTAL24_IN

4

PCH_PLTRST#_EC

12

RH77 100K_0402_5%

2

RH570 33_0201_5%EMI@

RH569 33_0201_5%EMI@

PCH_RTCX2

PCH_RTCX1

LAN

NGFF - WLAN

TBT-AR

NGFF - SSD

GPU

1 2

TOUCH_SCREEN_PD#

TOUCHPAD_INTR#

GC6_THM_DIS#

Need SW confirm!!!

INTRUDER#

Pilot Change DH1 footprint to AZ5125-01HPR7G_SOD523-2

TOUCHPAD_INTR# PTP_INT#

PCH_PLTRST#

PCH_PLTRST#_EC <27,28,29,33,36,39,46>

1

RTC CRYSTAL

1 2

RH70 10M_0402_5%

YH1

32.768KHZ 9PF 20PPM 9H03280012

1 2

SJ10000Q400

Max Crystal ESR

1

= 50k Ohm.

CH45

8.2P_0402_50V8D

2

XTAL24_OUT_R

XTAL24_IN_R

PCH CRYSTAL

1 2

1M_0402_5%

24MHZ_12PF_X3G024000DC1H

SJ10000CS00

123

1

CH47 15P_0402_50V8J

2

1 2

RH69 10K_0402_5%

1 2

RH179 10K_0402_5%

1 2

RH573 10K_0402_5%

1 2

RH143 1M_0402_5%

DH1

12

RB751S40T1G_SOD523-2

AZ5125-01HPR7G_SOD523-2

Reserve for ESD

1 2

CH208 100P_0402_50V8J

@ESD@

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PCH (2/8) SMBUS, CLK, SPI, LPC

RH72

4

YH2

LA-E992P

1

CH46

8.2P_0402_50V8D

2

1

2

+3VS

+RTCVCC

17 77Tuesday, July 25, 2017

CH48 15P_0402_50V8J

PTP_INT# <26,36>

1.0(A00)

5

+3VALW

1 2

RH21 1K_0402_5%

1 2

RH22 1K_0402_5%

1 2

RH62 499_0402_1%

1 2

RH63 499_0402_1%

+3VS

1 2

RH27 1K_0402_5%

1 2

RH26 1K_0402_5%

1 2

RH86 10K_0402_5%

D D

1 2

RH13 100K_0402_5%

1 2

RH581 100K_0402_5%

RTCRST_ON<36>

RH571

100K_0402_5%

C C

QH4A

2

DMN65D8LDW-7_SOT363-6

SMBCLK

SMBDATA

Buffer with Open Drain Output For VTT power control

B B

A A

6 1

3 4

QH4B DMN65D8LDW-7_SOT363-6

UC16

1

ME_FWP<36>

NC

2

A

3

GND

74AUP1G07SE-7_SOT353

SA00007WE00

VR_ON

Service Mode Switch: Add a switch to ME_FWP signal to unlock the ME region and allow the entire region of the SPI flash to be updated using FPT.

SMBCLK SMBDATA

SML0_SMBCLK SML0_SMBDATA

PCH_SMBCLK PCH_SMBDATA

DGPU_PWROK

PCH_RSMRST# SYS_PWROK

13

D

2

G

12

ME_FWP

S

+3VS

5

+3VALW

12

CC2980.1U_0402_16V7K

5

VCC

4

Y

RH18 1K_0402_5%

HDA_SDOUT_AUDIO<23>

HDA_SYNC_AUDIO<23>

HDA_BITCLK_AUDIO<23>

HDA_SDIN0_AUDIO<23>

AUD_AZA_CPU_SDO<7>

AUD_AZA_CPU_SDI_R<7>

AUD_AZA_CPU_SCLK<7>

PCH_RTCRST#

DVT1.0 Change QH6 to SB00000PU00

QH6 L2N7002LT1G_SOT23-3

PCH_RSMRST#<6,36>

PCH to DDR

PCH_SMBCLK

PCH_SMBDATA

H_VCCST_PWRGD

1 2

PCH_SMBCLK <6,14,15,29, 35>

PCH_SMBDATA <6,14,15,29,35>

H_VCCST_PWRGD <6,9> VR_ON <71>

HDA_SDOUT

1 2

HDA_SDOUT_AUDIO HDA_SDOUT

HDA_SYNC_AUDIO HDA_SYNC

CH5010P_0402_25V8J @EMI@

AUD_AZA_CPU_SCLK

DVT2.0 Change RH9, RH503 to 0ohm 0402 short-pad footprint.

PCH_RSMRST#

ME_FWP PCH has internal 20K PD.

FLASH DESCRIPTOR SECURITY OVERRIDE

Disable ME Protect (ME can be updated) Enable ME Protect (ME cannot be updated)(Default position)

5

GPU_THM_SMBCLK<27,36,46>

GPU_THM_SMBDAT<27,36,46>

4

1 2

Close to PCH

RH146

RH147

DGPU_PWROK<46,55,69>

RH503 0_0402_5%

RH9

+VCCIO_PG<74>

IMVP_VR_PG<71>

ALL_SYS_PWRGD<18,36,61>

IMVP_VR_ON<36>

RH552

10K_0402_5%

SD028100280

RH554

10K_0402_5%

SD028100280

4

RP15

1 8 2 7 3 6 4 5

33_0804_8P4R_5%

RH57233_0402_5% EMI@

1 2

30_0402_5%

1 2

30_0402_5%

1 2

@

1 2

@

0_0402_5%

MC74VHC1G08DFT2G_SC70-5

GPU ID

N/A N17P-G0 N17E-G1 N17P-G1

UMA@

3

UH2D

HDA_BITCLK

HDA_SDIN0_AUDIO

HDA_SDOUT HDA_SYNC

AUD_AZA_CPU_SDO_RAUD_AZA_CPU_SDO AUD_AZA_CPU_SDI_R AUD_AZA_CPU_SCLK_R

GPU_ID2 GPU_ID1

DGPU_PWROK

PCH_RTCRST# PCH_SRTCRST#

PCH_PWROK PCH_RSMRST#_R AC_PRESENT

PCH_DPWROK SMBALERT# SMBCLK SMBDATA SML0ALERT# SML0_SMBCLK SML0_SMBDATA SML1ALERT# GPU_THM_SMBCLK GPU_THM_SMBDAT

IMVP_VR_PG

ALL_SYS_PWRGD

IMVP_VR_ON

SIO_SLP_S3#

SA00000OH00

GPU ID2 (GPP_D6)

0 0 1 1

RH551

N17P_G0@

10K_0402_5%

SD028100280

RH554

N17P_G0@

10K_0402_5%

SD028100280

BA9

HDA_BCLK

BD8

HDA_RST#

BE7

HDA_SDI0

BC8

HDA_SDI1

BB7

HDA_SDO

BD9

HDA_SYNC

BD1

RSVD_BD1

BE2

RSVD_BE2

AM1

DISPA_SDO

AN2

DISPA_SDI

AM2

DISPA_BCLK

AL42

GPP_D8/SSP0_SCLK

AN42

GPP_D7/SSP0_RXD

AM43

GPP_D6/SSP0_TXD

AJ33

GPP_D5/SSP0_SFRM

AH44

GPP_D20/DMIC_DATA0

AJ35

GPP_D19/DMIC_CLK0

AJ38

GPP_D18/DMIC_DATA1

AJ42

GPP_D17/DMIC_CLK1

BC10

RTCRST#

BB10

SRTCRST#

AW11

PCH_PWROK

BA11

RSMRST#

AV11

DSW_PWRO K

BB41

GPP_C2/SMBALERT#

AW44

GPP_C0/SMBCLK

BB43

GPP_C1/SMBDATA

BA40

GPP_C5/SML0ALERT#

AY44

GPP_C3/SML0CLK

BB39

GPP_C4/SML0DATA

AT27

GPP_B23/SML1ALERT#/PCHHOT#

AW42

GPP_C6/SML1CLK

AW45

GPP_C7/SML1DATA

SKY-H-PCH_BGA837

@

+3VS

12

RH180 100K_0402_5%

RH103

1 2

MC74VHC1G08DFT2G_SC70-5

RH105

1 2

@

0_0402_5%

DVT2.0 Change RH103, RH105 to 0ohm 0402 short-pad footprint.

SA00000OH00

+3VALW

5

UZ21

1

VCC

IN1

OUT

2

IN2

GND

3

AUDIO

ALL_SYS_PWRGD+VCCIO_PG

@

+3VS

5

1

VCC

IN1

2

IN2

GND

3

4

12

RZ71 100K_0402_5%

GPU ID1 (GPP_D5)

0 1 0 1

RH551

RH552

N17E_G1@

10K_0402_5%

SD028100280

RH553

N17E_G1@

10K_0402_5%

SD028100280

N17P_G1@

10K_0402_5%

SD028100280

RH553

N17P_G1@

10K_0402_5%

SD028100280

SKY-S-PCH_BGA837

GPP_B1 GPP_B0

GPP_B11

SYS_PWROK

WAKE#

SLP_LAN#

SLP_SUS#

SYS_RESET#

ITP_PMODE

JTAGX JTAG_TMS JTAG_TDO

JTAG_TDI

JTAG_TCK

BB17 AW22

AR15

AV13

H_DRAMRST#

BC14 BD23

LAN_DISABLE#_R

AL27 AR27 N44 AN24

SYS_PWROK

AY1

PCH_PCIE_WAKE#

BC13 BC15 AV15

SIO_SLP_S0#

BC26

SIO_SLP_S3#

AW15

SIO_SLP_S4#

BD15

SIO_SLP_S5#

BA13

AN15

SUSCLK PCH_BATLOW#

BD13 BB19

ME_SUS_PWR_ACK

BD19

LAN_WAKE#

BD11 BB15 BB13

SIO_PWRBTN#

AT13

SYS_RESET#

AW1 BD26

SPKR H_CPUPWRGD

AM3

PCH_ITP_PMODE

AT2

PCH_JTAGX CPU_XDP_TCK

AR3

PCH_JTAG_TMS

AR2

PCH_JTAG_TDO

AP1

PCH_JTAG_TDI

AP2

PCH_JTAG_TCK

AN3

+RTCVCC

1 2

RH83 20K_0402_5%

+RTCVCC

1 2

RH84 20K_0402_5%

UH14

OUT

VR_ON

GPP_A12/BMBUSY#/ISH_GP6/SX_EXIT_HOLDOFF#

GPP_A13/SUSWARN#/SUSPW RDNACK

SMBUS

JTAG

4 OF 12REV = 1.3

ALL_SYS_PWRGD <18,36,61>

PCH_PWROK

4

12

RH94 10K_0402_5%

GPP_A8/CLKRUN#

GPD11/LANPHYPC

GPD9/SLP_WLAN#

DRAM_RESET#

GPP_B2/VRALERT#

GPP_G17/ADR_COMPLETE

GPD6/SLP_A#

GPP_B12/SLP_S0#

GPD4/SLP_S3# GPD5/SLP_S4#

GPD10/SLP_S5#

GPD8/SUSCLK

GPD0/BATLOW#

GPP_A15/SUSACK#

GPD2/LAN_WAKE#

GPD1/ACPRESENT

GPD3/PWRBTN#

GPP_B14/SPKR

PROCPWRGD

Reserve for ESD

CH212 100P_0402_50V8J

+3VS

12

10K_0402_5%

12

10K_0402_5%

@

RH553

@

RH554

12

GPU_ID1 GPU_ID2

12

2011/08/25 2012/07/25

@

RH551

10K_0402_5%

@

RH552

10K_0402_5%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

CH209 100P_0402_50V8J

Reserve for RF please close to UH1

Compal Secret Data

Deciphered Date

2

H_DRAMRST# <14>

LAN_DISABLE#_R <33>

SYS_PWROK <6,36>

1 2

RH114

@

0_0402_5%

SIO_SLP_S0# <27> SIO_SLP_S3# <38,39,42,43,44,62> SIO_SLP_S4# <42,43,63>

SUSCLK <28,29,36>

DVT2.0 Change RH11 to 0ohm 0402 short-pad footprint.

1 2

RH11 0_0402_5%@ DV1

12

RB751S40T1G_SOD523-2 AZ5125-01HPR7G_SOD523-2

SIO_PWRBTN# <6,36> SYS_RESET# <6> SPKR <23> H_CPUPWRGD <9>

PCH_ITP_PMODE <6>

PCH_JTAG_TMS <6> PCH_JTAG_TDO <6> PCH_JTAG_TDI <6> PCH_JTAG_TCK <6>

RTC Reset

CH52

1U_0402_6.3V6K

CH53

1U_0402_6.3V6K

12

ESD@

12

@ESD@

1 2

CH51 10P_0402_25V8J

@RF@

2

PCH_SRTCRST#

12

PCH_RTCRST#

12

PCH_PCIE_WAKE# PCH_BATLOW# LAN_WAKE# AC_PRESENT

SYS_RESET#

ME_SUS_PWR_ACK

DVT2.0 Change RH114 to 0ohm 0402 short-pad footprint.

PCIE_WAKE#

LANWAKE# ACAV_IN

PCIE_WAKE# <28,33,36,39>

LANWAKE# <36>

Pilot

DVT2.0 Change RH38 to 0ohm 0402 short-pad footprint.

RH38

1 2

@

0_0402_5%

Change DV1 footprint to AZ5125-01HPR7G_SOD523-2

+3VALW

RH66 2.2K_0402_5%@

TLS CONFIDENTIALITY

HIGH LOW(DEFAULT)

+3VALW

CLRP1 SHORT PADS

@

PCH_RSMRST#

SYS_RESET#

HDA_SDOUT

Title

Size Document Number Rev

Date: Sheet of

RH64 2.2K_0402_5%

EC interface

HIGH LOW(DEFAULT)

+3VALW

RH65 150K_0402_5%

PCHHOT#

HIGH LOW(DEFAULT)

+3VALW

RH82 2.2K_0402_5%@

Top Swap Override (internal PD)

HIGH LOW(DEFAULT)

Compal Electronics, Inc.

PCH (3/8) DMI,FDI,PM,GFX,DP

1

1 2

RH17 1K_0402_5%

1 2

RH81 10K_0402_5%

1 2

RH181 10K_0402_5%

1 2

RH125 100K_0402_5%

1 2

RH193 8.2K_0402_5%@

1 2

RH67 1M_0402_5%@

T4938 PAD @

ACAV_IN <36,59,60>

CPU_XDP_TCK <6,9>

1 2

Enable Disable

1 2

ESPI LPC

1 2

Enable Disable

1 2

ENABLE DISABLE

LA-E992P

1

SMBALERT#

SML0ALERT#

SML1ALERT#

SPKR

18 77Tuesday, July 25, 2017

+3V_PCH_DSW

+3VALW

+1.8V_PRIM

1.0(A00)

5

4

3

2

1

DMI_CTX_PRX_N0<7>

D D

TBT-AR

C C

LAN

NGFF

DMI_CTX_PRX_P0<7>

DMI_CRX_PTX_N0<7>

DMI_CRX_PTX_P0<7> DMI_CTX_PRX_N1<7> DMI_CTX_PRX_P1<7>

DMI_CRX_PTX_N1<7>

DMI_CRX_PTX_P1<7> DMI_CTX_PRX_N2<7> DMI_CTX_PRX_P2<7>

DMI_CRX_PTX_N2<7>

DMI_CRX_PTX_P2<7> DMI_CTX_PRX_N3<7> DMI_CTX_PRX_P3<7>

DMI_CRX_PTX_N3<7>

DMI_CRX_PTX_P3<7>

1 2

RH108

PCIE_PRX_TBTTX_N1<39> PCIE_PRX_TBTTX_P1<39>

PCIE_PRX_TBTTX_N2<39> PCIE_PRX_TBTTX_P2<39> PCIE_PRX_TBTTX_N3<39> PCIE_PRX_TBTTX_P3<39>

PCIE_PRX_TBTTX_N4<39> PCIE_PRX_TBTTX_P4<39>

PCIE_PRX_LANTX_N5<33> PCIE_PRX_LANTX_P5<33>

PCIE_PRX_WLANTX_N6<28 > PCIE_PRX_WLANTX_P6<28>

100_0402_1%

PCIE_PTX_TBTRX_N1<39>

PCIE_PTX_TBTRX_P1<39>

PCIE_PTX_TBTRX_N2<39>

PCIE_PTX_TBTRX_P2<39>

PCIE_PTX_TBTRX_N3<39>

PCIE_PTX_TBTRX_P3<39>

PCIE_PTX_TBTRX_N4<39>

PCIE_PTX_TBTRX_P4<39>

PCIE_PTX_LANRX_N5<33>

PCIE_PTX_LANRX_P5<33>

PCIE_PTX_WLANRX_N6<28 >

PCIE_PTX_WLANRX_P6<28>

DMI_CTX_PRX_N0 DMI_CTX_PRX_P0 DMI_CRX_PTX_N0 DMI_CRX_PTX_P0 DMI_CTX_PRX_N1 DMI_CTX_PRX_P1 DMI_CRX_PTX_N1 DMI_CRX_PTX_P1 DMI_CTX_PRX_N2 DMI_CTX_PRX_P2 DMI_CRX_PTX_N2 DMI_CRX_PTX_P2 DMI_CTX_PRX_N3 DMI_CTX_PRX_P3 DMI_CRX_PTX_N3 DMI_CRX_PTX_P3

PCIE_RCOMPN PCIE_RCOMPP

PCIE_PRX_TBTTX_N1 PCIE_PRX_TBTTX_P1 PCIE_PTX_TBTRX_N1 PCIE_PTX_TBTRX_P1 PCIE_PTX_TBTRX_N2 PCIE_PTX_TBTRX_P2 PCIE_PRX_TBTTX_N2 PCIE_PRX_TBTTX_P2 PCIE_PRX_TBTTX_N3 PCIE_PRX_TBTTX_P3 PCIE_PTX_TBTRX_N3 PCIE_PTX_TBTRX_P3 PCIE_PRX_TBTTX_N4 PCIE_PRX_TBTTX_P4 PCIE_PTX_TBTRX_N4 PCIE_PTX_TBTRX_P4 PCIE_PRX_LANTX_N5 PCIE_PRX_LANTX_P5 PCIE_PTX_LANRX_N5 PCIE_PTX_LANRX_P5 PCIE_PRX_WLANTX_N6 PCIE_PRX_WLANTX_P6 PCIE_PTX_WLANRX_N6 PCIE_PTX_WLANRX_P6

UH2B

L27

DMI_RXN0

N27

DMI_RXP0

C27

DMI_TXN0

B27

DMI_TXP0

E24

DMI_RXN1

G24

DMI_RXP1

B28

DMI_TXN1

A28

DMI_TXP1

G27

DMI_RXN2

E26

DMI_RXP2

B29

DMI_TXN2

C29

DMI_TXP2

L29

DMI_RXN3

K29

DMI_RXP3

B30

DMI_TXN3

A30

DMI_TXP3

B18

PCIE_RCOMPN

C17

PCIE_RCOMPP

H15

PCIE1_RXN/USB3_7_RXN

G15

PCIE1_RXP/USB3_7_RXP

A16

PCIE1_TXN/USB3_7_TXN

B16

PCIE1_TXP/USB3_7_TXP

B19

PCIE2_TXN/USB3_8_TXN

C19

PCIE2_TXP/USB3_8_TXP

E17

PCIE2_RXN/USB3_8_RXN

G17

PCIE2_RXP/USB3_8_RXP

L17

PCIE3_RXN/USB3_9_RXN

K17

PCIE3_RXP/USB3_9_RXP

B20

PCIE3_TXN/USB3_9_TXN

C20

PCIE3_TXP/USB3_9_TXP

E20

PCIE4_RXN/USB3_10_RXN

G19

PCIE4_RXP/USB3_10_RXP

B21

PCIE4_TXN/USB3_10_TXN

A21

PCIE4_TXP/USB3_10_TXP

K19

PCIE5_RXN

L19

PCIE5_RXP

D22

PCIE5_TXN

C22

PCIE5_TXP

G22

PCIE6_RXN

E22

PCIE6_RXP

B22

PCIE6_TXN

A23

PCIE6_TXP

L22

PCIE7_RXN

K22

PCIE7_RXP

C23

PCIE7_TXN

B23

PCIE7_TXP

K24

PCIE8_RXN

L24

PCIE8_RXP

C24

PCIE8_TXN

B24

PCIE8_TXP

SKY-H-PCH_BGA837

@

SKY-S-PCH_BGA837

DMI

USB 2.0

PCIe/USB 3

2 OF 12REV = 1.3

USB2N_1 USB2P_1 USB2N_2 USB2P_2 USB2N_3 USB2P_3 USB2N_4 USB2P_4 USB2N_5 USB2P_5 USB2N_6 USB2P_6 USB2N_7 USB2P_7 USB2N_8 USB2P_8 USB2N_9

USB2P_9 USB2N_10 USB2P_10 USB2N_11 USB2P_11 USB2N_12 USB2P_12 USB2N_13 USB2P_13 USB2N_14 USB2P_14

GPP_E9/USB2_OC0# GPP_E10/USB2_OC1# GPP_E11/USB2_OC2# GPP_E12/USB2_OC3#

GPP_F15/USB2_OCB_4 GPP_F16/USB2_OCB_5 GPP_F17/USB2_OCB_6 GPP_F18/USB2_OCB_7

USB2_COMP

USB2_VBUSSENSE

RSVD_AB13

USB2_ID

GPD7/RSVD

USB20_N1

AF5

USB20_P1

AG7

USB20_N2

AD5

USB20_P2

AD7

USB20_N3

AG8

USB20_P3

AG10

USB20_N4

AE1

USB20_P4

AE2 AC2 AC3

DVT1.0

AF2

Remove net USB20_N6/P6

AF3

USB20_N7

AB3

USB20_P7

AB2

USB20_N8

AL8

USB20_P8

AL7

USB20_N9

AA1

USB20_P9

AA2 AJ8 AJ7 W2 W3

USB20_N12

AD3

USB20_P12

AD2 V2 V1 AJ11 AJ13

USB_OC0#

AD43

USB_OC1#

AD42

USB_OC2#

AD39

USB_OC3#

AC44

USB_OC4#

Y43

USB_OC5#

Y41

USB_OC6#

W44

USB_OC7#

W43

USB2_COMP

AG3

USB2_VBUSSENSE

AD10 AB13

USB2_ID

AG2

BD14

USB20_N1 <31> USB20_P1 <3 1> USB20_N2 <32> USB20_P2 <3 2> USB20_N3 <32> USB20_P3 <3 2> USB20_N4 <28> USB20_P4 <2 8>

USB20_N7 <34> USB20_P7 <3 4> USB20_N8 <37> USB20_P8 <3 7> USB20_N9 <38> USB20_P9 <3 8>

USB20_N12 <38> USB20_P12 < 38>

USB_OC0# <31> USB_OC1# <32>

1 2

RH109 113_0402_1 %

1 2

RH112 1K_0402_5%

1 2

RH113 1K_0402_ 5%

Left USB Type-A

Right USB Type-A

Mini Card(WLAN)

Card Reader

Finger Print

Touch Screen

Camera

USB_OC3# USB_OC2# USB_OC1# USB_OC0#

USB_OC5# USB_OC4# USB_OC6# USB_OC7#

RP16

4 5 3 6 2 7 1 8

10K_0804_8P4R_5%

RP8

4 5 3 6 2 7 1 8

10K_0804_8P4R_5%

+3VALW

UH2F

C11

USB3_1_TXN

B11

USB3_1_TXP

B7

USB3_1_RXN

A7

USB3_1_RXP

B12

USB3_2_TXN/SSIC_1_TXN

A12

USB3_2_TXP/SSIC_1_TXP

C8

USB3_2_RXN/SSIC_1_RXN

B8

USB3_2_RXP/SSIC_1_RXP

B15

USB3_6_TXN

C15

USB3_6_TXP

K15

USB3_6_RXN

K13

USB3_6_RXP

B14

USB3_5_TXN

C14

USB3_5_TXP

G13

USB3_5_RXN

H13

USB3_5_RXP

D13

USB3_3_TXP/SSIC_2_TXP

C13

USB3_3_TXN/SSIC_2_TXN

A9

USB3_3_RXP/SSIC_2_RXP

B10

USB3_3_RXN/SSIC_2_RXN

B13

USB3_4_TXP

A14

USB3_4_TXN

G11

USB3_4_RXP

E11

USB3_4_RXN

SKY-H-PCH_BGA837

@

4

USB3TN1 USB3TP1 USB3RN1 USB3RP1

USB3TN2 USB3TP2 USB3RN2 USB3RP2

USB3TP3 USB3TN3 USB3RP3 USB3RN3

B B

Left USB Type-A

Right USB Type-A

A A

5

USB3TN1<31>

USB3TP1<31> USB3RN1<31> USB3RP1<31>

USB3TN2<32>

USB3TP2<32> USB3RN2<32> USB3RP2<32>

USB3TP3<32>

USB3TN3<32> USB3RP3<32> USB3RN3<32>

SKY-S-PCH_BGA837

LPC/eSPI

USB

SATA

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

GPP_A1/LAD0/ESPI_IO0 GPP_A2/LAD1/ESPI_IO1 GPP_A3/LAD2/ESPI_IO2 GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS#

GPP_A6/SERIRQ

GPP_A7/PIRQA#/ESPI_ALERT0#

GPP_A0/RCIN#/ESPI_ALERT1#

GPP_A14/SUS_STAT#/ESPI_RESET#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

GPP_A10/CLKOUT_LPC1

GPP_G19/SMI# GPP_G18/NMI#

GPP_E6/DEVSLP2 GPP_E5/DEVSLP1 GPP_E4/DEVSLP0 GPP_F9/DEVSLP7 GPP_F8/DEVSLP6 GPP_F7/DEVSLP5 GPP_F6/DEVSLP4 GPP_F5/DEVSLP3

6 OF 12REV = 1.3

2011/08/25 2012/07/25

3

AT22 AV22 AT19 BD16

BE16 BA17 AW17 AT17 BC18

BC17 AV19

M45 N43

AE45 AG43 AG42 AB39 AB36 AB43 AB42 AB41

PCH_ESPI_IO0 PCH_ESPI_IO1 PCH_ESPI_IO2 PCH_ESPI_IO3

ESPI_CS# ESPI_ALERT# PIRQA#

ESPI_RESET#

PCH_ESPI_CLK

HDD_DEVSLP mSATA_DEVSLP

RH574 15_0402_5% RH575 15_0402_5% RH576 15_0402_5% RH577 15_0402_5%

RH168

Compal Secret Data

Deciphered Date

1 2 1 2 1 2 1 2

ESPI_CS# <36> ESPI_ALERT# <36 >

ESPI_RESET# < 36>

1 2

22_0402_5%EMI@

HDD_DEVSLP <29> mSATA_DEVSLP < 29>

ESPI_CLK

2

ESPI_IO0 <36> ESPI_IO1 <36> ESPI_IO2 <36> ESPI_IO3 <36>

PIRQA#

ESPI_ALERT#

ESPI_CLK <36>

1 2

RH546 10K_0402_5%

1 2

RH578 8.2K_0402_5%

Reserve for EMI

ESPI_CLK

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PCH (4/8) PCI, USB

12

CC4

@EMI@ 12P_0402_50V8J

LA-E992P

1

+1.8V_PRIM

19 77Tuesday, July 25, 2017

1.0(A00)

5

4

3

2

1

D D

C C

B B

+3VS

1 2

RH10 10K_0402_5%

1 2

RH159 49.9K_0402_1%

1 2

RH160 49.9K_0402_1%

1 2

RH119 2.2K_0402_5%

1 2

RH120 2.2K_0402_5%

1 2

RH545 100K_0402_5%

+3VALW

1 2

RH91 10K_0402_5%

1 2

RZ96 100K_0402_5%

1 2

RH567 100K_0402_5%

Reserve for N17E HDMI HPD.

+3VS

12

@

RH547

10K_0402_5%

12

@

RH548

10K_0402_5%

@

RH549 10K_0402_5%

@

RH550 10K_0402_5%

SIO_EXT_SCI# UART_2_CTXD_DRXD UART_2_CRXD_DTXD I2C1_SCK_TP I2C1_SDA_TP GPU_GC6_FB_EN_H

SIO_EXT_WAKE# IR_CAM_DET#

HDMI_HPD_PCH

PHASE_ID1 PHASE_ID2

GPU_GC6_FB_EN_H<46>

GPU_EVENT#<46>

BT_RADIO_DIS#<2 8>

HDMI_HPD_PCH<44>

SIO_EXT_WAKE#<36>

UART_2_CTXD_DRXD<28>

UART_2_CRXD_DTXD<28>

I2C1_SCK_TP<26> I2C1_SDA_TP<26>

RH548

EVT@

10K_0402_5%

SD028100280

RH547

DVT1@

10K_0402_5%

SD028100280

RH548

DVT2@

FFS_INT1<29>

RH550

EVT@

10K_0402_5%

SD028100280

RH550

DVT1@

10K_0402_5%

SD028100280

RH549

DVT2@

BBS_BIT0

SIO_EXT_SCI# FFS_INT1

NRB_BIT

GPU_GC6_FB_EN_H

HDMI_HPD_PCH PHASE_ID2 PHASE_ID1

IR_CAM_DET# SIO_EXT_WAKE#

I2C1_SCK_TP I2C1_SDA_TP

UH2K

AT29

GPP_B22/GSPI1_MOSI

AR29

GPP_B21/GSPI1_MISO

AV29

GPP_B20/GSPI1_CLK

BC27

GPP_B19/GSPI1_CS#

BD28

GPP_B18/GSPI0_MOSI

BD27

GPP_B17/GSPI0_MISO

AW27

GPP_B16/GSPI0_CLK

AR24

GPP_B15/GSPI0_CS#

AV44

GPP_C9/UART0_TXD

BA41

GPP_C8/UART0_RXD

AU44

GPP_C11/UART0_CTS#

AV43

GPP_C10/UART0_RTS#

AU41

GPP_C15/UART1_CTS#/ISH_UART1_CTS#

AT44

GPP_C14/UART1_RTS#/ISH_UART1_RTS#

AT43

GPP_C13/UART1_TXD/ISH_UART1_TXD

AU43

GPP_C12/UART1_RXD/ISH_UART1_RXD

AN43

GPP_C23/UART2_CTS#

AN44

GPP_C22/UART2_RTS#

AR39

GPP_C21/UART2_TXD

AR45

GPP_C20/UART2_RXD

AR41

GPP_C19/I2C1_SCL

AR44

GPP_C18/I2C1_SDA

AR38

GPP_C17/I2C0_SCL

AT42

GPP_C16/I2C0_SDA

AM44

GPP_D4/ISH_I2C2_SDA

AJ44

GPP_D23/ISH_I2C2_SCL

SKY-H-PCH_BGA837

@

SKY-S-PCH_BGA837

11 OF 12REV = 1.3

GPP_D9 GPP_D10 GPP_D11

GPP_D16/ISH_UART0_CTS# GPP_D15/ISH_UART0_RTS#

GPP_D14/ISH_UART0_TXD GPP_D13/ISH_UART0_RXD

GPP_D12

GPP_H20/ISH_I2C0_SCL GPP_H19/ISH_I2C0_SDA

GPP_H22/ISH_I2C1_SCL GPP_H21/ISH_I2C1_SDA

GPP_A23/ISH_GP5 GPP_A22/ISH_GP4 GPP_A21/ISH_GP3 GPP_A20/ISH_GP2 GPP_A19/ISH_GP1 GPP_A18/ISH_GP0 GPP_A17/ISH_GP7

AL44 AL36 AL35 AJ39

AJ43 AL43 AK44 AK45

BC38 BB38

BD38 BE39

BC22 BD18 BE21 BD22 BD21 BB22 BC19

KB_DET#

DGPU_HOLD_RST# < 46> WLAN_WIGIG60GHZ_DIS# <28> DGPU_PWR_EN <55>

KB_DET# <25>

DGPU_PWR_EN

KB_DET#

1 2

RH129 10K_0402_5%

1 2

RH127 10K_0402_5%@

1 2

RH128 10K_0402_5%

+3VS

+1.8V_PRIM

+3VALW +3VALW

1 2

RH130 2.2K_0402_5%@

BBS_BIT0

Boot BIOS Strap Bit (internal PD) HIGH

LOW(DEFAULT)

Compal Secret Data

Deciphered Date

2

LPC SPI

1 2

RH92 2.2K_0402_5%@

NRB_BIT

NO REBOOT mode (internal PD)

HIGH LOW(DEFAULT)

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PCH (5/8) GPIO, CPU, MISC

LA-E992P

ENABLE DISABLE

1.0(A00)

20 77Tuesday, July 25, 2017

1

20 77Tuesday, July 25, 2017

1.0(A00)

PILOT@

10K_0402_5%

SD028100280

RH549

PILOT@

10K_0402_5%

SD028100280

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/08/25 2012/07/25

10K_0402_5%

PHASE ID

A A

EVT DVT1 DVT2 Pilot

PHASE ID2 PHASE ID1 (GPP_C13) (GPP_C12)

0 0 1 1

5

0 1 0 1

SD028100280

RH547

10K_0402_5%

SD028100280

5

4

3

2

1

@

PJP1302

1 2

PAD-OPEN 43x39

1 2

D D

C C

B B

RZ70 0_0805_5%@

DVT2.0 Change RZ70 to 0ohm 0805 short-pad footprint.

1 2

@

RH137 0_0603_5%

1 2

@

RH196 0_0402_5%

+1VALW

1 2

@

RH124 0_0603_5%

+1VALW

1 2

@

RH123 0_0603_5%

+1VALW

1 2

LH2 BLM15PX221SN1D_2P

1 2

LH1 BLM15PX221SN1D_2P

1 2

@

RH122 0_0603_5%

DVT2.0 Change RH137, RH124, RH123, RH122 to 0ohm 0603 short-pad footprint.

+1V_PCH_CLK5

Close to K2,K3 Close to A43,B43 Close to U21,U23

22U_0603_6.3V6M

1

CH177

2

+1V_MPHY_MPHYPLL +1V_PCH_USBPLL

1U_0402_6.3V6K

22U_0603_6.3V6M

CH179

1

CH178

@

2

+1V_PCH+1VALW

+1V_MPHY

+3V_PCH_DSW+3VALW

+1V_VCCDSW+1V_PCH_PRIM

+1V_MPHY_MPHYPLL

+1V_PCH_USBPLL

+1V_PCH_AZPLL

+3V_PCH_AZIO+3VALW

+1V_PCH_CLK5+1VALW

22U_0603_6.3V6M

1

CH181

@

2

Close to AN19

1

2

SKY-S-PCH_BGA837

CORE

MPHY

USB

8 OF 12 REV = 1.3

VCCGPIO

+1V_VCCDSW

Close to BA29

1U_0402_6.3V6K

1

2

VCCPRIM_1P0_AL22

VCCDSW_3P3_BA24

VCCPGPPBH_BC42 VCCPGPPBH_BD40

VCCPGPPEF_AJ41

VCCPGPPEF_AL41

VCCPRIM_3P3_AN5

VCCPRIM_1P0_AD15

VCCRTCPRIM_3P3

VCCPRIM_1P0_AJ20 VCCPRIM_1P0_AJ21 VCCPRIM_1P0_AJ23 VCCPRIM_1P0_AJ25

VCCPGPPCD_BC44 VCCPGPPCD_BA45 VCCPGPPCD_BC45 VCCPGPPCD_BB45

VCCPRIM_3P3_BD3 VCCPRIM_3P3_BE3 VCCPRIM_3P3_BE4

CH176

VCCPGPPA

VCCPGPPG

VCCATS

VCCRTC DCPRTC

VCCSPI_BE41 VCCSPI_BE43 VCCSPI_BE42

AL22

BA24

BA31

BC42 BD40 AJ41 AL41 AD41 AN5

AD15 AD13 BA20 BA22 BA26

AJ20 AJ21 AJ23 AJ25

BE41 BE43 BE42

BC44 BA45 BC45 BB45

BD3 BE3 BE4

+3V_PCH_AZIO

0.1U_0402_10V6K

CH200

1

2

+1V_PCH_PRIM

+3V_PCH_SPI

Close to BA15

+DCPRTC

0.0908A

0.92089A

0.0061A

0.0066A

0.0002A

0.0395A

0.0811A

0.403A

+1V_PCH_PRIM

DVT2.0 Change RH493 to 0ohm 0603 short-pad footprint.

+1V_PCH

+3V_PCH_DSW

+1.8V_PRIM

eSPI need use +1.8V_PRIM

+3VALW

+1V_PCH +3VS +3VALW

+RTCVCC +DCPRTC

+3VALW

Close to BA26

0.1U_0402_10V6K

CH70

1

2

@

12

Close to AD13

1U_0402_6.3V6K

1

2

RH4930_060 3_5%

CH188

2.75835A

+3VALW

0.0121A

@

PJP1303

+1V_VCCDSW

+1V_PCH

+1V_PCH_CLK5

+1V_MPHY

+1V_APLLEBB

+1V_PCH

+1V_PCH_AZPLL

+3V_HDA

+3V_PCH_DSW

+1V_PCH_PRIM

0.0454A

0.0046A

0.0248A

0.075A

1 2

PAD-OPEN 43x39

0.0348A

3.53A

+1V_MPHY_MPHYPLL

0.095A

0.533A

+1V_PCH_USBPLL

2.75835A

+1VALW

+1V_MPHY +3VS

Close to AJ5,AL5

1U_0402_6.3V6K

22U_0603_6.3V6M

CH180

1

CH182

2

10U_0402_6.3V6M

CH185

1

2

1U_0402_6.3V6K

CH184

1

2

CH183

1

2

22U_0603_6.3V6M

1

CH201

@

2

CH202

@

2

UH2H

AA23

VCCPRIM_1P0_AA23

AA26

VCCPRIM_1P0_AA26

AA28

VCCPRIM_1P0_AA28

AC23

VCCPRIM_1P0_AC23

AC26

VCCPRIM_1P0_AC26

AC28

VCCPRIM_1P0_AC28

AE23

VCCPRIM_1P0_AE23

AE26

VCCPRIM_1P0_AE26

Y23

VCCPRIM_1P0_Y23

Y25

VCCPRIM_1P0_Y25

BA29

DCPDSW_1P0

N17

VCCCLK1

R19

VCCCLK3

U20

VCCCLK4

V17

VCCCLK2

R17

VCCCLK6

K2

VCCCLK5_K2

K3

VCCCLK5_K3

U21

VCCMPHY_1P0_U21

U23

VCCMPHY_1P0_U23

U25

VCCMPHY_1P0_U25

U26

VCCMPHY_1P0_U26

V26

VCCMPHY_1P0_V26

A43

VCCMPHYPLL_1P0_A43

B43

VCCMPHYPLL_1P0_B43

C44

VCCPCIE3PLL_1P0_C44

C45

VCCPCIE3PLL_1P0_C45

V28

VCCAPLLEBB_1P0

AC17

VCCPRIM_1P0_AC17

AJ5

VCCUSB2PLL_1P0_AJ5

AL5

VCCUSB2PLL_1P0_AL5

AN19

VCCHDAPLL_1P0

BA15

VCCHDA

W15

VCCDSW_3P3_W15

SKY-H-PCH_BGA837

@

+1V_PCH_AZPLL

0.1U_0402_10V6K

CH203

+RTCVCC

Close to BA22 Close to BA20

0.1U_0402_10V6K

1U_0402_6.3V6K

CH173

CH80

1

2

+3VALW

+3V_PCH_AZIO +3V_HDA

1 2

@

0.1U_0402_10V6K

1U_0402_6.3V6K

CH186

CH187

1

2

DVT2.0 Change RH543 to 0ohm 0402 short-pad footprint.

2

RH543 0_0402_5%

RF@

+1V_MPHY

RH544 0_0402_5%

CH213

0.5P_0402_50V8C

1

DVT2.0 Change RH544 to 0ohm 0402 short-pad footprint.

2

1 2

@

+1V_APLLEBB

CH214

1

RF@

2

+3V_PCH_DSW

Close to W15

0.5P_0402_50V8C

0.1U_0402_10V7K

1

CH190

@

2

1U_0402_6.3V6K

CH82

1

@

2

+3VALW+3VALW +3VALW+3VALW

Close to AN5Close to AD41 Close to AJ41,AL41Close to BC42,BD40

0.1U_0402_10V7K

1

CH189

@

2

0.1U_0402_10V7K

1

CH192

@

2

0.1U_0402_10V7K

1

CH191

@

2

Close to BA15 Close to V28

A A

Security Classification

2011/08/25 2012/07/25

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/08/25 2012/07/25

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet

Compal Electronics, Inc.

PCH (6/8) PWR

LA-E992P

1.0(A00)

of

21 77Tuesday, July 25, 2017

1

5

4

3

2

1

C42 D10 D12 D15 D16 D17 D19 D21 D24 D25 D27 D29 D30 D31 D33 D35 D36 E13 E15 E31 E33

G42

H17 H19 H22 H24 H27 H29

H35

U10 U11 U14 U17 U18 U28 U29 U31 U32 U33 U38

V18 V20 V21 V23 V25 V29

V45 W14 W31 W32 W33 W38

Y17

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

F44

VSS

F8

VSS VSS

G9

VSS VSS VSS VSS VSS VSS VSS

H3

VSS VSS

J10

VSS

J11

VSS

J3

VSS

J39

VSS

J5

VSS

T42

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

U4

VSS

U8

VSS VSS VSS VSS VSS VSS VSS

V3

VSS VSS VSS VSS VSS VSS VSS

W4

VSS

W8

VSS VSS

@

SKY-S-PCH_BGA837

UH2L

SKY-H-PCH_BGA837

12 OF 12 REV = 1.3

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AB11 AB7 AB14 AB31 AB32 AB38 AB4 AB5 AC1 AC20 AC21 AC25 AC29 AC45 AB8 AD11 AD14 AB15 AD32 AD33 AD36 AD4 AD8 AE18 AE20 AE21 AE25 AE28 AL10 AL11 AL13 AL17 AL19 AL24 AL29 AL32 AL33 AL38 AM15 AM17 AM19 AM22 AM24 AM27 AM29 AM45 AN11 AN22 AN27 AN31 AN39 AN7 AN8 AP11 AP4 AR33 AR34 AR42 AR9 AT10 AT15 AT36 AT9 AU1 AU35 AU36 AU39 AU45 C4

BD2 BD45 BD44

BE44

D45

BB1

BC1

A42 B45 B44

A44

A4 A3 B2 A2 B1

C1 D1

UH2J

VSS_BD2 VSS_BD45 VSS_BD44 VSS_BE44 VSS_D45 VSS_A42 VSS_B45 VSS_B44 VSS_A4 VSS_A3 VSS_B2 VSS_A2 VSS_B1 VSS_BB1 VSS_BC1 VSS_A44

RSVD_C1 RSVD_D1

SKY-H-PCH_BGA837

@

SKY-S-PCH_BGA837

PCH_TRIGOUT

RSVD_AR22

RSVD_W13

RSVD_U13

RSVD_P31 RSVD_N31

RSVD_P27 RSVD_R27 RSVD_N29 RSVD_P29

RSVD_AN29

RSVD_R24 RSVD_P24

PREQ#

PRDY#

CPU_TRST#

PCH_TRIGIN

10 OF 12REV = 1.3

AR22 W13 U13

P31 N31

P27 R27 N29 P29 AN29 R24 P24

AT3 AT4 AY5 AL2 AK1

XDP_PREQ# <6,9> XDP_PRDY# <6,9> CPU_XDP_TRST# <6 ,9> PCH_TRIGGER <9> CPU_TRIGGER <9>

UH2I

SKY-S-PCH_BGA837

AC18

VSS

AN4

VSS

AN10

VSS

D D

C C

B B

BE14 BE18 BE23 BE28 BE32 BE37 BE40

BE9 C10

C28 C37

K10 K27 K33 K36

K42 K43

M35 M42

N10 N15 N19 N22 N24 N35 N36

N41

P17 P19 P22 P45 R10 R14 R22 R29 R33 R38

Y18 Y20 Y21 Y26 Y28 Y29 A18 A25 A32

A37 AA17 AA18 AA20 AA21 AA25 AA29

AA4 AA42 AB10

C2

J7

K4

L12 L13 L15

L4

L41

L8

N4

N5

R5 T1 T2 T4

@

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

SKY-H-PCH_BGA837

AR5

VSS

AR7

VSS

U15

VSS

AL4

VSS

AE29

VSS

AE4

VSS

AE42

VSS

AF18

VSS

AF20

VSS

AF21

VSS

AF23

VSS

AF25

VSS

AF26

VSS

AF28

VSS

AF29

VSS

AG11

VSS

AG13

VSS

AG31

VSS

AG32

VSS

AG33

VSS

AG38

VSS

AG4

VSS

AH1

VSS

AH17

VSS

AH18

VSS

AH20

VSS

AH21

VSS

AH23

VSS

AH25

VSS

AH26

VSS

AH28

VSS

AH29

VSS

AH45

VSS

AJ10

VSS

AJ14

VSS

AJ15

VSS

AJ17

VSS

AJ18

VSS

AJ26

VSS

AJ28

VSS

AJ29

VSS

AJ31

VSS

AJ32

VSS

AJ36

VSS

AK4

VSS

AK42

VSS

AU7

VSS

AV17

VSS

AV24

VSS

AV27

VSS

AV31

VSS

AV33

VSS

AV6

VSS

AW13

VSS

AW19

VSS

AW29

VSS

AW37

VSS

AW9

VSS

AY38

VSS

AY45

VSS

B25

VSS

B3

VSS

B37

VSS

B40

VSS

B6

VSS

BA1

VSS

BB11

VSS

BB16

VSS

BB21

VSS

BB25

VSS

BB30

VSS

BB34

VSS

BC2

VSS

BD43

VSS

9 OF 12REV = 1.3

A A

Security Classification

2011/08/25 2012/07/25

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/08/25 2012/07/25

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PCH (8/8) VSS

LA-E992P

22 77Tuesday, July 25, 2017

1

1.0(A00)

5

4

3

2

1

Main Func = Audio

Pilot Change RA1 to 0ohm 0402 short-pad footprint.

+1.8V_PRIM

LN2306LT1G_SOT23-3

DVT2.0

D D

Reserve RA58

DVT2.0 Pop CA7, UA1, RA2, CA10, CA4,RA57

+1.8V_DVDD

Pilot Change RA57 to 0ohm 0603 short-pad footprint.

+3VS +3V_DVDD

C C

+3VS

RA5

1 2

@

0_0402_5%

25mA

QA1

1 3

D

2

0_0603_5%

G

RA57

RA58

S

@

12

4.7U_0603_6.3V6K

1

2

12

@

0_0603_5%

5

+1.8VS

1U_0402_6.3V6K

4

CA7

1

2

CA8

G9090-180T11U_SOT23-5

Pilot

Change RA5 to 0ohm 0402

short-pad footprint.

1

CA9

0.1U_0402_10V6K

Close pin9

2

UA1

VOUT

NC

SA00004Z400

Speaker trace width >40mil @ 2W4ohm speaker power

B B

DMIC_CLK<38>

47P_0402_50V8J

Reserve for RF

Close pin3

@RF@

CA30

1

2

DVT 2.0 EMI request change LA1 to 470 ohm bead to depress EMI rediation.

RA1 0_0402_5%@

1

CA3

0.1U_0402_10V6K

Close pin36

2

VIN

GND

EN

Layout Note:

EC_MUTE#<36>

1 2

BLM15PX471SN1D_2P

moat

1 2

1

2

3

AUD_AGND

+3V_DVDD

LA1

EMI@

CA1

4.7U_0603_6.3V6K

+1.8V_AVDD+1.8V_DVDD

1

CA2

0.1U_0402_10V6K

2

AUD_AGND

+3VS

1 2

AUD_SPK_L+<24>

AUD_SPK_L-<24>

AUD_SPK_R-<24>

AUD_SPK_R+<24>

@

DMIC_DATA_R

@

HDA_SDOUT_AUDIO<18>

HDA_BITCLK_AUDIO<18>

HDA_SDIN0_AUDIO<18>

HDA_SYNC_AUDIO<18>

1U_0402_6.3V6K

CA4

1

2

1

2

12

RA2

10K_0402_5%

CA10

0.22U_0603_25V7K

1 2

CA22 10U_0603_6.3V6M

CA63 10U_0603_6.3V6M

1 2

RA23 100K_0402_5%

DMIC_DAT<38>

LINE1_VREFO_R<24>

LINE1_VREFO_L<24>

AUD_HP1_JACK_L<24>

AUD_HP1_JACK_R<24>

CBN

2

CA20 1U_0603_10V6K

1

CBP

LDO2_CAP

+1.8V_AVDD

+5V_PVDD

CA62 10P_0402_25V8J

DVT 1.0 Change RA27 to 33 ohm.

1 2

RA27 33_0402_5%

RA32

+1.8V_DVDD

HDA1

37

CBP

38

AVSS2

39

LDO2-CAP

40

AVDD2

41

PVDD1

42

SPK-OUT-L+

43

SPK-OUT-L-

44

SPK-OUT-R-

45

SPK-OUT-R+

46

PVDD2

47

PDB

48

SPDIF-OUT/GPIO2

49

GND

+3V_DVDD

1

CA25

2

1 2

33_0402_5%

1

@RF@

CA66 10P_0402_25V8J

2

CA15 1U_0603_10V6K

1 2

CPVEE

34

35

36

CBN

CPVEE

CPVDD

DVDD1GPIO0/DMIC-DATA2GPIO1/DMIC-CLK3EAPD/DC DET4SDATA-OUT5BCLK6LDO3-CAP7SDATA-IN8DVDD-IO9SYNC

4.7U_0603_6.3V6K

CA26

1

2

0.1U_0402_10V6K

DMIC_DATA_R

DMIC_CLK_R

HDA_SDOUT_AUDIO

HDA_BITCLK_AUDIO

HDA_CODEC_SDIN0

HDA_SYNC_AUDIO

31

32

33

LINE1-VREFO-L

HPOUT-L/PORT-I-L

HPOUT-R/PORT-I-R

ALC3246-CG-GP

SA00008GJ00

4.7U_0603_6.3V6K

2.2U_0402_6.3V6M

CA16

CA19

1

2

LDO1_CAP

26

27

28

29

30

VREF

AVDD1

LDO1-CAP

MIC2-VREFO

LINE1-VREFO-R

MIC2_R/SLEEVE

MIC2_L/RING2

SPDIFO/FRONT_JD/JD3/GPIO3

MIC2/LINE2_JD/JD2

HP/LINE1_JD/JD1

I2C_SDA

10

11

CA280.1U_0402_10V6K

CA274.7U_0603_6.3V6K

LDO3_CAP

1

2

12

RA11 100K_0402_5%

25

AVSS1

LINE2_L

LINE2_R

LINE1_L

LINE1_R

5/3D3VSTB

MIC-CAP

MONO-OUT

I2C_SCL

12

+3V_DVDD

AUD_AGND

+5V_AVDD

AUD_AGND

24

23

22

21

20

19

18

17

16

15

14

13

MIC2_VREFO <24>

LINE1_L <24>

LINE1_R <24>

SLEEVE <24>

RING2 <24>

AUD_SENSE_A

SPKR<18>

BEEP<36>

1 2

CA23 10U_0402_6.3V6M

1 2

RA19 0_0402_5%@

DVT2.0 Change RA19 to 0ohm 0402 short-pad footprint.

1 2

RA22

200K_0402_5%

Place close to Pin 13

3

2

Reserve for RF

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2015/07/15 2016/07/31

Compal Secret Data

Deciphered Date

Pilot Change RA7, RA10 to 0ohm 0805 short-pad footprint.

+5VS +5V_PVDD

1.5A

1 2

@

RA7 0_0805_5%

1 2

@

RA10 0_0805_5%

moat

RA8

Pilot Change RA8 to 0ohm 0603 short-pad footprint.

0_0603_5%

@

12

4.7U_0603_6.3V6K

CA18

moat

1 2

RA17 0_0402_5%@

1 2

RA18 0_0402_5%

AUD_AGND

Width>40mil, to improve Headpohone Crosstalk noise

Layout Note:

AUD_SENSE

Change it to sharp will be better. Add 2 vias (>0.5A) when trace layer change.

AUD_PC_BEEP

AUD_SENSE <24>

moat

D1

AUD_PC_BEEP_C

1

BAT54C-7-F_SOT23-3

1 2

RA30 1K_0402_5%

+3VS To +1.8V_DVDD

Pilot Change RA9, RA12, RA13, RA14, RA15 to 0ohm 0402 short-pad footprint.

Pilot Change RA16 to 0ohm 0805 short-pad footprint.

2

5V_PVDD trace width > 40mil.

CA11

1

2

10U_0603_6.3V6M~D

+5V_AVDD

1

2

AUD_AGND

+3VALW

1

2

1

2

CA12

0.1U_0402_10V6K

CA17

0.1U_0402_10V6K

Place close to Pin 26

+RTCVCC

12

CA14

CA13

1

2

0.1U_0402_10V6K

10U_0603_6.3V6M~D

Close pin46Close pin41

Pop RA18 to prevent "zizi" noise on G3 or DC S5/S4.

AUD_SENSE_A

1

CA24

0.1U_0402_10V6K

CA29

1 2

0.1U_0402_10V6K

RA33 10K_0402_5%

2

AUD_AGND

AUD_PC_BEEP

RA24

moat

+3V_DVDD

12

100K_0402_5%

moat

1 2

RA9 0_0402_5%@

1 2

RA12 0_0402_5%@

1 2

RA13 0_0402_5%@

1 2

RA14 0_0402_5%@

1 2

RA15 0_0402_5%@

AUD_AGND

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

1 2

RA16 0_0805_5%@

CODEC ALC3246

LA-E992P

1

23 77Tuesday, July 25, 2017

1.0(A00)

5

Main Func = Audio

4

3

2

1

Layout Note:

Speaker trace width >40mil @ 2W4ohm speaker power

2

1

3

LA19 BLM15PX330SN1D 0402ESD@ LA20 BLM15AX700SN1D_2PEMI@

LA21 BLM15AX700SN1D_2PEMI@ LA22 BLM15PX330SN1D 0402ESD@

AUD_SPK_R+_C AUD_SPK_R-_C AUD_SPK_L+_C AUD_SPK_L-_C

DA2

AZ5125-02S.R7G_SOT23-3

1 2 1 2

ESD@

2

3

DA3

1

AZ5125-02S.R7G_SOT23-3

1 2

D D

C C

AUD_SPK_R+<23> AUD_SPK_R-<23> AUD_SPK_L+<23> AUD_SPK_L-<23>

MIC2_VREFO<23>

RING2<23> AUD_HP1_JACK_L<23> LINE1_L<23> LINE1_VREFO_L<23>

AUD_HP1_JACK_R<23> LINE1_R<23> LINE1_VREFO_R<23>

SLEEVE<23>

LA23 BLM15PX181SN1D_2PEMI@

1 2

LA24 BLM15PX181SN1D_2PEMI@

1 2

LA25 BLM15PX181SN1D_2PEMI@

1 2

LA26 BLM15PX181SN1D_2PEMI@

RA42 2.2K_0402_5% RA43 2.2K_0402_5%

LINE1-L_C

1 2

CA64 10U_0603_6.3V6M~D

LINE1-L_R

1 2

CA65 10U_0603_6.3V6M~D

EMI@

CA36

CA37

1

2

1000P_0402_50V7K

1 2 1 2

1 2

RA44 10_0402_1%

1 2

RA48 1K_0402_5%

1 2

RA46 4.7K_0402_5%

1 2

RA49 10_0402_1%

1 2

RA51 1K_0402_5%

1 2

RA53 4.7K_0402_5%

EMI@

CA38

1

2

1000P_0402_50V7K

AUD_HP1_JACK_L1

AUD_HP1_JACK_R1

EMI@

CA39

1

2

ESD@

1000P_0402_50V7K

Close to HDA1

Universal Jack

3

1

RING2_R AUD_PORTA_L_R_B

JACK_PLUG AUD_PORTA_R_R_B SLEEVE_R

ESD@

2

DA4

moat

SLEEVE_R AUD_PORTA_R_R_B

JACK_PLUG

AUD_PORTA_L_R_B RING2_R

RING2_R

AUD_PORTA_L_R_B

B B

AUD_SENSE<23>

DVT2.0 Change RA56 to 0ohm 0402 short-pad footprint.

RA56

0_0402_5%

JACK_PLUG

12

@

AUD_PORTA_R_R_B SLEEVE_R

680P_0402_50V7K

1

ESD@

CA42

2

AUD_AGND AUD_AGND AUD_AGND AUD_ AGND

Pilot Change connect CA42.2, CA43.2, CA60.2, CA61.2 from GND to AGND. Change CA60, CA61 BS from EMI@ to @EMI@ reserve for EMI.

ESD@

CA43

1

2

CA60

@EMI@

1

2

33P_0402_50V8J

CA61

@EMI@

1

33P_0402_50V8J

2

ESD@

DA6

2

3

1

TVNST52302AB0_SOT523-3

ESD@

2

3

DA5

1

L03ESDL5V0CC3-2_SOT23-3

AZ5123-02S.R7G_SOT23-3

Need to check Speaker pin define

Speaker

EMI@

CA40

AUD_AGND

JSPK1

1

2

3

4

5

GND

6

GND

ACES_50278-0040N-001

CONN@

SP02001CE00

680P_0402_50V7K

1

2

AUD_AGND

JHP1

3

#3 M/G

2

#2 R

6

#6 AGND

5

#5

1

#1 L

4

#4 G/M

7

GND

SINGA_2SJ3095-106111F

CONN@

DC23000FV00

1

2

CONN Pin

Pin1

Pin2

Pin3

Pin4

RING2_R AUD_PORTA_L_R_B

AUD_PORTA_R_R_B SLEEVE_R

680P_0402_50V7K

Pilot

EMI@

Change CA40, CA41 from 100p

CA41

0402 to 680p 0402 and pop for EMI(EMI@).

Net name

SPK_R+

SPK_R-

SPK_L+

SPK_L-

SINGA_2SJ3095-106111F

A A

10 mils10 mils

Security Classification

2015/07/15 2016/07/31

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2015/07/15 2016/07/31

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

SPKR/JACK

LA-E992P

1

1.0(A00)

24 77Tuesday, July 25, 2017

Compal LA-E992P Schematics Rev1.0

Specifications and Main Features

Frequently Asked Questions

User Manual