Compal LA-E903P Schematics

A

1 1

B

C

D

E

Compal Confidential

2 2

C5V08/C5V09/D5PR8 Schematics Document

AMD Bristol Ridge/Stoney Ridge Platform

APU 15W/35W + Radeon R17M-P1-50/70/G1-70 25W/40W/50W

3 3

LA-E903P REV:1.A

2017-04-18

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGIN EERING DRAWING IS THE PROPRI ETARY PRO PERTY OF C OMPAL ELE CTRONI CS, INC . A ND CONTAI NS CONFIDENTIAL

THIS SHEET OF ENGIN EERING DRAWING IS THE PROPRI ETARY PRO PERTY OF C OMPAL ELE CTRONI CS, INC . A ND CONTAI NS CONFIDENTIAL

THIS SHEET OF ENGIN EERING DRAWING IS THE PROPRI ETARY PRO PERTY OF C OMPAL ELE CTRONI CS, INC . A ND CONTAI NS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

2017/04/18 2019/04/18

2017/04/18 2019/04/18

2017/04/18 2019/04/18

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

COVER PAGE

COVER PAGE

COVER PAGE

C5V08/D5PR8_LA-E903PR1A

C5V08/D5PR8_LA-E903PR1A

C5V08/D5PR8_LA-E903PR1A

150Tuesday, May 02, 2017

150Tuesday, May 02, 2017

150Tuesday, May 02, 2017

E

1.A

1.A

1.A

A

Compal Confidential

Model Name : Wartortle_BS

B

C

D

E

(Channel A)

1 1

GPU
S4 Package

PEG x8

RX540 : R17M-P1-50
RX550 : R17M-P1-70
RX560 : R17M-G1-70

page 15~23

Display Port

USB2.0

eDP Conn.

page 27 page 26

Port 3

2 2

Port 1Port 0

HDMI Conn.

AMD

BRISTOL RIDGE
STONEY RIDGE
Co-Lay

Memory BUS(DDR4)

1.2V DDRIV
1866Mhz

USB2.0

S/B

2.0 Conn.

USB3.0

260pin DDRIV SO-DIMM

Port 1

page 31 page 31

S/B

2.0 Conn.

page 13

Port 2Port 0

WLAN/BT
Combo

page 29

Port 1,2

page 32

Type-C

3.0 Conn.

AMD FP4 APU

PCIE

BGA 968-balls

Port 2, 3

page 30

SSD
NGFF Conn.

Port 0

LAN+CR
RTL8411

page 28

USB2.0

Port 2

Transformer
RJ45

page 28 page 28

3 3

Fan Control

page 35

Card Reader
Conn.

Port 1

WLAN/BT
NGFF Conn.

page 29

page 10

BIOS (8M)

SPI

page 33

Discrete TPM

page 6~12

LPC

ENE
KBC9022

page 24 page 30

PS2

page 33

HD Audio(AZ)

SATA III

I2C

Port 1

G-Sensor

(Reserve)

Port 3

PTP
(BR/SR)

HDD
Conn.

page 33

Port 0

page 30

Port 1

SSD
NGFF Conn.

page 30

(Channel B) *SR only Ch B

260pin DDRIV SO-DIMM

Port 3

Camera

page 27

Port 3

page 31

M/B

3.0 Conn.

Port 5

Audio
ALC255

page 27

Int. DMIC
on Camera

Int. Speaker
Conn.

Port 7

page 34

page 34

page 14

page 31

UAJ
on Sub/B

Int.KBD

RTC CKT.

page 11

Power On/Off CKT.

DC/DC Interface CKT.

4 4

Power Circuit DC/DC

VRAM Config Table

page 33

page 25

page 38~51

page 23

A

Sub Board

LS-E901 USB2.0/B

LS-E892 Hall Sensor/B

page 31

page 33

www.schematic-x.blogspot.com

Security Classific ation

Security Classific ation

Security Classific ation

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PR OPERT Y OF C OMPAL EL ECTRO NICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PR OPERT Y OF C OMPAL EL ECTRO NICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PR OPERT Y OF C OMPAL EL ECTRO NICS, INC. AND CO NTAINS CONFIDENTIAL

AND T RADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D

AND T RADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D

AND T RADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISC LOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISC LOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISC LOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2017/04/18 2019/04/18

2017/04/18 2019/04/18

2017/04/18 2019/04/18

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

BLOCK DIAGRAMS

BLOCK DIAGRAMS

BLOCK DIAGRAMS

C5V08/D5PR8_LA-E903PR1A

C5V08/D5PR8_LA-E903PR1A

C5V08/D5PR8_LA-E903PR1A

E

of

of

250Tuesday, May 02, 2017

of

250Tuesday, May 02, 2017

250Tuesday, May 02, 2017

1.A

1.A

1.A

5

PJP101
AC-IN

PU301

20493mA

+19VB

5416mA

2843mA

449mA

514mA

2311mA

+19V_VIN

+17.4V_BATT

D D

PJP201
DC-IN

C C

PU801

PU901

PU501

PU601

PU401

+APU_CORE

+APU_CORE_NB

+APU_GFX

+1.2V

6500mA

+0.6VS

1200mA

9300mA

+0.95VALW

(+1.05VALW)

+3VLP

KB9022

B B

+5VALW

14000mA3685mA 6500mA

PU401

L11

379mA
427mA

+INVPWR_B+

Panel BackLight

1500mA

A A

To VGA
+VGA_CORE
+VDDCI/VDD_08
+1.35VSDGPU

2969mA

13305mA

4

+3VALW

1753mA

212mA

PU602

PU902

7285mA

+1.8VALW

3213mA

+0.775VALW

U2

+3VS

+5VS

8500mA

1700mA

JRTC1

304mA

To VGA

1013mA

PU502

U2606

U1302

10mA

JUSB3

+0.95VS

U4

To VGA

+1.8VS

U3

U102

RM9

RL2

R463

U13

R212

U8

RW2

RW1

U45

R110

RS10

JPA8

U25

RO3

RF1/RF7

JPA1

U73

3

+RTC_APU_R

+2.5V

55000mA

17000mA

45000mA

200mA

1500mA

1500mA +0.95VS_GFX

7000mA

3000mA

200mA

500mA

200mA

800mA

900mA

45mA

400mA

3500mA

1200mA

125mA

3500mA

1400mA

200mA

1500mA

1500mA

50mA

1mA

200mA

290mA

250mA

3000mA

2000mA

2500mA

2000mA

2000mA

1500mA

1000mA

+VCC_FAN1

+APU_CORE

+APU_CORE_NB

+APU_GFX

+3VS

+1.8VS

+0.95VS

+1.2V

+3VALW

+1.8VALW

+1.8VS

+0.95VALW

+APU_CORE_FCH

+RTC_APU_R

+2.5V

+1.2V

+0.6VS

+3VS_SSD_NGFF

+3V_LAN

+TP_VCC

+3VS_WLAN

+LCDVDD

+3VS_TPM

+3VALW_TPM

+3VS_CAM

+1.2V_HDMI

+3VALW_CC

+5VALW_CC

+USB3_VCCA

+5VS_HDD

+VCC_FAN2

+VDDA

+5VS_DISP

2

APU Power Rail

VDDCR_CPU @0.75-1.5V

VDDCR_NB @0.75-1.2V

VDDCR_GFX @0.75-1.2V

VDD_33 @0.2A

VDD_18 @1.5A

VDDP_GFX @1.5A

VDDP @7.0A

VDDIO_MEM_S3 @3A

VDD_33_S5 @0.2A

VDD_18_S5 @0.5A

VDDIO_AUDIO @0.2A

VDDP_S5 @0.8A

VDDCR_FCH_S5 @0.9A

VDDBT_RTC_G @0.045A

DDR4 SO-DIMM/MEM-DOWN

+2.5V

+1.2V

+0.6VS

SATA Redriver

SSD

LAN RTL8411

Touch Pad

WLAN

Panel Logic

TPM

Camera

HDMI Redriver

Type C

USB3.0

USB/B

HDD

FAN1/FAN2

Audio

HDMI Logic

Group C, S0 domain

Group B, S0 domain

Group B, S3 domain

Group A, S5 domain

R17M-P1-50/70

+19VB

2969mA

+19VB

427mA

+3VS

10mA

+1.8VALW

1013mA

PU1401

PU1402

PU1001

UV7

UV8

6000mA

47000mA

10mA

1013mA

+VGA_CORE

+VDDCI+19VB 8000mA379mA

2000mA

+1.35VSDGPU

+3VSDGPU

+1.8VSDGPU

4000mA

+1.35VSDGPU

1

GPU Power Rail

VDDC @47A

@1.2V

VDDCI+VDD_08 @8A

VMEMIO @2A

VDD_GPIO33 @0.01A

VDD_18 @1A

TSVDD @13mA

VRAM x4pcs

@0.8~0.9V

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROP ERTY OF COM PAL EL ECTRONI CS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROP ERTY OF COM PAL EL ECTRONI CS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROP ERTY OF COM PAL EL ECTRONI CS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECT RONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECT RONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECT RONICS, INC.

2017/04/18 2019/04/18

2017/04/18 2019/04/18

2017/04/18 2019/04/18

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Tit le

Tit le

Tit le

Size

Size

Size

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

POWER MAP

POWER MAP

POWER MAP

Document Number Rev

Document Number Rev

Document Number Rev

C5V08/D5PR8_LA-E903PR1A

C5V08/D5PR8_LA-E903PR1A

C5V08/D5PR8_LA-E903PR1A

1

350Tuesd ay, M ay 02 , 20 17

350Tuesd ay, M ay 02 , 20 17

350Tuesd ay, M ay 02 , 20 17

1.A

1.A

1.A

5

Bristol/Stoney Platform Power Sequence

4

3

2

1

AC-IN G3 --> S0

+3VLP

D D

ACIN

EC_ON

+5VALW

ON/OFFBTN#

3V_EN

+3VALW

+0.775VALW

0.95_1.8VALW_PWREN

+1.8VALW

+0.95VALW

PBTN_OUT#

EC_RSMRST#

SLP_S5#

SLP_S3#

SYSON

+1.2V

C C

+2.5V

SUSP#

+5VS

+3VS

+1.8VS

+0.6VS

KBRST#

0.95VS_PWR_EN#

+0.95VS

VR_ON

+APU_CORE

+APU_CORE_NB

+APU_GFX

VGATE

SYS_PWRGD_EC

APU_PWROK

LPC_RST#

B B

APU_PCIE_RST#

APU_RST#

VGA Sequence

PE_GPIO1

VGA_ON

+3VSDGPU

+1.8VSDGPU

VGA_ON_B

+VGA_CORE

+VDDCI

DGPU_PWROK

+1.35VSDGPU

PE_GPIO0

PLT_RST_VGA#

14.82us

227us

3.348ms, Tr = 637us

4.32us

91ms

91ms

160ms

1.033ms, Tr = 670us

1.108ms, Tr = 364us

2.385ms, Tr = 691us

841us, Tr = 382us

7ms

114ms

100ms

120us

120us

120ms

807us, Tr = 239us

1.456ms, Tr = 1.025ms

20ms

770us, Tr = 616us

823us, Tr = 599us

290us, Tr = 193us

20ms

19.97ms

317us, Tr = 146us 307us, Tr = 138us139us, Tf = 1.419ms 133us, Tf = 955us

20.2ms

1.089ms, Tr = 293us

1.103, Tr = 320us

1.112ms, Tr = 318us

1.254ms

39.81ms

14.61ms

13.38ms

1.005ms

6.709ms

228ms

1.399ms

2.769ms, Tr = 1.598ms 2.782ms, Tr = 1.598ms

6.571ms

5.880ms, Tr = 37.32us

5.943ms, Tr = 35.7us Tf = 16.42ms

5.976ms

Tr = 325us Tr = 257usTf = 8.199ms Tf = 9.667ms

206ms

1.008ns

S0 --> S3 S3 --> S0

57.1ms

Tf = 13.95ms

Tf = 21.44ms

Tf = 8.428ms

57.1ms

58.11ms

88.45ms

Tf = 4.119ms

Tf = 817us

Tf = 807us

28ms

1.418ms

2.06ms

108us

13.51ns

3.145ms

6.158ms

Tf = 754us

Tf = 3.864ms

10.6us

Tf = 5.215ms

395ns

16.7ns

6.871ns

14.88ms

733us, Tr = 575us

789us, Tr = 551us

282us, Tr = 174us

8.25us, Tr = 6.9us10.14us, Tr = 9.399us Tf = 662us Tf = 677us

19.98ms

20.22ms

21.37ms

1.098ms, Tr = 301us

1.083, Tr = 300us

1.108ms, Tr = 306us

1.249ms

39.61ms

14.6ms

13.4ms

1.004ms

6.708ms

113.9ms

1.404ms

3.568ms, Tr = 918us3.553ms, Tr = 917us

6.545ms

5.840ms, Tr = 37.84us

5.932ms, Tr = 35.6us

5.976ms

197.2ms

7.374ns

S0 --> S5

61ms

Tf = 1.135ms

Tf = 11.64ms

53.3ms

Tf = 14.83ms

Tf = 23.94ms

Tf = 8.909ms

53.27ms

53.3ms

83.5ms

Tf = 5.572ms

Tf = 698us

Tf = 803us

23.17ms

1.416ms

2.072ms

97us

36.63ns

3.001ms

6.039ms

Tf = 685us

Tf = 3.659ms

13.21us

Tf = 5.215ms

Tf = 16.42ms

390.7ns

17.79ns

8.908ns

8.532s

8.542s

Tf = 19.35ms

Tf = 9.193ms

Tf = 3.951ms

Tf = 14.24mss

9.041s

9.042s

+3VLP

ACIN

EC_ON

+5VALW

ON/OFFBTN#

3V_EN

+3VALW

+0.775VALW

0.95_1.8VALW_PWREN

+1.8VALW

+0.95VALW

PBTN_OUT#

EC_RSMRST#

SLP_S5#

SLP_S3#

SYSON

+1.2V

+2.5V

SUSP#

+5VS

+3VS

+1.8VS

+0.6VS

KBRST#

0.95VS_PWR_EN#

+0.95VS

VR_ON

+APU_CORE

+APU_CORE_NB

+APU_GFX

VGATE

SYS_PWRGD_EC

APU_PWROK

LPC_RST#

APU_PCIE_RST#

APU_RST#

VGA Sequence

PE_GPIO1

VGA_ON

+3VSDGPU

+1.8VSDGPU

VGA_ON_B

+VGA_CORE

+VDDCI

DGPU_PWROK

+1.35VSDGPU

PE_GPIO0

PLT_RST_VGA#

A A

Security Classification

Security Classificat ion

Security Classificat ion

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2017/04/18 2019/04/18

2017/04/18 2019/04/18

2017/04/18 2019/04/18

2

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Ele ctronics, Inc.

Compal Ele ctronics, Inc.

Compal Ele ctronics, Inc.

Title

Title

Title

Size

Size

Size

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

POWER SEQUENCE

POWER SEQUENCE

POWER SEQUENCE

Document Number Rev

Document Number Rev

Document Number Rev

C5V08/D5PR8_LA-E903PR1A

C5V08/D5PR8_LA-E903PR1A

C5V08/D5PR8_LA-E903PR1A

1

450Tuesday, May 02, 2017

450Tuesday, May 02, 2017

450Tuesday, May 02, 2017

1.A

1.A

1.A

A

B

C

D

E

Vol tage R ails

Power Plane

+19V_VIN

+19VB

+APU_CORE

1 1

2 2

+APU_CORE_G FX

+APU_CORE_ FCH

+0.95VALW

+0.95VS

+1.8VALW

+1.8VS

+2.5V

+1.2V

+0.6VS

+3VALW

+3VS

+5VALW

+5VS

+RTC_APU

+3VSDGPU

+1.8VSDGPU

+VDDCI

+VGA_CORE

APU SMBus/I2C Address Table

Master

I2C Port 0
(+1.8VS)

I2C Port 1
(+1.8VS)

I2C Port 2
(+3VS)

SBMus Port 0

3 3

(+3VS)

I2C Port 3
(+3VALW)

SMBus Port 1
(+3VALW)

Description

Adapt er power s upply (19 V)

AC or ba ttery pow er rail for pow er c ircuit .

Core voltage for APU

Volt age fo r O n-di e V GA o f AP U

Volt age for GF X

Fusion Controller Hub Power Supply

0.95V always on power rail

0.95V switched power rail

1.8V always on power rail

1.8V switched power rail

2.5V power rail for AP U and DDR

1.2V power rail for AP U and DDR

0.6V switched power r ail for DDR terminator

0.775V always on power rail+0.775VALW

3.3V always on power rail

3.3V switched power rail

5V always on power rail

5V switched power rail

RTC power

VGA power

VGA power

VGA power

VGA power

Device

G-Sensor

(Reserver)

JDIMM1

JDIMM2

PTP

(Synaptics)

PTP
(ELAN)

Address [7:1]

0001 1000b

18h

0101 0000b

50h

0101 0001b

51h

0010 1100b
2Ch

0001 1111b

15h

Address [7:0]

Write

0011 0000b

30h

1010 0000b
A0h

1010 0010b
A2h

0101 1000b

58h

0011 1110b
3Eh

ON

ON

ON+APU_CORE_NB

ON

ON

ON

ON

ON ON

ON

ON ON

ON

ON

ON

ON

ON

ON

ON

S5S3S0

ONONON

ON ON

OFF

OFF

OFF

OFF

OFF OFF

ONONON

OFF

ONON

OFF OFF

OFF

ON

OFF OFF

OFF

OFF

ONON

OFF OFF

OFF

OFF

ONON

OFF OFF

AC:ON

ON

DC:OFF

OFF OFF

ONONON

OFF OFF

OFFOFF

OFFOFF

OFFOFF

Read

0011 0001b

31h

1010 0001b
A1h

1010 0011b
A3h

0101 1001b

59h

0011 1111b
3Fh

EC SMBus Address Table

SMBus Port 1
(+3VALW)

4 4

SMBus Port 2
(+3VS)

Smart Battery

Charger IC
(BQ24735)

APU Temp.

(TSI)

GPU Temp.

A

0000 1011b
0Bh

0000 1001b

09h

0100 1100b
4Ch

0100 0001b

41h

0001 0110b

16h

0001 0010b

12h

1001 1000b

98h

1000 0010b

82h

0001 0111b

17h

0001 0011b

13h

1001 1001b

99h

1000 0011b

83h

B

BOARD ID Table

Board ID

0
1
2
3

4
5
6
7
8

ZZZ

PCB

DA8001C0010

PCB 218 LA-E903P REV1 MB 2

@

PCB Revision

C5V08 EVT
C5V08 DVT
C5V08 PVT
C5V08 MP

D5PR8 DVT
D5PR8 PVT
D5PR8 MP
D5PR8_PVT_32P
D5PR8_MP_32P

ZZZ

PCB

DAZ21800201

PCB C5V08 LA-E903P LS-E901P/E892P

BOM Structure Table

BTO ItemBOM Structure

@
@EMC@
EMC@
45@
CONN@
JP@
RS@
TP@
TPM@
PCIE@
SATA@
T1@
T3@
GS@
LDO@
SWR@
2D@
PAR@
TI@
EVT@
CHG@
NCHG@
UMA@

EA@
VX@
DIS@
V2G_S@
V2G_H@
V2G_M@

RX540@
RX550@
RX560@

Unpop

EMI/ESD Unpop

EMI/ESD pop

HDMI Royalty

ME Connector

Jump

R-Short

Test Point

TPM Pop

PCIE SSD Device

SATA SSD Device

Bristol Pop

Stoney Pop

G-Sensor Circuits

RTL8411 LDO mode

RTL8411 Switching mode

For 2 SO-DIMM use

SATA Redriver PARADE solution

SATA Redriver TI solution

Only use on EVT

USB Charger

Non-USB Charger

UMA Config

CPU PN Refer p.6

EA Series

VX Series

VGA Circuits Pop

VRAM use SAMSUNG

VRAM use HYNIX

VRAM use MICRON

GPU PN Refer p.23

R17M-P1-50 GPU

R17M-P1-70 GPU

R17M-G1-70 GPU

Security Classific ation

Security Classific ation

Security Classific ation

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PR OPERT Y OF C OMPAL EL ECTRO NICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PR OPERT Y OF C OMPAL EL ECTRO NICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PR OPERT Y OF C OMPAL EL ECTRO NICS, INC. AND CO NTAINS CONFIDENTIAL
AND T RADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D

AND T RADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D

AND T RADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISC LOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISC LOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISC LOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

Board ID / SKU ID Table for AD channel

POWER SEQUENCE

G-A

G-B

G-C

G-D

+RTCBATT

EC_ON

+5VALW

3V_EN

+3VALW/+0.775VALW

0.95_1.8VALW_PWREN

+1.8VALW/+0.95VALW

S5_MUX_CTRL

+APU_CORE_FCH

SYSON

+1.2V/+2.5V

SUSP#

+5VS/+3VS/+1.8VS/+0.6VS

0.95VS_PWR_EN#

+0.95VS

VR_ON

+APU_CORE

+APU_CORE_NB

+APU_GFX

VGA POWER SEQUENCE

PE_GPIO1/VGA_ON

+3VSDGPU

+1.8VSDGPU

VGA_ON_B

+VGA_CORE

+VDDCI

DGPU_PWROK

+1.35VSDGPU

PE_GPIO0

Compal Secret Data

Compal Secret Data

2017/04/18 2019/04/18

2017/04/18 2019/04/18

2017/04/18 2019/04/18

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

NOTES LIST

NOTES LIST

NOTES LIST

C5V08/D5PR8_LA-E903PR1A

C5V08/D5PR8_LA-E903PR1A

C5V08/D5PR8_LA-E903PR1A

E

550Tuesday, May 02, 2017

550Tuesday, May 02, 2017

550Tuesday, May 02, 2017

1.A

1.A

1.A

5

D D

R542 196_0402_1%

+0.95VS

4

PCIE_ARX_DTX_P0<28>
PCIE_ARX_DTX_N0<28>

PCIE_ARX_DTX_P1<29>
PCIE_ARX_DTX_N1<29>

PCIE_ARX_DTX_P2<30>
PCIE_ARX_DTX_N2<30>

PCIE_ARX_DTX_P3<30>
PCIE_ARX_DTX_N3<30>

1 2

U10

U9

T6
T5

T9
T8

P7
P6

U7

UAPU1B

P_GPP_RXP[0]

P_GPP_RXN[0]

P_GPP_RXP[1]

P_GPP_RXN[1]

P_GPP_RXP[2]

P_GPP_RXN[2]

P_GPP_RXP[3]

P_GPP_RXN[3]

P_ZVDDP

3

@

PCIE

PCIE_ATX_DRX_P0

LAN + CR

WLAN

PCIE SSD

P_GPP_TXP[0]

P_GPP_TXN[0]

P_GPP_TXP[1]

P_GPP_TXN[1]

P_GPP_TXP[2]

P_GPP_TXN[2]

P_GPP_TXP[3]

P_GPP_TXN[3]

P_ZVSS/P_RX_ZVDDP

R1

PCIE_ATX_DRX_N0

R2

PCIE_ATX_DRX_P1

R4

PCIE_ATX_DRX_N1

R3

PCIE_ATX_DRX_P2

N1

PCIE_ATX_DRX_N2

N2

PCIE_ATX_DRX_P3

N4

PCIE_ATX_DRX_N3

N3

U6

P_ZVSSP_ZVDDP

R541 196_0402_1%

1 2

C19 .1U_0402_16V7K

1 2

C20 .1U_0402_16V7K

1 2

C17 .1U_0402_16V7K

1 2

C18 .1U_0402_16V7K

1 2

C2702 .1U_0402_16V7K

1 2

C2701 .1U_0402_16V7K

1 2

C2704 .1U_0402_16V7K

1 2

C2703 .1U_0402_16V7K

1 2

2

PCIE_ATX_C_DRX_P0 <28>
PCIE_ATX_C_DRX_N0 <28>

PCIE_ATX_C_DRX_P1 <29>
PCIE_ATX_C_DRX_N1 <29>

PCIE_ATX_C_DRX_P2 <30>
PCIE_ATX_C_DRX_N2 <30>

PCIE_ATX_C_DRX_P3 <30>
PCIE_ATX_C_DRX_N3 <30>

1

P10

PEG_GTX_C_HRX_P0<15>
PEG_GTX_C_HRX_N0<15>

PEG_GTX_C_HRX_P1<15>
PEG_GTX_C_HRX_N1<15>

PEG_GTX_C_HRX_P2<15>
PEG_GTX_C_HRX_N2<15>

PEG_GTX_C_HRX_P3<15>
PEG_GTX_C_HRX_N3<15>

PEG_GTX_C_HRX_N4<15>

C C

PEG_GTX_C_HRX_P5<15>

PEG_GTX_C_HRX_N6<15>

PEG_GTX_C_HRX_P7<15>

CPU PN Table

CPU Platform

UAPU1 BR_A10@

S IC A10-9620P AM962PADY44AB 2.5G BGA 968P AP

SA0000AK010

B B

Bristol
15W

UAPU1 BR_A12@

S IC A12-9720P AM972PADY44AB 2.7G BGA 968P APU

SA0000AJY10

UAPU1 BR_FX@

PN R3(ABO!)PN R1(ROH)

UAPU1 BR_A10R3@

S IC A10-9620P AM962PADY44AB 2.5G ABO!

SA0000AK020

UAPU1 BR_A12R3@

S IC A12-9720P AM972PADY44AB 2.7G ABO!

SA0000AJY20

UAPU1 BR_FXR3@

P_GFX_RXP[0]

P9

P_GFX_RXN[0]

N6

P_GFX_RXP[1]

N5

P_GFX_RXN[1]

N9

P_GFX_RXP[2]

N8

P_GFX_RXN[2]

L7

P_GFX_RXP[3]

L6

P_GFX_RXN[3]

L10

P_GFX_RXP[4]

L9

P_GFX_RXN[4]

K6

P_GFX_RXP[5]

K5

P_GFX_RXN[5]

K9

P_GFX_RXP[6]

K8

P_GFX_RXN[6]

J7

P_GFX_RXP[7]

J6

P_GFX_RXN[7]

CPU PN Table

CPU Platform

Bristol
35W

FP4 REV 0.93

FP4_BGA968

UAPU1 BR_35WA10@

S IC A10-9630P AM963PAEY44AB 2.6G BGA968

SA0000AOQ00

UAPU1 BR_35WA12@

S IC A12-9730P AM973PAEY44AB 2.8G BGA968

SA0000AOR00

UAPU1 BR_35WFX@

P_GFX_TXP[0]

P_GFX_TXN[0]

P_GFX_TXP[1]

P_GFX_TXN[1]

P_GFX_TXP[2]

P_GFX_TXN[2]

P_GFX_TXP[3]

P_GFX_TXN[3]

P_GFX_TXP[4]

P_GFX_TXN[4]

P_GFX_TXP[5]

P_GFX_TXN[5]

P_GFX_TXP[6]

P_GFX_TXN[6]

P_GFX_TXP[7]

P_GFX_TXN[7]

M2
M1

L1
L2

L4
L3

J1
J2

J4
J3

H2
H1

G1
G2

G4
G3

PEG_HTX_C_GRX_P0 <15>
PEG_HTX_C_GRX_N0 <15>

PEG_HTX_C_GRX_P1 <15>
PEG_HTX_C_GRX_N1 <15>

PEG_HTX_C_GRX_P2 <15>
PEG_HTX_C_GRX_N2 <15>

PEG_HTX_C_GRX_P3 <15>
PEG_HTX_C_GRX_N3 <15>

PEG_HTX_C_GRX_P4 <15>PEG_GTX_C_HRX_P4<15>
PEG_HTX_C_GRX_N4 <15>

PEG_HTX_C_GRX_P5 <15>
PEG_HTX_C_GRX_N5 <15>PEG_GTX_C_HRX_N5<15>

PEG_HTX_C_GRX_P6 <15>PEG_GTX_C_HRX_P6<15>
PEG_HTX_C_GRX_N6 <15>

PEG_HTX_C_GRX_P7 <15>
PEG_HTX_C_GRX_N7 <15>PEG_GTX_C_HRX_N7<15>

PN R3(ABO!)PN R1(ROH)

S IC FX-9800P FM980PADY44AB 2.7G BGA 968P APU

SA00009LB00

S IC FX-9800P FM980PADY44AB 2.7G ABO!

SA00009LB40

S IC FX-9830P FM983PAEY44AB 3G BGA 968P

SA0000AOS00

CPU PN Table

CPU Platform

A A

Stoney

UAPU1 SR_A6@

S IC A6-9220 AM9220AVY23AC 2.5G BGA 968P

SA0000ALL00

5

PN R3(ABO!)PN R1(ROH)

UAPU1 SR_A6R3@

S IC A6-9220 AM9220AVY23AC 2.5G BGA ABO!

SA0000ALL10

4

Security Classification

Security Classification

Security Classification

2017/04/18 2019/04/18

2017/04/18 2019/04/18

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGIN EERING DRAWING IS THE PROPRI ETARY PRO PERTY OF C OMPAL ELE CTRONI CS, INC . A ND CONTAI NS CONFIDENTIAL

THIS SHEET OF ENGIN EERING DRAWING IS THE PROPRI ETARY PRO PERTY OF C OMPAL ELE CTRONI CS, INC . A ND CONTAI NS CONFIDENTIAL

THIS SHEET OF ENGIN EERING DRAWING IS THE PROPRI ETARY PRO PERTY OF C OMPAL ELE CTRONI CS, INC . A ND CONTAI NS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2017/04/18 2019/04/18

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

FP4 PCIE

FP4 PCIE

FP4 PCIE

C5V08/D5PR8_LA-E903PR1A

C5V08/D5PR8_LA-E903PR1A

C5V08/D5PR8_LA-E903PR1A

650Tuesday, May 02, 2017

650Tuesday, May 02, 2017

650Tuesday, May 02, 2017

1

1.A

1.A

1.A

5

4

3

2

1

@

DDRA_SMA[13..0]<13>

D D

DDRA_BG1<13>

MEM_MA_ACT#<13> MEM_MB_ACT#<14>

DDRA_SBS0#<13>
DDRA_SBS1#<13>
DDRA_BG0<13>

DDRA_SDM[7..0]<13>

DDRA_SDQS0<13>
DDRA_SDQS0#<13>
DDRA_SDQS1<13>
DDRA_SDQS1#<13>

C C

B B

DDRA_SDQS2<13>
DDRA_SDQS2#<13>
DDRA_SDQS3<13>
DDRA_SDQS3#<13>
DDRA_SDQS4<13>
DDRA_SDQS4#<13>
DDRA_SDQS5<13>
DDRA_SDQS5#<13>
DDRA_SDQS6<13>
DDRA_SDQS6#<13>
DDRA_SDQS7<13>
DDRA_SDQS7#<13>

DDRA_CLK0<13>
DDRA_CLK0#<13>
DDRA_CLK1<13>
DDRA_CLK1#<13>

MEM_MA_RST#<13>

MEM_MA_EVENT#<13>

DDRA_CKE0<13>
DDRA_CKE1<13>

DDRA_ODT0<13>
DDRA_ODT1<13>

DDRA_SCS0#<13>
DDRA_SCS1#<13>

DDRA_SMA16<13>
DDRA_SMA15<13>
DDRA_SMA14<13>

T80
T4957

DDRA_SMA0
DDRA_SMA1
DDRA_SMA2
DDRA_SMA3
DDRA_SMA4
DDRA_SMA5
DDRA_SMA6
DDRA_SMA7
DDRA_SMA8
DDRA_SMA9
DDRA_SMA10
DDRA_SMA11
DDRA_SMA12
DDRA_SMA13
DDRA_BG1
MEM_MA_ACT#

DDRA_SBS0#
DDRA_SBS1#
DDRA_BG0

DDRA_SDM0
DDRA_SDM1
DDRA_SDM2
DDRA_SDM3
DDRA_SDM4
DDRA_SDM5
DDRA_SDM6
DDRA_SDM7

DDRA_SDQS0
DDRA_SDQS0#
DDRA_SDQS1
DDRA_SDQS1#
DDRA_SDQS2
DDRA_SDQS2#
DDRA_SDQS3
DDRA_SDQS3#
DDRA_SDQS4
DDRA_SDQS4#
DDRA_SDQS5
DDRA_SDQS5#
DDRA_SDQS6
DDRA_SDQS6#
DDRA_SDQS7
DDRA_SDQS7#

DDRA_CLK0
DDRA_CLK0#
DDRA_CLK1
DDRA_CLK1#

MEM_MA_RST#
MEM_MA_EVENT#

DDRA_CKE0
DDRA_CKE1

DDRA_ODT0
DDRA_ODT1

DDRA_SCS0#
DDRA_SCS1#

DDRA_SMA16
DDRA_SMA15
DDRA_SMA14

MA_VREFDQ
M_VREF

UAPU1A

AE28

MA_ADD[0]

Y27

MA_ADD[1]

Y29

MA_ADD[2]

Y26

MA_ADD[3]

W28

MA_ADD[4]

W29

MA_ADD[5]

W26

MA_ADD[6]

U29

MA_ADD[7]

W25

MA_ADD[8]

U26

MA_ADD[9]

AG29

MA_ADD[10]

U27

MA_ADD[11]

T28

MA_ADD[12]

AK26

MA_ADD[13]

T26

MA_ADD[14]/MA_BG[1]

T25

MA_ADD[15]/MA_ACT_L

AG26

MA_BANK[0]

AG27

MA_BANK[1]

T29

MA_BANK[2]/MA_BG[0]

E19

MA_DM[0]

D21

MA_DM[1]

K21

MA_DM[2]

F29

MA_DM[3]

AP28

MA_DM[4]

AV26

MA_DM[5]

AR22

MA_DM[6]

BC22

MA_DM[7]

K29

MA_DM[8]

H19

MA_DQS_H[0]

G19

MA_DQS_L[0]

B22

MA_DQS_H[1]

A22

MA_DQS_L[1]

F23

MA_DQS_H[2]

E23

MA_DQS_L[2]

G27

MA_DQS_H[3]

F27

MA_DQS_L[3]

AP25

MA_DQS_H[4]

AP26

MA_DQS_L[4]

AW27

MA_DQS_H[5]

AV27

MA_DQS_L[5]

AV22

MA_DQS_H[6]

AU22

MA_DQS_L[6]

BA21

MA_DQS_H[7]

AY21

MA_DQS_L[7]

L27

MA_DQS_H[8]

L26

MA_DQS_L[8]

AE25

MA_CLK_H[0]

AE26

MA_CLK_L[0]

AD26

MA_CLK_H[1]

AD27

MA_CLK_L[1]

AB28

MA_CLK_H[2]

AB29

MA_CLK_L[2]

AB25

MA_CLK_H[3]

AB26

MA_CLK_L[3]

N29

MA_RESET_L

AE29

MA_EVENT_L

P27

MA_CKE0

P29

MA_CKE1

AK27

MA0_ODT[0]

AL26

MA0_ODT[1]

AH25

MA1_ODT[0]

AL25

MA1_ODT[1]

AH26

MA0_CS_L[0]

AL29

MA0_CS_L[1]

AH29

MA1_CS_L[0]

AL28

MA1_CS_L[1]

AG24

MA_RAS_L/MA_RAS_L_ADD[16]

AK29

MA_CAS_L/MA_CAS_L_ADD[15]

AH28

MA_WE_L/MA_WE_L_ADD[14]

B19

MA_VREFDQ

T32

M_VREF

MEMORY A

FP4 REV 0.93

FP4_BGA968

MA_DATA[0]

MA_DATA[1]

MA_DATA[2]

MA_DATA[3]

MA_DATA[4]

MA_DATA[5]

MA_DATA[6]

MA_DATA[7]

MA_DATA[8]

MA_DATA[9]

MA_DATA[10]

MA_DATA[11]

MA_DATA[12]

MA_DATA[13]

MA_DATA[14]

MA_DATA[15]

MA_DATA[16]

MA_DATA[17]

MA_DATA[18]

MA_DATA[19]

MA_DATA[20]

MA_DATA[21]

MA_DATA[22]

MA_DATA[23]

MA_DATA[24]

MA_DATA[25]

MA_DATA[26]

MA_DATA[27]

MA_DATA[28]

MA_DATA[29]

MA_DATA[30]

MA_DATA[31]

MA_DATA[32]

MA_DATA[33]

MA_DATA[34]

MA_DATA[35]

MA_DATA[36]

MA_DATA[37]

MA_DATA[38]

MA_DATA[39]

MA_DATA[40]

MA_DATA[41]

MA_DATA[42]

MA_DATA[43]

MA_DATA[44]

MA_DATA[45]

MA_DATA[46]

MA_DATA[47]

MA_DATA[48]

MA_DATA[49]

MA_DATA[50]

MA_DATA[51]

MA_DATA[52]

MA_DATA[53]

MA_DATA[54]

MA_DATA[55]

MA_DATA[56]

MA_DATA[57]

MA_DATA[58]

MA_DATA[59]

MA_DATA[60]

MA_DATA[61]

MA_DATA[62]

MA_DATA[63]

MA_CHECK[0]

MA_CHECK[1]

MA_CHECK[2]

MA_CHECK[3]

MA_CHECK[4]

MA_CHECK[5]

MA_CHECK[6]

MA_CHECK[7]

MA_ZVDDIO_MEM_S

H17
J17
F20
H20
E17
F17
K18
E20

A21
C21
C23
D23
B20
B21
B23
A23

G22
H22
E25
G25
J20
E22
H23
J23

F26
E27
J26
J27
H25
E26
G28
G29

AN26
AP29
AR26
AP24
AN29
AN27
AR29
AR27

AU26
AV29
AU25
AW25
AU29
AU28
AW26
AT25

AV23
AW23
AV20
AW20
AR23
AT23
AR20
AT20

BB23
BB22
BB20
AY19
BA23
BC23
BC21
BB21

K26
K28
N26
N28
J29
K25
L29
N25

AD29

DDRA_SDQ0
DDRA_SDQ1
DDRA_SDQ2
DDRA_SDQ3
DDRA_SDQ4
DDRA_SDQ5
DDRA_SDQ6
DDRA_SDQ7

DDRA_SDQ8
DDRA_SDQ9
DDRA_SDQ10
DDRA_SDQ11
DDRA_SDQ12
DDRA_SDQ13
DDRA_SDQ14
DDRA_SDQ15

DDRA_SDQ16
DDRA_SDQ17
DDRA_SDQ18
DDRA_SDQ19
DDRA_SDQ20
DDRA_SDQ21
DDRA_SDQ22
DDRA_SDQ23

DDRA_SDQ24
DDRA_SDQ25
DDRA_SDQ26
DDRA_SDQ27
DDRA_SDQ28
DDRA_SDQ29
DDRA_SDQ30
DDRA_SDQ31

DDRA_SDQ32
DDRA_SDQ33
DDRA_SDQ34
DDRA_SDQ35
DDRA_SDQ36
DDRA_SDQ37
DDRA_SDQ38
DDRA_SDQ39

DDRA_SDQ40
DDRA_SDQ41
DDRA_SDQ42
DDRA_SDQ43
DDRA_SDQ44
DDRA_SDQ45
DDRA_SDQ46
DDRA_SDQ47

DDRA_SDQ48
DDRA_SDQ49
DDRA_SDQ50
DDRA_SDQ51
DDRA_SDQ52
DDRA_SDQ53
DDRA_SDQ54
DDRA_SDQ55

DDRA_SDQ56
DDRA_SDQ57
DDRA_SDQ58
DDRA_SDQ59
DDRA_SDQ60
DDRA_SDQ61
DDRA_SDQ62
DDRA_SDQ63

MEM_MA_ZVDDIO

DDRA_SDQ[63..0] <13>

R74

39.2_0402_1%

1 2

T1@

+1.2V

DDRB_SMA[13..0]<14>

DDRB_BG1<14>

DDRB_SBS0#<14>
DDRB_SBS1#<14>
DDRB_BG0<14>

DDRB_SDM[7..0]<14>

DDRB_SDQS0<14>
DDRB_SDQS0#<14>
DDRB_SDQS1<14>
DDRB_SDQS1#<14>
DDRB_SDQS2<14>
DDRB_SDQS2#<14>
DDRB_SDQS3<14>
DDRB_SDQS3#<14>
DDRB_SDQS4<14>
DDRB_SDQS4#<14>
DDRB_SDQS5<14>
DDRB_SDQS5#<14>
DDRB_SDQS6<14>
DDRB_SDQS6#<14>
DDRB_SDQS7<14>
DDRB_SDQS7#<14>

DDRB_CLK0<14>
DDRB_CLK0#<14>
DDRB_CLK1<14>
DDRB_CLK1#<14>

MEM_MB_RST#<14>

MEM_MB_EVENT#<14>

DDRB_CKE0<14>
DDRB_CKE1<14>

DDRB_ODT0<14>
DDRB_ODT1<14>

DDRB_SCS0#<14>
DDRB_SCS1#<14>

DDRB_SMA16<14>
DDRB_SMA15<14>
DDRB_SMA14<14>

T45

DDRB_SMA0
DDRB_SMA1
DDRB_SMA2
DDRB_SMA3
DDRB_SMA4
DDRB_SMA5
DDRB_SMA6
DDRB_SMA7
DDRB_SMA8
DDRB_SMA9
DDRB_SMA10
DDRB_SMA11
DDRB_SMA12
DDRB_SMA13
DDRB_BG1
MEM_MB_ACT#

DDRB_SBS0#
DDRB_SBS1#
DDRB_BG0

DDRB_SDM0
DDRB_SDM1
DDRB_SDM2
DDRB_SDM3
DDRB_SDM4
DDRB_SDM5
DDRB_SDM6
DDRB_SDM7

DDRB_SDQS0
DDRB_SDQS0#
DDRB_SDQS1
DDRB_SDQS1#
DDRB_SDQS2
DDRB_SDQS2#
DDRB_SDQS3
DDRB_SDQS3#
DDRB_SDQS4
DDRB_SDQS4#
DDRB_SDQS5
DDRB_SDQS5#
DDRB_SDQS6
DDRB_SDQS6#
DDRB_SDQS7
DDRB_SDQS7#

DDRB_CLK0
DDRB_CLK0#
DDRB_CLK1
DDRB_CLK1#

MEM_MB_RST#
MEM_MB_EVENT#

DDRB_CKE0
DDRB_CKE1

DDRB_ODT0
DDRB_ODT1

DDRB_SCS0#
DDRB_SCS1#

DDRB_SMA16
DDRB_SMA15
DDRB_SMA14

MB_VREFDQ

UAPU1I

AG31

MB_ADD[0]

AC30

MB_ADD[1]

AC31

MB_ADD[2]

AB32

MB_ADD[3]

AA32

MB_ADD[4]

AA33

MB_ADD[5]

AA31

MB_ADD[6]

Y33

MB_ADD[7]

AA30

MB_ADD[8]

W32

MB_ADD[9]

AG32

MB_ADD[10]

Y32

MB_ADD[11]

W33

MB_ADD[12]

AL31

MB_ADD[13]

W30

MB_ADD[14]/MB_BG[1]

V32

MB_ADD[15]/MB_ACT_L

AH32

MB_BANK[0]

AG33

MB_BANK[1]

W31

MB_BANK[2]/MB_BG[0]

D25

MB_DM[0]

D29

MB_DM[1]

E33

MB_DM[2]

J33

MB_DM[3]

AR30

MB_DM[4]

AW30

MB_DM[5]

BC30

MB_DM[6]

BC26

MB_DM[7]

N33

MB_DM[8]

B26

MB_DQS_H[0]

A26

MB_DQS_L[0]

B30

MB_DQS_H[1]

A30

MB_DQS_L[1]

F32

MB_DQS_H[2]

E32

MB_DQS_L[2]

K32

MB_DQS_H[3]

J32

MB_DQS_L[3]

AR32

MB_DQS_H[4]

AR33

MB_DQS_L[4]

AW32

MB_DQS_H[5]

AW33

MB_DQS_L[5]

BA29

MB_DQS_H[6]

AY29

MB_DQS_L[6]

BA25

MB_DQS_H[7]

AY25

MB_DQS_L[7]

P32

MB_DQS_H[8]

N32

MB_DQS_L[8]

AE33

MB_CLK_H[0]

AE32

MB_CLK_L[0]

AE30

MB_CLK_H[1]

AE31

MB_CLK_L[1]

AD32

MB_CLK_H[2]

AD33

MB_CLK_L[2]

AC33

MB_CLK_H[3]

AC32

MB_CLK_L[3]

T33

MB_RESET_L

AG30

MB_EVENT_L

U32

MB_CKE0

U33

MB_CKE1

AL30

MB0_ODT[0]

AM32

MB0_ODT[1]

AJ32

MB1_ODT[0]

AM33

MB1_ODT[1]

AJ33

MB0_CS_L[0]

AL32

MB0_CS_L[1]

AJ30

MB1_CS_L[0]

AL33

MB1_CS_L[1]

AH33

MB_RAS_L/MB_RAS_L_ADD[16]

AK32

MB_CAS_L/MB_CAS_L_ADD[15]

AJ31

MB_WE_L/MB_WE_L_ADD[14]

A19

MB_VREFDQ

@

MEMORY B

FP4 REV 0.93

FP4_BGA968

MB_DATA[0]

MB_DATA[1]

MB_DATA[2]

MB_DATA[3]

MB_DATA[4]

MB_DATA[5]

MB_DATA[6]

MB_DATA[7]

MB_DATA[8]

MB_DATA[9]

MB_DATA[10]

MB_DATA[11]

MB_DATA[12]

MB_DATA[13]

MB_DATA[14]

MB_DATA[15]

MB_DATA[16]

MB_DATA[17]

MB_DATA[18]

MB_DATA[19]

MB_DATA[20]

MB_DATA[21]

MB_DATA[22]

MB_DATA[23]

MB_DATA[24]

MB_DATA[25]

MB_DATA[26]

MB_DATA[27]

MB_DATA[28]

MB_DATA[29]

MB_DATA[30]

MB_DATA[31]

MB_DATA[32]

MB_DATA[33]

MB_DATA[34]

MB_DATA[35]

MB_DATA[36]

MB_DATA[37]

MB_DATA[38]

MB_DATA[39]

MB_DATA[40]

MB_DATA[41]

MB_DATA[42]

MB_DATA[43]

MB_DATA[44]

MB_DATA[45]

MB_DATA[46]

MB_DATA[47]

MB_DATA[48]

MB_DATA[49]

MB_DATA[50]

MB_DATA[51]

MB_DATA[52]

MB_DATA[53]

MB_DATA[54]

MB_DATA[55]

MB_DATA[56]

MB_DATA[57]

MB_DATA[58]

MB_DATA[59]

MB_DATA[60]

MB_DATA[61]

MB_DATA[62]

MB_DATA[63]

MB_CHECK[0]

MB_CHECK[1]

MB_CHECK[2]

MB_CHECK[3]

MB_CHECK[4]

MB_CHECK[5]

MB_CHECK[6]

MB_CHECK[7]

MB_ZVDDIO_MEM_S

A25
C25
C27
D27
B24
B25
B27
A27

A29
C29
B32
D32
B28
B29
A31
C31

E30
E31
G33
G32
C33
D33
G30
G31

J30
J31
L33
L32
H32
H33
L30
L31

AN31
AP32
AT32
AU32
AN33
AN32
AR31
AT33

AU30
AV32
BA33
AY32
AU33
AU31
AW31
AY33

BC31
BB30
BB28
AY27
BB32
BA31
BC29
BB29

BB27
BB26
BB24
AY23
BA27
BC27
BC25
BB25

N30
N31
R33
R32
M32
M33
R30
R31

AF32

DDRB_SDQ0
DDRB_SDQ1
DDRB_SDQ2
DDRB_SDQ3
DDRB_SDQ4
DDRB_SDQ5
DDRB_SDQ6
DDRB_SDQ7

DDRB_SDQ8
DDRB_SDQ9
DDRB_SDQ10
DDRB_SDQ11
DDRB_SDQ12
DDRB_SDQ13
DDRB_SDQ14
DDRB_SDQ15

DDRB_SDQ16
DDRB_SDQ17
DDRB_SDQ18
DDRB_SDQ19
DDRB_SDQ20
DDRB_SDQ21
DDRB_SDQ22
DDRB_SDQ23

DDRB_SDQ24
DDRB_SDQ25
DDRB_SDQ26
DDRB_SDQ27
DDRB_SDQ28
DDRB_SDQ29
DDRB_SDQ30
DDRB_SDQ31

DDRB_SDQ32
DDRB_SDQ33
DDRB_SDQ34
DDRB_SDQ35
DDRB_SDQ36
DDRB_SDQ37
DDRB_SDQ38
DDRB_SDQ39

DDRB_SDQ40
DDRB_SDQ41
DDRB_SDQ42
DDRB_SDQ43
DDRB_SDQ44
DDRB_SDQ45
DDRB_SDQ46
DDRB_SDQ47

DDRB_SDQ48
DDRB_SDQ49
DDRB_SDQ50
DDRB_SDQ51
DDRB_SDQ52
DDRB_SDQ53
DDRB_SDQ54
DDRB_SDQ55

DDRB_SDQ56
DDRB_SDQ57
DDRB_SDQ58
DDRB_SDQ59
DDRB_SDQ60
DDRB_SDQ61
DDRB_SDQ62
DDRB_SDQ63

MEM_MB_ZVDDIO

DDRB_SDQ[63..0] <14>

R75

39.2_0402_1%

1 2

+1.2V

+1.2V

R3979

2D@

1K_0402_5%

MEM_MA_EVENT#

12

R3994
1K_0402_5%

MEM_MB_EVENT#

12

A A

Security Classific ation

Security Classific ation

Security Classific ation

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PR OPERT Y OF C OMPAL EL ECTRO NICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PR OPERT Y OF C OMPAL EL ECTRO NICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PR OPERT Y OF C OMPAL EL ECTRO NICS, INC. AND CO NTAINS CONFIDENTIAL
AND T RADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D

AND T RADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D

AND T RADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISC LOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISC LOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISC LOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/04/18 2019/04/18

2017/04/18 2019/04/18

2017/04/18 2019/04/18

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

FP4 MEMORY INTERFACE

FP4 MEMORY INTERFACE

FP4 MEMORY INTERFACE

C5V08/D5PR8_LA-E903PR1A

C5V08/D5PR8_LA-E903PR1A

C5V08/D5PR8_LA-E903PR1A

1

750Tuesday, May 02, 2017

750Tuesday, May 02, 2017

750Tuesday, May 02, 2017

1.A

1.A

1.A

A

www.vinafix.com

B

C

D

E

+1.8VS

RP14

@

APU_SVT_R

18

APU_SVC

27

APU_SVD

36

1 1

45

1K_0804_8P4R_5%

RP17

@

GFX_SVC

18

GFX_SVD

27

GFX_SVT_R

36
45

1K_0804_8P4R_5%

1 2
1 2

1 2
1 2

1 2
1 2

APU_DP1_P0<26>
APU_DP1_N0<26>

APU_DP1_P1<26>
APU_DP1_N1<26>

APU_DP1_P2<26>
APU_DP1_N2<26>

APU_DP1_P3<26>
APU_DP1_N3<26>

EDP_TXP0<27>
EDP_TXN0<27>

EDP_TXP1<27>
EDP_TXN1<27>

EDP_TXP2<27>
EDP_TXN2<27>

EDP_TXP3<27>
EDP_TXN3<27>

APU_SVT_R
APU_SVC_R
APU_SVD_R

GFX_SVT_R
GFX_SVC_R
GFX_SVD_R

APU_SIC
APU_SID

APU_RST#
APU_PWROK

APU_PROCHOT#

APU_ALERT#

APU_TDI
APU_TDO
APU_TCK
APU_TMS
APU_TRST#
APU_DBRDY
APU_DBREQ#

C15
D17
D19

B15
B16
A18

B18
C17

D15
C19

A15
B17

H15
H14
D13
G15

C13
A11

J14

APU_PROCHOT#
APU_RST#
APU_PWROK

2 2

+1.8VS

3 3

RP25

1

EMC@

C2647
33P_0402_50V8J

2

APU_PROCHOT#

18

APU_SID

27

APU_ALERT#

36

APU_SIC

45

1

EMC@

C2648
33P_0402_50V8J

2

APU_SVT_R<44>
APU_SVC<44>
APU_SVD<44>

GFX_SVT_R<45>
GFX_SVC<45>
GFX_SVD<45>

APU_PROCHOT#<16,24,44,45>

Close to APU

1

@EMC@

C2649
.1U_040 2_16V7K

2

R2612 0_0402_5%
R2613 0_0402_5%

R2614 0_0402_5%T1@
R2615 0_0402_5%T1@

R80 300_0402_5%

+1.8VS

R82 300_0402_5%

+1.8VS

APU_PWROK<44,45>

1K_0804_8P4R_5%

+1.8VS

+3VS

1 2

R3969 2.2K_0402_5%

1 2

R3970 2.2K_0402_5%

EC_SMB_CK2

EC_SMB_DA2

EC_SMB_CK2<16,24>

EC_SMB_DA2<16,24>

EC_SMB_CK2

EC_SMB_DA2

5

3 4

SGD

Q79A

2

DMN63D8LDW_SOT363-6

G

6 1

S

D

Q79B
DMN63D8LDW_SOT363-6

VGS,on = 0.8~1.5V

APU_SIC

APU_SID

B6
A6

D7
C7

A7
B7

D9
C9

A2
A3

B4
A4

D5
C5

A5
B5

E2
E1

E3
E4

D1
D2

C1
B1

UAPU1C

DP2_TXP[0]

DP2_TXN[0]

DP2_TXP[1]

DP2_TXN[1]

DP2_TXP[2]

DP2_TXN[2]

DP2_TXP[3]

DP2_TXN[3]

DP1_TXP[0]

DP1_TXN[0]

DP1_TXP[1]

DP1_TXN[1]

DP1_TXP[2]

DP1_TXN[2]

DP1_TXP[3]

DP1_TXN[3]

DP0_TXP[0]

DP0_TXN[0]

DP0_TXP[1]

DP0_TXN[1]

DP0_TXP[2]

DP0_TXN[2]

DP0_TXP[3]

DP0_TXN[3]

SVT0

SVC0

SVD0

SVT1

SVC1

SVD1

SIC

SID

RESET_L

PWROK

PROCHOT_L

ALERT_L

TDI

TDO

TCK

TMS

TRST_L

DBRDY

DBREQ_L

@

DISPLAY/SV I2/JTAG/TES T

FP4 REV 0.93

FP4_BGA968

DP_ZVSS

DP_AUX_ZVSS

DP_BLON

DP_DIGON

DP_VARY_BL

DP2_AUXP

DP2_AUXN

DP2_HPD

DP1_AUXP

DP1_AUXN

DP1_HPD

DP0_AUXP

DP0_AUXN

DP0_HPD

RSVD_1

TEMPIN0

TEMPIN1

TEMPIN2

TEMPINRETURN

TEST410

TEST411

TEST28_H

TEST28_L

DP_STEREOSYNC/TEST36

VDDCR_GFX_SENSE

VDDCR_NB_SENSE

VDDCR_CPU_SENSE

VDDP_SENSE

VSS_SENSE

A9
B9
G5
G6
F11

H9
G9
E9

F7
E7
F5

F8
E8
G8

K24
E15
E14
E12
F14
AK24
AL24
P24

TEST4

N24

TEST5

AN24

TEST6

AB8

TEST9

Y9

TEST10

B10

TEST14

D11

TEST15

A10

TEST16

C11

TEST17

B11

TEST11

A14

TEST18

B14

TEST19

A13
B13
P26

TEST31

E11
A17

TEST37

H11
J12
G12
AY18

H12

APU_TRST#

DP_ZVSS
DP_AUX_ZVSS
ENBKL_R
ENVDD_R
INVT PWM_ R

APU_TEST410
APU_TEST411
APU_TEST4
APU_TEST5

1 2

R400 2K_0402_1%

1 2

R401 150_0402_1%

HDMI_SCLK <26>
HDMI_SDATA <26>
HDMI_HPD <26>

EDP_AUXP <27>
EDP_AUXN <27>

EDP_HPD <27>

TP@

T32

TP@

T33

TP@

T34

TP@

T35

ENVDD_R

ENBKL_R

+1.8VALW

5

U64

1

P

NC

2

A

G

NL17SZ07DFT2G_SC70-5

3

SA00004BV00

+1.8VALW

5

U2610

1

P

NC

2

A

G

NL17SZ07DFT2G_SC70-5

3

SA00004BV00

4

Y

@

Y

ENVDD <27>

4

ENBKL <24>

ENVDD

INVT PWM

ENBKL

APU_TEST14
APU_TEST15
APU_TEST16
APU_TEST17
APU_TEST11
APU_TEST18
APU_TEST19

APU_TEST28_H
APU_TEST28_L
APU_TEST31
APU_TEST36 APU_TEST36
APU_TEST37

APU_COREGFX_SEN_H <45>
APU_CORENB_SEN_H <44>
APU_CORE_SEN_H <44>

T40

T43
T42
T41

APU_VSS_SEN_L <44,45>

TP@

TP@
TP@
TP@

+1.8VS

APU_TEST11
APU_TEST17
APU_TEST16
APU_TEST14

APU_TEST37

1

3

5

7

1 2

R671 33_0402_5%

1 8
2 7
3 6
4 5

APU_TRST#_R

RP29

10K_0804_8P4R_5%

HDT_P11

HDT_P13

HDT_P15

9

11

13

15

17

19

1 2

1 2

HDT+

JHDT1

@

1

3

5

7

9

11

13

15

17

19

RP30

@

18
27
36
45

1K_0804_8P4R_5%

@

R117
1K_0402_5%

@

R118
1K_0402_5%

APU_TCK_R

2

2

APU_TMS_R

4

4

APU_TDI_R

6

6

APU_TDO_R

8

8

APU_PWROK_R

10

10

APU_RST#_R

12

12

APU_DBRDY_R

14

14

APU_DBREQ#_R

16

16

APU_TEST19

18

18

APU_TEST18

20

20

+1.8VS

1 2

@

R706 0_0402_5%

1 2

@

R694 0_0402_5%

1 2

@

R705 0_0402_5%

1 2

@

R704 0_0402_5%

1 2

@

R682 0_0402_5%

1 2

@

R707 0_0402_5%

1 2

@

R708 0_0402_5%

1 2

R672 33_0402_5%

SAMTE_ASP-136446-07-B

INVT PWM_ R

ENVDD_R

1 2

@

R1160

4.7K_0402_5%

1 2

R1161

4.7K_0402_5%

1 2

R3905

4.7K_0402_5%

1 2

R155
1K_0402_5%

1 2

R154
1K_0402_5%

APU_TCK

APU_TMS

APU_TDI

APU_TDO

APU_PWROK

APU_RST#

APU_DBRDY

APU_DBREQ#

+1.8VALW

5

1

P

NC

2

A

G

3

1 2

R683 0_0402_5%RS@

+3VS

@

APU_DBREQ#
APU_TDI
APU_TMS
APU_TCK

APU_TRST#
APU_TEST19
APU_TEST18

APU_TRST#

U2611

4

Y

NL17SZ07DFT2G_SC70-5

SA00004BV00

ENVDD_R

INVT PWM_ R

ENBKL_R

INVT PWM <27>

1 2

R3847
100K_0402_5%

1 2

@

R3835
100K_0402_5%

1 2

R3906
100K_0402_5%

+1.8VS

RP28

1 8
2 7
3 6
4 5

1K_0804_8P4R_5%

RP27

1 8
2 7
3 6
4 5

1K_0804_8P4R_5%

1 2

C141

0.01U_0402_16V7K

ENVDD

+1.8VS

+1.8VS

4 4

Security Classification

Security Classification

Security Classification

2017/04/18 2019/04/18

2017/04/18 2019/04/18

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGIN EERING DRAWING IS THE PROPRI ETARY PRO PERTY OF C OMPAL ELE CTRONI CS, INC . A ND CONTAI NS CONFIDENTIAL

THIS SHEET OF ENGIN EERING DRAWING IS THE PROPRI ETARY PRO PERTY OF C OMPAL ELE CTRONI CS, INC . A ND CONTAI NS CONFIDENTIAL

THIS SHEET OF ENGIN EERING DRAWING IS THE PROPRI ETARY PRO PERTY OF C OMPAL ELE CTRONI CS, INC . A ND CONTAI NS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2017/04/18 2019/04/18

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

FP4 DISP/MISC/HDT

FP4 DISP/MISC/HDT

FP4 DISP/MISC/HDT

C5V08/D5PR8_LA-E903PR1A

C5V08/D5PR8_LA-E903PR1A

C5V08/D5PR8_LA-E903PR1A

850Tuesday, May 02, 2017

850Tuesday, May 02, 2017

850Tuesday, May 02, 2017

E

1.A

1.A

1.A

A

1 2

C912 150P_0402_50V8J

1 2

C615 150P_0402_50V8J

1 2

LPC_RST#<24,33>

APU_PCIE_RST#<15,28,29,30>

1 1

2 2

+3VALW

1 2

R930 10K_0402_5%@

1 2

R905 100K_0402_5%@

1 2

R3927 10K_0402_5%

1 2

R685 10K_0402_5%@

1 2

R686 10K_0402_5%@

1 2

R2616 2.2K_0402_5%@

3 3

4 4

1 2

R2618 1K_0402_5%@

1 2

R2617 2.2K_0402_5%@

1 2

R3948 10K_0402_5%

+3VS

1 2

R676 2.2K_0402_5%

1 2

R677 2.2K_0402_5%

1 2

R3863 10K_0402_5%@

1 2

R3864 10K_0402_5%@

1 2

R3975 10K_0402_5%@

+1.8VS

1 2

R3946 10K_0402_5%

1 2

R3947 10K_0402_5%

1 2

R3945 10K_0402_5%@

1 2

R3929 10K_0402_5%

1 2

R3928 10K_0402_5%

1 2

R3954 10K_0402_5%@

1 2

R3850 10K_0402_5%

1 2

R3879 0_0402_5%@

1 2

R40 15K_0402_5%

1 2

R41 15K_0402_5%

1 2

R42 15K_0402_5%

1 2

R3949 10K_0402_5%

1 2

R3950 10K_0402_5%

1 2

R3961 10K_0402_5%T3@

R602 33_0402_5%
R907 33_0402_5%

EC_RSMRST#<24>

PBTN_OUT#<24>

SYS_PWRGD_EC<24>

SLP_S3#<24>
SLP_S5#<24>

S5_MUX_CTRL<25>

KBRST#<24>
GATEA20<24>
EC_SCI#<24>

LAN_CLKREQ#<28>
WLAN_CLKREQ#<29>
DGPU_PWROK<47,48>
SSD_CLKREQ#<30>
PEG_CLKREQ#<16>

USB_OC0#<31>

APU_PCIE_WAKE#
USB_OC0#

EC_SCI#
APU_I2C3_SCL
APU_I2C3_SDA

APU_TEST0
APU_TEST1
APU_TEST2

AGPIO8

APU_SMB_CLK0
APU_SMB_DATA0
LAN_CLKREQ#
WLAN_CLKREQ#
SSD_CLKREQ#

APU_I2C1_SCL
APU_I2C1_SDA

HDA_SDIN0
HDA_SDIN1
HDA_SDIN2
HDA_BITCLK

PEG_CLKREQ#
HVB

APU_TEST0
APU_TEST1
APU_TEST2

APU_I2C0_SCL
APU_I2C0_SDA
VDDGFX_PWRGD

A

1 2

HDA_SDIN0<34>

APU_I2C1_SCL<30>
APU_I2C1_SDA<30>

1U_0402_6.3V6K

Length<1.0"

LPC_RST_A#
APU_PCIE_RST#_R

EC_RSMRST#

PBTN_OUT#
SYS_PWRGD_EC
SYS_RST#
APU_PCIE_WAKE#

SLP_S3#
SLP_S5#

AGPIO10

APU_TEST0
APU_TEST1
APU_TEST2

KBRST#
GATEA20

EC_SCI#

AGPIO12
LAN_CLKREQ#

WLAN_CLKREQ#
DGPU_PWROK
SSD_CLKREQ#
PEG_CLKREQ#
USB_OC0#

HDA_BITCLK
HDA_SDIN0
HDA_SDIN1
HDA_SDIN2
HDA_RST#
HDA_SYNC
HDA_SDOUT

APU_I2C0_SCL
APU_I2C0_SDA
APU_I2C1_SCL
APU_I2C1_SDA

RTC_CLK

32K_X1

32K_X2

HDA_BITCLK_AUDIO<34>
HDA_SDOUT_AUDIO<34>
HDA_SYNC_AUDIO<34>
HDA_RST#_AUDIO<34>

+1.8VALW +3VS

R346

22K_0402_1%

EC_RSMRST#

SYS_PWRGD_EC

C999

B

@

UAPU1D

BB12

LPC_RST_L

AN7

PCIE_RST_L/EGPIO26

AE4

RSMRST_L

AE1

PWR_BTN_L/AGPIO0

BC9

PWR_GOOD

AF2

SYS_RESET_L/AGPIO1

AG2

WAKE_L/AGPIO2

AK7

SLP_S3_L

AH5

SLP_S5_L

AE8

S0A3_GPIO/AGPIO10

AH8

S5_MUX_CTRL/EGPIO42

AH6

TEST0

AK8

TEST1/TMS

AE3

TEST2

AY15

ESPI_RESET_L/KBRST_L/AGPIO129

BC19

GA20IN/AGPIO126

AD7

LPC_PME_L/AGPIO22

BB13

LPC_SMI_L/AGPIO86

AG3

AC_PRES/USB_OC4_L/IR_RX0/AGPI O23

AD5

IR_TX0/USB_OC5_L/AGPIO13

AL8

IR_TX1/USB_OC6_L/AGPIO14

AN8

IR_RX1/AGPIO15

AE2

IR_LED_L/LLB_L/AGPIO12

BC15

CLK_REQ0_L/SATA_IS0_L/SATA_ZP0_L/AGPIO92

BB17

CLK_REQ1_L/AGPIO115

BC17

CLK_REQ2_L/AGPIO116

BB18

CLK_REQ3_L/SATA_IS1_L/SATA_ZP1_L/EGPIO131

BB16

CLK_REQG_L/OSCIN/EGPIO132

AH9

USB_OC0_L/TRST_L/AGPIO16

AG1

USB_OC1_L/TDI/AGPIO17

AH2

USB_OC2_L/TCK/AGPIO18

AL9

USB_OC3_L/TDO/AGPIO24

AU6

AZ_BITCLK/I2S_BCLK_MIC

AR8

AZ_SDIN0/I2S_DATA_MIC[ 0]

AP6

AZ_SDIN1/I2S_LR_PLAYBACK

AR5

AZ_SDIN2/I2S_DATA_MIC[ 1]

AU9

AZ_RST_L/I2S_LR_MIC

AT9

AZ_SYNC/I2S_BCLK_PLAYBACK

AR7

AZ_SDOUT/I2S_DATA_PLAYBACK

BB10

I2C0_SCL/EGPIO145

BB9

I2C0_SDA/EGPIO146

BB7

I2C1_SCL/EGPIO147

BC7

I2C1_SDA/EGPIO148

AG7

RTCCLK

AT1

X32K_X1

AT2

X32K_X2

EMC@

RP13

1 8
2 7
3 6
4 5

33_0804_8P4R_5%

T1@

RP68

1K_0804_8P4R_5%

12

12

R348

4.7K_0402_5%

2

2

C1000

0.22U_0402_16V7K

1

1

B

ACPI/SD/AZ/GPIO/RTC/I2C/UART/MISC

HDA_BITCLK
HDA_SDOUT
HDA_SYNC
HDA_RST#

18
27
36
45

C

SD0_WP/EGPIO101

SD0_PWR_CTRL/AGPIO102

SD0_CLK/EGPIO95

SD0_CMD/EGPIO96

SD0_DATA0/EGPIO97

SD0_DATA1/EGPIO98

SD0_DATA2/EGPIO99

SD0_DATA3/EGPIO100

SD0_LED/EGPIO93

SCL0/I2C2_SCL/EGPIO113

SDA0/I2C2_SDA/EGPIO114

SCL1/I2C3_SCL/AGPIO19

SDA1/I2C3_SDA/AGPIO20

AGPIO6/LDT_RST

AGPIO7/LDT_PWROK

VDDGFX_PD/AGPIO39

AGPIO66/SHUTDOWN_L

AGPIO68/SGPIO_CLK

AGPIO69/SGPIO_LOAD

AGPIO71/SGPIO_DATAOUT

AGPIO72/SGPIO_DATAIN

BLINK/USB_OC7_L/AGPIO11

GENINT1_L/AGPIO89

GENINT2_L/AGPIO90

FANOUT0/AGPIO85

UART0_CTS_L/EGPIO135

UART0_RXD/EGPIO136

UART0_RTS_L/EGPIO137

UART0_TXD/EGPIO138

UART0_INTR/AGPIO139

UART1_CTS_L/BT_I2S_BCLK/EGPIO140

UART1_RXD/BT_I2S_SDI/EGPIO141

UART1_RTS_L/EGPIO142

UART1_TXD/BT_I2S_SDO/EGPIO143

FP4 REV 0.93

FP4_BGA968

UART1_INTR/BT_I2S_LRCLK/AGPIO144

H

L

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGIN EERING DRAWING IS THE PROPRI ETARY PRO PERTY OF C OMPAL ELE CTRONI CS, INC . A ND CONTAI NS CONFIDENTIAL

THIS SHEET OF ENGIN EERING DRAWING IS THE PROPRI ETARY PRO PERTY OF C OMPAL ELE CTRONI CS, INC . A ND CONTAI NS CONFIDENTIAL

THIS SHEET OF ENGIN EERING DRAWING IS THE PROPRI ETARY PRO PERTY OF C OMPAL ELE CTRONI CS, INC . A ND CONTAI NS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

BB2
BB5
BC2

SD0_CD/AGPIO25

BB4
AY5

BC3
BA3
BC5
BA5

PE_GPIO1

AGPIO3

AGPIO4

AGPIO5

AGPIO8

AGPIO9

AGPIO40

AGPIO64

AGPIO65

SPKR/AGPIO91

FANIN0/AGPIO84

BB6

APU_SMB_CLK0

BA15

APU_SMB_DATA0

AY17

APU_I2C3_SCL

AG5

APU_I2C3_SDA

AG4

AL5

AGPIO3

AL6
AJ1

AGPIO5

AJ3
AH1

AGPIO7

AJ4

AGPIO8

AK5
AD8

VDDGFX_PWRGD

AG8
AW15
AU15

G_INT#_APU

AT15
AU12
AT14

AGPIO69
PE_GPIO0

AR14
BC13

APU_SPKR

BA17

AN5

AGPIO11

BB14

HVB
TP_I2C_INT#_APU

BA19

BC18
BB19

AY9
AW8
AV5
AV8
AW9

AV11
AU7
AT11
AR11
AP9

PE_GPIO1 <25>

APU_SMB_CLK0 <13,14>
APU_SMB_DATA0 <13,14>

APU_I2C3_SCL <33>
APU_I2C3_SDA <33>

AGPIO8 <30>

VDDGFX_PWRGD <45>

G_INT#_APU <30>

PE_GPIO0 <15>

APU_SPKR <34>

TP_I2C_INT#_APU <33>

LPC_FRAME#LPC_CLK0_EC LPC_CLK1

BOOT FAIL
TIMER
ENABLED

BOOT FAIL
TIMER
DISABLED
(DEFAULT)

LPC_FRAME#<10,24,33>
LPC_CLK0_EC<10,24>
LPC_CLK1<10,33>

2017/04/18 2019/04/18

2017/04/18 2019/04/18

2017/04/18 2019/04/18

C

CLKGEN
ENABLE
(DEFAULT)

CLKGEN
DISABLED

+3VS

12

R902
10K_0402_5%

AGPIO3
RTC_CLK

SYS_RST#
AGPIO11

12

@

R903
2K_0402_5%

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

SPI ROM
(DEFAULT)

LPC ROM

12

12

@

R904
10K_0402_5%

R926
2K_0402_5%

MEM_VOLT_SEL/AGPIO3
<INT PU>

CZL CZ

1.8V SPI ROM

3.3V SPI ROM
(Default)

12

12

D

If no use, need Config Low

H

L

ENHANCED
RESET
(DEFAULT)

TRADITION
RESET

+3VALW

R925
10K_0402_5%

@

R927
2K_0402_5%

D

12

R928
10K_0402_5%

12

@

R929
2K_0402_5%

E

T1@

10K_0402_5%

10K_0402_5%

VX

EASR

1 2

T3@

1 2

R3953

10K_0402_5%

R3952

10K_0402_5%

VX@

1 2

EA@

1 2

R3978

R936

UMA

DIS

R4002

UMA@

10K_0402_5%

SD028100280

AGPIO5

RX550xRX560

RX540

RX550@

RX560@

AGPIO5
AGPIO7
AGPIO10
AGPIO12
AGPIO69

R4001

10K_0402_5%

R4002

10K_0402_5%

1 2

RX540@

1 2

R3999

10K_0402_5%

R4000

10K_0402_5%

R3892

1 2

@

R2624

1 2

AGPIO7 AGPIO10 AGPI O12 AGPIO69

BR

32.768KMHz CRYSTAL

32K_X1

12

32.768KHZ_12.5PF_Q13FC135000040

12

R914
20M_0402_5%

1

C686
18P_0402_50V8J

2

RTC_CLK
<INT PU>

COIN BATT
ON BOARD
(DEFAULT)

COIN BATT
NOT ON
BOARD

12

12

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

BLINK/AGPIO11
<INT PU>

LDT_RST#/PG
OUTPUT TO
APU
(DEFAULT)

OUTPUT
TO PADS

12

R949
10K_0402_5%

@

R2619
2K_0402_5%

C5V08/D5PR8_LA-E903PR1A

C5V08/D5PR8_LA-E903PR1A

C5V08/D5PR8_LA-E903PR1A

R951
10K_0402_5%

12

@

R2620
2K_0402_5%

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

FP4 GPIO/AZ/MISC/STRAPS

FP4 GPIO/AZ/MISC/STRAPS

FP4 GPIO/AZ/MISC/STRAPS

Y3

1

C682
22P_0402_50V8J

2

SYS_RST#
<INT PU>

NORMAL
RESET MODE
(DEFAULT)

SHORT RST
MODE

12

R954
10K_0402_5%

12

@

R2621
2K_0402_5%

E

32K_X2

950Tuesday, May 02, 2017

950Tuesday, May 02, 2017

950Tuesday, May 02, 2017

+3VALW

UMA@

10K_0402_5%

1 2

DIS@

10K_0402_5%

1 2

1.A

1.A

1.A

A

SATA_ATX_DRX_P0<30>

1 1

HDD

SSD

12

12

12

DEVSLP0

DEVSLP1

AGPIO130

R3852 1 0K_0402_5%

R3853 1 0K_0402_5%

R3882 1 0K_0402_5%

SATA_ATX_DRX_N0<30>

SATA_ARX_DTX_N0<30>
SATA_ARX_DTX_P0<30>

SATA_ATX_DRX_P1<30>
SATA_ATX_DRX_N1<30>

SATA_ARX_DTX_N1<30>
SATA_ARX_DTX_P1<30>

R90 1K_0402_1%
R96 1K_0402_1%

+0.95VS

DEVSLP1<30>

+3VS

12

CLKRUN#

@

R3872 1 0K_0402_5%

+3VALW

12

R3873 1 0K_0402_5%

2 2

+1.8VS

R634 10K_0402_5%

R635 10K_0402_5%

R636 10K_0402_5%

R637 10K_0402_5%

R638 10K_0402_5%

3 3

LPCPD#

APU_SPI_HOLD#

12

APU_SPI_WP#

12

APU_SPI_CS1#

12

APU_SPI_CS2#

12

APU_SPI_TPMCS#

12

VGA

LAN+CR

WLAN

PCIE_SSD

CLK_PEG_VGA<15>
CLK_PEG_VGA#<15>

CLK_PCIE_LAN<28>
CLK_PCIE_LAN#<28>

CLK_PCIE_WLAN<29>
CLK_PCIE_WLAN#<29>

CLK_PCIE_SSD<30>
CLK_PCIE_SSD#<30>

LPC_CLK0_EC<9,24>
LPC_CLK1<9,33>

LPC_AD0<24,33>
LPC_AD1<24,33>
LPC_AD2<24,33>
LPC_AD3<24,33>

LPC_FRAME#<9,24,33>

SERIRQ<24,33>
CLKRUN#<33>

APU_SPI_CLK APU_SPI_CLK_R

1 2

RS@

R106
0_0402_5%

8MB SPI ROM

12
12

1 2

R107 0_0402_5%RS@

1 2

R108 0_0402_5%RS@

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#

SERIRQ
CLKRUN#
LPCPD#

APU_SPI_CS1#
APU_SPI_CS2#
APU_SPI_MISO
APU_SPI_MOSI
APU_SPI_WP#
APU_SPI_HOLD#
APU_SPI_TPMCS#

B

SATA_ATX_DRX_P0
SATA_ATX_DRX_N0

SATA_ARX_DTX_N0
SATA_ARX_DTX_P0

SATA_ATX_DRX_P1
SATA_ATX_DRX_N1

SATA_ARX_DTX_N1
SATA_ARX_DTX_P1

SATA_ZVSS
SATA_ZVDD

DEVSLP0
DEVSLP1
AGPIO130

CLK_PEG_VGA
CLK_PEG_VGA#

CLK_PCIE_LAN
CLK_PCIE_LAN#

CLK_PCIE_WLAN
CLK_PCIE_WLAN#

CLK_PCIE_SSD
CLK_PCIE_SSD#

48M_X1

48M_X2

UAPU1E

AU3

SATA_TX0P

AU4

SATA_TX0N

AV1

SATA_RX0N

AV2

SATA_RX0P

AY2

SATA_TX1P

AY1

SATA_TX1N

AW4

SATA_RX1N

AW3

SATA_RX1P

AW1

SATA_ZVSS

AW2

SATA_ZVDDP

AT17

DEVSLP[0]/EGPIO67

AT12

DEVSLP[1]/EGPIO70

BB15

SATA_ACT_L/AGPIO130

AU2

SATA_X1

AU1

SATA_X2

U4

GFX_CLKP

U3

GFX_CLKN

U1

GPP_CLK0P

U2

GPP_CLK0N

W4

GPP_CLK1P

W3

GPP_CLK1N

W1

GPP_CLK2P

W2

GPP_CLK2N

Y2

GPP_CLK3P

Y1

GPP_CLK3N

BC10

X25M_48M_OSC

T2

X48M_X1

T1

X48M_X2

AW14

LPCCLK0/EGPIO74

AY13

LPCCLK1/EGPIO75

BB11

LAD0

BA11

LAD1

AY11

LAD2

BA13

LAD3

AV14

LFRAME_L

BA1

ESPI_ALERT_L/LDRQ0_L

BC14

SERIRQ/AGPIO87

BC11

LPC_CLKRUN_L/AGPIO88

AE9

LPC_PD_L/AGPIO21

BC6

SPI_CLK/ESPI_CLK/EGPIO117

BB8

SPI_CS1_L/EGPIO118

AW7

SPI_CS2_L/ESPI_CS_L/EGPIO119

BA9

SPI_DI/ESPI_DATA/EGPIO120

AY7

SPI_DO/EGPIO121

AW11

SPI_WP_L/EGPIO122

BA7

SPI_HOLD_L/EGPIO133

AW12

SPI_TPM_CS_L/AGPIO76

C

@

CLK/SATA/USB/SPI/LPC

FP4 REV 0.93

FP4_BGA968

USBCLK/25M_48M_OSC

USB_ZVSS

USB_HSD0P

USB_HSD0N

USB_HSD1P

USB_HSD1N

USB_HSD2P

USB_HSD2N

USB_HSD3P

USB_HSD3N

USB_HSD4P

USB_HSD4N

USB_HSD5P

USB_HSD5N

USB_HSD6P

USB_HSD6N

USB_HSD7P

USB_HSD7N

USB_SS_ZVSS

USB_SS_ZVDDP

USB_SS_0TXP

USB_SS_0TXN

USB_SS_0RXP

USB_SS_0RXN

USB_SS_1TXP

USB_SS_1TXN

USB_SS_1RXP

USB_SS_1RXN

USB_SS_2TXP

USB_SS_2TXN

USB_SS_2RXP

USB_SS_2RXN

USB_SS_3TXP

USB_SS_3TXN

USB_SS_3RXP

USB_SS_3RXN

AP8

AP5

AR2
AR1

AR3
AR4

AN2
AN1

AN3
AN4

AM1
AM2

AL2
AL1

AL3
AL4

AK2
AJ2

AD2
AD1

AA3
AA4

W9
W8

AA2
AA1

W5
W6

AC1
AC2

Y6
Y7

AC4
AC3

AB5
AB6

USB_ZVSS

USB20_P0
USB20_N0

USB20_P1
USB20_N1

USB20_P2
USB20_N2

USB20_P3
USB20_N3

USB20_P5
USB20_N5

USB20_P7
USB20_N7

USBSS_ZVSS
USBSS_ZVDD

1 2

R641 11.8K_0402_1%

USB20_P0 <31>
USB20_N0 <31>

USB20_P1 <31>
USB20_N1 <31>

USB20_P2 <29>
USB20_N2 <29>

USB20_P3 <27>
USB20_N3 <27>

USB20_P5 <32>
USB20_N5 <32>

USB20_P7 <31>
USB20_N7 <31>

1 2

R644 1K_0402_1%

1 2

R645 1K_0402_1%

USB3_ATX_DRX_P1 <32>
USB3_ATX_DRX_N1 <32>

USB3_ARX_DTX_P1 <32>
USB3_ARX_DTX_N1 <32>

USB3_ATX_DRX_P2 <32>
USB3_ATX_DRX_N2 <32>

USB3_ARX_DTX_P2 <32>
USB3_ARX_DTX_N2 <32>

USB3_ATX_DRX_P3 <31>
USB3_ATX_DRX_N3 <31>

USB3_ARX_DTX_P3 <31>
USB3_ARX_DTX_N3 <31>

D

S/B USB2.0 Conn.

S/B USB2.0 Conn.

WLAN/BT combo

Camera

Type -C Conn. (U3 p ort 1,2)

M/B USB3.0 Conn. (U3 port 3)

+0.95VALW

Type -C Con n.

Type -C Con n.

M/B USB3.0 Conn.

48MHz CRYSTAL

1 2

R938

1M_0402_5%

2

2

3

3

1

C794

2

4.7P_0402_50V8C

1

1

Y1
48MHZ_8PF_X3S048000D81H-W

Part Number = SJ10000AF00

4

4

1

C795

4.7P_0402_50V8C

2

E

R3980
0_0402_5%

1 2

1 2

R3981
0_0402_5%

48M_X2

48M_X1

+1.8VS

APU_SPI_CS1#
APU_SPI_MISO
APU_SPI_WP#

4 4

U56

1

CS#

2

DO(IO1)

HOLD#(IO3)

3

WP#(IO2)

4

GND

W25Q64FWSSIQ_SOIC_8P

APU_SPI_CLK

1 2

R617
10_0402_1%

DI(IO0)

@EMC@

8

VCC

7
6

CLK

5

1 2

C636
10P_0402_50V8J

APU_SPI_HOLD#
APU_SPI_CLK
APU_SPI_MOSI

@EMC@

12

@

C635 0.1U_0201_10V6K

Security Classification

Security Classification

Security Classification

2017/04/18 2019/04/18

2017/04/18 2019/04/18

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGIN EERING DRAWING IS THE PROPRI ETARY PRO PERTY OF C OMPAL ELE CTRONI CS, INC . A ND CONTAI NS CONFIDENTIAL

THIS SHEET OF ENGIN EERING DRAWING IS THE PROPRI ETARY PRO PERTY OF C OMPAL ELE CTRONI CS, INC . A ND CONTAI NS CONFIDENTIAL

THIS SHEET OF ENGIN EERING DRAWING IS THE PROPRI ETARY PRO PERTY OF C OMPAL ELE CTRONI CS, INC . A ND CONTAI NS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

2017/04/18 2019/04/18

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

FP4 SATA/CLK/USB/SPI

FP4 SATA/CLK/USB/SPI

FP4 SATA/CLK/USB/SPI

C5V08/D5PR8_LA-E903PR1A

C5V08/D5PR8_LA-E903PR1A

C5V08/D5PR8_LA-E903PR1A

10 50Tuesday, May 02, 2017

10 50Tuesday, May 02, 2017

10 50Tuesday, May 02, 2017

E

1.A

1.A

1.A

A

C1008 22U_0603_6.3V6M

1

2

1 1

C1126 0.22U_0402_16V7K

C1124 10U_0603_6.3V6M

1

2 2

2

C1109 10U_0603_6.3V6M

C1108 10U_0603_6.3V6M

1

2

3 3

C1118 10U_0603_6.3V6M

1

2

C1060 22U_0603_6.3V6M

C1059 22U_0603_6.3V6M

C1058 22U_0603_6.3V6M

C1057 22U_0603_6.3V6M

1

1

2

2

C1062 22U_0603_6.3V6M

C1061 22U_0603_6.3V6M

1

1

1

1

2

2

2

2

+3VALW

1

C1066 22U_0603_6.3V6M

C1063 22U_0603_6.3V6M

C1065 22U_0603_6.3V6M

C1064 22U_0603_6.3V6M

1

1

1

1

2

2

2

2

@

@

@

1 2

RS@

R119
0_0402_5%

2

+APU_CORE_FCH

C1110 0.22U_0402_16V7K

1

1

2

2

+0.95VALW

C1119 0.22U_0402_16V7K

1

2

C1085 10U_0603_6.3V6M

1

2

C1080 10U_0603_6.3V6M

C949 10U_0603_6.3V6M

C950 10U_0603_6.3V6M

1

1

1

2

2

2

For VDDP_S5

1 2

T1@

R3880
0_0603_5%

4 4

C2700 0.22U_0402_16V7K

C2699 10U_0603_6.3V6M

1

2

T1DIS@

1

2

T1DIS@

BR+DIS need pop

+0.95VS_GFX+0.95VS

C1087 0.22U_0402_16V7K

C1090 0.22U_0402_16V7K

C1089 0.22U_0402_16V7K

C1088 0.22U_0402_16V7K

1

1

1

1

2

2

2

2

C1114 0.22U_0402_16V7K

C1111 0.22U_0402_16V7K

C1113 0.22U_0402_16V7K

C1112 0.22U_0402_16V7K

1

1

1

1

2

2

2

2

+3VS_APU+3VS

C1137 10U_0603_6.3V6M

1

2

+1.8VALW +1.8VS

C1086 0.22U_0402_16V7K

1

2

C1099 0.22U_0402_16V7K

C1083 10U_0603_6.3V6M

1

2

C2691 0.22U_0402_16V7K

C2690 0.22U_0402_16V7K

1

1

1

2

2

2

For VDDP

0.22U_0402_16V7K

For VDDP_GFX

A

B

C1092 0.22U_0402_16V7K

C1093 180P_0402_50V8J

C1091 0.22U_0402_16V7K

1

1

1

2

2

2

Under APU

C1115 180P_0402_50V8J

+1.2V

C1116 180P_0402_50V8J

1

1

2

2

DIMMS/GND

C1102 0.22U_0402_16V7K

C1101 10U_0603_6.3V6M

1

1

2

2

C2693 0.22U_0402_16V7K

C2694 0.22U_0402_16V7K

C2692 0.22U_0402_16V7K

1

1

1

2

2

2

RTC OF APU

+RTC_APU_R

1

1U_0402_6.3V6K

2

B

C923

C166

+1.2V

For Audio
Near to AR19

C1005 1U_0402_6.3V6K

1

2

C245 180P_0402_50V8J

1

2

W=20mil s

2

1

C

@

C1006 1U_0402_6.3V6K

C1007 1U_0402_6.3V6K

1

1

2

2

+0.95VS

1 2

R93 1K_0402_5%

12

CLRP1

@

0_0603_5%

+1.8VS

+1.2V

+1.8VS

+0.95VS_GFX

+3VS_APU

+1.8VS

+1.8VALW

+3VALW

+0.95VALW

+APU_CORE_FCH

0.2A/0.9A

+0.95VS

+APU_CORE_NB

+RTC_APU_R

Need OPEN

+RTC_APU

3A

0.2A

1.5A

0.2A

1.5A

0.5A

0.2A

0.8A

7A

17A

+RTC_APU_R

0.1U_0201_10V6K

AB24
AB27
AB30
AB33
AD25
AD28
AD30
AE24
AE27

AF30

AF33
AG25
AG28
AH24
AH27
AH30
AK25
AK28
AK30
AK33

AL27
AM30

AR19

AP19
AP21

AP16
AP18

AP10

AP15
AR15

AN12
AP12

AP13
AR12

AW19

AU17
AU19
AV17
AV19

AW17

AL12

AL13

AL15

AL18

AL21
AN13
AN16
AN19
AN22

AR17

+RTC_APU

C106

P25
P28

U25
U28
V30

V33
W24
W27

Y25

Y28

Y30

AE6

AE5

AR9

T24
T27

1

2

UAPU1F

VDDIO_MEM_S3_1

VDDIO_MEM_S3_2

VDDIO_MEM_S3_3

VDDIO_MEM_S3_4

VDDIO_MEM_S3_5

VDDIO_MEM_S3_6

VDDIO_MEM_S3_7

VDDIO_MEM_S3_8

VDDIO_MEM_S3_9

VDDIO_MEM_S3_10

VDDIO_MEM_S3_11

VDDIO_MEM_S3_12

VDDIO_MEM_S3_13

VDDIO_MEM_S3_14

VDDIO_MEM_S3_15

VDDIO_MEM_S3_16

VDDIO_MEM_S3_17

VDDIO_MEM_S3_18

VDDIO_MEM_S3_19

VDDIO_MEM_S3_20

VDDIO_MEM_S3_21

VDDIO_MEM_S3_22

VDDIO_MEM_S3_23

VDDIO_MEM_S3_24

VDDIO_MEM_S3_25

VDDIO_MEM_S3_26

VDDIO_MEM_S3_27

VDDIO_MEM_S3_28

VDDIO_MEM_S3_29

VDDIO_MEM_S3_30

VDDIO_MEM_S3_31

VDDIO_MEM_S3_32

VDDIO_MEM_S3_33

VDDIO_MEM_S3_34

VDDIO_MEM_S3_35

VDDIO_AUDIO

VDDP_GFX_2

VDDP_GFX_1

VDD_33_1

VDD_33_2

VDD_18_1

VDD_18_2

VDD_18_S5_1

VDD_18_S5_2

VDD_33_S5_1

VDD_33_S5_2

VDDP_S5_1

VDDP_S5_2

VDDCR_FCH_S5_1

VDDCR_FCH_S5_2

VDDP_6

VDDP_1

VDDP_2

VDDP_3

VDDP_4

VDDP_5

VDDCR_NB_1

VDDCR_NB_2

VDDCR_NB_3

VDDCR_NB_4

VDDCR_NB_5

VDDCR_NB_6

VDDCR_NB_7

VDDCR_NB_8

VDDCR_NB_9

VDDBT_RTC_G

AP2138N-1.5TRG1_SOT23-3

FP4 REV 0.93

FP4_BGA968

Vo=1.5V

3

Vout

2

GND

POWER

U102

Vin

680P_0603_50V8J

1

for Clear CMOS

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRO NICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRO NICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRO NICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHO RIZED BY COMPAL ELECT RONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHO RIZED BY COMPAL ELECT RONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHO RIZED BY COMPAL ELECT RONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE US ED BY OR D ISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE US ED BY OR D ISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE US ED BY OR D ISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2017/04/18 2019/04/18

2017/04/18 2019/04/18

2017/04/18 2019/04/18

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Dat e

Deciphered Dat e

Deciphered Dat e

VDDCR_CPU_1

VDDCR_CPU_2

VDDCR_CPU_3

VDDCR_CPU_4

VDDCR_CPU_5

VDDCR_CPU_6

VDDCR_CPU_7

VDDCR_CPU_8

VDDCR_CPU_9

VDDCR_CPU_10

VDDCR_CPU_11

VDDCR_CPU_12

VDDCR_CPU_13

VDDCR_CPU_14

VDDCR_CPU_15

VDDCR_CPU_16

VDDCR_CPU_17

VDDCR_CPU_18

VDDCR_CPU_19

VDDCR_CPU_20

VDDCR_CPU_21

VDDCR_CPU_22

VDDCR_CPU_23

VDDCR_CPU_24

VDDCR_CPU_25

VDDCR_CPU_26

VDDCR_CPU_42

VDDCR_CPU_31

VDDCR_CPU_43

VDDCR_CPU_32

VDDCR_CPU_44

VDDCR_CPU_33

VDDCR_CPU_45

VDDCR_CPU_34

VDDCR_CPU_46

VDDCR_CPU_35

VDDCR_CPU_47

VDDCR_CPU_36

VDDCR_CPU_28

VDDCR_CPU_29

VDDCR_CPU_40

VDDCR_CPU_30

VDDCR_CPU_37

VDDCR_CPU_49

VDDCR_CPU_38

VDDCR_CPU_39

VDDCR_CPU_48

VDDCR_CPU_41

VDDCR_CPU_27

VDDCR_GFX_14

VDDCR_GFX_15

VDDCR_GFX_16

VDDCR_GFX_17

VDDCR_GFX_18

VDDCR_GFX_19

VDDCR_GFX_20

VDDCR_GFX_21

VDDCR_GFX_22

VDDCR_GFX_23

VDDCR_GFX_24

VDDCR_GFX_25

VDDCR_GFX_26

VDDCR_GFX_27

VDDCR_GFX_28

VDDCR_GFX_29

VDDCR_GFX_1

VDDCR_GFX_2

VDDCR_GFX_3

VDDCR_GFX_4

VDDCR_GFX_5

VDDCR_GFX_6

VDDCR_GFX_7

VDDCR_GFX_8

VDDCR_GFX_9

VDDCR_GFX_10

VDDCR_GFX_11

VDDCR_GFX_12

VDDCR_GFX_30

VDDCR_GFX_31

VDDCR_GFX_32

VDDCR_GFX_33

VDDCR_GFX_34

VDDCR_GFX_35

VDDCR_GFX_36

VDDCR_GFX_37

VDDCR_GFX_13

+RTCVCC

C105

D

U8
W7
W12
W15
W18
W21
Y8
Y10
Y13
Y16
Y19
Y22
AB7
AB9
AB12
AB15
AB18
AB21
AD6
AD10
AD13
AD16
AD19
AD22
AE7
AE12
AK9
AG10
AK10
AG13
AK13
AG16
AK16
AG19
AK19
AG22
AK22
AH7
AE18
AE21
AH21
AG6
AH12
AN6
AH15
AH18
AL7
AK6
AE15

L8
L13
L16
L19
L22
N7
N12
N15
N18
N21
P8
P13
P16
P19
P22
T7
F12
F15
G11
G14
J8
J9
J11
K7
K12
K13
K15
K16
T12
T15
T18
T21
U13
U16
U19
U22
K19

1

2

D

+APU_CORE

35A

+APU_GFX

35A

+RTCBATT

+RTCBATT

R4003

D103

1 2

3

1

1K_0402_5%

2

CHN202UPT_SC70-3

SC600000B00

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

+CHGRTC

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

FP4 PWR

FP4 PWR

FP4 PWR

Custom

Custom

Custom

C5V08/D5PR8_LA-E903PR1A

C5V08/D5PR8_LA-E903PR1A

C5V08/D5PR8_LA-E903PR1A

1
2

3
4

E

JRTC1

1
2

GND
GND

ACES_50271-0020N-001

CONN@

SP02000RO00

11 50Tuesday, May 02, 2017

11 50Tuesday, May 02, 2017

11 50Tuesday, May 02, 2017

E

1.A

1.A

1.A

A

B

C

D

E

@

UAPU1G

A8

RS@

ORIENT_APU#

1 2

R157
0_0402_5%

1 1

2 2

3 3

A12
A16
A20
A24
A28
A32

B12
B33

D10
D12
D14
D16
D18
D20
D22
D24
D26
D28
D30

F19
F22
F25
F30
F33

G17
G20
G23
G26

H30

J15
J19
J22
J25
J28

K10
K22
K27
K30
K33

L12
L15
L18
L21
L25

VSS_1

VSS_2

VSS_3

VSS_4

VSS_5

VSS_6

VSS_7

B2

VSS_8

B8

VSS_9

VSS_10

VSS_11

C3

VSS_12

D4

VSS_13

D6

VSS_14

D8

VSS_15

VSS_16

VSS_17

VSS_18

VSS_19

VSS_20

VSS_21

VSS_22

VSS_23

VSS_24

VSS_25

VSS_26

F1

VSS_27

F2

VSS_28

F4

VSS_29

F9

VSS_30

VSS_31

VSS_32

VSS_33

VSS_34

VSS_35

G7

VSS_36

VSS_37

VSS_38

VSS_39

VSS_40

H4

VSS_41

VSS_42

J5

VSS_43

VSS_44

VSS_45

VSS_46

VSS_47

VSS_48

K1

VSS_49

K2

VSS_50

K4

VSS_51

VSS_52

VSS_53

VSS_54

VSS_55

VSS_56

L5

VSS_57

VSS_58

VSS_59

VSS_60

VSS_61

VSS_62

GND

FP4 REV 0.93

FP4_BGA968

VSS_63

VSS_64

VSS_65

VSS_66

VSS_67

VSS_68

VSS_69

VSS_70

VSS_71

VSS_72

VSS_73

VSS_74

VSS_75

VSS_76

VSS_77

VSS_78

VSS_79

VSS_80

VSS_81

VSS_82

VSS_83

VSS_84

VSS_85

VSS_86

VSS_87

VSS_88

VSS_89

VSS_90

VSS_91

VSS_92

VSS_93

VSS_94

VSS_95

VSS_96

VSS_97

VSS_98

VSS_99

VSS_100

VSS_101

VSS_102

VSS_103

VSS_104

VSS_105

VSS_106

VSS_107

VSS_108

VSS_109

VSS_110

VSS_111

VSS_112

VSS_113

VSS_114

VSS_115

VSS_116

VSS_117

VSS_118

VSS_119

VSS_120

VSS_121

VSS_122

VSS_123

VSS_124

L28
M4
M30
N10
N13
N16
N19
N22
N27
P1
P2
P4
P5
P12
P15
P18
P21
P30
P33
T4
T10
T13
T16
T19
T22
T30
U5
U12
U15
U18
U21
U24
V1
V2
V4
W10
W13
W16
W19
W22
Y4
Y5
Y12
Y15
Y18
Y21
Y24
AB1
AB2
AB4
AB10
AB13
AB16
AB19
AB22
AD4
AD9
AD12
AD15
AD18
AD21
AD24

AE10
AE13
AE16
AE19
AE22

AF1
AF4

AG9
AG12
AG15
AG18
AG21

AH4
AH10
AH13
AH16
AH19
AH22

AK1

AK4
AK12
AK15
AK18

AL16
AL19
AL22

AM4

AN9
AN10
AN15
AN18
AN21
AN25
AN28

AP1

AP2

AP4

AP7
AP22
AP27
AP30
AP33

AR6
AR25
AR28

AT4
AT19
AT22
AT30

AU5

AU8
AU11
AU14
AU20
AU23
AU27

AV4

AV7

AV9

AV12
AV15
AV25

UAPU1H

VSS_125

VSS_126

VSS_127

VSS_128

VSS_129

VSS_130

VSS_131

VSS_132

VSS_133

VSS_134

VSS_135

VSS_136

VSS_137

VSS_138

VSS_139

VSS_140

VSS_141

VSS_142

VSS_143

VSS_144

VSS_145

VSS_146

VSS_147

VSS_148

VSS_149

VSS_150

VSS_151

VSS_152

VSS_153

VSS_154

VSS_155

VSS_156

VSS_157

VSS_158

VSS_159

VSS_160

VSS_161

VSS_162

VSS_163

VSS_164

VSS_165

VSS_166

VSS_167

VSS_168

VSS_169

VSS_170

VSS_171

VSS_172

VSS_173

VSS_174

VSS_175

VSS_176

VSS_177

VSS_178

VSS_179

VSS_180

VSS_181

VSS_182

VSS_183

VSS_184

VSS_185

VSS_186

@

GND

FP4 REV 0.93

FP4_BGA968

VSS_187

VSS_188

VSS_189

VSS_190

VSS_191

VSS_192

VSS_193

VSS_194

VSS_195

VSS_196

VSS_197

VSS_198

VSS_199

VSS_200

VSS_201

VSS_202

VSS_203

VSS_204

VSS_205

VSS_206

VSS_207

VSS_208

VSS_209

VSS_210

VSS_211

VSS_212

VSS_213

VSS_215

VSS_214

AV30
AV33
AW22
AY4
AY6
AY8
AY10
AY12
AY14
AY16
AY20
AY22
AY24
AY26
AY28
AY30
BB1
BB33
BC4
BC8
BC12
BC16
BC20
BC24
BC28
BC32

L24
AL10
AK21

U30
U31

AN30

UAPU1J

RSVD_2

RSVD_3

RSVD_4

@

FP4 REV 0.93

FP4_BGA968

4 4

Security Classification

Security Classification

Security Classification

2017/04/18 2019/04/18

2017/04/18 2019/04/18

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETARY PR OPERTY O F COMPAL E LECTRO NICS, INC. AN D CONTAI NS CONFIDENTIAL

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETARY PR OPERTY O F COMPAL E LECTRO NICS, INC. AN D CONTAI NS CONFIDENTIAL

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETARY PR OPERTY O F COMPAL E LECTRO NICS, INC. AN D CONTAI NS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRIT TEN CONSENT OF COMPAL E LECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRIT TEN CONSENT OF COMPAL E LECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRIT TEN CONSENT OF COMPAL E LECTRONICS, INC.

A

2017/04/18 2019/04/18

B

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Titl e

Titl e

Titl e

Size

Size

Size

Document Number Rev

Document Number Rev

Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

C

Date: Sheet of

D

Compal Electronics, Inc.

FP4 GND

FP4 GND

FP4 GND

C5V08/D5PR8_LA-E903PR1A

C5V08/D5PR8_LA-E903PR1A

C5V08/D5PR8_LA-E903PR1A

12 50Tuesday, May 02, 2017

12 50Tuesday, May 02, 2017

12 50Tuesday, May 02, 2017

E

1.A

1.A

1.A

A

B

C

D

E

Reverse Type-4H

2-3A to 1 DIMMs/channel

DDRA_CLK0<7>
DDRA_CLK0#<7>
DDRA_CLK1<7>

Address : A0

1 1

+3VS

12

RD5

0_0402_5%

@

12

RD8

0_0402_5%

RS@

Layout Note:
Place near JDIMM1

2 2

+1.2V

1U_0402_6.3V6K

1

2

+1.2V

10U_0603_6.3V6M

1

2

3 3

+1.2V

0.1U_0201_10V6K

2

1

12

12

12

CD2

CD10

CD61

RD7

0_0402_5%

RD6

0_0402_5%

@

@

DDRA_SA2 DDRA_SBS1#
DDRA_SA1
DDRA_SA0

12

RD9

0_0402_5%

RS@

RD10

0_0402_5%

RS@

Note:
Check voltage tolerance of
VREF_DQ at the DIMM socket

CRB use 0.1uF x12 (6 pop,6 unpop),180pF x1,100uF x2

1U_0402_6.3V6K

1U_0402_6.3V6K

CD3

1

1

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

CD11

1

1

2D@

2

2

0.1U_0201_10V6K

0.1U_0201_10V6K

CD62

2

2

1

1

1U_0402_6.3V6K

1U_0402_6.3V6K

CD4

1

2

10U_0603_6.3V6M

CD12

1

2D@

2

0.1U_0201_10V6K

CD63

2

1

1U_0402_6.3V6K

CD6

CD5

CD13

2D@

CD64

CD7

1

1

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

CD14

CD15

1

1

2D@

2D@

2

2

180P_0402_50V8J

2

1

DDR4 support Even Parity check in DRAMs.

+1.2V

@EMC@

CD1 .1U_0402_16V7K

Follow MA51

1

@

+

CD18
330U_D2_2V_Y

2

SGA00009S00
330U 2V H1.9
9mohm POLY

CD65

DDRA_CLK1#<7>

DDRA_CKE0<7>
DDRA_CKE1<7>

DDRA_SCS0#<7>
DDRA_SCS1#<7>

DDRA_ODT0<7>
DDRA_ODT1<7>

DDRA_BG0<7>

DDRA_BG1<7>
DDRA_SBS0#<7>
DDRA_SBS1#<7>

DDRA_SMA[16..0]<7>

MEM_MA_ACT#<7>

1 2

RD225 0_0402_5%RS@
RD1 1K_0402_1%

12

12

MEM_MA_EVENT#<7>

MEM_MA_RST#<7>

APU_SM B_DATA0<9,14>
APU_SM B_CLK0<9,14>

DDRA_SDM[7..0]<7>

DDRA_CLK0
DDRA_CLK0#
DDRA_CLK1
DDRA_CLK1#

DDRA_CKE0
DDRA_CKE1

DDRA_SCS0#
DDRA_SCS1#

DDRA_ODT0
DDRA_ODT1

DDRA_BG0
DDRA_BG1
DDRA_SBS0#

DDRA_SMA0
DDRA_SMA1
DDRA_SMA2
DDRA_SMA3
DDRA_SMA4
DDRA_SMA5
DDRA_SMA6
DDRA_SMA7
DDRA_SMA8
DDRA_SMA9
DDRA_SMA10
DDRA_SMA11
DDRA_SMA12
DDRA_SMA13
DDRA_SMA14
DDRA_SMA15
DDRA_SMA16

MEM_MA_ACT#

DDRA_PARITY
DDRA_ALERT#
MEM_MA_EVENT#
MEM_MA_RST#

APU_SM B_DATA0
APU_SM B_CLK0

DDRA_SA2
DDRA_SA1
DDRA_SA0

DDRA_SDM0
DDRA_SDM1
DDRA_SDM2
DDRA_SDM3
DDRA_SDM4
DDRA_SDM5
DDRA_SDM6
DDRA_SDM7

JDIMM1A

REVERSE

137

CK0(T)

139

CK0#(C)

138

CK1(T)

140

CK1#(C)

109

CKE0

110

CKE1

149

S0#

157

S1#

162

S2#/C0

165

S3#/C1

155

ODT0

161

ODT1

115

BG0

113

BG1

150

BA0

145

BA1

144

A0

133

A1

132

A2

131

A3

128

A4

126

A5

127

A6

122

A7

125

A8

121

A9

146

A10_AP

120

A11

119

A12

158

A13

151

A14_WE#

156

A15_CAS#

152

A16_RAS#

114

ACT#

143

PARITY

116

ALERT#

134

EVENT#

108

RESET#

254

SDA

253

SCL

166

SA2

260

SA1

256

SA0

92

CB0_NC

91

CB1_NC

101

CB2_NC

105

CB3_NC

88

CB4_NC

87

CB5_NC

100

CB6_NC

104

CB7_NC

97

DQS8(T)

95

DQS8#(C)

12

DM0#/DBI0#

33

DM1#/DBI1#

54

DM2#/DBI2#

75

DM3#/DBI3#

178

DM4#/DBI4#

199

DM5#/DBI5#

220

DM6#/DBI6#

241

DM7#/DBI7#

96

DM8#/DBI8#

LOTES_ADDR0206-P001A

CONN@

DQS0(T)

DQS0#(C)

DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

DQS1(T)

DQS1#(C)

DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23

DQS2(T)

DQS2#(C)

DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

DQS3(T)

DQS3#(C)

DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39

DQS4(T)

DQS4#(C)

DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47

DQS5(T)

DQS5#(C)

DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55

DQS6(T)

DQS6#(C)

DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

DQS7(T)

DQS7#(C)

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQ8
DQ9

DDRA_SDQ1

7

DDRA_SDQ2

20

DDRA_SDQ3

21

DDRA_SDQ4

4

DDRA_SDQ5

3

DDRA_SDQ6

16

DDRA_SDQ7

17

DDRA_SDQS0

13

DDRA_SDQS0#

11

DDRA_SDQ8

28

DDRA_SDQ9

29

DDRA_SDQ10

41

DDRA_SDQ11

42

DDRA_SDQ12

24

DDRA_SDQ13

25

DDRA_SDQ14

38

DDRA_SDQ15

37

DDRA_SDQS1

34

DDRA_SDQS1#

32

DDRA_SDQ16

50

DDRA_SDQ17

49

DDRA_SDQ18

62

DDRA_SDQ19

63

DDRA_SDQ20

46

DDRA_SDQ21

45

DDRA_SDQ22

58

DDRA_SDQ23

59

DDRA_SDQS2

55

DDRA_SDQS2#

53

DDRA_SDQ24

70

DDRA_SDQ25

71

DDRA_SDQ26

83

DDRA_SDQ27

84

DDRA_SDQ28

66

DDRA_SDQ29

67

DDRA_SDQ30

79

DDRA_SDQ31

80

DDRA_SDQS3

76

DDRA_SDQS3#

74

DDRA_SDQ32

174

DDRA_SDQ33

173

DDRA_SDQ34

187

DDRA_SDQ35

186

DDRA_SDQ36

170

DDRA_SDQ37

169

DDRA_SDQ38

183

DDRA_SDQ39

182

DDRA_SDQS4

179

DDRA_SDQS4#

177

DDRA_SDQ40

195

DDRA_SDQ41

194

DDRA_SDQ42

207

DDRA_SDQ43

208

DDRA_SDQ44

191

DDRA_SDQ45

190

DDRA_SDQ46

203

DDRA_SDQ47

204

DDRA_SDQS5

200

DDRA_SDQS5#

198

DDRA_SDQ48

216

DDRA_SDQ49

215

DDRA_SDQ50

228

DDRA_SDQ51

229

DDRA_SDQ52

211

DDRA_SDQ53

212

DDRA_SDQ54

224

DDRA_SDQ55

225

DDRA_SDQS6

221

DDRA_SDQS6#

219

DDRA_SDQ56

237

DDRA_SDQ57

236

DDRA_SDQ58

249

DDRA_SDQ59

250

DDRA_SDQ60

232

DDRA_SDQ61

233

DDRA_SDQ62

245

DDRA_SDQ63

246

DDRA_SDQS7

242

DDRA_SDQS7#

240

DDRA_SDQ0

8

DDRA_SDQ[7..0] <7>

DDRA_SDQS0 <7>
DDRA_SDQS0# <7>
DDRA_SDQ[15..8] <7>

DDRA_SDQS1 <7>
DDRA_SDQS1# <7>
DDRA_SDQ[23..16] <7>

DDRA_SDQS2 <7>
DDRA_SDQS2# <7>
DDRA_SDQ[31..24] <7>

DDRA_SDQS3 <7>
DDRA_SDQS3# <7>
DDRA_SDQ[39..32] <7>

DDRA_SDQS4 <7>
DDRA_SDQS4# <7>
DDRA_SDQ[47..40] <7>

DDRA_SDQS5 <7>
DDRA_SDQS5# <7>
DDRA_SDQ[55..48] <7>

DDRA_SDQS6 <7>
DDRA_SDQS6# <7>

DDRA_SDQ[63..56] <7>

DDRA_SDQS7 <7>
DDRA_SDQS7# <7>

Follow CRB design

+1.2V

RD3

1K_0402_1%

RD4

1K_0402_1%

1 2

CD20 4.7U_0402_6.3V6M

1 2

15mil

1

2D@

2

+VREFA_CA

CD22 0.1U_0201_10V6K

CD21 0.1U_0201_10V6K

CD19 1000P_0402_50V7K

2

2

1

1

1

2

Place near to SO-DIMM connector.

+1.2V +1.2V

JDIMM1B

REVERSE

111

VDD1

112
117
118
123
124
129
130

+3VS

135
136

255

164

1
2
5
6

9
10
14
15
18
19
22
23
26
27
30
31
35
36
39
40
43
44
47
48
51
52
56
57
60
61
64
65
68
69
72
73
77
78
81
82
85
86
89
90
93
94
98

262

Layout Note:
Place near JDIMM1.258

VDD11

VDD2

VDD12

VDD3

VDD13

VDD4

VDD14

VDD5

VDD15

VDD6

VDD16

VDD7

VDD17

VDD8

VDD18

VDD9

VDD19

VDD10

VDDSPD

VREFCA

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

GND

LOTES_ADDR0206-P001A

CONN@

VPP1
VPP2

GND

VTT

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

141
142
147
148
153
154
159
160

+0.6VS

163

258

257
259

99
102
103
106
107
167
168
171
172
175
176
180
181
184
185
188
189
192
193
196
197
201
202
205
206
209
210
213
214
217
218
222
223
226
227
230
231
234
235
238
239
243
244
247
248
251
252

261

+2.5V

CD31 1U_0402_6.3V6K

1

2

CRB use 1uF x1

CRB use 4.7uF x1,0.1uF x1

Layout Note:
Place near JDIMM1.257,259

CRB use 0.1uF x2,180pF x1

4 4

10U_0603_6.3V6M

1

2

+2.5V

1U_0402_6.3V6K

10U_0603_6.3V6M

CD23

CD25

CD24

1

1

2D@

2

2

A

Layout Note:
Place near JDIMM1.255

CRB use 1uF x1

+3VS

1U_0402_6.3V6K

CD26

1

2

1

2

Security Classific ation

Security Classific ation

Security Classific ation

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PR OPERT Y OF C OMPAL EL ECTRO NICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PR OPERT Y OF C OMPAL EL ECTRO NICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PR OPERT Y OF C OMPAL EL ECTRO NICS, INC. AND CO NTAINS CONFIDENTIAL
AND T RADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D

AND T RADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D

AND T RADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISC LOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISC LOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISC LOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2017/04/18 2019/04/18

2017/04/18 2019/04/18

2017/04/18 2019/04/18

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

C5V08/D5PR8_LA-E903PR1A

C5V08/D5PR8_LA-E903PR1A

C5V08/D5PR8_LA-E903PR1A

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

+0.6VS

10U_0603_6.3V6M

10U_0603_6.3V6M

CD27

CD28

1

2D@

2D@

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

DDR4_SO-DIMM

DDR4_SO-DIMM

DDR4_SO-DIMM

1U_0402_6.3V6K

1U_0402_6.3V6K

CD30

CD29

1

1

2

2

13 50Tuesday, May 02, 2017

13 50Tuesday, May 02, 2017

E

13 50Tuesday, May 02, 2017

1.A

1.A

1.A

A

B

C

D

E

*Stoney Platform will use 4H on JDIMM2*
Need to confirm Footprint

Reverse Type-8H

2-3A to 1 DIMMs/channel

DDRB_CLK0<7>
DDRB_CLK0#<7>
DDRB_CLK1<7>

Address : A2

1 1

+3VS

RD244

12

RD247

0_0402_5%

@

12

RD252

0_0402_5%

RS@

Layout Note:
Place near JDIMM2

2 2

+1.2V

1U_0402_6.3V6K

CD86

1

2

+1.2V

10U_0603_6.3V6M

CD82

1

2

3 3

+1.2V

0.1U_0201_10V6K
CD91

2

1

10K_0402_5%

12

12

RD248

0_0402_5%

@

DDRB_SA2 DDRB_SBS1#
DDRB_SA1
DDRB_SA0

12

12

RD249

0_0402_5%

RD246

0_0402_5%

RS@

@

Note:
Check voltage tolerance of
VREF_DQ at the DIMM socket

CRB use 0.1uF x12 (6 pop,6 unpop),180pF x1,100uF x2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

2

10U_0603_6.3V6M

1

2

0.1U_0201_10V6K

2

1

1U_0402_6.3V6K

CD78

CD67

1

1

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

CD90

CD96

1

1

2

2

0.1U_0201_10V6K

0.1U_0201_10V6K

CD94

CD97

2

2

1

1

1U_0402_6.3V6K

1U_0402_6.3V6K

CD93

CD77

CD66

CD81

CD71

1

1

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

CD68

CD88

1

1

2

2

180P_0402_50V8J

CD85

2

1

DDR4 support Even Parity check in DRAMs.

+1.2V

@EMC@

CD73 .1U_0402_16V7K

DDRB_CLK1#<7>

DDRB_CKE0<7>
DDRB_CKE1<7>

DDRB_SCS0#<7>
DDRB_SCS1#<7>

DDRB_ODT0<7>
DDRB_ODT1<7>

DDRB_BG0<7>

DDRB_BG1<7>
DDRB_SBS0#<7>
DDRB_SBS1#<7>

DDRB_SMA[16..0]<7>

MEM_MB_ACT#<7>

1 2

RD250 0_0402_5%RS@
RD245 1K_0402_1%

12

12

MEM_MB_EVENT#<7>

MEM_MB_RST#<7>

APU_SM B_DATA0<9,13>
APU_SM B_CLK0<9,13>

DDRB_SDM[7..0]<7>

DDRB_CLK0
DDRB_CLK0#
DDRB_CLK1
DDRB_CLK1#

DDRB_CKE0
DDRB_CKE1

DDRB_SCS0#
DDRB_SCS1#

DDRB_ODT0
DDRB_ODT1

DDRB_BG0
DDRB_BG1
DDRB_SBS0#

DDRB_SMA0
DDRB_SMA1
DDRB_SMA2
DDRB_SMA3
DDRB_SMA4
DDRB_SMA5
DDRB_SMA6
DDRB_SMA7
DDRB_SMA8
DDRB_SMA9
DDRB_SMA10
DDRB_SMA11
DDRB_SMA12
DDRB_SMA13
DDRB_SMA14
DDRB_SMA15
DDRB_SMA16

MEM_MB_ACT#

DDRB_PARITY
DDRB_ALERT#
MEM_MB_EVENT#
MEM_MB_RST#

APU_SM B_DATA0
APU_SM B_CLK0

DDRB_SA2
DDRB_SA1
DDRB_SA0

DDRB_SDM0
DDRB_SDM1
DDRB_SDM2
DDRB_SDM3
DDRB_SDM4
DDRB_SDM5
DDRB_SDM6
DDRB_SDM7

JDIMM2A

RESERVE

137

CK0(T)

139

CK0#(C)

138

CK1(T)

140

CK1#(C)

109

CKE0

110

CKE1

149

S0#

157

S1#

162

S2#/C0

165

S3#/C1

155

ODT0

161

ODT1

115

BG0

113

BG1

150

BA0

145

BA1

144

A0

133

A1

132

A2

131

A3

128

A4

126

A5

127

A6

122

A7

125

A8

121

A9

146

A10_AP

120

A11

119

A12

158

A13

151

A14_WE#

156

A15_CAS#

152

A16_RAS#

114

ACT#

143

PARITY

116

ALERT#

134

EVENT#

108

RESET#

254

SDA

253

SCL

166

SA2

260

SA1

256

SA0

92

CB0_NC

91

CB1_NC

101

CB2_NC

105

CB3_NC

88

CB4_NC

87

CB5_NC

100

CB6_NC

104

CB7_NC

97

DQS8(T)

95

DQS8#(C)

12

DM0#/DBI0#

33

DM1#/DBI1#

54

DM2#/DBI2#

75

DM3#/DBI3#

178

DM4#/DBI4#

199

DM5#/DBI5#

220

DM6#/DBI6#

241

DM7#/DBI7#

96

DM8#/DBI8#

LOTES_ADDR0070-P009A

CONN@

DQS0(T)

DQS0#(C)

DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

DQS1(T)

DQS1#(C)

DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23

DQS2(T)

DQS2#(C)

DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

DQS3(T)

DQS3#(C)

DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39

DQS4(T)

DQS4#(C)

DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47

DQS5(T)

DQS5#(C)

DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55

DQS6(T)

DQS6#(C)

DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

DQS7(T)

DQS7#(C)

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQ8
DQ9

DDRB_SDQ0

8

DDRB_SDQ1

7

DDRB_SDQ2

20

DDRB_SDQ3

21

DDRB_SDQ4

4

DDRB_SDQ5

3

DDRB_SDQ6

16

DDRB_SDQ7

17

DDRB_SDQS0

13

DDRB_SDQS0#

11

DDRB_SDQ8

28

DDRB_SDQ9

29

DDRB_SDQ10

41

DDRB_SDQ11

42

DDRB_SDQ12

24

DDRB_SDQ13

25

DDRB_SDQ14

38

DDRB_SDQ15

37

DDRB_SDQS1

34

DDRB_SDQS1#

32

DDRB_SDQ16

50

DDRB_SDQ17

49

DDRB_SDQ18

62

DDRB_SDQ19

63

DDRB_SDQ20

46

DDRB_SDQ21

45

DDRB_SDQ22

58

DDRB_SDQ23

59

DDRB_SDQS2

55

DDRB_SDQS2#

53

DDRB_SDQ24

70

DDRB_SDQ25

71

DDRB_SDQ26

83

DDRB_SDQ27

84

DDRB_SDQ28

66

DDRB_SDQ29

67

DDRB_SDQ30

79

DDRB_SDQ31

80

DDRB_SDQS3

76

DDRB_SDQS3#

74

DDRB_SDQ32

174

DDRB_SDQ33

173

DDRB_SDQ34

187

DDRB_SDQ35

186

DDRB_SDQ36

170

DDRB_SDQ37

169

DDRB_SDQ38

183

DDRB_SDQ39

182

DDRB_SDQS4

179

DDRB_SDQS4#

177

DDRB_SDQ40

195

DDRB_SDQ41

194

DDRB_SDQ42

207

DDRB_SDQ43

208

DDRB_SDQ44

191

DDRB_SDQ45

190

DDRB_SDQ46

203

DDRB_SDQ47

204

DDRB_SDQS5

200

DDRB_SDQS5#

198

DDRB_SDQ48

216

DDRB_SDQ49

215

DDRB_SDQ50

228

DDRB_SDQ51

229

DDRB_SDQ52

211

DDRB_SDQ53

212

DDRB_SDQ54

224

DDRB_SDQ55

225

DDRB_SDQS6

221

DDRB_SDQS6#

219

DDRB_SDQ56

237

DDRB_SDQ57

236

DDRB_SDQ58

249

DDRB_SDQ59

250

DDRB_SDQ60

232

DDRB_SDQ61

233

DDRB_SDQ62

245

DDRB_SDQ63

246

DDRB_SDQS7

242

DDRB_SDQS7#

240

DDRB_SDQ[7..0] <7>

DDRB_SDQS0 <7>
DDRB_SDQS0# <7>
DDRB_SDQ[15..8] <7>

DDRB_SDQS1 <7>
DDRB_SDQS1# <7>
DDRB_SDQ[23..16] <7>

DDRB_SDQS2 <7>
DDRB_SDQS2# <7>
DDRB_SDQ[31..24] <7>

DDRB_SDQS3 <7>
DDRB_SDQS3# <7>
DDRB_SDQ[39..32] <7>

DDRB_SDQS4 <7>
DDRB_SDQS4# <7>
DDRB_SDQ[47..40] <7>

DDRB_SDQS5 <7>
DDRB_SDQS5# <7>
DDRB_SDQ[55..48] <7>

DDRB_SDQS6 <7>
DDRB_SDQS6# <7>

DDRB_SDQ[63..56] <7>

DDRB_SDQS7 <7>
DDRB_SDQS7# <7>

Follow CRB design

+1.2V

RD243

1K_0402_1%

RD251

1K_0402_1%

1 2

CD84 4.7U_0402_6.3V6M

1 2

15mil

1

2D@

2

+VREFB_CA

CD80 0.1U_0201_10V6K

CD76 0.1U_0201_10V6K

CD87 1000P_0402_50V7K

2

2

1

1

1

2

Place near to SO-DIMM connector.

+1.2V +1.2V

JDIMM2B

RESERVE

111

VDD1

112
117
118
123
124
129
130

+3VS

135
136

255

164

1
2
5
6

9
10
14
15
18
19
22
23
26
27
30
31
35
36
39
40
43
44
47
48
51
52
56
57
60
61
64
65
68
69
72
73
77
78
81
82
85
86
89
90
93
94
98

262

Layout Note:
Place near JDIMM2.258

VDD11

VDD2

VDD12

VDD3

VDD13

VDD4

VDD14

VDD5

VDD15

VDD6

VDD16

VDD7

VDD17

VDD8

VDD18

VDD9

VDD19

VDD10

VDDSPD

VTT

VREFCA

VPP1
VPP2

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

GND

LOTES_ADDR0070-P009A

CONN@

GND

141
142
147
148
153
154
159
160

+0.6VS

163

258

257
259

99
102
103
106
107
167
168
171
172
175
176
180
181
184
185
188
189
192
193
196
197
201
202
205
206
209
210
213
214
217
218
222
223
226
227
230
231
234
235
238
239
243
244
247
248
251
252

261

+2.5V

CD89 1U_0402_6.3V6K

1

2

CRB use 1uF x1

CRB use 4.7uF x1,0.1uF x1

Layout Note:
Place near JDIMM2.257,259

CRB use 0.1uF x2,180pF x1

4 4

10U_0603_6.3V6M

1

2

+2.5V

1U_0402_6.3V6K

10U_0603_6.3V6M

CD79

CD75

CD83

1

1

2

2

A

Layout Note:
Place near JDIMM2.255

CRB use 1uF x1

+3VS

1U_0402_6.3V6K

CD95

1

2

1

2

Security Classific ation

Security Classific ation

Security Classific ation

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PR OPERT Y OF C OMPAL EL ECTRO NICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PR OPERT Y OF C OMPAL EL ECTRO NICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PR OPERT Y OF C OMPAL EL ECTRO NICS, INC. AND CO NTAINS CONFIDENTIAL
AND T RADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D

AND T RADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D

AND T RADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISC LOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISC LOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISC LOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2017/04/18 2019/04/18

2017/04/18 2019/04/18

2017/04/18 2019/04/18

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

+0.6VS

10U_0603_6.3V6M

10U_0603_6.3V6M

CD74

CD70

1

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

DDR4_SO-DIMM

DDR4_SO-DIMM

DDR4_SO-DIMM

C5V08/D5PR8_LA-E903PR1A

C5V08/D5PR8_LA-E903PR1A

C5V08/D5PR8_LA-E903PR1A

1U_0402_6.3V6K

1U_0402_6.3V6K

CD72

CD92

1

1

2

2

14 50Tuesday, May 02, 2017

14 50Tuesday, May 02, 2017

E

14 50Tuesday, May 02, 2017

1.A

1.A

1.A

5

4

3

2

1

PEG_HTX_C_GRX_P[0..7]<6>

D D

PEG_HTX_C_GRX_P0
PEG_HTX_C_GRX_N0

PEG_HTX_C_GRX_P1 PEG_HTX_GRX_P1
PEG_HTX_C_GRX_N1

PEG_HTX_C_GRX_P2
PEG_HTX_C_GRX_N2

PEG_HTX_C_GRX_P3
PEG_HTX_C_GRX_N3 PEG_HTX_GRX_N3

PEG_HTX_C_GRX_P4
PEG_HTX_C_GRX_N4

PEG_HTX_C_GRX_P5
PEG_HTX_C_GRX_N5

PEG_HTX_C_GRX_P6
PEG_HTX_C_GRX_N6

PEG_HTX_C_GRX_P7
PEG_HTX_C_GRX_N7

C C

PEG_HTX_C_GRX_N[0..7]<6>

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

CV312 0.22U_0402_16V7KDIS@
CV306 0.22U_0402_16V7KDIS@

CV308 0.22U_0402_16V7KDIS@
CV305 0.22U_0402_16V7KDIS@

CV307 0.22U_0402_16V7KDIS@
CV309 0.22U_0402_16V7KDIS@

CV313 0.22U_0402_16V7KDIS@
CV304 0.22U_0402_16V7KDIS@

CV2710 0.22U_0402_16V7KT1DIS@
CV2707 0.22U_0402_16V7KT1DIS@

CV2711 0.22U_0402_16V7KT1DIS@
CV2709 0.22U_0402_16V7KT1DIS@

CV2717 0.22U_0402_16V7KT1DIS@
CV2714 0.22U_0402_16V7KT1DIS@

CV2704 0.22U_0402_16V7KT1DIS@
CV2706 0.22U_0402_16V7KT1DIS@

CLK_PEG_VGA<10>
CLK_PEG_VGA#<10>

PEG_HTX_C_GRX_P[0..7]

PEG_HTX_C_GRX_N[0..7]

PEG_HTX_GRX_P0
PEG_HTX_GRX_N0

PEG_HTX_GRX_N1

PEG_HTX_GRX_P2
PEG_HTX_GRX_N2

PEG_HTX_GRX_P3

PEG_HTX_GRX_P4
PEG_HTX_GRX_N4

PEG_HTX_GRX_P5
PEG_HTX_GRX_N5

PEG_HTX_GRX_P6
PEG_HTX_GRX_N6

PEG_HTX_GRX_P7
PEG_HTX_GRX_N7

CLK_PEG_VGA
CLK_PEG_VGA#

UV1B

@

AT41
AT40

AR41
AR40

AP41
AP40

AM41
AM40

AL41
AL40

AK41
AK40

AJ41
AJ40

AH41
AH40

AV33
AU33

symbol2

PCIE_RX0P
PCIE_RX0N

PCIE_RX1P
PCIE_RX1N

PCIE_RX2P
PCIE_RX2N

PCIE_RX3P
PCIE_RX3N

PCIE_RX4P
PCIE_RX4N

PCIE_RX5P
PCIE_RX5N

PCIE_RX6P
PCIE_RX6N

PCIE_RX7P
PCIE_RX7N

PCIE_REFCLKP
PCIE_REFCLKN

REV 0.91

2160896088A1R16M_FCBGA769P-NH

PCIE_TX0P

PCIE_TX0N

PCIE_TX1P

PCIE_TX1N

PCIE_TX2P

PCIE_TX2N

PCIE_TX3P

PCIE_TX3N

PCIE_TX4P

PCIE_TX4N

PCIE_TX5P

PCIE_TX5N

PCIE_TX6P

PCIE_TX6N

PCIE_TX7P

PCIE_TX7N

PERSTB

PX_EN

PCIE_ZVSS

PEG_GTX_C_HRX_P[0..7]<6>

PEG_GTX_C_HRX_N[0..7]<6>

PEG_GTX_HRX_P0

AV35

PEG_GTX_HRX_N0

AU35

PEG_GTX_HRX_P1

AU38

PEG_GTX_HRX_N1

AU39

PEG_GTX_HRX_P2

AR37

PEG_GTX_HRX_N2

AR38

PEG_GTX_HRX_P3

AN37

PEG_GTX_HRX_N3

AN38

PEG_GTX_HRX_P4

AL37

PEG_GTX_HRX_N4

AL38

PEG_GTX_HRX_P5

AJ37

PEG_GTX_HRX_N5

AJ38

PEG_GTX_HRX_P6

AG37

PEG_GTX_HRX_N6

AG38

PEG_GTX_HRX_P7

AE37

PEG_GTX_HRX_N7

AE38

PLT_RST_VGA#

AV41

PX_EN

AC41

AU41

1

@

For BACO mode(AMD PowerXpress) use, NC if not use

RV371

DIS@

200_0402_1%

1 2

T218

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

PEG_GTX_C_HRX_P[0..7]

PEG_GTX_C_HRX_N[0..7]

CV1 0.22U_0402_16V7KDIS@
CV2 0.22U_0402_16V7KDIS@

CV3 0.22U_0402_16V7KDIS@
CV4 0.22U_0402_16V7KDIS@

CV5 0.22U_0402_16V7KDIS@
CV6 0.22U_0402_16V7KDIS@

CV7 0.22U_0402_16V7KDIS@
CV8 0.22U_0402_16V7KDIS@

CV2715 0.22U_0402_16V7KT1DIS@
CV2708 0.22U_0402_16V7KT1DIS@

CV2713 0.22U_0402_16V7KT1DIS@
CV2703 0.22U_0402_16V7KT1DIS@

CV2705 0.22U_0402_16V7KT1DIS@
CV2712 0.22U_0402_16V7KT1DIS@

CV2716 0.22U_0402_16V7KT1DIS@
CV2702 0.22U_0402_16V7KT1DIS@

PEG_GTX_C_HRX_P0
PEG_GTX_C_HRX_N0

PEG_GTX_C_HRX_P1
PEG_GTX_C_HRX_N1

PEG_GTX_C_HRX_P2
PEG_GTX_C_HRX_N2

PEG_GTX_C_HRX_P3
PEG_GTX_C_HRX_N3

PEG_GTX_C_HRX_P4
PEG_GTX_C_HRX_N4

PEG_GTX_C_HRX_P5
PEG_GTX_C_HRX_N5

PEG_GTX_C_HRX_P6
PEG_GTX_C_HRX_N6

PEG_GTX_C_HRX_P7
PEG_GTX_C_HRX_N7

B B

APU_PCIE_RST#<9,28,29,30>

PE_GPIO0<9>

12

RV370

2.2K_0402_5%

DIS@

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGIN EERING DRAWING IS THE PROPRI ETARY PRO PERTY OF C OMPAL ELE CTRONI CS, INC . A ND CONTAI NS CONFIDENTIAL

THIS SHEET OF ENGIN EERING DRAWING IS THE PROPRI ETARY PRO PERTY OF C OMPAL ELE CTRONI CS, INC . A ND CONTAI NS CONFIDENTIAL

THIS SHEET OF ENGIN EERING DRAWING IS THE PROPRI ETARY PRO PERTY OF C OMPAL ELE CTRONI CS, INC . A ND CONTAI NS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

+3VSDGPU

UV2
MC74VHC1G08DFT2G_SC70-5

5

DIS@

1

P

IN1

O

2

IN2

G

3

2017/04/18 2019/04/18

2017/04/18 2019/04/18

2017/04/18 2019/04/18

3

4

PLT_RST_VGA#

12

RV4
100K_0402_5%

DIS@

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

R17M-P1-50/70_(1/9)_PCIE

R17M-P1-50/70_(1/9)_PCIE

R17M-P1-50/70_(1/9)_PCIE

C5V08/D5PR8_LA-E903PR1A

C5V08/D5PR8_LA-E903PR1A

C5V08/D5PR8_LA-E903PR1A

15 50Tuesday, May 02, 2017

15 50Tuesday, May 02, 2017

15 50Tuesday, May 02, 2017

1

1.A

1.A

1.A